pima
1409bad40b
- Fixed indexed task notifications for INT and DMAf for both sensors - Fixed the INT debugger startup freeze (added != NULL check in callbacks) - Fixed DMA notifications not being read properly/too early - Changed IMU INT configure/enable function as one - Added proper DMA checking in IMU calibration
74152 lines
2.7 MiB
Plaintext
74152 lines
2.7 MiB
Plaintext
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Trinity_Devboard_V2.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000013c 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 0001dcb8 08000140 08000140 00001140 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000c58 0801ddf8 0801ddf8 0001edf8 2**3
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM 00000008 0801ea50 0801ea50 0001fa50 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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4 .init_array 00000004 0801ea58 0801ea58 0001fa58 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .fini_array 00000004 0801ea5c 0801ea5c 0001fa5c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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6 .data 000002d0 20000008 0801ea60 00020008 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 SYSTEM_DRIVER_CONTEXT 00000011 200002d8 0801ed30 000202d8 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .bss 000139fc 200002ec 0801ed41 000202ec 2**2
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ALLOC
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9 ._user_heap_stack 00000600 20013ce8 0801ed41 00020ce8 2**0
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ALLOC
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10 .ARM.attributes 00000030 00000000 00000000 0002194a 2**0
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CONTENTS, READONLY
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11 MAPPING_TABLE 00000028 20030000 20030000 00022000 2**2
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ALLOC
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12 MB_MEM1 000000b0 20030028 20030028 00022000 2**2
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ALLOC
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13 .MB_MEM2 00000872 200300d8 0801ed41 000210d8 2**2
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CONTENTS, ALLOC, LOAD, DATA
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14 .debug_info 0003ba51 00000000 00000000 0002197a 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_abbrev 00008770 00000000 00000000 0005d3cb 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_aranges 00003678 00000000 00000000 00065b40 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_rnglists 0000297a 00000000 00000000 000691b8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_macro 00032a00 00000000 00000000 0006bb32 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .debug_line 0003c367 00000000 00000000 0009e532 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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20 .debug_str 00112f33 00000000 00000000 000da899 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .comment 00000043 00000000 00000000 001ed7cc 2**0
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CONTENTS, READONLY
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22 .debug_frame 0000ee28 00000000 00000000 001ed810 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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23 .debug_line_str 00000061 00000000 00000000 001fc638 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000140 <__do_global_dtors_aux>:
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8000140: b510 push {r4, lr}
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8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>)
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8000144: 7823 ldrb r3, [r4, #0]
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8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16>
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8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>)
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800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12>
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800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>)
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800014e: f3af 8000 nop.w
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8000152: 2301 movs r3, #1
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8000154: 7023 strb r3, [r4, #0]
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8000156: bd10 pop {r4, pc}
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8000158: 200002ec .word 0x200002ec
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800015c: 00000000 .word 0x00000000
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8000160: 0801dde0 .word 0x0801dde0
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08000164 <frame_dummy>:
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8000164: b508 push {r3, lr}
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8000166: 4b03 ldr r3, [pc, #12] @ (8000174 <frame_dummy+0x10>)
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8000168: b11b cbz r3, 8000172 <frame_dummy+0xe>
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800016a: 4903 ldr r1, [pc, #12] @ (8000178 <frame_dummy+0x14>)
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800016c: 4803 ldr r0, [pc, #12] @ (800017c <frame_dummy+0x18>)
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800016e: f3af 8000 nop.w
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8000172: bd08 pop {r3, pc}
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8000174: 00000000 .word 0x00000000
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8000178: 200002f0 .word 0x200002f0
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800017c: 0801dde0 .word 0x0801dde0
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08000180 <memchr>:
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8000180: f001 01ff and.w r1, r1, #255 @ 0xff
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8000184: 2a10 cmp r2, #16
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8000186: db2b blt.n 80001e0 <memchr+0x60>
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8000188: f010 0f07 tst.w r0, #7
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800018c: d008 beq.n 80001a0 <memchr+0x20>
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800018e: f810 3b01 ldrb.w r3, [r0], #1
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8000192: 3a01 subs r2, #1
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8000194: 428b cmp r3, r1
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8000196: d02d beq.n 80001f4 <memchr+0x74>
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8000198: f010 0f07 tst.w r0, #7
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800019c: b342 cbz r2, 80001f0 <memchr+0x70>
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800019e: d1f6 bne.n 800018e <memchr+0xe>
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80001a0: b4f0 push {r4, r5, r6, r7}
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80001a2: ea41 2101 orr.w r1, r1, r1, lsl #8
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80001a6: ea41 4101 orr.w r1, r1, r1, lsl #16
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80001aa: f022 0407 bic.w r4, r2, #7
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80001ae: f07f 0700 mvns.w r7, #0
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80001b2: 2300 movs r3, #0
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80001b4: e8f0 5602 ldrd r5, r6, [r0], #8
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80001b8: 3c08 subs r4, #8
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80001ba: ea85 0501 eor.w r5, r5, r1
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80001be: ea86 0601 eor.w r6, r6, r1
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80001c2: fa85 f547 uadd8 r5, r5, r7
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80001c6: faa3 f587 sel r5, r3, r7
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80001ca: fa86 f647 uadd8 r6, r6, r7
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80001ce: faa5 f687 sel r6, r5, r7
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80001d2: b98e cbnz r6, 80001f8 <memchr+0x78>
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80001d4: d1ee bne.n 80001b4 <memchr+0x34>
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80001d6: bcf0 pop {r4, r5, r6, r7}
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80001d8: f001 01ff and.w r1, r1, #255 @ 0xff
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80001dc: f002 0207 and.w r2, r2, #7
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80001e0: b132 cbz r2, 80001f0 <memchr+0x70>
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80001e2: f810 3b01 ldrb.w r3, [r0], #1
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80001e6: 3a01 subs r2, #1
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80001e8: ea83 0301 eor.w r3, r3, r1
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80001ec: b113 cbz r3, 80001f4 <memchr+0x74>
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80001ee: d1f8 bne.n 80001e2 <memchr+0x62>
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80001f0: 2000 movs r0, #0
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80001f2: 4770 bx lr
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80001f4: 3801 subs r0, #1
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80001f6: 4770 bx lr
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80001f8: 2d00 cmp r5, #0
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80001fa: bf06 itte eq
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80001fc: 4635 moveq r5, r6
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80001fe: 3803 subeq r0, #3
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8000200: 3807 subne r0, #7
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8000202: f015 0f01 tst.w r5, #1
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8000206: d107 bne.n 8000218 <memchr+0x98>
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8000208: 3001 adds r0, #1
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800020a: f415 7f80 tst.w r5, #256 @ 0x100
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800020e: bf02 ittt eq
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8000210: 3001 addeq r0, #1
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8000212: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
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8000216: 3001 addeq r0, #1
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8000218: bcf0 pop {r4, r5, r6, r7}
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800021a: 3801 subs r0, #1
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800021c: 4770 bx lr
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800021e: bf00 nop
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08000220 <strlen>:
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8000220: 4603 mov r3, r0
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8000222: f813 2b01 ldrb.w r2, [r3], #1
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8000226: 2a00 cmp r2, #0
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8000228: d1fb bne.n 8000222 <strlen+0x2>
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800022a: 1a18 subs r0, r3, r0
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800022c: 3801 subs r0, #1
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800022e: 4770 bx lr
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08000230 <__aeabi_drsub>:
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8000230: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
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8000234: e002 b.n 800023c <__adddf3>
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8000236: bf00 nop
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08000238 <__aeabi_dsub>:
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8000238: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
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0800023c <__adddf3>:
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800023c: b530 push {r4, r5, lr}
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800023e: ea4f 0441 mov.w r4, r1, lsl #1
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8000242: ea4f 0543 mov.w r5, r3, lsl #1
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8000246: ea94 0f05 teq r4, r5
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800024a: bf08 it eq
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800024c: ea90 0f02 teqeq r0, r2
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8000250: bf1f itttt ne
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8000252: ea54 0c00 orrsne.w ip, r4, r0
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8000256: ea55 0c02 orrsne.w ip, r5, r2
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800025a: ea7f 5c64 mvnsne.w ip, r4, asr #21
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800025e: ea7f 5c65 mvnsne.w ip, r5, asr #21
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8000262: f000 80e2 beq.w 800042a <__adddf3+0x1ee>
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8000266: ea4f 5454 mov.w r4, r4, lsr #21
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800026a: ebd4 5555 rsbs r5, r4, r5, lsr #21
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800026e: bfb8 it lt
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8000270: 426d neglt r5, r5
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8000272: dd0c ble.n 800028e <__adddf3+0x52>
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8000274: 442c add r4, r5
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8000276: ea80 0202 eor.w r2, r0, r2
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800027a: ea81 0303 eor.w r3, r1, r3
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800027e: ea82 0000 eor.w r0, r2, r0
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8000282: ea83 0101 eor.w r1, r3, r1
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8000286: ea80 0202 eor.w r2, r0, r2
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800028a: ea81 0303 eor.w r3, r1, r3
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800028e: 2d36 cmp r5, #54 @ 0x36
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8000290: bf88 it hi
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8000292: bd30 pophi {r4, r5, pc}
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8000294: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
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8000298: ea4f 3101 mov.w r1, r1, lsl #12
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800029c: f44f 1c80 mov.w ip, #1048576 @ 0x100000
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80002a0: ea4c 3111 orr.w r1, ip, r1, lsr #12
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80002a4: d002 beq.n 80002ac <__adddf3+0x70>
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80002a6: 4240 negs r0, r0
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80002a8: eb61 0141 sbc.w r1, r1, r1, lsl #1
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80002ac: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
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80002b0: ea4f 3303 mov.w r3, r3, lsl #12
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80002b4: ea4c 3313 orr.w r3, ip, r3, lsr #12
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80002b8: d002 beq.n 80002c0 <__adddf3+0x84>
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80002ba: 4252 negs r2, r2
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80002bc: eb63 0343 sbc.w r3, r3, r3, lsl #1
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80002c0: ea94 0f05 teq r4, r5
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80002c4: f000 80a7 beq.w 8000416 <__adddf3+0x1da>
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80002c8: f1a4 0401 sub.w r4, r4, #1
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80002cc: f1d5 0e20 rsbs lr, r5, #32
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80002d0: db0d blt.n 80002ee <__adddf3+0xb2>
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80002d2: fa02 fc0e lsl.w ip, r2, lr
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80002d6: fa22 f205 lsr.w r2, r2, r5
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80002da: 1880 adds r0, r0, r2
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80002dc: f141 0100 adc.w r1, r1, #0
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80002e0: fa03 f20e lsl.w r2, r3, lr
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80002e4: 1880 adds r0, r0, r2
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80002e6: fa43 f305 asr.w r3, r3, r5
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80002ea: 4159 adcs r1, r3
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80002ec: e00e b.n 800030c <__adddf3+0xd0>
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80002ee: f1a5 0520 sub.w r5, r5, #32
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80002f2: f10e 0e20 add.w lr, lr, #32
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80002f6: 2a01 cmp r2, #1
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80002f8: fa03 fc0e lsl.w ip, r3, lr
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80002fc: bf28 it cs
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80002fe: f04c 0c02 orrcs.w ip, ip, #2
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8000302: fa43 f305 asr.w r3, r3, r5
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8000306: 18c0 adds r0, r0, r3
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8000308: eb51 71e3 adcs.w r1, r1, r3, asr #31
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800030c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
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8000310: d507 bpl.n 8000322 <__adddf3+0xe6>
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8000312: f04f 0e00 mov.w lr, #0
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8000316: f1dc 0c00 rsbs ip, ip, #0
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800031a: eb7e 0000 sbcs.w r0, lr, r0
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800031e: eb6e 0101 sbc.w r1, lr, r1
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8000322: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
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8000326: d31b bcc.n 8000360 <__adddf3+0x124>
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8000328: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
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800032c: d30c bcc.n 8000348 <__adddf3+0x10c>
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800032e: 0849 lsrs r1, r1, #1
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8000330: ea5f 0030 movs.w r0, r0, rrx
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8000334: ea4f 0c3c mov.w ip, ip, rrx
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8000338: f104 0401 add.w r4, r4, #1
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800033c: ea4f 5244 mov.w r2, r4, lsl #21
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8000340: f512 0f80 cmn.w r2, #4194304 @ 0x400000
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8000344: f080 809a bcs.w 800047c <__adddf3+0x240>
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8000348: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
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800034c: bf08 it eq
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800034e: ea5f 0c50 movseq.w ip, r0, lsr #1
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8000352: f150 0000 adcs.w r0, r0, #0
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8000356: eb41 5104 adc.w r1, r1, r4, lsl #20
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800035a: ea41 0105 orr.w r1, r1, r5
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800035e: bd30 pop {r4, r5, pc}
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8000360: ea5f 0c4c movs.w ip, ip, lsl #1
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8000364: 4140 adcs r0, r0
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8000366: eb41 0101 adc.w r1, r1, r1
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800036a: 3c01 subs r4, #1
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800036c: bf28 it cs
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800036e: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
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8000372: d2e9 bcs.n 8000348 <__adddf3+0x10c>
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8000374: f091 0f00 teq r1, #0
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8000378: bf04 itt eq
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800037a: 4601 moveq r1, r0
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800037c: 2000 moveq r0, #0
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800037e: fab1 f381 clz r3, r1
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8000382: bf08 it eq
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8000384: 3320 addeq r3, #32
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8000386: f1a3 030b sub.w r3, r3, #11
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800038a: f1b3 0220 subs.w r2, r3, #32
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800038e: da0c bge.n 80003aa <__adddf3+0x16e>
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8000390: 320c adds r2, #12
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8000392: dd08 ble.n 80003a6 <__adddf3+0x16a>
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8000394: f102 0c14 add.w ip, r2, #20
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8000398: f1c2 020c rsb r2, r2, #12
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800039c: fa01 f00c lsl.w r0, r1, ip
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80003a0: fa21 f102 lsr.w r1, r1, r2
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80003a4: e00c b.n 80003c0 <__adddf3+0x184>
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80003a6: f102 0214 add.w r2, r2, #20
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80003aa: bfd8 it le
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80003ac: f1c2 0c20 rsble ip, r2, #32
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80003b0: fa01 f102 lsl.w r1, r1, r2
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80003b4: fa20 fc0c lsr.w ip, r0, ip
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80003b8: bfdc itt le
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80003ba: ea41 010c orrle.w r1, r1, ip
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80003be: 4090 lslle r0, r2
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80003c0: 1ae4 subs r4, r4, r3
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80003c2: bfa2 ittt ge
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80003c4: eb01 5104 addge.w r1, r1, r4, lsl #20
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80003c8: 4329 orrge r1, r5
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80003ca: bd30 popge {r4, r5, pc}
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80003cc: ea6f 0404 mvn.w r4, r4
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80003d0: 3c1f subs r4, #31
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80003d2: da1c bge.n 800040e <__adddf3+0x1d2>
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80003d4: 340c adds r4, #12
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80003d6: dc0e bgt.n 80003f6 <__adddf3+0x1ba>
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80003d8: f104 0414 add.w r4, r4, #20
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80003dc: f1c4 0220 rsb r2, r4, #32
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80003e0: fa20 f004 lsr.w r0, r0, r4
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80003e4: fa01 f302 lsl.w r3, r1, r2
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80003e8: ea40 0003 orr.w r0, r0, r3
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80003ec: fa21 f304 lsr.w r3, r1, r4
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80003f0: ea45 0103 orr.w r1, r5, r3
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80003f4: bd30 pop {r4, r5, pc}
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80003f6: f1c4 040c rsb r4, r4, #12
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80003fa: f1c4 0220 rsb r2, r4, #32
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80003fe: fa20 f002 lsr.w r0, r0, r2
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8000402: fa01 f304 lsl.w r3, r1, r4
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8000406: ea40 0003 orr.w r0, r0, r3
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800040a: 4629 mov r1, r5
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800040c: bd30 pop {r4, r5, pc}
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800040e: fa21 f004 lsr.w r0, r1, r4
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8000412: 4629 mov r1, r5
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8000414: bd30 pop {r4, r5, pc}
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8000416: f094 0f00 teq r4, #0
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800041a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
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800041e: bf06 itte eq
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8000420: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
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8000424: 3401 addeq r4, #1
|
|
8000426: 3d01 subne r5, #1
|
|
8000428: e74e b.n 80002c8 <__adddf3+0x8c>
|
|
800042a: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
800042e: bf18 it ne
|
|
8000430: ea7f 5c65 mvnsne.w ip, r5, asr #21
|
|
8000434: d029 beq.n 800048a <__adddf3+0x24e>
|
|
8000436: ea94 0f05 teq r4, r5
|
|
800043a: bf08 it eq
|
|
800043c: ea90 0f02 teqeq r0, r2
|
|
8000440: d005 beq.n 800044e <__adddf3+0x212>
|
|
8000442: ea54 0c00 orrs.w ip, r4, r0
|
|
8000446: bf04 itt eq
|
|
8000448: 4619 moveq r1, r3
|
|
800044a: 4610 moveq r0, r2
|
|
800044c: bd30 pop {r4, r5, pc}
|
|
800044e: ea91 0f03 teq r1, r3
|
|
8000452: bf1e ittt ne
|
|
8000454: 2100 movne r1, #0
|
|
8000456: 2000 movne r0, #0
|
|
8000458: bd30 popne {r4, r5, pc}
|
|
800045a: ea5f 5c54 movs.w ip, r4, lsr #21
|
|
800045e: d105 bne.n 800046c <__adddf3+0x230>
|
|
8000460: 0040 lsls r0, r0, #1
|
|
8000462: 4149 adcs r1, r1
|
|
8000464: bf28 it cs
|
|
8000466: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
|
|
800046a: bd30 pop {r4, r5, pc}
|
|
800046c: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
|
|
8000470: bf3c itt cc
|
|
8000472: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
|
|
8000476: bd30 popcc {r4, r5, pc}
|
|
8000478: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
800047c: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
|
|
8000480: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
8000484: f04f 0000 mov.w r0, #0
|
|
8000488: bd30 pop {r4, r5, pc}
|
|
800048a: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
800048e: bf1a itte ne
|
|
8000490: 4619 movne r1, r3
|
|
8000492: 4610 movne r0, r2
|
|
8000494: ea7f 5c65 mvnseq.w ip, r5, asr #21
|
|
8000498: bf1c itt ne
|
|
800049a: 460b movne r3, r1
|
|
800049c: 4602 movne r2, r0
|
|
800049e: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80004a2: bf06 itte eq
|
|
80004a4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
|
|
80004a8: ea91 0f03 teqeq r1, r3
|
|
80004ac: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
|
|
80004b0: bd30 pop {r4, r5, pc}
|
|
80004b2: bf00 nop
|
|
|
|
080004b4 <__aeabi_ui2d>:
|
|
80004b4: f090 0f00 teq r0, #0
|
|
80004b8: bf04 itt eq
|
|
80004ba: 2100 moveq r1, #0
|
|
80004bc: 4770 bxeq lr
|
|
80004be: b530 push {r4, r5, lr}
|
|
80004c0: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80004c4: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80004c8: f04f 0500 mov.w r5, #0
|
|
80004cc: f04f 0100 mov.w r1, #0
|
|
80004d0: e750 b.n 8000374 <__adddf3+0x138>
|
|
80004d2: bf00 nop
|
|
|
|
080004d4 <__aeabi_i2d>:
|
|
80004d4: f090 0f00 teq r0, #0
|
|
80004d8: bf04 itt eq
|
|
80004da: 2100 moveq r1, #0
|
|
80004dc: 4770 bxeq lr
|
|
80004de: b530 push {r4, r5, lr}
|
|
80004e0: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80004e4: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80004e8: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
|
|
80004ec: bf48 it mi
|
|
80004ee: 4240 negmi r0, r0
|
|
80004f0: f04f 0100 mov.w r1, #0
|
|
80004f4: e73e b.n 8000374 <__adddf3+0x138>
|
|
80004f6: bf00 nop
|
|
|
|
080004f8 <__aeabi_f2d>:
|
|
80004f8: 0042 lsls r2, r0, #1
|
|
80004fa: ea4f 01e2 mov.w r1, r2, asr #3
|
|
80004fe: ea4f 0131 mov.w r1, r1, rrx
|
|
8000502: ea4f 7002 mov.w r0, r2, lsl #28
|
|
8000506: bf1f itttt ne
|
|
8000508: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
|
|
800050c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
|
|
8000510: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
|
|
8000514: 4770 bxne lr
|
|
8000516: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
|
|
800051a: bf08 it eq
|
|
800051c: 4770 bxeq lr
|
|
800051e: f093 4f7f teq r3, #4278190080 @ 0xff000000
|
|
8000522: bf04 itt eq
|
|
8000524: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
|
|
8000528: 4770 bxeq lr
|
|
800052a: b530 push {r4, r5, lr}
|
|
800052c: f44f 7460 mov.w r4, #896 @ 0x380
|
|
8000530: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
8000534: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000538: e71c b.n 8000374 <__adddf3+0x138>
|
|
800053a: bf00 nop
|
|
|
|
0800053c <__aeabi_ul2d>:
|
|
800053c: ea50 0201 orrs.w r2, r0, r1
|
|
8000540: bf08 it eq
|
|
8000542: 4770 bxeq lr
|
|
8000544: b530 push {r4, r5, lr}
|
|
8000546: f04f 0500 mov.w r5, #0
|
|
800054a: e00a b.n 8000562 <__aeabi_l2d+0x16>
|
|
|
|
0800054c <__aeabi_l2d>:
|
|
800054c: ea50 0201 orrs.w r2, r0, r1
|
|
8000550: bf08 it eq
|
|
8000552: 4770 bxeq lr
|
|
8000554: b530 push {r4, r5, lr}
|
|
8000556: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
|
|
800055a: d502 bpl.n 8000562 <__aeabi_l2d+0x16>
|
|
800055c: 4240 negs r0, r0
|
|
800055e: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
8000562: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000566: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
800056a: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
800056e: f43f aed8 beq.w 8000322 <__adddf3+0xe6>
|
|
8000572: f04f 0203 mov.w r2, #3
|
|
8000576: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
800057a: bf18 it ne
|
|
800057c: 3203 addne r2, #3
|
|
800057e: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
8000582: bf18 it ne
|
|
8000584: 3203 addne r2, #3
|
|
8000586: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
800058a: f1c2 0320 rsb r3, r2, #32
|
|
800058e: fa00 fc03 lsl.w ip, r0, r3
|
|
8000592: fa20 f002 lsr.w r0, r0, r2
|
|
8000596: fa01 fe03 lsl.w lr, r1, r3
|
|
800059a: ea40 000e orr.w r0, r0, lr
|
|
800059e: fa21 f102 lsr.w r1, r1, r2
|
|
80005a2: 4414 add r4, r2
|
|
80005a4: e6bd b.n 8000322 <__adddf3+0xe6>
|
|
80005a6: bf00 nop
|
|
|
|
080005a8 <__aeabi_dmul>:
|
|
80005a8: b570 push {r4, r5, r6, lr}
|
|
80005aa: f04f 0cff mov.w ip, #255 @ 0xff
|
|
80005ae: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
80005b2: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
80005b6: bf1d ittte ne
|
|
80005b8: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
80005bc: ea94 0f0c teqne r4, ip
|
|
80005c0: ea95 0f0c teqne r5, ip
|
|
80005c4: f000 f8de bleq 8000784 <__aeabi_dmul+0x1dc>
|
|
80005c8: 442c add r4, r5
|
|
80005ca: ea81 0603 eor.w r6, r1, r3
|
|
80005ce: ea21 514c bic.w r1, r1, ip, lsl #21
|
|
80005d2: ea23 534c bic.w r3, r3, ip, lsl #21
|
|
80005d6: ea50 3501 orrs.w r5, r0, r1, lsl #12
|
|
80005da: bf18 it ne
|
|
80005dc: ea52 3503 orrsne.w r5, r2, r3, lsl #12
|
|
80005e0: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80005e4: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
80005e8: d038 beq.n 800065c <__aeabi_dmul+0xb4>
|
|
80005ea: fba0 ce02 umull ip, lr, r0, r2
|
|
80005ee: f04f 0500 mov.w r5, #0
|
|
80005f2: fbe1 e502 umlal lr, r5, r1, r2
|
|
80005f6: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
|
|
80005fa: fbe0 e503 umlal lr, r5, r0, r3
|
|
80005fe: f04f 0600 mov.w r6, #0
|
|
8000602: fbe1 5603 umlal r5, r6, r1, r3
|
|
8000606: f09c 0f00 teq ip, #0
|
|
800060a: bf18 it ne
|
|
800060c: f04e 0e01 orrne.w lr, lr, #1
|
|
8000610: f1a4 04ff sub.w r4, r4, #255 @ 0xff
|
|
8000614: f5b6 7f00 cmp.w r6, #512 @ 0x200
|
|
8000618: f564 7440 sbc.w r4, r4, #768 @ 0x300
|
|
800061c: d204 bcs.n 8000628 <__aeabi_dmul+0x80>
|
|
800061e: ea5f 0e4e movs.w lr, lr, lsl #1
|
|
8000622: 416d adcs r5, r5
|
|
8000624: eb46 0606 adc.w r6, r6, r6
|
|
8000628: ea42 21c6 orr.w r1, r2, r6, lsl #11
|
|
800062c: ea41 5155 orr.w r1, r1, r5, lsr #21
|
|
8000630: ea4f 20c5 mov.w r0, r5, lsl #11
|
|
8000634: ea40 505e orr.w r0, r0, lr, lsr #21
|
|
8000638: ea4f 2ece mov.w lr, lr, lsl #11
|
|
800063c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
8000640: bf88 it hi
|
|
8000642: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000646: d81e bhi.n 8000686 <__aeabi_dmul+0xde>
|
|
8000648: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
|
|
800064c: bf08 it eq
|
|
800064e: ea5f 0e50 movseq.w lr, r0, lsr #1
|
|
8000652: f150 0000 adcs.w r0, r0, #0
|
|
8000656: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
800065a: bd70 pop {r4, r5, r6, pc}
|
|
800065c: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
|
|
8000660: ea46 0101 orr.w r1, r6, r1
|
|
8000664: ea40 0002 orr.w r0, r0, r2
|
|
8000668: ea81 0103 eor.w r1, r1, r3
|
|
800066c: ebb4 045c subs.w r4, r4, ip, lsr #1
|
|
8000670: bfc2 ittt gt
|
|
8000672: ebd4 050c rsbsgt r5, r4, ip
|
|
8000676: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
800067a: bd70 popgt {r4, r5, r6, pc}
|
|
800067c: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
8000680: f04f 0e00 mov.w lr, #0
|
|
8000684: 3c01 subs r4, #1
|
|
8000686: f300 80ab bgt.w 80007e0 <__aeabi_dmul+0x238>
|
|
800068a: f114 0f36 cmn.w r4, #54 @ 0x36
|
|
800068e: bfde ittt le
|
|
8000690: 2000 movle r0, #0
|
|
8000692: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
|
|
8000696: bd70 pople {r4, r5, r6, pc}
|
|
8000698: f1c4 0400 rsb r4, r4, #0
|
|
800069c: 3c20 subs r4, #32
|
|
800069e: da35 bge.n 800070c <__aeabi_dmul+0x164>
|
|
80006a0: 340c adds r4, #12
|
|
80006a2: dc1b bgt.n 80006dc <__aeabi_dmul+0x134>
|
|
80006a4: f104 0414 add.w r4, r4, #20
|
|
80006a8: f1c4 0520 rsb r5, r4, #32
|
|
80006ac: fa00 f305 lsl.w r3, r0, r5
|
|
80006b0: fa20 f004 lsr.w r0, r0, r4
|
|
80006b4: fa01 f205 lsl.w r2, r1, r5
|
|
80006b8: ea40 0002 orr.w r0, r0, r2
|
|
80006bc: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
|
|
80006c0: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
80006c4: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
80006c8: fa21 f604 lsr.w r6, r1, r4
|
|
80006cc: eb42 0106 adc.w r1, r2, r6
|
|
80006d0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
80006d4: bf08 it eq
|
|
80006d6: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
80006da: bd70 pop {r4, r5, r6, pc}
|
|
80006dc: f1c4 040c rsb r4, r4, #12
|
|
80006e0: f1c4 0520 rsb r5, r4, #32
|
|
80006e4: fa00 f304 lsl.w r3, r0, r4
|
|
80006e8: fa20 f005 lsr.w r0, r0, r5
|
|
80006ec: fa01 f204 lsl.w r2, r1, r4
|
|
80006f0: ea40 0002 orr.w r0, r0, r2
|
|
80006f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
80006f8: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
80006fc: f141 0100 adc.w r1, r1, #0
|
|
8000700: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000704: bf08 it eq
|
|
8000706: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800070a: bd70 pop {r4, r5, r6, pc}
|
|
800070c: f1c4 0520 rsb r5, r4, #32
|
|
8000710: fa00 f205 lsl.w r2, r0, r5
|
|
8000714: ea4e 0e02 orr.w lr, lr, r2
|
|
8000718: fa20 f304 lsr.w r3, r0, r4
|
|
800071c: fa01 f205 lsl.w r2, r1, r5
|
|
8000720: ea43 0302 orr.w r3, r3, r2
|
|
8000724: fa21 f004 lsr.w r0, r1, r4
|
|
8000728: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
800072c: fa21 f204 lsr.w r2, r1, r4
|
|
8000730: ea20 0002 bic.w r0, r0, r2
|
|
8000734: eb00 70d3 add.w r0, r0, r3, lsr #31
|
|
8000738: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
800073c: bf08 it eq
|
|
800073e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
8000742: bd70 pop {r4, r5, r6, pc}
|
|
8000744: f094 0f00 teq r4, #0
|
|
8000748: d10f bne.n 800076a <__aeabi_dmul+0x1c2>
|
|
800074a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
|
|
800074e: 0040 lsls r0, r0, #1
|
|
8000750: eb41 0101 adc.w r1, r1, r1
|
|
8000754: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000758: bf08 it eq
|
|
800075a: 3c01 subeq r4, #1
|
|
800075c: d0f7 beq.n 800074e <__aeabi_dmul+0x1a6>
|
|
800075e: ea41 0106 orr.w r1, r1, r6
|
|
8000762: f095 0f00 teq r5, #0
|
|
8000766: bf18 it ne
|
|
8000768: 4770 bxne lr
|
|
800076a: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
|
|
800076e: 0052 lsls r2, r2, #1
|
|
8000770: eb43 0303 adc.w r3, r3, r3
|
|
8000774: f413 1f80 tst.w r3, #1048576 @ 0x100000
|
|
8000778: bf08 it eq
|
|
800077a: 3d01 subeq r5, #1
|
|
800077c: d0f7 beq.n 800076e <__aeabi_dmul+0x1c6>
|
|
800077e: ea43 0306 orr.w r3, r3, r6
|
|
8000782: 4770 bx lr
|
|
8000784: ea94 0f0c teq r4, ip
|
|
8000788: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
800078c: bf18 it ne
|
|
800078e: ea95 0f0c teqne r5, ip
|
|
8000792: d00c beq.n 80007ae <__aeabi_dmul+0x206>
|
|
8000794: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000798: bf18 it ne
|
|
800079a: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
800079e: d1d1 bne.n 8000744 <__aeabi_dmul+0x19c>
|
|
80007a0: ea81 0103 eor.w r1, r1, r3
|
|
80007a4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
80007a8: f04f 0000 mov.w r0, #0
|
|
80007ac: bd70 pop {r4, r5, r6, pc}
|
|
80007ae: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
80007b2: bf06 itte eq
|
|
80007b4: 4610 moveq r0, r2
|
|
80007b6: 4619 moveq r1, r3
|
|
80007b8: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
80007bc: d019 beq.n 80007f2 <__aeabi_dmul+0x24a>
|
|
80007be: ea94 0f0c teq r4, ip
|
|
80007c2: d102 bne.n 80007ca <__aeabi_dmul+0x222>
|
|
80007c4: ea50 3601 orrs.w r6, r0, r1, lsl #12
|
|
80007c8: d113 bne.n 80007f2 <__aeabi_dmul+0x24a>
|
|
80007ca: ea95 0f0c teq r5, ip
|
|
80007ce: d105 bne.n 80007dc <__aeabi_dmul+0x234>
|
|
80007d0: ea52 3603 orrs.w r6, r2, r3, lsl #12
|
|
80007d4: bf1c itt ne
|
|
80007d6: 4610 movne r0, r2
|
|
80007d8: 4619 movne r1, r3
|
|
80007da: d10a bne.n 80007f2 <__aeabi_dmul+0x24a>
|
|
80007dc: ea81 0103 eor.w r1, r1, r3
|
|
80007e0: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
80007e4: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
80007e8: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
80007ec: f04f 0000 mov.w r0, #0
|
|
80007f0: bd70 pop {r4, r5, r6, pc}
|
|
80007f2: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
80007f6: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
|
|
80007fa: bd70 pop {r4, r5, r6, pc}
|
|
|
|
080007fc <__aeabi_ddiv>:
|
|
80007fc: b570 push {r4, r5, r6, lr}
|
|
80007fe: f04f 0cff mov.w ip, #255 @ 0xff
|
|
8000802: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000806: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
800080a: bf1d ittte ne
|
|
800080c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
8000810: ea94 0f0c teqne r4, ip
|
|
8000814: ea95 0f0c teqne r5, ip
|
|
8000818: f000 f8a7 bleq 800096a <__aeabi_ddiv+0x16e>
|
|
800081c: eba4 0405 sub.w r4, r4, r5
|
|
8000820: ea81 0e03 eor.w lr, r1, r3
|
|
8000824: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
8000828: ea4f 3101 mov.w r1, r1, lsl #12
|
|
800082c: f000 8088 beq.w 8000940 <__aeabi_ddiv+0x144>
|
|
8000830: ea4f 3303 mov.w r3, r3, lsl #12
|
|
8000834: f04f 5580 mov.w r5, #268435456 @ 0x10000000
|
|
8000838: ea45 1313 orr.w r3, r5, r3, lsr #4
|
|
800083c: ea43 6312 orr.w r3, r3, r2, lsr #24
|
|
8000840: ea4f 2202 mov.w r2, r2, lsl #8
|
|
8000844: ea45 1511 orr.w r5, r5, r1, lsr #4
|
|
8000848: ea45 6510 orr.w r5, r5, r0, lsr #24
|
|
800084c: ea4f 2600 mov.w r6, r0, lsl #8
|
|
8000850: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
|
|
8000854: 429d cmp r5, r3
|
|
8000856: bf08 it eq
|
|
8000858: 4296 cmpeq r6, r2
|
|
800085a: f144 04fd adc.w r4, r4, #253 @ 0xfd
|
|
800085e: f504 7440 add.w r4, r4, #768 @ 0x300
|
|
8000862: d202 bcs.n 800086a <__aeabi_ddiv+0x6e>
|
|
8000864: 085b lsrs r3, r3, #1
|
|
8000866: ea4f 0232 mov.w r2, r2, rrx
|
|
800086a: 1ab6 subs r6, r6, r2
|
|
800086c: eb65 0503 sbc.w r5, r5, r3
|
|
8000870: 085b lsrs r3, r3, #1
|
|
8000872: ea4f 0232 mov.w r2, r2, rrx
|
|
8000876: f44f 1080 mov.w r0, #1048576 @ 0x100000
|
|
800087a: f44f 2c00 mov.w ip, #524288 @ 0x80000
|
|
800087e: ebb6 0e02 subs.w lr, r6, r2
|
|
8000882: eb75 0e03 sbcs.w lr, r5, r3
|
|
8000886: bf22 ittt cs
|
|
8000888: 1ab6 subcs r6, r6, r2
|
|
800088a: 4675 movcs r5, lr
|
|
800088c: ea40 000c orrcs.w r0, r0, ip
|
|
8000890: 085b lsrs r3, r3, #1
|
|
8000892: ea4f 0232 mov.w r2, r2, rrx
|
|
8000896: ebb6 0e02 subs.w lr, r6, r2
|
|
800089a: eb75 0e03 sbcs.w lr, r5, r3
|
|
800089e: bf22 ittt cs
|
|
80008a0: 1ab6 subcs r6, r6, r2
|
|
80008a2: 4675 movcs r5, lr
|
|
80008a4: ea40 005c orrcs.w r0, r0, ip, lsr #1
|
|
80008a8: 085b lsrs r3, r3, #1
|
|
80008aa: ea4f 0232 mov.w r2, r2, rrx
|
|
80008ae: ebb6 0e02 subs.w lr, r6, r2
|
|
80008b2: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008b6: bf22 ittt cs
|
|
80008b8: 1ab6 subcs r6, r6, r2
|
|
80008ba: 4675 movcs r5, lr
|
|
80008bc: ea40 009c orrcs.w r0, r0, ip, lsr #2
|
|
80008c0: 085b lsrs r3, r3, #1
|
|
80008c2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008c6: ebb6 0e02 subs.w lr, r6, r2
|
|
80008ca: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008ce: bf22 ittt cs
|
|
80008d0: 1ab6 subcs r6, r6, r2
|
|
80008d2: 4675 movcs r5, lr
|
|
80008d4: ea40 00dc orrcs.w r0, r0, ip, lsr #3
|
|
80008d8: ea55 0e06 orrs.w lr, r5, r6
|
|
80008dc: d018 beq.n 8000910 <__aeabi_ddiv+0x114>
|
|
80008de: ea4f 1505 mov.w r5, r5, lsl #4
|
|
80008e2: ea45 7516 orr.w r5, r5, r6, lsr #28
|
|
80008e6: ea4f 1606 mov.w r6, r6, lsl #4
|
|
80008ea: ea4f 03c3 mov.w r3, r3, lsl #3
|
|
80008ee: ea43 7352 orr.w r3, r3, r2, lsr #29
|
|
80008f2: ea4f 02c2 mov.w r2, r2, lsl #3
|
|
80008f6: ea5f 1c1c movs.w ip, ip, lsr #4
|
|
80008fa: d1c0 bne.n 800087e <__aeabi_ddiv+0x82>
|
|
80008fc: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000900: d10b bne.n 800091a <__aeabi_ddiv+0x11e>
|
|
8000902: ea41 0100 orr.w r1, r1, r0
|
|
8000906: f04f 0000 mov.w r0, #0
|
|
800090a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
|
|
800090e: e7b6 b.n 800087e <__aeabi_ddiv+0x82>
|
|
8000910: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000914: bf04 itt eq
|
|
8000916: 4301 orreq r1, r0
|
|
8000918: 2000 moveq r0, #0
|
|
800091a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
800091e: bf88 it hi
|
|
8000920: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000924: f63f aeaf bhi.w 8000686 <__aeabi_dmul+0xde>
|
|
8000928: ebb5 0c03 subs.w ip, r5, r3
|
|
800092c: bf04 itt eq
|
|
800092e: ebb6 0c02 subseq.w ip, r6, r2
|
|
8000932: ea5f 0c50 movseq.w ip, r0, lsr #1
|
|
8000936: f150 0000 adcs.w r0, r0, #0
|
|
800093a: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
800093e: bd70 pop {r4, r5, r6, pc}
|
|
8000940: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
|
|
8000944: ea4e 3111 orr.w r1, lr, r1, lsr #12
|
|
8000948: eb14 045c adds.w r4, r4, ip, lsr #1
|
|
800094c: bfc2 ittt gt
|
|
800094e: ebd4 050c rsbsgt r5, r4, ip
|
|
8000952: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
8000956: bd70 popgt {r4, r5, r6, pc}
|
|
8000958: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
800095c: f04f 0e00 mov.w lr, #0
|
|
8000960: 3c01 subs r4, #1
|
|
8000962: e690 b.n 8000686 <__aeabi_dmul+0xde>
|
|
8000964: ea45 0e06 orr.w lr, r5, r6
|
|
8000968: e68d b.n 8000686 <__aeabi_dmul+0xde>
|
|
800096a: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
800096e: ea94 0f0c teq r4, ip
|
|
8000972: bf08 it eq
|
|
8000974: ea95 0f0c teqeq r5, ip
|
|
8000978: f43f af3b beq.w 80007f2 <__aeabi_dmul+0x24a>
|
|
800097c: ea94 0f0c teq r4, ip
|
|
8000980: d10a bne.n 8000998 <__aeabi_ddiv+0x19c>
|
|
8000982: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
8000986: f47f af34 bne.w 80007f2 <__aeabi_dmul+0x24a>
|
|
800098a: ea95 0f0c teq r5, ip
|
|
800098e: f47f af25 bne.w 80007dc <__aeabi_dmul+0x234>
|
|
8000992: 4610 mov r0, r2
|
|
8000994: 4619 mov r1, r3
|
|
8000996: e72c b.n 80007f2 <__aeabi_dmul+0x24a>
|
|
8000998: ea95 0f0c teq r5, ip
|
|
800099c: d106 bne.n 80009ac <__aeabi_ddiv+0x1b0>
|
|
800099e: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
80009a2: f43f aefd beq.w 80007a0 <__aeabi_dmul+0x1f8>
|
|
80009a6: 4610 mov r0, r2
|
|
80009a8: 4619 mov r1, r3
|
|
80009aa: e722 b.n 80007f2 <__aeabi_dmul+0x24a>
|
|
80009ac: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
80009b0: bf18 it ne
|
|
80009b2: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
80009b6: f47f aec5 bne.w 8000744 <__aeabi_dmul+0x19c>
|
|
80009ba: ea50 0441 orrs.w r4, r0, r1, lsl #1
|
|
80009be: f47f af0d bne.w 80007dc <__aeabi_dmul+0x234>
|
|
80009c2: ea52 0543 orrs.w r5, r2, r3, lsl #1
|
|
80009c6: f47f aeeb bne.w 80007a0 <__aeabi_dmul+0x1f8>
|
|
80009ca: e712 b.n 80007f2 <__aeabi_dmul+0x24a>
|
|
|
|
080009cc <__gedf2>:
|
|
80009cc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff
|
|
80009d0: e006 b.n 80009e0 <__cmpdf2+0x4>
|
|
80009d2: bf00 nop
|
|
|
|
080009d4 <__ledf2>:
|
|
80009d4: f04f 0c01 mov.w ip, #1
|
|
80009d8: e002 b.n 80009e0 <__cmpdf2+0x4>
|
|
80009da: bf00 nop
|
|
|
|
080009dc <__cmpdf2>:
|
|
80009dc: f04f 0c01 mov.w ip, #1
|
|
80009e0: f84d cd04 str.w ip, [sp, #-4]!
|
|
80009e4: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
80009e8: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
80009ec: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
80009f0: bf18 it ne
|
|
80009f2: ea7f 5c6c mvnsne.w ip, ip, asr #21
|
|
80009f6: d01b beq.n 8000a30 <__cmpdf2+0x54>
|
|
80009f8: b001 add sp, #4
|
|
80009fa: ea50 0c41 orrs.w ip, r0, r1, lsl #1
|
|
80009fe: bf0c ite eq
|
|
8000a00: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
|
|
8000a04: ea91 0f03 teqne r1, r3
|
|
8000a08: bf02 ittt eq
|
|
8000a0a: ea90 0f02 teqeq r0, r2
|
|
8000a0e: 2000 moveq r0, #0
|
|
8000a10: 4770 bxeq lr
|
|
8000a12: f110 0f00 cmn.w r0, #0
|
|
8000a16: ea91 0f03 teq r1, r3
|
|
8000a1a: bf58 it pl
|
|
8000a1c: 4299 cmppl r1, r3
|
|
8000a1e: bf08 it eq
|
|
8000a20: 4290 cmpeq r0, r2
|
|
8000a22: bf2c ite cs
|
|
8000a24: 17d8 asrcs r0, r3, #31
|
|
8000a26: ea6f 70e3 mvncc.w r0, r3, asr #31
|
|
8000a2a: f040 0001 orr.w r0, r0, #1
|
|
8000a2e: 4770 bx lr
|
|
8000a30: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a34: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a38: d102 bne.n 8000a40 <__cmpdf2+0x64>
|
|
8000a3a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000a3e: d107 bne.n 8000a50 <__cmpdf2+0x74>
|
|
8000a40: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a44: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a48: d1d6 bne.n 80009f8 <__cmpdf2+0x1c>
|
|
8000a4a: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000a4e: d0d3 beq.n 80009f8 <__cmpdf2+0x1c>
|
|
8000a50: f85d 0b04 ldr.w r0, [sp], #4
|
|
8000a54: 4770 bx lr
|
|
8000a56: bf00 nop
|
|
|
|
08000a58 <__aeabi_cdrcmple>:
|
|
8000a58: 4684 mov ip, r0
|
|
8000a5a: 4610 mov r0, r2
|
|
8000a5c: 4662 mov r2, ip
|
|
8000a5e: 468c mov ip, r1
|
|
8000a60: 4619 mov r1, r3
|
|
8000a62: 4663 mov r3, ip
|
|
8000a64: e000 b.n 8000a68 <__aeabi_cdcmpeq>
|
|
8000a66: bf00 nop
|
|
|
|
08000a68 <__aeabi_cdcmpeq>:
|
|
8000a68: b501 push {r0, lr}
|
|
8000a6a: f7ff ffb7 bl 80009dc <__cmpdf2>
|
|
8000a6e: 2800 cmp r0, #0
|
|
8000a70: bf48 it mi
|
|
8000a72: f110 0f00 cmnmi.w r0, #0
|
|
8000a76: bd01 pop {r0, pc}
|
|
|
|
08000a78 <__aeabi_dcmpeq>:
|
|
8000a78: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000a7c: f7ff fff4 bl 8000a68 <__aeabi_cdcmpeq>
|
|
8000a80: bf0c ite eq
|
|
8000a82: 2001 moveq r0, #1
|
|
8000a84: 2000 movne r0, #0
|
|
8000a86: f85d fb08 ldr.w pc, [sp], #8
|
|
8000a8a: bf00 nop
|
|
|
|
08000a8c <__aeabi_dcmplt>:
|
|
8000a8c: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000a90: f7ff ffea bl 8000a68 <__aeabi_cdcmpeq>
|
|
8000a94: bf34 ite cc
|
|
8000a96: 2001 movcc r0, #1
|
|
8000a98: 2000 movcs r0, #0
|
|
8000a9a: f85d fb08 ldr.w pc, [sp], #8
|
|
8000a9e: bf00 nop
|
|
|
|
08000aa0 <__aeabi_dcmple>:
|
|
8000aa0: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000aa4: f7ff ffe0 bl 8000a68 <__aeabi_cdcmpeq>
|
|
8000aa8: bf94 ite ls
|
|
8000aaa: 2001 movls r0, #1
|
|
8000aac: 2000 movhi r0, #0
|
|
8000aae: f85d fb08 ldr.w pc, [sp], #8
|
|
8000ab2: bf00 nop
|
|
|
|
08000ab4 <__aeabi_dcmpge>:
|
|
8000ab4: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000ab8: f7ff ffce bl 8000a58 <__aeabi_cdrcmple>
|
|
8000abc: bf94 ite ls
|
|
8000abe: 2001 movls r0, #1
|
|
8000ac0: 2000 movhi r0, #0
|
|
8000ac2: f85d fb08 ldr.w pc, [sp], #8
|
|
8000ac6: bf00 nop
|
|
|
|
08000ac8 <__aeabi_dcmpgt>:
|
|
8000ac8: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000acc: f7ff ffc4 bl 8000a58 <__aeabi_cdrcmple>
|
|
8000ad0: bf34 ite cc
|
|
8000ad2: 2001 movcc r0, #1
|
|
8000ad4: 2000 movcs r0, #0
|
|
8000ad6: f85d fb08 ldr.w pc, [sp], #8
|
|
8000ada: bf00 nop
|
|
|
|
08000adc <__aeabi_dcmpun>:
|
|
8000adc: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000ae0: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000ae4: d102 bne.n 8000aec <__aeabi_dcmpun+0x10>
|
|
8000ae6: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000aea: d10a bne.n 8000b02 <__aeabi_dcmpun+0x26>
|
|
8000aec: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000af0: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000af4: d102 bne.n 8000afc <__aeabi_dcmpun+0x20>
|
|
8000af6: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000afa: d102 bne.n 8000b02 <__aeabi_dcmpun+0x26>
|
|
8000afc: f04f 0000 mov.w r0, #0
|
|
8000b00: 4770 bx lr
|
|
8000b02: f04f 0001 mov.w r0, #1
|
|
8000b06: 4770 bx lr
|
|
|
|
08000b08 <__aeabi_d2iz>:
|
|
8000b08: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000b0c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
8000b10: d215 bcs.n 8000b3e <__aeabi_d2iz+0x36>
|
|
8000b12: d511 bpl.n 8000b38 <__aeabi_d2iz+0x30>
|
|
8000b14: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
8000b18: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
8000b1c: d912 bls.n 8000b44 <__aeabi_d2iz+0x3c>
|
|
8000b1e: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000b22: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000b26: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
8000b2a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
|
|
8000b2e: fa23 f002 lsr.w r0, r3, r2
|
|
8000b32: bf18 it ne
|
|
8000b34: 4240 negne r0, r0
|
|
8000b36: 4770 bx lr
|
|
8000b38: f04f 0000 mov.w r0, #0
|
|
8000b3c: 4770 bx lr
|
|
8000b3e: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000b42: d105 bne.n 8000b50 <__aeabi_d2iz+0x48>
|
|
8000b44: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
|
|
8000b48: bf08 it eq
|
|
8000b4a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
|
|
8000b4e: 4770 bx lr
|
|
8000b50: f04f 0000 mov.w r0, #0
|
|
8000b54: 4770 bx lr
|
|
8000b56: bf00 nop
|
|
|
|
08000b58 <__aeabi_d2uiz>:
|
|
8000b58: 004a lsls r2, r1, #1
|
|
8000b5a: d211 bcs.n 8000b80 <__aeabi_d2uiz+0x28>
|
|
8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
8000b60: d211 bcs.n 8000b86 <__aeabi_d2uiz+0x2e>
|
|
8000b62: d50d bpl.n 8000b80 <__aeabi_d2uiz+0x28>
|
|
8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
8000b6c: d40e bmi.n 8000b8c <__aeabi_d2uiz+0x34>
|
|
8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
8000b7a: fa23 f002 lsr.w r0, r3, r2
|
|
8000b7e: 4770 bx lr
|
|
8000b80: f04f 0000 mov.w r0, #0
|
|
8000b84: 4770 bx lr
|
|
8000b86: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000b8a: d102 bne.n 8000b92 <__aeabi_d2uiz+0x3a>
|
|
8000b8c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8000b90: 4770 bx lr
|
|
8000b92: f04f 0000 mov.w r0, #0
|
|
8000b96: 4770 bx lr
|
|
|
|
08000b98 <__aeabi_d2f>:
|
|
8000b98: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000b9c: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000
|
|
8000ba0: bf24 itt cs
|
|
8000ba2: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000
|
|
8000ba6: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000
|
|
8000baa: d90d bls.n 8000bc8 <__aeabi_d2f+0x30>
|
|
8000bac: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
|
|
8000bb0: ea4f 02c0 mov.w r2, r0, lsl #3
|
|
8000bb4: ea4c 7050 orr.w r0, ip, r0, lsr #29
|
|
8000bb8: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000
|
|
8000bbc: eb40 0083 adc.w r0, r0, r3, lsl #2
|
|
8000bc0: bf08 it eq
|
|
8000bc2: f020 0001 biceq.w r0, r0, #1
|
|
8000bc6: 4770 bx lr
|
|
8000bc8: f011 4f80 tst.w r1, #1073741824 @ 0x40000000
|
|
8000bcc: d121 bne.n 8000c12 <__aeabi_d2f+0x7a>
|
|
8000bce: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000
|
|
8000bd2: bfbc itt lt
|
|
8000bd4: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000
|
|
8000bd8: 4770 bxlt lr
|
|
8000bda: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
8000bde: ea4f 5252 mov.w r2, r2, lsr #21
|
|
8000be2: f1c2 0218 rsb r2, r2, #24
|
|
8000be6: f1c2 0c20 rsb ip, r2, #32
|
|
8000bea: fa10 f30c lsls.w r3, r0, ip
|
|
8000bee: fa20 f002 lsr.w r0, r0, r2
|
|
8000bf2: bf18 it ne
|
|
8000bf4: f040 0001 orrne.w r0, r0, #1
|
|
8000bf8: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000bfc: ea4f 23d3 mov.w r3, r3, lsr #11
|
|
8000c00: fa03 fc0c lsl.w ip, r3, ip
|
|
8000c04: ea40 000c orr.w r0, r0, ip
|
|
8000c08: fa23 f302 lsr.w r3, r3, r2
|
|
8000c0c: ea4f 0343 mov.w r3, r3, lsl #1
|
|
8000c10: e7cc b.n 8000bac <__aeabi_d2f+0x14>
|
|
8000c12: ea7f 5362 mvns.w r3, r2, asr #21
|
|
8000c16: d107 bne.n 8000c28 <__aeabi_d2f+0x90>
|
|
8000c18: ea50 3301 orrs.w r3, r0, r1, lsl #12
|
|
8000c1c: bf1e ittt ne
|
|
8000c1e: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000
|
|
8000c22: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000
|
|
8000c26: 4770 bxne lr
|
|
8000c28: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000
|
|
8000c2c: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
|
|
8000c30: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
|
|
8000c34: 4770 bx lr
|
|
8000c36: bf00 nop
|
|
|
|
08000c38 <__aeabi_d2lz>:
|
|
8000c38: b538 push {r3, r4, r5, lr}
|
|
8000c3a: 2200 movs r2, #0
|
|
8000c3c: 2300 movs r3, #0
|
|
8000c3e: 4604 mov r4, r0
|
|
8000c40: 460d mov r5, r1
|
|
8000c42: f7ff ff23 bl 8000a8c <__aeabi_dcmplt>
|
|
8000c46: b928 cbnz r0, 8000c54 <__aeabi_d2lz+0x1c>
|
|
8000c48: 4620 mov r0, r4
|
|
8000c4a: 4629 mov r1, r5
|
|
8000c4c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8000c50: f000 b80a b.w 8000c68 <__aeabi_d2ulz>
|
|
8000c54: 4620 mov r0, r4
|
|
8000c56: f105 4100 add.w r1, r5, #2147483648 @ 0x80000000
|
|
8000c5a: f000 f805 bl 8000c68 <__aeabi_d2ulz>
|
|
8000c5e: 4240 negs r0, r0
|
|
8000c60: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
8000c64: bd38 pop {r3, r4, r5, pc}
|
|
8000c66: bf00 nop
|
|
|
|
08000c68 <__aeabi_d2ulz>:
|
|
8000c68: b5d0 push {r4, r6, r7, lr}
|
|
8000c6a: 4b0c ldr r3, [pc, #48] @ (8000c9c <__aeabi_d2ulz+0x34>)
|
|
8000c6c: 2200 movs r2, #0
|
|
8000c6e: 4606 mov r6, r0
|
|
8000c70: 460f mov r7, r1
|
|
8000c72: f7ff fc99 bl 80005a8 <__aeabi_dmul>
|
|
8000c76: f7ff ff6f bl 8000b58 <__aeabi_d2uiz>
|
|
8000c7a: 4604 mov r4, r0
|
|
8000c7c: f7ff fc1a bl 80004b4 <__aeabi_ui2d>
|
|
8000c80: 4b07 ldr r3, [pc, #28] @ (8000ca0 <__aeabi_d2ulz+0x38>)
|
|
8000c82: 2200 movs r2, #0
|
|
8000c84: f7ff fc90 bl 80005a8 <__aeabi_dmul>
|
|
8000c88: 4602 mov r2, r0
|
|
8000c8a: 460b mov r3, r1
|
|
8000c8c: 4630 mov r0, r6
|
|
8000c8e: 4639 mov r1, r7
|
|
8000c90: f7ff fad2 bl 8000238 <__aeabi_dsub>
|
|
8000c94: f7ff ff60 bl 8000b58 <__aeabi_d2uiz>
|
|
8000c98: 4621 mov r1, r4
|
|
8000c9a: bdd0 pop {r4, r6, r7, pc}
|
|
8000c9c: 3df00000 .word 0x3df00000
|
|
8000ca0: 41f00000 .word 0x41f00000
|
|
|
|
08000ca4 <MadgwickAHRS_init>:
|
|
float invSqrt(float x);
|
|
|
|
//====================================================================================================
|
|
// Functions
|
|
|
|
void MadgwickAHRS_init (MadgwickAHRS_Filter* filter, float beta, float sample_freq) {
|
|
8000ca4: b480 push {r7}
|
|
8000ca6: b085 sub sp, #20
|
|
8000ca8: af00 add r7, sp, #0
|
|
8000caa: 60f8 str r0, [r7, #12]
|
|
8000cac: ed87 0a02 vstr s0, [r7, #8]
|
|
8000cb0: edc7 0a01 vstr s1, [r7, #4]
|
|
filter->q[0] = 1.0f; // qw
|
|
8000cb4: 68fb ldr r3, [r7, #12]
|
|
8000cb6: f04f 527e mov.w r2, #1065353216 @ 0x3f800000
|
|
8000cba: 601a str r2, [r3, #0]
|
|
filter->q[1] = 0.0f; // qx
|
|
8000cbc: 68fb ldr r3, [r7, #12]
|
|
8000cbe: f04f 0200 mov.w r2, #0
|
|
8000cc2: 605a str r2, [r3, #4]
|
|
filter->q[2] = 0.0f; // qy
|
|
8000cc4: 68fb ldr r3, [r7, #12]
|
|
8000cc6: f04f 0200 mov.w r2, #0
|
|
8000cca: 609a str r2, [r3, #8]
|
|
filter->q[3] = 0.0f; // qz
|
|
8000ccc: 68fb ldr r3, [r7, #12]
|
|
8000cce: f04f 0200 mov.w r2, #0
|
|
8000cd2: 60da str r2, [r3, #12]
|
|
filter->beta = beta;
|
|
8000cd4: 68fb ldr r3, [r7, #12]
|
|
8000cd6: 68ba ldr r2, [r7, #8]
|
|
8000cd8: 611a str r2, [r3, #16]
|
|
filter->sample_freq = sample_freq;
|
|
8000cda: 68fb ldr r3, [r7, #12]
|
|
8000cdc: 687a ldr r2, [r7, #4]
|
|
8000cde: 615a str r2, [r3, #20]
|
|
}
|
|
8000ce0: bf00 nop
|
|
8000ce2: 3714 adds r7, #20
|
|
8000ce4: 46bd mov sp, r7
|
|
8000ce6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000cea: 4770 bx lr
|
|
|
|
08000cec <MadgwickAHRS_update>:
|
|
|
|
|
|
//---------------------------------------------------------------------------------------------------
|
|
// AHRS algorithm update
|
|
|
|
void MadgwickAHRS_update(MadgwickAHRS_Filter* filter, float gx, float gy, float gz, float ax, float ay, float az, float mx, float my, float mz) {
|
|
8000cec: b580 push {r7, lr}
|
|
8000cee: b0b2 sub sp, #200 @ 0xc8
|
|
8000cf0: af00 add r7, sp, #0
|
|
8000cf2: 6278 str r0, [r7, #36] @ 0x24
|
|
8000cf4: ed87 0a08 vstr s0, [r7, #32]
|
|
8000cf8: edc7 0a07 vstr s1, [r7, #28]
|
|
8000cfc: ed87 1a06 vstr s2, [r7, #24]
|
|
8000d00: edc7 1a05 vstr s3, [r7, #20]
|
|
8000d04: ed87 2a04 vstr s4, [r7, #16]
|
|
8000d08: edc7 2a03 vstr s5, [r7, #12]
|
|
8000d0c: ed87 3a02 vstr s6, [r7, #8]
|
|
8000d10: edc7 3a01 vstr s7, [r7, #4]
|
|
8000d14: ed87 4a00 vstr s8, [r7]
|
|
float q[4] = {filter->q[0], filter->q[1], filter->q[2], filter->q[3]};
|
|
8000d18: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000d1a: 681b ldr r3, [r3, #0]
|
|
8000d1c: 63bb str r3, [r7, #56] @ 0x38
|
|
8000d1e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000d20: 685b ldr r3, [r3, #4]
|
|
8000d22: 63fb str r3, [r7, #60] @ 0x3c
|
|
8000d24: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000d26: 689b ldr r3, [r3, #8]
|
|
8000d28: 643b str r3, [r7, #64] @ 0x40
|
|
8000d2a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000d2c: 68db ldr r3, [r3, #12]
|
|
8000d2e: 647b str r3, [r7, #68] @ 0x44
|
|
float qDot[4];
|
|
float hx, hy;
|
|
float _2q0mx, _2q0my, _2q0mz, _2q1mx, _2bx, _2bz, _4bx, _4bz, _2q0, _2q1, _2q2, _2q3, _2q0q2, _2q2q3, q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3;
|
|
|
|
// Use IMU algorithm if magnetometer measurement invalid (avoids NaN in magnetometer normalisation)
|
|
if((mx == 0.0f) && (my == 0.0f) && (mz == 0.0f)) {
|
|
8000d30: edd7 7a02 vldr s15, [r7, #8]
|
|
8000d34: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8000d38: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8000d3c: d11e bne.n 8000d7c <MadgwickAHRS_update+0x90>
|
|
8000d3e: edd7 7a01 vldr s15, [r7, #4]
|
|
8000d42: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8000d46: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8000d4a: d117 bne.n 8000d7c <MadgwickAHRS_update+0x90>
|
|
8000d4c: edd7 7a00 vldr s15, [r7]
|
|
8000d50: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8000d54: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8000d58: d110 bne.n 8000d7c <MadgwickAHRS_update+0x90>
|
|
MadgwickAHRS_update_IMU(filter, gx, gy, gz, ax, ay, az);
|
|
8000d5a: edd7 2a03 vldr s5, [r7, #12]
|
|
8000d5e: ed97 2a04 vldr s4, [r7, #16]
|
|
8000d62: edd7 1a05 vldr s3, [r7, #20]
|
|
8000d66: ed97 1a06 vldr s2, [r7, #24]
|
|
8000d6a: edd7 0a07 vldr s1, [r7, #28]
|
|
8000d6e: ed97 0a08 vldr s0, [r7, #32]
|
|
8000d72: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
8000d74: f000 feb2 bl 8001adc <MadgwickAHRS_update_IMU>
|
|
8000d78: f000 bead b.w 8001ad6 <MadgwickAHRS_update+0xdea>
|
|
return;
|
|
}
|
|
|
|
// Rate of change of quaternion from gyroscope
|
|
qDot[0] = 0.5f * (-q[1] * gx - q[2] * gy - q[3] * gz);
|
|
8000d7c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8000d80: eeb1 7a67 vneg.f32 s14, s15
|
|
8000d84: edd7 7a08 vldr s15, [r7, #32]
|
|
8000d88: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8000d8c: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8000d90: edd7 7a07 vldr s15, [r7, #28]
|
|
8000d94: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8000d98: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8000d9c: edd7 6a11 vldr s13, [r7, #68] @ 0x44
|
|
8000da0: edd7 7a06 vldr s15, [r7, #24]
|
|
8000da4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8000da8: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8000dac: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
8000db0: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000db4: edc7 7a0a vstr s15, [r7, #40] @ 0x28
|
|
qDot[1] = 0.5f * (q[0] * gx + q[2] * gz - q[3] * gy);
|
|
8000db8: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8000dbc: edd7 7a08 vldr s15, [r7, #32]
|
|
8000dc0: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8000dc4: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8000dc8: edd7 7a06 vldr s15, [r7, #24]
|
|
8000dcc: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8000dd0: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8000dd4: edd7 6a11 vldr s13, [r7, #68] @ 0x44
|
|
8000dd8: edd7 7a07 vldr s15, [r7, #28]
|
|
8000ddc: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8000de0: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8000de4: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
8000de8: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000dec: edc7 7a0b vstr s15, [r7, #44] @ 0x2c
|
|
qDot[2] = 0.5f * (q[0] * gy - q[1] * gz + q[3] * gx);
|
|
8000df0: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8000df4: edd7 7a07 vldr s15, [r7, #28]
|
|
8000df8: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8000dfc: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
8000e00: edd7 7a06 vldr s15, [r7, #24]
|
|
8000e04: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8000e08: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8000e0c: edd7 6a11 vldr s13, [r7, #68] @ 0x44
|
|
8000e10: edd7 7a08 vldr s15, [r7, #32]
|
|
8000e14: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8000e18: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8000e1c: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
8000e20: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000e24: edc7 7a0c vstr s15, [r7, #48] @ 0x30
|
|
qDot[3] = 0.5f * (q[0] * gz + q[1] * gy - q[2] * gx);
|
|
8000e28: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8000e2c: edd7 7a06 vldr s15, [r7, #24]
|
|
8000e30: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8000e34: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
8000e38: edd7 7a07 vldr s15, [r7, #28]
|
|
8000e3c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8000e40: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8000e44: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8000e48: edd7 7a08 vldr s15, [r7, #32]
|
|
8000e4c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8000e50: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8000e54: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
8000e58: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000e5c: edc7 7a0d vstr s15, [r7, #52] @ 0x34
|
|
|
|
// Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation)
|
|
if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {
|
|
8000e60: edd7 7a05 vldr s15, [r7, #20]
|
|
8000e64: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8000e68: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8000e6c: d10e bne.n 8000e8c <MadgwickAHRS_update+0x1a0>
|
|
8000e6e: edd7 7a04 vldr s15, [r7, #16]
|
|
8000e72: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8000e76: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8000e7a: d107 bne.n 8000e8c <MadgwickAHRS_update+0x1a0>
|
|
8000e7c: edd7 7a03 vldr s15, [r7, #12]
|
|
8000e80: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8000e84: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8000e88: f000 854e beq.w 8001928 <MadgwickAHRS_update+0xc3c>
|
|
|
|
// Normalise accelerometer measurement
|
|
recipNorm = invSqrt(ax * ax + ay * ay + az * az);
|
|
8000e8c: edd7 7a05 vldr s15, [r7, #20]
|
|
8000e90: ee27 7aa7 vmul.f32 s14, s15, s15
|
|
8000e94: edd7 7a04 vldr s15, [r7, #16]
|
|
8000e98: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8000e9c: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8000ea0: edd7 7a03 vldr s15, [r7, #12]
|
|
8000ea4: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8000ea8: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8000eac: eeb0 0a67 vmov.f32 s0, s15
|
|
8000eb0: f001 f95a bl 8002168 <invSqrt>
|
|
8000eb4: ed87 0a31 vstr s0, [r7, #196] @ 0xc4
|
|
ax *= recipNorm;
|
|
8000eb8: ed97 7a05 vldr s14, [r7, #20]
|
|
8000ebc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8000ec0: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000ec4: edc7 7a05 vstr s15, [r7, #20]
|
|
ay *= recipNorm;
|
|
8000ec8: ed97 7a04 vldr s14, [r7, #16]
|
|
8000ecc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8000ed0: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000ed4: edc7 7a04 vstr s15, [r7, #16]
|
|
az *= recipNorm;
|
|
8000ed8: ed97 7a03 vldr s14, [r7, #12]
|
|
8000edc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8000ee0: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000ee4: edc7 7a03 vstr s15, [r7, #12]
|
|
|
|
// Normalise magnetometer measurement
|
|
recipNorm = invSqrt(mx * mx + my * my + mz * mz);
|
|
8000ee8: edd7 7a02 vldr s15, [r7, #8]
|
|
8000eec: ee27 7aa7 vmul.f32 s14, s15, s15
|
|
8000ef0: edd7 7a01 vldr s15, [r7, #4]
|
|
8000ef4: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8000ef8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8000efc: edd7 7a00 vldr s15, [r7]
|
|
8000f00: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8000f04: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8000f08: eeb0 0a67 vmov.f32 s0, s15
|
|
8000f0c: f001 f92c bl 8002168 <invSqrt>
|
|
8000f10: ed87 0a31 vstr s0, [r7, #196] @ 0xc4
|
|
mx *= recipNorm;
|
|
8000f14: ed97 7a02 vldr s14, [r7, #8]
|
|
8000f18: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8000f1c: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000f20: edc7 7a02 vstr s15, [r7, #8]
|
|
my *= recipNorm;
|
|
8000f24: ed97 7a01 vldr s14, [r7, #4]
|
|
8000f28: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8000f2c: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000f30: edc7 7a01 vstr s15, [r7, #4]
|
|
mz *= recipNorm;
|
|
8000f34: ed97 7a00 vldr s14, [r7]
|
|
8000f38: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8000f3c: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000f40: edc7 7a00 vstr s15, [r7]
|
|
|
|
// Auxiliary variables to avoid repeated arithmetic
|
|
_2q0mx = 2.0f * q[0] * mx;
|
|
8000f44: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8000f48: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8000f4c: ed97 7a02 vldr s14, [r7, #8]
|
|
8000f50: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000f54: edc7 7a30 vstr s15, [r7, #192] @ 0xc0
|
|
_2q0my = 2.0f * q[0] * my;
|
|
8000f58: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8000f5c: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8000f60: ed97 7a01 vldr s14, [r7, #4]
|
|
8000f64: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000f68: edc7 7a2f vstr s15, [r7, #188] @ 0xbc
|
|
_2q0mz = 2.0f * q[0] * mz;
|
|
8000f6c: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8000f70: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8000f74: ed97 7a00 vldr s14, [r7]
|
|
8000f78: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000f7c: edc7 7a2e vstr s15, [r7, #184] @ 0xb8
|
|
_2q1mx = 2.0f * q[1] * mx;
|
|
8000f80: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8000f84: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8000f88: ed97 7a02 vldr s14, [r7, #8]
|
|
8000f8c: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000f90: edc7 7a2d vstr s15, [r7, #180] @ 0xb4
|
|
_2q0 = 2.0f * q[0];
|
|
8000f94: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8000f98: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8000f9c: edc7 7a2c vstr s15, [r7, #176] @ 0xb0
|
|
_2q1 = 2.0f * q[1];
|
|
8000fa0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8000fa4: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8000fa8: edc7 7a2b vstr s15, [r7, #172] @ 0xac
|
|
_2q2 = 2.0f * q[2];
|
|
8000fac: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8000fb0: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8000fb4: edc7 7a2a vstr s15, [r7, #168] @ 0xa8
|
|
_2q3 = 2.0f * q[3];
|
|
8000fb8: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8000fbc: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8000fc0: edc7 7a29 vstr s15, [r7, #164] @ 0xa4
|
|
_2q0q2 = 2.0f * q[0] * q[2];
|
|
8000fc4: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8000fc8: ee37 7aa7 vadd.f32 s14, s15, s15
|
|
8000fcc: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8000fd0: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000fd4: edc7 7a28 vstr s15, [r7, #160] @ 0xa0
|
|
_2q2q3 = 2.0f * q[2] * q[3];
|
|
8000fd8: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8000fdc: ee37 7aa7 vadd.f32 s14, s15, s15
|
|
8000fe0: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8000fe4: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000fe8: edc7 7a27 vstr s15, [r7, #156] @ 0x9c
|
|
q0q0 = q[0] * q[0];
|
|
8000fec: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8000ff0: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8000ff4: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8000ff8: edc7 7a26 vstr s15, [r7, #152] @ 0x98
|
|
q0q1 = q[0] * q[1];
|
|
8000ffc: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8001000: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001004: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001008: edc7 7a25 vstr s15, [r7, #148] @ 0x94
|
|
q0q2 = q[0] * q[2];
|
|
800100c: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8001010: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001014: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001018: edc7 7a24 vstr s15, [r7, #144] @ 0x90
|
|
q0q3 = q[0] * q[3];
|
|
800101c: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8001020: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001024: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001028: edc7 7a23 vstr s15, [r7, #140] @ 0x8c
|
|
q1q1 = q[1] * q[1];
|
|
800102c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
8001030: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001034: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001038: edc7 7a22 vstr s15, [r7, #136] @ 0x88
|
|
q1q2 = q[1] * q[2];
|
|
800103c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
8001040: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001044: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001048: edc7 7a21 vstr s15, [r7, #132] @ 0x84
|
|
q1q3 = q[1] * q[3];
|
|
800104c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
8001050: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001054: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001058: edc7 7a20 vstr s15, [r7, #128] @ 0x80
|
|
q2q2 = q[2] * q[2];
|
|
800105c: ed97 7a10 vldr s14, [r7, #64] @ 0x40
|
|
8001060: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001064: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001068: edc7 7a1f vstr s15, [r7, #124] @ 0x7c
|
|
q2q3 = q[2] * q[3];
|
|
800106c: ed97 7a10 vldr s14, [r7, #64] @ 0x40
|
|
8001070: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001074: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001078: edc7 7a1e vstr s15, [r7, #120] @ 0x78
|
|
q3q3 = q[3] * q[3];
|
|
800107c: ed97 7a11 vldr s14, [r7, #68] @ 0x44
|
|
8001080: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001084: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001088: edc7 7a1d vstr s15, [r7, #116] @ 0x74
|
|
|
|
// Reference direction of Earth's magnetic field
|
|
hx = mx * q0q0 - _2q0my * q[3] + _2q0mz * q[2] + mx * q1q1 + _2q1 * my * q[2] + _2q1 * mz * q[3] - mx * q2q2 - mx * q3q3;
|
|
800108c: ed97 7a02 vldr s14, [r7, #8]
|
|
8001090: edd7 7a26 vldr s15, [r7, #152] @ 0x98
|
|
8001094: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001098: edd7 6a11 vldr s13, [r7, #68] @ 0x44
|
|
800109c: edd7 7a2f vldr s15, [r7, #188] @ 0xbc
|
|
80010a0: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80010a4: ee37 7a67 vsub.f32 s14, s14, s15
|
|
80010a8: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
80010ac: edd7 7a2e vldr s15, [r7, #184] @ 0xb8
|
|
80010b0: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80010b4: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80010b8: edd7 6a02 vldr s13, [r7, #8]
|
|
80010bc: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
80010c0: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80010c4: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80010c8: edd7 6a2b vldr s13, [r7, #172] @ 0xac
|
|
80010cc: edd7 7a01 vldr s15, [r7, #4]
|
|
80010d0: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
80010d4: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
80010d8: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80010dc: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80010e0: edd7 6a2b vldr s13, [r7, #172] @ 0xac
|
|
80010e4: edd7 7a00 vldr s15, [r7]
|
|
80010e8: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
80010ec: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
80010f0: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80010f4: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80010f8: edd7 6a02 vldr s13, [r7, #8]
|
|
80010fc: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
8001100: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001104: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001108: edd7 6a02 vldr s13, [r7, #8]
|
|
800110c: edd7 7a1d vldr s15, [r7, #116] @ 0x74
|
|
8001110: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001114: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001118: edc7 7a1c vstr s15, [r7, #112] @ 0x70
|
|
hy = _2q0mx * q[3] + my * q0q0 - _2q0mz * q[1] + _2q1mx * q[2] - my * q1q1 + my * q2q2 + _2q2 * mz * q[3] - my * q3q3;
|
|
800111c: ed97 7a11 vldr s14, [r7, #68] @ 0x44
|
|
8001120: edd7 7a30 vldr s15, [r7, #192] @ 0xc0
|
|
8001124: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001128: edd7 6a01 vldr s13, [r7, #4]
|
|
800112c: edd7 7a26 vldr s15, [r7, #152] @ 0x98
|
|
8001130: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001134: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001138: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
800113c: edd7 7a2e vldr s15, [r7, #184] @ 0xb8
|
|
8001140: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001144: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001148: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
800114c: edd7 7a2d vldr s15, [r7, #180] @ 0xb4
|
|
8001150: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001154: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001158: edd7 6a01 vldr s13, [r7, #4]
|
|
800115c: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
8001160: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001164: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001168: edd7 6a01 vldr s13, [r7, #4]
|
|
800116c: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
8001170: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001174: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001178: edd7 6a2a vldr s13, [r7, #168] @ 0xa8
|
|
800117c: edd7 7a00 vldr s15, [r7]
|
|
8001180: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001184: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001188: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
800118c: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001190: edd7 6a01 vldr s13, [r7, #4]
|
|
8001194: edd7 7a1d vldr s15, [r7, #116] @ 0x74
|
|
8001198: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
800119c: ee77 7a67 vsub.f32 s15, s14, s15
|
|
80011a0: edc7 7a1b vstr s15, [r7, #108] @ 0x6c
|
|
_2bx = sqrt(hx * hx + hy * hy);
|
|
80011a4: edd7 7a1c vldr s15, [r7, #112] @ 0x70
|
|
80011a8: ee27 7aa7 vmul.f32 s14, s15, s15
|
|
80011ac: edd7 7a1b vldr s15, [r7, #108] @ 0x6c
|
|
80011b0: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
80011b4: ee77 7a27 vadd.f32 s15, s14, s15
|
|
80011b8: ee17 0a90 vmov r0, s15
|
|
80011bc: f7ff f99c bl 80004f8 <__aeabi_f2d>
|
|
80011c0: 4602 mov r2, r0
|
|
80011c2: 460b mov r3, r1
|
|
80011c4: ec43 2b10 vmov d0, r2, r3
|
|
80011c8: f01c fcde bl 801db88 <sqrt>
|
|
80011cc: ec53 2b10 vmov r2, r3, d0
|
|
80011d0: 4610 mov r0, r2
|
|
80011d2: 4619 mov r1, r3
|
|
80011d4: f7ff fce0 bl 8000b98 <__aeabi_d2f>
|
|
80011d8: 4603 mov r3, r0
|
|
80011da: 66bb str r3, [r7, #104] @ 0x68
|
|
_2bz = -_2q0mx * q[2] + _2q0my * q[1] + mz * q0q0 + _2q1mx * q[3] - mz * q1q1 + _2q2 * my * q[3] - mz * q2q2 + mz * q3q3;
|
|
80011dc: edd7 7a30 vldr s15, [r7, #192] @ 0xc0
|
|
80011e0: eeb1 7a67 vneg.f32 s14, s15
|
|
80011e4: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
80011e8: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80011ec: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
80011f0: edd7 7a2f vldr s15, [r7, #188] @ 0xbc
|
|
80011f4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80011f8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80011fc: edd7 6a00 vldr s13, [r7]
|
|
8001200: edd7 7a26 vldr s15, [r7, #152] @ 0x98
|
|
8001204: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001208: ee37 7a27 vadd.f32 s14, s14, s15
|
|
800120c: edd7 6a11 vldr s13, [r7, #68] @ 0x44
|
|
8001210: edd7 7a2d vldr s15, [r7, #180] @ 0xb4
|
|
8001214: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001218: ee37 7a27 vadd.f32 s14, s14, s15
|
|
800121c: edd7 6a00 vldr s13, [r7]
|
|
8001220: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
8001224: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001228: ee37 7a67 vsub.f32 s14, s14, s15
|
|
800122c: edd7 6a2a vldr s13, [r7, #168] @ 0xa8
|
|
8001230: edd7 7a01 vldr s15, [r7, #4]
|
|
8001234: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001238: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
800123c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001240: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001244: edd7 6a00 vldr s13, [r7]
|
|
8001248: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
800124c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001250: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001254: edd7 6a00 vldr s13, [r7]
|
|
8001258: edd7 7a1d vldr s15, [r7, #116] @ 0x74
|
|
800125c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001260: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001264: edc7 7a19 vstr s15, [r7, #100] @ 0x64
|
|
_4bx = 2.0f * _2bx;
|
|
8001268: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
800126c: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8001270: edc7 7a18 vstr s15, [r7, #96] @ 0x60
|
|
_4bz = 2.0f * _2bz;
|
|
8001274: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001278: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
800127c: edc7 7a17 vstr s15, [r7, #92] @ 0x5c
|
|
|
|
// Gradient decent algorithm corrective step
|
|
s0 = -_2q2 * (2.0f * q1q3 - _2q0q2 - ax) + _2q1 * (2.0f * q0q1 + _2q2q3 - ay) - _2bz * q[2] * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (-_2bx * q[3] + _2bz * q[1]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + _2bx * q[2] * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
|
|
8001280: edd7 7a2a vldr s15, [r7, #168] @ 0xa8
|
|
8001284: eeb1 7a67 vneg.f32 s14, s15
|
|
8001288: edd7 7a20 vldr s15, [r7, #128] @ 0x80
|
|
800128c: ee77 6aa7 vadd.f32 s13, s15, s15
|
|
8001290: edd7 7a28 vldr s15, [r7, #160] @ 0xa0
|
|
8001294: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
8001298: edd7 7a05 vldr s15, [r7, #20]
|
|
800129c: ee76 7ae7 vsub.f32 s15, s13, s15
|
|
80012a0: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80012a4: edd7 7a25 vldr s15, [r7, #148] @ 0x94
|
|
80012a8: ee77 6aa7 vadd.f32 s13, s15, s15
|
|
80012ac: edd7 7a27 vldr s15, [r7, #156] @ 0x9c
|
|
80012b0: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
80012b4: edd7 7a04 vldr s15, [r7, #16]
|
|
80012b8: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
80012bc: edd7 7a2b vldr s15, [r7, #172] @ 0xac
|
|
80012c0: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80012c4: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80012c8: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
80012cc: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
80012d0: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
80012d4: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5
|
|
80012d8: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
80012dc: ee36 6a67 vsub.f32 s12, s12, s15
|
|
80012e0: edd7 7a1d vldr s15, [r7, #116] @ 0x74
|
|
80012e4: ee36 6a67 vsub.f32 s12, s12, s15
|
|
80012e8: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
80012ec: ee26 6a27 vmul.f32 s12, s12, s15
|
|
80012f0: edd7 5a20 vldr s11, [r7, #128] @ 0x80
|
|
80012f4: edd7 7a24 vldr s15, [r7, #144] @ 0x90
|
|
80012f8: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
80012fc: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001300: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
8001304: ee36 6a27 vadd.f32 s12, s12, s15
|
|
8001308: edd7 7a02 vldr s15, [r7, #8]
|
|
800130c: ee76 7a67 vsub.f32 s15, s12, s15
|
|
8001310: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001314: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001318: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
800131c: eef1 6a67 vneg.f32 s13, s15
|
|
8001320: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001324: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001328: ed97 6a0f vldr s12, [r7, #60] @ 0x3c
|
|
800132c: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001330: ee66 7a27 vmul.f32 s15, s12, s15
|
|
8001334: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
8001338: ed97 6a21 vldr s12, [r7, #132] @ 0x84
|
|
800133c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001340: ee36 6a67 vsub.f32 s12, s12, s15
|
|
8001344: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
8001348: ee26 6a27 vmul.f32 s12, s12, s15
|
|
800134c: edd7 5a25 vldr s11, [r7, #148] @ 0x94
|
|
8001350: edd7 7a1e vldr s15, [r7, #120] @ 0x78
|
|
8001354: ee75 5aa7 vadd.f32 s11, s11, s15
|
|
8001358: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
800135c: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
8001360: ee36 6a27 vadd.f32 s12, s12, s15
|
|
8001364: edd7 7a01 vldr s15, [r7, #4]
|
|
8001368: ee76 7a67 vsub.f32 s15, s12, s15
|
|
800136c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001370: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001374: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8001378: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
800137c: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001380: ed97 6a24 vldr s12, [r7, #144] @ 0x90
|
|
8001384: edd7 7a20 vldr s15, [r7, #128] @ 0x80
|
|
8001388: ee36 6a27 vadd.f32 s12, s12, s15
|
|
800138c: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
8001390: ee26 6a27 vmul.f32 s12, s12, s15
|
|
8001394: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5
|
|
8001398: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
800139c: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
80013a0: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
80013a4: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
80013a8: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
80013ac: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
80013b0: ee36 6a27 vadd.f32 s12, s12, s15
|
|
80013b4: edd7 7a00 vldr s15, [r7]
|
|
80013b8: ee76 7a67 vsub.f32 s15, s12, s15
|
|
80013bc: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80013c0: ee77 7a27 vadd.f32 s15, s14, s15
|
|
80013c4: edc7 7a16 vstr s15, [r7, #88] @ 0x58
|
|
s1 = _2q3 * (2.0f * q1q3 - _2q0q2 - ax) + _2q0 * (2.0f * q0q1 + _2q2q3 - ay) - 4.0f * q[1] * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) + _2bz * q[3] * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (_2bx * q[2] + _2bz * q[0]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + (_2bx * q[3] - _4bz * q[1]) * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
|
|
80013c8: edd7 7a20 vldr s15, [r7, #128] @ 0x80
|
|
80013cc: ee37 7aa7 vadd.f32 s14, s15, s15
|
|
80013d0: edd7 7a28 vldr s15, [r7, #160] @ 0xa0
|
|
80013d4: ee37 7a67 vsub.f32 s14, s14, s15
|
|
80013d8: edd7 7a05 vldr s15, [r7, #20]
|
|
80013dc: ee37 7a67 vsub.f32 s14, s14, s15
|
|
80013e0: edd7 7a29 vldr s15, [r7, #164] @ 0xa4
|
|
80013e4: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80013e8: edd7 7a25 vldr s15, [r7, #148] @ 0x94
|
|
80013ec: ee77 6aa7 vadd.f32 s13, s15, s15
|
|
80013f0: edd7 7a27 vldr s15, [r7, #156] @ 0x9c
|
|
80013f4: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
80013f8: edd7 7a04 vldr s15, [r7, #16]
|
|
80013fc: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
8001400: edd7 7a2c vldr s15, [r7, #176] @ 0xb0
|
|
8001404: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001408: ee37 7a27 vadd.f32 s14, s14, s15
|
|
800140c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001410: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0
|
|
8001414: ee67 6aa6 vmul.f32 s13, s15, s13
|
|
8001418: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
800141c: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8001420: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0
|
|
8001424: ee36 6a67 vsub.f32 s12, s12, s15
|
|
8001428: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
800142c: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8001430: ee36 6a67 vsub.f32 s12, s12, s15
|
|
8001434: edd7 7a03 vldr s15, [r7, #12]
|
|
8001438: ee76 7a67 vsub.f32 s15, s12, s15
|
|
800143c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001440: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001444: edd7 6a11 vldr s13, [r7, #68] @ 0x44
|
|
8001448: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
800144c: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001450: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5
|
|
8001454: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
8001458: ee36 6a67 vsub.f32 s12, s12, s15
|
|
800145c: edd7 7a1d vldr s15, [r7, #116] @ 0x74
|
|
8001460: ee36 6a67 vsub.f32 s12, s12, s15
|
|
8001464: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
8001468: ee26 6a27 vmul.f32 s12, s12, s15
|
|
800146c: edd7 5a20 vldr s11, [r7, #128] @ 0x80
|
|
8001470: edd7 7a24 vldr s15, [r7, #144] @ 0x90
|
|
8001474: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
8001478: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
800147c: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
8001480: ee36 6a27 vadd.f32 s12, s12, s15
|
|
8001484: edd7 7a02 vldr s15, [r7, #8]
|
|
8001488: ee76 7a67 vsub.f32 s15, s12, s15
|
|
800148c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001490: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001494: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8001498: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
800149c: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
80014a0: ed97 6a0e vldr s12, [r7, #56] @ 0x38
|
|
80014a4: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
80014a8: ee66 7a27 vmul.f32 s15, s12, s15
|
|
80014ac: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
80014b0: ed97 6a21 vldr s12, [r7, #132] @ 0x84
|
|
80014b4: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
80014b8: ee36 6a67 vsub.f32 s12, s12, s15
|
|
80014bc: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
80014c0: ee26 6a27 vmul.f32 s12, s12, s15
|
|
80014c4: edd7 5a25 vldr s11, [r7, #148] @ 0x94
|
|
80014c8: edd7 7a1e vldr s15, [r7, #120] @ 0x78
|
|
80014cc: ee75 5aa7 vadd.f32 s11, s11, s15
|
|
80014d0: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
80014d4: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
80014d8: ee36 6a27 vadd.f32 s12, s12, s15
|
|
80014dc: edd7 7a01 vldr s15, [r7, #4]
|
|
80014e0: ee76 7a67 vsub.f32 s15, s12, s15
|
|
80014e4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80014e8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80014ec: edd7 6a11 vldr s13, [r7, #68] @ 0x44
|
|
80014f0: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
80014f4: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
80014f8: ed97 6a0f vldr s12, [r7, #60] @ 0x3c
|
|
80014fc: edd7 7a17 vldr s15, [r7, #92] @ 0x5c
|
|
8001500: ee66 7a27 vmul.f32 s15, s12, s15
|
|
8001504: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
8001508: ed97 6a24 vldr s12, [r7, #144] @ 0x90
|
|
800150c: edd7 7a20 vldr s15, [r7, #128] @ 0x80
|
|
8001510: ee36 6a27 vadd.f32 s12, s12, s15
|
|
8001514: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
8001518: ee26 6a27 vmul.f32 s12, s12, s15
|
|
800151c: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5
|
|
8001520: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
8001524: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
8001528: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
800152c: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
8001530: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001534: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
8001538: ee36 6a27 vadd.f32 s12, s12, s15
|
|
800153c: edd7 7a00 vldr s15, [r7]
|
|
8001540: ee76 7a67 vsub.f32 s15, s12, s15
|
|
8001544: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001548: ee77 7a27 vadd.f32 s15, s14, s15
|
|
800154c: edc7 7a15 vstr s15, [r7, #84] @ 0x54
|
|
s2 = -_2q0 * (2.0f * q1q3 - _2q0q2 - ax) + _2q3 * (2.0f * q0q1 + _2q2q3 - ay) - 4.0f * q[2] * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) + (-_4bx * q[2] - _2bz * q[0]) * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (_2bx * q[1] + _2bz * q[3]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + (_2bx * q[0] - _4bz * q[2]) * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
|
|
8001550: edd7 7a2c vldr s15, [r7, #176] @ 0xb0
|
|
8001554: eeb1 7a67 vneg.f32 s14, s15
|
|
8001558: edd7 7a20 vldr s15, [r7, #128] @ 0x80
|
|
800155c: ee77 6aa7 vadd.f32 s13, s15, s15
|
|
8001560: edd7 7a28 vldr s15, [r7, #160] @ 0xa0
|
|
8001564: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
8001568: edd7 7a05 vldr s15, [r7, #20]
|
|
800156c: ee76 7ae7 vsub.f32 s15, s13, s15
|
|
8001570: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001574: edd7 7a25 vldr s15, [r7, #148] @ 0x94
|
|
8001578: ee77 6aa7 vadd.f32 s13, s15, s15
|
|
800157c: edd7 7a27 vldr s15, [r7, #156] @ 0x9c
|
|
8001580: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
8001584: edd7 7a04 vldr s15, [r7, #16]
|
|
8001588: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
800158c: edd7 7a29 vldr s15, [r7, #164] @ 0xa4
|
|
8001590: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001594: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001598: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
800159c: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0
|
|
80015a0: ee67 6aa6 vmul.f32 s13, s15, s13
|
|
80015a4: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
80015a8: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
80015ac: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0
|
|
80015b0: ee36 6a67 vsub.f32 s12, s12, s15
|
|
80015b4: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
80015b8: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
80015bc: ee36 6a67 vsub.f32 s12, s12, s15
|
|
80015c0: edd7 7a03 vldr s15, [r7, #12]
|
|
80015c4: ee76 7a67 vsub.f32 s15, s12, s15
|
|
80015c8: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80015cc: ee37 7a67 vsub.f32 s14, s14, s15
|
|
80015d0: edd7 7a18 vldr s15, [r7, #96] @ 0x60
|
|
80015d4: eef1 6a67 vneg.f32 s13, s15
|
|
80015d8: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
80015dc: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
80015e0: ed97 6a0e vldr s12, [r7, #56] @ 0x38
|
|
80015e4: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
80015e8: ee66 7a27 vmul.f32 s15, s12, s15
|
|
80015ec: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
80015f0: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5
|
|
80015f4: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
80015f8: ee36 6a67 vsub.f32 s12, s12, s15
|
|
80015fc: edd7 7a1d vldr s15, [r7, #116] @ 0x74
|
|
8001600: ee36 6a67 vsub.f32 s12, s12, s15
|
|
8001604: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
8001608: ee26 6a27 vmul.f32 s12, s12, s15
|
|
800160c: edd7 5a20 vldr s11, [r7, #128] @ 0x80
|
|
8001610: edd7 7a24 vldr s15, [r7, #144] @ 0x90
|
|
8001614: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
8001618: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
800161c: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
8001620: ee36 6a27 vadd.f32 s12, s12, s15
|
|
8001624: edd7 7a02 vldr s15, [r7, #8]
|
|
8001628: ee76 7a67 vsub.f32 s15, s12, s15
|
|
800162c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001630: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001634: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
8001638: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
800163c: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001640: ed97 6a11 vldr s12, [r7, #68] @ 0x44
|
|
8001644: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001648: ee66 7a27 vmul.f32 s15, s12, s15
|
|
800164c: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
8001650: ed97 6a21 vldr s12, [r7, #132] @ 0x84
|
|
8001654: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001658: ee36 6a67 vsub.f32 s12, s12, s15
|
|
800165c: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
8001660: ee26 6a27 vmul.f32 s12, s12, s15
|
|
8001664: edd7 5a25 vldr s11, [r7, #148] @ 0x94
|
|
8001668: edd7 7a1e vldr s15, [r7, #120] @ 0x78
|
|
800166c: ee75 5aa7 vadd.f32 s11, s11, s15
|
|
8001670: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001674: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
8001678: ee36 6a27 vadd.f32 s12, s12, s15
|
|
800167c: edd7 7a01 vldr s15, [r7, #4]
|
|
8001680: ee76 7a67 vsub.f32 s15, s12, s15
|
|
8001684: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001688: ee37 7a27 vadd.f32 s14, s14, s15
|
|
800168c: edd7 6a0e vldr s13, [r7, #56] @ 0x38
|
|
8001690: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
8001694: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001698: ed97 6a10 vldr s12, [r7, #64] @ 0x40
|
|
800169c: edd7 7a17 vldr s15, [r7, #92] @ 0x5c
|
|
80016a0: ee66 7a27 vmul.f32 s15, s12, s15
|
|
80016a4: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
80016a8: ed97 6a24 vldr s12, [r7, #144] @ 0x90
|
|
80016ac: edd7 7a20 vldr s15, [r7, #128] @ 0x80
|
|
80016b0: ee36 6a27 vadd.f32 s12, s12, s15
|
|
80016b4: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
80016b8: ee26 6a27 vmul.f32 s12, s12, s15
|
|
80016bc: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5
|
|
80016c0: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
80016c4: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
80016c8: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
80016cc: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
80016d0: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
80016d4: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
80016d8: ee36 6a27 vadd.f32 s12, s12, s15
|
|
80016dc: edd7 7a00 vldr s15, [r7]
|
|
80016e0: ee76 7a67 vsub.f32 s15, s12, s15
|
|
80016e4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80016e8: ee77 7a27 vadd.f32 s15, s14, s15
|
|
80016ec: edc7 7a14 vstr s15, [r7, #80] @ 0x50
|
|
s3 = _2q1 * (2.0f * q1q3 - _2q0q2 - ax) + _2q2 * (2.0f * q0q1 + _2q2q3 - ay) + (-_4bx * q[3] + _2bz * q[1]) * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (-_2bx * q[0] + _2bz * q[2]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + _2bx * q[1] * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
|
|
80016f0: edd7 7a20 vldr s15, [r7, #128] @ 0x80
|
|
80016f4: ee37 7aa7 vadd.f32 s14, s15, s15
|
|
80016f8: edd7 7a28 vldr s15, [r7, #160] @ 0xa0
|
|
80016fc: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001700: edd7 7a05 vldr s15, [r7, #20]
|
|
8001704: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001708: edd7 7a2b vldr s15, [r7, #172] @ 0xac
|
|
800170c: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001710: edd7 7a25 vldr s15, [r7, #148] @ 0x94
|
|
8001714: ee77 6aa7 vadd.f32 s13, s15, s15
|
|
8001718: edd7 7a27 vldr s15, [r7, #156] @ 0x9c
|
|
800171c: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
8001720: edd7 7a04 vldr s15, [r7, #16]
|
|
8001724: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
8001728: edd7 7a2a vldr s15, [r7, #168] @ 0xa8
|
|
800172c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001730: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001734: edd7 7a18 vldr s15, [r7, #96] @ 0x60
|
|
8001738: eef1 6a67 vneg.f32 s13, s15
|
|
800173c: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001740: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001744: ed97 6a0f vldr s12, [r7, #60] @ 0x3c
|
|
8001748: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
800174c: ee66 7a27 vmul.f32 s15, s12, s15
|
|
8001750: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
8001754: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5
|
|
8001758: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
800175c: ee36 6a67 vsub.f32 s12, s12, s15
|
|
8001760: edd7 7a1d vldr s15, [r7, #116] @ 0x74
|
|
8001764: ee36 6a67 vsub.f32 s12, s12, s15
|
|
8001768: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
800176c: ee26 6a27 vmul.f32 s12, s12, s15
|
|
8001770: edd7 5a20 vldr s11, [r7, #128] @ 0x80
|
|
8001774: edd7 7a24 vldr s15, [r7, #144] @ 0x90
|
|
8001778: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
800177c: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001780: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
8001784: ee36 6a27 vadd.f32 s12, s12, s15
|
|
8001788: edd7 7a02 vldr s15, [r7, #8]
|
|
800178c: ee76 7a67 vsub.f32 s15, s12, s15
|
|
8001790: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001794: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001798: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
800179c: eef1 6a67 vneg.f32 s13, s15
|
|
80017a0: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
80017a4: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
80017a8: ed97 6a10 vldr s12, [r7, #64] @ 0x40
|
|
80017ac: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
80017b0: ee66 7a27 vmul.f32 s15, s12, s15
|
|
80017b4: ee76 6aa7 vadd.f32 s13, s13, s15
|
|
80017b8: ed97 6a21 vldr s12, [r7, #132] @ 0x84
|
|
80017bc: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
80017c0: ee36 6a67 vsub.f32 s12, s12, s15
|
|
80017c4: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
80017c8: ee26 6a27 vmul.f32 s12, s12, s15
|
|
80017cc: edd7 5a25 vldr s11, [r7, #148] @ 0x94
|
|
80017d0: edd7 7a1e vldr s15, [r7, #120] @ 0x78
|
|
80017d4: ee75 5aa7 vadd.f32 s11, s11, s15
|
|
80017d8: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
80017dc: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
80017e0: ee36 6a27 vadd.f32 s12, s12, s15
|
|
80017e4: edd7 7a01 vldr s15, [r7, #4]
|
|
80017e8: ee76 7a67 vsub.f32 s15, s12, s15
|
|
80017ec: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80017f0: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80017f4: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
80017f8: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
80017fc: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
8001800: ed97 6a24 vldr s12, [r7, #144] @ 0x90
|
|
8001804: edd7 7a20 vldr s15, [r7, #128] @ 0x80
|
|
8001808: ee36 6a27 vadd.f32 s12, s12, s15
|
|
800180c: edd7 7a1a vldr s15, [r7, #104] @ 0x68
|
|
8001810: ee26 6a27 vmul.f32 s12, s12, s15
|
|
8001814: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5
|
|
8001818: edd7 7a22 vldr s15, [r7, #136] @ 0x88
|
|
800181c: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
8001820: edd7 7a1f vldr s15, [r7, #124] @ 0x7c
|
|
8001824: ee75 5ae7 vsub.f32 s11, s11, s15
|
|
8001828: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
800182c: ee65 7aa7 vmul.f32 s15, s11, s15
|
|
8001830: ee36 6a27 vadd.f32 s12, s12, s15
|
|
8001834: edd7 7a00 vldr s15, [r7]
|
|
8001838: ee76 7a67 vsub.f32 s15, s12, s15
|
|
800183c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001840: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001844: edc7 7a13 vstr s15, [r7, #76] @ 0x4c
|
|
recipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude
|
|
8001848: edd7 7a16 vldr s15, [r7, #88] @ 0x58
|
|
800184c: ee27 7aa7 vmul.f32 s14, s15, s15
|
|
8001850: edd7 7a15 vldr s15, [r7, #84] @ 0x54
|
|
8001854: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8001858: ee37 7a27 vadd.f32 s14, s14, s15
|
|
800185c: edd7 7a14 vldr s15, [r7, #80] @ 0x50
|
|
8001860: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8001864: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001868: edd7 7a13 vldr s15, [r7, #76] @ 0x4c
|
|
800186c: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8001870: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001874: eeb0 0a67 vmov.f32 s0, s15
|
|
8001878: f000 fc76 bl 8002168 <invSqrt>
|
|
800187c: ed87 0a31 vstr s0, [r7, #196] @ 0xc4
|
|
s0 *= recipNorm;
|
|
8001880: ed97 7a16 vldr s14, [r7, #88] @ 0x58
|
|
8001884: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8001888: ee67 7a27 vmul.f32 s15, s14, s15
|
|
800188c: edc7 7a16 vstr s15, [r7, #88] @ 0x58
|
|
s1 *= recipNorm;
|
|
8001890: ed97 7a15 vldr s14, [r7, #84] @ 0x54
|
|
8001894: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8001898: ee67 7a27 vmul.f32 s15, s14, s15
|
|
800189c: edc7 7a15 vstr s15, [r7, #84] @ 0x54
|
|
s2 *= recipNorm;
|
|
80018a0: ed97 7a14 vldr s14, [r7, #80] @ 0x50
|
|
80018a4: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
80018a8: ee67 7a27 vmul.f32 s15, s14, s15
|
|
80018ac: edc7 7a14 vstr s15, [r7, #80] @ 0x50
|
|
s3 *= recipNorm;
|
|
80018b0: ed97 7a13 vldr s14, [r7, #76] @ 0x4c
|
|
80018b4: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
80018b8: ee67 7a27 vmul.f32 s15, s14, s15
|
|
80018bc: edc7 7a13 vstr s15, [r7, #76] @ 0x4c
|
|
|
|
// Apply feedback step
|
|
qDot[0] -= filter->beta * s0;
|
|
80018c0: ed97 7a0a vldr s14, [r7, #40] @ 0x28
|
|
80018c4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80018c6: edd3 6a04 vldr s13, [r3, #16]
|
|
80018ca: edd7 7a16 vldr s15, [r7, #88] @ 0x58
|
|
80018ce: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80018d2: ee77 7a67 vsub.f32 s15, s14, s15
|
|
80018d6: edc7 7a0a vstr s15, [r7, #40] @ 0x28
|
|
qDot[1] -= filter->beta * s1;
|
|
80018da: ed97 7a0b vldr s14, [r7, #44] @ 0x2c
|
|
80018de: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80018e0: edd3 6a04 vldr s13, [r3, #16]
|
|
80018e4: edd7 7a15 vldr s15, [r7, #84] @ 0x54
|
|
80018e8: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80018ec: ee77 7a67 vsub.f32 s15, s14, s15
|
|
80018f0: edc7 7a0b vstr s15, [r7, #44] @ 0x2c
|
|
qDot[2] -= filter->beta * s2;
|
|
80018f4: ed97 7a0c vldr s14, [r7, #48] @ 0x30
|
|
80018f8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80018fa: edd3 6a04 vldr s13, [r3, #16]
|
|
80018fe: edd7 7a14 vldr s15, [r7, #80] @ 0x50
|
|
8001902: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001906: ee77 7a67 vsub.f32 s15, s14, s15
|
|
800190a: edc7 7a0c vstr s15, [r7, #48] @ 0x30
|
|
qDot[3] -= filter->beta * s3;
|
|
800190e: ed97 7a0d vldr s14, [r7, #52] @ 0x34
|
|
8001912: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001914: edd3 6a04 vldr s13, [r3, #16]
|
|
8001918: edd7 7a13 vldr s15, [r7, #76] @ 0x4c
|
|
800191c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001920: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001924: edc7 7a0d vstr s15, [r7, #52] @ 0x34
|
|
}
|
|
|
|
// Integrate rate of change of quaternion to yield quaternion
|
|
q[0] += qDot[0] * (1.0f / filter->sample_freq);
|
|
8001928: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
800192c: edd7 6a0a vldr s13, [r7, #40] @ 0x28
|
|
8001930: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001932: ed93 6a05 vldr s12, [r3, #20]
|
|
8001936: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
|
|
800193a: eec5 7a86 vdiv.f32 s15, s11, s12
|
|
800193e: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001942: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001946: edc7 7a0e vstr s15, [r7, #56] @ 0x38
|
|
q[1] += qDot[1] * (1.0f / filter->sample_freq);
|
|
800194a: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
800194e: edd7 6a0b vldr s13, [r7, #44] @ 0x2c
|
|
8001952: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001954: ed93 6a05 vldr s12, [r3, #20]
|
|
8001958: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
|
|
800195c: eec5 7a86 vdiv.f32 s15, s11, s12
|
|
8001960: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001964: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001968: edc7 7a0f vstr s15, [r7, #60] @ 0x3c
|
|
q[2] += qDot[2] * (1.0f / filter->sample_freq);
|
|
800196c: ed97 7a10 vldr s14, [r7, #64] @ 0x40
|
|
8001970: edd7 6a0c vldr s13, [r7, #48] @ 0x30
|
|
8001974: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001976: ed93 6a05 vldr s12, [r3, #20]
|
|
800197a: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
|
|
800197e: eec5 7a86 vdiv.f32 s15, s11, s12
|
|
8001982: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001986: ee77 7a27 vadd.f32 s15, s14, s15
|
|
800198a: edc7 7a10 vstr s15, [r7, #64] @ 0x40
|
|
q[3] += qDot[3] * (1.0f / filter->sample_freq);
|
|
800198e: ed97 7a11 vldr s14, [r7, #68] @ 0x44
|
|
8001992: edd7 6a0d vldr s13, [r7, #52] @ 0x34
|
|
8001996: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001998: ed93 6a05 vldr s12, [r3, #20]
|
|
800199c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
|
|
80019a0: eec5 7a86 vdiv.f32 s15, s11, s12
|
|
80019a4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80019a8: ee77 7a27 vadd.f32 s15, s14, s15
|
|
80019ac: edc7 7a11 vstr s15, [r7, #68] @ 0x44
|
|
|
|
// Normalise quaternion
|
|
recipNorm = invSqrt(q[0] * q[0] + q[1] * q[1] + q[2] * q[2] + q[3] * q[3]);
|
|
80019b0: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
80019b4: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
80019b8: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80019bc: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
80019c0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
80019c4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80019c8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80019cc: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
80019d0: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
80019d4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80019d8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80019dc: edd7 6a11 vldr s13, [r7, #68] @ 0x44
|
|
80019e0: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
80019e4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80019e8: ee77 7a27 vadd.f32 s15, s14, s15
|
|
80019ec: eeb0 0a67 vmov.f32 s0, s15
|
|
80019f0: f000 fbba bl 8002168 <invSqrt>
|
|
80019f4: ed87 0a31 vstr s0, [r7, #196] @ 0xc4
|
|
q[0] *= recipNorm;
|
|
80019f8: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
80019fc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8001a00: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001a04: edc7 7a0e vstr s15, [r7, #56] @ 0x38
|
|
q[1] *= recipNorm;
|
|
8001a08: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
8001a0c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8001a10: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001a14: edc7 7a0f vstr s15, [r7, #60] @ 0x3c
|
|
q[2] *= recipNorm;
|
|
8001a18: ed97 7a10 vldr s14, [r7, #64] @ 0x40
|
|
8001a1c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8001a20: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001a24: edc7 7a10 vstr s15, [r7, #64] @ 0x40
|
|
q[3] *= recipNorm;
|
|
8001a28: ed97 7a11 vldr s14, [r7, #68] @ 0x44
|
|
8001a2c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4
|
|
8001a30: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001a34: edc7 7a11 vstr s15, [r7, #68] @ 0x44
|
|
|
|
// enforce hemisphere continuity (because of the positive and negative doubling of output)
|
|
float dot = filter->q[0] * q[0] + filter->q[1] * q[1] + filter->q[2] * q[2] + filter->q[3] * q[3];
|
|
8001a38: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001a3a: ed93 7a00 vldr s14, [r3]
|
|
8001a3e: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8001a42: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001a46: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001a48: edd3 6a01 vldr s13, [r3, #4]
|
|
8001a4c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001a50: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001a54: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001a58: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001a5a: edd3 6a02 vldr s13, [r3, #8]
|
|
8001a5e: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001a62: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001a66: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001a6a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001a6c: edd3 6a03 vldr s13, [r3, #12]
|
|
8001a70: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001a74: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001a78: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001a7c: edc7 7a12 vstr s15, [r7, #72] @ 0x48
|
|
if (dot < 0.0f){
|
|
8001a80: edd7 7a12 vldr s15, [r7, #72] @ 0x48
|
|
8001a84: eef5 7ac0 vcmpe.f32 s15, #0.0
|
|
8001a88: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8001a8c: d517 bpl.n 8001abe <MadgwickAHRS_update+0xdd2>
|
|
q[0] = -q[0];
|
|
8001a8e: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8001a92: eef1 7a67 vneg.f32 s15, s15
|
|
8001a96: edc7 7a0e vstr s15, [r7, #56] @ 0x38
|
|
q[1] = -q[1];
|
|
8001a9a: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001a9e: eef1 7a67 vneg.f32 s15, s15
|
|
8001aa2: edc7 7a0f vstr s15, [r7, #60] @ 0x3c
|
|
q[2] = -q[2];
|
|
8001aa6: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001aaa: eef1 7a67 vneg.f32 s15, s15
|
|
8001aae: edc7 7a10 vstr s15, [r7, #64] @ 0x40
|
|
q[3] = -q[3];
|
|
8001ab2: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8001ab6: eef1 7a67 vneg.f32 s15, s15
|
|
8001aba: edc7 7a11 vstr s15, [r7, #68] @ 0x44
|
|
}
|
|
// Update filter state
|
|
filter->q[0] = q[0];
|
|
8001abe: 6bba ldr r2, [r7, #56] @ 0x38
|
|
8001ac0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001ac2: 601a str r2, [r3, #0]
|
|
filter->q[1] = q[1];
|
|
8001ac4: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
8001ac6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001ac8: 605a str r2, [r3, #4]
|
|
filter->q[2] = q[2];
|
|
8001aca: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8001acc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001ace: 609a str r2, [r3, #8]
|
|
filter->q[3] = q[3];
|
|
8001ad0: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8001ad2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001ad4: 60da str r2, [r3, #12]
|
|
}
|
|
8001ad6: 37c8 adds r7, #200 @ 0xc8
|
|
8001ad8: 46bd mov sp, r7
|
|
8001ada: bd80 pop {r7, pc}
|
|
|
|
08001adc <MadgwickAHRS_update_IMU>:
|
|
|
|
//---------------------------------------------------------------------------------------------------
|
|
// IMU algorithm update
|
|
|
|
void MadgwickAHRS_update_IMU(MadgwickAHRS_Filter* filter, float gx, float gy, float gz, float ax, float ay, float az) {
|
|
8001adc: b580 push {r7, lr}
|
|
8001ade: b0a4 sub sp, #144 @ 0x90
|
|
8001ae0: af00 add r7, sp, #0
|
|
8001ae2: 61f8 str r0, [r7, #28]
|
|
8001ae4: ed87 0a06 vstr s0, [r7, #24]
|
|
8001ae8: edc7 0a05 vstr s1, [r7, #20]
|
|
8001aec: ed87 1a04 vstr s2, [r7, #16]
|
|
8001af0: edc7 1a03 vstr s3, [r7, #12]
|
|
8001af4: ed87 2a02 vstr s4, [r7, #8]
|
|
8001af8: edc7 2a01 vstr s5, [r7, #4]
|
|
float q[4] = {filter->q[0], filter->q[1], filter->q[2], filter->q[3]};
|
|
8001afc: 69fb ldr r3, [r7, #28]
|
|
8001afe: 681b ldr r3, [r3, #0]
|
|
8001b00: 637b str r3, [r7, #52] @ 0x34
|
|
8001b02: 69fb ldr r3, [r7, #28]
|
|
8001b04: 685b ldr r3, [r3, #4]
|
|
8001b06: 63bb str r3, [r7, #56] @ 0x38
|
|
8001b08: 69fb ldr r3, [r7, #28]
|
|
8001b0a: 689b ldr r3, [r3, #8]
|
|
8001b0c: 63fb str r3, [r7, #60] @ 0x3c
|
|
8001b0e: 69fb ldr r3, [r7, #28]
|
|
8001b10: 68db ldr r3, [r3, #12]
|
|
8001b12: 643b str r3, [r7, #64] @ 0x40
|
|
float s0, s1, s2, s3;
|
|
float qDot[4];
|
|
float _2q0, _2q1, _2q2, _2q3, _4q0, _4q1, _4q2 ,_8q1, _8q2, q0q0, q1q1, q2q2, q3q3;
|
|
|
|
// Rate of change of quaternion from gyroscope
|
|
qDot[0] = 0.5f * (-q[1] * gx - q[2] * gy - q[3] * gz);
|
|
8001b14: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8001b18: eeb1 7a67 vneg.f32 s14, s15
|
|
8001b1c: edd7 7a06 vldr s15, [r7, #24]
|
|
8001b20: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001b24: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
8001b28: edd7 7a05 vldr s15, [r7, #20]
|
|
8001b2c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001b30: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001b34: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8001b38: edd7 7a04 vldr s15, [r7, #16]
|
|
8001b3c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001b40: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001b44: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
8001b48: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001b4c: edc7 7a09 vstr s15, [r7, #36] @ 0x24
|
|
qDot[1] = 0.5f * (q[0] * gx + q[2] * gz - q[3] * gy);
|
|
8001b50: ed97 7a0d vldr s14, [r7, #52] @ 0x34
|
|
8001b54: edd7 7a06 vldr s15, [r7, #24]
|
|
8001b58: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001b5c: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
8001b60: edd7 7a04 vldr s15, [r7, #16]
|
|
8001b64: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001b68: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001b6c: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8001b70: edd7 7a05 vldr s15, [r7, #20]
|
|
8001b74: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001b78: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001b7c: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
8001b80: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001b84: edc7 7a0a vstr s15, [r7, #40] @ 0x28
|
|
qDot[2] = 0.5f * (q[0] * gy - q[1] * gz + q[3] * gx);
|
|
8001b88: ed97 7a0d vldr s14, [r7, #52] @ 0x34
|
|
8001b8c: edd7 7a05 vldr s15, [r7, #20]
|
|
8001b90: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001b94: edd7 6a0e vldr s13, [r7, #56] @ 0x38
|
|
8001b98: edd7 7a04 vldr s15, [r7, #16]
|
|
8001b9c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001ba0: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001ba4: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8001ba8: edd7 7a06 vldr s15, [r7, #24]
|
|
8001bac: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001bb0: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001bb4: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
8001bb8: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001bbc: edc7 7a0b vstr s15, [r7, #44] @ 0x2c
|
|
qDot[3] = 0.5f * (q[0] * gz + q[1] * gy - q[2] * gx);
|
|
8001bc0: ed97 7a0d vldr s14, [r7, #52] @ 0x34
|
|
8001bc4: edd7 7a04 vldr s15, [r7, #16]
|
|
8001bc8: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001bcc: edd7 6a0e vldr s13, [r7, #56] @ 0x38
|
|
8001bd0: edd7 7a05 vldr s15, [r7, #20]
|
|
8001bd4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001bd8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001bdc: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
8001be0: edd7 7a06 vldr s15, [r7, #24]
|
|
8001be4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001be8: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001bec: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
8001bf0: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001bf4: edc7 7a0c vstr s15, [r7, #48] @ 0x30
|
|
|
|
// Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation)
|
|
if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {
|
|
8001bf8: edd7 7a03 vldr s15, [r7, #12]
|
|
8001bfc: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8001c00: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8001c04: d10e bne.n 8001c24 <MadgwickAHRS_update_IMU+0x148>
|
|
8001c06: edd7 7a02 vldr s15, [r7, #8]
|
|
8001c0a: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8001c0e: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8001c12: d107 bne.n 8001c24 <MadgwickAHRS_update_IMU+0x148>
|
|
8001c14: edd7 7a01 vldr s15, [r7, #4]
|
|
8001c18: eef5 7a40 vcmp.f32 s15, #0.0
|
|
8001c1c: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8001c20: f000 81c6 beq.w 8001fb0 <MadgwickAHRS_update_IMU+0x4d4>
|
|
|
|
// Normalise accelerometer measurement
|
|
recipNorm = invSqrt(ax * ax + ay * ay + az * az);
|
|
8001c24: edd7 7a03 vldr s15, [r7, #12]
|
|
8001c28: ee27 7aa7 vmul.f32 s14, s15, s15
|
|
8001c2c: edd7 7a02 vldr s15, [r7, #8]
|
|
8001c30: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8001c34: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001c38: edd7 7a01 vldr s15, [r7, #4]
|
|
8001c3c: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8001c40: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001c44: eeb0 0a67 vmov.f32 s0, s15
|
|
8001c48: f000 fa8e bl 8002168 <invSqrt>
|
|
8001c4c: ed87 0a23 vstr s0, [r7, #140] @ 0x8c
|
|
ax *= recipNorm;
|
|
8001c50: ed97 7a03 vldr s14, [r7, #12]
|
|
8001c54: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001c58: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001c5c: edc7 7a03 vstr s15, [r7, #12]
|
|
ay *= recipNorm;
|
|
8001c60: ed97 7a02 vldr s14, [r7, #8]
|
|
8001c64: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001c68: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001c6c: edc7 7a02 vstr s15, [r7, #8]
|
|
az *= recipNorm;
|
|
8001c70: ed97 7a01 vldr s14, [r7, #4]
|
|
8001c74: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001c78: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001c7c: edc7 7a01 vstr s15, [r7, #4]
|
|
|
|
// Auxiliary variables to avoid repeated arithmetic
|
|
_2q0 = 2.0f * q[0];
|
|
8001c80: edd7 7a0d vldr s15, [r7, #52] @ 0x34
|
|
8001c84: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8001c88: edc7 7a22 vstr s15, [r7, #136] @ 0x88
|
|
_2q1 = 2.0f * q[1];
|
|
8001c8c: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8001c90: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8001c94: edc7 7a21 vstr s15, [r7, #132] @ 0x84
|
|
_2q2 = 2.0f * q[2];
|
|
8001c98: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001c9c: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8001ca0: edc7 7a20 vstr s15, [r7, #128] @ 0x80
|
|
_2q3 = 2.0f * q[3];
|
|
8001ca4: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001ca8: ee77 7aa7 vadd.f32 s15, s15, s15
|
|
8001cac: edc7 7a1f vstr s15, [r7, #124] @ 0x7c
|
|
_4q0 = 4.0f * q[0];
|
|
8001cb0: edd7 7a0d vldr s15, [r7, #52] @ 0x34
|
|
8001cb4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
|
|
8001cb8: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001cbc: edc7 7a1e vstr s15, [r7, #120] @ 0x78
|
|
_4q1 = 4.0f * q[1];
|
|
8001cc0: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8001cc4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
|
|
8001cc8: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001ccc: edc7 7a1d vstr s15, [r7, #116] @ 0x74
|
|
_4q2 = 4.0f * q[2];
|
|
8001cd0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001cd4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
|
|
8001cd8: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001cdc: edc7 7a1c vstr s15, [r7, #112] @ 0x70
|
|
_8q1 = 8.0f * q[1];
|
|
8001ce0: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8001ce4: eeb2 7a00 vmov.f32 s14, #32 @ 0x41000000 8.0
|
|
8001ce8: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001cec: edc7 7a1b vstr s15, [r7, #108] @ 0x6c
|
|
_8q2 = 8.0f * q[2];
|
|
8001cf0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001cf4: eeb2 7a00 vmov.f32 s14, #32 @ 0x41000000 8.0
|
|
8001cf8: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001cfc: edc7 7a1a vstr s15, [r7, #104] @ 0x68
|
|
q0q0 = q[0] * q[0];
|
|
8001d00: ed97 7a0d vldr s14, [r7, #52] @ 0x34
|
|
8001d04: edd7 7a0d vldr s15, [r7, #52] @ 0x34
|
|
8001d08: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001d0c: edc7 7a19 vstr s15, [r7, #100] @ 0x64
|
|
q1q1 = q[1] * q[1];
|
|
8001d10: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8001d14: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8001d18: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001d1c: edc7 7a18 vstr s15, [r7, #96] @ 0x60
|
|
q2q2 = q[2] * q[2];
|
|
8001d20: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
8001d24: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001d28: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001d2c: edc7 7a17 vstr s15, [r7, #92] @ 0x5c
|
|
q3q3 = q[3] * q[3];
|
|
8001d30: ed97 7a10 vldr s14, [r7, #64] @ 0x40
|
|
8001d34: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001d38: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001d3c: edc7 7a16 vstr s15, [r7, #88] @ 0x58
|
|
|
|
// Gradient decent algorithm corrective step
|
|
s0 = _4q0 * q2q2 + _2q2 * ax + _4q0 * q1q1 - _2q1 * ay;
|
|
8001d40: ed97 7a1e vldr s14, [r7, #120] @ 0x78
|
|
8001d44: edd7 7a17 vldr s15, [r7, #92] @ 0x5c
|
|
8001d48: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001d4c: edd7 6a20 vldr s13, [r7, #128] @ 0x80
|
|
8001d50: edd7 7a03 vldr s15, [r7, #12]
|
|
8001d54: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001d58: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001d5c: edd7 6a1e vldr s13, [r7, #120] @ 0x78
|
|
8001d60: edd7 7a18 vldr s15, [r7, #96] @ 0x60
|
|
8001d64: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001d68: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001d6c: edd7 6a21 vldr s13, [r7, #132] @ 0x84
|
|
8001d70: edd7 7a02 vldr s15, [r7, #8]
|
|
8001d74: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001d78: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001d7c: edc7 7a15 vstr s15, [r7, #84] @ 0x54
|
|
s1 = _4q1 * q3q3 - _2q3 * ax + 4.0f * q0q0 * q[1] - _2q0 * ay - _4q1 + _8q1 * q1q1 + _8q1 * q2q2 + _4q1 * az;
|
|
8001d80: ed97 7a1d vldr s14, [r7, #116] @ 0x74
|
|
8001d84: edd7 7a16 vldr s15, [r7, #88] @ 0x58
|
|
8001d88: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001d8c: edd7 6a1f vldr s13, [r7, #124] @ 0x7c
|
|
8001d90: edd7 7a03 vldr s15, [r7, #12]
|
|
8001d94: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001d98: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001d9c: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001da0: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0
|
|
8001da4: ee67 6aa6 vmul.f32 s13, s15, s13
|
|
8001da8: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8001dac: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001db0: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001db4: edd7 6a22 vldr s13, [r7, #136] @ 0x88
|
|
8001db8: edd7 7a02 vldr s15, [r7, #8]
|
|
8001dbc: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001dc0: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001dc4: edd7 7a1d vldr s15, [r7, #116] @ 0x74
|
|
8001dc8: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001dcc: edd7 6a1b vldr s13, [r7, #108] @ 0x6c
|
|
8001dd0: edd7 7a18 vldr s15, [r7, #96] @ 0x60
|
|
8001dd4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001dd8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001ddc: edd7 6a1b vldr s13, [r7, #108] @ 0x6c
|
|
8001de0: edd7 7a17 vldr s15, [r7, #92] @ 0x5c
|
|
8001de4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001de8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001dec: edd7 6a1d vldr s13, [r7, #116] @ 0x74
|
|
8001df0: edd7 7a01 vldr s15, [r7, #4]
|
|
8001df4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001df8: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001dfc: edc7 7a14 vstr s15, [r7, #80] @ 0x50
|
|
s2 = 4.0f * q0q0 * q[2] + _2q0 * ax + _4q2 * q3q3 - _2q3 * ay - _4q2 + _8q2 * q1q1 + _8q2 * q2q2 + _4q2 * az;
|
|
8001e00: edd7 7a19 vldr s15, [r7, #100] @ 0x64
|
|
8001e04: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
|
|
8001e08: ee27 7a87 vmul.f32 s14, s15, s14
|
|
8001e0c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8001e10: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001e14: edd7 6a22 vldr s13, [r7, #136] @ 0x88
|
|
8001e18: edd7 7a03 vldr s15, [r7, #12]
|
|
8001e1c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001e20: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001e24: edd7 6a1c vldr s13, [r7, #112] @ 0x70
|
|
8001e28: edd7 7a16 vldr s15, [r7, #88] @ 0x58
|
|
8001e2c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001e30: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001e34: edd7 6a1f vldr s13, [r7, #124] @ 0x7c
|
|
8001e38: edd7 7a02 vldr s15, [r7, #8]
|
|
8001e3c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001e40: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001e44: edd7 7a1c vldr s15, [r7, #112] @ 0x70
|
|
8001e48: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001e4c: edd7 6a1a vldr s13, [r7, #104] @ 0x68
|
|
8001e50: edd7 7a18 vldr s15, [r7, #96] @ 0x60
|
|
8001e54: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001e58: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001e5c: edd7 6a1a vldr s13, [r7, #104] @ 0x68
|
|
8001e60: edd7 7a17 vldr s15, [r7, #92] @ 0x5c
|
|
8001e64: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001e68: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001e6c: edd7 6a1c vldr s13, [r7, #112] @ 0x70
|
|
8001e70: edd7 7a01 vldr s15, [r7, #4]
|
|
8001e74: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001e78: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001e7c: edc7 7a13 vstr s15, [r7, #76] @ 0x4c
|
|
s3 = 4.0f * q1q1 * q[3] - _2q1 * ax + 4.0f * q2q2 * q[3] - _2q2 * ay;
|
|
8001e80: edd7 7a18 vldr s15, [r7, #96] @ 0x60
|
|
8001e84: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
|
|
8001e88: ee27 7a87 vmul.f32 s14, s15, s14
|
|
8001e8c: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001e90: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001e94: edd7 6a21 vldr s13, [r7, #132] @ 0x84
|
|
8001e98: edd7 7a03 vldr s15, [r7, #12]
|
|
8001e9c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001ea0: ee37 7a67 vsub.f32 s14, s14, s15
|
|
8001ea4: edd7 7a17 vldr s15, [r7, #92] @ 0x5c
|
|
8001ea8: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0
|
|
8001eac: ee67 6aa6 vmul.f32 s13, s15, s13
|
|
8001eb0: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
8001eb4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001eb8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001ebc: edd7 6a20 vldr s13, [r7, #128] @ 0x80
|
|
8001ec0: edd7 7a02 vldr s15, [r7, #8]
|
|
8001ec4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001ec8: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001ecc: edc7 7a12 vstr s15, [r7, #72] @ 0x48
|
|
recipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude
|
|
8001ed0: edd7 7a15 vldr s15, [r7, #84] @ 0x54
|
|
8001ed4: ee27 7aa7 vmul.f32 s14, s15, s15
|
|
8001ed8: edd7 7a14 vldr s15, [r7, #80] @ 0x50
|
|
8001edc: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8001ee0: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001ee4: edd7 7a13 vldr s15, [r7, #76] @ 0x4c
|
|
8001ee8: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8001eec: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001ef0: edd7 7a12 vldr s15, [r7, #72] @ 0x48
|
|
8001ef4: ee67 7aa7 vmul.f32 s15, s15, s15
|
|
8001ef8: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001efc: eeb0 0a67 vmov.f32 s0, s15
|
|
8001f00: f000 f932 bl 8002168 <invSqrt>
|
|
8001f04: ed87 0a23 vstr s0, [r7, #140] @ 0x8c
|
|
s0 *= recipNorm;
|
|
8001f08: ed97 7a15 vldr s14, [r7, #84] @ 0x54
|
|
8001f0c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001f10: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001f14: edc7 7a15 vstr s15, [r7, #84] @ 0x54
|
|
s1 *= recipNorm;
|
|
8001f18: ed97 7a14 vldr s14, [r7, #80] @ 0x50
|
|
8001f1c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001f20: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001f24: edc7 7a14 vstr s15, [r7, #80] @ 0x50
|
|
s2 *= recipNorm;
|
|
8001f28: ed97 7a13 vldr s14, [r7, #76] @ 0x4c
|
|
8001f2c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001f30: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001f34: edc7 7a13 vstr s15, [r7, #76] @ 0x4c
|
|
s3 *= recipNorm;
|
|
8001f38: ed97 7a12 vldr s14, [r7, #72] @ 0x48
|
|
8001f3c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8001f40: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8001f44: edc7 7a12 vstr s15, [r7, #72] @ 0x48
|
|
|
|
// Apply feedback step
|
|
qDot[0] -= filter->beta * s0;
|
|
8001f48: ed97 7a09 vldr s14, [r7, #36] @ 0x24
|
|
8001f4c: 69fb ldr r3, [r7, #28]
|
|
8001f4e: edd3 6a04 vldr s13, [r3, #16]
|
|
8001f52: edd7 7a15 vldr s15, [r7, #84] @ 0x54
|
|
8001f56: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001f5a: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001f5e: edc7 7a09 vstr s15, [r7, #36] @ 0x24
|
|
qDot[1] -= filter->beta * s1;
|
|
8001f62: ed97 7a0a vldr s14, [r7, #40] @ 0x28
|
|
8001f66: 69fb ldr r3, [r7, #28]
|
|
8001f68: edd3 6a04 vldr s13, [r3, #16]
|
|
8001f6c: edd7 7a14 vldr s15, [r7, #80] @ 0x50
|
|
8001f70: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001f74: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001f78: edc7 7a0a vstr s15, [r7, #40] @ 0x28
|
|
qDot[2] -= filter->beta * s2;
|
|
8001f7c: ed97 7a0b vldr s14, [r7, #44] @ 0x2c
|
|
8001f80: 69fb ldr r3, [r7, #28]
|
|
8001f82: edd3 6a04 vldr s13, [r3, #16]
|
|
8001f86: edd7 7a13 vldr s15, [r7, #76] @ 0x4c
|
|
8001f8a: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001f8e: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001f92: edc7 7a0b vstr s15, [r7, #44] @ 0x2c
|
|
qDot[3] -= filter->beta * s3;
|
|
8001f96: ed97 7a0c vldr s14, [r7, #48] @ 0x30
|
|
8001f9a: 69fb ldr r3, [r7, #28]
|
|
8001f9c: edd3 6a04 vldr s13, [r3, #16]
|
|
8001fa0: edd7 7a12 vldr s15, [r7, #72] @ 0x48
|
|
8001fa4: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001fa8: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001fac: edc7 7a0c vstr s15, [r7, #48] @ 0x30
|
|
}
|
|
|
|
// Integrate rate of change of quaternion to yield quaternion
|
|
q[0] += qDot[0] * (1.0f / filter->sample_freq);
|
|
8001fb0: ed97 7a0d vldr s14, [r7, #52] @ 0x34
|
|
8001fb4: edd7 6a09 vldr s13, [r7, #36] @ 0x24
|
|
8001fb8: 69fb ldr r3, [r7, #28]
|
|
8001fba: ed93 6a05 vldr s12, [r3, #20]
|
|
8001fbe: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
|
|
8001fc2: eec5 7a86 vdiv.f32 s15, s11, s12
|
|
8001fc6: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001fca: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001fce: edc7 7a0d vstr s15, [r7, #52] @ 0x34
|
|
q[1] += qDot[1] * (1.0f / filter->sample_freq);
|
|
8001fd2: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8001fd6: edd7 6a0a vldr s13, [r7, #40] @ 0x28
|
|
8001fda: 69fb ldr r3, [r7, #28]
|
|
8001fdc: ed93 6a05 vldr s12, [r3, #20]
|
|
8001fe0: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
|
|
8001fe4: eec5 7a86 vdiv.f32 s15, s11, s12
|
|
8001fe8: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8001fec: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8001ff0: edc7 7a0e vstr s15, [r7, #56] @ 0x38
|
|
q[2] += qDot[2] * (1.0f / filter->sample_freq);
|
|
8001ff4: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
8001ff8: edd7 6a0b vldr s13, [r7, #44] @ 0x2c
|
|
8001ffc: 69fb ldr r3, [r7, #28]
|
|
8001ffe: ed93 6a05 vldr s12, [r3, #20]
|
|
8002002: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
|
|
8002006: eec5 7a86 vdiv.f32 s15, s11, s12
|
|
800200a: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
800200e: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8002012: edc7 7a0f vstr s15, [r7, #60] @ 0x3c
|
|
q[3] += qDot[3] * (1.0f / filter->sample_freq);
|
|
8002016: ed97 7a10 vldr s14, [r7, #64] @ 0x40
|
|
800201a: edd7 6a0c vldr s13, [r7, #48] @ 0x30
|
|
800201e: 69fb ldr r3, [r7, #28]
|
|
8002020: ed93 6a05 vldr s12, [r3, #20]
|
|
8002024: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
|
|
8002028: eec5 7a86 vdiv.f32 s15, s11, s12
|
|
800202c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8002030: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8002034: edc7 7a10 vstr s15, [r7, #64] @ 0x40
|
|
|
|
// Normalise quaternion
|
|
recipNorm = invSqrt(q[0] * q[0] + q[1] * q[1] + q[2] * q[2] + q[3] * q[3]);
|
|
8002038: ed97 7a0d vldr s14, [r7, #52] @ 0x34
|
|
800203c: edd7 7a0d vldr s15, [r7, #52] @ 0x34
|
|
8002040: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8002044: edd7 6a0e vldr s13, [r7, #56] @ 0x38
|
|
8002048: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
800204c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8002050: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8002054: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
|
|
8002058: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
800205c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8002060: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8002064: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8002068: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
800206c: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8002070: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8002074: eeb0 0a67 vmov.f32 s0, s15
|
|
8002078: f000 f876 bl 8002168 <invSqrt>
|
|
800207c: ed87 0a23 vstr s0, [r7, #140] @ 0x8c
|
|
q[0] *= recipNorm;
|
|
8002080: ed97 7a0d vldr s14, [r7, #52] @ 0x34
|
|
8002084: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8002088: ee67 7a27 vmul.f32 s15, s14, s15
|
|
800208c: edc7 7a0d vstr s15, [r7, #52] @ 0x34
|
|
q[1] *= recipNorm;
|
|
8002090: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8002094: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
8002098: ee67 7a27 vmul.f32 s15, s14, s15
|
|
800209c: edc7 7a0e vstr s15, [r7, #56] @ 0x38
|
|
q[2] *= recipNorm;
|
|
80020a0: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
80020a4: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
80020a8: ee67 7a27 vmul.f32 s15, s14, s15
|
|
80020ac: edc7 7a0f vstr s15, [r7, #60] @ 0x3c
|
|
q[3] *= recipNorm;
|
|
80020b0: ed97 7a10 vldr s14, [r7, #64] @ 0x40
|
|
80020b4: edd7 7a23 vldr s15, [r7, #140] @ 0x8c
|
|
80020b8: ee67 7a27 vmul.f32 s15, s14, s15
|
|
80020bc: edc7 7a10 vstr s15, [r7, #64] @ 0x40
|
|
|
|
// enforce hemisphere continuity (because of the positive and negative doubling of output)
|
|
float dot = filter->q[0] * q[0] + filter->q[1] * q[1] + filter->q[2] * q[2] + filter->q[3] * q[3];
|
|
80020c0: 69fb ldr r3, [r7, #28]
|
|
80020c2: ed93 7a00 vldr s14, [r3]
|
|
80020c6: edd7 7a0d vldr s15, [r7, #52] @ 0x34
|
|
80020ca: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80020ce: 69fb ldr r3, [r7, #28]
|
|
80020d0: edd3 6a01 vldr s13, [r3, #4]
|
|
80020d4: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
80020d8: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80020dc: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80020e0: 69fb ldr r3, [r7, #28]
|
|
80020e2: edd3 6a02 vldr s13, [r3, #8]
|
|
80020e6: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
80020ea: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80020ee: ee37 7a27 vadd.f32 s14, s14, s15
|
|
80020f2: 69fb ldr r3, [r7, #28]
|
|
80020f4: edd3 6a03 vldr s13, [r3, #12]
|
|
80020f8: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
80020fc: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8002100: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8002104: edc7 7a11 vstr s15, [r7, #68] @ 0x44
|
|
if (dot < 0.0f){
|
|
8002108: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
800210c: eef5 7ac0 vcmpe.f32 s15, #0.0
|
|
8002110: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8002114: d517 bpl.n 8002146 <MadgwickAHRS_update_IMU+0x66a>
|
|
q[0] = -q[0];
|
|
8002116: edd7 7a0d vldr s15, [r7, #52] @ 0x34
|
|
800211a: eef1 7a67 vneg.f32 s15, s15
|
|
800211e: edc7 7a0d vstr s15, [r7, #52] @ 0x34
|
|
q[1] = -q[1];
|
|
8002122: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8002126: eef1 7a67 vneg.f32 s15, s15
|
|
800212a: edc7 7a0e vstr s15, [r7, #56] @ 0x38
|
|
q[2] = -q[2];
|
|
800212e: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8002132: eef1 7a67 vneg.f32 s15, s15
|
|
8002136: edc7 7a0f vstr s15, [r7, #60] @ 0x3c
|
|
q[3] = -q[3];
|
|
800213a: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
800213e: eef1 7a67 vneg.f32 s15, s15
|
|
8002142: edc7 7a10 vstr s15, [r7, #64] @ 0x40
|
|
}
|
|
|
|
// Update filter state
|
|
filter->q[0] = q[0];
|
|
8002146: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
8002148: 69fb ldr r3, [r7, #28]
|
|
800214a: 601a str r2, [r3, #0]
|
|
filter->q[1] = q[1];
|
|
800214c: 6bba ldr r2, [r7, #56] @ 0x38
|
|
800214e: 69fb ldr r3, [r7, #28]
|
|
8002150: 605a str r2, [r3, #4]
|
|
filter->q[2] = q[2];
|
|
8002152: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
8002154: 69fb ldr r3, [r7, #28]
|
|
8002156: 609a str r2, [r3, #8]
|
|
filter->q[3] = q[3];
|
|
8002158: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
800215a: 69fb ldr r3, [r7, #28]
|
|
800215c: 60da str r2, [r3, #12]
|
|
}
|
|
800215e: bf00 nop
|
|
8002160: 3790 adds r7, #144 @ 0x90
|
|
8002162: 46bd mov sp, r7
|
|
8002164: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08002168 <invSqrt>:
|
|
|
|
//---------------------------------------------------------------------------------------------------
|
|
// Fast inverse square-root
|
|
// See: http://en.wikipedia.org/wiki/Fast_inverse_square_root
|
|
|
|
float invSqrt(float x) {
|
|
8002168: b480 push {r7}
|
|
800216a: b087 sub sp, #28
|
|
800216c: af00 add r7, sp, #0
|
|
800216e: ed87 0a01 vstr s0, [r7, #4]
|
|
float halfx = 0.5f * x;
|
|
8002172: edd7 7a01 vldr s15, [r7, #4]
|
|
8002176: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
|
|
800217a: ee67 7a87 vmul.f32 s15, s15, s14
|
|
800217e: edc7 7a05 vstr s15, [r7, #20]
|
|
float y = x;
|
|
8002182: 687b ldr r3, [r7, #4]
|
|
8002184: 613b str r3, [r7, #16]
|
|
long i = *(long*)&y;
|
|
8002186: f107 0310 add.w r3, r7, #16
|
|
800218a: 681b ldr r3, [r3, #0]
|
|
800218c: 60fb str r3, [r7, #12]
|
|
i = 0x5f3759df - (i>>1);
|
|
800218e: 68fb ldr r3, [r7, #12]
|
|
8002190: 105a asrs r2, r3, #1
|
|
8002192: 4b12 ldr r3, [pc, #72] @ (80021dc <invSqrt+0x74>)
|
|
8002194: 1a9b subs r3, r3, r2
|
|
8002196: 60fb str r3, [r7, #12]
|
|
y = *(float*)&i;
|
|
8002198: f107 030c add.w r3, r7, #12
|
|
800219c: 681b ldr r3, [r3, #0]
|
|
800219e: 613b str r3, [r7, #16]
|
|
y = y * (1.5f - (halfx * y * y));
|
|
80021a0: ed97 7a04 vldr s14, [r7, #16]
|
|
80021a4: edd7 7a05 vldr s15, [r7, #20]
|
|
80021a8: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80021ac: edd7 7a04 vldr s15, [r7, #16]
|
|
80021b0: ee67 7a27 vmul.f32 s15, s14, s15
|
|
80021b4: eeb7 7a08 vmov.f32 s14, #120 @ 0x3fc00000 1.5
|
|
80021b8: ee37 7a67 vsub.f32 s14, s14, s15
|
|
80021bc: edd7 7a04 vldr s15, [r7, #16]
|
|
80021c0: ee67 7a27 vmul.f32 s15, s14, s15
|
|
80021c4: edc7 7a04 vstr s15, [r7, #16]
|
|
return y;
|
|
80021c8: 693b ldr r3, [r7, #16]
|
|
80021ca: ee07 3a90 vmov s15, r3
|
|
}
|
|
80021ce: eeb0 0a67 vmov.f32 s0, s15
|
|
80021d2: 371c adds r7, #28
|
|
80021d4: 46bd mov sp, r7
|
|
80021d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80021da: 4770 bx lr
|
|
80021dc: 5f3759df .word 0x5f3759df
|
|
|
|
080021e0 <APPD_EnableCPU2>:
|
|
/* USER CODE END APPD_Init */
|
|
return;
|
|
}
|
|
|
|
void APPD_EnableCPU2( void )
|
|
{
|
|
80021e0: b5b0 push {r4, r5, r7, lr}
|
|
80021e2: b088 sub sp, #32
|
|
80021e4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN APPD_EnableCPU2 */
|
|
SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
|
|
80021e6: 4b0b ldr r3, [pc, #44] @ (8002214 <APPD_EnableCPU2+0x34>)
|
|
80021e8: 1d3c adds r4, r7, #4
|
|
80021ea: 461d mov r5, r3
|
|
80021ec: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
80021ee: c40f stmia r4!, {r0, r1, r2, r3}
|
|
80021f0: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
80021f4: c403 stmia r4!, {r0, r1}
|
|
80021f6: 8022 strh r2, [r4, #0]
|
|
80021f8: 3402 adds r4, #2
|
|
80021fa: 0c13 lsrs r3, r2, #16
|
|
80021fc: 7023 strb r3, [r4, #0]
|
|
NBR_OF_TRACES_CONFIG_PARAMETERS,
|
|
NBR_OF_GENERAL_CONFIG_PARAMETERS}
|
|
};
|
|
|
|
/**< Traces channel initialization */
|
|
TL_TRACES_Init( );
|
|
80021fe: f011 f985 bl 801350c <TL_TRACES_Init>
|
|
|
|
/** GPIO DEBUG Initialization */
|
|
SHCI_C2_DEBUG_Init( &DebugCmdPacket );
|
|
8002202: 1d3b adds r3, r7, #4
|
|
8002204: 4618 mov r0, r3
|
|
8002206: f010 fdfe bl 8012e06 <SHCI_C2_DEBUG_Init>
|
|
|
|
/* USER CODE END APPD_EnableCPU2 */
|
|
return;
|
|
800220a: bf00 nop
|
|
}
|
|
800220c: 3720 adds r7, #32
|
|
800220e: 46bd mov sp, r7
|
|
8002210: bdb0 pop {r4, r5, r7, pc}
|
|
8002212: bf00 nop
|
|
8002214: 0801ddf8 .word 0x0801ddf8
|
|
|
|
08002218 <LL_C2_PWR_SetPowerMode>:
|
|
*
|
|
* (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
|
|
{
|
|
8002218: b480 push {r7}
|
|
800221a: b083 sub sp, #12
|
|
800221c: af00 add r7, sp, #0
|
|
800221e: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode);
|
|
8002220: 4b07 ldr r3, [pc, #28] @ (8002240 <LL_C2_PWR_SetPowerMode+0x28>)
|
|
8002222: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8002226: f023 0207 bic.w r2, r3, #7
|
|
800222a: 4905 ldr r1, [pc, #20] @ (8002240 <LL_C2_PWR_SetPowerMode+0x28>)
|
|
800222c: 687b ldr r3, [r7, #4]
|
|
800222e: 4313 orrs r3, r2
|
|
8002230: f8c1 3080 str.w r3, [r1, #128] @ 0x80
|
|
}
|
|
8002234: bf00 nop
|
|
8002236: 370c adds r7, #12
|
|
8002238: 46bd mov sp, r7
|
|
800223a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800223e: 4770 bx lr
|
|
8002240: 58000400 .word 0x58000400
|
|
|
|
08002244 <LL_EXTI_EnableIT_32_63>:
|
|
* @arg @ref LL_EXTI_LINE_ALL_32_63
|
|
* (*) value not defined in all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
|
|
{
|
|
8002244: b480 push {r7}
|
|
8002246: b083 sub sp, #12
|
|
8002248: af00 add r7, sp, #0
|
|
800224a: 6078 str r0, [r7, #4]
|
|
SET_BIT(EXTI->IMR2, ExtiLine);
|
|
800224c: 4b06 ldr r3, [pc, #24] @ (8002268 <LL_EXTI_EnableIT_32_63+0x24>)
|
|
800224e: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90
|
|
8002252: 4905 ldr r1, [pc, #20] @ (8002268 <LL_EXTI_EnableIT_32_63+0x24>)
|
|
8002254: 687b ldr r3, [r7, #4]
|
|
8002256: 4313 orrs r3, r2
|
|
8002258: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
}
|
|
800225c: bf00 nop
|
|
800225e: 370c adds r7, #12
|
|
8002260: 46bd mov sp, r7
|
|
8002262: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002266: 4770 bx lr
|
|
8002268: 58000800 .word 0x58000800
|
|
|
|
0800226c <LL_RCC_HSE_SetCapacitorTuning>:
|
|
* @rmtoll HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning
|
|
* @param Value Between Min_Data = 0 and Max_Data = 63
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)
|
|
{
|
|
800226c: b480 push {r7}
|
|
800226e: b083 sub sp, #12
|
|
8002270: af00 add r7, sp, #0
|
|
8002272: 6078 str r0, [r7, #4]
|
|
WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
|
|
8002274: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002278: 4a0a ldr r2, [pc, #40] @ (80022a4 <LL_RCC_HSE_SetCapacitorTuning+0x38>)
|
|
800227a: f8c3 209c str.w r2, [r3, #156] @ 0x9c
|
|
MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos);
|
|
800227e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8002282: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c
|
|
8002286: f423 527c bic.w r2, r3, #16128 @ 0x3f00
|
|
800228a: 687b ldr r3, [r7, #4]
|
|
800228c: 021b lsls r3, r3, #8
|
|
800228e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8002292: 4313 orrs r3, r2
|
|
8002294: f8c1 309c str.w r3, [r1, #156] @ 0x9c
|
|
}
|
|
8002298: bf00 nop
|
|
800229a: 370c adds r7, #12
|
|
800229c: 46bd mov sp, r7
|
|
800229e: f85d 7b04 ldr.w r7, [sp], #4
|
|
80022a2: 4770 bx lr
|
|
80022a4: cafecafe .word 0xcafecafe
|
|
|
|
080022a8 <LL_RCC_SetClkAfterWakeFromStop>:
|
|
* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
|
|
* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
|
|
{
|
|
80022a8: b480 push {r7}
|
|
80022aa: b083 sub sp, #12
|
|
80022ac: af00 add r7, sp, #0
|
|
80022ae: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
|
|
80022b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80022b4: 689b ldr r3, [r3, #8]
|
|
80022b6: f423 4200 bic.w r2, r3, #32768 @ 0x8000
|
|
80022ba: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80022be: 687b ldr r3, [r7, #4]
|
|
80022c0: 4313 orrs r3, r2
|
|
80022c2: 608b str r3, [r1, #8]
|
|
}
|
|
80022c4: bf00 nop
|
|
80022c6: 370c adds r7, #12
|
|
80022c8: 46bd mov sp, r7
|
|
80022ca: f85d 7b04 ldr.w r7, [sp], #4
|
|
80022ce: 4770 bx lr
|
|
|
|
080022d0 <LL_DBGMCU_GetDeviceID>:
|
|
* @note For STM32WBxxxx devices, the device ID is 0x495
|
|
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
|
|
* @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495)
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
|
|
{
|
|
80022d0: b480 push {r7}
|
|
80022d2: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
|
|
80022d4: 4b04 ldr r3, [pc, #16] @ (80022e8 <LL_DBGMCU_GetDeviceID+0x18>)
|
|
80022d6: 681b ldr r3, [r3, #0]
|
|
80022d8: f3c3 030b ubfx r3, r3, #0, #12
|
|
}
|
|
80022dc: 4618 mov r0, r3
|
|
80022de: 46bd mov sp, r7
|
|
80022e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80022e4: 4770 bx lr
|
|
80022e6: bf00 nop
|
|
80022e8: e0042000 .word 0xe0042000
|
|
|
|
080022ec <LL_DBGMCU_GetRevisionID>:
|
|
* @note This field indicates the revision of the device.
|
|
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
|
|
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
|
|
{
|
|
80022ec: b480 push {r7}
|
|
80022ee: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
|
|
80022f0: 4b04 ldr r3, [pc, #16] @ (8002304 <LL_DBGMCU_GetRevisionID+0x18>)
|
|
80022f2: 681b ldr r3, [r3, #0]
|
|
80022f4: 0c1b lsrs r3, r3, #16
|
|
80022f6: b29b uxth r3, r3
|
|
}
|
|
80022f8: 4618 mov r0, r3
|
|
80022fa: 46bd mov sp, r7
|
|
80022fc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002300: 4770 bx lr
|
|
8002302: bf00 nop
|
|
8002304: e0042000 .word 0xe0042000
|
|
|
|
08002308 <LL_RTC_EnableWriteProtection>:
|
|
* @rmtoll WPR KEY LL_RTC_EnableWriteProtection
|
|
* @param RTCx RTC Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
|
|
{
|
|
8002308: b480 push {r7}
|
|
800230a: b083 sub sp, #12
|
|
800230c: af00 add r7, sp, #0
|
|
800230e: 6078 str r0, [r7, #4]
|
|
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
|
|
8002310: 687b ldr r3, [r7, #4]
|
|
8002312: 22ff movs r2, #255 @ 0xff
|
|
8002314: 625a str r2, [r3, #36] @ 0x24
|
|
}
|
|
8002316: bf00 nop
|
|
8002318: 370c adds r7, #12
|
|
800231a: 46bd mov sp, r7
|
|
800231c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002320: 4770 bx lr
|
|
|
|
08002322 <LL_RTC_DisableWriteProtection>:
|
|
* @rmtoll WPR KEY LL_RTC_DisableWriteProtection
|
|
* @param RTCx RTC Instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
|
|
{
|
|
8002322: b480 push {r7}
|
|
8002324: b083 sub sp, #12
|
|
8002326: af00 add r7, sp, #0
|
|
8002328: 6078 str r0, [r7, #4]
|
|
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
|
|
800232a: 687b ldr r3, [r7, #4]
|
|
800232c: 22ca movs r2, #202 @ 0xca
|
|
800232e: 625a str r2, [r3, #36] @ 0x24
|
|
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
|
|
8002330: 687b ldr r3, [r7, #4]
|
|
8002332: 2253 movs r2, #83 @ 0x53
|
|
8002334: 625a str r2, [r3, #36] @ 0x24
|
|
}
|
|
8002336: bf00 nop
|
|
8002338: 370c adds r7, #12
|
|
800233a: 46bd mov sp, r7
|
|
800233c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002340: 4770 bx lr
|
|
|
|
08002342 <LL_RTC_WAKEUP_SetClock>:
|
|
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
|
|
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
|
|
{
|
|
8002342: b480 push {r7}
|
|
8002344: b083 sub sp, #12
|
|
8002346: af00 add r7, sp, #0
|
|
8002348: 6078 str r0, [r7, #4]
|
|
800234a: 6039 str r1, [r7, #0]
|
|
MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
|
|
800234c: 687b ldr r3, [r7, #4]
|
|
800234e: 689b ldr r3, [r3, #8]
|
|
8002350: f023 0207 bic.w r2, r3, #7
|
|
8002354: 683b ldr r3, [r7, #0]
|
|
8002356: 431a orrs r2, r3
|
|
8002358: 687b ldr r3, [r7, #4]
|
|
800235a: 609a str r2, [r3, #8]
|
|
}
|
|
800235c: bf00 nop
|
|
800235e: 370c adds r7, #12
|
|
8002360: 46bd mov sp, r7
|
|
8002362: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002366: 4770 bx lr
|
|
|
|
08002368 <MX_APPE_Config>:
|
|
|
|
/* USER CODE END PFP */
|
|
|
|
/* Functions Definition ------------------------------------------------------*/
|
|
void MX_APPE_Config(void)
|
|
{
|
|
8002368: b580 push {r7, lr}
|
|
800236a: af00 add r7, sp, #0
|
|
/**
|
|
* The OPTVERR flag is wrongly set at power on
|
|
* It shall be cleared before using any HAL_FLASH_xxx() api
|
|
*/
|
|
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
|
|
800236c: 4b04 ldr r3, [pc, #16] @ (8002380 <MX_APPE_Config+0x18>)
|
|
800236e: f44f 4200 mov.w r2, #32768 @ 0x8000
|
|
8002372: 611a str r2, [r3, #16]
|
|
|
|
/**
|
|
* Reset some configurations so that the system behave in the same way
|
|
* when either out of nReset or Power On
|
|
*/
|
|
Reset_Device();
|
|
8002374: f000 f824 bl 80023c0 <Reset_Device>
|
|
|
|
/* Configure HSE Tuning */
|
|
Config_HSE();
|
|
8002378: f000 f829 bl 80023ce <Config_HSE>
|
|
|
|
return;
|
|
800237c: bf00 nop
|
|
}
|
|
800237e: bd80 pop {r7, pc}
|
|
8002380: 58004000 .word 0x58004000
|
|
|
|
08002384 <MX_APPE_Init>:
|
|
|
|
void MX_APPE_Init(void)
|
|
{
|
|
8002384: b580 push {r7, lr}
|
|
8002386: af00 add r7, sp, #0
|
|
System_Init(); /**< System initialization */
|
|
8002388: f000 f835 bl 80023f6 <System_Init>
|
|
|
|
SystemPower_Config(); /**< Configure the system Power Mode */
|
|
800238c: f000 f84e bl 800242c <SystemPower_Config>
|
|
|
|
HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
|
|
8002390: 4903 ldr r1, [pc, #12] @ (80023a0 <MX_APPE_Init+0x1c>)
|
|
8002392: 2000 movs r0, #0
|
|
8002394: f001 ffd6 bl 8004344 <HW_TS_Init>
|
|
|
|
/* USER CODE BEGIN APPE_Init_1 */
|
|
|
|
/* USER CODE END APPE_Init_1 */
|
|
appe_Tl_Init(); /* Initialize all transport layers */
|
|
8002398: f000 f856 bl 8002448 <appe_Tl_Init>
|
|
*/
|
|
/* USER CODE BEGIN APPE_Init_2 */
|
|
|
|
/* USER CODE END APPE_Init_2 */
|
|
|
|
return;
|
|
800239c: bf00 nop
|
|
}
|
|
800239e: bd80 pop {r7, pc}
|
|
80023a0: 20000504 .word 0x20000504
|
|
|
|
080023a4 <Init_Smps>:
|
|
|
|
void Init_Smps(void)
|
|
{
|
|
80023a4: b480 push {r7}
|
|
80023a6: af00 add r7, sp, #0
|
|
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
|
|
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
|
|
LL_PWR_SMPS_Enable();
|
|
#endif /* CFG_USE_SMPS != 0 */
|
|
|
|
return;
|
|
80023a8: bf00 nop
|
|
}
|
|
80023aa: 46bd mov sp, r7
|
|
80023ac: f85d 7b04 ldr.w r7, [sp], #4
|
|
80023b0: 4770 bx lr
|
|
|
|
080023b2 <Init_Exti>:
|
|
|
|
void Init_Exti(void)
|
|
{
|
|
80023b2: b580 push {r7, lr}
|
|
80023b4: af00 add r7, sp, #0
|
|
/* Enable IPCC(36), HSEM(38) wakeup interrupts on CPU1 */
|
|
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_36 | LL_EXTI_LINE_38);
|
|
80023b6: 2050 movs r0, #80 @ 0x50
|
|
80023b8: f7ff ff44 bl 8002244 <LL_EXTI_EnableIT_32_63>
|
|
|
|
return;
|
|
80023bc: bf00 nop
|
|
}
|
|
80023be: bd80 pop {r7, pc}
|
|
|
|
080023c0 <Reset_Device>:
|
|
*
|
|
* LOCAL FUNCTIONS
|
|
*
|
|
*************************************************************/
|
|
static void Reset_Device(void)
|
|
{
|
|
80023c0: b480 push {r7}
|
|
80023c2: af00 add r7, sp, #0
|
|
Reset_BackupDomain();
|
|
|
|
Reset_IPCC();
|
|
#endif /* CFG_HW_RESET_BY_FW == 1 */
|
|
|
|
return;
|
|
80023c4: bf00 nop
|
|
}
|
|
80023c6: 46bd mov sp, r7
|
|
80023c8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80023cc: 4770 bx lr
|
|
|
|
080023ce <Config_HSE>:
|
|
return;
|
|
}
|
|
#endif /* CFG_HW_RESET_BY_FW == 1 */
|
|
|
|
static void Config_HSE(void)
|
|
{
|
|
80023ce: b580 push {r7, lr}
|
|
80023d0: b082 sub sp, #8
|
|
80023d2: af00 add r7, sp, #0
|
|
OTP_ID0_t * p_otp;
|
|
|
|
/**
|
|
* Read HSE_Tuning from OTP
|
|
*/
|
|
p_otp = (OTP_ID0_t *) OTP_Read(0);
|
|
80023d4: 2000 movs r0, #0
|
|
80023d6: f011 f92d bl 8013634 <OTP_Read>
|
|
80023da: 6078 str r0, [r7, #4]
|
|
if (p_otp)
|
|
80023dc: 687b ldr r3, [r7, #4]
|
|
80023de: 2b00 cmp r3, #0
|
|
80023e0: d005 beq.n 80023ee <Config_HSE+0x20>
|
|
{
|
|
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
|
|
80023e2: 687b ldr r3, [r7, #4]
|
|
80023e4: 799b ldrb r3, [r3, #6]
|
|
80023e6: 4618 mov r0, r3
|
|
80023e8: f7ff ff40 bl 800226c <LL_RCC_HSE_SetCapacitorTuning>
|
|
}
|
|
|
|
return;
|
|
80023ec: bf00 nop
|
|
80023ee: bf00 nop
|
|
}
|
|
80023f0: 3708 adds r7, #8
|
|
80023f2: 46bd mov sp, r7
|
|
80023f4: bd80 pop {r7, pc}
|
|
|
|
080023f6 <System_Init>:
|
|
|
|
static void System_Init(void)
|
|
{
|
|
80023f6: b580 push {r7, lr}
|
|
80023f8: af00 add r7, sp, #0
|
|
Init_Smps();
|
|
80023fa: f7ff ffd3 bl 80023a4 <Init_Smps>
|
|
|
|
Init_Exti();
|
|
80023fe: f7ff ffd8 bl 80023b2 <Init_Exti>
|
|
|
|
Init_Rtc();
|
|
8002402: f000 f803 bl 800240c <Init_Rtc>
|
|
|
|
return;
|
|
8002406: bf00 nop
|
|
}
|
|
8002408: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800240c <Init_Rtc>:
|
|
|
|
static void Init_Rtc(void)
|
|
{
|
|
800240c: b580 push {r7, lr}
|
|
800240e: af00 add r7, sp, #0
|
|
/* Disable RTC registers write protection */
|
|
LL_RTC_DisableWriteProtection(RTC);
|
|
8002410: 4805 ldr r0, [pc, #20] @ (8002428 <Init_Rtc+0x1c>)
|
|
8002412: f7ff ff86 bl 8002322 <LL_RTC_DisableWriteProtection>
|
|
|
|
LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
|
|
8002416: 2100 movs r1, #0
|
|
8002418: 4803 ldr r0, [pc, #12] @ (8002428 <Init_Rtc+0x1c>)
|
|
800241a: f7ff ff92 bl 8002342 <LL_RTC_WAKEUP_SetClock>
|
|
|
|
/* Enable RTC registers write protection */
|
|
LL_RTC_EnableWriteProtection(RTC);
|
|
800241e: 4802 ldr r0, [pc, #8] @ (8002428 <Init_Rtc+0x1c>)
|
|
8002420: f7ff ff72 bl 8002308 <LL_RTC_EnableWriteProtection>
|
|
|
|
return;
|
|
8002424: bf00 nop
|
|
}
|
|
8002426: bd80 pop {r7, pc}
|
|
8002428: 40002800 .word 0x40002800
|
|
|
|
0800242c <SystemPower_Config>:
|
|
*
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SystemPower_Config(void)
|
|
{
|
|
800242c: b580 push {r7, lr}
|
|
800242e: af00 add r7, sp, #0
|
|
/**
|
|
* Select HSI as system clock source after Wake Up from Stop mode
|
|
*/
|
|
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
|
|
8002430: f44f 4000 mov.w r0, #32768 @ 0x8000
|
|
8002434: f7ff ff38 bl 80022a8 <LL_RCC_SetClkAfterWakeFromStop>
|
|
|
|
/* Initialize low power manager */
|
|
UTIL_LPM_Init();
|
|
8002438: f016 ff7e bl 8019338 <UTIL_LPM_Init>
|
|
/* Initialize the CPU2 reset value before starting CPU2 with C2BOOT */
|
|
LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
|
|
800243c: 2004 movs r0, #4
|
|
800243e: f7ff feeb bl 8002218 <LL_C2_PWR_SetPowerMode>
|
|
* Enable USB power
|
|
*/
|
|
HAL_PWREx_EnableVddUSB();
|
|
#endif /* CFG_USB_INTERFACE_ENABLE != 0 */
|
|
|
|
return;
|
|
8002442: bf00 nop
|
|
}
|
|
8002444: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08002448 <appe_Tl_Init>:
|
|
|
|
static void appe_Tl_Init(void)
|
|
{
|
|
8002448: b580 push {r7, lr}
|
|
800244a: b088 sub sp, #32
|
|
800244c: af00 add r7, sp, #0
|
|
TL_MM_Config_t tl_mm_config;
|
|
SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
|
|
/**< Reference table initialization */
|
|
TL_Init();
|
|
800244e: f010 fef3 bl 8013238 <TL_Init>
|
|
|
|
MtxShciId = osMutexNew(NULL);
|
|
8002452: 2000 movs r0, #0
|
|
8002454: f011 fc05 bl 8013c62 <osMutexNew>
|
|
8002458: 4603 mov r3, r0
|
|
800245a: 4a17 ldr r2, [pc, #92] @ (80024b8 <appe_Tl_Init+0x70>)
|
|
800245c: 6013 str r3, [r2, #0]
|
|
SemShciId = osSemaphoreNew(1, 0, NULL); /*< Create the semaphore and make it busy at initialization */
|
|
800245e: 2200 movs r2, #0
|
|
8002460: 2100 movs r1, #0
|
|
8002462: 2001 movs r0, #1
|
|
8002464: f011 fd08 bl 8013e78 <osSemaphoreNew>
|
|
8002468: 4603 mov r3, r0
|
|
800246a: 4a14 ldr r2, [pc, #80] @ (80024bc <appe_Tl_Init+0x74>)
|
|
800246c: 6013 str r3, [r2, #0]
|
|
|
|
/** FreeRTOS system task creation */
|
|
ShciUserEvtProcessId = osThreadNew(ShciUserEvtProcess, NULL, &ShciUserEvtProcess_attr);
|
|
800246e: 4a14 ldr r2, [pc, #80] @ (80024c0 <appe_Tl_Init+0x78>)
|
|
8002470: 2100 movs r1, #0
|
|
8002472: 4814 ldr r0, [pc, #80] @ (80024c4 <appe_Tl_Init+0x7c>)
|
|
8002474: f011 fa7e bl 8013974 <osThreadNew>
|
|
8002478: 4603 mov r3, r0
|
|
800247a: 4a13 ldr r2, [pc, #76] @ (80024c8 <appe_Tl_Init+0x80>)
|
|
800247c: 6013 str r3, [r2, #0]
|
|
|
|
/**< System channel initialization */
|
|
SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
|
|
800247e: 4b13 ldr r3, [pc, #76] @ (80024cc <appe_Tl_Init+0x84>)
|
|
8002480: 603b str r3, [r7, #0]
|
|
SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
|
|
8002482: 4b13 ldr r3, [pc, #76] @ (80024d0 <appe_Tl_Init+0x88>)
|
|
8002484: 607b str r3, [r7, #4]
|
|
shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
|
|
8002486: 463b mov r3, r7
|
|
8002488: 4619 mov r1, r3
|
|
800248a: 4812 ldr r0, [pc, #72] @ (80024d4 <appe_Tl_Init+0x8c>)
|
|
800248c: f010 fd96 bl 8012fbc <shci_init>
|
|
|
|
/**< Memory Manager channel initialization */
|
|
tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
|
|
8002490: 4b11 ldr r3, [pc, #68] @ (80024d8 <appe_Tl_Init+0x90>)
|
|
8002492: 60bb str r3, [r7, #8]
|
|
tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
|
|
8002494: 4b11 ldr r3, [pc, #68] @ (80024dc <appe_Tl_Init+0x94>)
|
|
8002496: 60fb str r3, [r7, #12]
|
|
tl_mm_config.p_AsynchEvtPool = EvtPool;
|
|
8002498: 4b11 ldr r3, [pc, #68] @ (80024e0 <appe_Tl_Init+0x98>)
|
|
800249a: 613b str r3, [r7, #16]
|
|
tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
|
|
800249c: f240 533c movw r3, #1340 @ 0x53c
|
|
80024a0: 617b str r3, [r7, #20]
|
|
TL_MM_Init(&tl_mm_config);
|
|
80024a2: f107 0308 add.w r3, r7, #8
|
|
80024a6: 4618 mov r0, r3
|
|
80024a8: f010 ffbc bl 8013424 <TL_MM_Init>
|
|
|
|
TL_Enable();
|
|
80024ac: f010 febe bl 801322c <TL_Enable>
|
|
|
|
return;
|
|
80024b0: bf00 nop
|
|
}
|
|
80024b2: 3720 adds r7, #32
|
|
80024b4: 46bd mov sp, r7
|
|
80024b6: bd80 pop {r7, pc}
|
|
80024b8: 20000308 .word 0x20000308
|
|
80024bc: 2000030c .word 0x2000030c
|
|
80024c0: 0801e4ac .word 0x0801e4ac
|
|
80024c4: 08002647 .word 0x08002647
|
|
80024c8: 20000310 .word 0x20000310
|
|
80024cc: 20030628 .word 0x20030628
|
|
80024d0: 080024f5 .word 0x080024f5
|
|
80024d4: 08002535 .word 0x08002535
|
|
80024d8: 20030840 .word 0x20030840
|
|
80024dc: 20030734 .word 0x20030734
|
|
80024e0: 200300ec .word 0x200300ec
|
|
|
|
080024e4 <APP_BLE_Init>:
|
|
|
|
__WEAK void APP_BLE_Init(void)
|
|
{
|
|
80024e4: b480 push {r7}
|
|
80024e6: af00 add r7, sp, #0
|
|
}
|
|
80024e8: bf00 nop
|
|
80024ea: 46bd mov sp, r7
|
|
80024ec: f85d 7b04 ldr.w r7, [sp], #4
|
|
80024f0: 4770 bx lr
|
|
...
|
|
|
|
080024f4 <APPE_SysStatusNot>:
|
|
|
|
static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status)
|
|
{
|
|
80024f4: b580 push {r7, lr}
|
|
80024f6: b082 sub sp, #8
|
|
80024f8: af00 add r7, sp, #0
|
|
80024fa: 4603 mov r3, r0
|
|
80024fc: 71fb strb r3, [r7, #7]
|
|
switch (status)
|
|
80024fe: 79fb ldrb r3, [r7, #7]
|
|
8002500: 2b00 cmp r3, #0
|
|
8002502: d002 beq.n 800250a <APPE_SysStatusNot+0x16>
|
|
8002504: 2b01 cmp r3, #1
|
|
8002506: d008 beq.n 800251a <APPE_SysStatusNot+0x26>
|
|
case SHCI_TL_CmdAvailable:
|
|
osMutexRelease(MtxShciId);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
8002508: e00d b.n 8002526 <APPE_SysStatusNot+0x32>
|
|
osMutexAcquire(MtxShciId, osWaitForever);
|
|
800250a: 4b09 ldr r3, [pc, #36] @ (8002530 <APPE_SysStatusNot+0x3c>)
|
|
800250c: 681b ldr r3, [r3, #0]
|
|
800250e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8002512: 4618 mov r0, r3
|
|
8002514: f011 fc2a bl 8013d6c <osMutexAcquire>
|
|
break;
|
|
8002518: e005 b.n 8002526 <APPE_SysStatusNot+0x32>
|
|
osMutexRelease(MtxShciId);
|
|
800251a: 4b05 ldr r3, [pc, #20] @ (8002530 <APPE_SysStatusNot+0x3c>)
|
|
800251c: 681b ldr r3, [r3, #0]
|
|
800251e: 4618 mov r0, r3
|
|
8002520: f011 fc6e bl 8013e00 <osMutexRelease>
|
|
break;
|
|
8002524: bf00 nop
|
|
}
|
|
return;
|
|
8002526: bf00 nop
|
|
}
|
|
8002528: 3708 adds r7, #8
|
|
800252a: 46bd mov sp, r7
|
|
800252c: bd80 pop {r7, pc}
|
|
800252e: bf00 nop
|
|
8002530: 20000308 .word 0x20000308
|
|
|
|
08002534 <APPE_SysUserEvtRx>:
|
|
* The buffer shall not be released
|
|
* (eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable)
|
|
* When the status is not filled, the buffer is released by default
|
|
*/
|
|
static void APPE_SysUserEvtRx(void * pPayload)
|
|
{
|
|
8002534: b580 push {r7, lr}
|
|
8002536: b088 sub sp, #32
|
|
8002538: af00 add r7, sp, #0
|
|
800253a: 6078 str r0, [r7, #4]
|
|
TL_AsynchEvt_t *p_sys_event;
|
|
WirelessFwInfo_t WirelessInfo;
|
|
|
|
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
|
|
800253c: 687b ldr r3, [r7, #4]
|
|
800253e: 685b ldr r3, [r3, #4]
|
|
8002540: 330b adds r3, #11
|
|
8002542: 61fb str r3, [r7, #28]
|
|
|
|
switch(p_sys_event->subevtcode)
|
|
8002544: 69fb ldr r3, [r7, #28]
|
|
8002546: 881b ldrh r3, [r3, #0]
|
|
8002548: b29b uxth r3, r3
|
|
800254a: f5a3 4312 sub.w r3, r3, #37376 @ 0x9200
|
|
800254e: 2b07 cmp r3, #7
|
|
8002550: d81f bhi.n 8002592 <APPE_SysUserEvtRx+0x5e>
|
|
8002552: a201 add r2, pc, #4 @ (adr r2, 8002558 <APPE_SysUserEvtRx+0x24>)
|
|
8002554: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8002558: 08002579 .word 0x08002579
|
|
800255c: 0800258b .word 0x0800258b
|
|
8002560: 08002593 .word 0x08002593
|
|
8002564: 08002593 .word 0x08002593
|
|
8002568: 08002593 .word 0x08002593
|
|
800256c: 08002593 .word 0x08002593
|
|
8002570: 08002593 .word 0x08002593
|
|
8002574: 08002593 .word 0x08002593
|
|
{
|
|
case SHCI_SUB_EVT_CODE_READY:
|
|
/* Read the firmware version of both the wireless firmware and the FUS */
|
|
SHCI_GetWirelessFwInfo(&WirelessInfo);
|
|
8002578: f107 030c add.w r3, r7, #12
|
|
800257c: 4618 mov r0, r3
|
|
800257e: f010 fc6f bl 8012e60 <SHCI_GetWirelessFwInfo>
|
|
APP_DBG_MSG("Wireless Firmware version %d.%d.%d\n", WirelessInfo.VersionMajor, WirelessInfo.VersionMinor, WirelessInfo.VersionSub);
|
|
APP_DBG_MSG("Wireless Firmware build %d\n", WirelessInfo.VersionReleaseType);
|
|
APP_DBG_MSG("FUS version %d.%d.%d\n", WirelessInfo.FusVersionMajor, WirelessInfo.FusVersionMinor, WirelessInfo.FusVersionSub);
|
|
|
|
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY\n\r");
|
|
APPE_SysEvtReadyProcessing(pPayload);
|
|
8002582: 6878 ldr r0, [r7, #4]
|
|
8002584: f000 f81b bl 80025be <APPE_SysEvtReadyProcessing>
|
|
break;
|
|
8002588: e004 b.n 8002594 <APPE_SysUserEvtRx+0x60>
|
|
|
|
case SHCI_SUB_EVT_ERROR_NOTIF:
|
|
APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF \n\r");
|
|
APPE_SysEvtError(pPayload);
|
|
800258a: 6878 ldr r0, [r7, #4]
|
|
800258c: f000 f806 bl 800259c <APPE_SysEvtError>
|
|
break;
|
|
8002590: e000 b.n 8002594 <APPE_SysUserEvtRx+0x60>
|
|
case SHCI_SUB_EVT_NVM_END_ERASE:
|
|
APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_ERASE\n\r");
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
8002592: bf00 nop
|
|
}
|
|
|
|
return;
|
|
8002594: bf00 nop
|
|
}
|
|
8002596: 3720 adds r7, #32
|
|
8002598: 46bd mov sp, r7
|
|
800259a: bd80 pop {r7, pc}
|
|
|
|
0800259c <APPE_SysEvtError>:
|
|
* @param ErrorCode : errorCode detected by the M0 firmware
|
|
*
|
|
* @retval None
|
|
*/
|
|
static void APPE_SysEvtError(void * pPayload)
|
|
{
|
|
800259c: b480 push {r7}
|
|
800259e: b085 sub sp, #20
|
|
80025a0: af00 add r7, sp, #0
|
|
80025a2: 6078 str r0, [r7, #4]
|
|
TL_AsynchEvt_t *p_sys_event;
|
|
SCHI_SystemErrCode_t *p_sys_error_code;
|
|
|
|
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
|
|
80025a4: 687b ldr r3, [r7, #4]
|
|
80025a6: 685b ldr r3, [r3, #4]
|
|
80025a8: 330b adds r3, #11
|
|
80025aa: 60fb str r3, [r7, #12]
|
|
p_sys_error_code = (SCHI_SystemErrCode_t*) p_sys_event->payload;
|
|
80025ac: 68fb ldr r3, [r7, #12]
|
|
80025ae: 3302 adds r3, #2
|
|
80025b0: 60bb str r3, [r7, #8]
|
|
}
|
|
else
|
|
{
|
|
APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - BLE ERROR \n");
|
|
}
|
|
return;
|
|
80025b2: bf00 nop
|
|
}
|
|
80025b4: 3714 adds r7, #20
|
|
80025b6: 46bd mov sp, r7
|
|
80025b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80025bc: 4770 bx lr
|
|
|
|
080025be <APPE_SysEvtReadyProcessing>:
|
|
|
|
static void APPE_SysEvtReadyProcessing(void * pPayload)
|
|
{
|
|
80025be: b580 push {r7, lr}
|
|
80025c0: b08a sub sp, #40 @ 0x28
|
|
80025c2: af00 add r7, sp, #0
|
|
80025c4: 6078 str r0, [r7, #4]
|
|
TL_AsynchEvt_t *p_sys_event;
|
|
SHCI_C2_Ready_Evt_t *p_sys_ready_event;
|
|
|
|
SHCI_C2_CONFIG_Cmd_Param_t config_param = {0};
|
|
80025c6: f107 0308 add.w r3, r7, #8
|
|
80025ca: 2200 movs r2, #0
|
|
80025cc: 601a str r2, [r3, #0]
|
|
80025ce: 605a str r2, [r3, #4]
|
|
80025d0: 609a str r2, [r3, #8]
|
|
80025d2: 60da str r2, [r3, #12]
|
|
uint32_t RevisionID=0;
|
|
80025d4: 2300 movs r3, #0
|
|
80025d6: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t DeviceID=0;
|
|
80025d8: 2300 movs r3, #0
|
|
80025da: 623b str r3, [r7, #32]
|
|
|
|
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
|
|
80025dc: 687b ldr r3, [r7, #4]
|
|
80025de: 685b ldr r3, [r3, #4]
|
|
80025e0: 330b adds r3, #11
|
|
80025e2: 61fb str r3, [r7, #28]
|
|
p_sys_ready_event = (SHCI_C2_Ready_Evt_t*) p_sys_event->payload;
|
|
80025e4: 69fb ldr r3, [r7, #28]
|
|
80025e6: 3302 adds r3, #2
|
|
80025e8: 61bb str r3, [r7, #24]
|
|
|
|
if (p_sys_ready_event->sysevt_ready_rsp == WIRELESS_FW_RUNNING)
|
|
80025ea: 69bb ldr r3, [r7, #24]
|
|
80025ec: 781b ldrb r3, [r3, #0]
|
|
80025ee: 2b00 cmp r3, #0
|
|
80025f0: d11d bne.n 800262e <APPE_SysEvtReadyProcessing+0x70>
|
|
* The wireless firmware is running on the CPU2
|
|
*/
|
|
APP_DBG_MSG(">>== WIRELESS_FW_RUNNING \n");
|
|
|
|
/* Traces channel initialization */
|
|
APPD_EnableCPU2();
|
|
80025f2: f7ff fdf5 bl 80021e0 <APPD_EnableCPU2>
|
|
|
|
/* Enable all events Notification */
|
|
config_param.PayloadCmdSize = SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE;
|
|
80025f6: 230f movs r3, #15
|
|
80025f8: 723b strb r3, [r7, #8]
|
|
config_param.EvtMask1 = SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE
|
|
80025fa: 237f movs r3, #127 @ 0x7f
|
|
80025fc: 72bb strb r3, [r7, #10]
|
|
* @brief Return the device revision identifier
|
|
* @note This field indicates the revision of the device.
|
|
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
|
|
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
|
|
*/
|
|
RevisionID = LL_DBGMCU_GetRevisionID();
|
|
80025fe: f7ff fe75 bl 80022ec <LL_DBGMCU_GetRevisionID>
|
|
8002602: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
APP_DBG_MSG(">>== DBGMCU_GetRevisionID= %lx \n\r", RevisionID);
|
|
|
|
config_param.RevisionID = (uint16_t)RevisionID;
|
|
8002604: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002606: b29b uxth r3, r3
|
|
8002608: 82bb strh r3, [r7, #20]
|
|
|
|
DeviceID = LL_DBGMCU_GetDeviceID();
|
|
800260a: f7ff fe61 bl 80022d0 <LL_DBGMCU_GetDeviceID>
|
|
800260e: 6238 str r0, [r7, #32]
|
|
APP_DBG_MSG(">>== DBGMCU_GetDeviceID= %lx \n\r", DeviceID);
|
|
config_param.DeviceID = (uint16_t)DeviceID;
|
|
8002610: 6a3b ldr r3, [r7, #32]
|
|
8002612: b29b uxth r3, r3
|
|
8002614: 82fb strh r3, [r7, #22]
|
|
(void)SHCI_C2_Config(&config_param);
|
|
8002616: f107 0308 add.w r3, r7, #8
|
|
800261a: 4618 mov r0, r3
|
|
800261c: f010 fc0a bl 8012e34 <SHCI_C2_Config>
|
|
|
|
APP_BLE_Init();
|
|
8002620: f7ff ff60 bl 80024e4 <APP_BLE_Init>
|
|
UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
|
|
8002624: 2100 movs r1, #0
|
|
8002626: 2001 movs r0, #1
|
|
8002628: f016 fe98 bl 801935c <UTIL_LPM_SetOffMode>
|
|
else
|
|
{
|
|
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - UNEXPECTED CASE \n\r");
|
|
}
|
|
|
|
return;
|
|
800262c: e007 b.n 800263e <APPE_SysEvtReadyProcessing+0x80>
|
|
else if (p_sys_ready_event->sysevt_ready_rsp == FUS_FW_RUNNING)
|
|
800262e: 69bb ldr r3, [r7, #24]
|
|
8002630: 781b ldrb r3, [r3, #0]
|
|
8002632: 2b01 cmp r3, #1
|
|
8002634: d103 bne.n 800263e <APPE_SysEvtReadyProcessing+0x80>
|
|
((tSHCI_UserEvtRxParam*)pPayload)->status = SHCI_TL_UserEventFlow_Disable;
|
|
8002636: 687b ldr r3, [r7, #4]
|
|
8002638: 2200 movs r2, #0
|
|
800263a: 701a strb r2, [r3, #0]
|
|
return;
|
|
800263c: bf00 nop
|
|
800263e: bf00 nop
|
|
}
|
|
8002640: 3728 adds r7, #40 @ 0x28
|
|
8002642: 46bd mov sp, r7
|
|
8002644: bd80 pop {r7, pc}
|
|
|
|
08002646 <ShciUserEvtProcess>:
|
|
*
|
|
* FREERTOS WRAPPER FUNCTIONS
|
|
*
|
|
*************************************************************/
|
|
static void ShciUserEvtProcess(void *argument)
|
|
{
|
|
8002646: b580 push {r7, lr}
|
|
8002648: b082 sub sp, #8
|
|
800264a: af00 add r7, sp, #0
|
|
800264c: 6078 str r0, [r7, #4]
|
|
for(;;)
|
|
{
|
|
/* USER CODE BEGIN SHCI_USER_EVT_PROCESS_1 */
|
|
|
|
/* USER CODE END SHCI_USER_EVT_PROCESS_1 */
|
|
osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever);
|
|
800264e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8002652: 2100 movs r1, #0
|
|
8002654: 2001 movs r0, #1
|
|
8002656: f011 fa81 bl 8013b5c <osThreadFlagsWait>
|
|
shci_user_evt_proc();
|
|
800265a: f010 fccb bl 8012ff4 <shci_user_evt_proc>
|
|
osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever);
|
|
800265e: bf00 nop
|
|
8002660: e7f5 b.n 800264e <ShciUserEvtProcess+0x8>
|
|
...
|
|
|
|
08002664 <shci_notify_asynch_evt>:
|
|
__WFI();
|
|
}
|
|
}
|
|
|
|
void shci_notify_asynch_evt(void* pdata)
|
|
{
|
|
8002664: b580 push {r7, lr}
|
|
8002666: b082 sub sp, #8
|
|
8002668: af00 add r7, sp, #0
|
|
800266a: 6078 str r0, [r7, #4]
|
|
UNUSED(pdata);
|
|
osThreadFlagsSet(ShciUserEvtProcessId, 1);
|
|
800266c: 4b04 ldr r3, [pc, #16] @ (8002680 <shci_notify_asynch_evt+0x1c>)
|
|
800266e: 681b ldr r3, [r3, #0]
|
|
8002670: 2101 movs r1, #1
|
|
8002672: 4618 mov r0, r3
|
|
8002674: f011 fa1c bl 8013ab0 <osThreadFlagsSet>
|
|
return;
|
|
8002678: bf00 nop
|
|
}
|
|
800267a: 3708 adds r7, #8
|
|
800267c: 46bd mov sp, r7
|
|
800267e: bd80 pop {r7, pc}
|
|
8002680: 20000310 .word 0x20000310
|
|
|
|
08002684 <shci_cmd_resp_release>:
|
|
|
|
void shci_cmd_resp_release(uint32_t flag)
|
|
{
|
|
8002684: b580 push {r7, lr}
|
|
8002686: b082 sub sp, #8
|
|
8002688: af00 add r7, sp, #0
|
|
800268a: 6078 str r0, [r7, #4]
|
|
UNUSED(flag);
|
|
osSemaphoreRelease(SemShciId);
|
|
800268c: 4b04 ldr r3, [pc, #16] @ (80026a0 <shci_cmd_resp_release+0x1c>)
|
|
800268e: 681b ldr r3, [r3, #0]
|
|
8002690: 4618 mov r0, r3
|
|
8002692: f011 fcc9 bl 8014028 <osSemaphoreRelease>
|
|
return;
|
|
8002696: bf00 nop
|
|
}
|
|
8002698: 3708 adds r7, #8
|
|
800269a: 46bd mov sp, r7
|
|
800269c: bd80 pop {r7, pc}
|
|
800269e: bf00 nop
|
|
80026a0: 2000030c .word 0x2000030c
|
|
|
|
080026a4 <shci_cmd_resp_wait>:
|
|
|
|
void shci_cmd_resp_wait(uint32_t timeout)
|
|
{
|
|
80026a4: b580 push {r7, lr}
|
|
80026a6: b082 sub sp, #8
|
|
80026a8: af00 add r7, sp, #0
|
|
80026aa: 6078 str r0, [r7, #4]
|
|
UNUSED(timeout);
|
|
osSemaphoreAcquire(SemShciId, osWaitForever);
|
|
80026ac: 4b05 ldr r3, [pc, #20] @ (80026c4 <shci_cmd_resp_wait+0x20>)
|
|
80026ae: 681b ldr r3, [r3, #0]
|
|
80026b0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80026b4: 4618 mov r0, r3
|
|
80026b6: f011 fc67 bl 8013f88 <osSemaphoreAcquire>
|
|
return;
|
|
80026ba: bf00 nop
|
|
}
|
|
80026bc: 3708 adds r7, #8
|
|
80026be: 46bd mov sp, r7
|
|
80026c0: bd80 pop {r7, pc}
|
|
80026c2: bf00 nop
|
|
80026c4: 2000030c .word 0x2000030c
|
|
|
|
080026c8 <vApplicationStackOverflowHook>:
|
|
/* Hook prototypes */
|
|
void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName);
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName)
|
|
{
|
|
80026c8: b480 push {r7}
|
|
80026ca: b083 sub sp, #12
|
|
80026cc: af00 add r7, sp, #0
|
|
80026ce: 6078 str r0, [r7, #4]
|
|
80026d0: 6039 str r1, [r7, #0]
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80026d2: b672 cpsid i
|
|
}
|
|
80026d4: bf00 nop
|
|
/* Run time stack overflow checking is performed if
|
|
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
|
|
called if a stack overflow is detected. */
|
|
__disable_irq();
|
|
for (;;) { } // breakpoint here
|
|
80026d6: bf00 nop
|
|
80026d8: e7fd b.n 80026d6 <vApplicationStackOverflowHook+0xe>
|
|
|
|
080026da <bmm350_init>:
|
|
|
|
/*!
|
|
* @brief This API is the entry point. Call this API before using other APIs.
|
|
*/
|
|
int8_t bmm350_init(struct bmm350_dev *dev)
|
|
{
|
|
80026da: b580 push {r7, lr}
|
|
80026dc: b084 sub sp, #16
|
|
80026de: af00 add r7, sp, #0
|
|
80026e0: 6078 str r0, [r7, #4]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
/* Variable to get chip id */
|
|
uint8_t chip_id = BMM350_DISABLE;
|
|
80026e2: 2300 movs r3, #0
|
|
80026e4: 73bb strb r3, [r7, #14]
|
|
|
|
/* Variable to store the command to power-off the OTP */
|
|
uint8_t otp_cmd = BMM350_OTP_CMD_PWR_OFF_OTP;
|
|
80026e6: 2380 movs r3, #128 @ 0x80
|
|
80026e8: 737b strb r3, [r7, #13]
|
|
|
|
/* Variable to store soft-reset command */
|
|
uint8_t soft_reset;
|
|
|
|
/* Check for null pointer in the device structure */
|
|
rslt = null_ptr_check(dev);
|
|
80026ea: 6878 ldr r0, [r7, #4]
|
|
80026ec: f000 fd8a bl 8003204 <null_ptr_check>
|
|
80026f0: 4603 mov r3, r0
|
|
80026f2: 73fb strb r3, [r7, #15]
|
|
|
|
/* Proceed if null check is fine */
|
|
if (rslt == BMM350_OK)
|
|
80026f4: f997 300f ldrsb.w r3, [r7, #15]
|
|
80026f8: 2b00 cmp r3, #0
|
|
80026fa: d173 bne.n 80027e4 <bmm350_init+0x10a>
|
|
{
|
|
dev->chip_id = 0;
|
|
80026fc: 687b ldr r3, [r7, #4]
|
|
80026fe: 2200 movs r2, #0
|
|
8002700: 711a strb r2, [r3, #4]
|
|
|
|
/* Assign axis_en with all axis enabled (BMM350_EN_XYZ_MSK) */
|
|
dev->axis_en = BMM350_EN_XYZ_MSK;
|
|
8002702: 687b ldr r3, [r7, #4]
|
|
8002704: 2207 movs r2, #7
|
|
8002706: 755a strb r2, [r3, #21]
|
|
|
|
rslt = bmm350_delay_us(BMM350_START_UP_TIME_FROM_POR, dev);
|
|
8002708: 6879 ldr r1, [r7, #4]
|
|
800270a: f640 30b8 movw r0, #3000 @ 0xbb8
|
|
800270e: f000 f8f8 bl 8002902 <bmm350_delay_us>
|
|
8002712: 4603 mov r3, r0
|
|
8002714: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002716: f997 300f ldrsb.w r3, [r7, #15]
|
|
800271a: 2b00 cmp r3, #0
|
|
800271c: d115 bne.n 800274a <bmm350_init+0x70>
|
|
{
|
|
/* Soft-reset */
|
|
soft_reset = BMM350_CMD_SOFTRESET;
|
|
800271e: 23b6 movs r3, #182 @ 0xb6
|
|
8002720: 733b strb r3, [r7, #12]
|
|
|
|
/* Set the command in the command register */
|
|
rslt = bmm350_set_regs(BMM350_REG_CMD, &soft_reset, 1, dev);
|
|
8002722: f107 010c add.w r1, r7, #12
|
|
8002726: 687b ldr r3, [r7, #4]
|
|
8002728: 2201 movs r2, #1
|
|
800272a: 207e movs r0, #126 @ 0x7e
|
|
800272c: f000 f860 bl 80027f0 <bmm350_set_regs>
|
|
8002730: 4603 mov r3, r0
|
|
8002732: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002734: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002738: 2b00 cmp r3, #0
|
|
800273a: d106 bne.n 800274a <bmm350_init+0x70>
|
|
{
|
|
rslt = bmm350_delay_us(BMM350_SOFT_RESET_DELAY, dev);
|
|
800273c: 6879 ldr r1, [r7, #4]
|
|
800273e: f645 50c0 movw r0, #24000 @ 0x5dc0
|
|
8002742: f000 f8de bl 8002902 <bmm350_delay_us>
|
|
8002746: 4603 mov r3, r0
|
|
8002748: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
|
|
if (rslt == BMM350_OK)
|
|
800274a: f997 300f ldrsb.w r3, [r7, #15]
|
|
800274e: 2b00 cmp r3, #0
|
|
8002750: d10f bne.n 8002772 <bmm350_init+0x98>
|
|
{
|
|
/* Chip ID of the sensor is read */
|
|
rslt = bmm350_get_regs(BMM350_REG_CHIP_ID, &chip_id, 1, dev);
|
|
8002752: f107 010e add.w r1, r7, #14
|
|
8002756: 687b ldr r3, [r7, #4]
|
|
8002758: 2201 movs r2, #1
|
|
800275a: 2000 movs r0, #0
|
|
800275c: f000 f87c bl 8002858 <bmm350_get_regs>
|
|
8002760: 4603 mov r3, r0
|
|
8002762: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002764: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002768: 2b00 cmp r3, #0
|
|
800276a: d102 bne.n 8002772 <bmm350_init+0x98>
|
|
{
|
|
/* Assign chip_id to dev->chip_id */
|
|
dev->chip_id = chip_id;
|
|
800276c: 7bba ldrb r2, [r7, #14]
|
|
800276e: 687b ldr r3, [r7, #4]
|
|
8002770: 711a strb r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* Check for chip id validity */
|
|
if ((rslt == BMM350_OK) && (dev->chip_id == BMM350_CHIP_ID))
|
|
8002772: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002776: 2b00 cmp r3, #0
|
|
8002778: d130 bne.n 80027dc <bmm350_init+0x102>
|
|
800277a: 687b ldr r3, [r7, #4]
|
|
800277c: 791b ldrb r3, [r3, #4]
|
|
800277e: 2b33 cmp r3, #51 @ 0x33
|
|
8002780: d12c bne.n 80027dc <bmm350_init+0x102>
|
|
{
|
|
/* Download OTP memory */
|
|
rslt = otp_dump_after_boot(dev);
|
|
8002782: 6878 ldr r0, [r7, #4]
|
|
8002784: f001 f910 bl 80039a8 <otp_dump_after_boot>
|
|
8002788: 4603 mov r3, r0
|
|
800278a: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
800278c: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002790: 2b00 cmp r3, #0
|
|
8002792: d126 bne.n 80027e2 <bmm350_init+0x108>
|
|
{
|
|
/* Power off OTP */
|
|
rslt = bmm350_set_regs(BMM350_REG_OTP_CMD_REG, &otp_cmd, 1, dev);
|
|
8002794: f107 010d add.w r1, r7, #13
|
|
8002798: 687b ldr r3, [r7, #4]
|
|
800279a: 2201 movs r2, #1
|
|
800279c: 2050 movs r0, #80 @ 0x50
|
|
800279e: f000 f827 bl 80027f0 <bmm350_set_regs>
|
|
80027a2: 4603 mov r3, r0
|
|
80027a4: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
80027a6: f997 300f ldrsb.w r3, [r7, #15]
|
|
80027aa: 2b00 cmp r3, #0
|
|
80027ac: d119 bne.n 80027e2 <bmm350_init+0x108>
|
|
{
|
|
if (dev->boot_done_status != BMM350_BOOT_NOT_DONE)
|
|
80027ae: 687b ldr r3, [r7, #4]
|
|
80027b0: f893 30ac ldrb.w r3, [r3, #172] @ 0xac
|
|
80027b4: 2b00 cmp r3, #0
|
|
80027b6: d003 beq.n 80027c0 <bmm350_init+0xe6>
|
|
{
|
|
dev->boot_done_status = BMM350_BOOT_NOT_DONE;
|
|
80027b8: 687b ldr r3, [r7, #4]
|
|
80027ba: 2200 movs r2, #0
|
|
80027bc: f883 20ac strb.w r2, [r3, #172] @ 0xac
|
|
}
|
|
|
|
rslt = bmm350_magnetic_reset_and_wait(dev);
|
|
80027c0: 6878 ldr r0, [r7, #4]
|
|
80027c2: f000 fa98 bl 8002cf6 <bmm350_magnetic_reset_and_wait>
|
|
80027c6: 4603 mov r3, r0
|
|
80027c8: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
80027ca: f997 300f ldrsb.w r3, [r7, #15]
|
|
80027ce: 2b00 cmp r3, #0
|
|
80027d0: d107 bne.n 80027e2 <bmm350_init+0x108>
|
|
{
|
|
dev->boot_done_status = BMM350_BOOT_DONE;
|
|
80027d2: 687b ldr r3, [r7, #4]
|
|
80027d4: 2201 movs r2, #1
|
|
80027d6: f883 20ac strb.w r2, [r3, #172] @ 0xac
|
|
if (rslt == BMM350_OK)
|
|
80027da: e002 b.n 80027e2 <bmm350_init+0x108>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rslt = BMM350_E_DEV_NOT_FOUND;
|
|
80027dc: 23fd movs r3, #253 @ 0xfd
|
|
80027de: 73fb strb r3, [r7, #15]
|
|
80027e0: e000 b.n 80027e4 <bmm350_init+0x10a>
|
|
if (rslt == BMM350_OK)
|
|
80027e2: bf00 nop
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
80027e4: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
80027e8: 4618 mov r0, r3
|
|
80027ea: 3710 adds r7, #16
|
|
80027ec: 46bd mov sp, r7
|
|
80027ee: bd80 pop {r7, pc}
|
|
|
|
080027f0 <bmm350_set_regs>:
|
|
/*!
|
|
* @brief This API writes the given data to the register address
|
|
* of the sensor.
|
|
*/
|
|
int8_t bmm350_set_regs(uint8_t reg_addr, const uint8_t *reg_data, uint16_t len, struct bmm350_dev *dev)
|
|
{
|
|
80027f0: b590 push {r4, r7, lr}
|
|
80027f2: b087 sub sp, #28
|
|
80027f4: af00 add r7, sp, #0
|
|
80027f6: 60b9 str r1, [r7, #8]
|
|
80027f8: 607b str r3, [r7, #4]
|
|
80027fa: 4603 mov r3, r0
|
|
80027fc: 73fb strb r3, [r7, #15]
|
|
80027fe: 4613 mov r3, r2
|
|
8002800: 81bb strh r3, [r7, #12]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
/* Check for null pointer in the device structure */
|
|
rslt = null_ptr_check(dev);
|
|
8002802: 6878 ldr r0, [r7, #4]
|
|
8002804: f000 fcfe bl 8003204 <null_ptr_check>
|
|
8002808: 4603 mov r3, r0
|
|
800280a: 75fb strb r3, [r7, #23]
|
|
|
|
/* Proceed if null check is fine */
|
|
if ((rslt == BMM350_OK) && (reg_data != NULL) && (len != 0))
|
|
800280c: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002810: 2b00 cmp r3, #0
|
|
8002812: d119 bne.n 8002848 <bmm350_set_regs+0x58>
|
|
8002814: 68bb ldr r3, [r7, #8]
|
|
8002816: 2b00 cmp r3, #0
|
|
8002818: d016 beq.n 8002848 <bmm350_set_regs+0x58>
|
|
800281a: 89bb ldrh r3, [r7, #12]
|
|
800281c: 2b00 cmp r3, #0
|
|
800281e: d013 beq.n 8002848 <bmm350_set_regs+0x58>
|
|
{
|
|
/* Write the data to the reg_addr */
|
|
dev->intf_rslt = dev->write(reg_addr, reg_data, len, dev->intf_ptr);
|
|
8002820: 687b ldr r3, [r7, #4]
|
|
8002822: 68dc ldr r4, [r3, #12]
|
|
8002824: 89ba ldrh r2, [r7, #12]
|
|
8002826: 687b ldr r3, [r7, #4]
|
|
8002828: 681b ldr r3, [r3, #0]
|
|
800282a: 7bf8 ldrb r0, [r7, #15]
|
|
800282c: 68b9 ldr r1, [r7, #8]
|
|
800282e: 47a0 blx r4
|
|
8002830: 4603 mov r3, r0
|
|
8002832: 461a mov r2, r3
|
|
8002834: 687b ldr r3, [r7, #4]
|
|
8002836: 751a strb r2, [r3, #20]
|
|
|
|
if (dev->intf_rslt != BMM350_INTF_RET_SUCCESS)
|
|
8002838: 687b ldr r3, [r7, #4]
|
|
800283a: f993 3014 ldrsb.w r3, [r3, #20]
|
|
800283e: 2b00 cmp r3, #0
|
|
8002840: d004 beq.n 800284c <bmm350_set_regs+0x5c>
|
|
{
|
|
rslt = BMM350_E_COM_FAIL;
|
|
8002842: 23fe movs r3, #254 @ 0xfe
|
|
8002844: 75fb strb r3, [r7, #23]
|
|
if (dev->intf_rslt != BMM350_INTF_RET_SUCCESS)
|
|
8002846: e001 b.n 800284c <bmm350_set_regs+0x5c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rslt = BMM350_E_NULL_PTR;
|
|
8002848: 23ff movs r3, #255 @ 0xff
|
|
800284a: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return rslt;
|
|
800284c: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
8002850: 4618 mov r0, r3
|
|
8002852: 371c adds r7, #28
|
|
8002854: 46bd mov sp, r7
|
|
8002856: bd90 pop {r4, r7, pc}
|
|
|
|
08002858 <bmm350_get_regs>:
|
|
|
|
/*!
|
|
* @brief This API reads the data from the given register address of sensor.
|
|
*/
|
|
int8_t bmm350_get_regs(uint8_t reg_addr, uint8_t *reg_data, uint16_t len, struct bmm350_dev *dev)
|
|
{
|
|
8002858: b590 push {r4, r7, lr}
|
|
800285a: b0a7 sub sp, #156 @ 0x9c
|
|
800285c: af00 add r7, sp, #0
|
|
800285e: 60b9 str r1, [r7, #8]
|
|
8002860: 607b str r3, [r7, #4]
|
|
8002862: 4603 mov r3, r0
|
|
8002864: 73fb strb r3, [r7, #15]
|
|
8002866: 4613 mov r3, r2
|
|
8002868: 81bb strh r3, [r7, #12]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
/* Variable to define temporary length */
|
|
uint16_t temp_len = len + BMM350_DUMMY_BYTES;
|
|
800286a: 89bb ldrh r3, [r7, #12]
|
|
800286c: 3302 adds r3, #2
|
|
800286e: f8a7 3092 strh.w r3, [r7, #146] @ 0x92
|
|
|
|
/* Variable to define temporary buffer */
|
|
uint8_t temp_buf[BMM350_READ_BUFFER_LENGTH];
|
|
|
|
/* Variable to define loop */
|
|
uint16_t index = 0;
|
|
8002872: 2300 movs r3, #0
|
|
8002874: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
|
|
/* Check for null pointer in the device structure */
|
|
rslt = null_ptr_check(dev);
|
|
8002878: 6878 ldr r0, [r7, #4]
|
|
800287a: f000 fcc3 bl 8003204 <null_ptr_check>
|
|
800287e: 4603 mov r3, r0
|
|
8002880: f887 3097 strb.w r3, [r7, #151] @ 0x97
|
|
|
|
/* Proceed if null check is fine */
|
|
if ((rslt == BMM350_OK) && (reg_data != NULL))
|
|
8002884: f997 3097 ldrsb.w r3, [r7, #151] @ 0x97
|
|
8002888: 2b00 cmp r3, #0
|
|
800288a: d131 bne.n 80028f0 <bmm350_get_regs+0x98>
|
|
800288c: 68bb ldr r3, [r7, #8]
|
|
800288e: 2b00 cmp r3, #0
|
|
8002890: d02e beq.n 80028f0 <bmm350_get_regs+0x98>
|
|
{
|
|
/* Read the data from the reg_addr */
|
|
dev->intf_rslt = dev->read(reg_addr, temp_buf, temp_len, dev->intf_ptr);
|
|
8002892: 687b ldr r3, [r7, #4]
|
|
8002894: 689c ldr r4, [r3, #8]
|
|
8002896: f8b7 2092 ldrh.w r2, [r7, #146] @ 0x92
|
|
800289a: 687b ldr r3, [r7, #4]
|
|
800289c: 681b ldr r3, [r3, #0]
|
|
800289e: f107 0110 add.w r1, r7, #16
|
|
80028a2: 7bf8 ldrb r0, [r7, #15]
|
|
80028a4: 47a0 blx r4
|
|
80028a6: 4603 mov r3, r0
|
|
80028a8: 461a mov r2, r3
|
|
80028aa: 687b ldr r3, [r7, #4]
|
|
80028ac: 751a strb r2, [r3, #20]
|
|
|
|
if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS)
|
|
80028ae: 687b ldr r3, [r7, #4]
|
|
80028b0: f993 3014 ldrsb.w r3, [r3, #20]
|
|
80028b4: 2b00 cmp r3, #0
|
|
80028b6: d117 bne.n 80028e8 <bmm350_get_regs+0x90>
|
|
{
|
|
/* Copy data after dummy byte indices */
|
|
while (index < len)
|
|
80028b8: e010 b.n 80028dc <bmm350_get_regs+0x84>
|
|
{
|
|
reg_data[index] = temp_buf[index + BMM350_DUMMY_BYTES];
|
|
80028ba: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
80028be: 1c9a adds r2, r3, #2
|
|
80028c0: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
80028c4: 68b9 ldr r1, [r7, #8]
|
|
80028c6: 440b add r3, r1
|
|
80028c8: 3298 adds r2, #152 @ 0x98
|
|
80028ca: 443a add r2, r7
|
|
80028cc: f812 2c88 ldrb.w r2, [r2, #-136]
|
|
80028d0: 701a strb r2, [r3, #0]
|
|
index++;
|
|
80028d2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
80028d6: 3301 adds r3, #1
|
|
80028d8: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
while (index < len)
|
|
80028dc: f8b7 2094 ldrh.w r2, [r7, #148] @ 0x94
|
|
80028e0: 89bb ldrh r3, [r7, #12]
|
|
80028e2: 429a cmp r2, r3
|
|
80028e4: d3e9 bcc.n 80028ba <bmm350_get_regs+0x62>
|
|
if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS)
|
|
80028e6: e006 b.n 80028f6 <bmm350_get_regs+0x9e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rslt = BMM350_E_COM_FAIL;
|
|
80028e8: 23fe movs r3, #254 @ 0xfe
|
|
80028ea: f887 3097 strb.w r3, [r7, #151] @ 0x97
|
|
if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS)
|
|
80028ee: e002 b.n 80028f6 <bmm350_get_regs+0x9e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rslt = BMM350_E_NULL_PTR;
|
|
80028f0: 23ff movs r3, #255 @ 0xff
|
|
80028f2: f887 3097 strb.w r3, [r7, #151] @ 0x97
|
|
}
|
|
|
|
return rslt;
|
|
80028f6: f997 3097 ldrsb.w r3, [r7, #151] @ 0x97
|
|
}
|
|
80028fa: 4618 mov r0, r3
|
|
80028fc: 379c adds r7, #156 @ 0x9c
|
|
80028fe: 46bd mov sp, r7
|
|
8002900: bd90 pop {r4, r7, pc}
|
|
|
|
08002902 <bmm350_delay_us>:
|
|
/*!
|
|
* @brief This function provides the delay for required time (Microsecond) as per the input provided in some of the
|
|
* APIs.
|
|
*/
|
|
int8_t bmm350_delay_us(uint32_t period_us, const struct bmm350_dev *dev)
|
|
{
|
|
8002902: b580 push {r7, lr}
|
|
8002904: b084 sub sp, #16
|
|
8002906: af00 add r7, sp, #0
|
|
8002908: 6078 str r0, [r7, #4]
|
|
800290a: 6039 str r1, [r7, #0]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
/* Check for null pointer in the device structure */
|
|
rslt = null_ptr_check(dev);
|
|
800290c: 6838 ldr r0, [r7, #0]
|
|
800290e: f000 fc79 bl 8003204 <null_ptr_check>
|
|
8002912: 4603 mov r3, r0
|
|
8002914: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002916: f997 300f ldrsb.w r3, [r7, #15]
|
|
800291a: 2b00 cmp r3, #0
|
|
800291c: d106 bne.n 800292c <bmm350_delay_us+0x2a>
|
|
{
|
|
dev->delay_us(period_us, dev->intf_ptr);
|
|
800291e: 683b ldr r3, [r7, #0]
|
|
8002920: 691b ldr r3, [r3, #16]
|
|
8002922: 683a ldr r2, [r7, #0]
|
|
8002924: 6812 ldr r2, [r2, #0]
|
|
8002926: 4611 mov r1, r2
|
|
8002928: 6878 ldr r0, [r7, #4]
|
|
800292a: 4798 blx r3
|
|
}
|
|
|
|
return rslt;
|
|
800292c: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8002930: 4618 mov r0, r3
|
|
8002932: 3710 adds r7, #16
|
|
8002934: 46bd mov sp, r7
|
|
8002936: bd80 pop {r7, pc}
|
|
|
|
08002938 <bmm350_set_powermode>:
|
|
|
|
/*!
|
|
* @brief This API is used to set the power mode of the sensor
|
|
*/
|
|
int8_t bmm350_set_powermode(enum bmm350_power_modes powermode, struct bmm350_dev *dev)
|
|
{
|
|
8002938: b580 push {r7, lr}
|
|
800293a: b084 sub sp, #16
|
|
800293c: af00 add r7, sp, #0
|
|
800293e: 4603 mov r3, r0
|
|
8002940: 6039 str r1, [r7, #0]
|
|
8002942: 71fb strb r3, [r7, #7]
|
|
|
|
uint8_t last_pwr_mode;
|
|
uint8_t reg_data;
|
|
|
|
/* Check for null pointer in the device structure */
|
|
rslt = null_ptr_check(dev);
|
|
8002944: 6838 ldr r0, [r7, #0]
|
|
8002946: f000 fc5d bl 8003204 <null_ptr_check>
|
|
800294a: 4603 mov r3, r0
|
|
800294c: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
800294e: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002952: 2b00 cmp r3, #0
|
|
8002954: d13c bne.n 80029d0 <bmm350_set_powermode+0x98>
|
|
{
|
|
rslt = bmm350_get_regs(BMM350_REG_PMU_CMD, &last_pwr_mode, 1, dev);
|
|
8002956: f107 010e add.w r1, r7, #14
|
|
800295a: 683b ldr r3, [r7, #0]
|
|
800295c: 2201 movs r2, #1
|
|
800295e: 2006 movs r0, #6
|
|
8002960: f7ff ff7a bl 8002858 <bmm350_get_regs>
|
|
8002964: 4603 mov r3, r0
|
|
8002966: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002968: f997 300f ldrsb.w r3, [r7, #15]
|
|
800296c: 2b00 cmp r3, #0
|
|
800296e: d12f bne.n 80029d0 <bmm350_set_powermode+0x98>
|
|
{
|
|
if (last_pwr_mode > BMM350_PMU_CMD_BR_FAST)
|
|
8002970: 7bbb ldrb r3, [r7, #14]
|
|
8002972: 2b08 cmp r3, #8
|
|
8002974: d901 bls.n 800297a <bmm350_set_powermode+0x42>
|
|
{
|
|
rslt = BMM350_E_INVALID_CONFIG;
|
|
8002976: 23fc movs r3, #252 @ 0xfc
|
|
8002978: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if ((rslt == BMM350_OK) &&
|
|
800297a: f997 300f ldrsb.w r3, [r7, #15]
|
|
800297e: 2b00 cmp r3, #0
|
|
8002980: d11b bne.n 80029ba <bmm350_set_powermode+0x82>
|
|
((last_pwr_mode == BMM350_PMU_CMD_NM) || (last_pwr_mode == BMM350_PMU_CMD_UPD_OAE)))
|
|
8002982: 7bbb ldrb r3, [r7, #14]
|
|
if ((rslt == BMM350_OK) &&
|
|
8002984: 2b01 cmp r3, #1
|
|
8002986: d002 beq.n 800298e <bmm350_set_powermode+0x56>
|
|
((last_pwr_mode == BMM350_PMU_CMD_NM) || (last_pwr_mode == BMM350_PMU_CMD_UPD_OAE)))
|
|
8002988: 7bbb ldrb r3, [r7, #14]
|
|
800298a: 2b02 cmp r3, #2
|
|
800298c: d115 bne.n 80029ba <bmm350_set_powermode+0x82>
|
|
{
|
|
reg_data = BMM350_PMU_CMD_SUS;
|
|
800298e: 2300 movs r3, #0
|
|
8002990: 737b strb r3, [r7, #13]
|
|
|
|
/* Set PMU command configuration */
|
|
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev);
|
|
8002992: f107 010d add.w r1, r7, #13
|
|
8002996: 683b ldr r3, [r7, #0]
|
|
8002998: 2201 movs r2, #1
|
|
800299a: 2006 movs r0, #6
|
|
800299c: f7ff ff28 bl 80027f0 <bmm350_set_regs>
|
|
80029a0: 4603 mov r3, r0
|
|
80029a2: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
80029a4: f997 300f ldrsb.w r3, [r7, #15]
|
|
80029a8: 2b00 cmp r3, #0
|
|
80029aa: d106 bne.n 80029ba <bmm350_set_powermode+0x82>
|
|
{
|
|
rslt = bmm350_delay_us(BMM350_GOTO_SUSPEND_DELAY, dev);
|
|
80029ac: 6839 ldr r1, [r7, #0]
|
|
80029ae: f241 7070 movw r0, #6000 @ 0x1770
|
|
80029b2: f7ff ffa6 bl 8002902 <bmm350_delay_us>
|
|
80029b6: 4603 mov r3, r0
|
|
80029b8: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
|
|
if (rslt == BMM350_OK)
|
|
80029ba: f997 300f ldrsb.w r3, [r7, #15]
|
|
80029be: 2b00 cmp r3, #0
|
|
80029c0: d106 bne.n 80029d0 <bmm350_set_powermode+0x98>
|
|
{
|
|
rslt = set_powermode(powermode, dev);
|
|
80029c2: 79fb ldrb r3, [r7, #7]
|
|
80029c4: 6839 ldr r1, [r7, #0]
|
|
80029c6: 4618 mov r0, r3
|
|
80029c8: f001 f82e bl 8003a28 <set_powermode>
|
|
80029cc: 4603 mov r3, r0
|
|
80029ce: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
80029d0: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
80029d4: 4618 mov r0, r3
|
|
80029d6: 3710 adds r7, #16
|
|
80029d8: 46bd mov sp, r7
|
|
80029da: bd80 pop {r7, pc}
|
|
|
|
080029dc <bmm350_set_odr_performance>:
|
|
* @brief This API sets the ODR and averaging factor.
|
|
*/
|
|
int8_t bmm350_set_odr_performance(enum bmm350_data_rates odr,
|
|
enum bmm350_performance_parameters performance,
|
|
struct bmm350_dev *dev)
|
|
{
|
|
80029dc: b580 push {r7, lr}
|
|
80029de: b084 sub sp, #16
|
|
80029e0: af00 add r7, sp, #0
|
|
80029e2: 4603 mov r3, r0
|
|
80029e4: 603a str r2, [r7, #0]
|
|
80029e6: 71fb strb r3, [r7, #7]
|
|
80029e8: 460b mov r3, r1
|
|
80029ea: 71bb strb r3, [r7, #6]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
/* Variable to get PMU command */
|
|
uint8_t reg_data = 0;
|
|
80029ec: 2300 movs r3, #0
|
|
80029ee: 737b strb r3, [r7, #13]
|
|
|
|
enum bmm350_performance_parameters performance_fix = performance;
|
|
80029f0: 79bb ldrb r3, [r7, #6]
|
|
80029f2: 73bb strb r3, [r7, #14]
|
|
|
|
/* Check for null pointer in the device structure */
|
|
rslt = null_ptr_check(dev);
|
|
80029f4: 6838 ldr r0, [r7, #0]
|
|
80029f6: f000 fc05 bl 8003204 <null_ptr_check>
|
|
80029fa: 4603 mov r3, r0
|
|
80029fc: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
80029fe: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002a02: 2b00 cmp r3, #0
|
|
8002a04: d151 bne.n 8002aaa <bmm350_set_odr_performance+0xce>
|
|
{
|
|
/* Reduce the performance setting when too high for the chosen ODR */
|
|
if ((odr == BMM350_DATA_RATE_400HZ) && (performance >= BMM350_AVERAGING_2))
|
|
8002a06: 79fb ldrb r3, [r7, #7]
|
|
8002a08: 2b02 cmp r3, #2
|
|
8002a0a: d105 bne.n 8002a18 <bmm350_set_odr_performance+0x3c>
|
|
8002a0c: 79bb ldrb r3, [r7, #6]
|
|
8002a0e: 2b00 cmp r3, #0
|
|
8002a10: d002 beq.n 8002a18 <bmm350_set_odr_performance+0x3c>
|
|
{
|
|
performance_fix = BMM350_NO_AVERAGING;
|
|
8002a12: 2300 movs r3, #0
|
|
8002a14: 73bb strb r3, [r7, #14]
|
|
8002a16: e010 b.n 8002a3a <bmm350_set_odr_performance+0x5e>
|
|
}
|
|
else if ((odr == BMM350_DATA_RATE_200HZ) && (performance >= BMM350_AVERAGING_4))
|
|
8002a18: 79fb ldrb r3, [r7, #7]
|
|
8002a1a: 2b03 cmp r3, #3
|
|
8002a1c: d105 bne.n 8002a2a <bmm350_set_odr_performance+0x4e>
|
|
8002a1e: 79bb ldrb r3, [r7, #6]
|
|
8002a20: 2b01 cmp r3, #1
|
|
8002a22: d902 bls.n 8002a2a <bmm350_set_odr_performance+0x4e>
|
|
{
|
|
performance_fix = BMM350_AVERAGING_2;
|
|
8002a24: 2301 movs r3, #1
|
|
8002a26: 73bb strb r3, [r7, #14]
|
|
8002a28: e007 b.n 8002a3a <bmm350_set_odr_performance+0x5e>
|
|
}
|
|
else if ((odr == BMM350_DATA_RATE_100HZ) && (performance >= BMM350_AVERAGING_8))
|
|
8002a2a: 79fb ldrb r3, [r7, #7]
|
|
8002a2c: 2b04 cmp r3, #4
|
|
8002a2e: d104 bne.n 8002a3a <bmm350_set_odr_performance+0x5e>
|
|
8002a30: 79bb ldrb r3, [r7, #6]
|
|
8002a32: 2b02 cmp r3, #2
|
|
8002a34: d901 bls.n 8002a3a <bmm350_set_odr_performance+0x5e>
|
|
{
|
|
performance_fix = BMM350_AVERAGING_4;
|
|
8002a36: 2302 movs r3, #2
|
|
8002a38: 73bb strb r3, [r7, #14]
|
|
}
|
|
|
|
/* ODR is an enum taking the generated constants from the register map */
|
|
reg_data = ((uint8_t)odr & BMM350_ODR_MSK);
|
|
8002a3a: 79fb ldrb r3, [r7, #7]
|
|
8002a3c: f003 030f and.w r3, r3, #15
|
|
8002a40: b2db uxtb r3, r3
|
|
8002a42: 737b strb r3, [r7, #13]
|
|
|
|
/* AVG / performance is an enum taking the generated constants from the register map */
|
|
reg_data = BMM350_SET_BITS(reg_data, BMM350_AVG, (uint8_t)performance_fix);
|
|
8002a44: 7b7b ldrb r3, [r7, #13]
|
|
8002a46: b25b sxtb r3, r3
|
|
8002a48: f023 0330 bic.w r3, r3, #48 @ 0x30
|
|
8002a4c: b25a sxtb r2, r3
|
|
8002a4e: f997 300e ldrsb.w r3, [r7, #14]
|
|
8002a52: 011b lsls r3, r3, #4
|
|
8002a54: b25b sxtb r3, r3
|
|
8002a56: f003 0330 and.w r3, r3, #48 @ 0x30
|
|
8002a5a: b25b sxtb r3, r3
|
|
8002a5c: 4313 orrs r3, r2
|
|
8002a5e: b25b sxtb r3, r3
|
|
8002a60: b2db uxtb r3, r3
|
|
8002a62: 737b strb r3, [r7, #13]
|
|
|
|
/* Set PMU command configurations for ODR and performance */
|
|
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD_AGGR_SET, ®_data, 1, dev);
|
|
8002a64: f107 010d add.w r1, r7, #13
|
|
8002a68: 683b ldr r3, [r7, #0]
|
|
8002a6a: 2201 movs r2, #1
|
|
8002a6c: 2004 movs r0, #4
|
|
8002a6e: f7ff febf bl 80027f0 <bmm350_set_regs>
|
|
8002a72: 4603 mov r3, r0
|
|
8002a74: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002a76: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002a7a: 2b00 cmp r3, #0
|
|
8002a7c: d115 bne.n 8002aaa <bmm350_set_odr_performance+0xce>
|
|
{
|
|
/* Set PMU command configurations to update odr and average */
|
|
reg_data = BMM350_PMU_CMD_UPD_OAE;
|
|
8002a7e: 2302 movs r3, #2
|
|
8002a80: 737b strb r3, [r7, #13]
|
|
|
|
/* Set PMU command configuration */
|
|
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev);
|
|
8002a82: f107 010d add.w r1, r7, #13
|
|
8002a86: 683b ldr r3, [r7, #0]
|
|
8002a88: 2201 movs r2, #1
|
|
8002a8a: 2006 movs r0, #6
|
|
8002a8c: f7ff feb0 bl 80027f0 <bmm350_set_regs>
|
|
8002a90: 4603 mov r3, r0
|
|
8002a92: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002a94: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002a98: 2b00 cmp r3, #0
|
|
8002a9a: d106 bne.n 8002aaa <bmm350_set_odr_performance+0xce>
|
|
{
|
|
rslt = bmm350_delay_us(BMM350_UPD_OAE_DELAY, dev);
|
|
8002a9c: 6839 ldr r1, [r7, #0]
|
|
8002a9e: f44f 707a mov.w r0, #1000 @ 0x3e8
|
|
8002aa2: f7ff ff2e bl 8002902 <bmm350_delay_us>
|
|
8002aa6: 4603 mov r3, r0
|
|
8002aa8: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
8002aaa: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8002aae: 4618 mov r0, r3
|
|
8002ab0: 3710 adds r7, #16
|
|
8002ab2: 46bd mov sp, r7
|
|
8002ab4: bd80 pop {r7, pc}
|
|
|
|
08002ab6 <bmm350_enable_interrupt>:
|
|
|
|
/*!
|
|
* @brief This API is used to enable or disable the data ready interrupt
|
|
*/
|
|
int8_t bmm350_enable_interrupt(enum bmm350_interrupt_enable_disable enable_disable, struct bmm350_dev *dev)
|
|
{
|
|
8002ab6: b580 push {r7, lr}
|
|
8002ab8: b084 sub sp, #16
|
|
8002aba: af00 add r7, sp, #0
|
|
8002abc: 4603 mov r3, r0
|
|
8002abe: 6039 str r1, [r7, #0]
|
|
8002ac0: 71fb strb r3, [r7, #7]
|
|
/* Variable to get interrupt control configuration */
|
|
uint8_t reg_data = 0;
|
|
8002ac2: 2300 movs r3, #0
|
|
8002ac4: 73bb strb r3, [r7, #14]
|
|
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
/* Get interrupt control configuration */
|
|
rslt = bmm350_get_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev);
|
|
8002ac6: f107 010e add.w r1, r7, #14
|
|
8002aca: 683b ldr r3, [r7, #0]
|
|
8002acc: 2201 movs r2, #1
|
|
8002ace: 202e movs r0, #46 @ 0x2e
|
|
8002ad0: f7ff fec2 bl 8002858 <bmm350_get_regs>
|
|
8002ad4: 4603 mov r3, r0
|
|
8002ad6: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002ad8: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002adc: 2b00 cmp r3, #0
|
|
8002ade: d115 bne.n 8002b0c <bmm350_enable_interrupt+0x56>
|
|
{
|
|
reg_data = BMM350_SET_BITS(reg_data, BMM350_DRDY_DATA_REG_EN, (uint8_t)enable_disable);
|
|
8002ae0: 7bbb ldrb r3, [r7, #14]
|
|
8002ae2: b25b sxtb r3, r3
|
|
8002ae4: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8002ae8: b25a sxtb r2, r3
|
|
8002aea: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8002aee: 01db lsls r3, r3, #7
|
|
8002af0: b25b sxtb r3, r3
|
|
8002af2: 4313 orrs r3, r2
|
|
8002af4: b25b sxtb r3, r3
|
|
8002af6: b2db uxtb r3, r3
|
|
8002af8: 73bb strb r3, [r7, #14]
|
|
|
|
/* Finally transfer the interrupt configurations */
|
|
rslt = bmm350_set_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev);
|
|
8002afa: f107 010e add.w r1, r7, #14
|
|
8002afe: 683b ldr r3, [r7, #0]
|
|
8002b00: 2201 movs r2, #1
|
|
8002b02: 202e movs r0, #46 @ 0x2e
|
|
8002b04: f7ff fe74 bl 80027f0 <bmm350_set_regs>
|
|
8002b08: 4603 mov r3, r0
|
|
8002b0a: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return rslt;
|
|
8002b0c: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8002b10: 4618 mov r0, r3
|
|
8002b12: 3710 adds r7, #16
|
|
8002b14: 46bd mov sp, r7
|
|
8002b16: bd80 pop {r7, pc}
|
|
|
|
08002b18 <bmm350_configure_interrupt>:
|
|
int8_t bmm350_configure_interrupt(enum bmm350_intr_latch latching,
|
|
enum bmm350_intr_polarity polarity,
|
|
enum bmm350_intr_drive drivertype,
|
|
enum bmm350_intr_map map_nomap,
|
|
struct bmm350_dev *dev)
|
|
{
|
|
8002b18: b590 push {r4, r7, lr}
|
|
8002b1a: b085 sub sp, #20
|
|
8002b1c: af00 add r7, sp, #0
|
|
8002b1e: 4604 mov r4, r0
|
|
8002b20: 4608 mov r0, r1
|
|
8002b22: 4611 mov r1, r2
|
|
8002b24: 461a mov r2, r3
|
|
8002b26: 4623 mov r3, r4
|
|
8002b28: 71fb strb r3, [r7, #7]
|
|
8002b2a: 4603 mov r3, r0
|
|
8002b2c: 71bb strb r3, [r7, #6]
|
|
8002b2e: 460b mov r3, r1
|
|
8002b30: 717b strb r3, [r7, #5]
|
|
8002b32: 4613 mov r3, r2
|
|
8002b34: 713b strb r3, [r7, #4]
|
|
/* Variable to get interrupt control configuration */
|
|
uint8_t reg_data = 0;
|
|
8002b36: 2300 movs r3, #0
|
|
8002b38: 73bb strb r3, [r7, #14]
|
|
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
/* Get interrupt control configuration */
|
|
rslt = bmm350_get_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev);
|
|
8002b3a: f107 010e add.w r1, r7, #14
|
|
8002b3e: 6a3b ldr r3, [r7, #32]
|
|
8002b40: 2201 movs r2, #1
|
|
8002b42: 202e movs r0, #46 @ 0x2e
|
|
8002b44: f7ff fe88 bl 8002858 <bmm350_get_regs>
|
|
8002b48: 4603 mov r3, r0
|
|
8002b4a: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002b4c: f997 300f ldrsb.w r3, [r7, #15]
|
|
8002b50: 2b00 cmp r3, #0
|
|
8002b52: d146 bne.n 8002be2 <bmm350_configure_interrupt+0xca>
|
|
{
|
|
reg_data = BMM350_SET_BITS_POS_0(reg_data, BMM350_INT_MODE, latching);
|
|
8002b54: 7bbb ldrb r3, [r7, #14]
|
|
8002b56: b25b sxtb r3, r3
|
|
8002b58: f023 0301 bic.w r3, r3, #1
|
|
8002b5c: b25a sxtb r2, r3
|
|
8002b5e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8002b62: f003 0301 and.w r3, r3, #1
|
|
8002b66: b25b sxtb r3, r3
|
|
8002b68: 4313 orrs r3, r2
|
|
8002b6a: b25b sxtb r3, r3
|
|
8002b6c: b2db uxtb r3, r3
|
|
8002b6e: 73bb strb r3, [r7, #14]
|
|
reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_POL, polarity);
|
|
8002b70: 7bbb ldrb r3, [r7, #14]
|
|
8002b72: b25b sxtb r3, r3
|
|
8002b74: f023 0302 bic.w r3, r3, #2
|
|
8002b78: b25a sxtb r2, r3
|
|
8002b7a: f997 3006 ldrsb.w r3, [r7, #6]
|
|
8002b7e: 005b lsls r3, r3, #1
|
|
8002b80: b25b sxtb r3, r3
|
|
8002b82: f003 0302 and.w r3, r3, #2
|
|
8002b86: b25b sxtb r3, r3
|
|
8002b88: 4313 orrs r3, r2
|
|
8002b8a: b25b sxtb r3, r3
|
|
8002b8c: b2db uxtb r3, r3
|
|
8002b8e: 73bb strb r3, [r7, #14]
|
|
reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_OD, drivertype);
|
|
8002b90: 7bbb ldrb r3, [r7, #14]
|
|
8002b92: b25b sxtb r3, r3
|
|
8002b94: f023 0304 bic.w r3, r3, #4
|
|
8002b98: b25a sxtb r2, r3
|
|
8002b9a: f997 3005 ldrsb.w r3, [r7, #5]
|
|
8002b9e: 009b lsls r3, r3, #2
|
|
8002ba0: b25b sxtb r3, r3
|
|
8002ba2: f003 0304 and.w r3, r3, #4
|
|
8002ba6: b25b sxtb r3, r3
|
|
8002ba8: 4313 orrs r3, r2
|
|
8002baa: b25b sxtb r3, r3
|
|
8002bac: b2db uxtb r3, r3
|
|
8002bae: 73bb strb r3, [r7, #14]
|
|
reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_OUTPUT_EN, map_nomap);
|
|
8002bb0: 7bbb ldrb r3, [r7, #14]
|
|
8002bb2: b25b sxtb r3, r3
|
|
8002bb4: f023 0308 bic.w r3, r3, #8
|
|
8002bb8: b25a sxtb r2, r3
|
|
8002bba: f997 3004 ldrsb.w r3, [r7, #4]
|
|
8002bbe: 00db lsls r3, r3, #3
|
|
8002bc0: b25b sxtb r3, r3
|
|
8002bc2: f003 0308 and.w r3, r3, #8
|
|
8002bc6: b25b sxtb r3, r3
|
|
8002bc8: 4313 orrs r3, r2
|
|
8002bca: b25b sxtb r3, r3
|
|
8002bcc: b2db uxtb r3, r3
|
|
8002bce: 73bb strb r3, [r7, #14]
|
|
|
|
/* Finally transfer the interrupt configurations */
|
|
rslt = bmm350_set_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev);
|
|
8002bd0: f107 010e add.w r1, r7, #14
|
|
8002bd4: 6a3b ldr r3, [r7, #32]
|
|
8002bd6: 2201 movs r2, #1
|
|
8002bd8: 202e movs r0, #46 @ 0x2e
|
|
8002bda: f7ff fe09 bl 80027f0 <bmm350_set_regs>
|
|
8002bde: 4603 mov r3, r0
|
|
8002be0: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return rslt;
|
|
8002be2: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8002be6: 4618 mov r0, r3
|
|
8002be8: 3714 adds r7, #20
|
|
8002bea: 46bd mov sp, r7
|
|
8002bec: bd90 pop {r4, r7, pc}
|
|
|
|
08002bee <bmm350_read_uncomp_mag_temp_data>:
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/*!
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* @brief This API is used to read uncompensated mag and temperature data.
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*/
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int8_t bmm350_read_uncomp_mag_temp_data(struct bmm350_raw_mag_data *raw_data, struct bmm350_dev *dev)
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{
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8002bee: b580 push {r7, lr}
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8002bf0: b08a sub sp, #40 @ 0x28
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8002bf2: af00 add r7, sp, #0
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8002bf4: 6078 str r0, [r7, #4]
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8002bf6: 6039 str r1, [r7, #0]
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/* Variable to store the function result */
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int8_t rslt;
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uint8_t mag_data[12] = { 0 };
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8002bf8: f107 0308 add.w r3, r7, #8
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8002bfc: 2200 movs r2, #0
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8002bfe: 601a str r2, [r3, #0]
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8002c00: 605a str r2, [r3, #4]
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8002c02: 609a str r2, [r3, #8]
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uint32_t raw_mag_x, raw_mag_y, raw_mag_z, raw_temp;
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if (raw_data != NULL)
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8002c04: 687b ldr r3, [r7, #4]
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8002c06: 2b00 cmp r3, #0
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8002c08: d06c beq.n 8002ce4 <bmm350_read_uncomp_mag_temp_data+0xf6>
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{
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/* Get uncompensated mag data */
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rslt = bmm350_get_regs(BMM350_REG_MAG_X_XLSB, mag_data, BMM350_MAG_TEMP_DATA_LEN, dev);
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8002c0a: f107 0108 add.w r1, r7, #8
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8002c0e: 683b ldr r3, [r7, #0]
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8002c10: 220c movs r2, #12
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8002c12: 2031 movs r0, #49 @ 0x31
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8002c14: f7ff fe20 bl 8002858 <bmm350_get_regs>
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8002c18: 4603 mov r3, r0
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8002c1a: f887 3027 strb.w r3, [r7, #39] @ 0x27
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if (rslt == BMM350_OK)
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8002c1e: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27
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8002c22: 2b00 cmp r3, #0
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8002c24: d161 bne.n 8002cea <bmm350_read_uncomp_mag_temp_data+0xfc>
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{
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raw_mag_x = (uint32_t)mag_data[0] + ((uint32_t)mag_data[1] << 8) + ((uint32_t)mag_data[2] << 16);
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8002c26: 7a3b ldrb r3, [r7, #8]
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8002c28: 461a mov r2, r3
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8002c2a: 7a7b ldrb r3, [r7, #9]
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8002c2c: 021b lsls r3, r3, #8
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8002c2e: 441a add r2, r3
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8002c30: 7abb ldrb r3, [r7, #10]
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8002c32: 041b lsls r3, r3, #16
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8002c34: 4413 add r3, r2
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8002c36: 623b str r3, [r7, #32]
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raw_mag_y = (uint32_t)mag_data[3] + ((uint32_t)mag_data[4] << 8) + ((uint32_t)mag_data[5] << 16);
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8002c38: 7afb ldrb r3, [r7, #11]
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8002c3a: 461a mov r2, r3
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8002c3c: 7b3b ldrb r3, [r7, #12]
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8002c3e: 021b lsls r3, r3, #8
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8002c40: 441a add r2, r3
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8002c42: 7b7b ldrb r3, [r7, #13]
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8002c44: 041b lsls r3, r3, #16
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8002c46: 4413 add r3, r2
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8002c48: 61fb str r3, [r7, #28]
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raw_mag_z = (uint32_t)mag_data[6] + ((uint32_t)mag_data[7] << 8) + ((uint32_t)mag_data[8] << 16);
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8002c4a: 7bbb ldrb r3, [r7, #14]
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8002c4c: 461a mov r2, r3
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8002c4e: 7bfb ldrb r3, [r7, #15]
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8002c50: 021b lsls r3, r3, #8
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8002c52: 441a add r2, r3
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8002c54: 7c3b ldrb r3, [r7, #16]
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8002c56: 041b lsls r3, r3, #16
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8002c58: 4413 add r3, r2
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8002c5a: 61bb str r3, [r7, #24]
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raw_temp = (uint32_t)mag_data[9] + ((uint32_t)mag_data[10] << 8) + ((uint32_t)mag_data[11] << 16);
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8002c5c: 7c7b ldrb r3, [r7, #17]
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8002c5e: 461a mov r2, r3
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8002c60: 7cbb ldrb r3, [r7, #18]
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8002c62: 021b lsls r3, r3, #8
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8002c64: 441a add r2, r3
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8002c66: 7cfb ldrb r3, [r7, #19]
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8002c68: 041b lsls r3, r3, #16
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8002c6a: 4413 add r3, r2
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8002c6c: 617b str r3, [r7, #20]
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if ((dev->axis_en & BMM350_EN_X_MSK) == BMM350_DISABLE)
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8002c6e: 683b ldr r3, [r7, #0]
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8002c70: 7d5b ldrb r3, [r3, #21]
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8002c72: f003 0301 and.w r3, r3, #1
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8002c76: 2b00 cmp r3, #0
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8002c78: d103 bne.n 8002c82 <bmm350_read_uncomp_mag_temp_data+0x94>
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{
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raw_data->raw_xdata = BMM350_DISABLE;
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8002c7a: 687b ldr r3, [r7, #4]
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8002c7c: 2200 movs r2, #0
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8002c7e: 601a str r2, [r3, #0]
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8002c80: e006 b.n 8002c90 <bmm350_read_uncomp_mag_temp_data+0xa2>
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}
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else
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{
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raw_data->raw_xdata = fix_sign(raw_mag_x, BMM350_SIGNED_24_BIT);
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8002c82: 2118 movs r1, #24
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8002c84: 6a38 ldr r0, [r7, #32]
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8002c86: f000 fadd bl 8003244 <fix_sign>
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8002c8a: 4602 mov r2, r0
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8002c8c: 687b ldr r3, [r7, #4]
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8002c8e: 601a str r2, [r3, #0]
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}
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if ((dev->axis_en & BMM350_EN_Y_MSK) == BMM350_DISABLE)
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8002c90: 683b ldr r3, [r7, #0]
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8002c92: 7d5b ldrb r3, [r3, #21]
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8002c94: f003 0302 and.w r3, r3, #2
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8002c98: 2b00 cmp r3, #0
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8002c9a: d103 bne.n 8002ca4 <bmm350_read_uncomp_mag_temp_data+0xb6>
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{
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raw_data->raw_ydata = BMM350_DISABLE;
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8002c9c: 687b ldr r3, [r7, #4]
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8002c9e: 2200 movs r2, #0
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8002ca0: 605a str r2, [r3, #4]
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8002ca2: e006 b.n 8002cb2 <bmm350_read_uncomp_mag_temp_data+0xc4>
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}
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else
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{
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raw_data->raw_ydata = fix_sign(raw_mag_y, BMM350_SIGNED_24_BIT);
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8002ca4: 2118 movs r1, #24
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8002ca6: 69f8 ldr r0, [r7, #28]
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8002ca8: f000 facc bl 8003244 <fix_sign>
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8002cac: 4602 mov r2, r0
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8002cae: 687b ldr r3, [r7, #4]
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8002cb0: 605a str r2, [r3, #4]
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}
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if ((dev->axis_en & BMM350_EN_Z_MSK) == BMM350_DISABLE)
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8002cb2: 683b ldr r3, [r7, #0]
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8002cb4: 7d5b ldrb r3, [r3, #21]
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8002cb6: f003 0304 and.w r3, r3, #4
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8002cba: 2b00 cmp r3, #0
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8002cbc: d103 bne.n 8002cc6 <bmm350_read_uncomp_mag_temp_data+0xd8>
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{
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raw_data->raw_zdata = BMM350_DISABLE;
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8002cbe: 687b ldr r3, [r7, #4]
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8002cc0: 2200 movs r2, #0
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8002cc2: 609a str r2, [r3, #8]
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8002cc4: e006 b.n 8002cd4 <bmm350_read_uncomp_mag_temp_data+0xe6>
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}
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else
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{
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raw_data->raw_zdata = fix_sign(raw_mag_z, BMM350_SIGNED_24_BIT);
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8002cc6: 2118 movs r1, #24
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8002cc8: 69b8 ldr r0, [r7, #24]
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8002cca: f000 fabb bl 8003244 <fix_sign>
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8002cce: 4602 mov r2, r0
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8002cd0: 687b ldr r3, [r7, #4]
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8002cd2: 609a str r2, [r3, #8]
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}
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raw_data->raw_data_t = fix_sign(raw_temp, BMM350_SIGNED_24_BIT);
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8002cd4: 2118 movs r1, #24
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8002cd6: 6978 ldr r0, [r7, #20]
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8002cd8: f000 fab4 bl 8003244 <fix_sign>
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8002cdc: 4602 mov r2, r0
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8002cde: 687b ldr r3, [r7, #4]
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8002ce0: 60da str r2, [r3, #12]
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8002ce2: e002 b.n 8002cea <bmm350_read_uncomp_mag_temp_data+0xfc>
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}
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}
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else
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{
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rslt = BMM350_E_NULL_PTR;
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8002ce4: 23ff movs r3, #255 @ 0xff
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8002ce6: f887 3027 strb.w r3, [r7, #39] @ 0x27
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}
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return rslt;
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8002cea: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27
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}
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8002cee: 4618 mov r0, r3
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8002cf0: 3728 adds r7, #40 @ 0x28
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8002cf2: 46bd mov sp, r7
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8002cf4: bd80 pop {r7, pc}
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08002cf6 <bmm350_magnetic_reset_and_wait>:
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* @brief This API is used to perform the magnetic reset of the sensor
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* which is necessary after a field shock (400mT field applied to sensor).
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* It sends flux guide or bit reset to the device in suspend mode.
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*/
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int8_t bmm350_magnetic_reset_and_wait(struct bmm350_dev *dev)
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{
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8002cf6: b580 push {r7, lr}
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8002cf8: b086 sub sp, #24
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8002cfa: af00 add r7, sp, #0
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8002cfc: 6078 str r0, [r7, #4]
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/* Variable to store the function result */
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int8_t rslt;
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uint8_t pmu_cmd = 0;
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8002cfe: 2300 movs r3, #0
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8002d00: 757b strb r3, [r7, #21]
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struct bmm350_pmu_cmd_status_0 pmu_cmd_stat_0 = { 0 };
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8002d02: f107 030c add.w r3, r7, #12
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8002d06: 2200 movs r2, #0
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8002d08: 601a str r2, [r3, #0]
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8002d0a: 809a strh r2, [r3, #4]
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uint8_t restore_normal = BMM350_DISABLE;
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8002d0c: 2300 movs r3, #0
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8002d0e: 75bb strb r3, [r7, #22]
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rslt = null_ptr_check(dev);
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8002d10: 6878 ldr r0, [r7, #4]
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8002d12: f000 fa77 bl 8003204 <null_ptr_check>
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8002d16: 4603 mov r3, r0
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8002d18: 75fb strb r3, [r7, #23]
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if ((rslt == BMM350_OK) && (dev->mraw_override))
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8002d1a: f997 3017 ldrsb.w r3, [r7, #23]
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8002d1e: 2b00 cmp r3, #0
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8002d20: d10c bne.n 8002d3c <bmm350_magnetic_reset_and_wait+0x46>
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8002d22: 687b ldr r3, [r7, #4]
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8002d24: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8
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8002d28: 2b00 cmp r3, #0
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8002d2a: d007 beq.n 8002d3c <bmm350_magnetic_reset_and_wait+0x46>
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{
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rslt = dev->mraw_override(dev);
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8002d2c: 687b ldr r3, [r7, #4]
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8002d2e: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8
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8002d32: 6878 ldr r0, [r7, #4]
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8002d34: 4798 blx r3
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8002d36: 4603 mov r3, r0
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8002d38: 75fb strb r3, [r7, #23]
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8002d3a: e081 b.n 8002e40 <bmm350_magnetic_reset_and_wait+0x14a>
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}
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else
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{
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/* Read PMU CMD status */
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rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev);
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8002d3c: f107 030c add.w r3, r7, #12
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8002d40: 6879 ldr r1, [r7, #4]
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8002d42: 4618 mov r0, r3
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8002d44: f000 fa15 bl 8003172 <bmm350_get_pmu_cmd_status_0>
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8002d48: 4603 mov r3, r0
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8002d4a: 75fb strb r3, [r7, #23]
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/* Check the powermode is normal before performing magnetic reset */
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if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pwr_mode_is_normal == BMM350_ENABLE))
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8002d4c: f997 3017 ldrsb.w r3, [r7, #23]
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8002d50: 2b00 cmp r3, #0
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8002d52: d10a bne.n 8002d6a <bmm350_magnetic_reset_and_wait+0x74>
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8002d54: 7bfb ldrb r3, [r7, #15]
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8002d56: 2b01 cmp r3, #1
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8002d58: d107 bne.n 8002d6a <bmm350_magnetic_reset_and_wait+0x74>
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{
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restore_normal = BMM350_ENABLE;
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8002d5a: 2301 movs r3, #1
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8002d5c: 75bb strb r3, [r7, #22]
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/* Reset can only be triggered in suspend */
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rslt = bmm350_set_powermode(BMM350_SUSPEND_MODE, dev);
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8002d5e: 6879 ldr r1, [r7, #4]
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8002d60: 2000 movs r0, #0
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8002d62: f7ff fde9 bl 8002938 <bmm350_set_powermode>
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8002d66: 4603 mov r3, r0
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8002d68: 75fb strb r3, [r7, #23]
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}
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if (rslt == BMM350_OK)
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8002d6a: f997 3017 ldrsb.w r3, [r7, #23]
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8002d6e: 2b00 cmp r3, #0
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8002d70: d115 bne.n 8002d9e <bmm350_magnetic_reset_and_wait+0xa8>
|
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{
|
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/* Set BR to PMU_CMD register */
|
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pmu_cmd = BMM350_PMU_CMD_BR;
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8002d72: 2307 movs r3, #7
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8002d74: 757b strb r3, [r7, #21]
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|
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rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &pmu_cmd, 1, dev);
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8002d76: f107 0115 add.w r1, r7, #21
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8002d7a: 687b ldr r3, [r7, #4]
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8002d7c: 2201 movs r2, #1
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8002d7e: 2006 movs r0, #6
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8002d80: f7ff fd36 bl 80027f0 <bmm350_set_regs>
|
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8002d84: 4603 mov r3, r0
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8002d86: 75fb strb r3, [r7, #23]
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if (rslt == BMM350_OK)
|
|
8002d88: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002d8c: 2b00 cmp r3, #0
|
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8002d8e: d106 bne.n 8002d9e <bmm350_magnetic_reset_and_wait+0xa8>
|
|
{
|
|
rslt = bmm350_delay_us(BMM350_BR_DELAY, dev);
|
|
8002d90: 6879 ldr r1, [r7, #4]
|
|
8002d92: f243 60b0 movw r0, #14000 @ 0x36b0
|
|
8002d96: f7ff fdb4 bl 8002902 <bmm350_delay_us>
|
|
8002d9a: 4603 mov r3, r0
|
|
8002d9c: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002d9e: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002da2: 2b00 cmp r3, #0
|
|
8002da4: d110 bne.n 8002dc8 <bmm350_magnetic_reset_and_wait+0xd2>
|
|
{
|
|
/* Verify if PMU_CMD_STATUS_0 register has BR set */
|
|
rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev);
|
|
8002da6: f107 030c add.w r3, r7, #12
|
|
8002daa: 6879 ldr r1, [r7, #4]
|
|
8002dac: 4618 mov r0, r3
|
|
8002dae: f000 f9e0 bl 8003172 <bmm350_get_pmu_cmd_status_0>
|
|
8002db2: 4603 mov r3, r0
|
|
8002db4: 75fb strb r3, [r7, #23]
|
|
|
|
if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pmu_cmd_value != BMM350_PMU_CMD_STATUS_0_BR))
|
|
8002db6: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002dba: 2b00 cmp r3, #0
|
|
8002dbc: d104 bne.n 8002dc8 <bmm350_magnetic_reset_and_wait+0xd2>
|
|
8002dbe: 7c7b ldrb r3, [r7, #17]
|
|
8002dc0: 2b07 cmp r3, #7
|
|
8002dc2: d001 beq.n 8002dc8 <bmm350_magnetic_reset_and_wait+0xd2>
|
|
{
|
|
rslt = BMM350_E_PMU_CMD_VALUE;
|
|
8002dc4: 23f0 movs r3, #240 @ 0xf0
|
|
8002dc6: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002dc8: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002dcc: 2b00 cmp r3, #0
|
|
8002dce: d115 bne.n 8002dfc <bmm350_magnetic_reset_and_wait+0x106>
|
|
{
|
|
/* Set FGR to PMU_CMD register */
|
|
pmu_cmd = BMM350_PMU_CMD_FGR;
|
|
8002dd0: 2305 movs r3, #5
|
|
8002dd2: 757b strb r3, [r7, #21]
|
|
|
|
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &pmu_cmd, 1, dev);
|
|
8002dd4: f107 0115 add.w r1, r7, #21
|
|
8002dd8: 687b ldr r3, [r7, #4]
|
|
8002dda: 2201 movs r2, #1
|
|
8002ddc: 2006 movs r0, #6
|
|
8002dde: f7ff fd07 bl 80027f0 <bmm350_set_regs>
|
|
8002de2: 4603 mov r3, r0
|
|
8002de4: 75fb strb r3, [r7, #23]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002de6: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002dea: 2b00 cmp r3, #0
|
|
8002dec: d106 bne.n 8002dfc <bmm350_magnetic_reset_and_wait+0x106>
|
|
{
|
|
rslt = bmm350_delay_us(BMM350_FGR_DELAY, dev);
|
|
8002dee: 6879 ldr r1, [r7, #4]
|
|
8002df0: f244 6050 movw r0, #18000 @ 0x4650
|
|
8002df4: f7ff fd85 bl 8002902 <bmm350_delay_us>
|
|
8002df8: 4603 mov r3, r0
|
|
8002dfa: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002dfc: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002e00: 2b00 cmp r3, #0
|
|
8002e02: d110 bne.n 8002e26 <bmm350_magnetic_reset_and_wait+0x130>
|
|
{
|
|
/* Verify if PMU_CMD_STATUS_0 register has FGR set */
|
|
rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev);
|
|
8002e04: f107 030c add.w r3, r7, #12
|
|
8002e08: 6879 ldr r1, [r7, #4]
|
|
8002e0a: 4618 mov r0, r3
|
|
8002e0c: f000 f9b1 bl 8003172 <bmm350_get_pmu_cmd_status_0>
|
|
8002e10: 4603 mov r3, r0
|
|
8002e12: 75fb strb r3, [r7, #23]
|
|
|
|
if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pmu_cmd_value != BMM350_PMU_CMD_STATUS_0_FGR))
|
|
8002e14: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002e18: 2b00 cmp r3, #0
|
|
8002e1a: d104 bne.n 8002e26 <bmm350_magnetic_reset_and_wait+0x130>
|
|
8002e1c: 7c7b ldrb r3, [r7, #17]
|
|
8002e1e: 2b05 cmp r3, #5
|
|
8002e20: d001 beq.n 8002e26 <bmm350_magnetic_reset_and_wait+0x130>
|
|
{
|
|
rslt = BMM350_E_PMU_CMD_VALUE;
|
|
8002e22: 23f0 movs r3, #240 @ 0xf0
|
|
8002e24: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
|
|
if ((rslt == BMM350_OK) && (restore_normal == BMM350_ENABLE))
|
|
8002e26: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8002e2a: 2b00 cmp r3, #0
|
|
8002e2c: d108 bne.n 8002e40 <bmm350_magnetic_reset_and_wait+0x14a>
|
|
8002e2e: 7dbb ldrb r3, [r7, #22]
|
|
8002e30: 2b01 cmp r3, #1
|
|
8002e32: d105 bne.n 8002e40 <bmm350_magnetic_reset_and_wait+0x14a>
|
|
{
|
|
rslt = bmm350_set_powermode(BMM350_NORMAL_MODE, dev);
|
|
8002e34: 6879 ldr r1, [r7, #4]
|
|
8002e36: 2001 movs r0, #1
|
|
8002e38: f7ff fd7e bl 8002938 <bmm350_set_powermode>
|
|
8002e3c: 4603 mov r3, r0
|
|
8002e3e: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
8002e40: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
8002e44: 4618 mov r0, r3
|
|
8002e46: 3718 adds r7, #24
|
|
8002e48: 46bd mov sp, r7
|
|
8002e4a: bd80 pop {r7, pc}
|
|
|
|
08002e4c <bmm350_get_compensated_mag_xyz_temp_data>:
|
|
|
|
/*!
|
|
* @brief This API is used to perform compensation for raw magnetometer and temperature data.
|
|
*/
|
|
int8_t bmm350_get_compensated_mag_xyz_temp_data(struct bmm350_mag_temp_data *mag_temp_data, struct bmm350_dev *dev)
|
|
{
|
|
8002e4c: b580 push {r7, lr}
|
|
8002e4e: b096 sub sp, #88 @ 0x58
|
|
8002e50: af00 add r7, sp, #0
|
|
8002e52: 6078 str r0, [r7, #4]
|
|
8002e54: 6039 str r1, [r7, #0]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
uint8_t indx;
|
|
|
|
float out_data[4] = { 0.0f };
|
|
8002e56: f107 0338 add.w r3, r7, #56 @ 0x38
|
|
8002e5a: 2200 movs r2, #0
|
|
8002e5c: 601a str r2, [r3, #0]
|
|
8002e5e: 605a str r2, [r3, #4]
|
|
8002e60: 609a str r2, [r3, #8]
|
|
8002e62: 60da str r2, [r3, #12]
|
|
float dut_offset_coef[3], dut_sensit_coef[3], dut_tco[3], dut_tcs[3];
|
|
float cr_ax_comp_x, cr_ax_comp_y, cr_ax_comp_z;
|
|
|
|
if (mag_temp_data != NULL)
|
|
8002e64: 687b ldr r3, [r7, #4]
|
|
8002e66: 2b00 cmp r3, #0
|
|
8002e68: f000 817a beq.w 8003160 <bmm350_get_compensated_mag_xyz_temp_data+0x314>
|
|
{
|
|
/* Reads raw magnetic x,y and z axis along with temperature */
|
|
rslt = read_out_raw_data(out_data, dev);
|
|
8002e6c: f107 0338 add.w r3, r7, #56 @ 0x38
|
|
8002e70: 6839 ldr r1, [r7, #0]
|
|
8002e72: 4618 mov r0, r3
|
|
8002e74: f000 fc9c bl 80037b0 <read_out_raw_data>
|
|
8002e78: 4603 mov r3, r0
|
|
8002e7a: f887 3057 strb.w r3, [r7, #87] @ 0x57
|
|
|
|
if (rslt == BMM350_OK)
|
|
8002e7e: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57
|
|
8002e82: 2b00 cmp r3, #0
|
|
8002e84: f040 813a bne.w 80030fc <bmm350_get_compensated_mag_xyz_temp_data+0x2b0>
|
|
{
|
|
/* Apply compensation to temperature reading */
|
|
out_data[3] = (1 + dev->mag_comp.dut_sensit_coef.t_sens) * out_data[3] +
|
|
8002e88: 683b ldr r3, [r7, #0]
|
|
8002e8a: edd3 7a0a vldr s15, [r3, #40] @ 0x28
|
|
8002e8e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
|
|
8002e92: ee37 7a87 vadd.f32 s14, s15, s14
|
|
8002e96: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
8002e9a: ee27 7a27 vmul.f32 s14, s14, s15
|
|
dev->mag_comp.dut_offset_coef.t_offs;
|
|
8002e9e: 683b ldr r3, [r7, #0]
|
|
8002ea0: edd3 7a06 vldr s15, [r3, #24]
|
|
out_data[3] = (1 + dev->mag_comp.dut_sensit_coef.t_sens) * out_data[3] +
|
|
8002ea4: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8002ea8: edc7 7a11 vstr s15, [r7, #68] @ 0x44
|
|
|
|
/* Store magnetic compensation structure to an array */
|
|
dut_offset_coef[0] = dev->mag_comp.dut_offset_coef.offset_x;
|
|
8002eac: 683b ldr r3, [r7, #0]
|
|
8002eae: 69db ldr r3, [r3, #28]
|
|
8002eb0: 62fb str r3, [r7, #44] @ 0x2c
|
|
dut_offset_coef[1] = dev->mag_comp.dut_offset_coef.offset_y;
|
|
8002eb2: 683b ldr r3, [r7, #0]
|
|
8002eb4: 6a1b ldr r3, [r3, #32]
|
|
8002eb6: 633b str r3, [r7, #48] @ 0x30
|
|
dut_offset_coef[2] = dev->mag_comp.dut_offset_coef.offset_z;
|
|
8002eb8: 683b ldr r3, [r7, #0]
|
|
8002eba: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002ebc: 637b str r3, [r7, #52] @ 0x34
|
|
|
|
dut_sensit_coef[0] = dev->mag_comp.dut_sensit_coef.sens_x;
|
|
8002ebe: 683b ldr r3, [r7, #0]
|
|
8002ec0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002ec2: 623b str r3, [r7, #32]
|
|
dut_sensit_coef[1] = dev->mag_comp.dut_sensit_coef.sens_y;
|
|
8002ec4: 683b ldr r3, [r7, #0]
|
|
8002ec6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8002ec8: 627b str r3, [r7, #36] @ 0x24
|
|
dut_sensit_coef[2] = dev->mag_comp.dut_sensit_coef.sens_z;
|
|
8002eca: 683b ldr r3, [r7, #0]
|
|
8002ecc: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8002ece: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
dut_tco[0] = dev->mag_comp.dut_tco.tco_x;
|
|
8002ed0: 683b ldr r3, [r7, #0]
|
|
8002ed2: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8002ed4: 617b str r3, [r7, #20]
|
|
dut_tco[1] = dev->mag_comp.dut_tco.tco_y;
|
|
8002ed6: 683b ldr r3, [r7, #0]
|
|
8002ed8: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002eda: 61bb str r3, [r7, #24]
|
|
dut_tco[2] = dev->mag_comp.dut_tco.tco_z;
|
|
8002edc: 683b ldr r3, [r7, #0]
|
|
8002ede: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002ee0: 61fb str r3, [r7, #28]
|
|
|
|
dut_tcs[0] = dev->mag_comp.dut_tcs.tcs_x;
|
|
8002ee2: 683b ldr r3, [r7, #0]
|
|
8002ee4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002ee6: 60bb str r3, [r7, #8]
|
|
dut_tcs[1] = dev->mag_comp.dut_tcs.tcs_y;
|
|
8002ee8: 683b ldr r3, [r7, #0]
|
|
8002eea: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8002eec: 60fb str r3, [r7, #12]
|
|
dut_tcs[2] = dev->mag_comp.dut_tcs.tcs_z;
|
|
8002eee: 683b ldr r3, [r7, #0]
|
|
8002ef0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002ef2: 613b str r3, [r7, #16]
|
|
|
|
/* Compensate raw magnetic data */
|
|
for (indx = 0; indx < 3; indx++)
|
|
8002ef4: 2300 movs r3, #0
|
|
8002ef6: f887 3056 strb.w r3, [r7, #86] @ 0x56
|
|
8002efa: e086 b.n 800300a <bmm350_get_compensated_mag_xyz_temp_data+0x1be>
|
|
{
|
|
out_data[indx] *= 1 + dut_sensit_coef[indx];
|
|
8002efc: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002f00: 009b lsls r3, r3, #2
|
|
8002f02: 3358 adds r3, #88 @ 0x58
|
|
8002f04: 443b add r3, r7
|
|
8002f06: 3b20 subs r3, #32
|
|
8002f08: ed93 7a00 vldr s14, [r3]
|
|
8002f0c: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002f10: 009b lsls r3, r3, #2
|
|
8002f12: 3358 adds r3, #88 @ 0x58
|
|
8002f14: 443b add r3, r7
|
|
8002f16: 3b38 subs r3, #56 @ 0x38
|
|
8002f18: edd3 7a00 vldr s15, [r3]
|
|
8002f1c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
|
|
8002f20: ee77 7aa6 vadd.f32 s15, s15, s13
|
|
8002f24: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002f28: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8002f2c: 009b lsls r3, r3, #2
|
|
8002f2e: 3358 adds r3, #88 @ 0x58
|
|
8002f30: 443b add r3, r7
|
|
8002f32: 3b20 subs r3, #32
|
|
8002f34: edc3 7a00 vstr s15, [r3]
|
|
out_data[indx] += dut_offset_coef[indx];
|
|
8002f38: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002f3c: 009b lsls r3, r3, #2
|
|
8002f3e: 3358 adds r3, #88 @ 0x58
|
|
8002f40: 443b add r3, r7
|
|
8002f42: 3b20 subs r3, #32
|
|
8002f44: ed93 7a00 vldr s14, [r3]
|
|
8002f48: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002f4c: 009b lsls r3, r3, #2
|
|
8002f4e: 3358 adds r3, #88 @ 0x58
|
|
8002f50: 443b add r3, r7
|
|
8002f52: 3b2c subs r3, #44 @ 0x2c
|
|
8002f54: edd3 7a00 vldr s15, [r3]
|
|
8002f58: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002f5c: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8002f60: 009b lsls r3, r3, #2
|
|
8002f62: 3358 adds r3, #88 @ 0x58
|
|
8002f64: 443b add r3, r7
|
|
8002f66: 3b20 subs r3, #32
|
|
8002f68: edc3 7a00 vstr s15, [r3]
|
|
out_data[indx] += dut_tco[indx] * (out_data[3] - dev->mag_comp.dut_t0);
|
|
8002f6c: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002f70: 009b lsls r3, r3, #2
|
|
8002f72: 3358 adds r3, #88 @ 0x58
|
|
8002f74: 443b add r3, r7
|
|
8002f76: 3b20 subs r3, #32
|
|
8002f78: ed93 7a00 vldr s14, [r3]
|
|
8002f7c: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002f80: 009b lsls r3, r3, #2
|
|
8002f82: 3358 adds r3, #88 @ 0x58
|
|
8002f84: 443b add r3, r7
|
|
8002f86: 3b44 subs r3, #68 @ 0x44
|
|
8002f88: edd3 6a00 vldr s13, [r3]
|
|
8002f8c: ed97 6a11 vldr s12, [r7, #68] @ 0x44
|
|
8002f90: 683b ldr r3, [r7, #0]
|
|
8002f92: edd3 7a14 vldr s15, [r3, #80] @ 0x50
|
|
8002f96: ee76 7a67 vsub.f32 s15, s12, s15
|
|
8002f9a: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8002f9e: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002fa2: ee77 7a27 vadd.f32 s15, s14, s15
|
|
8002fa6: 009b lsls r3, r3, #2
|
|
8002fa8: 3358 adds r3, #88 @ 0x58
|
|
8002faa: 443b add r3, r7
|
|
8002fac: 3b20 subs r3, #32
|
|
8002fae: edc3 7a00 vstr s15, [r3]
|
|
out_data[indx] /= 1 + dut_tcs[indx] * (out_data[3] - dev->mag_comp.dut_t0);
|
|
8002fb2: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002fb6: 009b lsls r3, r3, #2
|
|
8002fb8: 3358 adds r3, #88 @ 0x58
|
|
8002fba: 443b add r3, r7
|
|
8002fbc: 3b20 subs r3, #32
|
|
8002fbe: edd3 6a00 vldr s13, [r3]
|
|
8002fc2: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002fc6: 009b lsls r3, r3, #2
|
|
8002fc8: 3358 adds r3, #88 @ 0x58
|
|
8002fca: 443b add r3, r7
|
|
8002fcc: 3b50 subs r3, #80 @ 0x50
|
|
8002fce: ed93 7a00 vldr s14, [r3]
|
|
8002fd2: ed97 6a11 vldr s12, [r7, #68] @ 0x44
|
|
8002fd6: 683b ldr r3, [r7, #0]
|
|
8002fd8: edd3 7a14 vldr s15, [r3, #80] @ 0x50
|
|
8002fdc: ee76 7a67 vsub.f32 s15, s12, s15
|
|
8002fe0: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8002fe4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
|
|
8002fe8: ee37 7a87 vadd.f32 s14, s15, s14
|
|
8002fec: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8002ff0: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8002ff4: 009b lsls r3, r3, #2
|
|
8002ff6: 3358 adds r3, #88 @ 0x58
|
|
8002ff8: 443b add r3, r7
|
|
8002ffa: 3b20 subs r3, #32
|
|
8002ffc: edc3 7a00 vstr s15, [r3]
|
|
for (indx = 0; indx < 3; indx++)
|
|
8003000: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
8003004: 3301 adds r3, #1
|
|
8003006: f887 3056 strb.w r3, [r7, #86] @ 0x56
|
|
800300a: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
|
|
800300e: 2b02 cmp r3, #2
|
|
8003010: f67f af74 bls.w 8002efc <bmm350_get_compensated_mag_xyz_temp_data+0xb0>
|
|
}
|
|
|
|
cr_ax_comp_x = (out_data[0] - dev->mag_comp.cross_axis.cross_x_y * out_data[1]) /
|
|
8003014: ed97 7a0e vldr s14, [r7, #56] @ 0x38
|
|
8003018: 683b ldr r3, [r7, #0]
|
|
800301a: edd3 6a15 vldr s13, [r3, #84] @ 0x54
|
|
800301e: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
8003022: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
8003026: ee77 6a67 vsub.f32 s13, s14, s15
|
|
(1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y);
|
|
800302a: 683b ldr r3, [r7, #0]
|
|
800302c: ed93 7a16 vldr s14, [r3, #88] @ 0x58
|
|
8003030: 683b ldr r3, [r7, #0]
|
|
8003032: edd3 7a15 vldr s15, [r3, #84] @ 0x54
|
|
8003036: ee67 7a27 vmul.f32 s15, s14, s15
|
|
800303a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
|
|
800303e: ee37 7a67 vsub.f32 s14, s14, s15
|
|
cr_ax_comp_x = (out_data[0] - dev->mag_comp.cross_axis.cross_x_y * out_data[1]) /
|
|
8003042: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8003046: edc7 7a14 vstr s15, [r7, #80] @ 0x50
|
|
cr_ax_comp_y = (out_data[1] - dev->mag_comp.cross_axis.cross_y_x * out_data[0]) /
|
|
800304a: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
800304e: 683b ldr r3, [r7, #0]
|
|
8003050: edd3 6a16 vldr s13, [r3, #88] @ 0x58
|
|
8003054: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8003058: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
800305c: ee77 6a67 vsub.f32 s13, s14, s15
|
|
(1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y);
|
|
8003060: 683b ldr r3, [r7, #0]
|
|
8003062: ed93 7a16 vldr s14, [r3, #88] @ 0x58
|
|
8003066: 683b ldr r3, [r7, #0]
|
|
8003068: edd3 7a15 vldr s15, [r3, #84] @ 0x54
|
|
800306c: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8003070: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
|
|
8003074: ee37 7a67 vsub.f32 s14, s14, s15
|
|
cr_ax_comp_y = (out_data[1] - dev->mag_comp.cross_axis.cross_y_x * out_data[0]) /
|
|
8003078: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
800307c: edc7 7a13 vstr s15, [r7, #76] @ 0x4c
|
|
cr_ax_comp_z =
|
|
(out_data[2] +
|
|
8003080: ed97 7a10 vldr s14, [r7, #64] @ 0x40
|
|
(out_data[0] *
|
|
8003084: edd7 6a0e vldr s13, [r7, #56] @ 0x38
|
|
(dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_z_y -
|
|
8003088: 683b ldr r3, [r7, #0]
|
|
800308a: ed93 6a16 vldr s12, [r3, #88] @ 0x58
|
|
800308e: 683b ldr r3, [r7, #0]
|
|
8003090: edd3 7a18 vldr s15, [r3, #96] @ 0x60
|
|
8003094: ee26 6a27 vmul.f32 s12, s12, s15
|
|
dev->mag_comp.cross_axis.cross_z_x) - out_data[1] *
|
|
8003098: 683b ldr r3, [r7, #0]
|
|
800309a: edd3 7a17 vldr s15, [r3, #92] @ 0x5c
|
|
(dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_z_y -
|
|
800309e: ee76 7a67 vsub.f32 s15, s12, s15
|
|
(out_data[0] *
|
|
80030a2: ee66 6aa7 vmul.f32 s13, s13, s15
|
|
dev->mag_comp.cross_axis.cross_z_x) - out_data[1] *
|
|
80030a6: ed97 6a0f vldr s12, [r7, #60] @ 0x3c
|
|
(dev->mag_comp.cross_axis.cross_z_y - dev->mag_comp.cross_axis.cross_x_y *
|
|
80030aa: 683b ldr r3, [r7, #0]
|
|
80030ac: edd3 5a18 vldr s11, [r3, #96] @ 0x60
|
|
80030b0: 683b ldr r3, [r7, #0]
|
|
80030b2: ed93 5a15 vldr s10, [r3, #84] @ 0x54
|
|
dev->mag_comp.cross_axis.cross_z_x)) /
|
|
80030b6: 683b ldr r3, [r7, #0]
|
|
80030b8: edd3 7a17 vldr s15, [r3, #92] @ 0x5c
|
|
(dev->mag_comp.cross_axis.cross_z_y - dev->mag_comp.cross_axis.cross_x_y *
|
|
80030bc: ee65 7a27 vmul.f32 s15, s10, s15
|
|
80030c0: ee75 7ae7 vsub.f32 s15, s11, s15
|
|
dev->mag_comp.cross_axis.cross_z_x) - out_data[1] *
|
|
80030c4: ee66 7a27 vmul.f32 s15, s12, s15
|
|
80030c8: ee36 6ae7 vsub.f32 s12, s13, s15
|
|
(1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y));
|
|
80030cc: 683b ldr r3, [r7, #0]
|
|
80030ce: edd3 6a16 vldr s13, [r3, #88] @ 0x58
|
|
80030d2: 683b ldr r3, [r7, #0]
|
|
80030d4: edd3 7a15 vldr s15, [r3, #84] @ 0x54
|
|
80030d8: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80030dc: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
|
|
80030e0: ee76 6ae7 vsub.f32 s13, s13, s15
|
|
dev->mag_comp.cross_axis.cross_z_x)) /
|
|
80030e4: eec6 7a26 vdiv.f32 s15, s12, s13
|
|
cr_ax_comp_z =
|
|
80030e8: ee77 7a27 vadd.f32 s15, s14, s15
|
|
80030ec: edc7 7a12 vstr s15, [r7, #72] @ 0x48
|
|
|
|
out_data[0] = cr_ax_comp_x;
|
|
80030f0: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80030f2: 63bb str r3, [r7, #56] @ 0x38
|
|
out_data[1] = cr_ax_comp_y;
|
|
80030f4: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80030f6: 63fb str r3, [r7, #60] @ 0x3c
|
|
out_data[2] = cr_ax_comp_z;
|
|
80030f8: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80030fa: 643b str r3, [r7, #64] @ 0x40
|
|
}
|
|
|
|
if (rslt == BMM350_OK)
|
|
80030fc: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57
|
|
8003100: 2b00 cmp r3, #0
|
|
8003102: d130 bne.n 8003166 <bmm350_get_compensated_mag_xyz_temp_data+0x31a>
|
|
{
|
|
if ((dev->axis_en & BMM350_EN_X_MSK) == BMM350_DISABLE)
|
|
8003104: 683b ldr r3, [r7, #0]
|
|
8003106: 7d5b ldrb r3, [r3, #21]
|
|
8003108: f003 0301 and.w r3, r3, #1
|
|
800310c: 2b00 cmp r3, #0
|
|
800310e: d104 bne.n 800311a <bmm350_get_compensated_mag_xyz_temp_data+0x2ce>
|
|
{
|
|
mag_temp_data->x = BMM350_DISABLE;
|
|
8003110: 687b ldr r3, [r7, #4]
|
|
8003112: f04f 0200 mov.w r2, #0
|
|
8003116: 601a str r2, [r3, #0]
|
|
8003118: e002 b.n 8003120 <bmm350_get_compensated_mag_xyz_temp_data+0x2d4>
|
|
}
|
|
else
|
|
{
|
|
mag_temp_data->x = out_data[0];
|
|
800311a: 6bba ldr r2, [r7, #56] @ 0x38
|
|
800311c: 687b ldr r3, [r7, #4]
|
|
800311e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
if ((dev->axis_en & BMM350_EN_Y_MSK) == BMM350_DISABLE)
|
|
8003120: 683b ldr r3, [r7, #0]
|
|
8003122: 7d5b ldrb r3, [r3, #21]
|
|
8003124: f003 0302 and.w r3, r3, #2
|
|
8003128: 2b00 cmp r3, #0
|
|
800312a: d104 bne.n 8003136 <bmm350_get_compensated_mag_xyz_temp_data+0x2ea>
|
|
{
|
|
mag_temp_data->y = BMM350_DISABLE;
|
|
800312c: 687b ldr r3, [r7, #4]
|
|
800312e: f04f 0200 mov.w r2, #0
|
|
8003132: 605a str r2, [r3, #4]
|
|
8003134: e002 b.n 800313c <bmm350_get_compensated_mag_xyz_temp_data+0x2f0>
|
|
}
|
|
else
|
|
{
|
|
mag_temp_data->y = out_data[1];
|
|
8003136: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
8003138: 687b ldr r3, [r7, #4]
|
|
800313a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if ((dev->axis_en & BMM350_EN_Z_MSK) == BMM350_DISABLE)
|
|
800313c: 683b ldr r3, [r7, #0]
|
|
800313e: 7d5b ldrb r3, [r3, #21]
|
|
8003140: f003 0304 and.w r3, r3, #4
|
|
8003144: 2b00 cmp r3, #0
|
|
8003146: d104 bne.n 8003152 <bmm350_get_compensated_mag_xyz_temp_data+0x306>
|
|
{
|
|
mag_temp_data->z = BMM350_DISABLE;
|
|
8003148: 687b ldr r3, [r7, #4]
|
|
800314a: f04f 0200 mov.w r2, #0
|
|
800314e: 609a str r2, [r3, #8]
|
|
8003150: e002 b.n 8003158 <bmm350_get_compensated_mag_xyz_temp_data+0x30c>
|
|
}
|
|
else
|
|
{
|
|
mag_temp_data->z = out_data[2];
|
|
8003152: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8003154: 687b ldr r3, [r7, #4]
|
|
8003156: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
mag_temp_data->temperature = out_data[3];
|
|
8003158: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
800315a: 687b ldr r3, [r7, #4]
|
|
800315c: 60da str r2, [r3, #12]
|
|
800315e: e002 b.n 8003166 <bmm350_get_compensated_mag_xyz_temp_data+0x31a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rslt = BMM350_E_NULL_PTR;
|
|
8003160: 23ff movs r3, #255 @ 0xff
|
|
8003162: f887 3057 strb.w r3, [r7, #87] @ 0x57
|
|
}
|
|
|
|
return rslt;
|
|
8003166: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57
|
|
}
|
|
800316a: 4618 mov r0, r3
|
|
800316c: 3758 adds r7, #88 @ 0x58
|
|
800316e: 46bd mov sp, r7
|
|
8003170: bd80 pop {r7, pc}
|
|
|
|
08003172 <bmm350_get_pmu_cmd_status_0>:
|
|
|
|
/*!
|
|
* @brief This API gets the PMU command status 0 value
|
|
*/
|
|
int8_t bmm350_get_pmu_cmd_status_0(struct bmm350_pmu_cmd_status_0 *pmu_cmd_stat_0, struct bmm350_dev *dev)
|
|
{
|
|
8003172: b580 push {r7, lr}
|
|
8003174: b084 sub sp, #16
|
|
8003176: af00 add r7, sp, #0
|
|
8003178: 6078 str r0, [r7, #4]
|
|
800317a: 6039 str r1, [r7, #0]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
uint8_t reg_data;
|
|
|
|
if (pmu_cmd_stat_0 != NULL)
|
|
800317c: 687b ldr r3, [r7, #4]
|
|
800317e: 2b00 cmp r3, #0
|
|
8003180: d038 beq.n 80031f4 <bmm350_get_pmu_cmd_status_0+0x82>
|
|
{
|
|
/* Get PMU command status 0 data */
|
|
rslt = bmm350_get_regs(BMM350_REG_PMU_CMD_STATUS_0, ®_data, 1, dev);
|
|
8003182: f107 010e add.w r1, r7, #14
|
|
8003186: 683b ldr r3, [r7, #0]
|
|
8003188: 2201 movs r2, #1
|
|
800318a: 2007 movs r0, #7
|
|
800318c: f7ff fb64 bl 8002858 <bmm350_get_regs>
|
|
8003190: 4603 mov r3, r0
|
|
8003192: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BMM350_OK)
|
|
8003194: f997 300f ldrsb.w r3, [r7, #15]
|
|
8003198: 2b00 cmp r3, #0
|
|
800319a: d12d bne.n 80031f8 <bmm350_get_pmu_cmd_status_0+0x86>
|
|
{
|
|
pmu_cmd_stat_0->pmu_cmd_busy = BMM350_GET_BITS_POS_0(reg_data, BMM350_PMU_CMD_BUSY);
|
|
800319c: 7bbb ldrb r3, [r7, #14]
|
|
800319e: f003 0301 and.w r3, r3, #1
|
|
80031a2: b2da uxtb r2, r3
|
|
80031a4: 687b ldr r3, [r7, #4]
|
|
80031a6: 701a strb r2, [r3, #0]
|
|
|
|
pmu_cmd_stat_0->odr_ovwr = BMM350_GET_BITS(reg_data, BMM350_ODR_OVWR);
|
|
80031a8: 7bbb ldrb r3, [r7, #14]
|
|
80031aa: 105b asrs r3, r3, #1
|
|
80031ac: b2db uxtb r3, r3
|
|
80031ae: f003 0301 and.w r3, r3, #1
|
|
80031b2: b2da uxtb r2, r3
|
|
80031b4: 687b ldr r3, [r7, #4]
|
|
80031b6: 705a strb r2, [r3, #1]
|
|
|
|
pmu_cmd_stat_0->avr_ovwr = BMM350_GET_BITS(reg_data, BMM350_AVG_OVWR);
|
|
80031b8: 7bbb ldrb r3, [r7, #14]
|
|
80031ba: 109b asrs r3, r3, #2
|
|
80031bc: b2db uxtb r3, r3
|
|
80031be: f003 0301 and.w r3, r3, #1
|
|
80031c2: b2da uxtb r2, r3
|
|
80031c4: 687b ldr r3, [r7, #4]
|
|
80031c6: 709a strb r2, [r3, #2]
|
|
|
|
pmu_cmd_stat_0->pwr_mode_is_normal = BMM350_GET_BITS(reg_data, BMM350_PWR_MODE_IS_NORMAL);
|
|
80031c8: 7bbb ldrb r3, [r7, #14]
|
|
80031ca: 10db asrs r3, r3, #3
|
|
80031cc: b2db uxtb r3, r3
|
|
80031ce: f003 0301 and.w r3, r3, #1
|
|
80031d2: b2da uxtb r2, r3
|
|
80031d4: 687b ldr r3, [r7, #4]
|
|
80031d6: 70da strb r2, [r3, #3]
|
|
|
|
pmu_cmd_stat_0->cmd_is_illegal = BMM350_GET_BITS(reg_data, BMM350_CMD_IS_ILLEGAL);
|
|
80031d8: 7bbb ldrb r3, [r7, #14]
|
|
80031da: 111b asrs r3, r3, #4
|
|
80031dc: b2db uxtb r3, r3
|
|
80031de: f003 0301 and.w r3, r3, #1
|
|
80031e2: b2da uxtb r2, r3
|
|
80031e4: 687b ldr r3, [r7, #4]
|
|
80031e6: 711a strb r2, [r3, #4]
|
|
|
|
pmu_cmd_stat_0->pmu_cmd_value = BMM350_GET_BITS(reg_data, BMM350_PMU_CMD_VALUE);
|
|
80031e8: 7bbb ldrb r3, [r7, #14]
|
|
80031ea: 095b lsrs r3, r3, #5
|
|
80031ec: b2da uxtb r2, r3
|
|
80031ee: 687b ldr r3, [r7, #4]
|
|
80031f0: 715a strb r2, [r3, #5]
|
|
80031f2: e001 b.n 80031f8 <bmm350_get_pmu_cmd_status_0+0x86>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rslt = BMM350_E_NULL_PTR;
|
|
80031f4: 23ff movs r3, #255 @ 0xff
|
|
80031f6: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return rslt;
|
|
80031f8: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
80031fc: 4618 mov r0, r3
|
|
80031fe: 3710 adds r7, #16
|
|
8003200: 46bd mov sp, r7
|
|
8003202: bd80 pop {r7, pc}
|
|
|
|
08003204 <null_ptr_check>:
|
|
/*!
|
|
* @brief This internal API is used to validate the device structure pointer for
|
|
* null conditions.
|
|
*/
|
|
static int8_t null_ptr_check(const struct bmm350_dev *dev)
|
|
{
|
|
8003204: b480 push {r7}
|
|
8003206: b085 sub sp, #20
|
|
8003208: af00 add r7, sp, #0
|
|
800320a: 6078 str r0, [r7, #4]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
if ((dev == NULL) || (dev->read == NULL) || (dev->write == NULL) || (dev->delay_us == NULL))
|
|
800320c: 687b ldr r3, [r7, #4]
|
|
800320e: 2b00 cmp r3, #0
|
|
8003210: d00b beq.n 800322a <null_ptr_check+0x26>
|
|
8003212: 687b ldr r3, [r7, #4]
|
|
8003214: 689b ldr r3, [r3, #8]
|
|
8003216: 2b00 cmp r3, #0
|
|
8003218: d007 beq.n 800322a <null_ptr_check+0x26>
|
|
800321a: 687b ldr r3, [r7, #4]
|
|
800321c: 68db ldr r3, [r3, #12]
|
|
800321e: 2b00 cmp r3, #0
|
|
8003220: d003 beq.n 800322a <null_ptr_check+0x26>
|
|
8003222: 687b ldr r3, [r7, #4]
|
|
8003224: 691b ldr r3, [r3, #16]
|
|
8003226: 2b00 cmp r3, #0
|
|
8003228: d102 bne.n 8003230 <null_ptr_check+0x2c>
|
|
{
|
|
/* Device structure pointer is not valid */
|
|
rslt = BMM350_E_NULL_PTR;
|
|
800322a: 23ff movs r3, #255 @ 0xff
|
|
800322c: 73fb strb r3, [r7, #15]
|
|
800322e: e001 b.n 8003234 <null_ptr_check+0x30>
|
|
}
|
|
else
|
|
{
|
|
/* Device structure is fine */
|
|
rslt = BMM350_OK;
|
|
8003230: 2300 movs r3, #0
|
|
8003232: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return rslt;
|
|
8003234: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8003238: 4618 mov r0, r3
|
|
800323a: 3714 adds r7, #20
|
|
800323c: 46bd mov sp, r7
|
|
800323e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003242: 4770 bx lr
|
|
|
|
08003244 <fix_sign>:
|
|
|
|
/*!
|
|
* @brief This internal API converts the raw data from the IC data registers to signed integer
|
|
*/
|
|
static int32_t fix_sign(uint32_t inval, int8_t number_of_bits)
|
|
{
|
|
8003244: b480 push {r7}
|
|
8003246: b085 sub sp, #20
|
|
8003248: af00 add r7, sp, #0
|
|
800324a: 6078 str r0, [r7, #4]
|
|
800324c: 460b mov r3, r1
|
|
800324e: 70fb strb r3, [r7, #3]
|
|
int32_t power = 0;
|
|
8003250: 2300 movs r3, #0
|
|
8003252: 60fb str r3, [r7, #12]
|
|
int32_t retval;
|
|
|
|
switch (number_of_bits)
|
|
8003254: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8003258: 3b08 subs r3, #8
|
|
800325a: 2b10 cmp r3, #16
|
|
800325c: d837 bhi.n 80032ce <fix_sign+0x8a>
|
|
800325e: a201 add r2, pc, #4 @ (adr r2, 8003264 <fix_sign+0x20>)
|
|
8003260: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8003264: 080032a9 .word 0x080032a9
|
|
8003268: 080032cf .word 0x080032cf
|
|
800326c: 080032cf .word 0x080032cf
|
|
8003270: 080032cf .word 0x080032cf
|
|
8003274: 080032af .word 0x080032af
|
|
8003278: 080032cf .word 0x080032cf
|
|
800327c: 080032cf .word 0x080032cf
|
|
8003280: 080032cf .word 0x080032cf
|
|
8003284: 080032b7 .word 0x080032b7
|
|
8003288: 080032cf .word 0x080032cf
|
|
800328c: 080032cf .word 0x080032cf
|
|
8003290: 080032cf .word 0x080032cf
|
|
8003294: 080032cf .word 0x080032cf
|
|
8003298: 080032bf .word 0x080032bf
|
|
800329c: 080032cf .word 0x080032cf
|
|
80032a0: 080032cf .word 0x080032cf
|
|
80032a4: 080032c7 .word 0x080032c7
|
|
{
|
|
case BMM350_SIGNED_8_BIT:
|
|
power = 128; /* 2^7 */
|
|
80032a8: 2380 movs r3, #128 @ 0x80
|
|
80032aa: 60fb str r3, [r7, #12]
|
|
break;
|
|
80032ac: e012 b.n 80032d4 <fix_sign+0x90>
|
|
|
|
case BMM350_SIGNED_12_BIT:
|
|
power = 2048; /* 2^11 */
|
|
80032ae: f44f 6300 mov.w r3, #2048 @ 0x800
|
|
80032b2: 60fb str r3, [r7, #12]
|
|
break;
|
|
80032b4: e00e b.n 80032d4 <fix_sign+0x90>
|
|
|
|
case BMM350_SIGNED_16_BIT:
|
|
power = 32768; /* 2^15 */
|
|
80032b6: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80032ba: 60fb str r3, [r7, #12]
|
|
break;
|
|
80032bc: e00a b.n 80032d4 <fix_sign+0x90>
|
|
|
|
case BMM350_SIGNED_21_BIT:
|
|
power = 1048576; /* 2^20 */
|
|
80032be: f44f 1380 mov.w r3, #1048576 @ 0x100000
|
|
80032c2: 60fb str r3, [r7, #12]
|
|
break;
|
|
80032c4: e006 b.n 80032d4 <fix_sign+0x90>
|
|
|
|
case BMM350_SIGNED_24_BIT:
|
|
power = 8388608; /* 2^23 */
|
|
80032c6: f44f 0300 mov.w r3, #8388608 @ 0x800000
|
|
80032ca: 60fb str r3, [r7, #12]
|
|
break;
|
|
80032cc: e002 b.n 80032d4 <fix_sign+0x90>
|
|
|
|
default:
|
|
power = 0;
|
|
80032ce: 2300 movs r3, #0
|
|
80032d0: 60fb str r3, [r7, #12]
|
|
break;
|
|
80032d2: bf00 nop
|
|
}
|
|
|
|
retval = (int32_t)inval;
|
|
80032d4: 687b ldr r3, [r7, #4]
|
|
80032d6: 60bb str r3, [r7, #8]
|
|
|
|
if (retval >= power)
|
|
80032d8: 68ba ldr r2, [r7, #8]
|
|
80032da: 68fb ldr r3, [r7, #12]
|
|
80032dc: 429a cmp r2, r3
|
|
80032de: db04 blt.n 80032ea <fix_sign+0xa6>
|
|
{
|
|
retval = retval - (power * 2);
|
|
80032e0: 68fb ldr r3, [r7, #12]
|
|
80032e2: 005b lsls r3, r3, #1
|
|
80032e4: 68ba ldr r2, [r7, #8]
|
|
80032e6: 1ad3 subs r3, r2, r3
|
|
80032e8: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
return retval;
|
|
80032ea: 68bb ldr r3, [r7, #8]
|
|
}
|
|
80032ec: 4618 mov r0, r3
|
|
80032ee: 3714 adds r7, #20
|
|
80032f0: 46bd mov sp, r7
|
|
80032f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80032f6: 4770 bx lr
|
|
|
|
080032f8 <read_otp_word>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to read OTP word
|
|
*/
|
|
static int8_t read_otp_word(uint8_t addr, uint16_t *lsb_msb, struct bmm350_dev *dev)
|
|
{
|
|
80032f8: b580 push {r7, lr}
|
|
80032fa: b086 sub sp, #24
|
|
80032fc: af00 add r7, sp, #0
|
|
80032fe: 4603 mov r3, r0
|
|
8003300: 60b9 str r1, [r7, #8]
|
|
8003302: 607a str r2, [r7, #4]
|
|
8003304: 73fb strb r3, [r7, #15]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
uint8_t otp_cmd, otp_status = 0, otp_err = BMM350_OTP_STATUS_NO_ERROR, lsb = 0, msb = 0;
|
|
8003306: 2300 movs r3, #0
|
|
8003308: 753b strb r3, [r7, #20]
|
|
800330a: 2300 movs r3, #0
|
|
800330c: 75bb strb r3, [r7, #22]
|
|
800330e: 2300 movs r3, #0
|
|
8003310: 74fb strb r3, [r7, #19]
|
|
8003312: 2300 movs r3, #0
|
|
8003314: 74bb strb r3, [r7, #18]
|
|
|
|
if (lsb_msb != NULL)
|
|
8003316: 68bb ldr r3, [r7, #8]
|
|
8003318: 2b00 cmp r3, #0
|
|
800331a: f000 8087 beq.w 800342c <read_otp_word+0x134>
|
|
{
|
|
/* Set OTP command at specified address */
|
|
otp_cmd = BMM350_OTP_CMD_DIR_READ | (addr & BMM350_OTP_WORD_ADDR_MSK);
|
|
800331e: f997 300f ldrsb.w r3, [r7, #15]
|
|
8003322: f003 031f and.w r3, r3, #31
|
|
8003326: b25b sxtb r3, r3
|
|
8003328: f043 0320 orr.w r3, r3, #32
|
|
800332c: b25b sxtb r3, r3
|
|
800332e: b2db uxtb r3, r3
|
|
8003330: 757b strb r3, [r7, #21]
|
|
rslt = bmm350_set_regs(BMM350_REG_OTP_CMD_REG, &otp_cmd, 1, dev);
|
|
8003332: f107 0115 add.w r1, r7, #21
|
|
8003336: 687b ldr r3, [r7, #4]
|
|
8003338: 2201 movs r2, #1
|
|
800333a: 2050 movs r0, #80 @ 0x50
|
|
800333c: f7ff fa58 bl 80027f0 <bmm350_set_regs>
|
|
8003340: 4603 mov r3, r0
|
|
8003342: 75fb strb r3, [r7, #23]
|
|
if (rslt == BMM350_OK)
|
|
8003344: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8003348: 2b00 cmp r3, #0
|
|
800334a: d14c bne.n 80033e6 <read_otp_word+0xee>
|
|
{
|
|
do
|
|
{
|
|
rslt = bmm350_delay_us(300, dev);
|
|
800334c: 6879 ldr r1, [r7, #4]
|
|
800334e: f44f 7096 mov.w r0, #300 @ 0x12c
|
|
8003352: f7ff fad6 bl 8002902 <bmm350_delay_us>
|
|
8003356: 4603 mov r3, r0
|
|
8003358: 75fb strb r3, [r7, #23]
|
|
|
|
if (rslt == BMM350_OK)
|
|
800335a: f997 3017 ldrsb.w r3, [r7, #23]
|
|
800335e: 2b00 cmp r3, #0
|
|
8003360: d10f bne.n 8003382 <read_otp_word+0x8a>
|
|
{
|
|
/* Get OTP status */
|
|
rslt = bmm350_get_regs(BMM350_REG_OTP_STATUS_REG, &otp_status, 1, dev);
|
|
8003362: f107 0114 add.w r1, r7, #20
|
|
8003366: 687b ldr r3, [r7, #4]
|
|
8003368: 2201 movs r2, #1
|
|
800336a: 2055 movs r0, #85 @ 0x55
|
|
800336c: f7ff fa74 bl 8002858 <bmm350_get_regs>
|
|
8003370: 4603 mov r3, r0
|
|
8003372: 75fb strb r3, [r7, #23]
|
|
|
|
otp_err = BMM350_OTP_STATUS_ERROR(otp_status);
|
|
8003374: 7d3b ldrb r3, [r7, #20]
|
|
8003376: f023 031f bic.w r3, r3, #31
|
|
800337a: 75bb strb r3, [r7, #22]
|
|
if (otp_err != BMM350_OTP_STATUS_NO_ERROR)
|
|
800337c: 7dbb ldrb r3, [r7, #22]
|
|
800337e: 2b00 cmp r3, #0
|
|
8003380: d109 bne.n 8003396 <read_otp_word+0x9e>
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
} while ((!(otp_status & BMM350_OTP_STATUS_CMD_DONE)) && (rslt == BMM350_OK));
|
|
8003382: 7d3b ldrb r3, [r7, #20]
|
|
8003384: f003 0301 and.w r3, r3, #1
|
|
8003388: 2b00 cmp r3, #0
|
|
800338a: d105 bne.n 8003398 <read_otp_word+0xa0>
|
|
800338c: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8003390: 2b00 cmp r3, #0
|
|
8003392: d0db beq.n 800334c <read_otp_word+0x54>
|
|
8003394: e000 b.n 8003398 <read_otp_word+0xa0>
|
|
break;
|
|
8003396: bf00 nop
|
|
|
|
if (otp_err != BMM350_OTP_STATUS_NO_ERROR)
|
|
8003398: 7dbb ldrb r3, [r7, #22]
|
|
800339a: 2b00 cmp r3, #0
|
|
800339c: d023 beq.n 80033e6 <read_otp_word+0xee>
|
|
{
|
|
switch (otp_err)
|
|
800339e: 7dbb ldrb r3, [r7, #22]
|
|
80033a0: 2ba0 cmp r3, #160 @ 0xa0
|
|
80033a2: d01a beq.n 80033da <read_otp_word+0xe2>
|
|
80033a4: 2ba0 cmp r3, #160 @ 0xa0
|
|
80033a6: dc1b bgt.n 80033e0 <read_otp_word+0xe8>
|
|
80033a8: 2b80 cmp r3, #128 @ 0x80
|
|
80033aa: d013 beq.n 80033d4 <read_otp_word+0xdc>
|
|
80033ac: 2b80 cmp r3, #128 @ 0x80
|
|
80033ae: dc17 bgt.n 80033e0 <read_otp_word+0xe8>
|
|
80033b0: 2b60 cmp r3, #96 @ 0x60
|
|
80033b2: d00c beq.n 80033ce <read_otp_word+0xd6>
|
|
80033b4: 2b60 cmp r3, #96 @ 0x60
|
|
80033b6: dc13 bgt.n 80033e0 <read_otp_word+0xe8>
|
|
80033b8: 2b20 cmp r3, #32
|
|
80033ba: d002 beq.n 80033c2 <read_otp_word+0xca>
|
|
80033bc: 2b40 cmp r3, #64 @ 0x40
|
|
80033be: d003 beq.n 80033c8 <read_otp_word+0xd0>
|
|
80033c0: e00e b.n 80033e0 <read_otp_word+0xe8>
|
|
{
|
|
case BMM350_OTP_STATUS_BOOT_ERR:
|
|
rslt = BMM350_E_OTP_BOOT;
|
|
80033c2: 23f7 movs r3, #247 @ 0xf7
|
|
80033c4: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80033c6: e00e b.n 80033e6 <read_otp_word+0xee>
|
|
case BMM350_OTP_STATUS_PAGE_RD_ERR:
|
|
rslt = BMM350_E_OTP_PAGE_RD;
|
|
80033c8: 23f6 movs r3, #246 @ 0xf6
|
|
80033ca: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80033cc: e00b b.n 80033e6 <read_otp_word+0xee>
|
|
case BMM350_OTP_STATUS_PAGE_PRG_ERR:
|
|
rslt = BMM350_E_OTP_PAGE_PRG;
|
|
80033ce: 23f5 movs r3, #245 @ 0xf5
|
|
80033d0: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80033d2: e008 b.n 80033e6 <read_otp_word+0xee>
|
|
case BMM350_OTP_STATUS_SIGN_ERR:
|
|
rslt = BMM350_E_OTP_SIGN;
|
|
80033d4: 23f4 movs r3, #244 @ 0xf4
|
|
80033d6: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80033d8: e005 b.n 80033e6 <read_otp_word+0xee>
|
|
case BMM350_OTP_STATUS_INV_CMD_ERR:
|
|
rslt = BMM350_E_OTP_INV_CMD;
|
|
80033da: 23f3 movs r3, #243 @ 0xf3
|
|
80033dc: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80033de: e002 b.n 80033e6 <read_otp_word+0xee>
|
|
default:
|
|
rslt = BMM350_E_OTP_UNDEFINED;
|
|
80033e0: 23f2 movs r3, #242 @ 0xf2
|
|
80033e2: 75fb strb r3, [r7, #23]
|
|
break;
|
|
80033e4: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
|
|
if (rslt == BMM350_OK)
|
|
80033e6: f997 3017 ldrsb.w r3, [r7, #23]
|
|
80033ea: 2b00 cmp r3, #0
|
|
80033ec: d120 bne.n 8003430 <read_otp_word+0x138>
|
|
{
|
|
/* Get OTP MSB data */
|
|
rslt = bmm350_get_regs(BMM350_REG_OTP_DATA_MSB_REG, &msb, 1, dev);
|
|
80033ee: f107 0112 add.w r1, r7, #18
|
|
80033f2: 687b ldr r3, [r7, #4]
|
|
80033f4: 2201 movs r2, #1
|
|
80033f6: 2052 movs r0, #82 @ 0x52
|
|
80033f8: f7ff fa2e bl 8002858 <bmm350_get_regs>
|
|
80033fc: 4603 mov r3, r0
|
|
80033fe: 75fb strb r3, [r7, #23]
|
|
if (rslt == BMM350_OK)
|
|
8003400: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8003404: 2b00 cmp r3, #0
|
|
8003406: d113 bne.n 8003430 <read_otp_word+0x138>
|
|
{
|
|
/* Get OTP LSB data */
|
|
rslt = bmm350_get_regs(BMM350_REG_OTP_DATA_LSB_REG, &lsb, 1, dev);
|
|
8003408: f107 0113 add.w r1, r7, #19
|
|
800340c: 687b ldr r3, [r7, #4]
|
|
800340e: 2201 movs r2, #1
|
|
8003410: 2053 movs r0, #83 @ 0x53
|
|
8003412: f7ff fa21 bl 8002858 <bmm350_get_regs>
|
|
8003416: 4603 mov r3, r0
|
|
8003418: 75fb strb r3, [r7, #23]
|
|
*lsb_msb = ((uint16_t)(msb << 8) | lsb) & 0xFFFF;
|
|
800341a: 7cbb ldrb r3, [r7, #18]
|
|
800341c: 021b lsls r3, r3, #8
|
|
800341e: b29b uxth r3, r3
|
|
8003420: 7cfa ldrb r2, [r7, #19]
|
|
8003422: 4313 orrs r3, r2
|
|
8003424: b29a uxth r2, r3
|
|
8003426: 68bb ldr r3, [r7, #8]
|
|
8003428: 801a strh r2, [r3, #0]
|
|
800342a: e001 b.n 8003430 <read_otp_word+0x138>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rslt = BMM350_E_NULL_PTR;
|
|
800342c: 23ff movs r3, #255 @ 0xff
|
|
800342e: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return rslt;
|
|
8003430: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
8003434: 4618 mov r0, r3
|
|
8003436: 3718 adds r7, #24
|
|
8003438: 46bd mov sp, r7
|
|
800343a: bd80 pop {r7, pc}
|
|
|
|
0800343c <update_mag_off_sens>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to update magnetometer offset and sensitivity data.
|
|
*/
|
|
static void update_mag_off_sens(struct bmm350_dev *dev)
|
|
{
|
|
800343c: b580 push {r7, lr}
|
|
800343e: b088 sub sp, #32
|
|
8003440: af00 add r7, sp, #0
|
|
8003442: 6078 str r0, [r7, #4]
|
|
uint16_t off_x_lsb_msb, off_y_lsb_msb, off_z_lsb_msb, t_off = 0;
|
|
8003444: 2300 movs r3, #0
|
|
8003446: 83fb strh r3, [r7, #30]
|
|
uint8_t sens_x, sens_y, sens_z, t_sens = 0;
|
|
8003448: 2300 movs r3, #0
|
|
800344a: 777b strb r3, [r7, #29]
|
|
uint8_t tco_x, tco_y, tco_z = 0;
|
|
800344c: 2300 movs r3, #0
|
|
800344e: 773b strb r3, [r7, #28]
|
|
uint8_t tcs_x, tcs_y, tcs_z = 0;
|
|
8003450: 2300 movs r3, #0
|
|
8003452: 76fb strb r3, [r7, #27]
|
|
uint8_t cross_x_y, cross_y_x, cross_z_x, cross_z_y = 0;
|
|
8003454: 2300 movs r3, #0
|
|
8003456: 76bb strb r3, [r7, #26]
|
|
|
|
off_x_lsb_msb = dev->otp_data[BMM350_MAG_OFFSET_X] & 0x0FFF;
|
|
8003458: 687b ldr r3, [r7, #4]
|
|
800345a: f8b3 3080 ldrh.w r3, [r3, #128] @ 0x80
|
|
800345e: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003462: 833b strh r3, [r7, #24]
|
|
off_y_lsb_msb = ((dev->otp_data[BMM350_MAG_OFFSET_X] & 0xF000) >> 4) +
|
|
8003464: 687b ldr r3, [r7, #4]
|
|
8003466: f8b3 3080 ldrh.w r3, [r3, #128] @ 0x80
|
|
800346a: 111b asrs r3, r3, #4
|
|
800346c: b21b sxth r3, r3
|
|
800346e: f403 6370 and.w r3, r3, #3840 @ 0xf00
|
|
8003472: b21a sxth r2, r3
|
|
(dev->otp_data[BMM350_MAG_OFFSET_Y] & BMM350_LSB_MASK);
|
|
8003474: 687b ldr r3, [r7, #4]
|
|
8003476: f8b3 3082 ldrh.w r3, [r3, #130] @ 0x82
|
|
800347a: b21b sxth r3, r3
|
|
800347c: b2db uxtb r3, r3
|
|
800347e: b21b sxth r3, r3
|
|
off_y_lsb_msb = ((dev->otp_data[BMM350_MAG_OFFSET_X] & 0xF000) >> 4) +
|
|
8003480: 4313 orrs r3, r2
|
|
8003482: b21b sxth r3, r3
|
|
8003484: 82fb strh r3, [r7, #22]
|
|
off_z_lsb_msb = (dev->otp_data[BMM350_MAG_OFFSET_Y] & 0x0F00) +
|
|
8003486: 687b ldr r3, [r7, #4]
|
|
8003488: f8b3 3082 ldrh.w r3, [r3, #130] @ 0x82
|
|
800348c: b21b sxth r3, r3
|
|
800348e: f403 6370 and.w r3, r3, #3840 @ 0xf00
|
|
8003492: b21a sxth r2, r3
|
|
(dev->otp_data[BMM350_MAG_OFFSET_Z] & BMM350_LSB_MASK);
|
|
8003494: 687b ldr r3, [r7, #4]
|
|
8003496: f8b3 3084 ldrh.w r3, [r3, #132] @ 0x84
|
|
800349a: b21b sxth r3, r3
|
|
800349c: b2db uxtb r3, r3
|
|
800349e: b21b sxth r3, r3
|
|
off_z_lsb_msb = (dev->otp_data[BMM350_MAG_OFFSET_Y] & 0x0F00) +
|
|
80034a0: 4313 orrs r3, r2
|
|
80034a2: b21b sxth r3, r3
|
|
80034a4: 82bb strh r3, [r7, #20]
|
|
t_off = dev->otp_data[BMM350_TEMP_OFF_SENS] & BMM350_LSB_MASK;
|
|
80034a6: 687b ldr r3, [r7, #4]
|
|
80034a8: f8b3 307e ldrh.w r3, [r3, #126] @ 0x7e
|
|
80034ac: b2db uxtb r3, r3
|
|
80034ae: 83fb strh r3, [r7, #30]
|
|
dev->mag_comp.dut_offset_coef.offset_z = f16_from_int(fix_sign(off_z_lsb_msb, BMM350_SIGNED_12_BIT));
|
|
dev->mag_comp.dut_offset_coef.t_offs = fixed_mul_A48_16(f16_from_int(fix_sign(t_off, BMM350_SIGNED_8_BIT)),
|
|
A48_16_0_2);
|
|
|
|
#else
|
|
dev->mag_comp.dut_offset_coef.offset_x = fix_sign(off_x_lsb_msb, BMM350_SIGNED_12_BIT);
|
|
80034b0: 8b3b ldrh r3, [r7, #24]
|
|
80034b2: 210c movs r1, #12
|
|
80034b4: 4618 mov r0, r3
|
|
80034b6: f7ff fec5 bl 8003244 <fix_sign>
|
|
80034ba: ee07 0a90 vmov s15, r0
|
|
80034be: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80034c2: 687b ldr r3, [r7, #4]
|
|
80034c4: edc3 7a07 vstr s15, [r3, #28]
|
|
dev->mag_comp.dut_offset_coef.offset_y = fix_sign(off_y_lsb_msb, BMM350_SIGNED_12_BIT);
|
|
80034c8: 8afb ldrh r3, [r7, #22]
|
|
80034ca: 210c movs r1, #12
|
|
80034cc: 4618 mov r0, r3
|
|
80034ce: f7ff feb9 bl 8003244 <fix_sign>
|
|
80034d2: ee07 0a90 vmov s15, r0
|
|
80034d6: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80034da: 687b ldr r3, [r7, #4]
|
|
80034dc: edc3 7a08 vstr s15, [r3, #32]
|
|
dev->mag_comp.dut_offset_coef.offset_z = fix_sign(off_z_lsb_msb, BMM350_SIGNED_12_BIT);
|
|
80034e0: 8abb ldrh r3, [r7, #20]
|
|
80034e2: 210c movs r1, #12
|
|
80034e4: 4618 mov r0, r3
|
|
80034e6: f7ff fead bl 8003244 <fix_sign>
|
|
80034ea: ee07 0a90 vmov s15, r0
|
|
80034ee: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80034f2: 687b ldr r3, [r7, #4]
|
|
80034f4: edc3 7a09 vstr s15, [r3, #36] @ 0x24
|
|
dev->mag_comp.dut_offset_coef.t_offs = fix_sign(t_off, BMM350_SIGNED_8_BIT) / 5.0f;
|
|
80034f8: 8bfb ldrh r3, [r7, #30]
|
|
80034fa: 2108 movs r1, #8
|
|
80034fc: 4618 mov r0, r3
|
|
80034fe: f7ff fea1 bl 8003244 <fix_sign>
|
|
8003502: ee07 0a90 vmov s15, r0
|
|
8003506: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
800350a: eef1 6a04 vmov.f32 s13, #20 @ 0x40a00000 5.0
|
|
800350e: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
8003512: 687b ldr r3, [r7, #4]
|
|
8003514: edc3 7a06 vstr s15, [r3, #24]
|
|
#endif
|
|
|
|
sens_x = (dev->otp_data[BMM350_MAG_SENS_X] & BMM350_MSB_MASK) >> 8;
|
|
8003518: 687b ldr r3, [r7, #4]
|
|
800351a: f8b3 3084 ldrh.w r3, [r3, #132] @ 0x84
|
|
800351e: 0a1b lsrs r3, r3, #8
|
|
8003520: b29b uxth r3, r3
|
|
8003522: 74fb strb r3, [r7, #19]
|
|
sens_y = (dev->otp_data[BMM350_MAG_SENS_Y] & BMM350_LSB_MASK);
|
|
8003524: 687b ldr r3, [r7, #4]
|
|
8003526: f8b3 3086 ldrh.w r3, [r3, #134] @ 0x86
|
|
800352a: 74bb strb r3, [r7, #18]
|
|
sens_z = (dev->otp_data[BMM350_MAG_SENS_Z] & BMM350_MSB_MASK) >> 8;
|
|
800352c: 687b ldr r3, [r7, #4]
|
|
800352e: f8b3 3086 ldrh.w r3, [r3, #134] @ 0x86
|
|
8003532: 0a1b lsrs r3, r3, #8
|
|
8003534: b29b uxth r3, r3
|
|
8003536: 747b strb r3, [r7, #17]
|
|
t_sens = (dev->otp_data[BMM350_TEMP_OFF_SENS] & BMM350_MSB_MASK) >> 8;
|
|
8003538: 687b ldr r3, [r7, #4]
|
|
800353a: f8b3 307e ldrh.w r3, [r3, #126] @ 0x7e
|
|
800353e: 0a1b lsrs r3, r3, #8
|
|
8003540: b29b uxth r3, r3
|
|
8003542: 777b strb r3, [r7, #29]
|
|
A48_16_0_00390625);
|
|
dev->mag_comp.dut_sensit_coef.t_sens = fixed_mul_A48_16(f16_from_int(fix_sign(t_sens, BMM350_SIGNED_8_BIT)),
|
|
A48_16_0_001953125);
|
|
|
|
#else
|
|
dev->mag_comp.dut_sensit_coef.sens_x = fix_sign(sens_x, BMM350_SIGNED_8_BIT) / 256.0f;
|
|
8003544: 7cfb ldrb r3, [r7, #19]
|
|
8003546: 2108 movs r1, #8
|
|
8003548: 4618 mov r0, r3
|
|
800354a: f7ff fe7b bl 8003244 <fix_sign>
|
|
800354e: ee07 0a90 vmov s15, r0
|
|
8003552: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003556: eddf 6a91 vldr s13, [pc, #580] @ 800379c <update_mag_off_sens+0x360>
|
|
800355a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800355e: 687b ldr r3, [r7, #4]
|
|
8003560: edc3 7a0b vstr s15, [r3, #44] @ 0x2c
|
|
dev->mag_comp.dut_sensit_coef.sens_y = fix_sign(sens_y, BMM350_SIGNED_8_BIT) / 256.0f;
|
|
8003564: 7cbb ldrb r3, [r7, #18]
|
|
8003566: 2108 movs r1, #8
|
|
8003568: 4618 mov r0, r3
|
|
800356a: f7ff fe6b bl 8003244 <fix_sign>
|
|
800356e: ee07 0a90 vmov s15, r0
|
|
8003572: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003576: eddf 6a89 vldr s13, [pc, #548] @ 800379c <update_mag_off_sens+0x360>
|
|
800357a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800357e: 687b ldr r3, [r7, #4]
|
|
8003580: edc3 7a0c vstr s15, [r3, #48] @ 0x30
|
|
dev->mag_comp.dut_sensit_coef.sens_z = fix_sign(sens_z, BMM350_SIGNED_8_BIT) / 256.0f;
|
|
8003584: 7c7b ldrb r3, [r7, #17]
|
|
8003586: 2108 movs r1, #8
|
|
8003588: 4618 mov r0, r3
|
|
800358a: f7ff fe5b bl 8003244 <fix_sign>
|
|
800358e: ee07 0a90 vmov s15, r0
|
|
8003592: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003596: eddf 6a81 vldr s13, [pc, #516] @ 800379c <update_mag_off_sens+0x360>
|
|
800359a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800359e: 687b ldr r3, [r7, #4]
|
|
80035a0: edc3 7a0d vstr s15, [r3, #52] @ 0x34
|
|
dev->mag_comp.dut_sensit_coef.t_sens = fix_sign(t_sens, BMM350_SIGNED_8_BIT) / 512.0f;
|
|
80035a4: 7f7b ldrb r3, [r7, #29]
|
|
80035a6: 2108 movs r1, #8
|
|
80035a8: 4618 mov r0, r3
|
|
80035aa: f7ff fe4b bl 8003244 <fix_sign>
|
|
80035ae: ee07 0a90 vmov s15, r0
|
|
80035b2: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80035b6: eddf 6a7a vldr s13, [pc, #488] @ 80037a0 <update_mag_off_sens+0x364>
|
|
80035ba: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
80035be: 687b ldr r3, [r7, #4]
|
|
80035c0: edc3 7a0a vstr s15, [r3, #40] @ 0x28
|
|
#endif
|
|
|
|
tco_x = (dev->otp_data[BMM350_MAG_TCO_X] & BMM350_LSB_MASK);
|
|
80035c4: 687b ldr r3, [r7, #4]
|
|
80035c6: f8b3 3088 ldrh.w r3, [r3, #136] @ 0x88
|
|
80035ca: 743b strb r3, [r7, #16]
|
|
tco_y = (dev->otp_data[BMM350_MAG_TCO_Y] & BMM350_LSB_MASK);
|
|
80035cc: 687b ldr r3, [r7, #4]
|
|
80035ce: f8b3 308a ldrh.w r3, [r3, #138] @ 0x8a
|
|
80035d2: 73fb strb r3, [r7, #15]
|
|
tco_z = (dev->otp_data[BMM350_MAG_TCO_Z] & BMM350_LSB_MASK);
|
|
80035d4: 687b ldr r3, [r7, #4]
|
|
80035d6: f8b3 308c ldrh.w r3, [r3, #140] @ 0x8c
|
|
80035da: 773b strb r3, [r7, #28]
|
|
dev->mag_comp.dut_tco.tco_x = fixed_mul_A48_16(f16_from_int(fix_sign(tco_x, BMM350_SIGNED_8_BIT)), A48_16_0_03125);
|
|
dev->mag_comp.dut_tco.tco_y = fixed_mul_A48_16(f16_from_int(fix_sign(tco_y, BMM350_SIGNED_8_BIT)), A48_16_0_03125);
|
|
dev->mag_comp.dut_tco.tco_z = fixed_mul_A48_16(f16_from_int(fix_sign(tco_z, BMM350_SIGNED_8_BIT)), A48_16_0_03125);
|
|
|
|
#else
|
|
dev->mag_comp.dut_tco.tco_x = fix_sign(tco_x, BMM350_SIGNED_8_BIT) / 32.0f;
|
|
80035dc: 7c3b ldrb r3, [r7, #16]
|
|
80035de: 2108 movs r1, #8
|
|
80035e0: 4618 mov r0, r3
|
|
80035e2: f7ff fe2f bl 8003244 <fix_sign>
|
|
80035e6: ee07 0a90 vmov s15, r0
|
|
80035ea: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80035ee: eddf 6a6d vldr s13, [pc, #436] @ 80037a4 <update_mag_off_sens+0x368>
|
|
80035f2: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
80035f6: 687b ldr r3, [r7, #4]
|
|
80035f8: edc3 7a0e vstr s15, [r3, #56] @ 0x38
|
|
dev->mag_comp.dut_tco.tco_y = fix_sign(tco_y, BMM350_SIGNED_8_BIT) / 32.0f;
|
|
80035fc: 7bfb ldrb r3, [r7, #15]
|
|
80035fe: 2108 movs r1, #8
|
|
8003600: 4618 mov r0, r3
|
|
8003602: f7ff fe1f bl 8003244 <fix_sign>
|
|
8003606: ee07 0a90 vmov s15, r0
|
|
800360a: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
800360e: eddf 6a65 vldr s13, [pc, #404] @ 80037a4 <update_mag_off_sens+0x368>
|
|
8003612: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
8003616: 687b ldr r3, [r7, #4]
|
|
8003618: edc3 7a0f vstr s15, [r3, #60] @ 0x3c
|
|
dev->mag_comp.dut_tco.tco_z = fix_sign(tco_z, BMM350_SIGNED_8_BIT) / 32.0f;
|
|
800361c: 7f3b ldrb r3, [r7, #28]
|
|
800361e: 2108 movs r1, #8
|
|
8003620: 4618 mov r0, r3
|
|
8003622: f7ff fe0f bl 8003244 <fix_sign>
|
|
8003626: ee07 0a90 vmov s15, r0
|
|
800362a: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
800362e: eddf 6a5d vldr s13, [pc, #372] @ 80037a4 <update_mag_off_sens+0x368>
|
|
8003632: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
8003636: 687b ldr r3, [r7, #4]
|
|
8003638: edc3 7a10 vstr s15, [r3, #64] @ 0x40
|
|
#endif
|
|
|
|
tcs_x = (dev->otp_data[BMM350_MAG_TCS_X] & BMM350_MSB_MASK) >> 8;
|
|
800363c: 687b ldr r3, [r7, #4]
|
|
800363e: f8b3 3088 ldrh.w r3, [r3, #136] @ 0x88
|
|
8003642: 0a1b lsrs r3, r3, #8
|
|
8003644: b29b uxth r3, r3
|
|
8003646: 73bb strb r3, [r7, #14]
|
|
tcs_y = (dev->otp_data[BMM350_MAG_TCS_Y] & BMM350_MSB_MASK) >> 8;
|
|
8003648: 687b ldr r3, [r7, #4]
|
|
800364a: f8b3 308a ldrh.w r3, [r3, #138] @ 0x8a
|
|
800364e: 0a1b lsrs r3, r3, #8
|
|
8003650: b29b uxth r3, r3
|
|
8003652: 737b strb r3, [r7, #13]
|
|
tcs_z = (dev->otp_data[BMM350_MAG_TCS_Z] & BMM350_MSB_MASK) >> 8;
|
|
8003654: 687b ldr r3, [r7, #4]
|
|
8003656: f8b3 308c ldrh.w r3, [r3, #140] @ 0x8c
|
|
800365a: 0a1b lsrs r3, r3, #8
|
|
800365c: b29b uxth r3, r3
|
|
800365e: 76fb strb r3, [r7, #27]
|
|
A48_16_0_00006103515625);
|
|
dev->mag_comp.dut_tcs.tcs_z = fixed_mul_A48_16(f16_from_int(fix_sign(tcs_z, BMM350_SIGNED_8_BIT)),
|
|
A48_16_0_00006103515625);
|
|
|
|
#else
|
|
dev->mag_comp.dut_tcs.tcs_x = fix_sign(tcs_x, BMM350_SIGNED_8_BIT) / 16384.0f;
|
|
8003660: 7bbb ldrb r3, [r7, #14]
|
|
8003662: 2108 movs r1, #8
|
|
8003664: 4618 mov r0, r3
|
|
8003666: f7ff fded bl 8003244 <fix_sign>
|
|
800366a: ee07 0a90 vmov s15, r0
|
|
800366e: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003672: eddf 6a4d vldr s13, [pc, #308] @ 80037a8 <update_mag_off_sens+0x36c>
|
|
8003676: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800367a: 687b ldr r3, [r7, #4]
|
|
800367c: edc3 7a11 vstr s15, [r3, #68] @ 0x44
|
|
dev->mag_comp.dut_tcs.tcs_y = fix_sign(tcs_y, BMM350_SIGNED_8_BIT) / 16384.0f;
|
|
8003680: 7b7b ldrb r3, [r7, #13]
|
|
8003682: 2108 movs r1, #8
|
|
8003684: 4618 mov r0, r3
|
|
8003686: f7ff fddd bl 8003244 <fix_sign>
|
|
800368a: ee07 0a90 vmov s15, r0
|
|
800368e: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003692: eddf 6a45 vldr s13, [pc, #276] @ 80037a8 <update_mag_off_sens+0x36c>
|
|
8003696: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800369a: 687b ldr r3, [r7, #4]
|
|
800369c: edc3 7a12 vstr s15, [r3, #72] @ 0x48
|
|
dev->mag_comp.dut_tcs.tcs_z = fix_sign(tcs_z, BMM350_SIGNED_8_BIT) / 16384.0f;
|
|
80036a0: 7efb ldrb r3, [r7, #27]
|
|
80036a2: 2108 movs r1, #8
|
|
80036a4: 4618 mov r0, r3
|
|
80036a6: f7ff fdcd bl 8003244 <fix_sign>
|
|
80036aa: ee07 0a90 vmov s15, r0
|
|
80036ae: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80036b2: eddf 6a3d vldr s13, [pc, #244] @ 80037a8 <update_mag_off_sens+0x36c>
|
|
80036b6: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
80036ba: 687b ldr r3, [r7, #4]
|
|
80036bc: edc3 7a13 vstr s15, [r3, #76] @ 0x4c
|
|
dev->mag_comp.dut_t0 =
|
|
fixed_add(fixed_mul_A48_16(f16_from_int(fix_sign(dev->otp_data[BMM350_MAG_DUT_T_0], BMM350_SIGNED_16_BIT)),
|
|
A48_16_0_001953125), f16_from_int(23));
|
|
|
|
#else
|
|
dev->mag_comp.dut_t0 = (fix_sign(dev->otp_data[BMM350_MAG_DUT_T_0], BMM350_SIGNED_16_BIT) / 512.0f) + 23.0f;
|
|
80036c0: 687b ldr r3, [r7, #4]
|
|
80036c2: f8b3 3094 ldrh.w r3, [r3, #148] @ 0x94
|
|
80036c6: 2110 movs r1, #16
|
|
80036c8: 4618 mov r0, r3
|
|
80036ca: f7ff fdbb bl 8003244 <fix_sign>
|
|
80036ce: ee07 0a90 vmov s15, r0
|
|
80036d2: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80036d6: eddf 6a32 vldr s13, [pc, #200] @ 80037a0 <update_mag_off_sens+0x364>
|
|
80036da: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
80036de: eeb3 7a07 vmov.f32 s14, #55 @ 0x41b80000 23.0
|
|
80036e2: ee77 7a87 vadd.f32 s15, s15, s14
|
|
80036e6: 687b ldr r3, [r7, #4]
|
|
80036e8: edc3 7a14 vstr s15, [r3, #80] @ 0x50
|
|
#endif
|
|
|
|
cross_x_y = (dev->otp_data[BMM350_CROSS_X_Y] & BMM350_LSB_MASK);
|
|
80036ec: 687b ldr r3, [r7, #4]
|
|
80036ee: f8b3 308e ldrh.w r3, [r3, #142] @ 0x8e
|
|
80036f2: 733b strb r3, [r7, #12]
|
|
cross_y_x = (dev->otp_data[BMM350_CROSS_Y_X] & BMM350_MSB_MASK) >> 8;
|
|
80036f4: 687b ldr r3, [r7, #4]
|
|
80036f6: f8b3 308e ldrh.w r3, [r3, #142] @ 0x8e
|
|
80036fa: 0a1b lsrs r3, r3, #8
|
|
80036fc: b29b uxth r3, r3
|
|
80036fe: 72fb strb r3, [r7, #11]
|
|
cross_z_x = (dev->otp_data[BMM350_CROSS_Z_X] & BMM350_LSB_MASK);
|
|
8003700: 687b ldr r3, [r7, #4]
|
|
8003702: f8b3 3090 ldrh.w r3, [r3, #144] @ 0x90
|
|
8003706: 72bb strb r3, [r7, #10]
|
|
cross_z_y = (dev->otp_data[BMM350_CROSS_Z_Y] & BMM350_MSB_MASK) >> 8;
|
|
8003708: 687b ldr r3, [r7, #4]
|
|
800370a: f8b3 3090 ldrh.w r3, [r3, #144] @ 0x90
|
|
800370e: 0a1b lsrs r3, r3, #8
|
|
8003710: b29b uxth r3, r3
|
|
8003712: 76bb strb r3, [r7, #26]
|
|
A48_16_0_00125);
|
|
dev->mag_comp.cross_axis.cross_z_y = fixed_mul_A48_16(f16_from_int(fix_sign(cross_z_y, BMM350_SIGNED_8_BIT)),
|
|
A48_16_0_00125);
|
|
|
|
#else
|
|
dev->mag_comp.cross_axis.cross_x_y = fix_sign(cross_x_y, BMM350_SIGNED_8_BIT) / 800.0f;
|
|
8003714: 7b3b ldrb r3, [r7, #12]
|
|
8003716: 2108 movs r1, #8
|
|
8003718: 4618 mov r0, r3
|
|
800371a: f7ff fd93 bl 8003244 <fix_sign>
|
|
800371e: ee07 0a90 vmov s15, r0
|
|
8003722: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003726: eddf 6a21 vldr s13, [pc, #132] @ 80037ac <update_mag_off_sens+0x370>
|
|
800372a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800372e: 687b ldr r3, [r7, #4]
|
|
8003730: edc3 7a15 vstr s15, [r3, #84] @ 0x54
|
|
dev->mag_comp.cross_axis.cross_y_x = fix_sign(cross_y_x, BMM350_SIGNED_8_BIT) / 800.0f;
|
|
8003734: 7afb ldrb r3, [r7, #11]
|
|
8003736: 2108 movs r1, #8
|
|
8003738: 4618 mov r0, r3
|
|
800373a: f7ff fd83 bl 8003244 <fix_sign>
|
|
800373e: ee07 0a90 vmov s15, r0
|
|
8003742: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003746: eddf 6a19 vldr s13, [pc, #100] @ 80037ac <update_mag_off_sens+0x370>
|
|
800374a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800374e: 687b ldr r3, [r7, #4]
|
|
8003750: edc3 7a16 vstr s15, [r3, #88] @ 0x58
|
|
dev->mag_comp.cross_axis.cross_z_x = fix_sign(cross_z_x, BMM350_SIGNED_8_BIT) / 800.0f;
|
|
8003754: 7abb ldrb r3, [r7, #10]
|
|
8003756: 2108 movs r1, #8
|
|
8003758: 4618 mov r0, r3
|
|
800375a: f7ff fd73 bl 8003244 <fix_sign>
|
|
800375e: ee07 0a90 vmov s15, r0
|
|
8003762: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003766: eddf 6a11 vldr s13, [pc, #68] @ 80037ac <update_mag_off_sens+0x370>
|
|
800376a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800376e: 687b ldr r3, [r7, #4]
|
|
8003770: edc3 7a17 vstr s15, [r3, #92] @ 0x5c
|
|
dev->mag_comp.cross_axis.cross_z_y = fix_sign(cross_z_y, BMM350_SIGNED_8_BIT) / 800.0f;
|
|
8003774: 7ebb ldrb r3, [r7, #26]
|
|
8003776: 2108 movs r1, #8
|
|
8003778: 4618 mov r0, r3
|
|
800377a: f7ff fd63 bl 8003244 <fix_sign>
|
|
800377e: ee07 0a90 vmov s15, r0
|
|
8003782: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003786: eddf 6a09 vldr s13, [pc, #36] @ 80037ac <update_mag_off_sens+0x370>
|
|
800378a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800378e: 687b ldr r3, [r7, #4]
|
|
8003790: edc3 7a18 vstr s15, [r3, #96] @ 0x60
|
|
#endif
|
|
|
|
}
|
|
8003794: bf00 nop
|
|
8003796: 3720 adds r7, #32
|
|
8003798: 46bd mov sp, r7
|
|
800379a: bd80 pop {r7, pc}
|
|
800379c: 43800000 .word 0x43800000
|
|
80037a0: 44000000 .word 0x44000000
|
|
80037a4: 42000000 .word 0x42000000
|
|
80037a8: 46800000 .word 0x46800000
|
|
80037ac: 44480000 .word 0x44480000
|
|
|
|
080037b0 <read_out_raw_data>:
|
|
|
|
return rslt;
|
|
}
|
|
#else
|
|
static int8_t read_out_raw_data(float *out_data, struct bmm350_dev *dev)
|
|
{
|
|
80037b0: b590 push {r4, r7, lr}
|
|
80037b2: b08d sub sp, #52 @ 0x34
|
|
80037b4: af00 add r7, sp, #0
|
|
80037b6: 6078 str r0, [r7, #4]
|
|
80037b8: 6039 str r1, [r7, #0]
|
|
int8_t rslt;
|
|
|
|
/* Float variable to convert mag lsb to uT and temp lsb to degC */
|
|
float lsb_to_ut_degc[4];
|
|
|
|
struct bmm350_raw_mag_data raw_data = { 0 };
|
|
80037ba: f107 030c add.w r3, r7, #12
|
|
80037be: 2200 movs r2, #0
|
|
80037c0: 601a str r2, [r3, #0]
|
|
80037c2: 605a str r2, [r3, #4]
|
|
80037c4: 609a str r2, [r3, #8]
|
|
80037c6: 60da str r2, [r3, #12]
|
|
|
|
if (out_data != NULL)
|
|
80037c8: 687b ldr r3, [r7, #4]
|
|
80037ca: 2b00 cmp r3, #0
|
|
80037cc: d05b beq.n 8003886 <read_out_raw_data+0xd6>
|
|
{
|
|
rslt = bmm350_read_uncomp_mag_temp_data(&raw_data, dev);
|
|
80037ce: f107 030c add.w r3, r7, #12
|
|
80037d2: 6839 ldr r1, [r7, #0]
|
|
80037d4: 4618 mov r0, r3
|
|
80037d6: f7ff fa0a bl 8002bee <bmm350_read_uncomp_mag_temp_data>
|
|
80037da: 4603 mov r3, r0
|
|
80037dc: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
if (rslt == BMM350_OK)
|
|
80037e0: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
|
|
80037e4: 2b00 cmp r3, #0
|
|
80037e6: d151 bne.n 800388c <read_out_raw_data+0xdc>
|
|
{
|
|
/* Convert mag lsb to uT and temp lsb to degC */
|
|
update_default_coefiecents(lsb_to_ut_degc);
|
|
80037e8: f107 031c add.w r3, r7, #28
|
|
80037ec: 4618 mov r0, r3
|
|
80037ee: f000 f857 bl 80038a0 <update_default_coefiecents>
|
|
|
|
out_data[0] = (float)raw_data.raw_xdata * lsb_to_ut_degc[0];
|
|
80037f2: 68fb ldr r3, [r7, #12]
|
|
80037f4: ee07 3a90 vmov s15, r3
|
|
80037f8: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80037fc: edd7 7a07 vldr s15, [r7, #28]
|
|
8003800: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8003804: 687b ldr r3, [r7, #4]
|
|
8003806: edc3 7a00 vstr s15, [r3]
|
|
out_data[1] = (float)raw_data.raw_ydata * lsb_to_ut_degc[1];
|
|
800380a: 693b ldr r3, [r7, #16]
|
|
800380c: ee07 3a90 vmov s15, r3
|
|
8003810: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003814: edd7 7a08 vldr s15, [r7, #32]
|
|
8003818: 687b ldr r3, [r7, #4]
|
|
800381a: 3304 adds r3, #4
|
|
800381c: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8003820: edc3 7a00 vstr s15, [r3]
|
|
out_data[2] = (float)raw_data.raw_zdata * lsb_to_ut_degc[2];
|
|
8003824: 697b ldr r3, [r7, #20]
|
|
8003826: ee07 3a90 vmov s15, r3
|
|
800382a: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
800382e: edd7 7a09 vldr s15, [r7, #36] @ 0x24
|
|
8003832: 687b ldr r3, [r7, #4]
|
|
8003834: 3308 adds r3, #8
|
|
8003836: ee67 7a27 vmul.f32 s15, s14, s15
|
|
800383a: edc3 7a00 vstr s15, [r3]
|
|
out_data[3] = (float)raw_data.raw_data_t * lsb_to_ut_degc[3];
|
|
800383e: 69bb ldr r3, [r7, #24]
|
|
8003840: ee07 3a90 vmov s15, r3
|
|
8003844: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8003848: edd7 7a0a vldr s15, [r7, #40] @ 0x28
|
|
800384c: 687b ldr r3, [r7, #4]
|
|
800384e: 330c adds r3, #12
|
|
8003850: ee67 7a27 vmul.f32 s15, s14, s15
|
|
8003854: edc3 7a00 vstr s15, [r3]
|
|
|
|
out_data[3] = (float)(out_data[3] - (1 * 25.49));
|
|
8003858: 687b ldr r3, [r7, #4]
|
|
800385a: 330c adds r3, #12
|
|
800385c: 681b ldr r3, [r3, #0]
|
|
800385e: 4618 mov r0, r3
|
|
8003860: f7fc fe4a bl 80004f8 <__aeabi_f2d>
|
|
8003864: a30c add r3, pc, #48 @ (adr r3, 8003898 <read_out_raw_data+0xe8>)
|
|
8003866: e9d3 2300 ldrd r2, r3, [r3]
|
|
800386a: f7fc fce5 bl 8000238 <__aeabi_dsub>
|
|
800386e: 4602 mov r2, r0
|
|
8003870: 460b mov r3, r1
|
|
8003872: 4610 mov r0, r2
|
|
8003874: 4619 mov r1, r3
|
|
8003876: 687b ldr r3, [r7, #4]
|
|
8003878: f103 040c add.w r4, r3, #12
|
|
800387c: f7fd f98c bl 8000b98 <__aeabi_d2f>
|
|
8003880: 4603 mov r3, r0
|
|
8003882: 6023 str r3, [r4, #0]
|
|
8003884: e002 b.n 800388c <read_out_raw_data+0xdc>
|
|
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rslt = BMM350_E_NULL_PTR;
|
|
8003886: 23ff movs r3, #255 @ 0xff
|
|
8003888: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
}
|
|
|
|
return rslt;
|
|
800388c: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
|
|
}
|
|
8003890: 4618 mov r0, r3
|
|
8003892: 3734 adds r7, #52 @ 0x34
|
|
8003894: 46bd mov sp, r7
|
|
8003896: bd90 pop {r4, r7, pc}
|
|
8003898: a3d70a3d .word 0xa3d70a3d
|
|
800389c: 40397d70 .word 0x40397d70
|
|
|
|
080038a0 <update_default_coefiecents>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to convert lsb to uT and degC.
|
|
*/
|
|
static void update_default_coefiecents(float *lsb_to_ut_degc)
|
|
{
|
|
80038a0: b480 push {r7}
|
|
80038a2: b08b sub sp, #44 @ 0x2c
|
|
80038a4: af00 add r7, sp, #0
|
|
80038a6: 6078 str r0, [r7, #4]
|
|
float bxy_sens, bz_sens, temp_sens, ina_xy_gain_trgt, ina_z_gain_trgt, adc_gain, lut_gain;
|
|
float power;
|
|
|
|
bxy_sens = 14.55f;
|
|
80038a8: 4b36 ldr r3, [pc, #216] @ (8003984 <update_default_coefiecents+0xe4>)
|
|
80038aa: 627b str r3, [r7, #36] @ 0x24
|
|
bz_sens = 9.0f;
|
|
80038ac: 4b36 ldr r3, [pc, #216] @ (8003988 <update_default_coefiecents+0xe8>)
|
|
80038ae: 623b str r3, [r7, #32]
|
|
temp_sens = 0.00204f;
|
|
80038b0: 4b36 ldr r3, [pc, #216] @ (800398c <update_default_coefiecents+0xec>)
|
|
80038b2: 61fb str r3, [r7, #28]
|
|
|
|
ina_xy_gain_trgt = 19.46f;
|
|
80038b4: 4b36 ldr r3, [pc, #216] @ (8003990 <update_default_coefiecents+0xf0>)
|
|
80038b6: 61bb str r3, [r7, #24]
|
|
|
|
ina_z_gain_trgt = 31.0;
|
|
80038b8: 4b36 ldr r3, [pc, #216] @ (8003994 <update_default_coefiecents+0xf4>)
|
|
80038ba: 617b str r3, [r7, #20]
|
|
|
|
adc_gain = 1 / 1.5f;
|
|
80038bc: 4b36 ldr r3, [pc, #216] @ (8003998 <update_default_coefiecents+0xf8>)
|
|
80038be: 613b str r3, [r7, #16]
|
|
lut_gain = 0.714607238769531f;
|
|
80038c0: 4b36 ldr r3, [pc, #216] @ (800399c <update_default_coefiecents+0xfc>)
|
|
80038c2: 60fb str r3, [r7, #12]
|
|
|
|
power = (float)(1000000.0 / 1048576.0);
|
|
80038c4: 4b36 ldr r3, [pc, #216] @ (80039a0 <update_default_coefiecents+0x100>)
|
|
80038c6: 60bb str r3, [r7, #8]
|
|
|
|
lsb_to_ut_degc[0] = (power / (bxy_sens * ina_xy_gain_trgt * adc_gain * lut_gain));
|
|
80038c8: ed97 7a09 vldr s14, [r7, #36] @ 0x24
|
|
80038cc: edd7 7a06 vldr s15, [r7, #24]
|
|
80038d0: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80038d4: edd7 7a04 vldr s15, [r7, #16]
|
|
80038d8: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80038dc: edd7 7a03 vldr s15, [r7, #12]
|
|
80038e0: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80038e4: edd7 6a02 vldr s13, [r7, #8]
|
|
80038e8: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
80038ec: 687b ldr r3, [r7, #4]
|
|
80038ee: edc3 7a00 vstr s15, [r3]
|
|
lsb_to_ut_degc[1] = (power / (bxy_sens * ina_xy_gain_trgt * adc_gain * lut_gain));
|
|
80038f2: ed97 7a09 vldr s14, [r7, #36] @ 0x24
|
|
80038f6: edd7 7a06 vldr s15, [r7, #24]
|
|
80038fa: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80038fe: edd7 7a04 vldr s15, [r7, #16]
|
|
8003902: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8003906: edd7 7a03 vldr s15, [r7, #12]
|
|
800390a: ee27 7a27 vmul.f32 s14, s14, s15
|
|
800390e: 687b ldr r3, [r7, #4]
|
|
8003910: 3304 adds r3, #4
|
|
8003912: edd7 6a02 vldr s13, [r7, #8]
|
|
8003916: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
800391a: edc3 7a00 vstr s15, [r3]
|
|
lsb_to_ut_degc[2] = (power / (bz_sens * ina_z_gain_trgt * adc_gain * lut_gain));
|
|
800391e: ed97 7a08 vldr s14, [r7, #32]
|
|
8003922: edd7 7a05 vldr s15, [r7, #20]
|
|
8003926: ee27 7a27 vmul.f32 s14, s14, s15
|
|
800392a: edd7 7a04 vldr s15, [r7, #16]
|
|
800392e: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8003932: edd7 7a03 vldr s15, [r7, #12]
|
|
8003936: ee27 7a27 vmul.f32 s14, s14, s15
|
|
800393a: 687b ldr r3, [r7, #4]
|
|
800393c: 3308 adds r3, #8
|
|
800393e: edd7 6a02 vldr s13, [r7, #8]
|
|
8003942: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8003946: edc3 7a00 vstr s15, [r3]
|
|
lsb_to_ut_degc[3] = 1 / (temp_sens * adc_gain * lut_gain * 1048576);
|
|
800394a: ed97 7a07 vldr s14, [r7, #28]
|
|
800394e: edd7 7a04 vldr s15, [r7, #16]
|
|
8003952: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8003956: edd7 7a03 vldr s15, [r7, #12]
|
|
800395a: ee67 7a27 vmul.f32 s15, s14, s15
|
|
800395e: ed9f 7a11 vldr s14, [pc, #68] @ 80039a4 <update_default_coefiecents+0x104>
|
|
8003962: ee27 7a87 vmul.f32 s14, s15, s14
|
|
8003966: 687b ldr r3, [r7, #4]
|
|
8003968: 330c adds r3, #12
|
|
800396a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
|
|
800396e: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8003972: edc3 7a00 vstr s15, [r3]
|
|
}
|
|
8003976: bf00 nop
|
|
8003978: 372c adds r7, #44 @ 0x2c
|
|
800397a: 46bd mov sp, r7
|
|
800397c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003980: 4770 bx lr
|
|
8003982: bf00 nop
|
|
8003984: 4168cccd .word 0x4168cccd
|
|
8003988: 41100000 .word 0x41100000
|
|
800398c: 3b05b185 .word 0x3b05b185
|
|
8003990: 419bae14 .word 0x419bae14
|
|
8003994: 41f80000 .word 0x41f80000
|
|
8003998: 3f2aaaab .word 0x3f2aaaab
|
|
800399c: 3f36f080 .word 0x3f36f080
|
|
80039a0: 3f742400 .word 0x3f742400
|
|
80039a4: 49800000 .word 0x49800000
|
|
|
|
080039a8 <otp_dump_after_boot>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to read OTP data after boot in user mode.
|
|
*/
|
|
static int8_t otp_dump_after_boot(struct bmm350_dev *dev)
|
|
{
|
|
80039a8: b580 push {r7, lr}
|
|
80039aa: b084 sub sp, #16
|
|
80039ac: af00 add r7, sp, #0
|
|
80039ae: 6078 str r0, [r7, #4]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
uint16_t otp_word = 0;
|
|
80039b0: 2300 movs r3, #0
|
|
80039b2: 81bb strh r3, [r7, #12]
|
|
uint8_t indx;
|
|
|
|
for (indx = 0; indx < BMM350_OTP_DATA_LENGTH; indx++)
|
|
80039b4: 2300 movs r3, #0
|
|
80039b6: 73bb strb r3, [r7, #14]
|
|
80039b8: e013 b.n 80039e2 <otp_dump_after_boot+0x3a>
|
|
{
|
|
rslt = read_otp_word(indx, &otp_word, dev);
|
|
80039ba: f107 010c add.w r1, r7, #12
|
|
80039be: 7bbb ldrb r3, [r7, #14]
|
|
80039c0: 687a ldr r2, [r7, #4]
|
|
80039c2: 4618 mov r0, r3
|
|
80039c4: f7ff fc98 bl 80032f8 <read_otp_word>
|
|
80039c8: 4603 mov r3, r0
|
|
80039ca: 73fb strb r3, [r7, #15]
|
|
dev->otp_data[indx] = otp_word;
|
|
80039cc: 7bbb ldrb r3, [r7, #14]
|
|
80039ce: 89b9 ldrh r1, [r7, #12]
|
|
80039d0: 687a ldr r2, [r7, #4]
|
|
80039d2: 3330 adds r3, #48 @ 0x30
|
|
80039d4: 005b lsls r3, r3, #1
|
|
80039d6: 4413 add r3, r2
|
|
80039d8: 460a mov r2, r1
|
|
80039da: 809a strh r2, [r3, #4]
|
|
for (indx = 0; indx < BMM350_OTP_DATA_LENGTH; indx++)
|
|
80039dc: 7bbb ldrb r3, [r7, #14]
|
|
80039de: 3301 adds r3, #1
|
|
80039e0: 73bb strb r3, [r7, #14]
|
|
80039e2: 7bbb ldrb r3, [r7, #14]
|
|
80039e4: 2b1f cmp r3, #31
|
|
80039e6: d9e8 bls.n 80039ba <otp_dump_after_boot+0x12>
|
|
}
|
|
|
|
dev->var_id = (dev->otp_data[30] & 0x7f00) >> 9;
|
|
80039e8: 687b ldr r3, [r7, #4]
|
|
80039ea: f8b3 30a0 ldrh.w r3, [r3, #160] @ 0xa0
|
|
80039ee: 125b asrs r3, r3, #9
|
|
80039f0: b2db uxtb r3, r3
|
|
80039f2: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
80039f6: b2da uxtb r2, r3
|
|
80039f8: 687b ldr r3, [r7, #4]
|
|
80039fa: f883 20a4 strb.w r2, [r3, #164] @ 0xa4
|
|
|
|
/* Set the default auto bit reset configuration */
|
|
dev->enable_auto_br = ((dev->var_id > BMM350_CURRENT_SHUTTLE_VARIANT_ID) ? BMM350_DISABLE : BMM350_ENABLE);
|
|
80039fe: 687b ldr r3, [r7, #4]
|
|
8003a00: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4
|
|
8003a04: 2b11 cmp r3, #17
|
|
8003a06: bf94 ite ls
|
|
8003a08: 2301 movls r3, #1
|
|
8003a0a: 2300 movhi r3, #0
|
|
8003a0c: b2db uxtb r3, r3
|
|
8003a0e: 461a mov r2, r3
|
|
8003a10: 687b ldr r3, [r7, #4]
|
|
8003a12: f883 20ad strb.w r2, [r3, #173] @ 0xad
|
|
|
|
/* Update magnetometer offset and sensitivity data. */
|
|
update_mag_off_sens(dev);
|
|
8003a16: 6878 ldr r0, [r7, #4]
|
|
8003a18: f7ff fd10 bl 800343c <update_mag_off_sens>
|
|
|
|
return rslt;
|
|
8003a1c: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8003a20: 4618 mov r0, r3
|
|
8003a22: 3710 adds r7, #16
|
|
8003a24: 46bd mov sp, r7
|
|
8003a26: bd80 pop {r7, pc}
|
|
|
|
08003a28 <set_powermode>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to switch from suspend mode to normal mode or forced mode.
|
|
*/
|
|
static int8_t set_powermode(enum bmm350_power_modes powermode, struct bmm350_dev *dev)
|
|
{
|
|
8003a28: b590 push {r4, r7, lr}
|
|
8003a2a: b08f sub sp, #60 @ 0x3c
|
|
8003a2c: af00 add r7, sp, #0
|
|
8003a2e: 4603 mov r3, r0
|
|
8003a30: 6039 str r1, [r7, #0]
|
|
8003a32: 71fb strb r3, [r7, #7]
|
|
/* Variable to store the function result */
|
|
int8_t rslt;
|
|
|
|
uint8_t reg_data = powermode;
|
|
8003a34: 79fb ldrb r3, [r7, #7]
|
|
8003a36: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
uint8_t get_avg;
|
|
|
|
/* Array to store suspend to forced mode delay */
|
|
uint32_t sus_to_forced_mode[4] =
|
|
8003a3a: 4b36 ldr r3, [pc, #216] @ (8003b14 <set_powermode+0xec>)
|
|
8003a3c: f107 041c add.w r4, r7, #28
|
|
8003a40: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8003a42: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
{ BMM350_SUS_TO_FORCEDMODE_NO_AVG_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_2_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_4_DELAY,
|
|
BMM350_SUS_TO_FORCEDMODE_AVG_8_DELAY };
|
|
|
|
/* Array to store suspend to forced mode fast delay */
|
|
uint32_t sus_to_forced_mode_fast[4] =
|
|
8003a46: 4b34 ldr r3, [pc, #208] @ (8003b18 <set_powermode+0xf0>)
|
|
8003a48: f107 040c add.w r4, r7, #12
|
|
8003a4c: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8003a4e: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
{ BMM350_SUS_TO_FORCEDMODE_FAST_NO_AVG_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_2_DELAY,
|
|
BMM350_SUS_TO_FORCEDMODE_FAST_AVG_4_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_8_DELAY };
|
|
|
|
uint8_t avg = 0;
|
|
8003a52: 2300 movs r3, #0
|
|
8003a54: f887 3036 strb.w r3, [r7, #54] @ 0x36
|
|
uint32_t delay_us = 0;
|
|
8003a58: 2300 movs r3, #0
|
|
8003a5a: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
rslt = null_ptr_check(dev);
|
|
8003a5c: 6838 ldr r0, [r7, #0]
|
|
8003a5e: f7ff fbd1 bl 8003204 <null_ptr_check>
|
|
8003a62: 4603 mov r3, r0
|
|
8003a64: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
|
|
if (rslt == BMM350_OK)
|
|
8003a68: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
|
|
8003a6c: 2b00 cmp r3, #0
|
|
8003a6e: d123 bne.n 8003ab8 <set_powermode+0x90>
|
|
{
|
|
/* Set PMU command configuration to desired power mode */
|
|
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev);
|
|
8003a70: f107 012f add.w r1, r7, #47 @ 0x2f
|
|
8003a74: 683b ldr r3, [r7, #0]
|
|
8003a76: 2201 movs r2, #1
|
|
8003a78: 2006 movs r0, #6
|
|
8003a7a: f7fe feb9 bl 80027f0 <bmm350_set_regs>
|
|
8003a7e: 4603 mov r3, r0
|
|
8003a80: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
|
|
if (rslt == BMM350_OK)
|
|
8003a84: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
|
|
8003a88: 2b00 cmp r3, #0
|
|
8003a8a: d115 bne.n 8003ab8 <set_powermode+0x90>
|
|
{
|
|
/* Get average configuration */
|
|
rslt = bmm350_get_regs(BMM350_REG_PMU_CMD_AGGR_SET, &get_avg, 1, dev);
|
|
8003a8c: f107 012e add.w r1, r7, #46 @ 0x2e
|
|
8003a90: 683b ldr r3, [r7, #0]
|
|
8003a92: 2201 movs r2, #1
|
|
8003a94: 2004 movs r0, #4
|
|
8003a96: f7fe fedf bl 8002858 <bmm350_get_regs>
|
|
8003a9a: 4603 mov r3, r0
|
|
8003a9c: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
|
|
if (rslt == BMM350_OK)
|
|
8003aa0: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
|
|
8003aa4: 2b00 cmp r3, #0
|
|
8003aa6: d107 bne.n 8003ab8 <set_powermode+0x90>
|
|
{
|
|
/* Mask the average value */
|
|
avg = ((get_avg & BMM350_AVG_MSK) >> BMM350_AVG_POS);
|
|
8003aa8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
|
|
8003aac: 111b asrs r3, r3, #4
|
|
8003aae: b2db uxtb r3, r3
|
|
8003ab0: f003 0303 and.w r3, r3, #3
|
|
8003ab4: f887 3036 strb.w r3, [r7, #54] @ 0x36
|
|
}
|
|
}
|
|
}
|
|
|
|
if (rslt == BMM350_OK)
|
|
8003ab8: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
|
|
8003abc: 2b00 cmp r3, #0
|
|
8003abe: d122 bne.n 8003b06 <set_powermode+0xde>
|
|
{
|
|
/* Check if desired power mode is normal mode */
|
|
if (powermode == BMM350_NORMAL_MODE)
|
|
8003ac0: 79fb ldrb r3, [r7, #7]
|
|
8003ac2: 2b01 cmp r3, #1
|
|
8003ac4: d102 bne.n 8003acc <set_powermode+0xa4>
|
|
{
|
|
delay_us = BMM350_SUSPEND_TO_NORMAL_DELAY;
|
|
8003ac6: f249 4370 movw r3, #38000 @ 0x9470
|
|
8003aca: 633b str r3, [r7, #48] @ 0x30
|
|
}
|
|
|
|
/* Check if desired power mode is forced mode */
|
|
if (powermode == BMM350_FORCED_MODE)
|
|
8003acc: 79fb ldrb r3, [r7, #7]
|
|
8003ace: 2b03 cmp r3, #3
|
|
8003ad0: d107 bne.n 8003ae2 <set_powermode+0xba>
|
|
{
|
|
/* Store delay based on averaging mode */
|
|
delay_us = sus_to_forced_mode[avg];
|
|
8003ad2: f897 3036 ldrb.w r3, [r7, #54] @ 0x36
|
|
8003ad6: 009b lsls r3, r3, #2
|
|
8003ad8: 3338 adds r3, #56 @ 0x38
|
|
8003ada: 443b add r3, r7
|
|
8003adc: f853 3c1c ldr.w r3, [r3, #-28]
|
|
8003ae0: 633b str r3, [r7, #48] @ 0x30
|
|
}
|
|
|
|
/* Check if desired power mode is forced mode fast */
|
|
if (powermode == BMM350_FORCED_MODE_FAST)
|
|
8003ae2: 79fb ldrb r3, [r7, #7]
|
|
8003ae4: 2b04 cmp r3, #4
|
|
8003ae6: d107 bne.n 8003af8 <set_powermode+0xd0>
|
|
{
|
|
/* Store delay based on averaging mode */
|
|
delay_us = sus_to_forced_mode_fast[avg];
|
|
8003ae8: f897 3036 ldrb.w r3, [r7, #54] @ 0x36
|
|
8003aec: 009b lsls r3, r3, #2
|
|
8003aee: 3338 adds r3, #56 @ 0x38
|
|
8003af0: 443b add r3, r7
|
|
8003af2: f853 3c2c ldr.w r3, [r3, #-44]
|
|
8003af6: 633b str r3, [r7, #48] @ 0x30
|
|
}
|
|
|
|
/* Perform delay based on power mode */
|
|
rslt = bmm350_delay_us(delay_us, dev);
|
|
8003af8: 6839 ldr r1, [r7, #0]
|
|
8003afa: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8003afc: f7fe ff01 bl 8002902 <bmm350_delay_us>
|
|
8003b00: 4603 mov r3, r0
|
|
8003b02: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
}
|
|
|
|
return rslt;
|
|
8003b06: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
|
|
}
|
|
8003b0a: 4618 mov r0, r3
|
|
8003b0c: 373c adds r7, #60 @ 0x3c
|
|
8003b0e: 46bd mov sp, r7
|
|
8003b10: bd90 pop {r4, r7, pc}
|
|
8003b12: bf00 nop
|
|
8003b14: 0801de2c .word 0x0801de2c
|
|
8003b18: 0801de3c .word 0x0801de3c
|
|
|
|
08003b1c <LL_EXTI_EnableIT_0_31>:
|
|
{
|
|
8003b1c: b480 push {r7}
|
|
8003b1e: b083 sub sp, #12
|
|
8003b20: af00 add r7, sp, #0
|
|
8003b22: 6078 str r0, [r7, #4]
|
|
SET_BIT(EXTI->IMR1, ExtiLine);
|
|
8003b24: 4b06 ldr r3, [pc, #24] @ (8003b40 <LL_EXTI_EnableIT_0_31+0x24>)
|
|
8003b26: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80
|
|
8003b2a: 4905 ldr r1, [pc, #20] @ (8003b40 <LL_EXTI_EnableIT_0_31+0x24>)
|
|
8003b2c: 687b ldr r3, [r7, #4]
|
|
8003b2e: 4313 orrs r3, r2
|
|
8003b30: f8c1 3080 str.w r3, [r1, #128] @ 0x80
|
|
}
|
|
8003b34: bf00 nop
|
|
8003b36: 370c adds r7, #12
|
|
8003b38: 46bd mov sp, r7
|
|
8003b3a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003b3e: 4770 bx lr
|
|
8003b40: 58000800 .word 0x58000800
|
|
|
|
08003b44 <LL_EXTI_EnableRisingTrig_0_31>:
|
|
* @arg @ref LL_EXTI_LINE_31 (*)
|
|
* (*) value not defined in all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
|
|
{
|
|
8003b44: b480 push {r7}
|
|
8003b46: b083 sub sp, #12
|
|
8003b48: af00 add r7, sp, #0
|
|
8003b4a: 6078 str r0, [r7, #4]
|
|
SET_BIT(EXTI->RTSR1, ExtiLine);
|
|
8003b4c: 4b05 ldr r3, [pc, #20] @ (8003b64 <LL_EXTI_EnableRisingTrig_0_31+0x20>)
|
|
8003b4e: 681a ldr r2, [r3, #0]
|
|
8003b50: 4904 ldr r1, [pc, #16] @ (8003b64 <LL_EXTI_EnableRisingTrig_0_31+0x20>)
|
|
8003b52: 687b ldr r3, [r7, #4]
|
|
8003b54: 4313 orrs r3, r2
|
|
8003b56: 600b str r3, [r1, #0]
|
|
|
|
}
|
|
8003b58: bf00 nop
|
|
8003b5a: 370c adds r7, #12
|
|
8003b5c: 46bd mov sp, r7
|
|
8003b5e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003b62: 4770 bx lr
|
|
8003b64: 58000800 .word 0x58000800
|
|
|
|
08003b68 <ReadRtcSsrValue>:
|
|
* reliability of the value
|
|
* @param None
|
|
* @retval SSR value read
|
|
*/
|
|
static uint32_t ReadRtcSsrValue(void)
|
|
{
|
|
8003b68: b480 push {r7}
|
|
8003b6a: b083 sub sp, #12
|
|
8003b6c: af00 add r7, sp, #0
|
|
uint32_t first_read;
|
|
uint32_t second_read;
|
|
|
|
first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
|
|
8003b6e: 4b0d ldr r3, [pc, #52] @ (8003ba4 <ReadRtcSsrValue+0x3c>)
|
|
8003b70: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003b72: b29b uxth r3, r3
|
|
8003b74: 607b str r3, [r7, #4]
|
|
|
|
second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
|
|
8003b76: 4b0b ldr r3, [pc, #44] @ (8003ba4 <ReadRtcSsrValue+0x3c>)
|
|
8003b78: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003b7a: b29b uxth r3, r3
|
|
8003b7c: 603b str r3, [r7, #0]
|
|
|
|
while(first_read != second_read)
|
|
8003b7e: e005 b.n 8003b8c <ReadRtcSsrValue+0x24>
|
|
{
|
|
first_read = second_read;
|
|
8003b80: 683b ldr r3, [r7, #0]
|
|
8003b82: 607b str r3, [r7, #4]
|
|
|
|
second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
|
|
8003b84: 4b07 ldr r3, [pc, #28] @ (8003ba4 <ReadRtcSsrValue+0x3c>)
|
|
8003b86: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003b88: b29b uxth r3, r3
|
|
8003b8a: 603b str r3, [r7, #0]
|
|
while(first_read != second_read)
|
|
8003b8c: 687a ldr r2, [r7, #4]
|
|
8003b8e: 683b ldr r3, [r7, #0]
|
|
8003b90: 429a cmp r2, r3
|
|
8003b92: d1f5 bne.n 8003b80 <ReadRtcSsrValue+0x18>
|
|
}
|
|
|
|
return second_read;
|
|
8003b94: 683b ldr r3, [r7, #0]
|
|
}
|
|
8003b96: 4618 mov r0, r3
|
|
8003b98: 370c adds r7, #12
|
|
8003b9a: 46bd mov sp, r7
|
|
8003b9c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003ba0: 4770 bx lr
|
|
8003ba2: bf00 nop
|
|
8003ba4: 40002800 .word 0x40002800
|
|
|
|
08003ba8 <LinkTimerAfter>:
|
|
* @param TimerID: The ID of the Timer
|
|
* @param RefTimerID: The ID of the Timer to be linked after
|
|
* @retval None
|
|
*/
|
|
static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
|
|
{
|
|
8003ba8: b480 push {r7}
|
|
8003baa: b085 sub sp, #20
|
|
8003bac: af00 add r7, sp, #0
|
|
8003bae: 4603 mov r3, r0
|
|
8003bb0: 460a mov r2, r1
|
|
8003bb2: 71fb strb r3, [r7, #7]
|
|
8003bb4: 4613 mov r3, r2
|
|
8003bb6: 71bb strb r3, [r7, #6]
|
|
uint8_t next_id;
|
|
|
|
next_id = aTimerContext[RefTimerID].NextID;
|
|
8003bb8: 79ba ldrb r2, [r7, #6]
|
|
8003bba: 491d ldr r1, [pc, #116] @ (8003c30 <LinkTimerAfter+0x88>)
|
|
8003bbc: 4613 mov r3, r2
|
|
8003bbe: 005b lsls r3, r3, #1
|
|
8003bc0: 4413 add r3, r2
|
|
8003bc2: 00db lsls r3, r3, #3
|
|
8003bc4: 440b add r3, r1
|
|
8003bc6: 3315 adds r3, #21
|
|
8003bc8: 781b ldrb r3, [r3, #0]
|
|
8003bca: 73fb strb r3, [r7, #15]
|
|
|
|
if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
|
8003bcc: 7bfb ldrb r3, [r7, #15]
|
|
8003bce: 2b06 cmp r3, #6
|
|
8003bd0: d009 beq.n 8003be6 <LinkTimerAfter+0x3e>
|
|
{
|
|
aTimerContext[next_id].PreviousID = TimerID;
|
|
8003bd2: 7bfa ldrb r2, [r7, #15]
|
|
8003bd4: 4916 ldr r1, [pc, #88] @ (8003c30 <LinkTimerAfter+0x88>)
|
|
8003bd6: 4613 mov r3, r2
|
|
8003bd8: 005b lsls r3, r3, #1
|
|
8003bda: 4413 add r3, r2
|
|
8003bdc: 00db lsls r3, r3, #3
|
|
8003bde: 440b add r3, r1
|
|
8003be0: 3314 adds r3, #20
|
|
8003be2: 79fa ldrb r2, [r7, #7]
|
|
8003be4: 701a strb r2, [r3, #0]
|
|
}
|
|
aTimerContext[TimerID].NextID = next_id;
|
|
8003be6: 79fa ldrb r2, [r7, #7]
|
|
8003be8: 4911 ldr r1, [pc, #68] @ (8003c30 <LinkTimerAfter+0x88>)
|
|
8003bea: 4613 mov r3, r2
|
|
8003bec: 005b lsls r3, r3, #1
|
|
8003bee: 4413 add r3, r2
|
|
8003bf0: 00db lsls r3, r3, #3
|
|
8003bf2: 440b add r3, r1
|
|
8003bf4: 3315 adds r3, #21
|
|
8003bf6: 7bfa ldrb r2, [r7, #15]
|
|
8003bf8: 701a strb r2, [r3, #0]
|
|
aTimerContext[TimerID].PreviousID = RefTimerID ;
|
|
8003bfa: 79fa ldrb r2, [r7, #7]
|
|
8003bfc: 490c ldr r1, [pc, #48] @ (8003c30 <LinkTimerAfter+0x88>)
|
|
8003bfe: 4613 mov r3, r2
|
|
8003c00: 005b lsls r3, r3, #1
|
|
8003c02: 4413 add r3, r2
|
|
8003c04: 00db lsls r3, r3, #3
|
|
8003c06: 440b add r3, r1
|
|
8003c08: 3314 adds r3, #20
|
|
8003c0a: 79ba ldrb r2, [r7, #6]
|
|
8003c0c: 701a strb r2, [r3, #0]
|
|
aTimerContext[RefTimerID].NextID = TimerID;
|
|
8003c0e: 79ba ldrb r2, [r7, #6]
|
|
8003c10: 4907 ldr r1, [pc, #28] @ (8003c30 <LinkTimerAfter+0x88>)
|
|
8003c12: 4613 mov r3, r2
|
|
8003c14: 005b lsls r3, r3, #1
|
|
8003c16: 4413 add r3, r2
|
|
8003c18: 00db lsls r3, r3, #3
|
|
8003c1a: 440b add r3, r1
|
|
8003c1c: 3315 adds r3, #21
|
|
8003c1e: 79fa ldrb r2, [r7, #7]
|
|
8003c20: 701a strb r2, [r3, #0]
|
|
|
|
return;
|
|
8003c22: bf00 nop
|
|
}
|
|
8003c24: 3714 adds r7, #20
|
|
8003c26: 46bd mov sp, r7
|
|
8003c28: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003c2c: 4770 bx lr
|
|
8003c2e: bf00 nop
|
|
8003c30: 20000314 .word 0x20000314
|
|
|
|
08003c34 <LinkTimerBefore>:
|
|
* @param TimerID: The ID of the Timer
|
|
* @param RefTimerID: The ID of the Timer to be linked before
|
|
* @retval None
|
|
*/
|
|
static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
|
|
{
|
|
8003c34: b480 push {r7}
|
|
8003c36: b085 sub sp, #20
|
|
8003c38: af00 add r7, sp, #0
|
|
8003c3a: 4603 mov r3, r0
|
|
8003c3c: 460a mov r2, r1
|
|
8003c3e: 71fb strb r3, [r7, #7]
|
|
8003c40: 4613 mov r3, r2
|
|
8003c42: 71bb strb r3, [r7, #6]
|
|
uint8_t previous_id;
|
|
|
|
if(RefTimerID != CurrentRunningTimerID)
|
|
8003c44: 4b29 ldr r3, [pc, #164] @ (8003cec <LinkTimerBefore+0xb8>)
|
|
8003c46: 781b ldrb r3, [r3, #0]
|
|
8003c48: b2db uxtb r3, r3
|
|
8003c4a: 79ba ldrb r2, [r7, #6]
|
|
8003c4c: 429a cmp r2, r3
|
|
8003c4e: d032 beq.n 8003cb6 <LinkTimerBefore+0x82>
|
|
{
|
|
previous_id = aTimerContext[RefTimerID].PreviousID;
|
|
8003c50: 79ba ldrb r2, [r7, #6]
|
|
8003c52: 4927 ldr r1, [pc, #156] @ (8003cf0 <LinkTimerBefore+0xbc>)
|
|
8003c54: 4613 mov r3, r2
|
|
8003c56: 005b lsls r3, r3, #1
|
|
8003c58: 4413 add r3, r2
|
|
8003c5a: 00db lsls r3, r3, #3
|
|
8003c5c: 440b add r3, r1
|
|
8003c5e: 3314 adds r3, #20
|
|
8003c60: 781b ldrb r3, [r3, #0]
|
|
8003c62: 73fb strb r3, [r7, #15]
|
|
|
|
aTimerContext[previous_id].NextID = TimerID;
|
|
8003c64: 7bfa ldrb r2, [r7, #15]
|
|
8003c66: 4922 ldr r1, [pc, #136] @ (8003cf0 <LinkTimerBefore+0xbc>)
|
|
8003c68: 4613 mov r3, r2
|
|
8003c6a: 005b lsls r3, r3, #1
|
|
8003c6c: 4413 add r3, r2
|
|
8003c6e: 00db lsls r3, r3, #3
|
|
8003c70: 440b add r3, r1
|
|
8003c72: 3315 adds r3, #21
|
|
8003c74: 79fa ldrb r2, [r7, #7]
|
|
8003c76: 701a strb r2, [r3, #0]
|
|
aTimerContext[TimerID].NextID = RefTimerID;
|
|
8003c78: 79fa ldrb r2, [r7, #7]
|
|
8003c7a: 491d ldr r1, [pc, #116] @ (8003cf0 <LinkTimerBefore+0xbc>)
|
|
8003c7c: 4613 mov r3, r2
|
|
8003c7e: 005b lsls r3, r3, #1
|
|
8003c80: 4413 add r3, r2
|
|
8003c82: 00db lsls r3, r3, #3
|
|
8003c84: 440b add r3, r1
|
|
8003c86: 3315 adds r3, #21
|
|
8003c88: 79ba ldrb r2, [r7, #6]
|
|
8003c8a: 701a strb r2, [r3, #0]
|
|
aTimerContext[TimerID].PreviousID = previous_id ;
|
|
8003c8c: 79fa ldrb r2, [r7, #7]
|
|
8003c8e: 4918 ldr r1, [pc, #96] @ (8003cf0 <LinkTimerBefore+0xbc>)
|
|
8003c90: 4613 mov r3, r2
|
|
8003c92: 005b lsls r3, r3, #1
|
|
8003c94: 4413 add r3, r2
|
|
8003c96: 00db lsls r3, r3, #3
|
|
8003c98: 440b add r3, r1
|
|
8003c9a: 3314 adds r3, #20
|
|
8003c9c: 7bfa ldrb r2, [r7, #15]
|
|
8003c9e: 701a strb r2, [r3, #0]
|
|
aTimerContext[RefTimerID].PreviousID = TimerID;
|
|
8003ca0: 79ba ldrb r2, [r7, #6]
|
|
8003ca2: 4913 ldr r1, [pc, #76] @ (8003cf0 <LinkTimerBefore+0xbc>)
|
|
8003ca4: 4613 mov r3, r2
|
|
8003ca6: 005b lsls r3, r3, #1
|
|
8003ca8: 4413 add r3, r2
|
|
8003caa: 00db lsls r3, r3, #3
|
|
8003cac: 440b add r3, r1
|
|
8003cae: 3314 adds r3, #20
|
|
8003cb0: 79fa ldrb r2, [r7, #7]
|
|
8003cb2: 701a strb r2, [r3, #0]
|
|
{
|
|
aTimerContext[TimerID].NextID = RefTimerID;
|
|
aTimerContext[RefTimerID].PreviousID = TimerID;
|
|
}
|
|
|
|
return;
|
|
8003cb4: e014 b.n 8003ce0 <LinkTimerBefore+0xac>
|
|
aTimerContext[TimerID].NextID = RefTimerID;
|
|
8003cb6: 79fa ldrb r2, [r7, #7]
|
|
8003cb8: 490d ldr r1, [pc, #52] @ (8003cf0 <LinkTimerBefore+0xbc>)
|
|
8003cba: 4613 mov r3, r2
|
|
8003cbc: 005b lsls r3, r3, #1
|
|
8003cbe: 4413 add r3, r2
|
|
8003cc0: 00db lsls r3, r3, #3
|
|
8003cc2: 440b add r3, r1
|
|
8003cc4: 3315 adds r3, #21
|
|
8003cc6: 79ba ldrb r2, [r7, #6]
|
|
8003cc8: 701a strb r2, [r3, #0]
|
|
aTimerContext[RefTimerID].PreviousID = TimerID;
|
|
8003cca: 79ba ldrb r2, [r7, #6]
|
|
8003ccc: 4908 ldr r1, [pc, #32] @ (8003cf0 <LinkTimerBefore+0xbc>)
|
|
8003cce: 4613 mov r3, r2
|
|
8003cd0: 005b lsls r3, r3, #1
|
|
8003cd2: 4413 add r3, r2
|
|
8003cd4: 00db lsls r3, r3, #3
|
|
8003cd6: 440b add r3, r1
|
|
8003cd8: 3314 adds r3, #20
|
|
8003cda: 79fa ldrb r2, [r7, #7]
|
|
8003cdc: 701a strb r2, [r3, #0]
|
|
return;
|
|
8003cde: bf00 nop
|
|
}
|
|
8003ce0: 3714 adds r7, #20
|
|
8003ce2: 46bd mov sp, r7
|
|
8003ce4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003ce8: 4770 bx lr
|
|
8003cea: bf00 nop
|
|
8003cec: 200003a4 .word 0x200003a4
|
|
8003cf0: 20000314 .word 0x20000314
|
|
|
|
08003cf4 <linkTimer>:
|
|
* @brief Insert a Timer in the list
|
|
* @param TimerID: The ID of the Timer
|
|
* @retval None
|
|
*/
|
|
static uint16_t linkTimer(uint8_t TimerID)
|
|
{
|
|
8003cf4: b580 push {r7, lr}
|
|
8003cf6: b084 sub sp, #16
|
|
8003cf8: af00 add r7, sp, #0
|
|
8003cfa: 4603 mov r3, r0
|
|
8003cfc: 71fb strb r3, [r7, #7]
|
|
uint32_t time_left;
|
|
uint16_t time_elapsed;
|
|
uint8_t timer_id_lookup;
|
|
uint8_t next_id;
|
|
|
|
if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
|
8003cfe: 4b4e ldr r3, [pc, #312] @ (8003e38 <linkTimer+0x144>)
|
|
8003d00: 781b ldrb r3, [r3, #0]
|
|
8003d02: b2db uxtb r3, r3
|
|
8003d04: 2b06 cmp r3, #6
|
|
8003d06: d118 bne.n 8003d3a <linkTimer+0x46>
|
|
{
|
|
/**
|
|
* No timer in the list
|
|
*/
|
|
PreviousRunningTimerID = CurrentRunningTimerID;
|
|
8003d08: 4b4b ldr r3, [pc, #300] @ (8003e38 <linkTimer+0x144>)
|
|
8003d0a: 781b ldrb r3, [r3, #0]
|
|
8003d0c: b2da uxtb r2, r3
|
|
8003d0e: 4b4b ldr r3, [pc, #300] @ (8003e3c <linkTimer+0x148>)
|
|
8003d10: 701a strb r2, [r3, #0]
|
|
CurrentRunningTimerID = TimerID;
|
|
8003d12: 4a49 ldr r2, [pc, #292] @ (8003e38 <linkTimer+0x144>)
|
|
8003d14: 79fb ldrb r3, [r7, #7]
|
|
8003d16: 7013 strb r3, [r2, #0]
|
|
aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
|
|
8003d18: 79fa ldrb r2, [r7, #7]
|
|
8003d1a: 4949 ldr r1, [pc, #292] @ (8003e40 <linkTimer+0x14c>)
|
|
8003d1c: 4613 mov r3, r2
|
|
8003d1e: 005b lsls r3, r3, #1
|
|
8003d20: 4413 add r3, r2
|
|
8003d22: 00db lsls r3, r3, #3
|
|
8003d24: 440b add r3, r1
|
|
8003d26: 3315 adds r3, #21
|
|
8003d28: 2206 movs r2, #6
|
|
8003d2a: 701a strb r2, [r3, #0]
|
|
|
|
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
|
|
8003d2c: 4b45 ldr r3, [pc, #276] @ (8003e44 <linkTimer+0x150>)
|
|
8003d2e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8003d32: 601a str r2, [r3, #0]
|
|
time_elapsed = 0;
|
|
8003d34: 2300 movs r3, #0
|
|
8003d36: 81fb strh r3, [r7, #14]
|
|
8003d38: e078 b.n 8003e2c <linkTimer+0x138>
|
|
}
|
|
else
|
|
{
|
|
time_elapsed = ReturnTimeElapsed();
|
|
8003d3a: f000 f909 bl 8003f50 <ReturnTimeElapsed>
|
|
8003d3e: 4603 mov r3, r0
|
|
8003d40: 81fb strh r3, [r7, #14]
|
|
|
|
/**
|
|
* update count of the timer to be linked
|
|
*/
|
|
aTimerContext[TimerID].CountLeft += time_elapsed;
|
|
8003d42: 79fa ldrb r2, [r7, #7]
|
|
8003d44: 493e ldr r1, [pc, #248] @ (8003e40 <linkTimer+0x14c>)
|
|
8003d46: 4613 mov r3, r2
|
|
8003d48: 005b lsls r3, r3, #1
|
|
8003d4a: 4413 add r3, r2
|
|
8003d4c: 00db lsls r3, r3, #3
|
|
8003d4e: 440b add r3, r1
|
|
8003d50: 3308 adds r3, #8
|
|
8003d52: 6819 ldr r1, [r3, #0]
|
|
8003d54: 89fb ldrh r3, [r7, #14]
|
|
8003d56: 79fa ldrb r2, [r7, #7]
|
|
8003d58: 4419 add r1, r3
|
|
8003d5a: 4839 ldr r0, [pc, #228] @ (8003e40 <linkTimer+0x14c>)
|
|
8003d5c: 4613 mov r3, r2
|
|
8003d5e: 005b lsls r3, r3, #1
|
|
8003d60: 4413 add r3, r2
|
|
8003d62: 00db lsls r3, r3, #3
|
|
8003d64: 4403 add r3, r0
|
|
8003d66: 3308 adds r3, #8
|
|
8003d68: 6019 str r1, [r3, #0]
|
|
time_left = aTimerContext[TimerID].CountLeft;
|
|
8003d6a: 79fa ldrb r2, [r7, #7]
|
|
8003d6c: 4934 ldr r1, [pc, #208] @ (8003e40 <linkTimer+0x14c>)
|
|
8003d6e: 4613 mov r3, r2
|
|
8003d70: 005b lsls r3, r3, #1
|
|
8003d72: 4413 add r3, r2
|
|
8003d74: 00db lsls r3, r3, #3
|
|
8003d76: 440b add r3, r1
|
|
8003d78: 3308 adds r3, #8
|
|
8003d7a: 681b ldr r3, [r3, #0]
|
|
8003d7c: 60bb str r3, [r7, #8]
|
|
|
|
/**
|
|
* Search for index where the new timer shall be linked
|
|
*/
|
|
if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
|
|
8003d7e: 4b2e ldr r3, [pc, #184] @ (8003e38 <linkTimer+0x144>)
|
|
8003d80: 781b ldrb r3, [r3, #0]
|
|
8003d82: b2db uxtb r3, r3
|
|
8003d84: 4619 mov r1, r3
|
|
8003d86: 4a2e ldr r2, [pc, #184] @ (8003e40 <linkTimer+0x14c>)
|
|
8003d88: 460b mov r3, r1
|
|
8003d8a: 005b lsls r3, r3, #1
|
|
8003d8c: 440b add r3, r1
|
|
8003d8e: 00db lsls r3, r3, #3
|
|
8003d90: 4413 add r3, r2
|
|
8003d92: 3308 adds r3, #8
|
|
8003d94: 681b ldr r3, [r3, #0]
|
|
8003d96: 68ba ldr r2, [r7, #8]
|
|
8003d98: 429a cmp r2, r3
|
|
8003d9a: d337 bcc.n 8003e0c <linkTimer+0x118>
|
|
{
|
|
/**
|
|
* Search for the ID after the first one
|
|
*/
|
|
timer_id_lookup = CurrentRunningTimerID;
|
|
8003d9c: 4b26 ldr r3, [pc, #152] @ (8003e38 <linkTimer+0x144>)
|
|
8003d9e: 781b ldrb r3, [r3, #0]
|
|
8003da0: 737b strb r3, [r7, #13]
|
|
next_id = aTimerContext[timer_id_lookup].NextID;
|
|
8003da2: 7b7a ldrb r2, [r7, #13]
|
|
8003da4: 4926 ldr r1, [pc, #152] @ (8003e40 <linkTimer+0x14c>)
|
|
8003da6: 4613 mov r3, r2
|
|
8003da8: 005b lsls r3, r3, #1
|
|
8003daa: 4413 add r3, r2
|
|
8003dac: 00db lsls r3, r3, #3
|
|
8003dae: 440b add r3, r1
|
|
8003db0: 3315 adds r3, #21
|
|
8003db2: 781b ldrb r3, [r3, #0]
|
|
8003db4: 733b strb r3, [r7, #12]
|
|
while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
|
|
8003db6: e013 b.n 8003de0 <linkTimer+0xec>
|
|
{
|
|
timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
|
|
8003db8: 7b7a ldrb r2, [r7, #13]
|
|
8003dba: 4921 ldr r1, [pc, #132] @ (8003e40 <linkTimer+0x14c>)
|
|
8003dbc: 4613 mov r3, r2
|
|
8003dbe: 005b lsls r3, r3, #1
|
|
8003dc0: 4413 add r3, r2
|
|
8003dc2: 00db lsls r3, r3, #3
|
|
8003dc4: 440b add r3, r1
|
|
8003dc6: 3315 adds r3, #21
|
|
8003dc8: 781b ldrb r3, [r3, #0]
|
|
8003dca: 737b strb r3, [r7, #13]
|
|
next_id = aTimerContext[timer_id_lookup].NextID;
|
|
8003dcc: 7b7a ldrb r2, [r7, #13]
|
|
8003dce: 491c ldr r1, [pc, #112] @ (8003e40 <linkTimer+0x14c>)
|
|
8003dd0: 4613 mov r3, r2
|
|
8003dd2: 005b lsls r3, r3, #1
|
|
8003dd4: 4413 add r3, r2
|
|
8003dd6: 00db lsls r3, r3, #3
|
|
8003dd8: 440b add r3, r1
|
|
8003dda: 3315 adds r3, #21
|
|
8003ddc: 781b ldrb r3, [r3, #0]
|
|
8003dde: 733b strb r3, [r7, #12]
|
|
while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
|
|
8003de0: 7b3b ldrb r3, [r7, #12]
|
|
8003de2: 2b06 cmp r3, #6
|
|
8003de4: d00b beq.n 8003dfe <linkTimer+0x10a>
|
|
8003de6: 7b3a ldrb r2, [r7, #12]
|
|
8003de8: 4915 ldr r1, [pc, #84] @ (8003e40 <linkTimer+0x14c>)
|
|
8003dea: 4613 mov r3, r2
|
|
8003dec: 005b lsls r3, r3, #1
|
|
8003dee: 4413 add r3, r2
|
|
8003df0: 00db lsls r3, r3, #3
|
|
8003df2: 440b add r3, r1
|
|
8003df4: 3308 adds r3, #8
|
|
8003df6: 681b ldr r3, [r3, #0]
|
|
8003df8: 68ba ldr r2, [r7, #8]
|
|
8003dfa: 429a cmp r2, r3
|
|
8003dfc: d2dc bcs.n 8003db8 <linkTimer+0xc4>
|
|
}
|
|
|
|
/**
|
|
* Link after the ID
|
|
*/
|
|
LinkTimerAfter(TimerID, timer_id_lookup);
|
|
8003dfe: 7b7a ldrb r2, [r7, #13]
|
|
8003e00: 79fb ldrb r3, [r7, #7]
|
|
8003e02: 4611 mov r1, r2
|
|
8003e04: 4618 mov r0, r3
|
|
8003e06: f7ff fecf bl 8003ba8 <LinkTimerAfter>
|
|
8003e0a: e00f b.n 8003e2c <linkTimer+0x138>
|
|
else
|
|
{
|
|
/**
|
|
* Link before the first ID
|
|
*/
|
|
LinkTimerBefore(TimerID, CurrentRunningTimerID);
|
|
8003e0c: 4b0a ldr r3, [pc, #40] @ (8003e38 <linkTimer+0x144>)
|
|
8003e0e: 781b ldrb r3, [r3, #0]
|
|
8003e10: b2da uxtb r2, r3
|
|
8003e12: 79fb ldrb r3, [r7, #7]
|
|
8003e14: 4611 mov r1, r2
|
|
8003e16: 4618 mov r0, r3
|
|
8003e18: f7ff ff0c bl 8003c34 <LinkTimerBefore>
|
|
PreviousRunningTimerID = CurrentRunningTimerID;
|
|
8003e1c: 4b06 ldr r3, [pc, #24] @ (8003e38 <linkTimer+0x144>)
|
|
8003e1e: 781b ldrb r3, [r3, #0]
|
|
8003e20: b2da uxtb r2, r3
|
|
8003e22: 4b06 ldr r3, [pc, #24] @ (8003e3c <linkTimer+0x148>)
|
|
8003e24: 701a strb r2, [r3, #0]
|
|
CurrentRunningTimerID = TimerID;
|
|
8003e26: 4a04 ldr r2, [pc, #16] @ (8003e38 <linkTimer+0x144>)
|
|
8003e28: 79fb ldrb r3, [r7, #7]
|
|
8003e2a: 7013 strb r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
return time_elapsed;
|
|
8003e2c: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
8003e2e: 4618 mov r0, r3
|
|
8003e30: 3710 adds r7, #16
|
|
8003e32: 46bd mov sp, r7
|
|
8003e34: bd80 pop {r7, pc}
|
|
8003e36: bf00 nop
|
|
8003e38: 200003a4 .word 0x200003a4
|
|
8003e3c: 200003a5 .word 0x200003a5
|
|
8003e40: 20000314 .word 0x20000314
|
|
8003e44: 200003a8 .word 0x200003a8
|
|
|
|
08003e48 <UnlinkTimer>:
|
|
* @param TimerID: The ID of the Timer
|
|
* @param RequestReadSSR: Request to read the SSR register or not
|
|
* @retval None
|
|
*/
|
|
static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
|
|
{
|
|
8003e48: b480 push {r7}
|
|
8003e4a: b085 sub sp, #20
|
|
8003e4c: af00 add r7, sp, #0
|
|
8003e4e: 4603 mov r3, r0
|
|
8003e50: 460a mov r2, r1
|
|
8003e52: 71fb strb r3, [r7, #7]
|
|
8003e54: 4613 mov r3, r2
|
|
8003e56: 71bb strb r3, [r7, #6]
|
|
uint8_t previous_id;
|
|
uint8_t next_id;
|
|
|
|
if(TimerID == CurrentRunningTimerID)
|
|
8003e58: 4b39 ldr r3, [pc, #228] @ (8003f40 <UnlinkTimer+0xf8>)
|
|
8003e5a: 781b ldrb r3, [r3, #0]
|
|
8003e5c: b2db uxtb r3, r3
|
|
8003e5e: 79fa ldrb r2, [r7, #7]
|
|
8003e60: 429a cmp r2, r3
|
|
8003e62: d111 bne.n 8003e88 <UnlinkTimer+0x40>
|
|
{
|
|
PreviousRunningTimerID = CurrentRunningTimerID;
|
|
8003e64: 4b36 ldr r3, [pc, #216] @ (8003f40 <UnlinkTimer+0xf8>)
|
|
8003e66: 781b ldrb r3, [r3, #0]
|
|
8003e68: b2da uxtb r2, r3
|
|
8003e6a: 4b36 ldr r3, [pc, #216] @ (8003f44 <UnlinkTimer+0xfc>)
|
|
8003e6c: 701a strb r2, [r3, #0]
|
|
CurrentRunningTimerID = aTimerContext[TimerID].NextID;
|
|
8003e6e: 79fa ldrb r2, [r7, #7]
|
|
8003e70: 4935 ldr r1, [pc, #212] @ (8003f48 <UnlinkTimer+0x100>)
|
|
8003e72: 4613 mov r3, r2
|
|
8003e74: 005b lsls r3, r3, #1
|
|
8003e76: 4413 add r3, r2
|
|
8003e78: 00db lsls r3, r3, #3
|
|
8003e7a: 440b add r3, r1
|
|
8003e7c: 3315 adds r3, #21
|
|
8003e7e: 781b ldrb r3, [r3, #0]
|
|
8003e80: b2da uxtb r2, r3
|
|
8003e82: 4b2f ldr r3, [pc, #188] @ (8003f40 <UnlinkTimer+0xf8>)
|
|
8003e84: 701a strb r2, [r3, #0]
|
|
8003e86: e03e b.n 8003f06 <UnlinkTimer+0xbe>
|
|
}
|
|
else
|
|
{
|
|
previous_id = aTimerContext[TimerID].PreviousID;
|
|
8003e88: 79fa ldrb r2, [r7, #7]
|
|
8003e8a: 492f ldr r1, [pc, #188] @ (8003f48 <UnlinkTimer+0x100>)
|
|
8003e8c: 4613 mov r3, r2
|
|
8003e8e: 005b lsls r3, r3, #1
|
|
8003e90: 4413 add r3, r2
|
|
8003e92: 00db lsls r3, r3, #3
|
|
8003e94: 440b add r3, r1
|
|
8003e96: 3314 adds r3, #20
|
|
8003e98: 781b ldrb r3, [r3, #0]
|
|
8003e9a: 73fb strb r3, [r7, #15]
|
|
next_id = aTimerContext[TimerID].NextID;
|
|
8003e9c: 79fa ldrb r2, [r7, #7]
|
|
8003e9e: 492a ldr r1, [pc, #168] @ (8003f48 <UnlinkTimer+0x100>)
|
|
8003ea0: 4613 mov r3, r2
|
|
8003ea2: 005b lsls r3, r3, #1
|
|
8003ea4: 4413 add r3, r2
|
|
8003ea6: 00db lsls r3, r3, #3
|
|
8003ea8: 440b add r3, r1
|
|
8003eaa: 3315 adds r3, #21
|
|
8003eac: 781b ldrb r3, [r3, #0]
|
|
8003eae: 73bb strb r3, [r7, #14]
|
|
|
|
aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
|
|
8003eb0: 79f9 ldrb r1, [r7, #7]
|
|
8003eb2: 7bfa ldrb r2, [r7, #15]
|
|
8003eb4: 4824 ldr r0, [pc, #144] @ (8003f48 <UnlinkTimer+0x100>)
|
|
8003eb6: 460b mov r3, r1
|
|
8003eb8: 005b lsls r3, r3, #1
|
|
8003eba: 440b add r3, r1
|
|
8003ebc: 00db lsls r3, r3, #3
|
|
8003ebe: 4403 add r3, r0
|
|
8003ec0: 3315 adds r3, #21
|
|
8003ec2: 781b ldrb r3, [r3, #0]
|
|
8003ec4: b2d8 uxtb r0, r3
|
|
8003ec6: 4920 ldr r1, [pc, #128] @ (8003f48 <UnlinkTimer+0x100>)
|
|
8003ec8: 4613 mov r3, r2
|
|
8003eca: 005b lsls r3, r3, #1
|
|
8003ecc: 4413 add r3, r2
|
|
8003ece: 00db lsls r3, r3, #3
|
|
8003ed0: 440b add r3, r1
|
|
8003ed2: 3315 adds r3, #21
|
|
8003ed4: 4602 mov r2, r0
|
|
8003ed6: 701a strb r2, [r3, #0]
|
|
if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
|
8003ed8: 7bbb ldrb r3, [r7, #14]
|
|
8003eda: 2b06 cmp r3, #6
|
|
8003edc: d013 beq.n 8003f06 <UnlinkTimer+0xbe>
|
|
{
|
|
aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
|
|
8003ede: 79f9 ldrb r1, [r7, #7]
|
|
8003ee0: 7bba ldrb r2, [r7, #14]
|
|
8003ee2: 4819 ldr r0, [pc, #100] @ (8003f48 <UnlinkTimer+0x100>)
|
|
8003ee4: 460b mov r3, r1
|
|
8003ee6: 005b lsls r3, r3, #1
|
|
8003ee8: 440b add r3, r1
|
|
8003eea: 00db lsls r3, r3, #3
|
|
8003eec: 4403 add r3, r0
|
|
8003eee: 3314 adds r3, #20
|
|
8003ef0: 781b ldrb r3, [r3, #0]
|
|
8003ef2: b2d8 uxtb r0, r3
|
|
8003ef4: 4914 ldr r1, [pc, #80] @ (8003f48 <UnlinkTimer+0x100>)
|
|
8003ef6: 4613 mov r3, r2
|
|
8003ef8: 005b lsls r3, r3, #1
|
|
8003efa: 4413 add r3, r2
|
|
8003efc: 00db lsls r3, r3, #3
|
|
8003efe: 440b add r3, r1
|
|
8003f00: 3314 adds r3, #20
|
|
8003f02: 4602 mov r2, r0
|
|
8003f04: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/**
|
|
* Timer is out of the list
|
|
*/
|
|
aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
|
|
8003f06: 79fa ldrb r2, [r7, #7]
|
|
8003f08: 490f ldr r1, [pc, #60] @ (8003f48 <UnlinkTimer+0x100>)
|
|
8003f0a: 4613 mov r3, r2
|
|
8003f0c: 005b lsls r3, r3, #1
|
|
8003f0e: 4413 add r3, r2
|
|
8003f10: 00db lsls r3, r3, #3
|
|
8003f12: 440b add r3, r1
|
|
8003f14: 330c adds r3, #12
|
|
8003f16: 2201 movs r2, #1
|
|
8003f18: 701a strb r2, [r3, #0]
|
|
|
|
if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
|
|
8003f1a: 4b09 ldr r3, [pc, #36] @ (8003f40 <UnlinkTimer+0xf8>)
|
|
8003f1c: 781b ldrb r3, [r3, #0]
|
|
8003f1e: b2db uxtb r3, r3
|
|
8003f20: 2b06 cmp r3, #6
|
|
8003f22: d107 bne.n 8003f34 <UnlinkTimer+0xec>
|
|
8003f24: 79bb ldrb r3, [r7, #6]
|
|
8003f26: 2b00 cmp r3, #0
|
|
8003f28: d104 bne.n 8003f34 <UnlinkTimer+0xec>
|
|
{
|
|
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
|
|
8003f2a: 4b08 ldr r3, [pc, #32] @ (8003f4c <UnlinkTimer+0x104>)
|
|
8003f2c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8003f30: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
return;
|
|
8003f32: bf00 nop
|
|
8003f34: bf00 nop
|
|
}
|
|
8003f36: 3714 adds r7, #20
|
|
8003f38: 46bd mov sp, r7
|
|
8003f3a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003f3e: 4770 bx lr
|
|
8003f40: 200003a4 .word 0x200003a4
|
|
8003f44: 200003a5 .word 0x200003a5
|
|
8003f48: 20000314 .word 0x20000314
|
|
8003f4c: 200003a8 .word 0x200003a8
|
|
|
|
08003f50 <ReturnTimeElapsed>:
|
|
* since the time the timer has been started
|
|
* @param None
|
|
* @retval Time expired in Ticks
|
|
*/
|
|
static uint16_t ReturnTimeElapsed(void)
|
|
{
|
|
8003f50: b580 push {r7, lr}
|
|
8003f52: b082 sub sp, #8
|
|
8003f54: af00 add r7, sp, #0
|
|
uint32_t return_value;
|
|
uint32_t wrap_counter;
|
|
|
|
if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
|
|
8003f56: 4b1a ldr r3, [pc, #104] @ (8003fc0 <ReturnTimeElapsed+0x70>)
|
|
8003f58: 681b ldr r3, [r3, #0]
|
|
8003f5a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8003f5e: d026 beq.n 8003fae <ReturnTimeElapsed+0x5e>
|
|
{
|
|
return_value = ReadRtcSsrValue(); /**< Read SSR register first */
|
|
8003f60: f7ff fe02 bl 8003b68 <ReadRtcSsrValue>
|
|
8003f64: 6078 str r0, [r7, #4]
|
|
|
|
if (SSRValueOnLastSetup >= return_value)
|
|
8003f66: 4b16 ldr r3, [pc, #88] @ (8003fc0 <ReturnTimeElapsed+0x70>)
|
|
8003f68: 681b ldr r3, [r3, #0]
|
|
8003f6a: 687a ldr r2, [r7, #4]
|
|
8003f6c: 429a cmp r2, r3
|
|
8003f6e: d805 bhi.n 8003f7c <ReturnTimeElapsed+0x2c>
|
|
{
|
|
return_value = SSRValueOnLastSetup - return_value;
|
|
8003f70: 4b13 ldr r3, [pc, #76] @ (8003fc0 <ReturnTimeElapsed+0x70>)
|
|
8003f72: 681a ldr r2, [r3, #0]
|
|
8003f74: 687b ldr r3, [r7, #4]
|
|
8003f76: 1ad3 subs r3, r2, r3
|
|
8003f78: 607b str r3, [r7, #4]
|
|
8003f7a: e00a b.n 8003f92 <ReturnTimeElapsed+0x42>
|
|
}
|
|
else
|
|
{
|
|
wrap_counter = SynchPrescalerUserConfig - return_value;
|
|
8003f7c: 4b11 ldr r3, [pc, #68] @ (8003fc4 <ReturnTimeElapsed+0x74>)
|
|
8003f7e: 881b ldrh r3, [r3, #0]
|
|
8003f80: 461a mov r2, r3
|
|
8003f82: 687b ldr r3, [r7, #4]
|
|
8003f84: 1ad3 subs r3, r2, r3
|
|
8003f86: 603b str r3, [r7, #0]
|
|
return_value = SSRValueOnLastSetup + wrap_counter;
|
|
8003f88: 4b0d ldr r3, [pc, #52] @ (8003fc0 <ReturnTimeElapsed+0x70>)
|
|
8003f8a: 681b ldr r3, [r3, #0]
|
|
8003f8c: 683a ldr r2, [r7, #0]
|
|
8003f8e: 4413 add r3, r2
|
|
8003f90: 607b str r3, [r7, #4]
|
|
|
|
/**
|
|
* At this stage, ReturnValue holds the number of ticks counted by SSR
|
|
* Need to translate in number of ticks counted by the Wakeuptimer
|
|
*/
|
|
return_value = return_value*AsynchPrescalerUserConfig;
|
|
8003f92: 4b0d ldr r3, [pc, #52] @ (8003fc8 <ReturnTimeElapsed+0x78>)
|
|
8003f94: 781b ldrb r3, [r3, #0]
|
|
8003f96: 461a mov r2, r3
|
|
8003f98: 687b ldr r3, [r7, #4]
|
|
8003f9a: fb02 f303 mul.w r3, r2, r3
|
|
8003f9e: 607b str r3, [r7, #4]
|
|
return_value = return_value >> WakeupTimerDivider;
|
|
8003fa0: 4b0a ldr r3, [pc, #40] @ (8003fcc <ReturnTimeElapsed+0x7c>)
|
|
8003fa2: 781b ldrb r3, [r3, #0]
|
|
8003fa4: 461a mov r2, r3
|
|
8003fa6: 687b ldr r3, [r7, #4]
|
|
8003fa8: 40d3 lsrs r3, r2
|
|
8003faa: 607b str r3, [r7, #4]
|
|
8003fac: e001 b.n 8003fb2 <ReturnTimeElapsed+0x62>
|
|
}
|
|
else
|
|
{
|
|
return_value = 0;
|
|
8003fae: 2300 movs r3, #0
|
|
8003fb0: 607b str r3, [r7, #4]
|
|
}
|
|
|
|
return (uint16_t)return_value;
|
|
8003fb2: 687b ldr r3, [r7, #4]
|
|
8003fb4: b29b uxth r3, r3
|
|
}
|
|
8003fb6: 4618 mov r0, r3
|
|
8003fb8: 3708 adds r7, #8
|
|
8003fba: 46bd mov sp, r7
|
|
8003fbc: bd80 pop {r7, pc}
|
|
8003fbe: bf00 nop
|
|
8003fc0: 200003a8 .word 0x200003a8
|
|
8003fc4: 200003b0 .word 0x200003b0
|
|
8003fc8: 200003ae .word 0x200003ae
|
|
8003fcc: 200003ad .word 0x200003ad
|
|
|
|
08003fd0 <RestartWakeupCounter>:
|
|
* It assumes all condition are met to be allowed to write the wakeup counter
|
|
* @param Value: Value to be written in the counter
|
|
* @retval None
|
|
*/
|
|
static void RestartWakeupCounter(uint16_t Value)
|
|
{
|
|
8003fd0: b580 push {r7, lr}
|
|
8003fd2: b082 sub sp, #8
|
|
8003fd4: af00 add r7, sp, #0
|
|
8003fd6: 4603 mov r3, r0
|
|
8003fd8: 80fb strh r3, [r7, #6]
|
|
* The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
|
|
* FLAG when the new value will have to be written
|
|
* __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc);
|
|
*/
|
|
|
|
if(Value == 0)
|
|
8003fda: 88fb ldrh r3, [r7, #6]
|
|
8003fdc: 2b00 cmp r3, #0
|
|
8003fde: d108 bne.n 8003ff2 <RestartWakeupCounter+0x22>
|
|
{
|
|
SSRValueOnLastSetup = ReadRtcSsrValue();
|
|
8003fe0: f7ff fdc2 bl 8003b68 <ReadRtcSsrValue>
|
|
8003fe4: 4603 mov r3, r0
|
|
8003fe6: 4a21 ldr r2, [pc, #132] @ (800406c <RestartWakeupCounter+0x9c>)
|
|
8003fe8: 6013 str r3, [r2, #0]
|
|
|
|
/**
|
|
* Simulate that the Timer expired
|
|
*/
|
|
HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
|
|
8003fea: 2003 movs r0, #3
|
|
8003fec: f002 fe24 bl 8006c38 <HAL_NVIC_SetPendingIRQ>
|
|
__HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */
|
|
|
|
HW_TS_RTC_CountUpdated_AppNot();
|
|
}
|
|
|
|
return ;
|
|
8003ff0: e039 b.n 8004066 <RestartWakeupCounter+0x96>
|
|
if((Value > 1) ||(WakeupTimerDivider != 1))
|
|
8003ff2: 88fb ldrh r3, [r7, #6]
|
|
8003ff4: 2b01 cmp r3, #1
|
|
8003ff6: d803 bhi.n 8004000 <RestartWakeupCounter+0x30>
|
|
8003ff8: 4b1d ldr r3, [pc, #116] @ (8004070 <RestartWakeupCounter+0xa0>)
|
|
8003ffa: 781b ldrb r3, [r3, #0]
|
|
8003ffc: 2b01 cmp r3, #1
|
|
8003ffe: d002 beq.n 8004006 <RestartWakeupCounter+0x36>
|
|
Value -= 1;
|
|
8004000: 88fb ldrh r3, [r7, #6]
|
|
8004002: 3b01 subs r3, #1
|
|
8004004: 80fb strh r3, [r7, #6]
|
|
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
|
|
8004006: bf00 nop
|
|
8004008: 4b1a ldr r3, [pc, #104] @ (8004074 <RestartWakeupCounter+0xa4>)
|
|
800400a: 681b ldr r3, [r3, #0]
|
|
800400c: 68db ldr r3, [r3, #12]
|
|
800400e: f003 0304 and.w r3, r3, #4
|
|
8004012: 2b00 cmp r3, #0
|
|
8004014: d0f8 beq.n 8004008 <RestartWakeupCounter+0x38>
|
|
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
|
|
8004016: 4b17 ldr r3, [pc, #92] @ (8004074 <RestartWakeupCounter+0xa4>)
|
|
8004018: 681b ldr r3, [r3, #0]
|
|
800401a: 68db ldr r3, [r3, #12]
|
|
800401c: b2da uxtb r2, r3
|
|
800401e: 4b15 ldr r3, [pc, #84] @ (8004074 <RestartWakeupCounter+0xa4>)
|
|
8004020: 681b ldr r3, [r3, #0]
|
|
8004022: f462 6290 orn r2, r2, #1152 @ 0x480
|
|
8004026: 60da str r2, [r3, #12]
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
|
|
8004028: 4b13 ldr r3, [pc, #76] @ (8004078 <RestartWakeupCounter+0xa8>)
|
|
800402a: f44f 2200 mov.w r2, #524288 @ 0x80000
|
|
800402e: 60da str r2, [r3, #12]
|
|
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
|
|
8004030: 2003 movs r0, #3
|
|
8004032: f002 fe0f bl 8006c54 <HAL_NVIC_ClearPendingIRQ>
|
|
MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
|
|
8004036: 4b11 ldr r3, [pc, #68] @ (800407c <RestartWakeupCounter+0xac>)
|
|
8004038: 695b ldr r3, [r3, #20]
|
|
800403a: 0c1b lsrs r3, r3, #16
|
|
800403c: 041b lsls r3, r3, #16
|
|
800403e: 88fa ldrh r2, [r7, #6]
|
|
8004040: 490e ldr r1, [pc, #56] @ (800407c <RestartWakeupCounter+0xac>)
|
|
8004042: 4313 orrs r3, r2
|
|
8004044: 614b str r3, [r1, #20]
|
|
SSRValueOnLastSetup = ReadRtcSsrValue();
|
|
8004046: f7ff fd8f bl 8003b68 <ReadRtcSsrValue>
|
|
800404a: 4603 mov r3, r0
|
|
800404c: 4a07 ldr r2, [pc, #28] @ (800406c <RestartWakeupCounter+0x9c>)
|
|
800404e: 6013 str r3, [r2, #0]
|
|
__HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */
|
|
8004050: 4b08 ldr r3, [pc, #32] @ (8004074 <RestartWakeupCounter+0xa4>)
|
|
8004052: 681b ldr r3, [r3, #0]
|
|
8004054: 689a ldr r2, [r3, #8]
|
|
8004056: 4b07 ldr r3, [pc, #28] @ (8004074 <RestartWakeupCounter+0xa4>)
|
|
8004058: 681b ldr r3, [r3, #0]
|
|
800405a: f442 6280 orr.w r2, r2, #1024 @ 0x400
|
|
800405e: 609a str r2, [r3, #8]
|
|
HW_TS_RTC_CountUpdated_AppNot();
|
|
8004060: f3af 8000 nop.w
|
|
return ;
|
|
8004064: bf00 nop
|
|
}
|
|
8004066: 3708 adds r7, #8
|
|
8004068: 46bd mov sp, r7
|
|
800406a: bd80 pop {r7, pc}
|
|
800406c: 200003a8 .word 0x200003a8
|
|
8004070: 200003ad .word 0x200003ad
|
|
8004074: 20000504 .word 0x20000504
|
|
8004078: 58000800 .word 0x58000800
|
|
800407c: 40002800 .word 0x40002800
|
|
|
|
08004080 <RescheduleTimerList>:
|
|
* 2) Setup the wakeuptimer
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void RescheduleTimerList(void)
|
|
{
|
|
8004080: b580 push {r7, lr}
|
|
8004082: b084 sub sp, #16
|
|
8004084: af00 add r7, sp, #0
|
|
|
|
/**
|
|
* The wakeuptimer is disabled now to reduce the time to poll the WUTWF
|
|
* FLAG when the new value will have to be written
|
|
*/
|
|
if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
|
|
8004086: 4b45 ldr r3, [pc, #276] @ (800419c <RescheduleTimerList+0x11c>)
|
|
8004088: 689b ldr r3, [r3, #8]
|
|
800408a: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800408e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8004092: d107 bne.n 80040a4 <RescheduleTimerList+0x24>
|
|
{
|
|
/**
|
|
* Wait for the flag to be back to 0 when the wakeup timer is enabled
|
|
*/
|
|
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET);
|
|
8004094: bf00 nop
|
|
8004096: 4b42 ldr r3, [pc, #264] @ (80041a0 <RescheduleTimerList+0x120>)
|
|
8004098: 681b ldr r3, [r3, #0]
|
|
800409a: 68db ldr r3, [r3, #12]
|
|
800409c: f003 0304 and.w r3, r3, #4
|
|
80040a0: 2b00 cmp r3, #0
|
|
80040a2: d1f8 bne.n 8004096 <RescheduleTimerList+0x16>
|
|
}
|
|
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
|
|
80040a4: 4b3e ldr r3, [pc, #248] @ (80041a0 <RescheduleTimerList+0x120>)
|
|
80040a6: 681b ldr r3, [r3, #0]
|
|
80040a8: 689a ldr r2, [r3, #8]
|
|
80040aa: 4b3d ldr r3, [pc, #244] @ (80041a0 <RescheduleTimerList+0x120>)
|
|
80040ac: 681b ldr r3, [r3, #0]
|
|
80040ae: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
80040b2: 609a str r2, [r3, #8]
|
|
|
|
localTimerID = CurrentRunningTimerID;
|
|
80040b4: 4b3b ldr r3, [pc, #236] @ (80041a4 <RescheduleTimerList+0x124>)
|
|
80040b6: 781b ldrb r3, [r3, #0]
|
|
80040b8: 73fb strb r3, [r7, #15]
|
|
|
|
/**
|
|
* Calculate what will be the value to write in the wakeuptimer
|
|
*/
|
|
timecountleft = aTimerContext[localTimerID].CountLeft;
|
|
80040ba: 7bfa ldrb r2, [r7, #15]
|
|
80040bc: 493a ldr r1, [pc, #232] @ (80041a8 <RescheduleTimerList+0x128>)
|
|
80040be: 4613 mov r3, r2
|
|
80040c0: 005b lsls r3, r3, #1
|
|
80040c2: 4413 add r3, r2
|
|
80040c4: 00db lsls r3, r3, #3
|
|
80040c6: 440b add r3, r1
|
|
80040c8: 3308 adds r3, #8
|
|
80040ca: 681b ldr r3, [r3, #0]
|
|
80040cc: 60bb str r3, [r7, #8]
|
|
|
|
/**
|
|
* Read how much has been counted
|
|
*/
|
|
time_elapsed = ReturnTimeElapsed();
|
|
80040ce: f7ff ff3f bl 8003f50 <ReturnTimeElapsed>
|
|
80040d2: 4603 mov r3, r0
|
|
80040d4: 80fb strh r3, [r7, #6]
|
|
|
|
if(timecountleft < time_elapsed )
|
|
80040d6: 88fb ldrh r3, [r7, #6]
|
|
80040d8: 68ba ldr r2, [r7, #8]
|
|
80040da: 429a cmp r2, r3
|
|
80040dc: d205 bcs.n 80040ea <RescheduleTimerList+0x6a>
|
|
{
|
|
/**
|
|
* There is no tick left to count
|
|
*/
|
|
wakeup_timer_value = 0;
|
|
80040de: 2300 movs r3, #0
|
|
80040e0: 81bb strh r3, [r7, #12]
|
|
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
|
|
80040e2: 4b32 ldr r3, [pc, #200] @ (80041ac <RescheduleTimerList+0x12c>)
|
|
80040e4: 2201 movs r2, #1
|
|
80040e6: 701a strb r2, [r3, #0]
|
|
80040e8: e04d b.n 8004186 <RescheduleTimerList+0x106>
|
|
}
|
|
else
|
|
{
|
|
if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
|
|
80040ea: 88fb ldrh r3, [r7, #6]
|
|
80040ec: 4a30 ldr r2, [pc, #192] @ (80041b0 <RescheduleTimerList+0x130>)
|
|
80040ee: 8812 ldrh r2, [r2, #0]
|
|
80040f0: b292 uxth r2, r2
|
|
80040f2: 4413 add r3, r2
|
|
80040f4: 461a mov r2, r3
|
|
80040f6: 68bb ldr r3, [r7, #8]
|
|
80040f8: 4293 cmp r3, r2
|
|
80040fa: d906 bls.n 800410a <RescheduleTimerList+0x8a>
|
|
{
|
|
/**
|
|
* The number of tick left is greater than the Wakeuptimer maximum value
|
|
*/
|
|
wakeup_timer_value = MaxWakeupTimerSetup;
|
|
80040fc: 4b2c ldr r3, [pc, #176] @ (80041b0 <RescheduleTimerList+0x130>)
|
|
80040fe: 881b ldrh r3, [r3, #0]
|
|
8004100: 81bb strh r3, [r7, #12]
|
|
|
|
WakeupTimerLimitation = WakeupTimerValue_Overpassed;
|
|
8004102: 4b2a ldr r3, [pc, #168] @ (80041ac <RescheduleTimerList+0x12c>)
|
|
8004104: 2200 movs r2, #0
|
|
8004106: 701a strb r2, [r3, #0]
|
|
8004108: e03d b.n 8004186 <RescheduleTimerList+0x106>
|
|
}
|
|
else
|
|
{
|
|
wakeup_timer_value = timecountleft - time_elapsed;
|
|
800410a: 68bb ldr r3, [r7, #8]
|
|
800410c: b29a uxth r2, r3
|
|
800410e: 88fb ldrh r3, [r7, #6]
|
|
8004110: 1ad3 subs r3, r2, r3
|
|
8004112: 81bb strh r3, [r7, #12]
|
|
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
|
|
8004114: 4b25 ldr r3, [pc, #148] @ (80041ac <RescheduleTimerList+0x12c>)
|
|
8004116: 2201 movs r2, #1
|
|
8004118: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/**
|
|
* update ticks left to be counted for each timer
|
|
*/
|
|
while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
|
800411a: e034 b.n 8004186 <RescheduleTimerList+0x106>
|
|
{
|
|
if (aTimerContext[localTimerID].CountLeft < time_elapsed)
|
|
800411c: 7bfa ldrb r2, [r7, #15]
|
|
800411e: 4922 ldr r1, [pc, #136] @ (80041a8 <RescheduleTimerList+0x128>)
|
|
8004120: 4613 mov r3, r2
|
|
8004122: 005b lsls r3, r3, #1
|
|
8004124: 4413 add r3, r2
|
|
8004126: 00db lsls r3, r3, #3
|
|
8004128: 440b add r3, r1
|
|
800412a: 3308 adds r3, #8
|
|
800412c: 681a ldr r2, [r3, #0]
|
|
800412e: 88fb ldrh r3, [r7, #6]
|
|
8004130: 429a cmp r2, r3
|
|
8004132: d20a bcs.n 800414a <RescheduleTimerList+0xca>
|
|
{
|
|
aTimerContext[localTimerID].CountLeft = 0;
|
|
8004134: 7bfa ldrb r2, [r7, #15]
|
|
8004136: 491c ldr r1, [pc, #112] @ (80041a8 <RescheduleTimerList+0x128>)
|
|
8004138: 4613 mov r3, r2
|
|
800413a: 005b lsls r3, r3, #1
|
|
800413c: 4413 add r3, r2
|
|
800413e: 00db lsls r3, r3, #3
|
|
8004140: 440b add r3, r1
|
|
8004142: 3308 adds r3, #8
|
|
8004144: 2200 movs r2, #0
|
|
8004146: 601a str r2, [r3, #0]
|
|
8004148: e013 b.n 8004172 <RescheduleTimerList+0xf2>
|
|
}
|
|
else
|
|
{
|
|
aTimerContext[localTimerID].CountLeft -= time_elapsed;
|
|
800414a: 7bfa ldrb r2, [r7, #15]
|
|
800414c: 4916 ldr r1, [pc, #88] @ (80041a8 <RescheduleTimerList+0x128>)
|
|
800414e: 4613 mov r3, r2
|
|
8004150: 005b lsls r3, r3, #1
|
|
8004152: 4413 add r3, r2
|
|
8004154: 00db lsls r3, r3, #3
|
|
8004156: 440b add r3, r1
|
|
8004158: 3308 adds r3, #8
|
|
800415a: 6819 ldr r1, [r3, #0]
|
|
800415c: 88fb ldrh r3, [r7, #6]
|
|
800415e: 7bfa ldrb r2, [r7, #15]
|
|
8004160: 1ac9 subs r1, r1, r3
|
|
8004162: 4811 ldr r0, [pc, #68] @ (80041a8 <RescheduleTimerList+0x128>)
|
|
8004164: 4613 mov r3, r2
|
|
8004166: 005b lsls r3, r3, #1
|
|
8004168: 4413 add r3, r2
|
|
800416a: 00db lsls r3, r3, #3
|
|
800416c: 4403 add r3, r0
|
|
800416e: 3308 adds r3, #8
|
|
8004170: 6019 str r1, [r3, #0]
|
|
}
|
|
localTimerID = aTimerContext[localTimerID].NextID;
|
|
8004172: 7bfa ldrb r2, [r7, #15]
|
|
8004174: 490c ldr r1, [pc, #48] @ (80041a8 <RescheduleTimerList+0x128>)
|
|
8004176: 4613 mov r3, r2
|
|
8004178: 005b lsls r3, r3, #1
|
|
800417a: 4413 add r3, r2
|
|
800417c: 00db lsls r3, r3, #3
|
|
800417e: 440b add r3, r1
|
|
8004180: 3315 adds r3, #21
|
|
8004182: 781b ldrb r3, [r3, #0]
|
|
8004184: 73fb strb r3, [r7, #15]
|
|
while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
|
8004186: 7bfb ldrb r3, [r7, #15]
|
|
8004188: 2b06 cmp r3, #6
|
|
800418a: d1c7 bne.n 800411c <RescheduleTimerList+0x9c>
|
|
}
|
|
|
|
/**
|
|
* Write next count
|
|
*/
|
|
RestartWakeupCounter(wakeup_timer_value);
|
|
800418c: 89bb ldrh r3, [r7, #12]
|
|
800418e: 4618 mov r0, r3
|
|
8004190: f7ff ff1e bl 8003fd0 <RestartWakeupCounter>
|
|
|
|
return ;
|
|
8004194: bf00 nop
|
|
}
|
|
8004196: 3710 adds r7, #16
|
|
8004198: 46bd mov sp, r7
|
|
800419a: bd80 pop {r7, pc}
|
|
800419c: 40002800 .word 0x40002800
|
|
80041a0: 20000504 .word 0x20000504
|
|
80041a4: 200003a4 .word 0x200003a4
|
|
80041a8: 20000314 .word 0x20000314
|
|
80041ac: 200003ac .word 0x200003ac
|
|
80041b0: 200003b2 .word 0x200003b2
|
|
|
|
080041b4 <HW_TS_RTC_Wakeup_Handler>:
|
|
* In order to ease maintainability, the unlock is done at the top and the lock at then end
|
|
* in case some new implementation is coming in the future
|
|
*/
|
|
|
|
void HW_TS_RTC_Wakeup_Handler(void)
|
|
{
|
|
80041b4: b580 push {r7, lr}
|
|
80041b6: b08a sub sp, #40 @ 0x28
|
|
80041b8: af00 add r7, sp, #0
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80041ba: f3ef 8310 mrs r3, PRIMASK
|
|
80041be: 617b str r3, [r7, #20]
|
|
return(result);
|
|
80041c0: 697b ldr r3, [r7, #20]
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
uint32_t primask_bit;
|
|
#endif
|
|
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
|
80041c2: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80041c4: b672 cpsid i
|
|
}
|
|
80041c6: bf00 nop
|
|
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
|
#endif
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
|
80041c8: 4b59 ldr r3, [pc, #356] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
80041ca: 681b ldr r3, [r3, #0]
|
|
80041cc: 22ca movs r2, #202 @ 0xca
|
|
80041ce: 625a str r2, [r3, #36] @ 0x24
|
|
80041d0: 4b57 ldr r3, [pc, #348] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
80041d2: 681b ldr r3, [r3, #0]
|
|
80041d4: 2253 movs r2, #83 @ 0x53
|
|
80041d6: 625a str r2, [r3, #36] @ 0x24
|
|
/**
|
|
* Disable the Wakeup Timer
|
|
* This may speed up a bit the processing to wait the timer to be disabled
|
|
* The timer is still counting 2 RTCCLK
|
|
*/
|
|
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc);
|
|
80041d8: 4b55 ldr r3, [pc, #340] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
80041da: 681b ldr r3, [r3, #0]
|
|
80041dc: 689a ldr r2, [r3, #8]
|
|
80041de: 4b54 ldr r3, [pc, #336] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
80041e0: 681b ldr r3, [r3, #0]
|
|
80041e2: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
80041e6: 609a str r2, [r3, #8]
|
|
|
|
local_current_running_timer_id = CurrentRunningTimerID;
|
|
80041e8: 4b52 ldr r3, [pc, #328] @ (8004334 <HW_TS_RTC_Wakeup_Handler+0x180>)
|
|
80041ea: 781b ldrb r3, [r3, #0]
|
|
80041ec: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
|
|
if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
|
|
80041f0: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
|
|
80041f4: 4950 ldr r1, [pc, #320] @ (8004338 <HW_TS_RTC_Wakeup_Handler+0x184>)
|
|
80041f6: 4613 mov r3, r2
|
|
80041f8: 005b lsls r3, r3, #1
|
|
80041fa: 4413 add r3, r2
|
|
80041fc: 00db lsls r3, r3, #3
|
|
80041fe: 440b add r3, r1
|
|
8004200: 330c adds r3, #12
|
|
8004202: 781b ldrb r3, [r3, #0]
|
|
8004204: b2db uxtb r3, r3
|
|
8004206: 2b02 cmp r3, #2
|
|
8004208: d16e bne.n 80042e8 <HW_TS_RTC_Wakeup_Handler+0x134>
|
|
{
|
|
ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
|
|
800420a: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
|
|
800420e: 494a ldr r1, [pc, #296] @ (8004338 <HW_TS_RTC_Wakeup_Handler+0x184>)
|
|
8004210: 4613 mov r3, r2
|
|
8004212: 005b lsls r3, r3, #1
|
|
8004214: 4413 add r3, r2
|
|
8004216: 00db lsls r3, r3, #3
|
|
8004218: 440b add r3, r1
|
|
800421a: 681b ldr r3, [r3, #0]
|
|
800421c: 61fb str r3, [r7, #28]
|
|
timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
|
|
800421e: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
|
|
8004222: 4945 ldr r1, [pc, #276] @ (8004338 <HW_TS_RTC_Wakeup_Handler+0x184>)
|
|
8004224: 4613 mov r3, r2
|
|
8004226: 005b lsls r3, r3, #1
|
|
8004228: 4413 add r3, r2
|
|
800422a: 00db lsls r3, r3, #3
|
|
800422c: 440b add r3, r1
|
|
800422e: 3310 adds r3, #16
|
|
8004230: 681b ldr r3, [r3, #0]
|
|
8004232: 61bb str r3, [r7, #24]
|
|
* However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
|
|
* to be left whereas the count is over
|
|
* A more secure implementation has been done with a flag to state whereas the full count has been written
|
|
* in the wakeuptimer or not
|
|
*/
|
|
if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
|
|
8004234: 4b41 ldr r3, [pc, #260] @ (800433c <HW_TS_RTC_Wakeup_Handler+0x188>)
|
|
8004236: 781b ldrb r3, [r3, #0]
|
|
8004238: b2db uxtb r3, r3
|
|
800423a: 2b00 cmp r3, #0
|
|
800423c: d04c beq.n 80042d8 <HW_TS_RTC_Wakeup_Handler+0x124>
|
|
{
|
|
if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
|
|
800423e: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
|
|
8004242: 493d ldr r1, [pc, #244] @ (8004338 <HW_TS_RTC_Wakeup_Handler+0x184>)
|
|
8004244: 4613 mov r3, r2
|
|
8004246: 005b lsls r3, r3, #1
|
|
8004248: 4413 add r3, r2
|
|
800424a: 00db lsls r3, r3, #3
|
|
800424c: 440b add r3, r1
|
|
800424e: 330d adds r3, #13
|
|
8004250: 781b ldrb r3, [r3, #0]
|
|
8004252: b2db uxtb r3, r3
|
|
8004254: 2b01 cmp r3, #1
|
|
8004256: d124 bne.n 80042a2 <HW_TS_RTC_Wakeup_Handler+0xee>
|
|
{
|
|
UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
|
|
8004258: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
800425c: 2101 movs r1, #1
|
|
800425e: 4618 mov r0, r3
|
|
8004260: f7ff fdf2 bl 8003e48 <UnlinkTimer>
|
|
8004264: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004266: 613b str r3, [r7, #16]
|
|
\details Assigns the given value to the Priority Mask Register.
|
|
\param [in] priMask Priority Mask
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
|
|
{
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004268: 693b ldr r3, [r7, #16]
|
|
800426a: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800426e: bf00 nop
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
#endif
|
|
HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
|
|
8004270: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
|
|
8004274: 4930 ldr r1, [pc, #192] @ (8004338 <HW_TS_RTC_Wakeup_Handler+0x184>)
|
|
8004276: 4613 mov r3, r2
|
|
8004278: 005b lsls r3, r3, #1
|
|
800427a: 4413 add r3, r2
|
|
800427c: 00db lsls r3, r3, #3
|
|
800427e: 440b add r3, r1
|
|
8004280: 3304 adds r3, #4
|
|
8004282: 681a ldr r2, [r3, #0]
|
|
8004284: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8004288: 4611 mov r1, r2
|
|
800428a: 4618 mov r0, r3
|
|
800428c: f000 f9b8 bl 8004600 <HW_TS_Start>
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
|
8004290: 4b27 ldr r3, [pc, #156] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
8004292: 681b ldr r3, [r3, #0]
|
|
8004294: 22ca movs r2, #202 @ 0xca
|
|
8004296: 625a str r2, [r3, #36] @ 0x24
|
|
8004298: 4b25 ldr r3, [pc, #148] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
800429a: 681b ldr r3, [r3, #0]
|
|
800429c: 2253 movs r2, #83 @ 0x53
|
|
800429e: 625a str r2, [r3, #36] @ 0x24
|
|
80042a0: e012 b.n 80042c8 <HW_TS_RTC_Wakeup_Handler+0x114>
|
|
80042a2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80042a4: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80042a6: 68fb ldr r3, [r7, #12]
|
|
80042a8: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80042ac: bf00 nop
|
|
else
|
|
{
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
#endif
|
|
HW_TS_Stop(local_current_running_timer_id);
|
|
80042ae: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
80042b2: 4618 mov r0, r3
|
|
80042b4: f000 f920 bl 80044f8 <HW_TS_Stop>
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
|
80042b8: 4b1d ldr r3, [pc, #116] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
80042ba: 681b ldr r3, [r3, #0]
|
|
80042bc: 22ca movs r2, #202 @ 0xca
|
|
80042be: 625a str r2, [r3, #36] @ 0x24
|
|
80042c0: 4b1b ldr r3, [pc, #108] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
80042c2: 681b ldr r3, [r3, #0]
|
|
80042c4: 2253 movs r2, #83 @ 0x53
|
|
80042c6: 625a str r2, [r3, #36] @ 0x24
|
|
}
|
|
|
|
HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
|
|
80042c8: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
80042cc: 69fa ldr r2, [r7, #28]
|
|
80042ce: 4619 mov r1, r3
|
|
80042d0: 69b8 ldr r0, [r7, #24]
|
|
80042d2: f000 fa1b bl 800470c <HW_TS_RTC_Int_AppNot>
|
|
80042d6: e022 b.n 800431e <HW_TS_RTC_Wakeup_Handler+0x16a>
|
|
}
|
|
else
|
|
{
|
|
RescheduleTimerList();
|
|
80042d8: f7ff fed2 bl 8004080 <RescheduleTimerList>
|
|
80042dc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80042de: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80042e0: 68bb ldr r3, [r7, #8]
|
|
80042e2: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80042e6: e01a b.n 800431e <HW_TS_RTC_Wakeup_Handler+0x16a>
|
|
/**
|
|
* We should never end up in this case
|
|
* However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
|
|
* We could just clean the interrupt flag and get out from this unexpected interrupt
|
|
*/
|
|
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
|
|
80042e8: bf00 nop
|
|
80042ea: 4b11 ldr r3, [pc, #68] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
80042ec: 681b ldr r3, [r3, #0]
|
|
80042ee: 68db ldr r3, [r3, #12]
|
|
80042f0: f003 0304 and.w r3, r3, #4
|
|
80042f4: 2b00 cmp r3, #0
|
|
80042f6: d0f8 beq.n 80042ea <HW_TS_RTC_Wakeup_Handler+0x136>
|
|
* It takes 2 RTCCLK between the time the WUTE bit is disabled and the
|
|
* time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
|
|
* Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
|
|
* due to the autoreload feature
|
|
*/
|
|
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
|
|
80042f8: 4b0d ldr r3, [pc, #52] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
80042fa: 681b ldr r3, [r3, #0]
|
|
80042fc: 68db ldr r3, [r3, #12]
|
|
80042fe: b2da uxtb r2, r3
|
|
8004300: 4b0b ldr r3, [pc, #44] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
8004302: 681b ldr r3, [r3, #0]
|
|
8004304: f462 6290 orn r2, r2, #1152 @ 0x480
|
|
8004308: 60da str r2, [r3, #12]
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
|
|
800430a: 4b0d ldr r3, [pc, #52] @ (8004340 <HW_TS_RTC_Wakeup_Handler+0x18c>)
|
|
800430c: f44f 2200 mov.w r2, #524288 @ 0x80000
|
|
8004310: 60da str r2, [r3, #12]
|
|
8004312: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004314: 607b str r3, [r7, #4]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004316: 687b ldr r3, [r7, #4]
|
|
8004318: f383 8810 msr PRIMASK, r3
|
|
}
|
|
800431c: bf00 nop
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
#endif
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
|
|
800431e: 4b04 ldr r3, [pc, #16] @ (8004330 <HW_TS_RTC_Wakeup_Handler+0x17c>)
|
|
8004320: 681b ldr r3, [r3, #0]
|
|
8004322: 22ff movs r2, #255 @ 0xff
|
|
8004324: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return;
|
|
8004326: bf00 nop
|
|
}
|
|
8004328: 3728 adds r7, #40 @ 0x28
|
|
800432a: 46bd mov sp, r7
|
|
800432c: bd80 pop {r7, pc}
|
|
800432e: bf00 nop
|
|
8004330: 20000504 .word 0x20000504
|
|
8004334: 200003a4 .word 0x200003a4
|
|
8004338: 20000314 .word 0x20000314
|
|
800433c: 200003ac .word 0x200003ac
|
|
8004340: 58000800 .word 0x58000800
|
|
|
|
08004344 <HW_TS_Init>:
|
|
|
|
void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *phrtc)
|
|
{
|
|
8004344: b580 push {r7, lr}
|
|
8004346: b088 sub sp, #32
|
|
8004348: af00 add r7, sp, #0
|
|
800434a: 4603 mov r3, r0
|
|
800434c: 6039 str r1, [r7, #0]
|
|
800434e: 71fb strb r3, [r7, #7]
|
|
uint8_t loop;
|
|
uint32_t localmaxwakeuptimersetup;
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
|
8004350: 4b5e ldr r3, [pc, #376] @ (80044cc <HW_TS_Init+0x188>)
|
|
8004352: 681b ldr r3, [r3, #0]
|
|
8004354: 22ca movs r2, #202 @ 0xca
|
|
8004356: 625a str r2, [r3, #36] @ 0x24
|
|
8004358: 4b5c ldr r3, [pc, #368] @ (80044cc <HW_TS_Init+0x188>)
|
|
800435a: 681b ldr r3, [r3, #0]
|
|
800435c: 2253 movs r2, #83 @ 0x53
|
|
800435e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
|
8004360: 4b5b ldr r3, [pc, #364] @ (80044d0 <HW_TS_Init+0x18c>)
|
|
8004362: 689b ldr r3, [r3, #8]
|
|
8004364: 4a5a ldr r2, [pc, #360] @ (80044d0 <HW_TS_Init+0x18c>)
|
|
8004366: f043 0320 orr.w r3, r3, #32
|
|
800436a: 6093 str r3, [r2, #8]
|
|
|
|
/**
|
|
* Readout the user config
|
|
*/
|
|
WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
|
|
800436c: 4b58 ldr r3, [pc, #352] @ (80044d0 <HW_TS_Init+0x18c>)
|
|
800436e: 689b ldr r3, [r3, #8]
|
|
8004370: b2db uxtb r3, r3
|
|
8004372: f003 0307 and.w r3, r3, #7
|
|
8004376: b2db uxtb r3, r3
|
|
8004378: f1c3 0304 rsb r3, r3, #4
|
|
800437c: b2da uxtb r2, r3
|
|
800437e: 4b55 ldr r3, [pc, #340] @ (80044d4 <HW_TS_Init+0x190>)
|
|
8004380: 701a strb r2, [r3, #0]
|
|
|
|
AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
|
|
8004382: 4b53 ldr r3, [pc, #332] @ (80044d0 <HW_TS_Init+0x18c>)
|
|
8004384: 691b ldr r3, [r3, #16]
|
|
8004386: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000
|
|
800438a: f44f 02fe mov.w r2, #8323072 @ 0x7f0000
|
|
800438e: 613a str r2, [r7, #16]
|
|
uint32_t result;
|
|
|
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
|
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
|
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004390: 693a ldr r2, [r7, #16]
|
|
8004392: fa92 f2a2 rbit r2, r2
|
|
8004396: 60fa str r2, [r7, #12]
|
|
result |= value & 1U;
|
|
s--;
|
|
}
|
|
result <<= s; /* shift when v's highest bits are zero */
|
|
#endif
|
|
return result;
|
|
8004398: 68fa ldr r2, [r7, #12]
|
|
800439a: 617a str r2, [r7, #20]
|
|
optimisations using the logic "value was passed to __builtin_clz, so it
|
|
is non-zero".
|
|
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
|
|
single CLZ instruction.
|
|
*/
|
|
if (value == 0U)
|
|
800439c: 697a ldr r2, [r7, #20]
|
|
800439e: 2a00 cmp r2, #0
|
|
80043a0: d101 bne.n 80043a6 <HW_TS_Init+0x62>
|
|
{
|
|
return 32U;
|
|
80043a2: 2220 movs r2, #32
|
|
80043a4: e003 b.n 80043ae <HW_TS_Init+0x6a>
|
|
}
|
|
return __builtin_clz(value);
|
|
80043a6: 697a ldr r2, [r7, #20]
|
|
80043a8: fab2 f282 clz r2, r2
|
|
80043ac: b2d2 uxtb r2, r2
|
|
80043ae: 40d3 lsrs r3, r2
|
|
80043b0: b2db uxtb r3, r3
|
|
80043b2: 3301 adds r3, #1
|
|
80043b4: b2da uxtb r2, r3
|
|
80043b6: 4b48 ldr r3, [pc, #288] @ (80044d8 <HW_TS_Init+0x194>)
|
|
80043b8: 701a strb r2, [r3, #0]
|
|
|
|
SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
|
|
80043ba: 4b45 ldr r3, [pc, #276] @ (80044d0 <HW_TS_Init+0x18c>)
|
|
80043bc: 691b ldr r3, [r3, #16]
|
|
80043be: b29b uxth r3, r3
|
|
80043c0: f3c3 030e ubfx r3, r3, #0, #15
|
|
80043c4: b29b uxth r3, r3
|
|
80043c6: 3301 adds r3, #1
|
|
80043c8: b29a uxth r2, r3
|
|
80043ca: 4b44 ldr r3, [pc, #272] @ (80044dc <HW_TS_Init+0x198>)
|
|
80043cc: 801a strh r2, [r3, #0]
|
|
|
|
/**
|
|
* Margin is taken to avoid wrong calculation when the wrap around is there and some
|
|
* application interrupts may have delayed the reading
|
|
*/
|
|
localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
|
|
80043ce: 4b43 ldr r3, [pc, #268] @ (80044dc <HW_TS_Init+0x198>)
|
|
80043d0: 881b ldrh r3, [r3, #0]
|
|
80043d2: 3b01 subs r3, #1
|
|
80043d4: 4a40 ldr r2, [pc, #256] @ (80044d8 <HW_TS_Init+0x194>)
|
|
80043d6: 7812 ldrb r2, [r2, #0]
|
|
80043d8: fb02 f303 mul.w r3, r2, r3
|
|
80043dc: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
|
|
80043e0: 4a3c ldr r2, [pc, #240] @ (80044d4 <HW_TS_Init+0x190>)
|
|
80043e2: 7812 ldrb r2, [r2, #0]
|
|
80043e4: 40d3 lsrs r3, r2
|
|
80043e6: 61bb str r3, [r7, #24]
|
|
|
|
if(localmaxwakeuptimersetup >= 0xFFFF)
|
|
80043e8: 69bb ldr r3, [r7, #24]
|
|
80043ea: f64f 72fe movw r2, #65534 @ 0xfffe
|
|
80043ee: 4293 cmp r3, r2
|
|
80043f0: d904 bls.n 80043fc <HW_TS_Init+0xb8>
|
|
{
|
|
MaxWakeupTimerSetup = 0xFFFF;
|
|
80043f2: 4b3b ldr r3, [pc, #236] @ (80044e0 <HW_TS_Init+0x19c>)
|
|
80043f4: f64f 72ff movw r2, #65535 @ 0xffff
|
|
80043f8: 801a strh r2, [r3, #0]
|
|
80043fa: e003 b.n 8004404 <HW_TS_Init+0xc0>
|
|
}
|
|
else
|
|
{
|
|
MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
|
|
80043fc: 69bb ldr r3, [r7, #24]
|
|
80043fe: b29a uxth r2, r3
|
|
8004400: 4b37 ldr r3, [pc, #220] @ (80044e0 <HW_TS_Init+0x19c>)
|
|
8004402: 801a strh r2, [r3, #0]
|
|
}
|
|
|
|
/**
|
|
* Configure EXTI module
|
|
*/
|
|
LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
|
|
8004404: f44f 2000 mov.w r0, #524288 @ 0x80000
|
|
8004408: f7ff fb9c bl 8003b44 <LL_EXTI_EnableRisingTrig_0_31>
|
|
LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
|
|
800440c: f44f 2000 mov.w r0, #524288 @ 0x80000
|
|
8004410: f7ff fb84 bl 8003b1c <LL_EXTI_EnableIT_0_31>
|
|
|
|
if(TimerInitMode == hw_ts_InitMode_Full)
|
|
8004414: 79fb ldrb r3, [r7, #7]
|
|
8004416: 2b00 cmp r3, #0
|
|
8004418: d13d bne.n 8004496 <HW_TS_Init+0x152>
|
|
{
|
|
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
|
|
800441a: 4b32 ldr r3, [pc, #200] @ (80044e4 <HW_TS_Init+0x1a0>)
|
|
800441c: 2201 movs r2, #1
|
|
800441e: 701a strb r2, [r3, #0]
|
|
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
|
|
8004420: 4b31 ldr r3, [pc, #196] @ (80044e8 <HW_TS_Init+0x1a4>)
|
|
8004422: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8004426: 601a str r2, [r3, #0]
|
|
|
|
/**
|
|
* Initialize the timer server
|
|
*/
|
|
for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
|
|
8004428: 2300 movs r3, #0
|
|
800442a: 77fb strb r3, [r7, #31]
|
|
800442c: e00c b.n 8004448 <HW_TS_Init+0x104>
|
|
{
|
|
aTimerContext[loop].TimerIDStatus = TimerID_Free;
|
|
800442e: 7ffa ldrb r2, [r7, #31]
|
|
8004430: 492e ldr r1, [pc, #184] @ (80044ec <HW_TS_Init+0x1a8>)
|
|
8004432: 4613 mov r3, r2
|
|
8004434: 005b lsls r3, r3, #1
|
|
8004436: 4413 add r3, r2
|
|
8004438: 00db lsls r3, r3, #3
|
|
800443a: 440b add r3, r1
|
|
800443c: 330c adds r3, #12
|
|
800443e: 2200 movs r2, #0
|
|
8004440: 701a strb r2, [r3, #0]
|
|
for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
|
|
8004442: 7ffb ldrb r3, [r7, #31]
|
|
8004444: 3301 adds r3, #1
|
|
8004446: 77fb strb r3, [r7, #31]
|
|
8004448: 7ffb ldrb r3, [r7, #31]
|
|
800444a: 2b05 cmp r3, #5
|
|
800444c: d9ef bls.n 800442e <HW_TS_Init+0xea>
|
|
}
|
|
|
|
CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; /**< Set ID to non valid value */
|
|
800444e: 4b28 ldr r3, [pc, #160] @ (80044f0 <HW_TS_Init+0x1ac>)
|
|
8004450: 2206 movs r2, #6
|
|
8004452: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
|
|
8004454: 4b1d ldr r3, [pc, #116] @ (80044cc <HW_TS_Init+0x188>)
|
|
8004456: 681b ldr r3, [r3, #0]
|
|
8004458: 689a ldr r2, [r3, #8]
|
|
800445a: 4b1c ldr r3, [pc, #112] @ (80044cc <HW_TS_Init+0x188>)
|
|
800445c: 681b ldr r3, [r3, #0]
|
|
800445e: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8004462: 609a str r2, [r3, #8]
|
|
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
|
|
8004464: 4b19 ldr r3, [pc, #100] @ (80044cc <HW_TS_Init+0x188>)
|
|
8004466: 681b ldr r3, [r3, #0]
|
|
8004468: 68db ldr r3, [r3, #12]
|
|
800446a: b2da uxtb r2, r3
|
|
800446c: 4b17 ldr r3, [pc, #92] @ (80044cc <HW_TS_Init+0x188>)
|
|
800446e: 681b ldr r3, [r3, #0]
|
|
8004470: f462 6290 orn r2, r2, #1152 @ 0x480
|
|
8004474: 60da str r2, [r3, #12]
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
|
|
8004476: 4b1f ldr r3, [pc, #124] @ (80044f4 <HW_TS_Init+0x1b0>)
|
|
8004478: f44f 2200 mov.w r2, #524288 @ 0x80000
|
|
800447c: 60da str r2, [r3, #12]
|
|
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
|
|
800447e: 2003 movs r0, #3
|
|
8004480: f002 fbe8 bl 8006c54 <HAL_NVIC_ClearPendingIRQ>
|
|
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hrtc, RTC_IT_WUT); /**< Enable interrupt in RTC module */
|
|
8004484: 4b11 ldr r3, [pc, #68] @ (80044cc <HW_TS_Init+0x188>)
|
|
8004486: 681b ldr r3, [r3, #0]
|
|
8004488: 689a ldr r2, [r3, #8]
|
|
800448a: 4b10 ldr r3, [pc, #64] @ (80044cc <HW_TS_Init+0x188>)
|
|
800448c: 681b ldr r3, [r3, #0]
|
|
800448e: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
8004492: 609a str r2, [r3, #8]
|
|
8004494: e009 b.n 80044aa <HW_TS_Init+0x166>
|
|
}
|
|
else
|
|
{
|
|
if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTF) != RESET)
|
|
8004496: 4b0d ldr r3, [pc, #52] @ (80044cc <HW_TS_Init+0x188>)
|
|
8004498: 681b ldr r3, [r3, #0]
|
|
800449a: 68db ldr r3, [r3, #12]
|
|
800449c: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80044a0: 2b00 cmp r3, #0
|
|
80044a2: d002 beq.n 80044aa <HW_TS_Init+0x166>
|
|
{
|
|
/**
|
|
* Simulate that the Timer expired
|
|
*/
|
|
HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
|
|
80044a4: 2003 movs r0, #3
|
|
80044a6: f002 fbc7 bl 8006c38 <HAL_NVIC_SetPendingIRQ>
|
|
}
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
|
|
80044aa: 4b08 ldr r3, [pc, #32] @ (80044cc <HW_TS_Init+0x188>)
|
|
80044ac: 681b ldr r3, [r3, #0]
|
|
80044ae: 22ff movs r2, #255 @ 0xff
|
|
80044b0: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO); /**< Set NVIC priority */
|
|
80044b2: 2200 movs r2, #0
|
|
80044b4: 2106 movs r1, #6
|
|
80044b6: 2003 movs r0, #3
|
|
80044b8: f002 fb88 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
|
|
80044bc: 2003 movs r0, #3
|
|
80044be: f002 fb9f bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
return;
|
|
80044c2: bf00 nop
|
|
}
|
|
80044c4: 3720 adds r7, #32
|
|
80044c6: 46bd mov sp, r7
|
|
80044c8: bd80 pop {r7, pc}
|
|
80044ca: bf00 nop
|
|
80044cc: 20000504 .word 0x20000504
|
|
80044d0: 40002800 .word 0x40002800
|
|
80044d4: 200003ad .word 0x200003ad
|
|
80044d8: 200003ae .word 0x200003ae
|
|
80044dc: 200003b0 .word 0x200003b0
|
|
80044e0: 200003b2 .word 0x200003b2
|
|
80044e4: 200003ac .word 0x200003ac
|
|
80044e8: 200003a8 .word 0x200003a8
|
|
80044ec: 20000314 .word 0x20000314
|
|
80044f0: 200003a4 .word 0x200003a4
|
|
80044f4: 58000800 .word 0x58000800
|
|
|
|
080044f8 <HW_TS_Stop>:
|
|
|
|
return;
|
|
}
|
|
|
|
void HW_TS_Stop(uint8_t timer_id)
|
|
{
|
|
80044f8: b580 push {r7, lr}
|
|
80044fa: b086 sub sp, #24
|
|
80044fc: af00 add r7, sp, #0
|
|
80044fe: 4603 mov r3, r0
|
|
8004500: 71fb strb r3, [r7, #7]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
8004502: f3ef 8310 mrs r3, PRIMASK
|
|
8004506: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8004508: 68fb ldr r3, [r7, #12]
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
uint32_t primask_bit;
|
|
#endif
|
|
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
|
800450a: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800450c: b672 cpsid i
|
|
}
|
|
800450e: bf00 nop
|
|
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
|
#endif
|
|
|
|
HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */
|
|
8004510: 2003 movs r0, #3
|
|
8004512: f002 fb83 bl 8006c1c <HAL_NVIC_DisableIRQ>
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
|
8004516: 4b34 ldr r3, [pc, #208] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
8004518: 681b ldr r3, [r3, #0]
|
|
800451a: 22ca movs r2, #202 @ 0xca
|
|
800451c: 625a str r2, [r3, #36] @ 0x24
|
|
800451e: 4b32 ldr r3, [pc, #200] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
8004520: 681b ldr r3, [r3, #0]
|
|
8004522: 2253 movs r2, #83 @ 0x53
|
|
8004524: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
|
|
8004526: 79fa ldrb r2, [r7, #7]
|
|
8004528: 4930 ldr r1, [pc, #192] @ (80045ec <HW_TS_Stop+0xf4>)
|
|
800452a: 4613 mov r3, r2
|
|
800452c: 005b lsls r3, r3, #1
|
|
800452e: 4413 add r3, r2
|
|
8004530: 00db lsls r3, r3, #3
|
|
8004532: 440b add r3, r1
|
|
8004534: 330c adds r3, #12
|
|
8004536: 781b ldrb r3, [r3, #0]
|
|
8004538: b2db uxtb r3, r3
|
|
800453a: 2b02 cmp r3, #2
|
|
800453c: d142 bne.n 80045c4 <HW_TS_Stop+0xcc>
|
|
{
|
|
UnlinkTimer(timer_id, SSR_Read_Requested);
|
|
800453e: 79fb ldrb r3, [r7, #7]
|
|
8004540: 2100 movs r1, #0
|
|
8004542: 4618 mov r0, r3
|
|
8004544: f7ff fc80 bl 8003e48 <UnlinkTimer>
|
|
localcurrentrunningtimerid = CurrentRunningTimerID;
|
|
8004548: 4b29 ldr r3, [pc, #164] @ (80045f0 <HW_TS_Stop+0xf8>)
|
|
800454a: 781b ldrb r3, [r3, #0]
|
|
800454c: 74fb strb r3, [r7, #19]
|
|
|
|
if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
|
|
800454e: 7cfb ldrb r3, [r7, #19]
|
|
8004550: 2b06 cmp r3, #6
|
|
8004552: d12f bne.n 80045b4 <HW_TS_Stop+0xbc>
|
|
*/
|
|
|
|
/**
|
|
* Disable the timer
|
|
*/
|
|
if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
|
|
8004554: 4b27 ldr r3, [pc, #156] @ (80045f4 <HW_TS_Stop+0xfc>)
|
|
8004556: 689b ldr r3, [r3, #8]
|
|
8004558: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800455c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8004560: d107 bne.n 8004572 <HW_TS_Stop+0x7a>
|
|
{
|
|
/**
|
|
* Wait for the flag to be back to 0 when the wakeup timer is enabled
|
|
*/
|
|
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET);
|
|
8004562: bf00 nop
|
|
8004564: 4b20 ldr r3, [pc, #128] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
8004566: 681b ldr r3, [r3, #0]
|
|
8004568: 68db ldr r3, [r3, #12]
|
|
800456a: f003 0304 and.w r3, r3, #4
|
|
800456e: 2b00 cmp r3, #0
|
|
8004570: d1f8 bne.n 8004564 <HW_TS_Stop+0x6c>
|
|
}
|
|
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
|
|
8004572: 4b1d ldr r3, [pc, #116] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
8004574: 681b ldr r3, [r3, #0]
|
|
8004576: 689a ldr r2, [r3, #8]
|
|
8004578: 4b1b ldr r3, [pc, #108] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
800457a: 681b ldr r3, [r3, #0]
|
|
800457c: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8004580: 609a str r2, [r3, #8]
|
|
|
|
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
|
|
8004582: bf00 nop
|
|
8004584: 4b18 ldr r3, [pc, #96] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
8004586: 681b ldr r3, [r3, #0]
|
|
8004588: 68db ldr r3, [r3, #12]
|
|
800458a: f003 0304 and.w r3, r3, #4
|
|
800458e: 2b00 cmp r3, #0
|
|
8004590: d0f8 beq.n 8004584 <HW_TS_Stop+0x8c>
|
|
* It takes 2 RTCCLK between the time the WUTE bit is disabled and the
|
|
* time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
|
|
* Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
|
|
* due to the autoreload feature
|
|
*/
|
|
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
|
|
8004592: 4b15 ldr r3, [pc, #84] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
8004594: 681b ldr r3, [r3, #0]
|
|
8004596: 68db ldr r3, [r3, #12]
|
|
8004598: b2da uxtb r2, r3
|
|
800459a: 4b13 ldr r3, [pc, #76] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
800459c: 681b ldr r3, [r3, #0]
|
|
800459e: f462 6290 orn r2, r2, #1152 @ 0x480
|
|
80045a2: 60da str r2, [r3, #12]
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
|
|
80045a4: 4b14 ldr r3, [pc, #80] @ (80045f8 <HW_TS_Stop+0x100>)
|
|
80045a6: f44f 2200 mov.w r2, #524288 @ 0x80000
|
|
80045aa: 60da str r2, [r3, #12]
|
|
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
|
|
80045ac: 2003 movs r0, #3
|
|
80045ae: f002 fb51 bl 8006c54 <HAL_NVIC_ClearPendingIRQ>
|
|
80045b2: e007 b.n 80045c4 <HW_TS_Stop+0xcc>
|
|
}
|
|
else if(PreviousRunningTimerID != localcurrentrunningtimerid)
|
|
80045b4: 4b11 ldr r3, [pc, #68] @ (80045fc <HW_TS_Stop+0x104>)
|
|
80045b6: 781b ldrb r3, [r3, #0]
|
|
80045b8: b2db uxtb r3, r3
|
|
80045ba: 7cfa ldrb r2, [r7, #19]
|
|
80045bc: 429a cmp r2, r3
|
|
80045be: d001 beq.n 80045c4 <HW_TS_Stop+0xcc>
|
|
{
|
|
RescheduleTimerList();
|
|
80045c0: f7ff fd5e bl 8004080 <RescheduleTimerList>
|
|
}
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
|
|
80045c4: 4b08 ldr r3, [pc, #32] @ (80045e8 <HW_TS_Stop+0xf0>)
|
|
80045c6: 681b ldr r3, [r3, #0]
|
|
80045c8: 22ff movs r2, #255 @ 0xff
|
|
80045ca: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
|
|
80045cc: 2003 movs r0, #3
|
|
80045ce: f002 fb17 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
80045d2: 697b ldr r3, [r7, #20]
|
|
80045d4: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80045d6: 68bb ldr r3, [r7, #8]
|
|
80045d8: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80045dc: bf00 nop
|
|
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
#endif
|
|
|
|
return;
|
|
80045de: bf00 nop
|
|
}
|
|
80045e0: 3718 adds r7, #24
|
|
80045e2: 46bd mov sp, r7
|
|
80045e4: bd80 pop {r7, pc}
|
|
80045e6: bf00 nop
|
|
80045e8: 20000504 .word 0x20000504
|
|
80045ec: 20000314 .word 0x20000314
|
|
80045f0: 200003a4 .word 0x200003a4
|
|
80045f4: 40002800 .word 0x40002800
|
|
80045f8: 58000800 .word 0x58000800
|
|
80045fc: 200003a5 .word 0x200003a5
|
|
|
|
08004600 <HW_TS_Start>:
|
|
|
|
void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
|
|
{
|
|
8004600: b580 push {r7, lr}
|
|
8004602: b086 sub sp, #24
|
|
8004604: af00 add r7, sp, #0
|
|
8004606: 4603 mov r3, r0
|
|
8004608: 6039 str r1, [r7, #0]
|
|
800460a: 71fb strb r3, [r7, #7]
|
|
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
uint32_t primask_bit;
|
|
#endif
|
|
|
|
if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
|
|
800460c: 79fa ldrb r2, [r7, #7]
|
|
800460e: 493b ldr r1, [pc, #236] @ (80046fc <HW_TS_Start+0xfc>)
|
|
8004610: 4613 mov r3, r2
|
|
8004612: 005b lsls r3, r3, #1
|
|
8004614: 4413 add r3, r2
|
|
8004616: 00db lsls r3, r3, #3
|
|
8004618: 440b add r3, r1
|
|
800461a: 330c adds r3, #12
|
|
800461c: 781b ldrb r3, [r3, #0]
|
|
800461e: b2db uxtb r3, r3
|
|
8004620: 2b02 cmp r3, #2
|
|
8004622: d103 bne.n 800462c <HW_TS_Start+0x2c>
|
|
{
|
|
HW_TS_Stop( timer_id );
|
|
8004624: 79fb ldrb r3, [r7, #7]
|
|
8004626: 4618 mov r0, r3
|
|
8004628: f7ff ff66 bl 80044f8 <HW_TS_Stop>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
800462c: f3ef 8310 mrs r3, PRIMASK
|
|
8004630: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8004632: 68fb ldr r3, [r7, #12]
|
|
}
|
|
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
|
8004634: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8004636: b672 cpsid i
|
|
}
|
|
8004638: bf00 nop
|
|
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
|
#endif
|
|
|
|
HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */
|
|
800463a: 2003 movs r0, #3
|
|
800463c: f002 faee bl 8006c1c <HAL_NVIC_DisableIRQ>
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
|
|
8004640: 4b2f ldr r3, [pc, #188] @ (8004700 <HW_TS_Start+0x100>)
|
|
8004642: 681b ldr r3, [r3, #0]
|
|
8004644: 22ca movs r2, #202 @ 0xca
|
|
8004646: 625a str r2, [r3, #36] @ 0x24
|
|
8004648: 4b2d ldr r3, [pc, #180] @ (8004700 <HW_TS_Start+0x100>)
|
|
800464a: 681b ldr r3, [r3, #0]
|
|
800464c: 2253 movs r2, #83 @ 0x53
|
|
800464e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
|
|
8004650: 79fa ldrb r2, [r7, #7]
|
|
8004652: 492a ldr r1, [pc, #168] @ (80046fc <HW_TS_Start+0xfc>)
|
|
8004654: 4613 mov r3, r2
|
|
8004656: 005b lsls r3, r3, #1
|
|
8004658: 4413 add r3, r2
|
|
800465a: 00db lsls r3, r3, #3
|
|
800465c: 440b add r3, r1
|
|
800465e: 330c adds r3, #12
|
|
8004660: 2202 movs r2, #2
|
|
8004662: 701a strb r2, [r3, #0]
|
|
|
|
aTimerContext[timer_id].CountLeft = timeout_ticks;
|
|
8004664: 79fa ldrb r2, [r7, #7]
|
|
8004666: 4925 ldr r1, [pc, #148] @ (80046fc <HW_TS_Start+0xfc>)
|
|
8004668: 4613 mov r3, r2
|
|
800466a: 005b lsls r3, r3, #1
|
|
800466c: 4413 add r3, r2
|
|
800466e: 00db lsls r3, r3, #3
|
|
8004670: 440b add r3, r1
|
|
8004672: 3308 adds r3, #8
|
|
8004674: 683a ldr r2, [r7, #0]
|
|
8004676: 601a str r2, [r3, #0]
|
|
aTimerContext[timer_id].CounterInit = timeout_ticks;
|
|
8004678: 79fa ldrb r2, [r7, #7]
|
|
800467a: 4920 ldr r1, [pc, #128] @ (80046fc <HW_TS_Start+0xfc>)
|
|
800467c: 4613 mov r3, r2
|
|
800467e: 005b lsls r3, r3, #1
|
|
8004680: 4413 add r3, r2
|
|
8004682: 00db lsls r3, r3, #3
|
|
8004684: 440b add r3, r1
|
|
8004686: 3304 adds r3, #4
|
|
8004688: 683a ldr r2, [r7, #0]
|
|
800468a: 601a str r2, [r3, #0]
|
|
|
|
time_elapsed = linkTimer(timer_id);
|
|
800468c: 79fb ldrb r3, [r7, #7]
|
|
800468e: 4618 mov r0, r3
|
|
8004690: f7ff fb30 bl 8003cf4 <linkTimer>
|
|
8004694: 4603 mov r3, r0
|
|
8004696: 827b strh r3, [r7, #18]
|
|
|
|
localcurrentrunningtimerid = CurrentRunningTimerID;
|
|
8004698: 4b1a ldr r3, [pc, #104] @ (8004704 <HW_TS_Start+0x104>)
|
|
800469a: 781b ldrb r3, [r3, #0]
|
|
800469c: 747b strb r3, [r7, #17]
|
|
|
|
if(PreviousRunningTimerID != localcurrentrunningtimerid)
|
|
800469e: 4b1a ldr r3, [pc, #104] @ (8004708 <HW_TS_Start+0x108>)
|
|
80046a0: 781b ldrb r3, [r3, #0]
|
|
80046a2: b2db uxtb r3, r3
|
|
80046a4: 7c7a ldrb r2, [r7, #17]
|
|
80046a6: 429a cmp r2, r3
|
|
80046a8: d002 beq.n 80046b0 <HW_TS_Start+0xb0>
|
|
{
|
|
RescheduleTimerList();
|
|
80046aa: f7ff fce9 bl 8004080 <RescheduleTimerList>
|
|
80046ae: e013 b.n 80046d8 <HW_TS_Start+0xd8>
|
|
}
|
|
else
|
|
{
|
|
aTimerContext[timer_id].CountLeft -= time_elapsed;
|
|
80046b0: 79fa ldrb r2, [r7, #7]
|
|
80046b2: 4912 ldr r1, [pc, #72] @ (80046fc <HW_TS_Start+0xfc>)
|
|
80046b4: 4613 mov r3, r2
|
|
80046b6: 005b lsls r3, r3, #1
|
|
80046b8: 4413 add r3, r2
|
|
80046ba: 00db lsls r3, r3, #3
|
|
80046bc: 440b add r3, r1
|
|
80046be: 3308 adds r3, #8
|
|
80046c0: 6819 ldr r1, [r3, #0]
|
|
80046c2: 8a7b ldrh r3, [r7, #18]
|
|
80046c4: 79fa ldrb r2, [r7, #7]
|
|
80046c6: 1ac9 subs r1, r1, r3
|
|
80046c8: 480c ldr r0, [pc, #48] @ (80046fc <HW_TS_Start+0xfc>)
|
|
80046ca: 4613 mov r3, r2
|
|
80046cc: 005b lsls r3, r3, #1
|
|
80046ce: 4413 add r3, r2
|
|
80046d0: 00db lsls r3, r3, #3
|
|
80046d2: 4403 add r3, r0
|
|
80046d4: 3308 adds r3, #8
|
|
80046d6: 6019 str r1, [r3, #0]
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
|
|
80046d8: 4b09 ldr r3, [pc, #36] @ (8004700 <HW_TS_Start+0x100>)
|
|
80046da: 681b ldr r3, [r3, #0]
|
|
80046dc: 22ff movs r2, #255 @ 0xff
|
|
80046de: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
|
|
80046e0: 2003 movs r0, #3
|
|
80046e2: f002 fa8d bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
80046e6: 697b ldr r3, [r7, #20]
|
|
80046e8: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80046ea: 68bb ldr r3, [r7, #8]
|
|
80046ec: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80046f0: bf00 nop
|
|
|
|
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
#endif
|
|
|
|
return;
|
|
80046f2: bf00 nop
|
|
}
|
|
80046f4: 3718 adds r7, #24
|
|
80046f6: 46bd mov sp, r7
|
|
80046f8: bd80 pop {r7, pc}
|
|
80046fa: bf00 nop
|
|
80046fc: 20000314 .word 0x20000314
|
|
8004700: 20000504 .word 0x20000504
|
|
8004704: 200003a4 .word 0x200003a4
|
|
8004708: 200003a5 .word 0x200003a5
|
|
|
|
0800470c <HW_TS_RTC_Int_AppNot>:
|
|
|
|
return (return_value);
|
|
}
|
|
|
|
__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
|
|
{
|
|
800470c: b580 push {r7, lr}
|
|
800470e: b084 sub sp, #16
|
|
8004710: af00 add r7, sp, #0
|
|
8004712: 60f8 str r0, [r7, #12]
|
|
8004714: 460b mov r3, r1
|
|
8004716: 607a str r2, [r7, #4]
|
|
8004718: 72fb strb r3, [r7, #11]
|
|
pTimerCallBack();
|
|
800471a: 687b ldr r3, [r7, #4]
|
|
800471c: 4798 blx r3
|
|
|
|
return;
|
|
800471e: bf00 nop
|
|
}
|
|
8004720: 3710 adds r7, #16
|
|
8004722: 46bd mov sp, r7
|
|
8004724: bd80 pop {r7, pc}
|
|
|
|
08004726 <ITM_SendChar>:
|
|
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
|
|
\param [in] ch Character to transmit.
|
|
\returns Character to transmit.
|
|
*/
|
|
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
|
{
|
|
8004726: b480 push {r7}
|
|
8004728: b083 sub sp, #12
|
|
800472a: af00 add r7, sp, #0
|
|
800472c: 6078 str r0, [r7, #4]
|
|
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
|
800472e: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
|
|
8004732: f8d3 3e80 ldr.w r3, [r3, #3712] @ 0xe80
|
|
8004736: f003 0301 and.w r3, r3, #1
|
|
800473a: 2b00 cmp r3, #0
|
|
800473c: d013 beq.n 8004766 <ITM_SendChar+0x40>
|
|
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
|
|
800473e: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
|
|
8004742: f8d3 3e00 ldr.w r3, [r3, #3584] @ 0xe00
|
|
8004746: f003 0301 and.w r3, r3, #1
|
|
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
|
800474a: 2b00 cmp r3, #0
|
|
800474c: d00b beq.n 8004766 <ITM_SendChar+0x40>
|
|
{
|
|
while (ITM->PORT[0U].u32 == 0UL)
|
|
800474e: e000 b.n 8004752 <ITM_SendChar+0x2c>
|
|
{
|
|
__NOP();
|
|
8004750: bf00 nop
|
|
while (ITM->PORT[0U].u32 == 0UL)
|
|
8004752: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
|
|
8004756: 681b ldr r3, [r3, #0]
|
|
8004758: 2b00 cmp r3, #0
|
|
800475a: d0f9 beq.n 8004750 <ITM_SendChar+0x2a>
|
|
}
|
|
ITM->PORT[0U].u8 = (uint8_t)ch;
|
|
800475c: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
|
|
8004760: 687a ldr r2, [r7, #4]
|
|
8004762: b2d2 uxtb r2, r2
|
|
8004764: 701a strb r2, [r3, #0]
|
|
}
|
|
return (ch);
|
|
8004766: 687b ldr r3, [r7, #4]
|
|
}
|
|
8004768: 4618 mov r0, r3
|
|
800476a: 370c adds r7, #12
|
|
800476c: 46bd mov sp, r7
|
|
800476e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004772: 4770 bx lr
|
|
|
|
08004774 <LL_RCC_LSE_SetDriveCapability>:
|
|
{
|
|
8004774: b480 push {r7}
|
|
8004776: b083 sub sp, #12
|
|
8004778: af00 add r7, sp, #0
|
|
800477a: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
|
|
800477c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8004780: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004784: f023 0218 bic.w r2, r3, #24
|
|
8004788: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800478c: 687b ldr r3, [r7, #4]
|
|
800478e: 4313 orrs r3, r2
|
|
8004790: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
}
|
|
8004794: bf00 nop
|
|
8004796: 370c adds r7, #12
|
|
8004798: 46bd mov sp, r7
|
|
800479a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800479e: 4770 bx lr
|
|
|
|
080047a0 <LL_AHB1_GRP1_EnableClock>:
|
|
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
|
|
* @note (*) Not supported by all the devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
80047a0: b480 push {r7}
|
|
80047a2: b085 sub sp, #20
|
|
80047a4: af00 add r7, sp, #0
|
|
80047a6: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->AHB1ENR, Periphs);
|
|
80047a8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80047ac: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
80047ae: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80047b2: 687b ldr r3, [r7, #4]
|
|
80047b4: 4313 orrs r3, r2
|
|
80047b6: 648b str r3, [r1, #72] @ 0x48
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
|
|
80047b8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80047bc: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
80047be: 687b ldr r3, [r7, #4]
|
|
80047c0: 4013 ands r3, r2
|
|
80047c2: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
80047c4: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80047c6: bf00 nop
|
|
80047c8: 3714 adds r7, #20
|
|
80047ca: 46bd mov sp, r7
|
|
80047cc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80047d0: 4770 bx lr
|
|
|
|
080047d2 <LL_AHB2_GRP1_EnableClock>:
|
|
* @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
|
|
* @note (*) Not supported by all the devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
80047d2: b480 push {r7}
|
|
80047d4: b085 sub sp, #20
|
|
80047d6: af00 add r7, sp, #0
|
|
80047d8: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->AHB2ENR, Periphs);
|
|
80047da: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80047de: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
80047e0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80047e4: 687b ldr r3, [r7, #4]
|
|
80047e6: 4313 orrs r3, r2
|
|
80047e8: 64cb str r3, [r1, #76] @ 0x4c
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
|
|
80047ea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80047ee: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
80047f0: 687b ldr r3, [r7, #4]
|
|
80047f2: 4013 ands r3, r2
|
|
80047f4: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
80047f6: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80047f8: bf00 nop
|
|
80047fa: 3714 adds r7, #20
|
|
80047fc: 46bd mov sp, r7
|
|
80047fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004802: 4770 bx lr
|
|
|
|
08004804 <LL_HSEM_1StepLock>:
|
|
* @param HSEMx HSEM Instance.
|
|
* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
|
|
* @retval 1 lock fail, 0 lock successful or already locked by same core
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
|
|
{
|
|
8004804: b480 push {r7}
|
|
8004806: b083 sub sp, #12
|
|
8004808: af00 add r7, sp, #0
|
|
800480a: 6078 str r0, [r7, #4]
|
|
800480c: 6039 str r1, [r7, #0]
|
|
return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
|
|
800480e: 687b ldr r3, [r7, #4]
|
|
8004810: 683a ldr r2, [r7, #0]
|
|
8004812: 3220 adds r2, #32
|
|
8004814: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8004818: 4a05 ldr r2, [pc, #20] @ (8004830 <LL_HSEM_1StepLock+0x2c>)
|
|
800481a: 4293 cmp r3, r2
|
|
800481c: d001 beq.n 8004822 <LL_HSEM_1StepLock+0x1e>
|
|
800481e: 2301 movs r3, #1
|
|
8004820: e000 b.n 8004824 <LL_HSEM_1StepLock+0x20>
|
|
8004822: 2300 movs r3, #0
|
|
}
|
|
8004824: 4618 mov r0, r3
|
|
8004826: 370c adds r7, #12
|
|
8004828: 46bd mov sp, r7
|
|
800482a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800482e: 4770 bx lr
|
|
8004830: 80000400 .word 0x80000400
|
|
|
|
08004834 <_write>:
|
|
|
|
/* Private user code ---------------------------------------------------------*/
|
|
/* USER CODE BEGIN 0 */
|
|
|
|
// implementation of printf() functionality through ITM
|
|
int _write(int file, char *prt, int len) {
|
|
8004834: b580 push {r7, lr}
|
|
8004836: b086 sub sp, #24
|
|
8004838: af00 add r7, sp, #0
|
|
800483a: 60f8 str r0, [r7, #12]
|
|
800483c: 60b9 str r1, [r7, #8]
|
|
800483e: 607a str r2, [r7, #4]
|
|
for (int i = 0; i < len; i++) {
|
|
8004840: 2300 movs r3, #0
|
|
8004842: 617b str r3, [r7, #20]
|
|
8004844: e009 b.n 800485a <_write+0x26>
|
|
ITM_SendChar(*prt++);
|
|
8004846: 68bb ldr r3, [r7, #8]
|
|
8004848: 1c5a adds r2, r3, #1
|
|
800484a: 60ba str r2, [r7, #8]
|
|
800484c: 781b ldrb r3, [r3, #0]
|
|
800484e: 4618 mov r0, r3
|
|
8004850: f7ff ff69 bl 8004726 <ITM_SendChar>
|
|
for (int i = 0; i < len; i++) {
|
|
8004854: 697b ldr r3, [r7, #20]
|
|
8004856: 3301 adds r3, #1
|
|
8004858: 617b str r3, [r7, #20]
|
|
800485a: 697a ldr r2, [r7, #20]
|
|
800485c: 687b ldr r3, [r7, #4]
|
|
800485e: 429a cmp r2, r3
|
|
8004860: dbf1 blt.n 8004846 <_write+0x12>
|
|
}
|
|
return len;
|
|
8004862: 687b ldr r3, [r7, #4]
|
|
}
|
|
8004864: 4618 mov r0, r3
|
|
8004866: 3718 adds r7, #24
|
|
8004868: 46bd mov sp, r7
|
|
800486a: bd80 pop {r7, pc}
|
|
|
|
0800486c <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
800486c: b580 push {r7, lr}
|
|
800486e: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8004870: f002 f848 bl 8006904 <HAL_Init>
|
|
/* Config code for STM32_WPAN (HSE Tuning must be done before system clock configuration) */
|
|
MX_APPE_Config();
|
|
8004874: f7fd fd78 bl 8002368 <MX_APPE_Config>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8004878: f000 f86a bl 8004950 <SystemClock_Config>
|
|
|
|
/* Configure the peripherals common clocks */
|
|
PeriphCommonClock_Config();
|
|
800487c: f000 f8de bl 8004a3c <PeriphCommonClock_Config>
|
|
|
|
/* IPCC initialisation */
|
|
MX_IPCC_Init();
|
|
8004880: f000 f93c bl 8004afc <MX_IPCC_Init>
|
|
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
// Initialize DWT for the BMM350 delay function to work properly
|
|
bmm_init_DWT();
|
|
8004884: f001 fa0c bl 8005ca0 <bmm_init_DWT>
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8004888: f000 fa9e bl 8004dc8 <MX_GPIO_Init>
|
|
MX_DMA_Init();
|
|
800488c: f000 fa72 bl 8004d74 <MX_DMA_Init>
|
|
MX_I2C1_Init();
|
|
8004890: f000 f8f4 bl 8004a7c <MX_I2C1_Init>
|
|
MX_SPI1_Init();
|
|
8004894: f000 f982 bl 8004b9c <MX_SPI1_Init>
|
|
MX_SPI2_Init();
|
|
8004898: f000 f9be bl 8004c18 <MX_SPI2_Init>
|
|
MX_TIM2_Init();
|
|
800489c: f000 f9fa bl 8004c94 <MX_TIM2_Init>
|
|
MX_RTC_Init();
|
|
80048a0: f000 f948 bl 8004b34 <MX_RTC_Init>
|
|
MX_RF_Init();
|
|
80048a4: f000 f93e bl 8004b24 <MX_RF_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
/* USER CODE END 2 */
|
|
|
|
/* Init scheduler */
|
|
osKernelInitialize();
|
|
80048a8: f00f f814 bl 80138d4 <osKernelInitialize>
|
|
/* start timers, add new ones, ... */
|
|
/* USER CODE END RTOS_TIMERS */
|
|
|
|
/* Create the queue(s) */
|
|
/* creation of Q_ICM */
|
|
Q_ICMHandle = osMessageQueueNew (1, sizeof(ICM45686_Data), &Q_ICM_attributes);
|
|
80048ac: 4a1a ldr r2, [pc, #104] @ (8004918 <main+0xac>)
|
|
80048ae: 211c movs r1, #28
|
|
80048b0: 2001 movs r0, #1
|
|
80048b2: f00f fbfb bl 80140ac <osMessageQueueNew>
|
|
80048b6: 4603 mov r3, r0
|
|
80048b8: 4a18 ldr r2, [pc, #96] @ (800491c <main+0xb0>)
|
|
80048ba: 6013 str r3, [r2, #0]
|
|
|
|
/* creation of Q_BMM */
|
|
Q_BMMHandle = osMessageQueueNew (1, sizeof(struct bmm350_mag_temp_data), &Q_BMM_attributes);
|
|
80048bc: 4a18 ldr r2, [pc, #96] @ (8004920 <main+0xb4>)
|
|
80048be: 2110 movs r1, #16
|
|
80048c0: 2001 movs r0, #1
|
|
80048c2: f00f fbf3 bl 80140ac <osMessageQueueNew>
|
|
80048c6: 4603 mov r3, r0
|
|
80048c8: 4a16 ldr r2, [pc, #88] @ (8004924 <main+0xb8>)
|
|
80048ca: 6013 str r3, [r2, #0]
|
|
/* add queues, ... */
|
|
/* USER CODE END RTOS_QUEUES */
|
|
|
|
/* Create the thread(s) */
|
|
/* creation of Task_DataAnalys */
|
|
Task_DataAnalysHandle = osThreadNew(Start_DataAnalysis, NULL, &Task_DataAnalys_attributes);
|
|
80048cc: 4a16 ldr r2, [pc, #88] @ (8004928 <main+0xbc>)
|
|
80048ce: 2100 movs r1, #0
|
|
80048d0: 4816 ldr r0, [pc, #88] @ (800492c <main+0xc0>)
|
|
80048d2: f00f f84f bl 8013974 <osThreadNew>
|
|
80048d6: 4603 mov r3, r0
|
|
80048d8: 4a15 ldr r2, [pc, #84] @ (8004930 <main+0xc4>)
|
|
80048da: 6013 str r3, [r2, #0]
|
|
|
|
/* creation of Task_ICM45686 */
|
|
Task_ICM45686Handle = osThreadNew(Start_ICM45686, NULL, &Task_ICM45686_attributes);
|
|
80048dc: 4a15 ldr r2, [pc, #84] @ (8004934 <main+0xc8>)
|
|
80048de: 2100 movs r1, #0
|
|
80048e0: 4815 ldr r0, [pc, #84] @ (8004938 <main+0xcc>)
|
|
80048e2: f00f f847 bl 8013974 <osThreadNew>
|
|
80048e6: 4603 mov r3, r0
|
|
80048e8: 4a14 ldr r2, [pc, #80] @ (800493c <main+0xd0>)
|
|
80048ea: 6013 str r3, [r2, #0]
|
|
|
|
/* creation of Task_BMM350 */
|
|
Task_BMM350Handle = osThreadNew(Start_BMM350, NULL, &Task_BMM350_attributes);
|
|
80048ec: 4a14 ldr r2, [pc, #80] @ (8004940 <main+0xd4>)
|
|
80048ee: 2100 movs r1, #0
|
|
80048f0: 4814 ldr r0, [pc, #80] @ (8004944 <main+0xd8>)
|
|
80048f2: f00f f83f bl 8013974 <osThreadNew>
|
|
80048f6: 4603 mov r3, r0
|
|
80048f8: 4a13 ldr r2, [pc, #76] @ (8004948 <main+0xdc>)
|
|
80048fa: 6013 str r3, [r2, #0]
|
|
|
|
/* USER CODE BEGIN RTOS_EVENTS */
|
|
/* add events, ... */
|
|
/* USER CODE END RTOS_EVENTS */
|
|
|
|
while(LL_HSEM_1StepLock(HSEM, CFG_HW_CLK48_CONFIG_SEMID));
|
|
80048fc: bf00 nop
|
|
80048fe: 2105 movs r1, #5
|
|
8004900: 4812 ldr r0, [pc, #72] @ (800494c <main+0xe0>)
|
|
8004902: f7ff ff7f bl 8004804 <LL_HSEM_1StepLock>
|
|
8004906: 4603 mov r3, r0
|
|
8004908: 2b00 cmp r3, #0
|
|
800490a: d1f8 bne.n 80048fe <main+0x92>
|
|
|
|
/* Init code for STM32_WPAN */
|
|
MX_APPE_Init();
|
|
800490c: f7fd fd3a bl 8002384 <MX_APPE_Init>
|
|
|
|
/* Start scheduler */
|
|
osKernelStart();
|
|
8004910: f00f f806 bl 8013920 <osKernelStart>
|
|
|
|
/* We should never get here as control is now taken by the scheduler */
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
8004914: bf00 nop
|
|
8004916: e7fd b.n 8004914 <main+0xa8>
|
|
8004918: 0801e53c .word 0x0801e53c
|
|
800491c: 20000708 .word 0x20000708
|
|
8004920: 0801e554 .word 0x0801e554
|
|
8004924: 2000070c .word 0x2000070c
|
|
8004928: 0801e4d0 .word 0x0801e4d0
|
|
800492c: 08004e9d .word 0x08004e9d
|
|
8004930: 200006fc .word 0x200006fc
|
|
8004934: 0801e4f4 .word 0x0801e4f4
|
|
8004938: 08004f71 .word 0x08004f71
|
|
800493c: 20000700 .word 0x20000700
|
|
8004940: 0801e518 .word 0x0801e518
|
|
8004944: 08005295 .word 0x08005295
|
|
8004948: 20000704 .word 0x20000704
|
|
800494c: 58001400 .word 0x58001400
|
|
|
|
08004950 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8004950: b580 push {r7, lr}
|
|
8004952: b09a sub sp, #104 @ 0x68
|
|
8004954: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8004956: f107 0320 add.w r3, r7, #32
|
|
800495a: 2248 movs r2, #72 @ 0x48
|
|
800495c: 2100 movs r1, #0
|
|
800495e: 4618 mov r0, r3
|
|
8004960: f015 fcd0 bl 801a304 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8004964: 1d3b adds r3, r7, #4
|
|
8004966: 2200 movs r2, #0
|
|
8004968: 601a str r2, [r3, #0]
|
|
800496a: 605a str r2, [r3, #4]
|
|
800496c: 609a str r2, [r3, #8]
|
|
800496e: 60da str r2, [r3, #12]
|
|
8004970: 611a str r2, [r3, #16]
|
|
8004972: 615a str r2, [r3, #20]
|
|
8004974: 619a str r2, [r3, #24]
|
|
|
|
/** Configure LSE Drive Capability
|
|
*/
|
|
HAL_PWR_EnableBkUpAccess();
|
|
8004976: f006 fae3 bl 800af40 <HAL_PWR_EnableBkUpAccess>
|
|
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
|
|
800497a: 2010 movs r0, #16
|
|
800497c: f7ff fefa bl 8004774 <LL_RCC_LSE_SetDriveCapability>
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8004980: 4b2d ldr r3, [pc, #180] @ (8004a38 <SystemClock_Config+0xe8>)
|
|
8004982: 681b ldr r3, [r3, #0]
|
|
8004984: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8004988: 4a2b ldr r2, [pc, #172] @ (8004a38 <SystemClock_Config+0xe8>)
|
|
800498a: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800498e: 6013 str r3, [r2, #0]
|
|
8004990: 4b29 ldr r3, [pc, #164] @ (8004a38 <SystemClock_Config+0xe8>)
|
|
8004992: 681b ldr r3, [r3, #0]
|
|
8004994: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8004998: 603b str r3, [r7, #0]
|
|
800499a: 683b ldr r3, [r7, #0]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI1
|
|
800499c: 232f movs r3, #47 @ 0x2f
|
|
800499e: 623b str r3, [r7, #32]
|
|
|RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE
|
|
|RCC_OSCILLATORTYPE_MSI;
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
80049a0: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80049a4: 627b str r3, [r7, #36] @ 0x24
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
|
80049a6: 2301 movs r3, #1
|
|
80049a8: 62bb str r3, [r7, #40] @ 0x28
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
80049aa: f44f 7380 mov.w r3, #256 @ 0x100
|
|
80049ae: 62fb str r3, [r7, #44] @ 0x2c
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
|
80049b0: 2301 movs r3, #1
|
|
80049b2: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
80049b4: 2340 movs r3, #64 @ 0x40
|
|
80049b6: 633b str r3, [r7, #48] @ 0x30
|
|
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
|
80049b8: 2300 movs r3, #0
|
|
80049ba: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
|
80049bc: 2360 movs r3, #96 @ 0x60
|
|
80049be: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
|
80049c0: 2305 movs r3, #5
|
|
80049c2: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80049c4: 2302 movs r3, #2
|
|
80049c6: 64fb str r3, [r7, #76] @ 0x4c
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
|
80049c8: 2301 movs r3, #1
|
|
80049ca: 653b str r3, [r7, #80] @ 0x50
|
|
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
|
|
80049cc: 2300 movs r3, #0
|
|
80049ce: 657b str r3, [r7, #84] @ 0x54
|
|
RCC_OscInitStruct.PLL.PLLN = 32;
|
|
80049d0: 2320 movs r3, #32
|
|
80049d2: 65bb str r3, [r7, #88] @ 0x58
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
80049d4: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
80049d8: 65fb str r3, [r7, #92] @ 0x5c
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
80049da: f04f 5300 mov.w r3, #536870912 @ 0x20000000
|
|
80049de: 667b str r3, [r7, #100] @ 0x64
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
80049e0: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
80049e4: 663b str r3, [r7, #96] @ 0x60
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
80049e6: f107 0320 add.w r3, r7, #32
|
|
80049ea: 4618 mov r0, r3
|
|
80049ec: f006 fe58 bl 800b6a0 <HAL_RCC_OscConfig>
|
|
80049f0: 4603 mov r3, r0
|
|
80049f2: 2b00 cmp r3, #0
|
|
80049f4: d001 beq.n 80049fa <SystemClock_Config+0xaa>
|
|
{
|
|
Error_Handler();
|
|
80049f6: f000 fcbd bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
|
|
80049fa: 236f movs r3, #111 @ 0x6f
|
|
80049fc: 607b str r3, [r7, #4]
|
|
|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
80049fe: 2303 movs r3, #3
|
|
8004a00: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8004a02: 2300 movs r3, #0
|
|
8004a04: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8004a06: 2300 movs r3, #0
|
|
8004a08: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8004a0a: 2300 movs r3, #0
|
|
8004a0c: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
|
|
8004a0e: 2380 movs r3, #128 @ 0x80
|
|
8004a10: 61bb str r3, [r7, #24]
|
|
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
|
|
8004a12: 2300 movs r3, #0
|
|
8004a14: 61fb str r3, [r7, #28]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
|
8004a16: 1d3b adds r3, r7, #4
|
|
8004a18: 2103 movs r1, #3
|
|
8004a1a: 4618 mov r0, r3
|
|
8004a1c: f007 f9b4 bl 800bd88 <HAL_RCC_ClockConfig>
|
|
8004a20: 4603 mov r3, r0
|
|
8004a22: 2b00 cmp r3, #0
|
|
8004a24: d001 beq.n 8004a2a <SystemClock_Config+0xda>
|
|
{
|
|
Error_Handler();
|
|
8004a26: f000 fca5 bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
/** Enable MSI Auto calibration
|
|
*/
|
|
HAL_RCCEx_EnableMSIPLLMode();
|
|
8004a2a: f007 ff8b bl 800c944 <HAL_RCCEx_EnableMSIPLLMode>
|
|
}
|
|
8004a2e: bf00 nop
|
|
8004a30: 3768 adds r7, #104 @ 0x68
|
|
8004a32: 46bd mov sp, r7
|
|
8004a34: bd80 pop {r7, pc}
|
|
8004a36: bf00 nop
|
|
8004a38: 58000400 .word 0x58000400
|
|
|
|
08004a3c <PeriphCommonClock_Config>:
|
|
/**
|
|
* @brief Peripherals Common Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void PeriphCommonClock_Config(void)
|
|
{
|
|
8004a3c: b580 push {r7, lr}
|
|
8004a3e: b094 sub sp, #80 @ 0x50
|
|
8004a40: af00 add r7, sp, #0
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8004a42: 463b mov r3, r7
|
|
8004a44: 2250 movs r2, #80 @ 0x50
|
|
8004a46: 2100 movs r1, #0
|
|
8004a48: 4618 mov r0, r3
|
|
8004a4a: f015 fc5b bl 801a304 <memset>
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP;
|
|
8004a4e: f44f 5340 mov.w r3, #12288 @ 0x3000
|
|
8004a52: 603b str r3, [r7, #0]
|
|
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_HSE_DIV1024;
|
|
8004a54: f44f 4340 mov.w r3, #49152 @ 0xc000
|
|
8004a58: 647b str r3, [r7, #68] @ 0x44
|
|
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
|
|
8004a5a: 2300 movs r3, #0
|
|
8004a5c: 64bb str r3, [r7, #72] @ 0x48
|
|
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
|
|
8004a5e: 2310 movs r3, #16
|
|
8004a60: 64fb str r3, [r7, #76] @ 0x4c
|
|
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8004a62: 463b mov r3, r7
|
|
8004a64: 4618 mov r0, r3
|
|
8004a66: f007 fdf7 bl 800c658 <HAL_RCCEx_PeriphCLKConfig>
|
|
8004a6a: 4603 mov r3, r0
|
|
8004a6c: 2b00 cmp r3, #0
|
|
8004a6e: d001 beq.n 8004a74 <PeriphCommonClock_Config+0x38>
|
|
{
|
|
Error_Handler();
|
|
8004a70: f000 fc80 bl 8005374 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN Smps */
|
|
|
|
/* USER CODE END Smps */
|
|
}
|
|
8004a74: bf00 nop
|
|
8004a76: 3750 adds r7, #80 @ 0x50
|
|
8004a78: 46bd mov sp, r7
|
|
8004a7a: bd80 pop {r7, pc}
|
|
|
|
08004a7c <MX_I2C1_Init>:
|
|
* @brief I2C1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C1_Init(void)
|
|
{
|
|
8004a7c: b580 push {r7, lr}
|
|
8004a7e: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8004a80: 4b1b ldr r3, [pc, #108] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004a82: 4a1c ldr r2, [pc, #112] @ (8004af4 <MX_I2C1_Init+0x78>)
|
|
8004a84: 601a str r2, [r3, #0]
|
|
hi2c1.Init.Timing = 0x00C12166;
|
|
8004a86: 4b1a ldr r3, [pc, #104] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004a88: 4a1b ldr r2, [pc, #108] @ (8004af8 <MX_I2C1_Init+0x7c>)
|
|
8004a8a: 605a str r2, [r3, #4]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8004a8c: 4b18 ldr r3, [pc, #96] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004a8e: 2200 movs r2, #0
|
|
8004a90: 609a str r2, [r3, #8]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8004a92: 4b17 ldr r3, [pc, #92] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004a94: 2201 movs r2, #1
|
|
8004a96: 60da str r2, [r3, #12]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8004a98: 4b15 ldr r3, [pc, #84] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004a9a: 2200 movs r2, #0
|
|
8004a9c: 611a str r2, [r3, #16]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
8004a9e: 4b14 ldr r3, [pc, #80] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004aa0: 2200 movs r2, #0
|
|
8004aa2: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
8004aa4: 4b12 ldr r3, [pc, #72] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004aa6: 2200 movs r2, #0
|
|
8004aa8: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8004aaa: 4b11 ldr r3, [pc, #68] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004aac: 2200 movs r2, #0
|
|
8004aae: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8004ab0: 4b0f ldr r3, [pc, #60] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004ab2: 2200 movs r2, #0
|
|
8004ab4: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
8004ab6: 480e ldr r0, [pc, #56] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004ab8: f002 fdde bl 8007678 <HAL_I2C_Init>
|
|
8004abc: 4603 mov r3, r0
|
|
8004abe: 2b00 cmp r3, #0
|
|
8004ac0: d001 beq.n 8004ac6 <MX_I2C1_Init+0x4a>
|
|
{
|
|
Error_Handler();
|
|
8004ac2: f000 fc57 bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
8004ac6: 2100 movs r1, #0
|
|
8004ac8: 4809 ldr r0, [pc, #36] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004aca: f004 fbd9 bl 8009280 <HAL_I2CEx_ConfigAnalogFilter>
|
|
8004ace: 4603 mov r3, r0
|
|
8004ad0: 2b00 cmp r3, #0
|
|
8004ad2: d001 beq.n 8004ad8 <MX_I2C1_Init+0x5c>
|
|
{
|
|
Error_Handler();
|
|
8004ad4: f000 fc4e bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
|
|
8004ad8: 2100 movs r1, #0
|
|
8004ada: 4805 ldr r0, [pc, #20] @ (8004af0 <MX_I2C1_Init+0x74>)
|
|
8004adc: f004 fc1b bl 8009316 <HAL_I2CEx_ConfigDigitalFilter>
|
|
8004ae0: 4603 mov r3, r0
|
|
8004ae2: 2b00 cmp r3, #0
|
|
8004ae4: d001 beq.n 8004aea <MX_I2C1_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
8004ae6: f000 fc45 bl 8005374 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
8004aea: bf00 nop
|
|
8004aec: bd80 pop {r7, pc}
|
|
8004aee: bf00 nop
|
|
8004af0: 200003b4 .word 0x200003b4
|
|
8004af4: 40005400 .word 0x40005400
|
|
8004af8: 00c12166 .word 0x00c12166
|
|
|
|
08004afc <MX_IPCC_Init>:
|
|
* @brief IPCC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_IPCC_Init(void)
|
|
{
|
|
8004afc: b580 push {r7, lr}
|
|
8004afe: af00 add r7, sp, #0
|
|
/* USER CODE END IPCC_Init 0 */
|
|
|
|
/* USER CODE BEGIN IPCC_Init 1 */
|
|
|
|
/* USER CODE END IPCC_Init 1 */
|
|
hipcc.Instance = IPCC;
|
|
8004b00: 4b06 ldr r3, [pc, #24] @ (8004b1c <MX_IPCC_Init+0x20>)
|
|
8004b02: 4a07 ldr r2, [pc, #28] @ (8004b20 <MX_IPCC_Init+0x24>)
|
|
8004b04: 601a str r2, [r3, #0]
|
|
if (HAL_IPCC_Init(&hipcc) != HAL_OK)
|
|
8004b06: 4805 ldr r0, [pc, #20] @ (8004b1c <MX_IPCC_Init+0x20>)
|
|
8004b08: f004 fc52 bl 80093b0 <HAL_IPCC_Init>
|
|
8004b0c: 4603 mov r3, r0
|
|
8004b0e: 2b00 cmp r3, #0
|
|
8004b10: d001 beq.n 8004b16 <MX_IPCC_Init+0x1a>
|
|
{
|
|
Error_Handler();
|
|
8004b12: f000 fc2f bl 8005374 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN IPCC_Init 2 */
|
|
|
|
/* USER CODE END IPCC_Init 2 */
|
|
|
|
}
|
|
8004b16: bf00 nop
|
|
8004b18: bd80 pop {r7, pc}
|
|
8004b1a: bf00 nop
|
|
8004b1c: 200004c8 .word 0x200004c8
|
|
8004b20: 58000c00 .word 0x58000c00
|
|
|
|
08004b24 <MX_RF_Init>:
|
|
* @brief RF Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_RF_Init(void)
|
|
{
|
|
8004b24: b480 push {r7}
|
|
8004b26: af00 add r7, sp, #0
|
|
/* USER CODE END RF_Init 1 */
|
|
/* USER CODE BEGIN RF_Init 2 */
|
|
|
|
/* USER CODE END RF_Init 2 */
|
|
|
|
}
|
|
8004b28: bf00 nop
|
|
8004b2a: 46bd mov sp, r7
|
|
8004b2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b30: 4770 bx lr
|
|
...
|
|
|
|
08004b34 <MX_RTC_Init>:
|
|
* @brief RTC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_RTC_Init(void)
|
|
{
|
|
8004b34: b580 push {r7, lr}
|
|
8004b36: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END RTC_Init 1 */
|
|
|
|
/** Initialize RTC Only
|
|
*/
|
|
hrtc.Instance = RTC;
|
|
8004b38: 4b16 ldr r3, [pc, #88] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b3a: 4a17 ldr r2, [pc, #92] @ (8004b98 <MX_RTC_Init+0x64>)
|
|
8004b3c: 601a str r2, [r3, #0]
|
|
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
|
|
8004b3e: 4b15 ldr r3, [pc, #84] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b40: 2200 movs r2, #0
|
|
8004b42: 605a str r2, [r3, #4]
|
|
hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
|
|
8004b44: 4b13 ldr r3, [pc, #76] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b46: 220f movs r2, #15
|
|
8004b48: 609a str r2, [r3, #8]
|
|
hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
|
|
8004b4a: 4b12 ldr r3, [pc, #72] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b4c: f647 72ff movw r2, #32767 @ 0x7fff
|
|
8004b50: 60da str r2, [r3, #12]
|
|
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
|
|
8004b52: 4b10 ldr r3, [pc, #64] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b54: 2200 movs r2, #0
|
|
8004b56: 611a str r2, [r3, #16]
|
|
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
|
8004b58: 4b0e ldr r3, [pc, #56] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b5a: 2200 movs r2, #0
|
|
8004b5c: 619a str r2, [r3, #24]
|
|
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
|
8004b5e: 4b0d ldr r3, [pc, #52] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b60: 2200 movs r2, #0
|
|
8004b62: 61da str r2, [r3, #28]
|
|
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;
|
|
8004b64: 4b0b ldr r3, [pc, #44] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b66: 2200 movs r2, #0
|
|
8004b68: 615a str r2, [r3, #20]
|
|
if (HAL_RTC_Init(&hrtc) != HAL_OK)
|
|
8004b6a: 480a ldr r0, [pc, #40] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b6c: f008 f801 bl 800cb72 <HAL_RTC_Init>
|
|
8004b70: 4603 mov r3, r0
|
|
8004b72: 2b00 cmp r3, #0
|
|
8004b74: d001 beq.n 8004b7a <MX_RTC_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8004b76: f000 fbfd bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
/** Enable the WakeUp
|
|
*/
|
|
if (HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 0, RTC_WAKEUPCLOCK_RTCCLK_DIV16) != HAL_OK)
|
|
8004b7a: 2200 movs r2, #0
|
|
8004b7c: 2100 movs r1, #0
|
|
8004b7e: 4805 ldr r0, [pc, #20] @ (8004b94 <MX_RTC_Init+0x60>)
|
|
8004b80: f008 f904 bl 800cd8c <HAL_RTCEx_SetWakeUpTimer_IT>
|
|
8004b84: 4603 mov r3, r0
|
|
8004b86: 2b00 cmp r3, #0
|
|
8004b88: d001 beq.n 8004b8e <MX_RTC_Init+0x5a>
|
|
{
|
|
Error_Handler();
|
|
8004b8a: f000 fbf3 bl 8005374 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN RTC_Init 2 */
|
|
|
|
/* USER CODE END RTC_Init 2 */
|
|
|
|
}
|
|
8004b8e: bf00 nop
|
|
8004b90: bd80 pop {r7, pc}
|
|
8004b92: bf00 nop
|
|
8004b94: 20000504 .word 0x20000504
|
|
8004b98: 40002800 .word 0x40002800
|
|
|
|
08004b9c <MX_SPI1_Init>:
|
|
* @brief SPI1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_SPI1_Init(void)
|
|
{
|
|
8004b9c: b580 push {r7, lr}
|
|
8004b9e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN SPI1_Init 1 */
|
|
|
|
/* USER CODE END SPI1_Init 1 */
|
|
/* SPI1 parameter configuration*/
|
|
hspi1.Instance = SPI1;
|
|
8004ba0: 4b1b ldr r3, [pc, #108] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004ba2: 4a1c ldr r2, [pc, #112] @ (8004c14 <MX_SPI1_Init+0x78>)
|
|
8004ba4: 601a str r2, [r3, #0]
|
|
hspi1.Init.Mode = SPI_MODE_MASTER;
|
|
8004ba6: 4b1a ldr r3, [pc, #104] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004ba8: f44f 7282 mov.w r2, #260 @ 0x104
|
|
8004bac: 605a str r2, [r3, #4]
|
|
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
|
|
8004bae: 4b18 ldr r3, [pc, #96] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bb0: 2200 movs r2, #0
|
|
8004bb2: 609a str r2, [r3, #8]
|
|
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
|
|
8004bb4: 4b16 ldr r3, [pc, #88] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bb6: f44f 62e0 mov.w r2, #1792 @ 0x700
|
|
8004bba: 60da str r2, [r3, #12]
|
|
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
|
|
8004bbc: 4b14 ldr r3, [pc, #80] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bbe: 2202 movs r2, #2
|
|
8004bc0: 611a str r2, [r3, #16]
|
|
hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
|
|
8004bc2: 4b13 ldr r3, [pc, #76] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bc4: 2201 movs r2, #1
|
|
8004bc6: 615a str r2, [r3, #20]
|
|
hspi1.Init.NSS = SPI_NSS_SOFT;
|
|
8004bc8: 4b11 ldr r3, [pc, #68] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bca: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8004bce: 619a str r2, [r3, #24]
|
|
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
|
|
8004bd0: 4b0f ldr r3, [pc, #60] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bd2: 2218 movs r2, #24
|
|
8004bd4: 61da str r2, [r3, #28]
|
|
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
8004bd6: 4b0e ldr r3, [pc, #56] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bd8: 2200 movs r2, #0
|
|
8004bda: 621a str r2, [r3, #32]
|
|
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
8004bdc: 4b0c ldr r3, [pc, #48] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bde: 2200 movs r2, #0
|
|
8004be0: 625a str r2, [r3, #36] @ 0x24
|
|
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8004be2: 4b0b ldr r3, [pc, #44] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004be4: 2200 movs r2, #0
|
|
8004be6: 629a str r2, [r3, #40] @ 0x28
|
|
hspi1.Init.CRCPolynomial = 7;
|
|
8004be8: 4b09 ldr r3, [pc, #36] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bea: 2207 movs r2, #7
|
|
8004bec: 62da str r2, [r3, #44] @ 0x2c
|
|
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
|
|
8004bee: 4b08 ldr r3, [pc, #32] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bf0: 2200 movs r2, #0
|
|
8004bf2: 631a str r2, [r3, #48] @ 0x30
|
|
hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
|
|
8004bf4: 4b06 ldr r3, [pc, #24] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bf6: 2200 movs r2, #0
|
|
8004bf8: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_SPI_Init(&hspi1) != HAL_OK)
|
|
8004bfa: 4805 ldr r0, [pc, #20] @ (8004c10 <MX_SPI1_Init+0x74>)
|
|
8004bfc: f008 f992 bl 800cf24 <HAL_SPI_Init>
|
|
8004c00: 4603 mov r3, r0
|
|
8004c02: 2b00 cmp r3, #0
|
|
8004c04: d001 beq.n 8004c0a <MX_SPI1_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
8004c06: f000 fbb5 bl 8005374 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SPI1_Init 2 */
|
|
|
|
/* USER CODE END SPI1_Init 2 */
|
|
|
|
}
|
|
8004c0a: bf00 nop
|
|
8004c0c: bd80 pop {r7, pc}
|
|
8004c0e: bf00 nop
|
|
8004c10: 20000528 .word 0x20000528
|
|
8004c14: 40013000 .word 0x40013000
|
|
|
|
08004c18 <MX_SPI2_Init>:
|
|
* @brief SPI2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_SPI2_Init(void)
|
|
{
|
|
8004c18: b580 push {r7, lr}
|
|
8004c1a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN SPI2_Init 1 */
|
|
|
|
/* USER CODE END SPI2_Init 1 */
|
|
/* SPI2 parameter configuration*/
|
|
hspi2.Instance = SPI2;
|
|
8004c1c: 4b1b ldr r3, [pc, #108] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c1e: 4a1c ldr r2, [pc, #112] @ (8004c90 <MX_SPI2_Init+0x78>)
|
|
8004c20: 601a str r2, [r3, #0]
|
|
hspi2.Init.Mode = SPI_MODE_MASTER;
|
|
8004c22: 4b1a ldr r3, [pc, #104] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c24: f44f 7282 mov.w r2, #260 @ 0x104
|
|
8004c28: 605a str r2, [r3, #4]
|
|
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
|
|
8004c2a: 4b18 ldr r3, [pc, #96] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c2c: 2200 movs r2, #0
|
|
8004c2e: 609a str r2, [r3, #8]
|
|
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
|
|
8004c30: 4b16 ldr r3, [pc, #88] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c32: f44f 7240 mov.w r2, #768 @ 0x300
|
|
8004c36: 60da str r2, [r3, #12]
|
|
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
8004c38: 4b14 ldr r3, [pc, #80] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c3a: 2200 movs r2, #0
|
|
8004c3c: 611a str r2, [r3, #16]
|
|
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8004c3e: 4b13 ldr r3, [pc, #76] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c40: 2200 movs r2, #0
|
|
8004c42: 615a str r2, [r3, #20]
|
|
hspi2.Init.NSS = SPI_NSS_SOFT;
|
|
8004c44: 4b11 ldr r3, [pc, #68] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c46: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8004c4a: 619a str r2, [r3, #24]
|
|
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
8004c4c: 4b0f ldr r3, [pc, #60] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c4e: 2200 movs r2, #0
|
|
8004c50: 61da str r2, [r3, #28]
|
|
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
8004c52: 4b0e ldr r3, [pc, #56] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c54: 2200 movs r2, #0
|
|
8004c56: 621a str r2, [r3, #32]
|
|
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
8004c58: 4b0c ldr r3, [pc, #48] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c5a: 2200 movs r2, #0
|
|
8004c5c: 625a str r2, [r3, #36] @ 0x24
|
|
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8004c5e: 4b0b ldr r3, [pc, #44] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c60: 2200 movs r2, #0
|
|
8004c62: 629a str r2, [r3, #40] @ 0x28
|
|
hspi2.Init.CRCPolynomial = 7;
|
|
8004c64: 4b09 ldr r3, [pc, #36] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c66: 2207 movs r2, #7
|
|
8004c68: 62da str r2, [r3, #44] @ 0x2c
|
|
hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
|
|
8004c6a: 4b08 ldr r3, [pc, #32] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c6c: 2200 movs r2, #0
|
|
8004c6e: 631a str r2, [r3, #48] @ 0x30
|
|
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
|
8004c70: 4b06 ldr r3, [pc, #24] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c72: 2208 movs r2, #8
|
|
8004c74: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_SPI_Init(&hspi2) != HAL_OK)
|
|
8004c76: 4805 ldr r0, [pc, #20] @ (8004c8c <MX_SPI2_Init+0x74>)
|
|
8004c78: f008 f954 bl 800cf24 <HAL_SPI_Init>
|
|
8004c7c: 4603 mov r3, r0
|
|
8004c7e: 2b00 cmp r3, #0
|
|
8004c80: d001 beq.n 8004c86 <MX_SPI2_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
8004c82: f000 fb77 bl 8005374 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SPI2_Init 2 */
|
|
|
|
/* USER CODE END SPI2_Init 2 */
|
|
|
|
}
|
|
8004c86: bf00 nop
|
|
8004c88: bd80 pop {r7, pc}
|
|
8004c8a: bf00 nop
|
|
8004c8c: 2000058c .word 0x2000058c
|
|
8004c90: 40003800 .word 0x40003800
|
|
|
|
08004c94 <MX_TIM2_Init>:
|
|
* @brief TIM2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM2_Init(void)
|
|
{
|
|
8004c94: b580 push {r7, lr}
|
|
8004c96: b08a sub sp, #40 @ 0x28
|
|
8004c98: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8004c9a: f107 031c add.w r3, r7, #28
|
|
8004c9e: 2200 movs r2, #0
|
|
8004ca0: 601a str r2, [r3, #0]
|
|
8004ca2: 605a str r2, [r3, #4]
|
|
8004ca4: 609a str r2, [r3, #8]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8004ca6: 463b mov r3, r7
|
|
8004ca8: 2200 movs r2, #0
|
|
8004caa: 601a str r2, [r3, #0]
|
|
8004cac: 605a str r2, [r3, #4]
|
|
8004cae: 609a str r2, [r3, #8]
|
|
8004cb0: 60da str r2, [r3, #12]
|
|
8004cb2: 611a str r2, [r3, #16]
|
|
8004cb4: 615a str r2, [r3, #20]
|
|
8004cb6: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
8004cb8: 4b2d ldr r3, [pc, #180] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004cba: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
8004cbe: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 63;
|
|
8004cc0: 4b2b ldr r3, [pc, #172] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004cc2: 223f movs r2, #63 @ 0x3f
|
|
8004cc4: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8004cc6: 4b2a ldr r3, [pc, #168] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004cc8: 2200 movs r2, #0
|
|
8004cca: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 999;
|
|
8004ccc: 4b28 ldr r3, [pc, #160] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004cce: f240 32e7 movw r2, #999 @ 0x3e7
|
|
8004cd2: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8004cd4: 4b26 ldr r3, [pc, #152] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004cd6: 2200 movs r2, #0
|
|
8004cd8: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8004cda: 4b25 ldr r3, [pc, #148] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004cdc: 2200 movs r2, #0
|
|
8004cde: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
|
|
8004ce0: 4823 ldr r0, [pc, #140] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004ce2: f009 fc6b bl 800e5bc <HAL_TIM_PWM_Init>
|
|
8004ce6: 4603 mov r3, r0
|
|
8004ce8: 2b00 cmp r3, #0
|
|
8004cea: d001 beq.n 8004cf0 <MX_TIM2_Init+0x5c>
|
|
{
|
|
Error_Handler();
|
|
8004cec: f000 fb42 bl 8005374 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8004cf0: 2300 movs r3, #0
|
|
8004cf2: 61fb str r3, [r7, #28]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8004cf4: 2300 movs r3, #0
|
|
8004cf6: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
8004cf8: f107 031c add.w r3, r7, #28
|
|
8004cfc: 4619 mov r1, r3
|
|
8004cfe: 481c ldr r0, [pc, #112] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004d00: f00a f9e4 bl 800f0cc <HAL_TIMEx_MasterConfigSynchronization>
|
|
8004d04: 4603 mov r3, r0
|
|
8004d06: 2b00 cmp r3, #0
|
|
8004d08: d001 beq.n 8004d0e <MX_TIM2_Init+0x7a>
|
|
{
|
|
Error_Handler();
|
|
8004d0a: f000 fb33 bl 8005374 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
8004d0e: 2360 movs r3, #96 @ 0x60
|
|
8004d10: 603b str r3, [r7, #0]
|
|
sConfigOC.Pulse = 0;
|
|
8004d12: 2300 movs r3, #0
|
|
8004d14: 607b str r3, [r7, #4]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
8004d16: 2300 movs r3, #0
|
|
8004d18: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
8004d1a: 2300 movs r3, #0
|
|
8004d1c: 613b str r3, [r7, #16]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
8004d1e: 463b mov r3, r7
|
|
8004d20: 2200 movs r2, #0
|
|
8004d22: 4619 mov r1, r3
|
|
8004d24: 4812 ldr r0, [pc, #72] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004d26: f009 fda7 bl 800e878 <HAL_TIM_PWM_ConfigChannel>
|
|
8004d2a: 4603 mov r3, r0
|
|
8004d2c: 2b00 cmp r3, #0
|
|
8004d2e: d001 beq.n 8004d34 <MX_TIM2_Init+0xa0>
|
|
{
|
|
Error_Handler();
|
|
8004d30: f000 fb20 bl 8005374 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
|
|
8004d34: 463b mov r3, r7
|
|
8004d36: 2204 movs r2, #4
|
|
8004d38: 4619 mov r1, r3
|
|
8004d3a: 480d ldr r0, [pc, #52] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004d3c: f009 fd9c bl 800e878 <HAL_TIM_PWM_ConfigChannel>
|
|
8004d40: 4603 mov r3, r0
|
|
8004d42: 2b00 cmp r3, #0
|
|
8004d44: d001 beq.n 8004d4a <MX_TIM2_Init+0xb6>
|
|
{
|
|
Error_Handler();
|
|
8004d46: f000 fb15 bl 8005374 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
|
|
8004d4a: 463b mov r3, r7
|
|
8004d4c: 2208 movs r2, #8
|
|
8004d4e: 4619 mov r1, r3
|
|
8004d50: 4807 ldr r0, [pc, #28] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004d52: f009 fd91 bl 800e878 <HAL_TIM_PWM_ConfigChannel>
|
|
8004d56: 4603 mov r3, r0
|
|
8004d58: 2b00 cmp r3, #0
|
|
8004d5a: d001 beq.n 8004d60 <MX_TIM2_Init+0xcc>
|
|
{
|
|
Error_Handler();
|
|
8004d5c: f000 fb0a bl 8005374 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim2);
|
|
8004d60: 4803 ldr r0, [pc, #12] @ (8004d70 <MX_TIM2_Init+0xdc>)
|
|
8004d62: f001 fb59 bl 8006418 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8004d66: bf00 nop
|
|
8004d68: 3728 adds r7, #40 @ 0x28
|
|
8004d6a: 46bd mov sp, r7
|
|
8004d6c: bd80 pop {r7, pc}
|
|
8004d6e: bf00 nop
|
|
8004d70: 200006b0 .word 0x200006b0
|
|
|
|
08004d74 <MX_DMA_Init>:
|
|
|
|
/**
|
|
* Enable DMA controller clock
|
|
*/
|
|
static void MX_DMA_Init(void)
|
|
{
|
|
8004d74: b580 push {r7, lr}
|
|
8004d76: af00 add r7, sp, #0
|
|
|
|
/* DMA controller clock enable */
|
|
__HAL_RCC_DMAMUX1_CLK_ENABLE();
|
|
8004d78: 2004 movs r0, #4
|
|
8004d7a: f7ff fd11 bl 80047a0 <LL_AHB1_GRP1_EnableClock>
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8004d7e: 2001 movs r0, #1
|
|
8004d80: f7ff fd0e bl 80047a0 <LL_AHB1_GRP1_EnableClock>
|
|
|
|
/* DMA interrupt init */
|
|
/* DMA1_Channel1_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0);
|
|
8004d84: 2200 movs r2, #0
|
|
8004d86: 2105 movs r1, #5
|
|
8004d88: 200b movs r0, #11
|
|
8004d8a: f001 ff1f bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
|
|
8004d8e: 200b movs r0, #11
|
|
8004d90: f001 ff36 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Channel2_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 5, 0);
|
|
8004d94: 2200 movs r2, #0
|
|
8004d96: 2105 movs r1, #5
|
|
8004d98: 200c movs r0, #12
|
|
8004d9a: f001 ff17 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
|
|
8004d9e: 200c movs r0, #12
|
|
8004da0: f001 ff2e bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Channel3_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 5, 0);
|
|
8004da4: 2200 movs r2, #0
|
|
8004da6: 2105 movs r1, #5
|
|
8004da8: 200d movs r0, #13
|
|
8004daa: f001 ff0f bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
|
|
8004dae: 200d movs r0, #13
|
|
8004db0: f001 ff26 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
/* DMA1_Channel4_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 5, 0);
|
|
8004db4: 2200 movs r2, #0
|
|
8004db6: 2105 movs r1, #5
|
|
8004db8: 200e movs r0, #14
|
|
8004dba: f001 ff07 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
|
|
8004dbe: 200e movs r0, #14
|
|
8004dc0: f001 ff1e bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
8004dc4: bf00 nop
|
|
8004dc6: bd80 pop {r7, pc}
|
|
|
|
08004dc8 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8004dc8: b580 push {r7, lr}
|
|
8004dca: b086 sub sp, #24
|
|
8004dcc: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8004dce: 1d3b adds r3, r7, #4
|
|
8004dd0: 2200 movs r2, #0
|
|
8004dd2: 601a str r2, [r3, #0]
|
|
8004dd4: 605a str r2, [r3, #4]
|
|
8004dd6: 609a str r2, [r3, #8]
|
|
8004dd8: 60da str r2, [r3, #12]
|
|
8004dda: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8004ddc: 2004 movs r0, #4
|
|
8004dde: f7ff fcf8 bl 80047d2 <LL_AHB2_GRP1_EnableClock>
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8004de2: 2002 movs r0, #2
|
|
8004de4: f7ff fcf5 bl 80047d2 <LL_AHB2_GRP1_EnableClock>
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8004de8: 2001 movs r0, #1
|
|
8004dea: f7ff fcf2 bl 80047d2 <LL_AHB2_GRP1_EnableClock>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIO_SPI1_IMU_CS_GPIO_Port, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
|
|
8004dee: 2201 movs r2, #1
|
|
8004df0: 2108 movs r1, #8
|
|
8004df2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8004df6: f002 fbeb bl 80075d0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_SPI2_SD_CD_Pin|GPIO_SPI2_SD_CS_Pin, GPIO_PIN_SET);
|
|
8004dfa: 2201 movs r2, #1
|
|
8004dfc: 2160 movs r1, #96 @ 0x60
|
|
8004dfe: 4826 ldr r0, [pc, #152] @ (8004e98 <MX_GPIO_Init+0xd0>)
|
|
8004e00: f002 fbe6 bl 80075d0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIO_SD_LDO_EN_GPIO_Port, GPIO_SD_LDO_EN_Pin, GPIO_PIN_RESET);
|
|
8004e04: 2200 movs r2, #0
|
|
8004e06: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
8004e0a: 4823 ldr r0, [pc, #140] @ (8004e98 <MX_GPIO_Init+0xd0>)
|
|
8004e0c: f002 fbe0 bl 80075d0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin : GPIO_SPI1_IMU_CS_Pin */
|
|
GPIO_InitStruct.Pin = GPIO_SPI1_IMU_CS_Pin;
|
|
8004e10: 2308 movs r3, #8
|
|
8004e12: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8004e14: 2301 movs r3, #1
|
|
8004e16: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004e18: 2300 movs r3, #0
|
|
8004e1a: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004e1c: 2303 movs r3, #3
|
|
8004e1e: 613b str r3, [r7, #16]
|
|
HAL_GPIO_Init(GPIO_SPI1_IMU_CS_GPIO_Port, &GPIO_InitStruct);
|
|
8004e20: 1d3b adds r3, r7, #4
|
|
8004e22: 4619 mov r1, r3
|
|
8004e24: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8004e28: f002 fa62 bl 80072f0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : GPIO_SPI2_SD_CD_Pin GPIO_SPI2_SD_CS_Pin GPIO_SD_LDO_EN_Pin */
|
|
GPIO_InitStruct.Pin = GPIO_SPI2_SD_CD_Pin|GPIO_SPI2_SD_CS_Pin|GPIO_SD_LDO_EN_Pin;
|
|
8004e2c: f44f 5383 mov.w r3, #4192 @ 0x1060
|
|
8004e30: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8004e32: 2301 movs r3, #1
|
|
8004e34: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004e36: 2300 movs r3, #0
|
|
8004e38: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004e3a: 2303 movs r3, #3
|
|
8004e3c: 613b str r3, [r7, #16]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8004e3e: 1d3b adds r3, r7, #4
|
|
8004e40: 4619 mov r1, r3
|
|
8004e42: 4815 ldr r0, [pc, #84] @ (8004e98 <MX_GPIO_Init+0xd0>)
|
|
8004e44: f002 fa54 bl 80072f0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : GPIO_IMU_INT_Pin */
|
|
GPIO_InitStruct.Pin = GPIO_IMU_INT_Pin;
|
|
8004e48: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8004e4c: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
8004e4e: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
8004e52: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004e54: 2300 movs r3, #0
|
|
8004e56: 60fb str r3, [r7, #12]
|
|
HAL_GPIO_Init(GPIO_IMU_INT_GPIO_Port, &GPIO_InitStruct);
|
|
8004e58: 1d3b adds r3, r7, #4
|
|
8004e5a: 4619 mov r1, r3
|
|
8004e5c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8004e60: f002 fa46 bl 80072f0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : GPIO_MAGN_INT_Pin */
|
|
GPIO_InitStruct.Pin = GPIO_MAGN_INT_Pin;
|
|
8004e64: f44f 6300 mov.w r3, #2048 @ 0x800
|
|
8004e68: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
|
8004e6a: f44f 1388 mov.w r3, #1114112 @ 0x110000
|
|
8004e6e: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004e70: 2300 movs r3, #0
|
|
8004e72: 60fb str r3, [r7, #12]
|
|
HAL_GPIO_Init(GPIO_MAGN_INT_GPIO_Port, &GPIO_InitStruct);
|
|
8004e74: 1d3b adds r3, r7, #4
|
|
8004e76: 4619 mov r1, r3
|
|
8004e78: 4807 ldr r0, [pc, #28] @ (8004e98 <MX_GPIO_Init+0xd0>)
|
|
8004e7a: f002 fa39 bl 80072f0 <HAL_GPIO_Init>
|
|
|
|
/* EXTI interrupt init*/
|
|
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
|
|
8004e7e: 2200 movs r2, #0
|
|
8004e80: 2105 movs r1, #5
|
|
8004e82: 2028 movs r0, #40 @ 0x28
|
|
8004e84: f001 fea2 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
|
|
8004e88: 2028 movs r0, #40 @ 0x28
|
|
8004e8a: f001 feb9 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8004e8e: bf00 nop
|
|
8004e90: 3718 adds r7, #24
|
|
8004e92: 46bd mov sp, r7
|
|
8004e94: bd80 pop {r7, pc}
|
|
8004e96: bf00 nop
|
|
8004e98: 48000800 .word 0x48000800
|
|
|
|
08004e9c <Start_DataAnalysis>:
|
|
* @param argument: Not used
|
|
* @retval None
|
|
*/
|
|
/* USER CODE END Header_Start_DataAnalysis */
|
|
void Start_DataAnalysis(void *argument)
|
|
{
|
|
8004e9c: b580 push {r7, lr}
|
|
8004e9e: b092 sub sp, #72 @ 0x48
|
|
8004ea0: af00 add r7, sp, #0
|
|
8004ea2: 6078 str r0, [r7, #4]
|
|
/* init code for USB_Device */
|
|
MX_USB_Device_Init();
|
|
8004ea4: f013 fce8 bl 8018878 <MX_USB_Device_Init>
|
|
// char output_buffer[128];
|
|
ICM45686_Data imu_data;
|
|
struct bmm350_mag_temp_data magn_data;
|
|
// struct bmm350_raw_mag_data magn_data;
|
|
QuaternionData Quat_Dat;
|
|
Quat_Dat.StartByte = PACKET_START_BYTE;
|
|
8004ea8: 23de movs r3, #222 @ 0xde
|
|
8004eaa: 723b strb r3, [r7, #8]
|
|
Quat_Dat.SensorAddress = BMM350_I2C_ADSEL_SET_LOW;
|
|
8004eac: 2314 movs r3, #20
|
|
8004eae: 727b strb r3, [r7, #9]
|
|
Quat_Dat.EndByte = PACKET_END_BYTE;
|
|
8004eb0: 23ad movs r3, #173 @ 0xad
|
|
8004eb2: 76bb strb r3, [r7, #26]
|
|
|
|
MadgwickAHRS_init(&IMUQuat, 6400.0f, 0.00001f);
|
|
8004eb4: eddf 0a29 vldr s1, [pc, #164] @ 8004f5c <Start_DataAnalysis+0xc0>
|
|
8004eb8: ed9f 0a29 vldr s0, [pc, #164] @ 8004f60 <Start_DataAnalysis+0xc4>
|
|
8004ebc: 4829 ldr r0, [pc, #164] @ (8004f64 <Start_DataAnalysis+0xc8>)
|
|
8004ebe: f7fb fef1 bl 8000ca4 <MadgwickAHRS_init>
|
|
|
|
/* Infinite loop */
|
|
for(;;)
|
|
{
|
|
|
|
osMessageQueueGet(Q_BMMHandle, &magn_data, NULL, osWaitForever);
|
|
8004ec2: 4b29 ldr r3, [pc, #164] @ (8004f68 <Start_DataAnalysis+0xcc>)
|
|
8004ec4: 6818 ldr r0, [r3, #0]
|
|
8004ec6: f107 011c add.w r1, r7, #28
|
|
8004eca: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8004ece: 2200 movs r2, #0
|
|
8004ed0: f00f f9bc bl 801424c <osMessageQueueGet>
|
|
osMessageQueueGet(Q_ICMHandle, &imu_data, NULL, osWaitForever);
|
|
8004ed4: 4b25 ldr r3, [pc, #148] @ (8004f6c <Start_DataAnalysis+0xd0>)
|
|
8004ed6: 6818 ldr r0, [r3, #0]
|
|
8004ed8: f107 012c add.w r1, r7, #44 @ 0x2c
|
|
8004edc: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8004ee0: 2200 movs r2, #0
|
|
8004ee2: f00f f9b3 bl 801424c <osMessageQueueGet>
|
|
|
|
MadgwickAHRS_update(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz
|
|
8004ee6: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
8004eea: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
|
|
8004eee: edd7 6a10 vldr s13, [r7, #64] @ 0x40
|
|
8004ef2: ed97 6a0b vldr s12, [r7, #44] @ 0x2c
|
|
8004ef6: edd7 5a0c vldr s11, [r7, #48] @ 0x30
|
|
8004efa: ed97 5a0d vldr s10, [r7, #52] @ 0x34
|
|
8004efe: edd7 4a07 vldr s9, [r7, #28]
|
|
8004f02: edd7 3a08 vldr s7, [r7, #32]
|
|
8004f06: ed97 4a09 vldr s8, [r7, #36] @ 0x24
|
|
8004f0a: eeb0 3a64 vmov.f32 s6, s9
|
|
8004f0e: eef0 2a45 vmov.f32 s5, s10
|
|
8004f12: eeb0 2a65 vmov.f32 s4, s11
|
|
8004f16: eef0 1a46 vmov.f32 s3, s12
|
|
8004f1a: eeb0 1a66 vmov.f32 s2, s13
|
|
8004f1e: eef0 0a47 vmov.f32 s1, s14
|
|
8004f22: eeb0 0a67 vmov.f32 s0, s15
|
|
8004f26: 480f ldr r0, [pc, #60] @ (8004f64 <Start_DataAnalysis+0xc8>)
|
|
8004f28: f7fb fee0 bl 8000cec <MadgwickAHRS_update>
|
|
|
|
// MadgwickAHRS_update_IMU(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz
|
|
// imu_data.processed_imu_data[0], imu_data.processed_imu_data[1], imu_data.processed_imu_data[2]); // ax, ay, yz)
|
|
|
|
|
|
Quat_Dat.qw = IMUQuat.q[0];
|
|
8004f2c: 4b0d ldr r3, [pc, #52] @ (8004f64 <Start_DataAnalysis+0xc8>)
|
|
8004f2e: 681b ldr r3, [r3, #0]
|
|
8004f30: f8c7 300a str.w r3, [r7, #10]
|
|
Quat_Dat.qx = IMUQuat.q[1];
|
|
8004f34: 4b0b ldr r3, [pc, #44] @ (8004f64 <Start_DataAnalysis+0xc8>)
|
|
8004f36: 685b ldr r3, [r3, #4]
|
|
8004f38: f8c7 300e str.w r3, [r7, #14]
|
|
Quat_Dat.qy = IMUQuat.q[2];
|
|
8004f3c: 4b09 ldr r3, [pc, #36] @ (8004f64 <Start_DataAnalysis+0xc8>)
|
|
8004f3e: 689b ldr r3, [r3, #8]
|
|
8004f40: f8c7 3012 str.w r3, [r7, #18]
|
|
Quat_Dat.qz = IMUQuat.q[3];
|
|
8004f44: 4b07 ldr r3, [pc, #28] @ (8004f64 <Start_DataAnalysis+0xc8>)
|
|
8004f46: 68db ldr r3, [r3, #12]
|
|
8004f48: f8c7 3016 str.w r3, [r7, #22]
|
|
|
|
CDC_Transmit_FS((uint8_t*)&Quat_Dat, sizeof(Quat_Dat));
|
|
8004f4c: f107 0308 add.w r3, r7, #8
|
|
8004f50: 2113 movs r1, #19
|
|
8004f52: 4618 mov r0, r3
|
|
8004f54: f013 fd4e bl 80189f4 <CDC_Transmit_FS>
|
|
osMessageQueueGet(Q_BMMHandle, &magn_data, NULL, osWaitForever);
|
|
8004f58: bf00 nop
|
|
8004f5a: e7b2 b.n 8004ec2 <Start_DataAnalysis+0x26>
|
|
8004f5c: 3727c5ac .word 0x3727c5ac
|
|
8004f60: 45c80000 .word 0x45c80000
|
|
8004f64: 20000710 .word 0x20000710
|
|
8004f68: 2000070c .word 0x2000070c
|
|
8004f6c: 20000708 .word 0x20000708
|
|
|
|
08004f70 <Start_ICM45686>:
|
|
* @param argument: Not used
|
|
* @retval None
|
|
*/
|
|
/* USER CODE END Header_Start_ICM45686 */
|
|
void Start_ICM45686(void *argument)
|
|
{
|
|
8004f70: b580 push {r7, lr}
|
|
8004f72: b0a4 sub sp, #144 @ 0x90
|
|
8004f74: af00 add r7, sp, #0
|
|
8004f76: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN Start_ICM45686 */
|
|
HAL_StatusTypeDef status;
|
|
// char output_buffer[128];
|
|
xIMU_Task = osThreadGetId();
|
|
8004f78: f00e fd8e bl 8013a98 <osThreadGetId>
|
|
8004f7c: 4603 mov r3, r0
|
|
8004f7e: 4abd ldr r2, [pc, #756] @ (8005274 <Start_ICM45686+0x304>)
|
|
8004f80: 6013 str r3, [r2, #0]
|
|
uint8_t raw_imu_data[15];
|
|
int16_t imu_sensor_data[7];
|
|
ICM45686_Data processed_data;
|
|
|
|
ICM45686_HandleTypeDef imu;
|
|
imu.hspi = &hspi1;
|
|
8004f82: 4bbd ldr r3, [pc, #756] @ (8005278 <Start_ICM45686+0x308>)
|
|
8004f84: 61bb str r3, [r7, #24]
|
|
imu.GPIO_Port = GPIO_SPI1_IMU_CS_GPIO_Port;
|
|
8004f86: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
|
|
8004f8a: 61fb str r3, [r7, #28]
|
|
imu.GPIO_Pin = GPIO_SPI1_IMU_CS_Pin;
|
|
8004f8c: 2308 movs r3, #8
|
|
8004f8e: 843b strh r3, [r7, #32]
|
|
imu.acc_fs = ICM45686_ACC_FS_16G;
|
|
8004f90: 2310 movs r3, #16
|
|
8004f92: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
imu.acc_ssf = ICM45686_ACC_SSF[ICM45686_ACC_FS_16G >> 4];
|
|
8004f96: f04f 438a mov.w r3, #1157627904 @ 0x45000000
|
|
8004f9a: 62bb str r3, [r7, #40] @ 0x28
|
|
imu.gyro_fs = ICM45686_GYRO_FS_2000DPS;
|
|
8004f9c: 2310 movs r3, #16
|
|
8004f9e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
imu.gyro_ssf = ICM45686_GYRO_SSF[ICM45686_GYRO_FS_2000DPS >> 4];
|
|
8004fa2: 4bb6 ldr r3, [pc, #728] @ (800527c <Start_ICM45686+0x30c>)
|
|
8004fa4: 62fb str r3, [r7, #44] @ 0x2c
|
|
imu.odr = ICM45686_ODR_6_4kHz_LN ;
|
|
8004fa6: 2303 movs r3, #3
|
|
8004fa8: f887 3024 strb.w r3, [r7, #36] @ 0x24
|
|
|
|
uint8_t tx[15] = {0x00};
|
|
8004fac: f107 0308 add.w r3, r7, #8
|
|
8004fb0: 2200 movs r2, #0
|
|
8004fb2: 601a str r2, [r3, #0]
|
|
8004fb4: 605a str r2, [r3, #4]
|
|
8004fb6: 609a str r2, [r3, #8]
|
|
8004fb8: f8c3 200b str.w r2, [r3, #11]
|
|
tx[0] = 0x00 | 0x80;
|
|
8004fbc: 2380 movs r3, #128 @ 0x80
|
|
8004fbe: 723b strb r3, [r7, #8]
|
|
uint16_t tx_len = sizeof(tx);
|
|
8004fc0: 230f movs r3, #15
|
|
8004fc2: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
|
|
|
|
|
|
init_icm(&imu);
|
|
8004fc6: f107 0318 add.w r3, r7, #24
|
|
8004fca: 4618 mov r0, r3
|
|
8004fcc: f000 fb3e bl 800564c <init_icm>
|
|
configure_and_enable_int_icm(&imu);
|
|
8004fd0: f107 0318 add.w r3, r7, #24
|
|
8004fd4: 4618 mov r0, r3
|
|
8004fd6: f000 fdb9 bl 8005b4c <configure_and_enable_int_icm>
|
|
ulTaskNotifyTakeIndexed(ICM_NOTIFY_INT_DRDY, pdTRUE, 0);
|
|
8004fda: 2200 movs r2, #0
|
|
8004fdc: 2101 movs r1, #1
|
|
8004fde: 2000 movs r0, #0
|
|
8004fe0: f011 fda8 bl 8016b34 <ulTaskGenericNotifyTake>
|
|
ulTaskNotifyTakeIndexed(ICM_NOTIFY_DMA, pdTRUE, 0);
|
|
8004fe4: 2200 movs r2, #0
|
|
8004fe6: 2101 movs r1, #1
|
|
8004fe8: 2001 movs r0, #1
|
|
8004fea: f011 fda3 bl 8016b34 <ulTaskGenericNotifyTake>
|
|
calibrate_icm(&imu, 25000);
|
|
8004fee: f107 0318 add.w r3, r7, #24
|
|
8004ff2: f246 11a8 movw r1, #25000 @ 0x61a8
|
|
8004ff6: 4618 mov r0, r3
|
|
8004ff8: f000 fc16 bl 8005828 <calibrate_icm>
|
|
// if (status != HAL_OK) {
|
|
// printf("Reading IMU sensordata failed: %d\n", status);
|
|
// }
|
|
//// DEBUG ////
|
|
|
|
ulTaskNotifyTakeIndexed(ICM_NOTIFY_INT_DRDY, pdTRUE, portMAX_DELAY);
|
|
8004ffc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8005000: 2101 movs r1, #1
|
|
8005002: 2000 movs r0, #0
|
|
8005004: f011 fd96 bl 8016b34 <ulTaskGenericNotifyTake>
|
|
status = read_icm_dma(&imu, tx, raw_imu_data, tx_len);
|
|
8005008: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
|
|
800500c: f107 027c add.w r2, r7, #124 @ 0x7c
|
|
8005010: f107 0108 add.w r1, r7, #8
|
|
8005014: f107 0018 add.w r0, r7, #24
|
|
8005018: f000 fad5 bl 80055c6 <read_icm_dma>
|
|
800501c: 4603 mov r3, r0
|
|
800501e: f887 308d strb.w r3, [r7, #141] @ 0x8d
|
|
if (status != HAL_OK) {
|
|
8005022: f897 308d ldrb.w r3, [r7, #141] @ 0x8d
|
|
8005026: 2b00 cmp r3, #0
|
|
8005028: d005 beq.n 8005036 <Start_ICM45686+0xc6>
|
|
printf("Reading IMU sensordata failed: %d\n", status);
|
|
800502a: f897 308d ldrb.w r3, [r7, #141] @ 0x8d
|
|
800502e: 4619 mov r1, r3
|
|
8005030: 4893 ldr r0, [pc, #588] @ (8005280 <Start_ICM45686+0x310>)
|
|
8005032: f015 f8ef bl 801a214 <iprintf>
|
|
}
|
|
if (ulTaskNotifyTakeIndexed(ICM_NOTIFY_DMA, pdTRUE, pdMS_TO_TICKS(10)) > 0) {
|
|
8005036: 220a movs r2, #10
|
|
8005038: 2101 movs r1, #1
|
|
800503a: 2001 movs r0, #1
|
|
800503c: f011 fd7a bl 8016b34 <ulTaskGenericNotifyTake>
|
|
8005040: 4603 mov r3, r0
|
|
8005042: 2b00 cmp r3, #0
|
|
8005044: f000 8108 beq.w 8005258 <Start_ICM45686+0x2e8>
|
|
imu_sensor_data[0] = (int16_t)(raw_imu_data[1] << 8 | raw_imu_data[2]); // a_x
|
|
8005048: f897 307d ldrb.w r3, [r7, #125] @ 0x7d
|
|
800504c: b21b sxth r3, r3
|
|
800504e: 021b lsls r3, r3, #8
|
|
8005050: b21a sxth r2, r3
|
|
8005052: f897 307e ldrb.w r3, [r7, #126] @ 0x7e
|
|
8005056: b21b sxth r3, r3
|
|
8005058: 4313 orrs r3, r2
|
|
800505a: b21b sxth r3, r3
|
|
800505c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
imu_sensor_data[1] = (int16_t)(raw_imu_data[3] << 8 | raw_imu_data[4]); // a_y
|
|
8005060: f897 307f ldrb.w r3, [r7, #127] @ 0x7f
|
|
8005064: b21b sxth r3, r3
|
|
8005066: 021b lsls r3, r3, #8
|
|
8005068: b21a sxth r2, r3
|
|
800506a: f897 3080 ldrb.w r3, [r7, #128] @ 0x80
|
|
800506e: b21b sxth r3, r3
|
|
8005070: 4313 orrs r3, r2
|
|
8005072: b21b sxth r3, r3
|
|
8005074: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
imu_sensor_data[2] = (int16_t)(raw_imu_data[5] << 8 | raw_imu_data[6]); // a_z
|
|
8005078: f897 3081 ldrb.w r3, [r7, #129] @ 0x81
|
|
800507c: b21b sxth r3, r3
|
|
800507e: 021b lsls r3, r3, #8
|
|
8005080: b21a sxth r2, r3
|
|
8005082: f897 3082 ldrb.w r3, [r7, #130] @ 0x82
|
|
8005086: b21b sxth r3, r3
|
|
8005088: 4313 orrs r3, r2
|
|
800508a: b21b sxth r3, r3
|
|
800508c: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
|
|
imu_sensor_data[3] = (int16_t)(raw_imu_data[7] << 8 | raw_imu_data[8]); // g_x
|
|
8005090: f897 3083 ldrb.w r3, [r7, #131] @ 0x83
|
|
8005094: b21b sxth r3, r3
|
|
8005096: 021b lsls r3, r3, #8
|
|
8005098: b21a sxth r2, r3
|
|
800509a: f897 3084 ldrb.w r3, [r7, #132] @ 0x84
|
|
800509e: b21b sxth r3, r3
|
|
80050a0: 4313 orrs r3, r2
|
|
80050a2: b21b sxth r3, r3
|
|
80050a4: f8a7 3072 strh.w r3, [r7, #114] @ 0x72
|
|
imu_sensor_data[4] = (int16_t)(raw_imu_data[9] << 8 | raw_imu_data[10]); // g_y
|
|
80050a8: f897 3085 ldrb.w r3, [r7, #133] @ 0x85
|
|
80050ac: b21b sxth r3, r3
|
|
80050ae: 021b lsls r3, r3, #8
|
|
80050b0: b21a sxth r2, r3
|
|
80050b2: f897 3086 ldrb.w r3, [r7, #134] @ 0x86
|
|
80050b6: b21b sxth r3, r3
|
|
80050b8: 4313 orrs r3, r2
|
|
80050ba: b21b sxth r3, r3
|
|
80050bc: f8a7 3074 strh.w r3, [r7, #116] @ 0x74
|
|
imu_sensor_data[5] = (int16_t)(raw_imu_data[11] << 8 | raw_imu_data[12]); // g_z
|
|
80050c0: f897 3087 ldrb.w r3, [r7, #135] @ 0x87
|
|
80050c4: b21b sxth r3, r3
|
|
80050c6: 021b lsls r3, r3, #8
|
|
80050c8: b21a sxth r2, r3
|
|
80050ca: f897 3088 ldrb.w r3, [r7, #136] @ 0x88
|
|
80050ce: b21b sxth r3, r3
|
|
80050d0: 4313 orrs r3, r2
|
|
80050d2: b21b sxth r3, r3
|
|
80050d4: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
imu_sensor_data[6] = (int16_t)(raw_imu_data[13] << 8 | raw_imu_data[14]); // t
|
|
80050d8: f897 3089 ldrb.w r3, [r7, #137] @ 0x89
|
|
80050dc: b21b sxth r3, r3
|
|
80050de: 021b lsls r3, r3, #8
|
|
80050e0: b21a sxth r2, r3
|
|
80050e2: f897 308a ldrb.w r3, [r7, #138] @ 0x8a
|
|
80050e6: b21b sxth r3, r3
|
|
80050e8: 4313 orrs r3, r2
|
|
80050ea: b21b sxth r3, r3
|
|
80050ec: f8a7 3078 strh.w r3, [r7, #120] @ 0x78
|
|
|
|
processed_data.processed_imu_data[0] = (float)imu_sensor_data[0] / (float)imu.acc_fs;
|
|
80050f0: f9b7 306c ldrsh.w r3, [r7, #108] @ 0x6c
|
|
80050f4: ee07 3a90 vmov s15, r3
|
|
80050f8: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
80050fc: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
|
|
8005100: ee07 3a90 vmov s15, r3
|
|
8005104: eeb8 7a67 vcvt.f32.u32 s14, s15
|
|
8005108: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
800510c: edc7 7a14 vstr s15, [r7, #80] @ 0x50
|
|
processed_data.processed_imu_data[1] = (float)imu_sensor_data[1] / (float)imu.acc_fs;
|
|
8005110: f9b7 306e ldrsh.w r3, [r7, #110] @ 0x6e
|
|
8005114: ee07 3a90 vmov s15, r3
|
|
8005118: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
800511c: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
|
|
8005120: ee07 3a90 vmov s15, r3
|
|
8005124: eeb8 7a67 vcvt.f32.u32 s14, s15
|
|
8005128: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
800512c: edc7 7a15 vstr s15, [r7, #84] @ 0x54
|
|
processed_data.processed_imu_data[2] = (float)imu_sensor_data[2] / (float)imu.acc_fs;
|
|
8005130: f9b7 3070 ldrsh.w r3, [r7, #112] @ 0x70
|
|
8005134: ee07 3a90 vmov s15, r3
|
|
8005138: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
800513c: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
|
|
8005140: ee07 3a90 vmov s15, r3
|
|
8005144: eeb8 7a67 vcvt.f32.u32 s14, s15
|
|
8005148: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
800514c: edc7 7a16 vstr s15, [r7, #88] @ 0x58
|
|
processed_data.processed_imu_data[3] = (float)imu_sensor_data[3] / (float)imu.gyro_ssf;
|
|
8005150: f9b7 3072 ldrsh.w r3, [r7, #114] @ 0x72
|
|
8005154: ee07 3a90 vmov s15, r3
|
|
8005158: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
800515c: ed97 7a0b vldr s14, [r7, #44] @ 0x2c
|
|
8005160: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8005164: edc7 7a17 vstr s15, [r7, #92] @ 0x5c
|
|
processed_data.processed_imu_data[4] = (float)imu_sensor_data[4] / (float)imu.gyro_ssf;
|
|
8005168: f9b7 3074 ldrsh.w r3, [r7, #116] @ 0x74
|
|
800516c: ee07 3a90 vmov s15, r3
|
|
8005170: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
8005174: ed97 7a0b vldr s14, [r7, #44] @ 0x2c
|
|
8005178: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
800517c: edc7 7a18 vstr s15, [r7, #96] @ 0x60
|
|
processed_data.processed_imu_data[5] = (float)imu_sensor_data[5] / (float)imu.gyro_ssf;
|
|
8005180: f9b7 3076 ldrsh.w r3, [r7, #118] @ 0x76
|
|
8005184: ee07 3a90 vmov s15, r3
|
|
8005188: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
800518c: ed97 7a0b vldr s14, [r7, #44] @ 0x2c
|
|
8005190: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8005194: edc7 7a19 vstr s15, [r7, #100] @ 0x64
|
|
processed_data.processed_imu_data[6] = (float)(imu_sensor_data[6] / 128.0 + 25.0);
|
|
8005198: f9b7 3078 ldrsh.w r3, [r7, #120] @ 0x78
|
|
800519c: 4618 mov r0, r3
|
|
800519e: f7fb f999 bl 80004d4 <__aeabi_i2d>
|
|
80051a2: f04f 0200 mov.w r2, #0
|
|
80051a6: 4b37 ldr r3, [pc, #220] @ (8005284 <Start_ICM45686+0x314>)
|
|
80051a8: f7fb fb28 bl 80007fc <__aeabi_ddiv>
|
|
80051ac: 4602 mov r2, r0
|
|
80051ae: 460b mov r3, r1
|
|
80051b0: 4610 mov r0, r2
|
|
80051b2: 4619 mov r1, r3
|
|
80051b4: f04f 0200 mov.w r2, #0
|
|
80051b8: 4b33 ldr r3, [pc, #204] @ (8005288 <Start_ICM45686+0x318>)
|
|
80051ba: f7fb f83f bl 800023c <__adddf3>
|
|
80051be: 4602 mov r2, r0
|
|
80051c0: 460b mov r3, r1
|
|
80051c2: 4610 mov r0, r2
|
|
80051c4: 4619 mov r1, r3
|
|
80051c6: f7fb fce7 bl 8000b98 <__aeabi_d2f>
|
|
80051ca: 4603 mov r3, r0
|
|
80051cc: 66bb str r3, [r7, #104] @ 0x68
|
|
|
|
if (imu.calibated) {
|
|
80051ce: f897 3030 ldrb.w r3, [r7, #48] @ 0x30
|
|
80051d2: 2b00 cmp r3, #0
|
|
80051d4: d037 beq.n 8005246 <Start_ICM45686+0x2d6>
|
|
processed_data.processed_imu_data[0] -= imu.imu_bias[0];
|
|
80051d6: ed97 7a14 vldr s14, [r7, #80] @ 0x50
|
|
80051da: edd7 7a0d vldr s15, [r7, #52] @ 0x34
|
|
80051de: ee77 7a67 vsub.f32 s15, s14, s15
|
|
80051e2: edc7 7a14 vstr s15, [r7, #80] @ 0x50
|
|
processed_data.processed_imu_data[1] -= imu.imu_bias[1];
|
|
80051e6: ed97 7a15 vldr s14, [r7, #84] @ 0x54
|
|
80051ea: edd7 7a0e vldr s15, [r7, #56] @ 0x38
|
|
80051ee: ee77 7a67 vsub.f32 s15, s14, s15
|
|
80051f2: edc7 7a15 vstr s15, [r7, #84] @ 0x54
|
|
processed_data.processed_imu_data[2] -= imu.imu_bias[2];
|
|
80051f6: ed97 7a16 vldr s14, [r7, #88] @ 0x58
|
|
80051fa: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
|
|
80051fe: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8005202: edc7 7a16 vstr s15, [r7, #88] @ 0x58
|
|
processed_data.processed_imu_data[3] -= imu.imu_bias[3];
|
|
8005206: ed97 7a17 vldr s14, [r7, #92] @ 0x5c
|
|
800520a: edd7 7a10 vldr s15, [r7, #64] @ 0x40
|
|
800520e: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8005212: edc7 7a17 vstr s15, [r7, #92] @ 0x5c
|
|
processed_data.processed_imu_data[4] -= imu.imu_bias[4];
|
|
8005216: ed97 7a18 vldr s14, [r7, #96] @ 0x60
|
|
800521a: edd7 7a11 vldr s15, [r7, #68] @ 0x44
|
|
800521e: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8005222: edc7 7a18 vstr s15, [r7, #96] @ 0x60
|
|
processed_data.processed_imu_data[5] -= imu.imu_bias[5];
|
|
8005226: ed97 7a19 vldr s14, [r7, #100] @ 0x64
|
|
800522a: edd7 7a12 vldr s15, [r7, #72] @ 0x48
|
|
800522e: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8005232: edc7 7a19 vstr s15, [r7, #100] @ 0x64
|
|
processed_data.processed_imu_data[6] -= imu.imu_bias[6];
|
|
8005236: ed97 7a1a vldr s14, [r7, #104] @ 0x68
|
|
800523a: edd7 7a13 vldr s15, [r7, #76] @ 0x4c
|
|
800523e: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8005242: edc7 7a1a vstr s15, [r7, #104] @ 0x68
|
|
}
|
|
osMessageQueuePut(Q_ICMHandle, &processed_data, 0, 5);
|
|
8005246: 4b11 ldr r3, [pc, #68] @ (800528c <Start_ICM45686+0x31c>)
|
|
8005248: 6818 ldr r0, [r3, #0]
|
|
800524a: f107 0150 add.w r1, r7, #80 @ 0x50
|
|
800524e: 2305 movs r3, #5
|
|
8005250: 2200 movs r2, #0
|
|
8005252: f00e ff9d bl 8014190 <osMessageQueuePut>
|
|
8005256: e6d1 b.n 8004ffc <Start_ICM45686+0x8c>
|
|
} else {
|
|
HAL_SPI_Abort(imu.hspi);
|
|
8005258: 69bb ldr r3, [r7, #24]
|
|
800525a: 4618 mov r0, r3
|
|
800525c: f008 fc20 bl 800daa0 <HAL_SPI_Abort>
|
|
HAL_GPIO_WritePin(imu.GPIO_Port, imu.GPIO_Pin, GPIO_PIN_SET);
|
|
8005260: 69fb ldr r3, [r7, #28]
|
|
8005262: 8c39 ldrh r1, [r7, #32]
|
|
8005264: 2201 movs r2, #1
|
|
8005266: 4618 mov r0, r3
|
|
8005268: f002 f9b2 bl 80075d0 <HAL_GPIO_WritePin>
|
|
printf("IMU DMA data transaction timed out");
|
|
800526c: 4808 ldr r0, [pc, #32] @ (8005290 <Start_ICM45686+0x320>)
|
|
800526e: f014 ffd1 bl 801a214 <iprintf>
|
|
ulTaskNotifyTakeIndexed(ICM_NOTIFY_INT_DRDY, pdTRUE, portMAX_DELAY);
|
|
8005272: e6c3 b.n 8004ffc <Start_ICM45686+0x8c>
|
|
8005274: 20000728 .word 0x20000728
|
|
8005278: 20000528 .word 0x20000528
|
|
800527c: 41833333 .word 0x41833333
|
|
8005280: 0801de88 .word 0x0801de88
|
|
8005284: 40600000 .word 0x40600000
|
|
8005288: 40390000 .word 0x40390000
|
|
800528c: 20000708 .word 0x20000708
|
|
8005290: 0801deac .word 0x0801deac
|
|
|
|
08005294 <Start_BMM350>:
|
|
* @param argument: Not used
|
|
* @retval None
|
|
*/
|
|
/* USER CODE END Header_Start_BMM350 */
|
|
void Start_BMM350(void *argument)
|
|
{
|
|
8005294: b580 push {r7, lr}
|
|
8005296: b0b4 sub sp, #208 @ 0xd0
|
|
8005298: af00 add r7, sp, #0
|
|
800529a: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN Start_BMM350 */
|
|
xMagn_Task = osThreadGetId();
|
|
800529c: f00e fbfc bl 8013a98 <osThreadGetId>
|
|
80052a0: 4603 mov r3, r0
|
|
80052a2: 4a27 ldr r2, [pc, #156] @ (8005340 <Start_BMM350+0xac>)
|
|
80052a4: 6013 str r3, [r2, #0]
|
|
struct bmm350_dev dev = {0x00};
|
|
80052a6: f107 031c add.w r3, r7, #28
|
|
80052aa: 22b0 movs r2, #176 @ 0xb0
|
|
80052ac: 2100 movs r1, #0
|
|
80052ae: 4618 mov r0, r3
|
|
80052b0: f015 f828 bl 801a304 <memset>
|
|
int8_t rslt;
|
|
struct bmm350_mag_temp_data mag_data;
|
|
|
|
// ODR: 200HZ, AVG:
|
|
rslt = init_bmm(&dev);
|
|
80052b4: f107 031c add.w r3, r7, #28
|
|
80052b8: 4618 mov r0, r3
|
|
80052ba: f000 fd93 bl 8005de4 <init_bmm>
|
|
80052be: 4603 mov r3, r0
|
|
80052c0: f887 30cf strb.w r3, [r7, #207] @ 0xcf
|
|
if (rslt != BMM350_OK) {
|
|
80052c4: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf
|
|
80052c8: 2b00 cmp r3, #0
|
|
80052ca: d005 beq.n 80052d8 <Start_BMM350+0x44>
|
|
printf("BMM350 initialization failed: %d\n", rslt);
|
|
80052cc: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf
|
|
80052d0: 4619 mov r1, r3
|
|
80052d2: 481c ldr r0, [pc, #112] @ (8005344 <Start_BMM350+0xb0>)
|
|
80052d4: f014 ff9e bl 801a214 <iprintf>
|
|
}
|
|
//
|
|
rslt = bmm_configure_interrupt(&dev);
|
|
80052d8: f107 031c add.w r3, r7, #28
|
|
80052dc: 4618 mov r0, r3
|
|
80052de: f000 fdd9 bl 8005e94 <bmm_configure_interrupt>
|
|
80052e2: 4603 mov r3, r0
|
|
80052e4: f887 30cf strb.w r3, [r7, #207] @ 0xcf
|
|
if (rslt != BMM350_OK) {
|
|
80052e8: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf
|
|
80052ec: 2b00 cmp r3, #0
|
|
80052ee: d005 beq.n 80052fc <Start_BMM350+0x68>
|
|
printf("Configuring interrupt failed: %d\n", rslt);
|
|
80052f0: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf
|
|
80052f4: 4619 mov r1, r3
|
|
80052f6: 4814 ldr r0, [pc, #80] @ (8005348 <Start_BMM350+0xb4>)
|
|
80052f8: f014 ff8c bl 801a214 <iprintf>
|
|
}
|
|
ulTaskNotifyTakeIndexed(BMM_NOTIFY_INT_DRDY, pdTRUE, 0);
|
|
80052fc: 2200 movs r2, #0
|
|
80052fe: 2101 movs r1, #1
|
|
8005300: 2000 movs r0, #0
|
|
8005302: f011 fc17 bl 8016b34 <ulTaskGenericNotifyTake>
|
|
ulTaskNotifyTakeIndexed(BMM_NOTIFY_DMA, pdTRUE, 0);
|
|
8005306: 2200 movs r2, #0
|
|
8005308: 2101 movs r1, #1
|
|
800530a: 2001 movs r0, #1
|
|
800530c: f011 fc12 bl 8016b34 <ulTaskGenericNotifyTake>
|
|
{
|
|
// wait for the interrupt
|
|
// ulTaskNotifyTake(pdFALSE, osWaitForever);
|
|
// ulTaskNotifyTakeIndexed(pdFALSE, BMM_NOTIFY_INT_DRDY, osWaitForever);
|
|
// ulTaskNotifyTakeIndexed(BMM_NOTIFY_INT_DRDY, pdTRUE, osWaitForever);
|
|
rslt = bmm350_get_compensated_mag_xyz_temp_data(&mag_data, &dev);
|
|
8005310: f107 021c add.w r2, r7, #28
|
|
8005314: f107 030c add.w r3, r7, #12
|
|
8005318: 4611 mov r1, r2
|
|
800531a: 4618 mov r0, r3
|
|
800531c: f7fd fd96 bl 8002e4c <bmm350_get_compensated_mag_xyz_temp_data>
|
|
8005320: 4603 mov r3, r0
|
|
8005322: f887 30cf strb.w r3, [r7, #207] @ 0xcf
|
|
// ulTaskNotifyTake(pdFALSE, osWaitForever);
|
|
// ulTaskNotifyTakeIndexed(BMM_NOTIFY_DMA, pdTRUE, osWaitForever);
|
|
if (rslt == BMM350_OK)
|
|
8005326: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf
|
|
800532a: 2b00 cmp r3, #0
|
|
800532c: d1f0 bne.n 8005310 <Start_BMM350+0x7c>
|
|
{
|
|
osMessageQueuePut(Q_BMMHandle, &mag_data, 0, 5);
|
|
800532e: 4b07 ldr r3, [pc, #28] @ (800534c <Start_BMM350+0xb8>)
|
|
8005330: 6818 ldr r0, [r3, #0]
|
|
8005332: f107 010c add.w r1, r7, #12
|
|
8005336: 2305 movs r3, #5
|
|
8005338: 2200 movs r2, #0
|
|
800533a: f00e ff29 bl 8014190 <osMessageQueuePut>
|
|
rslt = bmm350_get_compensated_mag_xyz_temp_data(&mag_data, &dev);
|
|
800533e: e7e7 b.n 8005310 <Start_BMM350+0x7c>
|
|
8005340: 2000072c .word 0x2000072c
|
|
8005344: 0801ded0 .word 0x0801ded0
|
|
8005348: 0801def4 .word 0x0801def4
|
|
800534c: 2000070c .word 0x2000070c
|
|
|
|
08005350 <HAL_TIM_PeriodElapsedCallback>:
|
|
* a global variable "uwTick" used as application time base.
|
|
* @param htim : TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005350: b580 push {r7, lr}
|
|
8005352: b082 sub sp, #8
|
|
8005354: af00 add r7, sp, #0
|
|
8005356: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN Callback 0 */
|
|
|
|
/* USER CODE END Callback 0 */
|
|
if (htim->Instance == TIM16)
|
|
8005358: 687b ldr r3, [r7, #4]
|
|
800535a: 681b ldr r3, [r3, #0]
|
|
800535c: 4a04 ldr r2, [pc, #16] @ (8005370 <HAL_TIM_PeriodElapsedCallback+0x20>)
|
|
800535e: 4293 cmp r3, r2
|
|
8005360: d101 bne.n 8005366 <HAL_TIM_PeriodElapsedCallback+0x16>
|
|
{
|
|
HAL_IncTick();
|
|
8005362: f001 faef bl 8006944 <HAL_IncTick>
|
|
}
|
|
/* USER CODE BEGIN Callback 1 */
|
|
|
|
/* USER CODE END Callback 1 */
|
|
}
|
|
8005366: bf00 nop
|
|
8005368: 3708 adds r7, #8
|
|
800536a: 46bd mov sp, r7
|
|
800536c: bd80 pop {r7, pc}
|
|
800536e: bf00 nop
|
|
8005370: 40014400 .word 0x40014400
|
|
|
|
08005374 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8005374: b480 push {r7}
|
|
8005376: af00 add r7, sp, #0
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8005378: b672 cpsid i
|
|
}
|
|
800537a: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
800537c: bf00 nop
|
|
800537e: e7fd b.n 800537c <Error_Handler+0x8>
|
|
|
|
08005380 <HAL_SPI_TxRxCpltCallback>:
|
|
volatile osThreadId_t xIMU_Task = NULL;
|
|
volatile osThreadId_t xMagn_Task = NULL;
|
|
//osThreadId_t xData_Task = NULL;
|
|
|
|
|
|
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) {
|
|
8005380: b580 push {r7, lr}
|
|
8005382: b084 sub sp, #16
|
|
8005384: af00 add r7, sp, #0
|
|
8005386: 6078 str r0, [r7, #4]
|
|
if (hspi->Instance == SPI1 && xIMU_Task != NULL) {
|
|
8005388: 687b ldr r3, [r7, #4]
|
|
800538a: 681b ldr r3, [r3, #0]
|
|
800538c: 4a12 ldr r2, [pc, #72] @ (80053d8 <HAL_SPI_TxRxCpltCallback+0x58>)
|
|
800538e: 4293 cmp r3, r2
|
|
8005390: d11e bne.n 80053d0 <HAL_SPI_TxRxCpltCallback+0x50>
|
|
8005392: 4b12 ldr r3, [pc, #72] @ (80053dc <HAL_SPI_TxRxCpltCallback+0x5c>)
|
|
8005394: 681b ldr r3, [r3, #0]
|
|
8005396: 2b00 cmp r3, #0
|
|
8005398: d01a beq.n 80053d0 <HAL_SPI_TxRxCpltCallback+0x50>
|
|
HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
|
|
800539a: 2201 movs r2, #1
|
|
800539c: 2108 movs r1, #8
|
|
800539e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80053a2: f002 f915 bl 80075d0 <HAL_GPIO_WritePin>
|
|
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
|
80053a6: 2300 movs r3, #0
|
|
80053a8: 60fb str r3, [r7, #12]
|
|
vTaskNotifyGiveIndexedFromISR(xIMU_Task, ICM_NOTIFY_DMA, &xHigherPriorityTaskWoken);
|
|
80053aa: 4b0c ldr r3, [pc, #48] @ (80053dc <HAL_SPI_TxRxCpltCallback+0x5c>)
|
|
80053ac: 681b ldr r3, [r3, #0]
|
|
80053ae: f107 020c add.w r2, r7, #12
|
|
80053b2: 2101 movs r1, #1
|
|
80053b4: 4618 mov r0, r3
|
|
80053b6: f011 ff2d bl 8017214 <vTaskGenericNotifyGiveFromISR>
|
|
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
|
80053ba: 68fb ldr r3, [r7, #12]
|
|
80053bc: 2b00 cmp r3, #0
|
|
80053be: d007 beq.n 80053d0 <HAL_SPI_TxRxCpltCallback+0x50>
|
|
80053c0: 4b07 ldr r3, [pc, #28] @ (80053e0 <HAL_SPI_TxRxCpltCallback+0x60>)
|
|
80053c2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80053c6: 601a str r2, [r3, #0]
|
|
80053c8: f3bf 8f4f dsb sy
|
|
80053cc: f3bf 8f6f isb sy
|
|
}
|
|
}
|
|
80053d0: bf00 nop
|
|
80053d2: 3710 adds r7, #16
|
|
80053d4: 46bd mov sp, r7
|
|
80053d6: bd80 pop {r7, pc}
|
|
80053d8: 40013000 .word 0x40013000
|
|
80053dc: 20000728 .word 0x20000728
|
|
80053e0: e000ed04 .word 0xe000ed04
|
|
|
|
080053e4 <HAL_I2C_MemRxCpltCallback>:
|
|
|
|
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *I2C_address) {
|
|
80053e4: b580 push {r7, lr}
|
|
80053e6: b084 sub sp, #16
|
|
80053e8: af00 add r7, sp, #0
|
|
80053ea: 6078 str r0, [r7, #4]
|
|
if (I2C_address->Instance == I2C1 && xMagn_Task != NULL) {
|
|
80053ec: 687b ldr r3, [r7, #4]
|
|
80053ee: 681b ldr r3, [r3, #0]
|
|
80053f0: 4a0f ldr r2, [pc, #60] @ (8005430 <HAL_I2C_MemRxCpltCallback+0x4c>)
|
|
80053f2: 4293 cmp r3, r2
|
|
80053f4: d118 bne.n 8005428 <HAL_I2C_MemRxCpltCallback+0x44>
|
|
80053f6: 4b0f ldr r3, [pc, #60] @ (8005434 <HAL_I2C_MemRxCpltCallback+0x50>)
|
|
80053f8: 681b ldr r3, [r3, #0]
|
|
80053fa: 2b00 cmp r3, #0
|
|
80053fc: d014 beq.n 8005428 <HAL_I2C_MemRxCpltCallback+0x44>
|
|
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
|
80053fe: 2300 movs r3, #0
|
|
8005400: 60fb str r3, [r7, #12]
|
|
// vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken);
|
|
vTaskNotifyGiveIndexedFromISR(xMagn_Task, BMM_NOTIFY_DMA, &xHigherPriorityTaskWoken);
|
|
8005402: 4b0c ldr r3, [pc, #48] @ (8005434 <HAL_I2C_MemRxCpltCallback+0x50>)
|
|
8005404: 681b ldr r3, [r3, #0]
|
|
8005406: f107 020c add.w r2, r7, #12
|
|
800540a: 2101 movs r1, #1
|
|
800540c: 4618 mov r0, r3
|
|
800540e: f011 ff01 bl 8017214 <vTaskGenericNotifyGiveFromISR>
|
|
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
|
8005412: 68fb ldr r3, [r7, #12]
|
|
8005414: 2b00 cmp r3, #0
|
|
8005416: d007 beq.n 8005428 <HAL_I2C_MemRxCpltCallback+0x44>
|
|
8005418: 4b07 ldr r3, [pc, #28] @ (8005438 <HAL_I2C_MemRxCpltCallback+0x54>)
|
|
800541a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800541e: 601a str r2, [r3, #0]
|
|
8005420: f3bf 8f4f dsb sy
|
|
8005424: f3bf 8f6f isb sy
|
|
}
|
|
}
|
|
8005428: bf00 nop
|
|
800542a: 3710 adds r7, #16
|
|
800542c: 46bd mov sp, r7
|
|
800542e: bd80 pop {r7, pc}
|
|
8005430: 40005400 .word 0x40005400
|
|
8005434: 2000072c .word 0x2000072c
|
|
8005438: e000ed04 .word 0xe000ed04
|
|
|
|
0800543c <HAL_I2C_MemTxCpltCallback>:
|
|
|
|
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *I2C_address) {
|
|
800543c: b580 push {r7, lr}
|
|
800543e: b084 sub sp, #16
|
|
8005440: af00 add r7, sp, #0
|
|
8005442: 6078 str r0, [r7, #4]
|
|
if (I2C_address->Instance == I2C1 && xMagn_Task != NULL) {
|
|
8005444: 687b ldr r3, [r7, #4]
|
|
8005446: 681b ldr r3, [r3, #0]
|
|
8005448: 4a0f ldr r2, [pc, #60] @ (8005488 <HAL_I2C_MemTxCpltCallback+0x4c>)
|
|
800544a: 4293 cmp r3, r2
|
|
800544c: d118 bne.n 8005480 <HAL_I2C_MemTxCpltCallback+0x44>
|
|
800544e: 4b0f ldr r3, [pc, #60] @ (800548c <HAL_I2C_MemTxCpltCallback+0x50>)
|
|
8005450: 681b ldr r3, [r3, #0]
|
|
8005452: 2b00 cmp r3, #0
|
|
8005454: d014 beq.n 8005480 <HAL_I2C_MemTxCpltCallback+0x44>
|
|
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
|
8005456: 2300 movs r3, #0
|
|
8005458: 60fb str r3, [r7, #12]
|
|
// vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken);
|
|
vTaskNotifyGiveIndexedFromISR(xMagn_Task, BMM_NOTIFY_DMA, &xHigherPriorityTaskWoken);
|
|
800545a: 4b0c ldr r3, [pc, #48] @ (800548c <HAL_I2C_MemTxCpltCallback+0x50>)
|
|
800545c: 681b ldr r3, [r3, #0]
|
|
800545e: f107 020c add.w r2, r7, #12
|
|
8005462: 2101 movs r1, #1
|
|
8005464: 4618 mov r0, r3
|
|
8005466: f011 fed5 bl 8017214 <vTaskGenericNotifyGiveFromISR>
|
|
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
|
800546a: 68fb ldr r3, [r7, #12]
|
|
800546c: 2b00 cmp r3, #0
|
|
800546e: d007 beq.n 8005480 <HAL_I2C_MemTxCpltCallback+0x44>
|
|
8005470: 4b07 ldr r3, [pc, #28] @ (8005490 <HAL_I2C_MemTxCpltCallback+0x54>)
|
|
8005472: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8005476: 601a str r2, [r3, #0]
|
|
8005478: f3bf 8f4f dsb sy
|
|
800547c: f3bf 8f6f isb sy
|
|
}
|
|
}
|
|
8005480: bf00 nop
|
|
8005482: 3710 adds r7, #16
|
|
8005484: 46bd mov sp, r7
|
|
8005486: bd80 pop {r7, pc}
|
|
8005488: 40005400 .word 0x40005400
|
|
800548c: 2000072c .word 0x2000072c
|
|
8005490: e000ed04 .word 0xe000ed04
|
|
|
|
08005494 <HAL_I2C_ErrorCallback>:
|
|
|
|
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) {
|
|
8005494: b580 push {r7, lr}
|
|
8005496: b084 sub sp, #16
|
|
8005498: af00 add r7, sp, #0
|
|
800549a: 6078 str r0, [r7, #4]
|
|
if (hi2c->Instance == I2C1 && xMagn_Task != NULL) {
|
|
800549c: 687b ldr r3, [r7, #4]
|
|
800549e: 681b ldr r3, [r3, #0]
|
|
80054a0: 4a13 ldr r2, [pc, #76] @ (80054f0 <HAL_I2C_ErrorCallback+0x5c>)
|
|
80054a2: 4293 cmp r3, r2
|
|
80054a4: d120 bne.n 80054e8 <HAL_I2C_ErrorCallback+0x54>
|
|
80054a6: 4b13 ldr r3, [pc, #76] @ (80054f4 <HAL_I2C_ErrorCallback+0x60>)
|
|
80054a8: 681b ldr r3, [r3, #0]
|
|
80054aa: 2b00 cmp r3, #0
|
|
80054ac: d01c beq.n 80054e8 <HAL_I2C_ErrorCallback+0x54>
|
|
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
|
80054ae: 2300 movs r3, #0
|
|
80054b0: 60fb str r3, [r7, #12]
|
|
printf("ErrorCallback: %ld\n", HAL_I2C_GetError(hi2c));
|
|
80054b2: 6878 ldr r0, [r7, #4]
|
|
80054b4: f002 fc0d bl 8007cd2 <HAL_I2C_GetError>
|
|
80054b8: 4603 mov r3, r0
|
|
80054ba: 4619 mov r1, r3
|
|
80054bc: 480e ldr r0, [pc, #56] @ (80054f8 <HAL_I2C_ErrorCallback+0x64>)
|
|
80054be: f014 fea9 bl 801a214 <iprintf>
|
|
// vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken);
|
|
vTaskNotifyGiveIndexedFromISR(xMagn_Task, BMM_NOTIFY_DMA, &xHigherPriorityTaskWoken);
|
|
80054c2: 4b0c ldr r3, [pc, #48] @ (80054f4 <HAL_I2C_ErrorCallback+0x60>)
|
|
80054c4: 681b ldr r3, [r3, #0]
|
|
80054c6: f107 020c add.w r2, r7, #12
|
|
80054ca: 2101 movs r1, #1
|
|
80054cc: 4618 mov r0, r3
|
|
80054ce: f011 fea1 bl 8017214 <vTaskGenericNotifyGiveFromISR>
|
|
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
|
80054d2: 68fb ldr r3, [r7, #12]
|
|
80054d4: 2b00 cmp r3, #0
|
|
80054d6: d007 beq.n 80054e8 <HAL_I2C_ErrorCallback+0x54>
|
|
80054d8: 4b08 ldr r3, [pc, #32] @ (80054fc <HAL_I2C_ErrorCallback+0x68>)
|
|
80054da: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80054de: 601a str r2, [r3, #0]
|
|
80054e0: f3bf 8f4f dsb sy
|
|
80054e4: f3bf 8f6f isb sy
|
|
}
|
|
}
|
|
80054e8: bf00 nop
|
|
80054ea: 3710 adds r7, #16
|
|
80054ec: 46bd mov sp, r7
|
|
80054ee: bd80 pop {r7, pc}
|
|
80054f0: 40005400 .word 0x40005400
|
|
80054f4: 2000072c .word 0x2000072c
|
|
80054f8: 0801df18 .word 0x0801df18
|
|
80054fc: e000ed04 .word 0xe000ed04
|
|
|
|
08005500 <HAL_GPIO_EXTI_Callback>:
|
|
|
|
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
|
|
8005500: b580 push {r7, lr}
|
|
8005502: b084 sub sp, #16
|
|
8005504: af00 add r7, sp, #0
|
|
8005506: 4603 mov r3, r0
|
|
8005508: 80fb strh r3, [r7, #6]
|
|
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
|
800550a: 2300 movs r3, #0
|
|
800550c: 60fb str r3, [r7, #12]
|
|
if (GPIO_Pin == GPIO_IMU_INT_Pin && xIMU_Task != NULL) {
|
|
800550e: 88fb ldrh r3, [r7, #6]
|
|
8005510: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8005514: d10b bne.n 800552e <HAL_GPIO_EXTI_Callback+0x2e>
|
|
8005516: 4b15 ldr r3, [pc, #84] @ (800556c <HAL_GPIO_EXTI_Callback+0x6c>)
|
|
8005518: 681b ldr r3, [r3, #0]
|
|
800551a: 2b00 cmp r3, #0
|
|
800551c: d007 beq.n 800552e <HAL_GPIO_EXTI_Callback+0x2e>
|
|
// vTaskNotifyGiveFromISR(xIMU_Task, &xHigherPriorityTaskWoken);
|
|
vTaskNotifyGiveIndexedFromISR(xIMU_Task, ICM_NOTIFY_INT_DRDY, &xHigherPriorityTaskWoken);
|
|
800551e: 4b13 ldr r3, [pc, #76] @ (800556c <HAL_GPIO_EXTI_Callback+0x6c>)
|
|
8005520: 681b ldr r3, [r3, #0]
|
|
8005522: f107 020c add.w r2, r7, #12
|
|
8005526: 2100 movs r1, #0
|
|
8005528: 4618 mov r0, r3
|
|
800552a: f011 fe73 bl 8017214 <vTaskGenericNotifyGiveFromISR>
|
|
// printf("Triggered ICM45686 EXTI\n");
|
|
}
|
|
if (GPIO_Pin == GPIO_MAGN_INT_Pin && xMagn_Task != NULL) {
|
|
800552e: 88fb ldrh r3, [r7, #6]
|
|
8005530: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8005534: d10b bne.n 800554e <HAL_GPIO_EXTI_Callback+0x4e>
|
|
8005536: 4b0e ldr r3, [pc, #56] @ (8005570 <HAL_GPIO_EXTI_Callback+0x70>)
|
|
8005538: 681b ldr r3, [r3, #0]
|
|
800553a: 2b00 cmp r3, #0
|
|
800553c: d007 beq.n 800554e <HAL_GPIO_EXTI_Callback+0x4e>
|
|
// vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken);
|
|
vTaskNotifyGiveIndexedFromISR(xMagn_Task, BMM_NOTIFY_INT_DRDY, &xHigherPriorityTaskWoken);
|
|
800553e: 4b0c ldr r3, [pc, #48] @ (8005570 <HAL_GPIO_EXTI_Callback+0x70>)
|
|
8005540: 681b ldr r3, [r3, #0]
|
|
8005542: f107 020c add.w r2, r7, #12
|
|
8005546: 2100 movs r1, #0
|
|
8005548: 4618 mov r0, r3
|
|
800554a: f011 fe63 bl 8017214 <vTaskGenericNotifyGiveFromISR>
|
|
}
|
|
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
|
800554e: 68fb ldr r3, [r7, #12]
|
|
8005550: 2b00 cmp r3, #0
|
|
8005552: d007 beq.n 8005564 <HAL_GPIO_EXTI_Callback+0x64>
|
|
8005554: 4b07 ldr r3, [pc, #28] @ (8005574 <HAL_GPIO_EXTI_Callback+0x74>)
|
|
8005556: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800555a: 601a str r2, [r3, #0]
|
|
800555c: f3bf 8f4f dsb sy
|
|
8005560: f3bf 8f6f isb sy
|
|
}
|
|
8005564: bf00 nop
|
|
8005566: 3710 adds r7, #16
|
|
8005568: 46bd mov sp, r7
|
|
800556a: bd80 pop {r7, pc}
|
|
800556c: 20000728 .word 0x20000728
|
|
8005570: 2000072c .word 0x2000072c
|
|
8005574: e000ed04 .word 0xe000ed04
|
|
|
|
08005578 <read_icm>:
|
|
|
|
// ICM 45686
|
|
HAL_StatusTypeDef read_icm (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint8_t rx[], uint16_t len_tx) {
|
|
8005578: b580 push {r7, lr}
|
|
800557a: b088 sub sp, #32
|
|
800557c: af02 add r7, sp, #8
|
|
800557e: 60f8 str r0, [r7, #12]
|
|
8005580: 60b9 str r1, [r7, #8]
|
|
8005582: 607a str r2, [r7, #4]
|
|
8005584: 807b strh r3, [r7, #2]
|
|
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET);
|
|
8005586: 68fb ldr r3, [r7, #12]
|
|
8005588: 6858 ldr r0, [r3, #4]
|
|
800558a: 68fb ldr r3, [r7, #12]
|
|
800558c: 891b ldrh r3, [r3, #8]
|
|
800558e: 2200 movs r2, #0
|
|
8005590: 4619 mov r1, r3
|
|
8005592: f002 f81d bl 80075d0 <HAL_GPIO_WritePin>
|
|
HAL_StatusTypeDef status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, len_tx, 50);
|
|
8005596: 68fb ldr r3, [r7, #12]
|
|
8005598: 6818 ldr r0, [r3, #0]
|
|
800559a: 887b ldrh r3, [r7, #2]
|
|
800559c: 2232 movs r2, #50 @ 0x32
|
|
800559e: 9200 str r2, [sp, #0]
|
|
80055a0: 687a ldr r2, [r7, #4]
|
|
80055a2: 68b9 ldr r1, [r7, #8]
|
|
80055a4: f007 fed7 bl 800d356 <HAL_SPI_TransmitReceive>
|
|
80055a8: 4603 mov r3, r0
|
|
80055aa: 75fb strb r3, [r7, #23]
|
|
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_SET);
|
|
80055ac: 68fb ldr r3, [r7, #12]
|
|
80055ae: 6858 ldr r0, [r3, #4]
|
|
80055b0: 68fb ldr r3, [r7, #12]
|
|
80055b2: 891b ldrh r3, [r3, #8]
|
|
80055b4: 2201 movs r2, #1
|
|
80055b6: 4619 mov r1, r3
|
|
80055b8: f002 f80a bl 80075d0 <HAL_GPIO_WritePin>
|
|
return status;
|
|
80055bc: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80055be: 4618 mov r0, r3
|
|
80055c0: 3718 adds r7, #24
|
|
80055c2: 46bd mov sp, r7
|
|
80055c4: bd80 pop {r7, pc}
|
|
|
|
080055c6 <read_icm_dma>:
|
|
|
|
HAL_StatusTypeDef read_icm_dma (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint8_t rx[], uint16_t len_tx) {
|
|
80055c6: b580 push {r7, lr}
|
|
80055c8: b086 sub sp, #24
|
|
80055ca: af00 add r7, sp, #0
|
|
80055cc: 60f8 str r0, [r7, #12]
|
|
80055ce: 60b9 str r1, [r7, #8]
|
|
80055d0: 607a str r2, [r7, #4]
|
|
80055d2: 807b strh r3, [r7, #2]
|
|
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET);
|
|
80055d4: 68fb ldr r3, [r7, #12]
|
|
80055d6: 6858 ldr r0, [r3, #4]
|
|
80055d8: 68fb ldr r3, [r7, #12]
|
|
80055da: 891b ldrh r3, [r3, #8]
|
|
80055dc: 2200 movs r2, #0
|
|
80055de: 4619 mov r1, r3
|
|
80055e0: f001 fff6 bl 80075d0 <HAL_GPIO_WritePin>
|
|
HAL_StatusTypeDef status = HAL_SPI_TransmitReceive_DMA(imu->hspi, tx, rx, len_tx);
|
|
80055e4: 68fb ldr r3, [r7, #12]
|
|
80055e6: 6818 ldr r0, [r3, #0]
|
|
80055e8: 887b ldrh r3, [r7, #2]
|
|
80055ea: 687a ldr r2, [r7, #4]
|
|
80055ec: 68b9 ldr r1, [r7, #8]
|
|
80055ee: f008 f8d1 bl 800d794 <HAL_SPI_TransmitReceive_DMA>
|
|
80055f2: 4603 mov r3, r0
|
|
80055f4: 75fb strb r3, [r7, #23]
|
|
return status;
|
|
80055f6: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80055f8: 4618 mov r0, r3
|
|
80055fa: 3718 adds r7, #24
|
|
80055fc: 46bd mov sp, r7
|
|
80055fe: bd80 pop {r7, pc}
|
|
|
|
08005600 <write_icm>:
|
|
|
|
HAL_StatusTypeDef write_icm (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint16_t len_tx) {
|
|
8005600: b580 push {r7, lr}
|
|
8005602: b086 sub sp, #24
|
|
8005604: af00 add r7, sp, #0
|
|
8005606: 60f8 str r0, [r7, #12]
|
|
8005608: 60b9 str r1, [r7, #8]
|
|
800560a: 4613 mov r3, r2
|
|
800560c: 80fb strh r3, [r7, #6]
|
|
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET);
|
|
800560e: 68fb ldr r3, [r7, #12]
|
|
8005610: 6858 ldr r0, [r3, #4]
|
|
8005612: 68fb ldr r3, [r7, #12]
|
|
8005614: 891b ldrh r3, [r3, #8]
|
|
8005616: 2200 movs r2, #0
|
|
8005618: 4619 mov r1, r3
|
|
800561a: f001 ffd9 bl 80075d0 <HAL_GPIO_WritePin>
|
|
HAL_StatusTypeDef status = HAL_SPI_Transmit(imu->hspi, tx, len_tx, 50);
|
|
800561e: 68fb ldr r3, [r7, #12]
|
|
8005620: 6818 ldr r0, [r3, #0]
|
|
8005622: 88fa ldrh r2, [r7, #6]
|
|
8005624: 2332 movs r3, #50 @ 0x32
|
|
8005626: 68b9 ldr r1, [r7, #8]
|
|
8005628: f007 fd1f bl 800d06a <HAL_SPI_Transmit>
|
|
800562c: 4603 mov r3, r0
|
|
800562e: 75fb strb r3, [r7, #23]
|
|
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_SET);
|
|
8005630: 68fb ldr r3, [r7, #12]
|
|
8005632: 6858 ldr r0, [r3, #4]
|
|
8005634: 68fb ldr r3, [r7, #12]
|
|
8005636: 891b ldrh r3, [r3, #8]
|
|
8005638: 2201 movs r2, #1
|
|
800563a: 4619 mov r1, r3
|
|
800563c: f001 ffc8 bl 80075d0 <HAL_GPIO_WritePin>
|
|
return status;
|
|
8005640: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8005642: 4618 mov r0, r3
|
|
8005644: 3718 adds r7, #24
|
|
8005646: 46bd mov sp, r7
|
|
8005648: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800564c <init_icm>:
|
|
|
|
void init_icm(ICM45686_HandleTypeDef *imu) {
|
|
800564c: b580 push {r7, lr}
|
|
800564e: b084 sub sp, #16
|
|
8005650: af00 add r7, sp, #0
|
|
8005652: 6078 str r0, [r7, #4]
|
|
uint8_t tx[2], rx[2];
|
|
HAL_StatusTypeDef status;
|
|
// // WHO AM
|
|
tx[0] = ICM45686_WHO_AM_I | 0x80;
|
|
8005654: 23f2 movs r3, #242 @ 0xf2
|
|
8005656: 733b strb r3, [r7, #12]
|
|
status = read_icm(imu, tx, rx, sizeof(tx));
|
|
8005658: f107 0208 add.w r2, r7, #8
|
|
800565c: f107 010c add.w r1, r7, #12
|
|
8005660: 2302 movs r3, #2
|
|
8005662: 6878 ldr r0, [r7, #4]
|
|
8005664: f7ff ff88 bl 8005578 <read_icm>
|
|
8005668: 4603 mov r3, r0
|
|
800566a: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
800566c: 7bfb ldrb r3, [r7, #15]
|
|
800566e: 2b00 cmp r3, #0
|
|
8005670: d005 beq.n 800567e <init_icm+0x32>
|
|
printf("Error in reading WHO AM I:%d\n", status);
|
|
8005672: 7bfb ldrb r3, [r7, #15]
|
|
8005674: 4619 mov r1, r3
|
|
8005676: 485e ldr r0, [pc, #376] @ (80057f0 <init_icm+0x1a4>)
|
|
8005678: f014 fdcc bl 801a214 <iprintf>
|
|
800567c: e004 b.n 8005688 <init_icm+0x3c>
|
|
} else {
|
|
printf("WHO AM I (0xE9): 0x%02X \n", rx[1]);
|
|
800567e: 7a7b ldrb r3, [r7, #9]
|
|
8005680: 4619 mov r1, r3
|
|
8005682: 485c ldr r0, [pc, #368] @ (80057f4 <init_icm+0x1a8>)
|
|
8005684: f014 fdc6 bl 801a214 <iprintf>
|
|
}
|
|
|
|
// acc config
|
|
tx[0] = ICM45686_ACCEL_CONFIG0;
|
|
8005688: 231b movs r3, #27
|
|
800568a: 733b strb r3, [r7, #12]
|
|
tx[1] = imu->acc_fs | imu->odr;
|
|
800568c: 687b ldr r3, [r7, #4]
|
|
800568e: 7a9a ldrb r2, [r3, #10]
|
|
8005690: 687b ldr r3, [r7, #4]
|
|
8005692: 7b1b ldrb r3, [r3, #12]
|
|
8005694: 4313 orrs r3, r2
|
|
8005696: b2db uxtb r3, r3
|
|
8005698: 737b strb r3, [r7, #13]
|
|
status = write_icm(imu, tx, sizeof(tx));
|
|
800569a: f107 030c add.w r3, r7, #12
|
|
800569e: 2202 movs r2, #2
|
|
80056a0: 4619 mov r1, r3
|
|
80056a2: 6878 ldr r0, [r7, #4]
|
|
80056a4: f7ff ffac bl 8005600 <write_icm>
|
|
80056a8: 4603 mov r3, r0
|
|
80056aa: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
80056ac: 7bfb ldrb r3, [r7, #15]
|
|
80056ae: 2b00 cmp r3, #0
|
|
80056b0: d005 beq.n 80056be <init_icm+0x72>
|
|
printf("Error in setting ACCEL_CONFIG0:%d\n", status);
|
|
80056b2: 7bfb ldrb r3, [r7, #15]
|
|
80056b4: 4619 mov r1, r3
|
|
80056b6: 4850 ldr r0, [pc, #320] @ (80057f8 <init_icm+0x1ac>)
|
|
80056b8: f014 fdac bl 801a214 <iprintf>
|
|
80056bc: e004 b.n 80056c8 <init_icm+0x7c>
|
|
} else {
|
|
printf("ACCEL_CONFIG0 wrote: 0x%02X \n", tx[1]);
|
|
80056be: 7b7b ldrb r3, [r7, #13]
|
|
80056c0: 4619 mov r1, r3
|
|
80056c2: 484e ldr r0, [pc, #312] @ (80057fc <init_icm+0x1b0>)
|
|
80056c4: f014 fda6 bl 801a214 <iprintf>
|
|
}
|
|
|
|
tx[0] = ICM45686_ACCEL_CONFIG0 | 0x80;
|
|
80056c8: 239b movs r3, #155 @ 0x9b
|
|
80056ca: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x00;
|
|
80056cc: 2300 movs r3, #0
|
|
80056ce: 737b strb r3, [r7, #13]
|
|
status = read_icm(imu, tx, rx, sizeof(tx));
|
|
80056d0: f107 0208 add.w r2, r7, #8
|
|
80056d4: f107 010c add.w r1, r7, #12
|
|
80056d8: 2302 movs r3, #2
|
|
80056da: 6878 ldr r0, [r7, #4]
|
|
80056dc: f7ff ff4c bl 8005578 <read_icm>
|
|
80056e0: 4603 mov r3, r0
|
|
80056e2: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
80056e4: 7bfb ldrb r3, [r7, #15]
|
|
80056e6: 2b00 cmp r3, #0
|
|
80056e8: d005 beq.n 80056f6 <init_icm+0xaa>
|
|
printf("Error reading ACCEL_CONFIG0:%d\n", status);
|
|
80056ea: 7bfb ldrb r3, [r7, #15]
|
|
80056ec: 4619 mov r1, r3
|
|
80056ee: 4844 ldr r0, [pc, #272] @ (8005800 <init_icm+0x1b4>)
|
|
80056f0: f014 fd90 bl 801a214 <iprintf>
|
|
80056f4: e004 b.n 8005700 <init_icm+0xb4>
|
|
} else {
|
|
printf("ACCEL_CONFIG0 read: 0x%02X \n", rx[1]);
|
|
80056f6: 7a7b ldrb r3, [r7, #9]
|
|
80056f8: 4619 mov r1, r3
|
|
80056fa: 4842 ldr r0, [pc, #264] @ (8005804 <init_icm+0x1b8>)
|
|
80056fc: f014 fd8a bl 801a214 <iprintf>
|
|
}
|
|
|
|
// gyro config
|
|
tx[0] = ICM45686_GYRO_CONFIG0;
|
|
8005700: 231c movs r3, #28
|
|
8005702: 733b strb r3, [r7, #12]
|
|
tx[1] = imu->gyro_fs | imu->odr;
|
|
8005704: 687b ldr r3, [r7, #4]
|
|
8005706: 7ada ldrb r2, [r3, #11]
|
|
8005708: 687b ldr r3, [r7, #4]
|
|
800570a: 7b1b ldrb r3, [r3, #12]
|
|
800570c: 4313 orrs r3, r2
|
|
800570e: b2db uxtb r3, r3
|
|
8005710: 737b strb r3, [r7, #13]
|
|
status = write_icm(imu, tx, sizeof(tx));
|
|
8005712: f107 030c add.w r3, r7, #12
|
|
8005716: 2202 movs r2, #2
|
|
8005718: 4619 mov r1, r3
|
|
800571a: 6878 ldr r0, [r7, #4]
|
|
800571c: f7ff ff70 bl 8005600 <write_icm>
|
|
8005720: 4603 mov r3, r0
|
|
8005722: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8005724: 7bfb ldrb r3, [r7, #15]
|
|
8005726: 2b00 cmp r3, #0
|
|
8005728: d005 beq.n 8005736 <init_icm+0xea>
|
|
printf("Error in setting GYRO_CONFIG0:%d\n", status);
|
|
800572a: 7bfb ldrb r3, [r7, #15]
|
|
800572c: 4619 mov r1, r3
|
|
800572e: 4836 ldr r0, [pc, #216] @ (8005808 <init_icm+0x1bc>)
|
|
8005730: f014 fd70 bl 801a214 <iprintf>
|
|
8005734: e004 b.n 8005740 <init_icm+0xf4>
|
|
} else {
|
|
printf("GYRO_CONFIG0 wrote: 0x%02X \n", tx[1]);
|
|
8005736: 7b7b ldrb r3, [r7, #13]
|
|
8005738: 4619 mov r1, r3
|
|
800573a: 4834 ldr r0, [pc, #208] @ (800580c <init_icm+0x1c0>)
|
|
800573c: f014 fd6a bl 801a214 <iprintf>
|
|
}
|
|
|
|
tx[0] = ICM45686_GYRO_CONFIG0 | 0x80;
|
|
8005740: 239c movs r3, #156 @ 0x9c
|
|
8005742: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x00;
|
|
8005744: 2300 movs r3, #0
|
|
8005746: 737b strb r3, [r7, #13]
|
|
status = read_icm(imu, tx, rx, sizeof(tx));
|
|
8005748: f107 0208 add.w r2, r7, #8
|
|
800574c: f107 010c add.w r1, r7, #12
|
|
8005750: 2302 movs r3, #2
|
|
8005752: 6878 ldr r0, [r7, #4]
|
|
8005754: f7ff ff10 bl 8005578 <read_icm>
|
|
8005758: 4603 mov r3, r0
|
|
800575a: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
800575c: 7bfb ldrb r3, [r7, #15]
|
|
800575e: 2b00 cmp r3, #0
|
|
8005760: d005 beq.n 800576e <init_icm+0x122>
|
|
printf("Error reading GYRO_CONFIG0:%d\n", status);
|
|
8005762: 7bfb ldrb r3, [r7, #15]
|
|
8005764: 4619 mov r1, r3
|
|
8005766: 482a ldr r0, [pc, #168] @ (8005810 <init_icm+0x1c4>)
|
|
8005768: f014 fd54 bl 801a214 <iprintf>
|
|
800576c: e004 b.n 8005778 <init_icm+0x12c>
|
|
} else {
|
|
printf("GYRO_CONFIG0 read: 0x%02X \n", rx[1]);
|
|
800576e: 7a7b ldrb r3, [r7, #9]
|
|
8005770: 4619 mov r1, r3
|
|
8005772: 4828 ldr r0, [pc, #160] @ (8005814 <init_icm+0x1c8>)
|
|
8005774: f014 fd4e bl 801a214 <iprintf>
|
|
}
|
|
|
|
// power settings
|
|
tx[0] = ICM45686_PWR_MGMT0;
|
|
8005778: 2310 movs r3, #16
|
|
800577a: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x0F; //0x10 | 0x03;
|
|
800577c: 230f movs r3, #15
|
|
800577e: 737b strb r3, [r7, #13]
|
|
status = write_icm(imu, tx, sizeof(tx));
|
|
8005780: f107 030c add.w r3, r7, #12
|
|
8005784: 2202 movs r2, #2
|
|
8005786: 4619 mov r1, r3
|
|
8005788: 6878 ldr r0, [r7, #4]
|
|
800578a: f7ff ff39 bl 8005600 <write_icm>
|
|
800578e: 4603 mov r3, r0
|
|
8005790: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8005792: 7bfb ldrb r3, [r7, #15]
|
|
8005794: 2b00 cmp r3, #0
|
|
8005796: d005 beq.n 80057a4 <init_icm+0x158>
|
|
printf("Error in setting PWR_MGMT0:%d\n", status);
|
|
8005798: 7bfb ldrb r3, [r7, #15]
|
|
800579a: 4619 mov r1, r3
|
|
800579c: 481e ldr r0, [pc, #120] @ (8005818 <init_icm+0x1cc>)
|
|
800579e: f014 fd39 bl 801a214 <iprintf>
|
|
80057a2: e004 b.n 80057ae <init_icm+0x162>
|
|
} else {
|
|
printf("PWR_MGMT0 wrote: 0x%02X \n", tx[1]);
|
|
80057a4: 7b7b ldrb r3, [r7, #13]
|
|
80057a6: 4619 mov r1, r3
|
|
80057a8: 481c ldr r0, [pc, #112] @ (800581c <init_icm+0x1d0>)
|
|
80057aa: f014 fd33 bl 801a214 <iprintf>
|
|
}
|
|
|
|
tx[0] = ICM45686_PWR_MGMT0 | 0x80;
|
|
80057ae: 2390 movs r3, #144 @ 0x90
|
|
80057b0: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x00;
|
|
80057b2: 2300 movs r3, #0
|
|
80057b4: 737b strb r3, [r7, #13]
|
|
status = read_icm(imu, tx, rx, sizeof(tx));
|
|
80057b6: f107 0208 add.w r2, r7, #8
|
|
80057ba: f107 010c add.w r1, r7, #12
|
|
80057be: 2302 movs r3, #2
|
|
80057c0: 6878 ldr r0, [r7, #4]
|
|
80057c2: f7ff fed9 bl 8005578 <read_icm>
|
|
80057c6: 4603 mov r3, r0
|
|
80057c8: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
80057ca: 7bfb ldrb r3, [r7, #15]
|
|
80057cc: 2b00 cmp r3, #0
|
|
80057ce: d005 beq.n 80057dc <init_icm+0x190>
|
|
printf("Error reading PWR_MGMT0:%d\n", status);
|
|
80057d0: 7bfb ldrb r3, [r7, #15]
|
|
80057d2: 4619 mov r1, r3
|
|
80057d4: 4812 ldr r0, [pc, #72] @ (8005820 <init_icm+0x1d4>)
|
|
80057d6: f014 fd1d bl 801a214 <iprintf>
|
|
} else {
|
|
printf("PWR_MGMT0 read: 0x%02X \n", rx[1]);
|
|
}
|
|
}
|
|
80057da: e004 b.n 80057e6 <init_icm+0x19a>
|
|
printf("PWR_MGMT0 read: 0x%02X \n", rx[1]);
|
|
80057dc: 7a7b ldrb r3, [r7, #9]
|
|
80057de: 4619 mov r1, r3
|
|
80057e0: 4810 ldr r0, [pc, #64] @ (8005824 <init_icm+0x1d8>)
|
|
80057e2: f014 fd17 bl 801a214 <iprintf>
|
|
}
|
|
80057e6: bf00 nop
|
|
80057e8: 3710 adds r7, #16
|
|
80057ea: 46bd mov sp, r7
|
|
80057ec: bd80 pop {r7, pc}
|
|
80057ee: bf00 nop
|
|
80057f0: 0801df2c .word 0x0801df2c
|
|
80057f4: 0801df4c .word 0x0801df4c
|
|
80057f8: 0801df68 .word 0x0801df68
|
|
80057fc: 0801df8c .word 0x0801df8c
|
|
8005800: 0801dfac .word 0x0801dfac
|
|
8005804: 0801dfcc .word 0x0801dfcc
|
|
8005808: 0801dfec .word 0x0801dfec
|
|
800580c: 0801e010 .word 0x0801e010
|
|
8005810: 0801e030 .word 0x0801e030
|
|
8005814: 0801e050 .word 0x0801e050
|
|
8005818: 0801e06c .word 0x0801e06c
|
|
800581c: 0801e08c .word 0x0801e08c
|
|
8005820: 0801e0a8 .word 0x0801e0a8
|
|
8005824: 0801e0c4 .word 0x0801e0c4
|
|
|
|
08005828 <calibrate_icm>:
|
|
|
|
void calibrate_icm(ICM45686_HandleTypeDef *imu, int samples) {
|
|
8005828: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
800582c: b0a2 sub sp, #136 @ 0x88
|
|
800582e: af0c add r7, sp, #48 @ 0x30
|
|
8005830: 61f8 str r0, [r7, #28]
|
|
8005832: 61b9 str r1, [r7, #24]
|
|
HAL_StatusTypeDef status;
|
|
uint8_t raw_data[15];
|
|
int16_t sensor_data[7] = {0};
|
|
8005834: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8005838: 2200 movs r2, #0
|
|
800583a: 601a str r2, [r3, #0]
|
|
800583c: 605a str r2, [r3, #4]
|
|
800583e: 609a str r2, [r3, #8]
|
|
8005840: 819a strh r2, [r3, #12]
|
|
uint8_t tx[15] = {0x00};
|
|
8005842: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8005846: 2200 movs r2, #0
|
|
8005848: 601a str r2, [r3, #0]
|
|
800584a: 605a str r2, [r3, #4]
|
|
800584c: 609a str r2, [r3, #8]
|
|
800584e: f8c3 200b str.w r2, [r3, #11]
|
|
tx[0] = 0x00 | 0x80;
|
|
8005852: 2380 movs r3, #128 @ 0x80
|
|
8005854: f887 3024 strb.w r3, [r7, #36] @ 0x24
|
|
|
|
for (int i = 1; i <= samples; i++) {
|
|
8005858: 2301 movs r3, #1
|
|
800585a: 657b str r3, [r7, #84] @ 0x54
|
|
800585c: e0a4 b.n 80059a8 <calibrate_icm+0x180>
|
|
// status = read_icm_dma(imu, tx, raw_data, sizeof(tx));
|
|
// osDelay(1);
|
|
// if (status != HAL_OK) {
|
|
// printf("Calibration read ICM failed: %d\n", status);
|
|
// }
|
|
ulTaskNotifyTakeIndexed(ICM_NOTIFY_INT_DRDY, pdTRUE, portMAX_DELAY);
|
|
800585e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8005862: 2101 movs r1, #1
|
|
8005864: 2000 movs r0, #0
|
|
8005866: f011 f965 bl 8016b34 <ulTaskGenericNotifyTake>
|
|
status = read_icm_dma(imu, tx, raw_data, sizeof(tx));
|
|
800586a: f107 0244 add.w r2, r7, #68 @ 0x44
|
|
800586e: f107 0124 add.w r1, r7, #36 @ 0x24
|
|
8005872: 230f movs r3, #15
|
|
8005874: 69f8 ldr r0, [r7, #28]
|
|
8005876: f7ff fea6 bl 80055c6 <read_icm_dma>
|
|
800587a: 4603 mov r3, r0
|
|
800587c: f887 3053 strb.w r3, [r7, #83] @ 0x53
|
|
if (status != HAL_OK) {
|
|
8005880: f897 3053 ldrb.w r3, [r7, #83] @ 0x53
|
|
8005884: 2b00 cmp r3, #0
|
|
8005886: d005 beq.n 8005894 <calibrate_icm+0x6c>
|
|
printf("Calibration read ICM failed: %d\n", status);
|
|
8005888: f897 3053 ldrb.w r3, [r7, #83] @ 0x53
|
|
800588c: 4619 mov r1, r3
|
|
800588e: 48ad ldr r0, [pc, #692] @ (8005b44 <calibrate_icm+0x31c>)
|
|
8005890: f014 fcc0 bl 801a214 <iprintf>
|
|
}
|
|
if (ulTaskNotifyTakeIndexed(ICM_NOTIFY_DMA, pdTRUE, pdMS_TO_TICKS(10)) > 0) {
|
|
8005894: 220a movs r2, #10
|
|
8005896: 2101 movs r1, #1
|
|
8005898: 2001 movs r0, #1
|
|
800589a: f011 f94b bl 8016b34 <ulTaskGenericNotifyTake>
|
|
800589e: 4603 mov r3, r0
|
|
80058a0: 2b00 cmp r3, #0
|
|
80058a2: d07e beq.n 80059a2 <calibrate_icm+0x17a>
|
|
sensor_data[0] += (int16_t)(raw_data[1] << 8 | raw_data[2]); // a_x
|
|
80058a4: f9b7 3034 ldrsh.w r3, [r7, #52] @ 0x34
|
|
80058a8: b29a uxth r2, r3
|
|
80058aa: f897 3045 ldrb.w r3, [r7, #69] @ 0x45
|
|
80058ae: b21b sxth r3, r3
|
|
80058b0: 021b lsls r3, r3, #8
|
|
80058b2: b219 sxth r1, r3
|
|
80058b4: f897 3046 ldrb.w r3, [r7, #70] @ 0x46
|
|
80058b8: b21b sxth r3, r3
|
|
80058ba: 430b orrs r3, r1
|
|
80058bc: b21b sxth r3, r3
|
|
80058be: b29b uxth r3, r3
|
|
80058c0: 4413 add r3, r2
|
|
80058c2: b29b uxth r3, r3
|
|
80058c4: b21b sxth r3, r3
|
|
80058c6: 86bb strh r3, [r7, #52] @ 0x34
|
|
sensor_data[1] += (int16_t)(raw_data[3] << 8 | raw_data[4]); // a_y
|
|
80058c8: f9b7 3036 ldrsh.w r3, [r7, #54] @ 0x36
|
|
80058cc: b29a uxth r2, r3
|
|
80058ce: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
|
|
80058d2: b21b sxth r3, r3
|
|
80058d4: 021b lsls r3, r3, #8
|
|
80058d6: b219 sxth r1, r3
|
|
80058d8: f897 3048 ldrb.w r3, [r7, #72] @ 0x48
|
|
80058dc: b21b sxth r3, r3
|
|
80058de: 430b orrs r3, r1
|
|
80058e0: b21b sxth r3, r3
|
|
80058e2: b29b uxth r3, r3
|
|
80058e4: 4413 add r3, r2
|
|
80058e6: b29b uxth r3, r3
|
|
80058e8: b21b sxth r3, r3
|
|
80058ea: 86fb strh r3, [r7, #54] @ 0x36
|
|
sensor_data[2] += (int16_t)(raw_data[5] << 8 | raw_data[6]); // a_z
|
|
80058ec: f9b7 3038 ldrsh.w r3, [r7, #56] @ 0x38
|
|
80058f0: b29a uxth r2, r3
|
|
80058f2: f897 3049 ldrb.w r3, [r7, #73] @ 0x49
|
|
80058f6: b21b sxth r3, r3
|
|
80058f8: 021b lsls r3, r3, #8
|
|
80058fa: b219 sxth r1, r3
|
|
80058fc: f897 304a ldrb.w r3, [r7, #74] @ 0x4a
|
|
8005900: b21b sxth r3, r3
|
|
8005902: 430b orrs r3, r1
|
|
8005904: b21b sxth r3, r3
|
|
8005906: b29b uxth r3, r3
|
|
8005908: 4413 add r3, r2
|
|
800590a: b29b uxth r3, r3
|
|
800590c: b21b sxth r3, r3
|
|
800590e: 873b strh r3, [r7, #56] @ 0x38
|
|
sensor_data[3] += (int16_t)(raw_data[7] << 8 | raw_data[8]); // g_x
|
|
8005910: f9b7 303a ldrsh.w r3, [r7, #58] @ 0x3a
|
|
8005914: b29a uxth r2, r3
|
|
8005916: f897 304b ldrb.w r3, [r7, #75] @ 0x4b
|
|
800591a: b21b sxth r3, r3
|
|
800591c: 021b lsls r3, r3, #8
|
|
800591e: b219 sxth r1, r3
|
|
8005920: f897 304c ldrb.w r3, [r7, #76] @ 0x4c
|
|
8005924: b21b sxth r3, r3
|
|
8005926: 430b orrs r3, r1
|
|
8005928: b21b sxth r3, r3
|
|
800592a: b29b uxth r3, r3
|
|
800592c: 4413 add r3, r2
|
|
800592e: b29b uxth r3, r3
|
|
8005930: b21b sxth r3, r3
|
|
8005932: 877b strh r3, [r7, #58] @ 0x3a
|
|
sensor_data[4] += (int16_t)(raw_data[9] << 8 | raw_data[10]); // g_y
|
|
8005934: f9b7 303c ldrsh.w r3, [r7, #60] @ 0x3c
|
|
8005938: b29a uxth r2, r3
|
|
800593a: f897 304d ldrb.w r3, [r7, #77] @ 0x4d
|
|
800593e: b21b sxth r3, r3
|
|
8005940: 021b lsls r3, r3, #8
|
|
8005942: b219 sxth r1, r3
|
|
8005944: f897 304e ldrb.w r3, [r7, #78] @ 0x4e
|
|
8005948: b21b sxth r3, r3
|
|
800594a: 430b orrs r3, r1
|
|
800594c: b21b sxth r3, r3
|
|
800594e: b29b uxth r3, r3
|
|
8005950: 4413 add r3, r2
|
|
8005952: b29b uxth r3, r3
|
|
8005954: b21b sxth r3, r3
|
|
8005956: 87bb strh r3, [r7, #60] @ 0x3c
|
|
sensor_data[5] += (int16_t)(raw_data[11] << 8 | raw_data[12]); // g_z
|
|
8005958: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e
|
|
800595c: b29a uxth r2, r3
|
|
800595e: f897 304f ldrb.w r3, [r7, #79] @ 0x4f
|
|
8005962: b21b sxth r3, r3
|
|
8005964: 021b lsls r3, r3, #8
|
|
8005966: b219 sxth r1, r3
|
|
8005968: f897 3050 ldrb.w r3, [r7, #80] @ 0x50
|
|
800596c: b21b sxth r3, r3
|
|
800596e: 430b orrs r3, r1
|
|
8005970: b21b sxth r3, r3
|
|
8005972: b29b uxth r3, r3
|
|
8005974: 4413 add r3, r2
|
|
8005976: b29b uxth r3, r3
|
|
8005978: b21b sxth r3, r3
|
|
800597a: 87fb strh r3, [r7, #62] @ 0x3e
|
|
sensor_data[6] += (int16_t)(raw_data[13] << 8 | raw_data[14]); // t
|
|
800597c: f9b7 3040 ldrsh.w r3, [r7, #64] @ 0x40
|
|
8005980: b29a uxth r2, r3
|
|
8005982: f897 3051 ldrb.w r3, [r7, #81] @ 0x51
|
|
8005986: b21b sxth r3, r3
|
|
8005988: 021b lsls r3, r3, #8
|
|
800598a: b219 sxth r1, r3
|
|
800598c: f897 3052 ldrb.w r3, [r7, #82] @ 0x52
|
|
8005990: b21b sxth r3, r3
|
|
8005992: 430b orrs r3, r1
|
|
8005994: b21b sxth r3, r3
|
|
8005996: b29b uxth r3, r3
|
|
8005998: 4413 add r3, r2
|
|
800599a: b29b uxth r3, r3
|
|
800599c: b21b sxth r3, r3
|
|
800599e: f8a7 3040 strh.w r3, [r7, #64] @ 0x40
|
|
for (int i = 1; i <= samples; i++) {
|
|
80059a2: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80059a4: 3301 adds r3, #1
|
|
80059a6: 657b str r3, [r7, #84] @ 0x54
|
|
80059a8: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
80059aa: 69bb ldr r3, [r7, #24]
|
|
80059ac: 429a cmp r2, r3
|
|
80059ae: f77f af56 ble.w 800585e <calibrate_icm+0x36>
|
|
}
|
|
}
|
|
|
|
imu->imu_bias[0] = (float)sensor_data[0] / (float)samples;
|
|
80059b2: f9b7 3034 ldrsh.w r3, [r7, #52] @ 0x34
|
|
80059b6: ee07 3a90 vmov s15, r3
|
|
80059ba: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
80059be: 69bb ldr r3, [r7, #24]
|
|
80059c0: ee07 3a90 vmov s15, r3
|
|
80059c4: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80059c8: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
80059cc: 69fb ldr r3, [r7, #28]
|
|
80059ce: edc3 7a07 vstr s15, [r3, #28]
|
|
imu->imu_bias[1] = (float)sensor_data[1] / (float)samples;
|
|
80059d2: f9b7 3036 ldrsh.w r3, [r7, #54] @ 0x36
|
|
80059d6: ee07 3a90 vmov s15, r3
|
|
80059da: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
80059de: 69bb ldr r3, [r7, #24]
|
|
80059e0: ee07 3a90 vmov s15, r3
|
|
80059e4: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80059e8: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
80059ec: 69fb ldr r3, [r7, #28]
|
|
80059ee: edc3 7a08 vstr s15, [r3, #32]
|
|
imu->imu_bias[2] = (float)sensor_data[2] / (float)samples;
|
|
80059f2: f9b7 3038 ldrsh.w r3, [r7, #56] @ 0x38
|
|
80059f6: ee07 3a90 vmov s15, r3
|
|
80059fa: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
80059fe: 69bb ldr r3, [r7, #24]
|
|
8005a00: ee07 3a90 vmov s15, r3
|
|
8005a04: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8005a08: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8005a0c: 69fb ldr r3, [r7, #28]
|
|
8005a0e: edc3 7a09 vstr s15, [r3, #36] @ 0x24
|
|
imu->imu_bias[3] = (float)sensor_data[3] / (float)samples;
|
|
8005a12: f9b7 303a ldrsh.w r3, [r7, #58] @ 0x3a
|
|
8005a16: ee07 3a90 vmov s15, r3
|
|
8005a1a: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
8005a1e: 69bb ldr r3, [r7, #24]
|
|
8005a20: ee07 3a90 vmov s15, r3
|
|
8005a24: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8005a28: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8005a2c: 69fb ldr r3, [r7, #28]
|
|
8005a2e: edc3 7a0a vstr s15, [r3, #40] @ 0x28
|
|
imu->imu_bias[4] = (float)sensor_data[4] / (float)samples;
|
|
8005a32: f9b7 303c ldrsh.w r3, [r7, #60] @ 0x3c
|
|
8005a36: ee07 3a90 vmov s15, r3
|
|
8005a3a: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
8005a3e: 69bb ldr r3, [r7, #24]
|
|
8005a40: ee07 3a90 vmov s15, r3
|
|
8005a44: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8005a48: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8005a4c: 69fb ldr r3, [r7, #28]
|
|
8005a4e: edc3 7a0b vstr s15, [r3, #44] @ 0x2c
|
|
imu->imu_bias[5] = (float)sensor_data[5] / (float)samples;
|
|
8005a52: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e
|
|
8005a56: ee07 3a90 vmov s15, r3
|
|
8005a5a: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
8005a5e: 69bb ldr r3, [r7, #24]
|
|
8005a60: ee07 3a90 vmov s15, r3
|
|
8005a64: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8005a68: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8005a6c: 69fb ldr r3, [r7, #28]
|
|
8005a6e: edc3 7a0c vstr s15, [r3, #48] @ 0x30
|
|
imu->imu_bias[6] = (float)sensor_data[6] / (float)samples;
|
|
8005a72: f9b7 3040 ldrsh.w r3, [r7, #64] @ 0x40
|
|
8005a76: ee07 3a90 vmov s15, r3
|
|
8005a7a: eef8 6ae7 vcvt.f32.s32 s13, s15
|
|
8005a7e: 69bb ldr r3, [r7, #24]
|
|
8005a80: ee07 3a90 vmov s15, r3
|
|
8005a84: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8005a88: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8005a8c: 69fb ldr r3, [r7, #28]
|
|
8005a8e: edc3 7a0d vstr s15, [r3, #52] @ 0x34
|
|
|
|
// remrove gravity
|
|
imu->imu_bias[2] -= 1.0f;
|
|
8005a92: 69fb ldr r3, [r7, #28]
|
|
8005a94: edd3 7a09 vldr s15, [r3, #36] @ 0x24
|
|
8005a98: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
|
|
8005a9c: ee77 7ac7 vsub.f32 s15, s15, s14
|
|
8005aa0: 69fb ldr r3, [r7, #28]
|
|
8005aa2: edc3 7a09 vstr s15, [r3, #36] @ 0x24
|
|
|
|
imu->calibated = true;
|
|
8005aa6: 69fb ldr r3, [r7, #28]
|
|
8005aa8: 2201 movs r2, #1
|
|
8005aaa: 761a strb r2, [r3, #24]
|
|
|
|
printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n",
|
|
imu->imu_bias[0], imu->imu_bias[1], imu->imu_bias[2],
|
|
8005aac: 69fb ldr r3, [r7, #28]
|
|
8005aae: 69db ldr r3, [r3, #28]
|
|
printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n",
|
|
8005ab0: 4618 mov r0, r3
|
|
8005ab2: f7fa fd21 bl 80004f8 <__aeabi_f2d>
|
|
8005ab6: e9c7 0104 strd r0, r1, [r7, #16]
|
|
imu->imu_bias[0], imu->imu_bias[1], imu->imu_bias[2],
|
|
8005aba: 69fb ldr r3, [r7, #28]
|
|
8005abc: 6a1b ldr r3, [r3, #32]
|
|
printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n",
|
|
8005abe: 4618 mov r0, r3
|
|
8005ac0: f7fa fd1a bl 80004f8 <__aeabi_f2d>
|
|
8005ac4: 4680 mov r8, r0
|
|
8005ac6: 4689 mov r9, r1
|
|
imu->imu_bias[0], imu->imu_bias[1], imu->imu_bias[2],
|
|
8005ac8: 69fb ldr r3, [r7, #28]
|
|
8005aca: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n",
|
|
8005acc: 4618 mov r0, r3
|
|
8005ace: f7fa fd13 bl 80004f8 <__aeabi_f2d>
|
|
8005ad2: 4682 mov sl, r0
|
|
8005ad4: 468b mov fp, r1
|
|
imu->imu_bias[3], imu->imu_bias[4], imu->imu_bias[5],
|
|
8005ad6: 69fb ldr r3, [r7, #28]
|
|
8005ad8: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n",
|
|
8005ada: 4618 mov r0, r3
|
|
8005adc: f7fa fd0c bl 80004f8 <__aeabi_f2d>
|
|
8005ae0: e9c7 0102 strd r0, r1, [r7, #8]
|
|
imu->imu_bias[3], imu->imu_bias[4], imu->imu_bias[5],
|
|
8005ae4: 69fb ldr r3, [r7, #28]
|
|
8005ae6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n",
|
|
8005ae8: 4618 mov r0, r3
|
|
8005aea: f7fa fd05 bl 80004f8 <__aeabi_f2d>
|
|
8005aee: e9c7 0100 strd r0, r1, [r7]
|
|
imu->imu_bias[3], imu->imu_bias[4], imu->imu_bias[5],
|
|
8005af2: 69fb ldr r3, [r7, #28]
|
|
8005af4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n",
|
|
8005af6: 4618 mov r0, r3
|
|
8005af8: f7fa fcfe bl 80004f8 <__aeabi_f2d>
|
|
8005afc: 4604 mov r4, r0
|
|
8005afe: 460d mov r5, r1
|
|
imu->imu_bias[6]);
|
|
8005b00: 69fb ldr r3, [r7, #28]
|
|
8005b02: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n",
|
|
8005b04: 4618 mov r0, r3
|
|
8005b06: f7fa fcf7 bl 80004f8 <__aeabi_f2d>
|
|
8005b0a: 4602 mov r2, r0
|
|
8005b0c: 460b mov r3, r1
|
|
8005b0e: e9cd 230a strd r2, r3, [sp, #40] @ 0x28
|
|
8005b12: e9cd 4508 strd r4, r5, [sp, #32]
|
|
8005b16: ed97 7b00 vldr d7, [r7]
|
|
8005b1a: ed8d 7b06 vstr d7, [sp, #24]
|
|
8005b1e: ed97 7b02 vldr d7, [r7, #8]
|
|
8005b22: ed8d 7b04 vstr d7, [sp, #16]
|
|
8005b26: e9cd ab02 strd sl, fp, [sp, #8]
|
|
8005b2a: e9cd 8900 strd r8, r9, [sp]
|
|
8005b2e: e9d7 2304 ldrd r2, r3, [r7, #16]
|
|
8005b32: 4805 ldr r0, [pc, #20] @ (8005b48 <calibrate_icm+0x320>)
|
|
8005b34: f014 fb6e bl 801a214 <iprintf>
|
|
}
|
|
8005b38: bf00 nop
|
|
8005b3a: 3758 adds r7, #88 @ 0x58
|
|
8005b3c: 46bd mov sp, r7
|
|
8005b3e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8005b42: bf00 nop
|
|
8005b44: 0801e0e0 .word 0x0801e0e0
|
|
8005b48: 0801e104 .word 0x0801e104
|
|
|
|
08005b4c <configure_and_enable_int_icm>:
|
|
// } else {
|
|
// printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]);
|
|
// }
|
|
//}
|
|
|
|
void configure_and_enable_int_icm (ICM45686_HandleTypeDef *imu) {
|
|
8005b4c: b580 push {r7, lr}
|
|
8005b4e: b084 sub sp, #16
|
|
8005b50: af00 add r7, sp, #0
|
|
8005b52: 6078 str r0, [r7, #4]
|
|
uint8_t tx[2], rx[2] = {0x00, 0x00};
|
|
8005b54: 2300 movs r3, #0
|
|
8005b56: 813b strh r3, [r7, #8]
|
|
|
|
// turn off int
|
|
tx[0] = ICM45686_INT1_CONFIG0;
|
|
8005b58: 2316 movs r3, #22
|
|
8005b5a: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x00;
|
|
8005b5c: 2300 movs r3, #0
|
|
8005b5e: 737b strb r3, [r7, #13]
|
|
HAL_StatusTypeDef status = write_icm(imu, tx, sizeof(tx));
|
|
8005b60: f107 030c add.w r3, r7, #12
|
|
8005b64: 2202 movs r2, #2
|
|
8005b66: 4619 mov r1, r3
|
|
8005b68: 6878 ldr r0, [r7, #4]
|
|
8005b6a: f7ff fd49 bl 8005600 <write_icm>
|
|
8005b6e: 4603 mov r3, r0
|
|
8005b70: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8005b72: 7bfb ldrb r3, [r7, #15]
|
|
8005b74: 2b00 cmp r3, #0
|
|
8005b76: d004 beq.n 8005b82 <configure_and_enable_int_icm+0x36>
|
|
printf("Enabling of IMU INT failed: %d\n", status);
|
|
8005b78: 7bfb ldrb r3, [r7, #15]
|
|
8005b7a: 4619 mov r1, r3
|
|
8005b7c: 4842 ldr r0, [pc, #264] @ (8005c88 <configure_and_enable_int_icm+0x13c>)
|
|
8005b7e: f014 fb49 bl 801a214 <iprintf>
|
|
}
|
|
|
|
tx[0] = ICM45686_INT1_CONFIG0 | 0x80;
|
|
8005b82: 2396 movs r3, #150 @ 0x96
|
|
8005b84: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x00;
|
|
8005b86: 2300 movs r3, #0
|
|
8005b88: 737b strb r3, [r7, #13]
|
|
status = read_icm(imu, tx, rx, sizeof(tx));
|
|
8005b8a: f107 0208 add.w r2, r7, #8
|
|
8005b8e: f107 010c add.w r1, r7, #12
|
|
8005b92: 2302 movs r3, #2
|
|
8005b94: 6878 ldr r0, [r7, #4]
|
|
8005b96: f7ff fcef bl 8005578 <read_icm>
|
|
8005b9a: 4603 mov r3, r0
|
|
8005b9c: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8005b9e: 7bfb ldrb r3, [r7, #15]
|
|
8005ba0: 2b00 cmp r3, #0
|
|
8005ba2: d005 beq.n 8005bb0 <configure_and_enable_int_icm+0x64>
|
|
printf("Reading IMU INT1_CONFIG0 failed: %d\n", status);
|
|
8005ba4: 7bfb ldrb r3, [r7, #15]
|
|
8005ba6: 4619 mov r1, r3
|
|
8005ba8: 4838 ldr r0, [pc, #224] @ (8005c8c <configure_and_enable_int_icm+0x140>)
|
|
8005baa: f014 fb33 bl 801a214 <iprintf>
|
|
8005bae: e004 b.n 8005bba <configure_and_enable_int_icm+0x6e>
|
|
} else {
|
|
printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]);
|
|
8005bb0: 7a7b ldrb r3, [r7, #9]
|
|
8005bb2: 4619 mov r1, r3
|
|
8005bb4: 4836 ldr r0, [pc, #216] @ (8005c90 <configure_and_enable_int_icm+0x144>)
|
|
8005bb6: f014 fb2d bl 801a214 <iprintf>
|
|
}
|
|
|
|
// configure int1 to push-pull, pulse, active high
|
|
tx[0] = ICM45686_INT1_CONFIG2;
|
|
8005bba: 2318 movs r3, #24
|
|
8005bbc: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x01;
|
|
8005bbe: 2301 movs r3, #1
|
|
8005bc0: 737b strb r3, [r7, #13]
|
|
status = write_icm(imu, tx, sizeof(tx));
|
|
8005bc2: f107 030c add.w r3, r7, #12
|
|
8005bc6: 2202 movs r2, #2
|
|
8005bc8: 4619 mov r1, r3
|
|
8005bca: 6878 ldr r0, [r7, #4]
|
|
8005bcc: f7ff fd18 bl 8005600 <write_icm>
|
|
8005bd0: 4603 mov r3, r0
|
|
8005bd2: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8005bd4: 7bfb ldrb r3, [r7, #15]
|
|
8005bd6: 2b00 cmp r3, #0
|
|
8005bd8: d004 beq.n 8005be4 <configure_and_enable_int_icm+0x98>
|
|
printf("Configuration of IMU INT failed: %d\n", status);
|
|
8005bda: 7bfb ldrb r3, [r7, #15]
|
|
8005bdc: 4619 mov r1, r3
|
|
8005bde: 482d ldr r0, [pc, #180] @ (8005c94 <configure_and_enable_int_icm+0x148>)
|
|
8005be0: f014 fb18 bl 801a214 <iprintf>
|
|
}
|
|
|
|
tx[0] = ICM45686_INT1_CONFIG2 | 0x80;
|
|
8005be4: 2398 movs r3, #152 @ 0x98
|
|
8005be6: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x00;
|
|
8005be8: 2300 movs r3, #0
|
|
8005bea: 737b strb r3, [r7, #13]
|
|
status = read_icm(imu, tx, rx, sizeof(tx));
|
|
8005bec: f107 0208 add.w r2, r7, #8
|
|
8005bf0: f107 010c add.w r1, r7, #12
|
|
8005bf4: 2302 movs r3, #2
|
|
8005bf6: 6878 ldr r0, [r7, #4]
|
|
8005bf8: f7ff fcbe bl 8005578 <read_icm>
|
|
8005bfc: 4603 mov r3, r0
|
|
8005bfe: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8005c00: 7bfb ldrb r3, [r7, #15]
|
|
8005c02: 2b00 cmp r3, #0
|
|
8005c04: d005 beq.n 8005c12 <configure_and_enable_int_icm+0xc6>
|
|
printf("Reading IMU INT1_CONFIG2 failed: %d\n", status);
|
|
8005c06: 7bfb ldrb r3, [r7, #15]
|
|
8005c08: 4619 mov r1, r3
|
|
8005c0a: 4823 ldr r0, [pc, #140] @ (8005c98 <configure_and_enable_int_icm+0x14c>)
|
|
8005c0c: f014 fb02 bl 801a214 <iprintf>
|
|
8005c10: e004 b.n 8005c1c <configure_and_enable_int_icm+0xd0>
|
|
} else {
|
|
printf("INT1_CONFIG2 read: 0x%02X\n", rx[1]);
|
|
8005c12: 7a7b ldrb r3, [r7, #9]
|
|
8005c14: 4619 mov r1, r3
|
|
8005c16: 4821 ldr r0, [pc, #132] @ (8005c9c <configure_and_enable_int_icm+0x150>)
|
|
8005c18: f014 fafc bl 801a214 <iprintf>
|
|
}
|
|
|
|
// enable int
|
|
tx[0] = ICM45686_INT1_CONFIG0;
|
|
8005c1c: 2316 movs r3, #22
|
|
8005c1e: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x04;
|
|
8005c20: 2304 movs r3, #4
|
|
8005c22: 737b strb r3, [r7, #13]
|
|
status = write_icm(imu, tx, sizeof(tx));
|
|
8005c24: f107 030c add.w r3, r7, #12
|
|
8005c28: 2202 movs r2, #2
|
|
8005c2a: 4619 mov r1, r3
|
|
8005c2c: 6878 ldr r0, [r7, #4]
|
|
8005c2e: f7ff fce7 bl 8005600 <write_icm>
|
|
8005c32: 4603 mov r3, r0
|
|
8005c34: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8005c36: 7bfb ldrb r3, [r7, #15]
|
|
8005c38: 2b00 cmp r3, #0
|
|
8005c3a: d004 beq.n 8005c46 <configure_and_enable_int_icm+0xfa>
|
|
printf("Enabling of IMU INT failed: %d\n", status);
|
|
8005c3c: 7bfb ldrb r3, [r7, #15]
|
|
8005c3e: 4619 mov r1, r3
|
|
8005c40: 4811 ldr r0, [pc, #68] @ (8005c88 <configure_and_enable_int_icm+0x13c>)
|
|
8005c42: f014 fae7 bl 801a214 <iprintf>
|
|
}
|
|
|
|
tx[0] = ICM45686_INT1_CONFIG0 | 0x80;
|
|
8005c46: 2396 movs r3, #150 @ 0x96
|
|
8005c48: 733b strb r3, [r7, #12]
|
|
tx[1] = 0x00;
|
|
8005c4a: 2300 movs r3, #0
|
|
8005c4c: 737b strb r3, [r7, #13]
|
|
status = read_icm(imu, tx, rx, sizeof(tx));
|
|
8005c4e: f107 0208 add.w r2, r7, #8
|
|
8005c52: f107 010c add.w r1, r7, #12
|
|
8005c56: 2302 movs r3, #2
|
|
8005c58: 6878 ldr r0, [r7, #4]
|
|
8005c5a: f7ff fc8d bl 8005578 <read_icm>
|
|
8005c5e: 4603 mov r3, r0
|
|
8005c60: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8005c62: 7bfb ldrb r3, [r7, #15]
|
|
8005c64: 2b00 cmp r3, #0
|
|
8005c66: d005 beq.n 8005c74 <configure_and_enable_int_icm+0x128>
|
|
printf("Reading IMU INT1_CONFIG0 failed: %d\n", status);
|
|
8005c68: 7bfb ldrb r3, [r7, #15]
|
|
8005c6a: 4619 mov r1, r3
|
|
8005c6c: 4807 ldr r0, [pc, #28] @ (8005c8c <configure_and_enable_int_icm+0x140>)
|
|
8005c6e: f014 fad1 bl 801a214 <iprintf>
|
|
} else {
|
|
printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]);
|
|
}
|
|
}
|
|
8005c72: e004 b.n 8005c7e <configure_and_enable_int_icm+0x132>
|
|
printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]);
|
|
8005c74: 7a7b ldrb r3, [r7, #9]
|
|
8005c76: 4619 mov r1, r3
|
|
8005c78: 4805 ldr r0, [pc, #20] @ (8005c90 <configure_and_enable_int_icm+0x144>)
|
|
8005c7a: f014 facb bl 801a214 <iprintf>
|
|
}
|
|
8005c7e: bf00 nop
|
|
8005c80: 3710 adds r7, #16
|
|
8005c82: 46bd mov sp, r7
|
|
8005c84: bd80 pop {r7, pc}
|
|
8005c86: bf00 nop
|
|
8005c88: 0801e160 .word 0x0801e160
|
|
8005c8c: 0801e180 .word 0x0801e180
|
|
8005c90: 0801e1a8 .word 0x0801e1a8
|
|
8005c94: 0801e1c4 .word 0x0801e1c4
|
|
8005c98: 0801e1ec .word 0x0801e1ec
|
|
8005c9c: 0801e214 .word 0x0801e214
|
|
|
|
08005ca0 <bmm_init_DWT>:
|
|
|
|
// BMM350
|
|
void bmm_init_DWT(void){
|
|
8005ca0: b480 push {r7}
|
|
8005ca2: af00 add r7, sp, #0
|
|
// Enable trace and debug block (TRCENA)
|
|
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
|
8005ca4: 4b09 ldr r3, [pc, #36] @ (8005ccc <bmm_init_DWT+0x2c>)
|
|
8005ca6: 68db ldr r3, [r3, #12]
|
|
8005ca8: 4a08 ldr r2, [pc, #32] @ (8005ccc <bmm_init_DWT+0x2c>)
|
|
8005caa: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8005cae: 60d3 str r3, [r2, #12]
|
|
|
|
// Reset cycle counter
|
|
DWT->CYCCNT = 0;
|
|
8005cb0: 4b07 ldr r3, [pc, #28] @ (8005cd0 <bmm_init_DWT+0x30>)
|
|
8005cb2: 2200 movs r2, #0
|
|
8005cb4: 605a str r2, [r3, #4]
|
|
|
|
// Enable the cycle counter
|
|
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
|
|
8005cb6: 4b06 ldr r3, [pc, #24] @ (8005cd0 <bmm_init_DWT+0x30>)
|
|
8005cb8: 681b ldr r3, [r3, #0]
|
|
8005cba: 4a05 ldr r2, [pc, #20] @ (8005cd0 <bmm_init_DWT+0x30>)
|
|
8005cbc: f043 0301 orr.w r3, r3, #1
|
|
8005cc0: 6013 str r3, [r2, #0]
|
|
}
|
|
8005cc2: bf00 nop
|
|
8005cc4: 46bd mov sp, r7
|
|
8005cc6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005cca: 4770 bx lr
|
|
8005ccc: e000edf0 .word 0xe000edf0
|
|
8005cd0: e0001000 .word 0xe0001000
|
|
|
|
08005cd4 <bmm350_i2c_read>:
|
|
|
|
BMM350_INTF_RET_TYPE bmm350_i2c_read(uint8_t reg_addr, uint8_t *reg_data, uint32_t length, void *intf_ptr){
|
|
8005cd4: b580 push {r7, lr}
|
|
8005cd6: b088 sub sp, #32
|
|
8005cd8: af02 add r7, sp, #8
|
|
8005cda: 60b9 str r1, [r7, #8]
|
|
8005cdc: 607a str r2, [r7, #4]
|
|
8005cde: 603b str r3, [r7, #0]
|
|
8005ce0: 4603 mov r3, r0
|
|
8005ce2: 73fb strb r3, [r7, #15]
|
|
// Extract I2C device address from intf_ptr
|
|
uint8_t device_addr = *(uint8_t*)intf_ptr;
|
|
8005ce4: 683b ldr r3, [r7, #0]
|
|
8005ce6: 781b ldrb r3, [r3, #0]
|
|
8005ce8: 75fb strb r3, [r7, #23]
|
|
|
|
// STM32 HAL: Write register address, then read data
|
|
// Device address is left-shifted by 1 for STM32 HAL
|
|
// if (HAL_I2C_Mem_Read(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, reg_data, length, HAL_I2C_TIMEOUT ) == HAL_OK) {
|
|
if (HAL_I2C_Mem_Read_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, reg_data, length) == HAL_OK) {
|
|
8005cea: 7dfb ldrb r3, [r7, #23]
|
|
8005cec: b29b uxth r3, r3
|
|
8005cee: 005b lsls r3, r3, #1
|
|
8005cf0: b299 uxth r1, r3
|
|
8005cf2: 7bfb ldrb r3, [r7, #15]
|
|
8005cf4: b29a uxth r2, r3
|
|
8005cf6: 687b ldr r3, [r7, #4]
|
|
8005cf8: b29b uxth r3, r3
|
|
8005cfa: 9301 str r3, [sp, #4]
|
|
8005cfc: 68bb ldr r3, [r7, #8]
|
|
8005cfe: 9300 str r3, [sp, #0]
|
|
8005d00: 2301 movs r3, #1
|
|
8005d02: 480b ldr r0, [pc, #44] @ (8005d30 <bmm350_i2c_read+0x5c>)
|
|
8005d04: f001 fe3a bl 800797c <HAL_I2C_Mem_Read_DMA>
|
|
8005d08: 4603 mov r3, r0
|
|
8005d0a: 2b00 cmp r3, #0
|
|
8005d0c: d109 bne.n 8005d22 <bmm350_i2c_read+0x4e>
|
|
// if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) {
|
|
if (ulTaskNotifyTakeIndexed(BMM_NOTIFY_DMA, pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) {
|
|
8005d0e: 220a movs r2, #10
|
|
8005d10: 2101 movs r1, #1
|
|
8005d12: 2001 movs r0, #1
|
|
8005d14: f010 ff0e bl 8016b34 <ulTaskGenericNotifyTake>
|
|
8005d18: 4603 mov r3, r0
|
|
8005d1a: 2b01 cmp r3, #1
|
|
8005d1c: d101 bne.n 8005d22 <bmm350_i2c_read+0x4e>
|
|
// if (ulTaskNotifyTakeIndexed(pdTRUE, BMM_NOTIFY_DMA, pdMS_TO_TICKS(10)) == pdTRUE) {
|
|
return BMM350_INTF_RET_SUCCESS; // 0
|
|
8005d1e: 2300 movs r3, #0
|
|
8005d20: e001 b.n 8005d26 <bmm350_i2c_read+0x52>
|
|
}
|
|
}
|
|
return -1; // Communication failure
|
|
8005d22: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
|
|
}
|
|
8005d26: 4618 mov r0, r3
|
|
8005d28: 3718 adds r7, #24
|
|
8005d2a: 46bd mov sp, r7
|
|
8005d2c: bd80 pop {r7, pc}
|
|
8005d2e: bf00 nop
|
|
8005d30: 200003b4 .word 0x200003b4
|
|
|
|
08005d34 <bmm350_i2c_write>:
|
|
// }
|
|
//
|
|
// return -1; // Communication failure
|
|
//}
|
|
|
|
BMM350_INTF_RET_TYPE bmm350_i2c_write(uint8_t reg_addr, const uint8_t *reg_data, uint32_t length, void *intf_ptr){
|
|
8005d34: b580 push {r7, lr}
|
|
8005d36: b088 sub sp, #32
|
|
8005d38: af02 add r7, sp, #8
|
|
8005d3a: 60b9 str r1, [r7, #8]
|
|
8005d3c: 607a str r2, [r7, #4]
|
|
8005d3e: 603b str r3, [r7, #0]
|
|
8005d40: 4603 mov r3, r0
|
|
8005d42: 73fb strb r3, [r7, #15]
|
|
uint8_t device_addr = *(uint8_t*)intf_ptr;
|
|
8005d44: 683b ldr r3, [r7, #0]
|
|
8005d46: 781b ldrb r3, [r3, #0]
|
|
8005d48: 75fb strb r3, [r7, #23]
|
|
// uint8_t rslt = HAL_I2C_Mem_Write_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length);
|
|
// printf("rslt write: %d\n", rslt);
|
|
// // STM32 HAL: Write register address + data
|
|
if (HAL_I2C_Mem_Write_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length) == HAL_OK) {
|
|
8005d4a: 7dfb ldrb r3, [r7, #23]
|
|
8005d4c: b29b uxth r3, r3
|
|
8005d4e: 005b lsls r3, r3, #1
|
|
8005d50: b299 uxth r1, r3
|
|
8005d52: 7bfb ldrb r3, [r7, #15]
|
|
8005d54: b29a uxth r2, r3
|
|
8005d56: 687b ldr r3, [r7, #4]
|
|
8005d58: b29b uxth r3, r3
|
|
8005d5a: 9301 str r3, [sp, #4]
|
|
8005d5c: 68bb ldr r3, [r7, #8]
|
|
8005d5e: 9300 str r3, [sp, #0]
|
|
8005d60: 2301 movs r3, #1
|
|
8005d62: 480b ldr r0, [pc, #44] @ (8005d90 <bmm350_i2c_write+0x5c>)
|
|
8005d64: f001 fd24 bl 80077b0 <HAL_I2C_Mem_Write_DMA>
|
|
8005d68: 4603 mov r3, r0
|
|
8005d6a: 2b00 cmp r3, #0
|
|
8005d6c: d109 bne.n 8005d82 <bmm350_i2c_write+0x4e>
|
|
// if (HAL_I2C_Mem_Write(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length, HAL_I2C_TIMEOUT ) == HAL_OK) {
|
|
// if (rslt == HAL_OK) {
|
|
// if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) {
|
|
if (ulTaskNotifyTakeIndexed(BMM_NOTIFY_DMA, pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) {
|
|
8005d6e: 220a movs r2, #10
|
|
8005d70: 2101 movs r1, #1
|
|
8005d72: 2001 movs r0, #1
|
|
8005d74: f010 fede bl 8016b34 <ulTaskGenericNotifyTake>
|
|
8005d78: 4603 mov r3, r0
|
|
8005d7a: 2b01 cmp r3, #1
|
|
8005d7c: d101 bne.n 8005d82 <bmm350_i2c_write+0x4e>
|
|
// if (ulTaskNotifyTakeIndexed(pdTRUE, BMM_NOTIFY_DMA, pdMS_TO_TICKS(10)) == pdTRUE) {
|
|
return BMM350_INTF_RET_SUCCESS; // 0
|
|
8005d7e: 2300 movs r3, #0
|
|
8005d80: e001 b.n 8005d86 <bmm350_i2c_write+0x52>
|
|
}
|
|
}
|
|
return -1;
|
|
8005d82: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
8005d86: 4618 mov r0, r3
|
|
8005d88: 3718 adds r7, #24
|
|
8005d8a: 46bd mov sp, r7
|
|
8005d8c: bd80 pop {r7, pc}
|
|
8005d8e: bf00 nop
|
|
8005d90: 200003b4 .word 0x200003b4
|
|
|
|
08005d94 <bmm350_delay>:
|
|
// }
|
|
//
|
|
// return -1;
|
|
//}
|
|
|
|
void bmm350_delay(uint32_t period_us, void *intf_ptr){
|
|
8005d94: b480 push {r7}
|
|
8005d96: b085 sub sp, #20
|
|
8005d98: af00 add r7, sp, #0
|
|
8005d9a: 6078 str r0, [r7, #4]
|
|
8005d9c: 6039 str r1, [r7, #0]
|
|
(void)intf_ptr; // Unused
|
|
|
|
// For STM32, use DWT cycle counter for accurate microsecond delays
|
|
uint32_t start = DWT->CYCCNT;
|
|
8005d9e: 4b0e ldr r3, [pc, #56] @ (8005dd8 <bmm350_delay+0x44>)
|
|
8005da0: 685b ldr r3, [r3, #4]
|
|
8005da2: 60fb str r3, [r7, #12]
|
|
uint32_t cycles = period_us * (SystemCoreClock / 1000000);
|
|
8005da4: 4b0d ldr r3, [pc, #52] @ (8005ddc <bmm350_delay+0x48>)
|
|
8005da6: 681b ldr r3, [r3, #0]
|
|
8005da8: 4a0d ldr r2, [pc, #52] @ (8005de0 <bmm350_delay+0x4c>)
|
|
8005daa: fba2 2303 umull r2, r3, r2, r3
|
|
8005dae: 0c9a lsrs r2, r3, #18
|
|
8005db0: 687b ldr r3, [r7, #4]
|
|
8005db2: fb02 f303 mul.w r3, r2, r3
|
|
8005db6: 60bb str r3, [r7, #8]
|
|
|
|
while ((DWT->CYCCNT - start) < cycles);
|
|
8005db8: bf00 nop
|
|
8005dba: 4b07 ldr r3, [pc, #28] @ (8005dd8 <bmm350_delay+0x44>)
|
|
8005dbc: 685a ldr r2, [r3, #4]
|
|
8005dbe: 68fb ldr r3, [r7, #12]
|
|
8005dc0: 1ad3 subs r3, r2, r3
|
|
8005dc2: 68ba ldr r2, [r7, #8]
|
|
8005dc4: 429a cmp r2, r3
|
|
8005dc6: d8f8 bhi.n 8005dba <bmm350_delay+0x26>
|
|
}
|
|
8005dc8: bf00 nop
|
|
8005dca: bf00 nop
|
|
8005dcc: 3714 adds r7, #20
|
|
8005dce: 46bd mov sp, r7
|
|
8005dd0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005dd4: 4770 bx lr
|
|
8005dd6: bf00 nop
|
|
8005dd8: e0001000 .word 0xe0001000
|
|
8005ddc: 2000000c .word 0x2000000c
|
|
8005de0: 431bde83 .word 0x431bde83
|
|
|
|
08005de4 <init_bmm>:
|
|
|
|
// Initialization function
|
|
int8_t init_bmm(struct bmm350_dev *dev) {
|
|
8005de4: b580 push {r7, lr}
|
|
8005de6: b084 sub sp, #16
|
|
8005de8: af00 add r7, sp, #0
|
|
8005dea: 6078 str r0, [r7, #4]
|
|
|
|
// Static variable to hold I2C device address
|
|
// Must be static or global because dev.intf_ptr will point to it
|
|
static uint8_t dev_addr = BMM350_I2C_ADSEL_SET_LOW;
|
|
// Assign function pointers
|
|
dev->read = bmm350_i2c_read;
|
|
8005dec: 687b ldr r3, [r7, #4]
|
|
8005dee: 4a21 ldr r2, [pc, #132] @ (8005e74 <init_bmm+0x90>)
|
|
8005df0: 609a str r2, [r3, #8]
|
|
dev->write = bmm350_i2c_write;
|
|
8005df2: 687b ldr r3, [r7, #4]
|
|
8005df4: 4a20 ldr r2, [pc, #128] @ (8005e78 <init_bmm+0x94>)
|
|
8005df6: 60da str r2, [r3, #12]
|
|
dev->delay_us = bmm350_delay;
|
|
8005df8: 687b ldr r3, [r7, #4]
|
|
8005dfa: 4a20 ldr r2, [pc, #128] @ (8005e7c <init_bmm+0x98>)
|
|
8005dfc: 611a str r2, [r3, #16]
|
|
dev->intf_ptr = &dev_addr;
|
|
8005dfe: 687b ldr r3, [r7, #4]
|
|
8005e00: 4a1f ldr r2, [pc, #124] @ (8005e80 <init_bmm+0x9c>)
|
|
8005e02: 601a str r2, [r3, #0]
|
|
|
|
// printf("Starting up and configuring BMM350\n");
|
|
|
|
// Initialize BMM350 driver
|
|
rslt = bmm350_init(dev);
|
|
8005e04: 6878 ldr r0, [r7, #4]
|
|
8005e06: f7fc fc68 bl 80026da <bmm350_init>
|
|
8005e0a: 4603 mov r3, r0
|
|
8005e0c: 73fb strb r3, [r7, #15]
|
|
if (rslt != BMM350_OK)
|
|
8005e0e: f997 300f ldrsb.w r3, [r7, #15]
|
|
8005e12: 2b00 cmp r3, #0
|
|
8005e14: d002 beq.n 8005e1c <init_bmm+0x38>
|
|
{
|
|
// Handle error: chip ID mismatch, communication failure, etc.
|
|
return rslt;
|
|
8005e16: f997 300f ldrsb.w r3, [r7, #15]
|
|
8005e1a: e027 b.n 8005e6c <init_bmm+0x88>
|
|
}
|
|
printf("Initialization: %d\n", rslt);
|
|
8005e1c: f997 300f ldrsb.w r3, [r7, #15]
|
|
8005e20: 4619 mov r1, r3
|
|
8005e22: 4818 ldr r0, [pc, #96] @ (8005e84 <init_bmm+0xa0>)
|
|
8005e24: f014 f9f6 bl 801a214 <iprintf>
|
|
printf("CHIP_ID (should be 0x33) - Read Register: 0x00 BMM350 Chip ID: 0x%X\n", dev->chip_id);
|
|
8005e28: 687b ldr r3, [r7, #4]
|
|
8005e2a: 791b ldrb r3, [r3, #4]
|
|
8005e2c: 4619 mov r1, r3
|
|
8005e2e: 4816 ldr r0, [pc, #88] @ (8005e88 <init_bmm+0xa4>)
|
|
8005e30: f014 f9f0 bl 801a214 <iprintf>
|
|
|
|
// Set powermode, odr and avg
|
|
rslt = bmm350_set_powermode(BMM350_NORMAL_MODE, dev);
|
|
8005e34: 6879 ldr r1, [r7, #4]
|
|
8005e36: 2001 movs r0, #1
|
|
8005e38: f7fc fd7e bl 8002938 <bmm350_set_powermode>
|
|
8005e3c: 4603 mov r3, r0
|
|
8005e3e: 73fb strb r3, [r7, #15]
|
|
printf("Powermode (%d): %d\n", BMM350_NORMAL_MODE, rslt);
|
|
8005e40: f997 300f ldrsb.w r3, [r7, #15]
|
|
8005e44: 461a mov r2, r3
|
|
8005e46: 2101 movs r1, #1
|
|
8005e48: 4810 ldr r0, [pc, #64] @ (8005e8c <init_bmm+0xa8>)
|
|
8005e4a: f014 f9e3 bl 801a214 <iprintf>
|
|
rslt = bmm350_set_odr_performance(BMM350_DATA_RATE_400HZ, BMM350_NO_AVERAGING, dev);
|
|
8005e4e: 687a ldr r2, [r7, #4]
|
|
8005e50: 2100 movs r1, #0
|
|
8005e52: 2002 movs r0, #2
|
|
8005e54: f7fc fdc2 bl 80029dc <bmm350_set_odr_performance>
|
|
8005e58: 4603 mov r3, r0
|
|
8005e5a: 73fb strb r3, [r7, #15]
|
|
printf("ODR(%d) and AVG(%d): %d\n", BMM350_DATA_RATE_400HZ, BMM350_NO_AVERAGING, rslt);
|
|
8005e5c: f997 300f ldrsb.w r3, [r7, #15]
|
|
8005e60: 2200 movs r2, #0
|
|
8005e62: 2102 movs r1, #2
|
|
8005e64: 480a ldr r0, [pc, #40] @ (8005e90 <init_bmm+0xac>)
|
|
8005e66: f014 f9d5 bl 801a214 <iprintf>
|
|
// rslt = bmm350_enable_interrupt(BMM350_ENABLE_INTERRUPT, dev);
|
|
// printf("Interrupt enable: %d", rslt);
|
|
// rslt = bmm350_configure_interrupt(BMM350_LATCHED, BMM350_ACTIVE_HIGH, BMM350_INTR_OPEN_DRAIN, BMM350_MAP_TO_PIN, dev);
|
|
// printf("Configure interrupt: %d", rslt);
|
|
|
|
return BMM350_OK;
|
|
8005e6a: 2300 movs r3, #0
|
|
}
|
|
8005e6c: 4618 mov r0, r3
|
|
8005e6e: 3710 adds r7, #16
|
|
8005e70: 46bd mov sp, r7
|
|
8005e72: bd80 pop {r7, pc}
|
|
8005e74: 08005cd5 .word 0x08005cd5
|
|
8005e78: 08005d35 .word 0x08005d35
|
|
8005e7c: 08005d95 .word 0x08005d95
|
|
8005e80: 20000008 .word 0x20000008
|
|
8005e84: 0801e230 .word 0x0801e230
|
|
8005e88: 0801e244 .word 0x0801e244
|
|
8005e8c: 0801e28c .word 0x0801e28c
|
|
8005e90: 0801e2a0 .word 0x0801e2a0
|
|
|
|
08005e94 <bmm_configure_interrupt>:
|
|
|
|
int8_t bmm_configure_interrupt (struct bmm350_dev *dev) {
|
|
8005e94: b580 push {r7, lr}
|
|
8005e96: b086 sub sp, #24
|
|
8005e98: af02 add r7, sp, #8
|
|
8005e9a: 6078 str r0, [r7, #4]
|
|
int8_t rslt;
|
|
rslt = bmm350_enable_interrupt(BMM350_ENABLE_INTERRUPT, dev);
|
|
8005e9c: 6879 ldr r1, [r7, #4]
|
|
8005e9e: 2001 movs r0, #1
|
|
8005ea0: f7fc fe09 bl 8002ab6 <bmm350_enable_interrupt>
|
|
8005ea4: 4603 mov r3, r0
|
|
8005ea6: 73fb strb r3, [r7, #15]
|
|
printf("Interrupt enable: %d \n", rslt);
|
|
8005ea8: f997 300f ldrsb.w r3, [r7, #15]
|
|
8005eac: 4619 mov r1, r3
|
|
8005eae: 480c ldr r0, [pc, #48] @ (8005ee0 <bmm_configure_interrupt+0x4c>)
|
|
8005eb0: f014 f9b0 bl 801a214 <iprintf>
|
|
rslt = bmm350_configure_interrupt(BMM350_PULSED, BMM350_ACTIVE_HIGH, BMM350_INTR_PUSH_PULL, BMM350_MAP_TO_PIN, dev);
|
|
8005eb4: 687b ldr r3, [r7, #4]
|
|
8005eb6: 9300 str r3, [sp, #0]
|
|
8005eb8: 2301 movs r3, #1
|
|
8005eba: 2201 movs r2, #1
|
|
8005ebc: 2101 movs r1, #1
|
|
8005ebe: 2000 movs r0, #0
|
|
8005ec0: f7fc fe2a bl 8002b18 <bmm350_configure_interrupt>
|
|
8005ec4: 4603 mov r3, r0
|
|
8005ec6: 73fb strb r3, [r7, #15]
|
|
printf("Configure interrupt: %d \n", rslt);
|
|
8005ec8: f997 300f ldrsb.w r3, [r7, #15]
|
|
8005ecc: 4619 mov r1, r3
|
|
8005ece: 4805 ldr r0, [pc, #20] @ (8005ee4 <bmm_configure_interrupt+0x50>)
|
|
8005ed0: f014 f9a0 bl 801a214 <iprintf>
|
|
|
|
return BMM350_OK;
|
|
8005ed4: 2300 movs r3, #0
|
|
}
|
|
8005ed6: 4618 mov r0, r3
|
|
8005ed8: 3710 adds r7, #16
|
|
8005eda: 46bd mov sp, r7
|
|
8005edc: bd80 pop {r7, pc}
|
|
8005ede: bf00 nop
|
|
8005ee0: 0801e2bc .word 0x0801e2bc
|
|
8005ee4: 0801e2d4 .word 0x0801e2d4
|
|
|
|
08005ee8 <LL_RCC_EnableRTC>:
|
|
* @brief Enable RTC
|
|
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_EnableRTC(void)
|
|
{
|
|
8005ee8: b480 push {r7}
|
|
8005eea: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
|
|
8005eec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005ef0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005ef4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8005ef8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8005efc: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
8005f00: bf00 nop
|
|
8005f02: 46bd mov sp, r7
|
|
8005f04: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f08: 4770 bx lr
|
|
|
|
08005f0a <LL_AHB2_GRP1_EnableClock>:
|
|
{
|
|
8005f0a: b480 push {r7}
|
|
8005f0c: b085 sub sp, #20
|
|
8005f0e: af00 add r7, sp, #0
|
|
8005f10: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->AHB2ENR, Periphs);
|
|
8005f12: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005f16: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8005f18: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8005f1c: 687b ldr r3, [r7, #4]
|
|
8005f1e: 4313 orrs r3, r2
|
|
8005f20: 64cb str r3, [r1, #76] @ 0x4c
|
|
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
|
|
8005f22: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005f26: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8005f28: 687b ldr r3, [r7, #4]
|
|
8005f2a: 4013 ands r3, r2
|
|
8005f2c: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8005f2e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8005f30: bf00 nop
|
|
8005f32: 3714 adds r7, #20
|
|
8005f34: 46bd mov sp, r7
|
|
8005f36: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f3a: 4770 bx lr
|
|
|
|
08005f3c <LL_AHB3_GRP1_EnableClock>:
|
|
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
|
|
* @note (*) Not supported by all the devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
8005f3c: b480 push {r7}
|
|
8005f3e: b085 sub sp, #20
|
|
8005f40: af00 add r7, sp, #0
|
|
8005f42: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->AHB3ENR, Periphs);
|
|
8005f44: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005f48: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
8005f4a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8005f4e: 687b ldr r3, [r7, #4]
|
|
8005f50: 4313 orrs r3, r2
|
|
8005f52: 650b str r3, [r1, #80] @ 0x50
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
|
|
8005f54: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005f58: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
8005f5a: 687b ldr r3, [r7, #4]
|
|
8005f5c: 4013 ands r3, r2
|
|
8005f5e: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8005f60: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8005f62: bf00 nop
|
|
8005f64: 3714 adds r7, #20
|
|
8005f66: 46bd mov sp, r7
|
|
8005f68: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f6c: 4770 bx lr
|
|
|
|
08005f6e <LL_APB1_GRP1_EnableClock>:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
|
|
* @note (*) Not supported by all the devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
8005f6e: b480 push {r7}
|
|
8005f70: b085 sub sp, #20
|
|
8005f72: af00 add r7, sp, #0
|
|
8005f74: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APB1ENR1, Periphs);
|
|
8005f76: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005f7a: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8005f7c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8005f80: 687b ldr r3, [r7, #4]
|
|
8005f82: 4313 orrs r3, r2
|
|
8005f84: 658b str r3, [r1, #88] @ 0x58
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
|
|
8005f86: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005f8a: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8005f8c: 687b ldr r3, [r7, #4]
|
|
8005f8e: 4013 ands r3, r2
|
|
8005f90: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8005f92: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8005f94: bf00 nop
|
|
8005f96: 3714 adds r7, #20
|
|
8005f98: 46bd mov sp, r7
|
|
8005f9a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f9e: 4770 bx lr
|
|
|
|
08005fa0 <LL_APB2_GRP1_EnableClock>:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
|
|
* @note (*) Not supported by all the devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
8005fa0: b480 push {r7}
|
|
8005fa2: b085 sub sp, #20
|
|
8005fa4: af00 add r7, sp, #0
|
|
8005fa6: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APB2ENR, Periphs);
|
|
8005fa8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005fac: 6e1a ldr r2, [r3, #96] @ 0x60
|
|
8005fae: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8005fb2: 687b ldr r3, [r7, #4]
|
|
8005fb4: 4313 orrs r3, r2
|
|
8005fb6: 660b str r3, [r1, #96] @ 0x60
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
|
|
8005fb8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8005fbc: 6e1a ldr r2, [r3, #96] @ 0x60
|
|
8005fbe: 687b ldr r3, [r7, #4]
|
|
8005fc0: 4013 ands r3, r2
|
|
8005fc2: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8005fc4: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8005fc6: bf00 nop
|
|
8005fc8: 3714 adds r7, #20
|
|
8005fca: 46bd mov sp, r7
|
|
8005fcc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005fd0: 4770 bx lr
|
|
...
|
|
|
|
08005fd4 <LL_SYSCFG_EnableFastModePlus>:
|
|
{
|
|
8005fd4: b480 push {r7}
|
|
8005fd6: b083 sub sp, #12
|
|
8005fd8: af00 add r7, sp, #0
|
|
8005fda: 6078 str r0, [r7, #4]
|
|
SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
|
|
8005fdc: 4b05 ldr r3, [pc, #20] @ (8005ff4 <LL_SYSCFG_EnableFastModePlus+0x20>)
|
|
8005fde: 685a ldr r2, [r3, #4]
|
|
8005fe0: 4904 ldr r1, [pc, #16] @ (8005ff4 <LL_SYSCFG_EnableFastModePlus+0x20>)
|
|
8005fe2: 687b ldr r3, [r7, #4]
|
|
8005fe4: 4313 orrs r3, r2
|
|
8005fe6: 604b str r3, [r1, #4]
|
|
}
|
|
8005fe8: bf00 nop
|
|
8005fea: 370c adds r7, #12
|
|
8005fec: 46bd mov sp, r7
|
|
8005fee: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005ff2: 4770 bx lr
|
|
8005ff4: 40010000 .word 0x40010000
|
|
|
|
08005ff8 <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8005ff8: b580 push {r7, lr}
|
|
8005ffa: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_HSEM_CLK_ENABLE();
|
|
8005ffc: f44f 2000 mov.w r0, #524288 @ 0x80000
|
|
8006000: f7ff ff9c bl 8005f3c <LL_AHB3_GRP1_EnableClock>
|
|
HAL_PWREx_EnableVddUSB();
|
|
8006004: f004 ffba bl 800af7c <HAL_PWREx_EnableVddUSB>
|
|
|
|
/* System interrupt init*/
|
|
/* PendSV_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
|
|
8006008: 2200 movs r2, #0
|
|
800600a: 210f movs r1, #15
|
|
800600c: f06f 0001 mvn.w r0, #1
|
|
8006010: f000 fddc bl 8006bcc <HAL_NVIC_SetPriority>
|
|
|
|
/* Peripheral interrupt init */
|
|
/* HSEM_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(HSEM_IRQn, 5, 0);
|
|
8006014: 2200 movs r2, #0
|
|
8006016: 2105 movs r1, #5
|
|
8006018: 202e movs r0, #46 @ 0x2e
|
|
800601a: f000 fdd7 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(HSEM_IRQn);
|
|
800601e: 202e movs r0, #46 @ 0x2e
|
|
8006020: f000 fdee bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8006024: bf00 nop
|
|
8006026: bd80 pop {r7, pc}
|
|
|
|
08006028 <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8006028: b580 push {r7, lr}
|
|
800602a: b09c sub sp, #112 @ 0x70
|
|
800602c: af00 add r7, sp, #0
|
|
800602e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8006030: f107 035c add.w r3, r7, #92 @ 0x5c
|
|
8006034: 2200 movs r2, #0
|
|
8006036: 601a str r2, [r3, #0]
|
|
8006038: 605a str r2, [r3, #4]
|
|
800603a: 609a str r2, [r3, #8]
|
|
800603c: 60da str r2, [r3, #12]
|
|
800603e: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8006040: f107 030c add.w r3, r7, #12
|
|
8006044: 2250 movs r2, #80 @ 0x50
|
|
8006046: 2100 movs r1, #0
|
|
8006048: 4618 mov r0, r3
|
|
800604a: f014 f95b bl 801a304 <memset>
|
|
if(hi2c->Instance==I2C1)
|
|
800604e: 687b ldr r3, [r7, #4]
|
|
8006050: 681b ldr r3, [r3, #0]
|
|
8006052: 4a4d ldr r2, [pc, #308] @ (8006188 <HAL_I2C_MspInit+0x160>)
|
|
8006054: 4293 cmp r3, r2
|
|
8006056: f040 8093 bne.w 8006180 <HAL_I2C_MspInit+0x158>
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
|
|
800605a: 2304 movs r3, #4
|
|
800605c: 60fb str r3, [r7, #12]
|
|
PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
|
|
800605e: f44f 3340 mov.w r3, #196608 @ 0x30000
|
|
8006062: 62fb str r3, [r7, #44] @ 0x2c
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8006064: f107 030c add.w r3, r7, #12
|
|
8006068: 4618 mov r0, r3
|
|
800606a: f006 faf5 bl 800c658 <HAL_RCCEx_PeriphCLKConfig>
|
|
800606e: 4603 mov r3, r0
|
|
8006070: 2b00 cmp r3, #0
|
|
8006072: d001 beq.n 8006078 <HAL_I2C_MspInit+0x50>
|
|
{
|
|
Error_Handler();
|
|
8006074: f7ff f97e bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8006078: 2002 movs r0, #2
|
|
800607a: f7ff ff46 bl 8005f0a <LL_AHB2_GRP1_EnableClock>
|
|
/**I2C1 GPIO Configuration
|
|
PB8 ------> I2C1_SCL
|
|
PB9 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
|
|
800607e: f44f 7340 mov.w r3, #768 @ 0x300
|
|
8006082: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8006084: 2312 movs r3, #18
|
|
8006086: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8006088: 2300 movs r3, #0
|
|
800608a: 667b str r3, [r7, #100] @ 0x64
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800608c: 2303 movs r3, #3
|
|
800608e: 66bb str r3, [r7, #104] @ 0x68
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
8006090: 2304 movs r3, #4
|
|
8006092: 66fb str r3, [r7, #108] @ 0x6c
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8006094: f107 035c add.w r3, r7, #92 @ 0x5c
|
|
8006098: 4619 mov r1, r3
|
|
800609a: 483c ldr r0, [pc, #240] @ (800618c <HAL_I2C_MspInit+0x164>)
|
|
800609c: f001 f928 bl 80072f0 <HAL_GPIO_Init>
|
|
|
|
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(SYSCFG_FASTMODEPLUS_PB8);
|
|
80060a0: f44f 2080 mov.w r0, #262144 @ 0x40000
|
|
80060a4: f7ff ff96 bl 8005fd4 <LL_SYSCFG_EnableFastModePlus>
|
|
|
|
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(SYSCFG_FASTMODEPLUS_PB9);
|
|
80060a8: f44f 2000 mov.w r0, #524288 @ 0x80000
|
|
80060ac: f7ff ff92 bl 8005fd4 <LL_SYSCFG_EnableFastModePlus>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
80060b0: f44f 1000 mov.w r0, #2097152 @ 0x200000
|
|
80060b4: f7ff ff5b bl 8005f6e <LL_APB1_GRP1_EnableClock>
|
|
|
|
/* I2C1 DMA Init */
|
|
/* I2C1_TX Init */
|
|
hdma_i2c1_tx.Instance = DMA1_Channel3;
|
|
80060b8: 4b35 ldr r3, [pc, #212] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060ba: 4a36 ldr r2, [pc, #216] @ (8006194 <HAL_I2C_MspInit+0x16c>)
|
|
80060bc: 601a str r2, [r3, #0]
|
|
hdma_i2c1_tx.Init.Request = DMA_REQUEST_I2C1_TX;
|
|
80060be: 4b34 ldr r3, [pc, #208] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060c0: 220b movs r2, #11
|
|
80060c2: 605a str r2, [r3, #4]
|
|
hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
80060c4: 4b32 ldr r3, [pc, #200] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060c6: 2210 movs r2, #16
|
|
80060c8: 609a str r2, [r3, #8]
|
|
hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
80060ca: 4b31 ldr r3, [pc, #196] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060cc: 2200 movs r2, #0
|
|
80060ce: 60da str r2, [r3, #12]
|
|
hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
80060d0: 4b2f ldr r3, [pc, #188] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060d2: 2280 movs r2, #128 @ 0x80
|
|
80060d4: 611a str r2, [r3, #16]
|
|
hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
80060d6: 4b2e ldr r3, [pc, #184] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060d8: 2200 movs r2, #0
|
|
80060da: 615a str r2, [r3, #20]
|
|
hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
80060dc: 4b2c ldr r3, [pc, #176] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060de: 2200 movs r2, #0
|
|
80060e0: 619a str r2, [r3, #24]
|
|
hdma_i2c1_tx.Init.Mode = DMA_NORMAL;
|
|
80060e2: 4b2b ldr r3, [pc, #172] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060e4: 2200 movs r2, #0
|
|
80060e6: 61da str r2, [r3, #28]
|
|
hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_HIGH;
|
|
80060e8: 4b29 ldr r3, [pc, #164] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060ea: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
80060ee: 621a str r2, [r3, #32]
|
|
if (HAL_DMA_Init(&hdma_i2c1_tx) != HAL_OK)
|
|
80060f0: 4827 ldr r0, [pc, #156] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
80060f2: f000 fdbd bl 8006c70 <HAL_DMA_Init>
|
|
80060f6: 4603 mov r3, r0
|
|
80060f8: 2b00 cmp r3, #0
|
|
80060fa: d001 beq.n 8006100 <HAL_I2C_MspInit+0xd8>
|
|
{
|
|
Error_Handler();
|
|
80060fc: f7ff f93a bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(hi2c,hdmatx,hdma_i2c1_tx);
|
|
8006100: 687b ldr r3, [r7, #4]
|
|
8006102: 4a23 ldr r2, [pc, #140] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
8006104: 639a str r2, [r3, #56] @ 0x38
|
|
8006106: 4a22 ldr r2, [pc, #136] @ (8006190 <HAL_I2C_MspInit+0x168>)
|
|
8006108: 687b ldr r3, [r7, #4]
|
|
800610a: 6293 str r3, [r2, #40] @ 0x28
|
|
|
|
/* I2C1_RX Init */
|
|
hdma_i2c1_rx.Instance = DMA1_Channel4;
|
|
800610c: 4b22 ldr r3, [pc, #136] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
800610e: 4a23 ldr r2, [pc, #140] @ (800619c <HAL_I2C_MspInit+0x174>)
|
|
8006110: 601a str r2, [r3, #0]
|
|
hdma_i2c1_rx.Init.Request = DMA_REQUEST_I2C1_RX;
|
|
8006112: 4b21 ldr r3, [pc, #132] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
8006114: 220a movs r2, #10
|
|
8006116: 605a str r2, [r3, #4]
|
|
hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8006118: 4b1f ldr r3, [pc, #124] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
800611a: 2200 movs r2, #0
|
|
800611c: 609a str r2, [r3, #8]
|
|
hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
800611e: 4b1e ldr r3, [pc, #120] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
8006120: 2200 movs r2, #0
|
|
8006122: 60da str r2, [r3, #12]
|
|
hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8006124: 4b1c ldr r3, [pc, #112] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
8006126: 2280 movs r2, #128 @ 0x80
|
|
8006128: 611a str r2, [r3, #16]
|
|
hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
800612a: 4b1b ldr r3, [pc, #108] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
800612c: 2200 movs r2, #0
|
|
800612e: 615a str r2, [r3, #20]
|
|
hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8006130: 4b19 ldr r3, [pc, #100] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
8006132: 2200 movs r2, #0
|
|
8006134: 619a str r2, [r3, #24]
|
|
hdma_i2c1_rx.Init.Mode = DMA_NORMAL;
|
|
8006136: 4b18 ldr r3, [pc, #96] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
8006138: 2200 movs r2, #0
|
|
800613a: 61da str r2, [r3, #28]
|
|
hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
|
800613c: 4b16 ldr r3, [pc, #88] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
800613e: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
8006142: 621a str r2, [r3, #32]
|
|
if (HAL_DMA_Init(&hdma_i2c1_rx) != HAL_OK)
|
|
8006144: 4814 ldr r0, [pc, #80] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
8006146: f000 fd93 bl 8006c70 <HAL_DMA_Init>
|
|
800614a: 4603 mov r3, r0
|
|
800614c: 2b00 cmp r3, #0
|
|
800614e: d001 beq.n 8006154 <HAL_I2C_MspInit+0x12c>
|
|
{
|
|
Error_Handler();
|
|
8006150: f7ff f910 bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(hi2c,hdmarx,hdma_i2c1_rx);
|
|
8006154: 687b ldr r3, [r7, #4]
|
|
8006156: 4a10 ldr r2, [pc, #64] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
8006158: 63da str r2, [r3, #60] @ 0x3c
|
|
800615a: 4a0f ldr r2, [pc, #60] @ (8006198 <HAL_I2C_MspInit+0x170>)
|
|
800615c: 687b ldr r3, [r7, #4]
|
|
800615e: 6293 str r3, [r2, #40] @ 0x28
|
|
|
|
/* I2C1 interrupt Init */
|
|
HAL_NVIC_SetPriority(I2C1_EV_IRQn, 5, 0);
|
|
8006160: 2200 movs r2, #0
|
|
8006162: 2105 movs r1, #5
|
|
8006164: 201e movs r0, #30
|
|
8006166: f000 fd31 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
|
|
800616a: 201e movs r0, #30
|
|
800616c: f000 fd48 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_SetPriority(I2C1_ER_IRQn, 5, 0);
|
|
8006170: 2200 movs r2, #0
|
|
8006172: 2105 movs r1, #5
|
|
8006174: 201f movs r0, #31
|
|
8006176: f000 fd29 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
|
|
800617a: 201f movs r0, #31
|
|
800617c: f000 fd40 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END I2C1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8006180: bf00 nop
|
|
8006182: 3770 adds r7, #112 @ 0x70
|
|
8006184: 46bd mov sp, r7
|
|
8006186: bd80 pop {r7, pc}
|
|
8006188: 40005400 .word 0x40005400
|
|
800618c: 48000400 .word 0x48000400
|
|
8006190: 20000408 .word 0x20000408
|
|
8006194: 40020030 .word 0x40020030
|
|
8006198: 20000468 .word 0x20000468
|
|
800619c: 40020044 .word 0x40020044
|
|
|
|
080061a0 <HAL_IPCC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hipcc: IPCC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_IPCC_MspInit(IPCC_HandleTypeDef* hipcc)
|
|
{
|
|
80061a0: b580 push {r7, lr}
|
|
80061a2: b082 sub sp, #8
|
|
80061a4: af00 add r7, sp, #0
|
|
80061a6: 6078 str r0, [r7, #4]
|
|
if(hipcc->Instance==IPCC)
|
|
80061a8: 687b ldr r3, [r7, #4]
|
|
80061aa: 681b ldr r3, [r3, #0]
|
|
80061ac: 4a0d ldr r2, [pc, #52] @ (80061e4 <HAL_IPCC_MspInit+0x44>)
|
|
80061ae: 4293 cmp r3, r2
|
|
80061b0: d113 bne.n 80061da <HAL_IPCC_MspInit+0x3a>
|
|
{
|
|
/* USER CODE BEGIN IPCC_MspInit 0 */
|
|
|
|
/* USER CODE END IPCC_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_IPCC_CLK_ENABLE();
|
|
80061b2: f44f 1080 mov.w r0, #1048576 @ 0x100000
|
|
80061b6: f7ff fec1 bl 8005f3c <LL_AHB3_GRP1_EnableClock>
|
|
/* IPCC interrupt Init */
|
|
HAL_NVIC_SetPriority(IPCC_C1_RX_IRQn, 5, 0);
|
|
80061ba: 2200 movs r2, #0
|
|
80061bc: 2105 movs r1, #5
|
|
80061be: 202c movs r0, #44 @ 0x2c
|
|
80061c0: f000 fd04 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
|
|
80061c4: 202c movs r0, #44 @ 0x2c
|
|
80061c6: f000 fd1b bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_SetPriority(IPCC_C1_TX_IRQn, 5, 0);
|
|
80061ca: 2200 movs r2, #0
|
|
80061cc: 2105 movs r1, #5
|
|
80061ce: 202d movs r0, #45 @ 0x2d
|
|
80061d0: f000 fcfc bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
|
|
80061d4: 202d movs r0, #45 @ 0x2d
|
|
80061d6: f000 fd13 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END IPCC_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80061da: bf00 nop
|
|
80061dc: 3708 adds r7, #8
|
|
80061de: 46bd mov sp, r7
|
|
80061e0: bd80 pop {r7, pc}
|
|
80061e2: bf00 nop
|
|
80061e4: 58000c00 .word 0x58000c00
|
|
|
|
080061e8 <HAL_RTC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hrtc: RTC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
|
|
{
|
|
80061e8: b580 push {r7, lr}
|
|
80061ea: b096 sub sp, #88 @ 0x58
|
|
80061ec: af00 add r7, sp, #0
|
|
80061ee: 6078 str r0, [r7, #4]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
80061f0: f107 0308 add.w r3, r7, #8
|
|
80061f4: 2250 movs r2, #80 @ 0x50
|
|
80061f6: 2100 movs r1, #0
|
|
80061f8: 4618 mov r0, r3
|
|
80061fa: f014 f883 bl 801a304 <memset>
|
|
if(hrtc->Instance==RTC)
|
|
80061fe: 687b ldr r3, [r7, #4]
|
|
8006200: 681b ldr r3, [r3, #0]
|
|
8006202: 4a13 ldr r2, [pc, #76] @ (8006250 <HAL_RTC_MspInit+0x68>)
|
|
8006204: 4293 cmp r3, r2
|
|
8006206: d11f bne.n 8006248 <HAL_RTC_MspInit+0x60>
|
|
|
|
/* USER CODE END RTC_MspInit 0 */
|
|
|
|
/** Enable access to the backup domain
|
|
*/
|
|
HAL_PWR_EnableBkUpAccess();
|
|
8006208: f004 fe9a bl 800af40 <HAL_PWR_EnableBkUpAccess>
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
|
800620c: f44f 6300 mov.w r3, #2048 @ 0x800
|
|
8006210: 60bb str r3, [r7, #8]
|
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
|
8006212: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8006216: 64bb str r3, [r7, #72] @ 0x48
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8006218: f107 0308 add.w r3, r7, #8
|
|
800621c: 4618 mov r0, r3
|
|
800621e: f006 fa1b bl 800c658 <HAL_RCCEx_PeriphCLKConfig>
|
|
8006222: 4603 mov r3, r0
|
|
8006224: 2b00 cmp r3, #0
|
|
8006226: d001 beq.n 800622c <HAL_RTC_MspInit+0x44>
|
|
{
|
|
Error_Handler();
|
|
8006228: f7ff f8a4 bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_RTC_ENABLE();
|
|
800622c: f7ff fe5c bl 8005ee8 <LL_RCC_EnableRTC>
|
|
__HAL_RCC_RTCAPB_CLK_ENABLE();
|
|
8006230: f44f 6080 mov.w r0, #1024 @ 0x400
|
|
8006234: f7ff fe9b bl 8005f6e <LL_APB1_GRP1_EnableClock>
|
|
/* RTC interrupt Init */
|
|
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 5, 0);
|
|
8006238: 2200 movs r2, #0
|
|
800623a: 2105 movs r1, #5
|
|
800623c: 2003 movs r0, #3
|
|
800623e: f000 fcc5 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
|
|
8006242: 2003 movs r0, #3
|
|
8006244: f000 fcdc bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END RTC_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8006248: bf00 nop
|
|
800624a: 3758 adds r7, #88 @ 0x58
|
|
800624c: 46bd mov sp, r7
|
|
800624e: bd80 pop {r7, pc}
|
|
8006250: 40002800 .word 0x40002800
|
|
|
|
08006254 <HAL_SPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
8006254: b580 push {r7, lr}
|
|
8006256: b088 sub sp, #32
|
|
8006258: af00 add r7, sp, #0
|
|
800625a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800625c: f107 030c add.w r3, r7, #12
|
|
8006260: 2200 movs r2, #0
|
|
8006262: 601a str r2, [r3, #0]
|
|
8006264: 605a str r2, [r3, #4]
|
|
8006266: 609a str r2, [r3, #8]
|
|
8006268: 60da str r2, [r3, #12]
|
|
800626a: 611a str r2, [r3, #16]
|
|
if(hspi->Instance==SPI1)
|
|
800626c: 687b ldr r3, [r7, #4]
|
|
800626e: 681b ldr r3, [r3, #0]
|
|
8006270: 4a5a ldr r2, [pc, #360] @ (80063dc <HAL_SPI_MspInit+0x188>)
|
|
8006272: 4293 cmp r3, r2
|
|
8006274: d16c bne.n 8006350 <HAL_SPI_MspInit+0xfc>
|
|
{
|
|
/* USER CODE BEGIN SPI1_MspInit 0 */
|
|
|
|
/* USER CODE END SPI1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_SPI1_CLK_ENABLE();
|
|
8006276: f44f 5080 mov.w r0, #4096 @ 0x1000
|
|
800627a: f7ff fe91 bl 8005fa0 <LL_APB2_GRP1_EnableClock>
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800627e: 2001 movs r0, #1
|
|
8006280: f7ff fe43 bl 8005f0a <LL_AHB2_GRP1_EnableClock>
|
|
/**SPI1 GPIO Configuration
|
|
PA5 ------> SPI1_SCK
|
|
PA6 ------> SPI1_MISO
|
|
PA7 ------> SPI1_MOSI
|
|
*/
|
|
GPIO_InitStruct.Pin = SPI1_IMU_SCK_Pin|SPI1_IMU_MISO_Pin|SPI1_IMU_MOSI_Pin;
|
|
8006284: 23e0 movs r3, #224 @ 0xe0
|
|
8006286: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8006288: 2302 movs r3, #2
|
|
800628a: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800628c: 2300 movs r3, #0
|
|
800628e: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
8006290: 2302 movs r3, #2
|
|
8006292: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
|
|
8006294: 2305 movs r3, #5
|
|
8006296: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8006298: f107 030c add.w r3, r7, #12
|
|
800629c: 4619 mov r1, r3
|
|
800629e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80062a2: f001 f825 bl 80072f0 <HAL_GPIO_Init>
|
|
|
|
/* SPI1 DMA Init */
|
|
/* SPI1_TX Init */
|
|
hdma_spi1_tx.Instance = DMA1_Channel1;
|
|
80062a6: 4b4e ldr r3, [pc, #312] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062a8: 4a4e ldr r2, [pc, #312] @ (80063e4 <HAL_SPI_MspInit+0x190>)
|
|
80062aa: 601a str r2, [r3, #0]
|
|
hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX;
|
|
80062ac: 4b4c ldr r3, [pc, #304] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062ae: 2207 movs r2, #7
|
|
80062b0: 605a str r2, [r3, #4]
|
|
hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
80062b2: 4b4b ldr r3, [pc, #300] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062b4: 2210 movs r2, #16
|
|
80062b6: 609a str r2, [r3, #8]
|
|
hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
80062b8: 4b49 ldr r3, [pc, #292] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062ba: 2200 movs r2, #0
|
|
80062bc: 60da str r2, [r3, #12]
|
|
hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
80062be: 4b48 ldr r3, [pc, #288] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062c0: 2280 movs r2, #128 @ 0x80
|
|
80062c2: 611a str r2, [r3, #16]
|
|
hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
80062c4: 4b46 ldr r3, [pc, #280] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062c6: 2200 movs r2, #0
|
|
80062c8: 615a str r2, [r3, #20]
|
|
hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
80062ca: 4b45 ldr r3, [pc, #276] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062cc: 2200 movs r2, #0
|
|
80062ce: 619a str r2, [r3, #24]
|
|
hdma_spi1_tx.Init.Mode = DMA_NORMAL;
|
|
80062d0: 4b43 ldr r3, [pc, #268] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062d2: 2200 movs r2, #0
|
|
80062d4: 61da str r2, [r3, #28]
|
|
hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH;
|
|
80062d6: 4b42 ldr r3, [pc, #264] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062d8: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
80062dc: 621a str r2, [r3, #32]
|
|
if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
|
|
80062de: 4840 ldr r0, [pc, #256] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062e0: f000 fcc6 bl 8006c70 <HAL_DMA_Init>
|
|
80062e4: 4603 mov r3, r0
|
|
80062e6: 2b00 cmp r3, #0
|
|
80062e8: d001 beq.n 80062ee <HAL_SPI_MspInit+0x9a>
|
|
{
|
|
Error_Handler();
|
|
80062ea: f7ff f843 bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx);
|
|
80062ee: 687b ldr r3, [r7, #4]
|
|
80062f0: 4a3b ldr r2, [pc, #236] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062f2: 655a str r2, [r3, #84] @ 0x54
|
|
80062f4: 4a3a ldr r2, [pc, #232] @ (80063e0 <HAL_SPI_MspInit+0x18c>)
|
|
80062f6: 687b ldr r3, [r7, #4]
|
|
80062f8: 6293 str r3, [r2, #40] @ 0x28
|
|
|
|
/* SPI1_RX Init */
|
|
hdma_spi1_rx.Instance = DMA1_Channel2;
|
|
80062fa: 4b3b ldr r3, [pc, #236] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
80062fc: 4a3b ldr r2, [pc, #236] @ (80063ec <HAL_SPI_MspInit+0x198>)
|
|
80062fe: 601a str r2, [r3, #0]
|
|
hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX;
|
|
8006300: 4b39 ldr r3, [pc, #228] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
8006302: 2206 movs r2, #6
|
|
8006304: 605a str r2, [r3, #4]
|
|
hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8006306: 4b38 ldr r3, [pc, #224] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
8006308: 2200 movs r2, #0
|
|
800630a: 609a str r2, [r3, #8]
|
|
hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
800630c: 4b36 ldr r3, [pc, #216] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
800630e: 2200 movs r2, #0
|
|
8006310: 60da str r2, [r3, #12]
|
|
hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8006312: 4b35 ldr r3, [pc, #212] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
8006314: 2280 movs r2, #128 @ 0x80
|
|
8006316: 611a str r2, [r3, #16]
|
|
hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8006318: 4b33 ldr r3, [pc, #204] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
800631a: 2200 movs r2, #0
|
|
800631c: 615a str r2, [r3, #20]
|
|
hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
800631e: 4b32 ldr r3, [pc, #200] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
8006320: 2200 movs r2, #0
|
|
8006322: 619a str r2, [r3, #24]
|
|
hdma_spi1_rx.Init.Mode = DMA_NORMAL;
|
|
8006324: 4b30 ldr r3, [pc, #192] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
8006326: 2200 movs r2, #0
|
|
8006328: 61da str r2, [r3, #28]
|
|
hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
|
800632a: 4b2f ldr r3, [pc, #188] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
800632c: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
8006330: 621a str r2, [r3, #32]
|
|
if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
|
|
8006332: 482d ldr r0, [pc, #180] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
8006334: f000 fc9c bl 8006c70 <HAL_DMA_Init>
|
|
8006338: 4603 mov r3, r0
|
|
800633a: 2b00 cmp r3, #0
|
|
800633c: d001 beq.n 8006342 <HAL_SPI_MspInit+0xee>
|
|
{
|
|
Error_Handler();
|
|
800633e: f7ff f819 bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(hspi,hdmarx,hdma_spi1_rx);
|
|
8006342: 687b ldr r3, [r7, #4]
|
|
8006344: 4a28 ldr r2, [pc, #160] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
8006346: 659a str r2, [r3, #88] @ 0x58
|
|
8006348: 4a27 ldr r2, [pc, #156] @ (80063e8 <HAL_SPI_MspInit+0x194>)
|
|
800634a: 687b ldr r3, [r7, #4]
|
|
800634c: 6293 str r3, [r2, #40] @ 0x28
|
|
/* USER CODE BEGIN SPI2_MspInit 1 */
|
|
|
|
/* USER CODE END SPI2_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
800634e: e040 b.n 80063d2 <HAL_SPI_MspInit+0x17e>
|
|
else if(hspi->Instance==SPI2)
|
|
8006350: 687b ldr r3, [r7, #4]
|
|
8006352: 681b ldr r3, [r3, #0]
|
|
8006354: 4a26 ldr r2, [pc, #152] @ (80063f0 <HAL_SPI_MspInit+0x19c>)
|
|
8006356: 4293 cmp r3, r2
|
|
8006358: d13b bne.n 80063d2 <HAL_SPI_MspInit+0x17e>
|
|
__HAL_RCC_SPI2_CLK_ENABLE();
|
|
800635a: f44f 4080 mov.w r0, #16384 @ 0x4000
|
|
800635e: f7ff fe06 bl 8005f6e <LL_APB1_GRP1_EnableClock>
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8006362: 2004 movs r0, #4
|
|
8006364: f7ff fdd1 bl 8005f0a <LL_AHB2_GRP1_EnableClock>
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8006368: 2001 movs r0, #1
|
|
800636a: f7ff fdce bl 8005f0a <LL_AHB2_GRP1_EnableClock>
|
|
GPIO_InitStruct.Pin = SPI2_SD_MOSI_Pin;
|
|
800636e: 2302 movs r3, #2
|
|
8006370: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8006372: 2302 movs r3, #2
|
|
8006374: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8006376: 2300 movs r3, #0
|
|
8006378: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800637a: 2303 movs r3, #3
|
|
800637c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF3_SPI2;
|
|
800637e: 2303 movs r3, #3
|
|
8006380: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(SPI2_SD_MOSI_GPIO_Port, &GPIO_InitStruct);
|
|
8006382: f107 030c add.w r3, r7, #12
|
|
8006386: 4619 mov r1, r3
|
|
8006388: 481a ldr r0, [pc, #104] @ (80063f4 <HAL_SPI_MspInit+0x1a0>)
|
|
800638a: f000 ffb1 bl 80072f0 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = SPI2_SD_MISO_Pin;
|
|
800638e: 2304 movs r3, #4
|
|
8006390: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8006392: 2302 movs r3, #2
|
|
8006394: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8006396: 2300 movs r3, #0
|
|
8006398: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800639a: 2303 movs r3, #3
|
|
800639c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
800639e: 2305 movs r3, #5
|
|
80063a0: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(SPI2_SD_MISO_GPIO_Port, &GPIO_InitStruct);
|
|
80063a2: f107 030c add.w r3, r7, #12
|
|
80063a6: 4619 mov r1, r3
|
|
80063a8: 4812 ldr r0, [pc, #72] @ (80063f4 <HAL_SPI_MspInit+0x1a0>)
|
|
80063aa: f000 ffa1 bl 80072f0 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = SPI2_SD_SCK_Pin;
|
|
80063ae: f44f 7300 mov.w r3, #512 @ 0x200
|
|
80063b2: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80063b4: 2302 movs r3, #2
|
|
80063b6: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80063b8: 2300 movs r3, #0
|
|
80063ba: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80063bc: 2303 movs r3, #3
|
|
80063be: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
80063c0: 2305 movs r3, #5
|
|
80063c2: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(SPI2_SD_SCK_GPIO_Port, &GPIO_InitStruct);
|
|
80063c4: f107 030c add.w r3, r7, #12
|
|
80063c8: 4619 mov r1, r3
|
|
80063ca: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80063ce: f000 ff8f bl 80072f0 <HAL_GPIO_Init>
|
|
}
|
|
80063d2: bf00 nop
|
|
80063d4: 3720 adds r7, #32
|
|
80063d6: 46bd mov sp, r7
|
|
80063d8: bd80 pop {r7, pc}
|
|
80063da: bf00 nop
|
|
80063dc: 40013000 .word 0x40013000
|
|
80063e0: 200005f0 .word 0x200005f0
|
|
80063e4: 40020008 .word 0x40020008
|
|
80063e8: 20000650 .word 0x20000650
|
|
80063ec: 4002001c .word 0x4002001c
|
|
80063f0: 40003800 .word 0x40003800
|
|
80063f4: 48000800 .word 0x48000800
|
|
|
|
080063f8 <HAL_TIM_PWM_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_pwm: TIM_PWM handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
|
|
{
|
|
80063f8: b580 push {r7, lr}
|
|
80063fa: b082 sub sp, #8
|
|
80063fc: af00 add r7, sp, #0
|
|
80063fe: 6078 str r0, [r7, #4]
|
|
if(htim_pwm->Instance==TIM2)
|
|
8006400: 687b ldr r3, [r7, #4]
|
|
8006402: 681b ldr r3, [r3, #0]
|
|
8006404: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8006408: d102 bne.n 8006410 <HAL_TIM_PWM_MspInit+0x18>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
800640a: 2001 movs r0, #1
|
|
800640c: f7ff fdaf bl 8005f6e <LL_APB1_GRP1_EnableClock>
|
|
|
|
/* USER CODE END TIM2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8006410: bf00 nop
|
|
8006412: 3708 adds r7, #8
|
|
8006414: 46bd mov sp, r7
|
|
8006416: bd80 pop {r7, pc}
|
|
|
|
08006418 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8006418: b580 push {r7, lr}
|
|
800641a: b088 sub sp, #32
|
|
800641c: af00 add r7, sp, #0
|
|
800641e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8006420: f107 030c add.w r3, r7, #12
|
|
8006424: 2200 movs r2, #0
|
|
8006426: 601a str r2, [r3, #0]
|
|
8006428: 605a str r2, [r3, #4]
|
|
800642a: 609a str r2, [r3, #8]
|
|
800642c: 60da str r2, [r3, #12]
|
|
800642e: 611a str r2, [r3, #16]
|
|
if(htim->Instance==TIM2)
|
|
8006430: 687b ldr r3, [r7, #4]
|
|
8006432: 681b ldr r3, [r3, #0]
|
|
8006434: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8006438: d113 bne.n 8006462 <HAL_TIM_MspPostInit+0x4a>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800643a: 2001 movs r0, #1
|
|
800643c: f7ff fd65 bl 8005f0a <LL_AHB2_GRP1_EnableClock>
|
|
/**TIM2 GPIO Configuration
|
|
PA0 ------> TIM2_CH1
|
|
PA1 ------> TIM2_CH2
|
|
PA2 ------> TIM2_CH3
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_CONNECT_LED_Pin|GPIO_STATUS_LED_Pin|GPIO_DEBUG_LED_Pin;
|
|
8006440: 2307 movs r3, #7
|
|
8006442: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8006444: 2302 movs r3, #2
|
|
8006446: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8006448: 2300 movs r3, #0
|
|
800644a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800644c: 2300 movs r3, #0
|
|
800644e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
|
8006450: 2301 movs r3, #1
|
|
8006452: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8006454: f107 030c add.w r3, r7, #12
|
|
8006458: 4619 mov r1, r3
|
|
800645a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800645e: f000 ff47 bl 80072f0 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM2_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
8006462: bf00 nop
|
|
8006464: 3720 adds r7, #32
|
|
8006466: 46bd mov sp, r7
|
|
8006468: bd80 pop {r7, pc}
|
|
|
|
0800646a <LL_APB2_GRP1_EnableClock>:
|
|
{
|
|
800646a: b480 push {r7}
|
|
800646c: b085 sub sp, #20
|
|
800646e: af00 add r7, sp, #0
|
|
8006470: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->APB2ENR, Periphs);
|
|
8006472: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8006476: 6e1a ldr r2, [r3, #96] @ 0x60
|
|
8006478: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800647c: 687b ldr r3, [r7, #4]
|
|
800647e: 4313 orrs r3, r2
|
|
8006480: 660b str r3, [r1, #96] @ 0x60
|
|
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
|
|
8006482: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8006486: 6e1a ldr r2, [r3, #96] @ 0x60
|
|
8006488: 687b ldr r3, [r7, #4]
|
|
800648a: 4013 ands r3, r2
|
|
800648c: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
800648e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8006490: bf00 nop
|
|
8006492: 3714 adds r7, #20
|
|
8006494: 46bd mov sp, r7
|
|
8006496: f85d 7b04 ldr.w r7, [sp], #4
|
|
800649a: 4770 bx lr
|
|
|
|
0800649c <HAL_InitTick>:
|
|
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
|
* @param TickPriority: Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
800649c: b580 push {r7, lr}
|
|
800649e: b08e sub sp, #56 @ 0x38
|
|
80064a0: af00 add r7, sp, #0
|
|
80064a2: 6078 str r0, [r7, #4]
|
|
RCC_ClkInitTypeDef clkconfig;
|
|
uint32_t uwTimclock = 0;
|
|
80064a4: 2300 movs r3, #0
|
|
80064a6: 633b str r3, [r7, #48] @ 0x30
|
|
uint32_t uwPrescalerValue = 0;
|
|
80064a8: 2300 movs r3, #0
|
|
80064aa: 62fb str r3, [r7, #44] @ 0x2c
|
|
uint32_t pFLatency;
|
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80064ac: 2300 movs r3, #0
|
|
80064ae: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
|
|
/*Configure the TIM16 IRQ priority */
|
|
HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority ,0);
|
|
80064b2: 2200 movs r2, #0
|
|
80064b4: 6879 ldr r1, [r7, #4]
|
|
80064b6: 2019 movs r0, #25
|
|
80064b8: f000 fb88 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
/* Enable the TIM16 global Interrupt */
|
|
HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
|
|
80064bc: 2019 movs r0, #25
|
|
80064be: f000 fb9f bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* Enable TIM16 clock */
|
|
__HAL_RCC_TIM16_CLK_ENABLE();
|
|
80064c2: f44f 3000 mov.w r0, #131072 @ 0x20000
|
|
80064c6: f7ff ffd0 bl 800646a <LL_APB2_GRP1_EnableClock>
|
|
|
|
/* Get clock configuration */
|
|
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
|
80064ca: f107 020c add.w r2, r7, #12
|
|
80064ce: f107 0310 add.w r3, r7, #16
|
|
80064d2: 4611 mov r1, r2
|
|
80064d4: 4618 mov r0, r3
|
|
80064d6: f005 fe2d bl 800c134 <HAL_RCC_GetClockConfig>
|
|
|
|
/* Compute TIM16 clock */
|
|
uwTimclock = HAL_RCC_GetPCLK2Freq();
|
|
80064da: f005 fe15 bl 800c108 <HAL_RCC_GetPCLK2Freq>
|
|
80064de: 6338 str r0, [r7, #48] @ 0x30
|
|
|
|
/* Compute the prescaler value to have TIM16 counter clock equal to 1MHz */
|
|
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
|
80064e0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80064e2: 4a21 ldr r2, [pc, #132] @ (8006568 <HAL_InitTick+0xcc>)
|
|
80064e4: fba2 2303 umull r2, r3, r2, r3
|
|
80064e8: 0c9b lsrs r3, r3, #18
|
|
80064ea: 3b01 subs r3, #1
|
|
80064ec: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
/* Initialize TIM16 */
|
|
htim16.Instance = TIM16;
|
|
80064ee: 4b1f ldr r3, [pc, #124] @ (800656c <HAL_InitTick+0xd0>)
|
|
80064f0: 4a1f ldr r2, [pc, #124] @ (8006570 <HAL_InitTick+0xd4>)
|
|
80064f2: 601a str r2, [r3, #0]
|
|
* Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base.
|
|
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
|
* ClockDivision = 0
|
|
* Counter direction = Up
|
|
*/
|
|
htim16.Init.Period = (1000000U / 1000U) - 1U;
|
|
80064f4: 4b1d ldr r3, [pc, #116] @ (800656c <HAL_InitTick+0xd0>)
|
|
80064f6: f240 32e7 movw r2, #999 @ 0x3e7
|
|
80064fa: 60da str r2, [r3, #12]
|
|
htim16.Init.Prescaler = uwPrescalerValue;
|
|
80064fc: 4a1b ldr r2, [pc, #108] @ (800656c <HAL_InitTick+0xd0>)
|
|
80064fe: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006500: 6053 str r3, [r2, #4]
|
|
htim16.Init.ClockDivision = 0;
|
|
8006502: 4b1a ldr r3, [pc, #104] @ (800656c <HAL_InitTick+0xd0>)
|
|
8006504: 2200 movs r2, #0
|
|
8006506: 611a str r2, [r3, #16]
|
|
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8006508: 4b18 ldr r3, [pc, #96] @ (800656c <HAL_InitTick+0xd0>)
|
|
800650a: 2200 movs r2, #0
|
|
800650c: 609a str r2, [r3, #8]
|
|
|
|
status = HAL_TIM_Base_Init(&htim16);
|
|
800650e: 4817 ldr r0, [pc, #92] @ (800656c <HAL_InitTick+0xd0>)
|
|
8006510: f007 ffa4 bl 800e45c <HAL_TIM_Base_Init>
|
|
8006514: 4603 mov r3, r0
|
|
8006516: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
if (status == HAL_OK)
|
|
800651a: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
|
|
800651e: 2b00 cmp r3, #0
|
|
8006520: d11b bne.n 800655a <HAL_InitTick+0xbe>
|
|
/* Register callback */
|
|
HAL_TIM_RegisterCallback(&htim16, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback);
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
|
|
/* Start the TIM time Base generation in interrupt mode */
|
|
status = HAL_TIM_Base_Start_IT(&htim16);
|
|
8006522: 4812 ldr r0, [pc, #72] @ (800656c <HAL_InitTick+0xd0>)
|
|
8006524: f007 fffc bl 800e520 <HAL_TIM_Base_Start_IT>
|
|
8006528: 4603 mov r3, r0
|
|
800652a: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
if (status == HAL_OK)
|
|
800652e: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
|
|
8006532: 2b00 cmp r3, #0
|
|
8006534: d111 bne.n 800655a <HAL_InitTick+0xbe>
|
|
{
|
|
/* Enable the TIM16 global Interrupt */
|
|
HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
|
|
8006536: 2019 movs r0, #25
|
|
8006538: f000 fb62 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
800653c: 687b ldr r3, [r7, #4]
|
|
800653e: 2b0f cmp r3, #15
|
|
8006540: d808 bhi.n 8006554 <HAL_InitTick+0xb8>
|
|
{
|
|
/* Configure the TIM IRQ priority */
|
|
HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority, 0U);
|
|
8006542: 2200 movs r2, #0
|
|
8006544: 6879 ldr r1, [r7, #4]
|
|
8006546: 2019 movs r0, #25
|
|
8006548: f000 fb40 bl 8006bcc <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
800654c: 4a09 ldr r2, [pc, #36] @ (8006574 <HAL_InitTick+0xd8>)
|
|
800654e: 687b ldr r3, [r7, #4]
|
|
8006550: 6013 str r3, [r2, #0]
|
|
8006552: e002 b.n 800655a <HAL_InitTick+0xbe>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8006554: 2301 movs r3, #1
|
|
8006556: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
800655a: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
|
|
}
|
|
800655e: 4618 mov r0, r3
|
|
8006560: 3738 adds r7, #56 @ 0x38
|
|
8006562: 46bd mov sp, r7
|
|
8006564: bd80 pop {r7, pc}
|
|
8006566: bf00 nop
|
|
8006568: 431bde83 .word 0x431bde83
|
|
800656c: 20000730 .word 0x20000730
|
|
8006570: 40014400 .word 0x40014400
|
|
8006574: 20000010 .word 0x20000010
|
|
|
|
08006578 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8006578: b480 push {r7}
|
|
800657a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
800657c: bf00 nop
|
|
800657e: e7fd b.n 800657c <NMI_Handler+0x4>
|
|
|
|
08006580 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8006580: b480 push {r7}
|
|
8006582: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8006584: bf00 nop
|
|
8006586: e7fd b.n 8006584 <HardFault_Handler+0x4>
|
|
|
|
08006588 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8006588: b480 push {r7}
|
|
800658a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
800658c: bf00 nop
|
|
800658e: e7fd b.n 800658c <MemManage_Handler+0x4>
|
|
|
|
08006590 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8006590: b480 push {r7}
|
|
8006592: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8006594: bf00 nop
|
|
8006596: e7fd b.n 8006594 <BusFault_Handler+0x4>
|
|
|
|
08006598 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8006598: b480 push {r7}
|
|
800659a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
800659c: bf00 nop
|
|
800659e: e7fd b.n 800659c <UsageFault_Handler+0x4>
|
|
|
|
080065a0 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
80065a0: b480 push {r7}
|
|
80065a2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
80065a4: bf00 nop
|
|
80065a6: 46bd mov sp, r7
|
|
80065a8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80065ac: 4770 bx lr
|
|
|
|
080065ae <RTC_WKUP_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles RTC wake-up interrupt through EXTI line 19.
|
|
*/
|
|
void RTC_WKUP_IRQHandler(void)
|
|
{
|
|
80065ae: b580 push {r7, lr}
|
|
80065b0: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN RTC_WKUP_IRQn 0 */
|
|
|
|
/* USER CODE END RTC_WKUP_IRQn 0 */
|
|
HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc);
|
|
80065b2: f7fd fdff bl 80041b4 <HW_TS_RTC_Wakeup_Handler>
|
|
/* USER CODE BEGIN RTC_WKUP_IRQn 1 */
|
|
|
|
/* USER CODE END RTC_WKUP_IRQn 1 */
|
|
}
|
|
80065b6: bf00 nop
|
|
80065b8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080065bc <DMA1_Channel1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 channel1 global interrupt.
|
|
*/
|
|
void DMA1_Channel1_IRQHandler(void)
|
|
{
|
|
80065bc: b580 push {r7, lr}
|
|
80065be: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Channel1_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_spi1_tx);
|
|
80065c0: 4802 ldr r0, [pc, #8] @ (80065cc <DMA1_Channel1_IRQHandler+0x10>)
|
|
80065c2: f000 fd36 bl 8007032 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Channel1_IRQn 1 */
|
|
}
|
|
80065c6: bf00 nop
|
|
80065c8: bd80 pop {r7, pc}
|
|
80065ca: bf00 nop
|
|
80065cc: 200005f0 .word 0x200005f0
|
|
|
|
080065d0 <DMA1_Channel2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 channel2 global interrupt.
|
|
*/
|
|
void DMA1_Channel2_IRQHandler(void)
|
|
{
|
|
80065d0: b580 push {r7, lr}
|
|
80065d2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Channel2_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_spi1_rx);
|
|
80065d4: 4802 ldr r0, [pc, #8] @ (80065e0 <DMA1_Channel2_IRQHandler+0x10>)
|
|
80065d6: f000 fd2c bl 8007032 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Channel2_IRQn 1 */
|
|
}
|
|
80065da: bf00 nop
|
|
80065dc: bd80 pop {r7, pc}
|
|
80065de: bf00 nop
|
|
80065e0: 20000650 .word 0x20000650
|
|
|
|
080065e4 <DMA1_Channel3_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 channel3 global interrupt.
|
|
*/
|
|
void DMA1_Channel3_IRQHandler(void)
|
|
{
|
|
80065e4: b580 push {r7, lr}
|
|
80065e6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Channel3_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_i2c1_tx);
|
|
80065e8: 4802 ldr r0, [pc, #8] @ (80065f4 <DMA1_Channel3_IRQHandler+0x10>)
|
|
80065ea: f000 fd22 bl 8007032 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Channel3_IRQn 1 */
|
|
}
|
|
80065ee: bf00 nop
|
|
80065f0: bd80 pop {r7, pc}
|
|
80065f2: bf00 nop
|
|
80065f4: 20000408 .word 0x20000408
|
|
|
|
080065f8 <DMA1_Channel4_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 channel4 global interrupt.
|
|
*/
|
|
void DMA1_Channel4_IRQHandler(void)
|
|
{
|
|
80065f8: b580 push {r7, lr}
|
|
80065fa: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Channel4_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_i2c1_rx);
|
|
80065fc: 4802 ldr r0, [pc, #8] @ (8006608 <DMA1_Channel4_IRQHandler+0x10>)
|
|
80065fe: f000 fd18 bl 8007032 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Channel4_IRQn 1 */
|
|
}
|
|
8006602: bf00 nop
|
|
8006604: bd80 pop {r7, pc}
|
|
8006606: bf00 nop
|
|
8006608: 20000468 .word 0x20000468
|
|
|
|
0800660c <USB_LP_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB low priority interrupt, USB wake-up interrupt through EXTI line 28.
|
|
*/
|
|
void USB_LP_IRQHandler(void)
|
|
{
|
|
800660c: b580 push {r7, lr}
|
|
800660e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_LP_IRQn 0 */
|
|
|
|
/* USER CODE END USB_LP_IRQn 0 */
|
|
HAL_PCD_IRQHandler(&hpcd_USB_FS);
|
|
8006610: 4802 ldr r0, [pc, #8] @ (800661c <USB_LP_IRQHandler+0x10>)
|
|
8006612: f003 f843 bl 800969c <HAL_PCD_IRQHandler>
|
|
/* USER CODE BEGIN USB_LP_IRQn 1 */
|
|
|
|
/* USER CODE END USB_LP_IRQn 1 */
|
|
}
|
|
8006616: bf00 nop
|
|
8006618: bd80 pop {r7, pc}
|
|
800661a: bf00 nop
|
|
800661c: 20013698 .word 0x20013698
|
|
|
|
08006620 <TIM1_UP_TIM16_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
|
|
*/
|
|
void TIM1_UP_TIM16_IRQHandler(void)
|
|
{
|
|
8006620: b580 push {r7, lr}
|
|
8006622: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
|
|
|
|
/* USER CODE END TIM1_UP_TIM16_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim16);
|
|
8006624: 4802 ldr r0, [pc, #8] @ (8006630 <TIM1_UP_TIM16_IRQHandler+0x10>)
|
|
8006626: f008 f820 bl 800e66a <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
|
|
|
|
/* USER CODE END TIM1_UP_TIM16_IRQn 1 */
|
|
}
|
|
800662a: bf00 nop
|
|
800662c: bd80 pop {r7, pc}
|
|
800662e: bf00 nop
|
|
8006630: 20000730 .word 0x20000730
|
|
|
|
08006634 <I2C1_EV_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles I2C1 event interrupt.
|
|
*/
|
|
void I2C1_EV_IRQHandler(void)
|
|
{
|
|
8006634: b580 push {r7, lr}
|
|
8006636: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN I2C1_EV_IRQn 0 */
|
|
|
|
/* USER CODE END I2C1_EV_IRQn 0 */
|
|
HAL_I2C_EV_IRQHandler(&hi2c1);
|
|
8006638: 4802 ldr r0, [pc, #8] @ (8006644 <I2C1_EV_IRQHandler+0x10>)
|
|
800663a: f001 fa85 bl 8007b48 <HAL_I2C_EV_IRQHandler>
|
|
/* USER CODE BEGIN I2C1_EV_IRQn 1 */
|
|
|
|
/* USER CODE END I2C1_EV_IRQn 1 */
|
|
}
|
|
800663e: bf00 nop
|
|
8006640: bd80 pop {r7, pc}
|
|
8006642: bf00 nop
|
|
8006644: 200003b4 .word 0x200003b4
|
|
|
|
08006648 <I2C1_ER_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles I2C1 error interrupt.
|
|
*/
|
|
void I2C1_ER_IRQHandler(void)
|
|
{
|
|
8006648: b580 push {r7, lr}
|
|
800664a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN I2C1_ER_IRQn 0 */
|
|
|
|
/* USER CODE END I2C1_ER_IRQn 0 */
|
|
HAL_I2C_ER_IRQHandler(&hi2c1);
|
|
800664c: 4802 ldr r0, [pc, #8] @ (8006658 <I2C1_ER_IRQHandler+0x10>)
|
|
800664e: f001 fa95 bl 8007b7c <HAL_I2C_ER_IRQHandler>
|
|
/* USER CODE BEGIN I2C1_ER_IRQn 1 */
|
|
|
|
/* USER CODE END I2C1_ER_IRQn 1 */
|
|
}
|
|
8006652: bf00 nop
|
|
8006654: bd80 pop {r7, pc}
|
|
8006656: bf00 nop
|
|
8006658: 200003b4 .word 0x200003b4
|
|
|
|
0800665c <EXTI15_10_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles EXTI line[15:10] interrupts.
|
|
*/
|
|
void EXTI15_10_IRQHandler(void)
|
|
{
|
|
800665c: b580 push {r7, lr}
|
|
800665e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI15_10_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_IMU_INT_Pin);
|
|
8006660: f44f 6080 mov.w r0, #1024 @ 0x400
|
|
8006664: f000 ffcc bl 8007600 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(GPIO_MAGN_INT_Pin);
|
|
8006668: f44f 6000 mov.w r0, #2048 @ 0x800
|
|
800666c: f000 ffc8 bl 8007600 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI15_10_IRQn 1 */
|
|
}
|
|
8006670: bf00 nop
|
|
8006672: bd80 pop {r7, pc}
|
|
|
|
08006674 <IPCC_C1_RX_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles IPCC RX occupied interrupt.
|
|
*/
|
|
void IPCC_C1_RX_IRQHandler(void)
|
|
{
|
|
8006674: b580 push {r7, lr}
|
|
8006676: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN IPCC_C1_RX_IRQn 0 */
|
|
|
|
/* USER CODE END IPCC_C1_RX_IRQn 0 */
|
|
HAL_IPCC_RX_IRQHandler(&hipcc);
|
|
8006678: f011 ff68 bl 801854c <HW_IPCC_Rx_Handler>
|
|
/* USER CODE BEGIN IPCC_C1_RX_IRQn 1 */
|
|
|
|
/* USER CODE END IPCC_C1_RX_IRQn 1 */
|
|
}
|
|
800667c: bf00 nop
|
|
800667e: bd80 pop {r7, pc}
|
|
|
|
08006680 <IPCC_C1_TX_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles IPCC TX free interrupt.
|
|
*/
|
|
void IPCC_C1_TX_IRQHandler(void)
|
|
{
|
|
8006680: b580 push {r7, lr}
|
|
8006682: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN IPCC_C1_TX_IRQn 0 */
|
|
|
|
/* USER CODE END IPCC_C1_TX_IRQn 0 */
|
|
HAL_IPCC_TX_IRQHandler(&hipcc);
|
|
8006684: f011 ff98 bl 80185b8 <HW_IPCC_Tx_Handler>
|
|
/* USER CODE BEGIN IPCC_C1_TX_IRQn 1 */
|
|
|
|
/* USER CODE END IPCC_C1_TX_IRQn 1 */
|
|
}
|
|
8006688: bf00 nop
|
|
800668a: bd80 pop {r7, pc}
|
|
|
|
0800668c <HSEM_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles HSEM global interrupt.
|
|
*/
|
|
void HSEM_IRQHandler(void)
|
|
{
|
|
800668c: b580 push {r7, lr}
|
|
800668e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HSEM_IRQn 0 */
|
|
|
|
/* USER CODE END HSEM_IRQn 0 */
|
|
HAL_HSEM_IRQHandler();
|
|
8006690: f000 ffce bl 8007630 <HAL_HSEM_IRQHandler>
|
|
/* USER CODE BEGIN HSEM_IRQn 1 */
|
|
|
|
/* USER CODE END HSEM_IRQn 1 */
|
|
}
|
|
8006694: bf00 nop
|
|
8006696: bd80 pop {r7, pc}
|
|
|
|
08006698 <_getpid>:
|
|
void initialise_monitor_handles()
|
|
{
|
|
}
|
|
|
|
int _getpid(void)
|
|
{
|
|
8006698: b480 push {r7}
|
|
800669a: af00 add r7, sp, #0
|
|
return 1;
|
|
800669c: 2301 movs r3, #1
|
|
}
|
|
800669e: 4618 mov r0, r3
|
|
80066a0: 46bd mov sp, r7
|
|
80066a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066a6: 4770 bx lr
|
|
|
|
080066a8 <_kill>:
|
|
|
|
int _kill(int pid, int sig)
|
|
{
|
|
80066a8: b580 push {r7, lr}
|
|
80066aa: b082 sub sp, #8
|
|
80066ac: af00 add r7, sp, #0
|
|
80066ae: 6078 str r0, [r7, #4]
|
|
80066b0: 6039 str r1, [r7, #0]
|
|
(void)pid;
|
|
(void)sig;
|
|
errno = EINVAL;
|
|
80066b2: f013 fed7 bl 801a464 <__errno>
|
|
80066b6: 4603 mov r3, r0
|
|
80066b8: 2216 movs r2, #22
|
|
80066ba: 601a str r2, [r3, #0]
|
|
return -1;
|
|
80066bc: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
80066c0: 4618 mov r0, r3
|
|
80066c2: 3708 adds r7, #8
|
|
80066c4: 46bd mov sp, r7
|
|
80066c6: bd80 pop {r7, pc}
|
|
|
|
080066c8 <_exit>:
|
|
|
|
void _exit (int status)
|
|
{
|
|
80066c8: b580 push {r7, lr}
|
|
80066ca: b082 sub sp, #8
|
|
80066cc: af00 add r7, sp, #0
|
|
80066ce: 6078 str r0, [r7, #4]
|
|
_kill(status, -1);
|
|
80066d0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80066d4: 6878 ldr r0, [r7, #4]
|
|
80066d6: f7ff ffe7 bl 80066a8 <_kill>
|
|
while (1) {} /* Make sure we hang here */
|
|
80066da: bf00 nop
|
|
80066dc: e7fd b.n 80066da <_exit+0x12>
|
|
|
|
080066de <_read>:
|
|
}
|
|
|
|
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
|
{
|
|
80066de: b580 push {r7, lr}
|
|
80066e0: b086 sub sp, #24
|
|
80066e2: af00 add r7, sp, #0
|
|
80066e4: 60f8 str r0, [r7, #12]
|
|
80066e6: 60b9 str r1, [r7, #8]
|
|
80066e8: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
80066ea: 2300 movs r3, #0
|
|
80066ec: 617b str r3, [r7, #20]
|
|
80066ee: e00a b.n 8006706 <_read+0x28>
|
|
{
|
|
*ptr++ = __io_getchar();
|
|
80066f0: f3af 8000 nop.w
|
|
80066f4: 4601 mov r1, r0
|
|
80066f6: 68bb ldr r3, [r7, #8]
|
|
80066f8: 1c5a adds r2, r3, #1
|
|
80066fa: 60ba str r2, [r7, #8]
|
|
80066fc: b2ca uxtb r2, r1
|
|
80066fe: 701a strb r2, [r3, #0]
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8006700: 697b ldr r3, [r7, #20]
|
|
8006702: 3301 adds r3, #1
|
|
8006704: 617b str r3, [r7, #20]
|
|
8006706: 697a ldr r2, [r7, #20]
|
|
8006708: 687b ldr r3, [r7, #4]
|
|
800670a: 429a cmp r2, r3
|
|
800670c: dbf0 blt.n 80066f0 <_read+0x12>
|
|
}
|
|
|
|
return len;
|
|
800670e: 687b ldr r3, [r7, #4]
|
|
}
|
|
8006710: 4618 mov r0, r3
|
|
8006712: 3718 adds r7, #24
|
|
8006714: 46bd mov sp, r7
|
|
8006716: bd80 pop {r7, pc}
|
|
|
|
08006718 <_close>:
|
|
}
|
|
return len;
|
|
}
|
|
|
|
int _close(int file)
|
|
{
|
|
8006718: b480 push {r7}
|
|
800671a: b083 sub sp, #12
|
|
800671c: af00 add r7, sp, #0
|
|
800671e: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return -1;
|
|
8006720: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
8006724: 4618 mov r0, r3
|
|
8006726: 370c adds r7, #12
|
|
8006728: 46bd mov sp, r7
|
|
800672a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800672e: 4770 bx lr
|
|
|
|
08006730 <_fstat>:
|
|
|
|
|
|
int _fstat(int file, struct stat *st)
|
|
{
|
|
8006730: b480 push {r7}
|
|
8006732: b083 sub sp, #12
|
|
8006734: af00 add r7, sp, #0
|
|
8006736: 6078 str r0, [r7, #4]
|
|
8006738: 6039 str r1, [r7, #0]
|
|
(void)file;
|
|
st->st_mode = S_IFCHR;
|
|
800673a: 683b ldr r3, [r7, #0]
|
|
800673c: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
8006740: 605a str r2, [r3, #4]
|
|
return 0;
|
|
8006742: 2300 movs r3, #0
|
|
}
|
|
8006744: 4618 mov r0, r3
|
|
8006746: 370c adds r7, #12
|
|
8006748: 46bd mov sp, r7
|
|
800674a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800674e: 4770 bx lr
|
|
|
|
08006750 <_isatty>:
|
|
|
|
int _isatty(int file)
|
|
{
|
|
8006750: b480 push {r7}
|
|
8006752: b083 sub sp, #12
|
|
8006754: af00 add r7, sp, #0
|
|
8006756: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return 1;
|
|
8006758: 2301 movs r3, #1
|
|
}
|
|
800675a: 4618 mov r0, r3
|
|
800675c: 370c adds r7, #12
|
|
800675e: 46bd mov sp, r7
|
|
8006760: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006764: 4770 bx lr
|
|
|
|
08006766 <_lseek>:
|
|
|
|
int _lseek(int file, int ptr, int dir)
|
|
{
|
|
8006766: b480 push {r7}
|
|
8006768: b085 sub sp, #20
|
|
800676a: af00 add r7, sp, #0
|
|
800676c: 60f8 str r0, [r7, #12]
|
|
800676e: 60b9 str r1, [r7, #8]
|
|
8006770: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
(void)ptr;
|
|
(void)dir;
|
|
return 0;
|
|
8006772: 2300 movs r3, #0
|
|
}
|
|
8006774: 4618 mov r0, r3
|
|
8006776: 3714 adds r7, #20
|
|
8006778: 46bd mov sp, r7
|
|
800677a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800677e: 4770 bx lr
|
|
|
|
08006780 <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
8006780: b580 push {r7, lr}
|
|
8006782: b086 sub sp, #24
|
|
8006784: af00 add r7, sp, #0
|
|
8006786: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
8006788: 4a14 ldr r2, [pc, #80] @ (80067dc <_sbrk+0x5c>)
|
|
800678a: 4b15 ldr r3, [pc, #84] @ (80067e0 <_sbrk+0x60>)
|
|
800678c: 1ad3 subs r3, r2, r3
|
|
800678e: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
8006790: 697b ldr r3, [r7, #20]
|
|
8006792: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
8006794: 4b13 ldr r3, [pc, #76] @ (80067e4 <_sbrk+0x64>)
|
|
8006796: 681b ldr r3, [r3, #0]
|
|
8006798: 2b00 cmp r3, #0
|
|
800679a: d102 bne.n 80067a2 <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
800679c: 4b11 ldr r3, [pc, #68] @ (80067e4 <_sbrk+0x64>)
|
|
800679e: 4a12 ldr r2, [pc, #72] @ (80067e8 <_sbrk+0x68>)
|
|
80067a0: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
80067a2: 4b10 ldr r3, [pc, #64] @ (80067e4 <_sbrk+0x64>)
|
|
80067a4: 681a ldr r2, [r3, #0]
|
|
80067a6: 687b ldr r3, [r7, #4]
|
|
80067a8: 4413 add r3, r2
|
|
80067aa: 693a ldr r2, [r7, #16]
|
|
80067ac: 429a cmp r2, r3
|
|
80067ae: d207 bcs.n 80067c0 <_sbrk+0x40>
|
|
{
|
|
errno = ENOMEM;
|
|
80067b0: f013 fe58 bl 801a464 <__errno>
|
|
80067b4: 4603 mov r3, r0
|
|
80067b6: 220c movs r2, #12
|
|
80067b8: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
80067ba: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80067be: e009 b.n 80067d4 <_sbrk+0x54>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
80067c0: 4b08 ldr r3, [pc, #32] @ (80067e4 <_sbrk+0x64>)
|
|
80067c2: 681b ldr r3, [r3, #0]
|
|
80067c4: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
80067c6: 4b07 ldr r3, [pc, #28] @ (80067e4 <_sbrk+0x64>)
|
|
80067c8: 681a ldr r2, [r3, #0]
|
|
80067ca: 687b ldr r3, [r7, #4]
|
|
80067cc: 4413 add r3, r2
|
|
80067ce: 4a05 ldr r2, [pc, #20] @ (80067e4 <_sbrk+0x64>)
|
|
80067d0: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
80067d2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80067d4: 4618 mov r0, r3
|
|
80067d6: 3718 adds r7, #24
|
|
80067d8: 46bd mov sp, r7
|
|
80067da: bd80 pop {r7, pc}
|
|
80067dc: 20030000 .word 0x20030000
|
|
80067e0: 00000400 .word 0x00000400
|
|
80067e4: 2000077c .word 0x2000077c
|
|
80067e8: 20013ce8 .word 0x20013ce8
|
|
|
|
080067ec <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
80067ec: b480 push {r7}
|
|
80067ee: af00 add r7, sp, #0
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */
|
|
80067f0: 4b24 ldr r3, [pc, #144] @ (8006884 <SystemInit+0x98>)
|
|
80067f2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80067f6: 4a23 ldr r2, [pc, #140] @ (8006884 <SystemInit+0x98>)
|
|
80067f8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
80067fc: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
#endif /* FPU */
|
|
|
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
|
/* Set MSION bit */
|
|
RCC->CR |= RCC_CR_MSION;
|
|
8006800: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8006804: 681b ldr r3, [r3, #0]
|
|
8006806: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800680a: f043 0301 orr.w r3, r3, #1
|
|
800680e: 6013 str r3, [r2, #0]
|
|
|
|
/* Reset CFGR register */
|
|
RCC->CFGR = 0x00070000U;
|
|
8006810: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8006814: f44f 22e0 mov.w r2, #458752 @ 0x70000
|
|
8006818: 609a str r2, [r3, #8]
|
|
|
|
/* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
|
|
RCC->CR &= (uint32_t)0xFAF6FEFBU;
|
|
800681a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800681e: 681a ldr r2, [r3, #0]
|
|
8006820: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8006824: 4b18 ldr r3, [pc, #96] @ (8006888 <SystemInit+0x9c>)
|
|
8006826: 4013 ands r3, r2
|
|
8006828: 600b str r3, [r1, #0]
|
|
|
|
/*!< Reset LSI1 and LSI2 bits */
|
|
RCC->CSR &= (uint32_t)0xFFFFFFFAU;
|
|
800682a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800682e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8006832: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
8006836: f023 0305 bic.w r3, r3, #5
|
|
800683a: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/*!< Reset HSI48ON bit */
|
|
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
|
|
800683e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8006842: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
8006846: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800684a: f023 0301 bic.w r3, r3, #1
|
|
800684e: f8c2 3098 str.w r3, [r2, #152] @ 0x98
|
|
|
|
/* Reset PLLCFGR register */
|
|
RCC->PLLCFGR = 0x22041000U;
|
|
8006852: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8006856: 4a0d ldr r2, [pc, #52] @ (800688c <SystemInit+0xa0>)
|
|
8006858: 60da str r2, [r3, #12]
|
|
|
|
#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
|
|
/* Reset PLLSAI1CFGR register */
|
|
RCC->PLLSAI1CFGR = 0x22041000U;
|
|
800685a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800685e: 4a0b ldr r2, [pc, #44] @ (800688c <SystemInit+0xa0>)
|
|
8006860: 611a str r2, [r3, #16]
|
|
#endif /* STM32WB55xx || STM32WB5Mxx */
|
|
|
|
/* Reset HSEBYP bit */
|
|
RCC->CR &= 0xFFFBFFFFU;
|
|
8006862: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8006866: 681b ldr r3, [r3, #0]
|
|
8006868: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800686c: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8006870: 6013 str r3, [r2, #0]
|
|
|
|
/* Disable all interrupts */
|
|
RCC->CIER = 0x00000000;
|
|
8006872: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8006876: 2200 movs r2, #0
|
|
8006878: 619a str r2, [r3, #24]
|
|
}
|
|
800687a: bf00 nop
|
|
800687c: 46bd mov sp, r7
|
|
800687e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006882: 4770 bx lr
|
|
8006884: e000ed00 .word 0xe000ed00
|
|
8006888: faf6fefb .word 0xfaf6fefb
|
|
800688c: 22041000 .word 0x22041000
|
|
|
|
08006890 <CopyDataInit>:
|
|
bl LoopCopyDataInit
|
|
.endm
|
|
|
|
.section .text.data_initializers
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8006890: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8006892: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8006894: 3304 adds r3, #4
|
|
|
|
08006896 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8006896: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8006898: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
800689a: d3f9 bcc.n 8006890 <CopyDataInit>
|
|
bx lr
|
|
800689c: 4770 bx lr
|
|
|
|
0800689e <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r0]
|
|
800689e: 6003 str r3, [r0, #0]
|
|
adds r0, r0, #4
|
|
80068a0: 3004 adds r0, #4
|
|
|
|
080068a2 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r0, r1
|
|
80068a2: 4288 cmp r0, r1
|
|
bcc FillZerobss
|
|
80068a4: d3fb bcc.n 800689e <FillZerobss>
|
|
bx lr
|
|
80068a6: 4770 bx lr
|
|
|
|
080068a8 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr r0, =_estack
|
|
80068a8: 480c ldr r0, [pc, #48] @ (80068dc <LoopForever+0x2>)
|
|
mov sp, r0 /* set stack pointer */
|
|
80068aa: 4685 mov sp, r0
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
80068ac: f7ff ff9e bl 80067ec <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
INIT_DATA _sdata, _edata, _sidata
|
|
80068b0: 480b ldr r0, [pc, #44] @ (80068e0 <LoopForever+0x6>)
|
|
80068b2: 490c ldr r1, [pc, #48] @ (80068e4 <LoopForever+0xa>)
|
|
80068b4: 4a0c ldr r2, [pc, #48] @ (80068e8 <LoopForever+0xe>)
|
|
80068b6: 2300 movs r3, #0
|
|
80068b8: f7ff ffed bl 8006896 <LoopCopyDataInit>
|
|
INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2
|
|
80068bc: 480b ldr r0, [pc, #44] @ (80068ec <LoopForever+0x12>)
|
|
80068be: 490c ldr r1, [pc, #48] @ (80068f0 <LoopForever+0x16>)
|
|
80068c0: 4a0c ldr r2, [pc, #48] @ (80068f4 <LoopForever+0x1a>)
|
|
80068c2: 2300 movs r3, #0
|
|
80068c4: f7ff ffe7 bl 8006896 <LoopCopyDataInit>
|
|
|
|
/* Zero fill the bss segments. */
|
|
INIT_BSS _sbss, _ebss
|
|
80068c8: 480b ldr r0, [pc, #44] @ (80068f8 <LoopForever+0x1e>)
|
|
80068ca: 490c ldr r1, [pc, #48] @ (80068fc <LoopForever+0x22>)
|
|
80068cc: 2300 movs r3, #0
|
|
80068ce: f7ff ffe8 bl 80068a2 <LoopFillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
80068d2: f013 fdcd bl 801a470 <__libc_init_array>
|
|
/* Call the application s entry point.*/
|
|
bl main
|
|
80068d6: f7fd ffc9 bl 800486c <main>
|
|
|
|
080068da <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
80068da: e7fe b.n 80068da <LoopForever>
|
|
ldr r0, =_estack
|
|
80068dc: 20030000 .word 0x20030000
|
|
INIT_DATA _sdata, _edata, _sidata
|
|
80068e0: 20000008 .word 0x20000008
|
|
80068e4: 200002d8 .word 0x200002d8
|
|
80068e8: 0801ea60 .word 0x0801ea60
|
|
INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2
|
|
80068ec: 200300d8 .word 0x200300d8
|
|
80068f0: 2003094a .word 0x2003094a
|
|
80068f4: 0801ed41 .word 0x0801ed41
|
|
INIT_BSS _sbss, _ebss
|
|
80068f8: 200002ec .word 0x200002ec
|
|
80068fc: 20013ce8 .word 0x20013ce8
|
|
|
|
08006900 <ADC1_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8006900: e7fe b.n 8006900 <ADC1_IRQHandler>
|
|
...
|
|
|
|
08006904 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8006904: b580 push {r7, lr}
|
|
8006906: b082 sub sp, #8
|
|
8006908: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800690a: 2300 movs r3, #0
|
|
800690c: 71fb strb r3, [r7, #7]
|
|
#if (DATA_CACHE_ENABLE == 0U)
|
|
__HAL_FLASH_DATA_CACHE_DISABLE();
|
|
#endif /* DATA_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
800690e: 4b0c ldr r3, [pc, #48] @ (8006940 <HAL_Init+0x3c>)
|
|
8006910: 681b ldr r3, [r3, #0]
|
|
8006912: 4a0b ldr r2, [pc, #44] @ (8006940 <HAL_Init+0x3c>)
|
|
8006914: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8006918: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
800691a: 2003 movs r0, #3
|
|
800691c: f000 f94b bl 8006bb6 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
8006920: 200f movs r0, #15
|
|
8006922: f7ff fdbb bl 800649c <HAL_InitTick>
|
|
8006926: 4603 mov r3, r0
|
|
8006928: 2b00 cmp r3, #0
|
|
800692a: d002 beq.n 8006932 <HAL_Init+0x2e>
|
|
{
|
|
status = HAL_ERROR;
|
|
800692c: 2301 movs r3, #1
|
|
800692e: 71fb strb r3, [r7, #7]
|
|
8006930: e001 b.n 8006936 <HAL_Init+0x32>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8006932: f7ff fb61 bl 8005ff8 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8006936: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8006938: 4618 mov r0, r3
|
|
800693a: 3708 adds r7, #8
|
|
800693c: 46bd mov sp, r7
|
|
800693e: bd80 pop {r7, pc}
|
|
8006940: 58004000 .word 0x58004000
|
|
|
|
08006944 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8006944: b480 push {r7}
|
|
8006946: af00 add r7, sp, #0
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
8006948: 4b06 ldr r3, [pc, #24] @ (8006964 <HAL_IncTick+0x20>)
|
|
800694a: 781b ldrb r3, [r3, #0]
|
|
800694c: 461a mov r2, r3
|
|
800694e: 4b06 ldr r3, [pc, #24] @ (8006968 <HAL_IncTick+0x24>)
|
|
8006950: 681b ldr r3, [r3, #0]
|
|
8006952: 4413 add r3, r2
|
|
8006954: 4a04 ldr r2, [pc, #16] @ (8006968 <HAL_IncTick+0x24>)
|
|
8006956: 6013 str r3, [r2, #0]
|
|
}
|
|
8006958: bf00 nop
|
|
800695a: 46bd mov sp, r7
|
|
800695c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006960: 4770 bx lr
|
|
8006962: bf00 nop
|
|
8006964: 20000014 .word 0x20000014
|
|
8006968: 20000780 .word 0x20000780
|
|
|
|
0800696c <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
800696c: b480 push {r7}
|
|
800696e: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8006970: 4b03 ldr r3, [pc, #12] @ (8006980 <HAL_GetTick+0x14>)
|
|
8006972: 681b ldr r3, [r3, #0]
|
|
}
|
|
8006974: 4618 mov r0, r3
|
|
8006976: 46bd mov sp, r7
|
|
8006978: f85d 7b04 ldr.w r7, [sp], #4
|
|
800697c: 4770 bx lr
|
|
800697e: bf00 nop
|
|
8006980: 20000780 .word 0x20000780
|
|
|
|
08006984 <HAL_GetTickPrio>:
|
|
/**
|
|
* @brief This function returns a tick priority.
|
|
* @retval tick priority
|
|
*/
|
|
uint32_t HAL_GetTickPrio(void)
|
|
{
|
|
8006984: b480 push {r7}
|
|
8006986: af00 add r7, sp, #0
|
|
return uwTickPrio;
|
|
8006988: 4b03 ldr r3, [pc, #12] @ (8006998 <HAL_GetTickPrio+0x14>)
|
|
800698a: 681b ldr r3, [r3, #0]
|
|
}
|
|
800698c: 4618 mov r0, r3
|
|
800698e: 46bd mov sp, r7
|
|
8006990: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006994: 4770 bx lr
|
|
8006996: bf00 nop
|
|
8006998: 20000010 .word 0x20000010
|
|
|
|
0800699c <__NVIC_SetPriorityGrouping>:
|
|
{
|
|
800699c: b480 push {r7}
|
|
800699e: b085 sub sp, #20
|
|
80069a0: af00 add r7, sp, #0
|
|
80069a2: 6078 str r0, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80069a4: 687b ldr r3, [r7, #4]
|
|
80069a6: f003 0307 and.w r3, r3, #7
|
|
80069aa: 60fb str r3, [r7, #12]
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80069ac: 4b0c ldr r3, [pc, #48] @ (80069e0 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80069ae: 68db ldr r3, [r3, #12]
|
|
80069b0: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80069b2: 68ba ldr r2, [r7, #8]
|
|
80069b4: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80069b8: 4013 ands r3, r2
|
|
80069ba: 60bb str r3, [r7, #8]
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80069bc: 68fb ldr r3, [r7, #12]
|
|
80069be: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80069c0: 68bb ldr r3, [r7, #8]
|
|
80069c2: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80069c4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80069c8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80069cc: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80069ce: 4a04 ldr r2, [pc, #16] @ (80069e0 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80069d0: 68bb ldr r3, [r7, #8]
|
|
80069d2: 60d3 str r3, [r2, #12]
|
|
}
|
|
80069d4: bf00 nop
|
|
80069d6: 3714 adds r7, #20
|
|
80069d8: 46bd mov sp, r7
|
|
80069da: f85d 7b04 ldr.w r7, [sp], #4
|
|
80069de: 4770 bx lr
|
|
80069e0: e000ed00 .word 0xe000ed00
|
|
|
|
080069e4 <__NVIC_GetPriorityGrouping>:
|
|
{
|
|
80069e4: b480 push {r7}
|
|
80069e6: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80069e8: 4b04 ldr r3, [pc, #16] @ (80069fc <__NVIC_GetPriorityGrouping+0x18>)
|
|
80069ea: 68db ldr r3, [r3, #12]
|
|
80069ec: 0a1b lsrs r3, r3, #8
|
|
80069ee: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80069f2: 4618 mov r0, r3
|
|
80069f4: 46bd mov sp, r7
|
|
80069f6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80069fa: 4770 bx lr
|
|
80069fc: e000ed00 .word 0xe000ed00
|
|
|
|
08006a00 <__NVIC_EnableIRQ>:
|
|
{
|
|
8006a00: b480 push {r7}
|
|
8006a02: b083 sub sp, #12
|
|
8006a04: af00 add r7, sp, #0
|
|
8006a06: 4603 mov r3, r0
|
|
8006a08: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8006a0a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006a0e: 2b00 cmp r3, #0
|
|
8006a10: db0b blt.n 8006a2a <__NVIC_EnableIRQ+0x2a>
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8006a12: 79fb ldrb r3, [r7, #7]
|
|
8006a14: f003 021f and.w r2, r3, #31
|
|
8006a18: 4907 ldr r1, [pc, #28] @ (8006a38 <__NVIC_EnableIRQ+0x38>)
|
|
8006a1a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006a1e: 095b lsrs r3, r3, #5
|
|
8006a20: 2001 movs r0, #1
|
|
8006a22: fa00 f202 lsl.w r2, r0, r2
|
|
8006a26: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
}
|
|
8006a2a: bf00 nop
|
|
8006a2c: 370c adds r7, #12
|
|
8006a2e: 46bd mov sp, r7
|
|
8006a30: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006a34: 4770 bx lr
|
|
8006a36: bf00 nop
|
|
8006a38: e000e100 .word 0xe000e100
|
|
|
|
08006a3c <__NVIC_DisableIRQ>:
|
|
{
|
|
8006a3c: b480 push {r7}
|
|
8006a3e: b083 sub sp, #12
|
|
8006a40: af00 add r7, sp, #0
|
|
8006a42: 4603 mov r3, r0
|
|
8006a44: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8006a46: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006a4a: 2b00 cmp r3, #0
|
|
8006a4c: db12 blt.n 8006a74 <__NVIC_DisableIRQ+0x38>
|
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8006a4e: 79fb ldrb r3, [r7, #7]
|
|
8006a50: f003 021f and.w r2, r3, #31
|
|
8006a54: 490a ldr r1, [pc, #40] @ (8006a80 <__NVIC_DisableIRQ+0x44>)
|
|
8006a56: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006a5a: 095b lsrs r3, r3, #5
|
|
8006a5c: 2001 movs r0, #1
|
|
8006a5e: fa00 f202 lsl.w r2, r0, r2
|
|
8006a62: 3320 adds r3, #32
|
|
8006a64: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__ASM volatile ("dsb 0xF":::"memory");
|
|
8006a68: f3bf 8f4f dsb sy
|
|
}
|
|
8006a6c: bf00 nop
|
|
__ASM volatile ("isb 0xF":::"memory");
|
|
8006a6e: f3bf 8f6f isb sy
|
|
}
|
|
8006a72: bf00 nop
|
|
}
|
|
8006a74: bf00 nop
|
|
8006a76: 370c adds r7, #12
|
|
8006a78: 46bd mov sp, r7
|
|
8006a7a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006a7e: 4770 bx lr
|
|
8006a80: e000e100 .word 0xe000e100
|
|
|
|
08006a84 <__NVIC_SetPendingIRQ>:
|
|
{
|
|
8006a84: b480 push {r7}
|
|
8006a86: b083 sub sp, #12
|
|
8006a88: af00 add r7, sp, #0
|
|
8006a8a: 4603 mov r3, r0
|
|
8006a8c: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8006a8e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006a92: 2b00 cmp r3, #0
|
|
8006a94: db0c blt.n 8006ab0 <__NVIC_SetPendingIRQ+0x2c>
|
|
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8006a96: 79fb ldrb r3, [r7, #7]
|
|
8006a98: f003 021f and.w r2, r3, #31
|
|
8006a9c: 4907 ldr r1, [pc, #28] @ (8006abc <__NVIC_SetPendingIRQ+0x38>)
|
|
8006a9e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006aa2: 095b lsrs r3, r3, #5
|
|
8006aa4: 2001 movs r0, #1
|
|
8006aa6: fa00 f202 lsl.w r2, r0, r2
|
|
8006aaa: 3340 adds r3, #64 @ 0x40
|
|
8006aac: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
}
|
|
8006ab0: bf00 nop
|
|
8006ab2: 370c adds r7, #12
|
|
8006ab4: 46bd mov sp, r7
|
|
8006ab6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006aba: 4770 bx lr
|
|
8006abc: e000e100 .word 0xe000e100
|
|
|
|
08006ac0 <__NVIC_ClearPendingIRQ>:
|
|
{
|
|
8006ac0: b480 push {r7}
|
|
8006ac2: b083 sub sp, #12
|
|
8006ac4: af00 add r7, sp, #0
|
|
8006ac6: 4603 mov r3, r0
|
|
8006ac8: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8006aca: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006ace: 2b00 cmp r3, #0
|
|
8006ad0: db0c blt.n 8006aec <__NVIC_ClearPendingIRQ+0x2c>
|
|
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8006ad2: 79fb ldrb r3, [r7, #7]
|
|
8006ad4: f003 021f and.w r2, r3, #31
|
|
8006ad8: 4907 ldr r1, [pc, #28] @ (8006af8 <__NVIC_ClearPendingIRQ+0x38>)
|
|
8006ada: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006ade: 095b lsrs r3, r3, #5
|
|
8006ae0: 2001 movs r0, #1
|
|
8006ae2: fa00 f202 lsl.w r2, r0, r2
|
|
8006ae6: 3360 adds r3, #96 @ 0x60
|
|
8006ae8: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
}
|
|
8006aec: bf00 nop
|
|
8006aee: 370c adds r7, #12
|
|
8006af0: 46bd mov sp, r7
|
|
8006af2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006af6: 4770 bx lr
|
|
8006af8: e000e100 .word 0xe000e100
|
|
|
|
08006afc <__NVIC_SetPriority>:
|
|
{
|
|
8006afc: b480 push {r7}
|
|
8006afe: b083 sub sp, #12
|
|
8006b00: af00 add r7, sp, #0
|
|
8006b02: 4603 mov r3, r0
|
|
8006b04: 6039 str r1, [r7, #0]
|
|
8006b06: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8006b08: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006b0c: 2b00 cmp r3, #0
|
|
8006b0e: db0a blt.n 8006b26 <__NVIC_SetPriority+0x2a>
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8006b10: 683b ldr r3, [r7, #0]
|
|
8006b12: b2da uxtb r2, r3
|
|
8006b14: 490c ldr r1, [pc, #48] @ (8006b48 <__NVIC_SetPriority+0x4c>)
|
|
8006b16: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006b1a: 0112 lsls r2, r2, #4
|
|
8006b1c: b2d2 uxtb r2, r2
|
|
8006b1e: 440b add r3, r1
|
|
8006b20: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
8006b24: e00a b.n 8006b3c <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8006b26: 683b ldr r3, [r7, #0]
|
|
8006b28: b2da uxtb r2, r3
|
|
8006b2a: 4908 ldr r1, [pc, #32] @ (8006b4c <__NVIC_SetPriority+0x50>)
|
|
8006b2c: 79fb ldrb r3, [r7, #7]
|
|
8006b2e: f003 030f and.w r3, r3, #15
|
|
8006b32: 3b04 subs r3, #4
|
|
8006b34: 0112 lsls r2, r2, #4
|
|
8006b36: b2d2 uxtb r2, r2
|
|
8006b38: 440b add r3, r1
|
|
8006b3a: 761a strb r2, [r3, #24]
|
|
}
|
|
8006b3c: bf00 nop
|
|
8006b3e: 370c adds r7, #12
|
|
8006b40: 46bd mov sp, r7
|
|
8006b42: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006b46: 4770 bx lr
|
|
8006b48: e000e100 .word 0xe000e100
|
|
8006b4c: e000ed00 .word 0xe000ed00
|
|
|
|
08006b50 <NVIC_EncodePriority>:
|
|
{
|
|
8006b50: b480 push {r7}
|
|
8006b52: b089 sub sp, #36 @ 0x24
|
|
8006b54: af00 add r7, sp, #0
|
|
8006b56: 60f8 str r0, [r7, #12]
|
|
8006b58: 60b9 str r1, [r7, #8]
|
|
8006b5a: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8006b5c: 68fb ldr r3, [r7, #12]
|
|
8006b5e: f003 0307 and.w r3, r3, #7
|
|
8006b62: 61fb str r3, [r7, #28]
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8006b64: 69fb ldr r3, [r7, #28]
|
|
8006b66: f1c3 0307 rsb r3, r3, #7
|
|
8006b6a: 2b04 cmp r3, #4
|
|
8006b6c: bf28 it cs
|
|
8006b6e: 2304 movcs r3, #4
|
|
8006b70: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8006b72: 69fb ldr r3, [r7, #28]
|
|
8006b74: 3304 adds r3, #4
|
|
8006b76: 2b06 cmp r3, #6
|
|
8006b78: d902 bls.n 8006b80 <NVIC_EncodePriority+0x30>
|
|
8006b7a: 69fb ldr r3, [r7, #28]
|
|
8006b7c: 3b03 subs r3, #3
|
|
8006b7e: e000 b.n 8006b82 <NVIC_EncodePriority+0x32>
|
|
8006b80: 2300 movs r3, #0
|
|
8006b82: 617b str r3, [r7, #20]
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8006b84: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8006b88: 69bb ldr r3, [r7, #24]
|
|
8006b8a: fa02 f303 lsl.w r3, r2, r3
|
|
8006b8e: 43da mvns r2, r3
|
|
8006b90: 68bb ldr r3, [r7, #8]
|
|
8006b92: 401a ands r2, r3
|
|
8006b94: 697b ldr r3, [r7, #20]
|
|
8006b96: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8006b98: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8006b9c: 697b ldr r3, [r7, #20]
|
|
8006b9e: fa01 f303 lsl.w r3, r1, r3
|
|
8006ba2: 43d9 mvns r1, r3
|
|
8006ba4: 687b ldr r3, [r7, #4]
|
|
8006ba6: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8006ba8: 4313 orrs r3, r2
|
|
}
|
|
8006baa: 4618 mov r0, r3
|
|
8006bac: 3724 adds r7, #36 @ 0x24
|
|
8006bae: 46bd mov sp, r7
|
|
8006bb0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006bb4: 4770 bx lr
|
|
|
|
08006bb6 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8006bb6: b580 push {r7, lr}
|
|
8006bb8: b082 sub sp, #8
|
|
8006bba: af00 add r7, sp, #0
|
|
8006bbc: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8006bbe: 6878 ldr r0, [r7, #4]
|
|
8006bc0: f7ff feec bl 800699c <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8006bc4: bf00 nop
|
|
8006bc6: 3708 adds r7, #8
|
|
8006bc8: 46bd mov sp, r7
|
|
8006bca: bd80 pop {r7, pc}
|
|
|
|
08006bcc <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8006bcc: b580 push {r7, lr}
|
|
8006bce: b086 sub sp, #24
|
|
8006bd0: af00 add r7, sp, #0
|
|
8006bd2: 4603 mov r3, r0
|
|
8006bd4: 60b9 str r1, [r7, #8]
|
|
8006bd6: 607a str r2, [r7, #4]
|
|
8006bd8: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8006bda: f7ff ff03 bl 80069e4 <__NVIC_GetPriorityGrouping>
|
|
8006bde: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8006be0: 687a ldr r2, [r7, #4]
|
|
8006be2: 68b9 ldr r1, [r7, #8]
|
|
8006be4: 6978 ldr r0, [r7, #20]
|
|
8006be6: f7ff ffb3 bl 8006b50 <NVIC_EncodePriority>
|
|
8006bea: 4602 mov r2, r0
|
|
8006bec: f997 300f ldrsb.w r3, [r7, #15]
|
|
8006bf0: 4611 mov r1, r2
|
|
8006bf2: 4618 mov r0, r3
|
|
8006bf4: f7ff ff82 bl 8006afc <__NVIC_SetPriority>
|
|
}
|
|
8006bf8: bf00 nop
|
|
8006bfa: 3718 adds r7, #24
|
|
8006bfc: 46bd mov sp, r7
|
|
8006bfe: bd80 pop {r7, pc}
|
|
|
|
08006c00 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8006c00: b580 push {r7, lr}
|
|
8006c02: b082 sub sp, #8
|
|
8006c04: af00 add r7, sp, #0
|
|
8006c06: 4603 mov r3, r0
|
|
8006c08: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8006c0a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006c0e: 4618 mov r0, r3
|
|
8006c10: f7ff fef6 bl 8006a00 <__NVIC_EnableIRQ>
|
|
}
|
|
8006c14: bf00 nop
|
|
8006c16: 3708 adds r7, #8
|
|
8006c18: 46bd mov sp, r7
|
|
8006c1a: bd80 pop {r7, pc}
|
|
|
|
08006c1c <HAL_NVIC_DisableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8006c1c: b580 push {r7, lr}
|
|
8006c1e: b082 sub sp, #8
|
|
8006c20: af00 add r7, sp, #0
|
|
8006c22: 4603 mov r3, r0
|
|
8006c24: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Disable interrupt */
|
|
NVIC_DisableIRQ(IRQn);
|
|
8006c26: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006c2a: 4618 mov r0, r3
|
|
8006c2c: f7ff ff06 bl 8006a3c <__NVIC_DisableIRQ>
|
|
}
|
|
8006c30: bf00 nop
|
|
8006c32: 3708 adds r7, #8
|
|
8006c34: 46bd mov sp, r7
|
|
8006c36: bd80 pop {r7, pc}
|
|
|
|
08006c38 <HAL_NVIC_SetPendingIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
8006c38: b580 push {r7, lr}
|
|
8006c3a: b082 sub sp, #8
|
|
8006c3c: af00 add r7, sp, #0
|
|
8006c3e: 4603 mov r3, r0
|
|
8006c40: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Set interrupt pending */
|
|
NVIC_SetPendingIRQ(IRQn);
|
|
8006c42: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006c46: 4618 mov r0, r3
|
|
8006c48: f7ff ff1c bl 8006a84 <__NVIC_SetPendingIRQ>
|
|
}
|
|
8006c4c: bf00 nop
|
|
8006c4e: 3708 adds r7, #8
|
|
8006c50: 46bd mov sp, r7
|
|
8006c52: bd80 pop {r7, pc}
|
|
|
|
08006c54 <HAL_NVIC_ClearPendingIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
8006c54: b580 push {r7, lr}
|
|
8006c56: b082 sub sp, #8
|
|
8006c58: af00 add r7, sp, #0
|
|
8006c5a: 4603 mov r3, r0
|
|
8006c5c: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Clear pending interrupt */
|
|
NVIC_ClearPendingIRQ(IRQn);
|
|
8006c5e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006c62: 4618 mov r0, r3
|
|
8006c64: f7ff ff2c bl 8006ac0 <__NVIC_ClearPendingIRQ>
|
|
}
|
|
8006c68: bf00 nop
|
|
8006c6a: 3708 adds r7, #8
|
|
8006c6c: 46bd mov sp, r7
|
|
8006c6e: bd80 pop {r7, pc}
|
|
|
|
08006c70 <HAL_DMA_Init>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006c70: b580 push {r7, lr}
|
|
8006c72: b084 sub sp, #16
|
|
8006c74: af00 add r7, sp, #0
|
|
8006c76: 6078 str r0, [r7, #4]
|
|
uint32_t tmp;
|
|
|
|
/* Check the DMA handle allocation */
|
|
if (hdma == NULL)
|
|
8006c78: 687b ldr r3, [r7, #4]
|
|
8006c7a: 2b00 cmp r3, #0
|
|
8006c7c: d101 bne.n 8006c82 <HAL_DMA_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8006c7e: 2301 movs r3, #1
|
|
8006c80: e08e b.n 8006da0 <HAL_DMA_Init+0x130>
|
|
|
|
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
|
|
|
|
#if defined(DMA2)
|
|
/* Compute the channel index */
|
|
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
|
8006c82: 687b ldr r3, [r7, #4]
|
|
8006c84: 681b ldr r3, [r3, #0]
|
|
8006c86: 461a mov r2, r3
|
|
8006c88: 4b47 ldr r3, [pc, #284] @ (8006da8 <HAL_DMA_Init+0x138>)
|
|
8006c8a: 429a cmp r2, r3
|
|
8006c8c: d80f bhi.n 8006cae <HAL_DMA_Init+0x3e>
|
|
{
|
|
/* DMA1 */
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
|
8006c8e: 687b ldr r3, [r7, #4]
|
|
8006c90: 681b ldr r3, [r3, #0]
|
|
8006c92: 461a mov r2, r3
|
|
8006c94: 4b45 ldr r3, [pc, #276] @ (8006dac <HAL_DMA_Init+0x13c>)
|
|
8006c96: 4413 add r3, r2
|
|
8006c98: 4a45 ldr r2, [pc, #276] @ (8006db0 <HAL_DMA_Init+0x140>)
|
|
8006c9a: fba2 2303 umull r2, r3, r2, r3
|
|
8006c9e: 091b lsrs r3, r3, #4
|
|
8006ca0: 009a lsls r2, r3, #2
|
|
8006ca2: 687b ldr r3, [r7, #4]
|
|
8006ca4: 645a str r2, [r3, #68] @ 0x44
|
|
hdma->DmaBaseAddress = DMA1;
|
|
8006ca6: 687b ldr r3, [r7, #4]
|
|
8006ca8: 4a42 ldr r2, [pc, #264] @ (8006db4 <HAL_DMA_Init+0x144>)
|
|
8006caa: 641a str r2, [r3, #64] @ 0x40
|
|
8006cac: e00e b.n 8006ccc <HAL_DMA_Init+0x5c>
|
|
}
|
|
else
|
|
{
|
|
/* DMA2 */
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
|
8006cae: 687b ldr r3, [r7, #4]
|
|
8006cb0: 681b ldr r3, [r3, #0]
|
|
8006cb2: 461a mov r2, r3
|
|
8006cb4: 4b40 ldr r3, [pc, #256] @ (8006db8 <HAL_DMA_Init+0x148>)
|
|
8006cb6: 4413 add r3, r2
|
|
8006cb8: 4a3d ldr r2, [pc, #244] @ (8006db0 <HAL_DMA_Init+0x140>)
|
|
8006cba: fba2 2303 umull r2, r3, r2, r3
|
|
8006cbe: 091b lsrs r3, r3, #4
|
|
8006cc0: 009a lsls r2, r3, #2
|
|
8006cc2: 687b ldr r3, [r7, #4]
|
|
8006cc4: 645a str r2, [r3, #68] @ 0x44
|
|
hdma->DmaBaseAddress = DMA2;
|
|
8006cc6: 687b ldr r3, [r7, #4]
|
|
8006cc8: 4a3c ldr r2, [pc, #240] @ (8006dbc <HAL_DMA_Init+0x14c>)
|
|
8006cca: 641a str r2, [r3, #64] @ 0x40
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
|
hdma->DmaBaseAddress = DMA1;
|
|
#endif /* DMA2 */
|
|
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8006ccc: 687b ldr r3, [r7, #4]
|
|
8006cce: 2202 movs r2, #2
|
|
8006cd0: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Get the CR register value */
|
|
tmp = hdma->Instance->CCR;
|
|
8006cd4: 687b ldr r3, [r7, #4]
|
|
8006cd6: 681b ldr r3, [r3, #0]
|
|
8006cd8: 681b ldr r3, [r3, #0]
|
|
8006cda: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
|
|
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
|
|
8006cdc: 68fb ldr r3, [r7, #12]
|
|
8006cde: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
|
|
8006ce2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8006ce6: 60fb str r3, [r7, #12]
|
|
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
|
|
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
|
|
|
|
/* Prepare the DMA Channel configuration */
|
|
tmp |= hdma->Init.Direction |
|
|
8006ce8: 687b ldr r3, [r7, #4]
|
|
8006cea: 689a ldr r2, [r3, #8]
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
8006cec: 687b ldr r3, [r7, #4]
|
|
8006cee: 68db ldr r3, [r3, #12]
|
|
tmp |= hdma->Init.Direction |
|
|
8006cf0: 431a orrs r2, r3
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
8006cf2: 687b ldr r3, [r7, #4]
|
|
8006cf4: 691b ldr r3, [r3, #16]
|
|
8006cf6: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8006cf8: 687b ldr r3, [r7, #4]
|
|
8006cfa: 695b ldr r3, [r3, #20]
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
8006cfc: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8006cfe: 687b ldr r3, [r7, #4]
|
|
8006d00: 699b ldr r3, [r3, #24]
|
|
8006d02: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
8006d04: 687b ldr r3, [r7, #4]
|
|
8006d06: 69db ldr r3, [r3, #28]
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8006d08: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
8006d0a: 687b ldr r3, [r7, #4]
|
|
8006d0c: 6a1b ldr r3, [r3, #32]
|
|
8006d0e: 4313 orrs r3, r2
|
|
tmp |= hdma->Init.Direction |
|
|
8006d10: 68fa ldr r2, [r7, #12]
|
|
8006d12: 4313 orrs r3, r2
|
|
8006d14: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to DMA Channel CR register */
|
|
hdma->Instance->CCR = tmp;
|
|
8006d16: 687b ldr r3, [r7, #4]
|
|
8006d18: 681b ldr r3, [r3, #0]
|
|
8006d1a: 68fa ldr r2, [r7, #12]
|
|
8006d1c: 601a str r2, [r3, #0]
|
|
|
|
/* Initialize parameters for DMAMUX channel :
|
|
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
|
|
*/
|
|
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
|
|
8006d1e: 6878 ldr r0, [r7, #4]
|
|
8006d20: f000 fa82 bl 8007228 <DMA_CalcDMAMUXChannelBaseAndMask>
|
|
|
|
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
|
8006d24: 687b ldr r3, [r7, #4]
|
|
8006d26: 689b ldr r3, [r3, #8]
|
|
8006d28: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
8006d2c: d102 bne.n 8006d34 <HAL_DMA_Init+0xc4>
|
|
{
|
|
/* if memory to memory force the request to 0*/
|
|
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
|
|
8006d2e: 687b ldr r3, [r7, #4]
|
|
8006d30: 2200 movs r2, #0
|
|
8006d32: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Set peripheral request to DMAMUX channel */
|
|
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
|
|
8006d34: 687b ldr r3, [r7, #4]
|
|
8006d36: 685a ldr r2, [r3, #4]
|
|
8006d38: 687b ldr r3, [r7, #4]
|
|
8006d3a: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006d3c: f002 023f and.w r2, r2, #63 @ 0x3f
|
|
8006d40: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8006d42: 687b ldr r3, [r7, #4]
|
|
8006d44: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8006d46: 687a ldr r2, [r7, #4]
|
|
8006d48: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8006d4a: 605a str r2, [r3, #4]
|
|
|
|
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
|
8006d4c: 687b ldr r3, [r7, #4]
|
|
8006d4e: 685b ldr r3, [r3, #4]
|
|
8006d50: 2b00 cmp r3, #0
|
|
8006d52: d010 beq.n 8006d76 <HAL_DMA_Init+0x106>
|
|
8006d54: 687b ldr r3, [r7, #4]
|
|
8006d56: 685b ldr r3, [r3, #4]
|
|
8006d58: 2b04 cmp r3, #4
|
|
8006d5a: d80c bhi.n 8006d76 <HAL_DMA_Init+0x106>
|
|
{
|
|
/* Initialize parameters for DMAMUX request generator :
|
|
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
|
|
*/
|
|
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
|
|
8006d5c: 6878 ldr r0, [r7, #4]
|
|
8006d5e: f000 faa1 bl 80072a4 <DMA_CalcDMAMUXRequestGenBaseAndMask>
|
|
|
|
/* Reset the DMAMUX request generator register*/
|
|
hdma->DMAmuxRequestGen->RGCR = 0U;
|
|
8006d62: 687b ldr r3, [r7, #4]
|
|
8006d64: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006d66: 2200 movs r2, #0
|
|
8006d68: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8006d6a: 687b ldr r3, [r7, #4]
|
|
8006d6c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006d6e: 687a ldr r2, [r7, #4]
|
|
8006d70: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8006d72: 605a str r2, [r3, #4]
|
|
8006d74: e008 b.n 8006d88 <HAL_DMA_Init+0x118>
|
|
}
|
|
else
|
|
{
|
|
hdma->DMAmuxRequestGen = 0U;
|
|
8006d76: 687b ldr r3, [r7, #4]
|
|
8006d78: 2200 movs r2, #0
|
|
8006d7a: 655a str r2, [r3, #84] @ 0x54
|
|
hdma->DMAmuxRequestGenStatus = 0U;
|
|
8006d7c: 687b ldr r3, [r7, #4]
|
|
8006d7e: 2200 movs r2, #0
|
|
8006d80: 659a str r2, [r3, #88] @ 0x58
|
|
hdma->DMAmuxRequestGenStatusMask = 0U;
|
|
8006d82: 687b ldr r3, [r7, #4]
|
|
8006d84: 2200 movs r2, #0
|
|
8006d86: 65da str r2, [r3, #92] @ 0x5c
|
|
}
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8006d88: 687b ldr r3, [r7, #4]
|
|
8006d8a: 2200 movs r2, #0
|
|
8006d8c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Initialize the DMA state*/
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8006d8e: 687b ldr r3, [r7, #4]
|
|
8006d90: 2201 movs r2, #1
|
|
8006d92: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Allocate lock resource and initialize it */
|
|
hdma->Lock = HAL_UNLOCKED;
|
|
8006d96: 687b ldr r3, [r7, #4]
|
|
8006d98: 2200 movs r2, #0
|
|
8006d9a: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_OK;
|
|
8006d9e: 2300 movs r3, #0
|
|
}
|
|
8006da0: 4618 mov r0, r3
|
|
8006da2: 3710 adds r7, #16
|
|
8006da4: 46bd mov sp, r7
|
|
8006da6: bd80 pop {r7, pc}
|
|
8006da8: 40020407 .word 0x40020407
|
|
8006dac: bffdfff8 .word 0xbffdfff8
|
|
8006db0: cccccccd .word 0xcccccccd
|
|
8006db4: 40020000 .word 0x40020000
|
|
8006db8: bffdfbf8 .word 0xbffdfbf8
|
|
8006dbc: 40020400 .word 0x40020400
|
|
|
|
08006dc0 <HAL_DMA_Start_IT>:
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
|
|
uint32_t DataLength)
|
|
{
|
|
8006dc0: b580 push {r7, lr}
|
|
8006dc2: b086 sub sp, #24
|
|
8006dc4: af00 add r7, sp, #0
|
|
8006dc6: 60f8 str r0, [r7, #12]
|
|
8006dc8: 60b9 str r1, [r7, #8]
|
|
8006dca: 607a str r2, [r7, #4]
|
|
8006dcc: 603b str r3, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8006dce: 2300 movs r3, #0
|
|
8006dd0: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
8006dd2: 68fb ldr r3, [r7, #12]
|
|
8006dd4: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
8006dd8: 2b01 cmp r3, #1
|
|
8006dda: d101 bne.n 8006de0 <HAL_DMA_Start_IT+0x20>
|
|
8006ddc: 2302 movs r3, #2
|
|
8006dde: e066 b.n 8006eae <HAL_DMA_Start_IT+0xee>
|
|
8006de0: 68fb ldr r3, [r7, #12]
|
|
8006de2: 2201 movs r2, #1
|
|
8006de4: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
if (HAL_DMA_STATE_READY == hdma->State)
|
|
8006de8: 68fb ldr r3, [r7, #12]
|
|
8006dea: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
8006dee: b2db uxtb r3, r3
|
|
8006df0: 2b01 cmp r3, #1
|
|
8006df2: d155 bne.n 8006ea0 <HAL_DMA_Start_IT+0xe0>
|
|
{
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8006df4: 68fb ldr r3, [r7, #12]
|
|
8006df6: 2202 movs r2, #2
|
|
8006df8: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8006dfc: 68fb ldr r3, [r7, #12]
|
|
8006dfe: 2200 movs r2, #0
|
|
8006e00: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8006e02: 68fb ldr r3, [r7, #12]
|
|
8006e04: 681b ldr r3, [r3, #0]
|
|
8006e06: 681a ldr r2, [r3, #0]
|
|
8006e08: 68fb ldr r3, [r7, #12]
|
|
8006e0a: 681b ldr r3, [r3, #0]
|
|
8006e0c: f022 0201 bic.w r2, r2, #1
|
|
8006e10: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the source, destination address and the data length & clear flags*/
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
|
8006e12: 683b ldr r3, [r7, #0]
|
|
8006e14: 687a ldr r2, [r7, #4]
|
|
8006e16: 68b9 ldr r1, [r7, #8]
|
|
8006e18: 68f8 ldr r0, [r7, #12]
|
|
8006e1a: f000 f9c7 bl 80071ac <DMA_SetConfig>
|
|
|
|
/* Enable the transfer complete interrupt */
|
|
/* Enable the transfer Error interrupt */
|
|
if (NULL != hdma->XferHalfCpltCallback)
|
|
8006e1e: 68fb ldr r3, [r7, #12]
|
|
8006e20: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006e22: 2b00 cmp r3, #0
|
|
8006e24: d008 beq.n 8006e38 <HAL_DMA_Start_IT+0x78>
|
|
{
|
|
/* Enable the Half transfer complete interrupt as well */
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8006e26: 68fb ldr r3, [r7, #12]
|
|
8006e28: 681b ldr r3, [r3, #0]
|
|
8006e2a: 681a ldr r2, [r3, #0]
|
|
8006e2c: 68fb ldr r3, [r7, #12]
|
|
8006e2e: 681b ldr r3, [r3, #0]
|
|
8006e30: f042 020e orr.w r2, r2, #14
|
|
8006e34: 601a str r2, [r3, #0]
|
|
8006e36: e00f b.n 8006e58 <HAL_DMA_Start_IT+0x98>
|
|
}
|
|
else
|
|
{
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
|
8006e38: 68fb ldr r3, [r7, #12]
|
|
8006e3a: 681b ldr r3, [r3, #0]
|
|
8006e3c: 681a ldr r2, [r3, #0]
|
|
8006e3e: 68fb ldr r3, [r7, #12]
|
|
8006e40: 681b ldr r3, [r3, #0]
|
|
8006e42: f022 0204 bic.w r2, r2, #4
|
|
8006e46: 601a str r2, [r3, #0]
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
|
|
8006e48: 68fb ldr r3, [r7, #12]
|
|
8006e4a: 681b ldr r3, [r3, #0]
|
|
8006e4c: 681a ldr r2, [r3, #0]
|
|
8006e4e: 68fb ldr r3, [r7, #12]
|
|
8006e50: 681b ldr r3, [r3, #0]
|
|
8006e52: f042 020a orr.w r2, r2, #10
|
|
8006e56: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Check if DMAMUX Synchronization is enabled*/
|
|
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
|
|
8006e58: 68fb ldr r3, [r7, #12]
|
|
8006e5a: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006e5c: 681b ldr r3, [r3, #0]
|
|
8006e5e: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8006e62: 2b00 cmp r3, #0
|
|
8006e64: d007 beq.n 8006e76 <HAL_DMA_Start_IT+0xb6>
|
|
{
|
|
/* Enable DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
|
|
8006e66: 68fb ldr r3, [r7, #12]
|
|
8006e68: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006e6a: 681a ldr r2, [r3, #0]
|
|
8006e6c: 68fb ldr r3, [r7, #12]
|
|
8006e6e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006e70: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
8006e74: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
8006e76: 68fb ldr r3, [r7, #12]
|
|
8006e78: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006e7a: 2b00 cmp r3, #0
|
|
8006e7c: d007 beq.n 8006e8e <HAL_DMA_Start_IT+0xce>
|
|
{
|
|
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
|
|
/* enable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
|
|
8006e7e: 68fb ldr r3, [r7, #12]
|
|
8006e80: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006e82: 681a ldr r2, [r3, #0]
|
|
8006e84: 68fb ldr r3, [r7, #12]
|
|
8006e86: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006e88: f442 7280 orr.w r2, r2, #256 @ 0x100
|
|
8006e8c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_DMA_ENABLE(hdma);
|
|
8006e8e: 68fb ldr r3, [r7, #12]
|
|
8006e90: 681b ldr r3, [r3, #0]
|
|
8006e92: 681a ldr r2, [r3, #0]
|
|
8006e94: 68fb ldr r3, [r7, #12]
|
|
8006e96: 681b ldr r3, [r3, #0]
|
|
8006e98: f042 0201 orr.w r2, r2, #1
|
|
8006e9c: 601a str r2, [r3, #0]
|
|
8006e9e: e005 b.n 8006eac <HAL_DMA_Start_IT+0xec>
|
|
}
|
|
else
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8006ea0: 68fb ldr r3, [r7, #12]
|
|
8006ea2: 2200 movs r2, #0
|
|
8006ea4: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Remain BUSY */
|
|
status = HAL_BUSY;
|
|
8006ea8: 2302 movs r3, #2
|
|
8006eaa: 75fb strb r3, [r7, #23]
|
|
}
|
|
return status;
|
|
8006eac: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8006eae: 4618 mov r0, r3
|
|
8006eb0: 3718 adds r7, #24
|
|
8006eb2: 46bd mov sp, r7
|
|
8006eb4: bd80 pop {r7, pc}
|
|
|
|
08006eb6 <HAL_DMA_Abort>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006eb6: b480 push {r7}
|
|
8006eb8: b083 sub sp, #12
|
|
8006eba: af00 add r7, sp, #0
|
|
8006ebc: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the DMA peripheral handle */
|
|
if (NULL == hdma)
|
|
8006ebe: 687b ldr r3, [r7, #4]
|
|
8006ec0: 2b00 cmp r3, #0
|
|
8006ec2: d101 bne.n 8006ec8 <HAL_DMA_Abort+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8006ec4: 2301 movs r3, #1
|
|
8006ec6: e04f b.n 8006f68 <HAL_DMA_Abort+0xb2>
|
|
}
|
|
|
|
/* Check the DMA peripheral state */
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
|
8006ec8: 687b ldr r3, [r7, #4]
|
|
8006eca: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
8006ece: b2db uxtb r3, r3
|
|
8006ed0: 2b02 cmp r3, #2
|
|
8006ed2: d008 beq.n 8006ee6 <HAL_DMA_Abort+0x30>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8006ed4: 687b ldr r3, [r7, #4]
|
|
8006ed6: 2204 movs r2, #4
|
|
8006ed8: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8006eda: 687b ldr r3, [r7, #4]
|
|
8006edc: 2200 movs r2, #0
|
|
8006ede: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8006ee2: 2301 movs r3, #1
|
|
8006ee4: e040 b.n 8006f68 <HAL_DMA_Abort+0xb2>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8006ee6: 687b ldr r3, [r7, #4]
|
|
8006ee8: 681b ldr r3, [r3, #0]
|
|
8006eea: 681a ldr r2, [r3, #0]
|
|
8006eec: 687b ldr r3, [r7, #4]
|
|
8006eee: 681b ldr r3, [r3, #0]
|
|
8006ef0: f022 020e bic.w r2, r2, #14
|
|
8006ef4: 601a str r2, [r3, #0]
|
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
8006ef6: 687b ldr r3, [r7, #4]
|
|
8006ef8: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006efa: 681a ldr r2, [r3, #0]
|
|
8006efc: 687b ldr r3, [r7, #4]
|
|
8006efe: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006f00: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8006f04: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8006f06: 687b ldr r3, [r7, #4]
|
|
8006f08: 681b ldr r3, [r3, #0]
|
|
8006f0a: 681a ldr r2, [r3, #0]
|
|
8006f0c: 687b ldr r3, [r7, #4]
|
|
8006f0e: 681b ldr r3, [r3, #0]
|
|
8006f10: f022 0201 bic.w r2, r2, #1
|
|
8006f14: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
|
8006f16: 687b ldr r3, [r7, #4]
|
|
8006f18: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8006f1a: f003 021c and.w r2, r3, #28
|
|
8006f1e: 687b ldr r3, [r7, #4]
|
|
8006f20: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8006f22: 2101 movs r1, #1
|
|
8006f24: fa01 f202 lsl.w r2, r1, r2
|
|
8006f28: 605a str r2, [r3, #4]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8006f2a: 687b ldr r3, [r7, #4]
|
|
8006f2c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8006f2e: 687a ldr r2, [r7, #4]
|
|
8006f30: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8006f32: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
8006f34: 687b ldr r3, [r7, #4]
|
|
8006f36: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006f38: 2b00 cmp r3, #0
|
|
8006f3a: d00c beq.n 8006f56 <HAL_DMA_Abort+0xa0>
|
|
{
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
|
/* disable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
8006f3c: 687b ldr r3, [r7, #4]
|
|
8006f3e: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006f40: 681a ldr r2, [r3, #0]
|
|
8006f42: 687b ldr r3, [r7, #4]
|
|
8006f44: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006f46: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8006f4a: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8006f4c: 687b ldr r3, [r7, #4]
|
|
8006f4e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8006f50: 687a ldr r2, [r7, #4]
|
|
8006f52: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8006f54: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8006f56: 687b ldr r3, [r7, #4]
|
|
8006f58: 2201 movs r2, #1
|
|
8006f5a: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8006f5e: 687b ldr r3, [r7, #4]
|
|
8006f60: 2200 movs r2, #0
|
|
8006f62: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006f66: 2300 movs r3, #0
|
|
}
|
|
8006f68: 4618 mov r0, r3
|
|
8006f6a: 370c adds r7, #12
|
|
8006f6c: 46bd mov sp, r7
|
|
8006f6e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f72: 4770 bx lr
|
|
|
|
08006f74 <HAL_DMA_Abort_IT>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006f74: b580 push {r7, lr}
|
|
8006f76: b084 sub sp, #16
|
|
8006f78: af00 add r7, sp, #0
|
|
8006f7a: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8006f7c: 2300 movs r3, #0
|
|
8006f7e: 73fb strb r3, [r7, #15]
|
|
|
|
if (HAL_DMA_STATE_BUSY != hdma->State)
|
|
8006f80: 687b ldr r3, [r7, #4]
|
|
8006f82: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
8006f86: b2db uxtb r3, r3
|
|
8006f88: 2b02 cmp r3, #2
|
|
8006f8a: d005 beq.n 8006f98 <HAL_DMA_Abort_IT+0x24>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8006f8c: 687b ldr r3, [r7, #4]
|
|
8006f8e: 2204 movs r2, #4
|
|
8006f90: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
status = HAL_ERROR;
|
|
8006f92: 2301 movs r3, #1
|
|
8006f94: 73fb strb r3, [r7, #15]
|
|
8006f96: e047 b.n 8007028 <HAL_DMA_Abort_IT+0xb4>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8006f98: 687b ldr r3, [r7, #4]
|
|
8006f9a: 681b ldr r3, [r3, #0]
|
|
8006f9c: 681a ldr r2, [r3, #0]
|
|
8006f9e: 687b ldr r3, [r7, #4]
|
|
8006fa0: 681b ldr r3, [r3, #0]
|
|
8006fa2: f022 020e bic.w r2, r2, #14
|
|
8006fa6: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8006fa8: 687b ldr r3, [r7, #4]
|
|
8006faa: 681b ldr r3, [r3, #0]
|
|
8006fac: 681a ldr r2, [r3, #0]
|
|
8006fae: 687b ldr r3, [r7, #4]
|
|
8006fb0: 681b ldr r3, [r3, #0]
|
|
8006fb2: f022 0201 bic.w r2, r2, #1
|
|
8006fb6: 601a str r2, [r3, #0]
|
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
8006fb8: 687b ldr r3, [r7, #4]
|
|
8006fba: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006fbc: 681a ldr r2, [r3, #0]
|
|
8006fbe: 687b ldr r3, [r7, #4]
|
|
8006fc0: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8006fc2: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8006fc6: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
|
8006fc8: 687b ldr r3, [r7, #4]
|
|
8006fca: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8006fcc: f003 021c and.w r2, r3, #28
|
|
8006fd0: 687b ldr r3, [r7, #4]
|
|
8006fd2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8006fd4: 2101 movs r1, #1
|
|
8006fd6: fa01 f202 lsl.w r2, r1, r2
|
|
8006fda: 605a str r2, [r3, #4]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8006fdc: 687b ldr r3, [r7, #4]
|
|
8006fde: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8006fe0: 687a ldr r2, [r7, #4]
|
|
8006fe2: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8006fe4: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
8006fe6: 687b ldr r3, [r7, #4]
|
|
8006fe8: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006fea: 2b00 cmp r3, #0
|
|
8006fec: d00c beq.n 8007008 <HAL_DMA_Abort_IT+0x94>
|
|
{
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
|
/* disable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
8006fee: 687b ldr r3, [r7, #4]
|
|
8006ff0: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006ff2: 681a ldr r2, [r3, #0]
|
|
8006ff4: 687b ldr r3, [r7, #4]
|
|
8006ff6: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006ff8: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8006ffc: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8006ffe: 687b ldr r3, [r7, #4]
|
|
8007000: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8007002: 687a ldr r2, [r7, #4]
|
|
8007004: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8007006: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8007008: 687b ldr r3, [r7, #4]
|
|
800700a: 2201 movs r2, #1
|
|
800700c: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8007010: 687b ldr r3, [r7, #4]
|
|
8007012: 2200 movs r2, #0
|
|
8007014: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Call User Abort callback */
|
|
if (hdma->XferAbortCallback != NULL)
|
|
8007018: 687b ldr r3, [r7, #4]
|
|
800701a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800701c: 2b00 cmp r3, #0
|
|
800701e: d003 beq.n 8007028 <HAL_DMA_Abort_IT+0xb4>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
8007020: 687b ldr r3, [r7, #4]
|
|
8007022: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007024: 6878 ldr r0, [r7, #4]
|
|
8007026: 4798 blx r3
|
|
}
|
|
}
|
|
return status;
|
|
8007028: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800702a: 4618 mov r0, r3
|
|
800702c: 3710 adds r7, #16
|
|
800702e: 46bd mov sp, r7
|
|
8007030: bd80 pop {r7, pc}
|
|
|
|
08007032 <HAL_DMA_IRQHandler>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8007032: b580 push {r7, lr}
|
|
8007034: b084 sub sp, #16
|
|
8007036: af00 add r7, sp, #0
|
|
8007038: 6078 str r0, [r7, #4]
|
|
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
|
800703a: 687b ldr r3, [r7, #4]
|
|
800703c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800703e: 681b ldr r3, [r3, #0]
|
|
8007040: 60fb str r3, [r7, #12]
|
|
uint32_t source_it = hdma->Instance->CCR;
|
|
8007042: 687b ldr r3, [r7, #4]
|
|
8007044: 681b ldr r3, [r3, #0]
|
|
8007046: 681b ldr r3, [r3, #0]
|
|
8007048: 60bb str r3, [r7, #8]
|
|
|
|
/* Half Transfer Complete Interrupt management ******************************/
|
|
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
|
|
800704a: 687b ldr r3, [r7, #4]
|
|
800704c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800704e: f003 031c and.w r3, r3, #28
|
|
8007052: 2204 movs r2, #4
|
|
8007054: 409a lsls r2, r3
|
|
8007056: 68fb ldr r3, [r7, #12]
|
|
8007058: 4013 ands r3, r2
|
|
800705a: 2b00 cmp r3, #0
|
|
800705c: d026 beq.n 80070ac <HAL_DMA_IRQHandler+0x7a>
|
|
800705e: 68bb ldr r3, [r7, #8]
|
|
8007060: f003 0304 and.w r3, r3, #4
|
|
8007064: 2b00 cmp r3, #0
|
|
8007066: d021 beq.n 80070ac <HAL_DMA_IRQHandler+0x7a>
|
|
{
|
|
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
8007068: 687b ldr r3, [r7, #4]
|
|
800706a: 681b ldr r3, [r3, #0]
|
|
800706c: 681b ldr r3, [r3, #0]
|
|
800706e: f003 0320 and.w r3, r3, #32
|
|
8007072: 2b00 cmp r3, #0
|
|
8007074: d107 bne.n 8007086 <HAL_DMA_IRQHandler+0x54>
|
|
{
|
|
/* Disable the half transfer interrupt */
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
|
8007076: 687b ldr r3, [r7, #4]
|
|
8007078: 681b ldr r3, [r3, #0]
|
|
800707a: 681a ldr r2, [r3, #0]
|
|
800707c: 687b ldr r3, [r7, #4]
|
|
800707e: 681b ldr r3, [r3, #0]
|
|
8007080: f022 0204 bic.w r2, r2, #4
|
|
8007084: 601a str r2, [r3, #0]
|
|
}
|
|
/* Clear the half transfer complete flag */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
8007086: 687b ldr r3, [r7, #4]
|
|
8007088: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800708a: f003 021c and.w r2, r3, #28
|
|
800708e: 687b ldr r3, [r7, #4]
|
|
8007090: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007092: 2104 movs r1, #4
|
|
8007094: fa01 f202 lsl.w r2, r1, r2
|
|
8007098: 605a str r2, [r3, #4]
|
|
|
|
/* DMA peripheral state is not updated in Half Transfer */
|
|
/* but in Transfer Complete case */
|
|
|
|
if (hdma->XferHalfCpltCallback != NULL)
|
|
800709a: 687b ldr r3, [r7, #4]
|
|
800709c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800709e: 2b00 cmp r3, #0
|
|
80070a0: d071 beq.n 8007186 <HAL_DMA_IRQHandler+0x154>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
80070a2: 687b ldr r3, [r7, #4]
|
|
80070a4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80070a6: 6878 ldr r0, [r7, #4]
|
|
80070a8: 4798 blx r3
|
|
if (hdma->XferHalfCpltCallback != NULL)
|
|
80070aa: e06c b.n 8007186 <HAL_DMA_IRQHandler+0x154>
|
|
}
|
|
}
|
|
|
|
/* Transfer Complete Interrupt management ***********************************/
|
|
else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
|
|
80070ac: 687b ldr r3, [r7, #4]
|
|
80070ae: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80070b0: f003 031c and.w r3, r3, #28
|
|
80070b4: 2202 movs r2, #2
|
|
80070b6: 409a lsls r2, r3
|
|
80070b8: 68fb ldr r3, [r7, #12]
|
|
80070ba: 4013 ands r3, r2
|
|
80070bc: 2b00 cmp r3, #0
|
|
80070be: d02e beq.n 800711e <HAL_DMA_IRQHandler+0xec>
|
|
80070c0: 68bb ldr r3, [r7, #8]
|
|
80070c2: f003 0302 and.w r3, r3, #2
|
|
80070c6: 2b00 cmp r3, #0
|
|
80070c8: d029 beq.n 800711e <HAL_DMA_IRQHandler+0xec>
|
|
{
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
80070ca: 687b ldr r3, [r7, #4]
|
|
80070cc: 681b ldr r3, [r3, #0]
|
|
80070ce: 681b ldr r3, [r3, #0]
|
|
80070d0: f003 0320 and.w r3, r3, #32
|
|
80070d4: 2b00 cmp r3, #0
|
|
80070d6: d10b bne.n 80070f0 <HAL_DMA_IRQHandler+0xbe>
|
|
{
|
|
/* Disable the transfer complete and error interrupt */
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
|
80070d8: 687b ldr r3, [r7, #4]
|
|
80070da: 681b ldr r3, [r3, #0]
|
|
80070dc: 681a ldr r2, [r3, #0]
|
|
80070de: 687b ldr r3, [r7, #4]
|
|
80070e0: 681b ldr r3, [r3, #0]
|
|
80070e2: f022 020a bic.w r2, r2, #10
|
|
80070e6: 601a str r2, [r3, #0]
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80070e8: 687b ldr r3, [r7, #4]
|
|
80070ea: 2201 movs r2, #1
|
|
80070ec: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
}
|
|
/* Clear the transfer complete flag */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
|
|
80070f0: 687b ldr r3, [r7, #4]
|
|
80070f2: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80070f4: f003 021c and.w r2, r3, #28
|
|
80070f8: 687b ldr r3, [r7, #4]
|
|
80070fa: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80070fc: 2102 movs r1, #2
|
|
80070fe: fa01 f202 lsl.w r2, r1, r2
|
|
8007102: 605a str r2, [r3, #4]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8007104: 687b ldr r3, [r7, #4]
|
|
8007106: 2200 movs r2, #0
|
|
8007108: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
if (hdma->XferCpltCallback != NULL)
|
|
800710c: 687b ldr r3, [r7, #4]
|
|
800710e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007110: 2b00 cmp r3, #0
|
|
8007112: d038 beq.n 8007186 <HAL_DMA_IRQHandler+0x154>
|
|
{
|
|
/* Transfer complete callback */
|
|
hdma->XferCpltCallback(hdma);
|
|
8007114: 687b ldr r3, [r7, #4]
|
|
8007116: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007118: 6878 ldr r0, [r7, #4]
|
|
800711a: 4798 blx r3
|
|
if (hdma->XferCpltCallback != NULL)
|
|
800711c: e033 b.n 8007186 <HAL_DMA_IRQHandler+0x154>
|
|
}
|
|
}
|
|
|
|
/* Transfer Error Interrupt management **************************************/
|
|
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
|
|
800711e: 687b ldr r3, [r7, #4]
|
|
8007120: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007122: f003 031c and.w r3, r3, #28
|
|
8007126: 2208 movs r2, #8
|
|
8007128: 409a lsls r2, r3
|
|
800712a: 68fb ldr r3, [r7, #12]
|
|
800712c: 4013 ands r3, r2
|
|
800712e: 2b00 cmp r3, #0
|
|
8007130: d02a beq.n 8007188 <HAL_DMA_IRQHandler+0x156>
|
|
8007132: 68bb ldr r3, [r7, #8]
|
|
8007134: f003 0308 and.w r3, r3, #8
|
|
8007138: 2b00 cmp r3, #0
|
|
800713a: d025 beq.n 8007188 <HAL_DMA_IRQHandler+0x156>
|
|
{
|
|
/* When a DMA transfer error occurs */
|
|
/* A hardware clear of its EN bits is performed */
|
|
/* Disable ALL DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
800713c: 687b ldr r3, [r7, #4]
|
|
800713e: 681b ldr r3, [r3, #0]
|
|
8007140: 681a ldr r2, [r3, #0]
|
|
8007142: 687b ldr r3, [r7, #4]
|
|
8007144: 681b ldr r3, [r3, #0]
|
|
8007146: f022 020e bic.w r2, r2, #14
|
|
800714a: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
|
800714c: 687b ldr r3, [r7, #4]
|
|
800714e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007150: f003 021c and.w r2, r3, #28
|
|
8007154: 687b ldr r3, [r7, #4]
|
|
8007156: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007158: 2101 movs r1, #1
|
|
800715a: fa01 f202 lsl.w r2, r1, r2
|
|
800715e: 605a str r2, [r3, #4]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
|
8007160: 687b ldr r3, [r7, #4]
|
|
8007162: 2201 movs r2, #1
|
|
8007164: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8007166: 687b ldr r3, [r7, #4]
|
|
8007168: 2201 movs r2, #1
|
|
800716a: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
800716e: 687b ldr r3, [r7, #4]
|
|
8007170: 2200 movs r2, #0
|
|
8007172: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
if (hdma->XferErrorCallback != NULL)
|
|
8007176: 687b ldr r3, [r7, #4]
|
|
8007178: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800717a: 2b00 cmp r3, #0
|
|
800717c: d004 beq.n 8007188 <HAL_DMA_IRQHandler+0x156>
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
800717e: 687b ldr r3, [r7, #4]
|
|
8007180: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8007182: 6878 ldr r0, [r7, #4]
|
|
8007184: 4798 blx r3
|
|
}
|
|
else
|
|
{
|
|
/* Nothing To Do */
|
|
}
|
|
return;
|
|
8007186: bf00 nop
|
|
8007188: bf00 nop
|
|
}
|
|
800718a: 3710 adds r7, #16
|
|
800718c: 46bd mov sp, r7
|
|
800718e: bd80 pop {r7, pc}
|
|
|
|
08007190 <HAL_DMA_GetState>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL state
|
|
*/
|
|
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8007190: b480 push {r7}
|
|
8007192: b083 sub sp, #12
|
|
8007194: af00 add r7, sp, #0
|
|
8007196: 6078 str r0, [r7, #4]
|
|
/* Return DMA handle state */
|
|
return hdma->State;
|
|
8007198: 687b ldr r3, [r7, #4]
|
|
800719a: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
800719e: b2db uxtb r3, r3
|
|
}
|
|
80071a0: 4618 mov r0, r3
|
|
80071a2: 370c adds r7, #12
|
|
80071a4: 46bd mov sp, r7
|
|
80071a6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80071aa: 4770 bx lr
|
|
|
|
080071ac <DMA_SetConfig>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
80071ac: b480 push {r7}
|
|
80071ae: b085 sub sp, #20
|
|
80071b0: af00 add r7, sp, #0
|
|
80071b2: 60f8 str r0, [r7, #12]
|
|
80071b4: 60b9 str r1, [r7, #8]
|
|
80071b6: 607a str r2, [r7, #4]
|
|
80071b8: 603b str r3, [r7, #0]
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
80071ba: 68fb ldr r3, [r7, #12]
|
|
80071bc: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80071be: 68fa ldr r2, [r7, #12]
|
|
80071c0: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
80071c2: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
80071c4: 68fb ldr r3, [r7, #12]
|
|
80071c6: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80071c8: 2b00 cmp r3, #0
|
|
80071ca: d004 beq.n 80071d6 <DMA_SetConfig+0x2a>
|
|
{
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
80071cc: 68fb ldr r3, [r7, #12]
|
|
80071ce: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80071d0: 68fa ldr r2, [r7, #12]
|
|
80071d2: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
80071d4: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
|
|
80071d6: 68fb ldr r3, [r7, #12]
|
|
80071d8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80071da: f003 021c and.w r2, r3, #28
|
|
80071de: 68fb ldr r3, [r7, #12]
|
|
80071e0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80071e2: 2101 movs r1, #1
|
|
80071e4: fa01 f202 lsl.w r2, r1, r2
|
|
80071e8: 605a str r2, [r3, #4]
|
|
|
|
/* Configure DMA Channel data length */
|
|
hdma->Instance->CNDTR = DataLength;
|
|
80071ea: 68fb ldr r3, [r7, #12]
|
|
80071ec: 681b ldr r3, [r3, #0]
|
|
80071ee: 683a ldr r2, [r7, #0]
|
|
80071f0: 605a str r2, [r3, #4]
|
|
|
|
/* Memory to Peripheral */
|
|
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
80071f2: 68fb ldr r3, [r7, #12]
|
|
80071f4: 689b ldr r3, [r3, #8]
|
|
80071f6: 2b10 cmp r3, #16
|
|
80071f8: d108 bne.n 800720c <DMA_SetConfig+0x60>
|
|
{
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CPAR = DstAddress;
|
|
80071fa: 68fb ldr r3, [r7, #12]
|
|
80071fc: 681b ldr r3, [r3, #0]
|
|
80071fe: 687a ldr r2, [r7, #4]
|
|
8007200: 609a str r2, [r3, #8]
|
|
|
|
/* Configure DMA Channel source address */
|
|
hdma->Instance->CMAR = SrcAddress;
|
|
8007202: 68fb ldr r3, [r7, #12]
|
|
8007204: 681b ldr r3, [r3, #0]
|
|
8007206: 68ba ldr r2, [r7, #8]
|
|
8007208: 60da str r2, [r3, #12]
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CMAR = DstAddress;
|
|
}
|
|
}
|
|
800720a: e007 b.n 800721c <DMA_SetConfig+0x70>
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
800720c: 68fb ldr r3, [r7, #12]
|
|
800720e: 681b ldr r3, [r3, #0]
|
|
8007210: 68ba ldr r2, [r7, #8]
|
|
8007212: 609a str r2, [r3, #8]
|
|
hdma->Instance->CMAR = DstAddress;
|
|
8007214: 68fb ldr r3, [r7, #12]
|
|
8007216: 681b ldr r3, [r3, #0]
|
|
8007218: 687a ldr r2, [r7, #4]
|
|
800721a: 60da str r2, [r3, #12]
|
|
}
|
|
800721c: bf00 nop
|
|
800721e: 3714 adds r7, #20
|
|
8007220: 46bd mov sp, r7
|
|
8007222: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007226: 4770 bx lr
|
|
|
|
08007228 <DMA_CalcDMAMUXChannelBaseAndMask>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval None
|
|
*/
|
|
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8007228: b480 push {r7}
|
|
800722a: b085 sub sp, #20
|
|
800722c: af00 add r7, sp, #0
|
|
800722e: 6078 str r0, [r7, #4]
|
|
uint32_t channel_number;
|
|
|
|
/* check if instance is not outside the DMA channel range */
|
|
#if defined(DMA2)
|
|
if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
|
|
8007230: 687b ldr r3, [r7, #4]
|
|
8007232: 681b ldr r3, [r3, #0]
|
|
8007234: 461a mov r2, r3
|
|
8007236: 4b17 ldr r3, [pc, #92] @ (8007294 <DMA_CalcDMAMUXChannelBaseAndMask+0x6c>)
|
|
8007238: 429a cmp r2, r3
|
|
800723a: d80a bhi.n 8007252 <DMA_CalcDMAMUXChannelBaseAndMask+0x2a>
|
|
{
|
|
/* DMA1 */
|
|
hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
|
|
800723c: 687b ldr r3, [r7, #4]
|
|
800723e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007240: 089b lsrs r3, r3, #2
|
|
8007242: 009b lsls r3, r3, #2
|
|
8007244: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000
|
|
8007248: f503 3302 add.w r3, r3, #133120 @ 0x20800
|
|
800724c: 687a ldr r2, [r7, #4]
|
|
800724e: 6493 str r3, [r2, #72] @ 0x48
|
|
8007250: e007 b.n 8007262 <DMA_CalcDMAMUXChannelBaseAndMask+0x3a>
|
|
}
|
|
else
|
|
{
|
|
/* DMA2 */
|
|
hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
|
|
8007252: 687b ldr r3, [r7, #4]
|
|
8007254: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007256: 089b lsrs r3, r3, #2
|
|
8007258: 009a lsls r2, r3, #2
|
|
800725a: 4b0f ldr r3, [pc, #60] @ (8007298 <DMA_CalcDMAMUXChannelBaseAndMask+0x70>)
|
|
800725c: 4413 add r3, r2
|
|
800725e: 687a ldr r2, [r7, #4]
|
|
8007260: 6493 str r3, [r2, #72] @ 0x48
|
|
}
|
|
#else
|
|
/* DMA1 */
|
|
hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
|
|
#endif /* DMA2 */
|
|
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
|
|
8007262: 687b ldr r3, [r7, #4]
|
|
8007264: 681b ldr r3, [r3, #0]
|
|
8007266: b2db uxtb r3, r3
|
|
8007268: 3b08 subs r3, #8
|
|
800726a: 4a0c ldr r2, [pc, #48] @ (800729c <DMA_CalcDMAMUXChannelBaseAndMask+0x74>)
|
|
800726c: fba2 2303 umull r2, r3, r2, r3
|
|
8007270: 091b lsrs r3, r3, #4
|
|
8007272: 60fb str r3, [r7, #12]
|
|
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
|
|
8007274: 687b ldr r3, [r7, #4]
|
|
8007276: 4a0a ldr r2, [pc, #40] @ (80072a0 <DMA_CalcDMAMUXChannelBaseAndMask+0x78>)
|
|
8007278: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */
|
|
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
|
|
800727a: 68fb ldr r3, [r7, #12]
|
|
800727c: f003 031f and.w r3, r3, #31
|
|
8007280: 2201 movs r2, #1
|
|
8007282: 409a lsls r2, r3
|
|
8007284: 687b ldr r3, [r7, #4]
|
|
8007286: 651a str r2, [r3, #80] @ 0x50
|
|
}
|
|
8007288: bf00 nop
|
|
800728a: 3714 adds r7, #20
|
|
800728c: 46bd mov sp, r7
|
|
800728e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007292: 4770 bx lr
|
|
8007294: 40020407 .word 0x40020407
|
|
8007298: 4002081c .word 0x4002081c
|
|
800729c: cccccccd .word 0xcccccccd
|
|
80072a0: 40020880 .word 0x40020880
|
|
|
|
080072a4 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval None
|
|
*/
|
|
|
|
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80072a4: b480 push {r7}
|
|
80072a6: b085 sub sp, #20
|
|
80072a8: af00 add r7, sp, #0
|
|
80072aa: 6078 str r0, [r7, #4]
|
|
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
|
|
80072ac: 687b ldr r3, [r7, #4]
|
|
80072ae: 685b ldr r3, [r3, #4]
|
|
80072b0: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
80072b4: 60fb str r3, [r7, #12]
|
|
|
|
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
|
|
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
|
|
80072b6: 68fa ldr r2, [r7, #12]
|
|
80072b8: 4b0b ldr r3, [pc, #44] @ (80072e8 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
|
|
80072ba: 4413 add r3, r2
|
|
80072bc: 009b lsls r3, r3, #2
|
|
80072be: 461a mov r2, r3
|
|
80072c0: 687b ldr r3, [r7, #4]
|
|
80072c2: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
|
|
80072c4: 687b ldr r3, [r7, #4]
|
|
80072c6: 4a09 ldr r2, [pc, #36] @ (80072ec <DMA_CalcDMAMUXRequestGenBaseAndMask+0x48>)
|
|
80072c8: 659a str r2, [r3, #88] @ 0x58
|
|
|
|
/* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
|
|
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
|
|
80072ca: 68fb ldr r3, [r7, #12]
|
|
80072cc: 3b01 subs r3, #1
|
|
80072ce: f003 0303 and.w r3, r3, #3
|
|
80072d2: 2201 movs r2, #1
|
|
80072d4: 409a lsls r2, r3
|
|
80072d6: 687b ldr r3, [r7, #4]
|
|
80072d8: 65da str r2, [r3, #92] @ 0x5c
|
|
}
|
|
80072da: bf00 nop
|
|
80072dc: 3714 adds r7, #20
|
|
80072de: 46bd mov sp, r7
|
|
80072e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80072e4: 4770 bx lr
|
|
80072e6: bf00 nop
|
|
80072e8: 1000823f .word 0x1000823f
|
|
80072ec: 40020940 .word 0x40020940
|
|
|
|
080072f0 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80072f0: b480 push {r7}
|
|
80072f2: b087 sub sp, #28
|
|
80072f4: af00 add r7, sp, #0
|
|
80072f6: 6078 str r0, [r7, #4]
|
|
80072f8: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00UL;
|
|
80072fa: 2300 movs r3, #0
|
|
80072fc: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80072fe: e14c b.n 800759a <HAL_GPIO_Init+0x2aa>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
8007300: 683b ldr r3, [r7, #0]
|
|
8007302: 681a ldr r2, [r3, #0]
|
|
8007304: 2101 movs r1, #1
|
|
8007306: 697b ldr r3, [r7, #20]
|
|
8007308: fa01 f303 lsl.w r3, r1, r3
|
|
800730c: 4013 ands r3, r2
|
|
800730e: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
8007310: 68fb ldr r3, [r7, #12]
|
|
8007312: 2b00 cmp r3, #0
|
|
8007314: f000 813e beq.w 8007594 <HAL_GPIO_Init+0x2a4>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
8007318: 683b ldr r3, [r7, #0]
|
|
800731a: 685b ldr r3, [r3, #4]
|
|
800731c: f003 0303 and.w r3, r3, #3
|
|
8007320: 2b01 cmp r3, #1
|
|
8007322: d005 beq.n 8007330 <HAL_GPIO_Init+0x40>
|
|
8007324: 683b ldr r3, [r7, #0]
|
|
8007326: 685b ldr r3, [r3, #4]
|
|
8007328: f003 0303 and.w r3, r3, #3
|
|
800732c: 2b02 cmp r3, #2
|
|
800732e: d130 bne.n 8007392 <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8007330: 687b ldr r3, [r7, #4]
|
|
8007332: 689b ldr r3, [r3, #8]
|
|
8007334: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
8007336: 697b ldr r3, [r7, #20]
|
|
8007338: 005b lsls r3, r3, #1
|
|
800733a: 2203 movs r2, #3
|
|
800733c: fa02 f303 lsl.w r3, r2, r3
|
|
8007340: 43db mvns r3, r3
|
|
8007342: 693a ldr r2, [r7, #16]
|
|
8007344: 4013 ands r3, r2
|
|
8007346: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
8007348: 683b ldr r3, [r7, #0]
|
|
800734a: 68da ldr r2, [r3, #12]
|
|
800734c: 697b ldr r3, [r7, #20]
|
|
800734e: 005b lsls r3, r3, #1
|
|
8007350: fa02 f303 lsl.w r3, r2, r3
|
|
8007354: 693a ldr r2, [r7, #16]
|
|
8007356: 4313 orrs r3, r2
|
|
8007358: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
800735a: 687b ldr r3, [r7, #4]
|
|
800735c: 693a ldr r2, [r7, #16]
|
|
800735e: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8007360: 687b ldr r3, [r7, #4]
|
|
8007362: 685b ldr r3, [r3, #4]
|
|
8007364: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8007366: 2201 movs r2, #1
|
|
8007368: 697b ldr r3, [r7, #20]
|
|
800736a: fa02 f303 lsl.w r3, r2, r3
|
|
800736e: 43db mvns r3, r3
|
|
8007370: 693a ldr r2, [r7, #16]
|
|
8007372: 4013 ands r3, r2
|
|
8007374: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8007376: 683b ldr r3, [r7, #0]
|
|
8007378: 685b ldr r3, [r3, #4]
|
|
800737a: 091b lsrs r3, r3, #4
|
|
800737c: f003 0201 and.w r2, r3, #1
|
|
8007380: 697b ldr r3, [r7, #20]
|
|
8007382: fa02 f303 lsl.w r3, r2, r3
|
|
8007386: 693a ldr r2, [r7, #16]
|
|
8007388: 4313 orrs r3, r2
|
|
800738a: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
800738c: 687b ldr r3, [r7, #4]
|
|
800738e: 693a ldr r2, [r7, #16]
|
|
8007390: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
8007392: 683b ldr r3, [r7, #0]
|
|
8007394: 685b ldr r3, [r3, #4]
|
|
8007396: f003 0303 and.w r3, r3, #3
|
|
800739a: 2b03 cmp r3, #3
|
|
800739c: d017 beq.n 80073ce <HAL_GPIO_Init+0xde>
|
|
{
|
|
temp = GPIOx->PUPDR;
|
|
800739e: 687b ldr r3, [r7, #4]
|
|
80073a0: 68db ldr r3, [r3, #12]
|
|
80073a2: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
80073a4: 697b ldr r3, [r7, #20]
|
|
80073a6: 005b lsls r3, r3, #1
|
|
80073a8: 2203 movs r2, #3
|
|
80073aa: fa02 f303 lsl.w r3, r2, r3
|
|
80073ae: 43db mvns r3, r3
|
|
80073b0: 693a ldr r2, [r7, #16]
|
|
80073b2: 4013 ands r3, r2
|
|
80073b4: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
80073b6: 683b ldr r3, [r7, #0]
|
|
80073b8: 689a ldr r2, [r3, #8]
|
|
80073ba: 697b ldr r3, [r7, #20]
|
|
80073bc: 005b lsls r3, r3, #1
|
|
80073be: fa02 f303 lsl.w r3, r2, r3
|
|
80073c2: 693a ldr r2, [r7, #16]
|
|
80073c4: 4313 orrs r3, r2
|
|
80073c6: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
80073c8: 687b ldr r3, [r7, #4]
|
|
80073ca: 693a ldr r2, [r7, #16]
|
|
80073cc: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80073ce: 683b ldr r3, [r7, #0]
|
|
80073d0: 685b ldr r3, [r3, #4]
|
|
80073d2: f003 0303 and.w r3, r3, #3
|
|
80073d6: 2b02 cmp r3, #2
|
|
80073d8: d123 bne.n 8007422 <HAL_GPIO_Init+0x132>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
80073da: 697b ldr r3, [r7, #20]
|
|
80073dc: 08da lsrs r2, r3, #3
|
|
80073de: 687b ldr r3, [r7, #4]
|
|
80073e0: 3208 adds r2, #8
|
|
80073e2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80073e6: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFUL << ((position & 0x07UL) * 4UL));
|
|
80073e8: 697b ldr r3, [r7, #20]
|
|
80073ea: f003 0307 and.w r3, r3, #7
|
|
80073ee: 009b lsls r3, r3, #2
|
|
80073f0: 220f movs r2, #15
|
|
80073f2: fa02 f303 lsl.w r3, r2, r3
|
|
80073f6: 43db mvns r3, r3
|
|
80073f8: 693a ldr r2, [r7, #16]
|
|
80073fa: 4013 ands r3, r2
|
|
80073fc: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
80073fe: 683b ldr r3, [r7, #0]
|
|
8007400: 691a ldr r2, [r3, #16]
|
|
8007402: 697b ldr r3, [r7, #20]
|
|
8007404: f003 0307 and.w r3, r3, #7
|
|
8007408: 009b lsls r3, r3, #2
|
|
800740a: fa02 f303 lsl.w r3, r2, r3
|
|
800740e: 693a ldr r2, [r7, #16]
|
|
8007410: 4313 orrs r3, r2
|
|
8007412: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
8007414: 697b ldr r3, [r7, #20]
|
|
8007416: 08da lsrs r2, r3, #3
|
|
8007418: 687b ldr r3, [r7, #4]
|
|
800741a: 3208 adds r2, #8
|
|
800741c: 6939 ldr r1, [r7, #16]
|
|
800741e: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8007422: 687b ldr r3, [r7, #4]
|
|
8007424: 681b ldr r3, [r3, #0]
|
|
8007426: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
8007428: 697b ldr r3, [r7, #20]
|
|
800742a: 005b lsls r3, r3, #1
|
|
800742c: 2203 movs r2, #3
|
|
800742e: fa02 f303 lsl.w r3, r2, r3
|
|
8007432: 43db mvns r3, r3
|
|
8007434: 693a ldr r2, [r7, #16]
|
|
8007436: 4013 ands r3, r2
|
|
8007438: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
800743a: 683b ldr r3, [r7, #0]
|
|
800743c: 685b ldr r3, [r3, #4]
|
|
800743e: f003 0203 and.w r2, r3, #3
|
|
8007442: 697b ldr r3, [r7, #20]
|
|
8007444: 005b lsls r3, r3, #1
|
|
8007446: fa02 f303 lsl.w r3, r2, r3
|
|
800744a: 693a ldr r2, [r7, #16]
|
|
800744c: 4313 orrs r3, r2
|
|
800744e: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
8007450: 687b ldr r3, [r7, #4]
|
|
8007452: 693a ldr r2, [r7, #16]
|
|
8007454: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
8007456: 683b ldr r3, [r7, #0]
|
|
8007458: 685b ldr r3, [r3, #4]
|
|
800745a: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
800745e: 2b00 cmp r3, #0
|
|
8007460: f000 8098 beq.w 8007594 <HAL_GPIO_Init+0x2a4>
|
|
{
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
8007464: 4a54 ldr r2, [pc, #336] @ (80075b8 <HAL_GPIO_Init+0x2c8>)
|
|
8007466: 697b ldr r3, [r7, #20]
|
|
8007468: 089b lsrs r3, r3, #2
|
|
800746a: 3302 adds r3, #2
|
|
800746c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8007470: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
8007472: 697b ldr r3, [r7, #20]
|
|
8007474: f003 0303 and.w r3, r3, #3
|
|
8007478: 009b lsls r3, r3, #2
|
|
800747a: 220f movs r2, #15
|
|
800747c: fa02 f303 lsl.w r3, r2, r3
|
|
8007480: 43db mvns r3, r3
|
|
8007482: 693a ldr r2, [r7, #16]
|
|
8007484: 4013 ands r3, r2
|
|
8007486: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
8007488: 687b ldr r3, [r7, #4]
|
|
800748a: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
800748e: d019 beq.n 80074c4 <HAL_GPIO_Init+0x1d4>
|
|
8007490: 687b ldr r3, [r7, #4]
|
|
8007492: 4a4a ldr r2, [pc, #296] @ (80075bc <HAL_GPIO_Init+0x2cc>)
|
|
8007494: 4293 cmp r3, r2
|
|
8007496: d013 beq.n 80074c0 <HAL_GPIO_Init+0x1d0>
|
|
8007498: 687b ldr r3, [r7, #4]
|
|
800749a: 4a49 ldr r2, [pc, #292] @ (80075c0 <HAL_GPIO_Init+0x2d0>)
|
|
800749c: 4293 cmp r3, r2
|
|
800749e: d00d beq.n 80074bc <HAL_GPIO_Init+0x1cc>
|
|
80074a0: 687b ldr r3, [r7, #4]
|
|
80074a2: 4a48 ldr r2, [pc, #288] @ (80075c4 <HAL_GPIO_Init+0x2d4>)
|
|
80074a4: 4293 cmp r3, r2
|
|
80074a6: d007 beq.n 80074b8 <HAL_GPIO_Init+0x1c8>
|
|
80074a8: 687b ldr r3, [r7, #4]
|
|
80074aa: 4a47 ldr r2, [pc, #284] @ (80075c8 <HAL_GPIO_Init+0x2d8>)
|
|
80074ac: 4293 cmp r3, r2
|
|
80074ae: d101 bne.n 80074b4 <HAL_GPIO_Init+0x1c4>
|
|
80074b0: 2304 movs r3, #4
|
|
80074b2: e008 b.n 80074c6 <HAL_GPIO_Init+0x1d6>
|
|
80074b4: 2307 movs r3, #7
|
|
80074b6: e006 b.n 80074c6 <HAL_GPIO_Init+0x1d6>
|
|
80074b8: 2303 movs r3, #3
|
|
80074ba: e004 b.n 80074c6 <HAL_GPIO_Init+0x1d6>
|
|
80074bc: 2302 movs r3, #2
|
|
80074be: e002 b.n 80074c6 <HAL_GPIO_Init+0x1d6>
|
|
80074c0: 2301 movs r3, #1
|
|
80074c2: e000 b.n 80074c6 <HAL_GPIO_Init+0x1d6>
|
|
80074c4: 2300 movs r3, #0
|
|
80074c6: 697a ldr r2, [r7, #20]
|
|
80074c8: f002 0203 and.w r2, r2, #3
|
|
80074cc: 0092 lsls r2, r2, #2
|
|
80074ce: 4093 lsls r3, r2
|
|
80074d0: 693a ldr r2, [r7, #16]
|
|
80074d2: 4313 orrs r3, r2
|
|
80074d4: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
80074d6: 4938 ldr r1, [pc, #224] @ (80075b8 <HAL_GPIO_Init+0x2c8>)
|
|
80074d8: 697b ldr r3, [r7, #20]
|
|
80074da: 089b lsrs r3, r3, #2
|
|
80074dc: 3302 adds r3, #2
|
|
80074de: 693a ldr r2, [r7, #16]
|
|
80074e0: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
80074e4: 4b39 ldr r3, [pc, #228] @ (80075cc <HAL_GPIO_Init+0x2dc>)
|
|
80074e6: 681b ldr r3, [r3, #0]
|
|
80074e8: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80074ea: 68fb ldr r3, [r7, #12]
|
|
80074ec: 43db mvns r3, r3
|
|
80074ee: 693a ldr r2, [r7, #16]
|
|
80074f0: 4013 ands r3, r2
|
|
80074f2: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
80074f4: 683b ldr r3, [r7, #0]
|
|
80074f6: 685b ldr r3, [r3, #4]
|
|
80074f8: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80074fc: 2b00 cmp r3, #0
|
|
80074fe: d003 beq.n 8007508 <HAL_GPIO_Init+0x218>
|
|
{
|
|
temp |= iocurrent;
|
|
8007500: 693a ldr r2, [r7, #16]
|
|
8007502: 68fb ldr r3, [r7, #12]
|
|
8007504: 4313 orrs r3, r2
|
|
8007506: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
8007508: 4a30 ldr r2, [pc, #192] @ (80075cc <HAL_GPIO_Init+0x2dc>)
|
|
800750a: 693b ldr r3, [r7, #16]
|
|
800750c: 6013 str r3, [r2, #0]
|
|
|
|
temp = EXTI->FTSR1;
|
|
800750e: 4b2f ldr r3, [pc, #188] @ (80075cc <HAL_GPIO_Init+0x2dc>)
|
|
8007510: 685b ldr r3, [r3, #4]
|
|
8007512: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8007514: 68fb ldr r3, [r7, #12]
|
|
8007516: 43db mvns r3, r3
|
|
8007518: 693a ldr r2, [r7, #16]
|
|
800751a: 4013 ands r3, r2
|
|
800751c: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
800751e: 683b ldr r3, [r7, #0]
|
|
8007520: 685b ldr r3, [r3, #4]
|
|
8007522: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8007526: 2b00 cmp r3, #0
|
|
8007528: d003 beq.n 8007532 <HAL_GPIO_Init+0x242>
|
|
{
|
|
temp |= iocurrent;
|
|
800752a: 693a ldr r2, [r7, #16]
|
|
800752c: 68fb ldr r3, [r7, #12]
|
|
800752e: 4313 orrs r3, r2
|
|
8007530: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
8007532: 4a26 ldr r2, [pc, #152] @ (80075cc <HAL_GPIO_Init+0x2dc>)
|
|
8007534: 693b ldr r3, [r7, #16]
|
|
8007536: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR1;
|
|
8007538: 4b24 ldr r3, [pc, #144] @ (80075cc <HAL_GPIO_Init+0x2dc>)
|
|
800753a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800753e: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8007540: 68fb ldr r3, [r7, #12]
|
|
8007542: 43db mvns r3, r3
|
|
8007544: 693a ldr r2, [r7, #16]
|
|
8007546: 4013 ands r3, r2
|
|
8007548: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
800754a: 683b ldr r3, [r7, #0]
|
|
800754c: 685b ldr r3, [r3, #4]
|
|
800754e: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8007552: 2b00 cmp r3, #0
|
|
8007554: d003 beq.n 800755e <HAL_GPIO_Init+0x26e>
|
|
{
|
|
temp |= iocurrent;
|
|
8007556: 693a ldr r2, [r7, #16]
|
|
8007558: 68fb ldr r3, [r7, #12]
|
|
800755a: 4313 orrs r3, r2
|
|
800755c: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
800755e: 4a1b ldr r2, [pc, #108] @ (80075cc <HAL_GPIO_Init+0x2dc>)
|
|
8007560: 693b ldr r3, [r7, #16]
|
|
8007562: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
|
|
temp = EXTI->EMR1;
|
|
8007566: 4b19 ldr r3, [pc, #100] @ (80075cc <HAL_GPIO_Init+0x2dc>)
|
|
8007568: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800756c: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
800756e: 68fb ldr r3, [r7, #12]
|
|
8007570: 43db mvns r3, r3
|
|
8007572: 693a ldr r2, [r7, #16]
|
|
8007574: 4013 ands r3, r2
|
|
8007576: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
8007578: 683b ldr r3, [r7, #0]
|
|
800757a: 685b ldr r3, [r3, #4]
|
|
800757c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8007580: 2b00 cmp r3, #0
|
|
8007582: d003 beq.n 800758c <HAL_GPIO_Init+0x29c>
|
|
{
|
|
temp |= iocurrent;
|
|
8007584: 693a ldr r2, [r7, #16]
|
|
8007586: 68fb ldr r3, [r7, #12]
|
|
8007588: 4313 orrs r3, r2
|
|
800758a: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
800758c: 4a0f ldr r2, [pc, #60] @ (80075cc <HAL_GPIO_Init+0x2dc>)
|
|
800758e: 693b ldr r3, [r7, #16]
|
|
8007590: f8c2 3084 str.w r3, [r2, #132] @ 0x84
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8007594: 697b ldr r3, [r7, #20]
|
|
8007596: 3301 adds r3, #1
|
|
8007598: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
800759a: 683b ldr r3, [r7, #0]
|
|
800759c: 681a ldr r2, [r3, #0]
|
|
800759e: 697b ldr r3, [r7, #20]
|
|
80075a0: fa22 f303 lsr.w r3, r2, r3
|
|
80075a4: 2b00 cmp r3, #0
|
|
80075a6: f47f aeab bne.w 8007300 <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
80075aa: bf00 nop
|
|
80075ac: bf00 nop
|
|
80075ae: 371c adds r7, #28
|
|
80075b0: 46bd mov sp, r7
|
|
80075b2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80075b6: 4770 bx lr
|
|
80075b8: 40010000 .word 0x40010000
|
|
80075bc: 48000400 .word 0x48000400
|
|
80075c0: 48000800 .word 0x48000800
|
|
80075c4: 48000c00 .word 0x48000c00
|
|
80075c8: 48001000 .word 0x48001000
|
|
80075cc: 58000800 .word 0x58000800
|
|
|
|
080075d0 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
80075d0: b480 push {r7}
|
|
80075d2: b083 sub sp, #12
|
|
80075d4: af00 add r7, sp, #0
|
|
80075d6: 6078 str r0, [r7, #4]
|
|
80075d8: 460b mov r3, r1
|
|
80075da: 807b strh r3, [r7, #2]
|
|
80075dc: 4613 mov r3, r2
|
|
80075de: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
80075e0: 787b ldrb r3, [r7, #1]
|
|
80075e2: 2b00 cmp r3, #0
|
|
80075e4: d003 beq.n 80075ee <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
80075e6: 887a ldrh r2, [r7, #2]
|
|
80075e8: 687b ldr r3, [r7, #4]
|
|
80075ea: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
80075ec: e002 b.n 80075f4 <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
80075ee: 887a ldrh r2, [r7, #2]
|
|
80075f0: 687b ldr r3, [r7, #4]
|
|
80075f2: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
80075f4: bf00 nop
|
|
80075f6: 370c adds r7, #12
|
|
80075f8: 46bd mov sp, r7
|
|
80075fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80075fe: 4770 bx lr
|
|
|
|
08007600 <HAL_GPIO_EXTI_IRQHandler>:
|
|
* @brief Handle EXTI interrupt request.
|
|
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
|
{
|
|
8007600: b580 push {r7, lr}
|
|
8007602: b082 sub sp, #8
|
|
8007604: af00 add r7, sp, #0
|
|
8007606: 4603 mov r3, r0
|
|
8007608: 80fb strh r3, [r7, #6]
|
|
/* EXTI line interrupt detected */
|
|
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
|
800760a: 4b08 ldr r3, [pc, #32] @ (800762c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
|
|
800760c: 68da ldr r2, [r3, #12]
|
|
800760e: 88fb ldrh r3, [r7, #6]
|
|
8007610: 4013 ands r3, r2
|
|
8007612: 2b00 cmp r3, #0
|
|
8007614: d006 beq.n 8007624 <HAL_GPIO_EXTI_IRQHandler+0x24>
|
|
{
|
|
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
|
8007616: 4a05 ldr r2, [pc, #20] @ (800762c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
|
|
8007618: 88fb ldrh r3, [r7, #6]
|
|
800761a: 60d3 str r3, [r2, #12]
|
|
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
|
800761c: 88fb ldrh r3, [r7, #6]
|
|
800761e: 4618 mov r0, r3
|
|
8007620: f7fd ff6e bl 8005500 <HAL_GPIO_EXTI_Callback>
|
|
}
|
|
}
|
|
8007624: bf00 nop
|
|
8007626: 3708 adds r7, #8
|
|
8007628: 46bd mov sp, r7
|
|
800762a: bd80 pop {r7, pc}
|
|
800762c: 58000800 .word 0x58000800
|
|
|
|
08007630 <HAL_HSEM_IRQHandler>:
|
|
/**
|
|
* @brief This function handles HSEM interrupt request
|
|
* @retval None
|
|
*/
|
|
void HAL_HSEM_IRQHandler(void)
|
|
{
|
|
8007630: b580 push {r7, lr}
|
|
8007632: b082 sub sp, #8
|
|
8007634: af00 add r7, sp, #0
|
|
uint32_t statusreg;
|
|
/* Get the list of masked freed semaphores*/
|
|
statusreg = HSEM_COMMON->MISR;
|
|
8007636: 4b0a ldr r3, [pc, #40] @ (8007660 <HAL_HSEM_IRQHandler+0x30>)
|
|
8007638: 68db ldr r3, [r3, #12]
|
|
800763a: 607b str r3, [r7, #4]
|
|
|
|
/*Disable Interrupts*/
|
|
HSEM_COMMON->IER &= ~((uint32_t)statusreg);
|
|
800763c: 4b08 ldr r3, [pc, #32] @ (8007660 <HAL_HSEM_IRQHandler+0x30>)
|
|
800763e: 681a ldr r2, [r3, #0]
|
|
8007640: 687b ldr r3, [r7, #4]
|
|
8007642: 43db mvns r3, r3
|
|
8007644: 4906 ldr r1, [pc, #24] @ (8007660 <HAL_HSEM_IRQHandler+0x30>)
|
|
8007646: 4013 ands r3, r2
|
|
8007648: 600b str r3, [r1, #0]
|
|
|
|
/*Clear Flags*/
|
|
HSEM_COMMON->ICR = ((uint32_t)statusreg);
|
|
800764a: 4a05 ldr r2, [pc, #20] @ (8007660 <HAL_HSEM_IRQHandler+0x30>)
|
|
800764c: 687b ldr r3, [r7, #4]
|
|
800764e: 6053 str r3, [r2, #4]
|
|
|
|
/* Call FreeCallback */
|
|
HAL_HSEM_FreeCallback(statusreg);
|
|
8007650: 6878 ldr r0, [r7, #4]
|
|
8007652: f000 f807 bl 8007664 <HAL_HSEM_FreeCallback>
|
|
}
|
|
8007656: bf00 nop
|
|
8007658: 3708 adds r7, #8
|
|
800765a: 46bd mov sp, r7
|
|
800765c: bd80 pop {r7, pc}
|
|
800765e: bf00 nop
|
|
8007660: 58001500 .word 0x58001500
|
|
|
|
08007664 <HAL_HSEM_FreeCallback>:
|
|
* @brief Semaphore Released Callback.
|
|
* @param SemMask: Mask of Released semaphores
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
|
|
{
|
|
8007664: b480 push {r7}
|
|
8007666: b083 sub sp, #12
|
|
8007668: af00 add r7, sp, #0
|
|
800766a: 6078 str r0, [r7, #4]
|
|
UNUSED(SemMask);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_HSEM_FreeCallback can be implemented in the user file
|
|
*/
|
|
}
|
|
800766c: bf00 nop
|
|
800766e: 370c adds r7, #12
|
|
8007670: 46bd mov sp, r7
|
|
8007672: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007676: 4770 bx lr
|
|
|
|
08007678 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007678: b580 push {r7, lr}
|
|
800767a: b082 sub sp, #8
|
|
800767c: af00 add r7, sp, #0
|
|
800767e: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8007680: 687b ldr r3, [r7, #4]
|
|
8007682: 2b00 cmp r3, #0
|
|
8007684: d101 bne.n 800768a <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8007686: 2301 movs r3, #1
|
|
8007688: e08d b.n 80077a6 <HAL_I2C_Init+0x12e>
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
800768a: 687b ldr r3, [r7, #4]
|
|
800768c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8007690: b2db uxtb r3, r3
|
|
8007692: 2b00 cmp r3, #0
|
|
8007694: d106 bne.n 80076a4 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8007696: 687b ldr r3, [r7, #4]
|
|
8007698: 2200 movs r2, #0
|
|
800769a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
HAL_I2C_MspInit(hi2c);
|
|
800769e: 6878 ldr r0, [r7, #4]
|
|
80076a0: f7fe fcc2 bl 8006028 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80076a4: 687b ldr r3, [r7, #4]
|
|
80076a6: 2224 movs r2, #36 @ 0x24
|
|
80076a8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80076ac: 687b ldr r3, [r7, #4]
|
|
80076ae: 681b ldr r3, [r3, #0]
|
|
80076b0: 681a ldr r2, [r3, #0]
|
|
80076b2: 687b ldr r3, [r7, #4]
|
|
80076b4: 681b ldr r3, [r3, #0]
|
|
80076b6: f022 0201 bic.w r2, r2, #1
|
|
80076ba: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
|
|
80076bc: 687b ldr r3, [r7, #4]
|
|
80076be: 685a ldr r2, [r3, #4]
|
|
80076c0: 687b ldr r3, [r7, #4]
|
|
80076c2: 681b ldr r3, [r3, #0]
|
|
80076c4: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
|
|
80076c8: 611a str r2, [r3, #16]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Disable Own Address1 before set the Own Address1 configuration */
|
|
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
|
|
80076ca: 687b ldr r3, [r7, #4]
|
|
80076cc: 681b ldr r3, [r3, #0]
|
|
80076ce: 689a ldr r2, [r3, #8]
|
|
80076d0: 687b ldr r3, [r7, #4]
|
|
80076d2: 681b ldr r3, [r3, #0]
|
|
80076d4: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
80076d8: 609a str r2, [r3, #8]
|
|
|
|
/* Configure I2Cx: Own Address1 and ack own address1 mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
80076da: 687b ldr r3, [r7, #4]
|
|
80076dc: 68db ldr r3, [r3, #12]
|
|
80076de: 2b01 cmp r3, #1
|
|
80076e0: d107 bne.n 80076f2 <HAL_I2C_Init+0x7a>
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
|
|
80076e2: 687b ldr r3, [r7, #4]
|
|
80076e4: 689a ldr r2, [r3, #8]
|
|
80076e6: 687b ldr r3, [r7, #4]
|
|
80076e8: 681b ldr r3, [r3, #0]
|
|
80076ea: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
80076ee: 609a str r2, [r3, #8]
|
|
80076f0: e006 b.n 8007700 <HAL_I2C_Init+0x88>
|
|
}
|
|
else /* I2C_ADDRESSINGMODE_10BIT */
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
|
|
80076f2: 687b ldr r3, [r7, #4]
|
|
80076f4: 689a ldr r2, [r3, #8]
|
|
80076f6: 687b ldr r3, [r7, #4]
|
|
80076f8: 681b ldr r3, [r3, #0]
|
|
80076fa: f442 4204 orr.w r2, r2, #33792 @ 0x8400
|
|
80076fe: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Addressing Master mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
8007700: 687b ldr r3, [r7, #4]
|
|
8007702: 68db ldr r3, [r3, #12]
|
|
8007704: 2b02 cmp r3, #2
|
|
8007706: d108 bne.n 800771a <HAL_I2C_Init+0xa2>
|
|
{
|
|
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
8007708: 687b ldr r3, [r7, #4]
|
|
800770a: 681b ldr r3, [r3, #0]
|
|
800770c: 685a ldr r2, [r3, #4]
|
|
800770e: 687b ldr r3, [r7, #4]
|
|
8007710: 681b ldr r3, [r3, #0]
|
|
8007712: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8007716: 605a str r2, [r3, #4]
|
|
8007718: e007 b.n 800772a <HAL_I2C_Init+0xb2>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the I2C ADD10 bit */
|
|
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
800771a: 687b ldr r3, [r7, #4]
|
|
800771c: 681b ldr r3, [r3, #0]
|
|
800771e: 685a ldr r2, [r3, #4]
|
|
8007720: 687b ldr r3, [r7, #4]
|
|
8007722: 681b ldr r3, [r3, #0]
|
|
8007724: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8007728: 605a str r2, [r3, #4]
|
|
}
|
|
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
|
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
|
800772a: 687b ldr r3, [r7, #4]
|
|
800772c: 681b ldr r3, [r3, #0]
|
|
800772e: 685b ldr r3, [r3, #4]
|
|
8007730: 687a ldr r2, [r7, #4]
|
|
8007732: 6812 ldr r2, [r2, #0]
|
|
8007734: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
8007738: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800773c: 6053 str r3, [r2, #4]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Disable Own Address2 before set the Own Address2 configuration */
|
|
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
|
|
800773e: 687b ldr r3, [r7, #4]
|
|
8007740: 681b ldr r3, [r3, #0]
|
|
8007742: 68da ldr r2, [r3, #12]
|
|
8007744: 687b ldr r3, [r7, #4]
|
|
8007746: 681b ldr r3, [r3, #0]
|
|
8007748: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
800774c: 60da str r2, [r3, #12]
|
|
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
800774e: 687b ldr r3, [r7, #4]
|
|
8007750: 691a ldr r2, [r3, #16]
|
|
8007752: 687b ldr r3, [r7, #4]
|
|
8007754: 695b ldr r3, [r3, #20]
|
|
8007756: ea42 0103 orr.w r1, r2, r3
|
|
(hi2c->Init.OwnAddress2Masks << 8));
|
|
800775a: 687b ldr r3, [r7, #4]
|
|
800775c: 699b ldr r3, [r3, #24]
|
|
800775e: 021a lsls r2, r3, #8
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8007760: 687b ldr r3, [r7, #4]
|
|
8007762: 681b ldr r3, [r3, #0]
|
|
8007764: 430a orrs r2, r1
|
|
8007766: 60da str r2, [r3, #12]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
|
|
8007768: 687b ldr r3, [r7, #4]
|
|
800776a: 69d9 ldr r1, [r3, #28]
|
|
800776c: 687b ldr r3, [r7, #4]
|
|
800776e: 6a1a ldr r2, [r3, #32]
|
|
8007770: 687b ldr r3, [r7, #4]
|
|
8007772: 681b ldr r3, [r3, #0]
|
|
8007774: 430a orrs r2, r1
|
|
8007776: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8007778: 687b ldr r3, [r7, #4]
|
|
800777a: 681b ldr r3, [r3, #0]
|
|
800777c: 681a ldr r2, [r3, #0]
|
|
800777e: 687b ldr r3, [r7, #4]
|
|
8007780: 681b ldr r3, [r3, #0]
|
|
8007782: f042 0201 orr.w r2, r2, #1
|
|
8007786: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8007788: 687b ldr r3, [r7, #4]
|
|
800778a: 2200 movs r2, #0
|
|
800778c: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800778e: 687b ldr r3, [r7, #4]
|
|
8007790: 2220 movs r2, #32
|
|
8007792: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8007796: 687b ldr r3, [r7, #4]
|
|
8007798: 2200 movs r2, #0
|
|
800779a: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800779c: 687b ldr r3, [r7, #4]
|
|
800779e: 2200 movs r2, #0
|
|
80077a0: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_OK;
|
|
80077a4: 2300 movs r3, #0
|
|
}
|
|
80077a6: 4618 mov r0, r3
|
|
80077a8: 3708 adds r7, #8
|
|
80077aa: 46bd mov sp, r7
|
|
80077ac: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080077b0 <HAL_I2C_Mem_Write_DMA>:
|
|
* @param Size Amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
|
{
|
|
80077b0: b580 push {r7, lr}
|
|
80077b2: b088 sub sp, #32
|
|
80077b4: af02 add r7, sp, #8
|
|
80077b6: 60f8 str r0, [r7, #12]
|
|
80077b8: 4608 mov r0, r1
|
|
80077ba: 4611 mov r1, r2
|
|
80077bc: 461a mov r2, r3
|
|
80077be: 4603 mov r3, r0
|
|
80077c0: 817b strh r3, [r7, #10]
|
|
80077c2: 460b mov r3, r1
|
|
80077c4: 813b strh r3, [r7, #8]
|
|
80077c6: 4613 mov r3, r2
|
|
80077c8: 80fb strh r3, [r7, #6]
|
|
HAL_StatusTypeDef dmaxferstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
80077ca: 68fb ldr r3, [r7, #12]
|
|
80077cc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80077d0: b2db uxtb r3, r3
|
|
80077d2: 2b20 cmp r3, #32
|
|
80077d4: f040 80c3 bne.w 800795e <HAL_I2C_Mem_Write_DMA+0x1ae>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80077d8: 6a3b ldr r3, [r7, #32]
|
|
80077da: 2b00 cmp r3, #0
|
|
80077dc: d002 beq.n 80077e4 <HAL_I2C_Mem_Write_DMA+0x34>
|
|
80077de: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
80077e0: 2b00 cmp r3, #0
|
|
80077e2: d105 bne.n 80077f0 <HAL_I2C_Mem_Write_DMA+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
80077e4: 68fb ldr r3, [r7, #12]
|
|
80077e6: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80077ea: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
80077ec: 2301 movs r3, #1
|
|
80077ee: e0b7 b.n 8007960 <HAL_I2C_Mem_Write_DMA+0x1b0>
|
|
}
|
|
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
|
|
80077f0: 68fb ldr r3, [r7, #12]
|
|
80077f2: 681b ldr r3, [r3, #0]
|
|
80077f4: 699b ldr r3, [r3, #24]
|
|
80077f6: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80077fa: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80077fe: d101 bne.n 8007804 <HAL_I2C_Mem_Write_DMA+0x54>
|
|
{
|
|
return HAL_BUSY;
|
|
8007800: 2302 movs r3, #2
|
|
8007802: e0ad b.n 8007960 <HAL_I2C_Mem_Write_DMA+0x1b0>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8007804: 68fb ldr r3, [r7, #12]
|
|
8007806: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
800780a: 2b01 cmp r3, #1
|
|
800780c: d101 bne.n 8007812 <HAL_I2C_Mem_Write_DMA+0x62>
|
|
800780e: 2302 movs r3, #2
|
|
8007810: e0a6 b.n 8007960 <HAL_I2C_Mem_Write_DMA+0x1b0>
|
|
8007812: 68fb ldr r3, [r7, #12]
|
|
8007814: 2201 movs r2, #1
|
|
8007816: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
800781a: 68fb ldr r3, [r7, #12]
|
|
800781c: 2221 movs r2, #33 @ 0x21
|
|
800781e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8007822: 68fb ldr r3, [r7, #12]
|
|
8007824: 2240 movs r2, #64 @ 0x40
|
|
8007826: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
800782a: 68fb ldr r3, [r7, #12]
|
|
800782c: 2200 movs r2, #0
|
|
800782e: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8007830: 68fb ldr r3, [r7, #12]
|
|
8007832: 6a3a ldr r2, [r7, #32]
|
|
8007834: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8007836: 68fb ldr r3, [r7, #12]
|
|
8007838: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
800783a: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
|
800783c: 68fb ldr r3, [r7, #12]
|
|
800783e: 4a4a ldr r2, [pc, #296] @ (8007968 <HAL_I2C_Mem_Write_DMA+0x1b8>)
|
|
8007840: 62da str r2, [r3, #44] @ 0x2c
|
|
hi2c->XferISR = I2C_Mem_ISR_DMA;
|
|
8007842: 68fb ldr r3, [r7, #12]
|
|
8007844: 4a49 ldr r2, [pc, #292] @ (800796c <HAL_I2C_Mem_Write_DMA+0x1bc>)
|
|
8007846: 635a str r2, [r3, #52] @ 0x34
|
|
hi2c->Devaddress = DevAddress;
|
|
8007848: 897a ldrh r2, [r7, #10]
|
|
800784a: 68fb ldr r3, [r7, #12]
|
|
800784c: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
800784e: 68fb ldr r3, [r7, #12]
|
|
8007850: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007852: b29b uxth r3, r3
|
|
8007854: 2bff cmp r3, #255 @ 0xff
|
|
8007856: d903 bls.n 8007860 <HAL_I2C_Mem_Write_DMA+0xb0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8007858: 68fb ldr r3, [r7, #12]
|
|
800785a: 22ff movs r2, #255 @ 0xff
|
|
800785c: 851a strh r2, [r3, #40] @ 0x28
|
|
800785e: e004 b.n 800786a <HAL_I2C_Mem_Write_DMA+0xba>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8007860: 68fb ldr r3, [r7, #12]
|
|
8007862: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007864: b29a uxth r2, r3
|
|
8007866: 68fb ldr r3, [r7, #12]
|
|
8007868: 851a strh r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
800786a: 88fb ldrh r3, [r7, #6]
|
|
800786c: 2b01 cmp r3, #1
|
|
800786e: d109 bne.n 8007884 <HAL_I2C_Mem_Write_DMA+0xd4>
|
|
{
|
|
/* Prefetch Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8007870: 893b ldrh r3, [r7, #8]
|
|
8007872: b2da uxtb r2, r3
|
|
8007874: 68fb ldr r3, [r7, #12]
|
|
8007876: 681b ldr r3, [r3, #0]
|
|
8007878: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Reset Memaddress content */
|
|
hi2c->Memaddress = 0xFFFFFFFFU;
|
|
800787a: 68fb ldr r3, [r7, #12]
|
|
800787c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8007880: 651a str r2, [r3, #80] @ 0x50
|
|
8007882: e00b b.n 800789c <HAL_I2C_Mem_Write_DMA+0xec>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
8007884: 893b ldrh r3, [r7, #8]
|
|
8007886: 0a1b lsrs r3, r3, #8
|
|
8007888: b29b uxth r3, r3
|
|
800788a: b2da uxtb r2, r3
|
|
800788c: 68fb ldr r3, [r7, #12]
|
|
800788e: 681b ldr r3, [r3, #0]
|
|
8007890: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Prepare Memaddress buffer for LSB part */
|
|
hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
|
|
8007892: 893b ldrh r3, [r7, #8]
|
|
8007894: b2db uxtb r3, r3
|
|
8007896: 461a mov r2, r3
|
|
8007898: 68fb ldr r3, [r7, #12]
|
|
800789a: 651a str r2, [r3, #80] @ 0x50
|
|
}
|
|
|
|
if (hi2c->hdmatx != NULL)
|
|
800789c: 68fb ldr r3, [r7, #12]
|
|
800789e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80078a0: 2b00 cmp r3, #0
|
|
80078a2: d020 beq.n 80078e6 <HAL_I2C_Mem_Write_DMA+0x136>
|
|
{
|
|
/* Set the I2C DMA transfer complete callback */
|
|
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
|
|
80078a4: 68fb ldr r3, [r7, #12]
|
|
80078a6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80078a8: 4a31 ldr r2, [pc, #196] @ (8007970 <HAL_I2C_Mem_Write_DMA+0x1c0>)
|
|
80078aa: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the DMA error callback */
|
|
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
|
|
80078ac: 68fb ldr r3, [r7, #12]
|
|
80078ae: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80078b0: 4a30 ldr r2, [pc, #192] @ (8007974 <HAL_I2C_Mem_Write_DMA+0x1c4>)
|
|
80078b2: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Set the unused DMA callbacks to NULL */
|
|
hi2c->hdmatx->XferHalfCpltCallback = NULL;
|
|
80078b4: 68fb ldr r3, [r7, #12]
|
|
80078b6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80078b8: 2200 movs r2, #0
|
|
80078ba: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->hdmatx->XferAbortCallback = NULL;
|
|
80078bc: 68fb ldr r3, [r7, #12]
|
|
80078be: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80078c0: 2200 movs r2, #0
|
|
80078c2: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Enable the DMA channel */
|
|
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
|
|
80078c4: 68fb ldr r3, [r7, #12]
|
|
80078c6: 6b98 ldr r0, [r3, #56] @ 0x38
|
|
80078c8: 6a39 ldr r1, [r7, #32]
|
|
80078ca: 68fb ldr r3, [r7, #12]
|
|
80078cc: 681b ldr r3, [r3, #0]
|
|
80078ce: 3328 adds r3, #40 @ 0x28
|
|
80078d0: 461a mov r2, r3
|
|
hi2c->XferSize);
|
|
80078d2: 68fb ldr r3, [r7, #12]
|
|
80078d4: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
|
|
80078d6: f7ff fa73 bl 8006dc0 <HAL_DMA_Start_IT>
|
|
80078da: 4603 mov r3, r0
|
|
80078dc: 75fb strb r3, [r7, #23]
|
|
__HAL_UNLOCK(hi2c);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
if (dmaxferstatus == HAL_OK)
|
|
80078de: 7dfb ldrb r3, [r7, #23]
|
|
80078e0: 2b00 cmp r3, #0
|
|
80078e2: d128 bne.n 8007936 <HAL_I2C_Mem_Write_DMA+0x186>
|
|
80078e4: e013 b.n 800790e <HAL_I2C_Mem_Write_DMA+0x15e>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80078e6: 68fb ldr r3, [r7, #12]
|
|
80078e8: 2220 movs r2, #32
|
|
80078ea: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80078ee: 68fb ldr r3, [r7, #12]
|
|
80078f0: 2200 movs r2, #0
|
|
80078f2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
|
80078f6: 68fb ldr r3, [r7, #12]
|
|
80078f8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80078fa: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
80078fe: 68fb ldr r3, [r7, #12]
|
|
8007900: 645a str r2, [r3, #68] @ 0x44
|
|
__HAL_UNLOCK(hi2c);
|
|
8007902: 68fb ldr r3, [r7, #12]
|
|
8007904: 2200 movs r2, #0
|
|
8007906: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
800790a: 2301 movs r3, #1
|
|
800790c: e028 b.n 8007960 <HAL_I2C_Mem_Write_DMA+0x1b0>
|
|
{
|
|
/* Send Slave Address and Memory Address */
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
|
800790e: 88fb ldrh r3, [r7, #6]
|
|
8007910: b2da uxtb r2, r3
|
|
8007912: 8979 ldrh r1, [r7, #10]
|
|
8007914: 4b18 ldr r3, [pc, #96] @ (8007978 <HAL_I2C_Mem_Write_DMA+0x1c8>)
|
|
8007916: 9300 str r3, [sp, #0]
|
|
8007918: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
800791c: 68f8 ldr r0, [r7, #12]
|
|
800791e: f001 fb9b bl 8009058 <I2C_TransferConfig>
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007922: 68fb ldr r3, [r7, #12]
|
|
8007924: 2200 movs r2, #0
|
|
8007926: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
process unlock */
|
|
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
|
/* possible to enable all of these */
|
|
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
|
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
|
800792a: 2101 movs r1, #1
|
|
800792c: 68f8 ldr r0, [r7, #12]
|
|
800792e: f001 fbc5 bl 80090bc <I2C_Enable_IRQ>
|
|
__HAL_UNLOCK(hi2c);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007932: 2300 movs r3, #0
|
|
8007934: e014 b.n 8007960 <HAL_I2C_Mem_Write_DMA+0x1b0>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007936: 68fb ldr r3, [r7, #12]
|
|
8007938: 2220 movs r2, #32
|
|
800793a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800793e: 68fb ldr r3, [r7, #12]
|
|
8007940: 2200 movs r2, #0
|
|
8007942: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
|
|
8007946: 68fb ldr r3, [r7, #12]
|
|
8007948: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800794a: f043 0210 orr.w r2, r3, #16
|
|
800794e: 68fb ldr r3, [r7, #12]
|
|
8007950: 645a str r2, [r3, #68] @ 0x44
|
|
__HAL_UNLOCK(hi2c);
|
|
8007952: 68fb ldr r3, [r7, #12]
|
|
8007954: 2200 movs r2, #0
|
|
8007956: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
800795a: 2301 movs r3, #1
|
|
800795c: e000 b.n 8007960 <HAL_I2C_Mem_Write_DMA+0x1b0>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800795e: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8007960: 4618 mov r0, r3
|
|
8007962: 3718 adds r7, #24
|
|
8007964: 46bd mov sp, r7
|
|
8007966: bd80 pop {r7, pc}
|
|
8007968: ffff0000 .word 0xffff0000
|
|
800796c: 080080d9 .word 0x080080d9
|
|
8007970: 08008ec3 .word 0x08008ec3
|
|
8007974: 08008fef .word 0x08008fef
|
|
8007978: 80002000 .word 0x80002000
|
|
|
|
0800797c <HAL_I2C_Mem_Read_DMA>:
|
|
* @param Size Amount of data to be read
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
|
|
{
|
|
800797c: b580 push {r7, lr}
|
|
800797e: b088 sub sp, #32
|
|
8007980: af02 add r7, sp, #8
|
|
8007982: 60f8 str r0, [r7, #12]
|
|
8007984: 4608 mov r0, r1
|
|
8007986: 4611 mov r1, r2
|
|
8007988: 461a mov r2, r3
|
|
800798a: 4603 mov r3, r0
|
|
800798c: 817b strh r3, [r7, #10]
|
|
800798e: 460b mov r3, r1
|
|
8007990: 813b strh r3, [r7, #8]
|
|
8007992: 4613 mov r3, r2
|
|
8007994: 80fb strh r3, [r7, #6]
|
|
HAL_StatusTypeDef dmaxferstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8007996: 68fb ldr r3, [r7, #12]
|
|
8007998: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800799c: b2db uxtb r3, r3
|
|
800799e: 2b20 cmp r3, #32
|
|
80079a0: f040 80c2 bne.w 8007b28 <HAL_I2C_Mem_Read_DMA+0x1ac>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80079a4: 6a3b ldr r3, [r7, #32]
|
|
80079a6: 2b00 cmp r3, #0
|
|
80079a8: d002 beq.n 80079b0 <HAL_I2C_Mem_Read_DMA+0x34>
|
|
80079aa: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
80079ac: 2b00 cmp r3, #0
|
|
80079ae: d105 bne.n 80079bc <HAL_I2C_Mem_Read_DMA+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
80079b0: 68fb ldr r3, [r7, #12]
|
|
80079b2: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80079b6: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
80079b8: 2301 movs r3, #1
|
|
80079ba: e0b6 b.n 8007b2a <HAL_I2C_Mem_Read_DMA+0x1ae>
|
|
}
|
|
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
|
|
80079bc: 68fb ldr r3, [r7, #12]
|
|
80079be: 681b ldr r3, [r3, #0]
|
|
80079c0: 699b ldr r3, [r3, #24]
|
|
80079c2: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80079c6: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80079ca: d101 bne.n 80079d0 <HAL_I2C_Mem_Read_DMA+0x54>
|
|
{
|
|
return HAL_BUSY;
|
|
80079cc: 2302 movs r3, #2
|
|
80079ce: e0ac b.n 8007b2a <HAL_I2C_Mem_Read_DMA+0x1ae>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80079d0: 68fb ldr r3, [r7, #12]
|
|
80079d2: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
80079d6: 2b01 cmp r3, #1
|
|
80079d8: d101 bne.n 80079de <HAL_I2C_Mem_Read_DMA+0x62>
|
|
80079da: 2302 movs r3, #2
|
|
80079dc: e0a5 b.n 8007b2a <HAL_I2C_Mem_Read_DMA+0x1ae>
|
|
80079de: 68fb ldr r3, [r7, #12]
|
|
80079e0: 2201 movs r2, #1
|
|
80079e2: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
80079e6: 68fb ldr r3, [r7, #12]
|
|
80079e8: 2222 movs r2, #34 @ 0x22
|
|
80079ea: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
80079ee: 68fb ldr r3, [r7, #12]
|
|
80079f0: 2240 movs r2, #64 @ 0x40
|
|
80079f2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
80079f6: 68fb ldr r3, [r7, #12]
|
|
80079f8: 2200 movs r2, #0
|
|
80079fa: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
80079fc: 68fb ldr r3, [r7, #12]
|
|
80079fe: 6a3a ldr r2, [r7, #32]
|
|
8007a00: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8007a02: 68fb ldr r3, [r7, #12]
|
|
8007a04: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
8007a06: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
|
8007a08: 68fb ldr r3, [r7, #12]
|
|
8007a0a: 4a4a ldr r2, [pc, #296] @ (8007b34 <HAL_I2C_Mem_Read_DMA+0x1b8>)
|
|
8007a0c: 62da str r2, [r3, #44] @ 0x2c
|
|
hi2c->XferISR = I2C_Mem_ISR_DMA;
|
|
8007a0e: 68fb ldr r3, [r7, #12]
|
|
8007a10: 4a49 ldr r2, [pc, #292] @ (8007b38 <HAL_I2C_Mem_Read_DMA+0x1bc>)
|
|
8007a12: 635a str r2, [r3, #52] @ 0x34
|
|
hi2c->Devaddress = DevAddress;
|
|
8007a14: 897a ldrh r2, [r7, #10]
|
|
8007a16: 68fb ldr r3, [r7, #12]
|
|
8007a18: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8007a1a: 68fb ldr r3, [r7, #12]
|
|
8007a1c: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007a1e: b29b uxth r3, r3
|
|
8007a20: 2bff cmp r3, #255 @ 0xff
|
|
8007a22: d903 bls.n 8007a2c <HAL_I2C_Mem_Read_DMA+0xb0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8007a24: 68fb ldr r3, [r7, #12]
|
|
8007a26: 22ff movs r2, #255 @ 0xff
|
|
8007a28: 851a strh r2, [r3, #40] @ 0x28
|
|
8007a2a: e004 b.n 8007a36 <HAL_I2C_Mem_Read_DMA+0xba>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8007a2c: 68fb ldr r3, [r7, #12]
|
|
8007a2e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007a30: b29a uxth r2, r3
|
|
8007a32: 68fb ldr r3, [r7, #12]
|
|
8007a34: 851a strh r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
8007a36: 88fb ldrh r3, [r7, #6]
|
|
8007a38: 2b01 cmp r3, #1
|
|
8007a3a: d109 bne.n 8007a50 <HAL_I2C_Mem_Read_DMA+0xd4>
|
|
{
|
|
/* Prefetch Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8007a3c: 893b ldrh r3, [r7, #8]
|
|
8007a3e: b2da uxtb r2, r3
|
|
8007a40: 68fb ldr r3, [r7, #12]
|
|
8007a42: 681b ldr r3, [r3, #0]
|
|
8007a44: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Reset Memaddress content */
|
|
hi2c->Memaddress = 0xFFFFFFFFU;
|
|
8007a46: 68fb ldr r3, [r7, #12]
|
|
8007a48: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8007a4c: 651a str r2, [r3, #80] @ 0x50
|
|
8007a4e: e00b b.n 8007a68 <HAL_I2C_Mem_Read_DMA+0xec>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
8007a50: 893b ldrh r3, [r7, #8]
|
|
8007a52: 0a1b lsrs r3, r3, #8
|
|
8007a54: b29b uxth r3, r3
|
|
8007a56: b2da uxtb r2, r3
|
|
8007a58: 68fb ldr r3, [r7, #12]
|
|
8007a5a: 681b ldr r3, [r3, #0]
|
|
8007a5c: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Prepare Memaddress buffer for LSB part */
|
|
hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
|
|
8007a5e: 893b ldrh r3, [r7, #8]
|
|
8007a60: b2db uxtb r3, r3
|
|
8007a62: 461a mov r2, r3
|
|
8007a64: 68fb ldr r3, [r7, #12]
|
|
8007a66: 651a str r2, [r3, #80] @ 0x50
|
|
}
|
|
|
|
if (hi2c->hdmarx != NULL)
|
|
8007a68: 68fb ldr r3, [r7, #12]
|
|
8007a6a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8007a6c: 2b00 cmp r3, #0
|
|
8007a6e: d020 beq.n 8007ab2 <HAL_I2C_Mem_Read_DMA+0x136>
|
|
{
|
|
/* Set the I2C DMA transfer complete callback */
|
|
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
|
|
8007a70: 68fb ldr r3, [r7, #12]
|
|
8007a72: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8007a74: 4a31 ldr r2, [pc, #196] @ (8007b3c <HAL_I2C_Mem_Read_DMA+0x1c0>)
|
|
8007a76: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the DMA error callback */
|
|
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
|
|
8007a78: 68fb ldr r3, [r7, #12]
|
|
8007a7a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8007a7c: 4a30 ldr r2, [pc, #192] @ (8007b40 <HAL_I2C_Mem_Read_DMA+0x1c4>)
|
|
8007a7e: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Set the unused DMA callbacks to NULL */
|
|
hi2c->hdmarx->XferHalfCpltCallback = NULL;
|
|
8007a80: 68fb ldr r3, [r7, #12]
|
|
8007a82: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8007a84: 2200 movs r2, #0
|
|
8007a86: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->hdmarx->XferAbortCallback = NULL;
|
|
8007a88: 68fb ldr r3, [r7, #12]
|
|
8007a8a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8007a8c: 2200 movs r2, #0
|
|
8007a8e: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Enable the DMA channel */
|
|
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
|
|
8007a90: 68fb ldr r3, [r7, #12]
|
|
8007a92: 6bd8 ldr r0, [r3, #60] @ 0x3c
|
|
8007a94: 68fb ldr r3, [r7, #12]
|
|
8007a96: 681b ldr r3, [r3, #0]
|
|
8007a98: 3324 adds r3, #36 @ 0x24
|
|
8007a9a: 4619 mov r1, r3
|
|
8007a9c: 6a3a ldr r2, [r7, #32]
|
|
hi2c->XferSize);
|
|
8007a9e: 68fb ldr r3, [r7, #12]
|
|
8007aa0: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
|
|
8007aa2: f7ff f98d bl 8006dc0 <HAL_DMA_Start_IT>
|
|
8007aa6: 4603 mov r3, r0
|
|
8007aa8: 75fb strb r3, [r7, #23]
|
|
__HAL_UNLOCK(hi2c);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
if (dmaxferstatus == HAL_OK)
|
|
8007aaa: 7dfb ldrb r3, [r7, #23]
|
|
8007aac: 2b00 cmp r3, #0
|
|
8007aae: d127 bne.n 8007b00 <HAL_I2C_Mem_Read_DMA+0x184>
|
|
8007ab0: e013 b.n 8007ada <HAL_I2C_Mem_Read_DMA+0x15e>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007ab2: 68fb ldr r3, [r7, #12]
|
|
8007ab4: 2220 movs r2, #32
|
|
8007ab6: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8007aba: 68fb ldr r3, [r7, #12]
|
|
8007abc: 2200 movs r2, #0
|
|
8007abe: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
|
|
8007ac2: 68fb ldr r3, [r7, #12]
|
|
8007ac4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007ac6: f043 0280 orr.w r2, r3, #128 @ 0x80
|
|
8007aca: 68fb ldr r3, [r7, #12]
|
|
8007acc: 645a str r2, [r3, #68] @ 0x44
|
|
__HAL_UNLOCK(hi2c);
|
|
8007ace: 68fb ldr r3, [r7, #12]
|
|
8007ad0: 2200 movs r2, #0
|
|
8007ad2: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8007ad6: 2301 movs r3, #1
|
|
8007ad8: e027 b.n 8007b2a <HAL_I2C_Mem_Read_DMA+0x1ae>
|
|
{
|
|
/* Send Slave Address and Memory Address */
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
|
8007ada: 88fb ldrh r3, [r7, #6]
|
|
8007adc: b2da uxtb r2, r3
|
|
8007ade: 8979 ldrh r1, [r7, #10]
|
|
8007ae0: 4b18 ldr r3, [pc, #96] @ (8007b44 <HAL_I2C_Mem_Read_DMA+0x1c8>)
|
|
8007ae2: 9300 str r3, [sp, #0]
|
|
8007ae4: 2300 movs r3, #0
|
|
8007ae6: 68f8 ldr r0, [r7, #12]
|
|
8007ae8: f001 fab6 bl 8009058 <I2C_TransferConfig>
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007aec: 68fb ldr r3, [r7, #12]
|
|
8007aee: 2200 movs r2, #0
|
|
8007af0: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
process unlock */
|
|
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
|
/* possible to enable all of these */
|
|
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
|
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
|
8007af4: 2101 movs r1, #1
|
|
8007af6: 68f8 ldr r0, [r7, #12]
|
|
8007af8: f001 fae0 bl 80090bc <I2C_Enable_IRQ>
|
|
__HAL_UNLOCK(hi2c);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007afc: 2300 movs r3, #0
|
|
8007afe: e014 b.n 8007b2a <HAL_I2C_Mem_Read_DMA+0x1ae>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007b00: 68fb ldr r3, [r7, #12]
|
|
8007b02: 2220 movs r2, #32
|
|
8007b04: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8007b08: 68fb ldr r3, [r7, #12]
|
|
8007b0a: 2200 movs r2, #0
|
|
8007b0c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
|
|
8007b10: 68fb ldr r3, [r7, #12]
|
|
8007b12: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007b14: f043 0210 orr.w r2, r3, #16
|
|
8007b18: 68fb ldr r3, [r7, #12]
|
|
8007b1a: 645a str r2, [r3, #68] @ 0x44
|
|
__HAL_UNLOCK(hi2c);
|
|
8007b1c: 68fb ldr r3, [r7, #12]
|
|
8007b1e: 2200 movs r2, #0
|
|
8007b20: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8007b24: 2301 movs r3, #1
|
|
8007b26: e000 b.n 8007b2a <HAL_I2C_Mem_Read_DMA+0x1ae>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8007b28: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8007b2a: 4618 mov r0, r3
|
|
8007b2c: 3718 adds r7, #24
|
|
8007b2e: 46bd mov sp, r7
|
|
8007b30: bd80 pop {r7, pc}
|
|
8007b32: bf00 nop
|
|
8007b34: ffff0000 .word 0xffff0000
|
|
8007b38: 080080d9 .word 0x080080d9
|
|
8007b3c: 08008f59 .word 0x08008f59
|
|
8007b40: 08008fef .word 0x08008fef
|
|
8007b44: 80002000 .word 0x80002000
|
|
|
|
08007b48 <HAL_I2C_EV_IRQHandler>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
|
|
{
|
|
8007b48: b580 push {r7, lr}
|
|
8007b4a: b084 sub sp, #16
|
|
8007b4c: af00 add r7, sp, #0
|
|
8007b4e: 6078 str r0, [r7, #4]
|
|
/* Get current IT Flags and IT sources value */
|
|
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
|
|
8007b50: 687b ldr r3, [r7, #4]
|
|
8007b52: 681b ldr r3, [r3, #0]
|
|
8007b54: 699b ldr r3, [r3, #24]
|
|
8007b56: 60fb str r3, [r7, #12]
|
|
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
|
|
8007b58: 687b ldr r3, [r7, #4]
|
|
8007b5a: 681b ldr r3, [r3, #0]
|
|
8007b5c: 681b ldr r3, [r3, #0]
|
|
8007b5e: 60bb str r3, [r7, #8]
|
|
|
|
/* I2C events treatment -------------------------------------*/
|
|
if (hi2c->XferISR != NULL)
|
|
8007b60: 687b ldr r3, [r7, #4]
|
|
8007b62: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8007b64: 2b00 cmp r3, #0
|
|
8007b66: d005 beq.n 8007b74 <HAL_I2C_EV_IRQHandler+0x2c>
|
|
{
|
|
hi2c->XferISR(hi2c, itflags, itsources);
|
|
8007b68: 687b ldr r3, [r7, #4]
|
|
8007b6a: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8007b6c: 68ba ldr r2, [r7, #8]
|
|
8007b6e: 68f9 ldr r1, [r7, #12]
|
|
8007b70: 6878 ldr r0, [r7, #4]
|
|
8007b72: 4798 blx r3
|
|
}
|
|
}
|
|
8007b74: bf00 nop
|
|
8007b76: 3710 adds r7, #16
|
|
8007b78: 46bd mov sp, r7
|
|
8007b7a: bd80 pop {r7, pc}
|
|
|
|
08007b7c <HAL_I2C_ER_IRQHandler>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007b7c: b580 push {r7, lr}
|
|
8007b7e: b086 sub sp, #24
|
|
8007b80: af00 add r7, sp, #0
|
|
8007b82: 6078 str r0, [r7, #4]
|
|
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
|
|
8007b84: 687b ldr r3, [r7, #4]
|
|
8007b86: 681b ldr r3, [r3, #0]
|
|
8007b88: 699b ldr r3, [r3, #24]
|
|
8007b8a: 617b str r3, [r7, #20]
|
|
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
|
|
8007b8c: 687b ldr r3, [r7, #4]
|
|
8007b8e: 681b ldr r3, [r3, #0]
|
|
8007b90: 681b ldr r3, [r3, #0]
|
|
8007b92: 613b str r3, [r7, #16]
|
|
uint32_t tmperror;
|
|
|
|
/* I2C Bus error interrupt occurred ------------------------------------*/
|
|
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
|
|
8007b94: 697b ldr r3, [r7, #20]
|
|
8007b96: 0a1b lsrs r3, r3, #8
|
|
8007b98: f003 0301 and.w r3, r3, #1
|
|
8007b9c: 2b00 cmp r3, #0
|
|
8007b9e: d010 beq.n 8007bc2 <HAL_I2C_ER_IRQHandler+0x46>
|
|
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
|
|
8007ba0: 693b ldr r3, [r7, #16]
|
|
8007ba2: 09db lsrs r3, r3, #7
|
|
8007ba4: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
|
|
8007ba8: 2b00 cmp r3, #0
|
|
8007baa: d00a beq.n 8007bc2 <HAL_I2C_ER_IRQHandler+0x46>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
|
|
8007bac: 687b ldr r3, [r7, #4]
|
|
8007bae: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007bb0: f043 0201 orr.w r2, r3, #1
|
|
8007bb4: 687b ldr r3, [r7, #4]
|
|
8007bb6: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Clear BERR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
|
|
8007bb8: 687b ldr r3, [r7, #4]
|
|
8007bba: 681b ldr r3, [r3, #0]
|
|
8007bbc: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8007bc0: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
|
|
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
|
|
8007bc2: 697b ldr r3, [r7, #20]
|
|
8007bc4: 0a9b lsrs r3, r3, #10
|
|
8007bc6: f003 0301 and.w r3, r3, #1
|
|
8007bca: 2b00 cmp r3, #0
|
|
8007bcc: d010 beq.n 8007bf0 <HAL_I2C_ER_IRQHandler+0x74>
|
|
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
|
|
8007bce: 693b ldr r3, [r7, #16]
|
|
8007bd0: 09db lsrs r3, r3, #7
|
|
8007bd2: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
|
|
8007bd6: 2b00 cmp r3, #0
|
|
8007bd8: d00a beq.n 8007bf0 <HAL_I2C_ER_IRQHandler+0x74>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
|
|
8007bda: 687b ldr r3, [r7, #4]
|
|
8007bdc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007bde: f043 0208 orr.w r2, r3, #8
|
|
8007be2: 687b ldr r3, [r7, #4]
|
|
8007be4: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Clear OVR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
|
|
8007be6: 687b ldr r3, [r7, #4]
|
|
8007be8: 681b ldr r3, [r3, #0]
|
|
8007bea: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8007bee: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
|
|
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
|
|
8007bf0: 697b ldr r3, [r7, #20]
|
|
8007bf2: 0a5b lsrs r3, r3, #9
|
|
8007bf4: f003 0301 and.w r3, r3, #1
|
|
8007bf8: 2b00 cmp r3, #0
|
|
8007bfa: d010 beq.n 8007c1e <HAL_I2C_ER_IRQHandler+0xa2>
|
|
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
|
|
8007bfc: 693b ldr r3, [r7, #16]
|
|
8007bfe: 09db lsrs r3, r3, #7
|
|
8007c00: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
|
|
8007c04: 2b00 cmp r3, #0
|
|
8007c06: d00a beq.n 8007c1e <HAL_I2C_ER_IRQHandler+0xa2>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
|
|
8007c08: 687b ldr r3, [r7, #4]
|
|
8007c0a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007c0c: f043 0202 orr.w r2, r3, #2
|
|
8007c10: 687b ldr r3, [r7, #4]
|
|
8007c12: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Clear ARLO flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
|
|
8007c14: 687b ldr r3, [r7, #4]
|
|
8007c16: 681b ldr r3, [r3, #0]
|
|
8007c18: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8007c1c: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
/* Store current volatile hi2c->ErrorCode, misra rule */
|
|
tmperror = hi2c->ErrorCode;
|
|
8007c1e: 687b ldr r3, [r7, #4]
|
|
8007c20: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007c22: 60fb str r3, [r7, #12]
|
|
|
|
/* Call the Error Callback in case of Error detected */
|
|
if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
|
|
8007c24: 68fb ldr r3, [r7, #12]
|
|
8007c26: f003 030b and.w r3, r3, #11
|
|
8007c2a: 2b00 cmp r3, #0
|
|
8007c2c: d003 beq.n 8007c36 <HAL_I2C_ER_IRQHandler+0xba>
|
|
{
|
|
I2C_ITError(hi2c, tmperror);
|
|
8007c2e: 68f9 ldr r1, [r7, #12]
|
|
8007c30: 6878 ldr r0, [r7, #4]
|
|
8007c32: f001 f80b bl 8008c4c <I2C_ITError>
|
|
}
|
|
}
|
|
8007c36: bf00 nop
|
|
8007c38: 3718 adds r7, #24
|
|
8007c3a: 46bd mov sp, r7
|
|
8007c3c: bd80 pop {r7, pc}
|
|
|
|
08007c3e <HAL_I2C_MasterTxCpltCallback>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007c3e: b480 push {r7}
|
|
8007c40: b083 sub sp, #12
|
|
8007c42: af00 add r7, sp, #0
|
|
8007c44: 6078 str r0, [r7, #4]
|
|
UNUSED(hi2c);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8007c46: bf00 nop
|
|
8007c48: 370c adds r7, #12
|
|
8007c4a: 46bd mov sp, r7
|
|
8007c4c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c50: 4770 bx lr
|
|
|
|
08007c52 <HAL_I2C_MasterRxCpltCallback>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007c52: b480 push {r7}
|
|
8007c54: b083 sub sp, #12
|
|
8007c56: af00 add r7, sp, #0
|
|
8007c58: 6078 str r0, [r7, #4]
|
|
UNUSED(hi2c);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8007c5a: bf00 nop
|
|
8007c5c: 370c adds r7, #12
|
|
8007c5e: 46bd mov sp, r7
|
|
8007c60: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c64: 4770 bx lr
|
|
|
|
08007c66 <HAL_I2C_SlaveTxCpltCallback>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007c66: b480 push {r7}
|
|
8007c68: b083 sub sp, #12
|
|
8007c6a: af00 add r7, sp, #0
|
|
8007c6c: 6078 str r0, [r7, #4]
|
|
UNUSED(hi2c);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8007c6e: bf00 nop
|
|
8007c70: 370c adds r7, #12
|
|
8007c72: 46bd mov sp, r7
|
|
8007c74: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c78: 4770 bx lr
|
|
|
|
08007c7a <HAL_I2C_SlaveRxCpltCallback>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007c7a: b480 push {r7}
|
|
8007c7c: b083 sub sp, #12
|
|
8007c7e: af00 add r7, sp, #0
|
|
8007c80: 6078 str r0, [r7, #4]
|
|
UNUSED(hi2c);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8007c82: bf00 nop
|
|
8007c84: 370c adds r7, #12
|
|
8007c86: 46bd mov sp, r7
|
|
8007c88: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c8c: 4770 bx lr
|
|
|
|
08007c8e <HAL_I2C_AddrCallback>:
|
|
* @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
|
|
* @param AddrMatchCode Address Match Code
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
|
|
{
|
|
8007c8e: b480 push {r7}
|
|
8007c90: b083 sub sp, #12
|
|
8007c92: af00 add r7, sp, #0
|
|
8007c94: 6078 str r0, [r7, #4]
|
|
8007c96: 460b mov r3, r1
|
|
8007c98: 70fb strb r3, [r7, #3]
|
|
8007c9a: 4613 mov r3, r2
|
|
8007c9c: 803b strh r3, [r7, #0]
|
|
UNUSED(AddrMatchCode);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_I2C_AddrCallback() could be implemented in the user file
|
|
*/
|
|
}
|
|
8007c9e: bf00 nop
|
|
8007ca0: 370c adds r7, #12
|
|
8007ca2: 46bd mov sp, r7
|
|
8007ca4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007ca8: 4770 bx lr
|
|
|
|
08007caa <HAL_I2C_ListenCpltCallback>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007caa: b480 push {r7}
|
|
8007cac: b083 sub sp, #12
|
|
8007cae: af00 add r7, sp, #0
|
|
8007cb0: 6078 str r0, [r7, #4]
|
|
UNUSED(hi2c);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_I2C_ListenCpltCallback() could be implemented in the user file
|
|
*/
|
|
}
|
|
8007cb2: bf00 nop
|
|
8007cb4: 370c adds r7, #12
|
|
8007cb6: 46bd mov sp, r7
|
|
8007cb8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007cbc: 4770 bx lr
|
|
|
|
08007cbe <HAL_I2C_AbortCpltCallback>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007cbe: b480 push {r7}
|
|
8007cc0: b083 sub sp, #12
|
|
8007cc2: af00 add r7, sp, #0
|
|
8007cc4: 6078 str r0, [r7, #4]
|
|
UNUSED(hi2c);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_I2C_AbortCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8007cc6: bf00 nop
|
|
8007cc8: 370c adds r7, #12
|
|
8007cca: 46bd mov sp, r7
|
|
8007ccc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007cd0: 4770 bx lr
|
|
|
|
08007cd2 <HAL_I2C_GetError>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval I2C Error Code
|
|
*/
|
|
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007cd2: b480 push {r7}
|
|
8007cd4: b083 sub sp, #12
|
|
8007cd6: af00 add r7, sp, #0
|
|
8007cd8: 6078 str r0, [r7, #4]
|
|
return hi2c->ErrorCode;
|
|
8007cda: 687b ldr r3, [r7, #4]
|
|
8007cdc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
}
|
|
8007cde: 4618 mov r0, r3
|
|
8007ce0: 370c adds r7, #12
|
|
8007ce2: 46bd mov sp, r7
|
|
8007ce4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007ce8: 4770 bx lr
|
|
|
|
08007cea <I2C_Slave_ISR_IT>:
|
|
* @param ITSources Interrupt sources enabled.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
|
|
uint32_t ITSources)
|
|
{
|
|
8007cea: b580 push {r7, lr}
|
|
8007cec: b086 sub sp, #24
|
|
8007cee: af00 add r7, sp, #0
|
|
8007cf0: 60f8 str r0, [r7, #12]
|
|
8007cf2: 60b9 str r1, [r7, #8]
|
|
8007cf4: 607a str r2, [r7, #4]
|
|
uint32_t tmpoptions = hi2c->XferOptions;
|
|
8007cf6: 68fb ldr r3, [r7, #12]
|
|
8007cf8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007cfa: 617b str r3, [r7, #20]
|
|
uint32_t tmpITFlags = ITFlags;
|
|
8007cfc: 68bb ldr r3, [r7, #8]
|
|
8007cfe: 613b str r3, [r7, #16]
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hi2c);
|
|
8007d00: 68fb ldr r3, [r7, #12]
|
|
8007d02: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8007d06: 2b01 cmp r3, #1
|
|
8007d08: d101 bne.n 8007d0e <I2C_Slave_ISR_IT+0x24>
|
|
8007d0a: 2302 movs r3, #2
|
|
8007d0c: e0ed b.n 8007eea <I2C_Slave_ISR_IT+0x200>
|
|
8007d0e: 68fb ldr r3, [r7, #12]
|
|
8007d10: 2201 movs r2, #1
|
|
8007d12: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Check if STOPF is set */
|
|
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
|
|
8007d16: 693b ldr r3, [r7, #16]
|
|
8007d18: 095b lsrs r3, r3, #5
|
|
8007d1a: f003 0301 and.w r3, r3, #1
|
|
8007d1e: 2b00 cmp r3, #0
|
|
8007d20: d00a beq.n 8007d38 <I2C_Slave_ISR_IT+0x4e>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
|
|
8007d22: 687b ldr r3, [r7, #4]
|
|
8007d24: 095b lsrs r3, r3, #5
|
|
8007d26: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
|
|
8007d2a: 2b00 cmp r3, #0
|
|
8007d2c: d004 beq.n 8007d38 <I2C_Slave_ISR_IT+0x4e>
|
|
{
|
|
/* Call I2C Slave complete process */
|
|
I2C_ITSlaveCplt(hi2c, tmpITFlags);
|
|
8007d2e: 6939 ldr r1, [r7, #16]
|
|
8007d30: 68f8 ldr r0, [r7, #12]
|
|
8007d32: f000 fdcb bl 80088cc <I2C_ITSlaveCplt>
|
|
8007d36: e0d3 b.n 8007ee0 <I2C_Slave_ISR_IT+0x1f6>
|
|
}
|
|
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
|
8007d38: 693b ldr r3, [r7, #16]
|
|
8007d3a: 091b lsrs r3, r3, #4
|
|
8007d3c: f003 0301 and.w r3, r3, #1
|
|
8007d40: 2b00 cmp r3, #0
|
|
8007d42: d04d beq.n 8007de0 <I2C_Slave_ISR_IT+0xf6>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
|
8007d44: 687b ldr r3, [r7, #4]
|
|
8007d46: 091b lsrs r3, r3, #4
|
|
8007d48: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
|
8007d4c: 2b00 cmp r3, #0
|
|
8007d4e: d047 beq.n 8007de0 <I2C_Slave_ISR_IT+0xf6>
|
|
{
|
|
/* Check that I2C transfer finished */
|
|
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
|
/* Mean XferCount == 0*/
|
|
/* So clear Flag NACKF only */
|
|
if (hi2c->XferCount == 0U)
|
|
8007d50: 68fb ldr r3, [r7, #12]
|
|
8007d52: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007d54: b29b uxth r3, r3
|
|
8007d56: 2b00 cmp r3, #0
|
|
8007d58: d128 bne.n 8007dac <I2C_Slave_ISR_IT+0xc2>
|
|
{
|
|
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
|
8007d5a: 68fb ldr r3, [r7, #12]
|
|
8007d5c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8007d60: b2db uxtb r3, r3
|
|
8007d62: 2b28 cmp r3, #40 @ 0x28
|
|
8007d64: d108 bne.n 8007d78 <I2C_Slave_ISR_IT+0x8e>
|
|
8007d66: 697b ldr r3, [r7, #20]
|
|
8007d68: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
8007d6c: d104 bne.n 8007d78 <I2C_Slave_ISR_IT+0x8e>
|
|
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
|
|
Warning[Pa134]: left and right operands are identical */
|
|
{
|
|
/* Call I2C Listen complete process */
|
|
I2C_ITListenCplt(hi2c, tmpITFlags);
|
|
8007d6e: 6939 ldr r1, [r7, #16]
|
|
8007d70: 68f8 ldr r0, [r7, #12]
|
|
8007d72: f000 ff15 bl 8008ba0 <I2C_ITListenCplt>
|
|
8007d76: e032 b.n 8007dde <I2C_Slave_ISR_IT+0xf4>
|
|
}
|
|
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
|
|
8007d78: 68fb ldr r3, [r7, #12]
|
|
8007d7a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8007d7e: b2db uxtb r3, r3
|
|
8007d80: 2b29 cmp r3, #41 @ 0x29
|
|
8007d82: d10e bne.n 8007da2 <I2C_Slave_ISR_IT+0xb8>
|
|
8007d84: 697b ldr r3, [r7, #20]
|
|
8007d86: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
8007d8a: d00a beq.n 8007da2 <I2C_Slave_ISR_IT+0xb8>
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8007d8c: 68fb ldr r3, [r7, #12]
|
|
8007d8e: 681b ldr r3, [r3, #0]
|
|
8007d90: 2210 movs r2, #16
|
|
8007d92: 61da str r2, [r3, #28]
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8007d94: 68f8 ldr r0, [r7, #12]
|
|
8007d96: f001 f870 bl 8008e7a <I2C_Flush_TXDR>
|
|
|
|
/* Last Byte is Transmitted */
|
|
/* Call I2C Slave Sequential complete process */
|
|
I2C_ITSlaveSeqCplt(hi2c);
|
|
8007d9a: 68f8 ldr r0, [r7, #12]
|
|
8007d9c: f000 fc6e bl 800867c <I2C_ITSlaveSeqCplt>
|
|
8007da0: e01d b.n 8007dde <I2C_Slave_ISR_IT+0xf4>
|
|
}
|
|
else
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8007da2: 68fb ldr r3, [r7, #12]
|
|
8007da4: 681b ldr r3, [r3, #0]
|
|
8007da6: 2210 movs r2, #16
|
|
8007da8: 61da str r2, [r3, #28]
|
|
if (hi2c->XferCount == 0U)
|
|
8007daa: e096 b.n 8007eda <I2C_Slave_ISR_IT+0x1f0>
|
|
}
|
|
else
|
|
{
|
|
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8007dac: 68fb ldr r3, [r7, #12]
|
|
8007dae: 681b ldr r3, [r3, #0]
|
|
8007db0: 2210 movs r2, #16
|
|
8007db2: 61da str r2, [r3, #28]
|
|
|
|
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8007db4: 68fb ldr r3, [r7, #12]
|
|
8007db6: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007db8: f043 0204 orr.w r2, r3, #4
|
|
8007dbc: 68fb ldr r3, [r7, #12]
|
|
8007dbe: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
|
|
8007dc0: 697b ldr r3, [r7, #20]
|
|
8007dc2: 2b00 cmp r3, #0
|
|
8007dc4: d004 beq.n 8007dd0 <I2C_Slave_ISR_IT+0xe6>
|
|
8007dc6: 697b ldr r3, [r7, #20]
|
|
8007dc8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8007dcc: f040 8085 bne.w 8007eda <I2C_Slave_ISR_IT+0x1f0>
|
|
{
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, hi2c->ErrorCode);
|
|
8007dd0: 68fb ldr r3, [r7, #12]
|
|
8007dd2: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007dd4: 4619 mov r1, r3
|
|
8007dd6: 68f8 ldr r0, [r7, #12]
|
|
8007dd8: f000 ff38 bl 8008c4c <I2C_ITError>
|
|
if (hi2c->XferCount == 0U)
|
|
8007ddc: e07d b.n 8007eda <I2C_Slave_ISR_IT+0x1f0>
|
|
8007dde: e07c b.n 8007eda <I2C_Slave_ISR_IT+0x1f0>
|
|
}
|
|
}
|
|
}
|
|
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
|
|
8007de0: 693b ldr r3, [r7, #16]
|
|
8007de2: 089b lsrs r3, r3, #2
|
|
8007de4: f003 0301 and.w r3, r3, #1
|
|
8007de8: 2b00 cmp r3, #0
|
|
8007dea: d030 beq.n 8007e4e <I2C_Slave_ISR_IT+0x164>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
|
|
8007dec: 687b ldr r3, [r7, #4]
|
|
8007dee: 089b lsrs r3, r3, #2
|
|
8007df0: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
|
|
8007df4: 2b00 cmp r3, #0
|
|
8007df6: d02a beq.n 8007e4e <I2C_Slave_ISR_IT+0x164>
|
|
{
|
|
if (hi2c->XferCount > 0U)
|
|
8007df8: 68fb ldr r3, [r7, #12]
|
|
8007dfa: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007dfc: b29b uxth r3, r3
|
|
8007dfe: 2b00 cmp r3, #0
|
|
8007e00: d018 beq.n 8007e34 <I2C_Slave_ISR_IT+0x14a>
|
|
{
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
8007e02: 68fb ldr r3, [r7, #12]
|
|
8007e04: 681b ldr r3, [r3, #0]
|
|
8007e06: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8007e08: 68fb ldr r3, [r7, #12]
|
|
8007e0a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007e0c: b2d2 uxtb r2, r2
|
|
8007e0e: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8007e10: 68fb ldr r3, [r7, #12]
|
|
8007e12: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007e14: 1c5a adds r2, r3, #1
|
|
8007e16: 68fb ldr r3, [r7, #12]
|
|
8007e18: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferSize--;
|
|
8007e1a: 68fb ldr r3, [r7, #12]
|
|
8007e1c: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8007e1e: 3b01 subs r3, #1
|
|
8007e20: b29a uxth r2, r3
|
|
8007e22: 68fb ldr r3, [r7, #12]
|
|
8007e24: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
8007e26: 68fb ldr r3, [r7, #12]
|
|
8007e28: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007e2a: b29b uxth r3, r3
|
|
8007e2c: 3b01 subs r3, #1
|
|
8007e2e: b29a uxth r2, r3
|
|
8007e30: 68fb ldr r3, [r7, #12]
|
|
8007e32: 855a strh r2, [r3, #42] @ 0x2a
|
|
}
|
|
|
|
if ((hi2c->XferCount == 0U) && \
|
|
8007e34: 68fb ldr r3, [r7, #12]
|
|
8007e36: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007e38: b29b uxth r3, r3
|
|
8007e3a: 2b00 cmp r3, #0
|
|
8007e3c: d14f bne.n 8007ede <I2C_Slave_ISR_IT+0x1f4>
|
|
8007e3e: 697b ldr r3, [r7, #20]
|
|
8007e40: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
8007e44: d04b beq.n 8007ede <I2C_Slave_ISR_IT+0x1f4>
|
|
(tmpoptions != I2C_NO_OPTION_FRAME))
|
|
{
|
|
/* Call I2C Slave Sequential complete process */
|
|
I2C_ITSlaveSeqCplt(hi2c);
|
|
8007e46: 68f8 ldr r0, [r7, #12]
|
|
8007e48: f000 fc18 bl 800867c <I2C_ITSlaveSeqCplt>
|
|
if ((hi2c->XferCount == 0U) && \
|
|
8007e4c: e047 b.n 8007ede <I2C_Slave_ISR_IT+0x1f4>
|
|
}
|
|
}
|
|
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
|
|
8007e4e: 693b ldr r3, [r7, #16]
|
|
8007e50: 08db lsrs r3, r3, #3
|
|
8007e52: f003 0301 and.w r3, r3, #1
|
|
8007e56: 2b00 cmp r3, #0
|
|
8007e58: d00a beq.n 8007e70 <I2C_Slave_ISR_IT+0x186>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
|
|
8007e5a: 687b ldr r3, [r7, #4]
|
|
8007e5c: 08db lsrs r3, r3, #3
|
|
8007e5e: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
|
|
8007e62: 2b00 cmp r3, #0
|
|
8007e64: d004 beq.n 8007e70 <I2C_Slave_ISR_IT+0x186>
|
|
{
|
|
I2C_ITAddrCplt(hi2c, tmpITFlags);
|
|
8007e66: 6939 ldr r1, [r7, #16]
|
|
8007e68: 68f8 ldr r0, [r7, #12]
|
|
8007e6a: f000 fb46 bl 80084fa <I2C_ITAddrCplt>
|
|
8007e6e: e037 b.n 8007ee0 <I2C_Slave_ISR_IT+0x1f6>
|
|
}
|
|
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
|
|
8007e70: 693b ldr r3, [r7, #16]
|
|
8007e72: 085b lsrs r3, r3, #1
|
|
8007e74: f003 0301 and.w r3, r3, #1
|
|
8007e78: 2b00 cmp r3, #0
|
|
8007e7a: d031 beq.n 8007ee0 <I2C_Slave_ISR_IT+0x1f6>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
|
|
8007e7c: 687b ldr r3, [r7, #4]
|
|
8007e7e: 085b lsrs r3, r3, #1
|
|
8007e80: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
|
|
8007e84: 2b00 cmp r3, #0
|
|
8007e86: d02b beq.n 8007ee0 <I2C_Slave_ISR_IT+0x1f6>
|
|
{
|
|
/* Write data to TXDR only if XferCount not reach "0" */
|
|
/* A TXIS flag can be set, during STOP treatment */
|
|
/* Check if all Data have already been sent */
|
|
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
|
|
if (hi2c->XferCount > 0U)
|
|
8007e88: 68fb ldr r3, [r7, #12]
|
|
8007e8a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007e8c: b29b uxth r3, r3
|
|
8007e8e: 2b00 cmp r3, #0
|
|
8007e90: d018 beq.n 8007ec4 <I2C_Slave_ISR_IT+0x1da>
|
|
{
|
|
/* Write data to TXDR */
|
|
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
|
8007e92: 68fb ldr r3, [r7, #12]
|
|
8007e94: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007e96: 781a ldrb r2, [r3, #0]
|
|
8007e98: 68fb ldr r3, [r7, #12]
|
|
8007e9a: 681b ldr r3, [r3, #0]
|
|
8007e9c: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8007e9e: 68fb ldr r3, [r7, #12]
|
|
8007ea0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007ea2: 1c5a adds r2, r3, #1
|
|
8007ea4: 68fb ldr r3, [r7, #12]
|
|
8007ea6: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferCount--;
|
|
8007ea8: 68fb ldr r3, [r7, #12]
|
|
8007eaa: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007eac: b29b uxth r3, r3
|
|
8007eae: 3b01 subs r3, #1
|
|
8007eb0: b29a uxth r2, r3
|
|
8007eb2: 68fb ldr r3, [r7, #12]
|
|
8007eb4: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize--;
|
|
8007eb6: 68fb ldr r3, [r7, #12]
|
|
8007eb8: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8007eba: 3b01 subs r3, #1
|
|
8007ebc: b29a uxth r2, r3
|
|
8007ebe: 68fb ldr r3, [r7, #12]
|
|
8007ec0: 851a strh r2, [r3, #40] @ 0x28
|
|
8007ec2: e00d b.n 8007ee0 <I2C_Slave_ISR_IT+0x1f6>
|
|
}
|
|
else
|
|
{
|
|
if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
|
|
8007ec4: 697b ldr r3, [r7, #20]
|
|
8007ec6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8007eca: d002 beq.n 8007ed2 <I2C_Slave_ISR_IT+0x1e8>
|
|
8007ecc: 697b ldr r3, [r7, #20]
|
|
8007ece: 2b00 cmp r3, #0
|
|
8007ed0: d106 bne.n 8007ee0 <I2C_Slave_ISR_IT+0x1f6>
|
|
{
|
|
/* Last Byte is Transmitted */
|
|
/* Call I2C Slave Sequential complete process */
|
|
I2C_ITSlaveSeqCplt(hi2c);
|
|
8007ed2: 68f8 ldr r0, [r7, #12]
|
|
8007ed4: f000 fbd2 bl 800867c <I2C_ITSlaveSeqCplt>
|
|
8007ed8: e002 b.n 8007ee0 <I2C_Slave_ISR_IT+0x1f6>
|
|
if (hi2c->XferCount == 0U)
|
|
8007eda: bf00 nop
|
|
8007edc: e000 b.n 8007ee0 <I2C_Slave_ISR_IT+0x1f6>
|
|
if ((hi2c->XferCount == 0U) && \
|
|
8007ede: bf00 nop
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007ee0: 68fb ldr r3, [r7, #12]
|
|
8007ee2: 2200 movs r2, #0
|
|
8007ee4: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8007ee8: 2300 movs r3, #0
|
|
}
|
|
8007eea: 4618 mov r0, r3
|
|
8007eec: 3718 adds r7, #24
|
|
8007eee: 46bd mov sp, r7
|
|
8007ef0: bd80 pop {r7, pc}
|
|
|
|
08007ef2 <I2C_Master_ISR_DMA>:
|
|
* @param ITSources Interrupt sources enabled.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
|
|
uint32_t ITSources)
|
|
{
|
|
8007ef2: b580 push {r7, lr}
|
|
8007ef4: b088 sub sp, #32
|
|
8007ef6: af02 add r7, sp, #8
|
|
8007ef8: 60f8 str r0, [r7, #12]
|
|
8007efa: 60b9 str r1, [r7, #8]
|
|
8007efc: 607a str r2, [r7, #4]
|
|
uint16_t devaddress;
|
|
uint32_t xfermode;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8007efe: 68fb ldr r3, [r7, #12]
|
|
8007f00: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8007f04: 2b01 cmp r3, #1
|
|
8007f06: d101 bne.n 8007f0c <I2C_Master_ISR_DMA+0x1a>
|
|
8007f08: 2302 movs r3, #2
|
|
8007f0a: e0e1 b.n 80080d0 <I2C_Master_ISR_DMA+0x1de>
|
|
8007f0c: 68fb ldr r3, [r7, #12]
|
|
8007f0e: 2201 movs r2, #1
|
|
8007f10: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
|
8007f14: 68bb ldr r3, [r7, #8]
|
|
8007f16: 091b lsrs r3, r3, #4
|
|
8007f18: f003 0301 and.w r3, r3, #1
|
|
8007f1c: 2b00 cmp r3, #0
|
|
8007f1e: d017 beq.n 8007f50 <I2C_Master_ISR_DMA+0x5e>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
|
8007f20: 687b ldr r3, [r7, #4]
|
|
8007f22: 091b lsrs r3, r3, #4
|
|
8007f24: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
|
8007f28: 2b00 cmp r3, #0
|
|
8007f2a: d011 beq.n 8007f50 <I2C_Master_ISR_DMA+0x5e>
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8007f2c: 68fb ldr r3, [r7, #12]
|
|
8007f2e: 681b ldr r3, [r3, #0]
|
|
8007f30: 2210 movs r2, #16
|
|
8007f32: 61da str r2, [r3, #28]
|
|
|
|
/* Set corresponding Error Code */
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8007f34: 68fb ldr r3, [r7, #12]
|
|
8007f36: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8007f38: f043 0204 orr.w r2, r3, #4
|
|
8007f3c: 68fb ldr r3, [r7, #12]
|
|
8007f3e: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* No need to generate STOP, it is automatically done */
|
|
/* But enable STOP interrupt, to treat it */
|
|
/* Error callback will be send during stop flag treatment */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
|
|
8007f40: 2120 movs r1, #32
|
|
8007f42: 68f8 ldr r0, [r7, #12]
|
|
8007f44: f001 f8ba bl 80090bc <I2C_Enable_IRQ>
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8007f48: 68f8 ldr r0, [r7, #12]
|
|
8007f4a: f000 ff96 bl 8008e7a <I2C_Flush_TXDR>
|
|
8007f4e: e0ba b.n 80080c6 <I2C_Master_ISR_DMA+0x1d4>
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
|
|
8007f50: 68bb ldr r3, [r7, #8]
|
|
8007f52: 09db lsrs r3, r3, #7
|
|
8007f54: f003 0301 and.w r3, r3, #1
|
|
8007f58: 2b00 cmp r3, #0
|
|
8007f5a: d072 beq.n 8008042 <I2C_Master_ISR_DMA+0x150>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
|
8007f5c: 687b ldr r3, [r7, #4]
|
|
8007f5e: 099b lsrs r3, r3, #6
|
|
8007f60: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
|
|
8007f64: 2b00 cmp r3, #0
|
|
8007f66: d06c beq.n 8008042 <I2C_Master_ISR_DMA+0x150>
|
|
{
|
|
/* Disable TC interrupt */
|
|
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
|
|
8007f68: 68fb ldr r3, [r7, #12]
|
|
8007f6a: 681b ldr r3, [r3, #0]
|
|
8007f6c: 681a ldr r2, [r3, #0]
|
|
8007f6e: 68fb ldr r3, [r7, #12]
|
|
8007f70: 681b ldr r3, [r3, #0]
|
|
8007f72: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8007f76: 601a str r2, [r3, #0]
|
|
|
|
if (hi2c->XferCount != 0U)
|
|
8007f78: 68fb ldr r3, [r7, #12]
|
|
8007f7a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007f7c: b29b uxth r3, r3
|
|
8007f7e: 2b00 cmp r3, #0
|
|
8007f80: d04e beq.n 8008020 <I2C_Master_ISR_DMA+0x12e>
|
|
{
|
|
/* Recover Slave address */
|
|
devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
|
|
8007f82: 68fb ldr r3, [r7, #12]
|
|
8007f84: 681b ldr r3, [r3, #0]
|
|
8007f86: 685b ldr r3, [r3, #4]
|
|
8007f88: b29b uxth r3, r3
|
|
8007f8a: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8007f8e: 827b strh r3, [r7, #18]
|
|
|
|
/* Prepare the new XferSize to transfer */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8007f90: 68fb ldr r3, [r7, #12]
|
|
8007f92: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007f94: b29b uxth r3, r3
|
|
8007f96: 2bff cmp r3, #255 @ 0xff
|
|
8007f98: d906 bls.n 8007fa8 <I2C_Master_ISR_DMA+0xb6>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8007f9a: 68fb ldr r3, [r7, #12]
|
|
8007f9c: 22ff movs r2, #255 @ 0xff
|
|
8007f9e: 851a strh r2, [r3, #40] @ 0x28
|
|
xfermode = I2C_RELOAD_MODE;
|
|
8007fa0: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8007fa4: 617b str r3, [r7, #20]
|
|
8007fa6: e010 b.n 8007fca <I2C_Master_ISR_DMA+0xd8>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8007fa8: 68fb ldr r3, [r7, #12]
|
|
8007faa: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007fac: b29a uxth r2, r3
|
|
8007fae: 68fb ldr r3, [r7, #12]
|
|
8007fb0: 851a strh r2, [r3, #40] @ 0x28
|
|
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
|
|
8007fb2: 68fb ldr r3, [r7, #12]
|
|
8007fb4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007fb6: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
8007fba: d003 beq.n 8007fc4 <I2C_Master_ISR_DMA+0xd2>
|
|
{
|
|
xfermode = hi2c->XferOptions;
|
|
8007fbc: 68fb ldr r3, [r7, #12]
|
|
8007fbe: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007fc0: 617b str r3, [r7, #20]
|
|
8007fc2: e002 b.n 8007fca <I2C_Master_ISR_DMA+0xd8>
|
|
}
|
|
else
|
|
{
|
|
xfermode = I2C_AUTOEND_MODE;
|
|
8007fc4: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8007fc8: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
|
|
/* Set the new XferSize in Nbytes register */
|
|
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
|
|
8007fca: 68fb ldr r3, [r7, #12]
|
|
8007fcc: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8007fce: b2da uxtb r2, r3
|
|
8007fd0: 8a79 ldrh r1, [r7, #18]
|
|
8007fd2: 2300 movs r3, #0
|
|
8007fd4: 9300 str r3, [sp, #0]
|
|
8007fd6: 697b ldr r3, [r7, #20]
|
|
8007fd8: 68f8 ldr r0, [r7, #12]
|
|
8007fda: f001 f83d bl 8009058 <I2C_TransferConfig>
|
|
|
|
/* Update XferCount value */
|
|
hi2c->XferCount -= hi2c->XferSize;
|
|
8007fde: 68fb ldr r3, [r7, #12]
|
|
8007fe0: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8007fe2: b29a uxth r2, r3
|
|
8007fe4: 68fb ldr r3, [r7, #12]
|
|
8007fe6: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8007fe8: 1ad3 subs r3, r2, r3
|
|
8007fea: b29a uxth r2, r3
|
|
8007fec: 68fb ldr r3, [r7, #12]
|
|
8007fee: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
/* Enable DMA Request */
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
8007ff0: 68fb ldr r3, [r7, #12]
|
|
8007ff2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8007ff6: b2db uxtb r3, r3
|
|
8007ff8: 2b22 cmp r3, #34 @ 0x22
|
|
8007ffa: d108 bne.n 800800e <I2C_Master_ISR_DMA+0x11c>
|
|
{
|
|
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
|
|
8007ffc: 68fb ldr r3, [r7, #12]
|
|
8007ffe: 681b ldr r3, [r3, #0]
|
|
8008000: 681a ldr r2, [r3, #0]
|
|
8008002: 68fb ldr r3, [r7, #12]
|
|
8008004: 681b ldr r3, [r3, #0]
|
|
8008006: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
800800a: 601a str r2, [r3, #0]
|
|
if (hi2c->XferCount != 0U)
|
|
800800c: e05b b.n 80080c6 <I2C_Master_ISR_DMA+0x1d4>
|
|
}
|
|
else
|
|
{
|
|
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
|
|
800800e: 68fb ldr r3, [r7, #12]
|
|
8008010: 681b ldr r3, [r3, #0]
|
|
8008012: 681a ldr r2, [r3, #0]
|
|
8008014: 68fb ldr r3, [r7, #12]
|
|
8008016: 681b ldr r3, [r3, #0]
|
|
8008018: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
800801c: 601a str r2, [r3, #0]
|
|
if (hi2c->XferCount != 0U)
|
|
800801e: e052 b.n 80080c6 <I2C_Master_ISR_DMA+0x1d4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Call TxCpltCallback() if no stop mode is set */
|
|
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
|
|
8008020: 68fb ldr r3, [r7, #12]
|
|
8008022: 681b ldr r3, [r3, #0]
|
|
8008024: 685b ldr r3, [r3, #4]
|
|
8008026: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800802a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
800802e: d003 beq.n 8008038 <I2C_Master_ISR_DMA+0x146>
|
|
{
|
|
/* Call I2C Master Sequential complete process */
|
|
I2C_ITMasterSeqCplt(hi2c);
|
|
8008030: 68f8 ldr r0, [r7, #12]
|
|
8008032: f000 fae6 bl 8008602 <I2C_ITMasterSeqCplt>
|
|
if (hi2c->XferCount != 0U)
|
|
8008036: e046 b.n 80080c6 <I2C_Master_ISR_DMA+0x1d4>
|
|
}
|
|
else
|
|
{
|
|
/* Wrong size Status regarding TCR flag event */
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
|
|
8008038: 2140 movs r1, #64 @ 0x40
|
|
800803a: 68f8 ldr r0, [r7, #12]
|
|
800803c: f000 fe06 bl 8008c4c <I2C_ITError>
|
|
if (hi2c->XferCount != 0U)
|
|
8008040: e041 b.n 80080c6 <I2C_Master_ISR_DMA+0x1d4>
|
|
}
|
|
}
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
|
|
8008042: 68bb ldr r3, [r7, #8]
|
|
8008044: 099b lsrs r3, r3, #6
|
|
8008046: f003 0301 and.w r3, r3, #1
|
|
800804a: 2b00 cmp r3, #0
|
|
800804c: d029 beq.n 80080a2 <I2C_Master_ISR_DMA+0x1b0>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
|
800804e: 687b ldr r3, [r7, #4]
|
|
8008050: 099b lsrs r3, r3, #6
|
|
8008052: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
|
|
8008056: 2b00 cmp r3, #0
|
|
8008058: d023 beq.n 80080a2 <I2C_Master_ISR_DMA+0x1b0>
|
|
{
|
|
if (hi2c->XferCount == 0U)
|
|
800805a: 68fb ldr r3, [r7, #12]
|
|
800805c: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800805e: b29b uxth r3, r3
|
|
8008060: 2b00 cmp r3, #0
|
|
8008062: d119 bne.n 8008098 <I2C_Master_ISR_DMA+0x1a6>
|
|
{
|
|
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
|
|
8008064: 68fb ldr r3, [r7, #12]
|
|
8008066: 681b ldr r3, [r3, #0]
|
|
8008068: 685b ldr r3, [r3, #4]
|
|
800806a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800806e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
8008072: d027 beq.n 80080c4 <I2C_Master_ISR_DMA+0x1d2>
|
|
{
|
|
/* Generate a stop condition in case of no transfer option */
|
|
if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
|
|
8008074: 68fb ldr r3, [r7, #12]
|
|
8008076: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008078: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
800807c: d108 bne.n 8008090 <I2C_Master_ISR_DMA+0x19e>
|
|
{
|
|
/* Generate Stop */
|
|
hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
|
800807e: 68fb ldr r3, [r7, #12]
|
|
8008080: 681b ldr r3, [r3, #0]
|
|
8008082: 685a ldr r2, [r3, #4]
|
|
8008084: 68fb ldr r3, [r7, #12]
|
|
8008086: 681b ldr r3, [r3, #0]
|
|
8008088: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
800808c: 605a str r2, [r3, #4]
|
|
if (hi2c->XferCount == 0U)
|
|
800808e: e019 b.n 80080c4 <I2C_Master_ISR_DMA+0x1d2>
|
|
}
|
|
else
|
|
{
|
|
/* Call I2C Master Sequential complete process */
|
|
I2C_ITMasterSeqCplt(hi2c);
|
|
8008090: 68f8 ldr r0, [r7, #12]
|
|
8008092: f000 fab6 bl 8008602 <I2C_ITMasterSeqCplt>
|
|
if (hi2c->XferCount == 0U)
|
|
8008096: e015 b.n 80080c4 <I2C_Master_ISR_DMA+0x1d2>
|
|
}
|
|
else
|
|
{
|
|
/* Wrong size Status regarding TC flag event */
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
|
|
8008098: 2140 movs r1, #64 @ 0x40
|
|
800809a: 68f8 ldr r0, [r7, #12]
|
|
800809c: f000 fdd6 bl 8008c4c <I2C_ITError>
|
|
if (hi2c->XferCount == 0U)
|
|
80080a0: e010 b.n 80080c4 <I2C_Master_ISR_DMA+0x1d2>
|
|
}
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
|
|
80080a2: 68bb ldr r3, [r7, #8]
|
|
80080a4: 095b lsrs r3, r3, #5
|
|
80080a6: f003 0301 and.w r3, r3, #1
|
|
80080aa: 2b00 cmp r3, #0
|
|
80080ac: d00b beq.n 80080c6 <I2C_Master_ISR_DMA+0x1d4>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
|
|
80080ae: 687b ldr r3, [r7, #4]
|
|
80080b0: 095b lsrs r3, r3, #5
|
|
80080b2: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
|
|
80080b6: 2b00 cmp r3, #0
|
|
80080b8: d005 beq.n 80080c6 <I2C_Master_ISR_DMA+0x1d4>
|
|
{
|
|
/* Call I2C Master complete process */
|
|
I2C_ITMasterCplt(hi2c, ITFlags);
|
|
80080ba: 68b9 ldr r1, [r7, #8]
|
|
80080bc: 68f8 ldr r0, [r7, #12]
|
|
80080be: f000 fb3b bl 8008738 <I2C_ITMasterCplt>
|
|
80080c2: e000 b.n 80080c6 <I2C_Master_ISR_DMA+0x1d4>
|
|
if (hi2c->XferCount == 0U)
|
|
80080c4: bf00 nop
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80080c6: 68fb ldr r3, [r7, #12]
|
|
80080c8: 2200 movs r2, #0
|
|
80080ca: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
80080ce: 2300 movs r3, #0
|
|
}
|
|
80080d0: 4618 mov r0, r3
|
|
80080d2: 3718 adds r7, #24
|
|
80080d4: 46bd mov sp, r7
|
|
80080d6: bd80 pop {r7, pc}
|
|
|
|
080080d8 <I2C_Mem_ISR_DMA>:
|
|
* @param ITSources Interrupt sources enabled.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
|
|
uint32_t ITSources)
|
|
{
|
|
80080d8: b580 push {r7, lr}
|
|
80080da: b088 sub sp, #32
|
|
80080dc: af02 add r7, sp, #8
|
|
80080de: 60f8 str r0, [r7, #12]
|
|
80080e0: 60b9 str r1, [r7, #8]
|
|
80080e2: 607a str r2, [r7, #4]
|
|
uint32_t direction = I2C_GENERATE_START_WRITE;
|
|
80080e4: 4b92 ldr r3, [pc, #584] @ (8008330 <I2C_Mem_ISR_DMA+0x258>)
|
|
80080e6: 617b str r3, [r7, #20]
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80080e8: 68fb ldr r3, [r7, #12]
|
|
80080ea: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
80080ee: 2b01 cmp r3, #1
|
|
80080f0: d101 bne.n 80080f6 <I2C_Mem_ISR_DMA+0x1e>
|
|
80080f2: 2302 movs r3, #2
|
|
80080f4: e118 b.n 8008328 <I2C_Mem_ISR_DMA+0x250>
|
|
80080f6: 68fb ldr r3, [r7, #12]
|
|
80080f8: 2201 movs r2, #1
|
|
80080fa: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
|
80080fe: 68bb ldr r3, [r7, #8]
|
|
8008100: 091b lsrs r3, r3, #4
|
|
8008102: f003 0301 and.w r3, r3, #1
|
|
8008106: 2b00 cmp r3, #0
|
|
8008108: d017 beq.n 800813a <I2C_Mem_ISR_DMA+0x62>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
|
800810a: 687b ldr r3, [r7, #4]
|
|
800810c: 091b lsrs r3, r3, #4
|
|
800810e: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
|
8008112: 2b00 cmp r3, #0
|
|
8008114: d011 beq.n 800813a <I2C_Mem_ISR_DMA+0x62>
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8008116: 68fb ldr r3, [r7, #12]
|
|
8008118: 681b ldr r3, [r3, #0]
|
|
800811a: 2210 movs r2, #16
|
|
800811c: 61da str r2, [r3, #28]
|
|
|
|
/* Set corresponding Error Code */
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
800811e: 68fb ldr r3, [r7, #12]
|
|
8008120: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008122: f043 0204 orr.w r2, r3, #4
|
|
8008126: 68fb ldr r3, [r7, #12]
|
|
8008128: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* No need to generate STOP, it is automatically done */
|
|
/* But enable STOP interrupt, to treat it */
|
|
/* Error callback will be send during stop flag treatment */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
|
|
800812a: 2120 movs r1, #32
|
|
800812c: 68f8 ldr r0, [r7, #12]
|
|
800812e: f000 ffc5 bl 80090bc <I2C_Enable_IRQ>
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8008132: 68f8 ldr r0, [r7, #12]
|
|
8008134: f000 fea1 bl 8008e7a <I2C_Flush_TXDR>
|
|
8008138: e0f1 b.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
|
|
800813a: 68bb ldr r3, [r7, #8]
|
|
800813c: 085b lsrs r3, r3, #1
|
|
800813e: f003 0301 and.w r3, r3, #1
|
|
8008142: 2b00 cmp r3, #0
|
|
8008144: d00f beq.n 8008166 <I2C_Mem_ISR_DMA+0x8e>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
|
|
8008146: 687b ldr r3, [r7, #4]
|
|
8008148: 085b lsrs r3, r3, #1
|
|
800814a: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
|
|
800814e: 2b00 cmp r3, #0
|
|
8008150: d009 beq.n 8008166 <I2C_Mem_ISR_DMA+0x8e>
|
|
{
|
|
/* Write LSB part of Memory Address */
|
|
hi2c->Instance->TXDR = hi2c->Memaddress;
|
|
8008152: 68fb ldr r3, [r7, #12]
|
|
8008154: 681b ldr r3, [r3, #0]
|
|
8008156: 68fa ldr r2, [r7, #12]
|
|
8008158: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
800815a: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Reset Memaddress content */
|
|
hi2c->Memaddress = 0xFFFFFFFFU;
|
|
800815c: 68fb ldr r3, [r7, #12]
|
|
800815e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8008162: 651a str r2, [r3, #80] @ 0x50
|
|
8008164: e0db b.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
|
|
8008166: 68bb ldr r3, [r7, #8]
|
|
8008168: 09db lsrs r3, r3, #7
|
|
800816a: f003 0301 and.w r3, r3, #1
|
|
800816e: 2b00 cmp r3, #0
|
|
8008170: d060 beq.n 8008234 <I2C_Mem_ISR_DMA+0x15c>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
|
8008172: 687b ldr r3, [r7, #4]
|
|
8008174: 099b lsrs r3, r3, #6
|
|
8008176: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
|
|
800817a: 2b00 cmp r3, #0
|
|
800817c: d05a beq.n 8008234 <I2C_Mem_ISR_DMA+0x15c>
|
|
{
|
|
/* Disable Interrupt related to address step */
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
|
800817e: 2101 movs r1, #1
|
|
8008180: 68f8 ldr r0, [r7, #12]
|
|
8008182: f001 f81f bl 80091c4 <I2C_Disable_IRQ>
|
|
|
|
/* Enable only Error interrupt */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
|
|
8008186: 2110 movs r1, #16
|
|
8008188: 68f8 ldr r0, [r7, #12]
|
|
800818a: f000 ff97 bl 80090bc <I2C_Enable_IRQ>
|
|
|
|
if (hi2c->XferCount != 0U)
|
|
800818e: 68fb ldr r3, [r7, #12]
|
|
8008190: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008192: b29b uxth r3, r3
|
|
8008194: 2b00 cmp r3, #0
|
|
8008196: d048 beq.n 800822a <I2C_Mem_ISR_DMA+0x152>
|
|
{
|
|
/* Prepare the new XferSize to transfer */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8008198: 68fb ldr r3, [r7, #12]
|
|
800819a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800819c: b29b uxth r3, r3
|
|
800819e: 2bff cmp r3, #255 @ 0xff
|
|
80081a0: d910 bls.n 80081c4 <I2C_Mem_ISR_DMA+0xec>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
80081a2: 68fb ldr r3, [r7, #12]
|
|
80081a4: 22ff movs r2, #255 @ 0xff
|
|
80081a6: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
|
|
80081a8: 68fb ldr r3, [r7, #12]
|
|
80081aa: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80081ac: b299 uxth r1, r3
|
|
80081ae: 68fb ldr r3, [r7, #12]
|
|
80081b0: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80081b2: b2da uxtb r2, r3
|
|
80081b4: 2300 movs r3, #0
|
|
80081b6: 9300 str r3, [sp, #0]
|
|
80081b8: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
80081bc: 68f8 ldr r0, [r7, #12]
|
|
80081be: f000 ff4b bl 8009058 <I2C_TransferConfig>
|
|
80081c2: e011 b.n 80081e8 <I2C_Mem_ISR_DMA+0x110>
|
|
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
80081c4: 68fb ldr r3, [r7, #12]
|
|
80081c6: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80081c8: b29a uxth r2, r3
|
|
80081ca: 68fb ldr r3, [r7, #12]
|
|
80081cc: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
|
|
80081ce: 68fb ldr r3, [r7, #12]
|
|
80081d0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80081d2: b299 uxth r1, r3
|
|
80081d4: 68fb ldr r3, [r7, #12]
|
|
80081d6: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80081d8: b2da uxtb r2, r3
|
|
80081da: 2300 movs r3, #0
|
|
80081dc: 9300 str r3, [sp, #0]
|
|
80081de: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
80081e2: 68f8 ldr r0, [r7, #12]
|
|
80081e4: f000 ff38 bl 8009058 <I2C_TransferConfig>
|
|
I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
}
|
|
|
|
/* Update XferCount value */
|
|
hi2c->XferCount -= hi2c->XferSize;
|
|
80081e8: 68fb ldr r3, [r7, #12]
|
|
80081ea: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80081ec: b29a uxth r2, r3
|
|
80081ee: 68fb ldr r3, [r7, #12]
|
|
80081f0: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80081f2: 1ad3 subs r3, r2, r3
|
|
80081f4: b29a uxth r2, r3
|
|
80081f6: 68fb ldr r3, [r7, #12]
|
|
80081f8: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
/* Enable DMA Request */
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
80081fa: 68fb ldr r3, [r7, #12]
|
|
80081fc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008200: b2db uxtb r3, r3
|
|
8008202: 2b22 cmp r3, #34 @ 0x22
|
|
8008204: d108 bne.n 8008218 <I2C_Mem_ISR_DMA+0x140>
|
|
{
|
|
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
|
|
8008206: 68fb ldr r3, [r7, #12]
|
|
8008208: 681b ldr r3, [r3, #0]
|
|
800820a: 681a ldr r2, [r3, #0]
|
|
800820c: 68fb ldr r3, [r7, #12]
|
|
800820e: 681b ldr r3, [r3, #0]
|
|
8008210: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8008214: 601a str r2, [r3, #0]
|
|
if (hi2c->XferCount != 0U)
|
|
8008216: e082 b.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
}
|
|
else
|
|
{
|
|
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
|
|
8008218: 68fb ldr r3, [r7, #12]
|
|
800821a: 681b ldr r3, [r3, #0]
|
|
800821c: 681a ldr r2, [r3, #0]
|
|
800821e: 68fb ldr r3, [r7, #12]
|
|
8008220: 681b ldr r3, [r3, #0]
|
|
8008222: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
8008226: 601a str r2, [r3, #0]
|
|
if (hi2c->XferCount != 0U)
|
|
8008228: e079 b.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
}
|
|
else
|
|
{
|
|
/* Wrong size Status regarding TCR flag event */
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
|
|
800822a: 2140 movs r1, #64 @ 0x40
|
|
800822c: 68f8 ldr r0, [r7, #12]
|
|
800822e: f000 fd0d bl 8008c4c <I2C_ITError>
|
|
if (hi2c->XferCount != 0U)
|
|
8008232: e074 b.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
}
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
|
|
8008234: 68bb ldr r3, [r7, #8]
|
|
8008236: 099b lsrs r3, r3, #6
|
|
8008238: f003 0301 and.w r3, r3, #1
|
|
800823c: 2b00 cmp r3, #0
|
|
800823e: d05e beq.n 80082fe <I2C_Mem_ISR_DMA+0x226>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
|
8008240: 687b ldr r3, [r7, #4]
|
|
8008242: 099b lsrs r3, r3, #6
|
|
8008244: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
|
|
8008248: 2b00 cmp r3, #0
|
|
800824a: d058 beq.n 80082fe <I2C_Mem_ISR_DMA+0x226>
|
|
{
|
|
/* Disable Interrupt related to address step */
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
|
800824c: 2101 movs r1, #1
|
|
800824e: 68f8 ldr r0, [r7, #12]
|
|
8008250: f000 ffb8 bl 80091c4 <I2C_Disable_IRQ>
|
|
|
|
/* Enable only Error and NACK interrupt for data transfer */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
|
|
8008254: 2110 movs r1, #16
|
|
8008256: 68f8 ldr r0, [r7, #12]
|
|
8008258: f000 ff30 bl 80090bc <I2C_Enable_IRQ>
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
800825c: 68fb ldr r3, [r7, #12]
|
|
800825e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008262: b2db uxtb r3, r3
|
|
8008264: 2b22 cmp r3, #34 @ 0x22
|
|
8008266: d101 bne.n 800826c <I2C_Mem_ISR_DMA+0x194>
|
|
{
|
|
direction = I2C_GENERATE_START_READ;
|
|
8008268: 4b32 ldr r3, [pc, #200] @ (8008334 <I2C_Mem_ISR_DMA+0x25c>)
|
|
800826a: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
800826c: 68fb ldr r3, [r7, #12]
|
|
800826e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008270: b29b uxth r3, r3
|
|
8008272: 2bff cmp r3, #255 @ 0xff
|
|
8008274: d910 bls.n 8008298 <I2C_Mem_ISR_DMA+0x1c0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8008276: 68fb ldr r3, [r7, #12]
|
|
8008278: 22ff movs r2, #255 @ 0xff
|
|
800827a: 851a strh r2, [r3, #40] @ 0x28
|
|
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
|
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
|
|
800827c: 68fb ldr r3, [r7, #12]
|
|
800827e: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8008280: b299 uxth r1, r3
|
|
8008282: 68fb ldr r3, [r7, #12]
|
|
8008284: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8008286: b2da uxtb r2, r3
|
|
8008288: 697b ldr r3, [r7, #20]
|
|
800828a: 9300 str r3, [sp, #0]
|
|
800828c: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8008290: 68f8 ldr r0, [r7, #12]
|
|
8008292: f000 fee1 bl 8009058 <I2C_TransferConfig>
|
|
8008296: e011 b.n 80082bc <I2C_Mem_ISR_DMA+0x1e4>
|
|
I2C_RELOAD_MODE, direction);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8008298: 68fb ldr r3, [r7, #12]
|
|
800829a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800829c: b29a uxth r2, r3
|
|
800829e: 68fb ldr r3, [r7, #12]
|
|
80082a0: 851a strh r2, [r3, #40] @ 0x28
|
|
|
|
/* Set NBYTES to write and generate RESTART */
|
|
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
|
|
80082a2: 68fb ldr r3, [r7, #12]
|
|
80082a4: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80082a6: b299 uxth r1, r3
|
|
80082a8: 68fb ldr r3, [r7, #12]
|
|
80082aa: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80082ac: b2da uxtb r2, r3
|
|
80082ae: 697b ldr r3, [r7, #20]
|
|
80082b0: 9300 str r3, [sp, #0]
|
|
80082b2: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
80082b6: 68f8 ldr r0, [r7, #12]
|
|
80082b8: f000 fece bl 8009058 <I2C_TransferConfig>
|
|
I2C_AUTOEND_MODE, direction);
|
|
}
|
|
|
|
/* Update XferCount value */
|
|
hi2c->XferCount -= hi2c->XferSize;
|
|
80082bc: 68fb ldr r3, [r7, #12]
|
|
80082be: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80082c0: b29a uxth r2, r3
|
|
80082c2: 68fb ldr r3, [r7, #12]
|
|
80082c4: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80082c6: 1ad3 subs r3, r2, r3
|
|
80082c8: b29a uxth r2, r3
|
|
80082ca: 68fb ldr r3, [r7, #12]
|
|
80082cc: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
/* Enable DMA Request */
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
80082ce: 68fb ldr r3, [r7, #12]
|
|
80082d0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80082d4: b2db uxtb r3, r3
|
|
80082d6: 2b22 cmp r3, #34 @ 0x22
|
|
80082d8: d108 bne.n 80082ec <I2C_Mem_ISR_DMA+0x214>
|
|
{
|
|
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
|
|
80082da: 68fb ldr r3, [r7, #12]
|
|
80082dc: 681b ldr r3, [r3, #0]
|
|
80082de: 681a ldr r2, [r3, #0]
|
|
80082e0: 68fb ldr r3, [r7, #12]
|
|
80082e2: 681b ldr r3, [r3, #0]
|
|
80082e4: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
80082e8: 601a str r2, [r3, #0]
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
80082ea: e018 b.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
}
|
|
else
|
|
{
|
|
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
|
|
80082ec: 68fb ldr r3, [r7, #12]
|
|
80082ee: 681b ldr r3, [r3, #0]
|
|
80082f0: 681a ldr r2, [r3, #0]
|
|
80082f2: 68fb ldr r3, [r7, #12]
|
|
80082f4: 681b ldr r3, [r3, #0]
|
|
80082f6: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
80082fa: 601a str r2, [r3, #0]
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
80082fc: e00f b.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
}
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
|
|
80082fe: 68bb ldr r3, [r7, #8]
|
|
8008300: 095b lsrs r3, r3, #5
|
|
8008302: f003 0301 and.w r3, r3, #1
|
|
8008306: 2b00 cmp r3, #0
|
|
8008308: d009 beq.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
|
|
800830a: 687b ldr r3, [r7, #4]
|
|
800830c: 095b lsrs r3, r3, #5
|
|
800830e: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
|
|
8008312: 2b00 cmp r3, #0
|
|
8008314: d003 beq.n 800831e <I2C_Mem_ISR_DMA+0x246>
|
|
{
|
|
/* Call I2C Master complete process */
|
|
I2C_ITMasterCplt(hi2c, ITFlags);
|
|
8008316: 68b9 ldr r1, [r7, #8]
|
|
8008318: 68f8 ldr r0, [r7, #12]
|
|
800831a: f000 fa0d bl 8008738 <I2C_ITMasterCplt>
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800831e: 68fb ldr r3, [r7, #12]
|
|
8008320: 2200 movs r2, #0
|
|
8008322: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8008326: 2300 movs r3, #0
|
|
}
|
|
8008328: 4618 mov r0, r3
|
|
800832a: 3718 adds r7, #24
|
|
800832c: 46bd mov sp, r7
|
|
800832e: bd80 pop {r7, pc}
|
|
8008330: 80002000 .word 0x80002000
|
|
8008334: 80002400 .word 0x80002400
|
|
|
|
08008338 <I2C_Slave_ISR_DMA>:
|
|
* @param ITSources Interrupt sources enabled.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
|
|
uint32_t ITSources)
|
|
{
|
|
8008338: b580 push {r7, lr}
|
|
800833a: b088 sub sp, #32
|
|
800833c: af00 add r7, sp, #0
|
|
800833e: 60f8 str r0, [r7, #12]
|
|
8008340: 60b9 str r1, [r7, #8]
|
|
8008342: 607a str r2, [r7, #4]
|
|
uint32_t tmpoptions = hi2c->XferOptions;
|
|
8008344: 68fb ldr r3, [r7, #12]
|
|
8008346: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008348: 61bb str r3, [r7, #24]
|
|
uint32_t treatdmanack = 0U;
|
|
800834a: 2300 movs r3, #0
|
|
800834c: 61fb str r3, [r7, #28]
|
|
HAL_I2C_StateTypeDef tmpstate;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hi2c);
|
|
800834e: 68fb ldr r3, [r7, #12]
|
|
8008350: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8008354: 2b01 cmp r3, #1
|
|
8008356: d101 bne.n 800835c <I2C_Slave_ISR_DMA+0x24>
|
|
8008358: 2302 movs r3, #2
|
|
800835a: e0ca b.n 80084f2 <I2C_Slave_ISR_DMA+0x1ba>
|
|
800835c: 68fb ldr r3, [r7, #12]
|
|
800835e: 2201 movs r2, #1
|
|
8008360: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Check if STOPF is set */
|
|
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
|
|
8008364: 68bb ldr r3, [r7, #8]
|
|
8008366: 095b lsrs r3, r3, #5
|
|
8008368: f003 0301 and.w r3, r3, #1
|
|
800836c: 2b00 cmp r3, #0
|
|
800836e: d00a beq.n 8008386 <I2C_Slave_ISR_DMA+0x4e>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
|
|
8008370: 687b ldr r3, [r7, #4]
|
|
8008372: 095b lsrs r3, r3, #5
|
|
8008374: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
|
|
8008378: 2b00 cmp r3, #0
|
|
800837a: d004 beq.n 8008386 <I2C_Slave_ISR_DMA+0x4e>
|
|
{
|
|
/* Call I2C Slave complete process */
|
|
I2C_ITSlaveCplt(hi2c, ITFlags);
|
|
800837c: 68b9 ldr r1, [r7, #8]
|
|
800837e: 68f8 ldr r0, [r7, #12]
|
|
8008380: f000 faa4 bl 80088cc <I2C_ITSlaveCplt>
|
|
8008384: e0b0 b.n 80084e8 <I2C_Slave_ISR_DMA+0x1b0>
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
|
8008386: 68bb ldr r3, [r7, #8]
|
|
8008388: 091b lsrs r3, r3, #4
|
|
800838a: f003 0301 and.w r3, r3, #1
|
|
800838e: 2b00 cmp r3, #0
|
|
8008390: f000 809a beq.w 80084c8 <I2C_Slave_ISR_DMA+0x190>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
|
8008394: 687b ldr r3, [r7, #4]
|
|
8008396: 091b lsrs r3, r3, #4
|
|
8008398: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
|
800839c: 2b00 cmp r3, #0
|
|
800839e: f000 8093 beq.w 80084c8 <I2C_Slave_ISR_DMA+0x190>
|
|
{
|
|
/* Check that I2C transfer finished */
|
|
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
|
/* Mean XferCount == 0 */
|
|
/* So clear Flag NACKF only */
|
|
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
|
|
80083a2: 687b ldr r3, [r7, #4]
|
|
80083a4: 0b9b lsrs r3, r3, #14
|
|
80083a6: f003 0301 and.w r3, r3, #1
|
|
80083aa: 2b00 cmp r3, #0
|
|
80083ac: d105 bne.n 80083ba <I2C_Slave_ISR_DMA+0x82>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
|
|
80083ae: 687b ldr r3, [r7, #4]
|
|
80083b0: 0bdb lsrs r3, r3, #15
|
|
80083b2: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
|
|
80083b6: 2b00 cmp r3, #0
|
|
80083b8: d07f beq.n 80084ba <I2C_Slave_ISR_DMA+0x182>
|
|
{
|
|
/* Split check of hdmarx, for MISRA compliance */
|
|
if (hi2c->hdmarx != NULL)
|
|
80083ba: 68fb ldr r3, [r7, #12]
|
|
80083bc: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80083be: 2b00 cmp r3, #0
|
|
80083c0: d00d beq.n 80083de <I2C_Slave_ISR_DMA+0xa6>
|
|
{
|
|
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
|
|
80083c2: 687b ldr r3, [r7, #4]
|
|
80083c4: 0bdb lsrs r3, r3, #15
|
|
80083c6: f003 0301 and.w r3, r3, #1
|
|
80083ca: 2b00 cmp r3, #0
|
|
80083cc: d007 beq.n 80083de <I2C_Slave_ISR_DMA+0xa6>
|
|
{
|
|
if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
|
|
80083ce: 68fb ldr r3, [r7, #12]
|
|
80083d0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80083d2: 681b ldr r3, [r3, #0]
|
|
80083d4: 685b ldr r3, [r3, #4]
|
|
80083d6: 2b00 cmp r3, #0
|
|
80083d8: d101 bne.n 80083de <I2C_Slave_ISR_DMA+0xa6>
|
|
{
|
|
treatdmanack = 1U;
|
|
80083da: 2301 movs r3, #1
|
|
80083dc: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Split check of hdmatx, for MISRA compliance */
|
|
if (hi2c->hdmatx != NULL)
|
|
80083de: 68fb ldr r3, [r7, #12]
|
|
80083e0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80083e2: 2b00 cmp r3, #0
|
|
80083e4: d00d beq.n 8008402 <I2C_Slave_ISR_DMA+0xca>
|
|
{
|
|
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
|
|
80083e6: 687b ldr r3, [r7, #4]
|
|
80083e8: 0b9b lsrs r3, r3, #14
|
|
80083ea: f003 0301 and.w r3, r3, #1
|
|
80083ee: 2b00 cmp r3, #0
|
|
80083f0: d007 beq.n 8008402 <I2C_Slave_ISR_DMA+0xca>
|
|
{
|
|
if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
|
|
80083f2: 68fb ldr r3, [r7, #12]
|
|
80083f4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80083f6: 681b ldr r3, [r3, #0]
|
|
80083f8: 685b ldr r3, [r3, #4]
|
|
80083fa: 2b00 cmp r3, #0
|
|
80083fc: d101 bne.n 8008402 <I2C_Slave_ISR_DMA+0xca>
|
|
{
|
|
treatdmanack = 1U;
|
|
80083fe: 2301 movs r3, #1
|
|
8008400: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
}
|
|
|
|
if (treatdmanack == 1U)
|
|
8008402: 69fb ldr r3, [r7, #28]
|
|
8008404: 2b01 cmp r3, #1
|
|
8008406: d128 bne.n 800845a <I2C_Slave_ISR_DMA+0x122>
|
|
{
|
|
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
|
8008408: 68fb ldr r3, [r7, #12]
|
|
800840a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800840e: b2db uxtb r3, r3
|
|
8008410: 2b28 cmp r3, #40 @ 0x28
|
|
8008412: d108 bne.n 8008426 <I2C_Slave_ISR_DMA+0xee>
|
|
8008414: 69bb ldr r3, [r7, #24]
|
|
8008416: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
800841a: d104 bne.n 8008426 <I2C_Slave_ISR_DMA+0xee>
|
|
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
|
|
Warning[Pa134]: left and right operands are identical */
|
|
{
|
|
/* Call I2C Listen complete process */
|
|
I2C_ITListenCplt(hi2c, ITFlags);
|
|
800841c: 68b9 ldr r1, [r7, #8]
|
|
800841e: 68f8 ldr r0, [r7, #12]
|
|
8008420: f000 fbbe bl 8008ba0 <I2C_ITListenCplt>
|
|
8008424: e048 b.n 80084b8 <I2C_Slave_ISR_DMA+0x180>
|
|
}
|
|
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
|
|
8008426: 68fb ldr r3, [r7, #12]
|
|
8008428: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800842c: b2db uxtb r3, r3
|
|
800842e: 2b29 cmp r3, #41 @ 0x29
|
|
8008430: d10e bne.n 8008450 <I2C_Slave_ISR_DMA+0x118>
|
|
8008432: 69bb ldr r3, [r7, #24]
|
|
8008434: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
8008438: d00a beq.n 8008450 <I2C_Slave_ISR_DMA+0x118>
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
800843a: 68fb ldr r3, [r7, #12]
|
|
800843c: 681b ldr r3, [r3, #0]
|
|
800843e: 2210 movs r2, #16
|
|
8008440: 61da str r2, [r3, #28]
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8008442: 68f8 ldr r0, [r7, #12]
|
|
8008444: f000 fd19 bl 8008e7a <I2C_Flush_TXDR>
|
|
|
|
/* Last Byte is Transmitted */
|
|
/* Call I2C Slave Sequential complete process */
|
|
I2C_ITSlaveSeqCplt(hi2c);
|
|
8008448: 68f8 ldr r0, [r7, #12]
|
|
800844a: f000 f917 bl 800867c <I2C_ITSlaveSeqCplt>
|
|
800844e: e033 b.n 80084b8 <I2C_Slave_ISR_DMA+0x180>
|
|
}
|
|
else
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8008450: 68fb ldr r3, [r7, #12]
|
|
8008452: 681b ldr r3, [r3, #0]
|
|
8008454: 2210 movs r2, #16
|
|
8008456: 61da str r2, [r3, #28]
|
|
if (treatdmanack == 1U)
|
|
8008458: e034 b.n 80084c4 <I2C_Slave_ISR_DMA+0x18c>
|
|
}
|
|
else
|
|
{
|
|
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
800845a: 68fb ldr r3, [r7, #12]
|
|
800845c: 681b ldr r3, [r3, #0]
|
|
800845e: 2210 movs r2, #16
|
|
8008460: 61da str r2, [r3, #28]
|
|
|
|
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8008462: 68fb ldr r3, [r7, #12]
|
|
8008464: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008466: f043 0204 orr.w r2, r3, #4
|
|
800846a: 68fb ldr r3, [r7, #12]
|
|
800846c: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
|
|
tmpstate = hi2c->State;
|
|
800846e: 68fb ldr r3, [r7, #12]
|
|
8008470: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008474: 75fb strb r3, [r7, #23]
|
|
|
|
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
|
|
8008476: 69bb ldr r3, [r7, #24]
|
|
8008478: 2b00 cmp r3, #0
|
|
800847a: d003 beq.n 8008484 <I2C_Slave_ISR_DMA+0x14c>
|
|
800847c: 69bb ldr r3, [r7, #24]
|
|
800847e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8008482: d11f bne.n 80084c4 <I2C_Slave_ISR_DMA+0x18c>
|
|
{
|
|
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
|
|
8008484: 7dfb ldrb r3, [r7, #23]
|
|
8008486: 2b21 cmp r3, #33 @ 0x21
|
|
8008488: d002 beq.n 8008490 <I2C_Slave_ISR_DMA+0x158>
|
|
800848a: 7dfb ldrb r3, [r7, #23]
|
|
800848c: 2b29 cmp r3, #41 @ 0x29
|
|
800848e: d103 bne.n 8008498 <I2C_Slave_ISR_DMA+0x160>
|
|
{
|
|
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
|
|
8008490: 68fb ldr r3, [r7, #12]
|
|
8008492: 2221 movs r2, #33 @ 0x21
|
|
8008494: 631a str r2, [r3, #48] @ 0x30
|
|
8008496: e008 b.n 80084aa <I2C_Slave_ISR_DMA+0x172>
|
|
}
|
|
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
|
|
8008498: 7dfb ldrb r3, [r7, #23]
|
|
800849a: 2b22 cmp r3, #34 @ 0x22
|
|
800849c: d002 beq.n 80084a4 <I2C_Slave_ISR_DMA+0x16c>
|
|
800849e: 7dfb ldrb r3, [r7, #23]
|
|
80084a0: 2b2a cmp r3, #42 @ 0x2a
|
|
80084a2: d102 bne.n 80084aa <I2C_Slave_ISR_DMA+0x172>
|
|
{
|
|
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
|
|
80084a4: 68fb ldr r3, [r7, #12]
|
|
80084a6: 2222 movs r2, #34 @ 0x22
|
|
80084a8: 631a str r2, [r3, #48] @ 0x30
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, hi2c->ErrorCode);
|
|
80084aa: 68fb ldr r3, [r7, #12]
|
|
80084ac: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80084ae: 4619 mov r1, r3
|
|
80084b0: 68f8 ldr r0, [r7, #12]
|
|
80084b2: f000 fbcb bl 8008c4c <I2C_ITError>
|
|
if (treatdmanack == 1U)
|
|
80084b6: e005 b.n 80084c4 <I2C_Slave_ISR_DMA+0x18c>
|
|
80084b8: e004 b.n 80084c4 <I2C_Slave_ISR_DMA+0x18c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Only Clear NACK Flag, no DMA treatment is pending */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
80084ba: 68fb ldr r3, [r7, #12]
|
|
80084bc: 681b ldr r3, [r3, #0]
|
|
80084be: 2210 movs r2, #16
|
|
80084c0: 61da str r2, [r3, #28]
|
|
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
|
|
80084c2: e011 b.n 80084e8 <I2C_Slave_ISR_DMA+0x1b0>
|
|
if (treatdmanack == 1U)
|
|
80084c4: bf00 nop
|
|
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
|
|
80084c6: e00f b.n 80084e8 <I2C_Slave_ISR_DMA+0x1b0>
|
|
}
|
|
}
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
|
|
80084c8: 68bb ldr r3, [r7, #8]
|
|
80084ca: 08db lsrs r3, r3, #3
|
|
80084cc: f003 0301 and.w r3, r3, #1
|
|
80084d0: 2b00 cmp r3, #0
|
|
80084d2: d009 beq.n 80084e8 <I2C_Slave_ISR_DMA+0x1b0>
|
|
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
|
|
80084d4: 687b ldr r3, [r7, #4]
|
|
80084d6: 08db lsrs r3, r3, #3
|
|
80084d8: f003 0301 and.w r3, r3, #1
|
|
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
|
|
80084dc: 2b00 cmp r3, #0
|
|
80084de: d003 beq.n 80084e8 <I2C_Slave_ISR_DMA+0x1b0>
|
|
{
|
|
I2C_ITAddrCplt(hi2c, ITFlags);
|
|
80084e0: 68b9 ldr r1, [r7, #8]
|
|
80084e2: 68f8 ldr r0, [r7, #12]
|
|
80084e4: f000 f809 bl 80084fa <I2C_ITAddrCplt>
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80084e8: 68fb ldr r3, [r7, #12]
|
|
80084ea: 2200 movs r2, #0
|
|
80084ec: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
80084f0: 2300 movs r3, #0
|
|
}
|
|
80084f2: 4618 mov r0, r3
|
|
80084f4: 3720 adds r7, #32
|
|
80084f6: 46bd mov sp, r7
|
|
80084f8: bd80 pop {r7, pc}
|
|
|
|
080084fa <I2C_ITAddrCplt>:
|
|
* @param hi2c I2C handle.
|
|
* @param ITFlags Interrupt flags to handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|
{
|
|
80084fa: b580 push {r7, lr}
|
|
80084fc: b084 sub sp, #16
|
|
80084fe: af00 add r7, sp, #0
|
|
8008500: 6078 str r0, [r7, #4]
|
|
8008502: 6039 str r1, [r7, #0]
|
|
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(ITFlags);
|
|
|
|
/* In case of Listen state, need to inform upper layer of address match code event */
|
|
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
|
|
8008504: 687b ldr r3, [r7, #4]
|
|
8008506: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800850a: b2db uxtb r3, r3
|
|
800850c: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
8008510: 2b28 cmp r3, #40 @ 0x28
|
|
8008512: d16a bne.n 80085ea <I2C_ITAddrCplt+0xf0>
|
|
{
|
|
transferdirection = I2C_GET_DIR(hi2c);
|
|
8008514: 687b ldr r3, [r7, #4]
|
|
8008516: 681b ldr r3, [r3, #0]
|
|
8008518: 699b ldr r3, [r3, #24]
|
|
800851a: 0c1b lsrs r3, r3, #16
|
|
800851c: b2db uxtb r3, r3
|
|
800851e: f003 0301 and.w r3, r3, #1
|
|
8008522: 73fb strb r3, [r7, #15]
|
|
slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
|
|
8008524: 687b ldr r3, [r7, #4]
|
|
8008526: 681b ldr r3, [r3, #0]
|
|
8008528: 699b ldr r3, [r3, #24]
|
|
800852a: 0c1b lsrs r3, r3, #16
|
|
800852c: b29b uxth r3, r3
|
|
800852e: f003 03fe and.w r3, r3, #254 @ 0xfe
|
|
8008532: 81bb strh r3, [r7, #12]
|
|
ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
|
|
8008534: 687b ldr r3, [r7, #4]
|
|
8008536: 681b ldr r3, [r3, #0]
|
|
8008538: 689b ldr r3, [r3, #8]
|
|
800853a: b29b uxth r3, r3
|
|
800853c: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8008540: 817b strh r3, [r7, #10]
|
|
ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
|
|
8008542: 687b ldr r3, [r7, #4]
|
|
8008544: 681b ldr r3, [r3, #0]
|
|
8008546: 68db ldr r3, [r3, #12]
|
|
8008548: b29b uxth r3, r3
|
|
800854a: f003 03fe and.w r3, r3, #254 @ 0xfe
|
|
800854e: 813b strh r3, [r7, #8]
|
|
|
|
/* If 10bits addressing mode is selected */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
8008550: 687b ldr r3, [r7, #4]
|
|
8008552: 68db ldr r3, [r3, #12]
|
|
8008554: 2b02 cmp r3, #2
|
|
8008556: d138 bne.n 80085ca <I2C_ITAddrCplt+0xd0>
|
|
{
|
|
if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
|
|
8008558: 897b ldrh r3, [r7, #10]
|
|
800855a: 09db lsrs r3, r3, #7
|
|
800855c: b29a uxth r2, r3
|
|
800855e: 89bb ldrh r3, [r7, #12]
|
|
8008560: 4053 eors r3, r2
|
|
8008562: b29b uxth r3, r3
|
|
8008564: f003 0306 and.w r3, r3, #6
|
|
8008568: 2b00 cmp r3, #0
|
|
800856a: d11c bne.n 80085a6 <I2C_ITAddrCplt+0xac>
|
|
{
|
|
slaveaddrcode = ownadd1code;
|
|
800856c: 897b ldrh r3, [r7, #10]
|
|
800856e: 81bb strh r3, [r7, #12]
|
|
hi2c->AddrEventCount++;
|
|
8008570: 687b ldr r3, [r7, #4]
|
|
8008572: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8008574: 1c5a adds r2, r3, #1
|
|
8008576: 687b ldr r3, [r7, #4]
|
|
8008578: 649a str r2, [r3, #72] @ 0x48
|
|
if (hi2c->AddrEventCount == 2U)
|
|
800857a: 687b ldr r3, [r7, #4]
|
|
800857c: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800857e: 2b02 cmp r3, #2
|
|
8008580: d13b bne.n 80085fa <I2C_ITAddrCplt+0x100>
|
|
{
|
|
/* Reset Address Event counter */
|
|
hi2c->AddrEventCount = 0U;
|
|
8008582: 687b ldr r3, [r7, #4]
|
|
8008584: 2200 movs r2, #0
|
|
8008586: 649a str r2, [r3, #72] @ 0x48
|
|
|
|
/* Clear ADDR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
|
|
8008588: 687b ldr r3, [r7, #4]
|
|
800858a: 681b ldr r3, [r3, #0]
|
|
800858c: 2208 movs r2, #8
|
|
800858e: 61da str r2, [r3, #28]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008590: 687b ldr r3, [r7, #4]
|
|
8008592: 2200 movs r2, #0
|
|
8008594: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Call Slave Addr callback */
|
|
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
|
|
#else
|
|
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
|
|
8008598: 89ba ldrh r2, [r7, #12]
|
|
800859a: 7bfb ldrb r3, [r7, #15]
|
|
800859c: 4619 mov r1, r3
|
|
800859e: 6878 ldr r0, [r7, #4]
|
|
80085a0: f7ff fb75 bl 8007c8e <HAL_I2C_AddrCallback>
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
}
|
|
}
|
|
80085a4: e029 b.n 80085fa <I2C_ITAddrCplt+0x100>
|
|
slaveaddrcode = ownadd2code;
|
|
80085a6: 893b ldrh r3, [r7, #8]
|
|
80085a8: 81bb strh r3, [r7, #12]
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
|
|
80085aa: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
80085ae: 6878 ldr r0, [r7, #4]
|
|
80085b0: f000 fe08 bl 80091c4 <I2C_Disable_IRQ>
|
|
__HAL_UNLOCK(hi2c);
|
|
80085b4: 687b ldr r3, [r7, #4]
|
|
80085b6: 2200 movs r2, #0
|
|
80085b8: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
|
|
80085bc: 89ba ldrh r2, [r7, #12]
|
|
80085be: 7bfb ldrb r3, [r7, #15]
|
|
80085c0: 4619 mov r1, r3
|
|
80085c2: 6878 ldr r0, [r7, #4]
|
|
80085c4: f7ff fb63 bl 8007c8e <HAL_I2C_AddrCallback>
|
|
}
|
|
80085c8: e017 b.n 80085fa <I2C_ITAddrCplt+0x100>
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
|
|
80085ca: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
80085ce: 6878 ldr r0, [r7, #4]
|
|
80085d0: f000 fdf8 bl 80091c4 <I2C_Disable_IRQ>
|
|
__HAL_UNLOCK(hi2c);
|
|
80085d4: 687b ldr r3, [r7, #4]
|
|
80085d6: 2200 movs r2, #0
|
|
80085d8: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
|
|
80085dc: 89ba ldrh r2, [r7, #12]
|
|
80085de: 7bfb ldrb r3, [r7, #15]
|
|
80085e0: 4619 mov r1, r3
|
|
80085e2: 6878 ldr r0, [r7, #4]
|
|
80085e4: f7ff fb53 bl 8007c8e <HAL_I2C_AddrCallback>
|
|
}
|
|
80085e8: e007 b.n 80085fa <I2C_ITAddrCplt+0x100>
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
|
|
80085ea: 687b ldr r3, [r7, #4]
|
|
80085ec: 681b ldr r3, [r3, #0]
|
|
80085ee: 2208 movs r2, #8
|
|
80085f0: 61da str r2, [r3, #28]
|
|
__HAL_UNLOCK(hi2c);
|
|
80085f2: 687b ldr r3, [r7, #4]
|
|
80085f4: 2200 movs r2, #0
|
|
80085f6: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
}
|
|
80085fa: bf00 nop
|
|
80085fc: 3710 adds r7, #16
|
|
80085fe: 46bd mov sp, r7
|
|
8008600: bd80 pop {r7, pc}
|
|
|
|
08008602 <I2C_ITMasterSeqCplt>:
|
|
* @brief I2C Master sequential complete process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8008602: b580 push {r7, lr}
|
|
8008604: b082 sub sp, #8
|
|
8008606: af00 add r7, sp, #0
|
|
8008608: 6078 str r0, [r7, #4]
|
|
/* Reset I2C handle mode */
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800860a: 687b ldr r3, [r7, #4]
|
|
800860c: 2200 movs r2, #0
|
|
800860e: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* No Generate Stop, to permit restart mode */
|
|
/* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
|
|
8008612: 687b ldr r3, [r7, #4]
|
|
8008614: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008618: b2db uxtb r3, r3
|
|
800861a: 2b21 cmp r3, #33 @ 0x21
|
|
800861c: d115 bne.n 800864a <I2C_ITMasterSeqCplt+0x48>
|
|
{
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800861e: 687b ldr r3, [r7, #4]
|
|
8008620: 2220 movs r2, #32
|
|
8008622: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
|
|
8008626: 687b ldr r3, [r7, #4]
|
|
8008628: 2211 movs r2, #17
|
|
800862a: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->XferISR = NULL;
|
|
800862c: 687b ldr r3, [r7, #4]
|
|
800862e: 2200 movs r2, #0
|
|
8008630: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Disable Interrupts */
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
|
8008632: 2101 movs r1, #1
|
|
8008634: 6878 ldr r0, [r7, #4]
|
|
8008636: f000 fdc5 bl 80091c4 <I2C_Disable_IRQ>
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800863a: 687b ldr r3, [r7, #4]
|
|
800863c: 2200 movs r2, #0
|
|
800863e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
hi2c->MasterTxCpltCallback(hi2c);
|
|
#else
|
|
HAL_I2C_MasterTxCpltCallback(hi2c);
|
|
8008642: 6878 ldr r0, [r7, #4]
|
|
8008644: f7ff fafb bl 8007c3e <HAL_I2C_MasterTxCpltCallback>
|
|
hi2c->MasterRxCpltCallback(hi2c);
|
|
#else
|
|
HAL_I2C_MasterRxCpltCallback(hi2c);
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8008648: e014 b.n 8008674 <I2C_ITMasterSeqCplt+0x72>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800864a: 687b ldr r3, [r7, #4]
|
|
800864c: 2220 movs r2, #32
|
|
800864e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
|
|
8008652: 687b ldr r3, [r7, #4]
|
|
8008654: 2212 movs r2, #18
|
|
8008656: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->XferISR = NULL;
|
|
8008658: 687b ldr r3, [r7, #4]
|
|
800865a: 2200 movs r2, #0
|
|
800865c: 635a str r2, [r3, #52] @ 0x34
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
|
|
800865e: 2102 movs r1, #2
|
|
8008660: 6878 ldr r0, [r7, #4]
|
|
8008662: f000 fdaf bl 80091c4 <I2C_Disable_IRQ>
|
|
__HAL_UNLOCK(hi2c);
|
|
8008666: 687b ldr r3, [r7, #4]
|
|
8008668: 2200 movs r2, #0
|
|
800866a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_MasterRxCpltCallback(hi2c);
|
|
800866e: 6878 ldr r0, [r7, #4]
|
|
8008670: f7ff faef bl 8007c52 <HAL_I2C_MasterRxCpltCallback>
|
|
}
|
|
8008674: bf00 nop
|
|
8008676: 3708 adds r7, #8
|
|
8008678: 46bd mov sp, r7
|
|
800867a: bd80 pop {r7, pc}
|
|
|
|
0800867c <I2C_ITSlaveSeqCplt>:
|
|
* @brief I2C Slave sequential complete process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
800867c: b580 push {r7, lr}
|
|
800867e: b084 sub sp, #16
|
|
8008680: af00 add r7, sp, #0
|
|
8008682: 6078 str r0, [r7, #4]
|
|
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
|
|
8008684: 687b ldr r3, [r7, #4]
|
|
8008686: 681b ldr r3, [r3, #0]
|
|
8008688: 681b ldr r3, [r3, #0]
|
|
800868a: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2C handle mode */
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800868c: 687b ldr r3, [r7, #4]
|
|
800868e: 2200 movs r2, #0
|
|
8008690: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
#if defined(HAL_DMA_MODULE_ENABLED)
|
|
/* If a DMA is ongoing, Update handle size context */
|
|
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
|
|
8008694: 68fb ldr r3, [r7, #12]
|
|
8008696: 0b9b lsrs r3, r3, #14
|
|
8008698: f003 0301 and.w r3, r3, #1
|
|
800869c: 2b00 cmp r3, #0
|
|
800869e: d008 beq.n 80086b2 <I2C_ITSlaveSeqCplt+0x36>
|
|
{
|
|
/* Disable DMA Request */
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
|
|
80086a0: 687b ldr r3, [r7, #4]
|
|
80086a2: 681b ldr r3, [r3, #0]
|
|
80086a4: 681a ldr r2, [r3, #0]
|
|
80086a6: 687b ldr r3, [r7, #4]
|
|
80086a8: 681b ldr r3, [r3, #0]
|
|
80086aa: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
80086ae: 601a str r2, [r3, #0]
|
|
80086b0: e00d b.n 80086ce <I2C_ITSlaveSeqCplt+0x52>
|
|
}
|
|
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
|
|
80086b2: 68fb ldr r3, [r7, #12]
|
|
80086b4: 0bdb lsrs r3, r3, #15
|
|
80086b6: f003 0301 and.w r3, r3, #1
|
|
80086ba: 2b00 cmp r3, #0
|
|
80086bc: d007 beq.n 80086ce <I2C_ITSlaveSeqCplt+0x52>
|
|
{
|
|
/* Disable DMA Request */
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
|
|
80086be: 687b ldr r3, [r7, #4]
|
|
80086c0: 681b ldr r3, [r3, #0]
|
|
80086c2: 681a ldr r2, [r3, #0]
|
|
80086c4: 687b ldr r3, [r7, #4]
|
|
80086c6: 681b ldr r3, [r3, #0]
|
|
80086c8: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
80086cc: 601a str r2, [r3, #0]
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
|
|
80086ce: 687b ldr r3, [r7, #4]
|
|
80086d0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80086d4: b2db uxtb r3, r3
|
|
80086d6: 2b29 cmp r3, #41 @ 0x29
|
|
80086d8: d112 bne.n 8008700 <I2C_ITSlaveSeqCplt+0x84>
|
|
{
|
|
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
|
|
hi2c->State = HAL_I2C_STATE_LISTEN;
|
|
80086da: 687b ldr r3, [r7, #4]
|
|
80086dc: 2228 movs r2, #40 @ 0x28
|
|
80086de: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
|
|
80086e2: 687b ldr r3, [r7, #4]
|
|
80086e4: 2221 movs r2, #33 @ 0x21
|
|
80086e6: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Disable Interrupts */
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
|
80086e8: 2101 movs r1, #1
|
|
80086ea: 6878 ldr r0, [r7, #4]
|
|
80086ec: f000 fd6a bl 80091c4 <I2C_Disable_IRQ>
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80086f0: 687b ldr r3, [r7, #4]
|
|
80086f2: 2200 movs r2, #0
|
|
80086f4: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
hi2c->SlaveTxCpltCallback(hi2c);
|
|
#else
|
|
HAL_I2C_SlaveTxCpltCallback(hi2c);
|
|
80086f8: 6878 ldr r0, [r7, #4]
|
|
80086fa: f7ff fab4 bl 8007c66 <HAL_I2C_SlaveTxCpltCallback>
|
|
}
|
|
else
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
}
|
|
80086fe: e017 b.n 8008730 <I2C_ITSlaveSeqCplt+0xb4>
|
|
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
|
|
8008700: 687b ldr r3, [r7, #4]
|
|
8008702: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008706: b2db uxtb r3, r3
|
|
8008708: 2b2a cmp r3, #42 @ 0x2a
|
|
800870a: d111 bne.n 8008730 <I2C_ITSlaveSeqCplt+0xb4>
|
|
hi2c->State = HAL_I2C_STATE_LISTEN;
|
|
800870c: 687b ldr r3, [r7, #4]
|
|
800870e: 2228 movs r2, #40 @ 0x28
|
|
8008710: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
|
|
8008714: 687b ldr r3, [r7, #4]
|
|
8008716: 2222 movs r2, #34 @ 0x22
|
|
8008718: 631a str r2, [r3, #48] @ 0x30
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
|
|
800871a: 2102 movs r1, #2
|
|
800871c: 6878 ldr r0, [r7, #4]
|
|
800871e: f000 fd51 bl 80091c4 <I2C_Disable_IRQ>
|
|
__HAL_UNLOCK(hi2c);
|
|
8008722: 687b ldr r3, [r7, #4]
|
|
8008724: 2200 movs r2, #0
|
|
8008726: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_SlaveRxCpltCallback(hi2c);
|
|
800872a: 6878 ldr r0, [r7, #4]
|
|
800872c: f7ff faa5 bl 8007c7a <HAL_I2C_SlaveRxCpltCallback>
|
|
}
|
|
8008730: bf00 nop
|
|
8008732: 3710 adds r7, #16
|
|
8008734: 46bd mov sp, r7
|
|
8008736: bd80 pop {r7, pc}
|
|
|
|
08008738 <I2C_ITMasterCplt>:
|
|
* @param hi2c I2C handle.
|
|
* @param ITFlags Interrupt flags to handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|
{
|
|
8008738: b580 push {r7, lr}
|
|
800873a: b086 sub sp, #24
|
|
800873c: af00 add r7, sp, #0
|
|
800873e: 6078 str r0, [r7, #4]
|
|
8008740: 6039 str r1, [r7, #0]
|
|
uint32_t tmperror;
|
|
uint32_t tmpITFlags = ITFlags;
|
|
8008742: 683b ldr r3, [r7, #0]
|
|
8008744: 617b str r3, [r7, #20]
|
|
__IO uint32_t tmpreg;
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8008746: 687b ldr r3, [r7, #4]
|
|
8008748: 681b ldr r3, [r3, #0]
|
|
800874a: 2220 movs r2, #32
|
|
800874c: 61da str r2, [r3, #28]
|
|
|
|
/* Disable Interrupts and Store Previous state */
|
|
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
|
|
800874e: 687b ldr r3, [r7, #4]
|
|
8008750: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008754: b2db uxtb r3, r3
|
|
8008756: 2b21 cmp r3, #33 @ 0x21
|
|
8008758: d107 bne.n 800876a <I2C_ITMasterCplt+0x32>
|
|
{
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
|
800875a: 2101 movs r1, #1
|
|
800875c: 6878 ldr r0, [r7, #4]
|
|
800875e: f000 fd31 bl 80091c4 <I2C_Disable_IRQ>
|
|
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
|
|
8008762: 687b ldr r3, [r7, #4]
|
|
8008764: 2211 movs r2, #17
|
|
8008766: 631a str r2, [r3, #48] @ 0x30
|
|
8008768: e00c b.n 8008784 <I2C_ITMasterCplt+0x4c>
|
|
}
|
|
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
800876a: 687b ldr r3, [r7, #4]
|
|
800876c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008770: b2db uxtb r3, r3
|
|
8008772: 2b22 cmp r3, #34 @ 0x22
|
|
8008774: d106 bne.n 8008784 <I2C_ITMasterCplt+0x4c>
|
|
{
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
|
|
8008776: 2102 movs r1, #2
|
|
8008778: 6878 ldr r0, [r7, #4]
|
|
800877a: f000 fd23 bl 80091c4 <I2C_Disable_IRQ>
|
|
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
|
|
800877e: 687b ldr r3, [r7, #4]
|
|
8008780: 2212 movs r2, #18
|
|
8008782: 631a str r2, [r3, #48] @ 0x30
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8008784: 687b ldr r3, [r7, #4]
|
|
8008786: 681b ldr r3, [r3, #0]
|
|
8008788: 6859 ldr r1, [r3, #4]
|
|
800878a: 687b ldr r3, [r7, #4]
|
|
800878c: 681a ldr r2, [r3, #0]
|
|
800878e: 4b4d ldr r3, [pc, #308] @ (80088c4 <I2C_ITMasterCplt+0x18c>)
|
|
8008790: 400b ands r3, r1
|
|
8008792: 6053 str r3, [r2, #4]
|
|
|
|
/* Reset handle parameters */
|
|
hi2c->XferISR = NULL;
|
|
8008794: 687b ldr r3, [r7, #4]
|
|
8008796: 2200 movs r2, #0
|
|
8008798: 635a str r2, [r3, #52] @ 0x34
|
|
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
|
800879a: 687b ldr r3, [r7, #4]
|
|
800879c: 4a4a ldr r2, [pc, #296] @ (80088c8 <I2C_ITMasterCplt+0x190>)
|
|
800879e: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
|
|
80087a0: 697b ldr r3, [r7, #20]
|
|
80087a2: 091b lsrs r3, r3, #4
|
|
80087a4: f003 0301 and.w r3, r3, #1
|
|
80087a8: 2b00 cmp r3, #0
|
|
80087aa: d009 beq.n 80087c0 <I2C_ITMasterCplt+0x88>
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
80087ac: 687b ldr r3, [r7, #4]
|
|
80087ae: 681b ldr r3, [r3, #0]
|
|
80087b0: 2210 movs r2, #16
|
|
80087b2: 61da str r2, [r3, #28]
|
|
|
|
/* Set acknowledge error code */
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
80087b4: 687b ldr r3, [r7, #4]
|
|
80087b6: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80087b8: f043 0204 orr.w r2, r3, #4
|
|
80087bc: 687b ldr r3, [r7, #4]
|
|
80087be: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Fetch Last receive data if any */
|
|
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
|
|
80087c0: 687b ldr r3, [r7, #4]
|
|
80087c2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80087c6: b2db uxtb r3, r3
|
|
80087c8: 2b60 cmp r3, #96 @ 0x60
|
|
80087ca: d10b bne.n 80087e4 <I2C_ITMasterCplt+0xac>
|
|
80087cc: 697b ldr r3, [r7, #20]
|
|
80087ce: 089b lsrs r3, r3, #2
|
|
80087d0: f003 0301 and.w r3, r3, #1
|
|
80087d4: 2b00 cmp r3, #0
|
|
80087d6: d005 beq.n 80087e4 <I2C_ITMasterCplt+0xac>
|
|
{
|
|
/* Read data from RXDR */
|
|
tmpreg = (uint8_t)hi2c->Instance->RXDR;
|
|
80087d8: 687b ldr r3, [r7, #4]
|
|
80087da: 681b ldr r3, [r3, #0]
|
|
80087dc: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80087de: b2db uxtb r3, r3
|
|
80087e0: 60fb str r3, [r7, #12]
|
|
UNUSED(tmpreg);
|
|
80087e2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
80087e4: 6878 ldr r0, [r7, #4]
|
|
80087e6: f000 fb48 bl 8008e7a <I2C_Flush_TXDR>
|
|
|
|
/* Store current volatile hi2c->ErrorCode, misra rule */
|
|
tmperror = hi2c->ErrorCode;
|
|
80087ea: 687b ldr r3, [r7, #4]
|
|
80087ec: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80087ee: 613b str r3, [r7, #16]
|
|
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
|
|
80087f0: 687b ldr r3, [r7, #4]
|
|
80087f2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80087f6: b2db uxtb r3, r3
|
|
80087f8: 2b60 cmp r3, #96 @ 0x60
|
|
80087fa: d002 beq.n 8008802 <I2C_ITMasterCplt+0xca>
|
|
80087fc: 693b ldr r3, [r7, #16]
|
|
80087fe: 2b00 cmp r3, #0
|
|
8008800: d006 beq.n 8008810 <I2C_ITMasterCplt+0xd8>
|
|
{
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, hi2c->ErrorCode);
|
|
8008802: 687b ldr r3, [r7, #4]
|
|
8008804: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008806: 4619 mov r1, r3
|
|
8008808: 6878 ldr r0, [r7, #4]
|
|
800880a: f000 fa1f bl 8008c4c <I2C_ITError>
|
|
}
|
|
else
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
}
|
|
800880e: e054 b.n 80088ba <I2C_ITMasterCplt+0x182>
|
|
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
|
|
8008810: 687b ldr r3, [r7, #4]
|
|
8008812: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008816: b2db uxtb r3, r3
|
|
8008818: 2b21 cmp r3, #33 @ 0x21
|
|
800881a: d124 bne.n 8008866 <I2C_ITMasterCplt+0x12e>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800881c: 687b ldr r3, [r7, #4]
|
|
800881e: 2220 movs r2, #32
|
|
8008820: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8008824: 687b ldr r3, [r7, #4]
|
|
8008826: 2200 movs r2, #0
|
|
8008828: 631a str r2, [r3, #48] @ 0x30
|
|
if (hi2c->Mode == HAL_I2C_MODE_MEM)
|
|
800882a: 687b ldr r3, [r7, #4]
|
|
800882c: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8008830: b2db uxtb r3, r3
|
|
8008832: 2b40 cmp r3, #64 @ 0x40
|
|
8008834: d10b bne.n 800884e <I2C_ITMasterCplt+0x116>
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008836: 687b ldr r3, [r7, #4]
|
|
8008838: 2200 movs r2, #0
|
|
800883a: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
__HAL_UNLOCK(hi2c);
|
|
800883e: 687b ldr r3, [r7, #4]
|
|
8008840: 2200 movs r2, #0
|
|
8008842: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_MemTxCpltCallback(hi2c);
|
|
8008846: 6878 ldr r0, [r7, #4]
|
|
8008848: f7fc fdf8 bl 800543c <HAL_I2C_MemTxCpltCallback>
|
|
}
|
|
800884c: e035 b.n 80088ba <I2C_ITMasterCplt+0x182>
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800884e: 687b ldr r3, [r7, #4]
|
|
8008850: 2200 movs r2, #0
|
|
8008852: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
__HAL_UNLOCK(hi2c);
|
|
8008856: 687b ldr r3, [r7, #4]
|
|
8008858: 2200 movs r2, #0
|
|
800885a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_MasterTxCpltCallback(hi2c);
|
|
800885e: 6878 ldr r0, [r7, #4]
|
|
8008860: f7ff f9ed bl 8007c3e <HAL_I2C_MasterTxCpltCallback>
|
|
}
|
|
8008864: e029 b.n 80088ba <I2C_ITMasterCplt+0x182>
|
|
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
8008866: 687b ldr r3, [r7, #4]
|
|
8008868: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800886c: b2db uxtb r3, r3
|
|
800886e: 2b22 cmp r3, #34 @ 0x22
|
|
8008870: d123 bne.n 80088ba <I2C_ITMasterCplt+0x182>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008872: 687b ldr r3, [r7, #4]
|
|
8008874: 2220 movs r2, #32
|
|
8008876: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
800887a: 687b ldr r3, [r7, #4]
|
|
800887c: 2200 movs r2, #0
|
|
800887e: 631a str r2, [r3, #48] @ 0x30
|
|
if (hi2c->Mode == HAL_I2C_MODE_MEM)
|
|
8008880: 687b ldr r3, [r7, #4]
|
|
8008882: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8008886: b2db uxtb r3, r3
|
|
8008888: 2b40 cmp r3, #64 @ 0x40
|
|
800888a: d10b bne.n 80088a4 <I2C_ITMasterCplt+0x16c>
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800888c: 687b ldr r3, [r7, #4]
|
|
800888e: 2200 movs r2, #0
|
|
8008890: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
__HAL_UNLOCK(hi2c);
|
|
8008894: 687b ldr r3, [r7, #4]
|
|
8008896: 2200 movs r2, #0
|
|
8008898: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_MemRxCpltCallback(hi2c);
|
|
800889c: 6878 ldr r0, [r7, #4]
|
|
800889e: f7fc fda1 bl 80053e4 <HAL_I2C_MemRxCpltCallback>
|
|
}
|
|
80088a2: e00a b.n 80088ba <I2C_ITMasterCplt+0x182>
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80088a4: 687b ldr r3, [r7, #4]
|
|
80088a6: 2200 movs r2, #0
|
|
80088a8: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
__HAL_UNLOCK(hi2c);
|
|
80088ac: 687b ldr r3, [r7, #4]
|
|
80088ae: 2200 movs r2, #0
|
|
80088b0: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_MasterRxCpltCallback(hi2c);
|
|
80088b4: 6878 ldr r0, [r7, #4]
|
|
80088b6: f7ff f9cc bl 8007c52 <HAL_I2C_MasterRxCpltCallback>
|
|
}
|
|
80088ba: bf00 nop
|
|
80088bc: 3718 adds r7, #24
|
|
80088be: 46bd mov sp, r7
|
|
80088c0: bd80 pop {r7, pc}
|
|
80088c2: bf00 nop
|
|
80088c4: fe00e800 .word 0xfe00e800
|
|
80088c8: ffff0000 .word 0xffff0000
|
|
|
|
080088cc <I2C_ITSlaveCplt>:
|
|
* @param hi2c I2C handle.
|
|
* @param ITFlags Interrupt flags to handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|
{
|
|
80088cc: b580 push {r7, lr}
|
|
80088ce: b086 sub sp, #24
|
|
80088d0: af00 add r7, sp, #0
|
|
80088d2: 6078 str r0, [r7, #4]
|
|
80088d4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
|
|
80088d6: 687b ldr r3, [r7, #4]
|
|
80088d8: 681b ldr r3, [r3, #0]
|
|
80088da: 681b ldr r3, [r3, #0]
|
|
80088dc: 613b str r3, [r7, #16]
|
|
uint32_t tmpITFlags = ITFlags;
|
|
80088de: 683b ldr r3, [r7, #0]
|
|
80088e0: 617b str r3, [r7, #20]
|
|
uint32_t tmpoptions = hi2c->XferOptions;
|
|
80088e2: 687b ldr r3, [r7, #4]
|
|
80088e4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80088e6: 60fb str r3, [r7, #12]
|
|
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
|
80088e8: 687b ldr r3, [r7, #4]
|
|
80088ea: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80088ee: 72fb strb r3, [r7, #11]
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
80088f0: 687b ldr r3, [r7, #4]
|
|
80088f2: 681b ldr r3, [r3, #0]
|
|
80088f4: 2220 movs r2, #32
|
|
80088f6: 61da str r2, [r3, #28]
|
|
|
|
/* Disable Interrupts and Store Previous state */
|
|
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
|
|
80088f8: 7afb ldrb r3, [r7, #11]
|
|
80088fa: 2b21 cmp r3, #33 @ 0x21
|
|
80088fc: d002 beq.n 8008904 <I2C_ITSlaveCplt+0x38>
|
|
80088fe: 7afb ldrb r3, [r7, #11]
|
|
8008900: 2b29 cmp r3, #41 @ 0x29
|
|
8008902: d108 bne.n 8008916 <I2C_ITSlaveCplt+0x4a>
|
|
{
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
|
|
8008904: f248 0101 movw r1, #32769 @ 0x8001
|
|
8008908: 6878 ldr r0, [r7, #4]
|
|
800890a: f000 fc5b bl 80091c4 <I2C_Disable_IRQ>
|
|
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
|
|
800890e: 687b ldr r3, [r7, #4]
|
|
8008910: 2221 movs r2, #33 @ 0x21
|
|
8008912: 631a str r2, [r3, #48] @ 0x30
|
|
8008914: e019 b.n 800894a <I2C_ITSlaveCplt+0x7e>
|
|
}
|
|
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
|
|
8008916: 7afb ldrb r3, [r7, #11]
|
|
8008918: 2b22 cmp r3, #34 @ 0x22
|
|
800891a: d002 beq.n 8008922 <I2C_ITSlaveCplt+0x56>
|
|
800891c: 7afb ldrb r3, [r7, #11]
|
|
800891e: 2b2a cmp r3, #42 @ 0x2a
|
|
8008920: d108 bne.n 8008934 <I2C_ITSlaveCplt+0x68>
|
|
{
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
|
|
8008922: f248 0102 movw r1, #32770 @ 0x8002
|
|
8008926: 6878 ldr r0, [r7, #4]
|
|
8008928: f000 fc4c bl 80091c4 <I2C_Disable_IRQ>
|
|
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
|
|
800892c: 687b ldr r3, [r7, #4]
|
|
800892e: 2222 movs r2, #34 @ 0x22
|
|
8008930: 631a str r2, [r3, #48] @ 0x30
|
|
8008932: e00a b.n 800894a <I2C_ITSlaveCplt+0x7e>
|
|
}
|
|
else if (tmpstate == HAL_I2C_STATE_LISTEN)
|
|
8008934: 7afb ldrb r3, [r7, #11]
|
|
8008936: 2b28 cmp r3, #40 @ 0x28
|
|
8008938: d107 bne.n 800894a <I2C_ITSlaveCplt+0x7e>
|
|
{
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
|
|
800893a: f248 0103 movw r1, #32771 @ 0x8003
|
|
800893e: 6878 ldr r0, [r7, #4]
|
|
8008940: f000 fc40 bl 80091c4 <I2C_Disable_IRQ>
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8008944: 687b ldr r3, [r7, #4]
|
|
8008946: 2200 movs r2, #0
|
|
8008948: 631a str r2, [r3, #48] @ 0x30
|
|
{
|
|
/* Do nothing */
|
|
}
|
|
|
|
/* Disable Address Acknowledge */
|
|
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
|
800894a: 687b ldr r3, [r7, #4]
|
|
800894c: 681b ldr r3, [r3, #0]
|
|
800894e: 685a ldr r2, [r3, #4]
|
|
8008950: 687b ldr r3, [r7, #4]
|
|
8008952: 681b ldr r3, [r3, #0]
|
|
8008954: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8008958: 605a str r2, [r3, #4]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
800895a: 687b ldr r3, [r7, #4]
|
|
800895c: 681b ldr r3, [r3, #0]
|
|
800895e: 6859 ldr r1, [r3, #4]
|
|
8008960: 687b ldr r3, [r7, #4]
|
|
8008962: 681a ldr r2, [r3, #0]
|
|
8008964: 4b8c ldr r3, [pc, #560] @ (8008b98 <I2C_ITSlaveCplt+0x2cc>)
|
|
8008966: 400b ands r3, r1
|
|
8008968: 6053 str r3, [r2, #4]
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
800896a: 6878 ldr r0, [r7, #4]
|
|
800896c: f000 fa85 bl 8008e7a <I2C_Flush_TXDR>
|
|
|
|
#if defined(HAL_DMA_MODULE_ENABLED)
|
|
/* If a DMA is ongoing, Update handle size context */
|
|
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
|
|
8008970: 693b ldr r3, [r7, #16]
|
|
8008972: 0b9b lsrs r3, r3, #14
|
|
8008974: f003 0301 and.w r3, r3, #1
|
|
8008978: 2b00 cmp r3, #0
|
|
800897a: d013 beq.n 80089a4 <I2C_ITSlaveCplt+0xd8>
|
|
{
|
|
/* Disable DMA Request */
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
|
|
800897c: 687b ldr r3, [r7, #4]
|
|
800897e: 681b ldr r3, [r3, #0]
|
|
8008980: 681a ldr r2, [r3, #0]
|
|
8008982: 687b ldr r3, [r7, #4]
|
|
8008984: 681b ldr r3, [r3, #0]
|
|
8008986: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
800898a: 601a str r2, [r3, #0]
|
|
|
|
if (hi2c->hdmatx != NULL)
|
|
800898c: 687b ldr r3, [r7, #4]
|
|
800898e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008990: 2b00 cmp r3, #0
|
|
8008992: d020 beq.n 80089d6 <I2C_ITSlaveCplt+0x10a>
|
|
{
|
|
hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
|
|
8008994: 687b ldr r3, [r7, #4]
|
|
8008996: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008998: 681b ldr r3, [r3, #0]
|
|
800899a: 685b ldr r3, [r3, #4]
|
|
800899c: b29a uxth r2, r3
|
|
800899e: 687b ldr r3, [r7, #4]
|
|
80089a0: 855a strh r2, [r3, #42] @ 0x2a
|
|
80089a2: e018 b.n 80089d6 <I2C_ITSlaveCplt+0x10a>
|
|
}
|
|
}
|
|
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
|
|
80089a4: 693b ldr r3, [r7, #16]
|
|
80089a6: 0bdb lsrs r3, r3, #15
|
|
80089a8: f003 0301 and.w r3, r3, #1
|
|
80089ac: 2b00 cmp r3, #0
|
|
80089ae: d012 beq.n 80089d6 <I2C_ITSlaveCplt+0x10a>
|
|
{
|
|
/* Disable DMA Request */
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
|
|
80089b0: 687b ldr r3, [r7, #4]
|
|
80089b2: 681b ldr r3, [r3, #0]
|
|
80089b4: 681a ldr r2, [r3, #0]
|
|
80089b6: 687b ldr r3, [r7, #4]
|
|
80089b8: 681b ldr r3, [r3, #0]
|
|
80089ba: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
80089be: 601a str r2, [r3, #0]
|
|
|
|
if (hi2c->hdmarx != NULL)
|
|
80089c0: 687b ldr r3, [r7, #4]
|
|
80089c2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80089c4: 2b00 cmp r3, #0
|
|
80089c6: d006 beq.n 80089d6 <I2C_ITSlaveCplt+0x10a>
|
|
{
|
|
hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
|
|
80089c8: 687b ldr r3, [r7, #4]
|
|
80089ca: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80089cc: 681b ldr r3, [r3, #0]
|
|
80089ce: 685b ldr r3, [r3, #4]
|
|
80089d0: b29a uxth r2, r3
|
|
80089d2: 687b ldr r3, [r7, #4]
|
|
80089d4: 855a strh r2, [r3, #42] @ 0x2a
|
|
/* Do nothing */
|
|
}
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
|
|
/* Store Last receive data if any */
|
|
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
|
|
80089d6: 697b ldr r3, [r7, #20]
|
|
80089d8: 089b lsrs r3, r3, #2
|
|
80089da: f003 0301 and.w r3, r3, #1
|
|
80089de: 2b00 cmp r3, #0
|
|
80089e0: d020 beq.n 8008a24 <I2C_ITSlaveCplt+0x158>
|
|
{
|
|
/* Remove RXNE flag on temporary variable as read done */
|
|
tmpITFlags &= ~I2C_FLAG_RXNE;
|
|
80089e2: 697b ldr r3, [r7, #20]
|
|
80089e4: f023 0304 bic.w r3, r3, #4
|
|
80089e8: 617b str r3, [r7, #20]
|
|
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
80089ea: 687b ldr r3, [r7, #4]
|
|
80089ec: 681b ldr r3, [r3, #0]
|
|
80089ee: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
80089f0: 687b ldr r3, [r7, #4]
|
|
80089f2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80089f4: b2d2 uxtb r2, r2
|
|
80089f6: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
80089f8: 687b ldr r3, [r7, #4]
|
|
80089fa: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80089fc: 1c5a adds r2, r3, #1
|
|
80089fe: 687b ldr r3, [r7, #4]
|
|
8008a00: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
if (hi2c->XferSize > 0U)
|
|
8008a02: 687b ldr r3, [r7, #4]
|
|
8008a04: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8008a06: 2b00 cmp r3, #0
|
|
8008a08: d00c beq.n 8008a24 <I2C_ITSlaveCplt+0x158>
|
|
{
|
|
hi2c->XferSize--;
|
|
8008a0a: 687b ldr r3, [r7, #4]
|
|
8008a0c: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8008a0e: 3b01 subs r3, #1
|
|
8008a10: b29a uxth r2, r3
|
|
8008a12: 687b ldr r3, [r7, #4]
|
|
8008a14: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
8008a16: 687b ldr r3, [r7, #4]
|
|
8008a18: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008a1a: b29b uxth r3, r3
|
|
8008a1c: 3b01 subs r3, #1
|
|
8008a1e: b29a uxth r2, r3
|
|
8008a20: 687b ldr r3, [r7, #4]
|
|
8008a22: 855a strh r2, [r3, #42] @ 0x2a
|
|
}
|
|
}
|
|
|
|
/* All data are not transferred, so set error code accordingly */
|
|
if (hi2c->XferCount != 0U)
|
|
8008a24: 687b ldr r3, [r7, #4]
|
|
8008a26: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008a28: b29b uxth r3, r3
|
|
8008a2a: 2b00 cmp r3, #0
|
|
8008a2c: d005 beq.n 8008a3a <I2C_ITSlaveCplt+0x16e>
|
|
{
|
|
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8008a2e: 687b ldr r3, [r7, #4]
|
|
8008a30: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008a32: f043 0204 orr.w r2, r3, #4
|
|
8008a36: 687b ldr r3, [r7, #4]
|
|
8008a38: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
|
8008a3a: 697b ldr r3, [r7, #20]
|
|
8008a3c: 091b lsrs r3, r3, #4
|
|
8008a3e: f003 0301 and.w r3, r3, #1
|
|
8008a42: 2b00 cmp r3, #0
|
|
8008a44: d04a beq.n 8008adc <I2C_ITSlaveCplt+0x210>
|
|
(I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
|
|
8008a46: 693b ldr r3, [r7, #16]
|
|
8008a48: 091b lsrs r3, r3, #4
|
|
8008a4a: f003 0301 and.w r3, r3, #1
|
|
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
|
8008a4e: 2b00 cmp r3, #0
|
|
8008a50: d044 beq.n 8008adc <I2C_ITSlaveCplt+0x210>
|
|
{
|
|
/* Check that I2C transfer finished */
|
|
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
|
/* Mean XferCount == 0*/
|
|
/* So clear Flag NACKF only */
|
|
if (hi2c->XferCount == 0U)
|
|
8008a52: 687b ldr r3, [r7, #4]
|
|
8008a54: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008a56: b29b uxth r3, r3
|
|
8008a58: 2b00 cmp r3, #0
|
|
8008a5a: d128 bne.n 8008aae <I2C_ITSlaveCplt+0x1e2>
|
|
{
|
|
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
|
8008a5c: 687b ldr r3, [r7, #4]
|
|
8008a5e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008a62: b2db uxtb r3, r3
|
|
8008a64: 2b28 cmp r3, #40 @ 0x28
|
|
8008a66: d108 bne.n 8008a7a <I2C_ITSlaveCplt+0x1ae>
|
|
8008a68: 68fb ldr r3, [r7, #12]
|
|
8008a6a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
8008a6e: d104 bne.n 8008a7a <I2C_ITSlaveCplt+0x1ae>
|
|
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
|
|
Warning[Pa134]: left and right operands are identical */
|
|
{
|
|
/* Call I2C Listen complete process */
|
|
I2C_ITListenCplt(hi2c, tmpITFlags);
|
|
8008a70: 6979 ldr r1, [r7, #20]
|
|
8008a72: 6878 ldr r0, [r7, #4]
|
|
8008a74: f000 f894 bl 8008ba0 <I2C_ITListenCplt>
|
|
8008a78: e030 b.n 8008adc <I2C_ITSlaveCplt+0x210>
|
|
}
|
|
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
|
|
8008a7a: 687b ldr r3, [r7, #4]
|
|
8008a7c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008a80: b2db uxtb r3, r3
|
|
8008a82: 2b29 cmp r3, #41 @ 0x29
|
|
8008a84: d10e bne.n 8008aa4 <I2C_ITSlaveCplt+0x1d8>
|
|
8008a86: 68fb ldr r3, [r7, #12]
|
|
8008a88: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
8008a8c: d00a beq.n 8008aa4 <I2C_ITSlaveCplt+0x1d8>
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8008a8e: 687b ldr r3, [r7, #4]
|
|
8008a90: 681b ldr r3, [r3, #0]
|
|
8008a92: 2210 movs r2, #16
|
|
8008a94: 61da str r2, [r3, #28]
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8008a96: 6878 ldr r0, [r7, #4]
|
|
8008a98: f000 f9ef bl 8008e7a <I2C_Flush_TXDR>
|
|
|
|
/* Last Byte is Transmitted */
|
|
/* Call I2C Slave Sequential complete process */
|
|
I2C_ITSlaveSeqCplt(hi2c);
|
|
8008a9c: 6878 ldr r0, [r7, #4]
|
|
8008a9e: f7ff fded bl 800867c <I2C_ITSlaveSeqCplt>
|
|
8008aa2: e01b b.n 8008adc <I2C_ITSlaveCplt+0x210>
|
|
}
|
|
else
|
|
{
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8008aa4: 687b ldr r3, [r7, #4]
|
|
8008aa6: 681b ldr r3, [r3, #0]
|
|
8008aa8: 2210 movs r2, #16
|
|
8008aaa: 61da str r2, [r3, #28]
|
|
8008aac: e016 b.n 8008adc <I2C_ITSlaveCplt+0x210>
|
|
}
|
|
else
|
|
{
|
|
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8008aae: 687b ldr r3, [r7, #4]
|
|
8008ab0: 681b ldr r3, [r3, #0]
|
|
8008ab2: 2210 movs r2, #16
|
|
8008ab4: 61da str r2, [r3, #28]
|
|
|
|
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8008ab6: 687b ldr r3, [r7, #4]
|
|
8008ab8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008aba: f043 0204 orr.w r2, r3, #4
|
|
8008abe: 687b ldr r3, [r7, #4]
|
|
8008ac0: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
|
|
8008ac2: 68fb ldr r3, [r7, #12]
|
|
8008ac4: 2b00 cmp r3, #0
|
|
8008ac6: d003 beq.n 8008ad0 <I2C_ITSlaveCplt+0x204>
|
|
8008ac8: 68fb ldr r3, [r7, #12]
|
|
8008aca: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8008ace: d105 bne.n 8008adc <I2C_ITSlaveCplt+0x210>
|
|
{
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, hi2c->ErrorCode);
|
|
8008ad0: 687b ldr r3, [r7, #4]
|
|
8008ad2: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008ad4: 4619 mov r1, r3
|
|
8008ad6: 6878 ldr r0, [r7, #4]
|
|
8008ad8: f000 f8b8 bl 8008c4c <I2C_ITError>
|
|
}
|
|
}
|
|
}
|
|
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008adc: 687b ldr r3, [r7, #4]
|
|
8008ade: 2200 movs r2, #0
|
|
8008ae0: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->XferISR = NULL;
|
|
8008ae4: 687b ldr r3, [r7, #4]
|
|
8008ae6: 2200 movs r2, #0
|
|
8008ae8: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
|
|
8008aea: 687b ldr r3, [r7, #4]
|
|
8008aec: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008aee: 2b00 cmp r3, #0
|
|
8008af0: d010 beq.n 8008b14 <I2C_ITSlaveCplt+0x248>
|
|
{
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, hi2c->ErrorCode);
|
|
8008af2: 687b ldr r3, [r7, #4]
|
|
8008af4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008af6: 4619 mov r1, r3
|
|
8008af8: 6878 ldr r0, [r7, #4]
|
|
8008afa: f000 f8a7 bl 8008c4c <I2C_ITError>
|
|
|
|
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
|
|
if (hi2c->State == HAL_I2C_STATE_LISTEN)
|
|
8008afe: 687b ldr r3, [r7, #4]
|
|
8008b00: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008b04: b2db uxtb r3, r3
|
|
8008b06: 2b28 cmp r3, #40 @ 0x28
|
|
8008b08: d141 bne.n 8008b8e <I2C_ITSlaveCplt+0x2c2>
|
|
{
|
|
/* Call I2C Listen complete process */
|
|
I2C_ITListenCplt(hi2c, tmpITFlags);
|
|
8008b0a: 6979 ldr r1, [r7, #20]
|
|
8008b0c: 6878 ldr r0, [r7, #4]
|
|
8008b0e: f000 f847 bl 8008ba0 <I2C_ITListenCplt>
|
|
hi2c->SlaveTxCpltCallback(hi2c);
|
|
#else
|
|
HAL_I2C_SlaveTxCpltCallback(hi2c);
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8008b12: e03c b.n 8008b8e <I2C_ITSlaveCplt+0x2c2>
|
|
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
|
|
8008b14: 687b ldr r3, [r7, #4]
|
|
8008b16: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8008b18: f513 3f80 cmn.w r3, #65536 @ 0x10000
|
|
8008b1c: d014 beq.n 8008b48 <I2C_ITSlaveCplt+0x27c>
|
|
I2C_ITSlaveSeqCplt(hi2c);
|
|
8008b1e: 6878 ldr r0, [r7, #4]
|
|
8008b20: f7ff fdac bl 800867c <I2C_ITSlaveSeqCplt>
|
|
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
|
8008b24: 687b ldr r3, [r7, #4]
|
|
8008b26: 4a1d ldr r2, [pc, #116] @ (8008b9c <I2C_ITSlaveCplt+0x2d0>)
|
|
8008b28: 62da str r2, [r3, #44] @ 0x2c
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008b2a: 687b ldr r3, [r7, #4]
|
|
8008b2c: 2220 movs r2, #32
|
|
8008b2e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8008b32: 687b ldr r3, [r7, #4]
|
|
8008b34: 2200 movs r2, #0
|
|
8008b36: 631a str r2, [r3, #48] @ 0x30
|
|
__HAL_UNLOCK(hi2c);
|
|
8008b38: 687b ldr r3, [r7, #4]
|
|
8008b3a: 2200 movs r2, #0
|
|
8008b3c: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_ListenCpltCallback(hi2c);
|
|
8008b40: 6878 ldr r0, [r7, #4]
|
|
8008b42: f7ff f8b2 bl 8007caa <HAL_I2C_ListenCpltCallback>
|
|
}
|
|
8008b46: e022 b.n 8008b8e <I2C_ITSlaveCplt+0x2c2>
|
|
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
|
8008b48: 687b ldr r3, [r7, #4]
|
|
8008b4a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008b4e: b2db uxtb r3, r3
|
|
8008b50: 2b22 cmp r3, #34 @ 0x22
|
|
8008b52: d10e bne.n 8008b72 <I2C_ITSlaveCplt+0x2a6>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008b54: 687b ldr r3, [r7, #4]
|
|
8008b56: 2220 movs r2, #32
|
|
8008b58: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8008b5c: 687b ldr r3, [r7, #4]
|
|
8008b5e: 2200 movs r2, #0
|
|
8008b60: 631a str r2, [r3, #48] @ 0x30
|
|
__HAL_UNLOCK(hi2c);
|
|
8008b62: 687b ldr r3, [r7, #4]
|
|
8008b64: 2200 movs r2, #0
|
|
8008b66: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_SlaveRxCpltCallback(hi2c);
|
|
8008b6a: 6878 ldr r0, [r7, #4]
|
|
8008b6c: f7ff f885 bl 8007c7a <HAL_I2C_SlaveRxCpltCallback>
|
|
}
|
|
8008b70: e00d b.n 8008b8e <I2C_ITSlaveCplt+0x2c2>
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008b72: 687b ldr r3, [r7, #4]
|
|
8008b74: 2220 movs r2, #32
|
|
8008b76: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8008b7a: 687b ldr r3, [r7, #4]
|
|
8008b7c: 2200 movs r2, #0
|
|
8008b7e: 631a str r2, [r3, #48] @ 0x30
|
|
__HAL_UNLOCK(hi2c);
|
|
8008b80: 687b ldr r3, [r7, #4]
|
|
8008b82: 2200 movs r2, #0
|
|
8008b84: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_SlaveTxCpltCallback(hi2c);
|
|
8008b88: 6878 ldr r0, [r7, #4]
|
|
8008b8a: f7ff f86c bl 8007c66 <HAL_I2C_SlaveTxCpltCallback>
|
|
}
|
|
8008b8e: bf00 nop
|
|
8008b90: 3718 adds r7, #24
|
|
8008b92: 46bd mov sp, r7
|
|
8008b94: bd80 pop {r7, pc}
|
|
8008b96: bf00 nop
|
|
8008b98: fe00e800 .word 0xfe00e800
|
|
8008b9c: ffff0000 .word 0xffff0000
|
|
|
|
08008ba0 <I2C_ITListenCplt>:
|
|
* @param hi2c I2C handle.
|
|
* @param ITFlags Interrupt flags to handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|
{
|
|
8008ba0: b580 push {r7, lr}
|
|
8008ba2: b082 sub sp, #8
|
|
8008ba4: af00 add r7, sp, #0
|
|
8008ba6: 6078 str r0, [r7, #4]
|
|
8008ba8: 6039 str r1, [r7, #0]
|
|
/* Reset handle parameters */
|
|
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
|
8008baa: 687b ldr r3, [r7, #4]
|
|
8008bac: 4a26 ldr r2, [pc, #152] @ (8008c48 <I2C_ITListenCplt+0xa8>)
|
|
8008bae: 62da str r2, [r3, #44] @ 0x2c
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8008bb0: 687b ldr r3, [r7, #4]
|
|
8008bb2: 2200 movs r2, #0
|
|
8008bb4: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008bb6: 687b ldr r3, [r7, #4]
|
|
8008bb8: 2220 movs r2, #32
|
|
8008bba: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008bbe: 687b ldr r3, [r7, #4]
|
|
8008bc0: 2200 movs r2, #0
|
|
8008bc2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->XferISR = NULL;
|
|
8008bc6: 687b ldr r3, [r7, #4]
|
|
8008bc8: 2200 movs r2, #0
|
|
8008bca: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Store Last receive data if any */
|
|
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
|
|
8008bcc: 683b ldr r3, [r7, #0]
|
|
8008bce: 089b lsrs r3, r3, #2
|
|
8008bd0: f003 0301 and.w r3, r3, #1
|
|
8008bd4: 2b00 cmp r3, #0
|
|
8008bd6: d022 beq.n 8008c1e <I2C_ITListenCplt+0x7e>
|
|
{
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
8008bd8: 687b ldr r3, [r7, #4]
|
|
8008bda: 681b ldr r3, [r3, #0]
|
|
8008bdc: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8008bde: 687b ldr r3, [r7, #4]
|
|
8008be0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008be2: b2d2 uxtb r2, r2
|
|
8008be4: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8008be6: 687b ldr r3, [r7, #4]
|
|
8008be8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008bea: 1c5a adds r2, r3, #1
|
|
8008bec: 687b ldr r3, [r7, #4]
|
|
8008bee: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
if (hi2c->XferSize > 0U)
|
|
8008bf0: 687b ldr r3, [r7, #4]
|
|
8008bf2: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8008bf4: 2b00 cmp r3, #0
|
|
8008bf6: d012 beq.n 8008c1e <I2C_ITListenCplt+0x7e>
|
|
{
|
|
hi2c->XferSize--;
|
|
8008bf8: 687b ldr r3, [r7, #4]
|
|
8008bfa: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8008bfc: 3b01 subs r3, #1
|
|
8008bfe: b29a uxth r2, r3
|
|
8008c00: 687b ldr r3, [r7, #4]
|
|
8008c02: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
8008c04: 687b ldr r3, [r7, #4]
|
|
8008c06: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008c08: b29b uxth r3, r3
|
|
8008c0a: 3b01 subs r3, #1
|
|
8008c0c: b29a uxth r2, r3
|
|
8008c0e: 687b ldr r3, [r7, #4]
|
|
8008c10: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8008c12: 687b ldr r3, [r7, #4]
|
|
8008c14: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008c16: f043 0204 orr.w r2, r3, #4
|
|
8008c1a: 687b ldr r3, [r7, #4]
|
|
8008c1c: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
}
|
|
|
|
/* Disable all Interrupts*/
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
|
|
8008c1e: f248 0103 movw r1, #32771 @ 0x8003
|
|
8008c22: 6878 ldr r0, [r7, #4]
|
|
8008c24: f000 face bl 80091c4 <I2C_Disable_IRQ>
|
|
|
|
/* Clear NACK Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8008c28: 687b ldr r3, [r7, #4]
|
|
8008c2a: 681b ldr r3, [r3, #0]
|
|
8008c2c: 2210 movs r2, #16
|
|
8008c2e: 61da str r2, [r3, #28]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008c30: 687b ldr r3, [r7, #4]
|
|
8008c32: 2200 movs r2, #0
|
|
8008c34: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
|
|
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
hi2c->ListenCpltCallback(hi2c);
|
|
#else
|
|
HAL_I2C_ListenCpltCallback(hi2c);
|
|
8008c38: 6878 ldr r0, [r7, #4]
|
|
8008c3a: f7ff f836 bl 8007caa <HAL_I2C_ListenCpltCallback>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
8008c3e: bf00 nop
|
|
8008c40: 3708 adds r7, #8
|
|
8008c42: 46bd mov sp, r7
|
|
8008c44: bd80 pop {r7, pc}
|
|
8008c46: bf00 nop
|
|
8008c48: ffff0000 .word 0xffff0000
|
|
|
|
08008c4c <I2C_ITError>:
|
|
* @param hi2c I2C handle.
|
|
* @param ErrorCode Error code to handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
|
{
|
|
8008c4c: b580 push {r7, lr}
|
|
8008c4e: b084 sub sp, #16
|
|
8008c50: af00 add r7, sp, #0
|
|
8008c52: 6078 str r0, [r7, #4]
|
|
8008c54: 6039 str r1, [r7, #0]
|
|
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
|
8008c56: 687b ldr r3, [r7, #4]
|
|
8008c58: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008c5c: 73fb strb r3, [r7, #15]
|
|
#if defined(HAL_DMA_MODULE_ENABLED)
|
|
uint32_t tmppreviousstate;
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
|
|
/* Reset handle parameters */
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008c5e: 687b ldr r3, [r7, #4]
|
|
8008c60: 2200 movs r2, #0
|
|
8008c62: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
|
8008c66: 687b ldr r3, [r7, #4]
|
|
8008c68: 4a6d ldr r2, [pc, #436] @ (8008e20 <I2C_ITError+0x1d4>)
|
|
8008c6a: 62da str r2, [r3, #44] @ 0x2c
|
|
hi2c->XferCount = 0U;
|
|
8008c6c: 687b ldr r3, [r7, #4]
|
|
8008c6e: 2200 movs r2, #0
|
|
8008c70: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
/* Set new error code */
|
|
hi2c->ErrorCode |= ErrorCode;
|
|
8008c72: 687b ldr r3, [r7, #4]
|
|
8008c74: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8008c76: 683b ldr r3, [r7, #0]
|
|
8008c78: 431a orrs r2, r3
|
|
8008c7a: 687b ldr r3, [r7, #4]
|
|
8008c7c: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Disable Interrupts */
|
|
if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
|
|
8008c7e: 7bfb ldrb r3, [r7, #15]
|
|
8008c80: 2b28 cmp r3, #40 @ 0x28
|
|
8008c82: d005 beq.n 8008c90 <I2C_ITError+0x44>
|
|
8008c84: 7bfb ldrb r3, [r7, #15]
|
|
8008c86: 2b29 cmp r3, #41 @ 0x29
|
|
8008c88: d002 beq.n 8008c90 <I2C_ITError+0x44>
|
|
(tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
|
|
8008c8a: 7bfb ldrb r3, [r7, #15]
|
|
8008c8c: 2b2a cmp r3, #42 @ 0x2a
|
|
8008c8e: d10b bne.n 8008ca8 <I2C_ITError+0x5c>
|
|
(tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
|
|
{
|
|
/* Disable all interrupts, except interrupts related to LISTEN state */
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
|
|
8008c90: 2103 movs r1, #3
|
|
8008c92: 6878 ldr r0, [r7, #4]
|
|
8008c94: f000 fa96 bl 80091c4 <I2C_Disable_IRQ>
|
|
|
|
/* keep HAL_I2C_STATE_LISTEN if set */
|
|
hi2c->State = HAL_I2C_STATE_LISTEN;
|
|
8008c98: 687b ldr r3, [r7, #4]
|
|
8008c9a: 2228 movs r2, #40 @ 0x28
|
|
8008c9c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->XferISR = I2C_Slave_ISR_IT;
|
|
8008ca0: 687b ldr r3, [r7, #4]
|
|
8008ca2: 4a60 ldr r2, [pc, #384] @ (8008e24 <I2C_ITError+0x1d8>)
|
|
8008ca4: 635a str r2, [r3, #52] @ 0x34
|
|
8008ca6: e030 b.n 8008d0a <I2C_ITError+0xbe>
|
|
}
|
|
else
|
|
{
|
|
/* Disable all interrupts */
|
|
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
|
|
8008ca8: f248 0103 movw r1, #32771 @ 0x8003
|
|
8008cac: 6878 ldr r0, [r7, #4]
|
|
8008cae: f000 fa89 bl 80091c4 <I2C_Disable_IRQ>
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8008cb2: 6878 ldr r0, [r7, #4]
|
|
8008cb4: f000 f8e1 bl 8008e7a <I2C_Flush_TXDR>
|
|
|
|
/* If state is an abort treatment on going, don't change state */
|
|
/* This change will be do later */
|
|
if (hi2c->State != HAL_I2C_STATE_ABORT)
|
|
8008cb8: 687b ldr r3, [r7, #4]
|
|
8008cba: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008cbe: b2db uxtb r3, r3
|
|
8008cc0: 2b60 cmp r3, #96 @ 0x60
|
|
8008cc2: d01f beq.n 8008d04 <I2C_ITError+0xb8>
|
|
{
|
|
/* Set HAL_I2C_STATE_READY */
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008cc4: 687b ldr r3, [r7, #4]
|
|
8008cc6: 2220 movs r2, #32
|
|
8008cc8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Check if a STOPF is detected */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
|
|
8008ccc: 687b ldr r3, [r7, #4]
|
|
8008cce: 681b ldr r3, [r3, #0]
|
|
8008cd0: 699b ldr r3, [r3, #24]
|
|
8008cd2: f003 0320 and.w r3, r3, #32
|
|
8008cd6: 2b20 cmp r3, #32
|
|
8008cd8: d114 bne.n 8008d04 <I2C_ITError+0xb8>
|
|
{
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
|
8008cda: 687b ldr r3, [r7, #4]
|
|
8008cdc: 681b ldr r3, [r3, #0]
|
|
8008cde: 699b ldr r3, [r3, #24]
|
|
8008ce0: f003 0310 and.w r3, r3, #16
|
|
8008ce4: 2b10 cmp r3, #16
|
|
8008ce6: d109 bne.n 8008cfc <I2C_ITError+0xb0>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8008ce8: 687b ldr r3, [r7, #4]
|
|
8008cea: 681b ldr r3, [r3, #0]
|
|
8008cec: 2210 movs r2, #16
|
|
8008cee: 61da str r2, [r3, #28]
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8008cf0: 687b ldr r3, [r7, #4]
|
|
8008cf2: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8008cf4: f043 0204 orr.w r2, r3, #4
|
|
8008cf8: 687b ldr r3, [r7, #4]
|
|
8008cfa: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8008cfc: 687b ldr r3, [r7, #4]
|
|
8008cfe: 681b ldr r3, [r3, #0]
|
|
8008d00: 2220 movs r2, #32
|
|
8008d02: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
}
|
|
hi2c->XferISR = NULL;
|
|
8008d04: 687b ldr r3, [r7, #4]
|
|
8008d06: 2200 movs r2, #0
|
|
8008d08: 635a str r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
#if defined(HAL_DMA_MODULE_ENABLED)
|
|
/* Abort DMA TX transfer if any */
|
|
tmppreviousstate = hi2c->PreviousState;
|
|
8008d0a: 687b ldr r3, [r7, #4]
|
|
8008d0c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8008d0e: 60bb str r3, [r7, #8]
|
|
|
|
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
|
|
8008d10: 687b ldr r3, [r7, #4]
|
|
8008d12: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008d14: 2b00 cmp r3, #0
|
|
8008d16: d039 beq.n 8008d8c <I2C_ITError+0x140>
|
|
8008d18: 68bb ldr r3, [r7, #8]
|
|
8008d1a: 2b11 cmp r3, #17
|
|
8008d1c: d002 beq.n 8008d24 <I2C_ITError+0xd8>
|
|
8008d1e: 68bb ldr r3, [r7, #8]
|
|
8008d20: 2b21 cmp r3, #33 @ 0x21
|
|
8008d22: d133 bne.n 8008d8c <I2C_ITError+0x140>
|
|
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
|
|
{
|
|
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
|
|
8008d24: 687b ldr r3, [r7, #4]
|
|
8008d26: 681b ldr r3, [r3, #0]
|
|
8008d28: 681b ldr r3, [r3, #0]
|
|
8008d2a: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8008d2e: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
8008d32: d107 bne.n 8008d44 <I2C_ITError+0xf8>
|
|
{
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
|
|
8008d34: 687b ldr r3, [r7, #4]
|
|
8008d36: 681b ldr r3, [r3, #0]
|
|
8008d38: 681a ldr r2, [r3, #0]
|
|
8008d3a: 687b ldr r3, [r7, #4]
|
|
8008d3c: 681b ldr r3, [r3, #0]
|
|
8008d3e: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
8008d42: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
|
|
8008d44: 687b ldr r3, [r7, #4]
|
|
8008d46: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008d48: 4618 mov r0, r3
|
|
8008d4a: f7fe fa21 bl 8007190 <HAL_DMA_GetState>
|
|
8008d4e: 4603 mov r3, r0
|
|
8008d50: 2b01 cmp r3, #1
|
|
8008d52: d017 beq.n 8008d84 <I2C_ITError+0x138>
|
|
{
|
|
/* Set the I2C DMA Abort callback :
|
|
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
|
|
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
|
|
8008d54: 687b ldr r3, [r7, #4]
|
|
8008d56: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008d58: 4a33 ldr r2, [pc, #204] @ (8008e28 <I2C_ITError+0x1dc>)
|
|
8008d5a: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008d5c: 687b ldr r3, [r7, #4]
|
|
8008d5e: 2200 movs r2, #0
|
|
8008d60: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Abort DMA TX */
|
|
if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
|
|
8008d64: 687b ldr r3, [r7, #4]
|
|
8008d66: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008d68: 4618 mov r0, r3
|
|
8008d6a: f7fe f903 bl 8006f74 <HAL_DMA_Abort_IT>
|
|
8008d6e: 4603 mov r3, r0
|
|
8008d70: 2b00 cmp r3, #0
|
|
8008d72: d04d beq.n 8008e10 <I2C_ITError+0x1c4>
|
|
{
|
|
/* Call Directly XferAbortCallback function in case of error */
|
|
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
|
|
8008d74: 687b ldr r3, [r7, #4]
|
|
8008d76: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008d78: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008d7a: 687a ldr r2, [r7, #4]
|
|
8008d7c: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
8008d7e: 4610 mov r0, r2
|
|
8008d80: 4798 blx r3
|
|
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
|
|
8008d82: e045 b.n 8008e10 <I2C_ITError+0x1c4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
I2C_TreatErrorCallback(hi2c);
|
|
8008d84: 6878 ldr r0, [r7, #4]
|
|
8008d86: f000 f851 bl 8008e2c <I2C_TreatErrorCallback>
|
|
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
|
|
8008d8a: e041 b.n 8008e10 <I2C_ITError+0x1c4>
|
|
}
|
|
}
|
|
/* Abort DMA RX transfer if any */
|
|
else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
|
|
8008d8c: 687b ldr r3, [r7, #4]
|
|
8008d8e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8008d90: 2b00 cmp r3, #0
|
|
8008d92: d039 beq.n 8008e08 <I2C_ITError+0x1bc>
|
|
8008d94: 68bb ldr r3, [r7, #8]
|
|
8008d96: 2b12 cmp r3, #18
|
|
8008d98: d002 beq.n 8008da0 <I2C_ITError+0x154>
|
|
8008d9a: 68bb ldr r3, [r7, #8]
|
|
8008d9c: 2b22 cmp r3, #34 @ 0x22
|
|
8008d9e: d133 bne.n 8008e08 <I2C_ITError+0x1bc>
|
|
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
|
|
{
|
|
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
|
|
8008da0: 687b ldr r3, [r7, #4]
|
|
8008da2: 681b ldr r3, [r3, #0]
|
|
8008da4: 681b ldr r3, [r3, #0]
|
|
8008da6: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8008daa: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8008dae: d107 bne.n 8008dc0 <I2C_ITError+0x174>
|
|
{
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
|
|
8008db0: 687b ldr r3, [r7, #4]
|
|
8008db2: 681b ldr r3, [r3, #0]
|
|
8008db4: 681a ldr r2, [r3, #0]
|
|
8008db6: 687b ldr r3, [r7, #4]
|
|
8008db8: 681b ldr r3, [r3, #0]
|
|
8008dba: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8008dbe: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
|
|
8008dc0: 687b ldr r3, [r7, #4]
|
|
8008dc2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8008dc4: 4618 mov r0, r3
|
|
8008dc6: f7fe f9e3 bl 8007190 <HAL_DMA_GetState>
|
|
8008dca: 4603 mov r3, r0
|
|
8008dcc: 2b01 cmp r3, #1
|
|
8008dce: d017 beq.n 8008e00 <I2C_ITError+0x1b4>
|
|
{
|
|
/* Set the I2C DMA Abort callback :
|
|
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
|
|
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
|
|
8008dd0: 687b ldr r3, [r7, #4]
|
|
8008dd2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8008dd4: 4a14 ldr r2, [pc, #80] @ (8008e28 <I2C_ITError+0x1dc>)
|
|
8008dd6: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008dd8: 687b ldr r3, [r7, #4]
|
|
8008dda: 2200 movs r2, #0
|
|
8008ddc: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Abort DMA RX */
|
|
if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
|
|
8008de0: 687b ldr r3, [r7, #4]
|
|
8008de2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8008de4: 4618 mov r0, r3
|
|
8008de6: f7fe f8c5 bl 8006f74 <HAL_DMA_Abort_IT>
|
|
8008dea: 4603 mov r3, r0
|
|
8008dec: 2b00 cmp r3, #0
|
|
8008dee: d011 beq.n 8008e14 <I2C_ITError+0x1c8>
|
|
{
|
|
/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
|
|
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
|
|
8008df0: 687b ldr r3, [r7, #4]
|
|
8008df2: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8008df4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8008df6: 687a ldr r2, [r7, #4]
|
|
8008df8: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
8008dfa: 4610 mov r0, r2
|
|
8008dfc: 4798 blx r3
|
|
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
|
|
8008dfe: e009 b.n 8008e14 <I2C_ITError+0x1c8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
I2C_TreatErrorCallback(hi2c);
|
|
8008e00: 6878 ldr r0, [r7, #4]
|
|
8008e02: f000 f813 bl 8008e2c <I2C_TreatErrorCallback>
|
|
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
|
|
8008e06: e005 b.n 8008e14 <I2C_ITError+0x1c8>
|
|
}
|
|
}
|
|
else
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
{
|
|
I2C_TreatErrorCallback(hi2c);
|
|
8008e08: 6878 ldr r0, [r7, #4]
|
|
8008e0a: f000 f80f bl 8008e2c <I2C_TreatErrorCallback>
|
|
}
|
|
}
|
|
8008e0e: e002 b.n 8008e16 <I2C_ITError+0x1ca>
|
|
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
|
|
8008e10: bf00 nop
|
|
8008e12: e000 b.n 8008e16 <I2C_ITError+0x1ca>
|
|
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
|
|
8008e14: bf00 nop
|
|
}
|
|
8008e16: bf00 nop
|
|
8008e18: 3710 adds r7, #16
|
|
8008e1a: 46bd mov sp, r7
|
|
8008e1c: bd80 pop {r7, pc}
|
|
8008e1e: bf00 nop
|
|
8008e20: ffff0000 .word 0xffff0000
|
|
8008e24: 08007ceb .word 0x08007ceb
|
|
8008e28: 0800901d .word 0x0800901d
|
|
|
|
08008e2c <I2C_TreatErrorCallback>:
|
|
* @brief I2C Error callback treatment.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8008e2c: b580 push {r7, lr}
|
|
8008e2e: b082 sub sp, #8
|
|
8008e30: af00 add r7, sp, #0
|
|
8008e32: 6078 str r0, [r7, #4]
|
|
if (hi2c->State == HAL_I2C_STATE_ABORT)
|
|
8008e34: 687b ldr r3, [r7, #4]
|
|
8008e36: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8008e3a: b2db uxtb r3, r3
|
|
8008e3c: 2b60 cmp r3, #96 @ 0x60
|
|
8008e3e: d10e bne.n 8008e5e <I2C_TreatErrorCallback+0x32>
|
|
{
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008e40: 687b ldr r3, [r7, #4]
|
|
8008e42: 2220 movs r2, #32
|
|
8008e44: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8008e48: 687b ldr r3, [r7, #4]
|
|
8008e4a: 2200 movs r2, #0
|
|
8008e4c: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008e4e: 687b ldr r3, [r7, #4]
|
|
8008e50: 2200 movs r2, #0
|
|
8008e52: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
hi2c->AbortCpltCallback(hi2c);
|
|
#else
|
|
HAL_I2C_AbortCpltCallback(hi2c);
|
|
8008e56: 6878 ldr r0, [r7, #4]
|
|
8008e58: f7fe ff31 bl 8007cbe <HAL_I2C_AbortCpltCallback>
|
|
hi2c->ErrorCallback(hi2c);
|
|
#else
|
|
HAL_I2C_ErrorCallback(hi2c);
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8008e5c: e009 b.n 8008e72 <I2C_TreatErrorCallback+0x46>
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8008e5e: 687b ldr r3, [r7, #4]
|
|
8008e60: 2200 movs r2, #0
|
|
8008e62: 631a str r2, [r3, #48] @ 0x30
|
|
__HAL_UNLOCK(hi2c);
|
|
8008e64: 687b ldr r3, [r7, #4]
|
|
8008e66: 2200 movs r2, #0
|
|
8008e68: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
HAL_I2C_ErrorCallback(hi2c);
|
|
8008e6c: 6878 ldr r0, [r7, #4]
|
|
8008e6e: f7fc fb11 bl 8005494 <HAL_I2C_ErrorCallback>
|
|
}
|
|
8008e72: bf00 nop
|
|
8008e74: 3708 adds r7, #8
|
|
8008e76: 46bd mov sp, r7
|
|
8008e78: bd80 pop {r7, pc}
|
|
|
|
08008e7a <I2C_Flush_TXDR>:
|
|
* @brief I2C Tx data register flush process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8008e7a: b480 push {r7}
|
|
8008e7c: b083 sub sp, #12
|
|
8008e7e: af00 add r7, sp, #0
|
|
8008e80: 6078 str r0, [r7, #4]
|
|
/* If a pending TXIS flag is set */
|
|
/* Write a dummy data in TXDR to clear it */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
|
|
8008e82: 687b ldr r3, [r7, #4]
|
|
8008e84: 681b ldr r3, [r3, #0]
|
|
8008e86: 699b ldr r3, [r3, #24]
|
|
8008e88: f003 0302 and.w r3, r3, #2
|
|
8008e8c: 2b02 cmp r3, #2
|
|
8008e8e: d103 bne.n 8008e98 <I2C_Flush_TXDR+0x1e>
|
|
{
|
|
hi2c->Instance->TXDR = 0x00U;
|
|
8008e90: 687b ldr r3, [r7, #4]
|
|
8008e92: 681b ldr r3, [r3, #0]
|
|
8008e94: 2200 movs r2, #0
|
|
8008e96: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Flush TX register if not empty */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
8008e98: 687b ldr r3, [r7, #4]
|
|
8008e9a: 681b ldr r3, [r3, #0]
|
|
8008e9c: 699b ldr r3, [r3, #24]
|
|
8008e9e: f003 0301 and.w r3, r3, #1
|
|
8008ea2: 2b01 cmp r3, #1
|
|
8008ea4: d007 beq.n 8008eb6 <I2C_Flush_TXDR+0x3c>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
|
|
8008ea6: 687b ldr r3, [r7, #4]
|
|
8008ea8: 681b ldr r3, [r3, #0]
|
|
8008eaa: 699a ldr r2, [r3, #24]
|
|
8008eac: 687b ldr r3, [r7, #4]
|
|
8008eae: 681b ldr r3, [r3, #0]
|
|
8008eb0: f042 0201 orr.w r2, r2, #1
|
|
8008eb4: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
8008eb6: bf00 nop
|
|
8008eb8: 370c adds r7, #12
|
|
8008eba: 46bd mov sp, r7
|
|
8008ebc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008ec0: 4770 bx lr
|
|
|
|
08008ec2 <I2C_DMAMasterTransmitCplt>:
|
|
* @brief DMA I2C master transmit process complete callback.
|
|
* @param hdma DMA handle
|
|
* @retval None
|
|
*/
|
|
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8008ec2: b580 push {r7, lr}
|
|
8008ec4: b084 sub sp, #16
|
|
8008ec6: af00 add r7, sp, #0
|
|
8008ec8: 6078 str r0, [r7, #4]
|
|
/* Derogation MISRAC2012-Rule-11.5 */
|
|
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
8008eca: 687b ldr r3, [r7, #4]
|
|
8008ecc: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8008ece: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable DMA Request */
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
|
|
8008ed0: 68fb ldr r3, [r7, #12]
|
|
8008ed2: 681b ldr r3, [r3, #0]
|
|
8008ed4: 681a ldr r2, [r3, #0]
|
|
8008ed6: 68fb ldr r3, [r7, #12]
|
|
8008ed8: 681b ldr r3, [r3, #0]
|
|
8008eda: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
8008ede: 601a str r2, [r3, #0]
|
|
|
|
/* If last transfer, enable STOP interrupt */
|
|
if (hi2c->XferCount == 0U)
|
|
8008ee0: 68fb ldr r3, [r7, #12]
|
|
8008ee2: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008ee4: b29b uxth r3, r3
|
|
8008ee6: 2b00 cmp r3, #0
|
|
8008ee8: d104 bne.n 8008ef4 <I2C_DMAMasterTransmitCplt+0x32>
|
|
{
|
|
/* Enable STOP interrupt */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
|
|
8008eea: 2120 movs r1, #32
|
|
8008eec: 68f8 ldr r0, [r7, #12]
|
|
8008eee: f000 f8e5 bl 80090bc <I2C_Enable_IRQ>
|
|
{
|
|
/* Enable TC interrupts */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
|
|
}
|
|
}
|
|
}
|
|
8008ef2: e02d b.n 8008f50 <I2C_DMAMasterTransmitCplt+0x8e>
|
|
hi2c->pBuffPtr += hi2c->XferSize;
|
|
8008ef4: 68fb ldr r3, [r7, #12]
|
|
8008ef6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008ef8: 68fa ldr r2, [r7, #12]
|
|
8008efa: 8d12 ldrh r2, [r2, #40] @ 0x28
|
|
8008efc: 441a add r2, r3
|
|
8008efe: 68fb ldr r3, [r7, #12]
|
|
8008f00: 625a str r2, [r3, #36] @ 0x24
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8008f02: 68fb ldr r3, [r7, #12]
|
|
8008f04: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008f06: b29b uxth r3, r3
|
|
8008f08: 2bff cmp r3, #255 @ 0xff
|
|
8008f0a: d903 bls.n 8008f14 <I2C_DMAMasterTransmitCplt+0x52>
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8008f0c: 68fb ldr r3, [r7, #12]
|
|
8008f0e: 22ff movs r2, #255 @ 0xff
|
|
8008f10: 851a strh r2, [r3, #40] @ 0x28
|
|
8008f12: e004 b.n 8008f1e <I2C_DMAMasterTransmitCplt+0x5c>
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8008f14: 68fb ldr r3, [r7, #12]
|
|
8008f16: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008f18: b29a uxth r2, r3
|
|
8008f1a: 68fb ldr r3, [r7, #12]
|
|
8008f1c: 851a strh r2, [r3, #40] @ 0x28
|
|
if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
|
|
8008f1e: 68fb ldr r3, [r7, #12]
|
|
8008f20: 6b98 ldr r0, [r3, #56] @ 0x38
|
|
8008f22: 68fb ldr r3, [r7, #12]
|
|
8008f24: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008f26: 4619 mov r1, r3
|
|
8008f28: 68fb ldr r3, [r7, #12]
|
|
8008f2a: 681b ldr r3, [r3, #0]
|
|
8008f2c: 3328 adds r3, #40 @ 0x28
|
|
8008f2e: 461a mov r2, r3
|
|
hi2c->XferSize) != HAL_OK)
|
|
8008f30: 68fb ldr r3, [r7, #12]
|
|
8008f32: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
|
|
8008f34: f7fd ff44 bl 8006dc0 <HAL_DMA_Start_IT>
|
|
8008f38: 4603 mov r3, r0
|
|
8008f3a: 2b00 cmp r3, #0
|
|
8008f3c: d004 beq.n 8008f48 <I2C_DMAMasterTransmitCplt+0x86>
|
|
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
|
|
8008f3e: 2110 movs r1, #16
|
|
8008f40: 68f8 ldr r0, [r7, #12]
|
|
8008f42: f7ff fe83 bl 8008c4c <I2C_ITError>
|
|
}
|
|
8008f46: e003 b.n 8008f50 <I2C_DMAMasterTransmitCplt+0x8e>
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
|
|
8008f48: 2140 movs r1, #64 @ 0x40
|
|
8008f4a: 68f8 ldr r0, [r7, #12]
|
|
8008f4c: f000 f8b6 bl 80090bc <I2C_Enable_IRQ>
|
|
}
|
|
8008f50: bf00 nop
|
|
8008f52: 3710 adds r7, #16
|
|
8008f54: 46bd mov sp, r7
|
|
8008f56: bd80 pop {r7, pc}
|
|
|
|
08008f58 <I2C_DMAMasterReceiveCplt>:
|
|
* @brief DMA I2C master receive process complete callback.
|
|
* @param hdma DMA handle
|
|
* @retval None
|
|
*/
|
|
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8008f58: b580 push {r7, lr}
|
|
8008f5a: b084 sub sp, #16
|
|
8008f5c: af00 add r7, sp, #0
|
|
8008f5e: 6078 str r0, [r7, #4]
|
|
/* Derogation MISRAC2012-Rule-11.5 */
|
|
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
8008f60: 687b ldr r3, [r7, #4]
|
|
8008f62: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8008f64: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable DMA Request */
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
|
|
8008f66: 68fb ldr r3, [r7, #12]
|
|
8008f68: 681b ldr r3, [r3, #0]
|
|
8008f6a: 681a ldr r2, [r3, #0]
|
|
8008f6c: 68fb ldr r3, [r7, #12]
|
|
8008f6e: 681b ldr r3, [r3, #0]
|
|
8008f70: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8008f74: 601a str r2, [r3, #0]
|
|
|
|
/* If last transfer, enable STOP interrupt */
|
|
if (hi2c->XferCount == 0U)
|
|
8008f76: 68fb ldr r3, [r7, #12]
|
|
8008f78: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008f7a: b29b uxth r3, r3
|
|
8008f7c: 2b00 cmp r3, #0
|
|
8008f7e: d104 bne.n 8008f8a <I2C_DMAMasterReceiveCplt+0x32>
|
|
{
|
|
/* Enable STOP interrupt */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
|
|
8008f80: 2120 movs r1, #32
|
|
8008f82: 68f8 ldr r0, [r7, #12]
|
|
8008f84: f000 f89a bl 80090bc <I2C_Enable_IRQ>
|
|
{
|
|
/* Enable TC interrupts */
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
|
|
}
|
|
}
|
|
}
|
|
8008f88: e02d b.n 8008fe6 <I2C_DMAMasterReceiveCplt+0x8e>
|
|
hi2c->pBuffPtr += hi2c->XferSize;
|
|
8008f8a: 68fb ldr r3, [r7, #12]
|
|
8008f8c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008f8e: 68fa ldr r2, [r7, #12]
|
|
8008f90: 8d12 ldrh r2, [r2, #40] @ 0x28
|
|
8008f92: 441a add r2, r3
|
|
8008f94: 68fb ldr r3, [r7, #12]
|
|
8008f96: 625a str r2, [r3, #36] @ 0x24
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8008f98: 68fb ldr r3, [r7, #12]
|
|
8008f9a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008f9c: b29b uxth r3, r3
|
|
8008f9e: 2bff cmp r3, #255 @ 0xff
|
|
8008fa0: d903 bls.n 8008faa <I2C_DMAMasterReceiveCplt+0x52>
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8008fa2: 68fb ldr r3, [r7, #12]
|
|
8008fa4: 22ff movs r2, #255 @ 0xff
|
|
8008fa6: 851a strh r2, [r3, #40] @ 0x28
|
|
8008fa8: e004 b.n 8008fb4 <I2C_DMAMasterReceiveCplt+0x5c>
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8008faa: 68fb ldr r3, [r7, #12]
|
|
8008fac: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8008fae: b29a uxth r2, r3
|
|
8008fb0: 68fb ldr r3, [r7, #12]
|
|
8008fb2: 851a strh r2, [r3, #40] @ 0x28
|
|
if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
|
|
8008fb4: 68fb ldr r3, [r7, #12]
|
|
8008fb6: 6bd8 ldr r0, [r3, #60] @ 0x3c
|
|
8008fb8: 68fb ldr r3, [r7, #12]
|
|
8008fba: 681b ldr r3, [r3, #0]
|
|
8008fbc: 3324 adds r3, #36 @ 0x24
|
|
8008fbe: 4619 mov r1, r3
|
|
8008fc0: 68fb ldr r3, [r7, #12]
|
|
8008fc2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008fc4: 461a mov r2, r3
|
|
hi2c->XferSize) != HAL_OK)
|
|
8008fc6: 68fb ldr r3, [r7, #12]
|
|
8008fc8: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
|
|
8008fca: f7fd fef9 bl 8006dc0 <HAL_DMA_Start_IT>
|
|
8008fce: 4603 mov r3, r0
|
|
8008fd0: 2b00 cmp r3, #0
|
|
8008fd2: d004 beq.n 8008fde <I2C_DMAMasterReceiveCplt+0x86>
|
|
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
|
|
8008fd4: 2110 movs r1, #16
|
|
8008fd6: 68f8 ldr r0, [r7, #12]
|
|
8008fd8: f7ff fe38 bl 8008c4c <I2C_ITError>
|
|
}
|
|
8008fdc: e003 b.n 8008fe6 <I2C_DMAMasterReceiveCplt+0x8e>
|
|
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
|
|
8008fde: 2140 movs r1, #64 @ 0x40
|
|
8008fe0: 68f8 ldr r0, [r7, #12]
|
|
8008fe2: f000 f86b bl 80090bc <I2C_Enable_IRQ>
|
|
}
|
|
8008fe6: bf00 nop
|
|
8008fe8: 3710 adds r7, #16
|
|
8008fea: 46bd mov sp, r7
|
|
8008fec: bd80 pop {r7, pc}
|
|
|
|
08008fee <I2C_DMAError>:
|
|
* @brief DMA I2C communication error callback.
|
|
* @param hdma DMA handle
|
|
* @retval None
|
|
*/
|
|
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8008fee: b580 push {r7, lr}
|
|
8008ff0: b084 sub sp, #16
|
|
8008ff2: af00 add r7, sp, #0
|
|
8008ff4: 6078 str r0, [r7, #4]
|
|
/* Derogation MISRAC2012-Rule-11.5 */
|
|
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
8008ff6: 687b ldr r3, [r7, #4]
|
|
8008ff8: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8008ffa: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable Acknowledge */
|
|
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
|
8008ffc: 68fb ldr r3, [r7, #12]
|
|
8008ffe: 681b ldr r3, [r3, #0]
|
|
8009000: 685a ldr r2, [r3, #4]
|
|
8009002: 68fb ldr r3, [r7, #12]
|
|
8009004: 681b ldr r3, [r3, #0]
|
|
8009006: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
800900a: 605a str r2, [r3, #4]
|
|
|
|
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
|
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
|
|
800900c: 2110 movs r1, #16
|
|
800900e: 68f8 ldr r0, [r7, #12]
|
|
8009010: f7ff fe1c bl 8008c4c <I2C_ITError>
|
|
}
|
|
8009014: bf00 nop
|
|
8009016: 3710 adds r7, #16
|
|
8009018: 46bd mov sp, r7
|
|
800901a: bd80 pop {r7, pc}
|
|
|
|
0800901c <I2C_DMAAbort>:
|
|
* (To be called at end of DMA Abort procedure).
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800901c: b580 push {r7, lr}
|
|
800901e: b084 sub sp, #16
|
|
8009020: af00 add r7, sp, #0
|
|
8009022: 6078 str r0, [r7, #4]
|
|
/* Derogation MISRAC2012-Rule-11.5 */
|
|
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
8009024: 687b ldr r3, [r7, #4]
|
|
8009026: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8009028: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset AbortCpltCallback */
|
|
if (hi2c->hdmatx != NULL)
|
|
800902a: 68fb ldr r3, [r7, #12]
|
|
800902c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800902e: 2b00 cmp r3, #0
|
|
8009030: d003 beq.n 800903a <I2C_DMAAbort+0x1e>
|
|
{
|
|
hi2c->hdmatx->XferAbortCallback = NULL;
|
|
8009032: 68fb ldr r3, [r7, #12]
|
|
8009034: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8009036: 2200 movs r2, #0
|
|
8009038: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
if (hi2c->hdmarx != NULL)
|
|
800903a: 68fb ldr r3, [r7, #12]
|
|
800903c: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800903e: 2b00 cmp r3, #0
|
|
8009040: d003 beq.n 800904a <I2C_DMAAbort+0x2e>
|
|
{
|
|
hi2c->hdmarx->XferAbortCallback = NULL;
|
|
8009042: 68fb ldr r3, [r7, #12]
|
|
8009044: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8009046: 2200 movs r2, #0
|
|
8009048: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
|
|
I2C_TreatErrorCallback(hi2c);
|
|
800904a: 68f8 ldr r0, [r7, #12]
|
|
800904c: f7ff feee bl 8008e2c <I2C_TreatErrorCallback>
|
|
}
|
|
8009050: bf00 nop
|
|
8009052: 3710 adds r7, #16
|
|
8009054: 46bd mov sp, r7
|
|
8009056: bd80 pop {r7, pc}
|
|
|
|
08009058 <I2C_TransferConfig>:
|
|
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
|
uint32_t Request)
|
|
{
|
|
8009058: b480 push {r7}
|
|
800905a: b087 sub sp, #28
|
|
800905c: af00 add r7, sp, #0
|
|
800905e: 60f8 str r0, [r7, #12]
|
|
8009060: 607b str r3, [r7, #4]
|
|
8009062: 460b mov r3, r1
|
|
8009064: 817b strh r3, [r7, #10]
|
|
8009066: 4613 mov r3, r2
|
|
8009068: 727b strb r3, [r7, #9]
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_TRANSFER_MODE(Mode));
|
|
assert_param(IS_TRANSFER_REQUEST(Request));
|
|
|
|
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
|
tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
800906a: 897b ldrh r3, [r7, #10]
|
|
800906c: f3c3 0209 ubfx r2, r3, #0, #10
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
8009070: 7a7b ldrb r3, [r7, #9]
|
|
8009072: 041b lsls r3, r3, #16
|
|
8009074: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
8009078: 431a orrs r2, r3
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
800907a: 687b ldr r3, [r7, #4]
|
|
800907c: 431a orrs r2, r3
|
|
tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
800907e: 6a3b ldr r3, [r7, #32]
|
|
8009080: 4313 orrs r3, r2
|
|
8009082: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8009086: 617b str r3, [r7, #20]
|
|
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
|
|
|
|
/* update CR2 register */
|
|
MODIFY_REG(hi2c->Instance->CR2, \
|
|
8009088: 68fb ldr r3, [r7, #12]
|
|
800908a: 681b ldr r3, [r3, #0]
|
|
800908c: 685a ldr r2, [r3, #4]
|
|
800908e: 6a3b ldr r3, [r7, #32]
|
|
8009090: 0d5b lsrs r3, r3, #21
|
|
8009092: f403 6180 and.w r1, r3, #1024 @ 0x400
|
|
8009096: 4b08 ldr r3, [pc, #32] @ (80090b8 <I2C_TransferConfig+0x60>)
|
|
8009098: 430b orrs r3, r1
|
|
800909a: 43db mvns r3, r3
|
|
800909c: ea02 0103 and.w r1, r2, r3
|
|
80090a0: 68fb ldr r3, [r7, #12]
|
|
80090a2: 681b ldr r3, [r3, #0]
|
|
80090a4: 697a ldr r2, [r7, #20]
|
|
80090a6: 430a orrs r2, r1
|
|
80090a8: 605a str r2, [r3, #4]
|
|
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
|
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
|
|
I2C_CR2_START | I2C_CR2_STOP)), tmp);
|
|
}
|
|
80090aa: bf00 nop
|
|
80090ac: 371c adds r7, #28
|
|
80090ae: 46bd mov sp, r7
|
|
80090b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80090b4: 4770 bx lr
|
|
80090b6: bf00 nop
|
|
80090b8: 03ff63ff .word 0x03ff63ff
|
|
|
|
080090bc <I2C_Enable_IRQ>:
|
|
* the configuration information for the specified I2C.
|
|
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
|
{
|
|
80090bc: b480 push {r7}
|
|
80090be: b085 sub sp, #20
|
|
80090c0: af00 add r7, sp, #0
|
|
80090c2: 6078 str r0, [r7, #4]
|
|
80090c4: 460b mov r3, r1
|
|
80090c6: 807b strh r3, [r7, #2]
|
|
uint32_t tmpisr = 0U;
|
|
80090c8: 2300 movs r3, #0
|
|
80090ca: 60fb str r3, [r7, #12]
|
|
|
|
#if defined(HAL_DMA_MODULE_ENABLED)
|
|
if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
|
|
80090cc: 687b ldr r3, [r7, #4]
|
|
80090ce: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80090d0: 4a39 ldr r2, [pc, #228] @ (80091b8 <I2C_Enable_IRQ+0xfc>)
|
|
80090d2: 4293 cmp r3, r2
|
|
80090d4: d032 beq.n 800913c <I2C_Enable_IRQ+0x80>
|
|
(hi2c->XferISR != I2C_Slave_ISR_DMA) && \
|
|
80090d6: 687b ldr r3, [r7, #4]
|
|
80090d8: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
|
|
80090da: 4a38 ldr r2, [pc, #224] @ (80091bc <I2C_Enable_IRQ+0x100>)
|
|
80090dc: 4293 cmp r3, r2
|
|
80090de: d02d beq.n 800913c <I2C_Enable_IRQ+0x80>
|
|
(hi2c->XferISR != I2C_Mem_ISR_DMA))
|
|
80090e0: 687b ldr r3, [r7, #4]
|
|
80090e2: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
(hi2c->XferISR != I2C_Slave_ISR_DMA) && \
|
|
80090e4: 4a36 ldr r2, [pc, #216] @ (80091c0 <I2C_Enable_IRQ+0x104>)
|
|
80090e6: 4293 cmp r3, r2
|
|
80090e8: d028 beq.n 800913c <I2C_Enable_IRQ+0x80>
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
{
|
|
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
|
80090ea: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
80090ee: 2b00 cmp r3, #0
|
|
80090f0: da03 bge.n 80090fa <I2C_Enable_IRQ+0x3e>
|
|
{
|
|
/* Enable ERR, STOP, NACK and ADDR interrupts */
|
|
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
|
80090f2: 68fb ldr r3, [r7, #12]
|
|
80090f4: f043 03b8 orr.w r3, r3, #184 @ 0xb8
|
|
80090f8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
|
80090fa: 887b ldrh r3, [r7, #2]
|
|
80090fc: f003 0301 and.w r3, r3, #1
|
|
8009100: 2b00 cmp r3, #0
|
|
8009102: d003 beq.n 800910c <I2C_Enable_IRQ+0x50>
|
|
{
|
|
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
|
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
|
8009104: 68fb ldr r3, [r7, #12]
|
|
8009106: f043 03f2 orr.w r3, r3, #242 @ 0xf2
|
|
800910a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
|
800910c: 887b ldrh r3, [r7, #2]
|
|
800910e: f003 0302 and.w r3, r3, #2
|
|
8009112: 2b00 cmp r3, #0
|
|
8009114: d003 beq.n 800911e <I2C_Enable_IRQ+0x62>
|
|
{
|
|
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
|
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
|
8009116: 68fb ldr r3, [r7, #12]
|
|
8009118: f043 03f4 orr.w r3, r3, #244 @ 0xf4
|
|
800911c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
|
800911e: 887b ldrh r3, [r7, #2]
|
|
8009120: 2b10 cmp r3, #16
|
|
8009122: d103 bne.n 800912c <I2C_Enable_IRQ+0x70>
|
|
{
|
|
/* Enable ERR and NACK interrupts */
|
|
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
|
8009124: 68fb ldr r3, [r7, #12]
|
|
8009126: f043 0390 orr.w r3, r3, #144 @ 0x90
|
|
800912a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
|
800912c: 887b ldrh r3, [r7, #2]
|
|
800912e: 2b20 cmp r3, #32
|
|
8009130: d133 bne.n 800919a <I2C_Enable_IRQ+0xde>
|
|
{
|
|
/* Enable STOP interrupts */
|
|
tmpisr |= I2C_IT_STOPI;
|
|
8009132: 68fb ldr r3, [r7, #12]
|
|
8009134: f043 0320 orr.w r3, r3, #32
|
|
8009138: 60fb str r3, [r7, #12]
|
|
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
|
800913a: e02e b.n 800919a <I2C_Enable_IRQ+0xde>
|
|
}
|
|
|
|
#if defined(HAL_DMA_MODULE_ENABLED)
|
|
else
|
|
{
|
|
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
|
800913c: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
8009140: 2b00 cmp r3, #0
|
|
8009142: da03 bge.n 800914c <I2C_Enable_IRQ+0x90>
|
|
{
|
|
/* Enable ERR, STOP, NACK and ADDR interrupts */
|
|
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
|
8009144: 68fb ldr r3, [r7, #12]
|
|
8009146: f043 03b8 orr.w r3, r3, #184 @ 0xb8
|
|
800914a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
|
800914c: 887b ldrh r3, [r7, #2]
|
|
800914e: f003 0301 and.w r3, r3, #1
|
|
8009152: 2b00 cmp r3, #0
|
|
8009154: d003 beq.n 800915e <I2C_Enable_IRQ+0xa2>
|
|
{
|
|
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
|
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
|
8009156: 68fb ldr r3, [r7, #12]
|
|
8009158: f043 03f2 orr.w r3, r3, #242 @ 0xf2
|
|
800915c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
|
800915e: 887b ldrh r3, [r7, #2]
|
|
8009160: f003 0302 and.w r3, r3, #2
|
|
8009164: 2b00 cmp r3, #0
|
|
8009166: d003 beq.n 8009170 <I2C_Enable_IRQ+0xb4>
|
|
{
|
|
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
|
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
|
8009168: 68fb ldr r3, [r7, #12]
|
|
800916a: f043 03f4 orr.w r3, r3, #244 @ 0xf4
|
|
800916e: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
|
8009170: 887b ldrh r3, [r7, #2]
|
|
8009172: 2b10 cmp r3, #16
|
|
8009174: d103 bne.n 800917e <I2C_Enable_IRQ+0xc2>
|
|
{
|
|
/* Enable ERR and NACK interrupts */
|
|
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
|
8009176: 68fb ldr r3, [r7, #12]
|
|
8009178: f043 0390 orr.w r3, r3, #144 @ 0x90
|
|
800917c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
|
800917e: 887b ldrh r3, [r7, #2]
|
|
8009180: 2b20 cmp r3, #32
|
|
8009182: d103 bne.n 800918c <I2C_Enable_IRQ+0xd0>
|
|
{
|
|
/* Enable STOP interrupts */
|
|
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
|
|
8009184: 68fb ldr r3, [r7, #12]
|
|
8009186: f043 0360 orr.w r3, r3, #96 @ 0x60
|
|
800918a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (InterruptRequest == I2C_XFER_RELOAD_IT)
|
|
800918c: 887b ldrh r3, [r7, #2]
|
|
800918e: 2b40 cmp r3, #64 @ 0x40
|
|
8009190: d103 bne.n 800919a <I2C_Enable_IRQ+0xde>
|
|
{
|
|
/* Enable TC interrupts */
|
|
tmpisr |= I2C_IT_TCI;
|
|
8009192: 68fb ldr r3, [r7, #12]
|
|
8009194: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8009198: 60fb str r3, [r7, #12]
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
|
|
/* Enable interrupts only at the end */
|
|
/* to avoid the risk of I2C interrupt handle execution before */
|
|
/* all interrupts requested done */
|
|
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
|
|
800919a: 687b ldr r3, [r7, #4]
|
|
800919c: 681b ldr r3, [r3, #0]
|
|
800919e: 6819 ldr r1, [r3, #0]
|
|
80091a0: 687b ldr r3, [r7, #4]
|
|
80091a2: 681b ldr r3, [r3, #0]
|
|
80091a4: 68fa ldr r2, [r7, #12]
|
|
80091a6: 430a orrs r2, r1
|
|
80091a8: 601a str r2, [r3, #0]
|
|
}
|
|
80091aa: bf00 nop
|
|
80091ac: 3714 adds r7, #20
|
|
80091ae: 46bd mov sp, r7
|
|
80091b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80091b4: 4770 bx lr
|
|
80091b6: bf00 nop
|
|
80091b8: 08007ef3 .word 0x08007ef3
|
|
80091bc: 08008339 .word 0x08008339
|
|
80091c0: 080080d9 .word 0x080080d9
|
|
|
|
080091c4 <I2C_Disable_IRQ>:
|
|
* the configuration information for the specified I2C.
|
|
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
|
{
|
|
80091c4: b480 push {r7}
|
|
80091c6: b085 sub sp, #20
|
|
80091c8: af00 add r7, sp, #0
|
|
80091ca: 6078 str r0, [r7, #4]
|
|
80091cc: 460b mov r3, r1
|
|
80091ce: 807b strh r3, [r7, #2]
|
|
uint32_t tmpisr = 0U;
|
|
80091d0: 2300 movs r3, #0
|
|
80091d2: 60fb str r3, [r7, #12]
|
|
|
|
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
|
80091d4: 887b ldrh r3, [r7, #2]
|
|
80091d6: f003 0301 and.w r3, r3, #1
|
|
80091da: 2b00 cmp r3, #0
|
|
80091dc: d00f beq.n 80091fe <I2C_Disable_IRQ+0x3a>
|
|
{
|
|
/* Disable TC and TXI interrupts */
|
|
tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
|
|
80091de: 68fb ldr r3, [r7, #12]
|
|
80091e0: f043 0342 orr.w r3, r3, #66 @ 0x42
|
|
80091e4: 60fb str r3, [r7, #12]
|
|
|
|
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
|
|
80091e6: 687b ldr r3, [r7, #4]
|
|
80091e8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
80091ec: b2db uxtb r3, r3
|
|
80091ee: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
80091f2: 2b28 cmp r3, #40 @ 0x28
|
|
80091f4: d003 beq.n 80091fe <I2C_Disable_IRQ+0x3a>
|
|
{
|
|
/* Disable NACK and STOP interrupts */
|
|
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
|
80091f6: 68fb ldr r3, [r7, #12]
|
|
80091f8: f043 03b0 orr.w r3, r3, #176 @ 0xb0
|
|
80091fc: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
|
|
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
|
80091fe: 887b ldrh r3, [r7, #2]
|
|
8009200: f003 0302 and.w r3, r3, #2
|
|
8009204: 2b00 cmp r3, #0
|
|
8009206: d00f beq.n 8009228 <I2C_Disable_IRQ+0x64>
|
|
{
|
|
/* Disable TC and RXI interrupts */
|
|
tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
|
|
8009208: 68fb ldr r3, [r7, #12]
|
|
800920a: f043 0344 orr.w r3, r3, #68 @ 0x44
|
|
800920e: 60fb str r3, [r7, #12]
|
|
|
|
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
|
|
8009210: 687b ldr r3, [r7, #4]
|
|
8009212: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8009216: b2db uxtb r3, r3
|
|
8009218: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
800921c: 2b28 cmp r3, #40 @ 0x28
|
|
800921e: d003 beq.n 8009228 <I2C_Disable_IRQ+0x64>
|
|
{
|
|
/* Disable NACK and STOP interrupts */
|
|
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
|
8009220: 68fb ldr r3, [r7, #12]
|
|
8009222: f043 03b0 orr.w r3, r3, #176 @ 0xb0
|
|
8009226: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
|
|
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
|
8009228: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
800922c: 2b00 cmp r3, #0
|
|
800922e: da03 bge.n 8009238 <I2C_Disable_IRQ+0x74>
|
|
{
|
|
/* Disable ADDR, NACK and STOP interrupts */
|
|
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
|
8009230: 68fb ldr r3, [r7, #12]
|
|
8009232: f043 03b8 orr.w r3, r3, #184 @ 0xb8
|
|
8009236: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
|
8009238: 887b ldrh r3, [r7, #2]
|
|
800923a: 2b10 cmp r3, #16
|
|
800923c: d103 bne.n 8009246 <I2C_Disable_IRQ+0x82>
|
|
{
|
|
/* Enable ERR and NACK interrupts */
|
|
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
|
800923e: 68fb ldr r3, [r7, #12]
|
|
8009240: f043 0390 orr.w r3, r3, #144 @ 0x90
|
|
8009244: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
|
8009246: 887b ldrh r3, [r7, #2]
|
|
8009248: 2b20 cmp r3, #32
|
|
800924a: d103 bne.n 8009254 <I2C_Disable_IRQ+0x90>
|
|
{
|
|
/* Enable STOP interrupts */
|
|
tmpisr |= I2C_IT_STOPI;
|
|
800924c: 68fb ldr r3, [r7, #12]
|
|
800924e: f043 0320 orr.w r3, r3, #32
|
|
8009252: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (InterruptRequest == I2C_XFER_RELOAD_IT)
|
|
8009254: 887b ldrh r3, [r7, #2]
|
|
8009256: 2b40 cmp r3, #64 @ 0x40
|
|
8009258: d103 bne.n 8009262 <I2C_Disable_IRQ+0x9e>
|
|
{
|
|
/* Enable TC interrupts */
|
|
tmpisr |= I2C_IT_TCI;
|
|
800925a: 68fb ldr r3, [r7, #12]
|
|
800925c: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8009260: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Disable interrupts only at the end */
|
|
/* to avoid a breaking situation like at "t" time */
|
|
/* all disable interrupts request are not done */
|
|
__HAL_I2C_DISABLE_IT(hi2c, tmpisr);
|
|
8009262: 687b ldr r3, [r7, #4]
|
|
8009264: 681b ldr r3, [r3, #0]
|
|
8009266: 6819 ldr r1, [r3, #0]
|
|
8009268: 68fb ldr r3, [r7, #12]
|
|
800926a: 43da mvns r2, r3
|
|
800926c: 687b ldr r3, [r7, #4]
|
|
800926e: 681b ldr r3, [r3, #0]
|
|
8009270: 400a ands r2, r1
|
|
8009272: 601a str r2, [r3, #0]
|
|
}
|
|
8009274: bf00 nop
|
|
8009276: 3714 adds r7, #20
|
|
8009278: 46bd mov sp, r7
|
|
800927a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800927e: 4770 bx lr
|
|
|
|
08009280 <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter New state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8009280: b480 push {r7}
|
|
8009282: b083 sub sp, #12
|
|
8009284: af00 add r7, sp, #0
|
|
8009286: 6078 str r0, [r7, #4]
|
|
8009288: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
800928a: 687b ldr r3, [r7, #4]
|
|
800928c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8009290: b2db uxtb r3, r3
|
|
8009292: 2b20 cmp r3, #32
|
|
8009294: d138 bne.n 8009308 <HAL_I2CEx_ConfigAnalogFilter+0x88>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8009296: 687b ldr r3, [r7, #4]
|
|
8009298: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
800929c: 2b01 cmp r3, #1
|
|
800929e: d101 bne.n 80092a4 <HAL_I2CEx_ConfigAnalogFilter+0x24>
|
|
80092a0: 2302 movs r3, #2
|
|
80092a2: e032 b.n 800930a <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
80092a4: 687b ldr r3, [r7, #4]
|
|
80092a6: 2201 movs r2, #1
|
|
80092a8: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80092ac: 687b ldr r3, [r7, #4]
|
|
80092ae: 2224 movs r2, #36 @ 0x24
|
|
80092b0: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80092b4: 687b ldr r3, [r7, #4]
|
|
80092b6: 681b ldr r3, [r3, #0]
|
|
80092b8: 681a ldr r2, [r3, #0]
|
|
80092ba: 687b ldr r3, [r7, #4]
|
|
80092bc: 681b ldr r3, [r3, #0]
|
|
80092be: f022 0201 bic.w r2, r2, #1
|
|
80092c2: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
|
80092c4: 687b ldr r3, [r7, #4]
|
|
80092c6: 681b ldr r3, [r3, #0]
|
|
80092c8: 681a ldr r2, [r3, #0]
|
|
80092ca: 687b ldr r3, [r7, #4]
|
|
80092cc: 681b ldr r3, [r3, #0]
|
|
80092ce: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
80092d2: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog filter bit*/
|
|
hi2c->Instance->CR1 |= AnalogFilter;
|
|
80092d4: 687b ldr r3, [r7, #4]
|
|
80092d6: 681b ldr r3, [r3, #0]
|
|
80092d8: 6819 ldr r1, [r3, #0]
|
|
80092da: 687b ldr r3, [r7, #4]
|
|
80092dc: 681b ldr r3, [r3, #0]
|
|
80092de: 683a ldr r2, [r7, #0]
|
|
80092e0: 430a orrs r2, r1
|
|
80092e2: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
80092e4: 687b ldr r3, [r7, #4]
|
|
80092e6: 681b ldr r3, [r3, #0]
|
|
80092e8: 681a ldr r2, [r3, #0]
|
|
80092ea: 687b ldr r3, [r7, #4]
|
|
80092ec: 681b ldr r3, [r3, #0]
|
|
80092ee: f042 0201 orr.w r2, r2, #1
|
|
80092f2: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80092f4: 687b ldr r3, [r7, #4]
|
|
80092f6: 2220 movs r2, #32
|
|
80092f8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80092fc: 687b ldr r3, [r7, #4]
|
|
80092fe: 2200 movs r2, #0
|
|
8009300: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8009304: 2300 movs r3, #0
|
|
8009306: e000 b.n 800930a <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8009308: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800930a: 4618 mov r0, r3
|
|
800930c: 370c adds r7, #12
|
|
800930e: 46bd mov sp, r7
|
|
8009310: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009314: 4770 bx lr
|
|
|
|
08009316 <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
8009316: b480 push {r7}
|
|
8009318: b085 sub sp, #20
|
|
800931a: af00 add r7, sp, #0
|
|
800931c: 6078 str r0, [r7, #4]
|
|
800931e: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8009320: 687b ldr r3, [r7, #4]
|
|
8009322: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8009326: b2db uxtb r3, r3
|
|
8009328: 2b20 cmp r3, #32
|
|
800932a: d139 bne.n 80093a0 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
800932c: 687b ldr r3, [r7, #4]
|
|
800932e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8009332: 2b01 cmp r3, #1
|
|
8009334: d101 bne.n 800933a <HAL_I2CEx_ConfigDigitalFilter+0x24>
|
|
8009336: 2302 movs r3, #2
|
|
8009338: e033 b.n 80093a2 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
800933a: 687b ldr r3, [r7, #4]
|
|
800933c: 2201 movs r2, #1
|
|
800933e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8009342: 687b ldr r3, [r7, #4]
|
|
8009344: 2224 movs r2, #36 @ 0x24
|
|
8009346: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
800934a: 687b ldr r3, [r7, #4]
|
|
800934c: 681b ldr r3, [r3, #0]
|
|
800934e: 681a ldr r2, [r3, #0]
|
|
8009350: 687b ldr r3, [r7, #4]
|
|
8009352: 681b ldr r3, [r3, #0]
|
|
8009354: f022 0201 bic.w r2, r2, #1
|
|
8009358: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->CR1;
|
|
800935a: 687b ldr r3, [r7, #4]
|
|
800935c: 681b ldr r3, [r3, #0]
|
|
800935e: 681b ldr r3, [r3, #0]
|
|
8009360: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2Cx DNF bits [11:8] */
|
|
tmpreg &= ~(I2C_CR1_DNF);
|
|
8009362: 68fb ldr r3, [r7, #12]
|
|
8009364: f423 6370 bic.w r3, r3, #3840 @ 0xf00
|
|
8009368: 60fb str r3, [r7, #12]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter << 8U;
|
|
800936a: 683b ldr r3, [r7, #0]
|
|
800936c: 021b lsls r3, r3, #8
|
|
800936e: 68fa ldr r2, [r7, #12]
|
|
8009370: 4313 orrs r3, r2
|
|
8009372: 60fb str r3, [r7, #12]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->CR1 = tmpreg;
|
|
8009374: 687b ldr r3, [r7, #4]
|
|
8009376: 681b ldr r3, [r3, #0]
|
|
8009378: 68fa ldr r2, [r7, #12]
|
|
800937a: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
800937c: 687b ldr r3, [r7, #4]
|
|
800937e: 681b ldr r3, [r3, #0]
|
|
8009380: 681a ldr r2, [r3, #0]
|
|
8009382: 687b ldr r3, [r7, #4]
|
|
8009384: 681b ldr r3, [r3, #0]
|
|
8009386: f042 0201 orr.w r2, r2, #1
|
|
800938a: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800938c: 687b ldr r3, [r7, #4]
|
|
800938e: 2220 movs r2, #32
|
|
8009390: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8009394: 687b ldr r3, [r7, #4]
|
|
8009396: 2200 movs r2, #0
|
|
8009398: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
800939c: 2300 movs r3, #0
|
|
800939e: e000 b.n 80093a2 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80093a0: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80093a2: 4618 mov r0, r3
|
|
80093a4: 3714 adds r7, #20
|
|
80093a6: 46bd mov sp, r7
|
|
80093a8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80093ac: 4770 bx lr
|
|
...
|
|
|
|
080093b0 <HAL_IPCC_Init>:
|
|
* @brief Initialize the IPCC peripheral.
|
|
* @param hipcc IPCC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc)
|
|
{
|
|
80093b0: b580 push {r7, lr}
|
|
80093b2: b084 sub sp, #16
|
|
80093b4: af00 add r7, sp, #0
|
|
80093b6: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef err = HAL_OK;
|
|
80093b8: 2300 movs r3, #0
|
|
80093ba: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the IPCC handle allocation */
|
|
if (hipcc != NULL)
|
|
80093bc: 687b ldr r3, [r7, #4]
|
|
80093be: 2b00 cmp r3, #0
|
|
80093c0: d01e beq.n 8009400 <HAL_IPCC_Init+0x50>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
|
|
|
|
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
|
80093c2: 4b13 ldr r3, [pc, #76] @ (8009410 <HAL_IPCC_Init+0x60>)
|
|
80093c4: 60bb str r3, [r7, #8]
|
|
|
|
if (hipcc->State == HAL_IPCC_STATE_RESET)
|
|
80093c6: 687b ldr r3, [r7, #4]
|
|
80093c8: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
|
|
80093cc: b2db uxtb r3, r3
|
|
80093ce: 2b00 cmp r3, #0
|
|
80093d0: d102 bne.n 80093d8 <HAL_IPCC_Init+0x28>
|
|
{
|
|
/* Init the low level hardware : CLOCK, NVIC */
|
|
HAL_IPCC_MspInit(hipcc);
|
|
80093d2: 6878 ldr r0, [r7, #4]
|
|
80093d4: f7fc fee4 bl 80061a0 <HAL_IPCC_MspInit>
|
|
}
|
|
|
|
/* Reset all registers of the current cpu to default state */
|
|
IPCC_Reset_Register(currentInstance);
|
|
80093d8: 68b8 ldr r0, [r7, #8]
|
|
80093da: f000 f85b bl 8009494 <IPCC_Reset_Register>
|
|
|
|
/* Activate the interrupts */
|
|
currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE);
|
|
80093de: 68bb ldr r3, [r7, #8]
|
|
80093e0: 681b ldr r3, [r3, #0]
|
|
80093e2: f043 1201 orr.w r2, r3, #65537 @ 0x10001
|
|
80093e6: 68bb ldr r3, [r7, #8]
|
|
80093e8: 601a str r2, [r3, #0]
|
|
|
|
/* Clear callback pointers */
|
|
IPCC_SetDefaultCallbacks(hipcc);
|
|
80093ea: 6878 ldr r0, [r7, #4]
|
|
80093ec: f000 f82c bl 8009448 <IPCC_SetDefaultCallbacks>
|
|
|
|
/* Reset all callback notification request */
|
|
hipcc->callbackRequest = 0;
|
|
80093f0: 687b ldr r3, [r7, #4]
|
|
80093f2: 2200 movs r2, #0
|
|
80093f4: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
hipcc->State = HAL_IPCC_STATE_READY;
|
|
80093f6: 687b ldr r3, [r7, #4]
|
|
80093f8: 2201 movs r2, #1
|
|
80093fa: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
80093fe: e001 b.n 8009404 <HAL_IPCC_Init+0x54>
|
|
}
|
|
else
|
|
{
|
|
err = HAL_ERROR;
|
|
8009400: 2301 movs r3, #1
|
|
8009402: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return err;
|
|
8009404: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009406: 4618 mov r0, r3
|
|
8009408: 3710 adds r7, #16
|
|
800940a: 46bd mov sp, r7
|
|
800940c: bd80 pop {r7, pc}
|
|
800940e: bf00 nop
|
|
8009410: 58000c00 .word 0x58000c00
|
|
|
|
08009414 <HAL_IPCC_RxCallback>:
|
|
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
|
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
|
* @param ChannelDir Channel direction
|
|
*/
|
|
__weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
|
{
|
|
8009414: b480 push {r7}
|
|
8009416: b085 sub sp, #20
|
|
8009418: af00 add r7, sp, #0
|
|
800941a: 60f8 str r0, [r7, #12]
|
|
800941c: 60b9 str r1, [r7, #8]
|
|
800941e: 4613 mov r3, r2
|
|
8009420: 71fb strb r3, [r7, #7]
|
|
UNUSED(ChannelDir);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_IPCC_RxCallback can be implemented in the user file
|
|
*/
|
|
}
|
|
8009422: bf00 nop
|
|
8009424: 3714 adds r7, #20
|
|
8009426: 46bd mov sp, r7
|
|
8009428: f85d 7b04 ldr.w r7, [sp], #4
|
|
800942c: 4770 bx lr
|
|
|
|
0800942e <HAL_IPCC_TxCallback>:
|
|
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
|
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
|
* @param ChannelDir Channel direction
|
|
*/
|
|
__weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
|
{
|
|
800942e: b480 push {r7}
|
|
8009430: b085 sub sp, #20
|
|
8009432: af00 add r7, sp, #0
|
|
8009434: 60f8 str r0, [r7, #12]
|
|
8009436: 60b9 str r1, [r7, #8]
|
|
8009438: 4613 mov r3, r2
|
|
800943a: 71fb strb r3, [r7, #7]
|
|
UNUSED(ChannelDir);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_IPCC_TxCallback can be implemented in the user file
|
|
*/
|
|
}
|
|
800943c: bf00 nop
|
|
800943e: 3714 adds r7, #20
|
|
8009440: 46bd mov sp, r7
|
|
8009442: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009446: 4770 bx lr
|
|
|
|
08009448 <IPCC_SetDefaultCallbacks>:
|
|
/**
|
|
* @brief Reset all callbacks of the handle to NULL.
|
|
* @param hipcc IPCC handle
|
|
*/
|
|
void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc)
|
|
{
|
|
8009448: b480 push {r7}
|
|
800944a: b085 sub sp, #20
|
|
800944c: af00 add r7, sp, #0
|
|
800944e: 6078 str r0, [r7, #4]
|
|
uint32_t i;
|
|
/* Set all callbacks to default */
|
|
for (i = 0; i < IPCC_CHANNEL_NUMBER; i++)
|
|
8009450: 2300 movs r3, #0
|
|
8009452: 60fb str r3, [r7, #12]
|
|
8009454: e00f b.n 8009476 <IPCC_SetDefaultCallbacks+0x2e>
|
|
{
|
|
hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback;
|
|
8009456: 687a ldr r2, [r7, #4]
|
|
8009458: 68fb ldr r3, [r7, #12]
|
|
800945a: 009b lsls r3, r3, #2
|
|
800945c: 4413 add r3, r2
|
|
800945e: 4a0b ldr r2, [pc, #44] @ (800948c <IPCC_SetDefaultCallbacks+0x44>)
|
|
8009460: 605a str r2, [r3, #4]
|
|
hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback;
|
|
8009462: 687a ldr r2, [r7, #4]
|
|
8009464: 68fb ldr r3, [r7, #12]
|
|
8009466: 3306 adds r3, #6
|
|
8009468: 009b lsls r3, r3, #2
|
|
800946a: 4413 add r3, r2
|
|
800946c: 4a08 ldr r2, [pc, #32] @ (8009490 <IPCC_SetDefaultCallbacks+0x48>)
|
|
800946e: 605a str r2, [r3, #4]
|
|
for (i = 0; i < IPCC_CHANNEL_NUMBER; i++)
|
|
8009470: 68fb ldr r3, [r7, #12]
|
|
8009472: 3301 adds r3, #1
|
|
8009474: 60fb str r3, [r7, #12]
|
|
8009476: 68fb ldr r3, [r7, #12]
|
|
8009478: 2b05 cmp r3, #5
|
|
800947a: d9ec bls.n 8009456 <IPCC_SetDefaultCallbacks+0xe>
|
|
}
|
|
}
|
|
800947c: bf00 nop
|
|
800947e: bf00 nop
|
|
8009480: 3714 adds r7, #20
|
|
8009482: 46bd mov sp, r7
|
|
8009484: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009488: 4770 bx lr
|
|
800948a: bf00 nop
|
|
800948c: 08009415 .word 0x08009415
|
|
8009490: 0800942f .word 0x0800942f
|
|
|
|
08009494 <IPCC_Reset_Register>:
|
|
/**
|
|
* @brief Reset IPCC register to default value for the concerned instance.
|
|
* @param Instance pointer to register
|
|
*/
|
|
void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance)
|
|
{
|
|
8009494: b480 push {r7}
|
|
8009496: b083 sub sp, #12
|
|
8009498: af00 add r7, sp, #0
|
|
800949a: 6078 str r0, [r7, #4]
|
|
/* Disable RX and TX interrupts */
|
|
Instance->CR = 0x00000000U;
|
|
800949c: 687b ldr r3, [r7, #4]
|
|
800949e: 2200 movs r2, #0
|
|
80094a0: 601a str r2, [r3, #0]
|
|
|
|
/* Mask RX and TX interrupts */
|
|
Instance->MR = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF);
|
|
80094a2: 687b ldr r3, [r7, #4]
|
|
80094a4: f04f 123f mov.w r2, #4128831 @ 0x3f003f
|
|
80094a8: 605a str r2, [r3, #4]
|
|
|
|
/* Clear RX status */
|
|
Instance->SCR = IPCC_ALL_RX_BUF;
|
|
80094aa: 687b ldr r3, [r7, #4]
|
|
80094ac: 223f movs r2, #63 @ 0x3f
|
|
80094ae: 609a str r2, [r3, #8]
|
|
}
|
|
80094b0: bf00 nop
|
|
80094b2: 370c adds r7, #12
|
|
80094b4: 46bd mov sp, r7
|
|
80094b6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80094ba: 4770 bx lr
|
|
|
|
080094bc <HAL_PCD_Init>:
|
|
* parameters in the PCD_InitTypeDef and initialize the associated handle.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
80094bc: b580 push {r7, lr}
|
|
80094be: b084 sub sp, #16
|
|
80094c0: af00 add r7, sp, #0
|
|
80094c2: 6078 str r0, [r7, #4]
|
|
uint8_t i;
|
|
|
|
/* Check the PCD handle allocation */
|
|
if (hpcd == NULL)
|
|
80094c4: 687b ldr r3, [r7, #4]
|
|
80094c6: 2b00 cmp r3, #0
|
|
80094c8: d101 bne.n 80094ce <HAL_PCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80094ca: 2301 movs r3, #1
|
|
80094cc: e0c0 b.n 8009650 <HAL_PCD_Init+0x194>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
|
|
|
|
if (hpcd->State == HAL_PCD_STATE_RESET)
|
|
80094ce: 687b ldr r3, [r7, #4]
|
|
80094d0: f893 3291 ldrb.w r3, [r3, #657] @ 0x291
|
|
80094d4: b2db uxtb r3, r3
|
|
80094d6: 2b00 cmp r3, #0
|
|
80094d8: d106 bne.n 80094e8 <HAL_PCD_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hpcd->Lock = HAL_UNLOCKED;
|
|
80094da: 687b ldr r3, [r7, #4]
|
|
80094dc: 2200 movs r2, #0
|
|
80094de: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
/* Init the low level hardware */
|
|
hpcd->MspInitCallback(hpcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_PCD_MspInit(hpcd);
|
|
80094e2: 6878 ldr r0, [r7, #4]
|
|
80094e4: f00f fc00 bl 8018ce8 <HAL_PCD_MspInit>
|
|
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hpcd->State = HAL_PCD_STATE_BUSY;
|
|
80094e8: 687b ldr r3, [r7, #4]
|
|
80094ea: 2203 movs r2, #3
|
|
80094ec: f883 2291 strb.w r2, [r3, #657] @ 0x291
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_PCD_DISABLE(hpcd);
|
|
80094f0: 687b ldr r3, [r7, #4]
|
|
80094f2: 681b ldr r3, [r3, #0]
|
|
80094f4: 4618 mov r0, r3
|
|
80094f6: f005 fe7e bl 800f1f6 <USB_DisableGlobalInt>
|
|
|
|
/* Init endpoints structures */
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
80094fa: 2300 movs r3, #0
|
|
80094fc: 73fb strb r3, [r7, #15]
|
|
80094fe: e03e b.n 800957e <HAL_PCD_Init+0xc2>
|
|
{
|
|
/* Init ep structure */
|
|
hpcd->IN_ep[i].is_in = 1U;
|
|
8009500: 7bfa ldrb r2, [r7, #15]
|
|
8009502: 6879 ldr r1, [r7, #4]
|
|
8009504: 4613 mov r3, r2
|
|
8009506: 009b lsls r3, r3, #2
|
|
8009508: 4413 add r3, r2
|
|
800950a: 00db lsls r3, r3, #3
|
|
800950c: 440b add r3, r1
|
|
800950e: 3311 adds r3, #17
|
|
8009510: 2201 movs r2, #1
|
|
8009512: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].num = i;
|
|
8009514: 7bfa ldrb r2, [r7, #15]
|
|
8009516: 6879 ldr r1, [r7, #4]
|
|
8009518: 4613 mov r3, r2
|
|
800951a: 009b lsls r3, r3, #2
|
|
800951c: 4413 add r3, r2
|
|
800951e: 00db lsls r3, r3, #3
|
|
8009520: 440b add r3, r1
|
|
8009522: 3310 adds r3, #16
|
|
8009524: 7bfa ldrb r2, [r7, #15]
|
|
8009526: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
|
|
8009528: 7bfa ldrb r2, [r7, #15]
|
|
800952a: 6879 ldr r1, [r7, #4]
|
|
800952c: 4613 mov r3, r2
|
|
800952e: 009b lsls r3, r3, #2
|
|
8009530: 4413 add r3, r2
|
|
8009532: 00db lsls r3, r3, #3
|
|
8009534: 440b add r3, r1
|
|
8009536: 3313 adds r3, #19
|
|
8009538: 2200 movs r2, #0
|
|
800953a: 701a strb r2, [r3, #0]
|
|
hpcd->IN_ep[i].maxpacket = 0U;
|
|
800953c: 7bfa ldrb r2, [r7, #15]
|
|
800953e: 6879 ldr r1, [r7, #4]
|
|
8009540: 4613 mov r3, r2
|
|
8009542: 009b lsls r3, r3, #2
|
|
8009544: 4413 add r3, r2
|
|
8009546: 00db lsls r3, r3, #3
|
|
8009548: 440b add r3, r1
|
|
800954a: 3320 adds r3, #32
|
|
800954c: 2200 movs r2, #0
|
|
800954e: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_buff = 0U;
|
|
8009550: 7bfa ldrb r2, [r7, #15]
|
|
8009552: 6879 ldr r1, [r7, #4]
|
|
8009554: 4613 mov r3, r2
|
|
8009556: 009b lsls r3, r3, #2
|
|
8009558: 4413 add r3, r2
|
|
800955a: 00db lsls r3, r3, #3
|
|
800955c: 440b add r3, r1
|
|
800955e: 3324 adds r3, #36 @ 0x24
|
|
8009560: 2200 movs r2, #0
|
|
8009562: 601a str r2, [r3, #0]
|
|
hpcd->IN_ep[i].xfer_len = 0U;
|
|
8009564: 7bfb ldrb r3, [r7, #15]
|
|
8009566: 6879 ldr r1, [r7, #4]
|
|
8009568: 1c5a adds r2, r3, #1
|
|
800956a: 4613 mov r3, r2
|
|
800956c: 009b lsls r3, r3, #2
|
|
800956e: 4413 add r3, r2
|
|
8009570: 00db lsls r3, r3, #3
|
|
8009572: 440b add r3, r1
|
|
8009574: 2200 movs r2, #0
|
|
8009576: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8009578: 7bfb ldrb r3, [r7, #15]
|
|
800957a: 3301 adds r3, #1
|
|
800957c: 73fb strb r3, [r7, #15]
|
|
800957e: 687b ldr r3, [r7, #4]
|
|
8009580: 791b ldrb r3, [r3, #4]
|
|
8009582: 7bfa ldrb r2, [r7, #15]
|
|
8009584: 429a cmp r2, r3
|
|
8009586: d3bb bcc.n 8009500 <HAL_PCD_Init+0x44>
|
|
}
|
|
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8009588: 2300 movs r3, #0
|
|
800958a: 73fb strb r3, [r7, #15]
|
|
800958c: e044 b.n 8009618 <HAL_PCD_Init+0x15c>
|
|
{
|
|
hpcd->OUT_ep[i].is_in = 0U;
|
|
800958e: 7bfa ldrb r2, [r7, #15]
|
|
8009590: 6879 ldr r1, [r7, #4]
|
|
8009592: 4613 mov r3, r2
|
|
8009594: 009b lsls r3, r3, #2
|
|
8009596: 4413 add r3, r2
|
|
8009598: 00db lsls r3, r3, #3
|
|
800959a: 440b add r3, r1
|
|
800959c: f203 1351 addw r3, r3, #337 @ 0x151
|
|
80095a0: 2200 movs r2, #0
|
|
80095a2: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].num = i;
|
|
80095a4: 7bfa ldrb r2, [r7, #15]
|
|
80095a6: 6879 ldr r1, [r7, #4]
|
|
80095a8: 4613 mov r3, r2
|
|
80095aa: 009b lsls r3, r3, #2
|
|
80095ac: 4413 add r3, r2
|
|
80095ae: 00db lsls r3, r3, #3
|
|
80095b0: 440b add r3, r1
|
|
80095b2: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80095b6: 7bfa ldrb r2, [r7, #15]
|
|
80095b8: 701a strb r2, [r3, #0]
|
|
/* Control until ep is activated */
|
|
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
|
|
80095ba: 7bfa ldrb r2, [r7, #15]
|
|
80095bc: 6879 ldr r1, [r7, #4]
|
|
80095be: 4613 mov r3, r2
|
|
80095c0: 009b lsls r3, r3, #2
|
|
80095c2: 4413 add r3, r2
|
|
80095c4: 00db lsls r3, r3, #3
|
|
80095c6: 440b add r3, r1
|
|
80095c8: f203 1353 addw r3, r3, #339 @ 0x153
|
|
80095cc: 2200 movs r2, #0
|
|
80095ce: 701a strb r2, [r3, #0]
|
|
hpcd->OUT_ep[i].maxpacket = 0U;
|
|
80095d0: 7bfa ldrb r2, [r7, #15]
|
|
80095d2: 6879 ldr r1, [r7, #4]
|
|
80095d4: 4613 mov r3, r2
|
|
80095d6: 009b lsls r3, r3, #2
|
|
80095d8: 4413 add r3, r2
|
|
80095da: 00db lsls r3, r3, #3
|
|
80095dc: 440b add r3, r1
|
|
80095de: f503 73b0 add.w r3, r3, #352 @ 0x160
|
|
80095e2: 2200 movs r2, #0
|
|
80095e4: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_buff = 0U;
|
|
80095e6: 7bfa ldrb r2, [r7, #15]
|
|
80095e8: 6879 ldr r1, [r7, #4]
|
|
80095ea: 4613 mov r3, r2
|
|
80095ec: 009b lsls r3, r3, #2
|
|
80095ee: 4413 add r3, r2
|
|
80095f0: 00db lsls r3, r3, #3
|
|
80095f2: 440b add r3, r1
|
|
80095f4: f503 73b2 add.w r3, r3, #356 @ 0x164
|
|
80095f8: 2200 movs r2, #0
|
|
80095fa: 601a str r2, [r3, #0]
|
|
hpcd->OUT_ep[i].xfer_len = 0U;
|
|
80095fc: 7bfa ldrb r2, [r7, #15]
|
|
80095fe: 6879 ldr r1, [r7, #4]
|
|
8009600: 4613 mov r3, r2
|
|
8009602: 009b lsls r3, r3, #2
|
|
8009604: 4413 add r3, r2
|
|
8009606: 00db lsls r3, r3, #3
|
|
8009608: 440b add r3, r1
|
|
800960a: f503 73b4 add.w r3, r3, #360 @ 0x168
|
|
800960e: 2200 movs r2, #0
|
|
8009610: 601a str r2, [r3, #0]
|
|
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
|
|
8009612: 7bfb ldrb r3, [r7, #15]
|
|
8009614: 3301 adds r3, #1
|
|
8009616: 73fb strb r3, [r7, #15]
|
|
8009618: 687b ldr r3, [r7, #4]
|
|
800961a: 791b ldrb r3, [r3, #4]
|
|
800961c: 7bfa ldrb r2, [r7, #15]
|
|
800961e: 429a cmp r2, r3
|
|
8009620: d3b5 bcc.n 800958e <HAL_PCD_Init+0xd2>
|
|
}
|
|
|
|
/* Init Device */
|
|
(void)USB_DevInit(hpcd->Instance, hpcd->Init);
|
|
8009622: 687b ldr r3, [r7, #4]
|
|
8009624: 6818 ldr r0, [r3, #0]
|
|
8009626: 687b ldr r3, [r7, #4]
|
|
8009628: 3304 adds r3, #4
|
|
800962a: e893 0006 ldmia.w r3, {r1, r2}
|
|
800962e: f005 fdfd bl 800f22c <USB_DevInit>
|
|
|
|
hpcd->USB_Address = 0U;
|
|
8009632: 687b ldr r3, [r7, #4]
|
|
8009634: 2200 movs r2, #0
|
|
8009636: 731a strb r2, [r3, #12]
|
|
hpcd->State = HAL_PCD_STATE_READY;
|
|
8009638: 687b ldr r3, [r7, #4]
|
|
800963a: 2201 movs r2, #1
|
|
800963c: f883 2291 strb.w r2, [r3, #657] @ 0x291
|
|
|
|
/* Activate LPM */
|
|
if (hpcd->Init.lpm_enable == 1U)
|
|
8009640: 687b ldr r3, [r7, #4]
|
|
8009642: 7a9b ldrb r3, [r3, #10]
|
|
8009644: 2b01 cmp r3, #1
|
|
8009646: d102 bne.n 800964e <HAL_PCD_Init+0x192>
|
|
{
|
|
(void)HAL_PCDEx_ActivateLPM(hpcd);
|
|
8009648: 6878 ldr r0, [r7, #4]
|
|
800964a: f001 fc4f bl 800aeec <HAL_PCDEx_ActivateLPM>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800964e: 2300 movs r3, #0
|
|
}
|
|
8009650: 4618 mov r0, r3
|
|
8009652: 3710 adds r7, #16
|
|
8009654: 46bd mov sp, r7
|
|
8009656: bd80 pop {r7, pc}
|
|
|
|
08009658 <HAL_PCD_Start>:
|
|
* @brief Start the USB device
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8009658: b580 push {r7, lr}
|
|
800965a: b082 sub sp, #8
|
|
800965c: af00 add r7, sp, #0
|
|
800965e: 6078 str r0, [r7, #4]
|
|
__HAL_LOCK(hpcd);
|
|
8009660: 687b ldr r3, [r7, #4]
|
|
8009662: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
8009666: 2b01 cmp r3, #1
|
|
8009668: d101 bne.n 800966e <HAL_PCD_Start+0x16>
|
|
800966a: 2302 movs r3, #2
|
|
800966c: e012 b.n 8009694 <HAL_PCD_Start+0x3c>
|
|
800966e: 687b ldr r3, [r7, #4]
|
|
8009670: 2201 movs r2, #1
|
|
8009672: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
__HAL_PCD_ENABLE(hpcd);
|
|
8009676: 687b ldr r3, [r7, #4]
|
|
8009678: 681b ldr r3, [r3, #0]
|
|
800967a: 4618 mov r0, r3
|
|
800967c: f005 fda4 bl 800f1c8 <USB_EnableGlobalInt>
|
|
(void)USB_DevConnect(hpcd->Instance);
|
|
8009680: 687b ldr r3, [r7, #4]
|
|
8009682: 681b ldr r3, [r3, #0]
|
|
8009684: 4618 mov r0, r3
|
|
8009686: f007 fb81 bl 8010d8c <USB_DevConnect>
|
|
__HAL_UNLOCK(hpcd);
|
|
800968a: 687b ldr r3, [r7, #4]
|
|
800968c: 2200 movs r2, #0
|
|
800968e: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return HAL_OK;
|
|
8009692: 2300 movs r3, #0
|
|
}
|
|
8009694: 4618 mov r0, r3
|
|
8009696: 3708 adds r7, #8
|
|
8009698: 46bd mov sp, r7
|
|
800969a: bd80 pop {r7, pc}
|
|
|
|
0800969c <HAL_PCD_IRQHandler>:
|
|
* @brief This function handles PCD interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
800969c: b580 push {r7, lr}
|
|
800969e: b084 sub sp, #16
|
|
80096a0: af00 add r7, sp, #0
|
|
80096a2: 6078 str r0, [r7, #4]
|
|
uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
|
|
80096a4: 687b ldr r3, [r7, #4]
|
|
80096a6: 681b ldr r3, [r3, #0]
|
|
80096a8: 4618 mov r0, r3
|
|
80096aa: f007 fb86 bl 8010dba <USB_ReadInterrupts>
|
|
80096ae: 60f8 str r0, [r7, #12]
|
|
|
|
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
|
|
80096b0: 68fb ldr r3, [r7, #12]
|
|
80096b2: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80096b6: 2b00 cmp r3, #0
|
|
80096b8: d003 beq.n 80096c2 <HAL_PCD_IRQHandler+0x26>
|
|
{
|
|
/* servicing of the endpoint correct transfer interrupt */
|
|
/* clear of the CTR flag into the sub */
|
|
(void)PCD_EP_ISR_Handler(hpcd);
|
|
80096ba: 6878 ldr r0, [r7, #4]
|
|
80096bc: f000 fb06 bl 8009ccc <PCD_EP_ISR_Handler>
|
|
|
|
return;
|
|
80096c0: e110 b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
|
|
80096c2: 68fb ldr r3, [r7, #12]
|
|
80096c4: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80096c8: 2b00 cmp r3, #0
|
|
80096ca: d013 beq.n 80096f4 <HAL_PCD_IRQHandler+0x58>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
|
|
80096cc: 687b ldr r3, [r7, #4]
|
|
80096ce: 681b ldr r3, [r3, #0]
|
|
80096d0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80096d4: b29a uxth r2, r3
|
|
80096d6: 687b ldr r3, [r7, #4]
|
|
80096d8: 681b ldr r3, [r3, #0]
|
|
80096da: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
80096de: b292 uxth r2, r2
|
|
80096e0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResetCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResetCallback(hpcd);
|
|
80096e4: 6878 ldr r0, [r7, #4]
|
|
80096e6: f00f fbb2 bl 8018e4e <HAL_PCD_ResetCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
(void)HAL_PCD_SetAddress(hpcd, 0U);
|
|
80096ea: 2100 movs r1, #0
|
|
80096ec: 6878 ldr r0, [r7, #4]
|
|
80096ee: f000 f8fc bl 80098ea <HAL_PCD_SetAddress>
|
|
|
|
return;
|
|
80096f2: e0f7 b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
|
|
80096f4: 68fb ldr r3, [r7, #12]
|
|
80096f6: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80096fa: 2b00 cmp r3, #0
|
|
80096fc: d00c beq.n 8009718 <HAL_PCD_IRQHandler+0x7c>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
|
|
80096fe: 687b ldr r3, [r7, #4]
|
|
8009700: 681b ldr r3, [r3, #0]
|
|
8009702: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
8009706: b29a uxth r2, r3
|
|
8009708: 687b ldr r3, [r7, #4]
|
|
800970a: 681b ldr r3, [r3, #0]
|
|
800970c: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
8009710: b292 uxth r2, r2
|
|
8009712: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
return;
|
|
8009716: e0e5 b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
|
|
8009718: 68fb ldr r3, [r7, #12]
|
|
800971a: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
800971e: 2b00 cmp r3, #0
|
|
8009720: d00c beq.n 800973c <HAL_PCD_IRQHandler+0xa0>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
|
|
8009722: 687b ldr r3, [r7, #4]
|
|
8009724: 681b ldr r3, [r3, #0]
|
|
8009726: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
800972a: b29a uxth r2, r3
|
|
800972c: 687b ldr r3, [r7, #4]
|
|
800972e: 681b ldr r3, [r3, #0]
|
|
8009730: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8009734: b292 uxth r2, r2
|
|
8009736: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
return;
|
|
800973a: e0d3 b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
|
|
800973c: 68fb ldr r3, [r7, #12]
|
|
800973e: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8009742: 2b00 cmp r3, #0
|
|
8009744: d034 beq.n 80097b0 <HAL_PCD_IRQHandler+0x114>
|
|
{
|
|
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
|
|
8009746: 687b ldr r3, [r7, #4]
|
|
8009748: 681b ldr r3, [r3, #0]
|
|
800974a: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
800974e: b29a uxth r2, r3
|
|
8009750: 687b ldr r3, [r7, #4]
|
|
8009752: 681b ldr r3, [r3, #0]
|
|
8009754: f022 0204 bic.w r2, r2, #4
|
|
8009758: b292 uxth r2, r2
|
|
800975a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
|
|
800975e: 687b ldr r3, [r7, #4]
|
|
8009760: 681b ldr r3, [r3, #0]
|
|
8009762: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
8009766: b29a uxth r2, r3
|
|
8009768: 687b ldr r3, [r7, #4]
|
|
800976a: 681b ldr r3, [r3, #0]
|
|
800976c: f022 0208 bic.w r2, r2, #8
|
|
8009770: b292 uxth r2, r2
|
|
8009772: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
if (hpcd->LPM_State == LPM_L1)
|
|
8009776: 687b ldr r3, [r7, #4]
|
|
8009778: f893 32c8 ldrb.w r3, [r3, #712] @ 0x2c8
|
|
800977c: 2b01 cmp r3, #1
|
|
800977e: d107 bne.n 8009790 <HAL_PCD_IRQHandler+0xf4>
|
|
{
|
|
hpcd->LPM_State = LPM_L0;
|
|
8009780: 687b ldr r3, [r7, #4]
|
|
8009782: 2200 movs r2, #0
|
|
8009784: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
|
|
8009788: 2100 movs r1, #0
|
|
800978a: 6878 ldr r0, [r7, #4]
|
|
800978c: f00f fd54 bl 8019238 <HAL_PCDEx_LPM_Callback>
|
|
}
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->ResumeCallback(hpcd);
|
|
#else
|
|
HAL_PCD_ResumeCallback(hpcd);
|
|
8009790: 6878 ldr r0, [r7, #4]
|
|
8009792: f00f fb95 bl 8018ec0 <HAL_PCD_ResumeCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
|
|
8009796: 687b ldr r3, [r7, #4]
|
|
8009798: 681b ldr r3, [r3, #0]
|
|
800979a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
800979e: b29a uxth r2, r3
|
|
80097a0: 687b ldr r3, [r7, #4]
|
|
80097a2: 681b ldr r3, [r3, #0]
|
|
80097a4: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
80097a8: b292 uxth r2, r2
|
|
80097aa: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
return;
|
|
80097ae: e099 b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
|
|
80097b0: 68fb ldr r3, [r7, #12]
|
|
80097b2: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80097b6: 2b00 cmp r3, #0
|
|
80097b8: d027 beq.n 800980a <HAL_PCD_IRQHandler+0x16e>
|
|
{
|
|
/* Force low-power mode in the macrocell */
|
|
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
|
|
80097ba: 687b ldr r3, [r7, #4]
|
|
80097bc: 681b ldr r3, [r3, #0]
|
|
80097be: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
80097c2: b29a uxth r2, r3
|
|
80097c4: 687b ldr r3, [r7, #4]
|
|
80097c6: 681b ldr r3, [r3, #0]
|
|
80097c8: f042 0208 orr.w r2, r2, #8
|
|
80097cc: b292 uxth r2, r2
|
|
80097ce: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
|
|
80097d2: 687b ldr r3, [r7, #4]
|
|
80097d4: 681b ldr r3, [r3, #0]
|
|
80097d6: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80097da: b29a uxth r2, r3
|
|
80097dc: 687b ldr r3, [r7, #4]
|
|
80097de: 681b ldr r3, [r3, #0]
|
|
80097e0: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
80097e4: b292 uxth r2, r2
|
|
80097e6: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
|
|
80097ea: 687b ldr r3, [r7, #4]
|
|
80097ec: 681b ldr r3, [r3, #0]
|
|
80097ee: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
80097f2: b29a uxth r2, r3
|
|
80097f4: 687b ldr r3, [r7, #4]
|
|
80097f6: 681b ldr r3, [r3, #0]
|
|
80097f8: f042 0204 orr.w r2, r2, #4
|
|
80097fc: b292 uxth r2, r2
|
|
80097fe: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SuspendCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
8009802: 6878 ldr r0, [r7, #4]
|
|
8009804: f00f fb42 bl 8018e8c <HAL_PCD_SuspendCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
return;
|
|
8009808: e06c b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
}
|
|
|
|
/* Handle LPM Interrupt */
|
|
if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ)
|
|
800980a: 68fb ldr r3, [r7, #12]
|
|
800980c: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8009810: 2b00 cmp r3, #0
|
|
8009812: d040 beq.n 8009896 <HAL_PCD_IRQHandler+0x1fa>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
|
|
8009814: 687b ldr r3, [r7, #4]
|
|
8009816: 681b ldr r3, [r3, #0]
|
|
8009818: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
800981c: b29a uxth r2, r3
|
|
800981e: 687b ldr r3, [r7, #4]
|
|
8009820: 681b ldr r3, [r3, #0]
|
|
8009822: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8009826: b292 uxth r2, r2
|
|
8009828: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
if (hpcd->LPM_State == LPM_L0)
|
|
800982c: 687b ldr r3, [r7, #4]
|
|
800982e: f893 32c8 ldrb.w r3, [r3, #712] @ 0x2c8
|
|
8009832: 2b00 cmp r3, #0
|
|
8009834: d12b bne.n 800988e <HAL_PCD_IRQHandler+0x1f2>
|
|
{
|
|
/* Force suspend and low-power mode before going to L1 state*/
|
|
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
|
|
8009836: 687b ldr r3, [r7, #4]
|
|
8009838: 681b ldr r3, [r3, #0]
|
|
800983a: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
800983e: b29a uxth r2, r3
|
|
8009840: 687b ldr r3, [r7, #4]
|
|
8009842: 681b ldr r3, [r3, #0]
|
|
8009844: f042 0204 orr.w r2, r2, #4
|
|
8009848: b292 uxth r2, r2
|
|
800984a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
|
|
800984e: 687b ldr r3, [r7, #4]
|
|
8009850: 681b ldr r3, [r3, #0]
|
|
8009852: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
8009856: b29a uxth r2, r3
|
|
8009858: 687b ldr r3, [r7, #4]
|
|
800985a: 681b ldr r3, [r3, #0]
|
|
800985c: f042 0208 orr.w r2, r2, #8
|
|
8009860: b292 uxth r2, r2
|
|
8009862: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
hpcd->LPM_State = LPM_L1;
|
|
8009866: 687b ldr r3, [r7, #4]
|
|
8009868: 2201 movs r2, #1
|
|
800986a: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8
|
|
hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
|
|
800986e: 687b ldr r3, [r7, #4]
|
|
8009870: 681b ldr r3, [r3, #0]
|
|
8009872: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54
|
|
8009876: b29b uxth r3, r3
|
|
8009878: 089b lsrs r3, r3, #2
|
|
800987a: f003 023c and.w r2, r3, #60 @ 0x3c
|
|
800987e: 687b ldr r3, [r7, #4]
|
|
8009880: f8c3 22cc str.w r2, [r3, #716] @ 0x2cc
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
#else
|
|
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
|
|
8009884: 2101 movs r1, #1
|
|
8009886: 6878 ldr r0, [r7, #4]
|
|
8009888: f00f fcd6 bl 8019238 <HAL_PCDEx_LPM_Callback>
|
|
#else
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
return;
|
|
800988c: e02a b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
HAL_PCD_SuspendCallback(hpcd);
|
|
800988e: 6878 ldr r0, [r7, #4]
|
|
8009890: f00f fafc bl 8018e8c <HAL_PCD_SuspendCallback>
|
|
return;
|
|
8009894: e026 b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
|
|
8009896: 68fb ldr r3, [r7, #12]
|
|
8009898: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800989c: 2b00 cmp r3, #0
|
|
800989e: d00f beq.n 80098c0 <HAL_PCD_IRQHandler+0x224>
|
|
{
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
|
|
80098a0: 687b ldr r3, [r7, #4]
|
|
80098a2: 681b ldr r3, [r3, #0]
|
|
80098a4: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80098a8: b29a uxth r2, r3
|
|
80098aa: 687b ldr r3, [r7, #4]
|
|
80098ac: 681b ldr r3, [r3, #0]
|
|
80098ae: f422 7200 bic.w r2, r2, #512 @ 0x200
|
|
80098b2: b292 uxth r2, r2
|
|
80098b4: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SOFCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SOFCallback(hpcd);
|
|
80098b8: 6878 ldr r0, [r7, #4]
|
|
80098ba: f00f faba bl 8018e32 <HAL_PCD_SOFCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
return;
|
|
80098be: e011 b.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
}
|
|
|
|
if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
|
|
80098c0: 68fb ldr r3, [r7, #12]
|
|
80098c2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80098c6: 2b00 cmp r3, #0
|
|
80098c8: d00c beq.n 80098e4 <HAL_PCD_IRQHandler+0x248>
|
|
{
|
|
/* clear ESOF flag in ISTR */
|
|
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
|
|
80098ca: 687b ldr r3, [r7, #4]
|
|
80098cc: 681b ldr r3, [r3, #0]
|
|
80098ce: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
80098d2: b29a uxth r2, r3
|
|
80098d4: 687b ldr r3, [r7, #4]
|
|
80098d6: 681b ldr r3, [r3, #0]
|
|
80098d8: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
80098dc: b292 uxth r2, r2
|
|
80098de: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
return;
|
|
80098e2: bf00 nop
|
|
}
|
|
}
|
|
80098e4: 3710 adds r7, #16
|
|
80098e6: 46bd mov sp, r7
|
|
80098e8: bd80 pop {r7, pc}
|
|
|
|
080098ea <HAL_PCD_SetAddress>:
|
|
* @param hpcd PCD handle
|
|
* @param address new device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|
{
|
|
80098ea: b580 push {r7, lr}
|
|
80098ec: b082 sub sp, #8
|
|
80098ee: af00 add r7, sp, #0
|
|
80098f0: 6078 str r0, [r7, #4]
|
|
80098f2: 460b mov r3, r1
|
|
80098f4: 70fb strb r3, [r7, #3]
|
|
__HAL_LOCK(hpcd);
|
|
80098f6: 687b ldr r3, [r7, #4]
|
|
80098f8: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
80098fc: 2b01 cmp r3, #1
|
|
80098fe: d101 bne.n 8009904 <HAL_PCD_SetAddress+0x1a>
|
|
8009900: 2302 movs r3, #2
|
|
8009902: e012 b.n 800992a <HAL_PCD_SetAddress+0x40>
|
|
8009904: 687b ldr r3, [r7, #4]
|
|
8009906: 2201 movs r2, #1
|
|
8009908: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
hpcd->USB_Address = address;
|
|
800990c: 687b ldr r3, [r7, #4]
|
|
800990e: 78fa ldrb r2, [r7, #3]
|
|
8009910: 731a strb r2, [r3, #12]
|
|
(void)USB_SetDevAddress(hpcd->Instance, address);
|
|
8009912: 687b ldr r3, [r7, #4]
|
|
8009914: 681b ldr r3, [r3, #0]
|
|
8009916: 78fa ldrb r2, [r7, #3]
|
|
8009918: 4611 mov r1, r2
|
|
800991a: 4618 mov r0, r3
|
|
800991c: f007 fa22 bl 8010d64 <USB_SetDevAddress>
|
|
__HAL_UNLOCK(hpcd);
|
|
8009920: 687b ldr r3, [r7, #4]
|
|
8009922: 2200 movs r2, #0
|
|
8009924: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return HAL_OK;
|
|
8009928: 2300 movs r3, #0
|
|
}
|
|
800992a: 4618 mov r0, r3
|
|
800992c: 3708 adds r7, #8
|
|
800992e: 46bd mov sp, r7
|
|
8009930: bd80 pop {r7, pc}
|
|
|
|
08009932 <HAL_PCD_EP_Open>:
|
|
* @param ep_type endpoint type
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|
uint16_t ep_mps, uint8_t ep_type)
|
|
{
|
|
8009932: b580 push {r7, lr}
|
|
8009934: b084 sub sp, #16
|
|
8009936: af00 add r7, sp, #0
|
|
8009938: 6078 str r0, [r7, #4]
|
|
800993a: 4608 mov r0, r1
|
|
800993c: 4611 mov r1, r2
|
|
800993e: 461a mov r2, r3
|
|
8009940: 4603 mov r3, r0
|
|
8009942: 70fb strb r3, [r7, #3]
|
|
8009944: 460b mov r3, r1
|
|
8009946: 803b strh r3, [r7, #0]
|
|
8009948: 4613 mov r3, r2
|
|
800994a: 70bb strb r3, [r7, #2]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800994c: 2300 movs r3, #0
|
|
800994e: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
8009950: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8009954: 2b00 cmp r3, #0
|
|
8009956: da0e bge.n 8009976 <HAL_PCD_EP_Open+0x44>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8009958: 78fb ldrb r3, [r7, #3]
|
|
800995a: f003 0207 and.w r2, r3, #7
|
|
800995e: 4613 mov r3, r2
|
|
8009960: 009b lsls r3, r3, #2
|
|
8009962: 4413 add r3, r2
|
|
8009964: 00db lsls r3, r3, #3
|
|
8009966: 3310 adds r3, #16
|
|
8009968: 687a ldr r2, [r7, #4]
|
|
800996a: 4413 add r3, r2
|
|
800996c: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
800996e: 68fb ldr r3, [r7, #12]
|
|
8009970: 2201 movs r2, #1
|
|
8009972: 705a strb r2, [r3, #1]
|
|
8009974: e00e b.n 8009994 <HAL_PCD_EP_Open+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8009976: 78fb ldrb r3, [r7, #3]
|
|
8009978: f003 0207 and.w r2, r3, #7
|
|
800997c: 4613 mov r3, r2
|
|
800997e: 009b lsls r3, r3, #2
|
|
8009980: 4413 add r3, r2
|
|
8009982: 00db lsls r3, r3, #3
|
|
8009984: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009988: 687a ldr r2, [r7, #4]
|
|
800998a: 4413 add r3, r2
|
|
800998c: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
800998e: 68fb ldr r3, [r7, #12]
|
|
8009990: 2200 movs r2, #0
|
|
8009992: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8009994: 78fb ldrb r3, [r7, #3]
|
|
8009996: f003 0307 and.w r3, r3, #7
|
|
800999a: b2da uxtb r2, r3
|
|
800999c: 68fb ldr r3, [r7, #12]
|
|
800999e: 701a strb r2, [r3, #0]
|
|
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
|
|
80099a0: 883b ldrh r3, [r7, #0]
|
|
80099a2: f3c3 020a ubfx r2, r3, #0, #11
|
|
80099a6: 68fb ldr r3, [r7, #12]
|
|
80099a8: 611a str r2, [r3, #16]
|
|
ep->type = ep_type;
|
|
80099aa: 68fb ldr r3, [r7, #12]
|
|
80099ac: 78ba ldrb r2, [r7, #2]
|
|
80099ae: 70da strb r2, [r3, #3]
|
|
|
|
/* Set initial data PID. */
|
|
if (ep_type == EP_TYPE_BULK)
|
|
80099b0: 78bb ldrb r3, [r7, #2]
|
|
80099b2: 2b02 cmp r3, #2
|
|
80099b4: d102 bne.n 80099bc <HAL_PCD_EP_Open+0x8a>
|
|
{
|
|
ep->data_pid_start = 0U;
|
|
80099b6: 68fb ldr r3, [r7, #12]
|
|
80099b8: 2200 movs r2, #0
|
|
80099ba: 711a strb r2, [r3, #4]
|
|
}
|
|
|
|
__HAL_LOCK(hpcd);
|
|
80099bc: 687b ldr r3, [r7, #4]
|
|
80099be: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
80099c2: 2b01 cmp r3, #1
|
|
80099c4: d101 bne.n 80099ca <HAL_PCD_EP_Open+0x98>
|
|
80099c6: 2302 movs r3, #2
|
|
80099c8: e00e b.n 80099e8 <HAL_PCD_EP_Open+0xb6>
|
|
80099ca: 687b ldr r3, [r7, #4]
|
|
80099cc: 2201 movs r2, #1
|
|
80099ce: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
|
|
80099d2: 687b ldr r3, [r7, #4]
|
|
80099d4: 681b ldr r3, [r3, #0]
|
|
80099d6: 68f9 ldr r1, [r7, #12]
|
|
80099d8: 4618 mov r0, r3
|
|
80099da: f005 fc45 bl 800f268 <USB_ActivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
80099de: 687b ldr r3, [r7, #4]
|
|
80099e0: 2200 movs r2, #0
|
|
80099e2: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return ret;
|
|
80099e6: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
80099e8: 4618 mov r0, r3
|
|
80099ea: 3710 adds r7, #16
|
|
80099ec: 46bd mov sp, r7
|
|
80099ee: bd80 pop {r7, pc}
|
|
|
|
080099f0 <HAL_PCD_EP_Close>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
80099f0: b580 push {r7, lr}
|
|
80099f2: b084 sub sp, #16
|
|
80099f4: af00 add r7, sp, #0
|
|
80099f6: 6078 str r0, [r7, #4]
|
|
80099f8: 460b mov r3, r1
|
|
80099fa: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
80099fc: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8009a00: 2b00 cmp r3, #0
|
|
8009a02: da0e bge.n 8009a22 <HAL_PCD_EP_Close+0x32>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8009a04: 78fb ldrb r3, [r7, #3]
|
|
8009a06: f003 0207 and.w r2, r3, #7
|
|
8009a0a: 4613 mov r3, r2
|
|
8009a0c: 009b lsls r3, r3, #2
|
|
8009a0e: 4413 add r3, r2
|
|
8009a10: 00db lsls r3, r3, #3
|
|
8009a12: 3310 adds r3, #16
|
|
8009a14: 687a ldr r2, [r7, #4]
|
|
8009a16: 4413 add r3, r2
|
|
8009a18: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8009a1a: 68fb ldr r3, [r7, #12]
|
|
8009a1c: 2201 movs r2, #1
|
|
8009a1e: 705a strb r2, [r3, #1]
|
|
8009a20: e00e b.n 8009a40 <HAL_PCD_EP_Close+0x50>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8009a22: 78fb ldrb r3, [r7, #3]
|
|
8009a24: f003 0207 and.w r2, r3, #7
|
|
8009a28: 4613 mov r3, r2
|
|
8009a2a: 009b lsls r3, r3, #2
|
|
8009a2c: 4413 add r3, r2
|
|
8009a2e: 00db lsls r3, r3, #3
|
|
8009a30: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009a34: 687a ldr r2, [r7, #4]
|
|
8009a36: 4413 add r3, r2
|
|
8009a38: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8009a3a: 68fb ldr r3, [r7, #12]
|
|
8009a3c: 2200 movs r2, #0
|
|
8009a3e: 705a strb r2, [r3, #1]
|
|
}
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8009a40: 78fb ldrb r3, [r7, #3]
|
|
8009a42: f003 0307 and.w r3, r3, #7
|
|
8009a46: b2da uxtb r2, r3
|
|
8009a48: 68fb ldr r3, [r7, #12]
|
|
8009a4a: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8009a4c: 687b ldr r3, [r7, #4]
|
|
8009a4e: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
8009a52: 2b01 cmp r3, #1
|
|
8009a54: d101 bne.n 8009a5a <HAL_PCD_EP_Close+0x6a>
|
|
8009a56: 2302 movs r3, #2
|
|
8009a58: e00e b.n 8009a78 <HAL_PCD_EP_Close+0x88>
|
|
8009a5a: 687b ldr r3, [r7, #4]
|
|
8009a5c: 2201 movs r2, #1
|
|
8009a5e: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
|
|
8009a62: 687b ldr r3, [r7, #4]
|
|
8009a64: 681b ldr r3, [r3, #0]
|
|
8009a66: 68f9 ldr r1, [r7, #12]
|
|
8009a68: 4618 mov r0, r3
|
|
8009a6a: f006 f8e5 bl 800fc38 <USB_DeactivateEndpoint>
|
|
__HAL_UNLOCK(hpcd);
|
|
8009a6e: 687b ldr r3, [r7, #4]
|
|
8009a70: 2200 movs r2, #0
|
|
8009a72: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
return HAL_OK;
|
|
8009a76: 2300 movs r3, #0
|
|
}
|
|
8009a78: 4618 mov r0, r3
|
|
8009a7a: 3710 adds r7, #16
|
|
8009a7c: 46bd mov sp, r7
|
|
8009a7e: bd80 pop {r7, pc}
|
|
|
|
08009a80 <HAL_PCD_EP_Receive>:
|
|
* @param pBuf pointer to the reception buffer
|
|
* @param len amount of data to be received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8009a80: b580 push {r7, lr}
|
|
8009a82: b086 sub sp, #24
|
|
8009a84: af00 add r7, sp, #0
|
|
8009a86: 60f8 str r0, [r7, #12]
|
|
8009a88: 607a str r2, [r7, #4]
|
|
8009a8a: 603b str r3, [r7, #0]
|
|
8009a8c: 460b mov r3, r1
|
|
8009a8e: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8009a90: 7afb ldrb r3, [r7, #11]
|
|
8009a92: f003 0207 and.w r2, r3, #7
|
|
8009a96: 4613 mov r3, r2
|
|
8009a98: 009b lsls r3, r3, #2
|
|
8009a9a: 4413 add r3, r2
|
|
8009a9c: 00db lsls r3, r3, #3
|
|
8009a9e: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009aa2: 68fa ldr r2, [r7, #12]
|
|
8009aa4: 4413 add r3, r2
|
|
8009aa6: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8009aa8: 697b ldr r3, [r7, #20]
|
|
8009aaa: 687a ldr r2, [r7, #4]
|
|
8009aac: 615a str r2, [r3, #20]
|
|
ep->xfer_len = len;
|
|
8009aae: 697b ldr r3, [r7, #20]
|
|
8009ab0: 683a ldr r2, [r7, #0]
|
|
8009ab2: 619a str r2, [r3, #24]
|
|
ep->xfer_count = 0U;
|
|
8009ab4: 697b ldr r3, [r7, #20]
|
|
8009ab6: 2200 movs r2, #0
|
|
8009ab8: 61da str r2, [r3, #28]
|
|
ep->is_in = 0U;
|
|
8009aba: 697b ldr r3, [r7, #20]
|
|
8009abc: 2200 movs r2, #0
|
|
8009abe: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8009ac0: 7afb ldrb r3, [r7, #11]
|
|
8009ac2: f003 0307 and.w r3, r3, #7
|
|
8009ac6: b2da uxtb r2, r3
|
|
8009ac8: 697b ldr r3, [r7, #20]
|
|
8009aca: 701a strb r2, [r3, #0]
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
|
8009acc: 68fb ldr r3, [r7, #12]
|
|
8009ace: 681b ldr r3, [r3, #0]
|
|
8009ad0: 6979 ldr r1, [r7, #20]
|
|
8009ad2: 4618 mov r0, r3
|
|
8009ad4: f006 fa9d bl 8010012 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8009ad8: 2300 movs r3, #0
|
|
}
|
|
8009ada: 4618 mov r0, r3
|
|
8009adc: 3718 adds r7, #24
|
|
8009ade: 46bd mov sp, r7
|
|
8009ae0: bd80 pop {r7, pc}
|
|
|
|
08009ae2 <HAL_PCD_EP_GetRxCount>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval Data Size
|
|
*/
|
|
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
|
|
{
|
|
8009ae2: b480 push {r7}
|
|
8009ae4: b083 sub sp, #12
|
|
8009ae6: af00 add r7, sp, #0
|
|
8009ae8: 6078 str r0, [r7, #4]
|
|
8009aea: 460b mov r3, r1
|
|
8009aec: 70fb strb r3, [r7, #3]
|
|
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
|
|
8009aee: 78fb ldrb r3, [r7, #3]
|
|
8009af0: f003 0207 and.w r2, r3, #7
|
|
8009af4: 6879 ldr r1, [r7, #4]
|
|
8009af6: 4613 mov r3, r2
|
|
8009af8: 009b lsls r3, r3, #2
|
|
8009afa: 4413 add r3, r2
|
|
8009afc: 00db lsls r3, r3, #3
|
|
8009afe: 440b add r3, r1
|
|
8009b00: f503 73b6 add.w r3, r3, #364 @ 0x16c
|
|
8009b04: 681b ldr r3, [r3, #0]
|
|
}
|
|
8009b06: 4618 mov r0, r3
|
|
8009b08: 370c adds r7, #12
|
|
8009b0a: 46bd mov sp, r7
|
|
8009b0c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009b10: 4770 bx lr
|
|
|
|
08009b12 <HAL_PCD_EP_Transmit>:
|
|
* @param pBuf pointer to the transmission buffer
|
|
* @param len amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
|
|
{
|
|
8009b12: b580 push {r7, lr}
|
|
8009b14: b086 sub sp, #24
|
|
8009b16: af00 add r7, sp, #0
|
|
8009b18: 60f8 str r0, [r7, #12]
|
|
8009b1a: 607a str r2, [r7, #4]
|
|
8009b1c: 603b str r3, [r7, #0]
|
|
8009b1e: 460b mov r3, r1
|
|
8009b20: 72fb strb r3, [r7, #11]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8009b22: 7afb ldrb r3, [r7, #11]
|
|
8009b24: f003 0207 and.w r2, r3, #7
|
|
8009b28: 4613 mov r3, r2
|
|
8009b2a: 009b lsls r3, r3, #2
|
|
8009b2c: 4413 add r3, r2
|
|
8009b2e: 00db lsls r3, r3, #3
|
|
8009b30: 3310 adds r3, #16
|
|
8009b32: 68fa ldr r2, [r7, #12]
|
|
8009b34: 4413 add r3, r2
|
|
8009b36: 617b str r3, [r7, #20]
|
|
|
|
/*setup and start the Xfer */
|
|
ep->xfer_buff = pBuf;
|
|
8009b38: 697b ldr r3, [r7, #20]
|
|
8009b3a: 687a ldr r2, [r7, #4]
|
|
8009b3c: 615a str r2, [r3, #20]
|
|
ep->xfer_len = len;
|
|
8009b3e: 697b ldr r3, [r7, #20]
|
|
8009b40: 683a ldr r2, [r7, #0]
|
|
8009b42: 619a str r2, [r3, #24]
|
|
ep->xfer_fill_db = 1U;
|
|
8009b44: 697b ldr r3, [r7, #20]
|
|
8009b46: 2201 movs r2, #1
|
|
8009b48: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
ep->xfer_len_db = len;
|
|
8009b4c: 697b ldr r3, [r7, #20]
|
|
8009b4e: 683a ldr r2, [r7, #0]
|
|
8009b50: 621a str r2, [r3, #32]
|
|
ep->xfer_count = 0U;
|
|
8009b52: 697b ldr r3, [r7, #20]
|
|
8009b54: 2200 movs r2, #0
|
|
8009b56: 61da str r2, [r3, #28]
|
|
ep->is_in = 1U;
|
|
8009b58: 697b ldr r3, [r7, #20]
|
|
8009b5a: 2201 movs r2, #1
|
|
8009b5c: 705a strb r2, [r3, #1]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8009b5e: 7afb ldrb r3, [r7, #11]
|
|
8009b60: f003 0307 and.w r3, r3, #7
|
|
8009b64: b2da uxtb r2, r3
|
|
8009b66: 697b ldr r3, [r7, #20]
|
|
8009b68: 701a strb r2, [r3, #0]
|
|
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
|
8009b6a: 68fb ldr r3, [r7, #12]
|
|
8009b6c: 681b ldr r3, [r3, #0]
|
|
8009b6e: 6979 ldr r1, [r7, #20]
|
|
8009b70: 4618 mov r0, r3
|
|
8009b72: f006 fa4e bl 8010012 <USB_EPStartXfer>
|
|
|
|
return HAL_OK;
|
|
8009b76: 2300 movs r3, #0
|
|
}
|
|
8009b78: 4618 mov r0, r3
|
|
8009b7a: 3718 adds r7, #24
|
|
8009b7c: 46bd mov sp, r7
|
|
8009b7e: bd80 pop {r7, pc}
|
|
|
|
08009b80 <HAL_PCD_EP_SetStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8009b80: b580 push {r7, lr}
|
|
8009b82: b084 sub sp, #16
|
|
8009b84: af00 add r7, sp, #0
|
|
8009b86: 6078 str r0, [r7, #4]
|
|
8009b88: 460b mov r3, r1
|
|
8009b8a: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
|
|
8009b8c: 78fb ldrb r3, [r7, #3]
|
|
8009b8e: f003 0307 and.w r3, r3, #7
|
|
8009b92: 687a ldr r2, [r7, #4]
|
|
8009b94: 7912 ldrb r2, [r2, #4]
|
|
8009b96: 4293 cmp r3, r2
|
|
8009b98: d901 bls.n 8009b9e <HAL_PCD_EP_SetStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8009b9a: 2301 movs r3, #1
|
|
8009b9c: e03e b.n 8009c1c <HAL_PCD_EP_SetStall+0x9c>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8009b9e: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8009ba2: 2b00 cmp r3, #0
|
|
8009ba4: da0e bge.n 8009bc4 <HAL_PCD_EP_SetStall+0x44>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8009ba6: 78fb ldrb r3, [r7, #3]
|
|
8009ba8: f003 0207 and.w r2, r3, #7
|
|
8009bac: 4613 mov r3, r2
|
|
8009bae: 009b lsls r3, r3, #2
|
|
8009bb0: 4413 add r3, r2
|
|
8009bb2: 00db lsls r3, r3, #3
|
|
8009bb4: 3310 adds r3, #16
|
|
8009bb6: 687a ldr r2, [r7, #4]
|
|
8009bb8: 4413 add r3, r2
|
|
8009bba: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8009bbc: 68fb ldr r3, [r7, #12]
|
|
8009bbe: 2201 movs r2, #1
|
|
8009bc0: 705a strb r2, [r3, #1]
|
|
8009bc2: e00c b.n 8009bde <HAL_PCD_EP_SetStall+0x5e>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
8009bc4: 78fa ldrb r2, [r7, #3]
|
|
8009bc6: 4613 mov r3, r2
|
|
8009bc8: 009b lsls r3, r3, #2
|
|
8009bca: 4413 add r3, r2
|
|
8009bcc: 00db lsls r3, r3, #3
|
|
8009bce: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009bd2: 687a ldr r2, [r7, #4]
|
|
8009bd4: 4413 add r3, r2
|
|
8009bd6: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8009bd8: 68fb ldr r3, [r7, #12]
|
|
8009bda: 2200 movs r2, #0
|
|
8009bdc: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 1U;
|
|
8009bde: 68fb ldr r3, [r7, #12]
|
|
8009be0: 2201 movs r2, #1
|
|
8009be2: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8009be4: 78fb ldrb r3, [r7, #3]
|
|
8009be6: f003 0307 and.w r3, r3, #7
|
|
8009bea: b2da uxtb r2, r3
|
|
8009bec: 68fb ldr r3, [r7, #12]
|
|
8009bee: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8009bf0: 687b ldr r3, [r7, #4]
|
|
8009bf2: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
8009bf6: 2b01 cmp r3, #1
|
|
8009bf8: d101 bne.n 8009bfe <HAL_PCD_EP_SetStall+0x7e>
|
|
8009bfa: 2302 movs r3, #2
|
|
8009bfc: e00e b.n 8009c1c <HAL_PCD_EP_SetStall+0x9c>
|
|
8009bfe: 687b ldr r3, [r7, #4]
|
|
8009c00: 2201 movs r2, #1
|
|
8009c02: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
(void)USB_EPSetStall(hpcd->Instance, ep);
|
|
8009c06: 687b ldr r3, [r7, #4]
|
|
8009c08: 681b ldr r3, [r3, #0]
|
|
8009c0a: 68f9 ldr r1, [r7, #12]
|
|
8009c0c: 4618 mov r0, r3
|
|
8009c0e: f006 ffaf bl 8010b70 <USB_EPSetStall>
|
|
|
|
__HAL_UNLOCK(hpcd);
|
|
8009c12: 687b ldr r3, [r7, #4]
|
|
8009c14: 2200 movs r2, #0
|
|
8009c16: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return HAL_OK;
|
|
8009c1a: 2300 movs r3, #0
|
|
}
|
|
8009c1c: 4618 mov r0, r3
|
|
8009c1e: 3710 adds r7, #16
|
|
8009c20: 46bd mov sp, r7
|
|
8009c22: bd80 pop {r7, pc}
|
|
|
|
08009c24 <HAL_PCD_EP_ClrStall>:
|
|
* @param hpcd PCD handle
|
|
* @param ep_addr endpoint address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|
{
|
|
8009c24: b580 push {r7, lr}
|
|
8009c26: b084 sub sp, #16
|
|
8009c28: af00 add r7, sp, #0
|
|
8009c2a: 6078 str r0, [r7, #4]
|
|
8009c2c: 460b mov r3, r1
|
|
8009c2e: 70fb strb r3, [r7, #3]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
|
|
8009c30: 78fb ldrb r3, [r7, #3]
|
|
8009c32: f003 030f and.w r3, r3, #15
|
|
8009c36: 687a ldr r2, [r7, #4]
|
|
8009c38: 7912 ldrb r2, [r2, #4]
|
|
8009c3a: 4293 cmp r3, r2
|
|
8009c3c: d901 bls.n 8009c42 <HAL_PCD_EP_ClrStall+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
8009c3e: 2301 movs r3, #1
|
|
8009c40: e040 b.n 8009cc4 <HAL_PCD_EP_ClrStall+0xa0>
|
|
}
|
|
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
8009c42: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8009c46: 2b00 cmp r3, #0
|
|
8009c48: da0e bge.n 8009c68 <HAL_PCD_EP_ClrStall+0x44>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
8009c4a: 78fb ldrb r3, [r7, #3]
|
|
8009c4c: f003 0207 and.w r2, r3, #7
|
|
8009c50: 4613 mov r3, r2
|
|
8009c52: 009b lsls r3, r3, #2
|
|
8009c54: 4413 add r3, r2
|
|
8009c56: 00db lsls r3, r3, #3
|
|
8009c58: 3310 adds r3, #16
|
|
8009c5a: 687a ldr r2, [r7, #4]
|
|
8009c5c: 4413 add r3, r2
|
|
8009c5e: 60fb str r3, [r7, #12]
|
|
ep->is_in = 1U;
|
|
8009c60: 68fb ldr r3, [r7, #12]
|
|
8009c62: 2201 movs r2, #1
|
|
8009c64: 705a strb r2, [r3, #1]
|
|
8009c66: e00e b.n 8009c86 <HAL_PCD_EP_ClrStall+0x62>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
|
|
8009c68: 78fb ldrb r3, [r7, #3]
|
|
8009c6a: f003 0207 and.w r2, r3, #7
|
|
8009c6e: 4613 mov r3, r2
|
|
8009c70: 009b lsls r3, r3, #2
|
|
8009c72: 4413 add r3, r2
|
|
8009c74: 00db lsls r3, r3, #3
|
|
8009c76: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009c7a: 687a ldr r2, [r7, #4]
|
|
8009c7c: 4413 add r3, r2
|
|
8009c7e: 60fb str r3, [r7, #12]
|
|
ep->is_in = 0U;
|
|
8009c80: 68fb ldr r3, [r7, #12]
|
|
8009c82: 2200 movs r2, #0
|
|
8009c84: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
ep->is_stall = 0U;
|
|
8009c86: 68fb ldr r3, [r7, #12]
|
|
8009c88: 2200 movs r2, #0
|
|
8009c8a: 709a strb r2, [r3, #2]
|
|
ep->num = ep_addr & EP_ADDR_MSK;
|
|
8009c8c: 78fb ldrb r3, [r7, #3]
|
|
8009c8e: f003 0307 and.w r3, r3, #7
|
|
8009c92: b2da uxtb r2, r3
|
|
8009c94: 68fb ldr r3, [r7, #12]
|
|
8009c96: 701a strb r2, [r3, #0]
|
|
|
|
__HAL_LOCK(hpcd);
|
|
8009c98: 687b ldr r3, [r7, #4]
|
|
8009c9a: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
|
|
8009c9e: 2b01 cmp r3, #1
|
|
8009ca0: d101 bne.n 8009ca6 <HAL_PCD_EP_ClrStall+0x82>
|
|
8009ca2: 2302 movs r3, #2
|
|
8009ca4: e00e b.n 8009cc4 <HAL_PCD_EP_ClrStall+0xa0>
|
|
8009ca6: 687b ldr r3, [r7, #4]
|
|
8009ca8: 2201 movs r2, #1
|
|
8009caa: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
(void)USB_EPClearStall(hpcd->Instance, ep);
|
|
8009cae: 687b ldr r3, [r7, #4]
|
|
8009cb0: 681b ldr r3, [r3, #0]
|
|
8009cb2: 68f9 ldr r1, [r7, #12]
|
|
8009cb4: 4618 mov r0, r3
|
|
8009cb6: f006 ffac bl 8010c12 <USB_EPClearStall>
|
|
__HAL_UNLOCK(hpcd);
|
|
8009cba: 687b ldr r3, [r7, #4]
|
|
8009cbc: 2200 movs r2, #0
|
|
8009cbe: f883 2290 strb.w r2, [r3, #656] @ 0x290
|
|
|
|
return HAL_OK;
|
|
8009cc2: 2300 movs r3, #0
|
|
}
|
|
8009cc4: 4618 mov r0, r3
|
|
8009cc6: 3710 adds r7, #16
|
|
8009cc8: 46bd mov sp, r7
|
|
8009cca: bd80 pop {r7, pc}
|
|
|
|
08009ccc <PCD_EP_ISR_Handler>:
|
|
* @brief This function handles PCD Endpoint interrupt request.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
8009ccc: b580 push {r7, lr}
|
|
8009cce: b094 sub sp, #80 @ 0x50
|
|
8009cd0: af00 add r7, sp, #0
|
|
8009cd2: 6078 str r0, [r7, #4]
|
|
#if (USE_USB_DOUBLE_BUFFER != 1U)
|
|
count = 0U;
|
|
#endif /* USE_USB_DOUBLE_BUFFER */
|
|
|
|
/* stay in loop while pending interrupts */
|
|
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
|
|
8009cd4: e374 b.n 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
{
|
|
wIstr = hpcd->Instance->ISTR;
|
|
8009cd6: 687b ldr r3, [r7, #4]
|
|
8009cd8: 681b ldr r3, [r3, #0]
|
|
8009cda: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
8009cde: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
|
|
|
|
/* extract highest priority endpoint number */
|
|
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
|
|
8009ce2: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
|
|
8009ce6: b2db uxtb r3, r3
|
|
8009ce8: f003 030f and.w r3, r3, #15
|
|
8009cec: f887 3041 strb.w r3, [r7, #65] @ 0x41
|
|
|
|
if (epindex == 0U)
|
|
8009cf0: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
|
|
8009cf4: 2b00 cmp r3, #0
|
|
8009cf6: f040 8143 bne.w 8009f80 <PCD_EP_ISR_Handler+0x2b4>
|
|
{
|
|
/* Decode and service control endpoint interrupt */
|
|
|
|
/* DIR bit = origin of the interrupt */
|
|
if ((wIstr & USB_ISTR_DIR) == 0U)
|
|
8009cfa: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
|
|
8009cfe: f003 0310 and.w r3, r3, #16
|
|
8009d02: 2b00 cmp r3, #0
|
|
8009d04: d14c bne.n 8009da0 <PCD_EP_ISR_Handler+0xd4>
|
|
{
|
|
/* DIR = 0 */
|
|
|
|
/* DIR = 0 => IN int */
|
|
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
|
|
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
|
8009d06: 687b ldr r3, [r7, #4]
|
|
8009d08: 681b ldr r3, [r3, #0]
|
|
8009d0a: 881b ldrh r3, [r3, #0]
|
|
8009d0c: b29b uxth r3, r3
|
|
8009d0e: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
|
|
8009d12: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8009d16: 817b strh r3, [r7, #10]
|
|
8009d18: 687b ldr r3, [r7, #4]
|
|
8009d1a: 681a ldr r2, [r3, #0]
|
|
8009d1c: 897b ldrh r3, [r7, #10]
|
|
8009d1e: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8009d22: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8009d26: b29b uxth r3, r3
|
|
8009d28: 8013 strh r3, [r2, #0]
|
|
ep = &hpcd->IN_ep[0];
|
|
8009d2a: 687b ldr r3, [r7, #4]
|
|
8009d2c: 3310 adds r3, #16
|
|
8009d2e: 64bb str r3, [r7, #72] @ 0x48
|
|
|
|
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
|
|
8009d30: 687b ldr r3, [r7, #4]
|
|
8009d32: 681b ldr r3, [r3, #0]
|
|
8009d34: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8009d38: b29b uxth r3, r3
|
|
8009d3a: 461a mov r2, r3
|
|
8009d3c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009d3e: 781b ldrb r3, [r3, #0]
|
|
8009d40: 00db lsls r3, r3, #3
|
|
8009d42: 4413 add r3, r2
|
|
8009d44: 687a ldr r2, [r7, #4]
|
|
8009d46: 6812 ldr r2, [r2, #0]
|
|
8009d48: 4413 add r3, r2
|
|
8009d4a: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
8009d4e: 881b ldrh r3, [r3, #0]
|
|
8009d50: f3c3 0209 ubfx r2, r3, #0, #10
|
|
8009d54: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009d56: 61da str r2, [r3, #28]
|
|
ep->xfer_buff += ep->xfer_count;
|
|
8009d58: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009d5a: 695a ldr r2, [r3, #20]
|
|
8009d5c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009d5e: 69db ldr r3, [r3, #28]
|
|
8009d60: 441a add r2, r3
|
|
8009d62: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009d64: 615a str r2, [r3, #20]
|
|
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, 0U);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, 0U);
|
|
8009d66: 2100 movs r1, #0
|
|
8009d68: 6878 ldr r0, [r7, #4]
|
|
8009d6a: f00f f848 bl 8018dfe <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
|
|
8009d6e: 687b ldr r3, [r7, #4]
|
|
8009d70: 7b1b ldrb r3, [r3, #12]
|
|
8009d72: b2db uxtb r3, r3
|
|
8009d74: 2b00 cmp r3, #0
|
|
8009d76: f000 8323 beq.w 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
8009d7a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009d7c: 699b ldr r3, [r3, #24]
|
|
8009d7e: 2b00 cmp r3, #0
|
|
8009d80: f040 831e bne.w 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
{
|
|
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
|
|
8009d84: 687b ldr r3, [r7, #4]
|
|
8009d86: 7b1b ldrb r3, [r3, #12]
|
|
8009d88: b2db uxtb r3, r3
|
|
8009d8a: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8009d8e: b2da uxtb r2, r3
|
|
8009d90: 687b ldr r3, [r7, #4]
|
|
8009d92: 681b ldr r3, [r3, #0]
|
|
8009d94: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
|
|
hpcd->USB_Address = 0U;
|
|
8009d98: 687b ldr r3, [r7, #4]
|
|
8009d9a: 2200 movs r2, #0
|
|
8009d9c: 731a strb r2, [r3, #12]
|
|
8009d9e: e30f b.n 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
{
|
|
/* DIR = 1 */
|
|
|
|
/* DIR = 1 & CTR_RX => SETUP or OUT int */
|
|
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
|
|
ep = &hpcd->OUT_ep[0];
|
|
8009da0: 687b ldr r3, [r7, #4]
|
|
8009da2: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009da6: 64bb str r3, [r7, #72] @ 0x48
|
|
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
|
|
8009da8: 687b ldr r3, [r7, #4]
|
|
8009daa: 681b ldr r3, [r3, #0]
|
|
8009dac: 881b ldrh r3, [r3, #0]
|
|
8009dae: 87fb strh r3, [r7, #62] @ 0x3e
|
|
|
|
if ((wEPVal & USB_EP_SETUP) != 0U)
|
|
8009db0: 8ffb ldrh r3, [r7, #62] @ 0x3e
|
|
8009db2: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8009db6: 2b00 cmp r3, #0
|
|
8009db8: d07b beq.n 8009eb2 <PCD_EP_ISR_Handler+0x1e6>
|
|
{
|
|
/* Get SETUP Packet */
|
|
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
|
8009dba: 687b ldr r3, [r7, #4]
|
|
8009dbc: 681b ldr r3, [r3, #0]
|
|
8009dbe: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8009dc2: b29b uxth r3, r3
|
|
8009dc4: 461a mov r2, r3
|
|
8009dc6: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009dc8: 781b ldrb r3, [r3, #0]
|
|
8009dca: 00db lsls r3, r3, #3
|
|
8009dcc: 4413 add r3, r2
|
|
8009dce: 687a ldr r2, [r7, #4]
|
|
8009dd0: 6812 ldr r2, [r2, #0]
|
|
8009dd2: 4413 add r3, r2
|
|
8009dd4: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
8009dd8: 881b ldrh r3, [r3, #0]
|
|
8009dda: f3c3 0209 ubfx r2, r3, #0, #10
|
|
8009dde: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009de0: 61da str r2, [r3, #28]
|
|
|
|
if (ep->xfer_count != 8U)
|
|
8009de2: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009de4: 69db ldr r3, [r3, #28]
|
|
8009de6: 2b08 cmp r3, #8
|
|
8009de8: d044 beq.n 8009e74 <PCD_EP_ISR_Handler+0x1a8>
|
|
{
|
|
/* Set Stall condition for EP0 IN/OUT */
|
|
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL);
|
|
8009dea: 687b ldr r3, [r7, #4]
|
|
8009dec: 681b ldr r3, [r3, #0]
|
|
8009dee: 881b ldrh r3, [r3, #0]
|
|
8009df0: b29b uxth r3, r3
|
|
8009df2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8009df6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8009dfa: 823b strh r3, [r7, #16]
|
|
8009dfc: 8a3b ldrh r3, [r7, #16]
|
|
8009dfe: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8009e02: 823b strh r3, [r7, #16]
|
|
8009e04: 687b ldr r3, [r7, #4]
|
|
8009e06: 681a ldr r2, [r3, #0]
|
|
8009e08: 8a3b ldrh r3, [r7, #16]
|
|
8009e0a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8009e0e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8009e12: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8009e16: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8009e1a: b29b uxth r3, r3
|
|
8009e1c: 8013 strh r3, [r2, #0]
|
|
PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL);
|
|
8009e1e: 687b ldr r3, [r7, #4]
|
|
8009e20: 681b ldr r3, [r3, #0]
|
|
8009e22: 881b ldrh r3, [r3, #0]
|
|
8009e24: b29b uxth r3, r3
|
|
8009e26: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8009e2a: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8009e2e: 81fb strh r3, [r7, #14]
|
|
8009e30: 89fb ldrh r3, [r7, #14]
|
|
8009e32: f083 0310 eor.w r3, r3, #16
|
|
8009e36: 81fb strh r3, [r7, #14]
|
|
8009e38: 687b ldr r3, [r7, #4]
|
|
8009e3a: 681a ldr r2, [r3, #0]
|
|
8009e3c: 89fb ldrh r3, [r7, #14]
|
|
8009e3e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8009e42: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8009e46: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8009e4a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8009e4e: b29b uxth r3, r3
|
|
8009e50: 8013 strh r3, [r2, #0]
|
|
|
|
/* SETUP bit kept frozen while CTR_RX = 1 */
|
|
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
|
8009e52: 687b ldr r3, [r7, #4]
|
|
8009e54: 681b ldr r3, [r3, #0]
|
|
8009e56: 881b ldrh r3, [r3, #0]
|
|
8009e58: b29a uxth r2, r3
|
|
8009e5a: f640 738f movw r3, #3983 @ 0xf8f
|
|
8009e5e: 4013 ands r3, r2
|
|
8009e60: 81bb strh r3, [r7, #12]
|
|
8009e62: 687b ldr r3, [r7, #4]
|
|
8009e64: 681b ldr r3, [r3, #0]
|
|
8009e66: 89ba ldrh r2, [r7, #12]
|
|
8009e68: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
8009e6c: b292 uxth r2, r2
|
|
8009e6e: 801a strh r2, [r3, #0]
|
|
|
|
return HAL_OK;
|
|
8009e70: 2300 movs r3, #0
|
|
8009e72: e2af b.n 800a3d4 <PCD_EP_ISR_Handler+0x708>
|
|
}
|
|
|
|
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
|
|
8009e74: 687b ldr r3, [r7, #4]
|
|
8009e76: 6818 ldr r0, [r3, #0]
|
|
8009e78: 687b ldr r3, [r7, #4]
|
|
8009e7a: f503 7126 add.w r1, r3, #664 @ 0x298
|
|
8009e7e: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009e80: 88da ldrh r2, [r3, #6]
|
|
ep->pmaadress, (uint16_t)ep->xfer_count);
|
|
8009e82: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009e84: 69db ldr r3, [r3, #28]
|
|
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
|
|
8009e86: b29b uxth r3, r3
|
|
8009e88: f006 ffea bl 8010e60 <USB_ReadPMA>
|
|
|
|
/* SETUP bit kept frozen while CTR_RX = 1 */
|
|
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
|
8009e8c: 687b ldr r3, [r7, #4]
|
|
8009e8e: 681b ldr r3, [r3, #0]
|
|
8009e90: 881b ldrh r3, [r3, #0]
|
|
8009e92: b29a uxth r2, r3
|
|
8009e94: f640 738f movw r3, #3983 @ 0xf8f
|
|
8009e98: 4013 ands r3, r2
|
|
8009e9a: 827b strh r3, [r7, #18]
|
|
8009e9c: 687b ldr r3, [r7, #4]
|
|
8009e9e: 681b ldr r3, [r3, #0]
|
|
8009ea0: 8a7a ldrh r2, [r7, #18]
|
|
8009ea2: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
8009ea6: b292 uxth r2, r2
|
|
8009ea8: 801a strh r2, [r3, #0]
|
|
|
|
/* Process SETUP Packet*/
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->SetupStageCallback(hpcd);
|
|
#else
|
|
HAL_PCD_SetupStageCallback(hpcd);
|
|
8009eaa: 6878 ldr r0, [r7, #4]
|
|
8009eac: f00e ff7a bl 8018da4 <HAL_PCD_SetupStageCallback>
|
|
8009eb0: e286 b.n 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
|
|
8009eb2: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e
|
|
8009eb6: 2b00 cmp r3, #0
|
|
8009eb8: f280 8282 bge.w 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
{
|
|
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
|
|
8009ebc: 687b ldr r3, [r7, #4]
|
|
8009ebe: 681b ldr r3, [r3, #0]
|
|
8009ec0: 881b ldrh r3, [r3, #0]
|
|
8009ec2: b29a uxth r2, r3
|
|
8009ec4: f640 738f movw r3, #3983 @ 0xf8f
|
|
8009ec8: 4013 ands r3, r2
|
|
8009eca: 82fb strh r3, [r7, #22]
|
|
8009ecc: 687b ldr r3, [r7, #4]
|
|
8009ece: 681b ldr r3, [r3, #0]
|
|
8009ed0: 8afa ldrh r2, [r7, #22]
|
|
8009ed2: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
8009ed6: b292 uxth r2, r2
|
|
8009ed8: 801a strh r2, [r3, #0]
|
|
|
|
/* Get Control Data OUT Packet */
|
|
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
|
8009eda: 687b ldr r3, [r7, #4]
|
|
8009edc: 681b ldr r3, [r3, #0]
|
|
8009ede: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8009ee2: b29b uxth r3, r3
|
|
8009ee4: 461a mov r2, r3
|
|
8009ee6: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009ee8: 781b ldrb r3, [r3, #0]
|
|
8009eea: 00db lsls r3, r3, #3
|
|
8009eec: 4413 add r3, r2
|
|
8009eee: 687a ldr r2, [r7, #4]
|
|
8009ef0: 6812 ldr r2, [r2, #0]
|
|
8009ef2: 4413 add r3, r2
|
|
8009ef4: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
8009ef8: 881b ldrh r3, [r3, #0]
|
|
8009efa: f3c3 0209 ubfx r2, r3, #0, #10
|
|
8009efe: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f00: 61da str r2, [r3, #28]
|
|
|
|
if (ep->xfer_count == 0U)
|
|
8009f02: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f04: 69db ldr r3, [r3, #28]
|
|
8009f06: 2b00 cmp r3, #0
|
|
8009f08: d11e bne.n 8009f48 <PCD_EP_ISR_Handler+0x27c>
|
|
{
|
|
/* Status phase re-arm for next setup */
|
|
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
|
|
8009f0a: 687b ldr r3, [r7, #4]
|
|
8009f0c: 681b ldr r3, [r3, #0]
|
|
8009f0e: 881b ldrh r3, [r3, #0]
|
|
8009f10: b29b uxth r3, r3
|
|
8009f12: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8009f16: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8009f1a: 82bb strh r3, [r7, #20]
|
|
8009f1c: 8abb ldrh r3, [r7, #20]
|
|
8009f1e: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8009f22: 82bb strh r3, [r7, #20]
|
|
8009f24: 8abb ldrh r3, [r7, #20]
|
|
8009f26: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
8009f2a: 82bb strh r3, [r7, #20]
|
|
8009f2c: 687b ldr r3, [r7, #4]
|
|
8009f2e: 681a ldr r2, [r3, #0]
|
|
8009f30: 8abb ldrh r3, [r7, #20]
|
|
8009f32: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8009f36: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8009f3a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8009f3e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8009f42: b29b uxth r3, r3
|
|
8009f44: 8013 strh r3, [r2, #0]
|
|
8009f46: e23b b.n 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
}
|
|
else
|
|
{
|
|
if (ep->xfer_buff != 0U)
|
|
8009f48: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f4a: 695b ldr r3, [r3, #20]
|
|
8009f4c: 2b00 cmp r3, #0
|
|
8009f4e: f000 8237 beq.w 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
|
|
8009f52: 687b ldr r3, [r7, #4]
|
|
8009f54: 6818 ldr r0, [r3, #0]
|
|
8009f56: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f58: 6959 ldr r1, [r3, #20]
|
|
8009f5a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f5c: 88da ldrh r2, [r3, #6]
|
|
ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */
|
|
8009f5e: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f60: 69db ldr r3, [r3, #28]
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
|
|
8009f62: b29b uxth r3, r3
|
|
8009f64: f006 ff7c bl 8010e60 <USB_ReadPMA>
|
|
|
|
ep->xfer_buff += ep->xfer_count;
|
|
8009f68: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f6a: 695a ldr r2, [r3, #20]
|
|
8009f6c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f6e: 69db ldr r3, [r3, #28]
|
|
8009f70: 441a add r2, r3
|
|
8009f72: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009f74: 615a str r2, [r3, #20]
|
|
|
|
/* Process Control Data OUT Packet */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, 0U);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, 0U);
|
|
8009f76: 2100 movs r1, #0
|
|
8009f78: 6878 ldr r0, [r7, #4]
|
|
8009f7a: f00e ff25 bl 8018dc8 <HAL_PCD_DataOutStageCallback>
|
|
8009f7e: e21f b.n 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
}
|
|
else
|
|
{
|
|
/* Decode and service non control endpoints interrupt */
|
|
/* process related endpoint register */
|
|
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
|
|
8009f80: 687b ldr r3, [r7, #4]
|
|
8009f82: 681b ldr r3, [r3, #0]
|
|
8009f84: 461a mov r2, r3
|
|
8009f86: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
|
|
8009f8a: 009b lsls r3, r3, #2
|
|
8009f8c: 4413 add r3, r2
|
|
8009f8e: 881b ldrh r3, [r3, #0]
|
|
8009f90: 87fb strh r3, [r7, #62] @ 0x3e
|
|
|
|
if ((wEPVal & USB_EP_CTR_RX) != 0U)
|
|
8009f92: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e
|
|
8009f96: 2b00 cmp r3, #0
|
|
8009f98: f280 80f5 bge.w 800a186 <PCD_EP_ISR_Handler+0x4ba>
|
|
{
|
|
/* clear int flag */
|
|
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
|
|
8009f9c: 687b ldr r3, [r7, #4]
|
|
8009f9e: 681b ldr r3, [r3, #0]
|
|
8009fa0: 461a mov r2, r3
|
|
8009fa2: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
|
|
8009fa6: 009b lsls r3, r3, #2
|
|
8009fa8: 4413 add r3, r2
|
|
8009faa: 881b ldrh r3, [r3, #0]
|
|
8009fac: b29a uxth r2, r3
|
|
8009fae: f640 738f movw r3, #3983 @ 0xf8f
|
|
8009fb2: 4013 ands r3, r2
|
|
8009fb4: f8a7 3046 strh.w r3, [r7, #70] @ 0x46
|
|
8009fb8: 687b ldr r3, [r7, #4]
|
|
8009fba: 681b ldr r3, [r3, #0]
|
|
8009fbc: 461a mov r2, r3
|
|
8009fbe: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
|
|
8009fc2: 009b lsls r3, r3, #2
|
|
8009fc4: 4413 add r3, r2
|
|
8009fc6: f8b7 2046 ldrh.w r2, [r7, #70] @ 0x46
|
|
8009fca: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
8009fce: b292 uxth r2, r2
|
|
8009fd0: 801a strh r2, [r3, #0]
|
|
ep = &hpcd->OUT_ep[epindex];
|
|
8009fd2: f897 2041 ldrb.w r2, [r7, #65] @ 0x41
|
|
8009fd6: 4613 mov r3, r2
|
|
8009fd8: 009b lsls r3, r3, #2
|
|
8009fda: 4413 add r3, r2
|
|
8009fdc: 00db lsls r3, r3, #3
|
|
8009fde: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8009fe2: 687a ldr r2, [r7, #4]
|
|
8009fe4: 4413 add r3, r2
|
|
8009fe6: 64bb str r3, [r7, #72] @ 0x48
|
|
|
|
/* OUT Single Buffering */
|
|
if (ep->doublebuffer == 0U)
|
|
8009fe8: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009fea: 7b1b ldrb r3, [r3, #12]
|
|
8009fec: 2b00 cmp r3, #0
|
|
8009fee: d123 bne.n 800a038 <PCD_EP_ISR_Handler+0x36c>
|
|
{
|
|
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
|
|
8009ff0: 687b ldr r3, [r7, #4]
|
|
8009ff2: 681b ldr r3, [r3, #0]
|
|
8009ff4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8009ff8: b29b uxth r3, r3
|
|
8009ffa: 461a mov r2, r3
|
|
8009ffc: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8009ffe: 781b ldrb r3, [r3, #0]
|
|
800a000: 00db lsls r3, r3, #3
|
|
800a002: 4413 add r3, r2
|
|
800a004: 687a ldr r2, [r7, #4]
|
|
800a006: 6812 ldr r2, [r2, #0]
|
|
800a008: 4413 add r3, r2
|
|
800a00a: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800a00e: 881b ldrh r3, [r3, #0]
|
|
800a010: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a014: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
|
|
|
|
if (count != 0U)
|
|
800a018: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a01c: 2b00 cmp r3, #0
|
|
800a01e: f000 808d beq.w 800a13c <PCD_EP_ISR_Handler+0x470>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
|
|
800a022: 687b ldr r3, [r7, #4]
|
|
800a024: 6818 ldr r0, [r3, #0]
|
|
800a026: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a028: 6959 ldr r1, [r3, #20]
|
|
800a02a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a02c: 88da ldrh r2, [r3, #6]
|
|
800a02e: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a032: f006 ff15 bl 8010e60 <USB_ReadPMA>
|
|
800a036: e081 b.n 800a13c <PCD_EP_ISR_Handler+0x470>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
else
|
|
{
|
|
/* manage double buffer bulk out */
|
|
if (ep->type == EP_TYPE_BULK)
|
|
800a038: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a03a: 78db ldrb r3, [r3, #3]
|
|
800a03c: 2b02 cmp r3, #2
|
|
800a03e: d109 bne.n 800a054 <PCD_EP_ISR_Handler+0x388>
|
|
{
|
|
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
|
|
800a040: 8ffb ldrh r3, [r7, #62] @ 0x3e
|
|
800a042: 461a mov r2, r3
|
|
800a044: 6cb9 ldr r1, [r7, #72] @ 0x48
|
|
800a046: 6878 ldr r0, [r7, #4]
|
|
800a048: f000 f9c8 bl 800a3dc <HAL_PCD_EP_DB_Receive>
|
|
800a04c: 4603 mov r3, r0
|
|
800a04e: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
|
|
800a052: e073 b.n 800a13c <PCD_EP_ISR_Handler+0x470>
|
|
}
|
|
else /* manage double buffer iso out */
|
|
{
|
|
/* free EP OUT Buffer */
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
|
|
800a054: 687b ldr r3, [r7, #4]
|
|
800a056: 681b ldr r3, [r3, #0]
|
|
800a058: 461a mov r2, r3
|
|
800a05a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a05c: 781b ldrb r3, [r3, #0]
|
|
800a05e: 009b lsls r3, r3, #2
|
|
800a060: 4413 add r3, r2
|
|
800a062: 881b ldrh r3, [r3, #0]
|
|
800a064: b29b uxth r3, r3
|
|
800a066: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800a06a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800a06e: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
|
|
800a072: 687b ldr r3, [r7, #4]
|
|
800a074: 681b ldr r3, [r3, #0]
|
|
800a076: 461a mov r2, r3
|
|
800a078: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a07a: 781b ldrb r3, [r3, #0]
|
|
800a07c: 009b lsls r3, r3, #2
|
|
800a07e: 441a add r2, r3
|
|
800a080: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
|
|
800a084: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800a088: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800a08c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800a090: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800a094: b29b uxth r3, r3
|
|
800a096: 8013 strh r3, [r2, #0]
|
|
|
|
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
|
|
800a098: 687b ldr r3, [r7, #4]
|
|
800a09a: 681b ldr r3, [r3, #0]
|
|
800a09c: 461a mov r2, r3
|
|
800a09e: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a0a0: 781b ldrb r3, [r3, #0]
|
|
800a0a2: 009b lsls r3, r3, #2
|
|
800a0a4: 4413 add r3, r2
|
|
800a0a6: 881b ldrh r3, [r3, #0]
|
|
800a0a8: b29b uxth r3, r3
|
|
800a0aa: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800a0ae: 2b00 cmp r3, #0
|
|
800a0b0: d022 beq.n 800a0f8 <PCD_EP_ISR_Handler+0x42c>
|
|
{
|
|
/* read from endpoint BUF0Addr buffer */
|
|
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
|
800a0b2: 687b ldr r3, [r7, #4]
|
|
800a0b4: 681b ldr r3, [r3, #0]
|
|
800a0b6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a0ba: b29b uxth r3, r3
|
|
800a0bc: 461a mov r2, r3
|
|
800a0be: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a0c0: 781b ldrb r3, [r3, #0]
|
|
800a0c2: 00db lsls r3, r3, #3
|
|
800a0c4: 4413 add r3, r2
|
|
800a0c6: 687a ldr r2, [r7, #4]
|
|
800a0c8: 6812 ldr r2, [r2, #0]
|
|
800a0ca: 4413 add r3, r2
|
|
800a0cc: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a0d0: 881b ldrh r3, [r3, #0]
|
|
800a0d2: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a0d6: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
|
|
|
|
if (count != 0U)
|
|
800a0da: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a0de: 2b00 cmp r3, #0
|
|
800a0e0: d02c beq.n 800a13c <PCD_EP_ISR_Handler+0x470>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
|
|
800a0e2: 687b ldr r3, [r7, #4]
|
|
800a0e4: 6818 ldr r0, [r3, #0]
|
|
800a0e6: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a0e8: 6959 ldr r1, [r3, #20]
|
|
800a0ea: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a0ec: 891a ldrh r2, [r3, #8]
|
|
800a0ee: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a0f2: f006 feb5 bl 8010e60 <USB_ReadPMA>
|
|
800a0f6: e021 b.n 800a13c <PCD_EP_ISR_Handler+0x470>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* read from endpoint BUF1Addr buffer */
|
|
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
|
800a0f8: 687b ldr r3, [r7, #4]
|
|
800a0fa: 681b ldr r3, [r3, #0]
|
|
800a0fc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a100: b29b uxth r3, r3
|
|
800a102: 461a mov r2, r3
|
|
800a104: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a106: 781b ldrb r3, [r3, #0]
|
|
800a108: 00db lsls r3, r3, #3
|
|
800a10a: 4413 add r3, r2
|
|
800a10c: 687a ldr r2, [r7, #4]
|
|
800a10e: 6812 ldr r2, [r2, #0]
|
|
800a110: 4413 add r3, r2
|
|
800a112: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800a116: 881b ldrh r3, [r3, #0]
|
|
800a118: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a11c: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
|
|
|
|
if (count != 0U)
|
|
800a120: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a124: 2b00 cmp r3, #0
|
|
800a126: d009 beq.n 800a13c <PCD_EP_ISR_Handler+0x470>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
|
|
800a128: 687b ldr r3, [r7, #4]
|
|
800a12a: 6818 ldr r0, [r3, #0]
|
|
800a12c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a12e: 6959 ldr r1, [r3, #20]
|
|
800a130: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a132: 895a ldrh r2, [r3, #10]
|
|
800a134: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a138: f006 fe92 bl 8010e60 <USB_ReadPMA>
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
/* multi-packet on the NON control OUT endpoint */
|
|
ep->xfer_count += count;
|
|
800a13c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a13e: 69da ldr r2, [r3, #28]
|
|
800a140: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a144: 441a add r2, r3
|
|
800a146: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a148: 61da str r2, [r3, #28]
|
|
|
|
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
|
|
800a14a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a14c: 699b ldr r3, [r3, #24]
|
|
800a14e: 2b00 cmp r3, #0
|
|
800a150: d005 beq.n 800a15e <PCD_EP_ISR_Handler+0x492>
|
|
800a152: f8b7 204e ldrh.w r2, [r7, #78] @ 0x4e
|
|
800a156: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a158: 691b ldr r3, [r3, #16]
|
|
800a15a: 429a cmp r2, r3
|
|
800a15c: d206 bcs.n 800a16c <PCD_EP_ISR_Handler+0x4a0>
|
|
{
|
|
/* RX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataOutStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
|
|
800a15e: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a160: 781b ldrb r3, [r3, #0]
|
|
800a162: 4619 mov r1, r3
|
|
800a164: 6878 ldr r0, [r7, #4]
|
|
800a166: f00e fe2f bl 8018dc8 <HAL_PCD_DataOutStageCallback>
|
|
800a16a: e00c b.n 800a186 <PCD_EP_ISR_Handler+0x4ba>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_buff += count;
|
|
800a16c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a16e: 695a ldr r2, [r3, #20]
|
|
800a170: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a174: 441a add r2, r3
|
|
800a176: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a178: 615a str r2, [r3, #20]
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
|
800a17a: 687b ldr r3, [r7, #4]
|
|
800a17c: 681b ldr r3, [r3, #0]
|
|
800a17e: 6cb9 ldr r1, [r7, #72] @ 0x48
|
|
800a180: 4618 mov r0, r3
|
|
800a182: f005 ff46 bl 8010012 <USB_EPStartXfer>
|
|
}
|
|
}
|
|
|
|
if ((wEPVal & USB_EP_CTR_TX) != 0U)
|
|
800a186: 8ffb ldrh r3, [r7, #62] @ 0x3e
|
|
800a188: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800a18c: 2b00 cmp r3, #0
|
|
800a18e: f000 8117 beq.w 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
{
|
|
ep = &hpcd->IN_ep[epindex];
|
|
800a192: f897 2041 ldrb.w r2, [r7, #65] @ 0x41
|
|
800a196: 4613 mov r3, r2
|
|
800a198: 009b lsls r3, r3, #2
|
|
800a19a: 4413 add r3, r2
|
|
800a19c: 00db lsls r3, r3, #3
|
|
800a19e: 3310 adds r3, #16
|
|
800a1a0: 687a ldr r2, [r7, #4]
|
|
800a1a2: 4413 add r3, r2
|
|
800a1a4: 64bb str r3, [r7, #72] @ 0x48
|
|
|
|
/* clear int flag */
|
|
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
|
|
800a1a6: 687b ldr r3, [r7, #4]
|
|
800a1a8: 681b ldr r3, [r3, #0]
|
|
800a1aa: 461a mov r2, r3
|
|
800a1ac: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
|
|
800a1b0: 009b lsls r3, r3, #2
|
|
800a1b2: 4413 add r3, r2
|
|
800a1b4: 881b ldrh r3, [r3, #0]
|
|
800a1b6: b29b uxth r3, r3
|
|
800a1b8: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
|
|
800a1bc: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800a1c0: 87bb strh r3, [r7, #60] @ 0x3c
|
|
800a1c2: 687b ldr r3, [r7, #4]
|
|
800a1c4: 681b ldr r3, [r3, #0]
|
|
800a1c6: 461a mov r2, r3
|
|
800a1c8: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
|
|
800a1cc: 009b lsls r3, r3, #2
|
|
800a1ce: 441a add r2, r3
|
|
800a1d0: 8fbb ldrh r3, [r7, #60] @ 0x3c
|
|
800a1d2: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800a1d6: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800a1da: b29b uxth r3, r3
|
|
800a1dc: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->type == EP_TYPE_ISOC)
|
|
800a1de: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a1e0: 78db ldrb r3, [r3, #3]
|
|
800a1e2: 2b01 cmp r3, #1
|
|
800a1e4: f040 80a1 bne.w 800a32a <PCD_EP_ISR_Handler+0x65e>
|
|
{
|
|
ep->xfer_len = 0U;
|
|
800a1e8: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a1ea: 2200 movs r2, #0
|
|
800a1ec: 619a str r2, [r3, #24]
|
|
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
if (ep->doublebuffer != 0U)
|
|
800a1ee: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a1f0: 7b1b ldrb r3, [r3, #12]
|
|
800a1f2: 2b00 cmp r3, #0
|
|
800a1f4: f000 8092 beq.w 800a31c <PCD_EP_ISR_Handler+0x650>
|
|
{
|
|
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
|
800a1f8: 8ffb ldrh r3, [r7, #62] @ 0x3e
|
|
800a1fa: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800a1fe: 2b00 cmp r3, #0
|
|
800a200: d046 beq.n 800a290 <PCD_EP_ISR_Handler+0x5c4>
|
|
{
|
|
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
800a202: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a204: 785b ldrb r3, [r3, #1]
|
|
800a206: 2b00 cmp r3, #0
|
|
800a208: d126 bne.n 800a258 <PCD_EP_ISR_Handler+0x58c>
|
|
800a20a: 687b ldr r3, [r7, #4]
|
|
800a20c: 681b ldr r3, [r3, #0]
|
|
800a20e: 61fb str r3, [r7, #28]
|
|
800a210: 687b ldr r3, [r7, #4]
|
|
800a212: 681b ldr r3, [r3, #0]
|
|
800a214: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a218: b29b uxth r3, r3
|
|
800a21a: 461a mov r2, r3
|
|
800a21c: 69fb ldr r3, [r7, #28]
|
|
800a21e: 4413 add r3, r2
|
|
800a220: 61fb str r3, [r7, #28]
|
|
800a222: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a224: 781b ldrb r3, [r3, #0]
|
|
800a226: 00da lsls r2, r3, #3
|
|
800a228: 69fb ldr r3, [r7, #28]
|
|
800a22a: 4413 add r3, r2
|
|
800a22c: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a230: 61bb str r3, [r7, #24]
|
|
800a232: 69bb ldr r3, [r7, #24]
|
|
800a234: 881b ldrh r3, [r3, #0]
|
|
800a236: b29b uxth r3, r3
|
|
800a238: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a23c: b29a uxth r2, r3
|
|
800a23e: 69bb ldr r3, [r7, #24]
|
|
800a240: 801a strh r2, [r3, #0]
|
|
800a242: 69bb ldr r3, [r7, #24]
|
|
800a244: 881b ldrh r3, [r3, #0]
|
|
800a246: b29b uxth r3, r3
|
|
800a248: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800a24c: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800a250: b29a uxth r2, r3
|
|
800a252: 69bb ldr r3, [r7, #24]
|
|
800a254: 801a strh r2, [r3, #0]
|
|
800a256: e061 b.n 800a31c <PCD_EP_ISR_Handler+0x650>
|
|
800a258: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a25a: 785b ldrb r3, [r3, #1]
|
|
800a25c: 2b01 cmp r3, #1
|
|
800a25e: d15d bne.n 800a31c <PCD_EP_ISR_Handler+0x650>
|
|
800a260: 687b ldr r3, [r7, #4]
|
|
800a262: 681b ldr r3, [r3, #0]
|
|
800a264: 627b str r3, [r7, #36] @ 0x24
|
|
800a266: 687b ldr r3, [r7, #4]
|
|
800a268: 681b ldr r3, [r3, #0]
|
|
800a26a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a26e: b29b uxth r3, r3
|
|
800a270: 461a mov r2, r3
|
|
800a272: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a274: 4413 add r3, r2
|
|
800a276: 627b str r3, [r7, #36] @ 0x24
|
|
800a278: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a27a: 781b ldrb r3, [r3, #0]
|
|
800a27c: 00da lsls r2, r3, #3
|
|
800a27e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a280: 4413 add r3, r2
|
|
800a282: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a286: 623b str r3, [r7, #32]
|
|
800a288: 6a3b ldr r3, [r7, #32]
|
|
800a28a: 2200 movs r2, #0
|
|
800a28c: 801a strh r2, [r3, #0]
|
|
800a28e: e045 b.n 800a31c <PCD_EP_ISR_Handler+0x650>
|
|
}
|
|
else
|
|
{
|
|
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
800a290: 687b ldr r3, [r7, #4]
|
|
800a292: 681b ldr r3, [r3, #0]
|
|
800a294: 637b str r3, [r7, #52] @ 0x34
|
|
800a296: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a298: 785b ldrb r3, [r3, #1]
|
|
800a29a: 2b00 cmp r3, #0
|
|
800a29c: d126 bne.n 800a2ec <PCD_EP_ISR_Handler+0x620>
|
|
800a29e: 687b ldr r3, [r7, #4]
|
|
800a2a0: 681b ldr r3, [r3, #0]
|
|
800a2a2: 62fb str r3, [r7, #44] @ 0x2c
|
|
800a2a4: 687b ldr r3, [r7, #4]
|
|
800a2a6: 681b ldr r3, [r3, #0]
|
|
800a2a8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a2ac: b29b uxth r3, r3
|
|
800a2ae: 461a mov r2, r3
|
|
800a2b0: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a2b2: 4413 add r3, r2
|
|
800a2b4: 62fb str r3, [r7, #44] @ 0x2c
|
|
800a2b6: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a2b8: 781b ldrb r3, [r3, #0]
|
|
800a2ba: 00da lsls r2, r3, #3
|
|
800a2bc: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a2be: 4413 add r3, r2
|
|
800a2c0: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800a2c4: 62bb str r3, [r7, #40] @ 0x28
|
|
800a2c6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800a2c8: 881b ldrh r3, [r3, #0]
|
|
800a2ca: b29b uxth r3, r3
|
|
800a2cc: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a2d0: b29a uxth r2, r3
|
|
800a2d2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800a2d4: 801a strh r2, [r3, #0]
|
|
800a2d6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800a2d8: 881b ldrh r3, [r3, #0]
|
|
800a2da: b29b uxth r3, r3
|
|
800a2dc: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800a2e0: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800a2e4: b29a uxth r2, r3
|
|
800a2e6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800a2e8: 801a strh r2, [r3, #0]
|
|
800a2ea: e017 b.n 800a31c <PCD_EP_ISR_Handler+0x650>
|
|
800a2ec: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a2ee: 785b ldrb r3, [r3, #1]
|
|
800a2f0: 2b01 cmp r3, #1
|
|
800a2f2: d113 bne.n 800a31c <PCD_EP_ISR_Handler+0x650>
|
|
800a2f4: 687b ldr r3, [r7, #4]
|
|
800a2f6: 681b ldr r3, [r3, #0]
|
|
800a2f8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a2fc: b29b uxth r3, r3
|
|
800a2fe: 461a mov r2, r3
|
|
800a300: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800a302: 4413 add r3, r2
|
|
800a304: 637b str r3, [r7, #52] @ 0x34
|
|
800a306: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a308: 781b ldrb r3, [r3, #0]
|
|
800a30a: 00da lsls r2, r3, #3
|
|
800a30c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800a30e: 4413 add r3, r2
|
|
800a310: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800a314: 633b str r3, [r7, #48] @ 0x30
|
|
800a316: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a318: 2200 movs r2, #0
|
|
800a31a: 801a strh r2, [r3, #0]
|
|
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
|
800a31c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a31e: 781b ldrb r3, [r3, #0]
|
|
800a320: 4619 mov r1, r3
|
|
800a322: 6878 ldr r0, [r7, #4]
|
|
800a324: f00e fd6b bl 8018dfe <HAL_PCD_DataInStageCallback>
|
|
800a328: e04a b.n 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
/* Manage Single Buffer Transaction */
|
|
if ((wEPVal & USB_EP_KIND) == 0U)
|
|
800a32a: 8ffb ldrh r3, [r7, #62] @ 0x3e
|
|
800a32c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800a330: 2b00 cmp r3, #0
|
|
800a332: d13f bne.n 800a3b4 <PCD_EP_ISR_Handler+0x6e8>
|
|
{
|
|
/* Multi-packet on the NON control IN endpoint */
|
|
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
|
|
800a334: 687b ldr r3, [r7, #4]
|
|
800a336: 681b ldr r3, [r3, #0]
|
|
800a338: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a33c: b29b uxth r3, r3
|
|
800a33e: 461a mov r2, r3
|
|
800a340: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a342: 781b ldrb r3, [r3, #0]
|
|
800a344: 00db lsls r3, r3, #3
|
|
800a346: 4413 add r3, r2
|
|
800a348: 687a ldr r2, [r7, #4]
|
|
800a34a: 6812 ldr r2, [r2, #0]
|
|
800a34c: 4413 add r3, r2
|
|
800a34e: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a352: 881b ldrh r3, [r3, #0]
|
|
800a354: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a358: 877b strh r3, [r7, #58] @ 0x3a
|
|
|
|
if (ep->xfer_len > TxPctSize)
|
|
800a35a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a35c: 699a ldr r2, [r3, #24]
|
|
800a35e: 8f7b ldrh r3, [r7, #58] @ 0x3a
|
|
800a360: 429a cmp r2, r3
|
|
800a362: d906 bls.n 800a372 <PCD_EP_ISR_Handler+0x6a6>
|
|
{
|
|
ep->xfer_len -= TxPctSize;
|
|
800a364: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a366: 699a ldr r2, [r3, #24]
|
|
800a368: 8f7b ldrh r3, [r7, #58] @ 0x3a
|
|
800a36a: 1ad2 subs r2, r2, r3
|
|
800a36c: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a36e: 619a str r2, [r3, #24]
|
|
800a370: e002 b.n 800a378 <PCD_EP_ISR_Handler+0x6ac>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
800a372: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a374: 2200 movs r2, #0
|
|
800a376: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Zero Length Packet? */
|
|
if (ep->xfer_len == 0U)
|
|
800a378: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a37a: 699b ldr r3, [r3, #24]
|
|
800a37c: 2b00 cmp r3, #0
|
|
800a37e: d106 bne.n 800a38e <PCD_EP_ISR_Handler+0x6c2>
|
|
{
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
|
800a380: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a382: 781b ldrb r3, [r3, #0]
|
|
800a384: 4619 mov r1, r3
|
|
800a386: 6878 ldr r0, [r7, #4]
|
|
800a388: f00e fd39 bl 8018dfe <HAL_PCD_DataInStageCallback>
|
|
800a38c: e018 b.n 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
/* Transfer is not yet Done */
|
|
ep->xfer_buff += TxPctSize;
|
|
800a38e: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a390: 695a ldr r2, [r3, #20]
|
|
800a392: 8f7b ldrh r3, [r7, #58] @ 0x3a
|
|
800a394: 441a add r2, r3
|
|
800a396: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a398: 615a str r2, [r3, #20]
|
|
ep->xfer_count += TxPctSize;
|
|
800a39a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a39c: 69da ldr r2, [r3, #28]
|
|
800a39e: 8f7b ldrh r3, [r7, #58] @ 0x3a
|
|
800a3a0: 441a add r2, r3
|
|
800a3a2: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a3a4: 61da str r2, [r3, #28]
|
|
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
|
800a3a6: 687b ldr r3, [r7, #4]
|
|
800a3a8: 681b ldr r3, [r3, #0]
|
|
800a3aa: 6cb9 ldr r1, [r7, #72] @ 0x48
|
|
800a3ac: 4618 mov r0, r3
|
|
800a3ae: f005 fe30 bl 8010012 <USB_EPStartXfer>
|
|
800a3b2: e005 b.n 800a3c0 <PCD_EP_ISR_Handler+0x6f4>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
/* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
|
|
else
|
|
{
|
|
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
|
|
800a3b4: 8ffb ldrh r3, [r7, #62] @ 0x3e
|
|
800a3b6: 461a mov r2, r3
|
|
800a3b8: 6cb9 ldr r1, [r7, #72] @ 0x48
|
|
800a3ba: 6878 ldr r0, [r7, #4]
|
|
800a3bc: f000 f917 bl 800a5ee <HAL_PCD_EP_DB_Transmit>
|
|
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
|
|
800a3c0: 687b ldr r3, [r7, #4]
|
|
800a3c2: 681b ldr r3, [r3, #0]
|
|
800a3c4: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
800a3c8: b29b uxth r3, r3
|
|
800a3ca: b21b sxth r3, r3
|
|
800a3cc: 2b00 cmp r3, #0
|
|
800a3ce: f6ff ac82 blt.w 8009cd6 <PCD_EP_ISR_Handler+0xa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800a3d2: 2300 movs r3, #0
|
|
}
|
|
800a3d4: 4618 mov r0, r3
|
|
800a3d6: 3750 adds r7, #80 @ 0x50
|
|
800a3d8: 46bd mov sp, r7
|
|
800a3da: bd80 pop {r7, pc}
|
|
|
|
0800a3dc <HAL_PCD_EP_DB_Receive>:
|
|
* @param wEPVal Last snapshot of EPRx register value taken in ISR
|
|
* @retval HAL status
|
|
*/
|
|
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
|
|
PCD_EPTypeDef *ep, uint16_t wEPVal)
|
|
{
|
|
800a3dc: b580 push {r7, lr}
|
|
800a3de: b088 sub sp, #32
|
|
800a3e0: af00 add r7, sp, #0
|
|
800a3e2: 60f8 str r0, [r7, #12]
|
|
800a3e4: 60b9 str r1, [r7, #8]
|
|
800a3e6: 4613 mov r3, r2
|
|
800a3e8: 80fb strh r3, [r7, #6]
|
|
uint16_t count;
|
|
|
|
/* Manage Buffer0 OUT */
|
|
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
|
800a3ea: 88fb ldrh r3, [r7, #6]
|
|
800a3ec: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800a3f0: 2b00 cmp r3, #0
|
|
800a3f2: d07c beq.n 800a4ee <HAL_PCD_EP_DB_Receive+0x112>
|
|
{
|
|
/* Get count of received Data on buffer0 */
|
|
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
|
800a3f4: 68fb ldr r3, [r7, #12]
|
|
800a3f6: 681b ldr r3, [r3, #0]
|
|
800a3f8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a3fc: b29b uxth r3, r3
|
|
800a3fe: 461a mov r2, r3
|
|
800a400: 68bb ldr r3, [r7, #8]
|
|
800a402: 781b ldrb r3, [r3, #0]
|
|
800a404: 00db lsls r3, r3, #3
|
|
800a406: 4413 add r3, r2
|
|
800a408: 68fa ldr r2, [r7, #12]
|
|
800a40a: 6812 ldr r2, [r2, #0]
|
|
800a40c: 4413 add r3, r2
|
|
800a40e: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a412: 881b ldrh r3, [r3, #0]
|
|
800a414: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a418: 837b strh r3, [r7, #26]
|
|
|
|
if (ep->xfer_len >= count)
|
|
800a41a: 68bb ldr r3, [r7, #8]
|
|
800a41c: 699a ldr r2, [r3, #24]
|
|
800a41e: 8b7b ldrh r3, [r7, #26]
|
|
800a420: 429a cmp r2, r3
|
|
800a422: d306 bcc.n 800a432 <HAL_PCD_EP_DB_Receive+0x56>
|
|
{
|
|
ep->xfer_len -= count;
|
|
800a424: 68bb ldr r3, [r7, #8]
|
|
800a426: 699a ldr r2, [r3, #24]
|
|
800a428: 8b7b ldrh r3, [r7, #26]
|
|
800a42a: 1ad2 subs r2, r2, r3
|
|
800a42c: 68bb ldr r3, [r7, #8]
|
|
800a42e: 619a str r2, [r3, #24]
|
|
800a430: e002 b.n 800a438 <HAL_PCD_EP_DB_Receive+0x5c>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
800a432: 68bb ldr r3, [r7, #8]
|
|
800a434: 2200 movs r2, #0
|
|
800a436: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (ep->xfer_len == 0U)
|
|
800a438: 68bb ldr r3, [r7, #8]
|
|
800a43a: 699b ldr r3, [r3, #24]
|
|
800a43c: 2b00 cmp r3, #0
|
|
800a43e: d123 bne.n 800a488 <HAL_PCD_EP_DB_Receive+0xac>
|
|
{
|
|
/* Set NAK to OUT endpoint since double buffer is enabled */
|
|
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
|
|
800a440: 68fb ldr r3, [r7, #12]
|
|
800a442: 681b ldr r3, [r3, #0]
|
|
800a444: 461a mov r2, r3
|
|
800a446: 68bb ldr r3, [r7, #8]
|
|
800a448: 781b ldrb r3, [r3, #0]
|
|
800a44a: 009b lsls r3, r3, #2
|
|
800a44c: 4413 add r3, r2
|
|
800a44e: 881b ldrh r3, [r3, #0]
|
|
800a450: b29b uxth r3, r3
|
|
800a452: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800a456: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800a45a: 833b strh r3, [r7, #24]
|
|
800a45c: 8b3b ldrh r3, [r7, #24]
|
|
800a45e: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
800a462: 833b strh r3, [r7, #24]
|
|
800a464: 68fb ldr r3, [r7, #12]
|
|
800a466: 681b ldr r3, [r3, #0]
|
|
800a468: 461a mov r2, r3
|
|
800a46a: 68bb ldr r3, [r7, #8]
|
|
800a46c: 781b ldrb r3, [r3, #0]
|
|
800a46e: 009b lsls r3, r3, #2
|
|
800a470: 441a add r2, r3
|
|
800a472: 8b3b ldrh r3, [r7, #24]
|
|
800a474: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800a478: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800a47c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800a480: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800a484: b29b uxth r3, r3
|
|
800a486: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Check if Buffer1 is in blocked state which requires to toggle */
|
|
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
|
800a488: 88fb ldrh r3, [r7, #6]
|
|
800a48a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800a48e: 2b00 cmp r3, #0
|
|
800a490: d01f beq.n 800a4d2 <HAL_PCD_EP_DB_Receive+0xf6>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
|
|
800a492: 68fb ldr r3, [r7, #12]
|
|
800a494: 681b ldr r3, [r3, #0]
|
|
800a496: 461a mov r2, r3
|
|
800a498: 68bb ldr r3, [r7, #8]
|
|
800a49a: 781b ldrb r3, [r3, #0]
|
|
800a49c: 009b lsls r3, r3, #2
|
|
800a49e: 4413 add r3, r2
|
|
800a4a0: 881b ldrh r3, [r3, #0]
|
|
800a4a2: b29b uxth r3, r3
|
|
800a4a4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800a4a8: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800a4ac: 82fb strh r3, [r7, #22]
|
|
800a4ae: 68fb ldr r3, [r7, #12]
|
|
800a4b0: 681b ldr r3, [r3, #0]
|
|
800a4b2: 461a mov r2, r3
|
|
800a4b4: 68bb ldr r3, [r7, #8]
|
|
800a4b6: 781b ldrb r3, [r3, #0]
|
|
800a4b8: 009b lsls r3, r3, #2
|
|
800a4ba: 441a add r2, r3
|
|
800a4bc: 8afb ldrh r3, [r7, #22]
|
|
800a4be: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800a4c2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800a4c6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800a4ca: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800a4ce: b29b uxth r3, r3
|
|
800a4d0: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
if (count != 0U)
|
|
800a4d2: 8b7b ldrh r3, [r7, #26]
|
|
800a4d4: 2b00 cmp r3, #0
|
|
800a4d6: f000 8085 beq.w 800a5e4 <HAL_PCD_EP_DB_Receive+0x208>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
|
|
800a4da: 68fb ldr r3, [r7, #12]
|
|
800a4dc: 6818 ldr r0, [r3, #0]
|
|
800a4de: 68bb ldr r3, [r7, #8]
|
|
800a4e0: 6959 ldr r1, [r3, #20]
|
|
800a4e2: 68bb ldr r3, [r7, #8]
|
|
800a4e4: 891a ldrh r2, [r3, #8]
|
|
800a4e6: 8b7b ldrh r3, [r7, #26]
|
|
800a4e8: f006 fcba bl 8010e60 <USB_ReadPMA>
|
|
800a4ec: e07a b.n 800a5e4 <HAL_PCD_EP_DB_Receive+0x208>
|
|
}
|
|
/* Manage Buffer 1 DTOG_RX=0 */
|
|
else
|
|
{
|
|
/* Get count of received data */
|
|
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
|
800a4ee: 68fb ldr r3, [r7, #12]
|
|
800a4f0: 681b ldr r3, [r3, #0]
|
|
800a4f2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a4f6: b29b uxth r3, r3
|
|
800a4f8: 461a mov r2, r3
|
|
800a4fa: 68bb ldr r3, [r7, #8]
|
|
800a4fc: 781b ldrb r3, [r3, #0]
|
|
800a4fe: 00db lsls r3, r3, #3
|
|
800a500: 4413 add r3, r2
|
|
800a502: 68fa ldr r2, [r7, #12]
|
|
800a504: 6812 ldr r2, [r2, #0]
|
|
800a506: 4413 add r3, r2
|
|
800a508: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800a50c: 881b ldrh r3, [r3, #0]
|
|
800a50e: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a512: 837b strh r3, [r7, #26]
|
|
|
|
if (ep->xfer_len >= count)
|
|
800a514: 68bb ldr r3, [r7, #8]
|
|
800a516: 699a ldr r2, [r3, #24]
|
|
800a518: 8b7b ldrh r3, [r7, #26]
|
|
800a51a: 429a cmp r2, r3
|
|
800a51c: d306 bcc.n 800a52c <HAL_PCD_EP_DB_Receive+0x150>
|
|
{
|
|
ep->xfer_len -= count;
|
|
800a51e: 68bb ldr r3, [r7, #8]
|
|
800a520: 699a ldr r2, [r3, #24]
|
|
800a522: 8b7b ldrh r3, [r7, #26]
|
|
800a524: 1ad2 subs r2, r2, r3
|
|
800a526: 68bb ldr r3, [r7, #8]
|
|
800a528: 619a str r2, [r3, #24]
|
|
800a52a: e002 b.n 800a532 <HAL_PCD_EP_DB_Receive+0x156>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
800a52c: 68bb ldr r3, [r7, #8]
|
|
800a52e: 2200 movs r2, #0
|
|
800a530: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
if (ep->xfer_len == 0U)
|
|
800a532: 68bb ldr r3, [r7, #8]
|
|
800a534: 699b ldr r3, [r3, #24]
|
|
800a536: 2b00 cmp r3, #0
|
|
800a538: d123 bne.n 800a582 <HAL_PCD_EP_DB_Receive+0x1a6>
|
|
{
|
|
/* Set NAK on the current endpoint */
|
|
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
|
|
800a53a: 68fb ldr r3, [r7, #12]
|
|
800a53c: 681b ldr r3, [r3, #0]
|
|
800a53e: 461a mov r2, r3
|
|
800a540: 68bb ldr r3, [r7, #8]
|
|
800a542: 781b ldrb r3, [r3, #0]
|
|
800a544: 009b lsls r3, r3, #2
|
|
800a546: 4413 add r3, r2
|
|
800a548: 881b ldrh r3, [r3, #0]
|
|
800a54a: b29b uxth r3, r3
|
|
800a54c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800a550: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800a554: 83fb strh r3, [r7, #30]
|
|
800a556: 8bfb ldrh r3, [r7, #30]
|
|
800a558: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
800a55c: 83fb strh r3, [r7, #30]
|
|
800a55e: 68fb ldr r3, [r7, #12]
|
|
800a560: 681b ldr r3, [r3, #0]
|
|
800a562: 461a mov r2, r3
|
|
800a564: 68bb ldr r3, [r7, #8]
|
|
800a566: 781b ldrb r3, [r3, #0]
|
|
800a568: 009b lsls r3, r3, #2
|
|
800a56a: 441a add r2, r3
|
|
800a56c: 8bfb ldrh r3, [r7, #30]
|
|
800a56e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800a572: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800a576: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800a57a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800a57e: b29b uxth r3, r3
|
|
800a580: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Need to FreeUser Buffer */
|
|
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
|
|
800a582: 88fb ldrh r3, [r7, #6]
|
|
800a584: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800a588: 2b00 cmp r3, #0
|
|
800a58a: d11f bne.n 800a5cc <HAL_PCD_EP_DB_Receive+0x1f0>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
|
|
800a58c: 68fb ldr r3, [r7, #12]
|
|
800a58e: 681b ldr r3, [r3, #0]
|
|
800a590: 461a mov r2, r3
|
|
800a592: 68bb ldr r3, [r7, #8]
|
|
800a594: 781b ldrb r3, [r3, #0]
|
|
800a596: 009b lsls r3, r3, #2
|
|
800a598: 4413 add r3, r2
|
|
800a59a: 881b ldrh r3, [r3, #0]
|
|
800a59c: b29b uxth r3, r3
|
|
800a59e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800a5a2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800a5a6: 83bb strh r3, [r7, #28]
|
|
800a5a8: 68fb ldr r3, [r7, #12]
|
|
800a5aa: 681b ldr r3, [r3, #0]
|
|
800a5ac: 461a mov r2, r3
|
|
800a5ae: 68bb ldr r3, [r7, #8]
|
|
800a5b0: 781b ldrb r3, [r3, #0]
|
|
800a5b2: 009b lsls r3, r3, #2
|
|
800a5b4: 441a add r2, r3
|
|
800a5b6: 8bbb ldrh r3, [r7, #28]
|
|
800a5b8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800a5bc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800a5c0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800a5c4: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800a5c8: b29b uxth r3, r3
|
|
800a5ca: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
if (count != 0U)
|
|
800a5cc: 8b7b ldrh r3, [r7, #26]
|
|
800a5ce: 2b00 cmp r3, #0
|
|
800a5d0: d008 beq.n 800a5e4 <HAL_PCD_EP_DB_Receive+0x208>
|
|
{
|
|
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
|
|
800a5d2: 68fb ldr r3, [r7, #12]
|
|
800a5d4: 6818 ldr r0, [r3, #0]
|
|
800a5d6: 68bb ldr r3, [r7, #8]
|
|
800a5d8: 6959 ldr r1, [r3, #20]
|
|
800a5da: 68bb ldr r3, [r7, #8]
|
|
800a5dc: 895a ldrh r2, [r3, #10]
|
|
800a5de: 8b7b ldrh r3, [r7, #26]
|
|
800a5e0: f006 fc3e bl 8010e60 <USB_ReadPMA>
|
|
}
|
|
}
|
|
|
|
return count;
|
|
800a5e4: 8b7b ldrh r3, [r7, #26]
|
|
}
|
|
800a5e6: 4618 mov r0, r3
|
|
800a5e8: 3720 adds r7, #32
|
|
800a5ea: 46bd mov sp, r7
|
|
800a5ec: bd80 pop {r7, pc}
|
|
|
|
0800a5ee <HAL_PCD_EP_DB_Transmit>:
|
|
* @param wEPVal Last snapshot of EPRx register value taken in ISR
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
|
|
PCD_EPTypeDef *ep, uint16_t wEPVal)
|
|
{
|
|
800a5ee: b580 push {r7, lr}
|
|
800a5f0: b0a6 sub sp, #152 @ 0x98
|
|
800a5f2: af00 add r7, sp, #0
|
|
800a5f4: 60f8 str r0, [r7, #12]
|
|
800a5f6: 60b9 str r1, [r7, #8]
|
|
800a5f8: 4613 mov r3, r2
|
|
800a5fa: 80fb strh r3, [r7, #6]
|
|
uint32_t len;
|
|
uint16_t TxPctSize;
|
|
|
|
/* Data Buffer0 ACK received */
|
|
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
|
800a5fc: 88fb ldrh r3, [r7, #6]
|
|
800a5fe: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800a602: 2b00 cmp r3, #0
|
|
800a604: f000 81f7 beq.w 800a9f6 <HAL_PCD_EP_DB_Transmit+0x408>
|
|
{
|
|
/* multi-packet on the NON control IN endpoint */
|
|
TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
|
800a608: 68fb ldr r3, [r7, #12]
|
|
800a60a: 681b ldr r3, [r3, #0]
|
|
800a60c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a610: b29b uxth r3, r3
|
|
800a612: 461a mov r2, r3
|
|
800a614: 68bb ldr r3, [r7, #8]
|
|
800a616: 781b ldrb r3, [r3, #0]
|
|
800a618: 00db lsls r3, r3, #3
|
|
800a61a: 4413 add r3, r2
|
|
800a61c: 68fa ldr r2, [r7, #12]
|
|
800a61e: 6812 ldr r2, [r2, #0]
|
|
800a620: 4413 add r3, r2
|
|
800a622: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a626: 881b ldrh r3, [r3, #0]
|
|
800a628: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a62c: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
|
|
|
|
if (ep->xfer_len > TxPctSize)
|
|
800a630: 68bb ldr r3, [r7, #8]
|
|
800a632: 699a ldr r2, [r3, #24]
|
|
800a634: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800a638: 429a cmp r2, r3
|
|
800a63a: d907 bls.n 800a64c <HAL_PCD_EP_DB_Transmit+0x5e>
|
|
{
|
|
ep->xfer_len -= TxPctSize;
|
|
800a63c: 68bb ldr r3, [r7, #8]
|
|
800a63e: 699a ldr r2, [r3, #24]
|
|
800a640: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800a644: 1ad2 subs r2, r2, r3
|
|
800a646: 68bb ldr r3, [r7, #8]
|
|
800a648: 619a str r2, [r3, #24]
|
|
800a64a: e002 b.n 800a652 <HAL_PCD_EP_DB_Transmit+0x64>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
800a64c: 68bb ldr r3, [r7, #8]
|
|
800a64e: 2200 movs r2, #0
|
|
800a650: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Transfer is completed */
|
|
if (ep->xfer_len == 0U)
|
|
800a652: 68bb ldr r3, [r7, #8]
|
|
800a654: 699b ldr r3, [r3, #24]
|
|
800a656: 2b00 cmp r3, #0
|
|
800a658: f040 80e1 bne.w 800a81e <HAL_PCD_EP_DB_Transmit+0x230>
|
|
{
|
|
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
800a65c: 68bb ldr r3, [r7, #8]
|
|
800a65e: 785b ldrb r3, [r3, #1]
|
|
800a660: 2b00 cmp r3, #0
|
|
800a662: d126 bne.n 800a6b2 <HAL_PCD_EP_DB_Transmit+0xc4>
|
|
800a664: 68fb ldr r3, [r7, #12]
|
|
800a666: 681b ldr r3, [r3, #0]
|
|
800a668: 633b str r3, [r7, #48] @ 0x30
|
|
800a66a: 68fb ldr r3, [r7, #12]
|
|
800a66c: 681b ldr r3, [r3, #0]
|
|
800a66e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a672: b29b uxth r3, r3
|
|
800a674: 461a mov r2, r3
|
|
800a676: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a678: 4413 add r3, r2
|
|
800a67a: 633b str r3, [r7, #48] @ 0x30
|
|
800a67c: 68bb ldr r3, [r7, #8]
|
|
800a67e: 781b ldrb r3, [r3, #0]
|
|
800a680: 00da lsls r2, r3, #3
|
|
800a682: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a684: 4413 add r3, r2
|
|
800a686: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a68a: 62fb str r3, [r7, #44] @ 0x2c
|
|
800a68c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a68e: 881b ldrh r3, [r3, #0]
|
|
800a690: b29b uxth r3, r3
|
|
800a692: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a696: b29a uxth r2, r3
|
|
800a698: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a69a: 801a strh r2, [r3, #0]
|
|
800a69c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a69e: 881b ldrh r3, [r3, #0]
|
|
800a6a0: b29b uxth r3, r3
|
|
800a6a2: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800a6a6: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800a6aa: b29a uxth r2, r3
|
|
800a6ac: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a6ae: 801a strh r2, [r3, #0]
|
|
800a6b0: e01a b.n 800a6e8 <HAL_PCD_EP_DB_Transmit+0xfa>
|
|
800a6b2: 68bb ldr r3, [r7, #8]
|
|
800a6b4: 785b ldrb r3, [r3, #1]
|
|
800a6b6: 2b01 cmp r3, #1
|
|
800a6b8: d116 bne.n 800a6e8 <HAL_PCD_EP_DB_Transmit+0xfa>
|
|
800a6ba: 68fb ldr r3, [r7, #12]
|
|
800a6bc: 681b ldr r3, [r3, #0]
|
|
800a6be: 63bb str r3, [r7, #56] @ 0x38
|
|
800a6c0: 68fb ldr r3, [r7, #12]
|
|
800a6c2: 681b ldr r3, [r3, #0]
|
|
800a6c4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a6c8: b29b uxth r3, r3
|
|
800a6ca: 461a mov r2, r3
|
|
800a6cc: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800a6ce: 4413 add r3, r2
|
|
800a6d0: 63bb str r3, [r7, #56] @ 0x38
|
|
800a6d2: 68bb ldr r3, [r7, #8]
|
|
800a6d4: 781b ldrb r3, [r3, #0]
|
|
800a6d6: 00da lsls r2, r3, #3
|
|
800a6d8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800a6da: 4413 add r3, r2
|
|
800a6dc: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a6e0: 637b str r3, [r7, #52] @ 0x34
|
|
800a6e2: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800a6e4: 2200 movs r2, #0
|
|
800a6e6: 801a strh r2, [r3, #0]
|
|
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
800a6e8: 68fb ldr r3, [r7, #12]
|
|
800a6ea: 681b ldr r3, [r3, #0]
|
|
800a6ec: 62bb str r3, [r7, #40] @ 0x28
|
|
800a6ee: 68bb ldr r3, [r7, #8]
|
|
800a6f0: 785b ldrb r3, [r3, #1]
|
|
800a6f2: 2b00 cmp r3, #0
|
|
800a6f4: d126 bne.n 800a744 <HAL_PCD_EP_DB_Transmit+0x156>
|
|
800a6f6: 68fb ldr r3, [r7, #12]
|
|
800a6f8: 681b ldr r3, [r3, #0]
|
|
800a6fa: 623b str r3, [r7, #32]
|
|
800a6fc: 68fb ldr r3, [r7, #12]
|
|
800a6fe: 681b ldr r3, [r3, #0]
|
|
800a700: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a704: b29b uxth r3, r3
|
|
800a706: 461a mov r2, r3
|
|
800a708: 6a3b ldr r3, [r7, #32]
|
|
800a70a: 4413 add r3, r2
|
|
800a70c: 623b str r3, [r7, #32]
|
|
800a70e: 68bb ldr r3, [r7, #8]
|
|
800a710: 781b ldrb r3, [r3, #0]
|
|
800a712: 00da lsls r2, r3, #3
|
|
800a714: 6a3b ldr r3, [r7, #32]
|
|
800a716: 4413 add r3, r2
|
|
800a718: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800a71c: 61fb str r3, [r7, #28]
|
|
800a71e: 69fb ldr r3, [r7, #28]
|
|
800a720: 881b ldrh r3, [r3, #0]
|
|
800a722: b29b uxth r3, r3
|
|
800a724: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a728: b29a uxth r2, r3
|
|
800a72a: 69fb ldr r3, [r7, #28]
|
|
800a72c: 801a strh r2, [r3, #0]
|
|
800a72e: 69fb ldr r3, [r7, #28]
|
|
800a730: 881b ldrh r3, [r3, #0]
|
|
800a732: b29b uxth r3, r3
|
|
800a734: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800a738: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800a73c: b29a uxth r2, r3
|
|
800a73e: 69fb ldr r3, [r7, #28]
|
|
800a740: 801a strh r2, [r3, #0]
|
|
800a742: e017 b.n 800a774 <HAL_PCD_EP_DB_Transmit+0x186>
|
|
800a744: 68bb ldr r3, [r7, #8]
|
|
800a746: 785b ldrb r3, [r3, #1]
|
|
800a748: 2b01 cmp r3, #1
|
|
800a74a: d113 bne.n 800a774 <HAL_PCD_EP_DB_Transmit+0x186>
|
|
800a74c: 68fb ldr r3, [r7, #12]
|
|
800a74e: 681b ldr r3, [r3, #0]
|
|
800a750: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a754: b29b uxth r3, r3
|
|
800a756: 461a mov r2, r3
|
|
800a758: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800a75a: 4413 add r3, r2
|
|
800a75c: 62bb str r3, [r7, #40] @ 0x28
|
|
800a75e: 68bb ldr r3, [r7, #8]
|
|
800a760: 781b ldrb r3, [r3, #0]
|
|
800a762: 00da lsls r2, r3, #3
|
|
800a764: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800a766: 4413 add r3, r2
|
|
800a768: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800a76c: 627b str r3, [r7, #36] @ 0x24
|
|
800a76e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a770: 2200 movs r2, #0
|
|
800a772: 801a strh r2, [r3, #0]
|
|
|
|
if (ep->type == EP_TYPE_BULK)
|
|
800a774: 68bb ldr r3, [r7, #8]
|
|
800a776: 78db ldrb r3, [r3, #3]
|
|
800a778: 2b02 cmp r3, #2
|
|
800a77a: d123 bne.n 800a7c4 <HAL_PCD_EP_DB_Transmit+0x1d6>
|
|
{
|
|
/* Set Bulk endpoint in NAK state */
|
|
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
|
|
800a77c: 68fb ldr r3, [r7, #12]
|
|
800a77e: 681b ldr r3, [r3, #0]
|
|
800a780: 461a mov r2, r3
|
|
800a782: 68bb ldr r3, [r7, #8]
|
|
800a784: 781b ldrb r3, [r3, #0]
|
|
800a786: 009b lsls r3, r3, #2
|
|
800a788: 4413 add r3, r2
|
|
800a78a: 881b ldrh r3, [r3, #0]
|
|
800a78c: b29b uxth r3, r3
|
|
800a78e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800a792: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800a796: 837b strh r3, [r7, #26]
|
|
800a798: 8b7b ldrh r3, [r7, #26]
|
|
800a79a: f083 0320 eor.w r3, r3, #32
|
|
800a79e: 837b strh r3, [r7, #26]
|
|
800a7a0: 68fb ldr r3, [r7, #12]
|
|
800a7a2: 681b ldr r3, [r3, #0]
|
|
800a7a4: 461a mov r2, r3
|
|
800a7a6: 68bb ldr r3, [r7, #8]
|
|
800a7a8: 781b ldrb r3, [r3, #0]
|
|
800a7aa: 009b lsls r3, r3, #2
|
|
800a7ac: 441a add r2, r3
|
|
800a7ae: 8b7b ldrh r3, [r7, #26]
|
|
800a7b0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800a7b4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800a7b8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800a7bc: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800a7c0: b29b uxth r3, r3
|
|
800a7c2: 8013 strh r3, [r2, #0]
|
|
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
|
800a7c4: 68bb ldr r3, [r7, #8]
|
|
800a7c6: 781b ldrb r3, [r3, #0]
|
|
800a7c8: 4619 mov r1, r3
|
|
800a7ca: 68f8 ldr r0, [r7, #12]
|
|
800a7cc: f00e fb17 bl 8018dfe <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
|
800a7d0: 88fb ldrh r3, [r7, #6]
|
|
800a7d2: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800a7d6: 2b00 cmp r3, #0
|
|
800a7d8: d01f beq.n 800a81a <HAL_PCD_EP_DB_Transmit+0x22c>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
|
|
800a7da: 68fb ldr r3, [r7, #12]
|
|
800a7dc: 681b ldr r3, [r3, #0]
|
|
800a7de: 461a mov r2, r3
|
|
800a7e0: 68bb ldr r3, [r7, #8]
|
|
800a7e2: 781b ldrb r3, [r3, #0]
|
|
800a7e4: 009b lsls r3, r3, #2
|
|
800a7e6: 4413 add r3, r2
|
|
800a7e8: 881b ldrh r3, [r3, #0]
|
|
800a7ea: b29b uxth r3, r3
|
|
800a7ec: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800a7f0: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800a7f4: 833b strh r3, [r7, #24]
|
|
800a7f6: 68fb ldr r3, [r7, #12]
|
|
800a7f8: 681b ldr r3, [r3, #0]
|
|
800a7fa: 461a mov r2, r3
|
|
800a7fc: 68bb ldr r3, [r7, #8]
|
|
800a7fe: 781b ldrb r3, [r3, #0]
|
|
800a800: 009b lsls r3, r3, #2
|
|
800a802: 441a add r2, r3
|
|
800a804: 8b3b ldrh r3, [r7, #24]
|
|
800a806: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800a80a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800a80e: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800a812: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800a816: b29b uxth r3, r3
|
|
800a818: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
800a81a: 2300 movs r3, #0
|
|
800a81c: e31f b.n 800ae5e <HAL_PCD_EP_DB_Transmit+0x870>
|
|
}
|
|
else /* Transfer is not yet Done */
|
|
{
|
|
/* Need to Free USB Buffer */
|
|
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
|
|
800a81e: 88fb ldrh r3, [r7, #6]
|
|
800a820: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800a824: 2b00 cmp r3, #0
|
|
800a826: d021 beq.n 800a86c <HAL_PCD_EP_DB_Transmit+0x27e>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
|
|
800a828: 68fb ldr r3, [r7, #12]
|
|
800a82a: 681b ldr r3, [r3, #0]
|
|
800a82c: 461a mov r2, r3
|
|
800a82e: 68bb ldr r3, [r7, #8]
|
|
800a830: 781b ldrb r3, [r3, #0]
|
|
800a832: 009b lsls r3, r3, #2
|
|
800a834: 4413 add r3, r2
|
|
800a836: 881b ldrh r3, [r3, #0]
|
|
800a838: b29b uxth r3, r3
|
|
800a83a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800a83e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800a842: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
|
|
800a846: 68fb ldr r3, [r7, #12]
|
|
800a848: 681b ldr r3, [r3, #0]
|
|
800a84a: 461a mov r2, r3
|
|
800a84c: 68bb ldr r3, [r7, #8]
|
|
800a84e: 781b ldrb r3, [r3, #0]
|
|
800a850: 009b lsls r3, r3, #2
|
|
800a852: 441a add r2, r3
|
|
800a854: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
|
|
800a858: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800a85c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800a860: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800a864: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800a868: b29b uxth r3, r3
|
|
800a86a: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Still there is data to Fill in the next Buffer */
|
|
if (ep->xfer_fill_db == 1U)
|
|
800a86c: 68bb ldr r3, [r7, #8]
|
|
800a86e: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
800a872: 2b01 cmp r3, #1
|
|
800a874: f040 82ca bne.w 800ae0c <HAL_PCD_EP_DB_Transmit+0x81e>
|
|
{
|
|
ep->xfer_buff += TxPctSize;
|
|
800a878: 68bb ldr r3, [r7, #8]
|
|
800a87a: 695a ldr r2, [r3, #20]
|
|
800a87c: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800a880: 441a add r2, r3
|
|
800a882: 68bb ldr r3, [r7, #8]
|
|
800a884: 615a str r2, [r3, #20]
|
|
ep->xfer_count += TxPctSize;
|
|
800a886: 68bb ldr r3, [r7, #8]
|
|
800a888: 69da ldr r2, [r3, #28]
|
|
800a88a: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800a88e: 441a add r2, r3
|
|
800a890: 68bb ldr r3, [r7, #8]
|
|
800a892: 61da str r2, [r3, #28]
|
|
|
|
/* Calculate the len of the new buffer to fill */
|
|
if (ep->xfer_len_db >= ep->maxpacket)
|
|
800a894: 68bb ldr r3, [r7, #8]
|
|
800a896: 6a1a ldr r2, [r3, #32]
|
|
800a898: 68bb ldr r3, [r7, #8]
|
|
800a89a: 691b ldr r3, [r3, #16]
|
|
800a89c: 429a cmp r2, r3
|
|
800a89e: d309 bcc.n 800a8b4 <HAL_PCD_EP_DB_Transmit+0x2c6>
|
|
{
|
|
len = ep->maxpacket;
|
|
800a8a0: 68bb ldr r3, [r7, #8]
|
|
800a8a2: 691b ldr r3, [r3, #16]
|
|
800a8a4: 65bb str r3, [r7, #88] @ 0x58
|
|
ep->xfer_len_db -= len;
|
|
800a8a6: 68bb ldr r3, [r7, #8]
|
|
800a8a8: 6a1a ldr r2, [r3, #32]
|
|
800a8aa: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a8ac: 1ad2 subs r2, r2, r3
|
|
800a8ae: 68bb ldr r3, [r7, #8]
|
|
800a8b0: 621a str r2, [r3, #32]
|
|
800a8b2: e015 b.n 800a8e0 <HAL_PCD_EP_DB_Transmit+0x2f2>
|
|
}
|
|
else if (ep->xfer_len_db == 0U)
|
|
800a8b4: 68bb ldr r3, [r7, #8]
|
|
800a8b6: 6a1b ldr r3, [r3, #32]
|
|
800a8b8: 2b00 cmp r3, #0
|
|
800a8ba: d107 bne.n 800a8cc <HAL_PCD_EP_DB_Transmit+0x2de>
|
|
{
|
|
len = TxPctSize;
|
|
800a8bc: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800a8c0: 65bb str r3, [r7, #88] @ 0x58
|
|
ep->xfer_fill_db = 0U;
|
|
800a8c2: 68bb ldr r3, [r7, #8]
|
|
800a8c4: 2200 movs r2, #0
|
|
800a8c6: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
800a8ca: e009 b.n 800a8e0 <HAL_PCD_EP_DB_Transmit+0x2f2>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_fill_db = 0U;
|
|
800a8cc: 68bb ldr r3, [r7, #8]
|
|
800a8ce: 2200 movs r2, #0
|
|
800a8d0: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
len = ep->xfer_len_db;
|
|
800a8d4: 68bb ldr r3, [r7, #8]
|
|
800a8d6: 6a1b ldr r3, [r3, #32]
|
|
800a8d8: 65bb str r3, [r7, #88] @ 0x58
|
|
ep->xfer_len_db = 0U;
|
|
800a8da: 68bb ldr r3, [r7, #8]
|
|
800a8dc: 2200 movs r2, #0
|
|
800a8de: 621a str r2, [r3, #32]
|
|
}
|
|
|
|
/* Write remaining Data to Buffer */
|
|
/* Set the Double buffer counter for pma buffer0 */
|
|
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
|
|
800a8e0: 68bb ldr r3, [r7, #8]
|
|
800a8e2: 785b ldrb r3, [r3, #1]
|
|
800a8e4: 2b00 cmp r3, #0
|
|
800a8e6: d15f bne.n 800a9a8 <HAL_PCD_EP_DB_Transmit+0x3ba>
|
|
800a8e8: 68fb ldr r3, [r7, #12]
|
|
800a8ea: 681b ldr r3, [r3, #0]
|
|
800a8ec: 643b str r3, [r7, #64] @ 0x40
|
|
800a8ee: 68fb ldr r3, [r7, #12]
|
|
800a8f0: 681b ldr r3, [r3, #0]
|
|
800a8f2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a8f6: b29b uxth r3, r3
|
|
800a8f8: 461a mov r2, r3
|
|
800a8fa: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800a8fc: 4413 add r3, r2
|
|
800a8fe: 643b str r3, [r7, #64] @ 0x40
|
|
800a900: 68bb ldr r3, [r7, #8]
|
|
800a902: 781b ldrb r3, [r3, #0]
|
|
800a904: 00da lsls r2, r3, #3
|
|
800a906: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800a908: 4413 add r3, r2
|
|
800a90a: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a90e: 63fb str r3, [r7, #60] @ 0x3c
|
|
800a910: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800a912: 881b ldrh r3, [r3, #0]
|
|
800a914: b29b uxth r3, r3
|
|
800a916: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800a91a: b29a uxth r2, r3
|
|
800a91c: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800a91e: 801a strh r2, [r3, #0]
|
|
800a920: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a922: 2b00 cmp r3, #0
|
|
800a924: d10a bne.n 800a93c <HAL_PCD_EP_DB_Transmit+0x34e>
|
|
800a926: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800a928: 881b ldrh r3, [r3, #0]
|
|
800a92a: b29b uxth r3, r3
|
|
800a92c: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800a930: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800a934: b29a uxth r2, r3
|
|
800a936: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800a938: 801a strh r2, [r3, #0]
|
|
800a93a: e051 b.n 800a9e0 <HAL_PCD_EP_DB_Transmit+0x3f2>
|
|
800a93c: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a93e: 2b3e cmp r3, #62 @ 0x3e
|
|
800a940: d816 bhi.n 800a970 <HAL_PCD_EP_DB_Transmit+0x382>
|
|
800a942: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a944: 085b lsrs r3, r3, #1
|
|
800a946: 653b str r3, [r7, #80] @ 0x50
|
|
800a948: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a94a: f003 0301 and.w r3, r3, #1
|
|
800a94e: 2b00 cmp r3, #0
|
|
800a950: d002 beq.n 800a958 <HAL_PCD_EP_DB_Transmit+0x36a>
|
|
800a952: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800a954: 3301 adds r3, #1
|
|
800a956: 653b str r3, [r7, #80] @ 0x50
|
|
800a958: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800a95a: 881b ldrh r3, [r3, #0]
|
|
800a95c: b29a uxth r2, r3
|
|
800a95e: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800a960: b29b uxth r3, r3
|
|
800a962: 029b lsls r3, r3, #10
|
|
800a964: b29b uxth r3, r3
|
|
800a966: 4313 orrs r3, r2
|
|
800a968: b29a uxth r2, r3
|
|
800a96a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800a96c: 801a strh r2, [r3, #0]
|
|
800a96e: e037 b.n 800a9e0 <HAL_PCD_EP_DB_Transmit+0x3f2>
|
|
800a970: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a972: 095b lsrs r3, r3, #5
|
|
800a974: 653b str r3, [r7, #80] @ 0x50
|
|
800a976: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a978: f003 031f and.w r3, r3, #31
|
|
800a97c: 2b00 cmp r3, #0
|
|
800a97e: d102 bne.n 800a986 <HAL_PCD_EP_DB_Transmit+0x398>
|
|
800a980: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800a982: 3b01 subs r3, #1
|
|
800a984: 653b str r3, [r7, #80] @ 0x50
|
|
800a986: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800a988: 881b ldrh r3, [r3, #0]
|
|
800a98a: b29a uxth r2, r3
|
|
800a98c: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800a98e: b29b uxth r3, r3
|
|
800a990: 029b lsls r3, r3, #10
|
|
800a992: b29b uxth r3, r3
|
|
800a994: 4313 orrs r3, r2
|
|
800a996: b29b uxth r3, r3
|
|
800a998: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800a99c: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800a9a0: b29a uxth r2, r3
|
|
800a9a2: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800a9a4: 801a strh r2, [r3, #0]
|
|
800a9a6: e01b b.n 800a9e0 <HAL_PCD_EP_DB_Transmit+0x3f2>
|
|
800a9a8: 68bb ldr r3, [r7, #8]
|
|
800a9aa: 785b ldrb r3, [r3, #1]
|
|
800a9ac: 2b01 cmp r3, #1
|
|
800a9ae: d117 bne.n 800a9e0 <HAL_PCD_EP_DB_Transmit+0x3f2>
|
|
800a9b0: 68fb ldr r3, [r7, #12]
|
|
800a9b2: 681b ldr r3, [r3, #0]
|
|
800a9b4: 64bb str r3, [r7, #72] @ 0x48
|
|
800a9b6: 68fb ldr r3, [r7, #12]
|
|
800a9b8: 681b ldr r3, [r3, #0]
|
|
800a9ba: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a9be: b29b uxth r3, r3
|
|
800a9c0: 461a mov r2, r3
|
|
800a9c2: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a9c4: 4413 add r3, r2
|
|
800a9c6: 64bb str r3, [r7, #72] @ 0x48
|
|
800a9c8: 68bb ldr r3, [r7, #8]
|
|
800a9ca: 781b ldrb r3, [r3, #0]
|
|
800a9cc: 00da lsls r2, r3, #3
|
|
800a9ce: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800a9d0: 4413 add r3, r2
|
|
800a9d2: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800a9d6: 647b str r3, [r7, #68] @ 0x44
|
|
800a9d8: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a9da: b29a uxth r2, r3
|
|
800a9dc: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800a9de: 801a strh r2, [r3, #0]
|
|
|
|
/* Copy user buffer to USB PMA */
|
|
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
|
|
800a9e0: 68fb ldr r3, [r7, #12]
|
|
800a9e2: 6818 ldr r0, [r3, #0]
|
|
800a9e4: 68bb ldr r3, [r7, #8]
|
|
800a9e6: 6959 ldr r1, [r3, #20]
|
|
800a9e8: 68bb ldr r3, [r7, #8]
|
|
800a9ea: 891a ldrh r2, [r3, #8]
|
|
800a9ec: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800a9ee: b29b uxth r3, r3
|
|
800a9f0: f006 f9f3 bl 8010dda <USB_WritePMA>
|
|
800a9f4: e20a b.n 800ae0c <HAL_PCD_EP_DB_Transmit+0x81e>
|
|
}
|
|
}
|
|
else /* Data Buffer1 ACK received */
|
|
{
|
|
/* multi-packet on the NON control IN endpoint */
|
|
TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
|
|
800a9f6: 68fb ldr r3, [r7, #12]
|
|
800a9f8: 681b ldr r3, [r3, #0]
|
|
800a9fa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800a9fe: b29b uxth r3, r3
|
|
800aa00: 461a mov r2, r3
|
|
800aa02: 68bb ldr r3, [r7, #8]
|
|
800aa04: 781b ldrb r3, [r3, #0]
|
|
800aa06: 00db lsls r3, r3, #3
|
|
800aa08: 4413 add r3, r2
|
|
800aa0a: 68fa ldr r2, [r7, #12]
|
|
800aa0c: 6812 ldr r2, [r2, #0]
|
|
800aa0e: 4413 add r3, r2
|
|
800aa10: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800aa14: 881b ldrh r3, [r3, #0]
|
|
800aa16: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800aa1a: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
|
|
|
|
if (ep->xfer_len >= TxPctSize)
|
|
800aa1e: 68bb ldr r3, [r7, #8]
|
|
800aa20: 699a ldr r2, [r3, #24]
|
|
800aa22: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800aa26: 429a cmp r2, r3
|
|
800aa28: d307 bcc.n 800aa3a <HAL_PCD_EP_DB_Transmit+0x44c>
|
|
{
|
|
ep->xfer_len -= TxPctSize;
|
|
800aa2a: 68bb ldr r3, [r7, #8]
|
|
800aa2c: 699a ldr r2, [r3, #24]
|
|
800aa2e: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800aa32: 1ad2 subs r2, r2, r3
|
|
800aa34: 68bb ldr r3, [r7, #8]
|
|
800aa36: 619a str r2, [r3, #24]
|
|
800aa38: e002 b.n 800aa40 <HAL_PCD_EP_DB_Transmit+0x452>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
800aa3a: 68bb ldr r3, [r7, #8]
|
|
800aa3c: 2200 movs r2, #0
|
|
800aa3e: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Transfer is completed */
|
|
if (ep->xfer_len == 0U)
|
|
800aa40: 68bb ldr r3, [r7, #8]
|
|
800aa42: 699b ldr r3, [r3, #24]
|
|
800aa44: 2b00 cmp r3, #0
|
|
800aa46: f040 80f6 bne.w 800ac36 <HAL_PCD_EP_DB_Transmit+0x648>
|
|
{
|
|
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
800aa4a: 68bb ldr r3, [r7, #8]
|
|
800aa4c: 785b ldrb r3, [r3, #1]
|
|
800aa4e: 2b00 cmp r3, #0
|
|
800aa50: d126 bne.n 800aaa0 <HAL_PCD_EP_DB_Transmit+0x4b2>
|
|
800aa52: 68fb ldr r3, [r7, #12]
|
|
800aa54: 681b ldr r3, [r3, #0]
|
|
800aa56: 677b str r3, [r7, #116] @ 0x74
|
|
800aa58: 68fb ldr r3, [r7, #12]
|
|
800aa5a: 681b ldr r3, [r3, #0]
|
|
800aa5c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800aa60: b29b uxth r3, r3
|
|
800aa62: 461a mov r2, r3
|
|
800aa64: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
800aa66: 4413 add r3, r2
|
|
800aa68: 677b str r3, [r7, #116] @ 0x74
|
|
800aa6a: 68bb ldr r3, [r7, #8]
|
|
800aa6c: 781b ldrb r3, [r3, #0]
|
|
800aa6e: 00da lsls r2, r3, #3
|
|
800aa70: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
800aa72: 4413 add r3, r2
|
|
800aa74: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800aa78: 673b str r3, [r7, #112] @ 0x70
|
|
800aa7a: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800aa7c: 881b ldrh r3, [r3, #0]
|
|
800aa7e: b29b uxth r3, r3
|
|
800aa80: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800aa84: b29a uxth r2, r3
|
|
800aa86: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800aa88: 801a strh r2, [r3, #0]
|
|
800aa8a: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800aa8c: 881b ldrh r3, [r3, #0]
|
|
800aa8e: b29b uxth r3, r3
|
|
800aa90: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800aa94: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800aa98: b29a uxth r2, r3
|
|
800aa9a: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800aa9c: 801a strh r2, [r3, #0]
|
|
800aa9e: e01a b.n 800aad6 <HAL_PCD_EP_DB_Transmit+0x4e8>
|
|
800aaa0: 68bb ldr r3, [r7, #8]
|
|
800aaa2: 785b ldrb r3, [r3, #1]
|
|
800aaa4: 2b01 cmp r3, #1
|
|
800aaa6: d116 bne.n 800aad6 <HAL_PCD_EP_DB_Transmit+0x4e8>
|
|
800aaa8: 68fb ldr r3, [r7, #12]
|
|
800aaaa: 681b ldr r3, [r3, #0]
|
|
800aaac: 67fb str r3, [r7, #124] @ 0x7c
|
|
800aaae: 68fb ldr r3, [r7, #12]
|
|
800aab0: 681b ldr r3, [r3, #0]
|
|
800aab2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800aab6: b29b uxth r3, r3
|
|
800aab8: 461a mov r2, r3
|
|
800aaba: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
800aabc: 4413 add r3, r2
|
|
800aabe: 67fb str r3, [r7, #124] @ 0x7c
|
|
800aac0: 68bb ldr r3, [r7, #8]
|
|
800aac2: 781b ldrb r3, [r3, #0]
|
|
800aac4: 00da lsls r2, r3, #3
|
|
800aac6: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
800aac8: 4413 add r3, r2
|
|
800aaca: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800aace: 67bb str r3, [r7, #120] @ 0x78
|
|
800aad0: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800aad2: 2200 movs r2, #0
|
|
800aad4: 801a strh r2, [r3, #0]
|
|
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
|
800aad6: 68fb ldr r3, [r7, #12]
|
|
800aad8: 681b ldr r3, [r3, #0]
|
|
800aada: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
800aade: 68bb ldr r3, [r7, #8]
|
|
800aae0: 785b ldrb r3, [r3, #1]
|
|
800aae2: 2b00 cmp r3, #0
|
|
800aae4: d12f bne.n 800ab46 <HAL_PCD_EP_DB_Transmit+0x558>
|
|
800aae6: 68fb ldr r3, [r7, #12]
|
|
800aae8: 681b ldr r3, [r3, #0]
|
|
800aaea: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
800aaee: 68fb ldr r3, [r7, #12]
|
|
800aaf0: 681b ldr r3, [r3, #0]
|
|
800aaf2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800aaf6: b29b uxth r3, r3
|
|
800aaf8: 461a mov r2, r3
|
|
800aafa: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800aafe: 4413 add r3, r2
|
|
800ab00: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
800ab04: 68bb ldr r3, [r7, #8]
|
|
800ab06: 781b ldrb r3, [r3, #0]
|
|
800ab08: 00da lsls r2, r3, #3
|
|
800ab0a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800ab0e: 4413 add r3, r2
|
|
800ab10: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800ab14: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800ab18: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800ab1c: 881b ldrh r3, [r3, #0]
|
|
800ab1e: b29b uxth r3, r3
|
|
800ab20: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800ab24: b29a uxth r2, r3
|
|
800ab26: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800ab2a: 801a strh r2, [r3, #0]
|
|
800ab2c: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800ab30: 881b ldrh r3, [r3, #0]
|
|
800ab32: b29b uxth r3, r3
|
|
800ab34: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800ab38: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800ab3c: b29a uxth r2, r3
|
|
800ab3e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800ab42: 801a strh r2, [r3, #0]
|
|
800ab44: e01c b.n 800ab80 <HAL_PCD_EP_DB_Transmit+0x592>
|
|
800ab46: 68bb ldr r3, [r7, #8]
|
|
800ab48: 785b ldrb r3, [r3, #1]
|
|
800ab4a: 2b01 cmp r3, #1
|
|
800ab4c: d118 bne.n 800ab80 <HAL_PCD_EP_DB_Transmit+0x592>
|
|
800ab4e: 68fb ldr r3, [r7, #12]
|
|
800ab50: 681b ldr r3, [r3, #0]
|
|
800ab52: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800ab56: b29b uxth r3, r3
|
|
800ab58: 461a mov r2, r3
|
|
800ab5a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
800ab5e: 4413 add r3, r2
|
|
800ab60: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
800ab64: 68bb ldr r3, [r7, #8]
|
|
800ab66: 781b ldrb r3, [r3, #0]
|
|
800ab68: 00da lsls r2, r3, #3
|
|
800ab6a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
800ab6e: 4413 add r3, r2
|
|
800ab70: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800ab74: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
800ab78: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
800ab7c: 2200 movs r2, #0
|
|
800ab7e: 801a strh r2, [r3, #0]
|
|
|
|
if (ep->type == EP_TYPE_BULK)
|
|
800ab80: 68bb ldr r3, [r7, #8]
|
|
800ab82: 78db ldrb r3, [r3, #3]
|
|
800ab84: 2b02 cmp r3, #2
|
|
800ab86: d127 bne.n 800abd8 <HAL_PCD_EP_DB_Transmit+0x5ea>
|
|
{
|
|
/* Set Bulk endpoint in NAK state */
|
|
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
|
|
800ab88: 68fb ldr r3, [r7, #12]
|
|
800ab8a: 681b ldr r3, [r3, #0]
|
|
800ab8c: 461a mov r2, r3
|
|
800ab8e: 68bb ldr r3, [r7, #8]
|
|
800ab90: 781b ldrb r3, [r3, #0]
|
|
800ab92: 009b lsls r3, r3, #2
|
|
800ab94: 4413 add r3, r2
|
|
800ab96: 881b ldrh r3, [r3, #0]
|
|
800ab98: b29b uxth r3, r3
|
|
800ab9a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800ab9e: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800aba2: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
800aba6: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
800abaa: f083 0320 eor.w r3, r3, #32
|
|
800abae: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
800abb2: 68fb ldr r3, [r7, #12]
|
|
800abb4: 681b ldr r3, [r3, #0]
|
|
800abb6: 461a mov r2, r3
|
|
800abb8: 68bb ldr r3, [r7, #8]
|
|
800abba: 781b ldrb r3, [r3, #0]
|
|
800abbc: 009b lsls r3, r3, #2
|
|
800abbe: 441a add r2, r3
|
|
800abc0: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
800abc4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800abc8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800abcc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800abd0: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800abd4: b29b uxth r3, r3
|
|
800abd6: 8013 strh r3, [r2, #0]
|
|
|
|
/* TX COMPLETE */
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
hpcd->DataInStageCallback(hpcd, ep->num);
|
|
#else
|
|
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
|
800abd8: 68bb ldr r3, [r7, #8]
|
|
800abda: 781b ldrb r3, [r3, #0]
|
|
800abdc: 4619 mov r1, r3
|
|
800abde: 68f8 ldr r0, [r7, #12]
|
|
800abe0: f00e f90d bl 8018dfe <HAL_PCD_DataInStageCallback>
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
/* need to Free USB Buff */
|
|
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
|
|
800abe4: 88fb ldrh r3, [r7, #6]
|
|
800abe6: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800abea: 2b00 cmp r3, #0
|
|
800abec: d121 bne.n 800ac32 <HAL_PCD_EP_DB_Transmit+0x644>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
|
|
800abee: 68fb ldr r3, [r7, #12]
|
|
800abf0: 681b ldr r3, [r3, #0]
|
|
800abf2: 461a mov r2, r3
|
|
800abf4: 68bb ldr r3, [r7, #8]
|
|
800abf6: 781b ldrb r3, [r3, #0]
|
|
800abf8: 009b lsls r3, r3, #2
|
|
800abfa: 4413 add r3, r2
|
|
800abfc: 881b ldrh r3, [r3, #0]
|
|
800abfe: b29b uxth r3, r3
|
|
800ac00: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800ac04: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800ac08: f8a7 3092 strh.w r3, [r7, #146] @ 0x92
|
|
800ac0c: 68fb ldr r3, [r7, #12]
|
|
800ac0e: 681b ldr r3, [r3, #0]
|
|
800ac10: 461a mov r2, r3
|
|
800ac12: 68bb ldr r3, [r7, #8]
|
|
800ac14: 781b ldrb r3, [r3, #0]
|
|
800ac16: 009b lsls r3, r3, #2
|
|
800ac18: 441a add r2, r3
|
|
800ac1a: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
|
|
800ac1e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800ac22: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800ac26: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800ac2a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800ac2e: b29b uxth r3, r3
|
|
800ac30: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
800ac32: 2300 movs r3, #0
|
|
800ac34: e113 b.n 800ae5e <HAL_PCD_EP_DB_Transmit+0x870>
|
|
}
|
|
else /* Transfer is not yet Done */
|
|
{
|
|
/* Need to Free USB Buffer */
|
|
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
|
|
800ac36: 88fb ldrh r3, [r7, #6]
|
|
800ac38: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800ac3c: 2b00 cmp r3, #0
|
|
800ac3e: d121 bne.n 800ac84 <HAL_PCD_EP_DB_Transmit+0x696>
|
|
{
|
|
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
|
|
800ac40: 68fb ldr r3, [r7, #12]
|
|
800ac42: 681b ldr r3, [r3, #0]
|
|
800ac44: 461a mov r2, r3
|
|
800ac46: 68bb ldr r3, [r7, #8]
|
|
800ac48: 781b ldrb r3, [r3, #0]
|
|
800ac4a: 009b lsls r3, r3, #2
|
|
800ac4c: 4413 add r3, r2
|
|
800ac4e: 881b ldrh r3, [r3, #0]
|
|
800ac50: b29b uxth r3, r3
|
|
800ac52: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800ac56: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800ac5a: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
|
|
800ac5e: 68fb ldr r3, [r7, #12]
|
|
800ac60: 681b ldr r3, [r3, #0]
|
|
800ac62: 461a mov r2, r3
|
|
800ac64: 68bb ldr r3, [r7, #8]
|
|
800ac66: 781b ldrb r3, [r3, #0]
|
|
800ac68: 009b lsls r3, r3, #2
|
|
800ac6a: 441a add r2, r3
|
|
800ac6c: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
|
|
800ac70: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800ac74: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800ac78: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800ac7c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800ac80: b29b uxth r3, r3
|
|
800ac82: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Still there is data to Fill in the next Buffer */
|
|
if (ep->xfer_fill_db == 1U)
|
|
800ac84: 68bb ldr r3, [r7, #8]
|
|
800ac86: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
800ac8a: 2b01 cmp r3, #1
|
|
800ac8c: f040 80be bne.w 800ae0c <HAL_PCD_EP_DB_Transmit+0x81e>
|
|
{
|
|
ep->xfer_buff += TxPctSize;
|
|
800ac90: 68bb ldr r3, [r7, #8]
|
|
800ac92: 695a ldr r2, [r3, #20]
|
|
800ac94: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800ac98: 441a add r2, r3
|
|
800ac9a: 68bb ldr r3, [r7, #8]
|
|
800ac9c: 615a str r2, [r3, #20]
|
|
ep->xfer_count += TxPctSize;
|
|
800ac9e: 68bb ldr r3, [r7, #8]
|
|
800aca0: 69da ldr r2, [r3, #28]
|
|
800aca2: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800aca6: 441a add r2, r3
|
|
800aca8: 68bb ldr r3, [r7, #8]
|
|
800acaa: 61da str r2, [r3, #28]
|
|
|
|
/* Calculate the len of the new buffer to fill */
|
|
if (ep->xfer_len_db >= ep->maxpacket)
|
|
800acac: 68bb ldr r3, [r7, #8]
|
|
800acae: 6a1a ldr r2, [r3, #32]
|
|
800acb0: 68bb ldr r3, [r7, #8]
|
|
800acb2: 691b ldr r3, [r3, #16]
|
|
800acb4: 429a cmp r2, r3
|
|
800acb6: d309 bcc.n 800accc <HAL_PCD_EP_DB_Transmit+0x6de>
|
|
{
|
|
len = ep->maxpacket;
|
|
800acb8: 68bb ldr r3, [r7, #8]
|
|
800acba: 691b ldr r3, [r3, #16]
|
|
800acbc: 65bb str r3, [r7, #88] @ 0x58
|
|
ep->xfer_len_db -= len;
|
|
800acbe: 68bb ldr r3, [r7, #8]
|
|
800acc0: 6a1a ldr r2, [r3, #32]
|
|
800acc2: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800acc4: 1ad2 subs r2, r2, r3
|
|
800acc6: 68bb ldr r3, [r7, #8]
|
|
800acc8: 621a str r2, [r3, #32]
|
|
800acca: e015 b.n 800acf8 <HAL_PCD_EP_DB_Transmit+0x70a>
|
|
}
|
|
else if (ep->xfer_len_db == 0U)
|
|
800accc: 68bb ldr r3, [r7, #8]
|
|
800acce: 6a1b ldr r3, [r3, #32]
|
|
800acd0: 2b00 cmp r3, #0
|
|
800acd2: d107 bne.n 800ace4 <HAL_PCD_EP_DB_Transmit+0x6f6>
|
|
{
|
|
len = TxPctSize;
|
|
800acd4: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
|
|
800acd8: 65bb str r3, [r7, #88] @ 0x58
|
|
ep->xfer_fill_db = 0U;
|
|
800acda: 68bb ldr r3, [r7, #8]
|
|
800acdc: 2200 movs r2, #0
|
|
800acde: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
800ace2: e009 b.n 800acf8 <HAL_PCD_EP_DB_Transmit+0x70a>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len_db;
|
|
800ace4: 68bb ldr r3, [r7, #8]
|
|
800ace6: 6a1b ldr r3, [r3, #32]
|
|
800ace8: 65bb str r3, [r7, #88] @ 0x58
|
|
ep->xfer_len_db = 0U;
|
|
800acea: 68bb ldr r3, [r7, #8]
|
|
800acec: 2200 movs r2, #0
|
|
800acee: 621a str r2, [r3, #32]
|
|
ep->xfer_fill_db = 0;
|
|
800acf0: 68bb ldr r3, [r7, #8]
|
|
800acf2: 2200 movs r2, #0
|
|
800acf4: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
}
|
|
|
|
/* Set the Double buffer counter for pma buffer1 */
|
|
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
|
|
800acf8: 68fb ldr r3, [r7, #12]
|
|
800acfa: 681b ldr r3, [r3, #0]
|
|
800acfc: 65fb str r3, [r7, #92] @ 0x5c
|
|
800acfe: 68bb ldr r3, [r7, #8]
|
|
800ad00: 785b ldrb r3, [r3, #1]
|
|
800ad02: 2b00 cmp r3, #0
|
|
800ad04: d15f bne.n 800adc6 <HAL_PCD_EP_DB_Transmit+0x7d8>
|
|
800ad06: 68fb ldr r3, [r7, #12]
|
|
800ad08: 681b ldr r3, [r3, #0]
|
|
800ad0a: 66bb str r3, [r7, #104] @ 0x68
|
|
800ad0c: 68fb ldr r3, [r7, #12]
|
|
800ad0e: 681b ldr r3, [r3, #0]
|
|
800ad10: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800ad14: b29b uxth r3, r3
|
|
800ad16: 461a mov r2, r3
|
|
800ad18: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800ad1a: 4413 add r3, r2
|
|
800ad1c: 66bb str r3, [r7, #104] @ 0x68
|
|
800ad1e: 68bb ldr r3, [r7, #8]
|
|
800ad20: 781b ldrb r3, [r3, #0]
|
|
800ad22: 00da lsls r2, r3, #3
|
|
800ad24: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800ad26: 4413 add r3, r2
|
|
800ad28: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800ad2c: 667b str r3, [r7, #100] @ 0x64
|
|
800ad2e: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800ad30: 881b ldrh r3, [r3, #0]
|
|
800ad32: b29b uxth r3, r3
|
|
800ad34: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800ad38: b29a uxth r2, r3
|
|
800ad3a: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800ad3c: 801a strh r2, [r3, #0]
|
|
800ad3e: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800ad40: 2b00 cmp r3, #0
|
|
800ad42: d10a bne.n 800ad5a <HAL_PCD_EP_DB_Transmit+0x76c>
|
|
800ad44: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800ad46: 881b ldrh r3, [r3, #0]
|
|
800ad48: b29b uxth r3, r3
|
|
800ad4a: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800ad4e: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800ad52: b29a uxth r2, r3
|
|
800ad54: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800ad56: 801a strh r2, [r3, #0]
|
|
800ad58: e04e b.n 800adf8 <HAL_PCD_EP_DB_Transmit+0x80a>
|
|
800ad5a: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800ad5c: 2b3e cmp r3, #62 @ 0x3e
|
|
800ad5e: d816 bhi.n 800ad8e <HAL_PCD_EP_DB_Transmit+0x7a0>
|
|
800ad60: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800ad62: 085b lsrs r3, r3, #1
|
|
800ad64: 663b str r3, [r7, #96] @ 0x60
|
|
800ad66: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800ad68: f003 0301 and.w r3, r3, #1
|
|
800ad6c: 2b00 cmp r3, #0
|
|
800ad6e: d002 beq.n 800ad76 <HAL_PCD_EP_DB_Transmit+0x788>
|
|
800ad70: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800ad72: 3301 adds r3, #1
|
|
800ad74: 663b str r3, [r7, #96] @ 0x60
|
|
800ad76: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800ad78: 881b ldrh r3, [r3, #0]
|
|
800ad7a: b29a uxth r2, r3
|
|
800ad7c: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800ad7e: b29b uxth r3, r3
|
|
800ad80: 029b lsls r3, r3, #10
|
|
800ad82: b29b uxth r3, r3
|
|
800ad84: 4313 orrs r3, r2
|
|
800ad86: b29a uxth r2, r3
|
|
800ad88: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800ad8a: 801a strh r2, [r3, #0]
|
|
800ad8c: e034 b.n 800adf8 <HAL_PCD_EP_DB_Transmit+0x80a>
|
|
800ad8e: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800ad90: 095b lsrs r3, r3, #5
|
|
800ad92: 663b str r3, [r7, #96] @ 0x60
|
|
800ad94: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800ad96: f003 031f and.w r3, r3, #31
|
|
800ad9a: 2b00 cmp r3, #0
|
|
800ad9c: d102 bne.n 800ada4 <HAL_PCD_EP_DB_Transmit+0x7b6>
|
|
800ad9e: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800ada0: 3b01 subs r3, #1
|
|
800ada2: 663b str r3, [r7, #96] @ 0x60
|
|
800ada4: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800ada6: 881b ldrh r3, [r3, #0]
|
|
800ada8: b29a uxth r2, r3
|
|
800adaa: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800adac: b29b uxth r3, r3
|
|
800adae: 029b lsls r3, r3, #10
|
|
800adb0: b29b uxth r3, r3
|
|
800adb2: 4313 orrs r3, r2
|
|
800adb4: b29b uxth r3, r3
|
|
800adb6: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800adba: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800adbe: b29a uxth r2, r3
|
|
800adc0: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800adc2: 801a strh r2, [r3, #0]
|
|
800adc4: e018 b.n 800adf8 <HAL_PCD_EP_DB_Transmit+0x80a>
|
|
800adc6: 68bb ldr r3, [r7, #8]
|
|
800adc8: 785b ldrb r3, [r3, #1]
|
|
800adca: 2b01 cmp r3, #1
|
|
800adcc: d114 bne.n 800adf8 <HAL_PCD_EP_DB_Transmit+0x80a>
|
|
800adce: 68fb ldr r3, [r7, #12]
|
|
800add0: 681b ldr r3, [r3, #0]
|
|
800add2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800add6: b29b uxth r3, r3
|
|
800add8: 461a mov r2, r3
|
|
800adda: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
800addc: 4413 add r3, r2
|
|
800adde: 65fb str r3, [r7, #92] @ 0x5c
|
|
800ade0: 68bb ldr r3, [r7, #8]
|
|
800ade2: 781b ldrb r3, [r3, #0]
|
|
800ade4: 00da lsls r2, r3, #3
|
|
800ade6: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
800ade8: 4413 add r3, r2
|
|
800adea: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800adee: 66fb str r3, [r7, #108] @ 0x6c
|
|
800adf0: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800adf2: b29a uxth r2, r3
|
|
800adf4: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800adf6: 801a strh r2, [r3, #0]
|
|
|
|
/* Copy the user buffer to USB PMA */
|
|
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
|
|
800adf8: 68fb ldr r3, [r7, #12]
|
|
800adfa: 6818 ldr r0, [r3, #0]
|
|
800adfc: 68bb ldr r3, [r7, #8]
|
|
800adfe: 6959 ldr r1, [r3, #20]
|
|
800ae00: 68bb ldr r3, [r7, #8]
|
|
800ae02: 895a ldrh r2, [r3, #10]
|
|
800ae04: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800ae06: b29b uxth r3, r3
|
|
800ae08: f005 ffe7 bl 8010dda <USB_WritePMA>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Enable endpoint IN */
|
|
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
|
|
800ae0c: 68fb ldr r3, [r7, #12]
|
|
800ae0e: 681b ldr r3, [r3, #0]
|
|
800ae10: 461a mov r2, r3
|
|
800ae12: 68bb ldr r3, [r7, #8]
|
|
800ae14: 781b ldrb r3, [r3, #0]
|
|
800ae16: 009b lsls r3, r3, #2
|
|
800ae18: 4413 add r3, r2
|
|
800ae1a: 881b ldrh r3, [r3, #0]
|
|
800ae1c: b29b uxth r3, r3
|
|
800ae1e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800ae22: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800ae26: 82fb strh r3, [r7, #22]
|
|
800ae28: 8afb ldrh r3, [r7, #22]
|
|
800ae2a: f083 0310 eor.w r3, r3, #16
|
|
800ae2e: 82fb strh r3, [r7, #22]
|
|
800ae30: 8afb ldrh r3, [r7, #22]
|
|
800ae32: f083 0320 eor.w r3, r3, #32
|
|
800ae36: 82fb strh r3, [r7, #22]
|
|
800ae38: 68fb ldr r3, [r7, #12]
|
|
800ae3a: 681b ldr r3, [r3, #0]
|
|
800ae3c: 461a mov r2, r3
|
|
800ae3e: 68bb ldr r3, [r7, #8]
|
|
800ae40: 781b ldrb r3, [r3, #0]
|
|
800ae42: 009b lsls r3, r3, #2
|
|
800ae44: 441a add r2, r3
|
|
800ae46: 8afb ldrh r3, [r7, #22]
|
|
800ae48: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800ae4c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800ae50: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800ae54: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800ae58: b29b uxth r3, r3
|
|
800ae5a: 8013 strh r3, [r2, #0]
|
|
|
|
return HAL_OK;
|
|
800ae5c: 2300 movs r3, #0
|
|
}
|
|
800ae5e: 4618 mov r0, r3
|
|
800ae60: 3798 adds r7, #152 @ 0x98
|
|
800ae62: 46bd mov sp, r7
|
|
800ae64: bd80 pop {r7, pc}
|
|
|
|
0800ae66 <HAL_PCDEx_PMAConfig>:
|
|
* @retval HAL status
|
|
*/
|
|
|
|
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
|
uint16_t ep_kind, uint32_t pmaadress)
|
|
{
|
|
800ae66: b480 push {r7}
|
|
800ae68: b087 sub sp, #28
|
|
800ae6a: af00 add r7, sp, #0
|
|
800ae6c: 60f8 str r0, [r7, #12]
|
|
800ae6e: 607b str r3, [r7, #4]
|
|
800ae70: 460b mov r3, r1
|
|
800ae72: 817b strh r3, [r7, #10]
|
|
800ae74: 4613 mov r3, r2
|
|
800ae76: 813b strh r3, [r7, #8]
|
|
PCD_EPTypeDef *ep;
|
|
|
|
/* Initialize ep structure */
|
|
if ((0x80U & ep_addr) == 0x80U)
|
|
800ae78: 897b ldrh r3, [r7, #10]
|
|
800ae7a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800ae7e: b29b uxth r3, r3
|
|
800ae80: 2b00 cmp r3, #0
|
|
800ae82: d00b beq.n 800ae9c <HAL_PCDEx_PMAConfig+0x36>
|
|
{
|
|
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
|
800ae84: 897b ldrh r3, [r7, #10]
|
|
800ae86: f003 0207 and.w r2, r3, #7
|
|
800ae8a: 4613 mov r3, r2
|
|
800ae8c: 009b lsls r3, r3, #2
|
|
800ae8e: 4413 add r3, r2
|
|
800ae90: 00db lsls r3, r3, #3
|
|
800ae92: 3310 adds r3, #16
|
|
800ae94: 68fa ldr r2, [r7, #12]
|
|
800ae96: 4413 add r3, r2
|
|
800ae98: 617b str r3, [r7, #20]
|
|
800ae9a: e009 b.n 800aeb0 <HAL_PCDEx_PMAConfig+0x4a>
|
|
}
|
|
else
|
|
{
|
|
ep = &hpcd->OUT_ep[ep_addr];
|
|
800ae9c: 897a ldrh r2, [r7, #10]
|
|
800ae9e: 4613 mov r3, r2
|
|
800aea0: 009b lsls r3, r3, #2
|
|
800aea2: 4413 add r3, r2
|
|
800aea4: 00db lsls r3, r3, #3
|
|
800aea6: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
800aeaa: 68fa ldr r2, [r7, #12]
|
|
800aeac: 4413 add r3, r2
|
|
800aeae: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Here we check if the endpoint is single or double Buffer*/
|
|
if (ep_kind == PCD_SNG_BUF)
|
|
800aeb0: 893b ldrh r3, [r7, #8]
|
|
800aeb2: 2b00 cmp r3, #0
|
|
800aeb4: d107 bne.n 800aec6 <HAL_PCDEx_PMAConfig+0x60>
|
|
{
|
|
/* Single Buffer */
|
|
ep->doublebuffer = 0U;
|
|
800aeb6: 697b ldr r3, [r7, #20]
|
|
800aeb8: 2200 movs r2, #0
|
|
800aeba: 731a strb r2, [r3, #12]
|
|
|
|
/* Configure the PMA */
|
|
ep->pmaadress = (uint16_t)pmaadress;
|
|
800aebc: 687b ldr r3, [r7, #4]
|
|
800aebe: b29a uxth r2, r3
|
|
800aec0: 697b ldr r3, [r7, #20]
|
|
800aec2: 80da strh r2, [r3, #6]
|
|
800aec4: e00b b.n 800aede <HAL_PCDEx_PMAConfig+0x78>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
else /* USB_DBL_BUF */
|
|
{
|
|
/* Double Buffer Endpoint */
|
|
ep->doublebuffer = 1U;
|
|
800aec6: 697b ldr r3, [r7, #20]
|
|
800aec8: 2201 movs r2, #1
|
|
800aeca: 731a strb r2, [r3, #12]
|
|
|
|
/* Configure the PMA */
|
|
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
|
|
800aecc: 687b ldr r3, [r7, #4]
|
|
800aece: b29a uxth r2, r3
|
|
800aed0: 697b ldr r3, [r7, #20]
|
|
800aed2: 811a strh r2, [r3, #8]
|
|
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
|
|
800aed4: 687b ldr r3, [r7, #4]
|
|
800aed6: 0c1b lsrs r3, r3, #16
|
|
800aed8: b29a uxth r2, r3
|
|
800aeda: 697b ldr r3, [r7, #20]
|
|
800aedc: 815a strh r2, [r3, #10]
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
return HAL_OK;
|
|
800aede: 2300 movs r3, #0
|
|
}
|
|
800aee0: 4618 mov r0, r3
|
|
800aee2: 371c adds r7, #28
|
|
800aee4: 46bd mov sp, r7
|
|
800aee6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800aeea: 4770 bx lr
|
|
|
|
0800aeec <HAL_PCDEx_ActivateLPM>:
|
|
* @brief Activate LPM feature.
|
|
* @param hpcd PCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
|
{
|
|
800aeec: b480 push {r7}
|
|
800aeee: b085 sub sp, #20
|
|
800aef0: af00 add r7, sp, #0
|
|
800aef2: 6078 str r0, [r7, #4]
|
|
|
|
USB_TypeDef *USBx = hpcd->Instance;
|
|
800aef4: 687b ldr r3, [r7, #4]
|
|
800aef6: 681b ldr r3, [r3, #0]
|
|
800aef8: 60fb str r3, [r7, #12]
|
|
hpcd->lpm_active = 1U;
|
|
800aefa: 687b ldr r3, [r7, #4]
|
|
800aefc: 2201 movs r2, #1
|
|
800aefe: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
hpcd->LPM_State = LPM_L0;
|
|
800af02: 687b ldr r3, [r7, #4]
|
|
800af04: 2200 movs r2, #0
|
|
800af06: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8
|
|
|
|
USBx->LPMCSR |= USB_LPMCSR_LMPEN;
|
|
800af0a: 68fb ldr r3, [r7, #12]
|
|
800af0c: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54
|
|
800af10: b29b uxth r3, r3
|
|
800af12: f043 0301 orr.w r3, r3, #1
|
|
800af16: b29a uxth r2, r3
|
|
800af18: 68fb ldr r3, [r7, #12]
|
|
800af1a: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
|
|
USBx->LPMCSR |= USB_LPMCSR_LPMACK;
|
|
800af1e: 68fb ldr r3, [r7, #12]
|
|
800af20: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54
|
|
800af24: b29b uxth r3, r3
|
|
800af26: f043 0302 orr.w r3, r3, #2
|
|
800af2a: b29a uxth r2, r3
|
|
800af2c: 68fb ldr r3, [r7, #12]
|
|
800af2e: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
|
|
|
|
return HAL_OK;
|
|
800af32: 2300 movs r3, #0
|
|
}
|
|
800af34: 4618 mov r0, r3
|
|
800af36: 3714 adds r7, #20
|
|
800af38: 46bd mov sp, r7
|
|
800af3a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800af3e: 4770 bx lr
|
|
|
|
0800af40 <HAL_PWR_EnableBkUpAccess>:
|
|
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
|
|
* back-up domain.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_EnableBkUpAccess(void)
|
|
{
|
|
800af40: b480 push {r7}
|
|
800af42: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
800af44: 4b05 ldr r3, [pc, #20] @ (800af5c <HAL_PWR_EnableBkUpAccess+0x1c>)
|
|
800af46: 681b ldr r3, [r3, #0]
|
|
800af48: 4a04 ldr r2, [pc, #16] @ (800af5c <HAL_PWR_EnableBkUpAccess+0x1c>)
|
|
800af4a: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
800af4e: 6013 str r3, [r2, #0]
|
|
}
|
|
800af50: bf00 nop
|
|
800af52: 46bd mov sp, r7
|
|
800af54: f85d 7b04 ldr.w r7, [sp], #4
|
|
800af58: 4770 bx lr
|
|
800af5a: bf00 nop
|
|
800af5c: 58000400 .word 0x58000400
|
|
|
|
0800af60 <HAL_PWREx_GetVoltageRange>:
|
|
/**
|
|
* @brief Return Voltage Scaling Range.
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
|
|
*/
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
|
{
|
|
800af60: b480 push {r7}
|
|
800af62: af00 add r7, sp, #0
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
|
800af64: 4b04 ldr r3, [pc, #16] @ (800af78 <HAL_PWREx_GetVoltageRange+0x18>)
|
|
800af66: 681b ldr r3, [r3, #0]
|
|
800af68: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
}
|
|
800af6c: 4618 mov r0, r3
|
|
800af6e: 46bd mov sp, r7
|
|
800af70: f85d 7b04 ldr.w r7, [sp], #4
|
|
800af74: 4770 bx lr
|
|
800af76: bf00 nop
|
|
800af78: 58000400 .word 0x58000400
|
|
|
|
0800af7c <HAL_PWREx_EnableVddUSB>:
|
|
* @brief Enable VDDUSB supply.
|
|
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_EnableVddUSB(void)
|
|
{
|
|
800af7c: b480 push {r7}
|
|
800af7e: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR2, PWR_CR2_USV);
|
|
800af80: 4b05 ldr r3, [pc, #20] @ (800af98 <HAL_PWREx_EnableVddUSB+0x1c>)
|
|
800af82: 685b ldr r3, [r3, #4]
|
|
800af84: 4a04 ldr r2, [pc, #16] @ (800af98 <HAL_PWREx_EnableVddUSB+0x1c>)
|
|
800af86: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
800af8a: 6053 str r3, [r2, #4]
|
|
}
|
|
800af8c: bf00 nop
|
|
800af8e: 46bd mov sp, r7
|
|
800af90: f85d 7b04 ldr.w r7, [sp], #4
|
|
800af94: 4770 bx lr
|
|
800af96: bf00 nop
|
|
800af98: 58000400 .word 0x58000400
|
|
|
|
0800af9c <LL_RCC_HSE_IsEnabledDiv2>:
|
|
{
|
|
800af9c: b480 push {r7}
|
|
800af9e: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL);
|
|
800afa0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800afa4: 681b ldr r3, [r3, #0]
|
|
800afa6: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800afaa: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
800afae: d101 bne.n 800afb4 <LL_RCC_HSE_IsEnabledDiv2+0x18>
|
|
800afb0: 2301 movs r3, #1
|
|
800afb2: e000 b.n 800afb6 <LL_RCC_HSE_IsEnabledDiv2+0x1a>
|
|
800afb4: 2300 movs r3, #0
|
|
}
|
|
800afb6: 4618 mov r0, r3
|
|
800afb8: 46bd mov sp, r7
|
|
800afba: f85d 7b04 ldr.w r7, [sp], #4
|
|
800afbe: 4770 bx lr
|
|
|
|
0800afc0 <LL_RCC_HSE_Enable>:
|
|
{
|
|
800afc0: b480 push {r7}
|
|
800afc2: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_HSEON);
|
|
800afc4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800afc8: 681b ldr r3, [r3, #0]
|
|
800afca: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800afce: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800afd2: 6013 str r3, [r2, #0]
|
|
}
|
|
800afd4: bf00 nop
|
|
800afd6: 46bd mov sp, r7
|
|
800afd8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800afdc: 4770 bx lr
|
|
|
|
0800afde <LL_RCC_HSE_Disable>:
|
|
{
|
|
800afde: b480 push {r7}
|
|
800afe0: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
|
|
800afe2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800afe6: 681b ldr r3, [r3, #0]
|
|
800afe8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800afec: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800aff0: 6013 str r3, [r2, #0]
|
|
}
|
|
800aff2: bf00 nop
|
|
800aff4: 46bd mov sp, r7
|
|
800aff6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800affa: 4770 bx lr
|
|
|
|
0800affc <LL_RCC_HSE_IsReady>:
|
|
{
|
|
800affc: b480 push {r7}
|
|
800affe: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
|
|
800b000: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b004: 681b ldr r3, [r3, #0]
|
|
800b006: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800b00a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
|
|
800b00e: d101 bne.n 800b014 <LL_RCC_HSE_IsReady+0x18>
|
|
800b010: 2301 movs r3, #1
|
|
800b012: e000 b.n 800b016 <LL_RCC_HSE_IsReady+0x1a>
|
|
800b014: 2300 movs r3, #0
|
|
}
|
|
800b016: 4618 mov r0, r3
|
|
800b018: 46bd mov sp, r7
|
|
800b01a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b01e: 4770 bx lr
|
|
|
|
0800b020 <LL_RCC_HSI_Enable>:
|
|
{
|
|
800b020: b480 push {r7}
|
|
800b022: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_HSION);
|
|
800b024: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b028: 681b ldr r3, [r3, #0]
|
|
800b02a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b02e: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
800b032: 6013 str r3, [r2, #0]
|
|
}
|
|
800b034: bf00 nop
|
|
800b036: 46bd mov sp, r7
|
|
800b038: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b03c: 4770 bx lr
|
|
|
|
0800b03e <LL_RCC_HSI_Disable>:
|
|
{
|
|
800b03e: b480 push {r7}
|
|
800b040: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSION);
|
|
800b042: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b046: 681b ldr r3, [r3, #0]
|
|
800b048: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b04c: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800b050: 6013 str r3, [r2, #0]
|
|
}
|
|
800b052: bf00 nop
|
|
800b054: 46bd mov sp, r7
|
|
800b056: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b05a: 4770 bx lr
|
|
|
|
0800b05c <LL_RCC_HSI_IsReady>:
|
|
{
|
|
800b05c: b480 push {r7}
|
|
800b05e: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
|
|
800b060: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b064: 681b ldr r3, [r3, #0]
|
|
800b066: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800b06a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800b06e: d101 bne.n 800b074 <LL_RCC_HSI_IsReady+0x18>
|
|
800b070: 2301 movs r3, #1
|
|
800b072: e000 b.n 800b076 <LL_RCC_HSI_IsReady+0x1a>
|
|
800b074: 2300 movs r3, #0
|
|
}
|
|
800b076: 4618 mov r0, r3
|
|
800b078: 46bd mov sp, r7
|
|
800b07a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b07e: 4770 bx lr
|
|
|
|
0800b080 <LL_RCC_HSI_SetCalibTrimming>:
|
|
{
|
|
800b080: b480 push {r7}
|
|
800b082: b083 sub sp, #12
|
|
800b084: af00 add r7, sp, #0
|
|
800b086: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
|
|
800b088: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b08c: 685b ldr r3, [r3, #4]
|
|
800b08e: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
|
|
800b092: 687b ldr r3, [r7, #4]
|
|
800b094: 061b lsls r3, r3, #24
|
|
800b096: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b09a: 4313 orrs r3, r2
|
|
800b09c: 604b str r3, [r1, #4]
|
|
}
|
|
800b09e: bf00 nop
|
|
800b0a0: 370c adds r7, #12
|
|
800b0a2: 46bd mov sp, r7
|
|
800b0a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b0a8: 4770 bx lr
|
|
|
|
0800b0aa <LL_RCC_HSI48_Enable>:
|
|
{
|
|
800b0aa: b480 push {r7}
|
|
800b0ac: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
|
|
800b0ae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b0b2: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
800b0b6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b0ba: f043 0301 orr.w r3, r3, #1
|
|
800b0be: f8c2 3098 str.w r3, [r2, #152] @ 0x98
|
|
}
|
|
800b0c2: bf00 nop
|
|
800b0c4: 46bd mov sp, r7
|
|
800b0c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b0ca: 4770 bx lr
|
|
|
|
0800b0cc <LL_RCC_HSI48_Disable>:
|
|
{
|
|
800b0cc: b480 push {r7}
|
|
800b0ce: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
|
|
800b0d0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b0d4: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
800b0d8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b0dc: f023 0301 bic.w r3, r3, #1
|
|
800b0e0: f8c2 3098 str.w r3, [r2, #152] @ 0x98
|
|
}
|
|
800b0e4: bf00 nop
|
|
800b0e6: 46bd mov sp, r7
|
|
800b0e8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b0ec: 4770 bx lr
|
|
|
|
0800b0ee <LL_RCC_HSI48_IsReady>:
|
|
{
|
|
800b0ee: b480 push {r7}
|
|
800b0f0: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
|
|
800b0f2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b0f6: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
800b0fa: f003 0302 and.w r3, r3, #2
|
|
800b0fe: 2b02 cmp r3, #2
|
|
800b100: d101 bne.n 800b106 <LL_RCC_HSI48_IsReady+0x18>
|
|
800b102: 2301 movs r3, #1
|
|
800b104: e000 b.n 800b108 <LL_RCC_HSI48_IsReady+0x1a>
|
|
800b106: 2300 movs r3, #0
|
|
}
|
|
800b108: 4618 mov r0, r3
|
|
800b10a: 46bd mov sp, r7
|
|
800b10c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b110: 4770 bx lr
|
|
|
|
0800b112 <LL_RCC_LSE_Enable>:
|
|
{
|
|
800b112: b480 push {r7}
|
|
800b114: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
800b116: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b11a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800b11e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b122: f043 0301 orr.w r3, r3, #1
|
|
800b126: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
800b12a: bf00 nop
|
|
800b12c: 46bd mov sp, r7
|
|
800b12e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b132: 4770 bx lr
|
|
|
|
0800b134 <LL_RCC_LSE_Disable>:
|
|
{
|
|
800b134: b480 push {r7}
|
|
800b136: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
800b138: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b13c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800b140: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b144: f023 0301 bic.w r3, r3, #1
|
|
800b148: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
800b14c: bf00 nop
|
|
800b14e: 46bd mov sp, r7
|
|
800b150: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b154: 4770 bx lr
|
|
|
|
0800b156 <LL_RCC_LSE_EnableBypass>:
|
|
{
|
|
800b156: b480 push {r7}
|
|
800b158: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
800b15a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b15e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800b162: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b166: f043 0304 orr.w r3, r3, #4
|
|
800b16a: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
800b16e: bf00 nop
|
|
800b170: 46bd mov sp, r7
|
|
800b172: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b176: 4770 bx lr
|
|
|
|
0800b178 <LL_RCC_LSE_DisableBypass>:
|
|
{
|
|
800b178: b480 push {r7}
|
|
800b17a: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
800b17c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b180: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800b184: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b188: f023 0304 bic.w r3, r3, #4
|
|
800b18c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
800b190: bf00 nop
|
|
800b192: 46bd mov sp, r7
|
|
800b194: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b198: 4770 bx lr
|
|
|
|
0800b19a <LL_RCC_LSE_IsReady>:
|
|
{
|
|
800b19a: b480 push {r7}
|
|
800b19c: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
|
|
800b19e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b1a2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800b1a6: f003 0302 and.w r3, r3, #2
|
|
800b1aa: 2b02 cmp r3, #2
|
|
800b1ac: d101 bne.n 800b1b2 <LL_RCC_LSE_IsReady+0x18>
|
|
800b1ae: 2301 movs r3, #1
|
|
800b1b0: e000 b.n 800b1b4 <LL_RCC_LSE_IsReady+0x1a>
|
|
800b1b2: 2300 movs r3, #0
|
|
}
|
|
800b1b4: 4618 mov r0, r3
|
|
800b1b6: 46bd mov sp, r7
|
|
800b1b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b1bc: 4770 bx lr
|
|
|
|
0800b1be <LL_RCC_LSI1_Enable>:
|
|
{
|
|
800b1be: b480 push {r7}
|
|
800b1c0: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CSR, RCC_CSR_LSI1ON);
|
|
800b1c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b1c6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800b1ca: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b1ce: f043 0301 orr.w r3, r3, #1
|
|
800b1d2: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
}
|
|
800b1d6: bf00 nop
|
|
800b1d8: 46bd mov sp, r7
|
|
800b1da: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b1de: 4770 bx lr
|
|
|
|
0800b1e0 <LL_RCC_LSI1_Disable>:
|
|
{
|
|
800b1e0: b480 push {r7}
|
|
800b1e2: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON);
|
|
800b1e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b1e8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800b1ec: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b1f0: f023 0301 bic.w r3, r3, #1
|
|
800b1f4: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
}
|
|
800b1f8: bf00 nop
|
|
800b1fa: 46bd mov sp, r7
|
|
800b1fc: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b200: 4770 bx lr
|
|
|
|
0800b202 <LL_RCC_LSI1_IsReady>:
|
|
{
|
|
800b202: b480 push {r7}
|
|
800b204: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL);
|
|
800b206: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b20a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800b20e: f003 0302 and.w r3, r3, #2
|
|
800b212: 2b02 cmp r3, #2
|
|
800b214: d101 bne.n 800b21a <LL_RCC_LSI1_IsReady+0x18>
|
|
800b216: 2301 movs r3, #1
|
|
800b218: e000 b.n 800b21c <LL_RCC_LSI1_IsReady+0x1a>
|
|
800b21a: 2300 movs r3, #0
|
|
}
|
|
800b21c: 4618 mov r0, r3
|
|
800b21e: 46bd mov sp, r7
|
|
800b220: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b224: 4770 bx lr
|
|
|
|
0800b226 <LL_RCC_LSI2_Enable>:
|
|
{
|
|
800b226: b480 push {r7}
|
|
800b228: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CSR, RCC_CSR_LSI2ON);
|
|
800b22a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b22e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800b232: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b236: f043 0304 orr.w r3, r3, #4
|
|
800b23a: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
}
|
|
800b23e: bf00 nop
|
|
800b240: 46bd mov sp, r7
|
|
800b242: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b246: 4770 bx lr
|
|
|
|
0800b248 <LL_RCC_LSI2_Disable>:
|
|
{
|
|
800b248: b480 push {r7}
|
|
800b24a: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON);
|
|
800b24c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b250: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800b254: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b258: f023 0304 bic.w r3, r3, #4
|
|
800b25c: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
}
|
|
800b260: bf00 nop
|
|
800b262: 46bd mov sp, r7
|
|
800b264: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b268: 4770 bx lr
|
|
|
|
0800b26a <LL_RCC_LSI2_IsReady>:
|
|
{
|
|
800b26a: b480 push {r7}
|
|
800b26c: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL);
|
|
800b26e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b272: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800b276: f003 0308 and.w r3, r3, #8
|
|
800b27a: 2b08 cmp r3, #8
|
|
800b27c: d101 bne.n 800b282 <LL_RCC_LSI2_IsReady+0x18>
|
|
800b27e: 2301 movs r3, #1
|
|
800b280: e000 b.n 800b284 <LL_RCC_LSI2_IsReady+0x1a>
|
|
800b282: 2300 movs r3, #0
|
|
}
|
|
800b284: 4618 mov r0, r3
|
|
800b286: 46bd mov sp, r7
|
|
800b288: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b28c: 4770 bx lr
|
|
|
|
0800b28e <LL_RCC_LSI2_SetTrimming>:
|
|
{
|
|
800b28e: b480 push {r7}
|
|
800b290: b083 sub sp, #12
|
|
800b292: af00 add r7, sp, #0
|
|
800b294: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos);
|
|
800b296: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b29a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800b29e: f423 6270 bic.w r2, r3, #3840 @ 0xf00
|
|
800b2a2: 687b ldr r3, [r7, #4]
|
|
800b2a4: 021b lsls r3, r3, #8
|
|
800b2a6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b2aa: 4313 orrs r3, r2
|
|
800b2ac: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
800b2b0: bf00 nop
|
|
800b2b2: 370c adds r7, #12
|
|
800b2b4: 46bd mov sp, r7
|
|
800b2b6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b2ba: 4770 bx lr
|
|
|
|
0800b2bc <LL_RCC_MSI_Enable>:
|
|
{
|
|
800b2bc: b480 push {r7}
|
|
800b2be: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSION);
|
|
800b2c0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b2c4: 681b ldr r3, [r3, #0]
|
|
800b2c6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b2ca: f043 0301 orr.w r3, r3, #1
|
|
800b2ce: 6013 str r3, [r2, #0]
|
|
}
|
|
800b2d0: bf00 nop
|
|
800b2d2: 46bd mov sp, r7
|
|
800b2d4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b2d8: 4770 bx lr
|
|
|
|
0800b2da <LL_RCC_MSI_Disable>:
|
|
{
|
|
800b2da: b480 push {r7}
|
|
800b2dc: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_MSION);
|
|
800b2de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b2e2: 681b ldr r3, [r3, #0]
|
|
800b2e4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b2e8: f023 0301 bic.w r3, r3, #1
|
|
800b2ec: 6013 str r3, [r2, #0]
|
|
}
|
|
800b2ee: bf00 nop
|
|
800b2f0: 46bd mov sp, r7
|
|
800b2f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b2f6: 4770 bx lr
|
|
|
|
0800b2f8 <LL_RCC_MSI_IsReady>:
|
|
{
|
|
800b2f8: b480 push {r7}
|
|
800b2fa: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL);
|
|
800b2fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b300: 681b ldr r3, [r3, #0]
|
|
800b302: f003 0302 and.w r3, r3, #2
|
|
800b306: 2b02 cmp r3, #2
|
|
800b308: d101 bne.n 800b30e <LL_RCC_MSI_IsReady+0x16>
|
|
800b30a: 2301 movs r3, #1
|
|
800b30c: e000 b.n 800b310 <LL_RCC_MSI_IsReady+0x18>
|
|
800b30e: 2300 movs r3, #0
|
|
}
|
|
800b310: 4618 mov r0, r3
|
|
800b312: 46bd mov sp, r7
|
|
800b314: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b318: 4770 bx lr
|
|
|
|
0800b31a <LL_RCC_MSI_SetRange>:
|
|
{
|
|
800b31a: b480 push {r7}
|
|
800b31c: b083 sub sp, #12
|
|
800b31e: af00 add r7, sp, #0
|
|
800b320: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
|
|
800b322: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b326: 681b ldr r3, [r3, #0]
|
|
800b328: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
800b32c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b330: 687b ldr r3, [r7, #4]
|
|
800b332: 4313 orrs r3, r2
|
|
800b334: 600b str r3, [r1, #0]
|
|
}
|
|
800b336: bf00 nop
|
|
800b338: 370c adds r7, #12
|
|
800b33a: 46bd mov sp, r7
|
|
800b33c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b340: 4770 bx lr
|
|
|
|
0800b342 <LL_RCC_MSI_GetRange>:
|
|
{
|
|
800b342: b480 push {r7}
|
|
800b344: b083 sub sp, #12
|
|
800b346: af00 add r7, sp, #0
|
|
uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);
|
|
800b348: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b34c: 681b ldr r3, [r3, #0]
|
|
800b34e: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
800b352: 607b str r3, [r7, #4]
|
|
if (msiRange > LL_RCC_MSIRANGE_11)
|
|
800b354: 687b ldr r3, [r7, #4]
|
|
800b356: 2bb0 cmp r3, #176 @ 0xb0
|
|
800b358: d901 bls.n 800b35e <LL_RCC_MSI_GetRange+0x1c>
|
|
msiRange = LL_RCC_MSIRANGE_11;
|
|
800b35a: 23b0 movs r3, #176 @ 0xb0
|
|
800b35c: 607b str r3, [r7, #4]
|
|
return msiRange;
|
|
800b35e: 687b ldr r3, [r7, #4]
|
|
}
|
|
800b360: 4618 mov r0, r3
|
|
800b362: 370c adds r7, #12
|
|
800b364: 46bd mov sp, r7
|
|
800b366: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b36a: 4770 bx lr
|
|
|
|
0800b36c <LL_RCC_MSI_SetCalibTrimming>:
|
|
{
|
|
800b36c: b480 push {r7}
|
|
800b36e: b083 sub sp, #12
|
|
800b370: af00 add r7, sp, #0
|
|
800b372: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
|
|
800b374: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b378: 685b ldr r3, [r3, #4]
|
|
800b37a: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
800b37e: 687b ldr r3, [r7, #4]
|
|
800b380: 021b lsls r3, r3, #8
|
|
800b382: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b386: 4313 orrs r3, r2
|
|
800b388: 604b str r3, [r1, #4]
|
|
}
|
|
800b38a: bf00 nop
|
|
800b38c: 370c adds r7, #12
|
|
800b38e: 46bd mov sp, r7
|
|
800b390: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b394: 4770 bx lr
|
|
|
|
0800b396 <LL_RCC_SetSysClkSource>:
|
|
{
|
|
800b396: b480 push {r7}
|
|
800b398: b083 sub sp, #12
|
|
800b39a: af00 add r7, sp, #0
|
|
800b39c: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
|
|
800b39e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b3a2: 689b ldr r3, [r3, #8]
|
|
800b3a4: f023 0203 bic.w r2, r3, #3
|
|
800b3a8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b3ac: 687b ldr r3, [r7, #4]
|
|
800b3ae: 4313 orrs r3, r2
|
|
800b3b0: 608b str r3, [r1, #8]
|
|
}
|
|
800b3b2: bf00 nop
|
|
800b3b4: 370c adds r7, #12
|
|
800b3b6: 46bd mov sp, r7
|
|
800b3b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b3bc: 4770 bx lr
|
|
|
|
0800b3be <LL_RCC_GetSysClkSource>:
|
|
{
|
|
800b3be: b480 push {r7}
|
|
800b3c0: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
|
|
800b3c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b3c6: 689b ldr r3, [r3, #8]
|
|
800b3c8: f003 030c and.w r3, r3, #12
|
|
}
|
|
800b3cc: 4618 mov r0, r3
|
|
800b3ce: 46bd mov sp, r7
|
|
800b3d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b3d4: 4770 bx lr
|
|
|
|
0800b3d6 <LL_RCC_SetAHBPrescaler>:
|
|
{
|
|
800b3d6: b480 push {r7}
|
|
800b3d8: b083 sub sp, #12
|
|
800b3da: af00 add r7, sp, #0
|
|
800b3dc: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
|
|
800b3de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b3e2: 689b ldr r3, [r3, #8]
|
|
800b3e4: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
800b3e8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b3ec: 687b ldr r3, [r7, #4]
|
|
800b3ee: 4313 orrs r3, r2
|
|
800b3f0: 608b str r3, [r1, #8]
|
|
}
|
|
800b3f2: bf00 nop
|
|
800b3f4: 370c adds r7, #12
|
|
800b3f6: 46bd mov sp, r7
|
|
800b3f8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b3fc: 4770 bx lr
|
|
|
|
0800b3fe <LL_C2_RCC_SetAHBPrescaler>:
|
|
{
|
|
800b3fe: b480 push {r7}
|
|
800b400: b083 sub sp, #12
|
|
800b402: af00 add r7, sp, #0
|
|
800b404: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler);
|
|
800b406: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b40a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
800b40e: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
800b412: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b416: 687b ldr r3, [r7, #4]
|
|
800b418: 4313 orrs r3, r2
|
|
800b41a: f8c1 3108 str.w r3, [r1, #264] @ 0x108
|
|
}
|
|
800b41e: bf00 nop
|
|
800b420: 370c adds r7, #12
|
|
800b422: 46bd mov sp, r7
|
|
800b424: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b428: 4770 bx lr
|
|
|
|
0800b42a <LL_RCC_SetAHB4Prescaler>:
|
|
{
|
|
800b42a: b480 push {r7}
|
|
800b42c: b083 sub sp, #12
|
|
800b42e: af00 add r7, sp, #0
|
|
800b430: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4);
|
|
800b432: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b436: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
800b43a: f023 020f bic.w r2, r3, #15
|
|
800b43e: 687b ldr r3, [r7, #4]
|
|
800b440: 091b lsrs r3, r3, #4
|
|
800b442: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b446: 4313 orrs r3, r2
|
|
800b448: f8c1 3108 str.w r3, [r1, #264] @ 0x108
|
|
}
|
|
800b44c: bf00 nop
|
|
800b44e: 370c adds r7, #12
|
|
800b450: 46bd mov sp, r7
|
|
800b452: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b456: 4770 bx lr
|
|
|
|
0800b458 <LL_RCC_SetAPB1Prescaler>:
|
|
{
|
|
800b458: b480 push {r7}
|
|
800b45a: b083 sub sp, #12
|
|
800b45c: af00 add r7, sp, #0
|
|
800b45e: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
|
|
800b460: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b464: 689b ldr r3, [r3, #8]
|
|
800b466: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
800b46a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b46e: 687b ldr r3, [r7, #4]
|
|
800b470: 4313 orrs r3, r2
|
|
800b472: 608b str r3, [r1, #8]
|
|
}
|
|
800b474: bf00 nop
|
|
800b476: 370c adds r7, #12
|
|
800b478: 46bd mov sp, r7
|
|
800b47a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b47e: 4770 bx lr
|
|
|
|
0800b480 <LL_RCC_SetAPB2Prescaler>:
|
|
{
|
|
800b480: b480 push {r7}
|
|
800b482: b083 sub sp, #12
|
|
800b484: af00 add r7, sp, #0
|
|
800b486: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
|
|
800b488: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b48c: 689b ldr r3, [r3, #8]
|
|
800b48e: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
800b492: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800b496: 687b ldr r3, [r7, #4]
|
|
800b498: 4313 orrs r3, r2
|
|
800b49a: 608b str r3, [r1, #8]
|
|
}
|
|
800b49c: bf00 nop
|
|
800b49e: 370c adds r7, #12
|
|
800b4a0: 46bd mov sp, r7
|
|
800b4a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b4a6: 4770 bx lr
|
|
|
|
0800b4a8 <LL_RCC_GetAHBPrescaler>:
|
|
{
|
|
800b4a8: b480 push {r7}
|
|
800b4aa: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
|
|
800b4ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b4b0: 689b ldr r3, [r3, #8]
|
|
800b4b2: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
}
|
|
800b4b6: 4618 mov r0, r3
|
|
800b4b8: 46bd mov sp, r7
|
|
800b4ba: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b4be: 4770 bx lr
|
|
|
|
0800b4c0 <LL_C2_RCC_GetAHBPrescaler>:
|
|
{
|
|
800b4c0: b480 push {r7}
|
|
800b4c2: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE));
|
|
800b4c4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b4c8: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
800b4cc: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
}
|
|
800b4d0: 4618 mov r0, r3
|
|
800b4d2: 46bd mov sp, r7
|
|
800b4d4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b4d8: 4770 bx lr
|
|
|
|
0800b4da <LL_RCC_GetAHB4Prescaler>:
|
|
{
|
|
800b4da: b480 push {r7}
|
|
800b4dc: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4);
|
|
800b4de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b4e2: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
800b4e6: 011b lsls r3, r3, #4
|
|
800b4e8: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
}
|
|
800b4ec: 4618 mov r0, r3
|
|
800b4ee: 46bd mov sp, r7
|
|
800b4f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b4f4: 4770 bx lr
|
|
|
|
0800b4f6 <LL_RCC_GetAPB1Prescaler>:
|
|
{
|
|
800b4f6: b480 push {r7}
|
|
800b4f8: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
|
|
800b4fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b4fe: 689b ldr r3, [r3, #8]
|
|
800b500: f403 63e0 and.w r3, r3, #1792 @ 0x700
|
|
}
|
|
800b504: 4618 mov r0, r3
|
|
800b506: 46bd mov sp, r7
|
|
800b508: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b50c: 4770 bx lr
|
|
|
|
0800b50e <LL_RCC_GetAPB2Prescaler>:
|
|
{
|
|
800b50e: b480 push {r7}
|
|
800b510: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
|
|
800b512: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b516: 689b ldr r3, [r3, #8]
|
|
800b518: f403 5360 and.w r3, r3, #14336 @ 0x3800
|
|
}
|
|
800b51c: 4618 mov r0, r3
|
|
800b51e: 46bd mov sp, r7
|
|
800b520: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b524: 4770 bx lr
|
|
|
|
0800b526 <LL_RCC_PLL_Enable>:
|
|
* @brief Enable PLL
|
|
* @rmtoll CR PLLON LL_RCC_PLL_Enable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
|
|
{
|
|
800b526: b480 push {r7}
|
|
800b528: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_PLLON);
|
|
800b52a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b52e: 681b ldr r3, [r3, #0]
|
|
800b530: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b534: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
800b538: 6013 str r3, [r2, #0]
|
|
}
|
|
800b53a: bf00 nop
|
|
800b53c: 46bd mov sp, r7
|
|
800b53e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b542: 4770 bx lr
|
|
|
|
0800b544 <LL_RCC_PLL_Disable>:
|
|
* @note Cannot be disabled if the PLL clock is used as the system clock
|
|
* @rmtoll CR PLLON LL_RCC_PLL_Disable
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
|
|
{
|
|
800b544: b480 push {r7}
|
|
800b546: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
|
|
800b548: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b54c: 681b ldr r3, [r3, #0]
|
|
800b54e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800b552: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800b556: 6013 str r3, [r2, #0]
|
|
}
|
|
800b558: bf00 nop
|
|
800b55a: 46bd mov sp, r7
|
|
800b55c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b560: 4770 bx lr
|
|
|
|
0800b562 <LL_RCC_PLL_IsReady>:
|
|
* @brief Check if PLL Ready
|
|
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
|
|
{
|
|
800b562: b480 push {r7}
|
|
800b564: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
|
|
800b566: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b56a: 681b ldr r3, [r3, #0]
|
|
800b56c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800b570: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
800b574: d101 bne.n 800b57a <LL_RCC_PLL_IsReady+0x18>
|
|
800b576: 2301 movs r3, #1
|
|
800b578: e000 b.n 800b57c <LL_RCC_PLL_IsReady+0x1a>
|
|
800b57a: 2300 movs r3, #0
|
|
}
|
|
800b57c: 4618 mov r0, r3
|
|
800b57e: 46bd mov sp, r7
|
|
800b580: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b584: 4770 bx lr
|
|
|
|
0800b586 <LL_RCC_PLL_GetN>:
|
|
* @brief Get Main PLL multiplication factor for VCO
|
|
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
|
|
* @retval Between 6 and 127
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
|
|
{
|
|
800b586: b480 push {r7}
|
|
800b588: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
800b58a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b58e: 68db ldr r3, [r3, #12]
|
|
800b590: 0a1b lsrs r3, r3, #8
|
|
800b592: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
}
|
|
800b596: 4618 mov r0, r3
|
|
800b598: 46bd mov sp, r7
|
|
800b59a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b59e: 4770 bx lr
|
|
|
|
0800b5a0 <LL_RCC_PLL_GetR>:
|
|
* @arg @ref LL_RCC_PLLR_DIV_6
|
|
* @arg @ref LL_RCC_PLLR_DIV_7
|
|
* @arg @ref LL_RCC_PLLR_DIV_8
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
|
|
{
|
|
800b5a0: b480 push {r7}
|
|
800b5a2: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
|
|
800b5a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b5a8: 68db ldr r3, [r3, #12]
|
|
800b5aa: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000
|
|
}
|
|
800b5ae: 4618 mov r0, r3
|
|
800b5b0: 46bd mov sp, r7
|
|
800b5b2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b5b6: 4770 bx lr
|
|
|
|
0800b5b8 <LL_RCC_PLL_GetDivider>:
|
|
* @arg @ref LL_RCC_PLLM_DIV_6
|
|
* @arg @ref LL_RCC_PLLM_DIV_7
|
|
* @arg @ref LL_RCC_PLLM_DIV_8
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
|
|
{
|
|
800b5b8: b480 push {r7}
|
|
800b5ba: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
|
|
800b5bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b5c0: 68db ldr r3, [r3, #12]
|
|
800b5c2: f003 0370 and.w r3, r3, #112 @ 0x70
|
|
}
|
|
800b5c6: 4618 mov r0, r3
|
|
800b5c8: 46bd mov sp, r7
|
|
800b5ca: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b5ce: 4770 bx lr
|
|
|
|
0800b5d0 <LL_RCC_PLL_GetMainSource>:
|
|
* @arg @ref LL_RCC_PLLSOURCE_MSI
|
|
* @arg @ref LL_RCC_PLLSOURCE_HSI
|
|
* @arg @ref LL_RCC_PLLSOURCE_HSE
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
|
|
{
|
|
800b5d0: b480 push {r7}
|
|
800b5d2: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
|
|
800b5d4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b5d8: 68db ldr r3, [r3, #12]
|
|
800b5da: f003 0303 and.w r3, r3, #3
|
|
}
|
|
800b5de: 4618 mov r0, r3
|
|
800b5e0: 46bd mov sp, r7
|
|
800b5e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b5e6: 4770 bx lr
|
|
|
|
0800b5e8 <LL_RCC_IsActiveFlag_HPRE>:
|
|
* @brief Check if HCLK1 prescaler flag value has been applied or not
|
|
* @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void)
|
|
{
|
|
800b5e8: b480 push {r7}
|
|
800b5ea: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL);
|
|
800b5ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b5f0: 689b ldr r3, [r3, #8]
|
|
800b5f2: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
800b5f6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800b5fa: d101 bne.n 800b600 <LL_RCC_IsActiveFlag_HPRE+0x18>
|
|
800b5fc: 2301 movs r3, #1
|
|
800b5fe: e000 b.n 800b602 <LL_RCC_IsActiveFlag_HPRE+0x1a>
|
|
800b600: 2300 movs r3, #0
|
|
}
|
|
800b602: 4618 mov r0, r3
|
|
800b604: 46bd mov sp, r7
|
|
800b606: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b60a: 4770 bx lr
|
|
|
|
0800b60c <LL_RCC_IsActiveFlag_C2HPRE>:
|
|
* @brief Check if HCLK2 prescaler flag value has been applied or not
|
|
* @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void)
|
|
{
|
|
800b60c: b480 push {r7}
|
|
800b60e: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL);
|
|
800b610: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b614: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
800b618: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800b61c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
|
|
800b620: d101 bne.n 800b626 <LL_RCC_IsActiveFlag_C2HPRE+0x1a>
|
|
800b622: 2301 movs r3, #1
|
|
800b624: e000 b.n 800b628 <LL_RCC_IsActiveFlag_C2HPRE+0x1c>
|
|
800b626: 2300 movs r3, #0
|
|
}
|
|
800b628: 4618 mov r0, r3
|
|
800b62a: 46bd mov sp, r7
|
|
800b62c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b630: 4770 bx lr
|
|
|
|
0800b632 <LL_RCC_IsActiveFlag_SHDHPRE>:
|
|
* @brief Check if HCLK4 prescaler flag value has been applied or not
|
|
* @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void)
|
|
{
|
|
800b632: b480 push {r7}
|
|
800b634: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL);
|
|
800b636: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b63a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
|
|
800b63e: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
800b642: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800b646: d101 bne.n 800b64c <LL_RCC_IsActiveFlag_SHDHPRE+0x1a>
|
|
800b648: 2301 movs r3, #1
|
|
800b64a: e000 b.n 800b64e <LL_RCC_IsActiveFlag_SHDHPRE+0x1c>
|
|
800b64c: 2300 movs r3, #0
|
|
}
|
|
800b64e: 4618 mov r0, r3
|
|
800b650: 46bd mov sp, r7
|
|
800b652: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b656: 4770 bx lr
|
|
|
|
0800b658 <LL_RCC_IsActiveFlag_PPRE1>:
|
|
* @brief Check if PLCK1 prescaler flag value has been applied or not
|
|
* @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void)
|
|
{
|
|
800b658: b480 push {r7}
|
|
800b65a: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL);
|
|
800b65c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b660: 689b ldr r3, [r3, #8]
|
|
800b662: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800b666: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
|
|
800b66a: d101 bne.n 800b670 <LL_RCC_IsActiveFlag_PPRE1+0x18>
|
|
800b66c: 2301 movs r3, #1
|
|
800b66e: e000 b.n 800b672 <LL_RCC_IsActiveFlag_PPRE1+0x1a>
|
|
800b670: 2300 movs r3, #0
|
|
}
|
|
800b672: 4618 mov r0, r3
|
|
800b674: 46bd mov sp, r7
|
|
800b676: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b67a: 4770 bx lr
|
|
|
|
0800b67c <LL_RCC_IsActiveFlag_PPRE2>:
|
|
* @brief Check if PLCK2 prescaler flag value has been applied or not
|
|
* @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void)
|
|
{
|
|
800b67c: b480 push {r7}
|
|
800b67e: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL);
|
|
800b680: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800b684: 689b ldr r3, [r3, #8]
|
|
800b686: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
800b68a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
800b68e: d101 bne.n 800b694 <LL_RCC_IsActiveFlag_PPRE2+0x18>
|
|
800b690: 2301 movs r3, #1
|
|
800b692: e000 b.n 800b696 <LL_RCC_IsActiveFlag_PPRE2+0x1a>
|
|
800b694: 2300 movs r3, #0
|
|
}
|
|
800b696: 4618 mov r0, r3
|
|
800b698: 46bd mov sp, r7
|
|
800b69a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b69e: 4770 bx lr
|
|
|
|
0800b6a0 <HAL_RCC_OscConfig>:
|
|
* @note The PLL is not disabled when used as system clock.
|
|
* @note The PLL source is not updated when used as PLLSAI1 clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
800b6a0: b590 push {r4, r7, lr}
|
|
800b6a2: b08d sub sp, #52 @ 0x34
|
|
800b6a4: af00 add r7, sp, #0
|
|
800b6a6: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
800b6a8: 687b ldr r3, [r7, #4]
|
|
800b6aa: 2b00 cmp r3, #0
|
|
800b6ac: d101 bne.n 800b6b2 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800b6ae: 2301 movs r3, #1
|
|
800b6b0: e363 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
800b6b2: 687b ldr r3, [r7, #4]
|
|
800b6b4: 681b ldr r3, [r3, #0]
|
|
800b6b6: f003 0320 and.w r3, r3, #32
|
|
800b6ba: 2b00 cmp r3, #0
|
|
800b6bc: f000 808d beq.w 800b7da <HAL_RCC_OscConfig+0x13a>
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* When the MSI is used as system clock it will not be disabled */
|
|
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
800b6c0: f7ff fe7d bl 800b3be <LL_RCC_GetSysClkSource>
|
|
800b6c4: 62f8 str r0, [r7, #44] @ 0x2c
|
|
const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
800b6c6: f7ff ff83 bl 800b5d0 <LL_RCC_PLL_GetMainSource>
|
|
800b6ca: 62b8 str r0, [r7, #40] @ 0x28
|
|
if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) ||
|
|
800b6cc: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800b6ce: 2b00 cmp r3, #0
|
|
800b6d0: d005 beq.n 800b6de <HAL_RCC_OscConfig+0x3e>
|
|
800b6d2: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800b6d4: 2b0c cmp r3, #12
|
|
800b6d6: d147 bne.n 800b768 <HAL_RCC_OscConfig+0xc8>
|
|
((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_MSI)))
|
|
800b6d8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800b6da: 2b01 cmp r3, #1
|
|
800b6dc: d144 bne.n 800b768 <HAL_RCC_OscConfig+0xc8>
|
|
{
|
|
if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)
|
|
800b6de: 687b ldr r3, [r7, #4]
|
|
800b6e0: 69db ldr r3, [r3, #28]
|
|
800b6e2: 2b00 cmp r3, #0
|
|
800b6e4: d101 bne.n 800b6ea <HAL_RCC_OscConfig+0x4a>
|
|
{
|
|
return HAL_ERROR;
|
|
800b6e6: 2301 movs r3, #1
|
|
800b6e8: e347 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
else
|
|
{
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the AHB4 clock
|
|
and the supply voltage of the device. */
|
|
if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
800b6ea: 687b ldr r3, [r7, #4]
|
|
800b6ec: 6a5c ldr r4, [r3, #36] @ 0x24
|
|
800b6ee: f7ff fe28 bl 800b342 <LL_RCC_MSI_GetRange>
|
|
800b6f2: 4603 mov r3, r0
|
|
800b6f4: 429c cmp r4, r3
|
|
800b6f6: d914 bls.n 800b722 <HAL_RCC_OscConfig+0x82>
|
|
{
|
|
/* First increase number of wait states update if necessary */
|
|
if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
800b6f8: 687b ldr r3, [r7, #4]
|
|
800b6fa: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800b6fc: 4618 mov r0, r3
|
|
800b6fe: f000 fd4b bl 800c198 <RCC_SetFlashLatencyFromMSIRange>
|
|
800b702: 4603 mov r3, r0
|
|
800b704: 2b00 cmp r3, #0
|
|
800b706: d001 beq.n 800b70c <HAL_RCC_OscConfig+0x6c>
|
|
{
|
|
return HAL_ERROR;
|
|
800b708: 2301 movs r3, #1
|
|
800b70a: e336 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
800b70c: 687b ldr r3, [r7, #4]
|
|
800b70e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800b710: 4618 mov r0, r3
|
|
800b712: f7ff fe02 bl 800b31a <LL_RCC_MSI_SetRange>
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
800b716: 687b ldr r3, [r7, #4]
|
|
800b718: 6a1b ldr r3, [r3, #32]
|
|
800b71a: 4618 mov r0, r3
|
|
800b71c: f7ff fe26 bl 800b36c <LL_RCC_MSI_SetCalibTrimming>
|
|
800b720: e013 b.n 800b74a <HAL_RCC_OscConfig+0xaa>
|
|
}
|
|
else
|
|
{
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
800b722: 687b ldr r3, [r7, #4]
|
|
800b724: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800b726: 4618 mov r0, r3
|
|
800b728: f7ff fdf7 bl 800b31a <LL_RCC_MSI_SetRange>
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
800b72c: 687b ldr r3, [r7, #4]
|
|
800b72e: 6a1b ldr r3, [r3, #32]
|
|
800b730: 4618 mov r0, r3
|
|
800b732: f7ff fe1b bl 800b36c <LL_RCC_MSI_SetCalibTrimming>
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
800b736: 687b ldr r3, [r7, #4]
|
|
800b738: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800b73a: 4618 mov r0, r3
|
|
800b73c: f000 fd2c bl 800c198 <RCC_SetFlashLatencyFromMSIRange>
|
|
800b740: 4603 mov r3, r0
|
|
800b742: 2b00 cmp r3, #0
|
|
800b744: d001 beq.n 800b74a <HAL_RCC_OscConfig+0xaa>
|
|
{
|
|
return HAL_ERROR;
|
|
800b746: 2301 movs r3, #1
|
|
800b748: e317 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
}
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetHCLKFreq();
|
|
800b74a: f000 fcc9 bl 800c0e0 <HAL_RCC_GetHCLKFreq>
|
|
800b74e: 4603 mov r3, r0
|
|
800b750: 4aa4 ldr r2, [pc, #656] @ (800b9e4 <HAL_RCC_OscConfig+0x344>)
|
|
800b752: 6013 str r3, [r2, #0]
|
|
|
|
if (HAL_InitTick(uwTickPrio) != HAL_OK)
|
|
800b754: 4ba4 ldr r3, [pc, #656] @ (800b9e8 <HAL_RCC_OscConfig+0x348>)
|
|
800b756: 681b ldr r3, [r3, #0]
|
|
800b758: 4618 mov r0, r3
|
|
800b75a: f7fa fe9f bl 800649c <HAL_InitTick>
|
|
800b75e: 4603 mov r3, r0
|
|
800b760: 2b00 cmp r3, #0
|
|
800b762: d039 beq.n 800b7d8 <HAL_RCC_OscConfig+0x138>
|
|
{
|
|
return HAL_ERROR;
|
|
800b764: 2301 movs r3, #1
|
|
800b766: e308 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the MSI State */
|
|
if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
800b768: 687b ldr r3, [r7, #4]
|
|
800b76a: 69db ldr r3, [r3, #28]
|
|
800b76c: 2b00 cmp r3, #0
|
|
800b76e: d01e beq.n 800b7ae <HAL_RCC_OscConfig+0x10e>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_ENABLE();
|
|
800b770: f7ff fda4 bl 800b2bc <LL_RCC_MSI_Enable>
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
800b774: f7fb f8fa bl 800696c <HAL_GetTick>
|
|
800b778: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till MSI is ready */
|
|
while (LL_RCC_MSI_IsReady() == 0U)
|
|
800b77a: e008 b.n 800b78e <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
800b77c: f7fb f8f6 bl 800696c <HAL_GetTick>
|
|
800b780: 4602 mov r2, r0
|
|
800b782: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b784: 1ad3 subs r3, r2, r3
|
|
800b786: 2b02 cmp r3, #2
|
|
800b788: d901 bls.n 800b78e <HAL_RCC_OscConfig+0xee>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b78a: 2303 movs r3, #3
|
|
800b78c: e2f5 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_MSI_IsReady() == 0U)
|
|
800b78e: f7ff fdb3 bl 800b2f8 <LL_RCC_MSI_IsReady>
|
|
800b792: 4603 mov r3, r0
|
|
800b794: 2b00 cmp r3, #0
|
|
800b796: d0f1 beq.n 800b77c <HAL_RCC_OscConfig+0xdc>
|
|
}
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
800b798: 687b ldr r3, [r7, #4]
|
|
800b79a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800b79c: 4618 mov r0, r3
|
|
800b79e: f7ff fdbc bl 800b31a <LL_RCC_MSI_SetRange>
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
800b7a2: 687b ldr r3, [r7, #4]
|
|
800b7a4: 6a1b ldr r3, [r3, #32]
|
|
800b7a6: 4618 mov r0, r3
|
|
800b7a8: f7ff fde0 bl 800b36c <LL_RCC_MSI_SetCalibTrimming>
|
|
800b7ac: e015 b.n 800b7da <HAL_RCC_OscConfig+0x13a>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_DISABLE();
|
|
800b7ae: f7ff fd94 bl 800b2da <LL_RCC_MSI_Disable>
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
800b7b2: f7fb f8db bl 800696c <HAL_GetTick>
|
|
800b7b6: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till MSI is disabled */
|
|
while (LL_RCC_MSI_IsReady() != 0U)
|
|
800b7b8: e008 b.n 800b7cc <HAL_RCC_OscConfig+0x12c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
800b7ba: f7fb f8d7 bl 800696c <HAL_GetTick>
|
|
800b7be: 4602 mov r2, r0
|
|
800b7c0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b7c2: 1ad3 subs r3, r2, r3
|
|
800b7c4: 2b02 cmp r3, #2
|
|
800b7c6: d901 bls.n 800b7cc <HAL_RCC_OscConfig+0x12c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b7c8: 2303 movs r3, #3
|
|
800b7ca: e2d6 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_MSI_IsReady() != 0U)
|
|
800b7cc: f7ff fd94 bl 800b2f8 <LL_RCC_MSI_IsReady>
|
|
800b7d0: 4603 mov r3, r0
|
|
800b7d2: 2b00 cmp r3, #0
|
|
800b7d4: d1f1 bne.n 800b7ba <HAL_RCC_OscConfig+0x11a>
|
|
800b7d6: e000 b.n 800b7da <HAL_RCC_OscConfig+0x13a>
|
|
if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)
|
|
800b7d8: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
800b7da: 687b ldr r3, [r7, #4]
|
|
800b7dc: 681b ldr r3, [r3, #0]
|
|
800b7de: f003 0301 and.w r3, r3, #1
|
|
800b7e2: 2b00 cmp r3, #0
|
|
800b7e4: d047 beq.n 800b876 <HAL_RCC_OscConfig+0x1d6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
800b7e6: f7ff fdea bl 800b3be <LL_RCC_GetSysClkSource>
|
|
800b7ea: 6238 str r0, [r7, #32]
|
|
const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
800b7ec: f7ff fef0 bl 800b5d0 <LL_RCC_PLL_GetMainSource>
|
|
800b7f0: 61f8 str r0, [r7, #28]
|
|
if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) ||
|
|
800b7f2: 6a3b ldr r3, [r7, #32]
|
|
800b7f4: 2b08 cmp r3, #8
|
|
800b7f6: d005 beq.n 800b804 <HAL_RCC_OscConfig+0x164>
|
|
800b7f8: 6a3b ldr r3, [r7, #32]
|
|
800b7fa: 2b0c cmp r3, #12
|
|
800b7fc: d108 bne.n 800b810 <HAL_RCC_OscConfig+0x170>
|
|
((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSE)))
|
|
800b7fe: 69fb ldr r3, [r7, #28]
|
|
800b800: 2b03 cmp r3, #3
|
|
800b802: d105 bne.n 800b810 <HAL_RCC_OscConfig+0x170>
|
|
{
|
|
if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
|
|
800b804: 687b ldr r3, [r7, #4]
|
|
800b806: 685b ldr r3, [r3, #4]
|
|
800b808: 2b00 cmp r3, #0
|
|
800b80a: d134 bne.n 800b876 <HAL_RCC_OscConfig+0x1d6>
|
|
{
|
|
return HAL_ERROR;
|
|
800b80c: 2301 movs r3, #1
|
|
800b80e: e2b4 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
800b810: 687b ldr r3, [r7, #4]
|
|
800b812: 685b ldr r3, [r3, #4]
|
|
800b814: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800b818: d102 bne.n 800b820 <HAL_RCC_OscConfig+0x180>
|
|
800b81a: f7ff fbd1 bl 800afc0 <LL_RCC_HSE_Enable>
|
|
800b81e: e001 b.n 800b824 <HAL_RCC_OscConfig+0x184>
|
|
800b820: f7ff fbdd bl 800afde <LL_RCC_HSE_Disable>
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
800b824: 687b ldr r3, [r7, #4]
|
|
800b826: 685b ldr r3, [r3, #4]
|
|
800b828: 2b00 cmp r3, #0
|
|
800b82a: d012 beq.n 800b852 <HAL_RCC_OscConfig+0x1b2>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800b82c: f7fb f89e bl 800696c <HAL_GetTick>
|
|
800b830: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till HSE is ready */
|
|
while (LL_RCC_HSE_IsReady() == 0U)
|
|
800b832: e008 b.n 800b846 <HAL_RCC_OscConfig+0x1a6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
800b834: f7fb f89a bl 800696c <HAL_GetTick>
|
|
800b838: 4602 mov r2, r0
|
|
800b83a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b83c: 1ad3 subs r3, r2, r3
|
|
800b83e: 2b64 cmp r3, #100 @ 0x64
|
|
800b840: d901 bls.n 800b846 <HAL_RCC_OscConfig+0x1a6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b842: 2303 movs r3, #3
|
|
800b844: e299 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_HSE_IsReady() == 0U)
|
|
800b846: f7ff fbd9 bl 800affc <LL_RCC_HSE_IsReady>
|
|
800b84a: 4603 mov r3, r0
|
|
800b84c: 2b00 cmp r3, #0
|
|
800b84e: d0f1 beq.n 800b834 <HAL_RCC_OscConfig+0x194>
|
|
800b850: e011 b.n 800b876 <HAL_RCC_OscConfig+0x1d6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800b852: f7fb f88b bl 800696c <HAL_GetTick>
|
|
800b856: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (LL_RCC_HSE_IsReady() != 0U)
|
|
800b858: e008 b.n 800b86c <HAL_RCC_OscConfig+0x1cc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
800b85a: f7fb f887 bl 800696c <HAL_GetTick>
|
|
800b85e: 4602 mov r2, r0
|
|
800b860: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b862: 1ad3 subs r3, r2, r3
|
|
800b864: 2b64 cmp r3, #100 @ 0x64
|
|
800b866: d901 bls.n 800b86c <HAL_RCC_OscConfig+0x1cc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b868: 2303 movs r3, #3
|
|
800b86a: e286 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_HSE_IsReady() != 0U)
|
|
800b86c: f7ff fbc6 bl 800affc <LL_RCC_HSE_IsReady>
|
|
800b870: 4603 mov r3, r0
|
|
800b872: 2b00 cmp r3, #0
|
|
800b874: d1f1 bne.n 800b85a <HAL_RCC_OscConfig+0x1ba>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
800b876: 687b ldr r3, [r7, #4]
|
|
800b878: 681b ldr r3, [r3, #0]
|
|
800b87a: f003 0302 and.w r3, r3, #2
|
|
800b87e: 2b00 cmp r3, #0
|
|
800b880: d04c beq.n 800b91c <HAL_RCC_OscConfig+0x27c>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
800b882: f7ff fd9c bl 800b3be <LL_RCC_GetSysClkSource>
|
|
800b886: 61b8 str r0, [r7, #24]
|
|
const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
800b888: f7ff fea2 bl 800b5d0 <LL_RCC_PLL_GetMainSource>
|
|
800b88c: 6178 str r0, [r7, #20]
|
|
if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) ||
|
|
800b88e: 69bb ldr r3, [r7, #24]
|
|
800b890: 2b04 cmp r3, #4
|
|
800b892: d005 beq.n 800b8a0 <HAL_RCC_OscConfig+0x200>
|
|
800b894: 69bb ldr r3, [r7, #24]
|
|
800b896: 2b0c cmp r3, #12
|
|
800b898: d10e bne.n 800b8b8 <HAL_RCC_OscConfig+0x218>
|
|
((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSI)))
|
|
800b89a: 697b ldr r3, [r7, #20]
|
|
800b89c: 2b02 cmp r3, #2
|
|
800b89e: d10b bne.n 800b8b8 <HAL_RCC_OscConfig+0x218>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
|
|
800b8a0: 687b ldr r3, [r7, #4]
|
|
800b8a2: 68db ldr r3, [r3, #12]
|
|
800b8a4: 2b00 cmp r3, #0
|
|
800b8a6: d101 bne.n 800b8ac <HAL_RCC_OscConfig+0x20c>
|
|
{
|
|
return HAL_ERROR;
|
|
800b8a8: 2301 movs r3, #1
|
|
800b8aa: e266 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
800b8ac: 687b ldr r3, [r7, #4]
|
|
800b8ae: 691b ldr r3, [r3, #16]
|
|
800b8b0: 4618 mov r0, r3
|
|
800b8b2: f7ff fbe5 bl 800b080 <LL_RCC_HSI_SetCalibTrimming>
|
|
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
|
|
800b8b6: e031 b.n 800b91c <HAL_RCC_OscConfig+0x27c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
800b8b8: 687b ldr r3, [r7, #4]
|
|
800b8ba: 68db ldr r3, [r3, #12]
|
|
800b8bc: 2b00 cmp r3, #0
|
|
800b8be: d019 beq.n 800b8f4 <HAL_RCC_OscConfig+0x254>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
800b8c0: f7ff fbae bl 800b020 <LL_RCC_HSI_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800b8c4: f7fb f852 bl 800696c <HAL_GetTick>
|
|
800b8c8: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till HSI is ready */
|
|
while (LL_RCC_HSI_IsReady() == 0U)
|
|
800b8ca: e008 b.n 800b8de <HAL_RCC_OscConfig+0x23e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
800b8cc: f7fb f84e bl 800696c <HAL_GetTick>
|
|
800b8d0: 4602 mov r2, r0
|
|
800b8d2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b8d4: 1ad3 subs r3, r2, r3
|
|
800b8d6: 2b02 cmp r3, #2
|
|
800b8d8: d901 bls.n 800b8de <HAL_RCC_OscConfig+0x23e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b8da: 2303 movs r3, #3
|
|
800b8dc: e24d b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_HSI_IsReady() == 0U)
|
|
800b8de: f7ff fbbd bl 800b05c <LL_RCC_HSI_IsReady>
|
|
800b8e2: 4603 mov r3, r0
|
|
800b8e4: 2b00 cmp r3, #0
|
|
800b8e6: d0f1 beq.n 800b8cc <HAL_RCC_OscConfig+0x22c>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
800b8e8: 687b ldr r3, [r7, #4]
|
|
800b8ea: 691b ldr r3, [r3, #16]
|
|
800b8ec: 4618 mov r0, r3
|
|
800b8ee: f7ff fbc7 bl 800b080 <LL_RCC_HSI_SetCalibTrimming>
|
|
800b8f2: e013 b.n 800b91c <HAL_RCC_OscConfig+0x27c>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
800b8f4: f7ff fba3 bl 800b03e <LL_RCC_HSI_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800b8f8: f7fb f838 bl 800696c <HAL_GetTick>
|
|
800b8fc: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (LL_RCC_HSI_IsReady() != 0U)
|
|
800b8fe: e008 b.n 800b912 <HAL_RCC_OscConfig+0x272>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
800b900: f7fb f834 bl 800696c <HAL_GetTick>
|
|
800b904: 4602 mov r2, r0
|
|
800b906: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b908: 1ad3 subs r3, r2, r3
|
|
800b90a: 2b02 cmp r3, #2
|
|
800b90c: d901 bls.n 800b912 <HAL_RCC_OscConfig+0x272>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b90e: 2303 movs r3, #3
|
|
800b910: e233 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_HSI_IsReady() != 0U)
|
|
800b912: f7ff fba3 bl 800b05c <LL_RCC_HSI_IsReady>
|
|
800b916: 4603 mov r3, r0
|
|
800b918: 2b00 cmp r3, #0
|
|
800b91a: d1f1 bne.n 800b900 <HAL_RCC_OscConfig+0x260>
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration (LSI1 or LSI2) -------------------------*/
|
|
|
|
if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
|
|
800b91c: 687b ldr r3, [r7, #4]
|
|
800b91e: 681b ldr r3, [r3, #0]
|
|
800b920: f003 0308 and.w r3, r3, #8
|
|
800b924: 2b00 cmp r3, #0
|
|
800b926: d106 bne.n 800b936 <HAL_RCC_OscConfig+0x296>
|
|
(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2))
|
|
800b928: 687b ldr r3, [r7, #4]
|
|
800b92a: 681b ldr r3, [r3, #0]
|
|
800b92c: f003 0310 and.w r3, r3, #16
|
|
if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
|
|
800b930: 2b00 cmp r3, #0
|
|
800b932: f000 80a3 beq.w 800ba7c <HAL_RCC_OscConfig+0x3dc>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
800b936: 687b ldr r3, [r7, #4]
|
|
800b938: 695b ldr r3, [r3, #20]
|
|
800b93a: 2b00 cmp r3, #0
|
|
800b93c: d076 beq.n 800ba2c <HAL_RCC_OscConfig+0x38c>
|
|
{
|
|
/*------------------------------ LSI2 selected by default (when Switch ON) -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2)
|
|
800b93e: 687b ldr r3, [r7, #4]
|
|
800b940: 681b ldr r3, [r3, #0]
|
|
800b942: f003 0310 and.w r3, r3, #16
|
|
800b946: 2b00 cmp r3, #0
|
|
800b948: d046 beq.n 800b9d8 <HAL_RCC_OscConfig+0x338>
|
|
{
|
|
assert_param(IS_RCC_LSI2_CALIBRATION_VALUE(RCC_OscInitStruct->LSI2CalibrationValue));
|
|
|
|
/* 1. Check LSI1 state and enable if required */
|
|
if (LL_RCC_LSI1_IsReady() == 0U)
|
|
800b94a: f7ff fc5a bl 800b202 <LL_RCC_LSI1_IsReady>
|
|
800b94e: 4603 mov r3, r0
|
|
800b950: 2b00 cmp r3, #0
|
|
800b952: d113 bne.n 800b97c <HAL_RCC_OscConfig+0x2dc>
|
|
{
|
|
/* This is required to enable LSI1 before enabling LSI2 */
|
|
__HAL_RCC_LSI1_ENABLE();
|
|
800b954: f7ff fc33 bl 800b1be <LL_RCC_LSI1_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800b958: f7fb f808 bl 800696c <HAL_GetTick>
|
|
800b95c: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSI1 is ready */
|
|
while (LL_RCC_LSI1_IsReady() == 0U)
|
|
800b95e: e008 b.n 800b972 <HAL_RCC_OscConfig+0x2d2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
|
|
800b960: f7fb f804 bl 800696c <HAL_GetTick>
|
|
800b964: 4602 mov r2, r0
|
|
800b966: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b968: 1ad3 subs r3, r2, r3
|
|
800b96a: 2b02 cmp r3, #2
|
|
800b96c: d901 bls.n 800b972 <HAL_RCC_OscConfig+0x2d2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b96e: 2303 movs r3, #3
|
|
800b970: e203 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSI1_IsReady() == 0U)
|
|
800b972: f7ff fc46 bl 800b202 <LL_RCC_LSI1_IsReady>
|
|
800b976: 4603 mov r3, r0
|
|
800b978: 2b00 cmp r3, #0
|
|
800b97a: d0f1 beq.n 800b960 <HAL_RCC_OscConfig+0x2c0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* 2. Enable the Internal Low Speed oscillator (LSI2) and set trimming value */
|
|
__HAL_RCC_LSI2_ENABLE();
|
|
800b97c: f7ff fc53 bl 800b226 <LL_RCC_LSI2_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800b980: f7fa fff4 bl 800696c <HAL_GetTick>
|
|
800b984: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSI2 is ready */
|
|
while (LL_RCC_LSI2_IsReady() == 0U)
|
|
800b986: e008 b.n 800b99a <HAL_RCC_OscConfig+0x2fa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
|
|
800b988: f7fa fff0 bl 800696c <HAL_GetTick>
|
|
800b98c: 4602 mov r2, r0
|
|
800b98e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b990: 1ad3 subs r3, r2, r3
|
|
800b992: 2b03 cmp r3, #3
|
|
800b994: d901 bls.n 800b99a <HAL_RCC_OscConfig+0x2fa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b996: 2303 movs r3, #3
|
|
800b998: e1ef b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSI2_IsReady() == 0U)
|
|
800b99a: f7ff fc66 bl 800b26a <LL_RCC_LSI2_IsReady>
|
|
800b99e: 4603 mov r3, r0
|
|
800b9a0: 2b00 cmp r3, #0
|
|
800b9a2: d0f1 beq.n 800b988 <HAL_RCC_OscConfig+0x2e8>
|
|
}
|
|
}
|
|
/* Adjusts the Internal Low Spee oscillator (LSI2) calibration value */
|
|
__HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->LSI2CalibrationValue);
|
|
800b9a4: 687b ldr r3, [r7, #4]
|
|
800b9a6: 699b ldr r3, [r3, #24]
|
|
800b9a8: 4618 mov r0, r3
|
|
800b9aa: f7ff fc70 bl 800b28e <LL_RCC_LSI2_SetTrimming>
|
|
|
|
/* 3. Disable LSI1 */
|
|
|
|
/* LSI1 was initially not enable, require to disable it */
|
|
__HAL_RCC_LSI1_DISABLE();
|
|
800b9ae: f7ff fc17 bl 800b1e0 <LL_RCC_LSI1_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800b9b2: f7fa ffdb bl 800696c <HAL_GetTick>
|
|
800b9b6: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSI1 is disabled */
|
|
while (LL_RCC_LSI1_IsReady() != 0U)
|
|
800b9b8: e008 b.n 800b9cc <HAL_RCC_OscConfig+0x32c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
|
|
800b9ba: f7fa ffd7 bl 800696c <HAL_GetTick>
|
|
800b9be: 4602 mov r2, r0
|
|
800b9c0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b9c2: 1ad3 subs r3, r2, r3
|
|
800b9c4: 2b02 cmp r3, #2
|
|
800b9c6: d901 bls.n 800b9cc <HAL_RCC_OscConfig+0x32c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b9c8: 2303 movs r3, #3
|
|
800b9ca: e1d6 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSI1_IsReady() != 0U)
|
|
800b9cc: f7ff fc19 bl 800b202 <LL_RCC_LSI1_IsReady>
|
|
800b9d0: 4603 mov r3, r0
|
|
800b9d2: 2b00 cmp r3, #0
|
|
800b9d4: d1f1 bne.n 800b9ba <HAL_RCC_OscConfig+0x31a>
|
|
800b9d6: e051 b.n 800ba7c <HAL_RCC_OscConfig+0x3dc>
|
|
else
|
|
{
|
|
/*------------------------------ LSI1 selected (only if LSI2 OFF)-------------------------*/
|
|
|
|
/* 1. Enable the Internal Low Speed oscillator (LSI1). */
|
|
__HAL_RCC_LSI1_ENABLE();
|
|
800b9d8: f7ff fbf1 bl 800b1be <LL_RCC_LSI1_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800b9dc: f7fa ffc6 bl 800696c <HAL_GetTick>
|
|
800b9e0: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSI1 is ready */
|
|
while (LL_RCC_LSI1_IsReady() == 0U)
|
|
800b9e2: e00c b.n 800b9fe <HAL_RCC_OscConfig+0x35e>
|
|
800b9e4: 2000000c .word 0x2000000c
|
|
800b9e8: 20000010 .word 0x20000010
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
|
|
800b9ec: f7fa ffbe bl 800696c <HAL_GetTick>
|
|
800b9f0: 4602 mov r2, r0
|
|
800b9f2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b9f4: 1ad3 subs r3, r2, r3
|
|
800b9f6: 2b02 cmp r3, #2
|
|
800b9f8: d901 bls.n 800b9fe <HAL_RCC_OscConfig+0x35e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800b9fa: 2303 movs r3, #3
|
|
800b9fc: e1bd b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSI1_IsReady() == 0U)
|
|
800b9fe: f7ff fc00 bl 800b202 <LL_RCC_LSI1_IsReady>
|
|
800ba02: 4603 mov r3, r0
|
|
800ba04: 2b00 cmp r3, #0
|
|
800ba06: d0f1 beq.n 800b9ec <HAL_RCC_OscConfig+0x34c>
|
|
}
|
|
}
|
|
/*2. Switch OFF LSI2*/
|
|
|
|
/* Disable the Internal Low Speed oscillator (LSI2). */
|
|
__HAL_RCC_LSI2_DISABLE();
|
|
800ba08: f7ff fc1e bl 800b248 <LL_RCC_LSI2_Disable>
|
|
|
|
/* Wait till LSI2 is disabled */
|
|
while (LL_RCC_LSI2_IsReady() != 0U)
|
|
800ba0c: e008 b.n 800ba20 <HAL_RCC_OscConfig+0x380>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
|
|
800ba0e: f7fa ffad bl 800696c <HAL_GetTick>
|
|
800ba12: 4602 mov r2, r0
|
|
800ba14: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800ba16: 1ad3 subs r3, r2, r3
|
|
800ba18: 2b03 cmp r3, #3
|
|
800ba1a: d901 bls.n 800ba20 <HAL_RCC_OscConfig+0x380>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800ba1c: 2303 movs r3, #3
|
|
800ba1e: e1ac b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSI2_IsReady() != 0U)
|
|
800ba20: f7ff fc23 bl 800b26a <LL_RCC_LSI2_IsReady>
|
|
800ba24: 4603 mov r3, r0
|
|
800ba26: 2b00 cmp r3, #0
|
|
800ba28: d1f1 bne.n 800ba0e <HAL_RCC_OscConfig+0x36e>
|
|
800ba2a: e027 b.n 800ba7c <HAL_RCC_OscConfig+0x3dc>
|
|
}
|
|
else
|
|
{
|
|
|
|
/* Disable the Internal Low Speed oscillator (LSI2). */
|
|
__HAL_RCC_LSI2_DISABLE();
|
|
800ba2c: f7ff fc0c bl 800b248 <LL_RCC_LSI2_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800ba30: f7fa ff9c bl 800696c <HAL_GetTick>
|
|
800ba34: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSI2 is disabled */
|
|
while (LL_RCC_LSI2_IsReady() != 0U)
|
|
800ba36: e008 b.n 800ba4a <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
|
|
800ba38: f7fa ff98 bl 800696c <HAL_GetTick>
|
|
800ba3c: 4602 mov r2, r0
|
|
800ba3e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800ba40: 1ad3 subs r3, r2, r3
|
|
800ba42: 2b03 cmp r3, #3
|
|
800ba44: d901 bls.n 800ba4a <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800ba46: 2303 movs r3, #3
|
|
800ba48: e197 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSI2_IsReady() != 0U)
|
|
800ba4a: f7ff fc0e bl 800b26a <LL_RCC_LSI2_IsReady>
|
|
800ba4e: 4603 mov r3, r0
|
|
800ba50: 2b00 cmp r3, #0
|
|
800ba52: d1f1 bne.n 800ba38 <HAL_RCC_OscConfig+0x398>
|
|
}
|
|
}
|
|
|
|
/* Disable the Internal Low Speed oscillator (LSI1). */
|
|
__HAL_RCC_LSI1_DISABLE();
|
|
800ba54: f7ff fbc4 bl 800b1e0 <LL_RCC_LSI1_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800ba58: f7fa ff88 bl 800696c <HAL_GetTick>
|
|
800ba5c: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSI1 is disabled */
|
|
while (LL_RCC_LSI1_IsReady() != 0U)
|
|
800ba5e: e008 b.n 800ba72 <HAL_RCC_OscConfig+0x3d2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
|
|
800ba60: f7fa ff84 bl 800696c <HAL_GetTick>
|
|
800ba64: 4602 mov r2, r0
|
|
800ba66: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800ba68: 1ad3 subs r3, r2, r3
|
|
800ba6a: 2b02 cmp r3, #2
|
|
800ba6c: d901 bls.n 800ba72 <HAL_RCC_OscConfig+0x3d2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800ba6e: 2303 movs r3, #3
|
|
800ba70: e183 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSI1_IsReady() != 0U)
|
|
800ba72: f7ff fbc6 bl 800b202 <LL_RCC_LSI1_IsReady>
|
|
800ba76: 4603 mov r3, r0
|
|
800ba78: 2b00 cmp r3, #0
|
|
800ba7a: d1f1 bne.n 800ba60 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
800ba7c: 687b ldr r3, [r7, #4]
|
|
800ba7e: 681b ldr r3, [r3, #0]
|
|
800ba80: f003 0304 and.w r3, r3, #4
|
|
800ba84: 2b00 cmp r3, #0
|
|
800ba86: d05b beq.n 800bb40 <HAL_RCC_OscConfig+0x4a0>
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
800ba88: 4ba7 ldr r3, [pc, #668] @ (800bd28 <HAL_RCC_OscConfig+0x688>)
|
|
800ba8a: 681b ldr r3, [r3, #0]
|
|
800ba8c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800ba90: 2b00 cmp r3, #0
|
|
800ba92: d114 bne.n 800babe <HAL_RCC_OscConfig+0x41e>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
HAL_PWR_EnableBkUpAccess();
|
|
800ba94: f7ff fa54 bl 800af40 <HAL_PWR_EnableBkUpAccess>
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
800ba98: f7fa ff68 bl 800696c <HAL_GetTick>
|
|
800ba9c: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
800ba9e: e008 b.n 800bab2 <HAL_RCC_OscConfig+0x412>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800baa0: f7fa ff64 bl 800696c <HAL_GetTick>
|
|
800baa4: 4602 mov r2, r0
|
|
800baa6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800baa8: 1ad3 subs r3, r2, r3
|
|
800baaa: 2b02 cmp r3, #2
|
|
800baac: d901 bls.n 800bab2 <HAL_RCC_OscConfig+0x412>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800baae: 2303 movs r3, #3
|
|
800bab0: e163 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
800bab2: 4b9d ldr r3, [pc, #628] @ (800bd28 <HAL_RCC_OscConfig+0x688>)
|
|
800bab4: 681b ldr r3, [r3, #0]
|
|
800bab6: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800baba: 2b00 cmp r3, #0
|
|
800babc: d0f0 beq.n 800baa0 <HAL_RCC_OscConfig+0x400>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
800babe: 687b ldr r3, [r7, #4]
|
|
800bac0: 689b ldr r3, [r3, #8]
|
|
800bac2: 2b01 cmp r3, #1
|
|
800bac4: d102 bne.n 800bacc <HAL_RCC_OscConfig+0x42c>
|
|
800bac6: f7ff fb24 bl 800b112 <LL_RCC_LSE_Enable>
|
|
800baca: e00c b.n 800bae6 <HAL_RCC_OscConfig+0x446>
|
|
800bacc: 687b ldr r3, [r7, #4]
|
|
800bace: 689b ldr r3, [r3, #8]
|
|
800bad0: 2b05 cmp r3, #5
|
|
800bad2: d104 bne.n 800bade <HAL_RCC_OscConfig+0x43e>
|
|
800bad4: f7ff fb3f bl 800b156 <LL_RCC_LSE_EnableBypass>
|
|
800bad8: f7ff fb1b bl 800b112 <LL_RCC_LSE_Enable>
|
|
800badc: e003 b.n 800bae6 <HAL_RCC_OscConfig+0x446>
|
|
800bade: f7ff fb29 bl 800b134 <LL_RCC_LSE_Disable>
|
|
800bae2: f7ff fb49 bl 800b178 <LL_RCC_LSE_DisableBypass>
|
|
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
800bae6: 687b ldr r3, [r7, #4]
|
|
800bae8: 689b ldr r3, [r3, #8]
|
|
800baea: 2b00 cmp r3, #0
|
|
800baec: d014 beq.n 800bb18 <HAL_RCC_OscConfig+0x478>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800baee: f7fa ff3d bl 800696c <HAL_GetTick>
|
|
800baf2: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSE is ready */
|
|
while (LL_RCC_LSE_IsReady() == 0U)
|
|
800baf4: e00a b.n 800bb0c <HAL_RCC_OscConfig+0x46c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800baf6: f7fa ff39 bl 800696c <HAL_GetTick>
|
|
800bafa: 4602 mov r2, r0
|
|
800bafc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800bafe: 1ad3 subs r3, r2, r3
|
|
800bb00: f241 3288 movw r2, #5000 @ 0x1388
|
|
800bb04: 4293 cmp r3, r2
|
|
800bb06: d901 bls.n 800bb0c <HAL_RCC_OscConfig+0x46c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bb08: 2303 movs r3, #3
|
|
800bb0a: e136 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSE_IsReady() == 0U)
|
|
800bb0c: f7ff fb45 bl 800b19a <LL_RCC_LSE_IsReady>
|
|
800bb10: 4603 mov r3, r0
|
|
800bb12: 2b00 cmp r3, #0
|
|
800bb14: d0ef beq.n 800baf6 <HAL_RCC_OscConfig+0x456>
|
|
800bb16: e013 b.n 800bb40 <HAL_RCC_OscConfig+0x4a0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bb18: f7fa ff28 bl 800696c <HAL_GetTick>
|
|
800bb1c: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (LL_RCC_LSE_IsReady() != 0U)
|
|
800bb1e: e00a b.n 800bb36 <HAL_RCC_OscConfig+0x496>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800bb20: f7fa ff24 bl 800696c <HAL_GetTick>
|
|
800bb24: 4602 mov r2, r0
|
|
800bb26: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800bb28: 1ad3 subs r3, r2, r3
|
|
800bb2a: f241 3288 movw r2, #5000 @ 0x1388
|
|
800bb2e: 4293 cmp r3, r2
|
|
800bb30: d901 bls.n 800bb36 <HAL_RCC_OscConfig+0x496>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bb32: 2303 movs r3, #3
|
|
800bb34: e121 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_LSE_IsReady() != 0U)
|
|
800bb36: f7ff fb30 bl 800b19a <LL_RCC_LSE_IsReady>
|
|
800bb3a: 4603 mov r3, r0
|
|
800bb3c: 2b00 cmp r3, #0
|
|
800bb3e: d1ef bne.n 800bb20 <HAL_RCC_OscConfig+0x480>
|
|
}
|
|
|
|
}
|
|
#if defined(RCC_HSI48_SUPPORT)
|
|
/*------------------------------ HSI48 Configuration -----------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
|
|
800bb40: 687b ldr r3, [r7, #4]
|
|
800bb42: 681b ldr r3, [r3, #0]
|
|
800bb44: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800bb48: 2b00 cmp r3, #0
|
|
800bb4a: d02c beq.n 800bba6 <HAL_RCC_OscConfig+0x506>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
|
|
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
|
|
800bb4c: 687b ldr r3, [r7, #4]
|
|
800bb4e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800bb50: 2b00 cmp r3, #0
|
|
800bb52: d014 beq.n 800bb7e <HAL_RCC_OscConfig+0x4de>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_ENABLE();
|
|
800bb54: f7ff faa9 bl 800b0aa <LL_RCC_HSI48_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bb58: f7fa ff08 bl 800696c <HAL_GetTick>
|
|
800bb5c: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till HSI48 is ready */
|
|
while (LL_RCC_HSI48_IsReady() == 0U)
|
|
800bb5e: e008 b.n 800bb72 <HAL_RCC_OscConfig+0x4d2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
800bb60: f7fa ff04 bl 800696c <HAL_GetTick>
|
|
800bb64: 4602 mov r2, r0
|
|
800bb66: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800bb68: 1ad3 subs r3, r2, r3
|
|
800bb6a: 2b02 cmp r3, #2
|
|
800bb6c: d901 bls.n 800bb72 <HAL_RCC_OscConfig+0x4d2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bb6e: 2303 movs r3, #3
|
|
800bb70: e103 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_HSI48_IsReady() == 0U)
|
|
800bb72: f7ff fabc bl 800b0ee <LL_RCC_HSI48_IsReady>
|
|
800bb76: 4603 mov r3, r0
|
|
800bb78: 2b00 cmp r3, #0
|
|
800bb7a: d0f1 beq.n 800bb60 <HAL_RCC_OscConfig+0x4c0>
|
|
800bb7c: e013 b.n 800bba6 <HAL_RCC_OscConfig+0x506>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_DISABLE();
|
|
800bb7e: f7ff faa5 bl 800b0cc <LL_RCC_HSI48_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bb82: f7fa fef3 bl 800696c <HAL_GetTick>
|
|
800bb86: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till HSI48 is disabled */
|
|
while (LL_RCC_HSI48_IsReady() != 0U)
|
|
800bb88: e008 b.n 800bb9c <HAL_RCC_OscConfig+0x4fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
800bb8a: f7fa feef bl 800696c <HAL_GetTick>
|
|
800bb8e: 4602 mov r2, r0
|
|
800bb90: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800bb92: 1ad3 subs r3, r2, r3
|
|
800bb94: 2b02 cmp r3, #2
|
|
800bb96: d901 bls.n 800bb9c <HAL_RCC_OscConfig+0x4fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bb98: 2303 movs r3, #3
|
|
800bb9a: e0ee b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (LL_RCC_HSI48_IsReady() != 0U)
|
|
800bb9c: f7ff faa7 bl 800b0ee <LL_RCC_HSI48_IsReady>
|
|
800bba0: 4603 mov r3, r0
|
|
800bba2: 2b00 cmp r3, #0
|
|
800bba4: d1f1 bne.n 800bb8a <HAL_RCC_OscConfig+0x4ea>
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
800bba6: 687b ldr r3, [r7, #4]
|
|
800bba8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800bbaa: 2b00 cmp r3, #0
|
|
800bbac: f000 80e4 beq.w 800bd78 <HAL_RCC_OscConfig+0x6d8>
|
|
{
|
|
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
800bbb0: f7ff fc05 bl 800b3be <LL_RCC_GetSysClkSource>
|
|
800bbb4: 6138 str r0, [r7, #16]
|
|
const uint32_t temp_pllconfig = RCC->PLLCFGR;
|
|
800bbb6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bbba: 68db ldr r3, [r3, #12]
|
|
800bbbc: 60fb str r3, [r7, #12]
|
|
|
|
/* PLL On ? */
|
|
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
800bbbe: 687b ldr r3, [r7, #4]
|
|
800bbc0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800bbc2: 2b02 cmp r3, #2
|
|
800bbc4: f040 80b4 bne.w 800bd30 <HAL_RCC_OscConfig+0x690>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Do nothing if PLL configuration is unchanged */
|
|
if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800bbc8: 68fb ldr r3, [r7, #12]
|
|
800bbca: f003 0203 and.w r2, r3, #3
|
|
800bbce: 687b ldr r3, [r7, #4]
|
|
800bbd0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800bbd2: 429a cmp r2, r3
|
|
800bbd4: d123 bne.n 800bc1e <HAL_RCC_OscConfig+0x57e>
|
|
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
|
800bbd6: 68fb ldr r3, [r7, #12]
|
|
800bbd8: f003 0270 and.w r2, r3, #112 @ 0x70
|
|
800bbdc: 687b ldr r3, [r7, #4]
|
|
800bbde: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800bbe0: 429a cmp r2, r3
|
|
800bbe2: d11c bne.n 800bc1e <HAL_RCC_OscConfig+0x57e>
|
|
((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
|
|
800bbe4: 68fb ldr r3, [r7, #12]
|
|
800bbe6: 0a1b lsrs r3, r3, #8
|
|
800bbe8: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
800bbec: 687b ldr r3, [r7, #4]
|
|
800bbee: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
|
800bbf0: 429a cmp r2, r3
|
|
800bbf2: d114 bne.n 800bc1e <HAL_RCC_OscConfig+0x57e>
|
|
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
|
|
800bbf4: 68fb ldr r3, [r7, #12]
|
|
800bbf6: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000
|
|
800bbfa: 687b ldr r3, [r7, #4]
|
|
800bbfc: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
|
|
800bbfe: 429a cmp r2, r3
|
|
800bc00: d10d bne.n 800bc1e <HAL_RCC_OscConfig+0x57e>
|
|
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
|
|
800bc02: 68fb ldr r3, [r7, #12]
|
|
800bc04: f003 6260 and.w r2, r3, #234881024 @ 0xe000000
|
|
800bc08: 687b ldr r3, [r7, #4]
|
|
800bc0a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
|
|
800bc0c: 429a cmp r2, r3
|
|
800bc0e: d106 bne.n 800bc1e <HAL_RCC_OscConfig+0x57e>
|
|
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
|
|
800bc10: 68fb ldr r3, [r7, #12]
|
|
800bc12: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000
|
|
800bc16: 687b ldr r3, [r7, #4]
|
|
800bc18: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
|
|
800bc1a: 429a cmp r2, r3
|
|
800bc1c: d05d beq.n 800bcda <HAL_RCC_OscConfig+0x63a>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
800bc1e: 693b ldr r3, [r7, #16]
|
|
800bc20: 2b0c cmp r3, #12
|
|
800bc22: d058 beq.n 800bcd6 <HAL_RCC_OscConfig+0x636>
|
|
{
|
|
#if defined(SAI1)
|
|
/* Check if main PLL can be updated */
|
|
/* Not possible if the source is shared by other enabled PLLSAIx */
|
|
if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
|
|
800bc24: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bc28: 681b ldr r3, [r3, #0]
|
|
800bc2a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
800bc2e: 2b00 cmp r3, #0
|
|
800bc30: d001 beq.n 800bc36 <HAL_RCC_OscConfig+0x596>
|
|
|
|
{
|
|
return HAL_ERROR;
|
|
800bc32: 2301 movs r3, #1
|
|
800bc34: e0a1 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
}
|
|
else
|
|
#endif /* SAI1 */
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800bc36: f7ff fc85 bl 800b544 <LL_RCC_PLL_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bc3a: f7fa fe97 bl 800696c <HAL_GetTick>
|
|
800bc3e: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800bc40: e008 b.n 800bc54 <HAL_RCC_OscConfig+0x5b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800bc42: f7fa fe93 bl 800696c <HAL_GetTick>
|
|
800bc46: 4602 mov r2, r0
|
|
800bc48: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800bc4a: 1ad3 subs r3, r2, r3
|
|
800bc4c: 2b02 cmp r3, #2
|
|
800bc4e: d901 bls.n 800bc54 <HAL_RCC_OscConfig+0x5b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bc50: 2303 movs r3, #3
|
|
800bc52: e092 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800bc54: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bc58: 681b ldr r3, [r3, #0]
|
|
800bc5a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800bc5e: 2b00 cmp r3, #0
|
|
800bc60: d1ef bne.n 800bc42 <HAL_RCC_OscConfig+0x5a2>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
800bc62: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bc66: 68da ldr r2, [r3, #12]
|
|
800bc68: 4b30 ldr r3, [pc, #192] @ (800bd2c <HAL_RCC_OscConfig+0x68c>)
|
|
800bc6a: 4013 ands r3, r2
|
|
800bc6c: 687a ldr r2, [r7, #4]
|
|
800bc6e: 6b11 ldr r1, [r2, #48] @ 0x30
|
|
800bc70: 687a ldr r2, [r7, #4]
|
|
800bc72: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
800bc74: 4311 orrs r1, r2
|
|
800bc76: 687a ldr r2, [r7, #4]
|
|
800bc78: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
800bc7a: 0212 lsls r2, r2, #8
|
|
800bc7c: 4311 orrs r1, r2
|
|
800bc7e: 687a ldr r2, [r7, #4]
|
|
800bc80: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
800bc82: 4311 orrs r1, r2
|
|
800bc84: 687a ldr r2, [r7, #4]
|
|
800bc86: 6c12 ldr r2, [r2, #64] @ 0x40
|
|
800bc88: 4311 orrs r1, r2
|
|
800bc8a: 687a ldr r2, [r7, #4]
|
|
800bc8c: 6c52 ldr r2, [r2, #68] @ 0x44
|
|
800bc8e: 430a orrs r2, r1
|
|
800bc90: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800bc94: 4313 orrs r3, r2
|
|
800bc96: 60cb str r3, [r1, #12]
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
800bc98: f7ff fc45 bl 800b526 <LL_RCC_PLL_Enable>
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
800bc9c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bca0: 68db ldr r3, [r3, #12]
|
|
800bca2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800bca6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800bcaa: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bcac: f7fa fe5e bl 800696c <HAL_GetTick>
|
|
800bcb0: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800bcb2: e008 b.n 800bcc6 <HAL_RCC_OscConfig+0x626>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800bcb4: f7fa fe5a bl 800696c <HAL_GetTick>
|
|
800bcb8: 4602 mov r2, r0
|
|
800bcba: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800bcbc: 1ad3 subs r3, r2, r3
|
|
800bcbe: 2b02 cmp r3, #2
|
|
800bcc0: d901 bls.n 800bcc6 <HAL_RCC_OscConfig+0x626>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bcc2: 2303 movs r3, #3
|
|
800bcc4: e059 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800bcc6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bcca: 681b ldr r3, [r3, #0]
|
|
800bccc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800bcd0: 2b00 cmp r3, #0
|
|
800bcd2: d0ef beq.n 800bcb4 <HAL_RCC_OscConfig+0x614>
|
|
if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
800bcd4: e050 b.n 800bd78 <HAL_RCC_OscConfig+0x6d8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
800bcd6: 2301 movs r3, #1
|
|
800bcd8: e04f b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
}
|
|
else
|
|
{
|
|
/* PLL configuration is unchanged */
|
|
/* Re-enable PLL if it was disabled (ie. low power mode) */
|
|
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800bcda: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bcde: 681b ldr r3, [r3, #0]
|
|
800bce0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800bce4: 2b00 cmp r3, #0
|
|
800bce6: d147 bne.n 800bd78 <HAL_RCC_OscConfig+0x6d8>
|
|
{
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
800bce8: f7ff fc1d bl 800b526 <LL_RCC_PLL_Enable>
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
800bcec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bcf0: 68db ldr r3, [r3, #12]
|
|
800bcf2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800bcf6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800bcfa: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bcfc: f7fa fe36 bl 800696c <HAL_GetTick>
|
|
800bd00: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800bd02: e008 b.n 800bd16 <HAL_RCC_OscConfig+0x676>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800bd04: f7fa fe32 bl 800696c <HAL_GetTick>
|
|
800bd08: 4602 mov r2, r0
|
|
800bd0a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800bd0c: 1ad3 subs r3, r2, r3
|
|
800bd0e: 2b02 cmp r3, #2
|
|
800bd10: d901 bls.n 800bd16 <HAL_RCC_OscConfig+0x676>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bd12: 2303 movs r3, #3
|
|
800bd14: e031 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800bd16: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bd1a: 681b ldr r3, [r3, #0]
|
|
800bd1c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800bd20: 2b00 cmp r3, #0
|
|
800bd22: d0ef beq.n 800bd04 <HAL_RCC_OscConfig+0x664>
|
|
800bd24: e028 b.n 800bd78 <HAL_RCC_OscConfig+0x6d8>
|
|
800bd26: bf00 nop
|
|
800bd28: 58000400 .word 0x58000400
|
|
800bd2c: 11c1808c .word 0x11c1808c
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check that PLL is not used as system clock or not */
|
|
if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
800bd30: 693b ldr r3, [r7, #16]
|
|
800bd32: 2b0c cmp r3, #12
|
|
800bd34: d01e beq.n 800bd74 <HAL_RCC_OscConfig+0x6d4>
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800bd36: f7ff fc05 bl 800b544 <LL_RCC_PLL_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bd3a: f7fa fe17 bl 800696c <HAL_GetTick>
|
|
800bd3e: 6278 str r0, [r7, #36] @ 0x24
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800bd40: e008 b.n 800bd54 <HAL_RCC_OscConfig+0x6b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800bd42: f7fa fe13 bl 800696c <HAL_GetTick>
|
|
800bd46: 4602 mov r2, r0
|
|
800bd48: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800bd4a: 1ad3 subs r3, r2, r3
|
|
800bd4c: 2b02 cmp r3, #2
|
|
800bd4e: d901 bls.n 800bd54 <HAL_RCC_OscConfig+0x6b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bd50: 2303 movs r3, #3
|
|
800bd52: e012 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800bd54: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bd58: 681b ldr r3, [r3, #0]
|
|
800bd5a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800bd5e: 2b00 cmp r3, #0
|
|
800bd60: d1ef bne.n 800bd42 <HAL_RCC_OscConfig+0x6a2>
|
|
}
|
|
}
|
|
|
|
/* Disable the PLL source and outputs to save power when PLL is off */
|
|
#if defined(SAI1) && defined(USB)
|
|
CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN));
|
|
800bd62: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800bd66: 68da ldr r2, [r3, #12]
|
|
800bd68: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800bd6c: 4b05 ldr r3, [pc, #20] @ (800bd84 <HAL_RCC_OscConfig+0x6e4>)
|
|
800bd6e: 4013 ands r3, r2
|
|
800bd70: 60cb str r3, [r1, #12]
|
|
800bd72: e001 b.n 800bd78 <HAL_RCC_OscConfig+0x6d8>
|
|
#endif /* SAI1 && USB */
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
800bd74: 2301 movs r3, #1
|
|
800bd76: e000 b.n 800bd7a <HAL_RCC_OscConfig+0x6da>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800bd78: 2300 movs r3, #0
|
|
}
|
|
800bd7a: 4618 mov r0, r3
|
|
800bd7c: 3734 adds r7, #52 @ 0x34
|
|
800bd7e: 46bd mov sp, r7
|
|
800bd80: bd90 pop {r4, r7, pc}
|
|
800bd82: bf00 nop
|
|
800bd84: eefefffc .word 0xeefefffc
|
|
|
|
0800bd88 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
800bd88: b580 push {r7, lr}
|
|
800bd8a: b084 sub sp, #16
|
|
800bd8c: af00 add r7, sp, #0
|
|
800bd8e: 6078 str r0, [r7, #4]
|
|
800bd90: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
800bd92: 687b ldr r3, [r7, #4]
|
|
800bd94: 2b00 cmp r3, #0
|
|
800bd96: d101 bne.n 800bd9c <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
800bd98: 2301 movs r3, #1
|
|
800bd9a: e12d b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the FLASH clock
|
|
(HCLK4) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
800bd9c: 4b98 ldr r3, [pc, #608] @ (800c000 <HAL_RCC_ClockConfig+0x278>)
|
|
800bd9e: 681b ldr r3, [r3, #0]
|
|
800bda0: f003 0307 and.w r3, r3, #7
|
|
800bda4: 683a ldr r2, [r7, #0]
|
|
800bda6: 429a cmp r2, r3
|
|
800bda8: d91b bls.n 800bde2 <HAL_RCC_ClockConfig+0x5a>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800bdaa: 4b95 ldr r3, [pc, #596] @ (800c000 <HAL_RCC_ClockConfig+0x278>)
|
|
800bdac: 681b ldr r3, [r3, #0]
|
|
800bdae: f023 0207 bic.w r2, r3, #7
|
|
800bdb2: 4993 ldr r1, [pc, #588] @ (800c000 <HAL_RCC_ClockConfig+0x278>)
|
|
800bdb4: 683b ldr r3, [r7, #0]
|
|
800bdb6: 4313 orrs r3, r2
|
|
800bdb8: 600b str r3, [r1, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bdba: f7fa fdd7 bl 800696c <HAL_GetTick>
|
|
800bdbe: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800bdc0: e008 b.n 800bdd4 <HAL_RCC_ClockConfig+0x4c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
800bdc2: f7fa fdd3 bl 800696c <HAL_GetTick>
|
|
800bdc6: 4602 mov r2, r0
|
|
800bdc8: 68fb ldr r3, [r7, #12]
|
|
800bdca: 1ad3 subs r3, r2, r3
|
|
800bdcc: 2b02 cmp r3, #2
|
|
800bdce: d901 bls.n 800bdd4 <HAL_RCC_ClockConfig+0x4c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bdd0: 2303 movs r3, #3
|
|
800bdd2: e111 b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800bdd4: 4b8a ldr r3, [pc, #552] @ (800c000 <HAL_RCC_ClockConfig+0x278>)
|
|
800bdd6: 681b ldr r3, [r3, #0]
|
|
800bdd8: f003 0307 and.w r3, r3, #7
|
|
800bddc: 683a ldr r2, [r7, #0]
|
|
800bdde: 429a cmp r2, r3
|
|
800bde0: d1ef bne.n 800bdc2 <HAL_RCC_ClockConfig+0x3a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK1 Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
800bde2: 687b ldr r3, [r7, #4]
|
|
800bde4: 681b ldr r3, [r3, #0]
|
|
800bde6: f003 0302 and.w r3, r3, #2
|
|
800bdea: 2b00 cmp r3, #0
|
|
800bdec: d016 beq.n 800be1c <HAL_RCC_ClockConfig+0x94>
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider));
|
|
LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider);
|
|
800bdee: 687b ldr r3, [r7, #4]
|
|
800bdf0: 689b ldr r3, [r3, #8]
|
|
800bdf2: 4618 mov r0, r3
|
|
800bdf4: f7ff faef bl 800b3d6 <LL_RCC_SetAHBPrescaler>
|
|
|
|
/* HCLK1 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
800bdf8: f7fa fdb8 bl 800696c <HAL_GetTick>
|
|
800bdfc: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_HPRE() == 0U)
|
|
800bdfe: e008 b.n 800be12 <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
800be00: f7fa fdb4 bl 800696c <HAL_GetTick>
|
|
800be04: 4602 mov r2, r0
|
|
800be06: 68fb ldr r3, [r7, #12]
|
|
800be08: 1ad3 subs r3, r2, r3
|
|
800be0a: 2b02 cmp r3, #2
|
|
800be0c: d901 bls.n 800be12 <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800be0e: 2303 movs r3, #3
|
|
800be10: e0f2 b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
while (LL_RCC_IsActiveFlag_HPRE() == 0U)
|
|
800be12: f7ff fbe9 bl 800b5e8 <LL_RCC_IsActiveFlag_HPRE>
|
|
800be16: 4603 mov r3, r0
|
|
800be18: 2b00 cmp r3, #0
|
|
800be1a: d0f1 beq.n 800be00 <HAL_RCC_ClockConfig+0x78>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK2 Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2)
|
|
800be1c: 687b ldr r3, [r7, #4]
|
|
800be1e: 681b ldr r3, [r3, #0]
|
|
800be20: f003 0320 and.w r3, r3, #32
|
|
800be24: 2b00 cmp r3, #0
|
|
800be26: d016 beq.n 800be56 <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider));
|
|
LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider);
|
|
800be28: 687b ldr r3, [r7, #4]
|
|
800be2a: 695b ldr r3, [r3, #20]
|
|
800be2c: 4618 mov r0, r3
|
|
800be2e: f7ff fae6 bl 800b3fe <LL_C2_RCC_SetAHBPrescaler>
|
|
|
|
/* HCLK2 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
800be32: f7fa fd9b bl 800696c <HAL_GetTick>
|
|
800be36: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_C2HPRE() == 0U)
|
|
800be38: e008 b.n 800be4c <HAL_RCC_ClockConfig+0xc4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
800be3a: f7fa fd97 bl 800696c <HAL_GetTick>
|
|
800be3e: 4602 mov r2, r0
|
|
800be40: 68fb ldr r3, [r7, #12]
|
|
800be42: 1ad3 subs r3, r2, r3
|
|
800be44: 2b02 cmp r3, #2
|
|
800be46: d901 bls.n 800be4c <HAL_RCC_ClockConfig+0xc4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800be48: 2303 movs r3, #3
|
|
800be4a: e0d5 b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
while (LL_RCC_IsActiveFlag_C2HPRE() == 0U)
|
|
800be4c: f7ff fbde bl 800b60c <LL_RCC_IsActiveFlag_C2HPRE>
|
|
800be50: 4603 mov r3, r0
|
|
800be52: 2b00 cmp r3, #0
|
|
800be54: d0f1 beq.n 800be3a <HAL_RCC_ClockConfig+0xb2>
|
|
}
|
|
}
|
|
}
|
|
/*-------------------------- HCLK4 Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK4) == RCC_CLOCKTYPE_HCLK4)
|
|
800be56: 687b ldr r3, [r7, #4]
|
|
800be58: 681b ldr r3, [r3, #0]
|
|
800be5a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800be5e: 2b00 cmp r3, #0
|
|
800be60: d016 beq.n 800be90 <HAL_RCC_ClockConfig+0x108>
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK4Divider));
|
|
LL_RCC_SetAHB4Prescaler(RCC_ClkInitStruct->AHBCLK4Divider);
|
|
800be62: 687b ldr r3, [r7, #4]
|
|
800be64: 699b ldr r3, [r3, #24]
|
|
800be66: 4618 mov r0, r3
|
|
800be68: f7ff fadf bl 800b42a <LL_RCC_SetAHB4Prescaler>
|
|
|
|
/* AHB shared prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
800be6c: f7fa fd7e bl 800696c <HAL_GetTick>
|
|
800be70: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U)
|
|
800be72: e008 b.n 800be86 <HAL_RCC_ClockConfig+0xfe>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
800be74: f7fa fd7a bl 800696c <HAL_GetTick>
|
|
800be78: 4602 mov r2, r0
|
|
800be7a: 68fb ldr r3, [r7, #12]
|
|
800be7c: 1ad3 subs r3, r2, r3
|
|
800be7e: 2b02 cmp r3, #2
|
|
800be80: d901 bls.n 800be86 <HAL_RCC_ClockConfig+0xfe>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800be82: 2303 movs r3, #3
|
|
800be84: e0b8 b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U)
|
|
800be86: f7ff fbd4 bl 800b632 <LL_RCC_IsActiveFlag_SHDHPRE>
|
|
800be8a: 4603 mov r3, r0
|
|
800be8c: 2b00 cmp r3, #0
|
|
800be8e: d0f1 beq.n 800be74 <HAL_RCC_ClockConfig+0xec>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
800be90: 687b ldr r3, [r7, #4]
|
|
800be92: 681b ldr r3, [r3, #0]
|
|
800be94: f003 0304 and.w r3, r3, #4
|
|
800be98: 2b00 cmp r3, #0
|
|
800be9a: d016 beq.n 800beca <HAL_RCC_ClockConfig+0x142>
|
|
{
|
|
assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider));
|
|
LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider);
|
|
800be9c: 687b ldr r3, [r7, #4]
|
|
800be9e: 68db ldr r3, [r3, #12]
|
|
800bea0: 4618 mov r0, r3
|
|
800bea2: f7ff fad9 bl 800b458 <LL_RCC_SetAPB1Prescaler>
|
|
|
|
/* APB1 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
800bea6: f7fa fd61 bl 800696c <HAL_GetTick>
|
|
800beaa: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_PPRE1() == 0U)
|
|
800beac: e008 b.n 800bec0 <HAL_RCC_ClockConfig+0x138>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
800beae: f7fa fd5d bl 800696c <HAL_GetTick>
|
|
800beb2: 4602 mov r2, r0
|
|
800beb4: 68fb ldr r3, [r7, #12]
|
|
800beb6: 1ad3 subs r3, r2, r3
|
|
800beb8: 2b02 cmp r3, #2
|
|
800beba: d901 bls.n 800bec0 <HAL_RCC_ClockConfig+0x138>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bebc: 2303 movs r3, #3
|
|
800bebe: e09b b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
while (LL_RCC_IsActiveFlag_PPRE1() == 0U)
|
|
800bec0: f7ff fbca bl 800b658 <LL_RCC_IsActiveFlag_PPRE1>
|
|
800bec4: 4603 mov r3, r0
|
|
800bec6: 2b00 cmp r3, #0
|
|
800bec8: d0f1 beq.n 800beae <HAL_RCC_ClockConfig+0x126>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800beca: 687b ldr r3, [r7, #4]
|
|
800becc: 681b ldr r3, [r3, #0]
|
|
800bece: f003 0308 and.w r3, r3, #8
|
|
800bed2: 2b00 cmp r3, #0
|
|
800bed4: d017 beq.n 800bf06 <HAL_RCC_ClockConfig+0x17e>
|
|
{
|
|
assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider));
|
|
LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U);
|
|
800bed6: 687b ldr r3, [r7, #4]
|
|
800bed8: 691b ldr r3, [r3, #16]
|
|
800beda: 00db lsls r3, r3, #3
|
|
800bedc: 4618 mov r0, r3
|
|
800bede: f7ff facf bl 800b480 <LL_RCC_SetAPB2Prescaler>
|
|
|
|
/* APB2 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
800bee2: f7fa fd43 bl 800696c <HAL_GetTick>
|
|
800bee6: 60f8 str r0, [r7, #12]
|
|
while (LL_RCC_IsActiveFlag_PPRE2() == 0U)
|
|
800bee8: e008 b.n 800befc <HAL_RCC_ClockConfig+0x174>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
800beea: f7fa fd3f bl 800696c <HAL_GetTick>
|
|
800beee: 4602 mov r2, r0
|
|
800bef0: 68fb ldr r3, [r7, #12]
|
|
800bef2: 1ad3 subs r3, r2, r3
|
|
800bef4: 2b02 cmp r3, #2
|
|
800bef6: d901 bls.n 800befc <HAL_RCC_ClockConfig+0x174>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bef8: 2303 movs r3, #3
|
|
800befa: e07d b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
while (LL_RCC_IsActiveFlag_PPRE2() == 0U)
|
|
800befc: f7ff fbbe bl 800b67c <LL_RCC_IsActiveFlag_PPRE2>
|
|
800bf00: 4603 mov r3, r0
|
|
800bf02: 2b00 cmp r3, #0
|
|
800bf04: d0f1 beq.n 800beea <HAL_RCC_ClockConfig+0x162>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
800bf06: 687b ldr r3, [r7, #4]
|
|
800bf08: 681b ldr r3, [r3, #0]
|
|
800bf0a: f003 0301 and.w r3, r3, #1
|
|
800bf0e: 2b00 cmp r3, #0
|
|
800bf10: d043 beq.n 800bf9a <HAL_RCC_ClockConfig+0x212>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
800bf12: 687b ldr r3, [r7, #4]
|
|
800bf14: 685b ldr r3, [r3, #4]
|
|
800bf16: 2b02 cmp r3, #2
|
|
800bf18: d106 bne.n 800bf28 <HAL_RCC_ClockConfig+0x1a0>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (LL_RCC_HSE_IsReady() == 0U)
|
|
800bf1a: f7ff f86f bl 800affc <LL_RCC_HSE_IsReady>
|
|
800bf1e: 4603 mov r3, r0
|
|
800bf20: 2b00 cmp r3, #0
|
|
800bf22: d11e bne.n 800bf62 <HAL_RCC_ClockConfig+0x1da>
|
|
{
|
|
return HAL_ERROR;
|
|
800bf24: 2301 movs r3, #1
|
|
800bf26: e067 b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
800bf28: 687b ldr r3, [r7, #4]
|
|
800bf2a: 685b ldr r3, [r3, #4]
|
|
800bf2c: 2b03 cmp r3, #3
|
|
800bf2e: d106 bne.n 800bf3e <HAL_RCC_ClockConfig+0x1b6>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (LL_RCC_PLL_IsReady() == 0U)
|
|
800bf30: f7ff fb17 bl 800b562 <LL_RCC_PLL_IsReady>
|
|
800bf34: 4603 mov r3, r0
|
|
800bf36: 2b00 cmp r3, #0
|
|
800bf38: d113 bne.n 800bf62 <HAL_RCC_ClockConfig+0x1da>
|
|
{
|
|
return HAL_ERROR;
|
|
800bf3a: 2301 movs r3, #1
|
|
800bf3c: e05c b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
800bf3e: 687b ldr r3, [r7, #4]
|
|
800bf40: 685b ldr r3, [r3, #4]
|
|
800bf42: 2b00 cmp r3, #0
|
|
800bf44: d106 bne.n 800bf54 <HAL_RCC_ClockConfig+0x1cc>
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if (LL_RCC_MSI_IsReady() == 0U)
|
|
800bf46: f7ff f9d7 bl 800b2f8 <LL_RCC_MSI_IsReady>
|
|
800bf4a: 4603 mov r3, r0
|
|
800bf4c: 2b00 cmp r3, #0
|
|
800bf4e: d108 bne.n 800bf62 <HAL_RCC_ClockConfig+0x1da>
|
|
{
|
|
return HAL_ERROR;
|
|
800bf50: 2301 movs r3, #1
|
|
800bf52: e051 b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (LL_RCC_HSI_IsReady() == 0U)
|
|
800bf54: f7ff f882 bl 800b05c <LL_RCC_HSI_IsReady>
|
|
800bf58: 4603 mov r3, r0
|
|
800bf5a: 2b00 cmp r3, #0
|
|
800bf5c: d101 bne.n 800bf62 <HAL_RCC_ClockConfig+0x1da>
|
|
{
|
|
return HAL_ERROR;
|
|
800bf5e: 2301 movs r3, #1
|
|
800bf60: e04a b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
}
|
|
|
|
}
|
|
|
|
/* apply system clock switch */
|
|
LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource);
|
|
800bf62: 687b ldr r3, [r7, #4]
|
|
800bf64: 685b ldr r3, [r3, #4]
|
|
800bf66: 4618 mov r0, r3
|
|
800bf68: f7ff fa15 bl 800b396 <LL_RCC_SetSysClkSource>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bf6c: f7fa fcfe bl 800696c <HAL_GetTick>
|
|
800bf70: 60f8 str r0, [r7, #12]
|
|
|
|
/* check system clock source switch status */
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800bf72: e00a b.n 800bf8a <HAL_RCC_ClockConfig+0x202>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
800bf74: f7fa fcfa bl 800696c <HAL_GetTick>
|
|
800bf78: 4602 mov r2, r0
|
|
800bf7a: 68fb ldr r3, [r7, #12]
|
|
800bf7c: 1ad3 subs r3, r2, r3
|
|
800bf7e: f241 3288 movw r2, #5000 @ 0x1388
|
|
800bf82: 4293 cmp r3, r2
|
|
800bf84: d901 bls.n 800bf8a <HAL_RCC_ClockConfig+0x202>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bf86: 2303 movs r3, #3
|
|
800bf88: e036 b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800bf8a: f7ff fa18 bl 800b3be <LL_RCC_GetSysClkSource>
|
|
800bf8e: 4602 mov r2, r0
|
|
800bf90: 687b ldr r3, [r7, #4]
|
|
800bf92: 685b ldr r3, [r3, #4]
|
|
800bf94: 009b lsls r3, r3, #2
|
|
800bf96: 429a cmp r2, r3
|
|
800bf98: d1ec bne.n 800bf74 <HAL_RCC_ClockConfig+0x1ec>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
800bf9a: 4b19 ldr r3, [pc, #100] @ (800c000 <HAL_RCC_ClockConfig+0x278>)
|
|
800bf9c: 681b ldr r3, [r3, #0]
|
|
800bf9e: f003 0307 and.w r3, r3, #7
|
|
800bfa2: 683a ldr r2, [r7, #0]
|
|
800bfa4: 429a cmp r2, r3
|
|
800bfa6: d21b bcs.n 800bfe0 <HAL_RCC_ClockConfig+0x258>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800bfa8: 4b15 ldr r3, [pc, #84] @ (800c000 <HAL_RCC_ClockConfig+0x278>)
|
|
800bfaa: 681b ldr r3, [r3, #0]
|
|
800bfac: f023 0207 bic.w r2, r3, #7
|
|
800bfb0: 4913 ldr r1, [pc, #76] @ (800c000 <HAL_RCC_ClockConfig+0x278>)
|
|
800bfb2: 683b ldr r3, [r7, #0]
|
|
800bfb4: 4313 orrs r3, r2
|
|
800bfb6: 600b str r3, [r1, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800bfb8: f7fa fcd8 bl 800696c <HAL_GetTick>
|
|
800bfbc: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800bfbe: e008 b.n 800bfd2 <HAL_RCC_ClockConfig+0x24a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
800bfc0: f7fa fcd4 bl 800696c <HAL_GetTick>
|
|
800bfc4: 4602 mov r2, r0
|
|
800bfc6: 68fb ldr r3, [r7, #12]
|
|
800bfc8: 1ad3 subs r3, r2, r3
|
|
800bfca: 2b02 cmp r3, #2
|
|
800bfcc: d901 bls.n 800bfd2 <HAL_RCC_ClockConfig+0x24a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800bfce: 2303 movs r3, #3
|
|
800bfd0: e012 b.n 800bff8 <HAL_RCC_ClockConfig+0x270>
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800bfd2: 4b0b ldr r3, [pc, #44] @ (800c000 <HAL_RCC_ClockConfig+0x278>)
|
|
800bfd4: 681b ldr r3, [r3, #0]
|
|
800bfd6: f003 0307 and.w r3, r3, #7
|
|
800bfda: 683a ldr r2, [r7, #0]
|
|
800bfdc: 429a cmp r2, r3
|
|
800bfde: d1ef bne.n 800bfc0 <HAL_RCC_ClockConfig+0x238>
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetHCLKFreq();
|
|
800bfe0: f000 f87e bl 800c0e0 <HAL_RCC_GetHCLKFreq>
|
|
800bfe4: 4603 mov r3, r0
|
|
800bfe6: 4a07 ldr r2, [pc, #28] @ (800c004 <HAL_RCC_ClockConfig+0x27c>)
|
|
800bfe8: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
return HAL_InitTick(HAL_GetTickPrio());
|
|
800bfea: f7fa fccb bl 8006984 <HAL_GetTickPrio>
|
|
800bfee: 4603 mov r3, r0
|
|
800bff0: 4618 mov r0, r3
|
|
800bff2: f7fa fa53 bl 800649c <HAL_InitTick>
|
|
800bff6: 4603 mov r3, r0
|
|
}
|
|
800bff8: 4618 mov r0, r3
|
|
800bffa: 3710 adds r7, #16
|
|
800bffc: 46bd mov sp, r7
|
|
800bffe: bd80 pop {r7, pc}
|
|
800c000: 58004000 .word 0x58004000
|
|
800c004: 2000000c .word 0x2000000c
|
|
|
|
0800c008 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
800c008: b590 push {r4, r7, lr}
|
|
800c00a: b085 sub sp, #20
|
|
800c00c: af00 add r7, sp, #0
|
|
uint32_t pllsource;
|
|
uint32_t sysclockfreq;
|
|
uint32_t pllinputfreq;
|
|
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
800c00e: f7ff f9d6 bl 800b3be <LL_RCC_GetSysClkSource>
|
|
800c012: 6078 str r0, [r7, #4]
|
|
|
|
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI)
|
|
800c014: 687b ldr r3, [r7, #4]
|
|
800c016: 2b00 cmp r3, #0
|
|
800c018: d10a bne.n 800c030 <HAL_RCC_GetSysClockFreq+0x28>
|
|
{
|
|
/* Retrieve MSI frequency range in HZ*/
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
|
|
800c01a: f7ff f992 bl 800b342 <LL_RCC_MSI_GetRange>
|
|
800c01e: 4603 mov r3, r0
|
|
800c020: 091b lsrs r3, r3, #4
|
|
800c022: f003 030f and.w r3, r3, #15
|
|
800c026: 4a2b ldr r2, [pc, #172] @ (800c0d4 <HAL_RCC_GetSysClockFreq+0xcc>)
|
|
800c028: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800c02c: 60fb str r3, [r7, #12]
|
|
800c02e: e04b b.n 800c0c8 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
}
|
|
else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
800c030: 687b ldr r3, [r7, #4]
|
|
800c032: 2b04 cmp r3, #4
|
|
800c034: d102 bne.n 800c03c <HAL_RCC_GetSysClockFreq+0x34>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
800c036: 4b28 ldr r3, [pc, #160] @ (800c0d8 <HAL_RCC_GetSysClockFreq+0xd0>)
|
|
800c038: 60fb str r3, [r7, #12]
|
|
800c03a: e045 b.n 800c0c8 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
}
|
|
else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
800c03c: 687b ldr r3, [r7, #4]
|
|
800c03e: 2b08 cmp r3, #8
|
|
800c040: d10a bne.n 800c058 <HAL_RCC_GetSysClockFreq+0x50>
|
|
{
|
|
/* HSE used as system clock source */
|
|
if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
|
|
800c042: f7fe ffab bl 800af9c <LL_RCC_HSE_IsEnabledDiv2>
|
|
800c046: 4603 mov r3, r0
|
|
800c048: 2b01 cmp r3, #1
|
|
800c04a: d102 bne.n 800c052 <HAL_RCC_GetSysClockFreq+0x4a>
|
|
{
|
|
sysclockfreq = HSE_VALUE / 2U;
|
|
800c04c: 4b22 ldr r3, [pc, #136] @ (800c0d8 <HAL_RCC_GetSysClockFreq+0xd0>)
|
|
800c04e: 60fb str r3, [r7, #12]
|
|
800c050: e03a b.n 800c0c8 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
}
|
|
else
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
800c052: 4b22 ldr r3, [pc, #136] @ (800c0dc <HAL_RCC_GetSysClockFreq+0xd4>)
|
|
800c054: 60fb str r3, [r7, #12]
|
|
800c056: e037 b.n 800c0c8 <HAL_RCC_GetSysClockFreq+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLL used as system clock source */
|
|
pllsource = LL_RCC_PLL_GetMainSource();
|
|
800c058: f7ff faba bl 800b5d0 <LL_RCC_PLL_GetMainSource>
|
|
800c05c: 6038 str r0, [r7, #0]
|
|
switch (pllsource)
|
|
800c05e: 683b ldr r3, [r7, #0]
|
|
800c060: 2b02 cmp r3, #2
|
|
800c062: d003 beq.n 800c06c <HAL_RCC_GetSysClockFreq+0x64>
|
|
800c064: 683b ldr r3, [r7, #0]
|
|
800c066: 2b03 cmp r3, #3
|
|
800c068: d003 beq.n 800c072 <HAL_RCC_GetSysClockFreq+0x6a>
|
|
800c06a: e00d b.n 800c088 <HAL_RCC_GetSysClockFreq+0x80>
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllinputfreq = HSI_VALUE;
|
|
800c06c: 4b1a ldr r3, [pc, #104] @ (800c0d8 <HAL_RCC_GetSysClockFreq+0xd0>)
|
|
800c06e: 60bb str r3, [r7, #8]
|
|
break;
|
|
800c070: e015 b.n 800c09e <HAL_RCC_GetSysClockFreq+0x96>
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
|
|
800c072: f7fe ff93 bl 800af9c <LL_RCC_HSE_IsEnabledDiv2>
|
|
800c076: 4603 mov r3, r0
|
|
800c078: 2b01 cmp r3, #1
|
|
800c07a: d102 bne.n 800c082 <HAL_RCC_GetSysClockFreq+0x7a>
|
|
{
|
|
pllinputfreq = HSE_VALUE / 2U;
|
|
800c07c: 4b16 ldr r3, [pc, #88] @ (800c0d8 <HAL_RCC_GetSysClockFreq+0xd0>)
|
|
800c07e: 60bb str r3, [r7, #8]
|
|
}
|
|
else
|
|
{
|
|
pllinputfreq = HSE_VALUE;
|
|
}
|
|
break;
|
|
800c080: e00d b.n 800c09e <HAL_RCC_GetSysClockFreq+0x96>
|
|
pllinputfreq = HSE_VALUE;
|
|
800c082: 4b16 ldr r3, [pc, #88] @ (800c0dc <HAL_RCC_GetSysClockFreq+0xd4>)
|
|
800c084: 60bb str r3, [r7, #8]
|
|
break;
|
|
800c086: e00a b.n 800c09e <HAL_RCC_GetSysClockFreq+0x96>
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
|
|
800c088: f7ff f95b bl 800b342 <LL_RCC_MSI_GetRange>
|
|
800c08c: 4603 mov r3, r0
|
|
800c08e: 091b lsrs r3, r3, #4
|
|
800c090: f003 030f and.w r3, r3, #15
|
|
800c094: 4a0f ldr r2, [pc, #60] @ (800c0d4 <HAL_RCC_GetSysClockFreq+0xcc>)
|
|
800c096: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800c09a: 60bb str r3, [r7, #8]
|
|
break;
|
|
800c09c: bf00 nop
|
|
}
|
|
sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(),
|
|
800c09e: f7ff fa72 bl 800b586 <LL_RCC_PLL_GetN>
|
|
800c0a2: 4602 mov r2, r0
|
|
800c0a4: 68bb ldr r3, [r7, #8]
|
|
800c0a6: fb03 f402 mul.w r4, r3, r2
|
|
800c0aa: f7ff fa85 bl 800b5b8 <LL_RCC_PLL_GetDivider>
|
|
800c0ae: 4603 mov r3, r0
|
|
800c0b0: 091b lsrs r3, r3, #4
|
|
800c0b2: 3301 adds r3, #1
|
|
800c0b4: fbb4 f4f3 udiv r4, r4, r3
|
|
800c0b8: f7ff fa72 bl 800b5a0 <LL_RCC_PLL_GetR>
|
|
800c0bc: 4603 mov r3, r0
|
|
800c0be: 0f5b lsrs r3, r3, #29
|
|
800c0c0: 3301 adds r3, #1
|
|
800c0c2: fbb4 f3f3 udiv r3, r4, r3
|
|
800c0c6: 60fb str r3, [r7, #12]
|
|
LL_RCC_PLL_GetR());
|
|
}
|
|
|
|
return sysclockfreq;
|
|
800c0c8: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800c0ca: 4618 mov r0, r3
|
|
800c0cc: 3714 adds r7, #20
|
|
800c0ce: 46bd mov sp, r7
|
|
800c0d0: bd90 pop {r4, r7, pc}
|
|
800c0d2: bf00 nop
|
|
800c0d4: 0801e5cc .word 0x0801e5cc
|
|
800c0d8: 00f42400 .word 0x00f42400
|
|
800c0dc: 01e84800 .word 0x01e84800
|
|
|
|
0800c0e0 <HAL_RCC_GetHCLKFreq>:
|
|
/**
|
|
* @brief Return the HCLK frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
800c0e0: b598 push {r3, r4, r7, lr}
|
|
800c0e2: af00 add r7, sp, #0
|
|
/* Get SysClock and Compute HCLK1 frequency ---------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler())));
|
|
800c0e4: f7ff ff90 bl 800c008 <HAL_RCC_GetSysClockFreq>
|
|
800c0e8: 4604 mov r4, r0
|
|
800c0ea: f7ff f9dd bl 800b4a8 <LL_RCC_GetAHBPrescaler>
|
|
800c0ee: 4603 mov r3, r0
|
|
800c0f0: 091b lsrs r3, r3, #4
|
|
800c0f2: f003 030f and.w r3, r3, #15
|
|
800c0f6: 4a03 ldr r2, [pc, #12] @ (800c104 <HAL_RCC_GetHCLKFreq+0x24>)
|
|
800c0f8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800c0fc: fbb4 f3f3 udiv r3, r4, r3
|
|
}
|
|
800c100: 4618 mov r0, r3
|
|
800c102: bd98 pop {r3, r4, r7, pc}
|
|
800c104: 0801e56c .word 0x0801e56c
|
|
|
|
0800c108 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
800c108: b598 push {r3, r4, r7, lr}
|
|
800c10a: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler())));
|
|
800c10c: f7ff ffe8 bl 800c0e0 <HAL_RCC_GetHCLKFreq>
|
|
800c110: 4604 mov r4, r0
|
|
800c112: f7ff f9fc bl 800b50e <LL_RCC_GetAPB2Prescaler>
|
|
800c116: 4603 mov r3, r0
|
|
800c118: 0adb lsrs r3, r3, #11
|
|
800c11a: f003 0307 and.w r3, r3, #7
|
|
800c11e: 4a04 ldr r2, [pc, #16] @ (800c130 <HAL_RCC_GetPCLK2Freq+0x28>)
|
|
800c120: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800c124: f003 031f and.w r3, r3, #31
|
|
800c128: fa24 f303 lsr.w r3, r4, r3
|
|
}
|
|
800c12c: 4618 mov r0, r3
|
|
800c12e: bd98 pop {r3, r4, r7, pc}
|
|
800c130: 0801e5ac .word 0x0801e5ac
|
|
|
|
0800c134 <HAL_RCC_GetClockConfig>:
|
|
* will be configured.
|
|
* @param pFLatency Pointer on the Flash Latency.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
800c134: b580 push {r7, lr}
|
|
800c136: b082 sub sp, #8
|
|
800c138: af00 add r7, sp, #0
|
|
800c13a: 6078 str r0, [r7, #4]
|
|
800c13c: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(RCC_ClkInitStruct != (void *)NULL);
|
|
assert_param(pFLatency != (void *)NULL);
|
|
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 |
|
|
800c13e: 687b ldr r3, [r7, #4]
|
|
800c140: 226f movs r2, #111 @ 0x6f
|
|
800c142: 601a str r2, [r3, #0]
|
|
RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4);
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = LL_RCC_GetSysClkSource();
|
|
800c144: f7ff f93b bl 800b3be <LL_RCC_GetSysClkSource>
|
|
800c148: 4602 mov r2, r0
|
|
800c14a: 687b ldr r3, [r7, #4]
|
|
800c14c: 605a str r2, [r3, #4]
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = LL_RCC_GetAHBPrescaler();
|
|
800c14e: f7ff f9ab bl 800b4a8 <LL_RCC_GetAHBPrescaler>
|
|
800c152: 4602 mov r2, r0
|
|
800c154: 687b ldr r3, [r7, #4]
|
|
800c156: 609a str r2, [r3, #8]
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = LL_RCC_GetAPB1Prescaler();
|
|
800c158: f7ff f9cd bl 800b4f6 <LL_RCC_GetAPB1Prescaler>
|
|
800c15c: 4602 mov r2, r0
|
|
800c15e: 687b ldr r3, [r7, #4]
|
|
800c160: 60da str r2, [r3, #12]
|
|
|
|
/* Get the APB2 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB2CLKDivider = LL_RCC_GetAPB2Prescaler();
|
|
800c162: f7ff f9d4 bl 800b50e <LL_RCC_GetAPB2Prescaler>
|
|
800c166: 4602 mov r2, r0
|
|
800c168: 687b ldr r3, [r7, #4]
|
|
800c16a: 611a str r2, [r3, #16]
|
|
|
|
/* Get the AHBCLK2Divider configuration ------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLK2Divider = LL_C2_RCC_GetAHBPrescaler();
|
|
800c16c: f7ff f9a8 bl 800b4c0 <LL_C2_RCC_GetAHBPrescaler>
|
|
800c170: 4602 mov r2, r0
|
|
800c172: 687b ldr r3, [r7, #4]
|
|
800c174: 615a str r2, [r3, #20]
|
|
|
|
/* Get the AHBCLK4Divider configuration ------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLK4Divider = LL_RCC_GetAHB4Prescaler();
|
|
800c176: f7ff f9b0 bl 800b4da <LL_RCC_GetAHB4Prescaler>
|
|
800c17a: 4602 mov r2, r0
|
|
800c17c: 687b ldr r3, [r7, #4]
|
|
800c17e: 619a str r2, [r3, #24]
|
|
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = __HAL_FLASH_GET_LATENCY();
|
|
800c180: 4b04 ldr r3, [pc, #16] @ (800c194 <HAL_RCC_GetClockConfig+0x60>)
|
|
800c182: 681b ldr r3, [r3, #0]
|
|
800c184: f003 0207 and.w r2, r3, #7
|
|
800c188: 683b ldr r3, [r7, #0]
|
|
800c18a: 601a str r2, [r3, #0]
|
|
}
|
|
800c18c: bf00 nop
|
|
800c18e: 3708 adds r7, #8
|
|
800c190: 46bd mov sp, r7
|
|
800c192: bd80 pop {r7, pc}
|
|
800c194: 58004000 .word 0x58004000
|
|
|
|
0800c198 <RCC_SetFlashLatencyFromMSIRange>:
|
|
voltage range.
|
|
* @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range)
|
|
{
|
|
800c198: b590 push {r4, r7, lr}
|
|
800c19a: b085 sub sp, #20
|
|
800c19c: af00 add r7, sp, #0
|
|
800c19e: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range));
|
|
|
|
/* MSI frequency range in Hz */
|
|
if (MSI_Range > RCC_MSIRANGE_11)
|
|
800c1a0: 687b ldr r3, [r7, #4]
|
|
800c1a2: 2bb0 cmp r3, #176 @ 0xb0
|
|
800c1a4: d903 bls.n 800c1ae <RCC_SetFlashLatencyFromMSIRange+0x16>
|
|
{
|
|
msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11);
|
|
800c1a6: 4b15 ldr r3, [pc, #84] @ (800c1fc <RCC_SetFlashLatencyFromMSIRange+0x64>)
|
|
800c1a8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800c1aa: 60fb str r3, [r7, #12]
|
|
800c1ac: e007 b.n 800c1be <RCC_SetFlashLatencyFromMSIRange+0x26>
|
|
}
|
|
else
|
|
{
|
|
msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range);
|
|
800c1ae: 687b ldr r3, [r7, #4]
|
|
800c1b0: 091b lsrs r3, r3, #4
|
|
800c1b2: f003 030f and.w r3, r3, #15
|
|
800c1b6: 4a11 ldr r2, [pc, #68] @ (800c1fc <RCC_SetFlashLatencyFromMSIRange+0x64>)
|
|
800c1b8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800c1bc: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler());
|
|
800c1be: f7ff f98c bl 800b4da <LL_RCC_GetAHB4Prescaler>
|
|
800c1c2: 4603 mov r3, r0
|
|
800c1c4: 091b lsrs r3, r3, #4
|
|
800c1c6: f003 030f and.w r3, r3, #15
|
|
800c1ca: 4a0d ldr r2, [pc, #52] @ (800c200 <RCC_SetFlashLatencyFromMSIRange+0x68>)
|
|
800c1cc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800c1d0: 68fa ldr r2, [r7, #12]
|
|
800c1d2: fbb2 f3f3 udiv r3, r2, r3
|
|
800c1d6: 60bb str r3, [r7, #8]
|
|
|
|
#if defined(PWR_CR1_VOS)
|
|
return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange());
|
|
800c1d8: 68bb ldr r3, [r7, #8]
|
|
800c1da: 4a0a ldr r2, [pc, #40] @ (800c204 <RCC_SetFlashLatencyFromMSIRange+0x6c>)
|
|
800c1dc: fba2 2303 umull r2, r3, r2, r3
|
|
800c1e0: 0c9c lsrs r4, r3, #18
|
|
800c1e2: f7fe febd bl 800af60 <HAL_PWREx_GetVoltageRange>
|
|
800c1e6: 4603 mov r3, r0
|
|
800c1e8: 4619 mov r1, r3
|
|
800c1ea: 4620 mov r0, r4
|
|
800c1ec: f000 f80c bl 800c208 <RCC_SetFlashLatency>
|
|
800c1f0: 4603 mov r3, r0
|
|
#else
|
|
return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
#endif /* PWR_CR1_VOS */
|
|
}
|
|
800c1f2: 4618 mov r0, r3
|
|
800c1f4: 3714 adds r7, #20
|
|
800c1f6: 46bd mov sp, r7
|
|
800c1f8: bd90 pop {r4, r7, pc}
|
|
800c1fa: bf00 nop
|
|
800c1fc: 0801e5cc .word 0x0801e5cc
|
|
800c200: 0801e56c .word 0x0801e56c
|
|
800c204: 431bde83 .word 0x431bde83
|
|
|
|
0800c208 <RCC_SetFlashLatency>:
|
|
* @param Flash_ClkSrcFreq Flash Clock Source (in MHz)
|
|
* @param VCORE_Voltage Current Vcore voltage (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage)
|
|
{
|
|
800c208: b590 push {r4, r7, lr}
|
|
800c20a: b093 sub sp, #76 @ 0x4c
|
|
800c20c: af00 add r7, sp, #0
|
|
800c20e: 6078 str r0, [r7, #4]
|
|
800c210: 6039 str r1, [r7, #0]
|
|
/* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */
|
|
const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL};
|
|
800c212: 4b37 ldr r3, [pc, #220] @ (800c2f0 <RCC_SetFlashLatency+0xe8>)
|
|
800c214: f107 0428 add.w r4, r7, #40 @ 0x28
|
|
800c218: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
800c21a: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
#if defined(PWR_CR1_VOS)
|
|
/* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */
|
|
const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL};
|
|
800c21e: 4a35 ldr r2, [pc, #212] @ (800c2f4 <RCC_SetFlashLatency+0xec>)
|
|
800c220: f107 031c add.w r3, r7, #28
|
|
800c224: ca07 ldmia r2, {r0, r1, r2}
|
|
800c226: e883 0007 stmia.w r3, {r0, r1, r2}
|
|
#endif /* PWR_CR1_VOS */
|
|
/* Flash Latency range */
|
|
const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3};
|
|
800c22a: 4b33 ldr r3, [pc, #204] @ (800c2f8 <RCC_SetFlashLatency+0xf0>)
|
|
800c22c: f107 040c add.w r4, r7, #12
|
|
800c230: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
800c232: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
800c236: 2300 movs r3, #0
|
|
800c238: 647b str r3, [r7, #68] @ 0x44
|
|
uint32_t tickstart;
|
|
|
|
#if defined(PWR_CR1_VOS)
|
|
if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
800c23a: 683b ldr r3, [r7, #0]
|
|
800c23c: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
800c240: d11a bne.n 800c278 <RCC_SetFlashLatency+0x70>
|
|
{
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
|
|
800c242: 2300 movs r3, #0
|
|
800c244: 643b str r3, [r7, #64] @ 0x40
|
|
800c246: e013 b.n 800c270 <RCC_SetFlashLatency+0x68>
|
|
{
|
|
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index])
|
|
800c248: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800c24a: 009b lsls r3, r3, #2
|
|
800c24c: 3348 adds r3, #72 @ 0x48
|
|
800c24e: 443b add r3, r7
|
|
800c250: f853 3c20 ldr.w r3, [r3, #-32]
|
|
800c254: 687a ldr r2, [r7, #4]
|
|
800c256: 429a cmp r2, r3
|
|
800c258: d807 bhi.n 800c26a <RCC_SetFlashLatency+0x62>
|
|
{
|
|
latency = FLASH_LATENCY_RANGE[index];
|
|
800c25a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800c25c: 009b lsls r3, r3, #2
|
|
800c25e: 3348 adds r3, #72 @ 0x48
|
|
800c260: 443b add r3, r7
|
|
800c262: f853 3c3c ldr.w r3, [r3, #-60]
|
|
800c266: 647b str r3, [r7, #68] @ 0x44
|
|
break;
|
|
800c268: e020 b.n 800c2ac <RCC_SetFlashLatency+0xa4>
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
|
|
800c26a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800c26c: 3301 adds r3, #1
|
|
800c26e: 643b str r3, [r7, #64] @ 0x40
|
|
800c270: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800c272: 2b03 cmp r3, #3
|
|
800c274: d9e8 bls.n 800c248 <RCC_SetFlashLatency+0x40>
|
|
800c276: e019 b.n 800c2ac <RCC_SetFlashLatency+0xa4>
|
|
}
|
|
}
|
|
}
|
|
else /* PWR_REGULATOR_VOLTAGE_SCALE2 */
|
|
{
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++)
|
|
800c278: 2300 movs r3, #0
|
|
800c27a: 63fb str r3, [r7, #60] @ 0x3c
|
|
800c27c: e013 b.n 800c2a6 <RCC_SetFlashLatency+0x9e>
|
|
{
|
|
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index])
|
|
800c27e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c280: 009b lsls r3, r3, #2
|
|
800c282: 3348 adds r3, #72 @ 0x48
|
|
800c284: 443b add r3, r7
|
|
800c286: f853 3c2c ldr.w r3, [r3, #-44]
|
|
800c28a: 687a ldr r2, [r7, #4]
|
|
800c28c: 429a cmp r2, r3
|
|
800c28e: d807 bhi.n 800c2a0 <RCC_SetFlashLatency+0x98>
|
|
{
|
|
latency = FLASH_LATENCY_RANGE[index];
|
|
800c290: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c292: 009b lsls r3, r3, #2
|
|
800c294: 3348 adds r3, #72 @ 0x48
|
|
800c296: 443b add r3, r7
|
|
800c298: f853 3c3c ldr.w r3, [r3, #-60]
|
|
800c29c: 647b str r3, [r7, #68] @ 0x44
|
|
break;
|
|
800c29e: e005 b.n 800c2ac <RCC_SetFlashLatency+0xa4>
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++)
|
|
800c2a0: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c2a2: 3301 adds r3, #1
|
|
800c2a4: 63fb str r3, [r7, #60] @ 0x3c
|
|
800c2a6: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800c2a8: 2b02 cmp r3, #2
|
|
800c2aa: d9e8 bls.n 800c27e <RCC_SetFlashLatency+0x76>
|
|
break;
|
|
}
|
|
}
|
|
#endif /* PWR_CR1_VOS */
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
800c2ac: 4b13 ldr r3, [pc, #76] @ (800c2fc <RCC_SetFlashLatency+0xf4>)
|
|
800c2ae: 681b ldr r3, [r3, #0]
|
|
800c2b0: f023 0207 bic.w r2, r3, #7
|
|
800c2b4: 4911 ldr r1, [pc, #68] @ (800c2fc <RCC_SetFlashLatency+0xf4>)
|
|
800c2b6: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800c2b8: 4313 orrs r3, r2
|
|
800c2ba: 600b str r3, [r1, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800c2bc: f7fa fb56 bl 800696c <HAL_GetTick>
|
|
800c2c0: 63b8 str r0, [r7, #56] @ 0x38
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != latency)
|
|
800c2c2: e008 b.n 800c2d6 <RCC_SetFlashLatency+0xce>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
800c2c4: f7fa fb52 bl 800696c <HAL_GetTick>
|
|
800c2c8: 4602 mov r2, r0
|
|
800c2ca: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800c2cc: 1ad3 subs r3, r2, r3
|
|
800c2ce: 2b02 cmp r3, #2
|
|
800c2d0: d901 bls.n 800c2d6 <RCC_SetFlashLatency+0xce>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800c2d2: 2303 movs r3, #3
|
|
800c2d4: e007 b.n 800c2e6 <RCC_SetFlashLatency+0xde>
|
|
while (__HAL_FLASH_GET_LATENCY() != latency)
|
|
800c2d6: 4b09 ldr r3, [pc, #36] @ (800c2fc <RCC_SetFlashLatency+0xf4>)
|
|
800c2d8: 681b ldr r3, [r3, #0]
|
|
800c2da: f003 0307 and.w r3, r3, #7
|
|
800c2de: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
800c2e0: 429a cmp r2, r3
|
|
800c2e2: d1ef bne.n 800c2c4 <RCC_SetFlashLatency+0xbc>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800c2e4: 2300 movs r3, #0
|
|
}
|
|
800c2e6: 4618 mov r0, r3
|
|
800c2e8: 374c adds r7, #76 @ 0x4c
|
|
800c2ea: 46bd mov sp, r7
|
|
800c2ec: bd90 pop {r4, r7, pc}
|
|
800c2ee: bf00 nop
|
|
800c2f0: 0801e2f0 .word 0x0801e2f0
|
|
800c2f4: 0801e300 .word 0x0801e300
|
|
800c2f8: 0801e30c .word 0x0801e30c
|
|
800c2fc: 58004000 .word 0x58004000
|
|
|
|
0800c300 <LL_RCC_LSE_IsEnabled>:
|
|
{
|
|
800c300: b480 push {r7}
|
|
800c302: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL);
|
|
800c304: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c308: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800c30c: f003 0301 and.w r3, r3, #1
|
|
800c310: 2b01 cmp r3, #1
|
|
800c312: d101 bne.n 800c318 <LL_RCC_LSE_IsEnabled+0x18>
|
|
800c314: 2301 movs r3, #1
|
|
800c316: e000 b.n 800c31a <LL_RCC_LSE_IsEnabled+0x1a>
|
|
800c318: 2300 movs r3, #0
|
|
}
|
|
800c31a: 4618 mov r0, r3
|
|
800c31c: 46bd mov sp, r7
|
|
800c31e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c322: 4770 bx lr
|
|
|
|
0800c324 <LL_RCC_LSE_IsReady>:
|
|
{
|
|
800c324: b480 push {r7}
|
|
800c326: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
|
|
800c328: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c32c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800c330: f003 0302 and.w r3, r3, #2
|
|
800c334: 2b02 cmp r3, #2
|
|
800c336: d101 bne.n 800c33c <LL_RCC_LSE_IsReady+0x18>
|
|
800c338: 2301 movs r3, #1
|
|
800c33a: e000 b.n 800c33e <LL_RCC_LSE_IsReady+0x1a>
|
|
800c33c: 2300 movs r3, #0
|
|
}
|
|
800c33e: 4618 mov r0, r3
|
|
800c340: 46bd mov sp, r7
|
|
800c342: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c346: 4770 bx lr
|
|
|
|
0800c348 <LL_RCC_MSI_EnablePLLMode>:
|
|
{
|
|
800c348: b480 push {r7}
|
|
800c34a: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
|
|
800c34c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c350: 681b ldr r3, [r3, #0]
|
|
800c352: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c356: f043 0304 orr.w r3, r3, #4
|
|
800c35a: 6013 str r3, [r2, #0]
|
|
}
|
|
800c35c: bf00 nop
|
|
800c35e: 46bd mov sp, r7
|
|
800c360: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c364: 4770 bx lr
|
|
|
|
0800c366 <LL_RCC_SetRFWKPClockSource>:
|
|
{
|
|
800c366: b480 push {r7}
|
|
800c368: b083 sub sp, #12
|
|
800c36a: af00 add r7, sp, #0
|
|
800c36c: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source);
|
|
800c36e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c372: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800c376: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
800c37a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c37e: 687b ldr r3, [r7, #4]
|
|
800c380: 4313 orrs r3, r2
|
|
800c382: f8c1 3094 str.w r3, [r1, #148] @ 0x94
|
|
}
|
|
800c386: bf00 nop
|
|
800c388: 370c adds r7, #12
|
|
800c38a: 46bd mov sp, r7
|
|
800c38c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c390: 4770 bx lr
|
|
|
|
0800c392 <LL_RCC_SetSMPSClockSource>:
|
|
{
|
|
800c392: b480 push {r7}
|
|
800c394: b083 sub sp, #12
|
|
800c396: af00 add r7, sp, #0
|
|
800c398: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource);
|
|
800c39a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c39e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800c3a0: f023 0203 bic.w r2, r3, #3
|
|
800c3a4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c3a8: 687b ldr r3, [r7, #4]
|
|
800c3aa: 4313 orrs r3, r2
|
|
800c3ac: 624b str r3, [r1, #36] @ 0x24
|
|
}
|
|
800c3ae: bf00 nop
|
|
800c3b0: 370c adds r7, #12
|
|
800c3b2: 46bd mov sp, r7
|
|
800c3b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c3b8: 4770 bx lr
|
|
|
|
0800c3ba <LL_RCC_SetSMPSPrescaler>:
|
|
{
|
|
800c3ba: b480 push {r7}
|
|
800c3bc: b083 sub sp, #12
|
|
800c3be: af00 add r7, sp, #0
|
|
800c3c0: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler);
|
|
800c3c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c3c6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800c3c8: f023 0230 bic.w r2, r3, #48 @ 0x30
|
|
800c3cc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c3d0: 687b ldr r3, [r7, #4]
|
|
800c3d2: 4313 orrs r3, r2
|
|
800c3d4: 624b str r3, [r1, #36] @ 0x24
|
|
}
|
|
800c3d6: bf00 nop
|
|
800c3d8: 370c adds r7, #12
|
|
800c3da: 46bd mov sp, r7
|
|
800c3dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c3e0: 4770 bx lr
|
|
|
|
0800c3e2 <LL_RCC_SetUSARTClockSource>:
|
|
{
|
|
800c3e2: b480 push {r7}
|
|
800c3e4: b083 sub sp, #12
|
|
800c3e6: af00 add r7, sp, #0
|
|
800c3e8: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource);
|
|
800c3ea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c3ee: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800c3f2: f023 0203 bic.w r2, r3, #3
|
|
800c3f6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c3fa: 687b ldr r3, [r7, #4]
|
|
800c3fc: 4313 orrs r3, r2
|
|
800c3fe: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
800c402: bf00 nop
|
|
800c404: 370c adds r7, #12
|
|
800c406: 46bd mov sp, r7
|
|
800c408: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c40c: 4770 bx lr
|
|
|
|
0800c40e <LL_RCC_SetLPUARTClockSource>:
|
|
{
|
|
800c40e: b480 push {r7}
|
|
800c410: b083 sub sp, #12
|
|
800c412: af00 add r7, sp, #0
|
|
800c414: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
|
|
800c416: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c41a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800c41e: f423 6240 bic.w r2, r3, #3072 @ 0xc00
|
|
800c422: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c426: 687b ldr r3, [r7, #4]
|
|
800c428: 4313 orrs r3, r2
|
|
800c42a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
800c42e: bf00 nop
|
|
800c430: 370c adds r7, #12
|
|
800c432: 46bd mov sp, r7
|
|
800c434: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c438: 4770 bx lr
|
|
|
|
0800c43a <LL_RCC_SetI2CClockSource>:
|
|
{
|
|
800c43a: b480 push {r7}
|
|
800c43c: b083 sub sp, #12
|
|
800c43e: af00 add r7, sp, #0
|
|
800c440: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U));
|
|
800c442: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c446: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
|
|
800c44a: 687b ldr r3, [r7, #4]
|
|
800c44c: 091b lsrs r3, r3, #4
|
|
800c44e: f403 237f and.w r3, r3, #1044480 @ 0xff000
|
|
800c452: 43db mvns r3, r3
|
|
800c454: 401a ands r2, r3
|
|
800c456: 687b ldr r3, [r7, #4]
|
|
800c458: 011b lsls r3, r3, #4
|
|
800c45a: f403 237f and.w r3, r3, #1044480 @ 0xff000
|
|
800c45e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c462: 4313 orrs r3, r2
|
|
800c464: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
800c468: bf00 nop
|
|
800c46a: 370c adds r7, #12
|
|
800c46c: 46bd mov sp, r7
|
|
800c46e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c472: 4770 bx lr
|
|
|
|
0800c474 <LL_RCC_SetLPTIMClockSource>:
|
|
{
|
|
800c474: b480 push {r7}
|
|
800c476: b083 sub sp, #12
|
|
800c478: af00 add r7, sp, #0
|
|
800c47a: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
|
|
800c47c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c480: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
|
|
800c484: 687b ldr r3, [r7, #4]
|
|
800c486: 0c1b lsrs r3, r3, #16
|
|
800c488: 041b lsls r3, r3, #16
|
|
800c48a: 43db mvns r3, r3
|
|
800c48c: 401a ands r2, r3
|
|
800c48e: 687b ldr r3, [r7, #4]
|
|
800c490: 041b lsls r3, r3, #16
|
|
800c492: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c496: 4313 orrs r3, r2
|
|
800c498: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
800c49c: bf00 nop
|
|
800c49e: 370c adds r7, #12
|
|
800c4a0: 46bd mov sp, r7
|
|
800c4a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c4a6: 4770 bx lr
|
|
|
|
0800c4a8 <LL_RCC_SetSAIClockSource>:
|
|
{
|
|
800c4a8: b480 push {r7}
|
|
800c4aa: b083 sub sp, #12
|
|
800c4ac: af00 add r7, sp, #0
|
|
800c4ae: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
|
|
800c4b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c4b4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800c4b8: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
800c4bc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c4c0: 687b ldr r3, [r7, #4]
|
|
800c4c2: 4313 orrs r3, r2
|
|
800c4c4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
800c4c8: bf00 nop
|
|
800c4ca: 370c adds r7, #12
|
|
800c4cc: 46bd mov sp, r7
|
|
800c4ce: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c4d2: 4770 bx lr
|
|
|
|
0800c4d4 <LL_RCC_SetRNGClockSource>:
|
|
{
|
|
800c4d4: b480 push {r7}
|
|
800c4d6: b083 sub sp, #12
|
|
800c4d8: af00 add r7, sp, #0
|
|
800c4da: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
|
|
800c4dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c4e0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800c4e4: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000
|
|
800c4e8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c4ec: 687b ldr r3, [r7, #4]
|
|
800c4ee: 4313 orrs r3, r2
|
|
800c4f0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
800c4f4: bf00 nop
|
|
800c4f6: 370c adds r7, #12
|
|
800c4f8: 46bd mov sp, r7
|
|
800c4fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c4fe: 4770 bx lr
|
|
|
|
0800c500 <LL_RCC_SetCLK48ClockSource>:
|
|
{
|
|
800c500: b480 push {r7}
|
|
800c502: b083 sub sp, #12
|
|
800c504: af00 add r7, sp, #0
|
|
800c506: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource);
|
|
800c508: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c50c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800c510: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
800c514: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c518: 687b ldr r3, [r7, #4]
|
|
800c51a: 4313 orrs r3, r2
|
|
800c51c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
800c520: bf00 nop
|
|
800c522: 370c adds r7, #12
|
|
800c524: 46bd mov sp, r7
|
|
800c526: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c52a: 4770 bx lr
|
|
|
|
0800c52c <LL_RCC_SetUSBClockSource>:
|
|
{
|
|
800c52c: b580 push {r7, lr}
|
|
800c52e: b082 sub sp, #8
|
|
800c530: af00 add r7, sp, #0
|
|
800c532: 6078 str r0, [r7, #4]
|
|
LL_RCC_SetCLK48ClockSource(USBxSource);
|
|
800c534: 6878 ldr r0, [r7, #4]
|
|
800c536: f7ff ffe3 bl 800c500 <LL_RCC_SetCLK48ClockSource>
|
|
}
|
|
800c53a: bf00 nop
|
|
800c53c: 3708 adds r7, #8
|
|
800c53e: 46bd mov sp, r7
|
|
800c540: bd80 pop {r7, pc}
|
|
|
|
0800c542 <LL_RCC_SetADCClockSource>:
|
|
{
|
|
800c542: b480 push {r7}
|
|
800c544: b083 sub sp, #12
|
|
800c546: af00 add r7, sp, #0
|
|
800c548: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
|
|
800c54a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c54e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800c552: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
|
|
800c556: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c55a: 687b ldr r3, [r7, #4]
|
|
800c55c: 4313 orrs r3, r2
|
|
800c55e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
800c562: bf00 nop
|
|
800c564: 370c adds r7, #12
|
|
800c566: 46bd mov sp, r7
|
|
800c568: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c56c: 4770 bx lr
|
|
|
|
0800c56e <LL_RCC_SetRTCClockSource>:
|
|
{
|
|
800c56e: b480 push {r7}
|
|
800c570: b083 sub sp, #12
|
|
800c572: af00 add r7, sp, #0
|
|
800c574: 6078 str r0, [r7, #4]
|
|
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
|
|
800c576: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c57a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800c57e: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
800c582: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c586: 687b ldr r3, [r7, #4]
|
|
800c588: 4313 orrs r3, r2
|
|
800c58a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
}
|
|
800c58e: bf00 nop
|
|
800c590: 370c adds r7, #12
|
|
800c592: 46bd mov sp, r7
|
|
800c594: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c598: 4770 bx lr
|
|
|
|
0800c59a <LL_RCC_GetRTCClockSource>:
|
|
{
|
|
800c59a: b480 push {r7}
|
|
800c59c: af00 add r7, sp, #0
|
|
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
|
|
800c59e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c5a2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800c5a6: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
}
|
|
800c5aa: 4618 mov r0, r3
|
|
800c5ac: 46bd mov sp, r7
|
|
800c5ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c5b2: 4770 bx lr
|
|
|
|
0800c5b4 <LL_RCC_ForceBackupDomainReset>:
|
|
{
|
|
800c5b4: b480 push {r7}
|
|
800c5b6: af00 add r7, sp, #0
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
|
|
800c5b8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c5bc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800c5c0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c5c4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800c5c8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
800c5cc: bf00 nop
|
|
800c5ce: 46bd mov sp, r7
|
|
800c5d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c5d4: 4770 bx lr
|
|
|
|
0800c5d6 <LL_RCC_ReleaseBackupDomainReset>:
|
|
{
|
|
800c5d6: b480 push {r7}
|
|
800c5d8: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
|
|
800c5da: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c5de: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800c5e2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c5e6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800c5ea: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
800c5ee: bf00 nop
|
|
800c5f0: 46bd mov sp, r7
|
|
800c5f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c5f6: 4770 bx lr
|
|
|
|
0800c5f8 <LL_RCC_PLLSAI1_Enable>:
|
|
{
|
|
800c5f8: b480 push {r7}
|
|
800c5fa: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
|
|
800c5fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c600: 681b ldr r3, [r3, #0]
|
|
800c602: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c606: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
800c60a: 6013 str r3, [r2, #0]
|
|
}
|
|
800c60c: bf00 nop
|
|
800c60e: 46bd mov sp, r7
|
|
800c610: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c614: 4770 bx lr
|
|
|
|
0800c616 <LL_RCC_PLLSAI1_Disable>:
|
|
{
|
|
800c616: b480 push {r7}
|
|
800c618: af00 add r7, sp, #0
|
|
CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
|
|
800c61a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c61e: 681b ldr r3, [r3, #0]
|
|
800c620: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c624: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
800c628: 6013 str r3, [r2, #0]
|
|
}
|
|
800c62a: bf00 nop
|
|
800c62c: 46bd mov sp, r7
|
|
800c62e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c632: 4770 bx lr
|
|
|
|
0800c634 <LL_RCC_PLLSAI1_IsReady>:
|
|
{
|
|
800c634: b480 push {r7}
|
|
800c636: af00 add r7, sp, #0
|
|
return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL);
|
|
800c638: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c63c: 681b ldr r3, [r3, #0]
|
|
800c63e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
800c642: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
800c646: d101 bne.n 800c64c <LL_RCC_PLLSAI1_IsReady+0x18>
|
|
800c648: 2301 movs r3, #1
|
|
800c64a: e000 b.n 800c64e <LL_RCC_PLLSAI1_IsReady+0x1a>
|
|
800c64c: 2300 movs r3, #0
|
|
}
|
|
800c64e: 4618 mov r0, r3
|
|
800c650: 46bd mov sp, r7
|
|
800c652: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c656: 4770 bx lr
|
|
|
|
0800c658 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
800c658: b580 push {r7, lr}
|
|
800c65a: b088 sub sp, #32
|
|
800c65c: af00 add r7, sp, #0
|
|
800c65e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
800c660: 2300 movs r3, #0
|
|
800c662: 77fb strb r3, [r7, #31]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
800c664: 2300 movs r3, #0
|
|
800c666: 77bb strb r3, [r7, #30]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
#if defined(SAI1)
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
|
|
800c668: 687b ldr r3, [r7, #4]
|
|
800c66a: 681b ldr r3, [r3, #0]
|
|
800c66c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800c670: 2b00 cmp r3, #0
|
|
800c672: d034 beq.n 800c6de <HAL_RCCEx_PeriphCLKConfig+0x86>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
switch (PeriphClkInit->Sai1ClockSelection)
|
|
800c674: 687b ldr r3, [r7, #4]
|
|
800c676: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800c678: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
800c67c: d021 beq.n 800c6c2 <HAL_RCCEx_PeriphCLKConfig+0x6a>
|
|
800c67e: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
800c682: d81b bhi.n 800c6bc <HAL_RCCEx_PeriphCLKConfig+0x64>
|
|
800c684: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
800c688: d01d beq.n 800c6c6 <HAL_RCCEx_PeriphCLKConfig+0x6e>
|
|
800c68a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
800c68e: d815 bhi.n 800c6bc <HAL_RCCEx_PeriphCLKConfig+0x64>
|
|
800c690: 2b00 cmp r3, #0
|
|
800c692: d00b beq.n 800c6ac <HAL_RCCEx_PeriphCLKConfig+0x54>
|
|
800c694: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
800c698: d110 bne.n 800c6bc <HAL_RCCEx_PeriphCLKConfig+0x64>
|
|
{
|
|
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1 */
|
|
/* Enable SAI1 Clock output generated form System PLL . */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI1CLK);
|
|
800c69a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c69e: 68db ldr r3, [r3, #12]
|
|
800c6a0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c6a4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800c6a8: 60d3 str r3, [r2, #12]
|
|
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
800c6aa: e00d b.n 800c6c8 <HAL_RCCEx_PeriphCLKConfig+0x70>
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */
|
|
/* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1));
|
|
800c6ac: 687b ldr r3, [r7, #4]
|
|
800c6ae: 3304 adds r3, #4
|
|
800c6b0: 4618 mov r0, r3
|
|
800c6b2: f000 f94d bl 800c950 <RCCEx_PLLSAI1_ConfigNP>
|
|
800c6b6: 4603 mov r3, r0
|
|
800c6b8: 77fb strb r3, [r7, #31]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
800c6ba: e005 b.n 800c6c8 <HAL_RCCEx_PeriphCLKConfig+0x70>
|
|
case RCC_SAI1CLKSOURCE_HSI:
|
|
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
800c6bc: 2301 movs r3, #1
|
|
800c6be: 77fb strb r3, [r7, #31]
|
|
break;
|
|
800c6c0: e002 b.n 800c6c8 <HAL_RCCEx_PeriphCLKConfig+0x70>
|
|
break;
|
|
800c6c2: bf00 nop
|
|
800c6c4: e000 b.n 800c6c8 <HAL_RCCEx_PeriphCLKConfig+0x70>
|
|
break;
|
|
800c6c6: bf00 nop
|
|
}
|
|
|
|
if (ret == HAL_OK)
|
|
800c6c8: 7ffb ldrb r3, [r7, #31]
|
|
800c6ca: 2b00 cmp r3, #0
|
|
800c6cc: d105 bne.n 800c6da <HAL_RCCEx_PeriphCLKConfig+0x82>
|
|
{
|
|
/* Set the source of SAI1 clock*/
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
800c6ce: 687b ldr r3, [r7, #4]
|
|
800c6d0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800c6d2: 4618 mov r0, r3
|
|
800c6d4: f7ff fee8 bl 800c4a8 <LL_RCC_SetSAIClockSource>
|
|
800c6d8: e001 b.n 800c6de <HAL_RCCEx_PeriphCLKConfig+0x86>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800c6da: 7ffb ldrb r3, [r7, #31]
|
|
800c6dc: 77bb strb r3, [r7, #30]
|
|
}
|
|
}
|
|
#endif /* SAI1 */
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
800c6de: 687b ldr r3, [r7, #4]
|
|
800c6e0: 681b ldr r3, [r3, #0]
|
|
800c6e2: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
800c6e6: 2b00 cmp r3, #0
|
|
800c6e8: d046 beq.n 800c778 <HAL_RCCEx_PeriphCLKConfig+0x120>
|
|
{
|
|
uint32_t rtcclocksource = LL_RCC_GetRTCClockSource();
|
|
800c6ea: f7ff ff56 bl 800c59a <LL_RCC_GetRTCClockSource>
|
|
800c6ee: 61b8 str r0, [r7, #24]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Configure the clock source only if a different source is expected */
|
|
if (rtcclocksource != PeriphClkInit->RTCClockSelection)
|
|
800c6f0: 687b ldr r3, [r7, #4]
|
|
800c6f2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800c6f4: 69ba ldr r2, [r7, #24]
|
|
800c6f6: 429a cmp r2, r3
|
|
800c6f8: d03c beq.n 800c774 <HAL_RCCEx_PeriphCLKConfig+0x11c>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
HAL_PWR_EnableBkUpAccess();
|
|
800c6fa: f7fe fc21 bl 800af40 <HAL_PWR_EnableBkUpAccess>
|
|
|
|
/* If a clock source is not yet selected */
|
|
if (rtcclocksource == RCC_RTCCLKSOURCE_NONE)
|
|
800c6fe: 69bb ldr r3, [r7, #24]
|
|
800c700: 2b00 cmp r3, #0
|
|
800c702: d105 bne.n 800c710 <HAL_RCCEx_PeriphCLKConfig+0xb8>
|
|
{
|
|
/* Directly set the configuration of the clock source selection */
|
|
LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection);
|
|
800c704: 687b ldr r3, [r7, #4]
|
|
800c706: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800c708: 4618 mov r0, r3
|
|
800c70a: f7ff ff30 bl 800c56e <LL_RCC_SetRTCClockSource>
|
|
800c70e: e02e b.n 800c76e <HAL_RCCEx_PeriphCLKConfig+0x116>
|
|
}
|
|
else /* A clock source is already selected */
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
uint32_t bdcr = LL_RCC_ReadReg(BDCR);
|
|
800c710: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c714: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800c718: 617b str r3, [r7, #20]
|
|
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
LL_RCC_ForceBackupDomainReset();
|
|
800c71a: f7ff ff4b bl 800c5b4 <LL_RCC_ForceBackupDomainReset>
|
|
LL_RCC_ReleaseBackupDomainReset();
|
|
800c71e: f7ff ff5a bl 800c5d6 <LL_RCC_ReleaseBackupDomainReset>
|
|
|
|
/* Set the value of the clock source selection */
|
|
MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection);
|
|
800c722: 697b ldr r3, [r7, #20]
|
|
800c724: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
800c728: 687b ldr r3, [r7, #4]
|
|
800c72a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800c72c: 4313 orrs r3, r2
|
|
800c72e: 617b str r3, [r7, #20]
|
|
|
|
/* Restore the content of BDCR register */
|
|
LL_RCC_WriteReg(BDCR, bdcr);
|
|
800c730: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c734: 697b ldr r3, [r7, #20]
|
|
800c736: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (LL_RCC_LSE_IsEnabled() == 1U)
|
|
800c73a: f7ff fde1 bl 800c300 <LL_RCC_LSE_IsEnabled>
|
|
800c73e: 4603 mov r3, r0
|
|
800c740: 2b01 cmp r3, #1
|
|
800c742: d114 bne.n 800c76e <HAL_RCCEx_PeriphCLKConfig+0x116>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800c744: f7fa f912 bl 800696c <HAL_GetTick>
|
|
800c748: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (LL_RCC_LSE_IsReady() != 1U)
|
|
800c74a: e00b b.n 800c764 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800c74c: f7fa f90e bl 800696c <HAL_GetTick>
|
|
800c750: 4602 mov r2, r0
|
|
800c752: 693b ldr r3, [r7, #16]
|
|
800c754: 1ad3 subs r3, r2, r3
|
|
800c756: f241 3288 movw r2, #5000 @ 0x1388
|
|
800c75a: 4293 cmp r3, r2
|
|
800c75c: d902 bls.n 800c764 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
800c75e: 2303 movs r3, #3
|
|
800c760: 77fb strb r3, [r7, #31]
|
|
break;
|
|
800c762: e004 b.n 800c76e <HAL_RCCEx_PeriphCLKConfig+0x116>
|
|
while (LL_RCC_LSE_IsReady() != 1U)
|
|
800c764: f7ff fdde bl 800c324 <LL_RCC_LSE_IsReady>
|
|
800c768: 4603 mov r3, r0
|
|
800c76a: 2b01 cmp r3, #1
|
|
800c76c: d1ee bne.n 800c74c <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* set overall return value */
|
|
status = ret;
|
|
800c76e: 7ffb ldrb r3, [r7, #31]
|
|
800c770: 77bb strb r3, [r7, #30]
|
|
800c772: e001 b.n 800c778 <HAL_RCCEx_PeriphCLKConfig+0x120>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800c774: 7ffb ldrb r3, [r7, #31]
|
|
800c776: 77bb strb r3, [r7, #30]
|
|
}
|
|
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
800c778: 687b ldr r3, [r7, #4]
|
|
800c77a: 681b ldr r3, [r3, #0]
|
|
800c77c: f003 0301 and.w r3, r3, #1
|
|
800c780: 2b00 cmp r3, #0
|
|
800c782: d004 beq.n 800c78e <HAL_RCCEx_PeriphCLKConfig+0x136>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
800c784: 687b ldr r3, [r7, #4]
|
|
800c786: 699b ldr r3, [r3, #24]
|
|
800c788: 4618 mov r0, r3
|
|
800c78a: f7ff fe2a bl 800c3e2 <LL_RCC_SetUSARTClockSource>
|
|
}
|
|
|
|
#if defined(LPUART1)
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
800c78e: 687b ldr r3, [r7, #4]
|
|
800c790: 681b ldr r3, [r3, #0]
|
|
800c792: f003 0302 and.w r3, r3, #2
|
|
800c796: 2b00 cmp r3, #0
|
|
800c798: d004 beq.n 800c7a4 <HAL_RCCEx_PeriphCLKConfig+0x14c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUAR1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
800c79a: 687b ldr r3, [r7, #4]
|
|
800c79c: 69db ldr r3, [r3, #28]
|
|
800c79e: 4618 mov r0, r3
|
|
800c7a0: f7ff fe35 bl 800c40e <LL_RCC_SetLPUARTClockSource>
|
|
}
|
|
#endif /* LPUART1 */
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
800c7a4: 687b ldr r3, [r7, #4]
|
|
800c7a6: 681b ldr r3, [r3, #0]
|
|
800c7a8: f003 0310 and.w r3, r3, #16
|
|
800c7ac: 2b00 cmp r3, #0
|
|
800c7ae: d004 beq.n 800c7ba <HAL_RCCEx_PeriphCLKConfig+0x162>
|
|
{
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
800c7b0: 687b ldr r3, [r7, #4]
|
|
800c7b2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800c7b4: 4618 mov r0, r3
|
|
800c7b6: f7ff fe5d bl 800c474 <LL_RCC_SetLPTIMClockSource>
|
|
}
|
|
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
800c7ba: 687b ldr r3, [r7, #4]
|
|
800c7bc: 681b ldr r3, [r3, #0]
|
|
800c7be: f003 0320 and.w r3, r3, #32
|
|
800c7c2: 2b00 cmp r3, #0
|
|
800c7c4: d004 beq.n 800c7d0 <HAL_RCCEx_PeriphCLKConfig+0x178>
|
|
{
|
|
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
800c7c6: 687b ldr r3, [r7, #4]
|
|
800c7c8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800c7ca: 4618 mov r0, r3
|
|
800c7cc: f7ff fe52 bl 800c474 <LL_RCC_SetLPTIMClockSource>
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
800c7d0: 687b ldr r3, [r7, #4]
|
|
800c7d2: 681b ldr r3, [r3, #0]
|
|
800c7d4: f003 0304 and.w r3, r3, #4
|
|
800c7d8: 2b00 cmp r3, #0
|
|
800c7da: d004 beq.n 800c7e6 <HAL_RCCEx_PeriphCLKConfig+0x18e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
800c7dc: 687b ldr r3, [r7, #4]
|
|
800c7de: 6a1b ldr r3, [r3, #32]
|
|
800c7e0: 4618 mov r0, r3
|
|
800c7e2: f7ff fe2a bl 800c43a <LL_RCC_SetI2CClockSource>
|
|
}
|
|
|
|
#if defined(I2C3)
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
800c7e6: 687b ldr r3, [r7, #4]
|
|
800c7e8: 681b ldr r3, [r3, #0]
|
|
800c7ea: f003 0308 and.w r3, r3, #8
|
|
800c7ee: 2b00 cmp r3, #0
|
|
800c7f0: d004 beq.n 800c7fc <HAL_RCCEx_PeriphCLKConfig+0x1a4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
800c7f2: 687b ldr r3, [r7, #4]
|
|
800c7f4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800c7f6: 4618 mov r0, r3
|
|
800c7f8: f7ff fe1f bl 800c43a <LL_RCC_SetI2CClockSource>
|
|
}
|
|
#endif /* I2C3 */
|
|
|
|
#if defined(USB)
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|
800c7fc: 687b ldr r3, [r7, #4]
|
|
800c7fe: 681b ldr r3, [r3, #0]
|
|
800c800: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800c804: 2b00 cmp r3, #0
|
|
800c806: d022 beq.n 800c84e <HAL_RCCEx_PeriphCLKConfig+0x1f6>
|
|
{
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
800c808: 687b ldr r3, [r7, #4]
|
|
800c80a: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800c80c: 4618 mov r0, r3
|
|
800c80e: f7ff fe8d bl 800c52c <LL_RCC_SetUSBClockSource>
|
|
|
|
if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
|
800c812: 687b ldr r3, [r7, #4]
|
|
800c814: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800c816: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
800c81a: d107 bne.n 800c82c <HAL_RCCEx_PeriphCLKConfig+0x1d4>
|
|
{
|
|
/* Enable PLLQ output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK);
|
|
800c81c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c820: 68db ldr r3, [r3, #12]
|
|
800c822: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c826: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
800c82a: 60d3 str r3, [r2, #12]
|
|
}
|
|
#if defined(SAI1)
|
|
if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
|
|
800c82c: 687b ldr r3, [r7, #4]
|
|
800c82e: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800c830: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
800c834: d10b bne.n 800c84e <HAL_RCCEx_PeriphCLKConfig+0x1f6>
|
|
{
|
|
/* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
|
|
800c836: 687b ldr r3, [r7, #4]
|
|
800c838: 3304 adds r3, #4
|
|
800c83a: 4618 mov r0, r3
|
|
800c83c: f000 f8e3 bl 800ca06 <RCCEx_PLLSAI1_ConfigNQ>
|
|
800c840: 4603 mov r3, r0
|
|
800c842: 77fb strb r3, [r7, #31]
|
|
|
|
if (ret != HAL_OK)
|
|
800c844: 7ffb ldrb r3, [r7, #31]
|
|
800c846: 2b00 cmp r3, #0
|
|
800c848: d001 beq.n 800c84e <HAL_RCCEx_PeriphCLKConfig+0x1f6>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800c84a: 7ffb ldrb r3, [r7, #31]
|
|
800c84c: 77bb strb r3, [r7, #30]
|
|
#endif /* SAI1 */
|
|
}
|
|
#endif /* USB */
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
800c84e: 687b ldr r3, [r7, #4]
|
|
800c850: 681b ldr r3, [r3, #0]
|
|
800c852: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800c856: 2b00 cmp r3, #0
|
|
800c858: d02b beq.n 800c8b2 <HAL_RCCEx_PeriphCLKConfig+0x25a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
|
|
/* Configure the RNG clock source */
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
800c85a: 687b ldr r3, [r7, #4]
|
|
800c85c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800c85e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800c862: d008 beq.n 800c876 <HAL_RCCEx_PeriphCLKConfig+0x21e>
|
|
800c864: 687b ldr r3, [r7, #4]
|
|
800c866: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800c868: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800c86c: d003 beq.n 800c876 <HAL_RCCEx_PeriphCLKConfig+0x21e>
|
|
800c86e: 687b ldr r3, [r7, #4]
|
|
800c870: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800c872: 2b00 cmp r3, #0
|
|
800c874: d105 bne.n 800c882 <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
800c876: 687b ldr r3, [r7, #4]
|
|
800c878: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800c87a: 4618 mov r0, r3
|
|
800c87c: f7ff fe2a bl 800c4d4 <LL_RCC_SetRNGClockSource>
|
|
800c880: e00a b.n 800c898 <HAL_RCCEx_PeriphCLKConfig+0x240>
|
|
800c882: 687b ldr r3, [r7, #4]
|
|
800c884: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800c886: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800c88a: 60fb str r3, [r7, #12]
|
|
800c88c: 2000 movs r0, #0
|
|
800c88e: f7ff fe21 bl 800c4d4 <LL_RCC_SetRNGClockSource>
|
|
800c892: 68f8 ldr r0, [r7, #12]
|
|
800c894: f7ff fe34 bl 800c500 <LL_RCC_SetCLK48ClockSource>
|
|
|
|
if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
800c898: 687b ldr r3, [r7, #4]
|
|
800c89a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800c89c: f1b3 5fc0 cmp.w r3, #402653184 @ 0x18000000
|
|
800c8a0: d107 bne.n 800c8b2 <HAL_RCCEx_PeriphCLKConfig+0x25a>
|
|
{
|
|
/* Enable PLLQ output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK);
|
|
800c8a2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c8a6: 68db ldr r3, [r3, #12]
|
|
800c8a8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c8ac: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
800c8b0: 60d3 str r3, [r2, #12]
|
|
}
|
|
}
|
|
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
800c8b2: 687b ldr r3, [r7, #4]
|
|
800c8b4: 681b ldr r3, [r3, #0]
|
|
800c8b6: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800c8ba: 2b00 cmp r3, #0
|
|
800c8bc: d022 beq.n 800c904 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
800c8be: 687b ldr r3, [r7, #4]
|
|
800c8c0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800c8c2: 4618 mov r0, r3
|
|
800c8c4: f7ff fe3d bl 800c542 <LL_RCC_SetADCClockSource>
|
|
|
|
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL)
|
|
800c8c8: 687b ldr r3, [r7, #4]
|
|
800c8ca: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800c8cc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
800c8d0: d107 bne.n 800c8e2 <HAL_RCCEx_PeriphCLKConfig+0x28a>
|
|
{
|
|
/* Enable RCC_PLL_RNGCLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
|
|
800c8d2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c8d6: 68db ldr r3, [r3, #12]
|
|
800c8d8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
|
|
800c8dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800c8e0: 60d3 str r3, [r2, #12]
|
|
}
|
|
|
|
#if defined(SAI1)
|
|
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
|
|
800c8e2: 687b ldr r3, [r7, #4]
|
|
800c8e4: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800c8e6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
800c8ea: d10b bne.n 800c904 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
/* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1));
|
|
800c8ec: 687b ldr r3, [r7, #4]
|
|
800c8ee: 3304 adds r3, #4
|
|
800c8f0: 4618 mov r0, r3
|
|
800c8f2: f000 f8e3 bl 800cabc <RCCEx_PLLSAI1_ConfigNR>
|
|
800c8f6: 4603 mov r3, r0
|
|
800c8f8: 77fb strb r3, [r7, #31]
|
|
|
|
if (ret != HAL_OK)
|
|
800c8fa: 7ffb ldrb r3, [r7, #31]
|
|
800c8fc: 2b00 cmp r3, #0
|
|
800c8fe: d001 beq.n 800c904 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800c900: 7ffb ldrb r3, [r7, #31]
|
|
800c902: 77bb strb r3, [r7, #30]
|
|
}
|
|
#endif /* SAI1 */
|
|
}
|
|
|
|
/*-------------------------- RFWKP clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)
|
|
800c904: 687b ldr r3, [r7, #4]
|
|
800c906: 681b ldr r3, [r3, #0]
|
|
800c908: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
800c90c: 2b00 cmp r3, #0
|
|
800c90e: d004 beq.n 800c91a <HAL_RCCEx_PeriphCLKConfig+0x2c2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_RFWKPCLKSOURCE(PeriphClkInit->RFWakeUpClockSelection));
|
|
|
|
/* Configure the RFWKP interface clock source */
|
|
__HAL_RCC_RFWAKEUP_CONFIG(PeriphClkInit->RFWakeUpClockSelection);
|
|
800c910: 687b ldr r3, [r7, #4]
|
|
800c912: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800c914: 4618 mov r0, r3
|
|
800c916: f7ff fd26 bl 800c366 <LL_RCC_SetRFWKPClockSource>
|
|
|
|
}
|
|
|
|
#if defined(RCC_SMPS_SUPPORT)
|
|
/*-------------------------- SMPS clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)
|
|
800c91a: 687b ldr r3, [r7, #4]
|
|
800c91c: 681b ldr r3, [r3, #0]
|
|
800c91e: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
800c922: 2b00 cmp r3, #0
|
|
800c924: d009 beq.n 800c93a <HAL_RCCEx_PeriphCLKConfig+0x2e2>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SMPSCLKDIV(PeriphClkInit->SmpsDivSelection));
|
|
assert_param(IS_RCC_SMPSCLKSOURCE(PeriphClkInit->SmpsClockSelection));
|
|
|
|
/* Configure the SMPS interface clock division factor */
|
|
__HAL_RCC_SMPS_DIV_CONFIG(PeriphClkInit->SmpsDivSelection);
|
|
800c926: 687b ldr r3, [r7, #4]
|
|
800c928: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800c92a: 4618 mov r0, r3
|
|
800c92c: f7ff fd45 bl 800c3ba <LL_RCC_SetSMPSPrescaler>
|
|
|
|
/* Configure the SMPS interface clock source */
|
|
__HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection);
|
|
800c930: 687b ldr r3, [r7, #4]
|
|
800c932: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800c934: 4618 mov r0, r3
|
|
800c936: f7ff fd2c bl 800c392 <LL_RCC_SetSMPSClockSource>
|
|
}
|
|
#endif /* RCC_SMPS_SUPPORT */
|
|
|
|
return status;
|
|
800c93a: 7fbb ldrb r3, [r7, #30]
|
|
}
|
|
800c93c: 4618 mov r0, r3
|
|
800c93e: 3720 adds r7, #32
|
|
800c940: 46bd mov sp, r7
|
|
800c942: bd80 pop {r7, pc}
|
|
|
|
0800c944 <HAL_RCCEx_EnableMSIPLLMode>:
|
|
* @note Prior to enable the PLL-mode of the MSI for automatic hardware
|
|
* calibration LSE oscillator is to be enabled with @ref HAL_RCC_OscConfig().
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableMSIPLLMode(void)
|
|
{
|
|
800c944: b580 push {r7, lr}
|
|
800c946: af00 add r7, sp, #0
|
|
LL_RCC_MSI_EnablePLLMode() ;
|
|
800c948: f7ff fcfe bl 800c348 <LL_RCC_MSI_EnablePLLMode>
|
|
}
|
|
800c94c: bf00 nop
|
|
800c94e: bd80 pop {r7, pc}
|
|
|
|
0800c950 <RCCEx_PLLSAI1_ConfigNP>:
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1)
|
|
{
|
|
800c950: b580 push {r7, lr}
|
|
800c952: b084 sub sp, #16
|
|
800c954: af00 add r7, sp, #0
|
|
800c956: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800c958: 2300 movs r3, #0
|
|
800c95a: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
|
|
assert_param(IS_RCC_PLLP_VALUE(PLLSAI1->PLLP));
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
|
|
|
|
/* Disable the PLLSAI1 */
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
800c95c: f7ff fe5b bl 800c616 <LL_RCC_PLLSAI1_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800c960: f7fa f804 bl 800696c <HAL_GetTick>
|
|
800c964: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
while (LL_RCC_PLLSAI1_IsReady() != 0U)
|
|
800c966: e009 b.n 800c97c <RCCEx_PLLSAI1_ConfigNP+0x2c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
800c968: f7fa f800 bl 800696c <HAL_GetTick>
|
|
800c96c: 4602 mov r2, r0
|
|
800c96e: 68bb ldr r3, [r7, #8]
|
|
800c970: 1ad3 subs r3, r2, r3
|
|
800c972: 2b02 cmp r3, #2
|
|
800c974: d902 bls.n 800c97c <RCCEx_PLLSAI1_ConfigNP+0x2c>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
800c976: 2303 movs r3, #3
|
|
800c978: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800c97a: e004 b.n 800c986 <RCCEx_PLLSAI1_ConfigNP+0x36>
|
|
while (LL_RCC_PLLSAI1_IsReady() != 0U)
|
|
800c97c: f7ff fe5a bl 800c634 <LL_RCC_PLLSAI1_IsReady>
|
|
800c980: 4603 mov r3, r0
|
|
800c982: 2b00 cmp r3, #0
|
|
800c984: d1f0 bne.n 800c968 <RCCEx_PLLSAI1_ConfigNP+0x18>
|
|
}
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
800c986: 7bfb ldrb r3, [r7, #15]
|
|
800c988: 2b00 cmp r3, #0
|
|
800c98a: d137 bne.n 800c9fc <RCCEx_PLLSAI1_ConfigNP+0xac>
|
|
{
|
|
/* Configure the PLLSAI1 Multiplication factor N */
|
|
__HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
|
|
800c98c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c990: 691b ldr r3, [r3, #16]
|
|
800c992: f423 42fe bic.w r2, r3, #32512 @ 0x7f00
|
|
800c996: 687b ldr r3, [r7, #4]
|
|
800c998: 681b ldr r3, [r3, #0]
|
|
800c99a: 021b lsls r3, r3, #8
|
|
800c99c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c9a0: 4313 orrs r3, r2
|
|
800c9a2: 610b str r3, [r1, #16]
|
|
|
|
/* Configure the PLLSAI1 Division factor P */
|
|
__HAL_RCC_PLLSAI1_DIVP_CONFIG(PLLSAI1->PLLP);
|
|
800c9a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c9a8: 691b ldr r3, [r3, #16]
|
|
800c9aa: f423 1278 bic.w r2, r3, #4063232 @ 0x3e0000
|
|
800c9ae: 687b ldr r3, [r7, #4]
|
|
800c9b0: 685b ldr r3, [r3, #4]
|
|
800c9b2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c9b6: 4313 orrs r3, r2
|
|
800c9b8: 610b str r3, [r1, #16]
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
800c9ba: f7ff fe1d bl 800c5f8 <LL_RCC_PLLSAI1_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800c9be: f7f9 ffd5 bl 800696c <HAL_GetTick>
|
|
800c9c2: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
while (LL_RCC_PLLSAI1_IsReady() != 1U)
|
|
800c9c4: e009 b.n 800c9da <RCCEx_PLLSAI1_ConfigNP+0x8a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
800c9c6: f7f9 ffd1 bl 800696c <HAL_GetTick>
|
|
800c9ca: 4602 mov r2, r0
|
|
800c9cc: 68bb ldr r3, [r7, #8]
|
|
800c9ce: 1ad3 subs r3, r2, r3
|
|
800c9d0: 2b02 cmp r3, #2
|
|
800c9d2: d902 bls.n 800c9da <RCCEx_PLLSAI1_ConfigNP+0x8a>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
800c9d4: 2303 movs r3, #3
|
|
800c9d6: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800c9d8: e004 b.n 800c9e4 <RCCEx_PLLSAI1_ConfigNP+0x94>
|
|
while (LL_RCC_PLLSAI1_IsReady() != 1U)
|
|
800c9da: f7ff fe2b bl 800c634 <LL_RCC_PLLSAI1_IsReady>
|
|
800c9de: 4603 mov r3, r0
|
|
800c9e0: 2b01 cmp r3, #1
|
|
800c9e2: d1f0 bne.n 800c9c6 <RCCEx_PLLSAI1_ConfigNP+0x76>
|
|
}
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
800c9e4: 7bfb ldrb r3, [r7, #15]
|
|
800c9e6: 2b00 cmp r3, #0
|
|
800c9e8: d108 bne.n 800c9fc <RCCEx_PLLSAI1_ConfigNP+0xac>
|
|
{
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
|
|
800c9ea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800c9ee: 691a ldr r2, [r3, #16]
|
|
800c9f0: 687b ldr r3, [r7, #4]
|
|
800c9f2: 691b ldr r3, [r3, #16]
|
|
800c9f4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800c9f8: 4313 orrs r3, r2
|
|
800c9fa: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
return status;
|
|
800c9fc: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800c9fe: 4618 mov r0, r3
|
|
800ca00: 3710 adds r7, #16
|
|
800ca02: 46bd mov sp, r7
|
|
800ca04: bd80 pop {r7, pc}
|
|
|
|
0800ca06 <RCCEx_PLLSAI1_ConfigNQ>:
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1)
|
|
{
|
|
800ca06: b580 push {r7, lr}
|
|
800ca08: b084 sub sp, #16
|
|
800ca0a: af00 add r7, sp, #0
|
|
800ca0c: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800ca0e: 2300 movs r3, #0
|
|
800ca10: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
|
|
assert_param(IS_RCC_PLLQ_VALUE(PLLSAI1->PLLQ));
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
|
|
|
|
/* Disable the PLLSAI1 */
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
800ca12: f7ff fe00 bl 800c616 <LL_RCC_PLLSAI1_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800ca16: f7f9 ffa9 bl 800696c <HAL_GetTick>
|
|
800ca1a: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
while (LL_RCC_PLLSAI1_IsReady() != 0U)
|
|
800ca1c: e009 b.n 800ca32 <RCCEx_PLLSAI1_ConfigNQ+0x2c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
800ca1e: f7f9 ffa5 bl 800696c <HAL_GetTick>
|
|
800ca22: 4602 mov r2, r0
|
|
800ca24: 68bb ldr r3, [r7, #8]
|
|
800ca26: 1ad3 subs r3, r2, r3
|
|
800ca28: 2b02 cmp r3, #2
|
|
800ca2a: d902 bls.n 800ca32 <RCCEx_PLLSAI1_ConfigNQ+0x2c>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
800ca2c: 2303 movs r3, #3
|
|
800ca2e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800ca30: e004 b.n 800ca3c <RCCEx_PLLSAI1_ConfigNQ+0x36>
|
|
while (LL_RCC_PLLSAI1_IsReady() != 0U)
|
|
800ca32: f7ff fdff bl 800c634 <LL_RCC_PLLSAI1_IsReady>
|
|
800ca36: 4603 mov r3, r0
|
|
800ca38: 2b00 cmp r3, #0
|
|
800ca3a: d1f0 bne.n 800ca1e <RCCEx_PLLSAI1_ConfigNQ+0x18>
|
|
}
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
800ca3c: 7bfb ldrb r3, [r7, #15]
|
|
800ca3e: 2b00 cmp r3, #0
|
|
800ca40: d137 bne.n 800cab2 <RCCEx_PLLSAI1_ConfigNQ+0xac>
|
|
{
|
|
/* Configure the PLLSAI1 Multiplication factor N */
|
|
__HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
|
|
800ca42: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800ca46: 691b ldr r3, [r3, #16]
|
|
800ca48: f423 42fe bic.w r2, r3, #32512 @ 0x7f00
|
|
800ca4c: 687b ldr r3, [r7, #4]
|
|
800ca4e: 681b ldr r3, [r3, #0]
|
|
800ca50: 021b lsls r3, r3, #8
|
|
800ca52: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800ca56: 4313 orrs r3, r2
|
|
800ca58: 610b str r3, [r1, #16]
|
|
/* Configure the PLLSAI1 Division factor Q */
|
|
__HAL_RCC_PLLSAI1_DIVQ_CONFIG(PLLSAI1->PLLQ);
|
|
800ca5a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800ca5e: 691b ldr r3, [r3, #16]
|
|
800ca60: f023 6260 bic.w r2, r3, #234881024 @ 0xe000000
|
|
800ca64: 687b ldr r3, [r7, #4]
|
|
800ca66: 689b ldr r3, [r3, #8]
|
|
800ca68: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800ca6c: 4313 orrs r3, r2
|
|
800ca6e: 610b str r3, [r1, #16]
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
800ca70: f7ff fdc2 bl 800c5f8 <LL_RCC_PLLSAI1_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800ca74: f7f9 ff7a bl 800696c <HAL_GetTick>
|
|
800ca78: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
while (LL_RCC_PLLSAI1_IsReady() != 1U)
|
|
800ca7a: e009 b.n 800ca90 <RCCEx_PLLSAI1_ConfigNQ+0x8a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
800ca7c: f7f9 ff76 bl 800696c <HAL_GetTick>
|
|
800ca80: 4602 mov r2, r0
|
|
800ca82: 68bb ldr r3, [r7, #8]
|
|
800ca84: 1ad3 subs r3, r2, r3
|
|
800ca86: 2b02 cmp r3, #2
|
|
800ca88: d902 bls.n 800ca90 <RCCEx_PLLSAI1_ConfigNQ+0x8a>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
800ca8a: 2303 movs r3, #3
|
|
800ca8c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800ca8e: e004 b.n 800ca9a <RCCEx_PLLSAI1_ConfigNQ+0x94>
|
|
while (LL_RCC_PLLSAI1_IsReady() != 1U)
|
|
800ca90: f7ff fdd0 bl 800c634 <LL_RCC_PLLSAI1_IsReady>
|
|
800ca94: 4603 mov r3, r0
|
|
800ca96: 2b01 cmp r3, #1
|
|
800ca98: d1f0 bne.n 800ca7c <RCCEx_PLLSAI1_ConfigNQ+0x76>
|
|
}
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
800ca9a: 7bfb ldrb r3, [r7, #15]
|
|
800ca9c: 2b00 cmp r3, #0
|
|
800ca9e: d108 bne.n 800cab2 <RCCEx_PLLSAI1_ConfigNQ+0xac>
|
|
{
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
|
|
800caa0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800caa4: 691a ldr r2, [r3, #16]
|
|
800caa6: 687b ldr r3, [r7, #4]
|
|
800caa8: 691b ldr r3, [r3, #16]
|
|
800caaa: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800caae: 4313 orrs r3, r2
|
|
800cab0: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
return status;
|
|
800cab2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800cab4: 4618 mov r0, r3
|
|
800cab6: 3710 adds r7, #16
|
|
800cab8: 46bd mov sp, r7
|
|
800caba: bd80 pop {r7, pc}
|
|
|
|
0800cabc <RCCEx_PLLSAI1_ConfigNR>:
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1)
|
|
{
|
|
800cabc: b580 push {r7, lr}
|
|
800cabe: b084 sub sp, #16
|
|
800cac0: af00 add r7, sp, #0
|
|
800cac2: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800cac4: 2300 movs r3, #0
|
|
800cac6: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
|
|
assert_param(IS_RCC_PLLR_VALUE(PLLSAI1->PLLR));
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
|
|
|
|
/* Disable the PLLSAI1 */
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
800cac8: f7ff fda5 bl 800c616 <LL_RCC_PLLSAI1_Disable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800cacc: f7f9 ff4e bl 800696c <HAL_GetTick>
|
|
800cad0: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
while (LL_RCC_PLLSAI1_IsReady() != 0U)
|
|
800cad2: e009 b.n 800cae8 <RCCEx_PLLSAI1_ConfigNR+0x2c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
800cad4: f7f9 ff4a bl 800696c <HAL_GetTick>
|
|
800cad8: 4602 mov r2, r0
|
|
800cada: 68bb ldr r3, [r7, #8]
|
|
800cadc: 1ad3 subs r3, r2, r3
|
|
800cade: 2b02 cmp r3, #2
|
|
800cae0: d902 bls.n 800cae8 <RCCEx_PLLSAI1_ConfigNR+0x2c>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
800cae2: 2303 movs r3, #3
|
|
800cae4: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cae6: e004 b.n 800caf2 <RCCEx_PLLSAI1_ConfigNR+0x36>
|
|
while (LL_RCC_PLLSAI1_IsReady() != 0U)
|
|
800cae8: f7ff fda4 bl 800c634 <LL_RCC_PLLSAI1_IsReady>
|
|
800caec: 4603 mov r3, r0
|
|
800caee: 2b00 cmp r3, #0
|
|
800caf0: d1f0 bne.n 800cad4 <RCCEx_PLLSAI1_ConfigNR+0x18>
|
|
}
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
800caf2: 7bfb ldrb r3, [r7, #15]
|
|
800caf4: 2b00 cmp r3, #0
|
|
800caf6: d137 bne.n 800cb68 <RCCEx_PLLSAI1_ConfigNR+0xac>
|
|
{
|
|
/* Configure the PLLSAI1 Multiplication factor N */
|
|
__HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
|
|
800caf8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800cafc: 691b ldr r3, [r3, #16]
|
|
800cafe: f423 42fe bic.w r2, r3, #32512 @ 0x7f00
|
|
800cb02: 687b ldr r3, [r7, #4]
|
|
800cb04: 681b ldr r3, [r3, #0]
|
|
800cb06: 021b lsls r3, r3, #8
|
|
800cb08: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800cb0c: 4313 orrs r3, r2
|
|
800cb0e: 610b str r3, [r1, #16]
|
|
/* Configure the PLLSAI1 Division factor R */
|
|
__HAL_RCC_PLLSAI1_DIVR_CONFIG(PLLSAI1->PLLR);
|
|
800cb10: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800cb14: 691b ldr r3, [r3, #16]
|
|
800cb16: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000
|
|
800cb1a: 687b ldr r3, [r7, #4]
|
|
800cb1c: 68db ldr r3, [r3, #12]
|
|
800cb1e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800cb22: 4313 orrs r3, r2
|
|
800cb24: 610b str r3, [r1, #16]
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
800cb26: f7ff fd67 bl 800c5f8 <LL_RCC_PLLSAI1_Enable>
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800cb2a: f7f9 ff1f bl 800696c <HAL_GetTick>
|
|
800cb2e: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
while (LL_RCC_PLLSAI1_IsReady() != 1U)
|
|
800cb30: e009 b.n 800cb46 <RCCEx_PLLSAI1_ConfigNR+0x8a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
800cb32: f7f9 ff1b bl 800696c <HAL_GetTick>
|
|
800cb36: 4602 mov r2, r0
|
|
800cb38: 68bb ldr r3, [r7, #8]
|
|
800cb3a: 1ad3 subs r3, r2, r3
|
|
800cb3c: 2b02 cmp r3, #2
|
|
800cb3e: d902 bls.n 800cb46 <RCCEx_PLLSAI1_ConfigNR+0x8a>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
800cb40: 2303 movs r3, #3
|
|
800cb42: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cb44: e004 b.n 800cb50 <RCCEx_PLLSAI1_ConfigNR+0x94>
|
|
while (LL_RCC_PLLSAI1_IsReady() != 1U)
|
|
800cb46: f7ff fd75 bl 800c634 <LL_RCC_PLLSAI1_IsReady>
|
|
800cb4a: 4603 mov r3, r0
|
|
800cb4c: 2b01 cmp r3, #1
|
|
800cb4e: d1f0 bne.n 800cb32 <RCCEx_PLLSAI1_ConfigNR+0x76>
|
|
}
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
800cb50: 7bfb ldrb r3, [r7, #15]
|
|
800cb52: 2b00 cmp r3, #0
|
|
800cb54: d108 bne.n 800cb68 <RCCEx_PLLSAI1_ConfigNR+0xac>
|
|
{
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
|
|
800cb56: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
800cb5a: 691a ldr r2, [r3, #16]
|
|
800cb5c: 687b ldr r3, [r7, #4]
|
|
800cb5e: 691b ldr r3, [r3, #16]
|
|
800cb60: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
800cb64: 4313 orrs r3, r2
|
|
800cb66: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
|
|
return status;
|
|
800cb68: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800cb6a: 4618 mov r0, r3
|
|
800cb6c: 3710 adds r7, #16
|
|
800cb6e: 46bd mov sp, r7
|
|
800cb70: bd80 pop {r7, pc}
|
|
|
|
0800cb72 <HAL_RTC_Init>:
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
* the configuration information for RTC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
800cb72: b580 push {r7, lr}
|
|
800cb74: b084 sub sp, #16
|
|
800cb76: af00 add r7, sp, #0
|
|
800cb78: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check RTC handler validity */
|
|
if (hrtc == NULL)
|
|
800cb7a: 687b ldr r3, [r7, #4]
|
|
800cb7c: 2b00 cmp r3, #0
|
|
800cb7e: d101 bne.n 800cb84 <HAL_RTC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800cb80: 2301 movs r3, #1
|
|
800cb82: e07a b.n 800cc7a <HAL_RTC_Init+0x108>
|
|
{
|
|
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
|
|
}
|
|
}
|
|
#else /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
if (hrtc->State == HAL_RTC_STATE_RESET)
|
|
800cb84: 687b ldr r3, [r7, #4]
|
|
800cb86: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
|
|
800cb8a: b2db uxtb r3, r3
|
|
800cb8c: 2b00 cmp r3, #0
|
|
800cb8e: d106 bne.n 800cb9e <HAL_RTC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hrtc->Lock = HAL_UNLOCKED;
|
|
800cb90: 687b ldr r3, [r7, #4]
|
|
800cb92: 2200 movs r2, #0
|
|
800cb94: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
/* Initialize RTC MSP */
|
|
HAL_RTC_MspInit(hrtc);
|
|
800cb98: 6878 ldr r0, [r7, #4]
|
|
800cb9a: f7f9 fb25 bl 80061e8 <HAL_RTC_MspInit>
|
|
}
|
|
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
800cb9e: 687b ldr r3, [r7, #4]
|
|
800cba0: 2202 movs r2, #2
|
|
800cba2: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Check whether the calendar needs to be initialized */
|
|
if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
|
|
800cba6: 687b ldr r3, [r7, #4]
|
|
800cba8: 681b ldr r3, [r3, #0]
|
|
800cbaa: 68db ldr r3, [r3, #12]
|
|
800cbac: f003 0310 and.w r3, r3, #16
|
|
800cbb0: 2b10 cmp r3, #16
|
|
800cbb2: d058 beq.n 800cc66 <HAL_RTC_Init+0xf4>
|
|
{
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800cbb4: 687b ldr r3, [r7, #4]
|
|
800cbb6: 681b ldr r3, [r3, #0]
|
|
800cbb8: 22ca movs r2, #202 @ 0xca
|
|
800cbba: 625a str r2, [r3, #36] @ 0x24
|
|
800cbbc: 687b ldr r3, [r7, #4]
|
|
800cbbe: 681b ldr r3, [r3, #0]
|
|
800cbc0: 2253 movs r2, #83 @ 0x53
|
|
800cbc2: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Enter Initialization mode */
|
|
status = RTC_EnterInitMode(hrtc);
|
|
800cbc4: 6878 ldr r0, [r7, #4]
|
|
800cbc6: f000 f883 bl 800ccd0 <RTC_EnterInitMode>
|
|
800cbca: 4603 mov r3, r0
|
|
800cbcc: 73fb strb r3, [r7, #15]
|
|
|
|
if (status == HAL_OK)
|
|
800cbce: 7bfb ldrb r3, [r7, #15]
|
|
800cbd0: 2b00 cmp r3, #0
|
|
800cbd2: d12c bne.n 800cc2e <HAL_RTC_Init+0xbc>
|
|
{
|
|
/* Clear RTC_CR FMT, OSEL and POL Bits */
|
|
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
|
|
800cbd4: 687b ldr r3, [r7, #4]
|
|
800cbd6: 681b ldr r3, [r3, #0]
|
|
800cbd8: 689b ldr r3, [r3, #8]
|
|
800cbda: 687a ldr r2, [r7, #4]
|
|
800cbdc: 6812 ldr r2, [r2, #0]
|
|
800cbde: f423 03e0 bic.w r3, r3, #7340032 @ 0x700000
|
|
800cbe2: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800cbe6: 6093 str r3, [r2, #8]
|
|
/* Set RTC_CR register */
|
|
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
|
|
800cbe8: 687b ldr r3, [r7, #4]
|
|
800cbea: 681b ldr r3, [r3, #0]
|
|
800cbec: 6899 ldr r1, [r3, #8]
|
|
800cbee: 687b ldr r3, [r7, #4]
|
|
800cbf0: 685a ldr r2, [r3, #4]
|
|
800cbf2: 687b ldr r3, [r7, #4]
|
|
800cbf4: 691b ldr r3, [r3, #16]
|
|
800cbf6: 431a orrs r2, r3
|
|
800cbf8: 687b ldr r3, [r7, #4]
|
|
800cbfa: 699b ldr r3, [r3, #24]
|
|
800cbfc: 431a orrs r2, r3
|
|
800cbfe: 687b ldr r3, [r7, #4]
|
|
800cc00: 681b ldr r3, [r3, #0]
|
|
800cc02: 430a orrs r2, r1
|
|
800cc04: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the RTC PRER */
|
|
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
|
|
800cc06: 687b ldr r3, [r7, #4]
|
|
800cc08: 681b ldr r3, [r3, #0]
|
|
800cc0a: 687a ldr r2, [r7, #4]
|
|
800cc0c: 68d2 ldr r2, [r2, #12]
|
|
800cc0e: 611a str r2, [r3, #16]
|
|
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
|
|
800cc10: 687b ldr r3, [r7, #4]
|
|
800cc12: 681b ldr r3, [r3, #0]
|
|
800cc14: 6919 ldr r1, [r3, #16]
|
|
800cc16: 687b ldr r3, [r7, #4]
|
|
800cc18: 689b ldr r3, [r3, #8]
|
|
800cc1a: 041a lsls r2, r3, #16
|
|
800cc1c: 687b ldr r3, [r7, #4]
|
|
800cc1e: 681b ldr r3, [r3, #0]
|
|
800cc20: 430a orrs r2, r1
|
|
800cc22: 611a str r2, [r3, #16]
|
|
|
|
/* Exit Initialization mode */
|
|
status = RTC_ExitInitMode(hrtc);
|
|
800cc24: 6878 ldr r0, [r7, #4]
|
|
800cc26: f000 f88b bl 800cd40 <RTC_ExitInitMode>
|
|
800cc2a: 4603 mov r3, r0
|
|
800cc2c: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
800cc2e: 7bfb ldrb r3, [r7, #15]
|
|
800cc30: 2b00 cmp r3, #0
|
|
800cc32: d113 bne.n 800cc5c <HAL_RTC_Init+0xea>
|
|
{
|
|
#if defined(RTC_OR_ALARMOUTTYPE)
|
|
hrtc->Instance->OR &= (uint32_t)~(RTC_OUTPUT_TYPE_PUSHPULL | RTC_OUTPUT_REMAP_POS1);
|
|
800cc34: 687b ldr r3, [r7, #4]
|
|
800cc36: 681b ldr r3, [r3, #0]
|
|
800cc38: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
800cc3a: 687b ldr r3, [r7, #4]
|
|
800cc3c: 681b ldr r3, [r3, #0]
|
|
800cc3e: f022 0203 bic.w r2, r2, #3
|
|
800cc42: 64da str r2, [r3, #76] @ 0x4c
|
|
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
|
|
800cc44: 687b ldr r3, [r7, #4]
|
|
800cc46: 681b ldr r3, [r3, #0]
|
|
800cc48: 6cd9 ldr r1, [r3, #76] @ 0x4c
|
|
800cc4a: 687b ldr r3, [r7, #4]
|
|
800cc4c: 69da ldr r2, [r3, #28]
|
|
800cc4e: 687b ldr r3, [r7, #4]
|
|
800cc50: 695b ldr r3, [r3, #20]
|
|
800cc52: 431a orrs r2, r3
|
|
800cc54: 687b ldr r3, [r7, #4]
|
|
800cc56: 681b ldr r3, [r3, #0]
|
|
800cc58: 430a orrs r2, r1
|
|
800cc5a: 64da str r2, [r3, #76] @ 0x4c
|
|
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutRemap);
|
|
#endif /* RTC_OR_ALARMOUTTYPE */
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800cc5c: 687b ldr r3, [r7, #4]
|
|
800cc5e: 681b ldr r3, [r3, #0]
|
|
800cc60: 22ff movs r2, #255 @ 0xff
|
|
800cc62: 625a str r2, [r3, #36] @ 0x24
|
|
800cc64: e001 b.n 800cc6a <HAL_RTC_Init+0xf8>
|
|
}
|
|
else
|
|
{
|
|
/* The calendar is already initialized */
|
|
status = HAL_OK;
|
|
800cc66: 2300 movs r3, #0
|
|
800cc68: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if (status == HAL_OK)
|
|
800cc6a: 7bfb ldrb r3, [r7, #15]
|
|
800cc6c: 2b00 cmp r3, #0
|
|
800cc6e: d103 bne.n 800cc78 <HAL_RTC_Init+0x106>
|
|
{
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
800cc70: 687b ldr r3, [r7, #4]
|
|
800cc72: 2201 movs r2, #1
|
|
800cc74: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
}
|
|
|
|
return status;
|
|
800cc78: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800cc7a: 4618 mov r0, r3
|
|
800cc7c: 3710 adds r7, #16
|
|
800cc7e: 46bd mov sp, r7
|
|
800cc80: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800cc84 <HAL_RTC_WaitForSynchro>:
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
* the configuration information for RTC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
800cc84: b580 push {r7, lr}
|
|
800cc86: b084 sub sp, #16
|
|
800cc88: af00 add r7, sp, #0
|
|
800cc8a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
800cc8c: 2300 movs r3, #0
|
|
800cc8e: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
|
|
hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK));
|
|
800cc90: 687b ldr r3, [r7, #4]
|
|
800cc92: 681b ldr r3, [r3, #0]
|
|
800cc94: 4a0d ldr r2, [pc, #52] @ (800cccc <HAL_RTC_WaitForSynchro+0x48>)
|
|
800cc96: 60da str r2, [r3, #12]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800cc98: f7f9 fe68 bl 800696c <HAL_GetTick>
|
|
800cc9c: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait the registers to be synchronised */
|
|
while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
|
|
800cc9e: e009 b.n 800ccb4 <HAL_RTC_WaitForSynchro+0x30>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
800cca0: f7f9 fe64 bl 800696c <HAL_GetTick>
|
|
800cca4: 4602 mov r2, r0
|
|
800cca6: 68fb ldr r3, [r7, #12]
|
|
800cca8: 1ad3 subs r3, r2, r3
|
|
800ccaa: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
800ccae: d901 bls.n 800ccb4 <HAL_RTC_WaitForSynchro+0x30>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800ccb0: 2303 movs r3, #3
|
|
800ccb2: e007 b.n 800ccc4 <HAL_RTC_WaitForSynchro+0x40>
|
|
while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
|
|
800ccb4: 687b ldr r3, [r7, #4]
|
|
800ccb6: 681b ldr r3, [r3, #0]
|
|
800ccb8: 68db ldr r3, [r3, #12]
|
|
800ccba: f003 0320 and.w r3, r3, #32
|
|
800ccbe: 2b00 cmp r3, #0
|
|
800ccc0: d0ee beq.n 800cca0 <HAL_RTC_WaitForSynchro+0x1c>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800ccc2: 2300 movs r3, #0
|
|
}
|
|
800ccc4: 4618 mov r0, r3
|
|
800ccc6: 3710 adds r7, #16
|
|
800ccc8: 46bd mov sp, r7
|
|
800ccca: bd80 pop {r7, pc}
|
|
800cccc: 0001ff5f .word 0x0001ff5f
|
|
|
|
0800ccd0 <RTC_EnterInitMode>:
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
* the configuration information for RTC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
800ccd0: b580 push {r7, lr}
|
|
800ccd2: b084 sub sp, #16
|
|
800ccd4: af00 add r7, sp, #0
|
|
800ccd6: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
800ccd8: 2300 movs r3, #0
|
|
800ccda: 60bb str r3, [r7, #8]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800ccdc: 2300 movs r3, #0
|
|
800ccde: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check that Initialization mode is not already set */
|
|
if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U)
|
|
800cce0: 687b ldr r3, [r7, #4]
|
|
800cce2: 681b ldr r3, [r3, #0]
|
|
800cce4: 68db ldr r3, [r3, #12]
|
|
800cce6: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800ccea: 2b00 cmp r3, #0
|
|
800ccec: d123 bne.n 800cd36 <RTC_EnterInitMode+0x66>
|
|
{
|
|
/* Set INIT bit to enter Initialization mode */
|
|
SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
|
|
800ccee: 687b ldr r3, [r7, #4]
|
|
800ccf0: 681b ldr r3, [r3, #0]
|
|
800ccf2: 68da ldr r2, [r3, #12]
|
|
800ccf4: 687b ldr r3, [r7, #4]
|
|
800ccf6: 681b ldr r3, [r3, #0]
|
|
800ccf8: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
800ccfc: 60da str r2, [r3, #12]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800ccfe: f7f9 fe35 bl 800696c <HAL_GetTick>
|
|
800cd02: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till RTC is in INIT state and if timeout is reached exit */
|
|
while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR))
|
|
800cd04: e00d b.n 800cd22 <RTC_EnterInitMode+0x52>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
800cd06: f7f9 fe31 bl 800696c <HAL_GetTick>
|
|
800cd0a: 4602 mov r2, r0
|
|
800cd0c: 68bb ldr r3, [r7, #8]
|
|
800cd0e: 1ad3 subs r3, r2, r3
|
|
800cd10: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
800cd14: d905 bls.n 800cd22 <RTC_EnterInitMode+0x52>
|
|
{
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
800cd16: 687b ldr r3, [r7, #4]
|
|
800cd18: 2204 movs r2, #4
|
|
800cd1a: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
status = HAL_ERROR;
|
|
800cd1e: 2301 movs r3, #1
|
|
800cd20: 73fb strb r3, [r7, #15]
|
|
while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR))
|
|
800cd22: 687b ldr r3, [r7, #4]
|
|
800cd24: 681b ldr r3, [r3, #0]
|
|
800cd26: 68db ldr r3, [r3, #12]
|
|
800cd28: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800cd2c: 2b00 cmp r3, #0
|
|
800cd2e: d102 bne.n 800cd36 <RTC_EnterInitMode+0x66>
|
|
800cd30: 7bfb ldrb r3, [r7, #15]
|
|
800cd32: 2b01 cmp r3, #1
|
|
800cd34: d1e7 bne.n 800cd06 <RTC_EnterInitMode+0x36>
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
800cd36: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800cd38: 4618 mov r0, r3
|
|
800cd3a: 3710 adds r7, #16
|
|
800cd3c: 46bd mov sp, r7
|
|
800cd3e: bd80 pop {r7, pc}
|
|
|
|
0800cd40 <RTC_ExitInitMode>:
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
* the configuration information for RTC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
800cd40: b580 push {r7, lr}
|
|
800cd42: b084 sub sp, #16
|
|
800cd44: af00 add r7, sp, #0
|
|
800cd46: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800cd48: 2300 movs r3, #0
|
|
800cd4a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Clear INIT bit to exit Initialization mode */
|
|
CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
|
|
800cd4c: 687b ldr r3, [r7, #4]
|
|
800cd4e: 681b ldr r3, [r3, #0]
|
|
800cd50: 68da ldr r2, [r3, #12]
|
|
800cd52: 687b ldr r3, [r7, #4]
|
|
800cd54: 681b ldr r3, [r3, #0]
|
|
800cd56: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
800cd5a: 60da str r2, [r3, #12]
|
|
|
|
/* If CR_BYPSHAD bit = 0, wait for synchro */
|
|
if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U)
|
|
800cd5c: 687b ldr r3, [r7, #4]
|
|
800cd5e: 681b ldr r3, [r3, #0]
|
|
800cd60: 689b ldr r3, [r3, #8]
|
|
800cd62: f003 0320 and.w r3, r3, #32
|
|
800cd66: 2b00 cmp r3, #0
|
|
800cd68: d10b bne.n 800cd82 <RTC_ExitInitMode+0x42>
|
|
{
|
|
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
|
800cd6a: 6878 ldr r0, [r7, #4]
|
|
800cd6c: f7ff ff8a bl 800cc84 <HAL_RTC_WaitForSynchro>
|
|
800cd70: 4603 mov r3, r0
|
|
800cd72: 2b00 cmp r3, #0
|
|
800cd74: d005 beq.n 800cd82 <RTC_ExitInitMode+0x42>
|
|
{
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
800cd76: 687b ldr r3, [r7, #4]
|
|
800cd78: 2204 movs r2, #4
|
|
800cd7a: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
status = HAL_ERROR;
|
|
800cd7e: 2301 movs r3, #1
|
|
800cd80: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
|
|
return status;
|
|
800cd82: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800cd84: 4618 mov r0, r3
|
|
800cd86: 3710 adds r7, #16
|
|
800cd88: 46bd mov sp, r7
|
|
800cd8a: bd80 pop {r7, pc}
|
|
|
|
0800cd8c <HAL_RTCEx_SetWakeUpTimer_IT>:
|
|
* @param WakeUpCounter Wakeup counter
|
|
* @param WakeUpClock Wakeup clock
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
|
|
{
|
|
800cd8c: b480 push {r7}
|
|
800cd8e: b087 sub sp, #28
|
|
800cd90: af00 add r7, sp, #0
|
|
800cd92: 60f8 str r0, [r7, #12]
|
|
800cd94: 60b9 str r1, [r7, #8]
|
|
800cd96: 607a str r2, [r7, #4]
|
|
__IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
|
|
800cd98: 4b5f ldr r3, [pc, #380] @ (800cf18 <HAL_RTCEx_SetWakeUpTimer_IT+0x18c>)
|
|
800cd9a: 681b ldr r3, [r3, #0]
|
|
800cd9c: 4a5f ldr r2, [pc, #380] @ (800cf1c <HAL_RTCEx_SetWakeUpTimer_IT+0x190>)
|
|
800cd9e: fba2 2303 umull r2, r3, r2, r3
|
|
800cda2: 0adb lsrs r3, r3, #11
|
|
800cda4: f44f 727a mov.w r2, #1000 @ 0x3e8
|
|
800cda8: fb02 f303 mul.w r3, r2, r3
|
|
800cdac: 617b str r3, [r7, #20]
|
|
/* Check the parameters */
|
|
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
|
|
assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
800cdae: 68fb ldr r3, [r7, #12]
|
|
800cdb0: f893 3020 ldrb.w r3, [r3, #32]
|
|
800cdb4: 2b01 cmp r3, #1
|
|
800cdb6: d101 bne.n 800cdbc <HAL_RTCEx_SetWakeUpTimer_IT+0x30>
|
|
800cdb8: 2302 movs r3, #2
|
|
800cdba: e0a7 b.n 800cf0c <HAL_RTCEx_SetWakeUpTimer_IT+0x180>
|
|
800cdbc: 68fb ldr r3, [r7, #12]
|
|
800cdbe: 2201 movs r2, #1
|
|
800cdc0: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
800cdc4: 68fb ldr r3, [r7, #12]
|
|
800cdc6: 2202 movs r2, #2
|
|
800cdc8: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800cdcc: 68fb ldr r3, [r7, #12]
|
|
800cdce: 681b ldr r3, [r3, #0]
|
|
800cdd0: 22ca movs r2, #202 @ 0xca
|
|
800cdd2: 625a str r2, [r3, #36] @ 0x24
|
|
800cdd4: 68fb ldr r3, [r7, #12]
|
|
800cdd6: 681b ldr r3, [r3, #0]
|
|
800cdd8: 2253 movs r2, #83 @ 0x53
|
|
800cdda: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Check RTC WUTWF flag is reset only when wakeup timer enabled */
|
|
if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
|
|
800cddc: 68fb ldr r3, [r7, #12]
|
|
800cdde: 681b ldr r3, [r3, #0]
|
|
800cde0: 689b ldr r3, [r3, #8]
|
|
800cde2: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800cde6: 2b00 cmp r3, #0
|
|
800cde8: d01a beq.n 800ce20 <HAL_RTCEx_SetWakeUpTimer_IT+0x94>
|
|
{
|
|
/* Wait till RTC WUTWF flag is reset and if timeout is reached exit */
|
|
do
|
|
{
|
|
count = count - 1U;
|
|
800cdea: 697b ldr r3, [r7, #20]
|
|
800cdec: 3b01 subs r3, #1
|
|
800cdee: 617b str r3, [r7, #20]
|
|
if (count == 0U)
|
|
800cdf0: 697b ldr r3, [r7, #20]
|
|
800cdf2: 2b00 cmp r3, #0
|
|
800cdf4: d10d bne.n 800ce12 <HAL_RTCEx_SetWakeUpTimer_IT+0x86>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800cdf6: 68fb ldr r3, [r7, #12]
|
|
800cdf8: 681b ldr r3, [r3, #0]
|
|
800cdfa: 22ff movs r2, #255 @ 0xff
|
|
800cdfc: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
800cdfe: 68fb ldr r3, [r7, #12]
|
|
800ce00: 2203 movs r2, #3
|
|
800ce02: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800ce06: 68fb ldr r3, [r7, #12]
|
|
800ce08: 2200 movs r2, #0
|
|
800ce0a: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_TIMEOUT;
|
|
800ce0e: 2303 movs r3, #3
|
|
800ce10: e07c b.n 800cf0c <HAL_RTCEx_SetWakeUpTimer_IT+0x180>
|
|
}
|
|
} while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U);
|
|
800ce12: 68fb ldr r3, [r7, #12]
|
|
800ce14: 681b ldr r3, [r3, #0]
|
|
800ce16: 68db ldr r3, [r3, #12]
|
|
800ce18: f003 0304 and.w r3, r3, #4
|
|
800ce1c: 2b00 cmp r3, #0
|
|
800ce1e: d1e4 bne.n 800cdea <HAL_RTCEx_SetWakeUpTimer_IT+0x5e>
|
|
}
|
|
|
|
/* Disable the Wakeup timer */
|
|
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
|
|
800ce20: 68fb ldr r3, [r7, #12]
|
|
800ce22: 681b ldr r3, [r3, #0]
|
|
800ce24: 689a ldr r2, [r3, #8]
|
|
800ce26: 68fb ldr r3, [r7, #12]
|
|
800ce28: 681b ldr r3, [r3, #0]
|
|
800ce2a: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
800ce2e: 609a str r2, [r3, #8]
|
|
|
|
/* Clear the Wakeup flag */
|
|
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
|
|
800ce30: 68fb ldr r3, [r7, #12]
|
|
800ce32: 681b ldr r3, [r3, #0]
|
|
800ce34: 68db ldr r3, [r3, #12]
|
|
800ce36: b2da uxtb r2, r3
|
|
800ce38: 68fb ldr r3, [r7, #12]
|
|
800ce3a: 681b ldr r3, [r3, #0]
|
|
800ce3c: f462 6290 orn r2, r2, #1152 @ 0x480
|
|
800ce40: 60da str r2, [r3, #12]
|
|
|
|
/* Reload the counter */
|
|
count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
|
|
800ce42: 4b35 ldr r3, [pc, #212] @ (800cf18 <HAL_RTCEx_SetWakeUpTimer_IT+0x18c>)
|
|
800ce44: 681b ldr r3, [r3, #0]
|
|
800ce46: 4a35 ldr r2, [pc, #212] @ (800cf1c <HAL_RTCEx_SetWakeUpTimer_IT+0x190>)
|
|
800ce48: fba2 2303 umull r2, r3, r2, r3
|
|
800ce4c: 0adb lsrs r3, r3, #11
|
|
800ce4e: f44f 727a mov.w r2, #1000 @ 0x3e8
|
|
800ce52: fb02 f303 mul.w r3, r2, r3
|
|
800ce56: 617b str r3, [r7, #20]
|
|
|
|
/* Wait till RTC WUTWF flag is set and if timeout is reached exit */
|
|
do
|
|
{
|
|
count = count - 1U;
|
|
800ce58: 697b ldr r3, [r7, #20]
|
|
800ce5a: 3b01 subs r3, #1
|
|
800ce5c: 617b str r3, [r7, #20]
|
|
if (count == 0U)
|
|
800ce5e: 697b ldr r3, [r7, #20]
|
|
800ce60: 2b00 cmp r3, #0
|
|
800ce62: d10d bne.n 800ce80 <HAL_RTCEx_SetWakeUpTimer_IT+0xf4>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800ce64: 68fb ldr r3, [r7, #12]
|
|
800ce66: 681b ldr r3, [r3, #0]
|
|
800ce68: 22ff movs r2, #255 @ 0xff
|
|
800ce6a: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
800ce6c: 68fb ldr r3, [r7, #12]
|
|
800ce6e: 2203 movs r2, #3
|
|
800ce70: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800ce74: 68fb ldr r3, [r7, #12]
|
|
800ce76: 2200 movs r2, #0
|
|
800ce78: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_TIMEOUT;
|
|
800ce7c: 2303 movs r3, #3
|
|
800ce7e: e045 b.n 800cf0c <HAL_RTCEx_SetWakeUpTimer_IT+0x180>
|
|
}
|
|
} while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U);
|
|
800ce80: 68fb ldr r3, [r7, #12]
|
|
800ce82: 681b ldr r3, [r3, #0]
|
|
800ce84: 68db ldr r3, [r3, #12]
|
|
800ce86: f003 0304 and.w r3, r3, #4
|
|
800ce8a: 2b00 cmp r3, #0
|
|
800ce8c: d0e4 beq.n 800ce58 <HAL_RTCEx_SetWakeUpTimer_IT+0xcc>
|
|
|
|
/* Clear the Wakeup Timer clock source bits in CR register */
|
|
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
|
|
800ce8e: 68fb ldr r3, [r7, #12]
|
|
800ce90: 681b ldr r3, [r3, #0]
|
|
800ce92: 689a ldr r2, [r3, #8]
|
|
800ce94: 68fb ldr r3, [r7, #12]
|
|
800ce96: 681b ldr r3, [r3, #0]
|
|
800ce98: f022 0207 bic.w r2, r2, #7
|
|
800ce9c: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the clock source */
|
|
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
|
|
800ce9e: 68fb ldr r3, [r7, #12]
|
|
800cea0: 681b ldr r3, [r3, #0]
|
|
800cea2: 6899 ldr r1, [r3, #8]
|
|
800cea4: 68fb ldr r3, [r7, #12]
|
|
800cea6: 681b ldr r3, [r3, #0]
|
|
800cea8: 687a ldr r2, [r7, #4]
|
|
800ceaa: 430a orrs r2, r1
|
|
800ceac: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the Wakeup Timer counter */
|
|
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
|
|
800ceae: 68fb ldr r3, [r7, #12]
|
|
800ceb0: 681b ldr r3, [r3, #0]
|
|
800ceb2: 68ba ldr r2, [r7, #8]
|
|
800ceb4: 615a str r2, [r3, #20]
|
|
|
|
/* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
|
|
800ceb6: 4b1a ldr r3, [pc, #104] @ (800cf20 <HAL_RTCEx_SetWakeUpTimer_IT+0x194>)
|
|
800ceb8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800cebc: 4a18 ldr r2, [pc, #96] @ (800cf20 <HAL_RTCEx_SetWakeUpTimer_IT+0x194>)
|
|
800cebe: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
800cec2: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
|
|
800cec6: 4b16 ldr r3, [pc, #88] @ (800cf20 <HAL_RTCEx_SetWakeUpTimer_IT+0x194>)
|
|
800cec8: 681b ldr r3, [r3, #0]
|
|
800ceca: 4a15 ldr r2, [pc, #84] @ (800cf20 <HAL_RTCEx_SetWakeUpTimer_IT+0x194>)
|
|
800cecc: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
800ced0: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the interrupt in the RTC_CR register */
|
|
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
|
|
800ced2: 68fb ldr r3, [r7, #12]
|
|
800ced4: 681b ldr r3, [r3, #0]
|
|
800ced6: 689a ldr r2, [r3, #8]
|
|
800ced8: 68fb ldr r3, [r7, #12]
|
|
800ceda: 681b ldr r3, [r3, #0]
|
|
800cedc: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
800cee0: 609a str r2, [r3, #8]
|
|
|
|
/* Enable the Wakeup Timer */
|
|
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
|
|
800cee2: 68fb ldr r3, [r7, #12]
|
|
800cee4: 681b ldr r3, [r3, #0]
|
|
800cee6: 689a ldr r2, [r3, #8]
|
|
800cee8: 68fb ldr r3, [r7, #12]
|
|
800ceea: 681b ldr r3, [r3, #0]
|
|
800ceec: f442 6280 orr.w r2, r2, #1024 @ 0x400
|
|
800cef0: 609a str r2, [r3, #8]
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800cef2: 68fb ldr r3, [r7, #12]
|
|
800cef4: 681b ldr r3, [r3, #0]
|
|
800cef6: 22ff movs r2, #255 @ 0xff
|
|
800cef8: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
800cefa: 68fb ldr r3, [r7, #12]
|
|
800cefc: 2201 movs r2, #1
|
|
800cefe: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800cf02: 68fb ldr r3, [r7, #12]
|
|
800cf04: 2200 movs r2, #0
|
|
800cf06: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_OK;
|
|
800cf0a: 2300 movs r3, #0
|
|
}
|
|
800cf0c: 4618 mov r0, r3
|
|
800cf0e: 371c adds r7, #28
|
|
800cf10: 46bd mov sp, r7
|
|
800cf12: f85d 7b04 ldr.w r7, [sp], #4
|
|
800cf16: 4770 bx lr
|
|
800cf18: 2000000c .word 0x2000000c
|
|
800cf1c: 10624dd3 .word 0x10624dd3
|
|
800cf20: 58000800 .word 0x58000800
|
|
|
|
0800cf24 <HAL_SPI_Init>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800cf24: b580 push {r7, lr}
|
|
800cf26: b084 sub sp, #16
|
|
800cf28: af00 add r7, sp, #0
|
|
800cf2a: 6078 str r0, [r7, #4]
|
|
uint32_t frxth;
|
|
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
800cf2c: 687b ldr r3, [r7, #4]
|
|
800cf2e: 2b00 cmp r3, #0
|
|
800cf30: d101 bne.n 800cf36 <HAL_SPI_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800cf32: 2301 movs r3, #1
|
|
800cf34: e095 b.n 800d062 <HAL_SPI_Init+0x13e>
|
|
assert_param(IS_SPI_NSS(hspi->Init.NSS));
|
|
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
|
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
|
|
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
|
|
800cf36: 687b ldr r3, [r7, #4]
|
|
800cf38: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800cf3a: 2b00 cmp r3, #0
|
|
800cf3c: d108 bne.n 800cf50 <HAL_SPI_Init+0x2c>
|
|
{
|
|
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
|
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
|
|
|
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
|
800cf3e: 687b ldr r3, [r7, #4]
|
|
800cf40: 685b ldr r3, [r3, #4]
|
|
800cf42: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800cf46: d009 beq.n 800cf5c <HAL_SPI_Init+0x38>
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
}
|
|
else
|
|
{
|
|
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
|
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
800cf48: 687b ldr r3, [r7, #4]
|
|
800cf4a: 2200 movs r2, #0
|
|
800cf4c: 61da str r2, [r3, #28]
|
|
800cf4e: e005 b.n 800cf5c <HAL_SPI_Init+0x38>
|
|
else
|
|
{
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
|
|
/* Force polarity and phase to TI protocaol requirements */
|
|
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
800cf50: 687b ldr r3, [r7, #4]
|
|
800cf52: 2200 movs r2, #0
|
|
800cf54: 611a str r2, [r3, #16]
|
|
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
800cf56: 687b ldr r3, [r7, #4]
|
|
800cf58: 2200 movs r2, #0
|
|
800cf5a: 615a str r2, [r3, #20]
|
|
{
|
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
|
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
|
|
}
|
|
#else
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
800cf5c: 687b ldr r3, [r7, #4]
|
|
800cf5e: 2200 movs r2, #0
|
|
800cf60: 629a str r2, [r3, #40] @ 0x28
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->State == HAL_SPI_STATE_RESET)
|
|
800cf62: 687b ldr r3, [r7, #4]
|
|
800cf64: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800cf68: b2db uxtb r3, r3
|
|
800cf6a: 2b00 cmp r3, #0
|
|
800cf6c: d106 bne.n 800cf7c <HAL_SPI_Init+0x58>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hspi->Lock = HAL_UNLOCKED;
|
|
800cf6e: 687b ldr r3, [r7, #4]
|
|
800cf70: 2200 movs r2, #0
|
|
800cf72: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hspi->MspInitCallback(hspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspInit(hspi);
|
|
800cf76: 6878 ldr r0, [r7, #4]
|
|
800cf78: f7f9 f96c bl 8006254 <HAL_SPI_MspInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
800cf7c: 687b ldr r3, [r7, #4]
|
|
800cf7e: 2202 movs r2, #2
|
|
800cf80: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Disable the selected SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800cf84: 687b ldr r3, [r7, #4]
|
|
800cf86: 681b ldr r3, [r3, #0]
|
|
800cf88: 681a ldr r2, [r3, #0]
|
|
800cf8a: 687b ldr r3, [r7, #4]
|
|
800cf8c: 681b ldr r3, [r3, #0]
|
|
800cf8e: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800cf92: 601a str r2, [r3, #0]
|
|
|
|
/* Align by default the rs fifo threshold on the data size */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
800cf94: 687b ldr r3, [r7, #4]
|
|
800cf96: 68db ldr r3, [r3, #12]
|
|
800cf98: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
800cf9c: d902 bls.n 800cfa4 <HAL_SPI_Init+0x80>
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_HF;
|
|
800cf9e: 2300 movs r3, #0
|
|
800cfa0: 60fb str r3, [r7, #12]
|
|
800cfa2: e002 b.n 800cfaa <HAL_SPI_Init+0x86>
|
|
}
|
|
else
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_QF;
|
|
800cfa4: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
800cfa8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* CRC calculation is valid only for 16Bit and 8 Bit */
|
|
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
|
|
800cfaa: 687b ldr r3, [r7, #4]
|
|
800cfac: 68db ldr r3, [r3, #12]
|
|
800cfae: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
|
|
800cfb2: d007 beq.n 800cfc4 <HAL_SPI_Init+0xa0>
|
|
800cfb4: 687b ldr r3, [r7, #4]
|
|
800cfb6: 68db ldr r3, [r3, #12]
|
|
800cfb8: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
800cfbc: d002 beq.n 800cfc4 <HAL_SPI_Init+0xa0>
|
|
{
|
|
/* CRC must be disabled */
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
800cfbe: 687b ldr r3, [r7, #4]
|
|
800cfc0: 2200 movs r2, #0
|
|
800cfc2: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
|
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
|
|
Communication speed, First bit and CRC calculation state */
|
|
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
|
800cfc4: 687b ldr r3, [r7, #4]
|
|
800cfc6: 685b ldr r3, [r3, #4]
|
|
800cfc8: f403 7282 and.w r2, r3, #260 @ 0x104
|
|
800cfcc: 687b ldr r3, [r7, #4]
|
|
800cfce: 689b ldr r3, [r3, #8]
|
|
800cfd0: f403 4304 and.w r3, r3, #33792 @ 0x8400
|
|
800cfd4: 431a orrs r2, r3
|
|
800cfd6: 687b ldr r3, [r7, #4]
|
|
800cfd8: 691b ldr r3, [r3, #16]
|
|
800cfda: f003 0302 and.w r3, r3, #2
|
|
800cfde: 431a orrs r2, r3
|
|
800cfe0: 687b ldr r3, [r7, #4]
|
|
800cfe2: 695b ldr r3, [r3, #20]
|
|
800cfe4: f003 0301 and.w r3, r3, #1
|
|
800cfe8: 431a orrs r2, r3
|
|
800cfea: 687b ldr r3, [r7, #4]
|
|
800cfec: 699b ldr r3, [r3, #24]
|
|
800cfee: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800cff2: 431a orrs r2, r3
|
|
800cff4: 687b ldr r3, [r7, #4]
|
|
800cff6: 69db ldr r3, [r3, #28]
|
|
800cff8: f003 0338 and.w r3, r3, #56 @ 0x38
|
|
800cffc: 431a orrs r2, r3
|
|
800cffe: 687b ldr r3, [r7, #4]
|
|
800d000: 6a1b ldr r3, [r3, #32]
|
|
800d002: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800d006: ea42 0103 orr.w r1, r2, r3
|
|
800d00a: 687b ldr r3, [r7, #4]
|
|
800d00c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800d00e: f403 5200 and.w r2, r3, #8192 @ 0x2000
|
|
800d012: 687b ldr r3, [r7, #4]
|
|
800d014: 681b ldr r3, [r3, #0]
|
|
800d016: 430a orrs r2, r1
|
|
800d018: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
|
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
|
|
800d01a: 687b ldr r3, [r7, #4]
|
|
800d01c: 699b ldr r3, [r3, #24]
|
|
800d01e: 0c1b lsrs r3, r3, #16
|
|
800d020: f003 0204 and.w r2, r3, #4
|
|
800d024: 687b ldr r3, [r7, #4]
|
|
800d026: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800d028: f003 0310 and.w r3, r3, #16
|
|
800d02c: 431a orrs r2, r3
|
|
800d02e: 687b ldr r3, [r7, #4]
|
|
800d030: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800d032: f003 0308 and.w r3, r3, #8
|
|
800d036: 431a orrs r2, r3
|
|
800d038: 687b ldr r3, [r7, #4]
|
|
800d03a: 68db ldr r3, [r3, #12]
|
|
800d03c: f403 6370 and.w r3, r3, #3840 @ 0xf00
|
|
800d040: ea42 0103 orr.w r1, r2, r3
|
|
800d044: 68fb ldr r3, [r7, #12]
|
|
800d046: f403 5280 and.w r2, r3, #4096 @ 0x1000
|
|
800d04a: 687b ldr r3, [r7, #4]
|
|
800d04c: 681b ldr r3, [r3, #0]
|
|
800d04e: 430a orrs r2, r1
|
|
800d050: 605a str r2, [r3, #4]
|
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
800d052: 687b ldr r3, [r7, #4]
|
|
800d054: 2200 movs r2, #0
|
|
800d056: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800d058: 687b ldr r3, [r7, #4]
|
|
800d05a: 2201 movs r2, #1
|
|
800d05c: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
return HAL_OK;
|
|
800d060: 2300 movs r3, #0
|
|
}
|
|
800d062: 4618 mov r0, r3
|
|
800d064: 3710 adds r7, #16
|
|
800d066: 46bd mov sp, r7
|
|
800d068: bd80 pop {r7, pc}
|
|
|
|
0800d06a <HAL_SPI_Transmit>:
|
|
* @param Size amount of data elements (u8 or u16) to be sent
|
|
* @param Timeout Timeout duration in ms
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
800d06a: b580 push {r7, lr}
|
|
800d06c: b088 sub sp, #32
|
|
800d06e: af00 add r7, sp, #0
|
|
800d070: 60f8 str r0, [r7, #12]
|
|
800d072: 60b9 str r1, [r7, #8]
|
|
800d074: 603b str r3, [r7, #0]
|
|
800d076: 4613 mov r3, r2
|
|
800d078: 80fb strh r3, [r7, #6]
|
|
|
|
/* Check Direction parameter */
|
|
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
800d07a: f7f9 fc77 bl 800696c <HAL_GetTick>
|
|
800d07e: 61f8 str r0, [r7, #28]
|
|
initial_TxXferCount = Size;
|
|
800d080: 88fb ldrh r3, [r7, #6]
|
|
800d082: 837b strh r3, [r7, #26]
|
|
|
|
if (hspi->State != HAL_SPI_STATE_READY)
|
|
800d084: 68fb ldr r3, [r7, #12]
|
|
800d086: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800d08a: b2db uxtb r3, r3
|
|
800d08c: 2b01 cmp r3, #1
|
|
800d08e: d001 beq.n 800d094 <HAL_SPI_Transmit+0x2a>
|
|
{
|
|
return HAL_BUSY;
|
|
800d090: 2302 movs r3, #2
|
|
800d092: e15c b.n 800d34e <HAL_SPI_Transmit+0x2e4>
|
|
}
|
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
800d094: 68bb ldr r3, [r7, #8]
|
|
800d096: 2b00 cmp r3, #0
|
|
800d098: d002 beq.n 800d0a0 <HAL_SPI_Transmit+0x36>
|
|
800d09a: 88fb ldrh r3, [r7, #6]
|
|
800d09c: 2b00 cmp r3, #0
|
|
800d09e: d101 bne.n 800d0a4 <HAL_SPI_Transmit+0x3a>
|
|
{
|
|
return HAL_ERROR;
|
|
800d0a0: 2301 movs r3, #1
|
|
800d0a2: e154 b.n 800d34e <HAL_SPI_Transmit+0x2e4>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hspi);
|
|
800d0a4: 68fb ldr r3, [r7, #12]
|
|
800d0a6: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
800d0aa: 2b01 cmp r3, #1
|
|
800d0ac: d101 bne.n 800d0b2 <HAL_SPI_Transmit+0x48>
|
|
800d0ae: 2302 movs r3, #2
|
|
800d0b0: e14d b.n 800d34e <HAL_SPI_Transmit+0x2e4>
|
|
800d0b2: 68fb ldr r3, [r7, #12]
|
|
800d0b4: 2201 movs r2, #1
|
|
800d0b6: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set the transaction information */
|
|
hspi->State = HAL_SPI_STATE_BUSY_TX;
|
|
800d0ba: 68fb ldr r3, [r7, #12]
|
|
800d0bc: 2203 movs r2, #3
|
|
800d0be: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
800d0c2: 68fb ldr r3, [r7, #12]
|
|
800d0c4: 2200 movs r2, #0
|
|
800d0c6: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pTxBuffPtr = (const uint8_t *)pData;
|
|
800d0c8: 68fb ldr r3, [r7, #12]
|
|
800d0ca: 68ba ldr r2, [r7, #8]
|
|
800d0cc: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferSize = Size;
|
|
800d0ce: 68fb ldr r3, [r7, #12]
|
|
800d0d0: 88fa ldrh r2, [r7, #6]
|
|
800d0d2: 879a strh r2, [r3, #60] @ 0x3c
|
|
hspi->TxXferCount = Size;
|
|
800d0d4: 68fb ldr r3, [r7, #12]
|
|
800d0d6: 88fa ldrh r2, [r7, #6]
|
|
800d0d8: 87da strh r2, [r3, #62] @ 0x3e
|
|
|
|
/*Init field not used in handle to zero */
|
|
hspi->pRxBuffPtr = (uint8_t *)NULL;
|
|
800d0da: 68fb ldr r3, [r7, #12]
|
|
800d0dc: 2200 movs r2, #0
|
|
800d0de: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferSize = 0U;
|
|
800d0e0: 68fb ldr r3, [r7, #12]
|
|
800d0e2: 2200 movs r2, #0
|
|
800d0e4: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->RxXferCount = 0U;
|
|
800d0e8: 68fb ldr r3, [r7, #12]
|
|
800d0ea: 2200 movs r2, #0
|
|
800d0ec: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->TxISR = NULL;
|
|
800d0f0: 68fb ldr r3, [r7, #12]
|
|
800d0f2: 2200 movs r2, #0
|
|
800d0f4: 651a str r2, [r3, #80] @ 0x50
|
|
hspi->RxISR = NULL;
|
|
800d0f6: 68fb ldr r3, [r7, #12]
|
|
800d0f8: 2200 movs r2, #0
|
|
800d0fa: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Configure communication direction : 1Line */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
800d0fc: 68fb ldr r3, [r7, #12]
|
|
800d0fe: 689b ldr r3, [r3, #8]
|
|
800d100: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800d104: d10f bne.n 800d126 <HAL_SPI_Transmit+0xbc>
|
|
{
|
|
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800d106: 68fb ldr r3, [r7, #12]
|
|
800d108: 681b ldr r3, [r3, #0]
|
|
800d10a: 681a ldr r2, [r3, #0]
|
|
800d10c: 68fb ldr r3, [r7, #12]
|
|
800d10e: 681b ldr r3, [r3, #0]
|
|
800d110: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800d114: 601a str r2, [r3, #0]
|
|
SPI_1LINE_TX(hspi);
|
|
800d116: 68fb ldr r3, [r7, #12]
|
|
800d118: 681b ldr r3, [r3, #0]
|
|
800d11a: 681a ldr r2, [r3, #0]
|
|
800d11c: 68fb ldr r3, [r7, #12]
|
|
800d11e: 681b ldr r3, [r3, #0]
|
|
800d120: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
800d124: 601a str r2, [r3, #0]
|
|
SPI_RESET_CRC(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
800d126: 68fb ldr r3, [r7, #12]
|
|
800d128: 681b ldr r3, [r3, #0]
|
|
800d12a: 681b ldr r3, [r3, #0]
|
|
800d12c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800d130: 2b40 cmp r3, #64 @ 0x40
|
|
800d132: d007 beq.n 800d144 <HAL_SPI_Transmit+0xda>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
800d134: 68fb ldr r3, [r7, #12]
|
|
800d136: 681b ldr r3, [r3, #0]
|
|
800d138: 681a ldr r2, [r3, #0]
|
|
800d13a: 68fb ldr r3, [r7, #12]
|
|
800d13c: 681b ldr r3, [r3, #0]
|
|
800d13e: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
800d142: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Transmit data in 16 Bit mode */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
800d144: 68fb ldr r3, [r7, #12]
|
|
800d146: 68db ldr r3, [r3, #12]
|
|
800d148: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
800d14c: d952 bls.n 800d1f4 <HAL_SPI_Transmit+0x18a>
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
800d14e: 68fb ldr r3, [r7, #12]
|
|
800d150: 685b ldr r3, [r3, #4]
|
|
800d152: 2b00 cmp r3, #0
|
|
800d154: d002 beq.n 800d15c <HAL_SPI_Transmit+0xf2>
|
|
800d156: 8b7b ldrh r3, [r7, #26]
|
|
800d158: 2b01 cmp r3, #1
|
|
800d15a: d145 bne.n 800d1e8 <HAL_SPI_Transmit+0x17e>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800d15c: 68fb ldr r3, [r7, #12]
|
|
800d15e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d160: 881a ldrh r2, [r3, #0]
|
|
800d162: 68fb ldr r3, [r7, #12]
|
|
800d164: 681b ldr r3, [r3, #0]
|
|
800d166: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800d168: 68fb ldr r3, [r7, #12]
|
|
800d16a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d16c: 1c9a adds r2, r3, #2
|
|
800d16e: 68fb ldr r3, [r7, #12]
|
|
800d170: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800d172: 68fb ldr r3, [r7, #12]
|
|
800d174: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d176: b29b uxth r3, r3
|
|
800d178: 3b01 subs r3, #1
|
|
800d17a: b29a uxth r2, r3
|
|
800d17c: 68fb ldr r3, [r7, #12]
|
|
800d17e: 87da strh r2, [r3, #62] @ 0x3e
|
|
}
|
|
/* Transmit data in 16 Bit mode */
|
|
while (hspi->TxXferCount > 0U)
|
|
800d180: e032 b.n 800d1e8 <HAL_SPI_Transmit+0x17e>
|
|
{
|
|
/* Wait until TXE flag is set to send data */
|
|
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
|
|
800d182: 68fb ldr r3, [r7, #12]
|
|
800d184: 681b ldr r3, [r3, #0]
|
|
800d186: 689b ldr r3, [r3, #8]
|
|
800d188: f003 0302 and.w r3, r3, #2
|
|
800d18c: 2b02 cmp r3, #2
|
|
800d18e: d112 bne.n 800d1b6 <HAL_SPI_Transmit+0x14c>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800d190: 68fb ldr r3, [r7, #12]
|
|
800d192: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d194: 881a ldrh r2, [r3, #0]
|
|
800d196: 68fb ldr r3, [r7, #12]
|
|
800d198: 681b ldr r3, [r3, #0]
|
|
800d19a: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800d19c: 68fb ldr r3, [r7, #12]
|
|
800d19e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d1a0: 1c9a adds r2, r3, #2
|
|
800d1a2: 68fb ldr r3, [r7, #12]
|
|
800d1a4: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800d1a6: 68fb ldr r3, [r7, #12]
|
|
800d1a8: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d1aa: b29b uxth r3, r3
|
|
800d1ac: 3b01 subs r3, #1
|
|
800d1ae: b29a uxth r2, r3
|
|
800d1b0: 68fb ldr r3, [r7, #12]
|
|
800d1b2: 87da strh r2, [r3, #62] @ 0x3e
|
|
800d1b4: e018 b.n 800d1e8 <HAL_SPI_Transmit+0x17e>
|
|
}
|
|
else
|
|
{
|
|
/* Timeout management */
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
|
|
800d1b6: f7f9 fbd9 bl 800696c <HAL_GetTick>
|
|
800d1ba: 4602 mov r2, r0
|
|
800d1bc: 69fb ldr r3, [r7, #28]
|
|
800d1be: 1ad3 subs r3, r2, r3
|
|
800d1c0: 683a ldr r2, [r7, #0]
|
|
800d1c2: 429a cmp r2, r3
|
|
800d1c4: d803 bhi.n 800d1ce <HAL_SPI_Transmit+0x164>
|
|
800d1c6: 683b ldr r3, [r7, #0]
|
|
800d1c8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800d1cc: d102 bne.n 800d1d4 <HAL_SPI_Transmit+0x16a>
|
|
800d1ce: 683b ldr r3, [r7, #0]
|
|
800d1d0: 2b00 cmp r3, #0
|
|
800d1d2: d109 bne.n 800d1e8 <HAL_SPI_Transmit+0x17e>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800d1d4: 68fb ldr r3, [r7, #12]
|
|
800d1d6: 2201 movs r2, #1
|
|
800d1d8: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
800d1dc: 68fb ldr r3, [r7, #12]
|
|
800d1de: 2200 movs r2, #0
|
|
800d1e0: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
800d1e4: 2303 movs r3, #3
|
|
800d1e6: e0b2 b.n 800d34e <HAL_SPI_Transmit+0x2e4>
|
|
while (hspi->TxXferCount > 0U)
|
|
800d1e8: 68fb ldr r3, [r7, #12]
|
|
800d1ea: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d1ec: b29b uxth r3, r3
|
|
800d1ee: 2b00 cmp r3, #0
|
|
800d1f0: d1c7 bne.n 800d182 <HAL_SPI_Transmit+0x118>
|
|
800d1f2: e083 b.n 800d2fc <HAL_SPI_Transmit+0x292>
|
|
}
|
|
}
|
|
/* Transmit data in 8 Bit mode */
|
|
else
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
800d1f4: 68fb ldr r3, [r7, #12]
|
|
800d1f6: 685b ldr r3, [r3, #4]
|
|
800d1f8: 2b00 cmp r3, #0
|
|
800d1fa: d002 beq.n 800d202 <HAL_SPI_Transmit+0x198>
|
|
800d1fc: 8b7b ldrh r3, [r7, #26]
|
|
800d1fe: 2b01 cmp r3, #1
|
|
800d200: d177 bne.n 800d2f2 <HAL_SPI_Transmit+0x288>
|
|
{
|
|
if (hspi->TxXferCount > 1U)
|
|
800d202: 68fb ldr r3, [r7, #12]
|
|
800d204: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d206: b29b uxth r3, r3
|
|
800d208: 2b01 cmp r3, #1
|
|
800d20a: d912 bls.n 800d232 <HAL_SPI_Transmit+0x1c8>
|
|
{
|
|
/* write on the data register in packing mode */
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800d20c: 68fb ldr r3, [r7, #12]
|
|
800d20e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d210: 881a ldrh r2, [r3, #0]
|
|
800d212: 68fb ldr r3, [r7, #12]
|
|
800d214: 681b ldr r3, [r3, #0]
|
|
800d216: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800d218: 68fb ldr r3, [r7, #12]
|
|
800d21a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d21c: 1c9a adds r2, r3, #2
|
|
800d21e: 68fb ldr r3, [r7, #12]
|
|
800d220: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
800d222: 68fb ldr r3, [r7, #12]
|
|
800d224: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d226: b29b uxth r3, r3
|
|
800d228: 3b02 subs r3, #2
|
|
800d22a: b29a uxth r2, r3
|
|
800d22c: 68fb ldr r3, [r7, #12]
|
|
800d22e: 87da strh r2, [r3, #62] @ 0x3e
|
|
800d230: e05f b.n 800d2f2 <HAL_SPI_Transmit+0x288>
|
|
}
|
|
else
|
|
{
|
|
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
800d232: 68fb ldr r3, [r7, #12]
|
|
800d234: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800d236: 68fb ldr r3, [r7, #12]
|
|
800d238: 681b ldr r3, [r3, #0]
|
|
800d23a: 330c adds r3, #12
|
|
800d23c: 7812 ldrb r2, [r2, #0]
|
|
800d23e: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr ++;
|
|
800d240: 68fb ldr r3, [r7, #12]
|
|
800d242: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d244: 1c5a adds r2, r3, #1
|
|
800d246: 68fb ldr r3, [r7, #12]
|
|
800d248: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800d24a: 68fb ldr r3, [r7, #12]
|
|
800d24c: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d24e: b29b uxth r3, r3
|
|
800d250: 3b01 subs r3, #1
|
|
800d252: b29a uxth r2, r3
|
|
800d254: 68fb ldr r3, [r7, #12]
|
|
800d256: 87da strh r2, [r3, #62] @ 0x3e
|
|
}
|
|
}
|
|
while (hspi->TxXferCount > 0U)
|
|
800d258: e04b b.n 800d2f2 <HAL_SPI_Transmit+0x288>
|
|
{
|
|
/* Wait until TXE flag is set to send data */
|
|
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
|
|
800d25a: 68fb ldr r3, [r7, #12]
|
|
800d25c: 681b ldr r3, [r3, #0]
|
|
800d25e: 689b ldr r3, [r3, #8]
|
|
800d260: f003 0302 and.w r3, r3, #2
|
|
800d264: 2b02 cmp r3, #2
|
|
800d266: d12b bne.n 800d2c0 <HAL_SPI_Transmit+0x256>
|
|
{
|
|
if (hspi->TxXferCount > 1U)
|
|
800d268: 68fb ldr r3, [r7, #12]
|
|
800d26a: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d26c: b29b uxth r3, r3
|
|
800d26e: 2b01 cmp r3, #1
|
|
800d270: d912 bls.n 800d298 <HAL_SPI_Transmit+0x22e>
|
|
{
|
|
/* write on the data register in packing mode */
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800d272: 68fb ldr r3, [r7, #12]
|
|
800d274: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d276: 881a ldrh r2, [r3, #0]
|
|
800d278: 68fb ldr r3, [r7, #12]
|
|
800d27a: 681b ldr r3, [r3, #0]
|
|
800d27c: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800d27e: 68fb ldr r3, [r7, #12]
|
|
800d280: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d282: 1c9a adds r2, r3, #2
|
|
800d284: 68fb ldr r3, [r7, #12]
|
|
800d286: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
800d288: 68fb ldr r3, [r7, #12]
|
|
800d28a: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d28c: b29b uxth r3, r3
|
|
800d28e: 3b02 subs r3, #2
|
|
800d290: b29a uxth r2, r3
|
|
800d292: 68fb ldr r3, [r7, #12]
|
|
800d294: 87da strh r2, [r3, #62] @ 0x3e
|
|
800d296: e02c b.n 800d2f2 <HAL_SPI_Transmit+0x288>
|
|
}
|
|
else
|
|
{
|
|
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
800d298: 68fb ldr r3, [r7, #12]
|
|
800d29a: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800d29c: 68fb ldr r3, [r7, #12]
|
|
800d29e: 681b ldr r3, [r3, #0]
|
|
800d2a0: 330c adds r3, #12
|
|
800d2a2: 7812 ldrb r2, [r2, #0]
|
|
800d2a4: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr++;
|
|
800d2a6: 68fb ldr r3, [r7, #12]
|
|
800d2a8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d2aa: 1c5a adds r2, r3, #1
|
|
800d2ac: 68fb ldr r3, [r7, #12]
|
|
800d2ae: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800d2b0: 68fb ldr r3, [r7, #12]
|
|
800d2b2: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d2b4: b29b uxth r3, r3
|
|
800d2b6: 3b01 subs r3, #1
|
|
800d2b8: b29a uxth r2, r3
|
|
800d2ba: 68fb ldr r3, [r7, #12]
|
|
800d2bc: 87da strh r2, [r3, #62] @ 0x3e
|
|
800d2be: e018 b.n 800d2f2 <HAL_SPI_Transmit+0x288>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Timeout management */
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
|
|
800d2c0: f7f9 fb54 bl 800696c <HAL_GetTick>
|
|
800d2c4: 4602 mov r2, r0
|
|
800d2c6: 69fb ldr r3, [r7, #28]
|
|
800d2c8: 1ad3 subs r3, r2, r3
|
|
800d2ca: 683a ldr r2, [r7, #0]
|
|
800d2cc: 429a cmp r2, r3
|
|
800d2ce: d803 bhi.n 800d2d8 <HAL_SPI_Transmit+0x26e>
|
|
800d2d0: 683b ldr r3, [r7, #0]
|
|
800d2d2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800d2d6: d102 bne.n 800d2de <HAL_SPI_Transmit+0x274>
|
|
800d2d8: 683b ldr r3, [r7, #0]
|
|
800d2da: 2b00 cmp r3, #0
|
|
800d2dc: d109 bne.n 800d2f2 <HAL_SPI_Transmit+0x288>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800d2de: 68fb ldr r3, [r7, #12]
|
|
800d2e0: 2201 movs r2, #1
|
|
800d2e2: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
800d2e6: 68fb ldr r3, [r7, #12]
|
|
800d2e8: 2200 movs r2, #0
|
|
800d2ea: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
800d2ee: 2303 movs r3, #3
|
|
800d2f0: e02d b.n 800d34e <HAL_SPI_Transmit+0x2e4>
|
|
while (hspi->TxXferCount > 0U)
|
|
800d2f2: 68fb ldr r3, [r7, #12]
|
|
800d2f4: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d2f6: b29b uxth r3, r3
|
|
800d2f8: 2b00 cmp r3, #0
|
|
800d2fa: d1ae bne.n 800d25a <HAL_SPI_Transmit+0x1f0>
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
|
|
800d2fc: 69fa ldr r2, [r7, #28]
|
|
800d2fe: 6839 ldr r1, [r7, #0]
|
|
800d300: 68f8 ldr r0, [r7, #12]
|
|
800d302: f000 ff63 bl 800e1cc <SPI_EndRxTxTransaction>
|
|
800d306: 4603 mov r3, r0
|
|
800d308: 2b00 cmp r3, #0
|
|
800d30a: d002 beq.n 800d312 <HAL_SPI_Transmit+0x2a8>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
|
|
800d30c: 68fb ldr r3, [r7, #12]
|
|
800d30e: 2220 movs r2, #32
|
|
800d310: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Clear overrun flag in 2 Lines communication mode because received is not read */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
|
|
800d312: 68fb ldr r3, [r7, #12]
|
|
800d314: 689b ldr r3, [r3, #8]
|
|
800d316: 2b00 cmp r3, #0
|
|
800d318: d10a bne.n 800d330 <HAL_SPI_Transmit+0x2c6>
|
|
{
|
|
__HAL_SPI_CLEAR_OVRFLAG(hspi);
|
|
800d31a: 2300 movs r3, #0
|
|
800d31c: 617b str r3, [r7, #20]
|
|
800d31e: 68fb ldr r3, [r7, #12]
|
|
800d320: 681b ldr r3, [r3, #0]
|
|
800d322: 68db ldr r3, [r3, #12]
|
|
800d324: 617b str r3, [r7, #20]
|
|
800d326: 68fb ldr r3, [r7, #12]
|
|
800d328: 681b ldr r3, [r3, #0]
|
|
800d32a: 689b ldr r3, [r3, #8]
|
|
800d32c: 617b str r3, [r7, #20]
|
|
800d32e: 697b ldr r3, [r7, #20]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800d330: 68fb ldr r3, [r7, #12]
|
|
800d332: 2201 movs r2, #1
|
|
800d334: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
800d338: 68fb ldr r3, [r7, #12]
|
|
800d33a: 2200 movs r2, #0
|
|
800d33c: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
800d340: 68fb ldr r3, [r7, #12]
|
|
800d342: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800d344: 2b00 cmp r3, #0
|
|
800d346: d001 beq.n 800d34c <HAL_SPI_Transmit+0x2e2>
|
|
{
|
|
return HAL_ERROR;
|
|
800d348: 2301 movs r3, #1
|
|
800d34a: e000 b.n 800d34e <HAL_SPI_Transmit+0x2e4>
|
|
}
|
|
else
|
|
{
|
|
return HAL_OK;
|
|
800d34c: 2300 movs r3, #0
|
|
}
|
|
}
|
|
800d34e: 4618 mov r0, r3
|
|
800d350: 3720 adds r7, #32
|
|
800d352: 46bd mov sp, r7
|
|
800d354: bd80 pop {r7, pc}
|
|
|
|
0800d356 <HAL_SPI_TransmitReceive>:
|
|
* @param Timeout Timeout duration in ms
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
|
uint16_t Size, uint32_t Timeout)
|
|
{
|
|
800d356: b580 push {r7, lr}
|
|
800d358: b08a sub sp, #40 @ 0x28
|
|
800d35a: af00 add r7, sp, #0
|
|
800d35c: 60f8 str r0, [r7, #12]
|
|
800d35e: 60b9 str r1, [r7, #8]
|
|
800d360: 607a str r2, [r7, #4]
|
|
800d362: 807b strh r3, [r7, #2]
|
|
__IO uint8_t *ptmpreg8;
|
|
__IO uint8_t tmpreg8 = 0;
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Variable used to alternate Rx and Tx during transfer */
|
|
uint32_t txallowed = 1U;
|
|
800d364: 2301 movs r3, #1
|
|
800d366: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Check Direction parameter */
|
|
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
800d368: f7f9 fb00 bl 800696c <HAL_GetTick>
|
|
800d36c: 6238 str r0, [r7, #32]
|
|
|
|
/* Init temporary variables */
|
|
tmp_state = hspi->State;
|
|
800d36e: 68fb ldr r3, [r7, #12]
|
|
800d370: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800d374: 77fb strb r3, [r7, #31]
|
|
tmp_mode = hspi->Init.Mode;
|
|
800d376: 68fb ldr r3, [r7, #12]
|
|
800d378: 685b ldr r3, [r3, #4]
|
|
800d37a: 61bb str r3, [r7, #24]
|
|
initial_TxXferCount = Size;
|
|
800d37c: 887b ldrh r3, [r7, #2]
|
|
800d37e: 82fb strh r3, [r7, #22]
|
|
initial_RxXferCount = Size;
|
|
800d380: 887b ldrh r3, [r7, #2]
|
|
800d382: 82bb strh r3, [r7, #20]
|
|
#if (USE_SPI_CRC != 0U)
|
|
spi_cr1 = READ_REG(hspi->Instance->CR1);
|
|
spi_cr2 = READ_REG(hspi->Instance->CR2);
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (!((tmp_state == HAL_SPI_STATE_READY) || \
|
|
800d384: 7ffb ldrb r3, [r7, #31]
|
|
800d386: 2b01 cmp r3, #1
|
|
800d388: d00c beq.n 800d3a4 <HAL_SPI_TransmitReceive+0x4e>
|
|
800d38a: 69bb ldr r3, [r7, #24]
|
|
800d38c: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800d390: d106 bne.n 800d3a0 <HAL_SPI_TransmitReceive+0x4a>
|
|
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
|
|
800d392: 68fb ldr r3, [r7, #12]
|
|
800d394: 689b ldr r3, [r3, #8]
|
|
800d396: 2b00 cmp r3, #0
|
|
800d398: d102 bne.n 800d3a0 <HAL_SPI_TransmitReceive+0x4a>
|
|
800d39a: 7ffb ldrb r3, [r7, #31]
|
|
800d39c: 2b04 cmp r3, #4
|
|
800d39e: d001 beq.n 800d3a4 <HAL_SPI_TransmitReceive+0x4e>
|
|
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
|
|
{
|
|
return HAL_BUSY;
|
|
800d3a0: 2302 movs r3, #2
|
|
800d3a2: e1f3 b.n 800d78c <HAL_SPI_TransmitReceive+0x436>
|
|
}
|
|
|
|
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
|
|
800d3a4: 68bb ldr r3, [r7, #8]
|
|
800d3a6: 2b00 cmp r3, #0
|
|
800d3a8: d005 beq.n 800d3b6 <HAL_SPI_TransmitReceive+0x60>
|
|
800d3aa: 687b ldr r3, [r7, #4]
|
|
800d3ac: 2b00 cmp r3, #0
|
|
800d3ae: d002 beq.n 800d3b6 <HAL_SPI_TransmitReceive+0x60>
|
|
800d3b0: 887b ldrh r3, [r7, #2]
|
|
800d3b2: 2b00 cmp r3, #0
|
|
800d3b4: d101 bne.n 800d3ba <HAL_SPI_TransmitReceive+0x64>
|
|
{
|
|
return HAL_ERROR;
|
|
800d3b6: 2301 movs r3, #1
|
|
800d3b8: e1e8 b.n 800d78c <HAL_SPI_TransmitReceive+0x436>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hspi);
|
|
800d3ba: 68fb ldr r3, [r7, #12]
|
|
800d3bc: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
800d3c0: 2b01 cmp r3, #1
|
|
800d3c2: d101 bne.n 800d3c8 <HAL_SPI_TransmitReceive+0x72>
|
|
800d3c4: 2302 movs r3, #2
|
|
800d3c6: e1e1 b.n 800d78c <HAL_SPI_TransmitReceive+0x436>
|
|
800d3c8: 68fb ldr r3, [r7, #12]
|
|
800d3ca: 2201 movs r2, #1
|
|
800d3cc: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
|
|
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
|
|
800d3d0: 68fb ldr r3, [r7, #12]
|
|
800d3d2: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800d3d6: b2db uxtb r3, r3
|
|
800d3d8: 2b04 cmp r3, #4
|
|
800d3da: d003 beq.n 800d3e4 <HAL_SPI_TransmitReceive+0x8e>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
|
|
800d3dc: 68fb ldr r3, [r7, #12]
|
|
800d3de: 2205 movs r2, #5
|
|
800d3e0: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
}
|
|
|
|
/* Set the transaction information */
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
800d3e4: 68fb ldr r3, [r7, #12]
|
|
800d3e6: 2200 movs r2, #0
|
|
800d3e8: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pRxBuffPtr = (uint8_t *)pRxData;
|
|
800d3ea: 68fb ldr r3, [r7, #12]
|
|
800d3ec: 687a ldr r2, [r7, #4]
|
|
800d3ee: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount = Size;
|
|
800d3f0: 68fb ldr r3, [r7, #12]
|
|
800d3f2: 887a ldrh r2, [r7, #2]
|
|
800d3f4: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->RxXferSize = Size;
|
|
800d3f8: 68fb ldr r3, [r7, #12]
|
|
800d3fa: 887a ldrh r2, [r7, #2]
|
|
800d3fc: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
|
|
800d400: 68fb ldr r3, [r7, #12]
|
|
800d402: 68ba ldr r2, [r7, #8]
|
|
800d404: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount = Size;
|
|
800d406: 68fb ldr r3, [r7, #12]
|
|
800d408: 887a ldrh r2, [r7, #2]
|
|
800d40a: 87da strh r2, [r3, #62] @ 0x3e
|
|
hspi->TxXferSize = Size;
|
|
800d40c: 68fb ldr r3, [r7, #12]
|
|
800d40e: 887a ldrh r2, [r7, #2]
|
|
800d410: 879a strh r2, [r3, #60] @ 0x3c
|
|
|
|
/*Init field not used in handle to zero */
|
|
hspi->RxISR = NULL;
|
|
800d412: 68fb ldr r3, [r7, #12]
|
|
800d414: 2200 movs r2, #0
|
|
800d416: 64da str r2, [r3, #76] @ 0x4c
|
|
hspi->TxISR = NULL;
|
|
800d418: 68fb ldr r3, [r7, #12]
|
|
800d41a: 2200 movs r2, #0
|
|
800d41c: 651a str r2, [r3, #80] @ 0x50
|
|
SPI_RESET_CRC(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Set the Rx Fifo threshold */
|
|
if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
|
|
800d41e: 68fb ldr r3, [r7, #12]
|
|
800d420: 68db ldr r3, [r3, #12]
|
|
800d422: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
800d426: d802 bhi.n 800d42e <HAL_SPI_TransmitReceive+0xd8>
|
|
800d428: 8abb ldrh r3, [r7, #20]
|
|
800d42a: 2b01 cmp r3, #1
|
|
800d42c: d908 bls.n 800d440 <HAL_SPI_TransmitReceive+0xea>
|
|
{
|
|
/* Set fiforxthreshold according the reception data length: 16bit */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
800d42e: 68fb ldr r3, [r7, #12]
|
|
800d430: 681b ldr r3, [r3, #0]
|
|
800d432: 685a ldr r2, [r3, #4]
|
|
800d434: 68fb ldr r3, [r7, #12]
|
|
800d436: 681b ldr r3, [r3, #0]
|
|
800d438: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
800d43c: 605a str r2, [r3, #4]
|
|
800d43e: e007 b.n 800d450 <HAL_SPI_TransmitReceive+0xfa>
|
|
}
|
|
else
|
|
{
|
|
/* Set fiforxthreshold according the reception data length: 8bit */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
800d440: 68fb ldr r3, [r7, #12]
|
|
800d442: 681b ldr r3, [r3, #0]
|
|
800d444: 685a ldr r2, [r3, #4]
|
|
800d446: 68fb ldr r3, [r7, #12]
|
|
800d448: 681b ldr r3, [r3, #0]
|
|
800d44a: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
800d44e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
800d450: 68fb ldr r3, [r7, #12]
|
|
800d452: 681b ldr r3, [r3, #0]
|
|
800d454: 681b ldr r3, [r3, #0]
|
|
800d456: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800d45a: 2b40 cmp r3, #64 @ 0x40
|
|
800d45c: d007 beq.n 800d46e <HAL_SPI_TransmitReceive+0x118>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
800d45e: 68fb ldr r3, [r7, #12]
|
|
800d460: 681b ldr r3, [r3, #0]
|
|
800d462: 681a ldr r2, [r3, #0]
|
|
800d464: 68fb ldr r3, [r7, #12]
|
|
800d466: 681b ldr r3, [r3, #0]
|
|
800d468: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
800d46c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Transmit and Receive data in 16 Bit mode */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
800d46e: 68fb ldr r3, [r7, #12]
|
|
800d470: 68db ldr r3, [r3, #12]
|
|
800d472: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
800d476: f240 8083 bls.w 800d580 <HAL_SPI_TransmitReceive+0x22a>
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
800d47a: 68fb ldr r3, [r7, #12]
|
|
800d47c: 685b ldr r3, [r3, #4]
|
|
800d47e: 2b00 cmp r3, #0
|
|
800d480: d002 beq.n 800d488 <HAL_SPI_TransmitReceive+0x132>
|
|
800d482: 8afb ldrh r3, [r7, #22]
|
|
800d484: 2b01 cmp r3, #1
|
|
800d486: d16f bne.n 800d568 <HAL_SPI_TransmitReceive+0x212>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800d488: 68fb ldr r3, [r7, #12]
|
|
800d48a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d48c: 881a ldrh r2, [r3, #0]
|
|
800d48e: 68fb ldr r3, [r7, #12]
|
|
800d490: 681b ldr r3, [r3, #0]
|
|
800d492: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800d494: 68fb ldr r3, [r7, #12]
|
|
800d496: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d498: 1c9a adds r2, r3, #2
|
|
800d49a: 68fb ldr r3, [r7, #12]
|
|
800d49c: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800d49e: 68fb ldr r3, [r7, #12]
|
|
800d4a0: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d4a2: b29b uxth r3, r3
|
|
800d4a4: 3b01 subs r3, #1
|
|
800d4a6: b29a uxth r2, r3
|
|
800d4a8: 68fb ldr r3, [r7, #12]
|
|
800d4aa: 87da strh r2, [r3, #62] @ 0x3e
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
}
|
|
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
|
|
800d4ac: e05c b.n 800d568 <HAL_SPI_TransmitReceive+0x212>
|
|
{
|
|
/* Check TXE flag */
|
|
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
|
|
800d4ae: 68fb ldr r3, [r7, #12]
|
|
800d4b0: 681b ldr r3, [r3, #0]
|
|
800d4b2: 689b ldr r3, [r3, #8]
|
|
800d4b4: f003 0302 and.w r3, r3, #2
|
|
800d4b8: 2b02 cmp r3, #2
|
|
800d4ba: d11b bne.n 800d4f4 <HAL_SPI_TransmitReceive+0x19e>
|
|
800d4bc: 68fb ldr r3, [r7, #12]
|
|
800d4be: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d4c0: b29b uxth r3, r3
|
|
800d4c2: 2b00 cmp r3, #0
|
|
800d4c4: d016 beq.n 800d4f4 <HAL_SPI_TransmitReceive+0x19e>
|
|
800d4c6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800d4c8: 2b01 cmp r3, #1
|
|
800d4ca: d113 bne.n 800d4f4 <HAL_SPI_TransmitReceive+0x19e>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800d4cc: 68fb ldr r3, [r7, #12]
|
|
800d4ce: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d4d0: 881a ldrh r2, [r3, #0]
|
|
800d4d2: 68fb ldr r3, [r7, #12]
|
|
800d4d4: 681b ldr r3, [r3, #0]
|
|
800d4d6: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800d4d8: 68fb ldr r3, [r7, #12]
|
|
800d4da: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d4dc: 1c9a adds r2, r3, #2
|
|
800d4de: 68fb ldr r3, [r7, #12]
|
|
800d4e0: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800d4e2: 68fb ldr r3, [r7, #12]
|
|
800d4e4: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d4e6: b29b uxth r3, r3
|
|
800d4e8: 3b01 subs r3, #1
|
|
800d4ea: b29a uxth r2, r3
|
|
800d4ec: 68fb ldr r3, [r7, #12]
|
|
800d4ee: 87da strh r2, [r3, #62] @ 0x3e
|
|
/* Next Data is a reception (Rx). Tx not allowed */
|
|
txallowed = 0U;
|
|
800d4f0: 2300 movs r3, #0
|
|
800d4f2: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
}
|
|
|
|
/* Check RXNE flag */
|
|
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
|
|
800d4f4: 68fb ldr r3, [r7, #12]
|
|
800d4f6: 681b ldr r3, [r3, #0]
|
|
800d4f8: 689b ldr r3, [r3, #8]
|
|
800d4fa: f003 0301 and.w r3, r3, #1
|
|
800d4fe: 2b01 cmp r3, #1
|
|
800d500: d11c bne.n 800d53c <HAL_SPI_TransmitReceive+0x1e6>
|
|
800d502: 68fb ldr r3, [r7, #12]
|
|
800d504: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d508: b29b uxth r3, r3
|
|
800d50a: 2b00 cmp r3, #0
|
|
800d50c: d016 beq.n 800d53c <HAL_SPI_TransmitReceive+0x1e6>
|
|
{
|
|
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
|
|
800d50e: 68fb ldr r3, [r7, #12]
|
|
800d510: 681b ldr r3, [r3, #0]
|
|
800d512: 68da ldr r2, [r3, #12]
|
|
800d514: 68fb ldr r3, [r7, #12]
|
|
800d516: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d518: b292 uxth r2, r2
|
|
800d51a: 801a strh r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint16_t);
|
|
800d51c: 68fb ldr r3, [r7, #12]
|
|
800d51e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d520: 1c9a adds r2, r3, #2
|
|
800d522: 68fb ldr r3, [r7, #12]
|
|
800d524: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
800d526: 68fb ldr r3, [r7, #12]
|
|
800d528: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d52c: b29b uxth r3, r3
|
|
800d52e: 3b01 subs r3, #1
|
|
800d530: b29a uxth r2, r3
|
|
800d532: 68fb ldr r3, [r7, #12]
|
|
800d534: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
/* Next Data is a Transmission (Tx). Tx is allowed */
|
|
txallowed = 1U;
|
|
800d538: 2301 movs r3, #1
|
|
800d53a: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
|
|
800d53c: f7f9 fa16 bl 800696c <HAL_GetTick>
|
|
800d540: 4602 mov r2, r0
|
|
800d542: 6a3b ldr r3, [r7, #32]
|
|
800d544: 1ad3 subs r3, r2, r3
|
|
800d546: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800d548: 429a cmp r2, r3
|
|
800d54a: d80d bhi.n 800d568 <HAL_SPI_TransmitReceive+0x212>
|
|
800d54c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d54e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800d552: d009 beq.n 800d568 <HAL_SPI_TransmitReceive+0x212>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800d554: 68fb ldr r3, [r7, #12]
|
|
800d556: 2201 movs r2, #1
|
|
800d558: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
800d55c: 68fb ldr r3, [r7, #12]
|
|
800d55e: 2200 movs r2, #0
|
|
800d560: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
800d564: 2303 movs r3, #3
|
|
800d566: e111 b.n 800d78c <HAL_SPI_TransmitReceive+0x436>
|
|
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
|
|
800d568: 68fb ldr r3, [r7, #12]
|
|
800d56a: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d56c: b29b uxth r3, r3
|
|
800d56e: 2b00 cmp r3, #0
|
|
800d570: d19d bne.n 800d4ae <HAL_SPI_TransmitReceive+0x158>
|
|
800d572: 68fb ldr r3, [r7, #12]
|
|
800d574: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d578: b29b uxth r3, r3
|
|
800d57a: 2b00 cmp r3, #0
|
|
800d57c: d197 bne.n 800d4ae <HAL_SPI_TransmitReceive+0x158>
|
|
800d57e: e0e5 b.n 800d74c <HAL_SPI_TransmitReceive+0x3f6>
|
|
}
|
|
}
|
|
/* Transmit and Receive data in 8 Bit mode */
|
|
else
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
800d580: 68fb ldr r3, [r7, #12]
|
|
800d582: 685b ldr r3, [r3, #4]
|
|
800d584: 2b00 cmp r3, #0
|
|
800d586: d003 beq.n 800d590 <HAL_SPI_TransmitReceive+0x23a>
|
|
800d588: 8afb ldrh r3, [r7, #22]
|
|
800d58a: 2b01 cmp r3, #1
|
|
800d58c: f040 80d1 bne.w 800d732 <HAL_SPI_TransmitReceive+0x3dc>
|
|
{
|
|
if (hspi->TxXferCount > 1U)
|
|
800d590: 68fb ldr r3, [r7, #12]
|
|
800d592: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d594: b29b uxth r3, r3
|
|
800d596: 2b01 cmp r3, #1
|
|
800d598: d912 bls.n 800d5c0 <HAL_SPI_TransmitReceive+0x26a>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800d59a: 68fb ldr r3, [r7, #12]
|
|
800d59c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d59e: 881a ldrh r2, [r3, #0]
|
|
800d5a0: 68fb ldr r3, [r7, #12]
|
|
800d5a2: 681b ldr r3, [r3, #0]
|
|
800d5a4: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800d5a6: 68fb ldr r3, [r7, #12]
|
|
800d5a8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d5aa: 1c9a adds r2, r3, #2
|
|
800d5ac: 68fb ldr r3, [r7, #12]
|
|
800d5ae: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
800d5b0: 68fb ldr r3, [r7, #12]
|
|
800d5b2: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d5b4: b29b uxth r3, r3
|
|
800d5b6: 3b02 subs r3, #2
|
|
800d5b8: b29a uxth r2, r3
|
|
800d5ba: 68fb ldr r3, [r7, #12]
|
|
800d5bc: 87da strh r2, [r3, #62] @ 0x3e
|
|
800d5be: e0b8 b.n 800d732 <HAL_SPI_TransmitReceive+0x3dc>
|
|
}
|
|
else
|
|
{
|
|
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
800d5c0: 68fb ldr r3, [r7, #12]
|
|
800d5c2: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800d5c4: 68fb ldr r3, [r7, #12]
|
|
800d5c6: 681b ldr r3, [r3, #0]
|
|
800d5c8: 330c adds r3, #12
|
|
800d5ca: 7812 ldrb r2, [r2, #0]
|
|
800d5cc: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr++;
|
|
800d5ce: 68fb ldr r3, [r7, #12]
|
|
800d5d0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d5d2: 1c5a adds r2, r3, #1
|
|
800d5d4: 68fb ldr r3, [r7, #12]
|
|
800d5d6: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800d5d8: 68fb ldr r3, [r7, #12]
|
|
800d5da: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d5dc: b29b uxth r3, r3
|
|
800d5de: 3b01 subs r3, #1
|
|
800d5e0: b29a uxth r2, r3
|
|
800d5e2: 68fb ldr r3, [r7, #12]
|
|
800d5e4: 87da strh r2, [r3, #62] @ 0x3e
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
}
|
|
}
|
|
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
|
|
800d5e6: e0a4 b.n 800d732 <HAL_SPI_TransmitReceive+0x3dc>
|
|
{
|
|
/* Check TXE flag */
|
|
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
|
|
800d5e8: 68fb ldr r3, [r7, #12]
|
|
800d5ea: 681b ldr r3, [r3, #0]
|
|
800d5ec: 689b ldr r3, [r3, #8]
|
|
800d5ee: f003 0302 and.w r3, r3, #2
|
|
800d5f2: 2b02 cmp r3, #2
|
|
800d5f4: d134 bne.n 800d660 <HAL_SPI_TransmitReceive+0x30a>
|
|
800d5f6: 68fb ldr r3, [r7, #12]
|
|
800d5f8: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d5fa: b29b uxth r3, r3
|
|
800d5fc: 2b00 cmp r3, #0
|
|
800d5fe: d02f beq.n 800d660 <HAL_SPI_TransmitReceive+0x30a>
|
|
800d600: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800d602: 2b01 cmp r3, #1
|
|
800d604: d12c bne.n 800d660 <HAL_SPI_TransmitReceive+0x30a>
|
|
{
|
|
if (hspi->TxXferCount > 1U)
|
|
800d606: 68fb ldr r3, [r7, #12]
|
|
800d608: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d60a: b29b uxth r3, r3
|
|
800d60c: 2b01 cmp r3, #1
|
|
800d60e: d912 bls.n 800d636 <HAL_SPI_TransmitReceive+0x2e0>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800d610: 68fb ldr r3, [r7, #12]
|
|
800d612: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d614: 881a ldrh r2, [r3, #0]
|
|
800d616: 68fb ldr r3, [r7, #12]
|
|
800d618: 681b ldr r3, [r3, #0]
|
|
800d61a: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800d61c: 68fb ldr r3, [r7, #12]
|
|
800d61e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d620: 1c9a adds r2, r3, #2
|
|
800d622: 68fb ldr r3, [r7, #12]
|
|
800d624: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
800d626: 68fb ldr r3, [r7, #12]
|
|
800d628: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d62a: b29b uxth r3, r3
|
|
800d62c: 3b02 subs r3, #2
|
|
800d62e: b29a uxth r2, r3
|
|
800d630: 68fb ldr r3, [r7, #12]
|
|
800d632: 87da strh r2, [r3, #62] @ 0x3e
|
|
800d634: e012 b.n 800d65c <HAL_SPI_TransmitReceive+0x306>
|
|
}
|
|
else
|
|
{
|
|
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
800d636: 68fb ldr r3, [r7, #12]
|
|
800d638: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800d63a: 68fb ldr r3, [r7, #12]
|
|
800d63c: 681b ldr r3, [r3, #0]
|
|
800d63e: 330c adds r3, #12
|
|
800d640: 7812 ldrb r2, [r2, #0]
|
|
800d642: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr++;
|
|
800d644: 68fb ldr r3, [r7, #12]
|
|
800d646: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800d648: 1c5a adds r2, r3, #1
|
|
800d64a: 68fb ldr r3, [r7, #12]
|
|
800d64c: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800d64e: 68fb ldr r3, [r7, #12]
|
|
800d650: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d652: b29b uxth r3, r3
|
|
800d654: 3b01 subs r3, #1
|
|
800d656: b29a uxth r2, r3
|
|
800d658: 68fb ldr r3, [r7, #12]
|
|
800d65a: 87da strh r2, [r3, #62] @ 0x3e
|
|
}
|
|
/* Next Data is a reception (Rx). Tx not allowed */
|
|
txallowed = 0U;
|
|
800d65c: 2300 movs r3, #0
|
|
800d65e: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
}
|
|
|
|
/* Wait until RXNE flag is reset */
|
|
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
|
|
800d660: 68fb ldr r3, [r7, #12]
|
|
800d662: 681b ldr r3, [r3, #0]
|
|
800d664: 689b ldr r3, [r3, #8]
|
|
800d666: f003 0301 and.w r3, r3, #1
|
|
800d66a: 2b01 cmp r3, #1
|
|
800d66c: d148 bne.n 800d700 <HAL_SPI_TransmitReceive+0x3aa>
|
|
800d66e: 68fb ldr r3, [r7, #12]
|
|
800d670: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d674: b29b uxth r3, r3
|
|
800d676: 2b00 cmp r3, #0
|
|
800d678: d042 beq.n 800d700 <HAL_SPI_TransmitReceive+0x3aa>
|
|
{
|
|
if (hspi->RxXferCount > 1U)
|
|
800d67a: 68fb ldr r3, [r7, #12]
|
|
800d67c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d680: b29b uxth r3, r3
|
|
800d682: 2b01 cmp r3, #1
|
|
800d684: d923 bls.n 800d6ce <HAL_SPI_TransmitReceive+0x378>
|
|
{
|
|
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
|
|
800d686: 68fb ldr r3, [r7, #12]
|
|
800d688: 681b ldr r3, [r3, #0]
|
|
800d68a: 68da ldr r2, [r3, #12]
|
|
800d68c: 68fb ldr r3, [r7, #12]
|
|
800d68e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d690: b292 uxth r2, r2
|
|
800d692: 801a strh r2, [r3, #0]
|
|
hspi->pRxBuffPtr += sizeof(uint16_t);
|
|
800d694: 68fb ldr r3, [r7, #12]
|
|
800d696: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d698: 1c9a adds r2, r3, #2
|
|
800d69a: 68fb ldr r3, [r7, #12]
|
|
800d69c: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount -= 2U;
|
|
800d69e: 68fb ldr r3, [r7, #12]
|
|
800d6a0: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d6a4: b29b uxth r3, r3
|
|
800d6a6: 3b02 subs r3, #2
|
|
800d6a8: b29a uxth r2, r3
|
|
800d6aa: 68fb ldr r3, [r7, #12]
|
|
800d6ac: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
if (hspi->RxXferCount <= 1U)
|
|
800d6b0: 68fb ldr r3, [r7, #12]
|
|
800d6b2: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d6b6: b29b uxth r3, r3
|
|
800d6b8: 2b01 cmp r3, #1
|
|
800d6ba: d81f bhi.n 800d6fc <HAL_SPI_TransmitReceive+0x3a6>
|
|
{
|
|
/* Set RX Fifo threshold before to switch on 8 bit data size */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
800d6bc: 68fb ldr r3, [r7, #12]
|
|
800d6be: 681b ldr r3, [r3, #0]
|
|
800d6c0: 685a ldr r2, [r3, #4]
|
|
800d6c2: 68fb ldr r3, [r7, #12]
|
|
800d6c4: 681b ldr r3, [r3, #0]
|
|
800d6c6: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
800d6ca: 605a str r2, [r3, #4]
|
|
800d6cc: e016 b.n 800d6fc <HAL_SPI_TransmitReceive+0x3a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
|
|
800d6ce: 68fb ldr r3, [r7, #12]
|
|
800d6d0: 681b ldr r3, [r3, #0]
|
|
800d6d2: f103 020c add.w r2, r3, #12
|
|
800d6d6: 68fb ldr r3, [r7, #12]
|
|
800d6d8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d6da: 7812 ldrb r2, [r2, #0]
|
|
800d6dc: b2d2 uxtb r2, r2
|
|
800d6de: 701a strb r2, [r3, #0]
|
|
hspi->pRxBuffPtr++;
|
|
800d6e0: 68fb ldr r3, [r7, #12]
|
|
800d6e2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d6e4: 1c5a adds r2, r3, #1
|
|
800d6e6: 68fb ldr r3, [r7, #12]
|
|
800d6e8: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferCount--;
|
|
800d6ea: 68fb ldr r3, [r7, #12]
|
|
800d6ec: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d6f0: b29b uxth r3, r3
|
|
800d6f2: 3b01 subs r3, #1
|
|
800d6f4: b29a uxth r2, r3
|
|
800d6f6: 68fb ldr r3, [r7, #12]
|
|
800d6f8: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
}
|
|
/* Next Data is a Transmission (Tx). Tx is allowed */
|
|
txallowed = 1U;
|
|
800d6fc: 2301 movs r3, #1
|
|
800d6fe: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
|
|
800d700: f7f9 f934 bl 800696c <HAL_GetTick>
|
|
800d704: 4602 mov r2, r0
|
|
800d706: 6a3b ldr r3, [r7, #32]
|
|
800d708: 1ad3 subs r3, r2, r3
|
|
800d70a: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800d70c: 429a cmp r2, r3
|
|
800d70e: d803 bhi.n 800d718 <HAL_SPI_TransmitReceive+0x3c2>
|
|
800d710: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d712: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800d716: d102 bne.n 800d71e <HAL_SPI_TransmitReceive+0x3c8>
|
|
800d718: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800d71a: 2b00 cmp r3, #0
|
|
800d71c: d109 bne.n 800d732 <HAL_SPI_TransmitReceive+0x3dc>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800d71e: 68fb ldr r3, [r7, #12]
|
|
800d720: 2201 movs r2, #1
|
|
800d722: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
800d726: 68fb ldr r3, [r7, #12]
|
|
800d728: 2200 movs r2, #0
|
|
800d72a: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
800d72e: 2303 movs r3, #3
|
|
800d730: e02c b.n 800d78c <HAL_SPI_TransmitReceive+0x436>
|
|
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
|
|
800d732: 68fb ldr r3, [r7, #12]
|
|
800d734: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d736: b29b uxth r3, r3
|
|
800d738: 2b00 cmp r3, #0
|
|
800d73a: f47f af55 bne.w 800d5e8 <HAL_SPI_TransmitReceive+0x292>
|
|
800d73e: 68fb ldr r3, [r7, #12]
|
|
800d740: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d744: b29b uxth r3, r3
|
|
800d746: 2b00 cmp r3, #0
|
|
800d748: f47f af4e bne.w 800d5e8 <HAL_SPI_TransmitReceive+0x292>
|
|
return HAL_ERROR;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
|
|
800d74c: 6a3a ldr r2, [r7, #32]
|
|
800d74e: 6b39 ldr r1, [r7, #48] @ 0x30
|
|
800d750: 68f8 ldr r0, [r7, #12]
|
|
800d752: f000 fd3b bl 800e1cc <SPI_EndRxTxTransaction>
|
|
800d756: 4603 mov r3, r0
|
|
800d758: 2b00 cmp r3, #0
|
|
800d75a: d008 beq.n 800d76e <HAL_SPI_TransmitReceive+0x418>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
|
|
800d75c: 68fb ldr r3, [r7, #12]
|
|
800d75e: 2220 movs r2, #32
|
|
800d760: 661a str r2, [r3, #96] @ 0x60
|
|
__HAL_UNLOCK(hspi);
|
|
800d762: 68fb ldr r3, [r7, #12]
|
|
800d764: 2200 movs r2, #0
|
|
800d766: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_ERROR;
|
|
800d76a: 2301 movs r3, #1
|
|
800d76c: e00e b.n 800d78c <HAL_SPI_TransmitReceive+0x436>
|
|
}
|
|
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800d76e: 68fb ldr r3, [r7, #12]
|
|
800d770: 2201 movs r2, #1
|
|
800d772: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Unlock the process */
|
|
__HAL_UNLOCK(hspi);
|
|
800d776: 68fb ldr r3, [r7, #12]
|
|
800d778: 2200 movs r2, #0
|
|
800d77a: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
800d77e: 68fb ldr r3, [r7, #12]
|
|
800d780: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800d782: 2b00 cmp r3, #0
|
|
800d784: d001 beq.n 800d78a <HAL_SPI_TransmitReceive+0x434>
|
|
{
|
|
return HAL_ERROR;
|
|
800d786: 2301 movs r3, #1
|
|
800d788: e000 b.n 800d78c <HAL_SPI_TransmitReceive+0x436>
|
|
}
|
|
else
|
|
{
|
|
return HAL_OK;
|
|
800d78a: 2300 movs r3, #0
|
|
}
|
|
}
|
|
800d78c: 4618 mov r0, r3
|
|
800d78e: 3728 adds r7, #40 @ 0x28
|
|
800d790: 46bd mov sp, r7
|
|
800d792: bd80 pop {r7, pc}
|
|
|
|
0800d794 <HAL_SPI_TransmitReceive_DMA>:
|
|
* @param Size amount of data elements (u8 or u16) to be sent and received
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
|
uint16_t Size)
|
|
{
|
|
800d794: b580 push {r7, lr}
|
|
800d796: b086 sub sp, #24
|
|
800d798: af00 add r7, sp, #0
|
|
800d79a: 60f8 str r0, [r7, #12]
|
|
800d79c: 60b9 str r1, [r7, #8]
|
|
800d79e: 607a str r2, [r7, #4]
|
|
800d7a0: 807b strh r3, [r7, #2]
|
|
|
|
/* Check Direction parameter */
|
|
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
|
|
|
|
/* Init temporary variables */
|
|
tmp_state = hspi->State;
|
|
800d7a2: 68fb ldr r3, [r7, #12]
|
|
800d7a4: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800d7a8: 75fb strb r3, [r7, #23]
|
|
tmp_mode = hspi->Init.Mode;
|
|
800d7aa: 68fb ldr r3, [r7, #12]
|
|
800d7ac: 685b ldr r3, [r3, #4]
|
|
800d7ae: 613b str r3, [r7, #16]
|
|
|
|
if (!((tmp_state == HAL_SPI_STATE_READY) ||
|
|
800d7b0: 7dfb ldrb r3, [r7, #23]
|
|
800d7b2: 2b01 cmp r3, #1
|
|
800d7b4: d00c beq.n 800d7d0 <HAL_SPI_TransmitReceive_DMA+0x3c>
|
|
800d7b6: 693b ldr r3, [r7, #16]
|
|
800d7b8: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800d7bc: d106 bne.n 800d7cc <HAL_SPI_TransmitReceive_DMA+0x38>
|
|
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
|
|
800d7be: 68fb ldr r3, [r7, #12]
|
|
800d7c0: 689b ldr r3, [r3, #8]
|
|
800d7c2: 2b00 cmp r3, #0
|
|
800d7c4: d102 bne.n 800d7cc <HAL_SPI_TransmitReceive_DMA+0x38>
|
|
800d7c6: 7dfb ldrb r3, [r7, #23]
|
|
800d7c8: 2b04 cmp r3, #4
|
|
800d7ca: d001 beq.n 800d7d0 <HAL_SPI_TransmitReceive_DMA+0x3c>
|
|
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
|
|
{
|
|
return HAL_BUSY;
|
|
800d7cc: 2302 movs r3, #2
|
|
800d7ce: e158 b.n 800da82 <HAL_SPI_TransmitReceive_DMA+0x2ee>
|
|
}
|
|
|
|
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
|
|
800d7d0: 68bb ldr r3, [r7, #8]
|
|
800d7d2: 2b00 cmp r3, #0
|
|
800d7d4: d005 beq.n 800d7e2 <HAL_SPI_TransmitReceive_DMA+0x4e>
|
|
800d7d6: 687b ldr r3, [r7, #4]
|
|
800d7d8: 2b00 cmp r3, #0
|
|
800d7da: d002 beq.n 800d7e2 <HAL_SPI_TransmitReceive_DMA+0x4e>
|
|
800d7dc: 887b ldrh r3, [r7, #2]
|
|
800d7de: 2b00 cmp r3, #0
|
|
800d7e0: d101 bne.n 800d7e6 <HAL_SPI_TransmitReceive_DMA+0x52>
|
|
{
|
|
return HAL_ERROR;
|
|
800d7e2: 2301 movs r3, #1
|
|
800d7e4: e14d b.n 800da82 <HAL_SPI_TransmitReceive_DMA+0x2ee>
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hspi);
|
|
800d7e6: 68fb ldr r3, [r7, #12]
|
|
800d7e8: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
800d7ec: 2b01 cmp r3, #1
|
|
800d7ee: d101 bne.n 800d7f4 <HAL_SPI_TransmitReceive_DMA+0x60>
|
|
800d7f0: 2302 movs r3, #2
|
|
800d7f2: e146 b.n 800da82 <HAL_SPI_TransmitReceive_DMA+0x2ee>
|
|
800d7f4: 68fb ldr r3, [r7, #12]
|
|
800d7f6: 2201 movs r2, #1
|
|
800d7f8: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
|
|
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
|
|
800d7fc: 68fb ldr r3, [r7, #12]
|
|
800d7fe: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800d802: b2db uxtb r3, r3
|
|
800d804: 2b04 cmp r3, #4
|
|
800d806: d003 beq.n 800d810 <HAL_SPI_TransmitReceive_DMA+0x7c>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
|
|
800d808: 68fb ldr r3, [r7, #12]
|
|
800d80a: 2205 movs r2, #5
|
|
800d80c: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
}
|
|
|
|
/* Set the transaction information */
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
800d810: 68fb ldr r3, [r7, #12]
|
|
800d812: 2200 movs r2, #0
|
|
800d814: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
|
|
800d816: 68fb ldr r3, [r7, #12]
|
|
800d818: 68ba ldr r2, [r7, #8]
|
|
800d81a: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferSize = Size;
|
|
800d81c: 68fb ldr r3, [r7, #12]
|
|
800d81e: 887a ldrh r2, [r7, #2]
|
|
800d820: 879a strh r2, [r3, #60] @ 0x3c
|
|
hspi->TxXferCount = Size;
|
|
800d822: 68fb ldr r3, [r7, #12]
|
|
800d824: 887a ldrh r2, [r7, #2]
|
|
800d826: 87da strh r2, [r3, #62] @ 0x3e
|
|
hspi->pRxBuffPtr = (uint8_t *)pRxData;
|
|
800d828: 68fb ldr r3, [r7, #12]
|
|
800d82a: 687a ldr r2, [r7, #4]
|
|
800d82c: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferSize = Size;
|
|
800d82e: 68fb ldr r3, [r7, #12]
|
|
800d830: 887a ldrh r2, [r7, #2]
|
|
800d832: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->RxXferCount = Size;
|
|
800d836: 68fb ldr r3, [r7, #12]
|
|
800d838: 887a ldrh r2, [r7, #2]
|
|
800d83a: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Init field not used in handle to zero */
|
|
hspi->RxISR = NULL;
|
|
800d83e: 68fb ldr r3, [r7, #12]
|
|
800d840: 2200 movs r2, #0
|
|
800d842: 64da str r2, [r3, #76] @ 0x4c
|
|
hspi->TxISR = NULL;
|
|
800d844: 68fb ldr r3, [r7, #12]
|
|
800d846: 2200 movs r2, #0
|
|
800d848: 651a str r2, [r3, #80] @ 0x50
|
|
SPI_RESET_CRC(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Reset the threshold bit */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
|
|
800d84a: 68fb ldr r3, [r7, #12]
|
|
800d84c: 681b ldr r3, [r3, #0]
|
|
800d84e: 685a ldr r2, [r3, #4]
|
|
800d850: 68fb ldr r3, [r7, #12]
|
|
800d852: 681b ldr r3, [r3, #0]
|
|
800d854: f422 42c0 bic.w r2, r2, #24576 @ 0x6000
|
|
800d858: 605a str r2, [r3, #4]
|
|
|
|
/* The packing mode management is enabled by the DMA settings according the spi data size */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
800d85a: 68fb ldr r3, [r7, #12]
|
|
800d85c: 68db ldr r3, [r3, #12]
|
|
800d85e: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
800d862: d908 bls.n 800d876 <HAL_SPI_TransmitReceive_DMA+0xe2>
|
|
{
|
|
/* Set fiforxthreshold according the reception data length: 16bit */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
800d864: 68fb ldr r3, [r7, #12]
|
|
800d866: 681b ldr r3, [r3, #0]
|
|
800d868: 685a ldr r2, [r3, #4]
|
|
800d86a: 68fb ldr r3, [r7, #12]
|
|
800d86c: 681b ldr r3, [r3, #0]
|
|
800d86e: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
800d872: 605a str r2, [r3, #4]
|
|
800d874: e06f b.n 800d956 <HAL_SPI_TransmitReceive_DMA+0x1c2>
|
|
}
|
|
else
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 8bit */
|
|
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
800d876: 68fb ldr r3, [r7, #12]
|
|
800d878: 681b ldr r3, [r3, #0]
|
|
800d87a: 685a ldr r2, [r3, #4]
|
|
800d87c: 68fb ldr r3, [r7, #12]
|
|
800d87e: 681b ldr r3, [r3, #0]
|
|
800d880: f442 5280 orr.w r2, r2, #4096 @ 0x1000
|
|
800d884: 605a str r2, [r3, #4]
|
|
|
|
if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
|
|
800d886: 68fb ldr r3, [r7, #12]
|
|
800d888: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800d88a: 699b ldr r3, [r3, #24]
|
|
800d88c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800d890: d126 bne.n 800d8e0 <HAL_SPI_TransmitReceive_DMA+0x14c>
|
|
{
|
|
if ((hspi->TxXferSize & 0x1U) == 0x0U)
|
|
800d892: 68fb ldr r3, [r7, #12]
|
|
800d894: 8f9b ldrh r3, [r3, #60] @ 0x3c
|
|
800d896: f003 0301 and.w r3, r3, #1
|
|
800d89a: 2b00 cmp r3, #0
|
|
800d89c: d10f bne.n 800d8be <HAL_SPI_TransmitReceive_DMA+0x12a>
|
|
{
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
|
|
800d89e: 68fb ldr r3, [r7, #12]
|
|
800d8a0: 681b ldr r3, [r3, #0]
|
|
800d8a2: 685a ldr r2, [r3, #4]
|
|
800d8a4: 68fb ldr r3, [r7, #12]
|
|
800d8a6: 681b ldr r3, [r3, #0]
|
|
800d8a8: f422 4280 bic.w r2, r2, #16384 @ 0x4000
|
|
800d8ac: 605a str r2, [r3, #4]
|
|
hspi->TxXferCount = hspi->TxXferCount >> 1U;
|
|
800d8ae: 68fb ldr r3, [r7, #12]
|
|
800d8b0: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d8b2: b29b uxth r3, r3
|
|
800d8b4: 085b lsrs r3, r3, #1
|
|
800d8b6: b29a uxth r2, r3
|
|
800d8b8: 68fb ldr r3, [r7, #12]
|
|
800d8ba: 87da strh r2, [r3, #62] @ 0x3e
|
|
800d8bc: e010 b.n 800d8e0 <HAL_SPI_TransmitReceive_DMA+0x14c>
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
|
|
800d8be: 68fb ldr r3, [r7, #12]
|
|
800d8c0: 681b ldr r3, [r3, #0]
|
|
800d8c2: 685a ldr r2, [r3, #4]
|
|
800d8c4: 68fb ldr r3, [r7, #12]
|
|
800d8c6: 681b ldr r3, [r3, #0]
|
|
800d8c8: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
800d8cc: 605a str r2, [r3, #4]
|
|
hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
|
|
800d8ce: 68fb ldr r3, [r7, #12]
|
|
800d8d0: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800d8d2: b29b uxth r3, r3
|
|
800d8d4: 085b lsrs r3, r3, #1
|
|
800d8d6: b29b uxth r3, r3
|
|
800d8d8: 3301 adds r3, #1
|
|
800d8da: b29a uxth r2, r3
|
|
800d8dc: 68fb ldr r3, [r7, #12]
|
|
800d8de: 87da strh r2, [r3, #62] @ 0x3e
|
|
}
|
|
}
|
|
|
|
if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
|
|
800d8e0: 68fb ldr r3, [r7, #12]
|
|
800d8e2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800d8e4: 699b ldr r3, [r3, #24]
|
|
800d8e6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800d8ea: d134 bne.n 800d956 <HAL_SPI_TransmitReceive_DMA+0x1c2>
|
|
{
|
|
/* Set RX Fifo threshold according the reception data length: 16bit */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
|
|
800d8ec: 68fb ldr r3, [r7, #12]
|
|
800d8ee: 681b ldr r3, [r3, #0]
|
|
800d8f0: 685a ldr r2, [r3, #4]
|
|
800d8f2: 68fb ldr r3, [r7, #12]
|
|
800d8f4: 681b ldr r3, [r3, #0]
|
|
800d8f6: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
800d8fa: 605a str r2, [r3, #4]
|
|
|
|
if ((hspi->RxXferCount & 0x1U) == 0x0U)
|
|
800d8fc: 68fb ldr r3, [r7, #12]
|
|
800d8fe: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d902: b29b uxth r3, r3
|
|
800d904: f003 0301 and.w r3, r3, #1
|
|
800d908: 2b00 cmp r3, #0
|
|
800d90a: d111 bne.n 800d930 <HAL_SPI_TransmitReceive_DMA+0x19c>
|
|
{
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
|
|
800d90c: 68fb ldr r3, [r7, #12]
|
|
800d90e: 681b ldr r3, [r3, #0]
|
|
800d910: 685a ldr r2, [r3, #4]
|
|
800d912: 68fb ldr r3, [r7, #12]
|
|
800d914: 681b ldr r3, [r3, #0]
|
|
800d916: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
800d91a: 605a str r2, [r3, #4]
|
|
hspi->RxXferCount = hspi->RxXferCount >> 1U;
|
|
800d91c: 68fb ldr r3, [r7, #12]
|
|
800d91e: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d922: b29b uxth r3, r3
|
|
800d924: 085b lsrs r3, r3, #1
|
|
800d926: b29a uxth r2, r3
|
|
800d928: 68fb ldr r3, [r7, #12]
|
|
800d92a: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
800d92e: e012 b.n 800d956 <HAL_SPI_TransmitReceive_DMA+0x1c2>
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
|
|
800d930: 68fb ldr r3, [r7, #12]
|
|
800d932: 681b ldr r3, [r3, #0]
|
|
800d934: 685a ldr r2, [r3, #4]
|
|
800d936: 68fb ldr r3, [r7, #12]
|
|
800d938: 681b ldr r3, [r3, #0]
|
|
800d93a: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
800d93e: 605a str r2, [r3, #4]
|
|
hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
|
|
800d940: 68fb ldr r3, [r7, #12]
|
|
800d942: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d946: b29b uxth r3, r3
|
|
800d948: 085b lsrs r3, r3, #1
|
|
800d94a: b29b uxth r3, r3
|
|
800d94c: 3301 adds r3, #1
|
|
800d94e: b29a uxth r2, r3
|
|
800d950: 68fb ldr r3, [r7, #12]
|
|
800d952: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
|
|
if (hspi->State == HAL_SPI_STATE_BUSY_RX)
|
|
800d956: 68fb ldr r3, [r7, #12]
|
|
800d958: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800d95c: b2db uxtb r3, r3
|
|
800d95e: 2b04 cmp r3, #4
|
|
800d960: d108 bne.n 800d974 <HAL_SPI_TransmitReceive_DMA+0x1e0>
|
|
{
|
|
/* Set the SPI Rx DMA Half transfer complete callback */
|
|
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
|
|
800d962: 68fb ldr r3, [r7, #12]
|
|
800d964: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800d966: 4a49 ldr r2, [pc, #292] @ (800da8c <HAL_SPI_TransmitReceive_DMA+0x2f8>)
|
|
800d968: 631a str r2, [r3, #48] @ 0x30
|
|
hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
|
|
800d96a: 68fb ldr r3, [r7, #12]
|
|
800d96c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800d96e: 4a48 ldr r2, [pc, #288] @ (800da90 <HAL_SPI_TransmitReceive_DMA+0x2fc>)
|
|
800d970: 62da str r2, [r3, #44] @ 0x2c
|
|
800d972: e007 b.n 800d984 <HAL_SPI_TransmitReceive_DMA+0x1f0>
|
|
}
|
|
else
|
|
{
|
|
/* Set the SPI Tx/Rx DMA Half transfer complete callback */
|
|
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
|
|
800d974: 68fb ldr r3, [r7, #12]
|
|
800d976: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800d978: 4a46 ldr r2, [pc, #280] @ (800da94 <HAL_SPI_TransmitReceive_DMA+0x300>)
|
|
800d97a: 631a str r2, [r3, #48] @ 0x30
|
|
hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
|
|
800d97c: 68fb ldr r3, [r7, #12]
|
|
800d97e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800d980: 4a45 ldr r2, [pc, #276] @ (800da98 <HAL_SPI_TransmitReceive_DMA+0x304>)
|
|
800d982: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
/* Set the DMA error callback */
|
|
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
|
|
800d984: 68fb ldr r3, [r7, #12]
|
|
800d986: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800d988: 4a44 ldr r2, [pc, #272] @ (800da9c <HAL_SPI_TransmitReceive_DMA+0x308>)
|
|
800d98a: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Set the DMA AbortCpltCallback */
|
|
hspi->hdmarx->XferAbortCallback = NULL;
|
|
800d98c: 68fb ldr r3, [r7, #12]
|
|
800d98e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800d990: 2200 movs r2, #0
|
|
800d992: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Enable the Rx DMA Stream/Channel */
|
|
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
|
|
800d994: 68fb ldr r3, [r7, #12]
|
|
800d996: 6d98 ldr r0, [r3, #88] @ 0x58
|
|
800d998: 68fb ldr r3, [r7, #12]
|
|
800d99a: 681b ldr r3, [r3, #0]
|
|
800d99c: 330c adds r3, #12
|
|
800d99e: 4619 mov r1, r3
|
|
800d9a0: 68fb ldr r3, [r7, #12]
|
|
800d9a2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800d9a4: 461a mov r2, r3
|
|
hspi->RxXferCount))
|
|
800d9a6: 68fb ldr r3, [r7, #12]
|
|
800d9a8: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
|
|
800d9ac: b29b uxth r3, r3
|
|
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
|
|
800d9ae: f7f9 fa07 bl 8006dc0 <HAL_DMA_Start_IT>
|
|
800d9b2: 4603 mov r3, r0
|
|
800d9b4: 2b00 cmp r3, #0
|
|
800d9b6: d00b beq.n 800d9d0 <HAL_SPI_TransmitReceive_DMA+0x23c>
|
|
{
|
|
/* Update SPI error code */
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
|
|
800d9b8: 68fb ldr r3, [r7, #12]
|
|
800d9ba: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800d9bc: f043 0210 orr.w r2, r3, #16
|
|
800d9c0: 68fb ldr r3, [r7, #12]
|
|
800d9c2: 661a str r2, [r3, #96] @ 0x60
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
800d9c4: 68fb ldr r3, [r7, #12]
|
|
800d9c6: 2200 movs r2, #0
|
|
800d9c8: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_ERROR;
|
|
800d9cc: 2301 movs r3, #1
|
|
800d9ce: e058 b.n 800da82 <HAL_SPI_TransmitReceive_DMA+0x2ee>
|
|
}
|
|
|
|
/* Enable Rx DMA Request */
|
|
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
|
|
800d9d0: 68fb ldr r3, [r7, #12]
|
|
800d9d2: 681b ldr r3, [r3, #0]
|
|
800d9d4: 685a ldr r2, [r3, #4]
|
|
800d9d6: 68fb ldr r3, [r7, #12]
|
|
800d9d8: 681b ldr r3, [r3, #0]
|
|
800d9da: f042 0201 orr.w r2, r2, #1
|
|
800d9de: 605a str r2, [r3, #4]
|
|
|
|
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
|
|
is performed in DMA reception complete callback */
|
|
hspi->hdmatx->XferHalfCpltCallback = NULL;
|
|
800d9e0: 68fb ldr r3, [r7, #12]
|
|
800d9e2: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800d9e4: 2200 movs r2, #0
|
|
800d9e6: 631a str r2, [r3, #48] @ 0x30
|
|
hspi->hdmatx->XferCpltCallback = NULL;
|
|
800d9e8: 68fb ldr r3, [r7, #12]
|
|
800d9ea: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800d9ec: 2200 movs r2, #0
|
|
800d9ee: 62da str r2, [r3, #44] @ 0x2c
|
|
hspi->hdmatx->XferErrorCallback = NULL;
|
|
800d9f0: 68fb ldr r3, [r7, #12]
|
|
800d9f2: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800d9f4: 2200 movs r2, #0
|
|
800d9f6: 635a str r2, [r3, #52] @ 0x34
|
|
hspi->hdmatx->XferAbortCallback = NULL;
|
|
800d9f8: 68fb ldr r3, [r7, #12]
|
|
800d9fa: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800d9fc: 2200 movs r2, #0
|
|
800d9fe: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Enable the Tx DMA Stream/Channel */
|
|
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
|
|
800da00: 68fb ldr r3, [r7, #12]
|
|
800da02: 6d58 ldr r0, [r3, #84] @ 0x54
|
|
800da04: 68fb ldr r3, [r7, #12]
|
|
800da06: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800da08: 4619 mov r1, r3
|
|
800da0a: 68fb ldr r3, [r7, #12]
|
|
800da0c: 681b ldr r3, [r3, #0]
|
|
800da0e: 330c adds r3, #12
|
|
800da10: 461a mov r2, r3
|
|
hspi->TxXferCount))
|
|
800da12: 68fb ldr r3, [r7, #12]
|
|
800da14: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800da16: b29b uxth r3, r3
|
|
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
|
|
800da18: f7f9 f9d2 bl 8006dc0 <HAL_DMA_Start_IT>
|
|
800da1c: 4603 mov r3, r0
|
|
800da1e: 2b00 cmp r3, #0
|
|
800da20: d00b beq.n 800da3a <HAL_SPI_TransmitReceive_DMA+0x2a6>
|
|
{
|
|
/* Update SPI error code */
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
|
|
800da22: 68fb ldr r3, [r7, #12]
|
|
800da24: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800da26: f043 0210 orr.w r2, r3, #16
|
|
800da2a: 68fb ldr r3, [r7, #12]
|
|
800da2c: 661a str r2, [r3, #96] @ 0x60
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
800da2e: 68fb ldr r3, [r7, #12]
|
|
800da30: 2200 movs r2, #0
|
|
800da32: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_ERROR;
|
|
800da36: 2301 movs r3, #1
|
|
800da38: e023 b.n 800da82 <HAL_SPI_TransmitReceive_DMA+0x2ee>
|
|
}
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
800da3a: 68fb ldr r3, [r7, #12]
|
|
800da3c: 681b ldr r3, [r3, #0]
|
|
800da3e: 681b ldr r3, [r3, #0]
|
|
800da40: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800da44: 2b40 cmp r3, #64 @ 0x40
|
|
800da46: d007 beq.n 800da58 <HAL_SPI_TransmitReceive_DMA+0x2c4>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
800da48: 68fb ldr r3, [r7, #12]
|
|
800da4a: 681b ldr r3, [r3, #0]
|
|
800da4c: 681a ldr r2, [r3, #0]
|
|
800da4e: 68fb ldr r3, [r7, #12]
|
|
800da50: 681b ldr r3, [r3, #0]
|
|
800da52: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
800da56: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
800da58: 68fb ldr r3, [r7, #12]
|
|
800da5a: 2200 movs r2, #0
|
|
800da5c: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Enable the SPI Error Interrupt Bit */
|
|
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
|
|
800da60: 68fb ldr r3, [r7, #12]
|
|
800da62: 681b ldr r3, [r3, #0]
|
|
800da64: 685a ldr r2, [r3, #4]
|
|
800da66: 68fb ldr r3, [r7, #12]
|
|
800da68: 681b ldr r3, [r3, #0]
|
|
800da6a: f042 0220 orr.w r2, r2, #32
|
|
800da6e: 605a str r2, [r3, #4]
|
|
|
|
/* Enable Tx DMA Request */
|
|
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
|
|
800da70: 68fb ldr r3, [r7, #12]
|
|
800da72: 681b ldr r3, [r3, #0]
|
|
800da74: 685a ldr r2, [r3, #4]
|
|
800da76: 68fb ldr r3, [r7, #12]
|
|
800da78: 681b ldr r3, [r3, #0]
|
|
800da7a: f042 0202 orr.w r2, r2, #2
|
|
800da7e: 605a str r2, [r3, #4]
|
|
|
|
return HAL_OK;
|
|
800da80: 2300 movs r3, #0
|
|
}
|
|
800da82: 4618 mov r0, r3
|
|
800da84: 3718 adds r7, #24
|
|
800da86: 46bd mov sp, r7
|
|
800da88: bd80 pop {r7, pc}
|
|
800da8a: bf00 nop
|
|
800da8c: 0800de69 .word 0x0800de69
|
|
800da90: 0800dd31 .word 0x0800dd31
|
|
800da94: 0800de85 .word 0x0800de85
|
|
800da98: 0800ddd9 .word 0x0800ddd9
|
|
800da9c: 0800dea1 .word 0x0800dea1
|
|
|
|
0800daa0 <HAL_SPI_Abort>:
|
|
* - Set handle State to READY
|
|
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800daa0: b580 push {r7, lr}
|
|
800daa2: b08a sub sp, #40 @ 0x28
|
|
800daa4: af02 add r7, sp, #8
|
|
800daa6: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef errorcode;
|
|
__IO uint32_t count;
|
|
__IO uint32_t resetcount;
|
|
|
|
/* Initialized local variable */
|
|
errorcode = HAL_OK;
|
|
800daa8: 2300 movs r3, #0
|
|
800daaa: 77fb strb r3, [r7, #31]
|
|
resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
|
|
800daac: 4b88 ldr r3, [pc, #544] @ (800dcd0 <HAL_SPI_Abort+0x230>)
|
|
800daae: 681b ldr r3, [r3, #0]
|
|
800dab0: 4a88 ldr r2, [pc, #544] @ (800dcd4 <HAL_SPI_Abort+0x234>)
|
|
800dab2: fba2 2303 umull r2, r3, r2, r3
|
|
800dab6: 0a5b lsrs r3, r3, #9
|
|
800dab8: 2264 movs r2, #100 @ 0x64
|
|
800daba: fb02 f303 mul.w r3, r2, r3
|
|
800dabe: 617b str r3, [r7, #20]
|
|
count = resetcount;
|
|
800dac0: 697b ldr r3, [r7, #20]
|
|
800dac2: 61bb str r3, [r7, #24]
|
|
|
|
/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
|
|
800dac4: 687b ldr r3, [r7, #4]
|
|
800dac6: 681b ldr r3, [r3, #0]
|
|
800dac8: 685a ldr r2, [r3, #4]
|
|
800daca: 687b ldr r3, [r7, #4]
|
|
800dacc: 681b ldr r3, [r3, #0]
|
|
800dace: f022 0220 bic.w r2, r2, #32
|
|
800dad2: 605a str r2, [r3, #4]
|
|
|
|
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
|
|
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
|
|
800dad4: 687b ldr r3, [r7, #4]
|
|
800dad6: 681b ldr r3, [r3, #0]
|
|
800dad8: 685b ldr r3, [r3, #4]
|
|
800dada: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800dade: 2b80 cmp r3, #128 @ 0x80
|
|
800dae0: d117 bne.n 800db12 <HAL_SPI_Abort+0x72>
|
|
{
|
|
hspi->TxISR = SPI_AbortTx_ISR;
|
|
800dae2: 687b ldr r3, [r7, #4]
|
|
800dae4: 4a7c ldr r2, [pc, #496] @ (800dcd8 <HAL_SPI_Abort+0x238>)
|
|
800dae6: 651a str r2, [r3, #80] @ 0x50
|
|
/* Wait HAL_SPI_STATE_ABORT state */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
800dae8: 69bb ldr r3, [r7, #24]
|
|
800daea: 2b00 cmp r3, #0
|
|
800daec: d106 bne.n 800dafc <HAL_SPI_Abort+0x5c>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
|
|
800daee: 687b ldr r3, [r7, #4]
|
|
800daf0: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800daf2: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
800daf6: 687b ldr r3, [r7, #4]
|
|
800daf8: 661a str r2, [r3, #96] @ 0x60
|
|
break;
|
|
800dafa: e008 b.n 800db0e <HAL_SPI_Abort+0x6e>
|
|
}
|
|
count--;
|
|
800dafc: 69bb ldr r3, [r7, #24]
|
|
800dafe: 3b01 subs r3, #1
|
|
800db00: 61bb str r3, [r7, #24]
|
|
} while (hspi->State != HAL_SPI_STATE_ABORT);
|
|
800db02: 687b ldr r3, [r7, #4]
|
|
800db04: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800db08: b2db uxtb r3, r3
|
|
800db0a: 2b07 cmp r3, #7
|
|
800db0c: d1ec bne.n 800dae8 <HAL_SPI_Abort+0x48>
|
|
/* Reset Timeout Counter */
|
|
count = resetcount;
|
|
800db0e: 697b ldr r3, [r7, #20]
|
|
800db10: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
|
|
800db12: 687b ldr r3, [r7, #4]
|
|
800db14: 681b ldr r3, [r3, #0]
|
|
800db16: 685b ldr r3, [r3, #4]
|
|
800db18: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800db1c: 2b40 cmp r3, #64 @ 0x40
|
|
800db1e: d117 bne.n 800db50 <HAL_SPI_Abort+0xb0>
|
|
{
|
|
hspi->RxISR = SPI_AbortRx_ISR;
|
|
800db20: 687b ldr r3, [r7, #4]
|
|
800db22: 4a6e ldr r2, [pc, #440] @ (800dcdc <HAL_SPI_Abort+0x23c>)
|
|
800db24: 64da str r2, [r3, #76] @ 0x4c
|
|
/* Wait HAL_SPI_STATE_ABORT state */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
800db26: 69bb ldr r3, [r7, #24]
|
|
800db28: 2b00 cmp r3, #0
|
|
800db2a: d106 bne.n 800db3a <HAL_SPI_Abort+0x9a>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
|
|
800db2c: 687b ldr r3, [r7, #4]
|
|
800db2e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800db30: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
800db34: 687b ldr r3, [r7, #4]
|
|
800db36: 661a str r2, [r3, #96] @ 0x60
|
|
break;
|
|
800db38: e008 b.n 800db4c <HAL_SPI_Abort+0xac>
|
|
}
|
|
count--;
|
|
800db3a: 69bb ldr r3, [r7, #24]
|
|
800db3c: 3b01 subs r3, #1
|
|
800db3e: 61bb str r3, [r7, #24]
|
|
} while (hspi->State != HAL_SPI_STATE_ABORT);
|
|
800db40: 687b ldr r3, [r7, #4]
|
|
800db42: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
800db46: b2db uxtb r3, r3
|
|
800db48: 2b07 cmp r3, #7
|
|
800db4a: d1ec bne.n 800db26 <HAL_SPI_Abort+0x86>
|
|
/* Reset Timeout Counter */
|
|
count = resetcount;
|
|
800db4c: 697b ldr r3, [r7, #20]
|
|
800db4e: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
/* Disable the SPI DMA Tx request if enabled */
|
|
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
|
|
800db50: 687b ldr r3, [r7, #4]
|
|
800db52: 681b ldr r3, [r3, #0]
|
|
800db54: 685b ldr r3, [r3, #4]
|
|
800db56: f003 0302 and.w r3, r3, #2
|
|
800db5a: 2b02 cmp r3, #2
|
|
800db5c: d141 bne.n 800dbe2 <HAL_SPI_Abort+0x142>
|
|
{
|
|
/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
|
|
if (hspi->hdmatx != NULL)
|
|
800db5e: 687b ldr r3, [r7, #4]
|
|
800db60: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800db62: 2b00 cmp r3, #0
|
|
800db64: d03d beq.n 800dbe2 <HAL_SPI_Abort+0x142>
|
|
{
|
|
/* Set the SPI DMA Abort callback :
|
|
will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
|
|
hspi->hdmatx->XferAbortCallback = NULL;
|
|
800db66: 687b ldr r3, [r7, #4]
|
|
800db68: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800db6a: 2200 movs r2, #0
|
|
800db6c: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Abort DMA Tx Handle linked to SPI Peripheral */
|
|
if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
|
|
800db6e: 687b ldr r3, [r7, #4]
|
|
800db70: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800db72: 4618 mov r0, r3
|
|
800db74: f7f9 f99f bl 8006eb6 <HAL_DMA_Abort>
|
|
800db78: 4603 mov r3, r0
|
|
800db7a: 2b00 cmp r3, #0
|
|
800db7c: d002 beq.n 800db84 <HAL_SPI_Abort+0xe4>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800db7e: 687b ldr r3, [r7, #4]
|
|
800db80: 2240 movs r2, #64 @ 0x40
|
|
800db82: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Disable Tx DMA Request */
|
|
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
|
|
800db84: 687b ldr r3, [r7, #4]
|
|
800db86: 681b ldr r3, [r3, #0]
|
|
800db88: 685a ldr r2, [r3, #4]
|
|
800db8a: 687b ldr r3, [r7, #4]
|
|
800db8c: 681b ldr r3, [r3, #0]
|
|
800db8e: f022 0202 bic.w r2, r2, #2
|
|
800db92: 605a str r2, [r3, #4]
|
|
|
|
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
|
|
800db94: f7f8 feea bl 800696c <HAL_GetTick>
|
|
800db98: 4603 mov r3, r0
|
|
800db9a: 461a mov r2, r3
|
|
800db9c: 2164 movs r1, #100 @ 0x64
|
|
800db9e: 6878 ldr r0, [r7, #4]
|
|
800dba0: f000 fb14 bl 800e1cc <SPI_EndRxTxTransaction>
|
|
800dba4: 4603 mov r3, r0
|
|
800dba6: 2b00 cmp r3, #0
|
|
800dba8: d002 beq.n 800dbb0 <HAL_SPI_Abort+0x110>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800dbaa: 687b ldr r3, [r7, #4]
|
|
800dbac: 2240 movs r2, #64 @ 0x40
|
|
800dbae: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Disable SPI Peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800dbb0: 687b ldr r3, [r7, #4]
|
|
800dbb2: 681b ldr r3, [r3, #0]
|
|
800dbb4: 681a ldr r2, [r3, #0]
|
|
800dbb6: 687b ldr r3, [r7, #4]
|
|
800dbb8: 681b ldr r3, [r3, #0]
|
|
800dbba: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800dbbe: 601a str r2, [r3, #0]
|
|
|
|
/* Empty the FRLVL fifo */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
|
|
800dbc0: f7f8 fed4 bl 800696c <HAL_GetTick>
|
|
800dbc4: 4603 mov r3, r0
|
|
800dbc6: 9300 str r3, [sp, #0]
|
|
800dbc8: 2364 movs r3, #100 @ 0x64
|
|
800dbca: 2200 movs r2, #0
|
|
800dbcc: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800dbd0: 6878 ldr r0, [r7, #4]
|
|
800dbd2: f000 fa0d bl 800dff0 <SPI_WaitFifoStateUntilTimeout>
|
|
800dbd6: 4603 mov r3, r0
|
|
800dbd8: 2b00 cmp r3, #0
|
|
800dbda: d002 beq.n 800dbe2 <HAL_SPI_Abort+0x142>
|
|
HAL_GetTick()) != HAL_OK)
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800dbdc: 687b ldr r3, [r7, #4]
|
|
800dbde: 2240 movs r2, #64 @ 0x40
|
|
800dbe0: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Disable the SPI DMA Rx request if enabled */
|
|
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
|
|
800dbe2: 687b ldr r3, [r7, #4]
|
|
800dbe4: 681b ldr r3, [r3, #0]
|
|
800dbe6: 685b ldr r3, [r3, #4]
|
|
800dbe8: f003 0301 and.w r3, r3, #1
|
|
800dbec: 2b01 cmp r3, #1
|
|
800dbee: d143 bne.n 800dc78 <HAL_SPI_Abort+0x1d8>
|
|
{
|
|
/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
|
|
if (hspi->hdmarx != NULL)
|
|
800dbf0: 687b ldr r3, [r7, #4]
|
|
800dbf2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800dbf4: 2b00 cmp r3, #0
|
|
800dbf6: d03f beq.n 800dc78 <HAL_SPI_Abort+0x1d8>
|
|
{
|
|
/* Set the SPI DMA Abort callback :
|
|
will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
|
|
hspi->hdmarx->XferAbortCallback = NULL;
|
|
800dbf8: 687b ldr r3, [r7, #4]
|
|
800dbfa: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800dbfc: 2200 movs r2, #0
|
|
800dbfe: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Abort DMA Rx Handle linked to SPI Peripheral */
|
|
if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
|
|
800dc00: 687b ldr r3, [r7, #4]
|
|
800dc02: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800dc04: 4618 mov r0, r3
|
|
800dc06: f7f9 f956 bl 8006eb6 <HAL_DMA_Abort>
|
|
800dc0a: 4603 mov r3, r0
|
|
800dc0c: 2b00 cmp r3, #0
|
|
800dc0e: d002 beq.n 800dc16 <HAL_SPI_Abort+0x176>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800dc10: 687b ldr r3, [r7, #4]
|
|
800dc12: 2240 movs r2, #64 @ 0x40
|
|
800dc14: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Disable peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800dc16: 687b ldr r3, [r7, #4]
|
|
800dc18: 681b ldr r3, [r3, #0]
|
|
800dc1a: 681a ldr r2, [r3, #0]
|
|
800dc1c: 687b ldr r3, [r7, #4]
|
|
800dc1e: 681b ldr r3, [r3, #0]
|
|
800dc20: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800dc24: 601a str r2, [r3, #0]
|
|
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
|
|
800dc26: f7f8 fea1 bl 800696c <HAL_GetTick>
|
|
800dc2a: 4603 mov r3, r0
|
|
800dc2c: 9300 str r3, [sp, #0]
|
|
800dc2e: 2364 movs r3, #100 @ 0x64
|
|
800dc30: 2200 movs r2, #0
|
|
800dc32: 2180 movs r1, #128 @ 0x80
|
|
800dc34: 6878 ldr r0, [r7, #4]
|
|
800dc36: f000 f953 bl 800dee0 <SPI_WaitFlagStateUntilTimeout>
|
|
800dc3a: 4603 mov r3, r0
|
|
800dc3c: 2b00 cmp r3, #0
|
|
800dc3e: d002 beq.n 800dc46 <HAL_SPI_Abort+0x1a6>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800dc40: 687b ldr r3, [r7, #4]
|
|
800dc42: 2240 movs r2, #64 @ 0x40
|
|
800dc44: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Empty the FRLVL fifo */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
|
|
800dc46: f7f8 fe91 bl 800696c <HAL_GetTick>
|
|
800dc4a: 4603 mov r3, r0
|
|
800dc4c: 9300 str r3, [sp, #0]
|
|
800dc4e: 2364 movs r3, #100 @ 0x64
|
|
800dc50: 2200 movs r2, #0
|
|
800dc52: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800dc56: 6878 ldr r0, [r7, #4]
|
|
800dc58: f000 f9ca bl 800dff0 <SPI_WaitFifoStateUntilTimeout>
|
|
800dc5c: 4603 mov r3, r0
|
|
800dc5e: 2b00 cmp r3, #0
|
|
800dc60: d002 beq.n 800dc68 <HAL_SPI_Abort+0x1c8>
|
|
HAL_GetTick()) != HAL_OK)
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800dc62: 687b ldr r3, [r7, #4]
|
|
800dc64: 2240 movs r2, #64 @ 0x40
|
|
800dc66: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Disable Rx DMA Request */
|
|
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
|
|
800dc68: 687b ldr r3, [r7, #4]
|
|
800dc6a: 681b ldr r3, [r3, #0]
|
|
800dc6c: 685a ldr r2, [r3, #4]
|
|
800dc6e: 687b ldr r3, [r7, #4]
|
|
800dc70: 681b ldr r3, [r3, #0]
|
|
800dc72: f022 0201 bic.w r2, r2, #1
|
|
800dc76: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
/* Reset Tx and Rx transfer counters */
|
|
hspi->RxXferCount = 0U;
|
|
800dc78: 687b ldr r3, [r7, #4]
|
|
800dc7a: 2200 movs r2, #0
|
|
800dc7c: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->TxXferCount = 0U;
|
|
800dc80: 687b ldr r3, [r7, #4]
|
|
800dc82: 2200 movs r2, #0
|
|
800dc84: 87da strh r2, [r3, #62] @ 0x3e
|
|
|
|
/* Check error during Abort procedure */
|
|
if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
|
|
800dc86: 687b ldr r3, [r7, #4]
|
|
800dc88: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800dc8a: 2b40 cmp r3, #64 @ 0x40
|
|
800dc8c: d102 bne.n 800dc94 <HAL_SPI_Abort+0x1f4>
|
|
{
|
|
/* return HAL_Error in case of error during Abort procedure */
|
|
errorcode = HAL_ERROR;
|
|
800dc8e: 2301 movs r3, #1
|
|
800dc90: 77fb strb r3, [r7, #31]
|
|
800dc92: e002 b.n 800dc9a <HAL_SPI_Abort+0x1fa>
|
|
}
|
|
else
|
|
{
|
|
/* Reset errorCode */
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
800dc94: 687b ldr r3, [r7, #4]
|
|
800dc96: 2200 movs r2, #0
|
|
800dc98: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Clear the Error flags in the SR register */
|
|
__HAL_SPI_CLEAR_OVRFLAG(hspi);
|
|
800dc9a: 2300 movs r3, #0
|
|
800dc9c: 613b str r3, [r7, #16]
|
|
800dc9e: 687b ldr r3, [r7, #4]
|
|
800dca0: 681b ldr r3, [r3, #0]
|
|
800dca2: 68db ldr r3, [r3, #12]
|
|
800dca4: 613b str r3, [r7, #16]
|
|
800dca6: 687b ldr r3, [r7, #4]
|
|
800dca8: 681b ldr r3, [r3, #0]
|
|
800dcaa: 689b ldr r3, [r3, #8]
|
|
800dcac: 613b str r3, [r7, #16]
|
|
800dcae: 693b ldr r3, [r7, #16]
|
|
__HAL_SPI_CLEAR_FREFLAG(hspi);
|
|
800dcb0: 2300 movs r3, #0
|
|
800dcb2: 60fb str r3, [r7, #12]
|
|
800dcb4: 687b ldr r3, [r7, #4]
|
|
800dcb6: 681b ldr r3, [r3, #0]
|
|
800dcb8: 689b ldr r3, [r3, #8]
|
|
800dcba: 60fb str r3, [r7, #12]
|
|
800dcbc: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Restore hspi->state to ready */
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800dcbe: 687b ldr r3, [r7, #4]
|
|
800dcc0: 2201 movs r2, #1
|
|
800dcc2: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
return errorcode;
|
|
800dcc6: 7ffb ldrb r3, [r7, #31]
|
|
}
|
|
800dcc8: 4618 mov r0, r3
|
|
800dcca: 3720 adds r7, #32
|
|
800dccc: 46bd mov sp, r7
|
|
800dcce: bd80 pop {r7, pc}
|
|
800dcd0: 2000000c .word 0x2000000c
|
|
800dcd4: 057619f1 .word 0x057619f1
|
|
800dcd8: 0800e319 .word 0x0800e319
|
|
800dcdc: 0800e259 .word 0x0800e259
|
|
|
|
0800dce0 <HAL_SPI_RxCpltCallback>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800dce0: b480 push {r7}
|
|
800dce2: b083 sub sp, #12
|
|
800dce4: af00 add r7, sp, #0
|
|
800dce6: 6078 str r0, [r7, #4]
|
|
UNUSED(hspi);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_SPI_RxCpltCallback should be implemented in the user file
|
|
*/
|
|
}
|
|
800dce8: bf00 nop
|
|
800dcea: 370c adds r7, #12
|
|
800dcec: 46bd mov sp, r7
|
|
800dcee: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dcf2: 4770 bx lr
|
|
|
|
0800dcf4 <HAL_SPI_RxHalfCpltCallback>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800dcf4: b480 push {r7}
|
|
800dcf6: b083 sub sp, #12
|
|
800dcf8: af00 add r7, sp, #0
|
|
800dcfa: 6078 str r0, [r7, #4]
|
|
UNUSED(hspi);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
|
|
*/
|
|
}
|
|
800dcfc: bf00 nop
|
|
800dcfe: 370c adds r7, #12
|
|
800dd00: 46bd mov sp, r7
|
|
800dd02: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dd06: 4770 bx lr
|
|
|
|
0800dd08 <HAL_SPI_TxRxHalfCpltCallback>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800dd08: b480 push {r7}
|
|
800dd0a: b083 sub sp, #12
|
|
800dd0c: af00 add r7, sp, #0
|
|
800dd0e: 6078 str r0, [r7, #4]
|
|
UNUSED(hspi);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
|
|
*/
|
|
}
|
|
800dd10: bf00 nop
|
|
800dd12: 370c adds r7, #12
|
|
800dd14: 46bd mov sp, r7
|
|
800dd16: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dd1a: 4770 bx lr
|
|
|
|
0800dd1c <HAL_SPI_ErrorCallback>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800dd1c: b480 push {r7}
|
|
800dd1e: b083 sub sp, #12
|
|
800dd20: af00 add r7, sp, #0
|
|
800dd22: 6078 str r0, [r7, #4]
|
|
the HAL_SPI_ErrorCallback should be implemented in the user file
|
|
*/
|
|
/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
|
|
and user can use HAL_SPI_GetError() API to check the latest error occurred
|
|
*/
|
|
}
|
|
800dd24: bf00 nop
|
|
800dd26: 370c adds r7, #12
|
|
800dd28: 46bd mov sp, r7
|
|
800dd2a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dd2e: 4770 bx lr
|
|
|
|
0800dd30 <SPI_DMAReceiveCplt>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800dd30: b580 push {r7, lr}
|
|
800dd32: b084 sub sp, #16
|
|
800dd34: af00 add r7, sp, #0
|
|
800dd36: 6078 str r0, [r7, #4]
|
|
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
800dd38: 687b ldr r3, [r7, #4]
|
|
800dd3a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800dd3c: 60fb str r3, [r7, #12]
|
|
__IO uint8_t *ptmpreg8;
|
|
__IO uint8_t tmpreg8 = 0;
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
800dd3e: f7f8 fe15 bl 800696c <HAL_GetTick>
|
|
800dd42: 60b8 str r0, [r7, #8]
|
|
|
|
/* DMA Normal Mode */
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
|
|
800dd44: 687b ldr r3, [r7, #4]
|
|
800dd46: 681b ldr r3, [r3, #0]
|
|
800dd48: 681b ldr r3, [r3, #0]
|
|
800dd4a: f003 0320 and.w r3, r3, #32
|
|
800dd4e: 2b20 cmp r3, #32
|
|
800dd50: d03c beq.n 800ddcc <SPI_DMAReceiveCplt+0x9c>
|
|
{
|
|
/* Disable ERR interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
|
|
800dd52: 68fb ldr r3, [r7, #12]
|
|
800dd54: 681b ldr r3, [r3, #0]
|
|
800dd56: 685a ldr r2, [r3, #4]
|
|
800dd58: 68fb ldr r3, [r7, #12]
|
|
800dd5a: 681b ldr r3, [r3, #0]
|
|
800dd5c: f022 0220 bic.w r2, r2, #32
|
|
800dd60: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check if we are in Master RX 2 line mode */
|
|
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
|
|
800dd62: 68fb ldr r3, [r7, #12]
|
|
800dd64: 689b ldr r3, [r3, #8]
|
|
800dd66: 2b00 cmp r3, #0
|
|
800dd68: d10d bne.n 800dd86 <SPI_DMAReceiveCplt+0x56>
|
|
800dd6a: 68fb ldr r3, [r7, #12]
|
|
800dd6c: 685b ldr r3, [r3, #4]
|
|
800dd6e: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800dd72: d108 bne.n 800dd86 <SPI_DMAReceiveCplt+0x56>
|
|
{
|
|
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
|
|
800dd74: 68fb ldr r3, [r7, #12]
|
|
800dd76: 681b ldr r3, [r3, #0]
|
|
800dd78: 685a ldr r2, [r3, #4]
|
|
800dd7a: 68fb ldr r3, [r7, #12]
|
|
800dd7c: 681b ldr r3, [r3, #0]
|
|
800dd7e: f022 0203 bic.w r2, r2, #3
|
|
800dd82: 605a str r2, [r3, #4]
|
|
800dd84: e007 b.n 800dd96 <SPI_DMAReceiveCplt+0x66>
|
|
}
|
|
else
|
|
{
|
|
/* Normal case */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
|
|
800dd86: 68fb ldr r3, [r7, #12]
|
|
800dd88: 681b ldr r3, [r3, #0]
|
|
800dd8a: 685a ldr r2, [r3, #4]
|
|
800dd8c: 68fb ldr r3, [r7, #12]
|
|
800dd8e: 681b ldr r3, [r3, #0]
|
|
800dd90: f022 0201 bic.w r2, r2, #1
|
|
800dd94: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
|
|
800dd96: 68ba ldr r2, [r7, #8]
|
|
800dd98: 2164 movs r1, #100 @ 0x64
|
|
800dd9a: 68f8 ldr r0, [r7, #12]
|
|
800dd9c: f000 f9be bl 800e11c <SPI_EndRxTransaction>
|
|
800dda0: 4603 mov r3, r0
|
|
800dda2: 2b00 cmp r3, #0
|
|
800dda4: d002 beq.n 800ddac <SPI_DMAReceiveCplt+0x7c>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
|
|
800dda6: 68fb ldr r3, [r7, #12]
|
|
800dda8: 2220 movs r2, #32
|
|
800ddaa: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
hspi->RxXferCount = 0U;
|
|
800ddac: 68fb ldr r3, [r7, #12]
|
|
800ddae: 2200 movs r2, #0
|
|
800ddb0: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800ddb4: 68fb ldr r3, [r7, #12]
|
|
800ddb6: 2201 movs r2, #1
|
|
800ddb8: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
|
|
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
800ddbc: 68fb ldr r3, [r7, #12]
|
|
800ddbe: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800ddc0: 2b00 cmp r3, #0
|
|
800ddc2: d003 beq.n 800ddcc <SPI_DMAReceiveCplt+0x9c>
|
|
{
|
|
/* Call user error callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->ErrorCallback(hspi);
|
|
#else
|
|
HAL_SPI_ErrorCallback(hspi);
|
|
800ddc4: 68f8 ldr r0, [r7, #12]
|
|
800ddc6: f7ff ffa9 bl 800dd1c <HAL_SPI_ErrorCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
return;
|
|
800ddca: e002 b.n 800ddd2 <SPI_DMAReceiveCplt+0xa2>
|
|
}
|
|
/* Call user Rx complete callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->RxCpltCallback(hspi);
|
|
#else
|
|
HAL_SPI_RxCpltCallback(hspi);
|
|
800ddcc: 68f8 ldr r0, [r7, #12]
|
|
800ddce: f7ff ff87 bl 800dce0 <HAL_SPI_RxCpltCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
800ddd2: 3710 adds r7, #16
|
|
800ddd4: 46bd mov sp, r7
|
|
800ddd6: bd80 pop {r7, pc}
|
|
|
|
0800ddd8 <SPI_DMATransmitReceiveCplt>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800ddd8: b580 push {r7, lr}
|
|
800ddda: b084 sub sp, #16
|
|
800dddc: af00 add r7, sp, #0
|
|
800ddde: 6078 str r0, [r7, #4]
|
|
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
800dde0: 687b ldr r3, [r7, #4]
|
|
800dde2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800dde4: 60fb str r3, [r7, #12]
|
|
__IO uint8_t *ptmpreg8;
|
|
__IO uint8_t tmpreg8 = 0;
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
800dde6: f7f8 fdc1 bl 800696c <HAL_GetTick>
|
|
800ddea: 60b8 str r0, [r7, #8]
|
|
|
|
/* DMA Normal Mode */
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
|
|
800ddec: 687b ldr r3, [r7, #4]
|
|
800ddee: 681b ldr r3, [r3, #0]
|
|
800ddf0: 681b ldr r3, [r3, #0]
|
|
800ddf2: f003 0320 and.w r3, r3, #32
|
|
800ddf6: 2b20 cmp r3, #32
|
|
800ddf8: d030 beq.n 800de5c <SPI_DMATransmitReceiveCplt+0x84>
|
|
{
|
|
/* Disable ERR interrupt */
|
|
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
|
|
800ddfa: 68fb ldr r3, [r7, #12]
|
|
800ddfc: 681b ldr r3, [r3, #0]
|
|
800ddfe: 685a ldr r2, [r3, #4]
|
|
800de00: 68fb ldr r3, [r7, #12]
|
|
800de02: 681b ldr r3, [r3, #0]
|
|
800de04: f022 0220 bic.w r2, r2, #32
|
|
800de08: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
|
|
800de0a: 68ba ldr r2, [r7, #8]
|
|
800de0c: 2164 movs r1, #100 @ 0x64
|
|
800de0e: 68f8 ldr r0, [r7, #12]
|
|
800de10: f000 f9dc bl 800e1cc <SPI_EndRxTxTransaction>
|
|
800de14: 4603 mov r3, r0
|
|
800de16: 2b00 cmp r3, #0
|
|
800de18: d005 beq.n 800de26 <SPI_DMATransmitReceiveCplt+0x4e>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
800de1a: 68fb ldr r3, [r7, #12]
|
|
800de1c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800de1e: f043 0220 orr.w r2, r3, #32
|
|
800de22: 68fb ldr r3, [r7, #12]
|
|
800de24: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Disable Rx/Tx DMA Request */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
|
|
800de26: 68fb ldr r3, [r7, #12]
|
|
800de28: 681b ldr r3, [r3, #0]
|
|
800de2a: 685a ldr r2, [r3, #4]
|
|
800de2c: 68fb ldr r3, [r7, #12]
|
|
800de2e: 681b ldr r3, [r3, #0]
|
|
800de30: f022 0203 bic.w r2, r2, #3
|
|
800de34: 605a str r2, [r3, #4]
|
|
|
|
hspi->TxXferCount = 0U;
|
|
800de36: 68fb ldr r3, [r7, #12]
|
|
800de38: 2200 movs r2, #0
|
|
800de3a: 87da strh r2, [r3, #62] @ 0x3e
|
|
hspi->RxXferCount = 0U;
|
|
800de3c: 68fb ldr r3, [r7, #12]
|
|
800de3e: 2200 movs r2, #0
|
|
800de40: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800de44: 68fb ldr r3, [r7, #12]
|
|
800de46: 2201 movs r2, #1
|
|
800de48: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
|
|
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
800de4c: 68fb ldr r3, [r7, #12]
|
|
800de4e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800de50: 2b00 cmp r3, #0
|
|
800de52: d003 beq.n 800de5c <SPI_DMATransmitReceiveCplt+0x84>
|
|
{
|
|
/* Call user error callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->ErrorCallback(hspi);
|
|
#else
|
|
HAL_SPI_ErrorCallback(hspi);
|
|
800de54: 68f8 ldr r0, [r7, #12]
|
|
800de56: f7ff ff61 bl 800dd1c <HAL_SPI_ErrorCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
return;
|
|
800de5a: e002 b.n 800de62 <SPI_DMATransmitReceiveCplt+0x8a>
|
|
}
|
|
/* Call user TxRx complete callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->TxRxCpltCallback(hspi);
|
|
#else
|
|
HAL_SPI_TxRxCpltCallback(hspi);
|
|
800de5c: 68f8 ldr r0, [r7, #12]
|
|
800de5e: f7f7 fa8f bl 8005380 <HAL_SPI_TxRxCpltCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
800de62: 3710 adds r7, #16
|
|
800de64: 46bd mov sp, r7
|
|
800de66: bd80 pop {r7, pc}
|
|
|
|
0800de68 <SPI_DMAHalfReceiveCplt>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800de68: b580 push {r7, lr}
|
|
800de6a: b084 sub sp, #16
|
|
800de6c: af00 add r7, sp, #0
|
|
800de6e: 6078 str r0, [r7, #4]
|
|
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
800de70: 687b ldr r3, [r7, #4]
|
|
800de72: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800de74: 60fb str r3, [r7, #12]
|
|
|
|
/* Call user Rx half complete callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->RxHalfCpltCallback(hspi);
|
|
#else
|
|
HAL_SPI_RxHalfCpltCallback(hspi);
|
|
800de76: 68f8 ldr r0, [r7, #12]
|
|
800de78: f7ff ff3c bl 800dcf4 <HAL_SPI_RxHalfCpltCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
800de7c: bf00 nop
|
|
800de7e: 3710 adds r7, #16
|
|
800de80: 46bd mov sp, r7
|
|
800de82: bd80 pop {r7, pc}
|
|
|
|
0800de84 <SPI_DMAHalfTransmitReceiveCplt>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800de84: b580 push {r7, lr}
|
|
800de86: b084 sub sp, #16
|
|
800de88: af00 add r7, sp, #0
|
|
800de8a: 6078 str r0, [r7, #4]
|
|
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
800de8c: 687b ldr r3, [r7, #4]
|
|
800de8e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800de90: 60fb str r3, [r7, #12]
|
|
|
|
/* Call user TxRx half complete callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->TxRxHalfCpltCallback(hspi);
|
|
#else
|
|
HAL_SPI_TxRxHalfCpltCallback(hspi);
|
|
800de92: 68f8 ldr r0, [r7, #12]
|
|
800de94: f7ff ff38 bl 800dd08 <HAL_SPI_TxRxHalfCpltCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
800de98: bf00 nop
|
|
800de9a: 3710 adds r7, #16
|
|
800de9c: 46bd mov sp, r7
|
|
800de9e: bd80 pop {r7, pc}
|
|
|
|
0800dea0 <SPI_DMAError>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800dea0: b580 push {r7, lr}
|
|
800dea2: b084 sub sp, #16
|
|
800dea4: af00 add r7, sp, #0
|
|
800dea6: 6078 str r0, [r7, #4]
|
|
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
|
|
800dea8: 687b ldr r3, [r7, #4]
|
|
800deaa: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800deac: 60fb str r3, [r7, #12]
|
|
|
|
/* Stop the disable DMA transfer on SPI side */
|
|
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
|
|
800deae: 68fb ldr r3, [r7, #12]
|
|
800deb0: 681b ldr r3, [r3, #0]
|
|
800deb2: 685a ldr r2, [r3, #4]
|
|
800deb4: 68fb ldr r3, [r7, #12]
|
|
800deb6: 681b ldr r3, [r3, #0]
|
|
800deb8: f022 0203 bic.w r2, r2, #3
|
|
800debc: 605a str r2, [r3, #4]
|
|
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
|
|
800debe: 68fb ldr r3, [r7, #12]
|
|
800dec0: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800dec2: f043 0210 orr.w r2, r3, #16
|
|
800dec6: 68fb ldr r3, [r7, #12]
|
|
800dec8: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800deca: 68fb ldr r3, [r7, #12]
|
|
800decc: 2201 movs r2, #1
|
|
800dece: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Call user error callback */
|
|
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
hspi->ErrorCallback(hspi);
|
|
#else
|
|
HAL_SPI_ErrorCallback(hspi);
|
|
800ded2: 68f8 ldr r0, [r7, #12]
|
|
800ded4: f7ff ff22 bl 800dd1c <HAL_SPI_ErrorCallback>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
800ded8: bf00 nop
|
|
800deda: 3710 adds r7, #16
|
|
800dedc: 46bd mov sp, r7
|
|
800dede: bd80 pop {r7, pc}
|
|
|
|
0800dee0 <SPI_WaitFlagStateUntilTimeout>:
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800dee0: b580 push {r7, lr}
|
|
800dee2: b088 sub sp, #32
|
|
800dee4: af00 add r7, sp, #0
|
|
800dee6: 60f8 str r0, [r7, #12]
|
|
800dee8: 60b9 str r1, [r7, #8]
|
|
800deea: 603b str r3, [r7, #0]
|
|
800deec: 4613 mov r3, r2
|
|
800deee: 71fb strb r3, [r7, #7]
|
|
__IO uint32_t count;
|
|
uint32_t tmp_timeout;
|
|
uint32_t tmp_tickstart;
|
|
|
|
/* Adjust Timeout value in case of end of transfer */
|
|
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
|
800def0: f7f8 fd3c bl 800696c <HAL_GetTick>
|
|
800def4: 4602 mov r2, r0
|
|
800def6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800def8: 1a9b subs r3, r3, r2
|
|
800defa: 683a ldr r2, [r7, #0]
|
|
800defc: 4413 add r3, r2
|
|
800defe: 61fb str r3, [r7, #28]
|
|
tmp_tickstart = HAL_GetTick();
|
|
800df00: f7f8 fd34 bl 800696c <HAL_GetTick>
|
|
800df04: 61b8 str r0, [r7, #24]
|
|
|
|
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
|
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
|
|
800df06: 4b39 ldr r3, [pc, #228] @ (800dfec <SPI_WaitFlagStateUntilTimeout+0x10c>)
|
|
800df08: 681b ldr r3, [r3, #0]
|
|
800df0a: 015b lsls r3, r3, #5
|
|
800df0c: 0d1b lsrs r3, r3, #20
|
|
800df0e: 69fa ldr r2, [r7, #28]
|
|
800df10: fb02 f303 mul.w r3, r2, r3
|
|
800df14: 617b str r3, [r7, #20]
|
|
|
|
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
|
800df16: e055 b.n 800dfc4 <SPI_WaitFlagStateUntilTimeout+0xe4>
|
|
{
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800df18: 683b ldr r3, [r7, #0]
|
|
800df1a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800df1e: d051 beq.n 800dfc4 <SPI_WaitFlagStateUntilTimeout+0xe4>
|
|
{
|
|
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
|
800df20: f7f8 fd24 bl 800696c <HAL_GetTick>
|
|
800df24: 4602 mov r2, r0
|
|
800df26: 69bb ldr r3, [r7, #24]
|
|
800df28: 1ad3 subs r3, r2, r3
|
|
800df2a: 69fa ldr r2, [r7, #28]
|
|
800df2c: 429a cmp r2, r3
|
|
800df2e: d902 bls.n 800df36 <SPI_WaitFlagStateUntilTimeout+0x56>
|
|
800df30: 69fb ldr r3, [r7, #28]
|
|
800df32: 2b00 cmp r3, #0
|
|
800df34: d13d bne.n 800dfb2 <SPI_WaitFlagStateUntilTimeout+0xd2>
|
|
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
|
on both master and slave sides in order to resynchronize the master
|
|
and slave for their respective CRC calculation */
|
|
|
|
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
|
800df36: 68fb ldr r3, [r7, #12]
|
|
800df38: 681b ldr r3, [r3, #0]
|
|
800df3a: 685a ldr r2, [r3, #4]
|
|
800df3c: 68fb ldr r3, [r7, #12]
|
|
800df3e: 681b ldr r3, [r3, #0]
|
|
800df40: f022 02e0 bic.w r2, r2, #224 @ 0xe0
|
|
800df44: 605a str r2, [r3, #4]
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
800df46: 68fb ldr r3, [r7, #12]
|
|
800df48: 685b ldr r3, [r3, #4]
|
|
800df4a: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800df4e: d111 bne.n 800df74 <SPI_WaitFlagStateUntilTimeout+0x94>
|
|
800df50: 68fb ldr r3, [r7, #12]
|
|
800df52: 689b ldr r3, [r3, #8]
|
|
800df54: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800df58: d004 beq.n 800df64 <SPI_WaitFlagStateUntilTimeout+0x84>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
800df5a: 68fb ldr r3, [r7, #12]
|
|
800df5c: 689b ldr r3, [r3, #8]
|
|
800df5e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800df62: d107 bne.n 800df74 <SPI_WaitFlagStateUntilTimeout+0x94>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800df64: 68fb ldr r3, [r7, #12]
|
|
800df66: 681b ldr r3, [r3, #0]
|
|
800df68: 681a ldr r2, [r3, #0]
|
|
800df6a: 68fb ldr r3, [r7, #12]
|
|
800df6c: 681b ldr r3, [r3, #0]
|
|
800df6e: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800df72: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Reset CRC Calculation */
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
800df74: 68fb ldr r3, [r7, #12]
|
|
800df76: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800df78: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
800df7c: d10f bne.n 800df9e <SPI_WaitFlagStateUntilTimeout+0xbe>
|
|
{
|
|
SPI_RESET_CRC(hspi);
|
|
800df7e: 68fb ldr r3, [r7, #12]
|
|
800df80: 681b ldr r3, [r3, #0]
|
|
800df82: 681a ldr r2, [r3, #0]
|
|
800df84: 68fb ldr r3, [r7, #12]
|
|
800df86: 681b ldr r3, [r3, #0]
|
|
800df88: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
800df8c: 601a str r2, [r3, #0]
|
|
800df8e: 68fb ldr r3, [r7, #12]
|
|
800df90: 681b ldr r3, [r3, #0]
|
|
800df92: 681a ldr r2, [r3, #0]
|
|
800df94: 68fb ldr r3, [r7, #12]
|
|
800df96: 681b ldr r3, [r3, #0]
|
|
800df98: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
800df9c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800df9e: 68fb ldr r3, [r7, #12]
|
|
800dfa0: 2201 movs r2, #1
|
|
800dfa2: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
800dfa6: 68fb ldr r3, [r7, #12]
|
|
800dfa8: 2200 movs r2, #0
|
|
800dfaa: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
return HAL_TIMEOUT;
|
|
800dfae: 2303 movs r3, #3
|
|
800dfb0: e018 b.n 800dfe4 <SPI_WaitFlagStateUntilTimeout+0x104>
|
|
}
|
|
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
|
if (count == 0U)
|
|
800dfb2: 697b ldr r3, [r7, #20]
|
|
800dfb4: 2b00 cmp r3, #0
|
|
800dfb6: d102 bne.n 800dfbe <SPI_WaitFlagStateUntilTimeout+0xde>
|
|
{
|
|
tmp_timeout = 0U;
|
|
800dfb8: 2300 movs r3, #0
|
|
800dfba: 61fb str r3, [r7, #28]
|
|
800dfbc: e002 b.n 800dfc4 <SPI_WaitFlagStateUntilTimeout+0xe4>
|
|
}
|
|
else
|
|
{
|
|
count--;
|
|
800dfbe: 697b ldr r3, [r7, #20]
|
|
800dfc0: 3b01 subs r3, #1
|
|
800dfc2: 617b str r3, [r7, #20]
|
|
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
|
800dfc4: 68fb ldr r3, [r7, #12]
|
|
800dfc6: 681b ldr r3, [r3, #0]
|
|
800dfc8: 689a ldr r2, [r3, #8]
|
|
800dfca: 68bb ldr r3, [r7, #8]
|
|
800dfcc: 4013 ands r3, r2
|
|
800dfce: 68ba ldr r2, [r7, #8]
|
|
800dfd0: 429a cmp r2, r3
|
|
800dfd2: bf0c ite eq
|
|
800dfd4: 2301 moveq r3, #1
|
|
800dfd6: 2300 movne r3, #0
|
|
800dfd8: b2db uxtb r3, r3
|
|
800dfda: 461a mov r2, r3
|
|
800dfdc: 79fb ldrb r3, [r7, #7]
|
|
800dfde: 429a cmp r2, r3
|
|
800dfe0: d19a bne.n 800df18 <SPI_WaitFlagStateUntilTimeout+0x38>
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800dfe2: 2300 movs r3, #0
|
|
}
|
|
800dfe4: 4618 mov r0, r3
|
|
800dfe6: 3720 adds r7, #32
|
|
800dfe8: 46bd mov sp, r7
|
|
800dfea: bd80 pop {r7, pc}
|
|
800dfec: 2000000c .word 0x2000000c
|
|
|
|
0800dff0 <SPI_WaitFifoStateUntilTimeout>:
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800dff0: b580 push {r7, lr}
|
|
800dff2: b08a sub sp, #40 @ 0x28
|
|
800dff4: af00 add r7, sp, #0
|
|
800dff6: 60f8 str r0, [r7, #12]
|
|
800dff8: 60b9 str r1, [r7, #8]
|
|
800dffa: 607a str r2, [r7, #4]
|
|
800dffc: 603b str r3, [r7, #0]
|
|
__IO uint32_t count;
|
|
uint32_t tmp_timeout;
|
|
uint32_t tmp_tickstart;
|
|
__IO const uint8_t *ptmpreg8;
|
|
__IO uint8_t tmpreg8 = 0;
|
|
800dffe: 2300 movs r3, #0
|
|
800e000: 75fb strb r3, [r7, #23]
|
|
|
|
/* Adjust Timeout value in case of end of transfer */
|
|
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
|
800e002: f7f8 fcb3 bl 800696c <HAL_GetTick>
|
|
800e006: 4602 mov r2, r0
|
|
800e008: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800e00a: 1a9b subs r3, r3, r2
|
|
800e00c: 683a ldr r2, [r7, #0]
|
|
800e00e: 4413 add r3, r2
|
|
800e010: 627b str r3, [r7, #36] @ 0x24
|
|
tmp_tickstart = HAL_GetTick();
|
|
800e012: f7f8 fcab bl 800696c <HAL_GetTick>
|
|
800e016: 6238 str r0, [r7, #32]
|
|
|
|
/* Initialize the 8bit temporary pointer */
|
|
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
|
800e018: 68fb ldr r3, [r7, #12]
|
|
800e01a: 681b ldr r3, [r3, #0]
|
|
800e01c: 330c adds r3, #12
|
|
800e01e: 61fb str r3, [r7, #28]
|
|
|
|
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
|
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
|
|
800e020: 4b3d ldr r3, [pc, #244] @ (800e118 <SPI_WaitFifoStateUntilTimeout+0x128>)
|
|
800e022: 681a ldr r2, [r3, #0]
|
|
800e024: 4613 mov r3, r2
|
|
800e026: 009b lsls r3, r3, #2
|
|
800e028: 4413 add r3, r2
|
|
800e02a: 00da lsls r2, r3, #3
|
|
800e02c: 1ad3 subs r3, r2, r3
|
|
800e02e: 0d1b lsrs r3, r3, #20
|
|
800e030: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800e032: fb02 f303 mul.w r3, r2, r3
|
|
800e036: 61bb str r3, [r7, #24]
|
|
|
|
while ((hspi->Instance->SR & Fifo) != State)
|
|
800e038: e061 b.n 800e0fe <SPI_WaitFifoStateUntilTimeout+0x10e>
|
|
{
|
|
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
|
|
800e03a: 68bb ldr r3, [r7, #8]
|
|
800e03c: f5b3 6fc0 cmp.w r3, #1536 @ 0x600
|
|
800e040: d107 bne.n 800e052 <SPI_WaitFifoStateUntilTimeout+0x62>
|
|
800e042: 687b ldr r3, [r7, #4]
|
|
800e044: 2b00 cmp r3, #0
|
|
800e046: d104 bne.n 800e052 <SPI_WaitFifoStateUntilTimeout+0x62>
|
|
{
|
|
/* Flush Data Register by a blank read */
|
|
tmpreg8 = *ptmpreg8;
|
|
800e048: 69fb ldr r3, [r7, #28]
|
|
800e04a: 781b ldrb r3, [r3, #0]
|
|
800e04c: b2db uxtb r3, r3
|
|
800e04e: 75fb strb r3, [r7, #23]
|
|
/* To avoid GCC warning */
|
|
UNUSED(tmpreg8);
|
|
800e050: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800e052: 683b ldr r3, [r7, #0]
|
|
800e054: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800e058: d051 beq.n 800e0fe <SPI_WaitFifoStateUntilTimeout+0x10e>
|
|
{
|
|
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
|
800e05a: f7f8 fc87 bl 800696c <HAL_GetTick>
|
|
800e05e: 4602 mov r2, r0
|
|
800e060: 6a3b ldr r3, [r7, #32]
|
|
800e062: 1ad3 subs r3, r2, r3
|
|
800e064: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800e066: 429a cmp r2, r3
|
|
800e068: d902 bls.n 800e070 <SPI_WaitFifoStateUntilTimeout+0x80>
|
|
800e06a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800e06c: 2b00 cmp r3, #0
|
|
800e06e: d13d bne.n 800e0ec <SPI_WaitFifoStateUntilTimeout+0xfc>
|
|
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
|
on both master and slave sides in order to resynchronize the master
|
|
and slave for their respective CRC calculation */
|
|
|
|
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
|
800e070: 68fb ldr r3, [r7, #12]
|
|
800e072: 681b ldr r3, [r3, #0]
|
|
800e074: 685a ldr r2, [r3, #4]
|
|
800e076: 68fb ldr r3, [r7, #12]
|
|
800e078: 681b ldr r3, [r3, #0]
|
|
800e07a: f022 02e0 bic.w r2, r2, #224 @ 0xe0
|
|
800e07e: 605a str r2, [r3, #4]
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
800e080: 68fb ldr r3, [r7, #12]
|
|
800e082: 685b ldr r3, [r3, #4]
|
|
800e084: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800e088: d111 bne.n 800e0ae <SPI_WaitFifoStateUntilTimeout+0xbe>
|
|
800e08a: 68fb ldr r3, [r7, #12]
|
|
800e08c: 689b ldr r3, [r3, #8]
|
|
800e08e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800e092: d004 beq.n 800e09e <SPI_WaitFifoStateUntilTimeout+0xae>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
800e094: 68fb ldr r3, [r7, #12]
|
|
800e096: 689b ldr r3, [r3, #8]
|
|
800e098: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800e09c: d107 bne.n 800e0ae <SPI_WaitFifoStateUntilTimeout+0xbe>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800e09e: 68fb ldr r3, [r7, #12]
|
|
800e0a0: 681b ldr r3, [r3, #0]
|
|
800e0a2: 681a ldr r2, [r3, #0]
|
|
800e0a4: 68fb ldr r3, [r7, #12]
|
|
800e0a6: 681b ldr r3, [r3, #0]
|
|
800e0a8: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800e0ac: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Reset CRC Calculation */
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
800e0ae: 68fb ldr r3, [r7, #12]
|
|
800e0b0: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800e0b2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
800e0b6: d10f bne.n 800e0d8 <SPI_WaitFifoStateUntilTimeout+0xe8>
|
|
{
|
|
SPI_RESET_CRC(hspi);
|
|
800e0b8: 68fb ldr r3, [r7, #12]
|
|
800e0ba: 681b ldr r3, [r3, #0]
|
|
800e0bc: 681a ldr r2, [r3, #0]
|
|
800e0be: 68fb ldr r3, [r7, #12]
|
|
800e0c0: 681b ldr r3, [r3, #0]
|
|
800e0c2: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
800e0c6: 601a str r2, [r3, #0]
|
|
800e0c8: 68fb ldr r3, [r7, #12]
|
|
800e0ca: 681b ldr r3, [r3, #0]
|
|
800e0cc: 681a ldr r2, [r3, #0]
|
|
800e0ce: 68fb ldr r3, [r7, #12]
|
|
800e0d0: 681b ldr r3, [r3, #0]
|
|
800e0d2: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
800e0d6: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800e0d8: 68fb ldr r3, [r7, #12]
|
|
800e0da: 2201 movs r2, #1
|
|
800e0dc: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
800e0e0: 68fb ldr r3, [r7, #12]
|
|
800e0e2: 2200 movs r2, #0
|
|
800e0e4: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
return HAL_TIMEOUT;
|
|
800e0e8: 2303 movs r3, #3
|
|
800e0ea: e011 b.n 800e110 <SPI_WaitFifoStateUntilTimeout+0x120>
|
|
}
|
|
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
|
if (count == 0U)
|
|
800e0ec: 69bb ldr r3, [r7, #24]
|
|
800e0ee: 2b00 cmp r3, #0
|
|
800e0f0: d102 bne.n 800e0f8 <SPI_WaitFifoStateUntilTimeout+0x108>
|
|
{
|
|
tmp_timeout = 0U;
|
|
800e0f2: 2300 movs r3, #0
|
|
800e0f4: 627b str r3, [r7, #36] @ 0x24
|
|
800e0f6: e002 b.n 800e0fe <SPI_WaitFifoStateUntilTimeout+0x10e>
|
|
}
|
|
else
|
|
{
|
|
count--;
|
|
800e0f8: 69bb ldr r3, [r7, #24]
|
|
800e0fa: 3b01 subs r3, #1
|
|
800e0fc: 61bb str r3, [r7, #24]
|
|
while ((hspi->Instance->SR & Fifo) != State)
|
|
800e0fe: 68fb ldr r3, [r7, #12]
|
|
800e100: 681b ldr r3, [r3, #0]
|
|
800e102: 689a ldr r2, [r3, #8]
|
|
800e104: 68bb ldr r3, [r7, #8]
|
|
800e106: 4013 ands r3, r2
|
|
800e108: 687a ldr r2, [r7, #4]
|
|
800e10a: 429a cmp r2, r3
|
|
800e10c: d195 bne.n 800e03a <SPI_WaitFifoStateUntilTimeout+0x4a>
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800e10e: 2300 movs r3, #0
|
|
}
|
|
800e110: 4618 mov r0, r3
|
|
800e112: 3728 adds r7, #40 @ 0x28
|
|
800e114: 46bd mov sp, r7
|
|
800e116: bd80 pop {r7, pc}
|
|
800e118: 2000000c .word 0x2000000c
|
|
|
|
0800e11c <SPI_EndRxTransaction>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800e11c: b580 push {r7, lr}
|
|
800e11e: b086 sub sp, #24
|
|
800e120: af02 add r7, sp, #8
|
|
800e122: 60f8 str r0, [r7, #12]
|
|
800e124: 60b9 str r1, [r7, #8]
|
|
800e126: 607a str r2, [r7, #4]
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
800e128: 68fb ldr r3, [r7, #12]
|
|
800e12a: 685b ldr r3, [r3, #4]
|
|
800e12c: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800e130: d111 bne.n 800e156 <SPI_EndRxTransaction+0x3a>
|
|
800e132: 68fb ldr r3, [r7, #12]
|
|
800e134: 689b ldr r3, [r3, #8]
|
|
800e136: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800e13a: d004 beq.n 800e146 <SPI_EndRxTransaction+0x2a>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
800e13c: 68fb ldr r3, [r7, #12]
|
|
800e13e: 689b ldr r3, [r3, #8]
|
|
800e140: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800e144: d107 bne.n 800e156 <SPI_EndRxTransaction+0x3a>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800e146: 68fb ldr r3, [r7, #12]
|
|
800e148: 681b ldr r3, [r3, #0]
|
|
800e14a: 681a ldr r2, [r3, #0]
|
|
800e14c: 68fb ldr r3, [r7, #12]
|
|
800e14e: 681b ldr r3, [r3, #0]
|
|
800e150: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800e154: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
|
|
800e156: 687b ldr r3, [r7, #4]
|
|
800e158: 9300 str r3, [sp, #0]
|
|
800e15a: 68bb ldr r3, [r7, #8]
|
|
800e15c: 2200 movs r2, #0
|
|
800e15e: 2180 movs r1, #128 @ 0x80
|
|
800e160: 68f8 ldr r0, [r7, #12]
|
|
800e162: f7ff febd bl 800dee0 <SPI_WaitFlagStateUntilTimeout>
|
|
800e166: 4603 mov r3, r0
|
|
800e168: 2b00 cmp r3, #0
|
|
800e16a: d007 beq.n 800e17c <SPI_EndRxTransaction+0x60>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
800e16c: 68fb ldr r3, [r7, #12]
|
|
800e16e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800e170: f043 0220 orr.w r2, r3, #32
|
|
800e174: 68fb ldr r3, [r7, #12]
|
|
800e176: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
800e178: 2303 movs r3, #3
|
|
800e17a: e023 b.n 800e1c4 <SPI_EndRxTransaction+0xa8>
|
|
}
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
800e17c: 68fb ldr r3, [r7, #12]
|
|
800e17e: 685b ldr r3, [r3, #4]
|
|
800e180: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800e184: d11d bne.n 800e1c2 <SPI_EndRxTransaction+0xa6>
|
|
800e186: 68fb ldr r3, [r7, #12]
|
|
800e188: 689b ldr r3, [r3, #8]
|
|
800e18a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800e18e: d004 beq.n 800e19a <SPI_EndRxTransaction+0x7e>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
800e190: 68fb ldr r3, [r7, #12]
|
|
800e192: 689b ldr r3, [r3, #8]
|
|
800e194: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800e198: d113 bne.n 800e1c2 <SPI_EndRxTransaction+0xa6>
|
|
{
|
|
/* Empty the FRLVL fifo */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
|
|
800e19a: 687b ldr r3, [r7, #4]
|
|
800e19c: 9300 str r3, [sp, #0]
|
|
800e19e: 68bb ldr r3, [r7, #8]
|
|
800e1a0: 2200 movs r2, #0
|
|
800e1a2: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800e1a6: 68f8 ldr r0, [r7, #12]
|
|
800e1a8: f7ff ff22 bl 800dff0 <SPI_WaitFifoStateUntilTimeout>
|
|
800e1ac: 4603 mov r3, r0
|
|
800e1ae: 2b00 cmp r3, #0
|
|
800e1b0: d007 beq.n 800e1c2 <SPI_EndRxTransaction+0xa6>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
800e1b2: 68fb ldr r3, [r7, #12]
|
|
800e1b4: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800e1b6: f043 0220 orr.w r2, r3, #32
|
|
800e1ba: 68fb ldr r3, [r7, #12]
|
|
800e1bc: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
800e1be: 2303 movs r3, #3
|
|
800e1c0: e000 b.n 800e1c4 <SPI_EndRxTransaction+0xa8>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800e1c2: 2300 movs r3, #0
|
|
}
|
|
800e1c4: 4618 mov r0, r3
|
|
800e1c6: 3710 adds r7, #16
|
|
800e1c8: 46bd mov sp, r7
|
|
800e1ca: bd80 pop {r7, pc}
|
|
|
|
0800e1cc <SPI_EndRxTxTransaction>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800e1cc: b580 push {r7, lr}
|
|
800e1ce: b086 sub sp, #24
|
|
800e1d0: af02 add r7, sp, #8
|
|
800e1d2: 60f8 str r0, [r7, #12]
|
|
800e1d4: 60b9 str r1, [r7, #8]
|
|
800e1d6: 607a str r2, [r7, #4]
|
|
/* Control if the TX fifo is empty */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
|
|
800e1d8: 687b ldr r3, [r7, #4]
|
|
800e1da: 9300 str r3, [sp, #0]
|
|
800e1dc: 68bb ldr r3, [r7, #8]
|
|
800e1de: 2200 movs r2, #0
|
|
800e1e0: f44f 51c0 mov.w r1, #6144 @ 0x1800
|
|
800e1e4: 68f8 ldr r0, [r7, #12]
|
|
800e1e6: f7ff ff03 bl 800dff0 <SPI_WaitFifoStateUntilTimeout>
|
|
800e1ea: 4603 mov r3, r0
|
|
800e1ec: 2b00 cmp r3, #0
|
|
800e1ee: d007 beq.n 800e200 <SPI_EndRxTxTransaction+0x34>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
800e1f0: 68fb ldr r3, [r7, #12]
|
|
800e1f2: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800e1f4: f043 0220 orr.w r2, r3, #32
|
|
800e1f8: 68fb ldr r3, [r7, #12]
|
|
800e1fa: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
800e1fc: 2303 movs r3, #3
|
|
800e1fe: e027 b.n 800e250 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
|
|
800e200: 687b ldr r3, [r7, #4]
|
|
800e202: 9300 str r3, [sp, #0]
|
|
800e204: 68bb ldr r3, [r7, #8]
|
|
800e206: 2200 movs r2, #0
|
|
800e208: 2180 movs r1, #128 @ 0x80
|
|
800e20a: 68f8 ldr r0, [r7, #12]
|
|
800e20c: f7ff fe68 bl 800dee0 <SPI_WaitFlagStateUntilTimeout>
|
|
800e210: 4603 mov r3, r0
|
|
800e212: 2b00 cmp r3, #0
|
|
800e214: d007 beq.n 800e226 <SPI_EndRxTxTransaction+0x5a>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
800e216: 68fb ldr r3, [r7, #12]
|
|
800e218: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800e21a: f043 0220 orr.w r2, r3, #32
|
|
800e21e: 68fb ldr r3, [r7, #12]
|
|
800e220: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
800e222: 2303 movs r3, #3
|
|
800e224: e014 b.n 800e250 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
/* Control if the RX fifo is empty */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
|
|
800e226: 687b ldr r3, [r7, #4]
|
|
800e228: 9300 str r3, [sp, #0]
|
|
800e22a: 68bb ldr r3, [r7, #8]
|
|
800e22c: 2200 movs r2, #0
|
|
800e22e: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800e232: 68f8 ldr r0, [r7, #12]
|
|
800e234: f7ff fedc bl 800dff0 <SPI_WaitFifoStateUntilTimeout>
|
|
800e238: 4603 mov r3, r0
|
|
800e23a: 2b00 cmp r3, #0
|
|
800e23c: d007 beq.n 800e24e <SPI_EndRxTxTransaction+0x82>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
800e23e: 68fb ldr r3, [r7, #12]
|
|
800e240: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800e242: f043 0220 orr.w r2, r3, #32
|
|
800e246: 68fb ldr r3, [r7, #12]
|
|
800e248: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
800e24a: 2303 movs r3, #3
|
|
800e24c: e000 b.n 800e250 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800e24e: 2300 movs r3, #0
|
|
}
|
|
800e250: 4618 mov r0, r3
|
|
800e252: 3710 adds r7, #16
|
|
800e254: 46bd mov sp, r7
|
|
800e256: bd80 pop {r7, pc}
|
|
|
|
0800e258 <SPI_AbortRx_ISR>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800e258: b580 push {r7, lr}
|
|
800e25a: b086 sub sp, #24
|
|
800e25c: af02 add r7, sp, #8
|
|
800e25e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count;
|
|
|
|
/* Disable SPI Peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800e260: 687b ldr r3, [r7, #4]
|
|
800e262: 681b ldr r3, [r3, #0]
|
|
800e264: 681a ldr r2, [r3, #0]
|
|
800e266: 687b ldr r3, [r7, #4]
|
|
800e268: 681b ldr r3, [r3, #0]
|
|
800e26a: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800e26e: 601a str r2, [r3, #0]
|
|
|
|
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
|
|
800e270: 4b27 ldr r3, [pc, #156] @ (800e310 <SPI_AbortRx_ISR+0xb8>)
|
|
800e272: 681b ldr r3, [r3, #0]
|
|
800e274: 4a27 ldr r2, [pc, #156] @ (800e314 <SPI_AbortRx_ISR+0xbc>)
|
|
800e276: fba2 2303 umull r2, r3, r2, r3
|
|
800e27a: 0a5b lsrs r3, r3, #9
|
|
800e27c: 2264 movs r2, #100 @ 0x64
|
|
800e27e: fb02 f303 mul.w r3, r2, r3
|
|
800e282: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable RXNEIE interrupt */
|
|
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
|
|
800e284: 687b ldr r3, [r7, #4]
|
|
800e286: 681b ldr r3, [r3, #0]
|
|
800e288: 685a ldr r2, [r3, #4]
|
|
800e28a: 687b ldr r3, [r7, #4]
|
|
800e28c: 681b ldr r3, [r3, #0]
|
|
800e28e: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800e292: 605a str r2, [r3, #4]
|
|
|
|
/* Check RXNEIE is disabled */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
800e294: 68fb ldr r3, [r7, #12]
|
|
800e296: 2b00 cmp r3, #0
|
|
800e298: d106 bne.n 800e2a8 <SPI_AbortRx_ISR+0x50>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
|
|
800e29a: 687b ldr r3, [r7, #4]
|
|
800e29c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800e29e: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
800e2a2: 687b ldr r3, [r7, #4]
|
|
800e2a4: 661a str r2, [r3, #96] @ 0x60
|
|
break;
|
|
800e2a6: e009 b.n 800e2bc <SPI_AbortRx_ISR+0x64>
|
|
}
|
|
count--;
|
|
800e2a8: 68fb ldr r3, [r7, #12]
|
|
800e2aa: 3b01 subs r3, #1
|
|
800e2ac: 60fb str r3, [r7, #12]
|
|
} while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
|
|
800e2ae: 687b ldr r3, [r7, #4]
|
|
800e2b0: 681b ldr r3, [r3, #0]
|
|
800e2b2: 685b ldr r3, [r3, #4]
|
|
800e2b4: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800e2b8: 2b40 cmp r3, #64 @ 0x40
|
|
800e2ba: d0eb beq.n 800e294 <SPI_AbortRx_ISR+0x3c>
|
|
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
|
|
800e2bc: f7f8 fb56 bl 800696c <HAL_GetTick>
|
|
800e2c0: 4603 mov r3, r0
|
|
800e2c2: 9300 str r3, [sp, #0]
|
|
800e2c4: 2364 movs r3, #100 @ 0x64
|
|
800e2c6: 2200 movs r2, #0
|
|
800e2c8: 2180 movs r1, #128 @ 0x80
|
|
800e2ca: 6878 ldr r0, [r7, #4]
|
|
800e2cc: f7ff fe08 bl 800dee0 <SPI_WaitFlagStateUntilTimeout>
|
|
800e2d0: 4603 mov r3, r0
|
|
800e2d2: 2b00 cmp r3, #0
|
|
800e2d4: d002 beq.n 800e2dc <SPI_AbortRx_ISR+0x84>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800e2d6: 687b ldr r3, [r7, #4]
|
|
800e2d8: 2240 movs r2, #64 @ 0x40
|
|
800e2da: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Empty the FRLVL fifo */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
|
|
800e2dc: f7f8 fb46 bl 800696c <HAL_GetTick>
|
|
800e2e0: 4603 mov r3, r0
|
|
800e2e2: 9300 str r3, [sp, #0]
|
|
800e2e4: 2364 movs r3, #100 @ 0x64
|
|
800e2e6: 2200 movs r2, #0
|
|
800e2e8: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800e2ec: 6878 ldr r0, [r7, #4]
|
|
800e2ee: f7ff fe7f bl 800dff0 <SPI_WaitFifoStateUntilTimeout>
|
|
800e2f2: 4603 mov r3, r0
|
|
800e2f4: 2b00 cmp r3, #0
|
|
800e2f6: d002 beq.n 800e2fe <SPI_AbortRx_ISR+0xa6>
|
|
HAL_GetTick()) != HAL_OK)
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800e2f8: 687b ldr r3, [r7, #4]
|
|
800e2fa: 2240 movs r2, #64 @ 0x40
|
|
800e2fc: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_ABORT;
|
|
800e2fe: 687b ldr r3, [r7, #4]
|
|
800e300: 2207 movs r2, #7
|
|
800e302: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
}
|
|
800e306: bf00 nop
|
|
800e308: 3710 adds r7, #16
|
|
800e30a: 46bd mov sp, r7
|
|
800e30c: bd80 pop {r7, pc}
|
|
800e30e: bf00 nop
|
|
800e310: 2000000c .word 0x2000000c
|
|
800e314: 057619f1 .word 0x057619f1
|
|
|
|
0800e318 <SPI_AbortTx_ISR>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval None
|
|
*/
|
|
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800e318: b580 push {r7, lr}
|
|
800e31a: b086 sub sp, #24
|
|
800e31c: af02 add r7, sp, #8
|
|
800e31e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count;
|
|
|
|
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
|
|
800e320: 4b4c ldr r3, [pc, #304] @ (800e454 <SPI_AbortTx_ISR+0x13c>)
|
|
800e322: 681b ldr r3, [r3, #0]
|
|
800e324: 4a4c ldr r2, [pc, #304] @ (800e458 <SPI_AbortTx_ISR+0x140>)
|
|
800e326: fba2 2303 umull r2, r3, r2, r3
|
|
800e32a: 0a5b lsrs r3, r3, #9
|
|
800e32c: 2264 movs r2, #100 @ 0x64
|
|
800e32e: fb02 f303 mul.w r3, r2, r3
|
|
800e332: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable TXEIE interrupt */
|
|
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
|
|
800e334: 687b ldr r3, [r7, #4]
|
|
800e336: 681b ldr r3, [r3, #0]
|
|
800e338: 685a ldr r2, [r3, #4]
|
|
800e33a: 687b ldr r3, [r7, #4]
|
|
800e33c: 681b ldr r3, [r3, #0]
|
|
800e33e: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
800e342: 605a str r2, [r3, #4]
|
|
|
|
/* Check TXEIE is disabled */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
800e344: 68fb ldr r3, [r7, #12]
|
|
800e346: 2b00 cmp r3, #0
|
|
800e348: d106 bne.n 800e358 <SPI_AbortTx_ISR+0x40>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
|
|
800e34a: 687b ldr r3, [r7, #4]
|
|
800e34c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800e34e: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
800e352: 687b ldr r3, [r7, #4]
|
|
800e354: 661a str r2, [r3, #96] @ 0x60
|
|
break;
|
|
800e356: e009 b.n 800e36c <SPI_AbortTx_ISR+0x54>
|
|
}
|
|
count--;
|
|
800e358: 68fb ldr r3, [r7, #12]
|
|
800e35a: 3b01 subs r3, #1
|
|
800e35c: 60fb str r3, [r7, #12]
|
|
} while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
|
|
800e35e: 687b ldr r3, [r7, #4]
|
|
800e360: 681b ldr r3, [r3, #0]
|
|
800e362: 685b ldr r3, [r3, #4]
|
|
800e364: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800e368: 2b80 cmp r3, #128 @ 0x80
|
|
800e36a: d0eb beq.n 800e344 <SPI_AbortTx_ISR+0x2c>
|
|
|
|
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
|
|
800e36c: f7f8 fafe bl 800696c <HAL_GetTick>
|
|
800e370: 4603 mov r3, r0
|
|
800e372: 461a mov r2, r3
|
|
800e374: 2164 movs r1, #100 @ 0x64
|
|
800e376: 6878 ldr r0, [r7, #4]
|
|
800e378: f7ff ff28 bl 800e1cc <SPI_EndRxTxTransaction>
|
|
800e37c: 4603 mov r3, r0
|
|
800e37e: 2b00 cmp r3, #0
|
|
800e380: d002 beq.n 800e388 <SPI_AbortTx_ISR+0x70>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800e382: 687b ldr r3, [r7, #4]
|
|
800e384: 2240 movs r2, #64 @ 0x40
|
|
800e386: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Disable SPI Peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800e388: 687b ldr r3, [r7, #4]
|
|
800e38a: 681b ldr r3, [r3, #0]
|
|
800e38c: 681a ldr r2, [r3, #0]
|
|
800e38e: 687b ldr r3, [r7, #4]
|
|
800e390: 681b ldr r3, [r3, #0]
|
|
800e392: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800e396: 601a str r2, [r3, #0]
|
|
|
|
/* Empty the FRLVL fifo */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
|
|
800e398: f7f8 fae8 bl 800696c <HAL_GetTick>
|
|
800e39c: 4603 mov r3, r0
|
|
800e39e: 9300 str r3, [sp, #0]
|
|
800e3a0: 2364 movs r3, #100 @ 0x64
|
|
800e3a2: 2200 movs r2, #0
|
|
800e3a4: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800e3a8: 6878 ldr r0, [r7, #4]
|
|
800e3aa: f7ff fe21 bl 800dff0 <SPI_WaitFifoStateUntilTimeout>
|
|
800e3ae: 4603 mov r3, r0
|
|
800e3b0: 2b00 cmp r3, #0
|
|
800e3b2: d002 beq.n 800e3ba <SPI_AbortTx_ISR+0xa2>
|
|
HAL_GetTick()) != HAL_OK)
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800e3b4: 687b ldr r3, [r7, #4]
|
|
800e3b6: 2240 movs r2, #64 @ 0x40
|
|
800e3b8: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
|
|
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
|
|
800e3ba: 687b ldr r3, [r7, #4]
|
|
800e3bc: 681b ldr r3, [r3, #0]
|
|
800e3be: 685b ldr r3, [r3, #4]
|
|
800e3c0: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800e3c4: 2b40 cmp r3, #64 @ 0x40
|
|
800e3c6: d13c bne.n 800e442 <SPI_AbortTx_ISR+0x12a>
|
|
{
|
|
/* Disable RXNEIE interrupt */
|
|
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
|
|
800e3c8: 687b ldr r3, [r7, #4]
|
|
800e3ca: 681b ldr r3, [r3, #0]
|
|
800e3cc: 685a ldr r2, [r3, #4]
|
|
800e3ce: 687b ldr r3, [r7, #4]
|
|
800e3d0: 681b ldr r3, [r3, #0]
|
|
800e3d2: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800e3d6: 605a str r2, [r3, #4]
|
|
|
|
/* Check RXNEIE is disabled */
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
800e3d8: 68fb ldr r3, [r7, #12]
|
|
800e3da: 2b00 cmp r3, #0
|
|
800e3dc: d106 bne.n 800e3ec <SPI_AbortTx_ISR+0xd4>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
|
|
800e3de: 687b ldr r3, [r7, #4]
|
|
800e3e0: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800e3e2: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
800e3e6: 687b ldr r3, [r7, #4]
|
|
800e3e8: 661a str r2, [r3, #96] @ 0x60
|
|
break;
|
|
800e3ea: e009 b.n 800e400 <SPI_AbortTx_ISR+0xe8>
|
|
}
|
|
count--;
|
|
800e3ec: 68fb ldr r3, [r7, #12]
|
|
800e3ee: 3b01 subs r3, #1
|
|
800e3f0: 60fb str r3, [r7, #12]
|
|
} while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
|
|
800e3f2: 687b ldr r3, [r7, #4]
|
|
800e3f4: 681b ldr r3, [r3, #0]
|
|
800e3f6: 685b ldr r3, [r3, #4]
|
|
800e3f8: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800e3fc: 2b40 cmp r3, #64 @ 0x40
|
|
800e3fe: d0eb beq.n 800e3d8 <SPI_AbortTx_ISR+0xc0>
|
|
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
|
|
800e400: f7f8 fab4 bl 800696c <HAL_GetTick>
|
|
800e404: 4603 mov r3, r0
|
|
800e406: 9300 str r3, [sp, #0]
|
|
800e408: 2364 movs r3, #100 @ 0x64
|
|
800e40a: 2200 movs r2, #0
|
|
800e40c: 2180 movs r1, #128 @ 0x80
|
|
800e40e: 6878 ldr r0, [r7, #4]
|
|
800e410: f7ff fd66 bl 800dee0 <SPI_WaitFlagStateUntilTimeout>
|
|
800e414: 4603 mov r3, r0
|
|
800e416: 2b00 cmp r3, #0
|
|
800e418: d002 beq.n 800e420 <SPI_AbortTx_ISR+0x108>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800e41a: 687b ldr r3, [r7, #4]
|
|
800e41c: 2240 movs r2, #64 @ 0x40
|
|
800e41e: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Empty the FRLVL fifo */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
|
|
800e420: f7f8 faa4 bl 800696c <HAL_GetTick>
|
|
800e424: 4603 mov r3, r0
|
|
800e426: 9300 str r3, [sp, #0]
|
|
800e428: 2364 movs r3, #100 @ 0x64
|
|
800e42a: 2200 movs r2, #0
|
|
800e42c: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800e430: 6878 ldr r0, [r7, #4]
|
|
800e432: f7ff fddd bl 800dff0 <SPI_WaitFifoStateUntilTimeout>
|
|
800e436: 4603 mov r3, r0
|
|
800e438: 2b00 cmp r3, #0
|
|
800e43a: d002 beq.n 800e442 <SPI_AbortTx_ISR+0x12a>
|
|
HAL_GetTick()) != HAL_OK)
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
|
|
800e43c: 687b ldr r3, [r7, #4]
|
|
800e43e: 2240 movs r2, #64 @ 0x40
|
|
800e440: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
}
|
|
hspi->State = HAL_SPI_STATE_ABORT;
|
|
800e442: 687b ldr r3, [r7, #4]
|
|
800e444: 2207 movs r2, #7
|
|
800e446: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
}
|
|
800e44a: bf00 nop
|
|
800e44c: 3710 adds r7, #16
|
|
800e44e: 46bd mov sp, r7
|
|
800e450: bd80 pop {r7, pc}
|
|
800e452: bf00 nop
|
|
800e454: 2000000c .word 0x2000000c
|
|
800e458: 057619f1 .word 0x057619f1
|
|
|
|
0800e45c <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
800e45c: b580 push {r7, lr}
|
|
800e45e: b082 sub sp, #8
|
|
800e460: af00 add r7, sp, #0
|
|
800e462: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800e464: 687b ldr r3, [r7, #4]
|
|
800e466: 2b00 cmp r3, #0
|
|
800e468: d101 bne.n 800e46e <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800e46a: 2301 movs r3, #1
|
|
800e46c: e049 b.n 800e502 <HAL_TIM_Base_Init+0xa6>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800e46e: 687b ldr r3, [r7, #4]
|
|
800e470: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800e474: b2db uxtb r3, r3
|
|
800e476: 2b00 cmp r3, #0
|
|
800e478: d106 bne.n 800e488 <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
800e47a: 687b ldr r3, [r7, #4]
|
|
800e47c: 2200 movs r2, #0
|
|
800e47e: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
800e482: 6878 ldr r0, [r7, #4]
|
|
800e484: f000 f841 bl 800e50a <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800e488: 687b ldr r3, [r7, #4]
|
|
800e48a: 2202 movs r2, #2
|
|
800e48c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800e490: 687b ldr r3, [r7, #4]
|
|
800e492: 681a ldr r2, [r3, #0]
|
|
800e494: 687b ldr r3, [r7, #4]
|
|
800e496: 3304 adds r3, #4
|
|
800e498: 4619 mov r1, r3
|
|
800e49a: 4610 mov r0, r2
|
|
800e49c: f000 fb28 bl 800eaf0 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
800e4a0: 687b ldr r3, [r7, #4]
|
|
800e4a2: 2201 movs r2, #1
|
|
800e4a4: f883 2048 strb.w r2, [r3, #72] @ 0x48
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800e4a8: 687b ldr r3, [r7, #4]
|
|
800e4aa: 2201 movs r2, #1
|
|
800e4ac: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
800e4b0: 687b ldr r3, [r7, #4]
|
|
800e4b2: 2201 movs r2, #1
|
|
800e4b4: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
800e4b8: 687b ldr r3, [r7, #4]
|
|
800e4ba: 2201 movs r2, #1
|
|
800e4bc: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
800e4c0: 687b ldr r3, [r7, #4]
|
|
800e4c2: 2201 movs r2, #1
|
|
800e4c4: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
800e4c8: 687b ldr r3, [r7, #4]
|
|
800e4ca: 2201 movs r2, #1
|
|
800e4cc: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
800e4d0: 687b ldr r3, [r7, #4]
|
|
800e4d2: 2201 movs r2, #1
|
|
800e4d4: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800e4d8: 687b ldr r3, [r7, #4]
|
|
800e4da: 2201 movs r2, #1
|
|
800e4dc: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800e4e0: 687b ldr r3, [r7, #4]
|
|
800e4e2: 2201 movs r2, #1
|
|
800e4e4: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800e4e8: 687b ldr r3, [r7, #4]
|
|
800e4ea: 2201 movs r2, #1
|
|
800e4ec: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
800e4f0: 687b ldr r3, [r7, #4]
|
|
800e4f2: 2201 movs r2, #1
|
|
800e4f4: f883 2047 strb.w r2, [r3, #71] @ 0x47
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800e4f8: 687b ldr r3, [r7, #4]
|
|
800e4fa: 2201 movs r2, #1
|
|
800e4fc: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
800e500: 2300 movs r3, #0
|
|
}
|
|
800e502: 4618 mov r0, r3
|
|
800e504: 3708 adds r7, #8
|
|
800e506: 46bd mov sp, r7
|
|
800e508: bd80 pop {r7, pc}
|
|
|
|
0800e50a <HAL_TIM_Base_MspInit>:
|
|
* @brief Initializes the TIM Base MSP.
|
|
* @param htim TIM Base handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
|
|
{
|
|
800e50a: b480 push {r7}
|
|
800e50c: b083 sub sp, #12
|
|
800e50e: af00 add r7, sp, #0
|
|
800e510: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_Base_MspInit could be implemented in the user file
|
|
*/
|
|
}
|
|
800e512: bf00 nop
|
|
800e514: 370c adds r7, #12
|
|
800e516: 46bd mov sp, r7
|
|
800e518: f85d 7b04 ldr.w r7, [sp], #4
|
|
800e51c: 4770 bx lr
|
|
...
|
|
|
|
0800e520 <HAL_TIM_Base_Start_IT>:
|
|
* @brief Starts the TIM Base generation in interrupt mode.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
|
|
{
|
|
800e520: b480 push {r7}
|
|
800e522: b085 sub sp, #20
|
|
800e524: af00 add r7, sp, #0
|
|
800e526: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Check the TIM state */
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
800e528: 687b ldr r3, [r7, #4]
|
|
800e52a: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800e52e: b2db uxtb r3, r3
|
|
800e530: 2b01 cmp r3, #1
|
|
800e532: d001 beq.n 800e538 <HAL_TIM_Base_Start_IT+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
800e534: 2301 movs r3, #1
|
|
800e536: e036 b.n 800e5a6 <HAL_TIM_Base_Start_IT+0x86>
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800e538: 687b ldr r3, [r7, #4]
|
|
800e53a: 2202 movs r2, #2
|
|
800e53c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Enable the TIM Update interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|
800e540: 687b ldr r3, [r7, #4]
|
|
800e542: 681b ldr r3, [r3, #0]
|
|
800e544: 68da ldr r2, [r3, #12]
|
|
800e546: 687b ldr r3, [r7, #4]
|
|
800e548: 681b ldr r3, [r3, #0]
|
|
800e54a: f042 0201 orr.w r2, r2, #1
|
|
800e54e: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
800e550: 687b ldr r3, [r7, #4]
|
|
800e552: 681b ldr r3, [r3, #0]
|
|
800e554: 4a17 ldr r2, [pc, #92] @ (800e5b4 <HAL_TIM_Base_Start_IT+0x94>)
|
|
800e556: 4293 cmp r3, r2
|
|
800e558: d004 beq.n 800e564 <HAL_TIM_Base_Start_IT+0x44>
|
|
800e55a: 687b ldr r3, [r7, #4]
|
|
800e55c: 681b ldr r3, [r3, #0]
|
|
800e55e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800e562: d115 bne.n 800e590 <HAL_TIM_Base_Start_IT+0x70>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
800e564: 687b ldr r3, [r7, #4]
|
|
800e566: 681b ldr r3, [r3, #0]
|
|
800e568: 689a ldr r2, [r3, #8]
|
|
800e56a: 4b13 ldr r3, [pc, #76] @ (800e5b8 <HAL_TIM_Base_Start_IT+0x98>)
|
|
800e56c: 4013 ands r3, r2
|
|
800e56e: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800e570: 68fb ldr r3, [r7, #12]
|
|
800e572: 2b06 cmp r3, #6
|
|
800e574: d015 beq.n 800e5a2 <HAL_TIM_Base_Start_IT+0x82>
|
|
800e576: 68fb ldr r3, [r7, #12]
|
|
800e578: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800e57c: d011 beq.n 800e5a2 <HAL_TIM_Base_Start_IT+0x82>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
800e57e: 687b ldr r3, [r7, #4]
|
|
800e580: 681b ldr r3, [r3, #0]
|
|
800e582: 681a ldr r2, [r3, #0]
|
|
800e584: 687b ldr r3, [r7, #4]
|
|
800e586: 681b ldr r3, [r3, #0]
|
|
800e588: f042 0201 orr.w r2, r2, #1
|
|
800e58c: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800e58e: e008 b.n 800e5a2 <HAL_TIM_Base_Start_IT+0x82>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
800e590: 687b ldr r3, [r7, #4]
|
|
800e592: 681b ldr r3, [r3, #0]
|
|
800e594: 681a ldr r2, [r3, #0]
|
|
800e596: 687b ldr r3, [r7, #4]
|
|
800e598: 681b ldr r3, [r3, #0]
|
|
800e59a: f042 0201 orr.w r2, r2, #1
|
|
800e59e: 601a str r2, [r3, #0]
|
|
800e5a0: e000 b.n 800e5a4 <HAL_TIM_Base_Start_IT+0x84>
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800e5a2: bf00 nop
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800e5a4: 2300 movs r3, #0
|
|
}
|
|
800e5a6: 4618 mov r0, r3
|
|
800e5a8: 3714 adds r7, #20
|
|
800e5aa: 46bd mov sp, r7
|
|
800e5ac: f85d 7b04 ldr.w r7, [sp], #4
|
|
800e5b0: 4770 bx lr
|
|
800e5b2: bf00 nop
|
|
800e5b4: 40012c00 .word 0x40012c00
|
|
800e5b8: 00010007 .word 0x00010007
|
|
|
|
0800e5bc <HAL_TIM_PWM_Init>:
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
* @param htim TIM PWM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
800e5bc: b580 push {r7, lr}
|
|
800e5be: b082 sub sp, #8
|
|
800e5c0: af00 add r7, sp, #0
|
|
800e5c2: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800e5c4: 687b ldr r3, [r7, #4]
|
|
800e5c6: 2b00 cmp r3, #0
|
|
800e5c8: d101 bne.n 800e5ce <HAL_TIM_PWM_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800e5ca: 2301 movs r3, #1
|
|
800e5cc: e049 b.n 800e662 <HAL_TIM_PWM_Init+0xa6>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800e5ce: 687b ldr r3, [r7, #4]
|
|
800e5d0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800e5d4: b2db uxtb r3, r3
|
|
800e5d6: 2b00 cmp r3, #0
|
|
800e5d8: d106 bne.n 800e5e8 <HAL_TIM_PWM_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
800e5da: 687b ldr r3, [r7, #4]
|
|
800e5dc: 2200 movs r2, #0
|
|
800e5de: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->PWM_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
800e5e2: 6878 ldr r0, [r7, #4]
|
|
800e5e4: f7f7 ff08 bl 80063f8 <HAL_TIM_PWM_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800e5e8: 687b ldr r3, [r7, #4]
|
|
800e5ea: 2202 movs r2, #2
|
|
800e5ec: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Init the base time for the PWM */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800e5f0: 687b ldr r3, [r7, #4]
|
|
800e5f2: 681a ldr r2, [r3, #0]
|
|
800e5f4: 687b ldr r3, [r7, #4]
|
|
800e5f6: 3304 adds r3, #4
|
|
800e5f8: 4619 mov r1, r3
|
|
800e5fa: 4610 mov r0, r2
|
|
800e5fc: f000 fa78 bl 800eaf0 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
800e600: 687b ldr r3, [r7, #4]
|
|
800e602: 2201 movs r2, #1
|
|
800e604: f883 2048 strb.w r2, [r3, #72] @ 0x48
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800e608: 687b ldr r3, [r7, #4]
|
|
800e60a: 2201 movs r2, #1
|
|
800e60c: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
800e610: 687b ldr r3, [r7, #4]
|
|
800e612: 2201 movs r2, #1
|
|
800e614: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
800e618: 687b ldr r3, [r7, #4]
|
|
800e61a: 2201 movs r2, #1
|
|
800e61c: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
800e620: 687b ldr r3, [r7, #4]
|
|
800e622: 2201 movs r2, #1
|
|
800e624: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
800e628: 687b ldr r3, [r7, #4]
|
|
800e62a: 2201 movs r2, #1
|
|
800e62c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
800e630: 687b ldr r3, [r7, #4]
|
|
800e632: 2201 movs r2, #1
|
|
800e634: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800e638: 687b ldr r3, [r7, #4]
|
|
800e63a: 2201 movs r2, #1
|
|
800e63c: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800e640: 687b ldr r3, [r7, #4]
|
|
800e642: 2201 movs r2, #1
|
|
800e644: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800e648: 687b ldr r3, [r7, #4]
|
|
800e64a: 2201 movs r2, #1
|
|
800e64c: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
800e650: 687b ldr r3, [r7, #4]
|
|
800e652: 2201 movs r2, #1
|
|
800e654: f883 2047 strb.w r2, [r3, #71] @ 0x47
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800e658: 687b ldr r3, [r7, #4]
|
|
800e65a: 2201 movs r2, #1
|
|
800e65c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
800e660: 2300 movs r3, #0
|
|
}
|
|
800e662: 4618 mov r0, r3
|
|
800e664: 3708 adds r7, #8
|
|
800e666: 46bd mov sp, r7
|
|
800e668: bd80 pop {r7, pc}
|
|
|
|
0800e66a <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
800e66a: b580 push {r7, lr}
|
|
800e66c: b084 sub sp, #16
|
|
800e66e: af00 add r7, sp, #0
|
|
800e670: 6078 str r0, [r7, #4]
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
800e672: 687b ldr r3, [r7, #4]
|
|
800e674: 681b ldr r3, [r3, #0]
|
|
800e676: 68db ldr r3, [r3, #12]
|
|
800e678: 60fb str r3, [r7, #12]
|
|
uint32_t itflag = htim->Instance->SR;
|
|
800e67a: 687b ldr r3, [r7, #4]
|
|
800e67c: 681b ldr r3, [r3, #0]
|
|
800e67e: 691b ldr r3, [r3, #16]
|
|
800e680: 60bb str r3, [r7, #8]
|
|
|
|
/* Capture compare 1 event */
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
800e682: 68bb ldr r3, [r7, #8]
|
|
800e684: f003 0302 and.w r3, r3, #2
|
|
800e688: 2b00 cmp r3, #0
|
|
800e68a: d020 beq.n 800e6ce <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
|
800e68c: 68fb ldr r3, [r7, #12]
|
|
800e68e: f003 0302 and.w r3, r3, #2
|
|
800e692: 2b00 cmp r3, #0
|
|
800e694: d01b beq.n 800e6ce <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
|
800e696: 687b ldr r3, [r7, #4]
|
|
800e698: 681b ldr r3, [r3, #0]
|
|
800e69a: f06f 0202 mvn.w r2, #2
|
|
800e69e: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
800e6a0: 687b ldr r3, [r7, #4]
|
|
800e6a2: 2201 movs r2, #1
|
|
800e6a4: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
800e6a6: 687b ldr r3, [r7, #4]
|
|
800e6a8: 681b ldr r3, [r3, #0]
|
|
800e6aa: 699b ldr r3, [r3, #24]
|
|
800e6ac: f003 0303 and.w r3, r3, #3
|
|
800e6b0: 2b00 cmp r3, #0
|
|
800e6b2: d003 beq.n 800e6bc <HAL_TIM_IRQHandler+0x52>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800e6b4: 6878 ldr r0, [r7, #4]
|
|
800e6b6: f000 f9fd bl 800eab4 <HAL_TIM_IC_CaptureCallback>
|
|
800e6ba: e005 b.n 800e6c8 <HAL_TIM_IRQHandler+0x5e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800e6bc: 6878 ldr r0, [r7, #4]
|
|
800e6be: f000 f9ef bl 800eaa0 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800e6c2: 6878 ldr r0, [r7, #4]
|
|
800e6c4: f000 fa00 bl 800eac8 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800e6c8: 687b ldr r3, [r7, #4]
|
|
800e6ca: 2200 movs r2, #0
|
|
800e6cc: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
|
800e6ce: 68bb ldr r3, [r7, #8]
|
|
800e6d0: f003 0304 and.w r3, r3, #4
|
|
800e6d4: 2b00 cmp r3, #0
|
|
800e6d6: d020 beq.n 800e71a <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
|
800e6d8: 68fb ldr r3, [r7, #12]
|
|
800e6da: f003 0304 and.w r3, r3, #4
|
|
800e6de: 2b00 cmp r3, #0
|
|
800e6e0: d01b beq.n 800e71a <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
|
800e6e2: 687b ldr r3, [r7, #4]
|
|
800e6e4: 681b ldr r3, [r3, #0]
|
|
800e6e6: f06f 0204 mvn.w r2, #4
|
|
800e6ea: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
800e6ec: 687b ldr r3, [r7, #4]
|
|
800e6ee: 2202 movs r2, #2
|
|
800e6f0: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
800e6f2: 687b ldr r3, [r7, #4]
|
|
800e6f4: 681b ldr r3, [r3, #0]
|
|
800e6f6: 699b ldr r3, [r3, #24]
|
|
800e6f8: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800e6fc: 2b00 cmp r3, #0
|
|
800e6fe: d003 beq.n 800e708 <HAL_TIM_IRQHandler+0x9e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800e700: 6878 ldr r0, [r7, #4]
|
|
800e702: f000 f9d7 bl 800eab4 <HAL_TIM_IC_CaptureCallback>
|
|
800e706: e005 b.n 800e714 <HAL_TIM_IRQHandler+0xaa>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800e708: 6878 ldr r0, [r7, #4]
|
|
800e70a: f000 f9c9 bl 800eaa0 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800e70e: 6878 ldr r0, [r7, #4]
|
|
800e710: f000 f9da bl 800eac8 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800e714: 687b ldr r3, [r7, #4]
|
|
800e716: 2200 movs r2, #0
|
|
800e718: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
|
800e71a: 68bb ldr r3, [r7, #8]
|
|
800e71c: f003 0308 and.w r3, r3, #8
|
|
800e720: 2b00 cmp r3, #0
|
|
800e722: d020 beq.n 800e766 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
|
800e724: 68fb ldr r3, [r7, #12]
|
|
800e726: f003 0308 and.w r3, r3, #8
|
|
800e72a: 2b00 cmp r3, #0
|
|
800e72c: d01b beq.n 800e766 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
|
800e72e: 687b ldr r3, [r7, #4]
|
|
800e730: 681b ldr r3, [r3, #0]
|
|
800e732: f06f 0208 mvn.w r2, #8
|
|
800e736: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
800e738: 687b ldr r3, [r7, #4]
|
|
800e73a: 2204 movs r2, #4
|
|
800e73c: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
800e73e: 687b ldr r3, [r7, #4]
|
|
800e740: 681b ldr r3, [r3, #0]
|
|
800e742: 69db ldr r3, [r3, #28]
|
|
800e744: f003 0303 and.w r3, r3, #3
|
|
800e748: 2b00 cmp r3, #0
|
|
800e74a: d003 beq.n 800e754 <HAL_TIM_IRQHandler+0xea>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800e74c: 6878 ldr r0, [r7, #4]
|
|
800e74e: f000 f9b1 bl 800eab4 <HAL_TIM_IC_CaptureCallback>
|
|
800e752: e005 b.n 800e760 <HAL_TIM_IRQHandler+0xf6>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800e754: 6878 ldr r0, [r7, #4]
|
|
800e756: f000 f9a3 bl 800eaa0 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800e75a: 6878 ldr r0, [r7, #4]
|
|
800e75c: f000 f9b4 bl 800eac8 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800e760: 687b ldr r3, [r7, #4]
|
|
800e762: 2200 movs r2, #0
|
|
800e764: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
|
800e766: 68bb ldr r3, [r7, #8]
|
|
800e768: f003 0310 and.w r3, r3, #16
|
|
800e76c: 2b00 cmp r3, #0
|
|
800e76e: d020 beq.n 800e7b2 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
|
800e770: 68fb ldr r3, [r7, #12]
|
|
800e772: f003 0310 and.w r3, r3, #16
|
|
800e776: 2b00 cmp r3, #0
|
|
800e778: d01b beq.n 800e7b2 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
|
800e77a: 687b ldr r3, [r7, #4]
|
|
800e77c: 681b ldr r3, [r3, #0]
|
|
800e77e: f06f 0210 mvn.w r2, #16
|
|
800e782: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
800e784: 687b ldr r3, [r7, #4]
|
|
800e786: 2208 movs r2, #8
|
|
800e788: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
800e78a: 687b ldr r3, [r7, #4]
|
|
800e78c: 681b ldr r3, [r3, #0]
|
|
800e78e: 69db ldr r3, [r3, #28]
|
|
800e790: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800e794: 2b00 cmp r3, #0
|
|
800e796: d003 beq.n 800e7a0 <HAL_TIM_IRQHandler+0x136>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800e798: 6878 ldr r0, [r7, #4]
|
|
800e79a: f000 f98b bl 800eab4 <HAL_TIM_IC_CaptureCallback>
|
|
800e79e: e005 b.n 800e7ac <HAL_TIM_IRQHandler+0x142>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800e7a0: 6878 ldr r0, [r7, #4]
|
|
800e7a2: f000 f97d bl 800eaa0 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800e7a6: 6878 ldr r0, [r7, #4]
|
|
800e7a8: f000 f98e bl 800eac8 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800e7ac: 687b ldr r3, [r7, #4]
|
|
800e7ae: 2200 movs r2, #0
|
|
800e7b0: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
|
800e7b2: 68bb ldr r3, [r7, #8]
|
|
800e7b4: f003 0301 and.w r3, r3, #1
|
|
800e7b8: 2b00 cmp r3, #0
|
|
800e7ba: d00c beq.n 800e7d6 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
|
800e7bc: 68fb ldr r3, [r7, #12]
|
|
800e7be: f003 0301 and.w r3, r3, #1
|
|
800e7c2: 2b00 cmp r3, #0
|
|
800e7c4: d007 beq.n 800e7d6 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
800e7c6: 687b ldr r3, [r7, #4]
|
|
800e7c8: 681b ldr r3, [r3, #0]
|
|
800e7ca: f06f 0201 mvn.w r2, #1
|
|
800e7ce: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
800e7d0: 6878 ldr r0, [r7, #4]
|
|
800e7d2: f7f6 fdbd bl 8005350 <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
|
800e7d6: 68bb ldr r3, [r7, #8]
|
|
800e7d8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800e7dc: 2b00 cmp r3, #0
|
|
800e7de: d104 bne.n 800e7ea <HAL_TIM_IRQHandler+0x180>
|
|
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
|
|
800e7e0: 68bb ldr r3, [r7, #8]
|
|
800e7e2: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
|
800e7e6: 2b00 cmp r3, #0
|
|
800e7e8: d00c beq.n 800e804 <HAL_TIM_IRQHandler+0x19a>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
800e7ea: 68fb ldr r3, [r7, #12]
|
|
800e7ec: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800e7f0: 2b00 cmp r3, #0
|
|
800e7f2: d007 beq.n 800e804 <HAL_TIM_IRQHandler+0x19a>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
|
|
800e7f4: 687b ldr r3, [r7, #4]
|
|
800e7f6: 681b ldr r3, [r3, #0]
|
|
800e7f8: f46f 5202 mvn.w r2, #8320 @ 0x2080
|
|
800e7fc: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
800e7fe: 6878 ldr r0, [r7, #4]
|
|
800e800: f000 fcce bl 800f1a0 <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break2 input event */
|
|
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
|
|
800e804: 68bb ldr r3, [r7, #8]
|
|
800e806: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800e80a: 2b00 cmp r3, #0
|
|
800e80c: d00c beq.n 800e828 <HAL_TIM_IRQHandler+0x1be>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
800e80e: 68fb ldr r3, [r7, #12]
|
|
800e810: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800e814: 2b00 cmp r3, #0
|
|
800e816: d007 beq.n 800e828 <HAL_TIM_IRQHandler+0x1be>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
|
800e818: 687b ldr r3, [r7, #4]
|
|
800e81a: 681b ldr r3, [r3, #0]
|
|
800e81c: f46f 7280 mvn.w r2, #256 @ 0x100
|
|
800e820: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->Break2Callback(htim);
|
|
#else
|
|
HAL_TIMEx_Break2Callback(htim);
|
|
800e822: 6878 ldr r0, [r7, #4]
|
|
800e824: f000 fcc6 bl 800f1b4 <HAL_TIMEx_Break2Callback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Trigger detection event */
|
|
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
|
800e828: 68bb ldr r3, [r7, #8]
|
|
800e82a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800e82e: 2b00 cmp r3, #0
|
|
800e830: d00c beq.n 800e84c <HAL_TIM_IRQHandler+0x1e2>
|
|
{
|
|
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
|
800e832: 68fb ldr r3, [r7, #12]
|
|
800e834: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800e838: 2b00 cmp r3, #0
|
|
800e83a: d007 beq.n 800e84c <HAL_TIM_IRQHandler+0x1e2>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
800e83c: 687b ldr r3, [r7, #4]
|
|
800e83e: 681b ldr r3, [r3, #0]
|
|
800e840: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
800e844: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
800e846: 6878 ldr r0, [r7, #4]
|
|
800e848: f000 f948 bl 800eadc <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
|
800e84c: 68bb ldr r3, [r7, #8]
|
|
800e84e: f003 0320 and.w r3, r3, #32
|
|
800e852: 2b00 cmp r3, #0
|
|
800e854: d00c beq.n 800e870 <HAL_TIM_IRQHandler+0x206>
|
|
{
|
|
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
|
800e856: 68fb ldr r3, [r7, #12]
|
|
800e858: f003 0320 and.w r3, r3, #32
|
|
800e85c: 2b00 cmp r3, #0
|
|
800e85e: d007 beq.n 800e870 <HAL_TIM_IRQHandler+0x206>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
800e860: 687b ldr r3, [r7, #4]
|
|
800e862: 681b ldr r3, [r3, #0]
|
|
800e864: f06f 0220 mvn.w r2, #32
|
|
800e868: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
800e86a: 6878 ldr r0, [r7, #4]
|
|
800e86c: f000 fc8e bl 800f18c <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
800e870: bf00 nop
|
|
800e872: 3710 adds r7, #16
|
|
800e874: 46bd mov sp, r7
|
|
800e876: bd80 pop {r7, pc}
|
|
|
|
0800e878 <HAL_TIM_PWM_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
800e878: b580 push {r7, lr}
|
|
800e87a: b086 sub sp, #24
|
|
800e87c: af00 add r7, sp, #0
|
|
800e87e: 60f8 str r0, [r7, #12]
|
|
800e880: 60b9 str r1, [r7, #8]
|
|
800e882: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800e884: 2300 movs r3, #0
|
|
800e886: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
800e888: 68fb ldr r3, [r7, #12]
|
|
800e88a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
800e88e: 2b01 cmp r3, #1
|
|
800e890: d101 bne.n 800e896 <HAL_TIM_PWM_ConfigChannel+0x1e>
|
|
800e892: 2302 movs r3, #2
|
|
800e894: e0ff b.n 800ea96 <HAL_TIM_PWM_ConfigChannel+0x21e>
|
|
800e896: 68fb ldr r3, [r7, #12]
|
|
800e898: 2201 movs r2, #1
|
|
800e89a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
switch (Channel)
|
|
800e89e: 687b ldr r3, [r7, #4]
|
|
800e8a0: 2b14 cmp r3, #20
|
|
800e8a2: f200 80f0 bhi.w 800ea86 <HAL_TIM_PWM_ConfigChannel+0x20e>
|
|
800e8a6: a201 add r2, pc, #4 @ (adr r2, 800e8ac <HAL_TIM_PWM_ConfigChannel+0x34>)
|
|
800e8a8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800e8ac: 0800e901 .word 0x0800e901
|
|
800e8b0: 0800ea87 .word 0x0800ea87
|
|
800e8b4: 0800ea87 .word 0x0800ea87
|
|
800e8b8: 0800ea87 .word 0x0800ea87
|
|
800e8bc: 0800e941 .word 0x0800e941
|
|
800e8c0: 0800ea87 .word 0x0800ea87
|
|
800e8c4: 0800ea87 .word 0x0800ea87
|
|
800e8c8: 0800ea87 .word 0x0800ea87
|
|
800e8cc: 0800e983 .word 0x0800e983
|
|
800e8d0: 0800ea87 .word 0x0800ea87
|
|
800e8d4: 0800ea87 .word 0x0800ea87
|
|
800e8d8: 0800ea87 .word 0x0800ea87
|
|
800e8dc: 0800e9c3 .word 0x0800e9c3
|
|
800e8e0: 0800ea87 .word 0x0800ea87
|
|
800e8e4: 0800ea87 .word 0x0800ea87
|
|
800e8e8: 0800ea87 .word 0x0800ea87
|
|
800e8ec: 0800ea05 .word 0x0800ea05
|
|
800e8f0: 0800ea87 .word 0x0800ea87
|
|
800e8f4: 0800ea87 .word 0x0800ea87
|
|
800e8f8: 0800ea87 .word 0x0800ea87
|
|
800e8fc: 0800ea45 .word 0x0800ea45
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
800e900: 68fb ldr r3, [r7, #12]
|
|
800e902: 681b ldr r3, [r3, #0]
|
|
800e904: 68b9 ldr r1, [r7, #8]
|
|
800e906: 4618 mov r0, r3
|
|
800e908: f000 f95c bl 800ebc4 <TIM_OC1_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
800e90c: 68fb ldr r3, [r7, #12]
|
|
800e90e: 681b ldr r3, [r3, #0]
|
|
800e910: 699a ldr r2, [r3, #24]
|
|
800e912: 68fb ldr r3, [r7, #12]
|
|
800e914: 681b ldr r3, [r3, #0]
|
|
800e916: f042 0208 orr.w r2, r2, #8
|
|
800e91a: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
800e91c: 68fb ldr r3, [r7, #12]
|
|
800e91e: 681b ldr r3, [r3, #0]
|
|
800e920: 699a ldr r2, [r3, #24]
|
|
800e922: 68fb ldr r3, [r7, #12]
|
|
800e924: 681b ldr r3, [r3, #0]
|
|
800e926: f022 0204 bic.w r2, r2, #4
|
|
800e92a: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
800e92c: 68fb ldr r3, [r7, #12]
|
|
800e92e: 681b ldr r3, [r3, #0]
|
|
800e930: 6999 ldr r1, [r3, #24]
|
|
800e932: 68bb ldr r3, [r7, #8]
|
|
800e934: 691a ldr r2, [r3, #16]
|
|
800e936: 68fb ldr r3, [r7, #12]
|
|
800e938: 681b ldr r3, [r3, #0]
|
|
800e93a: 430a orrs r2, r1
|
|
800e93c: 619a str r2, [r3, #24]
|
|
break;
|
|
800e93e: e0a5 b.n 800ea8c <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
800e940: 68fb ldr r3, [r7, #12]
|
|
800e942: 681b ldr r3, [r3, #0]
|
|
800e944: 68b9 ldr r1, [r7, #8]
|
|
800e946: 4618 mov r0, r3
|
|
800e948: f000 f9ba bl 800ecc0 <TIM_OC2_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
800e94c: 68fb ldr r3, [r7, #12]
|
|
800e94e: 681b ldr r3, [r3, #0]
|
|
800e950: 699a ldr r2, [r3, #24]
|
|
800e952: 68fb ldr r3, [r7, #12]
|
|
800e954: 681b ldr r3, [r3, #0]
|
|
800e956: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
800e95a: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
800e95c: 68fb ldr r3, [r7, #12]
|
|
800e95e: 681b ldr r3, [r3, #0]
|
|
800e960: 699a ldr r2, [r3, #24]
|
|
800e962: 68fb ldr r3, [r7, #12]
|
|
800e964: 681b ldr r3, [r3, #0]
|
|
800e966: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
800e96a: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
800e96c: 68fb ldr r3, [r7, #12]
|
|
800e96e: 681b ldr r3, [r3, #0]
|
|
800e970: 6999 ldr r1, [r3, #24]
|
|
800e972: 68bb ldr r3, [r7, #8]
|
|
800e974: 691b ldr r3, [r3, #16]
|
|
800e976: 021a lsls r2, r3, #8
|
|
800e978: 68fb ldr r3, [r7, #12]
|
|
800e97a: 681b ldr r3, [r3, #0]
|
|
800e97c: 430a orrs r2, r1
|
|
800e97e: 619a str r2, [r3, #24]
|
|
break;
|
|
800e980: e084 b.n 800ea8c <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
800e982: 68fb ldr r3, [r7, #12]
|
|
800e984: 681b ldr r3, [r3, #0]
|
|
800e986: 68b9 ldr r1, [r7, #8]
|
|
800e988: 4618 mov r0, r3
|
|
800e98a: f000 fa15 bl 800edb8 <TIM_OC3_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
800e98e: 68fb ldr r3, [r7, #12]
|
|
800e990: 681b ldr r3, [r3, #0]
|
|
800e992: 69da ldr r2, [r3, #28]
|
|
800e994: 68fb ldr r3, [r7, #12]
|
|
800e996: 681b ldr r3, [r3, #0]
|
|
800e998: f042 0208 orr.w r2, r2, #8
|
|
800e99c: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
800e99e: 68fb ldr r3, [r7, #12]
|
|
800e9a0: 681b ldr r3, [r3, #0]
|
|
800e9a2: 69da ldr r2, [r3, #28]
|
|
800e9a4: 68fb ldr r3, [r7, #12]
|
|
800e9a6: 681b ldr r3, [r3, #0]
|
|
800e9a8: f022 0204 bic.w r2, r2, #4
|
|
800e9ac: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
800e9ae: 68fb ldr r3, [r7, #12]
|
|
800e9b0: 681b ldr r3, [r3, #0]
|
|
800e9b2: 69d9 ldr r1, [r3, #28]
|
|
800e9b4: 68bb ldr r3, [r7, #8]
|
|
800e9b6: 691a ldr r2, [r3, #16]
|
|
800e9b8: 68fb ldr r3, [r7, #12]
|
|
800e9ba: 681b ldr r3, [r3, #0]
|
|
800e9bc: 430a orrs r2, r1
|
|
800e9be: 61da str r2, [r3, #28]
|
|
break;
|
|
800e9c0: e064 b.n 800ea8c <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
800e9c2: 68fb ldr r3, [r7, #12]
|
|
800e9c4: 681b ldr r3, [r3, #0]
|
|
800e9c6: 68b9 ldr r1, [r7, #8]
|
|
800e9c8: 4618 mov r0, r3
|
|
800e9ca: f000 fa6f bl 800eeac <TIM_OC4_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
800e9ce: 68fb ldr r3, [r7, #12]
|
|
800e9d0: 681b ldr r3, [r3, #0]
|
|
800e9d2: 69da ldr r2, [r3, #28]
|
|
800e9d4: 68fb ldr r3, [r7, #12]
|
|
800e9d6: 681b ldr r3, [r3, #0]
|
|
800e9d8: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
800e9dc: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
800e9de: 68fb ldr r3, [r7, #12]
|
|
800e9e0: 681b ldr r3, [r3, #0]
|
|
800e9e2: 69da ldr r2, [r3, #28]
|
|
800e9e4: 68fb ldr r3, [r7, #12]
|
|
800e9e6: 681b ldr r3, [r3, #0]
|
|
800e9e8: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
800e9ec: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
800e9ee: 68fb ldr r3, [r7, #12]
|
|
800e9f0: 681b ldr r3, [r3, #0]
|
|
800e9f2: 69d9 ldr r1, [r3, #28]
|
|
800e9f4: 68bb ldr r3, [r7, #8]
|
|
800e9f6: 691b ldr r3, [r3, #16]
|
|
800e9f8: 021a lsls r2, r3, #8
|
|
800e9fa: 68fb ldr r3, [r7, #12]
|
|
800e9fc: 681b ldr r3, [r3, #0]
|
|
800e9fe: 430a orrs r2, r1
|
|
800ea00: 61da str r2, [r3, #28]
|
|
break;
|
|
800ea02: e043 b.n 800ea8c <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
800ea04: 68fb ldr r3, [r7, #12]
|
|
800ea06: 681b ldr r3, [r3, #0]
|
|
800ea08: 68b9 ldr r1, [r7, #8]
|
|
800ea0a: 4618 mov r0, r3
|
|
800ea0c: f000 faac bl 800ef68 <TIM_OC5_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel5*/
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
800ea10: 68fb ldr r3, [r7, #12]
|
|
800ea12: 681b ldr r3, [r3, #0]
|
|
800ea14: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
800ea16: 68fb ldr r3, [r7, #12]
|
|
800ea18: 681b ldr r3, [r3, #0]
|
|
800ea1a: f042 0208 orr.w r2, r2, #8
|
|
800ea1e: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
800ea20: 68fb ldr r3, [r7, #12]
|
|
800ea22: 681b ldr r3, [r3, #0]
|
|
800ea24: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
800ea26: 68fb ldr r3, [r7, #12]
|
|
800ea28: 681b ldr r3, [r3, #0]
|
|
800ea2a: f022 0204 bic.w r2, r2, #4
|
|
800ea2e: 655a str r2, [r3, #84] @ 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
800ea30: 68fb ldr r3, [r7, #12]
|
|
800ea32: 681b ldr r3, [r3, #0]
|
|
800ea34: 6d59 ldr r1, [r3, #84] @ 0x54
|
|
800ea36: 68bb ldr r3, [r7, #8]
|
|
800ea38: 691a ldr r2, [r3, #16]
|
|
800ea3a: 68fb ldr r3, [r7, #12]
|
|
800ea3c: 681b ldr r3, [r3, #0]
|
|
800ea3e: 430a orrs r2, r1
|
|
800ea40: 655a str r2, [r3, #84] @ 0x54
|
|
break;
|
|
800ea42: e023 b.n 800ea8c <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 6 in PWM mode */
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
800ea44: 68fb ldr r3, [r7, #12]
|
|
800ea46: 681b ldr r3, [r3, #0]
|
|
800ea48: 68b9 ldr r1, [r7, #8]
|
|
800ea4a: 4618 mov r0, r3
|
|
800ea4c: f000 fae4 bl 800f018 <TIM_OC6_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel6 */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
800ea50: 68fb ldr r3, [r7, #12]
|
|
800ea52: 681b ldr r3, [r3, #0]
|
|
800ea54: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
800ea56: 68fb ldr r3, [r7, #12]
|
|
800ea58: 681b ldr r3, [r3, #0]
|
|
800ea5a: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
800ea5e: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
800ea60: 68fb ldr r3, [r7, #12]
|
|
800ea62: 681b ldr r3, [r3, #0]
|
|
800ea64: 6d5a ldr r2, [r3, #84] @ 0x54
|
|
800ea66: 68fb ldr r3, [r7, #12]
|
|
800ea68: 681b ldr r3, [r3, #0]
|
|
800ea6a: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
800ea6e: 655a str r2, [r3, #84] @ 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
800ea70: 68fb ldr r3, [r7, #12]
|
|
800ea72: 681b ldr r3, [r3, #0]
|
|
800ea74: 6d59 ldr r1, [r3, #84] @ 0x54
|
|
800ea76: 68bb ldr r3, [r7, #8]
|
|
800ea78: 691b ldr r3, [r3, #16]
|
|
800ea7a: 021a lsls r2, r3, #8
|
|
800ea7c: 68fb ldr r3, [r7, #12]
|
|
800ea7e: 681b ldr r3, [r3, #0]
|
|
800ea80: 430a orrs r2, r1
|
|
800ea82: 655a str r2, [r3, #84] @ 0x54
|
|
break;
|
|
800ea84: e002 b.n 800ea8c <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
800ea86: 2301 movs r3, #1
|
|
800ea88: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800ea8a: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800ea8c: 68fb ldr r3, [r7, #12]
|
|
800ea8e: 2200 movs r2, #0
|
|
800ea90: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
800ea94: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800ea96: 4618 mov r0, r3
|
|
800ea98: 3718 adds r7, #24
|
|
800ea9a: 46bd mov sp, r7
|
|
800ea9c: bd80 pop {r7, pc}
|
|
800ea9e: bf00 nop
|
|
|
|
0800eaa0 <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800eaa0: b480 push {r7}
|
|
800eaa2: b083 sub sp, #12
|
|
800eaa4: af00 add r7, sp, #0
|
|
800eaa6: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800eaa8: bf00 nop
|
|
800eaaa: 370c adds r7, #12
|
|
800eaac: 46bd mov sp, r7
|
|
800eaae: f85d 7b04 ldr.w r7, [sp], #4
|
|
800eab2: 4770 bx lr
|
|
|
|
0800eab4 <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800eab4: b480 push {r7}
|
|
800eab6: b083 sub sp, #12
|
|
800eab8: af00 add r7, sp, #0
|
|
800eaba: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800eabc: bf00 nop
|
|
800eabe: 370c adds r7, #12
|
|
800eac0: 46bd mov sp, r7
|
|
800eac2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800eac6: 4770 bx lr
|
|
|
|
0800eac8 <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800eac8: b480 push {r7}
|
|
800eaca: b083 sub sp, #12
|
|
800eacc: af00 add r7, sp, #0
|
|
800eace: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800ead0: bf00 nop
|
|
800ead2: 370c adds r7, #12
|
|
800ead4: 46bd mov sp, r7
|
|
800ead6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800eada: 4770 bx lr
|
|
|
|
0800eadc <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800eadc: b480 push {r7}
|
|
800eade: b083 sub sp, #12
|
|
800eae0: af00 add r7, sp, #0
|
|
800eae2: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800eae4: bf00 nop
|
|
800eae6: 370c adds r7, #12
|
|
800eae8: 46bd mov sp, r7
|
|
800eaea: f85d 7b04 ldr.w r7, [sp], #4
|
|
800eaee: 4770 bx lr
|
|
|
|
0800eaf0 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
800eaf0: b480 push {r7}
|
|
800eaf2: b085 sub sp, #20
|
|
800eaf4: af00 add r7, sp, #0
|
|
800eaf6: 6078 str r0, [r7, #4]
|
|
800eaf8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800eafa: 687b ldr r3, [r7, #4]
|
|
800eafc: 681b ldr r3, [r3, #0]
|
|
800eafe: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
800eb00: 687b ldr r3, [r7, #4]
|
|
800eb02: 4a2d ldr r2, [pc, #180] @ (800ebb8 <TIM_Base_SetConfig+0xc8>)
|
|
800eb04: 4293 cmp r3, r2
|
|
800eb06: d003 beq.n 800eb10 <TIM_Base_SetConfig+0x20>
|
|
800eb08: 687b ldr r3, [r7, #4]
|
|
800eb0a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800eb0e: d108 bne.n 800eb22 <TIM_Base_SetConfig+0x32>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
800eb10: 68fb ldr r3, [r7, #12]
|
|
800eb12: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800eb16: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
800eb18: 683b ldr r3, [r7, #0]
|
|
800eb1a: 685b ldr r3, [r3, #4]
|
|
800eb1c: 68fa ldr r2, [r7, #12]
|
|
800eb1e: 4313 orrs r3, r2
|
|
800eb20: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
800eb22: 687b ldr r3, [r7, #4]
|
|
800eb24: 4a24 ldr r2, [pc, #144] @ (800ebb8 <TIM_Base_SetConfig+0xc8>)
|
|
800eb26: 4293 cmp r3, r2
|
|
800eb28: d00b beq.n 800eb42 <TIM_Base_SetConfig+0x52>
|
|
800eb2a: 687b ldr r3, [r7, #4]
|
|
800eb2c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800eb30: d007 beq.n 800eb42 <TIM_Base_SetConfig+0x52>
|
|
800eb32: 687b ldr r3, [r7, #4]
|
|
800eb34: 4a21 ldr r2, [pc, #132] @ (800ebbc <TIM_Base_SetConfig+0xcc>)
|
|
800eb36: 4293 cmp r3, r2
|
|
800eb38: d003 beq.n 800eb42 <TIM_Base_SetConfig+0x52>
|
|
800eb3a: 687b ldr r3, [r7, #4]
|
|
800eb3c: 4a20 ldr r2, [pc, #128] @ (800ebc0 <TIM_Base_SetConfig+0xd0>)
|
|
800eb3e: 4293 cmp r3, r2
|
|
800eb40: d108 bne.n 800eb54 <TIM_Base_SetConfig+0x64>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
800eb42: 68fb ldr r3, [r7, #12]
|
|
800eb44: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800eb48: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
800eb4a: 683b ldr r3, [r7, #0]
|
|
800eb4c: 68db ldr r3, [r3, #12]
|
|
800eb4e: 68fa ldr r2, [r7, #12]
|
|
800eb50: 4313 orrs r3, r2
|
|
800eb52: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
800eb54: 68fb ldr r3, [r7, #12]
|
|
800eb56: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
800eb5a: 683b ldr r3, [r7, #0]
|
|
800eb5c: 695b ldr r3, [r3, #20]
|
|
800eb5e: 4313 orrs r3, r2
|
|
800eb60: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
800eb62: 683b ldr r3, [r7, #0]
|
|
800eb64: 689a ldr r2, [r3, #8]
|
|
800eb66: 687b ldr r3, [r7, #4]
|
|
800eb68: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
800eb6a: 683b ldr r3, [r7, #0]
|
|
800eb6c: 681a ldr r2, [r3, #0]
|
|
800eb6e: 687b ldr r3, [r7, #4]
|
|
800eb70: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
800eb72: 687b ldr r3, [r7, #4]
|
|
800eb74: 4a10 ldr r2, [pc, #64] @ (800ebb8 <TIM_Base_SetConfig+0xc8>)
|
|
800eb76: 4293 cmp r3, r2
|
|
800eb78: d007 beq.n 800eb8a <TIM_Base_SetConfig+0x9a>
|
|
800eb7a: 687b ldr r3, [r7, #4]
|
|
800eb7c: 4a0f ldr r2, [pc, #60] @ (800ebbc <TIM_Base_SetConfig+0xcc>)
|
|
800eb7e: 4293 cmp r3, r2
|
|
800eb80: d003 beq.n 800eb8a <TIM_Base_SetConfig+0x9a>
|
|
800eb82: 687b ldr r3, [r7, #4]
|
|
800eb84: 4a0e ldr r2, [pc, #56] @ (800ebc0 <TIM_Base_SetConfig+0xd0>)
|
|
800eb86: 4293 cmp r3, r2
|
|
800eb88: d103 bne.n 800eb92 <TIM_Base_SetConfig+0xa2>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
800eb8a: 683b ldr r3, [r7, #0]
|
|
800eb8c: 691a ldr r2, [r3, #16]
|
|
800eb8e: 687b ldr r3, [r7, #4]
|
|
800eb90: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Disable Update Event (UEV) with Update Generation (UG)
|
|
by changing Update Request Source (URS) to avoid Update flag (UIF) */
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
800eb92: 687b ldr r3, [r7, #4]
|
|
800eb94: 681b ldr r3, [r3, #0]
|
|
800eb96: f043 0204 orr.w r2, r3, #4
|
|
800eb9a: 687b ldr r3, [r7, #4]
|
|
800eb9c: 601a str r2, [r3, #0]
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
800eb9e: 687b ldr r3, [r7, #4]
|
|
800eba0: 2201 movs r2, #1
|
|
800eba2: 615a str r2, [r3, #20]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
800eba4: 687b ldr r3, [r7, #4]
|
|
800eba6: 68fa ldr r2, [r7, #12]
|
|
800eba8: 601a str r2, [r3, #0]
|
|
}
|
|
800ebaa: bf00 nop
|
|
800ebac: 3714 adds r7, #20
|
|
800ebae: 46bd mov sp, r7
|
|
800ebb0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ebb4: 4770 bx lr
|
|
800ebb6: bf00 nop
|
|
800ebb8: 40012c00 .word 0x40012c00
|
|
800ebbc: 40014400 .word 0x40014400
|
|
800ebc0: 40014800 .word 0x40014800
|
|
|
|
0800ebc4 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800ebc4: b480 push {r7}
|
|
800ebc6: b087 sub sp, #28
|
|
800ebc8: af00 add r7, sp, #0
|
|
800ebca: 6078 str r0, [r7, #4]
|
|
800ebcc: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800ebce: 687b ldr r3, [r7, #4]
|
|
800ebd0: 6a1b ldr r3, [r3, #32]
|
|
800ebd2: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
800ebd4: 687b ldr r3, [r7, #4]
|
|
800ebd6: 6a1b ldr r3, [r3, #32]
|
|
800ebd8: f023 0201 bic.w r2, r3, #1
|
|
800ebdc: 687b ldr r3, [r7, #4]
|
|
800ebde: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800ebe0: 687b ldr r3, [r7, #4]
|
|
800ebe2: 685b ldr r3, [r3, #4]
|
|
800ebe4: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
800ebe6: 687b ldr r3, [r7, #4]
|
|
800ebe8: 699b ldr r3, [r3, #24]
|
|
800ebea: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
800ebec: 68fb ldr r3, [r7, #12]
|
|
800ebee: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800ebf2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800ebf6: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
800ebf8: 68fb ldr r3, [r7, #12]
|
|
800ebfa: f023 0303 bic.w r3, r3, #3
|
|
800ebfe: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
800ec00: 683b ldr r3, [r7, #0]
|
|
800ec02: 681b ldr r3, [r3, #0]
|
|
800ec04: 68fa ldr r2, [r7, #12]
|
|
800ec06: 4313 orrs r3, r2
|
|
800ec08: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
800ec0a: 697b ldr r3, [r7, #20]
|
|
800ec0c: f023 0302 bic.w r3, r3, #2
|
|
800ec10: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
800ec12: 683b ldr r3, [r7, #0]
|
|
800ec14: 689b ldr r3, [r3, #8]
|
|
800ec16: 697a ldr r2, [r7, #20]
|
|
800ec18: 4313 orrs r3, r2
|
|
800ec1a: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
800ec1c: 687b ldr r3, [r7, #4]
|
|
800ec1e: 4a25 ldr r2, [pc, #148] @ (800ecb4 <TIM_OC1_SetConfig+0xf0>)
|
|
800ec20: 4293 cmp r3, r2
|
|
800ec22: d007 beq.n 800ec34 <TIM_OC1_SetConfig+0x70>
|
|
800ec24: 687b ldr r3, [r7, #4]
|
|
800ec26: 4a24 ldr r2, [pc, #144] @ (800ecb8 <TIM_OC1_SetConfig+0xf4>)
|
|
800ec28: 4293 cmp r3, r2
|
|
800ec2a: d003 beq.n 800ec34 <TIM_OC1_SetConfig+0x70>
|
|
800ec2c: 687b ldr r3, [r7, #4]
|
|
800ec2e: 4a23 ldr r2, [pc, #140] @ (800ecbc <TIM_OC1_SetConfig+0xf8>)
|
|
800ec30: 4293 cmp r3, r2
|
|
800ec32: d10e bne.n 800ec52 <TIM_OC1_SetConfig+0x8e>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Disable the Channel 1N: Reset the CC1NE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1NE;
|
|
800ec34: 687b ldr r3, [r7, #4]
|
|
800ec36: 6a1b ldr r3, [r3, #32]
|
|
800ec38: f023 0204 bic.w r2, r3, #4
|
|
800ec3c: 687b ldr r3, [r7, #4]
|
|
800ec3e: 621a str r2, [r3, #32]
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
800ec40: 697b ldr r3, [r7, #20]
|
|
800ec42: f023 0308 bic.w r3, r3, #8
|
|
800ec46: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
800ec48: 683b ldr r3, [r7, #0]
|
|
800ec4a: 68db ldr r3, [r3, #12]
|
|
800ec4c: 697a ldr r2, [r7, #20]
|
|
800ec4e: 4313 orrs r3, r2
|
|
800ec50: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800ec52: 687b ldr r3, [r7, #4]
|
|
800ec54: 4a17 ldr r2, [pc, #92] @ (800ecb4 <TIM_OC1_SetConfig+0xf0>)
|
|
800ec56: 4293 cmp r3, r2
|
|
800ec58: d007 beq.n 800ec6a <TIM_OC1_SetConfig+0xa6>
|
|
800ec5a: 687b ldr r3, [r7, #4]
|
|
800ec5c: 4a17 ldr r2, [pc, #92] @ (800ecbc <TIM_OC1_SetConfig+0xf8>)
|
|
800ec5e: 4293 cmp r3, r2
|
|
800ec60: d003 beq.n 800ec6a <TIM_OC1_SetConfig+0xa6>
|
|
800ec62: 687b ldr r3, [r7, #4]
|
|
800ec64: 4a14 ldr r2, [pc, #80] @ (800ecb8 <TIM_OC1_SetConfig+0xf4>)
|
|
800ec66: 4293 cmp r3, r2
|
|
800ec68: d111 bne.n 800ec8e <TIM_OC1_SetConfig+0xca>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
800ec6a: 693b ldr r3, [r7, #16]
|
|
800ec6c: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800ec70: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
800ec72: 693b ldr r3, [r7, #16]
|
|
800ec74: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
800ec78: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
800ec7a: 683b ldr r3, [r7, #0]
|
|
800ec7c: 695b ldr r3, [r3, #20]
|
|
800ec7e: 693a ldr r2, [r7, #16]
|
|
800ec80: 4313 orrs r3, r2
|
|
800ec82: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
800ec84: 683b ldr r3, [r7, #0]
|
|
800ec86: 699b ldr r3, [r3, #24]
|
|
800ec88: 693a ldr r2, [r7, #16]
|
|
800ec8a: 4313 orrs r3, r2
|
|
800ec8c: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800ec8e: 687b ldr r3, [r7, #4]
|
|
800ec90: 693a ldr r2, [r7, #16]
|
|
800ec92: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800ec94: 687b ldr r3, [r7, #4]
|
|
800ec96: 68fa ldr r2, [r7, #12]
|
|
800ec98: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
800ec9a: 683b ldr r3, [r7, #0]
|
|
800ec9c: 685a ldr r2, [r3, #4]
|
|
800ec9e: 687b ldr r3, [r7, #4]
|
|
800eca0: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800eca2: 687b ldr r3, [r7, #4]
|
|
800eca4: 697a ldr r2, [r7, #20]
|
|
800eca6: 621a str r2, [r3, #32]
|
|
}
|
|
800eca8: bf00 nop
|
|
800ecaa: 371c adds r7, #28
|
|
800ecac: 46bd mov sp, r7
|
|
800ecae: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ecb2: 4770 bx lr
|
|
800ecb4: 40012c00 .word 0x40012c00
|
|
800ecb8: 40014800 .word 0x40014800
|
|
800ecbc: 40014400 .word 0x40014400
|
|
|
|
0800ecc0 <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800ecc0: b480 push {r7}
|
|
800ecc2: b087 sub sp, #28
|
|
800ecc4: af00 add r7, sp, #0
|
|
800ecc6: 6078 str r0, [r7, #4]
|
|
800ecc8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800ecca: 687b ldr r3, [r7, #4]
|
|
800eccc: 6a1b ldr r3, [r3, #32]
|
|
800ecce: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
800ecd0: 687b ldr r3, [r7, #4]
|
|
800ecd2: 6a1b ldr r3, [r3, #32]
|
|
800ecd4: f023 0210 bic.w r2, r3, #16
|
|
800ecd8: 687b ldr r3, [r7, #4]
|
|
800ecda: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800ecdc: 687b ldr r3, [r7, #4]
|
|
800ecde: 685b ldr r3, [r3, #4]
|
|
800ece0: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
800ece2: 687b ldr r3, [r7, #4]
|
|
800ece4: 699b ldr r3, [r3, #24]
|
|
800ece6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
800ece8: 68fb ldr r3, [r7, #12]
|
|
800ecea: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800ecee: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800ecf2: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
800ecf4: 68fb ldr r3, [r7, #12]
|
|
800ecf6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800ecfa: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800ecfc: 683b ldr r3, [r7, #0]
|
|
800ecfe: 681b ldr r3, [r3, #0]
|
|
800ed00: 021b lsls r3, r3, #8
|
|
800ed02: 68fa ldr r2, [r7, #12]
|
|
800ed04: 4313 orrs r3, r2
|
|
800ed06: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
800ed08: 697b ldr r3, [r7, #20]
|
|
800ed0a: f023 0320 bic.w r3, r3, #32
|
|
800ed0e: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
800ed10: 683b ldr r3, [r7, #0]
|
|
800ed12: 689b ldr r3, [r3, #8]
|
|
800ed14: 011b lsls r3, r3, #4
|
|
800ed16: 697a ldr r2, [r7, #20]
|
|
800ed18: 4313 orrs r3, r2
|
|
800ed1a: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
800ed1c: 687b ldr r3, [r7, #4]
|
|
800ed1e: 4a23 ldr r2, [pc, #140] @ (800edac <TIM_OC2_SetConfig+0xec>)
|
|
800ed20: 4293 cmp r3, r2
|
|
800ed22: d10f bne.n 800ed44 <TIM_OC2_SetConfig+0x84>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Disable the Channel 2N: Reset the CC2NE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2NE;
|
|
800ed24: 687b ldr r3, [r7, #4]
|
|
800ed26: 6a1b ldr r3, [r3, #32]
|
|
800ed28: f023 0240 bic.w r2, r3, #64 @ 0x40
|
|
800ed2c: 687b ldr r3, [r7, #4]
|
|
800ed2e: 621a str r2, [r3, #32]
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
800ed30: 697b ldr r3, [r7, #20]
|
|
800ed32: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
800ed36: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
800ed38: 683b ldr r3, [r7, #0]
|
|
800ed3a: 68db ldr r3, [r3, #12]
|
|
800ed3c: 011b lsls r3, r3, #4
|
|
800ed3e: 697a ldr r2, [r7, #20]
|
|
800ed40: 4313 orrs r3, r2
|
|
800ed42: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800ed44: 687b ldr r3, [r7, #4]
|
|
800ed46: 4a19 ldr r2, [pc, #100] @ (800edac <TIM_OC2_SetConfig+0xec>)
|
|
800ed48: 4293 cmp r3, r2
|
|
800ed4a: d007 beq.n 800ed5c <TIM_OC2_SetConfig+0x9c>
|
|
800ed4c: 687b ldr r3, [r7, #4]
|
|
800ed4e: 4a18 ldr r2, [pc, #96] @ (800edb0 <TIM_OC2_SetConfig+0xf0>)
|
|
800ed50: 4293 cmp r3, r2
|
|
800ed52: d003 beq.n 800ed5c <TIM_OC2_SetConfig+0x9c>
|
|
800ed54: 687b ldr r3, [r7, #4]
|
|
800ed56: 4a17 ldr r2, [pc, #92] @ (800edb4 <TIM_OC2_SetConfig+0xf4>)
|
|
800ed58: 4293 cmp r3, r2
|
|
800ed5a: d113 bne.n 800ed84 <TIM_OC2_SetConfig+0xc4>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
800ed5c: 693b ldr r3, [r7, #16]
|
|
800ed5e: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
800ed62: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
800ed64: 693b ldr r3, [r7, #16]
|
|
800ed66: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
800ed6a: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
800ed6c: 683b ldr r3, [r7, #0]
|
|
800ed6e: 695b ldr r3, [r3, #20]
|
|
800ed70: 009b lsls r3, r3, #2
|
|
800ed72: 693a ldr r2, [r7, #16]
|
|
800ed74: 4313 orrs r3, r2
|
|
800ed76: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
800ed78: 683b ldr r3, [r7, #0]
|
|
800ed7a: 699b ldr r3, [r3, #24]
|
|
800ed7c: 009b lsls r3, r3, #2
|
|
800ed7e: 693a ldr r2, [r7, #16]
|
|
800ed80: 4313 orrs r3, r2
|
|
800ed82: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800ed84: 687b ldr r3, [r7, #4]
|
|
800ed86: 693a ldr r2, [r7, #16]
|
|
800ed88: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800ed8a: 687b ldr r3, [r7, #4]
|
|
800ed8c: 68fa ldr r2, [r7, #12]
|
|
800ed8e: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
800ed90: 683b ldr r3, [r7, #0]
|
|
800ed92: 685a ldr r2, [r3, #4]
|
|
800ed94: 687b ldr r3, [r7, #4]
|
|
800ed96: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800ed98: 687b ldr r3, [r7, #4]
|
|
800ed9a: 697a ldr r2, [r7, #20]
|
|
800ed9c: 621a str r2, [r3, #32]
|
|
}
|
|
800ed9e: bf00 nop
|
|
800eda0: 371c adds r7, #28
|
|
800eda2: 46bd mov sp, r7
|
|
800eda4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800eda8: 4770 bx lr
|
|
800edaa: bf00 nop
|
|
800edac: 40012c00 .word 0x40012c00
|
|
800edb0: 40014400 .word 0x40014400
|
|
800edb4: 40014800 .word 0x40014800
|
|
|
|
0800edb8 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800edb8: b480 push {r7}
|
|
800edba: b087 sub sp, #28
|
|
800edbc: af00 add r7, sp, #0
|
|
800edbe: 6078 str r0, [r7, #4]
|
|
800edc0: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800edc2: 687b ldr r3, [r7, #4]
|
|
800edc4: 6a1b ldr r3, [r3, #32]
|
|
800edc6: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
800edc8: 687b ldr r3, [r7, #4]
|
|
800edca: 6a1b ldr r3, [r3, #32]
|
|
800edcc: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
800edd0: 687b ldr r3, [r7, #4]
|
|
800edd2: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800edd4: 687b ldr r3, [r7, #4]
|
|
800edd6: 685b ldr r3, [r3, #4]
|
|
800edd8: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
800edda: 687b ldr r3, [r7, #4]
|
|
800eddc: 69db ldr r3, [r3, #28]
|
|
800edde: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
800ede0: 68fb ldr r3, [r7, #12]
|
|
800ede2: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800ede6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800edea: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
800edec: 68fb ldr r3, [r7, #12]
|
|
800edee: f023 0303 bic.w r3, r3, #3
|
|
800edf2: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
800edf4: 683b ldr r3, [r7, #0]
|
|
800edf6: 681b ldr r3, [r3, #0]
|
|
800edf8: 68fa ldr r2, [r7, #12]
|
|
800edfa: 4313 orrs r3, r2
|
|
800edfc: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
800edfe: 697b ldr r3, [r7, #20]
|
|
800ee00: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
800ee04: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
800ee06: 683b ldr r3, [r7, #0]
|
|
800ee08: 689b ldr r3, [r3, #8]
|
|
800ee0a: 021b lsls r3, r3, #8
|
|
800ee0c: 697a ldr r2, [r7, #20]
|
|
800ee0e: 4313 orrs r3, r2
|
|
800ee10: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
800ee12: 687b ldr r3, [r7, #4]
|
|
800ee14: 4a22 ldr r2, [pc, #136] @ (800eea0 <TIM_OC3_SetConfig+0xe8>)
|
|
800ee16: 4293 cmp r3, r2
|
|
800ee18: d10f bne.n 800ee3a <TIM_OC3_SetConfig+0x82>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Disable the Channel 3N: Reset the CC3NE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3NE;
|
|
800ee1a: 687b ldr r3, [r7, #4]
|
|
800ee1c: 6a1b ldr r3, [r3, #32]
|
|
800ee1e: f423 6280 bic.w r2, r3, #1024 @ 0x400
|
|
800ee22: 687b ldr r3, [r7, #4]
|
|
800ee24: 621a str r2, [r3, #32]
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
800ee26: 697b ldr r3, [r7, #20]
|
|
800ee28: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
800ee2c: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
800ee2e: 683b ldr r3, [r7, #0]
|
|
800ee30: 68db ldr r3, [r3, #12]
|
|
800ee32: 021b lsls r3, r3, #8
|
|
800ee34: 697a ldr r2, [r7, #20]
|
|
800ee36: 4313 orrs r3, r2
|
|
800ee38: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800ee3a: 687b ldr r3, [r7, #4]
|
|
800ee3c: 4a18 ldr r2, [pc, #96] @ (800eea0 <TIM_OC3_SetConfig+0xe8>)
|
|
800ee3e: 4293 cmp r3, r2
|
|
800ee40: d007 beq.n 800ee52 <TIM_OC3_SetConfig+0x9a>
|
|
800ee42: 687b ldr r3, [r7, #4]
|
|
800ee44: 4a17 ldr r2, [pc, #92] @ (800eea4 <TIM_OC3_SetConfig+0xec>)
|
|
800ee46: 4293 cmp r3, r2
|
|
800ee48: d003 beq.n 800ee52 <TIM_OC3_SetConfig+0x9a>
|
|
800ee4a: 687b ldr r3, [r7, #4]
|
|
800ee4c: 4a16 ldr r2, [pc, #88] @ (800eea8 <TIM_OC3_SetConfig+0xf0>)
|
|
800ee4e: 4293 cmp r3, r2
|
|
800ee50: d113 bne.n 800ee7a <TIM_OC3_SetConfig+0xc2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
800ee52: 693b ldr r3, [r7, #16]
|
|
800ee54: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
800ee58: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
800ee5a: 693b ldr r3, [r7, #16]
|
|
800ee5c: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
800ee60: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
800ee62: 683b ldr r3, [r7, #0]
|
|
800ee64: 695b ldr r3, [r3, #20]
|
|
800ee66: 011b lsls r3, r3, #4
|
|
800ee68: 693a ldr r2, [r7, #16]
|
|
800ee6a: 4313 orrs r3, r2
|
|
800ee6c: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
800ee6e: 683b ldr r3, [r7, #0]
|
|
800ee70: 699b ldr r3, [r3, #24]
|
|
800ee72: 011b lsls r3, r3, #4
|
|
800ee74: 693a ldr r2, [r7, #16]
|
|
800ee76: 4313 orrs r3, r2
|
|
800ee78: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800ee7a: 687b ldr r3, [r7, #4]
|
|
800ee7c: 693a ldr r2, [r7, #16]
|
|
800ee7e: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800ee80: 687b ldr r3, [r7, #4]
|
|
800ee82: 68fa ldr r2, [r7, #12]
|
|
800ee84: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
800ee86: 683b ldr r3, [r7, #0]
|
|
800ee88: 685a ldr r2, [r3, #4]
|
|
800ee8a: 687b ldr r3, [r7, #4]
|
|
800ee8c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800ee8e: 687b ldr r3, [r7, #4]
|
|
800ee90: 697a ldr r2, [r7, #20]
|
|
800ee92: 621a str r2, [r3, #32]
|
|
}
|
|
800ee94: bf00 nop
|
|
800ee96: 371c adds r7, #28
|
|
800ee98: 46bd mov sp, r7
|
|
800ee9a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ee9e: 4770 bx lr
|
|
800eea0: 40012c00 .word 0x40012c00
|
|
800eea4: 40014400 .word 0x40014400
|
|
800eea8: 40014800 .word 0x40014800
|
|
|
|
0800eeac <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800eeac: b480 push {r7}
|
|
800eeae: b087 sub sp, #28
|
|
800eeb0: af00 add r7, sp, #0
|
|
800eeb2: 6078 str r0, [r7, #4]
|
|
800eeb4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800eeb6: 687b ldr r3, [r7, #4]
|
|
800eeb8: 6a1b ldr r3, [r3, #32]
|
|
800eeba: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
800eebc: 687b ldr r3, [r7, #4]
|
|
800eebe: 6a1b ldr r3, [r3, #32]
|
|
800eec0: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
800eec4: 687b ldr r3, [r7, #4]
|
|
800eec6: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800eec8: 687b ldr r3, [r7, #4]
|
|
800eeca: 685b ldr r3, [r3, #4]
|
|
800eecc: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
800eece: 687b ldr r3, [r7, #4]
|
|
800eed0: 69db ldr r3, [r3, #28]
|
|
800eed2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
800eed4: 68fb ldr r3, [r7, #12]
|
|
800eed6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800eeda: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800eede: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
800eee0: 68fb ldr r3, [r7, #12]
|
|
800eee2: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800eee6: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800eee8: 683b ldr r3, [r7, #0]
|
|
800eeea: 681b ldr r3, [r3, #0]
|
|
800eeec: 021b lsls r3, r3, #8
|
|
800eeee: 68fa ldr r2, [r7, #12]
|
|
800eef0: 4313 orrs r3, r2
|
|
800eef2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
800eef4: 693b ldr r3, [r7, #16]
|
|
800eef6: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
800eefa: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
800eefc: 683b ldr r3, [r7, #0]
|
|
800eefe: 689b ldr r3, [r3, #8]
|
|
800ef00: 031b lsls r3, r3, #12
|
|
800ef02: 693a ldr r2, [r7, #16]
|
|
800ef04: 4313 orrs r3, r2
|
|
800ef06: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800ef08: 687b ldr r3, [r7, #4]
|
|
800ef0a: 4a14 ldr r2, [pc, #80] @ (800ef5c <TIM_OC4_SetConfig+0xb0>)
|
|
800ef0c: 4293 cmp r3, r2
|
|
800ef0e: d007 beq.n 800ef20 <TIM_OC4_SetConfig+0x74>
|
|
800ef10: 687b ldr r3, [r7, #4]
|
|
800ef12: 4a13 ldr r2, [pc, #76] @ (800ef60 <TIM_OC4_SetConfig+0xb4>)
|
|
800ef14: 4293 cmp r3, r2
|
|
800ef16: d003 beq.n 800ef20 <TIM_OC4_SetConfig+0x74>
|
|
800ef18: 687b ldr r3, [r7, #4]
|
|
800ef1a: 4a12 ldr r2, [pc, #72] @ (800ef64 <TIM_OC4_SetConfig+0xb8>)
|
|
800ef1c: 4293 cmp r3, r2
|
|
800ef1e: d109 bne.n 800ef34 <TIM_OC4_SetConfig+0x88>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
800ef20: 697b ldr r3, [r7, #20]
|
|
800ef22: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800ef26: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
800ef28: 683b ldr r3, [r7, #0]
|
|
800ef2a: 695b ldr r3, [r3, #20]
|
|
800ef2c: 019b lsls r3, r3, #6
|
|
800ef2e: 697a ldr r2, [r7, #20]
|
|
800ef30: 4313 orrs r3, r2
|
|
800ef32: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800ef34: 687b ldr r3, [r7, #4]
|
|
800ef36: 697a ldr r2, [r7, #20]
|
|
800ef38: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800ef3a: 687b ldr r3, [r7, #4]
|
|
800ef3c: 68fa ldr r2, [r7, #12]
|
|
800ef3e: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
800ef40: 683b ldr r3, [r7, #0]
|
|
800ef42: 685a ldr r2, [r3, #4]
|
|
800ef44: 687b ldr r3, [r7, #4]
|
|
800ef46: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800ef48: 687b ldr r3, [r7, #4]
|
|
800ef4a: 693a ldr r2, [r7, #16]
|
|
800ef4c: 621a str r2, [r3, #32]
|
|
}
|
|
800ef4e: bf00 nop
|
|
800ef50: 371c adds r7, #28
|
|
800ef52: 46bd mov sp, r7
|
|
800ef54: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ef58: 4770 bx lr
|
|
800ef5a: bf00 nop
|
|
800ef5c: 40012c00 .word 0x40012c00
|
|
800ef60: 40014400 .word 0x40014400
|
|
800ef64: 40014800 .word 0x40014800
|
|
|
|
0800ef68 <TIM_OC5_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800ef68: b480 push {r7}
|
|
800ef6a: b087 sub sp, #28
|
|
800ef6c: af00 add r7, sp, #0
|
|
800ef6e: 6078 str r0, [r7, #4]
|
|
800ef70: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800ef72: 687b ldr r3, [r7, #4]
|
|
800ef74: 6a1b ldr r3, [r3, #32]
|
|
800ef76: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
800ef78: 687b ldr r3, [r7, #4]
|
|
800ef7a: 6a1b ldr r3, [r3, #32]
|
|
800ef7c: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
800ef80: 687b ldr r3, [r7, #4]
|
|
800ef82: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800ef84: 687b ldr r3, [r7, #4]
|
|
800ef86: 685b ldr r3, [r3, #4]
|
|
800ef88: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
800ef8a: 687b ldr r3, [r7, #4]
|
|
800ef8c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800ef8e: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
800ef90: 68fb ldr r3, [r7, #12]
|
|
800ef92: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800ef96: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800ef9a: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
800ef9c: 683b ldr r3, [r7, #0]
|
|
800ef9e: 681b ldr r3, [r3, #0]
|
|
800efa0: 68fa ldr r2, [r7, #12]
|
|
800efa2: 4313 orrs r3, r2
|
|
800efa4: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
800efa6: 693b ldr r3, [r7, #16]
|
|
800efa8: f423 3300 bic.w r3, r3, #131072 @ 0x20000
|
|
800efac: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
800efae: 683b ldr r3, [r7, #0]
|
|
800efb0: 689b ldr r3, [r3, #8]
|
|
800efb2: 041b lsls r3, r3, #16
|
|
800efb4: 693a ldr r2, [r7, #16]
|
|
800efb6: 4313 orrs r3, r2
|
|
800efb8: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800efba: 687b ldr r3, [r7, #4]
|
|
800efbc: 4a13 ldr r2, [pc, #76] @ (800f00c <TIM_OC5_SetConfig+0xa4>)
|
|
800efbe: 4293 cmp r3, r2
|
|
800efc0: d007 beq.n 800efd2 <TIM_OC5_SetConfig+0x6a>
|
|
800efc2: 687b ldr r3, [r7, #4]
|
|
800efc4: 4a12 ldr r2, [pc, #72] @ (800f010 <TIM_OC5_SetConfig+0xa8>)
|
|
800efc6: 4293 cmp r3, r2
|
|
800efc8: d003 beq.n 800efd2 <TIM_OC5_SetConfig+0x6a>
|
|
800efca: 687b ldr r3, [r7, #4]
|
|
800efcc: 4a11 ldr r2, [pc, #68] @ (800f014 <TIM_OC5_SetConfig+0xac>)
|
|
800efce: 4293 cmp r3, r2
|
|
800efd0: d109 bne.n 800efe6 <TIM_OC5_SetConfig+0x7e>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
800efd2: 697b ldr r3, [r7, #20]
|
|
800efd4: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800efd8: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
800efda: 683b ldr r3, [r7, #0]
|
|
800efdc: 695b ldr r3, [r3, #20]
|
|
800efde: 021b lsls r3, r3, #8
|
|
800efe0: 697a ldr r2, [r7, #20]
|
|
800efe2: 4313 orrs r3, r2
|
|
800efe4: 617b str r3, [r7, #20]
|
|
}
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800efe6: 687b ldr r3, [r7, #4]
|
|
800efe8: 697a ldr r2, [r7, #20]
|
|
800efea: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
800efec: 687b ldr r3, [r7, #4]
|
|
800efee: 68fa ldr r2, [r7, #12]
|
|
800eff0: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
800eff2: 683b ldr r3, [r7, #0]
|
|
800eff4: 685a ldr r2, [r3, #4]
|
|
800eff6: 687b ldr r3, [r7, #4]
|
|
800eff8: 659a str r2, [r3, #88] @ 0x58
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800effa: 687b ldr r3, [r7, #4]
|
|
800effc: 693a ldr r2, [r7, #16]
|
|
800effe: 621a str r2, [r3, #32]
|
|
}
|
|
800f000: bf00 nop
|
|
800f002: 371c adds r7, #28
|
|
800f004: 46bd mov sp, r7
|
|
800f006: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f00a: 4770 bx lr
|
|
800f00c: 40012c00 .word 0x40012c00
|
|
800f010: 40014400 .word 0x40014400
|
|
800f014: 40014800 .word 0x40014800
|
|
|
|
0800f018 <TIM_OC6_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800f018: b480 push {r7}
|
|
800f01a: b087 sub sp, #28
|
|
800f01c: af00 add r7, sp, #0
|
|
800f01e: 6078 str r0, [r7, #4]
|
|
800f020: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800f022: 687b ldr r3, [r7, #4]
|
|
800f024: 6a1b ldr r3, [r3, #32]
|
|
800f026: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
800f028: 687b ldr r3, [r7, #4]
|
|
800f02a: 6a1b ldr r3, [r3, #32]
|
|
800f02c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
|
|
800f030: 687b ldr r3, [r7, #4]
|
|
800f032: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800f034: 687b ldr r3, [r7, #4]
|
|
800f036: 685b ldr r3, [r3, #4]
|
|
800f038: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
800f03a: 687b ldr r3, [r7, #4]
|
|
800f03c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800f03e: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
800f040: 68fb ldr r3, [r7, #12]
|
|
800f042: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800f046: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f04a: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800f04c: 683b ldr r3, [r7, #0]
|
|
800f04e: 681b ldr r3, [r3, #0]
|
|
800f050: 021b lsls r3, r3, #8
|
|
800f052: 68fa ldr r2, [r7, #12]
|
|
800f054: 4313 orrs r3, r2
|
|
800f056: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
800f058: 693b ldr r3, [r7, #16]
|
|
800f05a: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
800f05e: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
800f060: 683b ldr r3, [r7, #0]
|
|
800f062: 689b ldr r3, [r3, #8]
|
|
800f064: 051b lsls r3, r3, #20
|
|
800f066: 693a ldr r2, [r7, #16]
|
|
800f068: 4313 orrs r3, r2
|
|
800f06a: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800f06c: 687b ldr r3, [r7, #4]
|
|
800f06e: 4a14 ldr r2, [pc, #80] @ (800f0c0 <TIM_OC6_SetConfig+0xa8>)
|
|
800f070: 4293 cmp r3, r2
|
|
800f072: d007 beq.n 800f084 <TIM_OC6_SetConfig+0x6c>
|
|
800f074: 687b ldr r3, [r7, #4]
|
|
800f076: 4a13 ldr r2, [pc, #76] @ (800f0c4 <TIM_OC6_SetConfig+0xac>)
|
|
800f078: 4293 cmp r3, r2
|
|
800f07a: d003 beq.n 800f084 <TIM_OC6_SetConfig+0x6c>
|
|
800f07c: 687b ldr r3, [r7, #4]
|
|
800f07e: 4a12 ldr r2, [pc, #72] @ (800f0c8 <TIM_OC6_SetConfig+0xb0>)
|
|
800f080: 4293 cmp r3, r2
|
|
800f082: d109 bne.n 800f098 <TIM_OC6_SetConfig+0x80>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
800f084: 697b ldr r3, [r7, #20]
|
|
800f086: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
800f08a: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
800f08c: 683b ldr r3, [r7, #0]
|
|
800f08e: 695b ldr r3, [r3, #20]
|
|
800f090: 029b lsls r3, r3, #10
|
|
800f092: 697a ldr r2, [r7, #20]
|
|
800f094: 4313 orrs r3, r2
|
|
800f096: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800f098: 687b ldr r3, [r7, #4]
|
|
800f09a: 697a ldr r2, [r7, #20]
|
|
800f09c: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
800f09e: 687b ldr r3, [r7, #4]
|
|
800f0a0: 68fa ldr r2, [r7, #12]
|
|
800f0a2: 655a str r2, [r3, #84] @ 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
800f0a4: 683b ldr r3, [r7, #0]
|
|
800f0a6: 685a ldr r2, [r3, #4]
|
|
800f0a8: 687b ldr r3, [r7, #4]
|
|
800f0aa: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800f0ac: 687b ldr r3, [r7, #4]
|
|
800f0ae: 693a ldr r2, [r7, #16]
|
|
800f0b0: 621a str r2, [r3, #32]
|
|
}
|
|
800f0b2: bf00 nop
|
|
800f0b4: 371c adds r7, #28
|
|
800f0b6: 46bd mov sp, r7
|
|
800f0b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f0bc: 4770 bx lr
|
|
800f0be: bf00 nop
|
|
800f0c0: 40012c00 .word 0x40012c00
|
|
800f0c4: 40014400 .word 0x40014400
|
|
800f0c8: 40014800 .word 0x40014800
|
|
|
|
0800f0cc <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
800f0cc: b480 push {r7}
|
|
800f0ce: b085 sub sp, #20
|
|
800f0d0: af00 add r7, sp, #0
|
|
800f0d2: 6078 str r0, [r7, #4]
|
|
800f0d4: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
800f0d6: 687b ldr r3, [r7, #4]
|
|
800f0d8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
800f0dc: 2b01 cmp r3, #1
|
|
800f0de: d101 bne.n 800f0e4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
800f0e0: 2302 movs r3, #2
|
|
800f0e2: e04a b.n 800f17a <HAL_TIMEx_MasterConfigSynchronization+0xae>
|
|
800f0e4: 687b ldr r3, [r7, #4]
|
|
800f0e6: 2201 movs r2, #1
|
|
800f0e8: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800f0ec: 687b ldr r3, [r7, #4]
|
|
800f0ee: 2202 movs r2, #2
|
|
800f0f0: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
800f0f4: 687b ldr r3, [r7, #4]
|
|
800f0f6: 681b ldr r3, [r3, #0]
|
|
800f0f8: 685b ldr r3, [r3, #4]
|
|
800f0fa: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800f0fc: 687b ldr r3, [r7, #4]
|
|
800f0fe: 681b ldr r3, [r3, #0]
|
|
800f100: 689b ldr r3, [r3, #8]
|
|
800f102: 60bb str r3, [r7, #8]
|
|
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
800f104: 687b ldr r3, [r7, #4]
|
|
800f106: 681b ldr r3, [r3, #0]
|
|
800f108: 4a1f ldr r2, [pc, #124] @ (800f188 <HAL_TIMEx_MasterConfigSynchronization+0xbc>)
|
|
800f10a: 4293 cmp r3, r2
|
|
800f10c: d108 bne.n 800f120 <HAL_TIMEx_MasterConfigSynchronization+0x54>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
800f10e: 68fb ldr r3, [r7, #12]
|
|
800f110: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
|
|
800f114: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
800f116: 683b ldr r3, [r7, #0]
|
|
800f118: 685b ldr r3, [r3, #4]
|
|
800f11a: 68fa ldr r2, [r7, #12]
|
|
800f11c: 4313 orrs r3, r2
|
|
800f11e: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
800f120: 68fb ldr r3, [r7, #12]
|
|
800f122: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f126: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
800f128: 683b ldr r3, [r7, #0]
|
|
800f12a: 681b ldr r3, [r3, #0]
|
|
800f12c: 68fa ldr r2, [r7, #12]
|
|
800f12e: 4313 orrs r3, r2
|
|
800f130: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
800f132: 687b ldr r3, [r7, #4]
|
|
800f134: 681b ldr r3, [r3, #0]
|
|
800f136: 68fa ldr r2, [r7, #12]
|
|
800f138: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
800f13a: 687b ldr r3, [r7, #4]
|
|
800f13c: 681b ldr r3, [r3, #0]
|
|
800f13e: 4a12 ldr r2, [pc, #72] @ (800f188 <HAL_TIMEx_MasterConfigSynchronization+0xbc>)
|
|
800f140: 4293 cmp r3, r2
|
|
800f142: d004 beq.n 800f14e <HAL_TIMEx_MasterConfigSynchronization+0x82>
|
|
800f144: 687b ldr r3, [r7, #4]
|
|
800f146: 681b ldr r3, [r3, #0]
|
|
800f148: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800f14c: d10c bne.n 800f168 <HAL_TIMEx_MasterConfigSynchronization+0x9c>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
800f14e: 68bb ldr r3, [r7, #8]
|
|
800f150: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
800f154: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
800f156: 683b ldr r3, [r7, #0]
|
|
800f158: 689b ldr r3, [r3, #8]
|
|
800f15a: 68ba ldr r2, [r7, #8]
|
|
800f15c: 4313 orrs r3, r2
|
|
800f15e: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800f160: 687b ldr r3, [r7, #4]
|
|
800f162: 681b ldr r3, [r3, #0]
|
|
800f164: 68ba ldr r2, [r7, #8]
|
|
800f166: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800f168: 687b ldr r3, [r7, #4]
|
|
800f16a: 2201 movs r2, #1
|
|
800f16c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800f170: 687b ldr r3, [r7, #4]
|
|
800f172: 2200 movs r2, #0
|
|
800f174: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
800f178: 2300 movs r3, #0
|
|
}
|
|
800f17a: 4618 mov r0, r3
|
|
800f17c: 3714 adds r7, #20
|
|
800f17e: 46bd mov sp, r7
|
|
800f180: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f184: 4770 bx lr
|
|
800f186: bf00 nop
|
|
800f188: 40012c00 .word 0x40012c00
|
|
|
|
0800f18c <HAL_TIMEx_CommutCallback>:
|
|
* @brief Commutation callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800f18c: b480 push {r7}
|
|
800f18e: b083 sub sp, #12
|
|
800f190: af00 add r7, sp, #0
|
|
800f192: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800f194: bf00 nop
|
|
800f196: 370c adds r7, #12
|
|
800f198: 46bd mov sp, r7
|
|
800f19a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f19e: 4770 bx lr
|
|
|
|
0800f1a0 <HAL_TIMEx_BreakCallback>:
|
|
* @brief Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800f1a0: b480 push {r7}
|
|
800f1a2: b083 sub sp, #12
|
|
800f1a4: af00 add r7, sp, #0
|
|
800f1a6: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800f1a8: bf00 nop
|
|
800f1aa: 370c adds r7, #12
|
|
800f1ac: 46bd mov sp, r7
|
|
800f1ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f1b2: 4770 bx lr
|
|
|
|
0800f1b4 <HAL_TIMEx_Break2Callback>:
|
|
* @brief Break2 detection callback in non blocking mode
|
|
* @param htim: TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800f1b4: b480 push {r7}
|
|
800f1b6: b083 sub sp, #12
|
|
800f1b8: af00 add r7, sp, #0
|
|
800f1ba: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_Break2Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
800f1bc: bf00 nop
|
|
800f1be: 370c adds r7, #12
|
|
800f1c0: 46bd mov sp, r7
|
|
800f1c2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f1c6: 4770 bx lr
|
|
|
|
0800f1c8 <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
|
|
{
|
|
800f1c8: b480 push {r7}
|
|
800f1ca: b085 sub sp, #20
|
|
800f1cc: af00 add r7, sp, #0
|
|
800f1ce: 6078 str r0, [r7, #4]
|
|
uint32_t winterruptmask;
|
|
|
|
/* Clear pending interrupts */
|
|
USBx->ISTR = 0U;
|
|
800f1d0: 687b ldr r3, [r7, #4]
|
|
800f1d2: 2200 movs r2, #0
|
|
800f1d4: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
/* Set winterruptmask variable */
|
|
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
|
|
800f1d8: f64b 7380 movw r3, #49024 @ 0xbf80
|
|
800f1dc: 60fb str r3, [r7, #12]
|
|
USB_CNTR_SUSPM | USB_CNTR_ERRM |
|
|
USB_CNTR_SOFM | USB_CNTR_ESOFM |
|
|
USB_CNTR_RESETM | USB_CNTR_L1REQM;
|
|
|
|
/* Set interrupt mask */
|
|
USBx->CNTR = (uint16_t)winterruptmask;
|
|
800f1de: 68fb ldr r3, [r7, #12]
|
|
800f1e0: b29a uxth r2, r3
|
|
800f1e2: 687b ldr r3, [r7, #4]
|
|
800f1e4: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
800f1e8: 2300 movs r3, #0
|
|
}
|
|
800f1ea: 4618 mov r0, r3
|
|
800f1ec: 3714 adds r7, #20
|
|
800f1ee: 46bd mov sp, r7
|
|
800f1f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f1f4: 4770 bx lr
|
|
|
|
0800f1f6 <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
|
|
{
|
|
800f1f6: b480 push {r7}
|
|
800f1f8: b085 sub sp, #20
|
|
800f1fa: af00 add r7, sp, #0
|
|
800f1fc: 6078 str r0, [r7, #4]
|
|
uint32_t winterruptmask;
|
|
|
|
/* Set winterruptmask variable */
|
|
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
|
|
800f1fe: f64b 7380 movw r3, #49024 @ 0xbf80
|
|
800f202: 60fb str r3, [r7, #12]
|
|
USB_CNTR_SUSPM | USB_CNTR_ERRM |
|
|
USB_CNTR_SOFM | USB_CNTR_ESOFM |
|
|
USB_CNTR_RESETM | USB_CNTR_L1REQM;
|
|
|
|
/* Clear interrupt mask */
|
|
USBx->CNTR &= (uint16_t)(~winterruptmask);
|
|
800f204: 687b ldr r3, [r7, #4]
|
|
800f206: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
|
|
800f20a: b29a uxth r2, r3
|
|
800f20c: 68fb ldr r3, [r7, #12]
|
|
800f20e: b29b uxth r3, r3
|
|
800f210: 43db mvns r3, r3
|
|
800f212: b29b uxth r3, r3
|
|
800f214: 4013 ands r3, r2
|
|
800f216: b29a uxth r2, r3
|
|
800f218: 687b ldr r3, [r7, #4]
|
|
800f21a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
800f21e: 2300 movs r3, #0
|
|
}
|
|
800f220: 4618 mov r0, r3
|
|
800f222: 3714 adds r7, #20
|
|
800f224: 46bd mov sp, r7
|
|
800f226: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f22a: 4770 bx lr
|
|
|
|
0800f22c <USB_DevInit>:
|
|
* @param cfg pointer to a USB_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
|
|
{
|
|
800f22c: b480 push {r7}
|
|
800f22e: b085 sub sp, #20
|
|
800f230: af00 add r7, sp, #0
|
|
800f232: 60f8 str r0, [r7, #12]
|
|
800f234: 1d3b adds r3, r7, #4
|
|
800f236: e883 0006 stmia.w r3, {r1, r2}
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(cfg);
|
|
|
|
/* Init Device */
|
|
/* CNTR_FRES = 1 */
|
|
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
|
|
800f23a: 68fb ldr r3, [r7, #12]
|
|
800f23c: 2201 movs r2, #1
|
|
800f23e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
/* CNTR_FRES = 0 */
|
|
USBx->CNTR = 0U;
|
|
800f242: 68fb ldr r3, [r7, #12]
|
|
800f244: 2200 movs r2, #0
|
|
800f246: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Clear pending interrupts */
|
|
USBx->ISTR = 0U;
|
|
800f24a: 68fb ldr r3, [r7, #12]
|
|
800f24c: 2200 movs r2, #0
|
|
800f24e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
|
|
/*Set Btable Address*/
|
|
USBx->BTABLE = BTABLE_ADDRESS;
|
|
800f252: 68fb ldr r3, [r7, #12]
|
|
800f254: 2200 movs r2, #0
|
|
800f256: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
|
|
|
|
return HAL_OK;
|
|
800f25a: 2300 movs r3, #0
|
|
}
|
|
800f25c: 4618 mov r0, r3
|
|
800f25e: 3714 adds r7, #20
|
|
800f260: 46bd mov sp, r7
|
|
800f262: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f266: 4770 bx lr
|
|
|
|
0800f268 <USB_ActivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
800f268: b480 push {r7}
|
|
800f26a: b0a7 sub sp, #156 @ 0x9c
|
|
800f26c: af00 add r7, sp, #0
|
|
800f26e: 6078 str r0, [r7, #4]
|
|
800f270: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800f272: 2300 movs r3, #0
|
|
800f274: f887 3097 strb.w r3, [r7, #151] @ 0x97
|
|
uint16_t wEpRegVal;
|
|
|
|
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
|
|
800f278: 687a ldr r2, [r7, #4]
|
|
800f27a: 683b ldr r3, [r7, #0]
|
|
800f27c: 781b ldrb r3, [r3, #0]
|
|
800f27e: 009b lsls r3, r3, #2
|
|
800f280: 4413 add r3, r2
|
|
800f282: 881b ldrh r3, [r3, #0]
|
|
800f284: b29b uxth r3, r3
|
|
800f286: f423 43ec bic.w r3, r3, #30208 @ 0x7600
|
|
800f28a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f28e: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
|
|
/* initialize Endpoint */
|
|
switch (ep->type)
|
|
800f292: 683b ldr r3, [r7, #0]
|
|
800f294: 78db ldrb r3, [r3, #3]
|
|
800f296: 2b03 cmp r3, #3
|
|
800f298: d81f bhi.n 800f2da <USB_ActivateEndpoint+0x72>
|
|
800f29a: a201 add r2, pc, #4 @ (adr r2, 800f2a0 <USB_ActivateEndpoint+0x38>)
|
|
800f29c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800f2a0: 0800f2b1 .word 0x0800f2b1
|
|
800f2a4: 0800f2cd .word 0x0800f2cd
|
|
800f2a8: 0800f2e3 .word 0x0800f2e3
|
|
800f2ac: 0800f2bf .word 0x0800f2bf
|
|
{
|
|
case EP_TYPE_CTRL:
|
|
wEpRegVal |= USB_EP_CONTROL;
|
|
800f2b0: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
800f2b4: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800f2b8: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
break;
|
|
800f2bc: e012 b.n 800f2e4 <USB_ActivateEndpoint+0x7c>
|
|
case EP_TYPE_BULK:
|
|
wEpRegVal |= USB_EP_BULK;
|
|
break;
|
|
|
|
case EP_TYPE_INTR:
|
|
wEpRegVal |= USB_EP_INTERRUPT;
|
|
800f2be: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
800f2c2: f443 63c0 orr.w r3, r3, #1536 @ 0x600
|
|
800f2c6: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
break;
|
|
800f2ca: e00b b.n 800f2e4 <USB_ActivateEndpoint+0x7c>
|
|
|
|
case EP_TYPE_ISOC:
|
|
wEpRegVal |= USB_EP_ISOCHRONOUS;
|
|
800f2cc: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
800f2d0: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
800f2d4: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
|
|
break;
|
|
800f2d8: e004 b.n 800f2e4 <USB_ActivateEndpoint+0x7c>
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
800f2da: 2301 movs r3, #1
|
|
800f2dc: f887 3097 strb.w r3, [r7, #151] @ 0x97
|
|
break;
|
|
800f2e0: e000 b.n 800f2e4 <USB_ActivateEndpoint+0x7c>
|
|
break;
|
|
800f2e2: bf00 nop
|
|
}
|
|
|
|
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
|
|
800f2e4: 687a ldr r2, [r7, #4]
|
|
800f2e6: 683b ldr r3, [r7, #0]
|
|
800f2e8: 781b ldrb r3, [r3, #0]
|
|
800f2ea: 009b lsls r3, r3, #2
|
|
800f2ec: 441a add r2, r3
|
|
800f2ee: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
|
|
800f2f2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f2f6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f2fa: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f2fe: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f302: b29b uxth r3, r3
|
|
800f304: 8013 strh r3, [r2, #0]
|
|
|
|
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
|
|
800f306: 687a ldr r2, [r7, #4]
|
|
800f308: 683b ldr r3, [r7, #0]
|
|
800f30a: 781b ldrb r3, [r3, #0]
|
|
800f30c: 009b lsls r3, r3, #2
|
|
800f30e: 4413 add r3, r2
|
|
800f310: 881b ldrh r3, [r3, #0]
|
|
800f312: b29b uxth r3, r3
|
|
800f314: b21b sxth r3, r3
|
|
800f316: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f31a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f31e: b21a sxth r2, r3
|
|
800f320: 683b ldr r3, [r7, #0]
|
|
800f322: 781b ldrb r3, [r3, #0]
|
|
800f324: b21b sxth r3, r3
|
|
800f326: 4313 orrs r3, r2
|
|
800f328: b21b sxth r3, r3
|
|
800f32a: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
|
|
800f32e: 687a ldr r2, [r7, #4]
|
|
800f330: 683b ldr r3, [r7, #0]
|
|
800f332: 781b ldrb r3, [r3, #0]
|
|
800f334: 009b lsls r3, r3, #2
|
|
800f336: 441a add r2, r3
|
|
800f338: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
|
|
800f33c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f340: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f344: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f348: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f34c: b29b uxth r3, r3
|
|
800f34e: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->doublebuffer == 0U)
|
|
800f350: 683b ldr r3, [r7, #0]
|
|
800f352: 7b1b ldrb r3, [r3, #12]
|
|
800f354: 2b00 cmp r3, #0
|
|
800f356: f040 8180 bne.w 800f65a <USB_ActivateEndpoint+0x3f2>
|
|
{
|
|
if (ep->is_in != 0U)
|
|
800f35a: 683b ldr r3, [r7, #0]
|
|
800f35c: 785b ldrb r3, [r3, #1]
|
|
800f35e: 2b00 cmp r3, #0
|
|
800f360: f000 8084 beq.w 800f46c <USB_ActivateEndpoint+0x204>
|
|
{
|
|
/*Set the endpoint Transmit buffer address */
|
|
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
|
|
800f364: 687b ldr r3, [r7, #4]
|
|
800f366: 61bb str r3, [r7, #24]
|
|
800f368: 687b ldr r3, [r7, #4]
|
|
800f36a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800f36e: b29b uxth r3, r3
|
|
800f370: 461a mov r2, r3
|
|
800f372: 69bb ldr r3, [r7, #24]
|
|
800f374: 4413 add r3, r2
|
|
800f376: 61bb str r3, [r7, #24]
|
|
800f378: 683b ldr r3, [r7, #0]
|
|
800f37a: 781b ldrb r3, [r3, #0]
|
|
800f37c: 00da lsls r2, r3, #3
|
|
800f37e: 69bb ldr r3, [r7, #24]
|
|
800f380: 4413 add r3, r2
|
|
800f382: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800f386: 617b str r3, [r7, #20]
|
|
800f388: 683b ldr r3, [r7, #0]
|
|
800f38a: 88db ldrh r3, [r3, #6]
|
|
800f38c: 085b lsrs r3, r3, #1
|
|
800f38e: b29b uxth r3, r3
|
|
800f390: 005b lsls r3, r3, #1
|
|
800f392: b29a uxth r2, r3
|
|
800f394: 697b ldr r3, [r7, #20]
|
|
800f396: 801a strh r2, [r3, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
800f398: 687a ldr r2, [r7, #4]
|
|
800f39a: 683b ldr r3, [r7, #0]
|
|
800f39c: 781b ldrb r3, [r3, #0]
|
|
800f39e: 009b lsls r3, r3, #2
|
|
800f3a0: 4413 add r3, r2
|
|
800f3a2: 881b ldrh r3, [r3, #0]
|
|
800f3a4: 827b strh r3, [r7, #18]
|
|
800f3a6: 8a7b ldrh r3, [r7, #18]
|
|
800f3a8: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800f3ac: 2b00 cmp r3, #0
|
|
800f3ae: d01b beq.n 800f3e8 <USB_ActivateEndpoint+0x180>
|
|
800f3b0: 687a ldr r2, [r7, #4]
|
|
800f3b2: 683b ldr r3, [r7, #0]
|
|
800f3b4: 781b ldrb r3, [r3, #0]
|
|
800f3b6: 009b lsls r3, r3, #2
|
|
800f3b8: 4413 add r3, r2
|
|
800f3ba: 881b ldrh r3, [r3, #0]
|
|
800f3bc: b29b uxth r3, r3
|
|
800f3be: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f3c2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f3c6: 823b strh r3, [r7, #16]
|
|
800f3c8: 687a ldr r2, [r7, #4]
|
|
800f3ca: 683b ldr r3, [r7, #0]
|
|
800f3cc: 781b ldrb r3, [r3, #0]
|
|
800f3ce: 009b lsls r3, r3, #2
|
|
800f3d0: 441a add r2, r3
|
|
800f3d2: 8a3b ldrh r3, [r7, #16]
|
|
800f3d4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f3d8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f3dc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f3e0: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800f3e4: b29b uxth r3, r3
|
|
800f3e6: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
800f3e8: 683b ldr r3, [r7, #0]
|
|
800f3ea: 78db ldrb r3, [r3, #3]
|
|
800f3ec: 2b01 cmp r3, #1
|
|
800f3ee: d020 beq.n 800f432 <USB_ActivateEndpoint+0x1ca>
|
|
{
|
|
/* Configure NAK status for the Endpoint */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
|
800f3f0: 687a ldr r2, [r7, #4]
|
|
800f3f2: 683b ldr r3, [r7, #0]
|
|
800f3f4: 781b ldrb r3, [r3, #0]
|
|
800f3f6: 009b lsls r3, r3, #2
|
|
800f3f8: 4413 add r3, r2
|
|
800f3fa: 881b ldrh r3, [r3, #0]
|
|
800f3fc: b29b uxth r3, r3
|
|
800f3fe: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f402: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800f406: 81bb strh r3, [r7, #12]
|
|
800f408: 89bb ldrh r3, [r7, #12]
|
|
800f40a: f083 0320 eor.w r3, r3, #32
|
|
800f40e: 81bb strh r3, [r7, #12]
|
|
800f410: 687a ldr r2, [r7, #4]
|
|
800f412: 683b ldr r3, [r7, #0]
|
|
800f414: 781b ldrb r3, [r3, #0]
|
|
800f416: 009b lsls r3, r3, #2
|
|
800f418: 441a add r2, r3
|
|
800f41a: 89bb ldrh r3, [r7, #12]
|
|
800f41c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f420: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f424: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f428: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f42c: b29b uxth r3, r3
|
|
800f42e: 8013 strh r3, [r2, #0]
|
|
800f430: e3f9 b.n 800fc26 <USB_ActivateEndpoint+0x9be>
|
|
}
|
|
else
|
|
{
|
|
/* Configure TX Endpoint to disabled state */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
800f432: 687a ldr r2, [r7, #4]
|
|
800f434: 683b ldr r3, [r7, #0]
|
|
800f436: 781b ldrb r3, [r3, #0]
|
|
800f438: 009b lsls r3, r3, #2
|
|
800f43a: 4413 add r3, r2
|
|
800f43c: 881b ldrh r3, [r3, #0]
|
|
800f43e: b29b uxth r3, r3
|
|
800f440: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f444: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800f448: 81fb strh r3, [r7, #14]
|
|
800f44a: 687a ldr r2, [r7, #4]
|
|
800f44c: 683b ldr r3, [r7, #0]
|
|
800f44e: 781b ldrb r3, [r3, #0]
|
|
800f450: 009b lsls r3, r3, #2
|
|
800f452: 441a add r2, r3
|
|
800f454: 89fb ldrh r3, [r7, #14]
|
|
800f456: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f45a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f45e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f462: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f466: b29b uxth r3, r3
|
|
800f468: 8013 strh r3, [r2, #0]
|
|
800f46a: e3dc b.n 800fc26 <USB_ActivateEndpoint+0x9be>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the endpoint Receive buffer address */
|
|
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
|
|
800f46c: 687b ldr r3, [r7, #4]
|
|
800f46e: 633b str r3, [r7, #48] @ 0x30
|
|
800f470: 687b ldr r3, [r7, #4]
|
|
800f472: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800f476: b29b uxth r3, r3
|
|
800f478: 461a mov r2, r3
|
|
800f47a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800f47c: 4413 add r3, r2
|
|
800f47e: 633b str r3, [r7, #48] @ 0x30
|
|
800f480: 683b ldr r3, [r7, #0]
|
|
800f482: 781b ldrb r3, [r3, #0]
|
|
800f484: 00da lsls r2, r3, #3
|
|
800f486: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800f488: 4413 add r3, r2
|
|
800f48a: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
800f48e: 62fb str r3, [r7, #44] @ 0x2c
|
|
800f490: 683b ldr r3, [r7, #0]
|
|
800f492: 88db ldrh r3, [r3, #6]
|
|
800f494: 085b lsrs r3, r3, #1
|
|
800f496: b29b uxth r3, r3
|
|
800f498: 005b lsls r3, r3, #1
|
|
800f49a: b29a uxth r2, r3
|
|
800f49c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800f49e: 801a strh r2, [r3, #0]
|
|
|
|
/* Set the endpoint Receive buffer counter */
|
|
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
|
|
800f4a0: 687b ldr r3, [r7, #4]
|
|
800f4a2: 62bb str r3, [r7, #40] @ 0x28
|
|
800f4a4: 687b ldr r3, [r7, #4]
|
|
800f4a6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800f4aa: b29b uxth r3, r3
|
|
800f4ac: 461a mov r2, r3
|
|
800f4ae: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800f4b0: 4413 add r3, r2
|
|
800f4b2: 62bb str r3, [r7, #40] @ 0x28
|
|
800f4b4: 683b ldr r3, [r7, #0]
|
|
800f4b6: 781b ldrb r3, [r3, #0]
|
|
800f4b8: 00da lsls r2, r3, #3
|
|
800f4ba: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800f4bc: 4413 add r3, r2
|
|
800f4be: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800f4c2: 627b str r3, [r7, #36] @ 0x24
|
|
800f4c4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f4c6: 881b ldrh r3, [r3, #0]
|
|
800f4c8: b29b uxth r3, r3
|
|
800f4ca: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800f4ce: b29a uxth r2, r3
|
|
800f4d0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f4d2: 801a strh r2, [r3, #0]
|
|
800f4d4: 683b ldr r3, [r7, #0]
|
|
800f4d6: 691b ldr r3, [r3, #16]
|
|
800f4d8: 2b00 cmp r3, #0
|
|
800f4da: d10a bne.n 800f4f2 <USB_ActivateEndpoint+0x28a>
|
|
800f4dc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f4de: 881b ldrh r3, [r3, #0]
|
|
800f4e0: b29b uxth r3, r3
|
|
800f4e2: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800f4e6: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800f4ea: b29a uxth r2, r3
|
|
800f4ec: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f4ee: 801a strh r2, [r3, #0]
|
|
800f4f0: e041 b.n 800f576 <USB_ActivateEndpoint+0x30e>
|
|
800f4f2: 683b ldr r3, [r7, #0]
|
|
800f4f4: 691b ldr r3, [r3, #16]
|
|
800f4f6: 2b3e cmp r3, #62 @ 0x3e
|
|
800f4f8: d81c bhi.n 800f534 <USB_ActivateEndpoint+0x2cc>
|
|
800f4fa: 683b ldr r3, [r7, #0]
|
|
800f4fc: 691b ldr r3, [r3, #16]
|
|
800f4fe: 085b lsrs r3, r3, #1
|
|
800f500: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
800f504: 683b ldr r3, [r7, #0]
|
|
800f506: 691b ldr r3, [r3, #16]
|
|
800f508: f003 0301 and.w r3, r3, #1
|
|
800f50c: 2b00 cmp r3, #0
|
|
800f50e: d004 beq.n 800f51a <USB_ActivateEndpoint+0x2b2>
|
|
800f510: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
800f514: 3301 adds r3, #1
|
|
800f516: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
800f51a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f51c: 881b ldrh r3, [r3, #0]
|
|
800f51e: b29a uxth r2, r3
|
|
800f520: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
800f524: b29b uxth r3, r3
|
|
800f526: 029b lsls r3, r3, #10
|
|
800f528: b29b uxth r3, r3
|
|
800f52a: 4313 orrs r3, r2
|
|
800f52c: b29a uxth r2, r3
|
|
800f52e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f530: 801a strh r2, [r3, #0]
|
|
800f532: e020 b.n 800f576 <USB_ActivateEndpoint+0x30e>
|
|
800f534: 683b ldr r3, [r7, #0]
|
|
800f536: 691b ldr r3, [r3, #16]
|
|
800f538: 095b lsrs r3, r3, #5
|
|
800f53a: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
800f53e: 683b ldr r3, [r7, #0]
|
|
800f540: 691b ldr r3, [r3, #16]
|
|
800f542: f003 031f and.w r3, r3, #31
|
|
800f546: 2b00 cmp r3, #0
|
|
800f548: d104 bne.n 800f554 <USB_ActivateEndpoint+0x2ec>
|
|
800f54a: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
800f54e: 3b01 subs r3, #1
|
|
800f550: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
800f554: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f556: 881b ldrh r3, [r3, #0]
|
|
800f558: b29a uxth r2, r3
|
|
800f55a: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
800f55e: b29b uxth r3, r3
|
|
800f560: 029b lsls r3, r3, #10
|
|
800f562: b29b uxth r3, r3
|
|
800f564: 4313 orrs r3, r2
|
|
800f566: b29b uxth r3, r3
|
|
800f568: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800f56c: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800f570: b29a uxth r2, r3
|
|
800f572: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800f574: 801a strh r2, [r3, #0]
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
800f576: 687a ldr r2, [r7, #4]
|
|
800f578: 683b ldr r3, [r7, #0]
|
|
800f57a: 781b ldrb r3, [r3, #0]
|
|
800f57c: 009b lsls r3, r3, #2
|
|
800f57e: 4413 add r3, r2
|
|
800f580: 881b ldrh r3, [r3, #0]
|
|
800f582: 847b strh r3, [r7, #34] @ 0x22
|
|
800f584: 8c7b ldrh r3, [r7, #34] @ 0x22
|
|
800f586: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800f58a: 2b00 cmp r3, #0
|
|
800f58c: d01b beq.n 800f5c6 <USB_ActivateEndpoint+0x35e>
|
|
800f58e: 687a ldr r2, [r7, #4]
|
|
800f590: 683b ldr r3, [r7, #0]
|
|
800f592: 781b ldrb r3, [r3, #0]
|
|
800f594: 009b lsls r3, r3, #2
|
|
800f596: 4413 add r3, r2
|
|
800f598: 881b ldrh r3, [r3, #0]
|
|
800f59a: b29b uxth r3, r3
|
|
800f59c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f5a0: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f5a4: 843b strh r3, [r7, #32]
|
|
800f5a6: 687a ldr r2, [r7, #4]
|
|
800f5a8: 683b ldr r3, [r7, #0]
|
|
800f5aa: 781b ldrb r3, [r3, #0]
|
|
800f5ac: 009b lsls r3, r3, #2
|
|
800f5ae: 441a add r2, r3
|
|
800f5b0: 8c3b ldrh r3, [r7, #32]
|
|
800f5b2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f5b6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f5ba: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800f5be: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f5c2: b29b uxth r3, r3
|
|
800f5c4: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->num == 0U)
|
|
800f5c6: 683b ldr r3, [r7, #0]
|
|
800f5c8: 781b ldrb r3, [r3, #0]
|
|
800f5ca: 2b00 cmp r3, #0
|
|
800f5cc: d124 bne.n 800f618 <USB_ActivateEndpoint+0x3b0>
|
|
{
|
|
/* Configure VALID status for EP0 */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
|
800f5ce: 687a ldr r2, [r7, #4]
|
|
800f5d0: 683b ldr r3, [r7, #0]
|
|
800f5d2: 781b ldrb r3, [r3, #0]
|
|
800f5d4: 009b lsls r3, r3, #2
|
|
800f5d6: 4413 add r3, r2
|
|
800f5d8: 881b ldrh r3, [r3, #0]
|
|
800f5da: b29b uxth r3, r3
|
|
800f5dc: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800f5e0: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f5e4: 83bb strh r3, [r7, #28]
|
|
800f5e6: 8bbb ldrh r3, [r7, #28]
|
|
800f5e8: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
800f5ec: 83bb strh r3, [r7, #28]
|
|
800f5ee: 8bbb ldrh r3, [r7, #28]
|
|
800f5f0: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
800f5f4: 83bb strh r3, [r7, #28]
|
|
800f5f6: 687a ldr r2, [r7, #4]
|
|
800f5f8: 683b ldr r3, [r7, #0]
|
|
800f5fa: 781b ldrb r3, [r3, #0]
|
|
800f5fc: 009b lsls r3, r3, #2
|
|
800f5fe: 441a add r2, r3
|
|
800f600: 8bbb ldrh r3, [r7, #28]
|
|
800f602: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f606: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f60a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f60e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f612: b29b uxth r3, r3
|
|
800f614: 8013 strh r3, [r2, #0]
|
|
800f616: e306 b.n 800fc26 <USB_ActivateEndpoint+0x9be>
|
|
}
|
|
else
|
|
{
|
|
/* Configure NAK status for OUT Endpoint */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
|
|
800f618: 687a ldr r2, [r7, #4]
|
|
800f61a: 683b ldr r3, [r7, #0]
|
|
800f61c: 781b ldrb r3, [r3, #0]
|
|
800f61e: 009b lsls r3, r3, #2
|
|
800f620: 4413 add r3, r2
|
|
800f622: 881b ldrh r3, [r3, #0]
|
|
800f624: b29b uxth r3, r3
|
|
800f626: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800f62a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f62e: 83fb strh r3, [r7, #30]
|
|
800f630: 8bfb ldrh r3, [r7, #30]
|
|
800f632: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
800f636: 83fb strh r3, [r7, #30]
|
|
800f638: 687a ldr r2, [r7, #4]
|
|
800f63a: 683b ldr r3, [r7, #0]
|
|
800f63c: 781b ldrb r3, [r3, #0]
|
|
800f63e: 009b lsls r3, r3, #2
|
|
800f640: 441a add r2, r3
|
|
800f642: 8bfb ldrh r3, [r7, #30]
|
|
800f644: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f648: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f64c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f650: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f654: b29b uxth r3, r3
|
|
800f656: 8013 strh r3, [r2, #0]
|
|
800f658: e2e5 b.n 800fc26 <USB_ActivateEndpoint+0x9be>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
/* Double Buffer */
|
|
else
|
|
{
|
|
if (ep->type == EP_TYPE_BULK)
|
|
800f65a: 683b ldr r3, [r7, #0]
|
|
800f65c: 78db ldrb r3, [r3, #3]
|
|
800f65e: 2b02 cmp r3, #2
|
|
800f660: d11e bne.n 800f6a0 <USB_ActivateEndpoint+0x438>
|
|
{
|
|
/* Set bulk endpoint as double buffered */
|
|
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
|
|
800f662: 687a ldr r2, [r7, #4]
|
|
800f664: 683b ldr r3, [r7, #0]
|
|
800f666: 781b ldrb r3, [r3, #0]
|
|
800f668: 009b lsls r3, r3, #2
|
|
800f66a: 4413 add r3, r2
|
|
800f66c: 881b ldrh r3, [r3, #0]
|
|
800f66e: b29b uxth r3, r3
|
|
800f670: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f674: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f678: f8a7 3082 strh.w r3, [r7, #130] @ 0x82
|
|
800f67c: 687a ldr r2, [r7, #4]
|
|
800f67e: 683b ldr r3, [r7, #0]
|
|
800f680: 781b ldrb r3, [r3, #0]
|
|
800f682: 009b lsls r3, r3, #2
|
|
800f684: 441a add r2, r3
|
|
800f686: f8b7 3082 ldrh.w r3, [r7, #130] @ 0x82
|
|
800f68a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f68e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f692: f443 4301 orr.w r3, r3, #33024 @ 0x8100
|
|
800f696: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f69a: b29b uxth r3, r3
|
|
800f69c: 8013 strh r3, [r2, #0]
|
|
800f69e: e01d b.n 800f6dc <USB_ActivateEndpoint+0x474>
|
|
}
|
|
else
|
|
{
|
|
/* Set the ISOC endpoint in double buffer mode */
|
|
PCD_CLEAR_EP_KIND(USBx, ep->num);
|
|
800f6a0: 687a ldr r2, [r7, #4]
|
|
800f6a2: 683b ldr r3, [r7, #0]
|
|
800f6a4: 781b ldrb r3, [r3, #0]
|
|
800f6a6: 009b lsls r3, r3, #2
|
|
800f6a8: 4413 add r3, r2
|
|
800f6aa: 881b ldrh r3, [r3, #0]
|
|
800f6ac: b29b uxth r3, r3
|
|
800f6ae: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
|
|
800f6b2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f6b6: f8a7 3084 strh.w r3, [r7, #132] @ 0x84
|
|
800f6ba: 687a ldr r2, [r7, #4]
|
|
800f6bc: 683b ldr r3, [r7, #0]
|
|
800f6be: 781b ldrb r3, [r3, #0]
|
|
800f6c0: 009b lsls r3, r3, #2
|
|
800f6c2: 441a add r2, r3
|
|
800f6c4: f8b7 3084 ldrh.w r3, [r7, #132] @ 0x84
|
|
800f6c8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f6cc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f6d0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f6d4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f6d8: b29b uxth r3, r3
|
|
800f6da: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Set buffer address for double buffered mode */
|
|
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
|
|
800f6dc: 687b ldr r3, [r7, #4]
|
|
800f6de: 67fb str r3, [r7, #124] @ 0x7c
|
|
800f6e0: 687b ldr r3, [r7, #4]
|
|
800f6e2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800f6e6: b29b uxth r3, r3
|
|
800f6e8: 461a mov r2, r3
|
|
800f6ea: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
800f6ec: 4413 add r3, r2
|
|
800f6ee: 67fb str r3, [r7, #124] @ 0x7c
|
|
800f6f0: 683b ldr r3, [r7, #0]
|
|
800f6f2: 781b ldrb r3, [r3, #0]
|
|
800f6f4: 00da lsls r2, r3, #3
|
|
800f6f6: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
800f6f8: 4413 add r3, r2
|
|
800f6fa: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800f6fe: 67bb str r3, [r7, #120] @ 0x78
|
|
800f700: 683b ldr r3, [r7, #0]
|
|
800f702: 891b ldrh r3, [r3, #8]
|
|
800f704: 085b lsrs r3, r3, #1
|
|
800f706: b29b uxth r3, r3
|
|
800f708: 005b lsls r3, r3, #1
|
|
800f70a: b29a uxth r2, r3
|
|
800f70c: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800f70e: 801a strh r2, [r3, #0]
|
|
800f710: 687b ldr r3, [r7, #4]
|
|
800f712: 677b str r3, [r7, #116] @ 0x74
|
|
800f714: 687b ldr r3, [r7, #4]
|
|
800f716: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800f71a: b29b uxth r3, r3
|
|
800f71c: 461a mov r2, r3
|
|
800f71e: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
800f720: 4413 add r3, r2
|
|
800f722: 677b str r3, [r7, #116] @ 0x74
|
|
800f724: 683b ldr r3, [r7, #0]
|
|
800f726: 781b ldrb r3, [r3, #0]
|
|
800f728: 00da lsls r2, r3, #3
|
|
800f72a: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
800f72c: 4413 add r3, r2
|
|
800f72e: f203 4304 addw r3, r3, #1028 @ 0x404
|
|
800f732: 673b str r3, [r7, #112] @ 0x70
|
|
800f734: 683b ldr r3, [r7, #0]
|
|
800f736: 895b ldrh r3, [r3, #10]
|
|
800f738: 085b lsrs r3, r3, #1
|
|
800f73a: b29b uxth r3, r3
|
|
800f73c: 005b lsls r3, r3, #1
|
|
800f73e: b29a uxth r2, r3
|
|
800f740: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800f742: 801a strh r2, [r3, #0]
|
|
|
|
if (ep->is_in == 0U)
|
|
800f744: 683b ldr r3, [r7, #0]
|
|
800f746: 785b ldrb r3, [r3, #1]
|
|
800f748: 2b00 cmp r3, #0
|
|
800f74a: f040 81af bne.w 800faac <USB_ActivateEndpoint+0x844>
|
|
{
|
|
/* Clear the data toggle bits for the endpoint IN/OUT */
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
800f74e: 687a ldr r2, [r7, #4]
|
|
800f750: 683b ldr r3, [r7, #0]
|
|
800f752: 781b ldrb r3, [r3, #0]
|
|
800f754: 009b lsls r3, r3, #2
|
|
800f756: 4413 add r3, r2
|
|
800f758: 881b ldrh r3, [r3, #0]
|
|
800f75a: f8a7 3060 strh.w r3, [r7, #96] @ 0x60
|
|
800f75e: f8b7 3060 ldrh.w r3, [r7, #96] @ 0x60
|
|
800f762: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800f766: 2b00 cmp r3, #0
|
|
800f768: d01d beq.n 800f7a6 <USB_ActivateEndpoint+0x53e>
|
|
800f76a: 687a ldr r2, [r7, #4]
|
|
800f76c: 683b ldr r3, [r7, #0]
|
|
800f76e: 781b ldrb r3, [r3, #0]
|
|
800f770: 009b lsls r3, r3, #2
|
|
800f772: 4413 add r3, r2
|
|
800f774: 881b ldrh r3, [r3, #0]
|
|
800f776: b29b uxth r3, r3
|
|
800f778: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f77c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f780: f8a7 305e strh.w r3, [r7, #94] @ 0x5e
|
|
800f784: 687a ldr r2, [r7, #4]
|
|
800f786: 683b ldr r3, [r7, #0]
|
|
800f788: 781b ldrb r3, [r3, #0]
|
|
800f78a: 009b lsls r3, r3, #2
|
|
800f78c: 441a add r2, r3
|
|
800f78e: f8b7 305e ldrh.w r3, [r7, #94] @ 0x5e
|
|
800f792: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f796: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f79a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800f79e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800f7a2: b29b uxth r3, r3
|
|
800f7a4: 8013 strh r3, [r2, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
800f7a6: 687a ldr r2, [r7, #4]
|
|
800f7a8: 683b ldr r3, [r7, #0]
|
|
800f7aa: 781b ldrb r3, [r3, #0]
|
|
800f7ac: 009b lsls r3, r3, #2
|
|
800f7ae: 4413 add r3, r2
|
|
800f7b0: 881b ldrh r3, [r3, #0]
|
|
800f7b2: f8a7 305c strh.w r3, [r7, #92] @ 0x5c
|
|
800f7b6: f8b7 305c ldrh.w r3, [r7, #92] @ 0x5c
|
|
800f7ba: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800f7be: 2b00 cmp r3, #0
|
|
800f7c0: d01d beq.n 800f7fe <USB_ActivateEndpoint+0x596>
|
|
800f7c2: 687a ldr r2, [r7, #4]
|
|
800f7c4: 683b ldr r3, [r7, #0]
|
|
800f7c6: 781b ldrb r3, [r3, #0]
|
|
800f7c8: 009b lsls r3, r3, #2
|
|
800f7ca: 4413 add r3, r2
|
|
800f7cc: 881b ldrh r3, [r3, #0]
|
|
800f7ce: b29b uxth r3, r3
|
|
800f7d0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800f7d4: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800f7d8: f8a7 305a strh.w r3, [r7, #90] @ 0x5a
|
|
800f7dc: 687a ldr r2, [r7, #4]
|
|
800f7de: 683b ldr r3, [r7, #0]
|
|
800f7e0: 781b ldrb r3, [r3, #0]
|
|
800f7e2: 009b lsls r3, r3, #2
|
|
800f7e4: 441a add r2, r3
|
|
800f7e6: f8b7 305a ldrh.w r3, [r7, #90] @ 0x5a
|
|
800f7ea: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800f7ee: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800f7f2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800f7f6: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800f7fa: b29b uxth r3, r3
|
|
800f7fc: 8013 strh r3, [r2, #0]
|
|
|
|
/* Set endpoint RX count */
|
|
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
|
|
800f7fe: 683b ldr r3, [r7, #0]
|
|
800f800: 785b ldrb r3, [r3, #1]
|
|
800f802: 2b00 cmp r3, #0
|
|
800f804: d16b bne.n 800f8de <USB_ActivateEndpoint+0x676>
|
|
800f806: 687b ldr r3, [r7, #4]
|
|
800f808: 64fb str r3, [r7, #76] @ 0x4c
|
|
800f80a: 687b ldr r3, [r7, #4]
|
|
800f80c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800f810: b29b uxth r3, r3
|
|
800f812: 461a mov r2, r3
|
|
800f814: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800f816: 4413 add r3, r2
|
|
800f818: 64fb str r3, [r7, #76] @ 0x4c
|
|
800f81a: 683b ldr r3, [r7, #0]
|
|
800f81c: 781b ldrb r3, [r3, #0]
|
|
800f81e: 00da lsls r2, r3, #3
|
|
800f820: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800f822: 4413 add r3, r2
|
|
800f824: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800f828: 64bb str r3, [r7, #72] @ 0x48
|
|
800f82a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800f82c: 881b ldrh r3, [r3, #0]
|
|
800f82e: b29b uxth r3, r3
|
|
800f830: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800f834: b29a uxth r2, r3
|
|
800f836: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800f838: 801a strh r2, [r3, #0]
|
|
800f83a: 683b ldr r3, [r7, #0]
|
|
800f83c: 691b ldr r3, [r3, #16]
|
|
800f83e: 2b00 cmp r3, #0
|
|
800f840: d10a bne.n 800f858 <USB_ActivateEndpoint+0x5f0>
|
|
800f842: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800f844: 881b ldrh r3, [r3, #0]
|
|
800f846: b29b uxth r3, r3
|
|
800f848: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800f84c: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800f850: b29a uxth r2, r3
|
|
800f852: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800f854: 801a strh r2, [r3, #0]
|
|
800f856: e05d b.n 800f914 <USB_ActivateEndpoint+0x6ac>
|
|
800f858: 683b ldr r3, [r7, #0]
|
|
800f85a: 691b ldr r3, [r3, #16]
|
|
800f85c: 2b3e cmp r3, #62 @ 0x3e
|
|
800f85e: d81c bhi.n 800f89a <USB_ActivateEndpoint+0x632>
|
|
800f860: 683b ldr r3, [r7, #0]
|
|
800f862: 691b ldr r3, [r3, #16]
|
|
800f864: 085b lsrs r3, r3, #1
|
|
800f866: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
800f86a: 683b ldr r3, [r7, #0]
|
|
800f86c: 691b ldr r3, [r3, #16]
|
|
800f86e: f003 0301 and.w r3, r3, #1
|
|
800f872: 2b00 cmp r3, #0
|
|
800f874: d004 beq.n 800f880 <USB_ActivateEndpoint+0x618>
|
|
800f876: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800f87a: 3301 adds r3, #1
|
|
800f87c: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
800f880: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800f882: 881b ldrh r3, [r3, #0]
|
|
800f884: b29a uxth r2, r3
|
|
800f886: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800f88a: b29b uxth r3, r3
|
|
800f88c: 029b lsls r3, r3, #10
|
|
800f88e: b29b uxth r3, r3
|
|
800f890: 4313 orrs r3, r2
|
|
800f892: b29a uxth r2, r3
|
|
800f894: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800f896: 801a strh r2, [r3, #0]
|
|
800f898: e03c b.n 800f914 <USB_ActivateEndpoint+0x6ac>
|
|
800f89a: 683b ldr r3, [r7, #0]
|
|
800f89c: 691b ldr r3, [r3, #16]
|
|
800f89e: 095b lsrs r3, r3, #5
|
|
800f8a0: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
800f8a4: 683b ldr r3, [r7, #0]
|
|
800f8a6: 691b ldr r3, [r3, #16]
|
|
800f8a8: f003 031f and.w r3, r3, #31
|
|
800f8ac: 2b00 cmp r3, #0
|
|
800f8ae: d104 bne.n 800f8ba <USB_ActivateEndpoint+0x652>
|
|
800f8b0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800f8b4: 3b01 subs r3, #1
|
|
800f8b6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
800f8ba: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800f8bc: 881b ldrh r3, [r3, #0]
|
|
800f8be: b29a uxth r2, r3
|
|
800f8c0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
800f8c4: b29b uxth r3, r3
|
|
800f8c6: 029b lsls r3, r3, #10
|
|
800f8c8: b29b uxth r3, r3
|
|
800f8ca: 4313 orrs r3, r2
|
|
800f8cc: b29b uxth r3, r3
|
|
800f8ce: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800f8d2: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800f8d6: b29a uxth r2, r3
|
|
800f8d8: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800f8da: 801a strh r2, [r3, #0]
|
|
800f8dc: e01a b.n 800f914 <USB_ActivateEndpoint+0x6ac>
|
|
800f8de: 683b ldr r3, [r7, #0]
|
|
800f8e0: 785b ldrb r3, [r3, #1]
|
|
800f8e2: 2b01 cmp r3, #1
|
|
800f8e4: d116 bne.n 800f914 <USB_ActivateEndpoint+0x6ac>
|
|
800f8e6: 687b ldr r3, [r7, #4]
|
|
800f8e8: 657b str r3, [r7, #84] @ 0x54
|
|
800f8ea: 687b ldr r3, [r7, #4]
|
|
800f8ec: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800f8f0: b29b uxth r3, r3
|
|
800f8f2: 461a mov r2, r3
|
|
800f8f4: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800f8f6: 4413 add r3, r2
|
|
800f8f8: 657b str r3, [r7, #84] @ 0x54
|
|
800f8fa: 683b ldr r3, [r7, #0]
|
|
800f8fc: 781b ldrb r3, [r3, #0]
|
|
800f8fe: 00da lsls r2, r3, #3
|
|
800f900: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800f902: 4413 add r3, r2
|
|
800f904: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
800f908: 653b str r3, [r7, #80] @ 0x50
|
|
800f90a: 683b ldr r3, [r7, #0]
|
|
800f90c: 691b ldr r3, [r3, #16]
|
|
800f90e: b29a uxth r2, r3
|
|
800f910: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800f912: 801a strh r2, [r3, #0]
|
|
800f914: 687b ldr r3, [r7, #4]
|
|
800f916: 647b str r3, [r7, #68] @ 0x44
|
|
800f918: 683b ldr r3, [r7, #0]
|
|
800f91a: 785b ldrb r3, [r3, #1]
|
|
800f91c: 2b00 cmp r3, #0
|
|
800f91e: d16b bne.n 800f9f8 <USB_ActivateEndpoint+0x790>
|
|
800f920: 687b ldr r3, [r7, #4]
|
|
800f922: 63fb str r3, [r7, #60] @ 0x3c
|
|
800f924: 687b ldr r3, [r7, #4]
|
|
800f926: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800f92a: b29b uxth r3, r3
|
|
800f92c: 461a mov r2, r3
|
|
800f92e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800f930: 4413 add r3, r2
|
|
800f932: 63fb str r3, [r7, #60] @ 0x3c
|
|
800f934: 683b ldr r3, [r7, #0]
|
|
800f936: 781b ldrb r3, [r3, #0]
|
|
800f938: 00da lsls r2, r3, #3
|
|
800f93a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800f93c: 4413 add r3, r2
|
|
800f93e: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800f942: 63bb str r3, [r7, #56] @ 0x38
|
|
800f944: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800f946: 881b ldrh r3, [r3, #0]
|
|
800f948: b29b uxth r3, r3
|
|
800f94a: f3c3 0309 ubfx r3, r3, #0, #10
|
|
800f94e: b29a uxth r2, r3
|
|
800f950: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800f952: 801a strh r2, [r3, #0]
|
|
800f954: 683b ldr r3, [r7, #0]
|
|
800f956: 691b ldr r3, [r3, #16]
|
|
800f958: 2b00 cmp r3, #0
|
|
800f95a: d10a bne.n 800f972 <USB_ActivateEndpoint+0x70a>
|
|
800f95c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800f95e: 881b ldrh r3, [r3, #0]
|
|
800f960: b29b uxth r3, r3
|
|
800f962: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800f966: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800f96a: b29a uxth r2, r3
|
|
800f96c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800f96e: 801a strh r2, [r3, #0]
|
|
800f970: e05b b.n 800fa2a <USB_ActivateEndpoint+0x7c2>
|
|
800f972: 683b ldr r3, [r7, #0]
|
|
800f974: 691b ldr r3, [r3, #16]
|
|
800f976: 2b3e cmp r3, #62 @ 0x3e
|
|
800f978: d81c bhi.n 800f9b4 <USB_ActivateEndpoint+0x74c>
|
|
800f97a: 683b ldr r3, [r7, #0]
|
|
800f97c: 691b ldr r3, [r3, #16]
|
|
800f97e: 085b lsrs r3, r3, #1
|
|
800f980: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800f984: 683b ldr r3, [r7, #0]
|
|
800f986: 691b ldr r3, [r3, #16]
|
|
800f988: f003 0301 and.w r3, r3, #1
|
|
800f98c: 2b00 cmp r3, #0
|
|
800f98e: d004 beq.n 800f99a <USB_ActivateEndpoint+0x732>
|
|
800f990: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800f994: 3301 adds r3, #1
|
|
800f996: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800f99a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800f99c: 881b ldrh r3, [r3, #0]
|
|
800f99e: b29a uxth r2, r3
|
|
800f9a0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800f9a4: b29b uxth r3, r3
|
|
800f9a6: 029b lsls r3, r3, #10
|
|
800f9a8: b29b uxth r3, r3
|
|
800f9aa: 4313 orrs r3, r2
|
|
800f9ac: b29a uxth r2, r3
|
|
800f9ae: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800f9b0: 801a strh r2, [r3, #0]
|
|
800f9b2: e03a b.n 800fa2a <USB_ActivateEndpoint+0x7c2>
|
|
800f9b4: 683b ldr r3, [r7, #0]
|
|
800f9b6: 691b ldr r3, [r3, #16]
|
|
800f9b8: 095b lsrs r3, r3, #5
|
|
800f9ba: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800f9be: 683b ldr r3, [r7, #0]
|
|
800f9c0: 691b ldr r3, [r3, #16]
|
|
800f9c2: f003 031f and.w r3, r3, #31
|
|
800f9c6: 2b00 cmp r3, #0
|
|
800f9c8: d104 bne.n 800f9d4 <USB_ActivateEndpoint+0x76c>
|
|
800f9ca: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800f9ce: 3b01 subs r3, #1
|
|
800f9d0: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800f9d4: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800f9d6: 881b ldrh r3, [r3, #0]
|
|
800f9d8: b29a uxth r2, r3
|
|
800f9da: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800f9de: b29b uxth r3, r3
|
|
800f9e0: 029b lsls r3, r3, #10
|
|
800f9e2: b29b uxth r3, r3
|
|
800f9e4: 4313 orrs r3, r2
|
|
800f9e6: b29b uxth r3, r3
|
|
800f9e8: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
800f9ec: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
800f9f0: b29a uxth r2, r3
|
|
800f9f2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800f9f4: 801a strh r2, [r3, #0]
|
|
800f9f6: e018 b.n 800fa2a <USB_ActivateEndpoint+0x7c2>
|
|
800f9f8: 683b ldr r3, [r7, #0]
|
|
800f9fa: 785b ldrb r3, [r3, #1]
|
|
800f9fc: 2b01 cmp r3, #1
|
|
800f9fe: d114 bne.n 800fa2a <USB_ActivateEndpoint+0x7c2>
|
|
800fa00: 687b ldr r3, [r7, #4]
|
|
800fa02: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
800fa06: b29b uxth r3, r3
|
|
800fa08: 461a mov r2, r3
|
|
800fa0a: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800fa0c: 4413 add r3, r2
|
|
800fa0e: 647b str r3, [r7, #68] @ 0x44
|
|
800fa10: 683b ldr r3, [r7, #0]
|
|
800fa12: 781b ldrb r3, [r3, #0]
|
|
800fa14: 00da lsls r2, r3, #3
|
|
800fa16: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800fa18: 4413 add r3, r2
|
|
800fa1a: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
800fa1e: 643b str r3, [r7, #64] @ 0x40
|
|
800fa20: 683b ldr r3, [r7, #0]
|
|
800fa22: 691b ldr r3, [r3, #16]
|
|
800fa24: b29a uxth r2, r3
|
|
800fa26: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800fa28: 801a strh r2, [r3, #0]
|
|
|
|
/* Set endpoint RX to valid state */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
|
800fa2a: 687a ldr r2, [r7, #4]
|
|
800fa2c: 683b ldr r3, [r7, #0]
|
|
800fa2e: 781b ldrb r3, [r3, #0]
|
|
800fa30: 009b lsls r3, r3, #2
|
|
800fa32: 4413 add r3, r2
|
|
800fa34: 881b ldrh r3, [r3, #0]
|
|
800fa36: b29b uxth r3, r3
|
|
800fa38: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800fa3c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fa40: 86fb strh r3, [r7, #54] @ 0x36
|
|
800fa42: 8efb ldrh r3, [r7, #54] @ 0x36
|
|
800fa44: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
800fa48: 86fb strh r3, [r7, #54] @ 0x36
|
|
800fa4a: 8efb ldrh r3, [r7, #54] @ 0x36
|
|
800fa4c: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
800fa50: 86fb strh r3, [r7, #54] @ 0x36
|
|
800fa52: 687a ldr r2, [r7, #4]
|
|
800fa54: 683b ldr r3, [r7, #0]
|
|
800fa56: 781b ldrb r3, [r3, #0]
|
|
800fa58: 009b lsls r3, r3, #2
|
|
800fa5a: 441a add r2, r3
|
|
800fa5c: 8efb ldrh r3, [r7, #54] @ 0x36
|
|
800fa5e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fa62: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fa66: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fa6a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fa6e: b29b uxth r3, r3
|
|
800fa70: 8013 strh r3, [r2, #0]
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
800fa72: 687a ldr r2, [r7, #4]
|
|
800fa74: 683b ldr r3, [r7, #0]
|
|
800fa76: 781b ldrb r3, [r3, #0]
|
|
800fa78: 009b lsls r3, r3, #2
|
|
800fa7a: 4413 add r3, r2
|
|
800fa7c: 881b ldrh r3, [r3, #0]
|
|
800fa7e: b29b uxth r3, r3
|
|
800fa80: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fa84: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800fa88: 86bb strh r3, [r7, #52] @ 0x34
|
|
800fa8a: 687a ldr r2, [r7, #4]
|
|
800fa8c: 683b ldr r3, [r7, #0]
|
|
800fa8e: 781b ldrb r3, [r3, #0]
|
|
800fa90: 009b lsls r3, r3, #2
|
|
800fa92: 441a add r2, r3
|
|
800fa94: 8ebb ldrh r3, [r7, #52] @ 0x34
|
|
800fa96: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fa9a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fa9e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800faa2: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800faa6: b29b uxth r3, r3
|
|
800faa8: 8013 strh r3, [r2, #0]
|
|
800faaa: e0bc b.n 800fc26 <USB_ActivateEndpoint+0x9be>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the data toggle bits for the endpoint IN/OUT */
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
800faac: 687a ldr r2, [r7, #4]
|
|
800faae: 683b ldr r3, [r7, #0]
|
|
800fab0: 781b ldrb r3, [r3, #0]
|
|
800fab2: 009b lsls r3, r3, #2
|
|
800fab4: 4413 add r3, r2
|
|
800fab6: 881b ldrh r3, [r3, #0]
|
|
800fab8: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
800fabc: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
800fac0: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800fac4: 2b00 cmp r3, #0
|
|
800fac6: d01d beq.n 800fb04 <USB_ActivateEndpoint+0x89c>
|
|
800fac8: 687a ldr r2, [r7, #4]
|
|
800faca: 683b ldr r3, [r7, #0]
|
|
800facc: 781b ldrb r3, [r3, #0]
|
|
800face: 009b lsls r3, r3, #2
|
|
800fad0: 4413 add r3, r2
|
|
800fad2: 881b ldrh r3, [r3, #0]
|
|
800fad4: b29b uxth r3, r3
|
|
800fad6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fada: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fade: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
800fae2: 687a ldr r2, [r7, #4]
|
|
800fae4: 683b ldr r3, [r7, #0]
|
|
800fae6: 781b ldrb r3, [r3, #0]
|
|
800fae8: 009b lsls r3, r3, #2
|
|
800faea: 441a add r2, r3
|
|
800faec: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
800faf0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800faf4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800faf8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800fafc: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fb00: b29b uxth r3, r3
|
|
800fb02: 8013 strh r3, [r2, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
800fb04: 687a ldr r2, [r7, #4]
|
|
800fb06: 683b ldr r3, [r7, #0]
|
|
800fb08: 781b ldrb r3, [r3, #0]
|
|
800fb0a: 009b lsls r3, r3, #2
|
|
800fb0c: 4413 add r3, r2
|
|
800fb0e: 881b ldrh r3, [r3, #0]
|
|
800fb10: f8a7 306a strh.w r3, [r7, #106] @ 0x6a
|
|
800fb14: f8b7 306a ldrh.w r3, [r7, #106] @ 0x6a
|
|
800fb18: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800fb1c: 2b00 cmp r3, #0
|
|
800fb1e: d01d beq.n 800fb5c <USB_ActivateEndpoint+0x8f4>
|
|
800fb20: 687a ldr r2, [r7, #4]
|
|
800fb22: 683b ldr r3, [r7, #0]
|
|
800fb24: 781b ldrb r3, [r3, #0]
|
|
800fb26: 009b lsls r3, r3, #2
|
|
800fb28: 4413 add r3, r2
|
|
800fb2a: 881b ldrh r3, [r3, #0]
|
|
800fb2c: b29b uxth r3, r3
|
|
800fb2e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fb32: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fb36: f8a7 3068 strh.w r3, [r7, #104] @ 0x68
|
|
800fb3a: 687a ldr r2, [r7, #4]
|
|
800fb3c: 683b ldr r3, [r7, #0]
|
|
800fb3e: 781b ldrb r3, [r3, #0]
|
|
800fb40: 009b lsls r3, r3, #2
|
|
800fb42: 441a add r2, r3
|
|
800fb44: f8b7 3068 ldrh.w r3, [r7, #104] @ 0x68
|
|
800fb48: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fb4c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fb50: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fb54: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800fb58: b29b uxth r3, r3
|
|
800fb5a: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
800fb5c: 683b ldr r3, [r7, #0]
|
|
800fb5e: 78db ldrb r3, [r3, #3]
|
|
800fb60: 2b01 cmp r3, #1
|
|
800fb62: d024 beq.n 800fbae <USB_ActivateEndpoint+0x946>
|
|
{
|
|
/* Configure NAK status for the Endpoint */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
|
800fb64: 687a ldr r2, [r7, #4]
|
|
800fb66: 683b ldr r3, [r7, #0]
|
|
800fb68: 781b ldrb r3, [r3, #0]
|
|
800fb6a: 009b lsls r3, r3, #2
|
|
800fb6c: 4413 add r3, r2
|
|
800fb6e: 881b ldrh r3, [r3, #0]
|
|
800fb70: b29b uxth r3, r3
|
|
800fb72: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fb76: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800fb7a: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
|
|
800fb7e: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
|
|
800fb82: f083 0320 eor.w r3, r3, #32
|
|
800fb86: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
|
|
800fb8a: 687a ldr r2, [r7, #4]
|
|
800fb8c: 683b ldr r3, [r7, #0]
|
|
800fb8e: 781b ldrb r3, [r3, #0]
|
|
800fb90: 009b lsls r3, r3, #2
|
|
800fb92: 441a add r2, r3
|
|
800fb94: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
|
|
800fb98: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fb9c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fba0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fba4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fba8: b29b uxth r3, r3
|
|
800fbaa: 8013 strh r3, [r2, #0]
|
|
800fbac: e01d b.n 800fbea <USB_ActivateEndpoint+0x982>
|
|
}
|
|
else
|
|
{
|
|
/* Configure TX Endpoint to disabled state */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
800fbae: 687a ldr r2, [r7, #4]
|
|
800fbb0: 683b ldr r3, [r7, #0]
|
|
800fbb2: 781b ldrb r3, [r3, #0]
|
|
800fbb4: 009b lsls r3, r3, #2
|
|
800fbb6: 4413 add r3, r2
|
|
800fbb8: 881b ldrh r3, [r3, #0]
|
|
800fbba: b29b uxth r3, r3
|
|
800fbbc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fbc0: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800fbc4: f8a7 3066 strh.w r3, [r7, #102] @ 0x66
|
|
800fbc8: 687a ldr r2, [r7, #4]
|
|
800fbca: 683b ldr r3, [r7, #0]
|
|
800fbcc: 781b ldrb r3, [r3, #0]
|
|
800fbce: 009b lsls r3, r3, #2
|
|
800fbd0: 441a add r2, r3
|
|
800fbd2: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66
|
|
800fbd6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fbda: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fbde: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fbe2: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fbe6: b29b uxth r3, r3
|
|
800fbe8: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
|
800fbea: 687a ldr r2, [r7, #4]
|
|
800fbec: 683b ldr r3, [r7, #0]
|
|
800fbee: 781b ldrb r3, [r3, #0]
|
|
800fbf0: 009b lsls r3, r3, #2
|
|
800fbf2: 4413 add r3, r2
|
|
800fbf4: 881b ldrh r3, [r3, #0]
|
|
800fbf6: b29b uxth r3, r3
|
|
800fbf8: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800fbfc: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fc00: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
|
|
800fc04: 687a ldr r2, [r7, #4]
|
|
800fc06: 683b ldr r3, [r7, #0]
|
|
800fc08: 781b ldrb r3, [r3, #0]
|
|
800fc0a: 009b lsls r3, r3, #2
|
|
800fc0c: 441a add r2, r3
|
|
800fc0e: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
|
|
800fc12: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fc16: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fc1a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fc1e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fc22: b29b uxth r3, r3
|
|
800fc24: 8013 strh r3, [r2, #0]
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
return ret;
|
|
800fc26: f897 3097 ldrb.w r3, [r7, #151] @ 0x97
|
|
}
|
|
800fc2a: 4618 mov r0, r3
|
|
800fc2c: 379c adds r7, #156 @ 0x9c
|
|
800fc2e: 46bd mov sp, r7
|
|
800fc30: f85d 7b04 ldr.w r7, [sp], #4
|
|
800fc34: 4770 bx lr
|
|
800fc36: bf00 nop
|
|
|
|
0800fc38 <USB_DeactivateEndpoint>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
800fc38: b480 push {r7}
|
|
800fc3a: b08d sub sp, #52 @ 0x34
|
|
800fc3c: af00 add r7, sp, #0
|
|
800fc3e: 6078 str r0, [r7, #4]
|
|
800fc40: 6039 str r1, [r7, #0]
|
|
if (ep->doublebuffer == 0U)
|
|
800fc42: 683b ldr r3, [r7, #0]
|
|
800fc44: 7b1b ldrb r3, [r3, #12]
|
|
800fc46: 2b00 cmp r3, #0
|
|
800fc48: f040 808e bne.w 800fd68 <USB_DeactivateEndpoint+0x130>
|
|
{
|
|
if (ep->is_in != 0U)
|
|
800fc4c: 683b ldr r3, [r7, #0]
|
|
800fc4e: 785b ldrb r3, [r3, #1]
|
|
800fc50: 2b00 cmp r3, #0
|
|
800fc52: d044 beq.n 800fcde <USB_DeactivateEndpoint+0xa6>
|
|
{
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
800fc54: 687a ldr r2, [r7, #4]
|
|
800fc56: 683b ldr r3, [r7, #0]
|
|
800fc58: 781b ldrb r3, [r3, #0]
|
|
800fc5a: 009b lsls r3, r3, #2
|
|
800fc5c: 4413 add r3, r2
|
|
800fc5e: 881b ldrh r3, [r3, #0]
|
|
800fc60: 81bb strh r3, [r7, #12]
|
|
800fc62: 89bb ldrh r3, [r7, #12]
|
|
800fc64: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800fc68: 2b00 cmp r3, #0
|
|
800fc6a: d01b beq.n 800fca4 <USB_DeactivateEndpoint+0x6c>
|
|
800fc6c: 687a ldr r2, [r7, #4]
|
|
800fc6e: 683b ldr r3, [r7, #0]
|
|
800fc70: 781b ldrb r3, [r3, #0]
|
|
800fc72: 009b lsls r3, r3, #2
|
|
800fc74: 4413 add r3, r2
|
|
800fc76: 881b ldrh r3, [r3, #0]
|
|
800fc78: b29b uxth r3, r3
|
|
800fc7a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fc7e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fc82: 817b strh r3, [r7, #10]
|
|
800fc84: 687a ldr r2, [r7, #4]
|
|
800fc86: 683b ldr r3, [r7, #0]
|
|
800fc88: 781b ldrb r3, [r3, #0]
|
|
800fc8a: 009b lsls r3, r3, #2
|
|
800fc8c: 441a add r2, r3
|
|
800fc8e: 897b ldrh r3, [r7, #10]
|
|
800fc90: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fc94: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fc98: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fc9c: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800fca0: b29b uxth r3, r3
|
|
800fca2: 8013 strh r3, [r2, #0]
|
|
|
|
/* Configure DISABLE status for the Endpoint */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
800fca4: 687a ldr r2, [r7, #4]
|
|
800fca6: 683b ldr r3, [r7, #0]
|
|
800fca8: 781b ldrb r3, [r3, #0]
|
|
800fcaa: 009b lsls r3, r3, #2
|
|
800fcac: 4413 add r3, r2
|
|
800fcae: 881b ldrh r3, [r3, #0]
|
|
800fcb0: b29b uxth r3, r3
|
|
800fcb2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fcb6: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800fcba: 813b strh r3, [r7, #8]
|
|
800fcbc: 687a ldr r2, [r7, #4]
|
|
800fcbe: 683b ldr r3, [r7, #0]
|
|
800fcc0: 781b ldrb r3, [r3, #0]
|
|
800fcc2: 009b lsls r3, r3, #2
|
|
800fcc4: 441a add r2, r3
|
|
800fcc6: 893b ldrh r3, [r7, #8]
|
|
800fcc8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fccc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fcd0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fcd4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fcd8: b29b uxth r3, r3
|
|
800fcda: 8013 strh r3, [r2, #0]
|
|
800fcdc: e192 b.n 8010004 <USB_DeactivateEndpoint+0x3cc>
|
|
}
|
|
|
|
else
|
|
{
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
800fcde: 687a ldr r2, [r7, #4]
|
|
800fce0: 683b ldr r3, [r7, #0]
|
|
800fce2: 781b ldrb r3, [r3, #0]
|
|
800fce4: 009b lsls r3, r3, #2
|
|
800fce6: 4413 add r3, r2
|
|
800fce8: 881b ldrh r3, [r3, #0]
|
|
800fcea: 827b strh r3, [r7, #18]
|
|
800fcec: 8a7b ldrh r3, [r7, #18]
|
|
800fcee: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800fcf2: 2b00 cmp r3, #0
|
|
800fcf4: d01b beq.n 800fd2e <USB_DeactivateEndpoint+0xf6>
|
|
800fcf6: 687a ldr r2, [r7, #4]
|
|
800fcf8: 683b ldr r3, [r7, #0]
|
|
800fcfa: 781b ldrb r3, [r3, #0]
|
|
800fcfc: 009b lsls r3, r3, #2
|
|
800fcfe: 4413 add r3, r2
|
|
800fd00: 881b ldrh r3, [r3, #0]
|
|
800fd02: b29b uxth r3, r3
|
|
800fd04: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fd08: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fd0c: 823b strh r3, [r7, #16]
|
|
800fd0e: 687a ldr r2, [r7, #4]
|
|
800fd10: 683b ldr r3, [r7, #0]
|
|
800fd12: 781b ldrb r3, [r3, #0]
|
|
800fd14: 009b lsls r3, r3, #2
|
|
800fd16: 441a add r2, r3
|
|
800fd18: 8a3b ldrh r3, [r7, #16]
|
|
800fd1a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fd1e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fd22: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800fd26: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fd2a: b29b uxth r3, r3
|
|
800fd2c: 8013 strh r3, [r2, #0]
|
|
|
|
/* Configure DISABLE status for the Endpoint */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
|
800fd2e: 687a ldr r2, [r7, #4]
|
|
800fd30: 683b ldr r3, [r7, #0]
|
|
800fd32: 781b ldrb r3, [r3, #0]
|
|
800fd34: 009b lsls r3, r3, #2
|
|
800fd36: 4413 add r3, r2
|
|
800fd38: 881b ldrh r3, [r3, #0]
|
|
800fd3a: b29b uxth r3, r3
|
|
800fd3c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800fd40: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fd44: 81fb strh r3, [r7, #14]
|
|
800fd46: 687a ldr r2, [r7, #4]
|
|
800fd48: 683b ldr r3, [r7, #0]
|
|
800fd4a: 781b ldrb r3, [r3, #0]
|
|
800fd4c: 009b lsls r3, r3, #2
|
|
800fd4e: 441a add r2, r3
|
|
800fd50: 89fb ldrh r3, [r7, #14]
|
|
800fd52: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fd56: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fd5a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fd5e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fd62: b29b uxth r3, r3
|
|
800fd64: 8013 strh r3, [r2, #0]
|
|
800fd66: e14d b.n 8010004 <USB_DeactivateEndpoint+0x3cc>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
/* Double Buffer */
|
|
else
|
|
{
|
|
if (ep->is_in == 0U)
|
|
800fd68: 683b ldr r3, [r7, #0]
|
|
800fd6a: 785b ldrb r3, [r3, #1]
|
|
800fd6c: 2b00 cmp r3, #0
|
|
800fd6e: f040 80a5 bne.w 800febc <USB_DeactivateEndpoint+0x284>
|
|
{
|
|
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
800fd72: 687a ldr r2, [r7, #4]
|
|
800fd74: 683b ldr r3, [r7, #0]
|
|
800fd76: 781b ldrb r3, [r3, #0]
|
|
800fd78: 009b lsls r3, r3, #2
|
|
800fd7a: 4413 add r3, r2
|
|
800fd7c: 881b ldrh r3, [r3, #0]
|
|
800fd7e: 843b strh r3, [r7, #32]
|
|
800fd80: 8c3b ldrh r3, [r7, #32]
|
|
800fd82: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800fd86: 2b00 cmp r3, #0
|
|
800fd88: d01b beq.n 800fdc2 <USB_DeactivateEndpoint+0x18a>
|
|
800fd8a: 687a ldr r2, [r7, #4]
|
|
800fd8c: 683b ldr r3, [r7, #0]
|
|
800fd8e: 781b ldrb r3, [r3, #0]
|
|
800fd90: 009b lsls r3, r3, #2
|
|
800fd92: 4413 add r3, r2
|
|
800fd94: 881b ldrh r3, [r3, #0]
|
|
800fd96: b29b uxth r3, r3
|
|
800fd98: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fd9c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fda0: 83fb strh r3, [r7, #30]
|
|
800fda2: 687a ldr r2, [r7, #4]
|
|
800fda4: 683b ldr r3, [r7, #0]
|
|
800fda6: 781b ldrb r3, [r3, #0]
|
|
800fda8: 009b lsls r3, r3, #2
|
|
800fdaa: 441a add r2, r3
|
|
800fdac: 8bfb ldrh r3, [r7, #30]
|
|
800fdae: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fdb2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fdb6: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800fdba: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fdbe: b29b uxth r3, r3
|
|
800fdc0: 8013 strh r3, [r2, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
800fdc2: 687a ldr r2, [r7, #4]
|
|
800fdc4: 683b ldr r3, [r7, #0]
|
|
800fdc6: 781b ldrb r3, [r3, #0]
|
|
800fdc8: 009b lsls r3, r3, #2
|
|
800fdca: 4413 add r3, r2
|
|
800fdcc: 881b ldrh r3, [r3, #0]
|
|
800fdce: 83bb strh r3, [r7, #28]
|
|
800fdd0: 8bbb ldrh r3, [r7, #28]
|
|
800fdd2: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800fdd6: 2b00 cmp r3, #0
|
|
800fdd8: d01b beq.n 800fe12 <USB_DeactivateEndpoint+0x1da>
|
|
800fdda: 687a ldr r2, [r7, #4]
|
|
800fddc: 683b ldr r3, [r7, #0]
|
|
800fdde: 781b ldrb r3, [r3, #0]
|
|
800fde0: 009b lsls r3, r3, #2
|
|
800fde2: 4413 add r3, r2
|
|
800fde4: 881b ldrh r3, [r3, #0]
|
|
800fde6: b29b uxth r3, r3
|
|
800fde8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fdec: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fdf0: 837b strh r3, [r7, #26]
|
|
800fdf2: 687a ldr r2, [r7, #4]
|
|
800fdf4: 683b ldr r3, [r7, #0]
|
|
800fdf6: 781b ldrb r3, [r3, #0]
|
|
800fdf8: 009b lsls r3, r3, #2
|
|
800fdfa: 441a add r2, r3
|
|
800fdfc: 8b7b ldrh r3, [r7, #26]
|
|
800fdfe: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fe02: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fe06: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fe0a: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800fe0e: b29b uxth r3, r3
|
|
800fe10: 8013 strh r3, [r2, #0]
|
|
|
|
/* Reset value of the data toggle bits for the endpoint out*/
|
|
PCD_TX_DTOG(USBx, ep->num);
|
|
800fe12: 687a ldr r2, [r7, #4]
|
|
800fe14: 683b ldr r3, [r7, #0]
|
|
800fe16: 781b ldrb r3, [r3, #0]
|
|
800fe18: 009b lsls r3, r3, #2
|
|
800fe1a: 4413 add r3, r2
|
|
800fe1c: 881b ldrh r3, [r3, #0]
|
|
800fe1e: b29b uxth r3, r3
|
|
800fe20: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fe24: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fe28: 833b strh r3, [r7, #24]
|
|
800fe2a: 687a ldr r2, [r7, #4]
|
|
800fe2c: 683b ldr r3, [r7, #0]
|
|
800fe2e: 781b ldrb r3, [r3, #0]
|
|
800fe30: 009b lsls r3, r3, #2
|
|
800fe32: 441a add r2, r3
|
|
800fe34: 8b3b ldrh r3, [r7, #24]
|
|
800fe36: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fe3a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fe3e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fe42: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800fe46: b29b uxth r3, r3
|
|
800fe48: 8013 strh r3, [r2, #0]
|
|
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
|
800fe4a: 687a ldr r2, [r7, #4]
|
|
800fe4c: 683b ldr r3, [r7, #0]
|
|
800fe4e: 781b ldrb r3, [r3, #0]
|
|
800fe50: 009b lsls r3, r3, #2
|
|
800fe52: 4413 add r3, r2
|
|
800fe54: 881b ldrh r3, [r3, #0]
|
|
800fe56: b29b uxth r3, r3
|
|
800fe58: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800fe5c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800fe60: 82fb strh r3, [r7, #22]
|
|
800fe62: 687a ldr r2, [r7, #4]
|
|
800fe64: 683b ldr r3, [r7, #0]
|
|
800fe66: 781b ldrb r3, [r3, #0]
|
|
800fe68: 009b lsls r3, r3, #2
|
|
800fe6a: 441a add r2, r3
|
|
800fe6c: 8afb ldrh r3, [r7, #22]
|
|
800fe6e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fe72: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fe76: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fe7a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800fe7e: b29b uxth r3, r3
|
|
800fe80: 8013 strh r3, [r2, #0]
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
800fe82: 687a ldr r2, [r7, #4]
|
|
800fe84: 683b ldr r3, [r7, #0]
|
|
800fe86: 781b ldrb r3, [r3, #0]
|
|
800fe88: 009b lsls r3, r3, #2
|
|
800fe8a: 4413 add r3, r2
|
|
800fe8c: 881b ldrh r3, [r3, #0]
|
|
800fe8e: b29b uxth r3, r3
|
|
800fe90: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fe94: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800fe98: 82bb strh r3, [r7, #20]
|
|
800fe9a: 687a ldr r2, [r7, #4]
|
|
800fe9c: 683b ldr r3, [r7, #0]
|
|
800fe9e: 781b ldrb r3, [r3, #0]
|
|
800fea0: 009b lsls r3, r3, #2
|
|
800fea2: 441a add r2, r3
|
|
800fea4: 8abb ldrh r3, [r7, #20]
|
|
800fea6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800feaa: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800feae: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800feb2: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800feb6: b29b uxth r3, r3
|
|
800feb8: 8013 strh r3, [r2, #0]
|
|
800feba: e0a3 b.n 8010004 <USB_DeactivateEndpoint+0x3cc>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
800febc: 687a ldr r2, [r7, #4]
|
|
800febe: 683b ldr r3, [r7, #0]
|
|
800fec0: 781b ldrb r3, [r3, #0]
|
|
800fec2: 009b lsls r3, r3, #2
|
|
800fec4: 4413 add r3, r2
|
|
800fec6: 881b ldrh r3, [r3, #0]
|
|
800fec8: 85fb strh r3, [r7, #46] @ 0x2e
|
|
800feca: 8dfb ldrh r3, [r7, #46] @ 0x2e
|
|
800fecc: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800fed0: 2b00 cmp r3, #0
|
|
800fed2: d01b beq.n 800ff0c <USB_DeactivateEndpoint+0x2d4>
|
|
800fed4: 687a ldr r2, [r7, #4]
|
|
800fed6: 683b ldr r3, [r7, #0]
|
|
800fed8: 781b ldrb r3, [r3, #0]
|
|
800feda: 009b lsls r3, r3, #2
|
|
800fedc: 4413 add r3, r2
|
|
800fede: 881b ldrh r3, [r3, #0]
|
|
800fee0: b29b uxth r3, r3
|
|
800fee2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800fee6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800feea: 85bb strh r3, [r7, #44] @ 0x2c
|
|
800feec: 687a ldr r2, [r7, #4]
|
|
800feee: 683b ldr r3, [r7, #0]
|
|
800fef0: 781b ldrb r3, [r3, #0]
|
|
800fef2: 009b lsls r3, r3, #2
|
|
800fef4: 441a add r2, r3
|
|
800fef6: 8dbb ldrh r3, [r7, #44] @ 0x2c
|
|
800fef8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fefc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800ff00: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800ff04: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800ff08: b29b uxth r3, r3
|
|
800ff0a: 8013 strh r3, [r2, #0]
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
800ff0c: 687a ldr r2, [r7, #4]
|
|
800ff0e: 683b ldr r3, [r7, #0]
|
|
800ff10: 781b ldrb r3, [r3, #0]
|
|
800ff12: 009b lsls r3, r3, #2
|
|
800ff14: 4413 add r3, r2
|
|
800ff16: 881b ldrh r3, [r3, #0]
|
|
800ff18: 857b strh r3, [r7, #42] @ 0x2a
|
|
800ff1a: 8d7b ldrh r3, [r7, #42] @ 0x2a
|
|
800ff1c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800ff20: 2b00 cmp r3, #0
|
|
800ff22: d01b beq.n 800ff5c <USB_DeactivateEndpoint+0x324>
|
|
800ff24: 687a ldr r2, [r7, #4]
|
|
800ff26: 683b ldr r3, [r7, #0]
|
|
800ff28: 781b ldrb r3, [r3, #0]
|
|
800ff2a: 009b lsls r3, r3, #2
|
|
800ff2c: 4413 add r3, r2
|
|
800ff2e: 881b ldrh r3, [r3, #0]
|
|
800ff30: b29b uxth r3, r3
|
|
800ff32: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800ff36: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800ff3a: 853b strh r3, [r7, #40] @ 0x28
|
|
800ff3c: 687a ldr r2, [r7, #4]
|
|
800ff3e: 683b ldr r3, [r7, #0]
|
|
800ff40: 781b ldrb r3, [r3, #0]
|
|
800ff42: 009b lsls r3, r3, #2
|
|
800ff44: 441a add r2, r3
|
|
800ff46: 8d3b ldrh r3, [r7, #40] @ 0x28
|
|
800ff48: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800ff4c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800ff50: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800ff54: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
800ff58: b29b uxth r3, r3
|
|
800ff5a: 8013 strh r3, [r2, #0]
|
|
PCD_RX_DTOG(USBx, ep->num);
|
|
800ff5c: 687a ldr r2, [r7, #4]
|
|
800ff5e: 683b ldr r3, [r7, #0]
|
|
800ff60: 781b ldrb r3, [r3, #0]
|
|
800ff62: 009b lsls r3, r3, #2
|
|
800ff64: 4413 add r3, r2
|
|
800ff66: 881b ldrh r3, [r3, #0]
|
|
800ff68: b29b uxth r3, r3
|
|
800ff6a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800ff6e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800ff72: 84fb strh r3, [r7, #38] @ 0x26
|
|
800ff74: 687a ldr r2, [r7, #4]
|
|
800ff76: 683b ldr r3, [r7, #0]
|
|
800ff78: 781b ldrb r3, [r3, #0]
|
|
800ff7a: 009b lsls r3, r3, #2
|
|
800ff7c: 441a add r2, r3
|
|
800ff7e: 8cfb ldrh r3, [r7, #38] @ 0x26
|
|
800ff80: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800ff84: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800ff88: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
800ff8c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800ff90: b29b uxth r3, r3
|
|
800ff92: 8013 strh r3, [r2, #0]
|
|
|
|
/* Configure DISABLE status for the Endpoint*/
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
|
800ff94: 687a ldr r2, [r7, #4]
|
|
800ff96: 683b ldr r3, [r7, #0]
|
|
800ff98: 781b ldrb r3, [r3, #0]
|
|
800ff9a: 009b lsls r3, r3, #2
|
|
800ff9c: 4413 add r3, r2
|
|
800ff9e: 881b ldrh r3, [r3, #0]
|
|
800ffa0: b29b uxth r3, r3
|
|
800ffa2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800ffa6: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800ffaa: 84bb strh r3, [r7, #36] @ 0x24
|
|
800ffac: 687a ldr r2, [r7, #4]
|
|
800ffae: 683b ldr r3, [r7, #0]
|
|
800ffb0: 781b ldrb r3, [r3, #0]
|
|
800ffb2: 009b lsls r3, r3, #2
|
|
800ffb4: 441a add r2, r3
|
|
800ffb6: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
800ffb8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800ffbc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800ffc0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800ffc4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800ffc8: b29b uxth r3, r3
|
|
800ffca: 8013 strh r3, [r2, #0]
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
|
800ffcc: 687a ldr r2, [r7, #4]
|
|
800ffce: 683b ldr r3, [r7, #0]
|
|
800ffd0: 781b ldrb r3, [r3, #0]
|
|
800ffd2: 009b lsls r3, r3, #2
|
|
800ffd4: 4413 add r3, r2
|
|
800ffd6: 881b ldrh r3, [r3, #0]
|
|
800ffd8: b29b uxth r3, r3
|
|
800ffda: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
800ffde: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800ffe2: 847b strh r3, [r7, #34] @ 0x22
|
|
800ffe4: 687a ldr r2, [r7, #4]
|
|
800ffe6: 683b ldr r3, [r7, #0]
|
|
800ffe8: 781b ldrb r3, [r3, #0]
|
|
800ffea: 009b lsls r3, r3, #2
|
|
800ffec: 441a add r2, r3
|
|
800ffee: 8c7b ldrh r3, [r7, #34] @ 0x22
|
|
800fff0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
800fff4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
800fff8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800fffc: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010000: b29b uxth r3, r3
|
|
8010002: 8013 strh r3, [r2, #0]
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
return HAL_OK;
|
|
8010004: 2300 movs r3, #0
|
|
}
|
|
8010006: 4618 mov r0, r3
|
|
8010008: 3734 adds r7, #52 @ 0x34
|
|
801000a: 46bd mov sp, r7
|
|
801000c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010010: 4770 bx lr
|
|
|
|
08010012 <USB_EPStartXfer>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
8010012: b580 push {r7, lr}
|
|
8010014: b0ac sub sp, #176 @ 0xb0
|
|
8010016: af00 add r7, sp, #0
|
|
8010018: 6078 str r0, [r7, #4]
|
|
801001a: 6039 str r1, [r7, #0]
|
|
uint16_t pmabuffer;
|
|
uint16_t wEPVal;
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
/* IN endpoint */
|
|
if (ep->is_in == 1U)
|
|
801001c: 683b ldr r3, [r7, #0]
|
|
801001e: 785b ldrb r3, [r3, #1]
|
|
8010020: 2b01 cmp r3, #1
|
|
8010022: f040 84ca bne.w 80109ba <USB_EPStartXfer+0x9a8>
|
|
{
|
|
/* Multi packet transfer */
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
8010026: 683b ldr r3, [r7, #0]
|
|
8010028: 699a ldr r2, [r3, #24]
|
|
801002a: 683b ldr r3, [r7, #0]
|
|
801002c: 691b ldr r3, [r3, #16]
|
|
801002e: 429a cmp r2, r3
|
|
8010030: d904 bls.n 801003c <USB_EPStartXfer+0x2a>
|
|
{
|
|
len = ep->maxpacket;
|
|
8010032: 683b ldr r3, [r7, #0]
|
|
8010034: 691b ldr r3, [r3, #16]
|
|
8010036: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
801003a: e003 b.n 8010044 <USB_EPStartXfer+0x32>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len;
|
|
801003c: 683b ldr r3, [r7, #0]
|
|
801003e: 699b ldr r3, [r3, #24]
|
|
8010040: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
}
|
|
|
|
/* configure and validate Tx endpoint */
|
|
if (ep->doublebuffer == 0U)
|
|
8010044: 683b ldr r3, [r7, #0]
|
|
8010046: 7b1b ldrb r3, [r3, #12]
|
|
8010048: 2b00 cmp r3, #0
|
|
801004a: d122 bne.n 8010092 <USB_EPStartXfer+0x80>
|
|
{
|
|
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
|
|
801004c: 683b ldr r3, [r7, #0]
|
|
801004e: 6959 ldr r1, [r3, #20]
|
|
8010050: 683b ldr r3, [r7, #0]
|
|
8010052: 88da ldrh r2, [r3, #6]
|
|
8010054: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010058: b29b uxth r3, r3
|
|
801005a: 6878 ldr r0, [r7, #4]
|
|
801005c: f000 febd bl 8010dda <USB_WritePMA>
|
|
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
|
|
8010060: 687b ldr r3, [r7, #4]
|
|
8010062: 613b str r3, [r7, #16]
|
|
8010064: 687b ldr r3, [r7, #4]
|
|
8010066: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
801006a: b29b uxth r3, r3
|
|
801006c: 461a mov r2, r3
|
|
801006e: 693b ldr r3, [r7, #16]
|
|
8010070: 4413 add r3, r2
|
|
8010072: 613b str r3, [r7, #16]
|
|
8010074: 683b ldr r3, [r7, #0]
|
|
8010076: 781b ldrb r3, [r3, #0]
|
|
8010078: 00da lsls r2, r3, #3
|
|
801007a: 693b ldr r3, [r7, #16]
|
|
801007c: 4413 add r3, r2
|
|
801007e: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
8010082: 60fb str r3, [r7, #12]
|
|
8010084: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010088: b29a uxth r2, r3
|
|
801008a: 68fb ldr r3, [r7, #12]
|
|
801008c: 801a strh r2, [r3, #0]
|
|
801008e: f000 bc6f b.w 8010970 <USB_EPStartXfer+0x95e>
|
|
}
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
else
|
|
{
|
|
/* double buffer bulk management */
|
|
if (ep->type == EP_TYPE_BULK)
|
|
8010092: 683b ldr r3, [r7, #0]
|
|
8010094: 78db ldrb r3, [r3, #3]
|
|
8010096: 2b02 cmp r3, #2
|
|
8010098: f040 831e bne.w 80106d8 <USB_EPStartXfer+0x6c6>
|
|
{
|
|
if (ep->xfer_len_db > ep->maxpacket)
|
|
801009c: 683b ldr r3, [r7, #0]
|
|
801009e: 6a1a ldr r2, [r3, #32]
|
|
80100a0: 683b ldr r3, [r7, #0]
|
|
80100a2: 691b ldr r3, [r3, #16]
|
|
80100a4: 429a cmp r2, r3
|
|
80100a6: f240 82cf bls.w 8010648 <USB_EPStartXfer+0x636>
|
|
{
|
|
/* enable double buffer */
|
|
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
|
|
80100aa: 687a ldr r2, [r7, #4]
|
|
80100ac: 683b ldr r3, [r7, #0]
|
|
80100ae: 781b ldrb r3, [r3, #0]
|
|
80100b0: 009b lsls r3, r3, #2
|
|
80100b2: 4413 add r3, r2
|
|
80100b4: 881b ldrh r3, [r3, #0]
|
|
80100b6: b29b uxth r3, r3
|
|
80100b8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80100bc: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80100c0: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
|
|
80100c4: 687a ldr r2, [r7, #4]
|
|
80100c6: 683b ldr r3, [r7, #0]
|
|
80100c8: 781b ldrb r3, [r3, #0]
|
|
80100ca: 009b lsls r3, r3, #2
|
|
80100cc: 441a add r2, r3
|
|
80100ce: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
|
|
80100d2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80100d6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80100da: f443 4301 orr.w r3, r3, #33024 @ 0x8100
|
|
80100de: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80100e2: b29b uxth r3, r3
|
|
80100e4: 8013 strh r3, [r2, #0]
|
|
|
|
/* each Time to write in PMA xfer_len_db will */
|
|
ep->xfer_len_db -= len;
|
|
80100e6: 683b ldr r3, [r7, #0]
|
|
80100e8: 6a1a ldr r2, [r3, #32]
|
|
80100ea: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80100ee: 1ad2 subs r2, r2, r3
|
|
80100f0: 683b ldr r3, [r7, #0]
|
|
80100f2: 621a str r2, [r3, #32]
|
|
|
|
/* Fill the two first buffer in the Buffer0 & Buffer1 */
|
|
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
|
|
80100f4: 687a ldr r2, [r7, #4]
|
|
80100f6: 683b ldr r3, [r7, #0]
|
|
80100f8: 781b ldrb r3, [r3, #0]
|
|
80100fa: 009b lsls r3, r3, #2
|
|
80100fc: 4413 add r3, r2
|
|
80100fe: 881b ldrh r3, [r3, #0]
|
|
8010100: b29b uxth r3, r3
|
|
8010102: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8010106: 2b00 cmp r3, #0
|
|
8010108: f000 814f beq.w 80103aa <USB_EPStartXfer+0x398>
|
|
{
|
|
/* Set the Double buffer counter for pmabuffer1 */
|
|
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
|
801010c: 687b ldr r3, [r7, #4]
|
|
801010e: 633b str r3, [r7, #48] @ 0x30
|
|
8010110: 683b ldr r3, [r7, #0]
|
|
8010112: 785b ldrb r3, [r3, #1]
|
|
8010114: 2b00 cmp r3, #0
|
|
8010116: d16b bne.n 80101f0 <USB_EPStartXfer+0x1de>
|
|
8010118: 687b ldr r3, [r7, #4]
|
|
801011a: 62bb str r3, [r7, #40] @ 0x28
|
|
801011c: 687b ldr r3, [r7, #4]
|
|
801011e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8010122: b29b uxth r3, r3
|
|
8010124: 461a mov r2, r3
|
|
8010126: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8010128: 4413 add r3, r2
|
|
801012a: 62bb str r3, [r7, #40] @ 0x28
|
|
801012c: 683b ldr r3, [r7, #0]
|
|
801012e: 781b ldrb r3, [r3, #0]
|
|
8010130: 00da lsls r2, r3, #3
|
|
8010132: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8010134: 4413 add r3, r2
|
|
8010136: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
801013a: 627b str r3, [r7, #36] @ 0x24
|
|
801013c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801013e: 881b ldrh r3, [r3, #0]
|
|
8010140: b29b uxth r3, r3
|
|
8010142: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8010146: b29a uxth r2, r3
|
|
8010148: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801014a: 801a strh r2, [r3, #0]
|
|
801014c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010150: 2b00 cmp r3, #0
|
|
8010152: d10a bne.n 801016a <USB_EPStartXfer+0x158>
|
|
8010154: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8010156: 881b ldrh r3, [r3, #0]
|
|
8010158: b29b uxth r3, r3
|
|
801015a: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
801015e: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8010162: b29a uxth r2, r3
|
|
8010164: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8010166: 801a strh r2, [r3, #0]
|
|
8010168: e05b b.n 8010222 <USB_EPStartXfer+0x210>
|
|
801016a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801016e: 2b3e cmp r3, #62 @ 0x3e
|
|
8010170: d81c bhi.n 80101ac <USB_EPStartXfer+0x19a>
|
|
8010172: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010176: 085b lsrs r3, r3, #1
|
|
8010178: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
801017c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010180: f003 0301 and.w r3, r3, #1
|
|
8010184: 2b00 cmp r3, #0
|
|
8010186: d004 beq.n 8010192 <USB_EPStartXfer+0x180>
|
|
8010188: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
801018c: 3301 adds r3, #1
|
|
801018e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
8010192: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8010194: 881b ldrh r3, [r3, #0]
|
|
8010196: b29a uxth r2, r3
|
|
8010198: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
801019c: b29b uxth r3, r3
|
|
801019e: 029b lsls r3, r3, #10
|
|
80101a0: b29b uxth r3, r3
|
|
80101a2: 4313 orrs r3, r2
|
|
80101a4: b29a uxth r2, r3
|
|
80101a6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80101a8: 801a strh r2, [r3, #0]
|
|
80101aa: e03a b.n 8010222 <USB_EPStartXfer+0x210>
|
|
80101ac: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80101b0: 095b lsrs r3, r3, #5
|
|
80101b2: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
80101b6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80101ba: f003 031f and.w r3, r3, #31
|
|
80101be: 2b00 cmp r3, #0
|
|
80101c0: d104 bne.n 80101cc <USB_EPStartXfer+0x1ba>
|
|
80101c2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
80101c6: 3b01 subs r3, #1
|
|
80101c8: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
80101cc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80101ce: 881b ldrh r3, [r3, #0]
|
|
80101d0: b29a uxth r2, r3
|
|
80101d2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
80101d6: b29b uxth r3, r3
|
|
80101d8: 029b lsls r3, r3, #10
|
|
80101da: b29b uxth r3, r3
|
|
80101dc: 4313 orrs r3, r2
|
|
80101de: b29b uxth r3, r3
|
|
80101e0: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80101e4: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80101e8: b29a uxth r2, r3
|
|
80101ea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80101ec: 801a strh r2, [r3, #0]
|
|
80101ee: e018 b.n 8010222 <USB_EPStartXfer+0x210>
|
|
80101f0: 683b ldr r3, [r7, #0]
|
|
80101f2: 785b ldrb r3, [r3, #1]
|
|
80101f4: 2b01 cmp r3, #1
|
|
80101f6: d114 bne.n 8010222 <USB_EPStartXfer+0x210>
|
|
80101f8: 687b ldr r3, [r7, #4]
|
|
80101fa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80101fe: b29b uxth r3, r3
|
|
8010200: 461a mov r2, r3
|
|
8010202: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8010204: 4413 add r3, r2
|
|
8010206: 633b str r3, [r7, #48] @ 0x30
|
|
8010208: 683b ldr r3, [r7, #0]
|
|
801020a: 781b ldrb r3, [r3, #0]
|
|
801020c: 00da lsls r2, r3, #3
|
|
801020e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8010210: 4413 add r3, r2
|
|
8010212: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
8010216: 62fb str r3, [r7, #44] @ 0x2c
|
|
8010218: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801021c: b29a uxth r2, r3
|
|
801021e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8010220: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr1;
|
|
8010222: 683b ldr r3, [r7, #0]
|
|
8010224: 895b ldrh r3, [r3, #10]
|
|
8010226: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
801022a: 683b ldr r3, [r7, #0]
|
|
801022c: 6959 ldr r1, [r3, #20]
|
|
801022e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010232: b29b uxth r3, r3
|
|
8010234: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
8010238: 6878 ldr r0, [r7, #4]
|
|
801023a: f000 fdce bl 8010dda <USB_WritePMA>
|
|
ep->xfer_buff += len;
|
|
801023e: 683b ldr r3, [r7, #0]
|
|
8010240: 695a ldr r2, [r3, #20]
|
|
8010242: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010246: 441a add r2, r3
|
|
8010248: 683b ldr r3, [r7, #0]
|
|
801024a: 615a str r2, [r3, #20]
|
|
|
|
if (ep->xfer_len_db > ep->maxpacket)
|
|
801024c: 683b ldr r3, [r7, #0]
|
|
801024e: 6a1a ldr r2, [r3, #32]
|
|
8010250: 683b ldr r3, [r7, #0]
|
|
8010252: 691b ldr r3, [r3, #16]
|
|
8010254: 429a cmp r2, r3
|
|
8010256: d907 bls.n 8010268 <USB_EPStartXfer+0x256>
|
|
{
|
|
ep->xfer_len_db -= len;
|
|
8010258: 683b ldr r3, [r7, #0]
|
|
801025a: 6a1a ldr r2, [r3, #32]
|
|
801025c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010260: 1ad2 subs r2, r2, r3
|
|
8010262: 683b ldr r3, [r7, #0]
|
|
8010264: 621a str r2, [r3, #32]
|
|
8010266: e006 b.n 8010276 <USB_EPStartXfer+0x264>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len_db;
|
|
8010268: 683b ldr r3, [r7, #0]
|
|
801026a: 6a1b ldr r3, [r3, #32]
|
|
801026c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
ep->xfer_len_db = 0U;
|
|
8010270: 683b ldr r3, [r7, #0]
|
|
8010272: 2200 movs r2, #0
|
|
8010274: 621a str r2, [r3, #32]
|
|
}
|
|
|
|
/* Set the Double buffer counter for pmabuffer0 */
|
|
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
|
8010276: 683b ldr r3, [r7, #0]
|
|
8010278: 785b ldrb r3, [r3, #1]
|
|
801027a: 2b00 cmp r3, #0
|
|
801027c: d16b bne.n 8010356 <USB_EPStartXfer+0x344>
|
|
801027e: 687b ldr r3, [r7, #4]
|
|
8010280: 61bb str r3, [r7, #24]
|
|
8010282: 687b ldr r3, [r7, #4]
|
|
8010284: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8010288: b29b uxth r3, r3
|
|
801028a: 461a mov r2, r3
|
|
801028c: 69bb ldr r3, [r7, #24]
|
|
801028e: 4413 add r3, r2
|
|
8010290: 61bb str r3, [r7, #24]
|
|
8010292: 683b ldr r3, [r7, #0]
|
|
8010294: 781b ldrb r3, [r3, #0]
|
|
8010296: 00da lsls r2, r3, #3
|
|
8010298: 69bb ldr r3, [r7, #24]
|
|
801029a: 4413 add r3, r2
|
|
801029c: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
80102a0: 617b str r3, [r7, #20]
|
|
80102a2: 697b ldr r3, [r7, #20]
|
|
80102a4: 881b ldrh r3, [r3, #0]
|
|
80102a6: b29b uxth r3, r3
|
|
80102a8: f3c3 0309 ubfx r3, r3, #0, #10
|
|
80102ac: b29a uxth r2, r3
|
|
80102ae: 697b ldr r3, [r7, #20]
|
|
80102b0: 801a strh r2, [r3, #0]
|
|
80102b2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80102b6: 2b00 cmp r3, #0
|
|
80102b8: d10a bne.n 80102d0 <USB_EPStartXfer+0x2be>
|
|
80102ba: 697b ldr r3, [r7, #20]
|
|
80102bc: 881b ldrh r3, [r3, #0]
|
|
80102be: b29b uxth r3, r3
|
|
80102c0: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80102c4: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80102c8: b29a uxth r2, r3
|
|
80102ca: 697b ldr r3, [r7, #20]
|
|
80102cc: 801a strh r2, [r3, #0]
|
|
80102ce: e05d b.n 801038c <USB_EPStartXfer+0x37a>
|
|
80102d0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80102d4: 2b3e cmp r3, #62 @ 0x3e
|
|
80102d6: d81c bhi.n 8010312 <USB_EPStartXfer+0x300>
|
|
80102d8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80102dc: 085b lsrs r3, r3, #1
|
|
80102de: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
80102e2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80102e6: f003 0301 and.w r3, r3, #1
|
|
80102ea: 2b00 cmp r3, #0
|
|
80102ec: d004 beq.n 80102f8 <USB_EPStartXfer+0x2e6>
|
|
80102ee: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
80102f2: 3301 adds r3, #1
|
|
80102f4: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
80102f8: 697b ldr r3, [r7, #20]
|
|
80102fa: 881b ldrh r3, [r3, #0]
|
|
80102fc: b29a uxth r2, r3
|
|
80102fe: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8010302: b29b uxth r3, r3
|
|
8010304: 029b lsls r3, r3, #10
|
|
8010306: b29b uxth r3, r3
|
|
8010308: 4313 orrs r3, r2
|
|
801030a: b29a uxth r2, r3
|
|
801030c: 697b ldr r3, [r7, #20]
|
|
801030e: 801a strh r2, [r3, #0]
|
|
8010310: e03c b.n 801038c <USB_EPStartXfer+0x37a>
|
|
8010312: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010316: 095b lsrs r3, r3, #5
|
|
8010318: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
801031c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010320: f003 031f and.w r3, r3, #31
|
|
8010324: 2b00 cmp r3, #0
|
|
8010326: d104 bne.n 8010332 <USB_EPStartXfer+0x320>
|
|
8010328: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
801032c: 3b01 subs r3, #1
|
|
801032e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
8010332: 697b ldr r3, [r7, #20]
|
|
8010334: 881b ldrh r3, [r3, #0]
|
|
8010336: b29a uxth r2, r3
|
|
8010338: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
801033c: b29b uxth r3, r3
|
|
801033e: 029b lsls r3, r3, #10
|
|
8010340: b29b uxth r3, r3
|
|
8010342: 4313 orrs r3, r2
|
|
8010344: b29b uxth r3, r3
|
|
8010346: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
801034a: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
801034e: b29a uxth r2, r3
|
|
8010350: 697b ldr r3, [r7, #20]
|
|
8010352: 801a strh r2, [r3, #0]
|
|
8010354: e01a b.n 801038c <USB_EPStartXfer+0x37a>
|
|
8010356: 683b ldr r3, [r7, #0]
|
|
8010358: 785b ldrb r3, [r3, #1]
|
|
801035a: 2b01 cmp r3, #1
|
|
801035c: d116 bne.n 801038c <USB_EPStartXfer+0x37a>
|
|
801035e: 687b ldr r3, [r7, #4]
|
|
8010360: 623b str r3, [r7, #32]
|
|
8010362: 687b ldr r3, [r7, #4]
|
|
8010364: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8010368: b29b uxth r3, r3
|
|
801036a: 461a mov r2, r3
|
|
801036c: 6a3b ldr r3, [r7, #32]
|
|
801036e: 4413 add r3, r2
|
|
8010370: 623b str r3, [r7, #32]
|
|
8010372: 683b ldr r3, [r7, #0]
|
|
8010374: 781b ldrb r3, [r3, #0]
|
|
8010376: 00da lsls r2, r3, #3
|
|
8010378: 6a3b ldr r3, [r7, #32]
|
|
801037a: 4413 add r3, r2
|
|
801037c: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
8010380: 61fb str r3, [r7, #28]
|
|
8010382: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010386: b29a uxth r2, r3
|
|
8010388: 69fb ldr r3, [r7, #28]
|
|
801038a: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr0;
|
|
801038c: 683b ldr r3, [r7, #0]
|
|
801038e: 891b ldrh r3, [r3, #8]
|
|
8010390: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
8010394: 683b ldr r3, [r7, #0]
|
|
8010396: 6959 ldr r1, [r3, #20]
|
|
8010398: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801039c: b29b uxth r3, r3
|
|
801039e: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
80103a2: 6878 ldr r0, [r7, #4]
|
|
80103a4: f000 fd19 bl 8010dda <USB_WritePMA>
|
|
80103a8: e2e2 b.n 8010970 <USB_EPStartXfer+0x95e>
|
|
}
|
|
else
|
|
{
|
|
/* Set the Double buffer counter for pmabuffer0 */
|
|
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
|
80103aa: 683b ldr r3, [r7, #0]
|
|
80103ac: 785b ldrb r3, [r3, #1]
|
|
80103ae: 2b00 cmp r3, #0
|
|
80103b0: d16b bne.n 801048a <USB_EPStartXfer+0x478>
|
|
80103b2: 687b ldr r3, [r7, #4]
|
|
80103b4: 64bb str r3, [r7, #72] @ 0x48
|
|
80103b6: 687b ldr r3, [r7, #4]
|
|
80103b8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80103bc: b29b uxth r3, r3
|
|
80103be: 461a mov r2, r3
|
|
80103c0: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80103c2: 4413 add r3, r2
|
|
80103c4: 64bb str r3, [r7, #72] @ 0x48
|
|
80103c6: 683b ldr r3, [r7, #0]
|
|
80103c8: 781b ldrb r3, [r3, #0]
|
|
80103ca: 00da lsls r2, r3, #3
|
|
80103cc: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80103ce: 4413 add r3, r2
|
|
80103d0: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
80103d4: 647b str r3, [r7, #68] @ 0x44
|
|
80103d6: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80103d8: 881b ldrh r3, [r3, #0]
|
|
80103da: b29b uxth r3, r3
|
|
80103dc: f3c3 0309 ubfx r3, r3, #0, #10
|
|
80103e0: b29a uxth r2, r3
|
|
80103e2: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80103e4: 801a strh r2, [r3, #0]
|
|
80103e6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80103ea: 2b00 cmp r3, #0
|
|
80103ec: d10a bne.n 8010404 <USB_EPStartXfer+0x3f2>
|
|
80103ee: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
80103f0: 881b ldrh r3, [r3, #0]
|
|
80103f2: b29b uxth r3, r3
|
|
80103f4: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80103f8: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80103fc: b29a uxth r2, r3
|
|
80103fe: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8010400: 801a strh r2, [r3, #0]
|
|
8010402: e05d b.n 80104c0 <USB_EPStartXfer+0x4ae>
|
|
8010404: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010408: 2b3e cmp r3, #62 @ 0x3e
|
|
801040a: d81c bhi.n 8010446 <USB_EPStartXfer+0x434>
|
|
801040c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010410: 085b lsrs r3, r3, #1
|
|
8010412: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
8010416: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801041a: f003 0301 and.w r3, r3, #1
|
|
801041e: 2b00 cmp r3, #0
|
|
8010420: d004 beq.n 801042c <USB_EPStartXfer+0x41a>
|
|
8010422: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8010426: 3301 adds r3, #1
|
|
8010428: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
801042c: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
801042e: 881b ldrh r3, [r3, #0]
|
|
8010430: b29a uxth r2, r3
|
|
8010432: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8010436: b29b uxth r3, r3
|
|
8010438: 029b lsls r3, r3, #10
|
|
801043a: b29b uxth r3, r3
|
|
801043c: 4313 orrs r3, r2
|
|
801043e: b29a uxth r2, r3
|
|
8010440: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8010442: 801a strh r2, [r3, #0]
|
|
8010444: e03c b.n 80104c0 <USB_EPStartXfer+0x4ae>
|
|
8010446: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801044a: 095b lsrs r3, r3, #5
|
|
801044c: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
8010450: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010454: f003 031f and.w r3, r3, #31
|
|
8010458: 2b00 cmp r3, #0
|
|
801045a: d104 bne.n 8010466 <USB_EPStartXfer+0x454>
|
|
801045c: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8010460: 3b01 subs r3, #1
|
|
8010462: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
8010466: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8010468: 881b ldrh r3, [r3, #0]
|
|
801046a: b29a uxth r2, r3
|
|
801046c: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8010470: b29b uxth r3, r3
|
|
8010472: 029b lsls r3, r3, #10
|
|
8010474: b29b uxth r3, r3
|
|
8010476: 4313 orrs r3, r2
|
|
8010478: b29b uxth r3, r3
|
|
801047a: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
801047e: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8010482: b29a uxth r2, r3
|
|
8010484: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8010486: 801a strh r2, [r3, #0]
|
|
8010488: e01a b.n 80104c0 <USB_EPStartXfer+0x4ae>
|
|
801048a: 683b ldr r3, [r7, #0]
|
|
801048c: 785b ldrb r3, [r3, #1]
|
|
801048e: 2b01 cmp r3, #1
|
|
8010490: d116 bne.n 80104c0 <USB_EPStartXfer+0x4ae>
|
|
8010492: 687b ldr r3, [r7, #4]
|
|
8010494: 653b str r3, [r7, #80] @ 0x50
|
|
8010496: 687b ldr r3, [r7, #4]
|
|
8010498: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
801049c: b29b uxth r3, r3
|
|
801049e: 461a mov r2, r3
|
|
80104a0: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80104a2: 4413 add r3, r2
|
|
80104a4: 653b str r3, [r7, #80] @ 0x50
|
|
80104a6: 683b ldr r3, [r7, #0]
|
|
80104a8: 781b ldrb r3, [r3, #0]
|
|
80104aa: 00da lsls r2, r3, #3
|
|
80104ac: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80104ae: 4413 add r3, r2
|
|
80104b0: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
80104b4: 64fb str r3, [r7, #76] @ 0x4c
|
|
80104b6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80104ba: b29a uxth r2, r3
|
|
80104bc: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80104be: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr0;
|
|
80104c0: 683b ldr r3, [r7, #0]
|
|
80104c2: 891b ldrh r3, [r3, #8]
|
|
80104c4: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
80104c8: 683b ldr r3, [r7, #0]
|
|
80104ca: 6959 ldr r1, [r3, #20]
|
|
80104cc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80104d0: b29b uxth r3, r3
|
|
80104d2: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
80104d6: 6878 ldr r0, [r7, #4]
|
|
80104d8: f000 fc7f bl 8010dda <USB_WritePMA>
|
|
ep->xfer_buff += len;
|
|
80104dc: 683b ldr r3, [r7, #0]
|
|
80104de: 695a ldr r2, [r3, #20]
|
|
80104e0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80104e4: 441a add r2, r3
|
|
80104e6: 683b ldr r3, [r7, #0]
|
|
80104e8: 615a str r2, [r3, #20]
|
|
|
|
if (ep->xfer_len_db > ep->maxpacket)
|
|
80104ea: 683b ldr r3, [r7, #0]
|
|
80104ec: 6a1a ldr r2, [r3, #32]
|
|
80104ee: 683b ldr r3, [r7, #0]
|
|
80104f0: 691b ldr r3, [r3, #16]
|
|
80104f2: 429a cmp r2, r3
|
|
80104f4: d907 bls.n 8010506 <USB_EPStartXfer+0x4f4>
|
|
{
|
|
ep->xfer_len_db -= len;
|
|
80104f6: 683b ldr r3, [r7, #0]
|
|
80104f8: 6a1a ldr r2, [r3, #32]
|
|
80104fa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80104fe: 1ad2 subs r2, r2, r3
|
|
8010500: 683b ldr r3, [r7, #0]
|
|
8010502: 621a str r2, [r3, #32]
|
|
8010504: e006 b.n 8010514 <USB_EPStartXfer+0x502>
|
|
}
|
|
else
|
|
{
|
|
len = ep->xfer_len_db;
|
|
8010506: 683b ldr r3, [r7, #0]
|
|
8010508: 6a1b ldr r3, [r3, #32]
|
|
801050a: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
ep->xfer_len_db = 0U;
|
|
801050e: 683b ldr r3, [r7, #0]
|
|
8010510: 2200 movs r2, #0
|
|
8010512: 621a str r2, [r3, #32]
|
|
}
|
|
|
|
/* Set the Double buffer counter for pmabuffer1 */
|
|
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
|
8010514: 687b ldr r3, [r7, #4]
|
|
8010516: 643b str r3, [r7, #64] @ 0x40
|
|
8010518: 683b ldr r3, [r7, #0]
|
|
801051a: 785b ldrb r3, [r3, #1]
|
|
801051c: 2b00 cmp r3, #0
|
|
801051e: d16b bne.n 80105f8 <USB_EPStartXfer+0x5e6>
|
|
8010520: 687b ldr r3, [r7, #4]
|
|
8010522: 63bb str r3, [r7, #56] @ 0x38
|
|
8010524: 687b ldr r3, [r7, #4]
|
|
8010526: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
801052a: b29b uxth r3, r3
|
|
801052c: 461a mov r2, r3
|
|
801052e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8010530: 4413 add r3, r2
|
|
8010532: 63bb str r3, [r7, #56] @ 0x38
|
|
8010534: 683b ldr r3, [r7, #0]
|
|
8010536: 781b ldrb r3, [r3, #0]
|
|
8010538: 00da lsls r2, r3, #3
|
|
801053a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
801053c: 4413 add r3, r2
|
|
801053e: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
8010542: 637b str r3, [r7, #52] @ 0x34
|
|
8010544: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8010546: 881b ldrh r3, [r3, #0]
|
|
8010548: b29b uxth r3, r3
|
|
801054a: f3c3 0309 ubfx r3, r3, #0, #10
|
|
801054e: b29a uxth r2, r3
|
|
8010550: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8010552: 801a strh r2, [r3, #0]
|
|
8010554: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010558: 2b00 cmp r3, #0
|
|
801055a: d10a bne.n 8010572 <USB_EPStartXfer+0x560>
|
|
801055c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
801055e: 881b ldrh r3, [r3, #0]
|
|
8010560: b29b uxth r3, r3
|
|
8010562: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8010566: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
801056a: b29a uxth r2, r3
|
|
801056c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
801056e: 801a strh r2, [r3, #0]
|
|
8010570: e05b b.n 801062a <USB_EPStartXfer+0x618>
|
|
8010572: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010576: 2b3e cmp r3, #62 @ 0x3e
|
|
8010578: d81c bhi.n 80105b4 <USB_EPStartXfer+0x5a2>
|
|
801057a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801057e: 085b lsrs r3, r3, #1
|
|
8010580: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8010584: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010588: f003 0301 and.w r3, r3, #1
|
|
801058c: 2b00 cmp r3, #0
|
|
801058e: d004 beq.n 801059a <USB_EPStartXfer+0x588>
|
|
8010590: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8010594: 3301 adds r3, #1
|
|
8010596: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
801059a: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
801059c: 881b ldrh r3, [r3, #0]
|
|
801059e: b29a uxth r2, r3
|
|
80105a0: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
80105a4: b29b uxth r3, r3
|
|
80105a6: 029b lsls r3, r3, #10
|
|
80105a8: b29b uxth r3, r3
|
|
80105aa: 4313 orrs r3, r2
|
|
80105ac: b29a uxth r2, r3
|
|
80105ae: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80105b0: 801a strh r2, [r3, #0]
|
|
80105b2: e03a b.n 801062a <USB_EPStartXfer+0x618>
|
|
80105b4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80105b8: 095b lsrs r3, r3, #5
|
|
80105ba: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
80105be: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80105c2: f003 031f and.w r3, r3, #31
|
|
80105c6: 2b00 cmp r3, #0
|
|
80105c8: d104 bne.n 80105d4 <USB_EPStartXfer+0x5c2>
|
|
80105ca: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
80105ce: 3b01 subs r3, #1
|
|
80105d0: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
80105d4: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80105d6: 881b ldrh r3, [r3, #0]
|
|
80105d8: b29a uxth r2, r3
|
|
80105da: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
80105de: b29b uxth r3, r3
|
|
80105e0: 029b lsls r3, r3, #10
|
|
80105e2: b29b uxth r3, r3
|
|
80105e4: 4313 orrs r3, r2
|
|
80105e6: b29b uxth r3, r3
|
|
80105e8: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80105ec: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80105f0: b29a uxth r2, r3
|
|
80105f2: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80105f4: 801a strh r2, [r3, #0]
|
|
80105f6: e018 b.n 801062a <USB_EPStartXfer+0x618>
|
|
80105f8: 683b ldr r3, [r7, #0]
|
|
80105fa: 785b ldrb r3, [r3, #1]
|
|
80105fc: 2b01 cmp r3, #1
|
|
80105fe: d114 bne.n 801062a <USB_EPStartXfer+0x618>
|
|
8010600: 687b ldr r3, [r7, #4]
|
|
8010602: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8010606: b29b uxth r3, r3
|
|
8010608: 461a mov r2, r3
|
|
801060a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
801060c: 4413 add r3, r2
|
|
801060e: 643b str r3, [r7, #64] @ 0x40
|
|
8010610: 683b ldr r3, [r7, #0]
|
|
8010612: 781b ldrb r3, [r3, #0]
|
|
8010614: 00da lsls r2, r3, #3
|
|
8010616: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8010618: 4413 add r3, r2
|
|
801061a: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
801061e: 63fb str r3, [r7, #60] @ 0x3c
|
|
8010620: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010624: b29a uxth r2, r3
|
|
8010626: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8010628: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr1;
|
|
801062a: 683b ldr r3, [r7, #0]
|
|
801062c: 895b ldrh r3, [r3, #10]
|
|
801062e: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
8010632: 683b ldr r3, [r7, #0]
|
|
8010634: 6959 ldr r1, [r3, #20]
|
|
8010636: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801063a: b29b uxth r3, r3
|
|
801063c: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
8010640: 6878 ldr r0, [r7, #4]
|
|
8010642: f000 fbca bl 8010dda <USB_WritePMA>
|
|
8010646: e193 b.n 8010970 <USB_EPStartXfer+0x95e>
|
|
}
|
|
}
|
|
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
|
|
else
|
|
{
|
|
len = ep->xfer_len_db;
|
|
8010648: 683b ldr r3, [r7, #0]
|
|
801064a: 6a1b ldr r3, [r3, #32]
|
|
801064c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
|
|
/* disable double buffer mode for Bulk endpoint */
|
|
PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
|
|
8010650: 687a ldr r2, [r7, #4]
|
|
8010652: 683b ldr r3, [r7, #0]
|
|
8010654: 781b ldrb r3, [r3, #0]
|
|
8010656: 009b lsls r3, r3, #2
|
|
8010658: 4413 add r3, r2
|
|
801065a: 881b ldrh r3, [r3, #0]
|
|
801065c: b29b uxth r3, r3
|
|
801065e: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
|
|
8010662: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8010666: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
|
|
801066a: 687a ldr r2, [r7, #4]
|
|
801066c: 683b ldr r3, [r7, #0]
|
|
801066e: 781b ldrb r3, [r3, #0]
|
|
8010670: 009b lsls r3, r3, #2
|
|
8010672: 441a add r2, r3
|
|
8010674: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
|
|
8010678: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
801067c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010680: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010684: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010688: b29b uxth r3, r3
|
|
801068a: 8013 strh r3, [r2, #0]
|
|
|
|
/* Set Tx count with nbre of byte to be transmitted */
|
|
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
|
|
801068c: 687b ldr r3, [r7, #4]
|
|
801068e: 65fb str r3, [r7, #92] @ 0x5c
|
|
8010690: 687b ldr r3, [r7, #4]
|
|
8010692: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8010696: b29b uxth r3, r3
|
|
8010698: 461a mov r2, r3
|
|
801069a: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
801069c: 4413 add r3, r2
|
|
801069e: 65fb str r3, [r7, #92] @ 0x5c
|
|
80106a0: 683b ldr r3, [r7, #0]
|
|
80106a2: 781b ldrb r3, [r3, #0]
|
|
80106a4: 00da lsls r2, r3, #3
|
|
80106a6: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80106a8: 4413 add r3, r2
|
|
80106aa: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
80106ae: 65bb str r3, [r7, #88] @ 0x58
|
|
80106b0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80106b4: b29a uxth r2, r3
|
|
80106b6: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80106b8: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr0;
|
|
80106ba: 683b ldr r3, [r7, #0]
|
|
80106bc: 891b ldrh r3, [r3, #8]
|
|
80106be: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
80106c2: 683b ldr r3, [r7, #0]
|
|
80106c4: 6959 ldr r1, [r3, #20]
|
|
80106c6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80106ca: b29b uxth r3, r3
|
|
80106cc: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
80106d0: 6878 ldr r0, [r7, #4]
|
|
80106d2: f000 fb82 bl 8010dda <USB_WritePMA>
|
|
80106d6: e14b b.n 8010970 <USB_EPStartXfer+0x95e>
|
|
}
|
|
}
|
|
else /* Manage isochronous double buffer IN mode */
|
|
{
|
|
/* Each Time to write in PMA xfer_len_db will */
|
|
ep->xfer_len_db -= len;
|
|
80106d8: 683b ldr r3, [r7, #0]
|
|
80106da: 6a1a ldr r2, [r3, #32]
|
|
80106dc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80106e0: 1ad2 subs r2, r2, r3
|
|
80106e2: 683b ldr r3, [r7, #0]
|
|
80106e4: 621a str r2, [r3, #32]
|
|
|
|
/* Fill the data buffer */
|
|
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
|
|
80106e6: 687a ldr r2, [r7, #4]
|
|
80106e8: 683b ldr r3, [r7, #0]
|
|
80106ea: 781b ldrb r3, [r3, #0]
|
|
80106ec: 009b lsls r3, r3, #2
|
|
80106ee: 4413 add r3, r2
|
|
80106f0: 881b ldrh r3, [r3, #0]
|
|
80106f2: b29b uxth r3, r3
|
|
80106f4: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80106f8: 2b00 cmp r3, #0
|
|
80106fa: f000 809a beq.w 8010832 <USB_EPStartXfer+0x820>
|
|
{
|
|
/* Set the Double buffer counter for pmabuffer1 */
|
|
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
|
80106fe: 687b ldr r3, [r7, #4]
|
|
8010700: 673b str r3, [r7, #112] @ 0x70
|
|
8010702: 683b ldr r3, [r7, #0]
|
|
8010704: 785b ldrb r3, [r3, #1]
|
|
8010706: 2b00 cmp r3, #0
|
|
8010708: d16b bne.n 80107e2 <USB_EPStartXfer+0x7d0>
|
|
801070a: 687b ldr r3, [r7, #4]
|
|
801070c: 66bb str r3, [r7, #104] @ 0x68
|
|
801070e: 687b ldr r3, [r7, #4]
|
|
8010710: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8010714: b29b uxth r3, r3
|
|
8010716: 461a mov r2, r3
|
|
8010718: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
801071a: 4413 add r3, r2
|
|
801071c: 66bb str r3, [r7, #104] @ 0x68
|
|
801071e: 683b ldr r3, [r7, #0]
|
|
8010720: 781b ldrb r3, [r3, #0]
|
|
8010722: 00da lsls r2, r3, #3
|
|
8010724: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8010726: 4413 add r3, r2
|
|
8010728: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
801072c: 667b str r3, [r7, #100] @ 0x64
|
|
801072e: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8010730: 881b ldrh r3, [r3, #0]
|
|
8010732: b29b uxth r3, r3
|
|
8010734: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8010738: b29a uxth r2, r3
|
|
801073a: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
801073c: 801a strh r2, [r3, #0]
|
|
801073e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010742: 2b00 cmp r3, #0
|
|
8010744: d10a bne.n 801075c <USB_EPStartXfer+0x74a>
|
|
8010746: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8010748: 881b ldrh r3, [r3, #0]
|
|
801074a: b29b uxth r3, r3
|
|
801074c: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8010750: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8010754: b29a uxth r2, r3
|
|
8010756: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8010758: 801a strh r2, [r3, #0]
|
|
801075a: e05b b.n 8010814 <USB_EPStartXfer+0x802>
|
|
801075c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010760: 2b3e cmp r3, #62 @ 0x3e
|
|
8010762: d81c bhi.n 801079e <USB_EPStartXfer+0x78c>
|
|
8010764: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010768: 085b lsrs r3, r3, #1
|
|
801076a: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
801076e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010772: f003 0301 and.w r3, r3, #1
|
|
8010776: 2b00 cmp r3, #0
|
|
8010778: d004 beq.n 8010784 <USB_EPStartXfer+0x772>
|
|
801077a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
801077e: 3301 adds r3, #1
|
|
8010780: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8010784: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8010786: 881b ldrh r3, [r3, #0]
|
|
8010788: b29a uxth r2, r3
|
|
801078a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
801078e: b29b uxth r3, r3
|
|
8010790: 029b lsls r3, r3, #10
|
|
8010792: b29b uxth r3, r3
|
|
8010794: 4313 orrs r3, r2
|
|
8010796: b29a uxth r2, r3
|
|
8010798: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
801079a: 801a strh r2, [r3, #0]
|
|
801079c: e03a b.n 8010814 <USB_EPStartXfer+0x802>
|
|
801079e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80107a2: 095b lsrs r3, r3, #5
|
|
80107a4: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
80107a8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80107ac: f003 031f and.w r3, r3, #31
|
|
80107b0: 2b00 cmp r3, #0
|
|
80107b2: d104 bne.n 80107be <USB_EPStartXfer+0x7ac>
|
|
80107b4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80107b8: 3b01 subs r3, #1
|
|
80107ba: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
80107be: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80107c0: 881b ldrh r3, [r3, #0]
|
|
80107c2: b29a uxth r2, r3
|
|
80107c4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80107c8: b29b uxth r3, r3
|
|
80107ca: 029b lsls r3, r3, #10
|
|
80107cc: b29b uxth r3, r3
|
|
80107ce: 4313 orrs r3, r2
|
|
80107d0: b29b uxth r3, r3
|
|
80107d2: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
80107d6: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
80107da: b29a uxth r2, r3
|
|
80107dc: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80107de: 801a strh r2, [r3, #0]
|
|
80107e0: e018 b.n 8010814 <USB_EPStartXfer+0x802>
|
|
80107e2: 683b ldr r3, [r7, #0]
|
|
80107e4: 785b ldrb r3, [r3, #1]
|
|
80107e6: 2b01 cmp r3, #1
|
|
80107e8: d114 bne.n 8010814 <USB_EPStartXfer+0x802>
|
|
80107ea: 687b ldr r3, [r7, #4]
|
|
80107ec: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
80107f0: b29b uxth r3, r3
|
|
80107f2: 461a mov r2, r3
|
|
80107f4: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
80107f6: 4413 add r3, r2
|
|
80107f8: 673b str r3, [r7, #112] @ 0x70
|
|
80107fa: 683b ldr r3, [r7, #0]
|
|
80107fc: 781b ldrb r3, [r3, #0]
|
|
80107fe: 00da lsls r2, r3, #3
|
|
8010800: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8010802: 4413 add r3, r2
|
|
8010804: f203 4306 addw r3, r3, #1030 @ 0x406
|
|
8010808: 66fb str r3, [r7, #108] @ 0x6c
|
|
801080a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801080e: b29a uxth r2, r3
|
|
8010810: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8010812: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr1;
|
|
8010814: 683b ldr r3, [r7, #0]
|
|
8010816: 895b ldrh r3, [r3, #10]
|
|
8010818: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
801081c: 683b ldr r3, [r7, #0]
|
|
801081e: 6959 ldr r1, [r3, #20]
|
|
8010820: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010824: b29b uxth r3, r3
|
|
8010826: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
801082a: 6878 ldr r0, [r7, #4]
|
|
801082c: f000 fad5 bl 8010dda <USB_WritePMA>
|
|
8010830: e09e b.n 8010970 <USB_EPStartXfer+0x95e>
|
|
}
|
|
else
|
|
{
|
|
/* Set the Double buffer counter for pmabuffer0 */
|
|
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
|
8010832: 683b ldr r3, [r7, #0]
|
|
8010834: 785b ldrb r3, [r3, #1]
|
|
8010836: 2b00 cmp r3, #0
|
|
8010838: d16b bne.n 8010912 <USB_EPStartXfer+0x900>
|
|
801083a: 687b ldr r3, [r7, #4]
|
|
801083c: 67fb str r3, [r7, #124] @ 0x7c
|
|
801083e: 687b ldr r3, [r7, #4]
|
|
8010840: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8010844: b29b uxth r3, r3
|
|
8010846: 461a mov r2, r3
|
|
8010848: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
801084a: 4413 add r3, r2
|
|
801084c: 67fb str r3, [r7, #124] @ 0x7c
|
|
801084e: 683b ldr r3, [r7, #0]
|
|
8010850: 781b ldrb r3, [r3, #0]
|
|
8010852: 00da lsls r2, r3, #3
|
|
8010854: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
8010856: 4413 add r3, r2
|
|
8010858: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
801085c: 67bb str r3, [r7, #120] @ 0x78
|
|
801085e: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8010860: 881b ldrh r3, [r3, #0]
|
|
8010862: b29b uxth r3, r3
|
|
8010864: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8010868: b29a uxth r2, r3
|
|
801086a: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
801086c: 801a strh r2, [r3, #0]
|
|
801086e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010872: 2b00 cmp r3, #0
|
|
8010874: d10a bne.n 801088c <USB_EPStartXfer+0x87a>
|
|
8010876: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8010878: 881b ldrh r3, [r3, #0]
|
|
801087a: b29b uxth r3, r3
|
|
801087c: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8010880: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8010884: b29a uxth r2, r3
|
|
8010886: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8010888: 801a strh r2, [r3, #0]
|
|
801088a: e063 b.n 8010954 <USB_EPStartXfer+0x942>
|
|
801088c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010890: 2b3e cmp r3, #62 @ 0x3e
|
|
8010892: d81c bhi.n 80108ce <USB_EPStartXfer+0x8bc>
|
|
8010894: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010898: 085b lsrs r3, r3, #1
|
|
801089a: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
801089e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80108a2: f003 0301 and.w r3, r3, #1
|
|
80108a6: 2b00 cmp r3, #0
|
|
80108a8: d004 beq.n 80108b4 <USB_EPStartXfer+0x8a2>
|
|
80108aa: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
|
|
80108ae: 3301 adds r3, #1
|
|
80108b0: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
80108b4: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80108b6: 881b ldrh r3, [r3, #0]
|
|
80108b8: b29a uxth r2, r3
|
|
80108ba: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
|
|
80108be: b29b uxth r3, r3
|
|
80108c0: 029b lsls r3, r3, #10
|
|
80108c2: b29b uxth r3, r3
|
|
80108c4: 4313 orrs r3, r2
|
|
80108c6: b29a uxth r2, r3
|
|
80108c8: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80108ca: 801a strh r2, [r3, #0]
|
|
80108cc: e042 b.n 8010954 <USB_EPStartXfer+0x942>
|
|
80108ce: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80108d2: 095b lsrs r3, r3, #5
|
|
80108d4: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
80108d8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80108dc: f003 031f and.w r3, r3, #31
|
|
80108e0: 2b00 cmp r3, #0
|
|
80108e2: d104 bne.n 80108ee <USB_EPStartXfer+0x8dc>
|
|
80108e4: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
|
|
80108e8: 3b01 subs r3, #1
|
|
80108ea: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
80108ee: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80108f0: 881b ldrh r3, [r3, #0]
|
|
80108f2: b29a uxth r2, r3
|
|
80108f4: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
|
|
80108f8: b29b uxth r3, r3
|
|
80108fa: 029b lsls r3, r3, #10
|
|
80108fc: b29b uxth r3, r3
|
|
80108fe: 4313 orrs r3, r2
|
|
8010900: b29b uxth r3, r3
|
|
8010902: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8010906: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
801090a: b29a uxth r2, r3
|
|
801090c: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
801090e: 801a strh r2, [r3, #0]
|
|
8010910: e020 b.n 8010954 <USB_EPStartXfer+0x942>
|
|
8010912: 683b ldr r3, [r7, #0]
|
|
8010914: 785b ldrb r3, [r3, #1]
|
|
8010916: 2b01 cmp r3, #1
|
|
8010918: d11c bne.n 8010954 <USB_EPStartXfer+0x942>
|
|
801091a: 687b ldr r3, [r7, #4]
|
|
801091c: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8010920: 687b ldr r3, [r7, #4]
|
|
8010922: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
|
|
8010926: b29b uxth r3, r3
|
|
8010928: 461a mov r2, r3
|
|
801092a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
801092e: 4413 add r3, r2
|
|
8010930: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8010934: 683b ldr r3, [r7, #0]
|
|
8010936: 781b ldrb r3, [r3, #0]
|
|
8010938: 00da lsls r2, r3, #3
|
|
801093a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
801093e: 4413 add r3, r2
|
|
8010940: f203 4302 addw r3, r3, #1026 @ 0x402
|
|
8010944: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8010948: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
801094c: b29a uxth r2, r3
|
|
801094e: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8010952: 801a strh r2, [r3, #0]
|
|
pmabuffer = ep->pmaaddr0;
|
|
8010954: 683b ldr r3, [r7, #0]
|
|
8010956: 891b ldrh r3, [r3, #8]
|
|
8010958: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
|
|
|
|
/* Write the user buffer to USB PMA */
|
|
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
|
801095c: 683b ldr r3, [r7, #0]
|
|
801095e: 6959 ldr r1, [r3, #20]
|
|
8010960: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8010964: b29b uxth r3, r3
|
|
8010966: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
|
|
801096a: 6878 ldr r0, [r7, #4]
|
|
801096c: f000 fa35 bl 8010dda <USB_WritePMA>
|
|
}
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
|
|
8010970: 687a ldr r2, [r7, #4]
|
|
8010972: 683b ldr r3, [r7, #0]
|
|
8010974: 781b ldrb r3, [r3, #0]
|
|
8010976: 009b lsls r3, r3, #2
|
|
8010978: 4413 add r3, r2
|
|
801097a: 881b ldrh r3, [r3, #0]
|
|
801097c: b29b uxth r3, r3
|
|
801097e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8010982: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8010986: 817b strh r3, [r7, #10]
|
|
8010988: 897b ldrh r3, [r7, #10]
|
|
801098a: f083 0310 eor.w r3, r3, #16
|
|
801098e: 817b strh r3, [r7, #10]
|
|
8010990: 897b ldrh r3, [r7, #10]
|
|
8010992: f083 0320 eor.w r3, r3, #32
|
|
8010996: 817b strh r3, [r7, #10]
|
|
8010998: 687a ldr r2, [r7, #4]
|
|
801099a: 683b ldr r3, [r7, #0]
|
|
801099c: 781b ldrb r3, [r3, #0]
|
|
801099e: 009b lsls r3, r3, #2
|
|
80109a0: 441a add r2, r3
|
|
80109a2: 897b ldrh r3, [r7, #10]
|
|
80109a4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80109a8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
80109ac: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80109b0: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80109b4: b29b uxth r3, r3
|
|
80109b6: 8013 strh r3, [r2, #0]
|
|
80109b8: e0d5 b.n 8010b66 <USB_EPStartXfer+0xb54>
|
|
}
|
|
else /* OUT endpoint */
|
|
{
|
|
if (ep->doublebuffer == 0U)
|
|
80109ba: 683b ldr r3, [r7, #0]
|
|
80109bc: 7b1b ldrb r3, [r3, #12]
|
|
80109be: 2b00 cmp r3, #0
|
|
80109c0: d156 bne.n 8010a70 <USB_EPStartXfer+0xa5e>
|
|
{
|
|
if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL))
|
|
80109c2: 683b ldr r3, [r7, #0]
|
|
80109c4: 699b ldr r3, [r3, #24]
|
|
80109c6: 2b00 cmp r3, #0
|
|
80109c8: d122 bne.n 8010a10 <USB_EPStartXfer+0x9fe>
|
|
80109ca: 683b ldr r3, [r7, #0]
|
|
80109cc: 78db ldrb r3, [r3, #3]
|
|
80109ce: 2b00 cmp r3, #0
|
|
80109d0: d11e bne.n 8010a10 <USB_EPStartXfer+0x9fe>
|
|
{
|
|
/* This is a status out stage set the OUT_STATUS */
|
|
PCD_SET_OUT_STATUS(USBx, ep->num);
|
|
80109d2: 687a ldr r2, [r7, #4]
|
|
80109d4: 683b ldr r3, [r7, #0]
|
|
80109d6: 781b ldrb r3, [r3, #0]
|
|
80109d8: 009b lsls r3, r3, #2
|
|
80109da: 4413 add r3, r2
|
|
80109dc: 881b ldrh r3, [r3, #0]
|
|
80109de: b29b uxth r3, r3
|
|
80109e0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80109e4: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80109e8: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
|
|
80109ec: 687a ldr r2, [r7, #4]
|
|
80109ee: 683b ldr r3, [r7, #0]
|
|
80109f0: 781b ldrb r3, [r3, #0]
|
|
80109f2: 009b lsls r3, r3, #2
|
|
80109f4: 441a add r2, r3
|
|
80109f6: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
|
|
80109fa: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
80109fe: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010a02: f443 4301 orr.w r3, r3, #33024 @ 0x8100
|
|
8010a06: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010a0a: b29b uxth r3, r3
|
|
8010a0c: 8013 strh r3, [r2, #0]
|
|
8010a0e: e01d b.n 8010a4c <USB_EPStartXfer+0xa3a>
|
|
}
|
|
else
|
|
{
|
|
PCD_CLEAR_OUT_STATUS(USBx, ep->num);
|
|
8010a10: 687a ldr r2, [r7, #4]
|
|
8010a12: 683b ldr r3, [r7, #0]
|
|
8010a14: 781b ldrb r3, [r3, #0]
|
|
8010a16: 009b lsls r3, r3, #2
|
|
8010a18: 4413 add r3, r2
|
|
8010a1a: 881b ldrh r3, [r3, #0]
|
|
8010a1c: b29b uxth r3, r3
|
|
8010a1e: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
|
|
8010a22: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8010a26: f8a7 308c strh.w r3, [r7, #140] @ 0x8c
|
|
8010a2a: 687a ldr r2, [r7, #4]
|
|
8010a2c: 683b ldr r3, [r7, #0]
|
|
8010a2e: 781b ldrb r3, [r3, #0]
|
|
8010a30: 009b lsls r3, r3, #2
|
|
8010a32: 441a add r2, r3
|
|
8010a34: f8b7 308c ldrh.w r3, [r7, #140] @ 0x8c
|
|
8010a38: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010a3c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010a40: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010a44: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010a48: b29b uxth r3, r3
|
|
8010a4a: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
/* Multi packet transfer */
|
|
if (ep->xfer_len > ep->maxpacket)
|
|
8010a4c: 683b ldr r3, [r7, #0]
|
|
8010a4e: 699a ldr r2, [r3, #24]
|
|
8010a50: 683b ldr r3, [r7, #0]
|
|
8010a52: 691b ldr r3, [r3, #16]
|
|
8010a54: 429a cmp r2, r3
|
|
8010a56: d907 bls.n 8010a68 <USB_EPStartXfer+0xa56>
|
|
{
|
|
ep->xfer_len -= ep->maxpacket;
|
|
8010a58: 683b ldr r3, [r7, #0]
|
|
8010a5a: 699a ldr r2, [r3, #24]
|
|
8010a5c: 683b ldr r3, [r7, #0]
|
|
8010a5e: 691b ldr r3, [r3, #16]
|
|
8010a60: 1ad2 subs r2, r2, r3
|
|
8010a62: 683b ldr r3, [r7, #0]
|
|
8010a64: 619a str r2, [r3, #24]
|
|
8010a66: e054 b.n 8010b12 <USB_EPStartXfer+0xb00>
|
|
}
|
|
else
|
|
{
|
|
ep->xfer_len = 0U;
|
|
8010a68: 683b ldr r3, [r7, #0]
|
|
8010a6a: 2200 movs r2, #0
|
|
8010a6c: 619a str r2, [r3, #24]
|
|
8010a6e: e050 b.n 8010b12 <USB_EPStartXfer+0xb00>
|
|
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
|
else
|
|
{
|
|
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
|
|
/* Set the Double buffer counter */
|
|
if (ep->type == EP_TYPE_BULK)
|
|
8010a70: 683b ldr r3, [r7, #0]
|
|
8010a72: 78db ldrb r3, [r3, #3]
|
|
8010a74: 2b02 cmp r3, #2
|
|
8010a76: d142 bne.n 8010afe <USB_EPStartXfer+0xaec>
|
|
{
|
|
/* Coming from ISR */
|
|
if (ep->xfer_count != 0U)
|
|
8010a78: 683b ldr r3, [r7, #0]
|
|
8010a7a: 69db ldr r3, [r3, #28]
|
|
8010a7c: 2b00 cmp r3, #0
|
|
8010a7e: d048 beq.n 8010b12 <USB_EPStartXfer+0xb00>
|
|
{
|
|
/* Update last value to check if there is blocking state */
|
|
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
|
|
8010a80: 687a ldr r2, [r7, #4]
|
|
8010a82: 683b ldr r3, [r7, #0]
|
|
8010a84: 781b ldrb r3, [r3, #0]
|
|
8010a86: 009b lsls r3, r3, #2
|
|
8010a88: 4413 add r3, r2
|
|
8010a8a: 881b ldrh r3, [r3, #0]
|
|
8010a8c: f8a7 3092 strh.w r3, [r7, #146] @ 0x92
|
|
|
|
/* Blocking State */
|
|
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
|
|
8010a90: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
|
|
8010a94: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8010a98: 2b00 cmp r3, #0
|
|
8010a9a: d005 beq.n 8010aa8 <USB_EPStartXfer+0xa96>
|
|
8010a9c: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
|
|
8010aa0: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8010aa4: 2b00 cmp r3, #0
|
|
8010aa6: d10b bne.n 8010ac0 <USB_EPStartXfer+0xaae>
|
|
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
|
|
8010aa8: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
|
|
8010aac: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
|
|
8010ab0: 2b00 cmp r3, #0
|
|
8010ab2: d12e bne.n 8010b12 <USB_EPStartXfer+0xb00>
|
|
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
|
|
8010ab4: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
|
|
8010ab8: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8010abc: 2b00 cmp r3, #0
|
|
8010abe: d128 bne.n 8010b12 <USB_EPStartXfer+0xb00>
|
|
{
|
|
PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
|
|
8010ac0: 687a ldr r2, [r7, #4]
|
|
8010ac2: 683b ldr r3, [r7, #0]
|
|
8010ac4: 781b ldrb r3, [r3, #0]
|
|
8010ac6: 009b lsls r3, r3, #2
|
|
8010ac8: 4413 add r3, r2
|
|
8010aca: 881b ldrh r3, [r3, #0]
|
|
8010acc: b29b uxth r3, r3
|
|
8010ace: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8010ad2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8010ad6: f8a7 3090 strh.w r3, [r7, #144] @ 0x90
|
|
8010ada: 687a ldr r2, [r7, #4]
|
|
8010adc: 683b ldr r3, [r7, #0]
|
|
8010ade: 781b ldrb r3, [r3, #0]
|
|
8010ae0: 009b lsls r3, r3, #2
|
|
8010ae2: 441a add r2, r3
|
|
8010ae4: f8b7 3090 ldrh.w r3, [r7, #144] @ 0x90
|
|
8010ae8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010aec: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010af0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010af4: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8010af8: b29b uxth r3, r3
|
|
8010afa: 8013 strh r3, [r2, #0]
|
|
8010afc: e009 b.n 8010b12 <USB_EPStartXfer+0xb00>
|
|
}
|
|
}
|
|
}
|
|
/* iso out double */
|
|
else if (ep->type == EP_TYPE_ISOC)
|
|
8010afe: 683b ldr r3, [r7, #0]
|
|
8010b00: 78db ldrb r3, [r3, #3]
|
|
8010b02: 2b01 cmp r3, #1
|
|
8010b04: d103 bne.n 8010b0e <USB_EPStartXfer+0xafc>
|
|
{
|
|
/* Only single packet transfer supported in FS */
|
|
ep->xfer_len = 0U;
|
|
8010b06: 683b ldr r3, [r7, #0]
|
|
8010b08: 2200 movs r2, #0
|
|
8010b0a: 619a str r2, [r3, #24]
|
|
8010b0c: e001 b.n 8010b12 <USB_EPStartXfer+0xb00>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
8010b0e: 2301 movs r3, #1
|
|
8010b10: e02a b.n 8010b68 <USB_EPStartXfer+0xb56>
|
|
}
|
|
}
|
|
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
|
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
|
8010b12: 687a ldr r2, [r7, #4]
|
|
8010b14: 683b ldr r3, [r7, #0]
|
|
8010b16: 781b ldrb r3, [r3, #0]
|
|
8010b18: 009b lsls r3, r3, #2
|
|
8010b1a: 4413 add r3, r2
|
|
8010b1c: 881b ldrh r3, [r3, #0]
|
|
8010b1e: b29b uxth r3, r3
|
|
8010b20: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8010b24: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8010b28: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
8010b2c: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
8010b30: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8010b34: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
8010b38: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
8010b3c: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
8010b40: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
8010b44: 687a ldr r2, [r7, #4]
|
|
8010b46: 683b ldr r3, [r7, #0]
|
|
8010b48: 781b ldrb r3, [r3, #0]
|
|
8010b4a: 009b lsls r3, r3, #2
|
|
8010b4c: 441a add r2, r3
|
|
8010b4e: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
8010b52: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010b56: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010b5a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010b5e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010b62: b29b uxth r3, r3
|
|
8010b64: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8010b66: 2300 movs r3, #0
|
|
}
|
|
8010b68: 4618 mov r0, r3
|
|
8010b6a: 37b0 adds r7, #176 @ 0xb0
|
|
8010b6c: 46bd mov sp, r7
|
|
8010b6e: bd80 pop {r7, pc}
|
|
|
|
08010b70 <USB_EPSetStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
8010b70: b480 push {r7}
|
|
8010b72: b085 sub sp, #20
|
|
8010b74: af00 add r7, sp, #0
|
|
8010b76: 6078 str r0, [r7, #4]
|
|
8010b78: 6039 str r1, [r7, #0]
|
|
if (ep->is_in != 0U)
|
|
8010b7a: 683b ldr r3, [r7, #0]
|
|
8010b7c: 785b ldrb r3, [r3, #1]
|
|
8010b7e: 2b00 cmp r3, #0
|
|
8010b80: d020 beq.n 8010bc4 <USB_EPSetStall+0x54>
|
|
{
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
|
|
8010b82: 687a ldr r2, [r7, #4]
|
|
8010b84: 683b ldr r3, [r7, #0]
|
|
8010b86: 781b ldrb r3, [r3, #0]
|
|
8010b88: 009b lsls r3, r3, #2
|
|
8010b8a: 4413 add r3, r2
|
|
8010b8c: 881b ldrh r3, [r3, #0]
|
|
8010b8e: b29b uxth r3, r3
|
|
8010b90: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8010b94: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8010b98: 81bb strh r3, [r7, #12]
|
|
8010b9a: 89bb ldrh r3, [r7, #12]
|
|
8010b9c: f083 0310 eor.w r3, r3, #16
|
|
8010ba0: 81bb strh r3, [r7, #12]
|
|
8010ba2: 687a ldr r2, [r7, #4]
|
|
8010ba4: 683b ldr r3, [r7, #0]
|
|
8010ba6: 781b ldrb r3, [r3, #0]
|
|
8010ba8: 009b lsls r3, r3, #2
|
|
8010baa: 441a add r2, r3
|
|
8010bac: 89bb ldrh r3, [r7, #12]
|
|
8010bae: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010bb2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010bb6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010bba: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010bbe: b29b uxth r3, r3
|
|
8010bc0: 8013 strh r3, [r2, #0]
|
|
8010bc2: e01f b.n 8010c04 <USB_EPSetStall+0x94>
|
|
}
|
|
else
|
|
{
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
|
|
8010bc4: 687a ldr r2, [r7, #4]
|
|
8010bc6: 683b ldr r3, [r7, #0]
|
|
8010bc8: 781b ldrb r3, [r3, #0]
|
|
8010bca: 009b lsls r3, r3, #2
|
|
8010bcc: 4413 add r3, r2
|
|
8010bce: 881b ldrh r3, [r3, #0]
|
|
8010bd0: b29b uxth r3, r3
|
|
8010bd2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8010bd6: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8010bda: 81fb strh r3, [r7, #14]
|
|
8010bdc: 89fb ldrh r3, [r7, #14]
|
|
8010bde: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8010be2: 81fb strh r3, [r7, #14]
|
|
8010be4: 687a ldr r2, [r7, #4]
|
|
8010be6: 683b ldr r3, [r7, #0]
|
|
8010be8: 781b ldrb r3, [r3, #0]
|
|
8010bea: 009b lsls r3, r3, #2
|
|
8010bec: 441a add r2, r3
|
|
8010bee: 89fb ldrh r3, [r7, #14]
|
|
8010bf0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010bf4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010bf8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010bfc: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010c00: b29b uxth r3, r3
|
|
8010c02: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8010c04: 2300 movs r3, #0
|
|
}
|
|
8010c06: 4618 mov r0, r3
|
|
8010c08: 3714 adds r7, #20
|
|
8010c0a: 46bd mov sp, r7
|
|
8010c0c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010c10: 4770 bx lr
|
|
|
|
08010c12 <USB_EPClearStall>:
|
|
* @param USBx Selected device
|
|
* @param ep pointer to endpoint structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
|
{
|
|
8010c12: b480 push {r7}
|
|
8010c14: b087 sub sp, #28
|
|
8010c16: af00 add r7, sp, #0
|
|
8010c18: 6078 str r0, [r7, #4]
|
|
8010c1a: 6039 str r1, [r7, #0]
|
|
if (ep->is_in != 0U)
|
|
8010c1c: 683b ldr r3, [r7, #0]
|
|
8010c1e: 785b ldrb r3, [r3, #1]
|
|
8010c20: 2b00 cmp r3, #0
|
|
8010c22: d04c beq.n 8010cbe <USB_EPClearStall+0xac>
|
|
{
|
|
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
|
8010c24: 687a ldr r2, [r7, #4]
|
|
8010c26: 683b ldr r3, [r7, #0]
|
|
8010c28: 781b ldrb r3, [r3, #0]
|
|
8010c2a: 009b lsls r3, r3, #2
|
|
8010c2c: 4413 add r3, r2
|
|
8010c2e: 881b ldrh r3, [r3, #0]
|
|
8010c30: 823b strh r3, [r7, #16]
|
|
8010c32: 8a3b ldrh r3, [r7, #16]
|
|
8010c34: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8010c38: 2b00 cmp r3, #0
|
|
8010c3a: d01b beq.n 8010c74 <USB_EPClearStall+0x62>
|
|
8010c3c: 687a ldr r2, [r7, #4]
|
|
8010c3e: 683b ldr r3, [r7, #0]
|
|
8010c40: 781b ldrb r3, [r3, #0]
|
|
8010c42: 009b lsls r3, r3, #2
|
|
8010c44: 4413 add r3, r2
|
|
8010c46: 881b ldrh r3, [r3, #0]
|
|
8010c48: b29b uxth r3, r3
|
|
8010c4a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8010c4e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8010c52: 81fb strh r3, [r7, #14]
|
|
8010c54: 687a ldr r2, [r7, #4]
|
|
8010c56: 683b ldr r3, [r7, #0]
|
|
8010c58: 781b ldrb r3, [r3, #0]
|
|
8010c5a: 009b lsls r3, r3, #2
|
|
8010c5c: 441a add r2, r3
|
|
8010c5e: 89fb ldrh r3, [r7, #14]
|
|
8010c60: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010c64: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010c68: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010c6c: f043 03c0 orr.w r3, r3, #192 @ 0xc0
|
|
8010c70: b29b uxth r3, r3
|
|
8010c72: 8013 strh r3, [r2, #0]
|
|
|
|
if (ep->type != EP_TYPE_ISOC)
|
|
8010c74: 683b ldr r3, [r7, #0]
|
|
8010c76: 78db ldrb r3, [r3, #3]
|
|
8010c78: 2b01 cmp r3, #1
|
|
8010c7a: d06c beq.n 8010d56 <USB_EPClearStall+0x144>
|
|
{
|
|
/* Configure NAK status for the Endpoint */
|
|
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
|
8010c7c: 687a ldr r2, [r7, #4]
|
|
8010c7e: 683b ldr r3, [r7, #0]
|
|
8010c80: 781b ldrb r3, [r3, #0]
|
|
8010c82: 009b lsls r3, r3, #2
|
|
8010c84: 4413 add r3, r2
|
|
8010c86: 881b ldrh r3, [r3, #0]
|
|
8010c88: b29b uxth r3, r3
|
|
8010c8a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8010c8e: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8010c92: 81bb strh r3, [r7, #12]
|
|
8010c94: 89bb ldrh r3, [r7, #12]
|
|
8010c96: f083 0320 eor.w r3, r3, #32
|
|
8010c9a: 81bb strh r3, [r7, #12]
|
|
8010c9c: 687a ldr r2, [r7, #4]
|
|
8010c9e: 683b ldr r3, [r7, #0]
|
|
8010ca0: 781b ldrb r3, [r3, #0]
|
|
8010ca2: 009b lsls r3, r3, #2
|
|
8010ca4: 441a add r2, r3
|
|
8010ca6: 89bb ldrh r3, [r7, #12]
|
|
8010ca8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010cac: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010cb0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010cb4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010cb8: b29b uxth r3, r3
|
|
8010cba: 8013 strh r3, [r2, #0]
|
|
8010cbc: e04b b.n 8010d56 <USB_EPClearStall+0x144>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
|
8010cbe: 687a ldr r2, [r7, #4]
|
|
8010cc0: 683b ldr r3, [r7, #0]
|
|
8010cc2: 781b ldrb r3, [r3, #0]
|
|
8010cc4: 009b lsls r3, r3, #2
|
|
8010cc6: 4413 add r3, r2
|
|
8010cc8: 881b ldrh r3, [r3, #0]
|
|
8010cca: 82fb strh r3, [r7, #22]
|
|
8010ccc: 8afb ldrh r3, [r7, #22]
|
|
8010cce: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8010cd2: 2b00 cmp r3, #0
|
|
8010cd4: d01b beq.n 8010d0e <USB_EPClearStall+0xfc>
|
|
8010cd6: 687a ldr r2, [r7, #4]
|
|
8010cd8: 683b ldr r3, [r7, #0]
|
|
8010cda: 781b ldrb r3, [r3, #0]
|
|
8010cdc: 009b lsls r3, r3, #2
|
|
8010cde: 4413 add r3, r2
|
|
8010ce0: 881b ldrh r3, [r3, #0]
|
|
8010ce2: b29b uxth r3, r3
|
|
8010ce4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
8010ce8: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8010cec: 82bb strh r3, [r7, #20]
|
|
8010cee: 687a ldr r2, [r7, #4]
|
|
8010cf0: 683b ldr r3, [r7, #0]
|
|
8010cf2: 781b ldrb r3, [r3, #0]
|
|
8010cf4: 009b lsls r3, r3, #2
|
|
8010cf6: 441a add r2, r3
|
|
8010cf8: 8abb ldrh r3, [r7, #20]
|
|
8010cfa: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010cfe: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010d02: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8010d06: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010d0a: b29b uxth r3, r3
|
|
8010d0c: 8013 strh r3, [r2, #0]
|
|
|
|
/* Configure VALID status for the Endpoint */
|
|
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
|
8010d0e: 687a ldr r2, [r7, #4]
|
|
8010d10: 683b ldr r3, [r7, #0]
|
|
8010d12: 781b ldrb r3, [r3, #0]
|
|
8010d14: 009b lsls r3, r3, #2
|
|
8010d16: 4413 add r3, r2
|
|
8010d18: 881b ldrh r3, [r3, #0]
|
|
8010d1a: b29b uxth r3, r3
|
|
8010d1c: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8010d20: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8010d24: 827b strh r3, [r7, #18]
|
|
8010d26: 8a7b ldrh r3, [r7, #18]
|
|
8010d28: f483 5380 eor.w r3, r3, #4096 @ 0x1000
|
|
8010d2c: 827b strh r3, [r7, #18]
|
|
8010d2e: 8a7b ldrh r3, [r7, #18]
|
|
8010d30: f483 5300 eor.w r3, r3, #8192 @ 0x2000
|
|
8010d34: 827b strh r3, [r7, #18]
|
|
8010d36: 687a ldr r2, [r7, #4]
|
|
8010d38: 683b ldr r3, [r7, #0]
|
|
8010d3a: 781b ldrb r3, [r3, #0]
|
|
8010d3c: 009b lsls r3, r3, #2
|
|
8010d3e: 441a add r2, r3
|
|
8010d40: 8a7b ldrh r3, [r7, #18]
|
|
8010d42: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8010d46: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8010d4a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8010d4e: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8010d52: b29b uxth r3, r3
|
|
8010d54: 8013 strh r3, [r2, #0]
|
|
}
|
|
|
|
return HAL_OK;
|
|
8010d56: 2300 movs r3, #0
|
|
}
|
|
8010d58: 4618 mov r0, r3
|
|
8010d5a: 371c adds r7, #28
|
|
8010d5c: 46bd mov sp, r7
|
|
8010d5e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010d62: 4770 bx lr
|
|
|
|
08010d64 <USB_SetDevAddress>:
|
|
* @param address new device address to be assigned
|
|
* This parameter can be a value from 0 to 255
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
|
|
{
|
|
8010d64: b480 push {r7}
|
|
8010d66: b083 sub sp, #12
|
|
8010d68: af00 add r7, sp, #0
|
|
8010d6a: 6078 str r0, [r7, #4]
|
|
8010d6c: 460b mov r3, r1
|
|
8010d6e: 70fb strb r3, [r7, #3]
|
|
if (address == 0U)
|
|
8010d70: 78fb ldrb r3, [r7, #3]
|
|
8010d72: 2b00 cmp r3, #0
|
|
8010d74: d103 bne.n 8010d7e <USB_SetDevAddress+0x1a>
|
|
{
|
|
/* set device address and enable function */
|
|
USBx->DADDR = (uint16_t)USB_DADDR_EF;
|
|
8010d76: 687b ldr r3, [r7, #4]
|
|
8010d78: 2280 movs r2, #128 @ 0x80
|
|
8010d7a: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
|
|
}
|
|
|
|
return HAL_OK;
|
|
8010d7e: 2300 movs r3, #0
|
|
}
|
|
8010d80: 4618 mov r0, r3
|
|
8010d82: 370c adds r7, #12
|
|
8010d84: 46bd mov sp, r7
|
|
8010d86: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010d8a: 4770 bx lr
|
|
|
|
08010d8c <USB_DevConnect>:
|
|
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
|
|
{
|
|
8010d8c: b480 push {r7}
|
|
8010d8e: b083 sub sp, #12
|
|
8010d90: af00 add r7, sp, #0
|
|
8010d92: 6078 str r0, [r7, #4]
|
|
/* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
|
|
USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
|
|
8010d94: 687b ldr r3, [r7, #4]
|
|
8010d96: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
8010d9a: b29b uxth r3, r3
|
|
8010d9c: ea6f 4343 mvn.w r3, r3, lsl #17
|
|
8010da0: ea6f 4353 mvn.w r3, r3, lsr #17
|
|
8010da4: b29a uxth r2, r3
|
|
8010da6: 687b ldr r3, [r7, #4]
|
|
8010da8: f8a3 2058 strh.w r2, [r3, #88] @ 0x58
|
|
|
|
return HAL_OK;
|
|
8010dac: 2300 movs r3, #0
|
|
}
|
|
8010dae: 4618 mov r0, r3
|
|
8010db0: 370c adds r7, #12
|
|
8010db2: 46bd mov sp, r7
|
|
8010db4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010db8: 4770 bx lr
|
|
|
|
08010dba <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
|
|
{
|
|
8010dba: b480 push {r7}
|
|
8010dbc: b085 sub sp, #20
|
|
8010dbe: af00 add r7, sp, #0
|
|
8010dc0: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->ISTR;
|
|
8010dc2: 687b ldr r3, [r7, #4]
|
|
8010dc4: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
|
|
8010dc8: b29b uxth r3, r3
|
|
8010dca: 60fb str r3, [r7, #12]
|
|
return tmpreg;
|
|
8010dcc: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8010dce: 4618 mov r0, r3
|
|
8010dd0: 3714 adds r7, #20
|
|
8010dd2: 46bd mov sp, r7
|
|
8010dd4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010dd8: 4770 bx lr
|
|
|
|
08010dda <USB_WritePMA>:
|
|
* @param wPMABufAddr address into PMA.
|
|
* @param wNBytes no. of bytes to be copied.
|
|
* @retval None
|
|
*/
|
|
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
|
{
|
|
8010dda: b480 push {r7}
|
|
8010ddc: b08b sub sp, #44 @ 0x2c
|
|
8010dde: af00 add r7, sp, #0
|
|
8010de0: 60f8 str r0, [r7, #12]
|
|
8010de2: 60b9 str r1, [r7, #8]
|
|
8010de4: 4611 mov r1, r2
|
|
8010de6: 461a mov r2, r3
|
|
8010de8: 460b mov r3, r1
|
|
8010dea: 80fb strh r3, [r7, #6]
|
|
8010dec: 4613 mov r3, r2
|
|
8010dee: 80bb strh r3, [r7, #4]
|
|
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
|
|
8010df0: 88bb ldrh r3, [r7, #4]
|
|
8010df2: 3301 adds r3, #1
|
|
8010df4: 085b lsrs r3, r3, #1
|
|
8010df6: 61bb str r3, [r7, #24]
|
|
uint32_t BaseAddr = (uint32_t)USBx;
|
|
8010df8: 68fb ldr r3, [r7, #12]
|
|
8010dfa: 617b str r3, [r7, #20]
|
|
uint32_t count;
|
|
uint16_t WrVal;
|
|
__IO uint16_t *pdwVal;
|
|
uint8_t *pBuf = pbUsrBuf;
|
|
8010dfc: 68bb ldr r3, [r7, #8]
|
|
8010dfe: 61fb str r3, [r7, #28]
|
|
|
|
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
|
|
8010e00: 88fa ldrh r2, [r7, #6]
|
|
8010e02: 697b ldr r3, [r7, #20]
|
|
8010e04: 4413 add r3, r2
|
|
8010e06: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8010e0a: 623b str r3, [r7, #32]
|
|
|
|
for (count = n; count != 0U; count--)
|
|
8010e0c: 69bb ldr r3, [r7, #24]
|
|
8010e0e: 627b str r3, [r7, #36] @ 0x24
|
|
8010e10: e01c b.n 8010e4c <USB_WritePMA+0x72>
|
|
{
|
|
WrVal = pBuf[0];
|
|
8010e12: 69fb ldr r3, [r7, #28]
|
|
8010e14: 781b ldrb r3, [r3, #0]
|
|
8010e16: 827b strh r3, [r7, #18]
|
|
WrVal |= (uint16_t)pBuf[1] << 8;
|
|
8010e18: 69fb ldr r3, [r7, #28]
|
|
8010e1a: 3301 adds r3, #1
|
|
8010e1c: 781b ldrb r3, [r3, #0]
|
|
8010e1e: b21b sxth r3, r3
|
|
8010e20: 021b lsls r3, r3, #8
|
|
8010e22: b21a sxth r2, r3
|
|
8010e24: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
8010e28: 4313 orrs r3, r2
|
|
8010e2a: b21b sxth r3, r3
|
|
8010e2c: 827b strh r3, [r7, #18]
|
|
*pdwVal = (WrVal & 0xFFFFU);
|
|
8010e2e: 6a3b ldr r3, [r7, #32]
|
|
8010e30: 8a7a ldrh r2, [r7, #18]
|
|
8010e32: 801a strh r2, [r3, #0]
|
|
pdwVal++;
|
|
8010e34: 6a3b ldr r3, [r7, #32]
|
|
8010e36: 3302 adds r3, #2
|
|
8010e38: 623b str r3, [r7, #32]
|
|
|
|
#if PMA_ACCESS > 1U
|
|
pdwVal++;
|
|
#endif /* PMA_ACCESS */
|
|
|
|
pBuf++;
|
|
8010e3a: 69fb ldr r3, [r7, #28]
|
|
8010e3c: 3301 adds r3, #1
|
|
8010e3e: 61fb str r3, [r7, #28]
|
|
pBuf++;
|
|
8010e40: 69fb ldr r3, [r7, #28]
|
|
8010e42: 3301 adds r3, #1
|
|
8010e44: 61fb str r3, [r7, #28]
|
|
for (count = n; count != 0U; count--)
|
|
8010e46: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8010e48: 3b01 subs r3, #1
|
|
8010e4a: 627b str r3, [r7, #36] @ 0x24
|
|
8010e4c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8010e4e: 2b00 cmp r3, #0
|
|
8010e50: d1df bne.n 8010e12 <USB_WritePMA+0x38>
|
|
}
|
|
}
|
|
8010e52: bf00 nop
|
|
8010e54: bf00 nop
|
|
8010e56: 372c adds r7, #44 @ 0x2c
|
|
8010e58: 46bd mov sp, r7
|
|
8010e5a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010e5e: 4770 bx lr
|
|
|
|
08010e60 <USB_ReadPMA>:
|
|
* @param wPMABufAddr address into PMA.
|
|
* @param wNBytes no. of bytes to be copied.
|
|
* @retval None
|
|
*/
|
|
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
|
{
|
|
8010e60: b480 push {r7}
|
|
8010e62: b08b sub sp, #44 @ 0x2c
|
|
8010e64: af00 add r7, sp, #0
|
|
8010e66: 60f8 str r0, [r7, #12]
|
|
8010e68: 60b9 str r1, [r7, #8]
|
|
8010e6a: 4611 mov r1, r2
|
|
8010e6c: 461a mov r2, r3
|
|
8010e6e: 460b mov r3, r1
|
|
8010e70: 80fb strh r3, [r7, #6]
|
|
8010e72: 4613 mov r3, r2
|
|
8010e74: 80bb strh r3, [r7, #4]
|
|
uint32_t n = (uint32_t)wNBytes >> 1;
|
|
8010e76: 88bb ldrh r3, [r7, #4]
|
|
8010e78: 085b lsrs r3, r3, #1
|
|
8010e7a: b29b uxth r3, r3
|
|
8010e7c: 61bb str r3, [r7, #24]
|
|
uint32_t BaseAddr = (uint32_t)USBx;
|
|
8010e7e: 68fb ldr r3, [r7, #12]
|
|
8010e80: 617b str r3, [r7, #20]
|
|
uint32_t count;
|
|
uint32_t RdVal;
|
|
__IO uint16_t *pdwVal;
|
|
uint8_t *pBuf = pbUsrBuf;
|
|
8010e82: 68bb ldr r3, [r7, #8]
|
|
8010e84: 61fb str r3, [r7, #28]
|
|
|
|
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
|
|
8010e86: 88fa ldrh r2, [r7, #6]
|
|
8010e88: 697b ldr r3, [r7, #20]
|
|
8010e8a: 4413 add r3, r2
|
|
8010e8c: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8010e90: 623b str r3, [r7, #32]
|
|
|
|
for (count = n; count != 0U; count--)
|
|
8010e92: 69bb ldr r3, [r7, #24]
|
|
8010e94: 627b str r3, [r7, #36] @ 0x24
|
|
8010e96: e018 b.n 8010eca <USB_ReadPMA+0x6a>
|
|
{
|
|
RdVal = *(__IO uint16_t *)pdwVal;
|
|
8010e98: 6a3b ldr r3, [r7, #32]
|
|
8010e9a: 881b ldrh r3, [r3, #0]
|
|
8010e9c: b29b uxth r3, r3
|
|
8010e9e: 613b str r3, [r7, #16]
|
|
pdwVal++;
|
|
8010ea0: 6a3b ldr r3, [r7, #32]
|
|
8010ea2: 3302 adds r3, #2
|
|
8010ea4: 623b str r3, [r7, #32]
|
|
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
|
|
8010ea6: 693b ldr r3, [r7, #16]
|
|
8010ea8: b2da uxtb r2, r3
|
|
8010eaa: 69fb ldr r3, [r7, #28]
|
|
8010eac: 701a strb r2, [r3, #0]
|
|
pBuf++;
|
|
8010eae: 69fb ldr r3, [r7, #28]
|
|
8010eb0: 3301 adds r3, #1
|
|
8010eb2: 61fb str r3, [r7, #28]
|
|
*pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
|
|
8010eb4: 693b ldr r3, [r7, #16]
|
|
8010eb6: 0a1b lsrs r3, r3, #8
|
|
8010eb8: b2da uxtb r2, r3
|
|
8010eba: 69fb ldr r3, [r7, #28]
|
|
8010ebc: 701a strb r2, [r3, #0]
|
|
pBuf++;
|
|
8010ebe: 69fb ldr r3, [r7, #28]
|
|
8010ec0: 3301 adds r3, #1
|
|
8010ec2: 61fb str r3, [r7, #28]
|
|
for (count = n; count != 0U; count--)
|
|
8010ec4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8010ec6: 3b01 subs r3, #1
|
|
8010ec8: 627b str r3, [r7, #36] @ 0x24
|
|
8010eca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8010ecc: 2b00 cmp r3, #0
|
|
8010ece: d1e3 bne.n 8010e98 <USB_ReadPMA+0x38>
|
|
#if PMA_ACCESS > 1U
|
|
pdwVal++;
|
|
#endif /* PMA_ACCESS */
|
|
}
|
|
|
|
if ((wNBytes % 2U) != 0U)
|
|
8010ed0: 88bb ldrh r3, [r7, #4]
|
|
8010ed2: f003 0301 and.w r3, r3, #1
|
|
8010ed6: b29b uxth r3, r3
|
|
8010ed8: 2b00 cmp r3, #0
|
|
8010eda: d007 beq.n 8010eec <USB_ReadPMA+0x8c>
|
|
{
|
|
RdVal = *pdwVal;
|
|
8010edc: 6a3b ldr r3, [r7, #32]
|
|
8010ede: 881b ldrh r3, [r3, #0]
|
|
8010ee0: b29b uxth r3, r3
|
|
8010ee2: 613b str r3, [r7, #16]
|
|
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
|
|
8010ee4: 693b ldr r3, [r7, #16]
|
|
8010ee6: b2da uxtb r2, r3
|
|
8010ee8: 69fb ldr r3, [r7, #28]
|
|
8010eea: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
8010eec: bf00 nop
|
|
8010eee: 372c adds r7, #44 @ 0x2c
|
|
8010ef0: 46bd mov sp, r7
|
|
8010ef2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010ef6: 4770 bx lr
|
|
|
|
08010ef8 <USBD_CDC_Init>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8010ef8: b580 push {r7, lr}
|
|
8010efa: b084 sub sp, #16
|
|
8010efc: af00 add r7, sp, #0
|
|
8010efe: 6078 str r0, [r7, #4]
|
|
8010f00: 460b mov r3, r1
|
|
8010f02: 70fb strb r3, [r7, #3]
|
|
UNUSED(cfgidx);
|
|
USBD_CDC_HandleTypeDef *hcdc;
|
|
|
|
hcdc = (USBD_CDC_HandleTypeDef *)USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
|
|
8010f04: f44f 7007 mov.w r0, #540 @ 0x21c
|
|
8010f08: f008 f9cc bl 80192a4 <USBD_static_malloc>
|
|
8010f0c: 60f8 str r0, [r7, #12]
|
|
|
|
if (hcdc == NULL)
|
|
8010f0e: 68fb ldr r3, [r7, #12]
|
|
8010f10: 2b00 cmp r3, #0
|
|
8010f12: d109 bne.n 8010f28 <USBD_CDC_Init+0x30>
|
|
{
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
8010f14: 687b ldr r3, [r7, #4]
|
|
8010f16: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8010f1a: 687b ldr r3, [r7, #4]
|
|
8010f1c: 32b0 adds r2, #176 @ 0xb0
|
|
8010f1e: 2100 movs r1, #0
|
|
8010f20: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
return (uint8_t)USBD_EMEM;
|
|
8010f24: 2302 movs r3, #2
|
|
8010f26: e0d4 b.n 80110d2 <USBD_CDC_Init+0x1da>
|
|
}
|
|
|
|
(void)USBD_memset(hcdc, 0, sizeof(USBD_CDC_HandleTypeDef));
|
|
8010f28: f44f 7207 mov.w r2, #540 @ 0x21c
|
|
8010f2c: 2100 movs r1, #0
|
|
8010f2e: 68f8 ldr r0, [r7, #12]
|
|
8010f30: f009 f9e8 bl 801a304 <memset>
|
|
|
|
pdev->pClassDataCmsit[pdev->classId] = (void *)hcdc;
|
|
8010f34: 687b ldr r3, [r7, #4]
|
|
8010f36: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8010f3a: 687b ldr r3, [r7, #4]
|
|
8010f3c: 32b0 adds r2, #176 @ 0xb0
|
|
8010f3e: 68f9 ldr r1, [r7, #12]
|
|
8010f40: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
|
|
8010f44: 687b ldr r3, [r7, #4]
|
|
8010f46: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8010f4a: 687b ldr r3, [r7, #4]
|
|
8010f4c: 32b0 adds r2, #176 @ 0xb0
|
|
8010f4e: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8010f52: 687b ldr r3, [r7, #4]
|
|
8010f54: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
|
|
CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId);
|
|
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId);
|
|
CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8010f58: 687b ldr r3, [r7, #4]
|
|
8010f5a: 7c1b ldrb r3, [r3, #16]
|
|
8010f5c: 2b00 cmp r3, #0
|
|
8010f5e: d138 bne.n 8010fd2 <USBD_CDC_Init+0xda>
|
|
{
|
|
/* Open EP IN */
|
|
(void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK,
|
|
8010f60: 4b5e ldr r3, [pc, #376] @ (80110dc <USBD_CDC_Init+0x1e4>)
|
|
8010f62: 7819 ldrb r1, [r3, #0]
|
|
8010f64: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8010f68: 2202 movs r2, #2
|
|
8010f6a: 6878 ldr r0, [r7, #4]
|
|
8010f6c: f008 f841 bl 8018ff2 <USBD_LL_OpenEP>
|
|
CDC_DATA_HS_IN_PACKET_SIZE);
|
|
|
|
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U;
|
|
8010f70: 4b5a ldr r3, [pc, #360] @ (80110dc <USBD_CDC_Init+0x1e4>)
|
|
8010f72: 781b ldrb r3, [r3, #0]
|
|
8010f74: f003 020f and.w r2, r3, #15
|
|
8010f78: 6879 ldr r1, [r7, #4]
|
|
8010f7a: 4613 mov r3, r2
|
|
8010f7c: 009b lsls r3, r3, #2
|
|
8010f7e: 4413 add r3, r2
|
|
8010f80: 009b lsls r3, r3, #2
|
|
8010f82: 440b add r3, r1
|
|
8010f84: 3323 adds r3, #35 @ 0x23
|
|
8010f86: 2201 movs r2, #1
|
|
8010f88: 701a strb r2, [r3, #0]
|
|
|
|
/* Open EP OUT */
|
|
(void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK,
|
|
8010f8a: 4b55 ldr r3, [pc, #340] @ (80110e0 <USBD_CDC_Init+0x1e8>)
|
|
8010f8c: 7819 ldrb r1, [r3, #0]
|
|
8010f8e: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8010f92: 2202 movs r2, #2
|
|
8010f94: 6878 ldr r0, [r7, #4]
|
|
8010f96: f008 f82c bl 8018ff2 <USBD_LL_OpenEP>
|
|
CDC_DATA_HS_OUT_PACKET_SIZE);
|
|
|
|
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U;
|
|
8010f9a: 4b51 ldr r3, [pc, #324] @ (80110e0 <USBD_CDC_Init+0x1e8>)
|
|
8010f9c: 781b ldrb r3, [r3, #0]
|
|
8010f9e: f003 020f and.w r2, r3, #15
|
|
8010fa2: 6879 ldr r1, [r7, #4]
|
|
8010fa4: 4613 mov r3, r2
|
|
8010fa6: 009b lsls r3, r3, #2
|
|
8010fa8: 4413 add r3, r2
|
|
8010faa: 009b lsls r3, r3, #2
|
|
8010fac: 440b add r3, r1
|
|
8010fae: f203 1363 addw r3, r3, #355 @ 0x163
|
|
8010fb2: 2201 movs r2, #1
|
|
8010fb4: 701a strb r2, [r3, #0]
|
|
|
|
/* Set bInterval for CDC CMD Endpoint */
|
|
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_HS_BINTERVAL;
|
|
8010fb6: 4b4b ldr r3, [pc, #300] @ (80110e4 <USBD_CDC_Init+0x1ec>)
|
|
8010fb8: 781b ldrb r3, [r3, #0]
|
|
8010fba: f003 020f and.w r2, r3, #15
|
|
8010fbe: 6879 ldr r1, [r7, #4]
|
|
8010fc0: 4613 mov r3, r2
|
|
8010fc2: 009b lsls r3, r3, #2
|
|
8010fc4: 4413 add r3, r2
|
|
8010fc6: 009b lsls r3, r3, #2
|
|
8010fc8: 440b add r3, r1
|
|
8010fca: 331c adds r3, #28
|
|
8010fcc: 2210 movs r2, #16
|
|
8010fce: 601a str r2, [r3, #0]
|
|
8010fd0: e035 b.n 801103e <USBD_CDC_Init+0x146>
|
|
}
|
|
else
|
|
{
|
|
/* Open EP IN */
|
|
(void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK,
|
|
8010fd2: 4b42 ldr r3, [pc, #264] @ (80110dc <USBD_CDC_Init+0x1e4>)
|
|
8010fd4: 7819 ldrb r1, [r3, #0]
|
|
8010fd6: 2340 movs r3, #64 @ 0x40
|
|
8010fd8: 2202 movs r2, #2
|
|
8010fda: 6878 ldr r0, [r7, #4]
|
|
8010fdc: f008 f809 bl 8018ff2 <USBD_LL_OpenEP>
|
|
CDC_DATA_FS_IN_PACKET_SIZE);
|
|
|
|
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U;
|
|
8010fe0: 4b3e ldr r3, [pc, #248] @ (80110dc <USBD_CDC_Init+0x1e4>)
|
|
8010fe2: 781b ldrb r3, [r3, #0]
|
|
8010fe4: f003 020f and.w r2, r3, #15
|
|
8010fe8: 6879 ldr r1, [r7, #4]
|
|
8010fea: 4613 mov r3, r2
|
|
8010fec: 009b lsls r3, r3, #2
|
|
8010fee: 4413 add r3, r2
|
|
8010ff0: 009b lsls r3, r3, #2
|
|
8010ff2: 440b add r3, r1
|
|
8010ff4: 3323 adds r3, #35 @ 0x23
|
|
8010ff6: 2201 movs r2, #1
|
|
8010ff8: 701a strb r2, [r3, #0]
|
|
|
|
/* Open EP OUT */
|
|
(void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK,
|
|
8010ffa: 4b39 ldr r3, [pc, #228] @ (80110e0 <USBD_CDC_Init+0x1e8>)
|
|
8010ffc: 7819 ldrb r1, [r3, #0]
|
|
8010ffe: 2340 movs r3, #64 @ 0x40
|
|
8011000: 2202 movs r2, #2
|
|
8011002: 6878 ldr r0, [r7, #4]
|
|
8011004: f007 fff5 bl 8018ff2 <USBD_LL_OpenEP>
|
|
CDC_DATA_FS_OUT_PACKET_SIZE);
|
|
|
|
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U;
|
|
8011008: 4b35 ldr r3, [pc, #212] @ (80110e0 <USBD_CDC_Init+0x1e8>)
|
|
801100a: 781b ldrb r3, [r3, #0]
|
|
801100c: f003 020f and.w r2, r3, #15
|
|
8011010: 6879 ldr r1, [r7, #4]
|
|
8011012: 4613 mov r3, r2
|
|
8011014: 009b lsls r3, r3, #2
|
|
8011016: 4413 add r3, r2
|
|
8011018: 009b lsls r3, r3, #2
|
|
801101a: 440b add r3, r1
|
|
801101c: f203 1363 addw r3, r3, #355 @ 0x163
|
|
8011020: 2201 movs r2, #1
|
|
8011022: 701a strb r2, [r3, #0]
|
|
|
|
/* Set bInterval for CMD Endpoint */
|
|
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_FS_BINTERVAL;
|
|
8011024: 4b2f ldr r3, [pc, #188] @ (80110e4 <USBD_CDC_Init+0x1ec>)
|
|
8011026: 781b ldrb r3, [r3, #0]
|
|
8011028: f003 020f and.w r2, r3, #15
|
|
801102c: 6879 ldr r1, [r7, #4]
|
|
801102e: 4613 mov r3, r2
|
|
8011030: 009b lsls r3, r3, #2
|
|
8011032: 4413 add r3, r2
|
|
8011034: 009b lsls r3, r3, #2
|
|
8011036: 440b add r3, r1
|
|
8011038: 331c adds r3, #28
|
|
801103a: 2210 movs r2, #16
|
|
801103c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Open Command IN EP */
|
|
(void)USBD_LL_OpenEP(pdev, CDCCmdEpAdd, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
|
|
801103e: 4b29 ldr r3, [pc, #164] @ (80110e4 <USBD_CDC_Init+0x1ec>)
|
|
8011040: 7819 ldrb r1, [r3, #0]
|
|
8011042: 2308 movs r3, #8
|
|
8011044: 2203 movs r2, #3
|
|
8011046: 6878 ldr r0, [r7, #4]
|
|
8011048: f007 ffd3 bl 8018ff2 <USBD_LL_OpenEP>
|
|
pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 1U;
|
|
801104c: 4b25 ldr r3, [pc, #148] @ (80110e4 <USBD_CDC_Init+0x1ec>)
|
|
801104e: 781b ldrb r3, [r3, #0]
|
|
8011050: f003 020f and.w r2, r3, #15
|
|
8011054: 6879 ldr r1, [r7, #4]
|
|
8011056: 4613 mov r3, r2
|
|
8011058: 009b lsls r3, r3, #2
|
|
801105a: 4413 add r3, r2
|
|
801105c: 009b lsls r3, r3, #2
|
|
801105e: 440b add r3, r1
|
|
8011060: 3323 adds r3, #35 @ 0x23
|
|
8011062: 2201 movs r2, #1
|
|
8011064: 701a strb r2, [r3, #0]
|
|
|
|
hcdc->RxBuffer = NULL;
|
|
8011066: 68fb ldr r3, [r7, #12]
|
|
8011068: 2200 movs r2, #0
|
|
801106a: f8c3 2204 str.w r2, [r3, #516] @ 0x204
|
|
|
|
/* Init physical Interface components */
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Init();
|
|
801106e: 687b ldr r3, [r7, #4]
|
|
8011070: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8011074: 687a ldr r2, [r7, #4]
|
|
8011076: 33b0 adds r3, #176 @ 0xb0
|
|
8011078: 009b lsls r3, r3, #2
|
|
801107a: 4413 add r3, r2
|
|
801107c: 685b ldr r3, [r3, #4]
|
|
801107e: 681b ldr r3, [r3, #0]
|
|
8011080: 4798 blx r3
|
|
|
|
/* Init Xfer states */
|
|
hcdc->TxState = 0U;
|
|
8011082: 68fb ldr r3, [r7, #12]
|
|
8011084: 2200 movs r2, #0
|
|
8011086: f8c3 2214 str.w r2, [r3, #532] @ 0x214
|
|
hcdc->RxState = 0U;
|
|
801108a: 68fb ldr r3, [r7, #12]
|
|
801108c: 2200 movs r2, #0
|
|
801108e: f8c3 2218 str.w r2, [r3, #536] @ 0x218
|
|
|
|
if (hcdc->RxBuffer == NULL)
|
|
8011092: 68fb ldr r3, [r7, #12]
|
|
8011094: f8d3 3204 ldr.w r3, [r3, #516] @ 0x204
|
|
8011098: 2b00 cmp r3, #0
|
|
801109a: d101 bne.n 80110a0 <USBD_CDC_Init+0x1a8>
|
|
{
|
|
return (uint8_t)USBD_EMEM;
|
|
801109c: 2302 movs r3, #2
|
|
801109e: e018 b.n 80110d2 <USBD_CDC_Init+0x1da>
|
|
}
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80110a0: 687b ldr r3, [r7, #4]
|
|
80110a2: 7c1b ldrb r3, [r3, #16]
|
|
80110a4: 2b00 cmp r3, #0
|
|
80110a6: d10a bne.n 80110be <USBD_CDC_Init+0x1c6>
|
|
{
|
|
/* Prepare Out endpoint to receive next packet */
|
|
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
|
|
80110a8: 4b0d ldr r3, [pc, #52] @ (80110e0 <USBD_CDC_Init+0x1e8>)
|
|
80110aa: 7819 ldrb r1, [r3, #0]
|
|
80110ac: 68fb ldr r3, [r7, #12]
|
|
80110ae: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
80110b2: f44f 7300 mov.w r3, #512 @ 0x200
|
|
80110b6: 6878 ldr r0, [r7, #4]
|
|
80110b8: f008 f88a bl 80191d0 <USBD_LL_PrepareReceive>
|
|
80110bc: e008 b.n 80110d0 <USBD_CDC_Init+0x1d8>
|
|
CDC_DATA_HS_OUT_PACKET_SIZE);
|
|
}
|
|
else
|
|
{
|
|
/* Prepare Out endpoint to receive next packet */
|
|
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
|
|
80110be: 4b08 ldr r3, [pc, #32] @ (80110e0 <USBD_CDC_Init+0x1e8>)
|
|
80110c0: 7819 ldrb r1, [r3, #0]
|
|
80110c2: 68fb ldr r3, [r7, #12]
|
|
80110c4: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
80110c8: 2340 movs r3, #64 @ 0x40
|
|
80110ca: 6878 ldr r0, [r7, #4]
|
|
80110cc: f008 f880 bl 80191d0 <USBD_LL_PrepareReceive>
|
|
CDC_DATA_FS_OUT_PACKET_SIZE);
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80110d0: 2300 movs r3, #0
|
|
}
|
|
80110d2: 4618 mov r0, r3
|
|
80110d4: 3710 adds r7, #16
|
|
80110d6: 46bd mov sp, r7
|
|
80110d8: bd80 pop {r7, pc}
|
|
80110da: bf00 nop
|
|
80110dc: 2000009f .word 0x2000009f
|
|
80110e0: 200000a0 .word 0x200000a0
|
|
80110e4: 200000a1 .word 0x200000a1
|
|
|
|
080110e8 <USBD_CDC_DeInit>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: Configuration index
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80110e8: b580 push {r7, lr}
|
|
80110ea: b082 sub sp, #8
|
|
80110ec: af00 add r7, sp, #0
|
|
80110ee: 6078 str r0, [r7, #4]
|
|
80110f0: 460b mov r3, r1
|
|
80110f2: 70fb strb r3, [r7, #3]
|
|
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId);
|
|
CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Close EP IN */
|
|
(void)USBD_LL_CloseEP(pdev, CDCInEpAdd);
|
|
80110f4: 4b3a ldr r3, [pc, #232] @ (80111e0 <USBD_CDC_DeInit+0xf8>)
|
|
80110f6: 781b ldrb r3, [r3, #0]
|
|
80110f8: 4619 mov r1, r3
|
|
80110fa: 6878 ldr r0, [r7, #4]
|
|
80110fc: f007 ff9f bl 801903e <USBD_LL_CloseEP>
|
|
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 0U;
|
|
8011100: 4b37 ldr r3, [pc, #220] @ (80111e0 <USBD_CDC_DeInit+0xf8>)
|
|
8011102: 781b ldrb r3, [r3, #0]
|
|
8011104: f003 020f and.w r2, r3, #15
|
|
8011108: 6879 ldr r1, [r7, #4]
|
|
801110a: 4613 mov r3, r2
|
|
801110c: 009b lsls r3, r3, #2
|
|
801110e: 4413 add r3, r2
|
|
8011110: 009b lsls r3, r3, #2
|
|
8011112: 440b add r3, r1
|
|
8011114: 3323 adds r3, #35 @ 0x23
|
|
8011116: 2200 movs r2, #0
|
|
8011118: 701a strb r2, [r3, #0]
|
|
|
|
/* Close EP OUT */
|
|
(void)USBD_LL_CloseEP(pdev, CDCOutEpAdd);
|
|
801111a: 4b32 ldr r3, [pc, #200] @ (80111e4 <USBD_CDC_DeInit+0xfc>)
|
|
801111c: 781b ldrb r3, [r3, #0]
|
|
801111e: 4619 mov r1, r3
|
|
8011120: 6878 ldr r0, [r7, #4]
|
|
8011122: f007 ff8c bl 801903e <USBD_LL_CloseEP>
|
|
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 0U;
|
|
8011126: 4b2f ldr r3, [pc, #188] @ (80111e4 <USBD_CDC_DeInit+0xfc>)
|
|
8011128: 781b ldrb r3, [r3, #0]
|
|
801112a: f003 020f and.w r2, r3, #15
|
|
801112e: 6879 ldr r1, [r7, #4]
|
|
8011130: 4613 mov r3, r2
|
|
8011132: 009b lsls r3, r3, #2
|
|
8011134: 4413 add r3, r2
|
|
8011136: 009b lsls r3, r3, #2
|
|
8011138: 440b add r3, r1
|
|
801113a: f203 1363 addw r3, r3, #355 @ 0x163
|
|
801113e: 2200 movs r2, #0
|
|
8011140: 701a strb r2, [r3, #0]
|
|
|
|
/* Close Command IN EP */
|
|
(void)USBD_LL_CloseEP(pdev, CDCCmdEpAdd);
|
|
8011142: 4b29 ldr r3, [pc, #164] @ (80111e8 <USBD_CDC_DeInit+0x100>)
|
|
8011144: 781b ldrb r3, [r3, #0]
|
|
8011146: 4619 mov r1, r3
|
|
8011148: 6878 ldr r0, [r7, #4]
|
|
801114a: f007 ff78 bl 801903e <USBD_LL_CloseEP>
|
|
pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 0U;
|
|
801114e: 4b26 ldr r3, [pc, #152] @ (80111e8 <USBD_CDC_DeInit+0x100>)
|
|
8011150: 781b ldrb r3, [r3, #0]
|
|
8011152: f003 020f and.w r2, r3, #15
|
|
8011156: 6879 ldr r1, [r7, #4]
|
|
8011158: 4613 mov r3, r2
|
|
801115a: 009b lsls r3, r3, #2
|
|
801115c: 4413 add r3, r2
|
|
801115e: 009b lsls r3, r3, #2
|
|
8011160: 440b add r3, r1
|
|
8011162: 3323 adds r3, #35 @ 0x23
|
|
8011164: 2200 movs r2, #0
|
|
8011166: 701a strb r2, [r3, #0]
|
|
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = 0U;
|
|
8011168: 4b1f ldr r3, [pc, #124] @ (80111e8 <USBD_CDC_DeInit+0x100>)
|
|
801116a: 781b ldrb r3, [r3, #0]
|
|
801116c: f003 020f and.w r2, r3, #15
|
|
8011170: 6879 ldr r1, [r7, #4]
|
|
8011172: 4613 mov r3, r2
|
|
8011174: 009b lsls r3, r3, #2
|
|
8011176: 4413 add r3, r2
|
|
8011178: 009b lsls r3, r3, #2
|
|
801117a: 440b add r3, r1
|
|
801117c: 331c adds r3, #28
|
|
801117e: 2200 movs r2, #0
|
|
8011180: 601a str r2, [r3, #0]
|
|
|
|
/* DeInit physical Interface components */
|
|
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
|
|
8011182: 687b ldr r3, [r7, #4]
|
|
8011184: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8011188: 687b ldr r3, [r7, #4]
|
|
801118a: 32b0 adds r2, #176 @ 0xb0
|
|
801118c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011190: 2b00 cmp r3, #0
|
|
8011192: d01f beq.n 80111d4 <USBD_CDC_DeInit+0xec>
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->DeInit();
|
|
8011194: 687b ldr r3, [r7, #4]
|
|
8011196: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
801119a: 687a ldr r2, [r7, #4]
|
|
801119c: 33b0 adds r3, #176 @ 0xb0
|
|
801119e: 009b lsls r3, r3, #2
|
|
80111a0: 4413 add r3, r2
|
|
80111a2: 685b ldr r3, [r3, #4]
|
|
80111a4: 685b ldr r3, [r3, #4]
|
|
80111a6: 4798 blx r3
|
|
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
|
|
80111a8: 687b ldr r3, [r7, #4]
|
|
80111aa: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80111ae: 687b ldr r3, [r7, #4]
|
|
80111b0: 32b0 adds r2, #176 @ 0xb0
|
|
80111b2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80111b6: 4618 mov r0, r3
|
|
80111b8: f008 f882 bl 80192c0 <USBD_static_free>
|
|
pdev->pClassDataCmsit[pdev->classId] = NULL;
|
|
80111bc: 687b ldr r3, [r7, #4]
|
|
80111be: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80111c2: 687b ldr r3, [r7, #4]
|
|
80111c4: 32b0 adds r2, #176 @ 0xb0
|
|
80111c6: 2100 movs r1, #0
|
|
80111c8: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
pdev->pClassData = NULL;
|
|
80111cc: 687b ldr r3, [r7, #4]
|
|
80111ce: 2200 movs r2, #0
|
|
80111d0: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
80111d4: 2300 movs r3, #0
|
|
}
|
|
80111d6: 4618 mov r0, r3
|
|
80111d8: 3708 adds r7, #8
|
|
80111da: 46bd mov sp, r7
|
|
80111dc: bd80 pop {r7, pc}
|
|
80111de: bf00 nop
|
|
80111e0: 2000009f .word 0x2000009f
|
|
80111e4: 200000a0 .word 0x200000a0
|
|
80111e8: 200000a1 .word 0x200000a1
|
|
|
|
080111ec <USBD_CDC_Setup>:
|
|
* @param req: usb requests
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
|
|
USBD_SetupReqTypedef *req)
|
|
{
|
|
80111ec: b580 push {r7, lr}
|
|
80111ee: b086 sub sp, #24
|
|
80111f0: af00 add r7, sp, #0
|
|
80111f2: 6078 str r0, [r7, #4]
|
|
80111f4: 6039 str r1, [r7, #0]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
80111f6: 687b ldr r3, [r7, #4]
|
|
80111f8: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80111fc: 687b ldr r3, [r7, #4]
|
|
80111fe: 32b0 adds r2, #176 @ 0xb0
|
|
8011200: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011204: 613b str r3, [r7, #16]
|
|
uint16_t len;
|
|
uint8_t ifalt = 0U;
|
|
8011206: 2300 movs r3, #0
|
|
8011208: 737b strb r3, [r7, #13]
|
|
uint16_t status_info = 0U;
|
|
801120a: 2300 movs r3, #0
|
|
801120c: 817b strh r3, [r7, #10]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
801120e: 2300 movs r3, #0
|
|
8011210: 75fb strb r3, [r7, #23]
|
|
|
|
if (hcdc == NULL)
|
|
8011212: 693b ldr r3, [r7, #16]
|
|
8011214: 2b00 cmp r3, #0
|
|
8011216: d101 bne.n 801121c <USBD_CDC_Setup+0x30>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8011218: 2303 movs r3, #3
|
|
801121a: e0bf b.n 801139c <USBD_CDC_Setup+0x1b0>
|
|
}
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
801121c: 683b ldr r3, [r7, #0]
|
|
801121e: 781b ldrb r3, [r3, #0]
|
|
8011220: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8011224: 2b00 cmp r3, #0
|
|
8011226: d050 beq.n 80112ca <USBD_CDC_Setup+0xde>
|
|
8011228: 2b20 cmp r3, #32
|
|
801122a: f040 80af bne.w 801138c <USBD_CDC_Setup+0x1a0>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
if (req->wLength != 0U)
|
|
801122e: 683b ldr r3, [r7, #0]
|
|
8011230: 88db ldrh r3, [r3, #6]
|
|
8011232: 2b00 cmp r3, #0
|
|
8011234: d03a beq.n 80112ac <USBD_CDC_Setup+0xc0>
|
|
{
|
|
if ((req->bmRequest & 0x80U) != 0U)
|
|
8011236: 683b ldr r3, [r7, #0]
|
|
8011238: 781b ldrb r3, [r3, #0]
|
|
801123a: b25b sxtb r3, r3
|
|
801123c: 2b00 cmp r3, #0
|
|
801123e: da1b bge.n 8011278 <USBD_CDC_Setup+0x8c>
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
|
|
8011240: 687b ldr r3, [r7, #4]
|
|
8011242: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8011246: 687a ldr r2, [r7, #4]
|
|
8011248: 33b0 adds r3, #176 @ 0xb0
|
|
801124a: 009b lsls r3, r3, #2
|
|
801124c: 4413 add r3, r2
|
|
801124e: 685b ldr r3, [r3, #4]
|
|
8011250: 689b ldr r3, [r3, #8]
|
|
8011252: 683a ldr r2, [r7, #0]
|
|
8011254: 7850 ldrb r0, [r2, #1]
|
|
(uint8_t *)hcdc->data,
|
|
8011256: 6939 ldr r1, [r7, #16]
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
|
|
8011258: 683a ldr r2, [r7, #0]
|
|
801125a: 88d2 ldrh r2, [r2, #6]
|
|
801125c: 4798 blx r3
|
|
req->wLength);
|
|
|
|
len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength);
|
|
801125e: 683b ldr r3, [r7, #0]
|
|
8011260: 88db ldrh r3, [r3, #6]
|
|
8011262: 2b07 cmp r3, #7
|
|
8011264: bf28 it cs
|
|
8011266: 2307 movcs r3, #7
|
|
8011268: 81fb strh r3, [r7, #14]
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len);
|
|
801126a: 693b ldr r3, [r7, #16]
|
|
801126c: 89fa ldrh r2, [r7, #14]
|
|
801126e: 4619 mov r1, r3
|
|
8011270: 6878 ldr r0, [r7, #4]
|
|
8011272: f001 fd41 bl 8012cf8 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
|
|
(uint8_t *)req, 0U);
|
|
}
|
|
break;
|
|
8011276: e090 b.n 801139a <USBD_CDC_Setup+0x1ae>
|
|
hcdc->CmdOpCode = req->bRequest;
|
|
8011278: 683b ldr r3, [r7, #0]
|
|
801127a: 785a ldrb r2, [r3, #1]
|
|
801127c: 693b ldr r3, [r7, #16]
|
|
801127e: f883 2200 strb.w r2, [r3, #512] @ 0x200
|
|
hcdc->CmdLength = (uint8_t)MIN(req->wLength, USB_MAX_EP0_SIZE);
|
|
8011282: 683b ldr r3, [r7, #0]
|
|
8011284: 88db ldrh r3, [r3, #6]
|
|
8011286: 2b3f cmp r3, #63 @ 0x3f
|
|
8011288: d803 bhi.n 8011292 <USBD_CDC_Setup+0xa6>
|
|
801128a: 683b ldr r3, [r7, #0]
|
|
801128c: 88db ldrh r3, [r3, #6]
|
|
801128e: b2da uxtb r2, r3
|
|
8011290: e000 b.n 8011294 <USBD_CDC_Setup+0xa8>
|
|
8011292: 2240 movs r2, #64 @ 0x40
|
|
8011294: 693b ldr r3, [r7, #16]
|
|
8011296: f883 2201 strb.w r2, [r3, #513] @ 0x201
|
|
(void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, hcdc->CmdLength);
|
|
801129a: 6939 ldr r1, [r7, #16]
|
|
801129c: 693b ldr r3, [r7, #16]
|
|
801129e: f893 3201 ldrb.w r3, [r3, #513] @ 0x201
|
|
80112a2: 461a mov r2, r3
|
|
80112a4: 6878 ldr r0, [r7, #4]
|
|
80112a6: f001 fd56 bl 8012d56 <USBD_CtlPrepareRx>
|
|
break;
|
|
80112aa: e076 b.n 801139a <USBD_CDC_Setup+0x1ae>
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
|
|
80112ac: 687b ldr r3, [r7, #4]
|
|
80112ae: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
80112b2: 687a ldr r2, [r7, #4]
|
|
80112b4: 33b0 adds r3, #176 @ 0xb0
|
|
80112b6: 009b lsls r3, r3, #2
|
|
80112b8: 4413 add r3, r2
|
|
80112ba: 685b ldr r3, [r3, #4]
|
|
80112bc: 689b ldr r3, [r3, #8]
|
|
80112be: 683a ldr r2, [r7, #0]
|
|
80112c0: 7850 ldrb r0, [r2, #1]
|
|
80112c2: 2200 movs r2, #0
|
|
80112c4: 6839 ldr r1, [r7, #0]
|
|
80112c6: 4798 blx r3
|
|
break;
|
|
80112c8: e067 b.n 801139a <USBD_CDC_Setup+0x1ae>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
80112ca: 683b ldr r3, [r7, #0]
|
|
80112cc: 785b ldrb r3, [r3, #1]
|
|
80112ce: 2b0b cmp r3, #11
|
|
80112d0: d851 bhi.n 8011376 <USBD_CDC_Setup+0x18a>
|
|
80112d2: a201 add r2, pc, #4 @ (adr r2, 80112d8 <USBD_CDC_Setup+0xec>)
|
|
80112d4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80112d8: 08011309 .word 0x08011309
|
|
80112dc: 08011385 .word 0x08011385
|
|
80112e0: 08011377 .word 0x08011377
|
|
80112e4: 08011377 .word 0x08011377
|
|
80112e8: 08011377 .word 0x08011377
|
|
80112ec: 08011377 .word 0x08011377
|
|
80112f0: 08011377 .word 0x08011377
|
|
80112f4: 08011377 .word 0x08011377
|
|
80112f8: 08011377 .word 0x08011377
|
|
80112fc: 08011377 .word 0x08011377
|
|
8011300: 08011333 .word 0x08011333
|
|
8011304: 0801135d .word 0x0801135d
|
|
{
|
|
case USB_REQ_GET_STATUS:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8011308: 687b ldr r3, [r7, #4]
|
|
801130a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
801130e: b2db uxtb r3, r3
|
|
8011310: 2b03 cmp r3, #3
|
|
8011312: d107 bne.n 8011324 <USBD_CDC_Setup+0x138>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
|
|
8011314: f107 030a add.w r3, r7, #10
|
|
8011318: 2202 movs r2, #2
|
|
801131a: 4619 mov r1, r3
|
|
801131c: 6878 ldr r0, [r7, #4]
|
|
801131e: f001 fceb bl 8012cf8 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
8011322: e032 b.n 801138a <USBD_CDC_Setup+0x19e>
|
|
USBD_CtlError(pdev, req);
|
|
8011324: 6839 ldr r1, [r7, #0]
|
|
8011326: 6878 ldr r0, [r7, #4]
|
|
8011328: f001 fc69 bl 8012bfe <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
801132c: 2303 movs r3, #3
|
|
801132e: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8011330: e02b b.n 801138a <USBD_CDC_Setup+0x19e>
|
|
|
|
case USB_REQ_GET_INTERFACE:
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8011332: 687b ldr r3, [r7, #4]
|
|
8011334: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011338: b2db uxtb r3, r3
|
|
801133a: 2b03 cmp r3, #3
|
|
801133c: d107 bne.n 801134e <USBD_CDC_Setup+0x162>
|
|
{
|
|
(void)USBD_CtlSendData(pdev, &ifalt, 1U);
|
|
801133e: f107 030d add.w r3, r7, #13
|
|
8011342: 2201 movs r2, #1
|
|
8011344: 4619 mov r1, r3
|
|
8011346: 6878 ldr r0, [r7, #4]
|
|
8011348: f001 fcd6 bl 8012cf8 <USBD_CtlSendData>
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
ret = USBD_FAIL;
|
|
}
|
|
break;
|
|
801134c: e01d b.n 801138a <USBD_CDC_Setup+0x19e>
|
|
USBD_CtlError(pdev, req);
|
|
801134e: 6839 ldr r1, [r7, #0]
|
|
8011350: 6878 ldr r0, [r7, #4]
|
|
8011352: f001 fc54 bl 8012bfe <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8011356: 2303 movs r3, #3
|
|
8011358: 75fb strb r3, [r7, #23]
|
|
break;
|
|
801135a: e016 b.n 801138a <USBD_CDC_Setup+0x19e>
|
|
|
|
case USB_REQ_SET_INTERFACE:
|
|
if (pdev->dev_state != USBD_STATE_CONFIGURED)
|
|
801135c: 687b ldr r3, [r7, #4]
|
|
801135e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011362: b2db uxtb r3, r3
|
|
8011364: 2b03 cmp r3, #3
|
|
8011366: d00f beq.n 8011388 <USBD_CDC_Setup+0x19c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8011368: 6839 ldr r1, [r7, #0]
|
|
801136a: 6878 ldr r0, [r7, #4]
|
|
801136c: f001 fc47 bl 8012bfe <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8011370: 2303 movs r3, #3
|
|
8011372: 75fb strb r3, [r7, #23]
|
|
}
|
|
break;
|
|
8011374: e008 b.n 8011388 <USBD_CDC_Setup+0x19c>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
break;
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8011376: 6839 ldr r1, [r7, #0]
|
|
8011378: 6878 ldr r0, [r7, #4]
|
|
801137a: f001 fc40 bl 8012bfe <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
801137e: 2303 movs r3, #3
|
|
8011380: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8011382: e002 b.n 801138a <USBD_CDC_Setup+0x19e>
|
|
break;
|
|
8011384: bf00 nop
|
|
8011386: e008 b.n 801139a <USBD_CDC_Setup+0x1ae>
|
|
break;
|
|
8011388: bf00 nop
|
|
}
|
|
break;
|
|
801138a: e006 b.n 801139a <USBD_CDC_Setup+0x1ae>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
801138c: 6839 ldr r1, [r7, #0]
|
|
801138e: 6878 ldr r0, [r7, #4]
|
|
8011390: f001 fc35 bl 8012bfe <USBD_CtlError>
|
|
ret = USBD_FAIL;
|
|
8011394: 2303 movs r3, #3
|
|
8011396: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8011398: bf00 nop
|
|
}
|
|
|
|
return (uint8_t)ret;
|
|
801139a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
801139c: 4618 mov r0, r3
|
|
801139e: 3718 adds r7, #24
|
|
80113a0: 46bd mov sp, r7
|
|
80113a2: bd80 pop {r7, pc}
|
|
|
|
080113a4 <USBD_CDC_DataIn>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint number
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
80113a4: b580 push {r7, lr}
|
|
80113a6: b084 sub sp, #16
|
|
80113a8: af00 add r7, sp, #0
|
|
80113aa: 6078 str r0, [r7, #4]
|
|
80113ac: 460b mov r3, r1
|
|
80113ae: 70fb strb r3, [r7, #3]
|
|
USBD_CDC_HandleTypeDef *hcdc;
|
|
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef *)pdev->pData;
|
|
80113b0: 687b ldr r3, [r7, #4]
|
|
80113b2: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80113b6: 60fb str r3, [r7, #12]
|
|
|
|
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
|
|
80113b8: 687b ldr r3, [r7, #4]
|
|
80113ba: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80113be: 687b ldr r3, [r7, #4]
|
|
80113c0: 32b0 adds r2, #176 @ 0xb0
|
|
80113c2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80113c6: 2b00 cmp r3, #0
|
|
80113c8: d101 bne.n 80113ce <USBD_CDC_DataIn+0x2a>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
80113ca: 2303 movs r3, #3
|
|
80113cc: e065 b.n 801149a <USBD_CDC_DataIn+0xf6>
|
|
}
|
|
|
|
hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
80113ce: 687b ldr r3, [r7, #4]
|
|
80113d0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80113d4: 687b ldr r3, [r7, #4]
|
|
80113d6: 32b0 adds r2, #176 @ 0xb0
|
|
80113d8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80113dc: 60bb str r3, [r7, #8]
|
|
|
|
if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) &&
|
|
80113de: 78fb ldrb r3, [r7, #3]
|
|
80113e0: f003 020f and.w r2, r3, #15
|
|
80113e4: 6879 ldr r1, [r7, #4]
|
|
80113e6: 4613 mov r3, r2
|
|
80113e8: 009b lsls r3, r3, #2
|
|
80113ea: 4413 add r3, r2
|
|
80113ec: 009b lsls r3, r3, #2
|
|
80113ee: 440b add r3, r1
|
|
80113f0: 3314 adds r3, #20
|
|
80113f2: 681b ldr r3, [r3, #0]
|
|
80113f4: 2b00 cmp r3, #0
|
|
80113f6: d02f beq.n 8011458 <USBD_CDC_DataIn+0xb4>
|
|
((pdev->ep_in[epnum & 0xFU].total_length % hpcd->IN_ep[epnum & 0xFU].maxpacket) == 0U))
|
|
80113f8: 78fb ldrb r3, [r7, #3]
|
|
80113fa: f003 020f and.w r2, r3, #15
|
|
80113fe: 6879 ldr r1, [r7, #4]
|
|
8011400: 4613 mov r3, r2
|
|
8011402: 009b lsls r3, r3, #2
|
|
8011404: 4413 add r3, r2
|
|
8011406: 009b lsls r3, r3, #2
|
|
8011408: 440b add r3, r1
|
|
801140a: 3314 adds r3, #20
|
|
801140c: 681a ldr r2, [r3, #0]
|
|
801140e: 78fb ldrb r3, [r7, #3]
|
|
8011410: f003 010f and.w r1, r3, #15
|
|
8011414: 68f8 ldr r0, [r7, #12]
|
|
8011416: 460b mov r3, r1
|
|
8011418: 009b lsls r3, r3, #2
|
|
801141a: 440b add r3, r1
|
|
801141c: 00db lsls r3, r3, #3
|
|
801141e: 4403 add r3, r0
|
|
8011420: 3320 adds r3, #32
|
|
8011422: 681b ldr r3, [r3, #0]
|
|
8011424: fbb2 f1f3 udiv r1, r2, r3
|
|
8011428: fb01 f303 mul.w r3, r1, r3
|
|
801142c: 1ad3 subs r3, r2, r3
|
|
if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) &&
|
|
801142e: 2b00 cmp r3, #0
|
|
8011430: d112 bne.n 8011458 <USBD_CDC_DataIn+0xb4>
|
|
{
|
|
/* Update the packet total length */
|
|
pdev->ep_in[epnum & 0xFU].total_length = 0U;
|
|
8011432: 78fb ldrb r3, [r7, #3]
|
|
8011434: f003 020f and.w r2, r3, #15
|
|
8011438: 6879 ldr r1, [r7, #4]
|
|
801143a: 4613 mov r3, r2
|
|
801143c: 009b lsls r3, r3, #2
|
|
801143e: 4413 add r3, r2
|
|
8011440: 009b lsls r3, r3, #2
|
|
8011442: 440b add r3, r1
|
|
8011444: 3314 adds r3, #20
|
|
8011446: 2200 movs r2, #0
|
|
8011448: 601a str r2, [r3, #0]
|
|
|
|
/* Send ZLP */
|
|
(void)USBD_LL_Transmit(pdev, epnum, NULL, 0U);
|
|
801144a: 78f9 ldrb r1, [r7, #3]
|
|
801144c: 2300 movs r3, #0
|
|
801144e: 2200 movs r2, #0
|
|
8011450: 6878 ldr r0, [r7, #4]
|
|
8011452: f007 fe9c bl 801918e <USBD_LL_Transmit>
|
|
8011456: e01f b.n 8011498 <USBD_CDC_DataIn+0xf4>
|
|
}
|
|
else
|
|
{
|
|
hcdc->TxState = 0U;
|
|
8011458: 68bb ldr r3, [r7, #8]
|
|
801145a: 2200 movs r2, #0
|
|
801145c: f8c3 2214 str.w r2, [r3, #532] @ 0x214
|
|
|
|
if (((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt != NULL)
|
|
8011460: 687b ldr r3, [r7, #4]
|
|
8011462: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8011466: 687a ldr r2, [r7, #4]
|
|
8011468: 33b0 adds r3, #176 @ 0xb0
|
|
801146a: 009b lsls r3, r3, #2
|
|
801146c: 4413 add r3, r2
|
|
801146e: 685b ldr r3, [r3, #4]
|
|
8011470: 691b ldr r3, [r3, #16]
|
|
8011472: 2b00 cmp r3, #0
|
|
8011474: d010 beq.n 8011498 <USBD_CDC_DataIn+0xf4>
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum);
|
|
8011476: 687b ldr r3, [r7, #4]
|
|
8011478: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
801147c: 687a ldr r2, [r7, #4]
|
|
801147e: 33b0 adds r3, #176 @ 0xb0
|
|
8011480: 009b lsls r3, r3, #2
|
|
8011482: 4413 add r3, r2
|
|
8011484: 685b ldr r3, [r3, #4]
|
|
8011486: 691b ldr r3, [r3, #16]
|
|
8011488: 68ba ldr r2, [r7, #8]
|
|
801148a: f8d2 0208 ldr.w r0, [r2, #520] @ 0x208
|
|
801148e: 68ba ldr r2, [r7, #8]
|
|
8011490: f502 7104 add.w r1, r2, #528 @ 0x210
|
|
8011494: 78fa ldrb r2, [r7, #3]
|
|
8011496: 4798 blx r3
|
|
}
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8011498: 2300 movs r3, #0
|
|
}
|
|
801149a: 4618 mov r0, r3
|
|
801149c: 3710 adds r7, #16
|
|
801149e: 46bd mov sp, r7
|
|
80114a0: bd80 pop {r7, pc}
|
|
|
|
080114a2 <USBD_CDC_DataOut>:
|
|
* @param pdev: device instance
|
|
* @param epnum: endpoint number
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
|
|
{
|
|
80114a2: b580 push {r7, lr}
|
|
80114a4: b084 sub sp, #16
|
|
80114a6: af00 add r7, sp, #0
|
|
80114a8: 6078 str r0, [r7, #4]
|
|
80114aa: 460b mov r3, r1
|
|
80114ac: 70fb strb r3, [r7, #3]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
80114ae: 687b ldr r3, [r7, #4]
|
|
80114b0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80114b4: 687b ldr r3, [r7, #4]
|
|
80114b6: 32b0 adds r2, #176 @ 0xb0
|
|
80114b8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80114bc: 60fb str r3, [r7, #12]
|
|
|
|
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
|
|
80114be: 687b ldr r3, [r7, #4]
|
|
80114c0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80114c4: 687b ldr r3, [r7, #4]
|
|
80114c6: 32b0 adds r2, #176 @ 0xb0
|
|
80114c8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80114cc: 2b00 cmp r3, #0
|
|
80114ce: d101 bne.n 80114d4 <USBD_CDC_DataOut+0x32>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
80114d0: 2303 movs r3, #3
|
|
80114d2: e01a b.n 801150a <USBD_CDC_DataOut+0x68>
|
|
}
|
|
|
|
/* Get the received data length */
|
|
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
|
|
80114d4: 78fb ldrb r3, [r7, #3]
|
|
80114d6: 4619 mov r1, r3
|
|
80114d8: 6878 ldr r0, [r7, #4]
|
|
80114da: f007 fe9a bl 8019212 <USBD_LL_GetRxDataSize>
|
|
80114de: 4602 mov r2, r0
|
|
80114e0: 68fb ldr r3, [r7, #12]
|
|
80114e2: f8c3 220c str.w r2, [r3, #524] @ 0x20c
|
|
|
|
/* USB data will be immediately processed, this allow next USB traffic being
|
|
NAKed till the end of the application Xfer */
|
|
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Receive(hcdc->RxBuffer, &hcdc->RxLength);
|
|
80114e6: 687b ldr r3, [r7, #4]
|
|
80114e8: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
80114ec: 687a ldr r2, [r7, #4]
|
|
80114ee: 33b0 adds r3, #176 @ 0xb0
|
|
80114f0: 009b lsls r3, r3, #2
|
|
80114f2: 4413 add r3, r2
|
|
80114f4: 685b ldr r3, [r3, #4]
|
|
80114f6: 68db ldr r3, [r3, #12]
|
|
80114f8: 68fa ldr r2, [r7, #12]
|
|
80114fa: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204
|
|
80114fe: 68fa ldr r2, [r7, #12]
|
|
8011500: f502 7203 add.w r2, r2, #524 @ 0x20c
|
|
8011504: 4611 mov r1, r2
|
|
8011506: 4798 blx r3
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8011508: 2300 movs r3, #0
|
|
}
|
|
801150a: 4618 mov r0, r3
|
|
801150c: 3710 adds r7, #16
|
|
801150e: 46bd mov sp, r7
|
|
8011510: bd80 pop {r7, pc}
|
|
|
|
08011512 <USBD_CDC_EP0_RxReady>:
|
|
* Handle EP0 Rx Ready event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8011512: b580 push {r7, lr}
|
|
8011514: b084 sub sp, #16
|
|
8011516: af00 add r7, sp, #0
|
|
8011518: 6078 str r0, [r7, #4]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
801151a: 687b ldr r3, [r7, #4]
|
|
801151c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8011520: 687b ldr r3, [r7, #4]
|
|
8011522: 32b0 adds r2, #176 @ 0xb0
|
|
8011524: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011528: 60fb str r3, [r7, #12]
|
|
|
|
if (hcdc == NULL)
|
|
801152a: 68fb ldr r3, [r7, #12]
|
|
801152c: 2b00 cmp r3, #0
|
|
801152e: d101 bne.n 8011534 <USBD_CDC_EP0_RxReady+0x22>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8011530: 2303 movs r3, #3
|
|
8011532: e024 b.n 801157e <USBD_CDC_EP0_RxReady+0x6c>
|
|
}
|
|
|
|
if ((pdev->pUserData[pdev->classId] != NULL) && (hcdc->CmdOpCode != 0xFFU))
|
|
8011534: 687b ldr r3, [r7, #4]
|
|
8011536: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
801153a: 687a ldr r2, [r7, #4]
|
|
801153c: 33b0 adds r3, #176 @ 0xb0
|
|
801153e: 009b lsls r3, r3, #2
|
|
8011540: 4413 add r3, r2
|
|
8011542: 685b ldr r3, [r3, #4]
|
|
8011544: 2b00 cmp r3, #0
|
|
8011546: d019 beq.n 801157c <USBD_CDC_EP0_RxReady+0x6a>
|
|
8011548: 68fb ldr r3, [r7, #12]
|
|
801154a: f893 3200 ldrb.w r3, [r3, #512] @ 0x200
|
|
801154e: 2bff cmp r3, #255 @ 0xff
|
|
8011550: d014 beq.n 801157c <USBD_CDC_EP0_RxReady+0x6a>
|
|
{
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode,
|
|
8011552: 687b ldr r3, [r7, #4]
|
|
8011554: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8011558: 687a ldr r2, [r7, #4]
|
|
801155a: 33b0 adds r3, #176 @ 0xb0
|
|
801155c: 009b lsls r3, r3, #2
|
|
801155e: 4413 add r3, r2
|
|
8011560: 685b ldr r3, [r3, #4]
|
|
8011562: 689b ldr r3, [r3, #8]
|
|
8011564: 68fa ldr r2, [r7, #12]
|
|
8011566: f892 0200 ldrb.w r0, [r2, #512] @ 0x200
|
|
(uint8_t *)hcdc->data,
|
|
801156a: 68f9 ldr r1, [r7, #12]
|
|
(uint16_t)hcdc->CmdLength);
|
|
801156c: 68fa ldr r2, [r7, #12]
|
|
801156e: f892 2201 ldrb.w r2, [r2, #513] @ 0x201
|
|
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode,
|
|
8011572: 4798 blx r3
|
|
hcdc->CmdOpCode = 0xFFU;
|
|
8011574: 68fb ldr r3, [r7, #12]
|
|
8011576: 22ff movs r2, #255 @ 0xff
|
|
8011578: f883 2200 strb.w r2, [r3, #512] @ 0x200
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
801157c: 2300 movs r3, #0
|
|
}
|
|
801157e: 4618 mov r0, r3
|
|
8011580: 3710 adds r7, #16
|
|
8011582: 46bd mov sp, r7
|
|
8011584: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08011588 <USBD_CDC_GetFSCfgDesc>:
|
|
* Return configuration descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
|
|
{
|
|
8011588: b580 push {r7, lr}
|
|
801158a: b086 sub sp, #24
|
|
801158c: af00 add r7, sp, #0
|
|
801158e: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
|
|
8011590: 2182 movs r1, #130 @ 0x82
|
|
8011592: 4818 ldr r0, [pc, #96] @ (80115f4 <USBD_CDC_GetFSCfgDesc+0x6c>)
|
|
8011594: f000 fcd0 bl 8011f38 <USBD_GetEpDesc>
|
|
8011598: 6178 str r0, [r7, #20]
|
|
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
|
|
801159a: 2101 movs r1, #1
|
|
801159c: 4815 ldr r0, [pc, #84] @ (80115f4 <USBD_CDC_GetFSCfgDesc+0x6c>)
|
|
801159e: f000 fccb bl 8011f38 <USBD_GetEpDesc>
|
|
80115a2: 6138 str r0, [r7, #16]
|
|
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
|
|
80115a4: 2181 movs r1, #129 @ 0x81
|
|
80115a6: 4813 ldr r0, [pc, #76] @ (80115f4 <USBD_CDC_GetFSCfgDesc+0x6c>)
|
|
80115a8: f000 fcc6 bl 8011f38 <USBD_GetEpDesc>
|
|
80115ac: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpCmdDesc != NULL)
|
|
80115ae: 697b ldr r3, [r7, #20]
|
|
80115b0: 2b00 cmp r3, #0
|
|
80115b2: d002 beq.n 80115ba <USBD_CDC_GetFSCfgDesc+0x32>
|
|
{
|
|
pEpCmdDesc->bInterval = CDC_FS_BINTERVAL;
|
|
80115b4: 697b ldr r3, [r7, #20]
|
|
80115b6: 2210 movs r2, #16
|
|
80115b8: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
if (pEpOutDesc != NULL)
|
|
80115ba: 693b ldr r3, [r7, #16]
|
|
80115bc: 2b00 cmp r3, #0
|
|
80115be: d006 beq.n 80115ce <USBD_CDC_GetFSCfgDesc+0x46>
|
|
{
|
|
pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
|
|
80115c0: 693b ldr r3, [r7, #16]
|
|
80115c2: 2200 movs r2, #0
|
|
80115c4: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
80115c8: 711a strb r2, [r3, #4]
|
|
80115ca: 2200 movs r2, #0
|
|
80115cc: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
if (pEpInDesc != NULL)
|
|
80115ce: 68fb ldr r3, [r7, #12]
|
|
80115d0: 2b00 cmp r3, #0
|
|
80115d2: d006 beq.n 80115e2 <USBD_CDC_GetFSCfgDesc+0x5a>
|
|
{
|
|
pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
|
|
80115d4: 68fb ldr r3, [r7, #12]
|
|
80115d6: 2200 movs r2, #0
|
|
80115d8: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
80115dc: 711a strb r2, [r3, #4]
|
|
80115de: 2200 movs r2, #0
|
|
80115e0: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
|
|
80115e2: 687b ldr r3, [r7, #4]
|
|
80115e4: 2243 movs r2, #67 @ 0x43
|
|
80115e6: 801a strh r2, [r3, #0]
|
|
return USBD_CDC_CfgDesc;
|
|
80115e8: 4b02 ldr r3, [pc, #8] @ (80115f4 <USBD_CDC_GetFSCfgDesc+0x6c>)
|
|
}
|
|
80115ea: 4618 mov r0, r3
|
|
80115ec: 3718 adds r7, #24
|
|
80115ee: 46bd mov sp, r7
|
|
80115f0: bd80 pop {r7, pc}
|
|
80115f2: bf00 nop
|
|
80115f4: 2000005c .word 0x2000005c
|
|
|
|
080115f8 <USBD_CDC_GetHSCfgDesc>:
|
|
* Return configuration descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
|
|
{
|
|
80115f8: b580 push {r7, lr}
|
|
80115fa: b086 sub sp, #24
|
|
80115fc: af00 add r7, sp, #0
|
|
80115fe: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
|
|
8011600: 2182 movs r1, #130 @ 0x82
|
|
8011602: 4818 ldr r0, [pc, #96] @ (8011664 <USBD_CDC_GetHSCfgDesc+0x6c>)
|
|
8011604: f000 fc98 bl 8011f38 <USBD_GetEpDesc>
|
|
8011608: 6178 str r0, [r7, #20]
|
|
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
|
|
801160a: 2101 movs r1, #1
|
|
801160c: 4815 ldr r0, [pc, #84] @ (8011664 <USBD_CDC_GetHSCfgDesc+0x6c>)
|
|
801160e: f000 fc93 bl 8011f38 <USBD_GetEpDesc>
|
|
8011612: 6138 str r0, [r7, #16]
|
|
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
|
|
8011614: 2181 movs r1, #129 @ 0x81
|
|
8011616: 4813 ldr r0, [pc, #76] @ (8011664 <USBD_CDC_GetHSCfgDesc+0x6c>)
|
|
8011618: f000 fc8e bl 8011f38 <USBD_GetEpDesc>
|
|
801161c: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpCmdDesc != NULL)
|
|
801161e: 697b ldr r3, [r7, #20]
|
|
8011620: 2b00 cmp r3, #0
|
|
8011622: d002 beq.n 801162a <USBD_CDC_GetHSCfgDesc+0x32>
|
|
{
|
|
pEpCmdDesc->bInterval = CDC_HS_BINTERVAL;
|
|
8011624: 697b ldr r3, [r7, #20]
|
|
8011626: 2210 movs r2, #16
|
|
8011628: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
if (pEpOutDesc != NULL)
|
|
801162a: 693b ldr r3, [r7, #16]
|
|
801162c: 2b00 cmp r3, #0
|
|
801162e: d006 beq.n 801163e <USBD_CDC_GetHSCfgDesc+0x46>
|
|
{
|
|
pEpOutDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE;
|
|
8011630: 693b ldr r3, [r7, #16]
|
|
8011632: 2200 movs r2, #0
|
|
8011634: 711a strb r2, [r3, #4]
|
|
8011636: 2200 movs r2, #0
|
|
8011638: f042 0202 orr.w r2, r2, #2
|
|
801163c: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
if (pEpInDesc != NULL)
|
|
801163e: 68fb ldr r3, [r7, #12]
|
|
8011640: 2b00 cmp r3, #0
|
|
8011642: d006 beq.n 8011652 <USBD_CDC_GetHSCfgDesc+0x5a>
|
|
{
|
|
pEpInDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE;
|
|
8011644: 68fb ldr r3, [r7, #12]
|
|
8011646: 2200 movs r2, #0
|
|
8011648: 711a strb r2, [r3, #4]
|
|
801164a: 2200 movs r2, #0
|
|
801164c: f042 0202 orr.w r2, r2, #2
|
|
8011650: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
|
|
8011652: 687b ldr r3, [r7, #4]
|
|
8011654: 2243 movs r2, #67 @ 0x43
|
|
8011656: 801a strh r2, [r3, #0]
|
|
return USBD_CDC_CfgDesc;
|
|
8011658: 4b02 ldr r3, [pc, #8] @ (8011664 <USBD_CDC_GetHSCfgDesc+0x6c>)
|
|
}
|
|
801165a: 4618 mov r0, r3
|
|
801165c: 3718 adds r7, #24
|
|
801165e: 46bd mov sp, r7
|
|
8011660: bd80 pop {r7, pc}
|
|
8011662: bf00 nop
|
|
8011664: 2000005c .word 0x2000005c
|
|
|
|
08011668 <USBD_CDC_GetOtherSpeedCfgDesc>:
|
|
* Return configuration descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
|
|
{
|
|
8011668: b580 push {r7, lr}
|
|
801166a: b086 sub sp, #24
|
|
801166c: af00 add r7, sp, #0
|
|
801166e: 6078 str r0, [r7, #4]
|
|
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
|
|
8011670: 2182 movs r1, #130 @ 0x82
|
|
8011672: 4818 ldr r0, [pc, #96] @ (80116d4 <USBD_CDC_GetOtherSpeedCfgDesc+0x6c>)
|
|
8011674: f000 fc60 bl 8011f38 <USBD_GetEpDesc>
|
|
8011678: 6178 str r0, [r7, #20]
|
|
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
|
|
801167a: 2101 movs r1, #1
|
|
801167c: 4815 ldr r0, [pc, #84] @ (80116d4 <USBD_CDC_GetOtherSpeedCfgDesc+0x6c>)
|
|
801167e: f000 fc5b bl 8011f38 <USBD_GetEpDesc>
|
|
8011682: 6138 str r0, [r7, #16]
|
|
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
|
|
8011684: 2181 movs r1, #129 @ 0x81
|
|
8011686: 4813 ldr r0, [pc, #76] @ (80116d4 <USBD_CDC_GetOtherSpeedCfgDesc+0x6c>)
|
|
8011688: f000 fc56 bl 8011f38 <USBD_GetEpDesc>
|
|
801168c: 60f8 str r0, [r7, #12]
|
|
|
|
if (pEpCmdDesc != NULL)
|
|
801168e: 697b ldr r3, [r7, #20]
|
|
8011690: 2b00 cmp r3, #0
|
|
8011692: d002 beq.n 801169a <USBD_CDC_GetOtherSpeedCfgDesc+0x32>
|
|
{
|
|
pEpCmdDesc->bInterval = CDC_FS_BINTERVAL;
|
|
8011694: 697b ldr r3, [r7, #20]
|
|
8011696: 2210 movs r2, #16
|
|
8011698: 719a strb r2, [r3, #6]
|
|
}
|
|
|
|
if (pEpOutDesc != NULL)
|
|
801169a: 693b ldr r3, [r7, #16]
|
|
801169c: 2b00 cmp r3, #0
|
|
801169e: d006 beq.n 80116ae <USBD_CDC_GetOtherSpeedCfgDesc+0x46>
|
|
{
|
|
pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
|
|
80116a0: 693b ldr r3, [r7, #16]
|
|
80116a2: 2200 movs r2, #0
|
|
80116a4: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
80116a8: 711a strb r2, [r3, #4]
|
|
80116aa: 2200 movs r2, #0
|
|
80116ac: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
if (pEpInDesc != NULL)
|
|
80116ae: 68fb ldr r3, [r7, #12]
|
|
80116b0: 2b00 cmp r3, #0
|
|
80116b2: d006 beq.n 80116c2 <USBD_CDC_GetOtherSpeedCfgDesc+0x5a>
|
|
{
|
|
pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
|
|
80116b4: 68fb ldr r3, [r7, #12]
|
|
80116b6: 2200 movs r2, #0
|
|
80116b8: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
80116bc: 711a strb r2, [r3, #4]
|
|
80116be: 2200 movs r2, #0
|
|
80116c0: 715a strb r2, [r3, #5]
|
|
}
|
|
|
|
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
|
|
80116c2: 687b ldr r3, [r7, #4]
|
|
80116c4: 2243 movs r2, #67 @ 0x43
|
|
80116c6: 801a strh r2, [r3, #0]
|
|
return USBD_CDC_CfgDesc;
|
|
80116c8: 4b02 ldr r3, [pc, #8] @ (80116d4 <USBD_CDC_GetOtherSpeedCfgDesc+0x6c>)
|
|
}
|
|
80116ca: 4618 mov r0, r3
|
|
80116cc: 3718 adds r7, #24
|
|
80116ce: 46bd mov sp, r7
|
|
80116d0: bd80 pop {r7, pc}
|
|
80116d2: bf00 nop
|
|
80116d4: 2000005c .word 0x2000005c
|
|
|
|
080116d8 <USBD_CDC_GetDeviceQualifierDescriptor>:
|
|
* return Device Qualifier descriptor
|
|
* @param length : pointer data length
|
|
* @retval pointer to descriptor buffer
|
|
*/
|
|
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
|
|
{
|
|
80116d8: b480 push {r7}
|
|
80116da: b083 sub sp, #12
|
|
80116dc: af00 add r7, sp, #0
|
|
80116de: 6078 str r0, [r7, #4]
|
|
*length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc);
|
|
80116e0: 687b ldr r3, [r7, #4]
|
|
80116e2: 220a movs r2, #10
|
|
80116e4: 801a strh r2, [r3, #0]
|
|
|
|
return USBD_CDC_DeviceQualifierDesc;
|
|
80116e6: 4b03 ldr r3, [pc, #12] @ (80116f4 <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
|
|
}
|
|
80116e8: 4618 mov r0, r3
|
|
80116ea: 370c adds r7, #12
|
|
80116ec: 46bd mov sp, r7
|
|
80116ee: f85d 7b04 ldr.w r7, [sp], #4
|
|
80116f2: 4770 bx lr
|
|
80116f4: 20000018 .word 0x20000018
|
|
|
|
080116f8 <USBD_CDC_RegisterInterface>:
|
|
* @param fops: CD Interface callback
|
|
* @retval status
|
|
*/
|
|
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
|
|
USBD_CDC_ItfTypeDef *fops)
|
|
{
|
|
80116f8: b480 push {r7}
|
|
80116fa: b083 sub sp, #12
|
|
80116fc: af00 add r7, sp, #0
|
|
80116fe: 6078 str r0, [r7, #4]
|
|
8011700: 6039 str r1, [r7, #0]
|
|
if (fops == NULL)
|
|
8011702: 683b ldr r3, [r7, #0]
|
|
8011704: 2b00 cmp r3, #0
|
|
8011706: d101 bne.n 801170c <USBD_CDC_RegisterInterface+0x14>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8011708: 2303 movs r3, #3
|
|
801170a: e009 b.n 8011720 <USBD_CDC_RegisterInterface+0x28>
|
|
}
|
|
|
|
pdev->pUserData[pdev->classId] = fops;
|
|
801170c: 687b ldr r3, [r7, #4]
|
|
801170e: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
|
|
8011712: 687a ldr r2, [r7, #4]
|
|
8011714: 33b0 adds r3, #176 @ 0xb0
|
|
8011716: 009b lsls r3, r3, #2
|
|
8011718: 4413 add r3, r2
|
|
801171a: 683a ldr r2, [r7, #0]
|
|
801171c: 605a str r2, [r3, #4]
|
|
|
|
return (uint8_t)USBD_OK;
|
|
801171e: 2300 movs r3, #0
|
|
}
|
|
8011720: 4618 mov r0, r3
|
|
8011722: 370c adds r7, #12
|
|
8011724: 46bd mov sp, r7
|
|
8011726: f85d 7b04 ldr.w r7, [sp], #4
|
|
801172a: 4770 bx lr
|
|
|
|
0801172c <USBD_CDC_SetTxBuffer>:
|
|
{
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
|
|
#else
|
|
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuff, uint32_t length)
|
|
{
|
|
801172c: b480 push {r7}
|
|
801172e: b087 sub sp, #28
|
|
8011730: af00 add r7, sp, #0
|
|
8011732: 60f8 str r0, [r7, #12]
|
|
8011734: 60b9 str r1, [r7, #8]
|
|
8011736: 607a str r2, [r7, #4]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8011738: 68fb ldr r3, [r7, #12]
|
|
801173a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
801173e: 68fb ldr r3, [r7, #12]
|
|
8011740: 32b0 adds r2, #176 @ 0xb0
|
|
8011742: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011746: 617b str r3, [r7, #20]
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (hcdc == NULL)
|
|
8011748: 697b ldr r3, [r7, #20]
|
|
801174a: 2b00 cmp r3, #0
|
|
801174c: d101 bne.n 8011752 <USBD_CDC_SetTxBuffer+0x26>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
801174e: 2303 movs r3, #3
|
|
8011750: e008 b.n 8011764 <USBD_CDC_SetTxBuffer+0x38>
|
|
}
|
|
|
|
hcdc->TxBuffer = pbuff;
|
|
8011752: 697b ldr r3, [r7, #20]
|
|
8011754: 68ba ldr r2, [r7, #8]
|
|
8011756: f8c3 2208 str.w r2, [r3, #520] @ 0x208
|
|
hcdc->TxLength = length;
|
|
801175a: 697b ldr r3, [r7, #20]
|
|
801175c: 687a ldr r2, [r7, #4]
|
|
801175e: f8c3 2210 str.w r2, [r3, #528] @ 0x210
|
|
|
|
return (uint8_t)USBD_OK;
|
|
8011762: 2300 movs r3, #0
|
|
}
|
|
8011764: 4618 mov r0, r3
|
|
8011766: 371c adds r7, #28
|
|
8011768: 46bd mov sp, r7
|
|
801176a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801176e: 4770 bx lr
|
|
|
|
08011770 <USBD_CDC_SetRxBuffer>:
|
|
* @param pdev: device instance
|
|
* @param pbuff: Rx Buffer
|
|
* @retval status
|
|
*/
|
|
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff)
|
|
{
|
|
8011770: b480 push {r7}
|
|
8011772: b085 sub sp, #20
|
|
8011774: af00 add r7, sp, #0
|
|
8011776: 6078 str r0, [r7, #4]
|
|
8011778: 6039 str r1, [r7, #0]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
801177a: 687b ldr r3, [r7, #4]
|
|
801177c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8011780: 687b ldr r3, [r7, #4]
|
|
8011782: 32b0 adds r2, #176 @ 0xb0
|
|
8011784: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011788: 60fb str r3, [r7, #12]
|
|
|
|
if (hcdc == NULL)
|
|
801178a: 68fb ldr r3, [r7, #12]
|
|
801178c: 2b00 cmp r3, #0
|
|
801178e: d101 bne.n 8011794 <USBD_CDC_SetRxBuffer+0x24>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8011790: 2303 movs r3, #3
|
|
8011792: e004 b.n 801179e <USBD_CDC_SetRxBuffer+0x2e>
|
|
}
|
|
|
|
hcdc->RxBuffer = pbuff;
|
|
8011794: 68fb ldr r3, [r7, #12]
|
|
8011796: 683a ldr r2, [r7, #0]
|
|
8011798: f8c3 2204 str.w r2, [r3, #516] @ 0x204
|
|
|
|
return (uint8_t)USBD_OK;
|
|
801179c: 2300 movs r3, #0
|
|
}
|
|
801179e: 4618 mov r0, r3
|
|
80117a0: 3714 adds r7, #20
|
|
80117a2: 46bd mov sp, r7
|
|
80117a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80117a8: 4770 bx lr
|
|
...
|
|
|
|
080117ac <USBD_CDC_TransmitPacket>:
|
|
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t ClassId)
|
|
{
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
|
|
#else
|
|
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
|
|
{
|
|
80117ac: b580 push {r7, lr}
|
|
80117ae: b084 sub sp, #16
|
|
80117b0: af00 add r7, sp, #0
|
|
80117b2: 6078 str r0, [r7, #4]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
80117b4: 687b ldr r3, [r7, #4]
|
|
80117b6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
80117ba: 687b ldr r3, [r7, #4]
|
|
80117bc: 32b0 adds r2, #176 @ 0xb0
|
|
80117be: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80117c2: 60bb str r3, [r7, #8]
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
USBD_StatusTypeDef ret = USBD_BUSY;
|
|
80117c4: 2301 movs r3, #1
|
|
80117c6: 73fb strb r3, [r7, #15]
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, ClassId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (hcdc == NULL)
|
|
80117c8: 68bb ldr r3, [r7, #8]
|
|
80117ca: 2b00 cmp r3, #0
|
|
80117cc: d101 bne.n 80117d2 <USBD_CDC_TransmitPacket+0x26>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
80117ce: 2303 movs r3, #3
|
|
80117d0: e025 b.n 801181e <USBD_CDC_TransmitPacket+0x72>
|
|
}
|
|
|
|
if (hcdc->TxState == 0U)
|
|
80117d2: 68bb ldr r3, [r7, #8]
|
|
80117d4: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
|
|
80117d8: 2b00 cmp r3, #0
|
|
80117da: d11f bne.n 801181c <USBD_CDC_TransmitPacket+0x70>
|
|
{
|
|
/* Tx Transfer in progress */
|
|
hcdc->TxState = 1U;
|
|
80117dc: 68bb ldr r3, [r7, #8]
|
|
80117de: 2201 movs r2, #1
|
|
80117e0: f8c3 2214 str.w r2, [r3, #532] @ 0x214
|
|
|
|
/* Update the packet total length */
|
|
pdev->ep_in[CDCInEpAdd & 0xFU].total_length = hcdc->TxLength;
|
|
80117e4: 4b10 ldr r3, [pc, #64] @ (8011828 <USBD_CDC_TransmitPacket+0x7c>)
|
|
80117e6: 781b ldrb r3, [r3, #0]
|
|
80117e8: f003 020f and.w r2, r3, #15
|
|
80117ec: 68bb ldr r3, [r7, #8]
|
|
80117ee: f8d3 1210 ldr.w r1, [r3, #528] @ 0x210
|
|
80117f2: 6878 ldr r0, [r7, #4]
|
|
80117f4: 4613 mov r3, r2
|
|
80117f6: 009b lsls r3, r3, #2
|
|
80117f8: 4413 add r3, r2
|
|
80117fa: 009b lsls r3, r3, #2
|
|
80117fc: 4403 add r3, r0
|
|
80117fe: 3314 adds r3, #20
|
|
8011800: 6019 str r1, [r3, #0]
|
|
|
|
/* Transmit next packet */
|
|
(void)USBD_LL_Transmit(pdev, CDCInEpAdd, hcdc->TxBuffer, hcdc->TxLength);
|
|
8011802: 4b09 ldr r3, [pc, #36] @ (8011828 <USBD_CDC_TransmitPacket+0x7c>)
|
|
8011804: 7819 ldrb r1, [r3, #0]
|
|
8011806: 68bb ldr r3, [r7, #8]
|
|
8011808: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208
|
|
801180c: 68bb ldr r3, [r7, #8]
|
|
801180e: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210
|
|
8011812: 6878 ldr r0, [r7, #4]
|
|
8011814: f007 fcbb bl 801918e <USBD_LL_Transmit>
|
|
|
|
ret = USBD_OK;
|
|
8011818: 2300 movs r3, #0
|
|
801181a: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return (uint8_t)ret;
|
|
801181c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
801181e: 4618 mov r0, r3
|
|
8011820: 3710 adds r7, #16
|
|
8011822: 46bd mov sp, r7
|
|
8011824: bd80 pop {r7, pc}
|
|
8011826: bf00 nop
|
|
8011828: 2000009f .word 0x2000009f
|
|
|
|
0801182c <USBD_CDC_ReceivePacket>:
|
|
* prepare OUT Endpoint for reception
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
|
|
{
|
|
801182c: b580 push {r7, lr}
|
|
801182e: b084 sub sp, #16
|
|
8011830: af00 add r7, sp, #0
|
|
8011832: 6078 str r0, [r7, #4]
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
|
|
8011834: 687b ldr r3, [r7, #4]
|
|
8011836: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
801183a: 687b ldr r3, [r7, #4]
|
|
801183c: 32b0 adds r2, #176 @ 0xb0
|
|
801183e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011842: 60fb str r3, [r7, #12]
|
|
#ifdef USE_USBD_COMPOSITE
|
|
/* Get the Endpoints addresses allocated for this class instance */
|
|
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId);
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
|
|
8011844: 687b ldr r3, [r7, #4]
|
|
8011846: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
801184a: 687b ldr r3, [r7, #4]
|
|
801184c: 32b0 adds r2, #176 @ 0xb0
|
|
801184e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011852: 2b00 cmp r3, #0
|
|
8011854: d101 bne.n 801185a <USBD_CDC_ReceivePacket+0x2e>
|
|
{
|
|
return (uint8_t)USBD_FAIL;
|
|
8011856: 2303 movs r3, #3
|
|
8011858: e018 b.n 801188c <USBD_CDC_ReceivePacket+0x60>
|
|
}
|
|
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
801185a: 687b ldr r3, [r7, #4]
|
|
801185c: 7c1b ldrb r3, [r3, #16]
|
|
801185e: 2b00 cmp r3, #0
|
|
8011860: d10a bne.n 8011878 <USBD_CDC_ReceivePacket+0x4c>
|
|
{
|
|
/* Prepare Out endpoint to receive next packet */
|
|
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
|
|
8011862: 4b0c ldr r3, [pc, #48] @ (8011894 <USBD_CDC_ReceivePacket+0x68>)
|
|
8011864: 7819 ldrb r1, [r3, #0]
|
|
8011866: 68fb ldr r3, [r7, #12]
|
|
8011868: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
801186c: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8011870: 6878 ldr r0, [r7, #4]
|
|
8011872: f007 fcad bl 80191d0 <USBD_LL_PrepareReceive>
|
|
8011876: e008 b.n 801188a <USBD_CDC_ReceivePacket+0x5e>
|
|
CDC_DATA_HS_OUT_PACKET_SIZE);
|
|
}
|
|
else
|
|
{
|
|
/* Prepare Out endpoint to receive next packet */
|
|
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
|
|
8011878: 4b06 ldr r3, [pc, #24] @ (8011894 <USBD_CDC_ReceivePacket+0x68>)
|
|
801187a: 7819 ldrb r1, [r3, #0]
|
|
801187c: 68fb ldr r3, [r7, #12]
|
|
801187e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
8011882: 2340 movs r3, #64 @ 0x40
|
|
8011884: 6878 ldr r0, [r7, #4]
|
|
8011886: f007 fca3 bl 80191d0 <USBD_LL_PrepareReceive>
|
|
CDC_DATA_FS_OUT_PACKET_SIZE);
|
|
}
|
|
|
|
return (uint8_t)USBD_OK;
|
|
801188a: 2300 movs r3, #0
|
|
}
|
|
801188c: 4618 mov r0, r3
|
|
801188e: 3710 adds r7, #16
|
|
8011890: 46bd mov sp, r7
|
|
8011892: bd80 pop {r7, pc}
|
|
8011894: 200000a0 .word 0x200000a0
|
|
|
|
08011898 <USBD_Init>:
|
|
* @param id: Low level core index
|
|
* @retval status: USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
|
|
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
|
|
{
|
|
8011898: b580 push {r7, lr}
|
|
801189a: b086 sub sp, #24
|
|
801189c: af00 add r7, sp, #0
|
|
801189e: 60f8 str r0, [r7, #12]
|
|
80118a0: 60b9 str r1, [r7, #8]
|
|
80118a2: 4613 mov r3, r2
|
|
80118a4: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
/* Check whether the USB Host handle is valid */
|
|
if (pdev == NULL)
|
|
80118a6: 68fb ldr r3, [r7, #12]
|
|
80118a8: 2b00 cmp r3, #0
|
|
80118aa: d101 bne.n 80118b0 <USBD_Init+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Device handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
80118ac: 2303 movs r3, #3
|
|
80118ae: e01f b.n 80118f0 <USBD_Init+0x58>
|
|
pdev->NumClasses = 0;
|
|
pdev->classId = 0;
|
|
}
|
|
#else
|
|
/* Unlink previous class*/
|
|
pdev->pClass[0] = NULL;
|
|
80118b0: 68fb ldr r3, [r7, #12]
|
|
80118b2: 2200 movs r2, #0
|
|
80118b4: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
pdev->pUserData[0] = NULL;
|
|
80118b8: 68fb ldr r3, [r7, #12]
|
|
80118ba: 2200 movs r2, #0
|
|
80118bc: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
pdev->pConfDesc = NULL;
|
|
80118c0: 68fb ldr r3, [r7, #12]
|
|
80118c2: 2200 movs r2, #0
|
|
80118c4: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
|
|
/* Assign USBD Descriptors */
|
|
if (pdesc != NULL)
|
|
80118c8: 68bb ldr r3, [r7, #8]
|
|
80118ca: 2b00 cmp r3, #0
|
|
80118cc: d003 beq.n 80118d6 <USBD_Init+0x3e>
|
|
{
|
|
pdev->pDesc = pdesc;
|
|
80118ce: 68fb ldr r3, [r7, #12]
|
|
80118d0: 68ba ldr r2, [r7, #8]
|
|
80118d2: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
|
|
}
|
|
|
|
/* Set Device initial State */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
80118d6: 68fb ldr r3, [r7, #12]
|
|
80118d8: 2201 movs r2, #1
|
|
80118da: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->id = id;
|
|
80118de: 68fb ldr r3, [r7, #12]
|
|
80118e0: 79fa ldrb r2, [r7, #7]
|
|
80118e2: 701a strb r2, [r3, #0]
|
|
|
|
/* Initialize low level driver */
|
|
ret = USBD_LL_Init(pdev);
|
|
80118e4: 68f8 ldr r0, [r7, #12]
|
|
80118e6: f007 fb07 bl 8018ef8 <USBD_LL_Init>
|
|
80118ea: 4603 mov r3, r0
|
|
80118ec: 75fb strb r3, [r7, #23]
|
|
|
|
return ret;
|
|
80118ee: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80118f0: 4618 mov r0, r3
|
|
80118f2: 3718 adds r7, #24
|
|
80118f4: 46bd mov sp, r7
|
|
80118f6: bd80 pop {r7, pc}
|
|
|
|
080118f8 <USBD_RegisterClass>:
|
|
* @param pdev: Device Handle
|
|
* @param pclass: Class handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
|
|
{
|
|
80118f8: b580 push {r7, lr}
|
|
80118fa: b084 sub sp, #16
|
|
80118fc: af00 add r7, sp, #0
|
|
80118fe: 6078 str r0, [r7, #4]
|
|
8011900: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
8011902: 2300 movs r3, #0
|
|
8011904: 81fb strh r3, [r7, #14]
|
|
|
|
if (pclass == NULL)
|
|
8011906: 683b ldr r3, [r7, #0]
|
|
8011908: 2b00 cmp r3, #0
|
|
801190a: d101 bne.n 8011910 <USBD_RegisterClass+0x18>
|
|
{
|
|
#if (USBD_DEBUG_LEVEL > 1U)
|
|
USBD_ErrLog("Invalid Class handle");
|
|
#endif /* (USBD_DEBUG_LEVEL > 1U) */
|
|
return USBD_FAIL;
|
|
801190c: 2303 movs r3, #3
|
|
801190e: e025 b.n 801195c <USBD_RegisterClass+0x64>
|
|
}
|
|
|
|
/* link the class to the USB Device handle */
|
|
pdev->pClass[0] = pclass;
|
|
8011910: 687b ldr r3, [r7, #4]
|
|
8011912: 683a ldr r2, [r7, #0]
|
|
8011914: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
|
|
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
|
|
}
|
|
#else /* Default USE_USB_FS */
|
|
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
|
|
8011918: 687b ldr r3, [r7, #4]
|
|
801191a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
801191e: 687b ldr r3, [r7, #4]
|
|
8011920: 32ae adds r2, #174 @ 0xae
|
|
8011922: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011926: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8011928: 2b00 cmp r3, #0
|
|
801192a: d00f beq.n 801194c <USBD_RegisterClass+0x54>
|
|
{
|
|
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
|
|
801192c: 687b ldr r3, [r7, #4]
|
|
801192e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
8011932: 687b ldr r3, [r7, #4]
|
|
8011934: 32ae adds r2, #174 @ 0xae
|
|
8011936: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
801193a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
801193c: f107 020e add.w r2, r7, #14
|
|
8011940: 4610 mov r0, r2
|
|
8011942: 4798 blx r3
|
|
8011944: 4602 mov r2, r0
|
|
8011946: 687b ldr r3, [r7, #4]
|
|
8011948: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
|
|
}
|
|
#endif /* USE_USB_FS */
|
|
|
|
/* Increment the NumClasses */
|
|
pdev->NumClasses++;
|
|
801194c: 687b ldr r3, [r7, #4]
|
|
801194e: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8011952: 1c5a adds r2, r3, #1
|
|
8011954: 687b ldr r3, [r7, #4]
|
|
8011956: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
|
|
|
|
return USBD_OK;
|
|
801195a: 2300 movs r3, #0
|
|
}
|
|
801195c: 4618 mov r0, r3
|
|
801195e: 3710 adds r7, #16
|
|
8011960: 46bd mov sp, r7
|
|
8011962: bd80 pop {r7, pc}
|
|
|
|
08011964 <USBD_Start>:
|
|
* Start the USB Device Core.
|
|
* @param pdev: Device Handle
|
|
* @retval USBD Status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8011964: b580 push {r7, lr}
|
|
8011966: b082 sub sp, #8
|
|
8011968: af00 add r7, sp, #0
|
|
801196a: 6078 str r0, [r7, #4]
|
|
#ifdef USE_USBD_COMPOSITE
|
|
pdev->classId = 0U;
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Start the low level driver */
|
|
return USBD_LL_Start(pdev);
|
|
801196c: 6878 ldr r0, [r7, #4]
|
|
801196e: f007 fb25 bl 8018fbc <USBD_LL_Start>
|
|
8011972: 4603 mov r3, r0
|
|
}
|
|
8011974: 4618 mov r0, r3
|
|
8011976: 3708 adds r7, #8
|
|
8011978: 46bd mov sp, r7
|
|
801197a: bd80 pop {r7, pc}
|
|
|
|
0801197c <USBD_RunTestMode>:
|
|
* Launch test mode process
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
|
|
{
|
|
801197c: b480 push {r7}
|
|
801197e: b083 sub sp, #12
|
|
8011980: af00 add r7, sp, #0
|
|
8011982: 6078 str r0, [r7, #4]
|
|
return ret;
|
|
#else
|
|
/* Prevent unused argument compilation warning */
|
|
UNUSED(pdev);
|
|
|
|
return USBD_OK;
|
|
8011984: 2300 movs r3, #0
|
|
#endif /* USBD_HS_TESTMODE_ENABLE */
|
|
}
|
|
8011986: 4618 mov r0, r3
|
|
8011988: 370c adds r7, #12
|
|
801198a: 46bd mov sp, r7
|
|
801198c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011990: 4770 bx lr
|
|
|
|
08011992 <USBD_SetClassConfig>:
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
|
|
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
8011992: b580 push {r7, lr}
|
|
8011994: b084 sub sp, #16
|
|
8011996: af00 add r7, sp, #0
|
|
8011998: 6078 str r0, [r7, #4]
|
|
801199a: 460b mov r3, r1
|
|
801199c: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
801199e: 2300 movs r3, #0
|
|
80119a0: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
80119a2: 687b ldr r3, [r7, #4]
|
|
80119a4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80119a8: 2b00 cmp r3, #0
|
|
80119aa: d009 beq.n 80119c0 <USBD_SetClassConfig+0x2e>
|
|
{
|
|
/* Set configuration and Start the Class */
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
|
|
80119ac: 687b ldr r3, [r7, #4]
|
|
80119ae: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80119b2: 681b ldr r3, [r3, #0]
|
|
80119b4: 78fa ldrb r2, [r7, #3]
|
|
80119b6: 4611 mov r1, r2
|
|
80119b8: 6878 ldr r0, [r7, #4]
|
|
80119ba: 4798 blx r3
|
|
80119bc: 4603 mov r3, r0
|
|
80119be: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
80119c0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80119c2: 4618 mov r0, r3
|
|
80119c4: 3710 adds r7, #16
|
|
80119c6: 46bd mov sp, r7
|
|
80119c8: bd80 pop {r7, pc}
|
|
|
|
080119ca <USBD_ClrClassConfig>:
|
|
* @param pdev: device instance
|
|
* @param cfgidx: configuration index
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
|
|
{
|
|
80119ca: b580 push {r7, lr}
|
|
80119cc: b084 sub sp, #16
|
|
80119ce: af00 add r7, sp, #0
|
|
80119d0: 6078 str r0, [r7, #4]
|
|
80119d2: 460b mov r3, r1
|
|
80119d4: 70fb strb r3, [r7, #3]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80119d6: 2300 movs r3, #0
|
|
80119d8: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
/* Clear configuration and De-initialize the Class process */
|
|
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
|
|
80119da: 687b ldr r3, [r7, #4]
|
|
80119dc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80119e0: 685b ldr r3, [r3, #4]
|
|
80119e2: 78fa ldrb r2, [r7, #3]
|
|
80119e4: 4611 mov r1, r2
|
|
80119e6: 6878 ldr r0, [r7, #4]
|
|
80119e8: 4798 blx r3
|
|
80119ea: 4603 mov r3, r0
|
|
80119ec: 2b00 cmp r3, #0
|
|
80119ee: d001 beq.n 80119f4 <USBD_ClrClassConfig+0x2a>
|
|
{
|
|
ret = USBD_FAIL;
|
|
80119f0: 2303 movs r3, #3
|
|
80119f2: 73fb strb r3, [r7, #15]
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
return ret;
|
|
80119f4: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80119f6: 4618 mov r0, r3
|
|
80119f8: 3710 adds r7, #16
|
|
80119fa: 46bd mov sp, r7
|
|
80119fc: bd80 pop {r7, pc}
|
|
|
|
080119fe <USBD_LL_SetupStage>:
|
|
* @param pdev: device instance
|
|
* @param psetup: setup packet buffer pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
|
|
{
|
|
80119fe: b580 push {r7, lr}
|
|
8011a00: b084 sub sp, #16
|
|
8011a02: af00 add r7, sp, #0
|
|
8011a04: 6078 str r0, [r7, #4]
|
|
8011a06: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret;
|
|
|
|
USBD_ParseSetupRequest(&pdev->request, psetup);
|
|
8011a08: 687b ldr r3, [r7, #4]
|
|
8011a0a: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8011a0e: 6839 ldr r1, [r7, #0]
|
|
8011a10: 4618 mov r0, r3
|
|
8011a12: f001 f8ba bl 8012b8a <USBD_ParseSetupRequest>
|
|
|
|
pdev->ep0_state = USBD_EP0_SETUP;
|
|
8011a16: 687b ldr r3, [r7, #4]
|
|
8011a18: 2201 movs r2, #1
|
|
8011a1a: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
pdev->ep0_data_len = pdev->request.wLength;
|
|
8011a1e: 687b ldr r3, [r7, #4]
|
|
8011a20: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
|
|
8011a24: 461a mov r2, r3
|
|
8011a26: 687b ldr r3, [r7, #4]
|
|
8011a28: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8011a2c: 687b ldr r3, [r7, #4]
|
|
8011a2e: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8011a32: f003 031f and.w r3, r3, #31
|
|
8011a36: 2b02 cmp r3, #2
|
|
8011a38: d01a beq.n 8011a70 <USBD_LL_SetupStage+0x72>
|
|
8011a3a: 2b02 cmp r3, #2
|
|
8011a3c: d822 bhi.n 8011a84 <USBD_LL_SetupStage+0x86>
|
|
8011a3e: 2b00 cmp r3, #0
|
|
8011a40: d002 beq.n 8011a48 <USBD_LL_SetupStage+0x4a>
|
|
8011a42: 2b01 cmp r3, #1
|
|
8011a44: d00a beq.n 8011a5c <USBD_LL_SetupStage+0x5e>
|
|
8011a46: e01d b.n 8011a84 <USBD_LL_SetupStage+0x86>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
ret = USBD_StdDevReq(pdev, &pdev->request);
|
|
8011a48: 687b ldr r3, [r7, #4]
|
|
8011a4a: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8011a4e: 4619 mov r1, r3
|
|
8011a50: 6878 ldr r0, [r7, #4]
|
|
8011a52: f000 fae5 bl 8012020 <USBD_StdDevReq>
|
|
8011a56: 4603 mov r3, r0
|
|
8011a58: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8011a5a: e020 b.n 8011a9e <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
ret = USBD_StdItfReq(pdev, &pdev->request);
|
|
8011a5c: 687b ldr r3, [r7, #4]
|
|
8011a5e: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8011a62: 4619 mov r1, r3
|
|
8011a64: 6878 ldr r0, [r7, #4]
|
|
8011a66: f000 fb4d bl 8012104 <USBD_StdItfReq>
|
|
8011a6a: 4603 mov r3, r0
|
|
8011a6c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8011a6e: e016 b.n 8011a9e <USBD_LL_SetupStage+0xa0>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
ret = USBD_StdEPReq(pdev, &pdev->request);
|
|
8011a70: 687b ldr r3, [r7, #4]
|
|
8011a72: f203 23aa addw r3, r3, #682 @ 0x2aa
|
|
8011a76: 4619 mov r1, r3
|
|
8011a78: 6878 ldr r0, [r7, #4]
|
|
8011a7a: f000 fbaf bl 80121dc <USBD_StdEPReq>
|
|
8011a7e: 4603 mov r3, r0
|
|
8011a80: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8011a82: e00c b.n 8011a9e <USBD_LL_SetupStage+0xa0>
|
|
|
|
default:
|
|
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
|
|
8011a84: 687b ldr r3, [r7, #4]
|
|
8011a86: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8011a8a: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
8011a8e: b2db uxtb r3, r3
|
|
8011a90: 4619 mov r1, r3
|
|
8011a92: 6878 ldr r0, [r7, #4]
|
|
8011a94: f007 faf2 bl 801907c <USBD_LL_StallEP>
|
|
8011a98: 4603 mov r3, r0
|
|
8011a9a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8011a9c: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8011a9e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8011aa0: 4618 mov r0, r3
|
|
8011aa2: 3710 adds r7, #16
|
|
8011aa4: 46bd mov sp, r7
|
|
8011aa6: bd80 pop {r7, pc}
|
|
|
|
08011aa8 <USBD_LL_DataOutStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8011aa8: b580 push {r7, lr}
|
|
8011aaa: b086 sub sp, #24
|
|
8011aac: af00 add r7, sp, #0
|
|
8011aae: 60f8 str r0, [r7, #12]
|
|
8011ab0: 460b mov r3, r1
|
|
8011ab2: 607a str r2, [r7, #4]
|
|
8011ab4: 72fb strb r3, [r7, #11]
|
|
USBD_EndpointTypeDef *pep;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8011ab6: 2300 movs r3, #0
|
|
8011ab8: 75fb strb r3, [r7, #23]
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
8011aba: 7afb ldrb r3, [r7, #11]
|
|
8011abc: 2b00 cmp r3, #0
|
|
8011abe: d177 bne.n 8011bb0 <USBD_LL_DataOutStage+0x108>
|
|
{
|
|
pep = &pdev->ep_out[0];
|
|
8011ac0: 68fb ldr r3, [r7, #12]
|
|
8011ac2: f503 73aa add.w r3, r3, #340 @ 0x154
|
|
8011ac6: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
|
|
8011ac8: 68fb ldr r3, [r7, #12]
|
|
8011aca: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8011ace: 2b03 cmp r3, #3
|
|
8011ad0: f040 80a1 bne.w 8011c16 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8011ad4: 693b ldr r3, [r7, #16]
|
|
8011ad6: 685b ldr r3, [r3, #4]
|
|
8011ad8: 693a ldr r2, [r7, #16]
|
|
8011ada: 8992 ldrh r2, [r2, #12]
|
|
8011adc: 4293 cmp r3, r2
|
|
8011ade: d91c bls.n 8011b1a <USBD_LL_DataOutStage+0x72>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8011ae0: 693b ldr r3, [r7, #16]
|
|
8011ae2: 685b ldr r3, [r3, #4]
|
|
8011ae4: 693a ldr r2, [r7, #16]
|
|
8011ae6: 8992 ldrh r2, [r2, #12]
|
|
8011ae8: 1a9a subs r2, r3, r2
|
|
8011aea: 693b ldr r3, [r7, #16]
|
|
8011aec: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
8011aee: 693b ldr r3, [r7, #16]
|
|
8011af0: 691b ldr r3, [r3, #16]
|
|
8011af2: 693a ldr r2, [r7, #16]
|
|
8011af4: 8992 ldrh r2, [r2, #12]
|
|
8011af6: 441a add r2, r3
|
|
8011af8: 693b ldr r3, [r7, #16]
|
|
8011afa: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket));
|
|
8011afc: 693b ldr r3, [r7, #16]
|
|
8011afe: 6919 ldr r1, [r3, #16]
|
|
8011b00: 693b ldr r3, [r7, #16]
|
|
8011b02: 899b ldrh r3, [r3, #12]
|
|
8011b04: 461a mov r2, r3
|
|
8011b06: 693b ldr r3, [r7, #16]
|
|
8011b08: 685b ldr r3, [r3, #4]
|
|
8011b0a: 4293 cmp r3, r2
|
|
8011b0c: bf38 it cc
|
|
8011b0e: 4613 movcc r3, r2
|
|
8011b10: 461a mov r2, r3
|
|
8011b12: 68f8 ldr r0, [r7, #12]
|
|
8011b14: f001 f940 bl 8012d98 <USBD_CtlContinueRx>
|
|
8011b18: e07d b.n 8011c16 <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
else
|
|
{
|
|
/* Find the class ID relative to the current request */
|
|
switch (pdev->request.bmRequest & 0x1FU)
|
|
8011b1a: 68fb ldr r3, [r7, #12]
|
|
8011b1c: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
|
|
8011b20: f003 031f and.w r3, r3, #31
|
|
8011b24: 2b02 cmp r3, #2
|
|
8011b26: d014 beq.n 8011b52 <USBD_LL_DataOutStage+0xaa>
|
|
8011b28: 2b02 cmp r3, #2
|
|
8011b2a: d81d bhi.n 8011b68 <USBD_LL_DataOutStage+0xc0>
|
|
8011b2c: 2b00 cmp r3, #0
|
|
8011b2e: d002 beq.n 8011b36 <USBD_LL_DataOutStage+0x8e>
|
|
8011b30: 2b01 cmp r3, #1
|
|
8011b32: d003 beq.n 8011b3c <USBD_LL_DataOutStage+0x94>
|
|
8011b34: e018 b.n 8011b68 <USBD_LL_DataOutStage+0xc0>
|
|
{
|
|
case USB_REQ_RECIPIENT_DEVICE:
|
|
/* Device requests must be managed by the first instantiated class
|
|
(or duplicated by all classes for simplicity) */
|
|
idx = 0U;
|
|
8011b36: 2300 movs r3, #0
|
|
8011b38: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8011b3a: e018 b.n 8011b6e <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_INTERFACE:
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
|
|
8011b3c: 68fb ldr r3, [r7, #12]
|
|
8011b3e: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8011b42: b2db uxtb r3, r3
|
|
8011b44: 4619 mov r1, r3
|
|
8011b46: 68f8 ldr r0, [r7, #12]
|
|
8011b48: f000 f9dc bl 8011f04 <USBD_CoreFindIF>
|
|
8011b4c: 4603 mov r3, r0
|
|
8011b4e: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8011b50: e00d b.n 8011b6e <USBD_LL_DataOutStage+0xc6>
|
|
|
|
case USB_REQ_RECIPIENT_ENDPOINT:
|
|
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
|
|
8011b52: 68fb ldr r3, [r7, #12]
|
|
8011b54: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
|
|
8011b58: b2db uxtb r3, r3
|
|
8011b5a: 4619 mov r1, r3
|
|
8011b5c: 68f8 ldr r0, [r7, #12]
|
|
8011b5e: f000 f9de bl 8011f1e <USBD_CoreFindEP>
|
|
8011b62: 4603 mov r3, r0
|
|
8011b64: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8011b66: e002 b.n 8011b6e <USBD_LL_DataOutStage+0xc6>
|
|
|
|
default:
|
|
/* Back to the first class in case of doubt */
|
|
idx = 0U;
|
|
8011b68: 2300 movs r3, #0
|
|
8011b6a: 75bb strb r3, [r7, #22]
|
|
break;
|
|
8011b6c: bf00 nop
|
|
}
|
|
|
|
if (idx < USBD_MAX_SUPPORTED_CLASS)
|
|
8011b6e: 7dbb ldrb r3, [r7, #22]
|
|
8011b70: 2b00 cmp r3, #0
|
|
8011b72: d119 bne.n 8011ba8 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
/* Setup the class ID and route the request to the relative class function */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8011b74: 68fb ldr r3, [r7, #12]
|
|
8011b76: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011b7a: b2db uxtb r3, r3
|
|
8011b7c: 2b03 cmp r3, #3
|
|
8011b7e: d113 bne.n 8011ba8 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
if (pdev->pClass[idx]->EP0_RxReady != NULL)
|
|
8011b80: 7dba ldrb r2, [r7, #22]
|
|
8011b82: 68fb ldr r3, [r7, #12]
|
|
8011b84: 32ae adds r2, #174 @ 0xae
|
|
8011b86: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011b8a: 691b ldr r3, [r3, #16]
|
|
8011b8c: 2b00 cmp r3, #0
|
|
8011b8e: d00b beq.n 8011ba8 <USBD_LL_DataOutStage+0x100>
|
|
{
|
|
pdev->classId = idx;
|
|
8011b90: 7dba ldrb r2, [r7, #22]
|
|
8011b92: 68fb ldr r3, [r7, #12]
|
|
8011b94: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[idx]->EP0_RxReady(pdev);
|
|
8011b98: 7dba ldrb r2, [r7, #22]
|
|
8011b9a: 68fb ldr r3, [r7, #12]
|
|
8011b9c: 32ae adds r2, #174 @ 0xae
|
|
8011b9e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011ba2: 691b ldr r3, [r3, #16]
|
|
8011ba4: 68f8 ldr r0, [r7, #12]
|
|
8011ba6: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8011ba8: 68f8 ldr r0, [r7, #12]
|
|
8011baa: f001 f906 bl 8012dba <USBD_CtlSendStatus>
|
|
8011bae: e032 b.n 8011c16 <USBD_LL_DataOutStage+0x16e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
|
|
8011bb0: 7afb ldrb r3, [r7, #11]
|
|
8011bb2: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8011bb6: b2db uxtb r3, r3
|
|
8011bb8: 4619 mov r1, r3
|
|
8011bba: 68f8 ldr r0, [r7, #12]
|
|
8011bbc: f000 f9af bl 8011f1e <USBD_CoreFindEP>
|
|
8011bc0: 4603 mov r3, r0
|
|
8011bc2: 75bb strb r3, [r7, #22]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8011bc4: 7dbb ldrb r3, [r7, #22]
|
|
8011bc6: 2bff cmp r3, #255 @ 0xff
|
|
8011bc8: d025 beq.n 8011c16 <USBD_LL_DataOutStage+0x16e>
|
|
8011bca: 7dbb ldrb r3, [r7, #22]
|
|
8011bcc: 2b00 cmp r3, #0
|
|
8011bce: d122 bne.n 8011c16 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8011bd0: 68fb ldr r3, [r7, #12]
|
|
8011bd2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011bd6: b2db uxtb r3, r3
|
|
8011bd8: 2b03 cmp r3, #3
|
|
8011bda: d117 bne.n 8011c0c <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
if (pdev->pClass[idx]->DataOut != NULL)
|
|
8011bdc: 7dba ldrb r2, [r7, #22]
|
|
8011bde: 68fb ldr r3, [r7, #12]
|
|
8011be0: 32ae adds r2, #174 @ 0xae
|
|
8011be2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011be6: 699b ldr r3, [r3, #24]
|
|
8011be8: 2b00 cmp r3, #0
|
|
8011bea: d00f beq.n 8011c0c <USBD_LL_DataOutStage+0x164>
|
|
{
|
|
pdev->classId = idx;
|
|
8011bec: 7dba ldrb r2, [r7, #22]
|
|
8011bee: 68fb ldr r3, [r7, #12]
|
|
8011bf0: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
|
|
8011bf4: 7dba ldrb r2, [r7, #22]
|
|
8011bf6: 68fb ldr r3, [r7, #12]
|
|
8011bf8: 32ae adds r2, #174 @ 0xae
|
|
8011bfa: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011bfe: 699b ldr r3, [r3, #24]
|
|
8011c00: 7afa ldrb r2, [r7, #11]
|
|
8011c02: 4611 mov r1, r2
|
|
8011c04: 68f8 ldr r0, [r7, #12]
|
|
8011c06: 4798 blx r3
|
|
8011c08: 4603 mov r3, r0
|
|
8011c0a: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
if (ret != USBD_OK)
|
|
8011c0c: 7dfb ldrb r3, [r7, #23]
|
|
8011c0e: 2b00 cmp r3, #0
|
|
8011c10: d001 beq.n 8011c16 <USBD_LL_DataOutStage+0x16e>
|
|
{
|
|
return ret;
|
|
8011c12: 7dfb ldrb r3, [r7, #23]
|
|
8011c14: e000 b.n 8011c18 <USBD_LL_DataOutStage+0x170>
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8011c16: 2300 movs r3, #0
|
|
}
|
|
8011c18: 4618 mov r0, r3
|
|
8011c1a: 3718 adds r7, #24
|
|
8011c1c: 46bd mov sp, r7
|
|
8011c1e: bd80 pop {r7, pc}
|
|
|
|
08011c20 <USBD_LL_DataInStage>:
|
|
* @param pdata: data pointer
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
|
|
uint8_t epnum, uint8_t *pdata)
|
|
{
|
|
8011c20: b580 push {r7, lr}
|
|
8011c22: b086 sub sp, #24
|
|
8011c24: af00 add r7, sp, #0
|
|
8011c26: 60f8 str r0, [r7, #12]
|
|
8011c28: 460b mov r3, r1
|
|
8011c2a: 607a str r2, [r7, #4]
|
|
8011c2c: 72fb strb r3, [r7, #11]
|
|
USBD_StatusTypeDef ret;
|
|
uint8_t idx;
|
|
|
|
UNUSED(pdata);
|
|
|
|
if (epnum == 0U)
|
|
8011c2e: 7afb ldrb r3, [r7, #11]
|
|
8011c30: 2b00 cmp r3, #0
|
|
8011c32: d178 bne.n 8011d26 <USBD_LL_DataInStage+0x106>
|
|
{
|
|
pep = &pdev->ep_in[0];
|
|
8011c34: 68fb ldr r3, [r7, #12]
|
|
8011c36: 3314 adds r3, #20
|
|
8011c38: 613b str r3, [r7, #16]
|
|
|
|
if (pdev->ep0_state == USBD_EP0_DATA_IN)
|
|
8011c3a: 68fb ldr r3, [r7, #12]
|
|
8011c3c: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
|
|
8011c40: 2b02 cmp r3, #2
|
|
8011c42: d163 bne.n 8011d0c <USBD_LL_DataInStage+0xec>
|
|
{
|
|
if (pep->rem_length > pep->maxpacket)
|
|
8011c44: 693b ldr r3, [r7, #16]
|
|
8011c46: 685b ldr r3, [r3, #4]
|
|
8011c48: 693a ldr r2, [r7, #16]
|
|
8011c4a: 8992 ldrh r2, [r2, #12]
|
|
8011c4c: 4293 cmp r3, r2
|
|
8011c4e: d91c bls.n 8011c8a <USBD_LL_DataInStage+0x6a>
|
|
{
|
|
pep->rem_length -= pep->maxpacket;
|
|
8011c50: 693b ldr r3, [r7, #16]
|
|
8011c52: 685b ldr r3, [r3, #4]
|
|
8011c54: 693a ldr r2, [r7, #16]
|
|
8011c56: 8992 ldrh r2, [r2, #12]
|
|
8011c58: 1a9a subs r2, r3, r2
|
|
8011c5a: 693b ldr r3, [r7, #16]
|
|
8011c5c: 605a str r2, [r3, #4]
|
|
pep->pbuffer += pep->maxpacket;
|
|
8011c5e: 693b ldr r3, [r7, #16]
|
|
8011c60: 691b ldr r3, [r3, #16]
|
|
8011c62: 693a ldr r2, [r7, #16]
|
|
8011c64: 8992 ldrh r2, [r2, #12]
|
|
8011c66: 441a add r2, r3
|
|
8011c68: 693b ldr r3, [r7, #16]
|
|
8011c6a: 611a str r2, [r3, #16]
|
|
|
|
(void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length);
|
|
8011c6c: 693b ldr r3, [r7, #16]
|
|
8011c6e: 6919 ldr r1, [r3, #16]
|
|
8011c70: 693b ldr r3, [r7, #16]
|
|
8011c72: 685b ldr r3, [r3, #4]
|
|
8011c74: 461a mov r2, r3
|
|
8011c76: 68f8 ldr r0, [r7, #12]
|
|
8011c78: f001 f85c bl 8012d34 <USBD_CtlContinueSendData>
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8011c7c: 2300 movs r3, #0
|
|
8011c7e: 2200 movs r2, #0
|
|
8011c80: 2100 movs r1, #0
|
|
8011c82: 68f8 ldr r0, [r7, #12]
|
|
8011c84: f007 faa4 bl 80191d0 <USBD_LL_PrepareReceive>
|
|
8011c88: e040 b.n 8011d0c <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
/* last packet is MPS multiple, so send ZLP packet */
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
8011c8a: 693b ldr r3, [r7, #16]
|
|
8011c8c: 899b ldrh r3, [r3, #12]
|
|
8011c8e: 461a mov r2, r3
|
|
8011c90: 693b ldr r3, [r7, #16]
|
|
8011c92: 685b ldr r3, [r3, #4]
|
|
8011c94: 429a cmp r2, r3
|
|
8011c96: d11c bne.n 8011cd2 <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8011c98: 693b ldr r3, [r7, #16]
|
|
8011c9a: 681b ldr r3, [r3, #0]
|
|
8011c9c: 693a ldr r2, [r7, #16]
|
|
8011c9e: 8992 ldrh r2, [r2, #12]
|
|
if ((pep->maxpacket == pep->rem_length) &&
|
|
8011ca0: 4293 cmp r3, r2
|
|
8011ca2: d316 bcc.n 8011cd2 <USBD_LL_DataInStage+0xb2>
|
|
(pep->total_length < pdev->ep0_data_len))
|
|
8011ca4: 693b ldr r3, [r7, #16]
|
|
8011ca6: 681a ldr r2, [r3, #0]
|
|
8011ca8: 68fb ldr r3, [r7, #12]
|
|
8011caa: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
|
|
(pep->total_length >= pep->maxpacket) &&
|
|
8011cae: 429a cmp r2, r3
|
|
8011cb0: d20f bcs.n 8011cd2 <USBD_LL_DataInStage+0xb2>
|
|
{
|
|
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
|
|
8011cb2: 2200 movs r2, #0
|
|
8011cb4: 2100 movs r1, #0
|
|
8011cb6: 68f8 ldr r0, [r7, #12]
|
|
8011cb8: f001 f83c bl 8012d34 <USBD_CtlContinueSendData>
|
|
pdev->ep0_data_len = 0U;
|
|
8011cbc: 68fb ldr r3, [r7, #12]
|
|
8011cbe: 2200 movs r2, #0
|
|
8011cc0: f8c3 2298 str.w r2, [r3, #664] @ 0x298
|
|
|
|
/* Prepare endpoint for premature end of transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8011cc4: 2300 movs r3, #0
|
|
8011cc6: 2200 movs r2, #0
|
|
8011cc8: 2100 movs r1, #0
|
|
8011cca: 68f8 ldr r0, [r7, #12]
|
|
8011ccc: f007 fa80 bl 80191d0 <USBD_LL_PrepareReceive>
|
|
8011cd0: e01c b.n 8011d0c <USBD_LL_DataInStage+0xec>
|
|
}
|
|
else
|
|
{
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8011cd2: 68fb ldr r3, [r7, #12]
|
|
8011cd4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011cd8: b2db uxtb r3, r3
|
|
8011cda: 2b03 cmp r3, #3
|
|
8011cdc: d10f bne.n 8011cfe <USBD_LL_DataInStage+0xde>
|
|
{
|
|
if (pdev->pClass[0]->EP0_TxSent != NULL)
|
|
8011cde: 68fb ldr r3, [r7, #12]
|
|
8011ce0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8011ce4: 68db ldr r3, [r3, #12]
|
|
8011ce6: 2b00 cmp r3, #0
|
|
8011ce8: d009 beq.n 8011cfe <USBD_LL_DataInStage+0xde>
|
|
{
|
|
pdev->classId = 0U;
|
|
8011cea: 68fb ldr r3, [r7, #12]
|
|
8011cec: 2200 movs r2, #0
|
|
8011cee: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
pdev->pClass[0]->EP0_TxSent(pdev);
|
|
8011cf2: 68fb ldr r3, [r7, #12]
|
|
8011cf4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8011cf8: 68db ldr r3, [r3, #12]
|
|
8011cfa: 68f8 ldr r0, [r7, #12]
|
|
8011cfc: 4798 blx r3
|
|
}
|
|
}
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8011cfe: 2180 movs r1, #128 @ 0x80
|
|
8011d00: 68f8 ldr r0, [r7, #12]
|
|
8011d02: f007 f9bb bl 801907c <USBD_LL_StallEP>
|
|
(void)USBD_CtlReceiveStatus(pdev);
|
|
8011d06: 68f8 ldr r0, [r7, #12]
|
|
8011d08: f001 f86a bl 8012de0 <USBD_CtlReceiveStatus>
|
|
}
|
|
}
|
|
}
|
|
|
|
if (pdev->dev_test_mode != 0U)
|
|
8011d0c: 68fb ldr r3, [r7, #12]
|
|
8011d0e: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
|
|
8011d12: 2b00 cmp r3, #0
|
|
8011d14: d03a beq.n 8011d8c <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
(void)USBD_RunTestMode(pdev);
|
|
8011d16: 68f8 ldr r0, [r7, #12]
|
|
8011d18: f7ff fe30 bl 801197c <USBD_RunTestMode>
|
|
pdev->dev_test_mode = 0U;
|
|
8011d1c: 68fb ldr r3, [r7, #12]
|
|
8011d1e: 2200 movs r2, #0
|
|
8011d20: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
8011d24: e032 b.n 8011d8c <USBD_LL_DataInStage+0x16c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
|
|
8011d26: 7afb ldrb r3, [r7, #11]
|
|
8011d28: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8011d2c: b2db uxtb r3, r3
|
|
8011d2e: 4619 mov r1, r3
|
|
8011d30: 68f8 ldr r0, [r7, #12]
|
|
8011d32: f000 f8f4 bl 8011f1e <USBD_CoreFindEP>
|
|
8011d36: 4603 mov r3, r0
|
|
8011d38: 75fb strb r3, [r7, #23]
|
|
|
|
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8011d3a: 7dfb ldrb r3, [r7, #23]
|
|
8011d3c: 2bff cmp r3, #255 @ 0xff
|
|
8011d3e: d025 beq.n 8011d8c <USBD_LL_DataInStage+0x16c>
|
|
8011d40: 7dfb ldrb r3, [r7, #23]
|
|
8011d42: 2b00 cmp r3, #0
|
|
8011d44: d122 bne.n 8011d8c <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8011d46: 68fb ldr r3, [r7, #12]
|
|
8011d48: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011d4c: b2db uxtb r3, r3
|
|
8011d4e: 2b03 cmp r3, #3
|
|
8011d50: d11c bne.n 8011d8c <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
if (pdev->pClass[idx]->DataIn != NULL)
|
|
8011d52: 7dfa ldrb r2, [r7, #23]
|
|
8011d54: 68fb ldr r3, [r7, #12]
|
|
8011d56: 32ae adds r2, #174 @ 0xae
|
|
8011d58: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011d5c: 695b ldr r3, [r3, #20]
|
|
8011d5e: 2b00 cmp r3, #0
|
|
8011d60: d014 beq.n 8011d8c <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
pdev->classId = idx;
|
|
8011d62: 7dfa ldrb r2, [r7, #23]
|
|
8011d64: 68fb ldr r3, [r7, #12]
|
|
8011d66: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
|
|
8011d6a: 7dfa ldrb r2, [r7, #23]
|
|
8011d6c: 68fb ldr r3, [r7, #12]
|
|
8011d6e: 32ae adds r2, #174 @ 0xae
|
|
8011d70: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8011d74: 695b ldr r3, [r3, #20]
|
|
8011d76: 7afa ldrb r2, [r7, #11]
|
|
8011d78: 4611 mov r1, r2
|
|
8011d7a: 68f8 ldr r0, [r7, #12]
|
|
8011d7c: 4798 blx r3
|
|
8011d7e: 4603 mov r3, r0
|
|
8011d80: 75bb strb r3, [r7, #22]
|
|
|
|
if (ret != USBD_OK)
|
|
8011d82: 7dbb ldrb r3, [r7, #22]
|
|
8011d84: 2b00 cmp r3, #0
|
|
8011d86: d001 beq.n 8011d8c <USBD_LL_DataInStage+0x16c>
|
|
{
|
|
return ret;
|
|
8011d88: 7dbb ldrb r3, [r7, #22]
|
|
8011d8a: e000 b.n 8011d8e <USBD_LL_DataInStage+0x16e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return USBD_OK;
|
|
8011d8c: 2300 movs r3, #0
|
|
}
|
|
8011d8e: 4618 mov r0, r3
|
|
8011d90: 3718 adds r7, #24
|
|
8011d92: 46bd mov sp, r7
|
|
8011d94: bd80 pop {r7, pc}
|
|
|
|
08011d96 <USBD_LL_Reset>:
|
|
* Handle Reset event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8011d96: b580 push {r7, lr}
|
|
8011d98: b084 sub sp, #16
|
|
8011d9a: af00 add r7, sp, #0
|
|
8011d9c: 6078 str r0, [r7, #4]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
8011d9e: 2300 movs r3, #0
|
|
8011da0: 73fb strb r3, [r7, #15]
|
|
|
|
/* Upon Reset call user call back */
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
8011da2: 687b ldr r3, [r7, #4]
|
|
8011da4: 2201 movs r2, #1
|
|
8011da6: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->ep0_state = USBD_EP0_IDLE;
|
|
8011daa: 687b ldr r3, [r7, #4]
|
|
8011dac: 2200 movs r2, #0
|
|
8011dae: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->dev_config = 0U;
|
|
8011db2: 687b ldr r3, [r7, #4]
|
|
8011db4: 2200 movs r2, #0
|
|
8011db6: 605a str r2, [r3, #4]
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8011db8: 687b ldr r3, [r7, #4]
|
|
8011dba: 2200 movs r2, #0
|
|
8011dbc: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
pdev->dev_test_mode = 0U;
|
|
8011dc0: 687b ldr r3, [r7, #4]
|
|
8011dc2: 2200 movs r2, #0
|
|
8011dc4: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
|
|
if (pdev->pClass[0] != NULL)
|
|
8011dc8: 687b ldr r3, [r7, #4]
|
|
8011dca: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8011dce: 2b00 cmp r3, #0
|
|
8011dd0: d014 beq.n 8011dfc <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit != NULL)
|
|
8011dd2: 687b ldr r3, [r7, #4]
|
|
8011dd4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8011dd8: 685b ldr r3, [r3, #4]
|
|
8011dda: 2b00 cmp r3, #0
|
|
8011ddc: d00e beq.n 8011dfc <USBD_LL_Reset+0x66>
|
|
{
|
|
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
|
|
8011dde: 687b ldr r3, [r7, #4]
|
|
8011de0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8011de4: 685b ldr r3, [r3, #4]
|
|
8011de6: 687a ldr r2, [r7, #4]
|
|
8011de8: 6852 ldr r2, [r2, #4]
|
|
8011dea: b2d2 uxtb r2, r2
|
|
8011dec: 4611 mov r1, r2
|
|
8011dee: 6878 ldr r0, [r7, #4]
|
|
8011df0: 4798 blx r3
|
|
8011df2: 4603 mov r3, r0
|
|
8011df4: 2b00 cmp r3, #0
|
|
8011df6: d001 beq.n 8011dfc <USBD_LL_Reset+0x66>
|
|
{
|
|
ret = USBD_FAIL;
|
|
8011df8: 2303 movs r3, #3
|
|
8011dfa: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
|
|
/* Open EP0 OUT */
|
|
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8011dfc: 2340 movs r3, #64 @ 0x40
|
|
8011dfe: 2200 movs r2, #0
|
|
8011e00: 2100 movs r1, #0
|
|
8011e02: 6878 ldr r0, [r7, #4]
|
|
8011e04: f007 f8f5 bl 8018ff2 <USBD_LL_OpenEP>
|
|
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
|
|
8011e08: 687b ldr r3, [r7, #4]
|
|
8011e0a: 2201 movs r2, #1
|
|
8011e0c: f883 2163 strb.w r2, [r3, #355] @ 0x163
|
|
|
|
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8011e10: 687b ldr r3, [r7, #4]
|
|
8011e12: 2240 movs r2, #64 @ 0x40
|
|
8011e14: f8a3 2160 strh.w r2, [r3, #352] @ 0x160
|
|
|
|
/* Open EP0 IN */
|
|
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
|
|
8011e18: 2340 movs r3, #64 @ 0x40
|
|
8011e1a: 2200 movs r2, #0
|
|
8011e1c: 2180 movs r1, #128 @ 0x80
|
|
8011e1e: 6878 ldr r0, [r7, #4]
|
|
8011e20: f007 f8e7 bl 8018ff2 <USBD_LL_OpenEP>
|
|
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
|
|
8011e24: 687b ldr r3, [r7, #4]
|
|
8011e26: 2201 movs r2, #1
|
|
8011e28: f883 2023 strb.w r2, [r3, #35] @ 0x23
|
|
|
|
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
|
|
8011e2c: 687b ldr r3, [r7, #4]
|
|
8011e2e: 2240 movs r2, #64 @ 0x40
|
|
8011e30: 841a strh r2, [r3, #32]
|
|
|
|
return ret;
|
|
8011e32: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8011e34: 4618 mov r0, r3
|
|
8011e36: 3710 adds r7, #16
|
|
8011e38: 46bd mov sp, r7
|
|
8011e3a: bd80 pop {r7, pc}
|
|
|
|
08011e3c <USBD_LL_SetSpeed>:
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
|
|
USBD_SpeedTypeDef speed)
|
|
{
|
|
8011e3c: b480 push {r7}
|
|
8011e3e: b083 sub sp, #12
|
|
8011e40: af00 add r7, sp, #0
|
|
8011e42: 6078 str r0, [r7, #4]
|
|
8011e44: 460b mov r3, r1
|
|
8011e46: 70fb strb r3, [r7, #3]
|
|
pdev->dev_speed = speed;
|
|
8011e48: 687b ldr r3, [r7, #4]
|
|
8011e4a: 78fa ldrb r2, [r7, #3]
|
|
8011e4c: 741a strb r2, [r3, #16]
|
|
|
|
return USBD_OK;
|
|
8011e4e: 2300 movs r3, #0
|
|
}
|
|
8011e50: 4618 mov r0, r3
|
|
8011e52: 370c adds r7, #12
|
|
8011e54: 46bd mov sp, r7
|
|
8011e56: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011e5a: 4770 bx lr
|
|
|
|
08011e5c <USBD_LL_Suspend>:
|
|
* Handle Suspend event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8011e5c: b480 push {r7}
|
|
8011e5e: b083 sub sp, #12
|
|
8011e60: af00 add r7, sp, #0
|
|
8011e62: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state != USBD_STATE_SUSPENDED)
|
|
8011e64: 687b ldr r3, [r7, #4]
|
|
8011e66: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011e6a: b2db uxtb r3, r3
|
|
8011e6c: 2b04 cmp r3, #4
|
|
8011e6e: d006 beq.n 8011e7e <USBD_LL_Suspend+0x22>
|
|
{
|
|
pdev->dev_old_state = pdev->dev_state;
|
|
8011e70: 687b ldr r3, [r7, #4]
|
|
8011e72: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011e76: b2da uxtb r2, r3
|
|
8011e78: 687b ldr r3, [r7, #4]
|
|
8011e7a: f883 229d strb.w r2, [r3, #669] @ 0x29d
|
|
}
|
|
|
|
pdev->dev_state = USBD_STATE_SUSPENDED;
|
|
8011e7e: 687b ldr r3, [r7, #4]
|
|
8011e80: 2204 movs r2, #4
|
|
8011e82: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
|
|
return USBD_OK;
|
|
8011e86: 2300 movs r3, #0
|
|
}
|
|
8011e88: 4618 mov r0, r3
|
|
8011e8a: 370c adds r7, #12
|
|
8011e8c: 46bd mov sp, r7
|
|
8011e8e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011e92: 4770 bx lr
|
|
|
|
08011e94 <USBD_LL_Resume>:
|
|
* Handle Resume event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8011e94: b480 push {r7}
|
|
8011e96: b083 sub sp, #12
|
|
8011e98: af00 add r7, sp, #0
|
|
8011e9a: 6078 str r0, [r7, #4]
|
|
if (pdev->dev_state == USBD_STATE_SUSPENDED)
|
|
8011e9c: 687b ldr r3, [r7, #4]
|
|
8011e9e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011ea2: b2db uxtb r3, r3
|
|
8011ea4: 2b04 cmp r3, #4
|
|
8011ea6: d106 bne.n 8011eb6 <USBD_LL_Resume+0x22>
|
|
{
|
|
pdev->dev_state = pdev->dev_old_state;
|
|
8011ea8: 687b ldr r3, [r7, #4]
|
|
8011eaa: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
|
|
8011eae: b2da uxtb r2, r3
|
|
8011eb0: 687b ldr r3, [r7, #4]
|
|
8011eb2: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
|
|
return USBD_OK;
|
|
8011eb6: 2300 movs r3, #0
|
|
}
|
|
8011eb8: 4618 mov r0, r3
|
|
8011eba: 370c adds r7, #12
|
|
8011ebc: 46bd mov sp, r7
|
|
8011ebe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011ec2: 4770 bx lr
|
|
|
|
08011ec4 <USBD_LL_SOF>:
|
|
* Handle SOF event
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8011ec4: b580 push {r7, lr}
|
|
8011ec6: b082 sub sp, #8
|
|
8011ec8: af00 add r7, sp, #0
|
|
8011eca: 6078 str r0, [r7, #4]
|
|
/* The SOF event can be distributed for all classes that support it */
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8011ecc: 687b ldr r3, [r7, #4]
|
|
8011ece: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8011ed2: b2db uxtb r3, r3
|
|
8011ed4: 2b03 cmp r3, #3
|
|
8011ed6: d110 bne.n 8011efa <USBD_LL_SOF+0x36>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (pdev->pClass[0] != NULL)
|
|
8011ed8: 687b ldr r3, [r7, #4]
|
|
8011eda: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8011ede: 2b00 cmp r3, #0
|
|
8011ee0: d00b beq.n 8011efa <USBD_LL_SOF+0x36>
|
|
{
|
|
if (pdev->pClass[0]->SOF != NULL)
|
|
8011ee2: 687b ldr r3, [r7, #4]
|
|
8011ee4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8011ee8: 69db ldr r3, [r3, #28]
|
|
8011eea: 2b00 cmp r3, #0
|
|
8011eec: d005 beq.n 8011efa <USBD_LL_SOF+0x36>
|
|
{
|
|
(void)pdev->pClass[0]->SOF(pdev);
|
|
8011eee: 687b ldr r3, [r7, #4]
|
|
8011ef0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8011ef4: 69db ldr r3, [r3, #28]
|
|
8011ef6: 6878 ldr r0, [r7, #4]
|
|
8011ef8: 4798 blx r3
|
|
}
|
|
}
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
|
|
return USBD_OK;
|
|
8011efa: 2300 movs r3, #0
|
|
}
|
|
8011efc: 4618 mov r0, r3
|
|
8011efe: 3708 adds r7, #8
|
|
8011f00: 46bd mov sp, r7
|
|
8011f02: bd80 pop {r7, pc}
|
|
|
|
08011f04 <USBD_CoreFindIF>:
|
|
* @param pdev: device instance
|
|
* @param index : selected interface number
|
|
* @retval index of the class using the selected interface number. OxFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8011f04: b480 push {r7}
|
|
8011f06: b083 sub sp, #12
|
|
8011f08: af00 add r7, sp, #0
|
|
8011f0a: 6078 str r0, [r7, #4]
|
|
8011f0c: 460b mov r3, r1
|
|
8011f0e: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8011f10: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8011f12: 4618 mov r0, r3
|
|
8011f14: 370c adds r7, #12
|
|
8011f16: 46bd mov sp, r7
|
|
8011f18: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011f1c: 4770 bx lr
|
|
|
|
08011f1e <USBD_CoreFindEP>:
|
|
* @param pdev: device instance
|
|
* @param index : selected endpoint number
|
|
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
|
|
*/
|
|
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
|
|
{
|
|
8011f1e: b480 push {r7}
|
|
8011f20: b083 sub sp, #12
|
|
8011f22: af00 add r7, sp, #0
|
|
8011f24: 6078 str r0, [r7, #4]
|
|
8011f26: 460b mov r3, r1
|
|
8011f28: 70fb strb r3, [r7, #3]
|
|
return 0xFFU;
|
|
#else
|
|
UNUSED(pdev);
|
|
UNUSED(index);
|
|
|
|
return 0x00U;
|
|
8011f2a: 2300 movs r3, #0
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
}
|
|
8011f2c: 4618 mov r0, r3
|
|
8011f2e: 370c adds r7, #12
|
|
8011f30: 46bd mov sp, r7
|
|
8011f32: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011f36: 4770 bx lr
|
|
|
|
08011f38 <USBD_GetEpDesc>:
|
|
* @param pConfDesc: pointer to Bos descriptor
|
|
* @param EpAddr: endpoint address
|
|
* @retval pointer to video endpoint descriptor
|
|
*/
|
|
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr)
|
|
{
|
|
8011f38: b580 push {r7, lr}
|
|
8011f3a: b086 sub sp, #24
|
|
8011f3c: af00 add r7, sp, #0
|
|
8011f3e: 6078 str r0, [r7, #4]
|
|
8011f40: 460b mov r3, r1
|
|
8011f42: 70fb strb r3, [r7, #3]
|
|
USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc;
|
|
8011f44: 687b ldr r3, [r7, #4]
|
|
8011f46: 617b str r3, [r7, #20]
|
|
USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc;
|
|
8011f48: 687b ldr r3, [r7, #4]
|
|
8011f4a: 60fb str r3, [r7, #12]
|
|
USBD_EpDescTypeDef *pEpDesc = NULL;
|
|
8011f4c: 2300 movs r3, #0
|
|
8011f4e: 613b str r3, [r7, #16]
|
|
uint16_t ptr;
|
|
|
|
if (desc->wTotalLength > desc->bLength)
|
|
8011f50: 68fb ldr r3, [r7, #12]
|
|
8011f52: 885b ldrh r3, [r3, #2]
|
|
8011f54: b29b uxth r3, r3
|
|
8011f56: 68fa ldr r2, [r7, #12]
|
|
8011f58: 7812 ldrb r2, [r2, #0]
|
|
8011f5a: 4293 cmp r3, r2
|
|
8011f5c: d91f bls.n 8011f9e <USBD_GetEpDesc+0x66>
|
|
{
|
|
ptr = desc->bLength;
|
|
8011f5e: 68fb ldr r3, [r7, #12]
|
|
8011f60: 781b ldrb r3, [r3, #0]
|
|
8011f62: 817b strh r3, [r7, #10]
|
|
|
|
while (ptr < desc->wTotalLength)
|
|
8011f64: e013 b.n 8011f8e <USBD_GetEpDesc+0x56>
|
|
{
|
|
pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr);
|
|
8011f66: f107 030a add.w r3, r7, #10
|
|
8011f6a: 4619 mov r1, r3
|
|
8011f6c: 6978 ldr r0, [r7, #20]
|
|
8011f6e: f000 f81b bl 8011fa8 <USBD_GetNextDesc>
|
|
8011f72: 6178 str r0, [r7, #20]
|
|
|
|
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
|
|
8011f74: 697b ldr r3, [r7, #20]
|
|
8011f76: 785b ldrb r3, [r3, #1]
|
|
8011f78: 2b05 cmp r3, #5
|
|
8011f7a: d108 bne.n 8011f8e <USBD_GetEpDesc+0x56>
|
|
{
|
|
pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc;
|
|
8011f7c: 697b ldr r3, [r7, #20]
|
|
8011f7e: 613b str r3, [r7, #16]
|
|
|
|
if (pEpDesc->bEndpointAddress == EpAddr)
|
|
8011f80: 693b ldr r3, [r7, #16]
|
|
8011f82: 789b ldrb r3, [r3, #2]
|
|
8011f84: 78fa ldrb r2, [r7, #3]
|
|
8011f86: 429a cmp r2, r3
|
|
8011f88: d008 beq.n 8011f9c <USBD_GetEpDesc+0x64>
|
|
{
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
pEpDesc = NULL;
|
|
8011f8a: 2300 movs r3, #0
|
|
8011f8c: 613b str r3, [r7, #16]
|
|
while (ptr < desc->wTotalLength)
|
|
8011f8e: 68fb ldr r3, [r7, #12]
|
|
8011f90: 885b ldrh r3, [r3, #2]
|
|
8011f92: b29a uxth r2, r3
|
|
8011f94: 897b ldrh r3, [r7, #10]
|
|
8011f96: 429a cmp r2, r3
|
|
8011f98: d8e5 bhi.n 8011f66 <USBD_GetEpDesc+0x2e>
|
|
8011f9a: e000 b.n 8011f9e <USBD_GetEpDesc+0x66>
|
|
break;
|
|
8011f9c: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return (void *)pEpDesc;
|
|
8011f9e: 693b ldr r3, [r7, #16]
|
|
}
|
|
8011fa0: 4618 mov r0, r3
|
|
8011fa2: 3718 adds r7, #24
|
|
8011fa4: 46bd mov sp, r7
|
|
8011fa6: bd80 pop {r7, pc}
|
|
|
|
08011fa8 <USBD_GetNextDesc>:
|
|
* @param buf: Buffer where the descriptor is available
|
|
* @param ptr: data pointer inside the descriptor
|
|
* @retval next header
|
|
*/
|
|
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
|
|
{
|
|
8011fa8: b480 push {r7}
|
|
8011faa: b085 sub sp, #20
|
|
8011fac: af00 add r7, sp, #0
|
|
8011fae: 6078 str r0, [r7, #4]
|
|
8011fb0: 6039 str r1, [r7, #0]
|
|
USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf;
|
|
8011fb2: 687b ldr r3, [r7, #4]
|
|
8011fb4: 60fb str r3, [r7, #12]
|
|
|
|
*ptr += pnext->bLength;
|
|
8011fb6: 683b ldr r3, [r7, #0]
|
|
8011fb8: 881b ldrh r3, [r3, #0]
|
|
8011fba: 68fa ldr r2, [r7, #12]
|
|
8011fbc: 7812 ldrb r2, [r2, #0]
|
|
8011fbe: 4413 add r3, r2
|
|
8011fc0: b29a uxth r2, r3
|
|
8011fc2: 683b ldr r3, [r7, #0]
|
|
8011fc4: 801a strh r2, [r3, #0]
|
|
pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength);
|
|
8011fc6: 68fb ldr r3, [r7, #12]
|
|
8011fc8: 781b ldrb r3, [r3, #0]
|
|
8011fca: 461a mov r2, r3
|
|
8011fcc: 687b ldr r3, [r7, #4]
|
|
8011fce: 4413 add r3, r2
|
|
8011fd0: 60fb str r3, [r7, #12]
|
|
|
|
return (pnext);
|
|
8011fd2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8011fd4: 4618 mov r0, r3
|
|
8011fd6: 3714 adds r7, #20
|
|
8011fd8: 46bd mov sp, r7
|
|
8011fda: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011fde: 4770 bx lr
|
|
|
|
08011fe0 <SWAPBYTE>:
|
|
|
|
/** @defgroup USBD_DEF_Exported_Macros
|
|
* @{
|
|
*/
|
|
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
|
|
{
|
|
8011fe0: b480 push {r7}
|
|
8011fe2: b087 sub sp, #28
|
|
8011fe4: af00 add r7, sp, #0
|
|
8011fe6: 6078 str r0, [r7, #4]
|
|
uint16_t _SwapVal;
|
|
uint16_t _Byte1;
|
|
uint16_t _Byte2;
|
|
uint8_t *_pbuff = addr;
|
|
8011fe8: 687b ldr r3, [r7, #4]
|
|
8011fea: 617b str r3, [r7, #20]
|
|
|
|
_Byte1 = *(uint8_t *)_pbuff;
|
|
8011fec: 697b ldr r3, [r7, #20]
|
|
8011fee: 781b ldrb r3, [r3, #0]
|
|
8011ff0: 827b strh r3, [r7, #18]
|
|
_pbuff++;
|
|
8011ff2: 697b ldr r3, [r7, #20]
|
|
8011ff4: 3301 adds r3, #1
|
|
8011ff6: 617b str r3, [r7, #20]
|
|
_Byte2 = *(uint8_t *)_pbuff;
|
|
8011ff8: 697b ldr r3, [r7, #20]
|
|
8011ffa: 781b ldrb r3, [r3, #0]
|
|
8011ffc: 823b strh r3, [r7, #16]
|
|
|
|
_SwapVal = (_Byte2 << 8) | _Byte1;
|
|
8011ffe: f9b7 3010 ldrsh.w r3, [r7, #16]
|
|
8012002: 021b lsls r3, r3, #8
|
|
8012004: b21a sxth r2, r3
|
|
8012006: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
801200a: 4313 orrs r3, r2
|
|
801200c: b21b sxth r3, r3
|
|
801200e: 81fb strh r3, [r7, #14]
|
|
|
|
return _SwapVal;
|
|
8012010: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
8012012: 4618 mov r0, r3
|
|
8012014: 371c adds r7, #28
|
|
8012016: 46bd mov sp, r7
|
|
8012018: f85d 7b04 ldr.w r7, [sp], #4
|
|
801201c: 4770 bx lr
|
|
...
|
|
|
|
08012020 <USBD_StdDevReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8012020: b580 push {r7, lr}
|
|
8012022: b084 sub sp, #16
|
|
8012024: af00 add r7, sp, #0
|
|
8012026: 6078 str r0, [r7, #4]
|
|
8012028: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
801202a: 2300 movs r3, #0
|
|
801202c: 73fb strb r3, [r7, #15]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
801202e: 683b ldr r3, [r7, #0]
|
|
8012030: 781b ldrb r3, [r3, #0]
|
|
8012032: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
8012036: 2b40 cmp r3, #64 @ 0x40
|
|
8012038: d005 beq.n 8012046 <USBD_StdDevReq+0x26>
|
|
801203a: 2b40 cmp r3, #64 @ 0x40
|
|
801203c: d857 bhi.n 80120ee <USBD_StdDevReq+0xce>
|
|
801203e: 2b00 cmp r3, #0
|
|
8012040: d00f beq.n 8012062 <USBD_StdDevReq+0x42>
|
|
8012042: 2b20 cmp r3, #32
|
|
8012044: d153 bne.n 80120ee <USBD_StdDevReq+0xce>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
|
|
8012046: 687b ldr r3, [r7, #4]
|
|
8012048: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
|
|
801204c: 687b ldr r3, [r7, #4]
|
|
801204e: 32ae adds r2, #174 @ 0xae
|
|
8012050: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8012054: 689b ldr r3, [r3, #8]
|
|
8012056: 6839 ldr r1, [r7, #0]
|
|
8012058: 6878 ldr r0, [r7, #4]
|
|
801205a: 4798 blx r3
|
|
801205c: 4603 mov r3, r0
|
|
801205e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8012060: e04a b.n 80120f8 <USBD_StdDevReq+0xd8>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
8012062: 683b ldr r3, [r7, #0]
|
|
8012064: 785b ldrb r3, [r3, #1]
|
|
8012066: 2b09 cmp r3, #9
|
|
8012068: d83b bhi.n 80120e2 <USBD_StdDevReq+0xc2>
|
|
801206a: a201 add r2, pc, #4 @ (adr r2, 8012070 <USBD_StdDevReq+0x50>)
|
|
801206c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8012070: 080120c5 .word 0x080120c5
|
|
8012074: 080120d9 .word 0x080120d9
|
|
8012078: 080120e3 .word 0x080120e3
|
|
801207c: 080120cf .word 0x080120cf
|
|
8012080: 080120e3 .word 0x080120e3
|
|
8012084: 080120a3 .word 0x080120a3
|
|
8012088: 08012099 .word 0x08012099
|
|
801208c: 080120e3 .word 0x080120e3
|
|
8012090: 080120bb .word 0x080120bb
|
|
8012094: 080120ad .word 0x080120ad
|
|
{
|
|
case USB_REQ_GET_DESCRIPTOR:
|
|
USBD_GetDescriptor(pdev, req);
|
|
8012098: 6839 ldr r1, [r7, #0]
|
|
801209a: 6878 ldr r0, [r7, #4]
|
|
801209c: f000 fa3e bl 801251c <USBD_GetDescriptor>
|
|
break;
|
|
80120a0: e024 b.n 80120ec <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
USBD_SetAddress(pdev, req);
|
|
80120a2: 6839 ldr r1, [r7, #0]
|
|
80120a4: 6878 ldr r0, [r7, #4]
|
|
80120a6: f000 fbcd bl 8012844 <USBD_SetAddress>
|
|
break;
|
|
80120aa: e01f b.n 80120ec <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
ret = USBD_SetConfig(pdev, req);
|
|
80120ac: 6839 ldr r1, [r7, #0]
|
|
80120ae: 6878 ldr r0, [r7, #4]
|
|
80120b0: f000 fc0c bl 80128cc <USBD_SetConfig>
|
|
80120b4: 4603 mov r3, r0
|
|
80120b6: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80120b8: e018 b.n 80120ec <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_CONFIGURATION:
|
|
USBD_GetConfig(pdev, req);
|
|
80120ba: 6839 ldr r1, [r7, #0]
|
|
80120bc: 6878 ldr r0, [r7, #4]
|
|
80120be: f000 fcaf bl 8012a20 <USBD_GetConfig>
|
|
break;
|
|
80120c2: e013 b.n 80120ec <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
USBD_GetStatus(pdev, req);
|
|
80120c4: 6839 ldr r1, [r7, #0]
|
|
80120c6: 6878 ldr r0, [r7, #4]
|
|
80120c8: f000 fce0 bl 8012a8c <USBD_GetStatus>
|
|
break;
|
|
80120cc: e00e b.n 80120ec <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
USBD_SetFeature(pdev, req);
|
|
80120ce: 6839 ldr r1, [r7, #0]
|
|
80120d0: 6878 ldr r0, [r7, #4]
|
|
80120d2: f000 fd0f bl 8012af4 <USBD_SetFeature>
|
|
break;
|
|
80120d6: e009 b.n 80120ec <USBD_StdDevReq+0xcc>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
USBD_ClrFeature(pdev, req);
|
|
80120d8: 6839 ldr r1, [r7, #0]
|
|
80120da: 6878 ldr r0, [r7, #4]
|
|
80120dc: f000 fd33 bl 8012b46 <USBD_ClrFeature>
|
|
break;
|
|
80120e0: e004 b.n 80120ec <USBD_StdDevReq+0xcc>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80120e2: 6839 ldr r1, [r7, #0]
|
|
80120e4: 6878 ldr r0, [r7, #4]
|
|
80120e6: f000 fd8a bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80120ea: bf00 nop
|
|
}
|
|
break;
|
|
80120ec: e004 b.n 80120f8 <USBD_StdDevReq+0xd8>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80120ee: 6839 ldr r1, [r7, #0]
|
|
80120f0: 6878 ldr r0, [r7, #4]
|
|
80120f2: f000 fd84 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80120f6: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
80120f8: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80120fa: 4618 mov r0, r3
|
|
80120fc: 3710 adds r7, #16
|
|
80120fe: 46bd mov sp, r7
|
|
8012100: bd80 pop {r7, pc}
|
|
8012102: bf00 nop
|
|
|
|
08012104 <USBD_StdItfReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8012104: b580 push {r7, lr}
|
|
8012106: b084 sub sp, #16
|
|
8012108: af00 add r7, sp, #0
|
|
801210a: 6078 str r0, [r7, #4]
|
|
801210c: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
801210e: 2300 movs r3, #0
|
|
8012110: 73fb strb r3, [r7, #15]
|
|
uint8_t idx;
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
8012112: 683b ldr r3, [r7, #0]
|
|
8012114: 781b ldrb r3, [r3, #0]
|
|
8012116: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
801211a: 2b40 cmp r3, #64 @ 0x40
|
|
801211c: d005 beq.n 801212a <USBD_StdItfReq+0x26>
|
|
801211e: 2b40 cmp r3, #64 @ 0x40
|
|
8012120: d852 bhi.n 80121c8 <USBD_StdItfReq+0xc4>
|
|
8012122: 2b00 cmp r3, #0
|
|
8012124: d001 beq.n 801212a <USBD_StdItfReq+0x26>
|
|
8012126: 2b20 cmp r3, #32
|
|
8012128: d14e bne.n 80121c8 <USBD_StdItfReq+0xc4>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (pdev->dev_state)
|
|
801212a: 687b ldr r3, [r7, #4]
|
|
801212c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8012130: b2db uxtb r3, r3
|
|
8012132: 3b01 subs r3, #1
|
|
8012134: 2b02 cmp r3, #2
|
|
8012136: d840 bhi.n 80121ba <USBD_StdItfReq+0xb6>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
|
|
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
|
|
8012138: 683b ldr r3, [r7, #0]
|
|
801213a: 889b ldrh r3, [r3, #4]
|
|
801213c: b2db uxtb r3, r3
|
|
801213e: 2b01 cmp r3, #1
|
|
8012140: d836 bhi.n 80121b0 <USBD_StdItfReq+0xac>
|
|
{
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
|
|
8012142: 683b ldr r3, [r7, #0]
|
|
8012144: 889b ldrh r3, [r3, #4]
|
|
8012146: b2db uxtb r3, r3
|
|
8012148: 4619 mov r1, r3
|
|
801214a: 6878 ldr r0, [r7, #4]
|
|
801214c: f7ff feda bl 8011f04 <USBD_CoreFindIF>
|
|
8012150: 4603 mov r3, r0
|
|
8012152: 73bb strb r3, [r7, #14]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
8012154: 7bbb ldrb r3, [r7, #14]
|
|
8012156: 2bff cmp r3, #255 @ 0xff
|
|
8012158: d01d beq.n 8012196 <USBD_StdItfReq+0x92>
|
|
801215a: 7bbb ldrb r3, [r7, #14]
|
|
801215c: 2b00 cmp r3, #0
|
|
801215e: d11a bne.n 8012196 <USBD_StdItfReq+0x92>
|
|
{
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8012160: 7bba ldrb r2, [r7, #14]
|
|
8012162: 687b ldr r3, [r7, #4]
|
|
8012164: 32ae adds r2, #174 @ 0xae
|
|
8012166: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
801216a: 689b ldr r3, [r3, #8]
|
|
801216c: 2b00 cmp r3, #0
|
|
801216e: d00f beq.n 8012190 <USBD_StdItfReq+0x8c>
|
|
{
|
|
pdev->classId = idx;
|
|
8012170: 7bba ldrb r2, [r7, #14]
|
|
8012172: 687b ldr r3, [r7, #4]
|
|
8012174: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8012178: 7bba ldrb r2, [r7, #14]
|
|
801217a: 687b ldr r3, [r7, #4]
|
|
801217c: 32ae adds r2, #174 @ 0xae
|
|
801217e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8012182: 689b ldr r3, [r3, #8]
|
|
8012184: 6839 ldr r1, [r7, #0]
|
|
8012186: 6878 ldr r0, [r7, #4]
|
|
8012188: 4798 blx r3
|
|
801218a: 4603 mov r3, r0
|
|
801218c: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
801218e: e004 b.n 801219a <USBD_StdItfReq+0x96>
|
|
}
|
|
else
|
|
{
|
|
/* should never reach this condition */
|
|
ret = USBD_FAIL;
|
|
8012190: 2303 movs r3, #3
|
|
8012192: 73fb strb r3, [r7, #15]
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8012194: e001 b.n 801219a <USBD_StdItfReq+0x96>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* No relative interface found */
|
|
ret = USBD_FAIL;
|
|
8012196: 2303 movs r3, #3
|
|
8012198: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
if ((req->wLength == 0U) && (ret == USBD_OK))
|
|
801219a: 683b ldr r3, [r7, #0]
|
|
801219c: 88db ldrh r3, [r3, #6]
|
|
801219e: 2b00 cmp r3, #0
|
|
80121a0: d110 bne.n 80121c4 <USBD_StdItfReq+0xc0>
|
|
80121a2: 7bfb ldrb r3, [r7, #15]
|
|
80121a4: 2b00 cmp r3, #0
|
|
80121a6: d10d bne.n 80121c4 <USBD_StdItfReq+0xc0>
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80121a8: 6878 ldr r0, [r7, #4]
|
|
80121aa: f000 fe06 bl 8012dba <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
80121ae: e009 b.n 80121c4 <USBD_StdItfReq+0xc0>
|
|
USBD_CtlError(pdev, req);
|
|
80121b0: 6839 ldr r1, [r7, #0]
|
|
80121b2: 6878 ldr r0, [r7, #4]
|
|
80121b4: f000 fd23 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80121b8: e004 b.n 80121c4 <USBD_StdItfReq+0xc0>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80121ba: 6839 ldr r1, [r7, #0]
|
|
80121bc: 6878 ldr r0, [r7, #4]
|
|
80121be: f000 fd1e bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80121c2: e000 b.n 80121c6 <USBD_StdItfReq+0xc2>
|
|
break;
|
|
80121c4: bf00 nop
|
|
}
|
|
break;
|
|
80121c6: e004 b.n 80121d2 <USBD_StdItfReq+0xce>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80121c8: 6839 ldr r1, [r7, #0]
|
|
80121ca: 6878 ldr r0, [r7, #4]
|
|
80121cc: f000 fd17 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80121d0: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
80121d2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80121d4: 4618 mov r0, r3
|
|
80121d6: 3710 adds r7, #16
|
|
80121d8: 46bd mov sp, r7
|
|
80121da: bd80 pop {r7, pc}
|
|
|
|
080121dc <USBD_StdEPReq>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80121dc: b580 push {r7, lr}
|
|
80121de: b084 sub sp, #16
|
|
80121e0: af00 add r7, sp, #0
|
|
80121e2: 6078 str r0, [r7, #4]
|
|
80121e4: 6039 str r1, [r7, #0]
|
|
USBD_EndpointTypeDef *pep;
|
|
uint8_t ep_addr;
|
|
uint8_t idx;
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80121e6: 2300 movs r3, #0
|
|
80121e8: 73fb strb r3, [r7, #15]
|
|
|
|
ep_addr = LOBYTE(req->wIndex);
|
|
80121ea: 683b ldr r3, [r7, #0]
|
|
80121ec: 889b ldrh r3, [r3, #4]
|
|
80121ee: 73bb strb r3, [r7, #14]
|
|
|
|
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
|
80121f0: 683b ldr r3, [r7, #0]
|
|
80121f2: 781b ldrb r3, [r3, #0]
|
|
80121f4: f003 0360 and.w r3, r3, #96 @ 0x60
|
|
80121f8: 2b40 cmp r3, #64 @ 0x40
|
|
80121fa: d007 beq.n 801220c <USBD_StdEPReq+0x30>
|
|
80121fc: 2b40 cmp r3, #64 @ 0x40
|
|
80121fe: f200 8181 bhi.w 8012504 <USBD_StdEPReq+0x328>
|
|
8012202: 2b00 cmp r3, #0
|
|
8012204: d02a beq.n 801225c <USBD_StdEPReq+0x80>
|
|
8012206: 2b20 cmp r3, #32
|
|
8012208: f040 817c bne.w 8012504 <USBD_StdEPReq+0x328>
|
|
{
|
|
case USB_REQ_TYPE_CLASS:
|
|
case USB_REQ_TYPE_VENDOR:
|
|
/* Get the class index relative to this endpoint */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
801220c: 7bbb ldrb r3, [r7, #14]
|
|
801220e: 4619 mov r1, r3
|
|
8012210: 6878 ldr r0, [r7, #4]
|
|
8012212: f7ff fe84 bl 8011f1e <USBD_CoreFindEP>
|
|
8012216: 4603 mov r3, r0
|
|
8012218: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
801221a: 7b7b ldrb r3, [r7, #13]
|
|
801221c: 2bff cmp r3, #255 @ 0xff
|
|
801221e: f000 8176 beq.w 801250e <USBD_StdEPReq+0x332>
|
|
8012222: 7b7b ldrb r3, [r7, #13]
|
|
8012224: 2b00 cmp r3, #0
|
|
8012226: f040 8172 bne.w 801250e <USBD_StdEPReq+0x332>
|
|
{
|
|
pdev->classId = idx;
|
|
801222a: 7b7a ldrb r2, [r7, #13]
|
|
801222c: 687b ldr r3, [r7, #4]
|
|
801222e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8012232: 7b7a ldrb r2, [r7, #13]
|
|
8012234: 687b ldr r3, [r7, #4]
|
|
8012236: 32ae adds r2, #174 @ 0xae
|
|
8012238: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
801223c: 689b ldr r3, [r3, #8]
|
|
801223e: 2b00 cmp r3, #0
|
|
8012240: f000 8165 beq.w 801250e <USBD_StdEPReq+0x332>
|
|
{
|
|
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
|
|
8012244: 7b7a ldrb r2, [r7, #13]
|
|
8012246: 687b ldr r3, [r7, #4]
|
|
8012248: 32ae adds r2, #174 @ 0xae
|
|
801224a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
801224e: 689b ldr r3, [r3, #8]
|
|
8012250: 6839 ldr r1, [r7, #0]
|
|
8012252: 6878 ldr r0, [r7, #4]
|
|
8012254: 4798 blx r3
|
|
8012256: 4603 mov r3, r0
|
|
8012258: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
801225a: e158 b.n 801250e <USBD_StdEPReq+0x332>
|
|
|
|
case USB_REQ_TYPE_STANDARD:
|
|
switch (req->bRequest)
|
|
801225c: 683b ldr r3, [r7, #0]
|
|
801225e: 785b ldrb r3, [r3, #1]
|
|
8012260: 2b03 cmp r3, #3
|
|
8012262: d008 beq.n 8012276 <USBD_StdEPReq+0x9a>
|
|
8012264: 2b03 cmp r3, #3
|
|
8012266: f300 8147 bgt.w 80124f8 <USBD_StdEPReq+0x31c>
|
|
801226a: 2b00 cmp r3, #0
|
|
801226c: f000 809b beq.w 80123a6 <USBD_StdEPReq+0x1ca>
|
|
8012270: 2b01 cmp r3, #1
|
|
8012272: d03c beq.n 80122ee <USBD_StdEPReq+0x112>
|
|
8012274: e140 b.n 80124f8 <USBD_StdEPReq+0x31c>
|
|
{
|
|
case USB_REQ_SET_FEATURE:
|
|
switch (pdev->dev_state)
|
|
8012276: 687b ldr r3, [r7, #4]
|
|
8012278: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
801227c: b2db uxtb r3, r3
|
|
801227e: 2b02 cmp r3, #2
|
|
8012280: d002 beq.n 8012288 <USBD_StdEPReq+0xac>
|
|
8012282: 2b03 cmp r3, #3
|
|
8012284: d016 beq.n 80122b4 <USBD_StdEPReq+0xd8>
|
|
8012286: e02c b.n 80122e2 <USBD_StdEPReq+0x106>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8012288: 7bbb ldrb r3, [r7, #14]
|
|
801228a: 2b00 cmp r3, #0
|
|
801228c: d00d beq.n 80122aa <USBD_StdEPReq+0xce>
|
|
801228e: 7bbb ldrb r3, [r7, #14]
|
|
8012290: 2b80 cmp r3, #128 @ 0x80
|
|
8012292: d00a beq.n 80122aa <USBD_StdEPReq+0xce>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
8012294: 7bbb ldrb r3, [r7, #14]
|
|
8012296: 4619 mov r1, r3
|
|
8012298: 6878 ldr r0, [r7, #4]
|
|
801229a: f006 feef bl 801907c <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
801229e: 2180 movs r1, #128 @ 0x80
|
|
80122a0: 6878 ldr r0, [r7, #4]
|
|
80122a2: f006 feeb bl 801907c <USBD_LL_StallEP>
|
|
80122a6: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
80122a8: e020 b.n 80122ec <USBD_StdEPReq+0x110>
|
|
USBD_CtlError(pdev, req);
|
|
80122aa: 6839 ldr r1, [r7, #0]
|
|
80122ac: 6878 ldr r0, [r7, #4]
|
|
80122ae: f000 fca6 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80122b2: e01b b.n 80122ec <USBD_StdEPReq+0x110>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
80122b4: 683b ldr r3, [r7, #0]
|
|
80122b6: 885b ldrh r3, [r3, #2]
|
|
80122b8: 2b00 cmp r3, #0
|
|
80122ba: d10e bne.n 80122da <USBD_StdEPReq+0xfe>
|
|
{
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
|
|
80122bc: 7bbb ldrb r3, [r7, #14]
|
|
80122be: 2b00 cmp r3, #0
|
|
80122c0: d00b beq.n 80122da <USBD_StdEPReq+0xfe>
|
|
80122c2: 7bbb ldrb r3, [r7, #14]
|
|
80122c4: 2b80 cmp r3, #128 @ 0x80
|
|
80122c6: d008 beq.n 80122da <USBD_StdEPReq+0xfe>
|
|
80122c8: 683b ldr r3, [r7, #0]
|
|
80122ca: 88db ldrh r3, [r3, #6]
|
|
80122cc: 2b00 cmp r3, #0
|
|
80122ce: d104 bne.n 80122da <USBD_StdEPReq+0xfe>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
80122d0: 7bbb ldrb r3, [r7, #14]
|
|
80122d2: 4619 mov r1, r3
|
|
80122d4: 6878 ldr r0, [r7, #4]
|
|
80122d6: f006 fed1 bl 801907c <USBD_LL_StallEP>
|
|
}
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80122da: 6878 ldr r0, [r7, #4]
|
|
80122dc: f000 fd6d bl 8012dba <USBD_CtlSendStatus>
|
|
|
|
break;
|
|
80122e0: e004 b.n 80122ec <USBD_StdEPReq+0x110>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80122e2: 6839 ldr r1, [r7, #0]
|
|
80122e4: 6878 ldr r0, [r7, #4]
|
|
80122e6: f000 fc8a bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80122ea: bf00 nop
|
|
}
|
|
break;
|
|
80122ec: e109 b.n 8012502 <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
switch (pdev->dev_state)
|
|
80122ee: 687b ldr r3, [r7, #4]
|
|
80122f0: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80122f4: b2db uxtb r3, r3
|
|
80122f6: 2b02 cmp r3, #2
|
|
80122f8: d002 beq.n 8012300 <USBD_StdEPReq+0x124>
|
|
80122fa: 2b03 cmp r3, #3
|
|
80122fc: d016 beq.n 801232c <USBD_StdEPReq+0x150>
|
|
80122fe: e04b b.n 8012398 <USBD_StdEPReq+0x1bc>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
8012300: 7bbb ldrb r3, [r7, #14]
|
|
8012302: 2b00 cmp r3, #0
|
|
8012304: d00d beq.n 8012322 <USBD_StdEPReq+0x146>
|
|
8012306: 7bbb ldrb r3, [r7, #14]
|
|
8012308: 2b80 cmp r3, #128 @ 0x80
|
|
801230a: d00a beq.n 8012322 <USBD_StdEPReq+0x146>
|
|
{
|
|
(void)USBD_LL_StallEP(pdev, ep_addr);
|
|
801230c: 7bbb ldrb r3, [r7, #14]
|
|
801230e: 4619 mov r1, r3
|
|
8012310: 6878 ldr r0, [r7, #4]
|
|
8012312: f006 feb3 bl 801907c <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8012316: 2180 movs r1, #128 @ 0x80
|
|
8012318: 6878 ldr r0, [r7, #4]
|
|
801231a: f006 feaf bl 801907c <USBD_LL_StallEP>
|
|
801231e: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
break;
|
|
8012320: e040 b.n 80123a4 <USBD_StdEPReq+0x1c8>
|
|
USBD_CtlError(pdev, req);
|
|
8012322: 6839 ldr r1, [r7, #0]
|
|
8012324: 6878 ldr r0, [r7, #4]
|
|
8012326: f000 fc6a bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
801232a: e03b b.n 80123a4 <USBD_StdEPReq+0x1c8>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_EP_HALT)
|
|
801232c: 683b ldr r3, [r7, #0]
|
|
801232e: 885b ldrh r3, [r3, #2]
|
|
8012330: 2b00 cmp r3, #0
|
|
8012332: d136 bne.n 80123a2 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
if ((ep_addr & 0x7FU) != 0x00U)
|
|
8012334: 7bbb ldrb r3, [r7, #14]
|
|
8012336: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
801233a: 2b00 cmp r3, #0
|
|
801233c: d004 beq.n 8012348 <USBD_StdEPReq+0x16c>
|
|
{
|
|
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
|
|
801233e: 7bbb ldrb r3, [r7, #14]
|
|
8012340: 4619 mov r1, r3
|
|
8012342: 6878 ldr r0, [r7, #4]
|
|
8012344: f006 feb9 bl 80190ba <USBD_LL_ClearStallEP>
|
|
}
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8012348: 6878 ldr r0, [r7, #4]
|
|
801234a: f000 fd36 bl 8012dba <USBD_CtlSendStatus>
|
|
|
|
/* Get the class index relative to this interface */
|
|
idx = USBD_CoreFindEP(pdev, ep_addr);
|
|
801234e: 7bbb ldrb r3, [r7, #14]
|
|
8012350: 4619 mov r1, r3
|
|
8012352: 6878 ldr r0, [r7, #4]
|
|
8012354: f7ff fde3 bl 8011f1e <USBD_CoreFindEP>
|
|
8012358: 4603 mov r3, r0
|
|
801235a: 737b strb r3, [r7, #13]
|
|
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
|
|
801235c: 7b7b ldrb r3, [r7, #13]
|
|
801235e: 2bff cmp r3, #255 @ 0xff
|
|
8012360: d01f beq.n 80123a2 <USBD_StdEPReq+0x1c6>
|
|
8012362: 7b7b ldrb r3, [r7, #13]
|
|
8012364: 2b00 cmp r3, #0
|
|
8012366: d11c bne.n 80123a2 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
pdev->classId = idx;
|
|
8012368: 7b7a ldrb r2, [r7, #13]
|
|
801236a: 687b ldr r3, [r7, #4]
|
|
801236c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
|
|
/* Call the class data out function to manage the request */
|
|
if (pdev->pClass[idx]->Setup != NULL)
|
|
8012370: 7b7a ldrb r2, [r7, #13]
|
|
8012372: 687b ldr r3, [r7, #4]
|
|
8012374: 32ae adds r2, #174 @ 0xae
|
|
8012376: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
801237a: 689b ldr r3, [r3, #8]
|
|
801237c: 2b00 cmp r3, #0
|
|
801237e: d010 beq.n 80123a2 <USBD_StdEPReq+0x1c6>
|
|
{
|
|
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
|
|
8012380: 7b7a ldrb r2, [r7, #13]
|
|
8012382: 687b ldr r3, [r7, #4]
|
|
8012384: 32ae adds r2, #174 @ 0xae
|
|
8012386: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
801238a: 689b ldr r3, [r3, #8]
|
|
801238c: 6839 ldr r1, [r7, #0]
|
|
801238e: 6878 ldr r0, [r7, #4]
|
|
8012390: 4798 blx r3
|
|
8012392: 4603 mov r3, r0
|
|
8012394: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
8012396: e004 b.n 80123a2 <USBD_StdEPReq+0x1c6>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8012398: 6839 ldr r1, [r7, #0]
|
|
801239a: 6878 ldr r0, [r7, #4]
|
|
801239c: f000 fc2f bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80123a0: e000 b.n 80123a4 <USBD_StdEPReq+0x1c8>
|
|
break;
|
|
80123a2: bf00 nop
|
|
}
|
|
break;
|
|
80123a4: e0ad b.n 8012502 <USBD_StdEPReq+0x326>
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
switch (pdev->dev_state)
|
|
80123a6: 687b ldr r3, [r7, #4]
|
|
80123a8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80123ac: b2db uxtb r3, r3
|
|
80123ae: 2b02 cmp r3, #2
|
|
80123b0: d002 beq.n 80123b8 <USBD_StdEPReq+0x1dc>
|
|
80123b2: 2b03 cmp r3, #3
|
|
80123b4: d033 beq.n 801241e <USBD_StdEPReq+0x242>
|
|
80123b6: e099 b.n 80124ec <USBD_StdEPReq+0x310>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
|
|
80123b8: 7bbb ldrb r3, [r7, #14]
|
|
80123ba: 2b00 cmp r3, #0
|
|
80123bc: d007 beq.n 80123ce <USBD_StdEPReq+0x1f2>
|
|
80123be: 7bbb ldrb r3, [r7, #14]
|
|
80123c0: 2b80 cmp r3, #128 @ 0x80
|
|
80123c2: d004 beq.n 80123ce <USBD_StdEPReq+0x1f2>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80123c4: 6839 ldr r1, [r7, #0]
|
|
80123c6: 6878 ldr r0, [r7, #4]
|
|
80123c8: f000 fc19 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80123cc: e093 b.n 80124f6 <USBD_StdEPReq+0x31a>
|
|
}
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80123ce: f997 300e ldrsb.w r3, [r7, #14]
|
|
80123d2: 2b00 cmp r3, #0
|
|
80123d4: da0b bge.n 80123ee <USBD_StdEPReq+0x212>
|
|
80123d6: 7bbb ldrb r3, [r7, #14]
|
|
80123d8: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
80123dc: 4613 mov r3, r2
|
|
80123de: 009b lsls r3, r3, #2
|
|
80123e0: 4413 add r3, r2
|
|
80123e2: 009b lsls r3, r3, #2
|
|
80123e4: 3310 adds r3, #16
|
|
80123e6: 687a ldr r2, [r7, #4]
|
|
80123e8: 4413 add r3, r2
|
|
80123ea: 3304 adds r3, #4
|
|
80123ec: e00b b.n 8012406 <USBD_StdEPReq+0x22a>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
80123ee: 7bbb ldrb r3, [r7, #14]
|
|
80123f0: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
80123f4: 4613 mov r3, r2
|
|
80123f6: 009b lsls r3, r3, #2
|
|
80123f8: 4413 add r3, r2
|
|
80123fa: 009b lsls r3, r3, #2
|
|
80123fc: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
8012400: 687a ldr r2, [r7, #4]
|
|
8012402: 4413 add r3, r2
|
|
8012404: 3304 adds r3, #4
|
|
8012406: 60bb str r3, [r7, #8]
|
|
|
|
pep->status = 0x0000U;
|
|
8012408: 68bb ldr r3, [r7, #8]
|
|
801240a: 2200 movs r2, #0
|
|
801240c: 739a strb r2, [r3, #14]
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
801240e: 68bb ldr r3, [r7, #8]
|
|
8012410: 330e adds r3, #14
|
|
8012412: 2202 movs r2, #2
|
|
8012414: 4619 mov r1, r3
|
|
8012416: 6878 ldr r0, [r7, #4]
|
|
8012418: f000 fc6e bl 8012cf8 <USBD_CtlSendData>
|
|
break;
|
|
801241c: e06b b.n 80124f6 <USBD_StdEPReq+0x31a>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if ((ep_addr & 0x80U) == 0x80U)
|
|
801241e: f997 300e ldrsb.w r3, [r7, #14]
|
|
8012422: 2b00 cmp r3, #0
|
|
8012424: da11 bge.n 801244a <USBD_StdEPReq+0x26e>
|
|
{
|
|
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
|
|
8012426: 7bbb ldrb r3, [r7, #14]
|
|
8012428: f003 020f and.w r2, r3, #15
|
|
801242c: 6879 ldr r1, [r7, #4]
|
|
801242e: 4613 mov r3, r2
|
|
8012430: 009b lsls r3, r3, #2
|
|
8012432: 4413 add r3, r2
|
|
8012434: 009b lsls r3, r3, #2
|
|
8012436: 440b add r3, r1
|
|
8012438: 3323 adds r3, #35 @ 0x23
|
|
801243a: 781b ldrb r3, [r3, #0]
|
|
801243c: 2b00 cmp r3, #0
|
|
801243e: d117 bne.n 8012470 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8012440: 6839 ldr r1, [r7, #0]
|
|
8012442: 6878 ldr r0, [r7, #4]
|
|
8012444: f000 fbdb bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
8012448: e055 b.n 80124f6 <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
|
|
801244a: 7bbb ldrb r3, [r7, #14]
|
|
801244c: f003 020f and.w r2, r3, #15
|
|
8012450: 6879 ldr r1, [r7, #4]
|
|
8012452: 4613 mov r3, r2
|
|
8012454: 009b lsls r3, r3, #2
|
|
8012456: 4413 add r3, r2
|
|
8012458: 009b lsls r3, r3, #2
|
|
801245a: 440b add r3, r1
|
|
801245c: f203 1363 addw r3, r3, #355 @ 0x163
|
|
8012460: 781b ldrb r3, [r3, #0]
|
|
8012462: 2b00 cmp r3, #0
|
|
8012464: d104 bne.n 8012470 <USBD_StdEPReq+0x294>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8012466: 6839 ldr r1, [r7, #0]
|
|
8012468: 6878 ldr r0, [r7, #4]
|
|
801246a: f000 fbc8 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
801246e: e042 b.n 80124f6 <USBD_StdEPReq+0x31a>
|
|
}
|
|
}
|
|
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8012470: f997 300e ldrsb.w r3, [r7, #14]
|
|
8012474: 2b00 cmp r3, #0
|
|
8012476: da0b bge.n 8012490 <USBD_StdEPReq+0x2b4>
|
|
8012478: 7bbb ldrb r3, [r7, #14]
|
|
801247a: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
801247e: 4613 mov r3, r2
|
|
8012480: 009b lsls r3, r3, #2
|
|
8012482: 4413 add r3, r2
|
|
8012484: 009b lsls r3, r3, #2
|
|
8012486: 3310 adds r3, #16
|
|
8012488: 687a ldr r2, [r7, #4]
|
|
801248a: 4413 add r3, r2
|
|
801248c: 3304 adds r3, #4
|
|
801248e: e00b b.n 80124a8 <USBD_StdEPReq+0x2cc>
|
|
&pdev->ep_out[ep_addr & 0x7FU];
|
|
8012490: 7bbb ldrb r3, [r7, #14]
|
|
8012492: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
|
|
8012496: 4613 mov r3, r2
|
|
8012498: 009b lsls r3, r3, #2
|
|
801249a: 4413 add r3, r2
|
|
801249c: 009b lsls r3, r3, #2
|
|
801249e: f503 73a8 add.w r3, r3, #336 @ 0x150
|
|
80124a2: 687a ldr r2, [r7, #4]
|
|
80124a4: 4413 add r3, r2
|
|
80124a6: 3304 adds r3, #4
|
|
80124a8: 60bb str r3, [r7, #8]
|
|
|
|
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
|
|
80124aa: 7bbb ldrb r3, [r7, #14]
|
|
80124ac: 2b00 cmp r3, #0
|
|
80124ae: d002 beq.n 80124b6 <USBD_StdEPReq+0x2da>
|
|
80124b0: 7bbb ldrb r3, [r7, #14]
|
|
80124b2: 2b80 cmp r3, #128 @ 0x80
|
|
80124b4: d103 bne.n 80124be <USBD_StdEPReq+0x2e2>
|
|
{
|
|
pep->status = 0x0000U;
|
|
80124b6: 68bb ldr r3, [r7, #8]
|
|
80124b8: 2200 movs r2, #0
|
|
80124ba: 739a strb r2, [r3, #14]
|
|
80124bc: e00e b.n 80124dc <USBD_StdEPReq+0x300>
|
|
}
|
|
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
|
|
80124be: 7bbb ldrb r3, [r7, #14]
|
|
80124c0: 4619 mov r1, r3
|
|
80124c2: 6878 ldr r0, [r7, #4]
|
|
80124c4: f006 fe18 bl 80190f8 <USBD_LL_IsStallEP>
|
|
80124c8: 4603 mov r3, r0
|
|
80124ca: 2b00 cmp r3, #0
|
|
80124cc: d003 beq.n 80124d6 <USBD_StdEPReq+0x2fa>
|
|
{
|
|
pep->status = 0x0001U;
|
|
80124ce: 68bb ldr r3, [r7, #8]
|
|
80124d0: 2201 movs r2, #1
|
|
80124d2: 739a strb r2, [r3, #14]
|
|
80124d4: e002 b.n 80124dc <USBD_StdEPReq+0x300>
|
|
}
|
|
else
|
|
{
|
|
pep->status = 0x0000U;
|
|
80124d6: 68bb ldr r3, [r7, #8]
|
|
80124d8: 2200 movs r2, #0
|
|
80124da: 739a strb r2, [r3, #14]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
|
|
80124dc: 68bb ldr r3, [r7, #8]
|
|
80124de: 330e adds r3, #14
|
|
80124e0: 2202 movs r2, #2
|
|
80124e2: 4619 mov r1, r3
|
|
80124e4: 6878 ldr r0, [r7, #4]
|
|
80124e6: f000 fc07 bl 8012cf8 <USBD_CtlSendData>
|
|
break;
|
|
80124ea: e004 b.n 80124f6 <USBD_StdEPReq+0x31a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80124ec: 6839 ldr r1, [r7, #0]
|
|
80124ee: 6878 ldr r0, [r7, #4]
|
|
80124f0: f000 fb85 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
80124f4: bf00 nop
|
|
}
|
|
break;
|
|
80124f6: e004 b.n 8012502 <USBD_StdEPReq+0x326>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80124f8: 6839 ldr r1, [r7, #0]
|
|
80124fa: 6878 ldr r0, [r7, #4]
|
|
80124fc: f000 fb7f bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
8012500: bf00 nop
|
|
}
|
|
break;
|
|
8012502: e005 b.n 8012510 <USBD_StdEPReq+0x334>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8012504: 6839 ldr r1, [r7, #0]
|
|
8012506: 6878 ldr r0, [r7, #4]
|
|
8012508: f000 fb79 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
801250c: e000 b.n 8012510 <USBD_StdEPReq+0x334>
|
|
break;
|
|
801250e: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8012510: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8012512: 4618 mov r0, r3
|
|
8012514: 3710 adds r7, #16
|
|
8012516: 46bd mov sp, r7
|
|
8012518: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0801251c <USBD_GetDescriptor>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
801251c: b580 push {r7, lr}
|
|
801251e: b084 sub sp, #16
|
|
8012520: af00 add r7, sp, #0
|
|
8012522: 6078 str r0, [r7, #4]
|
|
8012524: 6039 str r1, [r7, #0]
|
|
uint16_t len = 0U;
|
|
8012526: 2300 movs r3, #0
|
|
8012528: 813b strh r3, [r7, #8]
|
|
uint8_t *pbuf = NULL;
|
|
801252a: 2300 movs r3, #0
|
|
801252c: 60fb str r3, [r7, #12]
|
|
uint8_t err = 0U;
|
|
801252e: 2300 movs r3, #0
|
|
8012530: 72fb strb r3, [r7, #11]
|
|
|
|
switch (req->wValue >> 8)
|
|
8012532: 683b ldr r3, [r7, #0]
|
|
8012534: 885b ldrh r3, [r3, #2]
|
|
8012536: 0a1b lsrs r3, r3, #8
|
|
8012538: b29b uxth r3, r3
|
|
801253a: 3b01 subs r3, #1
|
|
801253c: 2b0e cmp r3, #14
|
|
801253e: f200 8152 bhi.w 80127e6 <USBD_GetDescriptor+0x2ca>
|
|
8012542: a201 add r2, pc, #4 @ (adr r2, 8012548 <USBD_GetDescriptor+0x2c>)
|
|
8012544: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8012548: 080125b9 .word 0x080125b9
|
|
801254c: 080125d1 .word 0x080125d1
|
|
8012550: 08012611 .word 0x08012611
|
|
8012554: 080127e7 .word 0x080127e7
|
|
8012558: 080127e7 .word 0x080127e7
|
|
801255c: 08012787 .word 0x08012787
|
|
8012560: 080127b3 .word 0x080127b3
|
|
8012564: 080127e7 .word 0x080127e7
|
|
8012568: 080127e7 .word 0x080127e7
|
|
801256c: 080127e7 .word 0x080127e7
|
|
8012570: 080127e7 .word 0x080127e7
|
|
8012574: 080127e7 .word 0x080127e7
|
|
8012578: 080127e7 .word 0x080127e7
|
|
801257c: 080127e7 .word 0x080127e7
|
|
8012580: 08012585 .word 0x08012585
|
|
{
|
|
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
|
|
case USB_DESC_TYPE_BOS:
|
|
if (pdev->pDesc->GetBOSDescriptor != NULL)
|
|
8012584: 687b ldr r3, [r7, #4]
|
|
8012586: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
801258a: 69db ldr r3, [r3, #28]
|
|
801258c: 2b00 cmp r3, #0
|
|
801258e: d00b beq.n 80125a8 <USBD_GetDescriptor+0x8c>
|
|
{
|
|
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
|
|
8012590: 687b ldr r3, [r7, #4]
|
|
8012592: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8012596: 69db ldr r3, [r3, #28]
|
|
8012598: 687a ldr r2, [r7, #4]
|
|
801259a: 7c12 ldrb r2, [r2, #16]
|
|
801259c: f107 0108 add.w r1, r7, #8
|
|
80125a0: 4610 mov r0, r2
|
|
80125a2: 4798 blx r3
|
|
80125a4: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80125a6: e126 b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80125a8: 6839 ldr r1, [r7, #0]
|
|
80125aa: 6878 ldr r0, [r7, #4]
|
|
80125ac: f000 fb27 bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
80125b0: 7afb ldrb r3, [r7, #11]
|
|
80125b2: 3301 adds r3, #1
|
|
80125b4: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80125b6: e11e b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
|
|
case USB_DESC_TYPE_DEVICE:
|
|
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
|
|
80125b8: 687b ldr r3, [r7, #4]
|
|
80125ba: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80125be: 681b ldr r3, [r3, #0]
|
|
80125c0: 687a ldr r2, [r7, #4]
|
|
80125c2: 7c12 ldrb r2, [r2, #16]
|
|
80125c4: f107 0108 add.w r1, r7, #8
|
|
80125c8: 4610 mov r0, r2
|
|
80125ca: 4798 blx r3
|
|
80125cc: 60f8 str r0, [r7, #12]
|
|
break;
|
|
80125ce: e112 b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80125d0: 687b ldr r3, [r7, #4]
|
|
80125d2: 7c1b ldrb r3, [r3, #16]
|
|
80125d4: 2b00 cmp r3, #0
|
|
80125d6: d10d bne.n 80125f4 <USBD_GetDescriptor+0xd8>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
|
|
80125d8: 687b ldr r3, [r7, #4]
|
|
80125da: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80125de: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80125e0: f107 0208 add.w r2, r7, #8
|
|
80125e4: 4610 mov r0, r2
|
|
80125e6: 4798 blx r3
|
|
80125e8: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
80125ea: 68fb ldr r3, [r7, #12]
|
|
80125ec: 3301 adds r3, #1
|
|
80125ee: 2202 movs r2, #2
|
|
80125f0: 701a strb r2, [r3, #0]
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
}
|
|
break;
|
|
80125f2: e100 b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
|
|
80125f4: 687b ldr r3, [r7, #4]
|
|
80125f6: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80125fa: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80125fc: f107 0208 add.w r2, r7, #8
|
|
8012600: 4610 mov r0, r2
|
|
8012602: 4798 blx r3
|
|
8012604: 60f8 str r0, [r7, #12]
|
|
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
|
8012606: 68fb ldr r3, [r7, #12]
|
|
8012608: 3301 adds r3, #1
|
|
801260a: 2202 movs r2, #2
|
|
801260c: 701a strb r2, [r3, #0]
|
|
break;
|
|
801260e: e0f2 b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_STRING:
|
|
switch ((uint8_t)(req->wValue))
|
|
8012610: 683b ldr r3, [r7, #0]
|
|
8012612: 885b ldrh r3, [r3, #2]
|
|
8012614: b2db uxtb r3, r3
|
|
8012616: 2b05 cmp r3, #5
|
|
8012618: f200 80ac bhi.w 8012774 <USBD_GetDescriptor+0x258>
|
|
801261c: a201 add r2, pc, #4 @ (adr r2, 8012624 <USBD_GetDescriptor+0x108>)
|
|
801261e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8012622: bf00 nop
|
|
8012624: 0801263d .word 0x0801263d
|
|
8012628: 08012671 .word 0x08012671
|
|
801262c: 080126a5 .word 0x080126a5
|
|
8012630: 080126d9 .word 0x080126d9
|
|
8012634: 0801270d .word 0x0801270d
|
|
8012638: 08012741 .word 0x08012741
|
|
{
|
|
case USBD_IDX_LANGID_STR:
|
|
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
|
|
801263c: 687b ldr r3, [r7, #4]
|
|
801263e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8012642: 685b ldr r3, [r3, #4]
|
|
8012644: 2b00 cmp r3, #0
|
|
8012646: d00b beq.n 8012660 <USBD_GetDescriptor+0x144>
|
|
{
|
|
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
|
|
8012648: 687b ldr r3, [r7, #4]
|
|
801264a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
801264e: 685b ldr r3, [r3, #4]
|
|
8012650: 687a ldr r2, [r7, #4]
|
|
8012652: 7c12 ldrb r2, [r2, #16]
|
|
8012654: f107 0108 add.w r1, r7, #8
|
|
8012658: 4610 mov r0, r2
|
|
801265a: 4798 blx r3
|
|
801265c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
801265e: e091 b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8012660: 6839 ldr r1, [r7, #0]
|
|
8012662: 6878 ldr r0, [r7, #4]
|
|
8012664: f000 facb bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
8012668: 7afb ldrb r3, [r7, #11]
|
|
801266a: 3301 adds r3, #1
|
|
801266c: 72fb strb r3, [r7, #11]
|
|
break;
|
|
801266e: e089 b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_MFC_STR:
|
|
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
|
|
8012670: 687b ldr r3, [r7, #4]
|
|
8012672: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8012676: 689b ldr r3, [r3, #8]
|
|
8012678: 2b00 cmp r3, #0
|
|
801267a: d00b beq.n 8012694 <USBD_GetDescriptor+0x178>
|
|
{
|
|
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
|
|
801267c: 687b ldr r3, [r7, #4]
|
|
801267e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8012682: 689b ldr r3, [r3, #8]
|
|
8012684: 687a ldr r2, [r7, #4]
|
|
8012686: 7c12 ldrb r2, [r2, #16]
|
|
8012688: f107 0108 add.w r1, r7, #8
|
|
801268c: 4610 mov r0, r2
|
|
801268e: 4798 blx r3
|
|
8012690: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8012692: e077 b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8012694: 6839 ldr r1, [r7, #0]
|
|
8012696: 6878 ldr r0, [r7, #4]
|
|
8012698: f000 fab1 bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
801269c: 7afb ldrb r3, [r7, #11]
|
|
801269e: 3301 adds r3, #1
|
|
80126a0: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80126a2: e06f b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_PRODUCT_STR:
|
|
if (pdev->pDesc->GetProductStrDescriptor != NULL)
|
|
80126a4: 687b ldr r3, [r7, #4]
|
|
80126a6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80126aa: 68db ldr r3, [r3, #12]
|
|
80126ac: 2b00 cmp r3, #0
|
|
80126ae: d00b beq.n 80126c8 <USBD_GetDescriptor+0x1ac>
|
|
{
|
|
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
|
|
80126b0: 687b ldr r3, [r7, #4]
|
|
80126b2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80126b6: 68db ldr r3, [r3, #12]
|
|
80126b8: 687a ldr r2, [r7, #4]
|
|
80126ba: 7c12 ldrb r2, [r2, #16]
|
|
80126bc: f107 0108 add.w r1, r7, #8
|
|
80126c0: 4610 mov r0, r2
|
|
80126c2: 4798 blx r3
|
|
80126c4: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80126c6: e05d b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80126c8: 6839 ldr r1, [r7, #0]
|
|
80126ca: 6878 ldr r0, [r7, #4]
|
|
80126cc: f000 fa97 bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
80126d0: 7afb ldrb r3, [r7, #11]
|
|
80126d2: 3301 adds r3, #1
|
|
80126d4: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80126d6: e055 b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_SERIAL_STR:
|
|
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
|
|
80126d8: 687b ldr r3, [r7, #4]
|
|
80126da: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80126de: 691b ldr r3, [r3, #16]
|
|
80126e0: 2b00 cmp r3, #0
|
|
80126e2: d00b beq.n 80126fc <USBD_GetDescriptor+0x1e0>
|
|
{
|
|
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
|
|
80126e4: 687b ldr r3, [r7, #4]
|
|
80126e6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
80126ea: 691b ldr r3, [r3, #16]
|
|
80126ec: 687a ldr r2, [r7, #4]
|
|
80126ee: 7c12 ldrb r2, [r2, #16]
|
|
80126f0: f107 0108 add.w r1, r7, #8
|
|
80126f4: 4610 mov r0, r2
|
|
80126f6: 4798 blx r3
|
|
80126f8: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80126fa: e043 b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
80126fc: 6839 ldr r1, [r7, #0]
|
|
80126fe: 6878 ldr r0, [r7, #4]
|
|
8012700: f000 fa7d bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
8012704: 7afb ldrb r3, [r7, #11]
|
|
8012706: 3301 adds r3, #1
|
|
8012708: 72fb strb r3, [r7, #11]
|
|
break;
|
|
801270a: e03b b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_CONFIG_STR:
|
|
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
|
|
801270c: 687b ldr r3, [r7, #4]
|
|
801270e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8012712: 695b ldr r3, [r3, #20]
|
|
8012714: 2b00 cmp r3, #0
|
|
8012716: d00b beq.n 8012730 <USBD_GetDescriptor+0x214>
|
|
{
|
|
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
|
|
8012718: 687b ldr r3, [r7, #4]
|
|
801271a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
801271e: 695b ldr r3, [r3, #20]
|
|
8012720: 687a ldr r2, [r7, #4]
|
|
8012722: 7c12 ldrb r2, [r2, #16]
|
|
8012724: f107 0108 add.w r1, r7, #8
|
|
8012728: 4610 mov r0, r2
|
|
801272a: 4798 blx r3
|
|
801272c: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
801272e: e029 b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8012730: 6839 ldr r1, [r7, #0]
|
|
8012732: 6878 ldr r0, [r7, #4]
|
|
8012734: f000 fa63 bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
8012738: 7afb ldrb r3, [r7, #11]
|
|
801273a: 3301 adds r3, #1
|
|
801273c: 72fb strb r3, [r7, #11]
|
|
break;
|
|
801273e: e021 b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
|
|
case USBD_IDX_INTERFACE_STR:
|
|
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
|
|
8012740: 687b ldr r3, [r7, #4]
|
|
8012742: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8012746: 699b ldr r3, [r3, #24]
|
|
8012748: 2b00 cmp r3, #0
|
|
801274a: d00b beq.n 8012764 <USBD_GetDescriptor+0x248>
|
|
{
|
|
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
|
|
801274c: 687b ldr r3, [r7, #4]
|
|
801274e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
|
|
8012752: 699b ldr r3, [r3, #24]
|
|
8012754: 687a ldr r2, [r7, #4]
|
|
8012756: 7c12 ldrb r2, [r2, #16]
|
|
8012758: f107 0108 add.w r1, r7, #8
|
|
801275c: 4610 mov r0, r2
|
|
801275e: 4798 blx r3
|
|
8012760: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
8012762: e00f b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
USBD_CtlError(pdev, req);
|
|
8012764: 6839 ldr r1, [r7, #0]
|
|
8012766: 6878 ldr r0, [r7, #4]
|
|
8012768: f000 fa49 bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
801276c: 7afb ldrb r3, [r7, #11]
|
|
801276e: 3301 adds r3, #1
|
|
8012770: 72fb strb r3, [r7, #11]
|
|
break;
|
|
8012772: e007 b.n 8012784 <USBD_GetDescriptor+0x268>
|
|
err++;
|
|
}
|
|
#endif /* USBD_SUPPORT_USER_STRING_DESC */
|
|
|
|
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
|
|
USBD_CtlError(pdev, req);
|
|
8012774: 6839 ldr r1, [r7, #0]
|
|
8012776: 6878 ldr r0, [r7, #4]
|
|
8012778: f000 fa41 bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
801277c: 7afb ldrb r3, [r7, #11]
|
|
801277e: 3301 adds r3, #1
|
|
8012780: 72fb strb r3, [r7, #11]
|
|
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
|
|
break;
|
|
8012782: bf00 nop
|
|
}
|
|
break;
|
|
8012784: e037 b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_DEVICE_QUALIFIER:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
8012786: 687b ldr r3, [r7, #4]
|
|
8012788: 7c1b ldrb r3, [r3, #16]
|
|
801278a: 2b00 cmp r3, #0
|
|
801278c: d109 bne.n 80127a2 <USBD_GetDescriptor+0x286>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
|
|
801278e: 687b ldr r3, [r7, #4]
|
|
8012790: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
8012794: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8012796: f107 0208 add.w r2, r7, #8
|
|
801279a: 4610 mov r0, r2
|
|
801279c: 4798 blx r3
|
|
801279e: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80127a0: e029 b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80127a2: 6839 ldr r1, [r7, #0]
|
|
80127a4: 6878 ldr r0, [r7, #4]
|
|
80127a6: f000 fa2a bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
80127aa: 7afb ldrb r3, [r7, #11]
|
|
80127ac: 3301 adds r3, #1
|
|
80127ae: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80127b0: e021 b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
|
|
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
|
|
if (pdev->dev_speed == USBD_SPEED_HIGH)
|
|
80127b2: 687b ldr r3, [r7, #4]
|
|
80127b4: 7c1b ldrb r3, [r3, #16]
|
|
80127b6: 2b00 cmp r3, #0
|
|
80127b8: d10d bne.n 80127d6 <USBD_GetDescriptor+0x2ba>
|
|
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
|
|
}
|
|
else
|
|
#endif /* USE_USBD_COMPOSITE */
|
|
{
|
|
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
|
|
80127ba: 687b ldr r3, [r7, #4]
|
|
80127bc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
|
|
80127c0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80127c2: f107 0208 add.w r2, r7, #8
|
|
80127c6: 4610 mov r0, r2
|
|
80127c8: 4798 blx r3
|
|
80127ca: 60f8 str r0, [r7, #12]
|
|
}
|
|
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
|
|
80127cc: 68fb ldr r3, [r7, #12]
|
|
80127ce: 3301 adds r3, #1
|
|
80127d0: 2207 movs r2, #7
|
|
80127d2: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
err++;
|
|
}
|
|
break;
|
|
80127d4: e00f b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
USBD_CtlError(pdev, req);
|
|
80127d6: 6839 ldr r1, [r7, #0]
|
|
80127d8: 6878 ldr r0, [r7, #4]
|
|
80127da: f000 fa10 bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
80127de: 7afb ldrb r3, [r7, #11]
|
|
80127e0: 3301 adds r3, #1
|
|
80127e2: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80127e4: e007 b.n 80127f6 <USBD_GetDescriptor+0x2da>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80127e6: 6839 ldr r1, [r7, #0]
|
|
80127e8: 6878 ldr r0, [r7, #4]
|
|
80127ea: f000 fa08 bl 8012bfe <USBD_CtlError>
|
|
err++;
|
|
80127ee: 7afb ldrb r3, [r7, #11]
|
|
80127f0: 3301 adds r3, #1
|
|
80127f2: 72fb strb r3, [r7, #11]
|
|
break;
|
|
80127f4: bf00 nop
|
|
}
|
|
|
|
if (err != 0U)
|
|
80127f6: 7afb ldrb r3, [r7, #11]
|
|
80127f8: 2b00 cmp r3, #0
|
|
80127fa: d11e bne.n 801283a <USBD_GetDescriptor+0x31e>
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (req->wLength != 0U)
|
|
80127fc: 683b ldr r3, [r7, #0]
|
|
80127fe: 88db ldrh r3, [r3, #6]
|
|
8012800: 2b00 cmp r3, #0
|
|
8012802: d016 beq.n 8012832 <USBD_GetDescriptor+0x316>
|
|
{
|
|
if (len != 0U)
|
|
8012804: 893b ldrh r3, [r7, #8]
|
|
8012806: 2b00 cmp r3, #0
|
|
8012808: d00e beq.n 8012828 <USBD_GetDescriptor+0x30c>
|
|
{
|
|
len = MIN(len, req->wLength);
|
|
801280a: 683b ldr r3, [r7, #0]
|
|
801280c: 88da ldrh r2, [r3, #6]
|
|
801280e: 893b ldrh r3, [r7, #8]
|
|
8012810: 4293 cmp r3, r2
|
|
8012812: bf28 it cs
|
|
8012814: 4613 movcs r3, r2
|
|
8012816: b29b uxth r3, r3
|
|
8012818: 813b strh r3, [r7, #8]
|
|
(void)USBD_CtlSendData(pdev, pbuf, len);
|
|
801281a: 893b ldrh r3, [r7, #8]
|
|
801281c: 461a mov r2, r3
|
|
801281e: 68f9 ldr r1, [r7, #12]
|
|
8012820: 6878 ldr r0, [r7, #4]
|
|
8012822: f000 fa69 bl 8012cf8 <USBD_CtlSendData>
|
|
8012826: e009 b.n 801283c <USBD_GetDescriptor+0x320>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8012828: 6839 ldr r1, [r7, #0]
|
|
801282a: 6878 ldr r0, [r7, #4]
|
|
801282c: f000 f9e7 bl 8012bfe <USBD_CtlError>
|
|
8012830: e004 b.n 801283c <USBD_GetDescriptor+0x320>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8012832: 6878 ldr r0, [r7, #4]
|
|
8012834: f000 fac1 bl 8012dba <USBD_CtlSendStatus>
|
|
8012838: e000 b.n 801283c <USBD_GetDescriptor+0x320>
|
|
return;
|
|
801283a: bf00 nop
|
|
}
|
|
}
|
|
801283c: 3710 adds r7, #16
|
|
801283e: 46bd mov sp, r7
|
|
8012840: bd80 pop {r7, pc}
|
|
8012842: bf00 nop
|
|
|
|
08012844 <USBD_SetAddress>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8012844: b580 push {r7, lr}
|
|
8012846: b084 sub sp, #16
|
|
8012848: af00 add r7, sp, #0
|
|
801284a: 6078 str r0, [r7, #4]
|
|
801284c: 6039 str r1, [r7, #0]
|
|
uint8_t dev_addr;
|
|
|
|
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
|
|
801284e: 683b ldr r3, [r7, #0]
|
|
8012850: 889b ldrh r3, [r3, #4]
|
|
8012852: 2b00 cmp r3, #0
|
|
8012854: d131 bne.n 80128ba <USBD_SetAddress+0x76>
|
|
8012856: 683b ldr r3, [r7, #0]
|
|
8012858: 88db ldrh r3, [r3, #6]
|
|
801285a: 2b00 cmp r3, #0
|
|
801285c: d12d bne.n 80128ba <USBD_SetAddress+0x76>
|
|
801285e: 683b ldr r3, [r7, #0]
|
|
8012860: 885b ldrh r3, [r3, #2]
|
|
8012862: 2b7f cmp r3, #127 @ 0x7f
|
|
8012864: d829 bhi.n 80128ba <USBD_SetAddress+0x76>
|
|
{
|
|
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
|
|
8012866: 683b ldr r3, [r7, #0]
|
|
8012868: 885b ldrh r3, [r3, #2]
|
|
801286a: b2db uxtb r3, r3
|
|
801286c: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
8012870: 73fb strb r3, [r7, #15]
|
|
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8012872: 687b ldr r3, [r7, #4]
|
|
8012874: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8012878: b2db uxtb r3, r3
|
|
801287a: 2b03 cmp r3, #3
|
|
801287c: d104 bne.n 8012888 <USBD_SetAddress+0x44>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
801287e: 6839 ldr r1, [r7, #0]
|
|
8012880: 6878 ldr r0, [r7, #4]
|
|
8012882: f000 f9bc bl 8012bfe <USBD_CtlError>
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
8012886: e01d b.n 80128c4 <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_address = dev_addr;
|
|
8012888: 687b ldr r3, [r7, #4]
|
|
801288a: 7bfa ldrb r2, [r7, #15]
|
|
801288c: f883 229e strb.w r2, [r3, #670] @ 0x29e
|
|
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
|
|
8012890: 7bfb ldrb r3, [r7, #15]
|
|
8012892: 4619 mov r1, r3
|
|
8012894: 6878 ldr r0, [r7, #4]
|
|
8012896: f006 fc5b bl 8019150 <USBD_LL_SetUSBAddress>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
801289a: 6878 ldr r0, [r7, #4]
|
|
801289c: f000 fa8d bl 8012dba <USBD_CtlSendStatus>
|
|
|
|
if (dev_addr != 0U)
|
|
80128a0: 7bfb ldrb r3, [r7, #15]
|
|
80128a2: 2b00 cmp r3, #0
|
|
80128a4: d004 beq.n 80128b0 <USBD_SetAddress+0x6c>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
80128a6: 687b ldr r3, [r7, #4]
|
|
80128a8: 2202 movs r2, #2
|
|
80128aa: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80128ae: e009 b.n 80128c4 <USBD_SetAddress+0x80>
|
|
}
|
|
else
|
|
{
|
|
pdev->dev_state = USBD_STATE_DEFAULT;
|
|
80128b0: 687b ldr r3, [r7, #4]
|
|
80128b2: 2201 movs r2, #1
|
|
80128b4: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
if (pdev->dev_state == USBD_STATE_CONFIGURED)
|
|
80128b8: e004 b.n 80128c4 <USBD_SetAddress+0x80>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80128ba: 6839 ldr r1, [r7, #0]
|
|
80128bc: 6878 ldr r0, [r7, #4]
|
|
80128be: f000 f99e bl 8012bfe <USBD_CtlError>
|
|
}
|
|
}
|
|
80128c2: bf00 nop
|
|
80128c4: bf00 nop
|
|
80128c6: 3710 adds r7, #16
|
|
80128c8: 46bd mov sp, r7
|
|
80128ca: bd80 pop {r7, pc}
|
|
|
|
080128cc <USBD_SetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval status
|
|
*/
|
|
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
80128cc: b580 push {r7, lr}
|
|
80128ce: b084 sub sp, #16
|
|
80128d0: af00 add r7, sp, #0
|
|
80128d2: 6078 str r0, [r7, #4]
|
|
80128d4: 6039 str r1, [r7, #0]
|
|
USBD_StatusTypeDef ret = USBD_OK;
|
|
80128d6: 2300 movs r3, #0
|
|
80128d8: 73fb strb r3, [r7, #15]
|
|
static uint8_t cfgidx;
|
|
|
|
cfgidx = (uint8_t)(req->wValue);
|
|
80128da: 683b ldr r3, [r7, #0]
|
|
80128dc: 885b ldrh r3, [r3, #2]
|
|
80128de: b2da uxtb r2, r3
|
|
80128e0: 4b4e ldr r3, [pc, #312] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
80128e2: 701a strb r2, [r3, #0]
|
|
|
|
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
|
|
80128e4: 4b4d ldr r3, [pc, #308] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
80128e6: 781b ldrb r3, [r3, #0]
|
|
80128e8: 2b01 cmp r3, #1
|
|
80128ea: d905 bls.n 80128f8 <USBD_SetConfig+0x2c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
80128ec: 6839 ldr r1, [r7, #0]
|
|
80128ee: 6878 ldr r0, [r7, #4]
|
|
80128f0: f000 f985 bl 8012bfe <USBD_CtlError>
|
|
return USBD_FAIL;
|
|
80128f4: 2303 movs r3, #3
|
|
80128f6: e08c b.n 8012a12 <USBD_SetConfig+0x146>
|
|
}
|
|
|
|
switch (pdev->dev_state)
|
|
80128f8: 687b ldr r3, [r7, #4]
|
|
80128fa: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
80128fe: b2db uxtb r3, r3
|
|
8012900: 2b02 cmp r3, #2
|
|
8012902: d002 beq.n 801290a <USBD_SetConfig+0x3e>
|
|
8012904: 2b03 cmp r3, #3
|
|
8012906: d029 beq.n 801295c <USBD_SetConfig+0x90>
|
|
8012908: e075 b.n 80129f6 <USBD_SetConfig+0x12a>
|
|
{
|
|
case USBD_STATE_ADDRESSED:
|
|
if (cfgidx != 0U)
|
|
801290a: 4b44 ldr r3, [pc, #272] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
801290c: 781b ldrb r3, [r3, #0]
|
|
801290e: 2b00 cmp r3, #0
|
|
8012910: d020 beq.n 8012954 <USBD_SetConfig+0x88>
|
|
{
|
|
pdev->dev_config = cfgidx;
|
|
8012912: 4b42 ldr r3, [pc, #264] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
8012914: 781b ldrb r3, [r3, #0]
|
|
8012916: 461a mov r2, r3
|
|
8012918: 687b ldr r3, [r7, #4]
|
|
801291a: 605a str r2, [r3, #4]
|
|
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
801291c: 4b3f ldr r3, [pc, #252] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
801291e: 781b ldrb r3, [r3, #0]
|
|
8012920: 4619 mov r1, r3
|
|
8012922: 6878 ldr r0, [r7, #4]
|
|
8012924: f7ff f835 bl 8011992 <USBD_SetClassConfig>
|
|
8012928: 4603 mov r3, r0
|
|
801292a: 73fb strb r3, [r7, #15]
|
|
|
|
if (ret != USBD_OK)
|
|
801292c: 7bfb ldrb r3, [r7, #15]
|
|
801292e: 2b00 cmp r3, #0
|
|
8012930: d008 beq.n 8012944 <USBD_SetConfig+0x78>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8012932: 6839 ldr r1, [r7, #0]
|
|
8012934: 6878 ldr r0, [r7, #4]
|
|
8012936: f000 f962 bl 8012bfe <USBD_CtlError>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
801293a: 687b ldr r3, [r7, #4]
|
|
801293c: 2202 movs r2, #2
|
|
801293e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8012942: e065 b.n 8012a10 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8012944: 6878 ldr r0, [r7, #4]
|
|
8012946: f000 fa38 bl 8012dba <USBD_CtlSendStatus>
|
|
pdev->dev_state = USBD_STATE_CONFIGURED;
|
|
801294a: 687b ldr r3, [r7, #4]
|
|
801294c: 2203 movs r2, #3
|
|
801294e: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
8012952: e05d b.n 8012a10 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8012954: 6878 ldr r0, [r7, #4]
|
|
8012956: f000 fa30 bl 8012dba <USBD_CtlSendStatus>
|
|
break;
|
|
801295a: e059 b.n 8012a10 <USBD_SetConfig+0x144>
|
|
|
|
case USBD_STATE_CONFIGURED:
|
|
if (cfgidx == 0U)
|
|
801295c: 4b2f ldr r3, [pc, #188] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
801295e: 781b ldrb r3, [r3, #0]
|
|
8012960: 2b00 cmp r3, #0
|
|
8012962: d112 bne.n 801298a <USBD_SetConfig+0xbe>
|
|
{
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
8012964: 687b ldr r3, [r7, #4]
|
|
8012966: 2202 movs r2, #2
|
|
8012968: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
pdev->dev_config = cfgidx;
|
|
801296c: 4b2b ldr r3, [pc, #172] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
801296e: 781b ldrb r3, [r3, #0]
|
|
8012970: 461a mov r2, r3
|
|
8012972: 687b ldr r3, [r7, #4]
|
|
8012974: 605a str r2, [r3, #4]
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
8012976: 4b29 ldr r3, [pc, #164] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
8012978: 781b ldrb r3, [r3, #0]
|
|
801297a: 4619 mov r1, r3
|
|
801297c: 6878 ldr r0, [r7, #4]
|
|
801297e: f7ff f824 bl 80119ca <USBD_ClrClassConfig>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8012982: 6878 ldr r0, [r7, #4]
|
|
8012984: f000 fa19 bl 8012dba <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
}
|
|
break;
|
|
8012988: e042 b.n 8012a10 <USBD_SetConfig+0x144>
|
|
else if (cfgidx != pdev->dev_config)
|
|
801298a: 4b24 ldr r3, [pc, #144] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
801298c: 781b ldrb r3, [r3, #0]
|
|
801298e: 461a mov r2, r3
|
|
8012990: 687b ldr r3, [r7, #4]
|
|
8012992: 685b ldr r3, [r3, #4]
|
|
8012994: 429a cmp r2, r3
|
|
8012996: d02a beq.n 80129ee <USBD_SetConfig+0x122>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
8012998: 687b ldr r3, [r7, #4]
|
|
801299a: 685b ldr r3, [r3, #4]
|
|
801299c: b2db uxtb r3, r3
|
|
801299e: 4619 mov r1, r3
|
|
80129a0: 6878 ldr r0, [r7, #4]
|
|
80129a2: f7ff f812 bl 80119ca <USBD_ClrClassConfig>
|
|
pdev->dev_config = cfgidx;
|
|
80129a6: 4b1d ldr r3, [pc, #116] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
80129a8: 781b ldrb r3, [r3, #0]
|
|
80129aa: 461a mov r2, r3
|
|
80129ac: 687b ldr r3, [r7, #4]
|
|
80129ae: 605a str r2, [r3, #4]
|
|
ret = USBD_SetClassConfig(pdev, cfgidx);
|
|
80129b0: 4b1a ldr r3, [pc, #104] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
80129b2: 781b ldrb r3, [r3, #0]
|
|
80129b4: 4619 mov r1, r3
|
|
80129b6: 6878 ldr r0, [r7, #4]
|
|
80129b8: f7fe ffeb bl 8011992 <USBD_SetClassConfig>
|
|
80129bc: 4603 mov r3, r0
|
|
80129be: 73fb strb r3, [r7, #15]
|
|
if (ret != USBD_OK)
|
|
80129c0: 7bfb ldrb r3, [r7, #15]
|
|
80129c2: 2b00 cmp r3, #0
|
|
80129c4: d00f beq.n 80129e6 <USBD_SetConfig+0x11a>
|
|
USBD_CtlError(pdev, req);
|
|
80129c6: 6839 ldr r1, [r7, #0]
|
|
80129c8: 6878 ldr r0, [r7, #4]
|
|
80129ca: f000 f918 bl 8012bfe <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
|
|
80129ce: 687b ldr r3, [r7, #4]
|
|
80129d0: 685b ldr r3, [r3, #4]
|
|
80129d2: b2db uxtb r3, r3
|
|
80129d4: 4619 mov r1, r3
|
|
80129d6: 6878 ldr r0, [r7, #4]
|
|
80129d8: f7fe fff7 bl 80119ca <USBD_ClrClassConfig>
|
|
pdev->dev_state = USBD_STATE_ADDRESSED;
|
|
80129dc: 687b ldr r3, [r7, #4]
|
|
80129de: 2202 movs r2, #2
|
|
80129e0: f883 229c strb.w r2, [r3, #668] @ 0x29c
|
|
break;
|
|
80129e4: e014 b.n 8012a10 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80129e6: 6878 ldr r0, [r7, #4]
|
|
80129e8: f000 f9e7 bl 8012dba <USBD_CtlSendStatus>
|
|
break;
|
|
80129ec: e010 b.n 8012a10 <USBD_SetConfig+0x144>
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
80129ee: 6878 ldr r0, [r7, #4]
|
|
80129f0: f000 f9e3 bl 8012dba <USBD_CtlSendStatus>
|
|
break;
|
|
80129f4: e00c b.n 8012a10 <USBD_SetConfig+0x144>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
80129f6: 6839 ldr r1, [r7, #0]
|
|
80129f8: 6878 ldr r0, [r7, #4]
|
|
80129fa: f000 f900 bl 8012bfe <USBD_CtlError>
|
|
(void)USBD_ClrClassConfig(pdev, cfgidx);
|
|
80129fe: 4b07 ldr r3, [pc, #28] @ (8012a1c <USBD_SetConfig+0x150>)
|
|
8012a00: 781b ldrb r3, [r3, #0]
|
|
8012a02: 4619 mov r1, r3
|
|
8012a04: 6878 ldr r0, [r7, #4]
|
|
8012a06: f7fe ffe0 bl 80119ca <USBD_ClrClassConfig>
|
|
ret = USBD_FAIL;
|
|
8012a0a: 2303 movs r3, #3
|
|
8012a0c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8012a0e: bf00 nop
|
|
}
|
|
|
|
return ret;
|
|
8012a10: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8012a12: 4618 mov r0, r3
|
|
8012a14: 3710 adds r7, #16
|
|
8012a16: 46bd mov sp, r7
|
|
8012a18: bd80 pop {r7, pc}
|
|
8012a1a: bf00 nop
|
|
8012a1c: 20000784 .word 0x20000784
|
|
|
|
08012a20 <USBD_GetConfig>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8012a20: b580 push {r7, lr}
|
|
8012a22: b082 sub sp, #8
|
|
8012a24: af00 add r7, sp, #0
|
|
8012a26: 6078 str r0, [r7, #4]
|
|
8012a28: 6039 str r1, [r7, #0]
|
|
if (req->wLength != 1U)
|
|
8012a2a: 683b ldr r3, [r7, #0]
|
|
8012a2c: 88db ldrh r3, [r3, #6]
|
|
8012a2e: 2b01 cmp r3, #1
|
|
8012a30: d004 beq.n 8012a3c <USBD_GetConfig+0x1c>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8012a32: 6839 ldr r1, [r7, #0]
|
|
8012a34: 6878 ldr r0, [r7, #4]
|
|
8012a36: f000 f8e2 bl 8012bfe <USBD_CtlError>
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
8012a3a: e023 b.n 8012a84 <USBD_GetConfig+0x64>
|
|
switch (pdev->dev_state)
|
|
8012a3c: 687b ldr r3, [r7, #4]
|
|
8012a3e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8012a42: b2db uxtb r3, r3
|
|
8012a44: 2b02 cmp r3, #2
|
|
8012a46: dc02 bgt.n 8012a4e <USBD_GetConfig+0x2e>
|
|
8012a48: 2b00 cmp r3, #0
|
|
8012a4a: dc03 bgt.n 8012a54 <USBD_GetConfig+0x34>
|
|
8012a4c: e015 b.n 8012a7a <USBD_GetConfig+0x5a>
|
|
8012a4e: 2b03 cmp r3, #3
|
|
8012a50: d00b beq.n 8012a6a <USBD_GetConfig+0x4a>
|
|
8012a52: e012 b.n 8012a7a <USBD_GetConfig+0x5a>
|
|
pdev->dev_default_config = 0U;
|
|
8012a54: 687b ldr r3, [r7, #4]
|
|
8012a56: 2200 movs r2, #0
|
|
8012a58: 609a str r2, [r3, #8]
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
|
|
8012a5a: 687b ldr r3, [r7, #4]
|
|
8012a5c: 3308 adds r3, #8
|
|
8012a5e: 2201 movs r2, #1
|
|
8012a60: 4619 mov r1, r3
|
|
8012a62: 6878 ldr r0, [r7, #4]
|
|
8012a64: f000 f948 bl 8012cf8 <USBD_CtlSendData>
|
|
break;
|
|
8012a68: e00c b.n 8012a84 <USBD_GetConfig+0x64>
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
|
|
8012a6a: 687b ldr r3, [r7, #4]
|
|
8012a6c: 3304 adds r3, #4
|
|
8012a6e: 2201 movs r2, #1
|
|
8012a70: 4619 mov r1, r3
|
|
8012a72: 6878 ldr r0, [r7, #4]
|
|
8012a74: f000 f940 bl 8012cf8 <USBD_CtlSendData>
|
|
break;
|
|
8012a78: e004 b.n 8012a84 <USBD_GetConfig+0x64>
|
|
USBD_CtlError(pdev, req);
|
|
8012a7a: 6839 ldr r1, [r7, #0]
|
|
8012a7c: 6878 ldr r0, [r7, #4]
|
|
8012a7e: f000 f8be bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
8012a82: bf00 nop
|
|
}
|
|
8012a84: bf00 nop
|
|
8012a86: 3708 adds r7, #8
|
|
8012a88: 46bd mov sp, r7
|
|
8012a8a: bd80 pop {r7, pc}
|
|
|
|
08012a8c <USBD_GetStatus>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8012a8c: b580 push {r7, lr}
|
|
8012a8e: b082 sub sp, #8
|
|
8012a90: af00 add r7, sp, #0
|
|
8012a92: 6078 str r0, [r7, #4]
|
|
8012a94: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
8012a96: 687b ldr r3, [r7, #4]
|
|
8012a98: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8012a9c: b2db uxtb r3, r3
|
|
8012a9e: 3b01 subs r3, #1
|
|
8012aa0: 2b02 cmp r3, #2
|
|
8012aa2: d81e bhi.n 8012ae2 <USBD_GetStatus+0x56>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wLength != 0x2U)
|
|
8012aa4: 683b ldr r3, [r7, #0]
|
|
8012aa6: 88db ldrh r3, [r3, #6]
|
|
8012aa8: 2b02 cmp r3, #2
|
|
8012aaa: d004 beq.n 8012ab6 <USBD_GetStatus+0x2a>
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
8012aac: 6839 ldr r1, [r7, #0]
|
|
8012aae: 6878 ldr r0, [r7, #4]
|
|
8012ab0: f000 f8a5 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
8012ab4: e01a b.n 8012aec <USBD_GetStatus+0x60>
|
|
}
|
|
|
|
#if (USBD_SELF_POWERED == 1U)
|
|
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
|
|
8012ab6: 687b ldr r3, [r7, #4]
|
|
8012ab8: 2201 movs r2, #1
|
|
8012aba: 60da str r2, [r3, #12]
|
|
#else
|
|
pdev->dev_config_status = 0U;
|
|
#endif /* USBD_SELF_POWERED */
|
|
|
|
if (pdev->dev_remote_wakeup != 0U)
|
|
8012abc: 687b ldr r3, [r7, #4]
|
|
8012abe: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
|
|
8012ac2: 2b00 cmp r3, #0
|
|
8012ac4: d005 beq.n 8012ad2 <USBD_GetStatus+0x46>
|
|
{
|
|
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
|
|
8012ac6: 687b ldr r3, [r7, #4]
|
|
8012ac8: 68db ldr r3, [r3, #12]
|
|
8012aca: f043 0202 orr.w r2, r3, #2
|
|
8012ace: 687b ldr r3, [r7, #4]
|
|
8012ad0: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
|
|
8012ad2: 687b ldr r3, [r7, #4]
|
|
8012ad4: 330c adds r3, #12
|
|
8012ad6: 2202 movs r2, #2
|
|
8012ad8: 4619 mov r1, r3
|
|
8012ada: 6878 ldr r0, [r7, #4]
|
|
8012adc: f000 f90c bl 8012cf8 <USBD_CtlSendData>
|
|
break;
|
|
8012ae0: e004 b.n 8012aec <USBD_GetStatus+0x60>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8012ae2: 6839 ldr r1, [r7, #0]
|
|
8012ae4: 6878 ldr r0, [r7, #4]
|
|
8012ae6: f000 f88a bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
8012aea: bf00 nop
|
|
}
|
|
}
|
|
8012aec: bf00 nop
|
|
8012aee: 3708 adds r7, #8
|
|
8012af0: 46bd mov sp, r7
|
|
8012af2: bd80 pop {r7, pc}
|
|
|
|
08012af4 <USBD_SetFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8012af4: b580 push {r7, lr}
|
|
8012af6: b082 sub sp, #8
|
|
8012af8: af00 add r7, sp, #0
|
|
8012afa: 6078 str r0, [r7, #4]
|
|
8012afc: 6039 str r1, [r7, #0]
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8012afe: 683b ldr r3, [r7, #0]
|
|
8012b00: 885b ldrh r3, [r3, #2]
|
|
8012b02: 2b01 cmp r3, #1
|
|
8012b04: d107 bne.n 8012b16 <USBD_SetFeature+0x22>
|
|
{
|
|
pdev->dev_remote_wakeup = 1U;
|
|
8012b06: 687b ldr r3, [r7, #4]
|
|
8012b08: 2201 movs r2, #1
|
|
8012b0a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8012b0e: 6878 ldr r0, [r7, #4]
|
|
8012b10: f000 f953 bl 8012dba <USBD_CtlSendStatus>
|
|
}
|
|
else
|
|
{
|
|
USBD_CtlError(pdev, req);
|
|
}
|
|
}
|
|
8012b14: e013 b.n 8012b3e <USBD_SetFeature+0x4a>
|
|
else if (req->wValue == USB_FEATURE_TEST_MODE)
|
|
8012b16: 683b ldr r3, [r7, #0]
|
|
8012b18: 885b ldrh r3, [r3, #2]
|
|
8012b1a: 2b02 cmp r3, #2
|
|
8012b1c: d10b bne.n 8012b36 <USBD_SetFeature+0x42>
|
|
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
|
|
8012b1e: 683b ldr r3, [r7, #0]
|
|
8012b20: 889b ldrh r3, [r3, #4]
|
|
8012b22: 0a1b lsrs r3, r3, #8
|
|
8012b24: b29b uxth r3, r3
|
|
8012b26: b2da uxtb r2, r3
|
|
8012b28: 687b ldr r3, [r7, #4]
|
|
8012b2a: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8012b2e: 6878 ldr r0, [r7, #4]
|
|
8012b30: f000 f943 bl 8012dba <USBD_CtlSendStatus>
|
|
}
|
|
8012b34: e003 b.n 8012b3e <USBD_SetFeature+0x4a>
|
|
USBD_CtlError(pdev, req);
|
|
8012b36: 6839 ldr r1, [r7, #0]
|
|
8012b38: 6878 ldr r0, [r7, #4]
|
|
8012b3a: f000 f860 bl 8012bfe <USBD_CtlError>
|
|
}
|
|
8012b3e: bf00 nop
|
|
8012b40: 3708 adds r7, #8
|
|
8012b42: 46bd mov sp, r7
|
|
8012b44: bd80 pop {r7, pc}
|
|
|
|
08012b46 <USBD_ClrFeature>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8012b46: b580 push {r7, lr}
|
|
8012b48: b082 sub sp, #8
|
|
8012b4a: af00 add r7, sp, #0
|
|
8012b4c: 6078 str r0, [r7, #4]
|
|
8012b4e: 6039 str r1, [r7, #0]
|
|
switch (pdev->dev_state)
|
|
8012b50: 687b ldr r3, [r7, #4]
|
|
8012b52: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
|
|
8012b56: b2db uxtb r3, r3
|
|
8012b58: 3b01 subs r3, #1
|
|
8012b5a: 2b02 cmp r3, #2
|
|
8012b5c: d80b bhi.n 8012b76 <USBD_ClrFeature+0x30>
|
|
{
|
|
case USBD_STATE_DEFAULT:
|
|
case USBD_STATE_ADDRESSED:
|
|
case USBD_STATE_CONFIGURED:
|
|
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
|
8012b5e: 683b ldr r3, [r7, #0]
|
|
8012b60: 885b ldrh r3, [r3, #2]
|
|
8012b62: 2b01 cmp r3, #1
|
|
8012b64: d10c bne.n 8012b80 <USBD_ClrFeature+0x3a>
|
|
{
|
|
pdev->dev_remote_wakeup = 0U;
|
|
8012b66: 687b ldr r3, [r7, #4]
|
|
8012b68: 2200 movs r2, #0
|
|
8012b6a: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
|
|
(void)USBD_CtlSendStatus(pdev);
|
|
8012b6e: 6878 ldr r0, [r7, #4]
|
|
8012b70: f000 f923 bl 8012dba <USBD_CtlSendStatus>
|
|
}
|
|
break;
|
|
8012b74: e004 b.n 8012b80 <USBD_ClrFeature+0x3a>
|
|
|
|
default:
|
|
USBD_CtlError(pdev, req);
|
|
8012b76: 6839 ldr r1, [r7, #0]
|
|
8012b78: 6878 ldr r0, [r7, #4]
|
|
8012b7a: f000 f840 bl 8012bfe <USBD_CtlError>
|
|
break;
|
|
8012b7e: e000 b.n 8012b82 <USBD_ClrFeature+0x3c>
|
|
break;
|
|
8012b80: bf00 nop
|
|
}
|
|
}
|
|
8012b82: bf00 nop
|
|
8012b84: 3708 adds r7, #8
|
|
8012b86: 46bd mov sp, r7
|
|
8012b88: bd80 pop {r7, pc}
|
|
|
|
08012b8a <USBD_ParseSetupRequest>:
|
|
* @param req: usb request
|
|
* @param pdata: setup data pointer
|
|
* @retval None
|
|
*/
|
|
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
|
|
{
|
|
8012b8a: b580 push {r7, lr}
|
|
8012b8c: b084 sub sp, #16
|
|
8012b8e: af00 add r7, sp, #0
|
|
8012b90: 6078 str r0, [r7, #4]
|
|
8012b92: 6039 str r1, [r7, #0]
|
|
uint8_t *pbuff = pdata;
|
|
8012b94: 683b ldr r3, [r7, #0]
|
|
8012b96: 60fb str r3, [r7, #12]
|
|
|
|
req->bmRequest = *(uint8_t *)(pbuff);
|
|
8012b98: 68fb ldr r3, [r7, #12]
|
|
8012b9a: 781a ldrb r2, [r3, #0]
|
|
8012b9c: 687b ldr r3, [r7, #4]
|
|
8012b9e: 701a strb r2, [r3, #0]
|
|
|
|
pbuff++;
|
|
8012ba0: 68fb ldr r3, [r7, #12]
|
|
8012ba2: 3301 adds r3, #1
|
|
8012ba4: 60fb str r3, [r7, #12]
|
|
req->bRequest = *(uint8_t *)(pbuff);
|
|
8012ba6: 68fb ldr r3, [r7, #12]
|
|
8012ba8: 781a ldrb r2, [r3, #0]
|
|
8012baa: 687b ldr r3, [r7, #4]
|
|
8012bac: 705a strb r2, [r3, #1]
|
|
|
|
pbuff++;
|
|
8012bae: 68fb ldr r3, [r7, #12]
|
|
8012bb0: 3301 adds r3, #1
|
|
8012bb2: 60fb str r3, [r7, #12]
|
|
req->wValue = SWAPBYTE(pbuff);
|
|
8012bb4: 68f8 ldr r0, [r7, #12]
|
|
8012bb6: f7ff fa13 bl 8011fe0 <SWAPBYTE>
|
|
8012bba: 4603 mov r3, r0
|
|
8012bbc: 461a mov r2, r3
|
|
8012bbe: 687b ldr r3, [r7, #4]
|
|
8012bc0: 805a strh r2, [r3, #2]
|
|
|
|
pbuff++;
|
|
8012bc2: 68fb ldr r3, [r7, #12]
|
|
8012bc4: 3301 adds r3, #1
|
|
8012bc6: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8012bc8: 68fb ldr r3, [r7, #12]
|
|
8012bca: 3301 adds r3, #1
|
|
8012bcc: 60fb str r3, [r7, #12]
|
|
req->wIndex = SWAPBYTE(pbuff);
|
|
8012bce: 68f8 ldr r0, [r7, #12]
|
|
8012bd0: f7ff fa06 bl 8011fe0 <SWAPBYTE>
|
|
8012bd4: 4603 mov r3, r0
|
|
8012bd6: 461a mov r2, r3
|
|
8012bd8: 687b ldr r3, [r7, #4]
|
|
8012bda: 809a strh r2, [r3, #4]
|
|
|
|
pbuff++;
|
|
8012bdc: 68fb ldr r3, [r7, #12]
|
|
8012bde: 3301 adds r3, #1
|
|
8012be0: 60fb str r3, [r7, #12]
|
|
pbuff++;
|
|
8012be2: 68fb ldr r3, [r7, #12]
|
|
8012be4: 3301 adds r3, #1
|
|
8012be6: 60fb str r3, [r7, #12]
|
|
req->wLength = SWAPBYTE(pbuff);
|
|
8012be8: 68f8 ldr r0, [r7, #12]
|
|
8012bea: f7ff f9f9 bl 8011fe0 <SWAPBYTE>
|
|
8012bee: 4603 mov r3, r0
|
|
8012bf0: 461a mov r2, r3
|
|
8012bf2: 687b ldr r3, [r7, #4]
|
|
8012bf4: 80da strh r2, [r3, #6]
|
|
}
|
|
8012bf6: bf00 nop
|
|
8012bf8: 3710 adds r7, #16
|
|
8012bfa: 46bd mov sp, r7
|
|
8012bfc: bd80 pop {r7, pc}
|
|
|
|
08012bfe <USBD_CtlError>:
|
|
* @param pdev: device instance
|
|
* @param req: usb request
|
|
* @retval None
|
|
*/
|
|
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
|
|
{
|
|
8012bfe: b580 push {r7, lr}
|
|
8012c00: b082 sub sp, #8
|
|
8012c02: af00 add r7, sp, #0
|
|
8012c04: 6078 str r0, [r7, #4]
|
|
8012c06: 6039 str r1, [r7, #0]
|
|
UNUSED(req);
|
|
|
|
(void)USBD_LL_StallEP(pdev, 0x80U);
|
|
8012c08: 2180 movs r1, #128 @ 0x80
|
|
8012c0a: 6878 ldr r0, [r7, #4]
|
|
8012c0c: f006 fa36 bl 801907c <USBD_LL_StallEP>
|
|
(void)USBD_LL_StallEP(pdev, 0U);
|
|
8012c10: 2100 movs r1, #0
|
|
8012c12: 6878 ldr r0, [r7, #4]
|
|
8012c14: f006 fa32 bl 801907c <USBD_LL_StallEP>
|
|
}
|
|
8012c18: bf00 nop
|
|
8012c1a: 3708 adds r7, #8
|
|
8012c1c: 46bd mov sp, r7
|
|
8012c1e: bd80 pop {r7, pc}
|
|
|
|
08012c20 <USBD_GetString>:
|
|
* @param unicode : Formatted string buffer (unicode)
|
|
* @param len : descriptor length
|
|
* @retval None
|
|
*/
|
|
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
|
|
{
|
|
8012c20: b580 push {r7, lr}
|
|
8012c22: b086 sub sp, #24
|
|
8012c24: af00 add r7, sp, #0
|
|
8012c26: 60f8 str r0, [r7, #12]
|
|
8012c28: 60b9 str r1, [r7, #8]
|
|
8012c2a: 607a str r2, [r7, #4]
|
|
uint8_t idx = 0U;
|
|
8012c2c: 2300 movs r3, #0
|
|
8012c2e: 75fb strb r3, [r7, #23]
|
|
uint8_t *pdesc;
|
|
|
|
if (desc == NULL)
|
|
8012c30: 68fb ldr r3, [r7, #12]
|
|
8012c32: 2b00 cmp r3, #0
|
|
8012c34: d042 beq.n 8012cbc <USBD_GetString+0x9c>
|
|
{
|
|
return;
|
|
}
|
|
|
|
pdesc = desc;
|
|
8012c36: 68fb ldr r3, [r7, #12]
|
|
8012c38: 613b str r3, [r7, #16]
|
|
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
|
|
8012c3a: 6938 ldr r0, [r7, #16]
|
|
8012c3c: f000 f842 bl 8012cc4 <USBD_GetLen>
|
|
8012c40: 4603 mov r3, r0
|
|
8012c42: 3301 adds r3, #1
|
|
8012c44: 005b lsls r3, r3, #1
|
|
8012c46: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8012c4a: d808 bhi.n 8012c5e <USBD_GetString+0x3e>
|
|
8012c4c: 6938 ldr r0, [r7, #16]
|
|
8012c4e: f000 f839 bl 8012cc4 <USBD_GetLen>
|
|
8012c52: 4603 mov r3, r0
|
|
8012c54: 3301 adds r3, #1
|
|
8012c56: b29b uxth r3, r3
|
|
8012c58: 005b lsls r3, r3, #1
|
|
8012c5a: b29a uxth r2, r3
|
|
8012c5c: e001 b.n 8012c62 <USBD_GetString+0x42>
|
|
8012c5e: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8012c62: 687b ldr r3, [r7, #4]
|
|
8012c64: 801a strh r2, [r3, #0]
|
|
|
|
unicode[idx] = *(uint8_t *)len;
|
|
8012c66: 7dfb ldrb r3, [r7, #23]
|
|
8012c68: 68ba ldr r2, [r7, #8]
|
|
8012c6a: 4413 add r3, r2
|
|
8012c6c: 687a ldr r2, [r7, #4]
|
|
8012c6e: 7812 ldrb r2, [r2, #0]
|
|
8012c70: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8012c72: 7dfb ldrb r3, [r7, #23]
|
|
8012c74: 3301 adds r3, #1
|
|
8012c76: 75fb strb r3, [r7, #23]
|
|
unicode[idx] = USB_DESC_TYPE_STRING;
|
|
8012c78: 7dfb ldrb r3, [r7, #23]
|
|
8012c7a: 68ba ldr r2, [r7, #8]
|
|
8012c7c: 4413 add r3, r2
|
|
8012c7e: 2203 movs r2, #3
|
|
8012c80: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8012c82: 7dfb ldrb r3, [r7, #23]
|
|
8012c84: 3301 adds r3, #1
|
|
8012c86: 75fb strb r3, [r7, #23]
|
|
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8012c88: e013 b.n 8012cb2 <USBD_GetString+0x92>
|
|
{
|
|
unicode[idx] = *pdesc;
|
|
8012c8a: 7dfb ldrb r3, [r7, #23]
|
|
8012c8c: 68ba ldr r2, [r7, #8]
|
|
8012c8e: 4413 add r3, r2
|
|
8012c90: 693a ldr r2, [r7, #16]
|
|
8012c92: 7812 ldrb r2, [r2, #0]
|
|
8012c94: 701a strb r2, [r3, #0]
|
|
pdesc++;
|
|
8012c96: 693b ldr r3, [r7, #16]
|
|
8012c98: 3301 adds r3, #1
|
|
8012c9a: 613b str r3, [r7, #16]
|
|
idx++;
|
|
8012c9c: 7dfb ldrb r3, [r7, #23]
|
|
8012c9e: 3301 adds r3, #1
|
|
8012ca0: 75fb strb r3, [r7, #23]
|
|
|
|
unicode[idx] = 0U;
|
|
8012ca2: 7dfb ldrb r3, [r7, #23]
|
|
8012ca4: 68ba ldr r2, [r7, #8]
|
|
8012ca6: 4413 add r3, r2
|
|
8012ca8: 2200 movs r2, #0
|
|
8012caa: 701a strb r2, [r3, #0]
|
|
idx++;
|
|
8012cac: 7dfb ldrb r3, [r7, #23]
|
|
8012cae: 3301 adds r3, #1
|
|
8012cb0: 75fb strb r3, [r7, #23]
|
|
while (*pdesc != (uint8_t)'\0')
|
|
8012cb2: 693b ldr r3, [r7, #16]
|
|
8012cb4: 781b ldrb r3, [r3, #0]
|
|
8012cb6: 2b00 cmp r3, #0
|
|
8012cb8: d1e7 bne.n 8012c8a <USBD_GetString+0x6a>
|
|
8012cba: e000 b.n 8012cbe <USBD_GetString+0x9e>
|
|
return;
|
|
8012cbc: bf00 nop
|
|
}
|
|
}
|
|
8012cbe: 3718 adds r7, #24
|
|
8012cc0: 46bd mov sp, r7
|
|
8012cc2: bd80 pop {r7, pc}
|
|
|
|
08012cc4 <USBD_GetLen>:
|
|
* return the string length
|
|
* @param buf : pointer to the ascii string buffer
|
|
* @retval string length
|
|
*/
|
|
static uint8_t USBD_GetLen(uint8_t *buf)
|
|
{
|
|
8012cc4: b480 push {r7}
|
|
8012cc6: b085 sub sp, #20
|
|
8012cc8: af00 add r7, sp, #0
|
|
8012cca: 6078 str r0, [r7, #4]
|
|
uint8_t len = 0U;
|
|
8012ccc: 2300 movs r3, #0
|
|
8012cce: 73fb strb r3, [r7, #15]
|
|
uint8_t *pbuff = buf;
|
|
8012cd0: 687b ldr r3, [r7, #4]
|
|
8012cd2: 60bb str r3, [r7, #8]
|
|
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8012cd4: e005 b.n 8012ce2 <USBD_GetLen+0x1e>
|
|
{
|
|
len++;
|
|
8012cd6: 7bfb ldrb r3, [r7, #15]
|
|
8012cd8: 3301 adds r3, #1
|
|
8012cda: 73fb strb r3, [r7, #15]
|
|
pbuff++;
|
|
8012cdc: 68bb ldr r3, [r7, #8]
|
|
8012cde: 3301 adds r3, #1
|
|
8012ce0: 60bb str r3, [r7, #8]
|
|
while (*pbuff != (uint8_t)'\0')
|
|
8012ce2: 68bb ldr r3, [r7, #8]
|
|
8012ce4: 781b ldrb r3, [r3, #0]
|
|
8012ce6: 2b00 cmp r3, #0
|
|
8012ce8: d1f5 bne.n 8012cd6 <USBD_GetLen+0x12>
|
|
}
|
|
|
|
return len;
|
|
8012cea: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8012cec: 4618 mov r0, r3
|
|
8012cee: 3714 adds r7, #20
|
|
8012cf0: 46bd mov sp, r7
|
|
8012cf2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8012cf6: 4770 bx lr
|
|
|
|
08012cf8 <USBD_CtlSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8012cf8: b580 push {r7, lr}
|
|
8012cfa: b084 sub sp, #16
|
|
8012cfc: af00 add r7, sp, #0
|
|
8012cfe: 60f8 str r0, [r7, #12]
|
|
8012d00: 60b9 str r1, [r7, #8]
|
|
8012d02: 607a str r2, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_IN;
|
|
8012d04: 68fb ldr r3, [r7, #12]
|
|
8012d06: 2202 movs r2, #2
|
|
8012d08: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_in[0].total_length = len;
|
|
8012d0c: 68fb ldr r3, [r7, #12]
|
|
8012d0e: 687a ldr r2, [r7, #4]
|
|
8012d10: 615a str r2, [r3, #20]
|
|
pdev->ep_in[0].pbuffer = pbuf;
|
|
8012d12: 68fb ldr r3, [r7, #12]
|
|
8012d14: 68ba ldr r2, [r7, #8]
|
|
8012d16: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
|
|
pdev->ep_in[0].rem_length = 0U;
|
|
#else
|
|
pdev->ep_in[0].rem_length = len;
|
|
8012d18: 68fb ldr r3, [r7, #12]
|
|
8012d1a: 687a ldr r2, [r7, #4]
|
|
8012d1c: 619a str r2, [r3, #24]
|
|
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8012d1e: 687b ldr r3, [r7, #4]
|
|
8012d20: 68ba ldr r2, [r7, #8]
|
|
8012d22: 2100 movs r1, #0
|
|
8012d24: 68f8 ldr r0, [r7, #12]
|
|
8012d26: f006 fa32 bl 801918e <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8012d2a: 2300 movs r3, #0
|
|
}
|
|
8012d2c: 4618 mov r0, r3
|
|
8012d2e: 3710 adds r7, #16
|
|
8012d30: 46bd mov sp, r7
|
|
8012d32: bd80 pop {r7, pc}
|
|
|
|
08012d34 <USBD_CtlContinueSendData>:
|
|
* @param len: length of data to be sent
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8012d34: b580 push {r7, lr}
|
|
8012d36: b084 sub sp, #16
|
|
8012d38: af00 add r7, sp, #0
|
|
8012d3a: 60f8 str r0, [r7, #12]
|
|
8012d3c: 60b9 str r1, [r7, #8]
|
|
8012d3e: 607a str r2, [r7, #4]
|
|
/* Start the next transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
|
|
8012d40: 687b ldr r3, [r7, #4]
|
|
8012d42: 68ba ldr r2, [r7, #8]
|
|
8012d44: 2100 movs r1, #0
|
|
8012d46: 68f8 ldr r0, [r7, #12]
|
|
8012d48: f006 fa21 bl 801918e <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8012d4c: 2300 movs r3, #0
|
|
}
|
|
8012d4e: 4618 mov r0, r3
|
|
8012d50: 3710 adds r7, #16
|
|
8012d52: 46bd mov sp, r7
|
|
8012d54: bd80 pop {r7, pc}
|
|
|
|
08012d56 <USBD_CtlPrepareRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8012d56: b580 push {r7, lr}
|
|
8012d58: b084 sub sp, #16
|
|
8012d5a: af00 add r7, sp, #0
|
|
8012d5c: 60f8 str r0, [r7, #12]
|
|
8012d5e: 60b9 str r1, [r7, #8]
|
|
8012d60: 607a str r2, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_DATA_OUT;
|
|
8012d62: 68fb ldr r3, [r7, #12]
|
|
8012d64: 2203 movs r2, #3
|
|
8012d66: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
pdev->ep_out[0].total_length = len;
|
|
8012d6a: 68fb ldr r3, [r7, #12]
|
|
8012d6c: 687a ldr r2, [r7, #4]
|
|
8012d6e: f8c3 2154 str.w r2, [r3, #340] @ 0x154
|
|
pdev->ep_out[0].pbuffer = pbuf;
|
|
8012d72: 68fb ldr r3, [r7, #12]
|
|
8012d74: 68ba ldr r2, [r7, #8]
|
|
8012d76: f8c3 2164 str.w r2, [r3, #356] @ 0x164
|
|
|
|
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
|
|
pdev->ep_out[0].rem_length = 0U;
|
|
#else
|
|
pdev->ep_out[0].rem_length = len;
|
|
8012d7a: 68fb ldr r3, [r7, #12]
|
|
8012d7c: 687a ldr r2, [r7, #4]
|
|
8012d7e: f8c3 2158 str.w r2, [r3, #344] @ 0x158
|
|
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
8012d82: 687b ldr r3, [r7, #4]
|
|
8012d84: 68ba ldr r2, [r7, #8]
|
|
8012d86: 2100 movs r1, #0
|
|
8012d88: 68f8 ldr r0, [r7, #12]
|
|
8012d8a: f006 fa21 bl 80191d0 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8012d8e: 2300 movs r3, #0
|
|
}
|
|
8012d90: 4618 mov r0, r3
|
|
8012d92: 3710 adds r7, #16
|
|
8012d94: 46bd mov sp, r7
|
|
8012d96: bd80 pop {r7, pc}
|
|
|
|
08012d98 <USBD_CtlContinueRx>:
|
|
* @param len: length of data to be received
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
|
|
uint8_t *pbuf, uint32_t len)
|
|
{
|
|
8012d98: b580 push {r7, lr}
|
|
8012d9a: b084 sub sp, #16
|
|
8012d9c: af00 add r7, sp, #0
|
|
8012d9e: 60f8 str r0, [r7, #12]
|
|
8012da0: 60b9 str r1, [r7, #8]
|
|
8012da2: 607a str r2, [r7, #4]
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
|
|
8012da4: 687b ldr r3, [r7, #4]
|
|
8012da6: 68ba ldr r2, [r7, #8]
|
|
8012da8: 2100 movs r1, #0
|
|
8012daa: 68f8 ldr r0, [r7, #12]
|
|
8012dac: f006 fa10 bl 80191d0 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8012db0: 2300 movs r3, #0
|
|
}
|
|
8012db2: 4618 mov r0, r3
|
|
8012db4: 3710 adds r7, #16
|
|
8012db6: 46bd mov sp, r7
|
|
8012db8: bd80 pop {r7, pc}
|
|
|
|
08012dba <USBD_CtlSendStatus>:
|
|
* send zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8012dba: b580 push {r7, lr}
|
|
8012dbc: b082 sub sp, #8
|
|
8012dbe: af00 add r7, sp, #0
|
|
8012dc0: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_IN;
|
|
8012dc2: 687b ldr r3, [r7, #4]
|
|
8012dc4: 2204 movs r2, #4
|
|
8012dc6: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
|
|
8012dca: 2300 movs r3, #0
|
|
8012dcc: 2200 movs r2, #0
|
|
8012dce: 2100 movs r1, #0
|
|
8012dd0: 6878 ldr r0, [r7, #4]
|
|
8012dd2: f006 f9dc bl 801918e <USBD_LL_Transmit>
|
|
|
|
return USBD_OK;
|
|
8012dd6: 2300 movs r3, #0
|
|
}
|
|
8012dd8: 4618 mov r0, r3
|
|
8012dda: 3708 adds r7, #8
|
|
8012ddc: 46bd mov sp, r7
|
|
8012dde: bd80 pop {r7, pc}
|
|
|
|
08012de0 <USBD_CtlReceiveStatus>:
|
|
* receive zero lzngth packet on the ctl pipe
|
|
* @param pdev: device instance
|
|
* @retval status
|
|
*/
|
|
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8012de0: b580 push {r7, lr}
|
|
8012de2: b082 sub sp, #8
|
|
8012de4: af00 add r7, sp, #0
|
|
8012de6: 6078 str r0, [r7, #4]
|
|
/* Set EP0 State */
|
|
pdev->ep0_state = USBD_EP0_STATUS_OUT;
|
|
8012de8: 687b ldr r3, [r7, #4]
|
|
8012dea: 2205 movs r2, #5
|
|
8012dec: f8c3 2294 str.w r2, [r3, #660] @ 0x294
|
|
|
|
/* Start the transfer */
|
|
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
|
|
8012df0: 2300 movs r3, #0
|
|
8012df2: 2200 movs r2, #0
|
|
8012df4: 2100 movs r1, #0
|
|
8012df6: 6878 ldr r0, [r7, #4]
|
|
8012df8: f006 f9ea bl 80191d0 <USBD_LL_PrepareReceive>
|
|
|
|
return USBD_OK;
|
|
8012dfc: 2300 movs r3, #0
|
|
}
|
|
8012dfe: 4618 mov r0, r3
|
|
8012e00: 3708 adds r7, #8
|
|
8012e02: 46bd mov sp, r7
|
|
8012e04: bd80 pop {r7, pc}
|
|
|
|
08012e06 <SHCI_C2_DEBUG_Init>:
|
|
|
|
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
|
|
}
|
|
|
|
SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket )
|
|
{
|
|
8012e06: b580 push {r7, lr}
|
|
8012e08: b088 sub sp, #32
|
|
8012e0a: af00 add r7, sp, #0
|
|
8012e0c: 6078 str r0, [r7, #4]
|
|
* Buffer is large enough to hold command complete without payload
|
|
*/
|
|
uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE];
|
|
TL_EvtPacket_t * p_rsp;
|
|
|
|
p_rsp = (TL_EvtPacket_t *)local_buffer;
|
|
8012e0e: f107 030c add.w r3, r7, #12
|
|
8012e12: 61fb str r3, [r7, #28]
|
|
|
|
shci_send( SHCI_OPCODE_C2_DEBUG_INIT,
|
|
sizeof( SHCI_C2_DEBUG_init_Cmd_Param_t ),
|
|
(uint8_t*)&pCmdPacket->Param,
|
|
8012e14: 687b ldr r3, [r7, #4]
|
|
8012e16: f103 020c add.w r2, r3, #12
|
|
shci_send( SHCI_OPCODE_C2_DEBUG_INIT,
|
|
8012e1a: 69fb ldr r3, [r7, #28]
|
|
8012e1c: 210f movs r1, #15
|
|
8012e1e: f64f 4068 movw r0, #64616 @ 0xfc68
|
|
8012e22: f000 f935 bl 8013090 <shci_send>
|
|
p_rsp );
|
|
|
|
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
|
|
8012e26: 69fb ldr r3, [r7, #28]
|
|
8012e28: 330b adds r3, #11
|
|
8012e2a: 78db ldrb r3, [r3, #3]
|
|
}
|
|
8012e2c: 4618 mov r0, r3
|
|
8012e2e: 3720 adds r7, #32
|
|
8012e30: 46bd mov sp, r7
|
|
8012e32: bd80 pop {r7, pc}
|
|
|
|
08012e34 <SHCI_C2_Config>:
|
|
|
|
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
|
|
}
|
|
|
|
SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket)
|
|
{
|
|
8012e34: b580 push {r7, lr}
|
|
8012e36: b088 sub sp, #32
|
|
8012e38: af00 add r7, sp, #0
|
|
8012e3a: 6078 str r0, [r7, #4]
|
|
* Buffer is large enough to hold command complete without payload
|
|
*/
|
|
uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE];
|
|
TL_EvtPacket_t * p_rsp;
|
|
|
|
p_rsp = (TL_EvtPacket_t *)local_buffer;
|
|
8012e3c: f107 030c add.w r3, r7, #12
|
|
8012e40: 61fb str r3, [r7, #28]
|
|
|
|
shci_send( SHCI_OPCODE_C2_CONFIG,
|
|
8012e42: 69fb ldr r3, [r7, #28]
|
|
8012e44: 687a ldr r2, [r7, #4]
|
|
8012e46: 2110 movs r1, #16
|
|
8012e48: f64f 4075 movw r0, #64629 @ 0xfc75
|
|
8012e4c: f000 f920 bl 8013090 <shci_send>
|
|
sizeof(SHCI_C2_CONFIG_Cmd_Param_t),
|
|
(uint8_t*)pCmdPacket,
|
|
p_rsp );
|
|
|
|
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
|
|
8012e50: 69fb ldr r3, [r7, #28]
|
|
8012e52: 330b adds r3, #11
|
|
8012e54: 78db ldrb r3, [r3, #3]
|
|
}
|
|
8012e56: 4618 mov r0, r3
|
|
8012e58: 3720 adds r7, #32
|
|
8012e5a: 46bd mov sp, r7
|
|
8012e5c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08012e60 <SHCI_GetWirelessFwInfo>:
|
|
* Local System COMMAND
|
|
* These commands are NOT sent to the CPU2
|
|
*/
|
|
|
|
SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo )
|
|
{
|
|
8012e60: b480 push {r7}
|
|
8012e62: b08b sub sp, #44 @ 0x2c
|
|
8012e64: af00 add r7, sp, #0
|
|
8012e66: 6078 str r0, [r7, #4]
|
|
uint32_t ipccdba = 0;
|
|
8012e68: 2300 movs r3, #0
|
|
8012e6a: 613b str r3, [r7, #16]
|
|
MB_RefTable_t * p_RefTable = NULL;
|
|
8012e6c: 2300 movs r3, #0
|
|
8012e6e: 60fb str r3, [r7, #12]
|
|
uint32_t wireless_firmware_version = 0;
|
|
8012e70: 2300 movs r3, #0
|
|
8012e72: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t wireless_firmware_memorySize = 0;
|
|
8012e74: 2300 movs r3, #0
|
|
8012e76: 623b str r3, [r7, #32]
|
|
uint32_t wireless_firmware_infoStack = 0;
|
|
8012e78: 2300 movs r3, #0
|
|
8012e7a: 61fb str r3, [r7, #28]
|
|
MB_FUS_DeviceInfoTable_t * p_fus_device_info_table = NULL;
|
|
8012e7c: 2300 movs r3, #0
|
|
8012e7e: 60bb str r3, [r7, #8]
|
|
uint32_t fus_version = 0;
|
|
8012e80: 2300 movs r3, #0
|
|
8012e82: 61bb str r3, [r7, #24]
|
|
uint32_t fus_memorySize = 0;
|
|
8012e84: 2300 movs r3, #0
|
|
8012e86: 617b str r3, [r7, #20]
|
|
|
|
ipccdba = READ_BIT( FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA );
|
|
8012e88: 4b4a ldr r3, [pc, #296] @ (8012fb4 <SHCI_GetWirelessFwInfo+0x154>)
|
|
8012e8a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8012e8c: f3c3 030d ubfx r3, r3, #0, #14
|
|
8012e90: 613b str r3, [r7, #16]
|
|
/**
|
|
* The Device Info Table mapping depends on which firmware is running on CPU2.
|
|
* If the FUS is running on CPU2, FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD shall be written in the table.
|
|
* Otherwise, it means the Wireless Firmware is running on the CPU2
|
|
*/
|
|
p_fus_device_info_table = (MB_FUS_DeviceInfoTable_t*)(*(uint32_t*)((ipccdba<<2) + SRAM2A_BASE));
|
|
8012e92: 693b ldr r3, [r7, #16]
|
|
8012e94: 009b lsls r3, r3, #2
|
|
8012e96: f103 5300 add.w r3, r3, #536870912 @ 0x20000000
|
|
8012e9a: f503 3340 add.w r3, r3, #196608 @ 0x30000
|
|
8012e9e: 681b ldr r3, [r3, #0]
|
|
8012ea0: 60bb str r3, [r7, #8]
|
|
|
|
if(p_fus_device_info_table->DeviceInfoTableState == FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD)
|
|
8012ea2: 68bb ldr r3, [r7, #8]
|
|
8012ea4: 681b ldr r3, [r3, #0]
|
|
8012ea6: 4a44 ldr r2, [pc, #272] @ (8012fb8 <SHCI_GetWirelessFwInfo+0x158>)
|
|
8012ea8: 4293 cmp r3, r2
|
|
8012eaa: d10f bne.n 8012ecc <SHCI_GetWirelessFwInfo+0x6c>
|
|
/* The FUS is running on CPU2 */
|
|
/**
|
|
* Retrieve the WirelessFwInfoTable
|
|
* This table is stored in RAM at startup during the TL (transport layer) initialization
|
|
*/
|
|
wireless_firmware_version = p_fus_device_info_table->WirelessStackVersion;
|
|
8012eac: 68bb ldr r3, [r7, #8]
|
|
8012eae: 695b ldr r3, [r3, #20]
|
|
8012eb0: 627b str r3, [r7, #36] @ 0x24
|
|
wireless_firmware_memorySize = p_fus_device_info_table->WirelessStackMemorySize;
|
|
8012eb2: 68bb ldr r3, [r7, #8]
|
|
8012eb4: 699b ldr r3, [r3, #24]
|
|
8012eb6: 623b str r3, [r7, #32]
|
|
wireless_firmware_infoStack = p_fus_device_info_table->WirelessFirmwareBleInfo;
|
|
8012eb8: 68bb ldr r3, [r7, #8]
|
|
8012eba: 69db ldr r3, [r3, #28]
|
|
8012ebc: 61fb str r3, [r7, #28]
|
|
|
|
/**
|
|
* Retrieve the FusInfoTable
|
|
* This table is stored in RAM at startup during the TL (transport layer) initialization
|
|
*/
|
|
fus_version = p_fus_device_info_table->FusVersion;
|
|
8012ebe: 68bb ldr r3, [r7, #8]
|
|
8012ec0: 68db ldr r3, [r3, #12]
|
|
8012ec2: 61bb str r3, [r7, #24]
|
|
fus_memorySize = p_fus_device_info_table->FusMemorySize;
|
|
8012ec4: 68bb ldr r3, [r7, #8]
|
|
8012ec6: 691b ldr r3, [r3, #16]
|
|
8012ec8: 617b str r3, [r7, #20]
|
|
8012eca: e01a b.n 8012f02 <SHCI_GetWirelessFwInfo+0xa2>
|
|
}
|
|
else
|
|
{
|
|
/* The Wireless Firmware is running on CPU2 */
|
|
p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE);
|
|
8012ecc: 693b ldr r3, [r7, #16]
|
|
8012ece: 009b lsls r3, r3, #2
|
|
8012ed0: f103 5300 add.w r3, r3, #536870912 @ 0x20000000
|
|
8012ed4: f503 3340 add.w r3, r3, #196608 @ 0x30000
|
|
8012ed8: 60fb str r3, [r7, #12]
|
|
|
|
/**
|
|
* Retrieve the WirelessFwInfoTable
|
|
* This table is stored in RAM at startup during the TL (transport layer) initialization
|
|
*/
|
|
wireless_firmware_version = p_RefTable->p_device_info_table->WirelessFwInfoTable.Version;
|
|
8012eda: 68fb ldr r3, [r7, #12]
|
|
8012edc: 681b ldr r3, [r3, #0]
|
|
8012ede: 691b ldr r3, [r3, #16]
|
|
8012ee0: 627b str r3, [r7, #36] @ 0x24
|
|
wireless_firmware_memorySize = p_RefTable->p_device_info_table->WirelessFwInfoTable.MemorySize;
|
|
8012ee2: 68fb ldr r3, [r7, #12]
|
|
8012ee4: 681b ldr r3, [r3, #0]
|
|
8012ee6: 695b ldr r3, [r3, #20]
|
|
8012ee8: 623b str r3, [r7, #32]
|
|
wireless_firmware_infoStack = p_RefTable->p_device_info_table->WirelessFwInfoTable.InfoStack;
|
|
8012eea: 68fb ldr r3, [r7, #12]
|
|
8012eec: 681b ldr r3, [r3, #0]
|
|
8012eee: 699b ldr r3, [r3, #24]
|
|
8012ef0: 61fb str r3, [r7, #28]
|
|
|
|
/**
|
|
* Retrieve the FusInfoTable
|
|
* This table is stored in RAM at startup during the TL (transport layer) initialization
|
|
*/
|
|
fus_version = p_RefTable->p_device_info_table->FusInfoTable.Version;
|
|
8012ef2: 68fb ldr r3, [r7, #12]
|
|
8012ef4: 681b ldr r3, [r3, #0]
|
|
8012ef6: 685b ldr r3, [r3, #4]
|
|
8012ef8: 61bb str r3, [r7, #24]
|
|
fus_memorySize = p_RefTable->p_device_info_table->FusInfoTable.MemorySize;
|
|
8012efa: 68fb ldr r3, [r7, #12]
|
|
8012efc: 681b ldr r3, [r3, #0]
|
|
8012efe: 689b ldr r3, [r3, #8]
|
|
8012f00: 617b str r3, [r7, #20]
|
|
|
|
/**
|
|
* Retrieve the WirelessFwInfoTable
|
|
* This table is stored in RAM at startup during the TL (transport layer) initialization
|
|
*/
|
|
pWirelessInfo->VersionMajor = ((wireless_firmware_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET);
|
|
8012f02: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8012f04: 0e1b lsrs r3, r3, #24
|
|
8012f06: b2da uxtb r2, r3
|
|
8012f08: 687b ldr r3, [r7, #4]
|
|
8012f0a: 701a strb r2, [r3, #0]
|
|
pWirelessInfo->VersionMinor = ((wireless_firmware_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET);
|
|
8012f0c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8012f0e: 0c1b lsrs r3, r3, #16
|
|
8012f10: b2da uxtb r2, r3
|
|
8012f12: 687b ldr r3, [r7, #4]
|
|
8012f14: 705a strb r2, [r3, #1]
|
|
pWirelessInfo->VersionSub = ((wireless_firmware_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET);
|
|
8012f16: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8012f18: 0a1b lsrs r3, r3, #8
|
|
8012f1a: b2da uxtb r2, r3
|
|
8012f1c: 687b ldr r3, [r7, #4]
|
|
8012f1e: 709a strb r2, [r3, #2]
|
|
pWirelessInfo->VersionBranch = ((wireless_firmware_version & INFO_VERSION_BRANCH_MASK) >> INFO_VERSION_BRANCH_OFFSET);
|
|
8012f20: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8012f22: 091b lsrs r3, r3, #4
|
|
8012f24: b2db uxtb r3, r3
|
|
8012f26: f003 030f and.w r3, r3, #15
|
|
8012f2a: b2da uxtb r2, r3
|
|
8012f2c: 687b ldr r3, [r7, #4]
|
|
8012f2e: 70da strb r2, [r3, #3]
|
|
pWirelessInfo->VersionReleaseType = ((wireless_firmware_version & INFO_VERSION_TYPE_MASK) >> INFO_VERSION_TYPE_OFFSET);
|
|
8012f30: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8012f32: b2db uxtb r3, r3
|
|
8012f34: f003 030f and.w r3, r3, #15
|
|
8012f38: b2da uxtb r2, r3
|
|
8012f3a: 687b ldr r3, [r7, #4]
|
|
8012f3c: 711a strb r2, [r3, #4]
|
|
|
|
pWirelessInfo->MemorySizeSram2B = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET);
|
|
8012f3e: 6a3b ldr r3, [r7, #32]
|
|
8012f40: 0e1b lsrs r3, r3, #24
|
|
8012f42: b2da uxtb r2, r3
|
|
8012f44: 687b ldr r3, [r7, #4]
|
|
8012f46: 715a strb r2, [r3, #5]
|
|
pWirelessInfo->MemorySizeSram2A = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET);
|
|
8012f48: 6a3b ldr r3, [r7, #32]
|
|
8012f4a: 0c1b lsrs r3, r3, #16
|
|
8012f4c: b2da uxtb r2, r3
|
|
8012f4e: 687b ldr r3, [r7, #4]
|
|
8012f50: 719a strb r2, [r3, #6]
|
|
pWirelessInfo->MemorySizeSram1 = ((wireless_firmware_memorySize & INFO_SIZE_SRAM1_MASK) >> INFO_SIZE_SRAM1_OFFSET);
|
|
8012f52: 6a3b ldr r3, [r7, #32]
|
|
8012f54: 0a1b lsrs r3, r3, #8
|
|
8012f56: b2da uxtb r2, r3
|
|
8012f58: 687b ldr r3, [r7, #4]
|
|
8012f5a: 71da strb r2, [r3, #7]
|
|
pWirelessInfo->MemorySizeFlash = ((wireless_firmware_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET);
|
|
8012f5c: 6a3b ldr r3, [r7, #32]
|
|
8012f5e: b2da uxtb r2, r3
|
|
8012f60: 687b ldr r3, [r7, #4]
|
|
8012f62: 721a strb r2, [r3, #8]
|
|
|
|
pWirelessInfo->StackType = ((wireless_firmware_infoStack & INFO_STACK_TYPE_MASK) >> INFO_STACK_TYPE_OFFSET);
|
|
8012f64: 69fb ldr r3, [r7, #28]
|
|
8012f66: b2da uxtb r2, r3
|
|
8012f68: 687b ldr r3, [r7, #4]
|
|
8012f6a: 725a strb r2, [r3, #9]
|
|
|
|
/**
|
|
* Retrieve the FusInfoTable
|
|
* This table is stored in RAM at startup during the TL (transport layer) initialization
|
|
*/
|
|
pWirelessInfo->FusVersionMajor = ((fus_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET);
|
|
8012f6c: 69bb ldr r3, [r7, #24]
|
|
8012f6e: 0e1b lsrs r3, r3, #24
|
|
8012f70: b2da uxtb r2, r3
|
|
8012f72: 687b ldr r3, [r7, #4]
|
|
8012f74: 729a strb r2, [r3, #10]
|
|
pWirelessInfo->FusVersionMinor = ((fus_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET);
|
|
8012f76: 69bb ldr r3, [r7, #24]
|
|
8012f78: 0c1b lsrs r3, r3, #16
|
|
8012f7a: b2da uxtb r2, r3
|
|
8012f7c: 687b ldr r3, [r7, #4]
|
|
8012f7e: 72da strb r2, [r3, #11]
|
|
pWirelessInfo->FusVersionSub = ((fus_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET);
|
|
8012f80: 69bb ldr r3, [r7, #24]
|
|
8012f82: 0a1b lsrs r3, r3, #8
|
|
8012f84: b2da uxtb r2, r3
|
|
8012f86: 687b ldr r3, [r7, #4]
|
|
8012f88: 731a strb r2, [r3, #12]
|
|
|
|
pWirelessInfo->FusMemorySizeSram2B = ((fus_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET);
|
|
8012f8a: 697b ldr r3, [r7, #20]
|
|
8012f8c: 0e1b lsrs r3, r3, #24
|
|
8012f8e: b2da uxtb r2, r3
|
|
8012f90: 687b ldr r3, [r7, #4]
|
|
8012f92: 735a strb r2, [r3, #13]
|
|
pWirelessInfo->FusMemorySizeSram2A = ((fus_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET);
|
|
8012f94: 697b ldr r3, [r7, #20]
|
|
8012f96: 0c1b lsrs r3, r3, #16
|
|
8012f98: b2da uxtb r2, r3
|
|
8012f9a: 687b ldr r3, [r7, #4]
|
|
8012f9c: 739a strb r2, [r3, #14]
|
|
pWirelessInfo->FusMemorySizeFlash = ((fus_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET);
|
|
8012f9e: 697b ldr r3, [r7, #20]
|
|
8012fa0: b2da uxtb r2, r3
|
|
8012fa2: 687b ldr r3, [r7, #4]
|
|
8012fa4: 73da strb r2, [r3, #15]
|
|
|
|
return (SHCI_Success);
|
|
8012fa6: 2300 movs r3, #0
|
|
}
|
|
8012fa8: 4618 mov r0, r3
|
|
8012faa: 372c adds r7, #44 @ 0x2c
|
|
8012fac: 46bd mov sp, r7
|
|
8012fae: f85d 7b04 ldr.w r7, [sp], #4
|
|
8012fb2: 4770 bx lr
|
|
8012fb4: 58004000 .word 0x58004000
|
|
8012fb8: a94656b9 .word 0xa94656b9
|
|
|
|
08012fbc <shci_init>:
|
|
static void TlUserEvtReceived(TL_EvtPacket_t *shcievt);
|
|
static void TlInit( TL_CmdPacket_t * p_cmdbuffer );
|
|
|
|
/* Interface ------- ---------------------------------------------------------*/
|
|
void shci_init(void(* UserEvtRx)(void* pData), void* pConf)
|
|
{
|
|
8012fbc: b580 push {r7, lr}
|
|
8012fbe: b082 sub sp, #8
|
|
8012fc0: af00 add r7, sp, #0
|
|
8012fc2: 6078 str r0, [r7, #4]
|
|
8012fc4: 6039 str r1, [r7, #0]
|
|
StatusNotCallBackFunction = ((SHCI_TL_HciInitConf_t *)pConf)->StatusNotCallBack;
|
|
8012fc6: 683b ldr r3, [r7, #0]
|
|
8012fc8: 685b ldr r3, [r3, #4]
|
|
8012fca: 4a08 ldr r2, [pc, #32] @ (8012fec <shci_init+0x30>)
|
|
8012fcc: 6013 str r3, [r2, #0]
|
|
shciContext.UserEvtRx = UserEvtRx;
|
|
8012fce: 4a08 ldr r2, [pc, #32] @ (8012ff0 <shci_init+0x34>)
|
|
8012fd0: 687b ldr r3, [r7, #4]
|
|
8012fd2: 61d3 str r3, [r2, #28]
|
|
|
|
shci_register_io_bus (&shciContext.io);
|
|
8012fd4: 4806 ldr r0, [pc, #24] @ (8012ff0 <shci_init+0x34>)
|
|
8012fd6: f000 f915 bl 8013204 <shci_register_io_bus>
|
|
|
|
TlInit((TL_CmdPacket_t *)(((SHCI_TL_HciInitConf_t *)pConf)->p_cmdbuffer));
|
|
8012fda: 683b ldr r3, [r7, #0]
|
|
8012fdc: 681b ldr r3, [r3, #0]
|
|
8012fde: 4618 mov r0, r3
|
|
8012fe0: f000 f898 bl 8013114 <TlInit>
|
|
|
|
return;
|
|
8012fe4: bf00 nop
|
|
}
|
|
8012fe6: 3708 adds r7, #8
|
|
8012fe8: 46bd mov sp, r7
|
|
8012fea: bd80 pop {r7, pc}
|
|
8012fec: 200007a8 .word 0x200007a8
|
|
8012ff0: 20000788 .word 0x20000788
|
|
|
|
08012ff4 <shci_user_evt_proc>:
|
|
|
|
void shci_user_evt_proc(void)
|
|
{
|
|
8012ff4: b580 push {r7, lr}
|
|
8012ff6: b084 sub sp, #16
|
|
8012ff8: af00 add r7, sp, #0
|
|
|
|
/**
|
|
* It is more secure to use LST_remove_head()/LST_insert_head() compare to LST_get_next_node()/LST_remove_node()
|
|
* in case the user overwrite the header where the next/prev pointers are located
|
|
*/
|
|
if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable))
|
|
8012ffa: 4822 ldr r0, [pc, #136] @ (8013084 <shci_user_evt_proc+0x90>)
|
|
8012ffc: f000 fb52 bl 80136a4 <LST_is_empty>
|
|
8013000: 4603 mov r3, r0
|
|
8013002: 2b00 cmp r3, #0
|
|
8013004: d12b bne.n 801305e <shci_user_evt_proc+0x6a>
|
|
8013006: 4b20 ldr r3, [pc, #128] @ (8013088 <shci_user_evt_proc+0x94>)
|
|
8013008: 781b ldrb r3, [r3, #0]
|
|
801300a: 2b00 cmp r3, #0
|
|
801300c: d027 beq.n 801305e <shci_user_evt_proc+0x6a>
|
|
{
|
|
LST_remove_head ( &SHciAsynchEventQueue, (tListNode **)&phcievtbuffer );
|
|
801300e: f107 030c add.w r3, r7, #12
|
|
8013012: 4619 mov r1, r3
|
|
8013014: 481b ldr r0, [pc, #108] @ (8013084 <shci_user_evt_proc+0x90>)
|
|
8013016: f000 fbd4 bl 80137c2 <LST_remove_head>
|
|
|
|
if (shciContext.UserEvtRx != NULL)
|
|
801301a: 4b1c ldr r3, [pc, #112] @ (801308c <shci_user_evt_proc+0x98>)
|
|
801301c: 69db ldr r3, [r3, #28]
|
|
801301e: 2b00 cmp r3, #0
|
|
8013020: d00c beq.n 801303c <shci_user_evt_proc+0x48>
|
|
{
|
|
UserEvtRxParam.pckt = phcievtbuffer;
|
|
8013022: 68fb ldr r3, [r7, #12]
|
|
8013024: 60bb str r3, [r7, #8]
|
|
UserEvtRxParam.status = SHCI_TL_UserEventFlow_Enable;
|
|
8013026: 2301 movs r3, #1
|
|
8013028: 713b strb r3, [r7, #4]
|
|
shciContext.UserEvtRx((void *)&UserEvtRxParam);
|
|
801302a: 4b18 ldr r3, [pc, #96] @ (801308c <shci_user_evt_proc+0x98>)
|
|
801302c: 69db ldr r3, [r3, #28]
|
|
801302e: 1d3a adds r2, r7, #4
|
|
8013030: 4610 mov r0, r2
|
|
8013032: 4798 blx r3
|
|
SHCI_TL_UserEventFlow = UserEvtRxParam.status;
|
|
8013034: 793a ldrb r2, [r7, #4]
|
|
8013036: 4b14 ldr r3, [pc, #80] @ (8013088 <shci_user_evt_proc+0x94>)
|
|
8013038: 701a strb r2, [r3, #0]
|
|
801303a: e002 b.n 8013042 <shci_user_evt_proc+0x4e>
|
|
}
|
|
else
|
|
{
|
|
SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable;
|
|
801303c: 4b12 ldr r3, [pc, #72] @ (8013088 <shci_user_evt_proc+0x94>)
|
|
801303e: 2201 movs r2, #1
|
|
8013040: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if(SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable)
|
|
8013042: 4b11 ldr r3, [pc, #68] @ (8013088 <shci_user_evt_proc+0x94>)
|
|
8013044: 781b ldrb r3, [r3, #0]
|
|
8013046: 2b00 cmp r3, #0
|
|
8013048: d004 beq.n 8013054 <shci_user_evt_proc+0x60>
|
|
{
|
|
TL_MM_EvtDone( phcievtbuffer );
|
|
801304a: 68fb ldr r3, [r7, #12]
|
|
801304c: 4618 mov r0, r3
|
|
801304e: f000 fa25 bl 801349c <TL_MM_EvtDone>
|
|
8013052: e004 b.n 801305e <shci_user_evt_proc+0x6a>
|
|
else
|
|
{
|
|
/**
|
|
* put back the event in the queue
|
|
*/
|
|
LST_insert_head ( &SHciAsynchEventQueue, (tListNode *)phcievtbuffer );
|
|
8013054: 68fb ldr r3, [r7, #12]
|
|
8013056: 4619 mov r1, r3
|
|
8013058: 480a ldr r0, [pc, #40] @ (8013084 <shci_user_evt_proc+0x90>)
|
|
801305a: f000 fb45 bl 80136e8 <LST_insert_head>
|
|
}
|
|
}
|
|
|
|
if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable))
|
|
801305e: 4809 ldr r0, [pc, #36] @ (8013084 <shci_user_evt_proc+0x90>)
|
|
8013060: f000 fb20 bl 80136a4 <LST_is_empty>
|
|
8013064: 4603 mov r3, r0
|
|
8013066: 2b00 cmp r3, #0
|
|
8013068: d107 bne.n 801307a <shci_user_evt_proc+0x86>
|
|
801306a: 4b07 ldr r3, [pc, #28] @ (8013088 <shci_user_evt_proc+0x94>)
|
|
801306c: 781b ldrb r3, [r3, #0]
|
|
801306e: 2b00 cmp r3, #0
|
|
8013070: d003 beq.n 801307a <shci_user_evt_proc+0x86>
|
|
{
|
|
shci_notify_asynch_evt((void*) &SHciAsynchEventQueue);
|
|
8013072: 4804 ldr r0, [pc, #16] @ (8013084 <shci_user_evt_proc+0x90>)
|
|
8013074: f7ef faf6 bl 8002664 <shci_notify_asynch_evt>
|
|
}
|
|
|
|
|
|
return;
|
|
8013078: bf00 nop
|
|
801307a: bf00 nop
|
|
}
|
|
801307c: 3710 adds r7, #16
|
|
801307e: 46bd mov sp, r7
|
|
8013080: bd80 pop {r7, pc}
|
|
8013082: bf00 nop
|
|
8013084: 200002d8 .word 0x200002d8
|
|
8013088: 200002e8 .word 0x200002e8
|
|
801308c: 20000788 .word 0x20000788
|
|
|
|
08013090 <shci_send>:
|
|
|
|
return;
|
|
}
|
|
|
|
void shci_send( uint16_t cmd_code, uint8_t len_cmd_payload, uint8_t * p_cmd_payload, TL_EvtPacket_t * p_rsp )
|
|
{
|
|
8013090: b580 push {r7, lr}
|
|
8013092: b084 sub sp, #16
|
|
8013094: af00 add r7, sp, #0
|
|
8013096: 60ba str r2, [r7, #8]
|
|
8013098: 607b str r3, [r7, #4]
|
|
801309a: 4603 mov r3, r0
|
|
801309c: 81fb strh r3, [r7, #14]
|
|
801309e: 460b mov r3, r1
|
|
80130a0: 737b strb r3, [r7, #13]
|
|
Cmd_SetStatus(SHCI_TL_CmdBusy);
|
|
80130a2: 2000 movs r0, #0
|
|
80130a4: f000 f868 bl 8013178 <Cmd_SetStatus>
|
|
|
|
pCmdBuffer->cmdserial.cmd.cmdcode = cmd_code;
|
|
80130a8: 4b17 ldr r3, [pc, #92] @ (8013108 <shci_send+0x78>)
|
|
80130aa: 681b ldr r3, [r3, #0]
|
|
80130ac: 89fa ldrh r2, [r7, #14]
|
|
80130ae: f8a3 2009 strh.w r2, [r3, #9]
|
|
pCmdBuffer->cmdserial.cmd.plen = len_cmd_payload;
|
|
80130b2: 4b15 ldr r3, [pc, #84] @ (8013108 <shci_send+0x78>)
|
|
80130b4: 681b ldr r3, [r3, #0]
|
|
80130b6: 7b7a ldrb r2, [r7, #13]
|
|
80130b8: 72da strb r2, [r3, #11]
|
|
|
|
memcpy(pCmdBuffer->cmdserial.cmd.payload, p_cmd_payload, len_cmd_payload );
|
|
80130ba: 4b13 ldr r3, [pc, #76] @ (8013108 <shci_send+0x78>)
|
|
80130bc: 681b ldr r3, [r3, #0]
|
|
80130be: 330c adds r3, #12
|
|
80130c0: 7b7a ldrb r2, [r7, #13]
|
|
80130c2: 68b9 ldr r1, [r7, #8]
|
|
80130c4: 4618 mov r0, r3
|
|
80130c6: f007 f9fa bl 801a4be <memcpy>
|
|
CmdRspStatusFlag = SHCI_TL_CMD_RESP_WAIT;
|
|
80130ca: 4b10 ldr r3, [pc, #64] @ (801310c <shci_send+0x7c>)
|
|
80130cc: 2201 movs r2, #1
|
|
80130ce: 701a strb r2, [r3, #0]
|
|
shciContext.io.Send(0,0);
|
|
80130d0: 4b0f ldr r3, [pc, #60] @ (8013110 <shci_send+0x80>)
|
|
80130d2: 691b ldr r3, [r3, #16]
|
|
80130d4: 2100 movs r1, #0
|
|
80130d6: 2000 movs r0, #0
|
|
80130d8: 4798 blx r3
|
|
|
|
shci_cmd_resp_wait(SHCI_TL_DEFAULT_TIMEOUT);
|
|
80130da: f248 00e8 movw r0, #33000 @ 0x80e8
|
|
80130de: f7ef fae1 bl 80026a4 <shci_cmd_resp_wait>
|
|
|
|
/**
|
|
* The command complete of a system command does not have the header
|
|
* It starts immediately with the evtserial field
|
|
*/
|
|
memcpy( &(p_rsp->evtserial), pCmdBuffer, ((TL_EvtSerial_t*)pCmdBuffer)->evt.plen + TL_EVT_HDR_SIZE );
|
|
80130e2: 687b ldr r3, [r7, #4]
|
|
80130e4: f103 0008 add.w r0, r3, #8
|
|
80130e8: 4b07 ldr r3, [pc, #28] @ (8013108 <shci_send+0x78>)
|
|
80130ea: 6819 ldr r1, [r3, #0]
|
|
80130ec: 4b06 ldr r3, [pc, #24] @ (8013108 <shci_send+0x78>)
|
|
80130ee: 681b ldr r3, [r3, #0]
|
|
80130f0: 789b ldrb r3, [r3, #2]
|
|
80130f2: 3303 adds r3, #3
|
|
80130f4: 461a mov r2, r3
|
|
80130f6: f007 f9e2 bl 801a4be <memcpy>
|
|
|
|
Cmd_SetStatus(SHCI_TL_CmdAvailable);
|
|
80130fa: 2001 movs r0, #1
|
|
80130fc: f000 f83c bl 8013178 <Cmd_SetStatus>
|
|
|
|
return;
|
|
8013100: bf00 nop
|
|
}
|
|
8013102: 3710 adds r7, #16
|
|
8013104: 46bd mov sp, r7
|
|
8013106: bd80 pop {r7, pc}
|
|
8013108: 200002e4 .word 0x200002e4
|
|
801310c: 200007ac .word 0x200007ac
|
|
8013110: 20000788 .word 0x20000788
|
|
|
|
08013114 <TlInit>:
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
static void TlInit( TL_CmdPacket_t * p_cmdbuffer )
|
|
{
|
|
8013114: b580 push {r7, lr}
|
|
8013116: b086 sub sp, #24
|
|
8013118: af00 add r7, sp, #0
|
|
801311a: 6078 str r0, [r7, #4]
|
|
TL_SYS_InitConf_t Conf;
|
|
|
|
pCmdBuffer = p_cmdbuffer;
|
|
801311c: 4a10 ldr r2, [pc, #64] @ (8013160 <TlInit+0x4c>)
|
|
801311e: 687b ldr r3, [r7, #4]
|
|
8013120: 6013 str r3, [r2, #0]
|
|
|
|
LST_init_head (&SHciAsynchEventQueue);
|
|
8013122: 4810 ldr r0, [pc, #64] @ (8013164 <TlInit+0x50>)
|
|
8013124: f000 faae bl 8013684 <LST_init_head>
|
|
|
|
Cmd_SetStatus(SHCI_TL_CmdAvailable);
|
|
8013128: 2001 movs r0, #1
|
|
801312a: f000 f825 bl 8013178 <Cmd_SetStatus>
|
|
|
|
SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable;
|
|
801312e: 4b0e ldr r3, [pc, #56] @ (8013168 <TlInit+0x54>)
|
|
8013130: 2201 movs r2, #1
|
|
8013132: 701a strb r2, [r3, #0]
|
|
|
|
/* Initialize low level driver */
|
|
if (shciContext.io.Init)
|
|
8013134: 4b0d ldr r3, [pc, #52] @ (801316c <TlInit+0x58>)
|
|
8013136: 681b ldr r3, [r3, #0]
|
|
8013138: 2b00 cmp r3, #0
|
|
801313a: d00c beq.n 8013156 <TlInit+0x42>
|
|
{
|
|
|
|
Conf.p_cmdbuffer = (uint8_t *)p_cmdbuffer;
|
|
801313c: 687b ldr r3, [r7, #4]
|
|
801313e: 617b str r3, [r7, #20]
|
|
Conf.IoBusCallBackCmdEvt = TlCmdEvtReceived;
|
|
8013140: 4b0b ldr r3, [pc, #44] @ (8013170 <TlInit+0x5c>)
|
|
8013142: 60fb str r3, [r7, #12]
|
|
Conf.IoBusCallBackUserEvt = TlUserEvtReceived;
|
|
8013144: 4b0b ldr r3, [pc, #44] @ (8013174 <TlInit+0x60>)
|
|
8013146: 613b str r3, [r7, #16]
|
|
shciContext.io.Init(&Conf);
|
|
8013148: 4b08 ldr r3, [pc, #32] @ (801316c <TlInit+0x58>)
|
|
801314a: 681b ldr r3, [r3, #0]
|
|
801314c: f107 020c add.w r2, r7, #12
|
|
8013150: 4610 mov r0, r2
|
|
8013152: 4798 blx r3
|
|
}
|
|
|
|
return;
|
|
8013154: bf00 nop
|
|
8013156: bf00 nop
|
|
}
|
|
8013158: 3718 adds r7, #24
|
|
801315a: 46bd mov sp, r7
|
|
801315c: bd80 pop {r7, pc}
|
|
801315e: bf00 nop
|
|
8013160: 200002e4 .word 0x200002e4
|
|
8013164: 200002d8 .word 0x200002d8
|
|
8013168: 200002e8 .word 0x200002e8
|
|
801316c: 20000788 .word 0x20000788
|
|
8013170: 080131c9 .word 0x080131c9
|
|
8013174: 080131e1 .word 0x080131e1
|
|
|
|
08013178 <Cmd_SetStatus>:
|
|
|
|
static void Cmd_SetStatus(SHCI_TL_CmdStatus_t shcicmdstatus)
|
|
{
|
|
8013178: b580 push {r7, lr}
|
|
801317a: b082 sub sp, #8
|
|
801317c: af00 add r7, sp, #0
|
|
801317e: 4603 mov r3, r0
|
|
8013180: 71fb strb r3, [r7, #7]
|
|
if(shcicmdstatus == SHCI_TL_CmdBusy)
|
|
8013182: 79fb ldrb r3, [r7, #7]
|
|
8013184: 2b00 cmp r3, #0
|
|
8013186: d10b bne.n 80131a0 <Cmd_SetStatus+0x28>
|
|
{
|
|
if(StatusNotCallBackFunction != 0)
|
|
8013188: 4b0d ldr r3, [pc, #52] @ (80131c0 <Cmd_SetStatus+0x48>)
|
|
801318a: 681b ldr r3, [r3, #0]
|
|
801318c: 2b00 cmp r3, #0
|
|
801318e: d003 beq.n 8013198 <Cmd_SetStatus+0x20>
|
|
{
|
|
StatusNotCallBackFunction( SHCI_TL_CmdBusy );
|
|
8013190: 4b0b ldr r3, [pc, #44] @ (80131c0 <Cmd_SetStatus+0x48>)
|
|
8013192: 681b ldr r3, [r3, #0]
|
|
8013194: 2000 movs r0, #0
|
|
8013196: 4798 blx r3
|
|
}
|
|
SHCICmdStatus = SHCI_TL_CmdBusy;
|
|
8013198: 4b0a ldr r3, [pc, #40] @ (80131c4 <Cmd_SetStatus+0x4c>)
|
|
801319a: 2200 movs r2, #0
|
|
801319c: 701a strb r2, [r3, #0]
|
|
{
|
|
StatusNotCallBackFunction( SHCI_TL_CmdAvailable );
|
|
}
|
|
}
|
|
|
|
return;
|
|
801319e: e00b b.n 80131b8 <Cmd_SetStatus+0x40>
|
|
SHCICmdStatus = SHCI_TL_CmdAvailable;
|
|
80131a0: 4b08 ldr r3, [pc, #32] @ (80131c4 <Cmd_SetStatus+0x4c>)
|
|
80131a2: 2201 movs r2, #1
|
|
80131a4: 701a strb r2, [r3, #0]
|
|
if(StatusNotCallBackFunction != 0)
|
|
80131a6: 4b06 ldr r3, [pc, #24] @ (80131c0 <Cmd_SetStatus+0x48>)
|
|
80131a8: 681b ldr r3, [r3, #0]
|
|
80131aa: 2b00 cmp r3, #0
|
|
80131ac: d004 beq.n 80131b8 <Cmd_SetStatus+0x40>
|
|
StatusNotCallBackFunction( SHCI_TL_CmdAvailable );
|
|
80131ae: 4b04 ldr r3, [pc, #16] @ (80131c0 <Cmd_SetStatus+0x48>)
|
|
80131b0: 681b ldr r3, [r3, #0]
|
|
80131b2: 2001 movs r0, #1
|
|
80131b4: 4798 blx r3
|
|
return;
|
|
80131b6: bf00 nop
|
|
80131b8: bf00 nop
|
|
}
|
|
80131ba: 3708 adds r7, #8
|
|
80131bc: 46bd mov sp, r7
|
|
80131be: bd80 pop {r7, pc}
|
|
80131c0: 200007a8 .word 0x200007a8
|
|
80131c4: 200002e0 .word 0x200002e0
|
|
|
|
080131c8 <TlCmdEvtReceived>:
|
|
|
|
static void TlCmdEvtReceived(TL_EvtPacket_t *shcievt)
|
|
{
|
|
80131c8: b580 push {r7, lr}
|
|
80131ca: b082 sub sp, #8
|
|
80131cc: af00 add r7, sp, #0
|
|
80131ce: 6078 str r0, [r7, #4]
|
|
(void)(shcievt);
|
|
shci_cmd_resp_release(0); /**< Notify the application the Cmd response has been received */
|
|
80131d0: 2000 movs r0, #0
|
|
80131d2: f7ef fa57 bl 8002684 <shci_cmd_resp_release>
|
|
|
|
return;
|
|
80131d6: bf00 nop
|
|
}
|
|
80131d8: 3708 adds r7, #8
|
|
80131da: 46bd mov sp, r7
|
|
80131dc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080131e0 <TlUserEvtReceived>:
|
|
|
|
static void TlUserEvtReceived(TL_EvtPacket_t *shcievt)
|
|
{
|
|
80131e0: b580 push {r7, lr}
|
|
80131e2: b082 sub sp, #8
|
|
80131e4: af00 add r7, sp, #0
|
|
80131e6: 6078 str r0, [r7, #4]
|
|
LST_insert_tail(&SHciAsynchEventQueue, (tListNode *)shcievt);
|
|
80131e8: 6879 ldr r1, [r7, #4]
|
|
80131ea: 4805 ldr r0, [pc, #20] @ (8013200 <TlUserEvtReceived+0x20>)
|
|
80131ec: f000 faa2 bl 8013734 <LST_insert_tail>
|
|
shci_notify_asynch_evt((void*) &SHciAsynchEventQueue); /**< Notify the application a full HCI event has been received */
|
|
80131f0: 4803 ldr r0, [pc, #12] @ (8013200 <TlUserEvtReceived+0x20>)
|
|
80131f2: f7ef fa37 bl 8002664 <shci_notify_asynch_evt>
|
|
|
|
return;
|
|
80131f6: bf00 nop
|
|
}
|
|
80131f8: 3708 adds r7, #8
|
|
80131fa: 46bd mov sp, r7
|
|
80131fc: bd80 pop {r7, pc}
|
|
80131fe: bf00 nop
|
|
8013200: 200002d8 .word 0x200002d8
|
|
|
|
08013204 <shci_register_io_bus>:
|
|
#include "shci_tl.h"
|
|
#include "tl.h"
|
|
|
|
|
|
void shci_register_io_bus(tSHciIO* fops)
|
|
{
|
|
8013204: b480 push {r7}
|
|
8013206: b083 sub sp, #12
|
|
8013208: af00 add r7, sp, #0
|
|
801320a: 6078 str r0, [r7, #4]
|
|
/* Register IO bus services */
|
|
fops->Init = TL_SYS_Init;
|
|
801320c: 687b ldr r3, [r7, #4]
|
|
801320e: 4a05 ldr r2, [pc, #20] @ (8013224 <shci_register_io_bus+0x20>)
|
|
8013210: 601a str r2, [r3, #0]
|
|
fops->Send = TL_SYS_SendCmd;
|
|
8013212: 687b ldr r3, [r7, #4]
|
|
8013214: 4a04 ldr r2, [pc, #16] @ (8013228 <shci_register_io_bus+0x24>)
|
|
8013216: 611a str r2, [r3, #16]
|
|
|
|
return;
|
|
8013218: bf00 nop
|
|
}
|
|
801321a: 370c adds r7, #12
|
|
801321c: 46bd mov sp, r7
|
|
801321e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8013222: 4770 bx lr
|
|
8013224: 08013329 .word 0x08013329
|
|
8013228: 0801337d .word 0x0801337d
|
|
|
|
0801322c <TL_Enable>:
|
|
|
|
/******************************************************************************
|
|
* GENERAL - refer to AN5289 for functions description.
|
|
******************************************************************************/
|
|
void TL_Enable( void )
|
|
{
|
|
801322c: b580 push {r7, lr}
|
|
801322e: af00 add r7, sp, #0
|
|
HW_IPCC_Enable();
|
|
8013230: f005 f9f8 bl 8018624 <HW_IPCC_Enable>
|
|
|
|
return;
|
|
8013234: bf00 nop
|
|
}
|
|
8013236: bd80 pop {r7, pc}
|
|
|
|
08013238 <TL_Init>:
|
|
|
|
|
|
void TL_Init( void )
|
|
{
|
|
8013238: b580 push {r7, lr}
|
|
801323a: af00 add r7, sp, #0
|
|
TL_RefTable.p_device_info_table = &TL_DeviceInfoTable;
|
|
801323c: 4b10 ldr r3, [pc, #64] @ (8013280 <TL_Init+0x48>)
|
|
801323e: 4a11 ldr r2, [pc, #68] @ (8013284 <TL_Init+0x4c>)
|
|
8013240: 601a str r2, [r3, #0]
|
|
TL_RefTable.p_ble_table = &TL_BleTable;
|
|
8013242: 4b0f ldr r3, [pc, #60] @ (8013280 <TL_Init+0x48>)
|
|
8013244: 4a10 ldr r2, [pc, #64] @ (8013288 <TL_Init+0x50>)
|
|
8013246: 605a str r2, [r3, #4]
|
|
TL_RefTable.p_thread_table = &TL_ThreadTable;
|
|
8013248: 4b0d ldr r3, [pc, #52] @ (8013280 <TL_Init+0x48>)
|
|
801324a: 4a10 ldr r2, [pc, #64] @ (801328c <TL_Init+0x54>)
|
|
801324c: 609a str r2, [r3, #8]
|
|
TL_RefTable.p_lld_tests_table = &TL_LldTestsTable;
|
|
801324e: 4b0c ldr r3, [pc, #48] @ (8013280 <TL_Init+0x48>)
|
|
8013250: 4a0f ldr r2, [pc, #60] @ (8013290 <TL_Init+0x58>)
|
|
8013252: 621a str r2, [r3, #32]
|
|
TL_RefTable.p_ble_lld_table = &TL_BleLldTable;
|
|
8013254: 4b0a ldr r3, [pc, #40] @ (8013280 <TL_Init+0x48>)
|
|
8013256: 4a0f ldr r2, [pc, #60] @ (8013294 <TL_Init+0x5c>)
|
|
8013258: 625a str r2, [r3, #36] @ 0x24
|
|
TL_RefTable.p_sys_table = &TL_SysTable;
|
|
801325a: 4b09 ldr r3, [pc, #36] @ (8013280 <TL_Init+0x48>)
|
|
801325c: 4a0e ldr r2, [pc, #56] @ (8013298 <TL_Init+0x60>)
|
|
801325e: 60da str r2, [r3, #12]
|
|
TL_RefTable.p_mem_manager_table = &TL_MemManagerTable;
|
|
8013260: 4b07 ldr r3, [pc, #28] @ (8013280 <TL_Init+0x48>)
|
|
8013262: 4a0e ldr r2, [pc, #56] @ (801329c <TL_Init+0x64>)
|
|
8013264: 611a str r2, [r3, #16]
|
|
TL_RefTable.p_traces_table = &TL_TracesTable;
|
|
8013266: 4b06 ldr r3, [pc, #24] @ (8013280 <TL_Init+0x48>)
|
|
8013268: 4a0d ldr r2, [pc, #52] @ (80132a0 <TL_Init+0x68>)
|
|
801326a: 615a str r2, [r3, #20]
|
|
TL_RefTable.p_mac_802_15_4_table = &TL_Mac_802_15_4_Table;
|
|
801326c: 4b04 ldr r3, [pc, #16] @ (8013280 <TL_Init+0x48>)
|
|
801326e: 4a0d ldr r2, [pc, #52] @ (80132a4 <TL_Init+0x6c>)
|
|
8013270: 619a str r2, [r3, #24]
|
|
TL_RefTable.p_zigbee_table = &TL_Zigbee_Table;
|
|
8013272: 4b03 ldr r3, [pc, #12] @ (8013280 <TL_Init+0x48>)
|
|
8013274: 4a0c ldr r2, [pc, #48] @ (80132a8 <TL_Init+0x70>)
|
|
8013276: 61da str r2, [r3, #28]
|
|
HW_IPCC_Init();
|
|
8013278: f005 f9e8 bl 801864c <HW_IPCC_Init>
|
|
|
|
return;
|
|
801327c: bf00 nop
|
|
}
|
|
801327e: bd80 pop {r7, pc}
|
|
8013280: 20030000 .word 0x20030000
|
|
8013284: 20030028 .word 0x20030028
|
|
8013288: 20030048 .word 0x20030048
|
|
801328c: 20030058 .word 0x20030058
|
|
8013290: 20030068 .word 0x20030068
|
|
8013294: 20030070 .word 0x20030070
|
|
8013298: 20030078 .word 0x20030078
|
|
801329c: 20030080 .word 0x20030080
|
|
80132a0: 2003009c .word 0x2003009c
|
|
80132a4: 200300a0 .word 0x200300a0
|
|
80132a8: 200300ac .word 0x200300ac
|
|
|
|
080132ac <HW_IPCC_BLE_RxEvtNot>:
|
|
|
|
return 0;
|
|
}
|
|
|
|
void HW_IPCC_BLE_RxEvtNot(void)
|
|
{
|
|
80132ac: b580 push {r7, lr}
|
|
80132ae: b082 sub sp, #8
|
|
80132b0: af00 add r7, sp, #0
|
|
TL_EvtPacket_t *phcievt;
|
|
|
|
while(LST_is_empty(&EvtQueue) == FALSE)
|
|
80132b2: e01c b.n 80132ee <HW_IPCC_BLE_RxEvtNot+0x42>
|
|
{
|
|
LST_remove_head (&EvtQueue, (tListNode **)&phcievt);
|
|
80132b4: 1d3b adds r3, r7, #4
|
|
80132b6: 4619 mov r1, r3
|
|
80132b8: 4812 ldr r0, [pc, #72] @ (8013304 <HW_IPCC_BLE_RxEvtNot+0x58>)
|
|
80132ba: f000 fa82 bl 80137c2 <LST_remove_head>
|
|
|
|
if ( ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CS_OPCODE) || ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CC_OPCODE ) )
|
|
80132be: 687b ldr r3, [r7, #4]
|
|
80132c0: 7a5b ldrb r3, [r3, #9]
|
|
80132c2: 2b0f cmp r3, #15
|
|
80132c4: d003 beq.n 80132ce <HW_IPCC_BLE_RxEvtNot+0x22>
|
|
80132c6: 687b ldr r3, [r7, #4]
|
|
80132c8: 7a5b ldrb r3, [r3, #9]
|
|
80132ca: 2b0e cmp r3, #14
|
|
80132cc: d105 bne.n 80132da <HW_IPCC_BLE_RxEvtNot+0x2e>
|
|
{
|
|
OutputDbgTrace(TL_MB_BLE_CMD_RSP, (uint8_t*)phcievt);
|
|
80132ce: 687b ldr r3, [r7, #4]
|
|
80132d0: 4619 mov r1, r3
|
|
80132d2: 2002 movs r0, #2
|
|
80132d4: f000 f950 bl 8013578 <OutputDbgTrace>
|
|
80132d8: e004 b.n 80132e4 <HW_IPCC_BLE_RxEvtNot+0x38>
|
|
}
|
|
else
|
|
{
|
|
OutputDbgTrace(TL_MB_BLE_ASYNCH_EVT, (uint8_t*)phcievt);
|
|
80132da: 687b ldr r3, [r7, #4]
|
|
80132dc: 4619 mov r1, r3
|
|
80132de: 2005 movs r0, #5
|
|
80132e0: f000 f94a bl 8013578 <OutputDbgTrace>
|
|
}
|
|
|
|
BLE_IoBusEvtCallBackFunction(phcievt);
|
|
80132e4: 4b08 ldr r3, [pc, #32] @ (8013308 <HW_IPCC_BLE_RxEvtNot+0x5c>)
|
|
80132e6: 681b ldr r3, [r3, #0]
|
|
80132e8: 687a ldr r2, [r7, #4]
|
|
80132ea: 4610 mov r0, r2
|
|
80132ec: 4798 blx r3
|
|
while(LST_is_empty(&EvtQueue) == FALSE)
|
|
80132ee: 4805 ldr r0, [pc, #20] @ (8013304 <HW_IPCC_BLE_RxEvtNot+0x58>)
|
|
80132f0: f000 f9d8 bl 80136a4 <LST_is_empty>
|
|
80132f4: 4603 mov r3, r0
|
|
80132f6: 2b00 cmp r3, #0
|
|
80132f8: d0dc beq.n 80132b4 <HW_IPCC_BLE_RxEvtNot+0x8>
|
|
}
|
|
|
|
return;
|
|
80132fa: bf00 nop
|
|
}
|
|
80132fc: 3708 adds r7, #8
|
|
80132fe: 46bd mov sp, r7
|
|
8013300: bd80 pop {r7, pc}
|
|
8013302: bf00 nop
|
|
8013304: 200300c8 .word 0x200300c8
|
|
8013308: 200007b8 .word 0x200007b8
|
|
|
|
0801330c <HW_IPCC_BLE_AclDataAckNot>:
|
|
|
|
return 0;
|
|
}
|
|
|
|
void HW_IPCC_BLE_AclDataAckNot(void)
|
|
{
|
|
801330c: b580 push {r7, lr}
|
|
801330e: af00 add r7, sp, #0
|
|
OutputDbgTrace(TL_MB_ACL_DATA_RSP, (uint8_t*)NULL);
|
|
8013310: 2100 movs r1, #0
|
|
8013312: 2004 movs r0, #4
|
|
8013314: f000 f930 bl 8013578 <OutputDbgTrace>
|
|
|
|
BLE_IoBusAclDataTxAck( );
|
|
8013318: 4b02 ldr r3, [pc, #8] @ (8013324 <HW_IPCC_BLE_AclDataAckNot+0x18>)
|
|
801331a: 681b ldr r3, [r3, #0]
|
|
801331c: 4798 blx r3
|
|
|
|
return;
|
|
801331e: bf00 nop
|
|
}
|
|
8013320: bd80 pop {r7, pc}
|
|
8013322: bf00 nop
|
|
8013324: 200007bc .word 0x200007bc
|
|
|
|
08013328 <TL_SYS_Init>:
|
|
|
|
/******************************************************************************
|
|
* SYSTEM
|
|
******************************************************************************/
|
|
int32_t TL_SYS_Init( void* pConf )
|
|
{
|
|
8013328: b580 push {r7, lr}
|
|
801332a: b084 sub sp, #16
|
|
801332c: af00 add r7, sp, #0
|
|
801332e: 6078 str r0, [r7, #4]
|
|
MB_SysTable_t * p_systable;
|
|
|
|
TL_SYS_InitConf_t *pInitHciConf = (TL_SYS_InitConf_t *) pConf;
|
|
8013330: 687b ldr r3, [r7, #4]
|
|
8013332: 60fb str r3, [r7, #12]
|
|
|
|
LST_init_head (&SystemEvtQueue);
|
|
8013334: 480d ldr r0, [pc, #52] @ (801336c <TL_SYS_Init+0x44>)
|
|
8013336: f000 f9a5 bl 8013684 <LST_init_head>
|
|
p_systable = TL_RefTable.p_sys_table;
|
|
801333a: 4b0d ldr r3, [pc, #52] @ (8013370 <TL_SYS_Init+0x48>)
|
|
801333c: 68db ldr r3, [r3, #12]
|
|
801333e: 60bb str r3, [r7, #8]
|
|
p_systable->pcmd_buffer = pInitHciConf->p_cmdbuffer;
|
|
8013340: 68fb ldr r3, [r7, #12]
|
|
8013342: 689a ldr r2, [r3, #8]
|
|
8013344: 68bb ldr r3, [r7, #8]
|
|
8013346: 601a str r2, [r3, #0]
|
|
p_systable->sys_queue = (uint8_t*)&SystemEvtQueue;
|
|
8013348: 68bb ldr r3, [r7, #8]
|
|
801334a: 4a08 ldr r2, [pc, #32] @ (801336c <TL_SYS_Init+0x44>)
|
|
801334c: 605a str r2, [r3, #4]
|
|
|
|
HW_IPCC_SYS_Init();
|
|
801334e: f005 f9bb bl 80186c8 <HW_IPCC_SYS_Init>
|
|
|
|
SYS_CMD_IoBusCallBackFunction = pInitHciConf->IoBusCallBackCmdEvt;
|
|
8013352: 68fb ldr r3, [r7, #12]
|
|
8013354: 681b ldr r3, [r3, #0]
|
|
8013356: 4a07 ldr r2, [pc, #28] @ (8013374 <TL_SYS_Init+0x4c>)
|
|
8013358: 6013 str r3, [r2, #0]
|
|
SYS_EVT_IoBusCallBackFunction = pInitHciConf->IoBusCallBackUserEvt;
|
|
801335a: 68fb ldr r3, [r7, #12]
|
|
801335c: 685b ldr r3, [r3, #4]
|
|
801335e: 4a06 ldr r2, [pc, #24] @ (8013378 <TL_SYS_Init+0x50>)
|
|
8013360: 6013 str r3, [r2, #0]
|
|
|
|
return 0;
|
|
8013362: 2300 movs r3, #0
|
|
}
|
|
8013364: 4618 mov r0, r3
|
|
8013366: 3710 adds r7, #16
|
|
8013368: 46bd mov sp, r7
|
|
801336a: bd80 pop {r7, pc}
|
|
801336c: 200300d0 .word 0x200300d0
|
|
8013370: 20030000 .word 0x20030000
|
|
8013374: 200007c0 .word 0x200007c0
|
|
8013378: 200007c4 .word 0x200007c4
|
|
|
|
0801337c <TL_SYS_SendCmd>:
|
|
|
|
int32_t TL_SYS_SendCmd( uint8_t* buffer, uint16_t size )
|
|
{
|
|
801337c: b580 push {r7, lr}
|
|
801337e: b082 sub sp, #8
|
|
8013380: af00 add r7, sp, #0
|
|
8013382: 6078 str r0, [r7, #4]
|
|
8013384: 460b mov r3, r1
|
|
8013386: 807b strh r3, [r7, #2]
|
|
(void)(buffer);
|
|
(void)(size);
|
|
|
|
((TL_CmdPacket_t *)(TL_RefTable.p_sys_table->pcmd_buffer))->cmdserial.type = TL_SYSCMD_PKT_TYPE;
|
|
8013388: 4b09 ldr r3, [pc, #36] @ (80133b0 <TL_SYS_SendCmd+0x34>)
|
|
801338a: 68db ldr r3, [r3, #12]
|
|
801338c: 681b ldr r3, [r3, #0]
|
|
801338e: 2210 movs r2, #16
|
|
8013390: 721a strb r2, [r3, #8]
|
|
|
|
OutputDbgTrace(TL_MB_SYS_CMD, TL_RefTable.p_sys_table->pcmd_buffer);
|
|
8013392: 4b07 ldr r3, [pc, #28] @ (80133b0 <TL_SYS_SendCmd+0x34>)
|
|
8013394: 68db ldr r3, [r3, #12]
|
|
8013396: 681b ldr r3, [r3, #0]
|
|
8013398: 4619 mov r1, r3
|
|
801339a: 2006 movs r0, #6
|
|
801339c: f000 f8ec bl 8013578 <OutputDbgTrace>
|
|
|
|
HW_IPCC_SYS_SendCmd();
|
|
80133a0: f005 f9ac bl 80186fc <HW_IPCC_SYS_SendCmd>
|
|
|
|
return 0;
|
|
80133a4: 2300 movs r3, #0
|
|
}
|
|
80133a6: 4618 mov r0, r3
|
|
80133a8: 3708 adds r7, #8
|
|
80133aa: 46bd mov sp, r7
|
|
80133ac: bd80 pop {r7, pc}
|
|
80133ae: bf00 nop
|
|
80133b0: 20030000 .word 0x20030000
|
|
|
|
080133b4 <HW_IPCC_SYS_CmdEvtNot>:
|
|
|
|
void HW_IPCC_SYS_CmdEvtNot(void)
|
|
{
|
|
80133b4: b580 push {r7, lr}
|
|
80133b6: af00 add r7, sp, #0
|
|
OutputDbgTrace(TL_MB_SYS_CMD_RSP, (uint8_t*)(TL_RefTable.p_sys_table->pcmd_buffer) );
|
|
80133b8: 4b07 ldr r3, [pc, #28] @ (80133d8 <HW_IPCC_SYS_CmdEvtNot+0x24>)
|
|
80133ba: 68db ldr r3, [r3, #12]
|
|
80133bc: 681b ldr r3, [r3, #0]
|
|
80133be: 4619 mov r1, r3
|
|
80133c0: 2007 movs r0, #7
|
|
80133c2: f000 f8d9 bl 8013578 <OutputDbgTrace>
|
|
|
|
SYS_CMD_IoBusCallBackFunction( (TL_EvtPacket_t*)(TL_RefTable.p_sys_table->pcmd_buffer) );
|
|
80133c6: 4b05 ldr r3, [pc, #20] @ (80133dc <HW_IPCC_SYS_CmdEvtNot+0x28>)
|
|
80133c8: 681b ldr r3, [r3, #0]
|
|
80133ca: 4a03 ldr r2, [pc, #12] @ (80133d8 <HW_IPCC_SYS_CmdEvtNot+0x24>)
|
|
80133cc: 68d2 ldr r2, [r2, #12]
|
|
80133ce: 6812 ldr r2, [r2, #0]
|
|
80133d0: 4610 mov r0, r2
|
|
80133d2: 4798 blx r3
|
|
|
|
return;
|
|
80133d4: bf00 nop
|
|
}
|
|
80133d6: bd80 pop {r7, pc}
|
|
80133d8: 20030000 .word 0x20030000
|
|
80133dc: 200007c0 .word 0x200007c0
|
|
|
|
080133e0 <HW_IPCC_SYS_EvtNot>:
|
|
|
|
void HW_IPCC_SYS_EvtNot( void )
|
|
{
|
|
80133e0: b580 push {r7, lr}
|
|
80133e2: b082 sub sp, #8
|
|
80133e4: af00 add r7, sp, #0
|
|
TL_EvtPacket_t *p_evt;
|
|
|
|
while(LST_is_empty(&SystemEvtQueue) == FALSE)
|
|
80133e6: e00e b.n 8013406 <HW_IPCC_SYS_EvtNot+0x26>
|
|
{
|
|
LST_remove_head (&SystemEvtQueue, (tListNode **)&p_evt);
|
|
80133e8: 1d3b adds r3, r7, #4
|
|
80133ea: 4619 mov r1, r3
|
|
80133ec: 480b ldr r0, [pc, #44] @ (801341c <HW_IPCC_SYS_EvtNot+0x3c>)
|
|
80133ee: f000 f9e8 bl 80137c2 <LST_remove_head>
|
|
|
|
OutputDbgTrace(TL_MB_SYS_ASYNCH_EVT, (uint8_t*)p_evt );
|
|
80133f2: 687b ldr r3, [r7, #4]
|
|
80133f4: 4619 mov r1, r3
|
|
80133f6: 2008 movs r0, #8
|
|
80133f8: f000 f8be bl 8013578 <OutputDbgTrace>
|
|
|
|
SYS_EVT_IoBusCallBackFunction( p_evt );
|
|
80133fc: 4b08 ldr r3, [pc, #32] @ (8013420 <HW_IPCC_SYS_EvtNot+0x40>)
|
|
80133fe: 681b ldr r3, [r3, #0]
|
|
8013400: 687a ldr r2, [r7, #4]
|
|
8013402: 4610 mov r0, r2
|
|
8013404: 4798 blx r3
|
|
while(LST_is_empty(&SystemEvtQueue) == FALSE)
|
|
8013406: 4805 ldr r0, [pc, #20] @ (801341c <HW_IPCC_SYS_EvtNot+0x3c>)
|
|
8013408: f000 f94c bl 80136a4 <LST_is_empty>
|
|
801340c: 4603 mov r3, r0
|
|
801340e: 2b00 cmp r3, #0
|
|
8013410: d0ea beq.n 80133e8 <HW_IPCC_SYS_EvtNot+0x8>
|
|
}
|
|
|
|
return;
|
|
8013412: bf00 nop
|
|
}
|
|
8013414: 3708 adds r7, #8
|
|
8013416: 46bd mov sp, r7
|
|
8013418: bd80 pop {r7, pc}
|
|
801341a: bf00 nop
|
|
801341c: 200300d0 .word 0x200300d0
|
|
8013420: 200007c4 .word 0x200007c4
|
|
|
|
08013424 <TL_MM_Init>:
|
|
|
|
/******************************************************************************
|
|
* MEMORY MANAGER
|
|
******************************************************************************/
|
|
void TL_MM_Init( TL_MM_Config_t *p_Config )
|
|
{
|
|
8013424: b580 push {r7, lr}
|
|
8013426: b082 sub sp, #8
|
|
8013428: af00 add r7, sp, #0
|
|
801342a: 6078 str r0, [r7, #4]
|
|
static MB_MemManagerTable_t * p_mem_manager_table;
|
|
|
|
LST_init_head (&FreeBufQueue);
|
|
801342c: 4817 ldr r0, [pc, #92] @ (801348c <TL_MM_Init+0x68>)
|
|
801342e: f000 f929 bl 8013684 <LST_init_head>
|
|
LST_init_head (&LocalFreeBufQueue);
|
|
8013432: 4817 ldr r0, [pc, #92] @ (8013490 <TL_MM_Init+0x6c>)
|
|
8013434: f000 f926 bl 8013684 <LST_init_head>
|
|
|
|
p_mem_manager_table = TL_RefTable.p_mem_manager_table;
|
|
8013438: 4b16 ldr r3, [pc, #88] @ (8013494 <TL_MM_Init+0x70>)
|
|
801343a: 691b ldr r3, [r3, #16]
|
|
801343c: 4a16 ldr r2, [pc, #88] @ (8013498 <TL_MM_Init+0x74>)
|
|
801343e: 6013 str r3, [r2, #0]
|
|
|
|
p_mem_manager_table->blepool = p_Config->p_AsynchEvtPool;
|
|
8013440: 4b15 ldr r3, [pc, #84] @ (8013498 <TL_MM_Init+0x74>)
|
|
8013442: 681b ldr r3, [r3, #0]
|
|
8013444: 687a ldr r2, [r7, #4]
|
|
8013446: 6892 ldr r2, [r2, #8]
|
|
8013448: 609a str r2, [r3, #8]
|
|
p_mem_manager_table->blepoolsize = p_Config->AsynchEvtPoolSize;
|
|
801344a: 4b13 ldr r3, [pc, #76] @ (8013498 <TL_MM_Init+0x74>)
|
|
801344c: 681b ldr r3, [r3, #0]
|
|
801344e: 687a ldr r2, [r7, #4]
|
|
8013450: 68d2 ldr r2, [r2, #12]
|
|
8013452: 60da str r2, [r3, #12]
|
|
p_mem_manager_table->pevt_free_buffer_queue = (uint8_t*)&FreeBufQueue;
|
|
8013454: 4b10 ldr r3, [pc, #64] @ (8013498 <TL_MM_Init+0x74>)
|
|
8013456: 681b ldr r3, [r3, #0]
|
|
8013458: 4a0c ldr r2, [pc, #48] @ (801348c <TL_MM_Init+0x68>)
|
|
801345a: 611a str r2, [r3, #16]
|
|
p_mem_manager_table->spare_ble_buffer = p_Config->p_BleSpareEvtBuffer;
|
|
801345c: 4b0e ldr r3, [pc, #56] @ (8013498 <TL_MM_Init+0x74>)
|
|
801345e: 681b ldr r3, [r3, #0]
|
|
8013460: 687a ldr r2, [r7, #4]
|
|
8013462: 6812 ldr r2, [r2, #0]
|
|
8013464: 601a str r2, [r3, #0]
|
|
p_mem_manager_table->spare_sys_buffer = p_Config->p_SystemSpareEvtBuffer;
|
|
8013466: 4b0c ldr r3, [pc, #48] @ (8013498 <TL_MM_Init+0x74>)
|
|
8013468: 681b ldr r3, [r3, #0]
|
|
801346a: 687a ldr r2, [r7, #4]
|
|
801346c: 6852 ldr r2, [r2, #4]
|
|
801346e: 605a str r2, [r3, #4]
|
|
p_mem_manager_table->traces_evt_pool = p_Config->p_TracesEvtPool;
|
|
8013470: 4b09 ldr r3, [pc, #36] @ (8013498 <TL_MM_Init+0x74>)
|
|
8013472: 681b ldr r3, [r3, #0]
|
|
8013474: 687a ldr r2, [r7, #4]
|
|
8013476: 6912 ldr r2, [r2, #16]
|
|
8013478: 615a str r2, [r3, #20]
|
|
p_mem_manager_table->tracespoolsize = p_Config->TracesEvtPoolSize;
|
|
801347a: 4b07 ldr r3, [pc, #28] @ (8013498 <TL_MM_Init+0x74>)
|
|
801347c: 681b ldr r3, [r3, #0]
|
|
801347e: 687a ldr r2, [r7, #4]
|
|
8013480: 6952 ldr r2, [r2, #20]
|
|
8013482: 619a str r2, [r3, #24]
|
|
|
|
return;
|
|
8013484: bf00 nop
|
|
}
|
|
8013486: 3708 adds r7, #8
|
|
8013488: 46bd mov sp, r7
|
|
801348a: bd80 pop {r7, pc}
|
|
801348c: 200300b8 .word 0x200300b8
|
|
8013490: 200007b0 .word 0x200007b0
|
|
8013494: 20030000 .word 0x20030000
|
|
8013498: 200007c8 .word 0x200007c8
|
|
|
|
0801349c <TL_MM_EvtDone>:
|
|
|
|
void TL_MM_EvtDone(TL_EvtPacket_t * phcievt)
|
|
{
|
|
801349c: b580 push {r7, lr}
|
|
801349e: b082 sub sp, #8
|
|
80134a0: af00 add r7, sp, #0
|
|
80134a2: 6078 str r0, [r7, #4]
|
|
LST_insert_tail(&LocalFreeBufQueue, (tListNode *)phcievt);
|
|
80134a4: 6879 ldr r1, [r7, #4]
|
|
80134a6: 4807 ldr r0, [pc, #28] @ (80134c4 <TL_MM_EvtDone+0x28>)
|
|
80134a8: f000 f944 bl 8013734 <LST_insert_tail>
|
|
|
|
OutputDbgTrace(TL_MB_MM_RELEASE_BUFFER, (uint8_t*)phcievt);
|
|
80134ac: 6879 ldr r1, [r7, #4]
|
|
80134ae: 2000 movs r0, #0
|
|
80134b0: f000 f862 bl 8013578 <OutputDbgTrace>
|
|
|
|
HW_IPCC_MM_SendFreeBuf( SendFreeBuf );
|
|
80134b4: 4804 ldr r0, [pc, #16] @ (80134c8 <TL_MM_EvtDone+0x2c>)
|
|
80134b6: f005 f967 bl 8018788 <HW_IPCC_MM_SendFreeBuf>
|
|
|
|
return;
|
|
80134ba: bf00 nop
|
|
}
|
|
80134bc: 3708 adds r7, #8
|
|
80134be: 46bd mov sp, r7
|
|
80134c0: bd80 pop {r7, pc}
|
|
80134c2: bf00 nop
|
|
80134c4: 200007b0 .word 0x200007b0
|
|
80134c8: 080134cd .word 0x080134cd
|
|
|
|
080134cc <SendFreeBuf>:
|
|
|
|
static void SendFreeBuf( void )
|
|
{
|
|
80134cc: b580 push {r7, lr}
|
|
80134ce: b082 sub sp, #8
|
|
80134d0: af00 add r7, sp, #0
|
|
tListNode *p_node;
|
|
|
|
while ( FALSE == LST_is_empty (&LocalFreeBufQueue) )
|
|
80134d2: e00c b.n 80134ee <SendFreeBuf+0x22>
|
|
{
|
|
LST_remove_head( &LocalFreeBufQueue, (tListNode **)&p_node );
|
|
80134d4: 1d3b adds r3, r7, #4
|
|
80134d6: 4619 mov r1, r3
|
|
80134d8: 480a ldr r0, [pc, #40] @ (8013504 <SendFreeBuf+0x38>)
|
|
80134da: f000 f972 bl 80137c2 <LST_remove_head>
|
|
LST_insert_tail( (tListNode*)(TL_RefTable.p_mem_manager_table->pevt_free_buffer_queue), p_node );
|
|
80134de: 4b0a ldr r3, [pc, #40] @ (8013508 <SendFreeBuf+0x3c>)
|
|
80134e0: 691b ldr r3, [r3, #16]
|
|
80134e2: 691b ldr r3, [r3, #16]
|
|
80134e4: 687a ldr r2, [r7, #4]
|
|
80134e6: 4611 mov r1, r2
|
|
80134e8: 4618 mov r0, r3
|
|
80134ea: f000 f923 bl 8013734 <LST_insert_tail>
|
|
while ( FALSE == LST_is_empty (&LocalFreeBufQueue) )
|
|
80134ee: 4805 ldr r0, [pc, #20] @ (8013504 <SendFreeBuf+0x38>)
|
|
80134f0: f000 f8d8 bl 80136a4 <LST_is_empty>
|
|
80134f4: 4603 mov r3, r0
|
|
80134f6: 2b00 cmp r3, #0
|
|
80134f8: d0ec beq.n 80134d4 <SendFreeBuf+0x8>
|
|
}
|
|
|
|
return;
|
|
80134fa: bf00 nop
|
|
}
|
|
80134fc: 3708 adds r7, #8
|
|
80134fe: 46bd mov sp, r7
|
|
8013500: bd80 pop {r7, pc}
|
|
8013502: bf00 nop
|
|
8013504: 200007b0 .word 0x200007b0
|
|
8013508: 20030000 .word 0x20030000
|
|
|
|
0801350c <TL_TRACES_Init>:
|
|
|
|
/******************************************************************************
|
|
* TRACES
|
|
******************************************************************************/
|
|
void TL_TRACES_Init( void )
|
|
{
|
|
801350c: b580 push {r7, lr}
|
|
801350e: af00 add r7, sp, #0
|
|
LST_init_head (&TracesEvtQueue);
|
|
8013510: 4805 ldr r0, [pc, #20] @ (8013528 <TL_TRACES_Init+0x1c>)
|
|
8013512: f000 f8b7 bl 8013684 <LST_init_head>
|
|
|
|
TL_RefTable.p_traces_table->traces_queue = (uint8_t*)&TracesEvtQueue;
|
|
8013516: 4b05 ldr r3, [pc, #20] @ (801352c <TL_TRACES_Init+0x20>)
|
|
8013518: 695b ldr r3, [r3, #20]
|
|
801351a: 4a03 ldr r2, [pc, #12] @ (8013528 <TL_TRACES_Init+0x1c>)
|
|
801351c: 601a str r2, [r3, #0]
|
|
|
|
HW_IPCC_TRACES_Init();
|
|
801351e: f005 f985 bl 801882c <HW_IPCC_TRACES_Init>
|
|
|
|
return;
|
|
8013522: bf00 nop
|
|
}
|
|
8013524: bd80 pop {r7, pc}
|
|
8013526: bf00 nop
|
|
8013528: 200300c0 .word 0x200300c0
|
|
801352c: 20030000 .word 0x20030000
|
|
|
|
08013530 <HW_IPCC_TRACES_EvtNot>:
|
|
|
|
void HW_IPCC_TRACES_EvtNot(void)
|
|
{
|
|
8013530: b580 push {r7, lr}
|
|
8013532: b082 sub sp, #8
|
|
8013534: af00 add r7, sp, #0
|
|
TL_EvtPacket_t *phcievt;
|
|
|
|
while(LST_is_empty(&TracesEvtQueue) == FALSE)
|
|
8013536: e008 b.n 801354a <HW_IPCC_TRACES_EvtNot+0x1a>
|
|
{
|
|
LST_remove_head (&TracesEvtQueue, (tListNode **)&phcievt);
|
|
8013538: 1d3b adds r3, r7, #4
|
|
801353a: 4619 mov r1, r3
|
|
801353c: 4808 ldr r0, [pc, #32] @ (8013560 <HW_IPCC_TRACES_EvtNot+0x30>)
|
|
801353e: f000 f940 bl 80137c2 <LST_remove_head>
|
|
TL_TRACES_EvtReceived( phcievt );
|
|
8013542: 687b ldr r3, [r7, #4]
|
|
8013544: 4618 mov r0, r3
|
|
8013546: f000 f80d bl 8013564 <TL_TRACES_EvtReceived>
|
|
while(LST_is_empty(&TracesEvtQueue) == FALSE)
|
|
801354a: 4805 ldr r0, [pc, #20] @ (8013560 <HW_IPCC_TRACES_EvtNot+0x30>)
|
|
801354c: f000 f8aa bl 80136a4 <LST_is_empty>
|
|
8013550: 4603 mov r3, r0
|
|
8013552: 2b00 cmp r3, #0
|
|
8013554: d0f0 beq.n 8013538 <HW_IPCC_TRACES_EvtNot+0x8>
|
|
}
|
|
|
|
return;
|
|
8013556: bf00 nop
|
|
}
|
|
8013558: 3708 adds r7, #8
|
|
801355a: 46bd mov sp, r7
|
|
801355c: bd80 pop {r7, pc}
|
|
801355e: bf00 nop
|
|
8013560: 200300c0 .word 0x200300c0
|
|
|
|
08013564 <TL_TRACES_EvtReceived>:
|
|
|
|
__WEAK void TL_TRACES_EvtReceived( TL_EvtPacket_t * hcievt )
|
|
{
|
|
8013564: b480 push {r7}
|
|
8013566: b083 sub sp, #12
|
|
8013568: af00 add r7, sp, #0
|
|
801356a: 6078 str r0, [r7, #4]
|
|
(void)(hcievt);
|
|
}
|
|
801356c: bf00 nop
|
|
801356e: 370c adds r7, #12
|
|
8013570: 46bd mov sp, r7
|
|
8013572: f85d 7b04 ldr.w r7, [sp], #4
|
|
8013576: 4770 bx lr
|
|
|
|
08013578 <OutputDbgTrace>:
|
|
|
|
/******************************************************************************
|
|
* DEBUG INFORMATION
|
|
******************************************************************************/
|
|
static void OutputDbgTrace(TL_MB_PacketType_t packet_type, uint8_t* buffer)
|
|
{
|
|
8013578: b480 push {r7}
|
|
801357a: b087 sub sp, #28
|
|
801357c: af00 add r7, sp, #0
|
|
801357e: 4603 mov r3, r0
|
|
8013580: 6039 str r1, [r7, #0]
|
|
8013582: 71fb strb r3, [r7, #7]
|
|
TL_EvtPacket_t *p_evt_packet;
|
|
TL_CmdPacket_t *p_cmd_packet;
|
|
TL_AclDataPacket_t *p_acldata_packet;
|
|
TL_EvtSerial_t *p_cmd_rsp_packet;
|
|
|
|
switch(packet_type)
|
|
8013584: 79fb ldrb r3, [r7, #7]
|
|
8013586: 2b08 cmp r3, #8
|
|
8013588: d84c bhi.n 8013624 <OutputDbgTrace+0xac>
|
|
801358a: a201 add r2, pc, #4 @ (adr r2, 8013590 <OutputDbgTrace+0x18>)
|
|
801358c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8013590: 080135b5 .word 0x080135b5
|
|
8013594: 080135d9 .word 0x080135d9
|
|
8013598: 080135e5 .word 0x080135e5
|
|
801359c: 080135df .word 0x080135df
|
|
80135a0: 08013625 .word 0x08013625
|
|
80135a4: 080135f9 .word 0x080135f9
|
|
80135a8: 08013605 .word 0x08013605
|
|
80135ac: 0801360b .word 0x0801360b
|
|
80135b0: 08013619 .word 0x08013619
|
|
{
|
|
case TL_MB_MM_RELEASE_BUFFER:
|
|
p_evt_packet = (TL_EvtPacket_t*)buffer;
|
|
80135b4: 683b ldr r3, [r7, #0]
|
|
80135b6: 617b str r3, [r7, #20]
|
|
switch(p_evt_packet->evtserial.evt.evtcode)
|
|
80135b8: 697b ldr r3, [r7, #20]
|
|
80135ba: 7a5b ldrb r3, [r3, #9]
|
|
80135bc: 2bff cmp r3, #255 @ 0xff
|
|
80135be: d005 beq.n 80135cc <OutputDbgTrace+0x54>
|
|
80135c0: 2bff cmp r3, #255 @ 0xff
|
|
80135c2: dc05 bgt.n 80135d0 <OutputDbgTrace+0x58>
|
|
80135c4: 2b0e cmp r3, #14
|
|
80135c6: d005 beq.n 80135d4 <OutputDbgTrace+0x5c>
|
|
80135c8: 2b0f cmp r3, #15
|
|
break;
|
|
|
|
default:
|
|
TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
|
|
TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet);
|
|
break;
|
|
80135ca: e001 b.n 80135d0 <OutputDbgTrace+0x58>
|
|
break;
|
|
80135cc: bf00 nop
|
|
80135ce: e02a b.n 8013626 <OutputDbgTrace+0xae>
|
|
break;
|
|
80135d0: bf00 nop
|
|
80135d2: e028 b.n 8013626 <OutputDbgTrace+0xae>
|
|
break;
|
|
80135d4: bf00 nop
|
|
}
|
|
|
|
TL_MM_DBG_MSG("\r\n");
|
|
break;
|
|
80135d6: e026 b.n 8013626 <OutputDbgTrace+0xae>
|
|
|
|
case TL_MB_BLE_CMD:
|
|
p_cmd_packet = (TL_CmdPacket_t*)buffer;
|
|
80135d8: 683b ldr r3, [r7, #0]
|
|
80135da: 60fb str r3, [r7, #12]
|
|
TL_HCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, "");
|
|
}
|
|
TL_HCI_CMD_DBG_MSG("\r\n");
|
|
|
|
TL_HCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE);
|
|
break;
|
|
80135dc: e023 b.n 8013626 <OutputDbgTrace+0xae>
|
|
|
|
case TL_MB_ACL_DATA:
|
|
(void)p_acldata_packet;
|
|
p_acldata_packet = (TL_AclDataPacket_t*)buffer;
|
|
80135de: 683b ldr r3, [r7, #0]
|
|
80135e0: 60bb str r3, [r7, #8]
|
|
TL_HCI_CMD_DBG_MSG(" payload:");
|
|
TL_HCI_CMD_DBG_BUF(p_acldata_packet->AclDataSerial.acl_data, p_acldata_packet->AclDataSerial.length, "");
|
|
}*/
|
|
TL_HCI_CMD_DBG_MSG("\r\n");
|
|
/*TL_HCI_CMD_DBG_RAW(&p_acldata_packet->AclDataSerial, p_acldata_packet->AclDataSerial.length+TL_CMD_HDR_SIZE);*/
|
|
break;
|
|
80135e2: e020 b.n 8013626 <OutputDbgTrace+0xae>
|
|
TL_HCI_CMD_DBG_MSG(" ACL Data Tx Ack received");
|
|
TL_HCI_CMD_DBG_MSG("\r\n");
|
|
break;
|
|
|
|
case TL_MB_BLE_CMD_RSP:
|
|
p_evt_packet = (TL_EvtPacket_t*)buffer;
|
|
80135e4: 683b ldr r3, [r7, #0]
|
|
80135e6: 617b str r3, [r7, #20]
|
|
switch(p_evt_packet->evtserial.evt.evtcode)
|
|
80135e8: 697b ldr r3, [r7, #20]
|
|
80135ea: 7a5b ldrb r3, [r3, #9]
|
|
80135ec: 2b0e cmp r3, #14
|
|
80135ee: d001 beq.n 80135f4 <OutputDbgTrace+0x7c>
|
|
80135f0: 2b0f cmp r3, #15
|
|
}
|
|
break;
|
|
|
|
default:
|
|
TL_HCI_CMD_DBG_MSG("unknown ble rsp received: %02X", p_evt_packet->evtserial.evt.evtcode);
|
|
break;
|
|
80135f2: e000 b.n 80135f6 <OutputDbgTrace+0x7e>
|
|
break;
|
|
80135f4: bf00 nop
|
|
}
|
|
|
|
TL_HCI_CMD_DBG_MSG("\r\n");
|
|
|
|
TL_HCI_CMD_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
|
|
break;
|
|
80135f6: e016 b.n 8013626 <OutputDbgTrace+0xae>
|
|
|
|
case TL_MB_BLE_ASYNCH_EVT:
|
|
p_evt_packet = (TL_EvtPacket_t*)buffer;
|
|
80135f8: 683b ldr r3, [r7, #0]
|
|
80135fa: 617b str r3, [r7, #20]
|
|
if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE)
|
|
80135fc: 697b ldr r3, [r7, #20]
|
|
80135fe: 7a5b ldrb r3, [r3, #9]
|
|
8013600: 2bff cmp r3, #255 @ 0xff
|
|
}
|
|
|
|
TL_HCI_EVT_DBG_MSG("\r\n");
|
|
|
|
TL_HCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
|
|
break;
|
|
8013602: e010 b.n 8013626 <OutputDbgTrace+0xae>
|
|
|
|
case TL_MB_SYS_CMD:
|
|
p_cmd_packet = (TL_CmdPacket_t*)buffer;
|
|
8013604: 683b ldr r3, [r7, #0]
|
|
8013606: 60fb str r3, [r7, #12]
|
|
TL_SHCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, "");
|
|
}
|
|
TL_SHCI_CMD_DBG_MSG("\r\n");
|
|
|
|
TL_SHCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE);
|
|
break;
|
|
8013608: e00d b.n 8013626 <OutputDbgTrace+0xae>
|
|
|
|
case TL_MB_SYS_CMD_RSP:
|
|
p_cmd_rsp_packet = (TL_EvtSerial_t*)buffer;
|
|
801360a: 683b ldr r3, [r7, #0]
|
|
801360c: 613b str r3, [r7, #16]
|
|
switch(p_cmd_rsp_packet->evt.evtcode)
|
|
801360e: 693b ldr r3, [r7, #16]
|
|
8013610: 785b ldrb r3, [r3, #1]
|
|
8013612: 2b0e cmp r3, #14
|
|
}
|
|
break;
|
|
|
|
default:
|
|
TL_SHCI_CMD_DBG_MSG("unknown sys rsp received: %02X", p_cmd_rsp_packet->evt.evtcode);
|
|
break;
|
|
8013614: bf00 nop
|
|
}
|
|
|
|
TL_SHCI_CMD_DBG_MSG("\r\n");
|
|
|
|
TL_SHCI_CMD_DBG_RAW(&p_cmd_rsp_packet->evt, p_cmd_rsp_packet->evt.plen+TL_EVT_HDR_SIZE);
|
|
break;
|
|
8013616: e006 b.n 8013626 <OutputDbgTrace+0xae>
|
|
|
|
case TL_MB_SYS_ASYNCH_EVT:
|
|
p_evt_packet = (TL_EvtPacket_t*)buffer;
|
|
8013618: 683b ldr r3, [r7, #0]
|
|
801361a: 617b str r3, [r7, #20]
|
|
if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE)
|
|
801361c: 697b ldr r3, [r7, #20]
|
|
801361e: 7a5b ldrb r3, [r3, #9]
|
|
8013620: 2bff cmp r3, #255 @ 0xff
|
|
}
|
|
|
|
TL_SHCI_EVT_DBG_MSG("\r\n");
|
|
|
|
TL_SHCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
|
|
break;
|
|
8013622: e000 b.n 8013626 <OutputDbgTrace+0xae>
|
|
|
|
default:
|
|
break;
|
|
8013624: bf00 nop
|
|
}
|
|
|
|
return;
|
|
8013626: bf00 nop
|
|
}
|
|
8013628: 371c adds r7, #28
|
|
801362a: 46bd mov sp, r7
|
|
801362c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8013630: 4770 bx lr
|
|
8013632: bf00 nop
|
|
|
|
08013634 <OTP_Read>:
|
|
/* Global variables ----------------------------------------------------------*/
|
|
/* Private function prototypes -----------------------------------------------*/
|
|
/* Functions Definition ------------------------------------------------------*/
|
|
|
|
uint8_t * OTP_Read( uint8_t id )
|
|
{
|
|
8013634: b480 push {r7}
|
|
8013636: b085 sub sp, #20
|
|
8013638: af00 add r7, sp, #0
|
|
801363a: 4603 mov r3, r0
|
|
801363c: 71fb strb r3, [r7, #7]
|
|
uint8_t *p_id;
|
|
|
|
p_id = (uint8_t*)(CFG_OTP_END_ADRESS - 7) ;
|
|
801363e: 4b0f ldr r3, [pc, #60] @ (801367c <OTP_Read+0x48>)
|
|
8013640: 60fb str r3, [r7, #12]
|
|
|
|
while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) )
|
|
8013642: e002 b.n 801364a <OTP_Read+0x16>
|
|
{
|
|
p_id -= 8 ;
|
|
8013644: 68fb ldr r3, [r7, #12]
|
|
8013646: 3b08 subs r3, #8
|
|
8013648: 60fb str r3, [r7, #12]
|
|
while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) )
|
|
801364a: 68fb ldr r3, [r7, #12]
|
|
801364c: 3307 adds r3, #7
|
|
801364e: 781b ldrb r3, [r3, #0]
|
|
8013650: 79fa ldrb r2, [r7, #7]
|
|
8013652: 429a cmp r2, r3
|
|
8013654: d003 beq.n 801365e <OTP_Read+0x2a>
|
|
8013656: 68fb ldr r3, [r7, #12]
|
|
8013658: 4a09 ldr r2, [pc, #36] @ (8013680 <OTP_Read+0x4c>)
|
|
801365a: 4293 cmp r3, r2
|
|
801365c: d1f2 bne.n 8013644 <OTP_Read+0x10>
|
|
}
|
|
|
|
if((*( p_id + 7 )) != id)
|
|
801365e: 68fb ldr r3, [r7, #12]
|
|
8013660: 3307 adds r3, #7
|
|
8013662: 781b ldrb r3, [r3, #0]
|
|
8013664: 79fa ldrb r2, [r7, #7]
|
|
8013666: 429a cmp r2, r3
|
|
8013668: d001 beq.n 801366e <OTP_Read+0x3a>
|
|
{
|
|
p_id = 0 ;
|
|
801366a: 2300 movs r3, #0
|
|
801366c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return p_id ;
|
|
801366e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8013670: 4618 mov r0, r3
|
|
8013672: 3714 adds r7, #20
|
|
8013674: 46bd mov sp, r7
|
|
8013676: f85d 7b04 ldr.w r7, [sp], #4
|
|
801367a: 4770 bx lr
|
|
801367c: 1fff73f8 .word 0x1fff73f8
|
|
8013680: 1fff7000 .word 0x1fff7000
|
|
|
|
08013684 <LST_init_head>:
|
|
|
|
/******************************************************************************
|
|
* Function Definitions
|
|
******************************************************************************/
|
|
void LST_init_head (tListNode * listHead)
|
|
{
|
|
8013684: b480 push {r7}
|
|
8013686: b083 sub sp, #12
|
|
8013688: af00 add r7, sp, #0
|
|
801368a: 6078 str r0, [r7, #4]
|
|
listHead->next = listHead;
|
|
801368c: 687b ldr r3, [r7, #4]
|
|
801368e: 687a ldr r2, [r7, #4]
|
|
8013690: 601a str r2, [r3, #0]
|
|
listHead->prev = listHead;
|
|
8013692: 687b ldr r3, [r7, #4]
|
|
8013694: 687a ldr r2, [r7, #4]
|
|
8013696: 605a str r2, [r3, #4]
|
|
}
|
|
8013698: bf00 nop
|
|
801369a: 370c adds r7, #12
|
|
801369c: 46bd mov sp, r7
|
|
801369e: f85d 7b04 ldr.w r7, [sp], #4
|
|
80136a2: 4770 bx lr
|
|
|
|
080136a4 <LST_is_empty>:
|
|
|
|
uint8_t LST_is_empty (tListNode * listHead)
|
|
{
|
|
80136a4: b480 push {r7}
|
|
80136a6: b087 sub sp, #28
|
|
80136a8: af00 add r7, sp, #0
|
|
80136aa: 6078 str r0, [r7, #4]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80136ac: f3ef 8310 mrs r3, PRIMASK
|
|
80136b0: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80136b2: 68fb ldr r3, [r7, #12]
|
|
uint32_t primask_bit;
|
|
uint8_t return_value;
|
|
|
|
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
|
80136b4: 613b str r3, [r7, #16]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80136b6: b672 cpsid i
|
|
}
|
|
80136b8: bf00 nop
|
|
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
|
if(listHead->next == listHead)
|
|
80136ba: 687b ldr r3, [r7, #4]
|
|
80136bc: 681b ldr r3, [r3, #0]
|
|
80136be: 687a ldr r2, [r7, #4]
|
|
80136c0: 429a cmp r2, r3
|
|
80136c2: d102 bne.n 80136ca <LST_is_empty+0x26>
|
|
{
|
|
return_value = TRUE;
|
|
80136c4: 2301 movs r3, #1
|
|
80136c6: 75fb strb r3, [r7, #23]
|
|
80136c8: e001 b.n 80136ce <LST_is_empty+0x2a>
|
|
}
|
|
else
|
|
{
|
|
return_value = FALSE;
|
|
80136ca: 2300 movs r3, #0
|
|
80136cc: 75fb strb r3, [r7, #23]
|
|
80136ce: 693b ldr r3, [r7, #16]
|
|
80136d0: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80136d2: 68bb ldr r3, [r7, #8]
|
|
80136d4: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80136d8: bf00 nop
|
|
}
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
|
|
return return_value;
|
|
80136da: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80136dc: 4618 mov r0, r3
|
|
80136de: 371c adds r7, #28
|
|
80136e0: 46bd mov sp, r7
|
|
80136e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80136e6: 4770 bx lr
|
|
|
|
080136e8 <LST_insert_head>:
|
|
|
|
void LST_insert_head (tListNode * listHead, tListNode * node)
|
|
{
|
|
80136e8: b480 push {r7}
|
|
80136ea: b087 sub sp, #28
|
|
80136ec: af00 add r7, sp, #0
|
|
80136ee: 6078 str r0, [r7, #4]
|
|
80136f0: 6039 str r1, [r7, #0]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80136f2: f3ef 8310 mrs r3, PRIMASK
|
|
80136f6: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80136f8: 68fb ldr r3, [r7, #12]
|
|
uint32_t primask_bit;
|
|
|
|
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
|
80136fa: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80136fc: b672 cpsid i
|
|
}
|
|
80136fe: bf00 nop
|
|
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
|
|
|
node->next = listHead->next;
|
|
8013700: 687b ldr r3, [r7, #4]
|
|
8013702: 681a ldr r2, [r3, #0]
|
|
8013704: 683b ldr r3, [r7, #0]
|
|
8013706: 601a str r2, [r3, #0]
|
|
node->prev = listHead;
|
|
8013708: 683b ldr r3, [r7, #0]
|
|
801370a: 687a ldr r2, [r7, #4]
|
|
801370c: 605a str r2, [r3, #4]
|
|
listHead->next = node;
|
|
801370e: 687b ldr r3, [r7, #4]
|
|
8013710: 683a ldr r2, [r7, #0]
|
|
8013712: 601a str r2, [r3, #0]
|
|
(node->next)->prev = node;
|
|
8013714: 683b ldr r3, [r7, #0]
|
|
8013716: 681b ldr r3, [r3, #0]
|
|
8013718: 683a ldr r2, [r7, #0]
|
|
801371a: 605a str r2, [r3, #4]
|
|
801371c: 697b ldr r3, [r7, #20]
|
|
801371e: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8013720: 693b ldr r3, [r7, #16]
|
|
8013722: f383 8810 msr PRIMASK, r3
|
|
}
|
|
8013726: bf00 nop
|
|
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
}
|
|
8013728: bf00 nop
|
|
801372a: 371c adds r7, #28
|
|
801372c: 46bd mov sp, r7
|
|
801372e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8013732: 4770 bx lr
|
|
|
|
08013734 <LST_insert_tail>:
|
|
|
|
|
|
void LST_insert_tail (tListNode * listHead, tListNode * node)
|
|
{
|
|
8013734: b480 push {r7}
|
|
8013736: b087 sub sp, #28
|
|
8013738: af00 add r7, sp, #0
|
|
801373a: 6078 str r0, [r7, #4]
|
|
801373c: 6039 str r1, [r7, #0]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
801373e: f3ef 8310 mrs r3, PRIMASK
|
|
8013742: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8013744: 68fb ldr r3, [r7, #12]
|
|
uint32_t primask_bit;
|
|
|
|
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
|
8013746: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8013748: b672 cpsid i
|
|
}
|
|
801374a: bf00 nop
|
|
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
|
|
|
node->next = listHead;
|
|
801374c: 683b ldr r3, [r7, #0]
|
|
801374e: 687a ldr r2, [r7, #4]
|
|
8013750: 601a str r2, [r3, #0]
|
|
node->prev = listHead->prev;
|
|
8013752: 687b ldr r3, [r7, #4]
|
|
8013754: 685a ldr r2, [r3, #4]
|
|
8013756: 683b ldr r3, [r7, #0]
|
|
8013758: 605a str r2, [r3, #4]
|
|
listHead->prev = node;
|
|
801375a: 687b ldr r3, [r7, #4]
|
|
801375c: 683a ldr r2, [r7, #0]
|
|
801375e: 605a str r2, [r3, #4]
|
|
(node->prev)->next = node;
|
|
8013760: 683b ldr r3, [r7, #0]
|
|
8013762: 685b ldr r3, [r3, #4]
|
|
8013764: 683a ldr r2, [r7, #0]
|
|
8013766: 601a str r2, [r3, #0]
|
|
8013768: 697b ldr r3, [r7, #20]
|
|
801376a: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
801376c: 693b ldr r3, [r7, #16]
|
|
801376e: f383 8810 msr PRIMASK, r3
|
|
}
|
|
8013772: bf00 nop
|
|
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
}
|
|
8013774: bf00 nop
|
|
8013776: 371c adds r7, #28
|
|
8013778: 46bd mov sp, r7
|
|
801377a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801377e: 4770 bx lr
|
|
|
|
08013780 <LST_remove_node>:
|
|
|
|
|
|
void LST_remove_node (tListNode * node)
|
|
{
|
|
8013780: b480 push {r7}
|
|
8013782: b087 sub sp, #28
|
|
8013784: af00 add r7, sp, #0
|
|
8013786: 6078 str r0, [r7, #4]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
8013788: f3ef 8310 mrs r3, PRIMASK
|
|
801378c: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
801378e: 68fb ldr r3, [r7, #12]
|
|
uint32_t primask_bit;
|
|
|
|
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
|
8013790: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8013792: b672 cpsid i
|
|
}
|
|
8013794: bf00 nop
|
|
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
|
|
|
(node->prev)->next = node->next;
|
|
8013796: 687b ldr r3, [r7, #4]
|
|
8013798: 685b ldr r3, [r3, #4]
|
|
801379a: 687a ldr r2, [r7, #4]
|
|
801379c: 6812 ldr r2, [r2, #0]
|
|
801379e: 601a str r2, [r3, #0]
|
|
(node->next)->prev = node->prev;
|
|
80137a0: 687b ldr r3, [r7, #4]
|
|
80137a2: 681b ldr r3, [r3, #0]
|
|
80137a4: 687a ldr r2, [r7, #4]
|
|
80137a6: 6852 ldr r2, [r2, #4]
|
|
80137a8: 605a str r2, [r3, #4]
|
|
80137aa: 697b ldr r3, [r7, #20]
|
|
80137ac: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80137ae: 693b ldr r3, [r7, #16]
|
|
80137b0: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80137b4: bf00 nop
|
|
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
}
|
|
80137b6: bf00 nop
|
|
80137b8: 371c adds r7, #28
|
|
80137ba: 46bd mov sp, r7
|
|
80137bc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80137c0: 4770 bx lr
|
|
|
|
080137c2 <LST_remove_head>:
|
|
|
|
|
|
void LST_remove_head (tListNode * listHead, tListNode ** node )
|
|
{
|
|
80137c2: b580 push {r7, lr}
|
|
80137c4: b086 sub sp, #24
|
|
80137c6: af00 add r7, sp, #0
|
|
80137c8: 6078 str r0, [r7, #4]
|
|
80137ca: 6039 str r1, [r7, #0]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80137cc: f3ef 8310 mrs r3, PRIMASK
|
|
80137d0: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80137d2: 68fb ldr r3, [r7, #12]
|
|
uint32_t primask_bit;
|
|
|
|
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
|
|
80137d4: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80137d6: b672 cpsid i
|
|
}
|
|
80137d8: bf00 nop
|
|
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
|
|
|
|
*node = listHead->next;
|
|
80137da: 687b ldr r3, [r7, #4]
|
|
80137dc: 681a ldr r2, [r3, #0]
|
|
80137de: 683b ldr r3, [r7, #0]
|
|
80137e0: 601a str r2, [r3, #0]
|
|
LST_remove_node (listHead->next);
|
|
80137e2: 687b ldr r3, [r7, #4]
|
|
80137e4: 681b ldr r3, [r3, #0]
|
|
80137e6: 4618 mov r0, r3
|
|
80137e8: f7ff ffca bl 8013780 <LST_remove_node>
|
|
80137ec: 697b ldr r3, [r7, #20]
|
|
80137ee: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80137f0: 693b ldr r3, [r7, #16]
|
|
80137f2: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80137f6: bf00 nop
|
|
|
|
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
|
|
}
|
|
80137f8: bf00 nop
|
|
80137fa: 3718 adds r7, #24
|
|
80137fc: 46bd mov sp, r7
|
|
80137fe: bd80 pop {r7, pc}
|
|
|
|
08013800 <__NVIC_SetPriority>:
|
|
{
|
|
8013800: b480 push {r7}
|
|
8013802: b083 sub sp, #12
|
|
8013804: af00 add r7, sp, #0
|
|
8013806: 4603 mov r3, r0
|
|
8013808: 6039 str r1, [r7, #0]
|
|
801380a: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
801380c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8013810: 2b00 cmp r3, #0
|
|
8013812: db0a blt.n 801382a <__NVIC_SetPriority+0x2a>
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8013814: 683b ldr r3, [r7, #0]
|
|
8013816: b2da uxtb r2, r3
|
|
8013818: 490c ldr r1, [pc, #48] @ (801384c <__NVIC_SetPriority+0x4c>)
|
|
801381a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
801381e: 0112 lsls r2, r2, #4
|
|
8013820: b2d2 uxtb r2, r2
|
|
8013822: 440b add r3, r1
|
|
8013824: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
8013828: e00a b.n 8013840 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
801382a: 683b ldr r3, [r7, #0]
|
|
801382c: b2da uxtb r2, r3
|
|
801382e: 4908 ldr r1, [pc, #32] @ (8013850 <__NVIC_SetPriority+0x50>)
|
|
8013830: 79fb ldrb r3, [r7, #7]
|
|
8013832: f003 030f and.w r3, r3, #15
|
|
8013836: 3b04 subs r3, #4
|
|
8013838: 0112 lsls r2, r2, #4
|
|
801383a: b2d2 uxtb r2, r2
|
|
801383c: 440b add r3, r1
|
|
801383e: 761a strb r2, [r3, #24]
|
|
}
|
|
8013840: bf00 nop
|
|
8013842: 370c adds r7, #12
|
|
8013844: 46bd mov sp, r7
|
|
8013846: f85d 7b04 ldr.w r7, [sp], #4
|
|
801384a: 4770 bx lr
|
|
801384c: e000e100 .word 0xe000e100
|
|
8013850: e000ed00 .word 0xe000ed00
|
|
|
|
08013854 <SysTick_Handler>:
|
|
|
|
/*
|
|
SysTick handler implementation that also clears overflow flag.
|
|
*/
|
|
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
|
|
void SysTick_Handler (void) {
|
|
8013854: b580 push {r7, lr}
|
|
8013856: af00 add r7, sp, #0
|
|
#if (configUSE_TICKLESS_IDLE == 0)
|
|
/* Clear overflow flag */
|
|
SysTick->CTRL;
|
|
8013858: 4b05 ldr r3, [pc, #20] @ (8013870 <SysTick_Handler+0x1c>)
|
|
801385a: 681b ldr r3, [r3, #0]
|
|
#endif
|
|
|
|
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
|
|
801385c: f002 ff64 bl 8016728 <xTaskGetSchedulerState>
|
|
8013860: 4603 mov r3, r0
|
|
8013862: 2b01 cmp r3, #1
|
|
8013864: d001 beq.n 801386a <SysTick_Handler+0x16>
|
|
/* Call tick handler */
|
|
xPortSysTickHandler();
|
|
8013866: f004 faf7 bl 8017e58 <xPortSysTickHandler>
|
|
}
|
|
}
|
|
801386a: bf00 nop
|
|
801386c: bd80 pop {r7, pc}
|
|
801386e: bf00 nop
|
|
8013870: e000e010 .word 0xe000e010
|
|
|
|
08013874 <SVC_Setup>:
|
|
#endif /* SysTick */
|
|
|
|
/*
|
|
Setup SVC to reset value.
|
|
*/
|
|
__STATIC_INLINE void SVC_Setup (void) {
|
|
8013874: b580 push {r7, lr}
|
|
8013876: af00 add r7, sp, #0
|
|
#if (__ARM_ARCH_7A__ == 0U)
|
|
/* Service Call interrupt might be configured before kernel start */
|
|
/* and when its priority is lower or equal to BASEPRI, svc instruction */
|
|
/* causes a Hard Fault. */
|
|
NVIC_SetPriority (SVCall_IRQn, 0U);
|
|
8013878: 2100 movs r1, #0
|
|
801387a: f06f 0004 mvn.w r0, #4
|
|
801387e: f7ff ffbf bl 8013800 <__NVIC_SetPriority>
|
|
#endif
|
|
}
|
|
8013882: bf00 nop
|
|
8013884: bd80 pop {r7, pc}
|
|
|
|
08013886 <IRQ_Context>:
|
|
#endif
|
|
|
|
/*
|
|
Determine if CPU executes from interrupt context or if interrupts are masked.
|
|
*/
|
|
__STATIC_INLINE uint32_t IRQ_Context (void) {
|
|
8013886: b580 push {r7, lr}
|
|
8013888: b086 sub sp, #24
|
|
801388a: af00 add r7, sp, #0
|
|
uint32_t irq;
|
|
BaseType_t state;
|
|
|
|
irq = 0U;
|
|
801388c: 2300 movs r3, #0
|
|
801388e: 617b str r3, [r7, #20]
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
|
8013890: f3ef 8305 mrs r3, IPSR
|
|
8013894: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8013896: 68fb ldr r3, [r7, #12]
|
|
|
|
if (IS_IRQ_MODE()) {
|
|
8013898: 2b00 cmp r3, #0
|
|
801389a: d002 beq.n 80138a2 <IRQ_Context+0x1c>
|
|
/* Called from interrupt context */
|
|
irq = 1U;
|
|
801389c: 2301 movs r3, #1
|
|
801389e: 617b str r3, [r7, #20]
|
|
80138a0: e013 b.n 80138ca <IRQ_Context+0x44>
|
|
}
|
|
else {
|
|
/* Get FreeRTOS scheduler state */
|
|
state = xTaskGetSchedulerState();
|
|
80138a2: f002 ff41 bl 8016728 <xTaskGetSchedulerState>
|
|
80138a6: 6138 str r0, [r7, #16]
|
|
|
|
if (state != taskSCHEDULER_NOT_STARTED) {
|
|
80138a8: 693b ldr r3, [r7, #16]
|
|
80138aa: 2b01 cmp r3, #1
|
|
80138ac: d00d beq.n 80138ca <IRQ_Context+0x44>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80138ae: f3ef 8310 mrs r3, PRIMASK
|
|
80138b2: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
80138b4: 68bb ldr r3, [r7, #8]
|
|
/* Scheduler was started */
|
|
if (IS_IRQ_MASKED()) {
|
|
80138b6: 2b00 cmp r3, #0
|
|
80138b8: d105 bne.n 80138c6 <IRQ_Context+0x40>
|
|
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
|
|
80138ba: f3ef 8311 mrs r3, BASEPRI
|
|
80138be: 607b str r3, [r7, #4]
|
|
return(result);
|
|
80138c0: 687b ldr r3, [r7, #4]
|
|
80138c2: 2b00 cmp r3, #0
|
|
80138c4: d001 beq.n 80138ca <IRQ_Context+0x44>
|
|
/* Interrupts are masked */
|
|
irq = 1U;
|
|
80138c6: 2301 movs r3, #1
|
|
80138c8: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return context, 0: thread context, 1: IRQ context */
|
|
return (irq);
|
|
80138ca: 697b ldr r3, [r7, #20]
|
|
}
|
|
80138cc: 4618 mov r0, r3
|
|
80138ce: 3718 adds r7, #24
|
|
80138d0: 46bd mov sp, r7
|
|
80138d2: bd80 pop {r7, pc}
|
|
|
|
080138d4 <osKernelInitialize>:
|
|
/* ==== Kernel Management Functions ==== */
|
|
|
|
/*
|
|
Initialize the RTOS Kernel.
|
|
*/
|
|
osStatus_t osKernelInitialize (void) {
|
|
80138d4: b580 push {r7, lr}
|
|
80138d6: b082 sub sp, #8
|
|
80138d8: af00 add r7, sp, #0
|
|
osStatus_t stat;
|
|
BaseType_t state;
|
|
|
|
if (IRQ_Context() != 0U) {
|
|
80138da: f7ff ffd4 bl 8013886 <IRQ_Context>
|
|
80138de: 4603 mov r3, r0
|
|
80138e0: 2b00 cmp r3, #0
|
|
80138e2: d003 beq.n 80138ec <osKernelInitialize+0x18>
|
|
stat = osErrorISR;
|
|
80138e4: f06f 0305 mvn.w r3, #5
|
|
80138e8: 607b str r3, [r7, #4]
|
|
80138ea: e012 b.n 8013912 <osKernelInitialize+0x3e>
|
|
}
|
|
else {
|
|
state = xTaskGetSchedulerState();
|
|
80138ec: f002 ff1c bl 8016728 <xTaskGetSchedulerState>
|
|
80138f0: 6038 str r0, [r7, #0]
|
|
|
|
/* Initialize if scheduler not started and not initialized before */
|
|
if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelInactive)) {
|
|
80138f2: 683b ldr r3, [r7, #0]
|
|
80138f4: 2b01 cmp r3, #1
|
|
80138f6: d109 bne.n 801390c <osKernelInitialize+0x38>
|
|
80138f8: 4b08 ldr r3, [pc, #32] @ (801391c <osKernelInitialize+0x48>)
|
|
80138fa: 681b ldr r3, [r3, #0]
|
|
80138fc: 2b00 cmp r3, #0
|
|
80138fe: d105 bne.n 801390c <osKernelInitialize+0x38>
|
|
#endif
|
|
#if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
|
|
/* Initialize the memory regions when using heap_5 variant */
|
|
vPortDefineHeapRegions (configHEAP_5_REGIONS);
|
|
#endif
|
|
KernelState = osKernelReady;
|
|
8013900: 4b06 ldr r3, [pc, #24] @ (801391c <osKernelInitialize+0x48>)
|
|
8013902: 2201 movs r2, #1
|
|
8013904: 601a str r2, [r3, #0]
|
|
stat = osOK;
|
|
8013906: 2300 movs r3, #0
|
|
8013908: 607b str r3, [r7, #4]
|
|
801390a: e002 b.n 8013912 <osKernelInitialize+0x3e>
|
|
} else {
|
|
stat = osError;
|
|
801390c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8013910: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
/* Return execution status */
|
|
return (stat);
|
|
8013912: 687b ldr r3, [r7, #4]
|
|
}
|
|
8013914: 4618 mov r0, r3
|
|
8013916: 3708 adds r7, #8
|
|
8013918: 46bd mov sp, r7
|
|
801391a: bd80 pop {r7, pc}
|
|
801391c: 200007cc .word 0x200007cc
|
|
|
|
08013920 <osKernelStart>:
|
|
}
|
|
|
|
/*
|
|
Start the RTOS Kernel scheduler.
|
|
*/
|
|
osStatus_t osKernelStart (void) {
|
|
8013920: b580 push {r7, lr}
|
|
8013922: b082 sub sp, #8
|
|
8013924: af00 add r7, sp, #0
|
|
osStatus_t stat;
|
|
BaseType_t state;
|
|
|
|
if (IRQ_Context() != 0U) {
|
|
8013926: f7ff ffae bl 8013886 <IRQ_Context>
|
|
801392a: 4603 mov r3, r0
|
|
801392c: 2b00 cmp r3, #0
|
|
801392e: d003 beq.n 8013938 <osKernelStart+0x18>
|
|
stat = osErrorISR;
|
|
8013930: f06f 0305 mvn.w r3, #5
|
|
8013934: 607b str r3, [r7, #4]
|
|
8013936: e016 b.n 8013966 <osKernelStart+0x46>
|
|
}
|
|
else {
|
|
state = xTaskGetSchedulerState();
|
|
8013938: f002 fef6 bl 8016728 <xTaskGetSchedulerState>
|
|
801393c: 6038 str r0, [r7, #0]
|
|
|
|
/* Start scheduler if initialized and not started before */
|
|
if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelReady)) {
|
|
801393e: 683b ldr r3, [r7, #0]
|
|
8013940: 2b01 cmp r3, #1
|
|
8013942: d10d bne.n 8013960 <osKernelStart+0x40>
|
|
8013944: 4b0a ldr r3, [pc, #40] @ (8013970 <osKernelStart+0x50>)
|
|
8013946: 681b ldr r3, [r3, #0]
|
|
8013948: 2b01 cmp r3, #1
|
|
801394a: d109 bne.n 8013960 <osKernelStart+0x40>
|
|
/* Ensure SVC priority is at the reset value */
|
|
SVC_Setup();
|
|
801394c: f7ff ff92 bl 8013874 <SVC_Setup>
|
|
/* Change state to ensure correct API flow */
|
|
KernelState = osKernelRunning;
|
|
8013950: 4b07 ldr r3, [pc, #28] @ (8013970 <osKernelStart+0x50>)
|
|
8013952: 2202 movs r2, #2
|
|
8013954: 601a str r2, [r3, #0]
|
|
/* Start the kernel scheduler */
|
|
vTaskStartScheduler();
|
|
8013956: f002 f8f1 bl 8015b3c <vTaskStartScheduler>
|
|
stat = osOK;
|
|
801395a: 2300 movs r3, #0
|
|
801395c: 607b str r3, [r7, #4]
|
|
801395e: e002 b.n 8013966 <osKernelStart+0x46>
|
|
} else {
|
|
stat = osError;
|
|
8013960: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8013964: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
/* Return execution status */
|
|
return (stat);
|
|
8013966: 687b ldr r3, [r7, #4]
|
|
}
|
|
8013968: 4618 mov r0, r3
|
|
801396a: 3708 adds r7, #8
|
|
801396c: 46bd mov sp, r7
|
|
801396e: bd80 pop {r7, pc}
|
|
8013970: 200007cc .word 0x200007cc
|
|
|
|
08013974 <osThreadNew>:
|
|
Limitations:
|
|
- The memory for control block and stack must be provided in the osThreadAttr_t
|
|
structure in order to allocate object statically.
|
|
- Attribute osThreadJoinable is not supported, NULL is returned if used.
|
|
*/
|
|
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
|
|
8013974: b580 push {r7, lr}
|
|
8013976: b08e sub sp, #56 @ 0x38
|
|
8013978: af04 add r7, sp, #16
|
|
801397a: 60f8 str r0, [r7, #12]
|
|
801397c: 60b9 str r1, [r7, #8]
|
|
801397e: 607a str r2, [r7, #4]
|
|
uint32_t stack;
|
|
TaskHandle_t hTask;
|
|
UBaseType_t prio;
|
|
int32_t mem;
|
|
|
|
hTask = NULL;
|
|
8013980: 2300 movs r3, #0
|
|
8013982: 617b str r3, [r7, #20]
|
|
|
|
if ((IRQ_Context() == 0U) && (func != NULL)) {
|
|
8013984: f7ff ff7f bl 8013886 <IRQ_Context>
|
|
8013988: 4603 mov r3, r0
|
|
801398a: 2b00 cmp r3, #0
|
|
801398c: d17f bne.n 8013a8e <osThreadNew+0x11a>
|
|
801398e: 68fb ldr r3, [r7, #12]
|
|
8013990: 2b00 cmp r3, #0
|
|
8013992: d07c beq.n 8013a8e <osThreadNew+0x11a>
|
|
stack = configMINIMAL_STACK_SIZE;
|
|
8013994: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8013998: 623b str r3, [r7, #32]
|
|
prio = (UBaseType_t)osPriorityNormal;
|
|
801399a: 2318 movs r3, #24
|
|
801399c: 61fb str r3, [r7, #28]
|
|
|
|
name = NULL;
|
|
801399e: 2300 movs r3, #0
|
|
80139a0: 627b str r3, [r7, #36] @ 0x24
|
|
mem = -1;
|
|
80139a2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80139a6: 61bb str r3, [r7, #24]
|
|
|
|
if (attr != NULL) {
|
|
80139a8: 687b ldr r3, [r7, #4]
|
|
80139aa: 2b00 cmp r3, #0
|
|
80139ac: d045 beq.n 8013a3a <osThreadNew+0xc6>
|
|
if (attr->name != NULL) {
|
|
80139ae: 687b ldr r3, [r7, #4]
|
|
80139b0: 681b ldr r3, [r3, #0]
|
|
80139b2: 2b00 cmp r3, #0
|
|
80139b4: d002 beq.n 80139bc <osThreadNew+0x48>
|
|
name = attr->name;
|
|
80139b6: 687b ldr r3, [r7, #4]
|
|
80139b8: 681b ldr r3, [r3, #0]
|
|
80139ba: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
if (attr->priority != osPriorityNone) {
|
|
80139bc: 687b ldr r3, [r7, #4]
|
|
80139be: 699b ldr r3, [r3, #24]
|
|
80139c0: 2b00 cmp r3, #0
|
|
80139c2: d002 beq.n 80139ca <osThreadNew+0x56>
|
|
prio = (UBaseType_t)attr->priority;
|
|
80139c4: 687b ldr r3, [r7, #4]
|
|
80139c6: 699b ldr r3, [r3, #24]
|
|
80139c8: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
|
|
80139ca: 69fb ldr r3, [r7, #28]
|
|
80139cc: 2b00 cmp r3, #0
|
|
80139ce: d008 beq.n 80139e2 <osThreadNew+0x6e>
|
|
80139d0: 69fb ldr r3, [r7, #28]
|
|
80139d2: 2b38 cmp r3, #56 @ 0x38
|
|
80139d4: d805 bhi.n 80139e2 <osThreadNew+0x6e>
|
|
80139d6: 687b ldr r3, [r7, #4]
|
|
80139d8: 685b ldr r3, [r3, #4]
|
|
80139da: f003 0301 and.w r3, r3, #1
|
|
80139de: 2b00 cmp r3, #0
|
|
80139e0: d001 beq.n 80139e6 <osThreadNew+0x72>
|
|
/* Invalid priority or unsupported osThreadJoinable attribute used */
|
|
return (NULL);
|
|
80139e2: 2300 movs r3, #0
|
|
80139e4: e054 b.n 8013a90 <osThreadNew+0x11c>
|
|
}
|
|
|
|
if (attr->stack_size > 0U) {
|
|
80139e6: 687b ldr r3, [r7, #4]
|
|
80139e8: 695b ldr r3, [r3, #20]
|
|
80139ea: 2b00 cmp r3, #0
|
|
80139ec: d003 beq.n 80139f6 <osThreadNew+0x82>
|
|
/* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */
|
|
/* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
|
|
stack = attr->stack_size / sizeof(StackType_t);
|
|
80139ee: 687b ldr r3, [r7, #4]
|
|
80139f0: 695b ldr r3, [r3, #20]
|
|
80139f2: 089b lsrs r3, r3, #2
|
|
80139f4: 623b str r3, [r7, #32]
|
|
}
|
|
|
|
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
|
|
80139f6: 687b ldr r3, [r7, #4]
|
|
80139f8: 689b ldr r3, [r3, #8]
|
|
80139fa: 2b00 cmp r3, #0
|
|
80139fc: d00e beq.n 8013a1c <osThreadNew+0xa8>
|
|
80139fe: 687b ldr r3, [r7, #4]
|
|
8013a00: 68db ldr r3, [r3, #12]
|
|
8013a02: 2bab cmp r3, #171 @ 0xab
|
|
8013a04: d90a bls.n 8013a1c <osThreadNew+0xa8>
|
|
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
|
|
8013a06: 687b ldr r3, [r7, #4]
|
|
8013a08: 691b ldr r3, [r3, #16]
|
|
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
|
|
8013a0a: 2b00 cmp r3, #0
|
|
8013a0c: d006 beq.n 8013a1c <osThreadNew+0xa8>
|
|
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
|
|
8013a0e: 687b ldr r3, [r7, #4]
|
|
8013a10: 695b ldr r3, [r3, #20]
|
|
8013a12: 2b00 cmp r3, #0
|
|
8013a14: d002 beq.n 8013a1c <osThreadNew+0xa8>
|
|
/* The memory for control block and stack is provided, use static object */
|
|
mem = 1;
|
|
8013a16: 2301 movs r3, #1
|
|
8013a18: 61bb str r3, [r7, #24]
|
|
8013a1a: e010 b.n 8013a3e <osThreadNew+0xca>
|
|
}
|
|
else {
|
|
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
|
|
8013a1c: 687b ldr r3, [r7, #4]
|
|
8013a1e: 689b ldr r3, [r3, #8]
|
|
8013a20: 2b00 cmp r3, #0
|
|
8013a22: d10c bne.n 8013a3e <osThreadNew+0xca>
|
|
8013a24: 687b ldr r3, [r7, #4]
|
|
8013a26: 68db ldr r3, [r3, #12]
|
|
8013a28: 2b00 cmp r3, #0
|
|
8013a2a: d108 bne.n 8013a3e <osThreadNew+0xca>
|
|
8013a2c: 687b ldr r3, [r7, #4]
|
|
8013a2e: 691b ldr r3, [r3, #16]
|
|
8013a30: 2b00 cmp r3, #0
|
|
8013a32: d104 bne.n 8013a3e <osThreadNew+0xca>
|
|
/* Control block and stack memory will be allocated from the dynamic pool */
|
|
mem = 0;
|
|
8013a34: 2300 movs r3, #0
|
|
8013a36: 61bb str r3, [r7, #24]
|
|
8013a38: e001 b.n 8013a3e <osThreadNew+0xca>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
mem = 0;
|
|
8013a3a: 2300 movs r3, #0
|
|
8013a3c: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
if (mem == 1) {
|
|
8013a3e: 69bb ldr r3, [r7, #24]
|
|
8013a40: 2b01 cmp r3, #1
|
|
8013a42: d110 bne.n 8013a66 <osThreadNew+0xf2>
|
|
#if (configSUPPORT_STATIC_ALLOCATION == 1)
|
|
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
|
|
8013a44: 687b ldr r3, [r7, #4]
|
|
8013a46: 691b ldr r3, [r3, #16]
|
|
(StaticTask_t *)attr->cb_mem);
|
|
8013a48: 687a ldr r2, [r7, #4]
|
|
8013a4a: 6892 ldr r2, [r2, #8]
|
|
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
|
|
8013a4c: 9202 str r2, [sp, #8]
|
|
8013a4e: 9301 str r3, [sp, #4]
|
|
8013a50: 69fb ldr r3, [r7, #28]
|
|
8013a52: 9300 str r3, [sp, #0]
|
|
8013a54: 68bb ldr r3, [r7, #8]
|
|
8013a56: 6a3a ldr r2, [r7, #32]
|
|
8013a58: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8013a5a: 68f8 ldr r0, [r7, #12]
|
|
8013a5c: f001 fe80 bl 8015760 <xTaskCreateStatic>
|
|
8013a60: 4603 mov r3, r0
|
|
8013a62: 617b str r3, [r7, #20]
|
|
8013a64: e013 b.n 8013a8e <osThreadNew+0x11a>
|
|
#endif
|
|
}
|
|
else {
|
|
if (mem == 0) {
|
|
8013a66: 69bb ldr r3, [r7, #24]
|
|
8013a68: 2b00 cmp r3, #0
|
|
8013a6a: d110 bne.n 8013a8e <osThreadNew+0x11a>
|
|
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
|
|
if (xTaskCreate ((TaskFunction_t)func, name, (configSTACK_DEPTH_TYPE)stack, argument, prio, &hTask) != pdPASS) {
|
|
8013a6c: 6a3b ldr r3, [r7, #32]
|
|
8013a6e: b29a uxth r2, r3
|
|
8013a70: f107 0314 add.w r3, r7, #20
|
|
8013a74: 9301 str r3, [sp, #4]
|
|
8013a76: 69fb ldr r3, [r7, #28]
|
|
8013a78: 9300 str r3, [sp, #0]
|
|
8013a7a: 68bb ldr r3, [r7, #8]
|
|
8013a7c: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8013a7e: 68f8 ldr r0, [r7, #12]
|
|
8013a80: f001 fed3 bl 801582a <xTaskCreate>
|
|
8013a84: 4603 mov r3, r0
|
|
8013a86: 2b01 cmp r3, #1
|
|
8013a88: d001 beq.n 8013a8e <osThreadNew+0x11a>
|
|
hTask = NULL;
|
|
8013a8a: 2300 movs r3, #0
|
|
8013a8c: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return thread ID */
|
|
return ((osThreadId_t)hTask);
|
|
8013a8e: 697b ldr r3, [r7, #20]
|
|
}
|
|
8013a90: 4618 mov r0, r3
|
|
8013a92: 3728 adds r7, #40 @ 0x28
|
|
8013a94: 46bd mov sp, r7
|
|
8013a96: bd80 pop {r7, pc}
|
|
|
|
08013a98 <osThreadGetId>:
|
|
}
|
|
|
|
/*
|
|
Return the thread ID of the current running thread.
|
|
*/
|
|
osThreadId_t osThreadGetId (void) {
|
|
8013a98: b580 push {r7, lr}
|
|
8013a9a: b082 sub sp, #8
|
|
8013a9c: af00 add r7, sp, #0
|
|
osThreadId_t id;
|
|
|
|
id = (osThreadId_t)xTaskGetCurrentTaskHandle();
|
|
8013a9e: f002 fe33 bl 8016708 <xTaskGetCurrentTaskHandle>
|
|
8013aa2: 6078 str r0, [r7, #4]
|
|
|
|
/* Return thread ID */
|
|
return (id);
|
|
8013aa4: 687b ldr r3, [r7, #4]
|
|
}
|
|
8013aa6: 4618 mov r0, r3
|
|
8013aa8: 3708 adds r7, #8
|
|
8013aaa: 46bd mov sp, r7
|
|
8013aac: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08013ab0 <osThreadFlagsSet>:
|
|
|
|
#if (configUSE_OS2_THREAD_FLAGS == 1)
|
|
/*
|
|
Set the specified Thread Flags of a thread.
|
|
*/
|
|
uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
|
|
8013ab0: b580 push {r7, lr}
|
|
8013ab2: b088 sub sp, #32
|
|
8013ab4: af02 add r7, sp, #8
|
|
8013ab6: 6078 str r0, [r7, #4]
|
|
8013ab8: 6039 str r1, [r7, #0]
|
|
TaskHandle_t hTask = (TaskHandle_t)thread_id;
|
|
8013aba: 687b ldr r3, [r7, #4]
|
|
8013abc: 617b str r3, [r7, #20]
|
|
uint32_t rflags;
|
|
BaseType_t yield;
|
|
|
|
if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) {
|
|
8013abe: 697b ldr r3, [r7, #20]
|
|
8013ac0: 2b00 cmp r3, #0
|
|
8013ac2: d002 beq.n 8013aca <osThreadFlagsSet+0x1a>
|
|
8013ac4: 683b ldr r3, [r7, #0]
|
|
8013ac6: 2b00 cmp r3, #0
|
|
8013ac8: da03 bge.n 8013ad2 <osThreadFlagsSet+0x22>
|
|
rflags = (uint32_t)osErrorParameter;
|
|
8013aca: f06f 0303 mvn.w r3, #3
|
|
8013ace: 613b str r3, [r7, #16]
|
|
8013ad0: e03c b.n 8013b4c <osThreadFlagsSet+0x9c>
|
|
}
|
|
else {
|
|
rflags = (uint32_t)osError;
|
|
8013ad2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8013ad6: 613b str r3, [r7, #16]
|
|
|
|
if (IRQ_Context() != 0U) {
|
|
8013ad8: f7ff fed5 bl 8013886 <IRQ_Context>
|
|
8013adc: 4603 mov r3, r0
|
|
8013ade: 2b00 cmp r3, #0
|
|
8013ae0: d023 beq.n 8013b2a <osThreadFlagsSet+0x7a>
|
|
yield = pdFALSE;
|
|
8013ae2: 2300 movs r3, #0
|
|
8013ae4: 60fb str r3, [r7, #12]
|
|
|
|
(void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield);
|
|
8013ae6: f107 030c add.w r3, r7, #12
|
|
8013aea: 9301 str r3, [sp, #4]
|
|
8013aec: 2300 movs r3, #0
|
|
8013aee: 9300 str r3, [sp, #0]
|
|
8013af0: 2301 movs r3, #1
|
|
8013af2: 683a ldr r2, [r7, #0]
|
|
8013af4: 2100 movs r1, #0
|
|
8013af6: 6978 ldr r0, [r7, #20]
|
|
8013af8: f003 fa2c bl 8016f54 <xTaskGenericNotifyFromISR>
|
|
(void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL);
|
|
8013afc: 2300 movs r3, #0
|
|
8013afe: 9301 str r3, [sp, #4]
|
|
8013b00: f107 0310 add.w r3, r7, #16
|
|
8013b04: 9300 str r3, [sp, #0]
|
|
8013b06: 2300 movs r3, #0
|
|
8013b08: 2200 movs r2, #0
|
|
8013b0a: 2100 movs r1, #0
|
|
8013b0c: 6978 ldr r0, [r7, #20]
|
|
8013b0e: f003 fa21 bl 8016f54 <xTaskGenericNotifyFromISR>
|
|
|
|
portYIELD_FROM_ISR (yield);
|
|
8013b12: 68fb ldr r3, [r7, #12]
|
|
8013b14: 2b00 cmp r3, #0
|
|
8013b16: d019 beq.n 8013b4c <osThreadFlagsSet+0x9c>
|
|
8013b18: 4b0f ldr r3, [pc, #60] @ (8013b58 <osThreadFlagsSet+0xa8>)
|
|
8013b1a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8013b1e: 601a str r2, [r3, #0]
|
|
8013b20: f3bf 8f4f dsb sy
|
|
8013b24: f3bf 8f6f isb sy
|
|
8013b28: e010 b.n 8013b4c <osThreadFlagsSet+0x9c>
|
|
}
|
|
else {
|
|
(void)xTaskNotify (hTask, flags, eSetBits);
|
|
8013b2a: 2300 movs r3, #0
|
|
8013b2c: 9300 str r3, [sp, #0]
|
|
8013b2e: 2301 movs r3, #1
|
|
8013b30: 683a ldr r2, [r7, #0]
|
|
8013b32: 2100 movs r1, #0
|
|
8013b34: 6978 ldr r0, [r7, #20]
|
|
8013b36: f003 f8e5 bl 8016d04 <xTaskGenericNotify>
|
|
(void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags);
|
|
8013b3a: f107 0310 add.w r3, r7, #16
|
|
8013b3e: 9300 str r3, [sp, #0]
|
|
8013b40: 2300 movs r3, #0
|
|
8013b42: 2200 movs r2, #0
|
|
8013b44: 2100 movs r1, #0
|
|
8013b46: 6978 ldr r0, [r7, #20]
|
|
8013b48: f003 f8dc bl 8016d04 <xTaskGenericNotify>
|
|
}
|
|
}
|
|
/* Return flags after setting */
|
|
return (rflags);
|
|
8013b4c: 693b ldr r3, [r7, #16]
|
|
}
|
|
8013b4e: 4618 mov r0, r3
|
|
8013b50: 3718 adds r7, #24
|
|
8013b52: 46bd mov sp, r7
|
|
8013b54: bd80 pop {r7, pc}
|
|
8013b56: bf00 nop
|
|
8013b58: e000ed04 .word 0xe000ed04
|
|
|
|
08013b5c <osThreadFlagsWait>:
|
|
}
|
|
|
|
/*
|
|
Wait for one or more Thread Flags of the current running thread to become signaled.
|
|
*/
|
|
uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
|
|
8013b5c: b580 push {r7, lr}
|
|
8013b5e: b08e sub sp, #56 @ 0x38
|
|
8013b60: af02 add r7, sp, #8
|
|
8013b62: 60f8 str r0, [r7, #12]
|
|
8013b64: 60b9 str r1, [r7, #8]
|
|
8013b66: 607a str r2, [r7, #4]
|
|
uint32_t rflags, nval;
|
|
uint32_t clear;
|
|
TickType_t t0, td, tout;
|
|
BaseType_t rval;
|
|
|
|
if (IRQ_Context() != 0U) {
|
|
8013b68: f7ff fe8d bl 8013886 <IRQ_Context>
|
|
8013b6c: 4603 mov r3, r0
|
|
8013b6e: 2b00 cmp r3, #0
|
|
8013b70: d003 beq.n 8013b7a <osThreadFlagsWait+0x1e>
|
|
rflags = (uint32_t)osErrorISR;
|
|
8013b72: f06f 0305 mvn.w r3, #5
|
|
8013b76: 62fb str r3, [r7, #44] @ 0x2c
|
|
8013b78: e06e b.n 8013c58 <osThreadFlagsWait+0xfc>
|
|
}
|
|
else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {
|
|
8013b7a: 68fb ldr r3, [r7, #12]
|
|
8013b7c: 2b00 cmp r3, #0
|
|
8013b7e: da03 bge.n 8013b88 <osThreadFlagsWait+0x2c>
|
|
rflags = (uint32_t)osErrorParameter;
|
|
8013b80: f06f 0303 mvn.w r3, #3
|
|
8013b84: 62fb str r3, [r7, #44] @ 0x2c
|
|
8013b86: e067 b.n 8013c58 <osThreadFlagsWait+0xfc>
|
|
}
|
|
else {
|
|
if ((options & osFlagsNoClear) == osFlagsNoClear) {
|
|
8013b88: 68bb ldr r3, [r7, #8]
|
|
8013b8a: f003 0302 and.w r3, r3, #2
|
|
8013b8e: 2b00 cmp r3, #0
|
|
8013b90: d002 beq.n 8013b98 <osThreadFlagsWait+0x3c>
|
|
clear = 0U;
|
|
8013b92: 2300 movs r3, #0
|
|
8013b94: 62bb str r3, [r7, #40] @ 0x28
|
|
8013b96: e001 b.n 8013b9c <osThreadFlagsWait+0x40>
|
|
} else {
|
|
clear = flags;
|
|
8013b98: 68fb ldr r3, [r7, #12]
|
|
8013b9a: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
|
|
rflags = 0U;
|
|
8013b9c: 2300 movs r3, #0
|
|
8013b9e: 62fb str r3, [r7, #44] @ 0x2c
|
|
tout = timeout;
|
|
8013ba0: 687b ldr r3, [r7, #4]
|
|
8013ba2: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
t0 = xTaskGetTickCount();
|
|
8013ba4: f002 f94a bl 8015e3c <xTaskGetTickCount>
|
|
8013ba8: 6238 str r0, [r7, #32]
|
|
do {
|
|
rval = xTaskNotifyWait (0, clear, &nval, tout);
|
|
8013baa: f107 0214 add.w r2, r7, #20
|
|
8013bae: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8013bb0: 9300 str r3, [sp, #0]
|
|
8013bb2: 4613 mov r3, r2
|
|
8013bb4: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8013bb6: 2100 movs r1, #0
|
|
8013bb8: 2000 movs r0, #0
|
|
8013bba: f003 f823 bl 8016c04 <xTaskGenericNotifyWait>
|
|
8013bbe: 61f8 str r0, [r7, #28]
|
|
|
|
if (rval == pdPASS) {
|
|
8013bc0: 69fb ldr r3, [r7, #28]
|
|
8013bc2: 2b01 cmp r3, #1
|
|
8013bc4: d137 bne.n 8013c36 <osThreadFlagsWait+0xda>
|
|
rflags &= flags;
|
|
8013bc6: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8013bc8: 68fb ldr r3, [r7, #12]
|
|
8013bca: 4013 ands r3, r2
|
|
8013bcc: 62fb str r3, [r7, #44] @ 0x2c
|
|
rflags |= nval;
|
|
8013bce: 697b ldr r3, [r7, #20]
|
|
8013bd0: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8013bd2: 4313 orrs r3, r2
|
|
8013bd4: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
if ((options & osFlagsWaitAll) == osFlagsWaitAll) {
|
|
8013bd6: 68bb ldr r3, [r7, #8]
|
|
8013bd8: f003 0301 and.w r3, r3, #1
|
|
8013bdc: 2b00 cmp r3, #0
|
|
8013bde: d00c beq.n 8013bfa <osThreadFlagsWait+0x9e>
|
|
if ((flags & rflags) == flags) {
|
|
8013be0: 68fa ldr r2, [r7, #12]
|
|
8013be2: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8013be4: 4013 ands r3, r2
|
|
8013be6: 68fa ldr r2, [r7, #12]
|
|
8013be8: 429a cmp r2, r3
|
|
8013bea: d032 beq.n 8013c52 <osThreadFlagsWait+0xf6>
|
|
break;
|
|
} else {
|
|
if (timeout == 0U) {
|
|
8013bec: 687b ldr r3, [r7, #4]
|
|
8013bee: 2b00 cmp r3, #0
|
|
8013bf0: d10f bne.n 8013c12 <osThreadFlagsWait+0xb6>
|
|
rflags = (uint32_t)osErrorResource;
|
|
8013bf2: f06f 0302 mvn.w r3, #2
|
|
8013bf6: 62fb str r3, [r7, #44] @ 0x2c
|
|
break;
|
|
8013bf8: e02e b.n 8013c58 <osThreadFlagsWait+0xfc>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
if ((flags & rflags) != 0) {
|
|
8013bfa: 68fa ldr r2, [r7, #12]
|
|
8013bfc: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8013bfe: 4013 ands r3, r2
|
|
8013c00: 2b00 cmp r3, #0
|
|
8013c02: d128 bne.n 8013c56 <osThreadFlagsWait+0xfa>
|
|
break;
|
|
} else {
|
|
if (timeout == 0U) {
|
|
8013c04: 687b ldr r3, [r7, #4]
|
|
8013c06: 2b00 cmp r3, #0
|
|
8013c08: d103 bne.n 8013c12 <osThreadFlagsWait+0xb6>
|
|
rflags = (uint32_t)osErrorResource;
|
|
8013c0a: f06f 0302 mvn.w r3, #2
|
|
8013c0e: 62fb str r3, [r7, #44] @ 0x2c
|
|
break;
|
|
8013c10: e022 b.n 8013c58 <osThreadFlagsWait+0xfc>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update timeout */
|
|
td = xTaskGetTickCount() - t0;
|
|
8013c12: f002 f913 bl 8015e3c <xTaskGetTickCount>
|
|
8013c16: 4602 mov r2, r0
|
|
8013c18: 6a3b ldr r3, [r7, #32]
|
|
8013c1a: 1ad3 subs r3, r2, r3
|
|
8013c1c: 61bb str r3, [r7, #24]
|
|
|
|
if (td > timeout) {
|
|
8013c1e: 69ba ldr r2, [r7, #24]
|
|
8013c20: 687b ldr r3, [r7, #4]
|
|
8013c22: 429a cmp r2, r3
|
|
8013c24: d902 bls.n 8013c2c <osThreadFlagsWait+0xd0>
|
|
tout = 0;
|
|
8013c26: 2300 movs r3, #0
|
|
8013c28: 627b str r3, [r7, #36] @ 0x24
|
|
8013c2a: e00e b.n 8013c4a <osThreadFlagsWait+0xee>
|
|
} else {
|
|
tout = timeout - td;
|
|
8013c2c: 687a ldr r2, [r7, #4]
|
|
8013c2e: 69bb ldr r3, [r7, #24]
|
|
8013c30: 1ad3 subs r3, r2, r3
|
|
8013c32: 627b str r3, [r7, #36] @ 0x24
|
|
8013c34: e009 b.n 8013c4a <osThreadFlagsWait+0xee>
|
|
}
|
|
}
|
|
else {
|
|
if (timeout == 0) {
|
|
8013c36: 687b ldr r3, [r7, #4]
|
|
8013c38: 2b00 cmp r3, #0
|
|
8013c3a: d103 bne.n 8013c44 <osThreadFlagsWait+0xe8>
|
|
rflags = (uint32_t)osErrorResource;
|
|
8013c3c: f06f 0302 mvn.w r3, #2
|
|
8013c40: 62fb str r3, [r7, #44] @ 0x2c
|
|
8013c42: e002 b.n 8013c4a <osThreadFlagsWait+0xee>
|
|
} else {
|
|
rflags = (uint32_t)osErrorTimeout;
|
|
8013c44: f06f 0301 mvn.w r3, #1
|
|
8013c48: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
}
|
|
}
|
|
while (rval != pdFAIL);
|
|
8013c4a: 69fb ldr r3, [r7, #28]
|
|
8013c4c: 2b00 cmp r3, #0
|
|
8013c4e: d1ac bne.n 8013baa <osThreadFlagsWait+0x4e>
|
|
8013c50: e002 b.n 8013c58 <osThreadFlagsWait+0xfc>
|
|
break;
|
|
8013c52: bf00 nop
|
|
8013c54: e000 b.n 8013c58 <osThreadFlagsWait+0xfc>
|
|
break;
|
|
8013c56: bf00 nop
|
|
}
|
|
|
|
/* Return flags before clearing */
|
|
return (rflags);
|
|
8013c58: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
}
|
|
8013c5a: 4618 mov r0, r3
|
|
8013c5c: 3730 adds r7, #48 @ 0x30
|
|
8013c5e: 46bd mov sp, r7
|
|
8013c60: bd80 pop {r7, pc}
|
|
|
|
08013c62 <osMutexNew>:
|
|
|
|
Limitations:
|
|
- Priority inherit protocol is used by default, osMutexPrioInherit attribute is ignored.
|
|
- Robust mutex is not supported, NULL is returned if used.
|
|
*/
|
|
osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
|
|
8013c62: b580 push {r7, lr}
|
|
8013c64: b086 sub sp, #24
|
|
8013c66: af00 add r7, sp, #0
|
|
8013c68: 6078 str r0, [r7, #4]
|
|
SemaphoreHandle_t hMutex;
|
|
uint32_t type;
|
|
uint32_t rmtx;
|
|
int32_t mem;
|
|
|
|
hMutex = NULL;
|
|
8013c6a: 2300 movs r3, #0
|
|
8013c6c: 617b str r3, [r7, #20]
|
|
|
|
if (IRQ_Context() == 0U) {
|
|
8013c6e: f7ff fe0a bl 8013886 <IRQ_Context>
|
|
8013c72: 4603 mov r3, r0
|
|
8013c74: 2b00 cmp r3, #0
|
|
8013c76: d174 bne.n 8013d62 <osMutexNew+0x100>
|
|
if (attr != NULL) {
|
|
8013c78: 687b ldr r3, [r7, #4]
|
|
8013c7a: 2b00 cmp r3, #0
|
|
8013c7c: d003 beq.n 8013c86 <osMutexNew+0x24>
|
|
type = attr->attr_bits;
|
|
8013c7e: 687b ldr r3, [r7, #4]
|
|
8013c80: 685b ldr r3, [r3, #4]
|
|
8013c82: 613b str r3, [r7, #16]
|
|
8013c84: e001 b.n 8013c8a <osMutexNew+0x28>
|
|
} else {
|
|
type = 0U;
|
|
8013c86: 2300 movs r3, #0
|
|
8013c88: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
if ((type & osMutexRecursive) == osMutexRecursive) {
|
|
8013c8a: 693b ldr r3, [r7, #16]
|
|
8013c8c: f003 0301 and.w r3, r3, #1
|
|
8013c90: 2b00 cmp r3, #0
|
|
8013c92: d002 beq.n 8013c9a <osMutexNew+0x38>
|
|
rmtx = 1U;
|
|
8013c94: 2301 movs r3, #1
|
|
8013c96: 60fb str r3, [r7, #12]
|
|
8013c98: e001 b.n 8013c9e <osMutexNew+0x3c>
|
|
} else {
|
|
rmtx = 0U;
|
|
8013c9a: 2300 movs r3, #0
|
|
8013c9c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if ((type & osMutexRobust) != osMutexRobust) {
|
|
8013c9e: 693b ldr r3, [r7, #16]
|
|
8013ca0: f003 0308 and.w r3, r3, #8
|
|
8013ca4: 2b00 cmp r3, #0
|
|
8013ca6: d15c bne.n 8013d62 <osMutexNew+0x100>
|
|
mem = -1;
|
|
8013ca8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8013cac: 60bb str r3, [r7, #8]
|
|
|
|
if (attr != NULL) {
|
|
8013cae: 687b ldr r3, [r7, #4]
|
|
8013cb0: 2b00 cmp r3, #0
|
|
8013cb2: d015 beq.n 8013ce0 <osMutexNew+0x7e>
|
|
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
|
|
8013cb4: 687b ldr r3, [r7, #4]
|
|
8013cb6: 689b ldr r3, [r3, #8]
|
|
8013cb8: 2b00 cmp r3, #0
|
|
8013cba: d006 beq.n 8013cca <osMutexNew+0x68>
|
|
8013cbc: 687b ldr r3, [r7, #4]
|
|
8013cbe: 68db ldr r3, [r3, #12]
|
|
8013cc0: 2b4f cmp r3, #79 @ 0x4f
|
|
8013cc2: d902 bls.n 8013cca <osMutexNew+0x68>
|
|
/* The memory for control block is provided, use static object */
|
|
mem = 1;
|
|
8013cc4: 2301 movs r3, #1
|
|
8013cc6: 60bb str r3, [r7, #8]
|
|
8013cc8: e00c b.n 8013ce4 <osMutexNew+0x82>
|
|
}
|
|
else {
|
|
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
|
|
8013cca: 687b ldr r3, [r7, #4]
|
|
8013ccc: 689b ldr r3, [r3, #8]
|
|
8013cce: 2b00 cmp r3, #0
|
|
8013cd0: d108 bne.n 8013ce4 <osMutexNew+0x82>
|
|
8013cd2: 687b ldr r3, [r7, #4]
|
|
8013cd4: 68db ldr r3, [r3, #12]
|
|
8013cd6: 2b00 cmp r3, #0
|
|
8013cd8: d104 bne.n 8013ce4 <osMutexNew+0x82>
|
|
/* Control block will be allocated from the dynamic pool */
|
|
mem = 0;
|
|
8013cda: 2300 movs r3, #0
|
|
8013cdc: 60bb str r3, [r7, #8]
|
|
8013cde: e001 b.n 8013ce4 <osMutexNew+0x82>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
mem = 0;
|
|
8013ce0: 2300 movs r3, #0
|
|
8013ce2: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
if (mem == 1) {
|
|
8013ce4: 68bb ldr r3, [r7, #8]
|
|
8013ce6: 2b01 cmp r3, #1
|
|
8013ce8: d112 bne.n 8013d10 <osMutexNew+0xae>
|
|
#if (configSUPPORT_STATIC_ALLOCATION == 1)
|
|
if (rmtx != 0U) {
|
|
8013cea: 68fb ldr r3, [r7, #12]
|
|
8013cec: 2b00 cmp r3, #0
|
|
8013cee: d007 beq.n 8013d00 <osMutexNew+0x9e>
|
|
#if (configUSE_RECURSIVE_MUTEXES == 1)
|
|
hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);
|
|
8013cf0: 687b ldr r3, [r7, #4]
|
|
8013cf2: 689b ldr r3, [r3, #8]
|
|
8013cf4: 4619 mov r1, r3
|
|
8013cf6: 2004 movs r0, #4
|
|
8013cf8: f000 fd63 bl 80147c2 <xQueueCreateMutexStatic>
|
|
8013cfc: 6178 str r0, [r7, #20]
|
|
8013cfe: e016 b.n 8013d2e <osMutexNew+0xcc>
|
|
#endif
|
|
}
|
|
else {
|
|
hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);
|
|
8013d00: 687b ldr r3, [r7, #4]
|
|
8013d02: 689b ldr r3, [r3, #8]
|
|
8013d04: 4619 mov r1, r3
|
|
8013d06: 2001 movs r0, #1
|
|
8013d08: f000 fd5b bl 80147c2 <xQueueCreateMutexStatic>
|
|
8013d0c: 6178 str r0, [r7, #20]
|
|
8013d0e: e00e b.n 8013d2e <osMutexNew+0xcc>
|
|
}
|
|
#endif
|
|
}
|
|
else {
|
|
if (mem == 0) {
|
|
8013d10: 68bb ldr r3, [r7, #8]
|
|
8013d12: 2b00 cmp r3, #0
|
|
8013d14: d10b bne.n 8013d2e <osMutexNew+0xcc>
|
|
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
|
|
if (rmtx != 0U) {
|
|
8013d16: 68fb ldr r3, [r7, #12]
|
|
8013d18: 2b00 cmp r3, #0
|
|
8013d1a: d004 beq.n 8013d26 <osMutexNew+0xc4>
|
|
#if (configUSE_RECURSIVE_MUTEXES == 1)
|
|
hMutex = xSemaphoreCreateRecursiveMutex ();
|
|
8013d1c: 2004 movs r0, #4
|
|
8013d1e: f000 fd38 bl 8014792 <xQueueCreateMutex>
|
|
8013d22: 6178 str r0, [r7, #20]
|
|
8013d24: e003 b.n 8013d2e <osMutexNew+0xcc>
|
|
#endif
|
|
} else {
|
|
hMutex = xSemaphoreCreateMutex ();
|
|
8013d26: 2001 movs r0, #1
|
|
8013d28: f000 fd33 bl 8014792 <xQueueCreateMutex>
|
|
8013d2c: 6178 str r0, [r7, #20]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
#if (configQUEUE_REGISTRY_SIZE > 0)
|
|
if (hMutex != NULL) {
|
|
8013d2e: 697b ldr r3, [r7, #20]
|
|
8013d30: 2b00 cmp r3, #0
|
|
8013d32: d00c beq.n 8013d4e <osMutexNew+0xec>
|
|
if ((attr != NULL) && (attr->name != NULL)) {
|
|
8013d34: 687b ldr r3, [r7, #4]
|
|
8013d36: 2b00 cmp r3, #0
|
|
8013d38: d009 beq.n 8013d4e <osMutexNew+0xec>
|
|
8013d3a: 687b ldr r3, [r7, #4]
|
|
8013d3c: 681b ldr r3, [r3, #0]
|
|
8013d3e: 2b00 cmp r3, #0
|
|
8013d40: d005 beq.n 8013d4e <osMutexNew+0xec>
|
|
/* Only non-NULL name objects are added to the Queue Registry */
|
|
vQueueAddToRegistry (hMutex, attr->name);
|
|
8013d42: 687b ldr r3, [r7, #4]
|
|
8013d44: 681b ldr r3, [r3, #0]
|
|
8013d46: 4619 mov r1, r3
|
|
8013d48: 6978 ldr r0, [r7, #20]
|
|
8013d4a: f001 fc4b bl 80155e4 <vQueueAddToRegistry>
|
|
}
|
|
}
|
|
#endif
|
|
|
|
if ((hMutex != NULL) && (rmtx != 0U)) {
|
|
8013d4e: 697b ldr r3, [r7, #20]
|
|
8013d50: 2b00 cmp r3, #0
|
|
8013d52: d006 beq.n 8013d62 <osMutexNew+0x100>
|
|
8013d54: 68fb ldr r3, [r7, #12]
|
|
8013d56: 2b00 cmp r3, #0
|
|
8013d58: d003 beq.n 8013d62 <osMutexNew+0x100>
|
|
/* Set LSB as 'recursive mutex flag' */
|
|
hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);
|
|
8013d5a: 697b ldr r3, [r7, #20]
|
|
8013d5c: f043 0301 orr.w r3, r3, #1
|
|
8013d60: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return mutex ID */
|
|
return ((osMutexId_t)hMutex);
|
|
8013d62: 697b ldr r3, [r7, #20]
|
|
}
|
|
8013d64: 4618 mov r0, r3
|
|
8013d66: 3718 adds r7, #24
|
|
8013d68: 46bd mov sp, r7
|
|
8013d6a: bd80 pop {r7, pc}
|
|
|
|
08013d6c <osMutexAcquire>:
|
|
|
|
/*
|
|
Acquire a Mutex or timeout if it is locked.
|
|
*/
|
|
osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
|
|
8013d6c: b580 push {r7, lr}
|
|
8013d6e: b086 sub sp, #24
|
|
8013d70: af00 add r7, sp, #0
|
|
8013d72: 6078 str r0, [r7, #4]
|
|
8013d74: 6039 str r1, [r7, #0]
|
|
SemaphoreHandle_t hMutex;
|
|
osStatus_t stat;
|
|
uint32_t rmtx;
|
|
|
|
hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
|
|
8013d76: 687b ldr r3, [r7, #4]
|
|
8013d78: f023 0301 bic.w r3, r3, #1
|
|
8013d7c: 613b str r3, [r7, #16]
|
|
|
|
/* Extract recursive mutex flag */
|
|
rmtx = (uint32_t)mutex_id & 1U;
|
|
8013d7e: 687b ldr r3, [r7, #4]
|
|
8013d80: f003 0301 and.w r3, r3, #1
|
|
8013d84: 60fb str r3, [r7, #12]
|
|
|
|
stat = osOK;
|
|
8013d86: 2300 movs r3, #0
|
|
8013d88: 617b str r3, [r7, #20]
|
|
|
|
if (IRQ_Context() != 0U) {
|
|
8013d8a: f7ff fd7c bl 8013886 <IRQ_Context>
|
|
8013d8e: 4603 mov r3, r0
|
|
8013d90: 2b00 cmp r3, #0
|
|
8013d92: d003 beq.n 8013d9c <osMutexAcquire+0x30>
|
|
stat = osErrorISR;
|
|
8013d94: f06f 0305 mvn.w r3, #5
|
|
8013d98: 617b str r3, [r7, #20]
|
|
8013d9a: e02c b.n 8013df6 <osMutexAcquire+0x8a>
|
|
}
|
|
else if (hMutex == NULL) {
|
|
8013d9c: 693b ldr r3, [r7, #16]
|
|
8013d9e: 2b00 cmp r3, #0
|
|
8013da0: d103 bne.n 8013daa <osMutexAcquire+0x3e>
|
|
stat = osErrorParameter;
|
|
8013da2: f06f 0303 mvn.w r3, #3
|
|
8013da6: 617b str r3, [r7, #20]
|
|
8013da8: e025 b.n 8013df6 <osMutexAcquire+0x8a>
|
|
}
|
|
else {
|
|
if (rmtx != 0U) {
|
|
8013daa: 68fb ldr r3, [r7, #12]
|
|
8013dac: 2b00 cmp r3, #0
|
|
8013dae: d011 beq.n 8013dd4 <osMutexAcquire+0x68>
|
|
#if (configUSE_RECURSIVE_MUTEXES == 1)
|
|
if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {
|
|
8013db0: 6839 ldr r1, [r7, #0]
|
|
8013db2: 6938 ldr r0, [r7, #16]
|
|
8013db4: f000 fd55 bl 8014862 <xQueueTakeMutexRecursive>
|
|
8013db8: 4603 mov r3, r0
|
|
8013dba: 2b01 cmp r3, #1
|
|
8013dbc: d01b beq.n 8013df6 <osMutexAcquire+0x8a>
|
|
if (timeout != 0U) {
|
|
8013dbe: 683b ldr r3, [r7, #0]
|
|
8013dc0: 2b00 cmp r3, #0
|
|
8013dc2: d003 beq.n 8013dcc <osMutexAcquire+0x60>
|
|
stat = osErrorTimeout;
|
|
8013dc4: f06f 0301 mvn.w r3, #1
|
|
8013dc8: 617b str r3, [r7, #20]
|
|
8013dca: e014 b.n 8013df6 <osMutexAcquire+0x8a>
|
|
} else {
|
|
stat = osErrorResource;
|
|
8013dcc: f06f 0302 mvn.w r3, #2
|
|
8013dd0: 617b str r3, [r7, #20]
|
|
8013dd2: e010 b.n 8013df6 <osMutexAcquire+0x8a>
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
else {
|
|
if (xSemaphoreTake (hMutex, timeout) != pdPASS) {
|
|
8013dd4: 6839 ldr r1, [r7, #0]
|
|
8013dd6: 6938 ldr r0, [r7, #16]
|
|
8013dd8: f001 f91e bl 8015018 <xQueueSemaphoreTake>
|
|
8013ddc: 4603 mov r3, r0
|
|
8013dde: 2b01 cmp r3, #1
|
|
8013de0: d009 beq.n 8013df6 <osMutexAcquire+0x8a>
|
|
if (timeout != 0U) {
|
|
8013de2: 683b ldr r3, [r7, #0]
|
|
8013de4: 2b00 cmp r3, #0
|
|
8013de6: d003 beq.n 8013df0 <osMutexAcquire+0x84>
|
|
stat = osErrorTimeout;
|
|
8013de8: f06f 0301 mvn.w r3, #1
|
|
8013dec: 617b str r3, [r7, #20]
|
|
8013dee: e002 b.n 8013df6 <osMutexAcquire+0x8a>
|
|
} else {
|
|
stat = osErrorResource;
|
|
8013df0: f06f 0302 mvn.w r3, #2
|
|
8013df4: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return execution status */
|
|
return (stat);
|
|
8013df6: 697b ldr r3, [r7, #20]
|
|
}
|
|
8013df8: 4618 mov r0, r3
|
|
8013dfa: 3718 adds r7, #24
|
|
8013dfc: 46bd mov sp, r7
|
|
8013dfe: bd80 pop {r7, pc}
|
|
|
|
08013e00 <osMutexRelease>:
|
|
|
|
/*
|
|
Release a Mutex that was acquired by osMutexAcquire.
|
|
*/
|
|
osStatus_t osMutexRelease (osMutexId_t mutex_id) {
|
|
8013e00: b580 push {r7, lr}
|
|
8013e02: b086 sub sp, #24
|
|
8013e04: af00 add r7, sp, #0
|
|
8013e06: 6078 str r0, [r7, #4]
|
|
SemaphoreHandle_t hMutex;
|
|
osStatus_t stat;
|
|
uint32_t rmtx;
|
|
|
|
hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
|
|
8013e08: 687b ldr r3, [r7, #4]
|
|
8013e0a: f023 0301 bic.w r3, r3, #1
|
|
8013e0e: 613b str r3, [r7, #16]
|
|
|
|
/* Extract recursive mutex flag */
|
|
rmtx = (uint32_t)mutex_id & 1U;
|
|
8013e10: 687b ldr r3, [r7, #4]
|
|
8013e12: f003 0301 and.w r3, r3, #1
|
|
8013e16: 60fb str r3, [r7, #12]
|
|
|
|
stat = osOK;
|
|
8013e18: 2300 movs r3, #0
|
|
8013e1a: 617b str r3, [r7, #20]
|
|
|
|
if (IRQ_Context() != 0U) {
|
|
8013e1c: f7ff fd33 bl 8013886 <IRQ_Context>
|
|
8013e20: 4603 mov r3, r0
|
|
8013e22: 2b00 cmp r3, #0
|
|
8013e24: d003 beq.n 8013e2e <osMutexRelease+0x2e>
|
|
stat = osErrorISR;
|
|
8013e26: f06f 0305 mvn.w r3, #5
|
|
8013e2a: 617b str r3, [r7, #20]
|
|
8013e2c: e01f b.n 8013e6e <osMutexRelease+0x6e>
|
|
}
|
|
else if (hMutex == NULL) {
|
|
8013e2e: 693b ldr r3, [r7, #16]
|
|
8013e30: 2b00 cmp r3, #0
|
|
8013e32: d103 bne.n 8013e3c <osMutexRelease+0x3c>
|
|
stat = osErrorParameter;
|
|
8013e34: f06f 0303 mvn.w r3, #3
|
|
8013e38: 617b str r3, [r7, #20]
|
|
8013e3a: e018 b.n 8013e6e <osMutexRelease+0x6e>
|
|
}
|
|
else {
|
|
if (rmtx != 0U) {
|
|
8013e3c: 68fb ldr r3, [r7, #12]
|
|
8013e3e: 2b00 cmp r3, #0
|
|
8013e40: d009 beq.n 8013e56 <osMutexRelease+0x56>
|
|
#if (configUSE_RECURSIVE_MUTEXES == 1)
|
|
if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {
|
|
8013e42: 6938 ldr r0, [r7, #16]
|
|
8013e44: f000 fcd8 bl 80147f8 <xQueueGiveMutexRecursive>
|
|
8013e48: 4603 mov r3, r0
|
|
8013e4a: 2b01 cmp r3, #1
|
|
8013e4c: d00f beq.n 8013e6e <osMutexRelease+0x6e>
|
|
stat = osErrorResource;
|
|
8013e4e: f06f 0302 mvn.w r3, #2
|
|
8013e52: 617b str r3, [r7, #20]
|
|
8013e54: e00b b.n 8013e6e <osMutexRelease+0x6e>
|
|
}
|
|
#endif
|
|
}
|
|
else {
|
|
if (xSemaphoreGive (hMutex) != pdPASS) {
|
|
8013e56: 2300 movs r3, #0
|
|
8013e58: 2200 movs r2, #0
|
|
8013e5a: 2100 movs r1, #0
|
|
8013e5c: 6938 ldr r0, [r7, #16]
|
|
8013e5e: f000 fd99 bl 8014994 <xQueueGenericSend>
|
|
8013e62: 4603 mov r3, r0
|
|
8013e64: 2b01 cmp r3, #1
|
|
8013e66: d002 beq.n 8013e6e <osMutexRelease+0x6e>
|
|
stat = osErrorResource;
|
|
8013e68: f06f 0302 mvn.w r3, #2
|
|
8013e6c: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return execution status */
|
|
return (stat);
|
|
8013e6e: 697b ldr r3, [r7, #20]
|
|
}
|
|
8013e70: 4618 mov r0, r3
|
|
8013e72: 3718 adds r7, #24
|
|
8013e74: 46bd mov sp, r7
|
|
8013e76: bd80 pop {r7, pc}
|
|
|
|
08013e78 <osSemaphoreNew>:
|
|
/* ==== Semaphore Management Functions ==== */
|
|
|
|
/*
|
|
Create and Initialize a Semaphore object.
|
|
*/
|
|
osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
|
|
8013e78: b580 push {r7, lr}
|
|
8013e7a: b088 sub sp, #32
|
|
8013e7c: af02 add r7, sp, #8
|
|
8013e7e: 60f8 str r0, [r7, #12]
|
|
8013e80: 60b9 str r1, [r7, #8]
|
|
8013e82: 607a str r2, [r7, #4]
|
|
SemaphoreHandle_t hSemaphore;
|
|
int32_t mem;
|
|
|
|
hSemaphore = NULL;
|
|
8013e84: 2300 movs r3, #0
|
|
8013e86: 617b str r3, [r7, #20]
|
|
|
|
if ((IRQ_Context() == 0U) && (max_count > 0U) && (initial_count <= max_count)) {
|
|
8013e88: f7ff fcfd bl 8013886 <IRQ_Context>
|
|
8013e8c: 4603 mov r3, r0
|
|
8013e8e: 2b00 cmp r3, #0
|
|
8013e90: d175 bne.n 8013f7e <osSemaphoreNew+0x106>
|
|
8013e92: 68fb ldr r3, [r7, #12]
|
|
8013e94: 2b00 cmp r3, #0
|
|
8013e96: d072 beq.n 8013f7e <osSemaphoreNew+0x106>
|
|
8013e98: 68ba ldr r2, [r7, #8]
|
|
8013e9a: 68fb ldr r3, [r7, #12]
|
|
8013e9c: 429a cmp r2, r3
|
|
8013e9e: d86e bhi.n 8013f7e <osSemaphoreNew+0x106>
|
|
mem = -1;
|
|
8013ea0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8013ea4: 613b str r3, [r7, #16]
|
|
|
|
if (attr != NULL) {
|
|
8013ea6: 687b ldr r3, [r7, #4]
|
|
8013ea8: 2b00 cmp r3, #0
|
|
8013eaa: d015 beq.n 8013ed8 <osSemaphoreNew+0x60>
|
|
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
|
|
8013eac: 687b ldr r3, [r7, #4]
|
|
8013eae: 689b ldr r3, [r3, #8]
|
|
8013eb0: 2b00 cmp r3, #0
|
|
8013eb2: d006 beq.n 8013ec2 <osSemaphoreNew+0x4a>
|
|
8013eb4: 687b ldr r3, [r7, #4]
|
|
8013eb6: 68db ldr r3, [r3, #12]
|
|
8013eb8: 2b4f cmp r3, #79 @ 0x4f
|
|
8013eba: d902 bls.n 8013ec2 <osSemaphoreNew+0x4a>
|
|
/* The memory for control block is provided, use static object */
|
|
mem = 1;
|
|
8013ebc: 2301 movs r3, #1
|
|
8013ebe: 613b str r3, [r7, #16]
|
|
8013ec0: e00c b.n 8013edc <osSemaphoreNew+0x64>
|
|
}
|
|
else {
|
|
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
|
|
8013ec2: 687b ldr r3, [r7, #4]
|
|
8013ec4: 689b ldr r3, [r3, #8]
|
|
8013ec6: 2b00 cmp r3, #0
|
|
8013ec8: d108 bne.n 8013edc <osSemaphoreNew+0x64>
|
|
8013eca: 687b ldr r3, [r7, #4]
|
|
8013ecc: 68db ldr r3, [r3, #12]
|
|
8013ece: 2b00 cmp r3, #0
|
|
8013ed0: d104 bne.n 8013edc <osSemaphoreNew+0x64>
|
|
/* Control block will be allocated from the dynamic pool */
|
|
mem = 0;
|
|
8013ed2: 2300 movs r3, #0
|
|
8013ed4: 613b str r3, [r7, #16]
|
|
8013ed6: e001 b.n 8013edc <osSemaphoreNew+0x64>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
mem = 0;
|
|
8013ed8: 2300 movs r3, #0
|
|
8013eda: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
if (mem != -1) {
|
|
8013edc: 693b ldr r3, [r7, #16]
|
|
8013ede: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8013ee2: d04c beq.n 8013f7e <osSemaphoreNew+0x106>
|
|
if (max_count == 1U) {
|
|
8013ee4: 68fb ldr r3, [r7, #12]
|
|
8013ee6: 2b01 cmp r3, #1
|
|
8013ee8: d128 bne.n 8013f3c <osSemaphoreNew+0xc4>
|
|
if (mem == 1) {
|
|
8013eea: 693b ldr r3, [r7, #16]
|
|
8013eec: 2b01 cmp r3, #1
|
|
8013eee: d10a bne.n 8013f06 <osSemaphoreNew+0x8e>
|
|
#if (configSUPPORT_STATIC_ALLOCATION == 1)
|
|
hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem);
|
|
8013ef0: 687b ldr r3, [r7, #4]
|
|
8013ef2: 689b ldr r3, [r3, #8]
|
|
8013ef4: 2203 movs r2, #3
|
|
8013ef6: 9200 str r2, [sp, #0]
|
|
8013ef8: 2200 movs r2, #0
|
|
8013efa: 2100 movs r1, #0
|
|
8013efc: 2001 movs r0, #1
|
|
8013efe: f000 fb57 bl 80145b0 <xQueueGenericCreateStatic>
|
|
8013f02: 6178 str r0, [r7, #20]
|
|
8013f04: e005 b.n 8013f12 <osSemaphoreNew+0x9a>
|
|
#endif
|
|
}
|
|
else {
|
|
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
|
|
hSemaphore = xSemaphoreCreateBinary();
|
|
8013f06: 2203 movs r2, #3
|
|
8013f08: 2100 movs r1, #0
|
|
8013f0a: 2001 movs r0, #1
|
|
8013f0c: f000 fbb1 bl 8014672 <xQueueGenericCreate>
|
|
8013f10: 6178 str r0, [r7, #20]
|
|
#endif
|
|
}
|
|
|
|
if ((hSemaphore != NULL) && (initial_count != 0U)) {
|
|
8013f12: 697b ldr r3, [r7, #20]
|
|
8013f14: 2b00 cmp r3, #0
|
|
8013f16: d022 beq.n 8013f5e <osSemaphoreNew+0xe6>
|
|
8013f18: 68bb ldr r3, [r7, #8]
|
|
8013f1a: 2b00 cmp r3, #0
|
|
8013f1c: d01f beq.n 8013f5e <osSemaphoreNew+0xe6>
|
|
if (xSemaphoreGive (hSemaphore) != pdPASS) {
|
|
8013f1e: 2300 movs r3, #0
|
|
8013f20: 2200 movs r2, #0
|
|
8013f22: 2100 movs r1, #0
|
|
8013f24: 6978 ldr r0, [r7, #20]
|
|
8013f26: f000 fd35 bl 8014994 <xQueueGenericSend>
|
|
8013f2a: 4603 mov r3, r0
|
|
8013f2c: 2b01 cmp r3, #1
|
|
8013f2e: d016 beq.n 8013f5e <osSemaphoreNew+0xe6>
|
|
vSemaphoreDelete (hSemaphore);
|
|
8013f30: 6978 ldr r0, [r7, #20]
|
|
8013f32: f001 fa0b bl 801534c <vQueueDelete>
|
|
hSemaphore = NULL;
|
|
8013f36: 2300 movs r3, #0
|
|
8013f38: 617b str r3, [r7, #20]
|
|
8013f3a: e010 b.n 8013f5e <osSemaphoreNew+0xe6>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
if (mem == 1) {
|
|
8013f3c: 693b ldr r3, [r7, #16]
|
|
8013f3e: 2b01 cmp r3, #1
|
|
8013f40: d108 bne.n 8013f54 <osSemaphoreNew+0xdc>
|
|
#if (configSUPPORT_STATIC_ALLOCATION == 1)
|
|
hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem);
|
|
8013f42: 687b ldr r3, [r7, #4]
|
|
8013f44: 689b ldr r3, [r3, #8]
|
|
8013f46: 461a mov r2, r3
|
|
8013f48: 68b9 ldr r1, [r7, #8]
|
|
8013f4a: 68f8 ldr r0, [r7, #12]
|
|
8013f4c: f000 fcc0 bl 80148d0 <xQueueCreateCountingSemaphoreStatic>
|
|
8013f50: 6178 str r0, [r7, #20]
|
|
8013f52: e004 b.n 8013f5e <osSemaphoreNew+0xe6>
|
|
#endif
|
|
}
|
|
else {
|
|
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
|
|
hSemaphore = xSemaphoreCreateCounting (max_count, initial_count);
|
|
8013f54: 68b9 ldr r1, [r7, #8]
|
|
8013f56: 68f8 ldr r0, [r7, #12]
|
|
8013f58: f000 fced bl 8014936 <xQueueCreateCountingSemaphore>
|
|
8013f5c: 6178 str r0, [r7, #20]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
#if (configQUEUE_REGISTRY_SIZE > 0)
|
|
if (hSemaphore != NULL) {
|
|
8013f5e: 697b ldr r3, [r7, #20]
|
|
8013f60: 2b00 cmp r3, #0
|
|
8013f62: d00c beq.n 8013f7e <osSemaphoreNew+0x106>
|
|
if ((attr != NULL) && (attr->name != NULL)) {
|
|
8013f64: 687b ldr r3, [r7, #4]
|
|
8013f66: 2b00 cmp r3, #0
|
|
8013f68: d009 beq.n 8013f7e <osSemaphoreNew+0x106>
|
|
8013f6a: 687b ldr r3, [r7, #4]
|
|
8013f6c: 681b ldr r3, [r3, #0]
|
|
8013f6e: 2b00 cmp r3, #0
|
|
8013f70: d005 beq.n 8013f7e <osSemaphoreNew+0x106>
|
|
/* Only non-NULL name objects are added to the Queue Registry */
|
|
vQueueAddToRegistry (hSemaphore, attr->name);
|
|
8013f72: 687b ldr r3, [r7, #4]
|
|
8013f74: 681b ldr r3, [r3, #0]
|
|
8013f76: 4619 mov r1, r3
|
|
8013f78: 6978 ldr r0, [r7, #20]
|
|
8013f7a: f001 fb33 bl 80155e4 <vQueueAddToRegistry>
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/* Return semaphore ID */
|
|
return ((osSemaphoreId_t)hSemaphore);
|
|
8013f7e: 697b ldr r3, [r7, #20]
|
|
}
|
|
8013f80: 4618 mov r0, r3
|
|
8013f82: 3718 adds r7, #24
|
|
8013f84: 46bd mov sp, r7
|
|
8013f86: bd80 pop {r7, pc}
|
|
|
|
08013f88 <osSemaphoreAcquire>:
|
|
|
|
/*
|
|
Acquire a Semaphore token or timeout if no tokens are available.
|
|
*/
|
|
osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
|
|
8013f88: b580 push {r7, lr}
|
|
8013f8a: b086 sub sp, #24
|
|
8013f8c: af00 add r7, sp, #0
|
|
8013f8e: 6078 str r0, [r7, #4]
|
|
8013f90: 6039 str r1, [r7, #0]
|
|
SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
|
|
8013f92: 687b ldr r3, [r7, #4]
|
|
8013f94: 613b str r3, [r7, #16]
|
|
osStatus_t stat;
|
|
BaseType_t yield;
|
|
|
|
stat = osOK;
|
|
8013f96: 2300 movs r3, #0
|
|
8013f98: 617b str r3, [r7, #20]
|
|
|
|
if (hSemaphore == NULL) {
|
|
8013f9a: 693b ldr r3, [r7, #16]
|
|
8013f9c: 2b00 cmp r3, #0
|
|
8013f9e: d103 bne.n 8013fa8 <osSemaphoreAcquire+0x20>
|
|
stat = osErrorParameter;
|
|
8013fa0: f06f 0303 mvn.w r3, #3
|
|
8013fa4: 617b str r3, [r7, #20]
|
|
8013fa6: e038 b.n 801401a <osSemaphoreAcquire+0x92>
|
|
}
|
|
else if (IRQ_Context() != 0U) {
|
|
8013fa8: f7ff fc6d bl 8013886 <IRQ_Context>
|
|
8013fac: 4603 mov r3, r0
|
|
8013fae: 2b00 cmp r3, #0
|
|
8013fb0: d022 beq.n 8013ff8 <osSemaphoreAcquire+0x70>
|
|
if (timeout != 0U) {
|
|
8013fb2: 683b ldr r3, [r7, #0]
|
|
8013fb4: 2b00 cmp r3, #0
|
|
8013fb6: d003 beq.n 8013fc0 <osSemaphoreAcquire+0x38>
|
|
stat = osErrorParameter;
|
|
8013fb8: f06f 0303 mvn.w r3, #3
|
|
8013fbc: 617b str r3, [r7, #20]
|
|
8013fbe: e02c b.n 801401a <osSemaphoreAcquire+0x92>
|
|
}
|
|
else {
|
|
yield = pdFALSE;
|
|
8013fc0: 2300 movs r3, #0
|
|
8013fc2: 60fb str r3, [r7, #12]
|
|
|
|
if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) {
|
|
8013fc4: f107 030c add.w r3, r7, #12
|
|
8013fc8: 461a mov r2, r3
|
|
8013fca: 2100 movs r1, #0
|
|
8013fcc: 6938 ldr r0, [r7, #16]
|
|
8013fce: f001 f923 bl 8015218 <xQueueReceiveFromISR>
|
|
8013fd2: 4603 mov r3, r0
|
|
8013fd4: 2b01 cmp r3, #1
|
|
8013fd6: d003 beq.n 8013fe0 <osSemaphoreAcquire+0x58>
|
|
stat = osErrorResource;
|
|
8013fd8: f06f 0302 mvn.w r3, #2
|
|
8013fdc: 617b str r3, [r7, #20]
|
|
8013fde: e01c b.n 801401a <osSemaphoreAcquire+0x92>
|
|
} else {
|
|
portYIELD_FROM_ISR (yield);
|
|
8013fe0: 68fb ldr r3, [r7, #12]
|
|
8013fe2: 2b00 cmp r3, #0
|
|
8013fe4: d019 beq.n 801401a <osSemaphoreAcquire+0x92>
|
|
8013fe6: 4b0f ldr r3, [pc, #60] @ (8014024 <osSemaphoreAcquire+0x9c>)
|
|
8013fe8: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8013fec: 601a str r2, [r3, #0]
|
|
8013fee: f3bf 8f4f dsb sy
|
|
8013ff2: f3bf 8f6f isb sy
|
|
8013ff6: e010 b.n 801401a <osSemaphoreAcquire+0x92>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) {
|
|
8013ff8: 6839 ldr r1, [r7, #0]
|
|
8013ffa: 6938 ldr r0, [r7, #16]
|
|
8013ffc: f001 f80c bl 8015018 <xQueueSemaphoreTake>
|
|
8014000: 4603 mov r3, r0
|
|
8014002: 2b01 cmp r3, #1
|
|
8014004: d009 beq.n 801401a <osSemaphoreAcquire+0x92>
|
|
if (timeout != 0U) {
|
|
8014006: 683b ldr r3, [r7, #0]
|
|
8014008: 2b00 cmp r3, #0
|
|
801400a: d003 beq.n 8014014 <osSemaphoreAcquire+0x8c>
|
|
stat = osErrorTimeout;
|
|
801400c: f06f 0301 mvn.w r3, #1
|
|
8014010: 617b str r3, [r7, #20]
|
|
8014012: e002 b.n 801401a <osSemaphoreAcquire+0x92>
|
|
} else {
|
|
stat = osErrorResource;
|
|
8014014: f06f 0302 mvn.w r3, #2
|
|
8014018: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return execution status */
|
|
return (stat);
|
|
801401a: 697b ldr r3, [r7, #20]
|
|
}
|
|
801401c: 4618 mov r0, r3
|
|
801401e: 3718 adds r7, #24
|
|
8014020: 46bd mov sp, r7
|
|
8014022: bd80 pop {r7, pc}
|
|
8014024: e000ed04 .word 0xe000ed04
|
|
|
|
08014028 <osSemaphoreRelease>:
|
|
|
|
/*
|
|
Release a Semaphore token up to the initial maximum count.
|
|
*/
|
|
osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {
|
|
8014028: b580 push {r7, lr}
|
|
801402a: b086 sub sp, #24
|
|
801402c: af00 add r7, sp, #0
|
|
801402e: 6078 str r0, [r7, #4]
|
|
SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
|
|
8014030: 687b ldr r3, [r7, #4]
|
|
8014032: 613b str r3, [r7, #16]
|
|
osStatus_t stat;
|
|
BaseType_t yield;
|
|
|
|
stat = osOK;
|
|
8014034: 2300 movs r3, #0
|
|
8014036: 617b str r3, [r7, #20]
|
|
|
|
if (hSemaphore == NULL) {
|
|
8014038: 693b ldr r3, [r7, #16]
|
|
801403a: 2b00 cmp r3, #0
|
|
801403c: d103 bne.n 8014046 <osSemaphoreRelease+0x1e>
|
|
stat = osErrorParameter;
|
|
801403e: f06f 0303 mvn.w r3, #3
|
|
8014042: 617b str r3, [r7, #20]
|
|
8014044: e02b b.n 801409e <osSemaphoreRelease+0x76>
|
|
}
|
|
else if (IRQ_Context() != 0U) {
|
|
8014046: f7ff fc1e bl 8013886 <IRQ_Context>
|
|
801404a: 4603 mov r3, r0
|
|
801404c: 2b00 cmp r3, #0
|
|
801404e: d01a beq.n 8014086 <osSemaphoreRelease+0x5e>
|
|
yield = pdFALSE;
|
|
8014050: 2300 movs r3, #0
|
|
8014052: 60fb str r3, [r7, #12]
|
|
|
|
if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) {
|
|
8014054: f107 030c add.w r3, r7, #12
|
|
8014058: 4619 mov r1, r3
|
|
801405a: 6938 ldr r0, [r7, #16]
|
|
801405c: f000 fe52 bl 8014d04 <xQueueGiveFromISR>
|
|
8014060: 4603 mov r3, r0
|
|
8014062: 2b01 cmp r3, #1
|
|
8014064: d003 beq.n 801406e <osSemaphoreRelease+0x46>
|
|
stat = osErrorResource;
|
|
8014066: f06f 0302 mvn.w r3, #2
|
|
801406a: 617b str r3, [r7, #20]
|
|
801406c: e017 b.n 801409e <osSemaphoreRelease+0x76>
|
|
} else {
|
|
portYIELD_FROM_ISR (yield);
|
|
801406e: 68fb ldr r3, [r7, #12]
|
|
8014070: 2b00 cmp r3, #0
|
|
8014072: d014 beq.n 801409e <osSemaphoreRelease+0x76>
|
|
8014074: 4b0c ldr r3, [pc, #48] @ (80140a8 <osSemaphoreRelease+0x80>)
|
|
8014076: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
801407a: 601a str r2, [r3, #0]
|
|
801407c: f3bf 8f4f dsb sy
|
|
8014080: f3bf 8f6f isb sy
|
|
8014084: e00b b.n 801409e <osSemaphoreRelease+0x76>
|
|
}
|
|
}
|
|
else {
|
|
if (xSemaphoreGive (hSemaphore) != pdPASS) {
|
|
8014086: 2300 movs r3, #0
|
|
8014088: 2200 movs r2, #0
|
|
801408a: 2100 movs r1, #0
|
|
801408c: 6938 ldr r0, [r7, #16]
|
|
801408e: f000 fc81 bl 8014994 <xQueueGenericSend>
|
|
8014092: 4603 mov r3, r0
|
|
8014094: 2b01 cmp r3, #1
|
|
8014096: d002 beq.n 801409e <osSemaphoreRelease+0x76>
|
|
stat = osErrorResource;
|
|
8014098: f06f 0302 mvn.w r3, #2
|
|
801409c: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
|
|
/* Return execution status */
|
|
return (stat);
|
|
801409e: 697b ldr r3, [r7, #20]
|
|
}
|
|
80140a0: 4618 mov r0, r3
|
|
80140a2: 3718 adds r7, #24
|
|
80140a4: 46bd mov sp, r7
|
|
80140a6: bd80 pop {r7, pc}
|
|
80140a8: e000ed04 .word 0xe000ed04
|
|
|
|
080140ac <osMessageQueueNew>:
|
|
|
|
Limitations:
|
|
- The memory for control block and and message data must be provided in the
|
|
osThreadAttr_t structure in order to allocate object statically.
|
|
*/
|
|
osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
|
|
80140ac: b580 push {r7, lr}
|
|
80140ae: b088 sub sp, #32
|
|
80140b0: af02 add r7, sp, #8
|
|
80140b2: 60f8 str r0, [r7, #12]
|
|
80140b4: 60b9 str r1, [r7, #8]
|
|
80140b6: 607a str r2, [r7, #4]
|
|
QueueHandle_t hQueue;
|
|
int32_t mem;
|
|
|
|
hQueue = NULL;
|
|
80140b8: 2300 movs r3, #0
|
|
80140ba: 617b str r3, [r7, #20]
|
|
|
|
if ((IRQ_Context() == 0U) && (msg_count > 0U) && (msg_size > 0U)) {
|
|
80140bc: f7ff fbe3 bl 8013886 <IRQ_Context>
|
|
80140c0: 4603 mov r3, r0
|
|
80140c2: 2b00 cmp r3, #0
|
|
80140c4: d15f bne.n 8014186 <osMessageQueueNew+0xda>
|
|
80140c6: 68fb ldr r3, [r7, #12]
|
|
80140c8: 2b00 cmp r3, #0
|
|
80140ca: d05c beq.n 8014186 <osMessageQueueNew+0xda>
|
|
80140cc: 68bb ldr r3, [r7, #8]
|
|
80140ce: 2b00 cmp r3, #0
|
|
80140d0: d059 beq.n 8014186 <osMessageQueueNew+0xda>
|
|
mem = -1;
|
|
80140d2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80140d6: 613b str r3, [r7, #16]
|
|
|
|
if (attr != NULL) {
|
|
80140d8: 687b ldr r3, [r7, #4]
|
|
80140da: 2b00 cmp r3, #0
|
|
80140dc: d029 beq.n 8014132 <osMessageQueueNew+0x86>
|
|
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
|
|
80140de: 687b ldr r3, [r7, #4]
|
|
80140e0: 689b ldr r3, [r3, #8]
|
|
80140e2: 2b00 cmp r3, #0
|
|
80140e4: d012 beq.n 801410c <osMessageQueueNew+0x60>
|
|
80140e6: 687b ldr r3, [r7, #4]
|
|
80140e8: 68db ldr r3, [r3, #12]
|
|
80140ea: 2b4f cmp r3, #79 @ 0x4f
|
|
80140ec: d90e bls.n 801410c <osMessageQueueNew+0x60>
|
|
(attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
|
|
80140ee: 687b ldr r3, [r7, #4]
|
|
80140f0: 691b ldr r3, [r3, #16]
|
|
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
|
|
80140f2: 2b00 cmp r3, #0
|
|
80140f4: d00a beq.n 801410c <osMessageQueueNew+0x60>
|
|
(attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
|
|
80140f6: 687b ldr r3, [r7, #4]
|
|
80140f8: 695a ldr r2, [r3, #20]
|
|
80140fa: 68fb ldr r3, [r7, #12]
|
|
80140fc: 68b9 ldr r1, [r7, #8]
|
|
80140fe: fb01 f303 mul.w r3, r1, r3
|
|
8014102: 429a cmp r2, r3
|
|
8014104: d302 bcc.n 801410c <osMessageQueueNew+0x60>
|
|
/* The memory for control block and message data is provided, use static object */
|
|
mem = 1;
|
|
8014106: 2301 movs r3, #1
|
|
8014108: 613b str r3, [r7, #16]
|
|
801410a: e014 b.n 8014136 <osMessageQueueNew+0x8a>
|
|
}
|
|
else {
|
|
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
|
|
801410c: 687b ldr r3, [r7, #4]
|
|
801410e: 689b ldr r3, [r3, #8]
|
|
8014110: 2b00 cmp r3, #0
|
|
8014112: d110 bne.n 8014136 <osMessageQueueNew+0x8a>
|
|
8014114: 687b ldr r3, [r7, #4]
|
|
8014116: 68db ldr r3, [r3, #12]
|
|
8014118: 2b00 cmp r3, #0
|
|
801411a: d10c bne.n 8014136 <osMessageQueueNew+0x8a>
|
|
(attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
|
|
801411c: 687b ldr r3, [r7, #4]
|
|
801411e: 691b ldr r3, [r3, #16]
|
|
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
|
|
8014120: 2b00 cmp r3, #0
|
|
8014122: d108 bne.n 8014136 <osMessageQueueNew+0x8a>
|
|
(attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
|
|
8014124: 687b ldr r3, [r7, #4]
|
|
8014126: 695b ldr r3, [r3, #20]
|
|
8014128: 2b00 cmp r3, #0
|
|
801412a: d104 bne.n 8014136 <osMessageQueueNew+0x8a>
|
|
/* Control block will be allocated from the dynamic pool */
|
|
mem = 0;
|
|
801412c: 2300 movs r3, #0
|
|
801412e: 613b str r3, [r7, #16]
|
|
8014130: e001 b.n 8014136 <osMessageQueueNew+0x8a>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
mem = 0;
|
|
8014132: 2300 movs r3, #0
|
|
8014134: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
if (mem == 1) {
|
|
8014136: 693b ldr r3, [r7, #16]
|
|
8014138: 2b01 cmp r3, #1
|
|
801413a: d10b bne.n 8014154 <osMessageQueueNew+0xa8>
|
|
#if (configSUPPORT_STATIC_ALLOCATION == 1)
|
|
hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);
|
|
801413c: 687b ldr r3, [r7, #4]
|
|
801413e: 691a ldr r2, [r3, #16]
|
|
8014140: 687b ldr r3, [r7, #4]
|
|
8014142: 689b ldr r3, [r3, #8]
|
|
8014144: 2100 movs r1, #0
|
|
8014146: 9100 str r1, [sp, #0]
|
|
8014148: 68b9 ldr r1, [r7, #8]
|
|
801414a: 68f8 ldr r0, [r7, #12]
|
|
801414c: f000 fa30 bl 80145b0 <xQueueGenericCreateStatic>
|
|
8014150: 6178 str r0, [r7, #20]
|
|
8014152: e008 b.n 8014166 <osMessageQueueNew+0xba>
|
|
#endif
|
|
}
|
|
else {
|
|
if (mem == 0) {
|
|
8014154: 693b ldr r3, [r7, #16]
|
|
8014156: 2b00 cmp r3, #0
|
|
8014158: d105 bne.n 8014166 <osMessageQueueNew+0xba>
|
|
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
|
|
hQueue = xQueueCreate (msg_count, msg_size);
|
|
801415a: 2200 movs r2, #0
|
|
801415c: 68b9 ldr r1, [r7, #8]
|
|
801415e: 68f8 ldr r0, [r7, #12]
|
|
8014160: f000 fa87 bl 8014672 <xQueueGenericCreate>
|
|
8014164: 6178 str r0, [r7, #20]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
#if (configQUEUE_REGISTRY_SIZE > 0)
|
|
if (hQueue != NULL) {
|
|
8014166: 697b ldr r3, [r7, #20]
|
|
8014168: 2b00 cmp r3, #0
|
|
801416a: d00c beq.n 8014186 <osMessageQueueNew+0xda>
|
|
if ((attr != NULL) && (attr->name != NULL)) {
|
|
801416c: 687b ldr r3, [r7, #4]
|
|
801416e: 2b00 cmp r3, #0
|
|
8014170: d009 beq.n 8014186 <osMessageQueueNew+0xda>
|
|
8014172: 687b ldr r3, [r7, #4]
|
|
8014174: 681b ldr r3, [r3, #0]
|
|
8014176: 2b00 cmp r3, #0
|
|
8014178: d005 beq.n 8014186 <osMessageQueueNew+0xda>
|
|
/* Only non-NULL name objects are added to the Queue Registry */
|
|
vQueueAddToRegistry (hQueue, attr->name);
|
|
801417a: 687b ldr r3, [r7, #4]
|
|
801417c: 681b ldr r3, [r3, #0]
|
|
801417e: 4619 mov r1, r3
|
|
8014180: 6978 ldr r0, [r7, #20]
|
|
8014182: f001 fa2f bl 80155e4 <vQueueAddToRegistry>
|
|
#endif
|
|
|
|
}
|
|
|
|
/* Return message queue ID */
|
|
return ((osMessageQueueId_t)hQueue);
|
|
8014186: 697b ldr r3, [r7, #20]
|
|
}
|
|
8014188: 4618 mov r0, r3
|
|
801418a: 3718 adds r7, #24
|
|
801418c: 46bd mov sp, r7
|
|
801418e: bd80 pop {r7, pc}
|
|
|
|
08014190 <osMessageQueuePut>:
|
|
Put a Message into a Queue or timeout if Queue is full.
|
|
|
|
Limitations:
|
|
- Message priority is ignored
|
|
*/
|
|
osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
|
|
8014190: b580 push {r7, lr}
|
|
8014192: b088 sub sp, #32
|
|
8014194: af00 add r7, sp, #0
|
|
8014196: 60f8 str r0, [r7, #12]
|
|
8014198: 60b9 str r1, [r7, #8]
|
|
801419a: 603b str r3, [r7, #0]
|
|
801419c: 4613 mov r3, r2
|
|
801419e: 71fb strb r3, [r7, #7]
|
|
QueueHandle_t hQueue = (QueueHandle_t)mq_id;
|
|
80141a0: 68fb ldr r3, [r7, #12]
|
|
80141a2: 61bb str r3, [r7, #24]
|
|
osStatus_t stat;
|
|
BaseType_t yield;
|
|
|
|
(void)msg_prio; /* Message priority is ignored */
|
|
|
|
stat = osOK;
|
|
80141a4: 2300 movs r3, #0
|
|
80141a6: 61fb str r3, [r7, #28]
|
|
|
|
if (IRQ_Context() != 0U) {
|
|
80141a8: f7ff fb6d bl 8013886 <IRQ_Context>
|
|
80141ac: 4603 mov r3, r0
|
|
80141ae: 2b00 cmp r3, #0
|
|
80141b0: d028 beq.n 8014204 <osMessageQueuePut+0x74>
|
|
if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
|
|
80141b2: 69bb ldr r3, [r7, #24]
|
|
80141b4: 2b00 cmp r3, #0
|
|
80141b6: d005 beq.n 80141c4 <osMessageQueuePut+0x34>
|
|
80141b8: 68bb ldr r3, [r7, #8]
|
|
80141ba: 2b00 cmp r3, #0
|
|
80141bc: d002 beq.n 80141c4 <osMessageQueuePut+0x34>
|
|
80141be: 683b ldr r3, [r7, #0]
|
|
80141c0: 2b00 cmp r3, #0
|
|
80141c2: d003 beq.n 80141cc <osMessageQueuePut+0x3c>
|
|
stat = osErrorParameter;
|
|
80141c4: f06f 0303 mvn.w r3, #3
|
|
80141c8: 61fb str r3, [r7, #28]
|
|
80141ca: e038 b.n 801423e <osMessageQueuePut+0xae>
|
|
}
|
|
else {
|
|
yield = pdFALSE;
|
|
80141cc: 2300 movs r3, #0
|
|
80141ce: 617b str r3, [r7, #20]
|
|
|
|
if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {
|
|
80141d0: f107 0214 add.w r2, r7, #20
|
|
80141d4: 2300 movs r3, #0
|
|
80141d6: 68b9 ldr r1, [r7, #8]
|
|
80141d8: 69b8 ldr r0, [r7, #24]
|
|
80141da: f000 fcdd bl 8014b98 <xQueueGenericSendFromISR>
|
|
80141de: 4603 mov r3, r0
|
|
80141e0: 2b01 cmp r3, #1
|
|
80141e2: d003 beq.n 80141ec <osMessageQueuePut+0x5c>
|
|
stat = osErrorResource;
|
|
80141e4: f06f 0302 mvn.w r3, #2
|
|
80141e8: 61fb str r3, [r7, #28]
|
|
80141ea: e028 b.n 801423e <osMessageQueuePut+0xae>
|
|
} else {
|
|
portYIELD_FROM_ISR (yield);
|
|
80141ec: 697b ldr r3, [r7, #20]
|
|
80141ee: 2b00 cmp r3, #0
|
|
80141f0: d025 beq.n 801423e <osMessageQueuePut+0xae>
|
|
80141f2: 4b15 ldr r3, [pc, #84] @ (8014248 <osMessageQueuePut+0xb8>)
|
|
80141f4: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80141f8: 601a str r2, [r3, #0]
|
|
80141fa: f3bf 8f4f dsb sy
|
|
80141fe: f3bf 8f6f isb sy
|
|
8014202: e01c b.n 801423e <osMessageQueuePut+0xae>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
if ((hQueue == NULL) || (msg_ptr == NULL)) {
|
|
8014204: 69bb ldr r3, [r7, #24]
|
|
8014206: 2b00 cmp r3, #0
|
|
8014208: d002 beq.n 8014210 <osMessageQueuePut+0x80>
|
|
801420a: 68bb ldr r3, [r7, #8]
|
|
801420c: 2b00 cmp r3, #0
|
|
801420e: d103 bne.n 8014218 <osMessageQueuePut+0x88>
|
|
stat = osErrorParameter;
|
|
8014210: f06f 0303 mvn.w r3, #3
|
|
8014214: 61fb str r3, [r7, #28]
|
|
8014216: e012 b.n 801423e <osMessageQueuePut+0xae>
|
|
}
|
|
else {
|
|
if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
|
|
8014218: 2300 movs r3, #0
|
|
801421a: 683a ldr r2, [r7, #0]
|
|
801421c: 68b9 ldr r1, [r7, #8]
|
|
801421e: 69b8 ldr r0, [r7, #24]
|
|
8014220: f000 fbb8 bl 8014994 <xQueueGenericSend>
|
|
8014224: 4603 mov r3, r0
|
|
8014226: 2b01 cmp r3, #1
|
|
8014228: d009 beq.n 801423e <osMessageQueuePut+0xae>
|
|
if (timeout != 0U) {
|
|
801422a: 683b ldr r3, [r7, #0]
|
|
801422c: 2b00 cmp r3, #0
|
|
801422e: d003 beq.n 8014238 <osMessageQueuePut+0xa8>
|
|
stat = osErrorTimeout;
|
|
8014230: f06f 0301 mvn.w r3, #1
|
|
8014234: 61fb str r3, [r7, #28]
|
|
8014236: e002 b.n 801423e <osMessageQueuePut+0xae>
|
|
} else {
|
|
stat = osErrorResource;
|
|
8014238: f06f 0302 mvn.w r3, #2
|
|
801423c: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return execution status */
|
|
return (stat);
|
|
801423e: 69fb ldr r3, [r7, #28]
|
|
}
|
|
8014240: 4618 mov r0, r3
|
|
8014242: 3720 adds r7, #32
|
|
8014244: 46bd mov sp, r7
|
|
8014246: bd80 pop {r7, pc}
|
|
8014248: e000ed04 .word 0xe000ed04
|
|
|
|
0801424c <osMessageQueueGet>:
|
|
Get a Message from a Queue or timeout if Queue is empty.
|
|
|
|
Limitations:
|
|
- Message priority is ignored
|
|
*/
|
|
osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
|
|
801424c: b580 push {r7, lr}
|
|
801424e: b088 sub sp, #32
|
|
8014250: af00 add r7, sp, #0
|
|
8014252: 60f8 str r0, [r7, #12]
|
|
8014254: 60b9 str r1, [r7, #8]
|
|
8014256: 607a str r2, [r7, #4]
|
|
8014258: 603b str r3, [r7, #0]
|
|
QueueHandle_t hQueue = (QueueHandle_t)mq_id;
|
|
801425a: 68fb ldr r3, [r7, #12]
|
|
801425c: 61bb str r3, [r7, #24]
|
|
osStatus_t stat;
|
|
BaseType_t yield;
|
|
|
|
(void)msg_prio; /* Message priority is ignored */
|
|
|
|
stat = osOK;
|
|
801425e: 2300 movs r3, #0
|
|
8014260: 61fb str r3, [r7, #28]
|
|
|
|
if (IRQ_Context() != 0U) {
|
|
8014262: f7ff fb10 bl 8013886 <IRQ_Context>
|
|
8014266: 4603 mov r3, r0
|
|
8014268: 2b00 cmp r3, #0
|
|
801426a: d028 beq.n 80142be <osMessageQueueGet+0x72>
|
|
if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
|
|
801426c: 69bb ldr r3, [r7, #24]
|
|
801426e: 2b00 cmp r3, #0
|
|
8014270: d005 beq.n 801427e <osMessageQueueGet+0x32>
|
|
8014272: 68bb ldr r3, [r7, #8]
|
|
8014274: 2b00 cmp r3, #0
|
|
8014276: d002 beq.n 801427e <osMessageQueueGet+0x32>
|
|
8014278: 683b ldr r3, [r7, #0]
|
|
801427a: 2b00 cmp r3, #0
|
|
801427c: d003 beq.n 8014286 <osMessageQueueGet+0x3a>
|
|
stat = osErrorParameter;
|
|
801427e: f06f 0303 mvn.w r3, #3
|
|
8014282: 61fb str r3, [r7, #28]
|
|
8014284: e037 b.n 80142f6 <osMessageQueueGet+0xaa>
|
|
}
|
|
else {
|
|
yield = pdFALSE;
|
|
8014286: 2300 movs r3, #0
|
|
8014288: 617b str r3, [r7, #20]
|
|
|
|
if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {
|
|
801428a: f107 0314 add.w r3, r7, #20
|
|
801428e: 461a mov r2, r3
|
|
8014290: 68b9 ldr r1, [r7, #8]
|
|
8014292: 69b8 ldr r0, [r7, #24]
|
|
8014294: f000 ffc0 bl 8015218 <xQueueReceiveFromISR>
|
|
8014298: 4603 mov r3, r0
|
|
801429a: 2b01 cmp r3, #1
|
|
801429c: d003 beq.n 80142a6 <osMessageQueueGet+0x5a>
|
|
stat = osErrorResource;
|
|
801429e: f06f 0302 mvn.w r3, #2
|
|
80142a2: 61fb str r3, [r7, #28]
|
|
80142a4: e027 b.n 80142f6 <osMessageQueueGet+0xaa>
|
|
} else {
|
|
portYIELD_FROM_ISR (yield);
|
|
80142a6: 697b ldr r3, [r7, #20]
|
|
80142a8: 2b00 cmp r3, #0
|
|
80142aa: d024 beq.n 80142f6 <osMessageQueueGet+0xaa>
|
|
80142ac: 4b14 ldr r3, [pc, #80] @ (8014300 <osMessageQueueGet+0xb4>)
|
|
80142ae: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80142b2: 601a str r2, [r3, #0]
|
|
80142b4: f3bf 8f4f dsb sy
|
|
80142b8: f3bf 8f6f isb sy
|
|
80142bc: e01b b.n 80142f6 <osMessageQueueGet+0xaa>
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
if ((hQueue == NULL) || (msg_ptr == NULL)) {
|
|
80142be: 69bb ldr r3, [r7, #24]
|
|
80142c0: 2b00 cmp r3, #0
|
|
80142c2: d002 beq.n 80142ca <osMessageQueueGet+0x7e>
|
|
80142c4: 68bb ldr r3, [r7, #8]
|
|
80142c6: 2b00 cmp r3, #0
|
|
80142c8: d103 bne.n 80142d2 <osMessageQueueGet+0x86>
|
|
stat = osErrorParameter;
|
|
80142ca: f06f 0303 mvn.w r3, #3
|
|
80142ce: 61fb str r3, [r7, #28]
|
|
80142d0: e011 b.n 80142f6 <osMessageQueueGet+0xaa>
|
|
}
|
|
else {
|
|
if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
|
|
80142d2: 683a ldr r2, [r7, #0]
|
|
80142d4: 68b9 ldr r1, [r7, #8]
|
|
80142d6: 69b8 ldr r0, [r7, #24]
|
|
80142d8: f000 fdbc bl 8014e54 <xQueueReceive>
|
|
80142dc: 4603 mov r3, r0
|
|
80142de: 2b01 cmp r3, #1
|
|
80142e0: d009 beq.n 80142f6 <osMessageQueueGet+0xaa>
|
|
if (timeout != 0U) {
|
|
80142e2: 683b ldr r3, [r7, #0]
|
|
80142e4: 2b00 cmp r3, #0
|
|
80142e6: d003 beq.n 80142f0 <osMessageQueueGet+0xa4>
|
|
stat = osErrorTimeout;
|
|
80142e8: f06f 0301 mvn.w r3, #1
|
|
80142ec: 61fb str r3, [r7, #28]
|
|
80142ee: e002 b.n 80142f6 <osMessageQueueGet+0xaa>
|
|
} else {
|
|
stat = osErrorResource;
|
|
80142f0: f06f 0302 mvn.w r3, #2
|
|
80142f4: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return execution status */
|
|
return (stat);
|
|
80142f6: 69fb ldr r3, [r7, #28]
|
|
}
|
|
80142f8: 4618 mov r0, r3
|
|
80142fa: 3720 adds r7, #32
|
|
80142fc: 46bd mov sp, r7
|
|
80142fe: bd80 pop {r7, pc}
|
|
8014300: e000ed04 .word 0xe000ed04
|
|
|
|
08014304 <vApplicationGetIdleTaskMemory>:
|
|
#if (configSUPPORT_STATIC_ALLOCATION == 1)
|
|
/*
|
|
vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
|
|
equals to 1 and is required for static memory allocation support.
|
|
*/
|
|
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
|
|
8014304: b480 push {r7}
|
|
8014306: b085 sub sp, #20
|
|
8014308: af00 add r7, sp, #0
|
|
801430a: 60f8 str r0, [r7, #12]
|
|
801430c: 60b9 str r1, [r7, #8]
|
|
801430e: 607a str r2, [r7, #4]
|
|
/* Idle task control block and stack */
|
|
static StaticTask_t Idle_TCB;
|
|
static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
|
|
|
|
*ppxIdleTaskTCBBuffer = &Idle_TCB;
|
|
8014310: 68fb ldr r3, [r7, #12]
|
|
8014312: 4a07 ldr r2, [pc, #28] @ (8014330 <vApplicationGetIdleTaskMemory+0x2c>)
|
|
8014314: 601a str r2, [r3, #0]
|
|
*ppxIdleTaskStackBuffer = &Idle_Stack[0];
|
|
8014316: 68bb ldr r3, [r7, #8]
|
|
8014318: 4a06 ldr r2, [pc, #24] @ (8014334 <vApplicationGetIdleTaskMemory+0x30>)
|
|
801431a: 601a str r2, [r3, #0]
|
|
*pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
|
|
801431c: 687b ldr r3, [r7, #4]
|
|
801431e: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8014322: 601a str r2, [r3, #0]
|
|
}
|
|
8014324: bf00 nop
|
|
8014326: 3714 adds r7, #20
|
|
8014328: 46bd mov sp, r7
|
|
801432a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801432e: 4770 bx lr
|
|
8014330: 200007d0 .word 0x200007d0
|
|
8014334: 2000087c .word 0x2000087c
|
|
|
|
08014338 <vApplicationGetTimerTaskMemory>:
|
|
|
|
/*
|
|
vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
|
|
equals to 1 and is required for static memory allocation support.
|
|
*/
|
|
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
|
|
8014338: b480 push {r7}
|
|
801433a: b085 sub sp, #20
|
|
801433c: af00 add r7, sp, #0
|
|
801433e: 60f8 str r0, [r7, #12]
|
|
8014340: 60b9 str r1, [r7, #8]
|
|
8014342: 607a str r2, [r7, #4]
|
|
/* Timer task control block and stack */
|
|
static StaticTask_t Timer_TCB;
|
|
static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
|
|
|
|
*ppxTimerTaskTCBBuffer = &Timer_TCB;
|
|
8014344: 68fb ldr r3, [r7, #12]
|
|
8014346: 4a07 ldr r2, [pc, #28] @ (8014364 <vApplicationGetTimerTaskMemory+0x2c>)
|
|
8014348: 601a str r2, [r3, #0]
|
|
*ppxTimerTaskStackBuffer = &Timer_Stack[0];
|
|
801434a: 68bb ldr r3, [r7, #8]
|
|
801434c: 4a06 ldr r2, [pc, #24] @ (8014368 <vApplicationGetTimerTaskMemory+0x30>)
|
|
801434e: 601a str r2, [r3, #0]
|
|
*pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
|
|
8014350: 687b ldr r3, [r7, #4]
|
|
8014352: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8014356: 601a str r2, [r3, #0]
|
|
}
|
|
8014358: bf00 nop
|
|
801435a: 3714 adds r7, #20
|
|
801435c: 46bd mov sp, r7
|
|
801435e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8014362: 4770 bx lr
|
|
8014364: 2000107c .word 0x2000107c
|
|
8014368: 20001128 .word 0x20001128
|
|
|
|
0801436c <vListInitialise>:
|
|
/*-----------------------------------------------------------
|
|
* PUBLIC LIST API documented in list.h
|
|
*----------------------------------------------------------*/
|
|
|
|
void vListInitialise( List_t * const pxList )
|
|
{
|
|
801436c: b480 push {r7}
|
|
801436e: b083 sub sp, #12
|
|
8014370: af00 add r7, sp, #0
|
|
8014372: 6078 str r0, [r7, #4]
|
|
/* The list structure contains a list item which is used to mark the
|
|
* end of the list. To initialise the list the list end is inserted
|
|
* as the only list entry. */
|
|
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
8014374: 687b ldr r3, [r7, #4]
|
|
8014376: f103 0208 add.w r2, r3, #8
|
|
801437a: 687b ldr r3, [r7, #4]
|
|
801437c: 605a str r2, [r3, #4]
|
|
|
|
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
|
|
|
|
/* The list end value is the highest possible value in the list to
|
|
* ensure it remains at the end of the list. */
|
|
pxList->xListEnd.xItemValue = portMAX_DELAY;
|
|
801437e: 687b ldr r3, [r7, #4]
|
|
8014380: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8014384: 609a str r2, [r3, #8]
|
|
|
|
/* The list end next and previous pointers point to itself so we know
|
|
* when the list is empty. */
|
|
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
8014386: 687b ldr r3, [r7, #4]
|
|
8014388: f103 0208 add.w r2, r3, #8
|
|
801438c: 687b ldr r3, [r7, #4]
|
|
801438e: 60da str r2, [r3, #12]
|
|
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
8014390: 687b ldr r3, [r7, #4]
|
|
8014392: f103 0208 add.w r2, r3, #8
|
|
8014396: 687b ldr r3, [r7, #4]
|
|
8014398: 611a str r2, [r3, #16]
|
|
pxList->xListEnd.pxContainer = NULL;
|
|
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
|
|
}
|
|
#endif
|
|
|
|
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
|
|
801439a: 687b ldr r3, [r7, #4]
|
|
801439c: 2200 movs r2, #0
|
|
801439e: 601a str r2, [r3, #0]
|
|
|
|
/* Write known values into the list if
|
|
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
|
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
|
|
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
|
|
}
|
|
80143a0: bf00 nop
|
|
80143a2: 370c adds r7, #12
|
|
80143a4: 46bd mov sp, r7
|
|
80143a6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80143aa: 4770 bx lr
|
|
|
|
080143ac <vListInitialiseItem>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInitialiseItem( ListItem_t * const pxItem )
|
|
{
|
|
80143ac: b480 push {r7}
|
|
80143ae: b083 sub sp, #12
|
|
80143b0: af00 add r7, sp, #0
|
|
80143b2: 6078 str r0, [r7, #4]
|
|
/* Make sure the list item is not recorded as being on a list. */
|
|
pxItem->pxContainer = NULL;
|
|
80143b4: 687b ldr r3, [r7, #4]
|
|
80143b6: 2200 movs r2, #0
|
|
80143b8: 611a str r2, [r3, #16]
|
|
|
|
/* Write known values into the list item if
|
|
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
|
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
}
|
|
80143ba: bf00 nop
|
|
80143bc: 370c adds r7, #12
|
|
80143be: 46bd mov sp, r7
|
|
80143c0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80143c4: 4770 bx lr
|
|
|
|
080143c6 <vListInsert>:
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsert( List_t * const pxList,
|
|
ListItem_t * const pxNewListItem )
|
|
{
|
|
80143c6: b480 push {r7}
|
|
80143c8: b085 sub sp, #20
|
|
80143ca: af00 add r7, sp, #0
|
|
80143cc: 6078 str r0, [r7, #4]
|
|
80143ce: 6039 str r1, [r7, #0]
|
|
ListItem_t * pxIterator;
|
|
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
|
|
80143d0: 683b ldr r3, [r7, #0]
|
|
80143d2: 681b ldr r3, [r3, #0]
|
|
80143d4: 60bb str r3, [r7, #8]
|
|
* new list item should be placed after it. This ensures that TCBs which are
|
|
* stored in ready lists (all of which have the same xItemValue value) get a
|
|
* share of the CPU. However, if the xItemValue is the same as the back marker
|
|
* the iteration loop below will not end. Therefore the value is checked
|
|
* first, and the algorithm slightly modified if necessary. */
|
|
if( xValueOfInsertion == portMAX_DELAY )
|
|
80143d6: 68bb ldr r3, [r7, #8]
|
|
80143d8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
80143dc: d103 bne.n 80143e6 <vListInsert+0x20>
|
|
{
|
|
pxIterator = pxList->xListEnd.pxPrevious;
|
|
80143de: 687b ldr r3, [r7, #4]
|
|
80143e0: 691b ldr r3, [r3, #16]
|
|
80143e2: 60fb str r3, [r7, #12]
|
|
80143e4: e00c b.n 8014400 <vListInsert+0x3a>
|
|
* 5) If the FreeRTOS port supports interrupt nesting then ensure that
|
|
* the priority of the tick interrupt is at or below
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
**********************************************************************/
|
|
|
|
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
|
|
80143e6: 687b ldr r3, [r7, #4]
|
|
80143e8: 3308 adds r3, #8
|
|
80143ea: 60fb str r3, [r7, #12]
|
|
80143ec: e002 b.n 80143f4 <vListInsert+0x2e>
|
|
80143ee: 68fb ldr r3, [r7, #12]
|
|
80143f0: 685b ldr r3, [r3, #4]
|
|
80143f2: 60fb str r3, [r7, #12]
|
|
80143f4: 68fb ldr r3, [r7, #12]
|
|
80143f6: 685b ldr r3, [r3, #4]
|
|
80143f8: 681b ldr r3, [r3, #0]
|
|
80143fa: 68ba ldr r2, [r7, #8]
|
|
80143fc: 429a cmp r2, r3
|
|
80143fe: d2f6 bcs.n 80143ee <vListInsert+0x28>
|
|
/* There is nothing to do here, just iterating to the wanted
|
|
* insertion position. */
|
|
}
|
|
}
|
|
|
|
pxNewListItem->pxNext = pxIterator->pxNext;
|
|
8014400: 68fb ldr r3, [r7, #12]
|
|
8014402: 685a ldr r2, [r3, #4]
|
|
8014404: 683b ldr r3, [r7, #0]
|
|
8014406: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
|
|
8014408: 683b ldr r3, [r7, #0]
|
|
801440a: 685b ldr r3, [r3, #4]
|
|
801440c: 683a ldr r2, [r7, #0]
|
|
801440e: 609a str r2, [r3, #8]
|
|
pxNewListItem->pxPrevious = pxIterator;
|
|
8014410: 683b ldr r3, [r7, #0]
|
|
8014412: 68fa ldr r2, [r7, #12]
|
|
8014414: 609a str r2, [r3, #8]
|
|
pxIterator->pxNext = pxNewListItem;
|
|
8014416: 68fb ldr r3, [r7, #12]
|
|
8014418: 683a ldr r2, [r7, #0]
|
|
801441a: 605a str r2, [r3, #4]
|
|
|
|
/* Remember which list the item is in. This allows fast removal of the
|
|
* item later. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
801441c: 683b ldr r3, [r7, #0]
|
|
801441e: 687a ldr r2, [r7, #4]
|
|
8014420: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
8014422: 687b ldr r3, [r7, #4]
|
|
8014424: 681b ldr r3, [r3, #0]
|
|
8014426: 1c5a adds r2, r3, #1
|
|
8014428: 687b ldr r3, [r7, #4]
|
|
801442a: 601a str r2, [r3, #0]
|
|
}
|
|
801442c: bf00 nop
|
|
801442e: 3714 adds r7, #20
|
|
8014430: 46bd mov sp, r7
|
|
8014432: f85d 7b04 ldr.w r7, [sp], #4
|
|
8014436: 4770 bx lr
|
|
|
|
08014438 <uxListRemove>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
|
|
{
|
|
8014438: b480 push {r7}
|
|
801443a: b085 sub sp, #20
|
|
801443c: af00 add r7, sp, #0
|
|
801443e: 6078 str r0, [r7, #4]
|
|
/* The list item knows which list it is in. Obtain the list from the list
|
|
* item. */
|
|
List_t * const pxList = pxItemToRemove->pxContainer;
|
|
8014440: 687b ldr r3, [r7, #4]
|
|
8014442: 691b ldr r3, [r3, #16]
|
|
8014444: 60fb str r3, [r7, #12]
|
|
|
|
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
|
|
8014446: 687b ldr r3, [r7, #4]
|
|
8014448: 685b ldr r3, [r3, #4]
|
|
801444a: 687a ldr r2, [r7, #4]
|
|
801444c: 6892 ldr r2, [r2, #8]
|
|
801444e: 609a str r2, [r3, #8]
|
|
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
|
|
8014450: 687b ldr r3, [r7, #4]
|
|
8014452: 689b ldr r3, [r3, #8]
|
|
8014454: 687a ldr r2, [r7, #4]
|
|
8014456: 6852 ldr r2, [r2, #4]
|
|
8014458: 605a str r2, [r3, #4]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
/* Make sure the index is left pointing to a valid item. */
|
|
if( pxList->pxIndex == pxItemToRemove )
|
|
801445a: 68fb ldr r3, [r7, #12]
|
|
801445c: 685b ldr r3, [r3, #4]
|
|
801445e: 687a ldr r2, [r7, #4]
|
|
8014460: 429a cmp r2, r3
|
|
8014462: d103 bne.n 801446c <uxListRemove+0x34>
|
|
{
|
|
pxList->pxIndex = pxItemToRemove->pxPrevious;
|
|
8014464: 687b ldr r3, [r7, #4]
|
|
8014466: 689a ldr r2, [r3, #8]
|
|
8014468: 68fb ldr r3, [r7, #12]
|
|
801446a: 605a str r2, [r3, #4]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxItemToRemove->pxContainer = NULL;
|
|
801446c: 687b ldr r3, [r7, #4]
|
|
801446e: 2200 movs r2, #0
|
|
8014470: 611a str r2, [r3, #16]
|
|
( pxList->uxNumberOfItems )--;
|
|
8014472: 68fb ldr r3, [r7, #12]
|
|
8014474: 681b ldr r3, [r3, #0]
|
|
8014476: 1e5a subs r2, r3, #1
|
|
8014478: 68fb ldr r3, [r7, #12]
|
|
801447a: 601a str r2, [r3, #0]
|
|
|
|
return pxList->uxNumberOfItems;
|
|
801447c: 68fb ldr r3, [r7, #12]
|
|
801447e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8014480: 4618 mov r0, r3
|
|
8014482: 3714 adds r7, #20
|
|
8014484: 46bd mov sp, r7
|
|
8014486: f85d 7b04 ldr.w r7, [sp], #4
|
|
801448a: 4770 bx lr
|
|
|
|
0801448c <xQueueGenericReset>:
|
|
} while( 0 )
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
|
|
BaseType_t xNewQueue )
|
|
{
|
|
801448c: b580 push {r7, lr}
|
|
801448e: b086 sub sp, #24
|
|
8014490: af00 add r7, sp, #0
|
|
8014492: 6078 str r0, [r7, #4]
|
|
8014494: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn = pdPASS;
|
|
8014496: 2301 movs r3, #1
|
|
8014498: 617b str r3, [r7, #20]
|
|
Queue_t * const pxQueue = xQueue;
|
|
801449a: 687b ldr r3, [r7, #4]
|
|
801449c: 613b str r3, [r7, #16]
|
|
|
|
configASSERT( pxQueue );
|
|
801449e: 693b ldr r3, [r7, #16]
|
|
80144a0: 2b00 cmp r3, #0
|
|
80144a2: d10b bne.n 80144bc <xQueueGenericReset+0x30>
|
|
|
|
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
80144a4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80144a8: f383 8811 msr BASEPRI, r3
|
|
80144ac: f3bf 8f6f isb sy
|
|
80144b0: f3bf 8f4f dsb sy
|
|
80144b4: 60fb str r3, [r7, #12]
|
|
" msr basepri, %0 \n"\
|
|
" isb \n"\
|
|
" dsb \n"\
|
|
: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
}
|
|
80144b6: bf00 nop
|
|
80144b8: bf00 nop
|
|
80144ba: e7fd b.n 80144b8 <xQueueGenericReset+0x2c>
|
|
|
|
if( ( pxQueue != NULL ) &&
|
|
80144bc: 693b ldr r3, [r7, #16]
|
|
80144be: 2b00 cmp r3, #0
|
|
80144c0: d05d beq.n 801457e <xQueueGenericReset+0xf2>
|
|
( pxQueue->uxLength >= 1U ) &&
|
|
80144c2: 693b ldr r3, [r7, #16]
|
|
80144c4: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
if( ( pxQueue != NULL ) &&
|
|
80144c6: 2b00 cmp r3, #0
|
|
80144c8: d059 beq.n 801457e <xQueueGenericReset+0xf2>
|
|
/* Check for multiplication overflow. */
|
|
( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) )
|
|
80144ca: 693b ldr r3, [r7, #16]
|
|
80144cc: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
80144ce: 693b ldr r3, [r7, #16]
|
|
80144d0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80144d2: 2100 movs r1, #0
|
|
80144d4: fba3 2302 umull r2, r3, r3, r2
|
|
80144d8: 2b00 cmp r3, #0
|
|
80144da: d000 beq.n 80144de <xQueueGenericReset+0x52>
|
|
80144dc: 2101 movs r1, #1
|
|
80144de: 460b mov r3, r1
|
|
( pxQueue->uxLength >= 1U ) &&
|
|
80144e0: 2b00 cmp r3, #0
|
|
80144e2: d14c bne.n 801457e <xQueueGenericReset+0xf2>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
80144e4: f003 fc24 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
80144e8: 693b ldr r3, [r7, #16]
|
|
80144ea: 681a ldr r2, [r3, #0]
|
|
80144ec: 693b ldr r3, [r7, #16]
|
|
80144ee: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80144f0: 6939 ldr r1, [r7, #16]
|
|
80144f2: 6c09 ldr r1, [r1, #64] @ 0x40
|
|
80144f4: fb01 f303 mul.w r3, r1, r3
|
|
80144f8: 441a add r2, r3
|
|
80144fa: 693b ldr r3, [r7, #16]
|
|
80144fc: 609a str r2, [r3, #8]
|
|
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
|
|
80144fe: 693b ldr r3, [r7, #16]
|
|
8014500: 2200 movs r2, #0
|
|
8014502: 639a str r2, [r3, #56] @ 0x38
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
8014504: 693b ldr r3, [r7, #16]
|
|
8014506: 681a ldr r2, [r3, #0]
|
|
8014508: 693b ldr r3, [r7, #16]
|
|
801450a: 605a str r2, [r3, #4]
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
801450c: 693b ldr r3, [r7, #16]
|
|
801450e: 681a ldr r2, [r3, #0]
|
|
8014510: 693b ldr r3, [r7, #16]
|
|
8014512: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8014514: 3b01 subs r3, #1
|
|
8014516: 6939 ldr r1, [r7, #16]
|
|
8014518: 6c09 ldr r1, [r1, #64] @ 0x40
|
|
801451a: fb01 f303 mul.w r3, r1, r3
|
|
801451e: 441a add r2, r3
|
|
8014520: 693b ldr r3, [r7, #16]
|
|
8014522: 60da str r2, [r3, #12]
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
8014524: 693b ldr r3, [r7, #16]
|
|
8014526: 22ff movs r2, #255 @ 0xff
|
|
8014528: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
801452c: 693b ldr r3, [r7, #16]
|
|
801452e: 22ff movs r2, #255 @ 0xff
|
|
8014530: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
if( xNewQueue == pdFALSE )
|
|
8014534: 683b ldr r3, [r7, #0]
|
|
8014536: 2b00 cmp r3, #0
|
|
8014538: d114 bne.n 8014564 <xQueueGenericReset+0xd8>
|
|
/* If there are tasks blocked waiting to read from the queue, then
|
|
* the tasks will remain blocked as after this function exits the queue
|
|
* will still be empty. If there are tasks blocked waiting to write to
|
|
* the queue, then one should be unblocked as after this function exits
|
|
* it will be possible to write to it. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
801453a: 693b ldr r3, [r7, #16]
|
|
801453c: 691b ldr r3, [r3, #16]
|
|
801453e: 2b00 cmp r3, #0
|
|
8014540: d01a beq.n 8014578 <xQueueGenericReset+0xec>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
8014542: 693b ldr r3, [r7, #16]
|
|
8014544: 3310 adds r3, #16
|
|
8014546: 4618 mov r0, r3
|
|
8014548: f001 fea2 bl 8016290 <xTaskRemoveFromEventList>
|
|
801454c: 4603 mov r3, r0
|
|
801454e: 2b00 cmp r3, #0
|
|
8014550: d012 beq.n 8014578 <xQueueGenericReset+0xec>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
8014552: 4b16 ldr r3, [pc, #88] @ (80145ac <xQueueGenericReset+0x120>)
|
|
8014554: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8014558: 601a str r2, [r3, #0]
|
|
801455a: f3bf 8f4f dsb sy
|
|
801455e: f3bf 8f6f isb sy
|
|
8014562: e009 b.n 8014578 <xQueueGenericReset+0xec>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Ensure the event queues start in the correct state. */
|
|
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
|
|
8014564: 693b ldr r3, [r7, #16]
|
|
8014566: 3310 adds r3, #16
|
|
8014568: 4618 mov r0, r3
|
|
801456a: f7ff feff bl 801436c <vListInitialise>
|
|
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
|
|
801456e: 693b ldr r3, [r7, #16]
|
|
8014570: 3324 adds r3, #36 @ 0x24
|
|
8014572: 4618 mov r0, r3
|
|
8014574: f7ff fefa bl 801436c <vListInitialise>
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8014578: f003 fc0c bl 8017d94 <vPortExitCritical>
|
|
801457c: e001 b.n 8014582 <xQueueGenericReset+0xf6>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFAIL;
|
|
801457e: 2300 movs r3, #0
|
|
8014580: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
configASSERT( xReturn != pdFAIL );
|
|
8014582: 697b ldr r3, [r7, #20]
|
|
8014584: 2b00 cmp r3, #0
|
|
8014586: d10b bne.n 80145a0 <xQueueGenericReset+0x114>
|
|
__asm volatile
|
|
8014588: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801458c: f383 8811 msr BASEPRI, r3
|
|
8014590: f3bf 8f6f isb sy
|
|
8014594: f3bf 8f4f dsb sy
|
|
8014598: 60bb str r3, [r7, #8]
|
|
}
|
|
801459a: bf00 nop
|
|
801459c: bf00 nop
|
|
801459e: e7fd b.n 801459c <xQueueGenericReset+0x110>
|
|
|
|
/* A value is returned for calling semantic consistency with previous
|
|
* versions. */
|
|
return xReturn;
|
|
80145a0: 697b ldr r3, [r7, #20]
|
|
}
|
|
80145a2: 4618 mov r0, r3
|
|
80145a4: 3718 adds r7, #24
|
|
80145a6: 46bd mov sp, r7
|
|
80145a8: bd80 pop {r7, pc}
|
|
80145aa: bf00 nop
|
|
80145ac: e000ed04 .word 0xe000ed04
|
|
|
|
080145b0 <xQueueGenericCreateStatic>:
|
|
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
|
|
const UBaseType_t uxItemSize,
|
|
uint8_t * pucQueueStorage,
|
|
StaticQueue_t * pxStaticQueue,
|
|
const uint8_t ucQueueType )
|
|
{
|
|
80145b0: b580 push {r7, lr}
|
|
80145b2: b08c sub sp, #48 @ 0x30
|
|
80145b4: af02 add r7, sp, #8
|
|
80145b6: 60f8 str r0, [r7, #12]
|
|
80145b8: 60b9 str r1, [r7, #8]
|
|
80145ba: 607a str r2, [r7, #4]
|
|
80145bc: 603b str r3, [r7, #0]
|
|
Queue_t * pxNewQueue = NULL;
|
|
80145be: 2300 movs r3, #0
|
|
80145c0: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* The StaticQueue_t structure and the queue storage area must be
|
|
* supplied. */
|
|
configASSERT( pxStaticQueue );
|
|
80145c2: 683b ldr r3, [r7, #0]
|
|
80145c4: 2b00 cmp r3, #0
|
|
80145c6: d10b bne.n 80145e0 <xQueueGenericCreateStatic+0x30>
|
|
__asm volatile
|
|
80145c8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80145cc: f383 8811 msr BASEPRI, r3
|
|
80145d0: f3bf 8f6f isb sy
|
|
80145d4: f3bf 8f4f dsb sy
|
|
80145d8: 623b str r3, [r7, #32]
|
|
}
|
|
80145da: bf00 nop
|
|
80145dc: bf00 nop
|
|
80145de: e7fd b.n 80145dc <xQueueGenericCreateStatic+0x2c>
|
|
|
|
if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
|
|
80145e0: 68fb ldr r3, [r7, #12]
|
|
80145e2: 2b00 cmp r3, #0
|
|
80145e4: d031 beq.n 801464a <xQueueGenericCreateStatic+0x9a>
|
|
80145e6: 683b ldr r3, [r7, #0]
|
|
80145e8: 2b00 cmp r3, #0
|
|
80145ea: d02e beq.n 801464a <xQueueGenericCreateStatic+0x9a>
|
|
( pxStaticQueue != NULL ) &&
|
|
80145ec: 687b ldr r3, [r7, #4]
|
|
80145ee: 2b00 cmp r3, #0
|
|
80145f0: d002 beq.n 80145f8 <xQueueGenericCreateStatic+0x48>
|
|
|
|
/* A queue storage area should be provided if the item size is not 0, and
|
|
* should not be provided if the item size is 0. */
|
|
( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) &&
|
|
80145f2: 68bb ldr r3, [r7, #8]
|
|
80145f4: 2b00 cmp r3, #0
|
|
80145f6: d028 beq.n 801464a <xQueueGenericCreateStatic+0x9a>
|
|
80145f8: 687b ldr r3, [r7, #4]
|
|
80145fa: 2b00 cmp r3, #0
|
|
80145fc: d102 bne.n 8014604 <xQueueGenericCreateStatic+0x54>
|
|
( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) )
|
|
80145fe: 68bb ldr r3, [r7, #8]
|
|
8014600: 2b00 cmp r3, #0
|
|
8014602: d122 bne.n 801464a <xQueueGenericCreateStatic+0x9a>
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
{
|
|
/* Sanity check that the size of the structure used to declare a
|
|
* variable of type StaticQueue_t or StaticSemaphore_t equals the size of
|
|
* the real queue and semaphore structures. */
|
|
volatile size_t xSize = sizeof( StaticQueue_t );
|
|
8014604: 2350 movs r3, #80 @ 0x50
|
|
8014606: 617b str r3, [r7, #20]
|
|
|
|
/* This assertion cannot be branch covered in unit tests */
|
|
configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */
|
|
8014608: 697b ldr r3, [r7, #20]
|
|
801460a: 2b50 cmp r3, #80 @ 0x50
|
|
801460c: d00b beq.n 8014626 <xQueueGenericCreateStatic+0x76>
|
|
__asm volatile
|
|
801460e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014612: f383 8811 msr BASEPRI, r3
|
|
8014616: f3bf 8f6f isb sy
|
|
801461a: f3bf 8f4f dsb sy
|
|
801461e: 61fb str r3, [r7, #28]
|
|
}
|
|
8014620: bf00 nop
|
|
8014622: bf00 nop
|
|
8014624: e7fd b.n 8014622 <xQueueGenericCreateStatic+0x72>
|
|
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
|
|
8014626: 697b ldr r3, [r7, #20]
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/* The address of a statically allocated queue was passed in, use it.
|
|
* The address of a statically allocated storage area was also passed in
|
|
* but is already set. */
|
|
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
|
8014628: 683b ldr r3, [r7, #0]
|
|
801462a: 627b str r3, [r7, #36] @ 0x24
|
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
{
|
|
/* Queues can be allocated wither statically or dynamically, so
|
|
* note this queue was allocated statically in case the queue is
|
|
* later deleted. */
|
|
pxNewQueue->ucStaticallyAllocated = pdTRUE;
|
|
801462c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801462e: 2201 movs r2, #1
|
|
8014630: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
|
8014634: f897 2030 ldrb.w r2, [r7, #48] @ 0x30
|
|
8014638: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801463a: 9300 str r3, [sp, #0]
|
|
801463c: 4613 mov r3, r2
|
|
801463e: 687a ldr r2, [r7, #4]
|
|
8014640: 68b9 ldr r1, [r7, #8]
|
|
8014642: 68f8 ldr r0, [r7, #12]
|
|
8014644: f000 f868 bl 8014718 <prvInitialiseNewQueue>
|
|
8014648: e00e b.n 8014668 <xQueueGenericCreateStatic+0xb8>
|
|
}
|
|
else
|
|
{
|
|
configASSERT( pxNewQueue );
|
|
801464a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801464c: 2b00 cmp r3, #0
|
|
801464e: d10b bne.n 8014668 <xQueueGenericCreateStatic+0xb8>
|
|
__asm volatile
|
|
8014650: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014654: f383 8811 msr BASEPRI, r3
|
|
8014658: f3bf 8f6f isb sy
|
|
801465c: f3bf 8f4f dsb sy
|
|
8014660: 61bb str r3, [r7, #24]
|
|
}
|
|
8014662: bf00 nop
|
|
8014664: bf00 nop
|
|
8014666: e7fd b.n 8014664 <xQueueGenericCreateStatic+0xb4>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return pxNewQueue;
|
|
8014668: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
801466a: 4618 mov r0, r3
|
|
801466c: 3728 adds r7, #40 @ 0x28
|
|
801466e: 46bd mov sp, r7
|
|
8014670: bd80 pop {r7, pc}
|
|
|
|
08014672 <xQueueGenericCreate>:
|
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
|
|
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
|
|
const UBaseType_t uxItemSize,
|
|
const uint8_t ucQueueType )
|
|
{
|
|
8014672: b580 push {r7, lr}
|
|
8014674: b08a sub sp, #40 @ 0x28
|
|
8014676: af02 add r7, sp, #8
|
|
8014678: 60f8 str r0, [r7, #12]
|
|
801467a: 60b9 str r1, [r7, #8]
|
|
801467c: 4613 mov r3, r2
|
|
801467e: 71fb strb r3, [r7, #7]
|
|
Queue_t * pxNewQueue = NULL;
|
|
8014680: 2300 movs r3, #0
|
|
8014682: 61fb str r3, [r7, #28]
|
|
size_t xQueueSizeInBytes;
|
|
uint8_t * pucQueueStorage;
|
|
|
|
if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
|
|
8014684: 68fb ldr r3, [r7, #12]
|
|
8014686: 2b00 cmp r3, #0
|
|
8014688: d032 beq.n 80146f0 <xQueueGenericCreate+0x7e>
|
|
/* Check for multiplication overflow. */
|
|
( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
|
|
801468a: 2100 movs r1, #0
|
|
801468c: 68ba ldr r2, [r7, #8]
|
|
801468e: 68fb ldr r3, [r7, #12]
|
|
8014690: fba3 2302 umull r2, r3, r3, r2
|
|
8014694: 2b00 cmp r3, #0
|
|
8014696: d000 beq.n 801469a <xQueueGenericCreate+0x28>
|
|
8014698: 2101 movs r1, #1
|
|
801469a: 460b mov r3, r1
|
|
if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
|
|
801469c: 2b00 cmp r3, #0
|
|
801469e: d127 bne.n 80146f0 <xQueueGenericCreate+0x7e>
|
|
/* Check for addition overflow. */
|
|
( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )
|
|
80146a0: 68fb ldr r3, [r7, #12]
|
|
80146a2: 68ba ldr r2, [r7, #8]
|
|
80146a4: fb02 f303 mul.w r3, r2, r3
|
|
( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
|
|
80146a8: f113 0f51 cmn.w r3, #81 @ 0x51
|
|
80146ac: d820 bhi.n 80146f0 <xQueueGenericCreate+0x7e>
|
|
{
|
|
/* Allocate enough space to hold the maximum number of items that
|
|
* can be in the queue at any time. It is valid for uxItemSize to be
|
|
* zero in the case the queue is used as a semaphore. */
|
|
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
80146ae: 68fb ldr r3, [r7, #12]
|
|
80146b0: 68ba ldr r2, [r7, #8]
|
|
80146b2: fb02 f303 mul.w r3, r2, r3
|
|
80146b6: 61bb str r3, [r7, #24]
|
|
* alignment requirements of the Queue_t structure - which in this case
|
|
* is an int8_t *. Therefore, whenever the stack alignment requirements
|
|
* are greater than or equal to the pointer to char requirements the cast
|
|
* is safe. In other cases alignment requirements are not strict (one or
|
|
* two bytes). */
|
|
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
|
|
80146b8: 69bb ldr r3, [r7, #24]
|
|
80146ba: 3350 adds r3, #80 @ 0x50
|
|
80146bc: 4618 mov r0, r3
|
|
80146be: f003 fc5f bl 8017f80 <pvPortMalloc>
|
|
80146c2: 61f8 str r0, [r7, #28]
|
|
|
|
if( pxNewQueue != NULL )
|
|
80146c4: 69fb ldr r3, [r7, #28]
|
|
80146c6: 2b00 cmp r3, #0
|
|
80146c8: d021 beq.n 801470e <xQueueGenericCreate+0x9c>
|
|
{
|
|
/* Jump past the queue structure to find the location of the queue
|
|
* storage area. */
|
|
pucQueueStorage = ( uint8_t * ) pxNewQueue;
|
|
80146ca: 69fb ldr r3, [r7, #28]
|
|
80146cc: 617b str r3, [r7, #20]
|
|
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
80146ce: 697b ldr r3, [r7, #20]
|
|
80146d0: 3350 adds r3, #80 @ 0x50
|
|
80146d2: 617b str r3, [r7, #20]
|
|
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
/* Queues can be created either statically or dynamically, so
|
|
* note this task was created dynamically in case it is later
|
|
* deleted. */
|
|
pxNewQueue->ucStaticallyAllocated = pdFALSE;
|
|
80146d4: 69fb ldr r3, [r7, #28]
|
|
80146d6: 2200 movs r2, #0
|
|
80146d8: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
}
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
|
80146dc: 79fa ldrb r2, [r7, #7]
|
|
80146de: 69fb ldr r3, [r7, #28]
|
|
80146e0: 9300 str r3, [sp, #0]
|
|
80146e2: 4613 mov r3, r2
|
|
80146e4: 697a ldr r2, [r7, #20]
|
|
80146e6: 68b9 ldr r1, [r7, #8]
|
|
80146e8: 68f8 ldr r0, [r7, #12]
|
|
80146ea: f000 f815 bl 8014718 <prvInitialiseNewQueue>
|
|
if( pxNewQueue != NULL )
|
|
80146ee: e00e b.n 801470e <xQueueGenericCreate+0x9c>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
configASSERT( pxNewQueue );
|
|
80146f0: 69fb ldr r3, [r7, #28]
|
|
80146f2: 2b00 cmp r3, #0
|
|
80146f4: d10b bne.n 801470e <xQueueGenericCreate+0x9c>
|
|
__asm volatile
|
|
80146f6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80146fa: f383 8811 msr BASEPRI, r3
|
|
80146fe: f3bf 8f6f isb sy
|
|
8014702: f3bf 8f4f dsb sy
|
|
8014706: 613b str r3, [r7, #16]
|
|
}
|
|
8014708: bf00 nop
|
|
801470a: bf00 nop
|
|
801470c: e7fd b.n 801470a <xQueueGenericCreate+0x98>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return pxNewQueue;
|
|
801470e: 69fb ldr r3, [r7, #28]
|
|
}
|
|
8014710: 4618 mov r0, r3
|
|
8014712: 3720 adds r7, #32
|
|
8014714: 46bd mov sp, r7
|
|
8014716: bd80 pop {r7, pc}
|
|
|
|
08014718 <prvInitialiseNewQueue>:
|
|
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
|
|
const UBaseType_t uxItemSize,
|
|
uint8_t * pucQueueStorage,
|
|
const uint8_t ucQueueType,
|
|
Queue_t * pxNewQueue )
|
|
{
|
|
8014718: b580 push {r7, lr}
|
|
801471a: b084 sub sp, #16
|
|
801471c: af00 add r7, sp, #0
|
|
801471e: 60f8 str r0, [r7, #12]
|
|
8014720: 60b9 str r1, [r7, #8]
|
|
8014722: 607a str r2, [r7, #4]
|
|
8014724: 70fb strb r3, [r7, #3]
|
|
/* Remove compiler warnings about unused parameters should
|
|
* configUSE_TRACE_FACILITY not be set to 1. */
|
|
( void ) ucQueueType;
|
|
|
|
if( uxItemSize == ( UBaseType_t ) 0 )
|
|
8014726: 68bb ldr r3, [r7, #8]
|
|
8014728: 2b00 cmp r3, #0
|
|
801472a: d103 bne.n 8014734 <prvInitialiseNewQueue+0x1c>
|
|
{
|
|
/* No RAM was allocated for the queue storage area, but PC head cannot
|
|
* be set to NULL because NULL is used as a key to say the queue is used as
|
|
* a mutex. Therefore just set pcHead to point to the queue as a benign
|
|
* value that is known to be within the memory map. */
|
|
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
|
|
801472c: 69bb ldr r3, [r7, #24]
|
|
801472e: 69ba ldr r2, [r7, #24]
|
|
8014730: 601a str r2, [r3, #0]
|
|
8014732: e002 b.n 801473a <prvInitialiseNewQueue+0x22>
|
|
}
|
|
else
|
|
{
|
|
/* Set the head to the start of the queue storage area. */
|
|
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
|
|
8014734: 69bb ldr r3, [r7, #24]
|
|
8014736: 687a ldr r2, [r7, #4]
|
|
8014738: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Initialise the queue members as described where the queue type is
|
|
* defined. */
|
|
pxNewQueue->uxLength = uxQueueLength;
|
|
801473a: 69bb ldr r3, [r7, #24]
|
|
801473c: 68fa ldr r2, [r7, #12]
|
|
801473e: 63da str r2, [r3, #60] @ 0x3c
|
|
pxNewQueue->uxItemSize = uxItemSize;
|
|
8014740: 69bb ldr r3, [r7, #24]
|
|
8014742: 68ba ldr r2, [r7, #8]
|
|
8014744: 641a str r2, [r3, #64] @ 0x40
|
|
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
|
|
8014746: 2101 movs r1, #1
|
|
8014748: 69b8 ldr r0, [r7, #24]
|
|
801474a: f7ff fe9f bl 801448c <xQueueGenericReset>
|
|
|
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
|
{
|
|
pxNewQueue->ucQueueType = ucQueueType;
|
|
801474e: 69bb ldr r3, [r7, #24]
|
|
8014750: 78fa ldrb r2, [r7, #3]
|
|
8014752: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
pxNewQueue->pxQueueSetContainer = NULL;
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
traceQUEUE_CREATE( pxNewQueue );
|
|
}
|
|
8014756: bf00 nop
|
|
8014758: 3710 adds r7, #16
|
|
801475a: 46bd mov sp, r7
|
|
801475c: bd80 pop {r7, pc}
|
|
|
|
0801475e <prvInitialiseMutex>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
static void prvInitialiseMutex( Queue_t * pxNewQueue )
|
|
{
|
|
801475e: b580 push {r7, lr}
|
|
8014760: b082 sub sp, #8
|
|
8014762: af00 add r7, sp, #0
|
|
8014764: 6078 str r0, [r7, #4]
|
|
if( pxNewQueue != NULL )
|
|
8014766: 687b ldr r3, [r7, #4]
|
|
8014768: 2b00 cmp r3, #0
|
|
801476a: d00e beq.n 801478a <prvInitialiseMutex+0x2c>
|
|
{
|
|
/* The queue create function will set all the queue structure members
|
|
* correctly for a generic queue, but this function is creating a
|
|
* mutex. Overwrite those members that need to be set differently -
|
|
* in particular the information required for priority inheritance. */
|
|
pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
|
|
801476c: 687b ldr r3, [r7, #4]
|
|
801476e: 2200 movs r2, #0
|
|
8014770: 609a str r2, [r3, #8]
|
|
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
|
|
8014772: 687b ldr r3, [r7, #4]
|
|
8014774: 2200 movs r2, #0
|
|
8014776: 601a str r2, [r3, #0]
|
|
|
|
/* In case this is a recursive mutex. */
|
|
pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
|
|
8014778: 687b ldr r3, [r7, #4]
|
|
801477a: 2200 movs r2, #0
|
|
801477c: 60da str r2, [r3, #12]
|
|
|
|
traceCREATE_MUTEX( pxNewQueue );
|
|
|
|
/* Start with the semaphore in the expected state. */
|
|
( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
|
|
801477e: 2300 movs r3, #0
|
|
8014780: 2200 movs r2, #0
|
|
8014782: 2100 movs r1, #0
|
|
8014784: 6878 ldr r0, [r7, #4]
|
|
8014786: f000 f905 bl 8014994 <xQueueGenericSend>
|
|
}
|
|
else
|
|
{
|
|
traceCREATE_MUTEX_FAILED();
|
|
}
|
|
}
|
|
801478a: bf00 nop
|
|
801478c: 3708 adds r7, #8
|
|
801478e: 46bd mov sp, r7
|
|
8014790: bd80 pop {r7, pc}
|
|
|
|
08014792 <xQueueCreateMutex>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
|
|
|
|
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
|
|
{
|
|
8014792: b580 push {r7, lr}
|
|
8014794: b086 sub sp, #24
|
|
8014796: af00 add r7, sp, #0
|
|
8014798: 4603 mov r3, r0
|
|
801479a: 71fb strb r3, [r7, #7]
|
|
QueueHandle_t xNewQueue;
|
|
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
|
|
801479c: 2301 movs r3, #1
|
|
801479e: 617b str r3, [r7, #20]
|
|
80147a0: 2300 movs r3, #0
|
|
80147a2: 613b str r3, [r7, #16]
|
|
|
|
xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
|
|
80147a4: 79fb ldrb r3, [r7, #7]
|
|
80147a6: 461a mov r2, r3
|
|
80147a8: 6939 ldr r1, [r7, #16]
|
|
80147aa: 6978 ldr r0, [r7, #20]
|
|
80147ac: f7ff ff61 bl 8014672 <xQueueGenericCreate>
|
|
80147b0: 60f8 str r0, [r7, #12]
|
|
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
|
|
80147b2: 68f8 ldr r0, [r7, #12]
|
|
80147b4: f7ff ffd3 bl 801475e <prvInitialiseMutex>
|
|
|
|
return xNewQueue;
|
|
80147b8: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80147ba: 4618 mov r0, r3
|
|
80147bc: 3718 adds r7, #24
|
|
80147be: 46bd mov sp, r7
|
|
80147c0: bd80 pop {r7, pc}
|
|
|
|
080147c2 <xQueueCreateMutexStatic>:
|
|
|
|
#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
|
|
|
|
QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
|
|
StaticQueue_t * pxStaticQueue )
|
|
{
|
|
80147c2: b580 push {r7, lr}
|
|
80147c4: b088 sub sp, #32
|
|
80147c6: af02 add r7, sp, #8
|
|
80147c8: 4603 mov r3, r0
|
|
80147ca: 6039 str r1, [r7, #0]
|
|
80147cc: 71fb strb r3, [r7, #7]
|
|
QueueHandle_t xNewQueue;
|
|
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
|
|
80147ce: 2301 movs r3, #1
|
|
80147d0: 617b str r3, [r7, #20]
|
|
80147d2: 2300 movs r3, #0
|
|
80147d4: 613b str r3, [r7, #16]
|
|
|
|
/* Prevent compiler warnings about unused parameters if
|
|
* configUSE_TRACE_FACILITY does not equal 1. */
|
|
( void ) ucQueueType;
|
|
|
|
xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
|
|
80147d6: 79fb ldrb r3, [r7, #7]
|
|
80147d8: 9300 str r3, [sp, #0]
|
|
80147da: 683b ldr r3, [r7, #0]
|
|
80147dc: 2200 movs r2, #0
|
|
80147de: 6939 ldr r1, [r7, #16]
|
|
80147e0: 6978 ldr r0, [r7, #20]
|
|
80147e2: f7ff fee5 bl 80145b0 <xQueueGenericCreateStatic>
|
|
80147e6: 60f8 str r0, [r7, #12]
|
|
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
|
|
80147e8: 68f8 ldr r0, [r7, #12]
|
|
80147ea: f7ff ffb8 bl 801475e <prvInitialiseMutex>
|
|
|
|
return xNewQueue;
|
|
80147ee: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80147f0: 4618 mov r0, r3
|
|
80147f2: 3718 adds r7, #24
|
|
80147f4: 46bd mov sp, r7
|
|
80147f6: bd80 pop {r7, pc}
|
|
|
|
080147f8 <xQueueGiveMutexRecursive>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
|
|
|
|
BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
|
|
{
|
|
80147f8: b590 push {r4, r7, lr}
|
|
80147fa: b087 sub sp, #28
|
|
80147fc: af00 add r7, sp, #0
|
|
80147fe: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
Queue_t * const pxMutex = ( Queue_t * ) xMutex;
|
|
8014800: 687b ldr r3, [r7, #4]
|
|
8014802: 613b str r3, [r7, #16]
|
|
|
|
configASSERT( pxMutex );
|
|
8014804: 693b ldr r3, [r7, #16]
|
|
8014806: 2b00 cmp r3, #0
|
|
8014808: d10b bne.n 8014822 <xQueueGiveMutexRecursive+0x2a>
|
|
__asm volatile
|
|
801480a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801480e: f383 8811 msr BASEPRI, r3
|
|
8014812: f3bf 8f6f isb sy
|
|
8014816: f3bf 8f4f dsb sy
|
|
801481a: 60fb str r3, [r7, #12]
|
|
}
|
|
801481c: bf00 nop
|
|
801481e: bf00 nop
|
|
8014820: e7fd b.n 801481e <xQueueGiveMutexRecursive+0x26>
|
|
* change outside of this task. If this task does not hold the mutex then
|
|
* pxMutexHolder can never coincidentally equal the tasks handle, and as
|
|
* this is the only condition we are interested in it does not matter if
|
|
* pxMutexHolder is accessed simultaneously by another task. Therefore no
|
|
* mutual exclusion is required to test the pxMutexHolder variable. */
|
|
if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
|
|
8014822: 693b ldr r3, [r7, #16]
|
|
8014824: 689c ldr r4, [r3, #8]
|
|
8014826: f001 ff6f bl 8016708 <xTaskGetCurrentTaskHandle>
|
|
801482a: 4603 mov r3, r0
|
|
801482c: 429c cmp r4, r3
|
|
801482e: d111 bne.n 8014854 <xQueueGiveMutexRecursive+0x5c>
|
|
/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
|
|
* the task handle, therefore no underflow check is required. Also,
|
|
* uxRecursiveCallCount is only modified by the mutex holder, and as
|
|
* there can only be one, no mutual exclusion is required to modify the
|
|
* uxRecursiveCallCount member. */
|
|
( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
|
|
8014830: 693b ldr r3, [r7, #16]
|
|
8014832: 68db ldr r3, [r3, #12]
|
|
8014834: 1e5a subs r2, r3, #1
|
|
8014836: 693b ldr r3, [r7, #16]
|
|
8014838: 60da str r2, [r3, #12]
|
|
|
|
/* Has the recursive call count unwound to 0? */
|
|
if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
|
|
801483a: 693b ldr r3, [r7, #16]
|
|
801483c: 68db ldr r3, [r3, #12]
|
|
801483e: 2b00 cmp r3, #0
|
|
8014840: d105 bne.n 801484e <xQueueGiveMutexRecursive+0x56>
|
|
{
|
|
/* Return the mutex. This will automatically unblock any other
|
|
* task that might be waiting to access the mutex. */
|
|
( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
|
|
8014842: 2300 movs r3, #0
|
|
8014844: 2200 movs r2, #0
|
|
8014846: 2100 movs r1, #0
|
|
8014848: 6938 ldr r0, [r7, #16]
|
|
801484a: f000 f8a3 bl 8014994 <xQueueGenericSend>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
801484e: 2301 movs r3, #1
|
|
8014850: 617b str r3, [r7, #20]
|
|
8014852: e001 b.n 8014858 <xQueueGiveMutexRecursive+0x60>
|
|
}
|
|
else
|
|
{
|
|
/* The mutex cannot be given because the calling task is not the
|
|
* holder. */
|
|
xReturn = pdFAIL;
|
|
8014854: 2300 movs r3, #0
|
|
8014856: 617b str r3, [r7, #20]
|
|
|
|
traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
|
|
}
|
|
|
|
return xReturn;
|
|
8014858: 697b ldr r3, [r7, #20]
|
|
}
|
|
801485a: 4618 mov r0, r3
|
|
801485c: 371c adds r7, #28
|
|
801485e: 46bd mov sp, r7
|
|
8014860: bd90 pop {r4, r7, pc}
|
|
|
|
08014862 <xQueueTakeMutexRecursive>:
|
|
|
|
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
|
|
|
|
BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
|
|
TickType_t xTicksToWait )
|
|
{
|
|
8014862: b590 push {r4, r7, lr}
|
|
8014864: b087 sub sp, #28
|
|
8014866: af00 add r7, sp, #0
|
|
8014868: 6078 str r0, [r7, #4]
|
|
801486a: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
Queue_t * const pxMutex = ( Queue_t * ) xMutex;
|
|
801486c: 687b ldr r3, [r7, #4]
|
|
801486e: 613b str r3, [r7, #16]
|
|
|
|
configASSERT( pxMutex );
|
|
8014870: 693b ldr r3, [r7, #16]
|
|
8014872: 2b00 cmp r3, #0
|
|
8014874: d10b bne.n 801488e <xQueueTakeMutexRecursive+0x2c>
|
|
__asm volatile
|
|
8014876: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801487a: f383 8811 msr BASEPRI, r3
|
|
801487e: f3bf 8f6f isb sy
|
|
8014882: f3bf 8f4f dsb sy
|
|
8014886: 60fb str r3, [r7, #12]
|
|
}
|
|
8014888: bf00 nop
|
|
801488a: bf00 nop
|
|
801488c: e7fd b.n 801488a <xQueueTakeMutexRecursive+0x28>
|
|
/* Comments regarding mutual exclusion as per those within
|
|
* xQueueGiveMutexRecursive(). */
|
|
|
|
traceTAKE_MUTEX_RECURSIVE( pxMutex );
|
|
|
|
if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
|
|
801488e: 693b ldr r3, [r7, #16]
|
|
8014890: 689c ldr r4, [r3, #8]
|
|
8014892: f001 ff39 bl 8016708 <xTaskGetCurrentTaskHandle>
|
|
8014896: 4603 mov r3, r0
|
|
8014898: 429c cmp r4, r3
|
|
801489a: d107 bne.n 80148ac <xQueueTakeMutexRecursive+0x4a>
|
|
{
|
|
( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
|
|
801489c: 693b ldr r3, [r7, #16]
|
|
801489e: 68db ldr r3, [r3, #12]
|
|
80148a0: 1c5a adds r2, r3, #1
|
|
80148a2: 693b ldr r3, [r7, #16]
|
|
80148a4: 60da str r2, [r3, #12]
|
|
xReturn = pdPASS;
|
|
80148a6: 2301 movs r3, #1
|
|
80148a8: 617b str r3, [r7, #20]
|
|
80148aa: e00c b.n 80148c6 <xQueueTakeMutexRecursive+0x64>
|
|
}
|
|
else
|
|
{
|
|
xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
|
|
80148ac: 6839 ldr r1, [r7, #0]
|
|
80148ae: 6938 ldr r0, [r7, #16]
|
|
80148b0: f000 fbb2 bl 8015018 <xQueueSemaphoreTake>
|
|
80148b4: 6178 str r0, [r7, #20]
|
|
|
|
/* pdPASS will only be returned if the mutex was successfully
|
|
* obtained. The calling task may have entered the Blocked state
|
|
* before reaching here. */
|
|
if( xReturn != pdFAIL )
|
|
80148b6: 697b ldr r3, [r7, #20]
|
|
80148b8: 2b00 cmp r3, #0
|
|
80148ba: d004 beq.n 80148c6 <xQueueTakeMutexRecursive+0x64>
|
|
{
|
|
( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
|
|
80148bc: 693b ldr r3, [r7, #16]
|
|
80148be: 68db ldr r3, [r3, #12]
|
|
80148c0: 1c5a adds r2, r3, #1
|
|
80148c2: 693b ldr r3, [r7, #16]
|
|
80148c4: 60da str r2, [r3, #12]
|
|
{
|
|
traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
|
|
}
|
|
}
|
|
|
|
return xReturn;
|
|
80148c6: 697b ldr r3, [r7, #20]
|
|
}
|
|
80148c8: 4618 mov r0, r3
|
|
80148ca: 371c adds r7, #28
|
|
80148cc: 46bd mov sp, r7
|
|
80148ce: bd90 pop {r4, r7, pc}
|
|
|
|
080148d0 <xQueueCreateCountingSemaphoreStatic>:
|
|
#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
|
|
|
|
QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
|
|
const UBaseType_t uxInitialCount,
|
|
StaticQueue_t * pxStaticQueue )
|
|
{
|
|
80148d0: b580 push {r7, lr}
|
|
80148d2: b088 sub sp, #32
|
|
80148d4: af02 add r7, sp, #8
|
|
80148d6: 60f8 str r0, [r7, #12]
|
|
80148d8: 60b9 str r1, [r7, #8]
|
|
80148da: 607a str r2, [r7, #4]
|
|
QueueHandle_t xHandle = NULL;
|
|
80148dc: 2300 movs r3, #0
|
|
80148de: 617b str r3, [r7, #20]
|
|
|
|
if( ( uxMaxCount != 0 ) &&
|
|
80148e0: 68fb ldr r3, [r7, #12]
|
|
80148e2: 2b00 cmp r3, #0
|
|
80148e4: d013 beq.n 801490e <xQueueCreateCountingSemaphoreStatic+0x3e>
|
|
80148e6: 68ba ldr r2, [r7, #8]
|
|
80148e8: 68fb ldr r3, [r7, #12]
|
|
80148ea: 429a cmp r2, r3
|
|
80148ec: d80f bhi.n 801490e <xQueueCreateCountingSemaphoreStatic+0x3e>
|
|
( uxInitialCount <= uxMaxCount ) )
|
|
{
|
|
xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
|
|
80148ee: 2302 movs r3, #2
|
|
80148f0: 9300 str r3, [sp, #0]
|
|
80148f2: 687b ldr r3, [r7, #4]
|
|
80148f4: 2200 movs r2, #0
|
|
80148f6: 2100 movs r1, #0
|
|
80148f8: 68f8 ldr r0, [r7, #12]
|
|
80148fa: f7ff fe59 bl 80145b0 <xQueueGenericCreateStatic>
|
|
80148fe: 6178 str r0, [r7, #20]
|
|
|
|
if( xHandle != NULL )
|
|
8014900: 697b ldr r3, [r7, #20]
|
|
8014902: 2b00 cmp r3, #0
|
|
8014904: d012 beq.n 801492c <xQueueCreateCountingSemaphoreStatic+0x5c>
|
|
{
|
|
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
|
|
8014906: 697b ldr r3, [r7, #20]
|
|
8014908: 68ba ldr r2, [r7, #8]
|
|
801490a: 639a str r2, [r3, #56] @ 0x38
|
|
if( xHandle != NULL )
|
|
801490c: e00e b.n 801492c <xQueueCreateCountingSemaphoreStatic+0x5c>
|
|
traceCREATE_COUNTING_SEMAPHORE_FAILED();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
configASSERT( xHandle );
|
|
801490e: 697b ldr r3, [r7, #20]
|
|
8014910: 2b00 cmp r3, #0
|
|
8014912: d10b bne.n 801492c <xQueueCreateCountingSemaphoreStatic+0x5c>
|
|
__asm volatile
|
|
8014914: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014918: f383 8811 msr BASEPRI, r3
|
|
801491c: f3bf 8f6f isb sy
|
|
8014920: f3bf 8f4f dsb sy
|
|
8014924: 613b str r3, [r7, #16]
|
|
}
|
|
8014926: bf00 nop
|
|
8014928: bf00 nop
|
|
801492a: e7fd b.n 8014928 <xQueueCreateCountingSemaphoreStatic+0x58>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xHandle;
|
|
801492c: 697b ldr r3, [r7, #20]
|
|
}
|
|
801492e: 4618 mov r0, r3
|
|
8014930: 3718 adds r7, #24
|
|
8014932: 46bd mov sp, r7
|
|
8014934: bd80 pop {r7, pc}
|
|
|
|
08014936 <xQueueCreateCountingSemaphore>:
|
|
|
|
#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
|
|
|
|
QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
|
|
const UBaseType_t uxInitialCount )
|
|
{
|
|
8014936: b580 push {r7, lr}
|
|
8014938: b084 sub sp, #16
|
|
801493a: af00 add r7, sp, #0
|
|
801493c: 6078 str r0, [r7, #4]
|
|
801493e: 6039 str r1, [r7, #0]
|
|
QueueHandle_t xHandle = NULL;
|
|
8014940: 2300 movs r3, #0
|
|
8014942: 60fb str r3, [r7, #12]
|
|
|
|
if( ( uxMaxCount != 0 ) &&
|
|
8014944: 687b ldr r3, [r7, #4]
|
|
8014946: 2b00 cmp r3, #0
|
|
8014948: d010 beq.n 801496c <xQueueCreateCountingSemaphore+0x36>
|
|
801494a: 683a ldr r2, [r7, #0]
|
|
801494c: 687b ldr r3, [r7, #4]
|
|
801494e: 429a cmp r2, r3
|
|
8014950: d80c bhi.n 801496c <xQueueCreateCountingSemaphore+0x36>
|
|
( uxInitialCount <= uxMaxCount ) )
|
|
{
|
|
xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
|
|
8014952: 2202 movs r2, #2
|
|
8014954: 2100 movs r1, #0
|
|
8014956: 6878 ldr r0, [r7, #4]
|
|
8014958: f7ff fe8b bl 8014672 <xQueueGenericCreate>
|
|
801495c: 60f8 str r0, [r7, #12]
|
|
|
|
if( xHandle != NULL )
|
|
801495e: 68fb ldr r3, [r7, #12]
|
|
8014960: 2b00 cmp r3, #0
|
|
8014962: d012 beq.n 801498a <xQueueCreateCountingSemaphore+0x54>
|
|
{
|
|
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
|
|
8014964: 68fb ldr r3, [r7, #12]
|
|
8014966: 683a ldr r2, [r7, #0]
|
|
8014968: 639a str r2, [r3, #56] @ 0x38
|
|
if( xHandle != NULL )
|
|
801496a: e00e b.n 801498a <xQueueCreateCountingSemaphore+0x54>
|
|
traceCREATE_COUNTING_SEMAPHORE_FAILED();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
configASSERT( xHandle );
|
|
801496c: 68fb ldr r3, [r7, #12]
|
|
801496e: 2b00 cmp r3, #0
|
|
8014970: d10b bne.n 801498a <xQueueCreateCountingSemaphore+0x54>
|
|
__asm volatile
|
|
8014972: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014976: f383 8811 msr BASEPRI, r3
|
|
801497a: f3bf 8f6f isb sy
|
|
801497e: f3bf 8f4f dsb sy
|
|
8014982: 60bb str r3, [r7, #8]
|
|
}
|
|
8014984: bf00 nop
|
|
8014986: bf00 nop
|
|
8014988: e7fd b.n 8014986 <xQueueCreateCountingSemaphore+0x50>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xHandle;
|
|
801498a: 68fb ldr r3, [r7, #12]
|
|
}
|
|
801498c: 4618 mov r0, r3
|
|
801498e: 3710 adds r7, #16
|
|
8014990: 46bd mov sp, r7
|
|
8014992: bd80 pop {r7, pc}
|
|
|
|
08014994 <xQueueGenericSend>:
|
|
|
|
BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
|
|
const void * const pvItemToQueue,
|
|
TickType_t xTicksToWait,
|
|
const BaseType_t xCopyPosition )
|
|
{
|
|
8014994: b580 push {r7, lr}
|
|
8014996: b08e sub sp, #56 @ 0x38
|
|
8014998: af00 add r7, sp, #0
|
|
801499a: 60f8 str r0, [r7, #12]
|
|
801499c: 60b9 str r1, [r7, #8]
|
|
801499e: 607a str r2, [r7, #4]
|
|
80149a0: 603b str r3, [r7, #0]
|
|
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
|
|
80149a2: 2300 movs r3, #0
|
|
80149a4: 637b str r3, [r7, #52] @ 0x34
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
80149a6: 68fb ldr r3, [r7, #12]
|
|
80149a8: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
configASSERT( pxQueue );
|
|
80149aa: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80149ac: 2b00 cmp r3, #0
|
|
80149ae: d10b bne.n 80149c8 <xQueueGenericSend+0x34>
|
|
__asm volatile
|
|
80149b0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80149b4: f383 8811 msr BASEPRI, r3
|
|
80149b8: f3bf 8f6f isb sy
|
|
80149bc: f3bf 8f4f dsb sy
|
|
80149c0: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
80149c2: bf00 nop
|
|
80149c4: bf00 nop
|
|
80149c6: e7fd b.n 80149c4 <xQueueGenericSend+0x30>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
80149c8: 68bb ldr r3, [r7, #8]
|
|
80149ca: 2b00 cmp r3, #0
|
|
80149cc: d103 bne.n 80149d6 <xQueueGenericSend+0x42>
|
|
80149ce: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80149d0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80149d2: 2b00 cmp r3, #0
|
|
80149d4: d101 bne.n 80149da <xQueueGenericSend+0x46>
|
|
80149d6: 2301 movs r3, #1
|
|
80149d8: e000 b.n 80149dc <xQueueGenericSend+0x48>
|
|
80149da: 2300 movs r3, #0
|
|
80149dc: 2b00 cmp r3, #0
|
|
80149de: d10b bne.n 80149f8 <xQueueGenericSend+0x64>
|
|
__asm volatile
|
|
80149e0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80149e4: f383 8811 msr BASEPRI, r3
|
|
80149e8: f3bf 8f6f isb sy
|
|
80149ec: f3bf 8f4f dsb sy
|
|
80149f0: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
80149f2: bf00 nop
|
|
80149f4: bf00 nop
|
|
80149f6: e7fd b.n 80149f4 <xQueueGenericSend+0x60>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
80149f8: 683b ldr r3, [r7, #0]
|
|
80149fa: 2b02 cmp r3, #2
|
|
80149fc: d103 bne.n 8014a06 <xQueueGenericSend+0x72>
|
|
80149fe: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014a00: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8014a02: 2b01 cmp r3, #1
|
|
8014a04: d101 bne.n 8014a0a <xQueueGenericSend+0x76>
|
|
8014a06: 2301 movs r3, #1
|
|
8014a08: e000 b.n 8014a0c <xQueueGenericSend+0x78>
|
|
8014a0a: 2300 movs r3, #0
|
|
8014a0c: 2b00 cmp r3, #0
|
|
8014a0e: d10b bne.n 8014a28 <xQueueGenericSend+0x94>
|
|
__asm volatile
|
|
8014a10: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014a14: f383 8811 msr BASEPRI, r3
|
|
8014a18: f3bf 8f6f isb sy
|
|
8014a1c: f3bf 8f4f dsb sy
|
|
8014a20: 623b str r3, [r7, #32]
|
|
}
|
|
8014a22: bf00 nop
|
|
8014a24: bf00 nop
|
|
8014a26: e7fd b.n 8014a24 <xQueueGenericSend+0x90>
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
8014a28: f001 fe7e bl 8016728 <xTaskGetSchedulerState>
|
|
8014a2c: 4603 mov r3, r0
|
|
8014a2e: 2b00 cmp r3, #0
|
|
8014a30: d102 bne.n 8014a38 <xQueueGenericSend+0xa4>
|
|
8014a32: 687b ldr r3, [r7, #4]
|
|
8014a34: 2b00 cmp r3, #0
|
|
8014a36: d101 bne.n 8014a3c <xQueueGenericSend+0xa8>
|
|
8014a38: 2301 movs r3, #1
|
|
8014a3a: e000 b.n 8014a3e <xQueueGenericSend+0xaa>
|
|
8014a3c: 2300 movs r3, #0
|
|
8014a3e: 2b00 cmp r3, #0
|
|
8014a40: d10b bne.n 8014a5a <xQueueGenericSend+0xc6>
|
|
__asm volatile
|
|
8014a42: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014a46: f383 8811 msr BASEPRI, r3
|
|
8014a4a: f3bf 8f6f isb sy
|
|
8014a4e: f3bf 8f4f dsb sy
|
|
8014a52: 61fb str r3, [r7, #28]
|
|
}
|
|
8014a54: bf00 nop
|
|
8014a56: bf00 nop
|
|
8014a58: e7fd b.n 8014a56 <xQueueGenericSend+0xc2>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
* allow return statements within the function itself. This is done in the
|
|
* interest of execution time efficiency. */
|
|
for( ; ; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
8014a5a: f003 f969 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
/* Is there room on the queue now? The running task must be the
|
|
* highest priority task wanting to access the queue. If the head item
|
|
* in the queue is to be overwritten then it does not matter if the
|
|
* queue is full. */
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
8014a5e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014a60: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8014a62: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014a64: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8014a66: 429a cmp r2, r3
|
|
8014a68: d302 bcc.n 8014a70 <xQueueGenericSend+0xdc>
|
|
8014a6a: 683b ldr r3, [r7, #0]
|
|
8014a6c: 2b02 cmp r3, #2
|
|
8014a6e: d129 bne.n 8014ac4 <xQueueGenericSend+0x130>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
8014a70: 683a ldr r2, [r7, #0]
|
|
8014a72: 68b9 ldr r1, [r7, #8]
|
|
8014a74: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8014a76: f000 fca5 bl 80153c4 <prvCopyDataToQueue>
|
|
8014a7a: 62f8 str r0, [r7, #44] @ 0x2c
|
|
|
|
/* If there was a task waiting for data to arrive on the
|
|
* queue then unblock it now. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
8014a7c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014a7e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8014a80: 2b00 cmp r3, #0
|
|
8014a82: d010 beq.n 8014aa6 <xQueueGenericSend+0x112>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
8014a84: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014a86: 3324 adds r3, #36 @ 0x24
|
|
8014a88: 4618 mov r0, r3
|
|
8014a8a: f001 fc01 bl 8016290 <xTaskRemoveFromEventList>
|
|
8014a8e: 4603 mov r3, r0
|
|
8014a90: 2b00 cmp r3, #0
|
|
8014a92: d013 beq.n 8014abc <xQueueGenericSend+0x128>
|
|
{
|
|
/* The unblocked task has a priority higher than
|
|
* our own so yield immediately. Yes it is ok to do
|
|
* this from within the critical section - the kernel
|
|
* takes care of that. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
8014a94: 4b3f ldr r3, [pc, #252] @ (8014b94 <xQueueGenericSend+0x200>)
|
|
8014a96: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8014a9a: 601a str r2, [r3, #0]
|
|
8014a9c: f3bf 8f4f dsb sy
|
|
8014aa0: f3bf 8f6f isb sy
|
|
8014aa4: e00a b.n 8014abc <xQueueGenericSend+0x128>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else if( xYieldRequired != pdFALSE )
|
|
8014aa6: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8014aa8: 2b00 cmp r3, #0
|
|
8014aaa: d007 beq.n 8014abc <xQueueGenericSend+0x128>
|
|
{
|
|
/* This path is a special case that will only get
|
|
* executed if the task was holding multiple mutexes and
|
|
* the mutexes were given back in an order that is
|
|
* different to that in which they were taken. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
8014aac: 4b39 ldr r3, [pc, #228] @ (8014b94 <xQueueGenericSend+0x200>)
|
|
8014aae: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8014ab2: 601a str r2, [r3, #0]
|
|
8014ab4: f3bf 8f4f dsb sy
|
|
8014ab8: f3bf 8f6f isb sy
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
taskEXIT_CRITICAL();
|
|
8014abc: f003 f96a bl 8017d94 <vPortExitCritical>
|
|
return pdPASS;
|
|
8014ac0: 2301 movs r3, #1
|
|
8014ac2: e063 b.n 8014b8c <xQueueGenericSend+0x1f8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
8014ac4: 687b ldr r3, [r7, #4]
|
|
8014ac6: 2b00 cmp r3, #0
|
|
8014ac8: d103 bne.n 8014ad2 <xQueueGenericSend+0x13e>
|
|
{
|
|
/* The queue was full and no block time is specified (or
|
|
* the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
8014aca: f003 f963 bl 8017d94 <vPortExitCritical>
|
|
|
|
/* Return to the original privilege level before exiting
|
|
* the function. */
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
8014ace: 2300 movs r3, #0
|
|
8014ad0: e05c b.n 8014b8c <xQueueGenericSend+0x1f8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
8014ad2: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8014ad4: 2b00 cmp r3, #0
|
|
8014ad6: d106 bne.n 8014ae6 <xQueueGenericSend+0x152>
|
|
{
|
|
/* The queue was full and a block time was specified so
|
|
* configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
8014ad8: f107 0314 add.w r3, r7, #20
|
|
8014adc: 4618 mov r0, r3
|
|
8014ade: f001 fcaf bl 8016440 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
8014ae2: 2301 movs r3, #1
|
|
8014ae4: 637b str r3, [r7, #52] @ 0x34
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8014ae6: f003 f955 bl 8017d94 <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
* now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
8014aea: f001 f89b bl 8015c24 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
8014aee: f003 f91f bl 8017d30 <vPortEnterCritical>
|
|
8014af2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014af4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
8014af8: b25b sxtb r3, r3
|
|
8014afa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8014afe: d103 bne.n 8014b08 <xQueueGenericSend+0x174>
|
|
8014b00: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014b02: 2200 movs r2, #0
|
|
8014b04: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8014b08: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014b0a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
8014b0e: b25b sxtb r3, r3
|
|
8014b10: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8014b14: d103 bne.n 8014b1e <xQueueGenericSend+0x18a>
|
|
8014b16: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014b18: 2200 movs r2, #0
|
|
8014b1a: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
8014b1e: f003 f939 bl 8017d94 <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
8014b22: 1d3a adds r2, r7, #4
|
|
8014b24: f107 0314 add.w r3, r7, #20
|
|
8014b28: 4611 mov r1, r2
|
|
8014b2a: 4618 mov r0, r3
|
|
8014b2c: f001 fc9e bl 801646c <xTaskCheckForTimeOut>
|
|
8014b30: 4603 mov r3, r0
|
|
8014b32: 2b00 cmp r3, #0
|
|
8014b34: d124 bne.n 8014b80 <xQueueGenericSend+0x1ec>
|
|
{
|
|
if( prvIsQueueFull( pxQueue ) != pdFALSE )
|
|
8014b36: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8014b38: f000 fd3c bl 80155b4 <prvIsQueueFull>
|
|
8014b3c: 4603 mov r3, r0
|
|
8014b3e: 2b00 cmp r3, #0
|
|
8014b40: d018 beq.n 8014b74 <xQueueGenericSend+0x1e0>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
|
|
8014b42: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014b44: 3310 adds r3, #16
|
|
8014b46: 687a ldr r2, [r7, #4]
|
|
8014b48: 4611 mov r1, r2
|
|
8014b4a: 4618 mov r0, r3
|
|
8014b4c: f001 fb34 bl 80161b8 <vTaskPlaceOnEventList>
|
|
/* Unlocking the queue means queue events can effect the
|
|
* event list. It is possible that interrupts occurring now
|
|
* remove this task from the event list again - but as the
|
|
* scheduler is suspended the task will go onto the pending
|
|
* ready list instead of the actual ready list. */
|
|
prvUnlockQueue( pxQueue );
|
|
8014b50: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8014b52: f000 fcc7 bl 80154e4 <prvUnlockQueue>
|
|
/* Resuming the scheduler will move tasks from the pending
|
|
* ready list into the ready list - so it is feasible that this
|
|
* task is already in the ready list before it yields - in which
|
|
* case the yield will not cause a context switch unless there
|
|
* is also a higher priority task in the pending ready list. */
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
8014b56: f001 f873 bl 8015c40 <xTaskResumeAll>
|
|
8014b5a: 4603 mov r3, r0
|
|
8014b5c: 2b00 cmp r3, #0
|
|
8014b5e: f47f af7c bne.w 8014a5a <xQueueGenericSend+0xc6>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
8014b62: 4b0c ldr r3, [pc, #48] @ (8014b94 <xQueueGenericSend+0x200>)
|
|
8014b64: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8014b68: 601a str r2, [r3, #0]
|
|
8014b6a: f3bf 8f4f dsb sy
|
|
8014b6e: f3bf 8f6f isb sy
|
|
8014b72: e772 b.n 8014a5a <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Try again. */
|
|
prvUnlockQueue( pxQueue );
|
|
8014b74: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8014b76: f000 fcb5 bl 80154e4 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
8014b7a: f001 f861 bl 8015c40 <xTaskResumeAll>
|
|
8014b7e: e76c b.n 8014a5a <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* The timeout has expired. */
|
|
prvUnlockQueue( pxQueue );
|
|
8014b80: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8014b82: f000 fcaf bl 80154e4 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
8014b86: f001 f85b bl 8015c40 <xTaskResumeAll>
|
|
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
8014b8a: 2300 movs r3, #0
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
8014b8c: 4618 mov r0, r3
|
|
8014b8e: 3738 adds r7, #56 @ 0x38
|
|
8014b90: 46bd mov sp, r7
|
|
8014b92: bd80 pop {r7, pc}
|
|
8014b94: e000ed04 .word 0xe000ed04
|
|
|
|
08014b98 <xQueueGenericSendFromISR>:
|
|
|
|
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
|
|
const void * const pvItemToQueue,
|
|
BaseType_t * const pxHigherPriorityTaskWoken,
|
|
const BaseType_t xCopyPosition )
|
|
{
|
|
8014b98: b580 push {r7, lr}
|
|
8014b9a: b092 sub sp, #72 @ 0x48
|
|
8014b9c: af00 add r7, sp, #0
|
|
8014b9e: 60f8 str r0, [r7, #12]
|
|
8014ba0: 60b9 str r1, [r7, #8]
|
|
8014ba2: 607a str r2, [r7, #4]
|
|
8014ba4: 603b str r3, [r7, #0]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
8014ba6: 68fb ldr r3, [r7, #12]
|
|
8014ba8: 643b str r3, [r7, #64] @ 0x40
|
|
|
|
configASSERT( pxQueue );
|
|
8014baa: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014bac: 2b00 cmp r3, #0
|
|
8014bae: d10b bne.n 8014bc8 <xQueueGenericSendFromISR+0x30>
|
|
__asm volatile
|
|
8014bb0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014bb4: f383 8811 msr BASEPRI, r3
|
|
8014bb8: f3bf 8f6f isb sy
|
|
8014bbc: f3bf 8f4f dsb sy
|
|
8014bc0: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
8014bc2: bf00 nop
|
|
8014bc4: bf00 nop
|
|
8014bc6: e7fd b.n 8014bc4 <xQueueGenericSendFromISR+0x2c>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
8014bc8: 68bb ldr r3, [r7, #8]
|
|
8014bca: 2b00 cmp r3, #0
|
|
8014bcc: d103 bne.n 8014bd6 <xQueueGenericSendFromISR+0x3e>
|
|
8014bce: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014bd0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8014bd2: 2b00 cmp r3, #0
|
|
8014bd4: d101 bne.n 8014bda <xQueueGenericSendFromISR+0x42>
|
|
8014bd6: 2301 movs r3, #1
|
|
8014bd8: e000 b.n 8014bdc <xQueueGenericSendFromISR+0x44>
|
|
8014bda: 2300 movs r3, #0
|
|
8014bdc: 2b00 cmp r3, #0
|
|
8014bde: d10b bne.n 8014bf8 <xQueueGenericSendFromISR+0x60>
|
|
__asm volatile
|
|
8014be0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014be4: f383 8811 msr BASEPRI, r3
|
|
8014be8: f3bf 8f6f isb sy
|
|
8014bec: f3bf 8f4f dsb sy
|
|
8014bf0: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
8014bf2: bf00 nop
|
|
8014bf4: bf00 nop
|
|
8014bf6: e7fd b.n 8014bf4 <xQueueGenericSendFromISR+0x5c>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
8014bf8: 683b ldr r3, [r7, #0]
|
|
8014bfa: 2b02 cmp r3, #2
|
|
8014bfc: d103 bne.n 8014c06 <xQueueGenericSendFromISR+0x6e>
|
|
8014bfe: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014c00: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8014c02: 2b01 cmp r3, #1
|
|
8014c04: d101 bne.n 8014c0a <xQueueGenericSendFromISR+0x72>
|
|
8014c06: 2301 movs r3, #1
|
|
8014c08: e000 b.n 8014c0c <xQueueGenericSendFromISR+0x74>
|
|
8014c0a: 2300 movs r3, #0
|
|
8014c0c: 2b00 cmp r3, #0
|
|
8014c0e: d10b bne.n 8014c28 <xQueueGenericSendFromISR+0x90>
|
|
__asm volatile
|
|
8014c10: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014c14: f383 8811 msr BASEPRI, r3
|
|
8014c18: f3bf 8f6f isb sy
|
|
8014c1c: f3bf 8f4f dsb sy
|
|
8014c20: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
8014c22: bf00 nop
|
|
8014c24: bf00 nop
|
|
8014c26: e7fd b.n 8014c24 <xQueueGenericSendFromISR+0x8c>
|
|
* that have been assigned a priority at or (logically) below the maximum
|
|
* system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
* safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
* More information (albeit Cortex-M specific) is provided on the following
|
|
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
8014c28: f003 f968 bl 8017efc <vPortValidateInterruptPriority>
|
|
|
|
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
8014c2c: f3ef 8211 mrs r2, BASEPRI
|
|
8014c30: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014c34: f383 8811 msr BASEPRI, r3
|
|
8014c38: f3bf 8f6f isb sy
|
|
8014c3c: f3bf 8f4f dsb sy
|
|
8014c40: 623a str r2, [r7, #32]
|
|
8014c42: 61fb str r3, [r7, #28]
|
|
: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
|
|
/* This return will not be reached but is necessary to prevent compiler
|
|
* warnings. */
|
|
return ulOriginalBASEPRI;
|
|
8014c44: 6a3b ldr r3, [r7, #32]
|
|
/* Similar to xQueueGenericSend, except without blocking if there is no room
|
|
* in the queue. Also don't directly wake a task that was blocked on a queue
|
|
* read, instead return a flag to say whether a context switch is required or
|
|
* not (i.e. has a task with a higher priority than us been woken by this
|
|
* post). */
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
8014c46: 63fb str r3, [r7, #60] @ 0x3c
|
|
{
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
8014c48: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014c4a: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8014c4c: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014c4e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8014c50: 429a cmp r2, r3
|
|
8014c52: d302 bcc.n 8014c5a <xQueueGenericSendFromISR+0xc2>
|
|
8014c54: 683b ldr r3, [r7, #0]
|
|
8014c56: 2b02 cmp r3, #2
|
|
8014c58: d147 bne.n 8014cea <xQueueGenericSendFromISR+0x152>
|
|
{
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
|
8014c5a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014c5c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
8014c60: f887 303b strb.w r3, [r7, #59] @ 0x3b
|
|
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
8014c64: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014c66: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8014c68: 637b str r3, [r7, #52] @ 0x34
|
|
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
|
|
* semaphore or mutex. That means prvCopyDataToQueue() cannot result
|
|
* in a task disinheriting a priority and prvCopyDataToQueue() can be
|
|
* called here even though the disinherit function does not check if
|
|
* the scheduler is suspended before accessing the ready lists. */
|
|
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
8014c6a: 683a ldr r2, [r7, #0]
|
|
8014c6c: 68b9 ldr r1, [r7, #8]
|
|
8014c6e: 6c38 ldr r0, [r7, #64] @ 0x40
|
|
8014c70: f000 fba8 bl 80153c4 <prvCopyDataToQueue>
|
|
|
|
/* The event list is not altered if the queue is locked. This will
|
|
* be done when the queue is unlocked later. */
|
|
if( cTxLock == queueUNLOCKED )
|
|
8014c74: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b
|
|
8014c78: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8014c7c: d112 bne.n 8014ca4 <xQueueGenericSendFromISR+0x10c>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
8014c7e: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014c80: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8014c82: 2b00 cmp r3, #0
|
|
8014c84: d02e beq.n 8014ce4 <xQueueGenericSendFromISR+0x14c>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
8014c86: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014c88: 3324 adds r3, #36 @ 0x24
|
|
8014c8a: 4618 mov r0, r3
|
|
8014c8c: f001 fb00 bl 8016290 <xTaskRemoveFromEventList>
|
|
8014c90: 4603 mov r3, r0
|
|
8014c92: 2b00 cmp r3, #0
|
|
8014c94: d026 beq.n 8014ce4 <xQueueGenericSendFromISR+0x14c>
|
|
{
|
|
/* The task waiting has a higher priority so record that a
|
|
* context switch is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
8014c96: 687b ldr r3, [r7, #4]
|
|
8014c98: 2b00 cmp r3, #0
|
|
8014c9a: d023 beq.n 8014ce4 <xQueueGenericSendFromISR+0x14c>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
8014c9c: 687b ldr r3, [r7, #4]
|
|
8014c9e: 2201 movs r2, #1
|
|
8014ca0: 601a str r2, [r3, #0]
|
|
8014ca2: e01f b.n 8014ce4 <xQueueGenericSendFromISR+0x14c>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
* knows that data was posted while it was locked. */
|
|
prvIncrementQueueTxLock( pxQueue, cTxLock );
|
|
8014ca4: f001 f8da bl 8015e5c <uxTaskGetNumberOfTasks>
|
|
8014ca8: 6338 str r0, [r7, #48] @ 0x30
|
|
8014caa: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b
|
|
8014cae: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8014cb0: 429a cmp r2, r3
|
|
8014cb2: d917 bls.n 8014ce4 <xQueueGenericSendFromISR+0x14c>
|
|
8014cb4: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b
|
|
8014cb8: 2b7f cmp r3, #127 @ 0x7f
|
|
8014cba: d10b bne.n 8014cd4 <xQueueGenericSendFromISR+0x13c>
|
|
__asm volatile
|
|
8014cbc: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014cc0: f383 8811 msr BASEPRI, r3
|
|
8014cc4: f3bf 8f6f isb sy
|
|
8014cc8: f3bf 8f4f dsb sy
|
|
8014ccc: 61bb str r3, [r7, #24]
|
|
}
|
|
8014cce: bf00 nop
|
|
8014cd0: bf00 nop
|
|
8014cd2: e7fd b.n 8014cd0 <xQueueGenericSendFromISR+0x138>
|
|
8014cd4: f897 303b ldrb.w r3, [r7, #59] @ 0x3b
|
|
8014cd8: 3301 adds r3, #1
|
|
8014cda: b2db uxtb r3, r3
|
|
8014cdc: b25a sxtb r2, r3
|
|
8014cde: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8014ce0: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
8014ce4: 2301 movs r3, #1
|
|
8014ce6: 647b str r3, [r7, #68] @ 0x44
|
|
{
|
|
8014ce8: e001 b.n 8014cee <xQueueGenericSendFromISR+0x156>
|
|
}
|
|
else
|
|
{
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
|
xReturn = errQUEUE_FULL;
|
|
8014cea: 2300 movs r3, #0
|
|
8014cec: 647b str r3, [r7, #68] @ 0x44
|
|
8014cee: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8014cf0: 617b str r3, [r7, #20]
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
|
{
|
|
__asm volatile
|
|
8014cf2: 697b ldr r3, [r7, #20]
|
|
8014cf4: f383 8811 msr BASEPRI, r3
|
|
(
|
|
" msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
|
|
);
|
|
}
|
|
8014cf8: bf00 nop
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
8014cfa: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
}
|
|
8014cfc: 4618 mov r0, r3
|
|
8014cfe: 3748 adds r7, #72 @ 0x48
|
|
8014d00: 46bd mov sp, r7
|
|
8014d02: bd80 pop {r7, pc}
|
|
|
|
08014d04 <xQueueGiveFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
|
|
BaseType_t * const pxHigherPriorityTaskWoken )
|
|
{
|
|
8014d04: b580 push {r7, lr}
|
|
8014d06: b090 sub sp, #64 @ 0x40
|
|
8014d08: af00 add r7, sp, #0
|
|
8014d0a: 6078 str r0, [r7, #4]
|
|
8014d0c: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
8014d0e: 687b ldr r3, [r7, #4]
|
|
8014d10: 63bb str r3, [r7, #56] @ 0x38
|
|
* item size is 0. Don't directly wake a task that was blocked on a queue
|
|
* read, instead return a flag to say whether a context switch is required or
|
|
* not (i.e. has a task with a higher priority than us been woken by this
|
|
* post). */
|
|
|
|
configASSERT( pxQueue );
|
|
8014d12: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014d14: 2b00 cmp r3, #0
|
|
8014d16: d10b bne.n 8014d30 <xQueueGiveFromISR+0x2c>
|
|
__asm volatile
|
|
8014d18: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014d1c: f383 8811 msr BASEPRI, r3
|
|
8014d20: f3bf 8f6f isb sy
|
|
8014d24: f3bf 8f4f dsb sy
|
|
8014d28: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
8014d2a: bf00 nop
|
|
8014d2c: bf00 nop
|
|
8014d2e: e7fd b.n 8014d2c <xQueueGiveFromISR+0x28>
|
|
|
|
/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
|
|
* if the item size is not 0. */
|
|
configASSERT( pxQueue->uxItemSize == 0 );
|
|
8014d30: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014d32: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8014d34: 2b00 cmp r3, #0
|
|
8014d36: d00b beq.n 8014d50 <xQueueGiveFromISR+0x4c>
|
|
__asm volatile
|
|
8014d38: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014d3c: f383 8811 msr BASEPRI, r3
|
|
8014d40: f3bf 8f6f isb sy
|
|
8014d44: f3bf 8f4f dsb sy
|
|
8014d48: 623b str r3, [r7, #32]
|
|
}
|
|
8014d4a: bf00 nop
|
|
8014d4c: bf00 nop
|
|
8014d4e: e7fd b.n 8014d4c <xQueueGiveFromISR+0x48>
|
|
|
|
/* Normally a mutex would not be given from an interrupt, especially if
|
|
* there is a mutex holder, as priority inheritance makes no sense for an
|
|
* interrupts, only tasks. */
|
|
configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
|
|
8014d50: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014d52: 681b ldr r3, [r3, #0]
|
|
8014d54: 2b00 cmp r3, #0
|
|
8014d56: d103 bne.n 8014d60 <xQueueGiveFromISR+0x5c>
|
|
8014d58: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014d5a: 689b ldr r3, [r3, #8]
|
|
8014d5c: 2b00 cmp r3, #0
|
|
8014d5e: d101 bne.n 8014d64 <xQueueGiveFromISR+0x60>
|
|
8014d60: 2301 movs r3, #1
|
|
8014d62: e000 b.n 8014d66 <xQueueGiveFromISR+0x62>
|
|
8014d64: 2300 movs r3, #0
|
|
8014d66: 2b00 cmp r3, #0
|
|
8014d68: d10b bne.n 8014d82 <xQueueGiveFromISR+0x7e>
|
|
__asm volatile
|
|
8014d6a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014d6e: f383 8811 msr BASEPRI, r3
|
|
8014d72: f3bf 8f6f isb sy
|
|
8014d76: f3bf 8f4f dsb sy
|
|
8014d7a: 61fb str r3, [r7, #28]
|
|
}
|
|
8014d7c: bf00 nop
|
|
8014d7e: bf00 nop
|
|
8014d80: e7fd b.n 8014d7e <xQueueGiveFromISR+0x7a>
|
|
* that have been assigned a priority at or (logically) below the maximum
|
|
* system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
* safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
* More information (albeit Cortex-M specific) is provided on the following
|
|
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
8014d82: f003 f8bb bl 8017efc <vPortValidateInterruptPriority>
|
|
__asm volatile
|
|
8014d86: f3ef 8211 mrs r2, BASEPRI
|
|
8014d8a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014d8e: f383 8811 msr BASEPRI, r3
|
|
8014d92: f3bf 8f6f isb sy
|
|
8014d96: f3bf 8f4f dsb sy
|
|
8014d9a: 61ba str r2, [r7, #24]
|
|
8014d9c: 617b str r3, [r7, #20]
|
|
return ulOriginalBASEPRI;
|
|
8014d9e: 69bb ldr r3, [r7, #24]
|
|
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
8014da0: 637b str r3, [r7, #52] @ 0x34
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
8014da2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014da4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8014da6: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
/* When the queue is used to implement a semaphore no data is ever
|
|
* moved through the queue but it is still valid to see if the queue 'has
|
|
* space'. */
|
|
if( uxMessagesWaiting < pxQueue->uxLength )
|
|
8014da8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014daa: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8014dac: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8014dae: 429a cmp r2, r3
|
|
8014db0: d243 bcs.n 8014e3a <xQueueGiveFromISR+0x136>
|
|
{
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
|
8014db2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014db4: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
8014db8: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
* holder - and if there is a mutex holder then the mutex cannot be
|
|
* given from an ISR. As this is the ISR version of the function it
|
|
* can be assumed there is no mutex holder and no need to determine if
|
|
* priority disinheritance is needed. Simply increase the count of
|
|
* messages (semaphores) available. */
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
|
8014dbc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8014dbe: 1c5a adds r2, r3, #1
|
|
8014dc0: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014dc2: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* The event list is not altered if the queue is locked. This will
|
|
* be done when the queue is unlocked later. */
|
|
if( cTxLock == queueUNLOCKED )
|
|
8014dc4: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
|
|
8014dc8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8014dcc: d112 bne.n 8014df4 <xQueueGiveFromISR+0xf0>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
8014dce: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014dd0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8014dd2: 2b00 cmp r3, #0
|
|
8014dd4: d02e beq.n 8014e34 <xQueueGiveFromISR+0x130>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
8014dd6: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014dd8: 3324 adds r3, #36 @ 0x24
|
|
8014dda: 4618 mov r0, r3
|
|
8014ddc: f001 fa58 bl 8016290 <xTaskRemoveFromEventList>
|
|
8014de0: 4603 mov r3, r0
|
|
8014de2: 2b00 cmp r3, #0
|
|
8014de4: d026 beq.n 8014e34 <xQueueGiveFromISR+0x130>
|
|
{
|
|
/* The task waiting has a higher priority so record that a
|
|
* context switch is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
8014de6: 683b ldr r3, [r7, #0]
|
|
8014de8: 2b00 cmp r3, #0
|
|
8014dea: d023 beq.n 8014e34 <xQueueGiveFromISR+0x130>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
8014dec: 683b ldr r3, [r7, #0]
|
|
8014dee: 2201 movs r2, #1
|
|
8014df0: 601a str r2, [r3, #0]
|
|
8014df2: e01f b.n 8014e34 <xQueueGiveFromISR+0x130>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
* knows that data was posted while it was locked. */
|
|
prvIncrementQueueTxLock( pxQueue, cTxLock );
|
|
8014df4: f001 f832 bl 8015e5c <uxTaskGetNumberOfTasks>
|
|
8014df8: 62b8 str r0, [r7, #40] @ 0x28
|
|
8014dfa: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
|
|
8014dfe: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8014e00: 429a cmp r2, r3
|
|
8014e02: d917 bls.n 8014e34 <xQueueGiveFromISR+0x130>
|
|
8014e04: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
|
|
8014e08: 2b7f cmp r3, #127 @ 0x7f
|
|
8014e0a: d10b bne.n 8014e24 <xQueueGiveFromISR+0x120>
|
|
__asm volatile
|
|
8014e0c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014e10: f383 8811 msr BASEPRI, r3
|
|
8014e14: f3bf 8f6f isb sy
|
|
8014e18: f3bf 8f4f dsb sy
|
|
8014e1c: 613b str r3, [r7, #16]
|
|
}
|
|
8014e1e: bf00 nop
|
|
8014e20: bf00 nop
|
|
8014e22: e7fd b.n 8014e20 <xQueueGiveFromISR+0x11c>
|
|
8014e24: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
8014e28: 3301 adds r3, #1
|
|
8014e2a: b2db uxtb r3, r3
|
|
8014e2c: b25a sxtb r2, r3
|
|
8014e2e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8014e30: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
8014e34: 2301 movs r3, #1
|
|
8014e36: 63fb str r3, [r7, #60] @ 0x3c
|
|
8014e38: e001 b.n 8014e3e <xQueueGiveFromISR+0x13a>
|
|
}
|
|
else
|
|
{
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
|
xReturn = errQUEUE_FULL;
|
|
8014e3a: 2300 movs r3, #0
|
|
8014e3c: 63fb str r3, [r7, #60] @ 0x3c
|
|
8014e3e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8014e40: 60fb str r3, [r7, #12]
|
|
__asm volatile
|
|
8014e42: 68fb ldr r3, [r7, #12]
|
|
8014e44: f383 8811 msr BASEPRI, r3
|
|
}
|
|
8014e48: bf00 nop
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
8014e4a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
}
|
|
8014e4c: 4618 mov r0, r3
|
|
8014e4e: 3740 adds r7, #64 @ 0x40
|
|
8014e50: 46bd mov sp, r7
|
|
8014e52: bd80 pop {r7, pc}
|
|
|
|
08014e54 <xQueueReceive>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueReceive( QueueHandle_t xQueue,
|
|
void * const pvBuffer,
|
|
TickType_t xTicksToWait )
|
|
{
|
|
8014e54: b580 push {r7, lr}
|
|
8014e56: b08c sub sp, #48 @ 0x30
|
|
8014e58: af00 add r7, sp, #0
|
|
8014e5a: 60f8 str r0, [r7, #12]
|
|
8014e5c: 60b9 str r1, [r7, #8]
|
|
8014e5e: 607a str r2, [r7, #4]
|
|
BaseType_t xEntryTimeSet = pdFALSE;
|
|
8014e60: 2300 movs r3, #0
|
|
8014e62: 62fb str r3, [r7, #44] @ 0x2c
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
8014e64: 68fb ldr r3, [r7, #12]
|
|
8014e66: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check the pointer is not NULL. */
|
|
configASSERT( ( pxQueue ) );
|
|
8014e68: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014e6a: 2b00 cmp r3, #0
|
|
8014e6c: d10b bne.n 8014e86 <xQueueReceive+0x32>
|
|
__asm volatile
|
|
8014e6e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014e72: f383 8811 msr BASEPRI, r3
|
|
8014e76: f3bf 8f6f isb sy
|
|
8014e7a: f3bf 8f4f dsb sy
|
|
8014e7e: 623b str r3, [r7, #32]
|
|
}
|
|
8014e80: bf00 nop
|
|
8014e82: bf00 nop
|
|
8014e84: e7fd b.n 8014e82 <xQueueReceive+0x2e>
|
|
|
|
/* The buffer into which data is received can only be NULL if the data size
|
|
* is zero (so no data is copied into the buffer). */
|
|
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
8014e86: 68bb ldr r3, [r7, #8]
|
|
8014e88: 2b00 cmp r3, #0
|
|
8014e8a: d103 bne.n 8014e94 <xQueueReceive+0x40>
|
|
8014e8c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014e8e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8014e90: 2b00 cmp r3, #0
|
|
8014e92: d101 bne.n 8014e98 <xQueueReceive+0x44>
|
|
8014e94: 2301 movs r3, #1
|
|
8014e96: e000 b.n 8014e9a <xQueueReceive+0x46>
|
|
8014e98: 2300 movs r3, #0
|
|
8014e9a: 2b00 cmp r3, #0
|
|
8014e9c: d10b bne.n 8014eb6 <xQueueReceive+0x62>
|
|
__asm volatile
|
|
8014e9e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014ea2: f383 8811 msr BASEPRI, r3
|
|
8014ea6: f3bf 8f6f isb sy
|
|
8014eaa: f3bf 8f4f dsb sy
|
|
8014eae: 61fb str r3, [r7, #28]
|
|
}
|
|
8014eb0: bf00 nop
|
|
8014eb2: bf00 nop
|
|
8014eb4: e7fd b.n 8014eb2 <xQueueReceive+0x5e>
|
|
|
|
/* Cannot block if the scheduler is suspended. */
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
8014eb6: f001 fc37 bl 8016728 <xTaskGetSchedulerState>
|
|
8014eba: 4603 mov r3, r0
|
|
8014ebc: 2b00 cmp r3, #0
|
|
8014ebe: d102 bne.n 8014ec6 <xQueueReceive+0x72>
|
|
8014ec0: 687b ldr r3, [r7, #4]
|
|
8014ec2: 2b00 cmp r3, #0
|
|
8014ec4: d101 bne.n 8014eca <xQueueReceive+0x76>
|
|
8014ec6: 2301 movs r3, #1
|
|
8014ec8: e000 b.n 8014ecc <xQueueReceive+0x78>
|
|
8014eca: 2300 movs r3, #0
|
|
8014ecc: 2b00 cmp r3, #0
|
|
8014ece: d10b bne.n 8014ee8 <xQueueReceive+0x94>
|
|
__asm volatile
|
|
8014ed0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8014ed4: f383 8811 msr BASEPRI, r3
|
|
8014ed8: f3bf 8f6f isb sy
|
|
8014edc: f3bf 8f4f dsb sy
|
|
8014ee0: 61bb str r3, [r7, #24]
|
|
}
|
|
8014ee2: bf00 nop
|
|
8014ee4: bf00 nop
|
|
8014ee6: e7fd b.n 8014ee4 <xQueueReceive+0x90>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
* allow return statements within the function itself. This is done in the
|
|
* interest of execution time efficiency. */
|
|
for( ; ; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
8014ee8: f002 ff22 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
8014eec: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014eee: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8014ef0: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Is there data in the queue now? To be running the calling task
|
|
* must be the highest priority task wanting to access the queue. */
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
8014ef2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8014ef4: 2b00 cmp r3, #0
|
|
8014ef6: d01f beq.n 8014f38 <xQueueReceive+0xe4>
|
|
{
|
|
/* Data available, remove one item. */
|
|
prvCopyDataFromQueue( pxQueue, pvBuffer );
|
|
8014ef8: 68b9 ldr r1, [r7, #8]
|
|
8014efa: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
8014efc: f000 facc bl 8015498 <prvCopyDataFromQueue>
|
|
traceQUEUE_RECEIVE( pxQueue );
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
|
|
8014f00: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8014f02: 1e5a subs r2, r3, #1
|
|
8014f04: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014f06: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* There is now space in the queue, were any tasks waiting to
|
|
* post to the queue? If so, unblock the highest priority waiting
|
|
* task. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
8014f08: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014f0a: 691b ldr r3, [r3, #16]
|
|
8014f0c: 2b00 cmp r3, #0
|
|
8014f0e: d00f beq.n 8014f30 <xQueueReceive+0xdc>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
8014f10: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014f12: 3310 adds r3, #16
|
|
8014f14: 4618 mov r0, r3
|
|
8014f16: f001 f9bb bl 8016290 <xTaskRemoveFromEventList>
|
|
8014f1a: 4603 mov r3, r0
|
|
8014f1c: 2b00 cmp r3, #0
|
|
8014f1e: d007 beq.n 8014f30 <xQueueReceive+0xdc>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
8014f20: 4b3c ldr r3, [pc, #240] @ (8015014 <xQueueReceive+0x1c0>)
|
|
8014f22: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8014f26: 601a str r2, [r3, #0]
|
|
8014f28: f3bf 8f4f dsb sy
|
|
8014f2c: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
taskEXIT_CRITICAL();
|
|
8014f30: f002 ff30 bl 8017d94 <vPortExitCritical>
|
|
return pdPASS;
|
|
8014f34: 2301 movs r3, #1
|
|
8014f36: e069 b.n 801500c <xQueueReceive+0x1b8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
8014f38: 687b ldr r3, [r7, #4]
|
|
8014f3a: 2b00 cmp r3, #0
|
|
8014f3c: d103 bne.n 8014f46 <xQueueReceive+0xf2>
|
|
{
|
|
/* The queue was empty and no block time is specified (or
|
|
* the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
8014f3e: f002 ff29 bl 8017d94 <vPortExitCritical>
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
8014f42: 2300 movs r3, #0
|
|
8014f44: e062 b.n 801500c <xQueueReceive+0x1b8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
8014f46: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8014f48: 2b00 cmp r3, #0
|
|
8014f4a: d106 bne.n 8014f5a <xQueueReceive+0x106>
|
|
{
|
|
/* The queue was empty and a block time was specified so
|
|
* configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
8014f4c: f107 0310 add.w r3, r7, #16
|
|
8014f50: 4618 mov r0, r3
|
|
8014f52: f001 fa75 bl 8016440 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
8014f56: 2301 movs r3, #1
|
|
8014f58: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8014f5a: f002 ff1b bl 8017d94 <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
* now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
8014f5e: f000 fe61 bl 8015c24 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
8014f62: f002 fee5 bl 8017d30 <vPortEnterCritical>
|
|
8014f66: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014f68: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
8014f6c: b25b sxtb r3, r3
|
|
8014f6e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8014f72: d103 bne.n 8014f7c <xQueueReceive+0x128>
|
|
8014f74: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014f76: 2200 movs r2, #0
|
|
8014f78: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8014f7c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014f7e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
8014f82: b25b sxtb r3, r3
|
|
8014f84: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8014f88: d103 bne.n 8014f92 <xQueueReceive+0x13e>
|
|
8014f8a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014f8c: 2200 movs r2, #0
|
|
8014f8e: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
8014f92: f002 feff bl 8017d94 <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
8014f96: 1d3a adds r2, r7, #4
|
|
8014f98: f107 0310 add.w r3, r7, #16
|
|
8014f9c: 4611 mov r1, r2
|
|
8014f9e: 4618 mov r0, r3
|
|
8014fa0: f001 fa64 bl 801646c <xTaskCheckForTimeOut>
|
|
8014fa4: 4603 mov r3, r0
|
|
8014fa6: 2b00 cmp r3, #0
|
|
8014fa8: d123 bne.n 8014ff2 <xQueueReceive+0x19e>
|
|
{
|
|
/* The timeout has not expired. If the queue is still empty place
|
|
* the task on the list of tasks waiting to receive from the queue. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
8014faa: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
8014fac: f000 faec bl 8015588 <prvIsQueueEmpty>
|
|
8014fb0: 4603 mov r3, r0
|
|
8014fb2: 2b00 cmp r3, #0
|
|
8014fb4: d017 beq.n 8014fe6 <xQueueReceive+0x192>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
|
|
8014fb6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8014fb8: 3324 adds r3, #36 @ 0x24
|
|
8014fba: 687a ldr r2, [r7, #4]
|
|
8014fbc: 4611 mov r1, r2
|
|
8014fbe: 4618 mov r0, r3
|
|
8014fc0: f001 f8fa bl 80161b8 <vTaskPlaceOnEventList>
|
|
prvUnlockQueue( pxQueue );
|
|
8014fc4: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
8014fc6: f000 fa8d bl 80154e4 <prvUnlockQueue>
|
|
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
8014fca: f000 fe39 bl 8015c40 <xTaskResumeAll>
|
|
8014fce: 4603 mov r3, r0
|
|
8014fd0: 2b00 cmp r3, #0
|
|
8014fd2: d189 bne.n 8014ee8 <xQueueReceive+0x94>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
8014fd4: 4b0f ldr r3, [pc, #60] @ (8015014 <xQueueReceive+0x1c0>)
|
|
8014fd6: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8014fda: 601a str r2, [r3, #0]
|
|
8014fdc: f3bf 8f4f dsb sy
|
|
8014fe0: f3bf 8f6f isb sy
|
|
8014fe4: e780 b.n 8014ee8 <xQueueReceive+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* The queue contains data again. Loop back to try and read the
|
|
* data. */
|
|
prvUnlockQueue( pxQueue );
|
|
8014fe6: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
8014fe8: f000 fa7c bl 80154e4 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
8014fec: f000 fe28 bl 8015c40 <xTaskResumeAll>
|
|
8014ff0: e77a b.n 8014ee8 <xQueueReceive+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* Timed out. If there is no data in the queue exit, otherwise loop
|
|
* back and attempt to read the data. */
|
|
prvUnlockQueue( pxQueue );
|
|
8014ff2: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
8014ff4: f000 fa76 bl 80154e4 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
8014ff8: f000 fe22 bl 8015c40 <xTaskResumeAll>
|
|
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
8014ffc: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
8014ffe: f000 fac3 bl 8015588 <prvIsQueueEmpty>
|
|
8015002: 4603 mov r3, r0
|
|
8015004: 2b00 cmp r3, #0
|
|
8015006: f43f af6f beq.w 8014ee8 <xQueueReceive+0x94>
|
|
{
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
801500a: 2300 movs r3, #0
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
801500c: 4618 mov r0, r3
|
|
801500e: 3730 adds r7, #48 @ 0x30
|
|
8015010: 46bd mov sp, r7
|
|
8015012: bd80 pop {r7, pc}
|
|
8015014: e000ed04 .word 0xe000ed04
|
|
|
|
08015018 <xQueueSemaphoreTake>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
|
|
TickType_t xTicksToWait )
|
|
{
|
|
8015018: b580 push {r7, lr}
|
|
801501a: b08c sub sp, #48 @ 0x30
|
|
801501c: af00 add r7, sp, #0
|
|
801501e: 6078 str r0, [r7, #4]
|
|
8015020: 6039 str r1, [r7, #0]
|
|
BaseType_t xEntryTimeSet = pdFALSE;
|
|
8015022: 2300 movs r3, #0
|
|
8015024: 62fb str r3, [r7, #44] @ 0x2c
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
8015026: 687b ldr r3, [r7, #4]
|
|
8015028: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
BaseType_t xInheritanceOccurred = pdFALSE;
|
|
801502a: 2300 movs r3, #0
|
|
801502c: 62bb str r3, [r7, #40] @ 0x28
|
|
#endif
|
|
|
|
/* Check the queue pointer is not NULL. */
|
|
configASSERT( ( pxQueue ) );
|
|
801502e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8015030: 2b00 cmp r3, #0
|
|
8015032: d10b bne.n 801504c <xQueueSemaphoreTake+0x34>
|
|
__asm volatile
|
|
8015034: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015038: f383 8811 msr BASEPRI, r3
|
|
801503c: f3bf 8f6f isb sy
|
|
8015040: f3bf 8f4f dsb sy
|
|
8015044: 61bb str r3, [r7, #24]
|
|
}
|
|
8015046: bf00 nop
|
|
8015048: bf00 nop
|
|
801504a: e7fd b.n 8015048 <xQueueSemaphoreTake+0x30>
|
|
|
|
/* Check this really is a semaphore, in which case the item size will be
|
|
* 0. */
|
|
configASSERT( pxQueue->uxItemSize == 0 );
|
|
801504c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801504e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8015050: 2b00 cmp r3, #0
|
|
8015052: d00b beq.n 801506c <xQueueSemaphoreTake+0x54>
|
|
__asm volatile
|
|
8015054: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015058: f383 8811 msr BASEPRI, r3
|
|
801505c: f3bf 8f6f isb sy
|
|
8015060: f3bf 8f4f dsb sy
|
|
8015064: 617b str r3, [r7, #20]
|
|
}
|
|
8015066: bf00 nop
|
|
8015068: bf00 nop
|
|
801506a: e7fd b.n 8015068 <xQueueSemaphoreTake+0x50>
|
|
|
|
/* Cannot block if the scheduler is suspended. */
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
801506c: f001 fb5c bl 8016728 <xTaskGetSchedulerState>
|
|
8015070: 4603 mov r3, r0
|
|
8015072: 2b00 cmp r3, #0
|
|
8015074: d102 bne.n 801507c <xQueueSemaphoreTake+0x64>
|
|
8015076: 683b ldr r3, [r7, #0]
|
|
8015078: 2b00 cmp r3, #0
|
|
801507a: d101 bne.n 8015080 <xQueueSemaphoreTake+0x68>
|
|
801507c: 2301 movs r3, #1
|
|
801507e: e000 b.n 8015082 <xQueueSemaphoreTake+0x6a>
|
|
8015080: 2300 movs r3, #0
|
|
8015082: 2b00 cmp r3, #0
|
|
8015084: d10b bne.n 801509e <xQueueSemaphoreTake+0x86>
|
|
__asm volatile
|
|
8015086: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801508a: f383 8811 msr BASEPRI, r3
|
|
801508e: f3bf 8f6f isb sy
|
|
8015092: f3bf 8f4f dsb sy
|
|
8015096: 613b str r3, [r7, #16]
|
|
}
|
|
8015098: bf00 nop
|
|
801509a: bf00 nop
|
|
801509c: e7fd b.n 801509a <xQueueSemaphoreTake+0x82>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
|
|
* statements within the function itself. This is done in the interest
|
|
* of execution time efficiency. */
|
|
for( ; ; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
801509e: f002 fe47 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
/* Semaphores are queues with an item size of 0, and where the
|
|
* number of messages in the queue is the semaphore's count value. */
|
|
const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
|
|
80150a2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80150a4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80150a6: 623b str r3, [r7, #32]
|
|
|
|
/* Is there data in the queue now? To be running the calling task
|
|
* must be the highest priority task wanting to access the queue. */
|
|
if( uxSemaphoreCount > ( UBaseType_t ) 0 )
|
|
80150a8: 6a3b ldr r3, [r7, #32]
|
|
80150aa: 2b00 cmp r3, #0
|
|
80150ac: d024 beq.n 80150f8 <xQueueSemaphoreTake+0xe0>
|
|
{
|
|
traceQUEUE_RECEIVE( pxQueue );
|
|
|
|
/* Semaphores are queues with a data size of zero and where the
|
|
* messages waiting is the semaphore's count. Reduce the count. */
|
|
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
|
|
80150ae: 6a3b ldr r3, [r7, #32]
|
|
80150b0: 1e5a subs r2, r3, #1
|
|
80150b2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80150b4: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
80150b6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80150b8: 681b ldr r3, [r3, #0]
|
|
80150ba: 2b00 cmp r3, #0
|
|
80150bc: d104 bne.n 80150c8 <xQueueSemaphoreTake+0xb0>
|
|
{
|
|
/* Record the information required to implement
|
|
* priority inheritance should it become necessary. */
|
|
pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
|
|
80150be: f001 fd25 bl 8016b0c <pvTaskIncrementMutexHeldCount>
|
|
80150c2: 4602 mov r2, r0
|
|
80150c4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80150c6: 609a str r2, [r3, #8]
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
/* Check to see if other tasks are blocked waiting to give the
|
|
* semaphore, and if so, unblock the highest priority such task. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
80150c8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80150ca: 691b ldr r3, [r3, #16]
|
|
80150cc: 2b00 cmp r3, #0
|
|
80150ce: d00f beq.n 80150f0 <xQueueSemaphoreTake+0xd8>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
80150d0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80150d2: 3310 adds r3, #16
|
|
80150d4: 4618 mov r0, r3
|
|
80150d6: f001 f8db bl 8016290 <xTaskRemoveFromEventList>
|
|
80150da: 4603 mov r3, r0
|
|
80150dc: 2b00 cmp r3, #0
|
|
80150de: d007 beq.n 80150f0 <xQueueSemaphoreTake+0xd8>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
80150e0: 4b4c ldr r3, [pc, #304] @ (8015214 <xQueueSemaphoreTake+0x1fc>)
|
|
80150e2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80150e6: 601a str r2, [r3, #0]
|
|
80150e8: f3bf 8f4f dsb sy
|
|
80150ec: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
taskEXIT_CRITICAL();
|
|
80150f0: f002 fe50 bl 8017d94 <vPortExitCritical>
|
|
return pdPASS;
|
|
80150f4: 2301 movs r3, #1
|
|
80150f6: e089 b.n 801520c <xQueueSemaphoreTake+0x1f4>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
80150f8: 683b ldr r3, [r7, #0]
|
|
80150fa: 2b00 cmp r3, #0
|
|
80150fc: d103 bne.n 8015106 <xQueueSemaphoreTake+0xee>
|
|
{
|
|
/* The semaphore count was 0 and no block time is specified
|
|
* (or the block time has expired) so exit now. */
|
|
taskEXIT_CRITICAL();
|
|
80150fe: f002 fe49 bl 8017d94 <vPortExitCritical>
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
8015102: 2300 movs r3, #0
|
|
8015104: e082 b.n 801520c <xQueueSemaphoreTake+0x1f4>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
8015106: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8015108: 2b00 cmp r3, #0
|
|
801510a: d106 bne.n 801511a <xQueueSemaphoreTake+0x102>
|
|
{
|
|
/* The semaphore count was 0 and a block time was specified
|
|
* so configure the timeout structure ready to block. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
801510c: f107 0308 add.w r3, r7, #8
|
|
8015110: 4618 mov r0, r3
|
|
8015112: f001 f995 bl 8016440 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
8015116: 2301 movs r3, #1
|
|
8015118: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
801511a: f002 fe3b bl 8017d94 <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can give to and take from the semaphore
|
|
* now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
801511e: f000 fd81 bl 8015c24 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
8015122: f002 fe05 bl 8017d30 <vPortEnterCritical>
|
|
8015126: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8015128: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
801512c: b25b sxtb r3, r3
|
|
801512e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8015132: d103 bne.n 801513c <xQueueSemaphoreTake+0x124>
|
|
8015134: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8015136: 2200 movs r2, #0
|
|
8015138: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
801513c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801513e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
8015142: b25b sxtb r3, r3
|
|
8015144: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8015148: d103 bne.n 8015152 <xQueueSemaphoreTake+0x13a>
|
|
801514a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801514c: 2200 movs r2, #0
|
|
801514e: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
8015152: f002 fe1f bl 8017d94 <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
8015156: 463a mov r2, r7
|
|
8015158: f107 0308 add.w r3, r7, #8
|
|
801515c: 4611 mov r1, r2
|
|
801515e: 4618 mov r0, r3
|
|
8015160: f001 f984 bl 801646c <xTaskCheckForTimeOut>
|
|
8015164: 4603 mov r3, r0
|
|
8015166: 2b00 cmp r3, #0
|
|
8015168: d132 bne.n 80151d0 <xQueueSemaphoreTake+0x1b8>
|
|
{
|
|
/* A block time is specified and not expired. If the semaphore
|
|
* count is 0 then enter the Blocked state to wait for a semaphore to
|
|
* become available. As semaphores are implemented with queues the
|
|
* queue being empty is equivalent to the semaphore count being 0. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
801516a: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
801516c: f000 fa0c bl 8015588 <prvIsQueueEmpty>
|
|
8015170: 4603 mov r3, r0
|
|
8015172: 2b00 cmp r3, #0
|
|
8015174: d026 beq.n 80151c4 <xQueueSemaphoreTake+0x1ac>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
8015176: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8015178: 681b ldr r3, [r3, #0]
|
|
801517a: 2b00 cmp r3, #0
|
|
801517c: d109 bne.n 8015192 <xQueueSemaphoreTake+0x17a>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
801517e: f002 fdd7 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
|
|
8015182: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8015184: 689b ldr r3, [r3, #8]
|
|
8015186: 4618 mov r0, r3
|
|
8015188: f001 faec bl 8016764 <xTaskPriorityInherit>
|
|
801518c: 62b8 str r0, [r7, #40] @ 0x28
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
801518e: f002 fe01 bl 8017d94 <vPortExitCritical>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* if ( configUSE_MUTEXES == 1 ) */
|
|
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
|
|
8015192: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8015194: 3324 adds r3, #36 @ 0x24
|
|
8015196: 683a ldr r2, [r7, #0]
|
|
8015198: 4611 mov r1, r2
|
|
801519a: 4618 mov r0, r3
|
|
801519c: f001 f80c bl 80161b8 <vTaskPlaceOnEventList>
|
|
prvUnlockQueue( pxQueue );
|
|
80151a0: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
80151a2: f000 f99f bl 80154e4 <prvUnlockQueue>
|
|
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
80151a6: f000 fd4b bl 8015c40 <xTaskResumeAll>
|
|
80151aa: 4603 mov r3, r0
|
|
80151ac: 2b00 cmp r3, #0
|
|
80151ae: f47f af76 bne.w 801509e <xQueueSemaphoreTake+0x86>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
80151b2: 4b18 ldr r3, [pc, #96] @ (8015214 <xQueueSemaphoreTake+0x1fc>)
|
|
80151b4: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80151b8: 601a str r2, [r3, #0]
|
|
80151ba: f3bf 8f4f dsb sy
|
|
80151be: f3bf 8f6f isb sy
|
|
80151c2: e76c b.n 801509e <xQueueSemaphoreTake+0x86>
|
|
}
|
|
else
|
|
{
|
|
/* There was no timeout and the semaphore count was not 0, so
|
|
* attempt to take the semaphore again. */
|
|
prvUnlockQueue( pxQueue );
|
|
80151c4: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
80151c6: f000 f98d bl 80154e4 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
80151ca: f000 fd39 bl 8015c40 <xTaskResumeAll>
|
|
80151ce: e766 b.n 801509e <xQueueSemaphoreTake+0x86>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Timed out. */
|
|
prvUnlockQueue( pxQueue );
|
|
80151d0: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
80151d2: f000 f987 bl 80154e4 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
80151d6: f000 fd33 bl 8015c40 <xTaskResumeAll>
|
|
|
|
/* If the semaphore count is 0 exit now as the timeout has
|
|
* expired. Otherwise return to attempt to take the semaphore that is
|
|
* known to be available. As semaphores are implemented by queues the
|
|
* queue being empty is equivalent to the semaphore count being 0. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
80151da: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
80151dc: f000 f9d4 bl 8015588 <prvIsQueueEmpty>
|
|
80151e0: 4603 mov r3, r0
|
|
80151e2: 2b00 cmp r3, #0
|
|
80151e4: f43f af5b beq.w 801509e <xQueueSemaphoreTake+0x86>
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
/* xInheritanceOccurred could only have be set if
|
|
* pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
|
|
* test the mutex type again to check it is actually a mutex. */
|
|
if( xInheritanceOccurred != pdFALSE )
|
|
80151e8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80151ea: 2b00 cmp r3, #0
|
|
80151ec: d00d beq.n 801520a <xQueueSemaphoreTake+0x1f2>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
80151ee: f002 fd9f bl 8017d30 <vPortEnterCritical>
|
|
/* This task blocking on the mutex caused another
|
|
* task to inherit this task's priority. Now this task
|
|
* has timed out the priority should be disinherited
|
|
* again, but only as low as the next highest priority
|
|
* task that is waiting for the same mutex. */
|
|
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
|
|
80151f2: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
80151f4: f000 f8ce bl 8015394 <prvGetDisinheritPriorityAfterTimeout>
|
|
80151f8: 61f8 str r0, [r7, #28]
|
|
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
|
|
80151fa: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80151fc: 689b ldr r3, [r3, #8]
|
|
80151fe: 69f9 ldr r1, [r7, #28]
|
|
8015200: 4618 mov r0, r3
|
|
8015202: f001 fbd7 bl 80169b4 <vTaskPriorityDisinheritAfterTimeout>
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8015206: f002 fdc5 bl 8017d94 <vPortExitCritical>
|
|
}
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
801520a: 2300 movs r3, #0
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
801520c: 4618 mov r0, r3
|
|
801520e: 3730 adds r7, #48 @ 0x30
|
|
8015210: 46bd mov sp, r7
|
|
8015212: bd80 pop {r7, pc}
|
|
8015214: e000ed04 .word 0xe000ed04
|
|
|
|
08015218 <xQueueReceiveFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
|
|
void * const pvBuffer,
|
|
BaseType_t * const pxHigherPriorityTaskWoken )
|
|
{
|
|
8015218: b580 push {r7, lr}
|
|
801521a: b090 sub sp, #64 @ 0x40
|
|
801521c: af00 add r7, sp, #0
|
|
801521e: 60f8 str r0, [r7, #12]
|
|
8015220: 60b9 str r1, [r7, #8]
|
|
8015222: 607a str r2, [r7, #4]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
8015224: 68fb ldr r3, [r7, #12]
|
|
8015226: 63bb str r3, [r7, #56] @ 0x38
|
|
|
|
configASSERT( pxQueue );
|
|
8015228: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
801522a: 2b00 cmp r3, #0
|
|
801522c: d10b bne.n 8015246 <xQueueReceiveFromISR+0x2e>
|
|
__asm volatile
|
|
801522e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015232: f383 8811 msr BASEPRI, r3
|
|
8015236: f3bf 8f6f isb sy
|
|
801523a: f3bf 8f4f dsb sy
|
|
801523e: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
8015240: bf00 nop
|
|
8015242: bf00 nop
|
|
8015244: e7fd b.n 8015242 <xQueueReceiveFromISR+0x2a>
|
|
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
8015246: 68bb ldr r3, [r7, #8]
|
|
8015248: 2b00 cmp r3, #0
|
|
801524a: d103 bne.n 8015254 <xQueueReceiveFromISR+0x3c>
|
|
801524c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
801524e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8015250: 2b00 cmp r3, #0
|
|
8015252: d101 bne.n 8015258 <xQueueReceiveFromISR+0x40>
|
|
8015254: 2301 movs r3, #1
|
|
8015256: e000 b.n 801525a <xQueueReceiveFromISR+0x42>
|
|
8015258: 2300 movs r3, #0
|
|
801525a: 2b00 cmp r3, #0
|
|
801525c: d10b bne.n 8015276 <xQueueReceiveFromISR+0x5e>
|
|
__asm volatile
|
|
801525e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015262: f383 8811 msr BASEPRI, r3
|
|
8015266: f3bf 8f6f isb sy
|
|
801526a: f3bf 8f4f dsb sy
|
|
801526e: 623b str r3, [r7, #32]
|
|
}
|
|
8015270: bf00 nop
|
|
8015272: bf00 nop
|
|
8015274: e7fd b.n 8015272 <xQueueReceiveFromISR+0x5a>
|
|
* that have been assigned a priority at or (logically) below the maximum
|
|
* system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
* safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
* More information (albeit Cortex-M specific) is provided on the following
|
|
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
8015276: f002 fe41 bl 8017efc <vPortValidateInterruptPriority>
|
|
__asm volatile
|
|
801527a: f3ef 8211 mrs r2, BASEPRI
|
|
801527e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015282: f383 8811 msr BASEPRI, r3
|
|
8015286: f3bf 8f6f isb sy
|
|
801528a: f3bf 8f4f dsb sy
|
|
801528e: 61fa str r2, [r7, #28]
|
|
8015290: 61bb str r3, [r7, #24]
|
|
return ulOriginalBASEPRI;
|
|
8015292: 69fb ldr r3, [r7, #28]
|
|
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
8015294: 637b str r3, [r7, #52] @ 0x34
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
8015296: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8015298: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
801529a: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
/* Cannot block in an ISR, so check there is data available. */
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
801529c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
801529e: 2b00 cmp r3, #0
|
|
80152a0: d047 beq.n 8015332 <xQueueReceiveFromISR+0x11a>
|
|
{
|
|
const int8_t cRxLock = pxQueue->cRxLock;
|
|
80152a2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80152a4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
80152a8: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
|
|
|
|
prvCopyDataFromQueue( pxQueue, pvBuffer );
|
|
80152ac: 68b9 ldr r1, [r7, #8]
|
|
80152ae: 6bb8 ldr r0, [r7, #56] @ 0x38
|
|
80152b0: f000 f8f2 bl 8015498 <prvCopyDataFromQueue>
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
|
|
80152b4: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80152b6: 1e5a subs r2, r3, #1
|
|
80152b8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80152ba: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* If the queue is locked the event list will not be modified.
|
|
* Instead update the lock count so the task that unlocks the queue
|
|
* will know that an ISR has removed data while the queue was
|
|
* locked. */
|
|
if( cRxLock == queueUNLOCKED )
|
|
80152bc: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
|
|
80152c0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
80152c4: d112 bne.n 80152ec <xQueueReceiveFromISR+0xd4>
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
80152c6: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80152c8: 691b ldr r3, [r3, #16]
|
|
80152ca: 2b00 cmp r3, #0
|
|
80152cc: d02e beq.n 801532c <xQueueReceiveFromISR+0x114>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
80152ce: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80152d0: 3310 adds r3, #16
|
|
80152d2: 4618 mov r0, r3
|
|
80152d4: f000 ffdc bl 8016290 <xTaskRemoveFromEventList>
|
|
80152d8: 4603 mov r3, r0
|
|
80152da: 2b00 cmp r3, #0
|
|
80152dc: d026 beq.n 801532c <xQueueReceiveFromISR+0x114>
|
|
{
|
|
/* The task waiting has a higher priority than us so
|
|
* force a context switch. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
80152de: 687b ldr r3, [r7, #4]
|
|
80152e0: 2b00 cmp r3, #0
|
|
80152e2: d023 beq.n 801532c <xQueueReceiveFromISR+0x114>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
80152e4: 687b ldr r3, [r7, #4]
|
|
80152e6: 2201 movs r2, #1
|
|
80152e8: 601a str r2, [r3, #0]
|
|
80152ea: e01f b.n 801532c <xQueueReceiveFromISR+0x114>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
* knows that data was removed while it was locked. */
|
|
prvIncrementQueueRxLock( pxQueue, cRxLock );
|
|
80152ec: f000 fdb6 bl 8015e5c <uxTaskGetNumberOfTasks>
|
|
80152f0: 62b8 str r0, [r7, #40] @ 0x28
|
|
80152f2: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
|
|
80152f6: 6aba ldr r2, [r7, #40] @ 0x28
|
|
80152f8: 429a cmp r2, r3
|
|
80152fa: d917 bls.n 801532c <xQueueReceiveFromISR+0x114>
|
|
80152fc: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
|
|
8015300: 2b7f cmp r3, #127 @ 0x7f
|
|
8015302: d10b bne.n 801531c <xQueueReceiveFromISR+0x104>
|
|
__asm volatile
|
|
8015304: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015308: f383 8811 msr BASEPRI, r3
|
|
801530c: f3bf 8f6f isb sy
|
|
8015310: f3bf 8f4f dsb sy
|
|
8015314: 617b str r3, [r7, #20]
|
|
}
|
|
8015316: bf00 nop
|
|
8015318: bf00 nop
|
|
801531a: e7fd b.n 8015318 <xQueueReceiveFromISR+0x100>
|
|
801531c: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
8015320: 3301 adds r3, #1
|
|
8015322: b2db uxtb r3, r3
|
|
8015324: b25a sxtb r2, r3
|
|
8015326: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8015328: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
801532c: 2301 movs r3, #1
|
|
801532e: 63fb str r3, [r7, #60] @ 0x3c
|
|
8015330: e001 b.n 8015336 <xQueueReceiveFromISR+0x11e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFAIL;
|
|
8015332: 2300 movs r3, #0
|
|
8015334: 63fb str r3, [r7, #60] @ 0x3c
|
|
8015336: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8015338: 613b str r3, [r7, #16]
|
|
__asm volatile
|
|
801533a: 693b ldr r3, [r7, #16]
|
|
801533c: f383 8811 msr BASEPRI, r3
|
|
}
|
|
8015340: bf00 nop
|
|
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
8015342: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
}
|
|
8015344: 4618 mov r0, r3
|
|
8015346: 3740 adds r7, #64 @ 0x40
|
|
8015348: 46bd mov sp, r7
|
|
801534a: bd80 pop {r7, pc}
|
|
|
|
0801534c <vQueueDelete>:
|
|
return uxReturn;
|
|
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vQueueDelete( QueueHandle_t xQueue )
|
|
{
|
|
801534c: b580 push {r7, lr}
|
|
801534e: b084 sub sp, #16
|
|
8015350: af00 add r7, sp, #0
|
|
8015352: 6078 str r0, [r7, #4]
|
|
Queue_t * const pxQueue = xQueue;
|
|
8015354: 687b ldr r3, [r7, #4]
|
|
8015356: 60fb str r3, [r7, #12]
|
|
|
|
configASSERT( pxQueue );
|
|
8015358: 68fb ldr r3, [r7, #12]
|
|
801535a: 2b00 cmp r3, #0
|
|
801535c: d10b bne.n 8015376 <vQueueDelete+0x2a>
|
|
__asm volatile
|
|
801535e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015362: f383 8811 msr BASEPRI, r3
|
|
8015366: f3bf 8f6f isb sy
|
|
801536a: f3bf 8f4f dsb sy
|
|
801536e: 60bb str r3, [r7, #8]
|
|
}
|
|
8015370: bf00 nop
|
|
8015372: bf00 nop
|
|
8015374: e7fd b.n 8015372 <vQueueDelete+0x26>
|
|
traceQUEUE_DELETE( pxQueue );
|
|
|
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
|
{
|
|
vQueueUnregisterQueue( pxQueue );
|
|
8015376: 68f8 ldr r0, [r7, #12]
|
|
8015378: f000 f984 bl 8015684 <vQueueUnregisterQueue>
|
|
}
|
|
#elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
|
|
{
|
|
/* The queue could have been allocated statically or dynamically, so
|
|
* check before attempting to free the memory. */
|
|
if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
|
|
801537c: 68fb ldr r3, [r7, #12]
|
|
801537e: f893 3046 ldrb.w r3, [r3, #70] @ 0x46
|
|
8015382: 2b00 cmp r3, #0
|
|
8015384: d102 bne.n 801538c <vQueueDelete+0x40>
|
|
{
|
|
vPortFree( pxQueue );
|
|
8015386: 68f8 ldr r0, [r7, #12]
|
|
8015388: f002 fec6 bl 8018118 <vPortFree>
|
|
/* The queue must have been statically allocated, so is not going to be
|
|
* deleted. Avoid compiler warnings about the unused parameter. */
|
|
( void ) pxQueue;
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
}
|
|
801538c: bf00 nop
|
|
801538e: 3710 adds r7, #16
|
|
8015390: 46bd mov sp, r7
|
|
8015392: bd80 pop {r7, pc}
|
|
|
|
08015394 <prvGetDisinheritPriorityAfterTimeout>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
|
|
{
|
|
8015394: b480 push {r7}
|
|
8015396: b085 sub sp, #20
|
|
8015398: af00 add r7, sp, #0
|
|
801539a: 6078 str r0, [r7, #4]
|
|
* priority, but the waiting task times out, then the holder should
|
|
* disinherit the priority - but only down to the highest priority of any
|
|
* other tasks that are waiting for the same mutex. For this purpose,
|
|
* return the priority of the highest priority task that is waiting for the
|
|
* mutex. */
|
|
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
|
|
801539c: 687b ldr r3, [r7, #4]
|
|
801539e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80153a0: 2b00 cmp r3, #0
|
|
80153a2: d006 beq.n 80153b2 <prvGetDisinheritPriorityAfterTimeout+0x1e>
|
|
{
|
|
uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
|
|
80153a4: 687b ldr r3, [r7, #4]
|
|
80153a6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80153a8: 681b ldr r3, [r3, #0]
|
|
80153aa: f1c3 0338 rsb r3, r3, #56 @ 0x38
|
|
80153ae: 60fb str r3, [r7, #12]
|
|
80153b0: e001 b.n 80153b6 <prvGetDisinheritPriorityAfterTimeout+0x22>
|
|
}
|
|
else
|
|
{
|
|
uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
|
|
80153b2: 2300 movs r3, #0
|
|
80153b4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return uxHighestPriorityOfWaitingTasks;
|
|
80153b6: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80153b8: 4618 mov r0, r3
|
|
80153ba: 3714 adds r7, #20
|
|
80153bc: 46bd mov sp, r7
|
|
80153be: f85d 7b04 ldr.w r7, [sp], #4
|
|
80153c2: 4770 bx lr
|
|
|
|
080153c4 <prvCopyDataToQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
|
|
const void * pvItemToQueue,
|
|
const BaseType_t xPosition )
|
|
{
|
|
80153c4: b580 push {r7, lr}
|
|
80153c6: b086 sub sp, #24
|
|
80153c8: af00 add r7, sp, #0
|
|
80153ca: 60f8 str r0, [r7, #12]
|
|
80153cc: 60b9 str r1, [r7, #8]
|
|
80153ce: 607a str r2, [r7, #4]
|
|
BaseType_t xReturn = pdFALSE;
|
|
80153d0: 2300 movs r3, #0
|
|
80153d2: 617b str r3, [r7, #20]
|
|
UBaseType_t uxMessagesWaiting;
|
|
|
|
/* This function is called from a critical section. */
|
|
|
|
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
80153d4: 68fb ldr r3, [r7, #12]
|
|
80153d6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80153d8: 613b str r3, [r7, #16]
|
|
|
|
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
|
|
80153da: 68fb ldr r3, [r7, #12]
|
|
80153dc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80153de: 2b00 cmp r3, #0
|
|
80153e0: d10d bne.n 80153fe <prvCopyDataToQueue+0x3a>
|
|
{
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
80153e2: 68fb ldr r3, [r7, #12]
|
|
80153e4: 681b ldr r3, [r3, #0]
|
|
80153e6: 2b00 cmp r3, #0
|
|
80153e8: d14d bne.n 8015486 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* The mutex is no longer being held. */
|
|
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
|
|
80153ea: 68fb ldr r3, [r7, #12]
|
|
80153ec: 689b ldr r3, [r3, #8]
|
|
80153ee: 4618 mov r0, r3
|
|
80153f0: f001 fa48 bl 8016884 <xTaskPriorityDisinherit>
|
|
80153f4: 6178 str r0, [r7, #20]
|
|
pxQueue->u.xSemaphore.xMutexHolder = NULL;
|
|
80153f6: 68fb ldr r3, [r7, #12]
|
|
80153f8: 2200 movs r2, #0
|
|
80153fa: 609a str r2, [r3, #8]
|
|
80153fc: e043 b.n 8015486 <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
}
|
|
else if( xPosition == queueSEND_TO_BACK )
|
|
80153fe: 687b ldr r3, [r7, #4]
|
|
8015400: 2b00 cmp r3, #0
|
|
8015402: d119 bne.n 8015438 <prvCopyDataToQueue+0x74>
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
8015404: 68fb ldr r3, [r7, #12]
|
|
8015406: 6858 ldr r0, [r3, #4]
|
|
8015408: 68fb ldr r3, [r7, #12]
|
|
801540a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
801540c: 461a mov r2, r3
|
|
801540e: 68b9 ldr r1, [r7, #8]
|
|
8015410: f005 f855 bl 801a4be <memcpy>
|
|
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
8015414: 68fb ldr r3, [r7, #12]
|
|
8015416: 685a ldr r2, [r3, #4]
|
|
8015418: 68fb ldr r3, [r7, #12]
|
|
801541a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
801541c: 441a add r2, r3
|
|
801541e: 68fb ldr r3, [r7, #12]
|
|
8015420: 605a str r2, [r3, #4]
|
|
|
|
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
8015422: 68fb ldr r3, [r7, #12]
|
|
8015424: 685a ldr r2, [r3, #4]
|
|
8015426: 68fb ldr r3, [r7, #12]
|
|
8015428: 689b ldr r3, [r3, #8]
|
|
801542a: 429a cmp r2, r3
|
|
801542c: d32b bcc.n 8015486 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
801542e: 68fb ldr r3, [r7, #12]
|
|
8015430: 681a ldr r2, [r3, #0]
|
|
8015432: 68fb ldr r3, [r7, #12]
|
|
8015434: 605a str r2, [r3, #4]
|
|
8015436: e026 b.n 8015486 <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
|
|
8015438: 68fb ldr r3, [r7, #12]
|
|
801543a: 68d8 ldr r0, [r3, #12]
|
|
801543c: 68fb ldr r3, [r7, #12]
|
|
801543e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8015440: 461a mov r2, r3
|
|
8015442: 68b9 ldr r1, [r7, #8]
|
|
8015444: f005 f83b bl 801a4be <memcpy>
|
|
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
|
|
8015448: 68fb ldr r3, [r7, #12]
|
|
801544a: 68da ldr r2, [r3, #12]
|
|
801544c: 68fb ldr r3, [r7, #12]
|
|
801544e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8015450: 425b negs r3, r3
|
|
8015452: 441a add r2, r3
|
|
8015454: 68fb ldr r3, [r7, #12]
|
|
8015456: 60da str r2, [r3, #12]
|
|
|
|
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
8015458: 68fb ldr r3, [r7, #12]
|
|
801545a: 68da ldr r2, [r3, #12]
|
|
801545c: 68fb ldr r3, [r7, #12]
|
|
801545e: 681b ldr r3, [r3, #0]
|
|
8015460: 429a cmp r2, r3
|
|
8015462: d207 bcs.n 8015474 <prvCopyDataToQueue+0xb0>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
|
|
8015464: 68fb ldr r3, [r7, #12]
|
|
8015466: 689a ldr r2, [r3, #8]
|
|
8015468: 68fb ldr r3, [r7, #12]
|
|
801546a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
801546c: 425b negs r3, r3
|
|
801546e: 441a add r2, r3
|
|
8015470: 68fb ldr r3, [r7, #12]
|
|
8015472: 60da str r2, [r3, #12]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( xPosition == queueOVERWRITE )
|
|
8015474: 687b ldr r3, [r7, #4]
|
|
8015476: 2b02 cmp r3, #2
|
|
8015478: d105 bne.n 8015486 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
801547a: 693b ldr r3, [r7, #16]
|
|
801547c: 2b00 cmp r3, #0
|
|
801547e: d002 beq.n 8015486 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* An item is not being added but overwritten, so subtract
|
|
* one from the recorded number of items in the queue so when
|
|
* one is added again below the number of recorded items remains
|
|
* correct. */
|
|
--uxMessagesWaiting;
|
|
8015480: 693b ldr r3, [r7, #16]
|
|
8015482: 3b01 subs r3, #1
|
|
8015484: 613b str r3, [r7, #16]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
|
8015486: 693b ldr r3, [r7, #16]
|
|
8015488: 1c5a adds r2, r3, #1
|
|
801548a: 68fb ldr r3, [r7, #12]
|
|
801548c: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
return xReturn;
|
|
801548e: 697b ldr r3, [r7, #20]
|
|
}
|
|
8015490: 4618 mov r0, r3
|
|
8015492: 3718 adds r7, #24
|
|
8015494: 46bd mov sp, r7
|
|
8015496: bd80 pop {r7, pc}
|
|
|
|
08015498 <prvCopyDataFromQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCopyDataFromQueue( Queue_t * const pxQueue,
|
|
void * const pvBuffer )
|
|
{
|
|
8015498: b580 push {r7, lr}
|
|
801549a: b082 sub sp, #8
|
|
801549c: af00 add r7, sp, #0
|
|
801549e: 6078 str r0, [r7, #4]
|
|
80154a0: 6039 str r1, [r7, #0]
|
|
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
|
|
80154a2: 687b ldr r3, [r7, #4]
|
|
80154a4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80154a6: 2b00 cmp r3, #0
|
|
80154a8: d018 beq.n 80154dc <prvCopyDataFromQueue+0x44>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
80154aa: 687b ldr r3, [r7, #4]
|
|
80154ac: 68da ldr r2, [r3, #12]
|
|
80154ae: 687b ldr r3, [r7, #4]
|
|
80154b0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80154b2: 441a add r2, r3
|
|
80154b4: 687b ldr r3, [r7, #4]
|
|
80154b6: 60da str r2, [r3, #12]
|
|
|
|
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
|
|
80154b8: 687b ldr r3, [r7, #4]
|
|
80154ba: 68da ldr r2, [r3, #12]
|
|
80154bc: 687b ldr r3, [r7, #4]
|
|
80154be: 689b ldr r3, [r3, #8]
|
|
80154c0: 429a cmp r2, r3
|
|
80154c2: d303 bcc.n 80154cc <prvCopyDataFromQueue+0x34>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
|
|
80154c4: 687b ldr r3, [r7, #4]
|
|
80154c6: 681a ldr r2, [r3, #0]
|
|
80154c8: 687b ldr r3, [r7, #4]
|
|
80154ca: 60da str r2, [r3, #12]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
80154cc: 687b ldr r3, [r7, #4]
|
|
80154ce: 68d9 ldr r1, [r3, #12]
|
|
80154d0: 687b ldr r3, [r7, #4]
|
|
80154d2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80154d4: 461a mov r2, r3
|
|
80154d6: 6838 ldr r0, [r7, #0]
|
|
80154d8: f004 fff1 bl 801a4be <memcpy>
|
|
}
|
|
}
|
|
80154dc: bf00 nop
|
|
80154de: 3708 adds r7, #8
|
|
80154e0: 46bd mov sp, r7
|
|
80154e2: bd80 pop {r7, pc}
|
|
|
|
080154e4 <prvUnlockQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvUnlockQueue( Queue_t * const pxQueue )
|
|
{
|
|
80154e4: b580 push {r7, lr}
|
|
80154e6: b084 sub sp, #16
|
|
80154e8: af00 add r7, sp, #0
|
|
80154ea: 6078 str r0, [r7, #4]
|
|
|
|
/* The lock counts contains the number of extra data items placed or
|
|
* removed from the queue while the queue was locked. When a queue is
|
|
* locked items can be added or removed, but the event lists cannot be
|
|
* updated. */
|
|
taskENTER_CRITICAL();
|
|
80154ec: f002 fc20 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
int8_t cTxLock = pxQueue->cTxLock;
|
|
80154f0: 687b ldr r3, [r7, #4]
|
|
80154f2: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
80154f6: 73fb strb r3, [r7, #15]
|
|
|
|
/* See if data was added to the queue while it was locked. */
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
80154f8: e011 b.n 801551e <prvUnlockQueue+0x3a>
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
/* Tasks that are removed from the event list will get added to
|
|
* the pending ready list as the scheduler is still suspended. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
80154fa: 687b ldr r3, [r7, #4]
|
|
80154fc: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80154fe: 2b00 cmp r3, #0
|
|
8015500: d012 beq.n 8015528 <prvUnlockQueue+0x44>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
8015502: 687b ldr r3, [r7, #4]
|
|
8015504: 3324 adds r3, #36 @ 0x24
|
|
8015506: 4618 mov r0, r3
|
|
8015508: f000 fec2 bl 8016290 <xTaskRemoveFromEventList>
|
|
801550c: 4603 mov r3, r0
|
|
801550e: 2b00 cmp r3, #0
|
|
8015510: d001 beq.n 8015516 <prvUnlockQueue+0x32>
|
|
{
|
|
/* The task waiting has a higher priority so record that
|
|
* a context switch is required. */
|
|
vTaskMissedYield();
|
|
8015512: f001 f813 bl 801653c <vTaskMissedYield>
|
|
break;
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
--cTxLock;
|
|
8015516: 7bfb ldrb r3, [r7, #15]
|
|
8015518: 3b01 subs r3, #1
|
|
801551a: b2db uxtb r3, r3
|
|
801551c: 73fb strb r3, [r7, #15]
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
801551e: f997 300f ldrsb.w r3, [r7, #15]
|
|
8015522: 2b00 cmp r3, #0
|
|
8015524: dce9 bgt.n 80154fa <prvUnlockQueue+0x16>
|
|
8015526: e000 b.n 801552a <prvUnlockQueue+0x46>
|
|
break;
|
|
8015528: bf00 nop
|
|
}
|
|
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
801552a: 687b ldr r3, [r7, #4]
|
|
801552c: 22ff movs r2, #255 @ 0xff
|
|
801552e: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8015532: f002 fc2f bl 8017d94 <vPortExitCritical>
|
|
|
|
/* Do the same for the Rx lock. */
|
|
taskENTER_CRITICAL();
|
|
8015536: f002 fbfb bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
int8_t cRxLock = pxQueue->cRxLock;
|
|
801553a: 687b ldr r3, [r7, #4]
|
|
801553c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
8015540: 73bb strb r3, [r7, #14]
|
|
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
8015542: e011 b.n 8015568 <prvUnlockQueue+0x84>
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
8015544: 687b ldr r3, [r7, #4]
|
|
8015546: 691b ldr r3, [r3, #16]
|
|
8015548: 2b00 cmp r3, #0
|
|
801554a: d012 beq.n 8015572 <prvUnlockQueue+0x8e>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
801554c: 687b ldr r3, [r7, #4]
|
|
801554e: 3310 adds r3, #16
|
|
8015550: 4618 mov r0, r3
|
|
8015552: f000 fe9d bl 8016290 <xTaskRemoveFromEventList>
|
|
8015556: 4603 mov r3, r0
|
|
8015558: 2b00 cmp r3, #0
|
|
801555a: d001 beq.n 8015560 <prvUnlockQueue+0x7c>
|
|
{
|
|
vTaskMissedYield();
|
|
801555c: f000 ffee bl 801653c <vTaskMissedYield>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
--cRxLock;
|
|
8015560: 7bbb ldrb r3, [r7, #14]
|
|
8015562: 3b01 subs r3, #1
|
|
8015564: b2db uxtb r3, r3
|
|
8015566: 73bb strb r3, [r7, #14]
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
8015568: f997 300e ldrsb.w r3, [r7, #14]
|
|
801556c: 2b00 cmp r3, #0
|
|
801556e: dce9 bgt.n 8015544 <prvUnlockQueue+0x60>
|
|
8015570: e000 b.n 8015574 <prvUnlockQueue+0x90>
|
|
}
|
|
else
|
|
{
|
|
break;
|
|
8015572: bf00 nop
|
|
}
|
|
}
|
|
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
8015574: 687b ldr r3, [r7, #4]
|
|
8015576: 22ff movs r2, #255 @ 0xff
|
|
8015578: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
801557c: f002 fc0a bl 8017d94 <vPortExitCritical>
|
|
}
|
|
8015580: bf00 nop
|
|
8015582: 3710 adds r7, #16
|
|
8015584: 46bd mov sp, r7
|
|
8015586: bd80 pop {r7, pc}
|
|
|
|
08015588 <prvIsQueueEmpty>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue )
|
|
{
|
|
8015588: b580 push {r7, lr}
|
|
801558a: b084 sub sp, #16
|
|
801558c: af00 add r7, sp, #0
|
|
801558e: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
8015590: f002 fbce bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
|
|
8015594: 687b ldr r3, [r7, #4]
|
|
8015596: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8015598: 2b00 cmp r3, #0
|
|
801559a: d102 bne.n 80155a2 <prvIsQueueEmpty+0x1a>
|
|
{
|
|
xReturn = pdTRUE;
|
|
801559c: 2301 movs r3, #1
|
|
801559e: 60fb str r3, [r7, #12]
|
|
80155a0: e001 b.n 80155a6 <prvIsQueueEmpty+0x1e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
80155a2: 2300 movs r3, #0
|
|
80155a4: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
80155a6: f002 fbf5 bl 8017d94 <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
80155aa: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80155ac: 4618 mov r0, r3
|
|
80155ae: 3710 adds r7, #16
|
|
80155b0: 46bd mov sp, r7
|
|
80155b2: bd80 pop {r7, pc}
|
|
|
|
080155b4 <prvIsQueueFull>:
|
|
return xReturn;
|
|
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueFull( const Queue_t * pxQueue )
|
|
{
|
|
80155b4: b580 push {r7, lr}
|
|
80155b6: b084 sub sp, #16
|
|
80155b8: af00 add r7, sp, #0
|
|
80155ba: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
80155bc: f002 fbb8 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
|
|
80155c0: 687b ldr r3, [r7, #4]
|
|
80155c2: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
80155c4: 687b ldr r3, [r7, #4]
|
|
80155c6: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80155c8: 429a cmp r2, r3
|
|
80155ca: d102 bne.n 80155d2 <prvIsQueueFull+0x1e>
|
|
{
|
|
xReturn = pdTRUE;
|
|
80155cc: 2301 movs r3, #1
|
|
80155ce: 60fb str r3, [r7, #12]
|
|
80155d0: e001 b.n 80155d6 <prvIsQueueFull+0x22>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
80155d2: 2300 movs r3, #0
|
|
80155d4: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
80155d6: f002 fbdd bl 8017d94 <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
80155da: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80155dc: 4618 mov r0, r3
|
|
80155de: 3710 adds r7, #16
|
|
80155e0: 46bd mov sp, r7
|
|
80155e2: bd80 pop {r7, pc}
|
|
|
|
080155e4 <vQueueAddToRegistry>:
|
|
|
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
|
|
|
void vQueueAddToRegistry( QueueHandle_t xQueue,
|
|
const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
|
|
{
|
|
80155e4: b480 push {r7}
|
|
80155e6: b087 sub sp, #28
|
|
80155e8: af00 add r7, sp, #0
|
|
80155ea: 6078 str r0, [r7, #4]
|
|
80155ec: 6039 str r1, [r7, #0]
|
|
UBaseType_t ux;
|
|
QueueRegistryItem_t * pxEntryToWrite = NULL;
|
|
80155ee: 2300 movs r3, #0
|
|
80155f0: 613b str r3, [r7, #16]
|
|
|
|
configASSERT( xQueue );
|
|
80155f2: 687b ldr r3, [r7, #4]
|
|
80155f4: 2b00 cmp r3, #0
|
|
80155f6: d10b bne.n 8015610 <vQueueAddToRegistry+0x2c>
|
|
__asm volatile
|
|
80155f8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80155fc: f383 8811 msr BASEPRI, r3
|
|
8015600: f3bf 8f6f isb sy
|
|
8015604: f3bf 8f4f dsb sy
|
|
8015608: 60fb str r3, [r7, #12]
|
|
}
|
|
801560a: bf00 nop
|
|
801560c: bf00 nop
|
|
801560e: e7fd b.n 801560c <vQueueAddToRegistry+0x28>
|
|
|
|
if( pcQueueName != NULL )
|
|
8015610: 683b ldr r3, [r7, #0]
|
|
8015612: 2b00 cmp r3, #0
|
|
8015614: d024 beq.n 8015660 <vQueueAddToRegistry+0x7c>
|
|
{
|
|
/* See if there is an empty space in the registry. A NULL name denotes
|
|
* a free slot. */
|
|
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
|
|
8015616: 2300 movs r3, #0
|
|
8015618: 617b str r3, [r7, #20]
|
|
801561a: e01e b.n 801565a <vQueueAddToRegistry+0x76>
|
|
{
|
|
/* Replace an existing entry if the queue is already in the registry. */
|
|
if( xQueue == xQueueRegistry[ ux ].xHandle )
|
|
801561c: 4a18 ldr r2, [pc, #96] @ (8015680 <vQueueAddToRegistry+0x9c>)
|
|
801561e: 697b ldr r3, [r7, #20]
|
|
8015620: 00db lsls r3, r3, #3
|
|
8015622: 4413 add r3, r2
|
|
8015624: 685b ldr r3, [r3, #4]
|
|
8015626: 687a ldr r2, [r7, #4]
|
|
8015628: 429a cmp r2, r3
|
|
801562a: d105 bne.n 8015638 <vQueueAddToRegistry+0x54>
|
|
{
|
|
pxEntryToWrite = &( xQueueRegistry[ ux ] );
|
|
801562c: 697b ldr r3, [r7, #20]
|
|
801562e: 00db lsls r3, r3, #3
|
|
8015630: 4a13 ldr r2, [pc, #76] @ (8015680 <vQueueAddToRegistry+0x9c>)
|
|
8015632: 4413 add r3, r2
|
|
8015634: 613b str r3, [r7, #16]
|
|
break;
|
|
8015636: e013 b.n 8015660 <vQueueAddToRegistry+0x7c>
|
|
}
|
|
/* Otherwise, store in the next empty location */
|
|
else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) )
|
|
8015638: 693b ldr r3, [r7, #16]
|
|
801563a: 2b00 cmp r3, #0
|
|
801563c: d10a bne.n 8015654 <vQueueAddToRegistry+0x70>
|
|
801563e: 4a10 ldr r2, [pc, #64] @ (8015680 <vQueueAddToRegistry+0x9c>)
|
|
8015640: 697b ldr r3, [r7, #20]
|
|
8015642: f852 3033 ldr.w r3, [r2, r3, lsl #3]
|
|
8015646: 2b00 cmp r3, #0
|
|
8015648: d104 bne.n 8015654 <vQueueAddToRegistry+0x70>
|
|
{
|
|
pxEntryToWrite = &( xQueueRegistry[ ux ] );
|
|
801564a: 697b ldr r3, [r7, #20]
|
|
801564c: 00db lsls r3, r3, #3
|
|
801564e: 4a0c ldr r2, [pc, #48] @ (8015680 <vQueueAddToRegistry+0x9c>)
|
|
8015650: 4413 add r3, r2
|
|
8015652: 613b str r3, [r7, #16]
|
|
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
|
|
8015654: 697b ldr r3, [r7, #20]
|
|
8015656: 3301 adds r3, #1
|
|
8015658: 617b str r3, [r7, #20]
|
|
801565a: 697b ldr r3, [r7, #20]
|
|
801565c: 2b07 cmp r3, #7
|
|
801565e: d9dd bls.n 801561c <vQueueAddToRegistry+0x38>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
|
|
if( pxEntryToWrite != NULL )
|
|
8015660: 693b ldr r3, [r7, #16]
|
|
8015662: 2b00 cmp r3, #0
|
|
8015664: d005 beq.n 8015672 <vQueueAddToRegistry+0x8e>
|
|
{
|
|
/* Store the information on this queue. */
|
|
pxEntryToWrite->pcQueueName = pcQueueName;
|
|
8015666: 693b ldr r3, [r7, #16]
|
|
8015668: 683a ldr r2, [r7, #0]
|
|
801566a: 601a str r2, [r3, #0]
|
|
pxEntryToWrite->xHandle = xQueue;
|
|
801566c: 693b ldr r3, [r7, #16]
|
|
801566e: 687a ldr r2, [r7, #4]
|
|
8015670: 605a str r2, [r3, #4]
|
|
|
|
traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
|
|
}
|
|
}
|
|
8015672: bf00 nop
|
|
8015674: 371c adds r7, #28
|
|
8015676: 46bd mov sp, r7
|
|
8015678: f85d 7b04 ldr.w r7, [sp], #4
|
|
801567c: 4770 bx lr
|
|
801567e: bf00 nop
|
|
8015680: 20002128 .word 0x20002128
|
|
|
|
08015684 <vQueueUnregisterQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
|
|
|
void vQueueUnregisterQueue( QueueHandle_t xQueue )
|
|
{
|
|
8015684: b480 push {r7}
|
|
8015686: b085 sub sp, #20
|
|
8015688: af00 add r7, sp, #0
|
|
801568a: 6078 str r0, [r7, #4]
|
|
UBaseType_t ux;
|
|
|
|
configASSERT( xQueue );
|
|
801568c: 687b ldr r3, [r7, #4]
|
|
801568e: 2b00 cmp r3, #0
|
|
8015690: d10b bne.n 80156aa <vQueueUnregisterQueue+0x26>
|
|
__asm volatile
|
|
8015692: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015696: f383 8811 msr BASEPRI, r3
|
|
801569a: f3bf 8f6f isb sy
|
|
801569e: f3bf 8f4f dsb sy
|
|
80156a2: 60bb str r3, [r7, #8]
|
|
}
|
|
80156a4: bf00 nop
|
|
80156a6: bf00 nop
|
|
80156a8: e7fd b.n 80156a6 <vQueueUnregisterQueue+0x22>
|
|
|
|
/* See if the handle of the queue being unregistered in actually in the
|
|
* registry. */
|
|
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
|
|
80156aa: 2300 movs r3, #0
|
|
80156ac: 60fb str r3, [r7, #12]
|
|
80156ae: e016 b.n 80156de <vQueueUnregisterQueue+0x5a>
|
|
{
|
|
if( xQueueRegistry[ ux ].xHandle == xQueue )
|
|
80156b0: 4a10 ldr r2, [pc, #64] @ (80156f4 <vQueueUnregisterQueue+0x70>)
|
|
80156b2: 68fb ldr r3, [r7, #12]
|
|
80156b4: 00db lsls r3, r3, #3
|
|
80156b6: 4413 add r3, r2
|
|
80156b8: 685b ldr r3, [r3, #4]
|
|
80156ba: 687a ldr r2, [r7, #4]
|
|
80156bc: 429a cmp r2, r3
|
|
80156be: d10b bne.n 80156d8 <vQueueUnregisterQueue+0x54>
|
|
{
|
|
/* Set the name to NULL to show that this slot if free again. */
|
|
xQueueRegistry[ ux ].pcQueueName = NULL;
|
|
80156c0: 4a0c ldr r2, [pc, #48] @ (80156f4 <vQueueUnregisterQueue+0x70>)
|
|
80156c2: 68fb ldr r3, [r7, #12]
|
|
80156c4: 2100 movs r1, #0
|
|
80156c6: f842 1033 str.w r1, [r2, r3, lsl #3]
|
|
|
|
/* Set the handle to NULL to ensure the same queue handle cannot
|
|
* appear in the registry twice if it is added, removed, then
|
|
* added again. */
|
|
xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
|
|
80156ca: 4a0a ldr r2, [pc, #40] @ (80156f4 <vQueueUnregisterQueue+0x70>)
|
|
80156cc: 68fb ldr r3, [r7, #12]
|
|
80156ce: 00db lsls r3, r3, #3
|
|
80156d0: 4413 add r3, r2
|
|
80156d2: 2200 movs r2, #0
|
|
80156d4: 605a str r2, [r3, #4]
|
|
break;
|
|
80156d6: e006 b.n 80156e6 <vQueueUnregisterQueue+0x62>
|
|
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
|
|
80156d8: 68fb ldr r3, [r7, #12]
|
|
80156da: 3301 adds r3, #1
|
|
80156dc: 60fb str r3, [r7, #12]
|
|
80156de: 68fb ldr r3, [r7, #12]
|
|
80156e0: 2b07 cmp r3, #7
|
|
80156e2: d9e5 bls.n 80156b0 <vQueueUnregisterQueue+0x2c>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
|
|
80156e4: bf00 nop
|
|
80156e6: bf00 nop
|
|
80156e8: 3714 adds r7, #20
|
|
80156ea: 46bd mov sp, r7
|
|
80156ec: f85d 7b04 ldr.w r7, [sp], #4
|
|
80156f0: 4770 bx lr
|
|
80156f2: bf00 nop
|
|
80156f4: 20002128 .word 0x20002128
|
|
|
|
080156f8 <vQueueWaitForMessageRestricted>:
|
|
#if ( configUSE_TIMERS == 1 )
|
|
|
|
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
|
|
TickType_t xTicksToWait,
|
|
const BaseType_t xWaitIndefinitely )
|
|
{
|
|
80156f8: b580 push {r7, lr}
|
|
80156fa: b086 sub sp, #24
|
|
80156fc: af00 add r7, sp, #0
|
|
80156fe: 60f8 str r0, [r7, #12]
|
|
8015700: 60b9 str r1, [r7, #8]
|
|
8015702: 607a str r2, [r7, #4]
|
|
Queue_t * const pxQueue = xQueue;
|
|
8015704: 68fb ldr r3, [r7, #12]
|
|
8015706: 617b str r3, [r7, #20]
|
|
* will not actually cause the task to block, just place it on a blocked
|
|
* list. It will not block until the scheduler is unlocked - at which
|
|
* time a yield will be performed. If an item is added to the queue while
|
|
* the queue is locked, and the calling task blocks on the queue, then the
|
|
* calling task will be immediately unblocked when the queue is unlocked. */
|
|
prvLockQueue( pxQueue );
|
|
8015708: f002 fb12 bl 8017d30 <vPortEnterCritical>
|
|
801570c: 697b ldr r3, [r7, #20]
|
|
801570e: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
8015712: b25b sxtb r3, r3
|
|
8015714: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8015718: d103 bne.n 8015722 <vQueueWaitForMessageRestricted+0x2a>
|
|
801571a: 697b ldr r3, [r7, #20]
|
|
801571c: 2200 movs r2, #0
|
|
801571e: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8015722: 697b ldr r3, [r7, #20]
|
|
8015724: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
8015728: b25b sxtb r3, r3
|
|
801572a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
801572e: d103 bne.n 8015738 <vQueueWaitForMessageRestricted+0x40>
|
|
8015730: 697b ldr r3, [r7, #20]
|
|
8015732: 2200 movs r2, #0
|
|
8015734: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
8015738: f002 fb2c bl 8017d94 <vPortExitCritical>
|
|
|
|
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
|
|
801573c: 697b ldr r3, [r7, #20]
|
|
801573e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8015740: 2b00 cmp r3, #0
|
|
8015742: d106 bne.n 8015752 <vQueueWaitForMessageRestricted+0x5a>
|
|
{
|
|
/* There is nothing in the queue, block for the specified period. */
|
|
vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
|
|
8015744: 697b ldr r3, [r7, #20]
|
|
8015746: 3324 adds r3, #36 @ 0x24
|
|
8015748: 687a ldr r2, [r7, #4]
|
|
801574a: 68b9 ldr r1, [r7, #8]
|
|
801574c: 4618 mov r0, r3
|
|
801574e: f000 fd59 bl 8016204 <vTaskPlaceOnEventListRestricted>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
prvUnlockQueue( pxQueue );
|
|
8015752: 6978 ldr r0, [r7, #20]
|
|
8015754: f7ff fec6 bl 80154e4 <prvUnlockQueue>
|
|
}
|
|
8015758: bf00 nop
|
|
801575a: 3718 adds r7, #24
|
|
801575c: 46bd mov sp, r7
|
|
801575e: bd80 pop {r7, pc}
|
|
|
|
08015760 <xTaskCreateStatic>:
|
|
const uint32_t ulStackDepth,
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
StackType_t * const puxStackBuffer,
|
|
StaticTask_t * const pxTaskBuffer )
|
|
{
|
|
8015760: b580 push {r7, lr}
|
|
8015762: b08e sub sp, #56 @ 0x38
|
|
8015764: af04 add r7, sp, #16
|
|
8015766: 60f8 str r0, [r7, #12]
|
|
8015768: 60b9 str r1, [r7, #8]
|
|
801576a: 607a str r2, [r7, #4]
|
|
801576c: 603b str r3, [r7, #0]
|
|
TCB_t * pxNewTCB;
|
|
TaskHandle_t xReturn;
|
|
|
|
configASSERT( puxStackBuffer != NULL );
|
|
801576e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8015770: 2b00 cmp r3, #0
|
|
8015772: d10b bne.n 801578c <xTaskCreateStatic+0x2c>
|
|
__asm volatile
|
|
8015774: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015778: f383 8811 msr BASEPRI, r3
|
|
801577c: f3bf 8f6f isb sy
|
|
8015780: f3bf 8f4f dsb sy
|
|
8015784: 623b str r3, [r7, #32]
|
|
}
|
|
8015786: bf00 nop
|
|
8015788: bf00 nop
|
|
801578a: e7fd b.n 8015788 <xTaskCreateStatic+0x28>
|
|
configASSERT( pxTaskBuffer != NULL );
|
|
801578c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
801578e: 2b00 cmp r3, #0
|
|
8015790: d10b bne.n 80157aa <xTaskCreateStatic+0x4a>
|
|
__asm volatile
|
|
8015792: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015796: f383 8811 msr BASEPRI, r3
|
|
801579a: f3bf 8f6f isb sy
|
|
801579e: f3bf 8f4f dsb sy
|
|
80157a2: 61fb str r3, [r7, #28]
|
|
}
|
|
80157a4: bf00 nop
|
|
80157a6: bf00 nop
|
|
80157a8: e7fd b.n 80157a6 <xTaskCreateStatic+0x46>
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
{
|
|
/* Sanity check that the size of the structure used to declare a
|
|
* variable of type StaticTask_t equals the size of the real task
|
|
* structure. */
|
|
volatile size_t xSize = sizeof( StaticTask_t );
|
|
80157aa: 23ac movs r3, #172 @ 0xac
|
|
80157ac: 613b str r3, [r7, #16]
|
|
configASSERT( xSize == sizeof( TCB_t ) );
|
|
80157ae: 693b ldr r3, [r7, #16]
|
|
80157b0: 2bac cmp r3, #172 @ 0xac
|
|
80157b2: d00b beq.n 80157cc <xTaskCreateStatic+0x6c>
|
|
__asm volatile
|
|
80157b4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80157b8: f383 8811 msr BASEPRI, r3
|
|
80157bc: f3bf 8f6f isb sy
|
|
80157c0: f3bf 8f4f dsb sy
|
|
80157c4: 61bb str r3, [r7, #24]
|
|
}
|
|
80157c6: bf00 nop
|
|
80157c8: bf00 nop
|
|
80157ca: e7fd b.n 80157c8 <xTaskCreateStatic+0x68>
|
|
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
|
|
80157cc: 693b ldr r3, [r7, #16]
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
|
|
80157ce: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80157d0: 2b00 cmp r3, #0
|
|
80157d2: d023 beq.n 801581c <xTaskCreateStatic+0xbc>
|
|
80157d4: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80157d6: 2b00 cmp r3, #0
|
|
80157d8: d020 beq.n 801581c <xTaskCreateStatic+0xbc>
|
|
{
|
|
/* The memory used for the task's TCB and stack are passed into this
|
|
* function - use them. */
|
|
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
|
80157da: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80157dc: 627b str r3, [r7, #36] @ 0x24
|
|
memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
|
|
80157de: 22ac movs r2, #172 @ 0xac
|
|
80157e0: 2100 movs r1, #0
|
|
80157e2: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
80157e4: f004 fd8e bl 801a304 <memset>
|
|
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
|
|
80157e8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80157ea: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
80157ec: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* Tasks can be created statically or dynamically, so note this
|
|
* task was created statically in case the task is later deleted. */
|
|
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
|
|
80157ee: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80157f0: 2202 movs r2, #2
|
|
80157f2: f883 20aa strb.w r2, [r3, #170] @ 0xaa
|
|
}
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
|
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
|
|
80157f6: 2300 movs r3, #0
|
|
80157f8: 9303 str r3, [sp, #12]
|
|
80157fa: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80157fc: 9302 str r3, [sp, #8]
|
|
80157fe: f107 0314 add.w r3, r7, #20
|
|
8015802: 9301 str r3, [sp, #4]
|
|
8015804: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8015806: 9300 str r3, [sp, #0]
|
|
8015808: 683b ldr r3, [r7, #0]
|
|
801580a: 687a ldr r2, [r7, #4]
|
|
801580c: 68b9 ldr r1, [r7, #8]
|
|
801580e: 68f8 ldr r0, [r7, #12]
|
|
8015810: f000 f856 bl 80158c0 <prvInitialiseNewTask>
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
|
8015814: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
8015816: f000 f8f9 bl 8015a0c <prvAddNewTaskToReadyList>
|
|
801581a: e001 b.n 8015820 <xTaskCreateStatic+0xc0>
|
|
}
|
|
else
|
|
{
|
|
xReturn = NULL;
|
|
801581c: 2300 movs r3, #0
|
|
801581e: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
return xReturn;
|
|
8015820: 697b ldr r3, [r7, #20]
|
|
}
|
|
8015822: 4618 mov r0, r3
|
|
8015824: 3728 adds r7, #40 @ 0x28
|
|
8015826: 46bd mov sp, r7
|
|
8015828: bd80 pop {r7, pc}
|
|
|
|
0801582a <xTaskCreate>:
|
|
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
|
|
const configSTACK_DEPTH_TYPE usStackDepth,
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
TaskHandle_t * const pxCreatedTask )
|
|
{
|
|
801582a: b580 push {r7, lr}
|
|
801582c: b08c sub sp, #48 @ 0x30
|
|
801582e: af04 add r7, sp, #16
|
|
8015830: 60f8 str r0, [r7, #12]
|
|
8015832: 60b9 str r1, [r7, #8]
|
|
8015834: 603b str r3, [r7, #0]
|
|
8015836: 4613 mov r3, r2
|
|
8015838: 80fb strh r3, [r7, #6]
|
|
#else /* portSTACK_GROWTH */
|
|
{
|
|
StackType_t * pxStack;
|
|
|
|
/* Allocate space for the stack used by the task being created. */
|
|
pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
|
|
801583a: 88fb ldrh r3, [r7, #6]
|
|
801583c: 009b lsls r3, r3, #2
|
|
801583e: 4618 mov r0, r3
|
|
8015840: f002 fb9e bl 8017f80 <pvPortMalloc>
|
|
8015844: 6178 str r0, [r7, #20]
|
|
|
|
if( pxStack != NULL )
|
|
8015846: 697b ldr r3, [r7, #20]
|
|
8015848: 2b00 cmp r3, #0
|
|
801584a: d013 beq.n 8015874 <xTaskCreate+0x4a>
|
|
{
|
|
/* Allocate space for the TCB. */
|
|
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
|
|
801584c: 20ac movs r0, #172 @ 0xac
|
|
801584e: f002 fb97 bl 8017f80 <pvPortMalloc>
|
|
8015852: 61f8 str r0, [r7, #28]
|
|
|
|
if( pxNewTCB != NULL )
|
|
8015854: 69fb ldr r3, [r7, #28]
|
|
8015856: 2b00 cmp r3, #0
|
|
8015858: d008 beq.n 801586c <xTaskCreate+0x42>
|
|
{
|
|
memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
|
|
801585a: 22ac movs r2, #172 @ 0xac
|
|
801585c: 2100 movs r1, #0
|
|
801585e: 69f8 ldr r0, [r7, #28]
|
|
8015860: f004 fd50 bl 801a304 <memset>
|
|
|
|
/* Store the stack location in the TCB. */
|
|
pxNewTCB->pxStack = pxStack;
|
|
8015864: 69fb ldr r3, [r7, #28]
|
|
8015866: 697a ldr r2, [r7, #20]
|
|
8015868: 631a str r2, [r3, #48] @ 0x30
|
|
801586a: e005 b.n 8015878 <xTaskCreate+0x4e>
|
|
}
|
|
else
|
|
{
|
|
/* The stack cannot be used as the TCB was not created. Free
|
|
* it again. */
|
|
vPortFreeStack( pxStack );
|
|
801586c: 6978 ldr r0, [r7, #20]
|
|
801586e: f002 fc53 bl 8018118 <vPortFree>
|
|
8015872: e001 b.n 8015878 <xTaskCreate+0x4e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxNewTCB = NULL;
|
|
8015874: 2300 movs r3, #0
|
|
8015876: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
|
|
if( pxNewTCB != NULL )
|
|
8015878: 69fb ldr r3, [r7, #28]
|
|
801587a: 2b00 cmp r3, #0
|
|
801587c: d017 beq.n 80158ae <xTaskCreate+0x84>
|
|
{
|
|
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* Tasks can be created statically or dynamically, so note this
|
|
* task was created dynamically in case it is later deleted. */
|
|
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
|
|
801587e: 69fb ldr r3, [r7, #28]
|
|
8015880: 2200 movs r2, #0
|
|
8015882: f883 20aa strb.w r2, [r3, #170] @ 0xaa
|
|
}
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
|
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
|
|
8015886: 88fa ldrh r2, [r7, #6]
|
|
8015888: 2300 movs r3, #0
|
|
801588a: 9303 str r3, [sp, #12]
|
|
801588c: 69fb ldr r3, [r7, #28]
|
|
801588e: 9302 str r3, [sp, #8]
|
|
8015890: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8015892: 9301 str r3, [sp, #4]
|
|
8015894: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8015896: 9300 str r3, [sp, #0]
|
|
8015898: 683b ldr r3, [r7, #0]
|
|
801589a: 68b9 ldr r1, [r7, #8]
|
|
801589c: 68f8 ldr r0, [r7, #12]
|
|
801589e: f000 f80f bl 80158c0 <prvInitialiseNewTask>
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
|
80158a2: 69f8 ldr r0, [r7, #28]
|
|
80158a4: f000 f8b2 bl 8015a0c <prvAddNewTaskToReadyList>
|
|
xReturn = pdPASS;
|
|
80158a8: 2301 movs r3, #1
|
|
80158aa: 61bb str r3, [r7, #24]
|
|
80158ac: e002 b.n 80158b4 <xTaskCreate+0x8a>
|
|
}
|
|
else
|
|
{
|
|
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
|
|
80158ae: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80158b2: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return xReturn;
|
|
80158b4: 69bb ldr r3, [r7, #24]
|
|
}
|
|
80158b6: 4618 mov r0, r3
|
|
80158b8: 3720 adds r7, #32
|
|
80158ba: 46bd mov sp, r7
|
|
80158bc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080158c0 <prvInitialiseNewTask>:
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
TaskHandle_t * const pxCreatedTask,
|
|
TCB_t * pxNewTCB,
|
|
const MemoryRegion_t * const xRegions )
|
|
{
|
|
80158c0: b580 push {r7, lr}
|
|
80158c2: b088 sub sp, #32
|
|
80158c4: af00 add r7, sp, #0
|
|
80158c6: 60f8 str r0, [r7, #12]
|
|
80158c8: 60b9 str r1, [r7, #8]
|
|
80158ca: 607a str r2, [r7, #4]
|
|
80158cc: 603b str r3, [r7, #0]
|
|
|
|
/* Avoid dependency on memset() if it is not required. */
|
|
#if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
|
|
{
|
|
/* Fill the stack with a known value to assist debugging. */
|
|
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
|
|
80158ce: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80158d0: 6b18 ldr r0, [r3, #48] @ 0x30
|
|
80158d2: 687b ldr r3, [r7, #4]
|
|
80158d4: 009b lsls r3, r3, #2
|
|
80158d6: 461a mov r2, r3
|
|
80158d8: 21a5 movs r1, #165 @ 0xa5
|
|
80158da: f004 fd13 bl 801a304 <memset>
|
|
* grows from high memory to low (as per the 80x86) or vice versa.
|
|
* portSTACK_GROWTH is used to make the result positive or negative as required
|
|
* by the port. */
|
|
#if ( portSTACK_GROWTH < 0 )
|
|
{
|
|
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
|
|
80158de: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80158e0: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
80158e2: 687b ldr r3, [r7, #4]
|
|
80158e4: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000
|
|
80158e8: 3b01 subs r3, #1
|
|
80158ea: 009b lsls r3, r3, #2
|
|
80158ec: 4413 add r3, r2
|
|
80158ee: 61bb str r3, [r7, #24]
|
|
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
|
|
80158f0: 69bb ldr r3, [r7, #24]
|
|
80158f2: f023 0307 bic.w r3, r3, #7
|
|
80158f6: 61bb str r3, [r7, #24]
|
|
|
|
/* Check the alignment of the calculated top of stack is correct. */
|
|
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
|
|
80158f8: 69bb ldr r3, [r7, #24]
|
|
80158fa: f003 0307 and.w r3, r3, #7
|
|
80158fe: 2b00 cmp r3, #0
|
|
8015900: d00b beq.n 801591a <prvInitialiseNewTask+0x5a>
|
|
__asm volatile
|
|
8015902: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015906: f383 8811 msr BASEPRI, r3
|
|
801590a: f3bf 8f6f isb sy
|
|
801590e: f3bf 8f4f dsb sy
|
|
8015912: 617b str r3, [r7, #20]
|
|
}
|
|
8015914: bf00 nop
|
|
8015916: bf00 nop
|
|
8015918: e7fd b.n 8015916 <prvInitialiseNewTask+0x56>
|
|
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
|
|
/* Store the task name in the TCB. */
|
|
if( pcName != NULL )
|
|
801591a: 68bb ldr r3, [r7, #8]
|
|
801591c: 2b00 cmp r3, #0
|
|
801591e: d01e beq.n 801595e <prvInitialiseNewTask+0x9e>
|
|
{
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
|
8015920: 2300 movs r3, #0
|
|
8015922: 61fb str r3, [r7, #28]
|
|
8015924: e012 b.n 801594c <prvInitialiseNewTask+0x8c>
|
|
{
|
|
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
|
|
8015926: 68ba ldr r2, [r7, #8]
|
|
8015928: 69fb ldr r3, [r7, #28]
|
|
801592a: 4413 add r3, r2
|
|
801592c: 7819 ldrb r1, [r3, #0]
|
|
801592e: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8015930: 69fb ldr r3, [r7, #28]
|
|
8015932: 4413 add r3, r2
|
|
8015934: 3334 adds r3, #52 @ 0x34
|
|
8015936: 460a mov r2, r1
|
|
8015938: 701a strb r2, [r3, #0]
|
|
|
|
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
|
|
* configMAX_TASK_NAME_LEN characters just in case the memory after the
|
|
* string is not accessible (extremely unlikely). */
|
|
if( pcName[ x ] == ( char ) 0x00 )
|
|
801593a: 68ba ldr r2, [r7, #8]
|
|
801593c: 69fb ldr r3, [r7, #28]
|
|
801593e: 4413 add r3, r2
|
|
8015940: 781b ldrb r3, [r3, #0]
|
|
8015942: 2b00 cmp r3, #0
|
|
8015944: d006 beq.n 8015954 <prvInitialiseNewTask+0x94>
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
|
8015946: 69fb ldr r3, [r7, #28]
|
|
8015948: 3301 adds r3, #1
|
|
801594a: 61fb str r3, [r7, #28]
|
|
801594c: 69fb ldr r3, [r7, #28]
|
|
801594e: 2b0f cmp r3, #15
|
|
8015950: d9e9 bls.n 8015926 <prvInitialiseNewTask+0x66>
|
|
8015952: e000 b.n 8015956 <prvInitialiseNewTask+0x96>
|
|
{
|
|
break;
|
|
8015954: bf00 nop
|
|
}
|
|
}
|
|
|
|
/* Ensure the name string is terminated in the case that the string length
|
|
* was greater or equal to configMAX_TASK_NAME_LEN. */
|
|
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
|
|
8015956: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8015958: 2200 movs r2, #0
|
|
801595a: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* This is used as an array index so must ensure it's not too large. */
|
|
configASSERT( uxPriority < configMAX_PRIORITIES );
|
|
801595e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8015960: 2b37 cmp r3, #55 @ 0x37
|
|
8015962: d90b bls.n 801597c <prvInitialiseNewTask+0xbc>
|
|
__asm volatile
|
|
8015964: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015968: f383 8811 msr BASEPRI, r3
|
|
801596c: f3bf 8f6f isb sy
|
|
8015970: f3bf 8f4f dsb sy
|
|
8015974: 613b str r3, [r7, #16]
|
|
}
|
|
8015976: bf00 nop
|
|
8015978: bf00 nop
|
|
801597a: e7fd b.n 8015978 <prvInitialiseNewTask+0xb8>
|
|
|
|
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
|
|
801597c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
801597e: 2b37 cmp r3, #55 @ 0x37
|
|
8015980: d901 bls.n 8015986 <prvInitialiseNewTask+0xc6>
|
|
{
|
|
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
|
|
8015982: 2337 movs r3, #55 @ 0x37
|
|
8015984: 62bb str r3, [r7, #40] @ 0x28
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxNewTCB->uxPriority = uxPriority;
|
|
8015986: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8015988: 6aba ldr r2, [r7, #40] @ 0x28
|
|
801598a: 62da str r2, [r3, #44] @ 0x2c
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
pxNewTCB->uxBasePriority = uxPriority;
|
|
801598c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
801598e: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8015990: 64da str r2, [r3, #76] @ 0x4c
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
|
|
8015992: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8015994: 3304 adds r3, #4
|
|
8015996: 4618 mov r0, r3
|
|
8015998: f7fe fd08 bl 80143ac <vListInitialiseItem>
|
|
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
|
|
801599c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
801599e: 3318 adds r3, #24
|
|
80159a0: 4618 mov r0, r3
|
|
80159a2: f7fe fd03 bl 80143ac <vListInitialiseItem>
|
|
|
|
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
|
|
* back to the containing TCB from a generic item in a list. */
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
|
|
80159a6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80159a8: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80159aa: 611a str r2, [r3, #16]
|
|
|
|
/* Event lists are always in priority order. */
|
|
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
80159ac: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80159ae: f1c3 0238 rsb r2, r3, #56 @ 0x38
|
|
80159b2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80159b4: 619a str r2, [r3, #24]
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
|
|
80159b6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80159b8: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80159ba: 625a str r2, [r3, #36] @ 0x24
|
|
#endif
|
|
|
|
#if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
|
|
{
|
|
/* Allocate and initialize memory for the task's TLS Block. */
|
|
configINIT_TLS_BLOCK( pxNewTCB->xTLSBlock, pxTopOfStack );
|
|
80159bc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80159be: 3354 adds r3, #84 @ 0x54
|
|
80159c0: 224c movs r2, #76 @ 0x4c
|
|
80159c2: 2100 movs r1, #0
|
|
80159c4: 4618 mov r0, r3
|
|
80159c6: f004 fc9d bl 801a304 <memset>
|
|
80159ca: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80159cc: 4a0c ldr r2, [pc, #48] @ (8015a00 <prvInitialiseNewTask+0x140>)
|
|
80159ce: 659a str r2, [r3, #88] @ 0x58
|
|
80159d0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80159d2: 4a0c ldr r2, [pc, #48] @ (8015a04 <prvInitialiseNewTask+0x144>)
|
|
80159d4: 65da str r2, [r3, #92] @ 0x5c
|
|
80159d6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80159d8: 4a0b ldr r2, [pc, #44] @ (8015a08 <prvInitialiseNewTask+0x148>)
|
|
80159da: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
}
|
|
#else /* portHAS_STACK_OVERFLOW_CHECKING */
|
|
{
|
|
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
|
|
80159dc: 683a ldr r2, [r7, #0]
|
|
80159de: 68f9 ldr r1, [r7, #12]
|
|
80159e0: 69b8 ldr r0, [r7, #24]
|
|
80159e2: f002 f857 bl 8017a94 <pxPortInitialiseStack>
|
|
80159e6: 4602 mov r2, r0
|
|
80159e8: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80159ea: 601a str r2, [r3, #0]
|
|
}
|
|
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
|
|
}
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
|
|
|
if( pxCreatedTask != NULL )
|
|
80159ec: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80159ee: 2b00 cmp r3, #0
|
|
80159f0: d002 beq.n 80159f8 <prvInitialiseNewTask+0x138>
|
|
{
|
|
/* Pass the handle out in an anonymous way. The handle can be used to
|
|
* change the created task's priority, delete the created task, etc.*/
|
|
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
|
|
80159f2: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80159f4: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80159f6: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
80159f8: bf00 nop
|
|
80159fa: 3720 adds r7, #32
|
|
80159fc: 46bd mov sp, r7
|
|
80159fe: bd80 pop {r7, pc}
|
|
8015a00: 20013b9c .word 0x20013b9c
|
|
8015a04: 20013c04 .word 0x20013c04
|
|
8015a08: 20013c6c .word 0x20013c6c
|
|
|
|
08015a0c <prvAddNewTaskToReadyList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
|
|
{
|
|
8015a0c: b580 push {r7, lr}
|
|
8015a0e: b084 sub sp, #16
|
|
8015a10: af00 add r7, sp, #0
|
|
8015a12: 6078 str r0, [r7, #4]
|
|
/* Ensure interrupts don't access the task lists while the lists are being
|
|
* updated. */
|
|
taskENTER_CRITICAL();
|
|
8015a14: f002 f98c bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
uxCurrentNumberOfTasks++;
|
|
8015a18: 4b41 ldr r3, [pc, #260] @ (8015b20 <prvAddNewTaskToReadyList+0x114>)
|
|
8015a1a: 681b ldr r3, [r3, #0]
|
|
8015a1c: 3301 adds r3, #1
|
|
8015a1e: 4a40 ldr r2, [pc, #256] @ (8015b20 <prvAddNewTaskToReadyList+0x114>)
|
|
8015a20: 6013 str r3, [r2, #0]
|
|
|
|
if( pxCurrentTCB == NULL )
|
|
8015a22: 4b40 ldr r3, [pc, #256] @ (8015b24 <prvAddNewTaskToReadyList+0x118>)
|
|
8015a24: 681b ldr r3, [r3, #0]
|
|
8015a26: 2b00 cmp r3, #0
|
|
8015a28: d109 bne.n 8015a3e <prvAddNewTaskToReadyList+0x32>
|
|
{
|
|
/* There are no other tasks, or all the other tasks are in
|
|
* the suspended state - make this the current task. */
|
|
pxCurrentTCB = pxNewTCB;
|
|
8015a2a: 4a3e ldr r2, [pc, #248] @ (8015b24 <prvAddNewTaskToReadyList+0x118>)
|
|
8015a2c: 687b ldr r3, [r7, #4]
|
|
8015a2e: 6013 str r3, [r2, #0]
|
|
|
|
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
|
|
8015a30: 4b3b ldr r3, [pc, #236] @ (8015b20 <prvAddNewTaskToReadyList+0x114>)
|
|
8015a32: 681b ldr r3, [r3, #0]
|
|
8015a34: 2b01 cmp r3, #1
|
|
8015a36: d110 bne.n 8015a5a <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
/* This is the first task to be created so do the preliminary
|
|
* initialisation required. We will not recover if this call
|
|
* fails, but we will report the failure. */
|
|
prvInitialiseTaskLists();
|
|
8015a38: f000 fda4 bl 8016584 <prvInitialiseTaskLists>
|
|
8015a3c: e00d b.n 8015a5a <prvAddNewTaskToReadyList+0x4e>
|
|
else
|
|
{
|
|
/* If the scheduler is not already running, make this task the
|
|
* current task if it is the highest priority task to be created
|
|
* so far. */
|
|
if( xSchedulerRunning == pdFALSE )
|
|
8015a3e: 4b3a ldr r3, [pc, #232] @ (8015b28 <prvAddNewTaskToReadyList+0x11c>)
|
|
8015a40: 681b ldr r3, [r3, #0]
|
|
8015a42: 2b00 cmp r3, #0
|
|
8015a44: d109 bne.n 8015a5a <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
|
|
8015a46: 4b37 ldr r3, [pc, #220] @ (8015b24 <prvAddNewTaskToReadyList+0x118>)
|
|
8015a48: 681b ldr r3, [r3, #0]
|
|
8015a4a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015a4c: 687b ldr r3, [r7, #4]
|
|
8015a4e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8015a50: 429a cmp r2, r3
|
|
8015a52: d802 bhi.n 8015a5a <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
pxCurrentTCB = pxNewTCB;
|
|
8015a54: 4a33 ldr r2, [pc, #204] @ (8015b24 <prvAddNewTaskToReadyList+0x118>)
|
|
8015a56: 687b ldr r3, [r7, #4]
|
|
8015a58: 6013 str r3, [r2, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
uxTaskNumber++;
|
|
8015a5a: 4b34 ldr r3, [pc, #208] @ (8015b2c <prvAddNewTaskToReadyList+0x120>)
|
|
8015a5c: 681b ldr r3, [r3, #0]
|
|
8015a5e: 3301 adds r3, #1
|
|
8015a60: 4a32 ldr r2, [pc, #200] @ (8015b2c <prvAddNewTaskToReadyList+0x120>)
|
|
8015a62: 6013 str r3, [r2, #0]
|
|
|
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
|
{
|
|
/* Add a counter into the TCB for tracing only. */
|
|
pxNewTCB->uxTCBNumber = uxTaskNumber;
|
|
8015a64: 4b31 ldr r3, [pc, #196] @ (8015b2c <prvAddNewTaskToReadyList+0x120>)
|
|
8015a66: 681a ldr r2, [r3, #0]
|
|
8015a68: 687b ldr r3, [r7, #4]
|
|
8015a6a: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
#endif /* configUSE_TRACE_FACILITY */
|
|
traceTASK_CREATE( pxNewTCB );
|
|
|
|
prvAddTaskToReadyList( pxNewTCB );
|
|
8015a6c: 687b ldr r3, [r7, #4]
|
|
8015a6e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015a70: 4b2f ldr r3, [pc, #188] @ (8015b30 <prvAddNewTaskToReadyList+0x124>)
|
|
8015a72: 681b ldr r3, [r3, #0]
|
|
8015a74: 429a cmp r2, r3
|
|
8015a76: d903 bls.n 8015a80 <prvAddNewTaskToReadyList+0x74>
|
|
8015a78: 687b ldr r3, [r7, #4]
|
|
8015a7a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8015a7c: 4a2c ldr r2, [pc, #176] @ (8015b30 <prvAddNewTaskToReadyList+0x124>)
|
|
8015a7e: 6013 str r3, [r2, #0]
|
|
8015a80: 687b ldr r3, [r7, #4]
|
|
8015a82: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015a84: 492b ldr r1, [pc, #172] @ (8015b34 <prvAddNewTaskToReadyList+0x128>)
|
|
8015a86: 4613 mov r3, r2
|
|
8015a88: 009b lsls r3, r3, #2
|
|
8015a8a: 4413 add r3, r2
|
|
8015a8c: 009b lsls r3, r3, #2
|
|
8015a8e: 440b add r3, r1
|
|
8015a90: 3304 adds r3, #4
|
|
8015a92: 681b ldr r3, [r3, #0]
|
|
8015a94: 60fb str r3, [r7, #12]
|
|
8015a96: 687b ldr r3, [r7, #4]
|
|
8015a98: 68fa ldr r2, [r7, #12]
|
|
8015a9a: 609a str r2, [r3, #8]
|
|
8015a9c: 68fb ldr r3, [r7, #12]
|
|
8015a9e: 689a ldr r2, [r3, #8]
|
|
8015aa0: 687b ldr r3, [r7, #4]
|
|
8015aa2: 60da str r2, [r3, #12]
|
|
8015aa4: 68fb ldr r3, [r7, #12]
|
|
8015aa6: 689b ldr r3, [r3, #8]
|
|
8015aa8: 687a ldr r2, [r7, #4]
|
|
8015aaa: 3204 adds r2, #4
|
|
8015aac: 605a str r2, [r3, #4]
|
|
8015aae: 687b ldr r3, [r7, #4]
|
|
8015ab0: 1d1a adds r2, r3, #4
|
|
8015ab2: 68fb ldr r3, [r7, #12]
|
|
8015ab4: 609a str r2, [r3, #8]
|
|
8015ab6: 687b ldr r3, [r7, #4]
|
|
8015ab8: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015aba: 4613 mov r3, r2
|
|
8015abc: 009b lsls r3, r3, #2
|
|
8015abe: 4413 add r3, r2
|
|
8015ac0: 009b lsls r3, r3, #2
|
|
8015ac2: 4a1c ldr r2, [pc, #112] @ (8015b34 <prvAddNewTaskToReadyList+0x128>)
|
|
8015ac4: 441a add r2, r3
|
|
8015ac6: 687b ldr r3, [r7, #4]
|
|
8015ac8: 615a str r2, [r3, #20]
|
|
8015aca: 687b ldr r3, [r7, #4]
|
|
8015acc: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015ace: 4919 ldr r1, [pc, #100] @ (8015b34 <prvAddNewTaskToReadyList+0x128>)
|
|
8015ad0: 4613 mov r3, r2
|
|
8015ad2: 009b lsls r3, r3, #2
|
|
8015ad4: 4413 add r3, r2
|
|
8015ad6: 009b lsls r3, r3, #2
|
|
8015ad8: 440b add r3, r1
|
|
8015ada: 681b ldr r3, [r3, #0]
|
|
8015adc: 1c59 adds r1, r3, #1
|
|
8015ade: 4815 ldr r0, [pc, #84] @ (8015b34 <prvAddNewTaskToReadyList+0x128>)
|
|
8015ae0: 4613 mov r3, r2
|
|
8015ae2: 009b lsls r3, r3, #2
|
|
8015ae4: 4413 add r3, r2
|
|
8015ae6: 009b lsls r3, r3, #2
|
|
8015ae8: 4403 add r3, r0
|
|
8015aea: 6019 str r1, [r3, #0]
|
|
|
|
portSETUP_TCB( pxNewTCB );
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8015aec: f002 f952 bl 8017d94 <vPortExitCritical>
|
|
|
|
if( xSchedulerRunning != pdFALSE )
|
|
8015af0: 4b0d ldr r3, [pc, #52] @ (8015b28 <prvAddNewTaskToReadyList+0x11c>)
|
|
8015af2: 681b ldr r3, [r3, #0]
|
|
8015af4: 2b00 cmp r3, #0
|
|
8015af6: d00e beq.n 8015b16 <prvAddNewTaskToReadyList+0x10a>
|
|
{
|
|
/* If the created task is of a higher priority than the current task
|
|
* then it should run now. */
|
|
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
|
|
8015af8: 4b0a ldr r3, [pc, #40] @ (8015b24 <prvAddNewTaskToReadyList+0x118>)
|
|
8015afa: 681b ldr r3, [r3, #0]
|
|
8015afc: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015afe: 687b ldr r3, [r7, #4]
|
|
8015b00: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8015b02: 429a cmp r2, r3
|
|
8015b04: d207 bcs.n 8015b16 <prvAddNewTaskToReadyList+0x10a>
|
|
{
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
8015b06: 4b0c ldr r3, [pc, #48] @ (8015b38 <prvAddNewTaskToReadyList+0x12c>)
|
|
8015b08: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8015b0c: 601a str r2, [r3, #0]
|
|
8015b0e: f3bf 8f4f dsb sy
|
|
8015b12: f3bf 8f6f isb sy
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
8015b16: bf00 nop
|
|
8015b18: 3710 adds r7, #16
|
|
8015b1a: 46bd mov sp, r7
|
|
8015b1c: bd80 pop {r7, pc}
|
|
8015b1e: bf00 nop
|
|
8015b20: 2000263c .word 0x2000263c
|
|
8015b24: 20002168 .word 0x20002168
|
|
8015b28: 20002648 .word 0x20002648
|
|
8015b2c: 20002658 .word 0x20002658
|
|
8015b30: 20002644 .word 0x20002644
|
|
8015b34: 2000216c .word 0x2000216c
|
|
8015b38: e000ed04 .word 0xe000ed04
|
|
|
|
08015b3c <vTaskStartScheduler>:
|
|
|
|
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskStartScheduler( void )
|
|
{
|
|
8015b3c: b580 push {r7, lr}
|
|
8015b3e: b08a sub sp, #40 @ 0x28
|
|
8015b40: af04 add r7, sp, #16
|
|
BaseType_t xReturn;
|
|
|
|
/* Add the idle task at the lowest priority. */
|
|
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
StaticTask_t * pxIdleTaskTCBBuffer = NULL;
|
|
8015b42: 2300 movs r3, #0
|
|
8015b44: 60bb str r3, [r7, #8]
|
|
StackType_t * pxIdleTaskStackBuffer = NULL;
|
|
8015b46: 2300 movs r3, #0
|
|
8015b48: 607b str r3, [r7, #4]
|
|
uint32_t ulIdleTaskStackSize;
|
|
|
|
/* The Idle task is created using user provided RAM - obtain the
|
|
* address of the RAM then create the idle task. */
|
|
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
|
|
8015b4a: 463a mov r2, r7
|
|
8015b4c: 1d39 adds r1, r7, #4
|
|
8015b4e: f107 0308 add.w r3, r7, #8
|
|
8015b52: 4618 mov r0, r3
|
|
8015b54: f7fe fbd6 bl 8014304 <vApplicationGetIdleTaskMemory>
|
|
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
|
|
8015b58: 6839 ldr r1, [r7, #0]
|
|
8015b5a: 687b ldr r3, [r7, #4]
|
|
8015b5c: 68ba ldr r2, [r7, #8]
|
|
8015b5e: 9202 str r2, [sp, #8]
|
|
8015b60: 9301 str r3, [sp, #4]
|
|
8015b62: 2300 movs r3, #0
|
|
8015b64: 9300 str r3, [sp, #0]
|
|
8015b66: 2300 movs r3, #0
|
|
8015b68: 460a mov r2, r1
|
|
8015b6a: 4925 ldr r1, [pc, #148] @ (8015c00 <vTaskStartScheduler+0xc4>)
|
|
8015b6c: 4825 ldr r0, [pc, #148] @ (8015c04 <vTaskStartScheduler+0xc8>)
|
|
8015b6e: f7ff fdf7 bl 8015760 <xTaskCreateStatic>
|
|
8015b72: 4603 mov r3, r0
|
|
8015b74: 4a24 ldr r2, [pc, #144] @ (8015c08 <vTaskStartScheduler+0xcc>)
|
|
8015b76: 6013 str r3, [r2, #0]
|
|
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
|
|
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
|
|
pxIdleTaskStackBuffer,
|
|
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
|
|
|
|
if( xIdleTaskHandle != NULL )
|
|
8015b78: 4b23 ldr r3, [pc, #140] @ (8015c08 <vTaskStartScheduler+0xcc>)
|
|
8015b7a: 681b ldr r3, [r3, #0]
|
|
8015b7c: 2b00 cmp r3, #0
|
|
8015b7e: d002 beq.n 8015b86 <vTaskStartScheduler+0x4a>
|
|
{
|
|
xReturn = pdPASS;
|
|
8015b80: 2301 movs r3, #1
|
|
8015b82: 617b str r3, [r7, #20]
|
|
8015b84: e001 b.n 8015b8a <vTaskStartScheduler+0x4e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFAIL;
|
|
8015b86: 2300 movs r3, #0
|
|
8015b88: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
|
|
#if ( configUSE_TIMERS == 1 )
|
|
{
|
|
if( xReturn == pdPASS )
|
|
8015b8a: 697b ldr r3, [r7, #20]
|
|
8015b8c: 2b01 cmp r3, #1
|
|
8015b8e: d102 bne.n 8015b96 <vTaskStartScheduler+0x5a>
|
|
{
|
|
xReturn = xTimerCreateTimerTask();
|
|
8015b90: f001 fcb8 bl 8017504 <xTimerCreateTimerTask>
|
|
8015b94: 6178 str r0, [r7, #20]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_TIMERS */
|
|
|
|
if( xReturn == pdPASS )
|
|
8015b96: 697b ldr r3, [r7, #20]
|
|
8015b98: 2b01 cmp r3, #1
|
|
8015b9a: d11b bne.n 8015bd4 <vTaskStartScheduler+0x98>
|
|
__asm volatile
|
|
8015b9c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015ba0: f383 8811 msr BASEPRI, r3
|
|
8015ba4: f3bf 8f6f isb sy
|
|
8015ba8: f3bf 8f4f dsb sy
|
|
8015bac: 613b str r3, [r7, #16]
|
|
}
|
|
8015bae: bf00 nop
|
|
|
|
#if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
|
|
{
|
|
/* Switch C-Runtime's TLS Block to point to the TLS
|
|
* block specific to the task that will run first. */
|
|
configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
|
|
8015bb0: 4b16 ldr r3, [pc, #88] @ (8015c0c <vTaskStartScheduler+0xd0>)
|
|
8015bb2: 681b ldr r3, [r3, #0]
|
|
8015bb4: 3354 adds r3, #84 @ 0x54
|
|
8015bb6: 4a16 ldr r2, [pc, #88] @ (8015c10 <vTaskStartScheduler+0xd4>)
|
|
8015bb8: 6013 str r3, [r2, #0]
|
|
}
|
|
#endif
|
|
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
8015bba: 4b16 ldr r3, [pc, #88] @ (8015c14 <vTaskStartScheduler+0xd8>)
|
|
8015bbc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8015bc0: 601a str r2, [r3, #0]
|
|
xSchedulerRunning = pdTRUE;
|
|
8015bc2: 4b15 ldr r3, [pc, #84] @ (8015c18 <vTaskStartScheduler+0xdc>)
|
|
8015bc4: 2201 movs r2, #1
|
|
8015bc6: 601a str r2, [r3, #0]
|
|
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
|
|
8015bc8: 4b14 ldr r3, [pc, #80] @ (8015c1c <vTaskStartScheduler+0xe0>)
|
|
8015bca: 2200 movs r2, #0
|
|
8015bcc: 601a str r2, [r3, #0]
|
|
|
|
traceTASK_SWITCHED_IN();
|
|
|
|
/* Setting up the timer tick is hardware specific and thus in the
|
|
* portable interface. */
|
|
xPortStartScheduler();
|
|
8015bce: f001 fff1 bl 8017bb4 <xPortStartScheduler>
|
|
8015bd2: e00f b.n 8015bf4 <vTaskStartScheduler+0xb8>
|
|
else
|
|
{
|
|
/* This line will only be reached if the kernel could not be started,
|
|
* because there was not enough FreeRTOS heap to create the idle task
|
|
* or the timer task. */
|
|
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
|
|
8015bd4: 697b ldr r3, [r7, #20]
|
|
8015bd6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8015bda: d10b bne.n 8015bf4 <vTaskStartScheduler+0xb8>
|
|
__asm volatile
|
|
8015bdc: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015be0: f383 8811 msr BASEPRI, r3
|
|
8015be4: f3bf 8f6f isb sy
|
|
8015be8: f3bf 8f4f dsb sy
|
|
8015bec: 60fb str r3, [r7, #12]
|
|
}
|
|
8015bee: bf00 nop
|
|
8015bf0: bf00 nop
|
|
8015bf2: e7fd b.n 8015bf0 <vTaskStartScheduler+0xb4>
|
|
* meaning xIdleTaskHandle is not used anywhere else. */
|
|
( void ) xIdleTaskHandle;
|
|
|
|
/* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
|
|
* from getting optimized out as it is no longer used by the kernel. */
|
|
( void ) uxTopUsedPriority;
|
|
8015bf4: 4b0a ldr r3, [pc, #40] @ (8015c20 <vTaskStartScheduler+0xe4>)
|
|
8015bf6: 681b ldr r3, [r3, #0]
|
|
}
|
|
8015bf8: bf00 nop
|
|
8015bfa: 3718 adds r7, #24
|
|
8015bfc: 46bd mov sp, r7
|
|
8015bfe: bd80 pop {r7, pc}
|
|
8015c00: 0801e31c .word 0x0801e31c
|
|
8015c04: 08016555 .word 0x08016555
|
|
8015c08: 20002660 .word 0x20002660
|
|
8015c0c: 20002168 .word 0x20002168
|
|
8015c10: 2000011c .word 0x2000011c
|
|
8015c14: 2000265c .word 0x2000265c
|
|
8015c18: 20002648 .word 0x20002648
|
|
8015c1c: 20002640 .word 0x20002640
|
|
8015c20: 0801e60c .word 0x0801e60c
|
|
|
|
08015c24 <vTaskSuspendAll>:
|
|
vPortEndScheduler();
|
|
}
|
|
/*----------------------------------------------------------*/
|
|
|
|
void vTaskSuspendAll( void )
|
|
{
|
|
8015c24: b480 push {r7}
|
|
8015c26: af00 add r7, sp, #0
|
|
* do not otherwise exhibit real time behaviour. */
|
|
portSOFTWARE_BARRIER();
|
|
|
|
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
|
|
* is used to allow calls to vTaskSuspendAll() to nest. */
|
|
++uxSchedulerSuspended;
|
|
8015c28: 4b04 ldr r3, [pc, #16] @ (8015c3c <vTaskSuspendAll+0x18>)
|
|
8015c2a: 681b ldr r3, [r3, #0]
|
|
8015c2c: 3301 adds r3, #1
|
|
8015c2e: 4a03 ldr r2, [pc, #12] @ (8015c3c <vTaskSuspendAll+0x18>)
|
|
8015c30: 6013 str r3, [r2, #0]
|
|
|
|
/* Enforces ordering for ports and optimised compilers that may otherwise place
|
|
* the above increment elsewhere. */
|
|
portMEMORY_BARRIER();
|
|
}
|
|
8015c32: bf00 nop
|
|
8015c34: 46bd mov sp, r7
|
|
8015c36: f85d 7b04 ldr.w r7, [sp], #4
|
|
8015c3a: 4770 bx lr
|
|
8015c3c: 20002664 .word 0x20002664
|
|
|
|
08015c40 <xTaskResumeAll>:
|
|
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskResumeAll( void )
|
|
{
|
|
8015c40: b580 push {r7, lr}
|
|
8015c42: b088 sub sp, #32
|
|
8015c44: af00 add r7, sp, #0
|
|
TCB_t * pxTCB = NULL;
|
|
8015c46: 2300 movs r3, #0
|
|
8015c48: 61fb str r3, [r7, #28]
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
|
8015c4a: 2300 movs r3, #0
|
|
8015c4c: 61bb str r3, [r7, #24]
|
|
|
|
/* If uxSchedulerSuspended is zero then this function does not match a
|
|
* previous call to vTaskSuspendAll(). */
|
|
configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
|
|
8015c4e: 4b72 ldr r3, [pc, #456] @ (8015e18 <xTaskResumeAll+0x1d8>)
|
|
8015c50: 681b ldr r3, [r3, #0]
|
|
8015c52: 2b00 cmp r3, #0
|
|
8015c54: d10b bne.n 8015c6e <xTaskResumeAll+0x2e>
|
|
__asm volatile
|
|
8015c56: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015c5a: f383 8811 msr BASEPRI, r3
|
|
8015c5e: f3bf 8f6f isb sy
|
|
8015c62: f3bf 8f4f dsb sy
|
|
8015c66: 607b str r3, [r7, #4]
|
|
}
|
|
8015c68: bf00 nop
|
|
8015c6a: bf00 nop
|
|
8015c6c: e7fd b.n 8015c6a <xTaskResumeAll+0x2a>
|
|
/* It is possible that an ISR caused a task to be removed from an event
|
|
* list while the scheduler was suspended. If this was the case then the
|
|
* removed task will have been added to the xPendingReadyList. Once the
|
|
* scheduler has been resumed it is safe to move all the pending ready
|
|
* tasks from this list into their appropriate ready list. */
|
|
taskENTER_CRITICAL();
|
|
8015c6e: f002 f85f bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
--uxSchedulerSuspended;
|
|
8015c72: 4b69 ldr r3, [pc, #420] @ (8015e18 <xTaskResumeAll+0x1d8>)
|
|
8015c74: 681b ldr r3, [r3, #0]
|
|
8015c76: 3b01 subs r3, #1
|
|
8015c78: 4a67 ldr r2, [pc, #412] @ (8015e18 <xTaskResumeAll+0x1d8>)
|
|
8015c7a: 6013 str r3, [r2, #0]
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
|
|
8015c7c: 4b66 ldr r3, [pc, #408] @ (8015e18 <xTaskResumeAll+0x1d8>)
|
|
8015c7e: 681b ldr r3, [r3, #0]
|
|
8015c80: 2b00 cmp r3, #0
|
|
8015c82: f040 80c1 bne.w 8015e08 <xTaskResumeAll+0x1c8>
|
|
{
|
|
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
|
|
8015c86: 4b65 ldr r3, [pc, #404] @ (8015e1c <xTaskResumeAll+0x1dc>)
|
|
8015c88: 681b ldr r3, [r3, #0]
|
|
8015c8a: 2b00 cmp r3, #0
|
|
8015c8c: f000 80bc beq.w 8015e08 <xTaskResumeAll+0x1c8>
|
|
{
|
|
/* Move any readied tasks from the pending list into the
|
|
* appropriate ready list. */
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
8015c90: e08b b.n 8015daa <xTaskResumeAll+0x16a>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
8015c92: 4b63 ldr r3, [pc, #396] @ (8015e20 <xTaskResumeAll+0x1e0>)
|
|
8015c94: 68db ldr r3, [r3, #12]
|
|
8015c96: 68db ldr r3, [r3, #12]
|
|
8015c98: 61fb str r3, [r7, #28]
|
|
listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
|
|
8015c9a: 69fb ldr r3, [r7, #28]
|
|
8015c9c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8015c9e: 613b str r3, [r7, #16]
|
|
8015ca0: 69fb ldr r3, [r7, #28]
|
|
8015ca2: 69db ldr r3, [r3, #28]
|
|
8015ca4: 69fa ldr r2, [r7, #28]
|
|
8015ca6: 6a12 ldr r2, [r2, #32]
|
|
8015ca8: 609a str r2, [r3, #8]
|
|
8015caa: 69fb ldr r3, [r7, #28]
|
|
8015cac: 6a1b ldr r3, [r3, #32]
|
|
8015cae: 69fa ldr r2, [r7, #28]
|
|
8015cb0: 69d2 ldr r2, [r2, #28]
|
|
8015cb2: 605a str r2, [r3, #4]
|
|
8015cb4: 693b ldr r3, [r7, #16]
|
|
8015cb6: 685a ldr r2, [r3, #4]
|
|
8015cb8: 69fb ldr r3, [r7, #28]
|
|
8015cba: 3318 adds r3, #24
|
|
8015cbc: 429a cmp r2, r3
|
|
8015cbe: d103 bne.n 8015cc8 <xTaskResumeAll+0x88>
|
|
8015cc0: 69fb ldr r3, [r7, #28]
|
|
8015cc2: 6a1a ldr r2, [r3, #32]
|
|
8015cc4: 693b ldr r3, [r7, #16]
|
|
8015cc6: 605a str r2, [r3, #4]
|
|
8015cc8: 69fb ldr r3, [r7, #28]
|
|
8015cca: 2200 movs r2, #0
|
|
8015ccc: 629a str r2, [r3, #40] @ 0x28
|
|
8015cce: 693b ldr r3, [r7, #16]
|
|
8015cd0: 681b ldr r3, [r3, #0]
|
|
8015cd2: 1e5a subs r2, r3, #1
|
|
8015cd4: 693b ldr r3, [r7, #16]
|
|
8015cd6: 601a str r2, [r3, #0]
|
|
portMEMORY_BARRIER();
|
|
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
|
|
8015cd8: 69fb ldr r3, [r7, #28]
|
|
8015cda: 695b ldr r3, [r3, #20]
|
|
8015cdc: 60fb str r3, [r7, #12]
|
|
8015cde: 69fb ldr r3, [r7, #28]
|
|
8015ce0: 689b ldr r3, [r3, #8]
|
|
8015ce2: 69fa ldr r2, [r7, #28]
|
|
8015ce4: 68d2 ldr r2, [r2, #12]
|
|
8015ce6: 609a str r2, [r3, #8]
|
|
8015ce8: 69fb ldr r3, [r7, #28]
|
|
8015cea: 68db ldr r3, [r3, #12]
|
|
8015cec: 69fa ldr r2, [r7, #28]
|
|
8015cee: 6892 ldr r2, [r2, #8]
|
|
8015cf0: 605a str r2, [r3, #4]
|
|
8015cf2: 68fb ldr r3, [r7, #12]
|
|
8015cf4: 685a ldr r2, [r3, #4]
|
|
8015cf6: 69fb ldr r3, [r7, #28]
|
|
8015cf8: 3304 adds r3, #4
|
|
8015cfa: 429a cmp r2, r3
|
|
8015cfc: d103 bne.n 8015d06 <xTaskResumeAll+0xc6>
|
|
8015cfe: 69fb ldr r3, [r7, #28]
|
|
8015d00: 68da ldr r2, [r3, #12]
|
|
8015d02: 68fb ldr r3, [r7, #12]
|
|
8015d04: 605a str r2, [r3, #4]
|
|
8015d06: 69fb ldr r3, [r7, #28]
|
|
8015d08: 2200 movs r2, #0
|
|
8015d0a: 615a str r2, [r3, #20]
|
|
8015d0c: 68fb ldr r3, [r7, #12]
|
|
8015d0e: 681b ldr r3, [r3, #0]
|
|
8015d10: 1e5a subs r2, r3, #1
|
|
8015d12: 68fb ldr r3, [r7, #12]
|
|
8015d14: 601a str r2, [r3, #0]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
8015d16: 69fb ldr r3, [r7, #28]
|
|
8015d18: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015d1a: 4b42 ldr r3, [pc, #264] @ (8015e24 <xTaskResumeAll+0x1e4>)
|
|
8015d1c: 681b ldr r3, [r3, #0]
|
|
8015d1e: 429a cmp r2, r3
|
|
8015d20: d903 bls.n 8015d2a <xTaskResumeAll+0xea>
|
|
8015d22: 69fb ldr r3, [r7, #28]
|
|
8015d24: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8015d26: 4a3f ldr r2, [pc, #252] @ (8015e24 <xTaskResumeAll+0x1e4>)
|
|
8015d28: 6013 str r3, [r2, #0]
|
|
8015d2a: 69fb ldr r3, [r7, #28]
|
|
8015d2c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015d2e: 493e ldr r1, [pc, #248] @ (8015e28 <xTaskResumeAll+0x1e8>)
|
|
8015d30: 4613 mov r3, r2
|
|
8015d32: 009b lsls r3, r3, #2
|
|
8015d34: 4413 add r3, r2
|
|
8015d36: 009b lsls r3, r3, #2
|
|
8015d38: 440b add r3, r1
|
|
8015d3a: 3304 adds r3, #4
|
|
8015d3c: 681b ldr r3, [r3, #0]
|
|
8015d3e: 60bb str r3, [r7, #8]
|
|
8015d40: 69fb ldr r3, [r7, #28]
|
|
8015d42: 68ba ldr r2, [r7, #8]
|
|
8015d44: 609a str r2, [r3, #8]
|
|
8015d46: 68bb ldr r3, [r7, #8]
|
|
8015d48: 689a ldr r2, [r3, #8]
|
|
8015d4a: 69fb ldr r3, [r7, #28]
|
|
8015d4c: 60da str r2, [r3, #12]
|
|
8015d4e: 68bb ldr r3, [r7, #8]
|
|
8015d50: 689b ldr r3, [r3, #8]
|
|
8015d52: 69fa ldr r2, [r7, #28]
|
|
8015d54: 3204 adds r2, #4
|
|
8015d56: 605a str r2, [r3, #4]
|
|
8015d58: 69fb ldr r3, [r7, #28]
|
|
8015d5a: 1d1a adds r2, r3, #4
|
|
8015d5c: 68bb ldr r3, [r7, #8]
|
|
8015d5e: 609a str r2, [r3, #8]
|
|
8015d60: 69fb ldr r3, [r7, #28]
|
|
8015d62: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015d64: 4613 mov r3, r2
|
|
8015d66: 009b lsls r3, r3, #2
|
|
8015d68: 4413 add r3, r2
|
|
8015d6a: 009b lsls r3, r3, #2
|
|
8015d6c: 4a2e ldr r2, [pc, #184] @ (8015e28 <xTaskResumeAll+0x1e8>)
|
|
8015d6e: 441a add r2, r3
|
|
8015d70: 69fb ldr r3, [r7, #28]
|
|
8015d72: 615a str r2, [r3, #20]
|
|
8015d74: 69fb ldr r3, [r7, #28]
|
|
8015d76: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015d78: 492b ldr r1, [pc, #172] @ (8015e28 <xTaskResumeAll+0x1e8>)
|
|
8015d7a: 4613 mov r3, r2
|
|
8015d7c: 009b lsls r3, r3, #2
|
|
8015d7e: 4413 add r3, r2
|
|
8015d80: 009b lsls r3, r3, #2
|
|
8015d82: 440b add r3, r1
|
|
8015d84: 681b ldr r3, [r3, #0]
|
|
8015d86: 1c59 adds r1, r3, #1
|
|
8015d88: 4827 ldr r0, [pc, #156] @ (8015e28 <xTaskResumeAll+0x1e8>)
|
|
8015d8a: 4613 mov r3, r2
|
|
8015d8c: 009b lsls r3, r3, #2
|
|
8015d8e: 4413 add r3, r2
|
|
8015d90: 009b lsls r3, r3, #2
|
|
8015d92: 4403 add r3, r0
|
|
8015d94: 6019 str r1, [r3, #0]
|
|
|
|
/* If the moved task has a priority higher than the current
|
|
* task then a yield must be performed. */
|
|
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
8015d96: 69fb ldr r3, [r7, #28]
|
|
8015d98: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015d9a: 4b24 ldr r3, [pc, #144] @ (8015e2c <xTaskResumeAll+0x1ec>)
|
|
8015d9c: 681b ldr r3, [r3, #0]
|
|
8015d9e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8015da0: 429a cmp r2, r3
|
|
8015da2: d902 bls.n 8015daa <xTaskResumeAll+0x16a>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
8015da4: 4b22 ldr r3, [pc, #136] @ (8015e30 <xTaskResumeAll+0x1f0>)
|
|
8015da6: 2201 movs r2, #1
|
|
8015da8: 601a str r2, [r3, #0]
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
8015daa: 4b1d ldr r3, [pc, #116] @ (8015e20 <xTaskResumeAll+0x1e0>)
|
|
8015dac: 681b ldr r3, [r3, #0]
|
|
8015dae: 2b00 cmp r3, #0
|
|
8015db0: f47f af6f bne.w 8015c92 <xTaskResumeAll+0x52>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( pxTCB != NULL )
|
|
8015db4: 69fb ldr r3, [r7, #28]
|
|
8015db6: 2b00 cmp r3, #0
|
|
8015db8: d001 beq.n 8015dbe <xTaskResumeAll+0x17e>
|
|
* which may have prevented the next unblock time from being
|
|
* re-calculated, in which case re-calculate it now. Mainly
|
|
* important for low power tickless implementations, where
|
|
* this can prevent an unnecessary exit from low power
|
|
* state. */
|
|
prvResetNextTaskUnblockTime();
|
|
8015dba: f000 fc89 bl 80166d0 <prvResetNextTaskUnblockTime>
|
|
/* If any ticks occurred while the scheduler was suspended then
|
|
* they should be processed now. This ensures the tick count does
|
|
* not slip, and that any delayed tasks are resumed at the correct
|
|
* time. */
|
|
{
|
|
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
|
|
8015dbe: 4b1d ldr r3, [pc, #116] @ (8015e34 <xTaskResumeAll+0x1f4>)
|
|
8015dc0: 681b ldr r3, [r3, #0]
|
|
8015dc2: 617b str r3, [r7, #20]
|
|
|
|
if( xPendedCounts > ( TickType_t ) 0U )
|
|
8015dc4: 697b ldr r3, [r7, #20]
|
|
8015dc6: 2b00 cmp r3, #0
|
|
8015dc8: d010 beq.n 8015dec <xTaskResumeAll+0x1ac>
|
|
{
|
|
do
|
|
{
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
8015dca: f000 f853 bl 8015e74 <xTaskIncrementTick>
|
|
8015dce: 4603 mov r3, r0
|
|
8015dd0: 2b00 cmp r3, #0
|
|
8015dd2: d002 beq.n 8015dda <xTaskResumeAll+0x19a>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
8015dd4: 4b16 ldr r3, [pc, #88] @ (8015e30 <xTaskResumeAll+0x1f0>)
|
|
8015dd6: 2201 movs r2, #1
|
|
8015dd8: 601a str r2, [r3, #0]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
--xPendedCounts;
|
|
8015dda: 697b ldr r3, [r7, #20]
|
|
8015ddc: 3b01 subs r3, #1
|
|
8015dde: 617b str r3, [r7, #20]
|
|
} while( xPendedCounts > ( TickType_t ) 0U );
|
|
8015de0: 697b ldr r3, [r7, #20]
|
|
8015de2: 2b00 cmp r3, #0
|
|
8015de4: d1f1 bne.n 8015dca <xTaskResumeAll+0x18a>
|
|
|
|
xPendedTicks = 0;
|
|
8015de6: 4b13 ldr r3, [pc, #76] @ (8015e34 <xTaskResumeAll+0x1f4>)
|
|
8015de8: 2200 movs r2, #0
|
|
8015dea: 601a str r2, [r3, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( xYieldPending != pdFALSE )
|
|
8015dec: 4b10 ldr r3, [pc, #64] @ (8015e30 <xTaskResumeAll+0x1f0>)
|
|
8015dee: 681b ldr r3, [r3, #0]
|
|
8015df0: 2b00 cmp r3, #0
|
|
8015df2: d009 beq.n 8015e08 <xTaskResumeAll+0x1c8>
|
|
{
|
|
#if ( configUSE_PREEMPTION != 0 )
|
|
{
|
|
xAlreadyYielded = pdTRUE;
|
|
8015df4: 2301 movs r3, #1
|
|
8015df6: 61bb str r3, [r7, #24]
|
|
}
|
|
#endif
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
8015df8: 4b0f ldr r3, [pc, #60] @ (8015e38 <xTaskResumeAll+0x1f8>)
|
|
8015dfa: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8015dfe: 601a str r2, [r3, #0]
|
|
8015e00: f3bf 8f4f dsb sy
|
|
8015e04: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8015e08: f001 ffc4 bl 8017d94 <vPortExitCritical>
|
|
|
|
return xAlreadyYielded;
|
|
8015e0c: 69bb ldr r3, [r7, #24]
|
|
}
|
|
8015e0e: 4618 mov r0, r3
|
|
8015e10: 3720 adds r7, #32
|
|
8015e12: 46bd mov sp, r7
|
|
8015e14: bd80 pop {r7, pc}
|
|
8015e16: bf00 nop
|
|
8015e18: 20002664 .word 0x20002664
|
|
8015e1c: 2000263c .word 0x2000263c
|
|
8015e20: 200025fc .word 0x200025fc
|
|
8015e24: 20002644 .word 0x20002644
|
|
8015e28: 2000216c .word 0x2000216c
|
|
8015e2c: 20002168 .word 0x20002168
|
|
8015e30: 20002650 .word 0x20002650
|
|
8015e34: 2000264c .word 0x2000264c
|
|
8015e38: e000ed04 .word 0xe000ed04
|
|
|
|
08015e3c <xTaskGetTickCount>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
TickType_t xTaskGetTickCount( void )
|
|
{
|
|
8015e3c: b480 push {r7}
|
|
8015e3e: b083 sub sp, #12
|
|
8015e40: af00 add r7, sp, #0
|
|
TickType_t xTicks;
|
|
|
|
/* Critical section required if running on a 16 bit processor. */
|
|
portTICK_TYPE_ENTER_CRITICAL();
|
|
{
|
|
xTicks = xTickCount;
|
|
8015e42: 4b05 ldr r3, [pc, #20] @ (8015e58 <xTaskGetTickCount+0x1c>)
|
|
8015e44: 681b ldr r3, [r3, #0]
|
|
8015e46: 607b str r3, [r7, #4]
|
|
}
|
|
portTICK_TYPE_EXIT_CRITICAL();
|
|
|
|
return xTicks;
|
|
8015e48: 687b ldr r3, [r7, #4]
|
|
}
|
|
8015e4a: 4618 mov r0, r3
|
|
8015e4c: 370c adds r7, #12
|
|
8015e4e: 46bd mov sp, r7
|
|
8015e50: f85d 7b04 ldr.w r7, [sp], #4
|
|
8015e54: 4770 bx lr
|
|
8015e56: bf00 nop
|
|
8015e58: 20002640 .word 0x20002640
|
|
|
|
08015e5c <uxTaskGetNumberOfTasks>:
|
|
return xReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxTaskGetNumberOfTasks( void )
|
|
{
|
|
8015e5c: b480 push {r7}
|
|
8015e5e: af00 add r7, sp, #0
|
|
/* A critical section is not required because the variables are of type
|
|
* BaseType_t. */
|
|
return uxCurrentNumberOfTasks;
|
|
8015e60: 4b03 ldr r3, [pc, #12] @ (8015e70 <uxTaskGetNumberOfTasks+0x14>)
|
|
8015e62: 681b ldr r3, [r3, #0]
|
|
}
|
|
8015e64: 4618 mov r0, r3
|
|
8015e66: 46bd mov sp, r7
|
|
8015e68: f85d 7b04 ldr.w r7, [sp], #4
|
|
8015e6c: 4770 bx lr
|
|
8015e6e: bf00 nop
|
|
8015e70: 2000263c .word 0x2000263c
|
|
|
|
08015e74 <xTaskIncrementTick>:
|
|
|
|
#endif /* INCLUDE_xTaskAbortDelay */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskIncrementTick( void )
|
|
{
|
|
8015e74: b580 push {r7, lr}
|
|
8015e76: b08a sub sp, #40 @ 0x28
|
|
8015e78: af00 add r7, sp, #0
|
|
TCB_t * pxTCB;
|
|
TickType_t xItemValue;
|
|
BaseType_t xSwitchRequired = pdFALSE;
|
|
8015e7a: 2300 movs r3, #0
|
|
8015e7c: 627b str r3, [r7, #36] @ 0x24
|
|
/* Called by the portable layer each time a tick interrupt occurs.
|
|
* Increments the tick then checks to see if the new tick value will cause any
|
|
* tasks to be unblocked. */
|
|
traceTASK_INCREMENT_TICK( xTickCount );
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
|
|
8015e7e: 4b7e ldr r3, [pc, #504] @ (8016078 <xTaskIncrementTick+0x204>)
|
|
8015e80: 681b ldr r3, [r3, #0]
|
|
8015e82: 2b00 cmp r3, #0
|
|
8015e84: f040 80ee bne.w 8016064 <xTaskIncrementTick+0x1f0>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this
|
|
* block. */
|
|
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
|
|
8015e88: 4b7c ldr r3, [pc, #496] @ (801607c <xTaskIncrementTick+0x208>)
|
|
8015e8a: 681b ldr r3, [r3, #0]
|
|
8015e8c: 3301 adds r3, #1
|
|
8015e8e: 623b str r3, [r7, #32]
|
|
|
|
/* Increment the RTOS tick, switching the delayed and overflowed
|
|
* delayed lists if it wraps to 0. */
|
|
xTickCount = xConstTickCount;
|
|
8015e90: 4a7a ldr r2, [pc, #488] @ (801607c <xTaskIncrementTick+0x208>)
|
|
8015e92: 6a3b ldr r3, [r7, #32]
|
|
8015e94: 6013 str r3, [r2, #0]
|
|
|
|
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
|
|
8015e96: 6a3b ldr r3, [r7, #32]
|
|
8015e98: 2b00 cmp r3, #0
|
|
8015e9a: d121 bne.n 8015ee0 <xTaskIncrementTick+0x6c>
|
|
{
|
|
taskSWITCH_DELAYED_LISTS();
|
|
8015e9c: 4b78 ldr r3, [pc, #480] @ (8016080 <xTaskIncrementTick+0x20c>)
|
|
8015e9e: 681b ldr r3, [r3, #0]
|
|
8015ea0: 681b ldr r3, [r3, #0]
|
|
8015ea2: 2b00 cmp r3, #0
|
|
8015ea4: d00b beq.n 8015ebe <xTaskIncrementTick+0x4a>
|
|
__asm volatile
|
|
8015ea6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8015eaa: f383 8811 msr BASEPRI, r3
|
|
8015eae: f3bf 8f6f isb sy
|
|
8015eb2: f3bf 8f4f dsb sy
|
|
8015eb6: 607b str r3, [r7, #4]
|
|
}
|
|
8015eb8: bf00 nop
|
|
8015eba: bf00 nop
|
|
8015ebc: e7fd b.n 8015eba <xTaskIncrementTick+0x46>
|
|
8015ebe: 4b70 ldr r3, [pc, #448] @ (8016080 <xTaskIncrementTick+0x20c>)
|
|
8015ec0: 681b ldr r3, [r3, #0]
|
|
8015ec2: 61fb str r3, [r7, #28]
|
|
8015ec4: 4b6f ldr r3, [pc, #444] @ (8016084 <xTaskIncrementTick+0x210>)
|
|
8015ec6: 681b ldr r3, [r3, #0]
|
|
8015ec8: 4a6d ldr r2, [pc, #436] @ (8016080 <xTaskIncrementTick+0x20c>)
|
|
8015eca: 6013 str r3, [r2, #0]
|
|
8015ecc: 4a6d ldr r2, [pc, #436] @ (8016084 <xTaskIncrementTick+0x210>)
|
|
8015ece: 69fb ldr r3, [r7, #28]
|
|
8015ed0: 6013 str r3, [r2, #0]
|
|
8015ed2: 4b6d ldr r3, [pc, #436] @ (8016088 <xTaskIncrementTick+0x214>)
|
|
8015ed4: 681b ldr r3, [r3, #0]
|
|
8015ed6: 3301 adds r3, #1
|
|
8015ed8: 4a6b ldr r2, [pc, #428] @ (8016088 <xTaskIncrementTick+0x214>)
|
|
8015eda: 6013 str r3, [r2, #0]
|
|
8015edc: f000 fbf8 bl 80166d0 <prvResetNextTaskUnblockTime>
|
|
|
|
/* See if this tick has made a timeout expire. Tasks are stored in
|
|
* the queue in the order of their wake time - meaning once one task
|
|
* has been found whose block time has not expired there is no need to
|
|
* look any further down the list. */
|
|
if( xConstTickCount >= xNextTaskUnblockTime )
|
|
8015ee0: 4b6a ldr r3, [pc, #424] @ (801608c <xTaskIncrementTick+0x218>)
|
|
8015ee2: 681b ldr r3, [r3, #0]
|
|
8015ee4: 6a3a ldr r2, [r7, #32]
|
|
8015ee6: 429a cmp r2, r3
|
|
8015ee8: f0c0 80a7 bcc.w 801603a <xTaskIncrementTick+0x1c6>
|
|
{
|
|
for( ; ; )
|
|
{
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
8015eec: 4b64 ldr r3, [pc, #400] @ (8016080 <xTaskIncrementTick+0x20c>)
|
|
8015eee: 681b ldr r3, [r3, #0]
|
|
8015ef0: 681b ldr r3, [r3, #0]
|
|
8015ef2: 2b00 cmp r3, #0
|
|
8015ef4: d104 bne.n 8015f00 <xTaskIncrementTick+0x8c>
|
|
/* The delayed list is empty. Set xNextTaskUnblockTime
|
|
* to the maximum possible value so it is extremely
|
|
* unlikely that the
|
|
* if( xTickCount >= xNextTaskUnblockTime ) test will pass
|
|
* next time through. */
|
|
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
8015ef6: 4b65 ldr r3, [pc, #404] @ (801608c <xTaskIncrementTick+0x218>)
|
|
8015ef8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8015efc: 601a str r2, [r3, #0]
|
|
break;
|
|
8015efe: e09c b.n 801603a <xTaskIncrementTick+0x1c6>
|
|
{
|
|
/* The delayed list is not empty, get the value of the
|
|
* item at the head of the delayed list. This is the time
|
|
* at which the task at the head of the delayed list must
|
|
* be removed from the Blocked state. */
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
8015f00: 4b5f ldr r3, [pc, #380] @ (8016080 <xTaskIncrementTick+0x20c>)
|
|
8015f02: 681b ldr r3, [r3, #0]
|
|
8015f04: 68db ldr r3, [r3, #12]
|
|
8015f06: 68db ldr r3, [r3, #12]
|
|
8015f08: 61bb str r3, [r7, #24]
|
|
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
|
|
8015f0a: 69bb ldr r3, [r7, #24]
|
|
8015f0c: 685b ldr r3, [r3, #4]
|
|
8015f0e: 617b str r3, [r7, #20]
|
|
|
|
if( xConstTickCount < xItemValue )
|
|
8015f10: 6a3a ldr r2, [r7, #32]
|
|
8015f12: 697b ldr r3, [r7, #20]
|
|
8015f14: 429a cmp r2, r3
|
|
8015f16: d203 bcs.n 8015f20 <xTaskIncrementTick+0xac>
|
|
/* It is not time to unblock this item yet, but the
|
|
* item value is the time at which the task at the head
|
|
* of the blocked list must be removed from the Blocked
|
|
* state - so record the item value in
|
|
* xNextTaskUnblockTime. */
|
|
xNextTaskUnblockTime = xItemValue;
|
|
8015f18: 4a5c ldr r2, [pc, #368] @ (801608c <xTaskIncrementTick+0x218>)
|
|
8015f1a: 697b ldr r3, [r7, #20]
|
|
8015f1c: 6013 str r3, [r2, #0]
|
|
break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */
|
|
8015f1e: e08c b.n 801603a <xTaskIncrementTick+0x1c6>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* It is time to remove the item from the Blocked state. */
|
|
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
|
|
8015f20: 69bb ldr r3, [r7, #24]
|
|
8015f22: 695b ldr r3, [r3, #20]
|
|
8015f24: 613b str r3, [r7, #16]
|
|
8015f26: 69bb ldr r3, [r7, #24]
|
|
8015f28: 689b ldr r3, [r3, #8]
|
|
8015f2a: 69ba ldr r2, [r7, #24]
|
|
8015f2c: 68d2 ldr r2, [r2, #12]
|
|
8015f2e: 609a str r2, [r3, #8]
|
|
8015f30: 69bb ldr r3, [r7, #24]
|
|
8015f32: 68db ldr r3, [r3, #12]
|
|
8015f34: 69ba ldr r2, [r7, #24]
|
|
8015f36: 6892 ldr r2, [r2, #8]
|
|
8015f38: 605a str r2, [r3, #4]
|
|
8015f3a: 693b ldr r3, [r7, #16]
|
|
8015f3c: 685a ldr r2, [r3, #4]
|
|
8015f3e: 69bb ldr r3, [r7, #24]
|
|
8015f40: 3304 adds r3, #4
|
|
8015f42: 429a cmp r2, r3
|
|
8015f44: d103 bne.n 8015f4e <xTaskIncrementTick+0xda>
|
|
8015f46: 69bb ldr r3, [r7, #24]
|
|
8015f48: 68da ldr r2, [r3, #12]
|
|
8015f4a: 693b ldr r3, [r7, #16]
|
|
8015f4c: 605a str r2, [r3, #4]
|
|
8015f4e: 69bb ldr r3, [r7, #24]
|
|
8015f50: 2200 movs r2, #0
|
|
8015f52: 615a str r2, [r3, #20]
|
|
8015f54: 693b ldr r3, [r7, #16]
|
|
8015f56: 681b ldr r3, [r3, #0]
|
|
8015f58: 1e5a subs r2, r3, #1
|
|
8015f5a: 693b ldr r3, [r7, #16]
|
|
8015f5c: 601a str r2, [r3, #0]
|
|
|
|
/* Is the task waiting on an event also? If so remove
|
|
* it from the event list. */
|
|
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
|
|
8015f5e: 69bb ldr r3, [r7, #24]
|
|
8015f60: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8015f62: 2b00 cmp r3, #0
|
|
8015f64: d01e beq.n 8015fa4 <xTaskIncrementTick+0x130>
|
|
{
|
|
listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
|
|
8015f66: 69bb ldr r3, [r7, #24]
|
|
8015f68: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8015f6a: 60fb str r3, [r7, #12]
|
|
8015f6c: 69bb ldr r3, [r7, #24]
|
|
8015f6e: 69db ldr r3, [r3, #28]
|
|
8015f70: 69ba ldr r2, [r7, #24]
|
|
8015f72: 6a12 ldr r2, [r2, #32]
|
|
8015f74: 609a str r2, [r3, #8]
|
|
8015f76: 69bb ldr r3, [r7, #24]
|
|
8015f78: 6a1b ldr r3, [r3, #32]
|
|
8015f7a: 69ba ldr r2, [r7, #24]
|
|
8015f7c: 69d2 ldr r2, [r2, #28]
|
|
8015f7e: 605a str r2, [r3, #4]
|
|
8015f80: 68fb ldr r3, [r7, #12]
|
|
8015f82: 685a ldr r2, [r3, #4]
|
|
8015f84: 69bb ldr r3, [r7, #24]
|
|
8015f86: 3318 adds r3, #24
|
|
8015f88: 429a cmp r2, r3
|
|
8015f8a: d103 bne.n 8015f94 <xTaskIncrementTick+0x120>
|
|
8015f8c: 69bb ldr r3, [r7, #24]
|
|
8015f8e: 6a1a ldr r2, [r3, #32]
|
|
8015f90: 68fb ldr r3, [r7, #12]
|
|
8015f92: 605a str r2, [r3, #4]
|
|
8015f94: 69bb ldr r3, [r7, #24]
|
|
8015f96: 2200 movs r2, #0
|
|
8015f98: 629a str r2, [r3, #40] @ 0x28
|
|
8015f9a: 68fb ldr r3, [r7, #12]
|
|
8015f9c: 681b ldr r3, [r3, #0]
|
|
8015f9e: 1e5a subs r2, r3, #1
|
|
8015fa0: 68fb ldr r3, [r7, #12]
|
|
8015fa2: 601a str r2, [r3, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Place the unblocked task into the appropriate ready
|
|
* list. */
|
|
prvAddTaskToReadyList( pxTCB );
|
|
8015fa4: 69bb ldr r3, [r7, #24]
|
|
8015fa6: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015fa8: 4b39 ldr r3, [pc, #228] @ (8016090 <xTaskIncrementTick+0x21c>)
|
|
8015faa: 681b ldr r3, [r3, #0]
|
|
8015fac: 429a cmp r2, r3
|
|
8015fae: d903 bls.n 8015fb8 <xTaskIncrementTick+0x144>
|
|
8015fb0: 69bb ldr r3, [r7, #24]
|
|
8015fb2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8015fb4: 4a36 ldr r2, [pc, #216] @ (8016090 <xTaskIncrementTick+0x21c>)
|
|
8015fb6: 6013 str r3, [r2, #0]
|
|
8015fb8: 69bb ldr r3, [r7, #24]
|
|
8015fba: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015fbc: 4935 ldr r1, [pc, #212] @ (8016094 <xTaskIncrementTick+0x220>)
|
|
8015fbe: 4613 mov r3, r2
|
|
8015fc0: 009b lsls r3, r3, #2
|
|
8015fc2: 4413 add r3, r2
|
|
8015fc4: 009b lsls r3, r3, #2
|
|
8015fc6: 440b add r3, r1
|
|
8015fc8: 3304 adds r3, #4
|
|
8015fca: 681b ldr r3, [r3, #0]
|
|
8015fcc: 60bb str r3, [r7, #8]
|
|
8015fce: 69bb ldr r3, [r7, #24]
|
|
8015fd0: 68ba ldr r2, [r7, #8]
|
|
8015fd2: 609a str r2, [r3, #8]
|
|
8015fd4: 68bb ldr r3, [r7, #8]
|
|
8015fd6: 689a ldr r2, [r3, #8]
|
|
8015fd8: 69bb ldr r3, [r7, #24]
|
|
8015fda: 60da str r2, [r3, #12]
|
|
8015fdc: 68bb ldr r3, [r7, #8]
|
|
8015fde: 689b ldr r3, [r3, #8]
|
|
8015fe0: 69ba ldr r2, [r7, #24]
|
|
8015fe2: 3204 adds r2, #4
|
|
8015fe4: 605a str r2, [r3, #4]
|
|
8015fe6: 69bb ldr r3, [r7, #24]
|
|
8015fe8: 1d1a adds r2, r3, #4
|
|
8015fea: 68bb ldr r3, [r7, #8]
|
|
8015fec: 609a str r2, [r3, #8]
|
|
8015fee: 69bb ldr r3, [r7, #24]
|
|
8015ff0: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8015ff2: 4613 mov r3, r2
|
|
8015ff4: 009b lsls r3, r3, #2
|
|
8015ff6: 4413 add r3, r2
|
|
8015ff8: 009b lsls r3, r3, #2
|
|
8015ffa: 4a26 ldr r2, [pc, #152] @ (8016094 <xTaskIncrementTick+0x220>)
|
|
8015ffc: 441a add r2, r3
|
|
8015ffe: 69bb ldr r3, [r7, #24]
|
|
8016000: 615a str r2, [r3, #20]
|
|
8016002: 69bb ldr r3, [r7, #24]
|
|
8016004: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016006: 4923 ldr r1, [pc, #140] @ (8016094 <xTaskIncrementTick+0x220>)
|
|
8016008: 4613 mov r3, r2
|
|
801600a: 009b lsls r3, r3, #2
|
|
801600c: 4413 add r3, r2
|
|
801600e: 009b lsls r3, r3, #2
|
|
8016010: 440b add r3, r1
|
|
8016012: 681b ldr r3, [r3, #0]
|
|
8016014: 1c59 adds r1, r3, #1
|
|
8016016: 481f ldr r0, [pc, #124] @ (8016094 <xTaskIncrementTick+0x220>)
|
|
8016018: 4613 mov r3, r2
|
|
801601a: 009b lsls r3, r3, #2
|
|
801601c: 4413 add r3, r2
|
|
801601e: 009b lsls r3, r3, #2
|
|
8016020: 4403 add r3, r0
|
|
8016022: 6019 str r1, [r3, #0]
|
|
* task.
|
|
* The case of equal priority tasks sharing
|
|
* processing time (which happens when both
|
|
* preemption and time slicing are on) is
|
|
* handled below.*/
|
|
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
8016024: 69bb ldr r3, [r7, #24]
|
|
8016026: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016028: 4b1b ldr r3, [pc, #108] @ (8016098 <xTaskIncrementTick+0x224>)
|
|
801602a: 681b ldr r3, [r3, #0]
|
|
801602c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
801602e: 429a cmp r2, r3
|
|
8016030: f67f af5c bls.w 8015eec <xTaskIncrementTick+0x78>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
8016034: 2301 movs r3, #1
|
|
8016036: 627b str r3, [r7, #36] @ 0x24
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
8016038: e758 b.n 8015eec <xTaskIncrementTick+0x78>
|
|
/* Tasks of equal priority to the currently running task will share
|
|
* processing time (time slice) if preemption is on, and the application
|
|
* writer has not explicitly turned time slicing off. */
|
|
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
|
|
{
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
|
|
801603a: 4b17 ldr r3, [pc, #92] @ (8016098 <xTaskIncrementTick+0x224>)
|
|
801603c: 681b ldr r3, [r3, #0]
|
|
801603e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016040: 4914 ldr r1, [pc, #80] @ (8016094 <xTaskIncrementTick+0x220>)
|
|
8016042: 4613 mov r3, r2
|
|
8016044: 009b lsls r3, r3, #2
|
|
8016046: 4413 add r3, r2
|
|
8016048: 009b lsls r3, r3, #2
|
|
801604a: 440b add r3, r1
|
|
801604c: 681b ldr r3, [r3, #0]
|
|
801604e: 2b01 cmp r3, #1
|
|
8016050: d901 bls.n 8016056 <xTaskIncrementTick+0x1e2>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
8016052: 2301 movs r3, #1
|
|
8016054: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
#endif /* configUSE_TICK_HOOK */
|
|
|
|
#if ( configUSE_PREEMPTION == 1 )
|
|
{
|
|
if( xYieldPending != pdFALSE )
|
|
8016056: 4b11 ldr r3, [pc, #68] @ (801609c <xTaskIncrementTick+0x228>)
|
|
8016058: 681b ldr r3, [r3, #0]
|
|
801605a: 2b00 cmp r3, #0
|
|
801605c: d007 beq.n 801606e <xTaskIncrementTick+0x1fa>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
801605e: 2301 movs r3, #1
|
|
8016060: 627b str r3, [r7, #36] @ 0x24
|
|
8016062: e004 b.n 801606e <xTaskIncrementTick+0x1fa>
|
|
}
|
|
#endif /* configUSE_PREEMPTION */
|
|
}
|
|
else
|
|
{
|
|
++xPendedTicks;
|
|
8016064: 4b0e ldr r3, [pc, #56] @ (80160a0 <xTaskIncrementTick+0x22c>)
|
|
8016066: 681b ldr r3, [r3, #0]
|
|
8016068: 3301 adds r3, #1
|
|
801606a: 4a0d ldr r2, [pc, #52] @ (80160a0 <xTaskIncrementTick+0x22c>)
|
|
801606c: 6013 str r3, [r2, #0]
|
|
vApplicationTickHook();
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return xSwitchRequired;
|
|
801606e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
8016070: 4618 mov r0, r3
|
|
8016072: 3728 adds r7, #40 @ 0x28
|
|
8016074: 46bd mov sp, r7
|
|
8016076: bd80 pop {r7, pc}
|
|
8016078: 20002664 .word 0x20002664
|
|
801607c: 20002640 .word 0x20002640
|
|
8016080: 200025f4 .word 0x200025f4
|
|
8016084: 200025f8 .word 0x200025f8
|
|
8016088: 20002654 .word 0x20002654
|
|
801608c: 2000265c .word 0x2000265c
|
|
8016090: 20002644 .word 0x20002644
|
|
8016094: 2000216c .word 0x2000216c
|
|
8016098: 20002168 .word 0x20002168
|
|
801609c: 20002650 .word 0x20002650
|
|
80160a0: 2000264c .word 0x2000264c
|
|
|
|
080160a4 <vTaskSwitchContext>:
|
|
|
|
#endif /* configUSE_APPLICATION_TASK_TAG */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskSwitchContext( void )
|
|
{
|
|
80160a4: b580 push {r7, lr}
|
|
80160a6: b086 sub sp, #24
|
|
80160a8: af00 add r7, sp, #0
|
|
if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
|
|
80160aa: 4b3d ldr r3, [pc, #244] @ (80161a0 <vTaskSwitchContext+0xfc>)
|
|
80160ac: 681b ldr r3, [r3, #0]
|
|
80160ae: 2b00 cmp r3, #0
|
|
80160b0: d003 beq.n 80160ba <vTaskSwitchContext+0x16>
|
|
{
|
|
/* The scheduler is currently suspended - do not allow a context
|
|
* switch. */
|
|
xYieldPending = pdTRUE;
|
|
80160b2: 4b3c ldr r3, [pc, #240] @ (80161a4 <vTaskSwitchContext+0x100>)
|
|
80160b4: 2201 movs r2, #1
|
|
80160b6: 601a str r2, [r3, #0]
|
|
* Block specific to this task. */
|
|
configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
80160b8: e06d b.n 8016196 <vTaskSwitchContext+0xf2>
|
|
xYieldPending = pdFALSE;
|
|
80160ba: 4b3a ldr r3, [pc, #232] @ (80161a4 <vTaskSwitchContext+0x100>)
|
|
80160bc: 2200 movs r2, #0
|
|
80160be: 601a str r2, [r3, #0]
|
|
taskCHECK_FOR_STACK_OVERFLOW();
|
|
80160c0: 4b39 ldr r3, [pc, #228] @ (80161a8 <vTaskSwitchContext+0x104>)
|
|
80160c2: 681b ldr r3, [r3, #0]
|
|
80160c4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80160c6: 613b str r3, [r7, #16]
|
|
80160c8: f04f 33a5 mov.w r3, #2779096485 @ 0xa5a5a5a5
|
|
80160cc: 60fb str r3, [r7, #12]
|
|
80160ce: 693b ldr r3, [r7, #16]
|
|
80160d0: 681b ldr r3, [r3, #0]
|
|
80160d2: 68fa ldr r2, [r7, #12]
|
|
80160d4: 429a cmp r2, r3
|
|
80160d6: d111 bne.n 80160fc <vTaskSwitchContext+0x58>
|
|
80160d8: 693b ldr r3, [r7, #16]
|
|
80160da: 3304 adds r3, #4
|
|
80160dc: 681b ldr r3, [r3, #0]
|
|
80160de: 68fa ldr r2, [r7, #12]
|
|
80160e0: 429a cmp r2, r3
|
|
80160e2: d10b bne.n 80160fc <vTaskSwitchContext+0x58>
|
|
80160e4: 693b ldr r3, [r7, #16]
|
|
80160e6: 3308 adds r3, #8
|
|
80160e8: 681b ldr r3, [r3, #0]
|
|
80160ea: 68fa ldr r2, [r7, #12]
|
|
80160ec: 429a cmp r2, r3
|
|
80160ee: d105 bne.n 80160fc <vTaskSwitchContext+0x58>
|
|
80160f0: 693b ldr r3, [r7, #16]
|
|
80160f2: 330c adds r3, #12
|
|
80160f4: 681b ldr r3, [r3, #0]
|
|
80160f6: 68fa ldr r2, [r7, #12]
|
|
80160f8: 429a cmp r2, r3
|
|
80160fa: d008 beq.n 801610e <vTaskSwitchContext+0x6a>
|
|
80160fc: 4b2a ldr r3, [pc, #168] @ (80161a8 <vTaskSwitchContext+0x104>)
|
|
80160fe: 681a ldr r2, [r3, #0]
|
|
8016100: 4b29 ldr r3, [pc, #164] @ (80161a8 <vTaskSwitchContext+0x104>)
|
|
8016102: 681b ldr r3, [r3, #0]
|
|
8016104: 3334 adds r3, #52 @ 0x34
|
|
8016106: 4619 mov r1, r3
|
|
8016108: 4610 mov r0, r2
|
|
801610a: f7ec fadd bl 80026c8 <vApplicationStackOverflowHook>
|
|
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
801610e: 4b27 ldr r3, [pc, #156] @ (80161ac <vTaskSwitchContext+0x108>)
|
|
8016110: 681b ldr r3, [r3, #0]
|
|
8016112: 617b str r3, [r7, #20]
|
|
8016114: e011 b.n 801613a <vTaskSwitchContext+0x96>
|
|
8016116: 697b ldr r3, [r7, #20]
|
|
8016118: 2b00 cmp r3, #0
|
|
801611a: d10b bne.n 8016134 <vTaskSwitchContext+0x90>
|
|
__asm volatile
|
|
801611c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016120: f383 8811 msr BASEPRI, r3
|
|
8016124: f3bf 8f6f isb sy
|
|
8016128: f3bf 8f4f dsb sy
|
|
801612c: 607b str r3, [r7, #4]
|
|
}
|
|
801612e: bf00 nop
|
|
8016130: bf00 nop
|
|
8016132: e7fd b.n 8016130 <vTaskSwitchContext+0x8c>
|
|
8016134: 697b ldr r3, [r7, #20]
|
|
8016136: 3b01 subs r3, #1
|
|
8016138: 617b str r3, [r7, #20]
|
|
801613a: 491d ldr r1, [pc, #116] @ (80161b0 <vTaskSwitchContext+0x10c>)
|
|
801613c: 697a ldr r2, [r7, #20]
|
|
801613e: 4613 mov r3, r2
|
|
8016140: 009b lsls r3, r3, #2
|
|
8016142: 4413 add r3, r2
|
|
8016144: 009b lsls r3, r3, #2
|
|
8016146: 440b add r3, r1
|
|
8016148: 681b ldr r3, [r3, #0]
|
|
801614a: 2b00 cmp r3, #0
|
|
801614c: d0e3 beq.n 8016116 <vTaskSwitchContext+0x72>
|
|
801614e: 697a ldr r2, [r7, #20]
|
|
8016150: 4613 mov r3, r2
|
|
8016152: 009b lsls r3, r3, #2
|
|
8016154: 4413 add r3, r2
|
|
8016156: 009b lsls r3, r3, #2
|
|
8016158: 4a15 ldr r2, [pc, #84] @ (80161b0 <vTaskSwitchContext+0x10c>)
|
|
801615a: 4413 add r3, r2
|
|
801615c: 60bb str r3, [r7, #8]
|
|
801615e: 68bb ldr r3, [r7, #8]
|
|
8016160: 685b ldr r3, [r3, #4]
|
|
8016162: 685a ldr r2, [r3, #4]
|
|
8016164: 68bb ldr r3, [r7, #8]
|
|
8016166: 605a str r2, [r3, #4]
|
|
8016168: 68bb ldr r3, [r7, #8]
|
|
801616a: 685a ldr r2, [r3, #4]
|
|
801616c: 68bb ldr r3, [r7, #8]
|
|
801616e: 3308 adds r3, #8
|
|
8016170: 429a cmp r2, r3
|
|
8016172: d103 bne.n 801617c <vTaskSwitchContext+0xd8>
|
|
8016174: 68bb ldr r3, [r7, #8]
|
|
8016176: 68da ldr r2, [r3, #12]
|
|
8016178: 68bb ldr r3, [r7, #8]
|
|
801617a: 605a str r2, [r3, #4]
|
|
801617c: 68bb ldr r3, [r7, #8]
|
|
801617e: 685b ldr r3, [r3, #4]
|
|
8016180: 68db ldr r3, [r3, #12]
|
|
8016182: 4a09 ldr r2, [pc, #36] @ (80161a8 <vTaskSwitchContext+0x104>)
|
|
8016184: 6013 str r3, [r2, #0]
|
|
8016186: 4a09 ldr r2, [pc, #36] @ (80161ac <vTaskSwitchContext+0x108>)
|
|
8016188: 697b ldr r3, [r7, #20]
|
|
801618a: 6013 str r3, [r2, #0]
|
|
configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
|
|
801618c: 4b06 ldr r3, [pc, #24] @ (80161a8 <vTaskSwitchContext+0x104>)
|
|
801618e: 681b ldr r3, [r3, #0]
|
|
8016190: 3354 adds r3, #84 @ 0x54
|
|
8016192: 4a08 ldr r2, [pc, #32] @ (80161b4 <vTaskSwitchContext+0x110>)
|
|
8016194: 6013 str r3, [r2, #0]
|
|
}
|
|
8016196: bf00 nop
|
|
8016198: 3718 adds r7, #24
|
|
801619a: 46bd mov sp, r7
|
|
801619c: bd80 pop {r7, pc}
|
|
801619e: bf00 nop
|
|
80161a0: 20002664 .word 0x20002664
|
|
80161a4: 20002650 .word 0x20002650
|
|
80161a8: 20002168 .word 0x20002168
|
|
80161ac: 20002644 .word 0x20002644
|
|
80161b0: 2000216c .word 0x2000216c
|
|
80161b4: 2000011c .word 0x2000011c
|
|
|
|
080161b8 <vTaskPlaceOnEventList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskPlaceOnEventList( List_t * const pxEventList,
|
|
const TickType_t xTicksToWait )
|
|
{
|
|
80161b8: b580 push {r7, lr}
|
|
80161ba: b084 sub sp, #16
|
|
80161bc: af00 add r7, sp, #0
|
|
80161be: 6078 str r0, [r7, #4]
|
|
80161c0: 6039 str r1, [r7, #0]
|
|
configASSERT( pxEventList );
|
|
80161c2: 687b ldr r3, [r7, #4]
|
|
80161c4: 2b00 cmp r3, #0
|
|
80161c6: d10b bne.n 80161e0 <vTaskPlaceOnEventList+0x28>
|
|
__asm volatile
|
|
80161c8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80161cc: f383 8811 msr BASEPRI, r3
|
|
80161d0: f3bf 8f6f isb sy
|
|
80161d4: f3bf 8f4f dsb sy
|
|
80161d8: 60fb str r3, [r7, #12]
|
|
}
|
|
80161da: bf00 nop
|
|
80161dc: bf00 nop
|
|
80161de: e7fd b.n 80161dc <vTaskPlaceOnEventList+0x24>
|
|
* xItemValue = ( configMAX_PRIORITIES - uxPriority )
|
|
* Therefore, the event list is sorted in descending priority order.
|
|
*
|
|
* The queue that contains the event list is locked, preventing
|
|
* simultaneous access from interrupts. */
|
|
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
|
80161e0: 4b07 ldr r3, [pc, #28] @ (8016200 <vTaskPlaceOnEventList+0x48>)
|
|
80161e2: 681b ldr r3, [r3, #0]
|
|
80161e4: 3318 adds r3, #24
|
|
80161e6: 4619 mov r1, r3
|
|
80161e8: 6878 ldr r0, [r7, #4]
|
|
80161ea: f7fe f8ec bl 80143c6 <vListInsert>
|
|
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
|
80161ee: 2101 movs r1, #1
|
|
80161f0: 6838 ldr r0, [r7, #0]
|
|
80161f2: f001 f919 bl 8017428 <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
80161f6: bf00 nop
|
|
80161f8: 3710 adds r7, #16
|
|
80161fa: 46bd mov sp, r7
|
|
80161fc: bd80 pop {r7, pc}
|
|
80161fe: bf00 nop
|
|
8016200: 20002168 .word 0x20002168
|
|
|
|
08016204 <vTaskPlaceOnEventListRestricted>:
|
|
#if ( configUSE_TIMERS == 1 )
|
|
|
|
void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
|
|
TickType_t xTicksToWait,
|
|
const BaseType_t xWaitIndefinitely )
|
|
{
|
|
8016204: b580 push {r7, lr}
|
|
8016206: b086 sub sp, #24
|
|
8016208: af00 add r7, sp, #0
|
|
801620a: 60f8 str r0, [r7, #12]
|
|
801620c: 60b9 str r1, [r7, #8]
|
|
801620e: 607a str r2, [r7, #4]
|
|
configASSERT( pxEventList );
|
|
8016210: 68fb ldr r3, [r7, #12]
|
|
8016212: 2b00 cmp r3, #0
|
|
8016214: d10b bne.n 801622e <vTaskPlaceOnEventListRestricted+0x2a>
|
|
__asm volatile
|
|
8016216: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801621a: f383 8811 msr BASEPRI, r3
|
|
801621e: f3bf 8f6f isb sy
|
|
8016222: f3bf 8f4f dsb sy
|
|
8016226: 613b str r3, [r7, #16]
|
|
}
|
|
8016228: bf00 nop
|
|
801622a: bf00 nop
|
|
801622c: e7fd b.n 801622a <vTaskPlaceOnEventListRestricted+0x26>
|
|
|
|
/* Place the event list item of the TCB in the appropriate event list.
|
|
* In this case it is assume that this is the only task that is going to
|
|
* be waiting on this event list, so the faster vListInsertEnd() function
|
|
* can be used in place of vListInsert. */
|
|
listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
|
801622e: 68fb ldr r3, [r7, #12]
|
|
8016230: 685b ldr r3, [r3, #4]
|
|
8016232: 617b str r3, [r7, #20]
|
|
8016234: 4b15 ldr r3, [pc, #84] @ (801628c <vTaskPlaceOnEventListRestricted+0x88>)
|
|
8016236: 681b ldr r3, [r3, #0]
|
|
8016238: 697a ldr r2, [r7, #20]
|
|
801623a: 61da str r2, [r3, #28]
|
|
801623c: 4b13 ldr r3, [pc, #76] @ (801628c <vTaskPlaceOnEventListRestricted+0x88>)
|
|
801623e: 681b ldr r3, [r3, #0]
|
|
8016240: 697a ldr r2, [r7, #20]
|
|
8016242: 6892 ldr r2, [r2, #8]
|
|
8016244: 621a str r2, [r3, #32]
|
|
8016246: 4b11 ldr r3, [pc, #68] @ (801628c <vTaskPlaceOnEventListRestricted+0x88>)
|
|
8016248: 681a ldr r2, [r3, #0]
|
|
801624a: 697b ldr r3, [r7, #20]
|
|
801624c: 689b ldr r3, [r3, #8]
|
|
801624e: 3218 adds r2, #24
|
|
8016250: 605a str r2, [r3, #4]
|
|
8016252: 4b0e ldr r3, [pc, #56] @ (801628c <vTaskPlaceOnEventListRestricted+0x88>)
|
|
8016254: 681b ldr r3, [r3, #0]
|
|
8016256: f103 0218 add.w r2, r3, #24
|
|
801625a: 697b ldr r3, [r7, #20]
|
|
801625c: 609a str r2, [r3, #8]
|
|
801625e: 4b0b ldr r3, [pc, #44] @ (801628c <vTaskPlaceOnEventListRestricted+0x88>)
|
|
8016260: 681b ldr r3, [r3, #0]
|
|
8016262: 68fa ldr r2, [r7, #12]
|
|
8016264: 629a str r2, [r3, #40] @ 0x28
|
|
8016266: 68fb ldr r3, [r7, #12]
|
|
8016268: 681b ldr r3, [r3, #0]
|
|
801626a: 1c5a adds r2, r3, #1
|
|
801626c: 68fb ldr r3, [r7, #12]
|
|
801626e: 601a str r2, [r3, #0]
|
|
|
|
/* If the task should block indefinitely then set the block time to a
|
|
* value that will be recognised as an indefinite delay inside the
|
|
* prvAddCurrentTaskToDelayedList() function. */
|
|
if( xWaitIndefinitely != pdFALSE )
|
|
8016270: 687b ldr r3, [r7, #4]
|
|
8016272: 2b00 cmp r3, #0
|
|
8016274: d002 beq.n 801627c <vTaskPlaceOnEventListRestricted+0x78>
|
|
{
|
|
xTicksToWait = portMAX_DELAY;
|
|
8016276: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
801627a: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
|
|
801627c: 6879 ldr r1, [r7, #4]
|
|
801627e: 68b8 ldr r0, [r7, #8]
|
|
8016280: f001 f8d2 bl 8017428 <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
8016284: bf00 nop
|
|
8016286: 3718 adds r7, #24
|
|
8016288: 46bd mov sp, r7
|
|
801628a: bd80 pop {r7, pc}
|
|
801628c: 20002168 .word 0x20002168
|
|
|
|
08016290 <xTaskRemoveFromEventList>:
|
|
|
|
#endif /* configUSE_TIMERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
|
|
{
|
|
8016290: b480 push {r7}
|
|
8016292: b08b sub sp, #44 @ 0x2c
|
|
8016294: af00 add r7, sp, #0
|
|
8016296: 6078 str r0, [r7, #4]
|
|
* get called - the lock count on the queue will get modified instead. This
|
|
* means exclusive access to the event list is guaranteed here.
|
|
*
|
|
* This function assumes that a check has already been made to ensure that
|
|
* pxEventList is not empty. */
|
|
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
8016298: 687b ldr r3, [r7, #4]
|
|
801629a: 68db ldr r3, [r3, #12]
|
|
801629c: 68db ldr r3, [r3, #12]
|
|
801629e: 623b str r3, [r7, #32]
|
|
configASSERT( pxUnblockedTCB );
|
|
80162a0: 6a3b ldr r3, [r7, #32]
|
|
80162a2: 2b00 cmp r3, #0
|
|
80162a4: d10b bne.n 80162be <xTaskRemoveFromEventList+0x2e>
|
|
__asm volatile
|
|
80162a6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80162aa: f383 8811 msr BASEPRI, r3
|
|
80162ae: f3bf 8f6f isb sy
|
|
80162b2: f3bf 8f4f dsb sy
|
|
80162b6: 60fb str r3, [r7, #12]
|
|
}
|
|
80162b8: bf00 nop
|
|
80162ba: bf00 nop
|
|
80162bc: e7fd b.n 80162ba <xTaskRemoveFromEventList+0x2a>
|
|
listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) );
|
|
80162be: 6a3b ldr r3, [r7, #32]
|
|
80162c0: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80162c2: 61fb str r3, [r7, #28]
|
|
80162c4: 6a3b ldr r3, [r7, #32]
|
|
80162c6: 69db ldr r3, [r3, #28]
|
|
80162c8: 6a3a ldr r2, [r7, #32]
|
|
80162ca: 6a12 ldr r2, [r2, #32]
|
|
80162cc: 609a str r2, [r3, #8]
|
|
80162ce: 6a3b ldr r3, [r7, #32]
|
|
80162d0: 6a1b ldr r3, [r3, #32]
|
|
80162d2: 6a3a ldr r2, [r7, #32]
|
|
80162d4: 69d2 ldr r2, [r2, #28]
|
|
80162d6: 605a str r2, [r3, #4]
|
|
80162d8: 69fb ldr r3, [r7, #28]
|
|
80162da: 685a ldr r2, [r3, #4]
|
|
80162dc: 6a3b ldr r3, [r7, #32]
|
|
80162de: 3318 adds r3, #24
|
|
80162e0: 429a cmp r2, r3
|
|
80162e2: d103 bne.n 80162ec <xTaskRemoveFromEventList+0x5c>
|
|
80162e4: 6a3b ldr r3, [r7, #32]
|
|
80162e6: 6a1a ldr r2, [r3, #32]
|
|
80162e8: 69fb ldr r3, [r7, #28]
|
|
80162ea: 605a str r2, [r3, #4]
|
|
80162ec: 6a3b ldr r3, [r7, #32]
|
|
80162ee: 2200 movs r2, #0
|
|
80162f0: 629a str r2, [r3, #40] @ 0x28
|
|
80162f2: 69fb ldr r3, [r7, #28]
|
|
80162f4: 681b ldr r3, [r3, #0]
|
|
80162f6: 1e5a subs r2, r3, #1
|
|
80162f8: 69fb ldr r3, [r7, #28]
|
|
80162fa: 601a str r2, [r3, #0]
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
|
|
80162fc: 4b4a ldr r3, [pc, #296] @ (8016428 <xTaskRemoveFromEventList+0x198>)
|
|
80162fe: 681b ldr r3, [r3, #0]
|
|
8016300: 2b00 cmp r3, #0
|
|
8016302: d15f bne.n 80163c4 <xTaskRemoveFromEventList+0x134>
|
|
{
|
|
listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );
|
|
8016304: 6a3b ldr r3, [r7, #32]
|
|
8016306: 695b ldr r3, [r3, #20]
|
|
8016308: 617b str r3, [r7, #20]
|
|
801630a: 6a3b ldr r3, [r7, #32]
|
|
801630c: 689b ldr r3, [r3, #8]
|
|
801630e: 6a3a ldr r2, [r7, #32]
|
|
8016310: 68d2 ldr r2, [r2, #12]
|
|
8016312: 609a str r2, [r3, #8]
|
|
8016314: 6a3b ldr r3, [r7, #32]
|
|
8016316: 68db ldr r3, [r3, #12]
|
|
8016318: 6a3a ldr r2, [r7, #32]
|
|
801631a: 6892 ldr r2, [r2, #8]
|
|
801631c: 605a str r2, [r3, #4]
|
|
801631e: 697b ldr r3, [r7, #20]
|
|
8016320: 685a ldr r2, [r3, #4]
|
|
8016322: 6a3b ldr r3, [r7, #32]
|
|
8016324: 3304 adds r3, #4
|
|
8016326: 429a cmp r2, r3
|
|
8016328: d103 bne.n 8016332 <xTaskRemoveFromEventList+0xa2>
|
|
801632a: 6a3b ldr r3, [r7, #32]
|
|
801632c: 68da ldr r2, [r3, #12]
|
|
801632e: 697b ldr r3, [r7, #20]
|
|
8016330: 605a str r2, [r3, #4]
|
|
8016332: 6a3b ldr r3, [r7, #32]
|
|
8016334: 2200 movs r2, #0
|
|
8016336: 615a str r2, [r3, #20]
|
|
8016338: 697b ldr r3, [r7, #20]
|
|
801633a: 681b ldr r3, [r3, #0]
|
|
801633c: 1e5a subs r2, r3, #1
|
|
801633e: 697b ldr r3, [r7, #20]
|
|
8016340: 601a str r2, [r3, #0]
|
|
prvAddTaskToReadyList( pxUnblockedTCB );
|
|
8016342: 6a3b ldr r3, [r7, #32]
|
|
8016344: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016346: 4b39 ldr r3, [pc, #228] @ (801642c <xTaskRemoveFromEventList+0x19c>)
|
|
8016348: 681b ldr r3, [r3, #0]
|
|
801634a: 429a cmp r2, r3
|
|
801634c: d903 bls.n 8016356 <xTaskRemoveFromEventList+0xc6>
|
|
801634e: 6a3b ldr r3, [r7, #32]
|
|
8016350: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016352: 4a36 ldr r2, [pc, #216] @ (801642c <xTaskRemoveFromEventList+0x19c>)
|
|
8016354: 6013 str r3, [r2, #0]
|
|
8016356: 6a3b ldr r3, [r7, #32]
|
|
8016358: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
801635a: 4935 ldr r1, [pc, #212] @ (8016430 <xTaskRemoveFromEventList+0x1a0>)
|
|
801635c: 4613 mov r3, r2
|
|
801635e: 009b lsls r3, r3, #2
|
|
8016360: 4413 add r3, r2
|
|
8016362: 009b lsls r3, r3, #2
|
|
8016364: 440b add r3, r1
|
|
8016366: 3304 adds r3, #4
|
|
8016368: 681b ldr r3, [r3, #0]
|
|
801636a: 613b str r3, [r7, #16]
|
|
801636c: 6a3b ldr r3, [r7, #32]
|
|
801636e: 693a ldr r2, [r7, #16]
|
|
8016370: 609a str r2, [r3, #8]
|
|
8016372: 693b ldr r3, [r7, #16]
|
|
8016374: 689a ldr r2, [r3, #8]
|
|
8016376: 6a3b ldr r3, [r7, #32]
|
|
8016378: 60da str r2, [r3, #12]
|
|
801637a: 693b ldr r3, [r7, #16]
|
|
801637c: 689b ldr r3, [r3, #8]
|
|
801637e: 6a3a ldr r2, [r7, #32]
|
|
8016380: 3204 adds r2, #4
|
|
8016382: 605a str r2, [r3, #4]
|
|
8016384: 6a3b ldr r3, [r7, #32]
|
|
8016386: 1d1a adds r2, r3, #4
|
|
8016388: 693b ldr r3, [r7, #16]
|
|
801638a: 609a str r2, [r3, #8]
|
|
801638c: 6a3b ldr r3, [r7, #32]
|
|
801638e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016390: 4613 mov r3, r2
|
|
8016392: 009b lsls r3, r3, #2
|
|
8016394: 4413 add r3, r2
|
|
8016396: 009b lsls r3, r3, #2
|
|
8016398: 4a25 ldr r2, [pc, #148] @ (8016430 <xTaskRemoveFromEventList+0x1a0>)
|
|
801639a: 441a add r2, r3
|
|
801639c: 6a3b ldr r3, [r7, #32]
|
|
801639e: 615a str r2, [r3, #20]
|
|
80163a0: 6a3b ldr r3, [r7, #32]
|
|
80163a2: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80163a4: 4922 ldr r1, [pc, #136] @ (8016430 <xTaskRemoveFromEventList+0x1a0>)
|
|
80163a6: 4613 mov r3, r2
|
|
80163a8: 009b lsls r3, r3, #2
|
|
80163aa: 4413 add r3, r2
|
|
80163ac: 009b lsls r3, r3, #2
|
|
80163ae: 440b add r3, r1
|
|
80163b0: 681b ldr r3, [r3, #0]
|
|
80163b2: 1c59 adds r1, r3, #1
|
|
80163b4: 481e ldr r0, [pc, #120] @ (8016430 <xTaskRemoveFromEventList+0x1a0>)
|
|
80163b6: 4613 mov r3, r2
|
|
80163b8: 009b lsls r3, r3, #2
|
|
80163ba: 4413 add r3, r2
|
|
80163bc: 009b lsls r3, r3, #2
|
|
80163be: 4403 add r3, r0
|
|
80163c0: 6019 str r1, [r3, #0]
|
|
80163c2: e01b b.n 80163fc <xTaskRemoveFromEventList+0x16c>
|
|
}
|
|
else
|
|
{
|
|
/* The delayed and ready lists cannot be accessed, so hold this task
|
|
* pending until the scheduler is resumed. */
|
|
listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
|
|
80163c4: 4b1b ldr r3, [pc, #108] @ (8016434 <xTaskRemoveFromEventList+0x1a4>)
|
|
80163c6: 685b ldr r3, [r3, #4]
|
|
80163c8: 61bb str r3, [r7, #24]
|
|
80163ca: 6a3b ldr r3, [r7, #32]
|
|
80163cc: 69ba ldr r2, [r7, #24]
|
|
80163ce: 61da str r2, [r3, #28]
|
|
80163d0: 69bb ldr r3, [r7, #24]
|
|
80163d2: 689a ldr r2, [r3, #8]
|
|
80163d4: 6a3b ldr r3, [r7, #32]
|
|
80163d6: 621a str r2, [r3, #32]
|
|
80163d8: 69bb ldr r3, [r7, #24]
|
|
80163da: 689b ldr r3, [r3, #8]
|
|
80163dc: 6a3a ldr r2, [r7, #32]
|
|
80163de: 3218 adds r2, #24
|
|
80163e0: 605a str r2, [r3, #4]
|
|
80163e2: 6a3b ldr r3, [r7, #32]
|
|
80163e4: f103 0218 add.w r2, r3, #24
|
|
80163e8: 69bb ldr r3, [r7, #24]
|
|
80163ea: 609a str r2, [r3, #8]
|
|
80163ec: 6a3b ldr r3, [r7, #32]
|
|
80163ee: 4a11 ldr r2, [pc, #68] @ (8016434 <xTaskRemoveFromEventList+0x1a4>)
|
|
80163f0: 629a str r2, [r3, #40] @ 0x28
|
|
80163f2: 4b10 ldr r3, [pc, #64] @ (8016434 <xTaskRemoveFromEventList+0x1a4>)
|
|
80163f4: 681b ldr r3, [r3, #0]
|
|
80163f6: 3301 adds r3, #1
|
|
80163f8: 4a0e ldr r2, [pc, #56] @ (8016434 <xTaskRemoveFromEventList+0x1a4>)
|
|
80163fa: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
80163fc: 6a3b ldr r3, [r7, #32]
|
|
80163fe: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016400: 4b0d ldr r3, [pc, #52] @ (8016438 <xTaskRemoveFromEventList+0x1a8>)
|
|
8016402: 681b ldr r3, [r3, #0]
|
|
8016404: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016406: 429a cmp r2, r3
|
|
8016408: d905 bls.n 8016416 <xTaskRemoveFromEventList+0x186>
|
|
{
|
|
/* Return true if the task removed from the event list has a higher
|
|
* priority than the calling task. This allows the calling task to know if
|
|
* it should force a context switch now. */
|
|
xReturn = pdTRUE;
|
|
801640a: 2301 movs r3, #1
|
|
801640c: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Mark that a yield is pending in case the user is not using the
|
|
* "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
|
|
xYieldPending = pdTRUE;
|
|
801640e: 4b0b ldr r3, [pc, #44] @ (801643c <xTaskRemoveFromEventList+0x1ac>)
|
|
8016410: 2201 movs r2, #1
|
|
8016412: 601a str r2, [r3, #0]
|
|
8016414: e001 b.n 801641a <xTaskRemoveFromEventList+0x18a>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
8016416: 2300 movs r3, #0
|
|
8016418: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
|
|
return xReturn;
|
|
801641a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
801641c: 4618 mov r0, r3
|
|
801641e: 372c adds r7, #44 @ 0x2c
|
|
8016420: 46bd mov sp, r7
|
|
8016422: f85d 7b04 ldr.w r7, [sp], #4
|
|
8016426: 4770 bx lr
|
|
8016428: 20002664 .word 0x20002664
|
|
801642c: 20002644 .word 0x20002644
|
|
8016430: 2000216c .word 0x2000216c
|
|
8016434: 200025fc .word 0x200025fc
|
|
8016438: 20002168 .word 0x20002168
|
|
801643c: 20002650 .word 0x20002650
|
|
|
|
08016440 <vTaskInternalSetTimeOutState>:
|
|
taskEXIT_CRITICAL();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
|
|
{
|
|
8016440: b480 push {r7}
|
|
8016442: b083 sub sp, #12
|
|
8016444: af00 add r7, sp, #0
|
|
8016446: 6078 str r0, [r7, #4]
|
|
/* For internal use only as it does not use a critical section. */
|
|
pxTimeOut->xOverflowCount = xNumOfOverflows;
|
|
8016448: 4b06 ldr r3, [pc, #24] @ (8016464 <vTaskInternalSetTimeOutState+0x24>)
|
|
801644a: 681a ldr r2, [r3, #0]
|
|
801644c: 687b ldr r3, [r7, #4]
|
|
801644e: 601a str r2, [r3, #0]
|
|
pxTimeOut->xTimeOnEntering = xTickCount;
|
|
8016450: 4b05 ldr r3, [pc, #20] @ (8016468 <vTaskInternalSetTimeOutState+0x28>)
|
|
8016452: 681a ldr r2, [r3, #0]
|
|
8016454: 687b ldr r3, [r7, #4]
|
|
8016456: 605a str r2, [r3, #4]
|
|
}
|
|
8016458: bf00 nop
|
|
801645a: 370c adds r7, #12
|
|
801645c: 46bd mov sp, r7
|
|
801645e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8016462: 4770 bx lr
|
|
8016464: 20002654 .word 0x20002654
|
|
8016468: 20002640 .word 0x20002640
|
|
|
|
0801646c <xTaskCheckForTimeOut>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
|
|
TickType_t * const pxTicksToWait )
|
|
{
|
|
801646c: b580 push {r7, lr}
|
|
801646e: b088 sub sp, #32
|
|
8016470: af00 add r7, sp, #0
|
|
8016472: 6078 str r0, [r7, #4]
|
|
8016474: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
|
|
configASSERT( pxTimeOut );
|
|
8016476: 687b ldr r3, [r7, #4]
|
|
8016478: 2b00 cmp r3, #0
|
|
801647a: d10b bne.n 8016494 <xTaskCheckForTimeOut+0x28>
|
|
__asm volatile
|
|
801647c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016480: f383 8811 msr BASEPRI, r3
|
|
8016484: f3bf 8f6f isb sy
|
|
8016488: f3bf 8f4f dsb sy
|
|
801648c: 613b str r3, [r7, #16]
|
|
}
|
|
801648e: bf00 nop
|
|
8016490: bf00 nop
|
|
8016492: e7fd b.n 8016490 <xTaskCheckForTimeOut+0x24>
|
|
configASSERT( pxTicksToWait );
|
|
8016494: 683b ldr r3, [r7, #0]
|
|
8016496: 2b00 cmp r3, #0
|
|
8016498: d10b bne.n 80164b2 <xTaskCheckForTimeOut+0x46>
|
|
__asm volatile
|
|
801649a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801649e: f383 8811 msr BASEPRI, r3
|
|
80164a2: f3bf 8f6f isb sy
|
|
80164a6: f3bf 8f4f dsb sy
|
|
80164aa: 60fb str r3, [r7, #12]
|
|
}
|
|
80164ac: bf00 nop
|
|
80164ae: bf00 nop
|
|
80164b0: e7fd b.n 80164ae <xTaskCheckForTimeOut+0x42>
|
|
|
|
taskENTER_CRITICAL();
|
|
80164b2: f001 fc3d bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this block. */
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
80164b6: 4b1f ldr r3, [pc, #124] @ (8016534 <xTaskCheckForTimeOut+0xc8>)
|
|
80164b8: 681b ldr r3, [r3, #0]
|
|
80164ba: 61bb str r3, [r7, #24]
|
|
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
|
|
80164bc: 687b ldr r3, [r7, #4]
|
|
80164be: 685b ldr r3, [r3, #4]
|
|
80164c0: 69ba ldr r2, [r7, #24]
|
|
80164c2: 1ad3 subs r3, r2, r3
|
|
80164c4: 617b str r3, [r7, #20]
|
|
}
|
|
else
|
|
#endif
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
if( *pxTicksToWait == portMAX_DELAY )
|
|
80164c6: 683b ldr r3, [r7, #0]
|
|
80164c8: 681b ldr r3, [r3, #0]
|
|
80164ca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
80164ce: d102 bne.n 80164d6 <xTaskCheckForTimeOut+0x6a>
|
|
{
|
|
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
|
|
* specified is the maximum block time then the task should block
|
|
* indefinitely, and therefore never time out. */
|
|
xReturn = pdFALSE;
|
|
80164d0: 2300 movs r3, #0
|
|
80164d2: 61fb str r3, [r7, #28]
|
|
80164d4: e026 b.n 8016524 <xTaskCheckForTimeOut+0xb8>
|
|
}
|
|
else
|
|
#endif
|
|
|
|
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
|
|
80164d6: 687b ldr r3, [r7, #4]
|
|
80164d8: 681a ldr r2, [r3, #0]
|
|
80164da: 4b17 ldr r3, [pc, #92] @ (8016538 <xTaskCheckForTimeOut+0xcc>)
|
|
80164dc: 681b ldr r3, [r3, #0]
|
|
80164de: 429a cmp r2, r3
|
|
80164e0: d00a beq.n 80164f8 <xTaskCheckForTimeOut+0x8c>
|
|
80164e2: 687b ldr r3, [r7, #4]
|
|
80164e4: 685b ldr r3, [r3, #4]
|
|
80164e6: 69ba ldr r2, [r7, #24]
|
|
80164e8: 429a cmp r2, r3
|
|
80164ea: d305 bcc.n 80164f8 <xTaskCheckForTimeOut+0x8c>
|
|
/* The tick count is greater than the time at which
|
|
* vTaskSetTimeout() was called, but has also overflowed since
|
|
* vTaskSetTimeOut() was called. It must have wrapped all the way
|
|
* around and gone past again. This passed since vTaskSetTimeout()
|
|
* was called. */
|
|
xReturn = pdTRUE;
|
|
80164ec: 2301 movs r3, #1
|
|
80164ee: 61fb str r3, [r7, #28]
|
|
*pxTicksToWait = ( TickType_t ) 0;
|
|
80164f0: 683b ldr r3, [r7, #0]
|
|
80164f2: 2200 movs r2, #0
|
|
80164f4: 601a str r2, [r3, #0]
|
|
80164f6: e015 b.n 8016524 <xTaskCheckForTimeOut+0xb8>
|
|
}
|
|
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
|
|
80164f8: 683b ldr r3, [r7, #0]
|
|
80164fa: 681b ldr r3, [r3, #0]
|
|
80164fc: 697a ldr r2, [r7, #20]
|
|
80164fe: 429a cmp r2, r3
|
|
8016500: d20b bcs.n 801651a <xTaskCheckForTimeOut+0xae>
|
|
{
|
|
/* Not a genuine timeout. Adjust parameters for time remaining. */
|
|
*pxTicksToWait -= xElapsedTime;
|
|
8016502: 683b ldr r3, [r7, #0]
|
|
8016504: 681a ldr r2, [r3, #0]
|
|
8016506: 697b ldr r3, [r7, #20]
|
|
8016508: 1ad2 subs r2, r2, r3
|
|
801650a: 683b ldr r3, [r7, #0]
|
|
801650c: 601a str r2, [r3, #0]
|
|
vTaskInternalSetTimeOutState( pxTimeOut );
|
|
801650e: 6878 ldr r0, [r7, #4]
|
|
8016510: f7ff ff96 bl 8016440 <vTaskInternalSetTimeOutState>
|
|
xReturn = pdFALSE;
|
|
8016514: 2300 movs r3, #0
|
|
8016516: 61fb str r3, [r7, #28]
|
|
8016518: e004 b.n 8016524 <xTaskCheckForTimeOut+0xb8>
|
|
}
|
|
else
|
|
{
|
|
*pxTicksToWait = ( TickType_t ) 0;
|
|
801651a: 683b ldr r3, [r7, #0]
|
|
801651c: 2200 movs r2, #0
|
|
801651e: 601a str r2, [r3, #0]
|
|
xReturn = pdTRUE;
|
|
8016520: 2301 movs r3, #1
|
|
8016522: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8016524: f001 fc36 bl 8017d94 <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
8016528: 69fb ldr r3, [r7, #28]
|
|
}
|
|
801652a: 4618 mov r0, r3
|
|
801652c: 3720 adds r7, #32
|
|
801652e: 46bd mov sp, r7
|
|
8016530: bd80 pop {r7, pc}
|
|
8016532: bf00 nop
|
|
8016534: 20002640 .word 0x20002640
|
|
8016538: 20002654 .word 0x20002654
|
|
|
|
0801653c <vTaskMissedYield>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskMissedYield( void )
|
|
{
|
|
801653c: b480 push {r7}
|
|
801653e: af00 add r7, sp, #0
|
|
xYieldPending = pdTRUE;
|
|
8016540: 4b03 ldr r3, [pc, #12] @ (8016550 <vTaskMissedYield+0x14>)
|
|
8016542: 2201 movs r2, #1
|
|
8016544: 601a str r2, [r3, #0]
|
|
}
|
|
8016546: bf00 nop
|
|
8016548: 46bd mov sp, r7
|
|
801654a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801654e: 4770 bx lr
|
|
8016550: 20002650 .word 0x20002650
|
|
|
|
08016554 <prvIdleTask>:
|
|
* void prvIdleTask( void *pvParameters );
|
|
*
|
|
*/
|
|
|
|
static portTASK_FUNCTION( prvIdleTask, pvParameters )
|
|
{
|
|
8016554: b580 push {r7, lr}
|
|
8016556: b082 sub sp, #8
|
|
8016558: af00 add r7, sp, #0
|
|
801655a: 6078 str r0, [r7, #4]
|
|
|
|
for( ; ; )
|
|
{
|
|
/* See if any tasks have deleted themselves - if so then the idle task
|
|
* is responsible for freeing the deleted task's TCB and stack. */
|
|
prvCheckTasksWaitingTermination();
|
|
801655c: f000 f852 bl 8016604 <prvCheckTasksWaitingTermination>
|
|
*
|
|
* A critical region is not required here as we are just reading from
|
|
* the list, and an occasional incorrect value will not matter. If
|
|
* the ready list at the idle priority contains more than one task
|
|
* then a task other than the idle task is ready to execute. */
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
|
|
8016560: 4b06 ldr r3, [pc, #24] @ (801657c <prvIdleTask+0x28>)
|
|
8016562: 681b ldr r3, [r3, #0]
|
|
8016564: 2b01 cmp r3, #1
|
|
8016566: d9f9 bls.n 801655c <prvIdleTask+0x8>
|
|
{
|
|
taskYIELD();
|
|
8016568: 4b05 ldr r3, [pc, #20] @ (8016580 <prvIdleTask+0x2c>)
|
|
801656a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
801656e: 601a str r2, [r3, #0]
|
|
8016570: f3bf 8f4f dsb sy
|
|
8016574: f3bf 8f6f isb sy
|
|
prvCheckTasksWaitingTermination();
|
|
8016578: e7f0 b.n 801655c <prvIdleTask+0x8>
|
|
801657a: bf00 nop
|
|
801657c: 2000216c .word 0x2000216c
|
|
8016580: e000ed04 .word 0xe000ed04
|
|
|
|
08016584 <prvInitialiseTaskLists>:
|
|
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInitialiseTaskLists( void )
|
|
{
|
|
8016584: b580 push {r7, lr}
|
|
8016586: b082 sub sp, #8
|
|
8016588: af00 add r7, sp, #0
|
|
UBaseType_t uxPriority;
|
|
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
|
801658a: 2300 movs r3, #0
|
|
801658c: 607b str r3, [r7, #4]
|
|
801658e: e00c b.n 80165aa <prvInitialiseTaskLists+0x26>
|
|
{
|
|
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
|
|
8016590: 687a ldr r2, [r7, #4]
|
|
8016592: 4613 mov r3, r2
|
|
8016594: 009b lsls r3, r3, #2
|
|
8016596: 4413 add r3, r2
|
|
8016598: 009b lsls r3, r3, #2
|
|
801659a: 4a12 ldr r2, [pc, #72] @ (80165e4 <prvInitialiseTaskLists+0x60>)
|
|
801659c: 4413 add r3, r2
|
|
801659e: 4618 mov r0, r3
|
|
80165a0: f7fd fee4 bl 801436c <vListInitialise>
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
|
80165a4: 687b ldr r3, [r7, #4]
|
|
80165a6: 3301 adds r3, #1
|
|
80165a8: 607b str r3, [r7, #4]
|
|
80165aa: 687b ldr r3, [r7, #4]
|
|
80165ac: 2b37 cmp r3, #55 @ 0x37
|
|
80165ae: d9ef bls.n 8016590 <prvInitialiseTaskLists+0xc>
|
|
}
|
|
|
|
vListInitialise( &xDelayedTaskList1 );
|
|
80165b0: 480d ldr r0, [pc, #52] @ (80165e8 <prvInitialiseTaskLists+0x64>)
|
|
80165b2: f7fd fedb bl 801436c <vListInitialise>
|
|
vListInitialise( &xDelayedTaskList2 );
|
|
80165b6: 480d ldr r0, [pc, #52] @ (80165ec <prvInitialiseTaskLists+0x68>)
|
|
80165b8: f7fd fed8 bl 801436c <vListInitialise>
|
|
vListInitialise( &xPendingReadyList );
|
|
80165bc: 480c ldr r0, [pc, #48] @ (80165f0 <prvInitialiseTaskLists+0x6c>)
|
|
80165be: f7fd fed5 bl 801436c <vListInitialise>
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
{
|
|
vListInitialise( &xTasksWaitingTermination );
|
|
80165c2: 480c ldr r0, [pc, #48] @ (80165f4 <prvInitialiseTaskLists+0x70>)
|
|
80165c4: f7fd fed2 bl 801436c <vListInitialise>
|
|
}
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
vListInitialise( &xSuspendedTaskList );
|
|
80165c8: 480b ldr r0, [pc, #44] @ (80165f8 <prvInitialiseTaskLists+0x74>)
|
|
80165ca: f7fd fecf bl 801436c <vListInitialise>
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
|
|
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
|
|
* using list2. */
|
|
pxDelayedTaskList = &xDelayedTaskList1;
|
|
80165ce: 4b0b ldr r3, [pc, #44] @ (80165fc <prvInitialiseTaskLists+0x78>)
|
|
80165d0: 4a05 ldr r2, [pc, #20] @ (80165e8 <prvInitialiseTaskLists+0x64>)
|
|
80165d2: 601a str r2, [r3, #0]
|
|
pxOverflowDelayedTaskList = &xDelayedTaskList2;
|
|
80165d4: 4b0a ldr r3, [pc, #40] @ (8016600 <prvInitialiseTaskLists+0x7c>)
|
|
80165d6: 4a05 ldr r2, [pc, #20] @ (80165ec <prvInitialiseTaskLists+0x68>)
|
|
80165d8: 601a str r2, [r3, #0]
|
|
}
|
|
80165da: bf00 nop
|
|
80165dc: 3708 adds r7, #8
|
|
80165de: 46bd mov sp, r7
|
|
80165e0: bd80 pop {r7, pc}
|
|
80165e2: bf00 nop
|
|
80165e4: 2000216c .word 0x2000216c
|
|
80165e8: 200025cc .word 0x200025cc
|
|
80165ec: 200025e0 .word 0x200025e0
|
|
80165f0: 200025fc .word 0x200025fc
|
|
80165f4: 20002610 .word 0x20002610
|
|
80165f8: 20002628 .word 0x20002628
|
|
80165fc: 200025f4 .word 0x200025f4
|
|
8016600: 200025f8 .word 0x200025f8
|
|
|
|
08016604 <prvCheckTasksWaitingTermination>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCheckTasksWaitingTermination( void )
|
|
{
|
|
8016604: b580 push {r7, lr}
|
|
8016606: b082 sub sp, #8
|
|
8016608: af00 add r7, sp, #0
|
|
{
|
|
TCB_t * pxTCB;
|
|
|
|
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
|
|
* being called too often in the idle task. */
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
|
801660a: e019 b.n 8016640 <prvCheckTasksWaitingTermination+0x3c>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
801660c: f001 fb90 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
8016610: 4b10 ldr r3, [pc, #64] @ (8016654 <prvCheckTasksWaitingTermination+0x50>)
|
|
8016612: 68db ldr r3, [r3, #12]
|
|
8016614: 68db ldr r3, [r3, #12]
|
|
8016616: 607b str r3, [r7, #4]
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
8016618: 687b ldr r3, [r7, #4]
|
|
801661a: 3304 adds r3, #4
|
|
801661c: 4618 mov r0, r3
|
|
801661e: f7fd ff0b bl 8014438 <uxListRemove>
|
|
--uxCurrentNumberOfTasks;
|
|
8016622: 4b0d ldr r3, [pc, #52] @ (8016658 <prvCheckTasksWaitingTermination+0x54>)
|
|
8016624: 681b ldr r3, [r3, #0]
|
|
8016626: 3b01 subs r3, #1
|
|
8016628: 4a0b ldr r2, [pc, #44] @ (8016658 <prvCheckTasksWaitingTermination+0x54>)
|
|
801662a: 6013 str r3, [r2, #0]
|
|
--uxDeletedTasksWaitingCleanUp;
|
|
801662c: 4b0b ldr r3, [pc, #44] @ (801665c <prvCheckTasksWaitingTermination+0x58>)
|
|
801662e: 681b ldr r3, [r3, #0]
|
|
8016630: 3b01 subs r3, #1
|
|
8016632: 4a0a ldr r2, [pc, #40] @ (801665c <prvCheckTasksWaitingTermination+0x58>)
|
|
8016634: 6013 str r3, [r2, #0]
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8016636: f001 fbad bl 8017d94 <vPortExitCritical>
|
|
|
|
prvDeleteTCB( pxTCB );
|
|
801663a: 6878 ldr r0, [r7, #4]
|
|
801663c: f000 f810 bl 8016660 <prvDeleteTCB>
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
|
8016640: 4b06 ldr r3, [pc, #24] @ (801665c <prvCheckTasksWaitingTermination+0x58>)
|
|
8016642: 681b ldr r3, [r3, #0]
|
|
8016644: 2b00 cmp r3, #0
|
|
8016646: d1e1 bne.n 801660c <prvCheckTasksWaitingTermination+0x8>
|
|
}
|
|
}
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
}
|
|
8016648: bf00 nop
|
|
801664a: bf00 nop
|
|
801664c: 3708 adds r7, #8
|
|
801664e: 46bd mov sp, r7
|
|
8016650: bd80 pop {r7, pc}
|
|
8016652: bf00 nop
|
|
8016654: 20002610 .word 0x20002610
|
|
8016658: 2000263c .word 0x2000263c
|
|
801665c: 20002624 .word 0x20002624
|
|
|
|
08016660 <prvDeleteTCB>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
|
|
static void prvDeleteTCB( TCB_t * pxTCB )
|
|
{
|
|
8016660: b580 push {r7, lr}
|
|
8016662: b084 sub sp, #16
|
|
8016664: af00 add r7, sp, #0
|
|
8016666: 6078 str r0, [r7, #4]
|
|
portCLEAN_UP_TCB( pxTCB );
|
|
|
|
#if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
|
|
{
|
|
/* Free up the memory allocated for the task's TLS Block. */
|
|
configDEINIT_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
|
|
8016668: 4b18 ldr r3, [pc, #96] @ (80166cc <prvDeleteTCB+0x6c>)
|
|
801666a: 681b ldr r3, [r3, #0]
|
|
801666c: 3354 adds r3, #84 @ 0x54
|
|
801666e: 4618 mov r0, r3
|
|
8016670: f003 fe64 bl 801a33c <_reclaim_reent>
|
|
#elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* The task could have been allocated statically or dynamically, so
|
|
* check what was statically allocated before trying to free the
|
|
* memory. */
|
|
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
|
|
8016674: 687b ldr r3, [r7, #4]
|
|
8016676: f893 30aa ldrb.w r3, [r3, #170] @ 0xaa
|
|
801667a: 2b00 cmp r3, #0
|
|
801667c: d108 bne.n 8016690 <prvDeleteTCB+0x30>
|
|
{
|
|
/* Both the stack and TCB were allocated dynamically, so both
|
|
* must be freed. */
|
|
vPortFreeStack( pxTCB->pxStack );
|
|
801667e: 687b ldr r3, [r7, #4]
|
|
8016680: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8016682: 4618 mov r0, r3
|
|
8016684: f001 fd48 bl 8018118 <vPortFree>
|
|
vPortFree( pxTCB );
|
|
8016688: 6878 ldr r0, [r7, #4]
|
|
801668a: f001 fd45 bl 8018118 <vPortFree>
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
}
|
|
801668e: e019 b.n 80166c4 <prvDeleteTCB+0x64>
|
|
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
|
|
8016690: 687b ldr r3, [r7, #4]
|
|
8016692: f893 30aa ldrb.w r3, [r3, #170] @ 0xaa
|
|
8016696: 2b01 cmp r3, #1
|
|
8016698: d103 bne.n 80166a2 <prvDeleteTCB+0x42>
|
|
vPortFree( pxTCB );
|
|
801669a: 6878 ldr r0, [r7, #4]
|
|
801669c: f001 fd3c bl 8018118 <vPortFree>
|
|
}
|
|
80166a0: e010 b.n 80166c4 <prvDeleteTCB+0x64>
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
|
80166a2: 687b ldr r3, [r7, #4]
|
|
80166a4: f893 30aa ldrb.w r3, [r3, #170] @ 0xaa
|
|
80166a8: 2b02 cmp r3, #2
|
|
80166aa: d00b beq.n 80166c4 <prvDeleteTCB+0x64>
|
|
__asm volatile
|
|
80166ac: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80166b0: f383 8811 msr BASEPRI, r3
|
|
80166b4: f3bf 8f6f isb sy
|
|
80166b8: f3bf 8f4f dsb sy
|
|
80166bc: 60fb str r3, [r7, #12]
|
|
}
|
|
80166be: bf00 nop
|
|
80166c0: bf00 nop
|
|
80166c2: e7fd b.n 80166c0 <prvDeleteTCB+0x60>
|
|
}
|
|
80166c4: bf00 nop
|
|
80166c6: 3710 adds r7, #16
|
|
80166c8: 46bd mov sp, r7
|
|
80166ca: bd80 pop {r7, pc}
|
|
80166cc: 20002168 .word 0x20002168
|
|
|
|
080166d0 <prvResetNextTaskUnblockTime>:
|
|
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvResetNextTaskUnblockTime( void )
|
|
{
|
|
80166d0: b480 push {r7}
|
|
80166d2: af00 add r7, sp, #0
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
80166d4: 4b0a ldr r3, [pc, #40] @ (8016700 <prvResetNextTaskUnblockTime+0x30>)
|
|
80166d6: 681b ldr r3, [r3, #0]
|
|
80166d8: 681b ldr r3, [r3, #0]
|
|
80166da: 2b00 cmp r3, #0
|
|
80166dc: d104 bne.n 80166e8 <prvResetNextTaskUnblockTime+0x18>
|
|
{
|
|
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
|
|
* the maximum possible value so it is extremely unlikely that the
|
|
* if( xTickCount >= xNextTaskUnblockTime ) test will pass until
|
|
* there is an item in the delayed list. */
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
80166de: 4b09 ldr r3, [pc, #36] @ (8016704 <prvResetNextTaskUnblockTime+0x34>)
|
|
80166e0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80166e4: 601a str r2, [r3, #0]
|
|
* the item at the head of the delayed list. This is the time at
|
|
* which the task at the head of the delayed list should be removed
|
|
* from the Blocked state. */
|
|
xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );
|
|
}
|
|
}
|
|
80166e6: e005 b.n 80166f4 <prvResetNextTaskUnblockTime+0x24>
|
|
xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );
|
|
80166e8: 4b05 ldr r3, [pc, #20] @ (8016700 <prvResetNextTaskUnblockTime+0x30>)
|
|
80166ea: 681b ldr r3, [r3, #0]
|
|
80166ec: 68db ldr r3, [r3, #12]
|
|
80166ee: 681b ldr r3, [r3, #0]
|
|
80166f0: 4a04 ldr r2, [pc, #16] @ (8016704 <prvResetNextTaskUnblockTime+0x34>)
|
|
80166f2: 6013 str r3, [r2, #0]
|
|
}
|
|
80166f4: bf00 nop
|
|
80166f6: 46bd mov sp, r7
|
|
80166f8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80166fc: 4770 bx lr
|
|
80166fe: bf00 nop
|
|
8016700: 200025f4 .word 0x200025f4
|
|
8016704: 2000265c .word 0x2000265c
|
|
|
|
08016708 <xTaskGetCurrentTaskHandle>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
|
|
|
|
TaskHandle_t xTaskGetCurrentTaskHandle( void )
|
|
{
|
|
8016708: b480 push {r7}
|
|
801670a: b083 sub sp, #12
|
|
801670c: af00 add r7, sp, #0
|
|
TaskHandle_t xReturn;
|
|
|
|
/* A critical section is not required as this is not called from
|
|
* an interrupt and the current TCB will always be the same for any
|
|
* individual execution thread. */
|
|
xReturn = pxCurrentTCB;
|
|
801670e: 4b05 ldr r3, [pc, #20] @ (8016724 <xTaskGetCurrentTaskHandle+0x1c>)
|
|
8016710: 681b ldr r3, [r3, #0]
|
|
8016712: 607b str r3, [r7, #4]
|
|
|
|
return xReturn;
|
|
8016714: 687b ldr r3, [r7, #4]
|
|
}
|
|
8016716: 4618 mov r0, r3
|
|
8016718: 370c adds r7, #12
|
|
801671a: 46bd mov sp, r7
|
|
801671c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8016720: 4770 bx lr
|
|
8016722: bf00 nop
|
|
8016724: 20002168 .word 0x20002168
|
|
|
|
08016728 <xTaskGetSchedulerState>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
|
|
BaseType_t xTaskGetSchedulerState( void )
|
|
{
|
|
8016728: b480 push {r7}
|
|
801672a: b083 sub sp, #12
|
|
801672c: af00 add r7, sp, #0
|
|
BaseType_t xReturn;
|
|
|
|
if( xSchedulerRunning == pdFALSE )
|
|
801672e: 4b0b ldr r3, [pc, #44] @ (801675c <xTaskGetSchedulerState+0x34>)
|
|
8016730: 681b ldr r3, [r3, #0]
|
|
8016732: 2b00 cmp r3, #0
|
|
8016734: d102 bne.n 801673c <xTaskGetSchedulerState+0x14>
|
|
{
|
|
xReturn = taskSCHEDULER_NOT_STARTED;
|
|
8016736: 2301 movs r3, #1
|
|
8016738: 607b str r3, [r7, #4]
|
|
801673a: e008 b.n 801674e <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
|
|
801673c: 4b08 ldr r3, [pc, #32] @ (8016760 <xTaskGetSchedulerState+0x38>)
|
|
801673e: 681b ldr r3, [r3, #0]
|
|
8016740: 2b00 cmp r3, #0
|
|
8016742: d102 bne.n 801674a <xTaskGetSchedulerState+0x22>
|
|
{
|
|
xReturn = taskSCHEDULER_RUNNING;
|
|
8016744: 2302 movs r3, #2
|
|
8016746: 607b str r3, [r7, #4]
|
|
8016748: e001 b.n 801674e <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
xReturn = taskSCHEDULER_SUSPENDED;
|
|
801674a: 2300 movs r3, #0
|
|
801674c: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
return xReturn;
|
|
801674e: 687b ldr r3, [r7, #4]
|
|
}
|
|
8016750: 4618 mov r0, r3
|
|
8016752: 370c adds r7, #12
|
|
8016754: 46bd mov sp, r7
|
|
8016756: f85d 7b04 ldr.w r7, [sp], #4
|
|
801675a: 4770 bx lr
|
|
801675c: 20002648 .word 0x20002648
|
|
8016760: 20002664 .word 0x20002664
|
|
|
|
08016764 <xTaskPriorityInherit>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
|
|
{
|
|
8016764: b580 push {r7, lr}
|
|
8016766: b086 sub sp, #24
|
|
8016768: af00 add r7, sp, #0
|
|
801676a: 6078 str r0, [r7, #4]
|
|
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
|
|
801676c: 687b ldr r3, [r7, #4]
|
|
801676e: 613b str r3, [r7, #16]
|
|
BaseType_t xReturn = pdFALSE;
|
|
8016770: 2300 movs r3, #0
|
|
8016772: 617b str r3, [r7, #20]
|
|
|
|
/* If the mutex was given back by an interrupt while the queue was
|
|
* locked then the mutex holder might now be NULL. _RB_ Is this still
|
|
* needed as interrupts can no longer use mutexes? */
|
|
if( pxMutexHolder != NULL )
|
|
8016774: 687b ldr r3, [r7, #4]
|
|
8016776: 2b00 cmp r3, #0
|
|
8016778: d079 beq.n 801686e <xTaskPriorityInherit+0x10a>
|
|
{
|
|
/* If the holder of the mutex has a priority below the priority of
|
|
* the task attempting to obtain the mutex then it will temporarily
|
|
* inherit the priority of the task attempting to obtain the mutex. */
|
|
if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
|
|
801677a: 693b ldr r3, [r7, #16]
|
|
801677c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
801677e: 4b3e ldr r3, [pc, #248] @ (8016878 <xTaskPriorityInherit+0x114>)
|
|
8016780: 681b ldr r3, [r3, #0]
|
|
8016782: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016784: 429a cmp r2, r3
|
|
8016786: d269 bcs.n 801685c <xTaskPriorityInherit+0xf8>
|
|
{
|
|
/* Adjust the mutex holder state to account for its new
|
|
* priority. Only reset the event list item value if the value is
|
|
* not being used for anything else. */
|
|
if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
|
|
8016788: 693b ldr r3, [r7, #16]
|
|
801678a: 699b ldr r3, [r3, #24]
|
|
801678c: 2b00 cmp r3, #0
|
|
801678e: db06 blt.n 801679e <xTaskPriorityInherit+0x3a>
|
|
{
|
|
listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
8016790: 4b39 ldr r3, [pc, #228] @ (8016878 <xTaskPriorityInherit+0x114>)
|
|
8016792: 681b ldr r3, [r3, #0]
|
|
8016794: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016796: f1c3 0238 rsb r2, r3, #56 @ 0x38
|
|
801679a: 693b ldr r3, [r7, #16]
|
|
801679c: 619a str r2, [r3, #24]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* If the task being modified is in the ready state it will need
|
|
* to be moved into a new list. */
|
|
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
|
|
801679e: 693b ldr r3, [r7, #16]
|
|
80167a0: 6959 ldr r1, [r3, #20]
|
|
80167a2: 693b ldr r3, [r7, #16]
|
|
80167a4: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80167a6: 4613 mov r3, r2
|
|
80167a8: 009b lsls r3, r3, #2
|
|
80167aa: 4413 add r3, r2
|
|
80167ac: 009b lsls r3, r3, #2
|
|
80167ae: 4a33 ldr r2, [pc, #204] @ (801687c <xTaskPriorityInherit+0x118>)
|
|
80167b0: 4413 add r3, r2
|
|
80167b2: 4299 cmp r1, r3
|
|
80167b4: d14a bne.n 801684c <xTaskPriorityInherit+0xe8>
|
|
{
|
|
if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
80167b6: 693b ldr r3, [r7, #16]
|
|
80167b8: 3304 adds r3, #4
|
|
80167ba: 4618 mov r0, r3
|
|
80167bc: f7fd fe3c bl 8014438 <uxListRemove>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Inherit the priority before being moved into the new list. */
|
|
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
|
|
80167c0: 4b2d ldr r3, [pc, #180] @ (8016878 <xTaskPriorityInherit+0x114>)
|
|
80167c2: 681b ldr r3, [r3, #0]
|
|
80167c4: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80167c6: 693b ldr r3, [r7, #16]
|
|
80167c8: 62da str r2, [r3, #44] @ 0x2c
|
|
prvAddTaskToReadyList( pxMutexHolderTCB );
|
|
80167ca: 693b ldr r3, [r7, #16]
|
|
80167cc: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80167ce: 4b2c ldr r3, [pc, #176] @ (8016880 <xTaskPriorityInherit+0x11c>)
|
|
80167d0: 681b ldr r3, [r3, #0]
|
|
80167d2: 429a cmp r2, r3
|
|
80167d4: d903 bls.n 80167de <xTaskPriorityInherit+0x7a>
|
|
80167d6: 693b ldr r3, [r7, #16]
|
|
80167d8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80167da: 4a29 ldr r2, [pc, #164] @ (8016880 <xTaskPriorityInherit+0x11c>)
|
|
80167dc: 6013 str r3, [r2, #0]
|
|
80167de: 693b ldr r3, [r7, #16]
|
|
80167e0: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80167e2: 4926 ldr r1, [pc, #152] @ (801687c <xTaskPriorityInherit+0x118>)
|
|
80167e4: 4613 mov r3, r2
|
|
80167e6: 009b lsls r3, r3, #2
|
|
80167e8: 4413 add r3, r2
|
|
80167ea: 009b lsls r3, r3, #2
|
|
80167ec: 440b add r3, r1
|
|
80167ee: 3304 adds r3, #4
|
|
80167f0: 681b ldr r3, [r3, #0]
|
|
80167f2: 60fb str r3, [r7, #12]
|
|
80167f4: 693b ldr r3, [r7, #16]
|
|
80167f6: 68fa ldr r2, [r7, #12]
|
|
80167f8: 609a str r2, [r3, #8]
|
|
80167fa: 68fb ldr r3, [r7, #12]
|
|
80167fc: 689a ldr r2, [r3, #8]
|
|
80167fe: 693b ldr r3, [r7, #16]
|
|
8016800: 60da str r2, [r3, #12]
|
|
8016802: 68fb ldr r3, [r7, #12]
|
|
8016804: 689b ldr r3, [r3, #8]
|
|
8016806: 693a ldr r2, [r7, #16]
|
|
8016808: 3204 adds r2, #4
|
|
801680a: 605a str r2, [r3, #4]
|
|
801680c: 693b ldr r3, [r7, #16]
|
|
801680e: 1d1a adds r2, r3, #4
|
|
8016810: 68fb ldr r3, [r7, #12]
|
|
8016812: 609a str r2, [r3, #8]
|
|
8016814: 693b ldr r3, [r7, #16]
|
|
8016816: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016818: 4613 mov r3, r2
|
|
801681a: 009b lsls r3, r3, #2
|
|
801681c: 4413 add r3, r2
|
|
801681e: 009b lsls r3, r3, #2
|
|
8016820: 4a16 ldr r2, [pc, #88] @ (801687c <xTaskPriorityInherit+0x118>)
|
|
8016822: 441a add r2, r3
|
|
8016824: 693b ldr r3, [r7, #16]
|
|
8016826: 615a str r2, [r3, #20]
|
|
8016828: 693b ldr r3, [r7, #16]
|
|
801682a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
801682c: 4913 ldr r1, [pc, #76] @ (801687c <xTaskPriorityInherit+0x118>)
|
|
801682e: 4613 mov r3, r2
|
|
8016830: 009b lsls r3, r3, #2
|
|
8016832: 4413 add r3, r2
|
|
8016834: 009b lsls r3, r3, #2
|
|
8016836: 440b add r3, r1
|
|
8016838: 681b ldr r3, [r3, #0]
|
|
801683a: 1c59 adds r1, r3, #1
|
|
801683c: 480f ldr r0, [pc, #60] @ (801687c <xTaskPriorityInherit+0x118>)
|
|
801683e: 4613 mov r3, r2
|
|
8016840: 009b lsls r3, r3, #2
|
|
8016842: 4413 add r3, r2
|
|
8016844: 009b lsls r3, r3, #2
|
|
8016846: 4403 add r3, r0
|
|
8016848: 6019 str r1, [r3, #0]
|
|
801684a: e004 b.n 8016856 <xTaskPriorityInherit+0xf2>
|
|
}
|
|
else
|
|
{
|
|
/* Just inherit the priority. */
|
|
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
|
|
801684c: 4b0a ldr r3, [pc, #40] @ (8016878 <xTaskPriorityInherit+0x114>)
|
|
801684e: 681b ldr r3, [r3, #0]
|
|
8016850: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016852: 693b ldr r3, [r7, #16]
|
|
8016854: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
|
|
|
|
/* Inheritance occurred. */
|
|
xReturn = pdTRUE;
|
|
8016856: 2301 movs r3, #1
|
|
8016858: 617b str r3, [r7, #20]
|
|
801685a: e008 b.n 801686e <xTaskPriorityInherit+0x10a>
|
|
}
|
|
else
|
|
{
|
|
if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
|
|
801685c: 693b ldr r3, [r7, #16]
|
|
801685e: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8016860: 4b05 ldr r3, [pc, #20] @ (8016878 <xTaskPriorityInherit+0x114>)
|
|
8016862: 681b ldr r3, [r3, #0]
|
|
8016864: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016866: 429a cmp r2, r3
|
|
8016868: d201 bcs.n 801686e <xTaskPriorityInherit+0x10a>
|
|
* current priority of the mutex holder is not lower than the
|
|
* priority of the task attempting to take the mutex.
|
|
* Therefore the mutex holder must have already inherited a
|
|
* priority, but inheritance would have occurred if that had
|
|
* not been the case. */
|
|
xReturn = pdTRUE;
|
|
801686a: 2301 movs r3, #1
|
|
801686c: 617b str r3, [r7, #20]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
801686e: 697b ldr r3, [r7, #20]
|
|
}
|
|
8016870: 4618 mov r0, r3
|
|
8016872: 3718 adds r7, #24
|
|
8016874: 46bd mov sp, r7
|
|
8016876: bd80 pop {r7, pc}
|
|
8016878: 20002168 .word 0x20002168
|
|
801687c: 2000216c .word 0x2000216c
|
|
8016880: 20002644 .word 0x20002644
|
|
|
|
08016884 <xTaskPriorityDisinherit>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
|
|
{
|
|
8016884: b580 push {r7, lr}
|
|
8016886: b088 sub sp, #32
|
|
8016888: af00 add r7, sp, #0
|
|
801688a: 6078 str r0, [r7, #4]
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
|
801688c: 687b ldr r3, [r7, #4]
|
|
801688e: 61bb str r3, [r7, #24]
|
|
BaseType_t xReturn = pdFALSE;
|
|
8016890: 2300 movs r3, #0
|
|
8016892: 61fb str r3, [r7, #28]
|
|
|
|
if( pxMutexHolder != NULL )
|
|
8016894: 687b ldr r3, [r7, #4]
|
|
8016896: 2b00 cmp r3, #0
|
|
8016898: f000 8081 beq.w 801699e <xTaskPriorityDisinherit+0x11a>
|
|
{
|
|
/* A task can only have an inherited priority if it holds the mutex.
|
|
* If the mutex is held by a task then it cannot be given from an
|
|
* interrupt, and if a mutex is given by the holding task then it must
|
|
* be the running state task. */
|
|
configASSERT( pxTCB == pxCurrentTCB );
|
|
801689c: 4b42 ldr r3, [pc, #264] @ (80169a8 <xTaskPriorityDisinherit+0x124>)
|
|
801689e: 681b ldr r3, [r3, #0]
|
|
80168a0: 69ba ldr r2, [r7, #24]
|
|
80168a2: 429a cmp r2, r3
|
|
80168a4: d00b beq.n 80168be <xTaskPriorityDisinherit+0x3a>
|
|
__asm volatile
|
|
80168a6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80168aa: f383 8811 msr BASEPRI, r3
|
|
80168ae: f3bf 8f6f isb sy
|
|
80168b2: f3bf 8f4f dsb sy
|
|
80168b6: 613b str r3, [r7, #16]
|
|
}
|
|
80168b8: bf00 nop
|
|
80168ba: bf00 nop
|
|
80168bc: e7fd b.n 80168ba <xTaskPriorityDisinherit+0x36>
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
|
80168be: 69bb ldr r3, [r7, #24]
|
|
80168c0: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80168c2: 2b00 cmp r3, #0
|
|
80168c4: d10b bne.n 80168de <xTaskPriorityDisinherit+0x5a>
|
|
__asm volatile
|
|
80168c6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80168ca: f383 8811 msr BASEPRI, r3
|
|
80168ce: f3bf 8f6f isb sy
|
|
80168d2: f3bf 8f4f dsb sy
|
|
80168d6: 60fb str r3, [r7, #12]
|
|
}
|
|
80168d8: bf00 nop
|
|
80168da: bf00 nop
|
|
80168dc: e7fd b.n 80168da <xTaskPriorityDisinherit+0x56>
|
|
( pxTCB->uxMutexesHeld )--;
|
|
80168de: 69bb ldr r3, [r7, #24]
|
|
80168e0: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80168e2: 1e5a subs r2, r3, #1
|
|
80168e4: 69bb ldr r3, [r7, #24]
|
|
80168e6: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Has the holder of the mutex inherited the priority of another
|
|
* task? */
|
|
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
|
|
80168e8: 69bb ldr r3, [r7, #24]
|
|
80168ea: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80168ec: 69bb ldr r3, [r7, #24]
|
|
80168ee: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80168f0: 429a cmp r2, r3
|
|
80168f2: d054 beq.n 801699e <xTaskPriorityDisinherit+0x11a>
|
|
{
|
|
/* Only disinherit if no other mutexes are held. */
|
|
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
|
|
80168f4: 69bb ldr r3, [r7, #24]
|
|
80168f6: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80168f8: 2b00 cmp r3, #0
|
|
80168fa: d150 bne.n 801699e <xTaskPriorityDisinherit+0x11a>
|
|
/* A task can only have an inherited priority if it holds
|
|
* the mutex. If the mutex is held by a task then it cannot be
|
|
* given from an interrupt, and if a mutex is given by the
|
|
* holding task then it must be the running state task. Remove
|
|
* the holding task from the ready list. */
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
80168fc: 69bb ldr r3, [r7, #24]
|
|
80168fe: 3304 adds r3, #4
|
|
8016900: 4618 mov r0, r3
|
|
8016902: f7fd fd99 bl 8014438 <uxListRemove>
|
|
}
|
|
|
|
/* Disinherit the priority before adding the task into the
|
|
* new ready list. */
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
|
|
pxTCB->uxPriority = pxTCB->uxBasePriority;
|
|
8016906: 69bb ldr r3, [r7, #24]
|
|
8016908: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
801690a: 69bb ldr r3, [r7, #24]
|
|
801690c: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Reset the event list item value. It cannot be in use for
|
|
* any other purpose if this task is running, and it must be
|
|
* running to give back the mutex. */
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
801690e: 69bb ldr r3, [r7, #24]
|
|
8016910: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016912: f1c3 0238 rsb r2, r3, #56 @ 0x38
|
|
8016916: 69bb ldr r3, [r7, #24]
|
|
8016918: 619a str r2, [r3, #24]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
801691a: 69bb ldr r3, [r7, #24]
|
|
801691c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
801691e: 4b23 ldr r3, [pc, #140] @ (80169ac <xTaskPriorityDisinherit+0x128>)
|
|
8016920: 681b ldr r3, [r3, #0]
|
|
8016922: 429a cmp r2, r3
|
|
8016924: d903 bls.n 801692e <xTaskPriorityDisinherit+0xaa>
|
|
8016926: 69bb ldr r3, [r7, #24]
|
|
8016928: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
801692a: 4a20 ldr r2, [pc, #128] @ (80169ac <xTaskPriorityDisinherit+0x128>)
|
|
801692c: 6013 str r3, [r2, #0]
|
|
801692e: 69bb ldr r3, [r7, #24]
|
|
8016930: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016932: 491f ldr r1, [pc, #124] @ (80169b0 <xTaskPriorityDisinherit+0x12c>)
|
|
8016934: 4613 mov r3, r2
|
|
8016936: 009b lsls r3, r3, #2
|
|
8016938: 4413 add r3, r2
|
|
801693a: 009b lsls r3, r3, #2
|
|
801693c: 440b add r3, r1
|
|
801693e: 3304 adds r3, #4
|
|
8016940: 681b ldr r3, [r3, #0]
|
|
8016942: 617b str r3, [r7, #20]
|
|
8016944: 69bb ldr r3, [r7, #24]
|
|
8016946: 697a ldr r2, [r7, #20]
|
|
8016948: 609a str r2, [r3, #8]
|
|
801694a: 697b ldr r3, [r7, #20]
|
|
801694c: 689a ldr r2, [r3, #8]
|
|
801694e: 69bb ldr r3, [r7, #24]
|
|
8016950: 60da str r2, [r3, #12]
|
|
8016952: 697b ldr r3, [r7, #20]
|
|
8016954: 689b ldr r3, [r3, #8]
|
|
8016956: 69ba ldr r2, [r7, #24]
|
|
8016958: 3204 adds r2, #4
|
|
801695a: 605a str r2, [r3, #4]
|
|
801695c: 69bb ldr r3, [r7, #24]
|
|
801695e: 1d1a adds r2, r3, #4
|
|
8016960: 697b ldr r3, [r7, #20]
|
|
8016962: 609a str r2, [r3, #8]
|
|
8016964: 69bb ldr r3, [r7, #24]
|
|
8016966: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016968: 4613 mov r3, r2
|
|
801696a: 009b lsls r3, r3, #2
|
|
801696c: 4413 add r3, r2
|
|
801696e: 009b lsls r3, r3, #2
|
|
8016970: 4a0f ldr r2, [pc, #60] @ (80169b0 <xTaskPriorityDisinherit+0x12c>)
|
|
8016972: 441a add r2, r3
|
|
8016974: 69bb ldr r3, [r7, #24]
|
|
8016976: 615a str r2, [r3, #20]
|
|
8016978: 69bb ldr r3, [r7, #24]
|
|
801697a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
801697c: 490c ldr r1, [pc, #48] @ (80169b0 <xTaskPriorityDisinherit+0x12c>)
|
|
801697e: 4613 mov r3, r2
|
|
8016980: 009b lsls r3, r3, #2
|
|
8016982: 4413 add r3, r2
|
|
8016984: 009b lsls r3, r3, #2
|
|
8016986: 440b add r3, r1
|
|
8016988: 681b ldr r3, [r3, #0]
|
|
801698a: 1c59 adds r1, r3, #1
|
|
801698c: 4808 ldr r0, [pc, #32] @ (80169b0 <xTaskPriorityDisinherit+0x12c>)
|
|
801698e: 4613 mov r3, r2
|
|
8016990: 009b lsls r3, r3, #2
|
|
8016992: 4413 add r3, r2
|
|
8016994: 009b lsls r3, r3, #2
|
|
8016996: 4403 add r3, r0
|
|
8016998: 6019 str r1, [r3, #0]
|
|
* in an order different to that in which they were taken.
|
|
* If a context switch did not occur when the first mutex was
|
|
* returned, even if a task was waiting on it, then a context
|
|
* switch should occur when the last mutex is returned whether
|
|
* a task is waiting on it or not. */
|
|
xReturn = pdTRUE;
|
|
801699a: 2301 movs r3, #1
|
|
801699c: 61fb str r3, [r7, #28]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
801699e: 69fb ldr r3, [r7, #28]
|
|
}
|
|
80169a0: 4618 mov r0, r3
|
|
80169a2: 3720 adds r7, #32
|
|
80169a4: 46bd mov sp, r7
|
|
80169a6: bd80 pop {r7, pc}
|
|
80169a8: 20002168 .word 0x20002168
|
|
80169ac: 20002644 .word 0x20002644
|
|
80169b0: 2000216c .word 0x2000216c
|
|
|
|
080169b4 <vTaskPriorityDisinheritAfterTimeout>:
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
|
|
UBaseType_t uxHighestPriorityWaitingTask )
|
|
{
|
|
80169b4: b580 push {r7, lr}
|
|
80169b6: b08a sub sp, #40 @ 0x28
|
|
80169b8: af00 add r7, sp, #0
|
|
80169ba: 6078 str r0, [r7, #4]
|
|
80169bc: 6039 str r1, [r7, #0]
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
|
80169be: 687b ldr r3, [r7, #4]
|
|
80169c0: 623b str r3, [r7, #32]
|
|
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
|
|
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
|
|
80169c2: 2301 movs r3, #1
|
|
80169c4: 61fb str r3, [r7, #28]
|
|
|
|
if( pxMutexHolder != NULL )
|
|
80169c6: 687b ldr r3, [r7, #4]
|
|
80169c8: 2b00 cmp r3, #0
|
|
80169ca: f000 8095 beq.w 8016af8 <vTaskPriorityDisinheritAfterTimeout+0x144>
|
|
{
|
|
/* If pxMutexHolder is not NULL then the holder must hold at least
|
|
* one mutex. */
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
|
80169ce: 6a3b ldr r3, [r7, #32]
|
|
80169d0: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80169d2: 2b00 cmp r3, #0
|
|
80169d4: d10b bne.n 80169ee <vTaskPriorityDisinheritAfterTimeout+0x3a>
|
|
__asm volatile
|
|
80169d6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80169da: f383 8811 msr BASEPRI, r3
|
|
80169de: f3bf 8f6f isb sy
|
|
80169e2: f3bf 8f4f dsb sy
|
|
80169e6: 613b str r3, [r7, #16]
|
|
}
|
|
80169e8: bf00 nop
|
|
80169ea: bf00 nop
|
|
80169ec: e7fd b.n 80169ea <vTaskPriorityDisinheritAfterTimeout+0x36>
|
|
|
|
/* Determine the priority to which the priority of the task that
|
|
* holds the mutex should be set. This will be the greater of the
|
|
* holding task's base priority and the priority of the highest
|
|
* priority task that is waiting to obtain the mutex. */
|
|
if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
|
|
80169ee: 6a3b ldr r3, [r7, #32]
|
|
80169f0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80169f2: 683a ldr r2, [r7, #0]
|
|
80169f4: 429a cmp r2, r3
|
|
80169f6: d902 bls.n 80169fe <vTaskPriorityDisinheritAfterTimeout+0x4a>
|
|
{
|
|
uxPriorityToUse = uxHighestPriorityWaitingTask;
|
|
80169f8: 683b ldr r3, [r7, #0]
|
|
80169fa: 627b str r3, [r7, #36] @ 0x24
|
|
80169fc: e002 b.n 8016a04 <vTaskPriorityDisinheritAfterTimeout+0x50>
|
|
}
|
|
else
|
|
{
|
|
uxPriorityToUse = pxTCB->uxBasePriority;
|
|
80169fe: 6a3b ldr r3, [r7, #32]
|
|
8016a00: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8016a02: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
|
|
/* Does the priority need to change? */
|
|
if( pxTCB->uxPriority != uxPriorityToUse )
|
|
8016a04: 6a3b ldr r3, [r7, #32]
|
|
8016a06: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016a08: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8016a0a: 429a cmp r2, r3
|
|
8016a0c: d074 beq.n 8016af8 <vTaskPriorityDisinheritAfterTimeout+0x144>
|
|
{
|
|
/* Only disinherit if no other mutexes are held. This is a
|
|
* simplification in the priority inheritance implementation. If
|
|
* the task that holds the mutex is also holding other mutexes then
|
|
* the other mutexes may have caused the priority inheritance. */
|
|
if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
|
|
8016a0e: 6a3b ldr r3, [r7, #32]
|
|
8016a10: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8016a12: 69fa ldr r2, [r7, #28]
|
|
8016a14: 429a cmp r2, r3
|
|
8016a16: d16f bne.n 8016af8 <vTaskPriorityDisinheritAfterTimeout+0x144>
|
|
{
|
|
/* If a task has timed out because it already holds the
|
|
* mutex it was trying to obtain then it cannot of inherited
|
|
* its own priority. */
|
|
configASSERT( pxTCB != pxCurrentTCB );
|
|
8016a18: 4b39 ldr r3, [pc, #228] @ (8016b00 <vTaskPriorityDisinheritAfterTimeout+0x14c>)
|
|
8016a1a: 681b ldr r3, [r3, #0]
|
|
8016a1c: 6a3a ldr r2, [r7, #32]
|
|
8016a1e: 429a cmp r2, r3
|
|
8016a20: d10b bne.n 8016a3a <vTaskPriorityDisinheritAfterTimeout+0x86>
|
|
__asm volatile
|
|
8016a22: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016a26: f383 8811 msr BASEPRI, r3
|
|
8016a2a: f3bf 8f6f isb sy
|
|
8016a2e: f3bf 8f4f dsb sy
|
|
8016a32: 60fb str r3, [r7, #12]
|
|
}
|
|
8016a34: bf00 nop
|
|
8016a36: bf00 nop
|
|
8016a38: e7fd b.n 8016a36 <vTaskPriorityDisinheritAfterTimeout+0x82>
|
|
|
|
/* Disinherit the priority, remembering the previous
|
|
* priority to facilitate determining the subject task's
|
|
* state. */
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse );
|
|
uxPriorityUsedOnEntry = pxTCB->uxPriority;
|
|
8016a3a: 6a3b ldr r3, [r7, #32]
|
|
8016a3c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016a3e: 61bb str r3, [r7, #24]
|
|
pxTCB->uxPriority = uxPriorityToUse;
|
|
8016a40: 6a3b ldr r3, [r7, #32]
|
|
8016a42: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8016a44: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Only reset the event list item value if the value is not
|
|
* being used for anything else. */
|
|
if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
|
|
8016a46: 6a3b ldr r3, [r7, #32]
|
|
8016a48: 699b ldr r3, [r3, #24]
|
|
8016a4a: 2b00 cmp r3, #0
|
|
8016a4c: db04 blt.n 8016a58 <vTaskPriorityDisinheritAfterTimeout+0xa4>
|
|
{
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
8016a4e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8016a50: f1c3 0238 rsb r2, r3, #56 @ 0x38
|
|
8016a54: 6a3b ldr r3, [r7, #32]
|
|
8016a56: 619a str r2, [r3, #24]
|
|
* then the task that holds the mutex could be in either the
|
|
* Ready, Blocked or Suspended states. Only remove the task
|
|
* from its current state list if it is in the Ready state as
|
|
* the task's priority is going to change and there is one
|
|
* Ready list per priority. */
|
|
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
|
|
8016a58: 6a3b ldr r3, [r7, #32]
|
|
8016a5a: 6959 ldr r1, [r3, #20]
|
|
8016a5c: 69ba ldr r2, [r7, #24]
|
|
8016a5e: 4613 mov r3, r2
|
|
8016a60: 009b lsls r3, r3, #2
|
|
8016a62: 4413 add r3, r2
|
|
8016a64: 009b lsls r3, r3, #2
|
|
8016a66: 4a27 ldr r2, [pc, #156] @ (8016b04 <vTaskPriorityDisinheritAfterTimeout+0x150>)
|
|
8016a68: 4413 add r3, r2
|
|
8016a6a: 4299 cmp r1, r3
|
|
8016a6c: d144 bne.n 8016af8 <vTaskPriorityDisinheritAfterTimeout+0x144>
|
|
{
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
8016a6e: 6a3b ldr r3, [r7, #32]
|
|
8016a70: 3304 adds r3, #4
|
|
8016a72: 4618 mov r0, r3
|
|
8016a74: f7fd fce0 bl 8014438 <uxListRemove>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
prvAddTaskToReadyList( pxTCB );
|
|
8016a78: 6a3b ldr r3, [r7, #32]
|
|
8016a7a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016a7c: 4b22 ldr r3, [pc, #136] @ (8016b08 <vTaskPriorityDisinheritAfterTimeout+0x154>)
|
|
8016a7e: 681b ldr r3, [r3, #0]
|
|
8016a80: 429a cmp r2, r3
|
|
8016a82: d903 bls.n 8016a8c <vTaskPriorityDisinheritAfterTimeout+0xd8>
|
|
8016a84: 6a3b ldr r3, [r7, #32]
|
|
8016a86: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016a88: 4a1f ldr r2, [pc, #124] @ (8016b08 <vTaskPriorityDisinheritAfterTimeout+0x154>)
|
|
8016a8a: 6013 str r3, [r2, #0]
|
|
8016a8c: 6a3b ldr r3, [r7, #32]
|
|
8016a8e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016a90: 491c ldr r1, [pc, #112] @ (8016b04 <vTaskPriorityDisinheritAfterTimeout+0x150>)
|
|
8016a92: 4613 mov r3, r2
|
|
8016a94: 009b lsls r3, r3, #2
|
|
8016a96: 4413 add r3, r2
|
|
8016a98: 009b lsls r3, r3, #2
|
|
8016a9a: 440b add r3, r1
|
|
8016a9c: 3304 adds r3, #4
|
|
8016a9e: 681b ldr r3, [r3, #0]
|
|
8016aa0: 617b str r3, [r7, #20]
|
|
8016aa2: 6a3b ldr r3, [r7, #32]
|
|
8016aa4: 697a ldr r2, [r7, #20]
|
|
8016aa6: 609a str r2, [r3, #8]
|
|
8016aa8: 697b ldr r3, [r7, #20]
|
|
8016aaa: 689a ldr r2, [r3, #8]
|
|
8016aac: 6a3b ldr r3, [r7, #32]
|
|
8016aae: 60da str r2, [r3, #12]
|
|
8016ab0: 697b ldr r3, [r7, #20]
|
|
8016ab2: 689b ldr r3, [r3, #8]
|
|
8016ab4: 6a3a ldr r2, [r7, #32]
|
|
8016ab6: 3204 adds r2, #4
|
|
8016ab8: 605a str r2, [r3, #4]
|
|
8016aba: 6a3b ldr r3, [r7, #32]
|
|
8016abc: 1d1a adds r2, r3, #4
|
|
8016abe: 697b ldr r3, [r7, #20]
|
|
8016ac0: 609a str r2, [r3, #8]
|
|
8016ac2: 6a3b ldr r3, [r7, #32]
|
|
8016ac4: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016ac6: 4613 mov r3, r2
|
|
8016ac8: 009b lsls r3, r3, #2
|
|
8016aca: 4413 add r3, r2
|
|
8016acc: 009b lsls r3, r3, #2
|
|
8016ace: 4a0d ldr r2, [pc, #52] @ (8016b04 <vTaskPriorityDisinheritAfterTimeout+0x150>)
|
|
8016ad0: 441a add r2, r3
|
|
8016ad2: 6a3b ldr r3, [r7, #32]
|
|
8016ad4: 615a str r2, [r3, #20]
|
|
8016ad6: 6a3b ldr r3, [r7, #32]
|
|
8016ad8: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016ada: 490a ldr r1, [pc, #40] @ (8016b04 <vTaskPriorityDisinheritAfterTimeout+0x150>)
|
|
8016adc: 4613 mov r3, r2
|
|
8016ade: 009b lsls r3, r3, #2
|
|
8016ae0: 4413 add r3, r2
|
|
8016ae2: 009b lsls r3, r3, #2
|
|
8016ae4: 440b add r3, r1
|
|
8016ae6: 681b ldr r3, [r3, #0]
|
|
8016ae8: 1c59 adds r1, r3, #1
|
|
8016aea: 4806 ldr r0, [pc, #24] @ (8016b04 <vTaskPriorityDisinheritAfterTimeout+0x150>)
|
|
8016aec: 4613 mov r3, r2
|
|
8016aee: 009b lsls r3, r3, #2
|
|
8016af0: 4413 add r3, r2
|
|
8016af2: 009b lsls r3, r3, #2
|
|
8016af4: 4403 add r3, r0
|
|
8016af6: 6019 str r1, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
8016af8: bf00 nop
|
|
8016afa: 3728 adds r7, #40 @ 0x28
|
|
8016afc: 46bd mov sp, r7
|
|
8016afe: bd80 pop {r7, pc}
|
|
8016b00: 20002168 .word 0x20002168
|
|
8016b04: 2000216c .word 0x2000216c
|
|
8016b08: 20002644 .word 0x20002644
|
|
|
|
08016b0c <pvTaskIncrementMutexHeldCount>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
|
|
{
|
|
8016b0c: b480 push {r7}
|
|
8016b0e: af00 add r7, sp, #0
|
|
/* If xSemaphoreCreateMutex() is called before any tasks have been created
|
|
* then pxCurrentTCB will be NULL. */
|
|
if( pxCurrentTCB != NULL )
|
|
8016b10: 4b07 ldr r3, [pc, #28] @ (8016b30 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
8016b12: 681b ldr r3, [r3, #0]
|
|
8016b14: 2b00 cmp r3, #0
|
|
8016b16: d004 beq.n 8016b22 <pvTaskIncrementMutexHeldCount+0x16>
|
|
{
|
|
( pxCurrentTCB->uxMutexesHeld )++;
|
|
8016b18: 4b05 ldr r3, [pc, #20] @ (8016b30 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
8016b1a: 681b ldr r3, [r3, #0]
|
|
8016b1c: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
8016b1e: 3201 adds r2, #1
|
|
8016b20: 651a str r2, [r3, #80] @ 0x50
|
|
}
|
|
|
|
return pxCurrentTCB;
|
|
8016b22: 4b03 ldr r3, [pc, #12] @ (8016b30 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
8016b24: 681b ldr r3, [r3, #0]
|
|
}
|
|
8016b26: 4618 mov r0, r3
|
|
8016b28: 46bd mov sp, r7
|
|
8016b2a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8016b2e: 4770 bx lr
|
|
8016b30: 20002168 .word 0x20002168
|
|
|
|
08016b34 <ulTaskGenericNotifyTake>:
|
|
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
|
|
|
|
uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait,
|
|
BaseType_t xClearCountOnExit,
|
|
TickType_t xTicksToWait )
|
|
{
|
|
8016b34: b580 push {r7, lr}
|
|
8016b36: b086 sub sp, #24
|
|
8016b38: af00 add r7, sp, #0
|
|
8016b3a: 60f8 str r0, [r7, #12]
|
|
8016b3c: 60b9 str r1, [r7, #8]
|
|
8016b3e: 607a str r2, [r7, #4]
|
|
uint32_t ulReturn;
|
|
|
|
configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
|
|
8016b40: 68fb ldr r3, [r7, #12]
|
|
8016b42: 2b01 cmp r3, #1
|
|
8016b44: d90b bls.n 8016b5e <ulTaskGenericNotifyTake+0x2a>
|
|
__asm volatile
|
|
8016b46: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016b4a: f383 8811 msr BASEPRI, r3
|
|
8016b4e: f3bf 8f6f isb sy
|
|
8016b52: f3bf 8f4f dsb sy
|
|
8016b56: 613b str r3, [r7, #16]
|
|
}
|
|
8016b58: bf00 nop
|
|
8016b5a: bf00 nop
|
|
8016b5c: e7fd b.n 8016b5a <ulTaskGenericNotifyTake+0x26>
|
|
|
|
taskENTER_CRITICAL();
|
|
8016b5e: f001 f8e7 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
/* Only block if the notification count is not already non-zero. */
|
|
if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL )
|
|
8016b62: 4b26 ldr r3, [pc, #152] @ (8016bfc <ulTaskGenericNotifyTake+0xc8>)
|
|
8016b64: 681b ldr r3, [r3, #0]
|
|
8016b66: 68fa ldr r2, [r7, #12]
|
|
8016b68: 3228 adds r2, #40 @ 0x28
|
|
8016b6a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8016b6e: 2b00 cmp r3, #0
|
|
8016b70: d115 bne.n 8016b9e <ulTaskGenericNotifyTake+0x6a>
|
|
{
|
|
/* Mark this task as waiting for a notification. */
|
|
pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
|
|
8016b72: 4b22 ldr r3, [pc, #136] @ (8016bfc <ulTaskGenericNotifyTake+0xc8>)
|
|
8016b74: 681a ldr r2, [r3, #0]
|
|
8016b76: 68fb ldr r3, [r7, #12]
|
|
8016b78: 4413 add r3, r2
|
|
8016b7a: 33a8 adds r3, #168 @ 0xa8
|
|
8016b7c: 2201 movs r2, #1
|
|
8016b7e: 701a strb r2, [r3, #0]
|
|
|
|
if( xTicksToWait > ( TickType_t ) 0 )
|
|
8016b80: 687b ldr r3, [r7, #4]
|
|
8016b82: 2b00 cmp r3, #0
|
|
8016b84: d00b beq.n 8016b9e <ulTaskGenericNotifyTake+0x6a>
|
|
{
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
|
8016b86: 2101 movs r1, #1
|
|
8016b88: 6878 ldr r0, [r7, #4]
|
|
8016b8a: f000 fc4d bl 8017428 <prvAddCurrentTaskToDelayedList>
|
|
|
|
/* All ports are written to allow a yield in a critical
|
|
* section (some will yield immediately, others wait until the
|
|
* critical section exits) - but it is not something that
|
|
* application code should ever do. */
|
|
portYIELD_WITHIN_API();
|
|
8016b8e: 4b1c ldr r3, [pc, #112] @ (8016c00 <ulTaskGenericNotifyTake+0xcc>)
|
|
8016b90: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8016b94: 601a str r2, [r3, #0]
|
|
8016b96: f3bf 8f4f dsb sy
|
|
8016b9a: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8016b9e: f001 f8f9 bl 8017d94 <vPortExitCritical>
|
|
|
|
taskENTER_CRITICAL();
|
|
8016ba2: f001 f8c5 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
traceTASK_NOTIFY_TAKE( uxIndexToWait );
|
|
ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
|
|
8016ba6: 4b15 ldr r3, [pc, #84] @ (8016bfc <ulTaskGenericNotifyTake+0xc8>)
|
|
8016ba8: 681b ldr r3, [r3, #0]
|
|
8016baa: 68fa ldr r2, [r7, #12]
|
|
8016bac: 3228 adds r2, #40 @ 0x28
|
|
8016bae: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8016bb2: 617b str r3, [r7, #20]
|
|
|
|
if( ulReturn != 0UL )
|
|
8016bb4: 697b ldr r3, [r7, #20]
|
|
8016bb6: 2b00 cmp r3, #0
|
|
8016bb8: d012 beq.n 8016be0 <ulTaskGenericNotifyTake+0xac>
|
|
{
|
|
if( xClearCountOnExit != pdFALSE )
|
|
8016bba: 68bb ldr r3, [r7, #8]
|
|
8016bbc: 2b00 cmp r3, #0
|
|
8016bbe: d007 beq.n 8016bd0 <ulTaskGenericNotifyTake+0x9c>
|
|
{
|
|
pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL;
|
|
8016bc0: 4b0e ldr r3, [pc, #56] @ (8016bfc <ulTaskGenericNotifyTake+0xc8>)
|
|
8016bc2: 681b ldr r3, [r3, #0]
|
|
8016bc4: 68fa ldr r2, [r7, #12]
|
|
8016bc6: 3228 adds r2, #40 @ 0x28
|
|
8016bc8: 2100 movs r1, #0
|
|
8016bca: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
8016bce: e007 b.n 8016be0 <ulTaskGenericNotifyTake+0xac>
|
|
}
|
|
else
|
|
{
|
|
pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1;
|
|
8016bd0: 4b0a ldr r3, [pc, #40] @ (8016bfc <ulTaskGenericNotifyTake+0xc8>)
|
|
8016bd2: 681b ldr r3, [r3, #0]
|
|
8016bd4: 697a ldr r2, [r7, #20]
|
|
8016bd6: 1e51 subs r1, r2, #1
|
|
8016bd8: 68fa ldr r2, [r7, #12]
|
|
8016bda: 3228 adds r2, #40 @ 0x28
|
|
8016bdc: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
|
|
8016be0: 4b06 ldr r3, [pc, #24] @ (8016bfc <ulTaskGenericNotifyTake+0xc8>)
|
|
8016be2: 681a ldr r2, [r3, #0]
|
|
8016be4: 68fb ldr r3, [r7, #12]
|
|
8016be6: 4413 add r3, r2
|
|
8016be8: 33a8 adds r3, #168 @ 0xa8
|
|
8016bea: 2200 movs r2, #0
|
|
8016bec: 701a strb r2, [r3, #0]
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8016bee: f001 f8d1 bl 8017d94 <vPortExitCritical>
|
|
|
|
return ulReturn;
|
|
8016bf2: 697b ldr r3, [r7, #20]
|
|
}
|
|
8016bf4: 4618 mov r0, r3
|
|
8016bf6: 3718 adds r7, #24
|
|
8016bf8: 46bd mov sp, r7
|
|
8016bfa: bd80 pop {r7, pc}
|
|
8016bfc: 20002168 .word 0x20002168
|
|
8016c00: e000ed04 .word 0xe000ed04
|
|
|
|
08016c04 <xTaskGenericNotifyWait>:
|
|
BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait,
|
|
uint32_t ulBitsToClearOnEntry,
|
|
uint32_t ulBitsToClearOnExit,
|
|
uint32_t * pulNotificationValue,
|
|
TickType_t xTicksToWait )
|
|
{
|
|
8016c04: b580 push {r7, lr}
|
|
8016c06: b086 sub sp, #24
|
|
8016c08: af00 add r7, sp, #0
|
|
8016c0a: 60f8 str r0, [r7, #12]
|
|
8016c0c: 60b9 str r1, [r7, #8]
|
|
8016c0e: 607a str r2, [r7, #4]
|
|
8016c10: 603b str r3, [r7, #0]
|
|
BaseType_t xReturn;
|
|
|
|
configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
|
|
8016c12: 68fb ldr r3, [r7, #12]
|
|
8016c14: 2b01 cmp r3, #1
|
|
8016c16: d90b bls.n 8016c30 <xTaskGenericNotifyWait+0x2c>
|
|
__asm volatile
|
|
8016c18: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016c1c: f383 8811 msr BASEPRI, r3
|
|
8016c20: f3bf 8f6f isb sy
|
|
8016c24: f3bf 8f4f dsb sy
|
|
8016c28: 613b str r3, [r7, #16]
|
|
}
|
|
8016c2a: bf00 nop
|
|
8016c2c: bf00 nop
|
|
8016c2e: e7fd b.n 8016c2c <xTaskGenericNotifyWait+0x28>
|
|
|
|
taskENTER_CRITICAL();
|
|
8016c30: f001 f87e bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
/* Only block if a notification is not already pending. */
|
|
if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
|
|
8016c34: 4b31 ldr r3, [pc, #196] @ (8016cfc <xTaskGenericNotifyWait+0xf8>)
|
|
8016c36: 681a ldr r2, [r3, #0]
|
|
8016c38: 68fb ldr r3, [r7, #12]
|
|
8016c3a: 4413 add r3, r2
|
|
8016c3c: 33a8 adds r3, #168 @ 0xa8
|
|
8016c3e: 781b ldrb r3, [r3, #0]
|
|
8016c40: b2db uxtb r3, r3
|
|
8016c42: 2b02 cmp r3, #2
|
|
8016c44: d022 beq.n 8016c8c <xTaskGenericNotifyWait+0x88>
|
|
{
|
|
/* Clear bits in the task's notification value as bits may get
|
|
* set by the notifying task or interrupt. This can be used to
|
|
* clear the value to zero. */
|
|
pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry;
|
|
8016c46: 4b2d ldr r3, [pc, #180] @ (8016cfc <xTaskGenericNotifyWait+0xf8>)
|
|
8016c48: 681b ldr r3, [r3, #0]
|
|
8016c4a: 68fa ldr r2, [r7, #12]
|
|
8016c4c: 3228 adds r2, #40 @ 0x28
|
|
8016c4e: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
8016c52: 68ba ldr r2, [r7, #8]
|
|
8016c54: 43d2 mvns r2, r2
|
|
8016c56: 4011 ands r1, r2
|
|
8016c58: 68fa ldr r2, [r7, #12]
|
|
8016c5a: 3228 adds r2, #40 @ 0x28
|
|
8016c5c: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
|
|
/* Mark this task as waiting for a notification. */
|
|
pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
|
|
8016c60: 4b26 ldr r3, [pc, #152] @ (8016cfc <xTaskGenericNotifyWait+0xf8>)
|
|
8016c62: 681a ldr r2, [r3, #0]
|
|
8016c64: 68fb ldr r3, [r7, #12]
|
|
8016c66: 4413 add r3, r2
|
|
8016c68: 33a8 adds r3, #168 @ 0xa8
|
|
8016c6a: 2201 movs r2, #1
|
|
8016c6c: 701a strb r2, [r3, #0]
|
|
|
|
if( xTicksToWait > ( TickType_t ) 0 )
|
|
8016c6e: 6a3b ldr r3, [r7, #32]
|
|
8016c70: 2b00 cmp r3, #0
|
|
8016c72: d00b beq.n 8016c8c <xTaskGenericNotifyWait+0x88>
|
|
{
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
|
8016c74: 2101 movs r1, #1
|
|
8016c76: 6a38 ldr r0, [r7, #32]
|
|
8016c78: f000 fbd6 bl 8017428 <prvAddCurrentTaskToDelayedList>
|
|
|
|
/* All ports are written to allow a yield in a critical
|
|
* section (some will yield immediately, others wait until the
|
|
* critical section exits) - but it is not something that
|
|
* application code should ever do. */
|
|
portYIELD_WITHIN_API();
|
|
8016c7c: 4b20 ldr r3, [pc, #128] @ (8016d00 <xTaskGenericNotifyWait+0xfc>)
|
|
8016c7e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8016c82: 601a str r2, [r3, #0]
|
|
8016c84: f3bf 8f4f dsb sy
|
|
8016c88: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8016c8c: f001 f882 bl 8017d94 <vPortExitCritical>
|
|
|
|
taskENTER_CRITICAL();
|
|
8016c90: f001 f84e bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
traceTASK_NOTIFY_WAIT( uxIndexToWait );
|
|
|
|
if( pulNotificationValue != NULL )
|
|
8016c94: 683b ldr r3, [r7, #0]
|
|
8016c96: 2b00 cmp r3, #0
|
|
8016c98: d007 beq.n 8016caa <xTaskGenericNotifyWait+0xa6>
|
|
{
|
|
/* Output the current notification value, which may or may not
|
|
* have changed. */
|
|
*pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
|
|
8016c9a: 4b18 ldr r3, [pc, #96] @ (8016cfc <xTaskGenericNotifyWait+0xf8>)
|
|
8016c9c: 681b ldr r3, [r3, #0]
|
|
8016c9e: 68fa ldr r2, [r7, #12]
|
|
8016ca0: 3228 adds r2, #40 @ 0x28
|
|
8016ca2: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8016ca6: 683b ldr r3, [r7, #0]
|
|
8016ca8: 601a str r2, [r3, #0]
|
|
|
|
/* If ucNotifyValue is set then either the task never entered the
|
|
* blocked state (because a notification was already pending) or the
|
|
* task unblocked because of a notification. Otherwise the task
|
|
* unblocked because of a timeout. */
|
|
if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
|
|
8016caa: 4b14 ldr r3, [pc, #80] @ (8016cfc <xTaskGenericNotifyWait+0xf8>)
|
|
8016cac: 681a ldr r2, [r3, #0]
|
|
8016cae: 68fb ldr r3, [r7, #12]
|
|
8016cb0: 4413 add r3, r2
|
|
8016cb2: 33a8 adds r3, #168 @ 0xa8
|
|
8016cb4: 781b ldrb r3, [r3, #0]
|
|
8016cb6: b2db uxtb r3, r3
|
|
8016cb8: 2b02 cmp r3, #2
|
|
8016cba: d002 beq.n 8016cc2 <xTaskGenericNotifyWait+0xbe>
|
|
{
|
|
/* A notification was not received. */
|
|
xReturn = pdFALSE;
|
|
8016cbc: 2300 movs r3, #0
|
|
8016cbe: 617b str r3, [r7, #20]
|
|
8016cc0: e00e b.n 8016ce0 <xTaskGenericNotifyWait+0xdc>
|
|
}
|
|
else
|
|
{
|
|
/* A notification was already pending or a notification was
|
|
* received while the task was waiting. */
|
|
pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit;
|
|
8016cc2: 4b0e ldr r3, [pc, #56] @ (8016cfc <xTaskGenericNotifyWait+0xf8>)
|
|
8016cc4: 681b ldr r3, [r3, #0]
|
|
8016cc6: 68fa ldr r2, [r7, #12]
|
|
8016cc8: 3228 adds r2, #40 @ 0x28
|
|
8016cca: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
8016cce: 687a ldr r2, [r7, #4]
|
|
8016cd0: 43d2 mvns r2, r2
|
|
8016cd2: 4011 ands r1, r2
|
|
8016cd4: 68fa ldr r2, [r7, #12]
|
|
8016cd6: 3228 adds r2, #40 @ 0x28
|
|
8016cd8: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
xReturn = pdTRUE;
|
|
8016cdc: 2301 movs r3, #1
|
|
8016cde: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
|
|
8016ce0: 4b06 ldr r3, [pc, #24] @ (8016cfc <xTaskGenericNotifyWait+0xf8>)
|
|
8016ce2: 681a ldr r2, [r3, #0]
|
|
8016ce4: 68fb ldr r3, [r7, #12]
|
|
8016ce6: 4413 add r3, r2
|
|
8016ce8: 33a8 adds r3, #168 @ 0xa8
|
|
8016cea: 2200 movs r2, #0
|
|
8016cec: 701a strb r2, [r3, #0]
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8016cee: f001 f851 bl 8017d94 <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
8016cf2: 697b ldr r3, [r7, #20]
|
|
}
|
|
8016cf4: 4618 mov r0, r3
|
|
8016cf6: 3718 adds r7, #24
|
|
8016cf8: 46bd mov sp, r7
|
|
8016cfa: bd80 pop {r7, pc}
|
|
8016cfc: 20002168 .word 0x20002168
|
|
8016d00: e000ed04 .word 0xe000ed04
|
|
|
|
08016d04 <xTaskGenericNotify>:
|
|
BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
|
|
UBaseType_t uxIndexToNotify,
|
|
uint32_t ulValue,
|
|
eNotifyAction eAction,
|
|
uint32_t * pulPreviousNotificationValue )
|
|
{
|
|
8016d04: b580 push {r7, lr}
|
|
8016d06: b08e sub sp, #56 @ 0x38
|
|
8016d08: af00 add r7, sp, #0
|
|
8016d0a: 60f8 str r0, [r7, #12]
|
|
8016d0c: 60b9 str r1, [r7, #8]
|
|
8016d0e: 607a str r2, [r7, #4]
|
|
8016d10: 70fb strb r3, [r7, #3]
|
|
TCB_t * pxTCB;
|
|
BaseType_t xReturn = pdPASS;
|
|
8016d12: 2301 movs r3, #1
|
|
8016d14: 637b str r3, [r7, #52] @ 0x34
|
|
uint8_t ucOriginalNotifyState;
|
|
|
|
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
|
|
8016d16: 68bb ldr r3, [r7, #8]
|
|
8016d18: 2b01 cmp r3, #1
|
|
8016d1a: d90b bls.n 8016d34 <xTaskGenericNotify+0x30>
|
|
__asm volatile
|
|
8016d1c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016d20: f383 8811 msr BASEPRI, r3
|
|
8016d24: f3bf 8f6f isb sy
|
|
8016d28: f3bf 8f4f dsb sy
|
|
8016d2c: 623b str r3, [r7, #32]
|
|
}
|
|
8016d2e: bf00 nop
|
|
8016d30: bf00 nop
|
|
8016d32: e7fd b.n 8016d30 <xTaskGenericNotify+0x2c>
|
|
configASSERT( xTaskToNotify );
|
|
8016d34: 68fb ldr r3, [r7, #12]
|
|
8016d36: 2b00 cmp r3, #0
|
|
8016d38: d10b bne.n 8016d52 <xTaskGenericNotify+0x4e>
|
|
__asm volatile
|
|
8016d3a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016d3e: f383 8811 msr BASEPRI, r3
|
|
8016d42: f3bf 8f6f isb sy
|
|
8016d46: f3bf 8f4f dsb sy
|
|
8016d4a: 61fb str r3, [r7, #28]
|
|
}
|
|
8016d4c: bf00 nop
|
|
8016d4e: bf00 nop
|
|
8016d50: e7fd b.n 8016d4e <xTaskGenericNotify+0x4a>
|
|
pxTCB = xTaskToNotify;
|
|
8016d52: 68fb ldr r3, [r7, #12]
|
|
8016d54: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
taskENTER_CRITICAL();
|
|
8016d56: f000 ffeb bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
if( pulPreviousNotificationValue != NULL )
|
|
8016d5a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8016d5c: 2b00 cmp r3, #0
|
|
8016d5e: d006 beq.n 8016d6e <xTaskGenericNotify+0x6a>
|
|
{
|
|
*pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
|
|
8016d60: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016d62: 68ba ldr r2, [r7, #8]
|
|
8016d64: 3228 adds r2, #40 @ 0x28
|
|
8016d66: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8016d6a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8016d6c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
|
|
8016d6e: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8016d70: 68bb ldr r3, [r7, #8]
|
|
8016d72: 4413 add r3, r2
|
|
8016d74: 33a8 adds r3, #168 @ 0xa8
|
|
8016d76: 781b ldrb r3, [r3, #0]
|
|
8016d78: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
|
|
8016d7c: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8016d7e: 68bb ldr r3, [r7, #8]
|
|
8016d80: 4413 add r3, r2
|
|
8016d82: 33a8 adds r3, #168 @ 0xa8
|
|
8016d84: 2202 movs r2, #2
|
|
8016d86: 701a strb r2, [r3, #0]
|
|
|
|
switch( eAction )
|
|
8016d88: 78fb ldrb r3, [r7, #3]
|
|
8016d8a: 2b04 cmp r3, #4
|
|
8016d8c: d83b bhi.n 8016e06 <xTaskGenericNotify+0x102>
|
|
8016d8e: a201 add r2, pc, #4 @ (adr r2, 8016d94 <xTaskGenericNotify+0x90>)
|
|
8016d90: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8016d94: 08016e27 .word 0x08016e27
|
|
8016d98: 08016da9 .word 0x08016da9
|
|
8016d9c: 08016dc5 .word 0x08016dc5
|
|
8016da0: 08016ddd .word 0x08016ddd
|
|
8016da4: 08016deb .word 0x08016deb
|
|
{
|
|
case eSetBits:
|
|
pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
|
|
8016da8: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016daa: 68ba ldr r2, [r7, #8]
|
|
8016dac: 3228 adds r2, #40 @ 0x28
|
|
8016dae: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8016db2: 687b ldr r3, [r7, #4]
|
|
8016db4: ea42 0103 orr.w r1, r2, r3
|
|
8016db8: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016dba: 68ba ldr r2, [r7, #8]
|
|
8016dbc: 3228 adds r2, #40 @ 0x28
|
|
8016dbe: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
break;
|
|
8016dc2: e033 b.n 8016e2c <xTaskGenericNotify+0x128>
|
|
|
|
case eIncrement:
|
|
( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
|
|
8016dc4: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016dc6: 68ba ldr r2, [r7, #8]
|
|
8016dc8: 3228 adds r2, #40 @ 0x28
|
|
8016dca: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8016dce: 1c59 adds r1, r3, #1
|
|
8016dd0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016dd2: 68ba ldr r2, [r7, #8]
|
|
8016dd4: 3228 adds r2, #40 @ 0x28
|
|
8016dd6: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
break;
|
|
8016dda: e027 b.n 8016e2c <xTaskGenericNotify+0x128>
|
|
|
|
case eSetValueWithOverwrite:
|
|
pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
|
|
8016ddc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016dde: 68ba ldr r2, [r7, #8]
|
|
8016de0: 3228 adds r2, #40 @ 0x28
|
|
8016de2: 6879 ldr r1, [r7, #4]
|
|
8016de4: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
break;
|
|
8016de8: e020 b.n 8016e2c <xTaskGenericNotify+0x128>
|
|
|
|
case eSetValueWithoutOverwrite:
|
|
|
|
if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
|
|
8016dea: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
8016dee: 2b02 cmp r3, #2
|
|
8016df0: d006 beq.n 8016e00 <xTaskGenericNotify+0xfc>
|
|
{
|
|
pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
|
|
8016df2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016df4: 68ba ldr r2, [r7, #8]
|
|
8016df6: 3228 adds r2, #40 @ 0x28
|
|
8016df8: 6879 ldr r1, [r7, #4]
|
|
8016dfa: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
{
|
|
/* The value could not be written to the task. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
|
|
break;
|
|
8016dfe: e015 b.n 8016e2c <xTaskGenericNotify+0x128>
|
|
xReturn = pdFAIL;
|
|
8016e00: 2300 movs r3, #0
|
|
8016e02: 637b str r3, [r7, #52] @ 0x34
|
|
break;
|
|
8016e04: e012 b.n 8016e2c <xTaskGenericNotify+0x128>
|
|
default:
|
|
|
|
/* Should not get here if all enums are handled.
|
|
* Artificially force an assert by testing a value the
|
|
* compiler can't assume is const. */
|
|
configASSERT( xTickCount == ( TickType_t ) 0 );
|
|
8016e06: 4b4e ldr r3, [pc, #312] @ (8016f40 <xTaskGenericNotify+0x23c>)
|
|
8016e08: 681b ldr r3, [r3, #0]
|
|
8016e0a: 2b00 cmp r3, #0
|
|
8016e0c: d00d beq.n 8016e2a <xTaskGenericNotify+0x126>
|
|
__asm volatile
|
|
8016e0e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016e12: f383 8811 msr BASEPRI, r3
|
|
8016e16: f3bf 8f6f isb sy
|
|
8016e1a: f3bf 8f4f dsb sy
|
|
8016e1e: 61bb str r3, [r7, #24]
|
|
}
|
|
8016e20: bf00 nop
|
|
8016e22: bf00 nop
|
|
8016e24: e7fd b.n 8016e22 <xTaskGenericNotify+0x11e>
|
|
break;
|
|
8016e26: bf00 nop
|
|
8016e28: e000 b.n 8016e2c <xTaskGenericNotify+0x128>
|
|
|
|
break;
|
|
8016e2a: bf00 nop
|
|
|
|
traceTASK_NOTIFY( uxIndexToNotify );
|
|
|
|
/* If the task is in the blocked state specifically to wait for a
|
|
* notification then unblock it now. */
|
|
if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
|
|
8016e2c: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
8016e30: 2b01 cmp r3, #1
|
|
8016e32: d17d bne.n 8016f30 <xTaskGenericNotify+0x22c>
|
|
{
|
|
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
|
|
8016e34: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e36: 695b ldr r3, [r3, #20]
|
|
8016e38: 62bb str r3, [r7, #40] @ 0x28
|
|
8016e3a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e3c: 689b ldr r3, [r3, #8]
|
|
8016e3e: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8016e40: 68d2 ldr r2, [r2, #12]
|
|
8016e42: 609a str r2, [r3, #8]
|
|
8016e44: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e46: 68db ldr r3, [r3, #12]
|
|
8016e48: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8016e4a: 6892 ldr r2, [r2, #8]
|
|
8016e4c: 605a str r2, [r3, #4]
|
|
8016e4e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8016e50: 685a ldr r2, [r3, #4]
|
|
8016e52: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e54: 3304 adds r3, #4
|
|
8016e56: 429a cmp r2, r3
|
|
8016e58: d103 bne.n 8016e62 <xTaskGenericNotify+0x15e>
|
|
8016e5a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e5c: 68da ldr r2, [r3, #12]
|
|
8016e5e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8016e60: 605a str r2, [r3, #4]
|
|
8016e62: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e64: 2200 movs r2, #0
|
|
8016e66: 615a str r2, [r3, #20]
|
|
8016e68: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8016e6a: 681b ldr r3, [r3, #0]
|
|
8016e6c: 1e5a subs r2, r3, #1
|
|
8016e6e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8016e70: 601a str r2, [r3, #0]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
8016e72: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e74: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016e76: 4b33 ldr r3, [pc, #204] @ (8016f44 <xTaskGenericNotify+0x240>)
|
|
8016e78: 681b ldr r3, [r3, #0]
|
|
8016e7a: 429a cmp r2, r3
|
|
8016e7c: d903 bls.n 8016e86 <xTaskGenericNotify+0x182>
|
|
8016e7e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e80: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016e82: 4a30 ldr r2, [pc, #192] @ (8016f44 <xTaskGenericNotify+0x240>)
|
|
8016e84: 6013 str r3, [r2, #0]
|
|
8016e86: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e88: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016e8a: 492f ldr r1, [pc, #188] @ (8016f48 <xTaskGenericNotify+0x244>)
|
|
8016e8c: 4613 mov r3, r2
|
|
8016e8e: 009b lsls r3, r3, #2
|
|
8016e90: 4413 add r3, r2
|
|
8016e92: 009b lsls r3, r3, #2
|
|
8016e94: 440b add r3, r1
|
|
8016e96: 3304 adds r3, #4
|
|
8016e98: 681b ldr r3, [r3, #0]
|
|
8016e9a: 627b str r3, [r7, #36] @ 0x24
|
|
8016e9c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016e9e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8016ea0: 609a str r2, [r3, #8]
|
|
8016ea2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8016ea4: 689a ldr r2, [r3, #8]
|
|
8016ea6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016ea8: 60da str r2, [r3, #12]
|
|
8016eaa: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8016eac: 689b ldr r3, [r3, #8]
|
|
8016eae: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8016eb0: 3204 adds r2, #4
|
|
8016eb2: 605a str r2, [r3, #4]
|
|
8016eb4: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016eb6: 1d1a adds r2, r3, #4
|
|
8016eb8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8016eba: 609a str r2, [r3, #8]
|
|
8016ebc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016ebe: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016ec0: 4613 mov r3, r2
|
|
8016ec2: 009b lsls r3, r3, #2
|
|
8016ec4: 4413 add r3, r2
|
|
8016ec6: 009b lsls r3, r3, #2
|
|
8016ec8: 4a1f ldr r2, [pc, #124] @ (8016f48 <xTaskGenericNotify+0x244>)
|
|
8016eca: 441a add r2, r3
|
|
8016ecc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016ece: 615a str r2, [r3, #20]
|
|
8016ed0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016ed2: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016ed4: 491c ldr r1, [pc, #112] @ (8016f48 <xTaskGenericNotify+0x244>)
|
|
8016ed6: 4613 mov r3, r2
|
|
8016ed8: 009b lsls r3, r3, #2
|
|
8016eda: 4413 add r3, r2
|
|
8016edc: 009b lsls r3, r3, #2
|
|
8016ede: 440b add r3, r1
|
|
8016ee0: 681b ldr r3, [r3, #0]
|
|
8016ee2: 1c59 adds r1, r3, #1
|
|
8016ee4: 4818 ldr r0, [pc, #96] @ (8016f48 <xTaskGenericNotify+0x244>)
|
|
8016ee6: 4613 mov r3, r2
|
|
8016ee8: 009b lsls r3, r3, #2
|
|
8016eea: 4413 add r3, r2
|
|
8016eec: 009b lsls r3, r3, #2
|
|
8016eee: 4403 add r3, r0
|
|
8016ef0: 6019 str r1, [r3, #0]
|
|
|
|
/* The task should not have been on an event list. */
|
|
configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
|
|
8016ef2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016ef4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8016ef6: 2b00 cmp r3, #0
|
|
8016ef8: d00b beq.n 8016f12 <xTaskGenericNotify+0x20e>
|
|
__asm volatile
|
|
8016efa: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016efe: f383 8811 msr BASEPRI, r3
|
|
8016f02: f3bf 8f6f isb sy
|
|
8016f06: f3bf 8f4f dsb sy
|
|
8016f0a: 617b str r3, [r7, #20]
|
|
}
|
|
8016f0c: bf00 nop
|
|
8016f0e: bf00 nop
|
|
8016f10: e7fd b.n 8016f0e <xTaskGenericNotify+0x20a>
|
|
* earliest possible time. */
|
|
prvResetNextTaskUnblockTime();
|
|
}
|
|
#endif
|
|
|
|
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
8016f12: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8016f14: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8016f16: 4b0d ldr r3, [pc, #52] @ (8016f4c <xTaskGenericNotify+0x248>)
|
|
8016f18: 681b ldr r3, [r3, #0]
|
|
8016f1a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8016f1c: 429a cmp r2, r3
|
|
8016f1e: d907 bls.n 8016f30 <xTaskGenericNotify+0x22c>
|
|
{
|
|
/* The notified task has a priority above the currently
|
|
* executing task so a yield is required. */
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
8016f20: 4b0b ldr r3, [pc, #44] @ (8016f50 <xTaskGenericNotify+0x24c>)
|
|
8016f22: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8016f26: 601a str r2, [r3, #0]
|
|
8016f28: f3bf 8f4f dsb sy
|
|
8016f2c: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8016f30: f000 ff30 bl 8017d94 <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
8016f34: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
}
|
|
8016f36: 4618 mov r0, r3
|
|
8016f38: 3738 adds r7, #56 @ 0x38
|
|
8016f3a: 46bd mov sp, r7
|
|
8016f3c: bd80 pop {r7, pc}
|
|
8016f3e: bf00 nop
|
|
8016f40: 20002640 .word 0x20002640
|
|
8016f44: 20002644 .word 0x20002644
|
|
8016f48: 2000216c .word 0x2000216c
|
|
8016f4c: 20002168 .word 0x20002168
|
|
8016f50: e000ed04 .word 0xe000ed04
|
|
|
|
08016f54 <xTaskGenericNotifyFromISR>:
|
|
UBaseType_t uxIndexToNotify,
|
|
uint32_t ulValue,
|
|
eNotifyAction eAction,
|
|
uint32_t * pulPreviousNotificationValue,
|
|
BaseType_t * pxHigherPriorityTaskWoken )
|
|
{
|
|
8016f54: b580 push {r7, lr}
|
|
8016f56: b092 sub sp, #72 @ 0x48
|
|
8016f58: af00 add r7, sp, #0
|
|
8016f5a: 60f8 str r0, [r7, #12]
|
|
8016f5c: 60b9 str r1, [r7, #8]
|
|
8016f5e: 607a str r2, [r7, #4]
|
|
8016f60: 70fb strb r3, [r7, #3]
|
|
TCB_t * pxTCB;
|
|
uint8_t ucOriginalNotifyState;
|
|
BaseType_t xReturn = pdPASS;
|
|
8016f62: 2301 movs r3, #1
|
|
8016f64: 647b str r3, [r7, #68] @ 0x44
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
|
|
configASSERT( xTaskToNotify );
|
|
8016f66: 68fb ldr r3, [r7, #12]
|
|
8016f68: 2b00 cmp r3, #0
|
|
8016f6a: d10b bne.n 8016f84 <xTaskGenericNotifyFromISR+0x30>
|
|
__asm volatile
|
|
8016f6c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016f70: f383 8811 msr BASEPRI, r3
|
|
8016f74: f3bf 8f6f isb sy
|
|
8016f78: f3bf 8f4f dsb sy
|
|
8016f7c: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
8016f7e: bf00 nop
|
|
8016f80: bf00 nop
|
|
8016f82: e7fd b.n 8016f80 <xTaskGenericNotifyFromISR+0x2c>
|
|
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
|
|
8016f84: 68bb ldr r3, [r7, #8]
|
|
8016f86: 2b01 cmp r3, #1
|
|
8016f88: d90b bls.n 8016fa2 <xTaskGenericNotifyFromISR+0x4e>
|
|
__asm volatile
|
|
8016f8a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016f8e: f383 8811 msr BASEPRI, r3
|
|
8016f92: f3bf 8f6f isb sy
|
|
8016f96: f3bf 8f4f dsb sy
|
|
8016f9a: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
8016f9c: bf00 nop
|
|
8016f9e: bf00 nop
|
|
8016fa0: e7fd b.n 8016f9e <xTaskGenericNotifyFromISR+0x4a>
|
|
* below the maximum system call interrupt priority. FreeRTOS maintains a
|
|
* separate interrupt safe API to ensure interrupt entry is as fast and as
|
|
* simple as possible. More information (albeit Cortex-M specific) is
|
|
* provided on the following link:
|
|
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
8016fa2: f000 ffab bl 8017efc <vPortValidateInterruptPriority>
|
|
|
|
pxTCB = xTaskToNotify;
|
|
8016fa6: 68fb ldr r3, [r7, #12]
|
|
8016fa8: 643b str r3, [r7, #64] @ 0x40
|
|
__asm volatile
|
|
8016faa: f3ef 8211 mrs r2, BASEPRI
|
|
8016fae: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8016fb2: f383 8811 msr BASEPRI, r3
|
|
8016fb6: f3bf 8f6f isb sy
|
|
8016fba: f3bf 8f4f dsb sy
|
|
8016fbe: 623a str r2, [r7, #32]
|
|
8016fc0: 61fb str r3, [r7, #28]
|
|
return ulOriginalBASEPRI;
|
|
8016fc2: 6a3b ldr r3, [r7, #32]
|
|
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
8016fc4: 63fb str r3, [r7, #60] @ 0x3c
|
|
{
|
|
if( pulPreviousNotificationValue != NULL )
|
|
8016fc6: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8016fc8: 2b00 cmp r3, #0
|
|
8016fca: d006 beq.n 8016fda <xTaskGenericNotifyFromISR+0x86>
|
|
{
|
|
*pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
|
|
8016fcc: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8016fce: 68ba ldr r2, [r7, #8]
|
|
8016fd0: 3228 adds r2, #40 @ 0x28
|
|
8016fd2: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8016fd6: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8016fd8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
|
|
8016fda: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8016fdc: 68bb ldr r3, [r7, #8]
|
|
8016fde: 4413 add r3, r2
|
|
8016fe0: 33a8 adds r3, #168 @ 0xa8
|
|
8016fe2: 781b ldrb r3, [r3, #0]
|
|
8016fe4: f887 303b strb.w r3, [r7, #59] @ 0x3b
|
|
pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
|
|
8016fe8: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8016fea: 68bb ldr r3, [r7, #8]
|
|
8016fec: 4413 add r3, r2
|
|
8016fee: 33a8 adds r3, #168 @ 0xa8
|
|
8016ff0: 2202 movs r2, #2
|
|
8016ff2: 701a strb r2, [r3, #0]
|
|
|
|
switch( eAction )
|
|
8016ff4: 78fb ldrb r3, [r7, #3]
|
|
8016ff6: 2b04 cmp r3, #4
|
|
8016ff8: d83b bhi.n 8017072 <xTaskGenericNotifyFromISR+0x11e>
|
|
8016ffa: a201 add r2, pc, #4 @ (adr r2, 8017000 <xTaskGenericNotifyFromISR+0xac>)
|
|
8016ffc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8017000: 08017093 .word 0x08017093
|
|
8017004: 08017015 .word 0x08017015
|
|
8017008: 08017031 .word 0x08017031
|
|
801700c: 08017049 .word 0x08017049
|
|
8017010: 08017057 .word 0x08017057
|
|
{
|
|
case eSetBits:
|
|
pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
|
|
8017014: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017016: 68ba ldr r2, [r7, #8]
|
|
8017018: 3228 adds r2, #40 @ 0x28
|
|
801701a: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
801701e: 687b ldr r3, [r7, #4]
|
|
8017020: ea42 0103 orr.w r1, r2, r3
|
|
8017024: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017026: 68ba ldr r2, [r7, #8]
|
|
8017028: 3228 adds r2, #40 @ 0x28
|
|
801702a: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
break;
|
|
801702e: e033 b.n 8017098 <xTaskGenericNotifyFromISR+0x144>
|
|
|
|
case eIncrement:
|
|
( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
|
|
8017030: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017032: 68ba ldr r2, [r7, #8]
|
|
8017034: 3228 adds r2, #40 @ 0x28
|
|
8017036: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
801703a: 1c59 adds r1, r3, #1
|
|
801703c: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
801703e: 68ba ldr r2, [r7, #8]
|
|
8017040: 3228 adds r2, #40 @ 0x28
|
|
8017042: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
break;
|
|
8017046: e027 b.n 8017098 <xTaskGenericNotifyFromISR+0x144>
|
|
|
|
case eSetValueWithOverwrite:
|
|
pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
|
|
8017048: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
801704a: 68ba ldr r2, [r7, #8]
|
|
801704c: 3228 adds r2, #40 @ 0x28
|
|
801704e: 6879 ldr r1, [r7, #4]
|
|
8017050: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
break;
|
|
8017054: e020 b.n 8017098 <xTaskGenericNotifyFromISR+0x144>
|
|
|
|
case eSetValueWithoutOverwrite:
|
|
|
|
if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
|
|
8017056: f897 303b ldrb.w r3, [r7, #59] @ 0x3b
|
|
801705a: 2b02 cmp r3, #2
|
|
801705c: d006 beq.n 801706c <xTaskGenericNotifyFromISR+0x118>
|
|
{
|
|
pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
|
|
801705e: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017060: 68ba ldr r2, [r7, #8]
|
|
8017062: 3228 adds r2, #40 @ 0x28
|
|
8017064: 6879 ldr r1, [r7, #4]
|
|
8017066: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
{
|
|
/* The value could not be written to the task. */
|
|
xReturn = pdFAIL;
|
|
}
|
|
|
|
break;
|
|
801706a: e015 b.n 8017098 <xTaskGenericNotifyFromISR+0x144>
|
|
xReturn = pdFAIL;
|
|
801706c: 2300 movs r3, #0
|
|
801706e: 647b str r3, [r7, #68] @ 0x44
|
|
break;
|
|
8017070: e012 b.n 8017098 <xTaskGenericNotifyFromISR+0x144>
|
|
default:
|
|
|
|
/* Should not get here if all enums are handled.
|
|
* Artificially force an assert by testing a value the
|
|
* compiler can't assume is const. */
|
|
configASSERT( xTickCount == ( TickType_t ) 0 );
|
|
8017072: 4b61 ldr r3, [pc, #388] @ (80171f8 <xTaskGenericNotifyFromISR+0x2a4>)
|
|
8017074: 681b ldr r3, [r3, #0]
|
|
8017076: 2b00 cmp r3, #0
|
|
8017078: d00d beq.n 8017096 <xTaskGenericNotifyFromISR+0x142>
|
|
__asm volatile
|
|
801707a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801707e: f383 8811 msr BASEPRI, r3
|
|
8017082: f3bf 8f6f isb sy
|
|
8017086: f3bf 8f4f dsb sy
|
|
801708a: 61bb str r3, [r7, #24]
|
|
}
|
|
801708c: bf00 nop
|
|
801708e: bf00 nop
|
|
8017090: e7fd b.n 801708e <xTaskGenericNotifyFromISR+0x13a>
|
|
break;
|
|
8017092: bf00 nop
|
|
8017094: e000 b.n 8017098 <xTaskGenericNotifyFromISR+0x144>
|
|
break;
|
|
8017096: bf00 nop
|
|
|
|
traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify );
|
|
|
|
/* If the task is in the blocked state specifically to wait for a
|
|
* notification then unblock it now. */
|
|
if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
|
|
8017098: f897 303b ldrb.w r3, [r7, #59] @ 0x3b
|
|
801709c: 2b01 cmp r3, #1
|
|
801709e: f040 80a0 bne.w 80171e2 <xTaskGenericNotifyFromISR+0x28e>
|
|
{
|
|
/* The task should not have been on an event list. */
|
|
configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
|
|
80170a2: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80170a4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80170a6: 2b00 cmp r3, #0
|
|
80170a8: d00b beq.n 80170c2 <xTaskGenericNotifyFromISR+0x16e>
|
|
__asm volatile
|
|
80170aa: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80170ae: f383 8811 msr BASEPRI, r3
|
|
80170b2: f3bf 8f6f isb sy
|
|
80170b6: f3bf 8f4f dsb sy
|
|
80170ba: 617b str r3, [r7, #20]
|
|
}
|
|
80170bc: bf00 nop
|
|
80170be: bf00 nop
|
|
80170c0: e7fd b.n 80170be <xTaskGenericNotifyFromISR+0x16a>
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
|
|
80170c2: 4b4e ldr r3, [pc, #312] @ (80171fc <xTaskGenericNotifyFromISR+0x2a8>)
|
|
80170c4: 681b ldr r3, [r3, #0]
|
|
80170c6: 2b00 cmp r3, #0
|
|
80170c8: d15f bne.n 801718a <xTaskGenericNotifyFromISR+0x236>
|
|
{
|
|
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
|
|
80170ca: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80170cc: 695b ldr r3, [r3, #20]
|
|
80170ce: 633b str r3, [r7, #48] @ 0x30
|
|
80170d0: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80170d2: 689b ldr r3, [r3, #8]
|
|
80170d4: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
80170d6: 68d2 ldr r2, [r2, #12]
|
|
80170d8: 609a str r2, [r3, #8]
|
|
80170da: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80170dc: 68db ldr r3, [r3, #12]
|
|
80170de: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
80170e0: 6892 ldr r2, [r2, #8]
|
|
80170e2: 605a str r2, [r3, #4]
|
|
80170e4: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80170e6: 685a ldr r2, [r3, #4]
|
|
80170e8: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80170ea: 3304 adds r3, #4
|
|
80170ec: 429a cmp r2, r3
|
|
80170ee: d103 bne.n 80170f8 <xTaskGenericNotifyFromISR+0x1a4>
|
|
80170f0: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80170f2: 68da ldr r2, [r3, #12]
|
|
80170f4: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80170f6: 605a str r2, [r3, #4]
|
|
80170f8: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80170fa: 2200 movs r2, #0
|
|
80170fc: 615a str r2, [r3, #20]
|
|
80170fe: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8017100: 681b ldr r3, [r3, #0]
|
|
8017102: 1e5a subs r2, r3, #1
|
|
8017104: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8017106: 601a str r2, [r3, #0]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
8017108: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
801710a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
801710c: 4b3c ldr r3, [pc, #240] @ (8017200 <xTaskGenericNotifyFromISR+0x2ac>)
|
|
801710e: 681b ldr r3, [r3, #0]
|
|
8017110: 429a cmp r2, r3
|
|
8017112: d903 bls.n 801711c <xTaskGenericNotifyFromISR+0x1c8>
|
|
8017114: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017116: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8017118: 4a39 ldr r2, [pc, #228] @ (8017200 <xTaskGenericNotifyFromISR+0x2ac>)
|
|
801711a: 6013 str r3, [r2, #0]
|
|
801711c: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
801711e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8017120: 4938 ldr r1, [pc, #224] @ (8017204 <xTaskGenericNotifyFromISR+0x2b0>)
|
|
8017122: 4613 mov r3, r2
|
|
8017124: 009b lsls r3, r3, #2
|
|
8017126: 4413 add r3, r2
|
|
8017128: 009b lsls r3, r3, #2
|
|
801712a: 440b add r3, r1
|
|
801712c: 3304 adds r3, #4
|
|
801712e: 681b ldr r3, [r3, #0]
|
|
8017130: 62fb str r3, [r7, #44] @ 0x2c
|
|
8017132: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017134: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8017136: 609a str r2, [r3, #8]
|
|
8017138: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
801713a: 689a ldr r2, [r3, #8]
|
|
801713c: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
801713e: 60da str r2, [r3, #12]
|
|
8017140: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8017142: 689b ldr r3, [r3, #8]
|
|
8017144: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8017146: 3204 adds r2, #4
|
|
8017148: 605a str r2, [r3, #4]
|
|
801714a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
801714c: 1d1a adds r2, r3, #4
|
|
801714e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8017150: 609a str r2, [r3, #8]
|
|
8017152: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017154: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8017156: 4613 mov r3, r2
|
|
8017158: 009b lsls r3, r3, #2
|
|
801715a: 4413 add r3, r2
|
|
801715c: 009b lsls r3, r3, #2
|
|
801715e: 4a29 ldr r2, [pc, #164] @ (8017204 <xTaskGenericNotifyFromISR+0x2b0>)
|
|
8017160: 441a add r2, r3
|
|
8017162: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017164: 615a str r2, [r3, #20]
|
|
8017166: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017168: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
801716a: 4926 ldr r1, [pc, #152] @ (8017204 <xTaskGenericNotifyFromISR+0x2b0>)
|
|
801716c: 4613 mov r3, r2
|
|
801716e: 009b lsls r3, r3, #2
|
|
8017170: 4413 add r3, r2
|
|
8017172: 009b lsls r3, r3, #2
|
|
8017174: 440b add r3, r1
|
|
8017176: 681b ldr r3, [r3, #0]
|
|
8017178: 1c59 adds r1, r3, #1
|
|
801717a: 4822 ldr r0, [pc, #136] @ (8017204 <xTaskGenericNotifyFromISR+0x2b0>)
|
|
801717c: 4613 mov r3, r2
|
|
801717e: 009b lsls r3, r3, #2
|
|
8017180: 4413 add r3, r2
|
|
8017182: 009b lsls r3, r3, #2
|
|
8017184: 4403 add r3, r0
|
|
8017186: 6019 str r1, [r3, #0]
|
|
8017188: e01b b.n 80171c2 <xTaskGenericNotifyFromISR+0x26e>
|
|
}
|
|
else
|
|
{
|
|
/* The delayed and ready lists cannot be accessed, so hold
|
|
* this task pending until the scheduler is resumed. */
|
|
listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
|
|
801718a: 4b1f ldr r3, [pc, #124] @ (8017208 <xTaskGenericNotifyFromISR+0x2b4>)
|
|
801718c: 685b ldr r3, [r3, #4]
|
|
801718e: 637b str r3, [r7, #52] @ 0x34
|
|
8017190: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8017192: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
8017194: 61da str r2, [r3, #28]
|
|
8017196: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8017198: 689a ldr r2, [r3, #8]
|
|
801719a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
801719c: 621a str r2, [r3, #32]
|
|
801719e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80171a0: 689b ldr r3, [r3, #8]
|
|
80171a2: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
80171a4: 3218 adds r2, #24
|
|
80171a6: 605a str r2, [r3, #4]
|
|
80171a8: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80171aa: f103 0218 add.w r2, r3, #24
|
|
80171ae: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80171b0: 609a str r2, [r3, #8]
|
|
80171b2: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80171b4: 4a14 ldr r2, [pc, #80] @ (8017208 <xTaskGenericNotifyFromISR+0x2b4>)
|
|
80171b6: 629a str r2, [r3, #40] @ 0x28
|
|
80171b8: 4b13 ldr r3, [pc, #76] @ (8017208 <xTaskGenericNotifyFromISR+0x2b4>)
|
|
80171ba: 681b ldr r3, [r3, #0]
|
|
80171bc: 3301 adds r3, #1
|
|
80171be: 4a12 ldr r2, [pc, #72] @ (8017208 <xTaskGenericNotifyFromISR+0x2b4>)
|
|
80171c0: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
80171c2: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80171c4: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80171c6: 4b11 ldr r3, [pc, #68] @ (801720c <xTaskGenericNotifyFromISR+0x2b8>)
|
|
80171c8: 681b ldr r3, [r3, #0]
|
|
80171ca: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80171cc: 429a cmp r2, r3
|
|
80171ce: d908 bls.n 80171e2 <xTaskGenericNotifyFromISR+0x28e>
|
|
{
|
|
/* The notified task has a priority above the currently
|
|
* executing task so a yield is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
80171d0: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80171d2: 2b00 cmp r3, #0
|
|
80171d4: d002 beq.n 80171dc <xTaskGenericNotifyFromISR+0x288>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
80171d6: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80171d8: 2201 movs r2, #1
|
|
80171da: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Mark that a yield is pending in case the user is not
|
|
* using the "xHigherPriorityTaskWoken" parameter to an ISR
|
|
* safe FreeRTOS function. */
|
|
xYieldPending = pdTRUE;
|
|
80171dc: 4b0c ldr r3, [pc, #48] @ (8017210 <xTaskGenericNotifyFromISR+0x2bc>)
|
|
80171de: 2201 movs r2, #1
|
|
80171e0: 601a str r2, [r3, #0]
|
|
80171e2: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80171e4: 613b str r3, [r7, #16]
|
|
__asm volatile
|
|
80171e6: 693b ldr r3, [r7, #16]
|
|
80171e8: f383 8811 msr BASEPRI, r3
|
|
}
|
|
80171ec: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
80171ee: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
}
|
|
80171f0: 4618 mov r0, r3
|
|
80171f2: 3748 adds r7, #72 @ 0x48
|
|
80171f4: 46bd mov sp, r7
|
|
80171f6: bd80 pop {r7, pc}
|
|
80171f8: 20002640 .word 0x20002640
|
|
80171fc: 20002664 .word 0x20002664
|
|
8017200: 20002644 .word 0x20002644
|
|
8017204: 2000216c .word 0x2000216c
|
|
8017208: 200025fc .word 0x200025fc
|
|
801720c: 20002168 .word 0x20002168
|
|
8017210: 20002650 .word 0x20002650
|
|
|
|
08017214 <vTaskGenericNotifyGiveFromISR>:
|
|
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
|
|
|
|
void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
|
|
UBaseType_t uxIndexToNotify,
|
|
BaseType_t * pxHigherPriorityTaskWoken )
|
|
{
|
|
8017214: b580 push {r7, lr}
|
|
8017216: b090 sub sp, #64 @ 0x40
|
|
8017218: af00 add r7, sp, #0
|
|
801721a: 60f8 str r0, [r7, #12]
|
|
801721c: 60b9 str r1, [r7, #8]
|
|
801721e: 607a str r2, [r7, #4]
|
|
TCB_t * pxTCB;
|
|
uint8_t ucOriginalNotifyState;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
|
|
configASSERT( xTaskToNotify );
|
|
8017220: 68fb ldr r3, [r7, #12]
|
|
8017222: 2b00 cmp r3, #0
|
|
8017224: d10b bne.n 801723e <vTaskGenericNotifyGiveFromISR+0x2a>
|
|
__asm volatile
|
|
8017226: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801722a: f383 8811 msr BASEPRI, r3
|
|
801722e: f3bf 8f6f isb sy
|
|
8017232: f3bf 8f4f dsb sy
|
|
8017236: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
8017238: bf00 nop
|
|
801723a: bf00 nop
|
|
801723c: e7fd b.n 801723a <vTaskGenericNotifyGiveFromISR+0x26>
|
|
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
|
|
801723e: 68bb ldr r3, [r7, #8]
|
|
8017240: 2b01 cmp r3, #1
|
|
8017242: d90b bls.n 801725c <vTaskGenericNotifyGiveFromISR+0x48>
|
|
__asm volatile
|
|
8017244: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017248: f383 8811 msr BASEPRI, r3
|
|
801724c: f3bf 8f6f isb sy
|
|
8017250: f3bf 8f4f dsb sy
|
|
8017254: 623b str r3, [r7, #32]
|
|
}
|
|
8017256: bf00 nop
|
|
8017258: bf00 nop
|
|
801725a: e7fd b.n 8017258 <vTaskGenericNotifyGiveFromISR+0x44>
|
|
* below the maximum system call interrupt priority. FreeRTOS maintains a
|
|
* separate interrupt safe API to ensure interrupt entry is as fast and as
|
|
* simple as possible. More information (albeit Cortex-M specific) is
|
|
* provided on the following link:
|
|
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
801725c: f000 fe4e bl 8017efc <vPortValidateInterruptPriority>
|
|
|
|
pxTCB = xTaskToNotify;
|
|
8017260: 68fb ldr r3, [r7, #12]
|
|
8017262: 63fb str r3, [r7, #60] @ 0x3c
|
|
__asm volatile
|
|
8017264: f3ef 8211 mrs r2, BASEPRI
|
|
8017268: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801726c: f383 8811 msr BASEPRI, r3
|
|
8017270: f3bf 8f6f isb sy
|
|
8017274: f3bf 8f4f dsb sy
|
|
8017278: 61fa str r2, [r7, #28]
|
|
801727a: 61bb str r3, [r7, #24]
|
|
return ulOriginalBASEPRI;
|
|
801727c: 69fb ldr r3, [r7, #28]
|
|
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
801727e: 63bb str r3, [r7, #56] @ 0x38
|
|
{
|
|
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
|
|
8017280: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
8017282: 68bb ldr r3, [r7, #8]
|
|
8017284: 4413 add r3, r2
|
|
8017286: 33a8 adds r3, #168 @ 0xa8
|
|
8017288: 781b ldrb r3, [r3, #0]
|
|
801728a: f887 3037 strb.w r3, [r7, #55] @ 0x37
|
|
pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
|
|
801728e: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
8017290: 68bb ldr r3, [r7, #8]
|
|
8017292: 4413 add r3, r2
|
|
8017294: 33a8 adds r3, #168 @ 0xa8
|
|
8017296: 2202 movs r2, #2
|
|
8017298: 701a strb r2, [r3, #0]
|
|
|
|
/* 'Giving' is equivalent to incrementing a count in a counting
|
|
* semaphore. */
|
|
( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
|
|
801729a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
801729c: 68ba ldr r2, [r7, #8]
|
|
801729e: 3228 adds r2, #40 @ 0x28
|
|
80172a0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80172a4: 1c59 adds r1, r3, #1
|
|
80172a6: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80172a8: 68ba ldr r2, [r7, #8]
|
|
80172aa: 3228 adds r2, #40 @ 0x28
|
|
80172ac: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
|
|
traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify );
|
|
|
|
/* If the task is in the blocked state specifically to wait for a
|
|
* notification then unblock it now. */
|
|
if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
|
|
80172b0: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
|
|
80172b4: 2b01 cmp r3, #1
|
|
80172b6: f040 80a0 bne.w 80173fa <vTaskGenericNotifyGiveFromISR+0x1e6>
|
|
{
|
|
/* The task should not have been on an event list. */
|
|
configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
|
|
80172ba: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80172bc: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80172be: 2b00 cmp r3, #0
|
|
80172c0: d00b beq.n 80172da <vTaskGenericNotifyGiveFromISR+0xc6>
|
|
__asm volatile
|
|
80172c2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80172c6: f383 8811 msr BASEPRI, r3
|
|
80172ca: f3bf 8f6f isb sy
|
|
80172ce: f3bf 8f4f dsb sy
|
|
80172d2: 617b str r3, [r7, #20]
|
|
}
|
|
80172d4: bf00 nop
|
|
80172d6: bf00 nop
|
|
80172d8: e7fd b.n 80172d6 <vTaskGenericNotifyGiveFromISR+0xc2>
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
|
|
80172da: 4b4d ldr r3, [pc, #308] @ (8017410 <vTaskGenericNotifyGiveFromISR+0x1fc>)
|
|
80172dc: 681b ldr r3, [r3, #0]
|
|
80172de: 2b00 cmp r3, #0
|
|
80172e0: d15f bne.n 80173a2 <vTaskGenericNotifyGiveFromISR+0x18e>
|
|
{
|
|
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
|
|
80172e2: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80172e4: 695b ldr r3, [r3, #20]
|
|
80172e6: 62fb str r3, [r7, #44] @ 0x2c
|
|
80172e8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80172ea: 689b ldr r3, [r3, #8]
|
|
80172ec: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
80172ee: 68d2 ldr r2, [r2, #12]
|
|
80172f0: 609a str r2, [r3, #8]
|
|
80172f2: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80172f4: 68db ldr r3, [r3, #12]
|
|
80172f6: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
80172f8: 6892 ldr r2, [r2, #8]
|
|
80172fa: 605a str r2, [r3, #4]
|
|
80172fc: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80172fe: 685a ldr r2, [r3, #4]
|
|
8017300: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8017302: 3304 adds r3, #4
|
|
8017304: 429a cmp r2, r3
|
|
8017306: d103 bne.n 8017310 <vTaskGenericNotifyGiveFromISR+0xfc>
|
|
8017308: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
801730a: 68da ldr r2, [r3, #12]
|
|
801730c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
801730e: 605a str r2, [r3, #4]
|
|
8017310: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8017312: 2200 movs r2, #0
|
|
8017314: 615a str r2, [r3, #20]
|
|
8017316: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8017318: 681b ldr r3, [r3, #0]
|
|
801731a: 1e5a subs r2, r3, #1
|
|
801731c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
801731e: 601a str r2, [r3, #0]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
8017320: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8017322: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8017324: 4b3b ldr r3, [pc, #236] @ (8017414 <vTaskGenericNotifyGiveFromISR+0x200>)
|
|
8017326: 681b ldr r3, [r3, #0]
|
|
8017328: 429a cmp r2, r3
|
|
801732a: d903 bls.n 8017334 <vTaskGenericNotifyGiveFromISR+0x120>
|
|
801732c: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
801732e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8017330: 4a38 ldr r2, [pc, #224] @ (8017414 <vTaskGenericNotifyGiveFromISR+0x200>)
|
|
8017332: 6013 str r3, [r2, #0]
|
|
8017334: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8017336: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8017338: 4937 ldr r1, [pc, #220] @ (8017418 <vTaskGenericNotifyGiveFromISR+0x204>)
|
|
801733a: 4613 mov r3, r2
|
|
801733c: 009b lsls r3, r3, #2
|
|
801733e: 4413 add r3, r2
|
|
8017340: 009b lsls r3, r3, #2
|
|
8017342: 440b add r3, r1
|
|
8017344: 3304 adds r3, #4
|
|
8017346: 681b ldr r3, [r3, #0]
|
|
8017348: 62bb str r3, [r7, #40] @ 0x28
|
|
801734a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
801734c: 6aba ldr r2, [r7, #40] @ 0x28
|
|
801734e: 609a str r2, [r3, #8]
|
|
8017350: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8017352: 689a ldr r2, [r3, #8]
|
|
8017354: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8017356: 60da str r2, [r3, #12]
|
|
8017358: 6abb ldr r3, [r7, #40] @ 0x28
|
|
801735a: 689b ldr r3, [r3, #8]
|
|
801735c: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
801735e: 3204 adds r2, #4
|
|
8017360: 605a str r2, [r3, #4]
|
|
8017362: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8017364: 1d1a adds r2, r3, #4
|
|
8017366: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8017368: 609a str r2, [r3, #8]
|
|
801736a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
801736c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
801736e: 4613 mov r3, r2
|
|
8017370: 009b lsls r3, r3, #2
|
|
8017372: 4413 add r3, r2
|
|
8017374: 009b lsls r3, r3, #2
|
|
8017376: 4a28 ldr r2, [pc, #160] @ (8017418 <vTaskGenericNotifyGiveFromISR+0x204>)
|
|
8017378: 441a add r2, r3
|
|
801737a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
801737c: 615a str r2, [r3, #20]
|
|
801737e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8017380: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8017382: 4925 ldr r1, [pc, #148] @ (8017418 <vTaskGenericNotifyGiveFromISR+0x204>)
|
|
8017384: 4613 mov r3, r2
|
|
8017386: 009b lsls r3, r3, #2
|
|
8017388: 4413 add r3, r2
|
|
801738a: 009b lsls r3, r3, #2
|
|
801738c: 440b add r3, r1
|
|
801738e: 681b ldr r3, [r3, #0]
|
|
8017390: 1c59 adds r1, r3, #1
|
|
8017392: 4821 ldr r0, [pc, #132] @ (8017418 <vTaskGenericNotifyGiveFromISR+0x204>)
|
|
8017394: 4613 mov r3, r2
|
|
8017396: 009b lsls r3, r3, #2
|
|
8017398: 4413 add r3, r2
|
|
801739a: 009b lsls r3, r3, #2
|
|
801739c: 4403 add r3, r0
|
|
801739e: 6019 str r1, [r3, #0]
|
|
80173a0: e01b b.n 80173da <vTaskGenericNotifyGiveFromISR+0x1c6>
|
|
}
|
|
else
|
|
{
|
|
/* The delayed and ready lists cannot be accessed, so hold
|
|
* this task pending until the scheduler is resumed. */
|
|
listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
|
|
80173a2: 4b1e ldr r3, [pc, #120] @ (801741c <vTaskGenericNotifyGiveFromISR+0x208>)
|
|
80173a4: 685b ldr r3, [r3, #4]
|
|
80173a6: 633b str r3, [r7, #48] @ 0x30
|
|
80173a8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80173aa: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80173ac: 61da str r2, [r3, #28]
|
|
80173ae: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80173b0: 689a ldr r2, [r3, #8]
|
|
80173b2: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80173b4: 621a str r2, [r3, #32]
|
|
80173b6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80173b8: 689b ldr r3, [r3, #8]
|
|
80173ba: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
80173bc: 3218 adds r2, #24
|
|
80173be: 605a str r2, [r3, #4]
|
|
80173c0: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80173c2: f103 0218 add.w r2, r3, #24
|
|
80173c6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80173c8: 609a str r2, [r3, #8]
|
|
80173ca: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80173cc: 4a13 ldr r2, [pc, #76] @ (801741c <vTaskGenericNotifyGiveFromISR+0x208>)
|
|
80173ce: 629a str r2, [r3, #40] @ 0x28
|
|
80173d0: 4b12 ldr r3, [pc, #72] @ (801741c <vTaskGenericNotifyGiveFromISR+0x208>)
|
|
80173d2: 681b ldr r3, [r3, #0]
|
|
80173d4: 3301 adds r3, #1
|
|
80173d6: 4a11 ldr r2, [pc, #68] @ (801741c <vTaskGenericNotifyGiveFromISR+0x208>)
|
|
80173d8: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
80173da: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80173dc: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80173de: 4b10 ldr r3, [pc, #64] @ (8017420 <vTaskGenericNotifyGiveFromISR+0x20c>)
|
|
80173e0: 681b ldr r3, [r3, #0]
|
|
80173e2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80173e4: 429a cmp r2, r3
|
|
80173e6: d908 bls.n 80173fa <vTaskGenericNotifyGiveFromISR+0x1e6>
|
|
{
|
|
/* The notified task has a priority above the currently
|
|
* executing task so a yield is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
80173e8: 687b ldr r3, [r7, #4]
|
|
80173ea: 2b00 cmp r3, #0
|
|
80173ec: d002 beq.n 80173f4 <vTaskGenericNotifyGiveFromISR+0x1e0>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
80173ee: 687b ldr r3, [r7, #4]
|
|
80173f0: 2201 movs r2, #1
|
|
80173f2: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Mark that a yield is pending in case the user is not
|
|
* using the "xHigherPriorityTaskWoken" parameter in an ISR
|
|
* safe FreeRTOS function. */
|
|
xYieldPending = pdTRUE;
|
|
80173f4: 4b0b ldr r3, [pc, #44] @ (8017424 <vTaskGenericNotifyGiveFromISR+0x210>)
|
|
80173f6: 2201 movs r2, #1
|
|
80173f8: 601a str r2, [r3, #0]
|
|
80173fa: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80173fc: 613b str r3, [r7, #16]
|
|
__asm volatile
|
|
80173fe: 693b ldr r3, [r7, #16]
|
|
8017400: f383 8811 msr BASEPRI, r3
|
|
}
|
|
8017404: bf00 nop
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
}
|
|
8017406: bf00 nop
|
|
8017408: 3740 adds r7, #64 @ 0x40
|
|
801740a: 46bd mov sp, r7
|
|
801740c: bd80 pop {r7, pc}
|
|
801740e: bf00 nop
|
|
8017410: 20002664 .word 0x20002664
|
|
8017414: 20002644 .word 0x20002644
|
|
8017418: 2000216c .word 0x2000216c
|
|
801741c: 200025fc .word 0x200025fc
|
|
8017420: 20002168 .word 0x20002168
|
|
8017424: 20002650 .word 0x20002650
|
|
|
|
08017428 <prvAddCurrentTaskToDelayedList>:
|
|
#endif
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
|
|
const BaseType_t xCanBlockIndefinitely )
|
|
{
|
|
8017428: b580 push {r7, lr}
|
|
801742a: b086 sub sp, #24
|
|
801742c: af00 add r7, sp, #0
|
|
801742e: 6078 str r0, [r7, #4]
|
|
8017430: 6039 str r1, [r7, #0]
|
|
TickType_t xTimeToWake;
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
8017432: 4b2e ldr r3, [pc, #184] @ (80174ec <prvAddCurrentTaskToDelayedList+0xc4>)
|
|
8017434: 681b ldr r3, [r3, #0]
|
|
8017436: 617b str r3, [r7, #20]
|
|
}
|
|
#endif
|
|
|
|
/* Remove the task from the ready list before adding it to the blocked list
|
|
* as the same list item is used for both lists. */
|
|
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
8017438: 4b2d ldr r3, [pc, #180] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
801743a: 681b ldr r3, [r3, #0]
|
|
801743c: 3304 adds r3, #4
|
|
801743e: 4618 mov r0, r3
|
|
8017440: f7fc fffa bl 8014438 <uxListRemove>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
|
|
8017444: 687b ldr r3, [r7, #4]
|
|
8017446: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
801744a: d124 bne.n 8017496 <prvAddCurrentTaskToDelayedList+0x6e>
|
|
801744c: 683b ldr r3, [r7, #0]
|
|
801744e: 2b00 cmp r3, #0
|
|
8017450: d021 beq.n 8017496 <prvAddCurrentTaskToDelayedList+0x6e>
|
|
{
|
|
/* Add the task to the suspended task list instead of a delayed task
|
|
* list to ensure it is not woken by a timing event. It will block
|
|
* indefinitely. */
|
|
listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
8017452: 4b28 ldr r3, [pc, #160] @ (80174f4 <prvAddCurrentTaskToDelayedList+0xcc>)
|
|
8017454: 685b ldr r3, [r3, #4]
|
|
8017456: 613b str r3, [r7, #16]
|
|
8017458: 4b25 ldr r3, [pc, #148] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
801745a: 681b ldr r3, [r3, #0]
|
|
801745c: 693a ldr r2, [r7, #16]
|
|
801745e: 609a str r2, [r3, #8]
|
|
8017460: 4b23 ldr r3, [pc, #140] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
8017462: 681b ldr r3, [r3, #0]
|
|
8017464: 693a ldr r2, [r7, #16]
|
|
8017466: 6892 ldr r2, [r2, #8]
|
|
8017468: 60da str r2, [r3, #12]
|
|
801746a: 4b21 ldr r3, [pc, #132] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
801746c: 681a ldr r2, [r3, #0]
|
|
801746e: 693b ldr r3, [r7, #16]
|
|
8017470: 689b ldr r3, [r3, #8]
|
|
8017472: 3204 adds r2, #4
|
|
8017474: 605a str r2, [r3, #4]
|
|
8017476: 4b1e ldr r3, [pc, #120] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
8017478: 681b ldr r3, [r3, #0]
|
|
801747a: 1d1a adds r2, r3, #4
|
|
801747c: 693b ldr r3, [r7, #16]
|
|
801747e: 609a str r2, [r3, #8]
|
|
8017480: 4b1b ldr r3, [pc, #108] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
8017482: 681b ldr r3, [r3, #0]
|
|
8017484: 4a1b ldr r2, [pc, #108] @ (80174f4 <prvAddCurrentTaskToDelayedList+0xcc>)
|
|
8017486: 615a str r2, [r3, #20]
|
|
8017488: 4b1a ldr r3, [pc, #104] @ (80174f4 <prvAddCurrentTaskToDelayedList+0xcc>)
|
|
801748a: 681b ldr r3, [r3, #0]
|
|
801748c: 3301 adds r3, #1
|
|
801748e: 4a19 ldr r2, [pc, #100] @ (80174f4 <prvAddCurrentTaskToDelayedList+0xcc>)
|
|
8017490: 6013 str r3, [r2, #0]
|
|
8017492: bf00 nop
|
|
|
|
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
|
|
( void ) xCanBlockIndefinitely;
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
}
|
|
8017494: e026 b.n 80174e4 <prvAddCurrentTaskToDelayedList+0xbc>
|
|
xTimeToWake = xConstTickCount + xTicksToWait;
|
|
8017496: 697a ldr r2, [r7, #20]
|
|
8017498: 687b ldr r3, [r7, #4]
|
|
801749a: 4413 add r3, r2
|
|
801749c: 60fb str r3, [r7, #12]
|
|
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
|
|
801749e: 4b14 ldr r3, [pc, #80] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
80174a0: 681b ldr r3, [r3, #0]
|
|
80174a2: 68fa ldr r2, [r7, #12]
|
|
80174a4: 605a str r2, [r3, #4]
|
|
if( xTimeToWake < xConstTickCount )
|
|
80174a6: 68fa ldr r2, [r7, #12]
|
|
80174a8: 697b ldr r3, [r7, #20]
|
|
80174aa: 429a cmp r2, r3
|
|
80174ac: d209 bcs.n 80174c2 <prvAddCurrentTaskToDelayedList+0x9a>
|
|
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
80174ae: 4b12 ldr r3, [pc, #72] @ (80174f8 <prvAddCurrentTaskToDelayedList+0xd0>)
|
|
80174b0: 681a ldr r2, [r3, #0]
|
|
80174b2: 4b0f ldr r3, [pc, #60] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
80174b4: 681b ldr r3, [r3, #0]
|
|
80174b6: 3304 adds r3, #4
|
|
80174b8: 4619 mov r1, r3
|
|
80174ba: 4610 mov r0, r2
|
|
80174bc: f7fc ff83 bl 80143c6 <vListInsert>
|
|
}
|
|
80174c0: e010 b.n 80174e4 <prvAddCurrentTaskToDelayedList+0xbc>
|
|
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
80174c2: 4b0e ldr r3, [pc, #56] @ (80174fc <prvAddCurrentTaskToDelayedList+0xd4>)
|
|
80174c4: 681a ldr r2, [r3, #0]
|
|
80174c6: 4b0a ldr r3, [pc, #40] @ (80174f0 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
80174c8: 681b ldr r3, [r3, #0]
|
|
80174ca: 3304 adds r3, #4
|
|
80174cc: 4619 mov r1, r3
|
|
80174ce: 4610 mov r0, r2
|
|
80174d0: f7fc ff79 bl 80143c6 <vListInsert>
|
|
if( xTimeToWake < xNextTaskUnblockTime )
|
|
80174d4: 4b0a ldr r3, [pc, #40] @ (8017500 <prvAddCurrentTaskToDelayedList+0xd8>)
|
|
80174d6: 681b ldr r3, [r3, #0]
|
|
80174d8: 68fa ldr r2, [r7, #12]
|
|
80174da: 429a cmp r2, r3
|
|
80174dc: d202 bcs.n 80174e4 <prvAddCurrentTaskToDelayedList+0xbc>
|
|
xNextTaskUnblockTime = xTimeToWake;
|
|
80174de: 4a08 ldr r2, [pc, #32] @ (8017500 <prvAddCurrentTaskToDelayedList+0xd8>)
|
|
80174e0: 68fb ldr r3, [r7, #12]
|
|
80174e2: 6013 str r3, [r2, #0]
|
|
}
|
|
80174e4: bf00 nop
|
|
80174e6: 3718 adds r7, #24
|
|
80174e8: 46bd mov sp, r7
|
|
80174ea: bd80 pop {r7, pc}
|
|
80174ec: 20002640 .word 0x20002640
|
|
80174f0: 20002168 .word 0x20002168
|
|
80174f4: 20002628 .word 0x20002628
|
|
80174f8: 200025f8 .word 0x200025f8
|
|
80174fc: 200025f4 .word 0x200025f4
|
|
8017500: 2000265c .word 0x2000265c
|
|
|
|
08017504 <xTimerCreateTimerTask>:
|
|
TimerCallbackFunction_t pxCallbackFunction,
|
|
Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION;
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTimerCreateTimerTask( void )
|
|
{
|
|
8017504: b580 push {r7, lr}
|
|
8017506: b08a sub sp, #40 @ 0x28
|
|
8017508: af04 add r7, sp, #16
|
|
BaseType_t xReturn = pdFAIL;
|
|
801750a: 2300 movs r3, #0
|
|
801750c: 617b str r3, [r7, #20]
|
|
|
|
/* This function is called when the scheduler is started if
|
|
* configUSE_TIMERS is set to 1. Check that the infrastructure used by the
|
|
* timer service task has been created/initialised. If timers have already
|
|
* been created then the initialisation will already have been performed. */
|
|
prvCheckForValidListAndQueue();
|
|
801750e: f000 fa81 bl 8017a14 <prvCheckForValidListAndQueue>
|
|
|
|
if( xTimerQueue != NULL )
|
|
8017512: 4b1d ldr r3, [pc, #116] @ (8017588 <xTimerCreateTimerTask+0x84>)
|
|
8017514: 681b ldr r3, [r3, #0]
|
|
8017516: 2b00 cmp r3, #0
|
|
8017518: d021 beq.n 801755e <xTimerCreateTimerTask+0x5a>
|
|
{
|
|
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
StaticTask_t * pxTimerTaskTCBBuffer = NULL;
|
|
801751a: 2300 movs r3, #0
|
|
801751c: 60fb str r3, [r7, #12]
|
|
StackType_t * pxTimerTaskStackBuffer = NULL;
|
|
801751e: 2300 movs r3, #0
|
|
8017520: 60bb str r3, [r7, #8]
|
|
uint32_t ulTimerTaskStackSize;
|
|
|
|
vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
|
|
8017522: 1d3a adds r2, r7, #4
|
|
8017524: f107 0108 add.w r1, r7, #8
|
|
8017528: f107 030c add.w r3, r7, #12
|
|
801752c: 4618 mov r0, r3
|
|
801752e: f7fc ff03 bl 8014338 <vApplicationGetTimerTaskMemory>
|
|
xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
|
|
8017532: 6879 ldr r1, [r7, #4]
|
|
8017534: 68bb ldr r3, [r7, #8]
|
|
8017536: 68fa ldr r2, [r7, #12]
|
|
8017538: 9202 str r2, [sp, #8]
|
|
801753a: 9301 str r3, [sp, #4]
|
|
801753c: 2302 movs r3, #2
|
|
801753e: 9300 str r3, [sp, #0]
|
|
8017540: 2300 movs r3, #0
|
|
8017542: 460a mov r2, r1
|
|
8017544: 4911 ldr r1, [pc, #68] @ (801758c <xTimerCreateTimerTask+0x88>)
|
|
8017546: 4812 ldr r0, [pc, #72] @ (8017590 <xTimerCreateTimerTask+0x8c>)
|
|
8017548: f7fe f90a bl 8015760 <xTaskCreateStatic>
|
|
801754c: 4603 mov r3, r0
|
|
801754e: 4a11 ldr r2, [pc, #68] @ (8017594 <xTimerCreateTimerTask+0x90>)
|
|
8017550: 6013 str r3, [r2, #0]
|
|
NULL,
|
|
( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
|
|
pxTimerTaskStackBuffer,
|
|
pxTimerTaskTCBBuffer );
|
|
|
|
if( xTimerTaskHandle != NULL )
|
|
8017552: 4b10 ldr r3, [pc, #64] @ (8017594 <xTimerCreateTimerTask+0x90>)
|
|
8017554: 681b ldr r3, [r3, #0]
|
|
8017556: 2b00 cmp r3, #0
|
|
8017558: d001 beq.n 801755e <xTimerCreateTimerTask+0x5a>
|
|
{
|
|
xReturn = pdPASS;
|
|
801755a: 2301 movs r3, #1
|
|
801755c: 617b str r3, [r7, #20]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
configASSERT( xReturn );
|
|
801755e: 697b ldr r3, [r7, #20]
|
|
8017560: 2b00 cmp r3, #0
|
|
8017562: d10b bne.n 801757c <xTimerCreateTimerTask+0x78>
|
|
__asm volatile
|
|
8017564: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017568: f383 8811 msr BASEPRI, r3
|
|
801756c: f3bf 8f6f isb sy
|
|
8017570: f3bf 8f4f dsb sy
|
|
8017574: 613b str r3, [r7, #16]
|
|
}
|
|
8017576: bf00 nop
|
|
8017578: bf00 nop
|
|
801757a: e7fd b.n 8017578 <xTimerCreateTimerTask+0x74>
|
|
return xReturn;
|
|
801757c: 697b ldr r3, [r7, #20]
|
|
}
|
|
801757e: 4618 mov r0, r3
|
|
8017580: 3718 adds r7, #24
|
|
8017582: 46bd mov sp, r7
|
|
8017584: bd80 pop {r7, pc}
|
|
8017586: bf00 nop
|
|
8017588: 20002698 .word 0x20002698
|
|
801758c: 0801e324 .word 0x0801e324
|
|
8017590: 0801763d .word 0x0801763d
|
|
8017594: 2000269c .word 0x2000269c
|
|
|
|
08017598 <prvReloadTimer>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvReloadTimer( Timer_t * const pxTimer,
|
|
TickType_t xExpiredTime,
|
|
const TickType_t xTimeNow )
|
|
{
|
|
8017598: b580 push {r7, lr}
|
|
801759a: b084 sub sp, #16
|
|
801759c: af00 add r7, sp, #0
|
|
801759e: 60f8 str r0, [r7, #12]
|
|
80175a0: 60b9 str r1, [r7, #8]
|
|
80175a2: 607a str r2, [r7, #4]
|
|
/* Insert the timer into the appropriate list for the next expiry time.
|
|
* If the next expiry time has already passed, advance the expiry time,
|
|
* call the callback function, and try again. */
|
|
while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE )
|
|
80175a4: e008 b.n 80175b8 <prvReloadTimer+0x20>
|
|
{
|
|
/* Advance the expiry time. */
|
|
xExpiredTime += pxTimer->xTimerPeriodInTicks;
|
|
80175a6: 68fb ldr r3, [r7, #12]
|
|
80175a8: 699b ldr r3, [r3, #24]
|
|
80175aa: 68ba ldr r2, [r7, #8]
|
|
80175ac: 4413 add r3, r2
|
|
80175ae: 60bb str r3, [r7, #8]
|
|
|
|
/* Call the timer callback. */
|
|
traceTIMER_EXPIRED( pxTimer );
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
|
80175b0: 68fb ldr r3, [r7, #12]
|
|
80175b2: 6a1b ldr r3, [r3, #32]
|
|
80175b4: 68f8 ldr r0, [r7, #12]
|
|
80175b6: 4798 blx r3
|
|
while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE )
|
|
80175b8: 68fb ldr r3, [r7, #12]
|
|
80175ba: 699a ldr r2, [r3, #24]
|
|
80175bc: 68bb ldr r3, [r7, #8]
|
|
80175be: 18d1 adds r1, r2, r3
|
|
80175c0: 68bb ldr r3, [r7, #8]
|
|
80175c2: 687a ldr r2, [r7, #4]
|
|
80175c4: 68f8 ldr r0, [r7, #12]
|
|
80175c6: f000 f8df bl 8017788 <prvInsertTimerInActiveList>
|
|
80175ca: 4603 mov r3, r0
|
|
80175cc: 2b00 cmp r3, #0
|
|
80175ce: d1ea bne.n 80175a6 <prvReloadTimer+0xe>
|
|
}
|
|
}
|
|
80175d0: bf00 nop
|
|
80175d2: bf00 nop
|
|
80175d4: 3710 adds r7, #16
|
|
80175d6: 46bd mov sp, r7
|
|
80175d8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080175dc <prvProcessExpiredTimer>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
|
|
const TickType_t xTimeNow )
|
|
{
|
|
80175dc: b580 push {r7, lr}
|
|
80175de: b084 sub sp, #16
|
|
80175e0: af00 add r7, sp, #0
|
|
80175e2: 6078 str r0, [r7, #4]
|
|
80175e4: 6039 str r1, [r7, #0]
|
|
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
80175e6: 4b14 ldr r3, [pc, #80] @ (8017638 <prvProcessExpiredTimer+0x5c>)
|
|
80175e8: 681b ldr r3, [r3, #0]
|
|
80175ea: 68db ldr r3, [r3, #12]
|
|
80175ec: 68db ldr r3, [r3, #12]
|
|
80175ee: 60fb str r3, [r7, #12]
|
|
|
|
/* Remove the timer from the list of active timers. A check has already
|
|
* been performed to ensure the list is not empty. */
|
|
|
|
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
|
|
80175f0: 68fb ldr r3, [r7, #12]
|
|
80175f2: 3304 adds r3, #4
|
|
80175f4: 4618 mov r0, r3
|
|
80175f6: f7fc ff1f bl 8014438 <uxListRemove>
|
|
|
|
/* If the timer is an auto-reload timer then calculate the next
|
|
* expiry time and re-insert the timer in the list of active timers. */
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
|
|
80175fa: 68fb ldr r3, [r7, #12]
|
|
80175fc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
8017600: f003 0304 and.w r3, r3, #4
|
|
8017604: 2b00 cmp r3, #0
|
|
8017606: d005 beq.n 8017614 <prvProcessExpiredTimer+0x38>
|
|
{
|
|
prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow );
|
|
8017608: 683a ldr r2, [r7, #0]
|
|
801760a: 6879 ldr r1, [r7, #4]
|
|
801760c: 68f8 ldr r0, [r7, #12]
|
|
801760e: f7ff ffc3 bl 8017598 <prvReloadTimer>
|
|
8017612: e008 b.n 8017626 <prvProcessExpiredTimer+0x4a>
|
|
}
|
|
else
|
|
{
|
|
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
|
|
8017614: 68fb ldr r3, [r7, #12]
|
|
8017616: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
801761a: f023 0301 bic.w r3, r3, #1
|
|
801761e: b2da uxtb r2, r3
|
|
8017620: 68fb ldr r3, [r7, #12]
|
|
8017622: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Call the timer callback. */
|
|
traceTIMER_EXPIRED( pxTimer );
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
|
8017626: 68fb ldr r3, [r7, #12]
|
|
8017628: 6a1b ldr r3, [r3, #32]
|
|
801762a: 68f8 ldr r0, [r7, #12]
|
|
801762c: 4798 blx r3
|
|
}
|
|
801762e: bf00 nop
|
|
8017630: 3710 adds r7, #16
|
|
8017632: 46bd mov sp, r7
|
|
8017634: bd80 pop {r7, pc}
|
|
8017636: bf00 nop
|
|
8017638: 20002690 .word 0x20002690
|
|
|
|
0801763c <prvTimerTask>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static portTASK_FUNCTION( prvTimerTask, pvParameters )
|
|
{
|
|
801763c: b580 push {r7, lr}
|
|
801763e: b084 sub sp, #16
|
|
8017640: af00 add r7, sp, #0
|
|
8017642: 6078 str r0, [r7, #4]
|
|
|
|
for( ; ; )
|
|
{
|
|
/* Query the timers list to see if it contains any timers, and if so,
|
|
* obtain the time at which the next timer will expire. */
|
|
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
|
|
8017644: f107 0308 add.w r3, r7, #8
|
|
8017648: 4618 mov r0, r3
|
|
801764a: f000 f859 bl 8017700 <prvGetNextExpireTime>
|
|
801764e: 60f8 str r0, [r7, #12]
|
|
|
|
/* If a timer has expired, process it. Otherwise, block this task
|
|
* until either a timer does expire, or a command is received. */
|
|
prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
|
|
8017650: 68bb ldr r3, [r7, #8]
|
|
8017652: 4619 mov r1, r3
|
|
8017654: 68f8 ldr r0, [r7, #12]
|
|
8017656: f000 f805 bl 8017664 <prvProcessTimerOrBlockTask>
|
|
|
|
/* Empty the command queue. */
|
|
prvProcessReceivedCommands();
|
|
801765a: f000 f8d7 bl 801780c <prvProcessReceivedCommands>
|
|
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
|
|
801765e: bf00 nop
|
|
8017660: e7f0 b.n 8017644 <prvTimerTask+0x8>
|
|
...
|
|
|
|
08017664 <prvProcessTimerOrBlockTask>:
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
|
|
BaseType_t xListWasEmpty )
|
|
{
|
|
8017664: b580 push {r7, lr}
|
|
8017666: b084 sub sp, #16
|
|
8017668: af00 add r7, sp, #0
|
|
801766a: 6078 str r0, [r7, #4]
|
|
801766c: 6039 str r1, [r7, #0]
|
|
TickType_t xTimeNow;
|
|
BaseType_t xTimerListsWereSwitched;
|
|
|
|
vTaskSuspendAll();
|
|
801766e: f7fe fad9 bl 8015c24 <vTaskSuspendAll>
|
|
/* Obtain the time now to make an assessment as to whether the timer
|
|
* has expired or not. If obtaining the time causes the lists to switch
|
|
* then don't process this timer as any timers that remained in the list
|
|
* when the lists were switched will have been processed within the
|
|
* prvSampleTimeNow() function. */
|
|
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
|
|
8017672: f107 0308 add.w r3, r7, #8
|
|
8017676: 4618 mov r0, r3
|
|
8017678: f000 f866 bl 8017748 <prvSampleTimeNow>
|
|
801767c: 60f8 str r0, [r7, #12]
|
|
|
|
if( xTimerListsWereSwitched == pdFALSE )
|
|
801767e: 68bb ldr r3, [r7, #8]
|
|
8017680: 2b00 cmp r3, #0
|
|
8017682: d130 bne.n 80176e6 <prvProcessTimerOrBlockTask+0x82>
|
|
{
|
|
/* The tick count has not overflowed, has the timer expired? */
|
|
if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
|
|
8017684: 683b ldr r3, [r7, #0]
|
|
8017686: 2b00 cmp r3, #0
|
|
8017688: d10a bne.n 80176a0 <prvProcessTimerOrBlockTask+0x3c>
|
|
801768a: 687a ldr r2, [r7, #4]
|
|
801768c: 68fb ldr r3, [r7, #12]
|
|
801768e: 429a cmp r2, r3
|
|
8017690: d806 bhi.n 80176a0 <prvProcessTimerOrBlockTask+0x3c>
|
|
{
|
|
( void ) xTaskResumeAll();
|
|
8017692: f7fe fad5 bl 8015c40 <xTaskResumeAll>
|
|
prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
|
|
8017696: 68f9 ldr r1, [r7, #12]
|
|
8017698: 6878 ldr r0, [r7, #4]
|
|
801769a: f7ff ff9f bl 80175dc <prvProcessExpiredTimer>
|
|
else
|
|
{
|
|
( void ) xTaskResumeAll();
|
|
}
|
|
}
|
|
}
|
|
801769e: e024 b.n 80176ea <prvProcessTimerOrBlockTask+0x86>
|
|
if( xListWasEmpty != pdFALSE )
|
|
80176a0: 683b ldr r3, [r7, #0]
|
|
80176a2: 2b00 cmp r3, #0
|
|
80176a4: d008 beq.n 80176b8 <prvProcessTimerOrBlockTask+0x54>
|
|
xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
|
|
80176a6: 4b13 ldr r3, [pc, #76] @ (80176f4 <prvProcessTimerOrBlockTask+0x90>)
|
|
80176a8: 681b ldr r3, [r3, #0]
|
|
80176aa: 681b ldr r3, [r3, #0]
|
|
80176ac: 2b00 cmp r3, #0
|
|
80176ae: d101 bne.n 80176b4 <prvProcessTimerOrBlockTask+0x50>
|
|
80176b0: 2301 movs r3, #1
|
|
80176b2: e000 b.n 80176b6 <prvProcessTimerOrBlockTask+0x52>
|
|
80176b4: 2300 movs r3, #0
|
|
80176b6: 603b str r3, [r7, #0]
|
|
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
|
|
80176b8: 4b0f ldr r3, [pc, #60] @ (80176f8 <prvProcessTimerOrBlockTask+0x94>)
|
|
80176ba: 6818 ldr r0, [r3, #0]
|
|
80176bc: 687a ldr r2, [r7, #4]
|
|
80176be: 68fb ldr r3, [r7, #12]
|
|
80176c0: 1ad3 subs r3, r2, r3
|
|
80176c2: 683a ldr r2, [r7, #0]
|
|
80176c4: 4619 mov r1, r3
|
|
80176c6: f7fe f817 bl 80156f8 <vQueueWaitForMessageRestricted>
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
80176ca: f7fe fab9 bl 8015c40 <xTaskResumeAll>
|
|
80176ce: 4603 mov r3, r0
|
|
80176d0: 2b00 cmp r3, #0
|
|
80176d2: d10a bne.n 80176ea <prvProcessTimerOrBlockTask+0x86>
|
|
portYIELD_WITHIN_API();
|
|
80176d4: 4b09 ldr r3, [pc, #36] @ (80176fc <prvProcessTimerOrBlockTask+0x98>)
|
|
80176d6: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80176da: 601a str r2, [r3, #0]
|
|
80176dc: f3bf 8f4f dsb sy
|
|
80176e0: f3bf 8f6f isb sy
|
|
}
|
|
80176e4: e001 b.n 80176ea <prvProcessTimerOrBlockTask+0x86>
|
|
( void ) xTaskResumeAll();
|
|
80176e6: f7fe faab bl 8015c40 <xTaskResumeAll>
|
|
}
|
|
80176ea: bf00 nop
|
|
80176ec: 3710 adds r7, #16
|
|
80176ee: 46bd mov sp, r7
|
|
80176f0: bd80 pop {r7, pc}
|
|
80176f2: bf00 nop
|
|
80176f4: 20002694 .word 0x20002694
|
|
80176f8: 20002698 .word 0x20002698
|
|
80176fc: e000ed04 .word 0xe000ed04
|
|
|
|
08017700 <prvGetNextExpireTime>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
|
|
{
|
|
8017700: b480 push {r7}
|
|
8017702: b085 sub sp, #20
|
|
8017704: af00 add r7, sp, #0
|
|
8017706: 6078 str r0, [r7, #4]
|
|
* the timer with the nearest expiry time will expire. If there are no
|
|
* active timers then just set the next expire time to 0. That will cause
|
|
* this task to unblock when the tick count overflows, at which point the
|
|
* timer lists will be switched and the next expiry time can be
|
|
* re-assessed. */
|
|
*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
|
|
8017708: 4b0e ldr r3, [pc, #56] @ (8017744 <prvGetNextExpireTime+0x44>)
|
|
801770a: 681b ldr r3, [r3, #0]
|
|
801770c: 681b ldr r3, [r3, #0]
|
|
801770e: 2b00 cmp r3, #0
|
|
8017710: d101 bne.n 8017716 <prvGetNextExpireTime+0x16>
|
|
8017712: 2201 movs r2, #1
|
|
8017714: e000 b.n 8017718 <prvGetNextExpireTime+0x18>
|
|
8017716: 2200 movs r2, #0
|
|
8017718: 687b ldr r3, [r7, #4]
|
|
801771a: 601a str r2, [r3, #0]
|
|
|
|
if( *pxListWasEmpty == pdFALSE )
|
|
801771c: 687b ldr r3, [r7, #4]
|
|
801771e: 681b ldr r3, [r3, #0]
|
|
8017720: 2b00 cmp r3, #0
|
|
8017722: d105 bne.n 8017730 <prvGetNextExpireTime+0x30>
|
|
{
|
|
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
|
|
8017724: 4b07 ldr r3, [pc, #28] @ (8017744 <prvGetNextExpireTime+0x44>)
|
|
8017726: 681b ldr r3, [r3, #0]
|
|
8017728: 68db ldr r3, [r3, #12]
|
|
801772a: 681b ldr r3, [r3, #0]
|
|
801772c: 60fb str r3, [r7, #12]
|
|
801772e: e001 b.n 8017734 <prvGetNextExpireTime+0x34>
|
|
}
|
|
else
|
|
{
|
|
/* Ensure the task unblocks when the tick count rolls over. */
|
|
xNextExpireTime = ( TickType_t ) 0U;
|
|
8017730: 2300 movs r3, #0
|
|
8017732: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return xNextExpireTime;
|
|
8017734: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8017736: 4618 mov r0, r3
|
|
8017738: 3714 adds r7, #20
|
|
801773a: 46bd mov sp, r7
|
|
801773c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8017740: 4770 bx lr
|
|
8017742: bf00 nop
|
|
8017744: 20002690 .word 0x20002690
|
|
|
|
08017748 <prvSampleTimeNow>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
|
|
{
|
|
8017748: b580 push {r7, lr}
|
|
801774a: b084 sub sp, #16
|
|
801774c: af00 add r7, sp, #0
|
|
801774e: 6078 str r0, [r7, #4]
|
|
TickType_t xTimeNow;
|
|
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
|
|
|
|
xTimeNow = xTaskGetTickCount();
|
|
8017750: f7fe fb74 bl 8015e3c <xTaskGetTickCount>
|
|
8017754: 60f8 str r0, [r7, #12]
|
|
|
|
if( xTimeNow < xLastTime )
|
|
8017756: 4b0b ldr r3, [pc, #44] @ (8017784 <prvSampleTimeNow+0x3c>)
|
|
8017758: 681b ldr r3, [r3, #0]
|
|
801775a: 68fa ldr r2, [r7, #12]
|
|
801775c: 429a cmp r2, r3
|
|
801775e: d205 bcs.n 801776c <prvSampleTimeNow+0x24>
|
|
{
|
|
prvSwitchTimerLists();
|
|
8017760: f000 f932 bl 80179c8 <prvSwitchTimerLists>
|
|
*pxTimerListsWereSwitched = pdTRUE;
|
|
8017764: 687b ldr r3, [r7, #4]
|
|
8017766: 2201 movs r2, #1
|
|
8017768: 601a str r2, [r3, #0]
|
|
801776a: e002 b.n 8017772 <prvSampleTimeNow+0x2a>
|
|
}
|
|
else
|
|
{
|
|
*pxTimerListsWereSwitched = pdFALSE;
|
|
801776c: 687b ldr r3, [r7, #4]
|
|
801776e: 2200 movs r2, #0
|
|
8017770: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
xLastTime = xTimeNow;
|
|
8017772: 4a04 ldr r2, [pc, #16] @ (8017784 <prvSampleTimeNow+0x3c>)
|
|
8017774: 68fb ldr r3, [r7, #12]
|
|
8017776: 6013 str r3, [r2, #0]
|
|
|
|
return xTimeNow;
|
|
8017778: 68fb ldr r3, [r7, #12]
|
|
}
|
|
801777a: 4618 mov r0, r3
|
|
801777c: 3710 adds r7, #16
|
|
801777e: 46bd mov sp, r7
|
|
8017780: bd80 pop {r7, pc}
|
|
8017782: bf00 nop
|
|
8017784: 200026a0 .word 0x200026a0
|
|
|
|
08017788 <prvInsertTimerInActiveList>:
|
|
|
|
static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
|
|
const TickType_t xNextExpiryTime,
|
|
const TickType_t xTimeNow,
|
|
const TickType_t xCommandTime )
|
|
{
|
|
8017788: b580 push {r7, lr}
|
|
801778a: b086 sub sp, #24
|
|
801778c: af00 add r7, sp, #0
|
|
801778e: 60f8 str r0, [r7, #12]
|
|
8017790: 60b9 str r1, [r7, #8]
|
|
8017792: 607a str r2, [r7, #4]
|
|
8017794: 603b str r3, [r7, #0]
|
|
BaseType_t xProcessTimerNow = pdFALSE;
|
|
8017796: 2300 movs r3, #0
|
|
8017798: 617b str r3, [r7, #20]
|
|
|
|
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
|
|
801779a: 68fb ldr r3, [r7, #12]
|
|
801779c: 68ba ldr r2, [r7, #8]
|
|
801779e: 605a str r2, [r3, #4]
|
|
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
|
|
80177a0: 68fb ldr r3, [r7, #12]
|
|
80177a2: 68fa ldr r2, [r7, #12]
|
|
80177a4: 611a str r2, [r3, #16]
|
|
|
|
if( xNextExpiryTime <= xTimeNow )
|
|
80177a6: 68ba ldr r2, [r7, #8]
|
|
80177a8: 687b ldr r3, [r7, #4]
|
|
80177aa: 429a cmp r2, r3
|
|
80177ac: d812 bhi.n 80177d4 <prvInsertTimerInActiveList+0x4c>
|
|
{
|
|
/* Has the expiry time elapsed between the command to start/reset a
|
|
* timer was issued, and the time the command was processed? */
|
|
if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
80177ae: 687a ldr r2, [r7, #4]
|
|
80177b0: 683b ldr r3, [r7, #0]
|
|
80177b2: 1ad2 subs r2, r2, r3
|
|
80177b4: 68fb ldr r3, [r7, #12]
|
|
80177b6: 699b ldr r3, [r3, #24]
|
|
80177b8: 429a cmp r2, r3
|
|
80177ba: d302 bcc.n 80177c2 <prvInsertTimerInActiveList+0x3a>
|
|
{
|
|
/* The time between a command being issued and the command being
|
|
* processed actually exceeds the timers period. */
|
|
xProcessTimerNow = pdTRUE;
|
|
80177bc: 2301 movs r3, #1
|
|
80177be: 617b str r3, [r7, #20]
|
|
80177c0: e01b b.n 80177fa <prvInsertTimerInActiveList+0x72>
|
|
}
|
|
else
|
|
{
|
|
vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
|
|
80177c2: 4b10 ldr r3, [pc, #64] @ (8017804 <prvInsertTimerInActiveList+0x7c>)
|
|
80177c4: 681a ldr r2, [r3, #0]
|
|
80177c6: 68fb ldr r3, [r7, #12]
|
|
80177c8: 3304 adds r3, #4
|
|
80177ca: 4619 mov r1, r3
|
|
80177cc: 4610 mov r0, r2
|
|
80177ce: f7fc fdfa bl 80143c6 <vListInsert>
|
|
80177d2: e012 b.n 80177fa <prvInsertTimerInActiveList+0x72>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
|
|
80177d4: 687a ldr r2, [r7, #4]
|
|
80177d6: 683b ldr r3, [r7, #0]
|
|
80177d8: 429a cmp r2, r3
|
|
80177da: d206 bcs.n 80177ea <prvInsertTimerInActiveList+0x62>
|
|
80177dc: 68ba ldr r2, [r7, #8]
|
|
80177de: 683b ldr r3, [r7, #0]
|
|
80177e0: 429a cmp r2, r3
|
|
80177e2: d302 bcc.n 80177ea <prvInsertTimerInActiveList+0x62>
|
|
{
|
|
/* If, since the command was issued, the tick count has overflowed
|
|
* but the expiry time has not, then the timer must have already passed
|
|
* its expiry time and should be processed immediately. */
|
|
xProcessTimerNow = pdTRUE;
|
|
80177e4: 2301 movs r3, #1
|
|
80177e6: 617b str r3, [r7, #20]
|
|
80177e8: e007 b.n 80177fa <prvInsertTimerInActiveList+0x72>
|
|
}
|
|
else
|
|
{
|
|
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
|
|
80177ea: 4b07 ldr r3, [pc, #28] @ (8017808 <prvInsertTimerInActiveList+0x80>)
|
|
80177ec: 681a ldr r2, [r3, #0]
|
|
80177ee: 68fb ldr r3, [r7, #12]
|
|
80177f0: 3304 adds r3, #4
|
|
80177f2: 4619 mov r1, r3
|
|
80177f4: 4610 mov r0, r2
|
|
80177f6: f7fc fde6 bl 80143c6 <vListInsert>
|
|
}
|
|
}
|
|
|
|
return xProcessTimerNow;
|
|
80177fa: 697b ldr r3, [r7, #20]
|
|
}
|
|
80177fc: 4618 mov r0, r3
|
|
80177fe: 3718 adds r7, #24
|
|
8017800: 46bd mov sp, r7
|
|
8017802: bd80 pop {r7, pc}
|
|
8017804: 20002694 .word 0x20002694
|
|
8017808: 20002690 .word 0x20002690
|
|
|
|
0801780c <prvProcessReceivedCommands>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvProcessReceivedCommands( void )
|
|
{
|
|
801780c: b580 push {r7, lr}
|
|
801780e: b08a sub sp, #40 @ 0x28
|
|
8017810: af00 add r7, sp, #0
|
|
DaemonTaskMessage_t xMessage;
|
|
Timer_t * pxTimer;
|
|
BaseType_t xTimerListsWereSwitched;
|
|
TickType_t xTimeNow;
|
|
|
|
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
|
|
8017812: e0c7 b.n 80179a4 <prvProcessReceivedCommands+0x198>
|
|
{
|
|
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
|
|
{
|
|
/* Negative commands are pended function calls rather than timer
|
|
* commands. */
|
|
if( xMessage.xMessageID < ( BaseType_t ) 0 )
|
|
8017814: 687b ldr r3, [r7, #4]
|
|
8017816: 2b00 cmp r3, #0
|
|
8017818: da19 bge.n 801784e <prvProcessReceivedCommands+0x42>
|
|
{
|
|
const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
|
|
801781a: 1d3b adds r3, r7, #4
|
|
801781c: 3304 adds r3, #4
|
|
801781e: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* The timer uses the xCallbackParameters member to request a
|
|
* callback be executed. Check the callback is not NULL. */
|
|
configASSERT( pxCallback );
|
|
8017820: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8017822: 2b00 cmp r3, #0
|
|
8017824: d10b bne.n 801783e <prvProcessReceivedCommands+0x32>
|
|
__asm volatile
|
|
8017826: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801782a: f383 8811 msr BASEPRI, r3
|
|
801782e: f3bf 8f6f isb sy
|
|
8017832: f3bf 8f4f dsb sy
|
|
8017836: 61bb str r3, [r7, #24]
|
|
}
|
|
8017838: bf00 nop
|
|
801783a: bf00 nop
|
|
801783c: e7fd b.n 801783a <prvProcessReceivedCommands+0x2e>
|
|
|
|
/* Call the function. */
|
|
pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
|
|
801783e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8017840: 681b ldr r3, [r3, #0]
|
|
8017842: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8017844: 6850 ldr r0, [r2, #4]
|
|
8017846: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8017848: 6892 ldr r2, [r2, #8]
|
|
801784a: 4611 mov r1, r2
|
|
801784c: 4798 blx r3
|
|
}
|
|
#endif /* INCLUDE_xTimerPendFunctionCall */
|
|
|
|
/* Commands that are positive are timer commands rather than pended
|
|
* function calls. */
|
|
if( xMessage.xMessageID >= ( BaseType_t ) 0 )
|
|
801784e: 687b ldr r3, [r7, #4]
|
|
8017850: 2b00 cmp r3, #0
|
|
8017852: f2c0 80a7 blt.w 80179a4 <prvProcessReceivedCommands+0x198>
|
|
{
|
|
/* The messages uses the xTimerParameters member to work on a
|
|
* software timer. */
|
|
pxTimer = xMessage.u.xTimerParameters.pxTimer;
|
|
8017856: 68fb ldr r3, [r7, #12]
|
|
8017858: 623b str r3, [r7, #32]
|
|
|
|
if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
|
|
801785a: 6a3b ldr r3, [r7, #32]
|
|
801785c: 695b ldr r3, [r3, #20]
|
|
801785e: 2b00 cmp r3, #0
|
|
8017860: d004 beq.n 801786c <prvProcessReceivedCommands+0x60>
|
|
{
|
|
/* The timer is in a list, remove it. */
|
|
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
|
|
8017862: 6a3b ldr r3, [r7, #32]
|
|
8017864: 3304 adds r3, #4
|
|
8017866: 4618 mov r0, r3
|
|
8017868: f7fc fde6 bl 8014438 <uxListRemove>
|
|
* it must be present in the function call. prvSampleTimeNow() must be
|
|
* called after the message is received from xTimerQueue so there is no
|
|
* possibility of a higher priority task adding a message to the message
|
|
* queue with a time that is ahead of the timer daemon task (because it
|
|
* pre-empted the timer daemon task after the xTimeNow value was set). */
|
|
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
|
|
801786c: 463b mov r3, r7
|
|
801786e: 4618 mov r0, r3
|
|
8017870: f7ff ff6a bl 8017748 <prvSampleTimeNow>
|
|
8017874: 61f8 str r0, [r7, #28]
|
|
|
|
switch( xMessage.xMessageID )
|
|
8017876: 687b ldr r3, [r7, #4]
|
|
8017878: 3b01 subs r3, #1
|
|
801787a: 2b08 cmp r3, #8
|
|
801787c: f200 808f bhi.w 801799e <prvProcessReceivedCommands+0x192>
|
|
8017880: a201 add r2, pc, #4 @ (adr r2, 8017888 <prvProcessReceivedCommands+0x7c>)
|
|
8017882: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8017886: bf00 nop
|
|
8017888: 080178ad .word 0x080178ad
|
|
801788c: 080178ad .word 0x080178ad
|
|
8017890: 08017915 .word 0x08017915
|
|
8017894: 08017929 .word 0x08017929
|
|
8017898: 08017975 .word 0x08017975
|
|
801789c: 080178ad .word 0x080178ad
|
|
80178a0: 080178ad .word 0x080178ad
|
|
80178a4: 08017915 .word 0x08017915
|
|
80178a8: 08017929 .word 0x08017929
|
|
case tmrCOMMAND_START:
|
|
case tmrCOMMAND_START_FROM_ISR:
|
|
case tmrCOMMAND_RESET:
|
|
case tmrCOMMAND_RESET_FROM_ISR:
|
|
/* Start or restart a timer. */
|
|
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
|
|
80178ac: 6a3b ldr r3, [r7, #32]
|
|
80178ae: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
80178b2: f043 0301 orr.w r3, r3, #1
|
|
80178b6: b2da uxtb r2, r3
|
|
80178b8: 6a3b ldr r3, [r7, #32]
|
|
80178ba: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
|
|
if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
|
|
80178be: 68ba ldr r2, [r7, #8]
|
|
80178c0: 6a3b ldr r3, [r7, #32]
|
|
80178c2: 699b ldr r3, [r3, #24]
|
|
80178c4: 18d1 adds r1, r2, r3
|
|
80178c6: 68bb ldr r3, [r7, #8]
|
|
80178c8: 69fa ldr r2, [r7, #28]
|
|
80178ca: 6a38 ldr r0, [r7, #32]
|
|
80178cc: f7ff ff5c bl 8017788 <prvInsertTimerInActiveList>
|
|
80178d0: 4603 mov r3, r0
|
|
80178d2: 2b00 cmp r3, #0
|
|
80178d4: d065 beq.n 80179a2 <prvProcessReceivedCommands+0x196>
|
|
{
|
|
/* The timer expired before it was added to the active
|
|
* timer list. Process it now. */
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
|
|
80178d6: 6a3b ldr r3, [r7, #32]
|
|
80178d8: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
80178dc: f003 0304 and.w r3, r3, #4
|
|
80178e0: 2b00 cmp r3, #0
|
|
80178e2: d009 beq.n 80178f8 <prvProcessReceivedCommands+0xec>
|
|
{
|
|
prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
|
|
80178e4: 68ba ldr r2, [r7, #8]
|
|
80178e6: 6a3b ldr r3, [r7, #32]
|
|
80178e8: 699b ldr r3, [r3, #24]
|
|
80178ea: 4413 add r3, r2
|
|
80178ec: 69fa ldr r2, [r7, #28]
|
|
80178ee: 4619 mov r1, r3
|
|
80178f0: 6a38 ldr r0, [r7, #32]
|
|
80178f2: f7ff fe51 bl 8017598 <prvReloadTimer>
|
|
80178f6: e008 b.n 801790a <prvProcessReceivedCommands+0xfe>
|
|
}
|
|
else
|
|
{
|
|
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
|
|
80178f8: 6a3b ldr r3, [r7, #32]
|
|
80178fa: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
80178fe: f023 0301 bic.w r3, r3, #1
|
|
8017902: b2da uxtb r2, r3
|
|
8017904: 6a3b ldr r3, [r7, #32]
|
|
8017906: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Call the timer callback. */
|
|
traceTIMER_EXPIRED( pxTimer );
|
|
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
|
|
801790a: 6a3b ldr r3, [r7, #32]
|
|
801790c: 6a1b ldr r3, [r3, #32]
|
|
801790e: 6a38 ldr r0, [r7, #32]
|
|
8017910: 4798 blx r3
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
break;
|
|
8017912: e046 b.n 80179a2 <prvProcessReceivedCommands+0x196>
|
|
|
|
case tmrCOMMAND_STOP:
|
|
case tmrCOMMAND_STOP_FROM_ISR:
|
|
/* The timer has already been removed from the active list. */
|
|
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
|
|
8017914: 6a3b ldr r3, [r7, #32]
|
|
8017916: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
801791a: f023 0301 bic.w r3, r3, #1
|
|
801791e: b2da uxtb r2, r3
|
|
8017920: 6a3b ldr r3, [r7, #32]
|
|
8017922: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
break;
|
|
8017926: e03d b.n 80179a4 <prvProcessReceivedCommands+0x198>
|
|
|
|
case tmrCOMMAND_CHANGE_PERIOD:
|
|
case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
|
|
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
|
|
8017928: 6a3b ldr r3, [r7, #32]
|
|
801792a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
801792e: f043 0301 orr.w r3, r3, #1
|
|
8017932: b2da uxtb r2, r3
|
|
8017934: 6a3b ldr r3, [r7, #32]
|
|
8017936: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
|
|
801793a: 68ba ldr r2, [r7, #8]
|
|
801793c: 6a3b ldr r3, [r7, #32]
|
|
801793e: 619a str r2, [r3, #24]
|
|
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
|
|
8017940: 6a3b ldr r3, [r7, #32]
|
|
8017942: 699b ldr r3, [r3, #24]
|
|
8017944: 2b00 cmp r3, #0
|
|
8017946: d10b bne.n 8017960 <prvProcessReceivedCommands+0x154>
|
|
__asm volatile
|
|
8017948: f04f 0350 mov.w r3, #80 @ 0x50
|
|
801794c: f383 8811 msr BASEPRI, r3
|
|
8017950: f3bf 8f6f isb sy
|
|
8017954: f3bf 8f4f dsb sy
|
|
8017958: 617b str r3, [r7, #20]
|
|
}
|
|
801795a: bf00 nop
|
|
801795c: bf00 nop
|
|
801795e: e7fd b.n 801795c <prvProcessReceivedCommands+0x150>
|
|
* be longer or shorter than the old one. The command time is
|
|
* therefore set to the current time, and as the period cannot
|
|
* be zero the next expiry time can only be in the future,
|
|
* meaning (unlike for the xTimerStart() case above) there is
|
|
* no fail case that needs to be handled here. */
|
|
( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
|
|
8017960: 6a3b ldr r3, [r7, #32]
|
|
8017962: 699a ldr r2, [r3, #24]
|
|
8017964: 69fb ldr r3, [r7, #28]
|
|
8017966: 18d1 adds r1, r2, r3
|
|
8017968: 69fb ldr r3, [r7, #28]
|
|
801796a: 69fa ldr r2, [r7, #28]
|
|
801796c: 6a38 ldr r0, [r7, #32]
|
|
801796e: f7ff ff0b bl 8017788 <prvInsertTimerInActiveList>
|
|
break;
|
|
8017972: e017 b.n 80179a4 <prvProcessReceivedCommands+0x198>
|
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
{
|
|
/* The timer has already been removed from the active list,
|
|
* just free up the memory if the memory was dynamically
|
|
* allocated. */
|
|
if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
|
|
8017974: 6a3b ldr r3, [r7, #32]
|
|
8017976: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
801797a: f003 0302 and.w r3, r3, #2
|
|
801797e: 2b00 cmp r3, #0
|
|
8017980: d103 bne.n 801798a <prvProcessReceivedCommands+0x17e>
|
|
{
|
|
vPortFree( pxTimer );
|
|
8017982: 6a38 ldr r0, [r7, #32]
|
|
8017984: f000 fbc8 bl 8018118 <vPortFree>
|
|
* no need to free the memory - just mark the timer as
|
|
* "not active". */
|
|
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
break;
|
|
8017988: e00c b.n 80179a4 <prvProcessReceivedCommands+0x198>
|
|
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
|
|
801798a: 6a3b ldr r3, [r7, #32]
|
|
801798c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
|
|
8017990: f023 0301 bic.w r3, r3, #1
|
|
8017994: b2da uxtb r2, r3
|
|
8017996: 6a3b ldr r3, [r7, #32]
|
|
8017998: f883 2028 strb.w r2, [r3, #40] @ 0x28
|
|
break;
|
|
801799c: e002 b.n 80179a4 <prvProcessReceivedCommands+0x198>
|
|
|
|
default:
|
|
/* Don't expect to get here. */
|
|
break;
|
|
801799e: bf00 nop
|
|
80179a0: e000 b.n 80179a4 <prvProcessReceivedCommands+0x198>
|
|
break;
|
|
80179a2: bf00 nop
|
|
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
|
|
80179a4: 4b07 ldr r3, [pc, #28] @ (80179c4 <prvProcessReceivedCommands+0x1b8>)
|
|
80179a6: 681b ldr r3, [r3, #0]
|
|
80179a8: 1d39 adds r1, r7, #4
|
|
80179aa: 2200 movs r2, #0
|
|
80179ac: 4618 mov r0, r3
|
|
80179ae: f7fd fa51 bl 8014e54 <xQueueReceive>
|
|
80179b2: 4603 mov r3, r0
|
|
80179b4: 2b00 cmp r3, #0
|
|
80179b6: f47f af2d bne.w 8017814 <prvProcessReceivedCommands+0x8>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
80179ba: bf00 nop
|
|
80179bc: bf00 nop
|
|
80179be: 3728 adds r7, #40 @ 0x28
|
|
80179c0: 46bd mov sp, r7
|
|
80179c2: bd80 pop {r7, pc}
|
|
80179c4: 20002698 .word 0x20002698
|
|
|
|
080179c8 <prvSwitchTimerLists>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvSwitchTimerLists( void )
|
|
{
|
|
80179c8: b580 push {r7, lr}
|
|
80179ca: b082 sub sp, #8
|
|
80179cc: af00 add r7, sp, #0
|
|
|
|
/* The tick count has overflowed. The timer lists must be switched.
|
|
* If there are any timers still referenced from the current timer list
|
|
* then they must have expired and should be processed before the lists
|
|
* are switched. */
|
|
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
|
|
80179ce: e009 b.n 80179e4 <prvSwitchTimerLists+0x1c>
|
|
{
|
|
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
|
|
80179d0: 4b0e ldr r3, [pc, #56] @ (8017a0c <prvSwitchTimerLists+0x44>)
|
|
80179d2: 681b ldr r3, [r3, #0]
|
|
80179d4: 68db ldr r3, [r3, #12]
|
|
80179d6: 681b ldr r3, [r3, #0]
|
|
80179d8: 603b str r3, [r7, #0]
|
|
|
|
/* Process the expired timer. For auto-reload timers, be careful to
|
|
* process only expirations that occur on the current list. Further
|
|
* expirations must wait until after the lists are switched. */
|
|
prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW );
|
|
80179da: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80179de: 6838 ldr r0, [r7, #0]
|
|
80179e0: f7ff fdfc bl 80175dc <prvProcessExpiredTimer>
|
|
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
|
|
80179e4: 4b09 ldr r3, [pc, #36] @ (8017a0c <prvSwitchTimerLists+0x44>)
|
|
80179e6: 681b ldr r3, [r3, #0]
|
|
80179e8: 681b ldr r3, [r3, #0]
|
|
80179ea: 2b00 cmp r3, #0
|
|
80179ec: d1f0 bne.n 80179d0 <prvSwitchTimerLists+0x8>
|
|
}
|
|
|
|
pxTemp = pxCurrentTimerList;
|
|
80179ee: 4b07 ldr r3, [pc, #28] @ (8017a0c <prvSwitchTimerLists+0x44>)
|
|
80179f0: 681b ldr r3, [r3, #0]
|
|
80179f2: 607b str r3, [r7, #4]
|
|
pxCurrentTimerList = pxOverflowTimerList;
|
|
80179f4: 4b06 ldr r3, [pc, #24] @ (8017a10 <prvSwitchTimerLists+0x48>)
|
|
80179f6: 681b ldr r3, [r3, #0]
|
|
80179f8: 4a04 ldr r2, [pc, #16] @ (8017a0c <prvSwitchTimerLists+0x44>)
|
|
80179fa: 6013 str r3, [r2, #0]
|
|
pxOverflowTimerList = pxTemp;
|
|
80179fc: 4a04 ldr r2, [pc, #16] @ (8017a10 <prvSwitchTimerLists+0x48>)
|
|
80179fe: 687b ldr r3, [r7, #4]
|
|
8017a00: 6013 str r3, [r2, #0]
|
|
}
|
|
8017a02: bf00 nop
|
|
8017a04: 3708 adds r7, #8
|
|
8017a06: 46bd mov sp, r7
|
|
8017a08: bd80 pop {r7, pc}
|
|
8017a0a: bf00 nop
|
|
8017a0c: 20002690 .word 0x20002690
|
|
8017a10: 20002694 .word 0x20002694
|
|
|
|
08017a14 <prvCheckForValidListAndQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCheckForValidListAndQueue( void )
|
|
{
|
|
8017a14: b580 push {r7, lr}
|
|
8017a16: b082 sub sp, #8
|
|
8017a18: af02 add r7, sp, #8
|
|
/* Check that the list from which active timers are referenced, and the
|
|
* queue used to communicate with the timer service, have been
|
|
* initialised. */
|
|
taskENTER_CRITICAL();
|
|
8017a1a: f000 f989 bl 8017d30 <vPortEnterCritical>
|
|
{
|
|
if( xTimerQueue == NULL )
|
|
8017a1e: 4b15 ldr r3, [pc, #84] @ (8017a74 <prvCheckForValidListAndQueue+0x60>)
|
|
8017a20: 681b ldr r3, [r3, #0]
|
|
8017a22: 2b00 cmp r3, #0
|
|
8017a24: d120 bne.n 8017a68 <prvCheckForValidListAndQueue+0x54>
|
|
{
|
|
vListInitialise( &xActiveTimerList1 );
|
|
8017a26: 4814 ldr r0, [pc, #80] @ (8017a78 <prvCheckForValidListAndQueue+0x64>)
|
|
8017a28: f7fc fca0 bl 801436c <vListInitialise>
|
|
vListInitialise( &xActiveTimerList2 );
|
|
8017a2c: 4813 ldr r0, [pc, #76] @ (8017a7c <prvCheckForValidListAndQueue+0x68>)
|
|
8017a2e: f7fc fc9d bl 801436c <vListInitialise>
|
|
pxCurrentTimerList = &xActiveTimerList1;
|
|
8017a32: 4b13 ldr r3, [pc, #76] @ (8017a80 <prvCheckForValidListAndQueue+0x6c>)
|
|
8017a34: 4a10 ldr r2, [pc, #64] @ (8017a78 <prvCheckForValidListAndQueue+0x64>)
|
|
8017a36: 601a str r2, [r3, #0]
|
|
pxOverflowTimerList = &xActiveTimerList2;
|
|
8017a38: 4b12 ldr r3, [pc, #72] @ (8017a84 <prvCheckForValidListAndQueue+0x70>)
|
|
8017a3a: 4a10 ldr r2, [pc, #64] @ (8017a7c <prvCheckForValidListAndQueue+0x68>)
|
|
8017a3c: 601a str r2, [r3, #0]
|
|
/* The timer queue is allocated statically in case
|
|
* configSUPPORT_DYNAMIC_ALLOCATION is 0. */
|
|
PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
|
|
PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
|
|
|
|
xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
|
|
8017a3e: 2300 movs r3, #0
|
|
8017a40: 9300 str r3, [sp, #0]
|
|
8017a42: 4b11 ldr r3, [pc, #68] @ (8017a88 <prvCheckForValidListAndQueue+0x74>)
|
|
8017a44: 4a11 ldr r2, [pc, #68] @ (8017a8c <prvCheckForValidListAndQueue+0x78>)
|
|
8017a46: 2110 movs r1, #16
|
|
8017a48: 200a movs r0, #10
|
|
8017a4a: f7fc fdb1 bl 80145b0 <xQueueGenericCreateStatic>
|
|
8017a4e: 4603 mov r3, r0
|
|
8017a50: 4a08 ldr r2, [pc, #32] @ (8017a74 <prvCheckForValidListAndQueue+0x60>)
|
|
8017a52: 6013 str r3, [r2, #0]
|
|
}
|
|
#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
|
|
|
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
|
{
|
|
if( xTimerQueue != NULL )
|
|
8017a54: 4b07 ldr r3, [pc, #28] @ (8017a74 <prvCheckForValidListAndQueue+0x60>)
|
|
8017a56: 681b ldr r3, [r3, #0]
|
|
8017a58: 2b00 cmp r3, #0
|
|
8017a5a: d005 beq.n 8017a68 <prvCheckForValidListAndQueue+0x54>
|
|
{
|
|
vQueueAddToRegistry( xTimerQueue, "TmrQ" );
|
|
8017a5c: 4b05 ldr r3, [pc, #20] @ (8017a74 <prvCheckForValidListAndQueue+0x60>)
|
|
8017a5e: 681b ldr r3, [r3, #0]
|
|
8017a60: 490b ldr r1, [pc, #44] @ (8017a90 <prvCheckForValidListAndQueue+0x7c>)
|
|
8017a62: 4618 mov r0, r3
|
|
8017a64: f7fd fdbe bl 80155e4 <vQueueAddToRegistry>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8017a68: f000 f994 bl 8017d94 <vPortExitCritical>
|
|
}
|
|
8017a6c: bf00 nop
|
|
8017a6e: 46bd mov sp, r7
|
|
8017a70: bd80 pop {r7, pc}
|
|
8017a72: bf00 nop
|
|
8017a74: 20002698 .word 0x20002698
|
|
8017a78: 20002668 .word 0x20002668
|
|
8017a7c: 2000267c .word 0x2000267c
|
|
8017a80: 20002690 .word 0x20002690
|
|
8017a84: 20002694 .word 0x20002694
|
|
8017a88: 20002744 .word 0x20002744
|
|
8017a8c: 200026a4 .word 0x200026a4
|
|
8017a90: 0801e32c .word 0x0801e32c
|
|
|
|
08017a94 <pxPortInitialiseStack>:
|
|
* See header file for description.
|
|
*/
|
|
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
|
TaskFunction_t pxCode,
|
|
void * pvParameters )
|
|
{
|
|
8017a94: b480 push {r7}
|
|
8017a96: b085 sub sp, #20
|
|
8017a98: af00 add r7, sp, #0
|
|
8017a9a: 60f8 str r0, [r7, #12]
|
|
8017a9c: 60b9 str r1, [r7, #8]
|
|
8017a9e: 607a str r2, [r7, #4]
|
|
/* Simulate the stack frame as it would be created by a context switch
|
|
* interrupt. */
|
|
|
|
/* Offset added to account for the way the MCU uses the stack on entry/exit
|
|
* of interrupts, and to ensure alignment. */
|
|
pxTopOfStack--;
|
|
8017aa0: 68fb ldr r3, [r7, #12]
|
|
8017aa2: 3b04 subs r3, #4
|
|
8017aa4: 60fb str r3, [r7, #12]
|
|
|
|
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
|
|
8017aa6: 68fb ldr r3, [r7, #12]
|
|
8017aa8: f04f 7280 mov.w r2, #16777216 @ 0x1000000
|
|
8017aac: 601a str r2, [r3, #0]
|
|
pxTopOfStack--;
|
|
8017aae: 68fb ldr r3, [r7, #12]
|
|
8017ab0: 3b04 subs r3, #4
|
|
8017ab2: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
|
|
8017ab4: 68bb ldr r3, [r7, #8]
|
|
8017ab6: f023 0201 bic.w r2, r3, #1
|
|
8017aba: 68fb ldr r3, [r7, #12]
|
|
8017abc: 601a str r2, [r3, #0]
|
|
pxTopOfStack--;
|
|
8017abe: 68fb ldr r3, [r7, #12]
|
|
8017ac0: 3b04 subs r3, #4
|
|
8017ac2: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
|
|
8017ac4: 4a0c ldr r2, [pc, #48] @ (8017af8 <pxPortInitialiseStack+0x64>)
|
|
8017ac6: 68fb ldr r3, [r7, #12]
|
|
8017ac8: 601a str r2, [r3, #0]
|
|
|
|
/* Save code space by skipping register initialisation. */
|
|
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
|
|
8017aca: 68fb ldr r3, [r7, #12]
|
|
8017acc: 3b14 subs r3, #20
|
|
8017ace: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
|
|
8017ad0: 687a ldr r2, [r7, #4]
|
|
8017ad2: 68fb ldr r3, [r7, #12]
|
|
8017ad4: 601a str r2, [r3, #0]
|
|
|
|
/* A save method is being used that requires each task to maintain its
|
|
* own exec return value. */
|
|
pxTopOfStack--;
|
|
8017ad6: 68fb ldr r3, [r7, #12]
|
|
8017ad8: 3b04 subs r3, #4
|
|
8017ada: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = portINITIAL_EXC_RETURN;
|
|
8017adc: 68fb ldr r3, [r7, #12]
|
|
8017ade: f06f 0202 mvn.w r2, #2
|
|
8017ae2: 601a str r2, [r3, #0]
|
|
|
|
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
|
|
8017ae4: 68fb ldr r3, [r7, #12]
|
|
8017ae6: 3b20 subs r3, #32
|
|
8017ae8: 60fb str r3, [r7, #12]
|
|
|
|
return pxTopOfStack;
|
|
8017aea: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8017aec: 4618 mov r0, r3
|
|
8017aee: 3714 adds r7, #20
|
|
8017af0: 46bd mov sp, r7
|
|
8017af2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8017af6: 4770 bx lr
|
|
8017af8: 08017afd .word 0x08017afd
|
|
|
|
08017afc <prvTaskExitError>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvTaskExitError( void )
|
|
{
|
|
8017afc: b480 push {r7}
|
|
8017afe: b085 sub sp, #20
|
|
8017b00: af00 add r7, sp, #0
|
|
volatile uint32_t ulDummy = 0;
|
|
8017b02: 2300 movs r3, #0
|
|
8017b04: 607b str r3, [r7, #4]
|
|
* its caller as there is nothing to return to. If a task wants to exit it
|
|
* should instead call vTaskDelete( NULL ).
|
|
*
|
|
* Artificially force an assert() to be triggered if configASSERT() is
|
|
* defined, then stop here so application writers can catch the error. */
|
|
configASSERT( uxCriticalNesting == ~0UL );
|
|
8017b06: 4b13 ldr r3, [pc, #76] @ (8017b54 <prvTaskExitError+0x58>)
|
|
8017b08: 681b ldr r3, [r3, #0]
|
|
8017b0a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8017b0e: d00b beq.n 8017b28 <prvTaskExitError+0x2c>
|
|
__asm volatile
|
|
8017b10: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017b14: f383 8811 msr BASEPRI, r3
|
|
8017b18: f3bf 8f6f isb sy
|
|
8017b1c: f3bf 8f4f dsb sy
|
|
8017b20: 60fb str r3, [r7, #12]
|
|
}
|
|
8017b22: bf00 nop
|
|
8017b24: bf00 nop
|
|
8017b26: e7fd b.n 8017b24 <prvTaskExitError+0x28>
|
|
__asm volatile
|
|
8017b28: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017b2c: f383 8811 msr BASEPRI, r3
|
|
8017b30: f3bf 8f6f isb sy
|
|
8017b34: f3bf 8f4f dsb sy
|
|
8017b38: 60bb str r3, [r7, #8]
|
|
}
|
|
8017b3a: bf00 nop
|
|
portDISABLE_INTERRUPTS();
|
|
|
|
while( ulDummy == 0 )
|
|
8017b3c: bf00 nop
|
|
8017b3e: 687b ldr r3, [r7, #4]
|
|
8017b40: 2b00 cmp r3, #0
|
|
8017b42: d0fc beq.n 8017b3e <prvTaskExitError+0x42>
|
|
* about code appearing after this function is called - making ulDummy
|
|
* volatile makes the compiler think the function could return and
|
|
* therefore not output an 'unreachable code' warning for code that appears
|
|
* after it. */
|
|
}
|
|
}
|
|
8017b44: bf00 nop
|
|
8017b46: bf00 nop
|
|
8017b48: 3714 adds r7, #20
|
|
8017b4a: 46bd mov sp, r7
|
|
8017b4c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8017b50: 4770 bx lr
|
|
8017b52: bf00 nop
|
|
8017b54: 200000a4 .word 0x200000a4
|
|
...
|
|
|
|
08017b60 <SVC_Handler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortSVCHandler( void )
|
|
{
|
|
__asm volatile (
|
|
8017b60: 4b07 ldr r3, [pc, #28] @ (8017b80 <pxCurrentTCBConst2>)
|
|
8017b62: 6819 ldr r1, [r3, #0]
|
|
8017b64: 6808 ldr r0, [r1, #0]
|
|
8017b66: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8017b6a: f380 8809 msr PSP, r0
|
|
8017b6e: f3bf 8f6f isb sy
|
|
8017b72: f04f 0000 mov.w r0, #0
|
|
8017b76: f380 8811 msr BASEPRI, r0
|
|
8017b7a: 4770 bx lr
|
|
8017b7c: f3af 8000 nop.w
|
|
|
|
08017b80 <pxCurrentTCBConst2>:
|
|
8017b80: 20002168 .word 0x20002168
|
|
" bx r14 \n"
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
|
|
);
|
|
}
|
|
8017b84: bf00 nop
|
|
8017b86: bf00 nop
|
|
|
|
08017b88 <prvPortStartFirstTask>:
|
|
{
|
|
/* Start the first task. This also clears the bit that indicates the FPU is
|
|
* in use in case the FPU was used before the scheduler was started - which
|
|
* would otherwise result in the unnecessary leaving of space in the SVC stack
|
|
* for lazy saving of FPU registers. */
|
|
__asm volatile (
|
|
8017b88: 4808 ldr r0, [pc, #32] @ (8017bac <prvPortStartFirstTask+0x24>)
|
|
8017b8a: 6800 ldr r0, [r0, #0]
|
|
8017b8c: 6800 ldr r0, [r0, #0]
|
|
8017b8e: f380 8808 msr MSP, r0
|
|
8017b92: f04f 0000 mov.w r0, #0
|
|
8017b96: f380 8814 msr CONTROL, r0
|
|
8017b9a: b662 cpsie i
|
|
8017b9c: b661 cpsie f
|
|
8017b9e: f3bf 8f4f dsb sy
|
|
8017ba2: f3bf 8f6f isb sy
|
|
8017ba6: df00 svc 0
|
|
8017ba8: bf00 nop
|
|
8017baa: 0000 .short 0x0000
|
|
8017bac: e000ed08 .word 0xe000ed08
|
|
" isb \n"
|
|
" svc 0 \n" /* System call to start first task. */
|
|
" nop \n"
|
|
" .ltorg \n"
|
|
);
|
|
}
|
|
8017bb0: bf00 nop
|
|
8017bb2: bf00 nop
|
|
|
|
08017bb4 <xPortStartScheduler>:
|
|
|
|
/*
|
|
* See header file for description.
|
|
*/
|
|
BaseType_t xPortStartScheduler( void )
|
|
{
|
|
8017bb4: b580 push {r7, lr}
|
|
8017bb6: b088 sub sp, #32
|
|
8017bb8: af00 add r7, sp, #0
|
|
/* This port can be used on all revisions of the Cortex-M7 core other than
|
|
* the r0p1 parts. r0p1 parts should use the port from the
|
|
* /source/portable/GCC/ARM_CM7/r0p1 directory. */
|
|
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
|
|
8017bba: 4b54 ldr r3, [pc, #336] @ (8017d0c <xPortStartScheduler+0x158>)
|
|
8017bbc: 681b ldr r3, [r3, #0]
|
|
8017bbe: 4a54 ldr r2, [pc, #336] @ (8017d10 <xPortStartScheduler+0x15c>)
|
|
8017bc0: 4293 cmp r3, r2
|
|
8017bc2: d10b bne.n 8017bdc <xPortStartScheduler+0x28>
|
|
__asm volatile
|
|
8017bc4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017bc8: f383 8811 msr BASEPRI, r3
|
|
8017bcc: f3bf 8f6f isb sy
|
|
8017bd0: f3bf 8f4f dsb sy
|
|
8017bd4: 617b str r3, [r7, #20]
|
|
}
|
|
8017bd6: bf00 nop
|
|
8017bd8: bf00 nop
|
|
8017bda: e7fd b.n 8017bd8 <xPortStartScheduler+0x24>
|
|
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
|
|
8017bdc: 4b4b ldr r3, [pc, #300] @ (8017d0c <xPortStartScheduler+0x158>)
|
|
8017bde: 681b ldr r3, [r3, #0]
|
|
8017be0: 4a4c ldr r2, [pc, #304] @ (8017d14 <xPortStartScheduler+0x160>)
|
|
8017be2: 4293 cmp r3, r2
|
|
8017be4: d10b bne.n 8017bfe <xPortStartScheduler+0x4a>
|
|
__asm volatile
|
|
8017be6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017bea: f383 8811 msr BASEPRI, r3
|
|
8017bee: f3bf 8f6f isb sy
|
|
8017bf2: f3bf 8f4f dsb sy
|
|
8017bf6: 61bb str r3, [r7, #24]
|
|
}
|
|
8017bf8: bf00 nop
|
|
8017bfa: bf00 nop
|
|
8017bfc: e7fd b.n 8017bfa <xPortStartScheduler+0x46>
|
|
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
{
|
|
volatile uint8_t ucOriginalPriority;
|
|
volatile uint32_t ulImplementedPrioBits = 0;
|
|
8017bfe: 2300 movs r3, #0
|
|
8017c00: 607b str r3, [r7, #4]
|
|
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
|
|
8017c02: 4b45 ldr r3, [pc, #276] @ (8017d18 <xPortStartScheduler+0x164>)
|
|
8017c04: 61fb str r3, [r7, #28]
|
|
* functions can be called. ISR safe functions are those that end in
|
|
* "FromISR". FreeRTOS maintains separate thread and ISR API functions to
|
|
* ensure interrupt entry is as fast and simple as possible.
|
|
*
|
|
* Save the interrupt priority value that is about to be clobbered. */
|
|
ucOriginalPriority = *pucFirstUserPriorityRegister;
|
|
8017c06: 69fb ldr r3, [r7, #28]
|
|
8017c08: 781b ldrb r3, [r3, #0]
|
|
8017c0a: b2db uxtb r3, r3
|
|
8017c0c: 72fb strb r3, [r7, #11]
|
|
|
|
/* Determine the number of priority bits available. First write to all
|
|
* possible bits. */
|
|
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
|
|
8017c0e: 69fb ldr r3, [r7, #28]
|
|
8017c10: 22ff movs r2, #255 @ 0xff
|
|
8017c12: 701a strb r2, [r3, #0]
|
|
|
|
/* Read the value back to see how many bits stuck. */
|
|
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
|
8017c14: 69fb ldr r3, [r7, #28]
|
|
8017c16: 781b ldrb r3, [r3, #0]
|
|
8017c18: b2db uxtb r3, r3
|
|
8017c1a: 70fb strb r3, [r7, #3]
|
|
|
|
/* Use the same mask on the maximum system call priority. */
|
|
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
|
8017c1c: 78fb ldrb r3, [r7, #3]
|
|
8017c1e: b2db uxtb r3, r3
|
|
8017c20: f003 0350 and.w r3, r3, #80 @ 0x50
|
|
8017c24: b2da uxtb r2, r3
|
|
8017c26: 4b3d ldr r3, [pc, #244] @ (8017d1c <xPortStartScheduler+0x168>)
|
|
8017c28: 701a strb r2, [r3, #0]
|
|
* accounting for the number of priority bits supported by the
|
|
* hardware. A priority of 0 is invalid because setting the BASEPRI
|
|
* register to 0 unmasks all interrupts, and interrupts with priority 0
|
|
* cannot be masked using BASEPRI.
|
|
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
|
|
configASSERT( ucMaxSysCallPriority );
|
|
8017c2a: 4b3c ldr r3, [pc, #240] @ (8017d1c <xPortStartScheduler+0x168>)
|
|
8017c2c: 781b ldrb r3, [r3, #0]
|
|
8017c2e: 2b00 cmp r3, #0
|
|
8017c30: d10b bne.n 8017c4a <xPortStartScheduler+0x96>
|
|
__asm volatile
|
|
8017c32: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017c36: f383 8811 msr BASEPRI, r3
|
|
8017c3a: f3bf 8f6f isb sy
|
|
8017c3e: f3bf 8f4f dsb sy
|
|
8017c42: 613b str r3, [r7, #16]
|
|
}
|
|
8017c44: bf00 nop
|
|
8017c46: bf00 nop
|
|
8017c48: e7fd b.n 8017c46 <xPortStartScheduler+0x92>
|
|
|
|
/* Check that the bits not implemented in hardware are zero in
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
|
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
|
|
8017c4a: 78fb ldrb r3, [r7, #3]
|
|
8017c4c: b2db uxtb r3, r3
|
|
8017c4e: 43db mvns r3, r3
|
|
8017c50: f003 0350 and.w r3, r3, #80 @ 0x50
|
|
8017c54: 2b00 cmp r3, #0
|
|
8017c56: d013 beq.n 8017c80 <xPortStartScheduler+0xcc>
|
|
__asm volatile
|
|
8017c58: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017c5c: f383 8811 msr BASEPRI, r3
|
|
8017c60: f3bf 8f6f isb sy
|
|
8017c64: f3bf 8f4f dsb sy
|
|
8017c68: 60fb str r3, [r7, #12]
|
|
}
|
|
8017c6a: bf00 nop
|
|
8017c6c: bf00 nop
|
|
8017c6e: e7fd b.n 8017c6c <xPortStartScheduler+0xb8>
|
|
/* Calculate the maximum acceptable priority group value for the number
|
|
* of bits read back. */
|
|
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
{
|
|
ulImplementedPrioBits++;
|
|
8017c70: 687b ldr r3, [r7, #4]
|
|
8017c72: 3301 adds r3, #1
|
|
8017c74: 607b str r3, [r7, #4]
|
|
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
|
|
8017c76: 78fb ldrb r3, [r7, #3]
|
|
8017c78: b2db uxtb r3, r3
|
|
8017c7a: 005b lsls r3, r3, #1
|
|
8017c7c: b2db uxtb r3, r3
|
|
8017c7e: 70fb strb r3, [r7, #3]
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
8017c80: 78fb ldrb r3, [r7, #3]
|
|
8017c82: b2db uxtb r3, r3
|
|
8017c84: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8017c88: 2b80 cmp r3, #128 @ 0x80
|
|
8017c8a: d0f1 beq.n 8017c70 <xPortStartScheduler+0xbc>
|
|
}
|
|
|
|
if( ulImplementedPrioBits == 8 )
|
|
8017c8c: 687b ldr r3, [r7, #4]
|
|
8017c8e: 2b08 cmp r3, #8
|
|
8017c90: d103 bne.n 8017c9a <xPortStartScheduler+0xe6>
|
|
*
|
|
* The following assert ensures that the sub-priority bit in the
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
|
|
* confusion. */
|
|
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
|
|
ulMaxPRIGROUPValue = 0;
|
|
8017c92: 4b23 ldr r3, [pc, #140] @ (8017d20 <xPortStartScheduler+0x16c>)
|
|
8017c94: 2200 movs r2, #0
|
|
8017c96: 601a str r2, [r3, #0]
|
|
8017c98: e004 b.n 8017ca4 <xPortStartScheduler+0xf0>
|
|
}
|
|
else
|
|
{
|
|
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
|
|
8017c9a: 687b ldr r3, [r7, #4]
|
|
8017c9c: f1c3 0307 rsb r3, r3, #7
|
|
8017ca0: 4a1f ldr r2, [pc, #124] @ (8017d20 <xPortStartScheduler+0x16c>)
|
|
8017ca2: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
/* Shift the priority group value back to its position within the AIRCR
|
|
* register. */
|
|
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
|
|
8017ca4: 4b1e ldr r3, [pc, #120] @ (8017d20 <xPortStartScheduler+0x16c>)
|
|
8017ca6: 681b ldr r3, [r3, #0]
|
|
8017ca8: 021b lsls r3, r3, #8
|
|
8017caa: 4a1d ldr r2, [pc, #116] @ (8017d20 <xPortStartScheduler+0x16c>)
|
|
8017cac: 6013 str r3, [r2, #0]
|
|
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
|
|
8017cae: 4b1c ldr r3, [pc, #112] @ (8017d20 <xPortStartScheduler+0x16c>)
|
|
8017cb0: 681b ldr r3, [r3, #0]
|
|
8017cb2: f403 63e0 and.w r3, r3, #1792 @ 0x700
|
|
8017cb6: 4a1a ldr r2, [pc, #104] @ (8017d20 <xPortStartScheduler+0x16c>)
|
|
8017cb8: 6013 str r3, [r2, #0]
|
|
|
|
/* Restore the clobbered interrupt priority register to its original
|
|
* value. */
|
|
*pucFirstUserPriorityRegister = ucOriginalPriority;
|
|
8017cba: 7afb ldrb r3, [r7, #11]
|
|
8017cbc: b2da uxtb r2, r3
|
|
8017cbe: 69fb ldr r3, [r7, #28]
|
|
8017cc0: 701a strb r2, [r3, #0]
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/* Make PendSV and SysTick the lowest priority interrupts. */
|
|
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
|
|
8017cc2: 4b18 ldr r3, [pc, #96] @ (8017d24 <xPortStartScheduler+0x170>)
|
|
8017cc4: 681b ldr r3, [r3, #0]
|
|
8017cc6: 4a17 ldr r2, [pc, #92] @ (8017d24 <xPortStartScheduler+0x170>)
|
|
8017cc8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
|
|
8017ccc: 6013 str r3, [r2, #0]
|
|
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
|
8017cce: 4b15 ldr r3, [pc, #84] @ (8017d24 <xPortStartScheduler+0x170>)
|
|
8017cd0: 681b ldr r3, [r3, #0]
|
|
8017cd2: 4a14 ldr r2, [pc, #80] @ (8017d24 <xPortStartScheduler+0x170>)
|
|
8017cd4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
|
|
8017cd8: 6013 str r3, [r2, #0]
|
|
|
|
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
|
* here already. */
|
|
vPortSetupTimerInterrupt();
|
|
8017cda: f000 f8df bl 8017e9c <vPortSetupTimerInterrupt>
|
|
|
|
/* Initialise the critical nesting count ready for the first task. */
|
|
uxCriticalNesting = 0;
|
|
8017cde: 4b12 ldr r3, [pc, #72] @ (8017d28 <xPortStartScheduler+0x174>)
|
|
8017ce0: 2200 movs r2, #0
|
|
8017ce2: 601a str r2, [r3, #0]
|
|
|
|
/* Ensure the VFP is enabled - it should be anyway. */
|
|
vPortEnableVFP();
|
|
8017ce4: f000 f8fe bl 8017ee4 <vPortEnableVFP>
|
|
|
|
/* Lazy save always. */
|
|
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
|
|
8017ce8: 4b10 ldr r3, [pc, #64] @ (8017d2c <xPortStartScheduler+0x178>)
|
|
8017cea: 681b ldr r3, [r3, #0]
|
|
8017cec: 4a0f ldr r2, [pc, #60] @ (8017d2c <xPortStartScheduler+0x178>)
|
|
8017cee: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000
|
|
8017cf2: 6013 str r3, [r2, #0]
|
|
|
|
/* Start the first task. */
|
|
prvPortStartFirstTask();
|
|
8017cf4: f7ff ff48 bl 8017b88 <prvPortStartFirstTask>
|
|
* exit error function to prevent compiler warnings about a static function
|
|
* not being called in the case that the application writer overrides this
|
|
* functionality by defining configTASK_RETURN_ADDRESS. Call
|
|
* vTaskSwitchContext() so link time optimisation does not remove the
|
|
* symbol. */
|
|
vTaskSwitchContext();
|
|
8017cf8: f7fe f9d4 bl 80160a4 <vTaskSwitchContext>
|
|
prvTaskExitError();
|
|
8017cfc: f7ff fefe bl 8017afc <prvTaskExitError>
|
|
|
|
/* Should not get here! */
|
|
return 0;
|
|
8017d00: 2300 movs r3, #0
|
|
}
|
|
8017d02: 4618 mov r0, r3
|
|
8017d04: 3720 adds r7, #32
|
|
8017d06: 46bd mov sp, r7
|
|
8017d08: bd80 pop {r7, pc}
|
|
8017d0a: bf00 nop
|
|
8017d0c: e000ed00 .word 0xe000ed00
|
|
8017d10: 410fc271 .word 0x410fc271
|
|
8017d14: 410fc270 .word 0x410fc270
|
|
8017d18: e000e400 .word 0xe000e400
|
|
8017d1c: 20002794 .word 0x20002794
|
|
8017d20: 20002798 .word 0x20002798
|
|
8017d24: e000ed20 .word 0xe000ed20
|
|
8017d28: 200000a4 .word 0x200000a4
|
|
8017d2c: e000ef34 .word 0xe000ef34
|
|
|
|
08017d30 <vPortEnterCritical>:
|
|
configASSERT( uxCriticalNesting == 1000UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
8017d30: b480 push {r7}
|
|
8017d32: b083 sub sp, #12
|
|
8017d34: af00 add r7, sp, #0
|
|
__asm volatile
|
|
8017d36: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017d3a: f383 8811 msr BASEPRI, r3
|
|
8017d3e: f3bf 8f6f isb sy
|
|
8017d42: f3bf 8f4f dsb sy
|
|
8017d46: 607b str r3, [r7, #4]
|
|
}
|
|
8017d48: bf00 nop
|
|
portDISABLE_INTERRUPTS();
|
|
uxCriticalNesting++;
|
|
8017d4a: 4b10 ldr r3, [pc, #64] @ (8017d8c <vPortEnterCritical+0x5c>)
|
|
8017d4c: 681b ldr r3, [r3, #0]
|
|
8017d4e: 3301 adds r3, #1
|
|
8017d50: 4a0e ldr r2, [pc, #56] @ (8017d8c <vPortEnterCritical+0x5c>)
|
|
8017d52: 6013 str r3, [r2, #0]
|
|
/* This is not the interrupt safe version of the enter critical function so
|
|
* assert() if it is being called from an interrupt context. Only API
|
|
* functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
* the critical nesting count is 1 to protect against recursive calls if the
|
|
* assert function also uses a critical section. */
|
|
if( uxCriticalNesting == 1 )
|
|
8017d54: 4b0d ldr r3, [pc, #52] @ (8017d8c <vPortEnterCritical+0x5c>)
|
|
8017d56: 681b ldr r3, [r3, #0]
|
|
8017d58: 2b01 cmp r3, #1
|
|
8017d5a: d110 bne.n 8017d7e <vPortEnterCritical+0x4e>
|
|
{
|
|
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
|
|
8017d5c: 4b0c ldr r3, [pc, #48] @ (8017d90 <vPortEnterCritical+0x60>)
|
|
8017d5e: 681b ldr r3, [r3, #0]
|
|
8017d60: b2db uxtb r3, r3
|
|
8017d62: 2b00 cmp r3, #0
|
|
8017d64: d00b beq.n 8017d7e <vPortEnterCritical+0x4e>
|
|
__asm volatile
|
|
8017d66: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017d6a: f383 8811 msr BASEPRI, r3
|
|
8017d6e: f3bf 8f6f isb sy
|
|
8017d72: f3bf 8f4f dsb sy
|
|
8017d76: 603b str r3, [r7, #0]
|
|
}
|
|
8017d78: bf00 nop
|
|
8017d7a: bf00 nop
|
|
8017d7c: e7fd b.n 8017d7a <vPortEnterCritical+0x4a>
|
|
}
|
|
}
|
|
8017d7e: bf00 nop
|
|
8017d80: 370c adds r7, #12
|
|
8017d82: 46bd mov sp, r7
|
|
8017d84: f85d 7b04 ldr.w r7, [sp], #4
|
|
8017d88: 4770 bx lr
|
|
8017d8a: bf00 nop
|
|
8017d8c: 200000a4 .word 0x200000a4
|
|
8017d90: e000ed04 .word 0xe000ed04
|
|
|
|
08017d94 <vPortExitCritical>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
8017d94: b480 push {r7}
|
|
8017d96: b083 sub sp, #12
|
|
8017d98: af00 add r7, sp, #0
|
|
configASSERT( uxCriticalNesting );
|
|
8017d9a: 4b12 ldr r3, [pc, #72] @ (8017de4 <vPortExitCritical+0x50>)
|
|
8017d9c: 681b ldr r3, [r3, #0]
|
|
8017d9e: 2b00 cmp r3, #0
|
|
8017da0: d10b bne.n 8017dba <vPortExitCritical+0x26>
|
|
__asm volatile
|
|
8017da2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017da6: f383 8811 msr BASEPRI, r3
|
|
8017daa: f3bf 8f6f isb sy
|
|
8017dae: f3bf 8f4f dsb sy
|
|
8017db2: 607b str r3, [r7, #4]
|
|
}
|
|
8017db4: bf00 nop
|
|
8017db6: bf00 nop
|
|
8017db8: e7fd b.n 8017db6 <vPortExitCritical+0x22>
|
|
uxCriticalNesting--;
|
|
8017dba: 4b0a ldr r3, [pc, #40] @ (8017de4 <vPortExitCritical+0x50>)
|
|
8017dbc: 681b ldr r3, [r3, #0]
|
|
8017dbe: 3b01 subs r3, #1
|
|
8017dc0: 4a08 ldr r2, [pc, #32] @ (8017de4 <vPortExitCritical+0x50>)
|
|
8017dc2: 6013 str r3, [r2, #0]
|
|
|
|
if( uxCriticalNesting == 0 )
|
|
8017dc4: 4b07 ldr r3, [pc, #28] @ (8017de4 <vPortExitCritical+0x50>)
|
|
8017dc6: 681b ldr r3, [r3, #0]
|
|
8017dc8: 2b00 cmp r3, #0
|
|
8017dca: d105 bne.n 8017dd8 <vPortExitCritical+0x44>
|
|
8017dcc: 2300 movs r3, #0
|
|
8017dce: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
8017dd0: 683b ldr r3, [r7, #0]
|
|
8017dd2: f383 8811 msr BASEPRI, r3
|
|
}
|
|
8017dd6: bf00 nop
|
|
{
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
}
|
|
8017dd8: bf00 nop
|
|
8017dda: 370c adds r7, #12
|
|
8017ddc: 46bd mov sp, r7
|
|
8017dde: f85d 7b04 ldr.w r7, [sp], #4
|
|
8017de2: 4770 bx lr
|
|
8017de4: 200000a4 .word 0x200000a4
|
|
...
|
|
|
|
08017df0 <PendSV_Handler>:
|
|
|
|
void xPortPendSVHandler( void )
|
|
{
|
|
/* This is a naked function. */
|
|
|
|
__asm volatile
|
|
8017df0: f3ef 8009 mrs r0, PSP
|
|
8017df4: f3bf 8f6f isb sy
|
|
8017df8: 4b15 ldr r3, [pc, #84] @ (8017e50 <pxCurrentTCBConst>)
|
|
8017dfa: 681a ldr r2, [r3, #0]
|
|
8017dfc: f01e 0f10 tst.w lr, #16
|
|
8017e00: bf08 it eq
|
|
8017e02: ed20 8a10 vstmdbeq r0!, {s16-s31}
|
|
8017e06: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8017e0a: 6010 str r0, [r2, #0]
|
|
8017e0c: b409 push {r0, r3}
|
|
8017e0e: f04f 0050 mov.w r0, #80 @ 0x50
|
|
8017e12: f380 8811 msr BASEPRI, r0
|
|
8017e16: f3bf 8f4f dsb sy
|
|
8017e1a: f3bf 8f6f isb sy
|
|
8017e1e: f7fe f941 bl 80160a4 <vTaskSwitchContext>
|
|
8017e22: f04f 0000 mov.w r0, #0
|
|
8017e26: f380 8811 msr BASEPRI, r0
|
|
8017e2a: bc09 pop {r0, r3}
|
|
8017e2c: 6819 ldr r1, [r3, #0]
|
|
8017e2e: 6808 ldr r0, [r1, #0]
|
|
8017e30: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8017e34: f01e 0f10 tst.w lr, #16
|
|
8017e38: bf08 it eq
|
|
8017e3a: ecb0 8a10 vldmiaeq r0!, {s16-s31}
|
|
8017e3e: f380 8809 msr PSP, r0
|
|
8017e42: f3bf 8f6f isb sy
|
|
8017e46: 4770 bx lr
|
|
8017e48: f3af 8000 nop.w
|
|
8017e4c: f3af 8000 nop.w
|
|
|
|
08017e50 <pxCurrentTCBConst>:
|
|
8017e50: 20002168 .word 0x20002168
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
|
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
|
|
);
|
|
}
|
|
8017e54: bf00 nop
|
|
8017e56: bf00 nop
|
|
|
|
08017e58 <xPortSysTickHandler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void xPortSysTickHandler( void )
|
|
{
|
|
8017e58: b580 push {r7, lr}
|
|
8017e5a: b082 sub sp, #8
|
|
8017e5c: af00 add r7, sp, #0
|
|
__asm volatile
|
|
8017e5e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017e62: f383 8811 msr BASEPRI, r3
|
|
8017e66: f3bf 8f6f isb sy
|
|
8017e6a: f3bf 8f4f dsb sy
|
|
8017e6e: 607b str r3, [r7, #4]
|
|
}
|
|
8017e70: bf00 nop
|
|
* save and then restore the interrupt mask value as its value is already
|
|
* known. */
|
|
portDISABLE_INTERRUPTS();
|
|
{
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
8017e72: f7fd ffff bl 8015e74 <xTaskIncrementTick>
|
|
8017e76: 4603 mov r3, r0
|
|
8017e78: 2b00 cmp r3, #0
|
|
8017e7a: d003 beq.n 8017e84 <xPortSysTickHandler+0x2c>
|
|
{
|
|
/* A context switch is required. Context switching is performed in
|
|
* the PendSV interrupt. Pend the PendSV interrupt. */
|
|
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
|
8017e7c: 4b06 ldr r3, [pc, #24] @ (8017e98 <xPortSysTickHandler+0x40>)
|
|
8017e7e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8017e82: 601a str r2, [r3, #0]
|
|
8017e84: 2300 movs r3, #0
|
|
8017e86: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
8017e88: 683b ldr r3, [r7, #0]
|
|
8017e8a: f383 8811 msr BASEPRI, r3
|
|
}
|
|
8017e8e: bf00 nop
|
|
}
|
|
}
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
8017e90: bf00 nop
|
|
8017e92: 3708 adds r7, #8
|
|
8017e94: 46bd mov sp, r7
|
|
8017e96: bd80 pop {r7, pc}
|
|
8017e98: e000ed04 .word 0xe000ed04
|
|
|
|
08017e9c <vPortSetupTimerInterrupt>:
|
|
/*
|
|
* Setup the systick timer to generate the tick interrupts at the required
|
|
* frequency.
|
|
*/
|
|
__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
|
|
{
|
|
8017e9c: b480 push {r7}
|
|
8017e9e: af00 add r7, sp, #0
|
|
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
|
|
}
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
|
|
/* Stop and clear the SysTick. */
|
|
portNVIC_SYSTICK_CTRL_REG = 0UL;
|
|
8017ea0: 4b0b ldr r3, [pc, #44] @ (8017ed0 <vPortSetupTimerInterrupt+0x34>)
|
|
8017ea2: 2200 movs r2, #0
|
|
8017ea4: 601a str r2, [r3, #0]
|
|
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
8017ea6: 4b0b ldr r3, [pc, #44] @ (8017ed4 <vPortSetupTimerInterrupt+0x38>)
|
|
8017ea8: 2200 movs r2, #0
|
|
8017eaa: 601a str r2, [r3, #0]
|
|
|
|
/* Configure SysTick to interrupt at the requested rate. */
|
|
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
|
8017eac: 4b0a ldr r3, [pc, #40] @ (8017ed8 <vPortSetupTimerInterrupt+0x3c>)
|
|
8017eae: 681b ldr r3, [r3, #0]
|
|
8017eb0: 4a0a ldr r2, [pc, #40] @ (8017edc <vPortSetupTimerInterrupt+0x40>)
|
|
8017eb2: fba2 2303 umull r2, r3, r2, r3
|
|
8017eb6: 099b lsrs r3, r3, #6
|
|
8017eb8: 4a09 ldr r2, [pc, #36] @ (8017ee0 <vPortSetupTimerInterrupt+0x44>)
|
|
8017eba: 3b01 subs r3, #1
|
|
8017ebc: 6013 str r3, [r2, #0]
|
|
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
|
|
8017ebe: 4b04 ldr r3, [pc, #16] @ (8017ed0 <vPortSetupTimerInterrupt+0x34>)
|
|
8017ec0: 2207 movs r2, #7
|
|
8017ec2: 601a str r2, [r3, #0]
|
|
}
|
|
8017ec4: bf00 nop
|
|
8017ec6: 46bd mov sp, r7
|
|
8017ec8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8017ecc: 4770 bx lr
|
|
8017ece: bf00 nop
|
|
8017ed0: e000e010 .word 0xe000e010
|
|
8017ed4: e000e018 .word 0xe000e018
|
|
8017ed8: 2000000c .word 0x2000000c
|
|
8017edc: 10624dd3 .word 0x10624dd3
|
|
8017ee0: e000e014 .word 0xe000e014
|
|
|
|
08017ee4 <vPortEnableVFP>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/* This is a naked function. */
|
|
static void vPortEnableVFP( void )
|
|
{
|
|
__asm volatile
|
|
8017ee4: f8df 000c ldr.w r0, [pc, #12] @ 8017ef4 <vPortEnableVFP+0x10>
|
|
8017ee8: 6801 ldr r1, [r0, #0]
|
|
8017eea: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
8017eee: 6001 str r1, [r0, #0]
|
|
8017ef0: 4770 bx lr
|
|
8017ef2: 0000 .short 0x0000
|
|
8017ef4: e000ed88 .word 0xe000ed88
|
|
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
|
|
" str r1, [r0] \n"
|
|
" bx r14 \n"
|
|
" .ltorg \n"
|
|
);
|
|
}
|
|
8017ef8: bf00 nop
|
|
8017efa: bf00 nop
|
|
|
|
08017efc <vPortValidateInterruptPriority>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
8017efc: b480 push {r7}
|
|
8017efe: b085 sub sp, #20
|
|
8017f00: af00 add r7, sp, #0
|
|
uint32_t ulCurrentInterrupt;
|
|
uint8_t ucCurrentPriority;
|
|
|
|
/* Obtain the number of the currently executing interrupt. */
|
|
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
|
|
8017f02: f3ef 8305 mrs r3, IPSR
|
|
8017f06: 60fb str r3, [r7, #12]
|
|
|
|
/* Is the interrupt number a user defined interrupt? */
|
|
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
|
|
8017f08: 68fb ldr r3, [r7, #12]
|
|
8017f0a: 2b0f cmp r3, #15
|
|
8017f0c: d915 bls.n 8017f3a <vPortValidateInterruptPriority+0x3e>
|
|
{
|
|
/* Look up the interrupt's priority. */
|
|
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
|
8017f0e: 4a18 ldr r2, [pc, #96] @ (8017f70 <vPortValidateInterruptPriority+0x74>)
|
|
8017f10: 68fb ldr r3, [r7, #12]
|
|
8017f12: 4413 add r3, r2
|
|
8017f14: 781b ldrb r3, [r3, #0]
|
|
8017f16: 72fb strb r3, [r7, #11]
|
|
* interrupt entry is as fast and simple as possible.
|
|
*
|
|
* The following links provide detailed information:
|
|
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
|
|
* https://www.FreeRTOS.org/FAQHelp.html */
|
|
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
|
8017f18: 4b16 ldr r3, [pc, #88] @ (8017f74 <vPortValidateInterruptPriority+0x78>)
|
|
8017f1a: 781b ldrb r3, [r3, #0]
|
|
8017f1c: 7afa ldrb r2, [r7, #11]
|
|
8017f1e: 429a cmp r2, r3
|
|
8017f20: d20b bcs.n 8017f3a <vPortValidateInterruptPriority+0x3e>
|
|
__asm volatile
|
|
8017f22: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017f26: f383 8811 msr BASEPRI, r3
|
|
8017f2a: f3bf 8f6f isb sy
|
|
8017f2e: f3bf 8f4f dsb sy
|
|
8017f32: 607b str r3, [r7, #4]
|
|
}
|
|
8017f34: bf00 nop
|
|
8017f36: bf00 nop
|
|
8017f38: e7fd b.n 8017f36 <vPortValidateInterruptPriority+0x3a>
|
|
* configuration then the correct setting can be achieved on all Cortex-M
|
|
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
|
* scheduler. Note however that some vendor specific peripheral libraries
|
|
* assume a non-zero priority group setting, in which cases using a value
|
|
* of zero will result in unpredictable behaviour. */
|
|
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
|
8017f3a: 4b0f ldr r3, [pc, #60] @ (8017f78 <vPortValidateInterruptPriority+0x7c>)
|
|
8017f3c: 681b ldr r3, [r3, #0]
|
|
8017f3e: f403 62e0 and.w r2, r3, #1792 @ 0x700
|
|
8017f42: 4b0e ldr r3, [pc, #56] @ (8017f7c <vPortValidateInterruptPriority+0x80>)
|
|
8017f44: 681b ldr r3, [r3, #0]
|
|
8017f46: 429a cmp r2, r3
|
|
8017f48: d90b bls.n 8017f62 <vPortValidateInterruptPriority+0x66>
|
|
__asm volatile
|
|
8017f4a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8017f4e: f383 8811 msr BASEPRI, r3
|
|
8017f52: f3bf 8f6f isb sy
|
|
8017f56: f3bf 8f4f dsb sy
|
|
8017f5a: 603b str r3, [r7, #0]
|
|
}
|
|
8017f5c: bf00 nop
|
|
8017f5e: bf00 nop
|
|
8017f60: e7fd b.n 8017f5e <vPortValidateInterruptPriority+0x62>
|
|
}
|
|
8017f62: bf00 nop
|
|
8017f64: 3714 adds r7, #20
|
|
8017f66: 46bd mov sp, r7
|
|
8017f68: f85d 7b04 ldr.w r7, [sp], #4
|
|
8017f6c: 4770 bx lr
|
|
8017f6e: bf00 nop
|
|
8017f70: e000e3f0 .word 0xe000e3f0
|
|
8017f74: 20002794 .word 0x20002794
|
|
8017f78: e000ed0c .word 0xe000ed0c
|
|
8017f7c: 20002798 .word 0x20002798
|
|
|
|
08017f80 <pvPortMalloc>:
|
|
PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void * pvPortMalloc( size_t xWantedSize )
|
|
{
|
|
8017f80: b580 push {r7, lr}
|
|
8017f82: b08a sub sp, #40 @ 0x28
|
|
8017f84: af00 add r7, sp, #0
|
|
8017f86: 6078 str r0, [r7, #4]
|
|
BlockLink_t * pxBlock;
|
|
BlockLink_t * pxPreviousBlock;
|
|
BlockLink_t * pxNewBlockLink;
|
|
void * pvReturn = NULL;
|
|
8017f88: 2300 movs r3, #0
|
|
8017f8a: 61fb str r3, [r7, #28]
|
|
size_t xAdditionalRequiredSize;
|
|
|
|
vTaskSuspendAll();
|
|
8017f8c: f7fd fe4a bl 8015c24 <vTaskSuspendAll>
|
|
{
|
|
/* If this is the first call to malloc then the heap will require
|
|
* initialisation to setup the list of free blocks. */
|
|
if( pxEnd == NULL )
|
|
8017f90: 4b5c ldr r3, [pc, #368] @ (8018104 <pvPortMalloc+0x184>)
|
|
8017f92: 681b ldr r3, [r3, #0]
|
|
8017f94: 2b00 cmp r3, #0
|
|
8017f96: d101 bne.n 8017f9c <pvPortMalloc+0x1c>
|
|
{
|
|
prvHeapInit();
|
|
8017f98: f000 f918 bl 80181cc <prvHeapInit>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( xWantedSize > 0 )
|
|
8017f9c: 687b ldr r3, [r7, #4]
|
|
8017f9e: 2b00 cmp r3, #0
|
|
8017fa0: d022 beq.n 8017fe8 <pvPortMalloc+0x68>
|
|
{
|
|
/* The wanted size must be increased so it can contain a BlockLink_t
|
|
* structure in addition to the requested amount of bytes. */
|
|
if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
|
|
8017fa2: 2308 movs r3, #8
|
|
8017fa4: 43db mvns r3, r3
|
|
8017fa6: 687a ldr r2, [r7, #4]
|
|
8017fa8: 429a cmp r2, r3
|
|
8017faa: d81b bhi.n 8017fe4 <pvPortMalloc+0x64>
|
|
{
|
|
xWantedSize += xHeapStructSize;
|
|
8017fac: 2208 movs r2, #8
|
|
8017fae: 687b ldr r3, [r7, #4]
|
|
8017fb0: 4413 add r3, r2
|
|
8017fb2: 607b str r3, [r7, #4]
|
|
|
|
/* Ensure that blocks are always aligned to the required number
|
|
* of bytes. */
|
|
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
|
|
8017fb4: 687b ldr r3, [r7, #4]
|
|
8017fb6: f003 0307 and.w r3, r3, #7
|
|
8017fba: 2b00 cmp r3, #0
|
|
8017fbc: d014 beq.n 8017fe8 <pvPortMalloc+0x68>
|
|
{
|
|
/* Byte alignment required. */
|
|
xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
|
|
8017fbe: 687b ldr r3, [r7, #4]
|
|
8017fc0: f003 0307 and.w r3, r3, #7
|
|
8017fc4: f1c3 0308 rsb r3, r3, #8
|
|
8017fc8: 61bb str r3, [r7, #24]
|
|
|
|
if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
|
|
8017fca: 69bb ldr r3, [r7, #24]
|
|
8017fcc: 43db mvns r3, r3
|
|
8017fce: 687a ldr r2, [r7, #4]
|
|
8017fd0: 429a cmp r2, r3
|
|
8017fd2: d804 bhi.n 8017fde <pvPortMalloc+0x5e>
|
|
{
|
|
xWantedSize += xAdditionalRequiredSize;
|
|
8017fd4: 687a ldr r2, [r7, #4]
|
|
8017fd6: 69bb ldr r3, [r7, #24]
|
|
8017fd8: 4413 add r3, r2
|
|
8017fda: 607b str r3, [r7, #4]
|
|
8017fdc: e004 b.n 8017fe8 <pvPortMalloc+0x68>
|
|
}
|
|
else
|
|
{
|
|
xWantedSize = 0;
|
|
8017fde: 2300 movs r3, #0
|
|
8017fe0: 607b str r3, [r7, #4]
|
|
8017fe2: e001 b.n 8017fe8 <pvPortMalloc+0x68>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
xWantedSize = 0;
|
|
8017fe4: 2300 movs r3, #0
|
|
8017fe6: 607b str r3, [r7, #4]
|
|
|
|
/* Check the block size we are trying to allocate is not so large that the
|
|
* top bit is set. The top bit of the block size member of the BlockLink_t
|
|
* structure is used to determine who owns the block - the application or
|
|
* the kernel, so it must be free. */
|
|
if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
|
|
8017fe8: 687b ldr r3, [r7, #4]
|
|
8017fea: 2b00 cmp r3, #0
|
|
8017fec: db71 blt.n 80180d2 <pvPortMalloc+0x152>
|
|
{
|
|
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
|
|
8017fee: 687b ldr r3, [r7, #4]
|
|
8017ff0: 2b00 cmp r3, #0
|
|
8017ff2: d06e beq.n 80180d2 <pvPortMalloc+0x152>
|
|
8017ff4: 4b44 ldr r3, [pc, #272] @ (8018108 <pvPortMalloc+0x188>)
|
|
8017ff6: 681b ldr r3, [r3, #0]
|
|
8017ff8: 687a ldr r2, [r7, #4]
|
|
8017ffa: 429a cmp r2, r3
|
|
8017ffc: d869 bhi.n 80180d2 <pvPortMalloc+0x152>
|
|
{
|
|
/* Traverse the list from the start (lowest address) block until
|
|
* one of adequate size is found. */
|
|
pxPreviousBlock = &xStart;
|
|
8017ffe: 4b43 ldr r3, [pc, #268] @ (801810c <pvPortMalloc+0x18c>)
|
|
8018000: 623b str r3, [r7, #32]
|
|
pxBlock = xStart.pxNextFreeBlock;
|
|
8018002: 4b42 ldr r3, [pc, #264] @ (801810c <pvPortMalloc+0x18c>)
|
|
8018004: 681b ldr r3, [r3, #0]
|
|
8018006: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
|
8018008: e004 b.n 8018014 <pvPortMalloc+0x94>
|
|
{
|
|
pxPreviousBlock = pxBlock;
|
|
801800a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801800c: 623b str r3, [r7, #32]
|
|
pxBlock = pxBlock->pxNextFreeBlock;
|
|
801800e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8018010: 681b ldr r3, [r3, #0]
|
|
8018012: 627b str r3, [r7, #36] @ 0x24
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
|
8018014: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8018016: 685b ldr r3, [r3, #4]
|
|
8018018: 687a ldr r2, [r7, #4]
|
|
801801a: 429a cmp r2, r3
|
|
801801c: d903 bls.n 8018026 <pvPortMalloc+0xa6>
|
|
801801e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8018020: 681b ldr r3, [r3, #0]
|
|
8018022: 2b00 cmp r3, #0
|
|
8018024: d1f1 bne.n 801800a <pvPortMalloc+0x8a>
|
|
}
|
|
|
|
/* If the end marker was reached then a block of adequate size
|
|
* was not found. */
|
|
if( pxBlock != pxEnd )
|
|
8018026: 4b37 ldr r3, [pc, #220] @ (8018104 <pvPortMalloc+0x184>)
|
|
8018028: 681b ldr r3, [r3, #0]
|
|
801802a: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
801802c: 429a cmp r2, r3
|
|
801802e: d050 beq.n 80180d2 <pvPortMalloc+0x152>
|
|
{
|
|
/* Return the memory space pointed to - jumping over the
|
|
* BlockLink_t structure at its start. */
|
|
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
|
|
8018030: 6a3b ldr r3, [r7, #32]
|
|
8018032: 681b ldr r3, [r3, #0]
|
|
8018034: 2208 movs r2, #8
|
|
8018036: 4413 add r3, r2
|
|
8018038: 61fb str r3, [r7, #28]
|
|
|
|
/* This block is being returned for use so must be taken out
|
|
* of the list of free blocks. */
|
|
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
|
|
801803a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801803c: 681a ldr r2, [r3, #0]
|
|
801803e: 6a3b ldr r3, [r7, #32]
|
|
8018040: 601a str r2, [r3, #0]
|
|
|
|
/* If the block is larger than required it can be split into
|
|
* two. */
|
|
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
|
|
8018042: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8018044: 685a ldr r2, [r3, #4]
|
|
8018046: 687b ldr r3, [r7, #4]
|
|
8018048: 1ad2 subs r2, r2, r3
|
|
801804a: 2308 movs r3, #8
|
|
801804c: 005b lsls r3, r3, #1
|
|
801804e: 429a cmp r2, r3
|
|
8018050: d920 bls.n 8018094 <pvPortMalloc+0x114>
|
|
{
|
|
/* This block is to be split into two. Create a new
|
|
* block following the number of bytes requested. The void
|
|
* cast is used to prevent byte alignment warnings from the
|
|
* compiler. */
|
|
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
|
|
8018052: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8018054: 687b ldr r3, [r7, #4]
|
|
8018056: 4413 add r3, r2
|
|
8018058: 617b str r3, [r7, #20]
|
|
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
801805a: 697b ldr r3, [r7, #20]
|
|
801805c: f003 0307 and.w r3, r3, #7
|
|
8018060: 2b00 cmp r3, #0
|
|
8018062: d00b beq.n 801807c <pvPortMalloc+0xfc>
|
|
__asm volatile
|
|
8018064: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8018068: f383 8811 msr BASEPRI, r3
|
|
801806c: f3bf 8f6f isb sy
|
|
8018070: f3bf 8f4f dsb sy
|
|
8018074: 613b str r3, [r7, #16]
|
|
}
|
|
8018076: bf00 nop
|
|
8018078: bf00 nop
|
|
801807a: e7fd b.n 8018078 <pvPortMalloc+0xf8>
|
|
|
|
/* Calculate the sizes of two blocks split from the
|
|
* single block. */
|
|
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
|
|
801807c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801807e: 685a ldr r2, [r3, #4]
|
|
8018080: 687b ldr r3, [r7, #4]
|
|
8018082: 1ad2 subs r2, r2, r3
|
|
8018084: 697b ldr r3, [r7, #20]
|
|
8018086: 605a str r2, [r3, #4]
|
|
pxBlock->xBlockSize = xWantedSize;
|
|
8018088: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801808a: 687a ldr r2, [r7, #4]
|
|
801808c: 605a str r2, [r3, #4]
|
|
|
|
/* Insert the new block into the list of free blocks. */
|
|
prvInsertBlockIntoFreeList( pxNewBlockLink );
|
|
801808e: 6978 ldr r0, [r7, #20]
|
|
8018090: f000 f8f8 bl 8018284 <prvInsertBlockIntoFreeList>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
xFreeBytesRemaining -= pxBlock->xBlockSize;
|
|
8018094: 4b1c ldr r3, [pc, #112] @ (8018108 <pvPortMalloc+0x188>)
|
|
8018096: 681a ldr r2, [r3, #0]
|
|
8018098: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
801809a: 685b ldr r3, [r3, #4]
|
|
801809c: 1ad3 subs r3, r2, r3
|
|
801809e: 4a1a ldr r2, [pc, #104] @ (8018108 <pvPortMalloc+0x188>)
|
|
80180a0: 6013 str r3, [r2, #0]
|
|
|
|
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
|
|
80180a2: 4b19 ldr r3, [pc, #100] @ (8018108 <pvPortMalloc+0x188>)
|
|
80180a4: 681a ldr r2, [r3, #0]
|
|
80180a6: 4b1a ldr r3, [pc, #104] @ (8018110 <pvPortMalloc+0x190>)
|
|
80180a8: 681b ldr r3, [r3, #0]
|
|
80180aa: 429a cmp r2, r3
|
|
80180ac: d203 bcs.n 80180b6 <pvPortMalloc+0x136>
|
|
{
|
|
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
|
|
80180ae: 4b16 ldr r3, [pc, #88] @ (8018108 <pvPortMalloc+0x188>)
|
|
80180b0: 681b ldr r3, [r3, #0]
|
|
80180b2: 4a17 ldr r2, [pc, #92] @ (8018110 <pvPortMalloc+0x190>)
|
|
80180b4: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* The block is being returned - it is allocated and owned
|
|
* by the application and has no "next" block. */
|
|
heapALLOCATE_BLOCK( pxBlock );
|
|
80180b6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80180b8: 685b ldr r3, [r3, #4]
|
|
80180ba: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
|
|
80180be: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80180c0: 605a str r2, [r3, #4]
|
|
pxBlock->pxNextFreeBlock = NULL;
|
|
80180c2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80180c4: 2200 movs r2, #0
|
|
80180c6: 601a str r2, [r3, #0]
|
|
xNumberOfSuccessfulAllocations++;
|
|
80180c8: 4b12 ldr r3, [pc, #72] @ (8018114 <pvPortMalloc+0x194>)
|
|
80180ca: 681b ldr r3, [r3, #0]
|
|
80180cc: 3301 adds r3, #1
|
|
80180ce: 4a11 ldr r2, [pc, #68] @ (8018114 <pvPortMalloc+0x194>)
|
|
80180d0: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
traceMALLOC( pvReturn, xWantedSize );
|
|
}
|
|
( void ) xTaskResumeAll();
|
|
80180d2: f7fd fdb5 bl 8015c40 <xTaskResumeAll>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
|
|
|
|
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
80180d6: 69fb ldr r3, [r7, #28]
|
|
80180d8: f003 0307 and.w r3, r3, #7
|
|
80180dc: 2b00 cmp r3, #0
|
|
80180de: d00b beq.n 80180f8 <pvPortMalloc+0x178>
|
|
__asm volatile
|
|
80180e0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80180e4: f383 8811 msr BASEPRI, r3
|
|
80180e8: f3bf 8f6f isb sy
|
|
80180ec: f3bf 8f4f dsb sy
|
|
80180f0: 60fb str r3, [r7, #12]
|
|
}
|
|
80180f2: bf00 nop
|
|
80180f4: bf00 nop
|
|
80180f6: e7fd b.n 80180f4 <pvPortMalloc+0x174>
|
|
return pvReturn;
|
|
80180f8: 69fb ldr r3, [r7, #28]
|
|
}
|
|
80180fa: 4618 mov r0, r3
|
|
80180fc: 3728 adds r7, #40 @ 0x28
|
|
80180fe: 46bd mov sp, r7
|
|
8018100: bd80 pop {r7, pc}
|
|
8018102: bf00 nop
|
|
8018104: 200121a4 .word 0x200121a4
|
|
8018108: 200121a8 .word 0x200121a8
|
|
801810c: 2001219c .word 0x2001219c
|
|
8018110: 200121ac .word 0x200121ac
|
|
8018114: 200121b0 .word 0x200121b0
|
|
|
|
08018118 <vPortFree>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortFree( void * pv )
|
|
{
|
|
8018118: b580 push {r7, lr}
|
|
801811a: b086 sub sp, #24
|
|
801811c: af00 add r7, sp, #0
|
|
801811e: 6078 str r0, [r7, #4]
|
|
uint8_t * puc = ( uint8_t * ) pv;
|
|
8018120: 687b ldr r3, [r7, #4]
|
|
8018122: 617b str r3, [r7, #20]
|
|
BlockLink_t * pxLink;
|
|
|
|
if( pv != NULL )
|
|
8018124: 687b ldr r3, [r7, #4]
|
|
8018126: 2b00 cmp r3, #0
|
|
8018128: d047 beq.n 80181ba <vPortFree+0xa2>
|
|
{
|
|
/* The memory being freed will have an BlockLink_t structure immediately
|
|
* before it. */
|
|
puc -= xHeapStructSize;
|
|
801812a: 2308 movs r3, #8
|
|
801812c: 425b negs r3, r3
|
|
801812e: 697a ldr r2, [r7, #20]
|
|
8018130: 4413 add r3, r2
|
|
8018132: 617b str r3, [r7, #20]
|
|
|
|
/* This casting is to keep the compiler from issuing warnings. */
|
|
pxLink = ( void * ) puc;
|
|
8018134: 697b ldr r3, [r7, #20]
|
|
8018136: 613b str r3, [r7, #16]
|
|
|
|
configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
|
|
8018138: 693b ldr r3, [r7, #16]
|
|
801813a: 685b ldr r3, [r3, #4]
|
|
801813c: 2b00 cmp r3, #0
|
|
801813e: db0b blt.n 8018158 <vPortFree+0x40>
|
|
__asm volatile
|
|
8018140: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8018144: f383 8811 msr BASEPRI, r3
|
|
8018148: f3bf 8f6f isb sy
|
|
801814c: f3bf 8f4f dsb sy
|
|
8018150: 60fb str r3, [r7, #12]
|
|
}
|
|
8018152: bf00 nop
|
|
8018154: bf00 nop
|
|
8018156: e7fd b.n 8018154 <vPortFree+0x3c>
|
|
configASSERT( pxLink->pxNextFreeBlock == NULL );
|
|
8018158: 693b ldr r3, [r7, #16]
|
|
801815a: 681b ldr r3, [r3, #0]
|
|
801815c: 2b00 cmp r3, #0
|
|
801815e: d00b beq.n 8018178 <vPortFree+0x60>
|
|
__asm volatile
|
|
8018160: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8018164: f383 8811 msr BASEPRI, r3
|
|
8018168: f3bf 8f6f isb sy
|
|
801816c: f3bf 8f4f dsb sy
|
|
8018170: 60bb str r3, [r7, #8]
|
|
}
|
|
8018172: bf00 nop
|
|
8018174: bf00 nop
|
|
8018176: e7fd b.n 8018174 <vPortFree+0x5c>
|
|
|
|
if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
|
|
8018178: 693b ldr r3, [r7, #16]
|
|
801817a: 685b ldr r3, [r3, #4]
|
|
801817c: 2b00 cmp r3, #0
|
|
801817e: da1c bge.n 80181ba <vPortFree+0xa2>
|
|
{
|
|
if( pxLink->pxNextFreeBlock == NULL )
|
|
8018180: 693b ldr r3, [r7, #16]
|
|
8018182: 681b ldr r3, [r3, #0]
|
|
8018184: 2b00 cmp r3, #0
|
|
8018186: d118 bne.n 80181ba <vPortFree+0xa2>
|
|
{
|
|
/* The block is being returned to the heap - it is no longer
|
|
* allocated. */
|
|
heapFREE_BLOCK( pxLink );
|
|
8018188: 693b ldr r3, [r7, #16]
|
|
801818a: 685b ldr r3, [r3, #4]
|
|
801818c: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
|
|
8018190: 693b ldr r3, [r7, #16]
|
|
8018192: 605a str r2, [r3, #4]
|
|
{
|
|
( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
|
|
}
|
|
#endif
|
|
|
|
vTaskSuspendAll();
|
|
8018194: f7fd fd46 bl 8015c24 <vTaskSuspendAll>
|
|
{
|
|
/* Add this block to the list of free blocks. */
|
|
xFreeBytesRemaining += pxLink->xBlockSize;
|
|
8018198: 693b ldr r3, [r7, #16]
|
|
801819a: 685a ldr r2, [r3, #4]
|
|
801819c: 4b09 ldr r3, [pc, #36] @ (80181c4 <vPortFree+0xac>)
|
|
801819e: 681b ldr r3, [r3, #0]
|
|
80181a0: 4413 add r3, r2
|
|
80181a2: 4a08 ldr r2, [pc, #32] @ (80181c4 <vPortFree+0xac>)
|
|
80181a4: 6013 str r3, [r2, #0]
|
|
traceFREE( pv, pxLink->xBlockSize );
|
|
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
|
|
80181a6: 6938 ldr r0, [r7, #16]
|
|
80181a8: f000 f86c bl 8018284 <prvInsertBlockIntoFreeList>
|
|
xNumberOfSuccessfulFrees++;
|
|
80181ac: 4b06 ldr r3, [pc, #24] @ (80181c8 <vPortFree+0xb0>)
|
|
80181ae: 681b ldr r3, [r3, #0]
|
|
80181b0: 3301 adds r3, #1
|
|
80181b2: 4a05 ldr r2, [pc, #20] @ (80181c8 <vPortFree+0xb0>)
|
|
80181b4: 6013 str r3, [r2, #0]
|
|
}
|
|
( void ) xTaskResumeAll();
|
|
80181b6: f7fd fd43 bl 8015c40 <xTaskResumeAll>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
80181ba: bf00 nop
|
|
80181bc: 3718 adds r7, #24
|
|
80181be: 46bd mov sp, r7
|
|
80181c0: bd80 pop {r7, pc}
|
|
80181c2: bf00 nop
|
|
80181c4: 200121a8 .word 0x200121a8
|
|
80181c8: 200121b4 .word 0x200121b4
|
|
|
|
080181cc <prvHeapInit>:
|
|
return pv;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
|
|
{
|
|
80181cc: b480 push {r7}
|
|
80181ce: b085 sub sp, #20
|
|
80181d0: af00 add r7, sp, #0
|
|
BlockLink_t * pxFirstFreeBlock;
|
|
uint8_t * pucAlignedHeap;
|
|
portPOINTER_SIZE_TYPE uxAddress;
|
|
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
|
|
80181d2: f44f 437a mov.w r3, #64000 @ 0xfa00
|
|
80181d6: 60bb str r3, [r7, #8]
|
|
|
|
/* Ensure the heap starts on a correctly aligned boundary. */
|
|
uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;
|
|
80181d8: 4b25 ldr r3, [pc, #148] @ (8018270 <prvHeapInit+0xa4>)
|
|
80181da: 60fb str r3, [r7, #12]
|
|
|
|
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
|
|
80181dc: 68fb ldr r3, [r7, #12]
|
|
80181de: f003 0307 and.w r3, r3, #7
|
|
80181e2: 2b00 cmp r3, #0
|
|
80181e4: d00c beq.n 8018200 <prvHeapInit+0x34>
|
|
{
|
|
uxAddress += ( portBYTE_ALIGNMENT - 1 );
|
|
80181e6: 68fb ldr r3, [r7, #12]
|
|
80181e8: 3307 adds r3, #7
|
|
80181ea: 60fb str r3, [r7, #12]
|
|
uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
|
|
80181ec: 68fb ldr r3, [r7, #12]
|
|
80181ee: f023 0307 bic.w r3, r3, #7
|
|
80181f2: 60fb str r3, [r7, #12]
|
|
xTotalHeapSize -= ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap );
|
|
80181f4: 68ba ldr r2, [r7, #8]
|
|
80181f6: 68fb ldr r3, [r7, #12]
|
|
80181f8: 1ad3 subs r3, r2, r3
|
|
80181fa: 4a1d ldr r2, [pc, #116] @ (8018270 <prvHeapInit+0xa4>)
|
|
80181fc: 4413 add r3, r2
|
|
80181fe: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
pucAlignedHeap = ( uint8_t * ) uxAddress;
|
|
8018200: 68fb ldr r3, [r7, #12]
|
|
8018202: 607b str r3, [r7, #4]
|
|
|
|
/* xStart is used to hold a pointer to the first item in the list of free
|
|
* blocks. The void cast is used to prevent compiler warnings. */
|
|
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
|
|
8018204: 4a1b ldr r2, [pc, #108] @ (8018274 <prvHeapInit+0xa8>)
|
|
8018206: 687b ldr r3, [r7, #4]
|
|
8018208: 6013 str r3, [r2, #0]
|
|
xStart.xBlockSize = ( size_t ) 0;
|
|
801820a: 4b1a ldr r3, [pc, #104] @ (8018274 <prvHeapInit+0xa8>)
|
|
801820c: 2200 movs r2, #0
|
|
801820e: 605a str r2, [r3, #4]
|
|
|
|
/* pxEnd is used to mark the end of the list of free blocks and is inserted
|
|
* at the end of the heap space. */
|
|
uxAddress = ( portPOINTER_SIZE_TYPE ) ( pucAlignedHeap + xTotalHeapSize );
|
|
8018210: 687a ldr r2, [r7, #4]
|
|
8018212: 68bb ldr r3, [r7, #8]
|
|
8018214: 4413 add r3, r2
|
|
8018216: 60fb str r3, [r7, #12]
|
|
uxAddress -= xHeapStructSize;
|
|
8018218: 2208 movs r2, #8
|
|
801821a: 68fb ldr r3, [r7, #12]
|
|
801821c: 1a9b subs r3, r3, r2
|
|
801821e: 60fb str r3, [r7, #12]
|
|
uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
|
|
8018220: 68fb ldr r3, [r7, #12]
|
|
8018222: f023 0307 bic.w r3, r3, #7
|
|
8018226: 60fb str r3, [r7, #12]
|
|
pxEnd = ( BlockLink_t * ) uxAddress;
|
|
8018228: 68fb ldr r3, [r7, #12]
|
|
801822a: 4a13 ldr r2, [pc, #76] @ (8018278 <prvHeapInit+0xac>)
|
|
801822c: 6013 str r3, [r2, #0]
|
|
pxEnd->xBlockSize = 0;
|
|
801822e: 4b12 ldr r3, [pc, #72] @ (8018278 <prvHeapInit+0xac>)
|
|
8018230: 681b ldr r3, [r3, #0]
|
|
8018232: 2200 movs r2, #0
|
|
8018234: 605a str r2, [r3, #4]
|
|
pxEnd->pxNextFreeBlock = NULL;
|
|
8018236: 4b10 ldr r3, [pc, #64] @ (8018278 <prvHeapInit+0xac>)
|
|
8018238: 681b ldr r3, [r3, #0]
|
|
801823a: 2200 movs r2, #0
|
|
801823c: 601a str r2, [r3, #0]
|
|
|
|
/* To start with there is a single free block that is sized to take up the
|
|
* entire heap space, minus the space taken by pxEnd. */
|
|
pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;
|
|
801823e: 687b ldr r3, [r7, #4]
|
|
8018240: 603b str r3, [r7, #0]
|
|
pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
|
|
8018242: 683b ldr r3, [r7, #0]
|
|
8018244: 68fa ldr r2, [r7, #12]
|
|
8018246: 1ad2 subs r2, r2, r3
|
|
8018248: 683b ldr r3, [r7, #0]
|
|
801824a: 605a str r2, [r3, #4]
|
|
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
|
|
801824c: 4b0a ldr r3, [pc, #40] @ (8018278 <prvHeapInit+0xac>)
|
|
801824e: 681a ldr r2, [r3, #0]
|
|
8018250: 683b ldr r3, [r7, #0]
|
|
8018252: 601a str r2, [r3, #0]
|
|
|
|
/* Only one block exists - and it covers the entire usable heap space. */
|
|
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
|
8018254: 683b ldr r3, [r7, #0]
|
|
8018256: 685b ldr r3, [r3, #4]
|
|
8018258: 4a08 ldr r2, [pc, #32] @ (801827c <prvHeapInit+0xb0>)
|
|
801825a: 6013 str r3, [r2, #0]
|
|
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
|
801825c: 683b ldr r3, [r7, #0]
|
|
801825e: 685b ldr r3, [r3, #4]
|
|
8018260: 4a07 ldr r2, [pc, #28] @ (8018280 <prvHeapInit+0xb4>)
|
|
8018262: 6013 str r3, [r2, #0]
|
|
}
|
|
8018264: bf00 nop
|
|
8018266: 3714 adds r7, #20
|
|
8018268: 46bd mov sp, r7
|
|
801826a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801826e: 4770 bx lr
|
|
8018270: 2000279c .word 0x2000279c
|
|
8018274: 2001219c .word 0x2001219c
|
|
8018278: 200121a4 .word 0x200121a4
|
|
801827c: 200121ac .word 0x200121ac
|
|
8018280: 200121a8 .word 0x200121a8
|
|
|
|
08018284 <prvInsertBlockIntoFreeList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */
|
|
{
|
|
8018284: b480 push {r7}
|
|
8018286: b085 sub sp, #20
|
|
8018288: af00 add r7, sp, #0
|
|
801828a: 6078 str r0, [r7, #4]
|
|
BlockLink_t * pxIterator;
|
|
uint8_t * puc;
|
|
|
|
/* Iterate through the list until a block is found that has a higher address
|
|
* than the block being inserted. */
|
|
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
|
|
801828c: 4b28 ldr r3, [pc, #160] @ (8018330 <prvInsertBlockIntoFreeList+0xac>)
|
|
801828e: 60fb str r3, [r7, #12]
|
|
8018290: e002 b.n 8018298 <prvInsertBlockIntoFreeList+0x14>
|
|
8018292: 68fb ldr r3, [r7, #12]
|
|
8018294: 681b ldr r3, [r3, #0]
|
|
8018296: 60fb str r3, [r7, #12]
|
|
8018298: 68fb ldr r3, [r7, #12]
|
|
801829a: 681b ldr r3, [r3, #0]
|
|
801829c: 687a ldr r2, [r7, #4]
|
|
801829e: 429a cmp r2, r3
|
|
80182a0: d8f7 bhi.n 8018292 <prvInsertBlockIntoFreeList+0xe>
|
|
/* Nothing to do here, just iterate to the right position. */
|
|
}
|
|
|
|
/* Do the block being inserted, and the block it is being inserted after
|
|
* make a contiguous block of memory? */
|
|
puc = ( uint8_t * ) pxIterator;
|
|
80182a2: 68fb ldr r3, [r7, #12]
|
|
80182a4: 60bb str r3, [r7, #8]
|
|
|
|
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
|
|
80182a6: 68fb ldr r3, [r7, #12]
|
|
80182a8: 685b ldr r3, [r3, #4]
|
|
80182aa: 68ba ldr r2, [r7, #8]
|
|
80182ac: 4413 add r3, r2
|
|
80182ae: 687a ldr r2, [r7, #4]
|
|
80182b0: 429a cmp r2, r3
|
|
80182b2: d108 bne.n 80182c6 <prvInsertBlockIntoFreeList+0x42>
|
|
{
|
|
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
|
|
80182b4: 68fb ldr r3, [r7, #12]
|
|
80182b6: 685a ldr r2, [r3, #4]
|
|
80182b8: 687b ldr r3, [r7, #4]
|
|
80182ba: 685b ldr r3, [r3, #4]
|
|
80182bc: 441a add r2, r3
|
|
80182be: 68fb ldr r3, [r7, #12]
|
|
80182c0: 605a str r2, [r3, #4]
|
|
pxBlockToInsert = pxIterator;
|
|
80182c2: 68fb ldr r3, [r7, #12]
|
|
80182c4: 607b str r3, [r7, #4]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Do the block being inserted, and the block it is being inserted before
|
|
* make a contiguous block of memory? */
|
|
puc = ( uint8_t * ) pxBlockToInsert;
|
|
80182c6: 687b ldr r3, [r7, #4]
|
|
80182c8: 60bb str r3, [r7, #8]
|
|
|
|
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
|
|
80182ca: 687b ldr r3, [r7, #4]
|
|
80182cc: 685b ldr r3, [r3, #4]
|
|
80182ce: 68ba ldr r2, [r7, #8]
|
|
80182d0: 441a add r2, r3
|
|
80182d2: 68fb ldr r3, [r7, #12]
|
|
80182d4: 681b ldr r3, [r3, #0]
|
|
80182d6: 429a cmp r2, r3
|
|
80182d8: d118 bne.n 801830c <prvInsertBlockIntoFreeList+0x88>
|
|
{
|
|
if( pxIterator->pxNextFreeBlock != pxEnd )
|
|
80182da: 68fb ldr r3, [r7, #12]
|
|
80182dc: 681a ldr r2, [r3, #0]
|
|
80182de: 4b15 ldr r3, [pc, #84] @ (8018334 <prvInsertBlockIntoFreeList+0xb0>)
|
|
80182e0: 681b ldr r3, [r3, #0]
|
|
80182e2: 429a cmp r2, r3
|
|
80182e4: d00d beq.n 8018302 <prvInsertBlockIntoFreeList+0x7e>
|
|
{
|
|
/* Form one big block from the two blocks. */
|
|
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
|
|
80182e6: 687b ldr r3, [r7, #4]
|
|
80182e8: 685a ldr r2, [r3, #4]
|
|
80182ea: 68fb ldr r3, [r7, #12]
|
|
80182ec: 681b ldr r3, [r3, #0]
|
|
80182ee: 685b ldr r3, [r3, #4]
|
|
80182f0: 441a add r2, r3
|
|
80182f2: 687b ldr r3, [r7, #4]
|
|
80182f4: 605a str r2, [r3, #4]
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
|
|
80182f6: 68fb ldr r3, [r7, #12]
|
|
80182f8: 681b ldr r3, [r3, #0]
|
|
80182fa: 681a ldr r2, [r3, #0]
|
|
80182fc: 687b ldr r3, [r7, #4]
|
|
80182fe: 601a str r2, [r3, #0]
|
|
8018300: e008 b.n 8018314 <prvInsertBlockIntoFreeList+0x90>
|
|
}
|
|
else
|
|
{
|
|
pxBlockToInsert->pxNextFreeBlock = pxEnd;
|
|
8018302: 4b0c ldr r3, [pc, #48] @ (8018334 <prvInsertBlockIntoFreeList+0xb0>)
|
|
8018304: 681a ldr r2, [r3, #0]
|
|
8018306: 687b ldr r3, [r7, #4]
|
|
8018308: 601a str r2, [r3, #0]
|
|
801830a: e003 b.n 8018314 <prvInsertBlockIntoFreeList+0x90>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
|
|
801830c: 68fb ldr r3, [r7, #12]
|
|
801830e: 681a ldr r2, [r3, #0]
|
|
8018310: 687b ldr r3, [r7, #4]
|
|
8018312: 601a str r2, [r3, #0]
|
|
|
|
/* If the block being inserted plugged a gab, so was merged with the block
|
|
* before and the block after, then it's pxNextFreeBlock pointer will have
|
|
* already been set, and should not be set here as that would make it point
|
|
* to itself. */
|
|
if( pxIterator != pxBlockToInsert )
|
|
8018314: 68fa ldr r2, [r7, #12]
|
|
8018316: 687b ldr r3, [r7, #4]
|
|
8018318: 429a cmp r2, r3
|
|
801831a: d002 beq.n 8018322 <prvInsertBlockIntoFreeList+0x9e>
|
|
{
|
|
pxIterator->pxNextFreeBlock = pxBlockToInsert;
|
|
801831c: 68fb ldr r3, [r7, #12]
|
|
801831e: 687a ldr r2, [r7, #4]
|
|
8018320: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
8018322: bf00 nop
|
|
8018324: 3714 adds r7, #20
|
|
8018326: 46bd mov sp, r7
|
|
8018328: f85d 7b04 ldr.w r7, [sp], #4
|
|
801832c: 4770 bx lr
|
|
801832e: bf00 nop
|
|
8018330: 2001219c .word 0x2001219c
|
|
8018334: 200121a4 .word 0x200121a4
|
|
|
|
08018338 <LL_PWR_EnableBootC2>:
|
|
{
|
|
8018338: b480 push {r7}
|
|
801833a: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR4, PWR_CR4_C2BOOT);
|
|
801833c: 4b05 ldr r3, [pc, #20] @ (8018354 <LL_PWR_EnableBootC2+0x1c>)
|
|
801833e: 68db ldr r3, [r3, #12]
|
|
8018340: 4a04 ldr r2, [pc, #16] @ (8018354 <LL_PWR_EnableBootC2+0x1c>)
|
|
8018342: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8018346: 60d3 str r3, [r2, #12]
|
|
}
|
|
8018348: bf00 nop
|
|
801834a: 46bd mov sp, r7
|
|
801834c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018350: 4770 bx lr
|
|
8018352: bf00 nop
|
|
8018354: 58000400 .word 0x58000400
|
|
|
|
08018358 <LL_C2_EXTI_EnableEvent_32_63>:
|
|
{
|
|
8018358: b480 push {r7}
|
|
801835a: b083 sub sp, #12
|
|
801835c: af00 add r7, sp, #0
|
|
801835e: 6078 str r0, [r7, #4]
|
|
SET_BIT(EXTI->C2EMR2, ExtiLine);
|
|
8018360: 4b06 ldr r3, [pc, #24] @ (801837c <LL_C2_EXTI_EnableEvent_32_63+0x24>)
|
|
8018362: f8d3 20d4 ldr.w r2, [r3, #212] @ 0xd4
|
|
8018366: 4905 ldr r1, [pc, #20] @ (801837c <LL_C2_EXTI_EnableEvent_32_63+0x24>)
|
|
8018368: 687b ldr r3, [r7, #4]
|
|
801836a: 4313 orrs r3, r2
|
|
801836c: f8c1 30d4 str.w r3, [r1, #212] @ 0xd4
|
|
}
|
|
8018370: bf00 nop
|
|
8018372: 370c adds r7, #12
|
|
8018374: 46bd mov sp, r7
|
|
8018376: f85d 7b04 ldr.w r7, [sp], #4
|
|
801837a: 4770 bx lr
|
|
801837c: 58000800 .word 0x58000800
|
|
|
|
08018380 <LL_EXTI_EnableRisingTrig_32_63>:
|
|
* @arg @ref LL_EXTI_LINE_41
|
|
* (*) value not defined in all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
|
|
{
|
|
8018380: b480 push {r7}
|
|
8018382: b083 sub sp, #12
|
|
8018384: af00 add r7, sp, #0
|
|
8018386: 6078 str r0, [r7, #4]
|
|
SET_BIT(EXTI->RTSR2, ExtiLine);
|
|
8018388: 4b05 ldr r3, [pc, #20] @ (80183a0 <LL_EXTI_EnableRisingTrig_32_63+0x20>)
|
|
801838a: 6a1a ldr r2, [r3, #32]
|
|
801838c: 4904 ldr r1, [pc, #16] @ (80183a0 <LL_EXTI_EnableRisingTrig_32_63+0x20>)
|
|
801838e: 687b ldr r3, [r7, #4]
|
|
8018390: 4313 orrs r3, r2
|
|
8018392: 620b str r3, [r1, #32]
|
|
}
|
|
8018394: bf00 nop
|
|
8018396: 370c adds r7, #12
|
|
8018398: 46bd mov sp, r7
|
|
801839a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801839e: 4770 bx lr
|
|
80183a0: 58000800 .word 0x58000800
|
|
|
|
080183a4 <LL_AHB3_GRP1_EnableClock>:
|
|
{
|
|
80183a4: b480 push {r7}
|
|
80183a6: b085 sub sp, #20
|
|
80183a8: af00 add r7, sp, #0
|
|
80183aa: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->AHB3ENR, Periphs);
|
|
80183ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80183b0: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
80183b2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80183b6: 687b ldr r3, [r7, #4]
|
|
80183b8: 4313 orrs r3, r2
|
|
80183ba: 650b str r3, [r1, #80] @ 0x50
|
|
tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
|
|
80183bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80183c0: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
80183c2: 687b ldr r3, [r7, #4]
|
|
80183c4: 4013 ands r3, r2
|
|
80183c6: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
80183c8: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80183ca: bf00 nop
|
|
80183cc: 3714 adds r7, #20
|
|
80183ce: 46bd mov sp, r7
|
|
80183d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80183d4: 4770 bx lr
|
|
|
|
080183d6 <LL_C2_AHB3_GRP1_EnableClock>:
|
|
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
|
|
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
80183d6: b480 push {r7}
|
|
80183d8: b085 sub sp, #20
|
|
80183da: af00 add r7, sp, #0
|
|
80183dc: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->C2AHB3ENR, Periphs);
|
|
80183de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80183e2: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150
|
|
80183e6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
80183ea: 687b ldr r3, [r7, #4]
|
|
80183ec: 4313 orrs r3, r2
|
|
80183ee: f8c1 3150 str.w r3, [r1, #336] @ 0x150
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs);
|
|
80183f2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
80183f6: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150
|
|
80183fa: 687b ldr r3, [r7, #4]
|
|
80183fc: 4013 ands r3, r2
|
|
80183fe: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8018400: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8018402: bf00 nop
|
|
8018404: 3714 adds r7, #20
|
|
8018406: 46bd mov sp, r7
|
|
8018408: f85d 7b04 ldr.w r7, [sp], #4
|
|
801840c: 4770 bx lr
|
|
|
|
0801840e <LL_C1_IPCC_EnableIT_TXF>:
|
|
* @rmtoll C1CR TXFIE LL_C1_IPCC_EnableIT_TXF
|
|
* @param IPCCx IPCC Instance.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
|
|
{
|
|
801840e: b480 push {r7}
|
|
8018410: b083 sub sp, #12
|
|
8018412: af00 add r7, sp, #0
|
|
8018414: 6078 str r0, [r7, #4]
|
|
SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
|
|
8018416: 687b ldr r3, [r7, #4]
|
|
8018418: 681b ldr r3, [r3, #0]
|
|
801841a: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
801841e: 687b ldr r3, [r7, #4]
|
|
8018420: 601a str r2, [r3, #0]
|
|
}
|
|
8018422: bf00 nop
|
|
8018424: 370c adds r7, #12
|
|
8018426: 46bd mov sp, r7
|
|
8018428: f85d 7b04 ldr.w r7, [sp], #4
|
|
801842c: 4770 bx lr
|
|
|
|
0801842e <LL_C1_IPCC_EnableIT_RXO>:
|
|
* @rmtoll C1CR RXOIE LL_C1_IPCC_EnableIT_RXO
|
|
* @param IPCCx IPCC Instance.
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
|
|
{
|
|
801842e: b480 push {r7}
|
|
8018430: b083 sub sp, #12
|
|
8018432: af00 add r7, sp, #0
|
|
8018434: 6078 str r0, [r7, #4]
|
|
SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
|
|
8018436: 687b ldr r3, [r7, #4]
|
|
8018438: 681b ldr r3, [r3, #0]
|
|
801843a: f043 0201 orr.w r2, r3, #1
|
|
801843e: 687b ldr r3, [r7, #4]
|
|
8018440: 601a str r2, [r3, #0]
|
|
}
|
|
8018442: bf00 nop
|
|
8018444: 370c adds r7, #12
|
|
8018446: 46bd mov sp, r7
|
|
8018448: f85d 7b04 ldr.w r7, [sp], #4
|
|
801844c: 4770 bx lr
|
|
|
|
0801844e <LL_C1_IPCC_EnableTransmitChannel>:
|
|
* @arg @ref LL_IPCC_CHANNEL_5
|
|
* @arg @ref LL_IPCC_CHANNEL_6
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
|
|
{
|
|
801844e: b480 push {r7}
|
|
8018450: b083 sub sp, #12
|
|
8018452: af00 add r7, sp, #0
|
|
8018454: 6078 str r0, [r7, #4]
|
|
8018456: 6039 str r1, [r7, #0]
|
|
CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
|
|
8018458: 687b ldr r3, [r7, #4]
|
|
801845a: 685a ldr r2, [r3, #4]
|
|
801845c: 683b ldr r3, [r7, #0]
|
|
801845e: 041b lsls r3, r3, #16
|
|
8018460: 43db mvns r3, r3
|
|
8018462: 401a ands r2, r3
|
|
8018464: 687b ldr r3, [r7, #4]
|
|
8018466: 605a str r2, [r3, #4]
|
|
}
|
|
8018468: bf00 nop
|
|
801846a: 370c adds r7, #12
|
|
801846c: 46bd mov sp, r7
|
|
801846e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018472: 4770 bx lr
|
|
|
|
08018474 <LL_C1_IPCC_DisableTransmitChannel>:
|
|
* @arg @ref LL_IPCC_CHANNEL_5
|
|
* @arg @ref LL_IPCC_CHANNEL_6
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
|
|
{
|
|
8018474: b480 push {r7}
|
|
8018476: b083 sub sp, #12
|
|
8018478: af00 add r7, sp, #0
|
|
801847a: 6078 str r0, [r7, #4]
|
|
801847c: 6039 str r1, [r7, #0]
|
|
SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
|
|
801847e: 687b ldr r3, [r7, #4]
|
|
8018480: 685a ldr r2, [r3, #4]
|
|
8018482: 683b ldr r3, [r7, #0]
|
|
8018484: 041b lsls r3, r3, #16
|
|
8018486: 431a orrs r2, r3
|
|
8018488: 687b ldr r3, [r7, #4]
|
|
801848a: 605a str r2, [r3, #4]
|
|
}
|
|
801848c: bf00 nop
|
|
801848e: 370c adds r7, #12
|
|
8018490: 46bd mov sp, r7
|
|
8018492: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018496: 4770 bx lr
|
|
|
|
08018498 <LL_C1_IPCC_EnableReceiveChannel>:
|
|
* @arg @ref LL_IPCC_CHANNEL_5
|
|
* @arg @ref LL_IPCC_CHANNEL_6
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
|
|
{
|
|
8018498: b480 push {r7}
|
|
801849a: b083 sub sp, #12
|
|
801849c: af00 add r7, sp, #0
|
|
801849e: 6078 str r0, [r7, #4]
|
|
80184a0: 6039 str r1, [r7, #0]
|
|
CLEAR_BIT(IPCCx->C1MR, Channel);
|
|
80184a2: 687b ldr r3, [r7, #4]
|
|
80184a4: 685a ldr r2, [r3, #4]
|
|
80184a6: 683b ldr r3, [r7, #0]
|
|
80184a8: 43db mvns r3, r3
|
|
80184aa: 401a ands r2, r3
|
|
80184ac: 687b ldr r3, [r7, #4]
|
|
80184ae: 605a str r2, [r3, #4]
|
|
}
|
|
80184b0: bf00 nop
|
|
80184b2: 370c adds r7, #12
|
|
80184b4: 46bd mov sp, r7
|
|
80184b6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80184ba: 4770 bx lr
|
|
|
|
080184bc <LL_C1_IPCC_ClearFlag_CHx>:
|
|
* @arg @ref LL_IPCC_CHANNEL_5
|
|
* @arg @ref LL_IPCC_CHANNEL_6
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
|
|
{
|
|
80184bc: b480 push {r7}
|
|
80184be: b083 sub sp, #12
|
|
80184c0: af00 add r7, sp, #0
|
|
80184c2: 6078 str r0, [r7, #4]
|
|
80184c4: 6039 str r1, [r7, #0]
|
|
WRITE_REG(IPCCx->C1SCR, Channel);
|
|
80184c6: 687b ldr r3, [r7, #4]
|
|
80184c8: 683a ldr r2, [r7, #0]
|
|
80184ca: 609a str r2, [r3, #8]
|
|
}
|
|
80184cc: bf00 nop
|
|
80184ce: 370c adds r7, #12
|
|
80184d0: 46bd mov sp, r7
|
|
80184d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80184d6: 4770 bx lr
|
|
|
|
080184d8 <LL_C1_IPCC_SetFlag_CHx>:
|
|
* @arg @ref LL_IPCC_CHANNEL_5
|
|
* @arg @ref LL_IPCC_CHANNEL_6
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
|
|
{
|
|
80184d8: b480 push {r7}
|
|
80184da: b083 sub sp, #12
|
|
80184dc: af00 add r7, sp, #0
|
|
80184de: 6078 str r0, [r7, #4]
|
|
80184e0: 6039 str r1, [r7, #0]
|
|
WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos);
|
|
80184e2: 683b ldr r3, [r7, #0]
|
|
80184e4: 041a lsls r2, r3, #16
|
|
80184e6: 687b ldr r3, [r7, #4]
|
|
80184e8: 609a str r2, [r3, #8]
|
|
}
|
|
80184ea: bf00 nop
|
|
80184ec: 370c adds r7, #12
|
|
80184ee: 46bd mov sp, r7
|
|
80184f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80184f4: 4770 bx lr
|
|
|
|
080184f6 <LL_C1_IPCC_IsActiveFlag_CHx>:
|
|
* @arg @ref LL_IPCC_CHANNEL_5
|
|
* @arg @ref LL_IPCC_CHANNEL_6
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
|
|
{
|
|
80184f6: b480 push {r7}
|
|
80184f8: b083 sub sp, #12
|
|
80184fa: af00 add r7, sp, #0
|
|
80184fc: 6078 str r0, [r7, #4]
|
|
80184fe: 6039 str r1, [r7, #0]
|
|
return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL);
|
|
8018500: 687b ldr r3, [r7, #4]
|
|
8018502: 68da ldr r2, [r3, #12]
|
|
8018504: 683b ldr r3, [r7, #0]
|
|
8018506: 4013 ands r3, r2
|
|
8018508: 683a ldr r2, [r7, #0]
|
|
801850a: 429a cmp r2, r3
|
|
801850c: d101 bne.n 8018512 <LL_C1_IPCC_IsActiveFlag_CHx+0x1c>
|
|
801850e: 2301 movs r3, #1
|
|
8018510: e000 b.n 8018514 <LL_C1_IPCC_IsActiveFlag_CHx+0x1e>
|
|
8018512: 2300 movs r3, #0
|
|
}
|
|
8018514: 4618 mov r0, r3
|
|
8018516: 370c adds r7, #12
|
|
8018518: 46bd mov sp, r7
|
|
801851a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801851e: 4770 bx lr
|
|
|
|
08018520 <LL_C2_IPCC_IsActiveFlag_CHx>:
|
|
* @arg @ref LL_IPCC_CHANNEL_5
|
|
* @arg @ref LL_IPCC_CHANNEL_6
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
|
|
{
|
|
8018520: b480 push {r7}
|
|
8018522: b083 sub sp, #12
|
|
8018524: af00 add r7, sp, #0
|
|
8018526: 6078 str r0, [r7, #4]
|
|
8018528: 6039 str r1, [r7, #0]
|
|
return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL);
|
|
801852a: 687b ldr r3, [r7, #4]
|
|
801852c: 69da ldr r2, [r3, #28]
|
|
801852e: 683b ldr r3, [r7, #0]
|
|
8018530: 4013 ands r3, r2
|
|
8018532: 683a ldr r2, [r7, #0]
|
|
8018534: 429a cmp r2, r3
|
|
8018536: d101 bne.n 801853c <LL_C2_IPCC_IsActiveFlag_CHx+0x1c>
|
|
8018538: 2301 movs r3, #1
|
|
801853a: e000 b.n 801853e <LL_C2_IPCC_IsActiveFlag_CHx+0x1e>
|
|
801853c: 2300 movs r3, #0
|
|
}
|
|
801853e: 4618 mov r0, r3
|
|
8018540: 370c adds r7, #12
|
|
8018542: 46bd mov sp, r7
|
|
8018544: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018548: 4770 bx lr
|
|
...
|
|
|
|
0801854c <HW_IPCC_Rx_Handler>:
|
|
|
|
/******************************************************************************
|
|
* INTERRUPT HANDLER
|
|
******************************************************************************/
|
|
void HW_IPCC_Rx_Handler( void )
|
|
{
|
|
801854c: b580 push {r7, lr}
|
|
801854e: af00 add r7, sp, #0
|
|
if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
|
|
8018550: 2102 movs r1, #2
|
|
8018552: 4818 ldr r0, [pc, #96] @ (80185b4 <HW_IPCC_Rx_Handler+0x68>)
|
|
8018554: f7ff ffe4 bl 8018520 <LL_C2_IPCC_IsActiveFlag_CHx>
|
|
8018558: 4603 mov r3, r0
|
|
801855a: 2b00 cmp r3, #0
|
|
801855c: d008 beq.n 8018570 <HW_IPCC_Rx_Handler+0x24>
|
|
801855e: 4b15 ldr r3, [pc, #84] @ (80185b4 <HW_IPCC_Rx_Handler+0x68>)
|
|
8018560: 685b ldr r3, [r3, #4]
|
|
8018562: f003 0302 and.w r3, r3, #2
|
|
8018566: 2b00 cmp r3, #0
|
|
8018568: d102 bne.n 8018570 <HW_IPCC_Rx_Handler+0x24>
|
|
{
|
|
HW_IPCC_SYS_EvtHandler();
|
|
801856a: f000 f901 bl 8018770 <HW_IPCC_SYS_EvtHandler>
|
|
801856e: e01e b.n 80185ae <HW_IPCC_Rx_Handler+0x62>
|
|
else if (HW_IPCC_RX_PENDING( HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL ))
|
|
{
|
|
HW_IPCC_ZIGBEE_StackM0RequestHandler();
|
|
}
|
|
#endif /* ZIGBEE_WB */
|
|
else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
|
|
8018570: 2101 movs r1, #1
|
|
8018572: 4810 ldr r0, [pc, #64] @ (80185b4 <HW_IPCC_Rx_Handler+0x68>)
|
|
8018574: f7ff ffd4 bl 8018520 <LL_C2_IPCC_IsActiveFlag_CHx>
|
|
8018578: 4603 mov r3, r0
|
|
801857a: 2b00 cmp r3, #0
|
|
801857c: d008 beq.n 8018590 <HW_IPCC_Rx_Handler+0x44>
|
|
801857e: 4b0d ldr r3, [pc, #52] @ (80185b4 <HW_IPCC_Rx_Handler+0x68>)
|
|
8018580: 685b ldr r3, [r3, #4]
|
|
8018582: f003 0301 and.w r3, r3, #1
|
|
8018586: 2b00 cmp r3, #0
|
|
8018588: d102 bne.n 8018590 <HW_IPCC_Rx_Handler+0x44>
|
|
{
|
|
HW_IPCC_BLE_EvtHandler();
|
|
801858a: f000 f875 bl 8018678 <HW_IPCC_BLE_EvtHandler>
|
|
801858e: e00e b.n 80185ae <HW_IPCC_Rx_Handler+0x62>
|
|
}
|
|
else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
|
|
8018590: 2108 movs r1, #8
|
|
8018592: 4808 ldr r0, [pc, #32] @ (80185b4 <HW_IPCC_Rx_Handler+0x68>)
|
|
8018594: f7ff ffc4 bl 8018520 <LL_C2_IPCC_IsActiveFlag_CHx>
|
|
8018598: 4603 mov r3, r0
|
|
801859a: 2b00 cmp r3, #0
|
|
801859c: d008 beq.n 80185b0 <HW_IPCC_Rx_Handler+0x64>
|
|
801859e: 4b05 ldr r3, [pc, #20] @ (80185b4 <HW_IPCC_Rx_Handler+0x68>)
|
|
80185a0: 685b ldr r3, [r3, #4]
|
|
80185a2: f003 0308 and.w r3, r3, #8
|
|
80185a6: 2b00 cmp r3, #0
|
|
80185a8: d102 bne.n 80185b0 <HW_IPCC_Rx_Handler+0x64>
|
|
{
|
|
HW_IPCC_TRACES_EvtHandler();
|
|
80185aa: f000 f959 bl 8018860 <HW_IPCC_TRACES_EvtHandler>
|
|
}
|
|
|
|
return;
|
|
80185ae: bf00 nop
|
|
80185b0: bf00 nop
|
|
}
|
|
80185b2: bd80 pop {r7, pc}
|
|
80185b4: 58000c00 .word 0x58000c00
|
|
|
|
080185b8 <HW_IPCC_Tx_Handler>:
|
|
|
|
void HW_IPCC_Tx_Handler( void )
|
|
{
|
|
80185b8: b580 push {r7, lr}
|
|
80185ba: af00 add r7, sp, #0
|
|
if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
|
|
80185bc: 2102 movs r1, #2
|
|
80185be: 4818 ldr r0, [pc, #96] @ (8018620 <HW_IPCC_Tx_Handler+0x68>)
|
|
80185c0: f7ff ff99 bl 80184f6 <LL_C1_IPCC_IsActiveFlag_CHx>
|
|
80185c4: 4603 mov r3, r0
|
|
80185c6: 2b00 cmp r3, #0
|
|
80185c8: d108 bne.n 80185dc <HW_IPCC_Tx_Handler+0x24>
|
|
80185ca: 4b15 ldr r3, [pc, #84] @ (8018620 <HW_IPCC_Tx_Handler+0x68>)
|
|
80185cc: 685b ldr r3, [r3, #4]
|
|
80185ce: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80185d2: 2b00 cmp r3, #0
|
|
80185d4: d102 bne.n 80185dc <HW_IPCC_Tx_Handler+0x24>
|
|
{
|
|
HW_IPCC_SYS_CmdEvtHandler();
|
|
80185d6: f000 f8af bl 8018738 <HW_IPCC_SYS_CmdEvtHandler>
|
|
80185da: e01e b.n 801861a <HW_IPCC_Tx_Handler+0x62>
|
|
if (HW_IPCC_TX_PENDING( HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL ))
|
|
{
|
|
HW_IPCC_ZIGBEE_CmdEvtHandler();
|
|
}
|
|
#endif /* ZIGBEE_WB */
|
|
else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
|
|
80185dc: 2108 movs r1, #8
|
|
80185de: 4810 ldr r0, [pc, #64] @ (8018620 <HW_IPCC_Tx_Handler+0x68>)
|
|
80185e0: f7ff ff89 bl 80184f6 <LL_C1_IPCC_IsActiveFlag_CHx>
|
|
80185e4: 4603 mov r3, r0
|
|
80185e6: 2b00 cmp r3, #0
|
|
80185e8: d108 bne.n 80185fc <HW_IPCC_Tx_Handler+0x44>
|
|
80185ea: 4b0d ldr r3, [pc, #52] @ (8018620 <HW_IPCC_Tx_Handler+0x68>)
|
|
80185ec: 685b ldr r3, [r3, #4]
|
|
80185ee: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80185f2: 2b00 cmp r3, #0
|
|
80185f4: d102 bne.n 80185fc <HW_IPCC_Tx_Handler+0x44>
|
|
{
|
|
HW_IPCC_MM_FreeBufHandler();
|
|
80185f6: f000 f8f5 bl 80187e4 <HW_IPCC_MM_FreeBufHandler>
|
|
80185fa: e00e b.n 801861a <HW_IPCC_Tx_Handler+0x62>
|
|
}
|
|
else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
|
|
80185fc: 2120 movs r1, #32
|
|
80185fe: 4808 ldr r0, [pc, #32] @ (8018620 <HW_IPCC_Tx_Handler+0x68>)
|
|
8018600: f7ff ff79 bl 80184f6 <LL_C1_IPCC_IsActiveFlag_CHx>
|
|
8018604: 4603 mov r3, r0
|
|
8018606: 2b00 cmp r3, #0
|
|
8018608: d108 bne.n 801861c <HW_IPCC_Tx_Handler+0x64>
|
|
801860a: 4b05 ldr r3, [pc, #20] @ (8018620 <HW_IPCC_Tx_Handler+0x68>)
|
|
801860c: 685b ldr r3, [r3, #4]
|
|
801860e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8018612: 2b00 cmp r3, #0
|
|
8018614: d102 bne.n 801861c <HW_IPCC_Tx_Handler+0x64>
|
|
{
|
|
HW_IPCC_BLE_AclDataEvtHandler();
|
|
8018616: f000 f83b bl 8018690 <HW_IPCC_BLE_AclDataEvtHandler>
|
|
}
|
|
|
|
return;
|
|
801861a: bf00 nop
|
|
801861c: bf00 nop
|
|
}
|
|
801861e: bd80 pop {r7, pc}
|
|
8018620: 58000c00 .word 0x58000c00
|
|
|
|
08018624 <HW_IPCC_Enable>:
|
|
/******************************************************************************
|
|
* GENERAL
|
|
******************************************************************************/
|
|
void HW_IPCC_Enable( void )
|
|
{
|
|
8018624: b580 push {r7, lr}
|
|
8018626: af00 add r7, sp, #0
|
|
/**
|
|
* Such as IPCC IP available to the CPU2, it is required to keep the IPCC clock running
|
|
* when FUS is running on CPU2 and CPU1 enters deep sleep mode
|
|
*/
|
|
LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC);
|
|
8018628: f44f 1080 mov.w r0, #1048576 @ 0x100000
|
|
801862c: f7ff fed3 bl 80183d6 <LL_C2_AHB3_GRP1_EnableClock>
|
|
|
|
/**
|
|
* When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
|
|
*/
|
|
LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
|
|
8018630: f44f 7000 mov.w r0, #512 @ 0x200
|
|
8018634: f7ff fea4 bl 8018380 <LL_EXTI_EnableRisingTrig_32_63>
|
|
/* It is required to have at least a system clock cycle before a SEV after LL_EXTI_EnableRisingTrig_32_63() */
|
|
LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
|
|
8018638: f44f 7000 mov.w r0, #512 @ 0x200
|
|
801863c: f7ff fe8c bl 8018358 <LL_C2_EXTI_EnableEvent_32_63>
|
|
* When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
|
|
* This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
|
|
* When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
|
|
* So, by default, the application shall both set the event flag and set the C2BOOT bit.
|
|
*/
|
|
__SEV( ); /* Set the internal event flag and send an event to the CPU2 */
|
|
8018640: bf40 sev
|
|
__WFE( ); /* Clear the internal event flag */
|
|
8018642: bf20 wfe
|
|
LL_PWR_EnableBootC2( );
|
|
8018644: f7ff fe78 bl 8018338 <LL_PWR_EnableBootC2>
|
|
|
|
return;
|
|
8018648: bf00 nop
|
|
}
|
|
801864a: bd80 pop {r7, pc}
|
|
|
|
0801864c <HW_IPCC_Init>:
|
|
|
|
void HW_IPCC_Init( void )
|
|
{
|
|
801864c: b580 push {r7, lr}
|
|
801864e: af00 add r7, sp, #0
|
|
LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
|
|
8018650: f44f 1080 mov.w r0, #1048576 @ 0x100000
|
|
8018654: f7ff fea6 bl 80183a4 <LL_AHB3_GRP1_EnableClock>
|
|
|
|
LL_C1_IPCC_EnableIT_RXO( IPCC );
|
|
8018658: 4806 ldr r0, [pc, #24] @ (8018674 <HW_IPCC_Init+0x28>)
|
|
801865a: f7ff fee8 bl 801842e <LL_C1_IPCC_EnableIT_RXO>
|
|
LL_C1_IPCC_EnableIT_TXF( IPCC );
|
|
801865e: 4805 ldr r0, [pc, #20] @ (8018674 <HW_IPCC_Init+0x28>)
|
|
8018660: f7ff fed5 bl 801840e <LL_C1_IPCC_EnableIT_TXF>
|
|
|
|
HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
|
|
8018664: 202c movs r0, #44 @ 0x2c
|
|
8018666: f7ee facb bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
|
|
801866a: 202d movs r0, #45 @ 0x2d
|
|
801866c: f7ee fac8 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
|
|
return;
|
|
8018670: bf00 nop
|
|
}
|
|
8018672: bd80 pop {r7, pc}
|
|
8018674: 58000c00 .word 0x58000c00
|
|
|
|
08018678 <HW_IPCC_BLE_EvtHandler>:
|
|
|
|
return;
|
|
}
|
|
|
|
static void HW_IPCC_BLE_EvtHandler( void )
|
|
{
|
|
8018678: b580 push {r7, lr}
|
|
801867a: af00 add r7, sp, #0
|
|
HW_IPCC_BLE_RxEvtNot();
|
|
801867c: f7fa fe16 bl 80132ac <HW_IPCC_BLE_RxEvtNot>
|
|
|
|
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
|
|
8018680: 2101 movs r1, #1
|
|
8018682: 4802 ldr r0, [pc, #8] @ (801868c <HW_IPCC_BLE_EvtHandler+0x14>)
|
|
8018684: f7ff ff1a bl 80184bc <LL_C1_IPCC_ClearFlag_CHx>
|
|
|
|
return;
|
|
8018688: bf00 nop
|
|
}
|
|
801868a: bd80 pop {r7, pc}
|
|
801868c: 58000c00 .word 0x58000c00
|
|
|
|
08018690 <HW_IPCC_BLE_AclDataEvtHandler>:
|
|
|
|
return;
|
|
}
|
|
|
|
static void HW_IPCC_BLE_AclDataEvtHandler( void )
|
|
{
|
|
8018690: b580 push {r7, lr}
|
|
8018692: b084 sub sp, #16
|
|
8018694: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
8018696: f3ef 8310 mrs r3, PRIMASK
|
|
801869a: 607b str r3, [r7, #4]
|
|
return(result);
|
|
801869c: 687b ldr r3, [r7, #4]
|
|
UTILS_ENTER_CRITICAL_SECTION();
|
|
801869e: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80186a0: b672 cpsid i
|
|
}
|
|
80186a2: bf00 nop
|
|
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
|
|
80186a4: 2120 movs r1, #32
|
|
80186a6: 4807 ldr r0, [pc, #28] @ (80186c4 <HW_IPCC_BLE_AclDataEvtHandler+0x34>)
|
|
80186a8: f7ff fee4 bl 8018474 <LL_C1_IPCC_DisableTransmitChannel>
|
|
80186ac: 68fb ldr r3, [r7, #12]
|
|
80186ae: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80186b0: 68bb ldr r3, [r7, #8]
|
|
80186b2: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80186b6: bf00 nop
|
|
UTILS_EXIT_CRITICAL_SECTION();
|
|
|
|
HW_IPCC_BLE_AclDataAckNot();
|
|
80186b8: f7fa fe28 bl 801330c <HW_IPCC_BLE_AclDataAckNot>
|
|
|
|
return;
|
|
80186bc: bf00 nop
|
|
}
|
|
80186be: 3710 adds r7, #16
|
|
80186c0: 46bd mov sp, r7
|
|
80186c2: bd80 pop {r7, pc}
|
|
80186c4: 58000c00 .word 0x58000c00
|
|
|
|
080186c8 <HW_IPCC_SYS_Init>:
|
|
|
|
/******************************************************************************
|
|
* SYSTEM
|
|
******************************************************************************/
|
|
void HW_IPCC_SYS_Init( void )
|
|
{
|
|
80186c8: b580 push {r7, lr}
|
|
80186ca: b084 sub sp, #16
|
|
80186cc: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80186ce: f3ef 8310 mrs r3, PRIMASK
|
|
80186d2: 607b str r3, [r7, #4]
|
|
return(result);
|
|
80186d4: 687b ldr r3, [r7, #4]
|
|
UTILS_ENTER_CRITICAL_SECTION();
|
|
80186d6: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80186d8: b672 cpsid i
|
|
}
|
|
80186da: bf00 nop
|
|
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
|
|
80186dc: 2102 movs r1, #2
|
|
80186de: 4806 ldr r0, [pc, #24] @ (80186f8 <HW_IPCC_SYS_Init+0x30>)
|
|
80186e0: f7ff feda bl 8018498 <LL_C1_IPCC_EnableReceiveChannel>
|
|
80186e4: 68fb ldr r3, [r7, #12]
|
|
80186e6: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80186e8: 68bb ldr r3, [r7, #8]
|
|
80186ea: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80186ee: bf00 nop
|
|
UTILS_EXIT_CRITICAL_SECTION();
|
|
|
|
return;
|
|
80186f0: bf00 nop
|
|
}
|
|
80186f2: 3710 adds r7, #16
|
|
80186f4: 46bd mov sp, r7
|
|
80186f6: bd80 pop {r7, pc}
|
|
80186f8: 58000c00 .word 0x58000c00
|
|
|
|
080186fc <HW_IPCC_SYS_SendCmd>:
|
|
|
|
void HW_IPCC_SYS_SendCmd( void )
|
|
{
|
|
80186fc: b580 push {r7, lr}
|
|
80186fe: b084 sub sp, #16
|
|
8018700: af00 add r7, sp, #0
|
|
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
|
|
8018702: 2102 movs r1, #2
|
|
8018704: 480b ldr r0, [pc, #44] @ (8018734 <HW_IPCC_SYS_SendCmd+0x38>)
|
|
8018706: f7ff fee7 bl 80184d8 <LL_C1_IPCC_SetFlag_CHx>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
801870a: f3ef 8310 mrs r3, PRIMASK
|
|
801870e: 607b str r3, [r7, #4]
|
|
return(result);
|
|
8018710: 687b ldr r3, [r7, #4]
|
|
UTILS_ENTER_CRITICAL_SECTION();
|
|
8018712: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8018714: b672 cpsid i
|
|
}
|
|
8018716: bf00 nop
|
|
LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
|
|
8018718: 2102 movs r1, #2
|
|
801871a: 4806 ldr r0, [pc, #24] @ (8018734 <HW_IPCC_SYS_SendCmd+0x38>)
|
|
801871c: f7ff fe97 bl 801844e <LL_C1_IPCC_EnableTransmitChannel>
|
|
8018720: 68fb ldr r3, [r7, #12]
|
|
8018722: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8018724: 68bb ldr r3, [r7, #8]
|
|
8018726: f383 8810 msr PRIMASK, r3
|
|
}
|
|
801872a: bf00 nop
|
|
UTILS_EXIT_CRITICAL_SECTION();
|
|
|
|
return;
|
|
801872c: bf00 nop
|
|
}
|
|
801872e: 3710 adds r7, #16
|
|
8018730: 46bd mov sp, r7
|
|
8018732: bd80 pop {r7, pc}
|
|
8018734: 58000c00 .word 0x58000c00
|
|
|
|
08018738 <HW_IPCC_SYS_CmdEvtHandler>:
|
|
|
|
static void HW_IPCC_SYS_CmdEvtHandler( void )
|
|
{
|
|
8018738: b580 push {r7, lr}
|
|
801873a: b084 sub sp, #16
|
|
801873c: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
801873e: f3ef 8310 mrs r3, PRIMASK
|
|
8018742: 607b str r3, [r7, #4]
|
|
return(result);
|
|
8018744: 687b ldr r3, [r7, #4]
|
|
UTILS_ENTER_CRITICAL_SECTION();
|
|
8018746: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8018748: b672 cpsid i
|
|
}
|
|
801874a: bf00 nop
|
|
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
|
|
801874c: 2102 movs r1, #2
|
|
801874e: 4807 ldr r0, [pc, #28] @ (801876c <HW_IPCC_SYS_CmdEvtHandler+0x34>)
|
|
8018750: f7ff fe90 bl 8018474 <LL_C1_IPCC_DisableTransmitChannel>
|
|
8018754: 68fb ldr r3, [r7, #12]
|
|
8018756: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8018758: 68bb ldr r3, [r7, #8]
|
|
801875a: f383 8810 msr PRIMASK, r3
|
|
}
|
|
801875e: bf00 nop
|
|
UTILS_EXIT_CRITICAL_SECTION();
|
|
|
|
HW_IPCC_SYS_CmdEvtNot();
|
|
8018760: f7fa fe28 bl 80133b4 <HW_IPCC_SYS_CmdEvtNot>
|
|
|
|
return;
|
|
8018764: bf00 nop
|
|
}
|
|
8018766: 3710 adds r7, #16
|
|
8018768: 46bd mov sp, r7
|
|
801876a: bd80 pop {r7, pc}
|
|
801876c: 58000c00 .word 0x58000c00
|
|
|
|
08018770 <HW_IPCC_SYS_EvtHandler>:
|
|
|
|
static void HW_IPCC_SYS_EvtHandler( void )
|
|
{
|
|
8018770: b580 push {r7, lr}
|
|
8018772: af00 add r7, sp, #0
|
|
HW_IPCC_SYS_EvtNot();
|
|
8018774: f7fa fe34 bl 80133e0 <HW_IPCC_SYS_EvtNot>
|
|
|
|
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
|
|
8018778: 2102 movs r1, #2
|
|
801877a: 4802 ldr r0, [pc, #8] @ (8018784 <HW_IPCC_SYS_EvtHandler+0x14>)
|
|
801877c: f7ff fe9e bl 80184bc <LL_C1_IPCC_ClearFlag_CHx>
|
|
|
|
return;
|
|
8018780: bf00 nop
|
|
}
|
|
8018782: bd80 pop {r7, pc}
|
|
8018784: 58000c00 .word 0x58000c00
|
|
|
|
08018788 <HW_IPCC_MM_SendFreeBuf>:
|
|
|
|
/******************************************************************************
|
|
* MEMORY MANAGER
|
|
******************************************************************************/
|
|
void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
|
|
{
|
|
8018788: b580 push {r7, lr}
|
|
801878a: b086 sub sp, #24
|
|
801878c: af00 add r7, sp, #0
|
|
801878e: 6078 str r0, [r7, #4]
|
|
if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
|
|
8018790: 2108 movs r1, #8
|
|
8018792: 4812 ldr r0, [pc, #72] @ (80187dc <HW_IPCC_MM_SendFreeBuf+0x54>)
|
|
8018794: f7ff feaf bl 80184f6 <LL_C1_IPCC_IsActiveFlag_CHx>
|
|
8018798: 4603 mov r3, r0
|
|
801879a: 2b00 cmp r3, #0
|
|
801879c: d013 beq.n 80187c6 <HW_IPCC_MM_SendFreeBuf+0x3e>
|
|
{
|
|
FreeBufCb = cb;
|
|
801879e: 4a10 ldr r2, [pc, #64] @ (80187e0 <HW_IPCC_MM_SendFreeBuf+0x58>)
|
|
80187a0: 687b ldr r3, [r7, #4]
|
|
80187a2: 6013 str r3, [r2, #0]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80187a4: f3ef 8310 mrs r3, PRIMASK
|
|
80187a8: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80187aa: 68fb ldr r3, [r7, #12]
|
|
UTILS_ENTER_CRITICAL_SECTION();
|
|
80187ac: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80187ae: b672 cpsid i
|
|
}
|
|
80187b0: bf00 nop
|
|
LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
|
|
80187b2: 2108 movs r1, #8
|
|
80187b4: 4809 ldr r0, [pc, #36] @ (80187dc <HW_IPCC_MM_SendFreeBuf+0x54>)
|
|
80187b6: f7ff fe4a bl 801844e <LL_C1_IPCC_EnableTransmitChannel>
|
|
80187ba: 697b ldr r3, [r7, #20]
|
|
80187bc: 613b str r3, [r7, #16]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80187be: 693b ldr r3, [r7, #16]
|
|
80187c0: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80187c4: e005 b.n 80187d2 <HW_IPCC_MM_SendFreeBuf+0x4a>
|
|
UTILS_EXIT_CRITICAL_SECTION();
|
|
}
|
|
else
|
|
{
|
|
cb();
|
|
80187c6: 687b ldr r3, [r7, #4]
|
|
80187c8: 4798 blx r3
|
|
|
|
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
|
|
80187ca: 2108 movs r1, #8
|
|
80187cc: 4803 ldr r0, [pc, #12] @ (80187dc <HW_IPCC_MM_SendFreeBuf+0x54>)
|
|
80187ce: f7ff fe83 bl 80184d8 <LL_C1_IPCC_SetFlag_CHx>
|
|
}
|
|
|
|
return;
|
|
80187d2: bf00 nop
|
|
}
|
|
80187d4: 3718 adds r7, #24
|
|
80187d6: 46bd mov sp, r7
|
|
80187d8: bd80 pop {r7, pc}
|
|
80187da: bf00 nop
|
|
80187dc: 58000c00 .word 0x58000c00
|
|
80187e0: 200121b8 .word 0x200121b8
|
|
|
|
080187e4 <HW_IPCC_MM_FreeBufHandler>:
|
|
|
|
static void HW_IPCC_MM_FreeBufHandler( void )
|
|
{
|
|
80187e4: b580 push {r7, lr}
|
|
80187e6: b084 sub sp, #16
|
|
80187e8: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80187ea: f3ef 8310 mrs r3, PRIMASK
|
|
80187ee: 607b str r3, [r7, #4]
|
|
return(result);
|
|
80187f0: 687b ldr r3, [r7, #4]
|
|
UTILS_ENTER_CRITICAL_SECTION();
|
|
80187f2: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80187f4: b672 cpsid i
|
|
}
|
|
80187f6: bf00 nop
|
|
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
|
|
80187f8: 2108 movs r1, #8
|
|
80187fa: 480a ldr r0, [pc, #40] @ (8018824 <HW_IPCC_MM_FreeBufHandler+0x40>)
|
|
80187fc: f7ff fe3a bl 8018474 <LL_C1_IPCC_DisableTransmitChannel>
|
|
8018800: 68fb ldr r3, [r7, #12]
|
|
8018802: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8018804: 68bb ldr r3, [r7, #8]
|
|
8018806: f383 8810 msr PRIMASK, r3
|
|
}
|
|
801880a: bf00 nop
|
|
UTILS_EXIT_CRITICAL_SECTION();
|
|
|
|
FreeBufCb();
|
|
801880c: 4b06 ldr r3, [pc, #24] @ (8018828 <HW_IPCC_MM_FreeBufHandler+0x44>)
|
|
801880e: 681b ldr r3, [r3, #0]
|
|
8018810: 4798 blx r3
|
|
|
|
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
|
|
8018812: 2108 movs r1, #8
|
|
8018814: 4803 ldr r0, [pc, #12] @ (8018824 <HW_IPCC_MM_FreeBufHandler+0x40>)
|
|
8018816: f7ff fe5f bl 80184d8 <LL_C1_IPCC_SetFlag_CHx>
|
|
|
|
return;
|
|
801881a: bf00 nop
|
|
}
|
|
801881c: 3710 adds r7, #16
|
|
801881e: 46bd mov sp, r7
|
|
8018820: bd80 pop {r7, pc}
|
|
8018822: bf00 nop
|
|
8018824: 58000c00 .word 0x58000c00
|
|
8018828: 200121b8 .word 0x200121b8
|
|
|
|
0801882c <HW_IPCC_TRACES_Init>:
|
|
|
|
/******************************************************************************
|
|
* TRACES
|
|
******************************************************************************/
|
|
void HW_IPCC_TRACES_Init( void )
|
|
{
|
|
801882c: b580 push {r7, lr}
|
|
801882e: b084 sub sp, #16
|
|
8018830: af00 add r7, sp, #0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
8018832: f3ef 8310 mrs r3, PRIMASK
|
|
8018836: 607b str r3, [r7, #4]
|
|
return(result);
|
|
8018838: 687b ldr r3, [r7, #4]
|
|
UTILS_ENTER_CRITICAL_SECTION();
|
|
801883a: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
801883c: b672 cpsid i
|
|
}
|
|
801883e: bf00 nop
|
|
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
|
|
8018840: 2108 movs r1, #8
|
|
8018842: 4806 ldr r0, [pc, #24] @ (801885c <HW_IPCC_TRACES_Init+0x30>)
|
|
8018844: f7ff fe28 bl 8018498 <LL_C1_IPCC_EnableReceiveChannel>
|
|
8018848: 68fb ldr r3, [r7, #12]
|
|
801884a: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
801884c: 68bb ldr r3, [r7, #8]
|
|
801884e: f383 8810 msr PRIMASK, r3
|
|
}
|
|
8018852: bf00 nop
|
|
UTILS_EXIT_CRITICAL_SECTION();
|
|
|
|
return;
|
|
8018854: bf00 nop
|
|
}
|
|
8018856: 3710 adds r7, #16
|
|
8018858: 46bd mov sp, r7
|
|
801885a: bd80 pop {r7, pc}
|
|
801885c: 58000c00 .word 0x58000c00
|
|
|
|
08018860 <HW_IPCC_TRACES_EvtHandler>:
|
|
|
|
static void HW_IPCC_TRACES_EvtHandler( void )
|
|
{
|
|
8018860: b580 push {r7, lr}
|
|
8018862: af00 add r7, sp, #0
|
|
HW_IPCC_TRACES_EvtNot();
|
|
8018864: f7fa fe64 bl 8013530 <HW_IPCC_TRACES_EvtNot>
|
|
|
|
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
|
|
8018868: 2108 movs r1, #8
|
|
801886a: 4802 ldr r0, [pc, #8] @ (8018874 <HW_IPCC_TRACES_EvtHandler+0x14>)
|
|
801886c: f7ff fe26 bl 80184bc <LL_C1_IPCC_ClearFlag_CHx>
|
|
|
|
return;
|
|
8018870: bf00 nop
|
|
}
|
|
8018872: bd80 pop {r7, pc}
|
|
8018874: 58000c00 .word 0x58000c00
|
|
|
|
08018878 <MX_USB_Device_Init>:
|
|
/**
|
|
* Init USB device Library, add supported class and start the library
|
|
* @retval None
|
|
*/
|
|
void MX_USB_Device_Init(void)
|
|
{
|
|
8018878: b580 push {r7, lr}
|
|
801887a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_Device_Init_PreTreatment */
|
|
|
|
/* USER CODE END USB_Device_Init_PreTreatment */
|
|
|
|
/* Init Device Library, add supported class and start the library. */
|
|
if (USBD_Init(&hUsbDeviceFS, &CDC_Desc, DEVICE_FS) != USBD_OK) {
|
|
801887c: 2200 movs r2, #0
|
|
801887e: 4912 ldr r1, [pc, #72] @ (80188c8 <MX_USB_Device_Init+0x50>)
|
|
8018880: 4812 ldr r0, [pc, #72] @ (80188cc <MX_USB_Device_Init+0x54>)
|
|
8018882: f7f9 f809 bl 8011898 <USBD_Init>
|
|
8018886: 4603 mov r3, r0
|
|
8018888: 2b00 cmp r3, #0
|
|
801888a: d001 beq.n 8018890 <MX_USB_Device_Init+0x18>
|
|
Error_Handler();
|
|
801888c: f7ec fd72 bl 8005374 <Error_Handler>
|
|
}
|
|
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) {
|
|
8018890: 490f ldr r1, [pc, #60] @ (80188d0 <MX_USB_Device_Init+0x58>)
|
|
8018892: 480e ldr r0, [pc, #56] @ (80188cc <MX_USB_Device_Init+0x54>)
|
|
8018894: f7f9 f830 bl 80118f8 <USBD_RegisterClass>
|
|
8018898: 4603 mov r3, r0
|
|
801889a: 2b00 cmp r3, #0
|
|
801889c: d001 beq.n 80188a2 <MX_USB_Device_Init+0x2a>
|
|
Error_Handler();
|
|
801889e: f7ec fd69 bl 8005374 <Error_Handler>
|
|
}
|
|
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) {
|
|
80188a2: 490c ldr r1, [pc, #48] @ (80188d4 <MX_USB_Device_Init+0x5c>)
|
|
80188a4: 4809 ldr r0, [pc, #36] @ (80188cc <MX_USB_Device_Init+0x54>)
|
|
80188a6: f7f8 ff27 bl 80116f8 <USBD_CDC_RegisterInterface>
|
|
80188aa: 4603 mov r3, r0
|
|
80188ac: 2b00 cmp r3, #0
|
|
80188ae: d001 beq.n 80188b4 <MX_USB_Device_Init+0x3c>
|
|
Error_Handler();
|
|
80188b0: f7ec fd60 bl 8005374 <Error_Handler>
|
|
}
|
|
if (USBD_Start(&hUsbDeviceFS) != USBD_OK) {
|
|
80188b4: 4805 ldr r0, [pc, #20] @ (80188cc <MX_USB_Device_Init+0x54>)
|
|
80188b6: f7f9 f855 bl 8011964 <USBD_Start>
|
|
80188ba: 4603 mov r3, r0
|
|
80188bc: 2b00 cmp r3, #0
|
|
80188be: d001 beq.n 80188c4 <MX_USB_Device_Init+0x4c>
|
|
Error_Handler();
|
|
80188c0: f7ec fd58 bl 8005374 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USB_Device_Init_PostTreatment */
|
|
|
|
/* USER CODE END USB_Device_Init_PostTreatment */
|
|
}
|
|
80188c4: bf00 nop
|
|
80188c6: bd80 pop {r7, pc}
|
|
80188c8: 200000bc .word 0x200000bc
|
|
80188cc: 200121bc .word 0x200121bc
|
|
80188d0: 20000024 .word 0x20000024
|
|
80188d4: 200000a8 .word 0x200000a8
|
|
|
|
080188d8 <CDC_Init_FS>:
|
|
/**
|
|
* @brief Initializes the CDC media low layer over the FS USB IP
|
|
* @retval USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_Init_FS(void)
|
|
{
|
|
80188d8: b580 push {r7, lr}
|
|
80188da: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN 3 */
|
|
/* Set Application Buffers */
|
|
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
|
|
80188dc: 2200 movs r2, #0
|
|
80188de: 4905 ldr r1, [pc, #20] @ (80188f4 <CDC_Init_FS+0x1c>)
|
|
80188e0: 4805 ldr r0, [pc, #20] @ (80188f8 <CDC_Init_FS+0x20>)
|
|
80188e2: f7f8 ff23 bl 801172c <USBD_CDC_SetTxBuffer>
|
|
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
|
|
80188e6: 4905 ldr r1, [pc, #20] @ (80188fc <CDC_Init_FS+0x24>)
|
|
80188e8: 4803 ldr r0, [pc, #12] @ (80188f8 <CDC_Init_FS+0x20>)
|
|
80188ea: f7f8 ff41 bl 8011770 <USBD_CDC_SetRxBuffer>
|
|
return (USBD_OK);
|
|
80188ee: 2300 movs r3, #0
|
|
/* USER CODE END 3 */
|
|
}
|
|
80188f0: 4618 mov r0, r3
|
|
80188f2: bd80 pop {r7, pc}
|
|
80188f4: 20012c98 .word 0x20012c98
|
|
80188f8: 200121bc .word 0x200121bc
|
|
80188fc: 20012498 .word 0x20012498
|
|
|
|
08018900 <CDC_DeInit_FS>:
|
|
/**
|
|
* @brief DeInitializes the CDC media low layer
|
|
* @retval USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_DeInit_FS(void)
|
|
{
|
|
8018900: b480 push {r7}
|
|
8018902: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN 4 */
|
|
return (USBD_OK);
|
|
8018904: 2300 movs r3, #0
|
|
/* USER CODE END 4 */
|
|
}
|
|
8018906: 4618 mov r0, r3
|
|
8018908: 46bd mov sp, r7
|
|
801890a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801890e: 4770 bx lr
|
|
|
|
08018910 <CDC_Control_FS>:
|
|
* @param pbuf: Buffer containing command data (request parameters)
|
|
* @param length: Number of data to be sent (in bytes)
|
|
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
|
|
{
|
|
8018910: b480 push {r7}
|
|
8018912: b083 sub sp, #12
|
|
8018914: af00 add r7, sp, #0
|
|
8018916: 4603 mov r3, r0
|
|
8018918: 6039 str r1, [r7, #0]
|
|
801891a: 71fb strb r3, [r7, #7]
|
|
801891c: 4613 mov r3, r2
|
|
801891e: 80bb strh r3, [r7, #4]
|
|
/* USER CODE BEGIN 5 */
|
|
switch(cmd)
|
|
8018920: 79fb ldrb r3, [r7, #7]
|
|
8018922: 2b23 cmp r3, #35 @ 0x23
|
|
8018924: d84a bhi.n 80189bc <CDC_Control_FS+0xac>
|
|
8018926: a201 add r2, pc, #4 @ (adr r2, 801892c <CDC_Control_FS+0x1c>)
|
|
8018928: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
801892c: 080189bd .word 0x080189bd
|
|
8018930: 080189bd .word 0x080189bd
|
|
8018934: 080189bd .word 0x080189bd
|
|
8018938: 080189bd .word 0x080189bd
|
|
801893c: 080189bd .word 0x080189bd
|
|
8018940: 080189bd .word 0x080189bd
|
|
8018944: 080189bd .word 0x080189bd
|
|
8018948: 080189bd .word 0x080189bd
|
|
801894c: 080189bd .word 0x080189bd
|
|
8018950: 080189bd .word 0x080189bd
|
|
8018954: 080189bd .word 0x080189bd
|
|
8018958: 080189bd .word 0x080189bd
|
|
801895c: 080189bd .word 0x080189bd
|
|
8018960: 080189bd .word 0x080189bd
|
|
8018964: 080189bd .word 0x080189bd
|
|
8018968: 080189bd .word 0x080189bd
|
|
801896c: 080189bd .word 0x080189bd
|
|
8018970: 080189bd .word 0x080189bd
|
|
8018974: 080189bd .word 0x080189bd
|
|
8018978: 080189bd .word 0x080189bd
|
|
801897c: 080189bd .word 0x080189bd
|
|
8018980: 080189bd .word 0x080189bd
|
|
8018984: 080189bd .word 0x080189bd
|
|
8018988: 080189bd .word 0x080189bd
|
|
801898c: 080189bd .word 0x080189bd
|
|
8018990: 080189bd .word 0x080189bd
|
|
8018994: 080189bd .word 0x080189bd
|
|
8018998: 080189bd .word 0x080189bd
|
|
801899c: 080189bd .word 0x080189bd
|
|
80189a0: 080189bd .word 0x080189bd
|
|
80189a4: 080189bd .word 0x080189bd
|
|
80189a8: 080189bd .word 0x080189bd
|
|
80189ac: 080189bd .word 0x080189bd
|
|
80189b0: 080189bd .word 0x080189bd
|
|
80189b4: 080189bd .word 0x080189bd
|
|
80189b8: 080189bd .word 0x080189bd
|
|
case CDC_SEND_BREAK:
|
|
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
80189bc: bf00 nop
|
|
}
|
|
|
|
return (USBD_OK);
|
|
80189be: 2300 movs r3, #0
|
|
/* USER CODE END 5 */
|
|
}
|
|
80189c0: 4618 mov r0, r3
|
|
80189c2: 370c adds r7, #12
|
|
80189c4: 46bd mov sp, r7
|
|
80189c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80189ca: 4770 bx lr
|
|
|
|
080189cc <CDC_Receive_FS>:
|
|
* @param Buf: Buffer of data to be received
|
|
* @param Len: Number of data received (in bytes)
|
|
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
|
|
{
|
|
80189cc: b580 push {r7, lr}
|
|
80189ce: b082 sub sp, #8
|
|
80189d0: af00 add r7, sp, #0
|
|
80189d2: 6078 str r0, [r7, #4]
|
|
80189d4: 6039 str r1, [r7, #0]
|
|
/* USER CODE BEGIN 6 */
|
|
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
|
|
80189d6: 6879 ldr r1, [r7, #4]
|
|
80189d8: 4805 ldr r0, [pc, #20] @ (80189f0 <CDC_Receive_FS+0x24>)
|
|
80189da: f7f8 fec9 bl 8011770 <USBD_CDC_SetRxBuffer>
|
|
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
|
|
80189de: 4804 ldr r0, [pc, #16] @ (80189f0 <CDC_Receive_FS+0x24>)
|
|
80189e0: f7f8 ff24 bl 801182c <USBD_CDC_ReceivePacket>
|
|
return (USBD_OK);
|
|
80189e4: 2300 movs r3, #0
|
|
/* USER CODE END 6 */
|
|
}
|
|
80189e6: 4618 mov r0, r3
|
|
80189e8: 3708 adds r7, #8
|
|
80189ea: 46bd mov sp, r7
|
|
80189ec: bd80 pop {r7, pc}
|
|
80189ee: bf00 nop
|
|
80189f0: 200121bc .word 0x200121bc
|
|
|
|
080189f4 <CDC_Transmit_FS>:
|
|
* @param Buf: Buffer of data to be sent
|
|
* @param Len: Number of data to be sent (in bytes)
|
|
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
|
|
*/
|
|
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
|
|
{
|
|
80189f4: b580 push {r7, lr}
|
|
80189f6: b084 sub sp, #16
|
|
80189f8: af00 add r7, sp, #0
|
|
80189fa: 6078 str r0, [r7, #4]
|
|
80189fc: 460b mov r3, r1
|
|
80189fe: 807b strh r3, [r7, #2]
|
|
uint8_t result = USBD_OK;
|
|
8018a00: 2300 movs r3, #0
|
|
8018a02: 73fb strb r3, [r7, #15]
|
|
/* USER CODE BEGIN 7 */
|
|
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
|
|
8018a04: 4b0d ldr r3, [pc, #52] @ (8018a3c <CDC_Transmit_FS+0x48>)
|
|
8018a06: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
|
|
8018a0a: 60bb str r3, [r7, #8]
|
|
if (hcdc->TxState != 0){
|
|
8018a0c: 68bb ldr r3, [r7, #8]
|
|
8018a0e: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
|
|
8018a12: 2b00 cmp r3, #0
|
|
8018a14: d001 beq.n 8018a1a <CDC_Transmit_FS+0x26>
|
|
return USBD_BUSY;
|
|
8018a16: 2301 movs r3, #1
|
|
8018a18: e00b b.n 8018a32 <CDC_Transmit_FS+0x3e>
|
|
}
|
|
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
|
|
8018a1a: 887b ldrh r3, [r7, #2]
|
|
8018a1c: 461a mov r2, r3
|
|
8018a1e: 6879 ldr r1, [r7, #4]
|
|
8018a20: 4806 ldr r0, [pc, #24] @ (8018a3c <CDC_Transmit_FS+0x48>)
|
|
8018a22: f7f8 fe83 bl 801172c <USBD_CDC_SetTxBuffer>
|
|
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
|
|
8018a26: 4805 ldr r0, [pc, #20] @ (8018a3c <CDC_Transmit_FS+0x48>)
|
|
8018a28: f7f8 fec0 bl 80117ac <USBD_CDC_TransmitPacket>
|
|
8018a2c: 4603 mov r3, r0
|
|
8018a2e: 73fb strb r3, [r7, #15]
|
|
/* USER CODE END 7 */
|
|
return result;
|
|
8018a30: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8018a32: 4618 mov r0, r3
|
|
8018a34: 3710 adds r7, #16
|
|
8018a36: 46bd mov sp, r7
|
|
8018a38: bd80 pop {r7, pc}
|
|
8018a3a: bf00 nop
|
|
8018a3c: 200121bc .word 0x200121bc
|
|
|
|
08018a40 <CDC_TransmitCplt_FS>:
|
|
* @param Buf: Buffer of data to be received
|
|
* @param Len: Number of data received (in bytes)
|
|
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
|
|
*/
|
|
static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum)
|
|
{
|
|
8018a40: b480 push {r7}
|
|
8018a42: b087 sub sp, #28
|
|
8018a44: af00 add r7, sp, #0
|
|
8018a46: 60f8 str r0, [r7, #12]
|
|
8018a48: 60b9 str r1, [r7, #8]
|
|
8018a4a: 4613 mov r3, r2
|
|
8018a4c: 71fb strb r3, [r7, #7]
|
|
uint8_t result = USBD_OK;
|
|
8018a4e: 2300 movs r3, #0
|
|
8018a50: 75fb strb r3, [r7, #23]
|
|
/* USER CODE BEGIN 13 */
|
|
UNUSED(Buf);
|
|
UNUSED(Len);
|
|
UNUSED(epnum);
|
|
/* USER CODE END 13 */
|
|
return result;
|
|
8018a52: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
8018a56: 4618 mov r0, r3
|
|
8018a58: 371c adds r7, #28
|
|
8018a5a: 46bd mov sp, r7
|
|
8018a5c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018a60: 4770 bx lr
|
|
...
|
|
|
|
08018a64 <USBD_CDC_DeviceDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_CDC_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8018a64: b480 push {r7}
|
|
8018a66: b083 sub sp, #12
|
|
8018a68: af00 add r7, sp, #0
|
|
8018a6a: 4603 mov r3, r0
|
|
8018a6c: 6039 str r1, [r7, #0]
|
|
8018a6e: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_CDC_DeviceDesc);
|
|
8018a70: 683b ldr r3, [r7, #0]
|
|
8018a72: 2212 movs r2, #18
|
|
8018a74: 801a strh r2, [r3, #0]
|
|
return USBD_CDC_DeviceDesc;
|
|
8018a76: 4b03 ldr r3, [pc, #12] @ (8018a84 <USBD_CDC_DeviceDescriptor+0x20>)
|
|
}
|
|
8018a78: 4618 mov r0, r3
|
|
8018a7a: 370c adds r7, #12
|
|
8018a7c: 46bd mov sp, r7
|
|
8018a7e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018a82: 4770 bx lr
|
|
8018a84: 200000dc .word 0x200000dc
|
|
|
|
08018a88 <USBD_CDC_LangIDStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_CDC_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8018a88: b480 push {r7}
|
|
8018a8a: b083 sub sp, #12
|
|
8018a8c: af00 add r7, sp, #0
|
|
8018a8e: 4603 mov r3, r0
|
|
8018a90: 6039 str r1, [r7, #0]
|
|
8018a92: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = sizeof(USBD_LangIDDesc);
|
|
8018a94: 683b ldr r3, [r7, #0]
|
|
8018a96: 2204 movs r2, #4
|
|
8018a98: 801a strh r2, [r3, #0]
|
|
return USBD_LangIDDesc;
|
|
8018a9a: 4b03 ldr r3, [pc, #12] @ (8018aa8 <USBD_CDC_LangIDStrDescriptor+0x20>)
|
|
}
|
|
8018a9c: 4618 mov r0, r3
|
|
8018a9e: 370c adds r7, #12
|
|
8018aa0: 46bd mov sp, r7
|
|
8018aa2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018aa6: 4770 bx lr
|
|
8018aa8: 200000f0 .word 0x200000f0
|
|
|
|
08018aac <USBD_CDC_ProductStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_CDC_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8018aac: b580 push {r7, lr}
|
|
8018aae: b082 sub sp, #8
|
|
8018ab0: af00 add r7, sp, #0
|
|
8018ab2: 4603 mov r3, r0
|
|
8018ab4: 6039 str r1, [r7, #0]
|
|
8018ab6: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8018ab8: 79fb ldrb r3, [r7, #7]
|
|
8018aba: 2b00 cmp r3, #0
|
|
8018abc: d105 bne.n 8018aca <USBD_CDC_ProductStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
|
|
8018abe: 683a ldr r2, [r7, #0]
|
|
8018ac0: 4907 ldr r1, [pc, #28] @ (8018ae0 <USBD_CDC_ProductStrDescriptor+0x34>)
|
|
8018ac2: 4808 ldr r0, [pc, #32] @ (8018ae4 <USBD_CDC_ProductStrDescriptor+0x38>)
|
|
8018ac4: f7fa f8ac bl 8012c20 <USBD_GetString>
|
|
8018ac8: e004 b.n 8018ad4 <USBD_CDC_ProductStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
|
|
8018aca: 683a ldr r2, [r7, #0]
|
|
8018acc: 4904 ldr r1, [pc, #16] @ (8018ae0 <USBD_CDC_ProductStrDescriptor+0x34>)
|
|
8018ace: 4805 ldr r0, [pc, #20] @ (8018ae4 <USBD_CDC_ProductStrDescriptor+0x38>)
|
|
8018ad0: f7fa f8a6 bl 8012c20 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8018ad4: 4b02 ldr r3, [pc, #8] @ (8018ae0 <USBD_CDC_ProductStrDescriptor+0x34>)
|
|
}
|
|
8018ad6: 4618 mov r0, r3
|
|
8018ad8: 3708 adds r7, #8
|
|
8018ada: 46bd mov sp, r7
|
|
8018adc: bd80 pop {r7, pc}
|
|
8018ade: bf00 nop
|
|
8018ae0: 20013498 .word 0x20013498
|
|
8018ae4: 0801e334 .word 0x0801e334
|
|
|
|
08018ae8 <USBD_CDC_ManufacturerStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_CDC_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8018ae8: b580 push {r7, lr}
|
|
8018aea: b082 sub sp, #8
|
|
8018aec: af00 add r7, sp, #0
|
|
8018aee: 4603 mov r3, r0
|
|
8018af0: 6039 str r1, [r7, #0]
|
|
8018af2: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
|
|
8018af4: 683a ldr r2, [r7, #0]
|
|
8018af6: 4904 ldr r1, [pc, #16] @ (8018b08 <USBD_CDC_ManufacturerStrDescriptor+0x20>)
|
|
8018af8: 4804 ldr r0, [pc, #16] @ (8018b0c <USBD_CDC_ManufacturerStrDescriptor+0x24>)
|
|
8018afa: f7fa f891 bl 8012c20 <USBD_GetString>
|
|
return USBD_StrDesc;
|
|
8018afe: 4b02 ldr r3, [pc, #8] @ (8018b08 <USBD_CDC_ManufacturerStrDescriptor+0x20>)
|
|
}
|
|
8018b00: 4618 mov r0, r3
|
|
8018b02: 3708 adds r7, #8
|
|
8018b04: 46bd mov sp, r7
|
|
8018b06: bd80 pop {r7, pc}
|
|
8018b08: 20013498 .word 0x20013498
|
|
8018b0c: 0801e34c .word 0x0801e34c
|
|
|
|
08018b10 <USBD_CDC_SerialStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_CDC_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8018b10: b580 push {r7, lr}
|
|
8018b12: b082 sub sp, #8
|
|
8018b14: af00 add r7, sp, #0
|
|
8018b16: 4603 mov r3, r0
|
|
8018b18: 6039 str r1, [r7, #0]
|
|
8018b1a: 71fb strb r3, [r7, #7]
|
|
UNUSED(speed);
|
|
*length = USB_SIZ_STRING_SERIAL;
|
|
8018b1c: 683b ldr r3, [r7, #0]
|
|
8018b1e: 221a movs r2, #26
|
|
8018b20: 801a strh r2, [r3, #0]
|
|
|
|
/* Update the serial number string descriptor with the data from the unique
|
|
* ID */
|
|
Get_SerialNum();
|
|
8018b22: f000 f843 bl 8018bac <Get_SerialNum>
|
|
|
|
/* USER CODE BEGIN USBD_CDC_SerialStrDescriptor */
|
|
|
|
/* USER CODE END USBD_CDC_SerialStrDescriptor */
|
|
|
|
return (uint8_t *) USBD_StringSerial;
|
|
8018b26: 4b02 ldr r3, [pc, #8] @ (8018b30 <USBD_CDC_SerialStrDescriptor+0x20>)
|
|
}
|
|
8018b28: 4618 mov r0, r3
|
|
8018b2a: 3708 adds r7, #8
|
|
8018b2c: 46bd mov sp, r7
|
|
8018b2e: bd80 pop {r7, pc}
|
|
8018b30: 200000f4 .word 0x200000f4
|
|
|
|
08018b34 <USBD_CDC_ConfigStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_CDC_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8018b34: b580 push {r7, lr}
|
|
8018b36: b082 sub sp, #8
|
|
8018b38: af00 add r7, sp, #0
|
|
8018b3a: 4603 mov r3, r0
|
|
8018b3c: 6039 str r1, [r7, #0]
|
|
8018b3e: 71fb strb r3, [r7, #7]
|
|
if(speed == USBD_SPEED_HIGH)
|
|
8018b40: 79fb ldrb r3, [r7, #7]
|
|
8018b42: 2b00 cmp r3, #0
|
|
8018b44: d105 bne.n 8018b52 <USBD_CDC_ConfigStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
|
|
8018b46: 683a ldr r2, [r7, #0]
|
|
8018b48: 4907 ldr r1, [pc, #28] @ (8018b68 <USBD_CDC_ConfigStrDescriptor+0x34>)
|
|
8018b4a: 4808 ldr r0, [pc, #32] @ (8018b6c <USBD_CDC_ConfigStrDescriptor+0x38>)
|
|
8018b4c: f7fa f868 bl 8012c20 <USBD_GetString>
|
|
8018b50: e004 b.n 8018b5c <USBD_CDC_ConfigStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
|
|
8018b52: 683a ldr r2, [r7, #0]
|
|
8018b54: 4904 ldr r1, [pc, #16] @ (8018b68 <USBD_CDC_ConfigStrDescriptor+0x34>)
|
|
8018b56: 4805 ldr r0, [pc, #20] @ (8018b6c <USBD_CDC_ConfigStrDescriptor+0x38>)
|
|
8018b58: f7fa f862 bl 8012c20 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8018b5c: 4b02 ldr r3, [pc, #8] @ (8018b68 <USBD_CDC_ConfigStrDescriptor+0x34>)
|
|
}
|
|
8018b5e: 4618 mov r0, r3
|
|
8018b60: 3708 adds r7, #8
|
|
8018b62: 46bd mov sp, r7
|
|
8018b64: bd80 pop {r7, pc}
|
|
8018b66: bf00 nop
|
|
8018b68: 20013498 .word 0x20013498
|
|
8018b6c: 0801e360 .word 0x0801e360
|
|
|
|
08018b70 <USBD_CDC_InterfaceStrDescriptor>:
|
|
* @param speed : Current device speed
|
|
* @param length : Pointer to data length variable
|
|
* @retval Pointer to descriptor buffer
|
|
*/
|
|
uint8_t * USBD_CDC_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
|
|
{
|
|
8018b70: b580 push {r7, lr}
|
|
8018b72: b082 sub sp, #8
|
|
8018b74: af00 add r7, sp, #0
|
|
8018b76: 4603 mov r3, r0
|
|
8018b78: 6039 str r1, [r7, #0]
|
|
8018b7a: 71fb strb r3, [r7, #7]
|
|
if(speed == 0)
|
|
8018b7c: 79fb ldrb r3, [r7, #7]
|
|
8018b7e: 2b00 cmp r3, #0
|
|
8018b80: d105 bne.n 8018b8e <USBD_CDC_InterfaceStrDescriptor+0x1e>
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
|
|
8018b82: 683a ldr r2, [r7, #0]
|
|
8018b84: 4907 ldr r1, [pc, #28] @ (8018ba4 <USBD_CDC_InterfaceStrDescriptor+0x34>)
|
|
8018b86: 4808 ldr r0, [pc, #32] @ (8018ba8 <USBD_CDC_InterfaceStrDescriptor+0x38>)
|
|
8018b88: f7fa f84a bl 8012c20 <USBD_GetString>
|
|
8018b8c: e004 b.n 8018b98 <USBD_CDC_InterfaceStrDescriptor+0x28>
|
|
}
|
|
else
|
|
{
|
|
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
|
|
8018b8e: 683a ldr r2, [r7, #0]
|
|
8018b90: 4904 ldr r1, [pc, #16] @ (8018ba4 <USBD_CDC_InterfaceStrDescriptor+0x34>)
|
|
8018b92: 4805 ldr r0, [pc, #20] @ (8018ba8 <USBD_CDC_InterfaceStrDescriptor+0x38>)
|
|
8018b94: f7fa f844 bl 8012c20 <USBD_GetString>
|
|
}
|
|
return USBD_StrDesc;
|
|
8018b98: 4b02 ldr r3, [pc, #8] @ (8018ba4 <USBD_CDC_InterfaceStrDescriptor+0x34>)
|
|
}
|
|
8018b9a: 4618 mov r0, r3
|
|
8018b9c: 3708 adds r7, #8
|
|
8018b9e: 46bd mov sp, r7
|
|
8018ba0: bd80 pop {r7, pc}
|
|
8018ba2: bf00 nop
|
|
8018ba4: 20013498 .word 0x20013498
|
|
8018ba8: 0801e36c .word 0x0801e36c
|
|
|
|
08018bac <Get_SerialNum>:
|
|
* @brief Create the serial number string descriptor
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void Get_SerialNum(void)
|
|
{
|
|
8018bac: b580 push {r7, lr}
|
|
8018bae: b084 sub sp, #16
|
|
8018bb0: af00 add r7, sp, #0
|
|
uint32_t deviceserial0;
|
|
uint32_t deviceserial1;
|
|
uint32_t deviceserial2;
|
|
|
|
deviceserial0 = *(uint32_t *) DEVICE_ID1;
|
|
8018bb2: 4b0f ldr r3, [pc, #60] @ (8018bf0 <Get_SerialNum+0x44>)
|
|
8018bb4: 681b ldr r3, [r3, #0]
|
|
8018bb6: 60fb str r3, [r7, #12]
|
|
deviceserial1 = *(uint32_t *) DEVICE_ID2;
|
|
8018bb8: 4b0e ldr r3, [pc, #56] @ (8018bf4 <Get_SerialNum+0x48>)
|
|
8018bba: 681b ldr r3, [r3, #0]
|
|
8018bbc: 60bb str r3, [r7, #8]
|
|
deviceserial2 = *(uint32_t *) DEVICE_ID3;
|
|
8018bbe: 4b0e ldr r3, [pc, #56] @ (8018bf8 <Get_SerialNum+0x4c>)
|
|
8018bc0: 681b ldr r3, [r3, #0]
|
|
8018bc2: 607b str r3, [r7, #4]
|
|
|
|
deviceserial0 += deviceserial2;
|
|
8018bc4: 68fa ldr r2, [r7, #12]
|
|
8018bc6: 687b ldr r3, [r7, #4]
|
|
8018bc8: 4413 add r3, r2
|
|
8018bca: 60fb str r3, [r7, #12]
|
|
|
|
if (deviceserial0 != 0)
|
|
8018bcc: 68fb ldr r3, [r7, #12]
|
|
8018bce: 2b00 cmp r3, #0
|
|
8018bd0: d009 beq.n 8018be6 <Get_SerialNum+0x3a>
|
|
{
|
|
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
|
|
8018bd2: 2208 movs r2, #8
|
|
8018bd4: 4909 ldr r1, [pc, #36] @ (8018bfc <Get_SerialNum+0x50>)
|
|
8018bd6: 68f8 ldr r0, [r7, #12]
|
|
8018bd8: f000 f814 bl 8018c04 <IntToUnicode>
|
|
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
|
|
8018bdc: 2204 movs r2, #4
|
|
8018bde: 4908 ldr r1, [pc, #32] @ (8018c00 <Get_SerialNum+0x54>)
|
|
8018be0: 68b8 ldr r0, [r7, #8]
|
|
8018be2: f000 f80f bl 8018c04 <IntToUnicode>
|
|
}
|
|
}
|
|
8018be6: bf00 nop
|
|
8018be8: 3710 adds r7, #16
|
|
8018bea: 46bd mov sp, r7
|
|
8018bec: bd80 pop {r7, pc}
|
|
8018bee: bf00 nop
|
|
8018bf0: 1fff7590 .word 0x1fff7590
|
|
8018bf4: 1fff7594 .word 0x1fff7594
|
|
8018bf8: 1fff7598 .word 0x1fff7598
|
|
8018bfc: 200000f6 .word 0x200000f6
|
|
8018c00: 20000106 .word 0x20000106
|
|
|
|
08018c04 <IntToUnicode>:
|
|
* @param pbuf: pointer to the buffer
|
|
* @param len: buffer length
|
|
* @retval None
|
|
*/
|
|
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
|
|
{
|
|
8018c04: b480 push {r7}
|
|
8018c06: b087 sub sp, #28
|
|
8018c08: af00 add r7, sp, #0
|
|
8018c0a: 60f8 str r0, [r7, #12]
|
|
8018c0c: 60b9 str r1, [r7, #8]
|
|
8018c0e: 4613 mov r3, r2
|
|
8018c10: 71fb strb r3, [r7, #7]
|
|
uint8_t idx = 0;
|
|
8018c12: 2300 movs r3, #0
|
|
8018c14: 75fb strb r3, [r7, #23]
|
|
|
|
for (idx = 0; idx < len; idx++)
|
|
8018c16: 2300 movs r3, #0
|
|
8018c18: 75fb strb r3, [r7, #23]
|
|
8018c1a: e027 b.n 8018c6c <IntToUnicode+0x68>
|
|
{
|
|
if (((value >> 28)) < 0xA)
|
|
8018c1c: 68fb ldr r3, [r7, #12]
|
|
8018c1e: 0f1b lsrs r3, r3, #28
|
|
8018c20: 2b09 cmp r3, #9
|
|
8018c22: d80b bhi.n 8018c3c <IntToUnicode+0x38>
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + '0';
|
|
8018c24: 68fb ldr r3, [r7, #12]
|
|
8018c26: 0f1b lsrs r3, r3, #28
|
|
8018c28: b2da uxtb r2, r3
|
|
8018c2a: 7dfb ldrb r3, [r7, #23]
|
|
8018c2c: 005b lsls r3, r3, #1
|
|
8018c2e: 4619 mov r1, r3
|
|
8018c30: 68bb ldr r3, [r7, #8]
|
|
8018c32: 440b add r3, r1
|
|
8018c34: 3230 adds r2, #48 @ 0x30
|
|
8018c36: b2d2 uxtb r2, r2
|
|
8018c38: 701a strb r2, [r3, #0]
|
|
8018c3a: e00a b.n 8018c52 <IntToUnicode+0x4e>
|
|
}
|
|
else
|
|
{
|
|
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
|
|
8018c3c: 68fb ldr r3, [r7, #12]
|
|
8018c3e: 0f1b lsrs r3, r3, #28
|
|
8018c40: b2da uxtb r2, r3
|
|
8018c42: 7dfb ldrb r3, [r7, #23]
|
|
8018c44: 005b lsls r3, r3, #1
|
|
8018c46: 4619 mov r1, r3
|
|
8018c48: 68bb ldr r3, [r7, #8]
|
|
8018c4a: 440b add r3, r1
|
|
8018c4c: 3237 adds r2, #55 @ 0x37
|
|
8018c4e: b2d2 uxtb r2, r2
|
|
8018c50: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
value = value << 4;
|
|
8018c52: 68fb ldr r3, [r7, #12]
|
|
8018c54: 011b lsls r3, r3, #4
|
|
8018c56: 60fb str r3, [r7, #12]
|
|
|
|
pbuf[2 * idx + 1] = 0;
|
|
8018c58: 7dfb ldrb r3, [r7, #23]
|
|
8018c5a: 005b lsls r3, r3, #1
|
|
8018c5c: 3301 adds r3, #1
|
|
8018c5e: 68ba ldr r2, [r7, #8]
|
|
8018c60: 4413 add r3, r2
|
|
8018c62: 2200 movs r2, #0
|
|
8018c64: 701a strb r2, [r3, #0]
|
|
for (idx = 0; idx < len; idx++)
|
|
8018c66: 7dfb ldrb r3, [r7, #23]
|
|
8018c68: 3301 adds r3, #1
|
|
8018c6a: 75fb strb r3, [r7, #23]
|
|
8018c6c: 7dfa ldrb r2, [r7, #23]
|
|
8018c6e: 79fb ldrb r3, [r7, #7]
|
|
8018c70: 429a cmp r2, r3
|
|
8018c72: d3d3 bcc.n 8018c1c <IntToUnicode+0x18>
|
|
}
|
|
}
|
|
8018c74: bf00 nop
|
|
8018c76: bf00 nop
|
|
8018c78: 371c adds r7, #28
|
|
8018c7a: 46bd mov sp, r7
|
|
8018c7c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018c80: 4770 bx lr
|
|
|
|
08018c82 <LL_AHB2_GRP1_EnableClock>:
|
|
{
|
|
8018c82: b480 push {r7}
|
|
8018c84: b085 sub sp, #20
|
|
8018c86: af00 add r7, sp, #0
|
|
8018c88: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->AHB2ENR, Periphs);
|
|
8018c8a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8018c8e: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8018c90: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8018c94: 687b ldr r3, [r7, #4]
|
|
8018c96: 4313 orrs r3, r2
|
|
8018c98: 64cb str r3, [r1, #76] @ 0x4c
|
|
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
|
|
8018c9a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8018c9e: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8018ca0: 687b ldr r3, [r7, #4]
|
|
8018ca2: 4013 ands r3, r2
|
|
8018ca4: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8018ca6: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8018ca8: bf00 nop
|
|
8018caa: 3714 adds r7, #20
|
|
8018cac: 46bd mov sp, r7
|
|
8018cae: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018cb2: 4770 bx lr
|
|
|
|
08018cb4 <LL_APB1_GRP1_EnableClock>:
|
|
{
|
|
8018cb4: b480 push {r7}
|
|
8018cb6: b085 sub sp, #20
|
|
8018cb8: af00 add r7, sp, #0
|
|
8018cba: 6078 str r0, [r7, #4]
|
|
SET_BIT(RCC->APB1ENR1, Periphs);
|
|
8018cbc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8018cc0: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8018cc2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
|
|
8018cc6: 687b ldr r3, [r7, #4]
|
|
8018cc8: 4313 orrs r3, r2
|
|
8018cca: 658b str r3, [r1, #88] @ 0x58
|
|
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
|
|
8018ccc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
|
|
8018cd0: 6d9a ldr r2, [r3, #88] @ 0x58
|
|
8018cd2: 687b ldr r3, [r7, #4]
|
|
8018cd4: 4013 ands r3, r2
|
|
8018cd6: 60fb str r3, [r7, #12]
|
|
(void)tmpreg;
|
|
8018cd8: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8018cda: bf00 nop
|
|
8018cdc: 3714 adds r7, #20
|
|
8018cde: 46bd mov sp, r7
|
|
8018ce0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8018ce4: 4770 bx lr
|
|
...
|
|
|
|
08018ce8 <HAL_PCD_MspInit>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
|
|
#else
|
|
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8018ce8: b580 push {r7, lr}
|
|
8018cea: b09c sub sp, #112 @ 0x70
|
|
8018cec: af00 add r7, sp, #0
|
|
8018cee: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8018cf0: f107 035c add.w r3, r7, #92 @ 0x5c
|
|
8018cf4: 2200 movs r2, #0
|
|
8018cf6: 601a str r2, [r3, #0]
|
|
8018cf8: 605a str r2, [r3, #4]
|
|
8018cfa: 609a str r2, [r3, #8]
|
|
8018cfc: 60da str r2, [r3, #12]
|
|
8018cfe: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8018d00: f107 030c add.w r3, r7, #12
|
|
8018d04: 2250 movs r2, #80 @ 0x50
|
|
8018d06: 2100 movs r1, #0
|
|
8018d08: 4618 mov r0, r3
|
|
8018d0a: f001 fafb bl 801a304 <memset>
|
|
if(pcdHandle->Instance==USB)
|
|
8018d0e: 687b ldr r3, [r7, #4]
|
|
8018d10: 681b ldr r3, [r3, #0]
|
|
8018d12: 4a23 ldr r2, [pc, #140] @ (8018da0 <HAL_PCD_MspInit+0xb8>)
|
|
8018d14: 4293 cmp r3, r2
|
|
8018d16: d13e bne.n 8018d96 <HAL_PCD_MspInit+0xae>
|
|
|
|
/* USER CODE END USB_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
|
8018d18: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8018d1c: 60fb str r3, [r7, #12]
|
|
PeriphClkInitStruct.PLLSAI1.PLLN = 24;
|
|
8018d1e: 2318 movs r3, #24
|
|
8018d20: 613b str r3, [r7, #16]
|
|
PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2;
|
|
8018d22: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8018d26: 617b str r3, [r7, #20]
|
|
PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2;
|
|
8018d28: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8018d2c: 61bb str r3, [r7, #24]
|
|
PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2;
|
|
8018d2e: f04f 5300 mov.w r3, #536870912 @ 0x20000000
|
|
8018d32: 61fb str r3, [r7, #28]
|
|
PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK;
|
|
8018d34: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8018d38: 623b str r3, [r7, #32]
|
|
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
|
8018d3a: f04f 6380 mov.w r3, #67108864 @ 0x4000000
|
|
8018d3e: 643b str r3, [r7, #64] @ 0x40
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8018d40: f107 030c add.w r3, r7, #12
|
|
8018d44: 4618 mov r0, r3
|
|
8018d46: f7f3 fc87 bl 800c658 <HAL_RCCEx_PeriphCLKConfig>
|
|
8018d4a: 4603 mov r3, r0
|
|
8018d4c: 2b00 cmp r3, #0
|
|
8018d4e: d001 beq.n 8018d54 <HAL_PCD_MspInit+0x6c>
|
|
{
|
|
Error_Handler();
|
|
8018d50: f7ec fb10 bl 8005374 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8018d54: 2001 movs r0, #1
|
|
8018d56: f7ff ff94 bl 8018c82 <LL_AHB2_GRP1_EnableClock>
|
|
/**USB GPIO Configuration
|
|
PA11 ------> USB_DM
|
|
PA12 ------> USB_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
|
8018d5a: f44f 53c0 mov.w r3, #6144 @ 0x1800
|
|
8018d5e: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8018d60: 2302 movs r3, #2
|
|
8018d62: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8018d64: 2300 movs r3, #0
|
|
8018d66: 667b str r3, [r7, #100] @ 0x64
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8018d68: 2303 movs r3, #3
|
|
8018d6a: 66bb str r3, [r7, #104] @ 0x68
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_USB;
|
|
8018d6c: 230a movs r3, #10
|
|
8018d6e: 66fb str r3, [r7, #108] @ 0x6c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8018d70: f107 035c add.w r3, r7, #92 @ 0x5c
|
|
8018d74: 4619 mov r1, r3
|
|
8018d76: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8018d7a: f7ee fab9 bl 80072f0 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_CLK_ENABLE();
|
|
8018d7e: f04f 6080 mov.w r0, #67108864 @ 0x4000000
|
|
8018d82: f7ff ff97 bl 8018cb4 <LL_APB1_GRP1_EnableClock>
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(USB_LP_IRQn, 5, 0);
|
|
8018d86: 2200 movs r2, #0
|
|
8018d88: 2105 movs r1, #5
|
|
8018d8a: 2014 movs r0, #20
|
|
8018d8c: f7ed ff1e bl 8006bcc <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USB_LP_IRQn);
|
|
8018d90: 2014 movs r0, #20
|
|
8018d92: f7ed ff35 bl 8006c00 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USB_MspInit 1 */
|
|
|
|
/* USER CODE END USB_MspInit 1 */
|
|
}
|
|
}
|
|
8018d96: bf00 nop
|
|
8018d98: 3770 adds r7, #112 @ 0x70
|
|
8018d9a: 46bd mov sp, r7
|
|
8018d9c: bd80 pop {r7, pc}
|
|
8018d9e: bf00 nop
|
|
8018da0: 40006800 .word 0x40006800
|
|
|
|
08018da4 <HAL_PCD_SetupStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8018da4: b580 push {r7, lr}
|
|
8018da6: b082 sub sp, #8
|
|
8018da8: af00 add r7, sp, #0
|
|
8018daa: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_SetupStageCallback_PreTreatment */
|
|
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
|
|
8018dac: 687b ldr r3, [r7, #4]
|
|
8018dae: f8d3 22d8 ldr.w r2, [r3, #728] @ 0x2d8
|
|
8018db2: 687b ldr r3, [r7, #4]
|
|
8018db4: f503 7326 add.w r3, r3, #664 @ 0x298
|
|
8018db8: 4619 mov r1, r3
|
|
8018dba: 4610 mov r0, r2
|
|
8018dbc: f7f8 fe1f bl 80119fe <USBD_LL_SetupStage>
|
|
/* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_SetupStageCallback_PostTreatment */
|
|
}
|
|
8018dc0: bf00 nop
|
|
8018dc2: 3708 adds r7, #8
|
|
8018dc4: 46bd mov sp, r7
|
|
8018dc6: bd80 pop {r7, pc}
|
|
|
|
08018dc8 <HAL_PCD_DataOutStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8018dc8: b580 push {r7, lr}
|
|
8018dca: b082 sub sp, #8
|
|
8018dcc: af00 add r7, sp, #0
|
|
8018dce: 6078 str r0, [r7, #4]
|
|
8018dd0: 460b mov r3, r1
|
|
8018dd2: 70fb strb r3, [r7, #3]
|
|
/* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_DataOutStageCallback_PreTreatment */
|
|
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
|
|
8018dd4: 687b ldr r3, [r7, #4]
|
|
8018dd6: f8d3 02d8 ldr.w r0, [r3, #728] @ 0x2d8
|
|
8018dda: 78fa ldrb r2, [r7, #3]
|
|
8018ddc: 6879 ldr r1, [r7, #4]
|
|
8018dde: 4613 mov r3, r2
|
|
8018de0: 009b lsls r3, r3, #2
|
|
8018de2: 4413 add r3, r2
|
|
8018de4: 00db lsls r3, r3, #3
|
|
8018de6: 440b add r3, r1
|
|
8018de8: f503 73b2 add.w r3, r3, #356 @ 0x164
|
|
8018dec: 681a ldr r2, [r3, #0]
|
|
8018dee: 78fb ldrb r3, [r7, #3]
|
|
8018df0: 4619 mov r1, r3
|
|
8018df2: f7f8 fe59 bl 8011aa8 <USBD_LL_DataOutStage>
|
|
/* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_DataOutStageCallback_PostTreatment */
|
|
}
|
|
8018df6: bf00 nop
|
|
8018df8: 3708 adds r7, #8
|
|
8018dfa: 46bd mov sp, r7
|
|
8018dfc: bd80 pop {r7, pc}
|
|
|
|
08018dfe <HAL_PCD_DataInStageCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#else
|
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8018dfe: b580 push {r7, lr}
|
|
8018e00: b082 sub sp, #8
|
|
8018e02: af00 add r7, sp, #0
|
|
8018e04: 6078 str r0, [r7, #4]
|
|
8018e06: 460b mov r3, r1
|
|
8018e08: 70fb strb r3, [r7, #3]
|
|
/* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_DataInStageCallback_PreTreatment */
|
|
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
|
|
8018e0a: 687b ldr r3, [r7, #4]
|
|
8018e0c: f8d3 02d8 ldr.w r0, [r3, #728] @ 0x2d8
|
|
8018e10: 78fa ldrb r2, [r7, #3]
|
|
8018e12: 6879 ldr r1, [r7, #4]
|
|
8018e14: 4613 mov r3, r2
|
|
8018e16: 009b lsls r3, r3, #2
|
|
8018e18: 4413 add r3, r2
|
|
8018e1a: 00db lsls r3, r3, #3
|
|
8018e1c: 440b add r3, r1
|
|
8018e1e: 3324 adds r3, #36 @ 0x24
|
|
8018e20: 681a ldr r2, [r3, #0]
|
|
8018e22: 78fb ldrb r3, [r7, #3]
|
|
8018e24: 4619 mov r1, r3
|
|
8018e26: f7f8 fefb bl 8011c20 <USBD_LL_DataInStage>
|
|
/* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_DataInStageCallback_PostTreatment */
|
|
}
|
|
8018e2a: bf00 nop
|
|
8018e2c: 3708 adds r7, #8
|
|
8018e2e: 46bd mov sp, r7
|
|
8018e30: bd80 pop {r7, pc}
|
|
|
|
08018e32 <HAL_PCD_SOFCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8018e32: b580 push {r7, lr}
|
|
8018e34: b082 sub sp, #8
|
|
8018e36: af00 add r7, sp, #0
|
|
8018e38: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_SOFCallback_PreTreatment */
|
|
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
|
|
8018e3a: 687b ldr r3, [r7, #4]
|
|
8018e3c: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8018e40: 4618 mov r0, r3
|
|
8018e42: f7f9 f83f bl 8011ec4 <USBD_LL_SOF>
|
|
/* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_SOFCallback_PostTreatment */
|
|
}
|
|
8018e46: bf00 nop
|
|
8018e48: 3708 adds r7, #8
|
|
8018e4a: 46bd mov sp, r7
|
|
8018e4c: bd80 pop {r7, pc}
|
|
|
|
08018e4e <HAL_PCD_ResetCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8018e4e: b580 push {r7, lr}
|
|
8018e50: b084 sub sp, #16
|
|
8018e52: af00 add r7, sp, #0
|
|
8018e54: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_ResetCallback_PreTreatment */
|
|
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
|
|
8018e56: 2301 movs r3, #1
|
|
8018e58: 73fb strb r3, [r7, #15]
|
|
|
|
if ( hpcd->Init.speed != PCD_SPEED_FULL)
|
|
8018e5a: 687b ldr r3, [r7, #4]
|
|
8018e5c: 795b ldrb r3, [r3, #5]
|
|
8018e5e: 2b02 cmp r3, #2
|
|
8018e60: d001 beq.n 8018e66 <HAL_PCD_ResetCallback+0x18>
|
|
{
|
|
Error_Handler();
|
|
8018e62: f7ec fa87 bl 8005374 <Error_Handler>
|
|
}
|
|
/* Set Speed. */
|
|
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
|
|
8018e66: 687b ldr r3, [r7, #4]
|
|
8018e68: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8018e6c: 7bfa ldrb r2, [r7, #15]
|
|
8018e6e: 4611 mov r1, r2
|
|
8018e70: 4618 mov r0, r3
|
|
8018e72: f7f8 ffe3 bl 8011e3c <USBD_LL_SetSpeed>
|
|
|
|
/* Reset Device. */
|
|
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
|
|
8018e76: 687b ldr r3, [r7, #4]
|
|
8018e78: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8018e7c: 4618 mov r0, r3
|
|
8018e7e: f7f8 ff8a bl 8011d96 <USBD_LL_Reset>
|
|
/* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_ResetCallback_PostTreatment */
|
|
}
|
|
8018e82: bf00 nop
|
|
8018e84: 3710 adds r7, #16
|
|
8018e86: 46bd mov sp, r7
|
|
8018e88: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08018e8c <HAL_PCD_SuspendCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8018e8c: b580 push {r7, lr}
|
|
8018e8e: b082 sub sp, #8
|
|
8018e90: af00 add r7, sp, #0
|
|
8018e92: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_SuspendCallback_PreTreatment */
|
|
/* Inform USB library that core enters in suspend Mode. */
|
|
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
|
|
8018e94: 687b ldr r3, [r7, #4]
|
|
8018e96: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8018e9a: 4618 mov r0, r3
|
|
8018e9c: f7f8 ffde bl 8011e5c <USBD_LL_Suspend>
|
|
/* Enter in STOP mode. */
|
|
/* USER CODE BEGIN 2 */
|
|
if (hpcd->Init.low_power_enable)
|
|
8018ea0: 687b ldr r3, [r7, #4]
|
|
8018ea2: 7a5b ldrb r3, [r3, #9]
|
|
8018ea4: 2b00 cmp r3, #0
|
|
8018ea6: d005 beq.n 8018eb4 <HAL_PCD_SuspendCallback+0x28>
|
|
{
|
|
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
8018ea8: 4b04 ldr r3, [pc, #16] @ (8018ebc <HAL_PCD_SuspendCallback+0x30>)
|
|
8018eaa: 691b ldr r3, [r3, #16]
|
|
8018eac: 4a03 ldr r2, [pc, #12] @ (8018ebc <HAL_PCD_SuspendCallback+0x30>)
|
|
8018eae: f043 0306 orr.w r3, r3, #6
|
|
8018eb2: 6113 str r3, [r2, #16]
|
|
}
|
|
/* USER CODE END 2 */
|
|
/* USER CODE BEGIN HAL_PCD_SuspendCallback_PostTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_SuspendCallback_PostTreatment */
|
|
}
|
|
8018eb4: bf00 nop
|
|
8018eb6: 3708 adds r7, #8
|
|
8018eb8: 46bd mov sp, r7
|
|
8018eba: bd80 pop {r7, pc}
|
|
8018ebc: e000ed00 .word 0xe000ed00
|
|
|
|
08018ec0 <HAL_PCD_ResumeCallback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#else
|
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8018ec0: b580 push {r7, lr}
|
|
8018ec2: b082 sub sp, #8
|
|
8018ec4: af00 add r7, sp, #0
|
|
8018ec6: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_ResumeCallback_PreTreatment */
|
|
|
|
/* USER CODE BEGIN 3 */
|
|
if (hpcd->Init.low_power_enable)
|
|
8018ec8: 687b ldr r3, [r7, #4]
|
|
8018eca: 7a5b ldrb r3, [r3, #9]
|
|
8018ecc: 2b00 cmp r3, #0
|
|
8018ece: d007 beq.n 8018ee0 <HAL_PCD_ResumeCallback+0x20>
|
|
{
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register. */
|
|
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
8018ed0: 4b08 ldr r3, [pc, #32] @ (8018ef4 <HAL_PCD_ResumeCallback+0x34>)
|
|
8018ed2: 691b ldr r3, [r3, #16]
|
|
8018ed4: 4a07 ldr r2, [pc, #28] @ (8018ef4 <HAL_PCD_ResumeCallback+0x34>)
|
|
8018ed6: f023 0306 bic.w r3, r3, #6
|
|
8018eda: 6113 str r3, [r2, #16]
|
|
SystemClockConfig_Resume();
|
|
8018edc: f000 f9fa bl 80192d4 <SystemClockConfig_Resume>
|
|
}
|
|
/* USER CODE END 3 */
|
|
|
|
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
|
|
8018ee0: 687b ldr r3, [r7, #4]
|
|
8018ee2: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
8018ee6: 4618 mov r0, r3
|
|
8018ee8: f7f8 ffd4 bl 8011e94 <USBD_LL_Resume>
|
|
/* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */
|
|
|
|
/* USER CODE END HAL_PCD_ResumeCallback_PostTreatment */
|
|
}
|
|
8018eec: bf00 nop
|
|
8018eee: 3708 adds r7, #8
|
|
8018ef0: 46bd mov sp, r7
|
|
8018ef2: bd80 pop {r7, pc}
|
|
8018ef4: e000ed00 .word 0xe000ed00
|
|
|
|
08018ef8 <USBD_LL_Init>:
|
|
* @brief Initializes the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8018ef8: b580 push {r7, lr}
|
|
8018efa: b082 sub sp, #8
|
|
8018efc: af00 add r7, sp, #0
|
|
8018efe: 6078 str r0, [r7, #4]
|
|
/* Init USB Ip. */
|
|
hpcd_USB_FS.pData = pdev;
|
|
8018f00: 4a2c ldr r2, [pc, #176] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f02: 687b ldr r3, [r7, #4]
|
|
8018f04: f8c2 32d8 str.w r3, [r2, #728] @ 0x2d8
|
|
/* Link the driver to the stack. */
|
|
pdev->pData = &hpcd_USB_FS;
|
|
8018f08: 687b ldr r3, [r7, #4]
|
|
8018f0a: 4a2a ldr r2, [pc, #168] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f0c: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
|
|
/* Enable USB power on Pwrctrl CR2 register. */
|
|
HAL_PWREx_EnableVddUSB();
|
|
8018f10: f7f2 f834 bl 800af7c <HAL_PWREx_EnableVddUSB>
|
|
|
|
hpcd_USB_FS.Instance = USB;
|
|
8018f14: 4b27 ldr r3, [pc, #156] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f16: 4a28 ldr r2, [pc, #160] @ (8018fb8 <USBD_LL_Init+0xc0>)
|
|
8018f18: 601a str r2, [r3, #0]
|
|
hpcd_USB_FS.Init.dev_endpoints = 8;
|
|
8018f1a: 4b26 ldr r3, [pc, #152] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f1c: 2208 movs r2, #8
|
|
8018f1e: 711a strb r2, [r3, #4]
|
|
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
|
|
8018f20: 4b24 ldr r3, [pc, #144] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f22: 2202 movs r2, #2
|
|
8018f24: 715a strb r2, [r3, #5]
|
|
hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
|
8018f26: 4b23 ldr r3, [pc, #140] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f28: 2202 movs r2, #2
|
|
8018f2a: 71da strb r2, [r3, #7]
|
|
hpcd_USB_FS.Init.Sof_enable = DISABLE;
|
|
8018f2c: 4b21 ldr r3, [pc, #132] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f2e: 2200 movs r2, #0
|
|
8018f30: 721a strb r2, [r3, #8]
|
|
hpcd_USB_FS.Init.low_power_enable = DISABLE;
|
|
8018f32: 4b20 ldr r3, [pc, #128] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f34: 2200 movs r2, #0
|
|
8018f36: 725a strb r2, [r3, #9]
|
|
hpcd_USB_FS.Init.lpm_enable = DISABLE;
|
|
8018f38: 4b1e ldr r3, [pc, #120] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f3a: 2200 movs r2, #0
|
|
8018f3c: 729a strb r2, [r3, #10]
|
|
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
|
|
8018f3e: 4b1d ldr r3, [pc, #116] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f40: 2200 movs r2, #0
|
|
8018f42: 72da strb r2, [r3, #11]
|
|
/* register Msp Callbacks (before the Init) */
|
|
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPINIT_CB_ID, PCD_MspInit);
|
|
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPDEINIT_CB_ID, PCD_MspDeInit);
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
|
|
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
|
|
8018f44: 481b ldr r0, [pc, #108] @ (8018fb4 <USBD_LL_Init+0xbc>)
|
|
8018f46: f7f0 fab9 bl 80094bc <HAL_PCD_Init>
|
|
8018f4a: 4603 mov r3, r0
|
|
8018f4c: 2b00 cmp r3, #0
|
|
8018f4e: d001 beq.n 8018f54 <USBD_LL_Init+0x5c>
|
|
{
|
|
Error_Handler( );
|
|
8018f50: f7ec fa10 bl 8005374 <Error_Handler>
|
|
/* USER CODE BEGIN RegisterCallBackSecondPart */
|
|
|
|
/* USER CODE END RegisterCallBackSecondPart */
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
/* USER CODE BEGIN EndPoint_Configuration */
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
|
|
8018f54: 687b ldr r3, [r7, #4]
|
|
8018f56: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
8018f5a: 2318 movs r3, #24
|
|
8018f5c: 2200 movs r2, #0
|
|
8018f5e: 2100 movs r1, #0
|
|
8018f60: f7f1 ff81 bl 800ae66 <HAL_PCDEx_PMAConfig>
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
|
|
8018f64: 687b ldr r3, [r7, #4]
|
|
8018f66: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
8018f6a: 2358 movs r3, #88 @ 0x58
|
|
8018f6c: 2200 movs r2, #0
|
|
8018f6e: 2180 movs r1, #128 @ 0x80
|
|
8018f70: f7f1 ff79 bl 800ae66 <HAL_PCDEx_PMAConfig>
|
|
/* USER CODE END EndPoint_Configuration */
|
|
/* USER CODE BEGIN EndPoint_Configuration_CDC */
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
|
|
8018f74: 687b ldr r3, [r7, #4]
|
|
8018f76: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
8018f7a: 23c0 movs r3, #192 @ 0xc0
|
|
8018f7c: 2200 movs r2, #0
|
|
8018f7e: 2181 movs r1, #129 @ 0x81
|
|
8018f80: f7f1 ff71 bl 800ae66 <HAL_PCDEx_PMAConfig>
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
|
|
8018f84: 687b ldr r3, [r7, #4]
|
|
8018f86: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
8018f8a: f44f 7388 mov.w r3, #272 @ 0x110
|
|
8018f8e: 2200 movs r2, #0
|
|
8018f90: 2101 movs r1, #1
|
|
8018f92: f7f1 ff68 bl 800ae66 <HAL_PCDEx_PMAConfig>
|
|
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
|
|
8018f96: 687b ldr r3, [r7, #4]
|
|
8018f98: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
8018f9c: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8018fa0: 2200 movs r2, #0
|
|
8018fa2: 2182 movs r1, #130 @ 0x82
|
|
8018fa4: f7f1 ff5f bl 800ae66 <HAL_PCDEx_PMAConfig>
|
|
/* USER CODE END EndPoint_Configuration_CDC */
|
|
return USBD_OK;
|
|
8018fa8: 2300 movs r3, #0
|
|
}
|
|
8018faa: 4618 mov r0, r3
|
|
8018fac: 3708 adds r7, #8
|
|
8018fae: 46bd mov sp, r7
|
|
8018fb0: bd80 pop {r7, pc}
|
|
8018fb2: bf00 nop
|
|
8018fb4: 20013698 .word 0x20013698
|
|
8018fb8: 40006800 .word 0x40006800
|
|
|
|
08018fbc <USBD_LL_Start>:
|
|
* @brief Starts the low level portion of the device driver.
|
|
* @param pdev: Device handle
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
|
{
|
|
8018fbc: b580 push {r7, lr}
|
|
8018fbe: b084 sub sp, #16
|
|
8018fc0: af00 add r7, sp, #0
|
|
8018fc2: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8018fc4: 2300 movs r3, #0
|
|
8018fc6: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8018fc8: 2300 movs r3, #0
|
|
8018fca: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_Start(pdev->pData);
|
|
8018fcc: 687b ldr r3, [r7, #4]
|
|
8018fce: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
8018fd2: 4618 mov r0, r3
|
|
8018fd4: f7f0 fb40 bl 8009658 <HAL_PCD_Start>
|
|
8018fd8: 4603 mov r3, r0
|
|
8018fda: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8018fdc: 7bfb ldrb r3, [r7, #15]
|
|
8018fde: 4618 mov r0, r3
|
|
8018fe0: f000 f97e bl 80192e0 <USBD_Get_USB_Status>
|
|
8018fe4: 4603 mov r3, r0
|
|
8018fe6: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8018fe8: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8018fea: 4618 mov r0, r3
|
|
8018fec: 3710 adds r7, #16
|
|
8018fee: 46bd mov sp, r7
|
|
8018ff0: bd80 pop {r7, pc}
|
|
|
|
08018ff2 <USBD_LL_OpenEP>:
|
|
* @param ep_type: Endpoint type
|
|
* @param ep_mps: Endpoint max packet size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
|
|
{
|
|
8018ff2: b580 push {r7, lr}
|
|
8018ff4: b084 sub sp, #16
|
|
8018ff6: af00 add r7, sp, #0
|
|
8018ff8: 6078 str r0, [r7, #4]
|
|
8018ffa: 4608 mov r0, r1
|
|
8018ffc: 4611 mov r1, r2
|
|
8018ffe: 461a mov r2, r3
|
|
8019000: 4603 mov r3, r0
|
|
8019002: 70fb strb r3, [r7, #3]
|
|
8019004: 460b mov r3, r1
|
|
8019006: 70bb strb r3, [r7, #2]
|
|
8019008: 4613 mov r3, r2
|
|
801900a: 803b strh r3, [r7, #0]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
801900c: 2300 movs r3, #0
|
|
801900e: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8019010: 2300 movs r3, #0
|
|
8019012: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
|
|
8019014: 687b ldr r3, [r7, #4]
|
|
8019016: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
801901a: 78bb ldrb r3, [r7, #2]
|
|
801901c: 883a ldrh r2, [r7, #0]
|
|
801901e: 78f9 ldrb r1, [r7, #3]
|
|
8019020: f7f0 fc87 bl 8009932 <HAL_PCD_EP_Open>
|
|
8019024: 4603 mov r3, r0
|
|
8019026: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8019028: 7bfb ldrb r3, [r7, #15]
|
|
801902a: 4618 mov r0, r3
|
|
801902c: f000 f958 bl 80192e0 <USBD_Get_USB_Status>
|
|
8019030: 4603 mov r3, r0
|
|
8019032: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8019034: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8019036: 4618 mov r0, r3
|
|
8019038: 3710 adds r7, #16
|
|
801903a: 46bd mov sp, r7
|
|
801903c: bd80 pop {r7, pc}
|
|
|
|
0801903e <USBD_LL_CloseEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
801903e: b580 push {r7, lr}
|
|
8019040: b084 sub sp, #16
|
|
8019042: af00 add r7, sp, #0
|
|
8019044: 6078 str r0, [r7, #4]
|
|
8019046: 460b mov r3, r1
|
|
8019048: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
801904a: 2300 movs r3, #0
|
|
801904c: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
801904e: 2300 movs r3, #0
|
|
8019050: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
|
|
8019052: 687b ldr r3, [r7, #4]
|
|
8019054: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
8019058: 78fa ldrb r2, [r7, #3]
|
|
801905a: 4611 mov r1, r2
|
|
801905c: 4618 mov r0, r3
|
|
801905e: f7f0 fcc7 bl 80099f0 <HAL_PCD_EP_Close>
|
|
8019062: 4603 mov r3, r0
|
|
8019064: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8019066: 7bfb ldrb r3, [r7, #15]
|
|
8019068: 4618 mov r0, r3
|
|
801906a: f000 f939 bl 80192e0 <USBD_Get_USB_Status>
|
|
801906e: 4603 mov r3, r0
|
|
8019070: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8019072: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8019074: 4618 mov r0, r3
|
|
8019076: 3710 adds r7, #16
|
|
8019078: 46bd mov sp, r7
|
|
801907a: bd80 pop {r7, pc}
|
|
|
|
0801907c <USBD_LL_StallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
801907c: b580 push {r7, lr}
|
|
801907e: b084 sub sp, #16
|
|
8019080: af00 add r7, sp, #0
|
|
8019082: 6078 str r0, [r7, #4]
|
|
8019084: 460b mov r3, r1
|
|
8019086: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8019088: 2300 movs r3, #0
|
|
801908a: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
801908c: 2300 movs r3, #0
|
|
801908e: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
|
|
8019090: 687b ldr r3, [r7, #4]
|
|
8019092: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
8019096: 78fa ldrb r2, [r7, #3]
|
|
8019098: 4611 mov r1, r2
|
|
801909a: 4618 mov r0, r3
|
|
801909c: f7f0 fd70 bl 8009b80 <HAL_PCD_EP_SetStall>
|
|
80190a0: 4603 mov r3, r0
|
|
80190a2: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80190a4: 7bfb ldrb r3, [r7, #15]
|
|
80190a6: 4618 mov r0, r3
|
|
80190a8: f000 f91a bl 80192e0 <USBD_Get_USB_Status>
|
|
80190ac: 4603 mov r3, r0
|
|
80190ae: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80190b0: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80190b2: 4618 mov r0, r3
|
|
80190b4: 3710 adds r7, #16
|
|
80190b6: 46bd mov sp, r7
|
|
80190b8: bd80 pop {r7, pc}
|
|
|
|
080190ba <USBD_LL_ClearStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
80190ba: b580 push {r7, lr}
|
|
80190bc: b084 sub sp, #16
|
|
80190be: af00 add r7, sp, #0
|
|
80190c0: 6078 str r0, [r7, #4]
|
|
80190c2: 460b mov r3, r1
|
|
80190c4: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80190c6: 2300 movs r3, #0
|
|
80190c8: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80190ca: 2300 movs r3, #0
|
|
80190cc: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
|
80190ce: 687b ldr r3, [r7, #4]
|
|
80190d0: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
80190d4: 78fa ldrb r2, [r7, #3]
|
|
80190d6: 4611 mov r1, r2
|
|
80190d8: 4618 mov r0, r3
|
|
80190da: f7f0 fda3 bl 8009c24 <HAL_PCD_EP_ClrStall>
|
|
80190de: 4603 mov r3, r0
|
|
80190e0: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80190e2: 7bfb ldrb r3, [r7, #15]
|
|
80190e4: 4618 mov r0, r3
|
|
80190e6: f000 f8fb bl 80192e0 <USBD_Get_USB_Status>
|
|
80190ea: 4603 mov r3, r0
|
|
80190ec: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
80190ee: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80190f0: 4618 mov r0, r3
|
|
80190f2: 3710 adds r7, #16
|
|
80190f4: 46bd mov sp, r7
|
|
80190f6: bd80 pop {r7, pc}
|
|
|
|
080190f8 <USBD_LL_IsStallEP>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Stall (1: Yes, 0: No)
|
|
*/
|
|
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
80190f8: b480 push {r7}
|
|
80190fa: b085 sub sp, #20
|
|
80190fc: af00 add r7, sp, #0
|
|
80190fe: 6078 str r0, [r7, #4]
|
|
8019100: 460b mov r3, r1
|
|
8019102: 70fb strb r3, [r7, #3]
|
|
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
|
|
8019104: 687b ldr r3, [r7, #4]
|
|
8019106: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
801910a: 60fb str r3, [r7, #12]
|
|
|
|
if((ep_addr & 0x80) == 0x80)
|
|
801910c: f997 3003 ldrsb.w r3, [r7, #3]
|
|
8019110: 2b00 cmp r3, #0
|
|
8019112: da0b bge.n 801912c <USBD_LL_IsStallEP+0x34>
|
|
{
|
|
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
|
8019114: 78fb ldrb r3, [r7, #3]
|
|
8019116: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
801911a: 68f9 ldr r1, [r7, #12]
|
|
801911c: 4613 mov r3, r2
|
|
801911e: 009b lsls r3, r3, #2
|
|
8019120: 4413 add r3, r2
|
|
8019122: 00db lsls r3, r3, #3
|
|
8019124: 440b add r3, r1
|
|
8019126: 3312 adds r3, #18
|
|
8019128: 781b ldrb r3, [r3, #0]
|
|
801912a: e00b b.n 8019144 <USBD_LL_IsStallEP+0x4c>
|
|
}
|
|
else
|
|
{
|
|
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
|
801912c: 78fb ldrb r3, [r7, #3]
|
|
801912e: f003 027f and.w r2, r3, #127 @ 0x7f
|
|
8019132: 68f9 ldr r1, [r7, #12]
|
|
8019134: 4613 mov r3, r2
|
|
8019136: 009b lsls r3, r3, #2
|
|
8019138: 4413 add r3, r2
|
|
801913a: 00db lsls r3, r3, #3
|
|
801913c: 440b add r3, r1
|
|
801913e: f503 73a9 add.w r3, r3, #338 @ 0x152
|
|
8019142: 781b ldrb r3, [r3, #0]
|
|
}
|
|
}
|
|
8019144: 4618 mov r0, r3
|
|
8019146: 3714 adds r7, #20
|
|
8019148: 46bd mov sp, r7
|
|
801914a: f85d 7b04 ldr.w r7, [sp], #4
|
|
801914e: 4770 bx lr
|
|
|
|
08019150 <USBD_LL_SetUSBAddress>:
|
|
* @param pdev: Device handle
|
|
* @param dev_addr: Device address
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
|
{
|
|
8019150: b580 push {r7, lr}
|
|
8019152: b084 sub sp, #16
|
|
8019154: af00 add r7, sp, #0
|
|
8019156: 6078 str r0, [r7, #4]
|
|
8019158: 460b mov r3, r1
|
|
801915a: 70fb strb r3, [r7, #3]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
801915c: 2300 movs r3, #0
|
|
801915e: 73fb strb r3, [r7, #15]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
8019160: 2300 movs r3, #0
|
|
8019162: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
|
|
8019164: 687b ldr r3, [r7, #4]
|
|
8019166: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
801916a: 78fa ldrb r2, [r7, #3]
|
|
801916c: 4611 mov r1, r2
|
|
801916e: 4618 mov r0, r3
|
|
8019170: f7f0 fbbb bl 80098ea <HAL_PCD_SetAddress>
|
|
8019174: 4603 mov r3, r0
|
|
8019176: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
8019178: 7bfb ldrb r3, [r7, #15]
|
|
801917a: 4618 mov r0, r3
|
|
801917c: f000 f8b0 bl 80192e0 <USBD_Get_USB_Status>
|
|
8019180: 4603 mov r3, r0
|
|
8019182: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8019184: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8019186: 4618 mov r0, r3
|
|
8019188: 3710 adds r7, #16
|
|
801918a: 46bd mov sp, r7
|
|
801918c: bd80 pop {r7, pc}
|
|
|
|
0801918e <USBD_LL_Transmit>:
|
|
* @param pbuf: Pointer to data to be sent
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
801918e: b580 push {r7, lr}
|
|
8019190: b086 sub sp, #24
|
|
8019192: af00 add r7, sp, #0
|
|
8019194: 60f8 str r0, [r7, #12]
|
|
8019196: 607a str r2, [r7, #4]
|
|
8019198: 603b str r3, [r7, #0]
|
|
801919a: 460b mov r3, r1
|
|
801919c: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
801919e: 2300 movs r3, #0
|
|
80191a0: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80191a2: 2300 movs r3, #0
|
|
80191a4: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
|
|
80191a6: 68fb ldr r3, [r7, #12]
|
|
80191a8: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
80191ac: 7af9 ldrb r1, [r7, #11]
|
|
80191ae: 683b ldr r3, [r7, #0]
|
|
80191b0: 687a ldr r2, [r7, #4]
|
|
80191b2: f7f0 fcae bl 8009b12 <HAL_PCD_EP_Transmit>
|
|
80191b6: 4603 mov r3, r0
|
|
80191b8: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80191ba: 7dfb ldrb r3, [r7, #23]
|
|
80191bc: 4618 mov r0, r3
|
|
80191be: f000 f88f bl 80192e0 <USBD_Get_USB_Status>
|
|
80191c2: 4603 mov r3, r0
|
|
80191c4: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
80191c6: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
80191c8: 4618 mov r0, r3
|
|
80191ca: 3718 adds r7, #24
|
|
80191cc: 46bd mov sp, r7
|
|
80191ce: bd80 pop {r7, pc}
|
|
|
|
080191d0 <USBD_LL_PrepareReceive>:
|
|
* @param pbuf: Pointer to data to be received
|
|
* @param size: Data size
|
|
* @retval USBD status
|
|
*/
|
|
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
|
|
{
|
|
80191d0: b580 push {r7, lr}
|
|
80191d2: b086 sub sp, #24
|
|
80191d4: af00 add r7, sp, #0
|
|
80191d6: 60f8 str r0, [r7, #12]
|
|
80191d8: 607a str r2, [r7, #4]
|
|
80191da: 603b str r3, [r7, #0]
|
|
80191dc: 460b mov r3, r1
|
|
80191de: 72fb strb r3, [r7, #11]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
80191e0: 2300 movs r3, #0
|
|
80191e2: 75fb strb r3, [r7, #23]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80191e4: 2300 movs r3, #0
|
|
80191e6: 75bb strb r3, [r7, #22]
|
|
|
|
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
|
|
80191e8: 68fb ldr r3, [r7, #12]
|
|
80191ea: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
|
|
80191ee: 7af9 ldrb r1, [r7, #11]
|
|
80191f0: 683b ldr r3, [r7, #0]
|
|
80191f2: 687a ldr r2, [r7, #4]
|
|
80191f4: f7f0 fc44 bl 8009a80 <HAL_PCD_EP_Receive>
|
|
80191f8: 4603 mov r3, r0
|
|
80191fa: 75fb strb r3, [r7, #23]
|
|
|
|
usb_status = USBD_Get_USB_Status(hal_status);
|
|
80191fc: 7dfb ldrb r3, [r7, #23]
|
|
80191fe: 4618 mov r0, r3
|
|
8019200: f000 f86e bl 80192e0 <USBD_Get_USB_Status>
|
|
8019204: 4603 mov r3, r0
|
|
8019206: 75bb strb r3, [r7, #22]
|
|
|
|
return usb_status;
|
|
8019208: 7dbb ldrb r3, [r7, #22]
|
|
}
|
|
801920a: 4618 mov r0, r3
|
|
801920c: 3718 adds r7, #24
|
|
801920e: 46bd mov sp, r7
|
|
8019210: bd80 pop {r7, pc}
|
|
|
|
08019212 <USBD_LL_GetRxDataSize>:
|
|
* @param pdev: Device handle
|
|
* @param ep_addr: Endpoint number
|
|
* @retval Received Data Size
|
|
*/
|
|
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
|
{
|
|
8019212: b580 push {r7, lr}
|
|
8019214: b082 sub sp, #8
|
|
8019216: af00 add r7, sp, #0
|
|
8019218: 6078 str r0, [r7, #4]
|
|
801921a: 460b mov r3, r1
|
|
801921c: 70fb strb r3, [r7, #3]
|
|
return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
|
|
801921e: 687b ldr r3, [r7, #4]
|
|
8019220: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
|
|
8019224: 78fa ldrb r2, [r7, #3]
|
|
8019226: 4611 mov r1, r2
|
|
8019228: 4618 mov r0, r3
|
|
801922a: f7f0 fc5a bl 8009ae2 <HAL_PCD_EP_GetRxCount>
|
|
801922e: 4603 mov r3, r0
|
|
}
|
|
8019230: 4618 mov r0, r3
|
|
8019232: 3708 adds r7, #8
|
|
8019234: 46bd mov sp, r7
|
|
8019236: bd80 pop {r7, pc}
|
|
|
|
08019238 <HAL_PCDEx_LPM_Callback>:
|
|
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
|
static void PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
|
#else
|
|
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
|
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
|
{
|
|
8019238: b580 push {r7, lr}
|
|
801923a: b082 sub sp, #8
|
|
801923c: af00 add r7, sp, #0
|
|
801923e: 6078 str r0, [r7, #4]
|
|
8019240: 460b mov r3, r1
|
|
8019242: 70fb strb r3, [r7, #3]
|
|
/* USER CODE BEGIN LPM_Callback */
|
|
switch (msg)
|
|
8019244: 78fb ldrb r3, [r7, #3]
|
|
8019246: 2b00 cmp r3, #0
|
|
8019248: d002 beq.n 8019250 <HAL_PCDEx_LPM_Callback+0x18>
|
|
801924a: 2b01 cmp r3, #1
|
|
801924c: d013 beq.n 8019276 <HAL_PCDEx_LPM_Callback+0x3e>
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
}
|
|
break;
|
|
}
|
|
/* USER CODE END LPM_Callback */
|
|
}
|
|
801924e: e023 b.n 8019298 <HAL_PCDEx_LPM_Callback+0x60>
|
|
if (hpcd->Init.low_power_enable)
|
|
8019250: 687b ldr r3, [r7, #4]
|
|
8019252: 7a5b ldrb r3, [r3, #9]
|
|
8019254: 2b00 cmp r3, #0
|
|
8019256: d007 beq.n 8019268 <HAL_PCDEx_LPM_Callback+0x30>
|
|
SystemClockConfig_Resume();
|
|
8019258: f000 f83c bl 80192d4 <SystemClockConfig_Resume>
|
|
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
801925c: 4b10 ldr r3, [pc, #64] @ (80192a0 <HAL_PCDEx_LPM_Callback+0x68>)
|
|
801925e: 691b ldr r3, [r3, #16]
|
|
8019260: 4a0f ldr r2, [pc, #60] @ (80192a0 <HAL_PCDEx_LPM_Callback+0x68>)
|
|
8019262: f023 0306 bic.w r3, r3, #6
|
|
8019266: 6113 str r3, [r2, #16]
|
|
USBD_LL_Resume(hpcd->pData);
|
|
8019268: 687b ldr r3, [r7, #4]
|
|
801926a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
801926e: 4618 mov r0, r3
|
|
8019270: f7f8 fe10 bl 8011e94 <USBD_LL_Resume>
|
|
break;
|
|
8019274: e010 b.n 8019298 <HAL_PCDEx_LPM_Callback+0x60>
|
|
USBD_LL_Suspend(hpcd->pData);
|
|
8019276: 687b ldr r3, [r7, #4]
|
|
8019278: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
|
|
801927c: 4618 mov r0, r3
|
|
801927e: f7f8 fded bl 8011e5c <USBD_LL_Suspend>
|
|
if (hpcd->Init.low_power_enable)
|
|
8019282: 687b ldr r3, [r7, #4]
|
|
8019284: 7a5b ldrb r3, [r3, #9]
|
|
8019286: 2b00 cmp r3, #0
|
|
8019288: d005 beq.n 8019296 <HAL_PCDEx_LPM_Callback+0x5e>
|
|
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
|
801928a: 4b05 ldr r3, [pc, #20] @ (80192a0 <HAL_PCDEx_LPM_Callback+0x68>)
|
|
801928c: 691b ldr r3, [r3, #16]
|
|
801928e: 4a04 ldr r2, [pc, #16] @ (80192a0 <HAL_PCDEx_LPM_Callback+0x68>)
|
|
8019290: f043 0306 orr.w r3, r3, #6
|
|
8019294: 6113 str r3, [r2, #16]
|
|
break;
|
|
8019296: bf00 nop
|
|
}
|
|
8019298: bf00 nop
|
|
801929a: 3708 adds r7, #8
|
|
801929c: 46bd mov sp, r7
|
|
801929e: bd80 pop {r7, pc}
|
|
80192a0: e000ed00 .word 0xe000ed00
|
|
|
|
080192a4 <USBD_static_malloc>:
|
|
* @brief Static single allocation.
|
|
* @param size: Size of allocated memory
|
|
* @retval None
|
|
*/
|
|
void *USBD_static_malloc(uint32_t size)
|
|
{
|
|
80192a4: b480 push {r7}
|
|
80192a6: b083 sub sp, #12
|
|
80192a8: af00 add r7, sp, #0
|
|
80192aa: 6078 str r0, [r7, #4]
|
|
UNUSED(size);
|
|
static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
|
|
return mem;
|
|
80192ac: 4b03 ldr r3, [pc, #12] @ (80192bc <USBD_static_malloc+0x18>)
|
|
}
|
|
80192ae: 4618 mov r0, r3
|
|
80192b0: 370c adds r7, #12
|
|
80192b2: 46bd mov sp, r7
|
|
80192b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80192b8: 4770 bx lr
|
|
80192ba: bf00 nop
|
|
80192bc: 20013974 .word 0x20013974
|
|
|
|
080192c0 <USBD_static_free>:
|
|
* @brief Dummy memory free
|
|
* @param p: Pointer to allocated memory address
|
|
* @retval None
|
|
*/
|
|
void USBD_static_free(void *p)
|
|
{
|
|
80192c0: b480 push {r7}
|
|
80192c2: b083 sub sp, #12
|
|
80192c4: af00 add r7, sp, #0
|
|
80192c6: 6078 str r0, [r7, #4]
|
|
UNUSED(p);
|
|
}
|
|
80192c8: bf00 nop
|
|
80192ca: 370c adds r7, #12
|
|
80192cc: 46bd mov sp, r7
|
|
80192ce: f85d 7b04 ldr.w r7, [sp], #4
|
|
80192d2: 4770 bx lr
|
|
|
|
080192d4 <SystemClockConfig_Resume>:
|
|
* @brief Configures system clock after wake-up from USB resume callBack:
|
|
* enable HSI, PLL and select PLL as system clock source.
|
|
* @retval None
|
|
*/
|
|
static void SystemClockConfig_Resume(void)
|
|
{
|
|
80192d4: b580 push {r7, lr}
|
|
80192d6: af00 add r7, sp, #0
|
|
SystemClock_Config();
|
|
80192d8: f7eb fb3a bl 8004950 <SystemClock_Config>
|
|
}
|
|
80192dc: bf00 nop
|
|
80192de: bd80 pop {r7, pc}
|
|
|
|
080192e0 <USBD_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
80192e0: b480 push {r7}
|
|
80192e2: b085 sub sp, #20
|
|
80192e4: af00 add r7, sp, #0
|
|
80192e6: 4603 mov r3, r0
|
|
80192e8: 71fb strb r3, [r7, #7]
|
|
USBD_StatusTypeDef usb_status = USBD_OK;
|
|
80192ea: 2300 movs r3, #0
|
|
80192ec: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
80192ee: 79fb ldrb r3, [r7, #7]
|
|
80192f0: 2b03 cmp r3, #3
|
|
80192f2: d817 bhi.n 8019324 <USBD_Get_USB_Status+0x44>
|
|
80192f4: a201 add r2, pc, #4 @ (adr r2, 80192fc <USBD_Get_USB_Status+0x1c>)
|
|
80192f6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80192fa: bf00 nop
|
|
80192fc: 0801930d .word 0x0801930d
|
|
8019300: 08019313 .word 0x08019313
|
|
8019304: 08019319 .word 0x08019319
|
|
8019308: 0801931f .word 0x0801931f
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBD_OK;
|
|
801930c: 2300 movs r3, #0
|
|
801930e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8019310: e00b b.n 801932a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBD_FAIL;
|
|
8019312: 2303 movs r3, #3
|
|
8019314: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8019316: e008 b.n 801932a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBD_BUSY;
|
|
8019318: 2301 movs r3, #1
|
|
801931a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
801931c: e005 b.n 801932a <USBD_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBD_FAIL;
|
|
801931e: 2303 movs r3, #3
|
|
8019320: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8019322: e002 b.n 801932a <USBD_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBD_FAIL;
|
|
8019324: 2303 movs r3, #3
|
|
8019326: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8019328: bf00 nop
|
|
}
|
|
return usb_status;
|
|
801932a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
801932c: 4618 mov r0, r3
|
|
801932e: 3714 adds r7, #20
|
|
8019330: 46bd mov sp, r7
|
|
8019332: f85d 7b04 ldr.w r7, [sp], #4
|
|
8019336: 4770 bx lr
|
|
|
|
08019338 <UTIL_LPM_Init>:
|
|
|
|
/** @addtogroup TINY_LPM_Exported_function
|
|
* @{
|
|
*/
|
|
void UTIL_LPM_Init( void )
|
|
{
|
|
8019338: b480 push {r7}
|
|
801933a: af00 add r7, sp, #0
|
|
StopModeDisable = UTIL_LPM_NO_BIT_SET;
|
|
801933c: 4b05 ldr r3, [pc, #20] @ (8019354 <UTIL_LPM_Init+0x1c>)
|
|
801933e: 2200 movs r2, #0
|
|
8019340: 601a str r2, [r3, #0]
|
|
OffModeDisable = UTIL_LPM_NO_BIT_SET;
|
|
8019342: 4b05 ldr r3, [pc, #20] @ (8019358 <UTIL_LPM_Init+0x20>)
|
|
8019344: 2200 movs r2, #0
|
|
8019346: 601a str r2, [r3, #0]
|
|
UTIL_LPM_INIT_CRITICAL_SECTION( );
|
|
}
|
|
8019348: bf00 nop
|
|
801934a: 46bd mov sp, r7
|
|
801934c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8019350: 4770 bx lr
|
|
8019352: bf00 nop
|
|
8019354: 20013b94 .word 0x20013b94
|
|
8019358: 20013b98 .word 0x20013b98
|
|
|
|
0801935c <UTIL_LPM_SetOffMode>:
|
|
|
|
UTIL_LPM_EXIT_CRITICAL_SECTION( );
|
|
}
|
|
|
|
void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state )
|
|
{
|
|
801935c: b480 push {r7}
|
|
801935e: b087 sub sp, #28
|
|
8019360: af00 add r7, sp, #0
|
|
8019362: 6078 str r0, [r7, #4]
|
|
8019364: 460b mov r3, r1
|
|
8019366: 70fb strb r3, [r7, #3]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
8019368: f3ef 8310 mrs r3, PRIMASK
|
|
801936c: 613b str r3, [r7, #16]
|
|
return(result);
|
|
801936e: 693b ldr r3, [r7, #16]
|
|
UTIL_LPM_ENTER_CRITICAL_SECTION( );
|
|
8019370: 617b str r3, [r7, #20]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8019372: b672 cpsid i
|
|
}
|
|
8019374: bf00 nop
|
|
|
|
switch(state)
|
|
8019376: 78fb ldrb r3, [r7, #3]
|
|
8019378: 2b00 cmp r3, #0
|
|
801937a: d008 beq.n 801938e <UTIL_LPM_SetOffMode+0x32>
|
|
801937c: 2b01 cmp r3, #1
|
|
801937e: d10e bne.n 801939e <UTIL_LPM_SetOffMode+0x42>
|
|
{
|
|
case UTIL_LPM_DISABLE:
|
|
{
|
|
OffModeDisable |= lpm_id_bm;
|
|
8019380: 4b0d ldr r3, [pc, #52] @ (80193b8 <UTIL_LPM_SetOffMode+0x5c>)
|
|
8019382: 681a ldr r2, [r3, #0]
|
|
8019384: 687b ldr r3, [r7, #4]
|
|
8019386: 4313 orrs r3, r2
|
|
8019388: 4a0b ldr r2, [pc, #44] @ (80193b8 <UTIL_LPM_SetOffMode+0x5c>)
|
|
801938a: 6013 str r3, [r2, #0]
|
|
break;
|
|
801938c: e008 b.n 80193a0 <UTIL_LPM_SetOffMode+0x44>
|
|
}
|
|
case UTIL_LPM_ENABLE:
|
|
{
|
|
OffModeDisable &= ( ~lpm_id_bm );
|
|
801938e: 687b ldr r3, [r7, #4]
|
|
8019390: 43da mvns r2, r3
|
|
8019392: 4b09 ldr r3, [pc, #36] @ (80193b8 <UTIL_LPM_SetOffMode+0x5c>)
|
|
8019394: 681b ldr r3, [r3, #0]
|
|
8019396: 4013 ands r3, r2
|
|
8019398: 4a07 ldr r2, [pc, #28] @ (80193b8 <UTIL_LPM_SetOffMode+0x5c>)
|
|
801939a: 6013 str r3, [r2, #0]
|
|
break;
|
|
801939c: e000 b.n 80193a0 <UTIL_LPM_SetOffMode+0x44>
|
|
}
|
|
default :
|
|
{
|
|
break;
|
|
801939e: bf00 nop
|
|
80193a0: 697b ldr r3, [r7, #20]
|
|
80193a2: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80193a4: 68fb ldr r3, [r7, #12]
|
|
80193a6: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80193aa: bf00 nop
|
|
}
|
|
}
|
|
|
|
UTIL_LPM_EXIT_CRITICAL_SECTION( );
|
|
}
|
|
80193ac: bf00 nop
|
|
80193ae: 371c adds r7, #28
|
|
80193b0: 46bd mov sp, r7
|
|
80193b2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80193b6: 4770 bx lr
|
|
80193b8: 20013b98 .word 0x20013b98
|
|
|
|
080193bc <__cvt>:
|
|
80193bc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
80193c0: ec57 6b10 vmov r6, r7, d0
|
|
80193c4: 2f00 cmp r7, #0
|
|
80193c6: 460c mov r4, r1
|
|
80193c8: 4619 mov r1, r3
|
|
80193ca: 463b mov r3, r7
|
|
80193cc: bfbb ittet lt
|
|
80193ce: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000
|
|
80193d2: 461f movlt r7, r3
|
|
80193d4: 2300 movge r3, #0
|
|
80193d6: 232d movlt r3, #45 @ 0x2d
|
|
80193d8: 700b strb r3, [r1, #0]
|
|
80193da: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
80193dc: f8dd a030 ldr.w sl, [sp, #48] @ 0x30
|
|
80193e0: 4691 mov r9, r2
|
|
80193e2: f023 0820 bic.w r8, r3, #32
|
|
80193e6: bfbc itt lt
|
|
80193e8: 4632 movlt r2, r6
|
|
80193ea: 4616 movlt r6, r2
|
|
80193ec: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
80193f0: d005 beq.n 80193fe <__cvt+0x42>
|
|
80193f2: f1b8 0f45 cmp.w r8, #69 @ 0x45
|
|
80193f6: d100 bne.n 80193fa <__cvt+0x3e>
|
|
80193f8: 3401 adds r4, #1
|
|
80193fa: 2102 movs r1, #2
|
|
80193fc: e000 b.n 8019400 <__cvt+0x44>
|
|
80193fe: 2103 movs r1, #3
|
|
8019400: ab03 add r3, sp, #12
|
|
8019402: 9301 str r3, [sp, #4]
|
|
8019404: ab02 add r3, sp, #8
|
|
8019406: 9300 str r3, [sp, #0]
|
|
8019408: ec47 6b10 vmov d0, r6, r7
|
|
801940c: 4653 mov r3, sl
|
|
801940e: 4622 mov r2, r4
|
|
8019410: f001 f8f2 bl 801a5f8 <_dtoa_r>
|
|
8019414: f1b8 0f47 cmp.w r8, #71 @ 0x47
|
|
8019418: 4605 mov r5, r0
|
|
801941a: d119 bne.n 8019450 <__cvt+0x94>
|
|
801941c: f019 0f01 tst.w r9, #1
|
|
8019420: d00e beq.n 8019440 <__cvt+0x84>
|
|
8019422: eb00 0904 add.w r9, r0, r4
|
|
8019426: 2200 movs r2, #0
|
|
8019428: 2300 movs r3, #0
|
|
801942a: 4630 mov r0, r6
|
|
801942c: 4639 mov r1, r7
|
|
801942e: f7e7 fb23 bl 8000a78 <__aeabi_dcmpeq>
|
|
8019432: b108 cbz r0, 8019438 <__cvt+0x7c>
|
|
8019434: f8cd 900c str.w r9, [sp, #12]
|
|
8019438: 2230 movs r2, #48 @ 0x30
|
|
801943a: 9b03 ldr r3, [sp, #12]
|
|
801943c: 454b cmp r3, r9
|
|
801943e: d31e bcc.n 801947e <__cvt+0xc2>
|
|
8019440: 9b03 ldr r3, [sp, #12]
|
|
8019442: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
8019444: 1b5b subs r3, r3, r5
|
|
8019446: 4628 mov r0, r5
|
|
8019448: 6013 str r3, [r2, #0]
|
|
801944a: b004 add sp, #16
|
|
801944c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8019450: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
8019454: eb00 0904 add.w r9, r0, r4
|
|
8019458: d1e5 bne.n 8019426 <__cvt+0x6a>
|
|
801945a: 7803 ldrb r3, [r0, #0]
|
|
801945c: 2b30 cmp r3, #48 @ 0x30
|
|
801945e: d10a bne.n 8019476 <__cvt+0xba>
|
|
8019460: 2200 movs r2, #0
|
|
8019462: 2300 movs r3, #0
|
|
8019464: 4630 mov r0, r6
|
|
8019466: 4639 mov r1, r7
|
|
8019468: f7e7 fb06 bl 8000a78 <__aeabi_dcmpeq>
|
|
801946c: b918 cbnz r0, 8019476 <__cvt+0xba>
|
|
801946e: f1c4 0401 rsb r4, r4, #1
|
|
8019472: f8ca 4000 str.w r4, [sl]
|
|
8019476: f8da 3000 ldr.w r3, [sl]
|
|
801947a: 4499 add r9, r3
|
|
801947c: e7d3 b.n 8019426 <__cvt+0x6a>
|
|
801947e: 1c59 adds r1, r3, #1
|
|
8019480: 9103 str r1, [sp, #12]
|
|
8019482: 701a strb r2, [r3, #0]
|
|
8019484: e7d9 b.n 801943a <__cvt+0x7e>
|
|
|
|
08019486 <__exponent>:
|
|
8019486: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
8019488: 2900 cmp r1, #0
|
|
801948a: bfba itte lt
|
|
801948c: 4249 neglt r1, r1
|
|
801948e: 232d movlt r3, #45 @ 0x2d
|
|
8019490: 232b movge r3, #43 @ 0x2b
|
|
8019492: 2909 cmp r1, #9
|
|
8019494: 7002 strb r2, [r0, #0]
|
|
8019496: 7043 strb r3, [r0, #1]
|
|
8019498: dd29 ble.n 80194ee <__exponent+0x68>
|
|
801949a: f10d 0407 add.w r4, sp, #7
|
|
801949e: 4625 mov r5, r4
|
|
80194a0: 270a movs r7, #10
|
|
80194a2: 4622 mov r2, r4
|
|
80194a4: fbb1 f6f7 udiv r6, r1, r7
|
|
80194a8: fb07 1316 mls r3, r7, r6, r1
|
|
80194ac: 3330 adds r3, #48 @ 0x30
|
|
80194ae: f802 3c01 strb.w r3, [r2, #-1]
|
|
80194b2: 460b mov r3, r1
|
|
80194b4: 2b63 cmp r3, #99 @ 0x63
|
|
80194b6: f104 34ff add.w r4, r4, #4294967295 @ 0xffffffff
|
|
80194ba: 4631 mov r1, r6
|
|
80194bc: dcf1 bgt.n 80194a2 <__exponent+0x1c>
|
|
80194be: 3130 adds r1, #48 @ 0x30
|
|
80194c0: 1e93 subs r3, r2, #2
|
|
80194c2: f804 1c01 strb.w r1, [r4, #-1]
|
|
80194c6: 1c41 adds r1, r0, #1
|
|
80194c8: 461c mov r4, r3
|
|
80194ca: 42ab cmp r3, r5
|
|
80194cc: d30a bcc.n 80194e4 <__exponent+0x5e>
|
|
80194ce: f10d 0309 add.w r3, sp, #9
|
|
80194d2: 1a9b subs r3, r3, r2
|
|
80194d4: 42a5 cmp r5, r4
|
|
80194d6: bf38 it cc
|
|
80194d8: 2300 movcc r3, #0
|
|
80194da: 1c82 adds r2, r0, #2
|
|
80194dc: 4413 add r3, r2
|
|
80194de: 1a18 subs r0, r3, r0
|
|
80194e0: b003 add sp, #12
|
|
80194e2: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80194e4: f813 6b01 ldrb.w r6, [r3], #1
|
|
80194e8: f801 6f01 strb.w r6, [r1, #1]!
|
|
80194ec: e7ed b.n 80194ca <__exponent+0x44>
|
|
80194ee: 2330 movs r3, #48 @ 0x30
|
|
80194f0: 3130 adds r1, #48 @ 0x30
|
|
80194f2: 7083 strb r3, [r0, #2]
|
|
80194f4: 70c1 strb r1, [r0, #3]
|
|
80194f6: 1d03 adds r3, r0, #4
|
|
80194f8: e7f1 b.n 80194de <__exponent+0x58>
|
|
...
|
|
|
|
080194fc <_printf_float>:
|
|
80194fc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8019500: b08d sub sp, #52 @ 0x34
|
|
8019502: 460c mov r4, r1
|
|
8019504: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
|
|
8019508: 4616 mov r6, r2
|
|
801950a: 461f mov r7, r3
|
|
801950c: 4605 mov r5, r0
|
|
801950e: f000 ff01 bl 801a314 <_localeconv_r>
|
|
8019512: 6803 ldr r3, [r0, #0]
|
|
8019514: 9306 str r3, [sp, #24]
|
|
8019516: 4618 mov r0, r3
|
|
8019518: f7e6 fe82 bl 8000220 <strlen>
|
|
801951c: 2300 movs r3, #0
|
|
801951e: 930a str r3, [sp, #40] @ 0x28
|
|
8019520: f8d8 3000 ldr.w r3, [r8]
|
|
8019524: f894 a018 ldrb.w sl, [r4, #24]
|
|
8019528: f8d4 b000 ldr.w fp, [r4]
|
|
801952c: 9007 str r0, [sp, #28]
|
|
801952e: 3307 adds r3, #7
|
|
8019530: f023 0307 bic.w r3, r3, #7
|
|
8019534: ecb3 7b02 vldmia r3!, {d7}
|
|
8019538: ed8d 7b04 vstr d7, [sp, #16]
|
|
801953c: f8c8 3000 str.w r3, [r8]
|
|
8019540: e9dd 8304 ldrd r8, r3, [sp, #16]
|
|
8019544: f023 4900 bic.w r9, r3, #2147483648 @ 0x80000000
|
|
8019548: ed84 7b12 vstr d7, [r4, #72] @ 0x48
|
|
801954c: 4b9c ldr r3, [pc, #624] @ (80197c0 <_printf_float+0x2c4>)
|
|
801954e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8019552: 4640 mov r0, r8
|
|
8019554: 4649 mov r1, r9
|
|
8019556: f7e7 fac1 bl 8000adc <__aeabi_dcmpun>
|
|
801955a: bb70 cbnz r0, 80195ba <_printf_float+0xbe>
|
|
801955c: 4b98 ldr r3, [pc, #608] @ (80197c0 <_printf_float+0x2c4>)
|
|
801955e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8019562: 4640 mov r0, r8
|
|
8019564: 4649 mov r1, r9
|
|
8019566: f7e7 fa9b bl 8000aa0 <__aeabi_dcmple>
|
|
801956a: bb30 cbnz r0, 80195ba <_printf_float+0xbe>
|
|
801956c: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8019570: 2200 movs r2, #0
|
|
8019572: 2300 movs r3, #0
|
|
8019574: f7e7 fa8a bl 8000a8c <__aeabi_dcmplt>
|
|
8019578: b110 cbz r0, 8019580 <_printf_float+0x84>
|
|
801957a: 232d movs r3, #45 @ 0x2d
|
|
801957c: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8019580: 4a90 ldr r2, [pc, #576] @ (80197c4 <_printf_float+0x2c8>)
|
|
8019582: 4b91 ldr r3, [pc, #580] @ (80197c8 <_printf_float+0x2cc>)
|
|
8019584: f1ba 0f47 cmp.w sl, #71 @ 0x47
|
|
8019588: bf8c ite hi
|
|
801958a: 4690 movhi r8, r2
|
|
801958c: 4698 movls r8, r3
|
|
801958e: 2303 movs r3, #3
|
|
8019590: 6123 str r3, [r4, #16]
|
|
8019592: f02b 0304 bic.w r3, fp, #4
|
|
8019596: 6023 str r3, [r4, #0]
|
|
8019598: f04f 0900 mov.w r9, #0
|
|
801959c: 9700 str r7, [sp, #0]
|
|
801959e: 4633 mov r3, r6
|
|
80195a0: aa0b add r2, sp, #44 @ 0x2c
|
|
80195a2: 4621 mov r1, r4
|
|
80195a4: 4628 mov r0, r5
|
|
80195a6: f000 f9d1 bl 801994c <_printf_common>
|
|
80195aa: 3001 adds r0, #1
|
|
80195ac: f040 808c bne.w 80196c8 <_printf_float+0x1cc>
|
|
80195b0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80195b4: b00d add sp, #52 @ 0x34
|
|
80195b6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80195ba: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
80195be: 4610 mov r0, r2
|
|
80195c0: 4619 mov r1, r3
|
|
80195c2: f7e7 fa8b bl 8000adc <__aeabi_dcmpun>
|
|
80195c6: b140 cbz r0, 80195da <_printf_float+0xde>
|
|
80195c8: 9b05 ldr r3, [sp, #20]
|
|
80195ca: 4a80 ldr r2, [pc, #512] @ (80197cc <_printf_float+0x2d0>)
|
|
80195cc: 2b00 cmp r3, #0
|
|
80195ce: bfbc itt lt
|
|
80195d0: 232d movlt r3, #45 @ 0x2d
|
|
80195d2: f884 3043 strblt.w r3, [r4, #67] @ 0x43
|
|
80195d6: 4b7e ldr r3, [pc, #504] @ (80197d0 <_printf_float+0x2d4>)
|
|
80195d8: e7d4 b.n 8019584 <_printf_float+0x88>
|
|
80195da: 6863 ldr r3, [r4, #4]
|
|
80195dc: 1c5a adds r2, r3, #1
|
|
80195de: f00a 09df and.w r9, sl, #223 @ 0xdf
|
|
80195e2: d13b bne.n 801965c <_printf_float+0x160>
|
|
80195e4: 2306 movs r3, #6
|
|
80195e6: 6063 str r3, [r4, #4]
|
|
80195e8: f44b 6280 orr.w r2, fp, #1024 @ 0x400
|
|
80195ec: 2300 movs r3, #0
|
|
80195ee: 6022 str r2, [r4, #0]
|
|
80195f0: 9303 str r3, [sp, #12]
|
|
80195f2: ab0a add r3, sp, #40 @ 0x28
|
|
80195f4: e9cd a301 strd sl, r3, [sp, #4]
|
|
80195f8: ab09 add r3, sp, #36 @ 0x24
|
|
80195fa: 9300 str r3, [sp, #0]
|
|
80195fc: 6861 ldr r1, [r4, #4]
|
|
80195fe: ed9d 0b04 vldr d0, [sp, #16]
|
|
8019602: f10d 0323 add.w r3, sp, #35 @ 0x23
|
|
8019606: 4628 mov r0, r5
|
|
8019608: f7ff fed8 bl 80193bc <__cvt>
|
|
801960c: f1b9 0f47 cmp.w r9, #71 @ 0x47
|
|
8019610: 9909 ldr r1, [sp, #36] @ 0x24
|
|
8019612: 4680 mov r8, r0
|
|
8019614: d129 bne.n 801966a <_printf_float+0x16e>
|
|
8019616: 1cc8 adds r0, r1, #3
|
|
8019618: db02 blt.n 8019620 <_printf_float+0x124>
|
|
801961a: 6863 ldr r3, [r4, #4]
|
|
801961c: 428b cmp r3, r1
|
|
801961e: da41 bge.n 80196a4 <_printf_float+0x1a8>
|
|
8019620: f1aa 0a02 sub.w sl, sl, #2
|
|
8019624: fa5f fa8a uxtb.w sl, sl
|
|
8019628: 3901 subs r1, #1
|
|
801962a: 4652 mov r2, sl
|
|
801962c: f104 0050 add.w r0, r4, #80 @ 0x50
|
|
8019630: 9109 str r1, [sp, #36] @ 0x24
|
|
8019632: f7ff ff28 bl 8019486 <__exponent>
|
|
8019636: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
8019638: 1813 adds r3, r2, r0
|
|
801963a: 2a01 cmp r2, #1
|
|
801963c: 4681 mov r9, r0
|
|
801963e: 6123 str r3, [r4, #16]
|
|
8019640: dc02 bgt.n 8019648 <_printf_float+0x14c>
|
|
8019642: 6822 ldr r2, [r4, #0]
|
|
8019644: 07d2 lsls r2, r2, #31
|
|
8019646: d501 bpl.n 801964c <_printf_float+0x150>
|
|
8019648: 3301 adds r3, #1
|
|
801964a: 6123 str r3, [r4, #16]
|
|
801964c: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
|
|
8019650: 2b00 cmp r3, #0
|
|
8019652: d0a3 beq.n 801959c <_printf_float+0xa0>
|
|
8019654: 232d movs r3, #45 @ 0x2d
|
|
8019656: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
801965a: e79f b.n 801959c <_printf_float+0xa0>
|
|
801965c: f1b9 0f47 cmp.w r9, #71 @ 0x47
|
|
8019660: d1c2 bne.n 80195e8 <_printf_float+0xec>
|
|
8019662: 2b00 cmp r3, #0
|
|
8019664: d1c0 bne.n 80195e8 <_printf_float+0xec>
|
|
8019666: 2301 movs r3, #1
|
|
8019668: e7bd b.n 80195e6 <_printf_float+0xea>
|
|
801966a: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
801966e: d9db bls.n 8019628 <_printf_float+0x12c>
|
|
8019670: f1ba 0f66 cmp.w sl, #102 @ 0x66
|
|
8019674: d118 bne.n 80196a8 <_printf_float+0x1ac>
|
|
8019676: 2900 cmp r1, #0
|
|
8019678: 6863 ldr r3, [r4, #4]
|
|
801967a: dd0b ble.n 8019694 <_printf_float+0x198>
|
|
801967c: 6121 str r1, [r4, #16]
|
|
801967e: b913 cbnz r3, 8019686 <_printf_float+0x18a>
|
|
8019680: 6822 ldr r2, [r4, #0]
|
|
8019682: 07d0 lsls r0, r2, #31
|
|
8019684: d502 bpl.n 801968c <_printf_float+0x190>
|
|
8019686: 3301 adds r3, #1
|
|
8019688: 440b add r3, r1
|
|
801968a: 6123 str r3, [r4, #16]
|
|
801968c: 65a1 str r1, [r4, #88] @ 0x58
|
|
801968e: f04f 0900 mov.w r9, #0
|
|
8019692: e7db b.n 801964c <_printf_float+0x150>
|
|
8019694: b913 cbnz r3, 801969c <_printf_float+0x1a0>
|
|
8019696: 6822 ldr r2, [r4, #0]
|
|
8019698: 07d2 lsls r2, r2, #31
|
|
801969a: d501 bpl.n 80196a0 <_printf_float+0x1a4>
|
|
801969c: 3302 adds r3, #2
|
|
801969e: e7f4 b.n 801968a <_printf_float+0x18e>
|
|
80196a0: 2301 movs r3, #1
|
|
80196a2: e7f2 b.n 801968a <_printf_float+0x18e>
|
|
80196a4: f04f 0a67 mov.w sl, #103 @ 0x67
|
|
80196a8: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
80196aa: 428b cmp r3, r1
|
|
80196ac: dc05 bgt.n 80196ba <_printf_float+0x1be>
|
|
80196ae: 6823 ldr r3, [r4, #0]
|
|
80196b0: 6121 str r1, [r4, #16]
|
|
80196b2: 07d8 lsls r0, r3, #31
|
|
80196b4: d5ea bpl.n 801968c <_printf_float+0x190>
|
|
80196b6: 1c4b adds r3, r1, #1
|
|
80196b8: e7e7 b.n 801968a <_printf_float+0x18e>
|
|
80196ba: 2900 cmp r1, #0
|
|
80196bc: bfd4 ite le
|
|
80196be: f1c1 0202 rsble r2, r1, #2
|
|
80196c2: 2201 movgt r2, #1
|
|
80196c4: 4413 add r3, r2
|
|
80196c6: e7e0 b.n 801968a <_printf_float+0x18e>
|
|
80196c8: 6823 ldr r3, [r4, #0]
|
|
80196ca: 055a lsls r2, r3, #21
|
|
80196cc: d407 bmi.n 80196de <_printf_float+0x1e2>
|
|
80196ce: 6923 ldr r3, [r4, #16]
|
|
80196d0: 4642 mov r2, r8
|
|
80196d2: 4631 mov r1, r6
|
|
80196d4: 4628 mov r0, r5
|
|
80196d6: 47b8 blx r7
|
|
80196d8: 3001 adds r0, #1
|
|
80196da: d12b bne.n 8019734 <_printf_float+0x238>
|
|
80196dc: e768 b.n 80195b0 <_printf_float+0xb4>
|
|
80196de: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
80196e2: f240 80dd bls.w 80198a0 <_printf_float+0x3a4>
|
|
80196e6: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
80196ea: 2200 movs r2, #0
|
|
80196ec: 2300 movs r3, #0
|
|
80196ee: f7e7 f9c3 bl 8000a78 <__aeabi_dcmpeq>
|
|
80196f2: 2800 cmp r0, #0
|
|
80196f4: d033 beq.n 801975e <_printf_float+0x262>
|
|
80196f6: 4a37 ldr r2, [pc, #220] @ (80197d4 <_printf_float+0x2d8>)
|
|
80196f8: 2301 movs r3, #1
|
|
80196fa: 4631 mov r1, r6
|
|
80196fc: 4628 mov r0, r5
|
|
80196fe: 47b8 blx r7
|
|
8019700: 3001 adds r0, #1
|
|
8019702: f43f af55 beq.w 80195b0 <_printf_float+0xb4>
|
|
8019706: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
|
|
801970a: 4543 cmp r3, r8
|
|
801970c: db02 blt.n 8019714 <_printf_float+0x218>
|
|
801970e: 6823 ldr r3, [r4, #0]
|
|
8019710: 07d8 lsls r0, r3, #31
|
|
8019712: d50f bpl.n 8019734 <_printf_float+0x238>
|
|
8019714: e9dd 2306 ldrd r2, r3, [sp, #24]
|
|
8019718: 4631 mov r1, r6
|
|
801971a: 4628 mov r0, r5
|
|
801971c: 47b8 blx r7
|
|
801971e: 3001 adds r0, #1
|
|
8019720: f43f af46 beq.w 80195b0 <_printf_float+0xb4>
|
|
8019724: f04f 0900 mov.w r9, #0
|
|
8019728: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
|
|
801972c: f104 0a1a add.w sl, r4, #26
|
|
8019730: 45c8 cmp r8, r9
|
|
8019732: dc09 bgt.n 8019748 <_printf_float+0x24c>
|
|
8019734: 6823 ldr r3, [r4, #0]
|
|
8019736: 079b lsls r3, r3, #30
|
|
8019738: f100 8103 bmi.w 8019942 <_printf_float+0x446>
|
|
801973c: 68e0 ldr r0, [r4, #12]
|
|
801973e: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8019740: 4298 cmp r0, r3
|
|
8019742: bfb8 it lt
|
|
8019744: 4618 movlt r0, r3
|
|
8019746: e735 b.n 80195b4 <_printf_float+0xb8>
|
|
8019748: 2301 movs r3, #1
|
|
801974a: 4652 mov r2, sl
|
|
801974c: 4631 mov r1, r6
|
|
801974e: 4628 mov r0, r5
|
|
8019750: 47b8 blx r7
|
|
8019752: 3001 adds r0, #1
|
|
8019754: f43f af2c beq.w 80195b0 <_printf_float+0xb4>
|
|
8019758: f109 0901 add.w r9, r9, #1
|
|
801975c: e7e8 b.n 8019730 <_printf_float+0x234>
|
|
801975e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8019760: 2b00 cmp r3, #0
|
|
8019762: dc39 bgt.n 80197d8 <_printf_float+0x2dc>
|
|
8019764: 4a1b ldr r2, [pc, #108] @ (80197d4 <_printf_float+0x2d8>)
|
|
8019766: 2301 movs r3, #1
|
|
8019768: 4631 mov r1, r6
|
|
801976a: 4628 mov r0, r5
|
|
801976c: 47b8 blx r7
|
|
801976e: 3001 adds r0, #1
|
|
8019770: f43f af1e beq.w 80195b0 <_printf_float+0xb4>
|
|
8019774: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
|
|
8019778: ea59 0303 orrs.w r3, r9, r3
|
|
801977c: d102 bne.n 8019784 <_printf_float+0x288>
|
|
801977e: 6823 ldr r3, [r4, #0]
|
|
8019780: 07d9 lsls r1, r3, #31
|
|
8019782: d5d7 bpl.n 8019734 <_printf_float+0x238>
|
|
8019784: e9dd 2306 ldrd r2, r3, [sp, #24]
|
|
8019788: 4631 mov r1, r6
|
|
801978a: 4628 mov r0, r5
|
|
801978c: 47b8 blx r7
|
|
801978e: 3001 adds r0, #1
|
|
8019790: f43f af0e beq.w 80195b0 <_printf_float+0xb4>
|
|
8019794: f04f 0a00 mov.w sl, #0
|
|
8019798: f104 0b1a add.w fp, r4, #26
|
|
801979c: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
801979e: 425b negs r3, r3
|
|
80197a0: 4553 cmp r3, sl
|
|
80197a2: dc01 bgt.n 80197a8 <_printf_float+0x2ac>
|
|
80197a4: 464b mov r3, r9
|
|
80197a6: e793 b.n 80196d0 <_printf_float+0x1d4>
|
|
80197a8: 2301 movs r3, #1
|
|
80197aa: 465a mov r2, fp
|
|
80197ac: 4631 mov r1, r6
|
|
80197ae: 4628 mov r0, r5
|
|
80197b0: 47b8 blx r7
|
|
80197b2: 3001 adds r0, #1
|
|
80197b4: f43f aefc beq.w 80195b0 <_printf_float+0xb4>
|
|
80197b8: f10a 0a01 add.w sl, sl, #1
|
|
80197bc: e7ee b.n 801979c <_printf_float+0x2a0>
|
|
80197be: bf00 nop
|
|
80197c0: 7fefffff .word 0x7fefffff
|
|
80197c4: 0801e614 .word 0x0801e614
|
|
80197c8: 0801e610 .word 0x0801e610
|
|
80197cc: 0801e61c .word 0x0801e61c
|
|
80197d0: 0801e618 .word 0x0801e618
|
|
80197d4: 0801e620 .word 0x0801e620
|
|
80197d8: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
80197da: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
80197de: 4553 cmp r3, sl
|
|
80197e0: bfa8 it ge
|
|
80197e2: 4653 movge r3, sl
|
|
80197e4: 2b00 cmp r3, #0
|
|
80197e6: 4699 mov r9, r3
|
|
80197e8: dc36 bgt.n 8019858 <_printf_float+0x35c>
|
|
80197ea: f04f 0b00 mov.w fp, #0
|
|
80197ee: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
80197f2: f104 021a add.w r2, r4, #26
|
|
80197f6: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
80197f8: 9304 str r3, [sp, #16]
|
|
80197fa: eba3 0309 sub.w r3, r3, r9
|
|
80197fe: 455b cmp r3, fp
|
|
8019800: dc31 bgt.n 8019866 <_printf_float+0x36a>
|
|
8019802: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8019804: 459a cmp sl, r3
|
|
8019806: dc3a bgt.n 801987e <_printf_float+0x382>
|
|
8019808: 6823 ldr r3, [r4, #0]
|
|
801980a: 07da lsls r2, r3, #31
|
|
801980c: d437 bmi.n 801987e <_printf_float+0x382>
|
|
801980e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8019810: ebaa 0903 sub.w r9, sl, r3
|
|
8019814: 9b04 ldr r3, [sp, #16]
|
|
8019816: ebaa 0303 sub.w r3, sl, r3
|
|
801981a: 4599 cmp r9, r3
|
|
801981c: bfa8 it ge
|
|
801981e: 4699 movge r9, r3
|
|
8019820: f1b9 0f00 cmp.w r9, #0
|
|
8019824: dc33 bgt.n 801988e <_printf_float+0x392>
|
|
8019826: f04f 0800 mov.w r8, #0
|
|
801982a: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
801982e: f104 0b1a add.w fp, r4, #26
|
|
8019832: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8019834: ebaa 0303 sub.w r3, sl, r3
|
|
8019838: eba3 0309 sub.w r3, r3, r9
|
|
801983c: 4543 cmp r3, r8
|
|
801983e: f77f af79 ble.w 8019734 <_printf_float+0x238>
|
|
8019842: 2301 movs r3, #1
|
|
8019844: 465a mov r2, fp
|
|
8019846: 4631 mov r1, r6
|
|
8019848: 4628 mov r0, r5
|
|
801984a: 47b8 blx r7
|
|
801984c: 3001 adds r0, #1
|
|
801984e: f43f aeaf beq.w 80195b0 <_printf_float+0xb4>
|
|
8019852: f108 0801 add.w r8, r8, #1
|
|
8019856: e7ec b.n 8019832 <_printf_float+0x336>
|
|
8019858: 4642 mov r2, r8
|
|
801985a: 4631 mov r1, r6
|
|
801985c: 4628 mov r0, r5
|
|
801985e: 47b8 blx r7
|
|
8019860: 3001 adds r0, #1
|
|
8019862: d1c2 bne.n 80197ea <_printf_float+0x2ee>
|
|
8019864: e6a4 b.n 80195b0 <_printf_float+0xb4>
|
|
8019866: 2301 movs r3, #1
|
|
8019868: 4631 mov r1, r6
|
|
801986a: 4628 mov r0, r5
|
|
801986c: 9204 str r2, [sp, #16]
|
|
801986e: 47b8 blx r7
|
|
8019870: 3001 adds r0, #1
|
|
8019872: f43f ae9d beq.w 80195b0 <_printf_float+0xb4>
|
|
8019876: 9a04 ldr r2, [sp, #16]
|
|
8019878: f10b 0b01 add.w fp, fp, #1
|
|
801987c: e7bb b.n 80197f6 <_printf_float+0x2fa>
|
|
801987e: e9dd 2306 ldrd r2, r3, [sp, #24]
|
|
8019882: 4631 mov r1, r6
|
|
8019884: 4628 mov r0, r5
|
|
8019886: 47b8 blx r7
|
|
8019888: 3001 adds r0, #1
|
|
801988a: d1c0 bne.n 801980e <_printf_float+0x312>
|
|
801988c: e690 b.n 80195b0 <_printf_float+0xb4>
|
|
801988e: 9a04 ldr r2, [sp, #16]
|
|
8019890: 464b mov r3, r9
|
|
8019892: 4442 add r2, r8
|
|
8019894: 4631 mov r1, r6
|
|
8019896: 4628 mov r0, r5
|
|
8019898: 47b8 blx r7
|
|
801989a: 3001 adds r0, #1
|
|
801989c: d1c3 bne.n 8019826 <_printf_float+0x32a>
|
|
801989e: e687 b.n 80195b0 <_printf_float+0xb4>
|
|
80198a0: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
80198a4: f1ba 0f01 cmp.w sl, #1
|
|
80198a8: dc01 bgt.n 80198ae <_printf_float+0x3b2>
|
|
80198aa: 07db lsls r3, r3, #31
|
|
80198ac: d536 bpl.n 801991c <_printf_float+0x420>
|
|
80198ae: 2301 movs r3, #1
|
|
80198b0: 4642 mov r2, r8
|
|
80198b2: 4631 mov r1, r6
|
|
80198b4: 4628 mov r0, r5
|
|
80198b6: 47b8 blx r7
|
|
80198b8: 3001 adds r0, #1
|
|
80198ba: f43f ae79 beq.w 80195b0 <_printf_float+0xb4>
|
|
80198be: e9dd 2306 ldrd r2, r3, [sp, #24]
|
|
80198c2: 4631 mov r1, r6
|
|
80198c4: 4628 mov r0, r5
|
|
80198c6: 47b8 blx r7
|
|
80198c8: 3001 adds r0, #1
|
|
80198ca: f43f ae71 beq.w 80195b0 <_printf_float+0xb4>
|
|
80198ce: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
80198d2: 2200 movs r2, #0
|
|
80198d4: 2300 movs r3, #0
|
|
80198d6: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
80198da: f7e7 f8cd bl 8000a78 <__aeabi_dcmpeq>
|
|
80198de: b9c0 cbnz r0, 8019912 <_printf_float+0x416>
|
|
80198e0: 4653 mov r3, sl
|
|
80198e2: f108 0201 add.w r2, r8, #1
|
|
80198e6: 4631 mov r1, r6
|
|
80198e8: 4628 mov r0, r5
|
|
80198ea: 47b8 blx r7
|
|
80198ec: 3001 adds r0, #1
|
|
80198ee: d10c bne.n 801990a <_printf_float+0x40e>
|
|
80198f0: e65e b.n 80195b0 <_printf_float+0xb4>
|
|
80198f2: 2301 movs r3, #1
|
|
80198f4: 465a mov r2, fp
|
|
80198f6: 4631 mov r1, r6
|
|
80198f8: 4628 mov r0, r5
|
|
80198fa: 47b8 blx r7
|
|
80198fc: 3001 adds r0, #1
|
|
80198fe: f43f ae57 beq.w 80195b0 <_printf_float+0xb4>
|
|
8019902: f108 0801 add.w r8, r8, #1
|
|
8019906: 45d0 cmp r8, sl
|
|
8019908: dbf3 blt.n 80198f2 <_printf_float+0x3f6>
|
|
801990a: 464b mov r3, r9
|
|
801990c: f104 0250 add.w r2, r4, #80 @ 0x50
|
|
8019910: e6df b.n 80196d2 <_printf_float+0x1d6>
|
|
8019912: f04f 0800 mov.w r8, #0
|
|
8019916: f104 0b1a add.w fp, r4, #26
|
|
801991a: e7f4 b.n 8019906 <_printf_float+0x40a>
|
|
801991c: 2301 movs r3, #1
|
|
801991e: 4642 mov r2, r8
|
|
8019920: e7e1 b.n 80198e6 <_printf_float+0x3ea>
|
|
8019922: 2301 movs r3, #1
|
|
8019924: 464a mov r2, r9
|
|
8019926: 4631 mov r1, r6
|
|
8019928: 4628 mov r0, r5
|
|
801992a: 47b8 blx r7
|
|
801992c: 3001 adds r0, #1
|
|
801992e: f43f ae3f beq.w 80195b0 <_printf_float+0xb4>
|
|
8019932: f108 0801 add.w r8, r8, #1
|
|
8019936: 68e3 ldr r3, [r4, #12]
|
|
8019938: 990b ldr r1, [sp, #44] @ 0x2c
|
|
801993a: 1a5b subs r3, r3, r1
|
|
801993c: 4543 cmp r3, r8
|
|
801993e: dcf0 bgt.n 8019922 <_printf_float+0x426>
|
|
8019940: e6fc b.n 801973c <_printf_float+0x240>
|
|
8019942: f04f 0800 mov.w r8, #0
|
|
8019946: f104 0919 add.w r9, r4, #25
|
|
801994a: e7f4 b.n 8019936 <_printf_float+0x43a>
|
|
|
|
0801994c <_printf_common>:
|
|
801994c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8019950: 4616 mov r6, r2
|
|
8019952: 4698 mov r8, r3
|
|
8019954: 688a ldr r2, [r1, #8]
|
|
8019956: 690b ldr r3, [r1, #16]
|
|
8019958: f8dd 9020 ldr.w r9, [sp, #32]
|
|
801995c: 4293 cmp r3, r2
|
|
801995e: bfb8 it lt
|
|
8019960: 4613 movlt r3, r2
|
|
8019962: 6033 str r3, [r6, #0]
|
|
8019964: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
|
|
8019968: 4607 mov r7, r0
|
|
801996a: 460c mov r4, r1
|
|
801996c: b10a cbz r2, 8019972 <_printf_common+0x26>
|
|
801996e: 3301 adds r3, #1
|
|
8019970: 6033 str r3, [r6, #0]
|
|
8019972: 6823 ldr r3, [r4, #0]
|
|
8019974: 0699 lsls r1, r3, #26
|
|
8019976: bf42 ittt mi
|
|
8019978: 6833 ldrmi r3, [r6, #0]
|
|
801997a: 3302 addmi r3, #2
|
|
801997c: 6033 strmi r3, [r6, #0]
|
|
801997e: 6825 ldr r5, [r4, #0]
|
|
8019980: f015 0506 ands.w r5, r5, #6
|
|
8019984: d106 bne.n 8019994 <_printf_common+0x48>
|
|
8019986: f104 0a19 add.w sl, r4, #25
|
|
801998a: 68e3 ldr r3, [r4, #12]
|
|
801998c: 6832 ldr r2, [r6, #0]
|
|
801998e: 1a9b subs r3, r3, r2
|
|
8019990: 42ab cmp r3, r5
|
|
8019992: dc26 bgt.n 80199e2 <_printf_common+0x96>
|
|
8019994: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
|
|
8019998: 6822 ldr r2, [r4, #0]
|
|
801999a: 3b00 subs r3, #0
|
|
801999c: bf18 it ne
|
|
801999e: 2301 movne r3, #1
|
|
80199a0: 0692 lsls r2, r2, #26
|
|
80199a2: d42b bmi.n 80199fc <_printf_common+0xb0>
|
|
80199a4: f104 0243 add.w r2, r4, #67 @ 0x43
|
|
80199a8: 4641 mov r1, r8
|
|
80199aa: 4638 mov r0, r7
|
|
80199ac: 47c8 blx r9
|
|
80199ae: 3001 adds r0, #1
|
|
80199b0: d01e beq.n 80199f0 <_printf_common+0xa4>
|
|
80199b2: 6823 ldr r3, [r4, #0]
|
|
80199b4: 6922 ldr r2, [r4, #16]
|
|
80199b6: f003 0306 and.w r3, r3, #6
|
|
80199ba: 2b04 cmp r3, #4
|
|
80199bc: bf02 ittt eq
|
|
80199be: 68e5 ldreq r5, [r4, #12]
|
|
80199c0: 6833 ldreq r3, [r6, #0]
|
|
80199c2: 1aed subeq r5, r5, r3
|
|
80199c4: 68a3 ldr r3, [r4, #8]
|
|
80199c6: bf0c ite eq
|
|
80199c8: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
80199cc: 2500 movne r5, #0
|
|
80199ce: 4293 cmp r3, r2
|
|
80199d0: bfc4 itt gt
|
|
80199d2: 1a9b subgt r3, r3, r2
|
|
80199d4: 18ed addgt r5, r5, r3
|
|
80199d6: 2600 movs r6, #0
|
|
80199d8: 341a adds r4, #26
|
|
80199da: 42b5 cmp r5, r6
|
|
80199dc: d11a bne.n 8019a14 <_printf_common+0xc8>
|
|
80199de: 2000 movs r0, #0
|
|
80199e0: e008 b.n 80199f4 <_printf_common+0xa8>
|
|
80199e2: 2301 movs r3, #1
|
|
80199e4: 4652 mov r2, sl
|
|
80199e6: 4641 mov r1, r8
|
|
80199e8: 4638 mov r0, r7
|
|
80199ea: 47c8 blx r9
|
|
80199ec: 3001 adds r0, #1
|
|
80199ee: d103 bne.n 80199f8 <_printf_common+0xac>
|
|
80199f0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80199f4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
80199f8: 3501 adds r5, #1
|
|
80199fa: e7c6 b.n 801998a <_printf_common+0x3e>
|
|
80199fc: 18e1 adds r1, r4, r3
|
|
80199fe: 1c5a adds r2, r3, #1
|
|
8019a00: 2030 movs r0, #48 @ 0x30
|
|
8019a02: f881 0043 strb.w r0, [r1, #67] @ 0x43
|
|
8019a06: 4422 add r2, r4
|
|
8019a08: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
|
|
8019a0c: f882 1043 strb.w r1, [r2, #67] @ 0x43
|
|
8019a10: 3302 adds r3, #2
|
|
8019a12: e7c7 b.n 80199a4 <_printf_common+0x58>
|
|
8019a14: 2301 movs r3, #1
|
|
8019a16: 4622 mov r2, r4
|
|
8019a18: 4641 mov r1, r8
|
|
8019a1a: 4638 mov r0, r7
|
|
8019a1c: 47c8 blx r9
|
|
8019a1e: 3001 adds r0, #1
|
|
8019a20: d0e6 beq.n 80199f0 <_printf_common+0xa4>
|
|
8019a22: 3601 adds r6, #1
|
|
8019a24: e7d9 b.n 80199da <_printf_common+0x8e>
|
|
...
|
|
|
|
08019a28 <_printf_i>:
|
|
8019a28: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
|
|
8019a2c: 7e0d ldrb r5, [r1, #24]
|
|
8019a2e: b085 sub sp, #20
|
|
8019a30: 2d78 cmp r5, #120 @ 0x78
|
|
8019a32: 4690 mov r8, r2
|
|
8019a34: 9e0c ldr r6, [sp, #48] @ 0x30
|
|
8019a36: 4607 mov r7, r0
|
|
8019a38: 460c mov r4, r1
|
|
8019a3a: 4699 mov r9, r3
|
|
8019a3c: f101 0243 add.w r2, r1, #67 @ 0x43
|
|
8019a40: d807 bhi.n 8019a52 <_printf_i+0x2a>
|
|
8019a42: 2d62 cmp r5, #98 @ 0x62
|
|
8019a44: d80a bhi.n 8019a5c <_printf_i+0x34>
|
|
8019a46: 2d00 cmp r5, #0
|
|
8019a48: f000 80d7 beq.w 8019bfa <_printf_i+0x1d2>
|
|
8019a4c: 2d58 cmp r5, #88 @ 0x58
|
|
8019a4e: f000 80bc beq.w 8019bca <_printf_i+0x1a2>
|
|
8019a52: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8019a56: f884 5042 strb.w r5, [r4, #66] @ 0x42
|
|
8019a5a: e03b b.n 8019ad4 <_printf_i+0xac>
|
|
8019a5c: f1a5 0363 sub.w r3, r5, #99 @ 0x63
|
|
8019a60: 2b15 cmp r3, #21
|
|
8019a62: d8f6 bhi.n 8019a52 <_printf_i+0x2a>
|
|
8019a64: a101 add r1, pc, #4 @ (adr r1, 8019a6c <_printf_i+0x44>)
|
|
8019a66: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
8019a6a: bf00 nop
|
|
8019a6c: 08019ac5 .word 0x08019ac5
|
|
8019a70: 08019ad9 .word 0x08019ad9
|
|
8019a74: 08019a53 .word 0x08019a53
|
|
8019a78: 08019a53 .word 0x08019a53
|
|
8019a7c: 08019a53 .word 0x08019a53
|
|
8019a80: 08019a53 .word 0x08019a53
|
|
8019a84: 08019ad9 .word 0x08019ad9
|
|
8019a88: 08019a53 .word 0x08019a53
|
|
8019a8c: 08019a53 .word 0x08019a53
|
|
8019a90: 08019a53 .word 0x08019a53
|
|
8019a94: 08019a53 .word 0x08019a53
|
|
8019a98: 08019be1 .word 0x08019be1
|
|
8019a9c: 08019b03 .word 0x08019b03
|
|
8019aa0: 08019b93 .word 0x08019b93
|
|
8019aa4: 08019a53 .word 0x08019a53
|
|
8019aa8: 08019a53 .word 0x08019a53
|
|
8019aac: 08019c03 .word 0x08019c03
|
|
8019ab0: 08019a53 .word 0x08019a53
|
|
8019ab4: 08019b03 .word 0x08019b03
|
|
8019ab8: 08019a53 .word 0x08019a53
|
|
8019abc: 08019a53 .word 0x08019a53
|
|
8019ac0: 08019b9b .word 0x08019b9b
|
|
8019ac4: 6833 ldr r3, [r6, #0]
|
|
8019ac6: 1d1a adds r2, r3, #4
|
|
8019ac8: 681b ldr r3, [r3, #0]
|
|
8019aca: 6032 str r2, [r6, #0]
|
|
8019acc: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8019ad0: f884 3042 strb.w r3, [r4, #66] @ 0x42
|
|
8019ad4: 2301 movs r3, #1
|
|
8019ad6: e0a1 b.n 8019c1c <_printf_i+0x1f4>
|
|
8019ad8: 6833 ldr r3, [r6, #0]
|
|
8019ada: 6820 ldr r0, [r4, #0]
|
|
8019adc: 1d19 adds r1, r3, #4
|
|
8019ade: 6031 str r1, [r6, #0]
|
|
8019ae0: 0606 lsls r6, r0, #24
|
|
8019ae2: d501 bpl.n 8019ae8 <_printf_i+0xc0>
|
|
8019ae4: 681d ldr r5, [r3, #0]
|
|
8019ae6: e003 b.n 8019af0 <_printf_i+0xc8>
|
|
8019ae8: 0645 lsls r5, r0, #25
|
|
8019aea: d5fb bpl.n 8019ae4 <_printf_i+0xbc>
|
|
8019aec: f9b3 5000 ldrsh.w r5, [r3]
|
|
8019af0: 2d00 cmp r5, #0
|
|
8019af2: da03 bge.n 8019afc <_printf_i+0xd4>
|
|
8019af4: 232d movs r3, #45 @ 0x2d
|
|
8019af6: 426d negs r5, r5
|
|
8019af8: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8019afc: 485b ldr r0, [pc, #364] @ (8019c6c <_printf_i+0x244>)
|
|
8019afe: 230a movs r3, #10
|
|
8019b00: e011 b.n 8019b26 <_printf_i+0xfe>
|
|
8019b02: 6821 ldr r1, [r4, #0]
|
|
8019b04: 6833 ldr r3, [r6, #0]
|
|
8019b06: 0608 lsls r0, r1, #24
|
|
8019b08: f853 5b04 ldr.w r5, [r3], #4
|
|
8019b0c: d402 bmi.n 8019b14 <_printf_i+0xec>
|
|
8019b0e: 0649 lsls r1, r1, #25
|
|
8019b10: bf48 it mi
|
|
8019b12: b2ad uxthmi r5, r5
|
|
8019b14: 6033 str r3, [r6, #0]
|
|
8019b16: 7e23 ldrb r3, [r4, #24]
|
|
8019b18: 4854 ldr r0, [pc, #336] @ (8019c6c <_printf_i+0x244>)
|
|
8019b1a: 2b6f cmp r3, #111 @ 0x6f
|
|
8019b1c: d15c bne.n 8019bd8 <_printf_i+0x1b0>
|
|
8019b1e: 2308 movs r3, #8
|
|
8019b20: 2100 movs r1, #0
|
|
8019b22: f884 1043 strb.w r1, [r4, #67] @ 0x43
|
|
8019b26: 6866 ldr r6, [r4, #4]
|
|
8019b28: 60a6 str r6, [r4, #8]
|
|
8019b2a: 2e00 cmp r6, #0
|
|
8019b2c: db05 blt.n 8019b3a <_printf_i+0x112>
|
|
8019b2e: 6821 ldr r1, [r4, #0]
|
|
8019b30: 432e orrs r6, r5
|
|
8019b32: f021 0104 bic.w r1, r1, #4
|
|
8019b36: 6021 str r1, [r4, #0]
|
|
8019b38: d050 beq.n 8019bdc <_printf_i+0x1b4>
|
|
8019b3a: 4616 mov r6, r2
|
|
8019b3c: fbb5 f1f3 udiv r1, r5, r3
|
|
8019b40: fb03 5c11 mls ip, r3, r1, r5
|
|
8019b44: f810 c00c ldrb.w ip, [r0, ip]
|
|
8019b48: f806 cd01 strb.w ip, [r6, #-1]!
|
|
8019b4c: 46ac mov ip, r5
|
|
8019b4e: 4563 cmp r3, ip
|
|
8019b50: 460d mov r5, r1
|
|
8019b52: d9f3 bls.n 8019b3c <_printf_i+0x114>
|
|
8019b54: 2b08 cmp r3, #8
|
|
8019b56: d10b bne.n 8019b70 <_printf_i+0x148>
|
|
8019b58: 6823 ldr r3, [r4, #0]
|
|
8019b5a: 07db lsls r3, r3, #31
|
|
8019b5c: d508 bpl.n 8019b70 <_printf_i+0x148>
|
|
8019b5e: 6923 ldr r3, [r4, #16]
|
|
8019b60: 6861 ldr r1, [r4, #4]
|
|
8019b62: 4299 cmp r1, r3
|
|
8019b64: bfde ittt le
|
|
8019b66: 2330 movle r3, #48 @ 0x30
|
|
8019b68: f806 3c01 strble.w r3, [r6, #-1]
|
|
8019b6c: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
|
|
8019b70: 1b92 subs r2, r2, r6
|
|
8019b72: 6122 str r2, [r4, #16]
|
|
8019b74: f8cd 9000 str.w r9, [sp]
|
|
8019b78: 4643 mov r3, r8
|
|
8019b7a: aa03 add r2, sp, #12
|
|
8019b7c: 4621 mov r1, r4
|
|
8019b7e: 4638 mov r0, r7
|
|
8019b80: f7ff fee4 bl 801994c <_printf_common>
|
|
8019b84: 3001 adds r0, #1
|
|
8019b86: d14e bne.n 8019c26 <_printf_i+0x1fe>
|
|
8019b88: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8019b8c: b005 add sp, #20
|
|
8019b8e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
8019b92: 6823 ldr r3, [r4, #0]
|
|
8019b94: f043 0320 orr.w r3, r3, #32
|
|
8019b98: 6023 str r3, [r4, #0]
|
|
8019b9a: 4835 ldr r0, [pc, #212] @ (8019c70 <_printf_i+0x248>)
|
|
8019b9c: 2578 movs r5, #120 @ 0x78
|
|
8019b9e: f884 5045 strb.w r5, [r4, #69] @ 0x45
|
|
8019ba2: 6823 ldr r3, [r4, #0]
|
|
8019ba4: 6831 ldr r1, [r6, #0]
|
|
8019ba6: f013 0f80 tst.w r3, #128 @ 0x80
|
|
8019baa: f851 5b04 ldr.w r5, [r1], #4
|
|
8019bae: d103 bne.n 8019bb8 <_printf_i+0x190>
|
|
8019bb0: f013 0f40 tst.w r3, #64 @ 0x40
|
|
8019bb4: bf18 it ne
|
|
8019bb6: b2ad uxthne r5, r5
|
|
8019bb8: 6031 str r1, [r6, #0]
|
|
8019bba: 07d9 lsls r1, r3, #31
|
|
8019bbc: bf44 itt mi
|
|
8019bbe: f043 0320 orrmi.w r3, r3, #32
|
|
8019bc2: 6023 strmi r3, [r4, #0]
|
|
8019bc4: b11d cbz r5, 8019bce <_printf_i+0x1a6>
|
|
8019bc6: 2310 movs r3, #16
|
|
8019bc8: e7aa b.n 8019b20 <_printf_i+0xf8>
|
|
8019bca: 4828 ldr r0, [pc, #160] @ (8019c6c <_printf_i+0x244>)
|
|
8019bcc: e7e7 b.n 8019b9e <_printf_i+0x176>
|
|
8019bce: 6823 ldr r3, [r4, #0]
|
|
8019bd0: f023 0320 bic.w r3, r3, #32
|
|
8019bd4: 6023 str r3, [r4, #0]
|
|
8019bd6: e7f6 b.n 8019bc6 <_printf_i+0x19e>
|
|
8019bd8: 230a movs r3, #10
|
|
8019bda: e7a1 b.n 8019b20 <_printf_i+0xf8>
|
|
8019bdc: 4616 mov r6, r2
|
|
8019bde: e7b9 b.n 8019b54 <_printf_i+0x12c>
|
|
8019be0: 6833 ldr r3, [r6, #0]
|
|
8019be2: 6825 ldr r5, [r4, #0]
|
|
8019be4: 6961 ldr r1, [r4, #20]
|
|
8019be6: 1d18 adds r0, r3, #4
|
|
8019be8: 6030 str r0, [r6, #0]
|
|
8019bea: 062e lsls r6, r5, #24
|
|
8019bec: 681b ldr r3, [r3, #0]
|
|
8019bee: d501 bpl.n 8019bf4 <_printf_i+0x1cc>
|
|
8019bf0: 6019 str r1, [r3, #0]
|
|
8019bf2: e002 b.n 8019bfa <_printf_i+0x1d2>
|
|
8019bf4: 0668 lsls r0, r5, #25
|
|
8019bf6: d5fb bpl.n 8019bf0 <_printf_i+0x1c8>
|
|
8019bf8: 8019 strh r1, [r3, #0]
|
|
8019bfa: 2300 movs r3, #0
|
|
8019bfc: 6123 str r3, [r4, #16]
|
|
8019bfe: 4616 mov r6, r2
|
|
8019c00: e7b8 b.n 8019b74 <_printf_i+0x14c>
|
|
8019c02: 6833 ldr r3, [r6, #0]
|
|
8019c04: 1d1a adds r2, r3, #4
|
|
8019c06: 6032 str r2, [r6, #0]
|
|
8019c08: 681e ldr r6, [r3, #0]
|
|
8019c0a: 6862 ldr r2, [r4, #4]
|
|
8019c0c: 2100 movs r1, #0
|
|
8019c0e: 4630 mov r0, r6
|
|
8019c10: f7e6 fab6 bl 8000180 <memchr>
|
|
8019c14: b108 cbz r0, 8019c1a <_printf_i+0x1f2>
|
|
8019c16: 1b80 subs r0, r0, r6
|
|
8019c18: 6060 str r0, [r4, #4]
|
|
8019c1a: 6863 ldr r3, [r4, #4]
|
|
8019c1c: 6123 str r3, [r4, #16]
|
|
8019c1e: 2300 movs r3, #0
|
|
8019c20: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8019c24: e7a6 b.n 8019b74 <_printf_i+0x14c>
|
|
8019c26: 6923 ldr r3, [r4, #16]
|
|
8019c28: 4632 mov r2, r6
|
|
8019c2a: 4641 mov r1, r8
|
|
8019c2c: 4638 mov r0, r7
|
|
8019c2e: 47c8 blx r9
|
|
8019c30: 3001 adds r0, #1
|
|
8019c32: d0a9 beq.n 8019b88 <_printf_i+0x160>
|
|
8019c34: 6823 ldr r3, [r4, #0]
|
|
8019c36: 079b lsls r3, r3, #30
|
|
8019c38: d413 bmi.n 8019c62 <_printf_i+0x23a>
|
|
8019c3a: 68e0 ldr r0, [r4, #12]
|
|
8019c3c: 9b03 ldr r3, [sp, #12]
|
|
8019c3e: 4298 cmp r0, r3
|
|
8019c40: bfb8 it lt
|
|
8019c42: 4618 movlt r0, r3
|
|
8019c44: e7a2 b.n 8019b8c <_printf_i+0x164>
|
|
8019c46: 2301 movs r3, #1
|
|
8019c48: 4632 mov r2, r6
|
|
8019c4a: 4641 mov r1, r8
|
|
8019c4c: 4638 mov r0, r7
|
|
8019c4e: 47c8 blx r9
|
|
8019c50: 3001 adds r0, #1
|
|
8019c52: d099 beq.n 8019b88 <_printf_i+0x160>
|
|
8019c54: 3501 adds r5, #1
|
|
8019c56: 68e3 ldr r3, [r4, #12]
|
|
8019c58: 9903 ldr r1, [sp, #12]
|
|
8019c5a: 1a5b subs r3, r3, r1
|
|
8019c5c: 42ab cmp r3, r5
|
|
8019c5e: dcf2 bgt.n 8019c46 <_printf_i+0x21e>
|
|
8019c60: e7eb b.n 8019c3a <_printf_i+0x212>
|
|
8019c62: 2500 movs r5, #0
|
|
8019c64: f104 0619 add.w r6, r4, #25
|
|
8019c68: e7f5 b.n 8019c56 <_printf_i+0x22e>
|
|
8019c6a: bf00 nop
|
|
8019c6c: 0801e622 .word 0x0801e622
|
|
8019c70: 0801e633 .word 0x0801e633
|
|
|
|
08019c74 <_scanf_float>:
|
|
8019c74: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8019c78: b087 sub sp, #28
|
|
8019c7a: 4691 mov r9, r2
|
|
8019c7c: 9303 str r3, [sp, #12]
|
|
8019c7e: 688b ldr r3, [r1, #8]
|
|
8019c80: 1e5a subs r2, r3, #1
|
|
8019c82: f5b2 7fae cmp.w r2, #348 @ 0x15c
|
|
8019c86: bf81 itttt hi
|
|
8019c88: f46f 75ae mvnhi.w r5, #348 @ 0x15c
|
|
8019c8c: eb03 0b05 addhi.w fp, r3, r5
|
|
8019c90: f240 135d movwhi r3, #349 @ 0x15d
|
|
8019c94: 608b strhi r3, [r1, #8]
|
|
8019c96: 680b ldr r3, [r1, #0]
|
|
8019c98: 460a mov r2, r1
|
|
8019c9a: f04f 0500 mov.w r5, #0
|
|
8019c9e: f443 63f0 orr.w r3, r3, #1920 @ 0x780
|
|
8019ca2: f842 3b1c str.w r3, [r2], #28
|
|
8019ca6: e9cd 5504 strd r5, r5, [sp, #16]
|
|
8019caa: 4680 mov r8, r0
|
|
8019cac: 460c mov r4, r1
|
|
8019cae: bf98 it ls
|
|
8019cb0: f04f 0b00 movls.w fp, #0
|
|
8019cb4: 9201 str r2, [sp, #4]
|
|
8019cb6: 4616 mov r6, r2
|
|
8019cb8: 46aa mov sl, r5
|
|
8019cba: 462f mov r7, r5
|
|
8019cbc: 9502 str r5, [sp, #8]
|
|
8019cbe: 68a2 ldr r2, [r4, #8]
|
|
8019cc0: b15a cbz r2, 8019cda <_scanf_float+0x66>
|
|
8019cc2: f8d9 3000 ldr.w r3, [r9]
|
|
8019cc6: 781b ldrb r3, [r3, #0]
|
|
8019cc8: 2b4e cmp r3, #78 @ 0x4e
|
|
8019cca: d863 bhi.n 8019d94 <_scanf_float+0x120>
|
|
8019ccc: 2b40 cmp r3, #64 @ 0x40
|
|
8019cce: d83b bhi.n 8019d48 <_scanf_float+0xd4>
|
|
8019cd0: f1a3 012b sub.w r1, r3, #43 @ 0x2b
|
|
8019cd4: b2c8 uxtb r0, r1
|
|
8019cd6: 280e cmp r0, #14
|
|
8019cd8: d939 bls.n 8019d4e <_scanf_float+0xda>
|
|
8019cda: b11f cbz r7, 8019ce4 <_scanf_float+0x70>
|
|
8019cdc: 6823 ldr r3, [r4, #0]
|
|
8019cde: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8019ce2: 6023 str r3, [r4, #0]
|
|
8019ce4: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
8019ce8: f1ba 0f01 cmp.w sl, #1
|
|
8019cec: f200 8114 bhi.w 8019f18 <_scanf_float+0x2a4>
|
|
8019cf0: 9b01 ldr r3, [sp, #4]
|
|
8019cf2: 429e cmp r6, r3
|
|
8019cf4: f200 8105 bhi.w 8019f02 <_scanf_float+0x28e>
|
|
8019cf8: 2001 movs r0, #1
|
|
8019cfa: b007 add sp, #28
|
|
8019cfc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8019d00: f1a3 0261 sub.w r2, r3, #97 @ 0x61
|
|
8019d04: 2a0d cmp r2, #13
|
|
8019d06: d8e8 bhi.n 8019cda <_scanf_float+0x66>
|
|
8019d08: a101 add r1, pc, #4 @ (adr r1, 8019d10 <_scanf_float+0x9c>)
|
|
8019d0a: f851 f022 ldr.w pc, [r1, r2, lsl #2]
|
|
8019d0e: bf00 nop
|
|
8019d10: 08019e59 .word 0x08019e59
|
|
8019d14: 08019cdb .word 0x08019cdb
|
|
8019d18: 08019cdb .word 0x08019cdb
|
|
8019d1c: 08019cdb .word 0x08019cdb
|
|
8019d20: 08019eb5 .word 0x08019eb5
|
|
8019d24: 08019e8f .word 0x08019e8f
|
|
8019d28: 08019cdb .word 0x08019cdb
|
|
8019d2c: 08019cdb .word 0x08019cdb
|
|
8019d30: 08019e67 .word 0x08019e67
|
|
8019d34: 08019cdb .word 0x08019cdb
|
|
8019d38: 08019cdb .word 0x08019cdb
|
|
8019d3c: 08019cdb .word 0x08019cdb
|
|
8019d40: 08019cdb .word 0x08019cdb
|
|
8019d44: 08019e23 .word 0x08019e23
|
|
8019d48: f1a3 0241 sub.w r2, r3, #65 @ 0x41
|
|
8019d4c: e7da b.n 8019d04 <_scanf_float+0x90>
|
|
8019d4e: 290e cmp r1, #14
|
|
8019d50: d8c3 bhi.n 8019cda <_scanf_float+0x66>
|
|
8019d52: a001 add r0, pc, #4 @ (adr r0, 8019d58 <_scanf_float+0xe4>)
|
|
8019d54: f850 f021 ldr.w pc, [r0, r1, lsl #2]
|
|
8019d58: 08019e13 .word 0x08019e13
|
|
8019d5c: 08019cdb .word 0x08019cdb
|
|
8019d60: 08019e13 .word 0x08019e13
|
|
8019d64: 08019ea3 .word 0x08019ea3
|
|
8019d68: 08019cdb .word 0x08019cdb
|
|
8019d6c: 08019db5 .word 0x08019db5
|
|
8019d70: 08019df9 .word 0x08019df9
|
|
8019d74: 08019df9 .word 0x08019df9
|
|
8019d78: 08019df9 .word 0x08019df9
|
|
8019d7c: 08019df9 .word 0x08019df9
|
|
8019d80: 08019df9 .word 0x08019df9
|
|
8019d84: 08019df9 .word 0x08019df9
|
|
8019d88: 08019df9 .word 0x08019df9
|
|
8019d8c: 08019df9 .word 0x08019df9
|
|
8019d90: 08019df9 .word 0x08019df9
|
|
8019d94: 2b6e cmp r3, #110 @ 0x6e
|
|
8019d96: d809 bhi.n 8019dac <_scanf_float+0x138>
|
|
8019d98: 2b60 cmp r3, #96 @ 0x60
|
|
8019d9a: d8b1 bhi.n 8019d00 <_scanf_float+0x8c>
|
|
8019d9c: 2b54 cmp r3, #84 @ 0x54
|
|
8019d9e: d07b beq.n 8019e98 <_scanf_float+0x224>
|
|
8019da0: 2b59 cmp r3, #89 @ 0x59
|
|
8019da2: d19a bne.n 8019cda <_scanf_float+0x66>
|
|
8019da4: 2d07 cmp r5, #7
|
|
8019da6: d198 bne.n 8019cda <_scanf_float+0x66>
|
|
8019da8: 2508 movs r5, #8
|
|
8019daa: e02f b.n 8019e0c <_scanf_float+0x198>
|
|
8019dac: 2b74 cmp r3, #116 @ 0x74
|
|
8019dae: d073 beq.n 8019e98 <_scanf_float+0x224>
|
|
8019db0: 2b79 cmp r3, #121 @ 0x79
|
|
8019db2: e7f6 b.n 8019da2 <_scanf_float+0x12e>
|
|
8019db4: 6821 ldr r1, [r4, #0]
|
|
8019db6: 05c8 lsls r0, r1, #23
|
|
8019db8: d51e bpl.n 8019df8 <_scanf_float+0x184>
|
|
8019dba: f021 0180 bic.w r1, r1, #128 @ 0x80
|
|
8019dbe: 6021 str r1, [r4, #0]
|
|
8019dc0: 3701 adds r7, #1
|
|
8019dc2: f1bb 0f00 cmp.w fp, #0
|
|
8019dc6: d003 beq.n 8019dd0 <_scanf_float+0x15c>
|
|
8019dc8: 3201 adds r2, #1
|
|
8019dca: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff
|
|
8019dce: 60a2 str r2, [r4, #8]
|
|
8019dd0: 68a3 ldr r3, [r4, #8]
|
|
8019dd2: 3b01 subs r3, #1
|
|
8019dd4: 60a3 str r3, [r4, #8]
|
|
8019dd6: 6923 ldr r3, [r4, #16]
|
|
8019dd8: 3301 adds r3, #1
|
|
8019dda: 6123 str r3, [r4, #16]
|
|
8019ddc: f8d9 3004 ldr.w r3, [r9, #4]
|
|
8019de0: 3b01 subs r3, #1
|
|
8019de2: 2b00 cmp r3, #0
|
|
8019de4: f8c9 3004 str.w r3, [r9, #4]
|
|
8019de8: f340 8082 ble.w 8019ef0 <_scanf_float+0x27c>
|
|
8019dec: f8d9 3000 ldr.w r3, [r9]
|
|
8019df0: 3301 adds r3, #1
|
|
8019df2: f8c9 3000 str.w r3, [r9]
|
|
8019df6: e762 b.n 8019cbe <_scanf_float+0x4a>
|
|
8019df8: eb1a 0105 adds.w r1, sl, r5
|
|
8019dfc: f47f af6d bne.w 8019cda <_scanf_float+0x66>
|
|
8019e00: 6822 ldr r2, [r4, #0]
|
|
8019e02: f422 72c0 bic.w r2, r2, #384 @ 0x180
|
|
8019e06: 6022 str r2, [r4, #0]
|
|
8019e08: 460d mov r5, r1
|
|
8019e0a: 468a mov sl, r1
|
|
8019e0c: f806 3b01 strb.w r3, [r6], #1
|
|
8019e10: e7de b.n 8019dd0 <_scanf_float+0x15c>
|
|
8019e12: 6822 ldr r2, [r4, #0]
|
|
8019e14: 0610 lsls r0, r2, #24
|
|
8019e16: f57f af60 bpl.w 8019cda <_scanf_float+0x66>
|
|
8019e1a: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
8019e1e: 6022 str r2, [r4, #0]
|
|
8019e20: e7f4 b.n 8019e0c <_scanf_float+0x198>
|
|
8019e22: f1ba 0f00 cmp.w sl, #0
|
|
8019e26: d10c bne.n 8019e42 <_scanf_float+0x1ce>
|
|
8019e28: b977 cbnz r7, 8019e48 <_scanf_float+0x1d4>
|
|
8019e2a: 6822 ldr r2, [r4, #0]
|
|
8019e2c: f402 61e0 and.w r1, r2, #1792 @ 0x700
|
|
8019e30: f5b1 6fe0 cmp.w r1, #1792 @ 0x700
|
|
8019e34: d108 bne.n 8019e48 <_scanf_float+0x1d4>
|
|
8019e36: f422 62f0 bic.w r2, r2, #1920 @ 0x780
|
|
8019e3a: 6022 str r2, [r4, #0]
|
|
8019e3c: f04f 0a01 mov.w sl, #1
|
|
8019e40: e7e4 b.n 8019e0c <_scanf_float+0x198>
|
|
8019e42: f1ba 0f02 cmp.w sl, #2
|
|
8019e46: d050 beq.n 8019eea <_scanf_float+0x276>
|
|
8019e48: 2d01 cmp r5, #1
|
|
8019e4a: d002 beq.n 8019e52 <_scanf_float+0x1de>
|
|
8019e4c: 2d04 cmp r5, #4
|
|
8019e4e: f47f af44 bne.w 8019cda <_scanf_float+0x66>
|
|
8019e52: 3501 adds r5, #1
|
|
8019e54: b2ed uxtb r5, r5
|
|
8019e56: e7d9 b.n 8019e0c <_scanf_float+0x198>
|
|
8019e58: f1ba 0f01 cmp.w sl, #1
|
|
8019e5c: f47f af3d bne.w 8019cda <_scanf_float+0x66>
|
|
8019e60: f04f 0a02 mov.w sl, #2
|
|
8019e64: e7d2 b.n 8019e0c <_scanf_float+0x198>
|
|
8019e66: b975 cbnz r5, 8019e86 <_scanf_float+0x212>
|
|
8019e68: 2f00 cmp r7, #0
|
|
8019e6a: f47f af37 bne.w 8019cdc <_scanf_float+0x68>
|
|
8019e6e: 6822 ldr r2, [r4, #0]
|
|
8019e70: f402 61e0 and.w r1, r2, #1792 @ 0x700
|
|
8019e74: f5b1 6fe0 cmp.w r1, #1792 @ 0x700
|
|
8019e78: f040 8102 bne.w 801a080 <_scanf_float+0x40c>
|
|
8019e7c: f422 62f0 bic.w r2, r2, #1920 @ 0x780
|
|
8019e80: 6022 str r2, [r4, #0]
|
|
8019e82: 2501 movs r5, #1
|
|
8019e84: e7c2 b.n 8019e0c <_scanf_float+0x198>
|
|
8019e86: 2d03 cmp r5, #3
|
|
8019e88: d0e3 beq.n 8019e52 <_scanf_float+0x1de>
|
|
8019e8a: 2d05 cmp r5, #5
|
|
8019e8c: e7df b.n 8019e4e <_scanf_float+0x1da>
|
|
8019e8e: 2d02 cmp r5, #2
|
|
8019e90: f47f af23 bne.w 8019cda <_scanf_float+0x66>
|
|
8019e94: 2503 movs r5, #3
|
|
8019e96: e7b9 b.n 8019e0c <_scanf_float+0x198>
|
|
8019e98: 2d06 cmp r5, #6
|
|
8019e9a: f47f af1e bne.w 8019cda <_scanf_float+0x66>
|
|
8019e9e: 2507 movs r5, #7
|
|
8019ea0: e7b4 b.n 8019e0c <_scanf_float+0x198>
|
|
8019ea2: 6822 ldr r2, [r4, #0]
|
|
8019ea4: 0591 lsls r1, r2, #22
|
|
8019ea6: f57f af18 bpl.w 8019cda <_scanf_float+0x66>
|
|
8019eaa: f422 7220 bic.w r2, r2, #640 @ 0x280
|
|
8019eae: 6022 str r2, [r4, #0]
|
|
8019eb0: 9702 str r7, [sp, #8]
|
|
8019eb2: e7ab b.n 8019e0c <_scanf_float+0x198>
|
|
8019eb4: 6822 ldr r2, [r4, #0]
|
|
8019eb6: f402 61a0 and.w r1, r2, #1280 @ 0x500
|
|
8019eba: f5b1 6f80 cmp.w r1, #1024 @ 0x400
|
|
8019ebe: d005 beq.n 8019ecc <_scanf_float+0x258>
|
|
8019ec0: 0550 lsls r0, r2, #21
|
|
8019ec2: f57f af0a bpl.w 8019cda <_scanf_float+0x66>
|
|
8019ec6: 2f00 cmp r7, #0
|
|
8019ec8: f000 80da beq.w 801a080 <_scanf_float+0x40c>
|
|
8019ecc: 0591 lsls r1, r2, #22
|
|
8019ece: bf58 it pl
|
|
8019ed0: 9902 ldrpl r1, [sp, #8]
|
|
8019ed2: f422 62f0 bic.w r2, r2, #1920 @ 0x780
|
|
8019ed6: bf58 it pl
|
|
8019ed8: 1a79 subpl r1, r7, r1
|
|
8019eda: f442 72c0 orr.w r2, r2, #384 @ 0x180
|
|
8019ede: bf58 it pl
|
|
8019ee0: e9cd 1604 strdpl r1, r6, [sp, #16]
|
|
8019ee4: 6022 str r2, [r4, #0]
|
|
8019ee6: 2700 movs r7, #0
|
|
8019ee8: e790 b.n 8019e0c <_scanf_float+0x198>
|
|
8019eea: f04f 0a03 mov.w sl, #3
|
|
8019eee: e78d b.n 8019e0c <_scanf_float+0x198>
|
|
8019ef0: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180
|
|
8019ef4: 4649 mov r1, r9
|
|
8019ef6: 4640 mov r0, r8
|
|
8019ef8: 4798 blx r3
|
|
8019efa: 2800 cmp r0, #0
|
|
8019efc: f43f aedf beq.w 8019cbe <_scanf_float+0x4a>
|
|
8019f00: e6eb b.n 8019cda <_scanf_float+0x66>
|
|
8019f02: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
8019f06: f816 1d01 ldrb.w r1, [r6, #-1]!
|
|
8019f0a: 464a mov r2, r9
|
|
8019f0c: 4640 mov r0, r8
|
|
8019f0e: 4798 blx r3
|
|
8019f10: 6923 ldr r3, [r4, #16]
|
|
8019f12: 3b01 subs r3, #1
|
|
8019f14: 6123 str r3, [r4, #16]
|
|
8019f16: e6eb b.n 8019cf0 <_scanf_float+0x7c>
|
|
8019f18: 1e6b subs r3, r5, #1
|
|
8019f1a: 2b06 cmp r3, #6
|
|
8019f1c: d824 bhi.n 8019f68 <_scanf_float+0x2f4>
|
|
8019f1e: 2d02 cmp r5, #2
|
|
8019f20: d836 bhi.n 8019f90 <_scanf_float+0x31c>
|
|
8019f22: 9b01 ldr r3, [sp, #4]
|
|
8019f24: 429e cmp r6, r3
|
|
8019f26: f67f aee7 bls.w 8019cf8 <_scanf_float+0x84>
|
|
8019f2a: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
8019f2e: f816 1d01 ldrb.w r1, [r6, #-1]!
|
|
8019f32: 464a mov r2, r9
|
|
8019f34: 4640 mov r0, r8
|
|
8019f36: 4798 blx r3
|
|
8019f38: 6923 ldr r3, [r4, #16]
|
|
8019f3a: 3b01 subs r3, #1
|
|
8019f3c: 6123 str r3, [r4, #16]
|
|
8019f3e: e7f0 b.n 8019f22 <_scanf_float+0x2ae>
|
|
8019f40: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
8019f44: f81b 1d01 ldrb.w r1, [fp, #-1]!
|
|
8019f48: 464a mov r2, r9
|
|
8019f4a: 4640 mov r0, r8
|
|
8019f4c: 4798 blx r3
|
|
8019f4e: 6923 ldr r3, [r4, #16]
|
|
8019f50: 3b01 subs r3, #1
|
|
8019f52: 6123 str r3, [r4, #16]
|
|
8019f54: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
8019f58: fa5f fa8a uxtb.w sl, sl
|
|
8019f5c: f1ba 0f02 cmp.w sl, #2
|
|
8019f60: d1ee bne.n 8019f40 <_scanf_float+0x2cc>
|
|
8019f62: 3d03 subs r5, #3
|
|
8019f64: b2ed uxtb r5, r5
|
|
8019f66: 1b76 subs r6, r6, r5
|
|
8019f68: 6823 ldr r3, [r4, #0]
|
|
8019f6a: 05da lsls r2, r3, #23
|
|
8019f6c: d530 bpl.n 8019fd0 <_scanf_float+0x35c>
|
|
8019f6e: 055d lsls r5, r3, #21
|
|
8019f70: d511 bpl.n 8019f96 <_scanf_float+0x322>
|
|
8019f72: 9b01 ldr r3, [sp, #4]
|
|
8019f74: 429e cmp r6, r3
|
|
8019f76: f67f aebf bls.w 8019cf8 <_scanf_float+0x84>
|
|
8019f7a: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
8019f7e: f816 1d01 ldrb.w r1, [r6, #-1]!
|
|
8019f82: 464a mov r2, r9
|
|
8019f84: 4640 mov r0, r8
|
|
8019f86: 4798 blx r3
|
|
8019f88: 6923 ldr r3, [r4, #16]
|
|
8019f8a: 3b01 subs r3, #1
|
|
8019f8c: 6123 str r3, [r4, #16]
|
|
8019f8e: e7f0 b.n 8019f72 <_scanf_float+0x2fe>
|
|
8019f90: 46aa mov sl, r5
|
|
8019f92: 46b3 mov fp, r6
|
|
8019f94: e7de b.n 8019f54 <_scanf_float+0x2e0>
|
|
8019f96: f816 1c01 ldrb.w r1, [r6, #-1]
|
|
8019f9a: 6923 ldr r3, [r4, #16]
|
|
8019f9c: 2965 cmp r1, #101 @ 0x65
|
|
8019f9e: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff
|
|
8019fa2: f106 35ff add.w r5, r6, #4294967295 @ 0xffffffff
|
|
8019fa6: 6123 str r3, [r4, #16]
|
|
8019fa8: d00c beq.n 8019fc4 <_scanf_float+0x350>
|
|
8019faa: 2945 cmp r1, #69 @ 0x45
|
|
8019fac: d00a beq.n 8019fc4 <_scanf_float+0x350>
|
|
8019fae: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
8019fb2: 464a mov r2, r9
|
|
8019fb4: 4640 mov r0, r8
|
|
8019fb6: 4798 blx r3
|
|
8019fb8: 6923 ldr r3, [r4, #16]
|
|
8019fba: f816 1c02 ldrb.w r1, [r6, #-2]
|
|
8019fbe: 3b01 subs r3, #1
|
|
8019fc0: 1eb5 subs r5, r6, #2
|
|
8019fc2: 6123 str r3, [r4, #16]
|
|
8019fc4: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
|
|
8019fc8: 464a mov r2, r9
|
|
8019fca: 4640 mov r0, r8
|
|
8019fcc: 4798 blx r3
|
|
8019fce: 462e mov r6, r5
|
|
8019fd0: 6822 ldr r2, [r4, #0]
|
|
8019fd2: f012 0210 ands.w r2, r2, #16
|
|
8019fd6: d001 beq.n 8019fdc <_scanf_float+0x368>
|
|
8019fd8: 2000 movs r0, #0
|
|
8019fda: e68e b.n 8019cfa <_scanf_float+0x86>
|
|
8019fdc: 7032 strb r2, [r6, #0]
|
|
8019fde: 6823 ldr r3, [r4, #0]
|
|
8019fe0: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8019fe4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8019fe8: d124 bne.n 801a034 <_scanf_float+0x3c0>
|
|
8019fea: 9b02 ldr r3, [sp, #8]
|
|
8019fec: 429f cmp r7, r3
|
|
8019fee: d00a beq.n 801a006 <_scanf_float+0x392>
|
|
8019ff0: 1bda subs r2, r3, r7
|
|
8019ff2: f204 136f addw r3, r4, #367 @ 0x16f
|
|
8019ff6: 429e cmp r6, r3
|
|
8019ff8: bf28 it cs
|
|
8019ffa: f504 76b7 addcs.w r6, r4, #366 @ 0x16e
|
|
8019ffe: 4921 ldr r1, [pc, #132] @ (801a084 <_scanf_float+0x410>)
|
|
801a000: 4630 mov r0, r6
|
|
801a002: f000 f919 bl 801a238 <siprintf>
|
|
801a006: 9901 ldr r1, [sp, #4]
|
|
801a008: 2200 movs r2, #0
|
|
801a00a: 4640 mov r0, r8
|
|
801a00c: f002 fc84 bl 801c918 <_strtod_r>
|
|
801a010: 9b03 ldr r3, [sp, #12]
|
|
801a012: 6821 ldr r1, [r4, #0]
|
|
801a014: 681b ldr r3, [r3, #0]
|
|
801a016: 0788 lsls r0, r1, #30
|
|
801a018: ec57 6b10 vmov r6, r7, d0
|
|
801a01c: f103 0204 add.w r2, r3, #4
|
|
801a020: d515 bpl.n 801a04e <_scanf_float+0x3da>
|
|
801a022: 9903 ldr r1, [sp, #12]
|
|
801a024: 600a str r2, [r1, #0]
|
|
801a026: 681b ldr r3, [r3, #0]
|
|
801a028: e9c3 6700 strd r6, r7, [r3]
|
|
801a02c: 68e3 ldr r3, [r4, #12]
|
|
801a02e: 3301 adds r3, #1
|
|
801a030: 60e3 str r3, [r4, #12]
|
|
801a032: e7d1 b.n 8019fd8 <_scanf_float+0x364>
|
|
801a034: 9b04 ldr r3, [sp, #16]
|
|
801a036: 2b00 cmp r3, #0
|
|
801a038: d0e5 beq.n 801a006 <_scanf_float+0x392>
|
|
801a03a: 9905 ldr r1, [sp, #20]
|
|
801a03c: 230a movs r3, #10
|
|
801a03e: 3101 adds r1, #1
|
|
801a040: 4640 mov r0, r8
|
|
801a042: f002 fce9 bl 801ca18 <_strtol_r>
|
|
801a046: 9b04 ldr r3, [sp, #16]
|
|
801a048: 9e05 ldr r6, [sp, #20]
|
|
801a04a: 1ac2 subs r2, r0, r3
|
|
801a04c: e7d1 b.n 8019ff2 <_scanf_float+0x37e>
|
|
801a04e: f011 0f04 tst.w r1, #4
|
|
801a052: 9903 ldr r1, [sp, #12]
|
|
801a054: 600a str r2, [r1, #0]
|
|
801a056: d1e6 bne.n 801a026 <_scanf_float+0x3b2>
|
|
801a058: 681d ldr r5, [r3, #0]
|
|
801a05a: 4632 mov r2, r6
|
|
801a05c: 463b mov r3, r7
|
|
801a05e: 4630 mov r0, r6
|
|
801a060: 4639 mov r1, r7
|
|
801a062: f7e6 fd3b bl 8000adc <__aeabi_dcmpun>
|
|
801a066: b128 cbz r0, 801a074 <_scanf_float+0x400>
|
|
801a068: 4807 ldr r0, [pc, #28] @ (801a088 <_scanf_float+0x414>)
|
|
801a06a: f000 fa37 bl 801a4dc <nanf>
|
|
801a06e: ed85 0a00 vstr s0, [r5]
|
|
801a072: e7db b.n 801a02c <_scanf_float+0x3b8>
|
|
801a074: 4630 mov r0, r6
|
|
801a076: 4639 mov r1, r7
|
|
801a078: f7e6 fd8e bl 8000b98 <__aeabi_d2f>
|
|
801a07c: 6028 str r0, [r5, #0]
|
|
801a07e: e7d5 b.n 801a02c <_scanf_float+0x3b8>
|
|
801a080: 2700 movs r7, #0
|
|
801a082: e62f b.n 8019ce4 <_scanf_float+0x70>
|
|
801a084: 0801e644 .word 0x0801e644
|
|
801a088: 0801e785 .word 0x0801e785
|
|
|
|
0801a08c <std>:
|
|
801a08c: 2300 movs r3, #0
|
|
801a08e: b510 push {r4, lr}
|
|
801a090: 4604 mov r4, r0
|
|
801a092: e9c0 3300 strd r3, r3, [r0]
|
|
801a096: e9c0 3304 strd r3, r3, [r0, #16]
|
|
801a09a: 6083 str r3, [r0, #8]
|
|
801a09c: 8181 strh r1, [r0, #12]
|
|
801a09e: 6643 str r3, [r0, #100] @ 0x64
|
|
801a0a0: 81c2 strh r2, [r0, #14]
|
|
801a0a2: 6183 str r3, [r0, #24]
|
|
801a0a4: 4619 mov r1, r3
|
|
801a0a6: 2208 movs r2, #8
|
|
801a0a8: 305c adds r0, #92 @ 0x5c
|
|
801a0aa: f000 f92b bl 801a304 <memset>
|
|
801a0ae: 4b0d ldr r3, [pc, #52] @ (801a0e4 <std+0x58>)
|
|
801a0b0: 6263 str r3, [r4, #36] @ 0x24
|
|
801a0b2: 4b0d ldr r3, [pc, #52] @ (801a0e8 <std+0x5c>)
|
|
801a0b4: 62a3 str r3, [r4, #40] @ 0x28
|
|
801a0b6: 4b0d ldr r3, [pc, #52] @ (801a0ec <std+0x60>)
|
|
801a0b8: 62e3 str r3, [r4, #44] @ 0x2c
|
|
801a0ba: 4b0d ldr r3, [pc, #52] @ (801a0f0 <std+0x64>)
|
|
801a0bc: 6323 str r3, [r4, #48] @ 0x30
|
|
801a0be: 4b0d ldr r3, [pc, #52] @ (801a0f4 <std+0x68>)
|
|
801a0c0: 6224 str r4, [r4, #32]
|
|
801a0c2: 429c cmp r4, r3
|
|
801a0c4: d006 beq.n 801a0d4 <std+0x48>
|
|
801a0c6: f103 0268 add.w r2, r3, #104 @ 0x68
|
|
801a0ca: 4294 cmp r4, r2
|
|
801a0cc: d002 beq.n 801a0d4 <std+0x48>
|
|
801a0ce: 33d0 adds r3, #208 @ 0xd0
|
|
801a0d0: 429c cmp r4, r3
|
|
801a0d2: d105 bne.n 801a0e0 <std+0x54>
|
|
801a0d4: f104 0058 add.w r0, r4, #88 @ 0x58
|
|
801a0d8: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
801a0dc: f000 b9ec b.w 801a4b8 <__retarget_lock_init_recursive>
|
|
801a0e0: bd10 pop {r4, pc}
|
|
801a0e2: bf00 nop
|
|
801a0e4: 0801a27d .word 0x0801a27d
|
|
801a0e8: 0801a29f .word 0x0801a29f
|
|
801a0ec: 0801a2d7 .word 0x0801a2d7
|
|
801a0f0: 0801a2fd .word 0x0801a2fd
|
|
801a0f4: 20013b9c .word 0x20013b9c
|
|
|
|
0801a0f8 <stdio_exit_handler>:
|
|
801a0f8: 4a02 ldr r2, [pc, #8] @ (801a104 <stdio_exit_handler+0xc>)
|
|
801a0fa: 4903 ldr r1, [pc, #12] @ (801a108 <stdio_exit_handler+0x10>)
|
|
801a0fc: 4803 ldr r0, [pc, #12] @ (801a10c <stdio_exit_handler+0x14>)
|
|
801a0fe: f000 b86b b.w 801a1d8 <_fwalk_sglue>
|
|
801a102: bf00 nop
|
|
801a104: 20000110 .word 0x20000110
|
|
801a108: 0801d04d .word 0x0801d04d
|
|
801a10c: 20000120 .word 0x20000120
|
|
|
|
0801a110 <cleanup_stdio>:
|
|
801a110: 6841 ldr r1, [r0, #4]
|
|
801a112: 4b0c ldr r3, [pc, #48] @ (801a144 <cleanup_stdio+0x34>)
|
|
801a114: 4299 cmp r1, r3
|
|
801a116: b510 push {r4, lr}
|
|
801a118: 4604 mov r4, r0
|
|
801a11a: d001 beq.n 801a120 <cleanup_stdio+0x10>
|
|
801a11c: f002 ff96 bl 801d04c <_fflush_r>
|
|
801a120: 68a1 ldr r1, [r4, #8]
|
|
801a122: 4b09 ldr r3, [pc, #36] @ (801a148 <cleanup_stdio+0x38>)
|
|
801a124: 4299 cmp r1, r3
|
|
801a126: d002 beq.n 801a12e <cleanup_stdio+0x1e>
|
|
801a128: 4620 mov r0, r4
|
|
801a12a: f002 ff8f bl 801d04c <_fflush_r>
|
|
801a12e: 68e1 ldr r1, [r4, #12]
|
|
801a130: 4b06 ldr r3, [pc, #24] @ (801a14c <cleanup_stdio+0x3c>)
|
|
801a132: 4299 cmp r1, r3
|
|
801a134: d004 beq.n 801a140 <cleanup_stdio+0x30>
|
|
801a136: 4620 mov r0, r4
|
|
801a138: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
801a13c: f002 bf86 b.w 801d04c <_fflush_r>
|
|
801a140: bd10 pop {r4, pc}
|
|
801a142: bf00 nop
|
|
801a144: 20013b9c .word 0x20013b9c
|
|
801a148: 20013c04 .word 0x20013c04
|
|
801a14c: 20013c6c .word 0x20013c6c
|
|
|
|
0801a150 <global_stdio_init.part.0>:
|
|
801a150: 4b0c ldr r3, [pc, #48] @ (801a184 <global_stdio_init.part.0+0x34>)
|
|
801a152: 4a0d ldr r2, [pc, #52] @ (801a188 <global_stdio_init.part.0+0x38>)
|
|
801a154: 480d ldr r0, [pc, #52] @ (801a18c <global_stdio_init.part.0+0x3c>)
|
|
801a156: b510 push {r4, lr}
|
|
801a158: 2104 movs r1, #4
|
|
801a15a: 601a str r2, [r3, #0]
|
|
801a15c: 2200 movs r2, #0
|
|
801a15e: f7ff ff95 bl 801a08c <std>
|
|
801a162: 4b0a ldr r3, [pc, #40] @ (801a18c <global_stdio_init.part.0+0x3c>)
|
|
801a164: 2201 movs r2, #1
|
|
801a166: 461c mov r4, r3
|
|
801a168: 2109 movs r1, #9
|
|
801a16a: f103 0068 add.w r0, r3, #104 @ 0x68
|
|
801a16e: f7ff ff8d bl 801a08c <std>
|
|
801a172: f104 00d0 add.w r0, r4, #208 @ 0xd0
|
|
801a176: 2202 movs r2, #2
|
|
801a178: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
801a17c: 2112 movs r1, #18
|
|
801a17e: f7ff bf85 b.w 801a08c <std>
|
|
801a182: bf00 nop
|
|
801a184: 20013cd4 .word 0x20013cd4
|
|
801a188: 0801a0f9 .word 0x0801a0f9
|
|
801a18c: 20013b9c .word 0x20013b9c
|
|
|
|
0801a190 <__sfp_lock_acquire>:
|
|
801a190: 4801 ldr r0, [pc, #4] @ (801a198 <__sfp_lock_acquire+0x8>)
|
|
801a192: f000 b992 b.w 801a4ba <__retarget_lock_acquire_recursive>
|
|
801a196: bf00 nop
|
|
801a198: 20013cdd .word 0x20013cdd
|
|
|
|
0801a19c <__sfp_lock_release>:
|
|
801a19c: 4801 ldr r0, [pc, #4] @ (801a1a4 <__sfp_lock_release+0x8>)
|
|
801a19e: f000 b98d b.w 801a4bc <__retarget_lock_release_recursive>
|
|
801a1a2: bf00 nop
|
|
801a1a4: 20013cdd .word 0x20013cdd
|
|
|
|
0801a1a8 <__sinit>:
|
|
801a1a8: b510 push {r4, lr}
|
|
801a1aa: 4604 mov r4, r0
|
|
801a1ac: f7ff fff0 bl 801a190 <__sfp_lock_acquire>
|
|
801a1b0: 6a23 ldr r3, [r4, #32]
|
|
801a1b2: b11b cbz r3, 801a1bc <__sinit+0x14>
|
|
801a1b4: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
801a1b8: f7ff bff0 b.w 801a19c <__sfp_lock_release>
|
|
801a1bc: 4b04 ldr r3, [pc, #16] @ (801a1d0 <__sinit+0x28>)
|
|
801a1be: 6223 str r3, [r4, #32]
|
|
801a1c0: 4b04 ldr r3, [pc, #16] @ (801a1d4 <__sinit+0x2c>)
|
|
801a1c2: 681b ldr r3, [r3, #0]
|
|
801a1c4: 2b00 cmp r3, #0
|
|
801a1c6: d1f5 bne.n 801a1b4 <__sinit+0xc>
|
|
801a1c8: f7ff ffc2 bl 801a150 <global_stdio_init.part.0>
|
|
801a1cc: e7f2 b.n 801a1b4 <__sinit+0xc>
|
|
801a1ce: bf00 nop
|
|
801a1d0: 0801a111 .word 0x0801a111
|
|
801a1d4: 20013cd4 .word 0x20013cd4
|
|
|
|
0801a1d8 <_fwalk_sglue>:
|
|
801a1d8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
801a1dc: 4607 mov r7, r0
|
|
801a1de: 4688 mov r8, r1
|
|
801a1e0: 4614 mov r4, r2
|
|
801a1e2: 2600 movs r6, #0
|
|
801a1e4: e9d4 9501 ldrd r9, r5, [r4, #4]
|
|
801a1e8: f1b9 0901 subs.w r9, r9, #1
|
|
801a1ec: d505 bpl.n 801a1fa <_fwalk_sglue+0x22>
|
|
801a1ee: 6824 ldr r4, [r4, #0]
|
|
801a1f0: 2c00 cmp r4, #0
|
|
801a1f2: d1f7 bne.n 801a1e4 <_fwalk_sglue+0xc>
|
|
801a1f4: 4630 mov r0, r6
|
|
801a1f6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
801a1fa: 89ab ldrh r3, [r5, #12]
|
|
801a1fc: 2b01 cmp r3, #1
|
|
801a1fe: d907 bls.n 801a210 <_fwalk_sglue+0x38>
|
|
801a200: f9b5 300e ldrsh.w r3, [r5, #14]
|
|
801a204: 3301 adds r3, #1
|
|
801a206: d003 beq.n 801a210 <_fwalk_sglue+0x38>
|
|
801a208: 4629 mov r1, r5
|
|
801a20a: 4638 mov r0, r7
|
|
801a20c: 47c0 blx r8
|
|
801a20e: 4306 orrs r6, r0
|
|
801a210: 3568 adds r5, #104 @ 0x68
|
|
801a212: e7e9 b.n 801a1e8 <_fwalk_sglue+0x10>
|
|
|
|
0801a214 <iprintf>:
|
|
801a214: b40f push {r0, r1, r2, r3}
|
|
801a216: b507 push {r0, r1, r2, lr}
|
|
801a218: 4906 ldr r1, [pc, #24] @ (801a234 <iprintf+0x20>)
|
|
801a21a: ab04 add r3, sp, #16
|
|
801a21c: 6808 ldr r0, [r1, #0]
|
|
801a21e: f853 2b04 ldr.w r2, [r3], #4
|
|
801a222: 6881 ldr r1, [r0, #8]
|
|
801a224: 9301 str r3, [sp, #4]
|
|
801a226: f002 fd7b bl 801cd20 <_vfiprintf_r>
|
|
801a22a: b003 add sp, #12
|
|
801a22c: f85d eb04 ldr.w lr, [sp], #4
|
|
801a230: b004 add sp, #16
|
|
801a232: 4770 bx lr
|
|
801a234: 2000011c .word 0x2000011c
|
|
|
|
0801a238 <siprintf>:
|
|
801a238: b40e push {r1, r2, r3}
|
|
801a23a: b510 push {r4, lr}
|
|
801a23c: b09d sub sp, #116 @ 0x74
|
|
801a23e: ab1f add r3, sp, #124 @ 0x7c
|
|
801a240: 9002 str r0, [sp, #8]
|
|
801a242: 9006 str r0, [sp, #24]
|
|
801a244: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
|
|
801a248: 480a ldr r0, [pc, #40] @ (801a274 <siprintf+0x3c>)
|
|
801a24a: 9107 str r1, [sp, #28]
|
|
801a24c: 9104 str r1, [sp, #16]
|
|
801a24e: 490a ldr r1, [pc, #40] @ (801a278 <siprintf+0x40>)
|
|
801a250: f853 2b04 ldr.w r2, [r3], #4
|
|
801a254: 9105 str r1, [sp, #20]
|
|
801a256: 2400 movs r4, #0
|
|
801a258: a902 add r1, sp, #8
|
|
801a25a: 6800 ldr r0, [r0, #0]
|
|
801a25c: 9301 str r3, [sp, #4]
|
|
801a25e: 941b str r4, [sp, #108] @ 0x6c
|
|
801a260: f002 fc3c bl 801cadc <_svfiprintf_r>
|
|
801a264: 9b02 ldr r3, [sp, #8]
|
|
801a266: 701c strb r4, [r3, #0]
|
|
801a268: b01d add sp, #116 @ 0x74
|
|
801a26a: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
801a26e: b003 add sp, #12
|
|
801a270: 4770 bx lr
|
|
801a272: bf00 nop
|
|
801a274: 2000011c .word 0x2000011c
|
|
801a278: ffff0208 .word 0xffff0208
|
|
|
|
0801a27c <__sread>:
|
|
801a27c: b510 push {r4, lr}
|
|
801a27e: 460c mov r4, r1
|
|
801a280: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801a284: f000 f8ca bl 801a41c <_read_r>
|
|
801a288: 2800 cmp r0, #0
|
|
801a28a: bfab itete ge
|
|
801a28c: 6d63 ldrge r3, [r4, #84] @ 0x54
|
|
801a28e: 89a3 ldrhlt r3, [r4, #12]
|
|
801a290: 181b addge r3, r3, r0
|
|
801a292: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
|
|
801a296: bfac ite ge
|
|
801a298: 6563 strge r3, [r4, #84] @ 0x54
|
|
801a29a: 81a3 strhlt r3, [r4, #12]
|
|
801a29c: bd10 pop {r4, pc}
|
|
|
|
0801a29e <__swrite>:
|
|
801a29e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
801a2a2: 461f mov r7, r3
|
|
801a2a4: 898b ldrh r3, [r1, #12]
|
|
801a2a6: 05db lsls r3, r3, #23
|
|
801a2a8: 4605 mov r5, r0
|
|
801a2aa: 460c mov r4, r1
|
|
801a2ac: 4616 mov r6, r2
|
|
801a2ae: d505 bpl.n 801a2bc <__swrite+0x1e>
|
|
801a2b0: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801a2b4: 2302 movs r3, #2
|
|
801a2b6: 2200 movs r2, #0
|
|
801a2b8: f000 f89e bl 801a3f8 <_lseek_r>
|
|
801a2bc: 89a3 ldrh r3, [r4, #12]
|
|
801a2be: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
801a2c2: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
801a2c6: 81a3 strh r3, [r4, #12]
|
|
801a2c8: 4632 mov r2, r6
|
|
801a2ca: 463b mov r3, r7
|
|
801a2cc: 4628 mov r0, r5
|
|
801a2ce: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
801a2d2: f000 b8b5 b.w 801a440 <_write_r>
|
|
|
|
0801a2d6 <__sseek>:
|
|
801a2d6: b510 push {r4, lr}
|
|
801a2d8: 460c mov r4, r1
|
|
801a2da: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801a2de: f000 f88b bl 801a3f8 <_lseek_r>
|
|
801a2e2: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801a2e6: 1c42 adds r2, r0, #1
|
|
801a2e8: bf0b itete eq
|
|
801a2ea: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
|
|
801a2ee: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
|
|
801a2f2: 81a3 strheq r3, [r4, #12]
|
|
801a2f4: 81a3 strhne r3, [r4, #12]
|
|
801a2f6: bf18 it ne
|
|
801a2f8: 6560 strne r0, [r4, #84] @ 0x54
|
|
801a2fa: bd10 pop {r4, pc}
|
|
|
|
0801a2fc <__sclose>:
|
|
801a2fc: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801a300: f000 b80c b.w 801a31c <_close_r>
|
|
|
|
0801a304 <memset>:
|
|
801a304: 4402 add r2, r0
|
|
801a306: 4603 mov r3, r0
|
|
801a308: 4293 cmp r3, r2
|
|
801a30a: d100 bne.n 801a30e <memset+0xa>
|
|
801a30c: 4770 bx lr
|
|
801a30e: f803 1b01 strb.w r1, [r3], #1
|
|
801a312: e7f9 b.n 801a308 <memset+0x4>
|
|
|
|
0801a314 <_localeconv_r>:
|
|
801a314: 4800 ldr r0, [pc, #0] @ (801a318 <_localeconv_r+0x4>)
|
|
801a316: 4770 bx lr
|
|
801a318: 2000025c .word 0x2000025c
|
|
|
|
0801a31c <_close_r>:
|
|
801a31c: b538 push {r3, r4, r5, lr}
|
|
801a31e: 4d06 ldr r5, [pc, #24] @ (801a338 <_close_r+0x1c>)
|
|
801a320: 2300 movs r3, #0
|
|
801a322: 4604 mov r4, r0
|
|
801a324: 4608 mov r0, r1
|
|
801a326: 602b str r3, [r5, #0]
|
|
801a328: f7ec f9f6 bl 8006718 <_close>
|
|
801a32c: 1c43 adds r3, r0, #1
|
|
801a32e: d102 bne.n 801a336 <_close_r+0x1a>
|
|
801a330: 682b ldr r3, [r5, #0]
|
|
801a332: b103 cbz r3, 801a336 <_close_r+0x1a>
|
|
801a334: 6023 str r3, [r4, #0]
|
|
801a336: bd38 pop {r3, r4, r5, pc}
|
|
801a338: 20013cd8 .word 0x20013cd8
|
|
|
|
0801a33c <_reclaim_reent>:
|
|
801a33c: 4b2d ldr r3, [pc, #180] @ (801a3f4 <_reclaim_reent+0xb8>)
|
|
801a33e: 681b ldr r3, [r3, #0]
|
|
801a340: 4283 cmp r3, r0
|
|
801a342: b570 push {r4, r5, r6, lr}
|
|
801a344: 4604 mov r4, r0
|
|
801a346: d053 beq.n 801a3f0 <_reclaim_reent+0xb4>
|
|
801a348: 69c3 ldr r3, [r0, #28]
|
|
801a34a: b31b cbz r3, 801a394 <_reclaim_reent+0x58>
|
|
801a34c: 68db ldr r3, [r3, #12]
|
|
801a34e: b163 cbz r3, 801a36a <_reclaim_reent+0x2e>
|
|
801a350: 2500 movs r5, #0
|
|
801a352: 69e3 ldr r3, [r4, #28]
|
|
801a354: 68db ldr r3, [r3, #12]
|
|
801a356: 5959 ldr r1, [r3, r5]
|
|
801a358: b9b1 cbnz r1, 801a388 <_reclaim_reent+0x4c>
|
|
801a35a: 3504 adds r5, #4
|
|
801a35c: 2d80 cmp r5, #128 @ 0x80
|
|
801a35e: d1f8 bne.n 801a352 <_reclaim_reent+0x16>
|
|
801a360: 69e3 ldr r3, [r4, #28]
|
|
801a362: 4620 mov r0, r4
|
|
801a364: 68d9 ldr r1, [r3, #12]
|
|
801a366: f000 ff23 bl 801b1b0 <_free_r>
|
|
801a36a: 69e3 ldr r3, [r4, #28]
|
|
801a36c: 6819 ldr r1, [r3, #0]
|
|
801a36e: b111 cbz r1, 801a376 <_reclaim_reent+0x3a>
|
|
801a370: 4620 mov r0, r4
|
|
801a372: f000 ff1d bl 801b1b0 <_free_r>
|
|
801a376: 69e3 ldr r3, [r4, #28]
|
|
801a378: 689d ldr r5, [r3, #8]
|
|
801a37a: b15d cbz r5, 801a394 <_reclaim_reent+0x58>
|
|
801a37c: 4629 mov r1, r5
|
|
801a37e: 4620 mov r0, r4
|
|
801a380: 682d ldr r5, [r5, #0]
|
|
801a382: f000 ff15 bl 801b1b0 <_free_r>
|
|
801a386: e7f8 b.n 801a37a <_reclaim_reent+0x3e>
|
|
801a388: 680e ldr r6, [r1, #0]
|
|
801a38a: 4620 mov r0, r4
|
|
801a38c: f000 ff10 bl 801b1b0 <_free_r>
|
|
801a390: 4631 mov r1, r6
|
|
801a392: e7e1 b.n 801a358 <_reclaim_reent+0x1c>
|
|
801a394: 6961 ldr r1, [r4, #20]
|
|
801a396: b111 cbz r1, 801a39e <_reclaim_reent+0x62>
|
|
801a398: 4620 mov r0, r4
|
|
801a39a: f000 ff09 bl 801b1b0 <_free_r>
|
|
801a39e: 69e1 ldr r1, [r4, #28]
|
|
801a3a0: b111 cbz r1, 801a3a8 <_reclaim_reent+0x6c>
|
|
801a3a2: 4620 mov r0, r4
|
|
801a3a4: f000 ff04 bl 801b1b0 <_free_r>
|
|
801a3a8: 6b21 ldr r1, [r4, #48] @ 0x30
|
|
801a3aa: b111 cbz r1, 801a3b2 <_reclaim_reent+0x76>
|
|
801a3ac: 4620 mov r0, r4
|
|
801a3ae: f000 feff bl 801b1b0 <_free_r>
|
|
801a3b2: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
801a3b4: b111 cbz r1, 801a3bc <_reclaim_reent+0x80>
|
|
801a3b6: 4620 mov r0, r4
|
|
801a3b8: f000 fefa bl 801b1b0 <_free_r>
|
|
801a3bc: 6ba1 ldr r1, [r4, #56] @ 0x38
|
|
801a3be: b111 cbz r1, 801a3c6 <_reclaim_reent+0x8a>
|
|
801a3c0: 4620 mov r0, r4
|
|
801a3c2: f000 fef5 bl 801b1b0 <_free_r>
|
|
801a3c6: 6ca1 ldr r1, [r4, #72] @ 0x48
|
|
801a3c8: b111 cbz r1, 801a3d0 <_reclaim_reent+0x94>
|
|
801a3ca: 4620 mov r0, r4
|
|
801a3cc: f000 fef0 bl 801b1b0 <_free_r>
|
|
801a3d0: 6c61 ldr r1, [r4, #68] @ 0x44
|
|
801a3d2: b111 cbz r1, 801a3da <_reclaim_reent+0x9e>
|
|
801a3d4: 4620 mov r0, r4
|
|
801a3d6: f000 feeb bl 801b1b0 <_free_r>
|
|
801a3da: 6ae1 ldr r1, [r4, #44] @ 0x2c
|
|
801a3dc: b111 cbz r1, 801a3e4 <_reclaim_reent+0xa8>
|
|
801a3de: 4620 mov r0, r4
|
|
801a3e0: f000 fee6 bl 801b1b0 <_free_r>
|
|
801a3e4: 6a23 ldr r3, [r4, #32]
|
|
801a3e6: b11b cbz r3, 801a3f0 <_reclaim_reent+0xb4>
|
|
801a3e8: 4620 mov r0, r4
|
|
801a3ea: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
|
|
801a3ee: 4718 bx r3
|
|
801a3f0: bd70 pop {r4, r5, r6, pc}
|
|
801a3f2: bf00 nop
|
|
801a3f4: 2000011c .word 0x2000011c
|
|
|
|
0801a3f8 <_lseek_r>:
|
|
801a3f8: b538 push {r3, r4, r5, lr}
|
|
801a3fa: 4d07 ldr r5, [pc, #28] @ (801a418 <_lseek_r+0x20>)
|
|
801a3fc: 4604 mov r4, r0
|
|
801a3fe: 4608 mov r0, r1
|
|
801a400: 4611 mov r1, r2
|
|
801a402: 2200 movs r2, #0
|
|
801a404: 602a str r2, [r5, #0]
|
|
801a406: 461a mov r2, r3
|
|
801a408: f7ec f9ad bl 8006766 <_lseek>
|
|
801a40c: 1c43 adds r3, r0, #1
|
|
801a40e: d102 bne.n 801a416 <_lseek_r+0x1e>
|
|
801a410: 682b ldr r3, [r5, #0]
|
|
801a412: b103 cbz r3, 801a416 <_lseek_r+0x1e>
|
|
801a414: 6023 str r3, [r4, #0]
|
|
801a416: bd38 pop {r3, r4, r5, pc}
|
|
801a418: 20013cd8 .word 0x20013cd8
|
|
|
|
0801a41c <_read_r>:
|
|
801a41c: b538 push {r3, r4, r5, lr}
|
|
801a41e: 4d07 ldr r5, [pc, #28] @ (801a43c <_read_r+0x20>)
|
|
801a420: 4604 mov r4, r0
|
|
801a422: 4608 mov r0, r1
|
|
801a424: 4611 mov r1, r2
|
|
801a426: 2200 movs r2, #0
|
|
801a428: 602a str r2, [r5, #0]
|
|
801a42a: 461a mov r2, r3
|
|
801a42c: f7ec f957 bl 80066de <_read>
|
|
801a430: 1c43 adds r3, r0, #1
|
|
801a432: d102 bne.n 801a43a <_read_r+0x1e>
|
|
801a434: 682b ldr r3, [r5, #0]
|
|
801a436: b103 cbz r3, 801a43a <_read_r+0x1e>
|
|
801a438: 6023 str r3, [r4, #0]
|
|
801a43a: bd38 pop {r3, r4, r5, pc}
|
|
801a43c: 20013cd8 .word 0x20013cd8
|
|
|
|
0801a440 <_write_r>:
|
|
801a440: b538 push {r3, r4, r5, lr}
|
|
801a442: 4d07 ldr r5, [pc, #28] @ (801a460 <_write_r+0x20>)
|
|
801a444: 4604 mov r4, r0
|
|
801a446: 4608 mov r0, r1
|
|
801a448: 4611 mov r1, r2
|
|
801a44a: 2200 movs r2, #0
|
|
801a44c: 602a str r2, [r5, #0]
|
|
801a44e: 461a mov r2, r3
|
|
801a450: f7ea f9f0 bl 8004834 <_write>
|
|
801a454: 1c43 adds r3, r0, #1
|
|
801a456: d102 bne.n 801a45e <_write_r+0x1e>
|
|
801a458: 682b ldr r3, [r5, #0]
|
|
801a45a: b103 cbz r3, 801a45e <_write_r+0x1e>
|
|
801a45c: 6023 str r3, [r4, #0]
|
|
801a45e: bd38 pop {r3, r4, r5, pc}
|
|
801a460: 20013cd8 .word 0x20013cd8
|
|
|
|
0801a464 <__errno>:
|
|
801a464: 4b01 ldr r3, [pc, #4] @ (801a46c <__errno+0x8>)
|
|
801a466: 6818 ldr r0, [r3, #0]
|
|
801a468: 4770 bx lr
|
|
801a46a: bf00 nop
|
|
801a46c: 2000011c .word 0x2000011c
|
|
|
|
0801a470 <__libc_init_array>:
|
|
801a470: b570 push {r4, r5, r6, lr}
|
|
801a472: 4b0d ldr r3, [pc, #52] @ (801a4a8 <__libc_init_array+0x38>)
|
|
801a474: 4d0d ldr r5, [pc, #52] @ (801a4ac <__libc_init_array+0x3c>)
|
|
801a476: 1b5b subs r3, r3, r5
|
|
801a478: 109c asrs r4, r3, #2
|
|
801a47a: 2600 movs r6, #0
|
|
801a47c: 42a6 cmp r6, r4
|
|
801a47e: d109 bne.n 801a494 <__libc_init_array+0x24>
|
|
801a480: f003 fcae bl 801dde0 <_init>
|
|
801a484: 4d0a ldr r5, [pc, #40] @ (801a4b0 <__libc_init_array+0x40>)
|
|
801a486: 4b0b ldr r3, [pc, #44] @ (801a4b4 <__libc_init_array+0x44>)
|
|
801a488: 1b5b subs r3, r3, r5
|
|
801a48a: 109c asrs r4, r3, #2
|
|
801a48c: 2600 movs r6, #0
|
|
801a48e: 42a6 cmp r6, r4
|
|
801a490: d105 bne.n 801a49e <__libc_init_array+0x2e>
|
|
801a492: bd70 pop {r4, r5, r6, pc}
|
|
801a494: f855 3b04 ldr.w r3, [r5], #4
|
|
801a498: 4798 blx r3
|
|
801a49a: 3601 adds r6, #1
|
|
801a49c: e7ee b.n 801a47c <__libc_init_array+0xc>
|
|
801a49e: f855 3b04 ldr.w r3, [r5], #4
|
|
801a4a2: 4798 blx r3
|
|
801a4a4: 3601 adds r6, #1
|
|
801a4a6: e7f2 b.n 801a48e <__libc_init_array+0x1e>
|
|
801a4a8: 0801ea58 .word 0x0801ea58
|
|
801a4ac: 0801ea58 .word 0x0801ea58
|
|
801a4b0: 0801ea58 .word 0x0801ea58
|
|
801a4b4: 0801ea5c .word 0x0801ea5c
|
|
|
|
0801a4b8 <__retarget_lock_init_recursive>:
|
|
801a4b8: 4770 bx lr
|
|
|
|
0801a4ba <__retarget_lock_acquire_recursive>:
|
|
801a4ba: 4770 bx lr
|
|
|
|
0801a4bc <__retarget_lock_release_recursive>:
|
|
801a4bc: 4770 bx lr
|
|
|
|
0801a4be <memcpy>:
|
|
801a4be: 440a add r2, r1
|
|
801a4c0: 4291 cmp r1, r2
|
|
801a4c2: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
801a4c6: d100 bne.n 801a4ca <memcpy+0xc>
|
|
801a4c8: 4770 bx lr
|
|
801a4ca: b510 push {r4, lr}
|
|
801a4cc: f811 4b01 ldrb.w r4, [r1], #1
|
|
801a4d0: f803 4f01 strb.w r4, [r3, #1]!
|
|
801a4d4: 4291 cmp r1, r2
|
|
801a4d6: d1f9 bne.n 801a4cc <memcpy+0xe>
|
|
801a4d8: bd10 pop {r4, pc}
|
|
...
|
|
|
|
0801a4dc <nanf>:
|
|
801a4dc: ed9f 0a01 vldr s0, [pc, #4] @ 801a4e4 <nanf+0x8>
|
|
801a4e0: 4770 bx lr
|
|
801a4e2: bf00 nop
|
|
801a4e4: 7fc00000 .word 0x7fc00000
|
|
|
|
0801a4e8 <quorem>:
|
|
801a4e8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801a4ec: 6903 ldr r3, [r0, #16]
|
|
801a4ee: 690c ldr r4, [r1, #16]
|
|
801a4f0: 42a3 cmp r3, r4
|
|
801a4f2: 4607 mov r7, r0
|
|
801a4f4: db7e blt.n 801a5f4 <quorem+0x10c>
|
|
801a4f6: 3c01 subs r4, #1
|
|
801a4f8: f101 0814 add.w r8, r1, #20
|
|
801a4fc: 00a3 lsls r3, r4, #2
|
|
801a4fe: f100 0514 add.w r5, r0, #20
|
|
801a502: 9300 str r3, [sp, #0]
|
|
801a504: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
801a508: 9301 str r3, [sp, #4]
|
|
801a50a: f858 3024 ldr.w r3, [r8, r4, lsl #2]
|
|
801a50e: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
801a512: 3301 adds r3, #1
|
|
801a514: 429a cmp r2, r3
|
|
801a516: eb08 0984 add.w r9, r8, r4, lsl #2
|
|
801a51a: fbb2 f6f3 udiv r6, r2, r3
|
|
801a51e: d32e bcc.n 801a57e <quorem+0x96>
|
|
801a520: f04f 0a00 mov.w sl, #0
|
|
801a524: 46c4 mov ip, r8
|
|
801a526: 46ae mov lr, r5
|
|
801a528: 46d3 mov fp, sl
|
|
801a52a: f85c 3b04 ldr.w r3, [ip], #4
|
|
801a52e: b298 uxth r0, r3
|
|
801a530: fb06 a000 mla r0, r6, r0, sl
|
|
801a534: 0c02 lsrs r2, r0, #16
|
|
801a536: 0c1b lsrs r3, r3, #16
|
|
801a538: fb06 2303 mla r3, r6, r3, r2
|
|
801a53c: f8de 2000 ldr.w r2, [lr]
|
|
801a540: b280 uxth r0, r0
|
|
801a542: b292 uxth r2, r2
|
|
801a544: 1a12 subs r2, r2, r0
|
|
801a546: 445a add r2, fp
|
|
801a548: f8de 0000 ldr.w r0, [lr]
|
|
801a54c: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
801a550: b29b uxth r3, r3
|
|
801a552: ebc3 4322 rsb r3, r3, r2, asr #16
|
|
801a556: eb03 4310 add.w r3, r3, r0, lsr #16
|
|
801a55a: b292 uxth r2, r2
|
|
801a55c: ea42 4203 orr.w r2, r2, r3, lsl #16
|
|
801a560: 45e1 cmp r9, ip
|
|
801a562: f84e 2b04 str.w r2, [lr], #4
|
|
801a566: ea4f 4b23 mov.w fp, r3, asr #16
|
|
801a56a: d2de bcs.n 801a52a <quorem+0x42>
|
|
801a56c: 9b00 ldr r3, [sp, #0]
|
|
801a56e: 58eb ldr r3, [r5, r3]
|
|
801a570: b92b cbnz r3, 801a57e <quorem+0x96>
|
|
801a572: 9b01 ldr r3, [sp, #4]
|
|
801a574: 3b04 subs r3, #4
|
|
801a576: 429d cmp r5, r3
|
|
801a578: 461a mov r2, r3
|
|
801a57a: d32f bcc.n 801a5dc <quorem+0xf4>
|
|
801a57c: 613c str r4, [r7, #16]
|
|
801a57e: 4638 mov r0, r7
|
|
801a580: f001 f9dc bl 801b93c <__mcmp>
|
|
801a584: 2800 cmp r0, #0
|
|
801a586: db25 blt.n 801a5d4 <quorem+0xec>
|
|
801a588: 4629 mov r1, r5
|
|
801a58a: 2000 movs r0, #0
|
|
801a58c: f858 2b04 ldr.w r2, [r8], #4
|
|
801a590: f8d1 c000 ldr.w ip, [r1]
|
|
801a594: fa1f fe82 uxth.w lr, r2
|
|
801a598: fa1f f38c uxth.w r3, ip
|
|
801a59c: eba3 030e sub.w r3, r3, lr
|
|
801a5a0: 4403 add r3, r0
|
|
801a5a2: 0c12 lsrs r2, r2, #16
|
|
801a5a4: ebc2 4223 rsb r2, r2, r3, asr #16
|
|
801a5a8: eb02 421c add.w r2, r2, ip, lsr #16
|
|
801a5ac: b29b uxth r3, r3
|
|
801a5ae: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
801a5b2: 45c1 cmp r9, r8
|
|
801a5b4: f841 3b04 str.w r3, [r1], #4
|
|
801a5b8: ea4f 4022 mov.w r0, r2, asr #16
|
|
801a5bc: d2e6 bcs.n 801a58c <quorem+0xa4>
|
|
801a5be: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
801a5c2: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
801a5c6: b922 cbnz r2, 801a5d2 <quorem+0xea>
|
|
801a5c8: 3b04 subs r3, #4
|
|
801a5ca: 429d cmp r5, r3
|
|
801a5cc: 461a mov r2, r3
|
|
801a5ce: d30b bcc.n 801a5e8 <quorem+0x100>
|
|
801a5d0: 613c str r4, [r7, #16]
|
|
801a5d2: 3601 adds r6, #1
|
|
801a5d4: 4630 mov r0, r6
|
|
801a5d6: b003 add sp, #12
|
|
801a5d8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801a5dc: 6812 ldr r2, [r2, #0]
|
|
801a5de: 3b04 subs r3, #4
|
|
801a5e0: 2a00 cmp r2, #0
|
|
801a5e2: d1cb bne.n 801a57c <quorem+0x94>
|
|
801a5e4: 3c01 subs r4, #1
|
|
801a5e6: e7c6 b.n 801a576 <quorem+0x8e>
|
|
801a5e8: 6812 ldr r2, [r2, #0]
|
|
801a5ea: 3b04 subs r3, #4
|
|
801a5ec: 2a00 cmp r2, #0
|
|
801a5ee: d1ef bne.n 801a5d0 <quorem+0xe8>
|
|
801a5f0: 3c01 subs r4, #1
|
|
801a5f2: e7ea b.n 801a5ca <quorem+0xe2>
|
|
801a5f4: 2000 movs r0, #0
|
|
801a5f6: e7ee b.n 801a5d6 <quorem+0xee>
|
|
|
|
0801a5f8 <_dtoa_r>:
|
|
801a5f8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801a5fc: b099 sub sp, #100 @ 0x64
|
|
801a5fe: ed8d 0b0e vstr d0, [sp, #56] @ 0x38
|
|
801a602: 920c str r2, [sp, #48] @ 0x30
|
|
801a604: 69c2 ldr r2, [r0, #28]
|
|
801a606: 9c22 ldr r4, [sp, #136] @ 0x88
|
|
801a608: 910a str r1, [sp, #40] @ 0x28
|
|
801a60a: ec57 6b10 vmov r6, r7, d0
|
|
801a60e: 4681 mov r9, r0
|
|
801a610: 9313 str r3, [sp, #76] @ 0x4c
|
|
801a612: b982 cbnz r2, 801a636 <_dtoa_r+0x3e>
|
|
801a614: 2010 movs r0, #16
|
|
801a616: f000 fe15 bl 801b244 <malloc>
|
|
801a61a: 4602 mov r2, r0
|
|
801a61c: f8c9 001c str.w r0, [r9, #28]
|
|
801a620: b920 cbnz r0, 801a62c <_dtoa_r+0x34>
|
|
801a622: 4bab ldr r3, [pc, #684] @ (801a8d0 <_dtoa_r+0x2d8>)
|
|
801a624: 21ef movs r1, #239 @ 0xef
|
|
801a626: 48ab ldr r0, [pc, #684] @ (801a8d4 <_dtoa_r+0x2dc>)
|
|
801a628: f002 fe0e bl 801d248 <__assert_func>
|
|
801a62c: 2300 movs r3, #0
|
|
801a62e: e9c0 3301 strd r3, r3, [r0, #4]
|
|
801a632: 6003 str r3, [r0, #0]
|
|
801a634: 60c3 str r3, [r0, #12]
|
|
801a636: 6811 ldr r1, [r2, #0]
|
|
801a638: b159 cbz r1, 801a652 <_dtoa_r+0x5a>
|
|
801a63a: 6852 ldr r2, [r2, #4]
|
|
801a63c: 604a str r2, [r1, #4]
|
|
801a63e: 2301 movs r3, #1
|
|
801a640: 4093 lsls r3, r2
|
|
801a642: 608b str r3, [r1, #8]
|
|
801a644: 4648 mov r0, r9
|
|
801a646: f000 fef1 bl 801b42c <_Bfree>
|
|
801a64a: f8d9 301c ldr.w r3, [r9, #28]
|
|
801a64e: 2200 movs r2, #0
|
|
801a650: 601a str r2, [r3, #0]
|
|
801a652: f1b7 0800 subs.w r8, r7, #0
|
|
801a656: bfb5 itete lt
|
|
801a658: 2301 movlt r3, #1
|
|
801a65a: 2300 movge r3, #0
|
|
801a65c: 6023 strlt r3, [r4, #0]
|
|
801a65e: 6023 strge r3, [r4, #0]
|
|
801a660: 4b9d ldr r3, [pc, #628] @ (801a8d8 <_dtoa_r+0x2e0>)
|
|
801a662: bfbc itt lt
|
|
801a664: f028 4800 biclt.w r8, r8, #2147483648 @ 0x80000000
|
|
801a668: f8cd 803c strlt.w r8, [sp, #60] @ 0x3c
|
|
801a66c: ea33 0308 bics.w r3, r3, r8
|
|
801a670: d11a bne.n 801a6a8 <_dtoa_r+0xb0>
|
|
801a672: 9a13 ldr r2, [sp, #76] @ 0x4c
|
|
801a674: f3c8 0813 ubfx r8, r8, #0, #20
|
|
801a678: f242 730f movw r3, #9999 @ 0x270f
|
|
801a67c: ea58 0806 orrs.w r8, r8, r6
|
|
801a680: 6013 str r3, [r2, #0]
|
|
801a682: f000 8568 beq.w 801b156 <_dtoa_r+0xb5e>
|
|
801a686: 9b23 ldr r3, [sp, #140] @ 0x8c
|
|
801a688: b953 cbnz r3, 801a6a0 <_dtoa_r+0xa8>
|
|
801a68a: 4b94 ldr r3, [pc, #592] @ (801a8dc <_dtoa_r+0x2e4>)
|
|
801a68c: e021 b.n 801a6d2 <_dtoa_r+0xda>
|
|
801a68e: 4b94 ldr r3, [pc, #592] @ (801a8e0 <_dtoa_r+0x2e8>)
|
|
801a690: 9300 str r3, [sp, #0]
|
|
801a692: 3308 adds r3, #8
|
|
801a694: 9a23 ldr r2, [sp, #140] @ 0x8c
|
|
801a696: 6013 str r3, [r2, #0]
|
|
801a698: 9800 ldr r0, [sp, #0]
|
|
801a69a: b019 add sp, #100 @ 0x64
|
|
801a69c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801a6a0: 4b8e ldr r3, [pc, #568] @ (801a8dc <_dtoa_r+0x2e4>)
|
|
801a6a2: 9300 str r3, [sp, #0]
|
|
801a6a4: 3303 adds r3, #3
|
|
801a6a6: e7f5 b.n 801a694 <_dtoa_r+0x9c>
|
|
801a6a8: ed9d 7b0e vldr d7, [sp, #56] @ 0x38
|
|
801a6ac: 2200 movs r2, #0
|
|
801a6ae: ec51 0b17 vmov r0, r1, d7
|
|
801a6b2: 2300 movs r3, #0
|
|
801a6b4: ed8d 7b06 vstr d7, [sp, #24]
|
|
801a6b8: f7e6 f9de bl 8000a78 <__aeabi_dcmpeq>
|
|
801a6bc: 4682 mov sl, r0
|
|
801a6be: b150 cbz r0, 801a6d6 <_dtoa_r+0xde>
|
|
801a6c0: 9a13 ldr r2, [sp, #76] @ 0x4c
|
|
801a6c2: 2301 movs r3, #1
|
|
801a6c4: 6013 str r3, [r2, #0]
|
|
801a6c6: 9b23 ldr r3, [sp, #140] @ 0x8c
|
|
801a6c8: b113 cbz r3, 801a6d0 <_dtoa_r+0xd8>
|
|
801a6ca: 9a23 ldr r2, [sp, #140] @ 0x8c
|
|
801a6cc: 4b85 ldr r3, [pc, #532] @ (801a8e4 <_dtoa_r+0x2ec>)
|
|
801a6ce: 6013 str r3, [r2, #0]
|
|
801a6d0: 4b85 ldr r3, [pc, #532] @ (801a8e8 <_dtoa_r+0x2f0>)
|
|
801a6d2: 9300 str r3, [sp, #0]
|
|
801a6d4: e7e0 b.n 801a698 <_dtoa_r+0xa0>
|
|
801a6d6: ed9d 0b06 vldr d0, [sp, #24]
|
|
801a6da: aa16 add r2, sp, #88 @ 0x58
|
|
801a6dc: a917 add r1, sp, #92 @ 0x5c
|
|
801a6de: 4648 mov r0, r9
|
|
801a6e0: f001 fa50 bl 801bb84 <__d2b>
|
|
801a6e4: ea5f 5418 movs.w r4, r8, lsr #20
|
|
801a6e8: 9d16 ldr r5, [sp, #88] @ 0x58
|
|
801a6ea: 9001 str r0, [sp, #4]
|
|
801a6ec: d079 beq.n 801a7e2 <_dtoa_r+0x1ea>
|
|
801a6ee: 9b07 ldr r3, [sp, #28]
|
|
801a6f0: f8cd a050 str.w sl, [sp, #80] @ 0x50
|
|
801a6f4: f3c3 0313 ubfx r3, r3, #0, #20
|
|
801a6f8: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
801a6fc: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000
|
|
801a700: f443 1340 orr.w r3, r3, #3145728 @ 0x300000
|
|
801a704: f2a4 34ff subw r4, r4, #1023 @ 0x3ff
|
|
801a708: 4619 mov r1, r3
|
|
801a70a: 2200 movs r2, #0
|
|
801a70c: 4b77 ldr r3, [pc, #476] @ (801a8ec <_dtoa_r+0x2f4>)
|
|
801a70e: f7e5 fd93 bl 8000238 <__aeabi_dsub>
|
|
801a712: a369 add r3, pc, #420 @ (adr r3, 801a8b8 <_dtoa_r+0x2c0>)
|
|
801a714: e9d3 2300 ldrd r2, r3, [r3]
|
|
801a718: f7e5 ff46 bl 80005a8 <__aeabi_dmul>
|
|
801a71c: a368 add r3, pc, #416 @ (adr r3, 801a8c0 <_dtoa_r+0x2c8>)
|
|
801a71e: e9d3 2300 ldrd r2, r3, [r3]
|
|
801a722: f7e5 fd8b bl 800023c <__adddf3>
|
|
801a726: 4606 mov r6, r0
|
|
801a728: 4620 mov r0, r4
|
|
801a72a: 460f mov r7, r1
|
|
801a72c: f7e5 fed2 bl 80004d4 <__aeabi_i2d>
|
|
801a730: a365 add r3, pc, #404 @ (adr r3, 801a8c8 <_dtoa_r+0x2d0>)
|
|
801a732: e9d3 2300 ldrd r2, r3, [r3]
|
|
801a736: f7e5 ff37 bl 80005a8 <__aeabi_dmul>
|
|
801a73a: 4602 mov r2, r0
|
|
801a73c: 460b mov r3, r1
|
|
801a73e: 4630 mov r0, r6
|
|
801a740: 4639 mov r1, r7
|
|
801a742: f7e5 fd7b bl 800023c <__adddf3>
|
|
801a746: 4606 mov r6, r0
|
|
801a748: 460f mov r7, r1
|
|
801a74a: f7e6 f9dd bl 8000b08 <__aeabi_d2iz>
|
|
801a74e: 2200 movs r2, #0
|
|
801a750: 4680 mov r8, r0
|
|
801a752: 2300 movs r3, #0
|
|
801a754: 4630 mov r0, r6
|
|
801a756: 4639 mov r1, r7
|
|
801a758: f7e6 f998 bl 8000a8c <__aeabi_dcmplt>
|
|
801a75c: b148 cbz r0, 801a772 <_dtoa_r+0x17a>
|
|
801a75e: 4640 mov r0, r8
|
|
801a760: f7e5 feb8 bl 80004d4 <__aeabi_i2d>
|
|
801a764: 4632 mov r2, r6
|
|
801a766: 463b mov r3, r7
|
|
801a768: f7e6 f986 bl 8000a78 <__aeabi_dcmpeq>
|
|
801a76c: b908 cbnz r0, 801a772 <_dtoa_r+0x17a>
|
|
801a76e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
|
|
801a772: f1b8 0f16 cmp.w r8, #22
|
|
801a776: d851 bhi.n 801a81c <_dtoa_r+0x224>
|
|
801a778: 4b5d ldr r3, [pc, #372] @ (801a8f0 <_dtoa_r+0x2f8>)
|
|
801a77a: eb03 03c8 add.w r3, r3, r8, lsl #3
|
|
801a77e: e9d3 2300 ldrd r2, r3, [r3]
|
|
801a782: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
801a786: f7e6 f981 bl 8000a8c <__aeabi_dcmplt>
|
|
801a78a: 2800 cmp r0, #0
|
|
801a78c: d048 beq.n 801a820 <_dtoa_r+0x228>
|
|
801a78e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
|
|
801a792: 2300 movs r3, #0
|
|
801a794: 9312 str r3, [sp, #72] @ 0x48
|
|
801a796: 1b2d subs r5, r5, r4
|
|
801a798: 1e6b subs r3, r5, #1
|
|
801a79a: 9308 str r3, [sp, #32]
|
|
801a79c: bf43 ittte mi
|
|
801a79e: 2300 movmi r3, #0
|
|
801a7a0: f1c5 0701 rsbmi r7, r5, #1
|
|
801a7a4: 9308 strmi r3, [sp, #32]
|
|
801a7a6: 2700 movpl r7, #0
|
|
801a7a8: f1b8 0f00 cmp.w r8, #0
|
|
801a7ac: db3a blt.n 801a824 <_dtoa_r+0x22c>
|
|
801a7ae: 9b08 ldr r3, [sp, #32]
|
|
801a7b0: f8cd 8034 str.w r8, [sp, #52] @ 0x34
|
|
801a7b4: 4443 add r3, r8
|
|
801a7b6: 9308 str r3, [sp, #32]
|
|
801a7b8: 2300 movs r3, #0
|
|
801a7ba: 9309 str r3, [sp, #36] @ 0x24
|
|
801a7bc: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801a7be: 2b09 cmp r3, #9
|
|
801a7c0: d862 bhi.n 801a888 <_dtoa_r+0x290>
|
|
801a7c2: 2b05 cmp r3, #5
|
|
801a7c4: bfc4 itt gt
|
|
801a7c6: 3b04 subgt r3, #4
|
|
801a7c8: 930a strgt r3, [sp, #40] @ 0x28
|
|
801a7ca: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801a7cc: f1a3 0302 sub.w r3, r3, #2
|
|
801a7d0: bfcc ite gt
|
|
801a7d2: 2400 movgt r4, #0
|
|
801a7d4: 2401 movle r4, #1
|
|
801a7d6: 2b03 cmp r3, #3
|
|
801a7d8: d862 bhi.n 801a8a0 <_dtoa_r+0x2a8>
|
|
801a7da: e8df f003 tbb [pc, r3]
|
|
801a7de: 5351 .short 0x5351
|
|
801a7e0: 2b36 .short 0x2b36
|
|
801a7e2: 9c17 ldr r4, [sp, #92] @ 0x5c
|
|
801a7e4: 442c add r4, r5
|
|
801a7e6: f204 4332 addw r3, r4, #1074 @ 0x432
|
|
801a7ea: 2b20 cmp r3, #32
|
|
801a7ec: bfc1 itttt gt
|
|
801a7ee: f1c3 0340 rsbgt r3, r3, #64 @ 0x40
|
|
801a7f2: fa08 f803 lslgt.w r8, r8, r3
|
|
801a7f6: f204 4312 addwgt r3, r4, #1042 @ 0x412
|
|
801a7fa: fa26 f303 lsrgt.w r3, r6, r3
|
|
801a7fe: bfd6 itet le
|
|
801a800: f1c3 0320 rsble r3, r3, #32
|
|
801a804: ea48 0003 orrgt.w r0, r8, r3
|
|
801a808: fa06 f003 lslle.w r0, r6, r3
|
|
801a80c: f7e5 fe52 bl 80004b4 <__aeabi_ui2d>
|
|
801a810: 2201 movs r2, #1
|
|
801a812: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000
|
|
801a816: 3c01 subs r4, #1
|
|
801a818: 9214 str r2, [sp, #80] @ 0x50
|
|
801a81a: e775 b.n 801a708 <_dtoa_r+0x110>
|
|
801a81c: 2301 movs r3, #1
|
|
801a81e: e7b9 b.n 801a794 <_dtoa_r+0x19c>
|
|
801a820: 9012 str r0, [sp, #72] @ 0x48
|
|
801a822: e7b8 b.n 801a796 <_dtoa_r+0x19e>
|
|
801a824: f1c8 0300 rsb r3, r8, #0
|
|
801a828: 9309 str r3, [sp, #36] @ 0x24
|
|
801a82a: 2300 movs r3, #0
|
|
801a82c: eba7 0708 sub.w r7, r7, r8
|
|
801a830: 930d str r3, [sp, #52] @ 0x34
|
|
801a832: e7c3 b.n 801a7bc <_dtoa_r+0x1c4>
|
|
801a834: 2301 movs r3, #1
|
|
801a836: 930b str r3, [sp, #44] @ 0x2c
|
|
801a838: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
801a83a: 4443 add r3, r8
|
|
801a83c: 9305 str r3, [sp, #20]
|
|
801a83e: 3301 adds r3, #1
|
|
801a840: 2b01 cmp r3, #1
|
|
801a842: 9304 str r3, [sp, #16]
|
|
801a844: bfb8 it lt
|
|
801a846: 2301 movlt r3, #1
|
|
801a848: e006 b.n 801a858 <_dtoa_r+0x260>
|
|
801a84a: 2301 movs r3, #1
|
|
801a84c: 930b str r3, [sp, #44] @ 0x2c
|
|
801a84e: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
801a850: 2b00 cmp r3, #0
|
|
801a852: dd28 ble.n 801a8a6 <_dtoa_r+0x2ae>
|
|
801a854: e9cd 3304 strd r3, r3, [sp, #16]
|
|
801a858: f8d9 001c ldr.w r0, [r9, #28]
|
|
801a85c: 2100 movs r1, #0
|
|
801a85e: 2204 movs r2, #4
|
|
801a860: f102 0514 add.w r5, r2, #20
|
|
801a864: 429d cmp r5, r3
|
|
801a866: d923 bls.n 801a8b0 <_dtoa_r+0x2b8>
|
|
801a868: 6041 str r1, [r0, #4]
|
|
801a86a: 4648 mov r0, r9
|
|
801a86c: f000 fda0 bl 801b3b0 <_Balloc>
|
|
801a870: 9000 str r0, [sp, #0]
|
|
801a872: 2800 cmp r0, #0
|
|
801a874: d140 bne.n 801a8f8 <_dtoa_r+0x300>
|
|
801a876: 4b1f ldr r3, [pc, #124] @ (801a8f4 <_dtoa_r+0x2fc>)
|
|
801a878: 4602 mov r2, r0
|
|
801a87a: f240 11af movw r1, #431 @ 0x1af
|
|
801a87e: e6d2 b.n 801a626 <_dtoa_r+0x2e>
|
|
801a880: 2300 movs r3, #0
|
|
801a882: e7e3 b.n 801a84c <_dtoa_r+0x254>
|
|
801a884: 2300 movs r3, #0
|
|
801a886: e7d6 b.n 801a836 <_dtoa_r+0x23e>
|
|
801a888: 2401 movs r4, #1
|
|
801a88a: 2300 movs r3, #0
|
|
801a88c: e9cd 340a strd r3, r4, [sp, #40] @ 0x28
|
|
801a890: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
801a894: e9cd 3304 strd r3, r3, [sp, #16]
|
|
801a898: 2200 movs r2, #0
|
|
801a89a: 2312 movs r3, #18
|
|
801a89c: 920c str r2, [sp, #48] @ 0x30
|
|
801a89e: e7db b.n 801a858 <_dtoa_r+0x260>
|
|
801a8a0: 2301 movs r3, #1
|
|
801a8a2: 930b str r3, [sp, #44] @ 0x2c
|
|
801a8a4: e7f4 b.n 801a890 <_dtoa_r+0x298>
|
|
801a8a6: 2301 movs r3, #1
|
|
801a8a8: e9cd 3304 strd r3, r3, [sp, #16]
|
|
801a8ac: 461a mov r2, r3
|
|
801a8ae: e7f5 b.n 801a89c <_dtoa_r+0x2a4>
|
|
801a8b0: 3101 adds r1, #1
|
|
801a8b2: 0052 lsls r2, r2, #1
|
|
801a8b4: e7d4 b.n 801a860 <_dtoa_r+0x268>
|
|
801a8b6: bf00 nop
|
|
801a8b8: 636f4361 .word 0x636f4361
|
|
801a8bc: 3fd287a7 .word 0x3fd287a7
|
|
801a8c0: 8b60c8b3 .word 0x8b60c8b3
|
|
801a8c4: 3fc68a28 .word 0x3fc68a28
|
|
801a8c8: 509f79fb .word 0x509f79fb
|
|
801a8cc: 3fd34413 .word 0x3fd34413
|
|
801a8d0: 0801e656 .word 0x0801e656
|
|
801a8d4: 0801e66d .word 0x0801e66d
|
|
801a8d8: 7ff00000 .word 0x7ff00000
|
|
801a8dc: 0801e652 .word 0x0801e652
|
|
801a8e0: 0801e649 .word 0x0801e649
|
|
801a8e4: 0801e621 .word 0x0801e621
|
|
801a8e8: 0801e620 .word 0x0801e620
|
|
801a8ec: 3ff80000 .word 0x3ff80000
|
|
801a8f0: 0801e820 .word 0x0801e820
|
|
801a8f4: 0801e6c5 .word 0x0801e6c5
|
|
801a8f8: f8d9 301c ldr.w r3, [r9, #28]
|
|
801a8fc: 9a00 ldr r2, [sp, #0]
|
|
801a8fe: 601a str r2, [r3, #0]
|
|
801a900: 9b04 ldr r3, [sp, #16]
|
|
801a902: 2b0e cmp r3, #14
|
|
801a904: f200 80a1 bhi.w 801aa4a <_dtoa_r+0x452>
|
|
801a908: 2c00 cmp r4, #0
|
|
801a90a: f000 809e beq.w 801aa4a <_dtoa_r+0x452>
|
|
801a90e: f1b8 0f00 cmp.w r8, #0
|
|
801a912: dd36 ble.n 801a982 <_dtoa_r+0x38a>
|
|
801a914: 4b9e ldr r3, [pc, #632] @ (801ab90 <_dtoa_r+0x598>)
|
|
801a916: f008 020f and.w r2, r8, #15
|
|
801a91a: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
801a91e: f418 7f80 tst.w r8, #256 @ 0x100
|
|
801a922: e9d3 ab00 ldrd sl, fp, [r3]
|
|
801a926: ea4f 1528 mov.w r5, r8, asr #4
|
|
801a92a: d016 beq.n 801a95a <_dtoa_r+0x362>
|
|
801a92c: 4b99 ldr r3, [pc, #612] @ (801ab94 <_dtoa_r+0x59c>)
|
|
801a92e: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
801a932: e9d3 2308 ldrd r2, r3, [r3, #32]
|
|
801a936: f7e5 ff61 bl 80007fc <__aeabi_ddiv>
|
|
801a93a: e9cd 0102 strd r0, r1, [sp, #8]
|
|
801a93e: f005 050f and.w r5, r5, #15
|
|
801a942: 2403 movs r4, #3
|
|
801a944: 4e93 ldr r6, [pc, #588] @ (801ab94 <_dtoa_r+0x59c>)
|
|
801a946: b975 cbnz r5, 801a966 <_dtoa_r+0x36e>
|
|
801a948: e9dd 0102 ldrd r0, r1, [sp, #8]
|
|
801a94c: 4652 mov r2, sl
|
|
801a94e: 465b mov r3, fp
|
|
801a950: f7e5 ff54 bl 80007fc <__aeabi_ddiv>
|
|
801a954: 4682 mov sl, r0
|
|
801a956: 468b mov fp, r1
|
|
801a958: e02d b.n 801a9b6 <_dtoa_r+0x3be>
|
|
801a95a: ed9d 7b06 vldr d7, [sp, #24]
|
|
801a95e: 2402 movs r4, #2
|
|
801a960: ed8d 7b02 vstr d7, [sp, #8]
|
|
801a964: e7ee b.n 801a944 <_dtoa_r+0x34c>
|
|
801a966: 07e9 lsls r1, r5, #31
|
|
801a968: d508 bpl.n 801a97c <_dtoa_r+0x384>
|
|
801a96a: 4650 mov r0, sl
|
|
801a96c: 4659 mov r1, fp
|
|
801a96e: e9d6 2300 ldrd r2, r3, [r6]
|
|
801a972: f7e5 fe19 bl 80005a8 <__aeabi_dmul>
|
|
801a976: 3401 adds r4, #1
|
|
801a978: 4682 mov sl, r0
|
|
801a97a: 468b mov fp, r1
|
|
801a97c: 106d asrs r5, r5, #1
|
|
801a97e: 3608 adds r6, #8
|
|
801a980: e7e1 b.n 801a946 <_dtoa_r+0x34e>
|
|
801a982: f000 80ad beq.w 801aae0 <_dtoa_r+0x4e8>
|
|
801a986: f1c8 0500 rsb r5, r8, #0
|
|
801a98a: 4b81 ldr r3, [pc, #516] @ (801ab90 <_dtoa_r+0x598>)
|
|
801a98c: 4e81 ldr r6, [pc, #516] @ (801ab94 <_dtoa_r+0x59c>)
|
|
801a98e: f005 020f and.w r2, r5, #15
|
|
801a992: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
801a996: e9d3 2300 ldrd r2, r3, [r3]
|
|
801a99a: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
801a99e: f7e5 fe03 bl 80005a8 <__aeabi_dmul>
|
|
801a9a2: 112d asrs r5, r5, #4
|
|
801a9a4: 4682 mov sl, r0
|
|
801a9a6: 468b mov fp, r1
|
|
801a9a8: 2300 movs r3, #0
|
|
801a9aa: 2402 movs r4, #2
|
|
801a9ac: 2d00 cmp r5, #0
|
|
801a9ae: f040 808c bne.w 801aaca <_dtoa_r+0x4d2>
|
|
801a9b2: 2b00 cmp r3, #0
|
|
801a9b4: d1ce bne.n 801a954 <_dtoa_r+0x35c>
|
|
801a9b6: 9b12 ldr r3, [sp, #72] @ 0x48
|
|
801a9b8: 2b00 cmp r3, #0
|
|
801a9ba: f000 8095 beq.w 801aae8 <_dtoa_r+0x4f0>
|
|
801a9be: 4b76 ldr r3, [pc, #472] @ (801ab98 <_dtoa_r+0x5a0>)
|
|
801a9c0: 2200 movs r2, #0
|
|
801a9c2: 4650 mov r0, sl
|
|
801a9c4: 4659 mov r1, fp
|
|
801a9c6: f7e6 f861 bl 8000a8c <__aeabi_dcmplt>
|
|
801a9ca: 2800 cmp r0, #0
|
|
801a9cc: f000 808c beq.w 801aae8 <_dtoa_r+0x4f0>
|
|
801a9d0: 9b04 ldr r3, [sp, #16]
|
|
801a9d2: 2b00 cmp r3, #0
|
|
801a9d4: f000 8088 beq.w 801aae8 <_dtoa_r+0x4f0>
|
|
801a9d8: 9b05 ldr r3, [sp, #20]
|
|
801a9da: 2b00 cmp r3, #0
|
|
801a9dc: dd35 ble.n 801aa4a <_dtoa_r+0x452>
|
|
801a9de: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff
|
|
801a9e2: 9302 str r3, [sp, #8]
|
|
801a9e4: 4650 mov r0, sl
|
|
801a9e6: 4659 mov r1, fp
|
|
801a9e8: 4b6c ldr r3, [pc, #432] @ (801ab9c <_dtoa_r+0x5a4>)
|
|
801a9ea: 2200 movs r2, #0
|
|
801a9ec: f7e5 fddc bl 80005a8 <__aeabi_dmul>
|
|
801a9f0: 9e05 ldr r6, [sp, #20]
|
|
801a9f2: 4682 mov sl, r0
|
|
801a9f4: 468b mov fp, r1
|
|
801a9f6: 3401 adds r4, #1
|
|
801a9f8: 4620 mov r0, r4
|
|
801a9fa: f7e5 fd6b bl 80004d4 <__aeabi_i2d>
|
|
801a9fe: 4652 mov r2, sl
|
|
801aa00: 465b mov r3, fp
|
|
801aa02: f7e5 fdd1 bl 80005a8 <__aeabi_dmul>
|
|
801aa06: 4b66 ldr r3, [pc, #408] @ (801aba0 <_dtoa_r+0x5a8>)
|
|
801aa08: 2200 movs r2, #0
|
|
801aa0a: f7e5 fc17 bl 800023c <__adddf3>
|
|
801aa0e: 4604 mov r4, r0
|
|
801aa10: f1a1 7550 sub.w r5, r1, #54525952 @ 0x3400000
|
|
801aa14: e9cd 4510 strd r4, r5, [sp, #64] @ 0x40
|
|
801aa18: 2e00 cmp r6, #0
|
|
801aa1a: d169 bne.n 801aaf0 <_dtoa_r+0x4f8>
|
|
801aa1c: 4b61 ldr r3, [pc, #388] @ (801aba4 <_dtoa_r+0x5ac>)
|
|
801aa1e: 2200 movs r2, #0
|
|
801aa20: 4650 mov r0, sl
|
|
801aa22: 4659 mov r1, fp
|
|
801aa24: f7e5 fc08 bl 8000238 <__aeabi_dsub>
|
|
801aa28: 4622 mov r2, r4
|
|
801aa2a: 462b mov r3, r5
|
|
801aa2c: 4682 mov sl, r0
|
|
801aa2e: 468b mov fp, r1
|
|
801aa30: f7e6 f84a bl 8000ac8 <__aeabi_dcmpgt>
|
|
801aa34: 2800 cmp r0, #0
|
|
801aa36: f040 8294 bne.w 801af62 <_dtoa_r+0x96a>
|
|
801aa3a: 4622 mov r2, r4
|
|
801aa3c: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000
|
|
801aa40: 4650 mov r0, sl
|
|
801aa42: 4659 mov r1, fp
|
|
801aa44: f7e6 f822 bl 8000a8c <__aeabi_dcmplt>
|
|
801aa48: bb20 cbnz r0, 801aa94 <_dtoa_r+0x49c>
|
|
801aa4a: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801aa4c: 2b00 cmp r3, #0
|
|
801aa4e: f2c0 8160 blt.w 801ad12 <_dtoa_r+0x71a>
|
|
801aa52: f1b8 0f0e cmp.w r8, #14
|
|
801aa56: f300 815c bgt.w 801ad12 <_dtoa_r+0x71a>
|
|
801aa5a: 4b4d ldr r3, [pc, #308] @ (801ab90 <_dtoa_r+0x598>)
|
|
801aa5c: eb03 03c8 add.w r3, r3, r8, lsl #3
|
|
801aa60: e9d3 ab00 ldrd sl, fp, [r3]
|
|
801aa64: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
801aa66: 2b00 cmp r3, #0
|
|
801aa68: f280 80ee bge.w 801ac48 <_dtoa_r+0x650>
|
|
801aa6c: 9b04 ldr r3, [sp, #16]
|
|
801aa6e: 2b00 cmp r3, #0
|
|
801aa70: f300 80ea bgt.w 801ac48 <_dtoa_r+0x650>
|
|
801aa74: d10e bne.n 801aa94 <_dtoa_r+0x49c>
|
|
801aa76: 4b4b ldr r3, [pc, #300] @ (801aba4 <_dtoa_r+0x5ac>)
|
|
801aa78: 2200 movs r2, #0
|
|
801aa7a: 4650 mov r0, sl
|
|
801aa7c: 4659 mov r1, fp
|
|
801aa7e: f7e5 fd93 bl 80005a8 <__aeabi_dmul>
|
|
801aa82: 4602 mov r2, r0
|
|
801aa84: 460b mov r3, r1
|
|
801aa86: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
801aa8a: f7e6 f809 bl 8000aa0 <__aeabi_dcmple>
|
|
801aa8e: 2800 cmp r0, #0
|
|
801aa90: f000 826a beq.w 801af68 <_dtoa_r+0x970>
|
|
801aa94: 2500 movs r5, #0
|
|
801aa96: 462c mov r4, r5
|
|
801aa98: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
801aa9a: 9e00 ldr r6, [sp, #0]
|
|
801aa9c: 43db mvns r3, r3
|
|
801aa9e: 9302 str r3, [sp, #8]
|
|
801aaa0: 4627 mov r7, r4
|
|
801aaa2: 2400 movs r4, #0
|
|
801aaa4: 4629 mov r1, r5
|
|
801aaa6: 4648 mov r0, r9
|
|
801aaa8: f000 fcc0 bl 801b42c <_Bfree>
|
|
801aaac: 2f00 cmp r7, #0
|
|
801aaae: f000 80c1 beq.w 801ac34 <_dtoa_r+0x63c>
|
|
801aab2: b12c cbz r4, 801aac0 <_dtoa_r+0x4c8>
|
|
801aab4: 42bc cmp r4, r7
|
|
801aab6: d003 beq.n 801aac0 <_dtoa_r+0x4c8>
|
|
801aab8: 4621 mov r1, r4
|
|
801aaba: 4648 mov r0, r9
|
|
801aabc: f000 fcb6 bl 801b42c <_Bfree>
|
|
801aac0: 4639 mov r1, r7
|
|
801aac2: 4648 mov r0, r9
|
|
801aac4: f000 fcb2 bl 801b42c <_Bfree>
|
|
801aac8: e0b4 b.n 801ac34 <_dtoa_r+0x63c>
|
|
801aaca: 07ea lsls r2, r5, #31
|
|
801aacc: d505 bpl.n 801aada <_dtoa_r+0x4e2>
|
|
801aace: e9d6 2300 ldrd r2, r3, [r6]
|
|
801aad2: f7e5 fd69 bl 80005a8 <__aeabi_dmul>
|
|
801aad6: 3401 adds r4, #1
|
|
801aad8: 2301 movs r3, #1
|
|
801aada: 106d asrs r5, r5, #1
|
|
801aadc: 3608 adds r6, #8
|
|
801aade: e765 b.n 801a9ac <_dtoa_r+0x3b4>
|
|
801aae0: e9dd ab06 ldrd sl, fp, [sp, #24]
|
|
801aae4: 2402 movs r4, #2
|
|
801aae6: e766 b.n 801a9b6 <_dtoa_r+0x3be>
|
|
801aae8: 9e04 ldr r6, [sp, #16]
|
|
801aaea: f8cd 8008 str.w r8, [sp, #8]
|
|
801aaee: e783 b.n 801a9f8 <_dtoa_r+0x400>
|
|
801aaf0: 4b27 ldr r3, [pc, #156] @ (801ab90 <_dtoa_r+0x598>)
|
|
801aaf2: eb03 03c6 add.w r3, r3, r6, lsl #3
|
|
801aaf6: e953 0102 ldrd r0, r1, [r3, #-8]
|
|
801aafa: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
801aafc: 2b00 cmp r3, #0
|
|
801aafe: d055 beq.n 801abac <_dtoa_r+0x5b4>
|
|
801ab00: 4602 mov r2, r0
|
|
801ab02: 460b mov r3, r1
|
|
801ab04: 2000 movs r0, #0
|
|
801ab06: 4928 ldr r1, [pc, #160] @ (801aba8 <_dtoa_r+0x5b0>)
|
|
801ab08: f7e5 fe78 bl 80007fc <__aeabi_ddiv>
|
|
801ab0c: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
|
|
801ab10: f7e5 fb92 bl 8000238 <__aeabi_dsub>
|
|
801ab14: 9b00 ldr r3, [sp, #0]
|
|
801ab16: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40
|
|
801ab1a: 199d adds r5, r3, r6
|
|
801ab1c: 461e mov r6, r3
|
|
801ab1e: 4659 mov r1, fp
|
|
801ab20: 4650 mov r0, sl
|
|
801ab22: f7e5 fff1 bl 8000b08 <__aeabi_d2iz>
|
|
801ab26: 4604 mov r4, r0
|
|
801ab28: f7e5 fcd4 bl 80004d4 <__aeabi_i2d>
|
|
801ab2c: 4602 mov r2, r0
|
|
801ab2e: 460b mov r3, r1
|
|
801ab30: 4650 mov r0, sl
|
|
801ab32: 4659 mov r1, fp
|
|
801ab34: f7e5 fb80 bl 8000238 <__aeabi_dsub>
|
|
801ab38: 3430 adds r4, #48 @ 0x30
|
|
801ab3a: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
|
|
801ab3e: f806 4b01 strb.w r4, [r6], #1
|
|
801ab42: 4682 mov sl, r0
|
|
801ab44: 468b mov fp, r1
|
|
801ab46: f7e5 ffa1 bl 8000a8c <__aeabi_dcmplt>
|
|
801ab4a: 2800 cmp r0, #0
|
|
801ab4c: d172 bne.n 801ac34 <_dtoa_r+0x63c>
|
|
801ab4e: 4652 mov r2, sl
|
|
801ab50: 465b mov r3, fp
|
|
801ab52: 4911 ldr r1, [pc, #68] @ (801ab98 <_dtoa_r+0x5a0>)
|
|
801ab54: 2000 movs r0, #0
|
|
801ab56: f7e5 fb6f bl 8000238 <__aeabi_dsub>
|
|
801ab5a: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
|
|
801ab5e: f7e5 ff95 bl 8000a8c <__aeabi_dcmplt>
|
|
801ab62: 2800 cmp r0, #0
|
|
801ab64: f040 80b6 bne.w 801acd4 <_dtoa_r+0x6dc>
|
|
801ab68: 42ae cmp r6, r5
|
|
801ab6a: f43f af6e beq.w 801aa4a <_dtoa_r+0x452>
|
|
801ab6e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40
|
|
801ab72: 4b0a ldr r3, [pc, #40] @ (801ab9c <_dtoa_r+0x5a4>)
|
|
801ab74: 2200 movs r2, #0
|
|
801ab76: f7e5 fd17 bl 80005a8 <__aeabi_dmul>
|
|
801ab7a: 4b08 ldr r3, [pc, #32] @ (801ab9c <_dtoa_r+0x5a4>)
|
|
801ab7c: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40
|
|
801ab80: 2200 movs r2, #0
|
|
801ab82: 4650 mov r0, sl
|
|
801ab84: 4659 mov r1, fp
|
|
801ab86: f7e5 fd0f bl 80005a8 <__aeabi_dmul>
|
|
801ab8a: 4682 mov sl, r0
|
|
801ab8c: 468b mov fp, r1
|
|
801ab8e: e7c6 b.n 801ab1e <_dtoa_r+0x526>
|
|
801ab90: 0801e820 .word 0x0801e820
|
|
801ab94: 0801e7f8 .word 0x0801e7f8
|
|
801ab98: 3ff00000 .word 0x3ff00000
|
|
801ab9c: 40240000 .word 0x40240000
|
|
801aba0: 401c0000 .word 0x401c0000
|
|
801aba4: 40140000 .word 0x40140000
|
|
801aba8: 3fe00000 .word 0x3fe00000
|
|
801abac: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
|
|
801abb0: f7e5 fcfa bl 80005a8 <__aeabi_dmul>
|
|
801abb4: 9b00 ldr r3, [sp, #0]
|
|
801abb6: 9d00 ldr r5, [sp, #0]
|
|
801abb8: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40
|
|
801abbc: 4433 add r3, r6
|
|
801abbe: 9315 str r3, [sp, #84] @ 0x54
|
|
801abc0: 4659 mov r1, fp
|
|
801abc2: 4650 mov r0, sl
|
|
801abc4: f7e5 ffa0 bl 8000b08 <__aeabi_d2iz>
|
|
801abc8: 4604 mov r4, r0
|
|
801abca: f7e5 fc83 bl 80004d4 <__aeabi_i2d>
|
|
801abce: 3430 adds r4, #48 @ 0x30
|
|
801abd0: 460b mov r3, r1
|
|
801abd2: 4602 mov r2, r0
|
|
801abd4: 4659 mov r1, fp
|
|
801abd6: 4650 mov r0, sl
|
|
801abd8: f7e5 fb2e bl 8000238 <__aeabi_dsub>
|
|
801abdc: f805 4b01 strb.w r4, [r5], #1
|
|
801abe0: 9b15 ldr r3, [sp, #84] @ 0x54
|
|
801abe2: 429d cmp r5, r3
|
|
801abe4: 4682 mov sl, r0
|
|
801abe6: 468b mov fp, r1
|
|
801abe8: d127 bne.n 801ac3a <_dtoa_r+0x642>
|
|
801abea: 9b00 ldr r3, [sp, #0]
|
|
801abec: 2200 movs r2, #0
|
|
801abee: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40
|
|
801abf2: 441e add r6, r3
|
|
801abf4: 4bb3 ldr r3, [pc, #716] @ (801aec4 <_dtoa_r+0x8cc>)
|
|
801abf6: f7e5 fb21 bl 800023c <__adddf3>
|
|
801abfa: 4602 mov r2, r0
|
|
801abfc: 460b mov r3, r1
|
|
801abfe: 4650 mov r0, sl
|
|
801ac00: 4659 mov r1, fp
|
|
801ac02: f7e5 ff61 bl 8000ac8 <__aeabi_dcmpgt>
|
|
801ac06: 2800 cmp r0, #0
|
|
801ac08: d164 bne.n 801acd4 <_dtoa_r+0x6dc>
|
|
801ac0a: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
|
|
801ac0e: 49ad ldr r1, [pc, #692] @ (801aec4 <_dtoa_r+0x8cc>)
|
|
801ac10: 2000 movs r0, #0
|
|
801ac12: f7e5 fb11 bl 8000238 <__aeabi_dsub>
|
|
801ac16: 4602 mov r2, r0
|
|
801ac18: 460b mov r3, r1
|
|
801ac1a: 4650 mov r0, sl
|
|
801ac1c: 4659 mov r1, fp
|
|
801ac1e: f7e5 ff35 bl 8000a8c <__aeabi_dcmplt>
|
|
801ac22: 2800 cmp r0, #0
|
|
801ac24: f43f af11 beq.w 801aa4a <_dtoa_r+0x452>
|
|
801ac28: 4633 mov r3, r6
|
|
801ac2a: f816 2d01 ldrb.w r2, [r6, #-1]!
|
|
801ac2e: 2a30 cmp r2, #48 @ 0x30
|
|
801ac30: d0fa beq.n 801ac28 <_dtoa_r+0x630>
|
|
801ac32: 461e mov r6, r3
|
|
801ac34: f8dd 8008 ldr.w r8, [sp, #8]
|
|
801ac38: e03a b.n 801acb0 <_dtoa_r+0x6b8>
|
|
801ac3a: 4ba3 ldr r3, [pc, #652] @ (801aec8 <_dtoa_r+0x8d0>)
|
|
801ac3c: 2200 movs r2, #0
|
|
801ac3e: f7e5 fcb3 bl 80005a8 <__aeabi_dmul>
|
|
801ac42: 4682 mov sl, r0
|
|
801ac44: 468b mov fp, r1
|
|
801ac46: e7bb b.n 801abc0 <_dtoa_r+0x5c8>
|
|
801ac48: 9e00 ldr r6, [sp, #0]
|
|
801ac4a: 4652 mov r2, sl
|
|
801ac4c: 465b mov r3, fp
|
|
801ac4e: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
801ac52: f7e5 fdd3 bl 80007fc <__aeabi_ddiv>
|
|
801ac56: f7e5 ff57 bl 8000b08 <__aeabi_d2iz>
|
|
801ac5a: 4607 mov r7, r0
|
|
801ac5c: f7e5 fc3a bl 80004d4 <__aeabi_i2d>
|
|
801ac60: 4652 mov r2, sl
|
|
801ac62: 465b mov r3, fp
|
|
801ac64: f7e5 fca0 bl 80005a8 <__aeabi_dmul>
|
|
801ac68: 4602 mov r2, r0
|
|
801ac6a: 460b mov r3, r1
|
|
801ac6c: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
801ac70: f7e5 fae2 bl 8000238 <__aeabi_dsub>
|
|
801ac74: f107 0c30 add.w ip, r7, #48 @ 0x30
|
|
801ac78: 9c00 ldr r4, [sp, #0]
|
|
801ac7a: f806 cb01 strb.w ip, [r6], #1
|
|
801ac7e: eba6 0c04 sub.w ip, r6, r4
|
|
801ac82: 9c04 ldr r4, [sp, #16]
|
|
801ac84: 4564 cmp r4, ip
|
|
801ac86: 4602 mov r2, r0
|
|
801ac88: 460b mov r3, r1
|
|
801ac8a: d133 bne.n 801acf4 <_dtoa_r+0x6fc>
|
|
801ac8c: f7e5 fad6 bl 800023c <__adddf3>
|
|
801ac90: 4652 mov r2, sl
|
|
801ac92: 465b mov r3, fp
|
|
801ac94: 4604 mov r4, r0
|
|
801ac96: 460d mov r5, r1
|
|
801ac98: f7e5 ff16 bl 8000ac8 <__aeabi_dcmpgt>
|
|
801ac9c: b9c0 cbnz r0, 801acd0 <_dtoa_r+0x6d8>
|
|
801ac9e: 4652 mov r2, sl
|
|
801aca0: 465b mov r3, fp
|
|
801aca2: 4620 mov r0, r4
|
|
801aca4: 4629 mov r1, r5
|
|
801aca6: f7e5 fee7 bl 8000a78 <__aeabi_dcmpeq>
|
|
801acaa: b108 cbz r0, 801acb0 <_dtoa_r+0x6b8>
|
|
801acac: 07fb lsls r3, r7, #31
|
|
801acae: d40f bmi.n 801acd0 <_dtoa_r+0x6d8>
|
|
801acb0: 9901 ldr r1, [sp, #4]
|
|
801acb2: 4648 mov r0, r9
|
|
801acb4: f000 fbba bl 801b42c <_Bfree>
|
|
801acb8: 2300 movs r3, #0
|
|
801acba: 9a13 ldr r2, [sp, #76] @ 0x4c
|
|
801acbc: 7033 strb r3, [r6, #0]
|
|
801acbe: f108 0301 add.w r3, r8, #1
|
|
801acc2: 6013 str r3, [r2, #0]
|
|
801acc4: 9b23 ldr r3, [sp, #140] @ 0x8c
|
|
801acc6: 2b00 cmp r3, #0
|
|
801acc8: f43f ace6 beq.w 801a698 <_dtoa_r+0xa0>
|
|
801accc: 601e str r6, [r3, #0]
|
|
801acce: e4e3 b.n 801a698 <_dtoa_r+0xa0>
|
|
801acd0: f8cd 8008 str.w r8, [sp, #8]
|
|
801acd4: 4633 mov r3, r6
|
|
801acd6: 461e mov r6, r3
|
|
801acd8: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
801acdc: 2a39 cmp r2, #57 @ 0x39
|
|
801acde: d106 bne.n 801acee <_dtoa_r+0x6f6>
|
|
801ace0: 9a00 ldr r2, [sp, #0]
|
|
801ace2: 429a cmp r2, r3
|
|
801ace4: d1f7 bne.n 801acd6 <_dtoa_r+0x6de>
|
|
801ace6: 9a02 ldr r2, [sp, #8]
|
|
801ace8: 3201 adds r2, #1
|
|
801acea: 9202 str r2, [sp, #8]
|
|
801acec: 2230 movs r2, #48 @ 0x30
|
|
801acee: 3201 adds r2, #1
|
|
801acf0: 701a strb r2, [r3, #0]
|
|
801acf2: e79f b.n 801ac34 <_dtoa_r+0x63c>
|
|
801acf4: 4b74 ldr r3, [pc, #464] @ (801aec8 <_dtoa_r+0x8d0>)
|
|
801acf6: 2200 movs r2, #0
|
|
801acf8: f7e5 fc56 bl 80005a8 <__aeabi_dmul>
|
|
801acfc: 4602 mov r2, r0
|
|
801acfe: 460b mov r3, r1
|
|
801ad00: e9cd 2306 strd r2, r3, [sp, #24]
|
|
801ad04: 2200 movs r2, #0
|
|
801ad06: 2300 movs r3, #0
|
|
801ad08: f7e5 feb6 bl 8000a78 <__aeabi_dcmpeq>
|
|
801ad0c: 2800 cmp r0, #0
|
|
801ad0e: d09c beq.n 801ac4a <_dtoa_r+0x652>
|
|
801ad10: e7ce b.n 801acb0 <_dtoa_r+0x6b8>
|
|
801ad12: 9a0b ldr r2, [sp, #44] @ 0x2c
|
|
801ad14: 2a00 cmp r2, #0
|
|
801ad16: f000 80e3 beq.w 801aee0 <_dtoa_r+0x8e8>
|
|
801ad1a: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
801ad1c: 2a01 cmp r2, #1
|
|
801ad1e: f300 80c2 bgt.w 801aea6 <_dtoa_r+0x8ae>
|
|
801ad22: 9a14 ldr r2, [sp, #80] @ 0x50
|
|
801ad24: 2a00 cmp r2, #0
|
|
801ad26: f000 80ba beq.w 801ae9e <_dtoa_r+0x8a6>
|
|
801ad2a: f203 4333 addw r3, r3, #1075 @ 0x433
|
|
801ad2e: 9d09 ldr r5, [sp, #36] @ 0x24
|
|
801ad30: 463e mov r6, r7
|
|
801ad32: 9a08 ldr r2, [sp, #32]
|
|
801ad34: 2101 movs r1, #1
|
|
801ad36: 441a add r2, r3
|
|
801ad38: 4648 mov r0, r9
|
|
801ad3a: 441f add r7, r3
|
|
801ad3c: 9208 str r2, [sp, #32]
|
|
801ad3e: f000 fc73 bl 801b628 <__i2b>
|
|
801ad42: 4604 mov r4, r0
|
|
801ad44: b156 cbz r6, 801ad5c <_dtoa_r+0x764>
|
|
801ad46: 9b08 ldr r3, [sp, #32]
|
|
801ad48: 2b00 cmp r3, #0
|
|
801ad4a: dd07 ble.n 801ad5c <_dtoa_r+0x764>
|
|
801ad4c: 42b3 cmp r3, r6
|
|
801ad4e: 9a08 ldr r2, [sp, #32]
|
|
801ad50: bfa8 it ge
|
|
801ad52: 4633 movge r3, r6
|
|
801ad54: 1aff subs r7, r7, r3
|
|
801ad56: 1af6 subs r6, r6, r3
|
|
801ad58: 1ad3 subs r3, r2, r3
|
|
801ad5a: 9308 str r3, [sp, #32]
|
|
801ad5c: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
801ad5e: b30b cbz r3, 801ada4 <_dtoa_r+0x7ac>
|
|
801ad60: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
801ad62: 2b00 cmp r3, #0
|
|
801ad64: f000 80c3 beq.w 801aeee <_dtoa_r+0x8f6>
|
|
801ad68: 2d00 cmp r5, #0
|
|
801ad6a: f000 80bd beq.w 801aee8 <_dtoa_r+0x8f0>
|
|
801ad6e: 4621 mov r1, r4
|
|
801ad70: 462a mov r2, r5
|
|
801ad72: 4648 mov r0, r9
|
|
801ad74: f000 fd18 bl 801b7a8 <__pow5mult>
|
|
801ad78: 9a01 ldr r2, [sp, #4]
|
|
801ad7a: 4601 mov r1, r0
|
|
801ad7c: 4604 mov r4, r0
|
|
801ad7e: 4648 mov r0, r9
|
|
801ad80: f000 fc68 bl 801b654 <__multiply>
|
|
801ad84: 9901 ldr r1, [sp, #4]
|
|
801ad86: 4682 mov sl, r0
|
|
801ad88: 4648 mov r0, r9
|
|
801ad8a: f000 fb4f bl 801b42c <_Bfree>
|
|
801ad8e: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
801ad90: 1b5b subs r3, r3, r5
|
|
801ad92: 9309 str r3, [sp, #36] @ 0x24
|
|
801ad94: f000 80ae beq.w 801aef4 <_dtoa_r+0x8fc>
|
|
801ad98: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
801ad9a: 4651 mov r1, sl
|
|
801ad9c: 4648 mov r0, r9
|
|
801ad9e: f000 fd03 bl 801b7a8 <__pow5mult>
|
|
801ada2: 9001 str r0, [sp, #4]
|
|
801ada4: 2101 movs r1, #1
|
|
801ada6: 4648 mov r0, r9
|
|
801ada8: f000 fc3e bl 801b628 <__i2b>
|
|
801adac: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
801adae: 4605 mov r5, r0
|
|
801adb0: 2b00 cmp r3, #0
|
|
801adb2: f000 81d7 beq.w 801b164 <_dtoa_r+0xb6c>
|
|
801adb6: 461a mov r2, r3
|
|
801adb8: 4601 mov r1, r0
|
|
801adba: 4648 mov r0, r9
|
|
801adbc: f000 fcf4 bl 801b7a8 <__pow5mult>
|
|
801adc0: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801adc2: 2b01 cmp r3, #1
|
|
801adc4: 4605 mov r5, r0
|
|
801adc6: f300 809d bgt.w 801af04 <_dtoa_r+0x90c>
|
|
801adca: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
801adcc: 2b00 cmp r3, #0
|
|
801adce: f040 8094 bne.w 801aefa <_dtoa_r+0x902>
|
|
801add2: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801add4: f3c3 0313 ubfx r3, r3, #0, #20
|
|
801add8: 2b00 cmp r3, #0
|
|
801adda: f040 808e bne.w 801aefa <_dtoa_r+0x902>
|
|
801adde: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801ade0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
801ade4: 0d1b lsrs r3, r3, #20
|
|
801ade6: 051b lsls r3, r3, #20
|
|
801ade8: 2b00 cmp r3, #0
|
|
801adea: f000 8089 beq.w 801af00 <_dtoa_r+0x908>
|
|
801adee: 9b08 ldr r3, [sp, #32]
|
|
801adf0: 3301 adds r3, #1
|
|
801adf2: 3701 adds r7, #1
|
|
801adf4: 9308 str r3, [sp, #32]
|
|
801adf6: f04f 0a01 mov.w sl, #1
|
|
801adfa: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
801adfc: 2b00 cmp r3, #0
|
|
801adfe: f000 81b7 beq.w 801b170 <_dtoa_r+0xb78>
|
|
801ae02: 692b ldr r3, [r5, #16]
|
|
801ae04: eb05 0383 add.w r3, r5, r3, lsl #2
|
|
801ae08: 6918 ldr r0, [r3, #16]
|
|
801ae0a: f000 fbc1 bl 801b590 <__hi0bits>
|
|
801ae0e: f1c0 0020 rsb r0, r0, #32
|
|
801ae12: 9b08 ldr r3, [sp, #32]
|
|
801ae14: 4418 add r0, r3
|
|
801ae16: f010 001f ands.w r0, r0, #31
|
|
801ae1a: d07e beq.n 801af1a <_dtoa_r+0x922>
|
|
801ae1c: f1c0 0320 rsb r3, r0, #32
|
|
801ae20: 2b04 cmp r3, #4
|
|
801ae22: dd72 ble.n 801af0a <_dtoa_r+0x912>
|
|
801ae24: 9b08 ldr r3, [sp, #32]
|
|
801ae26: f1c0 001c rsb r0, r0, #28
|
|
801ae2a: 4403 add r3, r0
|
|
801ae2c: 4407 add r7, r0
|
|
801ae2e: 4406 add r6, r0
|
|
801ae30: 9308 str r3, [sp, #32]
|
|
801ae32: 2f00 cmp r7, #0
|
|
801ae34: dd05 ble.n 801ae42 <_dtoa_r+0x84a>
|
|
801ae36: 9901 ldr r1, [sp, #4]
|
|
801ae38: 463a mov r2, r7
|
|
801ae3a: 4648 mov r0, r9
|
|
801ae3c: f000 fd10 bl 801b860 <__lshift>
|
|
801ae40: 9001 str r0, [sp, #4]
|
|
801ae42: 9b08 ldr r3, [sp, #32]
|
|
801ae44: 2b00 cmp r3, #0
|
|
801ae46: dd05 ble.n 801ae54 <_dtoa_r+0x85c>
|
|
801ae48: 4629 mov r1, r5
|
|
801ae4a: 461a mov r2, r3
|
|
801ae4c: 4648 mov r0, r9
|
|
801ae4e: f000 fd07 bl 801b860 <__lshift>
|
|
801ae52: 4605 mov r5, r0
|
|
801ae54: 9b12 ldr r3, [sp, #72] @ 0x48
|
|
801ae56: 2b00 cmp r3, #0
|
|
801ae58: d061 beq.n 801af1e <_dtoa_r+0x926>
|
|
801ae5a: 9801 ldr r0, [sp, #4]
|
|
801ae5c: 4629 mov r1, r5
|
|
801ae5e: f000 fd6d bl 801b93c <__mcmp>
|
|
801ae62: 2800 cmp r0, #0
|
|
801ae64: da5b bge.n 801af1e <_dtoa_r+0x926>
|
|
801ae66: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff
|
|
801ae6a: 9302 str r3, [sp, #8]
|
|
801ae6c: 9901 ldr r1, [sp, #4]
|
|
801ae6e: 2300 movs r3, #0
|
|
801ae70: 220a movs r2, #10
|
|
801ae72: 4648 mov r0, r9
|
|
801ae74: f000 fafc bl 801b470 <__multadd>
|
|
801ae78: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
801ae7a: 9001 str r0, [sp, #4]
|
|
801ae7c: 2b00 cmp r3, #0
|
|
801ae7e: f000 8179 beq.w 801b174 <_dtoa_r+0xb7c>
|
|
801ae82: 2300 movs r3, #0
|
|
801ae84: 4621 mov r1, r4
|
|
801ae86: 220a movs r2, #10
|
|
801ae88: 4648 mov r0, r9
|
|
801ae8a: f000 faf1 bl 801b470 <__multadd>
|
|
801ae8e: 9b05 ldr r3, [sp, #20]
|
|
801ae90: 2b00 cmp r3, #0
|
|
801ae92: 4604 mov r4, r0
|
|
801ae94: dc72 bgt.n 801af7c <_dtoa_r+0x984>
|
|
801ae96: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801ae98: 2b02 cmp r3, #2
|
|
801ae9a: dc49 bgt.n 801af30 <_dtoa_r+0x938>
|
|
801ae9c: e06e b.n 801af7c <_dtoa_r+0x984>
|
|
801ae9e: 9b16 ldr r3, [sp, #88] @ 0x58
|
|
801aea0: f1c3 0336 rsb r3, r3, #54 @ 0x36
|
|
801aea4: e743 b.n 801ad2e <_dtoa_r+0x736>
|
|
801aea6: 9b04 ldr r3, [sp, #16]
|
|
801aea8: 1e5d subs r5, r3, #1
|
|
801aeaa: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
801aeac: 42ab cmp r3, r5
|
|
801aeae: db0d blt.n 801aecc <_dtoa_r+0x8d4>
|
|
801aeb0: 1b5d subs r5, r3, r5
|
|
801aeb2: 9b04 ldr r3, [sp, #16]
|
|
801aeb4: 2b00 cmp r3, #0
|
|
801aeb6: f6bf af3b bge.w 801ad30 <_dtoa_r+0x738>
|
|
801aeba: 9b04 ldr r3, [sp, #16]
|
|
801aebc: 1afe subs r6, r7, r3
|
|
801aebe: 2300 movs r3, #0
|
|
801aec0: e737 b.n 801ad32 <_dtoa_r+0x73a>
|
|
801aec2: bf00 nop
|
|
801aec4: 3fe00000 .word 0x3fe00000
|
|
801aec8: 40240000 .word 0x40240000
|
|
801aecc: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
801aece: 9a0d ldr r2, [sp, #52] @ 0x34
|
|
801aed0: 9509 str r5, [sp, #36] @ 0x24
|
|
801aed2: 1aeb subs r3, r5, r3
|
|
801aed4: 441a add r2, r3
|
|
801aed6: 920d str r2, [sp, #52] @ 0x34
|
|
801aed8: 9b04 ldr r3, [sp, #16]
|
|
801aeda: 463e mov r6, r7
|
|
801aedc: 2500 movs r5, #0
|
|
801aede: e728 b.n 801ad32 <_dtoa_r+0x73a>
|
|
801aee0: 9d09 ldr r5, [sp, #36] @ 0x24
|
|
801aee2: 9c0b ldr r4, [sp, #44] @ 0x2c
|
|
801aee4: 463e mov r6, r7
|
|
801aee6: e72d b.n 801ad44 <_dtoa_r+0x74c>
|
|
801aee8: f8dd a004 ldr.w sl, [sp, #4]
|
|
801aeec: e754 b.n 801ad98 <_dtoa_r+0x7a0>
|
|
801aeee: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
801aef0: 9901 ldr r1, [sp, #4]
|
|
801aef2: e753 b.n 801ad9c <_dtoa_r+0x7a4>
|
|
801aef4: f8cd a004 str.w sl, [sp, #4]
|
|
801aef8: e754 b.n 801ada4 <_dtoa_r+0x7ac>
|
|
801aefa: f04f 0a00 mov.w sl, #0
|
|
801aefe: e77c b.n 801adfa <_dtoa_r+0x802>
|
|
801af00: 469a mov sl, r3
|
|
801af02: e77a b.n 801adfa <_dtoa_r+0x802>
|
|
801af04: f04f 0a00 mov.w sl, #0
|
|
801af08: e77b b.n 801ae02 <_dtoa_r+0x80a>
|
|
801af0a: d092 beq.n 801ae32 <_dtoa_r+0x83a>
|
|
801af0c: 9a08 ldr r2, [sp, #32]
|
|
801af0e: 331c adds r3, #28
|
|
801af10: 441a add r2, r3
|
|
801af12: 441f add r7, r3
|
|
801af14: 441e add r6, r3
|
|
801af16: 9208 str r2, [sp, #32]
|
|
801af18: e78b b.n 801ae32 <_dtoa_r+0x83a>
|
|
801af1a: 4603 mov r3, r0
|
|
801af1c: e7f6 b.n 801af0c <_dtoa_r+0x914>
|
|
801af1e: 9b04 ldr r3, [sp, #16]
|
|
801af20: f8cd 8008 str.w r8, [sp, #8]
|
|
801af24: 2b00 cmp r3, #0
|
|
801af26: dc23 bgt.n 801af70 <_dtoa_r+0x978>
|
|
801af28: 9305 str r3, [sp, #20]
|
|
801af2a: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801af2c: 2b02 cmp r3, #2
|
|
801af2e: dd21 ble.n 801af74 <_dtoa_r+0x97c>
|
|
801af30: 9b05 ldr r3, [sp, #20]
|
|
801af32: 2b00 cmp r3, #0
|
|
801af34: f47f adb0 bne.w 801aa98 <_dtoa_r+0x4a0>
|
|
801af38: 4629 mov r1, r5
|
|
801af3a: 2205 movs r2, #5
|
|
801af3c: 4648 mov r0, r9
|
|
801af3e: f000 fa97 bl 801b470 <__multadd>
|
|
801af42: 4601 mov r1, r0
|
|
801af44: 4605 mov r5, r0
|
|
801af46: 9801 ldr r0, [sp, #4]
|
|
801af48: f000 fcf8 bl 801b93c <__mcmp>
|
|
801af4c: 2800 cmp r0, #0
|
|
801af4e: f77f ada3 ble.w 801aa98 <_dtoa_r+0x4a0>
|
|
801af52: 9e00 ldr r6, [sp, #0]
|
|
801af54: 2331 movs r3, #49 @ 0x31
|
|
801af56: f806 3b01 strb.w r3, [r6], #1
|
|
801af5a: 9b02 ldr r3, [sp, #8]
|
|
801af5c: 3301 adds r3, #1
|
|
801af5e: 9302 str r3, [sp, #8]
|
|
801af60: e59e b.n 801aaa0 <_dtoa_r+0x4a8>
|
|
801af62: 4635 mov r5, r6
|
|
801af64: 462c mov r4, r5
|
|
801af66: e7f4 b.n 801af52 <_dtoa_r+0x95a>
|
|
801af68: 9d04 ldr r5, [sp, #16]
|
|
801af6a: f8cd 8008 str.w r8, [sp, #8]
|
|
801af6e: e7f9 b.n 801af64 <_dtoa_r+0x96c>
|
|
801af70: 9b04 ldr r3, [sp, #16]
|
|
801af72: 9305 str r3, [sp, #20]
|
|
801af74: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
801af76: 2b00 cmp r3, #0
|
|
801af78: f000 8100 beq.w 801b17c <_dtoa_r+0xb84>
|
|
801af7c: 2e00 cmp r6, #0
|
|
801af7e: dd05 ble.n 801af8c <_dtoa_r+0x994>
|
|
801af80: 4621 mov r1, r4
|
|
801af82: 4632 mov r2, r6
|
|
801af84: 4648 mov r0, r9
|
|
801af86: f000 fc6b bl 801b860 <__lshift>
|
|
801af8a: 4604 mov r4, r0
|
|
801af8c: f1ba 0f00 cmp.w sl, #0
|
|
801af90: d05a beq.n 801b048 <_dtoa_r+0xa50>
|
|
801af92: 6861 ldr r1, [r4, #4]
|
|
801af94: 4648 mov r0, r9
|
|
801af96: f000 fa0b bl 801b3b0 <_Balloc>
|
|
801af9a: 4606 mov r6, r0
|
|
801af9c: b928 cbnz r0, 801afaa <_dtoa_r+0x9b2>
|
|
801af9e: 4b82 ldr r3, [pc, #520] @ (801b1a8 <_dtoa_r+0xbb0>)
|
|
801afa0: 4602 mov r2, r0
|
|
801afa2: f240 21ef movw r1, #751 @ 0x2ef
|
|
801afa6: f7ff bb3e b.w 801a626 <_dtoa_r+0x2e>
|
|
801afaa: 6922 ldr r2, [r4, #16]
|
|
801afac: 3202 adds r2, #2
|
|
801afae: 0092 lsls r2, r2, #2
|
|
801afb0: f104 010c add.w r1, r4, #12
|
|
801afb4: 300c adds r0, #12
|
|
801afb6: f7ff fa82 bl 801a4be <memcpy>
|
|
801afba: 2201 movs r2, #1
|
|
801afbc: 4631 mov r1, r6
|
|
801afbe: 4648 mov r0, r9
|
|
801afc0: f000 fc4e bl 801b860 <__lshift>
|
|
801afc4: 4607 mov r7, r0
|
|
801afc6: 9b00 ldr r3, [sp, #0]
|
|
801afc8: 9a00 ldr r2, [sp, #0]
|
|
801afca: f103 0b01 add.w fp, r3, #1
|
|
801afce: 9b05 ldr r3, [sp, #20]
|
|
801afd0: 4413 add r3, r2
|
|
801afd2: 9306 str r3, [sp, #24]
|
|
801afd4: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
801afd6: f003 0301 and.w r3, r3, #1
|
|
801afda: 9308 str r3, [sp, #32]
|
|
801afdc: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff
|
|
801afe0: 4629 mov r1, r5
|
|
801afe2: 9801 ldr r0, [sp, #4]
|
|
801afe4: 9304 str r3, [sp, #16]
|
|
801afe6: f7ff fa7f bl 801a4e8 <quorem>
|
|
801afea: 4621 mov r1, r4
|
|
801afec: 9005 str r0, [sp, #20]
|
|
801afee: f100 0a30 add.w sl, r0, #48 @ 0x30
|
|
801aff2: 9801 ldr r0, [sp, #4]
|
|
801aff4: f000 fca2 bl 801b93c <__mcmp>
|
|
801aff8: 463a mov r2, r7
|
|
801affa: 4680 mov r8, r0
|
|
801affc: 4629 mov r1, r5
|
|
801affe: 4648 mov r0, r9
|
|
801b000: f000 fcb8 bl 801b974 <__mdiff>
|
|
801b004: 68c2 ldr r2, [r0, #12]
|
|
801b006: 4606 mov r6, r0
|
|
801b008: bb02 cbnz r2, 801b04c <_dtoa_r+0xa54>
|
|
801b00a: 4601 mov r1, r0
|
|
801b00c: 9801 ldr r0, [sp, #4]
|
|
801b00e: f000 fc95 bl 801b93c <__mcmp>
|
|
801b012: 4602 mov r2, r0
|
|
801b014: 4631 mov r1, r6
|
|
801b016: 4648 mov r0, r9
|
|
801b018: 9209 str r2, [sp, #36] @ 0x24
|
|
801b01a: f000 fa07 bl 801b42c <_Bfree>
|
|
801b01e: e9dd 2309 ldrd r2, r3, [sp, #36] @ 0x24
|
|
801b022: ea42 0103 orr.w r1, r2, r3
|
|
801b026: 9b08 ldr r3, [sp, #32]
|
|
801b028: 4319 orrs r1, r3
|
|
801b02a: 465e mov r6, fp
|
|
801b02c: d110 bne.n 801b050 <_dtoa_r+0xa58>
|
|
801b02e: f1ba 0f39 cmp.w sl, #57 @ 0x39
|
|
801b032: d02b beq.n 801b08c <_dtoa_r+0xa94>
|
|
801b034: f1b8 0f00 cmp.w r8, #0
|
|
801b038: dd02 ble.n 801b040 <_dtoa_r+0xa48>
|
|
801b03a: 9b05 ldr r3, [sp, #20]
|
|
801b03c: f103 0a31 add.w sl, r3, #49 @ 0x31
|
|
801b040: 9b04 ldr r3, [sp, #16]
|
|
801b042: f883 a000 strb.w sl, [r3]
|
|
801b046: e52d b.n 801aaa4 <_dtoa_r+0x4ac>
|
|
801b048: 4627 mov r7, r4
|
|
801b04a: e7bc b.n 801afc6 <_dtoa_r+0x9ce>
|
|
801b04c: 2201 movs r2, #1
|
|
801b04e: e7e1 b.n 801b014 <_dtoa_r+0xa1c>
|
|
801b050: f1b8 0f00 cmp.w r8, #0
|
|
801b054: db06 blt.n 801b064 <_dtoa_r+0xa6c>
|
|
801b056: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801b058: ea48 0803 orr.w r8, r8, r3
|
|
801b05c: 9b08 ldr r3, [sp, #32]
|
|
801b05e: ea58 0803 orrs.w r8, r8, r3
|
|
801b062: d120 bne.n 801b0a6 <_dtoa_r+0xaae>
|
|
801b064: 2a00 cmp r2, #0
|
|
801b066: ddeb ble.n 801b040 <_dtoa_r+0xa48>
|
|
801b068: 9901 ldr r1, [sp, #4]
|
|
801b06a: 2201 movs r2, #1
|
|
801b06c: 4648 mov r0, r9
|
|
801b06e: f000 fbf7 bl 801b860 <__lshift>
|
|
801b072: 4629 mov r1, r5
|
|
801b074: 9001 str r0, [sp, #4]
|
|
801b076: f000 fc61 bl 801b93c <__mcmp>
|
|
801b07a: 2800 cmp r0, #0
|
|
801b07c: dc03 bgt.n 801b086 <_dtoa_r+0xa8e>
|
|
801b07e: d1df bne.n 801b040 <_dtoa_r+0xa48>
|
|
801b080: f01a 0f01 tst.w sl, #1
|
|
801b084: d0dc beq.n 801b040 <_dtoa_r+0xa48>
|
|
801b086: f1ba 0f39 cmp.w sl, #57 @ 0x39
|
|
801b08a: d1d6 bne.n 801b03a <_dtoa_r+0xa42>
|
|
801b08c: 9a04 ldr r2, [sp, #16]
|
|
801b08e: 2339 movs r3, #57 @ 0x39
|
|
801b090: 7013 strb r3, [r2, #0]
|
|
801b092: 4633 mov r3, r6
|
|
801b094: 461e mov r6, r3
|
|
801b096: 3b01 subs r3, #1
|
|
801b098: f816 2c01 ldrb.w r2, [r6, #-1]
|
|
801b09c: 2a39 cmp r2, #57 @ 0x39
|
|
801b09e: d052 beq.n 801b146 <_dtoa_r+0xb4e>
|
|
801b0a0: 3201 adds r2, #1
|
|
801b0a2: 701a strb r2, [r3, #0]
|
|
801b0a4: e4fe b.n 801aaa4 <_dtoa_r+0x4ac>
|
|
801b0a6: 2a00 cmp r2, #0
|
|
801b0a8: dd07 ble.n 801b0ba <_dtoa_r+0xac2>
|
|
801b0aa: f1ba 0f39 cmp.w sl, #57 @ 0x39
|
|
801b0ae: d0ed beq.n 801b08c <_dtoa_r+0xa94>
|
|
801b0b0: 9a04 ldr r2, [sp, #16]
|
|
801b0b2: f10a 0301 add.w r3, sl, #1
|
|
801b0b6: 7013 strb r3, [r2, #0]
|
|
801b0b8: e4f4 b.n 801aaa4 <_dtoa_r+0x4ac>
|
|
801b0ba: 9b06 ldr r3, [sp, #24]
|
|
801b0bc: f80b ac01 strb.w sl, [fp, #-1]
|
|
801b0c0: 455b cmp r3, fp
|
|
801b0c2: d02a beq.n 801b11a <_dtoa_r+0xb22>
|
|
801b0c4: 9901 ldr r1, [sp, #4]
|
|
801b0c6: 2300 movs r3, #0
|
|
801b0c8: 220a movs r2, #10
|
|
801b0ca: 4648 mov r0, r9
|
|
801b0cc: f000 f9d0 bl 801b470 <__multadd>
|
|
801b0d0: 42bc cmp r4, r7
|
|
801b0d2: 9001 str r0, [sp, #4]
|
|
801b0d4: f04f 0300 mov.w r3, #0
|
|
801b0d8: f04f 020a mov.w r2, #10
|
|
801b0dc: 4621 mov r1, r4
|
|
801b0de: 4648 mov r0, r9
|
|
801b0e0: d106 bne.n 801b0f0 <_dtoa_r+0xaf8>
|
|
801b0e2: f000 f9c5 bl 801b470 <__multadd>
|
|
801b0e6: 4604 mov r4, r0
|
|
801b0e8: 4607 mov r7, r0
|
|
801b0ea: f10b 0b01 add.w fp, fp, #1
|
|
801b0ee: e775 b.n 801afdc <_dtoa_r+0x9e4>
|
|
801b0f0: f000 f9be bl 801b470 <__multadd>
|
|
801b0f4: 4639 mov r1, r7
|
|
801b0f6: 4604 mov r4, r0
|
|
801b0f8: 2300 movs r3, #0
|
|
801b0fa: 220a movs r2, #10
|
|
801b0fc: 4648 mov r0, r9
|
|
801b0fe: f000 f9b7 bl 801b470 <__multadd>
|
|
801b102: 4607 mov r7, r0
|
|
801b104: e7f1 b.n 801b0ea <_dtoa_r+0xaf2>
|
|
801b106: 9b05 ldr r3, [sp, #20]
|
|
801b108: 1e5e subs r6, r3, #1
|
|
801b10a: 2b00 cmp r3, #0
|
|
801b10c: 9b00 ldr r3, [sp, #0]
|
|
801b10e: bfd8 it le
|
|
801b110: 2600 movle r6, #0
|
|
801b112: 1c5a adds r2, r3, #1
|
|
801b114: 4627 mov r7, r4
|
|
801b116: 4416 add r6, r2
|
|
801b118: 2400 movs r4, #0
|
|
801b11a: 9901 ldr r1, [sp, #4]
|
|
801b11c: 2201 movs r2, #1
|
|
801b11e: 4648 mov r0, r9
|
|
801b120: f000 fb9e bl 801b860 <__lshift>
|
|
801b124: 4629 mov r1, r5
|
|
801b126: 9001 str r0, [sp, #4]
|
|
801b128: f000 fc08 bl 801b93c <__mcmp>
|
|
801b12c: 2800 cmp r0, #0
|
|
801b12e: dcb0 bgt.n 801b092 <_dtoa_r+0xa9a>
|
|
801b130: d102 bne.n 801b138 <_dtoa_r+0xb40>
|
|
801b132: f01a 0f01 tst.w sl, #1
|
|
801b136: d1ac bne.n 801b092 <_dtoa_r+0xa9a>
|
|
801b138: 4633 mov r3, r6
|
|
801b13a: 461e mov r6, r3
|
|
801b13c: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
801b140: 2a30 cmp r2, #48 @ 0x30
|
|
801b142: d0fa beq.n 801b13a <_dtoa_r+0xb42>
|
|
801b144: e4ae b.n 801aaa4 <_dtoa_r+0x4ac>
|
|
801b146: 9a00 ldr r2, [sp, #0]
|
|
801b148: 429a cmp r2, r3
|
|
801b14a: d1a3 bne.n 801b094 <_dtoa_r+0xa9c>
|
|
801b14c: 9b02 ldr r3, [sp, #8]
|
|
801b14e: 3301 adds r3, #1
|
|
801b150: 9302 str r3, [sp, #8]
|
|
801b152: 2331 movs r3, #49 @ 0x31
|
|
801b154: e7af b.n 801b0b6 <_dtoa_r+0xabe>
|
|
801b156: 9b23 ldr r3, [sp, #140] @ 0x8c
|
|
801b158: 2b00 cmp r3, #0
|
|
801b15a: f47f aa98 bne.w 801a68e <_dtoa_r+0x96>
|
|
801b15e: 4b13 ldr r3, [pc, #76] @ (801b1ac <_dtoa_r+0xbb4>)
|
|
801b160: f7ff bab7 b.w 801a6d2 <_dtoa_r+0xda>
|
|
801b164: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801b166: 2b01 cmp r3, #1
|
|
801b168: f77f ae2f ble.w 801adca <_dtoa_r+0x7d2>
|
|
801b16c: f8dd a034 ldr.w sl, [sp, #52] @ 0x34
|
|
801b170: 2001 movs r0, #1
|
|
801b172: e64e b.n 801ae12 <_dtoa_r+0x81a>
|
|
801b174: 9b05 ldr r3, [sp, #20]
|
|
801b176: 2b00 cmp r3, #0
|
|
801b178: f77f aed7 ble.w 801af2a <_dtoa_r+0x932>
|
|
801b17c: 9e00 ldr r6, [sp, #0]
|
|
801b17e: 9801 ldr r0, [sp, #4]
|
|
801b180: 4629 mov r1, r5
|
|
801b182: f7ff f9b1 bl 801a4e8 <quorem>
|
|
801b186: f100 0a30 add.w sl, r0, #48 @ 0x30
|
|
801b18a: 9b00 ldr r3, [sp, #0]
|
|
801b18c: f806 ab01 strb.w sl, [r6], #1
|
|
801b190: 1af2 subs r2, r6, r3
|
|
801b192: 9b05 ldr r3, [sp, #20]
|
|
801b194: 4293 cmp r3, r2
|
|
801b196: ddb6 ble.n 801b106 <_dtoa_r+0xb0e>
|
|
801b198: 9901 ldr r1, [sp, #4]
|
|
801b19a: 2300 movs r3, #0
|
|
801b19c: 220a movs r2, #10
|
|
801b19e: 4648 mov r0, r9
|
|
801b1a0: f000 f966 bl 801b470 <__multadd>
|
|
801b1a4: 9001 str r0, [sp, #4]
|
|
801b1a6: e7ea b.n 801b17e <_dtoa_r+0xb86>
|
|
801b1a8: 0801e6c5 .word 0x0801e6c5
|
|
801b1ac: 0801e649 .word 0x0801e649
|
|
|
|
0801b1b0 <_free_r>:
|
|
801b1b0: b538 push {r3, r4, r5, lr}
|
|
801b1b2: 4605 mov r5, r0
|
|
801b1b4: 2900 cmp r1, #0
|
|
801b1b6: d041 beq.n 801b23c <_free_r+0x8c>
|
|
801b1b8: f851 3c04 ldr.w r3, [r1, #-4]
|
|
801b1bc: 1f0c subs r4, r1, #4
|
|
801b1be: 2b00 cmp r3, #0
|
|
801b1c0: bfb8 it lt
|
|
801b1c2: 18e4 addlt r4, r4, r3
|
|
801b1c4: f000 f8e8 bl 801b398 <__malloc_lock>
|
|
801b1c8: 4a1d ldr r2, [pc, #116] @ (801b240 <_free_r+0x90>)
|
|
801b1ca: 6813 ldr r3, [r2, #0]
|
|
801b1cc: b933 cbnz r3, 801b1dc <_free_r+0x2c>
|
|
801b1ce: 6063 str r3, [r4, #4]
|
|
801b1d0: 6014 str r4, [r2, #0]
|
|
801b1d2: 4628 mov r0, r5
|
|
801b1d4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
801b1d8: f000 b8e4 b.w 801b3a4 <__malloc_unlock>
|
|
801b1dc: 42a3 cmp r3, r4
|
|
801b1de: d908 bls.n 801b1f2 <_free_r+0x42>
|
|
801b1e0: 6820 ldr r0, [r4, #0]
|
|
801b1e2: 1821 adds r1, r4, r0
|
|
801b1e4: 428b cmp r3, r1
|
|
801b1e6: bf01 itttt eq
|
|
801b1e8: 6819 ldreq r1, [r3, #0]
|
|
801b1ea: 685b ldreq r3, [r3, #4]
|
|
801b1ec: 1809 addeq r1, r1, r0
|
|
801b1ee: 6021 streq r1, [r4, #0]
|
|
801b1f0: e7ed b.n 801b1ce <_free_r+0x1e>
|
|
801b1f2: 461a mov r2, r3
|
|
801b1f4: 685b ldr r3, [r3, #4]
|
|
801b1f6: b10b cbz r3, 801b1fc <_free_r+0x4c>
|
|
801b1f8: 42a3 cmp r3, r4
|
|
801b1fa: d9fa bls.n 801b1f2 <_free_r+0x42>
|
|
801b1fc: 6811 ldr r1, [r2, #0]
|
|
801b1fe: 1850 adds r0, r2, r1
|
|
801b200: 42a0 cmp r0, r4
|
|
801b202: d10b bne.n 801b21c <_free_r+0x6c>
|
|
801b204: 6820 ldr r0, [r4, #0]
|
|
801b206: 4401 add r1, r0
|
|
801b208: 1850 adds r0, r2, r1
|
|
801b20a: 4283 cmp r3, r0
|
|
801b20c: 6011 str r1, [r2, #0]
|
|
801b20e: d1e0 bne.n 801b1d2 <_free_r+0x22>
|
|
801b210: 6818 ldr r0, [r3, #0]
|
|
801b212: 685b ldr r3, [r3, #4]
|
|
801b214: 6053 str r3, [r2, #4]
|
|
801b216: 4408 add r0, r1
|
|
801b218: 6010 str r0, [r2, #0]
|
|
801b21a: e7da b.n 801b1d2 <_free_r+0x22>
|
|
801b21c: d902 bls.n 801b224 <_free_r+0x74>
|
|
801b21e: 230c movs r3, #12
|
|
801b220: 602b str r3, [r5, #0]
|
|
801b222: e7d6 b.n 801b1d2 <_free_r+0x22>
|
|
801b224: 6820 ldr r0, [r4, #0]
|
|
801b226: 1821 adds r1, r4, r0
|
|
801b228: 428b cmp r3, r1
|
|
801b22a: bf04 itt eq
|
|
801b22c: 6819 ldreq r1, [r3, #0]
|
|
801b22e: 685b ldreq r3, [r3, #4]
|
|
801b230: 6063 str r3, [r4, #4]
|
|
801b232: bf04 itt eq
|
|
801b234: 1809 addeq r1, r1, r0
|
|
801b236: 6021 streq r1, [r4, #0]
|
|
801b238: 6054 str r4, [r2, #4]
|
|
801b23a: e7ca b.n 801b1d2 <_free_r+0x22>
|
|
801b23c: bd38 pop {r3, r4, r5, pc}
|
|
801b23e: bf00 nop
|
|
801b240: 20013ce4 .word 0x20013ce4
|
|
|
|
0801b244 <malloc>:
|
|
801b244: 4b02 ldr r3, [pc, #8] @ (801b250 <malloc+0xc>)
|
|
801b246: 4601 mov r1, r0
|
|
801b248: 6818 ldr r0, [r3, #0]
|
|
801b24a: f000 b825 b.w 801b298 <_malloc_r>
|
|
801b24e: bf00 nop
|
|
801b250: 2000011c .word 0x2000011c
|
|
|
|
0801b254 <sbrk_aligned>:
|
|
801b254: b570 push {r4, r5, r6, lr}
|
|
801b256: 4e0f ldr r6, [pc, #60] @ (801b294 <sbrk_aligned+0x40>)
|
|
801b258: 460c mov r4, r1
|
|
801b25a: 6831 ldr r1, [r6, #0]
|
|
801b25c: 4605 mov r5, r0
|
|
801b25e: b911 cbnz r1, 801b266 <sbrk_aligned+0x12>
|
|
801b260: f001 ffda bl 801d218 <_sbrk_r>
|
|
801b264: 6030 str r0, [r6, #0]
|
|
801b266: 4621 mov r1, r4
|
|
801b268: 4628 mov r0, r5
|
|
801b26a: f001 ffd5 bl 801d218 <_sbrk_r>
|
|
801b26e: 1c43 adds r3, r0, #1
|
|
801b270: d103 bne.n 801b27a <sbrk_aligned+0x26>
|
|
801b272: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
|
|
801b276: 4620 mov r0, r4
|
|
801b278: bd70 pop {r4, r5, r6, pc}
|
|
801b27a: 1cc4 adds r4, r0, #3
|
|
801b27c: f024 0403 bic.w r4, r4, #3
|
|
801b280: 42a0 cmp r0, r4
|
|
801b282: d0f8 beq.n 801b276 <sbrk_aligned+0x22>
|
|
801b284: 1a21 subs r1, r4, r0
|
|
801b286: 4628 mov r0, r5
|
|
801b288: f001 ffc6 bl 801d218 <_sbrk_r>
|
|
801b28c: 3001 adds r0, #1
|
|
801b28e: d1f2 bne.n 801b276 <sbrk_aligned+0x22>
|
|
801b290: e7ef b.n 801b272 <sbrk_aligned+0x1e>
|
|
801b292: bf00 nop
|
|
801b294: 20013ce0 .word 0x20013ce0
|
|
|
|
0801b298 <_malloc_r>:
|
|
801b298: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
801b29c: 1ccd adds r5, r1, #3
|
|
801b29e: f025 0503 bic.w r5, r5, #3
|
|
801b2a2: 3508 adds r5, #8
|
|
801b2a4: 2d0c cmp r5, #12
|
|
801b2a6: bf38 it cc
|
|
801b2a8: 250c movcc r5, #12
|
|
801b2aa: 2d00 cmp r5, #0
|
|
801b2ac: 4606 mov r6, r0
|
|
801b2ae: db01 blt.n 801b2b4 <_malloc_r+0x1c>
|
|
801b2b0: 42a9 cmp r1, r5
|
|
801b2b2: d904 bls.n 801b2be <_malloc_r+0x26>
|
|
801b2b4: 230c movs r3, #12
|
|
801b2b6: 6033 str r3, [r6, #0]
|
|
801b2b8: 2000 movs r0, #0
|
|
801b2ba: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
801b2be: f8df 80d4 ldr.w r8, [pc, #212] @ 801b394 <_malloc_r+0xfc>
|
|
801b2c2: f000 f869 bl 801b398 <__malloc_lock>
|
|
801b2c6: f8d8 3000 ldr.w r3, [r8]
|
|
801b2ca: 461c mov r4, r3
|
|
801b2cc: bb44 cbnz r4, 801b320 <_malloc_r+0x88>
|
|
801b2ce: 4629 mov r1, r5
|
|
801b2d0: 4630 mov r0, r6
|
|
801b2d2: f7ff ffbf bl 801b254 <sbrk_aligned>
|
|
801b2d6: 1c43 adds r3, r0, #1
|
|
801b2d8: 4604 mov r4, r0
|
|
801b2da: d158 bne.n 801b38e <_malloc_r+0xf6>
|
|
801b2dc: f8d8 4000 ldr.w r4, [r8]
|
|
801b2e0: 4627 mov r7, r4
|
|
801b2e2: 2f00 cmp r7, #0
|
|
801b2e4: d143 bne.n 801b36e <_malloc_r+0xd6>
|
|
801b2e6: 2c00 cmp r4, #0
|
|
801b2e8: d04b beq.n 801b382 <_malloc_r+0xea>
|
|
801b2ea: 6823 ldr r3, [r4, #0]
|
|
801b2ec: 4639 mov r1, r7
|
|
801b2ee: 4630 mov r0, r6
|
|
801b2f0: eb04 0903 add.w r9, r4, r3
|
|
801b2f4: f001 ff90 bl 801d218 <_sbrk_r>
|
|
801b2f8: 4581 cmp r9, r0
|
|
801b2fa: d142 bne.n 801b382 <_malloc_r+0xea>
|
|
801b2fc: 6821 ldr r1, [r4, #0]
|
|
801b2fe: 1a6d subs r5, r5, r1
|
|
801b300: 4629 mov r1, r5
|
|
801b302: 4630 mov r0, r6
|
|
801b304: f7ff ffa6 bl 801b254 <sbrk_aligned>
|
|
801b308: 3001 adds r0, #1
|
|
801b30a: d03a beq.n 801b382 <_malloc_r+0xea>
|
|
801b30c: 6823 ldr r3, [r4, #0]
|
|
801b30e: 442b add r3, r5
|
|
801b310: 6023 str r3, [r4, #0]
|
|
801b312: f8d8 3000 ldr.w r3, [r8]
|
|
801b316: 685a ldr r2, [r3, #4]
|
|
801b318: bb62 cbnz r2, 801b374 <_malloc_r+0xdc>
|
|
801b31a: f8c8 7000 str.w r7, [r8]
|
|
801b31e: e00f b.n 801b340 <_malloc_r+0xa8>
|
|
801b320: 6822 ldr r2, [r4, #0]
|
|
801b322: 1b52 subs r2, r2, r5
|
|
801b324: d420 bmi.n 801b368 <_malloc_r+0xd0>
|
|
801b326: 2a0b cmp r2, #11
|
|
801b328: d917 bls.n 801b35a <_malloc_r+0xc2>
|
|
801b32a: 1961 adds r1, r4, r5
|
|
801b32c: 42a3 cmp r3, r4
|
|
801b32e: 6025 str r5, [r4, #0]
|
|
801b330: bf18 it ne
|
|
801b332: 6059 strne r1, [r3, #4]
|
|
801b334: 6863 ldr r3, [r4, #4]
|
|
801b336: bf08 it eq
|
|
801b338: f8c8 1000 streq.w r1, [r8]
|
|
801b33c: 5162 str r2, [r4, r5]
|
|
801b33e: 604b str r3, [r1, #4]
|
|
801b340: 4630 mov r0, r6
|
|
801b342: f000 f82f bl 801b3a4 <__malloc_unlock>
|
|
801b346: f104 000b add.w r0, r4, #11
|
|
801b34a: 1d23 adds r3, r4, #4
|
|
801b34c: f020 0007 bic.w r0, r0, #7
|
|
801b350: 1ac2 subs r2, r0, r3
|
|
801b352: bf1c itt ne
|
|
801b354: 1a1b subne r3, r3, r0
|
|
801b356: 50a3 strne r3, [r4, r2]
|
|
801b358: e7af b.n 801b2ba <_malloc_r+0x22>
|
|
801b35a: 6862 ldr r2, [r4, #4]
|
|
801b35c: 42a3 cmp r3, r4
|
|
801b35e: bf0c ite eq
|
|
801b360: f8c8 2000 streq.w r2, [r8]
|
|
801b364: 605a strne r2, [r3, #4]
|
|
801b366: e7eb b.n 801b340 <_malloc_r+0xa8>
|
|
801b368: 4623 mov r3, r4
|
|
801b36a: 6864 ldr r4, [r4, #4]
|
|
801b36c: e7ae b.n 801b2cc <_malloc_r+0x34>
|
|
801b36e: 463c mov r4, r7
|
|
801b370: 687f ldr r7, [r7, #4]
|
|
801b372: e7b6 b.n 801b2e2 <_malloc_r+0x4a>
|
|
801b374: 461a mov r2, r3
|
|
801b376: 685b ldr r3, [r3, #4]
|
|
801b378: 42a3 cmp r3, r4
|
|
801b37a: d1fb bne.n 801b374 <_malloc_r+0xdc>
|
|
801b37c: 2300 movs r3, #0
|
|
801b37e: 6053 str r3, [r2, #4]
|
|
801b380: e7de b.n 801b340 <_malloc_r+0xa8>
|
|
801b382: 230c movs r3, #12
|
|
801b384: 6033 str r3, [r6, #0]
|
|
801b386: 4630 mov r0, r6
|
|
801b388: f000 f80c bl 801b3a4 <__malloc_unlock>
|
|
801b38c: e794 b.n 801b2b8 <_malloc_r+0x20>
|
|
801b38e: 6005 str r5, [r0, #0]
|
|
801b390: e7d6 b.n 801b340 <_malloc_r+0xa8>
|
|
801b392: bf00 nop
|
|
801b394: 20013ce4 .word 0x20013ce4
|
|
|
|
0801b398 <__malloc_lock>:
|
|
801b398: 4801 ldr r0, [pc, #4] @ (801b3a0 <__malloc_lock+0x8>)
|
|
801b39a: f7ff b88e b.w 801a4ba <__retarget_lock_acquire_recursive>
|
|
801b39e: bf00 nop
|
|
801b3a0: 20013cdc .word 0x20013cdc
|
|
|
|
0801b3a4 <__malloc_unlock>:
|
|
801b3a4: 4801 ldr r0, [pc, #4] @ (801b3ac <__malloc_unlock+0x8>)
|
|
801b3a6: f7ff b889 b.w 801a4bc <__retarget_lock_release_recursive>
|
|
801b3aa: bf00 nop
|
|
801b3ac: 20013cdc .word 0x20013cdc
|
|
|
|
0801b3b0 <_Balloc>:
|
|
801b3b0: b570 push {r4, r5, r6, lr}
|
|
801b3b2: 69c4 ldr r4, [r0, #28]
|
|
801b3b4: 4605 mov r5, r0
|
|
801b3b6: 460e mov r6, r1
|
|
801b3b8: b984 cbnz r4, 801b3dc <_Balloc+0x2c>
|
|
801b3ba: 2010 movs r0, #16
|
|
801b3bc: f7ff ff42 bl 801b244 <malloc>
|
|
801b3c0: 4604 mov r4, r0
|
|
801b3c2: 61e8 str r0, [r5, #28]
|
|
801b3c4: b928 cbnz r0, 801b3d2 <_Balloc+0x22>
|
|
801b3c6: 4602 mov r2, r0
|
|
801b3c8: 4b16 ldr r3, [pc, #88] @ (801b424 <_Balloc+0x74>)
|
|
801b3ca: 4817 ldr r0, [pc, #92] @ (801b428 <_Balloc+0x78>)
|
|
801b3cc: 216b movs r1, #107 @ 0x6b
|
|
801b3ce: f001 ff3b bl 801d248 <__assert_func>
|
|
801b3d2: 2300 movs r3, #0
|
|
801b3d4: e9c0 3301 strd r3, r3, [r0, #4]
|
|
801b3d8: 6003 str r3, [r0, #0]
|
|
801b3da: 60c3 str r3, [r0, #12]
|
|
801b3dc: 68e3 ldr r3, [r4, #12]
|
|
801b3de: b953 cbnz r3, 801b3f6 <_Balloc+0x46>
|
|
801b3e0: 2221 movs r2, #33 @ 0x21
|
|
801b3e2: 2104 movs r1, #4
|
|
801b3e4: 4628 mov r0, r5
|
|
801b3e6: f001 ff4d bl 801d284 <_calloc_r>
|
|
801b3ea: 69eb ldr r3, [r5, #28]
|
|
801b3ec: 60e0 str r0, [r4, #12]
|
|
801b3ee: 68db ldr r3, [r3, #12]
|
|
801b3f0: b90b cbnz r3, 801b3f6 <_Balloc+0x46>
|
|
801b3f2: 2000 movs r0, #0
|
|
801b3f4: bd70 pop {r4, r5, r6, pc}
|
|
801b3f6: f853 0026 ldr.w r0, [r3, r6, lsl #2]
|
|
801b3fa: b130 cbz r0, 801b40a <_Balloc+0x5a>
|
|
801b3fc: 6802 ldr r2, [r0, #0]
|
|
801b3fe: f843 2026 str.w r2, [r3, r6, lsl #2]
|
|
801b402: 2300 movs r3, #0
|
|
801b404: e9c0 3303 strd r3, r3, [r0, #12]
|
|
801b408: e7f4 b.n 801b3f4 <_Balloc+0x44>
|
|
801b40a: 2101 movs r1, #1
|
|
801b40c: fa01 f406 lsl.w r4, r1, r6
|
|
801b410: 1d62 adds r2, r4, #5
|
|
801b412: 0092 lsls r2, r2, #2
|
|
801b414: 4628 mov r0, r5
|
|
801b416: f001 ff35 bl 801d284 <_calloc_r>
|
|
801b41a: 2800 cmp r0, #0
|
|
801b41c: d0e9 beq.n 801b3f2 <_Balloc+0x42>
|
|
801b41e: e9c0 6401 strd r6, r4, [r0, #4]
|
|
801b422: e7ee b.n 801b402 <_Balloc+0x52>
|
|
801b424: 0801e656 .word 0x0801e656
|
|
801b428: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801b42c <_Bfree>:
|
|
801b42c: b570 push {r4, r5, r6, lr}
|
|
801b42e: 69c6 ldr r6, [r0, #28]
|
|
801b430: 4605 mov r5, r0
|
|
801b432: 460c mov r4, r1
|
|
801b434: b976 cbnz r6, 801b454 <_Bfree+0x28>
|
|
801b436: 2010 movs r0, #16
|
|
801b438: f7ff ff04 bl 801b244 <malloc>
|
|
801b43c: 4602 mov r2, r0
|
|
801b43e: 61e8 str r0, [r5, #28]
|
|
801b440: b920 cbnz r0, 801b44c <_Bfree+0x20>
|
|
801b442: 4b09 ldr r3, [pc, #36] @ (801b468 <_Bfree+0x3c>)
|
|
801b444: 4809 ldr r0, [pc, #36] @ (801b46c <_Bfree+0x40>)
|
|
801b446: 218f movs r1, #143 @ 0x8f
|
|
801b448: f001 fefe bl 801d248 <__assert_func>
|
|
801b44c: e9c0 6601 strd r6, r6, [r0, #4]
|
|
801b450: 6006 str r6, [r0, #0]
|
|
801b452: 60c6 str r6, [r0, #12]
|
|
801b454: b13c cbz r4, 801b466 <_Bfree+0x3a>
|
|
801b456: 69eb ldr r3, [r5, #28]
|
|
801b458: 6862 ldr r2, [r4, #4]
|
|
801b45a: 68db ldr r3, [r3, #12]
|
|
801b45c: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
801b460: 6021 str r1, [r4, #0]
|
|
801b462: f843 4022 str.w r4, [r3, r2, lsl #2]
|
|
801b466: bd70 pop {r4, r5, r6, pc}
|
|
801b468: 0801e656 .word 0x0801e656
|
|
801b46c: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801b470 <__multadd>:
|
|
801b470: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
801b474: 690d ldr r5, [r1, #16]
|
|
801b476: 4607 mov r7, r0
|
|
801b478: 460c mov r4, r1
|
|
801b47a: 461e mov r6, r3
|
|
801b47c: f101 0c14 add.w ip, r1, #20
|
|
801b480: 2000 movs r0, #0
|
|
801b482: f8dc 3000 ldr.w r3, [ip]
|
|
801b486: b299 uxth r1, r3
|
|
801b488: fb02 6101 mla r1, r2, r1, r6
|
|
801b48c: 0c1e lsrs r6, r3, #16
|
|
801b48e: 0c0b lsrs r3, r1, #16
|
|
801b490: fb02 3306 mla r3, r2, r6, r3
|
|
801b494: b289 uxth r1, r1
|
|
801b496: 3001 adds r0, #1
|
|
801b498: eb01 4103 add.w r1, r1, r3, lsl #16
|
|
801b49c: 4285 cmp r5, r0
|
|
801b49e: f84c 1b04 str.w r1, [ip], #4
|
|
801b4a2: ea4f 4613 mov.w r6, r3, lsr #16
|
|
801b4a6: dcec bgt.n 801b482 <__multadd+0x12>
|
|
801b4a8: b30e cbz r6, 801b4ee <__multadd+0x7e>
|
|
801b4aa: 68a3 ldr r3, [r4, #8]
|
|
801b4ac: 42ab cmp r3, r5
|
|
801b4ae: dc19 bgt.n 801b4e4 <__multadd+0x74>
|
|
801b4b0: 6861 ldr r1, [r4, #4]
|
|
801b4b2: 4638 mov r0, r7
|
|
801b4b4: 3101 adds r1, #1
|
|
801b4b6: f7ff ff7b bl 801b3b0 <_Balloc>
|
|
801b4ba: 4680 mov r8, r0
|
|
801b4bc: b928 cbnz r0, 801b4ca <__multadd+0x5a>
|
|
801b4be: 4602 mov r2, r0
|
|
801b4c0: 4b0c ldr r3, [pc, #48] @ (801b4f4 <__multadd+0x84>)
|
|
801b4c2: 480d ldr r0, [pc, #52] @ (801b4f8 <__multadd+0x88>)
|
|
801b4c4: 21ba movs r1, #186 @ 0xba
|
|
801b4c6: f001 febf bl 801d248 <__assert_func>
|
|
801b4ca: 6922 ldr r2, [r4, #16]
|
|
801b4cc: 3202 adds r2, #2
|
|
801b4ce: f104 010c add.w r1, r4, #12
|
|
801b4d2: 0092 lsls r2, r2, #2
|
|
801b4d4: 300c adds r0, #12
|
|
801b4d6: f7fe fff2 bl 801a4be <memcpy>
|
|
801b4da: 4621 mov r1, r4
|
|
801b4dc: 4638 mov r0, r7
|
|
801b4de: f7ff ffa5 bl 801b42c <_Bfree>
|
|
801b4e2: 4644 mov r4, r8
|
|
801b4e4: eb04 0385 add.w r3, r4, r5, lsl #2
|
|
801b4e8: 3501 adds r5, #1
|
|
801b4ea: 615e str r6, [r3, #20]
|
|
801b4ec: 6125 str r5, [r4, #16]
|
|
801b4ee: 4620 mov r0, r4
|
|
801b4f0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
801b4f4: 0801e6c5 .word 0x0801e6c5
|
|
801b4f8: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801b4fc <__s2b>:
|
|
801b4fc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
801b500: 460c mov r4, r1
|
|
801b502: 4615 mov r5, r2
|
|
801b504: 461f mov r7, r3
|
|
801b506: 2209 movs r2, #9
|
|
801b508: 3308 adds r3, #8
|
|
801b50a: 4606 mov r6, r0
|
|
801b50c: fb93 f3f2 sdiv r3, r3, r2
|
|
801b510: 2100 movs r1, #0
|
|
801b512: 2201 movs r2, #1
|
|
801b514: 429a cmp r2, r3
|
|
801b516: db09 blt.n 801b52c <__s2b+0x30>
|
|
801b518: 4630 mov r0, r6
|
|
801b51a: f7ff ff49 bl 801b3b0 <_Balloc>
|
|
801b51e: b940 cbnz r0, 801b532 <__s2b+0x36>
|
|
801b520: 4602 mov r2, r0
|
|
801b522: 4b19 ldr r3, [pc, #100] @ (801b588 <__s2b+0x8c>)
|
|
801b524: 4819 ldr r0, [pc, #100] @ (801b58c <__s2b+0x90>)
|
|
801b526: 21d3 movs r1, #211 @ 0xd3
|
|
801b528: f001 fe8e bl 801d248 <__assert_func>
|
|
801b52c: 0052 lsls r2, r2, #1
|
|
801b52e: 3101 adds r1, #1
|
|
801b530: e7f0 b.n 801b514 <__s2b+0x18>
|
|
801b532: 9b08 ldr r3, [sp, #32]
|
|
801b534: 6143 str r3, [r0, #20]
|
|
801b536: 2d09 cmp r5, #9
|
|
801b538: f04f 0301 mov.w r3, #1
|
|
801b53c: 6103 str r3, [r0, #16]
|
|
801b53e: dd16 ble.n 801b56e <__s2b+0x72>
|
|
801b540: f104 0809 add.w r8, r4, #9
|
|
801b544: 46c1 mov r9, r8
|
|
801b546: 442c add r4, r5
|
|
801b548: f819 3b01 ldrb.w r3, [r9], #1
|
|
801b54c: 4601 mov r1, r0
|
|
801b54e: 3b30 subs r3, #48 @ 0x30
|
|
801b550: 220a movs r2, #10
|
|
801b552: 4630 mov r0, r6
|
|
801b554: f7ff ff8c bl 801b470 <__multadd>
|
|
801b558: 45a1 cmp r9, r4
|
|
801b55a: d1f5 bne.n 801b548 <__s2b+0x4c>
|
|
801b55c: 44a8 add r8, r5
|
|
801b55e: f1a8 0408 sub.w r4, r8, #8
|
|
801b562: 1b2d subs r5, r5, r4
|
|
801b564: 1963 adds r3, r4, r5
|
|
801b566: 429f cmp r7, r3
|
|
801b568: dc04 bgt.n 801b574 <__s2b+0x78>
|
|
801b56a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
801b56e: 340a adds r4, #10
|
|
801b570: 2509 movs r5, #9
|
|
801b572: e7f6 b.n 801b562 <__s2b+0x66>
|
|
801b574: f814 3b01 ldrb.w r3, [r4], #1
|
|
801b578: 4601 mov r1, r0
|
|
801b57a: 3b30 subs r3, #48 @ 0x30
|
|
801b57c: 220a movs r2, #10
|
|
801b57e: 4630 mov r0, r6
|
|
801b580: f7ff ff76 bl 801b470 <__multadd>
|
|
801b584: e7ee b.n 801b564 <__s2b+0x68>
|
|
801b586: bf00 nop
|
|
801b588: 0801e6c5 .word 0x0801e6c5
|
|
801b58c: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801b590 <__hi0bits>:
|
|
801b590: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
|
|
801b594: 4603 mov r3, r0
|
|
801b596: bf36 itet cc
|
|
801b598: 0403 lslcc r3, r0, #16
|
|
801b59a: 2000 movcs r0, #0
|
|
801b59c: 2010 movcc r0, #16
|
|
801b59e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
801b5a2: bf3c itt cc
|
|
801b5a4: 021b lslcc r3, r3, #8
|
|
801b5a6: 3008 addcc r0, #8
|
|
801b5a8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
801b5ac: bf3c itt cc
|
|
801b5ae: 011b lslcc r3, r3, #4
|
|
801b5b0: 3004 addcc r0, #4
|
|
801b5b2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
801b5b6: bf3c itt cc
|
|
801b5b8: 009b lslcc r3, r3, #2
|
|
801b5ba: 3002 addcc r0, #2
|
|
801b5bc: 2b00 cmp r3, #0
|
|
801b5be: db05 blt.n 801b5cc <__hi0bits+0x3c>
|
|
801b5c0: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
|
|
801b5c4: f100 0001 add.w r0, r0, #1
|
|
801b5c8: bf08 it eq
|
|
801b5ca: 2020 moveq r0, #32
|
|
801b5cc: 4770 bx lr
|
|
|
|
0801b5ce <__lo0bits>:
|
|
801b5ce: 6803 ldr r3, [r0, #0]
|
|
801b5d0: 4602 mov r2, r0
|
|
801b5d2: f013 0007 ands.w r0, r3, #7
|
|
801b5d6: d00b beq.n 801b5f0 <__lo0bits+0x22>
|
|
801b5d8: 07d9 lsls r1, r3, #31
|
|
801b5da: d421 bmi.n 801b620 <__lo0bits+0x52>
|
|
801b5dc: 0798 lsls r0, r3, #30
|
|
801b5de: bf49 itett mi
|
|
801b5e0: 085b lsrmi r3, r3, #1
|
|
801b5e2: 089b lsrpl r3, r3, #2
|
|
801b5e4: 2001 movmi r0, #1
|
|
801b5e6: 6013 strmi r3, [r2, #0]
|
|
801b5e8: bf5c itt pl
|
|
801b5ea: 6013 strpl r3, [r2, #0]
|
|
801b5ec: 2002 movpl r0, #2
|
|
801b5ee: 4770 bx lr
|
|
801b5f0: b299 uxth r1, r3
|
|
801b5f2: b909 cbnz r1, 801b5f8 <__lo0bits+0x2a>
|
|
801b5f4: 0c1b lsrs r3, r3, #16
|
|
801b5f6: 2010 movs r0, #16
|
|
801b5f8: b2d9 uxtb r1, r3
|
|
801b5fa: b909 cbnz r1, 801b600 <__lo0bits+0x32>
|
|
801b5fc: 3008 adds r0, #8
|
|
801b5fe: 0a1b lsrs r3, r3, #8
|
|
801b600: 0719 lsls r1, r3, #28
|
|
801b602: bf04 itt eq
|
|
801b604: 091b lsreq r3, r3, #4
|
|
801b606: 3004 addeq r0, #4
|
|
801b608: 0799 lsls r1, r3, #30
|
|
801b60a: bf04 itt eq
|
|
801b60c: 089b lsreq r3, r3, #2
|
|
801b60e: 3002 addeq r0, #2
|
|
801b610: 07d9 lsls r1, r3, #31
|
|
801b612: d403 bmi.n 801b61c <__lo0bits+0x4e>
|
|
801b614: 085b lsrs r3, r3, #1
|
|
801b616: f100 0001 add.w r0, r0, #1
|
|
801b61a: d003 beq.n 801b624 <__lo0bits+0x56>
|
|
801b61c: 6013 str r3, [r2, #0]
|
|
801b61e: 4770 bx lr
|
|
801b620: 2000 movs r0, #0
|
|
801b622: 4770 bx lr
|
|
801b624: 2020 movs r0, #32
|
|
801b626: 4770 bx lr
|
|
|
|
0801b628 <__i2b>:
|
|
801b628: b510 push {r4, lr}
|
|
801b62a: 460c mov r4, r1
|
|
801b62c: 2101 movs r1, #1
|
|
801b62e: f7ff febf bl 801b3b0 <_Balloc>
|
|
801b632: 4602 mov r2, r0
|
|
801b634: b928 cbnz r0, 801b642 <__i2b+0x1a>
|
|
801b636: 4b05 ldr r3, [pc, #20] @ (801b64c <__i2b+0x24>)
|
|
801b638: 4805 ldr r0, [pc, #20] @ (801b650 <__i2b+0x28>)
|
|
801b63a: f240 1145 movw r1, #325 @ 0x145
|
|
801b63e: f001 fe03 bl 801d248 <__assert_func>
|
|
801b642: 2301 movs r3, #1
|
|
801b644: 6144 str r4, [r0, #20]
|
|
801b646: 6103 str r3, [r0, #16]
|
|
801b648: bd10 pop {r4, pc}
|
|
801b64a: bf00 nop
|
|
801b64c: 0801e6c5 .word 0x0801e6c5
|
|
801b650: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801b654 <__multiply>:
|
|
801b654: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801b658: f8d1 9010 ldr.w r9, [r1, #16]
|
|
801b65c: f8d2 a010 ldr.w sl, [r2, #16]
|
|
801b660: 45d1 cmp r9, sl
|
|
801b662: b085 sub sp, #20
|
|
801b664: 4688 mov r8, r1
|
|
801b666: 4614 mov r4, r2
|
|
801b668: db04 blt.n 801b674 <__multiply+0x20>
|
|
801b66a: 4653 mov r3, sl
|
|
801b66c: 460c mov r4, r1
|
|
801b66e: 46ca mov sl, r9
|
|
801b670: 4690 mov r8, r2
|
|
801b672: 4699 mov r9, r3
|
|
801b674: 68a3 ldr r3, [r4, #8]
|
|
801b676: 6861 ldr r1, [r4, #4]
|
|
801b678: eb0a 0609 add.w r6, sl, r9
|
|
801b67c: 42b3 cmp r3, r6
|
|
801b67e: bfb8 it lt
|
|
801b680: 3101 addlt r1, #1
|
|
801b682: f7ff fe95 bl 801b3b0 <_Balloc>
|
|
801b686: b930 cbnz r0, 801b696 <__multiply+0x42>
|
|
801b688: 4602 mov r2, r0
|
|
801b68a: 4b45 ldr r3, [pc, #276] @ (801b7a0 <__multiply+0x14c>)
|
|
801b68c: 4845 ldr r0, [pc, #276] @ (801b7a4 <__multiply+0x150>)
|
|
801b68e: f44f 71b1 mov.w r1, #354 @ 0x162
|
|
801b692: f001 fdd9 bl 801d248 <__assert_func>
|
|
801b696: f100 0514 add.w r5, r0, #20
|
|
801b69a: eb05 0786 add.w r7, r5, r6, lsl #2
|
|
801b69e: 462b mov r3, r5
|
|
801b6a0: 2200 movs r2, #0
|
|
801b6a2: 42bb cmp r3, r7
|
|
801b6a4: d31f bcc.n 801b6e6 <__multiply+0x92>
|
|
801b6a6: f104 0c14 add.w ip, r4, #20
|
|
801b6aa: f108 0114 add.w r1, r8, #20
|
|
801b6ae: eb0c 038a add.w r3, ip, sl, lsl #2
|
|
801b6b2: eb01 0289 add.w r2, r1, r9, lsl #2
|
|
801b6b6: 9202 str r2, [sp, #8]
|
|
801b6b8: 1b1a subs r2, r3, r4
|
|
801b6ba: 3a15 subs r2, #21
|
|
801b6bc: f022 0203 bic.w r2, r2, #3
|
|
801b6c0: 3415 adds r4, #21
|
|
801b6c2: 429c cmp r4, r3
|
|
801b6c4: bf88 it hi
|
|
801b6c6: 2200 movhi r2, #0
|
|
801b6c8: 9201 str r2, [sp, #4]
|
|
801b6ca: 9a02 ldr r2, [sp, #8]
|
|
801b6cc: 9103 str r1, [sp, #12]
|
|
801b6ce: 428a cmp r2, r1
|
|
801b6d0: d80c bhi.n 801b6ec <__multiply+0x98>
|
|
801b6d2: 2e00 cmp r6, #0
|
|
801b6d4: dd03 ble.n 801b6de <__multiply+0x8a>
|
|
801b6d6: f857 3d04 ldr.w r3, [r7, #-4]!
|
|
801b6da: 2b00 cmp r3, #0
|
|
801b6dc: d05d beq.n 801b79a <__multiply+0x146>
|
|
801b6de: 6106 str r6, [r0, #16]
|
|
801b6e0: b005 add sp, #20
|
|
801b6e2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801b6e6: f843 2b04 str.w r2, [r3], #4
|
|
801b6ea: e7da b.n 801b6a2 <__multiply+0x4e>
|
|
801b6ec: f8b1 a000 ldrh.w sl, [r1]
|
|
801b6f0: f1ba 0f00 cmp.w sl, #0
|
|
801b6f4: d024 beq.n 801b740 <__multiply+0xec>
|
|
801b6f6: 46e0 mov r8, ip
|
|
801b6f8: 46a9 mov r9, r5
|
|
801b6fa: f04f 0e00 mov.w lr, #0
|
|
801b6fe: f858 2b04 ldr.w r2, [r8], #4
|
|
801b702: f8d9 4000 ldr.w r4, [r9]
|
|
801b706: fa1f fb82 uxth.w fp, r2
|
|
801b70a: b2a4 uxth r4, r4
|
|
801b70c: fb0a 440b mla r4, sl, fp, r4
|
|
801b710: ea4f 4b12 mov.w fp, r2, lsr #16
|
|
801b714: f8d9 2000 ldr.w r2, [r9]
|
|
801b718: 4474 add r4, lr
|
|
801b71a: ea4f 4e12 mov.w lr, r2, lsr #16
|
|
801b71e: fb0a e20b mla r2, sl, fp, lr
|
|
801b722: eb02 4214 add.w r2, r2, r4, lsr #16
|
|
801b726: b2a4 uxth r4, r4
|
|
801b728: ea44 4402 orr.w r4, r4, r2, lsl #16
|
|
801b72c: 4543 cmp r3, r8
|
|
801b72e: f849 4b04 str.w r4, [r9], #4
|
|
801b732: ea4f 4e12 mov.w lr, r2, lsr #16
|
|
801b736: d8e2 bhi.n 801b6fe <__multiply+0xaa>
|
|
801b738: 9a01 ldr r2, [sp, #4]
|
|
801b73a: 18aa adds r2, r5, r2
|
|
801b73c: f8c2 e004 str.w lr, [r2, #4]
|
|
801b740: 9a03 ldr r2, [sp, #12]
|
|
801b742: f8b2 8002 ldrh.w r8, [r2, #2]
|
|
801b746: 3104 adds r1, #4
|
|
801b748: f1b8 0f00 cmp.w r8, #0
|
|
801b74c: d023 beq.n 801b796 <__multiply+0x142>
|
|
801b74e: 682a ldr r2, [r5, #0]
|
|
801b750: 46e6 mov lr, ip
|
|
801b752: 4691 mov r9, r2
|
|
801b754: 46aa mov sl, r5
|
|
801b756: f04f 0b00 mov.w fp, #0
|
|
801b75a: f8be 4000 ldrh.w r4, [lr]
|
|
801b75e: fb08 b404 mla r4, r8, r4, fp
|
|
801b762: eb04 4419 add.w r4, r4, r9, lsr #16
|
|
801b766: b292 uxth r2, r2
|
|
801b768: ea42 4204 orr.w r2, r2, r4, lsl #16
|
|
801b76c: f84a 2b04 str.w r2, [sl], #4
|
|
801b770: f85e 2b04 ldr.w r2, [lr], #4
|
|
801b774: f8da 9000 ldr.w r9, [sl]
|
|
801b778: ea4f 4b12 mov.w fp, r2, lsr #16
|
|
801b77c: fa1f f289 uxth.w r2, r9
|
|
801b780: fb08 220b mla r2, r8, fp, r2
|
|
801b784: eb02 4214 add.w r2, r2, r4, lsr #16
|
|
801b788: 4573 cmp r3, lr
|
|
801b78a: ea4f 4b12 mov.w fp, r2, lsr #16
|
|
801b78e: d8e4 bhi.n 801b75a <__multiply+0x106>
|
|
801b790: 9c01 ldr r4, [sp, #4]
|
|
801b792: 192c adds r4, r5, r4
|
|
801b794: 6062 str r2, [r4, #4]
|
|
801b796: 3504 adds r5, #4
|
|
801b798: e797 b.n 801b6ca <__multiply+0x76>
|
|
801b79a: 3e01 subs r6, #1
|
|
801b79c: e799 b.n 801b6d2 <__multiply+0x7e>
|
|
801b79e: bf00 nop
|
|
801b7a0: 0801e6c5 .word 0x0801e6c5
|
|
801b7a4: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801b7a8 <__pow5mult>:
|
|
801b7a8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
801b7ac: 4617 mov r7, r2
|
|
801b7ae: f012 0203 ands.w r2, r2, #3
|
|
801b7b2: 4680 mov r8, r0
|
|
801b7b4: 460d mov r5, r1
|
|
801b7b6: d007 beq.n 801b7c8 <__pow5mult+0x20>
|
|
801b7b8: 4c26 ldr r4, [pc, #152] @ (801b854 <__pow5mult+0xac>)
|
|
801b7ba: 3a01 subs r2, #1
|
|
801b7bc: 2300 movs r3, #0
|
|
801b7be: f854 2022 ldr.w r2, [r4, r2, lsl #2]
|
|
801b7c2: f7ff fe55 bl 801b470 <__multadd>
|
|
801b7c6: 4605 mov r5, r0
|
|
801b7c8: 10bf asrs r7, r7, #2
|
|
801b7ca: d03f beq.n 801b84c <__pow5mult+0xa4>
|
|
801b7cc: f8d8 401c ldr.w r4, [r8, #28]
|
|
801b7d0: b994 cbnz r4, 801b7f8 <__pow5mult+0x50>
|
|
801b7d2: 2010 movs r0, #16
|
|
801b7d4: f7ff fd36 bl 801b244 <malloc>
|
|
801b7d8: 4604 mov r4, r0
|
|
801b7da: f8c8 001c str.w r0, [r8, #28]
|
|
801b7de: b930 cbnz r0, 801b7ee <__pow5mult+0x46>
|
|
801b7e0: 4602 mov r2, r0
|
|
801b7e2: 4b1d ldr r3, [pc, #116] @ (801b858 <__pow5mult+0xb0>)
|
|
801b7e4: 481d ldr r0, [pc, #116] @ (801b85c <__pow5mult+0xb4>)
|
|
801b7e6: f240 11b3 movw r1, #435 @ 0x1b3
|
|
801b7ea: f001 fd2d bl 801d248 <__assert_func>
|
|
801b7ee: 2300 movs r3, #0
|
|
801b7f0: e9c0 3301 strd r3, r3, [r0, #4]
|
|
801b7f4: 6003 str r3, [r0, #0]
|
|
801b7f6: 60c3 str r3, [r0, #12]
|
|
801b7f8: 68a6 ldr r6, [r4, #8]
|
|
801b7fa: b946 cbnz r6, 801b80e <__pow5mult+0x66>
|
|
801b7fc: f240 2171 movw r1, #625 @ 0x271
|
|
801b800: 4640 mov r0, r8
|
|
801b802: f7ff ff11 bl 801b628 <__i2b>
|
|
801b806: 2300 movs r3, #0
|
|
801b808: 60a0 str r0, [r4, #8]
|
|
801b80a: 4606 mov r6, r0
|
|
801b80c: 6003 str r3, [r0, #0]
|
|
801b80e: 462c mov r4, r5
|
|
801b810: f04f 0900 mov.w r9, #0
|
|
801b814: f007 0301 and.w r3, r7, #1
|
|
801b818: 107f asrs r7, r7, #1
|
|
801b81a: b153 cbz r3, 801b832 <__pow5mult+0x8a>
|
|
801b81c: 4629 mov r1, r5
|
|
801b81e: 4632 mov r2, r6
|
|
801b820: 4640 mov r0, r8
|
|
801b822: f7ff ff17 bl 801b654 <__multiply>
|
|
801b826: 4621 mov r1, r4
|
|
801b828: 4605 mov r5, r0
|
|
801b82a: 4640 mov r0, r8
|
|
801b82c: f7ff fdfe bl 801b42c <_Bfree>
|
|
801b830: b167 cbz r7, 801b84c <__pow5mult+0xa4>
|
|
801b832: 6830 ldr r0, [r6, #0]
|
|
801b834: b938 cbnz r0, 801b846 <__pow5mult+0x9e>
|
|
801b836: 4632 mov r2, r6
|
|
801b838: 4631 mov r1, r6
|
|
801b83a: 4640 mov r0, r8
|
|
801b83c: f7ff ff0a bl 801b654 <__multiply>
|
|
801b840: 6030 str r0, [r6, #0]
|
|
801b842: f8c0 9000 str.w r9, [r0]
|
|
801b846: 4606 mov r6, r0
|
|
801b848: 462c mov r4, r5
|
|
801b84a: e7e3 b.n 801b814 <__pow5mult+0x6c>
|
|
801b84c: 4628 mov r0, r5
|
|
801b84e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
801b852: bf00 nop
|
|
801b854: 0801e7e8 .word 0x0801e7e8
|
|
801b858: 0801e656 .word 0x0801e656
|
|
801b85c: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801b860 <__lshift>:
|
|
801b860: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801b864: 460c mov r4, r1
|
|
801b866: 6849 ldr r1, [r1, #4]
|
|
801b868: 6923 ldr r3, [r4, #16]
|
|
801b86a: eb03 1862 add.w r8, r3, r2, asr #5
|
|
801b86e: 68a3 ldr r3, [r4, #8]
|
|
801b870: 4607 mov r7, r0
|
|
801b872: 4615 mov r5, r2
|
|
801b874: ea4f 1a62 mov.w sl, r2, asr #5
|
|
801b878: f108 0901 add.w r9, r8, #1
|
|
801b87c: 454b cmp r3, r9
|
|
801b87e: db0b blt.n 801b898 <__lshift+0x38>
|
|
801b880: 4638 mov r0, r7
|
|
801b882: f7ff fd95 bl 801b3b0 <_Balloc>
|
|
801b886: 4606 mov r6, r0
|
|
801b888: b948 cbnz r0, 801b89e <__lshift+0x3e>
|
|
801b88a: 4602 mov r2, r0
|
|
801b88c: 4b29 ldr r3, [pc, #164] @ (801b934 <__lshift+0xd4>)
|
|
801b88e: 482a ldr r0, [pc, #168] @ (801b938 <__lshift+0xd8>)
|
|
801b890: f44f 71ef mov.w r1, #478 @ 0x1de
|
|
801b894: f001 fcd8 bl 801d248 <__assert_func>
|
|
801b898: 3101 adds r1, #1
|
|
801b89a: 005b lsls r3, r3, #1
|
|
801b89c: e7ee b.n 801b87c <__lshift+0x1c>
|
|
801b89e: 2300 movs r3, #0
|
|
801b8a0: f100 0c14 add.w ip, r0, #20
|
|
801b8a4: f100 0210 add.w r2, r0, #16
|
|
801b8a8: 4619 mov r1, r3
|
|
801b8aa: 4553 cmp r3, sl
|
|
801b8ac: db35 blt.n 801b91a <__lshift+0xba>
|
|
801b8ae: 6922 ldr r2, [r4, #16]
|
|
801b8b0: ea2a 7aea bic.w sl, sl, sl, asr #31
|
|
801b8b4: eb0c 0c8a add.w ip, ip, sl, lsl #2
|
|
801b8b8: f104 0314 add.w r3, r4, #20
|
|
801b8bc: f015 0e1f ands.w lr, r5, #31
|
|
801b8c0: 4661 mov r1, ip
|
|
801b8c2: eb03 0282 add.w r2, r3, r2, lsl #2
|
|
801b8c6: d02c beq.n 801b922 <__lshift+0xc2>
|
|
801b8c8: f1ce 0a20 rsb sl, lr, #32
|
|
801b8cc: 2500 movs r5, #0
|
|
801b8ce: 6818 ldr r0, [r3, #0]
|
|
801b8d0: 468b mov fp, r1
|
|
801b8d2: fa00 f00e lsl.w r0, r0, lr
|
|
801b8d6: 4328 orrs r0, r5
|
|
801b8d8: f8cb 0000 str.w r0, [fp]
|
|
801b8dc: f853 5b04 ldr.w r5, [r3], #4
|
|
801b8e0: 429a cmp r2, r3
|
|
801b8e2: f101 0104 add.w r1, r1, #4
|
|
801b8e6: fa25 f50a lsr.w r5, r5, sl
|
|
801b8ea: d8f0 bhi.n 801b8ce <__lshift+0x6e>
|
|
801b8ec: 1b13 subs r3, r2, r4
|
|
801b8ee: 3b15 subs r3, #21
|
|
801b8f0: f023 0303 bic.w r3, r3, #3
|
|
801b8f4: f104 0115 add.w r1, r4, #21
|
|
801b8f8: 428a cmp r2, r1
|
|
801b8fa: bf38 it cc
|
|
801b8fc: 2300 movcc r3, #0
|
|
801b8fe: 449c add ip, r3
|
|
801b900: f8cc 5004 str.w r5, [ip, #4]
|
|
801b904: b905 cbnz r5, 801b908 <__lshift+0xa8>
|
|
801b906: 46c1 mov r9, r8
|
|
801b908: 4638 mov r0, r7
|
|
801b90a: f8c6 9010 str.w r9, [r6, #16]
|
|
801b90e: 4621 mov r1, r4
|
|
801b910: f7ff fd8c bl 801b42c <_Bfree>
|
|
801b914: 4630 mov r0, r6
|
|
801b916: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801b91a: f842 1f04 str.w r1, [r2, #4]!
|
|
801b91e: 3301 adds r3, #1
|
|
801b920: e7c3 b.n 801b8aa <__lshift+0x4a>
|
|
801b922: f853 5b04 ldr.w r5, [r3], #4
|
|
801b926: 600d str r5, [r1, #0]
|
|
801b928: 429a cmp r2, r3
|
|
801b92a: f101 0104 add.w r1, r1, #4
|
|
801b92e: d8f8 bhi.n 801b922 <__lshift+0xc2>
|
|
801b930: e7e9 b.n 801b906 <__lshift+0xa6>
|
|
801b932: bf00 nop
|
|
801b934: 0801e6c5 .word 0x0801e6c5
|
|
801b938: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801b93c <__mcmp>:
|
|
801b93c: 690a ldr r2, [r1, #16]
|
|
801b93e: 4603 mov r3, r0
|
|
801b940: 6900 ldr r0, [r0, #16]
|
|
801b942: 1a80 subs r0, r0, r2
|
|
801b944: b530 push {r4, r5, lr}
|
|
801b946: d10e bne.n 801b966 <__mcmp+0x2a>
|
|
801b948: 3314 adds r3, #20
|
|
801b94a: 3114 adds r1, #20
|
|
801b94c: eb03 0482 add.w r4, r3, r2, lsl #2
|
|
801b950: eb01 0182 add.w r1, r1, r2, lsl #2
|
|
801b954: f854 5d04 ldr.w r5, [r4, #-4]!
|
|
801b958: f851 2d04 ldr.w r2, [r1, #-4]!
|
|
801b95c: 4295 cmp r5, r2
|
|
801b95e: d003 beq.n 801b968 <__mcmp+0x2c>
|
|
801b960: d205 bcs.n 801b96e <__mcmp+0x32>
|
|
801b962: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801b966: bd30 pop {r4, r5, pc}
|
|
801b968: 42a3 cmp r3, r4
|
|
801b96a: d3f3 bcc.n 801b954 <__mcmp+0x18>
|
|
801b96c: e7fb b.n 801b966 <__mcmp+0x2a>
|
|
801b96e: 2001 movs r0, #1
|
|
801b970: e7f9 b.n 801b966 <__mcmp+0x2a>
|
|
...
|
|
|
|
0801b974 <__mdiff>:
|
|
801b974: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801b978: 468a mov sl, r1
|
|
801b97a: 4606 mov r6, r0
|
|
801b97c: 4611 mov r1, r2
|
|
801b97e: 4650 mov r0, sl
|
|
801b980: 4614 mov r4, r2
|
|
801b982: f7ff ffdb bl 801b93c <__mcmp>
|
|
801b986: 1e05 subs r5, r0, #0
|
|
801b988: d112 bne.n 801b9b0 <__mdiff+0x3c>
|
|
801b98a: 4629 mov r1, r5
|
|
801b98c: 4630 mov r0, r6
|
|
801b98e: f7ff fd0f bl 801b3b0 <_Balloc>
|
|
801b992: 4602 mov r2, r0
|
|
801b994: b928 cbnz r0, 801b9a2 <__mdiff+0x2e>
|
|
801b996: 4b41 ldr r3, [pc, #260] @ (801ba9c <__mdiff+0x128>)
|
|
801b998: f240 2137 movw r1, #567 @ 0x237
|
|
801b99c: 4840 ldr r0, [pc, #256] @ (801baa0 <__mdiff+0x12c>)
|
|
801b99e: f001 fc53 bl 801d248 <__assert_func>
|
|
801b9a2: 2301 movs r3, #1
|
|
801b9a4: e9c0 3504 strd r3, r5, [r0, #16]
|
|
801b9a8: 4610 mov r0, r2
|
|
801b9aa: b003 add sp, #12
|
|
801b9ac: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801b9b0: bfbc itt lt
|
|
801b9b2: 4653 movlt r3, sl
|
|
801b9b4: 46a2 movlt sl, r4
|
|
801b9b6: 4630 mov r0, r6
|
|
801b9b8: f8da 1004 ldr.w r1, [sl, #4]
|
|
801b9bc: bfba itte lt
|
|
801b9be: 461c movlt r4, r3
|
|
801b9c0: 2501 movlt r5, #1
|
|
801b9c2: 2500 movge r5, #0
|
|
801b9c4: f7ff fcf4 bl 801b3b0 <_Balloc>
|
|
801b9c8: 4602 mov r2, r0
|
|
801b9ca: b918 cbnz r0, 801b9d4 <__mdiff+0x60>
|
|
801b9cc: 4b33 ldr r3, [pc, #204] @ (801ba9c <__mdiff+0x128>)
|
|
801b9ce: f240 2145 movw r1, #581 @ 0x245
|
|
801b9d2: e7e3 b.n 801b99c <__mdiff+0x28>
|
|
801b9d4: f8da 7010 ldr.w r7, [sl, #16]
|
|
801b9d8: 6926 ldr r6, [r4, #16]
|
|
801b9da: 60c5 str r5, [r0, #12]
|
|
801b9dc: f10a 0914 add.w r9, sl, #20
|
|
801b9e0: f104 0e14 add.w lr, r4, #20
|
|
801b9e4: f100 0514 add.w r5, r0, #20
|
|
801b9e8: f10a 0310 add.w r3, sl, #16
|
|
801b9ec: eb09 0887 add.w r8, r9, r7, lsl #2
|
|
801b9f0: eb0e 0686 add.w r6, lr, r6, lsl #2
|
|
801b9f4: 9301 str r3, [sp, #4]
|
|
801b9f6: 46ab mov fp, r5
|
|
801b9f8: f04f 0c00 mov.w ip, #0
|
|
801b9fc: 9b01 ldr r3, [sp, #4]
|
|
801b9fe: f85e 0b04 ldr.w r0, [lr], #4
|
|
801ba02: f853 af04 ldr.w sl, [r3, #4]!
|
|
801ba06: 9301 str r3, [sp, #4]
|
|
801ba08: fa1f f38a uxth.w r3, sl
|
|
801ba0c: 4619 mov r1, r3
|
|
801ba0e: b283 uxth r3, r0
|
|
801ba10: 1acb subs r3, r1, r3
|
|
801ba12: 0c00 lsrs r0, r0, #16
|
|
801ba14: 4463 add r3, ip
|
|
801ba16: ebc0 401a rsb r0, r0, sl, lsr #16
|
|
801ba1a: eb00 4023 add.w r0, r0, r3, asr #16
|
|
801ba1e: b29b uxth r3, r3
|
|
801ba20: ea43 4300 orr.w r3, r3, r0, lsl #16
|
|
801ba24: 4576 cmp r6, lr
|
|
801ba26: f84b 3b04 str.w r3, [fp], #4
|
|
801ba2a: ea4f 4c20 mov.w ip, r0, asr #16
|
|
801ba2e: d8e5 bhi.n 801b9fc <__mdiff+0x88>
|
|
801ba30: 1b33 subs r3, r6, r4
|
|
801ba32: 3b15 subs r3, #21
|
|
801ba34: 3415 adds r4, #21
|
|
801ba36: f023 0303 bic.w r3, r3, #3
|
|
801ba3a: 42a6 cmp r6, r4
|
|
801ba3c: bf38 it cc
|
|
801ba3e: 2300 movcc r3, #0
|
|
801ba40: 18e8 adds r0, r5, r3
|
|
801ba42: 444b add r3, r9
|
|
801ba44: 1d1c adds r4, r3, #4
|
|
801ba46: 3004 adds r0, #4
|
|
801ba48: 4626 mov r6, r4
|
|
801ba4a: eba5 0509 sub.w r5, r5, r9
|
|
801ba4e: 4546 cmp r6, r8
|
|
801ba50: eb06 0e05 add.w lr, r6, r5
|
|
801ba54: d30e bcc.n 801ba74 <__mdiff+0x100>
|
|
801ba56: f108 0103 add.w r1, r8, #3
|
|
801ba5a: 1b09 subs r1, r1, r4
|
|
801ba5c: f021 0103 bic.w r1, r1, #3
|
|
801ba60: 3301 adds r3, #1
|
|
801ba62: 4598 cmp r8, r3
|
|
801ba64: bf38 it cc
|
|
801ba66: 2100 movcc r1, #0
|
|
801ba68: 4401 add r1, r0
|
|
801ba6a: f851 3d04 ldr.w r3, [r1, #-4]!
|
|
801ba6e: b19b cbz r3, 801ba98 <__mdiff+0x124>
|
|
801ba70: 6117 str r7, [r2, #16]
|
|
801ba72: e799 b.n 801b9a8 <__mdiff+0x34>
|
|
801ba74: f856 1b04 ldr.w r1, [r6], #4
|
|
801ba78: 46e2 mov sl, ip
|
|
801ba7a: ea4f 4911 mov.w r9, r1, lsr #16
|
|
801ba7e: fa1c fc81 uxtah ip, ip, r1
|
|
801ba82: 4451 add r1, sl
|
|
801ba84: eb09 492c add.w r9, r9, ip, asr #16
|
|
801ba88: b289 uxth r1, r1
|
|
801ba8a: ea41 4109 orr.w r1, r1, r9, lsl #16
|
|
801ba8e: ea4f 4c29 mov.w ip, r9, asr #16
|
|
801ba92: f8ce 1000 str.w r1, [lr]
|
|
801ba96: e7da b.n 801ba4e <__mdiff+0xda>
|
|
801ba98: 3f01 subs r7, #1
|
|
801ba9a: e7e6 b.n 801ba6a <__mdiff+0xf6>
|
|
801ba9c: 0801e6c5 .word 0x0801e6c5
|
|
801baa0: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801baa4 <__ulp>:
|
|
801baa4: b082 sub sp, #8
|
|
801baa6: ed8d 0b00 vstr d0, [sp]
|
|
801baaa: 9a01 ldr r2, [sp, #4]
|
|
801baac: 4b0f ldr r3, [pc, #60] @ (801baec <__ulp+0x48>)
|
|
801baae: 4013 ands r3, r2
|
|
801bab0: f1a3 7350 sub.w r3, r3, #54525952 @ 0x3400000
|
|
801bab4: 2b00 cmp r3, #0
|
|
801bab6: dc08 bgt.n 801baca <__ulp+0x26>
|
|
801bab8: 425b negs r3, r3
|
|
801baba: f1b3 7fa0 cmp.w r3, #20971520 @ 0x1400000
|
|
801babe: ea4f 5223 mov.w r2, r3, asr #20
|
|
801bac2: da04 bge.n 801bace <__ulp+0x2a>
|
|
801bac4: f44f 2300 mov.w r3, #524288 @ 0x80000
|
|
801bac8: 4113 asrs r3, r2
|
|
801baca: 2200 movs r2, #0
|
|
801bacc: e008 b.n 801bae0 <__ulp+0x3c>
|
|
801bace: f1a2 0314 sub.w r3, r2, #20
|
|
801bad2: 2b1e cmp r3, #30
|
|
801bad4: bfda itte le
|
|
801bad6: f04f 4200 movle.w r2, #2147483648 @ 0x80000000
|
|
801bada: 40da lsrle r2, r3
|
|
801badc: 2201 movgt r2, #1
|
|
801bade: 2300 movs r3, #0
|
|
801bae0: 4619 mov r1, r3
|
|
801bae2: 4610 mov r0, r2
|
|
801bae4: ec41 0b10 vmov d0, r0, r1
|
|
801bae8: b002 add sp, #8
|
|
801baea: 4770 bx lr
|
|
801baec: 7ff00000 .word 0x7ff00000
|
|
|
|
0801baf0 <__b2d>:
|
|
801baf0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
801baf4: 6906 ldr r6, [r0, #16]
|
|
801baf6: f100 0814 add.w r8, r0, #20
|
|
801bafa: eb08 0686 add.w r6, r8, r6, lsl #2
|
|
801bafe: 1f37 subs r7, r6, #4
|
|
801bb00: f856 2c04 ldr.w r2, [r6, #-4]
|
|
801bb04: 4610 mov r0, r2
|
|
801bb06: f7ff fd43 bl 801b590 <__hi0bits>
|
|
801bb0a: f1c0 0320 rsb r3, r0, #32
|
|
801bb0e: 280a cmp r0, #10
|
|
801bb10: 600b str r3, [r1, #0]
|
|
801bb12: 491b ldr r1, [pc, #108] @ (801bb80 <__b2d+0x90>)
|
|
801bb14: dc15 bgt.n 801bb42 <__b2d+0x52>
|
|
801bb16: f1c0 0c0b rsb ip, r0, #11
|
|
801bb1a: fa22 f30c lsr.w r3, r2, ip
|
|
801bb1e: 45b8 cmp r8, r7
|
|
801bb20: ea43 0501 orr.w r5, r3, r1
|
|
801bb24: bf34 ite cc
|
|
801bb26: f856 3c08 ldrcc.w r3, [r6, #-8]
|
|
801bb2a: 2300 movcs r3, #0
|
|
801bb2c: 3015 adds r0, #21
|
|
801bb2e: fa02 f000 lsl.w r0, r2, r0
|
|
801bb32: fa23 f30c lsr.w r3, r3, ip
|
|
801bb36: 4303 orrs r3, r0
|
|
801bb38: 461c mov r4, r3
|
|
801bb3a: ec45 4b10 vmov d0, r4, r5
|
|
801bb3e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
801bb42: 45b8 cmp r8, r7
|
|
801bb44: bf3a itte cc
|
|
801bb46: f856 3c08 ldrcc.w r3, [r6, #-8]
|
|
801bb4a: f1a6 0708 subcc.w r7, r6, #8
|
|
801bb4e: 2300 movcs r3, #0
|
|
801bb50: 380b subs r0, #11
|
|
801bb52: d012 beq.n 801bb7a <__b2d+0x8a>
|
|
801bb54: f1c0 0120 rsb r1, r0, #32
|
|
801bb58: fa23 f401 lsr.w r4, r3, r1
|
|
801bb5c: 4082 lsls r2, r0
|
|
801bb5e: 4322 orrs r2, r4
|
|
801bb60: 4547 cmp r7, r8
|
|
801bb62: f042 557f orr.w r5, r2, #1069547520 @ 0x3fc00000
|
|
801bb66: bf8c ite hi
|
|
801bb68: f857 2c04 ldrhi.w r2, [r7, #-4]
|
|
801bb6c: 2200 movls r2, #0
|
|
801bb6e: 4083 lsls r3, r0
|
|
801bb70: 40ca lsrs r2, r1
|
|
801bb72: f445 1540 orr.w r5, r5, #3145728 @ 0x300000
|
|
801bb76: 4313 orrs r3, r2
|
|
801bb78: e7de b.n 801bb38 <__b2d+0x48>
|
|
801bb7a: ea42 0501 orr.w r5, r2, r1
|
|
801bb7e: e7db b.n 801bb38 <__b2d+0x48>
|
|
801bb80: 3ff00000 .word 0x3ff00000
|
|
|
|
0801bb84 <__d2b>:
|
|
801bb84: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
|
|
801bb88: 460f mov r7, r1
|
|
801bb8a: 2101 movs r1, #1
|
|
801bb8c: ec59 8b10 vmov r8, r9, d0
|
|
801bb90: 4616 mov r6, r2
|
|
801bb92: f7ff fc0d bl 801b3b0 <_Balloc>
|
|
801bb96: 4604 mov r4, r0
|
|
801bb98: b930 cbnz r0, 801bba8 <__d2b+0x24>
|
|
801bb9a: 4602 mov r2, r0
|
|
801bb9c: 4b23 ldr r3, [pc, #140] @ (801bc2c <__d2b+0xa8>)
|
|
801bb9e: 4824 ldr r0, [pc, #144] @ (801bc30 <__d2b+0xac>)
|
|
801bba0: f240 310f movw r1, #783 @ 0x30f
|
|
801bba4: f001 fb50 bl 801d248 <__assert_func>
|
|
801bba8: f3c9 550a ubfx r5, r9, #20, #11
|
|
801bbac: f3c9 0313 ubfx r3, r9, #0, #20
|
|
801bbb0: b10d cbz r5, 801bbb6 <__d2b+0x32>
|
|
801bbb2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
801bbb6: 9301 str r3, [sp, #4]
|
|
801bbb8: f1b8 0300 subs.w r3, r8, #0
|
|
801bbbc: d023 beq.n 801bc06 <__d2b+0x82>
|
|
801bbbe: 4668 mov r0, sp
|
|
801bbc0: 9300 str r3, [sp, #0]
|
|
801bbc2: f7ff fd04 bl 801b5ce <__lo0bits>
|
|
801bbc6: 9900 ldr r1, [sp, #0]
|
|
801bbc8: b1d8 cbz r0, 801bc02 <__d2b+0x7e>
|
|
801bbca: 9a01 ldr r2, [sp, #4]
|
|
801bbcc: f1c0 0320 rsb r3, r0, #32
|
|
801bbd0: fa02 f303 lsl.w r3, r2, r3
|
|
801bbd4: 430b orrs r3, r1
|
|
801bbd6: 40c2 lsrs r2, r0
|
|
801bbd8: 6163 str r3, [r4, #20]
|
|
801bbda: 9201 str r2, [sp, #4]
|
|
801bbdc: 9b01 ldr r3, [sp, #4]
|
|
801bbde: 61a3 str r3, [r4, #24]
|
|
801bbe0: 2b00 cmp r3, #0
|
|
801bbe2: bf0c ite eq
|
|
801bbe4: 2201 moveq r2, #1
|
|
801bbe6: 2202 movne r2, #2
|
|
801bbe8: 6122 str r2, [r4, #16]
|
|
801bbea: b1a5 cbz r5, 801bc16 <__d2b+0x92>
|
|
801bbec: f2a5 4533 subw r5, r5, #1075 @ 0x433
|
|
801bbf0: 4405 add r5, r0
|
|
801bbf2: 603d str r5, [r7, #0]
|
|
801bbf4: f1c0 0035 rsb r0, r0, #53 @ 0x35
|
|
801bbf8: 6030 str r0, [r6, #0]
|
|
801bbfa: 4620 mov r0, r4
|
|
801bbfc: b003 add sp, #12
|
|
801bbfe: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
801bc02: 6161 str r1, [r4, #20]
|
|
801bc04: e7ea b.n 801bbdc <__d2b+0x58>
|
|
801bc06: a801 add r0, sp, #4
|
|
801bc08: f7ff fce1 bl 801b5ce <__lo0bits>
|
|
801bc0c: 9b01 ldr r3, [sp, #4]
|
|
801bc0e: 6163 str r3, [r4, #20]
|
|
801bc10: 3020 adds r0, #32
|
|
801bc12: 2201 movs r2, #1
|
|
801bc14: e7e8 b.n 801bbe8 <__d2b+0x64>
|
|
801bc16: eb04 0382 add.w r3, r4, r2, lsl #2
|
|
801bc1a: f2a0 4032 subw r0, r0, #1074 @ 0x432
|
|
801bc1e: 6038 str r0, [r7, #0]
|
|
801bc20: 6918 ldr r0, [r3, #16]
|
|
801bc22: f7ff fcb5 bl 801b590 <__hi0bits>
|
|
801bc26: ebc0 1042 rsb r0, r0, r2, lsl #5
|
|
801bc2a: e7e5 b.n 801bbf8 <__d2b+0x74>
|
|
801bc2c: 0801e6c5 .word 0x0801e6c5
|
|
801bc30: 0801e6d6 .word 0x0801e6d6
|
|
|
|
0801bc34 <__ratio>:
|
|
801bc34: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801bc38: b085 sub sp, #20
|
|
801bc3a: e9cd 1000 strd r1, r0, [sp]
|
|
801bc3e: a902 add r1, sp, #8
|
|
801bc40: f7ff ff56 bl 801baf0 <__b2d>
|
|
801bc44: 9800 ldr r0, [sp, #0]
|
|
801bc46: a903 add r1, sp, #12
|
|
801bc48: ec55 4b10 vmov r4, r5, d0
|
|
801bc4c: f7ff ff50 bl 801baf0 <__b2d>
|
|
801bc50: 9b01 ldr r3, [sp, #4]
|
|
801bc52: 6919 ldr r1, [r3, #16]
|
|
801bc54: 9b00 ldr r3, [sp, #0]
|
|
801bc56: 691b ldr r3, [r3, #16]
|
|
801bc58: 1ac9 subs r1, r1, r3
|
|
801bc5a: e9dd 3202 ldrd r3, r2, [sp, #8]
|
|
801bc5e: 1a9b subs r3, r3, r2
|
|
801bc60: ec5b ab10 vmov sl, fp, d0
|
|
801bc64: eb03 1341 add.w r3, r3, r1, lsl #5
|
|
801bc68: 2b00 cmp r3, #0
|
|
801bc6a: bfce itee gt
|
|
801bc6c: 462a movgt r2, r5
|
|
801bc6e: ebc3 3303 rsble r3, r3, r3, lsl #12
|
|
801bc72: 465a movle r2, fp
|
|
801bc74: 462f mov r7, r5
|
|
801bc76: 46d9 mov r9, fp
|
|
801bc78: bfcc ite gt
|
|
801bc7a: eb02 5703 addgt.w r7, r2, r3, lsl #20
|
|
801bc7e: eb02 5903 addle.w r9, r2, r3, lsl #20
|
|
801bc82: 464b mov r3, r9
|
|
801bc84: 4652 mov r2, sl
|
|
801bc86: 4620 mov r0, r4
|
|
801bc88: 4639 mov r1, r7
|
|
801bc8a: f7e4 fdb7 bl 80007fc <__aeabi_ddiv>
|
|
801bc8e: ec41 0b10 vmov d0, r0, r1
|
|
801bc92: b005 add sp, #20
|
|
801bc94: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
|
0801bc98 <__copybits>:
|
|
801bc98: 3901 subs r1, #1
|
|
801bc9a: b570 push {r4, r5, r6, lr}
|
|
801bc9c: 1149 asrs r1, r1, #5
|
|
801bc9e: 6914 ldr r4, [r2, #16]
|
|
801bca0: 3101 adds r1, #1
|
|
801bca2: f102 0314 add.w r3, r2, #20
|
|
801bca6: eb00 0181 add.w r1, r0, r1, lsl #2
|
|
801bcaa: eb03 0484 add.w r4, r3, r4, lsl #2
|
|
801bcae: 1f05 subs r5, r0, #4
|
|
801bcb0: 42a3 cmp r3, r4
|
|
801bcb2: d30c bcc.n 801bcce <__copybits+0x36>
|
|
801bcb4: 1aa3 subs r3, r4, r2
|
|
801bcb6: 3b11 subs r3, #17
|
|
801bcb8: f023 0303 bic.w r3, r3, #3
|
|
801bcbc: 3211 adds r2, #17
|
|
801bcbe: 4294 cmp r4, r2
|
|
801bcc0: bf38 it cc
|
|
801bcc2: 2300 movcc r3, #0
|
|
801bcc4: 4418 add r0, r3
|
|
801bcc6: 2300 movs r3, #0
|
|
801bcc8: 4288 cmp r0, r1
|
|
801bcca: d305 bcc.n 801bcd8 <__copybits+0x40>
|
|
801bccc: bd70 pop {r4, r5, r6, pc}
|
|
801bcce: f853 6b04 ldr.w r6, [r3], #4
|
|
801bcd2: f845 6f04 str.w r6, [r5, #4]!
|
|
801bcd6: e7eb b.n 801bcb0 <__copybits+0x18>
|
|
801bcd8: f840 3b04 str.w r3, [r0], #4
|
|
801bcdc: e7f4 b.n 801bcc8 <__copybits+0x30>
|
|
|
|
0801bcde <__any_on>:
|
|
801bcde: f100 0214 add.w r2, r0, #20
|
|
801bce2: 6900 ldr r0, [r0, #16]
|
|
801bce4: 114b asrs r3, r1, #5
|
|
801bce6: 4298 cmp r0, r3
|
|
801bce8: b510 push {r4, lr}
|
|
801bcea: db11 blt.n 801bd10 <__any_on+0x32>
|
|
801bcec: dd0a ble.n 801bd04 <__any_on+0x26>
|
|
801bcee: f011 011f ands.w r1, r1, #31
|
|
801bcf2: d007 beq.n 801bd04 <__any_on+0x26>
|
|
801bcf4: f852 4023 ldr.w r4, [r2, r3, lsl #2]
|
|
801bcf8: fa24 f001 lsr.w r0, r4, r1
|
|
801bcfc: fa00 f101 lsl.w r1, r0, r1
|
|
801bd00: 428c cmp r4, r1
|
|
801bd02: d10b bne.n 801bd1c <__any_on+0x3e>
|
|
801bd04: eb02 0383 add.w r3, r2, r3, lsl #2
|
|
801bd08: 4293 cmp r3, r2
|
|
801bd0a: d803 bhi.n 801bd14 <__any_on+0x36>
|
|
801bd0c: 2000 movs r0, #0
|
|
801bd0e: bd10 pop {r4, pc}
|
|
801bd10: 4603 mov r3, r0
|
|
801bd12: e7f7 b.n 801bd04 <__any_on+0x26>
|
|
801bd14: f853 1d04 ldr.w r1, [r3, #-4]!
|
|
801bd18: 2900 cmp r1, #0
|
|
801bd1a: d0f5 beq.n 801bd08 <__any_on+0x2a>
|
|
801bd1c: 2001 movs r0, #1
|
|
801bd1e: e7f6 b.n 801bd0e <__any_on+0x30>
|
|
|
|
0801bd20 <sulp>:
|
|
801bd20: b570 push {r4, r5, r6, lr}
|
|
801bd22: 4604 mov r4, r0
|
|
801bd24: 460d mov r5, r1
|
|
801bd26: ec45 4b10 vmov d0, r4, r5
|
|
801bd2a: 4616 mov r6, r2
|
|
801bd2c: f7ff feba bl 801baa4 <__ulp>
|
|
801bd30: ec51 0b10 vmov r0, r1, d0
|
|
801bd34: b17e cbz r6, 801bd56 <sulp+0x36>
|
|
801bd36: f3c5 530a ubfx r3, r5, #20, #11
|
|
801bd3a: f1c3 036b rsb r3, r3, #107 @ 0x6b
|
|
801bd3e: 2b00 cmp r3, #0
|
|
801bd40: dd09 ble.n 801bd56 <sulp+0x36>
|
|
801bd42: 051b lsls r3, r3, #20
|
|
801bd44: f103 557f add.w r5, r3, #1069547520 @ 0x3fc00000
|
|
801bd48: 2400 movs r4, #0
|
|
801bd4a: f505 1540 add.w r5, r5, #3145728 @ 0x300000
|
|
801bd4e: 4622 mov r2, r4
|
|
801bd50: 462b mov r3, r5
|
|
801bd52: f7e4 fc29 bl 80005a8 <__aeabi_dmul>
|
|
801bd56: ec41 0b10 vmov d0, r0, r1
|
|
801bd5a: bd70 pop {r4, r5, r6, pc}
|
|
801bd5c: 0000 movs r0, r0
|
|
...
|
|
|
|
0801bd60 <_strtod_l>:
|
|
801bd60: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801bd64: b09d sub sp, #116 @ 0x74
|
|
801bd66: 460e mov r6, r1
|
|
801bd68: 9215 str r2, [sp, #84] @ 0x54
|
|
801bd6a: 2200 movs r2, #0
|
|
801bd6c: 9004 str r0, [sp, #16]
|
|
801bd6e: 9218 str r2, [sp, #96] @ 0x60
|
|
801bd70: f04f 0800 mov.w r8, #0
|
|
801bd74: f04f 0900 mov.w r9, #0
|
|
801bd78: 9117 str r1, [sp, #92] @ 0x5c
|
|
801bd7a: 780a ldrb r2, [r1, #0]
|
|
801bd7c: 2a2b cmp r2, #43 @ 0x2b
|
|
801bd7e: 460d mov r5, r1
|
|
801bd80: f101 0101 add.w r1, r1, #1
|
|
801bd84: d01d beq.n 801bdc2 <_strtod_l+0x62>
|
|
801bd86: d80b bhi.n 801bda0 <_strtod_l+0x40>
|
|
801bd88: 2a0d cmp r2, #13
|
|
801bd8a: d806 bhi.n 801bd9a <_strtod_l+0x3a>
|
|
801bd8c: 2a08 cmp r2, #8
|
|
801bd8e: d8f3 bhi.n 801bd78 <_strtod_l+0x18>
|
|
801bd90: b17a cbz r2, 801bdb2 <_strtod_l+0x52>
|
|
801bd92: 2300 movs r3, #0
|
|
801bd94: 930b str r3, [sp, #44] @ 0x2c
|
|
801bd96: 469a mov sl, r3
|
|
801bd98: e083 b.n 801bea2 <_strtod_l+0x142>
|
|
801bd9a: 2a20 cmp r2, #32
|
|
801bd9c: d0ec beq.n 801bd78 <_strtod_l+0x18>
|
|
801bd9e: e7f8 b.n 801bd92 <_strtod_l+0x32>
|
|
801bda0: 2a2d cmp r2, #45 @ 0x2d
|
|
801bda2: d110 bne.n 801bdc6 <_strtod_l+0x66>
|
|
801bda4: 2201 movs r2, #1
|
|
801bda6: 1c69 adds r1, r5, #1
|
|
801bda8: 9117 str r1, [sp, #92] @ 0x5c
|
|
801bdaa: 920b str r2, [sp, #44] @ 0x2c
|
|
801bdac: 786a ldrb r2, [r5, #1]
|
|
801bdae: 2a00 cmp r2, #0
|
|
801bdb0: d137 bne.n 801be22 <_strtod_l+0xc2>
|
|
801bdb2: 9b15 ldr r3, [sp, #84] @ 0x54
|
|
801bdb4: 9617 str r6, [sp, #92] @ 0x5c
|
|
801bdb6: 2b00 cmp r3, #0
|
|
801bdb8: f040 8595 bne.w 801c8e6 <_strtod_l+0xb86>
|
|
801bdbc: 4642 mov r2, r8
|
|
801bdbe: 464b mov r3, r9
|
|
801bdc0: e02a b.n 801be18 <_strtod_l+0xb8>
|
|
801bdc2: 2200 movs r2, #0
|
|
801bdc4: e7ef b.n 801bda6 <_strtod_l+0x46>
|
|
801bdc6: 2100 movs r1, #0
|
|
801bdc8: 910b str r1, [sp, #44] @ 0x2c
|
|
801bdca: 2a30 cmp r2, #48 @ 0x30
|
|
801bdcc: f040 809b bne.w 801bf06 <_strtod_l+0x1a6>
|
|
801bdd0: 786a ldrb r2, [r5, #1]
|
|
801bdd2: f002 02df and.w r2, r2, #223 @ 0xdf
|
|
801bdd6: 2a58 cmp r2, #88 @ 0x58
|
|
801bdd8: d15a bne.n 801be90 <_strtod_l+0x130>
|
|
801bdda: 9302 str r3, [sp, #8]
|
|
801bddc: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
801bdde: 9301 str r3, [sp, #4]
|
|
801bde0: ab18 add r3, sp, #96 @ 0x60
|
|
801bde2: 9300 str r3, [sp, #0]
|
|
801bde4: 4a81 ldr r2, [pc, #516] @ (801bfec <_strtod_l+0x28c>)
|
|
801bde6: 9804 ldr r0, [sp, #16]
|
|
801bde8: ab19 add r3, sp, #100 @ 0x64
|
|
801bdea: a917 add r1, sp, #92 @ 0x5c
|
|
801bdec: f001 fac6 bl 801d37c <__gethex>
|
|
801bdf0: f010 060f ands.w r6, r0, #15
|
|
801bdf4: 4604 mov r4, r0
|
|
801bdf6: d005 beq.n 801be04 <_strtod_l+0xa4>
|
|
801bdf8: 2e06 cmp r6, #6
|
|
801bdfa: d114 bne.n 801be26 <_strtod_l+0xc6>
|
|
801bdfc: 3501 adds r5, #1
|
|
801bdfe: 2300 movs r3, #0
|
|
801be00: 9517 str r5, [sp, #92] @ 0x5c
|
|
801be02: 930b str r3, [sp, #44] @ 0x2c
|
|
801be04: 9b15 ldr r3, [sp, #84] @ 0x54
|
|
801be06: 2b00 cmp r3, #0
|
|
801be08: f040 856f bne.w 801c8ea <_strtod_l+0xb8a>
|
|
801be0c: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
801be0e: 2b00 cmp r3, #0
|
|
801be10: d0d4 beq.n 801bdbc <_strtod_l+0x5c>
|
|
801be12: 4642 mov r2, r8
|
|
801be14: f109 4300 add.w r3, r9, #2147483648 @ 0x80000000
|
|
801be18: ec43 2b10 vmov d0, r2, r3
|
|
801be1c: b01d add sp, #116 @ 0x74
|
|
801be1e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801be22: 460d mov r5, r1
|
|
801be24: e7d1 b.n 801bdca <_strtod_l+0x6a>
|
|
801be26: 9a18 ldr r2, [sp, #96] @ 0x60
|
|
801be28: b13a cbz r2, 801be3a <_strtod_l+0xda>
|
|
801be2a: 2135 movs r1, #53 @ 0x35
|
|
801be2c: a81a add r0, sp, #104 @ 0x68
|
|
801be2e: f7ff ff33 bl 801bc98 <__copybits>
|
|
801be32: 9918 ldr r1, [sp, #96] @ 0x60
|
|
801be34: 9804 ldr r0, [sp, #16]
|
|
801be36: f7ff faf9 bl 801b42c <_Bfree>
|
|
801be3a: 3e01 subs r6, #1
|
|
801be3c: 2e04 cmp r6, #4
|
|
801be3e: d806 bhi.n 801be4e <_strtod_l+0xee>
|
|
801be40: e8df f006 tbb [pc, r6]
|
|
801be44: 211e0314 .word 0x211e0314
|
|
801be48: 14 .byte 0x14
|
|
801be49: 00 .byte 0x00
|
|
801be4a: e9dd 891a ldrd r8, r9, [sp, #104] @ 0x68
|
|
801be4e: 05e0 lsls r0, r4, #23
|
|
801be50: bf48 it mi
|
|
801be52: f049 4900 orrmi.w r9, r9, #2147483648 @ 0x80000000
|
|
801be56: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
|
|
801be5a: 0d1b lsrs r3, r3, #20
|
|
801be5c: 051b lsls r3, r3, #20
|
|
801be5e: 2b00 cmp r3, #0
|
|
801be60: d1d0 bne.n 801be04 <_strtod_l+0xa4>
|
|
801be62: f7fe faff bl 801a464 <__errno>
|
|
801be66: 2322 movs r3, #34 @ 0x22
|
|
801be68: 6003 str r3, [r0, #0]
|
|
801be6a: e7cb b.n 801be04 <_strtod_l+0xa4>
|
|
801be6c: e9dd 831a ldrd r8, r3, [sp, #104] @ 0x68
|
|
801be70: 9a19 ldr r2, [sp, #100] @ 0x64
|
|
801be72: f423 1380 bic.w r3, r3, #1048576 @ 0x100000
|
|
801be76: f202 4233 addw r2, r2, #1075 @ 0x433
|
|
801be7a: ea43 5902 orr.w r9, r3, r2, lsl #20
|
|
801be7e: e7e6 b.n 801be4e <_strtod_l+0xee>
|
|
801be80: f8df 9170 ldr.w r9, [pc, #368] @ 801bff4 <_strtod_l+0x294>
|
|
801be84: e7e3 b.n 801be4e <_strtod_l+0xee>
|
|
801be86: f06f 4900 mvn.w r9, #2147483648 @ 0x80000000
|
|
801be8a: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff
|
|
801be8e: e7de b.n 801be4e <_strtod_l+0xee>
|
|
801be90: 3501 adds r5, #1
|
|
801be92: 9517 str r5, [sp, #92] @ 0x5c
|
|
801be94: 782b ldrb r3, [r5, #0]
|
|
801be96: 2b30 cmp r3, #48 @ 0x30
|
|
801be98: d0fa beq.n 801be90 <_strtod_l+0x130>
|
|
801be9a: 2b00 cmp r3, #0
|
|
801be9c: d0b2 beq.n 801be04 <_strtod_l+0xa4>
|
|
801be9e: f04f 0a01 mov.w sl, #1
|
|
801bea2: 2700 movs r7, #0
|
|
801bea4: 462b mov r3, r5
|
|
801bea6: 970e str r7, [sp, #56] @ 0x38
|
|
801bea8: 46bb mov fp, r7
|
|
801beaa: 210a movs r1, #10
|
|
801beac: 4618 mov r0, r3
|
|
801beae: f813 4b01 ldrb.w r4, [r3], #1
|
|
801beb2: f1a4 0230 sub.w r2, r4, #48 @ 0x30
|
|
801beb6: 2a09 cmp r2, #9
|
|
801beb8: d928 bls.n 801bf0c <_strtod_l+0x1ac>
|
|
801beba: 494d ldr r1, [pc, #308] @ (801bff0 <_strtod_l+0x290>)
|
|
801bebc: 2201 movs r2, #1
|
|
801bebe: f001 f998 bl 801d1f2 <strncmp>
|
|
801bec2: 2800 cmp r0, #0
|
|
801bec4: d034 beq.n 801bf30 <_strtod_l+0x1d0>
|
|
801bec6: 2000 movs r0, #0
|
|
801bec8: e9cd 0006 strd r0, r0, [sp, #24]
|
|
801becc: 4622 mov r2, r4
|
|
801bece: 465c mov r4, fp
|
|
801bed0: 2a65 cmp r2, #101 @ 0x65
|
|
801bed2: d001 beq.n 801bed8 <_strtod_l+0x178>
|
|
801bed4: 2a45 cmp r2, #69 @ 0x45
|
|
801bed6: d114 bne.n 801bf02 <_strtod_l+0x1a2>
|
|
801bed8: b924 cbnz r4, 801bee4 <_strtod_l+0x184>
|
|
801beda: ea5a 0300 orrs.w r3, sl, r0
|
|
801bede: f43f af68 beq.w 801bdb2 <_strtod_l+0x52>
|
|
801bee2: 2400 movs r4, #0
|
|
801bee4: 9e17 ldr r6, [sp, #92] @ 0x5c
|
|
801bee6: 1c73 adds r3, r6, #1
|
|
801bee8: 9317 str r3, [sp, #92] @ 0x5c
|
|
801beea: 7872 ldrb r2, [r6, #1]
|
|
801beec: 2a2b cmp r2, #43 @ 0x2b
|
|
801beee: d073 beq.n 801bfd8 <_strtod_l+0x278>
|
|
801bef0: 2a2d cmp r2, #45 @ 0x2d
|
|
801bef2: d077 beq.n 801bfe4 <_strtod_l+0x284>
|
|
801bef4: f04f 0c00 mov.w ip, #0
|
|
801bef8: f1a2 0330 sub.w r3, r2, #48 @ 0x30
|
|
801befc: 2b09 cmp r3, #9
|
|
801befe: d97f bls.n 801c000 <_strtod_l+0x2a0>
|
|
801bf00: 9617 str r6, [sp, #92] @ 0x5c
|
|
801bf02: 2300 movs r3, #0
|
|
801bf04: e09e b.n 801c044 <_strtod_l+0x2e4>
|
|
801bf06: f04f 0a00 mov.w sl, #0
|
|
801bf0a: e7ca b.n 801bea2 <_strtod_l+0x142>
|
|
801bf0c: f1bb 0f08 cmp.w fp, #8
|
|
801bf10: bfd8 it le
|
|
801bf12: 9a0e ldrle r2, [sp, #56] @ 0x38
|
|
801bf14: 9317 str r3, [sp, #92] @ 0x5c
|
|
801bf16: bfdb ittet le
|
|
801bf18: fb01 4202 mlale r2, r1, r2, r4
|
|
801bf1c: 3a30 suble r2, #48 @ 0x30
|
|
801bf1e: fb01 4207 mlagt r2, r1, r7, r4
|
|
801bf22: 920e strle r2, [sp, #56] @ 0x38
|
|
801bf24: bfc8 it gt
|
|
801bf26: f1a2 0730 subgt.w r7, r2, #48 @ 0x30
|
|
801bf2a: f10b 0b01 add.w fp, fp, #1
|
|
801bf2e: e7bd b.n 801beac <_strtod_l+0x14c>
|
|
801bf30: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801bf32: 1c5a adds r2, r3, #1
|
|
801bf34: 9217 str r2, [sp, #92] @ 0x5c
|
|
801bf36: 785a ldrb r2, [r3, #1]
|
|
801bf38: f1bb 0f00 cmp.w fp, #0
|
|
801bf3c: d033 beq.n 801bfa6 <_strtod_l+0x246>
|
|
801bf3e: 9006 str r0, [sp, #24]
|
|
801bf40: 465c mov r4, fp
|
|
801bf42: f1a2 0330 sub.w r3, r2, #48 @ 0x30
|
|
801bf46: 2b09 cmp r3, #9
|
|
801bf48: d912 bls.n 801bf70 <_strtod_l+0x210>
|
|
801bf4a: 2301 movs r3, #1
|
|
801bf4c: 9307 str r3, [sp, #28]
|
|
801bf4e: e7bf b.n 801bed0 <_strtod_l+0x170>
|
|
801bf50: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801bf52: 1c5a adds r2, r3, #1
|
|
801bf54: 9217 str r2, [sp, #92] @ 0x5c
|
|
801bf56: 785a ldrb r2, [r3, #1]
|
|
801bf58: 3001 adds r0, #1
|
|
801bf5a: 2a30 cmp r2, #48 @ 0x30
|
|
801bf5c: d0f8 beq.n 801bf50 <_strtod_l+0x1f0>
|
|
801bf5e: f1a2 0331 sub.w r3, r2, #49 @ 0x31
|
|
801bf62: 2b08 cmp r3, #8
|
|
801bf64: f200 84c6 bhi.w 801c8f4 <_strtod_l+0xb94>
|
|
801bf68: 9006 str r0, [sp, #24]
|
|
801bf6a: 9d17 ldr r5, [sp, #92] @ 0x5c
|
|
801bf6c: 2000 movs r0, #0
|
|
801bf6e: 4604 mov r4, r0
|
|
801bf70: 3a30 subs r2, #48 @ 0x30
|
|
801bf72: f100 0301 add.w r3, r0, #1
|
|
801bf76: d010 beq.n 801bf9a <_strtod_l+0x23a>
|
|
801bf78: 9906 ldr r1, [sp, #24]
|
|
801bf7a: 4419 add r1, r3
|
|
801bf7c: 9106 str r1, [sp, #24]
|
|
801bf7e: 4420 add r0, r4
|
|
801bf80: 230a movs r3, #10
|
|
801bf82: 42a0 cmp r0, r4
|
|
801bf84: d111 bne.n 801bfaa <_strtod_l+0x24a>
|
|
801bf86: 2808 cmp r0, #8
|
|
801bf88: f100 0401 add.w r4, r0, #1
|
|
801bf8c: dc19 bgt.n 801bfc2 <_strtod_l+0x262>
|
|
801bf8e: 990e ldr r1, [sp, #56] @ 0x38
|
|
801bf90: 230a movs r3, #10
|
|
801bf92: fb03 2301 mla r3, r3, r1, r2
|
|
801bf96: 930e str r3, [sp, #56] @ 0x38
|
|
801bf98: 2300 movs r3, #0
|
|
801bf9a: 9a17 ldr r2, [sp, #92] @ 0x5c
|
|
801bf9c: 1c51 adds r1, r2, #1
|
|
801bf9e: 9117 str r1, [sp, #92] @ 0x5c
|
|
801bfa0: 7852 ldrb r2, [r2, #1]
|
|
801bfa2: 4618 mov r0, r3
|
|
801bfa4: e7cd b.n 801bf42 <_strtod_l+0x1e2>
|
|
801bfa6: 4658 mov r0, fp
|
|
801bfa8: e7d7 b.n 801bf5a <_strtod_l+0x1fa>
|
|
801bfaa: 2c08 cmp r4, #8
|
|
801bfac: f104 0401 add.w r4, r4, #1
|
|
801bfb0: dc03 bgt.n 801bfba <_strtod_l+0x25a>
|
|
801bfb2: 990e ldr r1, [sp, #56] @ 0x38
|
|
801bfb4: 4359 muls r1, r3
|
|
801bfb6: 910e str r1, [sp, #56] @ 0x38
|
|
801bfb8: e7e3 b.n 801bf82 <_strtod_l+0x222>
|
|
801bfba: 2c10 cmp r4, #16
|
|
801bfbc: bfd8 it le
|
|
801bfbe: 435f mulle r7, r3
|
|
801bfc0: e7df b.n 801bf82 <_strtod_l+0x222>
|
|
801bfc2: 280f cmp r0, #15
|
|
801bfc4: bfdc itt le
|
|
801bfc6: 230a movle r3, #10
|
|
801bfc8: fb03 2707 mlale r7, r3, r7, r2
|
|
801bfcc: e7e4 b.n 801bf98 <_strtod_l+0x238>
|
|
801bfce: 2100 movs r1, #0
|
|
801bfd0: 2301 movs r3, #1
|
|
801bfd2: e9cd 1306 strd r1, r3, [sp, #24]
|
|
801bfd6: e780 b.n 801beda <_strtod_l+0x17a>
|
|
801bfd8: f04f 0c00 mov.w ip, #0
|
|
801bfdc: 1cb3 adds r3, r6, #2
|
|
801bfde: 9317 str r3, [sp, #92] @ 0x5c
|
|
801bfe0: 78b2 ldrb r2, [r6, #2]
|
|
801bfe2: e789 b.n 801bef8 <_strtod_l+0x198>
|
|
801bfe4: f04f 0c01 mov.w ip, #1
|
|
801bfe8: e7f8 b.n 801bfdc <_strtod_l+0x27c>
|
|
801bfea: bf00 nop
|
|
801bfec: 0801e8fc .word 0x0801e8fc
|
|
801bff0: 0801e72f .word 0x0801e72f
|
|
801bff4: 7ff00000 .word 0x7ff00000
|
|
801bff8: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801bffa: 1c5a adds r2, r3, #1
|
|
801bffc: 9217 str r2, [sp, #92] @ 0x5c
|
|
801bffe: 785a ldrb r2, [r3, #1]
|
|
801c000: 2a30 cmp r2, #48 @ 0x30
|
|
801c002: d0f9 beq.n 801bff8 <_strtod_l+0x298>
|
|
801c004: f1a2 0331 sub.w r3, r2, #49 @ 0x31
|
|
801c008: 2b08 cmp r3, #8
|
|
801c00a: f63f af7a bhi.w 801bf02 <_strtod_l+0x1a2>
|
|
801c00e: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801c010: 9305 str r3, [sp, #20]
|
|
801c012: f1a2 0e30 sub.w lr, r2, #48 @ 0x30
|
|
801c016: 3301 adds r3, #1
|
|
801c018: 9317 str r3, [sp, #92] @ 0x5c
|
|
801c01a: 781a ldrb r2, [r3, #0]
|
|
801c01c: f1a2 0130 sub.w r1, r2, #48 @ 0x30
|
|
801c020: 2909 cmp r1, #9
|
|
801c022: d93c bls.n 801c09e <_strtod_l+0x33e>
|
|
801c024: 9905 ldr r1, [sp, #20]
|
|
801c026: 1a5b subs r3, r3, r1
|
|
801c028: 2b08 cmp r3, #8
|
|
801c02a: f644 631f movw r3, #19999 @ 0x4e1f
|
|
801c02e: dc3c bgt.n 801c0aa <_strtod_l+0x34a>
|
|
801c030: 459e cmp lr, r3
|
|
801c032: 4671 mov r1, lr
|
|
801c034: bfa8 it ge
|
|
801c036: 4619 movge r1, r3
|
|
801c038: 9105 str r1, [sp, #20]
|
|
801c03a: f1bc 0f00 cmp.w ip, #0
|
|
801c03e: d002 beq.n 801c046 <_strtod_l+0x2e6>
|
|
801c040: 9b05 ldr r3, [sp, #20]
|
|
801c042: 425b negs r3, r3
|
|
801c044: 9305 str r3, [sp, #20]
|
|
801c046: 2c00 cmp r4, #0
|
|
801c048: d150 bne.n 801c0ec <_strtod_l+0x38c>
|
|
801c04a: ea5a 0000 orrs.w r0, sl, r0
|
|
801c04e: f47f aed9 bne.w 801be04 <_strtod_l+0xa4>
|
|
801c052: 9b07 ldr r3, [sp, #28]
|
|
801c054: 2b00 cmp r3, #0
|
|
801c056: f47f aeac bne.w 801bdb2 <_strtod_l+0x52>
|
|
801c05a: 2a69 cmp r2, #105 @ 0x69
|
|
801c05c: d029 beq.n 801c0b2 <_strtod_l+0x352>
|
|
801c05e: dc26 bgt.n 801c0ae <_strtod_l+0x34e>
|
|
801c060: 2a49 cmp r2, #73 @ 0x49
|
|
801c062: d026 beq.n 801c0b2 <_strtod_l+0x352>
|
|
801c064: 2a4e cmp r2, #78 @ 0x4e
|
|
801c066: f47f aea4 bne.w 801bdb2 <_strtod_l+0x52>
|
|
801c06a: 49a1 ldr r1, [pc, #644] @ (801c2f0 <_strtod_l+0x590>)
|
|
801c06c: a817 add r0, sp, #92 @ 0x5c
|
|
801c06e: f001 fba7 bl 801d7c0 <__match>
|
|
801c072: 2800 cmp r0, #0
|
|
801c074: f43f ae9d beq.w 801bdb2 <_strtod_l+0x52>
|
|
801c078: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801c07a: 781b ldrb r3, [r3, #0]
|
|
801c07c: 2b28 cmp r3, #40 @ 0x28
|
|
801c07e: d12f bne.n 801c0e0 <_strtod_l+0x380>
|
|
801c080: 499c ldr r1, [pc, #624] @ (801c2f4 <_strtod_l+0x594>)
|
|
801c082: aa1a add r2, sp, #104 @ 0x68
|
|
801c084: a817 add r0, sp, #92 @ 0x5c
|
|
801c086: f001 fbaf bl 801d7e8 <__hexnan>
|
|
801c08a: 2805 cmp r0, #5
|
|
801c08c: d128 bne.n 801c0e0 <_strtod_l+0x380>
|
|
801c08e: 9b1b ldr r3, [sp, #108] @ 0x6c
|
|
801c090: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68
|
|
801c094: f043 49ff orr.w r9, r3, #2139095040 @ 0x7f800000
|
|
801c098: f449 09e0 orr.w r9, r9, #7340032 @ 0x700000
|
|
801c09c: e6b2 b.n 801be04 <_strtod_l+0xa4>
|
|
801c09e: 210a movs r1, #10
|
|
801c0a0: fb01 220e mla r2, r1, lr, r2
|
|
801c0a4: f1a2 0e30 sub.w lr, r2, #48 @ 0x30
|
|
801c0a8: e7b5 b.n 801c016 <_strtod_l+0x2b6>
|
|
801c0aa: 9305 str r3, [sp, #20]
|
|
801c0ac: e7c5 b.n 801c03a <_strtod_l+0x2da>
|
|
801c0ae: 2a6e cmp r2, #110 @ 0x6e
|
|
801c0b0: e7d9 b.n 801c066 <_strtod_l+0x306>
|
|
801c0b2: 4991 ldr r1, [pc, #580] @ (801c2f8 <_strtod_l+0x598>)
|
|
801c0b4: a817 add r0, sp, #92 @ 0x5c
|
|
801c0b6: f001 fb83 bl 801d7c0 <__match>
|
|
801c0ba: 2800 cmp r0, #0
|
|
801c0bc: f43f ae79 beq.w 801bdb2 <_strtod_l+0x52>
|
|
801c0c0: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801c0c2: 498e ldr r1, [pc, #568] @ (801c2fc <_strtod_l+0x59c>)
|
|
801c0c4: 3b01 subs r3, #1
|
|
801c0c6: a817 add r0, sp, #92 @ 0x5c
|
|
801c0c8: 9317 str r3, [sp, #92] @ 0x5c
|
|
801c0ca: f001 fb79 bl 801d7c0 <__match>
|
|
801c0ce: b910 cbnz r0, 801c0d6 <_strtod_l+0x376>
|
|
801c0d0: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801c0d2: 3301 adds r3, #1
|
|
801c0d4: 9317 str r3, [sp, #92] @ 0x5c
|
|
801c0d6: f8df 9234 ldr.w r9, [pc, #564] @ 801c30c <_strtod_l+0x5ac>
|
|
801c0da: f04f 0800 mov.w r8, #0
|
|
801c0de: e691 b.n 801be04 <_strtod_l+0xa4>
|
|
801c0e0: 4887 ldr r0, [pc, #540] @ (801c300 <_strtod_l+0x5a0>)
|
|
801c0e2: f001 f8a9 bl 801d238 <nan>
|
|
801c0e6: ec59 8b10 vmov r8, r9, d0
|
|
801c0ea: e68b b.n 801be04 <_strtod_l+0xa4>
|
|
801c0ec: e9dd 3205 ldrd r3, r2, [sp, #20]
|
|
801c0f0: 980e ldr r0, [sp, #56] @ 0x38
|
|
801c0f2: 1a9b subs r3, r3, r2
|
|
801c0f4: f1bb 0f00 cmp.w fp, #0
|
|
801c0f8: bf08 it eq
|
|
801c0fa: 46a3 moveq fp, r4
|
|
801c0fc: 2c10 cmp r4, #16
|
|
801c0fe: 930a str r3, [sp, #40] @ 0x28
|
|
801c100: 46a2 mov sl, r4
|
|
801c102: bfa8 it ge
|
|
801c104: f04f 0a10 movge.w sl, #16
|
|
801c108: f7e4 f9d4 bl 80004b4 <__aeabi_ui2d>
|
|
801c10c: 2c09 cmp r4, #9
|
|
801c10e: 4680 mov r8, r0
|
|
801c110: 4689 mov r9, r1
|
|
801c112: dc13 bgt.n 801c13c <_strtod_l+0x3dc>
|
|
801c114: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801c116: 2b00 cmp r3, #0
|
|
801c118: f43f ae74 beq.w 801be04 <_strtod_l+0xa4>
|
|
801c11c: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801c11e: dd73 ble.n 801c208 <_strtod_l+0x4a8>
|
|
801c120: 2b16 cmp r3, #22
|
|
801c122: dc5a bgt.n 801c1da <_strtod_l+0x47a>
|
|
801c124: 4977 ldr r1, [pc, #476] @ (801c304 <_strtod_l+0x5a4>)
|
|
801c126: eb01 01c3 add.w r1, r1, r3, lsl #3
|
|
801c12a: e9d1 0100 ldrd r0, r1, [r1]
|
|
801c12e: 4642 mov r2, r8
|
|
801c130: 464b mov r3, r9
|
|
801c132: f7e4 fa39 bl 80005a8 <__aeabi_dmul>
|
|
801c136: 4680 mov r8, r0
|
|
801c138: 4689 mov r9, r1
|
|
801c13a: e663 b.n 801be04 <_strtod_l+0xa4>
|
|
801c13c: 4b71 ldr r3, [pc, #452] @ (801c304 <_strtod_l+0x5a4>)
|
|
801c13e: eb03 03ca add.w r3, r3, sl, lsl #3
|
|
801c142: e953 2312 ldrd r2, r3, [r3, #-72] @ 0x48
|
|
801c146: f7e4 fa2f bl 80005a8 <__aeabi_dmul>
|
|
801c14a: 4680 mov r8, r0
|
|
801c14c: 4638 mov r0, r7
|
|
801c14e: 4689 mov r9, r1
|
|
801c150: f7e4 f9b0 bl 80004b4 <__aeabi_ui2d>
|
|
801c154: 4602 mov r2, r0
|
|
801c156: 460b mov r3, r1
|
|
801c158: 4640 mov r0, r8
|
|
801c15a: 4649 mov r1, r9
|
|
801c15c: f7e4 f86e bl 800023c <__adddf3>
|
|
801c160: 2c0f cmp r4, #15
|
|
801c162: 4680 mov r8, r0
|
|
801c164: 4689 mov r9, r1
|
|
801c166: ddd5 ble.n 801c114 <_strtod_l+0x3b4>
|
|
801c168: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801c16a: eba4 0a0a sub.w sl, r4, sl
|
|
801c16e: 449a add sl, r3
|
|
801c170: f1ba 0f00 cmp.w sl, #0
|
|
801c174: f340 8097 ble.w 801c2a6 <_strtod_l+0x546>
|
|
801c178: f02a 060f bic.w r6, sl, #15
|
|
801c17c: f01a 0a0f ands.w sl, sl, #15
|
|
801c180: d151 bne.n 801c226 <_strtod_l+0x4c6>
|
|
801c182: f5b6 7f9a cmp.w r6, #308 @ 0x134
|
|
801c186: dc5e bgt.n 801c246 <_strtod_l+0x4e6>
|
|
801c188: 2300 movs r3, #0
|
|
801c18a: f8df a17c ldr.w sl, [pc, #380] @ 801c308 <_strtod_l+0x5a8>
|
|
801c18e: 1136 asrs r6, r6, #4
|
|
801c190: 4640 mov r0, r8
|
|
801c192: 4649 mov r1, r9
|
|
801c194: 461f mov r7, r3
|
|
801c196: 2e01 cmp r6, #1
|
|
801c198: d179 bne.n 801c28e <_strtod_l+0x52e>
|
|
801c19a: b10b cbz r3, 801c1a0 <_strtod_l+0x440>
|
|
801c19c: 4680 mov r8, r0
|
|
801c19e: 4689 mov r9, r1
|
|
801c1a0: 4959 ldr r1, [pc, #356] @ (801c308 <_strtod_l+0x5a8>)
|
|
801c1a2: f1a9 7954 sub.w r9, r9, #55574528 @ 0x3500000
|
|
801c1a6: eb01 01c7 add.w r1, r1, r7, lsl #3
|
|
801c1aa: 4642 mov r2, r8
|
|
801c1ac: 464b mov r3, r9
|
|
801c1ae: e9d1 0100 ldrd r0, r1, [r1]
|
|
801c1b2: f7e4 f9f9 bl 80005a8 <__aeabi_dmul>
|
|
801c1b6: 4b55 ldr r3, [pc, #340] @ (801c30c <_strtod_l+0x5ac>)
|
|
801c1b8: 460a mov r2, r1
|
|
801c1ba: 400b ands r3, r1
|
|
801c1bc: 4954 ldr r1, [pc, #336] @ (801c310 <_strtod_l+0x5b0>)
|
|
801c1be: 428b cmp r3, r1
|
|
801c1c0: 4680 mov r8, r0
|
|
801c1c2: d840 bhi.n 801c246 <_strtod_l+0x4e6>
|
|
801c1c4: f5a1 1180 sub.w r1, r1, #1048576 @ 0x100000
|
|
801c1c8: 428b cmp r3, r1
|
|
801c1ca: bf86 itte hi
|
|
801c1cc: f8df 9144 ldrhi.w r9, [pc, #324] @ 801c314 <_strtod_l+0x5b4>
|
|
801c1d0: f04f 38ff movhi.w r8, #4294967295 @ 0xffffffff
|
|
801c1d4: f102 7954 addls.w r9, r2, #55574528 @ 0x3500000
|
|
801c1d8: e032 b.n 801c240 <_strtod_l+0x4e0>
|
|
801c1da: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
801c1dc: f1c4 0325 rsb r3, r4, #37 @ 0x25
|
|
801c1e0: 4293 cmp r3, r2
|
|
801c1e2: dbc1 blt.n 801c168 <_strtod_l+0x408>
|
|
801c1e4: 4d47 ldr r5, [pc, #284] @ (801c304 <_strtod_l+0x5a4>)
|
|
801c1e6: f1c4 040f rsb r4, r4, #15
|
|
801c1ea: eb05 01c4 add.w r1, r5, r4, lsl #3
|
|
801c1ee: 4642 mov r2, r8
|
|
801c1f0: 464b mov r3, r9
|
|
801c1f2: e9d1 0100 ldrd r0, r1, [r1]
|
|
801c1f6: f7e4 f9d7 bl 80005a8 <__aeabi_dmul>
|
|
801c1fa: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801c1fc: 1b1c subs r4, r3, r4
|
|
801c1fe: eb05 05c4 add.w r5, r5, r4, lsl #3
|
|
801c202: e9d5 2300 ldrd r2, r3, [r5]
|
|
801c206: e794 b.n 801c132 <_strtod_l+0x3d2>
|
|
801c208: 3316 adds r3, #22
|
|
801c20a: dbad blt.n 801c168 <_strtod_l+0x408>
|
|
801c20c: e9dd 2305 ldrd r2, r3, [sp, #20]
|
|
801c210: 1a9a subs r2, r3, r2
|
|
801c212: 4b3c ldr r3, [pc, #240] @ (801c304 <_strtod_l+0x5a4>)
|
|
801c214: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
801c218: e9d3 2300 ldrd r2, r3, [r3]
|
|
801c21c: 4640 mov r0, r8
|
|
801c21e: 4649 mov r1, r9
|
|
801c220: f7e4 faec bl 80007fc <__aeabi_ddiv>
|
|
801c224: e787 b.n 801c136 <_strtod_l+0x3d6>
|
|
801c226: 4937 ldr r1, [pc, #220] @ (801c304 <_strtod_l+0x5a4>)
|
|
801c228: eb01 01ca add.w r1, r1, sl, lsl #3
|
|
801c22c: 4642 mov r2, r8
|
|
801c22e: 464b mov r3, r9
|
|
801c230: e9d1 0100 ldrd r0, r1, [r1]
|
|
801c234: f7e4 f9b8 bl 80005a8 <__aeabi_dmul>
|
|
801c238: 4680 mov r8, r0
|
|
801c23a: 4689 mov r9, r1
|
|
801c23c: 2e00 cmp r6, #0
|
|
801c23e: d1a0 bne.n 801c182 <_strtod_l+0x422>
|
|
801c240: 2300 movs r3, #0
|
|
801c242: 9307 str r3, [sp, #28]
|
|
801c244: e0a0 b.n 801c388 <_strtod_l+0x628>
|
|
801c246: 2400 movs r4, #0
|
|
801c248: 9405 str r4, [sp, #20]
|
|
801c24a: 940e str r4, [sp, #56] @ 0x38
|
|
801c24c: 9406 str r4, [sp, #24]
|
|
801c24e: 9a04 ldr r2, [sp, #16]
|
|
801c250: f8df 90b8 ldr.w r9, [pc, #184] @ 801c30c <_strtod_l+0x5ac>
|
|
801c254: 2322 movs r3, #34 @ 0x22
|
|
801c256: 6013 str r3, [r2, #0]
|
|
801c258: f04f 0800 mov.w r8, #0
|
|
801c25c: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
801c25e: 2b00 cmp r3, #0
|
|
801c260: f43f add0 beq.w 801be04 <_strtod_l+0xa4>
|
|
801c264: 9918 ldr r1, [sp, #96] @ 0x60
|
|
801c266: 9804 ldr r0, [sp, #16]
|
|
801c268: f7ff f8e0 bl 801b42c <_Bfree>
|
|
801c26c: 9906 ldr r1, [sp, #24]
|
|
801c26e: 9804 ldr r0, [sp, #16]
|
|
801c270: f7ff f8dc bl 801b42c <_Bfree>
|
|
801c274: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
801c278: f7ff f8d8 bl 801b42c <_Bfree>
|
|
801c27c: 990e ldr r1, [sp, #56] @ 0x38
|
|
801c27e: 9804 ldr r0, [sp, #16]
|
|
801c280: f7ff f8d4 bl 801b42c <_Bfree>
|
|
801c284: 9804 ldr r0, [sp, #16]
|
|
801c286: 4621 mov r1, r4
|
|
801c288: f7ff f8d0 bl 801b42c <_Bfree>
|
|
801c28c: e5ba b.n 801be04 <_strtod_l+0xa4>
|
|
801c28e: 07f2 lsls r2, r6, #31
|
|
801c290: d504 bpl.n 801c29c <_strtod_l+0x53c>
|
|
801c292: e9da 2300 ldrd r2, r3, [sl]
|
|
801c296: f7e4 f987 bl 80005a8 <__aeabi_dmul>
|
|
801c29a: 2301 movs r3, #1
|
|
801c29c: 3701 adds r7, #1
|
|
801c29e: 1076 asrs r6, r6, #1
|
|
801c2a0: f10a 0a08 add.w sl, sl, #8
|
|
801c2a4: e777 b.n 801c196 <_strtod_l+0x436>
|
|
801c2a6: d0cb beq.n 801c240 <_strtod_l+0x4e0>
|
|
801c2a8: f1ca 0a00 rsb sl, sl, #0
|
|
801c2ac: ea4f 162a mov.w r6, sl, asr #4
|
|
801c2b0: f01a 0a0f ands.w sl, sl, #15
|
|
801c2b4: d10d bne.n 801c2d2 <_strtod_l+0x572>
|
|
801c2b6: 2e1f cmp r6, #31
|
|
801c2b8: dd2e ble.n 801c318 <_strtod_l+0x5b8>
|
|
801c2ba: 2400 movs r4, #0
|
|
801c2bc: 9405 str r4, [sp, #20]
|
|
801c2be: 940e str r4, [sp, #56] @ 0x38
|
|
801c2c0: 9406 str r4, [sp, #24]
|
|
801c2c2: 9a04 ldr r2, [sp, #16]
|
|
801c2c4: 2322 movs r3, #34 @ 0x22
|
|
801c2c6: f04f 0800 mov.w r8, #0
|
|
801c2ca: f04f 0900 mov.w r9, #0
|
|
801c2ce: 6013 str r3, [r2, #0]
|
|
801c2d0: e7c4 b.n 801c25c <_strtod_l+0x4fc>
|
|
801c2d2: 4b0c ldr r3, [pc, #48] @ (801c304 <_strtod_l+0x5a4>)
|
|
801c2d4: eb03 03ca add.w r3, r3, sl, lsl #3
|
|
801c2d8: 4640 mov r0, r8
|
|
801c2da: 4649 mov r1, r9
|
|
801c2dc: e9d3 2300 ldrd r2, r3, [r3]
|
|
801c2e0: f7e4 fa8c bl 80007fc <__aeabi_ddiv>
|
|
801c2e4: 4680 mov r8, r0
|
|
801c2e6: 4689 mov r9, r1
|
|
801c2e8: 2e00 cmp r6, #0
|
|
801c2ea: d0a9 beq.n 801c240 <_strtod_l+0x4e0>
|
|
801c2ec: e7e3 b.n 801c2b6 <_strtod_l+0x556>
|
|
801c2ee: bf00 nop
|
|
801c2f0: 0801e61d .word 0x0801e61d
|
|
801c2f4: 0801e8e8 .word 0x0801e8e8
|
|
801c2f8: 0801e615 .word 0x0801e615
|
|
801c2fc: 0801e64c .word 0x0801e64c
|
|
801c300: 0801e785 .word 0x0801e785
|
|
801c304: 0801e820 .word 0x0801e820
|
|
801c308: 0801e7f8 .word 0x0801e7f8
|
|
801c30c: 7ff00000 .word 0x7ff00000
|
|
801c310: 7ca00000 .word 0x7ca00000
|
|
801c314: 7fefffff .word 0x7fefffff
|
|
801c318: f016 0310 ands.w r3, r6, #16
|
|
801c31c: bf18 it ne
|
|
801c31e: 236a movne r3, #106 @ 0x6a
|
|
801c320: 4f76 ldr r7, [pc, #472] @ (801c4fc <_strtod_l+0x79c>)
|
|
801c322: 9307 str r3, [sp, #28]
|
|
801c324: 4640 mov r0, r8
|
|
801c326: 4649 mov r1, r9
|
|
801c328: 2300 movs r3, #0
|
|
801c32a: 07f2 lsls r2, r6, #31
|
|
801c32c: d504 bpl.n 801c338 <_strtod_l+0x5d8>
|
|
801c32e: e9d7 2300 ldrd r2, r3, [r7]
|
|
801c332: f7e4 f939 bl 80005a8 <__aeabi_dmul>
|
|
801c336: 2301 movs r3, #1
|
|
801c338: 1076 asrs r6, r6, #1
|
|
801c33a: f107 0708 add.w r7, r7, #8
|
|
801c33e: d1f4 bne.n 801c32a <_strtod_l+0x5ca>
|
|
801c340: b10b cbz r3, 801c346 <_strtod_l+0x5e6>
|
|
801c342: 4680 mov r8, r0
|
|
801c344: 4689 mov r9, r1
|
|
801c346: 9b07 ldr r3, [sp, #28]
|
|
801c348: b1b3 cbz r3, 801c378 <_strtod_l+0x618>
|
|
801c34a: f3c9 520a ubfx r2, r9, #20, #11
|
|
801c34e: f1c2 036b rsb r3, r2, #107 @ 0x6b
|
|
801c352: 2b00 cmp r3, #0
|
|
801c354: 4649 mov r1, r9
|
|
801c356: dd0f ble.n 801c378 <_strtod_l+0x618>
|
|
801c358: 2b1f cmp r3, #31
|
|
801c35a: dd57 ble.n 801c40c <_strtod_l+0x6ac>
|
|
801c35c: 2b34 cmp r3, #52 @ 0x34
|
|
801c35e: bfde ittt le
|
|
801c360: f04f 33ff movle.w r3, #4294967295 @ 0xffffffff
|
|
801c364: f1c2 024b rsble r2, r2, #75 @ 0x4b
|
|
801c368: 4093 lslle r3, r2
|
|
801c36a: f04f 0800 mov.w r8, #0
|
|
801c36e: bfcc ite gt
|
|
801c370: f04f 795c movgt.w r9, #57671680 @ 0x3700000
|
|
801c374: ea03 0901 andle.w r9, r3, r1
|
|
801c378: 2200 movs r2, #0
|
|
801c37a: 2300 movs r3, #0
|
|
801c37c: 4640 mov r0, r8
|
|
801c37e: 4649 mov r1, r9
|
|
801c380: f7e4 fb7a bl 8000a78 <__aeabi_dcmpeq>
|
|
801c384: 2800 cmp r0, #0
|
|
801c386: d198 bne.n 801c2ba <_strtod_l+0x55a>
|
|
801c388: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
801c38a: 9300 str r3, [sp, #0]
|
|
801c38c: 9804 ldr r0, [sp, #16]
|
|
801c38e: 4623 mov r3, r4
|
|
801c390: 465a mov r2, fp
|
|
801c392: 4629 mov r1, r5
|
|
801c394: f7ff f8b2 bl 801b4fc <__s2b>
|
|
801c398: 900e str r0, [sp, #56] @ 0x38
|
|
801c39a: 2800 cmp r0, #0
|
|
801c39c: f43f af53 beq.w 801c246 <_strtod_l+0x4e6>
|
|
801c3a0: e9dd 2305 ldrd r2, r3, [sp, #20]
|
|
801c3a4: 1a9b subs r3, r3, r2
|
|
801c3a6: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
801c3a8: 2a00 cmp r2, #0
|
|
801c3aa: bfa8 it ge
|
|
801c3ac: 2300 movge r3, #0
|
|
801c3ae: 9312 str r3, [sp, #72] @ 0x48
|
|
801c3b0: 2400 movs r4, #0
|
|
801c3b2: ea22 73e2 bic.w r3, r2, r2, asr #31
|
|
801c3b6: 9314 str r3, [sp, #80] @ 0x50
|
|
801c3b8: 9405 str r4, [sp, #20]
|
|
801c3ba: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
801c3bc: 9804 ldr r0, [sp, #16]
|
|
801c3be: 6859 ldr r1, [r3, #4]
|
|
801c3c0: f7fe fff6 bl 801b3b0 <_Balloc>
|
|
801c3c4: 9006 str r0, [sp, #24]
|
|
801c3c6: 2800 cmp r0, #0
|
|
801c3c8: f43f af41 beq.w 801c24e <_strtod_l+0x4ee>
|
|
801c3cc: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
801c3ce: 691a ldr r2, [r3, #16]
|
|
801c3d0: 3202 adds r2, #2
|
|
801c3d2: f103 010c add.w r1, r3, #12
|
|
801c3d6: 0092 lsls r2, r2, #2
|
|
801c3d8: 300c adds r0, #12
|
|
801c3da: f7fe f870 bl 801a4be <memcpy>
|
|
801c3de: ec49 8b10 vmov d0, r8, r9
|
|
801c3e2: 9804 ldr r0, [sp, #16]
|
|
801c3e4: aa1a add r2, sp, #104 @ 0x68
|
|
801c3e6: a919 add r1, sp, #100 @ 0x64
|
|
801c3e8: e9cd 890c strd r8, r9, [sp, #48] @ 0x30
|
|
801c3ec: f7ff fbca bl 801bb84 <__d2b>
|
|
801c3f0: 9018 str r0, [sp, #96] @ 0x60
|
|
801c3f2: 2800 cmp r0, #0
|
|
801c3f4: f43f af2b beq.w 801c24e <_strtod_l+0x4ee>
|
|
801c3f8: 9804 ldr r0, [sp, #16]
|
|
801c3fa: 2101 movs r1, #1
|
|
801c3fc: f7ff f914 bl 801b628 <__i2b>
|
|
801c400: 9005 str r0, [sp, #20]
|
|
801c402: 4603 mov r3, r0
|
|
801c404: b948 cbnz r0, 801c41a <_strtod_l+0x6ba>
|
|
801c406: 2300 movs r3, #0
|
|
801c408: 9305 str r3, [sp, #20]
|
|
801c40a: e720 b.n 801c24e <_strtod_l+0x4ee>
|
|
801c40c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
801c410: fa02 f303 lsl.w r3, r2, r3
|
|
801c414: ea03 0808 and.w r8, r3, r8
|
|
801c418: e7ae b.n 801c378 <_strtod_l+0x618>
|
|
801c41a: 9d19 ldr r5, [sp, #100] @ 0x64
|
|
801c41c: 9a1a ldr r2, [sp, #104] @ 0x68
|
|
801c41e: 2d00 cmp r5, #0
|
|
801c420: bfab itete ge
|
|
801c422: 9b12 ldrge r3, [sp, #72] @ 0x48
|
|
801c424: 9b14 ldrlt r3, [sp, #80] @ 0x50
|
|
801c426: 9e14 ldrge r6, [sp, #80] @ 0x50
|
|
801c428: 9f12 ldrlt r7, [sp, #72] @ 0x48
|
|
801c42a: bfac ite ge
|
|
801c42c: 18ef addge r7, r5, r3
|
|
801c42e: 1b5e sublt r6, r3, r5
|
|
801c430: 9b07 ldr r3, [sp, #28]
|
|
801c432: 1aed subs r5, r5, r3
|
|
801c434: 4415 add r5, r2
|
|
801c436: 4b32 ldr r3, [pc, #200] @ (801c500 <_strtod_l+0x7a0>)
|
|
801c438: 3d01 subs r5, #1
|
|
801c43a: 429d cmp r5, r3
|
|
801c43c: f1c2 0236 rsb r2, r2, #54 @ 0x36
|
|
801c440: da4f bge.n 801c4e2 <_strtod_l+0x782>
|
|
801c442: 1b5b subs r3, r3, r5
|
|
801c444: 2b1f cmp r3, #31
|
|
801c446: eba2 0203 sub.w r2, r2, r3
|
|
801c44a: f04f 0101 mov.w r1, #1
|
|
801c44e: dc3c bgt.n 801c4ca <_strtod_l+0x76a>
|
|
801c450: fa01 fa03 lsl.w sl, r1, r3
|
|
801c454: f04f 0b00 mov.w fp, #0
|
|
801c458: 18bd adds r5, r7, r2
|
|
801c45a: 9b07 ldr r3, [sp, #28]
|
|
801c45c: 42af cmp r7, r5
|
|
801c45e: 4416 add r6, r2
|
|
801c460: 441e add r6, r3
|
|
801c462: 463b mov r3, r7
|
|
801c464: bfa8 it ge
|
|
801c466: 462b movge r3, r5
|
|
801c468: 42b3 cmp r3, r6
|
|
801c46a: bfa8 it ge
|
|
801c46c: 4633 movge r3, r6
|
|
801c46e: 2b00 cmp r3, #0
|
|
801c470: bfc2 ittt gt
|
|
801c472: 1aed subgt r5, r5, r3
|
|
801c474: 1af6 subgt r6, r6, r3
|
|
801c476: 1aff subgt r7, r7, r3
|
|
801c478: 9b12 ldr r3, [sp, #72] @ 0x48
|
|
801c47a: 2b00 cmp r3, #0
|
|
801c47c: dd16 ble.n 801c4ac <_strtod_l+0x74c>
|
|
801c47e: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
801c482: 461a mov r2, r3
|
|
801c484: f7ff f990 bl 801b7a8 <__pow5mult>
|
|
801c488: 9005 str r0, [sp, #20]
|
|
801c48a: 2800 cmp r0, #0
|
|
801c48c: d0bb beq.n 801c406 <_strtod_l+0x6a6>
|
|
801c48e: 4601 mov r1, r0
|
|
801c490: 9a18 ldr r2, [sp, #96] @ 0x60
|
|
801c492: 9804 ldr r0, [sp, #16]
|
|
801c494: f7ff f8de bl 801b654 <__multiply>
|
|
801c498: 900f str r0, [sp, #60] @ 0x3c
|
|
801c49a: 2800 cmp r0, #0
|
|
801c49c: f43f aed7 beq.w 801c24e <_strtod_l+0x4ee>
|
|
801c4a0: 9918 ldr r1, [sp, #96] @ 0x60
|
|
801c4a2: 9804 ldr r0, [sp, #16]
|
|
801c4a4: f7fe ffc2 bl 801b42c <_Bfree>
|
|
801c4a8: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801c4aa: 9318 str r3, [sp, #96] @ 0x60
|
|
801c4ac: 2d00 cmp r5, #0
|
|
801c4ae: dc1b bgt.n 801c4e8 <_strtod_l+0x788>
|
|
801c4b0: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
801c4b2: 2b00 cmp r3, #0
|
|
801c4b4: dd26 ble.n 801c504 <_strtod_l+0x7a4>
|
|
801c4b6: 9a14 ldr r2, [sp, #80] @ 0x50
|
|
801c4b8: 9906 ldr r1, [sp, #24]
|
|
801c4ba: 9804 ldr r0, [sp, #16]
|
|
801c4bc: f7ff f974 bl 801b7a8 <__pow5mult>
|
|
801c4c0: 9006 str r0, [sp, #24]
|
|
801c4c2: b9f8 cbnz r0, 801c504 <_strtod_l+0x7a4>
|
|
801c4c4: 2300 movs r3, #0
|
|
801c4c6: 9306 str r3, [sp, #24]
|
|
801c4c8: e6c1 b.n 801c24e <_strtod_l+0x4ee>
|
|
801c4ca: f1c5 457f rsb r5, r5, #4278190080 @ 0xff000000
|
|
801c4ce: f505 057f add.w r5, r5, #16711680 @ 0xff0000
|
|
801c4d2: f505 457b add.w r5, r5, #64256 @ 0xfb00
|
|
801c4d6: 35e2 adds r5, #226 @ 0xe2
|
|
801c4d8: fa01 fb05 lsl.w fp, r1, r5
|
|
801c4dc: f04f 0a01 mov.w sl, #1
|
|
801c4e0: e7ba b.n 801c458 <_strtod_l+0x6f8>
|
|
801c4e2: f04f 0b00 mov.w fp, #0
|
|
801c4e6: e7f9 b.n 801c4dc <_strtod_l+0x77c>
|
|
801c4e8: 9918 ldr r1, [sp, #96] @ 0x60
|
|
801c4ea: 9804 ldr r0, [sp, #16]
|
|
801c4ec: 462a mov r2, r5
|
|
801c4ee: f7ff f9b7 bl 801b860 <__lshift>
|
|
801c4f2: 9018 str r0, [sp, #96] @ 0x60
|
|
801c4f4: 2800 cmp r0, #0
|
|
801c4f6: d1db bne.n 801c4b0 <_strtod_l+0x750>
|
|
801c4f8: e6a9 b.n 801c24e <_strtod_l+0x4ee>
|
|
801c4fa: bf00 nop
|
|
801c4fc: 0801e910 .word 0x0801e910
|
|
801c500: fffffc02 .word 0xfffffc02
|
|
801c504: 2e00 cmp r6, #0
|
|
801c506: dd07 ble.n 801c518 <_strtod_l+0x7b8>
|
|
801c508: 9906 ldr r1, [sp, #24]
|
|
801c50a: 9804 ldr r0, [sp, #16]
|
|
801c50c: 4632 mov r2, r6
|
|
801c50e: f7ff f9a7 bl 801b860 <__lshift>
|
|
801c512: 9006 str r0, [sp, #24]
|
|
801c514: 2800 cmp r0, #0
|
|
801c516: d0d5 beq.n 801c4c4 <_strtod_l+0x764>
|
|
801c518: 2f00 cmp r7, #0
|
|
801c51a: dd08 ble.n 801c52e <_strtod_l+0x7ce>
|
|
801c51c: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
801c520: 463a mov r2, r7
|
|
801c522: f7ff f99d bl 801b860 <__lshift>
|
|
801c526: 9005 str r0, [sp, #20]
|
|
801c528: 2800 cmp r0, #0
|
|
801c52a: f43f ae90 beq.w 801c24e <_strtod_l+0x4ee>
|
|
801c52e: 9a06 ldr r2, [sp, #24]
|
|
801c530: 9918 ldr r1, [sp, #96] @ 0x60
|
|
801c532: 9804 ldr r0, [sp, #16]
|
|
801c534: f7ff fa1e bl 801b974 <__mdiff>
|
|
801c538: 4604 mov r4, r0
|
|
801c53a: 2800 cmp r0, #0
|
|
801c53c: f43f ae87 beq.w 801c24e <_strtod_l+0x4ee>
|
|
801c540: 68c3 ldr r3, [r0, #12]
|
|
801c542: 930f str r3, [sp, #60] @ 0x3c
|
|
801c544: 2300 movs r3, #0
|
|
801c546: 9905 ldr r1, [sp, #20]
|
|
801c548: 60c3 str r3, [r0, #12]
|
|
801c54a: f7ff f9f7 bl 801b93c <__mcmp>
|
|
801c54e: 2800 cmp r0, #0
|
|
801c550: da3c bge.n 801c5cc <_strtod_l+0x86c>
|
|
801c552: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801c554: ea53 0308 orrs.w r3, r3, r8
|
|
801c558: d15e bne.n 801c618 <_strtod_l+0x8b8>
|
|
801c55a: f3c9 0313 ubfx r3, r9, #0, #20
|
|
801c55e: 464d mov r5, r9
|
|
801c560: 2b00 cmp r3, #0
|
|
801c562: d159 bne.n 801c618 <_strtod_l+0x8b8>
|
|
801c564: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
|
|
801c568: 0d1b lsrs r3, r3, #20
|
|
801c56a: 051b lsls r3, r3, #20
|
|
801c56c: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000
|
|
801c570: d952 bls.n 801c618 <_strtod_l+0x8b8>
|
|
801c572: 6963 ldr r3, [r4, #20]
|
|
801c574: b913 cbnz r3, 801c57c <_strtod_l+0x81c>
|
|
801c576: 6923 ldr r3, [r4, #16]
|
|
801c578: 2b01 cmp r3, #1
|
|
801c57a: dd4d ble.n 801c618 <_strtod_l+0x8b8>
|
|
801c57c: 4621 mov r1, r4
|
|
801c57e: 2201 movs r2, #1
|
|
801c580: 9804 ldr r0, [sp, #16]
|
|
801c582: f7ff f96d bl 801b860 <__lshift>
|
|
801c586: 9905 ldr r1, [sp, #20]
|
|
801c588: 4604 mov r4, r0
|
|
801c58a: f7ff f9d7 bl 801b93c <__mcmp>
|
|
801c58e: 2800 cmp r0, #0
|
|
801c590: dd42 ble.n 801c618 <_strtod_l+0x8b8>
|
|
801c592: 4bad ldr r3, [pc, #692] @ (801c848 <_strtod_l+0xae8>)
|
|
801c594: 9a07 ldr r2, [sp, #28]
|
|
801c596: 402b ands r3, r5
|
|
801c598: 2a00 cmp r2, #0
|
|
801c59a: d05f beq.n 801c65c <_strtod_l+0x8fc>
|
|
801c59c: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000
|
|
801c5a0: d85c bhi.n 801c65c <_strtod_l+0x8fc>
|
|
801c5a2: f1b3 7f5c cmp.w r3, #57671680 @ 0x3700000
|
|
801c5a6: f67f ae8c bls.w 801c2c2 <_strtod_l+0x562>
|
|
801c5aa: 4ba8 ldr r3, [pc, #672] @ (801c84c <_strtod_l+0xaec>)
|
|
801c5ac: 4640 mov r0, r8
|
|
801c5ae: 4649 mov r1, r9
|
|
801c5b0: 2200 movs r2, #0
|
|
801c5b2: f7e3 fff9 bl 80005a8 <__aeabi_dmul>
|
|
801c5b6: 4ba4 ldr r3, [pc, #656] @ (801c848 <_strtod_l+0xae8>)
|
|
801c5b8: 400b ands r3, r1
|
|
801c5ba: 4680 mov r8, r0
|
|
801c5bc: 4689 mov r9, r1
|
|
801c5be: 2b00 cmp r3, #0
|
|
801c5c0: f47f ae50 bne.w 801c264 <_strtod_l+0x504>
|
|
801c5c4: 9a04 ldr r2, [sp, #16]
|
|
801c5c6: 2322 movs r3, #34 @ 0x22
|
|
801c5c8: 6013 str r3, [r2, #0]
|
|
801c5ca: e64b b.n 801c264 <_strtod_l+0x504>
|
|
801c5cc: 464d mov r5, r9
|
|
801c5ce: d162 bne.n 801c696 <_strtod_l+0x936>
|
|
801c5d0: 9a0f ldr r2, [sp, #60] @ 0x3c
|
|
801c5d2: f3c9 0313 ubfx r3, r9, #0, #20
|
|
801c5d6: b342 cbz r2, 801c62a <_strtod_l+0x8ca>
|
|
801c5d8: 4a9d ldr r2, [pc, #628] @ (801c850 <_strtod_l+0xaf0>)
|
|
801c5da: 4293 cmp r3, r2
|
|
801c5dc: d128 bne.n 801c630 <_strtod_l+0x8d0>
|
|
801c5de: 9b07 ldr r3, [sp, #28]
|
|
801c5e0: 4641 mov r1, r8
|
|
801c5e2: b1eb cbz r3, 801c620 <_strtod_l+0x8c0>
|
|
801c5e4: 4b98 ldr r3, [pc, #608] @ (801c848 <_strtod_l+0xae8>)
|
|
801c5e6: 402b ands r3, r5
|
|
801c5e8: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000
|
|
801c5ec: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
801c5f0: d819 bhi.n 801c626 <_strtod_l+0x8c6>
|
|
801c5f2: 0d1b lsrs r3, r3, #20
|
|
801c5f4: f1c3 036b rsb r3, r3, #107 @ 0x6b
|
|
801c5f8: fa02 f303 lsl.w r3, r2, r3
|
|
801c5fc: 4299 cmp r1, r3
|
|
801c5fe: d117 bne.n 801c630 <_strtod_l+0x8d0>
|
|
801c600: 4b94 ldr r3, [pc, #592] @ (801c854 <_strtod_l+0xaf4>)
|
|
801c602: 429d cmp r5, r3
|
|
801c604: d102 bne.n 801c60c <_strtod_l+0x8ac>
|
|
801c606: 3101 adds r1, #1
|
|
801c608: f43f ae21 beq.w 801c24e <_strtod_l+0x4ee>
|
|
801c60c: 4b8e ldr r3, [pc, #568] @ (801c848 <_strtod_l+0xae8>)
|
|
801c60e: 402b ands r3, r5
|
|
801c610: f503 1980 add.w r9, r3, #1048576 @ 0x100000
|
|
801c614: f04f 0800 mov.w r8, #0
|
|
801c618: 9b07 ldr r3, [sp, #28]
|
|
801c61a: 2b00 cmp r3, #0
|
|
801c61c: d1c5 bne.n 801c5aa <_strtod_l+0x84a>
|
|
801c61e: e621 b.n 801c264 <_strtod_l+0x504>
|
|
801c620: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
801c624: e7ea b.n 801c5fc <_strtod_l+0x89c>
|
|
801c626: 4613 mov r3, r2
|
|
801c628: e7e8 b.n 801c5fc <_strtod_l+0x89c>
|
|
801c62a: ea53 0308 orrs.w r3, r3, r8
|
|
801c62e: d0b0 beq.n 801c592 <_strtod_l+0x832>
|
|
801c630: f1bb 0f00 cmp.w fp, #0
|
|
801c634: d01b beq.n 801c66e <_strtod_l+0x90e>
|
|
801c636: ea1b 0f05 tst.w fp, r5
|
|
801c63a: d0ed beq.n 801c618 <_strtod_l+0x8b8>
|
|
801c63c: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801c63e: 9a07 ldr r2, [sp, #28]
|
|
801c640: 4640 mov r0, r8
|
|
801c642: 4649 mov r1, r9
|
|
801c644: b1b3 cbz r3, 801c674 <_strtod_l+0x914>
|
|
801c646: f7ff fb6b bl 801bd20 <sulp>
|
|
801c64a: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30
|
|
801c64e: ec53 2b10 vmov r2, r3, d0
|
|
801c652: f7e3 fdf3 bl 800023c <__adddf3>
|
|
801c656: 4680 mov r8, r0
|
|
801c658: 4689 mov r9, r1
|
|
801c65a: e7dd b.n 801c618 <_strtod_l+0x8b8>
|
|
801c65c: f5a3 1380 sub.w r3, r3, #1048576 @ 0x100000
|
|
801c660: ea6f 5913 mvn.w r9, r3, lsr #20
|
|
801c664: ea6f 5909 mvn.w r9, r9, lsl #20
|
|
801c668: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff
|
|
801c66c: e7d4 b.n 801c618 <_strtod_l+0x8b8>
|
|
801c66e: ea1a 0f08 tst.w sl, r8
|
|
801c672: e7e2 b.n 801c63a <_strtod_l+0x8da>
|
|
801c674: f7ff fb54 bl 801bd20 <sulp>
|
|
801c678: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30
|
|
801c67c: ec53 2b10 vmov r2, r3, d0
|
|
801c680: f7e3 fdda bl 8000238 <__aeabi_dsub>
|
|
801c684: 2200 movs r2, #0
|
|
801c686: 2300 movs r3, #0
|
|
801c688: 4680 mov r8, r0
|
|
801c68a: 4689 mov r9, r1
|
|
801c68c: f7e4 f9f4 bl 8000a78 <__aeabi_dcmpeq>
|
|
801c690: 2800 cmp r0, #0
|
|
801c692: d0c1 beq.n 801c618 <_strtod_l+0x8b8>
|
|
801c694: e615 b.n 801c2c2 <_strtod_l+0x562>
|
|
801c696: 9905 ldr r1, [sp, #20]
|
|
801c698: 4620 mov r0, r4
|
|
801c69a: f7ff facb bl 801bc34 <__ratio>
|
|
801c69e: ec57 6b10 vmov r6, r7, d0
|
|
801c6a2: 2200 movs r2, #0
|
|
801c6a4: f04f 4380 mov.w r3, #1073741824 @ 0x40000000
|
|
801c6a8: 4630 mov r0, r6
|
|
801c6aa: 4639 mov r1, r7
|
|
801c6ac: f7e4 f9f8 bl 8000aa0 <__aeabi_dcmple>
|
|
801c6b0: 2800 cmp r0, #0
|
|
801c6b2: d070 beq.n 801c796 <_strtod_l+0xa36>
|
|
801c6b4: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801c6b6: 2b00 cmp r3, #0
|
|
801c6b8: d17b bne.n 801c7b2 <_strtod_l+0xa52>
|
|
801c6ba: f1b8 0f00 cmp.w r8, #0
|
|
801c6be: d156 bne.n 801c76e <_strtod_l+0xa0e>
|
|
801c6c0: f3c9 0313 ubfx r3, r9, #0, #20
|
|
801c6c4: 2b00 cmp r3, #0
|
|
801c6c6: d158 bne.n 801c77a <_strtod_l+0xa1a>
|
|
801c6c8: 4b63 ldr r3, [pc, #396] @ (801c858 <_strtod_l+0xaf8>)
|
|
801c6ca: 2200 movs r2, #0
|
|
801c6cc: 4630 mov r0, r6
|
|
801c6ce: 4639 mov r1, r7
|
|
801c6d0: f7e4 f9dc bl 8000a8c <__aeabi_dcmplt>
|
|
801c6d4: 2800 cmp r0, #0
|
|
801c6d6: d159 bne.n 801c78c <_strtod_l+0xa2c>
|
|
801c6d8: 4b60 ldr r3, [pc, #384] @ (801c85c <_strtod_l+0xafc>)
|
|
801c6da: 2200 movs r2, #0
|
|
801c6dc: 4630 mov r0, r6
|
|
801c6de: 4639 mov r1, r7
|
|
801c6e0: f7e3 ff62 bl 80005a8 <__aeabi_dmul>
|
|
801c6e4: 4682 mov sl, r0
|
|
801c6e6: 468b mov fp, r1
|
|
801c6e8: f10b 4300 add.w r3, fp, #2147483648 @ 0x80000000
|
|
801c6ec: f8cd a020 str.w sl, [sp, #32]
|
|
801c6f0: 9309 str r3, [sp, #36] @ 0x24
|
|
801c6f2: 4b55 ldr r3, [pc, #340] @ (801c848 <_strtod_l+0xae8>)
|
|
801c6f4: 4a54 ldr r2, [pc, #336] @ (801c848 <_strtod_l+0xae8>)
|
|
801c6f6: 402b ands r3, r5
|
|
801c6f8: 9313 str r3, [sp, #76] @ 0x4c
|
|
801c6fa: 4b59 ldr r3, [pc, #356] @ (801c860 <_strtod_l+0xb00>)
|
|
801c6fc: 402a ands r2, r5
|
|
801c6fe: 429a cmp r2, r3
|
|
801c700: e9dd 6708 ldrd r6, r7, [sp, #32]
|
|
801c704: f040 80b0 bne.w 801c868 <_strtod_l+0xb08>
|
|
801c708: f1a5 7954 sub.w r9, r5, #55574528 @ 0x3500000
|
|
801c70c: ec49 8b10 vmov d0, r8, r9
|
|
801c710: f7ff f9c8 bl 801baa4 <__ulp>
|
|
801c714: e9dd 2308 ldrd r2, r3, [sp, #32]
|
|
801c718: ec51 0b10 vmov r0, r1, d0
|
|
801c71c: f7e3 ff44 bl 80005a8 <__aeabi_dmul>
|
|
801c720: 4642 mov r2, r8
|
|
801c722: 464b mov r3, r9
|
|
801c724: f7e3 fd8a bl 800023c <__adddf3>
|
|
801c728: 4d47 ldr r5, [pc, #284] @ (801c848 <_strtod_l+0xae8>)
|
|
801c72a: 4a4e ldr r2, [pc, #312] @ (801c864 <_strtod_l+0xb04>)
|
|
801c72c: 400d ands r5, r1
|
|
801c72e: 4295 cmp r5, r2
|
|
801c730: 4680 mov r8, r0
|
|
801c732: d945 bls.n 801c7c0 <_strtod_l+0xa60>
|
|
801c734: 9a0d ldr r2, [sp, #52] @ 0x34
|
|
801c736: 4b47 ldr r3, [pc, #284] @ (801c854 <_strtod_l+0xaf4>)
|
|
801c738: 429a cmp r2, r3
|
|
801c73a: d103 bne.n 801c744 <_strtod_l+0x9e4>
|
|
801c73c: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
801c73e: 3301 adds r3, #1
|
|
801c740: f43f ad85 beq.w 801c24e <_strtod_l+0x4ee>
|
|
801c744: f8df 910c ldr.w r9, [pc, #268] @ 801c854 <_strtod_l+0xaf4>
|
|
801c748: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff
|
|
801c74c: 9918 ldr r1, [sp, #96] @ 0x60
|
|
801c74e: 9804 ldr r0, [sp, #16]
|
|
801c750: f7fe fe6c bl 801b42c <_Bfree>
|
|
801c754: 9906 ldr r1, [sp, #24]
|
|
801c756: 9804 ldr r0, [sp, #16]
|
|
801c758: f7fe fe68 bl 801b42c <_Bfree>
|
|
801c75c: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
801c760: f7fe fe64 bl 801b42c <_Bfree>
|
|
801c764: 9804 ldr r0, [sp, #16]
|
|
801c766: 4621 mov r1, r4
|
|
801c768: f7fe fe60 bl 801b42c <_Bfree>
|
|
801c76c: e625 b.n 801c3ba <_strtod_l+0x65a>
|
|
801c76e: f1b8 0f01 cmp.w r8, #1
|
|
801c772: d102 bne.n 801c77a <_strtod_l+0xa1a>
|
|
801c774: 2d00 cmp r5, #0
|
|
801c776: f43f ada4 beq.w 801c2c2 <_strtod_l+0x562>
|
|
801c77a: ed9f 7b2b vldr d7, [pc, #172] @ 801c828 <_strtod_l+0xac8>
|
|
801c77e: f8df b0d8 ldr.w fp, [pc, #216] @ 801c858 <_strtod_l+0xaf8>
|
|
801c782: ed8d 7b08 vstr d7, [sp, #32]
|
|
801c786: f04f 0a00 mov.w sl, #0
|
|
801c78a: e7b2 b.n 801c6f2 <_strtod_l+0x992>
|
|
801c78c: f8df b0cc ldr.w fp, [pc, #204] @ 801c85c <_strtod_l+0xafc>
|
|
801c790: f04f 0a00 mov.w sl, #0
|
|
801c794: e7a8 b.n 801c6e8 <_strtod_l+0x988>
|
|
801c796: 4b31 ldr r3, [pc, #196] @ (801c85c <_strtod_l+0xafc>)
|
|
801c798: 2200 movs r2, #0
|
|
801c79a: 4630 mov r0, r6
|
|
801c79c: 4639 mov r1, r7
|
|
801c79e: f7e3 ff03 bl 80005a8 <__aeabi_dmul>
|
|
801c7a2: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801c7a4: 4682 mov sl, r0
|
|
801c7a6: 468b mov fp, r1
|
|
801c7a8: 2b00 cmp r3, #0
|
|
801c7aa: d09d beq.n 801c6e8 <_strtod_l+0x988>
|
|
801c7ac: e9cd ab08 strd sl, fp, [sp, #32]
|
|
801c7b0: e79f b.n 801c6f2 <_strtod_l+0x992>
|
|
801c7b2: ed9f 7b1f vldr d7, [pc, #124] @ 801c830 <_strtod_l+0xad0>
|
|
801c7b6: ed8d 7b08 vstr d7, [sp, #32]
|
|
801c7ba: ec5b ab17 vmov sl, fp, d7
|
|
801c7be: e798 b.n 801c6f2 <_strtod_l+0x992>
|
|
801c7c0: f101 7954 add.w r9, r1, #55574528 @ 0x3500000
|
|
801c7c4: 9b07 ldr r3, [sp, #28]
|
|
801c7c6: 2b00 cmp r3, #0
|
|
801c7c8: d1c0 bne.n 801c74c <_strtod_l+0x9ec>
|
|
801c7ca: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
|
|
801c7ce: 9a13 ldr r2, [sp, #76] @ 0x4c
|
|
801c7d0: 0d1b lsrs r3, r3, #20
|
|
801c7d2: 051b lsls r3, r3, #20
|
|
801c7d4: 429a cmp r2, r3
|
|
801c7d6: d1b9 bne.n 801c74c <_strtod_l+0x9ec>
|
|
801c7d8: 4650 mov r0, sl
|
|
801c7da: 4659 mov r1, fp
|
|
801c7dc: f7e4 fa2c bl 8000c38 <__aeabi_d2lz>
|
|
801c7e0: f7e3 feb4 bl 800054c <__aeabi_l2d>
|
|
801c7e4: 4602 mov r2, r0
|
|
801c7e6: 460b mov r3, r1
|
|
801c7e8: 4650 mov r0, sl
|
|
801c7ea: 4659 mov r1, fp
|
|
801c7ec: f7e3 fd24 bl 8000238 <__aeabi_dsub>
|
|
801c7f0: 9a0f ldr r2, [sp, #60] @ 0x3c
|
|
801c7f2: f3c9 0313 ubfx r3, r9, #0, #20
|
|
801c7f6: ea43 0308 orr.w r3, r3, r8
|
|
801c7fa: 4313 orrs r3, r2
|
|
801c7fc: 4606 mov r6, r0
|
|
801c7fe: 460f mov r7, r1
|
|
801c800: d06b beq.n 801c8da <_strtod_l+0xb7a>
|
|
801c802: a30d add r3, pc, #52 @ (adr r3, 801c838 <_strtod_l+0xad8>)
|
|
801c804: e9d3 2300 ldrd r2, r3, [r3]
|
|
801c808: f7e4 f940 bl 8000a8c <__aeabi_dcmplt>
|
|
801c80c: 2800 cmp r0, #0
|
|
801c80e: f47f ad29 bne.w 801c264 <_strtod_l+0x504>
|
|
801c812: a30b add r3, pc, #44 @ (adr r3, 801c840 <_strtod_l+0xae0>)
|
|
801c814: e9d3 2300 ldrd r2, r3, [r3]
|
|
801c818: 4630 mov r0, r6
|
|
801c81a: 4639 mov r1, r7
|
|
801c81c: f7e4 f954 bl 8000ac8 <__aeabi_dcmpgt>
|
|
801c820: 2800 cmp r0, #0
|
|
801c822: d093 beq.n 801c74c <_strtod_l+0x9ec>
|
|
801c824: e51e b.n 801c264 <_strtod_l+0x504>
|
|
801c826: bf00 nop
|
|
801c828: 00000000 .word 0x00000000
|
|
801c82c: bff00000 .word 0xbff00000
|
|
801c830: 00000000 .word 0x00000000
|
|
801c834: 3ff00000 .word 0x3ff00000
|
|
801c838: 94a03595 .word 0x94a03595
|
|
801c83c: 3fdfffff .word 0x3fdfffff
|
|
801c840: 35afe535 .word 0x35afe535
|
|
801c844: 3fe00000 .word 0x3fe00000
|
|
801c848: 7ff00000 .word 0x7ff00000
|
|
801c84c: 39500000 .word 0x39500000
|
|
801c850: 000fffff .word 0x000fffff
|
|
801c854: 7fefffff .word 0x7fefffff
|
|
801c858: 3ff00000 .word 0x3ff00000
|
|
801c85c: 3fe00000 .word 0x3fe00000
|
|
801c860: 7fe00000 .word 0x7fe00000
|
|
801c864: 7c9fffff .word 0x7c9fffff
|
|
801c868: 9b07 ldr r3, [sp, #28]
|
|
801c86a: b313 cbz r3, 801c8b2 <_strtod_l+0xb52>
|
|
801c86c: 9b13 ldr r3, [sp, #76] @ 0x4c
|
|
801c86e: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000
|
|
801c872: d81e bhi.n 801c8b2 <_strtod_l+0xb52>
|
|
801c874: a324 add r3, pc, #144 @ (adr r3, 801c908 <_strtod_l+0xba8>)
|
|
801c876: e9d3 2300 ldrd r2, r3, [r3]
|
|
801c87a: 4650 mov r0, sl
|
|
801c87c: 4659 mov r1, fp
|
|
801c87e: f7e4 f90f bl 8000aa0 <__aeabi_dcmple>
|
|
801c882: b190 cbz r0, 801c8aa <_strtod_l+0xb4a>
|
|
801c884: 4659 mov r1, fp
|
|
801c886: 4650 mov r0, sl
|
|
801c888: f7e4 f966 bl 8000b58 <__aeabi_d2uiz>
|
|
801c88c: 2801 cmp r0, #1
|
|
801c88e: bf38 it cc
|
|
801c890: 2001 movcc r0, #1
|
|
801c892: f7e3 fe0f bl 80004b4 <__aeabi_ui2d>
|
|
801c896: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801c898: 4682 mov sl, r0
|
|
801c89a: 468b mov fp, r1
|
|
801c89c: b9d3 cbnz r3, 801c8d4 <_strtod_l+0xb74>
|
|
801c89e: f101 4300 add.w r3, r1, #2147483648 @ 0x80000000
|
|
801c8a2: 9010 str r0, [sp, #64] @ 0x40
|
|
801c8a4: 9311 str r3, [sp, #68] @ 0x44
|
|
801c8a6: e9dd 6710 ldrd r6, r7, [sp, #64] @ 0x40
|
|
801c8aa: 9a13 ldr r2, [sp, #76] @ 0x4c
|
|
801c8ac: f107 63d6 add.w r3, r7, #112197632 @ 0x6b00000
|
|
801c8b0: 1a9f subs r7, r3, r2
|
|
801c8b2: ed9d 0b0c vldr d0, [sp, #48] @ 0x30
|
|
801c8b6: f7ff f8f5 bl 801baa4 <__ulp>
|
|
801c8ba: 4630 mov r0, r6
|
|
801c8bc: ec53 2b10 vmov r2, r3, d0
|
|
801c8c0: 4639 mov r1, r7
|
|
801c8c2: f7e3 fe71 bl 80005a8 <__aeabi_dmul>
|
|
801c8c6: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30
|
|
801c8ca: f7e3 fcb7 bl 800023c <__adddf3>
|
|
801c8ce: 4680 mov r8, r0
|
|
801c8d0: 4689 mov r9, r1
|
|
801c8d2: e777 b.n 801c7c4 <_strtod_l+0xa64>
|
|
801c8d4: e9cd ab10 strd sl, fp, [sp, #64] @ 0x40
|
|
801c8d8: e7e5 b.n 801c8a6 <_strtod_l+0xb46>
|
|
801c8da: a30d add r3, pc, #52 @ (adr r3, 801c910 <_strtod_l+0xbb0>)
|
|
801c8dc: e9d3 2300 ldrd r2, r3, [r3]
|
|
801c8e0: f7e4 f8d4 bl 8000a8c <__aeabi_dcmplt>
|
|
801c8e4: e79c b.n 801c820 <_strtod_l+0xac0>
|
|
801c8e6: 2300 movs r3, #0
|
|
801c8e8: 930b str r3, [sp, #44] @ 0x2c
|
|
801c8ea: 9a15 ldr r2, [sp, #84] @ 0x54
|
|
801c8ec: 9b17 ldr r3, [sp, #92] @ 0x5c
|
|
801c8ee: 6013 str r3, [r2, #0]
|
|
801c8f0: f7ff ba8c b.w 801be0c <_strtod_l+0xac>
|
|
801c8f4: 2a65 cmp r2, #101 @ 0x65
|
|
801c8f6: f43f ab6a beq.w 801bfce <_strtod_l+0x26e>
|
|
801c8fa: 2a45 cmp r2, #69 @ 0x45
|
|
801c8fc: f43f ab67 beq.w 801bfce <_strtod_l+0x26e>
|
|
801c900: 2301 movs r3, #1
|
|
801c902: 9307 str r3, [sp, #28]
|
|
801c904: f7ff bba1 b.w 801c04a <_strtod_l+0x2ea>
|
|
801c908: ffc00000 .word 0xffc00000
|
|
801c90c: 41dfffff .word 0x41dfffff
|
|
801c910: 94a03595 .word 0x94a03595
|
|
801c914: 3fcfffff .word 0x3fcfffff
|
|
|
|
0801c918 <_strtod_r>:
|
|
801c918: 4b01 ldr r3, [pc, #4] @ (801c920 <_strtod_r+0x8>)
|
|
801c91a: f7ff ba21 b.w 801bd60 <_strtod_l>
|
|
801c91e: bf00 nop
|
|
801c920: 2000016c .word 0x2000016c
|
|
|
|
0801c924 <_strtol_l.isra.0>:
|
|
801c924: 2b24 cmp r3, #36 @ 0x24
|
|
801c926: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
801c92a: 4686 mov lr, r0
|
|
801c92c: 4690 mov r8, r2
|
|
801c92e: d801 bhi.n 801c934 <_strtol_l.isra.0+0x10>
|
|
801c930: 2b01 cmp r3, #1
|
|
801c932: d106 bne.n 801c942 <_strtol_l.isra.0+0x1e>
|
|
801c934: f7fd fd96 bl 801a464 <__errno>
|
|
801c938: 2316 movs r3, #22
|
|
801c93a: 6003 str r3, [r0, #0]
|
|
801c93c: 2000 movs r0, #0
|
|
801c93e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
801c942: 4834 ldr r0, [pc, #208] @ (801ca14 <_strtol_l.isra.0+0xf0>)
|
|
801c944: 460d mov r5, r1
|
|
801c946: 462a mov r2, r5
|
|
801c948: f815 4b01 ldrb.w r4, [r5], #1
|
|
801c94c: 5d06 ldrb r6, [r0, r4]
|
|
801c94e: f016 0608 ands.w r6, r6, #8
|
|
801c952: d1f8 bne.n 801c946 <_strtol_l.isra.0+0x22>
|
|
801c954: 2c2d cmp r4, #45 @ 0x2d
|
|
801c956: d110 bne.n 801c97a <_strtol_l.isra.0+0x56>
|
|
801c958: 782c ldrb r4, [r5, #0]
|
|
801c95a: 2601 movs r6, #1
|
|
801c95c: 1c95 adds r5, r2, #2
|
|
801c95e: f033 0210 bics.w r2, r3, #16
|
|
801c962: d115 bne.n 801c990 <_strtol_l.isra.0+0x6c>
|
|
801c964: 2c30 cmp r4, #48 @ 0x30
|
|
801c966: d10d bne.n 801c984 <_strtol_l.isra.0+0x60>
|
|
801c968: 782a ldrb r2, [r5, #0]
|
|
801c96a: f002 02df and.w r2, r2, #223 @ 0xdf
|
|
801c96e: 2a58 cmp r2, #88 @ 0x58
|
|
801c970: d108 bne.n 801c984 <_strtol_l.isra.0+0x60>
|
|
801c972: 786c ldrb r4, [r5, #1]
|
|
801c974: 3502 adds r5, #2
|
|
801c976: 2310 movs r3, #16
|
|
801c978: e00a b.n 801c990 <_strtol_l.isra.0+0x6c>
|
|
801c97a: 2c2b cmp r4, #43 @ 0x2b
|
|
801c97c: bf04 itt eq
|
|
801c97e: 782c ldrbeq r4, [r5, #0]
|
|
801c980: 1c95 addeq r5, r2, #2
|
|
801c982: e7ec b.n 801c95e <_strtol_l.isra.0+0x3a>
|
|
801c984: 2b00 cmp r3, #0
|
|
801c986: d1f6 bne.n 801c976 <_strtol_l.isra.0+0x52>
|
|
801c988: 2c30 cmp r4, #48 @ 0x30
|
|
801c98a: bf14 ite ne
|
|
801c98c: 230a movne r3, #10
|
|
801c98e: 2308 moveq r3, #8
|
|
801c990: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000
|
|
801c994: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff
|
|
801c998: 2200 movs r2, #0
|
|
801c99a: fbbc f9f3 udiv r9, ip, r3
|
|
801c99e: 4610 mov r0, r2
|
|
801c9a0: fb03 ca19 mls sl, r3, r9, ip
|
|
801c9a4: f1a4 0730 sub.w r7, r4, #48 @ 0x30
|
|
801c9a8: 2f09 cmp r7, #9
|
|
801c9aa: d80f bhi.n 801c9cc <_strtol_l.isra.0+0xa8>
|
|
801c9ac: 463c mov r4, r7
|
|
801c9ae: 42a3 cmp r3, r4
|
|
801c9b0: dd1b ble.n 801c9ea <_strtol_l.isra.0+0xc6>
|
|
801c9b2: 1c57 adds r7, r2, #1
|
|
801c9b4: d007 beq.n 801c9c6 <_strtol_l.isra.0+0xa2>
|
|
801c9b6: 4581 cmp r9, r0
|
|
801c9b8: d314 bcc.n 801c9e4 <_strtol_l.isra.0+0xc0>
|
|
801c9ba: d101 bne.n 801c9c0 <_strtol_l.isra.0+0x9c>
|
|
801c9bc: 45a2 cmp sl, r4
|
|
801c9be: db11 blt.n 801c9e4 <_strtol_l.isra.0+0xc0>
|
|
801c9c0: fb00 4003 mla r0, r0, r3, r4
|
|
801c9c4: 2201 movs r2, #1
|
|
801c9c6: f815 4b01 ldrb.w r4, [r5], #1
|
|
801c9ca: e7eb b.n 801c9a4 <_strtol_l.isra.0+0x80>
|
|
801c9cc: f1a4 0741 sub.w r7, r4, #65 @ 0x41
|
|
801c9d0: 2f19 cmp r7, #25
|
|
801c9d2: d801 bhi.n 801c9d8 <_strtol_l.isra.0+0xb4>
|
|
801c9d4: 3c37 subs r4, #55 @ 0x37
|
|
801c9d6: e7ea b.n 801c9ae <_strtol_l.isra.0+0x8a>
|
|
801c9d8: f1a4 0761 sub.w r7, r4, #97 @ 0x61
|
|
801c9dc: 2f19 cmp r7, #25
|
|
801c9de: d804 bhi.n 801c9ea <_strtol_l.isra.0+0xc6>
|
|
801c9e0: 3c57 subs r4, #87 @ 0x57
|
|
801c9e2: e7e4 b.n 801c9ae <_strtol_l.isra.0+0x8a>
|
|
801c9e4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
801c9e8: e7ed b.n 801c9c6 <_strtol_l.isra.0+0xa2>
|
|
801c9ea: 1c53 adds r3, r2, #1
|
|
801c9ec: d108 bne.n 801ca00 <_strtol_l.isra.0+0xdc>
|
|
801c9ee: 2322 movs r3, #34 @ 0x22
|
|
801c9f0: f8ce 3000 str.w r3, [lr]
|
|
801c9f4: 4660 mov r0, ip
|
|
801c9f6: f1b8 0f00 cmp.w r8, #0
|
|
801c9fa: d0a0 beq.n 801c93e <_strtol_l.isra.0+0x1a>
|
|
801c9fc: 1e69 subs r1, r5, #1
|
|
801c9fe: e006 b.n 801ca0e <_strtol_l.isra.0+0xea>
|
|
801ca00: b106 cbz r6, 801ca04 <_strtol_l.isra.0+0xe0>
|
|
801ca02: 4240 negs r0, r0
|
|
801ca04: f1b8 0f00 cmp.w r8, #0
|
|
801ca08: d099 beq.n 801c93e <_strtol_l.isra.0+0x1a>
|
|
801ca0a: 2a00 cmp r2, #0
|
|
801ca0c: d1f6 bne.n 801c9fc <_strtol_l.isra.0+0xd8>
|
|
801ca0e: f8c8 1000 str.w r1, [r8]
|
|
801ca12: e794 b.n 801c93e <_strtol_l.isra.0+0x1a>
|
|
801ca14: 0801e939 .word 0x0801e939
|
|
|
|
0801ca18 <_strtol_r>:
|
|
801ca18: f7ff bf84 b.w 801c924 <_strtol_l.isra.0>
|
|
|
|
0801ca1c <__ssputs_r>:
|
|
801ca1c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
801ca20: 688e ldr r6, [r1, #8]
|
|
801ca22: 461f mov r7, r3
|
|
801ca24: 42be cmp r6, r7
|
|
801ca26: 4682 mov sl, r0
|
|
801ca28: 460c mov r4, r1
|
|
801ca2a: 4690 mov r8, r2
|
|
801ca2c: 4633 mov r3, r6
|
|
801ca2e: d853 bhi.n 801cad8 <__ssputs_r+0xbc>
|
|
801ca30: f9b1 000c ldrsh.w r0, [r1, #12]
|
|
801ca34: f410 6f90 tst.w r0, #1152 @ 0x480
|
|
801ca38: d02b beq.n 801ca92 <__ssputs_r+0x76>
|
|
801ca3a: 6965 ldr r5, [r4, #20]
|
|
801ca3c: 6823 ldr r3, [r4, #0]
|
|
801ca3e: 6909 ldr r1, [r1, #16]
|
|
801ca40: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
801ca44: eba3 0901 sub.w r9, r3, r1
|
|
801ca48: eb05 75d5 add.w r5, r5, r5, lsr #31
|
|
801ca4c: 1c7b adds r3, r7, #1
|
|
801ca4e: 106d asrs r5, r5, #1
|
|
801ca50: 444b add r3, r9
|
|
801ca52: 42ab cmp r3, r5
|
|
801ca54: 462a mov r2, r5
|
|
801ca56: bf84 itt hi
|
|
801ca58: 461d movhi r5, r3
|
|
801ca5a: 462a movhi r2, r5
|
|
801ca5c: 0543 lsls r3, r0, #21
|
|
801ca5e: d527 bpl.n 801cab0 <__ssputs_r+0x94>
|
|
801ca60: 4611 mov r1, r2
|
|
801ca62: 4650 mov r0, sl
|
|
801ca64: f7fe fc18 bl 801b298 <_malloc_r>
|
|
801ca68: 4606 mov r6, r0
|
|
801ca6a: b358 cbz r0, 801cac4 <__ssputs_r+0xa8>
|
|
801ca6c: 6921 ldr r1, [r4, #16]
|
|
801ca6e: 464a mov r2, r9
|
|
801ca70: f7fd fd25 bl 801a4be <memcpy>
|
|
801ca74: 89a3 ldrh r3, [r4, #12]
|
|
801ca76: f423 6390 bic.w r3, r3, #1152 @ 0x480
|
|
801ca7a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
801ca7e: 81a3 strh r3, [r4, #12]
|
|
801ca80: 6126 str r6, [r4, #16]
|
|
801ca82: 6165 str r5, [r4, #20]
|
|
801ca84: 444e add r6, r9
|
|
801ca86: eba5 0509 sub.w r5, r5, r9
|
|
801ca8a: 6026 str r6, [r4, #0]
|
|
801ca8c: 60a5 str r5, [r4, #8]
|
|
801ca8e: 463e mov r6, r7
|
|
801ca90: 463b mov r3, r7
|
|
801ca92: 461f mov r7, r3
|
|
801ca94: 6820 ldr r0, [r4, #0]
|
|
801ca96: 463a mov r2, r7
|
|
801ca98: 4641 mov r1, r8
|
|
801ca9a: f000 fb91 bl 801d1c0 <memmove>
|
|
801ca9e: 68a3 ldr r3, [r4, #8]
|
|
801caa0: 1b9b subs r3, r3, r6
|
|
801caa2: 60a3 str r3, [r4, #8]
|
|
801caa4: 6823 ldr r3, [r4, #0]
|
|
801caa6: 443b add r3, r7
|
|
801caa8: 6023 str r3, [r4, #0]
|
|
801caaa: 2000 movs r0, #0
|
|
801caac: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
801cab0: 4650 mov r0, sl
|
|
801cab2: f000 ff48 bl 801d946 <_realloc_r>
|
|
801cab6: 4606 mov r6, r0
|
|
801cab8: 2800 cmp r0, #0
|
|
801caba: d1e1 bne.n 801ca80 <__ssputs_r+0x64>
|
|
801cabc: 6921 ldr r1, [r4, #16]
|
|
801cabe: 4650 mov r0, sl
|
|
801cac0: f7fe fb76 bl 801b1b0 <_free_r>
|
|
801cac4: 230c movs r3, #12
|
|
801cac6: f8ca 3000 str.w r3, [sl]
|
|
801caca: 89a3 ldrh r3, [r4, #12]
|
|
801cacc: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
801cad0: 81a3 strh r3, [r4, #12]
|
|
801cad2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801cad6: e7e9 b.n 801caac <__ssputs_r+0x90>
|
|
801cad8: 463e mov r6, r7
|
|
801cada: e7db b.n 801ca94 <__ssputs_r+0x78>
|
|
|
|
0801cadc <_svfiprintf_r>:
|
|
801cadc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
801cae0: 461f mov r7, r3
|
|
801cae2: 898b ldrh r3, [r1, #12]
|
|
801cae4: 061b lsls r3, r3, #24
|
|
801cae6: b09c sub sp, #112 @ 0x70
|
|
801cae8: 4606 mov r6, r0
|
|
801caea: 460d mov r5, r1
|
|
801caec: 4614 mov r4, r2
|
|
801caee: d510 bpl.n 801cb12 <_svfiprintf_r+0x36>
|
|
801caf0: 690b ldr r3, [r1, #16]
|
|
801caf2: b973 cbnz r3, 801cb12 <_svfiprintf_r+0x36>
|
|
801caf4: 2140 movs r1, #64 @ 0x40
|
|
801caf6: f7fe fbcf bl 801b298 <_malloc_r>
|
|
801cafa: 6028 str r0, [r5, #0]
|
|
801cafc: 6128 str r0, [r5, #16]
|
|
801cafe: b930 cbnz r0, 801cb0e <_svfiprintf_r+0x32>
|
|
801cb00: 230c movs r3, #12
|
|
801cb02: 6033 str r3, [r6, #0]
|
|
801cb04: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801cb08: b01c add sp, #112 @ 0x70
|
|
801cb0a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
801cb0e: 2340 movs r3, #64 @ 0x40
|
|
801cb10: 616b str r3, [r5, #20]
|
|
801cb12: 2300 movs r3, #0
|
|
801cb14: 9309 str r3, [sp, #36] @ 0x24
|
|
801cb16: 2320 movs r3, #32
|
|
801cb18: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
801cb1c: 9703 str r7, [sp, #12]
|
|
801cb1e: 2330 movs r3, #48 @ 0x30
|
|
801cb20: 4f65 ldr r7, [pc, #404] @ (801ccb8 <_svfiprintf_r+0x1dc>)
|
|
801cb22: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
801cb26: f04f 0801 mov.w r8, #1
|
|
801cb2a: 4623 mov r3, r4
|
|
801cb2c: 4699 mov r9, r3
|
|
801cb2e: f813 2b01 ldrb.w r2, [r3], #1
|
|
801cb32: b10a cbz r2, 801cb38 <_svfiprintf_r+0x5c>
|
|
801cb34: 2a25 cmp r2, #37 @ 0x25
|
|
801cb36: d1f9 bne.n 801cb2c <_svfiprintf_r+0x50>
|
|
801cb38: ebb9 0a04 subs.w sl, r9, r4
|
|
801cb3c: d00b beq.n 801cb56 <_svfiprintf_r+0x7a>
|
|
801cb3e: 4653 mov r3, sl
|
|
801cb40: 4622 mov r2, r4
|
|
801cb42: 4629 mov r1, r5
|
|
801cb44: 4630 mov r0, r6
|
|
801cb46: f7ff ff69 bl 801ca1c <__ssputs_r>
|
|
801cb4a: 3001 adds r0, #1
|
|
801cb4c: f000 80a4 beq.w 801cc98 <_svfiprintf_r+0x1bc>
|
|
801cb50: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
801cb52: 4452 add r2, sl
|
|
801cb54: 9209 str r2, [sp, #36] @ 0x24
|
|
801cb56: f899 3000 ldrb.w r3, [r9]
|
|
801cb5a: 2b00 cmp r3, #0
|
|
801cb5c: f000 809c beq.w 801cc98 <_svfiprintf_r+0x1bc>
|
|
801cb60: 2300 movs r3, #0
|
|
801cb62: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
801cb66: e9cd 2305 strd r2, r3, [sp, #20]
|
|
801cb6a: f109 0901 add.w r9, r9, #1
|
|
801cb6e: 9304 str r3, [sp, #16]
|
|
801cb70: 9307 str r3, [sp, #28]
|
|
801cb72: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
801cb76: 931a str r3, [sp, #104] @ 0x68
|
|
801cb78: 464c mov r4, r9
|
|
801cb7a: 484f ldr r0, [pc, #316] @ (801ccb8 <_svfiprintf_r+0x1dc>)
|
|
801cb7c: f814 1b01 ldrb.w r1, [r4], #1
|
|
801cb80: 2205 movs r2, #5
|
|
801cb82: f7e3 fafd bl 8000180 <memchr>
|
|
801cb86: 9b04 ldr r3, [sp, #16]
|
|
801cb88: b9d0 cbnz r0, 801cbc0 <_svfiprintf_r+0xe4>
|
|
801cb8a: 06d8 lsls r0, r3, #27
|
|
801cb8c: bf44 itt mi
|
|
801cb8e: 2220 movmi r2, #32
|
|
801cb90: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53
|
|
801cb94: 0719 lsls r1, r3, #28
|
|
801cb96: bf44 itt mi
|
|
801cb98: 222b movmi r2, #43 @ 0x2b
|
|
801cb9a: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53
|
|
801cb9e: f899 2000 ldrb.w r2, [r9]
|
|
801cba2: 2a2a cmp r2, #42 @ 0x2a
|
|
801cba4: d013 beq.n 801cbce <_svfiprintf_r+0xf2>
|
|
801cba6: 9a07 ldr r2, [sp, #28]
|
|
801cba8: 464c mov r4, r9
|
|
801cbaa: 2000 movs r0, #0
|
|
801cbac: f04f 0c0a mov.w ip, #10
|
|
801cbb0: 4621 mov r1, r4
|
|
801cbb2: f811 3b01 ldrb.w r3, [r1], #1
|
|
801cbb6: 3b30 subs r3, #48 @ 0x30
|
|
801cbb8: 2b09 cmp r3, #9
|
|
801cbba: d949 bls.n 801cc50 <_svfiprintf_r+0x174>
|
|
801cbbc: b968 cbnz r0, 801cbda <_svfiprintf_r+0xfe>
|
|
801cbbe: e013 b.n 801cbe8 <_svfiprintf_r+0x10c>
|
|
801cbc0: 1bc0 subs r0, r0, r7
|
|
801cbc2: fa08 f000 lsl.w r0, r8, r0
|
|
801cbc6: 4318 orrs r0, r3
|
|
801cbc8: 9004 str r0, [sp, #16]
|
|
801cbca: 46a1 mov r9, r4
|
|
801cbcc: e7d4 b.n 801cb78 <_svfiprintf_r+0x9c>
|
|
801cbce: 9a03 ldr r2, [sp, #12]
|
|
801cbd0: 1d11 adds r1, r2, #4
|
|
801cbd2: 6812 ldr r2, [r2, #0]
|
|
801cbd4: 9103 str r1, [sp, #12]
|
|
801cbd6: 2a00 cmp r2, #0
|
|
801cbd8: db01 blt.n 801cbde <_svfiprintf_r+0x102>
|
|
801cbda: 9207 str r2, [sp, #28]
|
|
801cbdc: e004 b.n 801cbe8 <_svfiprintf_r+0x10c>
|
|
801cbde: 4252 negs r2, r2
|
|
801cbe0: f043 0302 orr.w r3, r3, #2
|
|
801cbe4: 9207 str r2, [sp, #28]
|
|
801cbe6: 9304 str r3, [sp, #16]
|
|
801cbe8: 7823 ldrb r3, [r4, #0]
|
|
801cbea: 2b2e cmp r3, #46 @ 0x2e
|
|
801cbec: d10a bne.n 801cc04 <_svfiprintf_r+0x128>
|
|
801cbee: 7863 ldrb r3, [r4, #1]
|
|
801cbf0: 2b2a cmp r3, #42 @ 0x2a
|
|
801cbf2: d132 bne.n 801cc5a <_svfiprintf_r+0x17e>
|
|
801cbf4: 9b03 ldr r3, [sp, #12]
|
|
801cbf6: 1d1a adds r2, r3, #4
|
|
801cbf8: 681b ldr r3, [r3, #0]
|
|
801cbfa: 9203 str r2, [sp, #12]
|
|
801cbfc: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
801cc00: 3402 adds r4, #2
|
|
801cc02: 9305 str r3, [sp, #20]
|
|
801cc04: f8df 90c0 ldr.w r9, [pc, #192] @ 801ccc8 <_svfiprintf_r+0x1ec>
|
|
801cc08: 7821 ldrb r1, [r4, #0]
|
|
801cc0a: 2203 movs r2, #3
|
|
801cc0c: 4648 mov r0, r9
|
|
801cc0e: f7e3 fab7 bl 8000180 <memchr>
|
|
801cc12: b138 cbz r0, 801cc24 <_svfiprintf_r+0x148>
|
|
801cc14: 9b04 ldr r3, [sp, #16]
|
|
801cc16: eba0 0009 sub.w r0, r0, r9
|
|
801cc1a: 2240 movs r2, #64 @ 0x40
|
|
801cc1c: 4082 lsls r2, r0
|
|
801cc1e: 4313 orrs r3, r2
|
|
801cc20: 3401 adds r4, #1
|
|
801cc22: 9304 str r3, [sp, #16]
|
|
801cc24: f814 1b01 ldrb.w r1, [r4], #1
|
|
801cc28: 4824 ldr r0, [pc, #144] @ (801ccbc <_svfiprintf_r+0x1e0>)
|
|
801cc2a: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
801cc2e: 2206 movs r2, #6
|
|
801cc30: f7e3 faa6 bl 8000180 <memchr>
|
|
801cc34: 2800 cmp r0, #0
|
|
801cc36: d035 beq.n 801cca4 <_svfiprintf_r+0x1c8>
|
|
801cc38: 4821 ldr r0, [pc, #132] @ (801ccc0 <_svfiprintf_r+0x1e4>)
|
|
801cc3a: bb18 cbnz r0, 801cc84 <_svfiprintf_r+0x1a8>
|
|
801cc3c: 9b03 ldr r3, [sp, #12]
|
|
801cc3e: 3307 adds r3, #7
|
|
801cc40: f023 0307 bic.w r3, r3, #7
|
|
801cc44: 3308 adds r3, #8
|
|
801cc46: 9303 str r3, [sp, #12]
|
|
801cc48: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
801cc4a: 4403 add r3, r0
|
|
801cc4c: 9309 str r3, [sp, #36] @ 0x24
|
|
801cc4e: e76c b.n 801cb2a <_svfiprintf_r+0x4e>
|
|
801cc50: fb0c 3202 mla r2, ip, r2, r3
|
|
801cc54: 460c mov r4, r1
|
|
801cc56: 2001 movs r0, #1
|
|
801cc58: e7aa b.n 801cbb0 <_svfiprintf_r+0xd4>
|
|
801cc5a: 2300 movs r3, #0
|
|
801cc5c: 3401 adds r4, #1
|
|
801cc5e: 9305 str r3, [sp, #20]
|
|
801cc60: 4619 mov r1, r3
|
|
801cc62: f04f 0c0a mov.w ip, #10
|
|
801cc66: 4620 mov r0, r4
|
|
801cc68: f810 2b01 ldrb.w r2, [r0], #1
|
|
801cc6c: 3a30 subs r2, #48 @ 0x30
|
|
801cc6e: 2a09 cmp r2, #9
|
|
801cc70: d903 bls.n 801cc7a <_svfiprintf_r+0x19e>
|
|
801cc72: 2b00 cmp r3, #0
|
|
801cc74: d0c6 beq.n 801cc04 <_svfiprintf_r+0x128>
|
|
801cc76: 9105 str r1, [sp, #20]
|
|
801cc78: e7c4 b.n 801cc04 <_svfiprintf_r+0x128>
|
|
801cc7a: fb0c 2101 mla r1, ip, r1, r2
|
|
801cc7e: 4604 mov r4, r0
|
|
801cc80: 2301 movs r3, #1
|
|
801cc82: e7f0 b.n 801cc66 <_svfiprintf_r+0x18a>
|
|
801cc84: ab03 add r3, sp, #12
|
|
801cc86: 9300 str r3, [sp, #0]
|
|
801cc88: 462a mov r2, r5
|
|
801cc8a: 4b0e ldr r3, [pc, #56] @ (801ccc4 <_svfiprintf_r+0x1e8>)
|
|
801cc8c: a904 add r1, sp, #16
|
|
801cc8e: 4630 mov r0, r6
|
|
801cc90: f7fc fc34 bl 80194fc <_printf_float>
|
|
801cc94: 1c42 adds r2, r0, #1
|
|
801cc96: d1d7 bne.n 801cc48 <_svfiprintf_r+0x16c>
|
|
801cc98: 89ab ldrh r3, [r5, #12]
|
|
801cc9a: 065b lsls r3, r3, #25
|
|
801cc9c: f53f af32 bmi.w 801cb04 <_svfiprintf_r+0x28>
|
|
801cca0: 9809 ldr r0, [sp, #36] @ 0x24
|
|
801cca2: e731 b.n 801cb08 <_svfiprintf_r+0x2c>
|
|
801cca4: ab03 add r3, sp, #12
|
|
801cca6: 9300 str r3, [sp, #0]
|
|
801cca8: 462a mov r2, r5
|
|
801ccaa: 4b06 ldr r3, [pc, #24] @ (801ccc4 <_svfiprintf_r+0x1e8>)
|
|
801ccac: a904 add r1, sp, #16
|
|
801ccae: 4630 mov r0, r6
|
|
801ccb0: f7fc feba bl 8019a28 <_printf_i>
|
|
801ccb4: e7ee b.n 801cc94 <_svfiprintf_r+0x1b8>
|
|
801ccb6: bf00 nop
|
|
801ccb8: 0801e731 .word 0x0801e731
|
|
801ccbc: 0801e73b .word 0x0801e73b
|
|
801ccc0: 080194fd .word 0x080194fd
|
|
801ccc4: 0801ca1d .word 0x0801ca1d
|
|
801ccc8: 0801e737 .word 0x0801e737
|
|
|
|
0801cccc <__sfputc_r>:
|
|
801cccc: 6893 ldr r3, [r2, #8]
|
|
801ccce: 3b01 subs r3, #1
|
|
801ccd0: 2b00 cmp r3, #0
|
|
801ccd2: b410 push {r4}
|
|
801ccd4: 6093 str r3, [r2, #8]
|
|
801ccd6: da08 bge.n 801ccea <__sfputc_r+0x1e>
|
|
801ccd8: 6994 ldr r4, [r2, #24]
|
|
801ccda: 42a3 cmp r3, r4
|
|
801ccdc: db01 blt.n 801cce2 <__sfputc_r+0x16>
|
|
801ccde: 290a cmp r1, #10
|
|
801cce0: d103 bne.n 801ccea <__sfputc_r+0x1e>
|
|
801cce2: f85d 4b04 ldr.w r4, [sp], #4
|
|
801cce6: f000 b9d9 b.w 801d09c <__swbuf_r>
|
|
801ccea: 6813 ldr r3, [r2, #0]
|
|
801ccec: 1c58 adds r0, r3, #1
|
|
801ccee: 6010 str r0, [r2, #0]
|
|
801ccf0: 7019 strb r1, [r3, #0]
|
|
801ccf2: 4608 mov r0, r1
|
|
801ccf4: f85d 4b04 ldr.w r4, [sp], #4
|
|
801ccf8: 4770 bx lr
|
|
|
|
0801ccfa <__sfputs_r>:
|
|
801ccfa: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801ccfc: 4606 mov r6, r0
|
|
801ccfe: 460f mov r7, r1
|
|
801cd00: 4614 mov r4, r2
|
|
801cd02: 18d5 adds r5, r2, r3
|
|
801cd04: 42ac cmp r4, r5
|
|
801cd06: d101 bne.n 801cd0c <__sfputs_r+0x12>
|
|
801cd08: 2000 movs r0, #0
|
|
801cd0a: e007 b.n 801cd1c <__sfputs_r+0x22>
|
|
801cd0c: f814 1b01 ldrb.w r1, [r4], #1
|
|
801cd10: 463a mov r2, r7
|
|
801cd12: 4630 mov r0, r6
|
|
801cd14: f7ff ffda bl 801cccc <__sfputc_r>
|
|
801cd18: 1c43 adds r3, r0, #1
|
|
801cd1a: d1f3 bne.n 801cd04 <__sfputs_r+0xa>
|
|
801cd1c: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
...
|
|
|
|
0801cd20 <_vfiprintf_r>:
|
|
801cd20: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
801cd24: 460d mov r5, r1
|
|
801cd26: b09c sub sp, #112 @ 0x70
|
|
801cd28: 4614 mov r4, r2
|
|
801cd2a: 461f mov r7, r3
|
|
801cd2c: 4606 mov r6, r0
|
|
801cd2e: b118 cbz r0, 801cd38 <_vfiprintf_r+0x18>
|
|
801cd30: 6a03 ldr r3, [r0, #32]
|
|
801cd32: b90b cbnz r3, 801cd38 <_vfiprintf_r+0x18>
|
|
801cd34: f7fd fa38 bl 801a1a8 <__sinit>
|
|
801cd38: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
801cd3a: 07d9 lsls r1, r3, #31
|
|
801cd3c: d405 bmi.n 801cd4a <_vfiprintf_r+0x2a>
|
|
801cd3e: 89ab ldrh r3, [r5, #12]
|
|
801cd40: 059a lsls r2, r3, #22
|
|
801cd42: d402 bmi.n 801cd4a <_vfiprintf_r+0x2a>
|
|
801cd44: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
801cd46: f7fd fbb8 bl 801a4ba <__retarget_lock_acquire_recursive>
|
|
801cd4a: 89ab ldrh r3, [r5, #12]
|
|
801cd4c: 071b lsls r3, r3, #28
|
|
801cd4e: d501 bpl.n 801cd54 <_vfiprintf_r+0x34>
|
|
801cd50: 692b ldr r3, [r5, #16]
|
|
801cd52: b99b cbnz r3, 801cd7c <_vfiprintf_r+0x5c>
|
|
801cd54: 4629 mov r1, r5
|
|
801cd56: 4630 mov r0, r6
|
|
801cd58: f000 f9de bl 801d118 <__swsetup_r>
|
|
801cd5c: b170 cbz r0, 801cd7c <_vfiprintf_r+0x5c>
|
|
801cd5e: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
801cd60: 07dc lsls r4, r3, #31
|
|
801cd62: d504 bpl.n 801cd6e <_vfiprintf_r+0x4e>
|
|
801cd64: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801cd68: b01c add sp, #112 @ 0x70
|
|
801cd6a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
801cd6e: 89ab ldrh r3, [r5, #12]
|
|
801cd70: 0598 lsls r0, r3, #22
|
|
801cd72: d4f7 bmi.n 801cd64 <_vfiprintf_r+0x44>
|
|
801cd74: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
801cd76: f7fd fba1 bl 801a4bc <__retarget_lock_release_recursive>
|
|
801cd7a: e7f3 b.n 801cd64 <_vfiprintf_r+0x44>
|
|
801cd7c: 2300 movs r3, #0
|
|
801cd7e: 9309 str r3, [sp, #36] @ 0x24
|
|
801cd80: 2320 movs r3, #32
|
|
801cd82: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
801cd86: 9703 str r7, [sp, #12]
|
|
801cd88: 2330 movs r3, #48 @ 0x30
|
|
801cd8a: 4f6a ldr r7, [pc, #424] @ (801cf34 <_vfiprintf_r+0x214>)
|
|
801cd8c: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
801cd90: f04f 0801 mov.w r8, #1
|
|
801cd94: 4623 mov r3, r4
|
|
801cd96: 4699 mov r9, r3
|
|
801cd98: f813 2b01 ldrb.w r2, [r3], #1
|
|
801cd9c: b10a cbz r2, 801cda2 <_vfiprintf_r+0x82>
|
|
801cd9e: 2a25 cmp r2, #37 @ 0x25
|
|
801cda0: d1f9 bne.n 801cd96 <_vfiprintf_r+0x76>
|
|
801cda2: ebb9 0a04 subs.w sl, r9, r4
|
|
801cda6: d00b beq.n 801cdc0 <_vfiprintf_r+0xa0>
|
|
801cda8: 4653 mov r3, sl
|
|
801cdaa: 4622 mov r2, r4
|
|
801cdac: 4629 mov r1, r5
|
|
801cdae: 4630 mov r0, r6
|
|
801cdb0: f7ff ffa3 bl 801ccfa <__sfputs_r>
|
|
801cdb4: 3001 adds r0, #1
|
|
801cdb6: f000 80a4 beq.w 801cf02 <_vfiprintf_r+0x1e2>
|
|
801cdba: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
801cdbc: 4452 add r2, sl
|
|
801cdbe: 9209 str r2, [sp, #36] @ 0x24
|
|
801cdc0: f899 3000 ldrb.w r3, [r9]
|
|
801cdc4: 2b00 cmp r3, #0
|
|
801cdc6: f000 809c beq.w 801cf02 <_vfiprintf_r+0x1e2>
|
|
801cdca: 2300 movs r3, #0
|
|
801cdcc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
801cdd0: e9cd 2305 strd r2, r3, [sp, #20]
|
|
801cdd4: f109 0901 add.w r9, r9, #1
|
|
801cdd8: 9304 str r3, [sp, #16]
|
|
801cdda: 9307 str r3, [sp, #28]
|
|
801cddc: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
801cde0: 931a str r3, [sp, #104] @ 0x68
|
|
801cde2: 464c mov r4, r9
|
|
801cde4: 4853 ldr r0, [pc, #332] @ (801cf34 <_vfiprintf_r+0x214>)
|
|
801cde6: f814 1b01 ldrb.w r1, [r4], #1
|
|
801cdea: 2205 movs r2, #5
|
|
801cdec: f7e3 f9c8 bl 8000180 <memchr>
|
|
801cdf0: 9b04 ldr r3, [sp, #16]
|
|
801cdf2: b9d0 cbnz r0, 801ce2a <_vfiprintf_r+0x10a>
|
|
801cdf4: 06d9 lsls r1, r3, #27
|
|
801cdf6: bf44 itt mi
|
|
801cdf8: 2220 movmi r2, #32
|
|
801cdfa: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53
|
|
801cdfe: 071a lsls r2, r3, #28
|
|
801ce00: bf44 itt mi
|
|
801ce02: 222b movmi r2, #43 @ 0x2b
|
|
801ce04: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53
|
|
801ce08: f899 2000 ldrb.w r2, [r9]
|
|
801ce0c: 2a2a cmp r2, #42 @ 0x2a
|
|
801ce0e: d013 beq.n 801ce38 <_vfiprintf_r+0x118>
|
|
801ce10: 9a07 ldr r2, [sp, #28]
|
|
801ce12: 464c mov r4, r9
|
|
801ce14: 2000 movs r0, #0
|
|
801ce16: f04f 0c0a mov.w ip, #10
|
|
801ce1a: 4621 mov r1, r4
|
|
801ce1c: f811 3b01 ldrb.w r3, [r1], #1
|
|
801ce20: 3b30 subs r3, #48 @ 0x30
|
|
801ce22: 2b09 cmp r3, #9
|
|
801ce24: d949 bls.n 801ceba <_vfiprintf_r+0x19a>
|
|
801ce26: b968 cbnz r0, 801ce44 <_vfiprintf_r+0x124>
|
|
801ce28: e013 b.n 801ce52 <_vfiprintf_r+0x132>
|
|
801ce2a: 1bc0 subs r0, r0, r7
|
|
801ce2c: fa08 f000 lsl.w r0, r8, r0
|
|
801ce30: 4318 orrs r0, r3
|
|
801ce32: 9004 str r0, [sp, #16]
|
|
801ce34: 46a1 mov r9, r4
|
|
801ce36: e7d4 b.n 801cde2 <_vfiprintf_r+0xc2>
|
|
801ce38: 9a03 ldr r2, [sp, #12]
|
|
801ce3a: 1d11 adds r1, r2, #4
|
|
801ce3c: 6812 ldr r2, [r2, #0]
|
|
801ce3e: 9103 str r1, [sp, #12]
|
|
801ce40: 2a00 cmp r2, #0
|
|
801ce42: db01 blt.n 801ce48 <_vfiprintf_r+0x128>
|
|
801ce44: 9207 str r2, [sp, #28]
|
|
801ce46: e004 b.n 801ce52 <_vfiprintf_r+0x132>
|
|
801ce48: 4252 negs r2, r2
|
|
801ce4a: f043 0302 orr.w r3, r3, #2
|
|
801ce4e: 9207 str r2, [sp, #28]
|
|
801ce50: 9304 str r3, [sp, #16]
|
|
801ce52: 7823 ldrb r3, [r4, #0]
|
|
801ce54: 2b2e cmp r3, #46 @ 0x2e
|
|
801ce56: d10a bne.n 801ce6e <_vfiprintf_r+0x14e>
|
|
801ce58: 7863 ldrb r3, [r4, #1]
|
|
801ce5a: 2b2a cmp r3, #42 @ 0x2a
|
|
801ce5c: d132 bne.n 801cec4 <_vfiprintf_r+0x1a4>
|
|
801ce5e: 9b03 ldr r3, [sp, #12]
|
|
801ce60: 1d1a adds r2, r3, #4
|
|
801ce62: 681b ldr r3, [r3, #0]
|
|
801ce64: 9203 str r2, [sp, #12]
|
|
801ce66: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
801ce6a: 3402 adds r4, #2
|
|
801ce6c: 9305 str r3, [sp, #20]
|
|
801ce6e: f8df 90d4 ldr.w r9, [pc, #212] @ 801cf44 <_vfiprintf_r+0x224>
|
|
801ce72: 7821 ldrb r1, [r4, #0]
|
|
801ce74: 2203 movs r2, #3
|
|
801ce76: 4648 mov r0, r9
|
|
801ce78: f7e3 f982 bl 8000180 <memchr>
|
|
801ce7c: b138 cbz r0, 801ce8e <_vfiprintf_r+0x16e>
|
|
801ce7e: 9b04 ldr r3, [sp, #16]
|
|
801ce80: eba0 0009 sub.w r0, r0, r9
|
|
801ce84: 2240 movs r2, #64 @ 0x40
|
|
801ce86: 4082 lsls r2, r0
|
|
801ce88: 4313 orrs r3, r2
|
|
801ce8a: 3401 adds r4, #1
|
|
801ce8c: 9304 str r3, [sp, #16]
|
|
801ce8e: f814 1b01 ldrb.w r1, [r4], #1
|
|
801ce92: 4829 ldr r0, [pc, #164] @ (801cf38 <_vfiprintf_r+0x218>)
|
|
801ce94: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
801ce98: 2206 movs r2, #6
|
|
801ce9a: f7e3 f971 bl 8000180 <memchr>
|
|
801ce9e: 2800 cmp r0, #0
|
|
801cea0: d03e beq.n 801cf20 <_vfiprintf_r+0x200>
|
|
801cea2: 4826 ldr r0, [pc, #152] @ (801cf3c <_vfiprintf_r+0x21c>)
|
|
801cea4: bb18 cbnz r0, 801ceee <_vfiprintf_r+0x1ce>
|
|
801cea6: 9b03 ldr r3, [sp, #12]
|
|
801cea8: 3307 adds r3, #7
|
|
801ceaa: f023 0307 bic.w r3, r3, #7
|
|
801ceae: 3308 adds r3, #8
|
|
801ceb0: 9303 str r3, [sp, #12]
|
|
801ceb2: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
801ceb4: 4403 add r3, r0
|
|
801ceb6: 9309 str r3, [sp, #36] @ 0x24
|
|
801ceb8: e76c b.n 801cd94 <_vfiprintf_r+0x74>
|
|
801ceba: fb0c 3202 mla r2, ip, r2, r3
|
|
801cebe: 460c mov r4, r1
|
|
801cec0: 2001 movs r0, #1
|
|
801cec2: e7aa b.n 801ce1a <_vfiprintf_r+0xfa>
|
|
801cec4: 2300 movs r3, #0
|
|
801cec6: 3401 adds r4, #1
|
|
801cec8: 9305 str r3, [sp, #20]
|
|
801ceca: 4619 mov r1, r3
|
|
801cecc: f04f 0c0a mov.w ip, #10
|
|
801ced0: 4620 mov r0, r4
|
|
801ced2: f810 2b01 ldrb.w r2, [r0], #1
|
|
801ced6: 3a30 subs r2, #48 @ 0x30
|
|
801ced8: 2a09 cmp r2, #9
|
|
801ceda: d903 bls.n 801cee4 <_vfiprintf_r+0x1c4>
|
|
801cedc: 2b00 cmp r3, #0
|
|
801cede: d0c6 beq.n 801ce6e <_vfiprintf_r+0x14e>
|
|
801cee0: 9105 str r1, [sp, #20]
|
|
801cee2: e7c4 b.n 801ce6e <_vfiprintf_r+0x14e>
|
|
801cee4: fb0c 2101 mla r1, ip, r1, r2
|
|
801cee8: 4604 mov r4, r0
|
|
801ceea: 2301 movs r3, #1
|
|
801ceec: e7f0 b.n 801ced0 <_vfiprintf_r+0x1b0>
|
|
801ceee: ab03 add r3, sp, #12
|
|
801cef0: 9300 str r3, [sp, #0]
|
|
801cef2: 462a mov r2, r5
|
|
801cef4: 4b12 ldr r3, [pc, #72] @ (801cf40 <_vfiprintf_r+0x220>)
|
|
801cef6: a904 add r1, sp, #16
|
|
801cef8: 4630 mov r0, r6
|
|
801cefa: f7fc faff bl 80194fc <_printf_float>
|
|
801cefe: 1c43 adds r3, r0, #1
|
|
801cf00: d1d7 bne.n 801ceb2 <_vfiprintf_r+0x192>
|
|
801cf02: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
801cf04: 07d9 lsls r1, r3, #31
|
|
801cf06: d405 bmi.n 801cf14 <_vfiprintf_r+0x1f4>
|
|
801cf08: 89ab ldrh r3, [r5, #12]
|
|
801cf0a: 059a lsls r2, r3, #22
|
|
801cf0c: d402 bmi.n 801cf14 <_vfiprintf_r+0x1f4>
|
|
801cf0e: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
801cf10: f7fd fad4 bl 801a4bc <__retarget_lock_release_recursive>
|
|
801cf14: 89ab ldrh r3, [r5, #12]
|
|
801cf16: 065b lsls r3, r3, #25
|
|
801cf18: f53f af24 bmi.w 801cd64 <_vfiprintf_r+0x44>
|
|
801cf1c: 9809 ldr r0, [sp, #36] @ 0x24
|
|
801cf1e: e723 b.n 801cd68 <_vfiprintf_r+0x48>
|
|
801cf20: ab03 add r3, sp, #12
|
|
801cf22: 9300 str r3, [sp, #0]
|
|
801cf24: 462a mov r2, r5
|
|
801cf26: 4b06 ldr r3, [pc, #24] @ (801cf40 <_vfiprintf_r+0x220>)
|
|
801cf28: a904 add r1, sp, #16
|
|
801cf2a: 4630 mov r0, r6
|
|
801cf2c: f7fc fd7c bl 8019a28 <_printf_i>
|
|
801cf30: e7e5 b.n 801cefe <_vfiprintf_r+0x1de>
|
|
801cf32: bf00 nop
|
|
801cf34: 0801e731 .word 0x0801e731
|
|
801cf38: 0801e73b .word 0x0801e73b
|
|
801cf3c: 080194fd .word 0x080194fd
|
|
801cf40: 0801ccfb .word 0x0801ccfb
|
|
801cf44: 0801e737 .word 0x0801e737
|
|
|
|
0801cf48 <__sflush_r>:
|
|
801cf48: f9b1 200c ldrsh.w r2, [r1, #12]
|
|
801cf4c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
801cf50: 0716 lsls r6, r2, #28
|
|
801cf52: 4605 mov r5, r0
|
|
801cf54: 460c mov r4, r1
|
|
801cf56: d451 bmi.n 801cffc <__sflush_r+0xb4>
|
|
801cf58: 684b ldr r3, [r1, #4]
|
|
801cf5a: 2b00 cmp r3, #0
|
|
801cf5c: dc02 bgt.n 801cf64 <__sflush_r+0x1c>
|
|
801cf5e: 6c0b ldr r3, [r1, #64] @ 0x40
|
|
801cf60: 2b00 cmp r3, #0
|
|
801cf62: dd49 ble.n 801cff8 <__sflush_r+0xb0>
|
|
801cf64: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
801cf66: 2e00 cmp r6, #0
|
|
801cf68: d046 beq.n 801cff8 <__sflush_r+0xb0>
|
|
801cf6a: 2300 movs r3, #0
|
|
801cf6c: f412 5280 ands.w r2, r2, #4096 @ 0x1000
|
|
801cf70: 682f ldr r7, [r5, #0]
|
|
801cf72: 602b str r3, [r5, #0]
|
|
801cf74: d031 beq.n 801cfda <__sflush_r+0x92>
|
|
801cf76: 6d62 ldr r2, [r4, #84] @ 0x54
|
|
801cf78: 89a3 ldrh r3, [r4, #12]
|
|
801cf7a: 0759 lsls r1, r3, #29
|
|
801cf7c: d505 bpl.n 801cf8a <__sflush_r+0x42>
|
|
801cf7e: 6863 ldr r3, [r4, #4]
|
|
801cf80: 1ad2 subs r2, r2, r3
|
|
801cf82: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
801cf84: b10b cbz r3, 801cf8a <__sflush_r+0x42>
|
|
801cf86: 6c23 ldr r3, [r4, #64] @ 0x40
|
|
801cf88: 1ad2 subs r2, r2, r3
|
|
801cf8a: 2300 movs r3, #0
|
|
801cf8c: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
801cf8e: 6a21 ldr r1, [r4, #32]
|
|
801cf90: 4628 mov r0, r5
|
|
801cf92: 47b0 blx r6
|
|
801cf94: 1c42 adds r2, r0, #1
|
|
801cf96: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801cf9a: d106 bne.n 801cfaa <__sflush_r+0x62>
|
|
801cf9c: 6829 ldr r1, [r5, #0]
|
|
801cf9e: 291d cmp r1, #29
|
|
801cfa0: d846 bhi.n 801d030 <__sflush_r+0xe8>
|
|
801cfa2: 4a29 ldr r2, [pc, #164] @ (801d048 <__sflush_r+0x100>)
|
|
801cfa4: 40ca lsrs r2, r1
|
|
801cfa6: 07d6 lsls r6, r2, #31
|
|
801cfa8: d542 bpl.n 801d030 <__sflush_r+0xe8>
|
|
801cfaa: 2200 movs r2, #0
|
|
801cfac: 6062 str r2, [r4, #4]
|
|
801cfae: 04d9 lsls r1, r3, #19
|
|
801cfb0: 6922 ldr r2, [r4, #16]
|
|
801cfb2: 6022 str r2, [r4, #0]
|
|
801cfb4: d504 bpl.n 801cfc0 <__sflush_r+0x78>
|
|
801cfb6: 1c42 adds r2, r0, #1
|
|
801cfb8: d101 bne.n 801cfbe <__sflush_r+0x76>
|
|
801cfba: 682b ldr r3, [r5, #0]
|
|
801cfbc: b903 cbnz r3, 801cfc0 <__sflush_r+0x78>
|
|
801cfbe: 6560 str r0, [r4, #84] @ 0x54
|
|
801cfc0: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
801cfc2: 602f str r7, [r5, #0]
|
|
801cfc4: b1c1 cbz r1, 801cff8 <__sflush_r+0xb0>
|
|
801cfc6: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
801cfca: 4299 cmp r1, r3
|
|
801cfcc: d002 beq.n 801cfd4 <__sflush_r+0x8c>
|
|
801cfce: 4628 mov r0, r5
|
|
801cfd0: f7fe f8ee bl 801b1b0 <_free_r>
|
|
801cfd4: 2300 movs r3, #0
|
|
801cfd6: 6363 str r3, [r4, #52] @ 0x34
|
|
801cfd8: e00e b.n 801cff8 <__sflush_r+0xb0>
|
|
801cfda: 6a21 ldr r1, [r4, #32]
|
|
801cfdc: 2301 movs r3, #1
|
|
801cfde: 4628 mov r0, r5
|
|
801cfe0: 47b0 blx r6
|
|
801cfe2: 4602 mov r2, r0
|
|
801cfe4: 1c50 adds r0, r2, #1
|
|
801cfe6: d1c7 bne.n 801cf78 <__sflush_r+0x30>
|
|
801cfe8: 682b ldr r3, [r5, #0]
|
|
801cfea: 2b00 cmp r3, #0
|
|
801cfec: d0c4 beq.n 801cf78 <__sflush_r+0x30>
|
|
801cfee: 2b1d cmp r3, #29
|
|
801cff0: d001 beq.n 801cff6 <__sflush_r+0xae>
|
|
801cff2: 2b16 cmp r3, #22
|
|
801cff4: d11a bne.n 801d02c <__sflush_r+0xe4>
|
|
801cff6: 602f str r7, [r5, #0]
|
|
801cff8: 2000 movs r0, #0
|
|
801cffa: e01e b.n 801d03a <__sflush_r+0xf2>
|
|
801cffc: 690f ldr r7, [r1, #16]
|
|
801cffe: 2f00 cmp r7, #0
|
|
801d000: d0fa beq.n 801cff8 <__sflush_r+0xb0>
|
|
801d002: 0793 lsls r3, r2, #30
|
|
801d004: 680e ldr r6, [r1, #0]
|
|
801d006: bf08 it eq
|
|
801d008: 694b ldreq r3, [r1, #20]
|
|
801d00a: 600f str r7, [r1, #0]
|
|
801d00c: bf18 it ne
|
|
801d00e: 2300 movne r3, #0
|
|
801d010: eba6 0807 sub.w r8, r6, r7
|
|
801d014: 608b str r3, [r1, #8]
|
|
801d016: f1b8 0f00 cmp.w r8, #0
|
|
801d01a: dded ble.n 801cff8 <__sflush_r+0xb0>
|
|
801d01c: 6a21 ldr r1, [r4, #32]
|
|
801d01e: 6aa6 ldr r6, [r4, #40] @ 0x28
|
|
801d020: 4643 mov r3, r8
|
|
801d022: 463a mov r2, r7
|
|
801d024: 4628 mov r0, r5
|
|
801d026: 47b0 blx r6
|
|
801d028: 2800 cmp r0, #0
|
|
801d02a: dc08 bgt.n 801d03e <__sflush_r+0xf6>
|
|
801d02c: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801d030: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
801d034: 81a3 strh r3, [r4, #12]
|
|
801d036: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801d03a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
801d03e: 4407 add r7, r0
|
|
801d040: eba8 0800 sub.w r8, r8, r0
|
|
801d044: e7e7 b.n 801d016 <__sflush_r+0xce>
|
|
801d046: bf00 nop
|
|
801d048: 20400001 .word 0x20400001
|
|
|
|
0801d04c <_fflush_r>:
|
|
801d04c: b538 push {r3, r4, r5, lr}
|
|
801d04e: 690b ldr r3, [r1, #16]
|
|
801d050: 4605 mov r5, r0
|
|
801d052: 460c mov r4, r1
|
|
801d054: b913 cbnz r3, 801d05c <_fflush_r+0x10>
|
|
801d056: 2500 movs r5, #0
|
|
801d058: 4628 mov r0, r5
|
|
801d05a: bd38 pop {r3, r4, r5, pc}
|
|
801d05c: b118 cbz r0, 801d066 <_fflush_r+0x1a>
|
|
801d05e: 6a03 ldr r3, [r0, #32]
|
|
801d060: b90b cbnz r3, 801d066 <_fflush_r+0x1a>
|
|
801d062: f7fd f8a1 bl 801a1a8 <__sinit>
|
|
801d066: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801d06a: 2b00 cmp r3, #0
|
|
801d06c: d0f3 beq.n 801d056 <_fflush_r+0xa>
|
|
801d06e: 6e62 ldr r2, [r4, #100] @ 0x64
|
|
801d070: 07d0 lsls r0, r2, #31
|
|
801d072: d404 bmi.n 801d07e <_fflush_r+0x32>
|
|
801d074: 0599 lsls r1, r3, #22
|
|
801d076: d402 bmi.n 801d07e <_fflush_r+0x32>
|
|
801d078: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
801d07a: f7fd fa1e bl 801a4ba <__retarget_lock_acquire_recursive>
|
|
801d07e: 4628 mov r0, r5
|
|
801d080: 4621 mov r1, r4
|
|
801d082: f7ff ff61 bl 801cf48 <__sflush_r>
|
|
801d086: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
801d088: 07da lsls r2, r3, #31
|
|
801d08a: 4605 mov r5, r0
|
|
801d08c: d4e4 bmi.n 801d058 <_fflush_r+0xc>
|
|
801d08e: 89a3 ldrh r3, [r4, #12]
|
|
801d090: 059b lsls r3, r3, #22
|
|
801d092: d4e1 bmi.n 801d058 <_fflush_r+0xc>
|
|
801d094: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
801d096: f7fd fa11 bl 801a4bc <__retarget_lock_release_recursive>
|
|
801d09a: e7dd b.n 801d058 <_fflush_r+0xc>
|
|
|
|
0801d09c <__swbuf_r>:
|
|
801d09c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801d09e: 460e mov r6, r1
|
|
801d0a0: 4614 mov r4, r2
|
|
801d0a2: 4605 mov r5, r0
|
|
801d0a4: b118 cbz r0, 801d0ae <__swbuf_r+0x12>
|
|
801d0a6: 6a03 ldr r3, [r0, #32]
|
|
801d0a8: b90b cbnz r3, 801d0ae <__swbuf_r+0x12>
|
|
801d0aa: f7fd f87d bl 801a1a8 <__sinit>
|
|
801d0ae: 69a3 ldr r3, [r4, #24]
|
|
801d0b0: 60a3 str r3, [r4, #8]
|
|
801d0b2: 89a3 ldrh r3, [r4, #12]
|
|
801d0b4: 071a lsls r2, r3, #28
|
|
801d0b6: d501 bpl.n 801d0bc <__swbuf_r+0x20>
|
|
801d0b8: 6923 ldr r3, [r4, #16]
|
|
801d0ba: b943 cbnz r3, 801d0ce <__swbuf_r+0x32>
|
|
801d0bc: 4621 mov r1, r4
|
|
801d0be: 4628 mov r0, r5
|
|
801d0c0: f000 f82a bl 801d118 <__swsetup_r>
|
|
801d0c4: b118 cbz r0, 801d0ce <__swbuf_r+0x32>
|
|
801d0c6: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
|
|
801d0ca: 4638 mov r0, r7
|
|
801d0cc: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
801d0ce: 6823 ldr r3, [r4, #0]
|
|
801d0d0: 6922 ldr r2, [r4, #16]
|
|
801d0d2: 1a98 subs r0, r3, r2
|
|
801d0d4: 6963 ldr r3, [r4, #20]
|
|
801d0d6: b2f6 uxtb r6, r6
|
|
801d0d8: 4283 cmp r3, r0
|
|
801d0da: 4637 mov r7, r6
|
|
801d0dc: dc05 bgt.n 801d0ea <__swbuf_r+0x4e>
|
|
801d0de: 4621 mov r1, r4
|
|
801d0e0: 4628 mov r0, r5
|
|
801d0e2: f7ff ffb3 bl 801d04c <_fflush_r>
|
|
801d0e6: 2800 cmp r0, #0
|
|
801d0e8: d1ed bne.n 801d0c6 <__swbuf_r+0x2a>
|
|
801d0ea: 68a3 ldr r3, [r4, #8]
|
|
801d0ec: 3b01 subs r3, #1
|
|
801d0ee: 60a3 str r3, [r4, #8]
|
|
801d0f0: 6823 ldr r3, [r4, #0]
|
|
801d0f2: 1c5a adds r2, r3, #1
|
|
801d0f4: 6022 str r2, [r4, #0]
|
|
801d0f6: 701e strb r6, [r3, #0]
|
|
801d0f8: 6962 ldr r2, [r4, #20]
|
|
801d0fa: 1c43 adds r3, r0, #1
|
|
801d0fc: 429a cmp r2, r3
|
|
801d0fe: d004 beq.n 801d10a <__swbuf_r+0x6e>
|
|
801d100: 89a3 ldrh r3, [r4, #12]
|
|
801d102: 07db lsls r3, r3, #31
|
|
801d104: d5e1 bpl.n 801d0ca <__swbuf_r+0x2e>
|
|
801d106: 2e0a cmp r6, #10
|
|
801d108: d1df bne.n 801d0ca <__swbuf_r+0x2e>
|
|
801d10a: 4621 mov r1, r4
|
|
801d10c: 4628 mov r0, r5
|
|
801d10e: f7ff ff9d bl 801d04c <_fflush_r>
|
|
801d112: 2800 cmp r0, #0
|
|
801d114: d0d9 beq.n 801d0ca <__swbuf_r+0x2e>
|
|
801d116: e7d6 b.n 801d0c6 <__swbuf_r+0x2a>
|
|
|
|
0801d118 <__swsetup_r>:
|
|
801d118: b538 push {r3, r4, r5, lr}
|
|
801d11a: 4b28 ldr r3, [pc, #160] @ (801d1bc <__swsetup_r+0xa4>)
|
|
801d11c: 4605 mov r5, r0
|
|
801d11e: 6818 ldr r0, [r3, #0]
|
|
801d120: 460c mov r4, r1
|
|
801d122: b118 cbz r0, 801d12c <__swsetup_r+0x14>
|
|
801d124: 6a03 ldr r3, [r0, #32]
|
|
801d126: b90b cbnz r3, 801d12c <__swsetup_r+0x14>
|
|
801d128: f7fd f83e bl 801a1a8 <__sinit>
|
|
801d12c: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801d130: 071a lsls r2, r3, #28
|
|
801d132: d421 bmi.n 801d178 <__swsetup_r+0x60>
|
|
801d134: 06d8 lsls r0, r3, #27
|
|
801d136: d407 bmi.n 801d148 <__swsetup_r+0x30>
|
|
801d138: 2209 movs r2, #9
|
|
801d13a: 602a str r2, [r5, #0]
|
|
801d13c: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
801d140: 81a3 strh r3, [r4, #12]
|
|
801d142: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801d146: e030 b.n 801d1aa <__swsetup_r+0x92>
|
|
801d148: 0759 lsls r1, r3, #29
|
|
801d14a: d512 bpl.n 801d172 <__swsetup_r+0x5a>
|
|
801d14c: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
801d14e: b141 cbz r1, 801d162 <__swsetup_r+0x4a>
|
|
801d150: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
801d154: 4299 cmp r1, r3
|
|
801d156: d002 beq.n 801d15e <__swsetup_r+0x46>
|
|
801d158: 4628 mov r0, r5
|
|
801d15a: f7fe f829 bl 801b1b0 <_free_r>
|
|
801d15e: 2300 movs r3, #0
|
|
801d160: 6363 str r3, [r4, #52] @ 0x34
|
|
801d162: 2200 movs r2, #0
|
|
801d164: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801d168: 6062 str r2, [r4, #4]
|
|
801d16a: 6922 ldr r2, [r4, #16]
|
|
801d16c: 6022 str r2, [r4, #0]
|
|
801d16e: f023 0324 bic.w r3, r3, #36 @ 0x24
|
|
801d172: f043 0308 orr.w r3, r3, #8
|
|
801d176: 81a3 strh r3, [r4, #12]
|
|
801d178: 6922 ldr r2, [r4, #16]
|
|
801d17a: b93a cbnz r2, 801d18c <__swsetup_r+0x74>
|
|
801d17c: 059a lsls r2, r3, #22
|
|
801d17e: d501 bpl.n 801d184 <__swsetup_r+0x6c>
|
|
801d180: 0618 lsls r0, r3, #24
|
|
801d182: d503 bpl.n 801d18c <__swsetup_r+0x74>
|
|
801d184: 4621 mov r1, r4
|
|
801d186: 4628 mov r0, r5
|
|
801d188: f000 fc4e bl 801da28 <__smakebuf_r>
|
|
801d18c: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801d190: f013 0201 ands.w r2, r3, #1
|
|
801d194: d00a beq.n 801d1ac <__swsetup_r+0x94>
|
|
801d196: 2200 movs r2, #0
|
|
801d198: 60a2 str r2, [r4, #8]
|
|
801d19a: 6962 ldr r2, [r4, #20]
|
|
801d19c: 4252 negs r2, r2
|
|
801d19e: 61a2 str r2, [r4, #24]
|
|
801d1a0: 6922 ldr r2, [r4, #16]
|
|
801d1a2: b942 cbnz r2, 801d1b6 <__swsetup_r+0x9e>
|
|
801d1a4: f013 0080 ands.w r0, r3, #128 @ 0x80
|
|
801d1a8: d1c8 bne.n 801d13c <__swsetup_r+0x24>
|
|
801d1aa: bd38 pop {r3, r4, r5, pc}
|
|
801d1ac: 0799 lsls r1, r3, #30
|
|
801d1ae: bf58 it pl
|
|
801d1b0: 6962 ldrpl r2, [r4, #20]
|
|
801d1b2: 60a2 str r2, [r4, #8]
|
|
801d1b4: e7f4 b.n 801d1a0 <__swsetup_r+0x88>
|
|
801d1b6: 2000 movs r0, #0
|
|
801d1b8: e7f7 b.n 801d1aa <__swsetup_r+0x92>
|
|
801d1ba: bf00 nop
|
|
801d1bc: 2000011c .word 0x2000011c
|
|
|
|
0801d1c0 <memmove>:
|
|
801d1c0: 4288 cmp r0, r1
|
|
801d1c2: b510 push {r4, lr}
|
|
801d1c4: eb01 0402 add.w r4, r1, r2
|
|
801d1c8: d902 bls.n 801d1d0 <memmove+0x10>
|
|
801d1ca: 4284 cmp r4, r0
|
|
801d1cc: 4623 mov r3, r4
|
|
801d1ce: d807 bhi.n 801d1e0 <memmove+0x20>
|
|
801d1d0: 1e43 subs r3, r0, #1
|
|
801d1d2: 42a1 cmp r1, r4
|
|
801d1d4: d007 beq.n 801d1e6 <memmove+0x26>
|
|
801d1d6: f811 2b01 ldrb.w r2, [r1], #1
|
|
801d1da: f803 2f01 strb.w r2, [r3, #1]!
|
|
801d1de: e7f8 b.n 801d1d2 <memmove+0x12>
|
|
801d1e0: 4402 add r2, r0
|
|
801d1e2: 4282 cmp r2, r0
|
|
801d1e4: d100 bne.n 801d1e8 <memmove+0x28>
|
|
801d1e6: bd10 pop {r4, pc}
|
|
801d1e8: f813 1d01 ldrb.w r1, [r3, #-1]!
|
|
801d1ec: f802 1d01 strb.w r1, [r2, #-1]!
|
|
801d1f0: e7f7 b.n 801d1e2 <memmove+0x22>
|
|
|
|
0801d1f2 <strncmp>:
|
|
801d1f2: b510 push {r4, lr}
|
|
801d1f4: b16a cbz r2, 801d212 <strncmp+0x20>
|
|
801d1f6: 3901 subs r1, #1
|
|
801d1f8: 1884 adds r4, r0, r2
|
|
801d1fa: f810 2b01 ldrb.w r2, [r0], #1
|
|
801d1fe: f811 3f01 ldrb.w r3, [r1, #1]!
|
|
801d202: 429a cmp r2, r3
|
|
801d204: d103 bne.n 801d20e <strncmp+0x1c>
|
|
801d206: 42a0 cmp r0, r4
|
|
801d208: d001 beq.n 801d20e <strncmp+0x1c>
|
|
801d20a: 2a00 cmp r2, #0
|
|
801d20c: d1f5 bne.n 801d1fa <strncmp+0x8>
|
|
801d20e: 1ad0 subs r0, r2, r3
|
|
801d210: bd10 pop {r4, pc}
|
|
801d212: 4610 mov r0, r2
|
|
801d214: e7fc b.n 801d210 <strncmp+0x1e>
|
|
...
|
|
|
|
0801d218 <_sbrk_r>:
|
|
801d218: b538 push {r3, r4, r5, lr}
|
|
801d21a: 4d06 ldr r5, [pc, #24] @ (801d234 <_sbrk_r+0x1c>)
|
|
801d21c: 2300 movs r3, #0
|
|
801d21e: 4604 mov r4, r0
|
|
801d220: 4608 mov r0, r1
|
|
801d222: 602b str r3, [r5, #0]
|
|
801d224: f7e9 faac bl 8006780 <_sbrk>
|
|
801d228: 1c43 adds r3, r0, #1
|
|
801d22a: d102 bne.n 801d232 <_sbrk_r+0x1a>
|
|
801d22c: 682b ldr r3, [r5, #0]
|
|
801d22e: b103 cbz r3, 801d232 <_sbrk_r+0x1a>
|
|
801d230: 6023 str r3, [r4, #0]
|
|
801d232: bd38 pop {r3, r4, r5, pc}
|
|
801d234: 20013cd8 .word 0x20013cd8
|
|
|
|
0801d238 <nan>:
|
|
801d238: ed9f 0b01 vldr d0, [pc, #4] @ 801d240 <nan+0x8>
|
|
801d23c: 4770 bx lr
|
|
801d23e: bf00 nop
|
|
801d240: 00000000 .word 0x00000000
|
|
801d244: 7ff80000 .word 0x7ff80000
|
|
|
|
0801d248 <__assert_func>:
|
|
801d248: b51f push {r0, r1, r2, r3, r4, lr}
|
|
801d24a: 4614 mov r4, r2
|
|
801d24c: 461a mov r2, r3
|
|
801d24e: 4b09 ldr r3, [pc, #36] @ (801d274 <__assert_func+0x2c>)
|
|
801d250: 681b ldr r3, [r3, #0]
|
|
801d252: 4605 mov r5, r0
|
|
801d254: 68d8 ldr r0, [r3, #12]
|
|
801d256: b14c cbz r4, 801d26c <__assert_func+0x24>
|
|
801d258: 4b07 ldr r3, [pc, #28] @ (801d278 <__assert_func+0x30>)
|
|
801d25a: 9100 str r1, [sp, #0]
|
|
801d25c: e9cd 3401 strd r3, r4, [sp, #4]
|
|
801d260: 4906 ldr r1, [pc, #24] @ (801d27c <__assert_func+0x34>)
|
|
801d262: 462b mov r3, r5
|
|
801d264: f000 fbaa bl 801d9bc <fiprintf>
|
|
801d268: f000 fc3a bl 801dae0 <abort>
|
|
801d26c: 4b04 ldr r3, [pc, #16] @ (801d280 <__assert_func+0x38>)
|
|
801d26e: 461c mov r4, r3
|
|
801d270: e7f3 b.n 801d25a <__assert_func+0x12>
|
|
801d272: bf00 nop
|
|
801d274: 2000011c .word 0x2000011c
|
|
801d278: 0801e74a .word 0x0801e74a
|
|
801d27c: 0801e757 .word 0x0801e757
|
|
801d280: 0801e785 .word 0x0801e785
|
|
|
|
0801d284 <_calloc_r>:
|
|
801d284: b570 push {r4, r5, r6, lr}
|
|
801d286: fba1 5402 umull r5, r4, r1, r2
|
|
801d28a: b934 cbnz r4, 801d29a <_calloc_r+0x16>
|
|
801d28c: 4629 mov r1, r5
|
|
801d28e: f7fe f803 bl 801b298 <_malloc_r>
|
|
801d292: 4606 mov r6, r0
|
|
801d294: b928 cbnz r0, 801d2a2 <_calloc_r+0x1e>
|
|
801d296: 4630 mov r0, r6
|
|
801d298: bd70 pop {r4, r5, r6, pc}
|
|
801d29a: 220c movs r2, #12
|
|
801d29c: 6002 str r2, [r0, #0]
|
|
801d29e: 2600 movs r6, #0
|
|
801d2a0: e7f9 b.n 801d296 <_calloc_r+0x12>
|
|
801d2a2: 462a mov r2, r5
|
|
801d2a4: 4621 mov r1, r4
|
|
801d2a6: f7fd f82d bl 801a304 <memset>
|
|
801d2aa: e7f4 b.n 801d296 <_calloc_r+0x12>
|
|
|
|
0801d2ac <rshift>:
|
|
801d2ac: 6903 ldr r3, [r0, #16]
|
|
801d2ae: ebb3 1f61 cmp.w r3, r1, asr #5
|
|
801d2b2: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
|
|
801d2b6: ea4f 1261 mov.w r2, r1, asr #5
|
|
801d2ba: f100 0414 add.w r4, r0, #20
|
|
801d2be: dd45 ble.n 801d34c <rshift+0xa0>
|
|
801d2c0: f011 011f ands.w r1, r1, #31
|
|
801d2c4: eb04 0683 add.w r6, r4, r3, lsl #2
|
|
801d2c8: eb04 0582 add.w r5, r4, r2, lsl #2
|
|
801d2cc: d10c bne.n 801d2e8 <rshift+0x3c>
|
|
801d2ce: f100 0710 add.w r7, r0, #16
|
|
801d2d2: 4629 mov r1, r5
|
|
801d2d4: 42b1 cmp r1, r6
|
|
801d2d6: d334 bcc.n 801d342 <rshift+0x96>
|
|
801d2d8: 1a9b subs r3, r3, r2
|
|
801d2da: 009b lsls r3, r3, #2
|
|
801d2dc: 1eea subs r2, r5, #3
|
|
801d2de: 4296 cmp r6, r2
|
|
801d2e0: bf38 it cc
|
|
801d2e2: 2300 movcc r3, #0
|
|
801d2e4: 4423 add r3, r4
|
|
801d2e6: e015 b.n 801d314 <rshift+0x68>
|
|
801d2e8: f854 7022 ldr.w r7, [r4, r2, lsl #2]
|
|
801d2ec: f1c1 0820 rsb r8, r1, #32
|
|
801d2f0: 40cf lsrs r7, r1
|
|
801d2f2: f105 0e04 add.w lr, r5, #4
|
|
801d2f6: 46a1 mov r9, r4
|
|
801d2f8: 4576 cmp r6, lr
|
|
801d2fa: 46f4 mov ip, lr
|
|
801d2fc: d815 bhi.n 801d32a <rshift+0x7e>
|
|
801d2fe: 1a9a subs r2, r3, r2
|
|
801d300: 0092 lsls r2, r2, #2
|
|
801d302: 3a04 subs r2, #4
|
|
801d304: 3501 adds r5, #1
|
|
801d306: 42ae cmp r6, r5
|
|
801d308: bf38 it cc
|
|
801d30a: 2200 movcc r2, #0
|
|
801d30c: 18a3 adds r3, r4, r2
|
|
801d30e: 50a7 str r7, [r4, r2]
|
|
801d310: b107 cbz r7, 801d314 <rshift+0x68>
|
|
801d312: 3304 adds r3, #4
|
|
801d314: 1b1a subs r2, r3, r4
|
|
801d316: 42a3 cmp r3, r4
|
|
801d318: ea4f 02a2 mov.w r2, r2, asr #2
|
|
801d31c: bf08 it eq
|
|
801d31e: 2300 moveq r3, #0
|
|
801d320: 6102 str r2, [r0, #16]
|
|
801d322: bf08 it eq
|
|
801d324: 6143 streq r3, [r0, #20]
|
|
801d326: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
801d32a: f8dc c000 ldr.w ip, [ip]
|
|
801d32e: fa0c fc08 lsl.w ip, ip, r8
|
|
801d332: ea4c 0707 orr.w r7, ip, r7
|
|
801d336: f849 7b04 str.w r7, [r9], #4
|
|
801d33a: f85e 7b04 ldr.w r7, [lr], #4
|
|
801d33e: 40cf lsrs r7, r1
|
|
801d340: e7da b.n 801d2f8 <rshift+0x4c>
|
|
801d342: f851 cb04 ldr.w ip, [r1], #4
|
|
801d346: f847 cf04 str.w ip, [r7, #4]!
|
|
801d34a: e7c3 b.n 801d2d4 <rshift+0x28>
|
|
801d34c: 4623 mov r3, r4
|
|
801d34e: e7e1 b.n 801d314 <rshift+0x68>
|
|
|
|
0801d350 <__hexdig_fun>:
|
|
801d350: f1a0 0330 sub.w r3, r0, #48 @ 0x30
|
|
801d354: 2b09 cmp r3, #9
|
|
801d356: d802 bhi.n 801d35e <__hexdig_fun+0xe>
|
|
801d358: 3820 subs r0, #32
|
|
801d35a: b2c0 uxtb r0, r0
|
|
801d35c: 4770 bx lr
|
|
801d35e: f1a0 0361 sub.w r3, r0, #97 @ 0x61
|
|
801d362: 2b05 cmp r3, #5
|
|
801d364: d801 bhi.n 801d36a <__hexdig_fun+0x1a>
|
|
801d366: 3847 subs r0, #71 @ 0x47
|
|
801d368: e7f7 b.n 801d35a <__hexdig_fun+0xa>
|
|
801d36a: f1a0 0341 sub.w r3, r0, #65 @ 0x41
|
|
801d36e: 2b05 cmp r3, #5
|
|
801d370: d801 bhi.n 801d376 <__hexdig_fun+0x26>
|
|
801d372: 3827 subs r0, #39 @ 0x27
|
|
801d374: e7f1 b.n 801d35a <__hexdig_fun+0xa>
|
|
801d376: 2000 movs r0, #0
|
|
801d378: 4770 bx lr
|
|
...
|
|
|
|
0801d37c <__gethex>:
|
|
801d37c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801d380: b085 sub sp, #20
|
|
801d382: 468a mov sl, r1
|
|
801d384: 9302 str r3, [sp, #8]
|
|
801d386: 680b ldr r3, [r1, #0]
|
|
801d388: 9001 str r0, [sp, #4]
|
|
801d38a: 4690 mov r8, r2
|
|
801d38c: 1c9c adds r4, r3, #2
|
|
801d38e: 46a1 mov r9, r4
|
|
801d390: f814 0b01 ldrb.w r0, [r4], #1
|
|
801d394: 2830 cmp r0, #48 @ 0x30
|
|
801d396: d0fa beq.n 801d38e <__gethex+0x12>
|
|
801d398: eba9 0303 sub.w r3, r9, r3
|
|
801d39c: f1a3 0b02 sub.w fp, r3, #2
|
|
801d3a0: f7ff ffd6 bl 801d350 <__hexdig_fun>
|
|
801d3a4: 4605 mov r5, r0
|
|
801d3a6: 2800 cmp r0, #0
|
|
801d3a8: d168 bne.n 801d47c <__gethex+0x100>
|
|
801d3aa: 49a0 ldr r1, [pc, #640] @ (801d62c <__gethex+0x2b0>)
|
|
801d3ac: 2201 movs r2, #1
|
|
801d3ae: 4648 mov r0, r9
|
|
801d3b0: f7ff ff1f bl 801d1f2 <strncmp>
|
|
801d3b4: 4607 mov r7, r0
|
|
801d3b6: 2800 cmp r0, #0
|
|
801d3b8: d167 bne.n 801d48a <__gethex+0x10e>
|
|
801d3ba: f899 0001 ldrb.w r0, [r9, #1]
|
|
801d3be: 4626 mov r6, r4
|
|
801d3c0: f7ff ffc6 bl 801d350 <__hexdig_fun>
|
|
801d3c4: 2800 cmp r0, #0
|
|
801d3c6: d062 beq.n 801d48e <__gethex+0x112>
|
|
801d3c8: 4623 mov r3, r4
|
|
801d3ca: 7818 ldrb r0, [r3, #0]
|
|
801d3cc: 2830 cmp r0, #48 @ 0x30
|
|
801d3ce: 4699 mov r9, r3
|
|
801d3d0: f103 0301 add.w r3, r3, #1
|
|
801d3d4: d0f9 beq.n 801d3ca <__gethex+0x4e>
|
|
801d3d6: f7ff ffbb bl 801d350 <__hexdig_fun>
|
|
801d3da: fab0 f580 clz r5, r0
|
|
801d3de: 096d lsrs r5, r5, #5
|
|
801d3e0: f04f 0b01 mov.w fp, #1
|
|
801d3e4: 464a mov r2, r9
|
|
801d3e6: 4616 mov r6, r2
|
|
801d3e8: 3201 adds r2, #1
|
|
801d3ea: 7830 ldrb r0, [r6, #0]
|
|
801d3ec: f7ff ffb0 bl 801d350 <__hexdig_fun>
|
|
801d3f0: 2800 cmp r0, #0
|
|
801d3f2: d1f8 bne.n 801d3e6 <__gethex+0x6a>
|
|
801d3f4: 498d ldr r1, [pc, #564] @ (801d62c <__gethex+0x2b0>)
|
|
801d3f6: 2201 movs r2, #1
|
|
801d3f8: 4630 mov r0, r6
|
|
801d3fa: f7ff fefa bl 801d1f2 <strncmp>
|
|
801d3fe: 2800 cmp r0, #0
|
|
801d400: d13f bne.n 801d482 <__gethex+0x106>
|
|
801d402: b944 cbnz r4, 801d416 <__gethex+0x9a>
|
|
801d404: 1c74 adds r4, r6, #1
|
|
801d406: 4622 mov r2, r4
|
|
801d408: 4616 mov r6, r2
|
|
801d40a: 3201 adds r2, #1
|
|
801d40c: 7830 ldrb r0, [r6, #0]
|
|
801d40e: f7ff ff9f bl 801d350 <__hexdig_fun>
|
|
801d412: 2800 cmp r0, #0
|
|
801d414: d1f8 bne.n 801d408 <__gethex+0x8c>
|
|
801d416: 1ba4 subs r4, r4, r6
|
|
801d418: 00a7 lsls r7, r4, #2
|
|
801d41a: 7833 ldrb r3, [r6, #0]
|
|
801d41c: f003 03df and.w r3, r3, #223 @ 0xdf
|
|
801d420: 2b50 cmp r3, #80 @ 0x50
|
|
801d422: d13e bne.n 801d4a2 <__gethex+0x126>
|
|
801d424: 7873 ldrb r3, [r6, #1]
|
|
801d426: 2b2b cmp r3, #43 @ 0x2b
|
|
801d428: d033 beq.n 801d492 <__gethex+0x116>
|
|
801d42a: 2b2d cmp r3, #45 @ 0x2d
|
|
801d42c: d034 beq.n 801d498 <__gethex+0x11c>
|
|
801d42e: 1c71 adds r1, r6, #1
|
|
801d430: 2400 movs r4, #0
|
|
801d432: 7808 ldrb r0, [r1, #0]
|
|
801d434: f7ff ff8c bl 801d350 <__hexdig_fun>
|
|
801d438: 1e43 subs r3, r0, #1
|
|
801d43a: b2db uxtb r3, r3
|
|
801d43c: 2b18 cmp r3, #24
|
|
801d43e: d830 bhi.n 801d4a2 <__gethex+0x126>
|
|
801d440: f1a0 0210 sub.w r2, r0, #16
|
|
801d444: f811 0f01 ldrb.w r0, [r1, #1]!
|
|
801d448: f7ff ff82 bl 801d350 <__hexdig_fun>
|
|
801d44c: f100 3cff add.w ip, r0, #4294967295 @ 0xffffffff
|
|
801d450: fa5f fc8c uxtb.w ip, ip
|
|
801d454: f1bc 0f18 cmp.w ip, #24
|
|
801d458: f04f 030a mov.w r3, #10
|
|
801d45c: d91e bls.n 801d49c <__gethex+0x120>
|
|
801d45e: b104 cbz r4, 801d462 <__gethex+0xe6>
|
|
801d460: 4252 negs r2, r2
|
|
801d462: 4417 add r7, r2
|
|
801d464: f8ca 1000 str.w r1, [sl]
|
|
801d468: b1ed cbz r5, 801d4a6 <__gethex+0x12a>
|
|
801d46a: f1bb 0f00 cmp.w fp, #0
|
|
801d46e: bf0c ite eq
|
|
801d470: 2506 moveq r5, #6
|
|
801d472: 2500 movne r5, #0
|
|
801d474: 4628 mov r0, r5
|
|
801d476: b005 add sp, #20
|
|
801d478: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801d47c: 2500 movs r5, #0
|
|
801d47e: 462c mov r4, r5
|
|
801d480: e7b0 b.n 801d3e4 <__gethex+0x68>
|
|
801d482: 2c00 cmp r4, #0
|
|
801d484: d1c7 bne.n 801d416 <__gethex+0x9a>
|
|
801d486: 4627 mov r7, r4
|
|
801d488: e7c7 b.n 801d41a <__gethex+0x9e>
|
|
801d48a: 464e mov r6, r9
|
|
801d48c: 462f mov r7, r5
|
|
801d48e: 2501 movs r5, #1
|
|
801d490: e7c3 b.n 801d41a <__gethex+0x9e>
|
|
801d492: 2400 movs r4, #0
|
|
801d494: 1cb1 adds r1, r6, #2
|
|
801d496: e7cc b.n 801d432 <__gethex+0xb6>
|
|
801d498: 2401 movs r4, #1
|
|
801d49a: e7fb b.n 801d494 <__gethex+0x118>
|
|
801d49c: fb03 0002 mla r0, r3, r2, r0
|
|
801d4a0: e7ce b.n 801d440 <__gethex+0xc4>
|
|
801d4a2: 4631 mov r1, r6
|
|
801d4a4: e7de b.n 801d464 <__gethex+0xe8>
|
|
801d4a6: eba6 0309 sub.w r3, r6, r9
|
|
801d4aa: 3b01 subs r3, #1
|
|
801d4ac: 4629 mov r1, r5
|
|
801d4ae: 2b07 cmp r3, #7
|
|
801d4b0: dc0a bgt.n 801d4c8 <__gethex+0x14c>
|
|
801d4b2: 9801 ldr r0, [sp, #4]
|
|
801d4b4: f7fd ff7c bl 801b3b0 <_Balloc>
|
|
801d4b8: 4604 mov r4, r0
|
|
801d4ba: b940 cbnz r0, 801d4ce <__gethex+0x152>
|
|
801d4bc: 4b5c ldr r3, [pc, #368] @ (801d630 <__gethex+0x2b4>)
|
|
801d4be: 4602 mov r2, r0
|
|
801d4c0: 21e4 movs r1, #228 @ 0xe4
|
|
801d4c2: 485c ldr r0, [pc, #368] @ (801d634 <__gethex+0x2b8>)
|
|
801d4c4: f7ff fec0 bl 801d248 <__assert_func>
|
|
801d4c8: 3101 adds r1, #1
|
|
801d4ca: 105b asrs r3, r3, #1
|
|
801d4cc: e7ef b.n 801d4ae <__gethex+0x132>
|
|
801d4ce: f100 0a14 add.w sl, r0, #20
|
|
801d4d2: 2300 movs r3, #0
|
|
801d4d4: 4655 mov r5, sl
|
|
801d4d6: 469b mov fp, r3
|
|
801d4d8: 45b1 cmp r9, r6
|
|
801d4da: d337 bcc.n 801d54c <__gethex+0x1d0>
|
|
801d4dc: f845 bb04 str.w fp, [r5], #4
|
|
801d4e0: eba5 050a sub.w r5, r5, sl
|
|
801d4e4: 10ad asrs r5, r5, #2
|
|
801d4e6: 6125 str r5, [r4, #16]
|
|
801d4e8: 4658 mov r0, fp
|
|
801d4ea: f7fe f851 bl 801b590 <__hi0bits>
|
|
801d4ee: 016d lsls r5, r5, #5
|
|
801d4f0: f8d8 6000 ldr.w r6, [r8]
|
|
801d4f4: 1a2d subs r5, r5, r0
|
|
801d4f6: 42b5 cmp r5, r6
|
|
801d4f8: dd54 ble.n 801d5a4 <__gethex+0x228>
|
|
801d4fa: 1bad subs r5, r5, r6
|
|
801d4fc: 4629 mov r1, r5
|
|
801d4fe: 4620 mov r0, r4
|
|
801d500: f7fe fbed bl 801bcde <__any_on>
|
|
801d504: 4681 mov r9, r0
|
|
801d506: b178 cbz r0, 801d528 <__gethex+0x1ac>
|
|
801d508: 1e6b subs r3, r5, #1
|
|
801d50a: 1159 asrs r1, r3, #5
|
|
801d50c: f003 021f and.w r2, r3, #31
|
|
801d510: f85a 1021 ldr.w r1, [sl, r1, lsl #2]
|
|
801d514: f04f 0901 mov.w r9, #1
|
|
801d518: fa09 f202 lsl.w r2, r9, r2
|
|
801d51c: 420a tst r2, r1
|
|
801d51e: d003 beq.n 801d528 <__gethex+0x1ac>
|
|
801d520: 454b cmp r3, r9
|
|
801d522: dc36 bgt.n 801d592 <__gethex+0x216>
|
|
801d524: f04f 0902 mov.w r9, #2
|
|
801d528: 4629 mov r1, r5
|
|
801d52a: 4620 mov r0, r4
|
|
801d52c: f7ff febe bl 801d2ac <rshift>
|
|
801d530: 442f add r7, r5
|
|
801d532: f8d8 3008 ldr.w r3, [r8, #8]
|
|
801d536: 42bb cmp r3, r7
|
|
801d538: da42 bge.n 801d5c0 <__gethex+0x244>
|
|
801d53a: 9801 ldr r0, [sp, #4]
|
|
801d53c: 4621 mov r1, r4
|
|
801d53e: f7fd ff75 bl 801b42c <_Bfree>
|
|
801d542: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
801d544: 2300 movs r3, #0
|
|
801d546: 6013 str r3, [r2, #0]
|
|
801d548: 25a3 movs r5, #163 @ 0xa3
|
|
801d54a: e793 b.n 801d474 <__gethex+0xf8>
|
|
801d54c: f816 2d01 ldrb.w r2, [r6, #-1]!
|
|
801d550: 2a2e cmp r2, #46 @ 0x2e
|
|
801d552: d012 beq.n 801d57a <__gethex+0x1fe>
|
|
801d554: 2b20 cmp r3, #32
|
|
801d556: d104 bne.n 801d562 <__gethex+0x1e6>
|
|
801d558: f845 bb04 str.w fp, [r5], #4
|
|
801d55c: f04f 0b00 mov.w fp, #0
|
|
801d560: 465b mov r3, fp
|
|
801d562: 7830 ldrb r0, [r6, #0]
|
|
801d564: 9303 str r3, [sp, #12]
|
|
801d566: f7ff fef3 bl 801d350 <__hexdig_fun>
|
|
801d56a: 9b03 ldr r3, [sp, #12]
|
|
801d56c: f000 000f and.w r0, r0, #15
|
|
801d570: 4098 lsls r0, r3
|
|
801d572: ea4b 0b00 orr.w fp, fp, r0
|
|
801d576: 3304 adds r3, #4
|
|
801d578: e7ae b.n 801d4d8 <__gethex+0x15c>
|
|
801d57a: 45b1 cmp r9, r6
|
|
801d57c: d8ea bhi.n 801d554 <__gethex+0x1d8>
|
|
801d57e: 492b ldr r1, [pc, #172] @ (801d62c <__gethex+0x2b0>)
|
|
801d580: 9303 str r3, [sp, #12]
|
|
801d582: 2201 movs r2, #1
|
|
801d584: 4630 mov r0, r6
|
|
801d586: f7ff fe34 bl 801d1f2 <strncmp>
|
|
801d58a: 9b03 ldr r3, [sp, #12]
|
|
801d58c: 2800 cmp r0, #0
|
|
801d58e: d1e1 bne.n 801d554 <__gethex+0x1d8>
|
|
801d590: e7a2 b.n 801d4d8 <__gethex+0x15c>
|
|
801d592: 1ea9 subs r1, r5, #2
|
|
801d594: 4620 mov r0, r4
|
|
801d596: f7fe fba2 bl 801bcde <__any_on>
|
|
801d59a: 2800 cmp r0, #0
|
|
801d59c: d0c2 beq.n 801d524 <__gethex+0x1a8>
|
|
801d59e: f04f 0903 mov.w r9, #3
|
|
801d5a2: e7c1 b.n 801d528 <__gethex+0x1ac>
|
|
801d5a4: da09 bge.n 801d5ba <__gethex+0x23e>
|
|
801d5a6: 1b75 subs r5, r6, r5
|
|
801d5a8: 4621 mov r1, r4
|
|
801d5aa: 9801 ldr r0, [sp, #4]
|
|
801d5ac: 462a mov r2, r5
|
|
801d5ae: f7fe f957 bl 801b860 <__lshift>
|
|
801d5b2: 1b7f subs r7, r7, r5
|
|
801d5b4: 4604 mov r4, r0
|
|
801d5b6: f100 0a14 add.w sl, r0, #20
|
|
801d5ba: f04f 0900 mov.w r9, #0
|
|
801d5be: e7b8 b.n 801d532 <__gethex+0x1b6>
|
|
801d5c0: f8d8 5004 ldr.w r5, [r8, #4]
|
|
801d5c4: 42bd cmp r5, r7
|
|
801d5c6: dd6f ble.n 801d6a8 <__gethex+0x32c>
|
|
801d5c8: 1bed subs r5, r5, r7
|
|
801d5ca: 42ae cmp r6, r5
|
|
801d5cc: dc34 bgt.n 801d638 <__gethex+0x2bc>
|
|
801d5ce: f8d8 300c ldr.w r3, [r8, #12]
|
|
801d5d2: 2b02 cmp r3, #2
|
|
801d5d4: d022 beq.n 801d61c <__gethex+0x2a0>
|
|
801d5d6: 2b03 cmp r3, #3
|
|
801d5d8: d024 beq.n 801d624 <__gethex+0x2a8>
|
|
801d5da: 2b01 cmp r3, #1
|
|
801d5dc: d115 bne.n 801d60a <__gethex+0x28e>
|
|
801d5de: 42ae cmp r6, r5
|
|
801d5e0: d113 bne.n 801d60a <__gethex+0x28e>
|
|
801d5e2: 2e01 cmp r6, #1
|
|
801d5e4: d10b bne.n 801d5fe <__gethex+0x282>
|
|
801d5e6: 9a02 ldr r2, [sp, #8]
|
|
801d5e8: f8d8 3004 ldr.w r3, [r8, #4]
|
|
801d5ec: 6013 str r3, [r2, #0]
|
|
801d5ee: 2301 movs r3, #1
|
|
801d5f0: 6123 str r3, [r4, #16]
|
|
801d5f2: f8ca 3000 str.w r3, [sl]
|
|
801d5f6: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
801d5f8: 2562 movs r5, #98 @ 0x62
|
|
801d5fa: 601c str r4, [r3, #0]
|
|
801d5fc: e73a b.n 801d474 <__gethex+0xf8>
|
|
801d5fe: 1e71 subs r1, r6, #1
|
|
801d600: 4620 mov r0, r4
|
|
801d602: f7fe fb6c bl 801bcde <__any_on>
|
|
801d606: 2800 cmp r0, #0
|
|
801d608: d1ed bne.n 801d5e6 <__gethex+0x26a>
|
|
801d60a: 9801 ldr r0, [sp, #4]
|
|
801d60c: 4621 mov r1, r4
|
|
801d60e: f7fd ff0d bl 801b42c <_Bfree>
|
|
801d612: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
801d614: 2300 movs r3, #0
|
|
801d616: 6013 str r3, [r2, #0]
|
|
801d618: 2550 movs r5, #80 @ 0x50
|
|
801d61a: e72b b.n 801d474 <__gethex+0xf8>
|
|
801d61c: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801d61e: 2b00 cmp r3, #0
|
|
801d620: d1f3 bne.n 801d60a <__gethex+0x28e>
|
|
801d622: e7e0 b.n 801d5e6 <__gethex+0x26a>
|
|
801d624: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801d626: 2b00 cmp r3, #0
|
|
801d628: d1dd bne.n 801d5e6 <__gethex+0x26a>
|
|
801d62a: e7ee b.n 801d60a <__gethex+0x28e>
|
|
801d62c: 0801e72f .word 0x0801e72f
|
|
801d630: 0801e6c5 .word 0x0801e6c5
|
|
801d634: 0801e786 .word 0x0801e786
|
|
801d638: 1e6f subs r7, r5, #1
|
|
801d63a: f1b9 0f00 cmp.w r9, #0
|
|
801d63e: d130 bne.n 801d6a2 <__gethex+0x326>
|
|
801d640: b127 cbz r7, 801d64c <__gethex+0x2d0>
|
|
801d642: 4639 mov r1, r7
|
|
801d644: 4620 mov r0, r4
|
|
801d646: f7fe fb4a bl 801bcde <__any_on>
|
|
801d64a: 4681 mov r9, r0
|
|
801d64c: 117a asrs r2, r7, #5
|
|
801d64e: 2301 movs r3, #1
|
|
801d650: f85a 2022 ldr.w r2, [sl, r2, lsl #2]
|
|
801d654: f007 071f and.w r7, r7, #31
|
|
801d658: 40bb lsls r3, r7
|
|
801d65a: 4213 tst r3, r2
|
|
801d65c: 4629 mov r1, r5
|
|
801d65e: 4620 mov r0, r4
|
|
801d660: bf18 it ne
|
|
801d662: f049 0902 orrne.w r9, r9, #2
|
|
801d666: f7ff fe21 bl 801d2ac <rshift>
|
|
801d66a: f8d8 7004 ldr.w r7, [r8, #4]
|
|
801d66e: 1b76 subs r6, r6, r5
|
|
801d670: 2502 movs r5, #2
|
|
801d672: f1b9 0f00 cmp.w r9, #0
|
|
801d676: d047 beq.n 801d708 <__gethex+0x38c>
|
|
801d678: f8d8 300c ldr.w r3, [r8, #12]
|
|
801d67c: 2b02 cmp r3, #2
|
|
801d67e: d015 beq.n 801d6ac <__gethex+0x330>
|
|
801d680: 2b03 cmp r3, #3
|
|
801d682: d017 beq.n 801d6b4 <__gethex+0x338>
|
|
801d684: 2b01 cmp r3, #1
|
|
801d686: d109 bne.n 801d69c <__gethex+0x320>
|
|
801d688: f019 0f02 tst.w r9, #2
|
|
801d68c: d006 beq.n 801d69c <__gethex+0x320>
|
|
801d68e: f8da 3000 ldr.w r3, [sl]
|
|
801d692: ea49 0903 orr.w r9, r9, r3
|
|
801d696: f019 0f01 tst.w r9, #1
|
|
801d69a: d10e bne.n 801d6ba <__gethex+0x33e>
|
|
801d69c: f045 0510 orr.w r5, r5, #16
|
|
801d6a0: e032 b.n 801d708 <__gethex+0x38c>
|
|
801d6a2: f04f 0901 mov.w r9, #1
|
|
801d6a6: e7d1 b.n 801d64c <__gethex+0x2d0>
|
|
801d6a8: 2501 movs r5, #1
|
|
801d6aa: e7e2 b.n 801d672 <__gethex+0x2f6>
|
|
801d6ac: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801d6ae: f1c3 0301 rsb r3, r3, #1
|
|
801d6b2: 930f str r3, [sp, #60] @ 0x3c
|
|
801d6b4: 9b0f ldr r3, [sp, #60] @ 0x3c
|
|
801d6b6: 2b00 cmp r3, #0
|
|
801d6b8: d0f0 beq.n 801d69c <__gethex+0x320>
|
|
801d6ba: f8d4 b010 ldr.w fp, [r4, #16]
|
|
801d6be: f104 0314 add.w r3, r4, #20
|
|
801d6c2: ea4f 0a8b mov.w sl, fp, lsl #2
|
|
801d6c6: eb03 018b add.w r1, r3, fp, lsl #2
|
|
801d6ca: f04f 0c00 mov.w ip, #0
|
|
801d6ce: 4618 mov r0, r3
|
|
801d6d0: f853 2b04 ldr.w r2, [r3], #4
|
|
801d6d4: f1b2 3fff cmp.w r2, #4294967295 @ 0xffffffff
|
|
801d6d8: d01b beq.n 801d712 <__gethex+0x396>
|
|
801d6da: 3201 adds r2, #1
|
|
801d6dc: 6002 str r2, [r0, #0]
|
|
801d6de: 2d02 cmp r5, #2
|
|
801d6e0: f104 0314 add.w r3, r4, #20
|
|
801d6e4: d13c bne.n 801d760 <__gethex+0x3e4>
|
|
801d6e6: f8d8 2000 ldr.w r2, [r8]
|
|
801d6ea: 3a01 subs r2, #1
|
|
801d6ec: 42b2 cmp r2, r6
|
|
801d6ee: d109 bne.n 801d704 <__gethex+0x388>
|
|
801d6f0: 1171 asrs r1, r6, #5
|
|
801d6f2: 2201 movs r2, #1
|
|
801d6f4: f853 3021 ldr.w r3, [r3, r1, lsl #2]
|
|
801d6f8: f006 061f and.w r6, r6, #31
|
|
801d6fc: fa02 f606 lsl.w r6, r2, r6
|
|
801d700: 421e tst r6, r3
|
|
801d702: d13a bne.n 801d77a <__gethex+0x3fe>
|
|
801d704: f045 0520 orr.w r5, r5, #32
|
|
801d708: 9b0e ldr r3, [sp, #56] @ 0x38
|
|
801d70a: 601c str r4, [r3, #0]
|
|
801d70c: 9b02 ldr r3, [sp, #8]
|
|
801d70e: 601f str r7, [r3, #0]
|
|
801d710: e6b0 b.n 801d474 <__gethex+0xf8>
|
|
801d712: 4299 cmp r1, r3
|
|
801d714: f843 cc04 str.w ip, [r3, #-4]
|
|
801d718: d8d9 bhi.n 801d6ce <__gethex+0x352>
|
|
801d71a: 68a3 ldr r3, [r4, #8]
|
|
801d71c: 459b cmp fp, r3
|
|
801d71e: db17 blt.n 801d750 <__gethex+0x3d4>
|
|
801d720: 6861 ldr r1, [r4, #4]
|
|
801d722: 9801 ldr r0, [sp, #4]
|
|
801d724: 3101 adds r1, #1
|
|
801d726: f7fd fe43 bl 801b3b0 <_Balloc>
|
|
801d72a: 4681 mov r9, r0
|
|
801d72c: b918 cbnz r0, 801d736 <__gethex+0x3ba>
|
|
801d72e: 4b1a ldr r3, [pc, #104] @ (801d798 <__gethex+0x41c>)
|
|
801d730: 4602 mov r2, r0
|
|
801d732: 2184 movs r1, #132 @ 0x84
|
|
801d734: e6c5 b.n 801d4c2 <__gethex+0x146>
|
|
801d736: 6922 ldr r2, [r4, #16]
|
|
801d738: 3202 adds r2, #2
|
|
801d73a: f104 010c add.w r1, r4, #12
|
|
801d73e: 0092 lsls r2, r2, #2
|
|
801d740: 300c adds r0, #12
|
|
801d742: f7fc febc bl 801a4be <memcpy>
|
|
801d746: 4621 mov r1, r4
|
|
801d748: 9801 ldr r0, [sp, #4]
|
|
801d74a: f7fd fe6f bl 801b42c <_Bfree>
|
|
801d74e: 464c mov r4, r9
|
|
801d750: 6923 ldr r3, [r4, #16]
|
|
801d752: 1c5a adds r2, r3, #1
|
|
801d754: eb04 0383 add.w r3, r4, r3, lsl #2
|
|
801d758: 6122 str r2, [r4, #16]
|
|
801d75a: 2201 movs r2, #1
|
|
801d75c: 615a str r2, [r3, #20]
|
|
801d75e: e7be b.n 801d6de <__gethex+0x362>
|
|
801d760: 6922 ldr r2, [r4, #16]
|
|
801d762: 455a cmp r2, fp
|
|
801d764: dd0b ble.n 801d77e <__gethex+0x402>
|
|
801d766: 2101 movs r1, #1
|
|
801d768: 4620 mov r0, r4
|
|
801d76a: f7ff fd9f bl 801d2ac <rshift>
|
|
801d76e: f8d8 3008 ldr.w r3, [r8, #8]
|
|
801d772: 3701 adds r7, #1
|
|
801d774: 42bb cmp r3, r7
|
|
801d776: f6ff aee0 blt.w 801d53a <__gethex+0x1be>
|
|
801d77a: 2501 movs r5, #1
|
|
801d77c: e7c2 b.n 801d704 <__gethex+0x388>
|
|
801d77e: f016 061f ands.w r6, r6, #31
|
|
801d782: d0fa beq.n 801d77a <__gethex+0x3fe>
|
|
801d784: 4453 add r3, sl
|
|
801d786: f1c6 0620 rsb r6, r6, #32
|
|
801d78a: f853 0c04 ldr.w r0, [r3, #-4]
|
|
801d78e: f7fd feff bl 801b590 <__hi0bits>
|
|
801d792: 42b0 cmp r0, r6
|
|
801d794: dbe7 blt.n 801d766 <__gethex+0x3ea>
|
|
801d796: e7f0 b.n 801d77a <__gethex+0x3fe>
|
|
801d798: 0801e6c5 .word 0x0801e6c5
|
|
|
|
0801d79c <L_shift>:
|
|
801d79c: f1c2 0208 rsb r2, r2, #8
|
|
801d7a0: 0092 lsls r2, r2, #2
|
|
801d7a2: b570 push {r4, r5, r6, lr}
|
|
801d7a4: f1c2 0620 rsb r6, r2, #32
|
|
801d7a8: 6843 ldr r3, [r0, #4]
|
|
801d7aa: 6804 ldr r4, [r0, #0]
|
|
801d7ac: fa03 f506 lsl.w r5, r3, r6
|
|
801d7b0: 432c orrs r4, r5
|
|
801d7b2: 40d3 lsrs r3, r2
|
|
801d7b4: 6004 str r4, [r0, #0]
|
|
801d7b6: f840 3f04 str.w r3, [r0, #4]!
|
|
801d7ba: 4288 cmp r0, r1
|
|
801d7bc: d3f4 bcc.n 801d7a8 <L_shift+0xc>
|
|
801d7be: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0801d7c0 <__match>:
|
|
801d7c0: b530 push {r4, r5, lr}
|
|
801d7c2: 6803 ldr r3, [r0, #0]
|
|
801d7c4: 3301 adds r3, #1
|
|
801d7c6: f811 4b01 ldrb.w r4, [r1], #1
|
|
801d7ca: b914 cbnz r4, 801d7d2 <__match+0x12>
|
|
801d7cc: 6003 str r3, [r0, #0]
|
|
801d7ce: 2001 movs r0, #1
|
|
801d7d0: bd30 pop {r4, r5, pc}
|
|
801d7d2: f813 2b01 ldrb.w r2, [r3], #1
|
|
801d7d6: f1a2 0541 sub.w r5, r2, #65 @ 0x41
|
|
801d7da: 2d19 cmp r5, #25
|
|
801d7dc: bf98 it ls
|
|
801d7de: 3220 addls r2, #32
|
|
801d7e0: 42a2 cmp r2, r4
|
|
801d7e2: d0f0 beq.n 801d7c6 <__match+0x6>
|
|
801d7e4: 2000 movs r0, #0
|
|
801d7e6: e7f3 b.n 801d7d0 <__match+0x10>
|
|
|
|
0801d7e8 <__hexnan>:
|
|
801d7e8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801d7ec: 680b ldr r3, [r1, #0]
|
|
801d7ee: 6801 ldr r1, [r0, #0]
|
|
801d7f0: 115e asrs r6, r3, #5
|
|
801d7f2: eb02 0686 add.w r6, r2, r6, lsl #2
|
|
801d7f6: f013 031f ands.w r3, r3, #31
|
|
801d7fa: b087 sub sp, #28
|
|
801d7fc: bf18 it ne
|
|
801d7fe: 3604 addne r6, #4
|
|
801d800: 2500 movs r5, #0
|
|
801d802: 1f37 subs r7, r6, #4
|
|
801d804: 4682 mov sl, r0
|
|
801d806: 4690 mov r8, r2
|
|
801d808: 9301 str r3, [sp, #4]
|
|
801d80a: f846 5c04 str.w r5, [r6, #-4]
|
|
801d80e: 46b9 mov r9, r7
|
|
801d810: 463c mov r4, r7
|
|
801d812: 9502 str r5, [sp, #8]
|
|
801d814: 46ab mov fp, r5
|
|
801d816: 784a ldrb r2, [r1, #1]
|
|
801d818: 1c4b adds r3, r1, #1
|
|
801d81a: 9303 str r3, [sp, #12]
|
|
801d81c: b342 cbz r2, 801d870 <__hexnan+0x88>
|
|
801d81e: 4610 mov r0, r2
|
|
801d820: 9105 str r1, [sp, #20]
|
|
801d822: 9204 str r2, [sp, #16]
|
|
801d824: f7ff fd94 bl 801d350 <__hexdig_fun>
|
|
801d828: 2800 cmp r0, #0
|
|
801d82a: d153 bne.n 801d8d4 <__hexnan+0xec>
|
|
801d82c: 9a04 ldr r2, [sp, #16]
|
|
801d82e: 9905 ldr r1, [sp, #20]
|
|
801d830: 2a20 cmp r2, #32
|
|
801d832: d818 bhi.n 801d866 <__hexnan+0x7e>
|
|
801d834: 9b02 ldr r3, [sp, #8]
|
|
801d836: 459b cmp fp, r3
|
|
801d838: dd13 ble.n 801d862 <__hexnan+0x7a>
|
|
801d83a: 454c cmp r4, r9
|
|
801d83c: d206 bcs.n 801d84c <__hexnan+0x64>
|
|
801d83e: 2d07 cmp r5, #7
|
|
801d840: dc04 bgt.n 801d84c <__hexnan+0x64>
|
|
801d842: 462a mov r2, r5
|
|
801d844: 4649 mov r1, r9
|
|
801d846: 4620 mov r0, r4
|
|
801d848: f7ff ffa8 bl 801d79c <L_shift>
|
|
801d84c: 4544 cmp r4, r8
|
|
801d84e: d954 bls.n 801d8fa <__hexnan+0x112>
|
|
801d850: 2300 movs r3, #0
|
|
801d852: f1a4 0904 sub.w r9, r4, #4
|
|
801d856: f844 3c04 str.w r3, [r4, #-4]
|
|
801d85a: f8cd b008 str.w fp, [sp, #8]
|
|
801d85e: 464c mov r4, r9
|
|
801d860: 461d mov r5, r3
|
|
801d862: 9903 ldr r1, [sp, #12]
|
|
801d864: e7d7 b.n 801d816 <__hexnan+0x2e>
|
|
801d866: 2a29 cmp r2, #41 @ 0x29
|
|
801d868: d159 bne.n 801d91e <__hexnan+0x136>
|
|
801d86a: 3102 adds r1, #2
|
|
801d86c: f8ca 1000 str.w r1, [sl]
|
|
801d870: f1bb 0f00 cmp.w fp, #0
|
|
801d874: d053 beq.n 801d91e <__hexnan+0x136>
|
|
801d876: 454c cmp r4, r9
|
|
801d878: d206 bcs.n 801d888 <__hexnan+0xa0>
|
|
801d87a: 2d07 cmp r5, #7
|
|
801d87c: dc04 bgt.n 801d888 <__hexnan+0xa0>
|
|
801d87e: 462a mov r2, r5
|
|
801d880: 4649 mov r1, r9
|
|
801d882: 4620 mov r0, r4
|
|
801d884: f7ff ff8a bl 801d79c <L_shift>
|
|
801d888: 4544 cmp r4, r8
|
|
801d88a: d938 bls.n 801d8fe <__hexnan+0x116>
|
|
801d88c: f1a8 0204 sub.w r2, r8, #4
|
|
801d890: 4623 mov r3, r4
|
|
801d892: f853 1b04 ldr.w r1, [r3], #4
|
|
801d896: f842 1f04 str.w r1, [r2, #4]!
|
|
801d89a: 429f cmp r7, r3
|
|
801d89c: d2f9 bcs.n 801d892 <__hexnan+0xaa>
|
|
801d89e: 1b3b subs r3, r7, r4
|
|
801d8a0: f023 0303 bic.w r3, r3, #3
|
|
801d8a4: 3401 adds r4, #1
|
|
801d8a6: 3e03 subs r6, #3
|
|
801d8a8: 42b4 cmp r4, r6
|
|
801d8aa: bf88 it hi
|
|
801d8ac: 2300 movhi r3, #0
|
|
801d8ae: f108 0204 add.w r2, r8, #4
|
|
801d8b2: 4413 add r3, r2
|
|
801d8b4: 2100 movs r1, #0
|
|
801d8b6: 461a mov r2, r3
|
|
801d8b8: 3304 adds r3, #4
|
|
801d8ba: 429f cmp r7, r3
|
|
801d8bc: 6011 str r1, [r2, #0]
|
|
801d8be: d2fa bcs.n 801d8b6 <__hexnan+0xce>
|
|
801d8c0: 683b ldr r3, [r7, #0]
|
|
801d8c2: b91b cbnz r3, 801d8cc <__hexnan+0xe4>
|
|
801d8c4: 4547 cmp r7, r8
|
|
801d8c6: d128 bne.n 801d91a <__hexnan+0x132>
|
|
801d8c8: 2301 movs r3, #1
|
|
801d8ca: 603b str r3, [r7, #0]
|
|
801d8cc: 2005 movs r0, #5
|
|
801d8ce: b007 add sp, #28
|
|
801d8d0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801d8d4: 3501 adds r5, #1
|
|
801d8d6: 2d08 cmp r5, #8
|
|
801d8d8: f10b 0b01 add.w fp, fp, #1
|
|
801d8dc: dd06 ble.n 801d8ec <__hexnan+0x104>
|
|
801d8de: 4544 cmp r4, r8
|
|
801d8e0: d9bf bls.n 801d862 <__hexnan+0x7a>
|
|
801d8e2: 2300 movs r3, #0
|
|
801d8e4: f844 3c04 str.w r3, [r4, #-4]
|
|
801d8e8: 2501 movs r5, #1
|
|
801d8ea: 3c04 subs r4, #4
|
|
801d8ec: 6822 ldr r2, [r4, #0]
|
|
801d8ee: f000 000f and.w r0, r0, #15
|
|
801d8f2: ea40 1002 orr.w r0, r0, r2, lsl #4
|
|
801d8f6: 6020 str r0, [r4, #0]
|
|
801d8f8: e7b3 b.n 801d862 <__hexnan+0x7a>
|
|
801d8fa: 2508 movs r5, #8
|
|
801d8fc: e7b1 b.n 801d862 <__hexnan+0x7a>
|
|
801d8fe: 9b01 ldr r3, [sp, #4]
|
|
801d900: 2b00 cmp r3, #0
|
|
801d902: d0dd beq.n 801d8c0 <__hexnan+0xd8>
|
|
801d904: f1c3 0320 rsb r3, r3, #32
|
|
801d908: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
801d90c: 40da lsrs r2, r3
|
|
801d90e: f856 3c04 ldr.w r3, [r6, #-4]
|
|
801d912: 4013 ands r3, r2
|
|
801d914: f846 3c04 str.w r3, [r6, #-4]
|
|
801d918: e7d2 b.n 801d8c0 <__hexnan+0xd8>
|
|
801d91a: 3f04 subs r7, #4
|
|
801d91c: e7d0 b.n 801d8c0 <__hexnan+0xd8>
|
|
801d91e: 2004 movs r0, #4
|
|
801d920: e7d5 b.n 801d8ce <__hexnan+0xe6>
|
|
|
|
0801d922 <__ascii_mbtowc>:
|
|
801d922: b082 sub sp, #8
|
|
801d924: b901 cbnz r1, 801d928 <__ascii_mbtowc+0x6>
|
|
801d926: a901 add r1, sp, #4
|
|
801d928: b142 cbz r2, 801d93c <__ascii_mbtowc+0x1a>
|
|
801d92a: b14b cbz r3, 801d940 <__ascii_mbtowc+0x1e>
|
|
801d92c: 7813 ldrb r3, [r2, #0]
|
|
801d92e: 600b str r3, [r1, #0]
|
|
801d930: 7812 ldrb r2, [r2, #0]
|
|
801d932: 1e10 subs r0, r2, #0
|
|
801d934: bf18 it ne
|
|
801d936: 2001 movne r0, #1
|
|
801d938: b002 add sp, #8
|
|
801d93a: 4770 bx lr
|
|
801d93c: 4610 mov r0, r2
|
|
801d93e: e7fb b.n 801d938 <__ascii_mbtowc+0x16>
|
|
801d940: f06f 0001 mvn.w r0, #1
|
|
801d944: e7f8 b.n 801d938 <__ascii_mbtowc+0x16>
|
|
|
|
0801d946 <_realloc_r>:
|
|
801d946: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
801d94a: 4607 mov r7, r0
|
|
801d94c: 4614 mov r4, r2
|
|
801d94e: 460d mov r5, r1
|
|
801d950: b921 cbnz r1, 801d95c <_realloc_r+0x16>
|
|
801d952: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
801d956: 4611 mov r1, r2
|
|
801d958: f7fd bc9e b.w 801b298 <_malloc_r>
|
|
801d95c: b92a cbnz r2, 801d96a <_realloc_r+0x24>
|
|
801d95e: f7fd fc27 bl 801b1b0 <_free_r>
|
|
801d962: 4625 mov r5, r4
|
|
801d964: 4628 mov r0, r5
|
|
801d966: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
801d96a: f000 f8c0 bl 801daee <_malloc_usable_size_r>
|
|
801d96e: 4284 cmp r4, r0
|
|
801d970: 4606 mov r6, r0
|
|
801d972: d802 bhi.n 801d97a <_realloc_r+0x34>
|
|
801d974: ebb4 0f50 cmp.w r4, r0, lsr #1
|
|
801d978: d8f4 bhi.n 801d964 <_realloc_r+0x1e>
|
|
801d97a: 4621 mov r1, r4
|
|
801d97c: 4638 mov r0, r7
|
|
801d97e: f7fd fc8b bl 801b298 <_malloc_r>
|
|
801d982: 4680 mov r8, r0
|
|
801d984: b908 cbnz r0, 801d98a <_realloc_r+0x44>
|
|
801d986: 4645 mov r5, r8
|
|
801d988: e7ec b.n 801d964 <_realloc_r+0x1e>
|
|
801d98a: 42b4 cmp r4, r6
|
|
801d98c: 4622 mov r2, r4
|
|
801d98e: 4629 mov r1, r5
|
|
801d990: bf28 it cs
|
|
801d992: 4632 movcs r2, r6
|
|
801d994: f7fc fd93 bl 801a4be <memcpy>
|
|
801d998: 4629 mov r1, r5
|
|
801d99a: 4638 mov r0, r7
|
|
801d99c: f7fd fc08 bl 801b1b0 <_free_r>
|
|
801d9a0: e7f1 b.n 801d986 <_realloc_r+0x40>
|
|
|
|
0801d9a2 <__ascii_wctomb>:
|
|
801d9a2: 4603 mov r3, r0
|
|
801d9a4: 4608 mov r0, r1
|
|
801d9a6: b141 cbz r1, 801d9ba <__ascii_wctomb+0x18>
|
|
801d9a8: 2aff cmp r2, #255 @ 0xff
|
|
801d9aa: d904 bls.n 801d9b6 <__ascii_wctomb+0x14>
|
|
801d9ac: 228a movs r2, #138 @ 0x8a
|
|
801d9ae: 601a str r2, [r3, #0]
|
|
801d9b0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801d9b4: 4770 bx lr
|
|
801d9b6: 700a strb r2, [r1, #0]
|
|
801d9b8: 2001 movs r0, #1
|
|
801d9ba: 4770 bx lr
|
|
|
|
0801d9bc <fiprintf>:
|
|
801d9bc: b40e push {r1, r2, r3}
|
|
801d9be: b503 push {r0, r1, lr}
|
|
801d9c0: 4601 mov r1, r0
|
|
801d9c2: ab03 add r3, sp, #12
|
|
801d9c4: 4805 ldr r0, [pc, #20] @ (801d9dc <fiprintf+0x20>)
|
|
801d9c6: f853 2b04 ldr.w r2, [r3], #4
|
|
801d9ca: 6800 ldr r0, [r0, #0]
|
|
801d9cc: 9301 str r3, [sp, #4]
|
|
801d9ce: f7ff f9a7 bl 801cd20 <_vfiprintf_r>
|
|
801d9d2: b002 add sp, #8
|
|
801d9d4: f85d eb04 ldr.w lr, [sp], #4
|
|
801d9d8: b003 add sp, #12
|
|
801d9da: 4770 bx lr
|
|
801d9dc: 2000011c .word 0x2000011c
|
|
|
|
0801d9e0 <__swhatbuf_r>:
|
|
801d9e0: b570 push {r4, r5, r6, lr}
|
|
801d9e2: 460c mov r4, r1
|
|
801d9e4: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801d9e8: 2900 cmp r1, #0
|
|
801d9ea: b096 sub sp, #88 @ 0x58
|
|
801d9ec: 4615 mov r5, r2
|
|
801d9ee: 461e mov r6, r3
|
|
801d9f0: da0a bge.n 801da08 <__swhatbuf_r+0x28>
|
|
801d9f2: 89a1 ldrh r1, [r4, #12]
|
|
801d9f4: f011 0180 ands.w r1, r1, #128 @ 0x80
|
|
801d9f8: d113 bne.n 801da22 <__swhatbuf_r+0x42>
|
|
801d9fa: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
801d9fe: 2000 movs r0, #0
|
|
801da00: 6031 str r1, [r6, #0]
|
|
801da02: 602a str r2, [r5, #0]
|
|
801da04: b016 add sp, #88 @ 0x58
|
|
801da06: bd70 pop {r4, r5, r6, pc}
|
|
801da08: 466a mov r2, sp
|
|
801da0a: f000 f847 bl 801da9c <_fstat_r>
|
|
801da0e: 2800 cmp r0, #0
|
|
801da10: dbef blt.n 801d9f2 <__swhatbuf_r+0x12>
|
|
801da12: 9901 ldr r1, [sp, #4]
|
|
801da14: f401 4170 and.w r1, r1, #61440 @ 0xf000
|
|
801da18: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
|
|
801da1c: 4259 negs r1, r3
|
|
801da1e: 4159 adcs r1, r3
|
|
801da20: e7eb b.n 801d9fa <__swhatbuf_r+0x1a>
|
|
801da22: 2100 movs r1, #0
|
|
801da24: 2240 movs r2, #64 @ 0x40
|
|
801da26: e7ea b.n 801d9fe <__swhatbuf_r+0x1e>
|
|
|
|
0801da28 <__smakebuf_r>:
|
|
801da28: 898b ldrh r3, [r1, #12]
|
|
801da2a: b573 push {r0, r1, r4, r5, r6, lr}
|
|
801da2c: 079e lsls r6, r3, #30
|
|
801da2e: 4605 mov r5, r0
|
|
801da30: 460c mov r4, r1
|
|
801da32: d507 bpl.n 801da44 <__smakebuf_r+0x1c>
|
|
801da34: f104 0347 add.w r3, r4, #71 @ 0x47
|
|
801da38: 6023 str r3, [r4, #0]
|
|
801da3a: 6123 str r3, [r4, #16]
|
|
801da3c: 2301 movs r3, #1
|
|
801da3e: 6163 str r3, [r4, #20]
|
|
801da40: b002 add sp, #8
|
|
801da42: bd70 pop {r4, r5, r6, pc}
|
|
801da44: ab01 add r3, sp, #4
|
|
801da46: 466a mov r2, sp
|
|
801da48: f7ff ffca bl 801d9e0 <__swhatbuf_r>
|
|
801da4c: 9e00 ldr r6, [sp, #0]
|
|
801da4e: 4628 mov r0, r5
|
|
801da50: 4631 mov r1, r6
|
|
801da52: f7fd fc21 bl 801b298 <_malloc_r>
|
|
801da56: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801da5a: b938 cbnz r0, 801da6c <__smakebuf_r+0x44>
|
|
801da5c: 059a lsls r2, r3, #22
|
|
801da5e: d4ef bmi.n 801da40 <__smakebuf_r+0x18>
|
|
801da60: f023 0303 bic.w r3, r3, #3
|
|
801da64: f043 0302 orr.w r3, r3, #2
|
|
801da68: 81a3 strh r3, [r4, #12]
|
|
801da6a: e7e3 b.n 801da34 <__smakebuf_r+0xc>
|
|
801da6c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
801da70: 81a3 strh r3, [r4, #12]
|
|
801da72: 9b01 ldr r3, [sp, #4]
|
|
801da74: 6020 str r0, [r4, #0]
|
|
801da76: e9c4 0604 strd r0, r6, [r4, #16]
|
|
801da7a: 2b00 cmp r3, #0
|
|
801da7c: d0e0 beq.n 801da40 <__smakebuf_r+0x18>
|
|
801da7e: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
801da82: 4628 mov r0, r5
|
|
801da84: f000 f81c bl 801dac0 <_isatty_r>
|
|
801da88: 2800 cmp r0, #0
|
|
801da8a: d0d9 beq.n 801da40 <__smakebuf_r+0x18>
|
|
801da8c: 89a3 ldrh r3, [r4, #12]
|
|
801da8e: f023 0303 bic.w r3, r3, #3
|
|
801da92: f043 0301 orr.w r3, r3, #1
|
|
801da96: 81a3 strh r3, [r4, #12]
|
|
801da98: e7d2 b.n 801da40 <__smakebuf_r+0x18>
|
|
...
|
|
|
|
0801da9c <_fstat_r>:
|
|
801da9c: b538 push {r3, r4, r5, lr}
|
|
801da9e: 4d07 ldr r5, [pc, #28] @ (801dabc <_fstat_r+0x20>)
|
|
801daa0: 2300 movs r3, #0
|
|
801daa2: 4604 mov r4, r0
|
|
801daa4: 4608 mov r0, r1
|
|
801daa6: 4611 mov r1, r2
|
|
801daa8: 602b str r3, [r5, #0]
|
|
801daaa: f7e8 fe41 bl 8006730 <_fstat>
|
|
801daae: 1c43 adds r3, r0, #1
|
|
801dab0: d102 bne.n 801dab8 <_fstat_r+0x1c>
|
|
801dab2: 682b ldr r3, [r5, #0]
|
|
801dab4: b103 cbz r3, 801dab8 <_fstat_r+0x1c>
|
|
801dab6: 6023 str r3, [r4, #0]
|
|
801dab8: bd38 pop {r3, r4, r5, pc}
|
|
801daba: bf00 nop
|
|
801dabc: 20013cd8 .word 0x20013cd8
|
|
|
|
0801dac0 <_isatty_r>:
|
|
801dac0: b538 push {r3, r4, r5, lr}
|
|
801dac2: 4d06 ldr r5, [pc, #24] @ (801dadc <_isatty_r+0x1c>)
|
|
801dac4: 2300 movs r3, #0
|
|
801dac6: 4604 mov r4, r0
|
|
801dac8: 4608 mov r0, r1
|
|
801daca: 602b str r3, [r5, #0]
|
|
801dacc: f7e8 fe40 bl 8006750 <_isatty>
|
|
801dad0: 1c43 adds r3, r0, #1
|
|
801dad2: d102 bne.n 801dada <_isatty_r+0x1a>
|
|
801dad4: 682b ldr r3, [r5, #0]
|
|
801dad6: b103 cbz r3, 801dada <_isatty_r+0x1a>
|
|
801dad8: 6023 str r3, [r4, #0]
|
|
801dada: bd38 pop {r3, r4, r5, pc}
|
|
801dadc: 20013cd8 .word 0x20013cd8
|
|
|
|
0801dae0 <abort>:
|
|
801dae0: b508 push {r3, lr}
|
|
801dae2: 2006 movs r0, #6
|
|
801dae4: f000 f834 bl 801db50 <raise>
|
|
801dae8: 2001 movs r0, #1
|
|
801daea: f7e8 fded bl 80066c8 <_exit>
|
|
|
|
0801daee <_malloc_usable_size_r>:
|
|
801daee: f851 3c04 ldr.w r3, [r1, #-4]
|
|
801daf2: 1f18 subs r0, r3, #4
|
|
801daf4: 2b00 cmp r3, #0
|
|
801daf6: bfbc itt lt
|
|
801daf8: 580b ldrlt r3, [r1, r0]
|
|
801dafa: 18c0 addlt r0, r0, r3
|
|
801dafc: 4770 bx lr
|
|
|
|
0801dafe <_raise_r>:
|
|
801dafe: 291f cmp r1, #31
|
|
801db00: b538 push {r3, r4, r5, lr}
|
|
801db02: 4605 mov r5, r0
|
|
801db04: 460c mov r4, r1
|
|
801db06: d904 bls.n 801db12 <_raise_r+0x14>
|
|
801db08: 2316 movs r3, #22
|
|
801db0a: 6003 str r3, [r0, #0]
|
|
801db0c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801db10: bd38 pop {r3, r4, r5, pc}
|
|
801db12: 6bc2 ldr r2, [r0, #60] @ 0x3c
|
|
801db14: b112 cbz r2, 801db1c <_raise_r+0x1e>
|
|
801db16: f852 3021 ldr.w r3, [r2, r1, lsl #2]
|
|
801db1a: b94b cbnz r3, 801db30 <_raise_r+0x32>
|
|
801db1c: 4628 mov r0, r5
|
|
801db1e: f000 f831 bl 801db84 <_getpid_r>
|
|
801db22: 4622 mov r2, r4
|
|
801db24: 4601 mov r1, r0
|
|
801db26: 4628 mov r0, r5
|
|
801db28: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
801db2c: f000 b818 b.w 801db60 <_kill_r>
|
|
801db30: 2b01 cmp r3, #1
|
|
801db32: d00a beq.n 801db4a <_raise_r+0x4c>
|
|
801db34: 1c59 adds r1, r3, #1
|
|
801db36: d103 bne.n 801db40 <_raise_r+0x42>
|
|
801db38: 2316 movs r3, #22
|
|
801db3a: 6003 str r3, [r0, #0]
|
|
801db3c: 2001 movs r0, #1
|
|
801db3e: e7e7 b.n 801db10 <_raise_r+0x12>
|
|
801db40: 2100 movs r1, #0
|
|
801db42: f842 1024 str.w r1, [r2, r4, lsl #2]
|
|
801db46: 4620 mov r0, r4
|
|
801db48: 4798 blx r3
|
|
801db4a: 2000 movs r0, #0
|
|
801db4c: e7e0 b.n 801db10 <_raise_r+0x12>
|
|
...
|
|
|
|
0801db50 <raise>:
|
|
801db50: 4b02 ldr r3, [pc, #8] @ (801db5c <raise+0xc>)
|
|
801db52: 4601 mov r1, r0
|
|
801db54: 6818 ldr r0, [r3, #0]
|
|
801db56: f7ff bfd2 b.w 801dafe <_raise_r>
|
|
801db5a: bf00 nop
|
|
801db5c: 2000011c .word 0x2000011c
|
|
|
|
0801db60 <_kill_r>:
|
|
801db60: b538 push {r3, r4, r5, lr}
|
|
801db62: 4d07 ldr r5, [pc, #28] @ (801db80 <_kill_r+0x20>)
|
|
801db64: 2300 movs r3, #0
|
|
801db66: 4604 mov r4, r0
|
|
801db68: 4608 mov r0, r1
|
|
801db6a: 4611 mov r1, r2
|
|
801db6c: 602b str r3, [r5, #0]
|
|
801db6e: f7e8 fd9b bl 80066a8 <_kill>
|
|
801db72: 1c43 adds r3, r0, #1
|
|
801db74: d102 bne.n 801db7c <_kill_r+0x1c>
|
|
801db76: 682b ldr r3, [r5, #0]
|
|
801db78: b103 cbz r3, 801db7c <_kill_r+0x1c>
|
|
801db7a: 6023 str r3, [r4, #0]
|
|
801db7c: bd38 pop {r3, r4, r5, pc}
|
|
801db7e: bf00 nop
|
|
801db80: 20013cd8 .word 0x20013cd8
|
|
|
|
0801db84 <_getpid_r>:
|
|
801db84: f7e8 bd88 b.w 8006698 <_getpid>
|
|
|
|
0801db88 <sqrt>:
|
|
801db88: b538 push {r3, r4, r5, lr}
|
|
801db8a: ed2d 8b02 vpush {d8}
|
|
801db8e: ec55 4b10 vmov r4, r5, d0
|
|
801db92: f000 f82d bl 801dbf0 <__ieee754_sqrt>
|
|
801db96: 4622 mov r2, r4
|
|
801db98: 462b mov r3, r5
|
|
801db9a: 4620 mov r0, r4
|
|
801db9c: 4629 mov r1, r5
|
|
801db9e: eeb0 8a40 vmov.f32 s16, s0
|
|
801dba2: eef0 8a60 vmov.f32 s17, s1
|
|
801dba6: f7e2 ff99 bl 8000adc <__aeabi_dcmpun>
|
|
801dbaa: b930 cbnz r0, 801dbba <sqrt+0x32>
|
|
801dbac: 2200 movs r2, #0
|
|
801dbae: 2300 movs r3, #0
|
|
801dbb0: 4620 mov r0, r4
|
|
801dbb2: 4629 mov r1, r5
|
|
801dbb4: f7e2 ff6a bl 8000a8c <__aeabi_dcmplt>
|
|
801dbb8: b930 cbnz r0, 801dbc8 <sqrt+0x40>
|
|
801dbba: eeb0 0a48 vmov.f32 s0, s16
|
|
801dbbe: eef0 0a68 vmov.f32 s1, s17
|
|
801dbc2: ecbd 8b02 vpop {d8}
|
|
801dbc6: bd38 pop {r3, r4, r5, pc}
|
|
801dbc8: f7fc fc4c bl 801a464 <__errno>
|
|
801dbcc: 2200 movs r2, #0
|
|
801dbce: 2300 movs r3, #0
|
|
801dbd0: 2121 movs r1, #33 @ 0x21
|
|
801dbd2: 6001 str r1, [r0, #0]
|
|
801dbd4: 4610 mov r0, r2
|
|
801dbd6: 4619 mov r1, r3
|
|
801dbd8: f7e2 fe10 bl 80007fc <__aeabi_ddiv>
|
|
801dbdc: ec41 0b18 vmov d8, r0, r1
|
|
801dbe0: eeb0 0a48 vmov.f32 s0, s16
|
|
801dbe4: eef0 0a68 vmov.f32 s1, s17
|
|
801dbe8: ecbd 8b02 vpop {d8}
|
|
801dbec: bd38 pop {r3, r4, r5, pc}
|
|
801dbee: bf00 nop
|
|
|
|
0801dbf0 <__ieee754_sqrt>:
|
|
801dbf0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801dbf4: 4977 ldr r1, [pc, #476] @ (801ddd4 <__ieee754_sqrt+0x1e4>)
|
|
801dbf6: ec55 4b10 vmov r4, r5, d0
|
|
801dbfa: 43a9 bics r1, r5
|
|
801dbfc: f000 80ae beq.w 801dd5c <__ieee754_sqrt+0x16c>
|
|
801dc00: 2d00 cmp r5, #0
|
|
801dc02: 462a mov r2, r5
|
|
801dc04: 4623 mov r3, r4
|
|
801dc06: dd55 ble.n 801dcb4 <__ieee754_sqrt+0xc4>
|
|
801dc08: 152c asrs r4, r5, #20
|
|
801dc0a: d062 beq.n 801dcd2 <__ieee754_sqrt+0xe2>
|
|
801dc0c: f3c2 0213 ubfx r2, r2, #0, #20
|
|
801dc10: 07e1 lsls r1, r4, #31
|
|
801dc12: f2a4 37ff subw r7, r4, #1023 @ 0x3ff
|
|
801dc16: f442 1280 orr.w r2, r2, #1048576 @ 0x100000
|
|
801dc1a: d403 bmi.n 801dc24 <__ieee754_sqrt+0x34>
|
|
801dc1c: 0052 lsls r2, r2, #1
|
|
801dc1e: eb02 72d3 add.w r2, r2, r3, lsr #31
|
|
801dc22: 005b lsls r3, r3, #1
|
|
801dc24: 0052 lsls r2, r2, #1
|
|
801dc26: 2600 movs r6, #0
|
|
801dc28: eb02 72d3 add.w r2, r2, r3, lsr #31
|
|
801dc2c: 107f asrs r7, r7, #1
|
|
801dc2e: 005b lsls r3, r3, #1
|
|
801dc30: 2416 movs r4, #22
|
|
801dc32: 46b4 mov ip, r6
|
|
801dc34: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
801dc38: eb0c 0001 add.w r0, ip, r1
|
|
801dc3c: 4290 cmp r0, r2
|
|
801dc3e: ea4f 75d3 mov.w r5, r3, lsr #31
|
|
801dc42: ea4f 0343 mov.w r3, r3, lsl #1
|
|
801dc46: dc03 bgt.n 801dc50 <__ieee754_sqrt+0x60>
|
|
801dc48: eb00 0c01 add.w ip, r0, r1
|
|
801dc4c: 1a12 subs r2, r2, r0
|
|
801dc4e: 440e add r6, r1
|
|
801dc50: 3c01 subs r4, #1
|
|
801dc52: eb05 0242 add.w r2, r5, r2, lsl #1
|
|
801dc56: ea4f 0151 mov.w r1, r1, lsr #1
|
|
801dc5a: d1ed bne.n 801dc38 <__ieee754_sqrt+0x48>
|
|
801dc5c: 46a0 mov r8, r4
|
|
801dc5e: 2520 movs r5, #32
|
|
801dc60: f04f 4000 mov.w r0, #2147483648 @ 0x80000000
|
|
801dc64: e00a b.n 801dc7c <__ieee754_sqrt+0x8c>
|
|
801dc66: d043 beq.n 801dcf0 <__ieee754_sqrt+0x100>
|
|
801dc68: 0051 lsls r1, r2, #1
|
|
801dc6a: eb01 71d3 add.w r1, r1, r3, lsr #31
|
|
801dc6e: 3d01 subs r5, #1
|
|
801dc70: 460a mov r2, r1
|
|
801dc72: ea4f 0343 mov.w r3, r3, lsl #1
|
|
801dc76: ea4f 0050 mov.w r0, r0, lsr #1
|
|
801dc7a: d045 beq.n 801dd08 <__ieee754_sqrt+0x118>
|
|
801dc7c: 4562 cmp r2, ip
|
|
801dc7e: eb00 0e08 add.w lr, r0, r8
|
|
801dc82: ddf0 ble.n 801dc66 <__ieee754_sqrt+0x76>
|
|
801dc84: f1be 0f00 cmp.w lr, #0
|
|
801dc88: eb0e 0800 add.w r8, lr, r0
|
|
801dc8c: db0c blt.n 801dca8 <__ieee754_sqrt+0xb8>
|
|
801dc8e: 46e1 mov r9, ip
|
|
801dc90: eba2 010c sub.w r1, r2, ip
|
|
801dc94: 459e cmp lr, r3
|
|
801dc96: bf88 it hi
|
|
801dc98: f101 31ff addhi.w r1, r1, #4294967295 @ 0xffffffff
|
|
801dc9c: 0049 lsls r1, r1, #1
|
|
801dc9e: 46cc mov ip, r9
|
|
801dca0: eba3 030e sub.w r3, r3, lr
|
|
801dca4: 4404 add r4, r0
|
|
801dca6: e7e0 b.n 801dc6a <__ieee754_sqrt+0x7a>
|
|
801dca8: f1b8 0f00 cmp.w r8, #0
|
|
801dcac: dbef blt.n 801dc8e <__ieee754_sqrt+0x9e>
|
|
801dcae: f10c 0901 add.w r9, ip, #1
|
|
801dcb2: e7ed b.n 801dc90 <__ieee754_sqrt+0xa0>
|
|
801dcb4: f025 4100 bic.w r1, r5, #2147483648 @ 0x80000000
|
|
801dcb8: 4321 orrs r1, r4
|
|
801dcba: d046 beq.n 801dd4a <__ieee754_sqrt+0x15a>
|
|
801dcbc: 2d00 cmp r5, #0
|
|
801dcbe: d174 bne.n 801ddaa <__ieee754_sqrt+0x1ba>
|
|
801dcc0: 0ad9 lsrs r1, r3, #11
|
|
801dcc2: 3a15 subs r2, #21
|
|
801dcc4: 055b lsls r3, r3, #21
|
|
801dcc6: 2900 cmp r1, #0
|
|
801dcc8: d0fa beq.n 801dcc0 <__ieee754_sqrt+0xd0>
|
|
801dcca: 02ce lsls r6, r1, #11
|
|
801dccc: 4614 mov r4, r2
|
|
801dcce: d47d bmi.n 801ddcc <__ieee754_sqrt+0x1dc>
|
|
801dcd0: 460a mov r2, r1
|
|
801dcd2: 2100 movs r1, #0
|
|
801dcd4: 0052 lsls r2, r2, #1
|
|
801dcd6: 02d5 lsls r5, r2, #11
|
|
801dcd8: 4608 mov r0, r1
|
|
801dcda: f101 0101 add.w r1, r1, #1
|
|
801dcde: d5f9 bpl.n 801dcd4 <__ieee754_sqrt+0xe4>
|
|
801dce0: f1c1 0520 rsb r5, r1, #32
|
|
801dce4: fa23 f505 lsr.w r5, r3, r5
|
|
801dce8: 432a orrs r2, r5
|
|
801dcea: 408b lsls r3, r1
|
|
801dcec: 1a24 subs r4, r4, r0
|
|
801dcee: e78d b.n 801dc0c <__ieee754_sqrt+0x1c>
|
|
801dcf0: 459e cmp lr, r3
|
|
801dcf2: d902 bls.n 801dcfa <__ieee754_sqrt+0x10a>
|
|
801dcf4: ea4f 014c mov.w r1, ip, lsl #1
|
|
801dcf8: e7b7 b.n 801dc6a <__ieee754_sqrt+0x7a>
|
|
801dcfa: f1be 0f00 cmp.w lr, #0
|
|
801dcfe: eb0e 0800 add.w r8, lr, r0
|
|
801dd02: db24 blt.n 801dd4e <__ieee754_sqrt+0x15e>
|
|
801dd04: 2100 movs r1, #0
|
|
801dd06: e7cb b.n 801dca0 <__ieee754_sqrt+0xb0>
|
|
801dd08: 4319 orrs r1, r3
|
|
801dd0a: d012 beq.n 801dd32 <__ieee754_sqrt+0x142>
|
|
801dd0c: f8df a0c8 ldr.w sl, [pc, #200] @ 801ddd8 <__ieee754_sqrt+0x1e8>
|
|
801dd10: f8df b0c8 ldr.w fp, [pc, #200] @ 801dddc <__ieee754_sqrt+0x1ec>
|
|
801dd14: e9da 0100 ldrd r0, r1, [sl]
|
|
801dd18: e9db 2300 ldrd r2, r3, [fp]
|
|
801dd1c: f7e2 fa8c bl 8000238 <__aeabi_dsub>
|
|
801dd20: e9da 8900 ldrd r8, r9, [sl]
|
|
801dd24: 4602 mov r2, r0
|
|
801dd26: 460b mov r3, r1
|
|
801dd28: 4640 mov r0, r8
|
|
801dd2a: 4649 mov r1, r9
|
|
801dd2c: f7e2 feb8 bl 8000aa0 <__aeabi_dcmple>
|
|
801dd30: bb10 cbnz r0, 801dd78 <__ieee754_sqrt+0x188>
|
|
801dd32: 0865 lsrs r5, r4, #1
|
|
801dd34: 1071 asrs r1, r6, #1
|
|
801dd36: f101 517f add.w r1, r1, #1069547520 @ 0x3fc00000
|
|
801dd3a: f501 1100 add.w r1, r1, #2097152 @ 0x200000
|
|
801dd3e: eb01 5307 add.w r3, r1, r7, lsl #20
|
|
801dd42: ea45 72c6 orr.w r2, r5, r6, lsl #31
|
|
801dd46: ec43 2b10 vmov d0, r2, r3
|
|
801dd4a: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801dd4e: f1b8 0f00 cmp.w r8, #0
|
|
801dd52: dbd7 blt.n 801dd04 <__ieee754_sqrt+0x114>
|
|
801dd54: f10c 0c01 add.w ip, ip, #1
|
|
801dd58: 2100 movs r1, #0
|
|
801dd5a: e7a1 b.n 801dca0 <__ieee754_sqrt+0xb0>
|
|
801dd5c: 4622 mov r2, r4
|
|
801dd5e: 462b mov r3, r5
|
|
801dd60: 4620 mov r0, r4
|
|
801dd62: 4629 mov r1, r5
|
|
801dd64: f7e2 fc20 bl 80005a8 <__aeabi_dmul>
|
|
801dd68: 4622 mov r2, r4
|
|
801dd6a: 462b mov r3, r5
|
|
801dd6c: f7e2 fa66 bl 800023c <__adddf3>
|
|
801dd70: ec41 0b10 vmov d0, r0, r1
|
|
801dd74: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801dd78: f1b4 3fff cmp.w r4, #4294967295 @ 0xffffffff
|
|
801dd7c: e9da 0100 ldrd r0, r1, [sl]
|
|
801dd80: e9db 2300 ldrd r2, r3, [fp]
|
|
801dd84: d01e beq.n 801ddc4 <__ieee754_sqrt+0x1d4>
|
|
801dd86: f7e2 fa59 bl 800023c <__adddf3>
|
|
801dd8a: e9da 8900 ldrd r8, r9, [sl]
|
|
801dd8e: 4602 mov r2, r0
|
|
801dd90: 460b mov r3, r1
|
|
801dd92: 4640 mov r0, r8
|
|
801dd94: 4649 mov r1, r9
|
|
801dd96: f7e2 fe79 bl 8000a8c <__aeabi_dcmplt>
|
|
801dd9a: b1a8 cbz r0, 801ddc8 <__ieee754_sqrt+0x1d8>
|
|
801dd9c: 1ca3 adds r3, r4, #2
|
|
801dd9e: f104 0502 add.w r5, r4, #2
|
|
801dda2: bf08 it eq
|
|
801dda4: 3601 addeq r6, #1
|
|
801dda6: 086d lsrs r5, r5, #1
|
|
801dda8: e7c4 b.n 801dd34 <__ieee754_sqrt+0x144>
|
|
801ddaa: 4622 mov r2, r4
|
|
801ddac: 462b mov r3, r5
|
|
801ddae: 4620 mov r0, r4
|
|
801ddb0: 4629 mov r1, r5
|
|
801ddb2: f7e2 fa41 bl 8000238 <__aeabi_dsub>
|
|
801ddb6: 4602 mov r2, r0
|
|
801ddb8: 460b mov r3, r1
|
|
801ddba: f7e2 fd1f bl 80007fc <__aeabi_ddiv>
|
|
801ddbe: ec41 0b10 vmov d0, r0, r1
|
|
801ddc2: e7c2 b.n 801dd4a <__ieee754_sqrt+0x15a>
|
|
801ddc4: 3601 adds r6, #1
|
|
801ddc6: e7b5 b.n 801dd34 <__ieee754_sqrt+0x144>
|
|
801ddc8: 3401 adds r4, #1
|
|
801ddca: e7b2 b.n 801dd32 <__ieee754_sqrt+0x142>
|
|
801ddcc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
801ddd0: 460a mov r2, r1
|
|
801ddd2: e78b b.n 801dcec <__ieee754_sqrt+0xfc>
|
|
801ddd4: 7ff00000 .word 0x7ff00000
|
|
801ddd8: 0801ea48 .word 0x0801ea48
|
|
801dddc: 0801ea40 .word 0x0801ea40
|
|
|
|
0801dde0 <_init>:
|
|
801dde0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801dde2: bf00 nop
|
|
801dde4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
801dde6: bc08 pop {r3}
|
|
801dde8: 469e mov lr, r3
|
|
801ddea: 4770 bx lr
|
|
|
|
0801ddec <_fini>:
|
|
801ddec: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801ddee: bf00 nop
|
|
801ddf0: bcf8 pop {r3, r4, r5, r6, r7}
|
|
801ddf2: bc08 pop {r3}
|
|
801ddf4: 469e mov lr, r3
|
|
801ddf6: 4770 bx lr
|