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Trinity_Devboard_V2.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000013c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0001bf50 08000140 08000140 00001140 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000b54 0801c090 0801c090 0001d090 2**3
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM 00000008 0801cbe4 0801cbe4 0001dbe4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
4 .init_array 00000004 0801cbec 0801cbec 0001dbec 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .fini_array 00000004 0801cbf0 0801cbf0 0001dbf0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
6 .data 000002d0 20000008 0801cbf4 0001e008 2**2
CONTENTS, ALLOC, LOAD, DATA
7 SYSTEM_DRIVER_CONTEXT 00000011 200002d8 0801cec4 0001e2d8 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .bss 0001395c 200002ec 0801ced5 0001e2ec 2**2
ALLOC
9 ._user_heap_stack 00000600 20013c48 0801ced5 0001ec48 2**0
ALLOC
10 .ARM.attributes 00000030 00000000 00000000 0001f94a 2**0
CONTENTS, READONLY
11 MAPPING_TABLE 00000028 20030000 20030000 00020000 2**2
ALLOC
12 MB_MEM1 000000b0 20030028 20030028 00020000 2**2
ALLOC
13 .MB_MEM2 00000872 200300d8 0801ced5 0001f0d8 2**2
CONTENTS, ALLOC, LOAD, DATA
14 .debug_info 0003a0d3 00000000 00000000 0001f97a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_abbrev 000085e3 00000000 00000000 00059a4d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_aranges 00003628 00000000 00000000 00062030 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_rnglists 00002942 00000000 00000000 00065658 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_macro 000318b5 00000000 00000000 00067f9a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_line 0003b2b9 00000000 00000000 0009984f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_str 00112843 00000000 00000000 000d4b08 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .comment 00000043 00000000 00000000 001e734b 2**0
CONTENTS, READONLY
22 .debug_frame 0000ecf0 00000000 00000000 001e7390 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
23 .debug_line_str 00000061 00000000 00000000 001f6080 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000140 <__do_global_dtors_aux>:
8000140: b510 push {r4, lr}
8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>)
8000144: 7823 ldrb r3, [r4, #0]
8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16>
8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>)
800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12>
800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>)
800014e: f3af 8000 nop.w
8000152: 2301 movs r3, #1
8000154: 7023 strb r3, [r4, #0]
8000156: bd10 pop {r4, pc}
8000158: 200002ec .word 0x200002ec
800015c: 00000000 .word 0x00000000
8000160: 0801c078 .word 0x0801c078
08000164 <frame_dummy>:
8000164: b508 push {r3, lr}
8000166: 4b03 ldr r3, [pc, #12] @ (8000174 <frame_dummy+0x10>)
8000168: b11b cbz r3, 8000172 <frame_dummy+0xe>
800016a: 4903 ldr r1, [pc, #12] @ (8000178 <frame_dummy+0x14>)
800016c: 4803 ldr r0, [pc, #12] @ (800017c <frame_dummy+0x18>)
800016e: f3af 8000 nop.w
8000172: bd08 pop {r3, pc}
8000174: 00000000 .word 0x00000000
8000178: 200002f0 .word 0x200002f0
800017c: 0801c078 .word 0x0801c078
08000180 <memchr>:
8000180: f001 01ff and.w r1, r1, #255 @ 0xff
8000184: 2a10 cmp r2, #16
8000186: db2b blt.n 80001e0 <memchr+0x60>
8000188: f010 0f07 tst.w r0, #7
800018c: d008 beq.n 80001a0 <memchr+0x20>
800018e: f810 3b01 ldrb.w r3, [r0], #1
8000192: 3a01 subs r2, #1
8000194: 428b cmp r3, r1
8000196: d02d beq.n 80001f4 <memchr+0x74>
8000198: f010 0f07 tst.w r0, #7
800019c: b342 cbz r2, 80001f0 <memchr+0x70>
800019e: d1f6 bne.n 800018e <memchr+0xe>
80001a0: b4f0 push {r4, r5, r6, r7}
80001a2: ea41 2101 orr.w r1, r1, r1, lsl #8
80001a6: ea41 4101 orr.w r1, r1, r1, lsl #16
80001aa: f022 0407 bic.w r4, r2, #7
80001ae: f07f 0700 mvns.w r7, #0
80001b2: 2300 movs r3, #0
80001b4: e8f0 5602 ldrd r5, r6, [r0], #8
80001b8: 3c08 subs r4, #8
80001ba: ea85 0501 eor.w r5, r5, r1
80001be: ea86 0601 eor.w r6, r6, r1
80001c2: fa85 f547 uadd8 r5, r5, r7
80001c6: faa3 f587 sel r5, r3, r7
80001ca: fa86 f647 uadd8 r6, r6, r7
80001ce: faa5 f687 sel r6, r5, r7
80001d2: b98e cbnz r6, 80001f8 <memchr+0x78>
80001d4: d1ee bne.n 80001b4 <memchr+0x34>
80001d6: bcf0 pop {r4, r5, r6, r7}
80001d8: f001 01ff and.w r1, r1, #255 @ 0xff
80001dc: f002 0207 and.w r2, r2, #7
80001e0: b132 cbz r2, 80001f0 <memchr+0x70>
80001e2: f810 3b01 ldrb.w r3, [r0], #1
80001e6: 3a01 subs r2, #1
80001e8: ea83 0301 eor.w r3, r3, r1
80001ec: b113 cbz r3, 80001f4 <memchr+0x74>
80001ee: d1f8 bne.n 80001e2 <memchr+0x62>
80001f0: 2000 movs r0, #0
80001f2: 4770 bx lr
80001f4: 3801 subs r0, #1
80001f6: 4770 bx lr
80001f8: 2d00 cmp r5, #0
80001fa: bf06 itte eq
80001fc: 4635 moveq r5, r6
80001fe: 3803 subeq r0, #3
8000200: 3807 subne r0, #7
8000202: f015 0f01 tst.w r5, #1
8000206: d107 bne.n 8000218 <memchr+0x98>
8000208: 3001 adds r0, #1
800020a: f415 7f80 tst.w r5, #256 @ 0x100
800020e: bf02 ittt eq
8000210: 3001 addeq r0, #1
8000212: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
8000216: 3001 addeq r0, #1
8000218: bcf0 pop {r4, r5, r6, r7}
800021a: 3801 subs r0, #1
800021c: 4770 bx lr
800021e: bf00 nop
08000220 <strlen>:
8000220: 4603 mov r3, r0
8000222: f813 2b01 ldrb.w r2, [r3], #1
8000226: 2a00 cmp r2, #0
8000228: d1fb bne.n 8000222 <strlen+0x2>
800022a: 1a18 subs r0, r3, r0
800022c: 3801 subs r0, #1
800022e: 4770 bx lr
08000230 <__aeabi_drsub>:
8000230: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
8000234: e002 b.n 800023c <__adddf3>
8000236: bf00 nop
08000238 <__aeabi_dsub>:
8000238: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
0800023c <__adddf3>:
800023c: b530 push {r4, r5, lr}
800023e: ea4f 0441 mov.w r4, r1, lsl #1
8000242: ea4f 0543 mov.w r5, r3, lsl #1
8000246: ea94 0f05 teq r4, r5
800024a: bf08 it eq
800024c: ea90 0f02 teqeq r0, r2
8000250: bf1f itttt ne
8000252: ea54 0c00 orrsne.w ip, r4, r0
8000256: ea55 0c02 orrsne.w ip, r5, r2
800025a: ea7f 5c64 mvnsne.w ip, r4, asr #21
800025e: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000262: f000 80e2 beq.w 800042a <__adddf3+0x1ee>
8000266: ea4f 5454 mov.w r4, r4, lsr #21
800026a: ebd4 5555 rsbs r5, r4, r5, lsr #21
800026e: bfb8 it lt
8000270: 426d neglt r5, r5
8000272: dd0c ble.n 800028e <__adddf3+0x52>
8000274: 442c add r4, r5
8000276: ea80 0202 eor.w r2, r0, r2
800027a: ea81 0303 eor.w r3, r1, r3
800027e: ea82 0000 eor.w r0, r2, r0
8000282: ea83 0101 eor.w r1, r3, r1
8000286: ea80 0202 eor.w r2, r0, r2
800028a: ea81 0303 eor.w r3, r1, r3
800028e: 2d36 cmp r5, #54 @ 0x36
8000290: bf88 it hi
8000292: bd30 pophi {r4, r5, pc}
8000294: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
8000298: ea4f 3101 mov.w r1, r1, lsl #12
800029c: f44f 1c80 mov.w ip, #1048576 @ 0x100000
80002a0: ea4c 3111 orr.w r1, ip, r1, lsr #12
80002a4: d002 beq.n 80002ac <__adddf3+0x70>
80002a6: 4240 negs r0, r0
80002a8: eb61 0141 sbc.w r1, r1, r1, lsl #1
80002ac: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
80002b0: ea4f 3303 mov.w r3, r3, lsl #12
80002b4: ea4c 3313 orr.w r3, ip, r3, lsr #12
80002b8: d002 beq.n 80002c0 <__adddf3+0x84>
80002ba: 4252 negs r2, r2
80002bc: eb63 0343 sbc.w r3, r3, r3, lsl #1
80002c0: ea94 0f05 teq r4, r5
80002c4: f000 80a7 beq.w 8000416 <__adddf3+0x1da>
80002c8: f1a4 0401 sub.w r4, r4, #1
80002cc: f1d5 0e20 rsbs lr, r5, #32
80002d0: db0d blt.n 80002ee <__adddf3+0xb2>
80002d2: fa02 fc0e lsl.w ip, r2, lr
80002d6: fa22 f205 lsr.w r2, r2, r5
80002da: 1880 adds r0, r0, r2
80002dc: f141 0100 adc.w r1, r1, #0
80002e0: fa03 f20e lsl.w r2, r3, lr
80002e4: 1880 adds r0, r0, r2
80002e6: fa43 f305 asr.w r3, r3, r5
80002ea: 4159 adcs r1, r3
80002ec: e00e b.n 800030c <__adddf3+0xd0>
80002ee: f1a5 0520 sub.w r5, r5, #32
80002f2: f10e 0e20 add.w lr, lr, #32
80002f6: 2a01 cmp r2, #1
80002f8: fa03 fc0e lsl.w ip, r3, lr
80002fc: bf28 it cs
80002fe: f04c 0c02 orrcs.w ip, ip, #2
8000302: fa43 f305 asr.w r3, r3, r5
8000306: 18c0 adds r0, r0, r3
8000308: eb51 71e3 adcs.w r1, r1, r3, asr #31
800030c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000310: d507 bpl.n 8000322 <__adddf3+0xe6>
8000312: f04f 0e00 mov.w lr, #0
8000316: f1dc 0c00 rsbs ip, ip, #0
800031a: eb7e 0000 sbcs.w r0, lr, r0
800031e: eb6e 0101 sbc.w r1, lr, r1
8000322: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
8000326: d31b bcc.n 8000360 <__adddf3+0x124>
8000328: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
800032c: d30c bcc.n 8000348 <__adddf3+0x10c>
800032e: 0849 lsrs r1, r1, #1
8000330: ea5f 0030 movs.w r0, r0, rrx
8000334: ea4f 0c3c mov.w ip, ip, rrx
8000338: f104 0401 add.w r4, r4, #1
800033c: ea4f 5244 mov.w r2, r4, lsl #21
8000340: f512 0f80 cmn.w r2, #4194304 @ 0x400000
8000344: f080 809a bcs.w 800047c <__adddf3+0x240>
8000348: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
800034c: bf08 it eq
800034e: ea5f 0c50 movseq.w ip, r0, lsr #1
8000352: f150 0000 adcs.w r0, r0, #0
8000356: eb41 5104 adc.w r1, r1, r4, lsl #20
800035a: ea41 0105 orr.w r1, r1, r5
800035e: bd30 pop {r4, r5, pc}
8000360: ea5f 0c4c movs.w ip, ip, lsl #1
8000364: 4140 adcs r0, r0
8000366: eb41 0101 adc.w r1, r1, r1
800036a: 3c01 subs r4, #1
800036c: bf28 it cs
800036e: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
8000372: d2e9 bcs.n 8000348 <__adddf3+0x10c>
8000374: f091 0f00 teq r1, #0
8000378: bf04 itt eq
800037a: 4601 moveq r1, r0
800037c: 2000 moveq r0, #0
800037e: fab1 f381 clz r3, r1
8000382: bf08 it eq
8000384: 3320 addeq r3, #32
8000386: f1a3 030b sub.w r3, r3, #11
800038a: f1b3 0220 subs.w r2, r3, #32
800038e: da0c bge.n 80003aa <__adddf3+0x16e>
8000390: 320c adds r2, #12
8000392: dd08 ble.n 80003a6 <__adddf3+0x16a>
8000394: f102 0c14 add.w ip, r2, #20
8000398: f1c2 020c rsb r2, r2, #12
800039c: fa01 f00c lsl.w r0, r1, ip
80003a0: fa21 f102 lsr.w r1, r1, r2
80003a4: e00c b.n 80003c0 <__adddf3+0x184>
80003a6: f102 0214 add.w r2, r2, #20
80003aa: bfd8 it le
80003ac: f1c2 0c20 rsble ip, r2, #32
80003b0: fa01 f102 lsl.w r1, r1, r2
80003b4: fa20 fc0c lsr.w ip, r0, ip
80003b8: bfdc itt le
80003ba: ea41 010c orrle.w r1, r1, ip
80003be: 4090 lslle r0, r2
80003c0: 1ae4 subs r4, r4, r3
80003c2: bfa2 ittt ge
80003c4: eb01 5104 addge.w r1, r1, r4, lsl #20
80003c8: 4329 orrge r1, r5
80003ca: bd30 popge {r4, r5, pc}
80003cc: ea6f 0404 mvn.w r4, r4
80003d0: 3c1f subs r4, #31
80003d2: da1c bge.n 800040e <__adddf3+0x1d2>
80003d4: 340c adds r4, #12
80003d6: dc0e bgt.n 80003f6 <__adddf3+0x1ba>
80003d8: f104 0414 add.w r4, r4, #20
80003dc: f1c4 0220 rsb r2, r4, #32
80003e0: fa20 f004 lsr.w r0, r0, r4
80003e4: fa01 f302 lsl.w r3, r1, r2
80003e8: ea40 0003 orr.w r0, r0, r3
80003ec: fa21 f304 lsr.w r3, r1, r4
80003f0: ea45 0103 orr.w r1, r5, r3
80003f4: bd30 pop {r4, r5, pc}
80003f6: f1c4 040c rsb r4, r4, #12
80003fa: f1c4 0220 rsb r2, r4, #32
80003fe: fa20 f002 lsr.w r0, r0, r2
8000402: fa01 f304 lsl.w r3, r1, r4
8000406: ea40 0003 orr.w r0, r0, r3
800040a: 4629 mov r1, r5
800040c: bd30 pop {r4, r5, pc}
800040e: fa21 f004 lsr.w r0, r1, r4
8000412: 4629 mov r1, r5
8000414: bd30 pop {r4, r5, pc}
8000416: f094 0f00 teq r4, #0
800041a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800041e: bf06 itte eq
8000420: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
8000424: 3401 addeq r4, #1
8000426: 3d01 subne r5, #1
8000428: e74e b.n 80002c8 <__adddf3+0x8c>
800042a: ea7f 5c64 mvns.w ip, r4, asr #21
800042e: bf18 it ne
8000430: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000434: d029 beq.n 800048a <__adddf3+0x24e>
8000436: ea94 0f05 teq r4, r5
800043a: bf08 it eq
800043c: ea90 0f02 teqeq r0, r2
8000440: d005 beq.n 800044e <__adddf3+0x212>
8000442: ea54 0c00 orrs.w ip, r4, r0
8000446: bf04 itt eq
8000448: 4619 moveq r1, r3
800044a: 4610 moveq r0, r2
800044c: bd30 pop {r4, r5, pc}
800044e: ea91 0f03 teq r1, r3
8000452: bf1e ittt ne
8000454: 2100 movne r1, #0
8000456: 2000 movne r0, #0
8000458: bd30 popne {r4, r5, pc}
800045a: ea5f 5c54 movs.w ip, r4, lsr #21
800045e: d105 bne.n 800046c <__adddf3+0x230>
8000460: 0040 lsls r0, r0, #1
8000462: 4149 adcs r1, r1
8000464: bf28 it cs
8000466: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
800046a: bd30 pop {r4, r5, pc}
800046c: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
8000470: bf3c itt cc
8000472: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
8000476: bd30 popcc {r4, r5, pc}
8000478: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
800047c: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
8000480: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
8000484: f04f 0000 mov.w r0, #0
8000488: bd30 pop {r4, r5, pc}
800048a: ea7f 5c64 mvns.w ip, r4, asr #21
800048e: bf1a itte ne
8000490: 4619 movne r1, r3
8000492: 4610 movne r0, r2
8000494: ea7f 5c65 mvnseq.w ip, r5, asr #21
8000498: bf1c itt ne
800049a: 460b movne r3, r1
800049c: 4602 movne r2, r0
800049e: ea50 3401 orrs.w r4, r0, r1, lsl #12
80004a2: bf06 itte eq
80004a4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
80004a8: ea91 0f03 teqeq r1, r3
80004ac: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
80004b0: bd30 pop {r4, r5, pc}
80004b2: bf00 nop
080004b4 <__aeabi_ui2d>:
80004b4: f090 0f00 teq r0, #0
80004b8: bf04 itt eq
80004ba: 2100 moveq r1, #0
80004bc: 4770 bxeq lr
80004be: b530 push {r4, r5, lr}
80004c0: f44f 6480 mov.w r4, #1024 @ 0x400
80004c4: f104 0432 add.w r4, r4, #50 @ 0x32
80004c8: f04f 0500 mov.w r5, #0
80004cc: f04f 0100 mov.w r1, #0
80004d0: e750 b.n 8000374 <__adddf3+0x138>
80004d2: bf00 nop
080004d4 <__aeabi_i2d>:
80004d4: f090 0f00 teq r0, #0
80004d8: bf04 itt eq
80004da: 2100 moveq r1, #0
80004dc: 4770 bxeq lr
80004de: b530 push {r4, r5, lr}
80004e0: f44f 6480 mov.w r4, #1024 @ 0x400
80004e4: f104 0432 add.w r4, r4, #50 @ 0x32
80004e8: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
80004ec: bf48 it mi
80004ee: 4240 negmi r0, r0
80004f0: f04f 0100 mov.w r1, #0
80004f4: e73e b.n 8000374 <__adddf3+0x138>
80004f6: bf00 nop
080004f8 <__aeabi_f2d>:
80004f8: 0042 lsls r2, r0, #1
80004fa: ea4f 01e2 mov.w r1, r2, asr #3
80004fe: ea4f 0131 mov.w r1, r1, rrx
8000502: ea4f 7002 mov.w r0, r2, lsl #28
8000506: bf1f itttt ne
8000508: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
800050c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
8000510: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000514: 4770 bxne lr
8000516: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
800051a: bf08 it eq
800051c: 4770 bxeq lr
800051e: f093 4f7f teq r3, #4278190080 @ 0xff000000
8000522: bf04 itt eq
8000524: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
8000528: 4770 bxeq lr
800052a: b530 push {r4, r5, lr}
800052c: f44f 7460 mov.w r4, #896 @ 0x380
8000530: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000534: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000538: e71c b.n 8000374 <__adddf3+0x138>
800053a: bf00 nop
0800053c <__aeabi_ul2d>:
800053c: ea50 0201 orrs.w r2, r0, r1
8000540: bf08 it eq
8000542: 4770 bxeq lr
8000544: b530 push {r4, r5, lr}
8000546: f04f 0500 mov.w r5, #0
800054a: e00a b.n 8000562 <__aeabi_l2d+0x16>
0800054c <__aeabi_l2d>:
800054c: ea50 0201 orrs.w r2, r0, r1
8000550: bf08 it eq
8000552: 4770 bxeq lr
8000554: b530 push {r4, r5, lr}
8000556: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
800055a: d502 bpl.n 8000562 <__aeabi_l2d+0x16>
800055c: 4240 negs r0, r0
800055e: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000562: f44f 6480 mov.w r4, #1024 @ 0x400
8000566: f104 0432 add.w r4, r4, #50 @ 0x32
800056a: ea5f 5c91 movs.w ip, r1, lsr #22
800056e: f43f aed8 beq.w 8000322 <__adddf3+0xe6>
8000572: f04f 0203 mov.w r2, #3
8000576: ea5f 0cdc movs.w ip, ip, lsr #3
800057a: bf18 it ne
800057c: 3203 addne r2, #3
800057e: ea5f 0cdc movs.w ip, ip, lsr #3
8000582: bf18 it ne
8000584: 3203 addne r2, #3
8000586: eb02 02dc add.w r2, r2, ip, lsr #3
800058a: f1c2 0320 rsb r3, r2, #32
800058e: fa00 fc03 lsl.w ip, r0, r3
8000592: fa20 f002 lsr.w r0, r0, r2
8000596: fa01 fe03 lsl.w lr, r1, r3
800059a: ea40 000e orr.w r0, r0, lr
800059e: fa21 f102 lsr.w r1, r1, r2
80005a2: 4414 add r4, r2
80005a4: e6bd b.n 8000322 <__adddf3+0xe6>
80005a6: bf00 nop
080005a8 <__aeabi_dmul>:
80005a8: b570 push {r4, r5, r6, lr}
80005aa: f04f 0cff mov.w ip, #255 @ 0xff
80005ae: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
80005b2: ea1c 5411 ands.w r4, ip, r1, lsr #20
80005b6: bf1d ittte ne
80005b8: ea1c 5513 andsne.w r5, ip, r3, lsr #20
80005bc: ea94 0f0c teqne r4, ip
80005c0: ea95 0f0c teqne r5, ip
80005c4: f000 f8de bleq 8000784 <__aeabi_dmul+0x1dc>
80005c8: 442c add r4, r5
80005ca: ea81 0603 eor.w r6, r1, r3
80005ce: ea21 514c bic.w r1, r1, ip, lsl #21
80005d2: ea23 534c bic.w r3, r3, ip, lsl #21
80005d6: ea50 3501 orrs.w r5, r0, r1, lsl #12
80005da: bf18 it ne
80005dc: ea52 3503 orrsne.w r5, r2, r3, lsl #12
80005e0: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80005e4: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80005e8: d038 beq.n 800065c <__aeabi_dmul+0xb4>
80005ea: fba0 ce02 umull ip, lr, r0, r2
80005ee: f04f 0500 mov.w r5, #0
80005f2: fbe1 e502 umlal lr, r5, r1, r2
80005f6: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
80005fa: fbe0 e503 umlal lr, r5, r0, r3
80005fe: f04f 0600 mov.w r6, #0
8000602: fbe1 5603 umlal r5, r6, r1, r3
8000606: f09c 0f00 teq ip, #0
800060a: bf18 it ne
800060c: f04e 0e01 orrne.w lr, lr, #1
8000610: f1a4 04ff sub.w r4, r4, #255 @ 0xff
8000614: f5b6 7f00 cmp.w r6, #512 @ 0x200
8000618: f564 7440 sbc.w r4, r4, #768 @ 0x300
800061c: d204 bcs.n 8000628 <__aeabi_dmul+0x80>
800061e: ea5f 0e4e movs.w lr, lr, lsl #1
8000622: 416d adcs r5, r5
8000624: eb46 0606 adc.w r6, r6, r6
8000628: ea42 21c6 orr.w r1, r2, r6, lsl #11
800062c: ea41 5155 orr.w r1, r1, r5, lsr #21
8000630: ea4f 20c5 mov.w r0, r5, lsl #11
8000634: ea40 505e orr.w r0, r0, lr, lsr #21
8000638: ea4f 2ece mov.w lr, lr, lsl #11
800063c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
8000640: bf88 it hi
8000642: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
8000646: d81e bhi.n 8000686 <__aeabi_dmul+0xde>
8000648: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
800064c: bf08 it eq
800064e: ea5f 0e50 movseq.w lr, r0, lsr #1
8000652: f150 0000 adcs.w r0, r0, #0
8000656: eb41 5104 adc.w r1, r1, r4, lsl #20
800065a: bd70 pop {r4, r5, r6, pc}
800065c: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
8000660: ea46 0101 orr.w r1, r6, r1
8000664: ea40 0002 orr.w r0, r0, r2
8000668: ea81 0103 eor.w r1, r1, r3
800066c: ebb4 045c subs.w r4, r4, ip, lsr #1
8000670: bfc2 ittt gt
8000672: ebd4 050c rsbsgt r5, r4, ip
8000676: ea41 5104 orrgt.w r1, r1, r4, lsl #20
800067a: bd70 popgt {r4, r5, r6, pc}
800067c: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000680: f04f 0e00 mov.w lr, #0
8000684: 3c01 subs r4, #1
8000686: f300 80ab bgt.w 80007e0 <__aeabi_dmul+0x238>
800068a: f114 0f36 cmn.w r4, #54 @ 0x36
800068e: bfde ittt le
8000690: 2000 movle r0, #0
8000692: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
8000696: bd70 pople {r4, r5, r6, pc}
8000698: f1c4 0400 rsb r4, r4, #0
800069c: 3c20 subs r4, #32
800069e: da35 bge.n 800070c <__aeabi_dmul+0x164>
80006a0: 340c adds r4, #12
80006a2: dc1b bgt.n 80006dc <__aeabi_dmul+0x134>
80006a4: f104 0414 add.w r4, r4, #20
80006a8: f1c4 0520 rsb r5, r4, #32
80006ac: fa00 f305 lsl.w r3, r0, r5
80006b0: fa20 f004 lsr.w r0, r0, r4
80006b4: fa01 f205 lsl.w r2, r1, r5
80006b8: ea40 0002 orr.w r0, r0, r2
80006bc: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
80006c0: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
80006c4: eb10 70d3 adds.w r0, r0, r3, lsr #31
80006c8: fa21 f604 lsr.w r6, r1, r4
80006cc: eb42 0106 adc.w r1, r2, r6
80006d0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80006d4: bf08 it eq
80006d6: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80006da: bd70 pop {r4, r5, r6, pc}
80006dc: f1c4 040c rsb r4, r4, #12
80006e0: f1c4 0520 rsb r5, r4, #32
80006e4: fa00 f304 lsl.w r3, r0, r4
80006e8: fa20 f005 lsr.w r0, r0, r5
80006ec: fa01 f204 lsl.w r2, r1, r4
80006f0: ea40 0002 orr.w r0, r0, r2
80006f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80006f8: eb10 70d3 adds.w r0, r0, r3, lsr #31
80006fc: f141 0100 adc.w r1, r1, #0
8000700: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000704: bf08 it eq
8000706: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800070a: bd70 pop {r4, r5, r6, pc}
800070c: f1c4 0520 rsb r5, r4, #32
8000710: fa00 f205 lsl.w r2, r0, r5
8000714: ea4e 0e02 orr.w lr, lr, r2
8000718: fa20 f304 lsr.w r3, r0, r4
800071c: fa01 f205 lsl.w r2, r1, r5
8000720: ea43 0302 orr.w r3, r3, r2
8000724: fa21 f004 lsr.w r0, r1, r4
8000728: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800072c: fa21 f204 lsr.w r2, r1, r4
8000730: ea20 0002 bic.w r0, r0, r2
8000734: eb00 70d3 add.w r0, r0, r3, lsr #31
8000738: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
800073c: bf08 it eq
800073e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
8000742: bd70 pop {r4, r5, r6, pc}
8000744: f094 0f00 teq r4, #0
8000748: d10f bne.n 800076a <__aeabi_dmul+0x1c2>
800074a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
800074e: 0040 lsls r0, r0, #1
8000750: eb41 0101 adc.w r1, r1, r1
8000754: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000758: bf08 it eq
800075a: 3c01 subeq r4, #1
800075c: d0f7 beq.n 800074e <__aeabi_dmul+0x1a6>
800075e: ea41 0106 orr.w r1, r1, r6
8000762: f095 0f00 teq r5, #0
8000766: bf18 it ne
8000768: 4770 bxne lr
800076a: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
800076e: 0052 lsls r2, r2, #1
8000770: eb43 0303 adc.w r3, r3, r3
8000774: f413 1f80 tst.w r3, #1048576 @ 0x100000
8000778: bf08 it eq
800077a: 3d01 subeq r5, #1
800077c: d0f7 beq.n 800076e <__aeabi_dmul+0x1c6>
800077e: ea43 0306 orr.w r3, r3, r6
8000782: 4770 bx lr
8000784: ea94 0f0c teq r4, ip
8000788: ea0c 5513 and.w r5, ip, r3, lsr #20
800078c: bf18 it ne
800078e: ea95 0f0c teqne r5, ip
8000792: d00c beq.n 80007ae <__aeabi_dmul+0x206>
8000794: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000798: bf18 it ne
800079a: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800079e: d1d1 bne.n 8000744 <__aeabi_dmul+0x19c>
80007a0: ea81 0103 eor.w r1, r1, r3
80007a4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80007a8: f04f 0000 mov.w r0, #0
80007ac: bd70 pop {r4, r5, r6, pc}
80007ae: ea50 0641 orrs.w r6, r0, r1, lsl #1
80007b2: bf06 itte eq
80007b4: 4610 moveq r0, r2
80007b6: 4619 moveq r1, r3
80007b8: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80007bc: d019 beq.n 80007f2 <__aeabi_dmul+0x24a>
80007be: ea94 0f0c teq r4, ip
80007c2: d102 bne.n 80007ca <__aeabi_dmul+0x222>
80007c4: ea50 3601 orrs.w r6, r0, r1, lsl #12
80007c8: d113 bne.n 80007f2 <__aeabi_dmul+0x24a>
80007ca: ea95 0f0c teq r5, ip
80007ce: d105 bne.n 80007dc <__aeabi_dmul+0x234>
80007d0: ea52 3603 orrs.w r6, r2, r3, lsl #12
80007d4: bf1c itt ne
80007d6: 4610 movne r0, r2
80007d8: 4619 movne r1, r3
80007da: d10a bne.n 80007f2 <__aeabi_dmul+0x24a>
80007dc: ea81 0103 eor.w r1, r1, r3
80007e0: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80007e4: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
80007e8: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80007ec: f04f 0000 mov.w r0, #0
80007f0: bd70 pop {r4, r5, r6, pc}
80007f2: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
80007f6: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
80007fa: bd70 pop {r4, r5, r6, pc}
080007fc <__aeabi_ddiv>:
80007fc: b570 push {r4, r5, r6, lr}
80007fe: f04f 0cff mov.w ip, #255 @ 0xff
8000802: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000806: ea1c 5411 ands.w r4, ip, r1, lsr #20
800080a: bf1d ittte ne
800080c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000810: ea94 0f0c teqne r4, ip
8000814: ea95 0f0c teqne r5, ip
8000818: f000 f8a7 bleq 800096a <__aeabi_ddiv+0x16e>
800081c: eba4 0405 sub.w r4, r4, r5
8000820: ea81 0e03 eor.w lr, r1, r3
8000824: ea52 3503 orrs.w r5, r2, r3, lsl #12
8000828: ea4f 3101 mov.w r1, r1, lsl #12
800082c: f000 8088 beq.w 8000940 <__aeabi_ddiv+0x144>
8000830: ea4f 3303 mov.w r3, r3, lsl #12
8000834: f04f 5580 mov.w r5, #268435456 @ 0x10000000
8000838: ea45 1313 orr.w r3, r5, r3, lsr #4
800083c: ea43 6312 orr.w r3, r3, r2, lsr #24
8000840: ea4f 2202 mov.w r2, r2, lsl #8
8000844: ea45 1511 orr.w r5, r5, r1, lsr #4
8000848: ea45 6510 orr.w r5, r5, r0, lsr #24
800084c: ea4f 2600 mov.w r6, r0, lsl #8
8000850: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
8000854: 429d cmp r5, r3
8000856: bf08 it eq
8000858: 4296 cmpeq r6, r2
800085a: f144 04fd adc.w r4, r4, #253 @ 0xfd
800085e: f504 7440 add.w r4, r4, #768 @ 0x300
8000862: d202 bcs.n 800086a <__aeabi_ddiv+0x6e>
8000864: 085b lsrs r3, r3, #1
8000866: ea4f 0232 mov.w r2, r2, rrx
800086a: 1ab6 subs r6, r6, r2
800086c: eb65 0503 sbc.w r5, r5, r3
8000870: 085b lsrs r3, r3, #1
8000872: ea4f 0232 mov.w r2, r2, rrx
8000876: f44f 1080 mov.w r0, #1048576 @ 0x100000
800087a: f44f 2c00 mov.w ip, #524288 @ 0x80000
800087e: ebb6 0e02 subs.w lr, r6, r2
8000882: eb75 0e03 sbcs.w lr, r5, r3
8000886: bf22 ittt cs
8000888: 1ab6 subcs r6, r6, r2
800088a: 4675 movcs r5, lr
800088c: ea40 000c orrcs.w r0, r0, ip
8000890: 085b lsrs r3, r3, #1
8000892: ea4f 0232 mov.w r2, r2, rrx
8000896: ebb6 0e02 subs.w lr, r6, r2
800089a: eb75 0e03 sbcs.w lr, r5, r3
800089e: bf22 ittt cs
80008a0: 1ab6 subcs r6, r6, r2
80008a2: 4675 movcs r5, lr
80008a4: ea40 005c orrcs.w r0, r0, ip, lsr #1
80008a8: 085b lsrs r3, r3, #1
80008aa: ea4f 0232 mov.w r2, r2, rrx
80008ae: ebb6 0e02 subs.w lr, r6, r2
80008b2: eb75 0e03 sbcs.w lr, r5, r3
80008b6: bf22 ittt cs
80008b8: 1ab6 subcs r6, r6, r2
80008ba: 4675 movcs r5, lr
80008bc: ea40 009c orrcs.w r0, r0, ip, lsr #2
80008c0: 085b lsrs r3, r3, #1
80008c2: ea4f 0232 mov.w r2, r2, rrx
80008c6: ebb6 0e02 subs.w lr, r6, r2
80008ca: eb75 0e03 sbcs.w lr, r5, r3
80008ce: bf22 ittt cs
80008d0: 1ab6 subcs r6, r6, r2
80008d2: 4675 movcs r5, lr
80008d4: ea40 00dc orrcs.w r0, r0, ip, lsr #3
80008d8: ea55 0e06 orrs.w lr, r5, r6
80008dc: d018 beq.n 8000910 <__aeabi_ddiv+0x114>
80008de: ea4f 1505 mov.w r5, r5, lsl #4
80008e2: ea45 7516 orr.w r5, r5, r6, lsr #28
80008e6: ea4f 1606 mov.w r6, r6, lsl #4
80008ea: ea4f 03c3 mov.w r3, r3, lsl #3
80008ee: ea43 7352 orr.w r3, r3, r2, lsr #29
80008f2: ea4f 02c2 mov.w r2, r2, lsl #3
80008f6: ea5f 1c1c movs.w ip, ip, lsr #4
80008fa: d1c0 bne.n 800087e <__aeabi_ddiv+0x82>
80008fc: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000900: d10b bne.n 800091a <__aeabi_ddiv+0x11e>
8000902: ea41 0100 orr.w r1, r1, r0
8000906: f04f 0000 mov.w r0, #0
800090a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
800090e: e7b6 b.n 800087e <__aeabi_ddiv+0x82>
8000910: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000914: bf04 itt eq
8000916: 4301 orreq r1, r0
8000918: 2000 moveq r0, #0
800091a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
800091e: bf88 it hi
8000920: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
8000924: f63f aeaf bhi.w 8000686 <__aeabi_dmul+0xde>
8000928: ebb5 0c03 subs.w ip, r5, r3
800092c: bf04 itt eq
800092e: ebb6 0c02 subseq.w ip, r6, r2
8000932: ea5f 0c50 movseq.w ip, r0, lsr #1
8000936: f150 0000 adcs.w r0, r0, #0
800093a: eb41 5104 adc.w r1, r1, r4, lsl #20
800093e: bd70 pop {r4, r5, r6, pc}
8000940: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
8000944: ea4e 3111 orr.w r1, lr, r1, lsr #12
8000948: eb14 045c adds.w r4, r4, ip, lsr #1
800094c: bfc2 ittt gt
800094e: ebd4 050c rsbsgt r5, r4, ip
8000952: ea41 5104 orrgt.w r1, r1, r4, lsl #20
8000956: bd70 popgt {r4, r5, r6, pc}
8000958: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
800095c: f04f 0e00 mov.w lr, #0
8000960: 3c01 subs r4, #1
8000962: e690 b.n 8000686 <__aeabi_dmul+0xde>
8000964: ea45 0e06 orr.w lr, r5, r6
8000968: e68d b.n 8000686 <__aeabi_dmul+0xde>
800096a: ea0c 5513 and.w r5, ip, r3, lsr #20
800096e: ea94 0f0c teq r4, ip
8000972: bf08 it eq
8000974: ea95 0f0c teqeq r5, ip
8000978: f43f af3b beq.w 80007f2 <__aeabi_dmul+0x24a>
800097c: ea94 0f0c teq r4, ip
8000980: d10a bne.n 8000998 <__aeabi_ddiv+0x19c>
8000982: ea50 3401 orrs.w r4, r0, r1, lsl #12
8000986: f47f af34 bne.w 80007f2 <__aeabi_dmul+0x24a>
800098a: ea95 0f0c teq r5, ip
800098e: f47f af25 bne.w 80007dc <__aeabi_dmul+0x234>
8000992: 4610 mov r0, r2
8000994: 4619 mov r1, r3
8000996: e72c b.n 80007f2 <__aeabi_dmul+0x24a>
8000998: ea95 0f0c teq r5, ip
800099c: d106 bne.n 80009ac <__aeabi_ddiv+0x1b0>
800099e: ea52 3503 orrs.w r5, r2, r3, lsl #12
80009a2: f43f aefd beq.w 80007a0 <__aeabi_dmul+0x1f8>
80009a6: 4610 mov r0, r2
80009a8: 4619 mov r1, r3
80009aa: e722 b.n 80007f2 <__aeabi_dmul+0x24a>
80009ac: ea50 0641 orrs.w r6, r0, r1, lsl #1
80009b0: bf18 it ne
80009b2: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80009b6: f47f aec5 bne.w 8000744 <__aeabi_dmul+0x19c>
80009ba: ea50 0441 orrs.w r4, r0, r1, lsl #1
80009be: f47f af0d bne.w 80007dc <__aeabi_dmul+0x234>
80009c2: ea52 0543 orrs.w r5, r2, r3, lsl #1
80009c6: f47f aeeb bne.w 80007a0 <__aeabi_dmul+0x1f8>
80009ca: e712 b.n 80007f2 <__aeabi_dmul+0x24a>
080009cc <__gedf2>:
80009cc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff
80009d0: e006 b.n 80009e0 <__cmpdf2+0x4>
80009d2: bf00 nop
080009d4 <__ledf2>:
80009d4: f04f 0c01 mov.w ip, #1
80009d8: e002 b.n 80009e0 <__cmpdf2+0x4>
80009da: bf00 nop
080009dc <__cmpdf2>:
80009dc: f04f 0c01 mov.w ip, #1
80009e0: f84d cd04 str.w ip, [sp, #-4]!
80009e4: ea4f 0c41 mov.w ip, r1, lsl #1
80009e8: ea7f 5c6c mvns.w ip, ip, asr #21
80009ec: ea4f 0c43 mov.w ip, r3, lsl #1
80009f0: bf18 it ne
80009f2: ea7f 5c6c mvnsne.w ip, ip, asr #21
80009f6: d01b beq.n 8000a30 <__cmpdf2+0x54>
80009f8: b001 add sp, #4
80009fa: ea50 0c41 orrs.w ip, r0, r1, lsl #1
80009fe: bf0c ite eq
8000a00: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
8000a04: ea91 0f03 teqne r1, r3
8000a08: bf02 ittt eq
8000a0a: ea90 0f02 teqeq r0, r2
8000a0e: 2000 moveq r0, #0
8000a10: 4770 bxeq lr
8000a12: f110 0f00 cmn.w r0, #0
8000a16: ea91 0f03 teq r1, r3
8000a1a: bf58 it pl
8000a1c: 4299 cmppl r1, r3
8000a1e: bf08 it eq
8000a20: 4290 cmpeq r0, r2
8000a22: bf2c ite cs
8000a24: 17d8 asrcs r0, r3, #31
8000a26: ea6f 70e3 mvncc.w r0, r3, asr #31
8000a2a: f040 0001 orr.w r0, r0, #1
8000a2e: 4770 bx lr
8000a30: ea4f 0c41 mov.w ip, r1, lsl #1
8000a34: ea7f 5c6c mvns.w ip, ip, asr #21
8000a38: d102 bne.n 8000a40 <__cmpdf2+0x64>
8000a3a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
8000a3e: d107 bne.n 8000a50 <__cmpdf2+0x74>
8000a40: ea4f 0c43 mov.w ip, r3, lsl #1
8000a44: ea7f 5c6c mvns.w ip, ip, asr #21
8000a48: d1d6 bne.n 80009f8 <__cmpdf2+0x1c>
8000a4a: ea52 3c03 orrs.w ip, r2, r3, lsl #12
8000a4e: d0d3 beq.n 80009f8 <__cmpdf2+0x1c>
8000a50: f85d 0b04 ldr.w r0, [sp], #4
8000a54: 4770 bx lr
8000a56: bf00 nop
08000a58 <__aeabi_cdrcmple>:
8000a58: 4684 mov ip, r0
8000a5a: 4610 mov r0, r2
8000a5c: 4662 mov r2, ip
8000a5e: 468c mov ip, r1
8000a60: 4619 mov r1, r3
8000a62: 4663 mov r3, ip
8000a64: e000 b.n 8000a68 <__aeabi_cdcmpeq>
8000a66: bf00 nop
08000a68 <__aeabi_cdcmpeq>:
8000a68: b501 push {r0, lr}
8000a6a: f7ff ffb7 bl 80009dc <__cmpdf2>
8000a6e: 2800 cmp r0, #0
8000a70: bf48 it mi
8000a72: f110 0f00 cmnmi.w r0, #0
8000a76: bd01 pop {r0, pc}
08000a78 <__aeabi_dcmpeq>:
8000a78: f84d ed08 str.w lr, [sp, #-8]!
8000a7c: f7ff fff4 bl 8000a68 <__aeabi_cdcmpeq>
8000a80: bf0c ite eq
8000a82: 2001 moveq r0, #1
8000a84: 2000 movne r0, #0
8000a86: f85d fb08 ldr.w pc, [sp], #8
8000a8a: bf00 nop
08000a8c <__aeabi_dcmplt>:
8000a8c: f84d ed08 str.w lr, [sp, #-8]!
8000a90: f7ff ffea bl 8000a68 <__aeabi_cdcmpeq>
8000a94: bf34 ite cc
8000a96: 2001 movcc r0, #1
8000a98: 2000 movcs r0, #0
8000a9a: f85d fb08 ldr.w pc, [sp], #8
8000a9e: bf00 nop
08000aa0 <__aeabi_dcmple>:
8000aa0: f84d ed08 str.w lr, [sp, #-8]!
8000aa4: f7ff ffe0 bl 8000a68 <__aeabi_cdcmpeq>
8000aa8: bf94 ite ls
8000aaa: 2001 movls r0, #1
8000aac: 2000 movhi r0, #0
8000aae: f85d fb08 ldr.w pc, [sp], #8
8000ab2: bf00 nop
08000ab4 <__aeabi_dcmpge>:
8000ab4: f84d ed08 str.w lr, [sp, #-8]!
8000ab8: f7ff ffce bl 8000a58 <__aeabi_cdrcmple>
8000abc: bf94 ite ls
8000abe: 2001 movls r0, #1
8000ac0: 2000 movhi r0, #0
8000ac2: f85d fb08 ldr.w pc, [sp], #8
8000ac6: bf00 nop
08000ac8 <__aeabi_dcmpgt>:
8000ac8: f84d ed08 str.w lr, [sp, #-8]!
8000acc: f7ff ffc4 bl 8000a58 <__aeabi_cdrcmple>
8000ad0: bf34 ite cc
8000ad2: 2001 movcc r0, #1
8000ad4: 2000 movcs r0, #0
8000ad6: f85d fb08 ldr.w pc, [sp], #8
8000ada: bf00 nop
08000adc <__aeabi_dcmpun>:
8000adc: ea4f 0c41 mov.w ip, r1, lsl #1
8000ae0: ea7f 5c6c mvns.w ip, ip, asr #21
8000ae4: d102 bne.n 8000aec <__aeabi_dcmpun+0x10>
8000ae6: ea50 3c01 orrs.w ip, r0, r1, lsl #12
8000aea: d10a bne.n 8000b02 <__aeabi_dcmpun+0x26>
8000aec: ea4f 0c43 mov.w ip, r3, lsl #1
8000af0: ea7f 5c6c mvns.w ip, ip, asr #21
8000af4: d102 bne.n 8000afc <__aeabi_dcmpun+0x20>
8000af6: ea52 3c03 orrs.w ip, r2, r3, lsl #12
8000afa: d102 bne.n 8000b02 <__aeabi_dcmpun+0x26>
8000afc: f04f 0000 mov.w r0, #0
8000b00: 4770 bx lr
8000b02: f04f 0001 mov.w r0, #1
8000b06: 4770 bx lr
08000b08 <__aeabi_d2iz>:
8000b08: ea4f 0241 mov.w r2, r1, lsl #1
8000b0c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000b10: d215 bcs.n 8000b3e <__aeabi_d2iz+0x36>
8000b12: d511 bpl.n 8000b38 <__aeabi_d2iz+0x30>
8000b14: f46f 7378 mvn.w r3, #992 @ 0x3e0
8000b18: ebb3 5262 subs.w r2, r3, r2, asr #21
8000b1c: d912 bls.n 8000b44 <__aeabi_d2iz+0x3c>
8000b1e: ea4f 23c1 mov.w r3, r1, lsl #11
8000b22: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000b26: ea43 5350 orr.w r3, r3, r0, lsr #21
8000b2a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
8000b2e: fa23 f002 lsr.w r0, r3, r2
8000b32: bf18 it ne
8000b34: 4240 negne r0, r0
8000b36: 4770 bx lr
8000b38: f04f 0000 mov.w r0, #0
8000b3c: 4770 bx lr
8000b3e: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000b42: d105 bne.n 8000b50 <__aeabi_d2iz+0x48>
8000b44: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
8000b48: bf08 it eq
8000b4a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
8000b4e: 4770 bx lr
8000b50: f04f 0000 mov.w r0, #0
8000b54: 4770 bx lr
8000b56: bf00 nop
08000b58 <__aeabi_d2uiz>:
8000b58: 004a lsls r2, r1, #1
8000b5a: d211 bcs.n 8000b80 <__aeabi_d2uiz+0x28>
8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000b60: d211 bcs.n 8000b86 <__aeabi_d2uiz+0x2e>
8000b62: d50d bpl.n 8000b80 <__aeabi_d2uiz+0x28>
8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0
8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21
8000b6c: d40e bmi.n 8000b8c <__aeabi_d2uiz+0x34>
8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11
8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21
8000b7a: fa23 f002 lsr.w r0, r3, r2
8000b7e: 4770 bx lr
8000b80: f04f 0000 mov.w r0, #0
8000b84: 4770 bx lr
8000b86: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000b8a: d102 bne.n 8000b92 <__aeabi_d2uiz+0x3a>
8000b8c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000b90: 4770 bx lr
8000b92: f04f 0000 mov.w r0, #0
8000b96: 4770 bx lr
08000b98 <__aeabi_d2f>:
8000b98: ea4f 0241 mov.w r2, r1, lsl #1
8000b9c: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000
8000ba0: bf24 itt cs
8000ba2: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000
8000ba6: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000
8000baa: d90d bls.n 8000bc8 <__aeabi_d2f+0x30>
8000bac: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000bb0: ea4f 02c0 mov.w r2, r0, lsl #3
8000bb4: ea4c 7050 orr.w r0, ip, r0, lsr #29
8000bb8: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000
8000bbc: eb40 0083 adc.w r0, r0, r3, lsl #2
8000bc0: bf08 it eq
8000bc2: f020 0001 biceq.w r0, r0, #1
8000bc6: 4770 bx lr
8000bc8: f011 4f80 tst.w r1, #1073741824 @ 0x40000000
8000bcc: d121 bne.n 8000c12 <__aeabi_d2f+0x7a>
8000bce: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000
8000bd2: bfbc itt lt
8000bd4: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000
8000bd8: 4770 bxlt lr
8000bda: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000bde: ea4f 5252 mov.w r2, r2, lsr #21
8000be2: f1c2 0218 rsb r2, r2, #24
8000be6: f1c2 0c20 rsb ip, r2, #32
8000bea: fa10 f30c lsls.w r3, r0, ip
8000bee: fa20 f002 lsr.w r0, r0, r2
8000bf2: bf18 it ne
8000bf4: f040 0001 orrne.w r0, r0, #1
8000bf8: ea4f 23c1 mov.w r3, r1, lsl #11
8000bfc: ea4f 23d3 mov.w r3, r3, lsr #11
8000c00: fa03 fc0c lsl.w ip, r3, ip
8000c04: ea40 000c orr.w r0, r0, ip
8000c08: fa23 f302 lsr.w r3, r3, r2
8000c0c: ea4f 0343 mov.w r3, r3, lsl #1
8000c10: e7cc b.n 8000bac <__aeabi_d2f+0x14>
8000c12: ea7f 5362 mvns.w r3, r2, asr #21
8000c16: d107 bne.n 8000c28 <__aeabi_d2f+0x90>
8000c18: ea50 3301 orrs.w r3, r0, r1, lsl #12
8000c1c: bf1e ittt ne
8000c1e: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000
8000c22: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000
8000c26: 4770 bxne lr
8000c28: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000
8000c2c: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000c30: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000c34: 4770 bx lr
8000c36: bf00 nop
08000c38 <__aeabi_d2lz>:
8000c38: b538 push {r3, r4, r5, lr}
8000c3a: 2200 movs r2, #0
8000c3c: 2300 movs r3, #0
8000c3e: 4604 mov r4, r0
8000c40: 460d mov r5, r1
8000c42: f7ff ff23 bl 8000a8c <__aeabi_dcmplt>
8000c46: b928 cbnz r0, 8000c54 <__aeabi_d2lz+0x1c>
8000c48: 4620 mov r0, r4
8000c4a: 4629 mov r1, r5
8000c4c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
8000c50: f000 b80a b.w 8000c68 <__aeabi_d2ulz>
8000c54: 4620 mov r0, r4
8000c56: f105 4100 add.w r1, r5, #2147483648 @ 0x80000000
8000c5a: f000 f805 bl 8000c68 <__aeabi_d2ulz>
8000c5e: 4240 negs r0, r0
8000c60: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000c64: bd38 pop {r3, r4, r5, pc}
8000c66: bf00 nop
08000c68 <__aeabi_d2ulz>:
8000c68: b5d0 push {r4, r6, r7, lr}
8000c6a: 4b0c ldr r3, [pc, #48] @ (8000c9c <__aeabi_d2ulz+0x34>)
8000c6c: 2200 movs r2, #0
8000c6e: 4606 mov r6, r0
8000c70: 460f mov r7, r1
8000c72: f7ff fc99 bl 80005a8 <__aeabi_dmul>
8000c76: f7ff ff6f bl 8000b58 <__aeabi_d2uiz>
8000c7a: 4604 mov r4, r0
8000c7c: f7ff fc1a bl 80004b4 <__aeabi_ui2d>
8000c80: 4b07 ldr r3, [pc, #28] @ (8000ca0 <__aeabi_d2ulz+0x38>)
8000c82: 2200 movs r2, #0
8000c84: f7ff fc90 bl 80005a8 <__aeabi_dmul>
8000c88: 4602 mov r2, r0
8000c8a: 460b mov r3, r1
8000c8c: 4630 mov r0, r6
8000c8e: 4639 mov r1, r7
8000c90: f7ff fad2 bl 8000238 <__aeabi_dsub>
8000c94: f7ff ff60 bl 8000b58 <__aeabi_d2uiz>
8000c98: 4621 mov r1, r4
8000c9a: bdd0 pop {r4, r6, r7, pc}
8000c9c: 3df00000 .word 0x3df00000
8000ca0: 41f00000 .word 0x41f00000
08000ca4 <MadgwickAHRS_init>:
float invSqrt(float x);
//====================================================================================================
// Functions
void MadgwickAHRS_init (MadgwickAHRS_Filter* filter, float beta, float sample_freq) {
8000ca4: b480 push {r7}
8000ca6: b085 sub sp, #20
8000ca8: af00 add r7, sp, #0
8000caa: 60f8 str r0, [r7, #12]
8000cac: ed87 0a02 vstr s0, [r7, #8]
8000cb0: edc7 0a01 vstr s1, [r7, #4]
filter->q[0] = 1.0f; // qw
8000cb4: 68fb ldr r3, [r7, #12]
8000cb6: f04f 527e mov.w r2, #1065353216 @ 0x3f800000
8000cba: 601a str r2, [r3, #0]
filter->q[1] = 0.0f; // qx
8000cbc: 68fb ldr r3, [r7, #12]
8000cbe: f04f 0200 mov.w r2, #0
8000cc2: 605a str r2, [r3, #4]
filter->q[2] = 0.0f; // qy
8000cc4: 68fb ldr r3, [r7, #12]
8000cc6: f04f 0200 mov.w r2, #0
8000cca: 609a str r2, [r3, #8]
filter->q[3] = 0.0f; // qz
8000ccc: 68fb ldr r3, [r7, #12]
8000cce: f04f 0200 mov.w r2, #0
8000cd2: 60da str r2, [r3, #12]
filter->beta = beta;
8000cd4: 68fb ldr r3, [r7, #12]
8000cd6: 68ba ldr r2, [r7, #8]
8000cd8: 611a str r2, [r3, #16]
filter->sample_freq = sample_freq;
8000cda: 68fb ldr r3, [r7, #12]
8000cdc: 687a ldr r2, [r7, #4]
8000cde: 615a str r2, [r3, #20]
}
8000ce0: bf00 nop
8000ce2: 3714 adds r7, #20
8000ce4: 46bd mov sp, r7
8000ce6: f85d 7b04 ldr.w r7, [sp], #4
8000cea: 4770 bx lr
08000cec <MadgwickAHRS_update_IMU>:
}
//---------------------------------------------------------------------------------------------------
// IMU algorithm update
void MadgwickAHRS_update_IMU(MadgwickAHRS_Filter* filter, float gx, float gy, float gz, float ax, float ay, float az) {
8000cec: b580 push {r7, lr}
8000cee: b0a2 sub sp, #136 @ 0x88
8000cf0: af00 add r7, sp, #0
8000cf2: 61f8 str r0, [r7, #28]
8000cf4: ed87 0a06 vstr s0, [r7, #24]
8000cf8: edc7 0a05 vstr s1, [r7, #20]
8000cfc: ed87 1a04 vstr s2, [r7, #16]
8000d00: edc7 1a03 vstr s3, [r7, #12]
8000d04: ed87 2a02 vstr s4, [r7, #8]
8000d08: edc7 2a01 vstr s5, [r7, #4]
float q[4] = {filter->q[0], filter->q[1], filter->q[2], filter->q[3]};
8000d0c: 69fb ldr r3, [r7, #28]
8000d0e: 681b ldr r3, [r3, #0]
8000d10: 633b str r3, [r7, #48] @ 0x30
8000d12: 69fb ldr r3, [r7, #28]
8000d14: 685b ldr r3, [r3, #4]
8000d16: 637b str r3, [r7, #52] @ 0x34
8000d18: 69fb ldr r3, [r7, #28]
8000d1a: 689b ldr r3, [r3, #8]
8000d1c: 63bb str r3, [r7, #56] @ 0x38
8000d1e: 69fb ldr r3, [r7, #28]
8000d20: 68db ldr r3, [r3, #12]
8000d22: 63fb str r3, [r7, #60] @ 0x3c
float s0, s1, s2, s3;
float qDot[4];
float _2q0, _2q1, _2q2, _2q3, _4q0, _4q1, _4q2 ,_8q1, _8q2, q0q0, q1q1, q2q2, q3q3;
// Rate of change of quaternion from gyroscope
qDot[0] = 0.5f * (-q[1] * gx - q[2] * gy - q[3] * gz);
8000d24: edd7 7a0d vldr s15, [r7, #52] @ 0x34
8000d28: eeb1 7a67 vneg.f32 s14, s15
8000d2c: edd7 7a06 vldr s15, [r7, #24]
8000d30: ee27 7a27 vmul.f32 s14, s14, s15
8000d34: edd7 6a0e vldr s13, [r7, #56] @ 0x38
8000d38: edd7 7a05 vldr s15, [r7, #20]
8000d3c: ee66 7aa7 vmul.f32 s15, s13, s15
8000d40: ee37 7a67 vsub.f32 s14, s14, s15
8000d44: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
8000d48: edd7 7a04 vldr s15, [r7, #16]
8000d4c: ee66 7aa7 vmul.f32 s15, s13, s15
8000d50: ee77 7a67 vsub.f32 s15, s14, s15
8000d54: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
8000d58: ee67 7a87 vmul.f32 s15, s15, s14
8000d5c: edc7 7a08 vstr s15, [r7, #32]
qDot[1] = 0.5f * (q[0] * gx + q[2] * gz - q[3] * gy);
8000d60: ed97 7a0c vldr s14, [r7, #48] @ 0x30
8000d64: edd7 7a06 vldr s15, [r7, #24]
8000d68: ee27 7a27 vmul.f32 s14, s14, s15
8000d6c: edd7 6a0e vldr s13, [r7, #56] @ 0x38
8000d70: edd7 7a04 vldr s15, [r7, #16]
8000d74: ee66 7aa7 vmul.f32 s15, s13, s15
8000d78: ee37 7a27 vadd.f32 s14, s14, s15
8000d7c: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
8000d80: edd7 7a05 vldr s15, [r7, #20]
8000d84: ee66 7aa7 vmul.f32 s15, s13, s15
8000d88: ee77 7a67 vsub.f32 s15, s14, s15
8000d8c: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
8000d90: ee67 7a87 vmul.f32 s15, s15, s14
8000d94: edc7 7a09 vstr s15, [r7, #36] @ 0x24
qDot[2] = 0.5f * (q[0] * gy - q[1] * gz + q[3] * gx);
8000d98: ed97 7a0c vldr s14, [r7, #48] @ 0x30
8000d9c: edd7 7a05 vldr s15, [r7, #20]
8000da0: ee27 7a27 vmul.f32 s14, s14, s15
8000da4: edd7 6a0d vldr s13, [r7, #52] @ 0x34
8000da8: edd7 7a04 vldr s15, [r7, #16]
8000dac: ee66 7aa7 vmul.f32 s15, s13, s15
8000db0: ee37 7a67 vsub.f32 s14, s14, s15
8000db4: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
8000db8: edd7 7a06 vldr s15, [r7, #24]
8000dbc: ee66 7aa7 vmul.f32 s15, s13, s15
8000dc0: ee77 7a27 vadd.f32 s15, s14, s15
8000dc4: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
8000dc8: ee67 7a87 vmul.f32 s15, s15, s14
8000dcc: edc7 7a0a vstr s15, [r7, #40] @ 0x28
qDot[3] = 0.5f * (q[0] * gz + q[1] * gy - q[2] * gx);
8000dd0: ed97 7a0c vldr s14, [r7, #48] @ 0x30
8000dd4: edd7 7a04 vldr s15, [r7, #16]
8000dd8: ee27 7a27 vmul.f32 s14, s14, s15
8000ddc: edd7 6a0d vldr s13, [r7, #52] @ 0x34
8000de0: edd7 7a05 vldr s15, [r7, #20]
8000de4: ee66 7aa7 vmul.f32 s15, s13, s15
8000de8: ee37 7a27 vadd.f32 s14, s14, s15
8000dec: edd7 6a0e vldr s13, [r7, #56] @ 0x38
8000df0: edd7 7a06 vldr s15, [r7, #24]
8000df4: ee66 7aa7 vmul.f32 s15, s13, s15
8000df8: ee77 7a67 vsub.f32 s15, s14, s15
8000dfc: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
8000e00: ee67 7a87 vmul.f32 s15, s15, s14
8000e04: edc7 7a0b vstr s15, [r7, #44] @ 0x2c
// Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation)
if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {
8000e08: edd7 7a03 vldr s15, [r7, #12]
8000e0c: eef5 7a40 vcmp.f32 s15, #0.0
8000e10: eef1 fa10 vmrs APSR_nzcv, fpscr
8000e14: d10e bne.n 8000e34 <MadgwickAHRS_update_IMU+0x148>
8000e16: edd7 7a02 vldr s15, [r7, #8]
8000e1a: eef5 7a40 vcmp.f32 s15, #0.0
8000e1e: eef1 fa10 vmrs APSR_nzcv, fpscr
8000e22: d107 bne.n 8000e34 <MadgwickAHRS_update_IMU+0x148>
8000e24: edd7 7a01 vldr s15, [r7, #4]
8000e28: eef5 7a40 vcmp.f32 s15, #0.0
8000e2c: eef1 fa10 vmrs APSR_nzcv, fpscr
8000e30: f000 81c6 beq.w 80011c0 <MadgwickAHRS_update_IMU+0x4d4>
// Normalise accelerometer measurement
recipNorm = invSqrt(ax * ax + ay * ay + az * az);
8000e34: edd7 7a03 vldr s15, [r7, #12]
8000e38: ee27 7aa7 vmul.f32 s14, s15, s15
8000e3c: edd7 7a02 vldr s15, [r7, #8]
8000e40: ee67 7aa7 vmul.f32 s15, s15, s15
8000e44: ee37 7a27 vadd.f32 s14, s14, s15
8000e48: edd7 7a01 vldr s15, [r7, #4]
8000e4c: ee67 7aa7 vmul.f32 s15, s15, s15
8000e50: ee77 7a27 vadd.f32 s15, s14, s15
8000e54: eeb0 0a67 vmov.f32 s0, s15
8000e58: f000 fa4a bl 80012f0 <invSqrt>
8000e5c: ed87 0a21 vstr s0, [r7, #132] @ 0x84
ax *= recipNorm;
8000e60: ed97 7a03 vldr s14, [r7, #12]
8000e64: edd7 7a21 vldr s15, [r7, #132] @ 0x84
8000e68: ee67 7a27 vmul.f32 s15, s14, s15
8000e6c: edc7 7a03 vstr s15, [r7, #12]
ay *= recipNorm;
8000e70: ed97 7a02 vldr s14, [r7, #8]
8000e74: edd7 7a21 vldr s15, [r7, #132] @ 0x84
8000e78: ee67 7a27 vmul.f32 s15, s14, s15
8000e7c: edc7 7a02 vstr s15, [r7, #8]
az *= recipNorm;
8000e80: ed97 7a01 vldr s14, [r7, #4]
8000e84: edd7 7a21 vldr s15, [r7, #132] @ 0x84
8000e88: ee67 7a27 vmul.f32 s15, s14, s15
8000e8c: edc7 7a01 vstr s15, [r7, #4]
// Auxiliary variables to avoid repeated arithmetic
_2q0 = 2.0f * q[0];
8000e90: edd7 7a0c vldr s15, [r7, #48] @ 0x30
8000e94: ee77 7aa7 vadd.f32 s15, s15, s15
8000e98: edc7 7a20 vstr s15, [r7, #128] @ 0x80
_2q1 = 2.0f * q[1];
8000e9c: edd7 7a0d vldr s15, [r7, #52] @ 0x34
8000ea0: ee77 7aa7 vadd.f32 s15, s15, s15
8000ea4: edc7 7a1f vstr s15, [r7, #124] @ 0x7c
_2q2 = 2.0f * q[2];
8000ea8: edd7 7a0e vldr s15, [r7, #56] @ 0x38
8000eac: ee77 7aa7 vadd.f32 s15, s15, s15
8000eb0: edc7 7a1e vstr s15, [r7, #120] @ 0x78
_2q3 = 2.0f * q[3];
8000eb4: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
8000eb8: ee77 7aa7 vadd.f32 s15, s15, s15
8000ebc: edc7 7a1d vstr s15, [r7, #116] @ 0x74
_4q0 = 4.0f * q[0];
8000ec0: edd7 7a0c vldr s15, [r7, #48] @ 0x30
8000ec4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
8000ec8: ee67 7a87 vmul.f32 s15, s15, s14
8000ecc: edc7 7a1c vstr s15, [r7, #112] @ 0x70
_4q1 = 4.0f * q[1];
8000ed0: edd7 7a0d vldr s15, [r7, #52] @ 0x34
8000ed4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
8000ed8: ee67 7a87 vmul.f32 s15, s15, s14
8000edc: edc7 7a1b vstr s15, [r7, #108] @ 0x6c
_4q2 = 4.0f * q[2];
8000ee0: edd7 7a0e vldr s15, [r7, #56] @ 0x38
8000ee4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
8000ee8: ee67 7a87 vmul.f32 s15, s15, s14
8000eec: edc7 7a1a vstr s15, [r7, #104] @ 0x68
_8q1 = 8.0f * q[1];
8000ef0: edd7 7a0d vldr s15, [r7, #52] @ 0x34
8000ef4: eeb2 7a00 vmov.f32 s14, #32 @ 0x41000000 8.0
8000ef8: ee67 7a87 vmul.f32 s15, s15, s14
8000efc: edc7 7a19 vstr s15, [r7, #100] @ 0x64
_8q2 = 8.0f * q[2];
8000f00: edd7 7a0e vldr s15, [r7, #56] @ 0x38
8000f04: eeb2 7a00 vmov.f32 s14, #32 @ 0x41000000 8.0
8000f08: ee67 7a87 vmul.f32 s15, s15, s14
8000f0c: edc7 7a18 vstr s15, [r7, #96] @ 0x60
q0q0 = q[0] * q[0];
8000f10: ed97 7a0c vldr s14, [r7, #48] @ 0x30
8000f14: edd7 7a0c vldr s15, [r7, #48] @ 0x30
8000f18: ee67 7a27 vmul.f32 s15, s14, s15
8000f1c: edc7 7a17 vstr s15, [r7, #92] @ 0x5c
q1q1 = q[1] * q[1];
8000f20: ed97 7a0d vldr s14, [r7, #52] @ 0x34
8000f24: edd7 7a0d vldr s15, [r7, #52] @ 0x34
8000f28: ee67 7a27 vmul.f32 s15, s14, s15
8000f2c: edc7 7a16 vstr s15, [r7, #88] @ 0x58
q2q2 = q[2] * q[2];
8000f30: ed97 7a0e vldr s14, [r7, #56] @ 0x38
8000f34: edd7 7a0e vldr s15, [r7, #56] @ 0x38
8000f38: ee67 7a27 vmul.f32 s15, s14, s15
8000f3c: edc7 7a15 vstr s15, [r7, #84] @ 0x54
q3q3 = q[3] * q[3];
8000f40: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
8000f44: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
8000f48: ee67 7a27 vmul.f32 s15, s14, s15
8000f4c: edc7 7a14 vstr s15, [r7, #80] @ 0x50
// Gradient decent algorithm corrective step
s0 = _4q0 * q2q2 + _2q2 * ax + _4q0 * q1q1 - _2q1 * ay;
8000f50: ed97 7a1c vldr s14, [r7, #112] @ 0x70
8000f54: edd7 7a15 vldr s15, [r7, #84] @ 0x54
8000f58: ee27 7a27 vmul.f32 s14, s14, s15
8000f5c: edd7 6a1e vldr s13, [r7, #120] @ 0x78
8000f60: edd7 7a03 vldr s15, [r7, #12]
8000f64: ee66 7aa7 vmul.f32 s15, s13, s15
8000f68: ee37 7a27 vadd.f32 s14, s14, s15
8000f6c: edd7 6a1c vldr s13, [r7, #112] @ 0x70
8000f70: edd7 7a16 vldr s15, [r7, #88] @ 0x58
8000f74: ee66 7aa7 vmul.f32 s15, s13, s15
8000f78: ee37 7a27 vadd.f32 s14, s14, s15
8000f7c: edd7 6a1f vldr s13, [r7, #124] @ 0x7c
8000f80: edd7 7a02 vldr s15, [r7, #8]
8000f84: ee66 7aa7 vmul.f32 s15, s13, s15
8000f88: ee77 7a67 vsub.f32 s15, s14, s15
8000f8c: edc7 7a13 vstr s15, [r7, #76] @ 0x4c
s1 = _4q1 * q3q3 - _2q3 * ax + 4.0f * q0q0 * q[1] - _2q0 * ay - _4q1 + _8q1 * q1q1 + _8q1 * q2q2 + _4q1 * az;
8000f90: ed97 7a1b vldr s14, [r7, #108] @ 0x6c
8000f94: edd7 7a14 vldr s15, [r7, #80] @ 0x50
8000f98: ee27 7a27 vmul.f32 s14, s14, s15
8000f9c: edd7 6a1d vldr s13, [r7, #116] @ 0x74
8000fa0: edd7 7a03 vldr s15, [r7, #12]
8000fa4: ee66 7aa7 vmul.f32 s15, s13, s15
8000fa8: ee37 7a67 vsub.f32 s14, s14, s15
8000fac: edd7 7a17 vldr s15, [r7, #92] @ 0x5c
8000fb0: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0
8000fb4: ee67 6aa6 vmul.f32 s13, s15, s13
8000fb8: edd7 7a0d vldr s15, [r7, #52] @ 0x34
8000fbc: ee66 7aa7 vmul.f32 s15, s13, s15
8000fc0: ee37 7a27 vadd.f32 s14, s14, s15
8000fc4: edd7 6a20 vldr s13, [r7, #128] @ 0x80
8000fc8: edd7 7a02 vldr s15, [r7, #8]
8000fcc: ee66 7aa7 vmul.f32 s15, s13, s15
8000fd0: ee37 7a67 vsub.f32 s14, s14, s15
8000fd4: edd7 7a1b vldr s15, [r7, #108] @ 0x6c
8000fd8: ee37 7a67 vsub.f32 s14, s14, s15
8000fdc: edd7 6a19 vldr s13, [r7, #100] @ 0x64
8000fe0: edd7 7a16 vldr s15, [r7, #88] @ 0x58
8000fe4: ee66 7aa7 vmul.f32 s15, s13, s15
8000fe8: ee37 7a27 vadd.f32 s14, s14, s15
8000fec: edd7 6a19 vldr s13, [r7, #100] @ 0x64
8000ff0: edd7 7a15 vldr s15, [r7, #84] @ 0x54
8000ff4: ee66 7aa7 vmul.f32 s15, s13, s15
8000ff8: ee37 7a27 vadd.f32 s14, s14, s15
8000ffc: edd7 6a1b vldr s13, [r7, #108] @ 0x6c
8001000: edd7 7a01 vldr s15, [r7, #4]
8001004: ee66 7aa7 vmul.f32 s15, s13, s15
8001008: ee77 7a27 vadd.f32 s15, s14, s15
800100c: edc7 7a12 vstr s15, [r7, #72] @ 0x48
s2 = 4.0f * q0q0 * q[2] + _2q0 * ax + _4q2 * q3q3 - _2q3 * ay - _4q2 + _8q2 * q1q1 + _8q2 * q2q2 + _4q2 * az;
8001010: edd7 7a17 vldr s15, [r7, #92] @ 0x5c
8001014: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
8001018: ee27 7a87 vmul.f32 s14, s15, s14
800101c: edd7 7a0e vldr s15, [r7, #56] @ 0x38
8001020: ee27 7a27 vmul.f32 s14, s14, s15
8001024: edd7 6a20 vldr s13, [r7, #128] @ 0x80
8001028: edd7 7a03 vldr s15, [r7, #12]
800102c: ee66 7aa7 vmul.f32 s15, s13, s15
8001030: ee37 7a27 vadd.f32 s14, s14, s15
8001034: edd7 6a1a vldr s13, [r7, #104] @ 0x68
8001038: edd7 7a14 vldr s15, [r7, #80] @ 0x50
800103c: ee66 7aa7 vmul.f32 s15, s13, s15
8001040: ee37 7a27 vadd.f32 s14, s14, s15
8001044: edd7 6a1d vldr s13, [r7, #116] @ 0x74
8001048: edd7 7a02 vldr s15, [r7, #8]
800104c: ee66 7aa7 vmul.f32 s15, s13, s15
8001050: ee37 7a67 vsub.f32 s14, s14, s15
8001054: edd7 7a1a vldr s15, [r7, #104] @ 0x68
8001058: ee37 7a67 vsub.f32 s14, s14, s15
800105c: edd7 6a18 vldr s13, [r7, #96] @ 0x60
8001060: edd7 7a16 vldr s15, [r7, #88] @ 0x58
8001064: ee66 7aa7 vmul.f32 s15, s13, s15
8001068: ee37 7a27 vadd.f32 s14, s14, s15
800106c: edd7 6a18 vldr s13, [r7, #96] @ 0x60
8001070: edd7 7a15 vldr s15, [r7, #84] @ 0x54
8001074: ee66 7aa7 vmul.f32 s15, s13, s15
8001078: ee37 7a27 vadd.f32 s14, s14, s15
800107c: edd7 6a1a vldr s13, [r7, #104] @ 0x68
8001080: edd7 7a01 vldr s15, [r7, #4]
8001084: ee66 7aa7 vmul.f32 s15, s13, s15
8001088: ee77 7a27 vadd.f32 s15, s14, s15
800108c: edc7 7a11 vstr s15, [r7, #68] @ 0x44
s3 = 4.0f * q1q1 * q[3] - _2q1 * ax + 4.0f * q2q2 * q[3] - _2q2 * ay;
8001090: edd7 7a16 vldr s15, [r7, #88] @ 0x58
8001094: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0
8001098: ee27 7a87 vmul.f32 s14, s15, s14
800109c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
80010a0: ee27 7a27 vmul.f32 s14, s14, s15
80010a4: edd7 6a1f vldr s13, [r7, #124] @ 0x7c
80010a8: edd7 7a03 vldr s15, [r7, #12]
80010ac: ee66 7aa7 vmul.f32 s15, s13, s15
80010b0: ee37 7a67 vsub.f32 s14, s14, s15
80010b4: edd7 7a15 vldr s15, [r7, #84] @ 0x54
80010b8: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0
80010bc: ee67 6aa6 vmul.f32 s13, s15, s13
80010c0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
80010c4: ee66 7aa7 vmul.f32 s15, s13, s15
80010c8: ee37 7a27 vadd.f32 s14, s14, s15
80010cc: edd7 6a1e vldr s13, [r7, #120] @ 0x78
80010d0: edd7 7a02 vldr s15, [r7, #8]
80010d4: ee66 7aa7 vmul.f32 s15, s13, s15
80010d8: ee77 7a67 vsub.f32 s15, s14, s15
80010dc: edc7 7a10 vstr s15, [r7, #64] @ 0x40
recipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude
80010e0: edd7 7a13 vldr s15, [r7, #76] @ 0x4c
80010e4: ee27 7aa7 vmul.f32 s14, s15, s15
80010e8: edd7 7a12 vldr s15, [r7, #72] @ 0x48
80010ec: ee67 7aa7 vmul.f32 s15, s15, s15
80010f0: ee37 7a27 vadd.f32 s14, s14, s15
80010f4: edd7 7a11 vldr s15, [r7, #68] @ 0x44
80010f8: ee67 7aa7 vmul.f32 s15, s15, s15
80010fc: ee37 7a27 vadd.f32 s14, s14, s15
8001100: edd7 7a10 vldr s15, [r7, #64] @ 0x40
8001104: ee67 7aa7 vmul.f32 s15, s15, s15
8001108: ee77 7a27 vadd.f32 s15, s14, s15
800110c: eeb0 0a67 vmov.f32 s0, s15
8001110: f000 f8ee bl 80012f0 <invSqrt>
8001114: ed87 0a21 vstr s0, [r7, #132] @ 0x84
s0 *= recipNorm;
8001118: ed97 7a13 vldr s14, [r7, #76] @ 0x4c
800111c: edd7 7a21 vldr s15, [r7, #132] @ 0x84
8001120: ee67 7a27 vmul.f32 s15, s14, s15
8001124: edc7 7a13 vstr s15, [r7, #76] @ 0x4c
s1 *= recipNorm;
8001128: ed97 7a12 vldr s14, [r7, #72] @ 0x48
800112c: edd7 7a21 vldr s15, [r7, #132] @ 0x84
8001130: ee67 7a27 vmul.f32 s15, s14, s15
8001134: edc7 7a12 vstr s15, [r7, #72] @ 0x48
s2 *= recipNorm;
8001138: ed97 7a11 vldr s14, [r7, #68] @ 0x44
800113c: edd7 7a21 vldr s15, [r7, #132] @ 0x84
8001140: ee67 7a27 vmul.f32 s15, s14, s15
8001144: edc7 7a11 vstr s15, [r7, #68] @ 0x44
s3 *= recipNorm;
8001148: ed97 7a10 vldr s14, [r7, #64] @ 0x40
800114c: edd7 7a21 vldr s15, [r7, #132] @ 0x84
8001150: ee67 7a27 vmul.f32 s15, s14, s15
8001154: edc7 7a10 vstr s15, [r7, #64] @ 0x40
// Apply feedback step
qDot[0] -= filter->beta * s0;
8001158: ed97 7a08 vldr s14, [r7, #32]
800115c: 69fb ldr r3, [r7, #28]
800115e: edd3 6a04 vldr s13, [r3, #16]
8001162: edd7 7a13 vldr s15, [r7, #76] @ 0x4c
8001166: ee66 7aa7 vmul.f32 s15, s13, s15
800116a: ee77 7a67 vsub.f32 s15, s14, s15
800116e: edc7 7a08 vstr s15, [r7, #32]
qDot[1] -= filter->beta * s1;
8001172: ed97 7a09 vldr s14, [r7, #36] @ 0x24
8001176: 69fb ldr r3, [r7, #28]
8001178: edd3 6a04 vldr s13, [r3, #16]
800117c: edd7 7a12 vldr s15, [r7, #72] @ 0x48
8001180: ee66 7aa7 vmul.f32 s15, s13, s15
8001184: ee77 7a67 vsub.f32 s15, s14, s15
8001188: edc7 7a09 vstr s15, [r7, #36] @ 0x24
qDot[2] -= filter->beta * s2;
800118c: ed97 7a0a vldr s14, [r7, #40] @ 0x28
8001190: 69fb ldr r3, [r7, #28]
8001192: edd3 6a04 vldr s13, [r3, #16]
8001196: edd7 7a11 vldr s15, [r7, #68] @ 0x44
800119a: ee66 7aa7 vmul.f32 s15, s13, s15
800119e: ee77 7a67 vsub.f32 s15, s14, s15
80011a2: edc7 7a0a vstr s15, [r7, #40] @ 0x28
qDot[3] -= filter->beta * s3;
80011a6: ed97 7a0b vldr s14, [r7, #44] @ 0x2c
80011aa: 69fb ldr r3, [r7, #28]
80011ac: edd3 6a04 vldr s13, [r3, #16]
80011b0: edd7 7a10 vldr s15, [r7, #64] @ 0x40
80011b4: ee66 7aa7 vmul.f32 s15, s13, s15
80011b8: ee77 7a67 vsub.f32 s15, s14, s15
80011bc: edc7 7a0b vstr s15, [r7, #44] @ 0x2c
}
// Integrate rate of change of quaternion to yield quaternion
q[0] += qDot[0] * (1.0f / filter->sample_freq);
80011c0: ed97 7a0c vldr s14, [r7, #48] @ 0x30
80011c4: edd7 6a08 vldr s13, [r7, #32]
80011c8: 69fb ldr r3, [r7, #28]
80011ca: ed93 6a05 vldr s12, [r3, #20]
80011ce: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
80011d2: eec5 7a86 vdiv.f32 s15, s11, s12
80011d6: ee66 7aa7 vmul.f32 s15, s13, s15
80011da: ee77 7a27 vadd.f32 s15, s14, s15
80011de: edc7 7a0c vstr s15, [r7, #48] @ 0x30
q[1] += qDot[1] * (1.0f / filter->sample_freq);
80011e2: ed97 7a0d vldr s14, [r7, #52] @ 0x34
80011e6: edd7 6a09 vldr s13, [r7, #36] @ 0x24
80011ea: 69fb ldr r3, [r7, #28]
80011ec: ed93 6a05 vldr s12, [r3, #20]
80011f0: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
80011f4: eec5 7a86 vdiv.f32 s15, s11, s12
80011f8: ee66 7aa7 vmul.f32 s15, s13, s15
80011fc: ee77 7a27 vadd.f32 s15, s14, s15
8001200: edc7 7a0d vstr s15, [r7, #52] @ 0x34
q[2] += qDot[2] * (1.0f / filter->sample_freq);
8001204: ed97 7a0e vldr s14, [r7, #56] @ 0x38
8001208: edd7 6a0a vldr s13, [r7, #40] @ 0x28
800120c: 69fb ldr r3, [r7, #28]
800120e: ed93 6a05 vldr s12, [r3, #20]
8001212: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
8001216: eec5 7a86 vdiv.f32 s15, s11, s12
800121a: ee66 7aa7 vmul.f32 s15, s13, s15
800121e: ee77 7a27 vadd.f32 s15, s14, s15
8001222: edc7 7a0e vstr s15, [r7, #56] @ 0x38
q[3] += qDot[3] * (1.0f / filter->sample_freq);
8001226: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
800122a: edd7 6a0b vldr s13, [r7, #44] @ 0x2c
800122e: 69fb ldr r3, [r7, #28]
8001230: ed93 6a05 vldr s12, [r3, #20]
8001234: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
8001238: eec5 7a86 vdiv.f32 s15, s11, s12
800123c: ee66 7aa7 vmul.f32 s15, s13, s15
8001240: ee77 7a27 vadd.f32 s15, s14, s15
8001244: edc7 7a0f vstr s15, [r7, #60] @ 0x3c
// Normalise quaternion
recipNorm = invSqrt(q[0] * q[0] + q[1] * q[1] + q[2] * q[2] + q[3] * q[3]);
8001248: ed97 7a0c vldr s14, [r7, #48] @ 0x30
800124c: edd7 7a0c vldr s15, [r7, #48] @ 0x30
8001250: ee27 7a27 vmul.f32 s14, s14, s15
8001254: edd7 6a0d vldr s13, [r7, #52] @ 0x34
8001258: edd7 7a0d vldr s15, [r7, #52] @ 0x34
800125c: ee66 7aa7 vmul.f32 s15, s13, s15
8001260: ee37 7a27 vadd.f32 s14, s14, s15
8001264: edd7 6a0e vldr s13, [r7, #56] @ 0x38
8001268: edd7 7a0e vldr s15, [r7, #56] @ 0x38
800126c: ee66 7aa7 vmul.f32 s15, s13, s15
8001270: ee37 7a27 vadd.f32 s14, s14, s15
8001274: edd7 6a0f vldr s13, [r7, #60] @ 0x3c
8001278: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
800127c: ee66 7aa7 vmul.f32 s15, s13, s15
8001280: ee77 7a27 vadd.f32 s15, s14, s15
8001284: eeb0 0a67 vmov.f32 s0, s15
8001288: f000 f832 bl 80012f0 <invSqrt>
800128c: ed87 0a21 vstr s0, [r7, #132] @ 0x84
q[0] *= recipNorm;
8001290: ed97 7a0c vldr s14, [r7, #48] @ 0x30
8001294: edd7 7a21 vldr s15, [r7, #132] @ 0x84
8001298: ee67 7a27 vmul.f32 s15, s14, s15
800129c: edc7 7a0c vstr s15, [r7, #48] @ 0x30
q[1] *= recipNorm;
80012a0: ed97 7a0d vldr s14, [r7, #52] @ 0x34
80012a4: edd7 7a21 vldr s15, [r7, #132] @ 0x84
80012a8: ee67 7a27 vmul.f32 s15, s14, s15
80012ac: edc7 7a0d vstr s15, [r7, #52] @ 0x34
q[2] *= recipNorm;
80012b0: ed97 7a0e vldr s14, [r7, #56] @ 0x38
80012b4: edd7 7a21 vldr s15, [r7, #132] @ 0x84
80012b8: ee67 7a27 vmul.f32 s15, s14, s15
80012bc: edc7 7a0e vstr s15, [r7, #56] @ 0x38
q[3] *= recipNorm;
80012c0: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
80012c4: edd7 7a21 vldr s15, [r7, #132] @ 0x84
80012c8: ee67 7a27 vmul.f32 s15, s14, s15
80012cc: edc7 7a0f vstr s15, [r7, #60] @ 0x3c
// Update filter state
filter->q[0] = q[0];
80012d0: 6b3a ldr r2, [r7, #48] @ 0x30
80012d2: 69fb ldr r3, [r7, #28]
80012d4: 601a str r2, [r3, #0]
filter->q[1] = q[1];
80012d6: 6b7a ldr r2, [r7, #52] @ 0x34
80012d8: 69fb ldr r3, [r7, #28]
80012da: 605a str r2, [r3, #4]
filter->q[2] = q[2];
80012dc: 6bba ldr r2, [r7, #56] @ 0x38
80012de: 69fb ldr r3, [r7, #28]
80012e0: 609a str r2, [r3, #8]
filter->q[3] = q[3];
80012e2: 6bfa ldr r2, [r7, #60] @ 0x3c
80012e4: 69fb ldr r3, [r7, #28]
80012e6: 60da str r2, [r3, #12]
}
80012e8: bf00 nop
80012ea: 3788 adds r7, #136 @ 0x88
80012ec: 46bd mov sp, r7
80012ee: bd80 pop {r7, pc}
080012f0 <invSqrt>:
//---------------------------------------------------------------------------------------------------
// Fast inverse square-root
// See: http://en.wikipedia.org/wiki/Fast_inverse_square_root
float invSqrt(float x) {
80012f0: b480 push {r7}
80012f2: b087 sub sp, #28
80012f4: af00 add r7, sp, #0
80012f6: ed87 0a01 vstr s0, [r7, #4]
float halfx = 0.5f * x;
80012fa: edd7 7a01 vldr s15, [r7, #4]
80012fe: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5
8001302: ee67 7a87 vmul.f32 s15, s15, s14
8001306: edc7 7a05 vstr s15, [r7, #20]
float y = x;
800130a: 687b ldr r3, [r7, #4]
800130c: 613b str r3, [r7, #16]
long i = *(long*)&y;
800130e: f107 0310 add.w r3, r7, #16
8001312: 681b ldr r3, [r3, #0]
8001314: 60fb str r3, [r7, #12]
i = 0x5f3759df - (i>>1);
8001316: 68fb ldr r3, [r7, #12]
8001318: 105a asrs r2, r3, #1
800131a: 4b12 ldr r3, [pc, #72] @ (8001364 <invSqrt+0x74>)
800131c: 1a9b subs r3, r3, r2
800131e: 60fb str r3, [r7, #12]
y = *(float*)&i;
8001320: f107 030c add.w r3, r7, #12
8001324: 681b ldr r3, [r3, #0]
8001326: 613b str r3, [r7, #16]
y = y * (1.5f - (halfx * y * y));
8001328: ed97 7a04 vldr s14, [r7, #16]
800132c: edd7 7a05 vldr s15, [r7, #20]
8001330: ee27 7a27 vmul.f32 s14, s14, s15
8001334: edd7 7a04 vldr s15, [r7, #16]
8001338: ee67 7a27 vmul.f32 s15, s14, s15
800133c: eeb7 7a08 vmov.f32 s14, #120 @ 0x3fc00000 1.5
8001340: ee37 7a67 vsub.f32 s14, s14, s15
8001344: edd7 7a04 vldr s15, [r7, #16]
8001348: ee67 7a27 vmul.f32 s15, s14, s15
800134c: edc7 7a04 vstr s15, [r7, #16]
return y;
8001350: 693b ldr r3, [r7, #16]
8001352: ee07 3a90 vmov s15, r3
}
8001356: eeb0 0a67 vmov.f32 s0, s15
800135a: 371c adds r7, #28
800135c: 46bd mov sp, r7
800135e: f85d 7b04 ldr.w r7, [sp], #4
8001362: 4770 bx lr
8001364: 5f3759df .word 0x5f3759df
08001368 <APPD_EnableCPU2>:
/* USER CODE END APPD_Init */
return;
}
void APPD_EnableCPU2( void )
{
8001368: b5b0 push {r4, r5, r7, lr}
800136a: b088 sub sp, #32
800136c: af00 add r7, sp, #0
/* USER CODE BEGIN APPD_EnableCPU2 */
SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket =
800136e: 4b0b ldr r3, [pc, #44] @ (800139c <APPD_EnableCPU2+0x34>)
8001370: 1d3c adds r4, r7, #4
8001372: 461d mov r5, r3
8001374: cd0f ldmia r5!, {r0, r1, r2, r3}
8001376: c40f stmia r4!, {r0, r1, r2, r3}
8001378: e895 0007 ldmia.w r5, {r0, r1, r2}
800137c: c403 stmia r4!, {r0, r1}
800137e: 8022 strh r2, [r4, #0]
8001380: 3402 adds r4, #2
8001382: 0c13 lsrs r3, r2, #16
8001384: 7023 strb r3, [r4, #0]
NBR_OF_TRACES_CONFIG_PARAMETERS,
NBR_OF_GENERAL_CONFIG_PARAMETERS}
};
/**< Traces channel initialization */
TL_TRACES_Init( );
8001386: f010 fb25 bl 80119d4 <TL_TRACES_Init>
/** GPIO DEBUG Initialization */
SHCI_C2_DEBUG_Init( &DebugCmdPacket );
800138a: 1d3b adds r3, r7, #4
800138c: 4618 mov r0, r3
800138e: f00f ff9e bl 80112ce <SHCI_C2_DEBUG_Init>
/* USER CODE END APPD_EnableCPU2 */
return;
8001392: bf00 nop
}
8001394: 3720 adds r7, #32
8001396: 46bd mov sp, r7
8001398: bdb0 pop {r4, r5, r7, pc}
800139a: bf00 nop
800139c: 0801c090 .word 0x0801c090
080013a0 <LL_C2_PWR_SetPowerMode>:
*
* (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx
* @retval None
*/
__STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
{
80013a0: b480 push {r7}
80013a2: b083 sub sp, #12
80013a4: af00 add r7, sp, #0
80013a6: 6078 str r0, [r7, #4]
MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode);
80013a8: 4b07 ldr r3, [pc, #28] @ (80013c8 <LL_C2_PWR_SetPowerMode+0x28>)
80013aa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80013ae: f023 0207 bic.w r2, r3, #7
80013b2: 4905 ldr r1, [pc, #20] @ (80013c8 <LL_C2_PWR_SetPowerMode+0x28>)
80013b4: 687b ldr r3, [r7, #4]
80013b6: 4313 orrs r3, r2
80013b8: f8c1 3080 str.w r3, [r1, #128] @ 0x80
}
80013bc: bf00 nop
80013be: 370c adds r7, #12
80013c0: 46bd mov sp, r7
80013c2: f85d 7b04 ldr.w r7, [sp], #4
80013c6: 4770 bx lr
80013c8: 58000400 .word 0x58000400
080013cc <LL_EXTI_EnableIT_32_63>:
* @arg @ref LL_EXTI_LINE_ALL_32_63
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
{
80013cc: b480 push {r7}
80013ce: b083 sub sp, #12
80013d0: af00 add r7, sp, #0
80013d2: 6078 str r0, [r7, #4]
SET_BIT(EXTI->IMR2, ExtiLine);
80013d4: 4b06 ldr r3, [pc, #24] @ (80013f0 <LL_EXTI_EnableIT_32_63+0x24>)
80013d6: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90
80013da: 4905 ldr r1, [pc, #20] @ (80013f0 <LL_EXTI_EnableIT_32_63+0x24>)
80013dc: 687b ldr r3, [r7, #4]
80013de: 4313 orrs r3, r2
80013e0: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
80013e4: bf00 nop
80013e6: 370c adds r7, #12
80013e8: 46bd mov sp, r7
80013ea: f85d 7b04 ldr.w r7, [sp], #4
80013ee: 4770 bx lr
80013f0: 58000800 .word 0x58000800
080013f4 <LL_RCC_HSE_SetCapacitorTuning>:
* @rmtoll HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning
* @param Value Between Min_Data = 0 and Max_Data = 63
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)
{
80013f4: b480 push {r7}
80013f6: b083 sub sp, #12
80013f8: af00 add r7, sp, #0
80013fa: 6078 str r0, [r7, #4]
WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
80013fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8001400: 4a0a ldr r2, [pc, #40] @ (800142c <LL_RCC_HSE_SetCapacitorTuning+0x38>)
8001402: f8c3 209c str.w r2, [r3, #156] @ 0x9c
MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos);
8001406: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800140a: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c
800140e: f423 527c bic.w r2, r3, #16128 @ 0x3f00
8001412: 687b ldr r3, [r7, #4]
8001414: 021b lsls r3, r3, #8
8001416: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800141a: 4313 orrs r3, r2
800141c: f8c1 309c str.w r3, [r1, #156] @ 0x9c
}
8001420: bf00 nop
8001422: 370c adds r7, #12
8001424: 46bd mov sp, r7
8001426: f85d 7b04 ldr.w r7, [sp], #4
800142a: 4770 bx lr
800142c: cafecafe .word 0xcafecafe
08001430 <LL_RCC_SetClkAfterWakeFromStop>:
* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
{
8001430: b480 push {r7}
8001432: b083 sub sp, #12
8001434: af00 add r7, sp, #0
8001436: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
8001438: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800143c: 689b ldr r3, [r3, #8]
800143e: f423 4200 bic.w r2, r3, #32768 @ 0x8000
8001442: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8001446: 687b ldr r3, [r7, #4]
8001448: 4313 orrs r3, r2
800144a: 608b str r3, [r1, #8]
}
800144c: bf00 nop
800144e: 370c adds r7, #12
8001450: 46bd mov sp, r7
8001452: f85d 7b04 ldr.w r7, [sp], #4
8001456: 4770 bx lr
08001458 <LL_DBGMCU_GetDeviceID>:
* @note For STM32WBxxxx devices, the device ID is 0x495
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495)
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
{
8001458: b480 push {r7}
800145a: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
800145c: 4b04 ldr r3, [pc, #16] @ (8001470 <LL_DBGMCU_GetDeviceID+0x18>)
800145e: 681b ldr r3, [r3, #0]
8001460: f3c3 030b ubfx r3, r3, #0, #12
}
8001464: 4618 mov r0, r3
8001466: 46bd mov sp, r7
8001468: f85d 7b04 ldr.w r7, [sp], #4
800146c: 4770 bx lr
800146e: bf00 nop
8001470: e0042000 .word 0xe0042000
08001474 <LL_DBGMCU_GetRevisionID>:
* @note This field indicates the revision of the device.
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
{
8001474: b480 push {r7}
8001476: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
8001478: 4b04 ldr r3, [pc, #16] @ (800148c <LL_DBGMCU_GetRevisionID+0x18>)
800147a: 681b ldr r3, [r3, #0]
800147c: 0c1b lsrs r3, r3, #16
800147e: b29b uxth r3, r3
}
8001480: 4618 mov r0, r3
8001482: 46bd mov sp, r7
8001484: f85d 7b04 ldr.w r7, [sp], #4
8001488: 4770 bx lr
800148a: bf00 nop
800148c: e0042000 .word 0xe0042000
08001490 <LL_RTC_EnableWriteProtection>:
* @rmtoll WPR KEY LL_RTC_EnableWriteProtection
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
{
8001490: b480 push {r7}
8001492: b083 sub sp, #12
8001494: af00 add r7, sp, #0
8001496: 6078 str r0, [r7, #4]
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
8001498: 687b ldr r3, [r7, #4]
800149a: 22ff movs r2, #255 @ 0xff
800149c: 625a str r2, [r3, #36] @ 0x24
}
800149e: bf00 nop
80014a0: 370c adds r7, #12
80014a2: 46bd mov sp, r7
80014a4: f85d 7b04 ldr.w r7, [sp], #4
80014a8: 4770 bx lr
080014aa <LL_RTC_DisableWriteProtection>:
* @rmtoll WPR KEY LL_RTC_DisableWriteProtection
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
{
80014aa: b480 push {r7}
80014ac: b083 sub sp, #12
80014ae: af00 add r7, sp, #0
80014b0: 6078 str r0, [r7, #4]
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
80014b2: 687b ldr r3, [r7, #4]
80014b4: 22ca movs r2, #202 @ 0xca
80014b6: 625a str r2, [r3, #36] @ 0x24
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
80014b8: 687b ldr r3, [r7, #4]
80014ba: 2253 movs r2, #83 @ 0x53
80014bc: 625a str r2, [r3, #36] @ 0x24
}
80014be: bf00 nop
80014c0: 370c adds r7, #12
80014c2: 46bd mov sp, r7
80014c4: f85d 7b04 ldr.w r7, [sp], #4
80014c8: 4770 bx lr
080014ca <LL_RTC_WAKEUP_SetClock>:
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
{
80014ca: b480 push {r7}
80014cc: b083 sub sp, #12
80014ce: af00 add r7, sp, #0
80014d0: 6078 str r0, [r7, #4]
80014d2: 6039 str r1, [r7, #0]
MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
80014d4: 687b ldr r3, [r7, #4]
80014d6: 689b ldr r3, [r3, #8]
80014d8: f023 0207 bic.w r2, r3, #7
80014dc: 683b ldr r3, [r7, #0]
80014de: 431a orrs r2, r3
80014e0: 687b ldr r3, [r7, #4]
80014e2: 609a str r2, [r3, #8]
}
80014e4: bf00 nop
80014e6: 370c adds r7, #12
80014e8: 46bd mov sp, r7
80014ea: f85d 7b04 ldr.w r7, [sp], #4
80014ee: 4770 bx lr
080014f0 <MX_APPE_Config>:
/* USER CODE END PFP */
/* Functions Definition ------------------------------------------------------*/
void MX_APPE_Config(void)
{
80014f0: b580 push {r7, lr}
80014f2: af00 add r7, sp, #0
/**
* The OPTVERR flag is wrongly set at power on
* It shall be cleared before using any HAL_FLASH_xxx() api
*/
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
80014f4: 4b04 ldr r3, [pc, #16] @ (8001508 <MX_APPE_Config+0x18>)
80014f6: f44f 4200 mov.w r2, #32768 @ 0x8000
80014fa: 611a str r2, [r3, #16]
/**
* Reset some configurations so that the system behave in the same way
* when either out of nReset or Power On
*/
Reset_Device();
80014fc: f000 f824 bl 8001548 <Reset_Device>
/* Configure HSE Tuning */
Config_HSE();
8001500: f000 f829 bl 8001556 <Config_HSE>
return;
8001504: bf00 nop
}
8001506: bd80 pop {r7, pc}
8001508: 58004000 .word 0x58004000
0800150c <MX_APPE_Init>:
void MX_APPE_Init(void)
{
800150c: b580 push {r7, lr}
800150e: af00 add r7, sp, #0
System_Init(); /**< System initialization */
8001510: f000 f835 bl 800157e <System_Init>
SystemPower_Config(); /**< Configure the system Power Mode */
8001514: f000 f84e bl 80015b4 <SystemPower_Config>
HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
8001518: 4903 ldr r1, [pc, #12] @ (8001528 <MX_APPE_Init+0x1c>)
800151a: 2000 movs r0, #0
800151c: f001 ff32 bl 8003384 <HW_TS_Init>
/* USER CODE BEGIN APPE_Init_1 */
/* USER CODE END APPE_Init_1 */
appe_Tl_Init(); /* Initialize all transport layers */
8001520: f000 f856 bl 80015d0 <appe_Tl_Init>
*/
/* USER CODE BEGIN APPE_Init_2 */
/* USER CODE END APPE_Init_2 */
return;
8001524: bf00 nop
}
8001526: bd80 pop {r7, pc}
8001528: 20000504 .word 0x20000504
0800152c <Init_Smps>:
void Init_Smps(void)
{
800152c: b480 push {r7}
800152e: af00 add r7, sp, #0
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
LL_PWR_SMPS_Enable();
#endif /* CFG_USE_SMPS != 0 */
return;
8001530: bf00 nop
}
8001532: 46bd mov sp, r7
8001534: f85d 7b04 ldr.w r7, [sp], #4
8001538: 4770 bx lr
0800153a <Init_Exti>:
void Init_Exti(void)
{
800153a: b580 push {r7, lr}
800153c: af00 add r7, sp, #0
/* Enable IPCC(36), HSEM(38) wakeup interrupts on CPU1 */
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_36 | LL_EXTI_LINE_38);
800153e: 2050 movs r0, #80 @ 0x50
8001540: f7ff ff44 bl 80013cc <LL_EXTI_EnableIT_32_63>
return;
8001544: bf00 nop
}
8001546: bd80 pop {r7, pc}
08001548 <Reset_Device>:
*
* LOCAL FUNCTIONS
*
*************************************************************/
static void Reset_Device(void)
{
8001548: b480 push {r7}
800154a: af00 add r7, sp, #0
Reset_BackupDomain();
Reset_IPCC();
#endif /* CFG_HW_RESET_BY_FW == 1 */
return;
800154c: bf00 nop
}
800154e: 46bd mov sp, r7
8001550: f85d 7b04 ldr.w r7, [sp], #4
8001554: 4770 bx lr
08001556 <Config_HSE>:
return;
}
#endif /* CFG_HW_RESET_BY_FW == 1 */
static void Config_HSE(void)
{
8001556: b580 push {r7, lr}
8001558: b082 sub sp, #8
800155a: af00 add r7, sp, #0
OTP_ID0_t * p_otp;
/**
* Read HSE_Tuning from OTP
*/
p_otp = (OTP_ID0_t *) OTP_Read(0);
800155c: 2000 movs r0, #0
800155e: f010 facd bl 8011afc <OTP_Read>
8001562: 6078 str r0, [r7, #4]
if (p_otp)
8001564: 687b ldr r3, [r7, #4]
8001566: 2b00 cmp r3, #0
8001568: d005 beq.n 8001576 <Config_HSE+0x20>
{
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
800156a: 687b ldr r3, [r7, #4]
800156c: 799b ldrb r3, [r3, #6]
800156e: 4618 mov r0, r3
8001570: f7ff ff40 bl 80013f4 <LL_RCC_HSE_SetCapacitorTuning>
}
return;
8001574: bf00 nop
8001576: bf00 nop
}
8001578: 3708 adds r7, #8
800157a: 46bd mov sp, r7
800157c: bd80 pop {r7, pc}
0800157e <System_Init>:
static void System_Init(void)
{
800157e: b580 push {r7, lr}
8001580: af00 add r7, sp, #0
Init_Smps();
8001582: f7ff ffd3 bl 800152c <Init_Smps>
Init_Exti();
8001586: f7ff ffd8 bl 800153a <Init_Exti>
Init_Rtc();
800158a: f000 f803 bl 8001594 <Init_Rtc>
return;
800158e: bf00 nop
}
8001590: bd80 pop {r7, pc}
...
08001594 <Init_Rtc>:
static void Init_Rtc(void)
{
8001594: b580 push {r7, lr}
8001596: af00 add r7, sp, #0
/* Disable RTC registers write protection */
LL_RTC_DisableWriteProtection(RTC);
8001598: 4805 ldr r0, [pc, #20] @ (80015b0 <Init_Rtc+0x1c>)
800159a: f7ff ff86 bl 80014aa <LL_RTC_DisableWriteProtection>
LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
800159e: 2100 movs r1, #0
80015a0: 4803 ldr r0, [pc, #12] @ (80015b0 <Init_Rtc+0x1c>)
80015a2: f7ff ff92 bl 80014ca <LL_RTC_WAKEUP_SetClock>
/* Enable RTC registers write protection */
LL_RTC_EnableWriteProtection(RTC);
80015a6: 4802 ldr r0, [pc, #8] @ (80015b0 <Init_Rtc+0x1c>)
80015a8: f7ff ff72 bl 8001490 <LL_RTC_EnableWriteProtection>
return;
80015ac: bf00 nop
}
80015ae: bd80 pop {r7, pc}
80015b0: 40002800 .word 0x40002800
080015b4 <SystemPower_Config>:
*
* @param None
* @retval None
*/
static void SystemPower_Config(void)
{
80015b4: b580 push {r7, lr}
80015b6: af00 add r7, sp, #0
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
80015b8: f44f 4000 mov.w r0, #32768 @ 0x8000
80015bc: f7ff ff38 bl 8001430 <LL_RCC_SetClkAfterWakeFromStop>
/* Initialize low power manager */
UTIL_LPM_Init();
80015c0: f016 f932 bl 8017828 <UTIL_LPM_Init>
/* Initialize the CPU2 reset value before starting CPU2 with C2BOOT */
LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
80015c4: 2004 movs r0, #4
80015c6: f7ff feeb bl 80013a0 <LL_C2_PWR_SetPowerMode>
* Enable USB power
*/
HAL_PWREx_EnableVddUSB();
#endif /* CFG_USB_INTERFACE_ENABLE != 0 */
return;
80015ca: bf00 nop
}
80015cc: bd80 pop {r7, pc}
...
080015d0 <appe_Tl_Init>:
static void appe_Tl_Init(void)
{
80015d0: b580 push {r7, lr}
80015d2: b088 sub sp, #32
80015d4: af00 add r7, sp, #0
TL_MM_Config_t tl_mm_config;
SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
/**< Reference table initialization */
TL_Init();
80015d6: f010 f893 bl 8011700 <TL_Init>
MtxShciId = osMutexNew(NULL);
80015da: 2000 movs r0, #0
80015dc: f010 fdbf bl 801215e <osMutexNew>
80015e0: 4603 mov r3, r0
80015e2: 4a17 ldr r2, [pc, #92] @ (8001640 <appe_Tl_Init+0x70>)
80015e4: 6013 str r3, [r2, #0]
SemShciId = osSemaphoreNew(1, 0, NULL); /*< Create the semaphore and make it busy at initialization */
80015e6: 2200 movs r2, #0
80015e8: 2100 movs r1, #0
80015ea: 2001 movs r0, #1
80015ec: f010 fec2 bl 8012374 <osSemaphoreNew>
80015f0: 4603 mov r3, r0
80015f2: 4a14 ldr r2, [pc, #80] @ (8001644 <appe_Tl_Init+0x74>)
80015f4: 6013 str r3, [r2, #0]
/** FreeRTOS system task creation */
ShciUserEvtProcessId = osThreadNew(ShciUserEvtProcess, NULL, &ShciUserEvtProcess_attr);
80015f6: 4a14 ldr r2, [pc, #80] @ (8001648 <appe_Tl_Init+0x78>)
80015f8: 2100 movs r1, #0
80015fa: 4814 ldr r0, [pc, #80] @ (800164c <appe_Tl_Init+0x7c>)
80015fc: f010 fc1e bl 8011e3c <osThreadNew>
8001600: 4603 mov r3, r0
8001602: 4a13 ldr r2, [pc, #76] @ (8001650 <appe_Tl_Init+0x80>)
8001604: 6013 str r3, [r2, #0]
/**< System channel initialization */
SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
8001606: 4b13 ldr r3, [pc, #76] @ (8001654 <appe_Tl_Init+0x84>)
8001608: 603b str r3, [r7, #0]
SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
800160a: 4b13 ldr r3, [pc, #76] @ (8001658 <appe_Tl_Init+0x88>)
800160c: 607b str r3, [r7, #4]
shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
800160e: 463b mov r3, r7
8001610: 4619 mov r1, r3
8001612: 4812 ldr r0, [pc, #72] @ (800165c <appe_Tl_Init+0x8c>)
8001614: f00f ff36 bl 8011484 <shci_init>
/**< Memory Manager channel initialization */
tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
8001618: 4b11 ldr r3, [pc, #68] @ (8001660 <appe_Tl_Init+0x90>)
800161a: 60bb str r3, [r7, #8]
tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
800161c: 4b11 ldr r3, [pc, #68] @ (8001664 <appe_Tl_Init+0x94>)
800161e: 60fb str r3, [r7, #12]
tl_mm_config.p_AsynchEvtPool = EvtPool;
8001620: 4b11 ldr r3, [pc, #68] @ (8001668 <appe_Tl_Init+0x98>)
8001622: 613b str r3, [r7, #16]
tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
8001624: f240 533c movw r3, #1340 @ 0x53c
8001628: 617b str r3, [r7, #20]
TL_MM_Init(&tl_mm_config);
800162a: f107 0308 add.w r3, r7, #8
800162e: 4618 mov r0, r3
8001630: f010 f95c bl 80118ec <TL_MM_Init>
TL_Enable();
8001634: f010 f85e bl 80116f4 <TL_Enable>
return;
8001638: bf00 nop
}
800163a: 3720 adds r7, #32
800163c: 46bd mov sp, r7
800163e: bd80 pop {r7, pc}
8001640: 20000308 .word 0x20000308
8001644: 2000030c .word 0x2000030c
8001648: 0801c658 .word 0x0801c658
800164c: 080017cf .word 0x080017cf
8001650: 20000310 .word 0x20000310
8001654: 20030628 .word 0x20030628
8001658: 0800167d .word 0x0800167d
800165c: 080016bd .word 0x080016bd
8001660: 20030840 .word 0x20030840
8001664: 20030734 .word 0x20030734
8001668: 200300ec .word 0x200300ec
0800166c <APP_BLE_Init>:
__WEAK void APP_BLE_Init(void)
{
800166c: b480 push {r7}
800166e: af00 add r7, sp, #0
}
8001670: bf00 nop
8001672: 46bd mov sp, r7
8001674: f85d 7b04 ldr.w r7, [sp], #4
8001678: 4770 bx lr
...
0800167c <APPE_SysStatusNot>:
static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status)
{
800167c: b580 push {r7, lr}
800167e: b082 sub sp, #8
8001680: af00 add r7, sp, #0
8001682: 4603 mov r3, r0
8001684: 71fb strb r3, [r7, #7]
switch (status)
8001686: 79fb ldrb r3, [r7, #7]
8001688: 2b00 cmp r3, #0
800168a: d002 beq.n 8001692 <APPE_SysStatusNot+0x16>
800168c: 2b01 cmp r3, #1
800168e: d008 beq.n 80016a2 <APPE_SysStatusNot+0x26>
case SHCI_TL_CmdAvailable:
osMutexRelease(MtxShciId);
break;
default:
break;
8001690: e00d b.n 80016ae <APPE_SysStatusNot+0x32>
osMutexAcquire(MtxShciId, osWaitForever);
8001692: 4b09 ldr r3, [pc, #36] @ (80016b8 <APPE_SysStatusNot+0x3c>)
8001694: 681b ldr r3, [r3, #0]
8001696: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
800169a: 4618 mov r0, r3
800169c: f010 fde4 bl 8012268 <osMutexAcquire>
break;
80016a0: e005 b.n 80016ae <APPE_SysStatusNot+0x32>
osMutexRelease(MtxShciId);
80016a2: 4b05 ldr r3, [pc, #20] @ (80016b8 <APPE_SysStatusNot+0x3c>)
80016a4: 681b ldr r3, [r3, #0]
80016a6: 4618 mov r0, r3
80016a8: f010 fe28 bl 80122fc <osMutexRelease>
break;
80016ac: bf00 nop
}
return;
80016ae: bf00 nop
}
80016b0: 3708 adds r7, #8
80016b2: 46bd mov sp, r7
80016b4: bd80 pop {r7, pc}
80016b6: bf00 nop
80016b8: 20000308 .word 0x20000308
080016bc <APPE_SysUserEvtRx>:
* The buffer shall not be released
* (eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable)
* When the status is not filled, the buffer is released by default
*/
static void APPE_SysUserEvtRx(void * pPayload)
{
80016bc: b580 push {r7, lr}
80016be: b088 sub sp, #32
80016c0: af00 add r7, sp, #0
80016c2: 6078 str r0, [r7, #4]
TL_AsynchEvt_t *p_sys_event;
WirelessFwInfo_t WirelessInfo;
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
80016c4: 687b ldr r3, [r7, #4]
80016c6: 685b ldr r3, [r3, #4]
80016c8: 330b adds r3, #11
80016ca: 61fb str r3, [r7, #28]
switch(p_sys_event->subevtcode)
80016cc: 69fb ldr r3, [r7, #28]
80016ce: 881b ldrh r3, [r3, #0]
80016d0: b29b uxth r3, r3
80016d2: f5a3 4312 sub.w r3, r3, #37376 @ 0x9200
80016d6: 2b07 cmp r3, #7
80016d8: d81f bhi.n 800171a <APPE_SysUserEvtRx+0x5e>
80016da: a201 add r2, pc, #4 @ (adr r2, 80016e0 <APPE_SysUserEvtRx+0x24>)
80016dc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80016e0: 08001701 .word 0x08001701
80016e4: 08001713 .word 0x08001713
80016e8: 0800171b .word 0x0800171b
80016ec: 0800171b .word 0x0800171b
80016f0: 0800171b .word 0x0800171b
80016f4: 0800171b .word 0x0800171b
80016f8: 0800171b .word 0x0800171b
80016fc: 0800171b .word 0x0800171b
{
case SHCI_SUB_EVT_CODE_READY:
/* Read the firmware version of both the wireless firmware and the FUS */
SHCI_GetWirelessFwInfo(&WirelessInfo);
8001700: f107 030c add.w r3, r7, #12
8001704: 4618 mov r0, r3
8001706: f00f fe0f bl 8011328 <SHCI_GetWirelessFwInfo>
APP_DBG_MSG("Wireless Firmware version %d.%d.%d\n", WirelessInfo.VersionMajor, WirelessInfo.VersionMinor, WirelessInfo.VersionSub);
APP_DBG_MSG("Wireless Firmware build %d\n", WirelessInfo.VersionReleaseType);
APP_DBG_MSG("FUS version %d.%d.%d\n", WirelessInfo.FusVersionMajor, WirelessInfo.FusVersionMinor, WirelessInfo.FusVersionSub);
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY\n\r");
APPE_SysEvtReadyProcessing(pPayload);
800170a: 6878 ldr r0, [r7, #4]
800170c: f000 f81b bl 8001746 <APPE_SysEvtReadyProcessing>
break;
8001710: e004 b.n 800171c <APPE_SysUserEvtRx+0x60>
case SHCI_SUB_EVT_ERROR_NOTIF:
APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF \n\r");
APPE_SysEvtError(pPayload);
8001712: 6878 ldr r0, [r7, #4]
8001714: f000 f806 bl 8001724 <APPE_SysEvtError>
break;
8001718: e000 b.n 800171c <APPE_SysUserEvtRx+0x60>
case SHCI_SUB_EVT_NVM_END_ERASE:
APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_ERASE\n\r");
break;
default:
break;
800171a: bf00 nop
}
return;
800171c: bf00 nop
}
800171e: 3720 adds r7, #32
8001720: 46bd mov sp, r7
8001722: bd80 pop {r7, pc}
08001724 <APPE_SysEvtError>:
* @param ErrorCode : errorCode detected by the M0 firmware
*
* @retval None
*/
static void APPE_SysEvtError(void * pPayload)
{
8001724: b480 push {r7}
8001726: b085 sub sp, #20
8001728: af00 add r7, sp, #0
800172a: 6078 str r0, [r7, #4]
TL_AsynchEvt_t *p_sys_event;
SCHI_SystemErrCode_t *p_sys_error_code;
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
800172c: 687b ldr r3, [r7, #4]
800172e: 685b ldr r3, [r3, #4]
8001730: 330b adds r3, #11
8001732: 60fb str r3, [r7, #12]
p_sys_error_code = (SCHI_SystemErrCode_t*) p_sys_event->payload;
8001734: 68fb ldr r3, [r7, #12]
8001736: 3302 adds r3, #2
8001738: 60bb str r3, [r7, #8]
}
else
{
APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - BLE ERROR \n");
}
return;
800173a: bf00 nop
}
800173c: 3714 adds r7, #20
800173e: 46bd mov sp, r7
8001740: f85d 7b04 ldr.w r7, [sp], #4
8001744: 4770 bx lr
08001746 <APPE_SysEvtReadyProcessing>:
static void APPE_SysEvtReadyProcessing(void * pPayload)
{
8001746: b580 push {r7, lr}
8001748: b08a sub sp, #40 @ 0x28
800174a: af00 add r7, sp, #0
800174c: 6078 str r0, [r7, #4]
TL_AsynchEvt_t *p_sys_event;
SHCI_C2_Ready_Evt_t *p_sys_ready_event;
SHCI_C2_CONFIG_Cmd_Param_t config_param = {0};
800174e: f107 0308 add.w r3, r7, #8
8001752: 2200 movs r2, #0
8001754: 601a str r2, [r3, #0]
8001756: 605a str r2, [r3, #4]
8001758: 609a str r2, [r3, #8]
800175a: 60da str r2, [r3, #12]
uint32_t RevisionID=0;
800175c: 2300 movs r3, #0
800175e: 627b str r3, [r7, #36] @ 0x24
uint32_t DeviceID=0;
8001760: 2300 movs r3, #0
8001762: 623b str r3, [r7, #32]
p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
8001764: 687b ldr r3, [r7, #4]
8001766: 685b ldr r3, [r3, #4]
8001768: 330b adds r3, #11
800176a: 61fb str r3, [r7, #28]
p_sys_ready_event = (SHCI_C2_Ready_Evt_t*) p_sys_event->payload;
800176c: 69fb ldr r3, [r7, #28]
800176e: 3302 adds r3, #2
8001770: 61bb str r3, [r7, #24]
if (p_sys_ready_event->sysevt_ready_rsp == WIRELESS_FW_RUNNING)
8001772: 69bb ldr r3, [r7, #24]
8001774: 781b ldrb r3, [r3, #0]
8001776: 2b00 cmp r3, #0
8001778: d11d bne.n 80017b6 <APPE_SysEvtReadyProcessing+0x70>
* The wireless firmware is running on the CPU2
*/
APP_DBG_MSG(">>== WIRELESS_FW_RUNNING \n");
/* Traces channel initialization */
APPD_EnableCPU2();
800177a: f7ff fdf5 bl 8001368 <APPD_EnableCPU2>
/* Enable all events Notification */
config_param.PayloadCmdSize = SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE;
800177e: 230f movs r3, #15
8001780: 723b strb r3, [r7, #8]
config_param.EvtMask1 = SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE
8001782: 237f movs r3, #127 @ 0x7f
8001784: 72bb strb r3, [r7, #10]
* @brief Return the device revision identifier
* @note This field indicates the revision of the device.
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
*/
RevisionID = LL_DBGMCU_GetRevisionID();
8001786: f7ff fe75 bl 8001474 <LL_DBGMCU_GetRevisionID>
800178a: 6278 str r0, [r7, #36] @ 0x24
APP_DBG_MSG(">>== DBGMCU_GetRevisionID= %lx \n\r", RevisionID);
config_param.RevisionID = (uint16_t)RevisionID;
800178c: 6a7b ldr r3, [r7, #36] @ 0x24
800178e: b29b uxth r3, r3
8001790: 82bb strh r3, [r7, #20]
DeviceID = LL_DBGMCU_GetDeviceID();
8001792: f7ff fe61 bl 8001458 <LL_DBGMCU_GetDeviceID>
8001796: 6238 str r0, [r7, #32]
APP_DBG_MSG(">>== DBGMCU_GetDeviceID= %lx \n\r", DeviceID);
config_param.DeviceID = (uint16_t)DeviceID;
8001798: 6a3b ldr r3, [r7, #32]
800179a: b29b uxth r3, r3
800179c: 82fb strh r3, [r7, #22]
(void)SHCI_C2_Config(&config_param);
800179e: f107 0308 add.w r3, r7, #8
80017a2: 4618 mov r0, r3
80017a4: f00f fdaa bl 80112fc <SHCI_C2_Config>
APP_BLE_Init();
80017a8: f7ff ff60 bl 800166c <APP_BLE_Init>
UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
80017ac: 2100 movs r1, #0
80017ae: 2001 movs r0, #1
80017b0: f016 f84c bl 801784c <UTIL_LPM_SetOffMode>
else
{
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - UNEXPECTED CASE \n\r");
}
return;
80017b4: e007 b.n 80017c6 <APPE_SysEvtReadyProcessing+0x80>
else if (p_sys_ready_event->sysevt_ready_rsp == FUS_FW_RUNNING)
80017b6: 69bb ldr r3, [r7, #24]
80017b8: 781b ldrb r3, [r3, #0]
80017ba: 2b01 cmp r3, #1
80017bc: d103 bne.n 80017c6 <APPE_SysEvtReadyProcessing+0x80>
((tSHCI_UserEvtRxParam*)pPayload)->status = SHCI_TL_UserEventFlow_Disable;
80017be: 687b ldr r3, [r7, #4]
80017c0: 2200 movs r2, #0
80017c2: 701a strb r2, [r3, #0]
return;
80017c4: bf00 nop
80017c6: bf00 nop
}
80017c8: 3728 adds r7, #40 @ 0x28
80017ca: 46bd mov sp, r7
80017cc: bd80 pop {r7, pc}
080017ce <ShciUserEvtProcess>:
*
* FREERTOS WRAPPER FUNCTIONS
*
*************************************************************/
static void ShciUserEvtProcess(void *argument)
{
80017ce: b580 push {r7, lr}
80017d0: b082 sub sp, #8
80017d2: af00 add r7, sp, #0
80017d4: 6078 str r0, [r7, #4]
for(;;)
{
/* USER CODE BEGIN SHCI_USER_EVT_PROCESS_1 */
/* USER CODE END SHCI_USER_EVT_PROCESS_1 */
osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever);
80017d6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80017da: 2100 movs r1, #0
80017dc: 2001 movs r0, #1
80017de: f010 fc21 bl 8012024 <osThreadFlagsWait>
shci_user_evt_proc();
80017e2: f00f fe6b bl 80114bc <shci_user_evt_proc>
osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever);
80017e6: bf00 nop
80017e8: e7f5 b.n 80017d6 <ShciUserEvtProcess+0x8>
...
080017ec <shci_notify_asynch_evt>:
__WFI();
}
}
void shci_notify_asynch_evt(void* pdata)
{
80017ec: b580 push {r7, lr}
80017ee: b082 sub sp, #8
80017f0: af00 add r7, sp, #0
80017f2: 6078 str r0, [r7, #4]
UNUSED(pdata);
osThreadFlagsSet(ShciUserEvtProcessId, 1);
80017f4: 4b04 ldr r3, [pc, #16] @ (8001808 <shci_notify_asynch_evt+0x1c>)
80017f6: 681b ldr r3, [r3, #0]
80017f8: 2101 movs r1, #1
80017fa: 4618 mov r0, r3
80017fc: f010 fbbc bl 8011f78 <osThreadFlagsSet>
return;
8001800: bf00 nop
}
8001802: 3708 adds r7, #8
8001804: 46bd mov sp, r7
8001806: bd80 pop {r7, pc}
8001808: 20000310 .word 0x20000310
0800180c <shci_cmd_resp_release>:
void shci_cmd_resp_release(uint32_t flag)
{
800180c: b580 push {r7, lr}
800180e: b082 sub sp, #8
8001810: af00 add r7, sp, #0
8001812: 6078 str r0, [r7, #4]
UNUSED(flag);
osSemaphoreRelease(SemShciId);
8001814: 4b04 ldr r3, [pc, #16] @ (8001828 <shci_cmd_resp_release+0x1c>)
8001816: 681b ldr r3, [r3, #0]
8001818: 4618 mov r0, r3
800181a: f010 fe83 bl 8012524 <osSemaphoreRelease>
return;
800181e: bf00 nop
}
8001820: 3708 adds r7, #8
8001822: 46bd mov sp, r7
8001824: bd80 pop {r7, pc}
8001826: bf00 nop
8001828: 2000030c .word 0x2000030c
0800182c <shci_cmd_resp_wait>:
void shci_cmd_resp_wait(uint32_t timeout)
{
800182c: b580 push {r7, lr}
800182e: b082 sub sp, #8
8001830: af00 add r7, sp, #0
8001832: 6078 str r0, [r7, #4]
UNUSED(timeout);
osSemaphoreAcquire(SemShciId, osWaitForever);
8001834: 4b05 ldr r3, [pc, #20] @ (800184c <shci_cmd_resp_wait+0x20>)
8001836: 681b ldr r3, [r3, #0]
8001838: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
800183c: 4618 mov r0, r3
800183e: f010 fe21 bl 8012484 <osSemaphoreAcquire>
return;
8001842: bf00 nop
}
8001844: 3708 adds r7, #8
8001846: 46bd mov sp, r7
8001848: bd80 pop {r7, pc}
800184a: bf00 nop
800184c: 2000030c .word 0x2000030c
08001850 <bmm350_init>:
/*!
* @brief This API is the entry point. Call this API before using other APIs.
*/
int8_t bmm350_init(struct bmm350_dev *dev)
{
8001850: b580 push {r7, lr}
8001852: b084 sub sp, #16
8001854: af00 add r7, sp, #0
8001856: 6078 str r0, [r7, #4]
/* Variable to store the function result */
int8_t rslt;
/* Variable to get chip id */
uint8_t chip_id = BMM350_DISABLE;
8001858: 2300 movs r3, #0
800185a: 73bb strb r3, [r7, #14]
/* Variable to store the command to power-off the OTP */
uint8_t otp_cmd = BMM350_OTP_CMD_PWR_OFF_OTP;
800185c: 2380 movs r3, #128 @ 0x80
800185e: 737b strb r3, [r7, #13]
/* Variable to store soft-reset command */
uint8_t soft_reset;
/* Check for null pointer in the device structure */
rslt = null_ptr_check(dev);
8001860: 6878 ldr r0, [r7, #4]
8001862: f000 fcee bl 8002242 <null_ptr_check>
8001866: 4603 mov r3, r0
8001868: 73fb strb r3, [r7, #15]
/* Proceed if null check is fine */
if (rslt == BMM350_OK)
800186a: f997 300f ldrsb.w r3, [r7, #15]
800186e: 2b00 cmp r3, #0
8001870: d173 bne.n 800195a <bmm350_init+0x10a>
{
dev->chip_id = 0;
8001872: 687b ldr r3, [r7, #4]
8001874: 2200 movs r2, #0
8001876: 711a strb r2, [r3, #4]
/* Assign axis_en with all axis enabled (BMM350_EN_XYZ_MSK) */
dev->axis_en = BMM350_EN_XYZ_MSK;
8001878: 687b ldr r3, [r7, #4]
800187a: 2207 movs r2, #7
800187c: 755a strb r2, [r3, #21]
rslt = bmm350_delay_us(BMM350_START_UP_TIME_FROM_POR, dev);
800187e: 6879 ldr r1, [r7, #4]
8001880: f640 30b8 movw r0, #3000 @ 0xbb8
8001884: f000 f8f8 bl 8001a78 <bmm350_delay_us>
8001888: 4603 mov r3, r0
800188a: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
800188c: f997 300f ldrsb.w r3, [r7, #15]
8001890: 2b00 cmp r3, #0
8001892: d115 bne.n 80018c0 <bmm350_init+0x70>
{
/* Soft-reset */
soft_reset = BMM350_CMD_SOFTRESET;
8001894: 23b6 movs r3, #182 @ 0xb6
8001896: 733b strb r3, [r7, #12]
/* Set the command in the command register */
rslt = bmm350_set_regs(BMM350_REG_CMD, &soft_reset, 1, dev);
8001898: f107 010c add.w r1, r7, #12
800189c: 687b ldr r3, [r7, #4]
800189e: 2201 movs r2, #1
80018a0: 207e movs r0, #126 @ 0x7e
80018a2: f000 f860 bl 8001966 <bmm350_set_regs>
80018a6: 4603 mov r3, r0
80018a8: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
80018aa: f997 300f ldrsb.w r3, [r7, #15]
80018ae: 2b00 cmp r3, #0
80018b0: d106 bne.n 80018c0 <bmm350_init+0x70>
{
rslt = bmm350_delay_us(BMM350_SOFT_RESET_DELAY, dev);
80018b2: 6879 ldr r1, [r7, #4]
80018b4: f645 50c0 movw r0, #24000 @ 0x5dc0
80018b8: f000 f8de bl 8001a78 <bmm350_delay_us>
80018bc: 4603 mov r3, r0
80018be: 73fb strb r3, [r7, #15]
}
}
if (rslt == BMM350_OK)
80018c0: f997 300f ldrsb.w r3, [r7, #15]
80018c4: 2b00 cmp r3, #0
80018c6: d10f bne.n 80018e8 <bmm350_init+0x98>
{
/* Chip ID of the sensor is read */
rslt = bmm350_get_regs(BMM350_REG_CHIP_ID, &chip_id, 1, dev);
80018c8: f107 010e add.w r1, r7, #14
80018cc: 687b ldr r3, [r7, #4]
80018ce: 2201 movs r2, #1
80018d0: 2000 movs r0, #0
80018d2: f000 f87c bl 80019ce <bmm350_get_regs>
80018d6: 4603 mov r3, r0
80018d8: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
80018da: f997 300f ldrsb.w r3, [r7, #15]
80018de: 2b00 cmp r3, #0
80018e0: d102 bne.n 80018e8 <bmm350_init+0x98>
{
/* Assign chip_id to dev->chip_id */
dev->chip_id = chip_id;
80018e2: 7bba ldrb r2, [r7, #14]
80018e4: 687b ldr r3, [r7, #4]
80018e6: 711a strb r2, [r3, #4]
}
}
/* Check for chip id validity */
if ((rslt == BMM350_OK) && (dev->chip_id == BMM350_CHIP_ID))
80018e8: f997 300f ldrsb.w r3, [r7, #15]
80018ec: 2b00 cmp r3, #0
80018ee: d130 bne.n 8001952 <bmm350_init+0x102>
80018f0: 687b ldr r3, [r7, #4]
80018f2: 791b ldrb r3, [r3, #4]
80018f4: 2b33 cmp r3, #51 @ 0x33
80018f6: d12c bne.n 8001952 <bmm350_init+0x102>
{
/* Download OTP memory */
rslt = otp_dump_after_boot(dev);
80018f8: 6878 ldr r0, [r7, #4]
80018fa: f001 f875 bl 80029e8 <otp_dump_after_boot>
80018fe: 4603 mov r3, r0
8001900: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001902: f997 300f ldrsb.w r3, [r7, #15]
8001906: 2b00 cmp r3, #0
8001908: d126 bne.n 8001958 <bmm350_init+0x108>
{
/* Power off OTP */
rslt = bmm350_set_regs(BMM350_REG_OTP_CMD_REG, &otp_cmd, 1, dev);
800190a: f107 010d add.w r1, r7, #13
800190e: 687b ldr r3, [r7, #4]
8001910: 2201 movs r2, #1
8001912: 2050 movs r0, #80 @ 0x50
8001914: f000 f827 bl 8001966 <bmm350_set_regs>
8001918: 4603 mov r3, r0
800191a: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
800191c: f997 300f ldrsb.w r3, [r7, #15]
8001920: 2b00 cmp r3, #0
8001922: d119 bne.n 8001958 <bmm350_init+0x108>
{
if (dev->boot_done_status != BMM350_BOOT_NOT_DONE)
8001924: 687b ldr r3, [r7, #4]
8001926: f893 30ac ldrb.w r3, [r3, #172] @ 0xac
800192a: 2b00 cmp r3, #0
800192c: d003 beq.n 8001936 <bmm350_init+0xe6>
{
dev->boot_done_status = BMM350_BOOT_NOT_DONE;
800192e: 687b ldr r3, [r7, #4]
8001930: 2200 movs r2, #0
8001932: f883 20ac strb.w r2, [r3, #172] @ 0xac
}
rslt = bmm350_magnetic_reset_and_wait(dev);
8001936: 6878 ldr r0, [r7, #4]
8001938: f000 f9fc bl 8001d34 <bmm350_magnetic_reset_and_wait>
800193c: 4603 mov r3, r0
800193e: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001940: f997 300f ldrsb.w r3, [r7, #15]
8001944: 2b00 cmp r3, #0
8001946: d107 bne.n 8001958 <bmm350_init+0x108>
{
dev->boot_done_status = BMM350_BOOT_DONE;
8001948: 687b ldr r3, [r7, #4]
800194a: 2201 movs r2, #1
800194c: f883 20ac strb.w r2, [r3, #172] @ 0xac
if (rslt == BMM350_OK)
8001950: e002 b.n 8001958 <bmm350_init+0x108>
}
}
}
else
{
rslt = BMM350_E_DEV_NOT_FOUND;
8001952: 23fd movs r3, #253 @ 0xfd
8001954: 73fb strb r3, [r7, #15]
8001956: e000 b.n 800195a <bmm350_init+0x10a>
if (rslt == BMM350_OK)
8001958: bf00 nop
}
}
return rslt;
800195a: f997 300f ldrsb.w r3, [r7, #15]
}
800195e: 4618 mov r0, r3
8001960: 3710 adds r7, #16
8001962: 46bd mov sp, r7
8001964: bd80 pop {r7, pc}
08001966 <bmm350_set_regs>:
/*!
* @brief This API writes the given data to the register address
* of the sensor.
*/
int8_t bmm350_set_regs(uint8_t reg_addr, const uint8_t *reg_data, uint16_t len, struct bmm350_dev *dev)
{
8001966: b590 push {r4, r7, lr}
8001968: b087 sub sp, #28
800196a: af00 add r7, sp, #0
800196c: 60b9 str r1, [r7, #8]
800196e: 607b str r3, [r7, #4]
8001970: 4603 mov r3, r0
8001972: 73fb strb r3, [r7, #15]
8001974: 4613 mov r3, r2
8001976: 81bb strh r3, [r7, #12]
/* Variable to store the function result */
int8_t rslt;
/* Check for null pointer in the device structure */
rslt = null_ptr_check(dev);
8001978: 6878 ldr r0, [r7, #4]
800197a: f000 fc62 bl 8002242 <null_ptr_check>
800197e: 4603 mov r3, r0
8001980: 75fb strb r3, [r7, #23]
/* Proceed if null check is fine */
if ((rslt == BMM350_OK) && (reg_data != NULL) && (len != 0))
8001982: f997 3017 ldrsb.w r3, [r7, #23]
8001986: 2b00 cmp r3, #0
8001988: d119 bne.n 80019be <bmm350_set_regs+0x58>
800198a: 68bb ldr r3, [r7, #8]
800198c: 2b00 cmp r3, #0
800198e: d016 beq.n 80019be <bmm350_set_regs+0x58>
8001990: 89bb ldrh r3, [r7, #12]
8001992: 2b00 cmp r3, #0
8001994: d013 beq.n 80019be <bmm350_set_regs+0x58>
{
/* Write the data to the reg_addr */
dev->intf_rslt = dev->write(reg_addr, reg_data, len, dev->intf_ptr);
8001996: 687b ldr r3, [r7, #4]
8001998: 68dc ldr r4, [r3, #12]
800199a: 89ba ldrh r2, [r7, #12]
800199c: 687b ldr r3, [r7, #4]
800199e: 681b ldr r3, [r3, #0]
80019a0: 7bf8 ldrb r0, [r7, #15]
80019a2: 68b9 ldr r1, [r7, #8]
80019a4: 47a0 blx r4
80019a6: 4603 mov r3, r0
80019a8: 461a mov r2, r3
80019aa: 687b ldr r3, [r7, #4]
80019ac: 751a strb r2, [r3, #20]
if (dev->intf_rslt != BMM350_INTF_RET_SUCCESS)
80019ae: 687b ldr r3, [r7, #4]
80019b0: f993 3014 ldrsb.w r3, [r3, #20]
80019b4: 2b00 cmp r3, #0
80019b6: d004 beq.n 80019c2 <bmm350_set_regs+0x5c>
{
rslt = BMM350_E_COM_FAIL;
80019b8: 23fe movs r3, #254 @ 0xfe
80019ba: 75fb strb r3, [r7, #23]
if (dev->intf_rslt != BMM350_INTF_RET_SUCCESS)
80019bc: e001 b.n 80019c2 <bmm350_set_regs+0x5c>
}
}
else
{
rslt = BMM350_E_NULL_PTR;
80019be: 23ff movs r3, #255 @ 0xff
80019c0: 75fb strb r3, [r7, #23]
}
return rslt;
80019c2: f997 3017 ldrsb.w r3, [r7, #23]
}
80019c6: 4618 mov r0, r3
80019c8: 371c adds r7, #28
80019ca: 46bd mov sp, r7
80019cc: bd90 pop {r4, r7, pc}
080019ce <bmm350_get_regs>:
/*!
* @brief This API reads the data from the given register address of sensor.
*/
int8_t bmm350_get_regs(uint8_t reg_addr, uint8_t *reg_data, uint16_t len, struct bmm350_dev *dev)
{
80019ce: b590 push {r4, r7, lr}
80019d0: b0a7 sub sp, #156 @ 0x9c
80019d2: af00 add r7, sp, #0
80019d4: 60b9 str r1, [r7, #8]
80019d6: 607b str r3, [r7, #4]
80019d8: 4603 mov r3, r0
80019da: 73fb strb r3, [r7, #15]
80019dc: 4613 mov r3, r2
80019de: 81bb strh r3, [r7, #12]
/* Variable to store the function result */
int8_t rslt;
/* Variable to define temporary length */
uint16_t temp_len = len + BMM350_DUMMY_BYTES;
80019e0: 89bb ldrh r3, [r7, #12]
80019e2: 3302 adds r3, #2
80019e4: f8a7 3092 strh.w r3, [r7, #146] @ 0x92
/* Variable to define temporary buffer */
uint8_t temp_buf[BMM350_READ_BUFFER_LENGTH];
/* Variable to define loop */
uint16_t index = 0;
80019e8: 2300 movs r3, #0
80019ea: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
/* Check for null pointer in the device structure */
rslt = null_ptr_check(dev);
80019ee: 6878 ldr r0, [r7, #4]
80019f0: f000 fc27 bl 8002242 <null_ptr_check>
80019f4: 4603 mov r3, r0
80019f6: f887 3097 strb.w r3, [r7, #151] @ 0x97
/* Proceed if null check is fine */
if ((rslt == BMM350_OK) && (reg_data != NULL))
80019fa: f997 3097 ldrsb.w r3, [r7, #151] @ 0x97
80019fe: 2b00 cmp r3, #0
8001a00: d131 bne.n 8001a66 <bmm350_get_regs+0x98>
8001a02: 68bb ldr r3, [r7, #8]
8001a04: 2b00 cmp r3, #0
8001a06: d02e beq.n 8001a66 <bmm350_get_regs+0x98>
{
/* Read the data from the reg_addr */
dev->intf_rslt = dev->read(reg_addr, temp_buf, temp_len, dev->intf_ptr);
8001a08: 687b ldr r3, [r7, #4]
8001a0a: 689c ldr r4, [r3, #8]
8001a0c: f8b7 2092 ldrh.w r2, [r7, #146] @ 0x92
8001a10: 687b ldr r3, [r7, #4]
8001a12: 681b ldr r3, [r3, #0]
8001a14: f107 0110 add.w r1, r7, #16
8001a18: 7bf8 ldrb r0, [r7, #15]
8001a1a: 47a0 blx r4
8001a1c: 4603 mov r3, r0
8001a1e: 461a mov r2, r3
8001a20: 687b ldr r3, [r7, #4]
8001a22: 751a strb r2, [r3, #20]
if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS)
8001a24: 687b ldr r3, [r7, #4]
8001a26: f993 3014 ldrsb.w r3, [r3, #20]
8001a2a: 2b00 cmp r3, #0
8001a2c: d117 bne.n 8001a5e <bmm350_get_regs+0x90>
{
/* Copy data after dummy byte indices */
while (index < len)
8001a2e: e010 b.n 8001a52 <bmm350_get_regs+0x84>
{
reg_data[index] = temp_buf[index + BMM350_DUMMY_BYTES];
8001a30: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
8001a34: 1c9a adds r2, r3, #2
8001a36: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
8001a3a: 68b9 ldr r1, [r7, #8]
8001a3c: 440b add r3, r1
8001a3e: 3298 adds r2, #152 @ 0x98
8001a40: 443a add r2, r7
8001a42: f812 2c88 ldrb.w r2, [r2, #-136]
8001a46: 701a strb r2, [r3, #0]
index++;
8001a48: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
8001a4c: 3301 adds r3, #1
8001a4e: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
while (index < len)
8001a52: f8b7 2094 ldrh.w r2, [r7, #148] @ 0x94
8001a56: 89bb ldrh r3, [r7, #12]
8001a58: 429a cmp r2, r3
8001a5a: d3e9 bcc.n 8001a30 <bmm350_get_regs+0x62>
if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS)
8001a5c: e006 b.n 8001a6c <bmm350_get_regs+0x9e>
}
}
else
{
rslt = BMM350_E_COM_FAIL;
8001a5e: 23fe movs r3, #254 @ 0xfe
8001a60: f887 3097 strb.w r3, [r7, #151] @ 0x97
if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS)
8001a64: e002 b.n 8001a6c <bmm350_get_regs+0x9e>
}
}
else
{
rslt = BMM350_E_NULL_PTR;
8001a66: 23ff movs r3, #255 @ 0xff
8001a68: f887 3097 strb.w r3, [r7, #151] @ 0x97
}
return rslt;
8001a6c: f997 3097 ldrsb.w r3, [r7, #151] @ 0x97
}
8001a70: 4618 mov r0, r3
8001a72: 379c adds r7, #156 @ 0x9c
8001a74: 46bd mov sp, r7
8001a76: bd90 pop {r4, r7, pc}
08001a78 <bmm350_delay_us>:
/*!
* @brief This function provides the delay for required time (Microsecond) as per the input provided in some of the
* APIs.
*/
int8_t bmm350_delay_us(uint32_t period_us, const struct bmm350_dev *dev)
{
8001a78: b580 push {r7, lr}
8001a7a: b084 sub sp, #16
8001a7c: af00 add r7, sp, #0
8001a7e: 6078 str r0, [r7, #4]
8001a80: 6039 str r1, [r7, #0]
/* Variable to store the function result */
int8_t rslt;
/* Check for null pointer in the device structure */
rslt = null_ptr_check(dev);
8001a82: 6838 ldr r0, [r7, #0]
8001a84: f000 fbdd bl 8002242 <null_ptr_check>
8001a88: 4603 mov r3, r0
8001a8a: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001a8c: f997 300f ldrsb.w r3, [r7, #15]
8001a90: 2b00 cmp r3, #0
8001a92: d106 bne.n 8001aa2 <bmm350_delay_us+0x2a>
{
dev->delay_us(period_us, dev->intf_ptr);
8001a94: 683b ldr r3, [r7, #0]
8001a96: 691b ldr r3, [r3, #16]
8001a98: 683a ldr r2, [r7, #0]
8001a9a: 6812 ldr r2, [r2, #0]
8001a9c: 4611 mov r1, r2
8001a9e: 6878 ldr r0, [r7, #4]
8001aa0: 4798 blx r3
}
return rslt;
8001aa2: f997 300f ldrsb.w r3, [r7, #15]
}
8001aa6: 4618 mov r0, r3
8001aa8: 3710 adds r7, #16
8001aaa: 46bd mov sp, r7
8001aac: bd80 pop {r7, pc}
08001aae <bmm350_set_powermode>:
/*!
* @brief This API is used to set the power mode of the sensor
*/
int8_t bmm350_set_powermode(enum bmm350_power_modes powermode, struct bmm350_dev *dev)
{
8001aae: b580 push {r7, lr}
8001ab0: b084 sub sp, #16
8001ab2: af00 add r7, sp, #0
8001ab4: 4603 mov r3, r0
8001ab6: 6039 str r1, [r7, #0]
8001ab8: 71fb strb r3, [r7, #7]
uint8_t last_pwr_mode;
uint8_t reg_data;
/* Check for null pointer in the device structure */
rslt = null_ptr_check(dev);
8001aba: 6838 ldr r0, [r7, #0]
8001abc: f000 fbc1 bl 8002242 <null_ptr_check>
8001ac0: 4603 mov r3, r0
8001ac2: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001ac4: f997 300f ldrsb.w r3, [r7, #15]
8001ac8: 2b00 cmp r3, #0
8001aca: d13c bne.n 8001b46 <bmm350_set_powermode+0x98>
{
rslt = bmm350_get_regs(BMM350_REG_PMU_CMD, &last_pwr_mode, 1, dev);
8001acc: f107 010e add.w r1, r7, #14
8001ad0: 683b ldr r3, [r7, #0]
8001ad2: 2201 movs r2, #1
8001ad4: 2006 movs r0, #6
8001ad6: f7ff ff7a bl 80019ce <bmm350_get_regs>
8001ada: 4603 mov r3, r0
8001adc: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001ade: f997 300f ldrsb.w r3, [r7, #15]
8001ae2: 2b00 cmp r3, #0
8001ae4: d12f bne.n 8001b46 <bmm350_set_powermode+0x98>
{
if (last_pwr_mode > BMM350_PMU_CMD_BR_FAST)
8001ae6: 7bbb ldrb r3, [r7, #14]
8001ae8: 2b08 cmp r3, #8
8001aea: d901 bls.n 8001af0 <bmm350_set_powermode+0x42>
{
rslt = BMM350_E_INVALID_CONFIG;
8001aec: 23fc movs r3, #252 @ 0xfc
8001aee: 73fb strb r3, [r7, #15]
}
if ((rslt == BMM350_OK) &&
8001af0: f997 300f ldrsb.w r3, [r7, #15]
8001af4: 2b00 cmp r3, #0
8001af6: d11b bne.n 8001b30 <bmm350_set_powermode+0x82>
((last_pwr_mode == BMM350_PMU_CMD_NM) || (last_pwr_mode == BMM350_PMU_CMD_UPD_OAE)))
8001af8: 7bbb ldrb r3, [r7, #14]
if ((rslt == BMM350_OK) &&
8001afa: 2b01 cmp r3, #1
8001afc: d002 beq.n 8001b04 <bmm350_set_powermode+0x56>
((last_pwr_mode == BMM350_PMU_CMD_NM) || (last_pwr_mode == BMM350_PMU_CMD_UPD_OAE)))
8001afe: 7bbb ldrb r3, [r7, #14]
8001b00: 2b02 cmp r3, #2
8001b02: d115 bne.n 8001b30 <bmm350_set_powermode+0x82>
{
reg_data = BMM350_PMU_CMD_SUS;
8001b04: 2300 movs r3, #0
8001b06: 737b strb r3, [r7, #13]
/* Set PMU command configuration */
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &reg_data, 1, dev);
8001b08: f107 010d add.w r1, r7, #13
8001b0c: 683b ldr r3, [r7, #0]
8001b0e: 2201 movs r2, #1
8001b10: 2006 movs r0, #6
8001b12: f7ff ff28 bl 8001966 <bmm350_set_regs>
8001b16: 4603 mov r3, r0
8001b18: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001b1a: f997 300f ldrsb.w r3, [r7, #15]
8001b1e: 2b00 cmp r3, #0
8001b20: d106 bne.n 8001b30 <bmm350_set_powermode+0x82>
{
rslt = bmm350_delay_us(BMM350_GOTO_SUSPEND_DELAY, dev);
8001b22: 6839 ldr r1, [r7, #0]
8001b24: f241 7070 movw r0, #6000 @ 0x1770
8001b28: f7ff ffa6 bl 8001a78 <bmm350_delay_us>
8001b2c: 4603 mov r3, r0
8001b2e: 73fb strb r3, [r7, #15]
}
}
if (rslt == BMM350_OK)
8001b30: f997 300f ldrsb.w r3, [r7, #15]
8001b34: 2b00 cmp r3, #0
8001b36: d106 bne.n 8001b46 <bmm350_set_powermode+0x98>
{
rslt = set_powermode(powermode, dev);
8001b38: 79fb ldrb r3, [r7, #7]
8001b3a: 6839 ldr r1, [r7, #0]
8001b3c: 4618 mov r0, r3
8001b3e: f000 ff93 bl 8002a68 <set_powermode>
8001b42: 4603 mov r3, r0
8001b44: 73fb strb r3, [r7, #15]
}
}
}
return rslt;
8001b46: f997 300f ldrsb.w r3, [r7, #15]
}
8001b4a: 4618 mov r0, r3
8001b4c: 3710 adds r7, #16
8001b4e: 46bd mov sp, r7
8001b50: bd80 pop {r7, pc}
08001b52 <bmm350_set_odr_performance>:
* @brief This API sets the ODR and averaging factor.
*/
int8_t bmm350_set_odr_performance(enum bmm350_data_rates odr,
enum bmm350_performance_parameters performance,
struct bmm350_dev *dev)
{
8001b52: b580 push {r7, lr}
8001b54: b084 sub sp, #16
8001b56: af00 add r7, sp, #0
8001b58: 4603 mov r3, r0
8001b5a: 603a str r2, [r7, #0]
8001b5c: 71fb strb r3, [r7, #7]
8001b5e: 460b mov r3, r1
8001b60: 71bb strb r3, [r7, #6]
/* Variable to store the function result */
int8_t rslt;
/* Variable to get PMU command */
uint8_t reg_data = 0;
8001b62: 2300 movs r3, #0
8001b64: 737b strb r3, [r7, #13]
enum bmm350_performance_parameters performance_fix = performance;
8001b66: 79bb ldrb r3, [r7, #6]
8001b68: 73bb strb r3, [r7, #14]
/* Check for null pointer in the device structure */
rslt = null_ptr_check(dev);
8001b6a: 6838 ldr r0, [r7, #0]
8001b6c: f000 fb69 bl 8002242 <null_ptr_check>
8001b70: 4603 mov r3, r0
8001b72: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001b74: f997 300f ldrsb.w r3, [r7, #15]
8001b78: 2b00 cmp r3, #0
8001b7a: d151 bne.n 8001c20 <bmm350_set_odr_performance+0xce>
{
/* Reduce the performance setting when too high for the chosen ODR */
if ((odr == BMM350_DATA_RATE_400HZ) && (performance >= BMM350_AVERAGING_2))
8001b7c: 79fb ldrb r3, [r7, #7]
8001b7e: 2b02 cmp r3, #2
8001b80: d105 bne.n 8001b8e <bmm350_set_odr_performance+0x3c>
8001b82: 79bb ldrb r3, [r7, #6]
8001b84: 2b00 cmp r3, #0
8001b86: d002 beq.n 8001b8e <bmm350_set_odr_performance+0x3c>
{
performance_fix = BMM350_NO_AVERAGING;
8001b88: 2300 movs r3, #0
8001b8a: 73bb strb r3, [r7, #14]
8001b8c: e010 b.n 8001bb0 <bmm350_set_odr_performance+0x5e>
}
else if ((odr == BMM350_DATA_RATE_200HZ) && (performance >= BMM350_AVERAGING_4))
8001b8e: 79fb ldrb r3, [r7, #7]
8001b90: 2b03 cmp r3, #3
8001b92: d105 bne.n 8001ba0 <bmm350_set_odr_performance+0x4e>
8001b94: 79bb ldrb r3, [r7, #6]
8001b96: 2b01 cmp r3, #1
8001b98: d902 bls.n 8001ba0 <bmm350_set_odr_performance+0x4e>
{
performance_fix = BMM350_AVERAGING_2;
8001b9a: 2301 movs r3, #1
8001b9c: 73bb strb r3, [r7, #14]
8001b9e: e007 b.n 8001bb0 <bmm350_set_odr_performance+0x5e>
}
else if ((odr == BMM350_DATA_RATE_100HZ) && (performance >= BMM350_AVERAGING_8))
8001ba0: 79fb ldrb r3, [r7, #7]
8001ba2: 2b04 cmp r3, #4
8001ba4: d104 bne.n 8001bb0 <bmm350_set_odr_performance+0x5e>
8001ba6: 79bb ldrb r3, [r7, #6]
8001ba8: 2b02 cmp r3, #2
8001baa: d901 bls.n 8001bb0 <bmm350_set_odr_performance+0x5e>
{
performance_fix = BMM350_AVERAGING_4;
8001bac: 2302 movs r3, #2
8001bae: 73bb strb r3, [r7, #14]
}
/* ODR is an enum taking the generated constants from the register map */
reg_data = ((uint8_t)odr & BMM350_ODR_MSK);
8001bb0: 79fb ldrb r3, [r7, #7]
8001bb2: f003 030f and.w r3, r3, #15
8001bb6: b2db uxtb r3, r3
8001bb8: 737b strb r3, [r7, #13]
/* AVG / performance is an enum taking the generated constants from the register map */
reg_data = BMM350_SET_BITS(reg_data, BMM350_AVG, (uint8_t)performance_fix);
8001bba: 7b7b ldrb r3, [r7, #13]
8001bbc: b25b sxtb r3, r3
8001bbe: f023 0330 bic.w r3, r3, #48 @ 0x30
8001bc2: b25a sxtb r2, r3
8001bc4: f997 300e ldrsb.w r3, [r7, #14]
8001bc8: 011b lsls r3, r3, #4
8001bca: b25b sxtb r3, r3
8001bcc: f003 0330 and.w r3, r3, #48 @ 0x30
8001bd0: b25b sxtb r3, r3
8001bd2: 4313 orrs r3, r2
8001bd4: b25b sxtb r3, r3
8001bd6: b2db uxtb r3, r3
8001bd8: 737b strb r3, [r7, #13]
/* Set PMU command configurations for ODR and performance */
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD_AGGR_SET, &reg_data, 1, dev);
8001bda: f107 010d add.w r1, r7, #13
8001bde: 683b ldr r3, [r7, #0]
8001be0: 2201 movs r2, #1
8001be2: 2004 movs r0, #4
8001be4: f7ff febf bl 8001966 <bmm350_set_regs>
8001be8: 4603 mov r3, r0
8001bea: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001bec: f997 300f ldrsb.w r3, [r7, #15]
8001bf0: 2b00 cmp r3, #0
8001bf2: d115 bne.n 8001c20 <bmm350_set_odr_performance+0xce>
{
/* Set PMU command configurations to update odr and average */
reg_data = BMM350_PMU_CMD_UPD_OAE;
8001bf4: 2302 movs r3, #2
8001bf6: 737b strb r3, [r7, #13]
/* Set PMU command configuration */
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &reg_data, 1, dev);
8001bf8: f107 010d add.w r1, r7, #13
8001bfc: 683b ldr r3, [r7, #0]
8001bfe: 2201 movs r2, #1
8001c00: 2006 movs r0, #6
8001c02: f7ff feb0 bl 8001966 <bmm350_set_regs>
8001c06: 4603 mov r3, r0
8001c08: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
8001c0a: f997 300f ldrsb.w r3, [r7, #15]
8001c0e: 2b00 cmp r3, #0
8001c10: d106 bne.n 8001c20 <bmm350_set_odr_performance+0xce>
{
rslt = bmm350_delay_us(BMM350_UPD_OAE_DELAY, dev);
8001c12: 6839 ldr r1, [r7, #0]
8001c14: f44f 707a mov.w r0, #1000 @ 0x3e8
8001c18: f7ff ff2e bl 8001a78 <bmm350_delay_us>
8001c1c: 4603 mov r3, r0
8001c1e: 73fb strb r3, [r7, #15]
}
}
}
return rslt;
8001c20: f997 300f ldrsb.w r3, [r7, #15]
}
8001c24: 4618 mov r0, r3
8001c26: 3710 adds r7, #16
8001c28: 46bd mov sp, r7
8001c2a: bd80 pop {r7, pc}
08001c2c <bmm350_read_uncomp_mag_temp_data>:
/*!
* @brief This API is used to read uncompensated mag and temperature data.
*/
int8_t bmm350_read_uncomp_mag_temp_data(struct bmm350_raw_mag_data *raw_data, struct bmm350_dev *dev)
{
8001c2c: b580 push {r7, lr}
8001c2e: b08a sub sp, #40 @ 0x28
8001c30: af00 add r7, sp, #0
8001c32: 6078 str r0, [r7, #4]
8001c34: 6039 str r1, [r7, #0]
/* Variable to store the function result */
int8_t rslt;
uint8_t mag_data[12] = { 0 };
8001c36: f107 0308 add.w r3, r7, #8
8001c3a: 2200 movs r2, #0
8001c3c: 601a str r2, [r3, #0]
8001c3e: 605a str r2, [r3, #4]
8001c40: 609a str r2, [r3, #8]
uint32_t raw_mag_x, raw_mag_y, raw_mag_z, raw_temp;
if (raw_data != NULL)
8001c42: 687b ldr r3, [r7, #4]
8001c44: 2b00 cmp r3, #0
8001c46: d06c beq.n 8001d22 <bmm350_read_uncomp_mag_temp_data+0xf6>
{
/* Get uncompensated mag data */
rslt = bmm350_get_regs(BMM350_REG_MAG_X_XLSB, mag_data, BMM350_MAG_TEMP_DATA_LEN, dev);
8001c48: f107 0108 add.w r1, r7, #8
8001c4c: 683b ldr r3, [r7, #0]
8001c4e: 220c movs r2, #12
8001c50: 2031 movs r0, #49 @ 0x31
8001c52: f7ff febc bl 80019ce <bmm350_get_regs>
8001c56: 4603 mov r3, r0
8001c58: f887 3027 strb.w r3, [r7, #39] @ 0x27
if (rslt == BMM350_OK)
8001c5c: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27
8001c60: 2b00 cmp r3, #0
8001c62: d161 bne.n 8001d28 <bmm350_read_uncomp_mag_temp_data+0xfc>
{
raw_mag_x = (uint32_t)mag_data[0] + ((uint32_t)mag_data[1] << 8) + ((uint32_t)mag_data[2] << 16);
8001c64: 7a3b ldrb r3, [r7, #8]
8001c66: 461a mov r2, r3
8001c68: 7a7b ldrb r3, [r7, #9]
8001c6a: 021b lsls r3, r3, #8
8001c6c: 441a add r2, r3
8001c6e: 7abb ldrb r3, [r7, #10]
8001c70: 041b lsls r3, r3, #16
8001c72: 4413 add r3, r2
8001c74: 623b str r3, [r7, #32]
raw_mag_y = (uint32_t)mag_data[3] + ((uint32_t)mag_data[4] << 8) + ((uint32_t)mag_data[5] << 16);
8001c76: 7afb ldrb r3, [r7, #11]
8001c78: 461a mov r2, r3
8001c7a: 7b3b ldrb r3, [r7, #12]
8001c7c: 021b lsls r3, r3, #8
8001c7e: 441a add r2, r3
8001c80: 7b7b ldrb r3, [r7, #13]
8001c82: 041b lsls r3, r3, #16
8001c84: 4413 add r3, r2
8001c86: 61fb str r3, [r7, #28]
raw_mag_z = (uint32_t)mag_data[6] + ((uint32_t)mag_data[7] << 8) + ((uint32_t)mag_data[8] << 16);
8001c88: 7bbb ldrb r3, [r7, #14]
8001c8a: 461a mov r2, r3
8001c8c: 7bfb ldrb r3, [r7, #15]
8001c8e: 021b lsls r3, r3, #8
8001c90: 441a add r2, r3
8001c92: 7c3b ldrb r3, [r7, #16]
8001c94: 041b lsls r3, r3, #16
8001c96: 4413 add r3, r2
8001c98: 61bb str r3, [r7, #24]
raw_temp = (uint32_t)mag_data[9] + ((uint32_t)mag_data[10] << 8) + ((uint32_t)mag_data[11] << 16);
8001c9a: 7c7b ldrb r3, [r7, #17]
8001c9c: 461a mov r2, r3
8001c9e: 7cbb ldrb r3, [r7, #18]
8001ca0: 021b lsls r3, r3, #8
8001ca2: 441a add r2, r3
8001ca4: 7cfb ldrb r3, [r7, #19]
8001ca6: 041b lsls r3, r3, #16
8001ca8: 4413 add r3, r2
8001caa: 617b str r3, [r7, #20]
if ((dev->axis_en & BMM350_EN_X_MSK) == BMM350_DISABLE)
8001cac: 683b ldr r3, [r7, #0]
8001cae: 7d5b ldrb r3, [r3, #21]
8001cb0: f003 0301 and.w r3, r3, #1
8001cb4: 2b00 cmp r3, #0
8001cb6: d103 bne.n 8001cc0 <bmm350_read_uncomp_mag_temp_data+0x94>
{
raw_data->raw_xdata = BMM350_DISABLE;
8001cb8: 687b ldr r3, [r7, #4]
8001cba: 2200 movs r2, #0
8001cbc: 601a str r2, [r3, #0]
8001cbe: e006 b.n 8001cce <bmm350_read_uncomp_mag_temp_data+0xa2>
}
else
{
raw_data->raw_xdata = fix_sign(raw_mag_x, BMM350_SIGNED_24_BIT);
8001cc0: 2118 movs r1, #24
8001cc2: 6a38 ldr r0, [r7, #32]
8001cc4: f000 fade bl 8002284 <fix_sign>
8001cc8: 4602 mov r2, r0
8001cca: 687b ldr r3, [r7, #4]
8001ccc: 601a str r2, [r3, #0]
}
if ((dev->axis_en & BMM350_EN_Y_MSK) == BMM350_DISABLE)
8001cce: 683b ldr r3, [r7, #0]
8001cd0: 7d5b ldrb r3, [r3, #21]
8001cd2: f003 0302 and.w r3, r3, #2
8001cd6: 2b00 cmp r3, #0
8001cd8: d103 bne.n 8001ce2 <bmm350_read_uncomp_mag_temp_data+0xb6>
{
raw_data->raw_ydata = BMM350_DISABLE;
8001cda: 687b ldr r3, [r7, #4]
8001cdc: 2200 movs r2, #0
8001cde: 605a str r2, [r3, #4]
8001ce0: e006 b.n 8001cf0 <bmm350_read_uncomp_mag_temp_data+0xc4>
}
else
{
raw_data->raw_ydata = fix_sign(raw_mag_y, BMM350_SIGNED_24_BIT);
8001ce2: 2118 movs r1, #24
8001ce4: 69f8 ldr r0, [r7, #28]
8001ce6: f000 facd bl 8002284 <fix_sign>
8001cea: 4602 mov r2, r0
8001cec: 687b ldr r3, [r7, #4]
8001cee: 605a str r2, [r3, #4]
}
if ((dev->axis_en & BMM350_EN_Z_MSK) == BMM350_DISABLE)
8001cf0: 683b ldr r3, [r7, #0]
8001cf2: 7d5b ldrb r3, [r3, #21]
8001cf4: f003 0304 and.w r3, r3, #4
8001cf8: 2b00 cmp r3, #0
8001cfa: d103 bne.n 8001d04 <bmm350_read_uncomp_mag_temp_data+0xd8>
{
raw_data->raw_zdata = BMM350_DISABLE;
8001cfc: 687b ldr r3, [r7, #4]
8001cfe: 2200 movs r2, #0
8001d00: 609a str r2, [r3, #8]
8001d02: e006 b.n 8001d12 <bmm350_read_uncomp_mag_temp_data+0xe6>
}
else
{
raw_data->raw_zdata = fix_sign(raw_mag_z, BMM350_SIGNED_24_BIT);
8001d04: 2118 movs r1, #24
8001d06: 69b8 ldr r0, [r7, #24]
8001d08: f000 fabc bl 8002284 <fix_sign>
8001d0c: 4602 mov r2, r0
8001d0e: 687b ldr r3, [r7, #4]
8001d10: 609a str r2, [r3, #8]
}
raw_data->raw_data_t = fix_sign(raw_temp, BMM350_SIGNED_24_BIT);
8001d12: 2118 movs r1, #24
8001d14: 6978 ldr r0, [r7, #20]
8001d16: f000 fab5 bl 8002284 <fix_sign>
8001d1a: 4602 mov r2, r0
8001d1c: 687b ldr r3, [r7, #4]
8001d1e: 60da str r2, [r3, #12]
8001d20: e002 b.n 8001d28 <bmm350_read_uncomp_mag_temp_data+0xfc>
}
}
else
{
rslt = BMM350_E_NULL_PTR;
8001d22: 23ff movs r3, #255 @ 0xff
8001d24: f887 3027 strb.w r3, [r7, #39] @ 0x27
}
return rslt;
8001d28: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27
}
8001d2c: 4618 mov r0, r3
8001d2e: 3728 adds r7, #40 @ 0x28
8001d30: 46bd mov sp, r7
8001d32: bd80 pop {r7, pc}
08001d34 <bmm350_magnetic_reset_and_wait>:
* @brief This API is used to perform the magnetic reset of the sensor
* which is necessary after a field shock (400mT field applied to sensor).
* It sends flux guide or bit reset to the device in suspend mode.
*/
int8_t bmm350_magnetic_reset_and_wait(struct bmm350_dev *dev)
{
8001d34: b580 push {r7, lr}
8001d36: b086 sub sp, #24
8001d38: af00 add r7, sp, #0
8001d3a: 6078 str r0, [r7, #4]
/* Variable to store the function result */
int8_t rslt;
uint8_t pmu_cmd = 0;
8001d3c: 2300 movs r3, #0
8001d3e: 757b strb r3, [r7, #21]
struct bmm350_pmu_cmd_status_0 pmu_cmd_stat_0 = { 0 };
8001d40: f107 030c add.w r3, r7, #12
8001d44: 2200 movs r2, #0
8001d46: 601a str r2, [r3, #0]
8001d48: 809a strh r2, [r3, #4]
uint8_t restore_normal = BMM350_DISABLE;
8001d4a: 2300 movs r3, #0
8001d4c: 75bb strb r3, [r7, #22]
rslt = null_ptr_check(dev);
8001d4e: 6878 ldr r0, [r7, #4]
8001d50: f000 fa77 bl 8002242 <null_ptr_check>
8001d54: 4603 mov r3, r0
8001d56: 75fb strb r3, [r7, #23]
if ((rslt == BMM350_OK) && (dev->mraw_override))
8001d58: f997 3017 ldrsb.w r3, [r7, #23]
8001d5c: 2b00 cmp r3, #0
8001d5e: d10c bne.n 8001d7a <bmm350_magnetic_reset_and_wait+0x46>
8001d60: 687b ldr r3, [r7, #4]
8001d62: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8
8001d66: 2b00 cmp r3, #0
8001d68: d007 beq.n 8001d7a <bmm350_magnetic_reset_and_wait+0x46>
{
rslt = dev->mraw_override(dev);
8001d6a: 687b ldr r3, [r7, #4]
8001d6c: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8
8001d70: 6878 ldr r0, [r7, #4]
8001d72: 4798 blx r3
8001d74: 4603 mov r3, r0
8001d76: 75fb strb r3, [r7, #23]
8001d78: e081 b.n 8001e7e <bmm350_magnetic_reset_and_wait+0x14a>
}
else
{
/* Read PMU CMD status */
rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev);
8001d7a: f107 030c add.w r3, r7, #12
8001d7e: 6879 ldr r1, [r7, #4]
8001d80: 4618 mov r0, r3
8001d82: f000 fa15 bl 80021b0 <bmm350_get_pmu_cmd_status_0>
8001d86: 4603 mov r3, r0
8001d88: 75fb strb r3, [r7, #23]
/* Check the powermode is normal before performing magnetic reset */
if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pwr_mode_is_normal == BMM350_ENABLE))
8001d8a: f997 3017 ldrsb.w r3, [r7, #23]
8001d8e: 2b00 cmp r3, #0
8001d90: d10a bne.n 8001da8 <bmm350_magnetic_reset_and_wait+0x74>
8001d92: 7bfb ldrb r3, [r7, #15]
8001d94: 2b01 cmp r3, #1
8001d96: d107 bne.n 8001da8 <bmm350_magnetic_reset_and_wait+0x74>
{
restore_normal = BMM350_ENABLE;
8001d98: 2301 movs r3, #1
8001d9a: 75bb strb r3, [r7, #22]
/* Reset can only be triggered in suspend */
rslt = bmm350_set_powermode(BMM350_SUSPEND_MODE, dev);
8001d9c: 6879 ldr r1, [r7, #4]
8001d9e: 2000 movs r0, #0
8001da0: f7ff fe85 bl 8001aae <bmm350_set_powermode>
8001da4: 4603 mov r3, r0
8001da6: 75fb strb r3, [r7, #23]
}
if (rslt == BMM350_OK)
8001da8: f997 3017 ldrsb.w r3, [r7, #23]
8001dac: 2b00 cmp r3, #0
8001dae: d115 bne.n 8001ddc <bmm350_magnetic_reset_and_wait+0xa8>
{
/* Set BR to PMU_CMD register */
pmu_cmd = BMM350_PMU_CMD_BR;
8001db0: 2307 movs r3, #7
8001db2: 757b strb r3, [r7, #21]
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &pmu_cmd, 1, dev);
8001db4: f107 0115 add.w r1, r7, #21
8001db8: 687b ldr r3, [r7, #4]
8001dba: 2201 movs r2, #1
8001dbc: 2006 movs r0, #6
8001dbe: f7ff fdd2 bl 8001966 <bmm350_set_regs>
8001dc2: 4603 mov r3, r0
8001dc4: 75fb strb r3, [r7, #23]
if (rslt == BMM350_OK)
8001dc6: f997 3017 ldrsb.w r3, [r7, #23]
8001dca: 2b00 cmp r3, #0
8001dcc: d106 bne.n 8001ddc <bmm350_magnetic_reset_and_wait+0xa8>
{
rslt = bmm350_delay_us(BMM350_BR_DELAY, dev);
8001dce: 6879 ldr r1, [r7, #4]
8001dd0: f243 60b0 movw r0, #14000 @ 0x36b0
8001dd4: f7ff fe50 bl 8001a78 <bmm350_delay_us>
8001dd8: 4603 mov r3, r0
8001dda: 75fb strb r3, [r7, #23]
}
}
if (rslt == BMM350_OK)
8001ddc: f997 3017 ldrsb.w r3, [r7, #23]
8001de0: 2b00 cmp r3, #0
8001de2: d110 bne.n 8001e06 <bmm350_magnetic_reset_and_wait+0xd2>
{
/* Verify if PMU_CMD_STATUS_0 register has BR set */
rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev);
8001de4: f107 030c add.w r3, r7, #12
8001de8: 6879 ldr r1, [r7, #4]
8001dea: 4618 mov r0, r3
8001dec: f000 f9e0 bl 80021b0 <bmm350_get_pmu_cmd_status_0>
8001df0: 4603 mov r3, r0
8001df2: 75fb strb r3, [r7, #23]
if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pmu_cmd_value != BMM350_PMU_CMD_STATUS_0_BR))
8001df4: f997 3017 ldrsb.w r3, [r7, #23]
8001df8: 2b00 cmp r3, #0
8001dfa: d104 bne.n 8001e06 <bmm350_magnetic_reset_and_wait+0xd2>
8001dfc: 7c7b ldrb r3, [r7, #17]
8001dfe: 2b07 cmp r3, #7
8001e00: d001 beq.n 8001e06 <bmm350_magnetic_reset_and_wait+0xd2>
{
rslt = BMM350_E_PMU_CMD_VALUE;
8001e02: 23f0 movs r3, #240 @ 0xf0
8001e04: 75fb strb r3, [r7, #23]
}
}
if (rslt == BMM350_OK)
8001e06: f997 3017 ldrsb.w r3, [r7, #23]
8001e0a: 2b00 cmp r3, #0
8001e0c: d115 bne.n 8001e3a <bmm350_magnetic_reset_and_wait+0x106>
{
/* Set FGR to PMU_CMD register */
pmu_cmd = BMM350_PMU_CMD_FGR;
8001e0e: 2305 movs r3, #5
8001e10: 757b strb r3, [r7, #21]
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &pmu_cmd, 1, dev);
8001e12: f107 0115 add.w r1, r7, #21
8001e16: 687b ldr r3, [r7, #4]
8001e18: 2201 movs r2, #1
8001e1a: 2006 movs r0, #6
8001e1c: f7ff fda3 bl 8001966 <bmm350_set_regs>
8001e20: 4603 mov r3, r0
8001e22: 75fb strb r3, [r7, #23]
if (rslt == BMM350_OK)
8001e24: f997 3017 ldrsb.w r3, [r7, #23]
8001e28: 2b00 cmp r3, #0
8001e2a: d106 bne.n 8001e3a <bmm350_magnetic_reset_and_wait+0x106>
{
rslt = bmm350_delay_us(BMM350_FGR_DELAY, dev);
8001e2c: 6879 ldr r1, [r7, #4]
8001e2e: f244 6050 movw r0, #18000 @ 0x4650
8001e32: f7ff fe21 bl 8001a78 <bmm350_delay_us>
8001e36: 4603 mov r3, r0
8001e38: 75fb strb r3, [r7, #23]
}
}
if (rslt == BMM350_OK)
8001e3a: f997 3017 ldrsb.w r3, [r7, #23]
8001e3e: 2b00 cmp r3, #0
8001e40: d110 bne.n 8001e64 <bmm350_magnetic_reset_and_wait+0x130>
{
/* Verify if PMU_CMD_STATUS_0 register has FGR set */
rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev);
8001e42: f107 030c add.w r3, r7, #12
8001e46: 6879 ldr r1, [r7, #4]
8001e48: 4618 mov r0, r3
8001e4a: f000 f9b1 bl 80021b0 <bmm350_get_pmu_cmd_status_0>
8001e4e: 4603 mov r3, r0
8001e50: 75fb strb r3, [r7, #23]
if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pmu_cmd_value != BMM350_PMU_CMD_STATUS_0_FGR))
8001e52: f997 3017 ldrsb.w r3, [r7, #23]
8001e56: 2b00 cmp r3, #0
8001e58: d104 bne.n 8001e64 <bmm350_magnetic_reset_and_wait+0x130>
8001e5a: 7c7b ldrb r3, [r7, #17]
8001e5c: 2b05 cmp r3, #5
8001e5e: d001 beq.n 8001e64 <bmm350_magnetic_reset_and_wait+0x130>
{
rslt = BMM350_E_PMU_CMD_VALUE;
8001e60: 23f0 movs r3, #240 @ 0xf0
8001e62: 75fb strb r3, [r7, #23]
}
}
if ((rslt == BMM350_OK) && (restore_normal == BMM350_ENABLE))
8001e64: f997 3017 ldrsb.w r3, [r7, #23]
8001e68: 2b00 cmp r3, #0
8001e6a: d108 bne.n 8001e7e <bmm350_magnetic_reset_and_wait+0x14a>
8001e6c: 7dbb ldrb r3, [r7, #22]
8001e6e: 2b01 cmp r3, #1
8001e70: d105 bne.n 8001e7e <bmm350_magnetic_reset_and_wait+0x14a>
{
rslt = bmm350_set_powermode(BMM350_NORMAL_MODE, dev);
8001e72: 6879 ldr r1, [r7, #4]
8001e74: 2001 movs r0, #1
8001e76: f7ff fe1a bl 8001aae <bmm350_set_powermode>
8001e7a: 4603 mov r3, r0
8001e7c: 75fb strb r3, [r7, #23]
}
}
return rslt;
8001e7e: f997 3017 ldrsb.w r3, [r7, #23]
}
8001e82: 4618 mov r0, r3
8001e84: 3718 adds r7, #24
8001e86: 46bd mov sp, r7
8001e88: bd80 pop {r7, pc}
08001e8a <bmm350_get_compensated_mag_xyz_temp_data>:
/*!
* @brief This API is used to perform compensation for raw magnetometer and temperature data.
*/
int8_t bmm350_get_compensated_mag_xyz_temp_data(struct bmm350_mag_temp_data *mag_temp_data, struct bmm350_dev *dev)
{
8001e8a: b580 push {r7, lr}
8001e8c: b096 sub sp, #88 @ 0x58
8001e8e: af00 add r7, sp, #0
8001e90: 6078 str r0, [r7, #4]
8001e92: 6039 str r1, [r7, #0]
/* Variable to store the function result */
int8_t rslt;
uint8_t indx;
float out_data[4] = { 0.0f };
8001e94: f107 0338 add.w r3, r7, #56 @ 0x38
8001e98: 2200 movs r2, #0
8001e9a: 601a str r2, [r3, #0]
8001e9c: 605a str r2, [r3, #4]
8001e9e: 609a str r2, [r3, #8]
8001ea0: 60da str r2, [r3, #12]
float dut_offset_coef[3], dut_sensit_coef[3], dut_tco[3], dut_tcs[3];
float cr_ax_comp_x, cr_ax_comp_y, cr_ax_comp_z;
if (mag_temp_data != NULL)
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 2b00 cmp r3, #0
8001ea6: f000 817a beq.w 800219e <bmm350_get_compensated_mag_xyz_temp_data+0x314>
{
/* Reads raw magnetic x,y and z axis along with temperature */
rslt = read_out_raw_data(out_data, dev);
8001eaa: f107 0338 add.w r3, r7, #56 @ 0x38
8001eae: 6839 ldr r1, [r7, #0]
8001eb0: 4618 mov r0, r3
8001eb2: f000 fc9d bl 80027f0 <read_out_raw_data>
8001eb6: 4603 mov r3, r0
8001eb8: f887 3057 strb.w r3, [r7, #87] @ 0x57
if (rslt == BMM350_OK)
8001ebc: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57
8001ec0: 2b00 cmp r3, #0
8001ec2: f040 813a bne.w 800213a <bmm350_get_compensated_mag_xyz_temp_data+0x2b0>
{
/* Apply compensation to temperature reading */
out_data[3] = (1 + dev->mag_comp.dut_sensit_coef.t_sens) * out_data[3] +
8001ec6: 683b ldr r3, [r7, #0]
8001ec8: edd3 7a0a vldr s15, [r3, #40] @ 0x28
8001ecc: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
8001ed0: ee37 7a87 vadd.f32 s14, s15, s14
8001ed4: edd7 7a11 vldr s15, [r7, #68] @ 0x44
8001ed8: ee27 7a27 vmul.f32 s14, s14, s15
dev->mag_comp.dut_offset_coef.t_offs;
8001edc: 683b ldr r3, [r7, #0]
8001ede: edd3 7a06 vldr s15, [r3, #24]
out_data[3] = (1 + dev->mag_comp.dut_sensit_coef.t_sens) * out_data[3] +
8001ee2: ee77 7a27 vadd.f32 s15, s14, s15
8001ee6: edc7 7a11 vstr s15, [r7, #68] @ 0x44
/* Store magnetic compensation structure to an array */
dut_offset_coef[0] = dev->mag_comp.dut_offset_coef.offset_x;
8001eea: 683b ldr r3, [r7, #0]
8001eec: 69db ldr r3, [r3, #28]
8001eee: 62fb str r3, [r7, #44] @ 0x2c
dut_offset_coef[1] = dev->mag_comp.dut_offset_coef.offset_y;
8001ef0: 683b ldr r3, [r7, #0]
8001ef2: 6a1b ldr r3, [r3, #32]
8001ef4: 633b str r3, [r7, #48] @ 0x30
dut_offset_coef[2] = dev->mag_comp.dut_offset_coef.offset_z;
8001ef6: 683b ldr r3, [r7, #0]
8001ef8: 6a5b ldr r3, [r3, #36] @ 0x24
8001efa: 637b str r3, [r7, #52] @ 0x34
dut_sensit_coef[0] = dev->mag_comp.dut_sensit_coef.sens_x;
8001efc: 683b ldr r3, [r7, #0]
8001efe: 6adb ldr r3, [r3, #44] @ 0x2c
8001f00: 623b str r3, [r7, #32]
dut_sensit_coef[1] = dev->mag_comp.dut_sensit_coef.sens_y;
8001f02: 683b ldr r3, [r7, #0]
8001f04: 6b1b ldr r3, [r3, #48] @ 0x30
8001f06: 627b str r3, [r7, #36] @ 0x24
dut_sensit_coef[2] = dev->mag_comp.dut_sensit_coef.sens_z;
8001f08: 683b ldr r3, [r7, #0]
8001f0a: 6b5b ldr r3, [r3, #52] @ 0x34
8001f0c: 62bb str r3, [r7, #40] @ 0x28
dut_tco[0] = dev->mag_comp.dut_tco.tco_x;
8001f0e: 683b ldr r3, [r7, #0]
8001f10: 6b9b ldr r3, [r3, #56] @ 0x38
8001f12: 617b str r3, [r7, #20]
dut_tco[1] = dev->mag_comp.dut_tco.tco_y;
8001f14: 683b ldr r3, [r7, #0]
8001f16: 6bdb ldr r3, [r3, #60] @ 0x3c
8001f18: 61bb str r3, [r7, #24]
dut_tco[2] = dev->mag_comp.dut_tco.tco_z;
8001f1a: 683b ldr r3, [r7, #0]
8001f1c: 6c1b ldr r3, [r3, #64] @ 0x40
8001f1e: 61fb str r3, [r7, #28]
dut_tcs[0] = dev->mag_comp.dut_tcs.tcs_x;
8001f20: 683b ldr r3, [r7, #0]
8001f22: 6c5b ldr r3, [r3, #68] @ 0x44
8001f24: 60bb str r3, [r7, #8]
dut_tcs[1] = dev->mag_comp.dut_tcs.tcs_y;
8001f26: 683b ldr r3, [r7, #0]
8001f28: 6c9b ldr r3, [r3, #72] @ 0x48
8001f2a: 60fb str r3, [r7, #12]
dut_tcs[2] = dev->mag_comp.dut_tcs.tcs_z;
8001f2c: 683b ldr r3, [r7, #0]
8001f2e: 6cdb ldr r3, [r3, #76] @ 0x4c
8001f30: 613b str r3, [r7, #16]
/* Compensate raw magnetic data */
for (indx = 0; indx < 3; indx++)
8001f32: 2300 movs r3, #0
8001f34: f887 3056 strb.w r3, [r7, #86] @ 0x56
8001f38: e086 b.n 8002048 <bmm350_get_compensated_mag_xyz_temp_data+0x1be>
{
out_data[indx] *= 1 + dut_sensit_coef[indx];
8001f3a: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001f3e: 009b lsls r3, r3, #2
8001f40: 3358 adds r3, #88 @ 0x58
8001f42: 443b add r3, r7
8001f44: 3b20 subs r3, #32
8001f46: ed93 7a00 vldr s14, [r3]
8001f4a: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001f4e: 009b lsls r3, r3, #2
8001f50: 3358 adds r3, #88 @ 0x58
8001f52: 443b add r3, r7
8001f54: 3b38 subs r3, #56 @ 0x38
8001f56: edd3 7a00 vldr s15, [r3]
8001f5a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8001f5e: ee77 7aa6 vadd.f32 s15, s15, s13
8001f62: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001f66: ee67 7a27 vmul.f32 s15, s14, s15
8001f6a: 009b lsls r3, r3, #2
8001f6c: 3358 adds r3, #88 @ 0x58
8001f6e: 443b add r3, r7
8001f70: 3b20 subs r3, #32
8001f72: edc3 7a00 vstr s15, [r3]
out_data[indx] += dut_offset_coef[indx];
8001f76: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001f7a: 009b lsls r3, r3, #2
8001f7c: 3358 adds r3, #88 @ 0x58
8001f7e: 443b add r3, r7
8001f80: 3b20 subs r3, #32
8001f82: ed93 7a00 vldr s14, [r3]
8001f86: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001f8a: 009b lsls r3, r3, #2
8001f8c: 3358 adds r3, #88 @ 0x58
8001f8e: 443b add r3, r7
8001f90: 3b2c subs r3, #44 @ 0x2c
8001f92: edd3 7a00 vldr s15, [r3]
8001f96: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001f9a: ee77 7a27 vadd.f32 s15, s14, s15
8001f9e: 009b lsls r3, r3, #2
8001fa0: 3358 adds r3, #88 @ 0x58
8001fa2: 443b add r3, r7
8001fa4: 3b20 subs r3, #32
8001fa6: edc3 7a00 vstr s15, [r3]
out_data[indx] += dut_tco[indx] * (out_data[3] - dev->mag_comp.dut_t0);
8001faa: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001fae: 009b lsls r3, r3, #2
8001fb0: 3358 adds r3, #88 @ 0x58
8001fb2: 443b add r3, r7
8001fb4: 3b20 subs r3, #32
8001fb6: ed93 7a00 vldr s14, [r3]
8001fba: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001fbe: 009b lsls r3, r3, #2
8001fc0: 3358 adds r3, #88 @ 0x58
8001fc2: 443b add r3, r7
8001fc4: 3b44 subs r3, #68 @ 0x44
8001fc6: edd3 6a00 vldr s13, [r3]
8001fca: ed97 6a11 vldr s12, [r7, #68] @ 0x44
8001fce: 683b ldr r3, [r7, #0]
8001fd0: edd3 7a14 vldr s15, [r3, #80] @ 0x50
8001fd4: ee76 7a67 vsub.f32 s15, s12, s15
8001fd8: ee66 7aa7 vmul.f32 s15, s13, s15
8001fdc: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001fe0: ee77 7a27 vadd.f32 s15, s14, s15
8001fe4: 009b lsls r3, r3, #2
8001fe6: 3358 adds r3, #88 @ 0x58
8001fe8: 443b add r3, r7
8001fea: 3b20 subs r3, #32
8001fec: edc3 7a00 vstr s15, [r3]
out_data[indx] /= 1 + dut_tcs[indx] * (out_data[3] - dev->mag_comp.dut_t0);
8001ff0: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8001ff4: 009b lsls r3, r3, #2
8001ff6: 3358 adds r3, #88 @ 0x58
8001ff8: 443b add r3, r7
8001ffa: 3b20 subs r3, #32
8001ffc: edd3 6a00 vldr s13, [r3]
8002000: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8002004: 009b lsls r3, r3, #2
8002006: 3358 adds r3, #88 @ 0x58
8002008: 443b add r3, r7
800200a: 3b50 subs r3, #80 @ 0x50
800200c: ed93 7a00 vldr s14, [r3]
8002010: ed97 6a11 vldr s12, [r7, #68] @ 0x44
8002014: 683b ldr r3, [r7, #0]
8002016: edd3 7a14 vldr s15, [r3, #80] @ 0x50
800201a: ee76 7a67 vsub.f32 s15, s12, s15
800201e: ee67 7a27 vmul.f32 s15, s14, s15
8002022: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
8002026: ee37 7a87 vadd.f32 s14, s15, s14
800202a: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
800202e: eec6 7a87 vdiv.f32 s15, s13, s14
8002032: 009b lsls r3, r3, #2
8002034: 3358 adds r3, #88 @ 0x58
8002036: 443b add r3, r7
8002038: 3b20 subs r3, #32
800203a: edc3 7a00 vstr s15, [r3]
for (indx = 0; indx < 3; indx++)
800203e: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
8002042: 3301 adds r3, #1
8002044: f887 3056 strb.w r3, [r7, #86] @ 0x56
8002048: f897 3056 ldrb.w r3, [r7, #86] @ 0x56
800204c: 2b02 cmp r3, #2
800204e: f67f af74 bls.w 8001f3a <bmm350_get_compensated_mag_xyz_temp_data+0xb0>
}
cr_ax_comp_x = (out_data[0] - dev->mag_comp.cross_axis.cross_x_y * out_data[1]) /
8002052: ed97 7a0e vldr s14, [r7, #56] @ 0x38
8002056: 683b ldr r3, [r7, #0]
8002058: edd3 6a15 vldr s13, [r3, #84] @ 0x54
800205c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
8002060: ee66 7aa7 vmul.f32 s15, s13, s15
8002064: ee77 6a67 vsub.f32 s13, s14, s15
(1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y);
8002068: 683b ldr r3, [r7, #0]
800206a: ed93 7a16 vldr s14, [r3, #88] @ 0x58
800206e: 683b ldr r3, [r7, #0]
8002070: edd3 7a15 vldr s15, [r3, #84] @ 0x54
8002074: ee67 7a27 vmul.f32 s15, s14, s15
8002078: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
800207c: ee37 7a67 vsub.f32 s14, s14, s15
cr_ax_comp_x = (out_data[0] - dev->mag_comp.cross_axis.cross_x_y * out_data[1]) /
8002080: eec6 7a87 vdiv.f32 s15, s13, s14
8002084: edc7 7a14 vstr s15, [r7, #80] @ 0x50
cr_ax_comp_y = (out_data[1] - dev->mag_comp.cross_axis.cross_y_x * out_data[0]) /
8002088: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
800208c: 683b ldr r3, [r7, #0]
800208e: edd3 6a16 vldr s13, [r3, #88] @ 0x58
8002092: edd7 7a0e vldr s15, [r7, #56] @ 0x38
8002096: ee66 7aa7 vmul.f32 s15, s13, s15
800209a: ee77 6a67 vsub.f32 s13, s14, s15
(1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y);
800209e: 683b ldr r3, [r7, #0]
80020a0: ed93 7a16 vldr s14, [r3, #88] @ 0x58
80020a4: 683b ldr r3, [r7, #0]
80020a6: edd3 7a15 vldr s15, [r3, #84] @ 0x54
80020aa: ee67 7a27 vmul.f32 s15, s14, s15
80020ae: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0
80020b2: ee37 7a67 vsub.f32 s14, s14, s15
cr_ax_comp_y = (out_data[1] - dev->mag_comp.cross_axis.cross_y_x * out_data[0]) /
80020b6: eec6 7a87 vdiv.f32 s15, s13, s14
80020ba: edc7 7a13 vstr s15, [r7, #76] @ 0x4c
cr_ax_comp_z =
(out_data[2] +
80020be: ed97 7a10 vldr s14, [r7, #64] @ 0x40
(out_data[0] *
80020c2: edd7 6a0e vldr s13, [r7, #56] @ 0x38
(dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_z_y -
80020c6: 683b ldr r3, [r7, #0]
80020c8: ed93 6a16 vldr s12, [r3, #88] @ 0x58
80020cc: 683b ldr r3, [r7, #0]
80020ce: edd3 7a18 vldr s15, [r3, #96] @ 0x60
80020d2: ee26 6a27 vmul.f32 s12, s12, s15
dev->mag_comp.cross_axis.cross_z_x) - out_data[1] *
80020d6: 683b ldr r3, [r7, #0]
80020d8: edd3 7a17 vldr s15, [r3, #92] @ 0x5c
(dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_z_y -
80020dc: ee76 7a67 vsub.f32 s15, s12, s15
(out_data[0] *
80020e0: ee66 6aa7 vmul.f32 s13, s13, s15
dev->mag_comp.cross_axis.cross_z_x) - out_data[1] *
80020e4: ed97 6a0f vldr s12, [r7, #60] @ 0x3c
(dev->mag_comp.cross_axis.cross_z_y - dev->mag_comp.cross_axis.cross_x_y *
80020e8: 683b ldr r3, [r7, #0]
80020ea: edd3 5a18 vldr s11, [r3, #96] @ 0x60
80020ee: 683b ldr r3, [r7, #0]
80020f0: ed93 5a15 vldr s10, [r3, #84] @ 0x54
dev->mag_comp.cross_axis.cross_z_x)) /
80020f4: 683b ldr r3, [r7, #0]
80020f6: edd3 7a17 vldr s15, [r3, #92] @ 0x5c
(dev->mag_comp.cross_axis.cross_z_y - dev->mag_comp.cross_axis.cross_x_y *
80020fa: ee65 7a27 vmul.f32 s15, s10, s15
80020fe: ee75 7ae7 vsub.f32 s15, s11, s15
dev->mag_comp.cross_axis.cross_z_x) - out_data[1] *
8002102: ee66 7a27 vmul.f32 s15, s12, s15
8002106: ee36 6ae7 vsub.f32 s12, s13, s15
(1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y));
800210a: 683b ldr r3, [r7, #0]
800210c: edd3 6a16 vldr s13, [r3, #88] @ 0x58
8002110: 683b ldr r3, [r7, #0]
8002112: edd3 7a15 vldr s15, [r3, #84] @ 0x54
8002116: ee66 7aa7 vmul.f32 s15, s13, s15
800211a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
800211e: ee76 6ae7 vsub.f32 s13, s13, s15
dev->mag_comp.cross_axis.cross_z_x)) /
8002122: eec6 7a26 vdiv.f32 s15, s12, s13
cr_ax_comp_z =
8002126: ee77 7a27 vadd.f32 s15, s14, s15
800212a: edc7 7a12 vstr s15, [r7, #72] @ 0x48
out_data[0] = cr_ax_comp_x;
800212e: 6d3b ldr r3, [r7, #80] @ 0x50
8002130: 63bb str r3, [r7, #56] @ 0x38
out_data[1] = cr_ax_comp_y;
8002132: 6cfb ldr r3, [r7, #76] @ 0x4c
8002134: 63fb str r3, [r7, #60] @ 0x3c
out_data[2] = cr_ax_comp_z;
8002136: 6cbb ldr r3, [r7, #72] @ 0x48
8002138: 643b str r3, [r7, #64] @ 0x40
}
if (rslt == BMM350_OK)
800213a: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57
800213e: 2b00 cmp r3, #0
8002140: d130 bne.n 80021a4 <bmm350_get_compensated_mag_xyz_temp_data+0x31a>
{
if ((dev->axis_en & BMM350_EN_X_MSK) == BMM350_DISABLE)
8002142: 683b ldr r3, [r7, #0]
8002144: 7d5b ldrb r3, [r3, #21]
8002146: f003 0301 and.w r3, r3, #1
800214a: 2b00 cmp r3, #0
800214c: d104 bne.n 8002158 <bmm350_get_compensated_mag_xyz_temp_data+0x2ce>
{
mag_temp_data->x = BMM350_DISABLE;
800214e: 687b ldr r3, [r7, #4]
8002150: f04f 0200 mov.w r2, #0
8002154: 601a str r2, [r3, #0]
8002156: e002 b.n 800215e <bmm350_get_compensated_mag_xyz_temp_data+0x2d4>
}
else
{
mag_temp_data->x = out_data[0];
8002158: 6bba ldr r2, [r7, #56] @ 0x38
800215a: 687b ldr r3, [r7, #4]
800215c: 601a str r2, [r3, #0]
}
if ((dev->axis_en & BMM350_EN_Y_MSK) == BMM350_DISABLE)
800215e: 683b ldr r3, [r7, #0]
8002160: 7d5b ldrb r3, [r3, #21]
8002162: f003 0302 and.w r3, r3, #2
8002166: 2b00 cmp r3, #0
8002168: d104 bne.n 8002174 <bmm350_get_compensated_mag_xyz_temp_data+0x2ea>
{
mag_temp_data->y = BMM350_DISABLE;
800216a: 687b ldr r3, [r7, #4]
800216c: f04f 0200 mov.w r2, #0
8002170: 605a str r2, [r3, #4]
8002172: e002 b.n 800217a <bmm350_get_compensated_mag_xyz_temp_data+0x2f0>
}
else
{
mag_temp_data->y = out_data[1];
8002174: 6bfa ldr r2, [r7, #60] @ 0x3c
8002176: 687b ldr r3, [r7, #4]
8002178: 605a str r2, [r3, #4]
}
if ((dev->axis_en & BMM350_EN_Z_MSK) == BMM350_DISABLE)
800217a: 683b ldr r3, [r7, #0]
800217c: 7d5b ldrb r3, [r3, #21]
800217e: f003 0304 and.w r3, r3, #4
8002182: 2b00 cmp r3, #0
8002184: d104 bne.n 8002190 <bmm350_get_compensated_mag_xyz_temp_data+0x306>
{
mag_temp_data->z = BMM350_DISABLE;
8002186: 687b ldr r3, [r7, #4]
8002188: f04f 0200 mov.w r2, #0
800218c: 609a str r2, [r3, #8]
800218e: e002 b.n 8002196 <bmm350_get_compensated_mag_xyz_temp_data+0x30c>
}
else
{
mag_temp_data->z = out_data[2];
8002190: 6c3a ldr r2, [r7, #64] @ 0x40
8002192: 687b ldr r3, [r7, #4]
8002194: 609a str r2, [r3, #8]
}
mag_temp_data->temperature = out_data[3];
8002196: 6c7a ldr r2, [r7, #68] @ 0x44
8002198: 687b ldr r3, [r7, #4]
800219a: 60da str r2, [r3, #12]
800219c: e002 b.n 80021a4 <bmm350_get_compensated_mag_xyz_temp_data+0x31a>
}
}
else
{
rslt = BMM350_E_NULL_PTR;
800219e: 23ff movs r3, #255 @ 0xff
80021a0: f887 3057 strb.w r3, [r7, #87] @ 0x57
}
return rslt;
80021a4: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57
}
80021a8: 4618 mov r0, r3
80021aa: 3758 adds r7, #88 @ 0x58
80021ac: 46bd mov sp, r7
80021ae: bd80 pop {r7, pc}
080021b0 <bmm350_get_pmu_cmd_status_0>:
/*!
* @brief This API gets the PMU command status 0 value
*/
int8_t bmm350_get_pmu_cmd_status_0(struct bmm350_pmu_cmd_status_0 *pmu_cmd_stat_0, struct bmm350_dev *dev)
{
80021b0: b580 push {r7, lr}
80021b2: b084 sub sp, #16
80021b4: af00 add r7, sp, #0
80021b6: 6078 str r0, [r7, #4]
80021b8: 6039 str r1, [r7, #0]
/* Variable to store the function result */
int8_t rslt;
uint8_t reg_data;
if (pmu_cmd_stat_0 != NULL)
80021ba: 687b ldr r3, [r7, #4]
80021bc: 2b00 cmp r3, #0
80021be: d038 beq.n 8002232 <bmm350_get_pmu_cmd_status_0+0x82>
{
/* Get PMU command status 0 data */
rslt = bmm350_get_regs(BMM350_REG_PMU_CMD_STATUS_0, &reg_data, 1, dev);
80021c0: f107 010e add.w r1, r7, #14
80021c4: 683b ldr r3, [r7, #0]
80021c6: 2201 movs r2, #1
80021c8: 2007 movs r0, #7
80021ca: f7ff fc00 bl 80019ce <bmm350_get_regs>
80021ce: 4603 mov r3, r0
80021d0: 73fb strb r3, [r7, #15]
if (rslt == BMM350_OK)
80021d2: f997 300f ldrsb.w r3, [r7, #15]
80021d6: 2b00 cmp r3, #0
80021d8: d12d bne.n 8002236 <bmm350_get_pmu_cmd_status_0+0x86>
{
pmu_cmd_stat_0->pmu_cmd_busy = BMM350_GET_BITS_POS_0(reg_data, BMM350_PMU_CMD_BUSY);
80021da: 7bbb ldrb r3, [r7, #14]
80021dc: f003 0301 and.w r3, r3, #1
80021e0: b2da uxtb r2, r3
80021e2: 687b ldr r3, [r7, #4]
80021e4: 701a strb r2, [r3, #0]
pmu_cmd_stat_0->odr_ovwr = BMM350_GET_BITS(reg_data, BMM350_ODR_OVWR);
80021e6: 7bbb ldrb r3, [r7, #14]
80021e8: 105b asrs r3, r3, #1
80021ea: b2db uxtb r3, r3
80021ec: f003 0301 and.w r3, r3, #1
80021f0: b2da uxtb r2, r3
80021f2: 687b ldr r3, [r7, #4]
80021f4: 705a strb r2, [r3, #1]
pmu_cmd_stat_0->avr_ovwr = BMM350_GET_BITS(reg_data, BMM350_AVG_OVWR);
80021f6: 7bbb ldrb r3, [r7, #14]
80021f8: 109b asrs r3, r3, #2
80021fa: b2db uxtb r3, r3
80021fc: f003 0301 and.w r3, r3, #1
8002200: b2da uxtb r2, r3
8002202: 687b ldr r3, [r7, #4]
8002204: 709a strb r2, [r3, #2]
pmu_cmd_stat_0->pwr_mode_is_normal = BMM350_GET_BITS(reg_data, BMM350_PWR_MODE_IS_NORMAL);
8002206: 7bbb ldrb r3, [r7, #14]
8002208: 10db asrs r3, r3, #3
800220a: b2db uxtb r3, r3
800220c: f003 0301 and.w r3, r3, #1
8002210: b2da uxtb r2, r3
8002212: 687b ldr r3, [r7, #4]
8002214: 70da strb r2, [r3, #3]
pmu_cmd_stat_0->cmd_is_illegal = BMM350_GET_BITS(reg_data, BMM350_CMD_IS_ILLEGAL);
8002216: 7bbb ldrb r3, [r7, #14]
8002218: 111b asrs r3, r3, #4
800221a: b2db uxtb r3, r3
800221c: f003 0301 and.w r3, r3, #1
8002220: b2da uxtb r2, r3
8002222: 687b ldr r3, [r7, #4]
8002224: 711a strb r2, [r3, #4]
pmu_cmd_stat_0->pmu_cmd_value = BMM350_GET_BITS(reg_data, BMM350_PMU_CMD_VALUE);
8002226: 7bbb ldrb r3, [r7, #14]
8002228: 095b lsrs r3, r3, #5
800222a: b2da uxtb r2, r3
800222c: 687b ldr r3, [r7, #4]
800222e: 715a strb r2, [r3, #5]
8002230: e001 b.n 8002236 <bmm350_get_pmu_cmd_status_0+0x86>
}
}
else
{
rslt = BMM350_E_NULL_PTR;
8002232: 23ff movs r3, #255 @ 0xff
8002234: 73fb strb r3, [r7, #15]
}
return rslt;
8002236: f997 300f ldrsb.w r3, [r7, #15]
}
800223a: 4618 mov r0, r3
800223c: 3710 adds r7, #16
800223e: 46bd mov sp, r7
8002240: bd80 pop {r7, pc}
08002242 <null_ptr_check>:
/*!
* @brief This internal API is used to validate the device structure pointer for
* null conditions.
*/
static int8_t null_ptr_check(const struct bmm350_dev *dev)
{
8002242: b480 push {r7}
8002244: b085 sub sp, #20
8002246: af00 add r7, sp, #0
8002248: 6078 str r0, [r7, #4]
/* Variable to store the function result */
int8_t rslt;
if ((dev == NULL) || (dev->read == NULL) || (dev->write == NULL) || (dev->delay_us == NULL))
800224a: 687b ldr r3, [r7, #4]
800224c: 2b00 cmp r3, #0
800224e: d00b beq.n 8002268 <null_ptr_check+0x26>
8002250: 687b ldr r3, [r7, #4]
8002252: 689b ldr r3, [r3, #8]
8002254: 2b00 cmp r3, #0
8002256: d007 beq.n 8002268 <null_ptr_check+0x26>
8002258: 687b ldr r3, [r7, #4]
800225a: 68db ldr r3, [r3, #12]
800225c: 2b00 cmp r3, #0
800225e: d003 beq.n 8002268 <null_ptr_check+0x26>
8002260: 687b ldr r3, [r7, #4]
8002262: 691b ldr r3, [r3, #16]
8002264: 2b00 cmp r3, #0
8002266: d102 bne.n 800226e <null_ptr_check+0x2c>
{
/* Device structure pointer is not valid */
rslt = BMM350_E_NULL_PTR;
8002268: 23ff movs r3, #255 @ 0xff
800226a: 73fb strb r3, [r7, #15]
800226c: e001 b.n 8002272 <null_ptr_check+0x30>
}
else
{
/* Device structure is fine */
rslt = BMM350_OK;
800226e: 2300 movs r3, #0
8002270: 73fb strb r3, [r7, #15]
}
return rslt;
8002272: f997 300f ldrsb.w r3, [r7, #15]
}
8002276: 4618 mov r0, r3
8002278: 3714 adds r7, #20
800227a: 46bd mov sp, r7
800227c: f85d 7b04 ldr.w r7, [sp], #4
8002280: 4770 bx lr
...
08002284 <fix_sign>:
/*!
* @brief This internal API converts the raw data from the IC data registers to signed integer
*/
static int32_t fix_sign(uint32_t inval, int8_t number_of_bits)
{
8002284: b480 push {r7}
8002286: b085 sub sp, #20
8002288: af00 add r7, sp, #0
800228a: 6078 str r0, [r7, #4]
800228c: 460b mov r3, r1
800228e: 70fb strb r3, [r7, #3]
int32_t power = 0;
8002290: 2300 movs r3, #0
8002292: 60fb str r3, [r7, #12]
int32_t retval;
switch (number_of_bits)
8002294: f997 3003 ldrsb.w r3, [r7, #3]
8002298: 3b08 subs r3, #8
800229a: 2b10 cmp r3, #16
800229c: d837 bhi.n 800230e <fix_sign+0x8a>
800229e: a201 add r2, pc, #4 @ (adr r2, 80022a4 <fix_sign+0x20>)
80022a0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80022a4: 080022e9 .word 0x080022e9
80022a8: 0800230f .word 0x0800230f
80022ac: 0800230f .word 0x0800230f
80022b0: 0800230f .word 0x0800230f
80022b4: 080022ef .word 0x080022ef
80022b8: 0800230f .word 0x0800230f
80022bc: 0800230f .word 0x0800230f
80022c0: 0800230f .word 0x0800230f
80022c4: 080022f7 .word 0x080022f7
80022c8: 0800230f .word 0x0800230f
80022cc: 0800230f .word 0x0800230f
80022d0: 0800230f .word 0x0800230f
80022d4: 0800230f .word 0x0800230f
80022d8: 080022ff .word 0x080022ff
80022dc: 0800230f .word 0x0800230f
80022e0: 0800230f .word 0x0800230f
80022e4: 08002307 .word 0x08002307
{
case BMM350_SIGNED_8_BIT:
power = 128; /* 2^7 */
80022e8: 2380 movs r3, #128 @ 0x80
80022ea: 60fb str r3, [r7, #12]
break;
80022ec: e012 b.n 8002314 <fix_sign+0x90>
case BMM350_SIGNED_12_BIT:
power = 2048; /* 2^11 */
80022ee: f44f 6300 mov.w r3, #2048 @ 0x800
80022f2: 60fb str r3, [r7, #12]
break;
80022f4: e00e b.n 8002314 <fix_sign+0x90>
case BMM350_SIGNED_16_BIT:
power = 32768; /* 2^15 */
80022f6: f44f 4300 mov.w r3, #32768 @ 0x8000
80022fa: 60fb str r3, [r7, #12]
break;
80022fc: e00a b.n 8002314 <fix_sign+0x90>
case BMM350_SIGNED_21_BIT:
power = 1048576; /* 2^20 */
80022fe: f44f 1380 mov.w r3, #1048576 @ 0x100000
8002302: 60fb str r3, [r7, #12]
break;
8002304: e006 b.n 8002314 <fix_sign+0x90>
case BMM350_SIGNED_24_BIT:
power = 8388608; /* 2^23 */
8002306: f44f 0300 mov.w r3, #8388608 @ 0x800000
800230a: 60fb str r3, [r7, #12]
break;
800230c: e002 b.n 8002314 <fix_sign+0x90>
default:
power = 0;
800230e: 2300 movs r3, #0
8002310: 60fb str r3, [r7, #12]
break;
8002312: bf00 nop
}
retval = (int32_t)inval;
8002314: 687b ldr r3, [r7, #4]
8002316: 60bb str r3, [r7, #8]
if (retval >= power)
8002318: 68ba ldr r2, [r7, #8]
800231a: 68fb ldr r3, [r7, #12]
800231c: 429a cmp r2, r3
800231e: db04 blt.n 800232a <fix_sign+0xa6>
{
retval = retval - (power * 2);
8002320: 68fb ldr r3, [r7, #12]
8002322: 005b lsls r3, r3, #1
8002324: 68ba ldr r2, [r7, #8]
8002326: 1ad3 subs r3, r2, r3
8002328: 60bb str r3, [r7, #8]
}
return retval;
800232a: 68bb ldr r3, [r7, #8]
}
800232c: 4618 mov r0, r3
800232e: 3714 adds r7, #20
8002330: 46bd mov sp, r7
8002332: f85d 7b04 ldr.w r7, [sp], #4
8002336: 4770 bx lr
08002338 <read_otp_word>:
/*!
* @brief This internal API is used to read OTP word
*/
static int8_t read_otp_word(uint8_t addr, uint16_t *lsb_msb, struct bmm350_dev *dev)
{
8002338: b580 push {r7, lr}
800233a: b086 sub sp, #24
800233c: af00 add r7, sp, #0
800233e: 4603 mov r3, r0
8002340: 60b9 str r1, [r7, #8]
8002342: 607a str r2, [r7, #4]
8002344: 73fb strb r3, [r7, #15]
/* Variable to store the function result */
int8_t rslt;
uint8_t otp_cmd, otp_status = 0, otp_err = BMM350_OTP_STATUS_NO_ERROR, lsb = 0, msb = 0;
8002346: 2300 movs r3, #0
8002348: 753b strb r3, [r7, #20]
800234a: 2300 movs r3, #0
800234c: 75bb strb r3, [r7, #22]
800234e: 2300 movs r3, #0
8002350: 74fb strb r3, [r7, #19]
8002352: 2300 movs r3, #0
8002354: 74bb strb r3, [r7, #18]
if (lsb_msb != NULL)
8002356: 68bb ldr r3, [r7, #8]
8002358: 2b00 cmp r3, #0
800235a: f000 8087 beq.w 800246c <read_otp_word+0x134>
{
/* Set OTP command at specified address */
otp_cmd = BMM350_OTP_CMD_DIR_READ | (addr & BMM350_OTP_WORD_ADDR_MSK);
800235e: f997 300f ldrsb.w r3, [r7, #15]
8002362: f003 031f and.w r3, r3, #31
8002366: b25b sxtb r3, r3
8002368: f043 0320 orr.w r3, r3, #32
800236c: b25b sxtb r3, r3
800236e: b2db uxtb r3, r3
8002370: 757b strb r3, [r7, #21]
rslt = bmm350_set_regs(BMM350_REG_OTP_CMD_REG, &otp_cmd, 1, dev);
8002372: f107 0115 add.w r1, r7, #21
8002376: 687b ldr r3, [r7, #4]
8002378: 2201 movs r2, #1
800237a: 2050 movs r0, #80 @ 0x50
800237c: f7ff faf3 bl 8001966 <bmm350_set_regs>
8002380: 4603 mov r3, r0
8002382: 75fb strb r3, [r7, #23]
if (rslt == BMM350_OK)
8002384: f997 3017 ldrsb.w r3, [r7, #23]
8002388: 2b00 cmp r3, #0
800238a: d14c bne.n 8002426 <read_otp_word+0xee>
{
do
{
rslt = bmm350_delay_us(300, dev);
800238c: 6879 ldr r1, [r7, #4]
800238e: f44f 7096 mov.w r0, #300 @ 0x12c
8002392: f7ff fb71 bl 8001a78 <bmm350_delay_us>
8002396: 4603 mov r3, r0
8002398: 75fb strb r3, [r7, #23]
if (rslt == BMM350_OK)
800239a: f997 3017 ldrsb.w r3, [r7, #23]
800239e: 2b00 cmp r3, #0
80023a0: d10f bne.n 80023c2 <read_otp_word+0x8a>
{
/* Get OTP status */
rslt = bmm350_get_regs(BMM350_REG_OTP_STATUS_REG, &otp_status, 1, dev);
80023a2: f107 0114 add.w r1, r7, #20
80023a6: 687b ldr r3, [r7, #4]
80023a8: 2201 movs r2, #1
80023aa: 2055 movs r0, #85 @ 0x55
80023ac: f7ff fb0f bl 80019ce <bmm350_get_regs>
80023b0: 4603 mov r3, r0
80023b2: 75fb strb r3, [r7, #23]
otp_err = BMM350_OTP_STATUS_ERROR(otp_status);
80023b4: 7d3b ldrb r3, [r7, #20]
80023b6: f023 031f bic.w r3, r3, #31
80023ba: 75bb strb r3, [r7, #22]
if (otp_err != BMM350_OTP_STATUS_NO_ERROR)
80023bc: 7dbb ldrb r3, [r7, #22]
80023be: 2b00 cmp r3, #0
80023c0: d109 bne.n 80023d6 <read_otp_word+0x9e>
{
break;
}
}
} while ((!(otp_status & BMM350_OTP_STATUS_CMD_DONE)) && (rslt == BMM350_OK));
80023c2: 7d3b ldrb r3, [r7, #20]
80023c4: f003 0301 and.w r3, r3, #1
80023c8: 2b00 cmp r3, #0
80023ca: d105 bne.n 80023d8 <read_otp_word+0xa0>
80023cc: f997 3017 ldrsb.w r3, [r7, #23]
80023d0: 2b00 cmp r3, #0
80023d2: d0db beq.n 800238c <read_otp_word+0x54>
80023d4: e000 b.n 80023d8 <read_otp_word+0xa0>
break;
80023d6: bf00 nop
if (otp_err != BMM350_OTP_STATUS_NO_ERROR)
80023d8: 7dbb ldrb r3, [r7, #22]
80023da: 2b00 cmp r3, #0
80023dc: d023 beq.n 8002426 <read_otp_word+0xee>
{
switch (otp_err)
80023de: 7dbb ldrb r3, [r7, #22]
80023e0: 2ba0 cmp r3, #160 @ 0xa0
80023e2: d01a beq.n 800241a <read_otp_word+0xe2>
80023e4: 2ba0 cmp r3, #160 @ 0xa0
80023e6: dc1b bgt.n 8002420 <read_otp_word+0xe8>
80023e8: 2b80 cmp r3, #128 @ 0x80
80023ea: d013 beq.n 8002414 <read_otp_word+0xdc>
80023ec: 2b80 cmp r3, #128 @ 0x80
80023ee: dc17 bgt.n 8002420 <read_otp_word+0xe8>
80023f0: 2b60 cmp r3, #96 @ 0x60
80023f2: d00c beq.n 800240e <read_otp_word+0xd6>
80023f4: 2b60 cmp r3, #96 @ 0x60
80023f6: dc13 bgt.n 8002420 <read_otp_word+0xe8>
80023f8: 2b20 cmp r3, #32
80023fa: d002 beq.n 8002402 <read_otp_word+0xca>
80023fc: 2b40 cmp r3, #64 @ 0x40
80023fe: d003 beq.n 8002408 <read_otp_word+0xd0>
8002400: e00e b.n 8002420 <read_otp_word+0xe8>
{
case BMM350_OTP_STATUS_BOOT_ERR:
rslt = BMM350_E_OTP_BOOT;
8002402: 23f7 movs r3, #247 @ 0xf7
8002404: 75fb strb r3, [r7, #23]
break;
8002406: e00e b.n 8002426 <read_otp_word+0xee>
case BMM350_OTP_STATUS_PAGE_RD_ERR:
rslt = BMM350_E_OTP_PAGE_RD;
8002408: 23f6 movs r3, #246 @ 0xf6
800240a: 75fb strb r3, [r7, #23]
break;
800240c: e00b b.n 8002426 <read_otp_word+0xee>
case BMM350_OTP_STATUS_PAGE_PRG_ERR:
rslt = BMM350_E_OTP_PAGE_PRG;
800240e: 23f5 movs r3, #245 @ 0xf5
8002410: 75fb strb r3, [r7, #23]
break;
8002412: e008 b.n 8002426 <read_otp_word+0xee>
case BMM350_OTP_STATUS_SIGN_ERR:
rslt = BMM350_E_OTP_SIGN;
8002414: 23f4 movs r3, #244 @ 0xf4
8002416: 75fb strb r3, [r7, #23]
break;
8002418: e005 b.n 8002426 <read_otp_word+0xee>
case BMM350_OTP_STATUS_INV_CMD_ERR:
rslt = BMM350_E_OTP_INV_CMD;
800241a: 23f3 movs r3, #243 @ 0xf3
800241c: 75fb strb r3, [r7, #23]
break;
800241e: e002 b.n 8002426 <read_otp_word+0xee>
default:
rslt = BMM350_E_OTP_UNDEFINED;
8002420: 23f2 movs r3, #242 @ 0xf2
8002422: 75fb strb r3, [r7, #23]
break;
8002424: bf00 nop
}
}
}
if (rslt == BMM350_OK)
8002426: f997 3017 ldrsb.w r3, [r7, #23]
800242a: 2b00 cmp r3, #0
800242c: d120 bne.n 8002470 <read_otp_word+0x138>
{
/* Get OTP MSB data */
rslt = bmm350_get_regs(BMM350_REG_OTP_DATA_MSB_REG, &msb, 1, dev);
800242e: f107 0112 add.w r1, r7, #18
8002432: 687b ldr r3, [r7, #4]
8002434: 2201 movs r2, #1
8002436: 2052 movs r0, #82 @ 0x52
8002438: f7ff fac9 bl 80019ce <bmm350_get_regs>
800243c: 4603 mov r3, r0
800243e: 75fb strb r3, [r7, #23]
if (rslt == BMM350_OK)
8002440: f997 3017 ldrsb.w r3, [r7, #23]
8002444: 2b00 cmp r3, #0
8002446: d113 bne.n 8002470 <read_otp_word+0x138>
{
/* Get OTP LSB data */
rslt = bmm350_get_regs(BMM350_REG_OTP_DATA_LSB_REG, &lsb, 1, dev);
8002448: f107 0113 add.w r1, r7, #19
800244c: 687b ldr r3, [r7, #4]
800244e: 2201 movs r2, #1
8002450: 2053 movs r0, #83 @ 0x53
8002452: f7ff fabc bl 80019ce <bmm350_get_regs>
8002456: 4603 mov r3, r0
8002458: 75fb strb r3, [r7, #23]
*lsb_msb = ((uint16_t)(msb << 8) | lsb) & 0xFFFF;
800245a: 7cbb ldrb r3, [r7, #18]
800245c: 021b lsls r3, r3, #8
800245e: b29b uxth r3, r3
8002460: 7cfa ldrb r2, [r7, #19]
8002462: 4313 orrs r3, r2
8002464: b29a uxth r2, r3
8002466: 68bb ldr r3, [r7, #8]
8002468: 801a strh r2, [r3, #0]
800246a: e001 b.n 8002470 <read_otp_word+0x138>
}
}
}
else
{
rslt = BMM350_E_NULL_PTR;
800246c: 23ff movs r3, #255 @ 0xff
800246e: 75fb strb r3, [r7, #23]
}
return rslt;
8002470: f997 3017 ldrsb.w r3, [r7, #23]
}
8002474: 4618 mov r0, r3
8002476: 3718 adds r7, #24
8002478: 46bd mov sp, r7
800247a: bd80 pop {r7, pc}
0800247c <update_mag_off_sens>:
/*!
* @brief This internal API is used to update magnetometer offset and sensitivity data.
*/
static void update_mag_off_sens(struct bmm350_dev *dev)
{
800247c: b580 push {r7, lr}
800247e: b088 sub sp, #32
8002480: af00 add r7, sp, #0
8002482: 6078 str r0, [r7, #4]
uint16_t off_x_lsb_msb, off_y_lsb_msb, off_z_lsb_msb, t_off = 0;
8002484: 2300 movs r3, #0
8002486: 83fb strh r3, [r7, #30]
uint8_t sens_x, sens_y, sens_z, t_sens = 0;
8002488: 2300 movs r3, #0
800248a: 777b strb r3, [r7, #29]
uint8_t tco_x, tco_y, tco_z = 0;
800248c: 2300 movs r3, #0
800248e: 773b strb r3, [r7, #28]
uint8_t tcs_x, tcs_y, tcs_z = 0;
8002490: 2300 movs r3, #0
8002492: 76fb strb r3, [r7, #27]
uint8_t cross_x_y, cross_y_x, cross_z_x, cross_z_y = 0;
8002494: 2300 movs r3, #0
8002496: 76bb strb r3, [r7, #26]
off_x_lsb_msb = dev->otp_data[BMM350_MAG_OFFSET_X] & 0x0FFF;
8002498: 687b ldr r3, [r7, #4]
800249a: f8b3 3080 ldrh.w r3, [r3, #128] @ 0x80
800249e: f3c3 030b ubfx r3, r3, #0, #12
80024a2: 833b strh r3, [r7, #24]
off_y_lsb_msb = ((dev->otp_data[BMM350_MAG_OFFSET_X] & 0xF000) >> 4) +
80024a4: 687b ldr r3, [r7, #4]
80024a6: f8b3 3080 ldrh.w r3, [r3, #128] @ 0x80
80024aa: 111b asrs r3, r3, #4
80024ac: b21b sxth r3, r3
80024ae: f403 6370 and.w r3, r3, #3840 @ 0xf00
80024b2: b21a sxth r2, r3
(dev->otp_data[BMM350_MAG_OFFSET_Y] & BMM350_LSB_MASK);
80024b4: 687b ldr r3, [r7, #4]
80024b6: f8b3 3082 ldrh.w r3, [r3, #130] @ 0x82
80024ba: b21b sxth r3, r3
80024bc: b2db uxtb r3, r3
80024be: b21b sxth r3, r3
off_y_lsb_msb = ((dev->otp_data[BMM350_MAG_OFFSET_X] & 0xF000) >> 4) +
80024c0: 4313 orrs r3, r2
80024c2: b21b sxth r3, r3
80024c4: 82fb strh r3, [r7, #22]
off_z_lsb_msb = (dev->otp_data[BMM350_MAG_OFFSET_Y] & 0x0F00) +
80024c6: 687b ldr r3, [r7, #4]
80024c8: f8b3 3082 ldrh.w r3, [r3, #130] @ 0x82
80024cc: b21b sxth r3, r3
80024ce: f403 6370 and.w r3, r3, #3840 @ 0xf00
80024d2: b21a sxth r2, r3
(dev->otp_data[BMM350_MAG_OFFSET_Z] & BMM350_LSB_MASK);
80024d4: 687b ldr r3, [r7, #4]
80024d6: f8b3 3084 ldrh.w r3, [r3, #132] @ 0x84
80024da: b21b sxth r3, r3
80024dc: b2db uxtb r3, r3
80024de: b21b sxth r3, r3
off_z_lsb_msb = (dev->otp_data[BMM350_MAG_OFFSET_Y] & 0x0F00) +
80024e0: 4313 orrs r3, r2
80024e2: b21b sxth r3, r3
80024e4: 82bb strh r3, [r7, #20]
t_off = dev->otp_data[BMM350_TEMP_OFF_SENS] & BMM350_LSB_MASK;
80024e6: 687b ldr r3, [r7, #4]
80024e8: f8b3 307e ldrh.w r3, [r3, #126] @ 0x7e
80024ec: b2db uxtb r3, r3
80024ee: 83fb strh r3, [r7, #30]
dev->mag_comp.dut_offset_coef.offset_z = f16_from_int(fix_sign(off_z_lsb_msb, BMM350_SIGNED_12_BIT));
dev->mag_comp.dut_offset_coef.t_offs = fixed_mul_A48_16(f16_from_int(fix_sign(t_off, BMM350_SIGNED_8_BIT)),
A48_16_0_2);
#else
dev->mag_comp.dut_offset_coef.offset_x = fix_sign(off_x_lsb_msb, BMM350_SIGNED_12_BIT);
80024f0: 8b3b ldrh r3, [r7, #24]
80024f2: 210c movs r1, #12
80024f4: 4618 mov r0, r3
80024f6: f7ff fec5 bl 8002284 <fix_sign>
80024fa: ee07 0a90 vmov s15, r0
80024fe: eef8 7ae7 vcvt.f32.s32 s15, s15
8002502: 687b ldr r3, [r7, #4]
8002504: edc3 7a07 vstr s15, [r3, #28]
dev->mag_comp.dut_offset_coef.offset_y = fix_sign(off_y_lsb_msb, BMM350_SIGNED_12_BIT);
8002508: 8afb ldrh r3, [r7, #22]
800250a: 210c movs r1, #12
800250c: 4618 mov r0, r3
800250e: f7ff feb9 bl 8002284 <fix_sign>
8002512: ee07 0a90 vmov s15, r0
8002516: eef8 7ae7 vcvt.f32.s32 s15, s15
800251a: 687b ldr r3, [r7, #4]
800251c: edc3 7a08 vstr s15, [r3, #32]
dev->mag_comp.dut_offset_coef.offset_z = fix_sign(off_z_lsb_msb, BMM350_SIGNED_12_BIT);
8002520: 8abb ldrh r3, [r7, #20]
8002522: 210c movs r1, #12
8002524: 4618 mov r0, r3
8002526: f7ff fead bl 8002284 <fix_sign>
800252a: ee07 0a90 vmov s15, r0
800252e: eef8 7ae7 vcvt.f32.s32 s15, s15
8002532: 687b ldr r3, [r7, #4]
8002534: edc3 7a09 vstr s15, [r3, #36] @ 0x24
dev->mag_comp.dut_offset_coef.t_offs = fix_sign(t_off, BMM350_SIGNED_8_BIT) / 5.0f;
8002538: 8bfb ldrh r3, [r7, #30]
800253a: 2108 movs r1, #8
800253c: 4618 mov r0, r3
800253e: f7ff fea1 bl 8002284 <fix_sign>
8002542: ee07 0a90 vmov s15, r0
8002546: eeb8 7ae7 vcvt.f32.s32 s14, s15
800254a: eef1 6a04 vmov.f32 s13, #20 @ 0x40a00000 5.0
800254e: eec7 7a26 vdiv.f32 s15, s14, s13
8002552: 687b ldr r3, [r7, #4]
8002554: edc3 7a06 vstr s15, [r3, #24]
#endif
sens_x = (dev->otp_data[BMM350_MAG_SENS_X] & BMM350_MSB_MASK) >> 8;
8002558: 687b ldr r3, [r7, #4]
800255a: f8b3 3084 ldrh.w r3, [r3, #132] @ 0x84
800255e: 0a1b lsrs r3, r3, #8
8002560: b29b uxth r3, r3
8002562: 74fb strb r3, [r7, #19]
sens_y = (dev->otp_data[BMM350_MAG_SENS_Y] & BMM350_LSB_MASK);
8002564: 687b ldr r3, [r7, #4]
8002566: f8b3 3086 ldrh.w r3, [r3, #134] @ 0x86
800256a: 74bb strb r3, [r7, #18]
sens_z = (dev->otp_data[BMM350_MAG_SENS_Z] & BMM350_MSB_MASK) >> 8;
800256c: 687b ldr r3, [r7, #4]
800256e: f8b3 3086 ldrh.w r3, [r3, #134] @ 0x86
8002572: 0a1b lsrs r3, r3, #8
8002574: b29b uxth r3, r3
8002576: 747b strb r3, [r7, #17]
t_sens = (dev->otp_data[BMM350_TEMP_OFF_SENS] & BMM350_MSB_MASK) >> 8;
8002578: 687b ldr r3, [r7, #4]
800257a: f8b3 307e ldrh.w r3, [r3, #126] @ 0x7e
800257e: 0a1b lsrs r3, r3, #8
8002580: b29b uxth r3, r3
8002582: 777b strb r3, [r7, #29]
A48_16_0_00390625);
dev->mag_comp.dut_sensit_coef.t_sens = fixed_mul_A48_16(f16_from_int(fix_sign(t_sens, BMM350_SIGNED_8_BIT)),
A48_16_0_001953125);
#else
dev->mag_comp.dut_sensit_coef.sens_x = fix_sign(sens_x, BMM350_SIGNED_8_BIT) / 256.0f;
8002584: 7cfb ldrb r3, [r7, #19]
8002586: 2108 movs r1, #8
8002588: 4618 mov r0, r3
800258a: f7ff fe7b bl 8002284 <fix_sign>
800258e: ee07 0a90 vmov s15, r0
8002592: eeb8 7ae7 vcvt.f32.s32 s14, s15
8002596: eddf 6a91 vldr s13, [pc, #580] @ 80027dc <update_mag_off_sens+0x360>
800259a: eec7 7a26 vdiv.f32 s15, s14, s13
800259e: 687b ldr r3, [r7, #4]
80025a0: edc3 7a0b vstr s15, [r3, #44] @ 0x2c
dev->mag_comp.dut_sensit_coef.sens_y = fix_sign(sens_y, BMM350_SIGNED_8_BIT) / 256.0f;
80025a4: 7cbb ldrb r3, [r7, #18]
80025a6: 2108 movs r1, #8
80025a8: 4618 mov r0, r3
80025aa: f7ff fe6b bl 8002284 <fix_sign>
80025ae: ee07 0a90 vmov s15, r0
80025b2: eeb8 7ae7 vcvt.f32.s32 s14, s15
80025b6: eddf 6a89 vldr s13, [pc, #548] @ 80027dc <update_mag_off_sens+0x360>
80025ba: eec7 7a26 vdiv.f32 s15, s14, s13
80025be: 687b ldr r3, [r7, #4]
80025c0: edc3 7a0c vstr s15, [r3, #48] @ 0x30
dev->mag_comp.dut_sensit_coef.sens_z = fix_sign(sens_z, BMM350_SIGNED_8_BIT) / 256.0f;
80025c4: 7c7b ldrb r3, [r7, #17]
80025c6: 2108 movs r1, #8
80025c8: 4618 mov r0, r3
80025ca: f7ff fe5b bl 8002284 <fix_sign>
80025ce: ee07 0a90 vmov s15, r0
80025d2: eeb8 7ae7 vcvt.f32.s32 s14, s15
80025d6: eddf 6a81 vldr s13, [pc, #516] @ 80027dc <update_mag_off_sens+0x360>
80025da: eec7 7a26 vdiv.f32 s15, s14, s13
80025de: 687b ldr r3, [r7, #4]
80025e0: edc3 7a0d vstr s15, [r3, #52] @ 0x34
dev->mag_comp.dut_sensit_coef.t_sens = fix_sign(t_sens, BMM350_SIGNED_8_BIT) / 512.0f;
80025e4: 7f7b ldrb r3, [r7, #29]
80025e6: 2108 movs r1, #8
80025e8: 4618 mov r0, r3
80025ea: f7ff fe4b bl 8002284 <fix_sign>
80025ee: ee07 0a90 vmov s15, r0
80025f2: eeb8 7ae7 vcvt.f32.s32 s14, s15
80025f6: eddf 6a7a vldr s13, [pc, #488] @ 80027e0 <update_mag_off_sens+0x364>
80025fa: eec7 7a26 vdiv.f32 s15, s14, s13
80025fe: 687b ldr r3, [r7, #4]
8002600: edc3 7a0a vstr s15, [r3, #40] @ 0x28
#endif
tco_x = (dev->otp_data[BMM350_MAG_TCO_X] & BMM350_LSB_MASK);
8002604: 687b ldr r3, [r7, #4]
8002606: f8b3 3088 ldrh.w r3, [r3, #136] @ 0x88
800260a: 743b strb r3, [r7, #16]
tco_y = (dev->otp_data[BMM350_MAG_TCO_Y] & BMM350_LSB_MASK);
800260c: 687b ldr r3, [r7, #4]
800260e: f8b3 308a ldrh.w r3, [r3, #138] @ 0x8a
8002612: 73fb strb r3, [r7, #15]
tco_z = (dev->otp_data[BMM350_MAG_TCO_Z] & BMM350_LSB_MASK);
8002614: 687b ldr r3, [r7, #4]
8002616: f8b3 308c ldrh.w r3, [r3, #140] @ 0x8c
800261a: 773b strb r3, [r7, #28]
dev->mag_comp.dut_tco.tco_x = fixed_mul_A48_16(f16_from_int(fix_sign(tco_x, BMM350_SIGNED_8_BIT)), A48_16_0_03125);
dev->mag_comp.dut_tco.tco_y = fixed_mul_A48_16(f16_from_int(fix_sign(tco_y, BMM350_SIGNED_8_BIT)), A48_16_0_03125);
dev->mag_comp.dut_tco.tco_z = fixed_mul_A48_16(f16_from_int(fix_sign(tco_z, BMM350_SIGNED_8_BIT)), A48_16_0_03125);
#else
dev->mag_comp.dut_tco.tco_x = fix_sign(tco_x, BMM350_SIGNED_8_BIT) / 32.0f;
800261c: 7c3b ldrb r3, [r7, #16]
800261e: 2108 movs r1, #8
8002620: 4618 mov r0, r3
8002622: f7ff fe2f bl 8002284 <fix_sign>
8002626: ee07 0a90 vmov s15, r0
800262a: eeb8 7ae7 vcvt.f32.s32 s14, s15
800262e: eddf 6a6d vldr s13, [pc, #436] @ 80027e4 <update_mag_off_sens+0x368>
8002632: eec7 7a26 vdiv.f32 s15, s14, s13
8002636: 687b ldr r3, [r7, #4]
8002638: edc3 7a0e vstr s15, [r3, #56] @ 0x38
dev->mag_comp.dut_tco.tco_y = fix_sign(tco_y, BMM350_SIGNED_8_BIT) / 32.0f;
800263c: 7bfb ldrb r3, [r7, #15]
800263e: 2108 movs r1, #8
8002640: 4618 mov r0, r3
8002642: f7ff fe1f bl 8002284 <fix_sign>
8002646: ee07 0a90 vmov s15, r0
800264a: eeb8 7ae7 vcvt.f32.s32 s14, s15
800264e: eddf 6a65 vldr s13, [pc, #404] @ 80027e4 <update_mag_off_sens+0x368>
8002652: eec7 7a26 vdiv.f32 s15, s14, s13
8002656: 687b ldr r3, [r7, #4]
8002658: edc3 7a0f vstr s15, [r3, #60] @ 0x3c
dev->mag_comp.dut_tco.tco_z = fix_sign(tco_z, BMM350_SIGNED_8_BIT) / 32.0f;
800265c: 7f3b ldrb r3, [r7, #28]
800265e: 2108 movs r1, #8
8002660: 4618 mov r0, r3
8002662: f7ff fe0f bl 8002284 <fix_sign>
8002666: ee07 0a90 vmov s15, r0
800266a: eeb8 7ae7 vcvt.f32.s32 s14, s15
800266e: eddf 6a5d vldr s13, [pc, #372] @ 80027e4 <update_mag_off_sens+0x368>
8002672: eec7 7a26 vdiv.f32 s15, s14, s13
8002676: 687b ldr r3, [r7, #4]
8002678: edc3 7a10 vstr s15, [r3, #64] @ 0x40
#endif
tcs_x = (dev->otp_data[BMM350_MAG_TCS_X] & BMM350_MSB_MASK) >> 8;
800267c: 687b ldr r3, [r7, #4]
800267e: f8b3 3088 ldrh.w r3, [r3, #136] @ 0x88
8002682: 0a1b lsrs r3, r3, #8
8002684: b29b uxth r3, r3
8002686: 73bb strb r3, [r7, #14]
tcs_y = (dev->otp_data[BMM350_MAG_TCS_Y] & BMM350_MSB_MASK) >> 8;
8002688: 687b ldr r3, [r7, #4]
800268a: f8b3 308a ldrh.w r3, [r3, #138] @ 0x8a
800268e: 0a1b lsrs r3, r3, #8
8002690: b29b uxth r3, r3
8002692: 737b strb r3, [r7, #13]
tcs_z = (dev->otp_data[BMM350_MAG_TCS_Z] & BMM350_MSB_MASK) >> 8;
8002694: 687b ldr r3, [r7, #4]
8002696: f8b3 308c ldrh.w r3, [r3, #140] @ 0x8c
800269a: 0a1b lsrs r3, r3, #8
800269c: b29b uxth r3, r3
800269e: 76fb strb r3, [r7, #27]
A48_16_0_00006103515625);
dev->mag_comp.dut_tcs.tcs_z = fixed_mul_A48_16(f16_from_int(fix_sign(tcs_z, BMM350_SIGNED_8_BIT)),
A48_16_0_00006103515625);
#else
dev->mag_comp.dut_tcs.tcs_x = fix_sign(tcs_x, BMM350_SIGNED_8_BIT) / 16384.0f;
80026a0: 7bbb ldrb r3, [r7, #14]
80026a2: 2108 movs r1, #8
80026a4: 4618 mov r0, r3
80026a6: f7ff fded bl 8002284 <fix_sign>
80026aa: ee07 0a90 vmov s15, r0
80026ae: eeb8 7ae7 vcvt.f32.s32 s14, s15
80026b2: eddf 6a4d vldr s13, [pc, #308] @ 80027e8 <update_mag_off_sens+0x36c>
80026b6: eec7 7a26 vdiv.f32 s15, s14, s13
80026ba: 687b ldr r3, [r7, #4]
80026bc: edc3 7a11 vstr s15, [r3, #68] @ 0x44
dev->mag_comp.dut_tcs.tcs_y = fix_sign(tcs_y, BMM350_SIGNED_8_BIT) / 16384.0f;
80026c0: 7b7b ldrb r3, [r7, #13]
80026c2: 2108 movs r1, #8
80026c4: 4618 mov r0, r3
80026c6: f7ff fddd bl 8002284 <fix_sign>
80026ca: ee07 0a90 vmov s15, r0
80026ce: eeb8 7ae7 vcvt.f32.s32 s14, s15
80026d2: eddf 6a45 vldr s13, [pc, #276] @ 80027e8 <update_mag_off_sens+0x36c>
80026d6: eec7 7a26 vdiv.f32 s15, s14, s13
80026da: 687b ldr r3, [r7, #4]
80026dc: edc3 7a12 vstr s15, [r3, #72] @ 0x48
dev->mag_comp.dut_tcs.tcs_z = fix_sign(tcs_z, BMM350_SIGNED_8_BIT) / 16384.0f;
80026e0: 7efb ldrb r3, [r7, #27]
80026e2: 2108 movs r1, #8
80026e4: 4618 mov r0, r3
80026e6: f7ff fdcd bl 8002284 <fix_sign>
80026ea: ee07 0a90 vmov s15, r0
80026ee: eeb8 7ae7 vcvt.f32.s32 s14, s15
80026f2: eddf 6a3d vldr s13, [pc, #244] @ 80027e8 <update_mag_off_sens+0x36c>
80026f6: eec7 7a26 vdiv.f32 s15, s14, s13
80026fa: 687b ldr r3, [r7, #4]
80026fc: edc3 7a13 vstr s15, [r3, #76] @ 0x4c
dev->mag_comp.dut_t0 =
fixed_add(fixed_mul_A48_16(f16_from_int(fix_sign(dev->otp_data[BMM350_MAG_DUT_T_0], BMM350_SIGNED_16_BIT)),
A48_16_0_001953125), f16_from_int(23));
#else
dev->mag_comp.dut_t0 = (fix_sign(dev->otp_data[BMM350_MAG_DUT_T_0], BMM350_SIGNED_16_BIT) / 512.0f) + 23.0f;
8002700: 687b ldr r3, [r7, #4]
8002702: f8b3 3094 ldrh.w r3, [r3, #148] @ 0x94
8002706: 2110 movs r1, #16
8002708: 4618 mov r0, r3
800270a: f7ff fdbb bl 8002284 <fix_sign>
800270e: ee07 0a90 vmov s15, r0
8002712: eeb8 7ae7 vcvt.f32.s32 s14, s15
8002716: eddf 6a32 vldr s13, [pc, #200] @ 80027e0 <update_mag_off_sens+0x364>
800271a: eec7 7a26 vdiv.f32 s15, s14, s13
800271e: eeb3 7a07 vmov.f32 s14, #55 @ 0x41b80000 23.0
8002722: ee77 7a87 vadd.f32 s15, s15, s14
8002726: 687b ldr r3, [r7, #4]
8002728: edc3 7a14 vstr s15, [r3, #80] @ 0x50
#endif
cross_x_y = (dev->otp_data[BMM350_CROSS_X_Y] & BMM350_LSB_MASK);
800272c: 687b ldr r3, [r7, #4]
800272e: f8b3 308e ldrh.w r3, [r3, #142] @ 0x8e
8002732: 733b strb r3, [r7, #12]
cross_y_x = (dev->otp_data[BMM350_CROSS_Y_X] & BMM350_MSB_MASK) >> 8;
8002734: 687b ldr r3, [r7, #4]
8002736: f8b3 308e ldrh.w r3, [r3, #142] @ 0x8e
800273a: 0a1b lsrs r3, r3, #8
800273c: b29b uxth r3, r3
800273e: 72fb strb r3, [r7, #11]
cross_z_x = (dev->otp_data[BMM350_CROSS_Z_X] & BMM350_LSB_MASK);
8002740: 687b ldr r3, [r7, #4]
8002742: f8b3 3090 ldrh.w r3, [r3, #144] @ 0x90
8002746: 72bb strb r3, [r7, #10]
cross_z_y = (dev->otp_data[BMM350_CROSS_Z_Y] & BMM350_MSB_MASK) >> 8;
8002748: 687b ldr r3, [r7, #4]
800274a: f8b3 3090 ldrh.w r3, [r3, #144] @ 0x90
800274e: 0a1b lsrs r3, r3, #8
8002750: b29b uxth r3, r3
8002752: 76bb strb r3, [r7, #26]
A48_16_0_00125);
dev->mag_comp.cross_axis.cross_z_y = fixed_mul_A48_16(f16_from_int(fix_sign(cross_z_y, BMM350_SIGNED_8_BIT)),
A48_16_0_00125);
#else
dev->mag_comp.cross_axis.cross_x_y = fix_sign(cross_x_y, BMM350_SIGNED_8_BIT) / 800.0f;
8002754: 7b3b ldrb r3, [r7, #12]
8002756: 2108 movs r1, #8
8002758: 4618 mov r0, r3
800275a: f7ff fd93 bl 8002284 <fix_sign>
800275e: ee07 0a90 vmov s15, r0
8002762: eeb8 7ae7 vcvt.f32.s32 s14, s15
8002766: eddf 6a21 vldr s13, [pc, #132] @ 80027ec <update_mag_off_sens+0x370>
800276a: eec7 7a26 vdiv.f32 s15, s14, s13
800276e: 687b ldr r3, [r7, #4]
8002770: edc3 7a15 vstr s15, [r3, #84] @ 0x54
dev->mag_comp.cross_axis.cross_y_x = fix_sign(cross_y_x, BMM350_SIGNED_8_BIT) / 800.0f;
8002774: 7afb ldrb r3, [r7, #11]
8002776: 2108 movs r1, #8
8002778: 4618 mov r0, r3
800277a: f7ff fd83 bl 8002284 <fix_sign>
800277e: ee07 0a90 vmov s15, r0
8002782: eeb8 7ae7 vcvt.f32.s32 s14, s15
8002786: eddf 6a19 vldr s13, [pc, #100] @ 80027ec <update_mag_off_sens+0x370>
800278a: eec7 7a26 vdiv.f32 s15, s14, s13
800278e: 687b ldr r3, [r7, #4]
8002790: edc3 7a16 vstr s15, [r3, #88] @ 0x58
dev->mag_comp.cross_axis.cross_z_x = fix_sign(cross_z_x, BMM350_SIGNED_8_BIT) / 800.0f;
8002794: 7abb ldrb r3, [r7, #10]
8002796: 2108 movs r1, #8
8002798: 4618 mov r0, r3
800279a: f7ff fd73 bl 8002284 <fix_sign>
800279e: ee07 0a90 vmov s15, r0
80027a2: eeb8 7ae7 vcvt.f32.s32 s14, s15
80027a6: eddf 6a11 vldr s13, [pc, #68] @ 80027ec <update_mag_off_sens+0x370>
80027aa: eec7 7a26 vdiv.f32 s15, s14, s13
80027ae: 687b ldr r3, [r7, #4]
80027b0: edc3 7a17 vstr s15, [r3, #92] @ 0x5c
dev->mag_comp.cross_axis.cross_z_y = fix_sign(cross_z_y, BMM350_SIGNED_8_BIT) / 800.0f;
80027b4: 7ebb ldrb r3, [r7, #26]
80027b6: 2108 movs r1, #8
80027b8: 4618 mov r0, r3
80027ba: f7ff fd63 bl 8002284 <fix_sign>
80027be: ee07 0a90 vmov s15, r0
80027c2: eeb8 7ae7 vcvt.f32.s32 s14, s15
80027c6: eddf 6a09 vldr s13, [pc, #36] @ 80027ec <update_mag_off_sens+0x370>
80027ca: eec7 7a26 vdiv.f32 s15, s14, s13
80027ce: 687b ldr r3, [r7, #4]
80027d0: edc3 7a18 vstr s15, [r3, #96] @ 0x60
#endif
}
80027d4: bf00 nop
80027d6: 3720 adds r7, #32
80027d8: 46bd mov sp, r7
80027da: bd80 pop {r7, pc}
80027dc: 43800000 .word 0x43800000
80027e0: 44000000 .word 0x44000000
80027e4: 42000000 .word 0x42000000
80027e8: 46800000 .word 0x46800000
80027ec: 44480000 .word 0x44480000
080027f0 <read_out_raw_data>:
return rslt;
}
#else
static int8_t read_out_raw_data(float *out_data, struct bmm350_dev *dev)
{
80027f0: b590 push {r4, r7, lr}
80027f2: b08d sub sp, #52 @ 0x34
80027f4: af00 add r7, sp, #0
80027f6: 6078 str r0, [r7, #4]
80027f8: 6039 str r1, [r7, #0]
int8_t rslt;
/* Float variable to convert mag lsb to uT and temp lsb to degC */
float lsb_to_ut_degc[4];
struct bmm350_raw_mag_data raw_data = { 0 };
80027fa: f107 030c add.w r3, r7, #12
80027fe: 2200 movs r2, #0
8002800: 601a str r2, [r3, #0]
8002802: 605a str r2, [r3, #4]
8002804: 609a str r2, [r3, #8]
8002806: 60da str r2, [r3, #12]
if (out_data != NULL)
8002808: 687b ldr r3, [r7, #4]
800280a: 2b00 cmp r3, #0
800280c: d05b beq.n 80028c6 <read_out_raw_data+0xd6>
{
rslt = bmm350_read_uncomp_mag_temp_data(&raw_data, dev);
800280e: f107 030c add.w r3, r7, #12
8002812: 6839 ldr r1, [r7, #0]
8002814: 4618 mov r0, r3
8002816: f7ff fa09 bl 8001c2c <bmm350_read_uncomp_mag_temp_data>
800281a: 4603 mov r3, r0
800281c: f887 302f strb.w r3, [r7, #47] @ 0x2f
if (rslt == BMM350_OK)
8002820: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
8002824: 2b00 cmp r3, #0
8002826: d151 bne.n 80028cc <read_out_raw_data+0xdc>
{
/* Convert mag lsb to uT and temp lsb to degC */
update_default_coefiecents(lsb_to_ut_degc);
8002828: f107 031c add.w r3, r7, #28
800282c: 4618 mov r0, r3
800282e: f000 f857 bl 80028e0 <update_default_coefiecents>
out_data[0] = (float)raw_data.raw_xdata * lsb_to_ut_degc[0];
8002832: 68fb ldr r3, [r7, #12]
8002834: ee07 3a90 vmov s15, r3
8002838: eeb8 7ae7 vcvt.f32.s32 s14, s15
800283c: edd7 7a07 vldr s15, [r7, #28]
8002840: ee67 7a27 vmul.f32 s15, s14, s15
8002844: 687b ldr r3, [r7, #4]
8002846: edc3 7a00 vstr s15, [r3]
out_data[1] = (float)raw_data.raw_ydata * lsb_to_ut_degc[1];
800284a: 693b ldr r3, [r7, #16]
800284c: ee07 3a90 vmov s15, r3
8002850: eeb8 7ae7 vcvt.f32.s32 s14, s15
8002854: edd7 7a08 vldr s15, [r7, #32]
8002858: 687b ldr r3, [r7, #4]
800285a: 3304 adds r3, #4
800285c: ee67 7a27 vmul.f32 s15, s14, s15
8002860: edc3 7a00 vstr s15, [r3]
out_data[2] = (float)raw_data.raw_zdata * lsb_to_ut_degc[2];
8002864: 697b ldr r3, [r7, #20]
8002866: ee07 3a90 vmov s15, r3
800286a: eeb8 7ae7 vcvt.f32.s32 s14, s15
800286e: edd7 7a09 vldr s15, [r7, #36] @ 0x24
8002872: 687b ldr r3, [r7, #4]
8002874: 3308 adds r3, #8
8002876: ee67 7a27 vmul.f32 s15, s14, s15
800287a: edc3 7a00 vstr s15, [r3]
out_data[3] = (float)raw_data.raw_data_t * lsb_to_ut_degc[3];
800287e: 69bb ldr r3, [r7, #24]
8002880: ee07 3a90 vmov s15, r3
8002884: eeb8 7ae7 vcvt.f32.s32 s14, s15
8002888: edd7 7a0a vldr s15, [r7, #40] @ 0x28
800288c: 687b ldr r3, [r7, #4]
800288e: 330c adds r3, #12
8002890: ee67 7a27 vmul.f32 s15, s14, s15
8002894: edc3 7a00 vstr s15, [r3]
out_data[3] = (float)(out_data[3] - (1 * 25.49));
8002898: 687b ldr r3, [r7, #4]
800289a: 330c adds r3, #12
800289c: 681b ldr r3, [r3, #0]
800289e: 4618 mov r0, r3
80028a0: f7fd fe2a bl 80004f8 <__aeabi_f2d>
80028a4: a30c add r3, pc, #48 @ (adr r3, 80028d8 <read_out_raw_data+0xe8>)
80028a6: e9d3 2300 ldrd r2, r3, [r3]
80028aa: f7fd fcc5 bl 8000238 <__aeabi_dsub>
80028ae: 4602 mov r2, r0
80028b0: 460b mov r3, r1
80028b2: 4610 mov r0, r2
80028b4: 4619 mov r1, r3
80028b6: 687b ldr r3, [r7, #4]
80028b8: f103 040c add.w r4, r3, #12
80028bc: f7fe f96c bl 8000b98 <__aeabi_d2f>
80028c0: 4603 mov r3, r0
80028c2: 6023 str r3, [r4, #0]
80028c4: e002 b.n 80028cc <read_out_raw_data+0xdc>
}
}
else
{
rslt = BMM350_E_NULL_PTR;
80028c6: 23ff movs r3, #255 @ 0xff
80028c8: f887 302f strb.w r3, [r7, #47] @ 0x2f
}
return rslt;
80028cc: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
}
80028d0: 4618 mov r0, r3
80028d2: 3734 adds r7, #52 @ 0x34
80028d4: 46bd mov sp, r7
80028d6: bd90 pop {r4, r7, pc}
80028d8: a3d70a3d .word 0xa3d70a3d
80028dc: 40397d70 .word 0x40397d70
080028e0 <update_default_coefiecents>:
/*!
* @brief This internal API is used to convert lsb to uT and degC.
*/
static void update_default_coefiecents(float *lsb_to_ut_degc)
{
80028e0: b480 push {r7}
80028e2: b08b sub sp, #44 @ 0x2c
80028e4: af00 add r7, sp, #0
80028e6: 6078 str r0, [r7, #4]
float bxy_sens, bz_sens, temp_sens, ina_xy_gain_trgt, ina_z_gain_trgt, adc_gain, lut_gain;
float power;
bxy_sens = 14.55f;
80028e8: 4b36 ldr r3, [pc, #216] @ (80029c4 <update_default_coefiecents+0xe4>)
80028ea: 627b str r3, [r7, #36] @ 0x24
bz_sens = 9.0f;
80028ec: 4b36 ldr r3, [pc, #216] @ (80029c8 <update_default_coefiecents+0xe8>)
80028ee: 623b str r3, [r7, #32]
temp_sens = 0.00204f;
80028f0: 4b36 ldr r3, [pc, #216] @ (80029cc <update_default_coefiecents+0xec>)
80028f2: 61fb str r3, [r7, #28]
ina_xy_gain_trgt = 19.46f;
80028f4: 4b36 ldr r3, [pc, #216] @ (80029d0 <update_default_coefiecents+0xf0>)
80028f6: 61bb str r3, [r7, #24]
ina_z_gain_trgt = 31.0;
80028f8: 4b36 ldr r3, [pc, #216] @ (80029d4 <update_default_coefiecents+0xf4>)
80028fa: 617b str r3, [r7, #20]
adc_gain = 1 / 1.5f;
80028fc: 4b36 ldr r3, [pc, #216] @ (80029d8 <update_default_coefiecents+0xf8>)
80028fe: 613b str r3, [r7, #16]
lut_gain = 0.714607238769531f;
8002900: 4b36 ldr r3, [pc, #216] @ (80029dc <update_default_coefiecents+0xfc>)
8002902: 60fb str r3, [r7, #12]
power = (float)(1000000.0 / 1048576.0);
8002904: 4b36 ldr r3, [pc, #216] @ (80029e0 <update_default_coefiecents+0x100>)
8002906: 60bb str r3, [r7, #8]
lsb_to_ut_degc[0] = (power / (bxy_sens * ina_xy_gain_trgt * adc_gain * lut_gain));
8002908: ed97 7a09 vldr s14, [r7, #36] @ 0x24
800290c: edd7 7a06 vldr s15, [r7, #24]
8002910: ee27 7a27 vmul.f32 s14, s14, s15
8002914: edd7 7a04 vldr s15, [r7, #16]
8002918: ee27 7a27 vmul.f32 s14, s14, s15
800291c: edd7 7a03 vldr s15, [r7, #12]
8002920: ee27 7a27 vmul.f32 s14, s14, s15
8002924: edd7 6a02 vldr s13, [r7, #8]
8002928: eec6 7a87 vdiv.f32 s15, s13, s14
800292c: 687b ldr r3, [r7, #4]
800292e: edc3 7a00 vstr s15, [r3]
lsb_to_ut_degc[1] = (power / (bxy_sens * ina_xy_gain_trgt * adc_gain * lut_gain));
8002932: ed97 7a09 vldr s14, [r7, #36] @ 0x24
8002936: edd7 7a06 vldr s15, [r7, #24]
800293a: ee27 7a27 vmul.f32 s14, s14, s15
800293e: edd7 7a04 vldr s15, [r7, #16]
8002942: ee27 7a27 vmul.f32 s14, s14, s15
8002946: edd7 7a03 vldr s15, [r7, #12]
800294a: ee27 7a27 vmul.f32 s14, s14, s15
800294e: 687b ldr r3, [r7, #4]
8002950: 3304 adds r3, #4
8002952: edd7 6a02 vldr s13, [r7, #8]
8002956: eec6 7a87 vdiv.f32 s15, s13, s14
800295a: edc3 7a00 vstr s15, [r3]
lsb_to_ut_degc[2] = (power / (bz_sens * ina_z_gain_trgt * adc_gain * lut_gain));
800295e: ed97 7a08 vldr s14, [r7, #32]
8002962: edd7 7a05 vldr s15, [r7, #20]
8002966: ee27 7a27 vmul.f32 s14, s14, s15
800296a: edd7 7a04 vldr s15, [r7, #16]
800296e: ee27 7a27 vmul.f32 s14, s14, s15
8002972: edd7 7a03 vldr s15, [r7, #12]
8002976: ee27 7a27 vmul.f32 s14, s14, s15
800297a: 687b ldr r3, [r7, #4]
800297c: 3308 adds r3, #8
800297e: edd7 6a02 vldr s13, [r7, #8]
8002982: eec6 7a87 vdiv.f32 s15, s13, s14
8002986: edc3 7a00 vstr s15, [r3]
lsb_to_ut_degc[3] = 1 / (temp_sens * adc_gain * lut_gain * 1048576);
800298a: ed97 7a07 vldr s14, [r7, #28]
800298e: edd7 7a04 vldr s15, [r7, #16]
8002992: ee27 7a27 vmul.f32 s14, s14, s15
8002996: edd7 7a03 vldr s15, [r7, #12]
800299a: ee67 7a27 vmul.f32 s15, s14, s15
800299e: ed9f 7a11 vldr s14, [pc, #68] @ 80029e4 <update_default_coefiecents+0x104>
80029a2: ee27 7a87 vmul.f32 s14, s15, s14
80029a6: 687b ldr r3, [r7, #4]
80029a8: 330c adds r3, #12
80029aa: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
80029ae: eec6 7a87 vdiv.f32 s15, s13, s14
80029b2: edc3 7a00 vstr s15, [r3]
}
80029b6: bf00 nop
80029b8: 372c adds r7, #44 @ 0x2c
80029ba: 46bd mov sp, r7
80029bc: f85d 7b04 ldr.w r7, [sp], #4
80029c0: 4770 bx lr
80029c2: bf00 nop
80029c4: 4168cccd .word 0x4168cccd
80029c8: 41100000 .word 0x41100000
80029cc: 3b05b185 .word 0x3b05b185
80029d0: 419bae14 .word 0x419bae14
80029d4: 41f80000 .word 0x41f80000
80029d8: 3f2aaaab .word 0x3f2aaaab
80029dc: 3f36f080 .word 0x3f36f080
80029e0: 3f742400 .word 0x3f742400
80029e4: 49800000 .word 0x49800000
080029e8 <otp_dump_after_boot>:
/*!
* @brief This internal API is used to read OTP data after boot in user mode.
*/
static int8_t otp_dump_after_boot(struct bmm350_dev *dev)
{
80029e8: b580 push {r7, lr}
80029ea: b084 sub sp, #16
80029ec: af00 add r7, sp, #0
80029ee: 6078 str r0, [r7, #4]
/* Variable to store the function result */
int8_t rslt;
uint16_t otp_word = 0;
80029f0: 2300 movs r3, #0
80029f2: 81bb strh r3, [r7, #12]
uint8_t indx;
for (indx = 0; indx < BMM350_OTP_DATA_LENGTH; indx++)
80029f4: 2300 movs r3, #0
80029f6: 73bb strb r3, [r7, #14]
80029f8: e013 b.n 8002a22 <otp_dump_after_boot+0x3a>
{
rslt = read_otp_word(indx, &otp_word, dev);
80029fa: f107 010c add.w r1, r7, #12
80029fe: 7bbb ldrb r3, [r7, #14]
8002a00: 687a ldr r2, [r7, #4]
8002a02: 4618 mov r0, r3
8002a04: f7ff fc98 bl 8002338 <read_otp_word>
8002a08: 4603 mov r3, r0
8002a0a: 73fb strb r3, [r7, #15]
dev->otp_data[indx] = otp_word;
8002a0c: 7bbb ldrb r3, [r7, #14]
8002a0e: 89b9 ldrh r1, [r7, #12]
8002a10: 687a ldr r2, [r7, #4]
8002a12: 3330 adds r3, #48 @ 0x30
8002a14: 005b lsls r3, r3, #1
8002a16: 4413 add r3, r2
8002a18: 460a mov r2, r1
8002a1a: 809a strh r2, [r3, #4]
for (indx = 0; indx < BMM350_OTP_DATA_LENGTH; indx++)
8002a1c: 7bbb ldrb r3, [r7, #14]
8002a1e: 3301 adds r3, #1
8002a20: 73bb strb r3, [r7, #14]
8002a22: 7bbb ldrb r3, [r7, #14]
8002a24: 2b1f cmp r3, #31
8002a26: d9e8 bls.n 80029fa <otp_dump_after_boot+0x12>
}
dev->var_id = (dev->otp_data[30] & 0x7f00) >> 9;
8002a28: 687b ldr r3, [r7, #4]
8002a2a: f8b3 30a0 ldrh.w r3, [r3, #160] @ 0xa0
8002a2e: 125b asrs r3, r3, #9
8002a30: b2db uxtb r3, r3
8002a32: f003 033f and.w r3, r3, #63 @ 0x3f
8002a36: b2da uxtb r2, r3
8002a38: 687b ldr r3, [r7, #4]
8002a3a: f883 20a4 strb.w r2, [r3, #164] @ 0xa4
/* Set the default auto bit reset configuration */
dev->enable_auto_br = ((dev->var_id > BMM350_CURRENT_SHUTTLE_VARIANT_ID) ? BMM350_DISABLE : BMM350_ENABLE);
8002a3e: 687b ldr r3, [r7, #4]
8002a40: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4
8002a44: 2b11 cmp r3, #17
8002a46: bf94 ite ls
8002a48: 2301 movls r3, #1
8002a4a: 2300 movhi r3, #0
8002a4c: b2db uxtb r3, r3
8002a4e: 461a mov r2, r3
8002a50: 687b ldr r3, [r7, #4]
8002a52: f883 20ad strb.w r2, [r3, #173] @ 0xad
/* Update magnetometer offset and sensitivity data. */
update_mag_off_sens(dev);
8002a56: 6878 ldr r0, [r7, #4]
8002a58: f7ff fd10 bl 800247c <update_mag_off_sens>
return rslt;
8002a5c: f997 300f ldrsb.w r3, [r7, #15]
}
8002a60: 4618 mov r0, r3
8002a62: 3710 adds r7, #16
8002a64: 46bd mov sp, r7
8002a66: bd80 pop {r7, pc}
08002a68 <set_powermode>:
/*!
* @brief This internal API is used to switch from suspend mode to normal mode or forced mode.
*/
static int8_t set_powermode(enum bmm350_power_modes powermode, struct bmm350_dev *dev)
{
8002a68: b590 push {r4, r7, lr}
8002a6a: b08f sub sp, #60 @ 0x3c
8002a6c: af00 add r7, sp, #0
8002a6e: 4603 mov r3, r0
8002a70: 6039 str r1, [r7, #0]
8002a72: 71fb strb r3, [r7, #7]
/* Variable to store the function result */
int8_t rslt;
uint8_t reg_data = powermode;
8002a74: 79fb ldrb r3, [r7, #7]
8002a76: f887 302f strb.w r3, [r7, #47] @ 0x2f
uint8_t get_avg;
/* Array to store suspend to forced mode delay */
uint32_t sus_to_forced_mode[4] =
8002a7a: 4b36 ldr r3, [pc, #216] @ (8002b54 <set_powermode+0xec>)
8002a7c: f107 041c add.w r4, r7, #28
8002a80: cb0f ldmia r3, {r0, r1, r2, r3}
8002a82: e884 000f stmia.w r4, {r0, r1, r2, r3}
{ BMM350_SUS_TO_FORCEDMODE_NO_AVG_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_2_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_4_DELAY,
BMM350_SUS_TO_FORCEDMODE_AVG_8_DELAY };
/* Array to store suspend to forced mode fast delay */
uint32_t sus_to_forced_mode_fast[4] =
8002a86: 4b34 ldr r3, [pc, #208] @ (8002b58 <set_powermode+0xf0>)
8002a88: f107 040c add.w r4, r7, #12
8002a8c: cb0f ldmia r3, {r0, r1, r2, r3}
8002a8e: e884 000f stmia.w r4, {r0, r1, r2, r3}
{ BMM350_SUS_TO_FORCEDMODE_FAST_NO_AVG_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_2_DELAY,
BMM350_SUS_TO_FORCEDMODE_FAST_AVG_4_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_8_DELAY };
uint8_t avg = 0;
8002a92: 2300 movs r3, #0
8002a94: f887 3036 strb.w r3, [r7, #54] @ 0x36
uint32_t delay_us = 0;
8002a98: 2300 movs r3, #0
8002a9a: 633b str r3, [r7, #48] @ 0x30
rslt = null_ptr_check(dev);
8002a9c: 6838 ldr r0, [r7, #0]
8002a9e: f7ff fbd0 bl 8002242 <null_ptr_check>
8002aa2: 4603 mov r3, r0
8002aa4: f887 3037 strb.w r3, [r7, #55] @ 0x37
if (rslt == BMM350_OK)
8002aa8: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
8002aac: 2b00 cmp r3, #0
8002aae: d123 bne.n 8002af8 <set_powermode+0x90>
{
/* Set PMU command configuration to desired power mode */
rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &reg_data, 1, dev);
8002ab0: f107 012f add.w r1, r7, #47 @ 0x2f
8002ab4: 683b ldr r3, [r7, #0]
8002ab6: 2201 movs r2, #1
8002ab8: 2006 movs r0, #6
8002aba: f7fe ff54 bl 8001966 <bmm350_set_regs>
8002abe: 4603 mov r3, r0
8002ac0: f887 3037 strb.w r3, [r7, #55] @ 0x37
if (rslt == BMM350_OK)
8002ac4: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
8002ac8: 2b00 cmp r3, #0
8002aca: d115 bne.n 8002af8 <set_powermode+0x90>
{
/* Get average configuration */
rslt = bmm350_get_regs(BMM350_REG_PMU_CMD_AGGR_SET, &get_avg, 1, dev);
8002acc: f107 012e add.w r1, r7, #46 @ 0x2e
8002ad0: 683b ldr r3, [r7, #0]
8002ad2: 2201 movs r2, #1
8002ad4: 2004 movs r0, #4
8002ad6: f7fe ff7a bl 80019ce <bmm350_get_regs>
8002ada: 4603 mov r3, r0
8002adc: f887 3037 strb.w r3, [r7, #55] @ 0x37
if (rslt == BMM350_OK)
8002ae0: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
8002ae4: 2b00 cmp r3, #0
8002ae6: d107 bne.n 8002af8 <set_powermode+0x90>
{
/* Mask the average value */
avg = ((get_avg & BMM350_AVG_MSK) >> BMM350_AVG_POS);
8002ae8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
8002aec: 111b asrs r3, r3, #4
8002aee: b2db uxtb r3, r3
8002af0: f003 0303 and.w r3, r3, #3
8002af4: f887 3036 strb.w r3, [r7, #54] @ 0x36
}
}
}
if (rslt == BMM350_OK)
8002af8: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
8002afc: 2b00 cmp r3, #0
8002afe: d122 bne.n 8002b46 <set_powermode+0xde>
{
/* Check if desired power mode is normal mode */
if (powermode == BMM350_NORMAL_MODE)
8002b00: 79fb ldrb r3, [r7, #7]
8002b02: 2b01 cmp r3, #1
8002b04: d102 bne.n 8002b0c <set_powermode+0xa4>
{
delay_us = BMM350_SUSPEND_TO_NORMAL_DELAY;
8002b06: f249 4370 movw r3, #38000 @ 0x9470
8002b0a: 633b str r3, [r7, #48] @ 0x30
}
/* Check if desired power mode is forced mode */
if (powermode == BMM350_FORCED_MODE)
8002b0c: 79fb ldrb r3, [r7, #7]
8002b0e: 2b03 cmp r3, #3
8002b10: d107 bne.n 8002b22 <set_powermode+0xba>
{
/* Store delay based on averaging mode */
delay_us = sus_to_forced_mode[avg];
8002b12: f897 3036 ldrb.w r3, [r7, #54] @ 0x36
8002b16: 009b lsls r3, r3, #2
8002b18: 3338 adds r3, #56 @ 0x38
8002b1a: 443b add r3, r7
8002b1c: f853 3c1c ldr.w r3, [r3, #-28]
8002b20: 633b str r3, [r7, #48] @ 0x30
}
/* Check if desired power mode is forced mode fast */
if (powermode == BMM350_FORCED_MODE_FAST)
8002b22: 79fb ldrb r3, [r7, #7]
8002b24: 2b04 cmp r3, #4
8002b26: d107 bne.n 8002b38 <set_powermode+0xd0>
{
/* Store delay based on averaging mode */
delay_us = sus_to_forced_mode_fast[avg];
8002b28: f897 3036 ldrb.w r3, [r7, #54] @ 0x36
8002b2c: 009b lsls r3, r3, #2
8002b2e: 3338 adds r3, #56 @ 0x38
8002b30: 443b add r3, r7
8002b32: f853 3c2c ldr.w r3, [r3, #-44]
8002b36: 633b str r3, [r7, #48] @ 0x30
}
/* Perform delay based on power mode */
rslt = bmm350_delay_us(delay_us, dev);
8002b38: 6839 ldr r1, [r7, #0]
8002b3a: 6b38 ldr r0, [r7, #48] @ 0x30
8002b3c: f7fe ff9c bl 8001a78 <bmm350_delay_us>
8002b40: 4603 mov r3, r0
8002b42: f887 3037 strb.w r3, [r7, #55] @ 0x37
}
return rslt;
8002b46: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37
}
8002b4a: 4618 mov r0, r3
8002b4c: 373c adds r7, #60 @ 0x3c
8002b4e: 46bd mov sp, r7
8002b50: bd90 pop {r4, r7, pc}
8002b52: bf00 nop
8002b54: 0801c0c4 .word 0x0801c0c4
8002b58: 0801c0d4 .word 0x0801c0d4
08002b5c <LL_EXTI_EnableIT_0_31>:
{
8002b5c: b480 push {r7}
8002b5e: b083 sub sp, #12
8002b60: af00 add r7, sp, #0
8002b62: 6078 str r0, [r7, #4]
SET_BIT(EXTI->IMR1, ExtiLine);
8002b64: 4b06 ldr r3, [pc, #24] @ (8002b80 <LL_EXTI_EnableIT_0_31+0x24>)
8002b66: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80
8002b6a: 4905 ldr r1, [pc, #20] @ (8002b80 <LL_EXTI_EnableIT_0_31+0x24>)
8002b6c: 687b ldr r3, [r7, #4]
8002b6e: 4313 orrs r3, r2
8002b70: f8c1 3080 str.w r3, [r1, #128] @ 0x80
}
8002b74: bf00 nop
8002b76: 370c adds r7, #12
8002b78: 46bd mov sp, r7
8002b7a: f85d 7b04 ldr.w r7, [sp], #4
8002b7e: 4770 bx lr
8002b80: 58000800 .word 0x58000800
08002b84 <LL_EXTI_EnableRisingTrig_0_31>:
* @arg @ref LL_EXTI_LINE_31 (*)
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
8002b84: b480 push {r7}
8002b86: b083 sub sp, #12
8002b88: af00 add r7, sp, #0
8002b8a: 6078 str r0, [r7, #4]
SET_BIT(EXTI->RTSR1, ExtiLine);
8002b8c: 4b05 ldr r3, [pc, #20] @ (8002ba4 <LL_EXTI_EnableRisingTrig_0_31+0x20>)
8002b8e: 681a ldr r2, [r3, #0]
8002b90: 4904 ldr r1, [pc, #16] @ (8002ba4 <LL_EXTI_EnableRisingTrig_0_31+0x20>)
8002b92: 687b ldr r3, [r7, #4]
8002b94: 4313 orrs r3, r2
8002b96: 600b str r3, [r1, #0]
}
8002b98: bf00 nop
8002b9a: 370c adds r7, #12
8002b9c: 46bd mov sp, r7
8002b9e: f85d 7b04 ldr.w r7, [sp], #4
8002ba2: 4770 bx lr
8002ba4: 58000800 .word 0x58000800
08002ba8 <ReadRtcSsrValue>:
* reliability of the value
* @param None
* @retval SSR value read
*/
static uint32_t ReadRtcSsrValue(void)
{
8002ba8: b480 push {r7}
8002baa: b083 sub sp, #12
8002bac: af00 add r7, sp, #0
uint32_t first_read;
uint32_t second_read;
first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
8002bae: 4b0d ldr r3, [pc, #52] @ (8002be4 <ReadRtcSsrValue+0x3c>)
8002bb0: 6a9b ldr r3, [r3, #40] @ 0x28
8002bb2: b29b uxth r3, r3
8002bb4: 607b str r3, [r7, #4]
second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
8002bb6: 4b0b ldr r3, [pc, #44] @ (8002be4 <ReadRtcSsrValue+0x3c>)
8002bb8: 6a9b ldr r3, [r3, #40] @ 0x28
8002bba: b29b uxth r3, r3
8002bbc: 603b str r3, [r7, #0]
while(first_read != second_read)
8002bbe: e005 b.n 8002bcc <ReadRtcSsrValue+0x24>
{
first_read = second_read;
8002bc0: 683b ldr r3, [r7, #0]
8002bc2: 607b str r3, [r7, #4]
second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS));
8002bc4: 4b07 ldr r3, [pc, #28] @ (8002be4 <ReadRtcSsrValue+0x3c>)
8002bc6: 6a9b ldr r3, [r3, #40] @ 0x28
8002bc8: b29b uxth r3, r3
8002bca: 603b str r3, [r7, #0]
while(first_read != second_read)
8002bcc: 687a ldr r2, [r7, #4]
8002bce: 683b ldr r3, [r7, #0]
8002bd0: 429a cmp r2, r3
8002bd2: d1f5 bne.n 8002bc0 <ReadRtcSsrValue+0x18>
}
return second_read;
8002bd4: 683b ldr r3, [r7, #0]
}
8002bd6: 4618 mov r0, r3
8002bd8: 370c adds r7, #12
8002bda: 46bd mov sp, r7
8002bdc: f85d 7b04 ldr.w r7, [sp], #4
8002be0: 4770 bx lr
8002be2: bf00 nop
8002be4: 40002800 .word 0x40002800
08002be8 <LinkTimerAfter>:
* @param TimerID: The ID of the Timer
* @param RefTimerID: The ID of the Timer to be linked after
* @retval None
*/
static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID)
{
8002be8: b480 push {r7}
8002bea: b085 sub sp, #20
8002bec: af00 add r7, sp, #0
8002bee: 4603 mov r3, r0
8002bf0: 460a mov r2, r1
8002bf2: 71fb strb r3, [r7, #7]
8002bf4: 4613 mov r3, r2
8002bf6: 71bb strb r3, [r7, #6]
uint8_t next_id;
next_id = aTimerContext[RefTimerID].NextID;
8002bf8: 79ba ldrb r2, [r7, #6]
8002bfa: 491d ldr r1, [pc, #116] @ (8002c70 <LinkTimerAfter+0x88>)
8002bfc: 4613 mov r3, r2
8002bfe: 005b lsls r3, r3, #1
8002c00: 4413 add r3, r2
8002c02: 00db lsls r3, r3, #3
8002c04: 440b add r3, r1
8002c06: 3315 adds r3, #21
8002c08: 781b ldrb r3, [r3, #0]
8002c0a: 73fb strb r3, [r7, #15]
if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
8002c0c: 7bfb ldrb r3, [r7, #15]
8002c0e: 2b06 cmp r3, #6
8002c10: d009 beq.n 8002c26 <LinkTimerAfter+0x3e>
{
aTimerContext[next_id].PreviousID = TimerID;
8002c12: 7bfa ldrb r2, [r7, #15]
8002c14: 4916 ldr r1, [pc, #88] @ (8002c70 <LinkTimerAfter+0x88>)
8002c16: 4613 mov r3, r2
8002c18: 005b lsls r3, r3, #1
8002c1a: 4413 add r3, r2
8002c1c: 00db lsls r3, r3, #3
8002c1e: 440b add r3, r1
8002c20: 3314 adds r3, #20
8002c22: 79fa ldrb r2, [r7, #7]
8002c24: 701a strb r2, [r3, #0]
}
aTimerContext[TimerID].NextID = next_id;
8002c26: 79fa ldrb r2, [r7, #7]
8002c28: 4911 ldr r1, [pc, #68] @ (8002c70 <LinkTimerAfter+0x88>)
8002c2a: 4613 mov r3, r2
8002c2c: 005b lsls r3, r3, #1
8002c2e: 4413 add r3, r2
8002c30: 00db lsls r3, r3, #3
8002c32: 440b add r3, r1
8002c34: 3315 adds r3, #21
8002c36: 7bfa ldrb r2, [r7, #15]
8002c38: 701a strb r2, [r3, #0]
aTimerContext[TimerID].PreviousID = RefTimerID ;
8002c3a: 79fa ldrb r2, [r7, #7]
8002c3c: 490c ldr r1, [pc, #48] @ (8002c70 <LinkTimerAfter+0x88>)
8002c3e: 4613 mov r3, r2
8002c40: 005b lsls r3, r3, #1
8002c42: 4413 add r3, r2
8002c44: 00db lsls r3, r3, #3
8002c46: 440b add r3, r1
8002c48: 3314 adds r3, #20
8002c4a: 79ba ldrb r2, [r7, #6]
8002c4c: 701a strb r2, [r3, #0]
aTimerContext[RefTimerID].NextID = TimerID;
8002c4e: 79ba ldrb r2, [r7, #6]
8002c50: 4907 ldr r1, [pc, #28] @ (8002c70 <LinkTimerAfter+0x88>)
8002c52: 4613 mov r3, r2
8002c54: 005b lsls r3, r3, #1
8002c56: 4413 add r3, r2
8002c58: 00db lsls r3, r3, #3
8002c5a: 440b add r3, r1
8002c5c: 3315 adds r3, #21
8002c5e: 79fa ldrb r2, [r7, #7]
8002c60: 701a strb r2, [r3, #0]
return;
8002c62: bf00 nop
}
8002c64: 3714 adds r7, #20
8002c66: 46bd mov sp, r7
8002c68: f85d 7b04 ldr.w r7, [sp], #4
8002c6c: 4770 bx lr
8002c6e: bf00 nop
8002c70: 20000314 .word 0x20000314
08002c74 <LinkTimerBefore>:
* @param TimerID: The ID of the Timer
* @param RefTimerID: The ID of the Timer to be linked before
* @retval None
*/
static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID)
{
8002c74: b480 push {r7}
8002c76: b085 sub sp, #20
8002c78: af00 add r7, sp, #0
8002c7a: 4603 mov r3, r0
8002c7c: 460a mov r2, r1
8002c7e: 71fb strb r3, [r7, #7]
8002c80: 4613 mov r3, r2
8002c82: 71bb strb r3, [r7, #6]
uint8_t previous_id;
if(RefTimerID != CurrentRunningTimerID)
8002c84: 4b29 ldr r3, [pc, #164] @ (8002d2c <LinkTimerBefore+0xb8>)
8002c86: 781b ldrb r3, [r3, #0]
8002c88: b2db uxtb r3, r3
8002c8a: 79ba ldrb r2, [r7, #6]
8002c8c: 429a cmp r2, r3
8002c8e: d032 beq.n 8002cf6 <LinkTimerBefore+0x82>
{
previous_id = aTimerContext[RefTimerID].PreviousID;
8002c90: 79ba ldrb r2, [r7, #6]
8002c92: 4927 ldr r1, [pc, #156] @ (8002d30 <LinkTimerBefore+0xbc>)
8002c94: 4613 mov r3, r2
8002c96: 005b lsls r3, r3, #1
8002c98: 4413 add r3, r2
8002c9a: 00db lsls r3, r3, #3
8002c9c: 440b add r3, r1
8002c9e: 3314 adds r3, #20
8002ca0: 781b ldrb r3, [r3, #0]
8002ca2: 73fb strb r3, [r7, #15]
aTimerContext[previous_id].NextID = TimerID;
8002ca4: 7bfa ldrb r2, [r7, #15]
8002ca6: 4922 ldr r1, [pc, #136] @ (8002d30 <LinkTimerBefore+0xbc>)
8002ca8: 4613 mov r3, r2
8002caa: 005b lsls r3, r3, #1
8002cac: 4413 add r3, r2
8002cae: 00db lsls r3, r3, #3
8002cb0: 440b add r3, r1
8002cb2: 3315 adds r3, #21
8002cb4: 79fa ldrb r2, [r7, #7]
8002cb6: 701a strb r2, [r3, #0]
aTimerContext[TimerID].NextID = RefTimerID;
8002cb8: 79fa ldrb r2, [r7, #7]
8002cba: 491d ldr r1, [pc, #116] @ (8002d30 <LinkTimerBefore+0xbc>)
8002cbc: 4613 mov r3, r2
8002cbe: 005b lsls r3, r3, #1
8002cc0: 4413 add r3, r2
8002cc2: 00db lsls r3, r3, #3
8002cc4: 440b add r3, r1
8002cc6: 3315 adds r3, #21
8002cc8: 79ba ldrb r2, [r7, #6]
8002cca: 701a strb r2, [r3, #0]
aTimerContext[TimerID].PreviousID = previous_id ;
8002ccc: 79fa ldrb r2, [r7, #7]
8002cce: 4918 ldr r1, [pc, #96] @ (8002d30 <LinkTimerBefore+0xbc>)
8002cd0: 4613 mov r3, r2
8002cd2: 005b lsls r3, r3, #1
8002cd4: 4413 add r3, r2
8002cd6: 00db lsls r3, r3, #3
8002cd8: 440b add r3, r1
8002cda: 3314 adds r3, #20
8002cdc: 7bfa ldrb r2, [r7, #15]
8002cde: 701a strb r2, [r3, #0]
aTimerContext[RefTimerID].PreviousID = TimerID;
8002ce0: 79ba ldrb r2, [r7, #6]
8002ce2: 4913 ldr r1, [pc, #76] @ (8002d30 <LinkTimerBefore+0xbc>)
8002ce4: 4613 mov r3, r2
8002ce6: 005b lsls r3, r3, #1
8002ce8: 4413 add r3, r2
8002cea: 00db lsls r3, r3, #3
8002cec: 440b add r3, r1
8002cee: 3314 adds r3, #20
8002cf0: 79fa ldrb r2, [r7, #7]
8002cf2: 701a strb r2, [r3, #0]
{
aTimerContext[TimerID].NextID = RefTimerID;
aTimerContext[RefTimerID].PreviousID = TimerID;
}
return;
8002cf4: e014 b.n 8002d20 <LinkTimerBefore+0xac>
aTimerContext[TimerID].NextID = RefTimerID;
8002cf6: 79fa ldrb r2, [r7, #7]
8002cf8: 490d ldr r1, [pc, #52] @ (8002d30 <LinkTimerBefore+0xbc>)
8002cfa: 4613 mov r3, r2
8002cfc: 005b lsls r3, r3, #1
8002cfe: 4413 add r3, r2
8002d00: 00db lsls r3, r3, #3
8002d02: 440b add r3, r1
8002d04: 3315 adds r3, #21
8002d06: 79ba ldrb r2, [r7, #6]
8002d08: 701a strb r2, [r3, #0]
aTimerContext[RefTimerID].PreviousID = TimerID;
8002d0a: 79ba ldrb r2, [r7, #6]
8002d0c: 4908 ldr r1, [pc, #32] @ (8002d30 <LinkTimerBefore+0xbc>)
8002d0e: 4613 mov r3, r2
8002d10: 005b lsls r3, r3, #1
8002d12: 4413 add r3, r2
8002d14: 00db lsls r3, r3, #3
8002d16: 440b add r3, r1
8002d18: 3314 adds r3, #20
8002d1a: 79fa ldrb r2, [r7, #7]
8002d1c: 701a strb r2, [r3, #0]
return;
8002d1e: bf00 nop
}
8002d20: 3714 adds r7, #20
8002d22: 46bd mov sp, r7
8002d24: f85d 7b04 ldr.w r7, [sp], #4
8002d28: 4770 bx lr
8002d2a: bf00 nop
8002d2c: 200003a4 .word 0x200003a4
8002d30: 20000314 .word 0x20000314
08002d34 <linkTimer>:
* @brief Insert a Timer in the list
* @param TimerID: The ID of the Timer
* @retval None
*/
static uint16_t linkTimer(uint8_t TimerID)
{
8002d34: b580 push {r7, lr}
8002d36: b084 sub sp, #16
8002d38: af00 add r7, sp, #0
8002d3a: 4603 mov r3, r0
8002d3c: 71fb strb r3, [r7, #7]
uint32_t time_left;
uint16_t time_elapsed;
uint8_t timer_id_lookup;
uint8_t next_id;
if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
8002d3e: 4b4e ldr r3, [pc, #312] @ (8002e78 <linkTimer+0x144>)
8002d40: 781b ldrb r3, [r3, #0]
8002d42: b2db uxtb r3, r3
8002d44: 2b06 cmp r3, #6
8002d46: d118 bne.n 8002d7a <linkTimer+0x46>
{
/**
* No timer in the list
*/
PreviousRunningTimerID = CurrentRunningTimerID;
8002d48: 4b4b ldr r3, [pc, #300] @ (8002e78 <linkTimer+0x144>)
8002d4a: 781b ldrb r3, [r3, #0]
8002d4c: b2da uxtb r2, r3
8002d4e: 4b4b ldr r3, [pc, #300] @ (8002e7c <linkTimer+0x148>)
8002d50: 701a strb r2, [r3, #0]
CurrentRunningTimerID = TimerID;
8002d52: 4a49 ldr r2, [pc, #292] @ (8002e78 <linkTimer+0x144>)
8002d54: 79fb ldrb r3, [r7, #7]
8002d56: 7013 strb r3, [r2, #0]
aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER;
8002d58: 79fa ldrb r2, [r7, #7]
8002d5a: 4949 ldr r1, [pc, #292] @ (8002e80 <linkTimer+0x14c>)
8002d5c: 4613 mov r3, r2
8002d5e: 005b lsls r3, r3, #1
8002d60: 4413 add r3, r2
8002d62: 00db lsls r3, r3, #3
8002d64: 440b add r3, r1
8002d66: 3315 adds r3, #21
8002d68: 2206 movs r2, #6
8002d6a: 701a strb r2, [r3, #0]
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
8002d6c: 4b45 ldr r3, [pc, #276] @ (8002e84 <linkTimer+0x150>)
8002d6e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8002d72: 601a str r2, [r3, #0]
time_elapsed = 0;
8002d74: 2300 movs r3, #0
8002d76: 81fb strh r3, [r7, #14]
8002d78: e078 b.n 8002e6c <linkTimer+0x138>
}
else
{
time_elapsed = ReturnTimeElapsed();
8002d7a: f000 f909 bl 8002f90 <ReturnTimeElapsed>
8002d7e: 4603 mov r3, r0
8002d80: 81fb strh r3, [r7, #14]
/**
* update count of the timer to be linked
*/
aTimerContext[TimerID].CountLeft += time_elapsed;
8002d82: 79fa ldrb r2, [r7, #7]
8002d84: 493e ldr r1, [pc, #248] @ (8002e80 <linkTimer+0x14c>)
8002d86: 4613 mov r3, r2
8002d88: 005b lsls r3, r3, #1
8002d8a: 4413 add r3, r2
8002d8c: 00db lsls r3, r3, #3
8002d8e: 440b add r3, r1
8002d90: 3308 adds r3, #8
8002d92: 6819 ldr r1, [r3, #0]
8002d94: 89fb ldrh r3, [r7, #14]
8002d96: 79fa ldrb r2, [r7, #7]
8002d98: 4419 add r1, r3
8002d9a: 4839 ldr r0, [pc, #228] @ (8002e80 <linkTimer+0x14c>)
8002d9c: 4613 mov r3, r2
8002d9e: 005b lsls r3, r3, #1
8002da0: 4413 add r3, r2
8002da2: 00db lsls r3, r3, #3
8002da4: 4403 add r3, r0
8002da6: 3308 adds r3, #8
8002da8: 6019 str r1, [r3, #0]
time_left = aTimerContext[TimerID].CountLeft;
8002daa: 79fa ldrb r2, [r7, #7]
8002dac: 4934 ldr r1, [pc, #208] @ (8002e80 <linkTimer+0x14c>)
8002dae: 4613 mov r3, r2
8002db0: 005b lsls r3, r3, #1
8002db2: 4413 add r3, r2
8002db4: 00db lsls r3, r3, #3
8002db6: 440b add r3, r1
8002db8: 3308 adds r3, #8
8002dba: 681b ldr r3, [r3, #0]
8002dbc: 60bb str r3, [r7, #8]
/**
* Search for index where the new timer shall be linked
*/
if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left)
8002dbe: 4b2e ldr r3, [pc, #184] @ (8002e78 <linkTimer+0x144>)
8002dc0: 781b ldrb r3, [r3, #0]
8002dc2: b2db uxtb r3, r3
8002dc4: 4619 mov r1, r3
8002dc6: 4a2e ldr r2, [pc, #184] @ (8002e80 <linkTimer+0x14c>)
8002dc8: 460b mov r3, r1
8002dca: 005b lsls r3, r3, #1
8002dcc: 440b add r3, r1
8002dce: 00db lsls r3, r3, #3
8002dd0: 4413 add r3, r2
8002dd2: 3308 adds r3, #8
8002dd4: 681b ldr r3, [r3, #0]
8002dd6: 68ba ldr r2, [r7, #8]
8002dd8: 429a cmp r2, r3
8002dda: d337 bcc.n 8002e4c <linkTimer+0x118>
{
/**
* Search for the ID after the first one
*/
timer_id_lookup = CurrentRunningTimerID;
8002ddc: 4b26 ldr r3, [pc, #152] @ (8002e78 <linkTimer+0x144>)
8002dde: 781b ldrb r3, [r3, #0]
8002de0: 737b strb r3, [r7, #13]
next_id = aTimerContext[timer_id_lookup].NextID;
8002de2: 7b7a ldrb r2, [r7, #13]
8002de4: 4926 ldr r1, [pc, #152] @ (8002e80 <linkTimer+0x14c>)
8002de6: 4613 mov r3, r2
8002de8: 005b lsls r3, r3, #1
8002dea: 4413 add r3, r2
8002dec: 00db lsls r3, r3, #3
8002dee: 440b add r3, r1
8002df0: 3315 adds r3, #21
8002df2: 781b ldrb r3, [r3, #0]
8002df4: 733b strb r3, [r7, #12]
while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
8002df6: e013 b.n 8002e20 <linkTimer+0xec>
{
timer_id_lookup = aTimerContext[timer_id_lookup].NextID;
8002df8: 7b7a ldrb r2, [r7, #13]
8002dfa: 4921 ldr r1, [pc, #132] @ (8002e80 <linkTimer+0x14c>)
8002dfc: 4613 mov r3, r2
8002dfe: 005b lsls r3, r3, #1
8002e00: 4413 add r3, r2
8002e02: 00db lsls r3, r3, #3
8002e04: 440b add r3, r1
8002e06: 3315 adds r3, #21
8002e08: 781b ldrb r3, [r3, #0]
8002e0a: 737b strb r3, [r7, #13]
next_id = aTimerContext[timer_id_lookup].NextID;
8002e0c: 7b7a ldrb r2, [r7, #13]
8002e0e: 491c ldr r1, [pc, #112] @ (8002e80 <linkTimer+0x14c>)
8002e10: 4613 mov r3, r2
8002e12: 005b lsls r3, r3, #1
8002e14: 4413 add r3, r2
8002e16: 00db lsls r3, r3, #3
8002e18: 440b add r3, r1
8002e1a: 3315 adds r3, #21
8002e1c: 781b ldrb r3, [r3, #0]
8002e1e: 733b strb r3, [r7, #12]
while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left))
8002e20: 7b3b ldrb r3, [r7, #12]
8002e22: 2b06 cmp r3, #6
8002e24: d00b beq.n 8002e3e <linkTimer+0x10a>
8002e26: 7b3a ldrb r2, [r7, #12]
8002e28: 4915 ldr r1, [pc, #84] @ (8002e80 <linkTimer+0x14c>)
8002e2a: 4613 mov r3, r2
8002e2c: 005b lsls r3, r3, #1
8002e2e: 4413 add r3, r2
8002e30: 00db lsls r3, r3, #3
8002e32: 440b add r3, r1
8002e34: 3308 adds r3, #8
8002e36: 681b ldr r3, [r3, #0]
8002e38: 68ba ldr r2, [r7, #8]
8002e3a: 429a cmp r2, r3
8002e3c: d2dc bcs.n 8002df8 <linkTimer+0xc4>
}
/**
* Link after the ID
*/
LinkTimerAfter(TimerID, timer_id_lookup);
8002e3e: 7b7a ldrb r2, [r7, #13]
8002e40: 79fb ldrb r3, [r7, #7]
8002e42: 4611 mov r1, r2
8002e44: 4618 mov r0, r3
8002e46: f7ff fecf bl 8002be8 <LinkTimerAfter>
8002e4a: e00f b.n 8002e6c <linkTimer+0x138>
else
{
/**
* Link before the first ID
*/
LinkTimerBefore(TimerID, CurrentRunningTimerID);
8002e4c: 4b0a ldr r3, [pc, #40] @ (8002e78 <linkTimer+0x144>)
8002e4e: 781b ldrb r3, [r3, #0]
8002e50: b2da uxtb r2, r3
8002e52: 79fb ldrb r3, [r7, #7]
8002e54: 4611 mov r1, r2
8002e56: 4618 mov r0, r3
8002e58: f7ff ff0c bl 8002c74 <LinkTimerBefore>
PreviousRunningTimerID = CurrentRunningTimerID;
8002e5c: 4b06 ldr r3, [pc, #24] @ (8002e78 <linkTimer+0x144>)
8002e5e: 781b ldrb r3, [r3, #0]
8002e60: b2da uxtb r2, r3
8002e62: 4b06 ldr r3, [pc, #24] @ (8002e7c <linkTimer+0x148>)
8002e64: 701a strb r2, [r3, #0]
CurrentRunningTimerID = TimerID;
8002e66: 4a04 ldr r2, [pc, #16] @ (8002e78 <linkTimer+0x144>)
8002e68: 79fb ldrb r3, [r7, #7]
8002e6a: 7013 strb r3, [r2, #0]
}
}
return time_elapsed;
8002e6c: 89fb ldrh r3, [r7, #14]
}
8002e6e: 4618 mov r0, r3
8002e70: 3710 adds r7, #16
8002e72: 46bd mov sp, r7
8002e74: bd80 pop {r7, pc}
8002e76: bf00 nop
8002e78: 200003a4 .word 0x200003a4
8002e7c: 200003a5 .word 0x200003a5
8002e80: 20000314 .word 0x20000314
8002e84: 200003a8 .word 0x200003a8
08002e88 <UnlinkTimer>:
* @param TimerID: The ID of the Timer
* @param RequestReadSSR: Request to read the SSR register or not
* @retval None
*/
static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR)
{
8002e88: b480 push {r7}
8002e8a: b085 sub sp, #20
8002e8c: af00 add r7, sp, #0
8002e8e: 4603 mov r3, r0
8002e90: 460a mov r2, r1
8002e92: 71fb strb r3, [r7, #7]
8002e94: 4613 mov r3, r2
8002e96: 71bb strb r3, [r7, #6]
uint8_t previous_id;
uint8_t next_id;
if(TimerID == CurrentRunningTimerID)
8002e98: 4b39 ldr r3, [pc, #228] @ (8002f80 <UnlinkTimer+0xf8>)
8002e9a: 781b ldrb r3, [r3, #0]
8002e9c: b2db uxtb r3, r3
8002e9e: 79fa ldrb r2, [r7, #7]
8002ea0: 429a cmp r2, r3
8002ea2: d111 bne.n 8002ec8 <UnlinkTimer+0x40>
{
PreviousRunningTimerID = CurrentRunningTimerID;
8002ea4: 4b36 ldr r3, [pc, #216] @ (8002f80 <UnlinkTimer+0xf8>)
8002ea6: 781b ldrb r3, [r3, #0]
8002ea8: b2da uxtb r2, r3
8002eaa: 4b36 ldr r3, [pc, #216] @ (8002f84 <UnlinkTimer+0xfc>)
8002eac: 701a strb r2, [r3, #0]
CurrentRunningTimerID = aTimerContext[TimerID].NextID;
8002eae: 79fa ldrb r2, [r7, #7]
8002eb0: 4935 ldr r1, [pc, #212] @ (8002f88 <UnlinkTimer+0x100>)
8002eb2: 4613 mov r3, r2
8002eb4: 005b lsls r3, r3, #1
8002eb6: 4413 add r3, r2
8002eb8: 00db lsls r3, r3, #3
8002eba: 440b add r3, r1
8002ebc: 3315 adds r3, #21
8002ebe: 781b ldrb r3, [r3, #0]
8002ec0: b2da uxtb r2, r3
8002ec2: 4b2f ldr r3, [pc, #188] @ (8002f80 <UnlinkTimer+0xf8>)
8002ec4: 701a strb r2, [r3, #0]
8002ec6: e03e b.n 8002f46 <UnlinkTimer+0xbe>
}
else
{
previous_id = aTimerContext[TimerID].PreviousID;
8002ec8: 79fa ldrb r2, [r7, #7]
8002eca: 492f ldr r1, [pc, #188] @ (8002f88 <UnlinkTimer+0x100>)
8002ecc: 4613 mov r3, r2
8002ece: 005b lsls r3, r3, #1
8002ed0: 4413 add r3, r2
8002ed2: 00db lsls r3, r3, #3
8002ed4: 440b add r3, r1
8002ed6: 3314 adds r3, #20
8002ed8: 781b ldrb r3, [r3, #0]
8002eda: 73fb strb r3, [r7, #15]
next_id = aTimerContext[TimerID].NextID;
8002edc: 79fa ldrb r2, [r7, #7]
8002ede: 492a ldr r1, [pc, #168] @ (8002f88 <UnlinkTimer+0x100>)
8002ee0: 4613 mov r3, r2
8002ee2: 005b lsls r3, r3, #1
8002ee4: 4413 add r3, r2
8002ee6: 00db lsls r3, r3, #3
8002ee8: 440b add r3, r1
8002eea: 3315 adds r3, #21
8002eec: 781b ldrb r3, [r3, #0]
8002eee: 73bb strb r3, [r7, #14]
aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID;
8002ef0: 79f9 ldrb r1, [r7, #7]
8002ef2: 7bfa ldrb r2, [r7, #15]
8002ef4: 4824 ldr r0, [pc, #144] @ (8002f88 <UnlinkTimer+0x100>)
8002ef6: 460b mov r3, r1
8002ef8: 005b lsls r3, r3, #1
8002efa: 440b add r3, r1
8002efc: 00db lsls r3, r3, #3
8002efe: 4403 add r3, r0
8002f00: 3315 adds r3, #21
8002f02: 781b ldrb r3, [r3, #0]
8002f04: b2d8 uxtb r0, r3
8002f06: 4920 ldr r1, [pc, #128] @ (8002f88 <UnlinkTimer+0x100>)
8002f08: 4613 mov r3, r2
8002f0a: 005b lsls r3, r3, #1
8002f0c: 4413 add r3, r2
8002f0e: 00db lsls r3, r3, #3
8002f10: 440b add r3, r1
8002f12: 3315 adds r3, #21
8002f14: 4602 mov r2, r0
8002f16: 701a strb r2, [r3, #0]
if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
8002f18: 7bbb ldrb r3, [r7, #14]
8002f1a: 2b06 cmp r3, #6
8002f1c: d013 beq.n 8002f46 <UnlinkTimer+0xbe>
{
aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID;
8002f1e: 79f9 ldrb r1, [r7, #7]
8002f20: 7bba ldrb r2, [r7, #14]
8002f22: 4819 ldr r0, [pc, #100] @ (8002f88 <UnlinkTimer+0x100>)
8002f24: 460b mov r3, r1
8002f26: 005b lsls r3, r3, #1
8002f28: 440b add r3, r1
8002f2a: 00db lsls r3, r3, #3
8002f2c: 4403 add r3, r0
8002f2e: 3314 adds r3, #20
8002f30: 781b ldrb r3, [r3, #0]
8002f32: b2d8 uxtb r0, r3
8002f34: 4914 ldr r1, [pc, #80] @ (8002f88 <UnlinkTimer+0x100>)
8002f36: 4613 mov r3, r2
8002f38: 005b lsls r3, r3, #1
8002f3a: 4413 add r3, r2
8002f3c: 00db lsls r3, r3, #3
8002f3e: 440b add r3, r1
8002f40: 3314 adds r3, #20
8002f42: 4602 mov r2, r0
8002f44: 701a strb r2, [r3, #0]
}
/**
* Timer is out of the list
*/
aTimerContext[TimerID].TimerIDStatus = TimerID_Created;
8002f46: 79fa ldrb r2, [r7, #7]
8002f48: 490f ldr r1, [pc, #60] @ (8002f88 <UnlinkTimer+0x100>)
8002f4a: 4613 mov r3, r2
8002f4c: 005b lsls r3, r3, #1
8002f4e: 4413 add r3, r2
8002f50: 00db lsls r3, r3, #3
8002f52: 440b add r3, r1
8002f54: 330c adds r3, #12
8002f56: 2201 movs r2, #1
8002f58: 701a strb r2, [r3, #0]
if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested))
8002f5a: 4b09 ldr r3, [pc, #36] @ (8002f80 <UnlinkTimer+0xf8>)
8002f5c: 781b ldrb r3, [r3, #0]
8002f5e: b2db uxtb r3, r3
8002f60: 2b06 cmp r3, #6
8002f62: d107 bne.n 8002f74 <UnlinkTimer+0xec>
8002f64: 79bb ldrb r3, [r7, #6]
8002f66: 2b00 cmp r3, #0
8002f68: d104 bne.n 8002f74 <UnlinkTimer+0xec>
{
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
8002f6a: 4b08 ldr r3, [pc, #32] @ (8002f8c <UnlinkTimer+0x104>)
8002f6c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8002f70: 601a str r2, [r3, #0]
}
return;
8002f72: bf00 nop
8002f74: bf00 nop
}
8002f76: 3714 adds r7, #20
8002f78: 46bd mov sp, r7
8002f7a: f85d 7b04 ldr.w r7, [sp], #4
8002f7e: 4770 bx lr
8002f80: 200003a4 .word 0x200003a4
8002f84: 200003a5 .word 0x200003a5
8002f88: 20000314 .word 0x20000314
8002f8c: 200003a8 .word 0x200003a8
08002f90 <ReturnTimeElapsed>:
* since the time the timer has been started
* @param None
* @retval Time expired in Ticks
*/
static uint16_t ReturnTimeElapsed(void)
{
8002f90: b580 push {r7, lr}
8002f92: b082 sub sp, #8
8002f94: af00 add r7, sp, #0
uint32_t return_value;
uint32_t wrap_counter;
if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE)
8002f96: 4b1a ldr r3, [pc, #104] @ (8003000 <ReturnTimeElapsed+0x70>)
8002f98: 681b ldr r3, [r3, #0]
8002f9a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8002f9e: d026 beq.n 8002fee <ReturnTimeElapsed+0x5e>
{
return_value = ReadRtcSsrValue(); /**< Read SSR register first */
8002fa0: f7ff fe02 bl 8002ba8 <ReadRtcSsrValue>
8002fa4: 6078 str r0, [r7, #4]
if (SSRValueOnLastSetup >= return_value)
8002fa6: 4b16 ldr r3, [pc, #88] @ (8003000 <ReturnTimeElapsed+0x70>)
8002fa8: 681b ldr r3, [r3, #0]
8002faa: 687a ldr r2, [r7, #4]
8002fac: 429a cmp r2, r3
8002fae: d805 bhi.n 8002fbc <ReturnTimeElapsed+0x2c>
{
return_value = SSRValueOnLastSetup - return_value;
8002fb0: 4b13 ldr r3, [pc, #76] @ (8003000 <ReturnTimeElapsed+0x70>)
8002fb2: 681a ldr r2, [r3, #0]
8002fb4: 687b ldr r3, [r7, #4]
8002fb6: 1ad3 subs r3, r2, r3
8002fb8: 607b str r3, [r7, #4]
8002fba: e00a b.n 8002fd2 <ReturnTimeElapsed+0x42>
}
else
{
wrap_counter = SynchPrescalerUserConfig - return_value;
8002fbc: 4b11 ldr r3, [pc, #68] @ (8003004 <ReturnTimeElapsed+0x74>)
8002fbe: 881b ldrh r3, [r3, #0]
8002fc0: 461a mov r2, r3
8002fc2: 687b ldr r3, [r7, #4]
8002fc4: 1ad3 subs r3, r2, r3
8002fc6: 603b str r3, [r7, #0]
return_value = SSRValueOnLastSetup + wrap_counter;
8002fc8: 4b0d ldr r3, [pc, #52] @ (8003000 <ReturnTimeElapsed+0x70>)
8002fca: 681b ldr r3, [r3, #0]
8002fcc: 683a ldr r2, [r7, #0]
8002fce: 4413 add r3, r2
8002fd0: 607b str r3, [r7, #4]
/**
* At this stage, ReturnValue holds the number of ticks counted by SSR
* Need to translate in number of ticks counted by the Wakeuptimer
*/
return_value = return_value*AsynchPrescalerUserConfig;
8002fd2: 4b0d ldr r3, [pc, #52] @ (8003008 <ReturnTimeElapsed+0x78>)
8002fd4: 781b ldrb r3, [r3, #0]
8002fd6: 461a mov r2, r3
8002fd8: 687b ldr r3, [r7, #4]
8002fda: fb02 f303 mul.w r3, r2, r3
8002fde: 607b str r3, [r7, #4]
return_value = return_value >> WakeupTimerDivider;
8002fe0: 4b0a ldr r3, [pc, #40] @ (800300c <ReturnTimeElapsed+0x7c>)
8002fe2: 781b ldrb r3, [r3, #0]
8002fe4: 461a mov r2, r3
8002fe6: 687b ldr r3, [r7, #4]
8002fe8: 40d3 lsrs r3, r2
8002fea: 607b str r3, [r7, #4]
8002fec: e001 b.n 8002ff2 <ReturnTimeElapsed+0x62>
}
else
{
return_value = 0;
8002fee: 2300 movs r3, #0
8002ff0: 607b str r3, [r7, #4]
}
return (uint16_t)return_value;
8002ff2: 687b ldr r3, [r7, #4]
8002ff4: b29b uxth r3, r3
}
8002ff6: 4618 mov r0, r3
8002ff8: 3708 adds r7, #8
8002ffa: 46bd mov sp, r7
8002ffc: bd80 pop {r7, pc}
8002ffe: bf00 nop
8003000: 200003a8 .word 0x200003a8
8003004: 200003b0 .word 0x200003b0
8003008: 200003ae .word 0x200003ae
800300c: 200003ad .word 0x200003ad
08003010 <RestartWakeupCounter>:
* It assumes all condition are met to be allowed to write the wakeup counter
* @param Value: Value to be written in the counter
* @retval None
*/
static void RestartWakeupCounter(uint16_t Value)
{
8003010: b580 push {r7, lr}
8003012: b082 sub sp, #8
8003014: af00 add r7, sp, #0
8003016: 4603 mov r3, r0
8003018: 80fb strh r3, [r7, #6]
* The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF
* FLAG when the new value will have to be written
* __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc);
*/
if(Value == 0)
800301a: 88fb ldrh r3, [r7, #6]
800301c: 2b00 cmp r3, #0
800301e: d108 bne.n 8003032 <RestartWakeupCounter+0x22>
{
SSRValueOnLastSetup = ReadRtcSsrValue();
8003020: f7ff fdc2 bl 8002ba8 <ReadRtcSsrValue>
8003024: 4603 mov r3, r0
8003026: 4a21 ldr r2, [pc, #132] @ (80030ac <RestartWakeupCounter+0x9c>)
8003028: 6013 str r3, [r2, #0]
/**
* Simulate that the Timer expired
*/
HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
800302a: 2003 movs r0, #3
800302c: f002 fb00 bl 8005630 <HAL_NVIC_SetPendingIRQ>
__HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */
HW_TS_RTC_CountUpdated_AppNot();
}
return ;
8003030: e039 b.n 80030a6 <RestartWakeupCounter+0x96>
if((Value > 1) ||(WakeupTimerDivider != 1))
8003032: 88fb ldrh r3, [r7, #6]
8003034: 2b01 cmp r3, #1
8003036: d803 bhi.n 8003040 <RestartWakeupCounter+0x30>
8003038: 4b1d ldr r3, [pc, #116] @ (80030b0 <RestartWakeupCounter+0xa0>)
800303a: 781b ldrb r3, [r3, #0]
800303c: 2b01 cmp r3, #1
800303e: d002 beq.n 8003046 <RestartWakeupCounter+0x36>
Value -= 1;
8003040: 88fb ldrh r3, [r7, #6]
8003042: 3b01 subs r3, #1
8003044: 80fb strh r3, [r7, #6]
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
8003046: bf00 nop
8003048: 4b1a ldr r3, [pc, #104] @ (80030b4 <RestartWakeupCounter+0xa4>)
800304a: 681b ldr r3, [r3, #0]
800304c: 68db ldr r3, [r3, #12]
800304e: f003 0304 and.w r3, r3, #4
8003052: 2b00 cmp r3, #0
8003054: d0f8 beq.n 8003048 <RestartWakeupCounter+0x38>
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
8003056: 4b17 ldr r3, [pc, #92] @ (80030b4 <RestartWakeupCounter+0xa4>)
8003058: 681b ldr r3, [r3, #0]
800305a: 68db ldr r3, [r3, #12]
800305c: b2da uxtb r2, r3
800305e: 4b15 ldr r3, [pc, #84] @ (80030b4 <RestartWakeupCounter+0xa4>)
8003060: 681b ldr r3, [r3, #0]
8003062: f462 6290 orn r2, r2, #1152 @ 0x480
8003066: 60da str r2, [r3, #12]
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
8003068: 4b13 ldr r3, [pc, #76] @ (80030b8 <RestartWakeupCounter+0xa8>)
800306a: f44f 2200 mov.w r2, #524288 @ 0x80000
800306e: 60da str r2, [r3, #12]
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
8003070: 2003 movs r0, #3
8003072: f002 faeb bl 800564c <HAL_NVIC_ClearPendingIRQ>
MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value);
8003076: 4b11 ldr r3, [pc, #68] @ (80030bc <RestartWakeupCounter+0xac>)
8003078: 695b ldr r3, [r3, #20]
800307a: 0c1b lsrs r3, r3, #16
800307c: 041b lsls r3, r3, #16
800307e: 88fa ldrh r2, [r7, #6]
8003080: 490e ldr r1, [pc, #56] @ (80030bc <RestartWakeupCounter+0xac>)
8003082: 4313 orrs r3, r2
8003084: 614b str r3, [r1, #20]
SSRValueOnLastSetup = ReadRtcSsrValue();
8003086: f7ff fd8f bl 8002ba8 <ReadRtcSsrValue>
800308a: 4603 mov r3, r0
800308c: 4a07 ldr r2, [pc, #28] @ (80030ac <RestartWakeupCounter+0x9c>)
800308e: 6013 str r3, [r2, #0]
__HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */
8003090: 4b08 ldr r3, [pc, #32] @ (80030b4 <RestartWakeupCounter+0xa4>)
8003092: 681b ldr r3, [r3, #0]
8003094: 689a ldr r2, [r3, #8]
8003096: 4b07 ldr r3, [pc, #28] @ (80030b4 <RestartWakeupCounter+0xa4>)
8003098: 681b ldr r3, [r3, #0]
800309a: f442 6280 orr.w r2, r2, #1024 @ 0x400
800309e: 609a str r2, [r3, #8]
HW_TS_RTC_CountUpdated_AppNot();
80030a0: f3af 8000 nop.w
return ;
80030a4: bf00 nop
}
80030a6: 3708 adds r7, #8
80030a8: 46bd mov sp, r7
80030aa: bd80 pop {r7, pc}
80030ac: 200003a8 .word 0x200003a8
80030b0: 200003ad .word 0x200003ad
80030b4: 20000504 .word 0x20000504
80030b8: 58000800 .word 0x58000800
80030bc: 40002800 .word 0x40002800
080030c0 <RescheduleTimerList>:
* 2) Setup the wakeuptimer
* @param None
* @retval None
*/
static void RescheduleTimerList(void)
{
80030c0: b580 push {r7, lr}
80030c2: b084 sub sp, #16
80030c4: af00 add r7, sp, #0
/**
* The wakeuptimer is disabled now to reduce the time to poll the WUTWF
* FLAG when the new value will have to be written
*/
if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
80030c6: 4b45 ldr r3, [pc, #276] @ (80031dc <RescheduleTimerList+0x11c>)
80030c8: 689b ldr r3, [r3, #8]
80030ca: f403 6380 and.w r3, r3, #1024 @ 0x400
80030ce: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80030d2: d107 bne.n 80030e4 <RescheduleTimerList+0x24>
{
/**
* Wait for the flag to be back to 0 when the wakeup timer is enabled
*/
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET);
80030d4: bf00 nop
80030d6: 4b42 ldr r3, [pc, #264] @ (80031e0 <RescheduleTimerList+0x120>)
80030d8: 681b ldr r3, [r3, #0]
80030da: 68db ldr r3, [r3, #12]
80030dc: f003 0304 and.w r3, r3, #4
80030e0: 2b00 cmp r3, #0
80030e2: d1f8 bne.n 80030d6 <RescheduleTimerList+0x16>
}
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
80030e4: 4b3e ldr r3, [pc, #248] @ (80031e0 <RescheduleTimerList+0x120>)
80030e6: 681b ldr r3, [r3, #0]
80030e8: 689a ldr r2, [r3, #8]
80030ea: 4b3d ldr r3, [pc, #244] @ (80031e0 <RescheduleTimerList+0x120>)
80030ec: 681b ldr r3, [r3, #0]
80030ee: f422 6280 bic.w r2, r2, #1024 @ 0x400
80030f2: 609a str r2, [r3, #8]
localTimerID = CurrentRunningTimerID;
80030f4: 4b3b ldr r3, [pc, #236] @ (80031e4 <RescheduleTimerList+0x124>)
80030f6: 781b ldrb r3, [r3, #0]
80030f8: 73fb strb r3, [r7, #15]
/**
* Calculate what will be the value to write in the wakeuptimer
*/
timecountleft = aTimerContext[localTimerID].CountLeft;
80030fa: 7bfa ldrb r2, [r7, #15]
80030fc: 493a ldr r1, [pc, #232] @ (80031e8 <RescheduleTimerList+0x128>)
80030fe: 4613 mov r3, r2
8003100: 005b lsls r3, r3, #1
8003102: 4413 add r3, r2
8003104: 00db lsls r3, r3, #3
8003106: 440b add r3, r1
8003108: 3308 adds r3, #8
800310a: 681b ldr r3, [r3, #0]
800310c: 60bb str r3, [r7, #8]
/**
* Read how much has been counted
*/
time_elapsed = ReturnTimeElapsed();
800310e: f7ff ff3f bl 8002f90 <ReturnTimeElapsed>
8003112: 4603 mov r3, r0
8003114: 80fb strh r3, [r7, #6]
if(timecountleft < time_elapsed )
8003116: 88fb ldrh r3, [r7, #6]
8003118: 68ba ldr r2, [r7, #8]
800311a: 429a cmp r2, r3
800311c: d205 bcs.n 800312a <RescheduleTimerList+0x6a>
{
/**
* There is no tick left to count
*/
wakeup_timer_value = 0;
800311e: 2300 movs r3, #0
8003120: 81bb strh r3, [r7, #12]
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
8003122: 4b32 ldr r3, [pc, #200] @ (80031ec <RescheduleTimerList+0x12c>)
8003124: 2201 movs r2, #1
8003126: 701a strb r2, [r3, #0]
8003128: e04d b.n 80031c6 <RescheduleTimerList+0x106>
}
else
{
if(timecountleft > (time_elapsed + MaxWakeupTimerSetup))
800312a: 88fb ldrh r3, [r7, #6]
800312c: 4a30 ldr r2, [pc, #192] @ (80031f0 <RescheduleTimerList+0x130>)
800312e: 8812 ldrh r2, [r2, #0]
8003130: b292 uxth r2, r2
8003132: 4413 add r3, r2
8003134: 461a mov r2, r3
8003136: 68bb ldr r3, [r7, #8]
8003138: 4293 cmp r3, r2
800313a: d906 bls.n 800314a <RescheduleTimerList+0x8a>
{
/**
* The number of tick left is greater than the Wakeuptimer maximum value
*/
wakeup_timer_value = MaxWakeupTimerSetup;
800313c: 4b2c ldr r3, [pc, #176] @ (80031f0 <RescheduleTimerList+0x130>)
800313e: 881b ldrh r3, [r3, #0]
8003140: 81bb strh r3, [r7, #12]
WakeupTimerLimitation = WakeupTimerValue_Overpassed;
8003142: 4b2a ldr r3, [pc, #168] @ (80031ec <RescheduleTimerList+0x12c>)
8003144: 2200 movs r2, #0
8003146: 701a strb r2, [r3, #0]
8003148: e03d b.n 80031c6 <RescheduleTimerList+0x106>
}
else
{
wakeup_timer_value = timecountleft - time_elapsed;
800314a: 68bb ldr r3, [r7, #8]
800314c: b29a uxth r2, r3
800314e: 88fb ldrh r3, [r7, #6]
8003150: 1ad3 subs r3, r2, r3
8003152: 81bb strh r3, [r7, #12]
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
8003154: 4b25 ldr r3, [pc, #148] @ (80031ec <RescheduleTimerList+0x12c>)
8003156: 2201 movs r2, #1
8003158: 701a strb r2, [r3, #0]
}
/**
* update ticks left to be counted for each timer
*/
while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
800315a: e034 b.n 80031c6 <RescheduleTimerList+0x106>
{
if (aTimerContext[localTimerID].CountLeft < time_elapsed)
800315c: 7bfa ldrb r2, [r7, #15]
800315e: 4922 ldr r1, [pc, #136] @ (80031e8 <RescheduleTimerList+0x128>)
8003160: 4613 mov r3, r2
8003162: 005b lsls r3, r3, #1
8003164: 4413 add r3, r2
8003166: 00db lsls r3, r3, #3
8003168: 440b add r3, r1
800316a: 3308 adds r3, #8
800316c: 681a ldr r2, [r3, #0]
800316e: 88fb ldrh r3, [r7, #6]
8003170: 429a cmp r2, r3
8003172: d20a bcs.n 800318a <RescheduleTimerList+0xca>
{
aTimerContext[localTimerID].CountLeft = 0;
8003174: 7bfa ldrb r2, [r7, #15]
8003176: 491c ldr r1, [pc, #112] @ (80031e8 <RescheduleTimerList+0x128>)
8003178: 4613 mov r3, r2
800317a: 005b lsls r3, r3, #1
800317c: 4413 add r3, r2
800317e: 00db lsls r3, r3, #3
8003180: 440b add r3, r1
8003182: 3308 adds r3, #8
8003184: 2200 movs r2, #0
8003186: 601a str r2, [r3, #0]
8003188: e013 b.n 80031b2 <RescheduleTimerList+0xf2>
}
else
{
aTimerContext[localTimerID].CountLeft -= time_elapsed;
800318a: 7bfa ldrb r2, [r7, #15]
800318c: 4916 ldr r1, [pc, #88] @ (80031e8 <RescheduleTimerList+0x128>)
800318e: 4613 mov r3, r2
8003190: 005b lsls r3, r3, #1
8003192: 4413 add r3, r2
8003194: 00db lsls r3, r3, #3
8003196: 440b add r3, r1
8003198: 3308 adds r3, #8
800319a: 6819 ldr r1, [r3, #0]
800319c: 88fb ldrh r3, [r7, #6]
800319e: 7bfa ldrb r2, [r7, #15]
80031a0: 1ac9 subs r1, r1, r3
80031a2: 4811 ldr r0, [pc, #68] @ (80031e8 <RescheduleTimerList+0x128>)
80031a4: 4613 mov r3, r2
80031a6: 005b lsls r3, r3, #1
80031a8: 4413 add r3, r2
80031aa: 00db lsls r3, r3, #3
80031ac: 4403 add r3, r0
80031ae: 3308 adds r3, #8
80031b0: 6019 str r1, [r3, #0]
}
localTimerID = aTimerContext[localTimerID].NextID;
80031b2: 7bfa ldrb r2, [r7, #15]
80031b4: 490c ldr r1, [pc, #48] @ (80031e8 <RescheduleTimerList+0x128>)
80031b6: 4613 mov r3, r2
80031b8: 005b lsls r3, r3, #1
80031ba: 4413 add r3, r2
80031bc: 00db lsls r3, r3, #3
80031be: 440b add r3, r1
80031c0: 3315 adds r3, #21
80031c2: 781b ldrb r3, [r3, #0]
80031c4: 73fb strb r3, [r7, #15]
while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
80031c6: 7bfb ldrb r3, [r7, #15]
80031c8: 2b06 cmp r3, #6
80031ca: d1c7 bne.n 800315c <RescheduleTimerList+0x9c>
}
/**
* Write next count
*/
RestartWakeupCounter(wakeup_timer_value);
80031cc: 89bb ldrh r3, [r7, #12]
80031ce: 4618 mov r0, r3
80031d0: f7ff ff1e bl 8003010 <RestartWakeupCounter>
return ;
80031d4: bf00 nop
}
80031d6: 3710 adds r7, #16
80031d8: 46bd mov sp, r7
80031da: bd80 pop {r7, pc}
80031dc: 40002800 .word 0x40002800
80031e0: 20000504 .word 0x20000504
80031e4: 200003a4 .word 0x200003a4
80031e8: 20000314 .word 0x20000314
80031ec: 200003ac .word 0x200003ac
80031f0: 200003b2 .word 0x200003b2
080031f4 <HW_TS_RTC_Wakeup_Handler>:
* In order to ease maintainability, the unlock is done at the top and the lock at then end
* in case some new implementation is coming in the future
*/
void HW_TS_RTC_Wakeup_Handler(void)
{
80031f4: b580 push {r7, lr}
80031f6: b08a sub sp, #40 @ 0x28
80031f8: af00 add r7, sp, #0
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80031fa: f3ef 8310 mrs r3, PRIMASK
80031fe: 617b str r3, [r7, #20]
return(result);
8003200: 697b ldr r3, [r7, #20]
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
uint32_t primask_bit;
#endif
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
8003202: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("cpsid i" : : : "memory");
8003204: b672 cpsid i
}
8003206: bf00 nop
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
#endif
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
8003208: 4b59 ldr r3, [pc, #356] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
800320a: 681b ldr r3, [r3, #0]
800320c: 22ca movs r2, #202 @ 0xca
800320e: 625a str r2, [r3, #36] @ 0x24
8003210: 4b57 ldr r3, [pc, #348] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
8003212: 681b ldr r3, [r3, #0]
8003214: 2253 movs r2, #83 @ 0x53
8003216: 625a str r2, [r3, #36] @ 0x24
/**
* Disable the Wakeup Timer
* This may speed up a bit the processing to wait the timer to be disabled
* The timer is still counting 2 RTCCLK
*/
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc);
8003218: 4b55 ldr r3, [pc, #340] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
800321a: 681b ldr r3, [r3, #0]
800321c: 689a ldr r2, [r3, #8]
800321e: 4b54 ldr r3, [pc, #336] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
8003220: 681b ldr r3, [r3, #0]
8003222: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003226: 609a str r2, [r3, #8]
local_current_running_timer_id = CurrentRunningTimerID;
8003228: 4b52 ldr r3, [pc, #328] @ (8003374 <HW_TS_RTC_Wakeup_Handler+0x180>)
800322a: 781b ldrb r3, [r3, #0]
800322c: f887 3023 strb.w r3, [r7, #35] @ 0x23
if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running)
8003230: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
8003234: 4950 ldr r1, [pc, #320] @ (8003378 <HW_TS_RTC_Wakeup_Handler+0x184>)
8003236: 4613 mov r3, r2
8003238: 005b lsls r3, r3, #1
800323a: 4413 add r3, r2
800323c: 00db lsls r3, r3, #3
800323e: 440b add r3, r1
8003240: 330c adds r3, #12
8003242: 781b ldrb r3, [r3, #0]
8003244: b2db uxtb r3, r3
8003246: 2b02 cmp r3, #2
8003248: d16e bne.n 8003328 <HW_TS_RTC_Wakeup_Handler+0x134>
{
ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack;
800324a: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
800324e: 494a ldr r1, [pc, #296] @ (8003378 <HW_TS_RTC_Wakeup_Handler+0x184>)
8003250: 4613 mov r3, r2
8003252: 005b lsls r3, r3, #1
8003254: 4413 add r3, r2
8003256: 00db lsls r3, r3, #3
8003258: 440b add r3, r1
800325a: 681b ldr r3, [r3, #0]
800325c: 61fb str r3, [r7, #28]
timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID;
800325e: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
8003262: 4945 ldr r1, [pc, #276] @ (8003378 <HW_TS_RTC_Wakeup_Handler+0x184>)
8003264: 4613 mov r3, r2
8003266: 005b lsls r3, r3, #1
8003268: 4413 add r3, r2
800326a: 00db lsls r3, r3, #3
800326c: 440b add r3, r1
800326e: 3310 adds r3, #16
8003270: 681b ldr r3, [r3, #0]
8003272: 61bb str r3, [r7, #24]
* However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick
* to be left whereas the count is over
* A more secure implementation has been done with a flag to state whereas the full count has been written
* in the wakeuptimer or not
*/
if(WakeupTimerLimitation != WakeupTimerValue_Overpassed)
8003274: 4b41 ldr r3, [pc, #260] @ (800337c <HW_TS_RTC_Wakeup_Handler+0x188>)
8003276: 781b ldrb r3, [r3, #0]
8003278: b2db uxtb r3, r3
800327a: 2b00 cmp r3, #0
800327c: d04c beq.n 8003318 <HW_TS_RTC_Wakeup_Handler+0x124>
{
if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated)
800327e: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
8003282: 493d ldr r1, [pc, #244] @ (8003378 <HW_TS_RTC_Wakeup_Handler+0x184>)
8003284: 4613 mov r3, r2
8003286: 005b lsls r3, r3, #1
8003288: 4413 add r3, r2
800328a: 00db lsls r3, r3, #3
800328c: 440b add r3, r1
800328e: 330d adds r3, #13
8003290: 781b ldrb r3, [r3, #0]
8003292: b2db uxtb r3, r3
8003294: 2b01 cmp r3, #1
8003296: d124 bne.n 80032e2 <HW_TS_RTC_Wakeup_Handler+0xee>
{
UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested);
8003298: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
800329c: 2101 movs r1, #1
800329e: 4618 mov r0, r3
80032a0: f7ff fdf2 bl 8002e88 <UnlinkTimer>
80032a4: 6a7b ldr r3, [r7, #36] @ 0x24
80032a6: 613b str r3, [r7, #16]
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80032a8: 693b ldr r3, [r7, #16]
80032aa: f383 8810 msr PRIMASK, r3
}
80032ae: bf00 nop
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
#endif
HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit);
80032b0: f897 2023 ldrb.w r2, [r7, #35] @ 0x23
80032b4: 4930 ldr r1, [pc, #192] @ (8003378 <HW_TS_RTC_Wakeup_Handler+0x184>)
80032b6: 4613 mov r3, r2
80032b8: 005b lsls r3, r3, #1
80032ba: 4413 add r3, r2
80032bc: 00db lsls r3, r3, #3
80032be: 440b add r3, r1
80032c0: 3304 adds r3, #4
80032c2: 681a ldr r2, [r3, #0]
80032c4: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
80032c8: 4611 mov r1, r2
80032ca: 4618 mov r0, r3
80032cc: f000 f9b8 bl 8003640 <HW_TS_Start>
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
80032d0: 4b27 ldr r3, [pc, #156] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
80032d2: 681b ldr r3, [r3, #0]
80032d4: 22ca movs r2, #202 @ 0xca
80032d6: 625a str r2, [r3, #36] @ 0x24
80032d8: 4b25 ldr r3, [pc, #148] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
80032da: 681b ldr r3, [r3, #0]
80032dc: 2253 movs r2, #83 @ 0x53
80032de: 625a str r2, [r3, #36] @ 0x24
80032e0: e012 b.n 8003308 <HW_TS_RTC_Wakeup_Handler+0x114>
80032e2: 6a7b ldr r3, [r7, #36] @ 0x24
80032e4: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80032e6: 68fb ldr r3, [r7, #12]
80032e8: f383 8810 msr PRIMASK, r3
}
80032ec: bf00 nop
else
{
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
#endif
HW_TS_Stop(local_current_running_timer_id);
80032ee: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
80032f2: 4618 mov r0, r3
80032f4: f000 f920 bl 8003538 <HW_TS_Stop>
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
80032f8: 4b1d ldr r3, [pc, #116] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
80032fa: 681b ldr r3, [r3, #0]
80032fc: 22ca movs r2, #202 @ 0xca
80032fe: 625a str r2, [r3, #36] @ 0x24
8003300: 4b1b ldr r3, [pc, #108] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
8003302: 681b ldr r3, [r3, #0]
8003304: 2253 movs r2, #83 @ 0x53
8003306: 625a str r2, [r3, #36] @ 0x24
}
HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback);
8003308: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
800330c: 69fa ldr r2, [r7, #28]
800330e: 4619 mov r1, r3
8003310: 69b8 ldr r0, [r7, #24]
8003312: f000 fa1b bl 800374c <HW_TS_RTC_Int_AppNot>
8003316: e022 b.n 800335e <HW_TS_RTC_Wakeup_Handler+0x16a>
}
else
{
RescheduleTimerList();
8003318: f7ff fed2 bl 80030c0 <RescheduleTimerList>
800331c: 6a7b ldr r3, [r7, #36] @ 0x24
800331e: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8003320: 68bb ldr r3, [r7, #8]
8003322: f383 8810 msr PRIMASK, r3
}
8003326: e01a b.n 800335e <HW_TS_RTC_Wakeup_Handler+0x16a>
/**
* We should never end up in this case
* However, if due to any bug in the timer server this is the case, the mistake may not impact the user.
* We could just clean the interrupt flag and get out from this unexpected interrupt
*/
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
8003328: bf00 nop
800332a: 4b11 ldr r3, [pc, #68] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
800332c: 681b ldr r3, [r3, #0]
800332e: 68db ldr r3, [r3, #12]
8003330: f003 0304 and.w r3, r3, #4
8003334: 2b00 cmp r3, #0
8003336: d0f8 beq.n 800332a <HW_TS_RTC_Wakeup_Handler+0x136>
* It takes 2 RTCCLK between the time the WUTE bit is disabled and the
* time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
* Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
* due to the autoreload feature
*/
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
8003338: 4b0d ldr r3, [pc, #52] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
800333a: 681b ldr r3, [r3, #0]
800333c: 68db ldr r3, [r3, #12]
800333e: b2da uxtb r2, r3
8003340: 4b0b ldr r3, [pc, #44] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
8003342: 681b ldr r3, [r3, #0]
8003344: f462 6290 orn r2, r2, #1152 @ 0x480
8003348: 60da str r2, [r3, #12]
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
800334a: 4b0d ldr r3, [pc, #52] @ (8003380 <HW_TS_RTC_Wakeup_Handler+0x18c>)
800334c: f44f 2200 mov.w r2, #524288 @ 0x80000
8003350: 60da str r2, [r3, #12]
8003352: 6a7b ldr r3, [r7, #36] @ 0x24
8003354: 607b str r3, [r7, #4]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8003356: 687b ldr r3, [r7, #4]
8003358: f383 8810 msr PRIMASK, r3
}
800335c: bf00 nop
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
#endif
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
800335e: 4b04 ldr r3, [pc, #16] @ (8003370 <HW_TS_RTC_Wakeup_Handler+0x17c>)
8003360: 681b ldr r3, [r3, #0]
8003362: 22ff movs r2, #255 @ 0xff
8003364: 625a str r2, [r3, #36] @ 0x24
return;
8003366: bf00 nop
}
8003368: 3728 adds r7, #40 @ 0x28
800336a: 46bd mov sp, r7
800336c: bd80 pop {r7, pc}
800336e: bf00 nop
8003370: 20000504 .word 0x20000504
8003374: 200003a4 .word 0x200003a4
8003378: 20000314 .word 0x20000314
800337c: 200003ac .word 0x200003ac
8003380: 58000800 .word 0x58000800
08003384 <HW_TS_Init>:
void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *phrtc)
{
8003384: b580 push {r7, lr}
8003386: b088 sub sp, #32
8003388: af00 add r7, sp, #0
800338a: 4603 mov r3, r0
800338c: 6039 str r1, [r7, #0]
800338e: 71fb strb r3, [r7, #7]
uint8_t loop;
uint32_t localmaxwakeuptimersetup;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
8003390: 4b5e ldr r3, [pc, #376] @ (800350c <HW_TS_Init+0x188>)
8003392: 681b ldr r3, [r3, #0]
8003394: 22ca movs r2, #202 @ 0xca
8003396: 625a str r2, [r3, #36] @ 0x24
8003398: 4b5c ldr r3, [pc, #368] @ (800350c <HW_TS_Init+0x188>)
800339a: 681b ldr r3, [r3, #0]
800339c: 2253 movs r2, #83 @ 0x53
800339e: 625a str r2, [r3, #36] @ 0x24
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
80033a0: 4b5b ldr r3, [pc, #364] @ (8003510 <HW_TS_Init+0x18c>)
80033a2: 689b ldr r3, [r3, #8]
80033a4: 4a5a ldr r2, [pc, #360] @ (8003510 <HW_TS_Init+0x18c>)
80033a6: f043 0320 orr.w r3, r3, #32
80033aa: 6093 str r3, [r2, #8]
/**
* Readout the user config
*/
WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL))));
80033ac: 4b58 ldr r3, [pc, #352] @ (8003510 <HW_TS_Init+0x18c>)
80033ae: 689b ldr r3, [r3, #8]
80033b0: b2db uxtb r3, r3
80033b2: f003 0307 and.w r3, r3, #7
80033b6: b2db uxtb r3, r3
80033b8: f1c3 0304 rsb r3, r3, #4
80033bc: b2da uxtb r2, r3
80033be: 4b55 ldr r3, [pc, #340] @ (8003514 <HW_TS_Init+0x190>)
80033c0: 701a strb r2, [r3, #0]
AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1;
80033c2: 4b53 ldr r3, [pc, #332] @ (8003510 <HW_TS_Init+0x18c>)
80033c4: 691b ldr r3, [r3, #16]
80033c6: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000
80033ca: f44f 02fe mov.w r2, #8323072 @ 0x7f0000
80033ce: 613a str r2, [r7, #16]
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80033d0: 693a ldr r2, [r7, #16]
80033d2: fa92 f2a2 rbit r2, r2
80033d6: 60fa str r2, [r7, #12]
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
80033d8: 68fa ldr r2, [r7, #12]
80033da: 617a str r2, [r7, #20]
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
80033dc: 697a ldr r2, [r7, #20]
80033de: 2a00 cmp r2, #0
80033e0: d101 bne.n 80033e6 <HW_TS_Init+0x62>
{
return 32U;
80033e2: 2220 movs r2, #32
80033e4: e003 b.n 80033ee <HW_TS_Init+0x6a>
}
return __builtin_clz(value);
80033e6: 697a ldr r2, [r7, #20]
80033e8: fab2 f282 clz r2, r2
80033ec: b2d2 uxtb r2, r2
80033ee: 40d3 lsrs r3, r2
80033f0: b2db uxtb r3, r3
80033f2: 3301 adds r3, #1
80033f4: b2da uxtb r2, r3
80033f6: 4b48 ldr r3, [pc, #288] @ (8003518 <HW_TS_Init+0x194>)
80033f8: 701a strb r2, [r3, #0]
SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1;
80033fa: 4b45 ldr r3, [pc, #276] @ (8003510 <HW_TS_Init+0x18c>)
80033fc: 691b ldr r3, [r3, #16]
80033fe: b29b uxth r3, r3
8003400: f3c3 030e ubfx r3, r3, #0, #15
8003404: b29b uxth r3, r3
8003406: 3301 adds r3, #1
8003408: b29a uxth r2, r3
800340a: 4b44 ldr r3, [pc, #272] @ (800351c <HW_TS_Init+0x198>)
800340c: 801a strh r2, [r3, #0]
/**
* Margin is taken to avoid wrong calculation when the wrap around is there and some
* application interrupts may have delayed the reading
*/
localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider);
800340e: 4b43 ldr r3, [pc, #268] @ (800351c <HW_TS_Init+0x198>)
8003410: 881b ldrh r3, [r3, #0]
8003412: 3b01 subs r3, #1
8003414: 4a40 ldr r2, [pc, #256] @ (8003518 <HW_TS_Init+0x194>)
8003416: 7812 ldrb r2, [r2, #0]
8003418: fb02 f303 mul.w r3, r2, r3
800341c: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
8003420: 4a3c ldr r2, [pc, #240] @ (8003514 <HW_TS_Init+0x190>)
8003422: 7812 ldrb r2, [r2, #0]
8003424: 40d3 lsrs r3, r2
8003426: 61bb str r3, [r7, #24]
if(localmaxwakeuptimersetup >= 0xFFFF)
8003428: 69bb ldr r3, [r7, #24]
800342a: f64f 72fe movw r2, #65534 @ 0xfffe
800342e: 4293 cmp r3, r2
8003430: d904 bls.n 800343c <HW_TS_Init+0xb8>
{
MaxWakeupTimerSetup = 0xFFFF;
8003432: 4b3b ldr r3, [pc, #236] @ (8003520 <HW_TS_Init+0x19c>)
8003434: f64f 72ff movw r2, #65535 @ 0xffff
8003438: 801a strh r2, [r3, #0]
800343a: e003 b.n 8003444 <HW_TS_Init+0xc0>
}
else
{
MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup;
800343c: 69bb ldr r3, [r7, #24]
800343e: b29a uxth r2, r3
8003440: 4b37 ldr r3, [pc, #220] @ (8003520 <HW_TS_Init+0x19c>)
8003442: 801a strh r2, [r3, #0]
}
/**
* Configure EXTI module
*/
LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
8003444: f44f 2000 mov.w r0, #524288 @ 0x80000
8003448: f7ff fb9c bl 8002b84 <LL_EXTI_EnableRisingTrig_0_31>
LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
800344c: f44f 2000 mov.w r0, #524288 @ 0x80000
8003450: f7ff fb84 bl 8002b5c <LL_EXTI_EnableIT_0_31>
if(TimerInitMode == hw_ts_InitMode_Full)
8003454: 79fb ldrb r3, [r7, #7]
8003456: 2b00 cmp r3, #0
8003458: d13d bne.n 80034d6 <HW_TS_Init+0x152>
{
WakeupTimerLimitation = WakeupTimerValue_LargeEnough;
800345a: 4b32 ldr r3, [pc, #200] @ (8003524 <HW_TS_Init+0x1a0>)
800345c: 2201 movs r2, #1
800345e: 701a strb r2, [r3, #0]
SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE;
8003460: 4b31 ldr r3, [pc, #196] @ (8003528 <HW_TS_Init+0x1a4>)
8003462: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8003466: 601a str r2, [r3, #0]
/**
* Initialize the timer server
*/
for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
8003468: 2300 movs r3, #0
800346a: 77fb strb r3, [r7, #31]
800346c: e00c b.n 8003488 <HW_TS_Init+0x104>
{
aTimerContext[loop].TimerIDStatus = TimerID_Free;
800346e: 7ffa ldrb r2, [r7, #31]
8003470: 492e ldr r1, [pc, #184] @ (800352c <HW_TS_Init+0x1a8>)
8003472: 4613 mov r3, r2
8003474: 005b lsls r3, r3, #1
8003476: 4413 add r3, r2
8003478: 00db lsls r3, r3, #3
800347a: 440b add r3, r1
800347c: 330c adds r3, #12
800347e: 2200 movs r2, #0
8003480: 701a strb r2, [r3, #0]
for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++)
8003482: 7ffb ldrb r3, [r7, #31]
8003484: 3301 adds r3, #1
8003486: 77fb strb r3, [r7, #31]
8003488: 7ffb ldrb r3, [r7, #31]
800348a: 2b05 cmp r3, #5
800348c: d9ef bls.n 800346e <HW_TS_Init+0xea>
}
CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; /**< Set ID to non valid value */
800348e: 4b28 ldr r3, [pc, #160] @ (8003530 <HW_TS_Init+0x1ac>)
8003490: 2206 movs r2, #6
8003492: 701a strb r2, [r3, #0]
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
8003494: 4b1d ldr r3, [pc, #116] @ (800350c <HW_TS_Init+0x188>)
8003496: 681b ldr r3, [r3, #0]
8003498: 689a ldr r2, [r3, #8]
800349a: 4b1c ldr r3, [pc, #112] @ (800350c <HW_TS_Init+0x188>)
800349c: 681b ldr r3, [r3, #0]
800349e: f422 6280 bic.w r2, r2, #1024 @ 0x400
80034a2: 609a str r2, [r3, #8]
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
80034a4: 4b19 ldr r3, [pc, #100] @ (800350c <HW_TS_Init+0x188>)
80034a6: 681b ldr r3, [r3, #0]
80034a8: 68db ldr r3, [r3, #12]
80034aa: b2da uxtb r2, r3
80034ac: 4b17 ldr r3, [pc, #92] @ (800350c <HW_TS_Init+0x188>)
80034ae: 681b ldr r3, [r3, #0]
80034b0: f462 6290 orn r2, r2, #1152 @ 0x480
80034b4: 60da str r2, [r3, #12]
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
80034b6: 4b1f ldr r3, [pc, #124] @ (8003534 <HW_TS_Init+0x1b0>)
80034b8: f44f 2200 mov.w r2, #524288 @ 0x80000
80034bc: 60da str r2, [r3, #12]
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
80034be: 2003 movs r0, #3
80034c0: f002 f8c4 bl 800564c <HAL_NVIC_ClearPendingIRQ>
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hrtc, RTC_IT_WUT); /**< Enable interrupt in RTC module */
80034c4: 4b11 ldr r3, [pc, #68] @ (800350c <HW_TS_Init+0x188>)
80034c6: 681b ldr r3, [r3, #0]
80034c8: 689a ldr r2, [r3, #8]
80034ca: 4b10 ldr r3, [pc, #64] @ (800350c <HW_TS_Init+0x188>)
80034cc: 681b ldr r3, [r3, #0]
80034ce: f442 4280 orr.w r2, r2, #16384 @ 0x4000
80034d2: 609a str r2, [r3, #8]
80034d4: e009 b.n 80034ea <HW_TS_Init+0x166>
}
else
{
if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTF) != RESET)
80034d6: 4b0d ldr r3, [pc, #52] @ (800350c <HW_TS_Init+0x188>)
80034d8: 681b ldr r3, [r3, #0]
80034da: 68db ldr r3, [r3, #12]
80034dc: f403 6380 and.w r3, r3, #1024 @ 0x400
80034e0: 2b00 cmp r3, #0
80034e2: d002 beq.n 80034ea <HW_TS_Init+0x166>
{
/**
* Simulate that the Timer expired
*/
HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID);
80034e4: 2003 movs r0, #3
80034e6: f002 f8a3 bl 8005630 <HAL_NVIC_SetPendingIRQ>
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
80034ea: 4b08 ldr r3, [pc, #32] @ (800350c <HW_TS_Init+0x188>)
80034ec: 681b ldr r3, [r3, #0]
80034ee: 22ff movs r2, #255 @ 0xff
80034f0: 625a str r2, [r3, #36] @ 0x24
HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO); /**< Set NVIC priority */
80034f2: 2200 movs r2, #0
80034f4: 2106 movs r1, #6
80034f6: 2003 movs r0, #3
80034f8: f002 f864 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
80034fc: 2003 movs r0, #3
80034fe: f002 f87b bl 80055f8 <HAL_NVIC_EnableIRQ>
return;
8003502: bf00 nop
}
8003504: 3720 adds r7, #32
8003506: 46bd mov sp, r7
8003508: bd80 pop {r7, pc}
800350a: bf00 nop
800350c: 20000504 .word 0x20000504
8003510: 40002800 .word 0x40002800
8003514: 200003ad .word 0x200003ad
8003518: 200003ae .word 0x200003ae
800351c: 200003b0 .word 0x200003b0
8003520: 200003b2 .word 0x200003b2
8003524: 200003ac .word 0x200003ac
8003528: 200003a8 .word 0x200003a8
800352c: 20000314 .word 0x20000314
8003530: 200003a4 .word 0x200003a4
8003534: 58000800 .word 0x58000800
08003538 <HW_TS_Stop>:
return;
}
void HW_TS_Stop(uint8_t timer_id)
{
8003538: b580 push {r7, lr}
800353a: b086 sub sp, #24
800353c: af00 add r7, sp, #0
800353e: 4603 mov r3, r0
8003540: 71fb strb r3, [r7, #7]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8003542: f3ef 8310 mrs r3, PRIMASK
8003546: 60fb str r3, [r7, #12]
return(result);
8003548: 68fb ldr r3, [r7, #12]
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
uint32_t primask_bit;
#endif
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
800354a: 617b str r3, [r7, #20]
__ASM volatile ("cpsid i" : : : "memory");
800354c: b672 cpsid i
}
800354e: bf00 nop
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
#endif
HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */
8003550: 2003 movs r0, #3
8003552: f002 f85f bl 8005614 <HAL_NVIC_DisableIRQ>
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
8003556: 4b34 ldr r3, [pc, #208] @ (8003628 <HW_TS_Stop+0xf0>)
8003558: 681b ldr r3, [r3, #0]
800355a: 22ca movs r2, #202 @ 0xca
800355c: 625a str r2, [r3, #36] @ 0x24
800355e: 4b32 ldr r3, [pc, #200] @ (8003628 <HW_TS_Stop+0xf0>)
8003560: 681b ldr r3, [r3, #0]
8003562: 2253 movs r2, #83 @ 0x53
8003564: 625a str r2, [r3, #36] @ 0x24
if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
8003566: 79fa ldrb r2, [r7, #7]
8003568: 4930 ldr r1, [pc, #192] @ (800362c <HW_TS_Stop+0xf4>)
800356a: 4613 mov r3, r2
800356c: 005b lsls r3, r3, #1
800356e: 4413 add r3, r2
8003570: 00db lsls r3, r3, #3
8003572: 440b add r3, r1
8003574: 330c adds r3, #12
8003576: 781b ldrb r3, [r3, #0]
8003578: b2db uxtb r3, r3
800357a: 2b02 cmp r3, #2
800357c: d142 bne.n 8003604 <HW_TS_Stop+0xcc>
{
UnlinkTimer(timer_id, SSR_Read_Requested);
800357e: 79fb ldrb r3, [r7, #7]
8003580: 2100 movs r1, #0
8003582: 4618 mov r0, r3
8003584: f7ff fc80 bl 8002e88 <UnlinkTimer>
localcurrentrunningtimerid = CurrentRunningTimerID;
8003588: 4b29 ldr r3, [pc, #164] @ (8003630 <HW_TS_Stop+0xf8>)
800358a: 781b ldrb r3, [r3, #0]
800358c: 74fb strb r3, [r7, #19]
if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER)
800358e: 7cfb ldrb r3, [r7, #19]
8003590: 2b06 cmp r3, #6
8003592: d12f bne.n 80035f4 <HW_TS_Stop+0xbc>
*/
/**
* Disable the timer
*/
if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET)
8003594: 4b27 ldr r3, [pc, #156] @ (8003634 <HW_TS_Stop+0xfc>)
8003596: 689b ldr r3, [r3, #8]
8003598: f403 6380 and.w r3, r3, #1024 @ 0x400
800359c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80035a0: d107 bne.n 80035b2 <HW_TS_Stop+0x7a>
{
/**
* Wait for the flag to be back to 0 when the wakeup timer is enabled
*/
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET);
80035a2: bf00 nop
80035a4: 4b20 ldr r3, [pc, #128] @ (8003628 <HW_TS_Stop+0xf0>)
80035a6: 681b ldr r3, [r3, #0]
80035a8: 68db ldr r3, [r3, #12]
80035aa: f003 0304 and.w r3, r3, #4
80035ae: 2b00 cmp r3, #0
80035b0: d1f8 bne.n 80035a4 <HW_TS_Stop+0x6c>
}
__HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */
80035b2: 4b1d ldr r3, [pc, #116] @ (8003628 <HW_TS_Stop+0xf0>)
80035b4: 681b ldr r3, [r3, #0]
80035b6: 689a ldr r2, [r3, #8]
80035b8: 4b1b ldr r3, [pc, #108] @ (8003628 <HW_TS_Stop+0xf0>)
80035ba: 681b ldr r3, [r3, #0]
80035bc: f422 6280 bic.w r2, r2, #1024 @ 0x400
80035c0: 609a str r2, [r3, #8]
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET);
80035c2: bf00 nop
80035c4: 4b18 ldr r3, [pc, #96] @ (8003628 <HW_TS_Stop+0xf0>)
80035c6: 681b ldr r3, [r3, #0]
80035c8: 68db ldr r3, [r3, #12]
80035ca: f003 0304 and.w r3, r3, #4
80035ce: 2b00 cmp r3, #0
80035d0: d0f8 beq.n 80035c4 <HW_TS_Stop+0x8c>
* It takes 2 RTCCLK between the time the WUTE bit is disabled and the
* time the timer is disabled. The WUTWF bit somehow guarantee the system is stable
* Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between
* due to the autoreload feature
*/
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */
80035d2: 4b15 ldr r3, [pc, #84] @ (8003628 <HW_TS_Stop+0xf0>)
80035d4: 681b ldr r3, [r3, #0]
80035d6: 68db ldr r3, [r3, #12]
80035d8: b2da uxtb r2, r3
80035da: 4b13 ldr r3, [pc, #76] @ (8003628 <HW_TS_Stop+0xf0>)
80035dc: 681b ldr r3, [r3, #0]
80035de: f462 6290 orn r2, r2, #1152 @ 0x480
80035e2: 60da str r2, [r3, #12]
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */
80035e4: 4b14 ldr r3, [pc, #80] @ (8003638 <HW_TS_Stop+0x100>)
80035e6: f44f 2200 mov.w r2, #524288 @ 0x80000
80035ea: 60da str r2, [r3, #12]
HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */
80035ec: 2003 movs r0, #3
80035ee: f002 f82d bl 800564c <HAL_NVIC_ClearPendingIRQ>
80035f2: e007 b.n 8003604 <HW_TS_Stop+0xcc>
}
else if(PreviousRunningTimerID != localcurrentrunningtimerid)
80035f4: 4b11 ldr r3, [pc, #68] @ (800363c <HW_TS_Stop+0x104>)
80035f6: 781b ldrb r3, [r3, #0]
80035f8: b2db uxtb r3, r3
80035fa: 7cfa ldrb r2, [r7, #19]
80035fc: 429a cmp r2, r3
80035fe: d001 beq.n 8003604 <HW_TS_Stop+0xcc>
{
RescheduleTimerList();
8003600: f7ff fd5e bl 80030c0 <RescheduleTimerList>
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
8003604: 4b08 ldr r3, [pc, #32] @ (8003628 <HW_TS_Stop+0xf0>)
8003606: 681b ldr r3, [r3, #0]
8003608: 22ff movs r2, #255 @ 0xff
800360a: 625a str r2, [r3, #36] @ 0x24
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
800360c: 2003 movs r0, #3
800360e: f001 fff3 bl 80055f8 <HAL_NVIC_EnableIRQ>
8003612: 697b ldr r3, [r7, #20]
8003614: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8003616: 68bb ldr r3, [r7, #8]
8003618: f383 8810 msr PRIMASK, r3
}
800361c: bf00 nop
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
#endif
return;
800361e: bf00 nop
}
8003620: 3718 adds r7, #24
8003622: 46bd mov sp, r7
8003624: bd80 pop {r7, pc}
8003626: bf00 nop
8003628: 20000504 .word 0x20000504
800362c: 20000314 .word 0x20000314
8003630: 200003a4 .word 0x200003a4
8003634: 40002800 .word 0x40002800
8003638: 58000800 .word 0x58000800
800363c: 200003a5 .word 0x200003a5
08003640 <HW_TS_Start>:
void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks)
{
8003640: b580 push {r7, lr}
8003642: b086 sub sp, #24
8003644: af00 add r7, sp, #0
8003646: 4603 mov r3, r0
8003648: 6039 str r1, [r7, #0]
800364a: 71fb strb r3, [r7, #7]
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
uint32_t primask_bit;
#endif
if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running)
800364c: 79fa ldrb r2, [r7, #7]
800364e: 493b ldr r1, [pc, #236] @ (800373c <HW_TS_Start+0xfc>)
8003650: 4613 mov r3, r2
8003652: 005b lsls r3, r3, #1
8003654: 4413 add r3, r2
8003656: 00db lsls r3, r3, #3
8003658: 440b add r3, r1
800365a: 330c adds r3, #12
800365c: 781b ldrb r3, [r3, #0]
800365e: b2db uxtb r3, r3
8003660: 2b02 cmp r3, #2
8003662: d103 bne.n 800366c <HW_TS_Start+0x2c>
{
HW_TS_Stop( timer_id );
8003664: 79fb ldrb r3, [r7, #7]
8003666: 4618 mov r0, r3
8003668: f7ff ff66 bl 8003538 <HW_TS_Stop>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800366c: f3ef 8310 mrs r3, PRIMASK
8003670: 60fb str r3, [r7, #12]
return(result);
8003672: 68fb ldr r3, [r7, #12]
}
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
8003674: 617b str r3, [r7, #20]
__ASM volatile ("cpsid i" : : : "memory");
8003676: b672 cpsid i
}
8003678: bf00 nop
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
#endif
HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */
800367a: 2003 movs r0, #3
800367c: f001 ffca bl 8005614 <HAL_NVIC_DisableIRQ>
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc );
8003680: 4b2f ldr r3, [pc, #188] @ (8003740 <HW_TS_Start+0x100>)
8003682: 681b ldr r3, [r3, #0]
8003684: 22ca movs r2, #202 @ 0xca
8003686: 625a str r2, [r3, #36] @ 0x24
8003688: 4b2d ldr r3, [pc, #180] @ (8003740 <HW_TS_Start+0x100>)
800368a: 681b ldr r3, [r3, #0]
800368c: 2253 movs r2, #83 @ 0x53
800368e: 625a str r2, [r3, #36] @ 0x24
aTimerContext[timer_id].TimerIDStatus = TimerID_Running;
8003690: 79fa ldrb r2, [r7, #7]
8003692: 492a ldr r1, [pc, #168] @ (800373c <HW_TS_Start+0xfc>)
8003694: 4613 mov r3, r2
8003696: 005b lsls r3, r3, #1
8003698: 4413 add r3, r2
800369a: 00db lsls r3, r3, #3
800369c: 440b add r3, r1
800369e: 330c adds r3, #12
80036a0: 2202 movs r2, #2
80036a2: 701a strb r2, [r3, #0]
aTimerContext[timer_id].CountLeft = timeout_ticks;
80036a4: 79fa ldrb r2, [r7, #7]
80036a6: 4925 ldr r1, [pc, #148] @ (800373c <HW_TS_Start+0xfc>)
80036a8: 4613 mov r3, r2
80036aa: 005b lsls r3, r3, #1
80036ac: 4413 add r3, r2
80036ae: 00db lsls r3, r3, #3
80036b0: 440b add r3, r1
80036b2: 3308 adds r3, #8
80036b4: 683a ldr r2, [r7, #0]
80036b6: 601a str r2, [r3, #0]
aTimerContext[timer_id].CounterInit = timeout_ticks;
80036b8: 79fa ldrb r2, [r7, #7]
80036ba: 4920 ldr r1, [pc, #128] @ (800373c <HW_TS_Start+0xfc>)
80036bc: 4613 mov r3, r2
80036be: 005b lsls r3, r3, #1
80036c0: 4413 add r3, r2
80036c2: 00db lsls r3, r3, #3
80036c4: 440b add r3, r1
80036c6: 3304 adds r3, #4
80036c8: 683a ldr r2, [r7, #0]
80036ca: 601a str r2, [r3, #0]
time_elapsed = linkTimer(timer_id);
80036cc: 79fb ldrb r3, [r7, #7]
80036ce: 4618 mov r0, r3
80036d0: f7ff fb30 bl 8002d34 <linkTimer>
80036d4: 4603 mov r3, r0
80036d6: 827b strh r3, [r7, #18]
localcurrentrunningtimerid = CurrentRunningTimerID;
80036d8: 4b1a ldr r3, [pc, #104] @ (8003744 <HW_TS_Start+0x104>)
80036da: 781b ldrb r3, [r3, #0]
80036dc: 747b strb r3, [r7, #17]
if(PreviousRunningTimerID != localcurrentrunningtimerid)
80036de: 4b1a ldr r3, [pc, #104] @ (8003748 <HW_TS_Start+0x108>)
80036e0: 781b ldrb r3, [r3, #0]
80036e2: b2db uxtb r3, r3
80036e4: 7c7a ldrb r2, [r7, #17]
80036e6: 429a cmp r2, r3
80036e8: d002 beq.n 80036f0 <HW_TS_Start+0xb0>
{
RescheduleTimerList();
80036ea: f7ff fce9 bl 80030c0 <RescheduleTimerList>
80036ee: e013 b.n 8003718 <HW_TS_Start+0xd8>
}
else
{
aTimerContext[timer_id].CountLeft -= time_elapsed;
80036f0: 79fa ldrb r2, [r7, #7]
80036f2: 4912 ldr r1, [pc, #72] @ (800373c <HW_TS_Start+0xfc>)
80036f4: 4613 mov r3, r2
80036f6: 005b lsls r3, r3, #1
80036f8: 4413 add r3, r2
80036fa: 00db lsls r3, r3, #3
80036fc: 440b add r3, r1
80036fe: 3308 adds r3, #8
8003700: 6819 ldr r1, [r3, #0]
8003702: 8a7b ldrh r3, [r7, #18]
8003704: 79fa ldrb r2, [r7, #7]
8003706: 1ac9 subs r1, r1, r3
8003708: 480c ldr r0, [pc, #48] @ (800373c <HW_TS_Start+0xfc>)
800370a: 4613 mov r3, r2
800370c: 005b lsls r3, r3, #1
800370e: 4413 add r3, r2
8003710: 00db lsls r3, r3, #3
8003712: 4403 add r3, r0
8003714: 3308 adds r3, #8
8003716: 6019 str r1, [r3, #0]
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc );
8003718: 4b09 ldr r3, [pc, #36] @ (8003740 <HW_TS_Start+0x100>)
800371a: 681b ldr r3, [r3, #0]
800371c: 22ff movs r2, #255 @ 0xff
800371e: 625a str r2, [r3, #36] @ 0x24
HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */
8003720: 2003 movs r0, #3
8003722: f001 ff69 bl 80055f8 <HAL_NVIC_EnableIRQ>
8003726: 697b ldr r3, [r7, #20]
8003728: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800372a: 68bb ldr r3, [r7, #8]
800372c: f383 8810 msr PRIMASK, r3
}
8003730: bf00 nop
#if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1)
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
#endif
return;
8003732: bf00 nop
}
8003734: 3718 adds r7, #24
8003736: 46bd mov sp, r7
8003738: bd80 pop {r7, pc}
800373a: bf00 nop
800373c: 20000314 .word 0x20000314
8003740: 20000504 .word 0x20000504
8003744: 200003a4 .word 0x200003a4
8003748: 200003a5 .word 0x200003a5
0800374c <HW_TS_RTC_Int_AppNot>:
return (return_value);
}
__weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack)
{
800374c: b580 push {r7, lr}
800374e: b084 sub sp, #16
8003750: af00 add r7, sp, #0
8003752: 60f8 str r0, [r7, #12]
8003754: 460b mov r3, r1
8003756: 607a str r2, [r7, #4]
8003758: 72fb strb r3, [r7, #11]
pTimerCallBack();
800375a: 687b ldr r3, [r7, #4]
800375c: 4798 blx r3
return;
800375e: bf00 nop
}
8003760: 3710 adds r7, #16
8003762: 46bd mov sp, r7
8003764: bd80 pop {r7, pc}
08003766 <ITM_SendChar>:
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
8003766: b480 push {r7}
8003768: b083 sub sp, #12
800376a: af00 add r7, sp, #0
800376c: 6078 str r0, [r7, #4]
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
800376e: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
8003772: f8d3 3e80 ldr.w r3, [r3, #3712] @ 0xe80
8003776: f003 0301 and.w r3, r3, #1
800377a: 2b00 cmp r3, #0
800377c: d013 beq.n 80037a6 <ITM_SendChar+0x40>
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
800377e: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
8003782: f8d3 3e00 ldr.w r3, [r3, #3584] @ 0xe00
8003786: f003 0301 and.w r3, r3, #1
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
800378a: 2b00 cmp r3, #0
800378c: d00b beq.n 80037a6 <ITM_SendChar+0x40>
{
while (ITM->PORT[0U].u32 == 0UL)
800378e: e000 b.n 8003792 <ITM_SendChar+0x2c>
{
__NOP();
8003790: bf00 nop
while (ITM->PORT[0U].u32 == 0UL)
8003792: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
8003796: 681b ldr r3, [r3, #0]
8003798: 2b00 cmp r3, #0
800379a: d0f9 beq.n 8003790 <ITM_SendChar+0x2a>
}
ITM->PORT[0U].u8 = (uint8_t)ch;
800379c: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000
80037a0: 687a ldr r2, [r7, #4]
80037a2: b2d2 uxtb r2, r2
80037a4: 701a strb r2, [r3, #0]
}
return (ch);
80037a6: 687b ldr r3, [r7, #4]
}
80037a8: 4618 mov r0, r3
80037aa: 370c adds r7, #12
80037ac: 46bd mov sp, r7
80037ae: f85d 7b04 ldr.w r7, [sp], #4
80037b2: 4770 bx lr
080037b4 <LL_RCC_LSE_SetDriveCapability>:
{
80037b4: b480 push {r7}
80037b6: b083 sub sp, #12
80037b8: af00 add r7, sp, #0
80037ba: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
80037bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80037c0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80037c4: f023 0218 bic.w r2, r3, #24
80037c8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
80037cc: 687b ldr r3, [r7, #4]
80037ce: 4313 orrs r3, r2
80037d0: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
80037d4: bf00 nop
80037d6: 370c adds r7, #12
80037d8: 46bd mov sp, r7
80037da: f85d 7b04 ldr.w r7, [sp], #4
80037de: 4770 bx lr
080037e0 <LL_AHB1_GRP1_EnableClock>:
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @note (*) Not supported by all the devices
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
{
80037e0: b480 push {r7}
80037e2: b085 sub sp, #20
80037e4: af00 add r7, sp, #0
80037e6: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB1ENR, Periphs);
80037e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80037ec: 6c9a ldr r2, [r3, #72] @ 0x48
80037ee: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
80037f2: 687b ldr r3, [r7, #4]
80037f4: 4313 orrs r3, r2
80037f6: 648b str r3, [r1, #72] @ 0x48
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
80037f8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80037fc: 6c9a ldr r2, [r3, #72] @ 0x48
80037fe: 687b ldr r3, [r7, #4]
8003800: 4013 ands r3, r2
8003802: 60fb str r3, [r7, #12]
(void)tmpreg;
8003804: 68fb ldr r3, [r7, #12]
}
8003806: bf00 nop
8003808: 3714 adds r7, #20
800380a: 46bd mov sp, r7
800380c: f85d 7b04 ldr.w r7, [sp], #4
8003810: 4770 bx lr
08003812 <LL_AHB2_GRP1_EnableClock>:
* @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*)
* @note (*) Not supported by all the devices
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
8003812: b480 push {r7}
8003814: b085 sub sp, #20
8003816: af00 add r7, sp, #0
8003818: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB2ENR, Periphs);
800381a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800381e: 6cda ldr r2, [r3, #76] @ 0x4c
8003820: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8003824: 687b ldr r3, [r7, #4]
8003826: 4313 orrs r3, r2
8003828: 64cb str r3, [r1, #76] @ 0x4c
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
800382a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800382e: 6cda ldr r2, [r3, #76] @ 0x4c
8003830: 687b ldr r3, [r7, #4]
8003832: 4013 ands r3, r2
8003834: 60fb str r3, [r7, #12]
(void)tmpreg;
8003836: 68fb ldr r3, [r7, #12]
}
8003838: bf00 nop
800383a: 3714 adds r7, #20
800383c: 46bd mov sp, r7
800383e: f85d 7b04 ldr.w r7, [sp], #4
8003842: 4770 bx lr
08003844 <LL_HSEM_1StepLock>:
* @param HSEMx HSEM Instance.
* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
* @retval 1 lock fail, 0 lock successful or already locked by same core
*/
__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
{
8003844: b480 push {r7}
8003846: b083 sub sp, #12
8003848: af00 add r7, sp, #0
800384a: 6078 str r0, [r7, #4]
800384c: 6039 str r1, [r7, #0]
return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
800384e: 687b ldr r3, [r7, #4]
8003850: 683a ldr r2, [r7, #0]
8003852: 3220 adds r2, #32
8003854: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8003858: 4a05 ldr r2, [pc, #20] @ (8003870 <LL_HSEM_1StepLock+0x2c>)
800385a: 4293 cmp r3, r2
800385c: d001 beq.n 8003862 <LL_HSEM_1StepLock+0x1e>
800385e: 2301 movs r3, #1
8003860: e000 b.n 8003864 <LL_HSEM_1StepLock+0x20>
8003862: 2300 movs r3, #0
}
8003864: 4618 mov r0, r3
8003866: 370c adds r7, #12
8003868: 46bd mov sp, r7
800386a: f85d 7b04 ldr.w r7, [sp], #4
800386e: 4770 bx lr
8003870: 80000400 .word 0x80000400
08003874 <_write>:
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
// implementation of printf() functionality through ITM
int _write(int file, char *prt, int len) {
8003874: b580 push {r7, lr}
8003876: b086 sub sp, #24
8003878: af00 add r7, sp, #0
800387a: 60f8 str r0, [r7, #12]
800387c: 60b9 str r1, [r7, #8]
800387e: 607a str r2, [r7, #4]
for (int i = 0; i < len; i++) {
8003880: 2300 movs r3, #0
8003882: 617b str r3, [r7, #20]
8003884: e009 b.n 800389a <_write+0x26>
ITM_SendChar(*prt++);
8003886: 68bb ldr r3, [r7, #8]
8003888: 1c5a adds r2, r3, #1
800388a: 60ba str r2, [r7, #8]
800388c: 781b ldrb r3, [r3, #0]
800388e: 4618 mov r0, r3
8003890: f7ff ff69 bl 8003766 <ITM_SendChar>
for (int i = 0; i < len; i++) {
8003894: 697b ldr r3, [r7, #20]
8003896: 3301 adds r3, #1
8003898: 617b str r3, [r7, #20]
800389a: 697a ldr r2, [r7, #20]
800389c: 687b ldr r3, [r7, #4]
800389e: 429a cmp r2, r3
80038a0: dbf1 blt.n 8003886 <_write+0x12>
}
return len;
80038a2: 687b ldr r3, [r7, #4]
}
80038a4: 4618 mov r0, r3
80038a6: 3718 adds r7, #24
80038a8: 46bd mov sp, r7
80038aa: bd80 pop {r7, pc}
080038ac <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80038ac: b580 push {r7, lr}
80038ae: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80038b0: f001 fd24 bl 80052fc <HAL_Init>
/* Config code for STM32_WPAN (HSE Tuning must be done before system clock configuration) */
MX_APPE_Config();
80038b4: f7fd fe1c bl 80014f0 <MX_APPE_Config>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80038b8: f000 f86a bl 8003990 <SystemClock_Config>
/* Configure the peripherals common clocks */
PeriphCommonClock_Config();
80038bc: f000 f8de bl 8003a7c <PeriphCommonClock_Config>
/* IPCC initialisation */
MX_IPCC_Init();
80038c0: f000 f93c bl 8003b3c <MX_IPCC_Init>
/* USER CODE BEGIN SysInit */
// Initialize DWT for the BMM350 delay function to work properly
bmm_init_DWT();
80038c4: f000 ff32 bl 800472c <bmm_init_DWT>
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80038c8: f000 fa9e bl 8003e08 <MX_GPIO_Init>
MX_DMA_Init();
80038cc: f000 fa72 bl 8003db4 <MX_DMA_Init>
MX_I2C1_Init();
80038d0: f000 f8f4 bl 8003abc <MX_I2C1_Init>
MX_SPI1_Init();
80038d4: f000 f982 bl 8003bdc <MX_SPI1_Init>
MX_SPI2_Init();
80038d8: f000 f9be bl 8003c58 <MX_SPI2_Init>
MX_TIM2_Init();
80038dc: f000 f9fa bl 8003cd4 <MX_TIM2_Init>
MX_RTC_Init();
80038e0: f000 f948 bl 8003b74 <MX_RTC_Init>
MX_RF_Init();
80038e4: f000 f93e bl 8003b64 <MX_RF_Init>
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Init scheduler */
osKernelInitialize();
80038e8: f00e fa58 bl 8011d9c <osKernelInitialize>
/* start timers, add new ones, ... */
/* USER CODE END RTOS_TIMERS */
/* Create the queue(s) */
/* creation of Q_ICM */
Q_ICMHandle = osMessageQueueNew (1, sizeof(ICM45686_Data), &Q_ICM_attributes);
80038ec: 4a1a ldr r2, [pc, #104] @ (8003958 <main+0xac>)
80038ee: 211c movs r1, #28
80038f0: 2001 movs r0, #1
80038f2: f00e fe59 bl 80125a8 <osMessageQueueNew>
80038f6: 4603 mov r3, r0
80038f8: 4a18 ldr r2, [pc, #96] @ (800395c <main+0xb0>)
80038fa: 6013 str r3, [r2, #0]
/* creation of Q_BMM */
Q_BMMHandle = osMessageQueueNew (1, sizeof(struct bmm350_mag_temp_data), &Q_BMM_attributes);
80038fc: 4a18 ldr r2, [pc, #96] @ (8003960 <main+0xb4>)
80038fe: 2110 movs r1, #16
8003900: 2001 movs r0, #1
8003902: f00e fe51 bl 80125a8 <osMessageQueueNew>
8003906: 4603 mov r3, r0
8003908: 4a16 ldr r2, [pc, #88] @ (8003964 <main+0xb8>)
800390a: 6013 str r3, [r2, #0]
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* creation of Task_DataAnalys */
Task_DataAnalysHandle = osThreadNew(Start_DataAnalysis, NULL, &Task_DataAnalys_attributes);
800390c: 4a16 ldr r2, [pc, #88] @ (8003968 <main+0xbc>)
800390e: 2100 movs r1, #0
8003910: 4816 ldr r0, [pc, #88] @ (800396c <main+0xc0>)
8003912: f00e fa93 bl 8011e3c <osThreadNew>
8003916: 4603 mov r3, r0
8003918: 4a15 ldr r2, [pc, #84] @ (8003970 <main+0xc4>)
800391a: 6013 str r3, [r2, #0]
/* creation of Task_ICM45686 */
Task_ICM45686Handle = osThreadNew(Start_ICM45686, NULL, &Task_ICM45686_attributes);
800391c: 4a15 ldr r2, [pc, #84] @ (8003974 <main+0xc8>)
800391e: 2100 movs r1, #0
8003920: 4815 ldr r0, [pc, #84] @ (8003978 <main+0xcc>)
8003922: f00e fa8b bl 8011e3c <osThreadNew>
8003926: 4603 mov r3, r0
8003928: 4a14 ldr r2, [pc, #80] @ (800397c <main+0xd0>)
800392a: 6013 str r3, [r2, #0]
/* creation of Task_BMM350 */
Task_BMM350Handle = osThreadNew(Start_BMM350, NULL, &Task_BMM350_attributes);
800392c: 4a14 ldr r2, [pc, #80] @ (8003980 <main+0xd4>)
800392e: 2100 movs r1, #0
8003930: 4814 ldr r0, [pc, #80] @ (8003984 <main+0xd8>)
8003932: f00e fa83 bl 8011e3c <osThreadNew>
8003936: 4603 mov r3, r0
8003938: 4a13 ldr r2, [pc, #76] @ (8003988 <main+0xdc>)
800393a: 6013 str r3, [r2, #0]
/* USER CODE BEGIN RTOS_EVENTS */
/* add events, ... */
/* USER CODE END RTOS_EVENTS */
while(LL_HSEM_1StepLock(HSEM, CFG_HW_CLK48_CONFIG_SEMID));
800393c: bf00 nop
800393e: 2105 movs r1, #5
8003940: 4812 ldr r0, [pc, #72] @ (800398c <main+0xe0>)
8003942: f7ff ff7f bl 8003844 <LL_HSEM_1StepLock>
8003946: 4603 mov r3, r0
8003948: 2b00 cmp r3, #0
800394a: d1f8 bne.n 800393e <main+0x92>
/* Init code for STM32_WPAN */
MX_APPE_Init();
800394c: f7fd fdde bl 800150c <MX_APPE_Init>
/* Start scheduler */
osKernelStart();
8003950: f00e fa4a bl 8011de8 <osKernelStart>
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
8003954: bf00 nop
8003956: e7fd b.n 8003954 <main+0xa8>
8003958: 0801c6e8 .word 0x0801c6e8
800395c: 20000708 .word 0x20000708
8003960: 0801c700 .word 0x0801c700
8003964: 2000070c .word 0x2000070c
8003968: 0801c67c .word 0x0801c67c
800396c: 08003ecd .word 0x08003ecd
8003970: 200006fc .word 0x200006fc
8003974: 0801c6a0 .word 0x0801c6a0
8003978: 08003f99 .word 0x08003f99
800397c: 20000700 .word 0x20000700
8003980: 0801c6c4 .word 0x0801c6c4
8003984: 08004251 .word 0x08004251
8003988: 20000704 .word 0x20000704
800398c: 58001400 .word 0x58001400
08003990 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8003990: b580 push {r7, lr}
8003992: b09a sub sp, #104 @ 0x68
8003994: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8003996: f107 0320 add.w r3, r7, #32
800399a: 2248 movs r2, #72 @ 0x48
800399c: 2100 movs r1, #0
800399e: 4618 mov r0, r3
80039a0: f015 f818 bl 80189d4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80039a4: 1d3b adds r3, r7, #4
80039a6: 2200 movs r2, #0
80039a8: 601a str r2, [r3, #0]
80039aa: 605a str r2, [r3, #4]
80039ac: 609a str r2, [r3, #8]
80039ae: 60da str r2, [r3, #12]
80039b0: 611a str r2, [r3, #16]
80039b2: 615a str r2, [r3, #20]
80039b4: 619a str r2, [r3, #24]
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
80039b6: f005 ff49 bl 800984c <HAL_PWR_EnableBkUpAccess>
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
80039ba: 2010 movs r0, #16
80039bc: f7ff fefa bl 80037b4 <LL_RCC_LSE_SetDriveCapability>
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
80039c0: 4b2d ldr r3, [pc, #180] @ (8003a78 <SystemClock_Config+0xe8>)
80039c2: 681b ldr r3, [r3, #0]
80039c4: f423 63c0 bic.w r3, r3, #1536 @ 0x600
80039c8: 4a2b ldr r2, [pc, #172] @ (8003a78 <SystemClock_Config+0xe8>)
80039ca: f443 7300 orr.w r3, r3, #512 @ 0x200
80039ce: 6013 str r3, [r2, #0]
80039d0: 4b29 ldr r3, [pc, #164] @ (8003a78 <SystemClock_Config+0xe8>)
80039d2: 681b ldr r3, [r3, #0]
80039d4: f403 63c0 and.w r3, r3, #1536 @ 0x600
80039d8: 603b str r3, [r7, #0]
80039da: 683b ldr r3, [r7, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI1
80039dc: 232f movs r3, #47 @ 0x2f
80039de: 623b str r3, [r7, #32]
|RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE
|RCC_OSCILLATORTYPE_MSI;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80039e0: f44f 3380 mov.w r3, #65536 @ 0x10000
80039e4: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
80039e6: 2301 movs r3, #1
80039e8: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80039ea: f44f 7380 mov.w r3, #256 @ 0x100
80039ee: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
80039f0: 2301 movs r3, #1
80039f2: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80039f4: 2340 movs r3, #64 @ 0x40
80039f6: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
80039f8: 2300 movs r3, #0
80039fa: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
80039fc: 2360 movs r3, #96 @ 0x60
80039fe: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
8003a00: 2305 movs r3, #5
8003a02: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8003a04: 2302 movs r3, #2
8003a06: 64fb str r3, [r7, #76] @ 0x4c
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
8003a08: 2301 movs r3, #1
8003a0a: 653b str r3, [r7, #80] @ 0x50
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
8003a0c: 2300 movs r3, #0
8003a0e: 657b str r3, [r7, #84] @ 0x54
RCC_OscInitStruct.PLL.PLLN = 32;
8003a10: 2320 movs r3, #32
8003a12: 65bb str r3, [r7, #88] @ 0x58
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8003a14: f44f 3300 mov.w r3, #131072 @ 0x20000
8003a18: 65fb str r3, [r7, #92] @ 0x5c
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
8003a1a: f04f 5300 mov.w r3, #536870912 @ 0x20000000
8003a1e: 667b str r3, [r7, #100] @ 0x64
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
8003a20: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8003a24: 663b str r3, [r7, #96] @ 0x60
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8003a26: f107 0320 add.w r3, r7, #32
8003a2a: 4618 mov r0, r3
8003a2c: f006 fabe bl 8009fac <HAL_RCC_OscConfig>
8003a30: 4603 mov r3, r0
8003a32: 2b00 cmp r3, #0
8003a34: d001 beq.n 8003a3a <SystemClock_Config+0xaa>
{
Error_Handler();
8003a36: f000 fc6b bl 8004310 <Error_Handler>
}
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
8003a3a: 236f movs r3, #111 @ 0x6f
8003a3c: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8003a3e: 2303 movs r3, #3
8003a40: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8003a42: 2300 movs r3, #0
8003a44: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8003a46: 2300 movs r3, #0
8003a48: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8003a4a: 2300 movs r3, #0
8003a4c: 617b str r3, [r7, #20]
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
8003a4e: 2380 movs r3, #128 @ 0x80
8003a50: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
8003a52: 2300 movs r3, #0
8003a54: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
8003a56: 1d3b adds r3, r7, #4
8003a58: 2103 movs r1, #3
8003a5a: 4618 mov r0, r3
8003a5c: f006 fe1a bl 800a694 <HAL_RCC_ClockConfig>
8003a60: 4603 mov r3, r0
8003a62: 2b00 cmp r3, #0
8003a64: d001 beq.n 8003a6a <SystemClock_Config+0xda>
{
Error_Handler();
8003a66: f000 fc53 bl 8004310 <Error_Handler>
}
/** Enable MSI Auto calibration
*/
HAL_RCCEx_EnableMSIPLLMode();
8003a6a: f007 fbf1 bl 800b250 <HAL_RCCEx_EnableMSIPLLMode>
}
8003a6e: bf00 nop
8003a70: 3768 adds r7, #104 @ 0x68
8003a72: 46bd mov sp, r7
8003a74: bd80 pop {r7, pc}
8003a76: bf00 nop
8003a78: 58000400 .word 0x58000400
08003a7c <PeriphCommonClock_Config>:
/**
* @brief Peripherals Common Clock Configuration
* @retval None
*/
void PeriphCommonClock_Config(void)
{
8003a7c: b580 push {r7, lr}
8003a7e: b094 sub sp, #80 @ 0x50
8003a80: af00 add r7, sp, #0
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8003a82: 463b mov r3, r7
8003a84: 2250 movs r2, #80 @ 0x50
8003a86: 2100 movs r1, #0
8003a88: 4618 mov r0, r3
8003a8a: f014 ffa3 bl 80189d4 <memset>
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP;
8003a8e: f44f 5340 mov.w r3, #12288 @ 0x3000
8003a92: 603b str r3, [r7, #0]
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_HSE_DIV1024;
8003a94: f44f 4340 mov.w r3, #49152 @ 0xc000
8003a98: 647b str r3, [r7, #68] @ 0x44
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
8003a9a: 2300 movs r3, #0
8003a9c: 64bb str r3, [r7, #72] @ 0x48
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
8003a9e: 2310 movs r3, #16
8003aa0: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8003aa2: 463b mov r3, r7
8003aa4: 4618 mov r0, r3
8003aa6: f007 fa5d bl 800af64 <HAL_RCCEx_PeriphCLKConfig>
8003aaa: 4603 mov r3, r0
8003aac: 2b00 cmp r3, #0
8003aae: d001 beq.n 8003ab4 <PeriphCommonClock_Config+0x38>
{
Error_Handler();
8003ab0: f000 fc2e bl 8004310 <Error_Handler>
}
/* USER CODE BEGIN Smps */
/* USER CODE END Smps */
}
8003ab4: bf00 nop
8003ab6: 3750 adds r7, #80 @ 0x50
8003ab8: 46bd mov sp, r7
8003aba: bd80 pop {r7, pc}
08003abc <MX_I2C1_Init>:
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
8003abc: b580 push {r7, lr}
8003abe: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
8003ac0: 4b1b ldr r3, [pc, #108] @ (8003b30 <MX_I2C1_Init+0x74>)
8003ac2: 4a1c ldr r2, [pc, #112] @ (8003b34 <MX_I2C1_Init+0x78>)
8003ac4: 601a str r2, [r3, #0]
hi2c1.Init.Timing = 0x10B17DB5;
8003ac6: 4b1a ldr r3, [pc, #104] @ (8003b30 <MX_I2C1_Init+0x74>)
8003ac8: 4a1b ldr r2, [pc, #108] @ (8003b38 <MX_I2C1_Init+0x7c>)
8003aca: 605a str r2, [r3, #4]
hi2c1.Init.OwnAddress1 = 0;
8003acc: 4b18 ldr r3, [pc, #96] @ (8003b30 <MX_I2C1_Init+0x74>)
8003ace: 2200 movs r2, #0
8003ad0: 609a str r2, [r3, #8]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8003ad2: 4b17 ldr r3, [pc, #92] @ (8003b30 <MX_I2C1_Init+0x74>)
8003ad4: 2201 movs r2, #1
8003ad6: 60da str r2, [r3, #12]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8003ad8: 4b15 ldr r3, [pc, #84] @ (8003b30 <MX_I2C1_Init+0x74>)
8003ada: 2200 movs r2, #0
8003adc: 611a str r2, [r3, #16]
hi2c1.Init.OwnAddress2 = 0;
8003ade: 4b14 ldr r3, [pc, #80] @ (8003b30 <MX_I2C1_Init+0x74>)
8003ae0: 2200 movs r2, #0
8003ae2: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
8003ae4: 4b12 ldr r3, [pc, #72] @ (8003b30 <MX_I2C1_Init+0x74>)
8003ae6: 2200 movs r2, #0
8003ae8: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8003aea: 4b11 ldr r3, [pc, #68] @ (8003b30 <MX_I2C1_Init+0x74>)
8003aec: 2200 movs r2, #0
8003aee: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8003af0: 4b0f ldr r3, [pc, #60] @ (8003b30 <MX_I2C1_Init+0x74>)
8003af2: 2200 movs r2, #0
8003af4: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
8003af6: 480e ldr r0, [pc, #56] @ (8003b30 <MX_I2C1_Init+0x74>)
8003af8: f002 fa44 bl 8005f84 <HAL_I2C_Init>
8003afc: 4603 mov r3, r0
8003afe: 2b00 cmp r3, #0
8003b00: d001 beq.n 8003b06 <MX_I2C1_Init+0x4a>
{
Error_Handler();
8003b02: f000 fc05 bl 8004310 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
8003b06: 2100 movs r1, #0
8003b08: 4809 ldr r0, [pc, #36] @ (8003b30 <MX_I2C1_Init+0x74>)
8003b0a: f004 f83f bl 8007b8c <HAL_I2CEx_ConfigAnalogFilter>
8003b0e: 4603 mov r3, r0
8003b10: 2b00 cmp r3, #0
8003b12: d001 beq.n 8003b18 <MX_I2C1_Init+0x5c>
{
Error_Handler();
8003b14: f000 fbfc bl 8004310 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
8003b18: 2100 movs r1, #0
8003b1a: 4805 ldr r0, [pc, #20] @ (8003b30 <MX_I2C1_Init+0x74>)
8003b1c: f004 f881 bl 8007c22 <HAL_I2CEx_ConfigDigitalFilter>
8003b20: 4603 mov r3, r0
8003b22: 2b00 cmp r3, #0
8003b24: d001 beq.n 8003b2a <MX_I2C1_Init+0x6e>
{
Error_Handler();
8003b26: f000 fbf3 bl 8004310 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
8003b2a: bf00 nop
8003b2c: bd80 pop {r7, pc}
8003b2e: bf00 nop
8003b30: 200003b4 .word 0x200003b4
8003b34: 40005400 .word 0x40005400
8003b38: 10b17db5 .word 0x10b17db5
08003b3c <MX_IPCC_Init>:
* @brief IPCC Initialization Function
* @param None
* @retval None
*/
static void MX_IPCC_Init(void)
{
8003b3c: b580 push {r7, lr}
8003b3e: af00 add r7, sp, #0
/* USER CODE END IPCC_Init 0 */
/* USER CODE BEGIN IPCC_Init 1 */
/* USER CODE END IPCC_Init 1 */
hipcc.Instance = IPCC;
8003b40: 4b06 ldr r3, [pc, #24] @ (8003b5c <MX_IPCC_Init+0x20>)
8003b42: 4a07 ldr r2, [pc, #28] @ (8003b60 <MX_IPCC_Init+0x24>)
8003b44: 601a str r2, [r3, #0]
if (HAL_IPCC_Init(&hipcc) != HAL_OK)
8003b46: 4805 ldr r0, [pc, #20] @ (8003b5c <MX_IPCC_Init+0x20>)
8003b48: f004 f8b8 bl 8007cbc <HAL_IPCC_Init>
8003b4c: 4603 mov r3, r0
8003b4e: 2b00 cmp r3, #0
8003b50: d001 beq.n 8003b56 <MX_IPCC_Init+0x1a>
{
Error_Handler();
8003b52: f000 fbdd bl 8004310 <Error_Handler>
}
/* USER CODE BEGIN IPCC_Init 2 */
/* USER CODE END IPCC_Init 2 */
}
8003b56: bf00 nop
8003b58: bd80 pop {r7, pc}
8003b5a: bf00 nop
8003b5c: 200004c8 .word 0x200004c8
8003b60: 58000c00 .word 0x58000c00
08003b64 <MX_RF_Init>:
* @brief RF Initialization Function
* @param None
* @retval None
*/
static void MX_RF_Init(void)
{
8003b64: b480 push {r7}
8003b66: af00 add r7, sp, #0
/* USER CODE END RF_Init 1 */
/* USER CODE BEGIN RF_Init 2 */
/* USER CODE END RF_Init 2 */
}
8003b68: bf00 nop
8003b6a: 46bd mov sp, r7
8003b6c: f85d 7b04 ldr.w r7, [sp], #4
8003b70: 4770 bx lr
...
08003b74 <MX_RTC_Init>:
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static void MX_RTC_Init(void)
{
8003b74: b580 push {r7, lr}
8003b76: af00 add r7, sp, #0
/* USER CODE END RTC_Init 1 */
/** Initialize RTC Only
*/
hrtc.Instance = RTC;
8003b78: 4b16 ldr r3, [pc, #88] @ (8003bd4 <MX_RTC_Init+0x60>)
8003b7a: 4a17 ldr r2, [pc, #92] @ (8003bd8 <MX_RTC_Init+0x64>)
8003b7c: 601a str r2, [r3, #0]
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
8003b7e: 4b15 ldr r3, [pc, #84] @ (8003bd4 <MX_RTC_Init+0x60>)
8003b80: 2200 movs r2, #0
8003b82: 605a str r2, [r3, #4]
hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER;
8003b84: 4b13 ldr r3, [pc, #76] @ (8003bd4 <MX_RTC_Init+0x60>)
8003b86: 220f movs r2, #15
8003b88: 609a str r2, [r3, #8]
hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER;
8003b8a: 4b12 ldr r3, [pc, #72] @ (8003bd4 <MX_RTC_Init+0x60>)
8003b8c: f647 72ff movw r2, #32767 @ 0x7fff
8003b90: 60da str r2, [r3, #12]
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
8003b92: 4b10 ldr r3, [pc, #64] @ (8003bd4 <MX_RTC_Init+0x60>)
8003b94: 2200 movs r2, #0
8003b96: 611a str r2, [r3, #16]
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
8003b98: 4b0e ldr r3, [pc, #56] @ (8003bd4 <MX_RTC_Init+0x60>)
8003b9a: 2200 movs r2, #0
8003b9c: 619a str r2, [r3, #24]
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
8003b9e: 4b0d ldr r3, [pc, #52] @ (8003bd4 <MX_RTC_Init+0x60>)
8003ba0: 2200 movs r2, #0
8003ba2: 61da str r2, [r3, #28]
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;
8003ba4: 4b0b ldr r3, [pc, #44] @ (8003bd4 <MX_RTC_Init+0x60>)
8003ba6: 2200 movs r2, #0
8003ba8: 615a str r2, [r3, #20]
if (HAL_RTC_Init(&hrtc) != HAL_OK)
8003baa: 480a ldr r0, [pc, #40] @ (8003bd4 <MX_RTC_Init+0x60>)
8003bac: f007 fc67 bl 800b47e <HAL_RTC_Init>
8003bb0: 4603 mov r3, r0
8003bb2: 2b00 cmp r3, #0
8003bb4: d001 beq.n 8003bba <MX_RTC_Init+0x46>
{
Error_Handler();
8003bb6: f000 fbab bl 8004310 <Error_Handler>
}
/** Enable the WakeUp
*/
if (HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 0, RTC_WAKEUPCLOCK_RTCCLK_DIV16) != HAL_OK)
8003bba: 2200 movs r2, #0
8003bbc: 2100 movs r1, #0
8003bbe: 4805 ldr r0, [pc, #20] @ (8003bd4 <MX_RTC_Init+0x60>)
8003bc0: f007 fd6a bl 800b698 <HAL_RTCEx_SetWakeUpTimer_IT>
8003bc4: 4603 mov r3, r0
8003bc6: 2b00 cmp r3, #0
8003bc8: d001 beq.n 8003bce <MX_RTC_Init+0x5a>
{
Error_Handler();
8003bca: f000 fba1 bl 8004310 <Error_Handler>
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
8003bce: bf00 nop
8003bd0: bd80 pop {r7, pc}
8003bd2: bf00 nop
8003bd4: 20000504 .word 0x20000504
8003bd8: 40002800 .word 0x40002800
08003bdc <MX_SPI1_Init>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
8003bdc: b580 push {r7, lr}
8003bde: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
8003be0: 4b1b ldr r3, [pc, #108] @ (8003c50 <MX_SPI1_Init+0x74>)
8003be2: 4a1c ldr r2, [pc, #112] @ (8003c54 <MX_SPI1_Init+0x78>)
8003be4: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
8003be6: 4b1a ldr r3, [pc, #104] @ (8003c50 <MX_SPI1_Init+0x74>)
8003be8: f44f 7282 mov.w r2, #260 @ 0x104
8003bec: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
8003bee: 4b18 ldr r3, [pc, #96] @ (8003c50 <MX_SPI1_Init+0x74>)
8003bf0: 2200 movs r2, #0
8003bf2: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
8003bf4: 4b16 ldr r3, [pc, #88] @ (8003c50 <MX_SPI1_Init+0x74>)
8003bf6: f44f 62e0 mov.w r2, #1792 @ 0x700
8003bfa: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
8003bfc: 4b14 ldr r3, [pc, #80] @ (8003c50 <MX_SPI1_Init+0x74>)
8003bfe: 2202 movs r2, #2
8003c00: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
8003c02: 4b13 ldr r3, [pc, #76] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c04: 2201 movs r2, #1
8003c06: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
8003c08: 4b11 ldr r3, [pc, #68] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c0a: f44f 7200 mov.w r2, #512 @ 0x200
8003c0e: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
8003c10: 4b0f ldr r3, [pc, #60] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c12: 2228 movs r2, #40 @ 0x28
8003c14: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
8003c16: 4b0e ldr r3, [pc, #56] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c18: 2200 movs r2, #0
8003c1a: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8003c1c: 4b0c ldr r3, [pc, #48] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c1e: 2200 movs r2, #0
8003c20: 625a str r2, [r3, #36] @ 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003c22: 4b0b ldr r3, [pc, #44] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c24: 2200 movs r2, #0
8003c26: 629a str r2, [r3, #40] @ 0x28
hspi1.Init.CRCPolynomial = 7;
8003c28: 4b09 ldr r3, [pc, #36] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c2a: 2207 movs r2, #7
8003c2c: 62da str r2, [r3, #44] @ 0x2c
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
8003c2e: 4b08 ldr r3, [pc, #32] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c30: 2200 movs r2, #0
8003c32: 631a str r2, [r3, #48] @ 0x30
hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
8003c34: 4b06 ldr r3, [pc, #24] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c36: 2200 movs r2, #0
8003c38: 635a str r2, [r3, #52] @ 0x34
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8003c3a: 4805 ldr r0, [pc, #20] @ (8003c50 <MX_SPI1_Init+0x74>)
8003c3c: f007 fdf8 bl 800b830 <HAL_SPI_Init>
8003c40: 4603 mov r3, r0
8003c42: 2b00 cmp r3, #0
8003c44: d001 beq.n 8003c4a <MX_SPI1_Init+0x6e>
{
Error_Handler();
8003c46: f000 fb63 bl 8004310 <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
8003c4a: bf00 nop
8003c4c: bd80 pop {r7, pc}
8003c4e: bf00 nop
8003c50: 20000528 .word 0x20000528
8003c54: 40013000 .word 0x40013000
08003c58 <MX_SPI2_Init>:
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
8003c58: b580 push {r7, lr}
8003c5a: af00 add r7, sp, #0
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
8003c5c: 4b1b ldr r3, [pc, #108] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c5e: 4a1c ldr r2, [pc, #112] @ (8003cd0 <MX_SPI2_Init+0x78>)
8003c60: 601a str r2, [r3, #0]
hspi2.Init.Mode = SPI_MODE_MASTER;
8003c62: 4b1a ldr r3, [pc, #104] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c64: f44f 7282 mov.w r2, #260 @ 0x104
8003c68: 605a str r2, [r3, #4]
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
8003c6a: 4b18 ldr r3, [pc, #96] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c6c: 2200 movs r2, #0
8003c6e: 609a str r2, [r3, #8]
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
8003c70: 4b16 ldr r3, [pc, #88] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c72: f44f 7240 mov.w r2, #768 @ 0x300
8003c76: 60da str r2, [r3, #12]
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
8003c78: 4b14 ldr r3, [pc, #80] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c7a: 2200 movs r2, #0
8003c7c: 611a str r2, [r3, #16]
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
8003c7e: 4b13 ldr r3, [pc, #76] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c80: 2200 movs r2, #0
8003c82: 615a str r2, [r3, #20]
hspi2.Init.NSS = SPI_NSS_SOFT;
8003c84: 4b11 ldr r3, [pc, #68] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c86: f44f 7200 mov.w r2, #512 @ 0x200
8003c8a: 619a str r2, [r3, #24]
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8003c8c: 4b0f ldr r3, [pc, #60] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c8e: 2200 movs r2, #0
8003c90: 61da str r2, [r3, #28]
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
8003c92: 4b0e ldr r3, [pc, #56] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c94: 2200 movs r2, #0
8003c96: 621a str r2, [r3, #32]
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
8003c98: 4b0c ldr r3, [pc, #48] @ (8003ccc <MX_SPI2_Init+0x74>)
8003c9a: 2200 movs r2, #0
8003c9c: 625a str r2, [r3, #36] @ 0x24
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003c9e: 4b0b ldr r3, [pc, #44] @ (8003ccc <MX_SPI2_Init+0x74>)
8003ca0: 2200 movs r2, #0
8003ca2: 629a str r2, [r3, #40] @ 0x28
hspi2.Init.CRCPolynomial = 7;
8003ca4: 4b09 ldr r3, [pc, #36] @ (8003ccc <MX_SPI2_Init+0x74>)
8003ca6: 2207 movs r2, #7
8003ca8: 62da str r2, [r3, #44] @ 0x2c
hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
8003caa: 4b08 ldr r3, [pc, #32] @ (8003ccc <MX_SPI2_Init+0x74>)
8003cac: 2200 movs r2, #0
8003cae: 631a str r2, [r3, #48] @ 0x30
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
8003cb0: 4b06 ldr r3, [pc, #24] @ (8003ccc <MX_SPI2_Init+0x74>)
8003cb2: 2208 movs r2, #8
8003cb4: 635a str r2, [r3, #52] @ 0x34
if (HAL_SPI_Init(&hspi2) != HAL_OK)
8003cb6: 4805 ldr r0, [pc, #20] @ (8003ccc <MX_SPI2_Init+0x74>)
8003cb8: f007 fdba bl 800b830 <HAL_SPI_Init>
8003cbc: 4603 mov r3, r0
8003cbe: 2b00 cmp r3, #0
8003cc0: d001 beq.n 8003cc6 <MX_SPI2_Init+0x6e>
{
Error_Handler();
8003cc2: f000 fb25 bl 8004310 <Error_Handler>
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
8003cc6: bf00 nop
8003cc8: bd80 pop {r7, pc}
8003cca: bf00 nop
8003ccc: 2000058c .word 0x2000058c
8003cd0: 40003800 .word 0x40003800
08003cd4 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8003cd4: b580 push {r7, lr}
8003cd6: b08a sub sp, #40 @ 0x28
8003cd8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
8003cda: f107 031c add.w r3, r7, #28
8003cde: 2200 movs r2, #0
8003ce0: 601a str r2, [r3, #0]
8003ce2: 605a str r2, [r3, #4]
8003ce4: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
8003ce6: 463b mov r3, r7
8003ce8: 2200 movs r2, #0
8003cea: 601a str r2, [r3, #0]
8003cec: 605a str r2, [r3, #4]
8003cee: 609a str r2, [r3, #8]
8003cf0: 60da str r2, [r3, #12]
8003cf2: 611a str r2, [r3, #16]
8003cf4: 615a str r2, [r3, #20]
8003cf6: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8003cf8: 4b2d ldr r3, [pc, #180] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003cfa: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8003cfe: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 63;
8003d00: 4b2b ldr r3, [pc, #172] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d02: 223f movs r2, #63 @ 0x3f
8003d04: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8003d06: 4b2a ldr r3, [pc, #168] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d08: 2200 movs r2, #0
8003d0a: 609a str r2, [r3, #8]
htim2.Init.Period = 999;
8003d0c: 4b28 ldr r3, [pc, #160] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d0e: f240 32e7 movw r2, #999 @ 0x3e7
8003d12: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8003d14: 4b26 ldr r3, [pc, #152] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d16: 2200 movs r2, #0
8003d18: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8003d1a: 4b25 ldr r3, [pc, #148] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d1c: 2200 movs r2, #0
8003d1e: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
8003d20: 4823 ldr r0, [pc, #140] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d22: f008 feaf bl 800ca84 <HAL_TIM_PWM_Init>
8003d26: 4603 mov r3, r0
8003d28: 2b00 cmp r3, #0
8003d2a: d001 beq.n 8003d30 <MX_TIM2_Init+0x5c>
{
Error_Handler();
8003d2c: f000 faf0 bl 8004310 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8003d30: 2300 movs r3, #0
8003d32: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8003d34: 2300 movs r3, #0
8003d36: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8003d38: f107 031c add.w r3, r7, #28
8003d3c: 4619 mov r1, r3
8003d3e: 481c ldr r0, [pc, #112] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d40: f009 fc28 bl 800d594 <HAL_TIMEx_MasterConfigSynchronization>
8003d44: 4603 mov r3, r0
8003d46: 2b00 cmp r3, #0
8003d48: d001 beq.n 8003d4e <MX_TIM2_Init+0x7a>
{
Error_Handler();
8003d4a: f000 fae1 bl 8004310 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8003d4e: 2360 movs r3, #96 @ 0x60
8003d50: 603b str r3, [r7, #0]
sConfigOC.Pulse = 0;
8003d52: 2300 movs r3, #0
8003d54: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8003d56: 2300 movs r3, #0
8003d58: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8003d5a: 2300 movs r3, #0
8003d5c: 613b str r3, [r7, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8003d5e: 463b mov r3, r7
8003d60: 2200 movs r2, #0
8003d62: 4619 mov r1, r3
8003d64: 4812 ldr r0, [pc, #72] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d66: f008 ffeb bl 800cd40 <HAL_TIM_PWM_ConfigChannel>
8003d6a: 4603 mov r3, r0
8003d6c: 2b00 cmp r3, #0
8003d6e: d001 beq.n 8003d74 <MX_TIM2_Init+0xa0>
{
Error_Handler();
8003d70: f000 face bl 8004310 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8003d74: 463b mov r3, r7
8003d76: 2204 movs r2, #4
8003d78: 4619 mov r1, r3
8003d7a: 480d ldr r0, [pc, #52] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d7c: f008 ffe0 bl 800cd40 <HAL_TIM_PWM_ConfigChannel>
8003d80: 4603 mov r3, r0
8003d82: 2b00 cmp r3, #0
8003d84: d001 beq.n 8003d8a <MX_TIM2_Init+0xb6>
{
Error_Handler();
8003d86: f000 fac3 bl 8004310 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8003d8a: 463b mov r3, r7
8003d8c: 2208 movs r2, #8
8003d8e: 4619 mov r1, r3
8003d90: 4807 ldr r0, [pc, #28] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003d92: f008 ffd5 bl 800cd40 <HAL_TIM_PWM_ConfigChannel>
8003d96: 4603 mov r3, r0
8003d98: 2b00 cmp r3, #0
8003d9a: d001 beq.n 8003da0 <MX_TIM2_Init+0xcc>
{
Error_Handler();
8003d9c: f000 fab8 bl 8004310 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
8003da0: 4803 ldr r0, [pc, #12] @ (8003db0 <MX_TIM2_Init+0xdc>)
8003da2: f001 f841 bl 8004e28 <HAL_TIM_MspPostInit>
}
8003da6: bf00 nop
8003da8: 3728 adds r7, #40 @ 0x28
8003daa: 46bd mov sp, r7
8003dac: bd80 pop {r7, pc}
8003dae: bf00 nop
8003db0: 200006b0 .word 0x200006b0
08003db4 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
8003db4: b580 push {r7, lr}
8003db6: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
8003db8: 2004 movs r0, #4
8003dba: f7ff fd11 bl 80037e0 <LL_AHB1_GRP1_EnableClock>
__HAL_RCC_DMA1_CLK_ENABLE();
8003dbe: 2001 movs r0, #1
8003dc0: f7ff fd0e bl 80037e0 <LL_AHB1_GRP1_EnableClock>
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0);
8003dc4: 2200 movs r2, #0
8003dc6: 2105 movs r1, #5
8003dc8: 200b movs r0, #11
8003dca: f001 fbfb bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
8003dce: 200b movs r0, #11
8003dd0: f001 fc12 bl 80055f8 <HAL_NVIC_EnableIRQ>
/* DMA1_Channel2_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 5, 0);
8003dd4: 2200 movs r2, #0
8003dd6: 2105 movs r1, #5
8003dd8: 200c movs r0, #12
8003dda: f001 fbf3 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
8003dde: 200c movs r0, #12
8003de0: f001 fc0a bl 80055f8 <HAL_NVIC_EnableIRQ>
/* DMA1_Channel3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 5, 0);
8003de4: 2200 movs r2, #0
8003de6: 2105 movs r1, #5
8003de8: 200d movs r0, #13
8003dea: f001 fbeb bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
8003dee: 200d movs r0, #13
8003df0: f001 fc02 bl 80055f8 <HAL_NVIC_EnableIRQ>
/* DMA1_Channel4_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 5, 0);
8003df4: 2200 movs r2, #0
8003df6: 2105 movs r1, #5
8003df8: 200e movs r0, #14
8003dfa: f001 fbe3 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
8003dfe: 200e movs r0, #14
8003e00: f001 fbfa bl 80055f8 <HAL_NVIC_EnableIRQ>
}
8003e04: bf00 nop
8003e06: bd80 pop {r7, pc}
08003e08 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8003e08: b580 push {r7, lr}
8003e0a: b086 sub sp, #24
8003e0c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003e0e: 1d3b adds r3, r7, #4
8003e10: 2200 movs r2, #0
8003e12: 601a str r2, [r3, #0]
8003e14: 605a str r2, [r3, #4]
8003e16: 609a str r2, [r3, #8]
8003e18: 60da str r2, [r3, #12]
8003e1a: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8003e1c: 2004 movs r0, #4
8003e1e: f7ff fcf8 bl 8003812 <LL_AHB2_GRP1_EnableClock>
__HAL_RCC_GPIOB_CLK_ENABLE();
8003e22: 2002 movs r0, #2
8003e24: f7ff fcf5 bl 8003812 <LL_AHB2_GRP1_EnableClock>
__HAL_RCC_GPIOA_CLK_ENABLE();
8003e28: 2001 movs r0, #1
8003e2a: f7ff fcf2 bl 8003812 <LL_AHB2_GRP1_EnableClock>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIO_SPI1_IMU_CS_GPIO_Port, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
8003e2e: 2201 movs r2, #1
8003e30: 2108 movs r1, #8
8003e32: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8003e36: f002 f869 bl 8005f0c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_SPI2_SD_CD_Pin|GPIO_SPI2_SD_CS_Pin, GPIO_PIN_SET);
8003e3a: 2201 movs r2, #1
8003e3c: 2160 movs r1, #96 @ 0x60
8003e3e: 4822 ldr r0, [pc, #136] @ (8003ec8 <MX_GPIO_Init+0xc0>)
8003e40: f002 f864 bl 8005f0c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIO_SD_LDO_EN_GPIO_Port, GPIO_SD_LDO_EN_Pin, GPIO_PIN_RESET);
8003e44: 2200 movs r2, #0
8003e46: f44f 5180 mov.w r1, #4096 @ 0x1000
8003e4a: 481f ldr r0, [pc, #124] @ (8003ec8 <MX_GPIO_Init+0xc0>)
8003e4c: f002 f85e bl 8005f0c <HAL_GPIO_WritePin>
/*Configure GPIO pin : GPIO_SPI1_IMU_CS_Pin */
GPIO_InitStruct.Pin = GPIO_SPI1_IMU_CS_Pin;
8003e50: 2308 movs r3, #8
8003e52: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8003e54: 2301 movs r3, #1
8003e56: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003e58: 2300 movs r3, #0
8003e5a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8003e5c: 2303 movs r3, #3
8003e5e: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIO_SPI1_IMU_CS_GPIO_Port, &GPIO_InitStruct);
8003e60: 1d3b adds r3, r7, #4
8003e62: 4619 mov r1, r3
8003e64: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8003e68: f001 fee0 bl 8005c2c <HAL_GPIO_Init>
/*Configure GPIO pins : GPIO_SPI2_SD_CD_Pin GPIO_SPI2_SD_CS_Pin GPIO_SD_LDO_EN_Pin */
GPIO_InitStruct.Pin = GPIO_SPI2_SD_CD_Pin|GPIO_SPI2_SD_CS_Pin|GPIO_SD_LDO_EN_Pin;
8003e6c: f44f 5383 mov.w r3, #4192 @ 0x1060
8003e70: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8003e72: 2301 movs r3, #1
8003e74: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003e76: 2300 movs r3, #0
8003e78: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8003e7a: 2303 movs r3, #3
8003e7c: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8003e7e: 1d3b adds r3, r7, #4
8003e80: 4619 mov r1, r3
8003e82: 4811 ldr r0, [pc, #68] @ (8003ec8 <MX_GPIO_Init+0xc0>)
8003e84: f001 fed2 bl 8005c2c <HAL_GPIO_Init>
/*Configure GPIO pin : GPIO_IMU_INT_Pin */
GPIO_InitStruct.Pin = GPIO_IMU_INT_Pin;
8003e88: f44f 6380 mov.w r3, #1024 @ 0x400
8003e8c: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8003e8e: f44f 1388 mov.w r3, #1114112 @ 0x110000
8003e92: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003e94: 2300 movs r3, #0
8003e96: 60fb str r3, [r7, #12]
HAL_GPIO_Init(GPIO_IMU_INT_GPIO_Port, &GPIO_InitStruct);
8003e98: 1d3b adds r3, r7, #4
8003e9a: 4619 mov r1, r3
8003e9c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8003ea0: f001 fec4 bl 8005c2c <HAL_GPIO_Init>
/*Configure GPIO pin : GPIO_MAGN_INT_Pin */
GPIO_InitStruct.Pin = GPIO_MAGN_INT_Pin;
8003ea4: f44f 6300 mov.w r3, #2048 @ 0x800
8003ea8: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8003eaa: f44f 1388 mov.w r3, #1114112 @ 0x110000
8003eae: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003eb0: 2300 movs r3, #0
8003eb2: 60fb str r3, [r7, #12]
HAL_GPIO_Init(GPIO_MAGN_INT_GPIO_Port, &GPIO_InitStruct);
8003eb4: 1d3b adds r3, r7, #4
8003eb6: 4619 mov r1, r3
8003eb8: 4803 ldr r0, [pc, #12] @ (8003ec8 <MX_GPIO_Init+0xc0>)
8003eba: f001 feb7 bl 8005c2c <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8003ebe: bf00 nop
8003ec0: 3718 adds r7, #24
8003ec2: 46bd mov sp, r7
8003ec4: bd80 pop {r7, pc}
8003ec6: bf00 nop
8003ec8: 48000800 .word 0x48000800
08003ecc <Start_DataAnalysis>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_Start_DataAnalysis */
void Start_DataAnalysis(void *argument)
{
8003ecc: b580 push {r7, lr}
8003ece: b092 sub sp, #72 @ 0x48
8003ed0: af00 add r7, sp, #0
8003ed2: 6078 str r0, [r7, #4]
/* init code for USB_Device */
MX_USB_Device_Init();
8003ed4: f012 ff48 bl 8016d68 <MX_USB_Device_Init>
// char output_buffer[128];
ICM45686_Data imu_data;
struct bmm350_mag_temp_data magn_data;
// struct bmm350_raw_mag_data magn_data;
QuaternionData Quat_Dat;
Quat_Dat.StartByte = PACKET_START_BYTE;
8003ed8: 23de movs r3, #222 @ 0xde
8003eda: 723b strb r3, [r7, #8]
Quat_Dat.SensorAddress = BMM350_I2C_ADSEL_SET_LOW;
8003edc: 2314 movs r3, #20
8003ede: 727b strb r3, [r7, #9]
Quat_Dat.EndByte = PACKET_END_BYTE;
8003ee0: 23ad movs r3, #173 @ 0xad
8003ee2: 76bb strb r3, [r7, #26]
MadgwickAHRS_init(&IMUQuat, 6400.0f, 0.15f);
8003ee4: eddf 0a27 vldr s1, [pc, #156] @ 8003f84 <Start_DataAnalysis+0xb8>
8003ee8: ed9f 0a27 vldr s0, [pc, #156] @ 8003f88 <Start_DataAnalysis+0xbc>
8003eec: 4827 ldr r0, [pc, #156] @ (8003f8c <Start_DataAnalysis+0xc0>)
8003eee: f7fc fed9 bl 8000ca4 <MadgwickAHRS_init>
/* Infinite loop */
for(;;)
{
osMessageQueueGet(Q_BMMHandle, &magn_data, NULL, osWaitForever);
8003ef2: 4b27 ldr r3, [pc, #156] @ (8003f90 <Start_DataAnalysis+0xc4>)
8003ef4: 6818 ldr r0, [r3, #0]
8003ef6: f107 011c add.w r1, r7, #28
8003efa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8003efe: 2200 movs r2, #0
8003f00: f00e fc22 bl 8012748 <osMessageQueueGet>
osMessageQueueGet(Q_ICMHandle, &imu_data, NULL, osWaitForever);
8003f04: 4b23 ldr r3, [pc, #140] @ (8003f94 <Start_DataAnalysis+0xc8>)
8003f06: 6818 ldr r0, [r3, #0]
8003f08: f107 012c add.w r1, r7, #44 @ 0x2c
8003f0c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8003f10: 2200 movs r2, #0
8003f12: f00e fc19 bl 8012748 <osMessageQueueGet>
// MadgwickAHRS_update(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz
// imu_data.processed_imu_data[0], imu_data.processed_imu_data[1], imu_data.processed_imu_data[2], // ax, ay, yz
// magn_data.x, magn_data.y, magn_data.z); // mx, my, mz
MadgwickAHRS_update_IMU(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz
8003f16: edd7 7a0e vldr s15, [r7, #56] @ 0x38
8003f1a: ed97 7a0f vldr s14, [r7, #60] @ 0x3c
8003f1e: edd7 6a10 vldr s13, [r7, #64] @ 0x40
8003f22: ed97 6a0b vldr s12, [r7, #44] @ 0x2c
8003f26: edd7 5a0c vldr s11, [r7, #48] @ 0x30
8003f2a: ed97 5a0d vldr s10, [r7, #52] @ 0x34
8003f2e: eef0 2a45 vmov.f32 s5, s10
8003f32: eeb0 2a65 vmov.f32 s4, s11
8003f36: eef0 1a46 vmov.f32 s3, s12
8003f3a: eeb0 1a66 vmov.f32 s2, s13
8003f3e: eef0 0a47 vmov.f32 s1, s14
8003f42: eeb0 0a67 vmov.f32 s0, s15
8003f46: 4811 ldr r0, [pc, #68] @ (8003f8c <Start_DataAnalysis+0xc0>)
8003f48: f7fc fed0 bl 8000cec <MadgwickAHRS_update_IMU>
imu_data.processed_imu_data[0], imu_data.processed_imu_data[1], imu_data.processed_imu_data[2]); // ax, ay, yz)
Quat_Dat.qw = IMUQuat.q[0];
8003f4c: 4b0f ldr r3, [pc, #60] @ (8003f8c <Start_DataAnalysis+0xc0>)
8003f4e: 681b ldr r3, [r3, #0]
8003f50: f8c7 300a str.w r3, [r7, #10]
Quat_Dat.qx = IMUQuat.q[1];
8003f54: 4b0d ldr r3, [pc, #52] @ (8003f8c <Start_DataAnalysis+0xc0>)
8003f56: 685b ldr r3, [r3, #4]
8003f58: f8c7 300e str.w r3, [r7, #14]
Quat_Dat.qy = IMUQuat.q[2];
8003f5c: 4b0b ldr r3, [pc, #44] @ (8003f8c <Start_DataAnalysis+0xc0>)
8003f5e: 689b ldr r3, [r3, #8]
8003f60: f8c7 3012 str.w r3, [r7, #18]
Quat_Dat.qz = IMUQuat.q[3];
8003f64: 4b09 ldr r3, [pc, #36] @ (8003f8c <Start_DataAnalysis+0xc0>)
8003f66: 68db ldr r3, [r3, #12]
8003f68: f8c7 3016 str.w r3, [r7, #22]
CDC_Transmit_FS((uint8_t*)&Quat_Dat, sizeof(Quat_Dat));
8003f6c: f107 0308 add.w r3, r7, #8
8003f70: 2113 movs r1, #19
8003f72: 4618 mov r0, r3
8003f74: f012 ffb6 bl 8016ee4 <CDC_Transmit_FS>
// Quat_Dat.qw, Quat_Dat.qx, Quat_Dat.qy, Quat_Dat.qz);
// CDC_Transmit_FS((uint8_t*)output_buffer, (uint16_t)strlen(output_buffer));
//
// sprintf(output_buffer, "------------\n");
// CDC_Transmit_FS((uint8_t*)output_buffer, (uint16_t)strlen(output_buffer));
osDelay(100);
8003f78: 2064 movs r0, #100 @ 0x64
8003f7a: f00e f8d6 bl 801212a <osDelay>
osMessageQueueGet(Q_BMMHandle, &magn_data, NULL, osWaitForever);
8003f7e: bf00 nop
8003f80: e7b7 b.n 8003ef2 <Start_DataAnalysis+0x26>
8003f82: bf00 nop
8003f84: 3e19999a .word 0x3e19999a
8003f88: 45c80000 .word 0x45c80000
8003f8c: 20000710 .word 0x20000710
8003f90: 2000070c .word 0x2000070c
8003f94: 20000708 .word 0x20000708
08003f98 <Start_ICM45686>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_Start_ICM45686 */
void Start_ICM45686(void *argument)
{
8003f98: b580 push {r7, lr}
8003f9a: b0a4 sub sp, #144 @ 0x90
8003f9c: af00 add r7, sp, #0
8003f9e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Start_ICM45686 */
HAL_StatusTypeDef status;
// char output_buffer[128];
xIMU_Task = osThreadGetId();
8003fa0: f00d ffde bl 8011f60 <osThreadGetId>
8003fa4: 4603 mov r3, r0
8003fa6: 4aa3 ldr r2, [pc, #652] @ (8004234 <Start_ICM45686+0x29c>)
8003fa8: 6013 str r3, [r2, #0]
uint8_t raw_imu_data[15];
int16_t imu_sensor_data[7];
ICM45686_Data processed_data;
ICM45686_HandleTypeDef imu;
imu.hspi = &hspi1;
8003faa: 4ba3 ldr r3, [pc, #652] @ (8004238 <Start_ICM45686+0x2a0>)
8003fac: 61fb str r3, [r7, #28]
imu.GPIO_Port = GPIO_SPI1_IMU_CS_GPIO_Port;
8003fae: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
8003fb2: 623b str r3, [r7, #32]
imu.GPIO_Pin = GPIO_SPI1_IMU_CS_Pin;
8003fb4: 2308 movs r3, #8
8003fb6: 84bb strh r3, [r7, #36] @ 0x24
imu.acc_fs = ICM45686_ACC_FS_4G;
8003fb8: 2330 movs r3, #48 @ 0x30
8003fba: f887 3026 strb.w r3, [r7, #38] @ 0x26
imu.acc_ssf = ICM45686_ACC_SSF[ICM45686_ACC_FS_4G >> 4];
8003fbe: f04f 438c mov.w r3, #1174405120 @ 0x46000000
8003fc2: 62fb str r3, [r7, #44] @ 0x2c
imu.gyro_fs = ICM45686_GYRO_FS_250DPS;
8003fc4: 2340 movs r3, #64 @ 0x40
8003fc6: f887 3027 strb.w r3, [r7, #39] @ 0x27
imu.gyro_ssf = ICM45686_GYRO_SSF[ICM45686_GYRO_FS_250DPS >> 4];
8003fca: 4b9c ldr r3, [pc, #624] @ (800423c <Start_ICM45686+0x2a4>)
8003fcc: 633b str r3, [r7, #48] @ 0x30
imu.odr = ICM45686_ODR_6_4kHz_LN ;
8003fce: 2303 movs r3, #3
8003fd0: f887 3028 strb.w r3, [r7, #40] @ 0x28
uint8_t tx[15] = {0x00};
8003fd4: f107 030c add.w r3, r7, #12
8003fd8: 2200 movs r2, #0
8003fda: 601a str r2, [r3, #0]
8003fdc: 605a str r2, [r3, #4]
8003fde: 609a str r2, [r3, #8]
8003fe0: f8c3 200b str.w r2, [r3, #11]
tx[0] = 0x00 | 0x80;
8003fe4: 2380 movs r3, #128 @ 0x80
8003fe6: 733b strb r3, [r7, #12]
init_icm(&imu);
8003fe8: f107 031c add.w r3, r7, #28
8003fec: 4618 mov r0, r3
8003fee: f000 faab bl 8004548 <init_icm>
for(;;)
{
// imu
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET);
// status = HAL_SPI_TransmitReceive_DMA(&hspi1, tx, raw_imu_data, sizeof(raw_imu_data)); //(&hspi1, tx, raw_imu_data, sizeof(raw_imu_data), 50);
status = read_icm_dma(&imu, tx, raw_imu_data);
8003ff2: f107 0280 add.w r2, r7, #128 @ 0x80
8003ff6: f107 010c add.w r1, r7, #12
8003ffa: f107 031c add.w r3, r7, #28
8003ffe: 4618 mov r0, r3
8004000: f000 fa62 bl 80044c8 <read_icm_dma>
8004004: 4603 mov r3, r0
8004006: f887 308f strb.w r3, [r7, #143] @ 0x8f
if (status != HAL_OK) {
800400a: f897 308f ldrb.w r3, [r7, #143] @ 0x8f
800400e: 2b00 cmp r3, #0
8004010: d005 beq.n 800401e <Start_ICM45686+0x86>
printf("Reading IMU sensordata failed: %d\n", status);
8004012: f897 308f ldrb.w r3, [r7, #143] @ 0x8f
8004016: 4619 mov r1, r3
8004018: 4889 ldr r0, [pc, #548] @ (8004240 <Start_ICM45686+0x2a8>)
800401a: f014 fb73 bl 8018704 <iprintf>
}
imu_sensor_data[0] = (int16_t)(raw_imu_data[1] << 8 | raw_imu_data[2]); // a_x
800401e: f897 3081 ldrb.w r3, [r7, #129] @ 0x81
8004022: b21b sxth r3, r3
8004024: 021b lsls r3, r3, #8
8004026: b21a sxth r2, r3
8004028: f897 3082 ldrb.w r3, [r7, #130] @ 0x82
800402c: b21b sxth r3, r3
800402e: 4313 orrs r3, r2
8004030: b21b sxth r3, r3
8004032: f8a7 3070 strh.w r3, [r7, #112] @ 0x70
imu_sensor_data[1] = (int16_t)(raw_imu_data[3] << 8 | raw_imu_data[4]); // a_y
8004036: f897 3083 ldrb.w r3, [r7, #131] @ 0x83
800403a: b21b sxth r3, r3
800403c: 021b lsls r3, r3, #8
800403e: b21a sxth r2, r3
8004040: f897 3084 ldrb.w r3, [r7, #132] @ 0x84
8004044: b21b sxth r3, r3
8004046: 4313 orrs r3, r2
8004048: b21b sxth r3, r3
800404a: f8a7 3072 strh.w r3, [r7, #114] @ 0x72
imu_sensor_data[2] = (int16_t)(raw_imu_data[5] << 8 | raw_imu_data[6]); // a_z
800404e: f897 3085 ldrb.w r3, [r7, #133] @ 0x85
8004052: b21b sxth r3, r3
8004054: 021b lsls r3, r3, #8
8004056: b21a sxth r2, r3
8004058: f897 3086 ldrb.w r3, [r7, #134] @ 0x86
800405c: b21b sxth r3, r3
800405e: 4313 orrs r3, r2
8004060: b21b sxth r3, r3
8004062: f8a7 3074 strh.w r3, [r7, #116] @ 0x74
imu_sensor_data[3] = (int16_t)(raw_imu_data[7] << 8 | raw_imu_data[8]); // g_x
8004066: f897 3087 ldrb.w r3, [r7, #135] @ 0x87
800406a: b21b sxth r3, r3
800406c: 021b lsls r3, r3, #8
800406e: b21a sxth r2, r3
8004070: f897 3088 ldrb.w r3, [r7, #136] @ 0x88
8004074: b21b sxth r3, r3
8004076: 4313 orrs r3, r2
8004078: b21b sxth r3, r3
800407a: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
imu_sensor_data[4] = (int16_t)(raw_imu_data[9] << 8 | raw_imu_data[10]); // g_y
800407e: f897 3089 ldrb.w r3, [r7, #137] @ 0x89
8004082: b21b sxth r3, r3
8004084: 021b lsls r3, r3, #8
8004086: b21a sxth r2, r3
8004088: f897 308a ldrb.w r3, [r7, #138] @ 0x8a
800408c: b21b sxth r3, r3
800408e: 4313 orrs r3, r2
8004090: b21b sxth r3, r3
8004092: f8a7 3078 strh.w r3, [r7, #120] @ 0x78
imu_sensor_data[5] = (int16_t)(raw_imu_data[11] << 8 | raw_imu_data[12]); // g_z
8004096: f897 308b ldrb.w r3, [r7, #139] @ 0x8b
800409a: b21b sxth r3, r3
800409c: 021b lsls r3, r3, #8
800409e: b21a sxth r2, r3
80040a0: f897 308c ldrb.w r3, [r7, #140] @ 0x8c
80040a4: b21b sxth r3, r3
80040a6: 4313 orrs r3, r2
80040a8: b21b sxth r3, r3
80040aa: f8a7 307a strh.w r3, [r7, #122] @ 0x7a
imu_sensor_data[6] = (int16_t)(raw_imu_data[13] << 8 | raw_imu_data[14]); // t
80040ae: f897 308d ldrb.w r3, [r7, #141] @ 0x8d
80040b2: b21b sxth r3, r3
80040b4: 021b lsls r3, r3, #8
80040b6: b21a sxth r2, r3
80040b8: f897 308e ldrb.w r3, [r7, #142] @ 0x8e
80040bc: b21b sxth r3, r3
80040be: 4313 orrs r3, r2
80040c0: b21b sxth r3, r3
80040c2: f8a7 307c strh.w r3, [r7, #124] @ 0x7c
processed_data.processed_imu_data[0] = (float)imu_sensor_data[0] / (float)imu.acc_fs;
80040c6: f9b7 3070 ldrsh.w r3, [r7, #112] @ 0x70
80040ca: ee07 3a90 vmov s15, r3
80040ce: eef8 6ae7 vcvt.f32.s32 s13, s15
80040d2: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
80040d6: ee07 3a90 vmov s15, r3
80040da: eeb8 7a67 vcvt.f32.u32 s14, s15
80040de: eec6 7a87 vdiv.f32 s15, s13, s14
80040e2: edc7 7a15 vstr s15, [r7, #84] @ 0x54
processed_data.processed_imu_data[1] = (float)imu_sensor_data[1] / (float)imu.acc_fs;
80040e6: f9b7 3072 ldrsh.w r3, [r7, #114] @ 0x72
80040ea: ee07 3a90 vmov s15, r3
80040ee: eef8 6ae7 vcvt.f32.s32 s13, s15
80040f2: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
80040f6: ee07 3a90 vmov s15, r3
80040fa: eeb8 7a67 vcvt.f32.u32 s14, s15
80040fe: eec6 7a87 vdiv.f32 s15, s13, s14
8004102: edc7 7a16 vstr s15, [r7, #88] @ 0x58
processed_data.processed_imu_data[2] = (float)imu_sensor_data[2] / (float)imu.acc_fs;
8004106: f9b7 3074 ldrsh.w r3, [r7, #116] @ 0x74
800410a: ee07 3a90 vmov s15, r3
800410e: eef8 6ae7 vcvt.f32.s32 s13, s15
8004112: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
8004116: ee07 3a90 vmov s15, r3
800411a: eeb8 7a67 vcvt.f32.u32 s14, s15
800411e: eec6 7a87 vdiv.f32 s15, s13, s14
8004122: edc7 7a17 vstr s15, [r7, #92] @ 0x5c
processed_data.processed_imu_data[3] = (float)imu_sensor_data[3] / (float)imu.gyro_ssf;
8004126: f9b7 3076 ldrsh.w r3, [r7, #118] @ 0x76
800412a: ee07 3a90 vmov s15, r3
800412e: eef8 6ae7 vcvt.f32.s32 s13, s15
8004132: ed97 7a0c vldr s14, [r7, #48] @ 0x30
8004136: eec6 7a87 vdiv.f32 s15, s13, s14
800413a: edc7 7a18 vstr s15, [r7, #96] @ 0x60
processed_data.processed_imu_data[4] = (float)imu_sensor_data[4] / (float)imu.gyro_ssf;
800413e: f9b7 3078 ldrsh.w r3, [r7, #120] @ 0x78
8004142: ee07 3a90 vmov s15, r3
8004146: eef8 6ae7 vcvt.f32.s32 s13, s15
800414a: ed97 7a0c vldr s14, [r7, #48] @ 0x30
800414e: eec6 7a87 vdiv.f32 s15, s13, s14
8004152: edc7 7a19 vstr s15, [r7, #100] @ 0x64
processed_data.processed_imu_data[5] = (float)imu_sensor_data[5] / (float)imu.gyro_ssf;
8004156: f9b7 307a ldrsh.w r3, [r7, #122] @ 0x7a
800415a: ee07 3a90 vmov s15, r3
800415e: eef8 6ae7 vcvt.f32.s32 s13, s15
8004162: ed97 7a0c vldr s14, [r7, #48] @ 0x30
8004166: eec6 7a87 vdiv.f32 s15, s13, s14
800416a: edc7 7a1a vstr s15, [r7, #104] @ 0x68
processed_data.processed_imu_data[6] = (float)(imu_sensor_data[6] / 128.0 + 25.0);
800416e: f9b7 307c ldrsh.w r3, [r7, #124] @ 0x7c
8004172: 4618 mov r0, r3
8004174: f7fc f9ae bl 80004d4 <__aeabi_i2d>
8004178: f04f 0200 mov.w r2, #0
800417c: 4b31 ldr r3, [pc, #196] @ (8004244 <Start_ICM45686+0x2ac>)
800417e: f7fc fb3d bl 80007fc <__aeabi_ddiv>
8004182: 4602 mov r2, r0
8004184: 460b mov r3, r1
8004186: 4610 mov r0, r2
8004188: 4619 mov r1, r3
800418a: f04f 0200 mov.w r2, #0
800418e: 4b2e ldr r3, [pc, #184] @ (8004248 <Start_ICM45686+0x2b0>)
8004190: f7fc f854 bl 800023c <__adddf3>
8004194: 4602 mov r2, r0
8004196: 460b mov r3, r1
8004198: 4610 mov r0, r2
800419a: 4619 mov r1, r3
800419c: f7fc fcfc bl 8000b98 <__aeabi_d2f>
80041a0: 4603 mov r3, r0
80041a2: 66fb str r3, [r7, #108] @ 0x6c
if (imu.calibated) {
80041a4: f897 3034 ldrb.w r3, [r7, #52] @ 0x34
80041a8: 2b00 cmp r3, #0
80041aa: d037 beq.n 800421c <Start_ICM45686+0x284>
processed_data.processed_imu_data[0] -= imu.imu_bias[0];
80041ac: ed97 7a15 vldr s14, [r7, #84] @ 0x54
80041b0: edd7 7a0e vldr s15, [r7, #56] @ 0x38
80041b4: ee77 7a67 vsub.f32 s15, s14, s15
80041b8: edc7 7a15 vstr s15, [r7, #84] @ 0x54
processed_data.processed_imu_data[1] -= imu.imu_bias[1];
80041bc: ed97 7a16 vldr s14, [r7, #88] @ 0x58
80041c0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c
80041c4: ee77 7a67 vsub.f32 s15, s14, s15
80041c8: edc7 7a16 vstr s15, [r7, #88] @ 0x58
processed_data.processed_imu_data[2] -= imu.imu_bias[2];
80041cc: ed97 7a17 vldr s14, [r7, #92] @ 0x5c
80041d0: edd7 7a10 vldr s15, [r7, #64] @ 0x40
80041d4: ee77 7a67 vsub.f32 s15, s14, s15
80041d8: edc7 7a17 vstr s15, [r7, #92] @ 0x5c
processed_data.processed_imu_data[3] -= imu.imu_bias[3];
80041dc: ed97 7a18 vldr s14, [r7, #96] @ 0x60
80041e0: edd7 7a11 vldr s15, [r7, #68] @ 0x44
80041e4: ee77 7a67 vsub.f32 s15, s14, s15
80041e8: edc7 7a18 vstr s15, [r7, #96] @ 0x60
processed_data.processed_imu_data[4] -= imu.imu_bias[4];
80041ec: ed97 7a19 vldr s14, [r7, #100] @ 0x64
80041f0: edd7 7a12 vldr s15, [r7, #72] @ 0x48
80041f4: ee77 7a67 vsub.f32 s15, s14, s15
80041f8: edc7 7a19 vstr s15, [r7, #100] @ 0x64
processed_data.processed_imu_data[5] -= imu.imu_bias[5];
80041fc: ed97 7a1a vldr s14, [r7, #104] @ 0x68
8004200: edd7 7a13 vldr s15, [r7, #76] @ 0x4c
8004204: ee77 7a67 vsub.f32 s15, s14, s15
8004208: edc7 7a1a vstr s15, [r7, #104] @ 0x68
processed_data.processed_imu_data[6] -= imu.imu_bias[7];
800420c: ed97 7a1b vldr s14, [r7, #108] @ 0x6c
8004210: edd7 7a15 vldr s15, [r7, #84] @ 0x54
8004214: ee77 7a67 vsub.f32 s15, s14, s15
8004218: edc7 7a1b vstr s15, [r7, #108] @ 0x6c
}
// printf("[0]: %.2f [3]: %.2f [6]: %.2f\n", processed_data.processed_imu_data[0], processed_data.processed_imu_data[3], processed_data.processed_imu_data[6]);
osMessageQueuePut(Q_ICMHandle, &processed_data, 0, 5);
800421c: 4b0b ldr r3, [pc, #44] @ (800424c <Start_ICM45686+0x2b4>)
800421e: 6818 ldr r0, [r3, #0]
8004220: f107 0154 add.w r1, r7, #84 @ 0x54
8004224: 2305 movs r3, #5
8004226: 2200 movs r2, #0
8004228: f00e fa30 bl 801268c <osMessageQueuePut>
osDelay(100);
800422c: 2064 movs r0, #100 @ 0x64
800422e: f00d ff7c bl 801212a <osDelay>
status = read_icm_dma(&imu, tx, raw_imu_data);
8004232: e6de b.n 8003ff2 <Start_ICM45686+0x5a>
8004234: 20000728 .word 0x20000728
8004238: 20000528 .word 0x20000528
800423c: 43030000 .word 0x43030000
8004240: 0801c120 .word 0x0801c120
8004244: 40600000 .word 0x40600000
8004248: 40390000 .word 0x40390000
800424c: 20000708 .word 0x20000708
08004250 <Start_BMM350>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_Start_BMM350 */
void Start_BMM350(void *argument)
{
8004250: b580 push {r7, lr}
8004252: b0b4 sub sp, #208 @ 0xd0
8004254: af00 add r7, sp, #0
8004256: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Start_BMM350 */
// HAL_StatusTypeDef status;
// char output_buffer[128];
xMagn_Task = osThreadGetId();
8004258: f00d fe82 bl 8011f60 <osThreadGetId>
800425c: 4603 mov r3, r0
800425e: 4a1f ldr r2, [pc, #124] @ (80042dc <Start_BMM350+0x8c>)
8004260: 6013 str r3, [r2, #0]
// BMM
struct bmm350_dev dev = {0x00};
8004262: f107 031c add.w r3, r7, #28
8004266: 22b0 movs r2, #176 @ 0xb0
8004268: 2100 movs r1, #0
800426a: 4618 mov r0, r3
800426c: f014 fbb2 bl 80189d4 <memset>
int8_t rslt;
struct bmm350_mag_temp_data mag_data;
osDelay(250);
8004270: 20fa movs r0, #250 @ 0xfa
8004272: f00d ff5a bl 801212a <osDelay>
// struct bmm350_mag_temp_data mag_temp_data;
// struct bmm350_pmu_cmd_status_0 pmu_cmd_stat_0;
// ODR: 200HZ, AVG:
rslt = init_bmm(&dev);
8004276: f107 031c add.w r3, r7, #28
800427a: 4618 mov r0, r3
800427c: f000 faf8 bl 8004870 <init_bmm>
8004280: 4603 mov r3, r0
8004282: f887 30cf strb.w r3, [r7, #207] @ 0xcf
if (rslt != BMM350_OK) {
8004286: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf
800428a: 2b00 cmp r3, #0
800428c: d00b beq.n 80042a6 <Start_BMM350+0x56>
printf("BMM350 initialization failed: %d\n", rslt);
800428e: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf
8004292: 4619 mov r1, r3
8004294: 4812 ldr r0, [pc, #72] @ (80042e0 <Start_BMM350+0x90>)
8004296: f014 fa35 bl 8018704 <iprintf>
printf("Chip id: 0x%02X\n", dev.chip_id);
800429a: f897 3020 ldrb.w r3, [r7, #32]
800429e: 4619 mov r1, r3
80042a0: 4810 ldr r0, [pc, #64] @ (80042e4 <Start_BMM350+0x94>)
80042a2: f014 fa2f bl 8018704 <iprintf>
}
/* Infinite loop */
for(;;)
{
// magnetometer
rslt = bmm350_get_compensated_mag_xyz_temp_data(&mag_data, &dev);
80042a6: f107 021c add.w r2, r7, #28
80042aa: f107 030c add.w r3, r7, #12
80042ae: 4611 mov r1, r2
80042b0: 4618 mov r0, r3
80042b2: f7fd fdea bl 8001e8a <bmm350_get_compensated_mag_xyz_temp_data>
80042b6: 4603 mov r3, r0
80042b8: f887 30cf strb.w r3, [r7, #207] @ 0xcf
// rslt = bmm350_read_uncomp_mag_temp_data(&mag_data, &dev);
if (rslt == BMM350_OK)
80042bc: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf
80042c0: 2b00 cmp r3, #0
80042c2: d107 bne.n 80042d4 <Start_BMM350+0x84>
{
// sprintf(output_buffer, "X: %.2f uT, Y: %.2f uT, Z: %.2f uT, Temp: %.2f C\n",
// mag_data.x, mag_data.y, mag_data.z, mag_data.temperature);
// CDC_Transmit_FS((uint8_t*)output_buffer, (uint16_t)strlen(output_buffer));
osMessageQueuePut(Q_BMMHandle, &mag_data, 0, 5);
80042c4: 4b08 ldr r3, [pc, #32] @ (80042e8 <Start_BMM350+0x98>)
80042c6: 6818 ldr r0, [r3, #0]
80042c8: f107 010c add.w r1, r7, #12
80042cc: 2305 movs r3, #5
80042ce: 2200 movs r2, #0
80042d0: f00e f9dc bl 801268c <osMessageQueuePut>
}
osDelay(100);
80042d4: 2064 movs r0, #100 @ 0x64
80042d6: f00d ff28 bl 801212a <osDelay>
rslt = bmm350_get_compensated_mag_xyz_temp_data(&mag_data, &dev);
80042da: e7e4 b.n 80042a6 <Start_BMM350+0x56>
80042dc: 2000072c .word 0x2000072c
80042e0: 0801c144 .word 0x0801c144
80042e4: 0801c168 .word 0x0801c168
80042e8: 2000070c .word 0x2000070c
080042ec <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
80042ec: b580 push {r7, lr}
80042ee: b082 sub sp, #8
80042f0: af00 add r7, sp, #0
80042f2: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM16)
80042f4: 687b ldr r3, [r7, #4]
80042f6: 681b ldr r3, [r3, #0]
80042f8: 4a04 ldr r2, [pc, #16] @ (800430c <HAL_TIM_PeriodElapsedCallback+0x20>)
80042fa: 4293 cmp r3, r2
80042fc: d101 bne.n 8004302 <HAL_TIM_PeriodElapsedCallback+0x16>
{
HAL_IncTick();
80042fe: f001 f81d bl 800533c <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8004302: bf00 nop
8004304: 3708 adds r7, #8
8004306: 46bd mov sp, r7
8004308: bd80 pop {r7, pc}
800430a: bf00 nop
800430c: 40014400 .word 0x40014400
08004310 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8004310: b480 push {r7}
8004312: af00 add r7, sp, #0
__ASM volatile ("cpsid i" : : : "memory");
8004314: b672 cpsid i
}
8004316: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8004318: bf00 nop
800431a: e7fd b.n 8004318 <Error_Handler+0x8>
0800431c <HAL_SPI_TxRxCpltCallback>:
osThreadId_t xIMU_Task = NULL;
osThreadId_t xMagn_Task = NULL;
//osThreadId_t xData_Task = NULL;
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) {
800431c: b580 push {r7, lr}
800431e: b084 sub sp, #16
8004320: af00 add r7, sp, #0
8004322: 6078 str r0, [r7, #4]
if (hspi->Instance == SPI1) {
8004324: 687b ldr r3, [r7, #4]
8004326: 681b ldr r3, [r3, #0]
8004328: 4a10 ldr r2, [pc, #64] @ (800436c <HAL_SPI_TxRxCpltCallback+0x50>)
800432a: 4293 cmp r3, r2
800432c: d11a bne.n 8004364 <HAL_SPI_TxRxCpltCallback+0x48>
HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
800432e: 2201 movs r2, #1
8004330: 2108 movs r1, #8
8004332: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8004336: f001 fde9 bl 8005f0c <HAL_GPIO_WritePin>
// notify the task that the data is ready
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
800433a: 2300 movs r3, #0
800433c: 60fb str r3, [r7, #12]
vTaskNotifyGiveFromISR(xIMU_Task, &xHigherPriorityTaskWoken);
800433e: 4b0c ldr r3, [pc, #48] @ (8004370 <HAL_SPI_TxRxCpltCallback+0x54>)
8004340: 681b ldr r3, [r3, #0]
8004342: f107 020c add.w r2, r7, #12
8004346: 2100 movs r1, #0
8004348: 4618 mov r0, r3
800434a: f011 f9dd bl 8015708 <vTaskGenericNotifyGiveFromISR>
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
800434e: 68fb ldr r3, [r7, #12]
8004350: 2b00 cmp r3, #0
8004352: d007 beq.n 8004364 <HAL_SPI_TxRxCpltCallback+0x48>
8004354: 4b07 ldr r3, [pc, #28] @ (8004374 <HAL_SPI_TxRxCpltCallback+0x58>)
8004356: f04f 5280 mov.w r2, #268435456 @ 0x10000000
800435a: 601a str r2, [r3, #0]
800435c: f3bf 8f4f dsb sy
8004360: f3bf 8f6f isb sy
}
}
8004364: bf00 nop
8004366: 3710 adds r7, #16
8004368: 46bd mov sp, r7
800436a: bd80 pop {r7, pc}
800436c: 40013000 .word 0x40013000
8004370: 20000728 .word 0x20000728
8004374: e000ed04 .word 0xe000ed04
08004378 <HAL_I2C_MemRxCpltCallback>:
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *I2C_address) {
8004378: b580 push {r7, lr}
800437a: b084 sub sp, #16
800437c: af00 add r7, sp, #0
800437e: 6078 str r0, [r7, #4]
// printf("HAL_I2C_MemRxCpltCallback");
if (I2C_address->Instance == I2C1) {
8004380: 687b ldr r3, [r7, #4]
8004382: 681b ldr r3, [r3, #0]
8004384: 4a0d ldr r2, [pc, #52] @ (80043bc <HAL_I2C_MemRxCpltCallback+0x44>)
8004386: 4293 cmp r3, r2
8004388: d114 bne.n 80043b4 <HAL_I2C_MemRxCpltCallback+0x3c>
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
800438a: 2300 movs r3, #0
800438c: 60fb str r3, [r7, #12]
vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken);
800438e: 4b0c ldr r3, [pc, #48] @ (80043c0 <HAL_I2C_MemRxCpltCallback+0x48>)
8004390: 681b ldr r3, [r3, #0]
8004392: f107 020c add.w r2, r7, #12
8004396: 2100 movs r1, #0
8004398: 4618 mov r0, r3
800439a: f011 f9b5 bl 8015708 <vTaskGenericNotifyGiveFromISR>
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
800439e: 68fb ldr r3, [r7, #12]
80043a0: 2b00 cmp r3, #0
80043a2: d007 beq.n 80043b4 <HAL_I2C_MemRxCpltCallback+0x3c>
80043a4: 4b07 ldr r3, [pc, #28] @ (80043c4 <HAL_I2C_MemRxCpltCallback+0x4c>)
80043a6: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80043aa: 601a str r2, [r3, #0]
80043ac: f3bf 8f4f dsb sy
80043b0: f3bf 8f6f isb sy
}
}
80043b4: bf00 nop
80043b6: 3710 adds r7, #16
80043b8: 46bd mov sp, r7
80043ba: bd80 pop {r7, pc}
80043bc: 40005400 .word 0x40005400
80043c0: 2000072c .word 0x2000072c
80043c4: e000ed04 .word 0xe000ed04
080043c8 <HAL_I2C_MemTxCpltCallback>:
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *I2C_address) {
80043c8: b580 push {r7, lr}
80043ca: b084 sub sp, #16
80043cc: af00 add r7, sp, #0
80043ce: 6078 str r0, [r7, #4]
// printf("HAL_I2C_MemTxCpltCallback");
if (I2C_address->Instance == I2C1) {
80043d0: 687b ldr r3, [r7, #4]
80043d2: 681b ldr r3, [r3, #0]
80043d4: 4a0d ldr r2, [pc, #52] @ (800440c <HAL_I2C_MemTxCpltCallback+0x44>)
80043d6: 4293 cmp r3, r2
80043d8: d114 bne.n 8004404 <HAL_I2C_MemTxCpltCallback+0x3c>
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
80043da: 2300 movs r3, #0
80043dc: 60fb str r3, [r7, #12]
vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken);
80043de: 4b0c ldr r3, [pc, #48] @ (8004410 <HAL_I2C_MemTxCpltCallback+0x48>)
80043e0: 681b ldr r3, [r3, #0]
80043e2: f107 020c add.w r2, r7, #12
80043e6: 2100 movs r1, #0
80043e8: 4618 mov r0, r3
80043ea: f011 f98d bl 8015708 <vTaskGenericNotifyGiveFromISR>
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
80043ee: 68fb ldr r3, [r7, #12]
80043f0: 2b00 cmp r3, #0
80043f2: d007 beq.n 8004404 <HAL_I2C_MemTxCpltCallback+0x3c>
80043f4: 4b07 ldr r3, [pc, #28] @ (8004414 <HAL_I2C_MemTxCpltCallback+0x4c>)
80043f6: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80043fa: 601a str r2, [r3, #0]
80043fc: f3bf 8f4f dsb sy
8004400: f3bf 8f6f isb sy
}
}
8004404: bf00 nop
8004406: 3710 adds r7, #16
8004408: 46bd mov sp, r7
800440a: bd80 pop {r7, pc}
800440c: 40005400 .word 0x40005400
8004410: 2000072c .word 0x2000072c
8004414: e000ed04 .word 0xe000ed04
08004418 <HAL_I2C_ErrorCallback>:
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) {
8004418: b580 push {r7, lr}
800441a: b084 sub sp, #16
800441c: af00 add r7, sp, #0
800441e: 6078 str r0, [r7, #4]
if (hi2c->Instance == I2C1) {
8004420: 687b ldr r3, [r7, #4]
8004422: 681b ldr r3, [r3, #0]
8004424: 4a11 ldr r2, [pc, #68] @ (800446c <HAL_I2C_ErrorCallback+0x54>)
8004426: 4293 cmp r3, r2
8004428: d11c bne.n 8004464 <HAL_I2C_ErrorCallback+0x4c>
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
800442a: 2300 movs r3, #0
800442c: 60fb str r3, [r7, #12]
printf("ErrorCallback: %ld", HAL_I2C_GetError(hi2c));
800442e: 6878 ldr r0, [r7, #4]
8004430: f002 f8d5 bl 80065de <HAL_I2C_GetError>
8004434: 4603 mov r3, r0
8004436: 4619 mov r1, r3
8004438: 480d ldr r0, [pc, #52] @ (8004470 <HAL_I2C_ErrorCallback+0x58>)
800443a: f014 f963 bl 8018704 <iprintf>
vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken);
800443e: 4b0d ldr r3, [pc, #52] @ (8004474 <HAL_I2C_ErrorCallback+0x5c>)
8004440: 681b ldr r3, [r3, #0]
8004442: f107 020c add.w r2, r7, #12
8004446: 2100 movs r1, #0
8004448: 4618 mov r0, r3
800444a: f011 f95d bl 8015708 <vTaskGenericNotifyGiveFromISR>
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
800444e: 68fb ldr r3, [r7, #12]
8004450: 2b00 cmp r3, #0
8004452: d007 beq.n 8004464 <HAL_I2C_ErrorCallback+0x4c>
8004454: 4b08 ldr r3, [pc, #32] @ (8004478 <HAL_I2C_ErrorCallback+0x60>)
8004456: f04f 5280 mov.w r2, #268435456 @ 0x10000000
800445a: 601a str r2, [r3, #0]
800445c: f3bf 8f4f dsb sy
8004460: f3bf 8f6f isb sy
}
}
8004464: bf00 nop
8004466: 3710 adds r7, #16
8004468: 46bd mov sp, r7
800446a: bd80 pop {r7, pc}
800446c: 40005400 .word 0x40005400
8004470: 0801c17c .word 0x0801c17c
8004474: 2000072c .word 0x2000072c
8004478: e000ed04 .word 0xe000ed04
0800447c <read_icm>:
// ICM 45686
HAL_StatusTypeDef read_icm (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint8_t rx[]) {
800447c: b580 push {r7, lr}
800447e: b088 sub sp, #32
8004480: af02 add r7, sp, #8
8004482: 60f8 str r0, [r7, #12]
8004484: 60b9 str r1, [r7, #8]
8004486: 607a str r2, [r7, #4]
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET);
8004488: 68fb ldr r3, [r7, #12]
800448a: 6858 ldr r0, [r3, #4]
800448c: 68fb ldr r3, [r7, #12]
800448e: 891b ldrh r3, [r3, #8]
8004490: 2200 movs r2, #0
8004492: 4619 mov r1, r3
8004494: f001 fd3a bl 8005f0c <HAL_GPIO_WritePin>
HAL_StatusTypeDef status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50);
8004498: 68fb ldr r3, [r7, #12]
800449a: 6818 ldr r0, [r3, #0]
800449c: 2332 movs r3, #50 @ 0x32
800449e: 9300 str r3, [sp, #0]
80044a0: 2304 movs r3, #4
80044a2: 687a ldr r2, [r7, #4]
80044a4: 68b9 ldr r1, [r7, #8]
80044a6: f007 fbdc bl 800bc62 <HAL_SPI_TransmitReceive>
80044aa: 4603 mov r3, r0
80044ac: 75fb strb r3, [r7, #23]
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_SET);
80044ae: 68fb ldr r3, [r7, #12]
80044b0: 6858 ldr r0, [r3, #4]
80044b2: 68fb ldr r3, [r7, #12]
80044b4: 891b ldrh r3, [r3, #8]
80044b6: 2201 movs r2, #1
80044b8: 4619 mov r1, r3
80044ba: f001 fd27 bl 8005f0c <HAL_GPIO_WritePin>
return status;
80044be: 7dfb ldrb r3, [r7, #23]
}
80044c0: 4618 mov r0, r3
80044c2: 3718 adds r7, #24
80044c4: 46bd mov sp, r7
80044c6: bd80 pop {r7, pc}
080044c8 <read_icm_dma>:
HAL_StatusTypeDef read_icm_dma (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint8_t rx[]) {
80044c8: b580 push {r7, lr}
80044ca: b086 sub sp, #24
80044cc: af00 add r7, sp, #0
80044ce: 60f8 str r0, [r7, #12]
80044d0: 60b9 str r1, [r7, #8]
80044d2: 607a str r2, [r7, #4]
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET);
80044d4: 68fb ldr r3, [r7, #12]
80044d6: 6858 ldr r0, [r3, #4]
80044d8: 68fb ldr r3, [r7, #12]
80044da: 891b ldrh r3, [r3, #8]
80044dc: 2200 movs r2, #0
80044de: 4619 mov r1, r3
80044e0: f001 fd14 bl 8005f0c <HAL_GPIO_WritePin>
HAL_StatusTypeDef status = HAL_SPI_TransmitReceive_DMA(imu->hspi, tx, rx, sizeof(rx));
80044e4: 68fb ldr r3, [r7, #12]
80044e6: 6818 ldr r0, [r3, #0]
80044e8: 2304 movs r3, #4
80044ea: 687a ldr r2, [r7, #4]
80044ec: 68b9 ldr r1, [r7, #8]
80044ee: f007 fdd7 bl 800c0a0 <HAL_SPI_TransmitReceive_DMA>
80044f2: 4603 mov r3, r0
80044f4: 75fb strb r3, [r7, #23]
return status;
80044f6: 7dfb ldrb r3, [r7, #23]
}
80044f8: 4618 mov r0, r3
80044fa: 3718 adds r7, #24
80044fc: 46bd mov sp, r7
80044fe: bd80 pop {r7, pc}
08004500 <write_icm>:
HAL_StatusTypeDef write_icm (ICM45686_HandleTypeDef *imu, uint8_t tx[]) {
8004500: b580 push {r7, lr}
8004502: b084 sub sp, #16
8004504: af00 add r7, sp, #0
8004506: 6078 str r0, [r7, #4]
8004508: 6039 str r1, [r7, #0]
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET);
800450a: 687b ldr r3, [r7, #4]
800450c: 6858 ldr r0, [r3, #4]
800450e: 687b ldr r3, [r7, #4]
8004510: 891b ldrh r3, [r3, #8]
8004512: 2200 movs r2, #0
8004514: 4619 mov r1, r3
8004516: f001 fcf9 bl 8005f0c <HAL_GPIO_WritePin>
HAL_StatusTypeDef status = HAL_SPI_Transmit(imu->hspi, tx, sizeof(tx), 50);
800451a: 687b ldr r3, [r7, #4]
800451c: 6818 ldr r0, [r3, #0]
800451e: 2332 movs r3, #50 @ 0x32
8004520: 2204 movs r2, #4
8004522: 6839 ldr r1, [r7, #0]
8004524: f007 fa27 bl 800b976 <HAL_SPI_Transmit>
8004528: 4603 mov r3, r0
800452a: 73fb strb r3, [r7, #15]
HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_SET);
800452c: 687b ldr r3, [r7, #4]
800452e: 6858 ldr r0, [r3, #4]
8004530: 687b ldr r3, [r7, #4]
8004532: 891b ldrh r3, [r3, #8]
8004534: 2201 movs r2, #1
8004536: 4619 mov r1, r3
8004538: f001 fce8 bl 8005f0c <HAL_GPIO_WritePin>
return status;
800453c: 7bfb ldrb r3, [r7, #15]
}
800453e: 4618 mov r0, r3
8004540: 3710 adds r7, #16
8004542: 46bd mov sp, r7
8004544: bd80 pop {r7, pc}
...
08004548 <init_icm>:
void init_icm(ICM45686_HandleTypeDef *imu) {
8004548: b580 push {r7, lr}
800454a: b084 sub sp, #16
800454c: af00 add r7, sp, #0
800454e: 6078 str r0, [r7, #4]
// EDMP???
uint8_t tx[2], rx[2];
HAL_StatusTypeDef status;
printf("Initializing ICM45686\n");
8004550: 4867 ldr r0, [pc, #412] @ (80046f0 <init_icm+0x1a8>)
8004552: f014 f93f bl 80187d4 <puts>
// WHO AM
tx[0] = ICM45686_WHO_AM_I | 0x80;
8004556: 23f2 movs r3, #242 @ 0xf2
8004558: 733b strb r3, [r7, #12]
// HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET);
// status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50);
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
status = read_icm(imu, tx, rx);
800455a: f107 0208 add.w r2, r7, #8
800455e: f107 030c add.w r3, r7, #12
8004562: 4619 mov r1, r3
8004564: 6878 ldr r0, [r7, #4]
8004566: f7ff ff89 bl 800447c <read_icm>
800456a: 4603 mov r3, r0
800456c: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
800456e: 7bfb ldrb r3, [r7, #15]
8004570: 2b00 cmp r3, #0
8004572: d005 beq.n 8004580 <init_icm+0x38>
printf("Error in reading WHO AM I:%d\n", status);
8004574: 7bfb ldrb r3, [r7, #15]
8004576: 4619 mov r1, r3
8004578: 485e ldr r0, [pc, #376] @ (80046f4 <init_icm+0x1ac>)
800457a: f014 f8c3 bl 8018704 <iprintf>
800457e: e004 b.n 800458a <init_icm+0x42>
} else {
printf("WHO AM I (0xE9): 0x%02X \n", rx[1]);
8004580: 7a7b ldrb r3, [r7, #9]
8004582: 4619 mov r1, r3
8004584: 485c ldr r0, [pc, #368] @ (80046f8 <init_icm+0x1b0>)
8004586: f014 f8bd bl 8018704 <iprintf>
}
// acc
tx[0] = ICM45686_ACCEL_CONFIG0;
800458a: 231b movs r3, #27
800458c: 733b strb r3, [r7, #12]
tx[1] = imu->acc_fs | imu->odr;
800458e: 687b ldr r3, [r7, #4]
8004590: 7a9a ldrb r2, [r3, #10]
8004592: 687b ldr r3, [r7, #4]
8004594: 7b1b ldrb r3, [r3, #12]
8004596: 4313 orrs r3, r2
8004598: b2db uxtb r3, r3
800459a: 737b strb r3, [r7, #13]
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET);
// status = HAL_SPI_Transmit(imu->hspi, tx, sizeof(tx), 50);
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
status = write_icm(imu, tx);
800459c: f107 030c add.w r3, r7, #12
80045a0: 4619 mov r1, r3
80045a2: 6878 ldr r0, [r7, #4]
80045a4: f7ff ffac bl 8004500 <write_icm>
80045a8: 4603 mov r3, r0
80045aa: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
80045ac: 7bfb ldrb r3, [r7, #15]
80045ae: 2b00 cmp r3, #0
80045b0: d005 beq.n 80045be <init_icm+0x76>
printf("Error in setting ACCEL_CONFIG0:%d\n", status);
80045b2: 7bfb ldrb r3, [r7, #15]
80045b4: 4619 mov r1, r3
80045b6: 4851 ldr r0, [pc, #324] @ (80046fc <init_icm+0x1b4>)
80045b8: f014 f8a4 bl 8018704 <iprintf>
80045bc: e004 b.n 80045c8 <init_icm+0x80>
} else {
printf("ACCEL_CONFIG0 wrote: 0x%02X \n", tx[1]);
80045be: 7b7b ldrb r3, [r7, #13]
80045c0: 4619 mov r1, r3
80045c2: 484f ldr r0, [pc, #316] @ (8004700 <init_icm+0x1b8>)
80045c4: f014 f89e bl 8018704 <iprintf>
}
tx[0] = ICM45686_ACCEL_CONFIG0 | 0x80;
80045c8: 239b movs r3, #155 @ 0x9b
80045ca: 733b strb r3, [r7, #12]
tx[1] = 0x00;
80045cc: 2300 movs r3, #0
80045ce: 737b strb r3, [r7, #13]
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET);
// status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50);
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
status = read_icm(imu, tx, rx);
80045d0: f107 0208 add.w r2, r7, #8
80045d4: f107 030c add.w r3, r7, #12
80045d8: 4619 mov r1, r3
80045da: 6878 ldr r0, [r7, #4]
80045dc: f7ff ff4e bl 800447c <read_icm>
80045e0: 4603 mov r3, r0
80045e2: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
80045e4: 7bfb ldrb r3, [r7, #15]
80045e6: 2b00 cmp r3, #0
80045e8: d005 beq.n 80045f6 <init_icm+0xae>
printf("Error reading ACCEL_CONFIG0:%d\n", status);
80045ea: 7bfb ldrb r3, [r7, #15]
80045ec: 4619 mov r1, r3
80045ee: 4845 ldr r0, [pc, #276] @ (8004704 <init_icm+0x1bc>)
80045f0: f014 f888 bl 8018704 <iprintf>
80045f4: e004 b.n 8004600 <init_icm+0xb8>
} else {
printf("ACCEL_CONFIG0 read: 0x%02X \n", rx[1]);
80045f6: 7a7b ldrb r3, [r7, #9]
80045f8: 4619 mov r1, r3
80045fa: 4843 ldr r0, [pc, #268] @ (8004708 <init_icm+0x1c0>)
80045fc: f014 f882 bl 8018704 <iprintf>
}
// gyro
tx[0] = ICM45686_GYRO_CONFIG0;
8004600: 231c movs r3, #28
8004602: 733b strb r3, [r7, #12]
tx[1] = imu->gyro_fs | imu->odr;
8004604: 687b ldr r3, [r7, #4]
8004606: 7ada ldrb r2, [r3, #11]
8004608: 687b ldr r3, [r7, #4]
800460a: 7b1b ldrb r3, [r3, #12]
800460c: 4313 orrs r3, r2
800460e: b2db uxtb r3, r3
8004610: 737b strb r3, [r7, #13]
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET);
// status = HAL_SPI_Transmit(imu->hspi, tx, sizeof(tx), 50);
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
status = write_icm(imu, tx);
8004612: f107 030c add.w r3, r7, #12
8004616: 4619 mov r1, r3
8004618: 6878 ldr r0, [r7, #4]
800461a: f7ff ff71 bl 8004500 <write_icm>
800461e: 4603 mov r3, r0
8004620: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
8004622: 7bfb ldrb r3, [r7, #15]
8004624: 2b00 cmp r3, #0
8004626: d005 beq.n 8004634 <init_icm+0xec>
printf("Error in setting GYRO_CONFIG0:%d\n", status);
8004628: 7bfb ldrb r3, [r7, #15]
800462a: 4619 mov r1, r3
800462c: 4837 ldr r0, [pc, #220] @ (800470c <init_icm+0x1c4>)
800462e: f014 f869 bl 8018704 <iprintf>
8004632: e004 b.n 800463e <init_icm+0xf6>
} else {
printf("GYRO_CONFIG0 wrote: 0x%02X \n", tx[1]);
8004634: 7b7b ldrb r3, [r7, #13]
8004636: 4619 mov r1, r3
8004638: 4835 ldr r0, [pc, #212] @ (8004710 <init_icm+0x1c8>)
800463a: f014 f863 bl 8018704 <iprintf>
}
tx[0] = ICM45686_GYRO_CONFIG0 | 0x80;
800463e: 239c movs r3, #156 @ 0x9c
8004640: 733b strb r3, [r7, #12]
tx[1] = 0x00;
8004642: 2300 movs r3, #0
8004644: 737b strb r3, [r7, #13]
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET);
// status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50);
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
status = read_icm(imu, tx, rx);
8004646: f107 0208 add.w r2, r7, #8
800464a: f107 030c add.w r3, r7, #12
800464e: 4619 mov r1, r3
8004650: 6878 ldr r0, [r7, #4]
8004652: f7ff ff13 bl 800447c <read_icm>
8004656: 4603 mov r3, r0
8004658: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
800465a: 7bfb ldrb r3, [r7, #15]
800465c: 2b00 cmp r3, #0
800465e: d005 beq.n 800466c <init_icm+0x124>
printf("Error reading GYRO_CONFIG0:%d\n", status);
8004660: 7bfb ldrb r3, [r7, #15]
8004662: 4619 mov r1, r3
8004664: 482b ldr r0, [pc, #172] @ (8004714 <init_icm+0x1cc>)
8004666: f014 f84d bl 8018704 <iprintf>
800466a: e004 b.n 8004676 <init_icm+0x12e>
} else {
printf("GYRO_CONFIG0 read: 0x%02X \n", rx[1]);
800466c: 7a7b ldrb r3, [r7, #9]
800466e: 4619 mov r1, r3
8004670: 4829 ldr r0, [pc, #164] @ (8004718 <init_icm+0x1d0>)
8004672: f014 f847 bl 8018704 <iprintf>
}
// power settings
tx[0] = ICM45686_PWR_MGMT0;
8004676: 2310 movs r3, #16
8004678: 733b strb r3, [r7, #12]
tx[1] = 0x0F; //0x10 | 0x03;
800467a: 230f movs r3, #15
800467c: 737b strb r3, [r7, #13]
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET);
// status = HAL_SPI_Transmit(imu->hspi, tx, sizeof(tx), 50);
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
status = write_icm(imu, tx);
800467e: f107 030c add.w r3, r7, #12
8004682: 4619 mov r1, r3
8004684: 6878 ldr r0, [r7, #4]
8004686: f7ff ff3b bl 8004500 <write_icm>
800468a: 4603 mov r3, r0
800468c: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
800468e: 7bfb ldrb r3, [r7, #15]
8004690: 2b00 cmp r3, #0
8004692: d005 beq.n 80046a0 <init_icm+0x158>
printf("Error in setting PWR_MGMT0:%d\n", status);
8004694: 7bfb ldrb r3, [r7, #15]
8004696: 4619 mov r1, r3
8004698: 4820 ldr r0, [pc, #128] @ (800471c <init_icm+0x1d4>)
800469a: f014 f833 bl 8018704 <iprintf>
800469e: e004 b.n 80046aa <init_icm+0x162>
} else {
printf("PWR_MGMT0 wrote: 0x%02X \n", tx[1]);
80046a0: 7b7b ldrb r3, [r7, #13]
80046a2: 4619 mov r1, r3
80046a4: 481e ldr r0, [pc, #120] @ (8004720 <init_icm+0x1d8>)
80046a6: f014 f82d bl 8018704 <iprintf>
}
tx[0] = ICM45686_PWR_MGMT0 | 0x80;
80046aa: 2390 movs r3, #144 @ 0x90
80046ac: 733b strb r3, [r7, #12]
tx[1] = 0x00;
80046ae: 2300 movs r3, #0
80046b0: 737b strb r3, [r7, #13]
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET);
// status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50);
// HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET);
status = read_icm(imu, tx, rx);
80046b2: f107 0208 add.w r2, r7, #8
80046b6: f107 030c add.w r3, r7, #12
80046ba: 4619 mov r1, r3
80046bc: 6878 ldr r0, [r7, #4]
80046be: f7ff fedd bl 800447c <read_icm>
80046c2: 4603 mov r3, r0
80046c4: 73fb strb r3, [r7, #15]
if (status != HAL_OK) {
80046c6: 7bfb ldrb r3, [r7, #15]
80046c8: 2b00 cmp r3, #0
80046ca: d005 beq.n 80046d8 <init_icm+0x190>
printf("Error reading PWR_MGMT0:%d\n", status);
80046cc: 7bfb ldrb r3, [r7, #15]
80046ce: 4619 mov r1, r3
80046d0: 4814 ldr r0, [pc, #80] @ (8004724 <init_icm+0x1dc>)
80046d2: f014 f817 bl 8018704 <iprintf>
80046d6: e004 b.n 80046e2 <init_icm+0x19a>
} else {
printf("PWR_MGMT0 read: 0x%02X \n", rx[1]);
80046d8: 7a7b ldrb r3, [r7, #9]
80046da: 4619 mov r1, r3
80046dc: 4812 ldr r0, [pc, #72] @ (8004728 <init_icm+0x1e0>)
80046de: f014 f811 bl 8018704 <iprintf>
}
osDelay(250);
80046e2: 20fa movs r0, #250 @ 0xfa
80046e4: f00d fd21 bl 801212a <osDelay>
}
80046e8: bf00 nop
80046ea: 3710 adds r7, #16
80046ec: 46bd mov sp, r7
80046ee: bd80 pop {r7, pc}
80046f0: 0801c190 .word 0x0801c190
80046f4: 0801c1a8 .word 0x0801c1a8
80046f8: 0801c1c8 .word 0x0801c1c8
80046fc: 0801c1e4 .word 0x0801c1e4
8004700: 0801c208 .word 0x0801c208
8004704: 0801c228 .word 0x0801c228
8004708: 0801c248 .word 0x0801c248
800470c: 0801c268 .word 0x0801c268
8004710: 0801c28c .word 0x0801c28c
8004714: 0801c2ac .word 0x0801c2ac
8004718: 0801c2cc .word 0x0801c2cc
800471c: 0801c2e8 .word 0x0801c2e8
8004720: 0801c308 .word 0x0801c308
8004724: 0801c324 .word 0x0801c324
8004728: 0801c340 .word 0x0801c340
0800472c <bmm_init_DWT>:
imu->imu_bias[6]);
}
// BMM350
void bmm_init_DWT(void){
800472c: b480 push {r7}
800472e: af00 add r7, sp, #0
// Enable trace and debug block (TRCENA)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
8004730: 4b09 ldr r3, [pc, #36] @ (8004758 <bmm_init_DWT+0x2c>)
8004732: 68db ldr r3, [r3, #12]
8004734: 4a08 ldr r2, [pc, #32] @ (8004758 <bmm_init_DWT+0x2c>)
8004736: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800473a: 60d3 str r3, [r2, #12]
// Reset cycle counter
DWT->CYCCNT = 0;
800473c: 4b07 ldr r3, [pc, #28] @ (800475c <bmm_init_DWT+0x30>)
800473e: 2200 movs r2, #0
8004740: 605a str r2, [r3, #4]
// Enable the cycle counter
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
8004742: 4b06 ldr r3, [pc, #24] @ (800475c <bmm_init_DWT+0x30>)
8004744: 681b ldr r3, [r3, #0]
8004746: 4a05 ldr r2, [pc, #20] @ (800475c <bmm_init_DWT+0x30>)
8004748: f043 0301 orr.w r3, r3, #1
800474c: 6013 str r3, [r2, #0]
}
800474e: bf00 nop
8004750: 46bd mov sp, r7
8004752: f85d 7b04 ldr.w r7, [sp], #4
8004756: 4770 bx lr
8004758: e000edf0 .word 0xe000edf0
800475c: e0001000 .word 0xe0001000
08004760 <bmm350_i2c_read>:
BMM350_INTF_RET_TYPE bmm350_i2c_read(uint8_t reg_addr, uint8_t *reg_data, uint32_t length, void *intf_ptr){
8004760: b580 push {r7, lr}
8004762: b088 sub sp, #32
8004764: af02 add r7, sp, #8
8004766: 60b9 str r1, [r7, #8]
8004768: 607a str r2, [r7, #4]
800476a: 603b str r3, [r7, #0]
800476c: 4603 mov r3, r0
800476e: 73fb strb r3, [r7, #15]
// Extract I2C device address from intf_ptr
uint8_t device_addr = *(uint8_t*)intf_ptr;
8004770: 683b ldr r3, [r7, #0]
8004772: 781b ldrb r3, [r3, #0]
8004774: 75fb strb r3, [r7, #23]
// STM32 HAL: Write register address, then read data
// Device address is left-shifted by 1 for STM32 HAL
// if (HAL_I2C_Mem_Read(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, reg_data, length, HAL_I2C_TIMEOUT ) == HAL_OK) {
if (HAL_I2C_Mem_Read_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, reg_data, length) == HAL_OK) {
8004776: 7dfb ldrb r3, [r7, #23]
8004778: b29b uxth r3, r3
800477a: 005b lsls r3, r3, #1
800477c: b299 uxth r1, r3
800477e: 7bfb ldrb r3, [r7, #15]
8004780: b29a uxth r2, r3
8004782: 687b ldr r3, [r7, #4]
8004784: b29b uxth r3, r3
8004786: 9301 str r3, [sp, #4]
8004788: 68bb ldr r3, [r7, #8]
800478a: 9300 str r3, [sp, #0]
800478c: 2301 movs r3, #1
800478e: 480b ldr r0, [pc, #44] @ (80047bc <bmm350_i2c_read+0x5c>)
8004790: f001 fd7a bl 8006288 <HAL_I2C_Mem_Read_DMA>
8004794: 4603 mov r3, r0
8004796: 2b00 cmp r3, #0
8004798: d109 bne.n 80047ae <bmm350_i2c_read+0x4e>
if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) {
800479a: 220a movs r2, #10
800479c: 2101 movs r1, #1
800479e: 2000 movs r0, #0
80047a0: f010 fc2a bl 8014ff8 <ulTaskGenericNotifyTake>
80047a4: 4603 mov r3, r0
80047a6: 2b01 cmp r3, #1
80047a8: d101 bne.n 80047ae <bmm350_i2c_read+0x4e>
return BMM350_INTF_RET_SUCCESS; // 0
80047aa: 2300 movs r3, #0
80047ac: e001 b.n 80047b2 <bmm350_i2c_read+0x52>
}
}
return -1; // Communication failure
80047ae: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
}
80047b2: 4618 mov r0, r3
80047b4: 3718 adds r7, #24
80047b6: 46bd mov sp, r7
80047b8: bd80 pop {r7, pc}
80047ba: bf00 nop
80047bc: 200003b4 .word 0x200003b4
080047c0 <bmm350_i2c_write>:
BMM350_INTF_RET_TYPE bmm350_i2c_write(uint8_t reg_addr, const uint8_t *reg_data, uint32_t length, void *intf_ptr){
80047c0: b580 push {r7, lr}
80047c2: b088 sub sp, #32
80047c4: af02 add r7, sp, #8
80047c6: 60b9 str r1, [r7, #8]
80047c8: 607a str r2, [r7, #4]
80047ca: 603b str r3, [r7, #0]
80047cc: 4603 mov r3, r0
80047ce: 73fb strb r3, [r7, #15]
uint8_t device_addr = *(uint8_t*)intf_ptr;
80047d0: 683b ldr r3, [r7, #0]
80047d2: 781b ldrb r3, [r3, #0]
80047d4: 75fb strb r3, [r7, #23]
// uint8_t rslt = HAL_I2C_Mem_Write_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length);
// printf("rslt write: %d\n", rslt);
// // STM32 HAL: Write register address + data
if (HAL_I2C_Mem_Write_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length) == HAL_OK) {
80047d6: 7dfb ldrb r3, [r7, #23]
80047d8: b29b uxth r3, r3
80047da: 005b lsls r3, r3, #1
80047dc: b299 uxth r1, r3
80047de: 7bfb ldrb r3, [r7, #15]
80047e0: b29a uxth r2, r3
80047e2: 687b ldr r3, [r7, #4]
80047e4: b29b uxth r3, r3
80047e6: 9301 str r3, [sp, #4]
80047e8: 68bb ldr r3, [r7, #8]
80047ea: 9300 str r3, [sp, #0]
80047ec: 2301 movs r3, #1
80047ee: 480b ldr r0, [pc, #44] @ (800481c <bmm350_i2c_write+0x5c>)
80047f0: f001 fc64 bl 80060bc <HAL_I2C_Mem_Write_DMA>
80047f4: 4603 mov r3, r0
80047f6: 2b00 cmp r3, #0
80047f8: d109 bne.n 800480e <bmm350_i2c_write+0x4e>
// if (HAL_I2C_Mem_Write(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length, HAL_I2C_TIMEOUT ) == HAL_OK) {
// if (rslt == HAL_OK) {
if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) {
80047fa: 220a movs r2, #10
80047fc: 2101 movs r1, #1
80047fe: 2000 movs r0, #0
8004800: f010 fbfa bl 8014ff8 <ulTaskGenericNotifyTake>
8004804: 4603 mov r3, r0
8004806: 2b01 cmp r3, #1
8004808: d101 bne.n 800480e <bmm350_i2c_write+0x4e>
return BMM350_INTF_RET_SUCCESS; // 0
800480a: 2300 movs r3, #0
800480c: e001 b.n 8004812 <bmm350_i2c_write+0x52>
}
}
return -1;
800480e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
}
8004812: 4618 mov r0, r3
8004814: 3718 adds r7, #24
8004816: 46bd mov sp, r7
8004818: bd80 pop {r7, pc}
800481a: bf00 nop
800481c: 200003b4 .word 0x200003b4
08004820 <bmm350_delay>:
void bmm350_delay(uint32_t period_us, void *intf_ptr){
8004820: b480 push {r7}
8004822: b085 sub sp, #20
8004824: af00 add r7, sp, #0
8004826: 6078 str r0, [r7, #4]
8004828: 6039 str r1, [r7, #0]
(void)intf_ptr; // Unused
// For STM32, use DWT cycle counter for accurate microsecond delays
uint32_t start = DWT->CYCCNT;
800482a: 4b0e ldr r3, [pc, #56] @ (8004864 <bmm350_delay+0x44>)
800482c: 685b ldr r3, [r3, #4]
800482e: 60fb str r3, [r7, #12]
uint32_t cycles = period_us * (SystemCoreClock / 1000000);
8004830: 4b0d ldr r3, [pc, #52] @ (8004868 <bmm350_delay+0x48>)
8004832: 681b ldr r3, [r3, #0]
8004834: 4a0d ldr r2, [pc, #52] @ (800486c <bmm350_delay+0x4c>)
8004836: fba2 2303 umull r2, r3, r2, r3
800483a: 0c9a lsrs r2, r3, #18
800483c: 687b ldr r3, [r7, #4]
800483e: fb02 f303 mul.w r3, r2, r3
8004842: 60bb str r3, [r7, #8]
while ((DWT->CYCCNT - start) < cycles);
8004844: bf00 nop
8004846: 4b07 ldr r3, [pc, #28] @ (8004864 <bmm350_delay+0x44>)
8004848: 685a ldr r2, [r3, #4]
800484a: 68fb ldr r3, [r7, #12]
800484c: 1ad3 subs r3, r2, r3
800484e: 68ba ldr r2, [r7, #8]
8004850: 429a cmp r2, r3
8004852: d8f8 bhi.n 8004846 <bmm350_delay+0x26>
}
8004854: bf00 nop
8004856: bf00 nop
8004858: 3714 adds r7, #20
800485a: 46bd mov sp, r7
800485c: f85d 7b04 ldr.w r7, [sp], #4
8004860: 4770 bx lr
8004862: bf00 nop
8004864: e0001000 .word 0xe0001000
8004868: 2000000c .word 0x2000000c
800486c: 431bde83 .word 0x431bde83
08004870 <init_bmm>:
// Initialization function
int8_t init_bmm(struct bmm350_dev *dev) {
8004870: b580 push {r7, lr}
8004872: b084 sub sp, #16
8004874: af00 add r7, sp, #0
8004876: 6078 str r0, [r7, #4]
// Static variable to hold I2C device address
// Must be static or global because dev.intf_ptr will point to it
static uint8_t dev_addr = BMM350_I2C_ADSEL_SET_LOW;
// Assign function pointers
dev->read = bmm350_i2c_read;
8004878: 687b ldr r3, [r7, #4]
800487a: 4a23 ldr r2, [pc, #140] @ (8004908 <init_bmm+0x98>)
800487c: 609a str r2, [r3, #8]
dev->write = bmm350_i2c_write;
800487e: 687b ldr r3, [r7, #4]
8004880: 4a22 ldr r2, [pc, #136] @ (800490c <init_bmm+0x9c>)
8004882: 60da str r2, [r3, #12]
dev->delay_us = bmm350_delay;
8004884: 687b ldr r3, [r7, #4]
8004886: 4a22 ldr r2, [pc, #136] @ (8004910 <init_bmm+0xa0>)
8004888: 611a str r2, [r3, #16]
dev->intf_ptr = &dev_addr;
800488a: 687b ldr r3, [r7, #4]
800488c: 4a21 ldr r2, [pc, #132] @ (8004914 <init_bmm+0xa4>)
800488e: 601a str r2, [r3, #0]
printf("Starting up and configuring BMM350\n");
8004890: 4821 ldr r0, [pc, #132] @ (8004918 <init_bmm+0xa8>)
8004892: f013 ff9f bl 80187d4 <puts>
// Initialize BMM350 driver
rslt = bmm350_init(dev);
8004896: 6878 ldr r0, [r7, #4]
8004898: f7fc ffda bl 8001850 <bmm350_init>
800489c: 4603 mov r3, r0
800489e: 73fb strb r3, [r7, #15]
if (rslt != BMM350_OK)
80048a0: f997 300f ldrsb.w r3, [r7, #15]
80048a4: 2b00 cmp r3, #0
80048a6: d002 beq.n 80048ae <init_bmm+0x3e>
{
// Handle error: chip ID mismatch, communication failure, etc.
return rslt;
80048a8: f997 300f ldrsb.w r3, [r7, #15]
80048ac: e027 b.n 80048fe <init_bmm+0x8e>
}
printf("Initialization: %d\n", rslt);
80048ae: f997 300f ldrsb.w r3, [r7, #15]
80048b2: 4619 mov r1, r3
80048b4: 4819 ldr r0, [pc, #100] @ (800491c <init_bmm+0xac>)
80048b6: f013 ff25 bl 8018704 <iprintf>
printf("CHIP_ID (should be 0x33) - Read Register: 0x00 BMM350 Chip ID: 0x%X\n", dev->chip_id);
80048ba: 687b ldr r3, [r7, #4]
80048bc: 791b ldrb r3, [r3, #4]
80048be: 4619 mov r1, r3
80048c0: 4817 ldr r0, [pc, #92] @ (8004920 <init_bmm+0xb0>)
80048c2: f013 ff1f bl 8018704 <iprintf>
// Set powermode, odr and avg
rslt = bmm350_set_powermode(BMM350_NORMAL_MODE, dev);
80048c6: 6879 ldr r1, [r7, #4]
80048c8: 2001 movs r0, #1
80048ca: f7fd f8f0 bl 8001aae <bmm350_set_powermode>
80048ce: 4603 mov r3, r0
80048d0: 73fb strb r3, [r7, #15]
printf("Powermode (%d): %d\n", BMM350_NORMAL_MODE, rslt);
80048d2: f997 300f ldrsb.w r3, [r7, #15]
80048d6: 461a mov r2, r3
80048d8: 2101 movs r1, #1
80048da: 4812 ldr r0, [pc, #72] @ (8004924 <init_bmm+0xb4>)
80048dc: f013 ff12 bl 8018704 <iprintf>
rslt = bmm350_set_odr_performance(BMM350_DATA_RATE_200HZ, BMM350_AVERAGING_2, dev);
80048e0: 687a ldr r2, [r7, #4]
80048e2: 2101 movs r1, #1
80048e4: 2003 movs r0, #3
80048e6: f7fd f934 bl 8001b52 <bmm350_set_odr_performance>
80048ea: 4603 mov r3, r0
80048ec: 73fb strb r3, [r7, #15]
printf("ODR(%d) and AVG(%d): %d\n", BMM350_DATA_RATE_200HZ, BMM350_AVERAGING_2, rslt);
80048ee: f997 300f ldrsb.w r3, [r7, #15]
80048f2: 2201 movs r2, #1
80048f4: 2103 movs r1, #3
80048f6: 480c ldr r0, [pc, #48] @ (8004928 <init_bmm+0xb8>)
80048f8: f013 ff04 bl 8018704 <iprintf>
return BMM350_OK;
80048fc: 2300 movs r3, #0
}
80048fe: 4618 mov r0, r3
8004900: 3710 adds r7, #16
8004902: 46bd mov sp, r7
8004904: bd80 pop {r7, pc}
8004906: bf00 nop
8004908: 08004761 .word 0x08004761
800490c: 080047c1 .word 0x080047c1
8004910: 08004821 .word 0x08004821
8004914: 20000008 .word 0x20000008
8004918: 0801c3ec .word 0x0801c3ec
800491c: 0801c410 .word 0x0801c410
8004920: 0801c424 .word 0x0801c424
8004924: 0801c46c .word 0x0801c46c
8004928: 0801c480 .word 0x0801c480
0800492c <LL_RCC_EnableRTC>:
* @brief Enable RTC
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableRTC(void)
{
800492c: b480 push {r7}
800492e: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
8004930: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8004934: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004938: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800493c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8004940: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
8004944: bf00 nop
8004946: 46bd mov sp, r7
8004948: f85d 7b04 ldr.w r7, [sp], #4
800494c: 4770 bx lr
0800494e <LL_AHB2_GRP1_EnableClock>:
{
800494e: b480 push {r7}
8004950: b085 sub sp, #20
8004952: af00 add r7, sp, #0
8004954: 6078 str r0, [r7, #4]
SET_BIT(RCC->AHB2ENR, Periphs);
8004956: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800495a: 6cda ldr r2, [r3, #76] @ 0x4c
800495c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8004960: 687b ldr r3, [r7, #4]
8004962: 4313 orrs r3, r2
8004964: 64cb str r3, [r1, #76] @ 0x4c
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
8004966: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800496a: 6cda ldr r2, [r3, #76] @ 0x4c
800496c: 687b ldr r3, [r7, #4]
800496e: 4013 ands r3, r2
8004970: 60fb str r3, [r7, #12]
(void)tmpreg;
8004972: 68fb ldr r3, [r7, #12]
}
8004974: bf00 nop
8004976: 3714 adds r7, #20
8004978: 46bd mov sp, r7
800497a: f85d 7b04 ldr.w r7, [sp], #4
800497e: 4770 bx lr
08004980 <LL_AHB3_GRP1_EnableClock>:
* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
* @note (*) Not supported by all the devices
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
{
8004980: b480 push {r7}
8004982: b085 sub sp, #20
8004984: af00 add r7, sp, #0
8004986: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB3ENR, Periphs);
8004988: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800498c: 6d1a ldr r2, [r3, #80] @ 0x50
800498e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8004992: 687b ldr r3, [r7, #4]
8004994: 4313 orrs r3, r2
8004996: 650b str r3, [r1, #80] @ 0x50
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
8004998: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800499c: 6d1a ldr r2, [r3, #80] @ 0x50
800499e: 687b ldr r3, [r7, #4]
80049a0: 4013 ands r3, r2
80049a2: 60fb str r3, [r7, #12]
(void)tmpreg;
80049a4: 68fb ldr r3, [r7, #12]
}
80049a6: bf00 nop
80049a8: 3714 adds r7, #20
80049aa: 46bd mov sp, r7
80049ac: f85d 7b04 ldr.w r7, [sp], #4
80049b0: 4770 bx lr
080049b2 <LL_APB1_GRP1_EnableClock>:
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
* @note (*) Not supported by all the devices
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
{
80049b2: b480 push {r7}
80049b4: b085 sub sp, #20
80049b6: af00 add r7, sp, #0
80049b8: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1ENR1, Periphs);
80049ba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80049be: 6d9a ldr r2, [r3, #88] @ 0x58
80049c0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
80049c4: 687b ldr r3, [r7, #4]
80049c6: 4313 orrs r3, r2
80049c8: 658b str r3, [r1, #88] @ 0x58
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
80049ca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80049ce: 6d9a ldr r2, [r3, #88] @ 0x58
80049d0: 687b ldr r3, [r7, #4]
80049d2: 4013 ands r3, r2
80049d4: 60fb str r3, [r7, #12]
(void)tmpreg;
80049d6: 68fb ldr r3, [r7, #12]
}
80049d8: bf00 nop
80049da: 3714 adds r7, #20
80049dc: 46bd mov sp, r7
80049de: f85d 7b04 ldr.w r7, [sp], #4
80049e2: 4770 bx lr
080049e4 <LL_APB2_GRP1_EnableClock>:
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
* @note (*) Not supported by all the devices
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
{
80049e4: b480 push {r7}
80049e6: b085 sub sp, #20
80049e8: af00 add r7, sp, #0
80049ea: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg;
SET_BIT(RCC->APB2ENR, Periphs);
80049ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80049f0: 6e1a ldr r2, [r3, #96] @ 0x60
80049f2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
80049f6: 687b ldr r3, [r7, #4]
80049f8: 4313 orrs r3, r2
80049fa: 660b str r3, [r1, #96] @ 0x60
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
80049fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8004a00: 6e1a ldr r2, [r3, #96] @ 0x60
8004a02: 687b ldr r3, [r7, #4]
8004a04: 4013 ands r3, r2
8004a06: 60fb str r3, [r7, #12]
(void)tmpreg;
8004a08: 68fb ldr r3, [r7, #12]
}
8004a0a: bf00 nop
8004a0c: 3714 adds r7, #20
8004a0e: 46bd mov sp, r7
8004a10: f85d 7b04 ldr.w r7, [sp], #4
8004a14: 4770 bx lr
08004a16 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8004a16: b580 push {r7, lr}
8004a18: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_HSEM_CLK_ENABLE();
8004a1a: f44f 2000 mov.w r0, #524288 @ 0x80000
8004a1e: f7ff ffaf bl 8004980 <LL_AHB3_GRP1_EnableClock>
HAL_PWREx_EnableVddUSB();
8004a22: f004 ff31 bl 8009888 <HAL_PWREx_EnableVddUSB>
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
8004a26: 2200 movs r2, #0
8004a28: 210f movs r1, #15
8004a2a: f06f 0001 mvn.w r0, #1
8004a2e: f000 fdc9 bl 80055c4 <HAL_NVIC_SetPriority>
/* Peripheral interrupt init */
/* HSEM_IRQn interrupt configuration */
HAL_NVIC_SetPriority(HSEM_IRQn, 5, 0);
8004a32: 2200 movs r2, #0
8004a34: 2105 movs r1, #5
8004a36: 202e movs r0, #46 @ 0x2e
8004a38: f000 fdc4 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(HSEM_IRQn);
8004a3c: 202e movs r0, #46 @ 0x2e
8004a3e: f000 fddb bl 80055f8 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8004a42: bf00 nop
8004a44: bd80 pop {r7, pc}
...
08004a48 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8004a48: b580 push {r7, lr}
8004a4a: b09c sub sp, #112 @ 0x70
8004a4c: af00 add r7, sp, #0
8004a4e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8004a50: f107 035c add.w r3, r7, #92 @ 0x5c
8004a54: 2200 movs r2, #0
8004a56: 601a str r2, [r3, #0]
8004a58: 605a str r2, [r3, #4]
8004a5a: 609a str r2, [r3, #8]
8004a5c: 60da str r2, [r3, #12]
8004a5e: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8004a60: f107 030c add.w r3, r7, #12
8004a64: 2250 movs r2, #80 @ 0x50
8004a66: 2100 movs r1, #0
8004a68: 4618 mov r0, r3
8004a6a: f013 ffb3 bl 80189d4 <memset>
if(hi2c->Instance==I2C1)
8004a6e: 687b ldr r3, [r7, #4]
8004a70: 681b ldr r3, [r3, #0]
8004a72: 4a49 ldr r2, [pc, #292] @ (8004b98 <HAL_I2C_MspInit+0x150>)
8004a74: 4293 cmp r3, r2
8004a76: f040 808b bne.w 8004b90 <HAL_I2C_MspInit+0x148>
/* USER CODE END I2C1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
8004a7a: 2304 movs r3, #4
8004a7c: 60fb str r3, [r7, #12]
PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
8004a7e: f44f 3340 mov.w r3, #196608 @ 0x30000
8004a82: 62fb str r3, [r7, #44] @ 0x2c
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8004a84: f107 030c add.w r3, r7, #12
8004a88: 4618 mov r0, r3
8004a8a: f006 fa6b bl 800af64 <HAL_RCCEx_PeriphCLKConfig>
8004a8e: 4603 mov r3, r0
8004a90: 2b00 cmp r3, #0
8004a92: d001 beq.n 8004a98 <HAL_I2C_MspInit+0x50>
{
Error_Handler();
8004a94: f7ff fc3c bl 8004310 <Error_Handler>
}
__HAL_RCC_GPIOB_CLK_ENABLE();
8004a98: 2002 movs r0, #2
8004a9a: f7ff ff58 bl 800494e <LL_AHB2_GRP1_EnableClock>
/**I2C1 GPIO Configuration
PB8 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
8004a9e: f44f 7340 mov.w r3, #768 @ 0x300
8004aa2: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8004aa4: 2312 movs r3, #18
8004aa6: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004aa8: 2300 movs r3, #0
8004aaa: 667b str r3, [r7, #100] @ 0x64
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8004aac: 2300 movs r3, #0
8004aae: 66bb str r3, [r7, #104] @ 0x68
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
8004ab0: 2304 movs r3, #4
8004ab2: 66fb str r3, [r7, #108] @ 0x6c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8004ab4: f107 035c add.w r3, r7, #92 @ 0x5c
8004ab8: 4619 mov r1, r3
8004aba: 4838 ldr r0, [pc, #224] @ (8004b9c <HAL_I2C_MspInit+0x154>)
8004abc: f001 f8b6 bl 8005c2c <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
8004ac0: f44f 1000 mov.w r0, #2097152 @ 0x200000
8004ac4: f7ff ff75 bl 80049b2 <LL_APB1_GRP1_EnableClock>
/* I2C1 DMA Init */
/* I2C1_TX Init */
hdma_i2c1_tx.Instance = DMA1_Channel3;
8004ac8: 4b35 ldr r3, [pc, #212] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004aca: 4a36 ldr r2, [pc, #216] @ (8004ba4 <HAL_I2C_MspInit+0x15c>)
8004acc: 601a str r2, [r3, #0]
hdma_i2c1_tx.Init.Request = DMA_REQUEST_I2C1_TX;
8004ace: 4b34 ldr r3, [pc, #208] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004ad0: 220b movs r2, #11
8004ad2: 605a str r2, [r3, #4]
hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
8004ad4: 4b32 ldr r3, [pc, #200] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004ad6: 2210 movs r2, #16
8004ad8: 609a str r2, [r3, #8]
hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
8004ada: 4b31 ldr r3, [pc, #196] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004adc: 2200 movs r2, #0
8004ade: 60da str r2, [r3, #12]
hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE;
8004ae0: 4b2f ldr r3, [pc, #188] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004ae2: 2280 movs r2, #128 @ 0x80
8004ae4: 611a str r2, [r3, #16]
hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
8004ae6: 4b2e ldr r3, [pc, #184] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004ae8: 2200 movs r2, #0
8004aea: 615a str r2, [r3, #20]
hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
8004aec: 4b2c ldr r3, [pc, #176] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004aee: 2200 movs r2, #0
8004af0: 619a str r2, [r3, #24]
hdma_i2c1_tx.Init.Mode = DMA_NORMAL;
8004af2: 4b2b ldr r3, [pc, #172] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004af4: 2200 movs r2, #0
8004af6: 61da str r2, [r3, #28]
hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_HIGH;
8004af8: 4b29 ldr r3, [pc, #164] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004afa: f44f 5200 mov.w r2, #8192 @ 0x2000
8004afe: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_i2c1_tx) != HAL_OK)
8004b00: 4827 ldr r0, [pc, #156] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004b02: f000 fdb1 bl 8005668 <HAL_DMA_Init>
8004b06: 4603 mov r3, r0
8004b08: 2b00 cmp r3, #0
8004b0a: d001 beq.n 8004b10 <HAL_I2C_MspInit+0xc8>
{
Error_Handler();
8004b0c: f7ff fc00 bl 8004310 <Error_Handler>
}
__HAL_LINKDMA(hi2c,hdmatx,hdma_i2c1_tx);
8004b10: 687b ldr r3, [r7, #4]
8004b12: 4a23 ldr r2, [pc, #140] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004b14: 639a str r2, [r3, #56] @ 0x38
8004b16: 4a22 ldr r2, [pc, #136] @ (8004ba0 <HAL_I2C_MspInit+0x158>)
8004b18: 687b ldr r3, [r7, #4]
8004b1a: 6293 str r3, [r2, #40] @ 0x28
/* I2C1_RX Init */
hdma_i2c1_rx.Instance = DMA1_Channel4;
8004b1c: 4b22 ldr r3, [pc, #136] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b1e: 4a23 ldr r2, [pc, #140] @ (8004bac <HAL_I2C_MspInit+0x164>)
8004b20: 601a str r2, [r3, #0]
hdma_i2c1_rx.Init.Request = DMA_REQUEST_I2C1_RX;
8004b22: 4b21 ldr r3, [pc, #132] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b24: 220a movs r2, #10
8004b26: 605a str r2, [r3, #4]
hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
8004b28: 4b1f ldr r3, [pc, #124] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b2a: 2200 movs r2, #0
8004b2c: 609a str r2, [r3, #8]
hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
8004b2e: 4b1e ldr r3, [pc, #120] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b30: 2200 movs r2, #0
8004b32: 60da str r2, [r3, #12]
hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE;
8004b34: 4b1c ldr r3, [pc, #112] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b36: 2280 movs r2, #128 @ 0x80
8004b38: 611a str r2, [r3, #16]
hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
8004b3a: 4b1b ldr r3, [pc, #108] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b3c: 2200 movs r2, #0
8004b3e: 615a str r2, [r3, #20]
hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
8004b40: 4b19 ldr r3, [pc, #100] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b42: 2200 movs r2, #0
8004b44: 619a str r2, [r3, #24]
hdma_i2c1_rx.Init.Mode = DMA_NORMAL;
8004b46: 4b18 ldr r3, [pc, #96] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b48: 2200 movs r2, #0
8004b4a: 61da str r2, [r3, #28]
hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_HIGH;
8004b4c: 4b16 ldr r3, [pc, #88] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b4e: f44f 5200 mov.w r2, #8192 @ 0x2000
8004b52: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_i2c1_rx) != HAL_OK)
8004b54: 4814 ldr r0, [pc, #80] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b56: f000 fd87 bl 8005668 <HAL_DMA_Init>
8004b5a: 4603 mov r3, r0
8004b5c: 2b00 cmp r3, #0
8004b5e: d001 beq.n 8004b64 <HAL_I2C_MspInit+0x11c>
{
Error_Handler();
8004b60: f7ff fbd6 bl 8004310 <Error_Handler>
}
__HAL_LINKDMA(hi2c,hdmarx,hdma_i2c1_rx);
8004b64: 687b ldr r3, [r7, #4]
8004b66: 4a10 ldr r2, [pc, #64] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b68: 63da str r2, [r3, #60] @ 0x3c
8004b6a: 4a0f ldr r2, [pc, #60] @ (8004ba8 <HAL_I2C_MspInit+0x160>)
8004b6c: 687b ldr r3, [r7, #4]
8004b6e: 6293 str r3, [r2, #40] @ 0x28
/* I2C1 interrupt Init */
HAL_NVIC_SetPriority(I2C1_EV_IRQn, 5, 0);
8004b70: 2200 movs r2, #0
8004b72: 2105 movs r1, #5
8004b74: 201e movs r0, #30
8004b76: f000 fd25 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
8004b7a: 201e movs r0, #30
8004b7c: f000 fd3c bl 80055f8 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(I2C1_ER_IRQn, 5, 0);
8004b80: 2200 movs r2, #0
8004b82: 2105 movs r1, #5
8004b84: 201f movs r0, #31
8004b86: f000 fd1d bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
8004b8a: 201f movs r0, #31
8004b8c: f000 fd34 bl 80055f8 <HAL_NVIC_EnableIRQ>
/* USER CODE END I2C1_MspInit 1 */
}
}
8004b90: bf00 nop
8004b92: 3770 adds r7, #112 @ 0x70
8004b94: 46bd mov sp, r7
8004b96: bd80 pop {r7, pc}
8004b98: 40005400 .word 0x40005400
8004b9c: 48000400 .word 0x48000400
8004ba0: 20000408 .word 0x20000408
8004ba4: 40020030 .word 0x40020030
8004ba8: 20000468 .word 0x20000468
8004bac: 40020044 .word 0x40020044
08004bb0 <HAL_IPCC_MspInit>:
* This function configures the hardware resources used in this example
* @param hipcc: IPCC handle pointer
* @retval None
*/
void HAL_IPCC_MspInit(IPCC_HandleTypeDef* hipcc)
{
8004bb0: b580 push {r7, lr}
8004bb2: b082 sub sp, #8
8004bb4: af00 add r7, sp, #0
8004bb6: 6078 str r0, [r7, #4]
if(hipcc->Instance==IPCC)
8004bb8: 687b ldr r3, [r7, #4]
8004bba: 681b ldr r3, [r3, #0]
8004bbc: 4a0d ldr r2, [pc, #52] @ (8004bf4 <HAL_IPCC_MspInit+0x44>)
8004bbe: 4293 cmp r3, r2
8004bc0: d113 bne.n 8004bea <HAL_IPCC_MspInit+0x3a>
{
/* USER CODE BEGIN IPCC_MspInit 0 */
/* USER CODE END IPCC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_IPCC_CLK_ENABLE();
8004bc2: f44f 1080 mov.w r0, #1048576 @ 0x100000
8004bc6: f7ff fedb bl 8004980 <LL_AHB3_GRP1_EnableClock>
/* IPCC interrupt Init */
HAL_NVIC_SetPriority(IPCC_C1_RX_IRQn, 5, 0);
8004bca: 2200 movs r2, #0
8004bcc: 2105 movs r1, #5
8004bce: 202c movs r0, #44 @ 0x2c
8004bd0: f000 fcf8 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
8004bd4: 202c movs r0, #44 @ 0x2c
8004bd6: f000 fd0f bl 80055f8 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(IPCC_C1_TX_IRQn, 5, 0);
8004bda: 2200 movs r2, #0
8004bdc: 2105 movs r1, #5
8004bde: 202d movs r0, #45 @ 0x2d
8004be0: f000 fcf0 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
8004be4: 202d movs r0, #45 @ 0x2d
8004be6: f000 fd07 bl 80055f8 <HAL_NVIC_EnableIRQ>
/* USER CODE END IPCC_MspInit 1 */
}
}
8004bea: bf00 nop
8004bec: 3708 adds r7, #8
8004bee: 46bd mov sp, r7
8004bf0: bd80 pop {r7, pc}
8004bf2: bf00 nop
8004bf4: 58000c00 .word 0x58000c00
08004bf8 <HAL_RTC_MspInit>:
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
8004bf8: b580 push {r7, lr}
8004bfa: b096 sub sp, #88 @ 0x58
8004bfc: af00 add r7, sp, #0
8004bfe: 6078 str r0, [r7, #4]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8004c00: f107 0308 add.w r3, r7, #8
8004c04: 2250 movs r2, #80 @ 0x50
8004c06: 2100 movs r1, #0
8004c08: 4618 mov r0, r3
8004c0a: f013 fee3 bl 80189d4 <memset>
if(hrtc->Instance==RTC)
8004c0e: 687b ldr r3, [r7, #4]
8004c10: 681b ldr r3, [r3, #0]
8004c12: 4a13 ldr r2, [pc, #76] @ (8004c60 <HAL_RTC_MspInit+0x68>)
8004c14: 4293 cmp r3, r2
8004c16: d11f bne.n 8004c58 <HAL_RTC_MspInit+0x60>
/* USER CODE END RTC_MspInit 0 */
/** Enable access to the backup domain
*/
HAL_PWR_EnableBkUpAccess();
8004c18: f004 fe18 bl 800984c <HAL_PWR_EnableBkUpAccess>
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
8004c1c: f44f 6300 mov.w r3, #2048 @ 0x800
8004c20: 60bb str r3, [r7, #8]
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
8004c22: f44f 7300 mov.w r3, #512 @ 0x200
8004c26: 64bb str r3, [r7, #72] @ 0x48
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8004c28: f107 0308 add.w r3, r7, #8
8004c2c: 4618 mov r0, r3
8004c2e: f006 f999 bl 800af64 <HAL_RCCEx_PeriphCLKConfig>
8004c32: 4603 mov r3, r0
8004c34: 2b00 cmp r3, #0
8004c36: d001 beq.n 8004c3c <HAL_RTC_MspInit+0x44>
{
Error_Handler();
8004c38: f7ff fb6a bl 8004310 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE();
8004c3c: f7ff fe76 bl 800492c <LL_RCC_EnableRTC>
__HAL_RCC_RTCAPB_CLK_ENABLE();
8004c40: f44f 6080 mov.w r0, #1024 @ 0x400
8004c44: f7ff feb5 bl 80049b2 <LL_APB1_GRP1_EnableClock>
/* RTC interrupt Init */
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 5, 0);
8004c48: 2200 movs r2, #0
8004c4a: 2105 movs r1, #5
8004c4c: 2003 movs r0, #3
8004c4e: f000 fcb9 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
8004c52: 2003 movs r0, #3
8004c54: f000 fcd0 bl 80055f8 <HAL_NVIC_EnableIRQ>
/* USER CODE END RTC_MspInit 1 */
}
}
8004c58: bf00 nop
8004c5a: 3758 adds r7, #88 @ 0x58
8004c5c: 46bd mov sp, r7
8004c5e: bd80 pop {r7, pc}
8004c60: 40002800 .word 0x40002800
08004c64 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8004c64: b580 push {r7, lr}
8004c66: b088 sub sp, #32
8004c68: af00 add r7, sp, #0
8004c6a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8004c6c: f107 030c add.w r3, r7, #12
8004c70: 2200 movs r2, #0
8004c72: 601a str r2, [r3, #0]
8004c74: 605a str r2, [r3, #4]
8004c76: 609a str r2, [r3, #8]
8004c78: 60da str r2, [r3, #12]
8004c7a: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
8004c7c: 687b ldr r3, [r7, #4]
8004c7e: 681b ldr r3, [r3, #0]
8004c80: 4a5a ldr r2, [pc, #360] @ (8004dec <HAL_SPI_MspInit+0x188>)
8004c82: 4293 cmp r3, r2
8004c84: d16c bne.n 8004d60 <HAL_SPI_MspInit+0xfc>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
8004c86: f44f 5080 mov.w r0, #4096 @ 0x1000
8004c8a: f7ff feab bl 80049e4 <LL_APB2_GRP1_EnableClock>
__HAL_RCC_GPIOA_CLK_ENABLE();
8004c8e: 2001 movs r0, #1
8004c90: f7ff fe5d bl 800494e <LL_AHB2_GRP1_EnableClock>
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = SPI1_IMU_SCK_Pin|SPI1_IMU_MISO_Pin|SPI1_IMU_MOSI_Pin;
8004c94: 23e0 movs r3, #224 @ 0xe0
8004c96: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004c98: 2302 movs r3, #2
8004c9a: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004c9c: 2300 movs r3, #0
8004c9e: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8004ca0: 2302 movs r3, #2
8004ca2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8004ca4: 2305 movs r3, #5
8004ca6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8004ca8: f107 030c add.w r3, r7, #12
8004cac: 4619 mov r1, r3
8004cae: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8004cb2: f000 ffbb bl 8005c2c <HAL_GPIO_Init>
/* SPI1 DMA Init */
/* SPI1_TX Init */
hdma_spi1_tx.Instance = DMA1_Channel1;
8004cb6: 4b4e ldr r3, [pc, #312] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004cb8: 4a4e ldr r2, [pc, #312] @ (8004df4 <HAL_SPI_MspInit+0x190>)
8004cba: 601a str r2, [r3, #0]
hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX;
8004cbc: 4b4c ldr r3, [pc, #304] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004cbe: 2207 movs r2, #7
8004cc0: 605a str r2, [r3, #4]
hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
8004cc2: 4b4b ldr r3, [pc, #300] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004cc4: 2210 movs r2, #16
8004cc6: 609a str r2, [r3, #8]
hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
8004cc8: 4b49 ldr r3, [pc, #292] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004cca: 2200 movs r2, #0
8004ccc: 60da str r2, [r3, #12]
hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
8004cce: 4b48 ldr r3, [pc, #288] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004cd0: 2280 movs r2, #128 @ 0x80
8004cd2: 611a str r2, [r3, #16]
hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
8004cd4: 4b46 ldr r3, [pc, #280] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004cd6: 2200 movs r2, #0
8004cd8: 615a str r2, [r3, #20]
hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
8004cda: 4b45 ldr r3, [pc, #276] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004cdc: 2200 movs r2, #0
8004cde: 619a str r2, [r3, #24]
hdma_spi1_tx.Init.Mode = DMA_NORMAL;
8004ce0: 4b43 ldr r3, [pc, #268] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004ce2: 2200 movs r2, #0
8004ce4: 61da str r2, [r3, #28]
hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH;
8004ce6: 4b42 ldr r3, [pc, #264] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004ce8: f44f 5200 mov.w r2, #8192 @ 0x2000
8004cec: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
8004cee: 4840 ldr r0, [pc, #256] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004cf0: f000 fcba bl 8005668 <HAL_DMA_Init>
8004cf4: 4603 mov r3, r0
8004cf6: 2b00 cmp r3, #0
8004cf8: d001 beq.n 8004cfe <HAL_SPI_MspInit+0x9a>
{
Error_Handler();
8004cfa: f7ff fb09 bl 8004310 <Error_Handler>
}
__HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx);
8004cfe: 687b ldr r3, [r7, #4]
8004d00: 4a3b ldr r2, [pc, #236] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004d02: 655a str r2, [r3, #84] @ 0x54
8004d04: 4a3a ldr r2, [pc, #232] @ (8004df0 <HAL_SPI_MspInit+0x18c>)
8004d06: 687b ldr r3, [r7, #4]
8004d08: 6293 str r3, [r2, #40] @ 0x28
/* SPI1_RX Init */
hdma_spi1_rx.Instance = DMA1_Channel2;
8004d0a: 4b3b ldr r3, [pc, #236] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d0c: 4a3b ldr r2, [pc, #236] @ (8004dfc <HAL_SPI_MspInit+0x198>)
8004d0e: 601a str r2, [r3, #0]
hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX;
8004d10: 4b39 ldr r3, [pc, #228] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d12: 2206 movs r2, #6
8004d14: 605a str r2, [r3, #4]
hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
8004d16: 4b38 ldr r3, [pc, #224] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d18: 2200 movs r2, #0
8004d1a: 609a str r2, [r3, #8]
hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
8004d1c: 4b36 ldr r3, [pc, #216] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d1e: 2200 movs r2, #0
8004d20: 60da str r2, [r3, #12]
hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
8004d22: 4b35 ldr r3, [pc, #212] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d24: 2280 movs r2, #128 @ 0x80
8004d26: 611a str r2, [r3, #16]
hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
8004d28: 4b33 ldr r3, [pc, #204] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d2a: 2200 movs r2, #0
8004d2c: 615a str r2, [r3, #20]
hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
8004d2e: 4b32 ldr r3, [pc, #200] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d30: 2200 movs r2, #0
8004d32: 619a str r2, [r3, #24]
hdma_spi1_rx.Init.Mode = DMA_NORMAL;
8004d34: 4b30 ldr r3, [pc, #192] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d36: 2200 movs r2, #0
8004d38: 61da str r2, [r3, #28]
hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
8004d3a: 4b2f ldr r3, [pc, #188] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d3c: f44f 5200 mov.w r2, #8192 @ 0x2000
8004d40: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
8004d42: 482d ldr r0, [pc, #180] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d44: f000 fc90 bl 8005668 <HAL_DMA_Init>
8004d48: 4603 mov r3, r0
8004d4a: 2b00 cmp r3, #0
8004d4c: d001 beq.n 8004d52 <HAL_SPI_MspInit+0xee>
{
Error_Handler();
8004d4e: f7ff fadf bl 8004310 <Error_Handler>
}
__HAL_LINKDMA(hspi,hdmarx,hdma_spi1_rx);
8004d52: 687b ldr r3, [r7, #4]
8004d54: 4a28 ldr r2, [pc, #160] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d56: 659a str r2, [r3, #88] @ 0x58
8004d58: 4a27 ldr r2, [pc, #156] @ (8004df8 <HAL_SPI_MspInit+0x194>)
8004d5a: 687b ldr r3, [r7, #4]
8004d5c: 6293 str r3, [r2, #40] @ 0x28
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
}
8004d5e: e040 b.n 8004de2 <HAL_SPI_MspInit+0x17e>
else if(hspi->Instance==SPI2)
8004d60: 687b ldr r3, [r7, #4]
8004d62: 681b ldr r3, [r3, #0]
8004d64: 4a26 ldr r2, [pc, #152] @ (8004e00 <HAL_SPI_MspInit+0x19c>)
8004d66: 4293 cmp r3, r2
8004d68: d13b bne.n 8004de2 <HAL_SPI_MspInit+0x17e>
__HAL_RCC_SPI2_CLK_ENABLE();
8004d6a: f44f 4080 mov.w r0, #16384 @ 0x4000
8004d6e: f7ff fe20 bl 80049b2 <LL_APB1_GRP1_EnableClock>
__HAL_RCC_GPIOC_CLK_ENABLE();
8004d72: 2004 movs r0, #4
8004d74: f7ff fdeb bl 800494e <LL_AHB2_GRP1_EnableClock>
__HAL_RCC_GPIOA_CLK_ENABLE();
8004d78: 2001 movs r0, #1
8004d7a: f7ff fde8 bl 800494e <LL_AHB2_GRP1_EnableClock>
GPIO_InitStruct.Pin = SPI2_SD_MOSI_Pin;
8004d7e: 2302 movs r3, #2
8004d80: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004d82: 2302 movs r3, #2
8004d84: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004d86: 2300 movs r3, #0
8004d88: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004d8a: 2303 movs r3, #3
8004d8c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF3_SPI2;
8004d8e: 2303 movs r3, #3
8004d90: 61fb str r3, [r7, #28]
HAL_GPIO_Init(SPI2_SD_MOSI_GPIO_Port, &GPIO_InitStruct);
8004d92: f107 030c add.w r3, r7, #12
8004d96: 4619 mov r1, r3
8004d98: 481a ldr r0, [pc, #104] @ (8004e04 <HAL_SPI_MspInit+0x1a0>)
8004d9a: f000 ff47 bl 8005c2c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = SPI2_SD_MISO_Pin;
8004d9e: 2304 movs r3, #4
8004da0: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004da2: 2302 movs r3, #2
8004da4: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004da6: 2300 movs r3, #0
8004da8: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004daa: 2303 movs r3, #3
8004dac: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8004dae: 2305 movs r3, #5
8004db0: 61fb str r3, [r7, #28]
HAL_GPIO_Init(SPI2_SD_MISO_GPIO_Port, &GPIO_InitStruct);
8004db2: f107 030c add.w r3, r7, #12
8004db6: 4619 mov r1, r3
8004db8: 4812 ldr r0, [pc, #72] @ (8004e04 <HAL_SPI_MspInit+0x1a0>)
8004dba: f000 ff37 bl 8005c2c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = SPI2_SD_SCK_Pin;
8004dbe: f44f 7300 mov.w r3, #512 @ 0x200
8004dc2: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004dc4: 2302 movs r3, #2
8004dc6: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004dc8: 2300 movs r3, #0
8004dca: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004dcc: 2303 movs r3, #3
8004dce: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8004dd0: 2305 movs r3, #5
8004dd2: 61fb str r3, [r7, #28]
HAL_GPIO_Init(SPI2_SD_SCK_GPIO_Port, &GPIO_InitStruct);
8004dd4: f107 030c add.w r3, r7, #12
8004dd8: 4619 mov r1, r3
8004dda: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8004dde: f000 ff25 bl 8005c2c <HAL_GPIO_Init>
}
8004de2: bf00 nop
8004de4: 3720 adds r7, #32
8004de6: 46bd mov sp, r7
8004de8: bd80 pop {r7, pc}
8004dea: bf00 nop
8004dec: 40013000 .word 0x40013000
8004df0: 200005f0 .word 0x200005f0
8004df4: 40020008 .word 0x40020008
8004df8: 20000650 .word 0x20000650
8004dfc: 4002001c .word 0x4002001c
8004e00: 40003800 .word 0x40003800
8004e04: 48000800 .word 0x48000800
08004e08 <HAL_TIM_PWM_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{
8004e08: b580 push {r7, lr}
8004e0a: b082 sub sp, #8
8004e0c: af00 add r7, sp, #0
8004e0e: 6078 str r0, [r7, #4]
if(htim_pwm->Instance==TIM2)
8004e10: 687b ldr r3, [r7, #4]
8004e12: 681b ldr r3, [r3, #0]
8004e14: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004e18: d102 bne.n 8004e20 <HAL_TIM_PWM_MspInit+0x18>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8004e1a: 2001 movs r0, #1
8004e1c: f7ff fdc9 bl 80049b2 <LL_APB1_GRP1_EnableClock>
/* USER CODE END TIM2_MspInit 1 */
}
}
8004e20: bf00 nop
8004e22: 3708 adds r7, #8
8004e24: 46bd mov sp, r7
8004e26: bd80 pop {r7, pc}
08004e28 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8004e28: b580 push {r7, lr}
8004e2a: b088 sub sp, #32
8004e2c: af00 add r7, sp, #0
8004e2e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8004e30: f107 030c add.w r3, r7, #12
8004e34: 2200 movs r2, #0
8004e36: 601a str r2, [r3, #0]
8004e38: 605a str r2, [r3, #4]
8004e3a: 609a str r2, [r3, #8]
8004e3c: 60da str r2, [r3, #12]
8004e3e: 611a str r2, [r3, #16]
if(htim->Instance==TIM2)
8004e40: 687b ldr r3, [r7, #4]
8004e42: 681b ldr r3, [r3, #0]
8004e44: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004e48: d113 bne.n 8004e72 <HAL_TIM_MspPostInit+0x4a>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8004e4a: 2001 movs r0, #1
8004e4c: f7ff fd7f bl 800494e <LL_AHB2_GRP1_EnableClock>
/**TIM2 GPIO Configuration
PA0 ------> TIM2_CH1
PA1 ------> TIM2_CH2
PA2 ------> TIM2_CH3
*/
GPIO_InitStruct.Pin = GPIO_CONNECT_LED_Pin|GPIO_STATUS_LED_Pin|GPIO_DEBUG_LED_Pin;
8004e50: 2307 movs r3, #7
8004e52: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004e54: 2302 movs r3, #2
8004e56: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004e58: 2300 movs r3, #0
8004e5a: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8004e5c: 2300 movs r3, #0
8004e5e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
8004e60: 2301 movs r3, #1
8004e62: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8004e64: f107 030c add.w r3, r7, #12
8004e68: 4619 mov r1, r3
8004e6a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8004e6e: f000 fedd bl 8005c2c <HAL_GPIO_Init>
/* USER CODE BEGIN TIM2_MspPostInit 1 */
/* USER CODE END TIM2_MspPostInit 1 */
}
}
8004e72: bf00 nop
8004e74: 3720 adds r7, #32
8004e76: 46bd mov sp, r7
8004e78: bd80 pop {r7, pc}
08004e7a <LL_APB2_GRP1_EnableClock>:
{
8004e7a: b480 push {r7}
8004e7c: b085 sub sp, #20
8004e7e: af00 add r7, sp, #0
8004e80: 6078 str r0, [r7, #4]
SET_BIT(RCC->APB2ENR, Periphs);
8004e82: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8004e86: 6e1a ldr r2, [r3, #96] @ 0x60
8004e88: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8004e8c: 687b ldr r3, [r7, #4]
8004e8e: 4313 orrs r3, r2
8004e90: 660b str r3, [r1, #96] @ 0x60
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
8004e92: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8004e96: 6e1a ldr r2, [r3, #96] @ 0x60
8004e98: 687b ldr r3, [r7, #4]
8004e9a: 4013 ands r3, r2
8004e9c: 60fb str r3, [r7, #12]
(void)tmpreg;
8004e9e: 68fb ldr r3, [r7, #12]
}
8004ea0: bf00 nop
8004ea2: 3714 adds r7, #20
8004ea4: 46bd mov sp, r7
8004ea6: f85d 7b04 ldr.w r7, [sp], #4
8004eaa: 4770 bx lr
08004eac <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8004eac: b580 push {r7, lr}
8004eae: b08e sub sp, #56 @ 0x38
8004eb0: af00 add r7, sp, #0
8004eb2: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
8004eb4: 2300 movs r3, #0
8004eb6: 633b str r3, [r7, #48] @ 0x30
uint32_t uwPrescalerValue = 0;
8004eb8: 2300 movs r3, #0
8004eba: 62fb str r3, [r7, #44] @ 0x2c
uint32_t pFLatency;
HAL_StatusTypeDef status = HAL_OK;
8004ebc: 2300 movs r3, #0
8004ebe: f887 3037 strb.w r3, [r7, #55] @ 0x37
/*Configure the TIM16 IRQ priority */
HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority ,0);
8004ec2: 2200 movs r2, #0
8004ec4: 6879 ldr r1, [r7, #4]
8004ec6: 2019 movs r0, #25
8004ec8: f000 fb7c bl 80055c4 <HAL_NVIC_SetPriority>
/* Enable the TIM16 global Interrupt */
HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
8004ecc: 2019 movs r0, #25
8004ece: f000 fb93 bl 80055f8 <HAL_NVIC_EnableIRQ>
/* Enable TIM16 clock */
__HAL_RCC_TIM16_CLK_ENABLE();
8004ed2: f44f 3000 mov.w r0, #131072 @ 0x20000
8004ed6: f7ff ffd0 bl 8004e7a <LL_APB2_GRP1_EnableClock>
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8004eda: f107 020c add.w r2, r7, #12
8004ede: f107 0310 add.w r3, r7, #16
8004ee2: 4611 mov r1, r2
8004ee4: 4618 mov r0, r3
8004ee6: f005 fdab bl 800aa40 <HAL_RCC_GetClockConfig>
/* Compute TIM16 clock */
uwTimclock = HAL_RCC_GetPCLK2Freq();
8004eea: f005 fd93 bl 800aa14 <HAL_RCC_GetPCLK2Freq>
8004eee: 6338 str r0, [r7, #48] @ 0x30
/* Compute the prescaler value to have TIM16 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
8004ef0: 6b3b ldr r3, [r7, #48] @ 0x30
8004ef2: 4a21 ldr r2, [pc, #132] @ (8004f78 <HAL_InitTick+0xcc>)
8004ef4: fba2 2303 umull r2, r3, r2, r3
8004ef8: 0c9b lsrs r3, r3, #18
8004efa: 3b01 subs r3, #1
8004efc: 62fb str r3, [r7, #44] @ 0x2c
/* Initialize TIM16 */
htim16.Instance = TIM16;
8004efe: 4b1f ldr r3, [pc, #124] @ (8004f7c <HAL_InitTick+0xd0>)
8004f00: 4a1f ldr r2, [pc, #124] @ (8004f80 <HAL_InitTick+0xd4>)
8004f02: 601a str r2, [r3, #0]
* Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base.
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
* ClockDivision = 0
* Counter direction = Up
*/
htim16.Init.Period = (1000000U / 1000U) - 1U;
8004f04: 4b1d ldr r3, [pc, #116] @ (8004f7c <HAL_InitTick+0xd0>)
8004f06: f240 32e7 movw r2, #999 @ 0x3e7
8004f0a: 60da str r2, [r3, #12]
htim16.Init.Prescaler = uwPrescalerValue;
8004f0c: 4a1b ldr r2, [pc, #108] @ (8004f7c <HAL_InitTick+0xd0>)
8004f0e: 6afb ldr r3, [r7, #44] @ 0x2c
8004f10: 6053 str r3, [r2, #4]
htim16.Init.ClockDivision = 0;
8004f12: 4b1a ldr r3, [pc, #104] @ (8004f7c <HAL_InitTick+0xd0>)
8004f14: 2200 movs r2, #0
8004f16: 611a str r2, [r3, #16]
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
8004f18: 4b18 ldr r3, [pc, #96] @ (8004f7c <HAL_InitTick+0xd0>)
8004f1a: 2200 movs r2, #0
8004f1c: 609a str r2, [r3, #8]
status = HAL_TIM_Base_Init(&htim16);
8004f1e: 4817 ldr r0, [pc, #92] @ (8004f7c <HAL_InitTick+0xd0>)
8004f20: f007 fd00 bl 800c924 <HAL_TIM_Base_Init>
8004f24: 4603 mov r3, r0
8004f26: f887 3037 strb.w r3, [r7, #55] @ 0x37
if (status == HAL_OK)
8004f2a: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
8004f2e: 2b00 cmp r3, #0
8004f30: d11b bne.n 8004f6a <HAL_InitTick+0xbe>
/* Register callback */
HAL_TIM_RegisterCallback(&htim16, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim16);
8004f32: 4812 ldr r0, [pc, #72] @ (8004f7c <HAL_InitTick+0xd0>)
8004f34: f007 fd58 bl 800c9e8 <HAL_TIM_Base_Start_IT>
8004f38: 4603 mov r3, r0
8004f3a: f887 3037 strb.w r3, [r7, #55] @ 0x37
if (status == HAL_OK)
8004f3e: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
8004f42: 2b00 cmp r3, #0
8004f44: d111 bne.n 8004f6a <HAL_InitTick+0xbe>
{
/* Enable the TIM16 global Interrupt */
HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
8004f46: 2019 movs r0, #25
8004f48: f000 fb56 bl 80055f8 <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8004f4c: 687b ldr r3, [r7, #4]
8004f4e: 2b0f cmp r3, #15
8004f50: d808 bhi.n 8004f64 <HAL_InitTick+0xb8>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority, 0U);
8004f52: 2200 movs r2, #0
8004f54: 6879 ldr r1, [r7, #4]
8004f56: 2019 movs r0, #25
8004f58: f000 fb34 bl 80055c4 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8004f5c: 4a09 ldr r2, [pc, #36] @ (8004f84 <HAL_InitTick+0xd8>)
8004f5e: 687b ldr r3, [r7, #4]
8004f60: 6013 str r3, [r2, #0]
8004f62: e002 b.n 8004f6a <HAL_InitTick+0xbe>
}
else
{
status = HAL_ERROR;
8004f64: 2301 movs r3, #1
8004f66: f887 3037 strb.w r3, [r7, #55] @ 0x37
}
}
}
/* Return function status */
return status;
8004f6a: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
}
8004f6e: 4618 mov r0, r3
8004f70: 3738 adds r7, #56 @ 0x38
8004f72: 46bd mov sp, r7
8004f74: bd80 pop {r7, pc}
8004f76: bf00 nop
8004f78: 431bde83 .word 0x431bde83
8004f7c: 20000730 .word 0x20000730
8004f80: 40014400 .word 0x40014400
8004f84: 20000010 .word 0x20000010
08004f88 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8004f88: b480 push {r7}
8004f8a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8004f8c: bf00 nop
8004f8e: e7fd b.n 8004f8c <NMI_Handler+0x4>
08004f90 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8004f90: b480 push {r7}
8004f92: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8004f94: bf00 nop
8004f96: e7fd b.n 8004f94 <HardFault_Handler+0x4>
08004f98 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8004f98: b480 push {r7}
8004f9a: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8004f9c: bf00 nop
8004f9e: e7fd b.n 8004f9c <MemManage_Handler+0x4>
08004fa0 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8004fa0: b480 push {r7}
8004fa2: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8004fa4: bf00 nop
8004fa6: e7fd b.n 8004fa4 <BusFault_Handler+0x4>
08004fa8 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8004fa8: b480 push {r7}
8004faa: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8004fac: bf00 nop
8004fae: e7fd b.n 8004fac <UsageFault_Handler+0x4>
08004fb0 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8004fb0: b480 push {r7}
8004fb2: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8004fb4: bf00 nop
8004fb6: 46bd mov sp, r7
8004fb8: f85d 7b04 ldr.w r7, [sp], #4
8004fbc: 4770 bx lr
08004fbe <RTC_WKUP_IRQHandler>:
/**
* @brief This function handles RTC wake-up interrupt through EXTI line 19.
*/
void RTC_WKUP_IRQHandler(void)
{
8004fbe: b580 push {r7, lr}
8004fc0: af00 add r7, sp, #0
/* USER CODE BEGIN RTC_WKUP_IRQn 0 */
/* USER CODE END RTC_WKUP_IRQn 0 */
HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc);
8004fc2: f7fe f917 bl 80031f4 <HW_TS_RTC_Wakeup_Handler>
/* USER CODE BEGIN RTC_WKUP_IRQn 1 */
/* USER CODE END RTC_WKUP_IRQn 1 */
}
8004fc6: bf00 nop
8004fc8: bd80 pop {r7, pc}
...
08004fcc <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel1 global interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
8004fcc: b580 push {r7, lr}
8004fce: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_spi1_tx);
8004fd0: 4802 ldr r0, [pc, #8] @ (8004fdc <DMA1_Channel1_IRQHandler+0x10>)
8004fd2: f000 fccb bl 800596c <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
8004fd6: bf00 nop
8004fd8: bd80 pop {r7, pc}
8004fda: bf00 nop
8004fdc: 200005f0 .word 0x200005f0
08004fe0 <DMA1_Channel2_IRQHandler>:
/**
* @brief This function handles DMA1 channel2 global interrupt.
*/
void DMA1_Channel2_IRQHandler(void)
{
8004fe0: b580 push {r7, lr}
8004fe2: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
/* USER CODE END DMA1_Channel2_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_spi1_rx);
8004fe4: 4802 ldr r0, [pc, #8] @ (8004ff0 <DMA1_Channel2_IRQHandler+0x10>)
8004fe6: f000 fcc1 bl 800596c <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
/* USER CODE END DMA1_Channel2_IRQn 1 */
}
8004fea: bf00 nop
8004fec: bd80 pop {r7, pc}
8004fee: bf00 nop
8004ff0: 20000650 .word 0x20000650
08004ff4 <DMA1_Channel3_IRQHandler>:
/**
* @brief This function handles DMA1 channel3 global interrupt.
*/
void DMA1_Channel3_IRQHandler(void)
{
8004ff4: b580 push {r7, lr}
8004ff6: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
/* USER CODE END DMA1_Channel3_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_i2c1_tx);
8004ff8: 4802 ldr r0, [pc, #8] @ (8005004 <DMA1_Channel3_IRQHandler+0x10>)
8004ffa: f000 fcb7 bl 800596c <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
/* USER CODE END DMA1_Channel3_IRQn 1 */
}
8004ffe: bf00 nop
8005000: bd80 pop {r7, pc}
8005002: bf00 nop
8005004: 20000408 .word 0x20000408
08005008 <DMA1_Channel4_IRQHandler>:
/**
* @brief This function handles DMA1 channel4 global interrupt.
*/
void DMA1_Channel4_IRQHandler(void)
{
8005008: b580 push {r7, lr}
800500a: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
/* USER CODE END DMA1_Channel4_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_i2c1_rx);
800500c: 4802 ldr r0, [pc, #8] @ (8005018 <DMA1_Channel4_IRQHandler+0x10>)
800500e: f000 fcad bl 800596c <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
/* USER CODE END DMA1_Channel4_IRQn 1 */
}
8005012: bf00 nop
8005014: bd80 pop {r7, pc}
8005016: bf00 nop
8005018: 20000468 .word 0x20000468
0800501c <USB_LP_IRQHandler>:
/**
* @brief This function handles USB low priority interrupt, USB wake-up interrupt through EXTI line 28.
*/
void USB_LP_IRQHandler(void)
{
800501c: b580 push {r7, lr}
800501e: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_IRQn 0 */
/* USER CODE END USB_LP_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_FS);
8005020: 4802 ldr r0, [pc, #8] @ (800502c <USB_LP_IRQHandler+0x10>)
8005022: f002 ffc1 bl 8007fa8 <HAL_PCD_IRQHandler>
/* USER CODE BEGIN USB_LP_IRQn 1 */
/* USER CODE END USB_LP_IRQn 1 */
}
8005026: bf00 nop
8005028: bd80 pop {r7, pc}
800502a: bf00 nop
800502c: 200135f8 .word 0x200135f8
08005030 <TIM1_UP_TIM16_IRQHandler>:
/**
* @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
*/
void TIM1_UP_TIM16_IRQHandler(void)
{
8005030: b580 push {r7, lr}
8005032: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
/* USER CODE END TIM1_UP_TIM16_IRQn 0 */
HAL_TIM_IRQHandler(&htim16);
8005034: 4802 ldr r0, [pc, #8] @ (8005040 <TIM1_UP_TIM16_IRQHandler+0x10>)
8005036: f007 fd7c bl 800cb32 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
/* USER CODE END TIM1_UP_TIM16_IRQn 1 */
}
800503a: bf00 nop
800503c: bd80 pop {r7, pc}
800503e: bf00 nop
8005040: 20000730 .word 0x20000730
08005044 <I2C1_EV_IRQHandler>:
/**
* @brief This function handles I2C1 event interrupt.
*/
void I2C1_EV_IRQHandler(void)
{
8005044: b580 push {r7, lr}
8005046: af00 add r7, sp, #0
/* USER CODE BEGIN I2C1_EV_IRQn 0 */
/* USER CODE END I2C1_EV_IRQn 0 */
HAL_I2C_EV_IRQHandler(&hi2c1);
8005048: 4802 ldr r0, [pc, #8] @ (8005054 <I2C1_EV_IRQHandler+0x10>)
800504a: f001 fa03 bl 8006454 <HAL_I2C_EV_IRQHandler>
/* USER CODE BEGIN I2C1_EV_IRQn 1 */
/* USER CODE END I2C1_EV_IRQn 1 */
}
800504e: bf00 nop
8005050: bd80 pop {r7, pc}
8005052: bf00 nop
8005054: 200003b4 .word 0x200003b4
08005058 <I2C1_ER_IRQHandler>:
/**
* @brief This function handles I2C1 error interrupt.
*/
void I2C1_ER_IRQHandler(void)
{
8005058: b580 push {r7, lr}
800505a: af00 add r7, sp, #0
/* USER CODE BEGIN I2C1_ER_IRQn 0 */
/* USER CODE END I2C1_ER_IRQn 0 */
HAL_I2C_ER_IRQHandler(&hi2c1);
800505c: 4802 ldr r0, [pc, #8] @ (8005068 <I2C1_ER_IRQHandler+0x10>)
800505e: f001 fa13 bl 8006488 <HAL_I2C_ER_IRQHandler>
/* USER CODE BEGIN I2C1_ER_IRQn 1 */
/* USER CODE END I2C1_ER_IRQn 1 */
}
8005062: bf00 nop
8005064: bd80 pop {r7, pc}
8005066: bf00 nop
8005068: 200003b4 .word 0x200003b4
0800506c <IPCC_C1_RX_IRQHandler>:
/**
* @brief This function handles IPCC RX occupied interrupt.
*/
void IPCC_C1_RX_IRQHandler(void)
{
800506c: b580 push {r7, lr}
800506e: af00 add r7, sp, #0
/* USER CODE BEGIN IPCC_C1_RX_IRQn 0 */
/* USER CODE END IPCC_C1_RX_IRQn 0 */
HAL_IPCC_RX_IRQHandler(&hipcc);
8005070: f011 fce4 bl 8016a3c <HW_IPCC_Rx_Handler>
/* USER CODE BEGIN IPCC_C1_RX_IRQn 1 */
/* USER CODE END IPCC_C1_RX_IRQn 1 */
}
8005074: bf00 nop
8005076: bd80 pop {r7, pc}
08005078 <IPCC_C1_TX_IRQHandler>:
/**
* @brief This function handles IPCC TX free interrupt.
*/
void IPCC_C1_TX_IRQHandler(void)
{
8005078: b580 push {r7, lr}
800507a: af00 add r7, sp, #0
/* USER CODE BEGIN IPCC_C1_TX_IRQn 0 */
/* USER CODE END IPCC_C1_TX_IRQn 0 */
HAL_IPCC_TX_IRQHandler(&hipcc);
800507c: f011 fd14 bl 8016aa8 <HW_IPCC_Tx_Handler>
/* USER CODE BEGIN IPCC_C1_TX_IRQn 1 */
/* USER CODE END IPCC_C1_TX_IRQn 1 */
}
8005080: bf00 nop
8005082: bd80 pop {r7, pc}
08005084 <HSEM_IRQHandler>:
/**
* @brief This function handles HSEM global interrupt.
*/
void HSEM_IRQHandler(void)
{
8005084: b580 push {r7, lr}
8005086: af00 add r7, sp, #0
/* USER CODE BEGIN HSEM_IRQn 0 */
/* USER CODE END HSEM_IRQn 0 */
HAL_HSEM_IRQHandler();
8005088: f000 ff58 bl 8005f3c <HAL_HSEM_IRQHandler>
/* USER CODE BEGIN HSEM_IRQn 1 */
/* USER CODE END HSEM_IRQn 1 */
}
800508c: bf00 nop
800508e: bd80 pop {r7, pc}
08005090 <_getpid>:
void initialise_monitor_handles()
{
}
int _getpid(void)
{
8005090: b480 push {r7}
8005092: af00 add r7, sp, #0
return 1;
8005094: 2301 movs r3, #1
}
8005096: 4618 mov r0, r3
8005098: 46bd mov sp, r7
800509a: f85d 7b04 ldr.w r7, [sp], #4
800509e: 4770 bx lr
080050a0 <_kill>:
int _kill(int pid, int sig)
{
80050a0: b580 push {r7, lr}
80050a2: b082 sub sp, #8
80050a4: af00 add r7, sp, #0
80050a6: 6078 str r0, [r7, #4]
80050a8: 6039 str r1, [r7, #0]
(void)pid;
(void)sig;
errno = EINVAL;
80050aa: f013 fce5 bl 8018a78 <__errno>
80050ae: 4603 mov r3, r0
80050b0: 2216 movs r2, #22
80050b2: 601a str r2, [r3, #0]
return -1;
80050b4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
}
80050b8: 4618 mov r0, r3
80050ba: 3708 adds r7, #8
80050bc: 46bd mov sp, r7
80050be: bd80 pop {r7, pc}
080050c0 <_exit>:
void _exit (int status)
{
80050c0: b580 push {r7, lr}
80050c2: b082 sub sp, #8
80050c4: af00 add r7, sp, #0
80050c6: 6078 str r0, [r7, #4]
_kill(status, -1);
80050c8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
80050cc: 6878 ldr r0, [r7, #4]
80050ce: f7ff ffe7 bl 80050a0 <_kill>
while (1) {} /* Make sure we hang here */
80050d2: bf00 nop
80050d4: e7fd b.n 80050d2 <_exit+0x12>
080050d6 <_read>:
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
80050d6: b580 push {r7, lr}
80050d8: b086 sub sp, #24
80050da: af00 add r7, sp, #0
80050dc: 60f8 str r0, [r7, #12]
80050de: 60b9 str r1, [r7, #8]
80050e0: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
80050e2: 2300 movs r3, #0
80050e4: 617b str r3, [r7, #20]
80050e6: e00a b.n 80050fe <_read+0x28>
{
*ptr++ = __io_getchar();
80050e8: f3af 8000 nop.w
80050ec: 4601 mov r1, r0
80050ee: 68bb ldr r3, [r7, #8]
80050f0: 1c5a adds r2, r3, #1
80050f2: 60ba str r2, [r7, #8]
80050f4: b2ca uxtb r2, r1
80050f6: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
80050f8: 697b ldr r3, [r7, #20]
80050fa: 3301 adds r3, #1
80050fc: 617b str r3, [r7, #20]
80050fe: 697a ldr r2, [r7, #20]
8005100: 687b ldr r3, [r7, #4]
8005102: 429a cmp r2, r3
8005104: dbf0 blt.n 80050e8 <_read+0x12>
}
return len;
8005106: 687b ldr r3, [r7, #4]
}
8005108: 4618 mov r0, r3
800510a: 3718 adds r7, #24
800510c: 46bd mov sp, r7
800510e: bd80 pop {r7, pc}
08005110 <_close>:
}
return len;
}
int _close(int file)
{
8005110: b480 push {r7}
8005112: b083 sub sp, #12
8005114: af00 add r7, sp, #0
8005116: 6078 str r0, [r7, #4]
(void)file;
return -1;
8005118: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
}
800511c: 4618 mov r0, r3
800511e: 370c adds r7, #12
8005120: 46bd mov sp, r7
8005122: f85d 7b04 ldr.w r7, [sp], #4
8005126: 4770 bx lr
08005128 <_fstat>:
int _fstat(int file, struct stat *st)
{
8005128: b480 push {r7}
800512a: b083 sub sp, #12
800512c: af00 add r7, sp, #0
800512e: 6078 str r0, [r7, #4]
8005130: 6039 str r1, [r7, #0]
(void)file;
st->st_mode = S_IFCHR;
8005132: 683b ldr r3, [r7, #0]
8005134: f44f 5200 mov.w r2, #8192 @ 0x2000
8005138: 605a str r2, [r3, #4]
return 0;
800513a: 2300 movs r3, #0
}
800513c: 4618 mov r0, r3
800513e: 370c adds r7, #12
8005140: 46bd mov sp, r7
8005142: f85d 7b04 ldr.w r7, [sp], #4
8005146: 4770 bx lr
08005148 <_isatty>:
int _isatty(int file)
{
8005148: b480 push {r7}
800514a: b083 sub sp, #12
800514c: af00 add r7, sp, #0
800514e: 6078 str r0, [r7, #4]
(void)file;
return 1;
8005150: 2301 movs r3, #1
}
8005152: 4618 mov r0, r3
8005154: 370c adds r7, #12
8005156: 46bd mov sp, r7
8005158: f85d 7b04 ldr.w r7, [sp], #4
800515c: 4770 bx lr
0800515e <_lseek>:
int _lseek(int file, int ptr, int dir)
{
800515e: b480 push {r7}
8005160: b085 sub sp, #20
8005162: af00 add r7, sp, #0
8005164: 60f8 str r0, [r7, #12]
8005166: 60b9 str r1, [r7, #8]
8005168: 607a str r2, [r7, #4]
(void)file;
(void)ptr;
(void)dir;
return 0;
800516a: 2300 movs r3, #0
}
800516c: 4618 mov r0, r3
800516e: 3714 adds r7, #20
8005170: 46bd mov sp, r7
8005172: f85d 7b04 ldr.w r7, [sp], #4
8005176: 4770 bx lr
08005178 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8005178: b580 push {r7, lr}
800517a: b086 sub sp, #24
800517c: af00 add r7, sp, #0
800517e: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8005180: 4a14 ldr r2, [pc, #80] @ (80051d4 <_sbrk+0x5c>)
8005182: 4b15 ldr r3, [pc, #84] @ (80051d8 <_sbrk+0x60>)
8005184: 1ad3 subs r3, r2, r3
8005186: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8005188: 697b ldr r3, [r7, #20]
800518a: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
800518c: 4b13 ldr r3, [pc, #76] @ (80051dc <_sbrk+0x64>)
800518e: 681b ldr r3, [r3, #0]
8005190: 2b00 cmp r3, #0
8005192: d102 bne.n 800519a <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8005194: 4b11 ldr r3, [pc, #68] @ (80051dc <_sbrk+0x64>)
8005196: 4a12 ldr r2, [pc, #72] @ (80051e0 <_sbrk+0x68>)
8005198: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
800519a: 4b10 ldr r3, [pc, #64] @ (80051dc <_sbrk+0x64>)
800519c: 681a ldr r2, [r3, #0]
800519e: 687b ldr r3, [r7, #4]
80051a0: 4413 add r3, r2
80051a2: 693a ldr r2, [r7, #16]
80051a4: 429a cmp r2, r3
80051a6: d207 bcs.n 80051b8 <_sbrk+0x40>
{
errno = ENOMEM;
80051a8: f013 fc66 bl 8018a78 <__errno>
80051ac: 4603 mov r3, r0
80051ae: 220c movs r2, #12
80051b0: 601a str r2, [r3, #0]
return (void *)-1;
80051b2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
80051b6: e009 b.n 80051cc <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
80051b8: 4b08 ldr r3, [pc, #32] @ (80051dc <_sbrk+0x64>)
80051ba: 681b ldr r3, [r3, #0]
80051bc: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
80051be: 4b07 ldr r3, [pc, #28] @ (80051dc <_sbrk+0x64>)
80051c0: 681a ldr r2, [r3, #0]
80051c2: 687b ldr r3, [r7, #4]
80051c4: 4413 add r3, r2
80051c6: 4a05 ldr r2, [pc, #20] @ (80051dc <_sbrk+0x64>)
80051c8: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
80051ca: 68fb ldr r3, [r7, #12]
}
80051cc: 4618 mov r0, r3
80051ce: 3718 adds r7, #24
80051d0: 46bd mov sp, r7
80051d2: bd80 pop {r7, pc}
80051d4: 20030000 .word 0x20030000
80051d8: 00000400 .word 0x00000400
80051dc: 2000077c .word 0x2000077c
80051e0: 20013c48 .word 0x20013c48
080051e4 <SystemInit>:
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
80051e4: b480 push {r7}
80051e6: af00 add r7, sp, #0
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif /* USER_VECT_TAB_ADDRESS */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */
80051e8: 4b24 ldr r3, [pc, #144] @ (800527c <SystemInit+0x98>)
80051ea: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80051ee: 4a23 ldr r2, [pc, #140] @ (800527c <SystemInit+0x98>)
80051f0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80051f4: f8c2 3088 str.w r3, [r2, #136] @ 0x88
#endif /* FPU */
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC->CR |= RCC_CR_MSION;
80051f8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80051fc: 681b ldr r3, [r3, #0]
80051fe: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8005202: f043 0301 orr.w r3, r3, #1
8005206: 6013 str r3, [r2, #0]
/* Reset CFGR register */
RCC->CFGR = 0x00070000U;
8005208: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800520c: f44f 22e0 mov.w r2, #458752 @ 0x70000
8005210: 609a str r2, [r3, #8]
/* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
RCC->CR &= (uint32_t)0xFAF6FEFBU;
8005212: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8005216: 681a ldr r2, [r3, #0]
8005218: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800521c: 4b18 ldr r3, [pc, #96] @ (8005280 <SystemInit+0x9c>)
800521e: 4013 ands r3, r2
8005220: 600b str r3, [r1, #0]
/*!< Reset LSI1 and LSI2 bits */
RCC->CSR &= (uint32_t)0xFFFFFFFAU;
8005222: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8005226: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800522a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800522e: f023 0305 bic.w r3, r3, #5
8005232: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
8005236: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800523a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
800523e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8005242: f023 0301 bic.w r3, r3, #1
8005246: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x22041000U;
800524a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800524e: 4a0d ldr r2, [pc, #52] @ (8005284 <SystemInit+0xa0>)
8005250: 60da str r2, [r3, #12]
#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
/* Reset PLLSAI1CFGR register */
RCC->PLLSAI1CFGR = 0x22041000U;
8005252: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8005256: 4a0b ldr r2, [pc, #44] @ (8005284 <SystemInit+0xa0>)
8005258: 611a str r2, [r3, #16]
#endif /* STM32WB55xx || STM32WB5Mxx */
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
800525a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800525e: 681b ldr r3, [r3, #0]
8005260: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8005264: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005268: 6013 str r3, [r2, #0]
/* Disable all interrupts */
RCC->CIER = 0x00000000;
800526a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800526e: 2200 movs r2, #0
8005270: 619a str r2, [r3, #24]
}
8005272: bf00 nop
8005274: 46bd mov sp, r7
8005276: f85d 7b04 ldr.w r7, [sp], #4
800527a: 4770 bx lr
800527c: e000ed00 .word 0xe000ed00
8005280: faf6fefb .word 0xfaf6fefb
8005284: 22041000 .word 0x22041000
08005288 <CopyDataInit>:
bl LoopCopyDataInit
.endm
.section .text.data_initializers
CopyDataInit:
ldr r4, [r2, r3]
8005288: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
800528a: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800528c: 3304 adds r3, #4
0800528e <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800528e: 18c4 adds r4, r0, r3
cmp r4, r1
8005290: 428c cmp r4, r1
bcc CopyDataInit
8005292: d3f9 bcc.n 8005288 <CopyDataInit>
bx lr
8005294: 4770 bx lr
08005296 <FillZerobss>:
FillZerobss:
str r3, [r0]
8005296: 6003 str r3, [r0, #0]
adds r0, r0, #4
8005298: 3004 adds r0, #4
0800529a <LoopFillZerobss>:
LoopFillZerobss:
cmp r0, r1
800529a: 4288 cmp r0, r1
bcc FillZerobss
800529c: d3fb bcc.n 8005296 <FillZerobss>
bx lr
800529e: 4770 bx lr
080052a0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
80052a0: 480c ldr r0, [pc, #48] @ (80052d4 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
80052a2: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
80052a4: f7ff ff9e bl 80051e4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
INIT_DATA _sdata, _edata, _sidata
80052a8: 480b ldr r0, [pc, #44] @ (80052d8 <LoopForever+0x6>)
80052aa: 490c ldr r1, [pc, #48] @ (80052dc <LoopForever+0xa>)
80052ac: 4a0c ldr r2, [pc, #48] @ (80052e0 <LoopForever+0xe>)
80052ae: 2300 movs r3, #0
80052b0: f7ff ffed bl 800528e <LoopCopyDataInit>
INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2
80052b4: 480b ldr r0, [pc, #44] @ (80052e4 <LoopForever+0x12>)
80052b6: 490c ldr r1, [pc, #48] @ (80052e8 <LoopForever+0x16>)
80052b8: 4a0c ldr r2, [pc, #48] @ (80052ec <LoopForever+0x1a>)
80052ba: 2300 movs r3, #0
80052bc: f7ff ffe7 bl 800528e <LoopCopyDataInit>
/* Zero fill the bss segments. */
INIT_BSS _sbss, _ebss
80052c0: 480b ldr r0, [pc, #44] @ (80052f0 <LoopForever+0x1e>)
80052c2: 490c ldr r1, [pc, #48] @ (80052f4 <LoopForever+0x22>)
80052c4: 2300 movs r3, #0
80052c6: f7ff ffe8 bl 800529a <LoopFillZerobss>
/* Call static constructors */
bl __libc_init_array
80052ca: f013 fbdb bl 8018a84 <__libc_init_array>
/* Call the application s entry point.*/
bl main
80052ce: f7fe faed bl 80038ac <main>
080052d2 <LoopForever>:
LoopForever:
b LoopForever
80052d2: e7fe b.n 80052d2 <LoopForever>
ldr r0, =_estack
80052d4: 20030000 .word 0x20030000
INIT_DATA _sdata, _edata, _sidata
80052d8: 20000008 .word 0x20000008
80052dc: 200002d8 .word 0x200002d8
80052e0: 0801cbf4 .word 0x0801cbf4
INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2
80052e4: 200300d8 .word 0x200300d8
80052e8: 2003094a .word 0x2003094a
80052ec: 0801ced5 .word 0x0801ced5
INIT_BSS _sbss, _ebss
80052f0: 200002ec .word 0x200002ec
80052f4: 20013c48 .word 0x20013c48
080052f8 <ADC1_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80052f8: e7fe b.n 80052f8 <ADC1_IRQHandler>
...
080052fc <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80052fc: b580 push {r7, lr}
80052fe: b082 sub sp, #8
8005300: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8005302: 2300 movs r3, #0
8005304: 71fb strb r3, [r7, #7]
#if (DATA_CACHE_ENABLE == 0U)
__HAL_FLASH_DATA_CACHE_DISABLE();
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8005306: 4b0c ldr r3, [pc, #48] @ (8005338 <HAL_Init+0x3c>)
8005308: 681b ldr r3, [r3, #0]
800530a: 4a0b ldr r2, [pc, #44] @ (8005338 <HAL_Init+0x3c>)
800530c: f443 7380 orr.w r3, r3, #256 @ 0x100
8005310: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8005312: 2003 movs r0, #3
8005314: f000 f94b bl 80055ae <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8005318: 200f movs r0, #15
800531a: f7ff fdc7 bl 8004eac <HAL_InitTick>
800531e: 4603 mov r3, r0
8005320: 2b00 cmp r3, #0
8005322: d002 beq.n 800532a <HAL_Init+0x2e>
{
status = HAL_ERROR;
8005324: 2301 movs r3, #1
8005326: 71fb strb r3, [r7, #7]
8005328: e001 b.n 800532e <HAL_Init+0x32>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
800532a: f7ff fb74 bl 8004a16 <HAL_MspInit>
}
/* Return function status */
return status;
800532e: 79fb ldrb r3, [r7, #7]
}
8005330: 4618 mov r0, r3
8005332: 3708 adds r7, #8
8005334: 46bd mov sp, r7
8005336: bd80 pop {r7, pc}
8005338: 58004000 .word 0x58004000
0800533c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
800533c: b480 push {r7}
800533e: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
8005340: 4b06 ldr r3, [pc, #24] @ (800535c <HAL_IncTick+0x20>)
8005342: 781b ldrb r3, [r3, #0]
8005344: 461a mov r2, r3
8005346: 4b06 ldr r3, [pc, #24] @ (8005360 <HAL_IncTick+0x24>)
8005348: 681b ldr r3, [r3, #0]
800534a: 4413 add r3, r2
800534c: 4a04 ldr r2, [pc, #16] @ (8005360 <HAL_IncTick+0x24>)
800534e: 6013 str r3, [r2, #0]
}
8005350: bf00 nop
8005352: 46bd mov sp, r7
8005354: f85d 7b04 ldr.w r7, [sp], #4
8005358: 4770 bx lr
800535a: bf00 nop
800535c: 20000014 .word 0x20000014
8005360: 20000780 .word 0x20000780
08005364 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8005364: b480 push {r7}
8005366: af00 add r7, sp, #0
return uwTick;
8005368: 4b03 ldr r3, [pc, #12] @ (8005378 <HAL_GetTick+0x14>)
800536a: 681b ldr r3, [r3, #0]
}
800536c: 4618 mov r0, r3
800536e: 46bd mov sp, r7
8005370: f85d 7b04 ldr.w r7, [sp], #4
8005374: 4770 bx lr
8005376: bf00 nop
8005378: 20000780 .word 0x20000780
0800537c <HAL_GetTickPrio>:
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
800537c: b480 push {r7}
800537e: af00 add r7, sp, #0
return uwTickPrio;
8005380: 4b03 ldr r3, [pc, #12] @ (8005390 <HAL_GetTickPrio+0x14>)
8005382: 681b ldr r3, [r3, #0]
}
8005384: 4618 mov r0, r3
8005386: 46bd mov sp, r7
8005388: f85d 7b04 ldr.w r7, [sp], #4
800538c: 4770 bx lr
800538e: bf00 nop
8005390: 20000010 .word 0x20000010
08005394 <__NVIC_SetPriorityGrouping>:
{
8005394: b480 push {r7}
8005396: b085 sub sp, #20
8005398: af00 add r7, sp, #0
800539a: 6078 str r0, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800539c: 687b ldr r3, [r7, #4]
800539e: f003 0307 and.w r3, r3, #7
80053a2: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80053a4: 4b0c ldr r3, [pc, #48] @ (80053d8 <__NVIC_SetPriorityGrouping+0x44>)
80053a6: 68db ldr r3, [r3, #12]
80053a8: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80053aa: 68ba ldr r2, [r7, #8]
80053ac: f64f 03ff movw r3, #63743 @ 0xf8ff
80053b0: 4013 ands r3, r2
80053b2: 60bb str r3, [r7, #8]
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80053b4: 68fb ldr r3, [r7, #12]
80053b6: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80053b8: 68bb ldr r3, [r7, #8]
80053ba: 4313 orrs r3, r2
reg_value = (reg_value |
80053bc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
80053c0: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80053c4: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80053c6: 4a04 ldr r2, [pc, #16] @ (80053d8 <__NVIC_SetPriorityGrouping+0x44>)
80053c8: 68bb ldr r3, [r7, #8]
80053ca: 60d3 str r3, [r2, #12]
}
80053cc: bf00 nop
80053ce: 3714 adds r7, #20
80053d0: 46bd mov sp, r7
80053d2: f85d 7b04 ldr.w r7, [sp], #4
80053d6: 4770 bx lr
80053d8: e000ed00 .word 0xe000ed00
080053dc <__NVIC_GetPriorityGrouping>:
{
80053dc: b480 push {r7}
80053de: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80053e0: 4b04 ldr r3, [pc, #16] @ (80053f4 <__NVIC_GetPriorityGrouping+0x18>)
80053e2: 68db ldr r3, [r3, #12]
80053e4: 0a1b lsrs r3, r3, #8
80053e6: f003 0307 and.w r3, r3, #7
}
80053ea: 4618 mov r0, r3
80053ec: 46bd mov sp, r7
80053ee: f85d 7b04 ldr.w r7, [sp], #4
80053f2: 4770 bx lr
80053f4: e000ed00 .word 0xe000ed00
080053f8 <__NVIC_EnableIRQ>:
{
80053f8: b480 push {r7}
80053fa: b083 sub sp, #12
80053fc: af00 add r7, sp, #0
80053fe: 4603 mov r3, r0
8005400: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8005402: f997 3007 ldrsb.w r3, [r7, #7]
8005406: 2b00 cmp r3, #0
8005408: db0b blt.n 8005422 <__NVIC_EnableIRQ+0x2a>
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800540a: 79fb ldrb r3, [r7, #7]
800540c: f003 021f and.w r2, r3, #31
8005410: 4907 ldr r1, [pc, #28] @ (8005430 <__NVIC_EnableIRQ+0x38>)
8005412: f997 3007 ldrsb.w r3, [r7, #7]
8005416: 095b lsrs r3, r3, #5
8005418: 2001 movs r0, #1
800541a: fa00 f202 lsl.w r2, r0, r2
800541e: f841 2023 str.w r2, [r1, r3, lsl #2]
}
8005422: bf00 nop
8005424: 370c adds r7, #12
8005426: 46bd mov sp, r7
8005428: f85d 7b04 ldr.w r7, [sp], #4
800542c: 4770 bx lr
800542e: bf00 nop
8005430: e000e100 .word 0xe000e100
08005434 <__NVIC_DisableIRQ>:
{
8005434: b480 push {r7}
8005436: b083 sub sp, #12
8005438: af00 add r7, sp, #0
800543a: 4603 mov r3, r0
800543c: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800543e: f997 3007 ldrsb.w r3, [r7, #7]
8005442: 2b00 cmp r3, #0
8005444: db12 blt.n 800546c <__NVIC_DisableIRQ+0x38>
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8005446: 79fb ldrb r3, [r7, #7]
8005448: f003 021f and.w r2, r3, #31
800544c: 490a ldr r1, [pc, #40] @ (8005478 <__NVIC_DisableIRQ+0x44>)
800544e: f997 3007 ldrsb.w r3, [r7, #7]
8005452: 095b lsrs r3, r3, #5
8005454: 2001 movs r0, #1
8005456: fa00 f202 lsl.w r2, r0, r2
800545a: 3320 adds r3, #32
800545c: f841 2023 str.w r2, [r1, r3, lsl #2]
__ASM volatile ("dsb 0xF":::"memory");
8005460: f3bf 8f4f dsb sy
}
8005464: bf00 nop
__ASM volatile ("isb 0xF":::"memory");
8005466: f3bf 8f6f isb sy
}
800546a: bf00 nop
}
800546c: bf00 nop
800546e: 370c adds r7, #12
8005470: 46bd mov sp, r7
8005472: f85d 7b04 ldr.w r7, [sp], #4
8005476: 4770 bx lr
8005478: e000e100 .word 0xe000e100
0800547c <__NVIC_SetPendingIRQ>:
{
800547c: b480 push {r7}
800547e: b083 sub sp, #12
8005480: af00 add r7, sp, #0
8005482: 4603 mov r3, r0
8005484: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8005486: f997 3007 ldrsb.w r3, [r7, #7]
800548a: 2b00 cmp r3, #0
800548c: db0c blt.n 80054a8 <__NVIC_SetPendingIRQ+0x2c>
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800548e: 79fb ldrb r3, [r7, #7]
8005490: f003 021f and.w r2, r3, #31
8005494: 4907 ldr r1, [pc, #28] @ (80054b4 <__NVIC_SetPendingIRQ+0x38>)
8005496: f997 3007 ldrsb.w r3, [r7, #7]
800549a: 095b lsrs r3, r3, #5
800549c: 2001 movs r0, #1
800549e: fa00 f202 lsl.w r2, r0, r2
80054a2: 3340 adds r3, #64 @ 0x40
80054a4: f841 2023 str.w r2, [r1, r3, lsl #2]
}
80054a8: bf00 nop
80054aa: 370c adds r7, #12
80054ac: 46bd mov sp, r7
80054ae: f85d 7b04 ldr.w r7, [sp], #4
80054b2: 4770 bx lr
80054b4: e000e100 .word 0xe000e100
080054b8 <__NVIC_ClearPendingIRQ>:
{
80054b8: b480 push {r7}
80054ba: b083 sub sp, #12
80054bc: af00 add r7, sp, #0
80054be: 4603 mov r3, r0
80054c0: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80054c2: f997 3007 ldrsb.w r3, [r7, #7]
80054c6: 2b00 cmp r3, #0
80054c8: db0c blt.n 80054e4 <__NVIC_ClearPendingIRQ+0x2c>
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80054ca: 79fb ldrb r3, [r7, #7]
80054cc: f003 021f and.w r2, r3, #31
80054d0: 4907 ldr r1, [pc, #28] @ (80054f0 <__NVIC_ClearPendingIRQ+0x38>)
80054d2: f997 3007 ldrsb.w r3, [r7, #7]
80054d6: 095b lsrs r3, r3, #5
80054d8: 2001 movs r0, #1
80054da: fa00 f202 lsl.w r2, r0, r2
80054de: 3360 adds r3, #96 @ 0x60
80054e0: f841 2023 str.w r2, [r1, r3, lsl #2]
}
80054e4: bf00 nop
80054e6: 370c adds r7, #12
80054e8: 46bd mov sp, r7
80054ea: f85d 7b04 ldr.w r7, [sp], #4
80054ee: 4770 bx lr
80054f0: e000e100 .word 0xe000e100
080054f4 <__NVIC_SetPriority>:
{
80054f4: b480 push {r7}
80054f6: b083 sub sp, #12
80054f8: af00 add r7, sp, #0
80054fa: 4603 mov r3, r0
80054fc: 6039 str r1, [r7, #0]
80054fe: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8005500: f997 3007 ldrsb.w r3, [r7, #7]
8005504: 2b00 cmp r3, #0
8005506: db0a blt.n 800551e <__NVIC_SetPriority+0x2a>
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8005508: 683b ldr r3, [r7, #0]
800550a: b2da uxtb r2, r3
800550c: 490c ldr r1, [pc, #48] @ (8005540 <__NVIC_SetPriority+0x4c>)
800550e: f997 3007 ldrsb.w r3, [r7, #7]
8005512: 0112 lsls r2, r2, #4
8005514: b2d2 uxtb r2, r2
8005516: 440b add r3, r1
8005518: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
800551c: e00a b.n 8005534 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800551e: 683b ldr r3, [r7, #0]
8005520: b2da uxtb r2, r3
8005522: 4908 ldr r1, [pc, #32] @ (8005544 <__NVIC_SetPriority+0x50>)
8005524: 79fb ldrb r3, [r7, #7]
8005526: f003 030f and.w r3, r3, #15
800552a: 3b04 subs r3, #4
800552c: 0112 lsls r2, r2, #4
800552e: b2d2 uxtb r2, r2
8005530: 440b add r3, r1
8005532: 761a strb r2, [r3, #24]
}
8005534: bf00 nop
8005536: 370c adds r7, #12
8005538: 46bd mov sp, r7
800553a: f85d 7b04 ldr.w r7, [sp], #4
800553e: 4770 bx lr
8005540: e000e100 .word 0xe000e100
8005544: e000ed00 .word 0xe000ed00
08005548 <NVIC_EncodePriority>:
{
8005548: b480 push {r7}
800554a: b089 sub sp, #36 @ 0x24
800554c: af00 add r7, sp, #0
800554e: 60f8 str r0, [r7, #12]
8005550: 60b9 str r1, [r7, #8]
8005552: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8005554: 68fb ldr r3, [r7, #12]
8005556: f003 0307 and.w r3, r3, #7
800555a: 61fb str r3, [r7, #28]
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
800555c: 69fb ldr r3, [r7, #28]
800555e: f1c3 0307 rsb r3, r3, #7
8005562: 2b04 cmp r3, #4
8005564: bf28 it cs
8005566: 2304 movcs r3, #4
8005568: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800556a: 69fb ldr r3, [r7, #28]
800556c: 3304 adds r3, #4
800556e: 2b06 cmp r3, #6
8005570: d902 bls.n 8005578 <NVIC_EncodePriority+0x30>
8005572: 69fb ldr r3, [r7, #28]
8005574: 3b03 subs r3, #3
8005576: e000 b.n 800557a <NVIC_EncodePriority+0x32>
8005578: 2300 movs r3, #0
800557a: 617b str r3, [r7, #20]
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800557c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8005580: 69bb ldr r3, [r7, #24]
8005582: fa02 f303 lsl.w r3, r2, r3
8005586: 43da mvns r2, r3
8005588: 68bb ldr r3, [r7, #8]
800558a: 401a ands r2, r3
800558c: 697b ldr r3, [r7, #20]
800558e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8005590: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8005594: 697b ldr r3, [r7, #20]
8005596: fa01 f303 lsl.w r3, r1, r3
800559a: 43d9 mvns r1, r3
800559c: 687b ldr r3, [r7, #4]
800559e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80055a0: 4313 orrs r3, r2
}
80055a2: 4618 mov r0, r3
80055a4: 3724 adds r7, #36 @ 0x24
80055a6: 46bd mov sp, r7
80055a8: f85d 7b04 ldr.w r7, [sp], #4
80055ac: 4770 bx lr
080055ae <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80055ae: b580 push {r7, lr}
80055b0: b082 sub sp, #8
80055b2: af00 add r7, sp, #0
80055b4: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
80055b6: 6878 ldr r0, [r7, #4]
80055b8: f7ff feec bl 8005394 <__NVIC_SetPriorityGrouping>
}
80055bc: bf00 nop
80055be: 3708 adds r7, #8
80055c0: 46bd mov sp, r7
80055c2: bd80 pop {r7, pc}
080055c4 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80055c4: b580 push {r7, lr}
80055c6: b086 sub sp, #24
80055c8: af00 add r7, sp, #0
80055ca: 4603 mov r3, r0
80055cc: 60b9 str r1, [r7, #8]
80055ce: 607a str r2, [r7, #4]
80055d0: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80055d2: f7ff ff03 bl 80053dc <__NVIC_GetPriorityGrouping>
80055d6: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80055d8: 687a ldr r2, [r7, #4]
80055da: 68b9 ldr r1, [r7, #8]
80055dc: 6978 ldr r0, [r7, #20]
80055de: f7ff ffb3 bl 8005548 <NVIC_EncodePriority>
80055e2: 4602 mov r2, r0
80055e4: f997 300f ldrsb.w r3, [r7, #15]
80055e8: 4611 mov r1, r2
80055ea: 4618 mov r0, r3
80055ec: f7ff ff82 bl 80054f4 <__NVIC_SetPriority>
}
80055f0: bf00 nop
80055f2: 3718 adds r7, #24
80055f4: 46bd mov sp, r7
80055f6: bd80 pop {r7, pc}
080055f8 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80055f8: b580 push {r7, lr}
80055fa: b082 sub sp, #8
80055fc: af00 add r7, sp, #0
80055fe: 4603 mov r3, r0
8005600: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8005602: f997 3007 ldrsb.w r3, [r7, #7]
8005606: 4618 mov r0, r3
8005608: f7ff fef6 bl 80053f8 <__NVIC_EnableIRQ>
}
800560c: bf00 nop
800560e: 3708 adds r7, #8
8005610: 46bd mov sp, r7
8005612: bd80 pop {r7, pc}
08005614 <HAL_NVIC_DisableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
8005614: b580 push {r7, lr}
8005616: b082 sub sp, #8
8005618: af00 add r7, sp, #0
800561a: 4603 mov r3, r0
800561c: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
800561e: f997 3007 ldrsb.w r3, [r7, #7]
8005622: 4618 mov r0, r3
8005624: f7ff ff06 bl 8005434 <__NVIC_DisableIRQ>
}
8005628: bf00 nop
800562a: 3708 adds r7, #8
800562c: 46bd mov sp, r7
800562e: bd80 pop {r7, pc}
08005630 <HAL_NVIC_SetPendingIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
8005630: b580 push {r7, lr}
8005632: b082 sub sp, #8
8005634: af00 add r7, sp, #0
8005636: 4603 mov r3, r0
8005638: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
800563a: f997 3007 ldrsb.w r3, [r7, #7]
800563e: 4618 mov r0, r3
8005640: f7ff ff1c bl 800547c <__NVIC_SetPendingIRQ>
}
8005644: bf00 nop
8005646: 3708 adds r7, #8
8005648: 46bd mov sp, r7
800564a: bd80 pop {r7, pc}
0800564c <HAL_NVIC_ClearPendingIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
800564c: b580 push {r7, lr}
800564e: b082 sub sp, #8
8005650: af00 add r7, sp, #0
8005652: 4603 mov r3, r0
8005654: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
8005656: f997 3007 ldrsb.w r3, [r7, #7]
800565a: 4618 mov r0, r3
800565c: f7ff ff2c bl 80054b8 <__NVIC_ClearPendingIRQ>
}
8005660: bf00 nop
8005662: 3708 adds r7, #8
8005664: 46bd mov sp, r7
8005666: bd80 pop {r7, pc}
08005668 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8005668: b580 push {r7, lr}
800566a: b084 sub sp, #16
800566c: af00 add r7, sp, #0
800566e: 6078 str r0, [r7, #4]
uint32_t tmp;
/* Check the DMA handle allocation */
if (hdma == NULL)
8005670: 687b ldr r3, [r7, #4]
8005672: 2b00 cmp r3, #0
8005674: d101 bne.n 800567a <HAL_DMA_Init+0x12>
{
return HAL_ERROR;
8005676: 2301 movs r3, #1
8005678: e08e b.n 8005798 <HAL_DMA_Init+0x130>
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
#if defined(DMA2)
/* Compute the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
800567a: 687b ldr r3, [r7, #4]
800567c: 681b ldr r3, [r3, #0]
800567e: 461a mov r2, r3
8005680: 4b47 ldr r3, [pc, #284] @ (80057a0 <HAL_DMA_Init+0x138>)
8005682: 429a cmp r2, r3
8005684: d80f bhi.n 80056a6 <HAL_DMA_Init+0x3e>
{
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
8005686: 687b ldr r3, [r7, #4]
8005688: 681b ldr r3, [r3, #0]
800568a: 461a mov r2, r3
800568c: 4b45 ldr r3, [pc, #276] @ (80057a4 <HAL_DMA_Init+0x13c>)
800568e: 4413 add r3, r2
8005690: 4a45 ldr r2, [pc, #276] @ (80057a8 <HAL_DMA_Init+0x140>)
8005692: fba2 2303 umull r2, r3, r2, r3
8005696: 091b lsrs r3, r3, #4
8005698: 009a lsls r2, r3, #2
800569a: 687b ldr r3, [r7, #4]
800569c: 645a str r2, [r3, #68] @ 0x44
hdma->DmaBaseAddress = DMA1;
800569e: 687b ldr r3, [r7, #4]
80056a0: 4a42 ldr r2, [pc, #264] @ (80057ac <HAL_DMA_Init+0x144>)
80056a2: 641a str r2, [r3, #64] @ 0x40
80056a4: e00e b.n 80056c4 <HAL_DMA_Init+0x5c>
}
else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
80056a6: 687b ldr r3, [r7, #4]
80056a8: 681b ldr r3, [r3, #0]
80056aa: 461a mov r2, r3
80056ac: 4b40 ldr r3, [pc, #256] @ (80057b0 <HAL_DMA_Init+0x148>)
80056ae: 4413 add r3, r2
80056b0: 4a3d ldr r2, [pc, #244] @ (80057a8 <HAL_DMA_Init+0x140>)
80056b2: fba2 2303 umull r2, r3, r2, r3
80056b6: 091b lsrs r3, r3, #4
80056b8: 009a lsls r2, r3, #2
80056ba: 687b ldr r3, [r7, #4]
80056bc: 645a str r2, [r3, #68] @ 0x44
hdma->DmaBaseAddress = DMA2;
80056be: 687b ldr r3, [r7, #4]
80056c0: 4a3c ldr r2, [pc, #240] @ (80057b4 <HAL_DMA_Init+0x14c>)
80056c2: 641a str r2, [r3, #64] @ 0x40
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
#endif /* DMA2 */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
80056c4: 687b ldr r3, [r7, #4]
80056c6: 2202 movs r2, #2
80056c8: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Get the CR register value */
tmp = hdma->Instance->CCR;
80056cc: 687b ldr r3, [r7, #4]
80056ce: 681b ldr r3, [r3, #0]
80056d0: 681b ldr r3, [r3, #0]
80056d2: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
80056d4: 68fb ldr r3, [r7, #12]
80056d6: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
80056da: f023 0370 bic.w r3, r3, #112 @ 0x70
80056de: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
80056e0: 687b ldr r3, [r7, #4]
80056e2: 689a ldr r2, [r3, #8]
hdma->Init.PeriphInc | hdma->Init.MemInc |
80056e4: 687b ldr r3, [r7, #4]
80056e6: 68db ldr r3, [r3, #12]
tmp |= hdma->Init.Direction |
80056e8: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
80056ea: 687b ldr r3, [r7, #4]
80056ec: 691b ldr r3, [r3, #16]
80056ee: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80056f0: 687b ldr r3, [r7, #4]
80056f2: 695b ldr r3, [r3, #20]
hdma->Init.PeriphInc | hdma->Init.MemInc |
80056f4: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80056f6: 687b ldr r3, [r7, #4]
80056f8: 699b ldr r3, [r3, #24]
80056fa: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
80056fc: 687b ldr r3, [r7, #4]
80056fe: 69db ldr r3, [r3, #28]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8005700: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8005702: 687b ldr r3, [r7, #4]
8005704: 6a1b ldr r3, [r3, #32]
8005706: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
8005708: 68fa ldr r2, [r7, #12]
800570a: 4313 orrs r3, r2
800570c: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
800570e: 687b ldr r3, [r7, #4]
8005710: 681b ldr r3, [r3, #0]
8005712: 68fa ldr r2, [r7, #12]
8005714: 601a str r2, [r3, #0]
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
8005716: 6878 ldr r0, [r7, #4]
8005718: f000 fa24 bl 8005b64 <DMA_CalcDMAMUXChannelBaseAndMask>
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
800571c: 687b ldr r3, [r7, #4]
800571e: 689b ldr r3, [r3, #8]
8005720: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8005724: d102 bne.n 800572c <HAL_DMA_Init+0xc4>
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
8005726: 687b ldr r3, [r7, #4]
8005728: 2200 movs r2, #0
800572a: 605a str r2, [r3, #4]
}
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
800572c: 687b ldr r3, [r7, #4]
800572e: 685a ldr r2, [r3, #4]
8005730: 687b ldr r3, [r7, #4]
8005732: 6c9b ldr r3, [r3, #72] @ 0x48
8005734: f002 023f and.w r2, r2, #63 @ 0x3f
8005738: 601a str r2, [r3, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
800573a: 687b ldr r3, [r7, #4]
800573c: 6cdb ldr r3, [r3, #76] @ 0x4c
800573e: 687a ldr r2, [r7, #4]
8005740: 6d12 ldr r2, [r2, #80] @ 0x50
8005742: 605a str r2, [r3, #4]
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
8005744: 687b ldr r3, [r7, #4]
8005746: 685b ldr r3, [r3, #4]
8005748: 2b00 cmp r3, #0
800574a: d010 beq.n 800576e <HAL_DMA_Init+0x106>
800574c: 687b ldr r3, [r7, #4]
800574e: 685b ldr r3, [r3, #4]
8005750: 2b04 cmp r3, #4
8005752: d80c bhi.n 800576e <HAL_DMA_Init+0x106>
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
*/
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
8005754: 6878 ldr r0, [r7, #4]
8005756: f000 fa43 bl 8005be0 <DMA_CalcDMAMUXRequestGenBaseAndMask>
/* Reset the DMAMUX request generator register*/
hdma->DMAmuxRequestGen->RGCR = 0U;
800575a: 687b ldr r3, [r7, #4]
800575c: 6d5b ldr r3, [r3, #84] @ 0x54
800575e: 2200 movs r2, #0
8005760: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8005762: 687b ldr r3, [r7, #4]
8005764: 6d9b ldr r3, [r3, #88] @ 0x58
8005766: 687a ldr r2, [r7, #4]
8005768: 6dd2 ldr r2, [r2, #92] @ 0x5c
800576a: 605a str r2, [r3, #4]
800576c: e008 b.n 8005780 <HAL_DMA_Init+0x118>
}
else
{
hdma->DMAmuxRequestGen = 0U;
800576e: 687b ldr r3, [r7, #4]
8005770: 2200 movs r2, #0
8005772: 655a str r2, [r3, #84] @ 0x54
hdma->DMAmuxRequestGenStatus = 0U;
8005774: 687b ldr r3, [r7, #4]
8005776: 2200 movs r2, #0
8005778: 659a str r2, [r3, #88] @ 0x58
hdma->DMAmuxRequestGenStatusMask = 0U;
800577a: 687b ldr r3, [r7, #4]
800577c: 2200 movs r2, #0
800577e: 65da str r2, [r3, #92] @ 0x5c
}
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8005780: 687b ldr r3, [r7, #4]
8005782: 2200 movs r2, #0
8005784: 63da str r2, [r3, #60] @ 0x3c
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8005786: 687b ldr r3, [r7, #4]
8005788: 2201 movs r2, #1
800578a: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
800578e: 687b ldr r3, [r7, #4]
8005790: 2200 movs r2, #0
8005792: f883 2024 strb.w r2, [r3, #36] @ 0x24
return HAL_OK;
8005796: 2300 movs r3, #0
}
8005798: 4618 mov r0, r3
800579a: 3710 adds r7, #16
800579c: 46bd mov sp, r7
800579e: bd80 pop {r7, pc}
80057a0: 40020407 .word 0x40020407
80057a4: bffdfff8 .word 0xbffdfff8
80057a8: cccccccd .word 0xcccccccd
80057ac: 40020000 .word 0x40020000
80057b0: bffdfbf8 .word 0xbffdfbf8
80057b4: 40020400 .word 0x40020400
080057b8 <HAL_DMA_Start_IT>:
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
uint32_t DataLength)
{
80057b8: b580 push {r7, lr}
80057ba: b086 sub sp, #24
80057bc: af00 add r7, sp, #0
80057be: 60f8 str r0, [r7, #12]
80057c0: 60b9 str r1, [r7, #8]
80057c2: 607a str r2, [r7, #4]
80057c4: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
80057c6: 2300 movs r3, #0
80057c8: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
80057ca: 68fb ldr r3, [r7, #12]
80057cc: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80057d0: 2b01 cmp r3, #1
80057d2: d101 bne.n 80057d8 <HAL_DMA_Start_IT+0x20>
80057d4: 2302 movs r3, #2
80057d6: e066 b.n 80058a6 <HAL_DMA_Start_IT+0xee>
80057d8: 68fb ldr r3, [r7, #12]
80057da: 2201 movs r2, #1
80057dc: f883 2024 strb.w r2, [r3, #36] @ 0x24
if (HAL_DMA_STATE_READY == hdma->State)
80057e0: 68fb ldr r3, [r7, #12]
80057e2: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
80057e6: b2db uxtb r3, r3
80057e8: 2b01 cmp r3, #1
80057ea: d155 bne.n 8005898 <HAL_DMA_Start_IT+0xe0>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
80057ec: 68fb ldr r3, [r7, #12]
80057ee: 2202 movs r2, #2
80057f0: f883 2025 strb.w r2, [r3, #37] @ 0x25
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80057f4: 68fb ldr r3, [r7, #12]
80057f6: 2200 movs r2, #0
80057f8: 63da str r2, [r3, #60] @ 0x3c
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
80057fa: 68fb ldr r3, [r7, #12]
80057fc: 681b ldr r3, [r3, #0]
80057fe: 681a ldr r2, [r3, #0]
8005800: 68fb ldr r3, [r7, #12]
8005802: 681b ldr r3, [r3, #0]
8005804: f022 0201 bic.w r2, r2, #1
8005808: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
800580a: 683b ldr r3, [r7, #0]
800580c: 687a ldr r2, [r7, #4]
800580e: 68b9 ldr r1, [r7, #8]
8005810: 68f8 ldr r0, [r7, #12]
8005812: f000 f968 bl 8005ae6 <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if (NULL != hdma->XferHalfCpltCallback)
8005816: 68fb ldr r3, [r7, #12]
8005818: 6b1b ldr r3, [r3, #48] @ 0x30
800581a: 2b00 cmp r3, #0
800581c: d008 beq.n 8005830 <HAL_DMA_Start_IT+0x78>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800581e: 68fb ldr r3, [r7, #12]
8005820: 681b ldr r3, [r3, #0]
8005822: 681a ldr r2, [r3, #0]
8005824: 68fb ldr r3, [r7, #12]
8005826: 681b ldr r3, [r3, #0]
8005828: f042 020e orr.w r2, r2, #14
800582c: 601a str r2, [r3, #0]
800582e: e00f b.n 8005850 <HAL_DMA_Start_IT+0x98>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8005830: 68fb ldr r3, [r7, #12]
8005832: 681b ldr r3, [r3, #0]
8005834: 681a ldr r2, [r3, #0]
8005836: 68fb ldr r3, [r7, #12]
8005838: 681b ldr r3, [r3, #0]
800583a: f022 0204 bic.w r2, r2, #4
800583e: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8005840: 68fb ldr r3, [r7, #12]
8005842: 681b ldr r3, [r3, #0]
8005844: 681a ldr r2, [r3, #0]
8005846: 68fb ldr r3, [r7, #12]
8005848: 681b ldr r3, [r3, #0]
800584a: f042 020a orr.w r2, r2, #10
800584e: 601a str r2, [r3, #0]
}
/* Check if DMAMUX Synchronization is enabled*/
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
8005850: 68fb ldr r3, [r7, #12]
8005852: 6c9b ldr r3, [r3, #72] @ 0x48
8005854: 681b ldr r3, [r3, #0]
8005856: f403 3380 and.w r3, r3, #65536 @ 0x10000
800585a: 2b00 cmp r3, #0
800585c: d007 beq.n 800586e <HAL_DMA_Start_IT+0xb6>
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
800585e: 68fb ldr r3, [r7, #12]
8005860: 6c9b ldr r3, [r3, #72] @ 0x48
8005862: 681a ldr r2, [r3, #0]
8005864: 68fb ldr r3, [r7, #12]
8005866: 6c9b ldr r3, [r3, #72] @ 0x48
8005868: f442 7280 orr.w r2, r2, #256 @ 0x100
800586c: 601a str r2, [r3, #0]
}
if (hdma->DMAmuxRequestGen != 0U)
800586e: 68fb ldr r3, [r7, #12]
8005870: 6d5b ldr r3, [r3, #84] @ 0x54
8005872: 2b00 cmp r3, #0
8005874: d007 beq.n 8005886 <HAL_DMA_Start_IT+0xce>
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
8005876: 68fb ldr r3, [r7, #12]
8005878: 6d5b ldr r3, [r3, #84] @ 0x54
800587a: 681a ldr r2, [r3, #0]
800587c: 68fb ldr r3, [r7, #12]
800587e: 6d5b ldr r3, [r3, #84] @ 0x54
8005880: f442 7280 orr.w r2, r2, #256 @ 0x100
8005884: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
8005886: 68fb ldr r3, [r7, #12]
8005888: 681b ldr r3, [r3, #0]
800588a: 681a ldr r2, [r3, #0]
800588c: 68fb ldr r3, [r7, #12]
800588e: 681b ldr r3, [r3, #0]
8005890: f042 0201 orr.w r2, r2, #1
8005894: 601a str r2, [r3, #0]
8005896: e005 b.n 80058a4 <HAL_DMA_Start_IT+0xec>
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8005898: 68fb ldr r3, [r7, #12]
800589a: 2200 movs r2, #0
800589c: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Remain BUSY */
status = HAL_BUSY;
80058a0: 2302 movs r3, #2
80058a2: 75fb strb r3, [r7, #23]
}
return status;
80058a4: 7dfb ldrb r3, [r7, #23]
}
80058a6: 4618 mov r0, r3
80058a8: 3718 adds r7, #24
80058aa: 46bd mov sp, r7
80058ac: bd80 pop {r7, pc}
080058ae <HAL_DMA_Abort_IT>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
80058ae: b580 push {r7, lr}
80058b0: b084 sub sp, #16
80058b2: af00 add r7, sp, #0
80058b4: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80058b6: 2300 movs r3, #0
80058b8: 73fb strb r3, [r7, #15]
if (HAL_DMA_STATE_BUSY != hdma->State)
80058ba: 687b ldr r3, [r7, #4]
80058bc: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
80058c0: b2db uxtb r3, r3
80058c2: 2b02 cmp r3, #2
80058c4: d005 beq.n 80058d2 <HAL_DMA_Abort_IT+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
80058c6: 687b ldr r3, [r7, #4]
80058c8: 2204 movs r2, #4
80058ca: 63da str r2, [r3, #60] @ 0x3c
status = HAL_ERROR;
80058cc: 2301 movs r3, #1
80058ce: 73fb strb r3, [r7, #15]
80058d0: e047 b.n 8005962 <HAL_DMA_Abort_IT+0xb4>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
80058d2: 687b ldr r3, [r7, #4]
80058d4: 681b ldr r3, [r3, #0]
80058d6: 681a ldr r2, [r3, #0]
80058d8: 687b ldr r3, [r7, #4]
80058da: 681b ldr r3, [r3, #0]
80058dc: f022 020e bic.w r2, r2, #14
80058e0: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
80058e2: 687b ldr r3, [r7, #4]
80058e4: 681b ldr r3, [r3, #0]
80058e6: 681a ldr r2, [r3, #0]
80058e8: 687b ldr r3, [r7, #4]
80058ea: 681b ldr r3, [r3, #0]
80058ec: f022 0201 bic.w r2, r2, #1
80058f0: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
80058f2: 687b ldr r3, [r7, #4]
80058f4: 6c9b ldr r3, [r3, #72] @ 0x48
80058f6: 681a ldr r2, [r3, #0]
80058f8: 687b ldr r3, [r7, #4]
80058fa: 6c9b ldr r3, [r3, #72] @ 0x48
80058fc: f422 7280 bic.w r2, r2, #256 @ 0x100
8005900: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
8005902: 687b ldr r3, [r7, #4]
8005904: 6c5b ldr r3, [r3, #68] @ 0x44
8005906: f003 021c and.w r2, r3, #28
800590a: 687b ldr r3, [r7, #4]
800590c: 6c1b ldr r3, [r3, #64] @ 0x40
800590e: 2101 movs r1, #1
8005910: fa01 f202 lsl.w r2, r1, r2
8005914: 605a str r2, [r3, #4]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8005916: 687b ldr r3, [r7, #4]
8005918: 6cdb ldr r3, [r3, #76] @ 0x4c
800591a: 687a ldr r2, [r7, #4]
800591c: 6d12 ldr r2, [r2, #80] @ 0x50
800591e: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8005920: 687b ldr r3, [r7, #4]
8005922: 6d5b ldr r3, [r3, #84] @ 0x54
8005924: 2b00 cmp r3, #0
8005926: d00c beq.n 8005942 <HAL_DMA_Abort_IT+0x94>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8005928: 687b ldr r3, [r7, #4]
800592a: 6d5b ldr r3, [r3, #84] @ 0x54
800592c: 681a ldr r2, [r3, #0]
800592e: 687b ldr r3, [r7, #4]
8005930: 6d5b ldr r3, [r3, #84] @ 0x54
8005932: f422 7280 bic.w r2, r2, #256 @ 0x100
8005936: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8005938: 687b ldr r3, [r7, #4]
800593a: 6d9b ldr r3, [r3, #88] @ 0x58
800593c: 687a ldr r2, [r7, #4]
800593e: 6dd2 ldr r2, [r2, #92] @ 0x5c
8005940: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8005942: 687b ldr r3, [r7, #4]
8005944: 2201 movs r2, #1
8005946: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800594a: 687b ldr r3, [r7, #4]
800594c: 2200 movs r2, #0
800594e: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Call User Abort callback */
if (hdma->XferAbortCallback != NULL)
8005952: 687b ldr r3, [r7, #4]
8005954: 6b9b ldr r3, [r3, #56] @ 0x38
8005956: 2b00 cmp r3, #0
8005958: d003 beq.n 8005962 <HAL_DMA_Abort_IT+0xb4>
{
hdma->XferAbortCallback(hdma);
800595a: 687b ldr r3, [r7, #4]
800595c: 6b9b ldr r3, [r3, #56] @ 0x38
800595e: 6878 ldr r0, [r7, #4]
8005960: 4798 blx r3
}
}
return status;
8005962: 7bfb ldrb r3, [r7, #15]
}
8005964: 4618 mov r0, r3
8005966: 3710 adds r7, #16
8005968: 46bd mov sp, r7
800596a: bd80 pop {r7, pc}
0800596c <HAL_DMA_IRQHandler>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
800596c: b580 push {r7, lr}
800596e: b084 sub sp, #16
8005970: af00 add r7, sp, #0
8005972: 6078 str r0, [r7, #4]
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
8005974: 687b ldr r3, [r7, #4]
8005976: 6c1b ldr r3, [r3, #64] @ 0x40
8005978: 681b ldr r3, [r3, #0]
800597a: 60fb str r3, [r7, #12]
uint32_t source_it = hdma->Instance->CCR;
800597c: 687b ldr r3, [r7, #4]
800597e: 681b ldr r3, [r3, #0]
8005980: 681b ldr r3, [r3, #0]
8005982: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
8005984: 687b ldr r3, [r7, #4]
8005986: 6c5b ldr r3, [r3, #68] @ 0x44
8005988: f003 031c and.w r3, r3, #28
800598c: 2204 movs r2, #4
800598e: 409a lsls r2, r3
8005990: 68fb ldr r3, [r7, #12]
8005992: 4013 ands r3, r2
8005994: 2b00 cmp r3, #0
8005996: d026 beq.n 80059e6 <HAL_DMA_IRQHandler+0x7a>
8005998: 68bb ldr r3, [r7, #8]
800599a: f003 0304 and.w r3, r3, #4
800599e: 2b00 cmp r3, #0
80059a0: d021 beq.n 80059e6 <HAL_DMA_IRQHandler+0x7a>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
80059a2: 687b ldr r3, [r7, #4]
80059a4: 681b ldr r3, [r3, #0]
80059a6: 681b ldr r3, [r3, #0]
80059a8: f003 0320 and.w r3, r3, #32
80059ac: 2b00 cmp r3, #0
80059ae: d107 bne.n 80059c0 <HAL_DMA_IRQHandler+0x54>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
80059b0: 687b ldr r3, [r7, #4]
80059b2: 681b ldr r3, [r3, #0]
80059b4: 681a ldr r2, [r3, #0]
80059b6: 687b ldr r3, [r7, #4]
80059b8: 681b ldr r3, [r3, #0]
80059ba: f022 0204 bic.w r2, r2, #4
80059be: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU));
80059c0: 687b ldr r3, [r7, #4]
80059c2: 6c5b ldr r3, [r3, #68] @ 0x44
80059c4: f003 021c and.w r2, r3, #28
80059c8: 687b ldr r3, [r7, #4]
80059ca: 6c1b ldr r3, [r3, #64] @ 0x40
80059cc: 2104 movs r1, #4
80059ce: fa01 f202 lsl.w r2, r1, r2
80059d2: 605a str r2, [r3, #4]
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if (hdma->XferHalfCpltCallback != NULL)
80059d4: 687b ldr r3, [r7, #4]
80059d6: 6b1b ldr r3, [r3, #48] @ 0x30
80059d8: 2b00 cmp r3, #0
80059da: d071 beq.n 8005ac0 <HAL_DMA_IRQHandler+0x154>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
80059dc: 687b ldr r3, [r7, #4]
80059de: 6b1b ldr r3, [r3, #48] @ 0x30
80059e0: 6878 ldr r0, [r7, #4]
80059e2: 4798 blx r3
if (hdma->XferHalfCpltCallback != NULL)
80059e4: e06c b.n 8005ac0 <HAL_DMA_IRQHandler+0x154>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
80059e6: 687b ldr r3, [r7, #4]
80059e8: 6c5b ldr r3, [r3, #68] @ 0x44
80059ea: f003 031c and.w r3, r3, #28
80059ee: 2202 movs r2, #2
80059f0: 409a lsls r2, r3
80059f2: 68fb ldr r3, [r7, #12]
80059f4: 4013 ands r3, r2
80059f6: 2b00 cmp r3, #0
80059f8: d02e beq.n 8005a58 <HAL_DMA_IRQHandler+0xec>
80059fa: 68bb ldr r3, [r7, #8]
80059fc: f003 0302 and.w r3, r3, #2
8005a00: 2b00 cmp r3, #0
8005a02: d029 beq.n 8005a58 <HAL_DMA_IRQHandler+0xec>
{
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8005a04: 687b ldr r3, [r7, #4]
8005a06: 681b ldr r3, [r3, #0]
8005a08: 681b ldr r3, [r3, #0]
8005a0a: f003 0320 and.w r3, r3, #32
8005a0e: 2b00 cmp r3, #0
8005a10: d10b bne.n 8005a2a <HAL_DMA_IRQHandler+0xbe>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
8005a12: 687b ldr r3, [r7, #4]
8005a14: 681b ldr r3, [r3, #0]
8005a16: 681a ldr r2, [r3, #0]
8005a18: 687b ldr r3, [r7, #4]
8005a1a: 681b ldr r3, [r3, #0]
8005a1c: f022 020a bic.w r2, r2, #10
8005a20: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8005a22: 687b ldr r3, [r7, #4]
8005a24: 2201 movs r2, #1
8005a26: f883 2025 strb.w r2, [r3, #37] @ 0x25
}
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
8005a2a: 687b ldr r3, [r7, #4]
8005a2c: 6c5b ldr r3, [r3, #68] @ 0x44
8005a2e: f003 021c and.w r2, r3, #28
8005a32: 687b ldr r3, [r7, #4]
8005a34: 6c1b ldr r3, [r3, #64] @ 0x40
8005a36: 2102 movs r1, #2
8005a38: fa01 f202 lsl.w r2, r1, r2
8005a3c: 605a str r2, [r3, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8005a3e: 687b ldr r3, [r7, #4]
8005a40: 2200 movs r2, #0
8005a42: f883 2024 strb.w r2, [r3, #36] @ 0x24
if (hdma->XferCpltCallback != NULL)
8005a46: 687b ldr r3, [r7, #4]
8005a48: 6adb ldr r3, [r3, #44] @ 0x2c
8005a4a: 2b00 cmp r3, #0
8005a4c: d038 beq.n 8005ac0 <HAL_DMA_IRQHandler+0x154>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
8005a4e: 687b ldr r3, [r7, #4]
8005a50: 6adb ldr r3, [r3, #44] @ 0x2c
8005a52: 6878 ldr r0, [r7, #4]
8005a54: 4798 blx r3
if (hdma->XferCpltCallback != NULL)
8005a56: e033 b.n 8005ac0 <HAL_DMA_IRQHandler+0x154>
}
}
/* Transfer Error Interrupt management **************************************/
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
8005a58: 687b ldr r3, [r7, #4]
8005a5a: 6c5b ldr r3, [r3, #68] @ 0x44
8005a5c: f003 031c and.w r3, r3, #28
8005a60: 2208 movs r2, #8
8005a62: 409a lsls r2, r3
8005a64: 68fb ldr r3, [r7, #12]
8005a66: 4013 ands r3, r2
8005a68: 2b00 cmp r3, #0
8005a6a: d02a beq.n 8005ac2 <HAL_DMA_IRQHandler+0x156>
8005a6c: 68bb ldr r3, [r7, #8]
8005a6e: f003 0308 and.w r3, r3, #8
8005a72: 2b00 cmp r3, #0
8005a74: d025 beq.n 8005ac2 <HAL_DMA_IRQHandler+0x156>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8005a76: 687b ldr r3, [r7, #4]
8005a78: 681b ldr r3, [r3, #0]
8005a7a: 681a ldr r2, [r3, #0]
8005a7c: 687b ldr r3, [r7, #4]
8005a7e: 681b ldr r3, [r3, #0]
8005a80: f022 020e bic.w r2, r2, #14
8005a84: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
8005a86: 687b ldr r3, [r7, #4]
8005a88: 6c5b ldr r3, [r3, #68] @ 0x44
8005a8a: f003 021c and.w r2, r3, #28
8005a8e: 687b ldr r3, [r7, #4]
8005a90: 6c1b ldr r3, [r3, #64] @ 0x40
8005a92: 2101 movs r1, #1
8005a94: fa01 f202 lsl.w r2, r1, r2
8005a98: 605a str r2, [r3, #4]
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
8005a9a: 687b ldr r3, [r7, #4]
8005a9c: 2201 movs r2, #1
8005a9e: 63da str r2, [r3, #60] @ 0x3c
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8005aa0: 687b ldr r3, [r7, #4]
8005aa2: 2201 movs r2, #1
8005aa4: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8005aa8: 687b ldr r3, [r7, #4]
8005aaa: 2200 movs r2, #0
8005aac: f883 2024 strb.w r2, [r3, #36] @ 0x24
if (hdma->XferErrorCallback != NULL)
8005ab0: 687b ldr r3, [r7, #4]
8005ab2: 6b5b ldr r3, [r3, #52] @ 0x34
8005ab4: 2b00 cmp r3, #0
8005ab6: d004 beq.n 8005ac2 <HAL_DMA_IRQHandler+0x156>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
8005ab8: 687b ldr r3, [r7, #4]
8005aba: 6b5b ldr r3, [r3, #52] @ 0x34
8005abc: 6878 ldr r0, [r7, #4]
8005abe: 4798 blx r3
}
else
{
/* Nothing To Do */
}
return;
8005ac0: bf00 nop
8005ac2: bf00 nop
}
8005ac4: 3710 adds r7, #16
8005ac6: 46bd mov sp, r7
8005ac8: bd80 pop {r7, pc}
08005aca <HAL_DMA_GetState>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
{
8005aca: b480 push {r7}
8005acc: b083 sub sp, #12
8005ace: af00 add r7, sp, #0
8005ad0: 6078 str r0, [r7, #4]
/* Return DMA handle state */
return hdma->State;
8005ad2: 687b ldr r3, [r7, #4]
8005ad4: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
8005ad8: b2db uxtb r3, r3
}
8005ada: 4618 mov r0, r3
8005adc: 370c adds r7, #12
8005ade: 46bd mov sp, r7
8005ae0: f85d 7b04 ldr.w r7, [sp], #4
8005ae4: 4770 bx lr
08005ae6 <DMA_SetConfig>:
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8005ae6: b480 push {r7}
8005ae8: b085 sub sp, #20
8005aea: af00 add r7, sp, #0
8005aec: 60f8 str r0, [r7, #12]
8005aee: 60b9 str r1, [r7, #8]
8005af0: 607a str r2, [r7, #4]
8005af2: 603b str r3, [r7, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8005af4: 68fb ldr r3, [r7, #12]
8005af6: 6cdb ldr r3, [r3, #76] @ 0x4c
8005af8: 68fa ldr r2, [r7, #12]
8005afa: 6d12 ldr r2, [r2, #80] @ 0x50
8005afc: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8005afe: 68fb ldr r3, [r7, #12]
8005b00: 6d5b ldr r3, [r3, #84] @ 0x54
8005b02: 2b00 cmp r3, #0
8005b04: d004 beq.n 8005b10 <DMA_SetConfig+0x2a>
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8005b06: 68fb ldr r3, [r7, #12]
8005b08: 6d9b ldr r3, [r3, #88] @ 0x58
8005b0a: 68fa ldr r2, [r7, #12]
8005b0c: 6dd2 ldr r2, [r2, #92] @ 0x5c
8005b0e: 605a str r2, [r3, #4]
}
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
8005b10: 68fb ldr r3, [r7, #12]
8005b12: 6c5b ldr r3, [r3, #68] @ 0x44
8005b14: f003 021c and.w r2, r3, #28
8005b18: 68fb ldr r3, [r7, #12]
8005b1a: 6c1b ldr r3, [r3, #64] @ 0x40
8005b1c: 2101 movs r1, #1
8005b1e: fa01 f202 lsl.w r2, r1, r2
8005b22: 605a str r2, [r3, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8005b24: 68fb ldr r3, [r7, #12]
8005b26: 681b ldr r3, [r3, #0]
8005b28: 683a ldr r2, [r7, #0]
8005b2a: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8005b2c: 68fb ldr r3, [r7, #12]
8005b2e: 689b ldr r3, [r3, #8]
8005b30: 2b10 cmp r3, #16
8005b32: d108 bne.n 8005b46 <DMA_SetConfig+0x60>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8005b34: 68fb ldr r3, [r7, #12]
8005b36: 681b ldr r3, [r3, #0]
8005b38: 687a ldr r2, [r7, #4]
8005b3a: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8005b3c: 68fb ldr r3, [r7, #12]
8005b3e: 681b ldr r3, [r3, #0]
8005b40: 68ba ldr r2, [r7, #8]
8005b42: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8005b44: e007 b.n 8005b56 <DMA_SetConfig+0x70>
hdma->Instance->CPAR = SrcAddress;
8005b46: 68fb ldr r3, [r7, #12]
8005b48: 681b ldr r3, [r3, #0]
8005b4a: 68ba ldr r2, [r7, #8]
8005b4c: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8005b4e: 68fb ldr r3, [r7, #12]
8005b50: 681b ldr r3, [r3, #0]
8005b52: 687a ldr r2, [r7, #4]
8005b54: 60da str r2, [r3, #12]
}
8005b56: bf00 nop
8005b58: 3714 adds r7, #20
8005b5a: 46bd mov sp, r7
8005b5c: f85d 7b04 ldr.w r7, [sp], #4
8005b60: 4770 bx lr
...
08005b64 <DMA_CalcDMAMUXChannelBaseAndMask>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
8005b64: b480 push {r7}
8005b66: b085 sub sp, #20
8005b68: af00 add r7, sp, #0
8005b6a: 6078 str r0, [r7, #4]
uint32_t channel_number;
/* check if instance is not outside the DMA channel range */
#if defined(DMA2)
if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
8005b6c: 687b ldr r3, [r7, #4]
8005b6e: 681b ldr r3, [r3, #0]
8005b70: 461a mov r2, r3
8005b72: 4b17 ldr r3, [pc, #92] @ (8005bd0 <DMA_CalcDMAMUXChannelBaseAndMask+0x6c>)
8005b74: 429a cmp r2, r3
8005b76: d80a bhi.n 8005b8e <DMA_CalcDMAMUXChannelBaseAndMask+0x2a>
{
/* DMA1 */
hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
8005b78: 687b ldr r3, [r7, #4]
8005b7a: 6c5b ldr r3, [r3, #68] @ 0x44
8005b7c: 089b lsrs r3, r3, #2
8005b7e: 009b lsls r3, r3, #2
8005b80: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000
8005b84: f503 3302 add.w r3, r3, #133120 @ 0x20800
8005b88: 687a ldr r2, [r7, #4]
8005b8a: 6493 str r3, [r2, #72] @ 0x48
8005b8c: e007 b.n 8005b9e <DMA_CalcDMAMUXChannelBaseAndMask+0x3a>
}
else
{
/* DMA2 */
hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
8005b8e: 687b ldr r3, [r7, #4]
8005b90: 6c5b ldr r3, [r3, #68] @ 0x44
8005b92: 089b lsrs r3, r3, #2
8005b94: 009a lsls r2, r3, #2
8005b96: 4b0f ldr r3, [pc, #60] @ (8005bd4 <DMA_CalcDMAMUXChannelBaseAndMask+0x70>)
8005b98: 4413 add r3, r2
8005b9a: 687a ldr r2, [r7, #4]
8005b9c: 6493 str r3, [r2, #72] @ 0x48
}
#else
/* DMA1 */
hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
#endif /* DMA2 */
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
8005b9e: 687b ldr r3, [r7, #4]
8005ba0: 681b ldr r3, [r3, #0]
8005ba2: b2db uxtb r3, r3
8005ba4: 3b08 subs r3, #8
8005ba6: 4a0c ldr r2, [pc, #48] @ (8005bd8 <DMA_CalcDMAMUXChannelBaseAndMask+0x74>)
8005ba8: fba2 2303 umull r2, r3, r2, r3
8005bac: 091b lsrs r3, r3, #4
8005bae: 60fb str r3, [r7, #12]
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
8005bb0: 687b ldr r3, [r7, #4]
8005bb2: 4a0a ldr r2, [pc, #40] @ (8005bdc <DMA_CalcDMAMUXChannelBaseAndMask+0x78>)
8005bb4: 64da str r2, [r3, #76] @ 0x4c
/* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
8005bb6: 68fb ldr r3, [r7, #12]
8005bb8: f003 031f and.w r3, r3, #31
8005bbc: 2201 movs r2, #1
8005bbe: 409a lsls r2, r3
8005bc0: 687b ldr r3, [r7, #4]
8005bc2: 651a str r2, [r3, #80] @ 0x50
}
8005bc4: bf00 nop
8005bc6: 3714 adds r7, #20
8005bc8: 46bd mov sp, r7
8005bca: f85d 7b04 ldr.w r7, [sp], #4
8005bce: 4770 bx lr
8005bd0: 40020407 .word 0x40020407
8005bd4: 4002081c .word 0x4002081c
8005bd8: cccccccd .word 0xcccccccd
8005bdc: 40020880 .word 0x40020880
08005be0 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
* the configuration information for the specified DMA Channel.
* @retval None
*/
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
8005be0: b480 push {r7}
8005be2: b085 sub sp, #20
8005be4: af00 add r7, sp, #0
8005be6: 6078 str r0, [r7, #4]
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
8005be8: 687b ldr r3, [r7, #4]
8005bea: 685b ldr r3, [r3, #4]
8005bec: f003 033f and.w r3, r3, #63 @ 0x3f
8005bf0: 60fb str r3, [r7, #12]
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
8005bf2: 68fa ldr r2, [r7, #12]
8005bf4: 4b0b ldr r3, [pc, #44] @ (8005c24 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
8005bf6: 4413 add r3, r2
8005bf8: 009b lsls r3, r3, #2
8005bfa: 461a mov r2, r3
8005bfc: 687b ldr r3, [r7, #4]
8005bfe: 655a str r2, [r3, #84] @ 0x54
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
8005c00: 687b ldr r3, [r7, #4]
8005c02: 4a09 ldr r2, [pc, #36] @ (8005c28 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x48>)
8005c04: 659a str r2, [r3, #88] @ 0x58
/* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
8005c06: 68fb ldr r3, [r7, #12]
8005c08: 3b01 subs r3, #1
8005c0a: f003 0303 and.w r3, r3, #3
8005c0e: 2201 movs r2, #1
8005c10: 409a lsls r2, r3
8005c12: 687b ldr r3, [r7, #4]
8005c14: 65da str r2, [r3, #92] @ 0x5c
}
8005c16: bf00 nop
8005c18: 3714 adds r7, #20
8005c1a: 46bd mov sp, r7
8005c1c: f85d 7b04 ldr.w r7, [sp], #4
8005c20: 4770 bx lr
8005c22: bf00 nop
8005c24: 1000823f .word 0x1000823f
8005c28: 40020940 .word 0x40020940
08005c2c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init)
{
8005c2c: b480 push {r7}
8005c2e: b087 sub sp, #28
8005c30: af00 add r7, sp, #0
8005c32: 6078 str r0, [r7, #4]
8005c34: 6039 str r1, [r7, #0]
uint32_t position = 0x00UL;
8005c36: 2300 movs r3, #0
8005c38: 617b str r3, [r7, #20]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8005c3a: e14c b.n 8005ed6 <HAL_GPIO_Init+0x2aa>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8005c3c: 683b ldr r3, [r7, #0]
8005c3e: 681a ldr r2, [r3, #0]
8005c40: 2101 movs r1, #1
8005c42: 697b ldr r3, [r7, #20]
8005c44: fa01 f303 lsl.w r3, r1, r3
8005c48: 4013 ands r3, r2
8005c4a: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8005c4c: 68fb ldr r3, [r7, #12]
8005c4e: 2b00 cmp r3, #0
8005c50: f000 813e beq.w 8005ed0 <HAL_GPIO_Init+0x2a4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8005c54: 683b ldr r3, [r7, #0]
8005c56: 685b ldr r3, [r3, #4]
8005c58: f003 0303 and.w r3, r3, #3
8005c5c: 2b01 cmp r3, #1
8005c5e: d005 beq.n 8005c6c <HAL_GPIO_Init+0x40>
8005c60: 683b ldr r3, [r7, #0]
8005c62: 685b ldr r3, [r3, #4]
8005c64: f003 0303 and.w r3, r3, #3
8005c68: 2b02 cmp r3, #2
8005c6a: d130 bne.n 8005cce <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8005c6c: 687b ldr r3, [r7, #4]
8005c6e: 689b ldr r3, [r3, #8]
8005c70: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
8005c72: 697b ldr r3, [r7, #20]
8005c74: 005b lsls r3, r3, #1
8005c76: 2203 movs r2, #3
8005c78: fa02 f303 lsl.w r3, r2, r3
8005c7c: 43db mvns r3, r3
8005c7e: 693a ldr r2, [r7, #16]
8005c80: 4013 ands r3, r2
8005c82: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8005c84: 683b ldr r3, [r7, #0]
8005c86: 68da ldr r2, [r3, #12]
8005c88: 697b ldr r3, [r7, #20]
8005c8a: 005b lsls r3, r3, #1
8005c8c: fa02 f303 lsl.w r3, r2, r3
8005c90: 693a ldr r2, [r7, #16]
8005c92: 4313 orrs r3, r2
8005c94: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8005c96: 687b ldr r3, [r7, #4]
8005c98: 693a ldr r2, [r7, #16]
8005c9a: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8005c9c: 687b ldr r3, [r7, #4]
8005c9e: 685b ldr r3, [r3, #4]
8005ca0: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8005ca2: 2201 movs r2, #1
8005ca4: 697b ldr r3, [r7, #20]
8005ca6: fa02 f303 lsl.w r3, r2, r3
8005caa: 43db mvns r3, r3
8005cac: 693a ldr r2, [r7, #16]
8005cae: 4013 ands r3, r2
8005cb0: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8005cb2: 683b ldr r3, [r7, #0]
8005cb4: 685b ldr r3, [r3, #4]
8005cb6: 091b lsrs r3, r3, #4
8005cb8: f003 0201 and.w r2, r3, #1
8005cbc: 697b ldr r3, [r7, #20]
8005cbe: fa02 f303 lsl.w r3, r2, r3
8005cc2: 693a ldr r2, [r7, #16]
8005cc4: 4313 orrs r3, r2
8005cc6: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8005cc8: 687b ldr r3, [r7, #4]
8005cca: 693a ldr r2, [r7, #16]
8005ccc: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8005cce: 683b ldr r3, [r7, #0]
8005cd0: 685b ldr r3, [r3, #4]
8005cd2: f003 0303 and.w r3, r3, #3
8005cd6: 2b03 cmp r3, #3
8005cd8: d017 beq.n 8005d0a <HAL_GPIO_Init+0xde>
{
temp = GPIOx->PUPDR;
8005cda: 687b ldr r3, [r7, #4]
8005cdc: 68db ldr r3, [r3, #12]
8005cde: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8005ce0: 697b ldr r3, [r7, #20]
8005ce2: 005b lsls r3, r3, #1
8005ce4: 2203 movs r2, #3
8005ce6: fa02 f303 lsl.w r3, r2, r3
8005cea: 43db mvns r3, r3
8005cec: 693a ldr r2, [r7, #16]
8005cee: 4013 ands r3, r2
8005cf0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8005cf2: 683b ldr r3, [r7, #0]
8005cf4: 689a ldr r2, [r3, #8]
8005cf6: 697b ldr r3, [r7, #20]
8005cf8: 005b lsls r3, r3, #1
8005cfa: fa02 f303 lsl.w r3, r2, r3
8005cfe: 693a ldr r2, [r7, #16]
8005d00: 4313 orrs r3, r2
8005d02: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8005d04: 687b ldr r3, [r7, #4]
8005d06: 693a ldr r2, [r7, #16]
8005d08: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8005d0a: 683b ldr r3, [r7, #0]
8005d0c: 685b ldr r3, [r3, #4]
8005d0e: f003 0303 and.w r3, r3, #3
8005d12: 2b02 cmp r3, #2
8005d14: d123 bne.n 8005d5e <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8005d16: 697b ldr r3, [r7, #20]
8005d18: 08da lsrs r2, r3, #3
8005d1a: 687b ldr r3, [r7, #4]
8005d1c: 3208 adds r2, #8
8005d1e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8005d22: 613b str r3, [r7, #16]
temp &= ~(0xFUL << ((position & 0x07UL) * 4UL));
8005d24: 697b ldr r3, [r7, #20]
8005d26: f003 0307 and.w r3, r3, #7
8005d2a: 009b lsls r3, r3, #2
8005d2c: 220f movs r2, #15
8005d2e: fa02 f303 lsl.w r3, r2, r3
8005d32: 43db mvns r3, r3
8005d34: 693a ldr r2, [r7, #16]
8005d36: 4013 ands r3, r2
8005d38: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8005d3a: 683b ldr r3, [r7, #0]
8005d3c: 691a ldr r2, [r3, #16]
8005d3e: 697b ldr r3, [r7, #20]
8005d40: f003 0307 and.w r3, r3, #7
8005d44: 009b lsls r3, r3, #2
8005d46: fa02 f303 lsl.w r3, r2, r3
8005d4a: 693a ldr r2, [r7, #16]
8005d4c: 4313 orrs r3, r2
8005d4e: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8005d50: 697b ldr r3, [r7, #20]
8005d52: 08da lsrs r2, r3, #3
8005d54: 687b ldr r3, [r7, #4]
8005d56: 3208 adds r2, #8
8005d58: 6939 ldr r1, [r7, #16]
8005d5a: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8005d5e: 687b ldr r3, [r7, #4]
8005d60: 681b ldr r3, [r3, #0]
8005d62: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8005d64: 697b ldr r3, [r7, #20]
8005d66: 005b lsls r3, r3, #1
8005d68: 2203 movs r2, #3
8005d6a: fa02 f303 lsl.w r3, r2, r3
8005d6e: 43db mvns r3, r3
8005d70: 693a ldr r2, [r7, #16]
8005d72: 4013 ands r3, r2
8005d74: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8005d76: 683b ldr r3, [r7, #0]
8005d78: 685b ldr r3, [r3, #4]
8005d7a: f003 0203 and.w r2, r3, #3
8005d7e: 697b ldr r3, [r7, #20]
8005d80: 005b lsls r3, r3, #1
8005d82: fa02 f303 lsl.w r3, r2, r3
8005d86: 693a ldr r2, [r7, #16]
8005d88: 4313 orrs r3, r2
8005d8a: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8005d8c: 687b ldr r3, [r7, #4]
8005d8e: 693a ldr r2, [r7, #16]
8005d90: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8005d92: 683b ldr r3, [r7, #0]
8005d94: 685b ldr r3, [r3, #4]
8005d96: f403 3340 and.w r3, r3, #196608 @ 0x30000
8005d9a: 2b00 cmp r3, #0
8005d9c: f000 8098 beq.w 8005ed0 <HAL_GPIO_Init+0x2a4>
{
temp = SYSCFG->EXTICR[position >> 2u];
8005da0: 4a54 ldr r2, [pc, #336] @ (8005ef4 <HAL_GPIO_Init+0x2c8>)
8005da2: 697b ldr r3, [r7, #20]
8005da4: 089b lsrs r3, r3, #2
8005da6: 3302 adds r3, #2
8005da8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8005dac: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8005dae: 697b ldr r3, [r7, #20]
8005db0: f003 0303 and.w r3, r3, #3
8005db4: 009b lsls r3, r3, #2
8005db6: 220f movs r2, #15
8005db8: fa02 f303 lsl.w r3, r2, r3
8005dbc: 43db mvns r3, r3
8005dbe: 693a ldr r2, [r7, #16]
8005dc0: 4013 ands r3, r2
8005dc2: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8005dc4: 687b ldr r3, [r7, #4]
8005dc6: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8005dca: d019 beq.n 8005e00 <HAL_GPIO_Init+0x1d4>
8005dcc: 687b ldr r3, [r7, #4]
8005dce: 4a4a ldr r2, [pc, #296] @ (8005ef8 <HAL_GPIO_Init+0x2cc>)
8005dd0: 4293 cmp r3, r2
8005dd2: d013 beq.n 8005dfc <HAL_GPIO_Init+0x1d0>
8005dd4: 687b ldr r3, [r7, #4]
8005dd6: 4a49 ldr r2, [pc, #292] @ (8005efc <HAL_GPIO_Init+0x2d0>)
8005dd8: 4293 cmp r3, r2
8005dda: d00d beq.n 8005df8 <HAL_GPIO_Init+0x1cc>
8005ddc: 687b ldr r3, [r7, #4]
8005dde: 4a48 ldr r2, [pc, #288] @ (8005f00 <HAL_GPIO_Init+0x2d4>)
8005de0: 4293 cmp r3, r2
8005de2: d007 beq.n 8005df4 <HAL_GPIO_Init+0x1c8>
8005de4: 687b ldr r3, [r7, #4]
8005de6: 4a47 ldr r2, [pc, #284] @ (8005f04 <HAL_GPIO_Init+0x2d8>)
8005de8: 4293 cmp r3, r2
8005dea: d101 bne.n 8005df0 <HAL_GPIO_Init+0x1c4>
8005dec: 2304 movs r3, #4
8005dee: e008 b.n 8005e02 <HAL_GPIO_Init+0x1d6>
8005df0: 2307 movs r3, #7
8005df2: e006 b.n 8005e02 <HAL_GPIO_Init+0x1d6>
8005df4: 2303 movs r3, #3
8005df6: e004 b.n 8005e02 <HAL_GPIO_Init+0x1d6>
8005df8: 2302 movs r3, #2
8005dfa: e002 b.n 8005e02 <HAL_GPIO_Init+0x1d6>
8005dfc: 2301 movs r3, #1
8005dfe: e000 b.n 8005e02 <HAL_GPIO_Init+0x1d6>
8005e00: 2300 movs r3, #0
8005e02: 697a ldr r2, [r7, #20]
8005e04: f002 0203 and.w r2, r2, #3
8005e08: 0092 lsls r2, r2, #2
8005e0a: 4093 lsls r3, r2
8005e0c: 693a ldr r2, [r7, #16]
8005e0e: 4313 orrs r3, r2
8005e10: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8005e12: 4938 ldr r1, [pc, #224] @ (8005ef4 <HAL_GPIO_Init+0x2c8>)
8005e14: 697b ldr r3, [r7, #20]
8005e16: 089b lsrs r3, r3, #2
8005e18: 3302 adds r3, #2
8005e1a: 693a ldr r2, [r7, #16]
8005e1c: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8005e20: 4b39 ldr r3, [pc, #228] @ (8005f08 <HAL_GPIO_Init+0x2dc>)
8005e22: 681b ldr r3, [r3, #0]
8005e24: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8005e26: 68fb ldr r3, [r7, #12]
8005e28: 43db mvns r3, r3
8005e2a: 693a ldr r2, [r7, #16]
8005e2c: 4013 ands r3, r2
8005e2e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8005e30: 683b ldr r3, [r7, #0]
8005e32: 685b ldr r3, [r3, #4]
8005e34: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8005e38: 2b00 cmp r3, #0
8005e3a: d003 beq.n 8005e44 <HAL_GPIO_Init+0x218>
{
temp |= iocurrent;
8005e3c: 693a ldr r2, [r7, #16]
8005e3e: 68fb ldr r3, [r7, #12]
8005e40: 4313 orrs r3, r2
8005e42: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8005e44: 4a30 ldr r2, [pc, #192] @ (8005f08 <HAL_GPIO_Init+0x2dc>)
8005e46: 693b ldr r3, [r7, #16]
8005e48: 6013 str r3, [r2, #0]
temp = EXTI->FTSR1;
8005e4a: 4b2f ldr r3, [pc, #188] @ (8005f08 <HAL_GPIO_Init+0x2dc>)
8005e4c: 685b ldr r3, [r3, #4]
8005e4e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8005e50: 68fb ldr r3, [r7, #12]
8005e52: 43db mvns r3, r3
8005e54: 693a ldr r2, [r7, #16]
8005e56: 4013 ands r3, r2
8005e58: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8005e5a: 683b ldr r3, [r7, #0]
8005e5c: 685b ldr r3, [r3, #4]
8005e5e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8005e62: 2b00 cmp r3, #0
8005e64: d003 beq.n 8005e6e <HAL_GPIO_Init+0x242>
{
temp |= iocurrent;
8005e66: 693a ldr r2, [r7, #16]
8005e68: 68fb ldr r3, [r7, #12]
8005e6a: 4313 orrs r3, r2
8005e6c: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8005e6e: 4a26 ldr r2, [pc, #152] @ (8005f08 <HAL_GPIO_Init+0x2dc>)
8005e70: 693b ldr r3, [r7, #16]
8005e72: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
8005e74: 4b24 ldr r3, [pc, #144] @ (8005f08 <HAL_GPIO_Init+0x2dc>)
8005e76: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8005e7a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8005e7c: 68fb ldr r3, [r7, #12]
8005e7e: 43db mvns r3, r3
8005e80: 693a ldr r2, [r7, #16]
8005e82: 4013 ands r3, r2
8005e84: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8005e86: 683b ldr r3, [r7, #0]
8005e88: 685b ldr r3, [r3, #4]
8005e8a: f403 3380 and.w r3, r3, #65536 @ 0x10000
8005e8e: 2b00 cmp r3, #0
8005e90: d003 beq.n 8005e9a <HAL_GPIO_Init+0x26e>
{
temp |= iocurrent;
8005e92: 693a ldr r2, [r7, #16]
8005e94: 68fb ldr r3, [r7, #12]
8005e96: 4313 orrs r3, r2
8005e98: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8005e9a: 4a1b ldr r2, [pc, #108] @ (8005f08 <HAL_GPIO_Init+0x2dc>)
8005e9c: 693b ldr r3, [r7, #16]
8005e9e: f8c2 3080 str.w r3, [r2, #128] @ 0x80
temp = EXTI->EMR1;
8005ea2: 4b19 ldr r3, [pc, #100] @ (8005f08 <HAL_GPIO_Init+0x2dc>)
8005ea4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8005ea8: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8005eaa: 68fb ldr r3, [r7, #12]
8005eac: 43db mvns r3, r3
8005eae: 693a ldr r2, [r7, #16]
8005eb0: 4013 ands r3, r2
8005eb2: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8005eb4: 683b ldr r3, [r7, #0]
8005eb6: 685b ldr r3, [r3, #4]
8005eb8: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005ebc: 2b00 cmp r3, #0
8005ebe: d003 beq.n 8005ec8 <HAL_GPIO_Init+0x29c>
{
temp |= iocurrent;
8005ec0: 693a ldr r2, [r7, #16]
8005ec2: 68fb ldr r3, [r7, #12]
8005ec4: 4313 orrs r3, r2
8005ec6: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8005ec8: 4a0f ldr r2, [pc, #60] @ (8005f08 <HAL_GPIO_Init+0x2dc>)
8005eca: 693b ldr r3, [r7, #16]
8005ecc: f8c2 3084 str.w r3, [r2, #132] @ 0x84
}
}
position++;
8005ed0: 697b ldr r3, [r7, #20]
8005ed2: 3301 adds r3, #1
8005ed4: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8005ed6: 683b ldr r3, [r7, #0]
8005ed8: 681a ldr r2, [r3, #0]
8005eda: 697b ldr r3, [r7, #20]
8005edc: fa22 f303 lsr.w r3, r2, r3
8005ee0: 2b00 cmp r3, #0
8005ee2: f47f aeab bne.w 8005c3c <HAL_GPIO_Init+0x10>
}
}
8005ee6: bf00 nop
8005ee8: bf00 nop
8005eea: 371c adds r7, #28
8005eec: 46bd mov sp, r7
8005eee: f85d 7b04 ldr.w r7, [sp], #4
8005ef2: 4770 bx lr
8005ef4: 40010000 .word 0x40010000
8005ef8: 48000400 .word 0x48000400
8005efc: 48000800 .word 0x48000800
8005f00: 48000c00 .word 0x48000c00
8005f04: 48001000 .word 0x48001000
8005f08: 58000800 .word 0x58000800
08005f0c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8005f0c: b480 push {r7}
8005f0e: b083 sub sp, #12
8005f10: af00 add r7, sp, #0
8005f12: 6078 str r0, [r7, #4]
8005f14: 460b mov r3, r1
8005f16: 807b strh r3, [r7, #2]
8005f18: 4613 mov r3, r2
8005f1a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8005f1c: 787b ldrb r3, [r7, #1]
8005f1e: 2b00 cmp r3, #0
8005f20: d003 beq.n 8005f2a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8005f22: 887a ldrh r2, [r7, #2]
8005f24: 687b ldr r3, [r7, #4]
8005f26: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8005f28: e002 b.n 8005f30 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8005f2a: 887a ldrh r2, [r7, #2]
8005f2c: 687b ldr r3, [r7, #4]
8005f2e: 629a str r2, [r3, #40] @ 0x28
}
8005f30: bf00 nop
8005f32: 370c adds r7, #12
8005f34: 46bd mov sp, r7
8005f36: f85d 7b04 ldr.w r7, [sp], #4
8005f3a: 4770 bx lr
08005f3c <HAL_HSEM_IRQHandler>:
/**
* @brief This function handles HSEM interrupt request
* @retval None
*/
void HAL_HSEM_IRQHandler(void)
{
8005f3c: b580 push {r7, lr}
8005f3e: b082 sub sp, #8
8005f40: af00 add r7, sp, #0
uint32_t statusreg;
/* Get the list of masked freed semaphores*/
statusreg = HSEM_COMMON->MISR;
8005f42: 4b0a ldr r3, [pc, #40] @ (8005f6c <HAL_HSEM_IRQHandler+0x30>)
8005f44: 68db ldr r3, [r3, #12]
8005f46: 607b str r3, [r7, #4]
/*Disable Interrupts*/
HSEM_COMMON->IER &= ~((uint32_t)statusreg);
8005f48: 4b08 ldr r3, [pc, #32] @ (8005f6c <HAL_HSEM_IRQHandler+0x30>)
8005f4a: 681a ldr r2, [r3, #0]
8005f4c: 687b ldr r3, [r7, #4]
8005f4e: 43db mvns r3, r3
8005f50: 4906 ldr r1, [pc, #24] @ (8005f6c <HAL_HSEM_IRQHandler+0x30>)
8005f52: 4013 ands r3, r2
8005f54: 600b str r3, [r1, #0]
/*Clear Flags*/
HSEM_COMMON->ICR = ((uint32_t)statusreg);
8005f56: 4a05 ldr r2, [pc, #20] @ (8005f6c <HAL_HSEM_IRQHandler+0x30>)
8005f58: 687b ldr r3, [r7, #4]
8005f5a: 6053 str r3, [r2, #4]
/* Call FreeCallback */
HAL_HSEM_FreeCallback(statusreg);
8005f5c: 6878 ldr r0, [r7, #4]
8005f5e: f000 f807 bl 8005f70 <HAL_HSEM_FreeCallback>
}
8005f62: bf00 nop
8005f64: 3708 adds r7, #8
8005f66: 46bd mov sp, r7
8005f68: bd80 pop {r7, pc}
8005f6a: bf00 nop
8005f6c: 58001500 .word 0x58001500
08005f70 <HAL_HSEM_FreeCallback>:
* @brief Semaphore Released Callback.
* @param SemMask: Mask of Released semaphores
* @retval None
*/
__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
{
8005f70: b480 push {r7}
8005f72: b083 sub sp, #12
8005f74: af00 add r7, sp, #0
8005f76: 6078 str r0, [r7, #4]
UNUSED(SemMask);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HSEM_FreeCallback can be implemented in the user file
*/
}
8005f78: bf00 nop
8005f7a: 370c adds r7, #12
8005f7c: 46bd mov sp, r7
8005f7e: f85d 7b04 ldr.w r7, [sp], #4
8005f82: 4770 bx lr
08005f84 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8005f84: b580 push {r7, lr}
8005f86: b082 sub sp, #8
8005f88: af00 add r7, sp, #0
8005f8a: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8005f8c: 687b ldr r3, [r7, #4]
8005f8e: 2b00 cmp r3, #0
8005f90: d101 bne.n 8005f96 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8005f92: 2301 movs r3, #1
8005f94: e08d b.n 80060b2 <HAL_I2C_Init+0x12e>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8005f96: 687b ldr r3, [r7, #4]
8005f98: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005f9c: b2db uxtb r3, r3
8005f9e: 2b00 cmp r3, #0
8005fa0: d106 bne.n 8005fb0 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8005fa2: 687b ldr r3, [r7, #4]
8005fa4: 2200 movs r2, #0
8005fa6: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
8005faa: 6878 ldr r0, [r7, #4]
8005fac: f7fe fd4c bl 8004a48 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8005fb0: 687b ldr r3, [r7, #4]
8005fb2: 2224 movs r2, #36 @ 0x24
8005fb4: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8005fb8: 687b ldr r3, [r7, #4]
8005fba: 681b ldr r3, [r3, #0]
8005fbc: 681a ldr r2, [r3, #0]
8005fbe: 687b ldr r3, [r7, #4]
8005fc0: 681b ldr r3, [r3, #0]
8005fc2: f022 0201 bic.w r2, r2, #1
8005fc6: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8005fc8: 687b ldr r3, [r7, #4]
8005fca: 685a ldr r2, [r3, #4]
8005fcc: 687b ldr r3, [r7, #4]
8005fce: 681b ldr r3, [r3, #0]
8005fd0: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
8005fd4: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8005fd6: 687b ldr r3, [r7, #4]
8005fd8: 681b ldr r3, [r3, #0]
8005fda: 689a ldr r2, [r3, #8]
8005fdc: 687b ldr r3, [r7, #4]
8005fde: 681b ldr r3, [r3, #0]
8005fe0: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8005fe4: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8005fe6: 687b ldr r3, [r7, #4]
8005fe8: 68db ldr r3, [r3, #12]
8005fea: 2b01 cmp r3, #1
8005fec: d107 bne.n 8005ffe <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
8005fee: 687b ldr r3, [r7, #4]
8005ff0: 689a ldr r2, [r3, #8]
8005ff2: 687b ldr r3, [r7, #4]
8005ff4: 681b ldr r3, [r3, #0]
8005ff6: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8005ffa: 609a str r2, [r3, #8]
8005ffc: e006 b.n 800600c <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
8005ffe: 687b ldr r3, [r7, #4]
8006000: 689a ldr r2, [r3, #8]
8006002: 687b ldr r3, [r7, #4]
8006004: 681b ldr r3, [r3, #0]
8006006: f442 4204 orr.w r2, r2, #33792 @ 0x8400
800600a: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
800600c: 687b ldr r3, [r7, #4]
800600e: 68db ldr r3, [r3, #12]
8006010: 2b02 cmp r3, #2
8006012: d108 bne.n 8006026 <HAL_I2C_Init+0xa2>
{
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8006014: 687b ldr r3, [r7, #4]
8006016: 681b ldr r3, [r3, #0]
8006018: 685a ldr r2, [r3, #4]
800601a: 687b ldr r3, [r7, #4]
800601c: 681b ldr r3, [r3, #0]
800601e: f442 6200 orr.w r2, r2, #2048 @ 0x800
8006022: 605a str r2, [r3, #4]
8006024: e007 b.n 8006036 <HAL_I2C_Init+0xb2>
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
8006026: 687b ldr r3, [r7, #4]
8006028: 681b ldr r3, [r3, #0]
800602a: 685a ldr r2, [r3, #4]
800602c: 687b ldr r3, [r7, #4]
800602e: 681b ldr r3, [r3, #0]
8006030: f422 6200 bic.w r2, r2, #2048 @ 0x800
8006034: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8006036: 687b ldr r3, [r7, #4]
8006038: 681b ldr r3, [r3, #0]
800603a: 685b ldr r3, [r3, #4]
800603c: 687a ldr r2, [r7, #4]
800603e: 6812 ldr r2, [r2, #0]
8006040: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8006044: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8006048: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
800604a: 687b ldr r3, [r7, #4]
800604c: 681b ldr r3, [r3, #0]
800604e: 68da ldr r2, [r3, #12]
8006050: 687b ldr r3, [r7, #4]
8006052: 681b ldr r3, [r3, #0]
8006054: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8006058: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
800605a: 687b ldr r3, [r7, #4]
800605c: 691a ldr r2, [r3, #16]
800605e: 687b ldr r3, [r7, #4]
8006060: 695b ldr r3, [r3, #20]
8006062: ea42 0103 orr.w r1, r2, r3
(hi2c->Init.OwnAddress2Masks << 8));
8006066: 687b ldr r3, [r7, #4]
8006068: 699b ldr r3, [r3, #24]
800606a: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
800606c: 687b ldr r3, [r7, #4]
800606e: 681b ldr r3, [r3, #0]
8006070: 430a orrs r2, r1
8006072: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8006074: 687b ldr r3, [r7, #4]
8006076: 69d9 ldr r1, [r3, #28]
8006078: 687b ldr r3, [r7, #4]
800607a: 6a1a ldr r2, [r3, #32]
800607c: 687b ldr r3, [r7, #4]
800607e: 681b ldr r3, [r3, #0]
8006080: 430a orrs r2, r1
8006082: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8006084: 687b ldr r3, [r7, #4]
8006086: 681b ldr r3, [r3, #0]
8006088: 681a ldr r2, [r3, #0]
800608a: 687b ldr r3, [r7, #4]
800608c: 681b ldr r3, [r3, #0]
800608e: f042 0201 orr.w r2, r2, #1
8006092: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8006094: 687b ldr r3, [r7, #4]
8006096: 2200 movs r2, #0
8006098: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
800609a: 687b ldr r3, [r7, #4]
800609c: 2220 movs r2, #32
800609e: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
80060a2: 687b ldr r3, [r7, #4]
80060a4: 2200 movs r2, #0
80060a6: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80060a8: 687b ldr r3, [r7, #4]
80060aa: 2200 movs r2, #0
80060ac: f883 2042 strb.w r2, [r3, #66] @ 0x42
return HAL_OK;
80060b0: 2300 movs r3, #0
}
80060b2: 4618 mov r0, r3
80060b4: 3708 adds r7, #8
80060b6: 46bd mov sp, r7
80060b8: bd80 pop {r7, pc}
...
080060bc <HAL_I2C_Mem_Write_DMA>:
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
80060bc: b580 push {r7, lr}
80060be: b088 sub sp, #32
80060c0: af02 add r7, sp, #8
80060c2: 60f8 str r0, [r7, #12]
80060c4: 4608 mov r0, r1
80060c6: 4611 mov r1, r2
80060c8: 461a mov r2, r3
80060ca: 4603 mov r3, r0
80060cc: 817b strh r3, [r7, #10]
80060ce: 460b mov r3, r1
80060d0: 813b strh r3, [r7, #8]
80060d2: 4613 mov r3, r2
80060d4: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
80060d6: 68fb ldr r3, [r7, #12]
80060d8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80060dc: b2db uxtb r3, r3
80060de: 2b20 cmp r3, #32
80060e0: f040 80c3 bne.w 800626a <HAL_I2C_Mem_Write_DMA+0x1ae>
{
if ((pData == NULL) || (Size == 0U))
80060e4: 6a3b ldr r3, [r7, #32]
80060e6: 2b00 cmp r3, #0
80060e8: d002 beq.n 80060f0 <HAL_I2C_Mem_Write_DMA+0x34>
80060ea: 8cbb ldrh r3, [r7, #36] @ 0x24
80060ec: 2b00 cmp r3, #0
80060ee: d105 bne.n 80060fc <HAL_I2C_Mem_Write_DMA+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
80060f0: 68fb ldr r3, [r7, #12]
80060f2: f44f 7200 mov.w r2, #512 @ 0x200
80060f6: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
80060f8: 2301 movs r3, #1
80060fa: e0b7 b.n 800626c <HAL_I2C_Mem_Write_DMA+0x1b0>
}
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
80060fc: 68fb ldr r3, [r7, #12]
80060fe: 681b ldr r3, [r3, #0]
8006100: 699b ldr r3, [r3, #24]
8006102: f403 4300 and.w r3, r3, #32768 @ 0x8000
8006106: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800610a: d101 bne.n 8006110 <HAL_I2C_Mem_Write_DMA+0x54>
{
return HAL_BUSY;
800610c: 2302 movs r3, #2
800610e: e0ad b.n 800626c <HAL_I2C_Mem_Write_DMA+0x1b0>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8006110: 68fb ldr r3, [r7, #12]
8006112: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8006116: 2b01 cmp r3, #1
8006118: d101 bne.n 800611e <HAL_I2C_Mem_Write_DMA+0x62>
800611a: 2302 movs r3, #2
800611c: e0a6 b.n 800626c <HAL_I2C_Mem_Write_DMA+0x1b0>
800611e: 68fb ldr r3, [r7, #12]
8006120: 2201 movs r2, #1
8006122: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY_TX;
8006126: 68fb ldr r3, [r7, #12]
8006128: 2221 movs r2, #33 @ 0x21
800612a: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
800612e: 68fb ldr r3, [r7, #12]
8006130: 2240 movs r2, #64 @ 0x40
8006132: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8006136: 68fb ldr r3, [r7, #12]
8006138: 2200 movs r2, #0
800613a: 645a str r2, [r3, #68] @ 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
800613c: 68fb ldr r3, [r7, #12]
800613e: 6a3a ldr r2, [r7, #32]
8006140: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8006142: 68fb ldr r3, [r7, #12]
8006144: 8cba ldrh r2, [r7, #36] @ 0x24
8006146: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8006148: 68fb ldr r3, [r7, #12]
800614a: 4a4a ldr r2, [pc, #296] @ (8006274 <HAL_I2C_Mem_Write_DMA+0x1b8>)
800614c: 62da str r2, [r3, #44] @ 0x2c
hi2c->XferISR = I2C_Mem_ISR_DMA;
800614e: 68fb ldr r3, [r7, #12]
8006150: 4a49 ldr r2, [pc, #292] @ (8006278 <HAL_I2C_Mem_Write_DMA+0x1bc>)
8006152: 635a str r2, [r3, #52] @ 0x34
hi2c->Devaddress = DevAddress;
8006154: 897a ldrh r2, [r7, #10]
8006156: 68fb ldr r3, [r7, #12]
8006158: 64da str r2, [r3, #76] @ 0x4c
if (hi2c->XferCount > MAX_NBYTE_SIZE)
800615a: 68fb ldr r3, [r7, #12]
800615c: 8d5b ldrh r3, [r3, #42] @ 0x2a
800615e: b29b uxth r3, r3
8006160: 2bff cmp r3, #255 @ 0xff
8006162: d903 bls.n 800616c <HAL_I2C_Mem_Write_DMA+0xb0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8006164: 68fb ldr r3, [r7, #12]
8006166: 22ff movs r2, #255 @ 0xff
8006168: 851a strh r2, [r3, #40] @ 0x28
800616a: e004 b.n 8006176 <HAL_I2C_Mem_Write_DMA+0xba>
}
else
{
hi2c->XferSize = hi2c->XferCount;
800616c: 68fb ldr r3, [r7, #12]
800616e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006170: b29a uxth r2, r3
8006172: 68fb ldr r3, [r7, #12]
8006174: 851a strh r2, [r3, #40] @ 0x28
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8006176: 88fb ldrh r3, [r7, #6]
8006178: 2b01 cmp r3, #1
800617a: d109 bne.n 8006190 <HAL_I2C_Mem_Write_DMA+0xd4>
{
/* Prefetch Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
800617c: 893b ldrh r3, [r7, #8]
800617e: b2da uxtb r2, r3
8006180: 68fb ldr r3, [r7, #12]
8006182: 681b ldr r3, [r3, #0]
8006184: 629a str r2, [r3, #40] @ 0x28
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
8006186: 68fb ldr r3, [r7, #12]
8006188: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
800618c: 651a str r2, [r3, #80] @ 0x50
800618e: e00b b.n 80061a8 <HAL_I2C_Mem_Write_DMA+0xec>
}
/* If Memory address size is 16Bit */
else
{
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8006190: 893b ldrh r3, [r7, #8]
8006192: 0a1b lsrs r3, r3, #8
8006194: b29b uxth r3, r3
8006196: b2da uxtb r2, r3
8006198: 68fb ldr r3, [r7, #12]
800619a: 681b ldr r3, [r3, #0]
800619c: 629a str r2, [r3, #40] @ 0x28
/* Prepare Memaddress buffer for LSB part */
hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
800619e: 893b ldrh r3, [r7, #8]
80061a0: b2db uxtb r3, r3
80061a2: 461a mov r2, r3
80061a4: 68fb ldr r3, [r7, #12]
80061a6: 651a str r2, [r3, #80] @ 0x50
}
if (hi2c->hdmatx != NULL)
80061a8: 68fb ldr r3, [r7, #12]
80061aa: 6b9b ldr r3, [r3, #56] @ 0x38
80061ac: 2b00 cmp r3, #0
80061ae: d020 beq.n 80061f2 <HAL_I2C_Mem_Write_DMA+0x136>
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
80061b0: 68fb ldr r3, [r7, #12]
80061b2: 6b9b ldr r3, [r3, #56] @ 0x38
80061b4: 4a31 ldr r2, [pc, #196] @ (800627c <HAL_I2C_Mem_Write_DMA+0x1c0>)
80061b6: 62da str r2, [r3, #44] @ 0x2c
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
80061b8: 68fb ldr r3, [r7, #12]
80061ba: 6b9b ldr r3, [r3, #56] @ 0x38
80061bc: 4a30 ldr r2, [pc, #192] @ (8006280 <HAL_I2C_Mem_Write_DMA+0x1c4>)
80061be: 635a str r2, [r3, #52] @ 0x34
/* Set the unused DMA callbacks to NULL */
hi2c->hdmatx->XferHalfCpltCallback = NULL;
80061c0: 68fb ldr r3, [r7, #12]
80061c2: 6b9b ldr r3, [r3, #56] @ 0x38
80061c4: 2200 movs r2, #0
80061c6: 631a str r2, [r3, #48] @ 0x30
hi2c->hdmatx->XferAbortCallback = NULL;
80061c8: 68fb ldr r3, [r7, #12]
80061ca: 6b9b ldr r3, [r3, #56] @ 0x38
80061cc: 2200 movs r2, #0
80061ce: 639a str r2, [r3, #56] @ 0x38
/* Enable the DMA channel */
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
80061d0: 68fb ldr r3, [r7, #12]
80061d2: 6b98 ldr r0, [r3, #56] @ 0x38
80061d4: 6a39 ldr r1, [r7, #32]
80061d6: 68fb ldr r3, [r7, #12]
80061d8: 681b ldr r3, [r3, #0]
80061da: 3328 adds r3, #40 @ 0x28
80061dc: 461a mov r2, r3
hi2c->XferSize);
80061de: 68fb ldr r3, [r7, #12]
80061e0: 8d1b ldrh r3, [r3, #40] @ 0x28
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
80061e2: f7ff fae9 bl 80057b8 <HAL_DMA_Start_IT>
80061e6: 4603 mov r3, r0
80061e8: 75fb strb r3, [r7, #23]
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
80061ea: 7dfb ldrb r3, [r7, #23]
80061ec: 2b00 cmp r3, #0
80061ee: d128 bne.n 8006242 <HAL_I2C_Mem_Write_DMA+0x186>
80061f0: e013 b.n 800621a <HAL_I2C_Mem_Write_DMA+0x15e>
hi2c->State = HAL_I2C_STATE_READY;
80061f2: 68fb ldr r3, [r7, #12]
80061f4: 2220 movs r2, #32
80061f6: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
80061fa: 68fb ldr r3, [r7, #12]
80061fc: 2200 movs r2, #0
80061fe: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
8006202: 68fb ldr r3, [r7, #12]
8006204: 6c5b ldr r3, [r3, #68] @ 0x44
8006206: f043 0280 orr.w r2, r3, #128 @ 0x80
800620a: 68fb ldr r3, [r7, #12]
800620c: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(hi2c);
800620e: 68fb ldr r3, [r7, #12]
8006210: 2200 movs r2, #0
8006212: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8006216: 2301 movs r3, #1
8006218: e028 b.n 800626c <HAL_I2C_Mem_Write_DMA+0x1b0>
{
/* Send Slave Address and Memory Address */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
800621a: 88fb ldrh r3, [r7, #6]
800621c: b2da uxtb r2, r3
800621e: 8979 ldrh r1, [r7, #10]
8006220: 4b18 ldr r3, [pc, #96] @ (8006284 <HAL_I2C_Mem_Write_DMA+0x1c8>)
8006222: 9300 str r3, [sp, #0]
8006224: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8006228: 68f8 ldr r0, [r7, #12]
800622a: f001 fb9b bl 8007964 <I2C_TransferConfig>
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800622e: 68fb ldr r3, [r7, #12]
8006230: 2200 movs r2, #0
8006232: f883 2040 strb.w r2, [r3, #64] @ 0x40
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
8006236: 2101 movs r1, #1
8006238: 68f8 ldr r0, [r7, #12]
800623a: f001 fbc5 bl 80079c8 <I2C_Enable_IRQ>
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
return HAL_OK;
800623e: 2300 movs r3, #0
8006240: e014 b.n 800626c <HAL_I2C_Mem_Write_DMA+0x1b0>
hi2c->State = HAL_I2C_STATE_READY;
8006242: 68fb ldr r3, [r7, #12]
8006244: 2220 movs r2, #32
8006246: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
800624a: 68fb ldr r3, [r7, #12]
800624c: 2200 movs r2, #0
800624e: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
8006252: 68fb ldr r3, [r7, #12]
8006254: 6c5b ldr r3, [r3, #68] @ 0x44
8006256: f043 0210 orr.w r2, r3, #16
800625a: 68fb ldr r3, [r7, #12]
800625c: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(hi2c);
800625e: 68fb ldr r3, [r7, #12]
8006260: 2200 movs r2, #0
8006262: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8006266: 2301 movs r3, #1
8006268: e000 b.n 800626c <HAL_I2C_Mem_Write_DMA+0x1b0>
}
else
{
return HAL_BUSY;
800626a: 2302 movs r3, #2
}
}
800626c: 4618 mov r0, r3
800626e: 3718 adds r7, #24
8006270: 46bd mov sp, r7
8006272: bd80 pop {r7, pc}
8006274: ffff0000 .word 0xffff0000
8006278: 080069e5 .word 0x080069e5
800627c: 080077cf .word 0x080077cf
8006280: 080078fb .word 0x080078fb
8006284: 80002000 .word 0x80002000
08006288 <HAL_I2C_Mem_Read_DMA>:
* @param Size Amount of data to be read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
8006288: b580 push {r7, lr}
800628a: b088 sub sp, #32
800628c: af02 add r7, sp, #8
800628e: 60f8 str r0, [r7, #12]
8006290: 4608 mov r0, r1
8006292: 4611 mov r1, r2
8006294: 461a mov r2, r3
8006296: 4603 mov r3, r0
8006298: 817b strh r3, [r7, #10]
800629a: 460b mov r3, r1
800629c: 813b strh r3, [r7, #8]
800629e: 4613 mov r3, r2
80062a0: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
80062a2: 68fb ldr r3, [r7, #12]
80062a4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80062a8: b2db uxtb r3, r3
80062aa: 2b20 cmp r3, #32
80062ac: f040 80c2 bne.w 8006434 <HAL_I2C_Mem_Read_DMA+0x1ac>
{
if ((pData == NULL) || (Size == 0U))
80062b0: 6a3b ldr r3, [r7, #32]
80062b2: 2b00 cmp r3, #0
80062b4: d002 beq.n 80062bc <HAL_I2C_Mem_Read_DMA+0x34>
80062b6: 8cbb ldrh r3, [r7, #36] @ 0x24
80062b8: 2b00 cmp r3, #0
80062ba: d105 bne.n 80062c8 <HAL_I2C_Mem_Read_DMA+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
80062bc: 68fb ldr r3, [r7, #12]
80062be: f44f 7200 mov.w r2, #512 @ 0x200
80062c2: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
80062c4: 2301 movs r3, #1
80062c6: e0b6 b.n 8006436 <HAL_I2C_Mem_Read_DMA+0x1ae>
}
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
80062c8: 68fb ldr r3, [r7, #12]
80062ca: 681b ldr r3, [r3, #0]
80062cc: 699b ldr r3, [r3, #24]
80062ce: f403 4300 and.w r3, r3, #32768 @ 0x8000
80062d2: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80062d6: d101 bne.n 80062dc <HAL_I2C_Mem_Read_DMA+0x54>
{
return HAL_BUSY;
80062d8: 2302 movs r3, #2
80062da: e0ac b.n 8006436 <HAL_I2C_Mem_Read_DMA+0x1ae>
}
/* Process Locked */
__HAL_LOCK(hi2c);
80062dc: 68fb ldr r3, [r7, #12]
80062de: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80062e2: 2b01 cmp r3, #1
80062e4: d101 bne.n 80062ea <HAL_I2C_Mem_Read_DMA+0x62>
80062e6: 2302 movs r3, #2
80062e8: e0a5 b.n 8006436 <HAL_I2C_Mem_Read_DMA+0x1ae>
80062ea: 68fb ldr r3, [r7, #12]
80062ec: 2201 movs r2, #1
80062ee: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY_RX;
80062f2: 68fb ldr r3, [r7, #12]
80062f4: 2222 movs r2, #34 @ 0x22
80062f6: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
80062fa: 68fb ldr r3, [r7, #12]
80062fc: 2240 movs r2, #64 @ 0x40
80062fe: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8006302: 68fb ldr r3, [r7, #12]
8006304: 2200 movs r2, #0
8006306: 645a str r2, [r3, #68] @ 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8006308: 68fb ldr r3, [r7, #12]
800630a: 6a3a ldr r2, [r7, #32]
800630c: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
800630e: 68fb ldr r3, [r7, #12]
8006310: 8cba ldrh r2, [r7, #36] @ 0x24
8006312: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8006314: 68fb ldr r3, [r7, #12]
8006316: 4a4a ldr r2, [pc, #296] @ (8006440 <HAL_I2C_Mem_Read_DMA+0x1b8>)
8006318: 62da str r2, [r3, #44] @ 0x2c
hi2c->XferISR = I2C_Mem_ISR_DMA;
800631a: 68fb ldr r3, [r7, #12]
800631c: 4a49 ldr r2, [pc, #292] @ (8006444 <HAL_I2C_Mem_Read_DMA+0x1bc>)
800631e: 635a str r2, [r3, #52] @ 0x34
hi2c->Devaddress = DevAddress;
8006320: 897a ldrh r2, [r7, #10]
8006322: 68fb ldr r3, [r7, #12]
8006324: 64da str r2, [r3, #76] @ 0x4c
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8006326: 68fb ldr r3, [r7, #12]
8006328: 8d5b ldrh r3, [r3, #42] @ 0x2a
800632a: b29b uxth r3, r3
800632c: 2bff cmp r3, #255 @ 0xff
800632e: d903 bls.n 8006338 <HAL_I2C_Mem_Read_DMA+0xb0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8006330: 68fb ldr r3, [r7, #12]
8006332: 22ff movs r2, #255 @ 0xff
8006334: 851a strh r2, [r3, #40] @ 0x28
8006336: e004 b.n 8006342 <HAL_I2C_Mem_Read_DMA+0xba>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8006338: 68fb ldr r3, [r7, #12]
800633a: 8d5b ldrh r3, [r3, #42] @ 0x2a
800633c: b29a uxth r2, r3
800633e: 68fb ldr r3, [r7, #12]
8006340: 851a strh r2, [r3, #40] @ 0x28
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8006342: 88fb ldrh r3, [r7, #6]
8006344: 2b01 cmp r3, #1
8006346: d109 bne.n 800635c <HAL_I2C_Mem_Read_DMA+0xd4>
{
/* Prefetch Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8006348: 893b ldrh r3, [r7, #8]
800634a: b2da uxtb r2, r3
800634c: 68fb ldr r3, [r7, #12]
800634e: 681b ldr r3, [r3, #0]
8006350: 629a str r2, [r3, #40] @ 0x28
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
8006352: 68fb ldr r3, [r7, #12]
8006354: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8006358: 651a str r2, [r3, #80] @ 0x50
800635a: e00b b.n 8006374 <HAL_I2C_Mem_Read_DMA+0xec>
}
/* If Memory address size is 16Bit */
else
{
/* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
800635c: 893b ldrh r3, [r7, #8]
800635e: 0a1b lsrs r3, r3, #8
8006360: b29b uxth r3, r3
8006362: b2da uxtb r2, r3
8006364: 68fb ldr r3, [r7, #12]
8006366: 681b ldr r3, [r3, #0]
8006368: 629a str r2, [r3, #40] @ 0x28
/* Prepare Memaddress buffer for LSB part */
hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
800636a: 893b ldrh r3, [r7, #8]
800636c: b2db uxtb r3, r3
800636e: 461a mov r2, r3
8006370: 68fb ldr r3, [r7, #12]
8006372: 651a str r2, [r3, #80] @ 0x50
}
if (hi2c->hdmarx != NULL)
8006374: 68fb ldr r3, [r7, #12]
8006376: 6bdb ldr r3, [r3, #60] @ 0x3c
8006378: 2b00 cmp r3, #0
800637a: d020 beq.n 80063be <HAL_I2C_Mem_Read_DMA+0x136>
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
800637c: 68fb ldr r3, [r7, #12]
800637e: 6bdb ldr r3, [r3, #60] @ 0x3c
8006380: 4a31 ldr r2, [pc, #196] @ (8006448 <HAL_I2C_Mem_Read_DMA+0x1c0>)
8006382: 62da str r2, [r3, #44] @ 0x2c
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
8006384: 68fb ldr r3, [r7, #12]
8006386: 6bdb ldr r3, [r3, #60] @ 0x3c
8006388: 4a30 ldr r2, [pc, #192] @ (800644c <HAL_I2C_Mem_Read_DMA+0x1c4>)
800638a: 635a str r2, [r3, #52] @ 0x34
/* Set the unused DMA callbacks to NULL */
hi2c->hdmarx->XferHalfCpltCallback = NULL;
800638c: 68fb ldr r3, [r7, #12]
800638e: 6bdb ldr r3, [r3, #60] @ 0x3c
8006390: 2200 movs r2, #0
8006392: 631a str r2, [r3, #48] @ 0x30
hi2c->hdmarx->XferAbortCallback = NULL;
8006394: 68fb ldr r3, [r7, #12]
8006396: 6bdb ldr r3, [r3, #60] @ 0x3c
8006398: 2200 movs r2, #0
800639a: 639a str r2, [r3, #56] @ 0x38
/* Enable the DMA channel */
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
800639c: 68fb ldr r3, [r7, #12]
800639e: 6bd8 ldr r0, [r3, #60] @ 0x3c
80063a0: 68fb ldr r3, [r7, #12]
80063a2: 681b ldr r3, [r3, #0]
80063a4: 3324 adds r3, #36 @ 0x24
80063a6: 4619 mov r1, r3
80063a8: 6a3a ldr r2, [r7, #32]
hi2c->XferSize);
80063aa: 68fb ldr r3, [r7, #12]
80063ac: 8d1b ldrh r3, [r3, #40] @ 0x28
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
80063ae: f7ff fa03 bl 80057b8 <HAL_DMA_Start_IT>
80063b2: 4603 mov r3, r0
80063b4: 75fb strb r3, [r7, #23]
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
80063b6: 7dfb ldrb r3, [r7, #23]
80063b8: 2b00 cmp r3, #0
80063ba: d127 bne.n 800640c <HAL_I2C_Mem_Read_DMA+0x184>
80063bc: e013 b.n 80063e6 <HAL_I2C_Mem_Read_DMA+0x15e>
hi2c->State = HAL_I2C_STATE_READY;
80063be: 68fb ldr r3, [r7, #12]
80063c0: 2220 movs r2, #32
80063c2: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
80063c6: 68fb ldr r3, [r7, #12]
80063c8: 2200 movs r2, #0
80063ca: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
80063ce: 68fb ldr r3, [r7, #12]
80063d0: 6c5b ldr r3, [r3, #68] @ 0x44
80063d2: f043 0280 orr.w r2, r3, #128 @ 0x80
80063d6: 68fb ldr r3, [r7, #12]
80063d8: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(hi2c);
80063da: 68fb ldr r3, [r7, #12]
80063dc: 2200 movs r2, #0
80063de: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
80063e2: 2301 movs r3, #1
80063e4: e027 b.n 8006436 <HAL_I2C_Mem_Read_DMA+0x1ae>
{
/* Send Slave Address and Memory Address */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
80063e6: 88fb ldrh r3, [r7, #6]
80063e8: b2da uxtb r2, r3
80063ea: 8979 ldrh r1, [r7, #10]
80063ec: 4b18 ldr r3, [pc, #96] @ (8006450 <HAL_I2C_Mem_Read_DMA+0x1c8>)
80063ee: 9300 str r3, [sp, #0]
80063f0: 2300 movs r3, #0
80063f2: 68f8 ldr r0, [r7, #12]
80063f4: f001 fab6 bl 8007964 <I2C_TransferConfig>
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80063f8: 68fb ldr r3, [r7, #12]
80063fa: 2200 movs r2, #0
80063fc: f883 2040 strb.w r2, [r3, #64] @ 0x40
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
8006400: 2101 movs r1, #1
8006402: 68f8 ldr r0, [r7, #12]
8006404: f001 fae0 bl 80079c8 <I2C_Enable_IRQ>
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
return HAL_OK;
8006408: 2300 movs r3, #0
800640a: e014 b.n 8006436 <HAL_I2C_Mem_Read_DMA+0x1ae>
hi2c->State = HAL_I2C_STATE_READY;
800640c: 68fb ldr r3, [r7, #12]
800640e: 2220 movs r2, #32
8006410: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8006414: 68fb ldr r3, [r7, #12]
8006416: 2200 movs r2, #0
8006418: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
800641c: 68fb ldr r3, [r7, #12]
800641e: 6c5b ldr r3, [r3, #68] @ 0x44
8006420: f043 0210 orr.w r2, r3, #16
8006424: 68fb ldr r3, [r7, #12]
8006426: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(hi2c);
8006428: 68fb ldr r3, [r7, #12]
800642a: 2200 movs r2, #0
800642c: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_ERROR;
8006430: 2301 movs r3, #1
8006432: e000 b.n 8006436 <HAL_I2C_Mem_Read_DMA+0x1ae>
}
else
{
return HAL_BUSY;
8006434: 2302 movs r3, #2
}
}
8006436: 4618 mov r0, r3
8006438: 3718 adds r7, #24
800643a: 46bd mov sp, r7
800643c: bd80 pop {r7, pc}
800643e: bf00 nop
8006440: ffff0000 .word 0xffff0000
8006444: 080069e5 .word 0x080069e5
8006448: 08007865 .word 0x08007865
800644c: 080078fb .word 0x080078fb
8006450: 80002000 .word 0x80002000
08006454 <HAL_I2C_EV_IRQHandler>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
{
8006454: b580 push {r7, lr}
8006456: b084 sub sp, #16
8006458: af00 add r7, sp, #0
800645a: 6078 str r0, [r7, #4]
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
800645c: 687b ldr r3, [r7, #4]
800645e: 681b ldr r3, [r3, #0]
8006460: 699b ldr r3, [r3, #24]
8006462: 60fb str r3, [r7, #12]
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
8006464: 687b ldr r3, [r7, #4]
8006466: 681b ldr r3, [r3, #0]
8006468: 681b ldr r3, [r3, #0]
800646a: 60bb str r3, [r7, #8]
/* I2C events treatment -------------------------------------*/
if (hi2c->XferISR != NULL)
800646c: 687b ldr r3, [r7, #4]
800646e: 6b5b ldr r3, [r3, #52] @ 0x34
8006470: 2b00 cmp r3, #0
8006472: d005 beq.n 8006480 <HAL_I2C_EV_IRQHandler+0x2c>
{
hi2c->XferISR(hi2c, itflags, itsources);
8006474: 687b ldr r3, [r7, #4]
8006476: 6b5b ldr r3, [r3, #52] @ 0x34
8006478: 68ba ldr r2, [r7, #8]
800647a: 68f9 ldr r1, [r7, #12]
800647c: 6878 ldr r0, [r7, #4]
800647e: 4798 blx r3
}
}
8006480: bf00 nop
8006482: 3710 adds r7, #16
8006484: 46bd mov sp, r7
8006486: bd80 pop {r7, pc}
08006488 <HAL_I2C_ER_IRQHandler>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
{
8006488: b580 push {r7, lr}
800648a: b086 sub sp, #24
800648c: af00 add r7, sp, #0
800648e: 6078 str r0, [r7, #4]
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
8006490: 687b ldr r3, [r7, #4]
8006492: 681b ldr r3, [r3, #0]
8006494: 699b ldr r3, [r3, #24]
8006496: 617b str r3, [r7, #20]
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
8006498: 687b ldr r3, [r7, #4]
800649a: 681b ldr r3, [r3, #0]
800649c: 681b ldr r3, [r3, #0]
800649e: 613b str r3, [r7, #16]
uint32_t tmperror;
/* I2C Bus error interrupt occurred ------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
80064a0: 697b ldr r3, [r7, #20]
80064a2: 0a1b lsrs r3, r3, #8
80064a4: f003 0301 and.w r3, r3, #1
80064a8: 2b00 cmp r3, #0
80064aa: d010 beq.n 80064ce <HAL_I2C_ER_IRQHandler+0x46>
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
80064ac: 693b ldr r3, [r7, #16]
80064ae: 09db lsrs r3, r3, #7
80064b0: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
80064b4: 2b00 cmp r3, #0
80064b6: d00a beq.n 80064ce <HAL_I2C_ER_IRQHandler+0x46>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
80064b8: 687b ldr r3, [r7, #4]
80064ba: 6c5b ldr r3, [r3, #68] @ 0x44
80064bc: f043 0201 orr.w r2, r3, #1
80064c0: 687b ldr r3, [r7, #4]
80064c2: 645a str r2, [r3, #68] @ 0x44
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
80064c4: 687b ldr r3, [r7, #4]
80064c6: 681b ldr r3, [r3, #0]
80064c8: f44f 7280 mov.w r2, #256 @ 0x100
80064cc: 61da str r2, [r3, #28]
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
80064ce: 697b ldr r3, [r7, #20]
80064d0: 0a9b lsrs r3, r3, #10
80064d2: f003 0301 and.w r3, r3, #1
80064d6: 2b00 cmp r3, #0
80064d8: d010 beq.n 80064fc <HAL_I2C_ER_IRQHandler+0x74>
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
80064da: 693b ldr r3, [r7, #16]
80064dc: 09db lsrs r3, r3, #7
80064de: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
80064e2: 2b00 cmp r3, #0
80064e4: d00a beq.n 80064fc <HAL_I2C_ER_IRQHandler+0x74>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
80064e6: 687b ldr r3, [r7, #4]
80064e8: 6c5b ldr r3, [r3, #68] @ 0x44
80064ea: f043 0208 orr.w r2, r3, #8
80064ee: 687b ldr r3, [r7, #4]
80064f0: 645a str r2, [r3, #68] @ 0x44
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
80064f2: 687b ldr r3, [r7, #4]
80064f4: 681b ldr r3, [r3, #0]
80064f6: f44f 6280 mov.w r2, #1024 @ 0x400
80064fa: 61da str r2, [r3, #28]
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
80064fc: 697b ldr r3, [r7, #20]
80064fe: 0a5b lsrs r3, r3, #9
8006500: f003 0301 and.w r3, r3, #1
8006504: 2b00 cmp r3, #0
8006506: d010 beq.n 800652a <HAL_I2C_ER_IRQHandler+0xa2>
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
8006508: 693b ldr r3, [r7, #16]
800650a: 09db lsrs r3, r3, #7
800650c: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
8006510: 2b00 cmp r3, #0
8006512: d00a beq.n 800652a <HAL_I2C_ER_IRQHandler+0xa2>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
8006514: 687b ldr r3, [r7, #4]
8006516: 6c5b ldr r3, [r3, #68] @ 0x44
8006518: f043 0202 orr.w r2, r3, #2
800651c: 687b ldr r3, [r7, #4]
800651e: 645a str r2, [r3, #68] @ 0x44
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
8006520: 687b ldr r3, [r7, #4]
8006522: 681b ldr r3, [r3, #0]
8006524: f44f 7200 mov.w r2, #512 @ 0x200
8006528: 61da str r2, [r3, #28]
}
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
800652a: 687b ldr r3, [r7, #4]
800652c: 6c5b ldr r3, [r3, #68] @ 0x44
800652e: 60fb str r3, [r7, #12]
/* Call the Error Callback in case of Error detected */
if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
8006530: 68fb ldr r3, [r7, #12]
8006532: f003 030b and.w r3, r3, #11
8006536: 2b00 cmp r3, #0
8006538: d003 beq.n 8006542 <HAL_I2C_ER_IRQHandler+0xba>
{
I2C_ITError(hi2c, tmperror);
800653a: 68f9 ldr r1, [r7, #12]
800653c: 6878 ldr r0, [r7, #4]
800653e: f001 f80b bl 8007558 <I2C_ITError>
}
}
8006542: bf00 nop
8006544: 3718 adds r7, #24
8006546: 46bd mov sp, r7
8006548: bd80 pop {r7, pc}
0800654a <HAL_I2C_MasterTxCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
800654a: b480 push {r7}
800654c: b083 sub sp, #12
800654e: af00 add r7, sp, #0
8006550: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
*/
}
8006552: bf00 nop
8006554: 370c adds r7, #12
8006556: 46bd mov sp, r7
8006558: f85d 7b04 ldr.w r7, [sp], #4
800655c: 4770 bx lr
0800655e <HAL_I2C_MasterRxCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
800655e: b480 push {r7}
8006560: b083 sub sp, #12
8006562: af00 add r7, sp, #0
8006564: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
*/
}
8006566: bf00 nop
8006568: 370c adds r7, #12
800656a: 46bd mov sp, r7
800656c: f85d 7b04 ldr.w r7, [sp], #4
8006570: 4770 bx lr
08006572 <HAL_I2C_SlaveTxCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
8006572: b480 push {r7}
8006574: b083 sub sp, #12
8006576: af00 add r7, sp, #0
8006578: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
*/
}
800657a: bf00 nop
800657c: 370c adds r7, #12
800657e: 46bd mov sp, r7
8006580: f85d 7b04 ldr.w r7, [sp], #4
8006584: 4770 bx lr
08006586 <HAL_I2C_SlaveRxCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
8006586: b480 push {r7}
8006588: b083 sub sp, #12
800658a: af00 add r7, sp, #0
800658c: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
*/
}
800658e: bf00 nop
8006590: 370c adds r7, #12
8006592: 46bd mov sp, r7
8006594: f85d 7b04 ldr.w r7, [sp], #4
8006598: 4770 bx lr
0800659a <HAL_I2C_AddrCallback>:
* @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
* @param AddrMatchCode Address Match Code
* @retval None
*/
__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
{
800659a: b480 push {r7}
800659c: b083 sub sp, #12
800659e: af00 add r7, sp, #0
80065a0: 6078 str r0, [r7, #4]
80065a2: 460b mov r3, r1
80065a4: 70fb strb r3, [r7, #3]
80065a6: 4613 mov r3, r2
80065a8: 803b strh r3, [r7, #0]
UNUSED(AddrMatchCode);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_AddrCallback() could be implemented in the user file
*/
}
80065aa: bf00 nop
80065ac: 370c adds r7, #12
80065ae: 46bd mov sp, r7
80065b0: f85d 7b04 ldr.w r7, [sp], #4
80065b4: 4770 bx lr
080065b6 <HAL_I2C_ListenCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
{
80065b6: b480 push {r7}
80065b8: b083 sub sp, #12
80065ba: af00 add r7, sp, #0
80065bc: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ListenCpltCallback() could be implemented in the user file
*/
}
80065be: bf00 nop
80065c0: 370c adds r7, #12
80065c2: 46bd mov sp, r7
80065c4: f85d 7b04 ldr.w r7, [sp], #4
80065c8: 4770 bx lr
080065ca <HAL_I2C_AbortCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
{
80065ca: b480 push {r7}
80065cc: b083 sub sp, #12
80065ce: af00 add r7, sp, #0
80065d0: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_AbortCpltCallback could be implemented in the user file
*/
}
80065d2: bf00 nop
80065d4: 370c adds r7, #12
80065d6: 46bd mov sp, r7
80065d8: f85d 7b04 ldr.w r7, [sp], #4
80065dc: 4770 bx lr
080065de <HAL_I2C_GetError>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval I2C Error Code
*/
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
{
80065de: b480 push {r7}
80065e0: b083 sub sp, #12
80065e2: af00 add r7, sp, #0
80065e4: 6078 str r0, [r7, #4]
return hi2c->ErrorCode;
80065e6: 687b ldr r3, [r7, #4]
80065e8: 6c5b ldr r3, [r3, #68] @ 0x44
}
80065ea: 4618 mov r0, r3
80065ec: 370c adds r7, #12
80065ee: 46bd mov sp, r7
80065f0: f85d 7b04 ldr.w r7, [sp], #4
80065f4: 4770 bx lr
080065f6 <I2C_Slave_ISR_IT>:
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
80065f6: b580 push {r7, lr}
80065f8: b086 sub sp, #24
80065fa: af00 add r7, sp, #0
80065fc: 60f8 str r0, [r7, #12]
80065fe: 60b9 str r1, [r7, #8]
8006600: 607a str r2, [r7, #4]
uint32_t tmpoptions = hi2c->XferOptions;
8006602: 68fb ldr r3, [r7, #12]
8006604: 6adb ldr r3, [r3, #44] @ 0x2c
8006606: 617b str r3, [r7, #20]
uint32_t tmpITFlags = ITFlags;
8006608: 68bb ldr r3, [r7, #8]
800660a: 613b str r3, [r7, #16]
/* Process locked */
__HAL_LOCK(hi2c);
800660c: 68fb ldr r3, [r7, #12]
800660e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8006612: 2b01 cmp r3, #1
8006614: d101 bne.n 800661a <I2C_Slave_ISR_IT+0x24>
8006616: 2302 movs r3, #2
8006618: e0ed b.n 80067f6 <I2C_Slave_ISR_IT+0x200>
800661a: 68fb ldr r3, [r7, #12]
800661c: 2201 movs r2, #1
800661e: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
8006622: 693b ldr r3, [r7, #16]
8006624: 095b lsrs r3, r3, #5
8006626: f003 0301 and.w r3, r3, #1
800662a: 2b00 cmp r3, #0
800662c: d00a beq.n 8006644 <I2C_Slave_ISR_IT+0x4e>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
800662e: 687b ldr r3, [r7, #4]
8006630: 095b lsrs r3, r3, #5
8006632: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
8006636: 2b00 cmp r3, #0
8006638: d004 beq.n 8006644 <I2C_Slave_ISR_IT+0x4e>
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
800663a: 6939 ldr r1, [r7, #16]
800663c: 68f8 ldr r0, [r7, #12]
800663e: f000 fdcb bl 80071d8 <I2C_ITSlaveCplt>
8006642: e0d3 b.n 80067ec <I2C_Slave_ISR_IT+0x1f6>
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
8006644: 693b ldr r3, [r7, #16]
8006646: 091b lsrs r3, r3, #4
8006648: f003 0301 and.w r3, r3, #1
800664c: 2b00 cmp r3, #0
800664e: d04d beq.n 80066ec <I2C_Slave_ISR_IT+0xf6>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
8006650: 687b ldr r3, [r7, #4]
8006652: 091b lsrs r3, r3, #4
8006654: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
8006658: 2b00 cmp r3, #0
800665a: d047 beq.n 80066ec <I2C_Slave_ISR_IT+0xf6>
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
800665c: 68fb ldr r3, [r7, #12]
800665e: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006660: b29b uxth r3, r3
8006662: 2b00 cmp r3, #0
8006664: d128 bne.n 80066b8 <I2C_Slave_ISR_IT+0xc2>
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
8006666: 68fb ldr r3, [r7, #12]
8006668: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800666c: b2db uxtb r3, r3
800666e: 2b28 cmp r3, #40 @ 0x28
8006670: d108 bne.n 8006684 <I2C_Slave_ISR_IT+0x8e>
8006672: 697b ldr r3, [r7, #20]
8006674: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8006678: d104 bne.n 8006684 <I2C_Slave_ISR_IT+0x8e>
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
800667a: 6939 ldr r1, [r7, #16]
800667c: 68f8 ldr r0, [r7, #12]
800667e: f000 ff15 bl 80074ac <I2C_ITListenCplt>
8006682: e032 b.n 80066ea <I2C_Slave_ISR_IT+0xf4>
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
8006684: 68fb ldr r3, [r7, #12]
8006686: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800668a: b2db uxtb r3, r3
800668c: 2b29 cmp r3, #41 @ 0x29
800668e: d10e bne.n 80066ae <I2C_Slave_ISR_IT+0xb8>
8006690: 697b ldr r3, [r7, #20]
8006692: f513 3f80 cmn.w r3, #65536 @ 0x10000
8006696: d00a beq.n 80066ae <I2C_Slave_ISR_IT+0xb8>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8006698: 68fb ldr r3, [r7, #12]
800669a: 681b ldr r3, [r3, #0]
800669c: 2210 movs r2, #16
800669e: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
80066a0: 68f8 ldr r0, [r7, #12]
80066a2: f001 f870 bl 8007786 <I2C_Flush_TXDR>
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
80066a6: 68f8 ldr r0, [r7, #12]
80066a8: f000 fc6e bl 8006f88 <I2C_ITSlaveSeqCplt>
80066ac: e01d b.n 80066ea <I2C_Slave_ISR_IT+0xf4>
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
80066ae: 68fb ldr r3, [r7, #12]
80066b0: 681b ldr r3, [r3, #0]
80066b2: 2210 movs r2, #16
80066b4: 61da str r2, [r3, #28]
if (hi2c->XferCount == 0U)
80066b6: e096 b.n 80067e6 <I2C_Slave_ISR_IT+0x1f0>
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
80066b8: 68fb ldr r3, [r7, #12]
80066ba: 681b ldr r3, [r3, #0]
80066bc: 2210 movs r2, #16
80066be: 61da str r2, [r3, #28]
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
80066c0: 68fb ldr r3, [r7, #12]
80066c2: 6c5b ldr r3, [r3, #68] @ 0x44
80066c4: f043 0204 orr.w r2, r3, #4
80066c8: 68fb ldr r3, [r7, #12]
80066ca: 645a str r2, [r3, #68] @ 0x44
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
80066cc: 697b ldr r3, [r7, #20]
80066ce: 2b00 cmp r3, #0
80066d0: d004 beq.n 80066dc <I2C_Slave_ISR_IT+0xe6>
80066d2: 697b ldr r3, [r7, #20]
80066d4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80066d8: f040 8085 bne.w 80067e6 <I2C_Slave_ISR_IT+0x1f0>
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
80066dc: 68fb ldr r3, [r7, #12]
80066de: 6c5b ldr r3, [r3, #68] @ 0x44
80066e0: 4619 mov r1, r3
80066e2: 68f8 ldr r0, [r7, #12]
80066e4: f000 ff38 bl 8007558 <I2C_ITError>
if (hi2c->XferCount == 0U)
80066e8: e07d b.n 80067e6 <I2C_Slave_ISR_IT+0x1f0>
80066ea: e07c b.n 80067e6 <I2C_Slave_ISR_IT+0x1f0>
}
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
80066ec: 693b ldr r3, [r7, #16]
80066ee: 089b lsrs r3, r3, #2
80066f0: f003 0301 and.w r3, r3, #1
80066f4: 2b00 cmp r3, #0
80066f6: d030 beq.n 800675a <I2C_Slave_ISR_IT+0x164>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
80066f8: 687b ldr r3, [r7, #4]
80066fa: 089b lsrs r3, r3, #2
80066fc: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
8006700: 2b00 cmp r3, #0
8006702: d02a beq.n 800675a <I2C_Slave_ISR_IT+0x164>
{
if (hi2c->XferCount > 0U)
8006704: 68fb ldr r3, [r7, #12]
8006706: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006708: b29b uxth r3, r3
800670a: 2b00 cmp r3, #0
800670c: d018 beq.n 8006740 <I2C_Slave_ISR_IT+0x14a>
{
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
800670e: 68fb ldr r3, [r7, #12]
8006710: 681b ldr r3, [r3, #0]
8006712: 6a5a ldr r2, [r3, #36] @ 0x24
8006714: 68fb ldr r3, [r7, #12]
8006716: 6a5b ldr r3, [r3, #36] @ 0x24
8006718: b2d2 uxtb r2, r2
800671a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800671c: 68fb ldr r3, [r7, #12]
800671e: 6a5b ldr r3, [r3, #36] @ 0x24
8006720: 1c5a adds r2, r3, #1
8006722: 68fb ldr r3, [r7, #12]
8006724: 625a str r2, [r3, #36] @ 0x24
hi2c->XferSize--;
8006726: 68fb ldr r3, [r7, #12]
8006728: 8d1b ldrh r3, [r3, #40] @ 0x28
800672a: 3b01 subs r3, #1
800672c: b29a uxth r2, r3
800672e: 68fb ldr r3, [r7, #12]
8006730: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8006732: 68fb ldr r3, [r7, #12]
8006734: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006736: b29b uxth r3, r3
8006738: 3b01 subs r3, #1
800673a: b29a uxth r2, r3
800673c: 68fb ldr r3, [r7, #12]
800673e: 855a strh r2, [r3, #42] @ 0x2a
}
if ((hi2c->XferCount == 0U) && \
8006740: 68fb ldr r3, [r7, #12]
8006742: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006744: b29b uxth r3, r3
8006746: 2b00 cmp r3, #0
8006748: d14f bne.n 80067ea <I2C_Slave_ISR_IT+0x1f4>
800674a: 697b ldr r3, [r7, #20]
800674c: f513 3f80 cmn.w r3, #65536 @ 0x10000
8006750: d04b beq.n 80067ea <I2C_Slave_ISR_IT+0x1f4>
(tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
8006752: 68f8 ldr r0, [r7, #12]
8006754: f000 fc18 bl 8006f88 <I2C_ITSlaveSeqCplt>
if ((hi2c->XferCount == 0U) && \
8006758: e047 b.n 80067ea <I2C_Slave_ISR_IT+0x1f4>
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
800675a: 693b ldr r3, [r7, #16]
800675c: 08db lsrs r3, r3, #3
800675e: f003 0301 and.w r3, r3, #1
8006762: 2b00 cmp r3, #0
8006764: d00a beq.n 800677c <I2C_Slave_ISR_IT+0x186>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
8006766: 687b ldr r3, [r7, #4]
8006768: 08db lsrs r3, r3, #3
800676a: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
800676e: 2b00 cmp r3, #0
8006770: d004 beq.n 800677c <I2C_Slave_ISR_IT+0x186>
{
I2C_ITAddrCplt(hi2c, tmpITFlags);
8006772: 6939 ldr r1, [r7, #16]
8006774: 68f8 ldr r0, [r7, #12]
8006776: f000 fb46 bl 8006e06 <I2C_ITAddrCplt>
800677a: e037 b.n 80067ec <I2C_Slave_ISR_IT+0x1f6>
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
800677c: 693b ldr r3, [r7, #16]
800677e: 085b lsrs r3, r3, #1
8006780: f003 0301 and.w r3, r3, #1
8006784: 2b00 cmp r3, #0
8006786: d031 beq.n 80067ec <I2C_Slave_ISR_IT+0x1f6>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
8006788: 687b ldr r3, [r7, #4]
800678a: 085b lsrs r3, r3, #1
800678c: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
8006790: 2b00 cmp r3, #0
8006792: d02b beq.n 80067ec <I2C_Slave_ISR_IT+0x1f6>
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
8006794: 68fb ldr r3, [r7, #12]
8006796: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006798: b29b uxth r3, r3
800679a: 2b00 cmp r3, #0
800679c: d018 beq.n 80067d0 <I2C_Slave_ISR_IT+0x1da>
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
800679e: 68fb ldr r3, [r7, #12]
80067a0: 6a5b ldr r3, [r3, #36] @ 0x24
80067a2: 781a ldrb r2, [r3, #0]
80067a4: 68fb ldr r3, [r7, #12]
80067a6: 681b ldr r3, [r3, #0]
80067a8: 629a str r2, [r3, #40] @ 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80067aa: 68fb ldr r3, [r7, #12]
80067ac: 6a5b ldr r3, [r3, #36] @ 0x24
80067ae: 1c5a adds r2, r3, #1
80067b0: 68fb ldr r3, [r7, #12]
80067b2: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount--;
80067b4: 68fb ldr r3, [r7, #12]
80067b6: 8d5b ldrh r3, [r3, #42] @ 0x2a
80067b8: b29b uxth r3, r3
80067ba: 3b01 subs r3, #1
80067bc: b29a uxth r2, r3
80067be: 68fb ldr r3, [r7, #12]
80067c0: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
80067c2: 68fb ldr r3, [r7, #12]
80067c4: 8d1b ldrh r3, [r3, #40] @ 0x28
80067c6: 3b01 subs r3, #1
80067c8: b29a uxth r2, r3
80067ca: 68fb ldr r3, [r7, #12]
80067cc: 851a strh r2, [r3, #40] @ 0x28
80067ce: e00d b.n 80067ec <I2C_Slave_ISR_IT+0x1f6>
}
else
{
if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
80067d0: 697b ldr r3, [r7, #20]
80067d2: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80067d6: d002 beq.n 80067de <I2C_Slave_ISR_IT+0x1e8>
80067d8: 697b ldr r3, [r7, #20]
80067da: 2b00 cmp r3, #0
80067dc: d106 bne.n 80067ec <I2C_Slave_ISR_IT+0x1f6>
{
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
80067de: 68f8 ldr r0, [r7, #12]
80067e0: f000 fbd2 bl 8006f88 <I2C_ITSlaveSeqCplt>
80067e4: e002 b.n 80067ec <I2C_Slave_ISR_IT+0x1f6>
if (hi2c->XferCount == 0U)
80067e6: bf00 nop
80067e8: e000 b.n 80067ec <I2C_Slave_ISR_IT+0x1f6>
if ((hi2c->XferCount == 0U) && \
80067ea: bf00 nop
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80067ec: 68fb ldr r3, [r7, #12]
80067ee: 2200 movs r2, #0
80067f0: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
80067f4: 2300 movs r3, #0
}
80067f6: 4618 mov r0, r3
80067f8: 3718 adds r7, #24
80067fa: 46bd mov sp, r7
80067fc: bd80 pop {r7, pc}
080067fe <I2C_Master_ISR_DMA>:
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
80067fe: b580 push {r7, lr}
8006800: b088 sub sp, #32
8006802: af02 add r7, sp, #8
8006804: 60f8 str r0, [r7, #12]
8006806: 60b9 str r1, [r7, #8]
8006808: 607a str r2, [r7, #4]
uint16_t devaddress;
uint32_t xfermode;
/* Process Locked */
__HAL_LOCK(hi2c);
800680a: 68fb ldr r3, [r7, #12]
800680c: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8006810: 2b01 cmp r3, #1
8006812: d101 bne.n 8006818 <I2C_Master_ISR_DMA+0x1a>
8006814: 2302 movs r3, #2
8006816: e0e1 b.n 80069dc <I2C_Master_ISR_DMA+0x1de>
8006818: 68fb ldr r3, [r7, #12]
800681a: 2201 movs r2, #1
800681c: f883 2040 strb.w r2, [r3, #64] @ 0x40
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8006820: 68bb ldr r3, [r7, #8]
8006822: 091b lsrs r3, r3, #4
8006824: f003 0301 and.w r3, r3, #1
8006828: 2b00 cmp r3, #0
800682a: d017 beq.n 800685c <I2C_Master_ISR_DMA+0x5e>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
800682c: 687b ldr r3, [r7, #4]
800682e: 091b lsrs r3, r3, #4
8006830: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8006834: 2b00 cmp r3, #0
8006836: d011 beq.n 800685c <I2C_Master_ISR_DMA+0x5e>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8006838: 68fb ldr r3, [r7, #12]
800683a: 681b ldr r3, [r3, #0]
800683c: 2210 movs r2, #16
800683e: 61da str r2, [r3, #28]
/* Set corresponding Error Code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8006840: 68fb ldr r3, [r7, #12]
8006842: 6c5b ldr r3, [r3, #68] @ 0x44
8006844: f043 0204 orr.w r2, r3, #4
8006848: 68fb ldr r3, [r7, #12]
800684a: 645a str r2, [r3, #68] @ 0x44
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
800684c: 2120 movs r1, #32
800684e: 68f8 ldr r0, [r7, #12]
8006850: f001 f8ba bl 80079c8 <I2C_Enable_IRQ>
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8006854: 68f8 ldr r0, [r7, #12]
8006856: f000 ff96 bl 8007786 <I2C_Flush_TXDR>
800685a: e0ba b.n 80069d2 <I2C_Master_ISR_DMA+0x1d4>
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
800685c: 68bb ldr r3, [r7, #8]
800685e: 09db lsrs r3, r3, #7
8006860: f003 0301 and.w r3, r3, #1
8006864: 2b00 cmp r3, #0
8006866: d072 beq.n 800694e <I2C_Master_ISR_DMA+0x150>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
8006868: 687b ldr r3, [r7, #4]
800686a: 099b lsrs r3, r3, #6
800686c: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
8006870: 2b00 cmp r3, #0
8006872: d06c beq.n 800694e <I2C_Master_ISR_DMA+0x150>
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
8006874: 68fb ldr r3, [r7, #12]
8006876: 681b ldr r3, [r3, #0]
8006878: 681a ldr r2, [r3, #0]
800687a: 68fb ldr r3, [r7, #12]
800687c: 681b ldr r3, [r3, #0]
800687e: f022 0240 bic.w r2, r2, #64 @ 0x40
8006882: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
8006884: 68fb ldr r3, [r7, #12]
8006886: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006888: b29b uxth r3, r3
800688a: 2b00 cmp r3, #0
800688c: d04e beq.n 800692c <I2C_Master_ISR_DMA+0x12e>
{
/* Recover Slave address */
devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
800688e: 68fb ldr r3, [r7, #12]
8006890: 681b ldr r3, [r3, #0]
8006892: 685b ldr r3, [r3, #4]
8006894: b29b uxth r3, r3
8006896: f3c3 0309 ubfx r3, r3, #0, #10
800689a: 827b strh r3, [r7, #18]
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
800689c: 68fb ldr r3, [r7, #12]
800689e: 8d5b ldrh r3, [r3, #42] @ 0x2a
80068a0: b29b uxth r3, r3
80068a2: 2bff cmp r3, #255 @ 0xff
80068a4: d906 bls.n 80068b4 <I2C_Master_ISR_DMA+0xb6>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80068a6: 68fb ldr r3, [r7, #12]
80068a8: 22ff movs r2, #255 @ 0xff
80068aa: 851a strh r2, [r3, #40] @ 0x28
xfermode = I2C_RELOAD_MODE;
80068ac: f04f 7380 mov.w r3, #16777216 @ 0x1000000
80068b0: 617b str r3, [r7, #20]
80068b2: e010 b.n 80068d6 <I2C_Master_ISR_DMA+0xd8>
}
else
{
hi2c->XferSize = hi2c->XferCount;
80068b4: 68fb ldr r3, [r7, #12]
80068b6: 8d5b ldrh r3, [r3, #42] @ 0x2a
80068b8: b29a uxth r2, r3
80068ba: 68fb ldr r3, [r7, #12]
80068bc: 851a strh r2, [r3, #40] @ 0x28
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
80068be: 68fb ldr r3, [r7, #12]
80068c0: 6adb ldr r3, [r3, #44] @ 0x2c
80068c2: f513 3f80 cmn.w r3, #65536 @ 0x10000
80068c6: d003 beq.n 80068d0 <I2C_Master_ISR_DMA+0xd2>
{
xfermode = hi2c->XferOptions;
80068c8: 68fb ldr r3, [r7, #12]
80068ca: 6adb ldr r3, [r3, #44] @ 0x2c
80068cc: 617b str r3, [r7, #20]
80068ce: e002 b.n 80068d6 <I2C_Master_ISR_DMA+0xd8>
}
else
{
xfermode = I2C_AUTOEND_MODE;
80068d0: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80068d4: 617b str r3, [r7, #20]
}
}
/* Set the new XferSize in Nbytes register */
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
80068d6: 68fb ldr r3, [r7, #12]
80068d8: 8d1b ldrh r3, [r3, #40] @ 0x28
80068da: b2da uxtb r2, r3
80068dc: 8a79 ldrh r1, [r7, #18]
80068de: 2300 movs r3, #0
80068e0: 9300 str r3, [sp, #0]
80068e2: 697b ldr r3, [r7, #20]
80068e4: 68f8 ldr r0, [r7, #12]
80068e6: f001 f83d bl 8007964 <I2C_TransferConfig>
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
80068ea: 68fb ldr r3, [r7, #12]
80068ec: 8d5b ldrh r3, [r3, #42] @ 0x2a
80068ee: b29a uxth r2, r3
80068f0: 68fb ldr r3, [r7, #12]
80068f2: 8d1b ldrh r3, [r3, #40] @ 0x28
80068f4: 1ad3 subs r3, r2, r3
80068f6: b29a uxth r2, r3
80068f8: 68fb ldr r3, [r7, #12]
80068fa: 855a strh r2, [r3, #42] @ 0x2a
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
80068fc: 68fb ldr r3, [r7, #12]
80068fe: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006902: b2db uxtb r3, r3
8006904: 2b22 cmp r3, #34 @ 0x22
8006906: d108 bne.n 800691a <I2C_Master_ISR_DMA+0x11c>
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
8006908: 68fb ldr r3, [r7, #12]
800690a: 681b ldr r3, [r3, #0]
800690c: 681a ldr r2, [r3, #0]
800690e: 68fb ldr r3, [r7, #12]
8006910: 681b ldr r3, [r3, #0]
8006912: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8006916: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
8006918: e05b b.n 80069d2 <I2C_Master_ISR_DMA+0x1d4>
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
800691a: 68fb ldr r3, [r7, #12]
800691c: 681b ldr r3, [r3, #0]
800691e: 681a ldr r2, [r3, #0]
8006920: 68fb ldr r3, [r7, #12]
8006922: 681b ldr r3, [r3, #0]
8006924: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8006928: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
800692a: e052 b.n 80069d2 <I2C_Master_ISR_DMA+0x1d4>
}
}
else
{
/* Call TxCpltCallback() if no stop mode is set */
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
800692c: 68fb ldr r3, [r7, #12]
800692e: 681b ldr r3, [r3, #0]
8006930: 685b ldr r3, [r3, #4]
8006932: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8006936: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
800693a: d003 beq.n 8006944 <I2C_Master_ISR_DMA+0x146>
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSeqCplt(hi2c);
800693c: 68f8 ldr r0, [r7, #12]
800693e: f000 fae6 bl 8006f0e <I2C_ITMasterSeqCplt>
if (hi2c->XferCount != 0U)
8006942: e046 b.n 80069d2 <I2C_Master_ISR_DMA+0x1d4>
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
8006944: 2140 movs r1, #64 @ 0x40
8006946: 68f8 ldr r0, [r7, #12]
8006948: f000 fe06 bl 8007558 <I2C_ITError>
if (hi2c->XferCount != 0U)
800694c: e041 b.n 80069d2 <I2C_Master_ISR_DMA+0x1d4>
}
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
800694e: 68bb ldr r3, [r7, #8]
8006950: 099b lsrs r3, r3, #6
8006952: f003 0301 and.w r3, r3, #1
8006956: 2b00 cmp r3, #0
8006958: d029 beq.n 80069ae <I2C_Master_ISR_DMA+0x1b0>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
800695a: 687b ldr r3, [r7, #4]
800695c: 099b lsrs r3, r3, #6
800695e: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
8006962: 2b00 cmp r3, #0
8006964: d023 beq.n 80069ae <I2C_Master_ISR_DMA+0x1b0>
{
if (hi2c->XferCount == 0U)
8006966: 68fb ldr r3, [r7, #12]
8006968: 8d5b ldrh r3, [r3, #42] @ 0x2a
800696a: b29b uxth r3, r3
800696c: 2b00 cmp r3, #0
800696e: d119 bne.n 80069a4 <I2C_Master_ISR_DMA+0x1a6>
{
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
8006970: 68fb ldr r3, [r7, #12]
8006972: 681b ldr r3, [r3, #0]
8006974: 685b ldr r3, [r3, #4]
8006976: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800697a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
800697e: d027 beq.n 80069d0 <I2C_Master_ISR_DMA+0x1d2>
{
/* Generate a stop condition in case of no transfer option */
if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
8006980: 68fb ldr r3, [r7, #12]
8006982: 6adb ldr r3, [r3, #44] @ 0x2c
8006984: f513 3f80 cmn.w r3, #65536 @ 0x10000
8006988: d108 bne.n 800699c <I2C_Master_ISR_DMA+0x19e>
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
800698a: 68fb ldr r3, [r7, #12]
800698c: 681b ldr r3, [r3, #0]
800698e: 685a ldr r2, [r3, #4]
8006990: 68fb ldr r3, [r7, #12]
8006992: 681b ldr r3, [r3, #0]
8006994: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8006998: 605a str r2, [r3, #4]
if (hi2c->XferCount == 0U)
800699a: e019 b.n 80069d0 <I2C_Master_ISR_DMA+0x1d2>
}
else
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSeqCplt(hi2c);
800699c: 68f8 ldr r0, [r7, #12]
800699e: f000 fab6 bl 8006f0e <I2C_ITMasterSeqCplt>
if (hi2c->XferCount == 0U)
80069a2: e015 b.n 80069d0 <I2C_Master_ISR_DMA+0x1d2>
}
else
{
/* Wrong size Status regarding TC flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
80069a4: 2140 movs r1, #64 @ 0x40
80069a6: 68f8 ldr r0, [r7, #12]
80069a8: f000 fdd6 bl 8007558 <I2C_ITError>
if (hi2c->XferCount == 0U)
80069ac: e010 b.n 80069d0 <I2C_Master_ISR_DMA+0x1d2>
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
80069ae: 68bb ldr r3, [r7, #8]
80069b0: 095b lsrs r3, r3, #5
80069b2: f003 0301 and.w r3, r3, #1
80069b6: 2b00 cmp r3, #0
80069b8: d00b beq.n 80069d2 <I2C_Master_ISR_DMA+0x1d4>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
80069ba: 687b ldr r3, [r7, #4]
80069bc: 095b lsrs r3, r3, #5
80069be: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
80069c2: 2b00 cmp r3, #0
80069c4: d005 beq.n 80069d2 <I2C_Master_ISR_DMA+0x1d4>
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
80069c6: 68b9 ldr r1, [r7, #8]
80069c8: 68f8 ldr r0, [r7, #12]
80069ca: f000 fb3b bl 8007044 <I2C_ITMasterCplt>
80069ce: e000 b.n 80069d2 <I2C_Master_ISR_DMA+0x1d4>
if (hi2c->XferCount == 0U)
80069d0: bf00 nop
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80069d2: 68fb ldr r3, [r7, #12]
80069d4: 2200 movs r2, #0
80069d6: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
80069da: 2300 movs r3, #0
}
80069dc: 4618 mov r0, r3
80069de: 3718 adds r7, #24
80069e0: 46bd mov sp, r7
80069e2: bd80 pop {r7, pc}
080069e4 <I2C_Mem_ISR_DMA>:
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
80069e4: b580 push {r7, lr}
80069e6: b088 sub sp, #32
80069e8: af02 add r7, sp, #8
80069ea: 60f8 str r0, [r7, #12]
80069ec: 60b9 str r1, [r7, #8]
80069ee: 607a str r2, [r7, #4]
uint32_t direction = I2C_GENERATE_START_WRITE;
80069f0: 4b92 ldr r3, [pc, #584] @ (8006c3c <I2C_Mem_ISR_DMA+0x258>)
80069f2: 617b str r3, [r7, #20]
/* Process Locked */
__HAL_LOCK(hi2c);
80069f4: 68fb ldr r3, [r7, #12]
80069f6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80069fa: 2b01 cmp r3, #1
80069fc: d101 bne.n 8006a02 <I2C_Mem_ISR_DMA+0x1e>
80069fe: 2302 movs r3, #2
8006a00: e118 b.n 8006c34 <I2C_Mem_ISR_DMA+0x250>
8006a02: 68fb ldr r3, [r7, #12]
8006a04: 2201 movs r2, #1
8006a06: f883 2040 strb.w r2, [r3, #64] @ 0x40
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8006a0a: 68bb ldr r3, [r7, #8]
8006a0c: 091b lsrs r3, r3, #4
8006a0e: f003 0301 and.w r3, r3, #1
8006a12: 2b00 cmp r3, #0
8006a14: d017 beq.n 8006a46 <I2C_Mem_ISR_DMA+0x62>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
8006a16: 687b ldr r3, [r7, #4]
8006a18: 091b lsrs r3, r3, #4
8006a1a: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8006a1e: 2b00 cmp r3, #0
8006a20: d011 beq.n 8006a46 <I2C_Mem_ISR_DMA+0x62>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8006a22: 68fb ldr r3, [r7, #12]
8006a24: 681b ldr r3, [r3, #0]
8006a26: 2210 movs r2, #16
8006a28: 61da str r2, [r3, #28]
/* Set corresponding Error Code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8006a2a: 68fb ldr r3, [r7, #12]
8006a2c: 6c5b ldr r3, [r3, #68] @ 0x44
8006a2e: f043 0204 orr.w r2, r3, #4
8006a32: 68fb ldr r3, [r7, #12]
8006a34: 645a str r2, [r3, #68] @ 0x44
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
8006a36: 2120 movs r1, #32
8006a38: 68f8 ldr r0, [r7, #12]
8006a3a: f000 ffc5 bl 80079c8 <I2C_Enable_IRQ>
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8006a3e: 68f8 ldr r0, [r7, #12]
8006a40: f000 fea1 bl 8007786 <I2C_Flush_TXDR>
8006a44: e0f1 b.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
8006a46: 68bb ldr r3, [r7, #8]
8006a48: 085b lsrs r3, r3, #1
8006a4a: f003 0301 and.w r3, r3, #1
8006a4e: 2b00 cmp r3, #0
8006a50: d00f beq.n 8006a72 <I2C_Mem_ISR_DMA+0x8e>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
8006a52: 687b ldr r3, [r7, #4]
8006a54: 085b lsrs r3, r3, #1
8006a56: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
8006a5a: 2b00 cmp r3, #0
8006a5c: d009 beq.n 8006a72 <I2C_Mem_ISR_DMA+0x8e>
{
/* Write LSB part of Memory Address */
hi2c->Instance->TXDR = hi2c->Memaddress;
8006a5e: 68fb ldr r3, [r7, #12]
8006a60: 681b ldr r3, [r3, #0]
8006a62: 68fa ldr r2, [r7, #12]
8006a64: 6d12 ldr r2, [r2, #80] @ 0x50
8006a66: 629a str r2, [r3, #40] @ 0x28
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
8006a68: 68fb ldr r3, [r7, #12]
8006a6a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8006a6e: 651a str r2, [r3, #80] @ 0x50
8006a70: e0db b.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
8006a72: 68bb ldr r3, [r7, #8]
8006a74: 09db lsrs r3, r3, #7
8006a76: f003 0301 and.w r3, r3, #1
8006a7a: 2b00 cmp r3, #0
8006a7c: d060 beq.n 8006b40 <I2C_Mem_ISR_DMA+0x15c>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
8006a7e: 687b ldr r3, [r7, #4]
8006a80: 099b lsrs r3, r3, #6
8006a82: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
8006a86: 2b00 cmp r3, #0
8006a88: d05a beq.n 8006b40 <I2C_Mem_ISR_DMA+0x15c>
{
/* Disable Interrupt related to address step */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
8006a8a: 2101 movs r1, #1
8006a8c: 68f8 ldr r0, [r7, #12]
8006a8e: f001 f81f bl 8007ad0 <I2C_Disable_IRQ>
/* Enable only Error interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
8006a92: 2110 movs r1, #16
8006a94: 68f8 ldr r0, [r7, #12]
8006a96: f000 ff97 bl 80079c8 <I2C_Enable_IRQ>
if (hi2c->XferCount != 0U)
8006a9a: 68fb ldr r3, [r7, #12]
8006a9c: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006a9e: b29b uxth r3, r3
8006aa0: 2b00 cmp r3, #0
8006aa2: d048 beq.n 8006b36 <I2C_Mem_ISR_DMA+0x152>
{
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8006aa4: 68fb ldr r3, [r7, #12]
8006aa6: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006aa8: b29b uxth r3, r3
8006aaa: 2bff cmp r3, #255 @ 0xff
8006aac: d910 bls.n 8006ad0 <I2C_Mem_ISR_DMA+0xec>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8006aae: 68fb ldr r3, [r7, #12]
8006ab0: 22ff movs r2, #255 @ 0xff
8006ab2: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
8006ab4: 68fb ldr r3, [r7, #12]
8006ab6: 6cdb ldr r3, [r3, #76] @ 0x4c
8006ab8: b299 uxth r1, r3
8006aba: 68fb ldr r3, [r7, #12]
8006abc: 8d1b ldrh r3, [r3, #40] @ 0x28
8006abe: b2da uxtb r2, r3
8006ac0: 2300 movs r3, #0
8006ac2: 9300 str r3, [sp, #0]
8006ac4: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8006ac8: 68f8 ldr r0, [r7, #12]
8006aca: f000 ff4b bl 8007964 <I2C_TransferConfig>
8006ace: e011 b.n 8006af4 <I2C_Mem_ISR_DMA+0x110>
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8006ad0: 68fb ldr r3, [r7, #12]
8006ad2: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006ad4: b29a uxth r2, r3
8006ad6: 68fb ldr r3, [r7, #12]
8006ad8: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
8006ada: 68fb ldr r3, [r7, #12]
8006adc: 6cdb ldr r3, [r3, #76] @ 0x4c
8006ade: b299 uxth r1, r3
8006ae0: 68fb ldr r3, [r7, #12]
8006ae2: 8d1b ldrh r3, [r3, #40] @ 0x28
8006ae4: b2da uxtb r2, r3
8006ae6: 2300 movs r3, #0
8006ae8: 9300 str r3, [sp, #0]
8006aea: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8006aee: 68f8 ldr r0, [r7, #12]
8006af0: f000 ff38 bl 8007964 <I2C_TransferConfig>
I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
8006af4: 68fb ldr r3, [r7, #12]
8006af6: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006af8: b29a uxth r2, r3
8006afa: 68fb ldr r3, [r7, #12]
8006afc: 8d1b ldrh r3, [r3, #40] @ 0x28
8006afe: 1ad3 subs r3, r2, r3
8006b00: b29a uxth r2, r3
8006b02: 68fb ldr r3, [r7, #12]
8006b04: 855a strh r2, [r3, #42] @ 0x2a
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8006b06: 68fb ldr r3, [r7, #12]
8006b08: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006b0c: b2db uxtb r3, r3
8006b0e: 2b22 cmp r3, #34 @ 0x22
8006b10: d108 bne.n 8006b24 <I2C_Mem_ISR_DMA+0x140>
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
8006b12: 68fb ldr r3, [r7, #12]
8006b14: 681b ldr r3, [r3, #0]
8006b16: 681a ldr r2, [r3, #0]
8006b18: 68fb ldr r3, [r7, #12]
8006b1a: 681b ldr r3, [r3, #0]
8006b1c: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8006b20: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
8006b22: e082 b.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
8006b24: 68fb ldr r3, [r7, #12]
8006b26: 681b ldr r3, [r3, #0]
8006b28: 681a ldr r2, [r3, #0]
8006b2a: 68fb ldr r3, [r7, #12]
8006b2c: 681b ldr r3, [r3, #0]
8006b2e: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8006b32: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
8006b34: e079 b.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
8006b36: 2140 movs r1, #64 @ 0x40
8006b38: 68f8 ldr r0, [r7, #12]
8006b3a: f000 fd0d bl 8007558 <I2C_ITError>
if (hi2c->XferCount != 0U)
8006b3e: e074 b.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
8006b40: 68bb ldr r3, [r7, #8]
8006b42: 099b lsrs r3, r3, #6
8006b44: f003 0301 and.w r3, r3, #1
8006b48: 2b00 cmp r3, #0
8006b4a: d05e beq.n 8006c0a <I2C_Mem_ISR_DMA+0x226>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
8006b4c: 687b ldr r3, [r7, #4]
8006b4e: 099b lsrs r3, r3, #6
8006b50: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
8006b54: 2b00 cmp r3, #0
8006b56: d058 beq.n 8006c0a <I2C_Mem_ISR_DMA+0x226>
{
/* Disable Interrupt related to address step */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
8006b58: 2101 movs r1, #1
8006b5a: 68f8 ldr r0, [r7, #12]
8006b5c: f000 ffb8 bl 8007ad0 <I2C_Disable_IRQ>
/* Enable only Error and NACK interrupt for data transfer */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
8006b60: 2110 movs r1, #16
8006b62: 68f8 ldr r0, [r7, #12]
8006b64: f000 ff30 bl 80079c8 <I2C_Enable_IRQ>
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8006b68: 68fb ldr r3, [r7, #12]
8006b6a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006b6e: b2db uxtb r3, r3
8006b70: 2b22 cmp r3, #34 @ 0x22
8006b72: d101 bne.n 8006b78 <I2C_Mem_ISR_DMA+0x194>
{
direction = I2C_GENERATE_START_READ;
8006b74: 4b32 ldr r3, [pc, #200] @ (8006c40 <I2C_Mem_ISR_DMA+0x25c>)
8006b76: 617b str r3, [r7, #20]
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8006b78: 68fb ldr r3, [r7, #12]
8006b7a: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006b7c: b29b uxth r3, r3
8006b7e: 2bff cmp r3, #255 @ 0xff
8006b80: d910 bls.n 8006ba4 <I2C_Mem_ISR_DMA+0x1c0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8006b82: 68fb ldr r3, [r7, #12]
8006b84: 22ff movs r2, #255 @ 0xff
8006b86: 851a strh r2, [r3, #40] @ 0x28
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
8006b88: 68fb ldr r3, [r7, #12]
8006b8a: 6cdb ldr r3, [r3, #76] @ 0x4c
8006b8c: b299 uxth r1, r3
8006b8e: 68fb ldr r3, [r7, #12]
8006b90: 8d1b ldrh r3, [r3, #40] @ 0x28
8006b92: b2da uxtb r2, r3
8006b94: 697b ldr r3, [r7, #20]
8006b96: 9300 str r3, [sp, #0]
8006b98: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8006b9c: 68f8 ldr r0, [r7, #12]
8006b9e: f000 fee1 bl 8007964 <I2C_TransferConfig>
8006ba2: e011 b.n 8006bc8 <I2C_Mem_ISR_DMA+0x1e4>
I2C_RELOAD_MODE, direction);
}
else
{
hi2c->XferSize = hi2c->XferCount;
8006ba4: 68fb ldr r3, [r7, #12]
8006ba6: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006ba8: b29a uxth r2, r3
8006baa: 68fb ldr r3, [r7, #12]
8006bac: 851a strh r2, [r3, #40] @ 0x28
/* Set NBYTES to write and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
8006bae: 68fb ldr r3, [r7, #12]
8006bb0: 6cdb ldr r3, [r3, #76] @ 0x4c
8006bb2: b299 uxth r1, r3
8006bb4: 68fb ldr r3, [r7, #12]
8006bb6: 8d1b ldrh r3, [r3, #40] @ 0x28
8006bb8: b2da uxtb r2, r3
8006bba: 697b ldr r3, [r7, #20]
8006bbc: 9300 str r3, [sp, #0]
8006bbe: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8006bc2: 68f8 ldr r0, [r7, #12]
8006bc4: f000 fece bl 8007964 <I2C_TransferConfig>
I2C_AUTOEND_MODE, direction);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
8006bc8: 68fb ldr r3, [r7, #12]
8006bca: 8d5b ldrh r3, [r3, #42] @ 0x2a
8006bcc: b29a uxth r2, r3
8006bce: 68fb ldr r3, [r7, #12]
8006bd0: 8d1b ldrh r3, [r3, #40] @ 0x28
8006bd2: 1ad3 subs r3, r2, r3
8006bd4: b29a uxth r2, r3
8006bd6: 68fb ldr r3, [r7, #12]
8006bd8: 855a strh r2, [r3, #42] @ 0x2a
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8006bda: 68fb ldr r3, [r7, #12]
8006bdc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006be0: b2db uxtb r3, r3
8006be2: 2b22 cmp r3, #34 @ 0x22
8006be4: d108 bne.n 8006bf8 <I2C_Mem_ISR_DMA+0x214>
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
8006be6: 68fb ldr r3, [r7, #12]
8006be8: 681b ldr r3, [r3, #0]
8006bea: 681a ldr r2, [r3, #0]
8006bec: 68fb ldr r3, [r7, #12]
8006bee: 681b ldr r3, [r3, #0]
8006bf0: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8006bf4: 601a str r2, [r3, #0]
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8006bf6: e018 b.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
8006bf8: 68fb ldr r3, [r7, #12]
8006bfa: 681b ldr r3, [r3, #0]
8006bfc: 681a ldr r2, [r3, #0]
8006bfe: 68fb ldr r3, [r7, #12]
8006c00: 681b ldr r3, [r3, #0]
8006c02: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8006c06: 601a str r2, [r3, #0]
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8006c08: e00f b.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
8006c0a: 68bb ldr r3, [r7, #8]
8006c0c: 095b lsrs r3, r3, #5
8006c0e: f003 0301 and.w r3, r3, #1
8006c12: 2b00 cmp r3, #0
8006c14: d009 beq.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
8006c16: 687b ldr r3, [r7, #4]
8006c18: 095b lsrs r3, r3, #5
8006c1a: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
8006c1e: 2b00 cmp r3, #0
8006c20: d003 beq.n 8006c2a <I2C_Mem_ISR_DMA+0x246>
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
8006c22: 68b9 ldr r1, [r7, #8]
8006c24: 68f8 ldr r0, [r7, #12]
8006c26: f000 fa0d bl 8007044 <I2C_ITMasterCplt>
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006c2a: 68fb ldr r3, [r7, #12]
8006c2c: 2200 movs r2, #0
8006c2e: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8006c32: 2300 movs r3, #0
}
8006c34: 4618 mov r0, r3
8006c36: 3718 adds r7, #24
8006c38: 46bd mov sp, r7
8006c3a: bd80 pop {r7, pc}
8006c3c: 80002000 .word 0x80002000
8006c40: 80002400 .word 0x80002400
08006c44 <I2C_Slave_ISR_DMA>:
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
8006c44: b580 push {r7, lr}
8006c46: b088 sub sp, #32
8006c48: af00 add r7, sp, #0
8006c4a: 60f8 str r0, [r7, #12]
8006c4c: 60b9 str r1, [r7, #8]
8006c4e: 607a str r2, [r7, #4]
uint32_t tmpoptions = hi2c->XferOptions;
8006c50: 68fb ldr r3, [r7, #12]
8006c52: 6adb ldr r3, [r3, #44] @ 0x2c
8006c54: 61bb str r3, [r7, #24]
uint32_t treatdmanack = 0U;
8006c56: 2300 movs r3, #0
8006c58: 61fb str r3, [r7, #28]
HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
8006c5a: 68fb ldr r3, [r7, #12]
8006c5c: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8006c60: 2b01 cmp r3, #1
8006c62: d101 bne.n 8006c68 <I2C_Slave_ISR_DMA+0x24>
8006c64: 2302 movs r3, #2
8006c66: e0ca b.n 8006dfe <I2C_Slave_ISR_DMA+0x1ba>
8006c68: 68fb ldr r3, [r7, #12]
8006c6a: 2201 movs r2, #1
8006c6c: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
8006c70: 68bb ldr r3, [r7, #8]
8006c72: 095b lsrs r3, r3, #5
8006c74: f003 0301 and.w r3, r3, #1
8006c78: 2b00 cmp r3, #0
8006c7a: d00a beq.n 8006c92 <I2C_Slave_ISR_DMA+0x4e>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
8006c7c: 687b ldr r3, [r7, #4]
8006c7e: 095b lsrs r3, r3, #5
8006c80: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
8006c84: 2b00 cmp r3, #0
8006c86: d004 beq.n 8006c92 <I2C_Slave_ISR_DMA+0x4e>
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
8006c88: 68b9 ldr r1, [r7, #8]
8006c8a: 68f8 ldr r0, [r7, #12]
8006c8c: f000 faa4 bl 80071d8 <I2C_ITSlaveCplt>
8006c90: e0b0 b.n 8006df4 <I2C_Slave_ISR_DMA+0x1b0>
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8006c92: 68bb ldr r3, [r7, #8]
8006c94: 091b lsrs r3, r3, #4
8006c96: f003 0301 and.w r3, r3, #1
8006c9a: 2b00 cmp r3, #0
8006c9c: f000 809a beq.w 8006dd4 <I2C_Slave_ISR_DMA+0x190>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
8006ca0: 687b ldr r3, [r7, #4]
8006ca2: 091b lsrs r3, r3, #4
8006ca4: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8006ca8: 2b00 cmp r3, #0
8006caa: f000 8093 beq.w 8006dd4 <I2C_Slave_ISR_DMA+0x190>
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
8006cae: 687b ldr r3, [r7, #4]
8006cb0: 0b9b lsrs r3, r3, #14
8006cb2: f003 0301 and.w r3, r3, #1
8006cb6: 2b00 cmp r3, #0
8006cb8: d105 bne.n 8006cc6 <I2C_Slave_ISR_DMA+0x82>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
8006cba: 687b ldr r3, [r7, #4]
8006cbc: 0bdb lsrs r3, r3, #15
8006cbe: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
8006cc2: 2b00 cmp r3, #0
8006cc4: d07f beq.n 8006dc6 <I2C_Slave_ISR_DMA+0x182>
{
/* Split check of hdmarx, for MISRA compliance */
if (hi2c->hdmarx != NULL)
8006cc6: 68fb ldr r3, [r7, #12]
8006cc8: 6bdb ldr r3, [r3, #60] @ 0x3c
8006cca: 2b00 cmp r3, #0
8006ccc: d00d beq.n 8006cea <I2C_Slave_ISR_DMA+0xa6>
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
8006cce: 687b ldr r3, [r7, #4]
8006cd0: 0bdb lsrs r3, r3, #15
8006cd2: f003 0301 and.w r3, r3, #1
8006cd6: 2b00 cmp r3, #0
8006cd8: d007 beq.n 8006cea <I2C_Slave_ISR_DMA+0xa6>
{
if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
8006cda: 68fb ldr r3, [r7, #12]
8006cdc: 6bdb ldr r3, [r3, #60] @ 0x3c
8006cde: 681b ldr r3, [r3, #0]
8006ce0: 685b ldr r3, [r3, #4]
8006ce2: 2b00 cmp r3, #0
8006ce4: d101 bne.n 8006cea <I2C_Slave_ISR_DMA+0xa6>
{
treatdmanack = 1U;
8006ce6: 2301 movs r3, #1
8006ce8: 61fb str r3, [r7, #28]
}
}
}
/* Split check of hdmatx, for MISRA compliance */
if (hi2c->hdmatx != NULL)
8006cea: 68fb ldr r3, [r7, #12]
8006cec: 6b9b ldr r3, [r3, #56] @ 0x38
8006cee: 2b00 cmp r3, #0
8006cf0: d00d beq.n 8006d0e <I2C_Slave_ISR_DMA+0xca>
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
8006cf2: 687b ldr r3, [r7, #4]
8006cf4: 0b9b lsrs r3, r3, #14
8006cf6: f003 0301 and.w r3, r3, #1
8006cfa: 2b00 cmp r3, #0
8006cfc: d007 beq.n 8006d0e <I2C_Slave_ISR_DMA+0xca>
{
if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
8006cfe: 68fb ldr r3, [r7, #12]
8006d00: 6b9b ldr r3, [r3, #56] @ 0x38
8006d02: 681b ldr r3, [r3, #0]
8006d04: 685b ldr r3, [r3, #4]
8006d06: 2b00 cmp r3, #0
8006d08: d101 bne.n 8006d0e <I2C_Slave_ISR_DMA+0xca>
{
treatdmanack = 1U;
8006d0a: 2301 movs r3, #1
8006d0c: 61fb str r3, [r7, #28]
}
}
}
if (treatdmanack == 1U)
8006d0e: 69fb ldr r3, [r7, #28]
8006d10: 2b01 cmp r3, #1
8006d12: d128 bne.n 8006d66 <I2C_Slave_ISR_DMA+0x122>
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
8006d14: 68fb ldr r3, [r7, #12]
8006d16: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006d1a: b2db uxtb r3, r3
8006d1c: 2b28 cmp r3, #40 @ 0x28
8006d1e: d108 bne.n 8006d32 <I2C_Slave_ISR_DMA+0xee>
8006d20: 69bb ldr r3, [r7, #24]
8006d22: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8006d26: d104 bne.n 8006d32 <I2C_Slave_ISR_DMA+0xee>
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
8006d28: 68b9 ldr r1, [r7, #8]
8006d2a: 68f8 ldr r0, [r7, #12]
8006d2c: f000 fbbe bl 80074ac <I2C_ITListenCplt>
8006d30: e048 b.n 8006dc4 <I2C_Slave_ISR_DMA+0x180>
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
8006d32: 68fb ldr r3, [r7, #12]
8006d34: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006d38: b2db uxtb r3, r3
8006d3a: 2b29 cmp r3, #41 @ 0x29
8006d3c: d10e bne.n 8006d5c <I2C_Slave_ISR_DMA+0x118>
8006d3e: 69bb ldr r3, [r7, #24]
8006d40: f513 3f80 cmn.w r3, #65536 @ 0x10000
8006d44: d00a beq.n 8006d5c <I2C_Slave_ISR_DMA+0x118>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8006d46: 68fb ldr r3, [r7, #12]
8006d48: 681b ldr r3, [r3, #0]
8006d4a: 2210 movs r2, #16
8006d4c: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8006d4e: 68f8 ldr r0, [r7, #12]
8006d50: f000 fd19 bl 8007786 <I2C_Flush_TXDR>
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
8006d54: 68f8 ldr r0, [r7, #12]
8006d56: f000 f917 bl 8006f88 <I2C_ITSlaveSeqCplt>
8006d5a: e033 b.n 8006dc4 <I2C_Slave_ISR_DMA+0x180>
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8006d5c: 68fb ldr r3, [r7, #12]
8006d5e: 681b ldr r3, [r3, #0]
8006d60: 2210 movs r2, #16
8006d62: 61da str r2, [r3, #28]
if (treatdmanack == 1U)
8006d64: e034 b.n 8006dd0 <I2C_Slave_ISR_DMA+0x18c>
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8006d66: 68fb ldr r3, [r7, #12]
8006d68: 681b ldr r3, [r3, #0]
8006d6a: 2210 movs r2, #16
8006d6c: 61da str r2, [r3, #28]
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8006d6e: 68fb ldr r3, [r7, #12]
8006d70: 6c5b ldr r3, [r3, #68] @ 0x44
8006d72: f043 0204 orr.w r2, r3, #4
8006d76: 68fb ldr r3, [r7, #12]
8006d78: 645a str r2, [r3, #68] @ 0x44
/* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
tmpstate = hi2c->State;
8006d7a: 68fb ldr r3, [r7, #12]
8006d7c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006d80: 75fb strb r3, [r7, #23]
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
8006d82: 69bb ldr r3, [r7, #24]
8006d84: 2b00 cmp r3, #0
8006d86: d003 beq.n 8006d90 <I2C_Slave_ISR_DMA+0x14c>
8006d88: 69bb ldr r3, [r7, #24]
8006d8a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8006d8e: d11f bne.n 8006dd0 <I2C_Slave_ISR_DMA+0x18c>
{
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
8006d90: 7dfb ldrb r3, [r7, #23]
8006d92: 2b21 cmp r3, #33 @ 0x21
8006d94: d002 beq.n 8006d9c <I2C_Slave_ISR_DMA+0x158>
8006d96: 7dfb ldrb r3, [r7, #23]
8006d98: 2b29 cmp r3, #41 @ 0x29
8006d9a: d103 bne.n 8006da4 <I2C_Slave_ISR_DMA+0x160>
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
8006d9c: 68fb ldr r3, [r7, #12]
8006d9e: 2221 movs r2, #33 @ 0x21
8006da0: 631a str r2, [r3, #48] @ 0x30
8006da2: e008 b.n 8006db6 <I2C_Slave_ISR_DMA+0x172>
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
8006da4: 7dfb ldrb r3, [r7, #23]
8006da6: 2b22 cmp r3, #34 @ 0x22
8006da8: d002 beq.n 8006db0 <I2C_Slave_ISR_DMA+0x16c>
8006daa: 7dfb ldrb r3, [r7, #23]
8006dac: 2b2a cmp r3, #42 @ 0x2a
8006dae: d102 bne.n 8006db6 <I2C_Slave_ISR_DMA+0x172>
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
8006db0: 68fb ldr r3, [r7, #12]
8006db2: 2222 movs r2, #34 @ 0x22
8006db4: 631a str r2, [r3, #48] @ 0x30
{
/* Do nothing */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
8006db6: 68fb ldr r3, [r7, #12]
8006db8: 6c5b ldr r3, [r3, #68] @ 0x44
8006dba: 4619 mov r1, r3
8006dbc: 68f8 ldr r0, [r7, #12]
8006dbe: f000 fbcb bl 8007558 <I2C_ITError>
if (treatdmanack == 1U)
8006dc2: e005 b.n 8006dd0 <I2C_Slave_ISR_DMA+0x18c>
8006dc4: e004 b.n 8006dd0 <I2C_Slave_ISR_DMA+0x18c>
}
}
else
{
/* Only Clear NACK Flag, no DMA treatment is pending */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8006dc6: 68fb ldr r3, [r7, #12]
8006dc8: 681b ldr r3, [r3, #0]
8006dca: 2210 movs r2, #16
8006dcc: 61da str r2, [r3, #28]
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
8006dce: e011 b.n 8006df4 <I2C_Slave_ISR_DMA+0x1b0>
if (treatdmanack == 1U)
8006dd0: bf00 nop
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
8006dd2: e00f b.n 8006df4 <I2C_Slave_ISR_DMA+0x1b0>
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
8006dd4: 68bb ldr r3, [r7, #8]
8006dd6: 08db lsrs r3, r3, #3
8006dd8: f003 0301 and.w r3, r3, #1
8006ddc: 2b00 cmp r3, #0
8006dde: d009 beq.n 8006df4 <I2C_Slave_ISR_DMA+0x1b0>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
8006de0: 687b ldr r3, [r7, #4]
8006de2: 08db lsrs r3, r3, #3
8006de4: f003 0301 and.w r3, r3, #1
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
8006de8: 2b00 cmp r3, #0
8006dea: d003 beq.n 8006df4 <I2C_Slave_ISR_DMA+0x1b0>
{
I2C_ITAddrCplt(hi2c, ITFlags);
8006dec: 68b9 ldr r1, [r7, #8]
8006dee: 68f8 ldr r0, [r7, #12]
8006df0: f000 f809 bl 8006e06 <I2C_ITAddrCplt>
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006df4: 68fb ldr r3, [r7, #12]
8006df6: 2200 movs r2, #0
8006df8: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8006dfc: 2300 movs r3, #0
}
8006dfe: 4618 mov r0, r3
8006e00: 3720 adds r7, #32
8006e02: 46bd mov sp, r7
8006e04: bd80 pop {r7, pc}
08006e06 <I2C_ITAddrCplt>:
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
8006e06: b580 push {r7, lr}
8006e08: b084 sub sp, #16
8006e0a: af00 add r7, sp, #0
8006e0c: 6078 str r0, [r7, #4]
8006e0e: 6039 str r1, [r7, #0]
/* Prevent unused argument(s) compilation warning */
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
8006e10: 687b ldr r3, [r7, #4]
8006e12: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006e16: b2db uxtb r3, r3
8006e18: f003 0328 and.w r3, r3, #40 @ 0x28
8006e1c: 2b28 cmp r3, #40 @ 0x28
8006e1e: d16a bne.n 8006ef6 <I2C_ITAddrCplt+0xf0>
{
transferdirection = I2C_GET_DIR(hi2c);
8006e20: 687b ldr r3, [r7, #4]
8006e22: 681b ldr r3, [r3, #0]
8006e24: 699b ldr r3, [r3, #24]
8006e26: 0c1b lsrs r3, r3, #16
8006e28: b2db uxtb r3, r3
8006e2a: f003 0301 and.w r3, r3, #1
8006e2e: 73fb strb r3, [r7, #15]
slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
8006e30: 687b ldr r3, [r7, #4]
8006e32: 681b ldr r3, [r3, #0]
8006e34: 699b ldr r3, [r3, #24]
8006e36: 0c1b lsrs r3, r3, #16
8006e38: b29b uxth r3, r3
8006e3a: f003 03fe and.w r3, r3, #254 @ 0xfe
8006e3e: 81bb strh r3, [r7, #12]
ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
8006e40: 687b ldr r3, [r7, #4]
8006e42: 681b ldr r3, [r3, #0]
8006e44: 689b ldr r3, [r3, #8]
8006e46: b29b uxth r3, r3
8006e48: f3c3 0309 ubfx r3, r3, #0, #10
8006e4c: 817b strh r3, [r7, #10]
ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
8006e4e: 687b ldr r3, [r7, #4]
8006e50: 681b ldr r3, [r3, #0]
8006e52: 68db ldr r3, [r3, #12]
8006e54: b29b uxth r3, r3
8006e56: f003 03fe and.w r3, r3, #254 @ 0xfe
8006e5a: 813b strh r3, [r7, #8]
/* If 10bits addressing mode is selected */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
8006e5c: 687b ldr r3, [r7, #4]
8006e5e: 68db ldr r3, [r3, #12]
8006e60: 2b02 cmp r3, #2
8006e62: d138 bne.n 8006ed6 <I2C_ITAddrCplt+0xd0>
{
if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
8006e64: 897b ldrh r3, [r7, #10]
8006e66: 09db lsrs r3, r3, #7
8006e68: b29a uxth r2, r3
8006e6a: 89bb ldrh r3, [r7, #12]
8006e6c: 4053 eors r3, r2
8006e6e: b29b uxth r3, r3
8006e70: f003 0306 and.w r3, r3, #6
8006e74: 2b00 cmp r3, #0
8006e76: d11c bne.n 8006eb2 <I2C_ITAddrCplt+0xac>
{
slaveaddrcode = ownadd1code;
8006e78: 897b ldrh r3, [r7, #10]
8006e7a: 81bb strh r3, [r7, #12]
hi2c->AddrEventCount++;
8006e7c: 687b ldr r3, [r7, #4]
8006e7e: 6c9b ldr r3, [r3, #72] @ 0x48
8006e80: 1c5a adds r2, r3, #1
8006e82: 687b ldr r3, [r7, #4]
8006e84: 649a str r2, [r3, #72] @ 0x48
if (hi2c->AddrEventCount == 2U)
8006e86: 687b ldr r3, [r7, #4]
8006e88: 6c9b ldr r3, [r3, #72] @ 0x48
8006e8a: 2b02 cmp r3, #2
8006e8c: d13b bne.n 8006f06 <I2C_ITAddrCplt+0x100>
{
/* Reset Address Event counter */
hi2c->AddrEventCount = 0U;
8006e8e: 687b ldr r3, [r7, #4]
8006e90: 2200 movs r2, #0
8006e92: 649a str r2, [r3, #72] @ 0x48
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
8006e94: 687b ldr r3, [r7, #4]
8006e96: 681b ldr r3, [r3, #0]
8006e98: 2208 movs r2, #8
8006e9a: 61da str r2, [r3, #28]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006e9c: 687b ldr r3, [r7, #4]
8006e9e: 2200 movs r2, #0
8006ea0: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Call Slave Addr callback */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
8006ea4: 89ba ldrh r2, [r7, #12]
8006ea6: 7bfb ldrb r3, [r7, #15]
8006ea8: 4619 mov r1, r3
8006eaa: 6878 ldr r0, [r7, #4]
8006eac: f7ff fb75 bl 800659a <HAL_I2C_AddrCallback>
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
}
}
8006eb0: e029 b.n 8006f06 <I2C_ITAddrCplt+0x100>
slaveaddrcode = ownadd2code;
8006eb2: 893b ldrh r3, [r7, #8]
8006eb4: 81bb strh r3, [r7, #12]
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
8006eb6: f44f 4100 mov.w r1, #32768 @ 0x8000
8006eba: 6878 ldr r0, [r7, #4]
8006ebc: f000 fe08 bl 8007ad0 <I2C_Disable_IRQ>
__HAL_UNLOCK(hi2c);
8006ec0: 687b ldr r3, [r7, #4]
8006ec2: 2200 movs r2, #0
8006ec4: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
8006ec8: 89ba ldrh r2, [r7, #12]
8006eca: 7bfb ldrb r3, [r7, #15]
8006ecc: 4619 mov r1, r3
8006ece: 6878 ldr r0, [r7, #4]
8006ed0: f7ff fb63 bl 800659a <HAL_I2C_AddrCallback>
}
8006ed4: e017 b.n 8006f06 <I2C_ITAddrCplt+0x100>
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
8006ed6: f44f 4100 mov.w r1, #32768 @ 0x8000
8006eda: 6878 ldr r0, [r7, #4]
8006edc: f000 fdf8 bl 8007ad0 <I2C_Disable_IRQ>
__HAL_UNLOCK(hi2c);
8006ee0: 687b ldr r3, [r7, #4]
8006ee2: 2200 movs r2, #0
8006ee4: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
8006ee8: 89ba ldrh r2, [r7, #12]
8006eea: 7bfb ldrb r3, [r7, #15]
8006eec: 4619 mov r1, r3
8006eee: 6878 ldr r0, [r7, #4]
8006ef0: f7ff fb53 bl 800659a <HAL_I2C_AddrCallback>
}
8006ef4: e007 b.n 8006f06 <I2C_ITAddrCplt+0x100>
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
8006ef6: 687b ldr r3, [r7, #4]
8006ef8: 681b ldr r3, [r3, #0]
8006efa: 2208 movs r2, #8
8006efc: 61da str r2, [r3, #28]
__HAL_UNLOCK(hi2c);
8006efe: 687b ldr r3, [r7, #4]
8006f00: 2200 movs r2, #0
8006f02: f883 2040 strb.w r2, [r3, #64] @ 0x40
}
8006f06: bf00 nop
8006f08: 3710 adds r7, #16
8006f0a: 46bd mov sp, r7
8006f0c: bd80 pop {r7, pc}
08006f0e <I2C_ITMasterSeqCplt>:
* @brief I2C Master sequential complete process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
{
8006f0e: b580 push {r7, lr}
8006f10: b082 sub sp, #8
8006f12: af00 add r7, sp, #0
8006f14: 6078 str r0, [r7, #4]
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
8006f16: 687b ldr r3, [r7, #4]
8006f18: 2200 movs r2, #0
8006f1a: f883 2042 strb.w r2, [r3, #66] @ 0x42
/* No Generate Stop, to permit restart mode */
/* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
8006f1e: 687b ldr r3, [r7, #4]
8006f20: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006f24: b2db uxtb r3, r3
8006f26: 2b21 cmp r3, #33 @ 0x21
8006f28: d115 bne.n 8006f56 <I2C_ITMasterSeqCplt+0x48>
{
hi2c->State = HAL_I2C_STATE_READY;
8006f2a: 687b ldr r3, [r7, #4]
8006f2c: 2220 movs r2, #32
8006f2e: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
8006f32: 687b ldr r3, [r7, #4]
8006f34: 2211 movs r2, #17
8006f36: 631a str r2, [r3, #48] @ 0x30
hi2c->XferISR = NULL;
8006f38: 687b ldr r3, [r7, #4]
8006f3a: 2200 movs r2, #0
8006f3c: 635a str r2, [r3, #52] @ 0x34
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
8006f3e: 2101 movs r1, #1
8006f40: 6878 ldr r0, [r7, #4]
8006f42: f000 fdc5 bl 8007ad0 <I2C_Disable_IRQ>
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006f46: 687b ldr r3, [r7, #4]
8006f48: 2200 movs r2, #0
8006f4a: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterTxCpltCallback(hi2c);
#else
HAL_I2C_MasterTxCpltCallback(hi2c);
8006f4e: 6878 ldr r0, [r7, #4]
8006f50: f7ff fafb bl 800654a <HAL_I2C_MasterTxCpltCallback>
hi2c->MasterRxCpltCallback(hi2c);
#else
HAL_I2C_MasterRxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
8006f54: e014 b.n 8006f80 <I2C_ITMasterSeqCplt+0x72>
hi2c->State = HAL_I2C_STATE_READY;
8006f56: 687b ldr r3, [r7, #4]
8006f58: 2220 movs r2, #32
8006f5a: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
8006f5e: 687b ldr r3, [r7, #4]
8006f60: 2212 movs r2, #18
8006f62: 631a str r2, [r3, #48] @ 0x30
hi2c->XferISR = NULL;
8006f64: 687b ldr r3, [r7, #4]
8006f66: 2200 movs r2, #0
8006f68: 635a str r2, [r3, #52] @ 0x34
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
8006f6a: 2102 movs r1, #2
8006f6c: 6878 ldr r0, [r7, #4]
8006f6e: f000 fdaf bl 8007ad0 <I2C_Disable_IRQ>
__HAL_UNLOCK(hi2c);
8006f72: 687b ldr r3, [r7, #4]
8006f74: 2200 movs r2, #0
8006f76: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_MasterRxCpltCallback(hi2c);
8006f7a: 6878 ldr r0, [r7, #4]
8006f7c: f7ff faef bl 800655e <HAL_I2C_MasterRxCpltCallback>
}
8006f80: bf00 nop
8006f82: 3708 adds r7, #8
8006f84: 46bd mov sp, r7
8006f86: bd80 pop {r7, pc}
08006f88 <I2C_ITSlaveSeqCplt>:
* @brief I2C Slave sequential complete process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
8006f88: b580 push {r7, lr}
8006f8a: b084 sub sp, #16
8006f8c: af00 add r7, sp, #0
8006f8e: 6078 str r0, [r7, #4]
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
8006f90: 687b ldr r3, [r7, #4]
8006f92: 681b ldr r3, [r3, #0]
8006f94: 681b ldr r3, [r3, #0]
8006f96: 60fb str r3, [r7, #12]
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
8006f98: 687b ldr r3, [r7, #4]
8006f9a: 2200 movs r2, #0
8006f9c: f883 2042 strb.w r2, [r3, #66] @ 0x42
#if defined(HAL_DMA_MODULE_ENABLED)
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
8006fa0: 68fb ldr r3, [r7, #12]
8006fa2: 0b9b lsrs r3, r3, #14
8006fa4: f003 0301 and.w r3, r3, #1
8006fa8: 2b00 cmp r3, #0
8006faa: d008 beq.n 8006fbe <I2C_ITSlaveSeqCplt+0x36>
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
8006fac: 687b ldr r3, [r7, #4]
8006fae: 681b ldr r3, [r3, #0]
8006fb0: 681a ldr r2, [r3, #0]
8006fb2: 687b ldr r3, [r7, #4]
8006fb4: 681b ldr r3, [r3, #0]
8006fb6: f422 4280 bic.w r2, r2, #16384 @ 0x4000
8006fba: 601a str r2, [r3, #0]
8006fbc: e00d b.n 8006fda <I2C_ITSlaveSeqCplt+0x52>
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
8006fbe: 68fb ldr r3, [r7, #12]
8006fc0: 0bdb lsrs r3, r3, #15
8006fc2: f003 0301 and.w r3, r3, #1
8006fc6: 2b00 cmp r3, #0
8006fc8: d007 beq.n 8006fda <I2C_ITSlaveSeqCplt+0x52>
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
8006fca: 687b ldr r3, [r7, #4]
8006fcc: 681b ldr r3, [r3, #0]
8006fce: 681a ldr r2, [r3, #0]
8006fd0: 687b ldr r3, [r7, #4]
8006fd2: 681b ldr r3, [r3, #0]
8006fd4: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8006fd8: 601a str r2, [r3, #0]
{
/* Do nothing */
}
#endif /* HAL_DMA_MODULE_ENABLED */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
8006fda: 687b ldr r3, [r7, #4]
8006fdc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8006fe0: b2db uxtb r3, r3
8006fe2: 2b29 cmp r3, #41 @ 0x29
8006fe4: d112 bne.n 800700c <I2C_ITSlaveSeqCplt+0x84>
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
hi2c->State = HAL_I2C_STATE_LISTEN;
8006fe6: 687b ldr r3, [r7, #4]
8006fe8: 2228 movs r2, #40 @ 0x28
8006fea: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
8006fee: 687b ldr r3, [r7, #4]
8006ff0: 2221 movs r2, #33 @ 0x21
8006ff2: 631a str r2, [r3, #48] @ 0x30
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
8006ff4: 2101 movs r1, #1
8006ff6: 6878 ldr r0, [r7, #4]
8006ff8: f000 fd6a bl 8007ad0 <I2C_Disable_IRQ>
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006ffc: 687b ldr r3, [r7, #4]
8006ffe: 2200 movs r2, #0
8007000: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->SlaveTxCpltCallback(hi2c);
#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
8007004: 6878 ldr r0, [r7, #4]
8007006: f7ff fab4 bl 8006572 <HAL_I2C_SlaveTxCpltCallback>
}
else
{
/* Nothing to do */
}
}
800700a: e017 b.n 800703c <I2C_ITSlaveSeqCplt+0xb4>
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
800700c: 687b ldr r3, [r7, #4]
800700e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007012: b2db uxtb r3, r3
8007014: 2b2a cmp r3, #42 @ 0x2a
8007016: d111 bne.n 800703c <I2C_ITSlaveSeqCplt+0xb4>
hi2c->State = HAL_I2C_STATE_LISTEN;
8007018: 687b ldr r3, [r7, #4]
800701a: 2228 movs r2, #40 @ 0x28
800701c: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
8007020: 687b ldr r3, [r7, #4]
8007022: 2222 movs r2, #34 @ 0x22
8007024: 631a str r2, [r3, #48] @ 0x30
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
8007026: 2102 movs r1, #2
8007028: 6878 ldr r0, [r7, #4]
800702a: f000 fd51 bl 8007ad0 <I2C_Disable_IRQ>
__HAL_UNLOCK(hi2c);
800702e: 687b ldr r3, [r7, #4]
8007030: 2200 movs r2, #0
8007032: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_SlaveRxCpltCallback(hi2c);
8007036: 6878 ldr r0, [r7, #4]
8007038: f7ff faa5 bl 8006586 <HAL_I2C_SlaveRxCpltCallback>
}
800703c: bf00 nop
800703e: 3710 adds r7, #16
8007040: 46bd mov sp, r7
8007042: bd80 pop {r7, pc}
08007044 <I2C_ITMasterCplt>:
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
8007044: b580 push {r7, lr}
8007046: b086 sub sp, #24
8007048: af00 add r7, sp, #0
800704a: 6078 str r0, [r7, #4]
800704c: 6039 str r1, [r7, #0]
uint32_t tmperror;
uint32_t tmpITFlags = ITFlags;
800704e: 683b ldr r3, [r7, #0]
8007050: 617b str r3, [r7, #20]
__IO uint32_t tmpreg;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8007052: 687b ldr r3, [r7, #4]
8007054: 681b ldr r3, [r3, #0]
8007056: 2220 movs r2, #32
8007058: 61da str r2, [r3, #28]
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
800705a: 687b ldr r3, [r7, #4]
800705c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007060: b2db uxtb r3, r3
8007062: 2b21 cmp r3, #33 @ 0x21
8007064: d107 bne.n 8007076 <I2C_ITMasterCplt+0x32>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
8007066: 2101 movs r1, #1
8007068: 6878 ldr r0, [r7, #4]
800706a: f000 fd31 bl 8007ad0 <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
800706e: 687b ldr r3, [r7, #4]
8007070: 2211 movs r2, #17
8007072: 631a str r2, [r3, #48] @ 0x30
8007074: e00c b.n 8007090 <I2C_ITMasterCplt+0x4c>
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8007076: 687b ldr r3, [r7, #4]
8007078: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800707c: b2db uxtb r3, r3
800707e: 2b22 cmp r3, #34 @ 0x22
8007080: d106 bne.n 8007090 <I2C_ITMasterCplt+0x4c>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
8007082: 2102 movs r1, #2
8007084: 6878 ldr r0, [r7, #4]
8007086: f000 fd23 bl 8007ad0 <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
800708a: 687b ldr r3, [r7, #4]
800708c: 2212 movs r2, #18
800708e: 631a str r2, [r3, #48] @ 0x30
{
/* Do nothing */
}
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8007090: 687b ldr r3, [r7, #4]
8007092: 681b ldr r3, [r3, #0]
8007094: 6859 ldr r1, [r3, #4]
8007096: 687b ldr r3, [r7, #4]
8007098: 681a ldr r2, [r3, #0]
800709a: 4b4d ldr r3, [pc, #308] @ (80071d0 <I2C_ITMasterCplt+0x18c>)
800709c: 400b ands r3, r1
800709e: 6053 str r3, [r2, #4]
/* Reset handle parameters */
hi2c->XferISR = NULL;
80070a0: 687b ldr r3, [r7, #4]
80070a2: 2200 movs r2, #0
80070a4: 635a str r2, [r3, #52] @ 0x34
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
80070a6: 687b ldr r3, [r7, #4]
80070a8: 4a4a ldr r2, [pc, #296] @ (80071d4 <I2C_ITMasterCplt+0x190>)
80070aa: 62da str r2, [r3, #44] @ 0x2c
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
80070ac: 697b ldr r3, [r7, #20]
80070ae: 091b lsrs r3, r3, #4
80070b0: f003 0301 and.w r3, r3, #1
80070b4: 2b00 cmp r3, #0
80070b6: d009 beq.n 80070cc <I2C_ITMasterCplt+0x88>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
80070b8: 687b ldr r3, [r7, #4]
80070ba: 681b ldr r3, [r3, #0]
80070bc: 2210 movs r2, #16
80070be: 61da str r2, [r3, #28]
/* Set acknowledge error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
80070c0: 687b ldr r3, [r7, #4]
80070c2: 6c5b ldr r3, [r3, #68] @ 0x44
80070c4: f043 0204 orr.w r2, r3, #4
80070c8: 687b ldr r3, [r7, #4]
80070ca: 645a str r2, [r3, #68] @ 0x44
}
/* Fetch Last receive data if any */
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
80070cc: 687b ldr r3, [r7, #4]
80070ce: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80070d2: b2db uxtb r3, r3
80070d4: 2b60 cmp r3, #96 @ 0x60
80070d6: d10b bne.n 80070f0 <I2C_ITMasterCplt+0xac>
80070d8: 697b ldr r3, [r7, #20]
80070da: 089b lsrs r3, r3, #2
80070dc: f003 0301 and.w r3, r3, #1
80070e0: 2b00 cmp r3, #0
80070e2: d005 beq.n 80070f0 <I2C_ITMasterCplt+0xac>
{
/* Read data from RXDR */
tmpreg = (uint8_t)hi2c->Instance->RXDR;
80070e4: 687b ldr r3, [r7, #4]
80070e6: 681b ldr r3, [r3, #0]
80070e8: 6a5b ldr r3, [r3, #36] @ 0x24
80070ea: b2db uxtb r3, r3
80070ec: 60fb str r3, [r7, #12]
UNUSED(tmpreg);
80070ee: 68fb ldr r3, [r7, #12]
}
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
80070f0: 6878 ldr r0, [r7, #4]
80070f2: f000 fb48 bl 8007786 <I2C_Flush_TXDR>
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
80070f6: 687b ldr r3, [r7, #4]
80070f8: 6c5b ldr r3, [r3, #68] @ 0x44
80070fa: 613b str r3, [r7, #16]
/* Call the corresponding callback to inform upper layer of End of Transfer */
if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
80070fc: 687b ldr r3, [r7, #4]
80070fe: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007102: b2db uxtb r3, r3
8007104: 2b60 cmp r3, #96 @ 0x60
8007106: d002 beq.n 800710e <I2C_ITMasterCplt+0xca>
8007108: 693b ldr r3, [r7, #16]
800710a: 2b00 cmp r3, #0
800710c: d006 beq.n 800711c <I2C_ITMasterCplt+0xd8>
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
800710e: 687b ldr r3, [r7, #4]
8007110: 6c5b ldr r3, [r3, #68] @ 0x44
8007112: 4619 mov r1, r3
8007114: 6878 ldr r0, [r7, #4]
8007116: f000 fa1f bl 8007558 <I2C_ITError>
}
else
{
/* Nothing to do */
}
}
800711a: e054 b.n 80071c6 <I2C_ITMasterCplt+0x182>
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
800711c: 687b ldr r3, [r7, #4]
800711e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007122: b2db uxtb r3, r3
8007124: 2b21 cmp r3, #33 @ 0x21
8007126: d124 bne.n 8007172 <I2C_ITMasterCplt+0x12e>
hi2c->State = HAL_I2C_STATE_READY;
8007128: 687b ldr r3, [r7, #4]
800712a: 2220 movs r2, #32
800712c: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8007130: 687b ldr r3, [r7, #4]
8007132: 2200 movs r2, #0
8007134: 631a str r2, [r3, #48] @ 0x30
if (hi2c->Mode == HAL_I2C_MODE_MEM)
8007136: 687b ldr r3, [r7, #4]
8007138: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
800713c: b2db uxtb r3, r3
800713e: 2b40 cmp r3, #64 @ 0x40
8007140: d10b bne.n 800715a <I2C_ITMasterCplt+0x116>
hi2c->Mode = HAL_I2C_MODE_NONE;
8007142: 687b ldr r3, [r7, #4]
8007144: 2200 movs r2, #0
8007146: f883 2042 strb.w r2, [r3, #66] @ 0x42
__HAL_UNLOCK(hi2c);
800714a: 687b ldr r3, [r7, #4]
800714c: 2200 movs r2, #0
800714e: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_MemTxCpltCallback(hi2c);
8007152: 6878 ldr r0, [r7, #4]
8007154: f7fd f938 bl 80043c8 <HAL_I2C_MemTxCpltCallback>
}
8007158: e035 b.n 80071c6 <I2C_ITMasterCplt+0x182>
hi2c->Mode = HAL_I2C_MODE_NONE;
800715a: 687b ldr r3, [r7, #4]
800715c: 2200 movs r2, #0
800715e: f883 2042 strb.w r2, [r3, #66] @ 0x42
__HAL_UNLOCK(hi2c);
8007162: 687b ldr r3, [r7, #4]
8007164: 2200 movs r2, #0
8007166: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_MasterTxCpltCallback(hi2c);
800716a: 6878 ldr r0, [r7, #4]
800716c: f7ff f9ed bl 800654a <HAL_I2C_MasterTxCpltCallback>
}
8007170: e029 b.n 80071c6 <I2C_ITMasterCplt+0x182>
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8007172: 687b ldr r3, [r7, #4]
8007174: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007178: b2db uxtb r3, r3
800717a: 2b22 cmp r3, #34 @ 0x22
800717c: d123 bne.n 80071c6 <I2C_ITMasterCplt+0x182>
hi2c->State = HAL_I2C_STATE_READY;
800717e: 687b ldr r3, [r7, #4]
8007180: 2220 movs r2, #32
8007182: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8007186: 687b ldr r3, [r7, #4]
8007188: 2200 movs r2, #0
800718a: 631a str r2, [r3, #48] @ 0x30
if (hi2c->Mode == HAL_I2C_MODE_MEM)
800718c: 687b ldr r3, [r7, #4]
800718e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
8007192: b2db uxtb r3, r3
8007194: 2b40 cmp r3, #64 @ 0x40
8007196: d10b bne.n 80071b0 <I2C_ITMasterCplt+0x16c>
hi2c->Mode = HAL_I2C_MODE_NONE;
8007198: 687b ldr r3, [r7, #4]
800719a: 2200 movs r2, #0
800719c: f883 2042 strb.w r2, [r3, #66] @ 0x42
__HAL_UNLOCK(hi2c);
80071a0: 687b ldr r3, [r7, #4]
80071a2: 2200 movs r2, #0
80071a4: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_MemRxCpltCallback(hi2c);
80071a8: 6878 ldr r0, [r7, #4]
80071aa: f7fd f8e5 bl 8004378 <HAL_I2C_MemRxCpltCallback>
}
80071ae: e00a b.n 80071c6 <I2C_ITMasterCplt+0x182>
hi2c->Mode = HAL_I2C_MODE_NONE;
80071b0: 687b ldr r3, [r7, #4]
80071b2: 2200 movs r2, #0
80071b4: f883 2042 strb.w r2, [r3, #66] @ 0x42
__HAL_UNLOCK(hi2c);
80071b8: 687b ldr r3, [r7, #4]
80071ba: 2200 movs r2, #0
80071bc: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_MasterRxCpltCallback(hi2c);
80071c0: 6878 ldr r0, [r7, #4]
80071c2: f7ff f9cc bl 800655e <HAL_I2C_MasterRxCpltCallback>
}
80071c6: bf00 nop
80071c8: 3718 adds r7, #24
80071ca: 46bd mov sp, r7
80071cc: bd80 pop {r7, pc}
80071ce: bf00 nop
80071d0: fe00e800 .word 0xfe00e800
80071d4: ffff0000 .word 0xffff0000
080071d8 <I2C_ITSlaveCplt>:
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
80071d8: b580 push {r7, lr}
80071da: b086 sub sp, #24
80071dc: af00 add r7, sp, #0
80071de: 6078 str r0, [r7, #4]
80071e0: 6039 str r1, [r7, #0]
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
80071e2: 687b ldr r3, [r7, #4]
80071e4: 681b ldr r3, [r3, #0]
80071e6: 681b ldr r3, [r3, #0]
80071e8: 613b str r3, [r7, #16]
uint32_t tmpITFlags = ITFlags;
80071ea: 683b ldr r3, [r7, #0]
80071ec: 617b str r3, [r7, #20]
uint32_t tmpoptions = hi2c->XferOptions;
80071ee: 687b ldr r3, [r7, #4]
80071f0: 6adb ldr r3, [r3, #44] @ 0x2c
80071f2: 60fb str r3, [r7, #12]
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
80071f4: 687b ldr r3, [r7, #4]
80071f6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80071fa: 72fb strb r3, [r7, #11]
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
80071fc: 687b ldr r3, [r7, #4]
80071fe: 681b ldr r3, [r3, #0]
8007200: 2220 movs r2, #32
8007202: 61da str r2, [r3, #28]
/* Disable Interrupts and Store Previous state */
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
8007204: 7afb ldrb r3, [r7, #11]
8007206: 2b21 cmp r3, #33 @ 0x21
8007208: d002 beq.n 8007210 <I2C_ITSlaveCplt+0x38>
800720a: 7afb ldrb r3, [r7, #11]
800720c: 2b29 cmp r3, #41 @ 0x29
800720e: d108 bne.n 8007222 <I2C_ITSlaveCplt+0x4a>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
8007210: f248 0101 movw r1, #32769 @ 0x8001
8007214: 6878 ldr r0, [r7, #4]
8007216: f000 fc5b bl 8007ad0 <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
800721a: 687b ldr r3, [r7, #4]
800721c: 2221 movs r2, #33 @ 0x21
800721e: 631a str r2, [r3, #48] @ 0x30
8007220: e019 b.n 8007256 <I2C_ITSlaveCplt+0x7e>
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
8007222: 7afb ldrb r3, [r7, #11]
8007224: 2b22 cmp r3, #34 @ 0x22
8007226: d002 beq.n 800722e <I2C_ITSlaveCplt+0x56>
8007228: 7afb ldrb r3, [r7, #11]
800722a: 2b2a cmp r3, #42 @ 0x2a
800722c: d108 bne.n 8007240 <I2C_ITSlaveCplt+0x68>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
800722e: f248 0102 movw r1, #32770 @ 0x8002
8007232: 6878 ldr r0, [r7, #4]
8007234: f000 fc4c bl 8007ad0 <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
8007238: 687b ldr r3, [r7, #4]
800723a: 2222 movs r2, #34 @ 0x22
800723c: 631a str r2, [r3, #48] @ 0x30
800723e: e00a b.n 8007256 <I2C_ITSlaveCplt+0x7e>
}
else if (tmpstate == HAL_I2C_STATE_LISTEN)
8007240: 7afb ldrb r3, [r7, #11]
8007242: 2b28 cmp r3, #40 @ 0x28
8007244: d107 bne.n 8007256 <I2C_ITSlaveCplt+0x7e>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
8007246: f248 0103 movw r1, #32771 @ 0x8003
800724a: 6878 ldr r0, [r7, #4]
800724c: f000 fc40 bl 8007ad0 <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_NONE;
8007250: 687b ldr r3, [r7, #4]
8007252: 2200 movs r2, #0
8007254: 631a str r2, [r3, #48] @ 0x30
{
/* Do nothing */
}
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
8007256: 687b ldr r3, [r7, #4]
8007258: 681b ldr r3, [r3, #0]
800725a: 685a ldr r2, [r3, #4]
800725c: 687b ldr r3, [r7, #4]
800725e: 681b ldr r3, [r3, #0]
8007260: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8007264: 605a str r2, [r3, #4]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8007266: 687b ldr r3, [r7, #4]
8007268: 681b ldr r3, [r3, #0]
800726a: 6859 ldr r1, [r3, #4]
800726c: 687b ldr r3, [r7, #4]
800726e: 681a ldr r2, [r3, #0]
8007270: 4b8c ldr r3, [pc, #560] @ (80074a4 <I2C_ITSlaveCplt+0x2cc>)
8007272: 400b ands r3, r1
8007274: 6053 str r3, [r2, #4]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8007276: 6878 ldr r0, [r7, #4]
8007278: f000 fa85 bl 8007786 <I2C_Flush_TXDR>
#if defined(HAL_DMA_MODULE_ENABLED)
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
800727c: 693b ldr r3, [r7, #16]
800727e: 0b9b lsrs r3, r3, #14
8007280: f003 0301 and.w r3, r3, #1
8007284: 2b00 cmp r3, #0
8007286: d013 beq.n 80072b0 <I2C_ITSlaveCplt+0xd8>
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
8007288: 687b ldr r3, [r7, #4]
800728a: 681b ldr r3, [r3, #0]
800728c: 681a ldr r2, [r3, #0]
800728e: 687b ldr r3, [r7, #4]
8007290: 681b ldr r3, [r3, #0]
8007292: f422 4280 bic.w r2, r2, #16384 @ 0x4000
8007296: 601a str r2, [r3, #0]
if (hi2c->hdmatx != NULL)
8007298: 687b ldr r3, [r7, #4]
800729a: 6b9b ldr r3, [r3, #56] @ 0x38
800729c: 2b00 cmp r3, #0
800729e: d020 beq.n 80072e2 <I2C_ITSlaveCplt+0x10a>
{
hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
80072a0: 687b ldr r3, [r7, #4]
80072a2: 6b9b ldr r3, [r3, #56] @ 0x38
80072a4: 681b ldr r3, [r3, #0]
80072a6: 685b ldr r3, [r3, #4]
80072a8: b29a uxth r2, r3
80072aa: 687b ldr r3, [r7, #4]
80072ac: 855a strh r2, [r3, #42] @ 0x2a
80072ae: e018 b.n 80072e2 <I2C_ITSlaveCplt+0x10a>
}
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
80072b0: 693b ldr r3, [r7, #16]
80072b2: 0bdb lsrs r3, r3, #15
80072b4: f003 0301 and.w r3, r3, #1
80072b8: 2b00 cmp r3, #0
80072ba: d012 beq.n 80072e2 <I2C_ITSlaveCplt+0x10a>
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
80072bc: 687b ldr r3, [r7, #4]
80072be: 681b ldr r3, [r3, #0]
80072c0: 681a ldr r2, [r3, #0]
80072c2: 687b ldr r3, [r7, #4]
80072c4: 681b ldr r3, [r3, #0]
80072c6: f422 4200 bic.w r2, r2, #32768 @ 0x8000
80072ca: 601a str r2, [r3, #0]
if (hi2c->hdmarx != NULL)
80072cc: 687b ldr r3, [r7, #4]
80072ce: 6bdb ldr r3, [r3, #60] @ 0x3c
80072d0: 2b00 cmp r3, #0
80072d2: d006 beq.n 80072e2 <I2C_ITSlaveCplt+0x10a>
{
hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
80072d4: 687b ldr r3, [r7, #4]
80072d6: 6bdb ldr r3, [r3, #60] @ 0x3c
80072d8: 681b ldr r3, [r3, #0]
80072da: 685b ldr r3, [r3, #4]
80072dc: b29a uxth r2, r3
80072de: 687b ldr r3, [r7, #4]
80072e0: 855a strh r2, [r3, #42] @ 0x2a
/* Do nothing */
}
#endif /* HAL_DMA_MODULE_ENABLED */
/* Store Last receive data if any */
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
80072e2: 697b ldr r3, [r7, #20]
80072e4: 089b lsrs r3, r3, #2
80072e6: f003 0301 and.w r3, r3, #1
80072ea: 2b00 cmp r3, #0
80072ec: d020 beq.n 8007330 <I2C_ITSlaveCplt+0x158>
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
80072ee: 697b ldr r3, [r7, #20]
80072f0: f023 0304 bic.w r3, r3, #4
80072f4: 617b str r3, [r7, #20]
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
80072f6: 687b ldr r3, [r7, #4]
80072f8: 681b ldr r3, [r3, #0]
80072fa: 6a5a ldr r2, [r3, #36] @ 0x24
80072fc: 687b ldr r3, [r7, #4]
80072fe: 6a5b ldr r3, [r3, #36] @ 0x24
8007300: b2d2 uxtb r2, r2
8007302: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8007304: 687b ldr r3, [r7, #4]
8007306: 6a5b ldr r3, [r3, #36] @ 0x24
8007308: 1c5a adds r2, r3, #1
800730a: 687b ldr r3, [r7, #4]
800730c: 625a str r2, [r3, #36] @ 0x24
if (hi2c->XferSize > 0U)
800730e: 687b ldr r3, [r7, #4]
8007310: 8d1b ldrh r3, [r3, #40] @ 0x28
8007312: 2b00 cmp r3, #0
8007314: d00c beq.n 8007330 <I2C_ITSlaveCplt+0x158>
{
hi2c->XferSize--;
8007316: 687b ldr r3, [r7, #4]
8007318: 8d1b ldrh r3, [r3, #40] @ 0x28
800731a: 3b01 subs r3, #1
800731c: b29a uxth r2, r3
800731e: 687b ldr r3, [r7, #4]
8007320: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8007322: 687b ldr r3, [r7, #4]
8007324: 8d5b ldrh r3, [r3, #42] @ 0x2a
8007326: b29b uxth r3, r3
8007328: 3b01 subs r3, #1
800732a: b29a uxth r2, r3
800732c: 687b ldr r3, [r7, #4]
800732e: 855a strh r2, [r3, #42] @ 0x2a
}
}
/* All data are not transferred, so set error code accordingly */
if (hi2c->XferCount != 0U)
8007330: 687b ldr r3, [r7, #4]
8007332: 8d5b ldrh r3, [r3, #42] @ 0x2a
8007334: b29b uxth r3, r3
8007336: 2b00 cmp r3, #0
8007338: d005 beq.n 8007346 <I2C_ITSlaveCplt+0x16e>
{
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
800733a: 687b ldr r3, [r7, #4]
800733c: 6c5b ldr r3, [r3, #68] @ 0x44
800733e: f043 0204 orr.w r2, r3, #4
8007342: 687b ldr r3, [r7, #4]
8007344: 645a str r2, [r3, #68] @ 0x44
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
8007346: 697b ldr r3, [r7, #20]
8007348: 091b lsrs r3, r3, #4
800734a: f003 0301 and.w r3, r3, #1
800734e: 2b00 cmp r3, #0
8007350: d04a beq.n 80073e8 <I2C_ITSlaveCplt+0x210>
(I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
8007352: 693b ldr r3, [r7, #16]
8007354: 091b lsrs r3, r3, #4
8007356: f003 0301 and.w r3, r3, #1
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
800735a: 2b00 cmp r3, #0
800735c: d044 beq.n 80073e8 <I2C_ITSlaveCplt+0x210>
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
800735e: 687b ldr r3, [r7, #4]
8007360: 8d5b ldrh r3, [r3, #42] @ 0x2a
8007362: b29b uxth r3, r3
8007364: 2b00 cmp r3, #0
8007366: d128 bne.n 80073ba <I2C_ITSlaveCplt+0x1e2>
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
8007368: 687b ldr r3, [r7, #4]
800736a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800736e: b2db uxtb r3, r3
8007370: 2b28 cmp r3, #40 @ 0x28
8007372: d108 bne.n 8007386 <I2C_ITSlaveCplt+0x1ae>
8007374: 68fb ldr r3, [r7, #12]
8007376: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
800737a: d104 bne.n 8007386 <I2C_ITSlaveCplt+0x1ae>
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
800737c: 6979 ldr r1, [r7, #20]
800737e: 6878 ldr r0, [r7, #4]
8007380: f000 f894 bl 80074ac <I2C_ITListenCplt>
8007384: e030 b.n 80073e8 <I2C_ITSlaveCplt+0x210>
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
8007386: 687b ldr r3, [r7, #4]
8007388: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800738c: b2db uxtb r3, r3
800738e: 2b29 cmp r3, #41 @ 0x29
8007390: d10e bne.n 80073b0 <I2C_ITSlaveCplt+0x1d8>
8007392: 68fb ldr r3, [r7, #12]
8007394: f513 3f80 cmn.w r3, #65536 @ 0x10000
8007398: d00a beq.n 80073b0 <I2C_ITSlaveCplt+0x1d8>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
800739a: 687b ldr r3, [r7, #4]
800739c: 681b ldr r3, [r3, #0]
800739e: 2210 movs r2, #16
80073a0: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
80073a2: 6878 ldr r0, [r7, #4]
80073a4: f000 f9ef bl 8007786 <I2C_Flush_TXDR>
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
80073a8: 6878 ldr r0, [r7, #4]
80073aa: f7ff fded bl 8006f88 <I2C_ITSlaveSeqCplt>
80073ae: e01b b.n 80073e8 <I2C_ITSlaveCplt+0x210>
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
80073b0: 687b ldr r3, [r7, #4]
80073b2: 681b ldr r3, [r3, #0]
80073b4: 2210 movs r2, #16
80073b6: 61da str r2, [r3, #28]
80073b8: e016 b.n 80073e8 <I2C_ITSlaveCplt+0x210>
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
80073ba: 687b ldr r3, [r7, #4]
80073bc: 681b ldr r3, [r3, #0]
80073be: 2210 movs r2, #16
80073c0: 61da str r2, [r3, #28]
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
80073c2: 687b ldr r3, [r7, #4]
80073c4: 6c5b ldr r3, [r3, #68] @ 0x44
80073c6: f043 0204 orr.w r2, r3, #4
80073ca: 687b ldr r3, [r7, #4]
80073cc: 645a str r2, [r3, #68] @ 0x44
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
80073ce: 68fb ldr r3, [r7, #12]
80073d0: 2b00 cmp r3, #0
80073d2: d003 beq.n 80073dc <I2C_ITSlaveCplt+0x204>
80073d4: 68fb ldr r3, [r7, #12]
80073d6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80073da: d105 bne.n 80073e8 <I2C_ITSlaveCplt+0x210>
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
80073dc: 687b ldr r3, [r7, #4]
80073de: 6c5b ldr r3, [r3, #68] @ 0x44
80073e0: 4619 mov r1, r3
80073e2: 6878 ldr r0, [r7, #4]
80073e4: f000 f8b8 bl 8007558 <I2C_ITError>
}
}
}
hi2c->Mode = HAL_I2C_MODE_NONE;
80073e8: 687b ldr r3, [r7, #4]
80073ea: 2200 movs r2, #0
80073ec: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->XferISR = NULL;
80073f0: 687b ldr r3, [r7, #4]
80073f2: 2200 movs r2, #0
80073f4: 635a str r2, [r3, #52] @ 0x34
if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
80073f6: 687b ldr r3, [r7, #4]
80073f8: 6c5b ldr r3, [r3, #68] @ 0x44
80073fa: 2b00 cmp r3, #0
80073fc: d010 beq.n 8007420 <I2C_ITSlaveCplt+0x248>
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
80073fe: 687b ldr r3, [r7, #4]
8007400: 6c5b ldr r3, [r3, #68] @ 0x44
8007402: 4619 mov r1, r3
8007404: 6878 ldr r0, [r7, #4]
8007406: f000 f8a7 bl 8007558 <I2C_ITError>
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
if (hi2c->State == HAL_I2C_STATE_LISTEN)
800740a: 687b ldr r3, [r7, #4]
800740c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007410: b2db uxtb r3, r3
8007412: 2b28 cmp r3, #40 @ 0x28
8007414: d141 bne.n 800749a <I2C_ITSlaveCplt+0x2c2>
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
8007416: 6979 ldr r1, [r7, #20]
8007418: 6878 ldr r0, [r7, #4]
800741a: f000 f847 bl 80074ac <I2C_ITListenCplt>
hi2c->SlaveTxCpltCallback(hi2c);
#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
800741e: e03c b.n 800749a <I2C_ITSlaveCplt+0x2c2>
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
8007420: 687b ldr r3, [r7, #4]
8007422: 6adb ldr r3, [r3, #44] @ 0x2c
8007424: f513 3f80 cmn.w r3, #65536 @ 0x10000
8007428: d014 beq.n 8007454 <I2C_ITSlaveCplt+0x27c>
I2C_ITSlaveSeqCplt(hi2c);
800742a: 6878 ldr r0, [r7, #4]
800742c: f7ff fdac bl 8006f88 <I2C_ITSlaveSeqCplt>
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8007430: 687b ldr r3, [r7, #4]
8007432: 4a1d ldr r2, [pc, #116] @ (80074a8 <I2C_ITSlaveCplt+0x2d0>)
8007434: 62da str r2, [r3, #44] @ 0x2c
hi2c->State = HAL_I2C_STATE_READY;
8007436: 687b ldr r3, [r7, #4]
8007438: 2220 movs r2, #32
800743a: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
800743e: 687b ldr r3, [r7, #4]
8007440: 2200 movs r2, #0
8007442: 631a str r2, [r3, #48] @ 0x30
__HAL_UNLOCK(hi2c);
8007444: 687b ldr r3, [r7, #4]
8007446: 2200 movs r2, #0
8007448: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_ListenCpltCallback(hi2c);
800744c: 6878 ldr r0, [r7, #4]
800744e: f7ff f8b2 bl 80065b6 <HAL_I2C_ListenCpltCallback>
}
8007452: e022 b.n 800749a <I2C_ITSlaveCplt+0x2c2>
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8007454: 687b ldr r3, [r7, #4]
8007456: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
800745a: b2db uxtb r3, r3
800745c: 2b22 cmp r3, #34 @ 0x22
800745e: d10e bne.n 800747e <I2C_ITSlaveCplt+0x2a6>
hi2c->State = HAL_I2C_STATE_READY;
8007460: 687b ldr r3, [r7, #4]
8007462: 2220 movs r2, #32
8007464: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8007468: 687b ldr r3, [r7, #4]
800746a: 2200 movs r2, #0
800746c: 631a str r2, [r3, #48] @ 0x30
__HAL_UNLOCK(hi2c);
800746e: 687b ldr r3, [r7, #4]
8007470: 2200 movs r2, #0
8007472: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_SlaveRxCpltCallback(hi2c);
8007476: 6878 ldr r0, [r7, #4]
8007478: f7ff f885 bl 8006586 <HAL_I2C_SlaveRxCpltCallback>
}
800747c: e00d b.n 800749a <I2C_ITSlaveCplt+0x2c2>
hi2c->State = HAL_I2C_STATE_READY;
800747e: 687b ldr r3, [r7, #4]
8007480: 2220 movs r2, #32
8007482: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8007486: 687b ldr r3, [r7, #4]
8007488: 2200 movs r2, #0
800748a: 631a str r2, [r3, #48] @ 0x30
__HAL_UNLOCK(hi2c);
800748c: 687b ldr r3, [r7, #4]
800748e: 2200 movs r2, #0
8007490: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_SlaveTxCpltCallback(hi2c);
8007494: 6878 ldr r0, [r7, #4]
8007496: f7ff f86c bl 8006572 <HAL_I2C_SlaveTxCpltCallback>
}
800749a: bf00 nop
800749c: 3718 adds r7, #24
800749e: 46bd mov sp, r7
80074a0: bd80 pop {r7, pc}
80074a2: bf00 nop
80074a4: fe00e800 .word 0xfe00e800
80074a8: ffff0000 .word 0xffff0000
080074ac <I2C_ITListenCplt>:
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
80074ac: b580 push {r7, lr}
80074ae: b082 sub sp, #8
80074b0: af00 add r7, sp, #0
80074b2: 6078 str r0, [r7, #4]
80074b4: 6039 str r1, [r7, #0]
/* Reset handle parameters */
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
80074b6: 687b ldr r3, [r7, #4]
80074b8: 4a26 ldr r2, [pc, #152] @ (8007554 <I2C_ITListenCplt+0xa8>)
80074ba: 62da str r2, [r3, #44] @ 0x2c
hi2c->PreviousState = I2C_STATE_NONE;
80074bc: 687b ldr r3, [r7, #4]
80074be: 2200 movs r2, #0
80074c0: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
80074c2: 687b ldr r3, [r7, #4]
80074c4: 2220 movs r2, #32
80074c6: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
80074ca: 687b ldr r3, [r7, #4]
80074cc: 2200 movs r2, #0
80074ce: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->XferISR = NULL;
80074d2: 687b ldr r3, [r7, #4]
80074d4: 2200 movs r2, #0
80074d6: 635a str r2, [r3, #52] @ 0x34
/* Store Last receive data if any */
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
80074d8: 683b ldr r3, [r7, #0]
80074da: 089b lsrs r3, r3, #2
80074dc: f003 0301 and.w r3, r3, #1
80074e0: 2b00 cmp r3, #0
80074e2: d022 beq.n 800752a <I2C_ITListenCplt+0x7e>
{
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
80074e4: 687b ldr r3, [r7, #4]
80074e6: 681b ldr r3, [r3, #0]
80074e8: 6a5a ldr r2, [r3, #36] @ 0x24
80074ea: 687b ldr r3, [r7, #4]
80074ec: 6a5b ldr r3, [r3, #36] @ 0x24
80074ee: b2d2 uxtb r2, r2
80074f0: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
80074f2: 687b ldr r3, [r7, #4]
80074f4: 6a5b ldr r3, [r3, #36] @ 0x24
80074f6: 1c5a adds r2, r3, #1
80074f8: 687b ldr r3, [r7, #4]
80074fa: 625a str r2, [r3, #36] @ 0x24
if (hi2c->XferSize > 0U)
80074fc: 687b ldr r3, [r7, #4]
80074fe: 8d1b ldrh r3, [r3, #40] @ 0x28
8007500: 2b00 cmp r3, #0
8007502: d012 beq.n 800752a <I2C_ITListenCplt+0x7e>
{
hi2c->XferSize--;
8007504: 687b ldr r3, [r7, #4]
8007506: 8d1b ldrh r3, [r3, #40] @ 0x28
8007508: 3b01 subs r3, #1
800750a: b29a uxth r2, r3
800750c: 687b ldr r3, [r7, #4]
800750e: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8007510: 687b ldr r3, [r7, #4]
8007512: 8d5b ldrh r3, [r3, #42] @ 0x2a
8007514: b29b uxth r3, r3
8007516: 3b01 subs r3, #1
8007518: b29a uxth r2, r3
800751a: 687b ldr r3, [r7, #4]
800751c: 855a strh r2, [r3, #42] @ 0x2a
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
800751e: 687b ldr r3, [r7, #4]
8007520: 6c5b ldr r3, [r3, #68] @ 0x44
8007522: f043 0204 orr.w r2, r3, #4
8007526: 687b ldr r3, [r7, #4]
8007528: 645a str r2, [r3, #68] @ 0x44
}
}
/* Disable all Interrupts*/
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
800752a: f248 0103 movw r1, #32771 @ 0x8003
800752e: 6878 ldr r0, [r7, #4]
8007530: f000 face bl 8007ad0 <I2C_Disable_IRQ>
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8007534: 687b ldr r3, [r7, #4]
8007536: 681b ldr r3, [r3, #0]
8007538: 2210 movs r2, #16
800753a: 61da str r2, [r3, #28]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800753c: 687b ldr r3, [r7, #4]
800753e: 2200 movs r2, #0
8007540: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ListenCpltCallback(hi2c);
#else
HAL_I2C_ListenCpltCallback(hi2c);
8007544: 6878 ldr r0, [r7, #4]
8007546: f7ff f836 bl 80065b6 <HAL_I2C_ListenCpltCallback>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
800754a: bf00 nop
800754c: 3708 adds r7, #8
800754e: 46bd mov sp, r7
8007550: bd80 pop {r7, pc}
8007552: bf00 nop
8007554: ffff0000 .word 0xffff0000
08007558 <I2C_ITError>:
* @param hi2c I2C handle.
* @param ErrorCode Error code to handle.
* @retval None
*/
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
8007558: b580 push {r7, lr}
800755a: b084 sub sp, #16
800755c: af00 add r7, sp, #0
800755e: 6078 str r0, [r7, #4]
8007560: 6039 str r1, [r7, #0]
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
8007562: 687b ldr r3, [r7, #4]
8007564: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007568: 73fb strb r3, [r7, #15]
#if defined(HAL_DMA_MODULE_ENABLED)
uint32_t tmppreviousstate;
#endif /* HAL_DMA_MODULE_ENABLED */
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
800756a: 687b ldr r3, [r7, #4]
800756c: 2200 movs r2, #0
800756e: f883 2042 strb.w r2, [r3, #66] @ 0x42
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8007572: 687b ldr r3, [r7, #4]
8007574: 4a6d ldr r2, [pc, #436] @ (800772c <I2C_ITError+0x1d4>)
8007576: 62da str r2, [r3, #44] @ 0x2c
hi2c->XferCount = 0U;
8007578: 687b ldr r3, [r7, #4]
800757a: 2200 movs r2, #0
800757c: 855a strh r2, [r3, #42] @ 0x2a
/* Set new error code */
hi2c->ErrorCode |= ErrorCode;
800757e: 687b ldr r3, [r7, #4]
8007580: 6c5a ldr r2, [r3, #68] @ 0x44
8007582: 683b ldr r3, [r7, #0]
8007584: 431a orrs r2, r3
8007586: 687b ldr r3, [r7, #4]
8007588: 645a str r2, [r3, #68] @ 0x44
/* Disable Interrupts */
if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
800758a: 7bfb ldrb r3, [r7, #15]
800758c: 2b28 cmp r3, #40 @ 0x28
800758e: d005 beq.n 800759c <I2C_ITError+0x44>
8007590: 7bfb ldrb r3, [r7, #15]
8007592: 2b29 cmp r3, #41 @ 0x29
8007594: d002 beq.n 800759c <I2C_ITError+0x44>
(tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
8007596: 7bfb ldrb r3, [r7, #15]
8007598: 2b2a cmp r3, #42 @ 0x2a
800759a: d10b bne.n 80075b4 <I2C_ITError+0x5c>
(tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
800759c: 2103 movs r1, #3
800759e: 6878 ldr r0, [r7, #4]
80075a0: f000 fa96 bl 8007ad0 <I2C_Disable_IRQ>
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
80075a4: 687b ldr r3, [r7, #4]
80075a6: 2228 movs r2, #40 @ 0x28
80075a8: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->XferISR = I2C_Slave_ISR_IT;
80075ac: 687b ldr r3, [r7, #4]
80075ae: 4a60 ldr r2, [pc, #384] @ (8007730 <I2C_ITError+0x1d8>)
80075b0: 635a str r2, [r3, #52] @ 0x34
80075b2: e030 b.n 8007616 <I2C_ITError+0xbe>
}
else
{
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
80075b4: f248 0103 movw r1, #32771 @ 0x8003
80075b8: 6878 ldr r0, [r7, #4]
80075ba: f000 fa89 bl 8007ad0 <I2C_Disable_IRQ>
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
80075be: 6878 ldr r0, [r7, #4]
80075c0: f000 f8e1 bl 8007786 <I2C_Flush_TXDR>
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
80075c4: 687b ldr r3, [r7, #4]
80075c6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80075ca: b2db uxtb r3, r3
80075cc: 2b60 cmp r3, #96 @ 0x60
80075ce: d01f beq.n 8007610 <I2C_ITError+0xb8>
{
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
80075d0: 687b ldr r3, [r7, #4]
80075d2: 2220 movs r2, #32
80075d4: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
80075d8: 687b ldr r3, [r7, #4]
80075da: 681b ldr r3, [r3, #0]
80075dc: 699b ldr r3, [r3, #24]
80075de: f003 0320 and.w r3, r3, #32
80075e2: 2b20 cmp r3, #32
80075e4: d114 bne.n 8007610 <I2C_ITError+0xb8>
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
80075e6: 687b ldr r3, [r7, #4]
80075e8: 681b ldr r3, [r3, #0]
80075ea: 699b ldr r3, [r3, #24]
80075ec: f003 0310 and.w r3, r3, #16
80075f0: 2b10 cmp r3, #16
80075f2: d109 bne.n 8007608 <I2C_ITError+0xb0>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
80075f4: 687b ldr r3, [r7, #4]
80075f6: 681b ldr r3, [r3, #0]
80075f8: 2210 movs r2, #16
80075fa: 61da str r2, [r3, #28]
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
80075fc: 687b ldr r3, [r7, #4]
80075fe: 6c5b ldr r3, [r3, #68] @ 0x44
8007600: f043 0204 orr.w r2, r3, #4
8007604: 687b ldr r3, [r7, #4]
8007606: 645a str r2, [r3, #68] @ 0x44
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8007608: 687b ldr r3, [r7, #4]
800760a: 681b ldr r3, [r3, #0]
800760c: 2220 movs r2, #32
800760e: 61da str r2, [r3, #28]
}
}
hi2c->XferISR = NULL;
8007610: 687b ldr r3, [r7, #4]
8007612: 2200 movs r2, #0
8007614: 635a str r2, [r3, #52] @ 0x34
}
#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
8007616: 687b ldr r3, [r7, #4]
8007618: 6b1b ldr r3, [r3, #48] @ 0x30
800761a: 60bb str r3, [r7, #8]
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
800761c: 687b ldr r3, [r7, #4]
800761e: 6b9b ldr r3, [r3, #56] @ 0x38
8007620: 2b00 cmp r3, #0
8007622: d039 beq.n 8007698 <I2C_ITError+0x140>
8007624: 68bb ldr r3, [r7, #8]
8007626: 2b11 cmp r3, #17
8007628: d002 beq.n 8007630 <I2C_ITError+0xd8>
800762a: 68bb ldr r3, [r7, #8]
800762c: 2b21 cmp r3, #33 @ 0x21
800762e: d133 bne.n 8007698 <I2C_ITError+0x140>
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
8007630: 687b ldr r3, [r7, #4]
8007632: 681b ldr r3, [r3, #0]
8007634: 681b ldr r3, [r3, #0]
8007636: f403 4380 and.w r3, r3, #16384 @ 0x4000
800763a: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
800763e: d107 bne.n 8007650 <I2C_ITError+0xf8>
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
8007640: 687b ldr r3, [r7, #4]
8007642: 681b ldr r3, [r3, #0]
8007644: 681a ldr r2, [r3, #0]
8007646: 687b ldr r3, [r7, #4]
8007648: 681b ldr r3, [r3, #0]
800764a: f422 4280 bic.w r2, r2, #16384 @ 0x4000
800764e: 601a str r2, [r3, #0]
}
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
8007650: 687b ldr r3, [r7, #4]
8007652: 6b9b ldr r3, [r3, #56] @ 0x38
8007654: 4618 mov r0, r3
8007656: f7fe fa38 bl 8005aca <HAL_DMA_GetState>
800765a: 4603 mov r3, r0
800765c: 2b01 cmp r3, #1
800765e: d017 beq.n 8007690 <I2C_ITError+0x138>
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
8007660: 687b ldr r3, [r7, #4]
8007662: 6b9b ldr r3, [r3, #56] @ 0x38
8007664: 4a33 ldr r2, [pc, #204] @ (8007734 <I2C_ITError+0x1dc>)
8007666: 639a str r2, [r3, #56] @ 0x38
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007668: 687b ldr r3, [r7, #4]
800766a: 2200 movs r2, #0
800766c: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
8007670: 687b ldr r3, [r7, #4]
8007672: 6b9b ldr r3, [r3, #56] @ 0x38
8007674: 4618 mov r0, r3
8007676: f7fe f91a bl 80058ae <HAL_DMA_Abort_IT>
800767a: 4603 mov r3, r0
800767c: 2b00 cmp r3, #0
800767e: d04d beq.n 800771c <I2C_ITError+0x1c4>
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
8007680: 687b ldr r3, [r7, #4]
8007682: 6b9b ldr r3, [r3, #56] @ 0x38
8007684: 6b9b ldr r3, [r3, #56] @ 0x38
8007686: 687a ldr r2, [r7, #4]
8007688: 6b92 ldr r2, [r2, #56] @ 0x38
800768a: 4610 mov r0, r2
800768c: 4798 blx r3
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
800768e: e045 b.n 800771c <I2C_ITError+0x1c4>
}
}
else
{
I2C_TreatErrorCallback(hi2c);
8007690: 6878 ldr r0, [r7, #4]
8007692: f000 f851 bl 8007738 <I2C_TreatErrorCallback>
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
8007696: e041 b.n 800771c <I2C_ITError+0x1c4>
}
}
/* Abort DMA RX transfer if any */
else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
8007698: 687b ldr r3, [r7, #4]
800769a: 6bdb ldr r3, [r3, #60] @ 0x3c
800769c: 2b00 cmp r3, #0
800769e: d039 beq.n 8007714 <I2C_ITError+0x1bc>
80076a0: 68bb ldr r3, [r7, #8]
80076a2: 2b12 cmp r3, #18
80076a4: d002 beq.n 80076ac <I2C_ITError+0x154>
80076a6: 68bb ldr r3, [r7, #8]
80076a8: 2b22 cmp r3, #34 @ 0x22
80076aa: d133 bne.n 8007714 <I2C_ITError+0x1bc>
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
80076ac: 687b ldr r3, [r7, #4]
80076ae: 681b ldr r3, [r3, #0]
80076b0: 681b ldr r3, [r3, #0]
80076b2: f403 4300 and.w r3, r3, #32768 @ 0x8000
80076b6: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80076ba: d107 bne.n 80076cc <I2C_ITError+0x174>
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
80076bc: 687b ldr r3, [r7, #4]
80076be: 681b ldr r3, [r3, #0]
80076c0: 681a ldr r2, [r3, #0]
80076c2: 687b ldr r3, [r7, #4]
80076c4: 681b ldr r3, [r3, #0]
80076c6: f422 4200 bic.w r2, r2, #32768 @ 0x8000
80076ca: 601a str r2, [r3, #0]
}
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
80076cc: 687b ldr r3, [r7, #4]
80076ce: 6bdb ldr r3, [r3, #60] @ 0x3c
80076d0: 4618 mov r0, r3
80076d2: f7fe f9fa bl 8005aca <HAL_DMA_GetState>
80076d6: 4603 mov r3, r0
80076d8: 2b01 cmp r3, #1
80076da: d017 beq.n 800770c <I2C_ITError+0x1b4>
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
80076dc: 687b ldr r3, [r7, #4]
80076de: 6bdb ldr r3, [r3, #60] @ 0x3c
80076e0: 4a14 ldr r2, [pc, #80] @ (8007734 <I2C_ITError+0x1dc>)
80076e2: 639a str r2, [r3, #56] @ 0x38
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80076e4: 687b ldr r3, [r7, #4]
80076e6: 2200 movs r2, #0
80076e8: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
80076ec: 687b ldr r3, [r7, #4]
80076ee: 6bdb ldr r3, [r3, #60] @ 0x3c
80076f0: 4618 mov r0, r3
80076f2: f7fe f8dc bl 80058ae <HAL_DMA_Abort_IT>
80076f6: 4603 mov r3, r0
80076f8: 2b00 cmp r3, #0
80076fa: d011 beq.n 8007720 <I2C_ITError+0x1c8>
{
/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
80076fc: 687b ldr r3, [r7, #4]
80076fe: 6bdb ldr r3, [r3, #60] @ 0x3c
8007700: 6b9b ldr r3, [r3, #56] @ 0x38
8007702: 687a ldr r2, [r7, #4]
8007704: 6bd2 ldr r2, [r2, #60] @ 0x3c
8007706: 4610 mov r0, r2
8007708: 4798 blx r3
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
800770a: e009 b.n 8007720 <I2C_ITError+0x1c8>
}
}
else
{
I2C_TreatErrorCallback(hi2c);
800770c: 6878 ldr r0, [r7, #4]
800770e: f000 f813 bl 8007738 <I2C_TreatErrorCallback>
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
8007712: e005 b.n 8007720 <I2C_ITError+0x1c8>
}
}
else
#endif /* HAL_DMA_MODULE_ENABLED */
{
I2C_TreatErrorCallback(hi2c);
8007714: 6878 ldr r0, [r7, #4]
8007716: f000 f80f bl 8007738 <I2C_TreatErrorCallback>
}
}
800771a: e002 b.n 8007722 <I2C_ITError+0x1ca>
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
800771c: bf00 nop
800771e: e000 b.n 8007722 <I2C_ITError+0x1ca>
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
8007720: bf00 nop
}
8007722: bf00 nop
8007724: 3710 adds r7, #16
8007726: 46bd mov sp, r7
8007728: bd80 pop {r7, pc}
800772a: bf00 nop
800772c: ffff0000 .word 0xffff0000
8007730: 080065f7 .word 0x080065f7
8007734: 08007929 .word 0x08007929
08007738 <I2C_TreatErrorCallback>:
* @brief I2C Error callback treatment.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
{
8007738: b580 push {r7, lr}
800773a: b082 sub sp, #8
800773c: af00 add r7, sp, #0
800773e: 6078 str r0, [r7, #4]
if (hi2c->State == HAL_I2C_STATE_ABORT)
8007740: 687b ldr r3, [r7, #4]
8007742: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007746: b2db uxtb r3, r3
8007748: 2b60 cmp r3, #96 @ 0x60
800774a: d10e bne.n 800776a <I2C_TreatErrorCallback+0x32>
{
hi2c->State = HAL_I2C_STATE_READY;
800774c: 687b ldr r3, [r7, #4]
800774e: 2220 movs r2, #32
8007750: f883 2041 strb.w r2, [r3, #65] @ 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8007754: 687b ldr r3, [r7, #4]
8007756: 2200 movs r2, #0
8007758: 631a str r2, [r3, #48] @ 0x30
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800775a: 687b ldr r3, [r7, #4]
800775c: 2200 movs r2, #0
800775e: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AbortCpltCallback(hi2c);
#else
HAL_I2C_AbortCpltCallback(hi2c);
8007762: 6878 ldr r0, [r7, #4]
8007764: f7fe ff31 bl 80065ca <HAL_I2C_AbortCpltCallback>
hi2c->ErrorCallback(hi2c);
#else
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
8007768: e009 b.n 800777e <I2C_TreatErrorCallback+0x46>
hi2c->PreviousState = I2C_STATE_NONE;
800776a: 687b ldr r3, [r7, #4]
800776c: 2200 movs r2, #0
800776e: 631a str r2, [r3, #48] @ 0x30
__HAL_UNLOCK(hi2c);
8007770: 687b ldr r3, [r7, #4]
8007772: 2200 movs r2, #0
8007774: f883 2040 strb.w r2, [r3, #64] @ 0x40
HAL_I2C_ErrorCallback(hi2c);
8007778: 6878 ldr r0, [r7, #4]
800777a: f7fc fe4d bl 8004418 <HAL_I2C_ErrorCallback>
}
800777e: bf00 nop
8007780: 3708 adds r7, #8
8007782: 46bd mov sp, r7
8007784: bd80 pop {r7, pc}
08007786 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
8007786: b480 push {r7}
8007788: b083 sub sp, #12
800778a: af00 add r7, sp, #0
800778c: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
800778e: 687b ldr r3, [r7, #4]
8007790: 681b ldr r3, [r3, #0]
8007792: 699b ldr r3, [r3, #24]
8007794: f003 0302 and.w r3, r3, #2
8007798: 2b02 cmp r3, #2
800779a: d103 bne.n 80077a4 <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
800779c: 687b ldr r3, [r7, #4]
800779e: 681b ldr r3, [r3, #0]
80077a0: 2200 movs r2, #0
80077a2: 629a str r2, [r3, #40] @ 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
80077a4: 687b ldr r3, [r7, #4]
80077a6: 681b ldr r3, [r3, #0]
80077a8: 699b ldr r3, [r3, #24]
80077aa: f003 0301 and.w r3, r3, #1
80077ae: 2b01 cmp r3, #1
80077b0: d007 beq.n 80077c2 <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
80077b2: 687b ldr r3, [r7, #4]
80077b4: 681b ldr r3, [r3, #0]
80077b6: 699a ldr r2, [r3, #24]
80077b8: 687b ldr r3, [r7, #4]
80077ba: 681b ldr r3, [r3, #0]
80077bc: f042 0201 orr.w r2, r2, #1
80077c0: 619a str r2, [r3, #24]
}
}
80077c2: bf00 nop
80077c4: 370c adds r7, #12
80077c6: 46bd mov sp, r7
80077c8: f85d 7b04 ldr.w r7, [sp], #4
80077cc: 4770 bx lr
080077ce <I2C_DMAMasterTransmitCplt>:
* @brief DMA I2C master transmit process complete callback.
* @param hdma DMA handle
* @retval None
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
80077ce: b580 push {r7, lr}
80077d0: b084 sub sp, #16
80077d2: af00 add r7, sp, #0
80077d4: 6078 str r0, [r7, #4]
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
80077d6: 687b ldr r3, [r7, #4]
80077d8: 6a9b ldr r3, [r3, #40] @ 0x28
80077da: 60fb str r3, [r7, #12]
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
80077dc: 68fb ldr r3, [r7, #12]
80077de: 681b ldr r3, [r3, #0]
80077e0: 681a ldr r2, [r3, #0]
80077e2: 68fb ldr r3, [r7, #12]
80077e4: 681b ldr r3, [r3, #0]
80077e6: f422 4280 bic.w r2, r2, #16384 @ 0x4000
80077ea: 601a str r2, [r3, #0]
/* If last transfer, enable STOP interrupt */
if (hi2c->XferCount == 0U)
80077ec: 68fb ldr r3, [r7, #12]
80077ee: 8d5b ldrh r3, [r3, #42] @ 0x2a
80077f0: b29b uxth r3, r3
80077f2: 2b00 cmp r3, #0
80077f4: d104 bne.n 8007800 <I2C_DMAMasterTransmitCplt+0x32>
{
/* Enable STOP interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
80077f6: 2120 movs r1, #32
80077f8: 68f8 ldr r0, [r7, #12]
80077fa: f000 f8e5 bl 80079c8 <I2C_Enable_IRQ>
{
/* Enable TC interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
}
}
}
80077fe: e02d b.n 800785c <I2C_DMAMasterTransmitCplt+0x8e>
hi2c->pBuffPtr += hi2c->XferSize;
8007800: 68fb ldr r3, [r7, #12]
8007802: 6a5b ldr r3, [r3, #36] @ 0x24
8007804: 68fa ldr r2, [r7, #12]
8007806: 8d12 ldrh r2, [r2, #40] @ 0x28
8007808: 441a add r2, r3
800780a: 68fb ldr r3, [r7, #12]
800780c: 625a str r2, [r3, #36] @ 0x24
if (hi2c->XferCount > MAX_NBYTE_SIZE)
800780e: 68fb ldr r3, [r7, #12]
8007810: 8d5b ldrh r3, [r3, #42] @ 0x2a
8007812: b29b uxth r3, r3
8007814: 2bff cmp r3, #255 @ 0xff
8007816: d903 bls.n 8007820 <I2C_DMAMasterTransmitCplt+0x52>
hi2c->XferSize = MAX_NBYTE_SIZE;
8007818: 68fb ldr r3, [r7, #12]
800781a: 22ff movs r2, #255 @ 0xff
800781c: 851a strh r2, [r3, #40] @ 0x28
800781e: e004 b.n 800782a <I2C_DMAMasterTransmitCplt+0x5c>
hi2c->XferSize = hi2c->XferCount;
8007820: 68fb ldr r3, [r7, #12]
8007822: 8d5b ldrh r3, [r3, #42] @ 0x2a
8007824: b29a uxth r2, r3
8007826: 68fb ldr r3, [r7, #12]
8007828: 851a strh r2, [r3, #40] @ 0x28
if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
800782a: 68fb ldr r3, [r7, #12]
800782c: 6b98 ldr r0, [r3, #56] @ 0x38
800782e: 68fb ldr r3, [r7, #12]
8007830: 6a5b ldr r3, [r3, #36] @ 0x24
8007832: 4619 mov r1, r3
8007834: 68fb ldr r3, [r7, #12]
8007836: 681b ldr r3, [r3, #0]
8007838: 3328 adds r3, #40 @ 0x28
800783a: 461a mov r2, r3
hi2c->XferSize) != HAL_OK)
800783c: 68fb ldr r3, [r7, #12]
800783e: 8d1b ldrh r3, [r3, #40] @ 0x28
if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
8007840: f7fd ffba bl 80057b8 <HAL_DMA_Start_IT>
8007844: 4603 mov r3, r0
8007846: 2b00 cmp r3, #0
8007848: d004 beq.n 8007854 <I2C_DMAMasterTransmitCplt+0x86>
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
800784a: 2110 movs r1, #16
800784c: 68f8 ldr r0, [r7, #12]
800784e: f7ff fe83 bl 8007558 <I2C_ITError>
}
8007852: e003 b.n 800785c <I2C_DMAMasterTransmitCplt+0x8e>
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
8007854: 2140 movs r1, #64 @ 0x40
8007856: 68f8 ldr r0, [r7, #12]
8007858: f000 f8b6 bl 80079c8 <I2C_Enable_IRQ>
}
800785c: bf00 nop
800785e: 3710 adds r7, #16
8007860: 46bd mov sp, r7
8007862: bd80 pop {r7, pc}
08007864 <I2C_DMAMasterReceiveCplt>:
* @brief DMA I2C master receive process complete callback.
* @param hdma DMA handle
* @retval None
*/
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
8007864: b580 push {r7, lr}
8007866: b084 sub sp, #16
8007868: af00 add r7, sp, #0
800786a: 6078 str r0, [r7, #4]
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
800786c: 687b ldr r3, [r7, #4]
800786e: 6a9b ldr r3, [r3, #40] @ 0x28
8007870: 60fb str r3, [r7, #12]
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
8007872: 68fb ldr r3, [r7, #12]
8007874: 681b ldr r3, [r3, #0]
8007876: 681a ldr r2, [r3, #0]
8007878: 68fb ldr r3, [r7, #12]
800787a: 681b ldr r3, [r3, #0]
800787c: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8007880: 601a str r2, [r3, #0]
/* If last transfer, enable STOP interrupt */
if (hi2c->XferCount == 0U)
8007882: 68fb ldr r3, [r7, #12]
8007884: 8d5b ldrh r3, [r3, #42] @ 0x2a
8007886: b29b uxth r3, r3
8007888: 2b00 cmp r3, #0
800788a: d104 bne.n 8007896 <I2C_DMAMasterReceiveCplt+0x32>
{
/* Enable STOP interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
800788c: 2120 movs r1, #32
800788e: 68f8 ldr r0, [r7, #12]
8007890: f000 f89a bl 80079c8 <I2C_Enable_IRQ>
{
/* Enable TC interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
}
}
}
8007894: e02d b.n 80078f2 <I2C_DMAMasterReceiveCplt+0x8e>
hi2c->pBuffPtr += hi2c->XferSize;
8007896: 68fb ldr r3, [r7, #12]
8007898: 6a5b ldr r3, [r3, #36] @ 0x24
800789a: 68fa ldr r2, [r7, #12]
800789c: 8d12 ldrh r2, [r2, #40] @ 0x28
800789e: 441a add r2, r3
80078a0: 68fb ldr r3, [r7, #12]
80078a2: 625a str r2, [r3, #36] @ 0x24
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80078a4: 68fb ldr r3, [r7, #12]
80078a6: 8d5b ldrh r3, [r3, #42] @ 0x2a
80078a8: b29b uxth r3, r3
80078aa: 2bff cmp r3, #255 @ 0xff
80078ac: d903 bls.n 80078b6 <I2C_DMAMasterReceiveCplt+0x52>
hi2c->XferSize = MAX_NBYTE_SIZE;
80078ae: 68fb ldr r3, [r7, #12]
80078b0: 22ff movs r2, #255 @ 0xff
80078b2: 851a strh r2, [r3, #40] @ 0x28
80078b4: e004 b.n 80078c0 <I2C_DMAMasterReceiveCplt+0x5c>
hi2c->XferSize = hi2c->XferCount;
80078b6: 68fb ldr r3, [r7, #12]
80078b8: 8d5b ldrh r3, [r3, #42] @ 0x2a
80078ba: b29a uxth r2, r3
80078bc: 68fb ldr r3, [r7, #12]
80078be: 851a strh r2, [r3, #40] @ 0x28
if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
80078c0: 68fb ldr r3, [r7, #12]
80078c2: 6bd8 ldr r0, [r3, #60] @ 0x3c
80078c4: 68fb ldr r3, [r7, #12]
80078c6: 681b ldr r3, [r3, #0]
80078c8: 3324 adds r3, #36 @ 0x24
80078ca: 4619 mov r1, r3
80078cc: 68fb ldr r3, [r7, #12]
80078ce: 6a5b ldr r3, [r3, #36] @ 0x24
80078d0: 461a mov r2, r3
hi2c->XferSize) != HAL_OK)
80078d2: 68fb ldr r3, [r7, #12]
80078d4: 8d1b ldrh r3, [r3, #40] @ 0x28
if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
80078d6: f7fd ff6f bl 80057b8 <HAL_DMA_Start_IT>
80078da: 4603 mov r3, r0
80078dc: 2b00 cmp r3, #0
80078de: d004 beq.n 80078ea <I2C_DMAMasterReceiveCplt+0x86>
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
80078e0: 2110 movs r1, #16
80078e2: 68f8 ldr r0, [r7, #12]
80078e4: f7ff fe38 bl 8007558 <I2C_ITError>
}
80078e8: e003 b.n 80078f2 <I2C_DMAMasterReceiveCplt+0x8e>
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
80078ea: 2140 movs r1, #64 @ 0x40
80078ec: 68f8 ldr r0, [r7, #12]
80078ee: f000 f86b bl 80079c8 <I2C_Enable_IRQ>
}
80078f2: bf00 nop
80078f4: 3710 adds r7, #16
80078f6: 46bd mov sp, r7
80078f8: bd80 pop {r7, pc}
080078fa <I2C_DMAError>:
* @brief DMA I2C communication error callback.
* @param hdma DMA handle
* @retval None
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
80078fa: b580 push {r7, lr}
80078fc: b084 sub sp, #16
80078fe: af00 add r7, sp, #0
8007900: 6078 str r0, [r7, #4]
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
8007902: 687b ldr r3, [r7, #4]
8007904: 6a9b ldr r3, [r3, #40] @ 0x28
8007906: 60fb str r3, [r7, #12]
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
8007908: 68fb ldr r3, [r7, #12]
800790a: 681b ldr r3, [r3, #0]
800790c: 685a ldr r2, [r3, #4]
800790e: 68fb ldr r3, [r7, #12]
8007910: 681b ldr r3, [r3, #0]
8007912: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8007916: 605a str r2, [r3, #4]
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
8007918: 2110 movs r1, #16
800791a: 68f8 ldr r0, [r7, #12]
800791c: f7ff fe1c bl 8007558 <I2C_ITError>
}
8007920: bf00 nop
8007922: 3710 adds r7, #16
8007924: 46bd mov sp, r7
8007926: bd80 pop {r7, pc}
08007928 <I2C_DMAAbort>:
* (To be called at end of DMA Abort procedure).
* @param hdma DMA handle.
* @retval None
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
8007928: b580 push {r7, lr}
800792a: b084 sub sp, #16
800792c: af00 add r7, sp, #0
800792e: 6078 str r0, [r7, #4]
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
8007930: 687b ldr r3, [r7, #4]
8007932: 6a9b ldr r3, [r3, #40] @ 0x28
8007934: 60fb str r3, [r7, #12]
/* Reset AbortCpltCallback */
if (hi2c->hdmatx != NULL)
8007936: 68fb ldr r3, [r7, #12]
8007938: 6b9b ldr r3, [r3, #56] @ 0x38
800793a: 2b00 cmp r3, #0
800793c: d003 beq.n 8007946 <I2C_DMAAbort+0x1e>
{
hi2c->hdmatx->XferAbortCallback = NULL;
800793e: 68fb ldr r3, [r7, #12]
8007940: 6b9b ldr r3, [r3, #56] @ 0x38
8007942: 2200 movs r2, #0
8007944: 639a str r2, [r3, #56] @ 0x38
}
if (hi2c->hdmarx != NULL)
8007946: 68fb ldr r3, [r7, #12]
8007948: 6bdb ldr r3, [r3, #60] @ 0x3c
800794a: 2b00 cmp r3, #0
800794c: d003 beq.n 8007956 <I2C_DMAAbort+0x2e>
{
hi2c->hdmarx->XferAbortCallback = NULL;
800794e: 68fb ldr r3, [r7, #12]
8007950: 6bdb ldr r3, [r3, #60] @ 0x3c
8007952: 2200 movs r2, #0
8007954: 639a str r2, [r3, #56] @ 0x38
}
I2C_TreatErrorCallback(hi2c);
8007956: 68f8 ldr r0, [r7, #12]
8007958: f7ff feee bl 8007738 <I2C_TreatErrorCallback>
}
800795c: bf00 nop
800795e: 3710 adds r7, #16
8007960: 46bd mov sp, r7
8007962: bd80 pop {r7, pc}
08007964 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
8007964: b480 push {r7}
8007966: b087 sub sp, #28
8007968: af00 add r7, sp, #0
800796a: 60f8 str r0, [r7, #12]
800796c: 607b str r3, [r7, #4]
800796e: 460b mov r3, r1
8007970: 817b strh r3, [r7, #10]
8007972: 4613 mov r3, r2
8007974: 727b strb r3, [r7, #9]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* Declaration of tmp to prevent undefined behavior of volatile usage */
tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8007976: 897b ldrh r3, [r7, #10]
8007978: f3c3 0209 ubfx r2, r3, #0, #10
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
800797c: 7a7b ldrb r3, [r7, #9]
800797e: 041b lsls r3, r3, #16
8007980: f403 037f and.w r3, r3, #16711680 @ 0xff0000
tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8007984: 431a orrs r2, r3
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
8007986: 687b ldr r3, [r7, #4]
8007988: 431a orrs r2, r3
tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
800798a: 6a3b ldr r3, [r7, #32]
800798c: 4313 orrs r3, r2
800798e: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8007992: 617b str r3, [r7, #20]
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
8007994: 68fb ldr r3, [r7, #12]
8007996: 681b ldr r3, [r3, #0]
8007998: 685a ldr r2, [r3, #4]
800799a: 6a3b ldr r3, [r7, #32]
800799c: 0d5b lsrs r3, r3, #21
800799e: f403 6180 and.w r1, r3, #1024 @ 0x400
80079a2: 4b08 ldr r3, [pc, #32] @ (80079c4 <I2C_TransferConfig+0x60>)
80079a4: 430b orrs r3, r1
80079a6: 43db mvns r3, r3
80079a8: ea02 0103 and.w r1, r2, r3
80079ac: 68fb ldr r3, [r7, #12]
80079ae: 681b ldr r3, [r3, #0]
80079b0: 697a ldr r2, [r7, #20]
80079b2: 430a orrs r2, r1
80079b4: 605a str r2, [r3, #4]
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
80079b6: bf00 nop
80079b8: 371c adds r7, #28
80079ba: 46bd mov sp, r7
80079bc: f85d 7b04 ldr.w r7, [sp], #4
80079c0: 4770 bx lr
80079c2: bf00 nop
80079c4: 03ff63ff .word 0x03ff63ff
080079c8 <I2C_Enable_IRQ>:
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
* @retval None
*/
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
80079c8: b480 push {r7}
80079ca: b085 sub sp, #20
80079cc: af00 add r7, sp, #0
80079ce: 6078 str r0, [r7, #4]
80079d0: 460b mov r3, r1
80079d2: 807b strh r3, [r7, #2]
uint32_t tmpisr = 0U;
80079d4: 2300 movs r3, #0
80079d6: 60fb str r3, [r7, #12]
#if defined(HAL_DMA_MODULE_ENABLED)
if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
80079d8: 687b ldr r3, [r7, #4]
80079da: 6b5b ldr r3, [r3, #52] @ 0x34
80079dc: 4a39 ldr r2, [pc, #228] @ (8007ac4 <I2C_Enable_IRQ+0xfc>)
80079de: 4293 cmp r3, r2
80079e0: d032 beq.n 8007a48 <I2C_Enable_IRQ+0x80>
(hi2c->XferISR != I2C_Slave_ISR_DMA) && \
80079e2: 687b ldr r3, [r7, #4]
80079e4: 6b5b ldr r3, [r3, #52] @ 0x34
if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
80079e6: 4a38 ldr r2, [pc, #224] @ (8007ac8 <I2C_Enable_IRQ+0x100>)
80079e8: 4293 cmp r3, r2
80079ea: d02d beq.n 8007a48 <I2C_Enable_IRQ+0x80>
(hi2c->XferISR != I2C_Mem_ISR_DMA))
80079ec: 687b ldr r3, [r7, #4]
80079ee: 6b5b ldr r3, [r3, #52] @ 0x34
(hi2c->XferISR != I2C_Slave_ISR_DMA) && \
80079f0: 4a36 ldr r2, [pc, #216] @ (8007acc <I2C_Enable_IRQ+0x104>)
80079f2: 4293 cmp r3, r2
80079f4: d028 beq.n 8007a48 <I2C_Enable_IRQ+0x80>
#endif /* HAL_DMA_MODULE_ENABLED */
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
80079f6: f9b7 3002 ldrsh.w r3, [r7, #2]
80079fa: 2b00 cmp r3, #0
80079fc: da03 bge.n 8007a06 <I2C_Enable_IRQ+0x3e>
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
80079fe: 68fb ldr r3, [r7, #12]
8007a00: f043 03b8 orr.w r3, r3, #184 @ 0xb8
8007a04: 60fb str r3, [r7, #12]
}
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
8007a06: 887b ldrh r3, [r7, #2]
8007a08: f003 0301 and.w r3, r3, #1
8007a0c: 2b00 cmp r3, #0
8007a0e: d003 beq.n 8007a18 <I2C_Enable_IRQ+0x50>
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
8007a10: 68fb ldr r3, [r7, #12]
8007a12: f043 03f2 orr.w r3, r3, #242 @ 0xf2
8007a16: 60fb str r3, [r7, #12]
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
8007a18: 887b ldrh r3, [r7, #2]
8007a1a: f003 0302 and.w r3, r3, #2
8007a1e: 2b00 cmp r3, #0
8007a20: d003 beq.n 8007a2a <I2C_Enable_IRQ+0x62>
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
8007a22: 68fb ldr r3, [r7, #12]
8007a24: f043 03f4 orr.w r3, r3, #244 @ 0xf4
8007a28: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
8007a2a: 887b ldrh r3, [r7, #2]
8007a2c: 2b10 cmp r3, #16
8007a2e: d103 bne.n 8007a38 <I2C_Enable_IRQ+0x70>
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
8007a30: 68fb ldr r3, [r7, #12]
8007a32: f043 0390 orr.w r3, r3, #144 @ 0x90
8007a36: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
8007a38: 887b ldrh r3, [r7, #2]
8007a3a: 2b20 cmp r3, #32
8007a3c: d133 bne.n 8007aa6 <I2C_Enable_IRQ+0xde>
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
8007a3e: 68fb ldr r3, [r7, #12]
8007a40: f043 0320 orr.w r3, r3, #32
8007a44: 60fb str r3, [r7, #12]
if (InterruptRequest == I2C_XFER_CPLT_IT)
8007a46: e02e b.n 8007aa6 <I2C_Enable_IRQ+0xde>
}
#if defined(HAL_DMA_MODULE_ENABLED)
else
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
8007a48: f9b7 3002 ldrsh.w r3, [r7, #2]
8007a4c: 2b00 cmp r3, #0
8007a4e: da03 bge.n 8007a58 <I2C_Enable_IRQ+0x90>
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
8007a50: 68fb ldr r3, [r7, #12]
8007a52: f043 03b8 orr.w r3, r3, #184 @ 0xb8
8007a56: 60fb str r3, [r7, #12]
}
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
8007a58: 887b ldrh r3, [r7, #2]
8007a5a: f003 0301 and.w r3, r3, #1
8007a5e: 2b00 cmp r3, #0
8007a60: d003 beq.n 8007a6a <I2C_Enable_IRQ+0xa2>
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
8007a62: 68fb ldr r3, [r7, #12]
8007a64: f043 03f2 orr.w r3, r3, #242 @ 0xf2
8007a68: 60fb str r3, [r7, #12]
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
8007a6a: 887b ldrh r3, [r7, #2]
8007a6c: f003 0302 and.w r3, r3, #2
8007a70: 2b00 cmp r3, #0
8007a72: d003 beq.n 8007a7c <I2C_Enable_IRQ+0xb4>
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
8007a74: 68fb ldr r3, [r7, #12]
8007a76: f043 03f4 orr.w r3, r3, #244 @ 0xf4
8007a7a: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
8007a7c: 887b ldrh r3, [r7, #2]
8007a7e: 2b10 cmp r3, #16
8007a80: d103 bne.n 8007a8a <I2C_Enable_IRQ+0xc2>
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
8007a82: 68fb ldr r3, [r7, #12]
8007a84: f043 0390 orr.w r3, r3, #144 @ 0x90
8007a88: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
8007a8a: 887b ldrh r3, [r7, #2]
8007a8c: 2b20 cmp r3, #32
8007a8e: d103 bne.n 8007a98 <I2C_Enable_IRQ+0xd0>
{
/* Enable STOP interrupts */
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
8007a90: 68fb ldr r3, [r7, #12]
8007a92: f043 0360 orr.w r3, r3, #96 @ 0x60
8007a96: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_RELOAD_IT)
8007a98: 887b ldrh r3, [r7, #2]
8007a9a: 2b40 cmp r3, #64 @ 0x40
8007a9c: d103 bne.n 8007aa6 <I2C_Enable_IRQ+0xde>
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
8007a9e: 68fb ldr r3, [r7, #12]
8007aa0: f043 0340 orr.w r3, r3, #64 @ 0x40
8007aa4: 60fb str r3, [r7, #12]
#endif /* HAL_DMA_MODULE_ENABLED */
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
8007aa6: 687b ldr r3, [r7, #4]
8007aa8: 681b ldr r3, [r3, #0]
8007aaa: 6819 ldr r1, [r3, #0]
8007aac: 687b ldr r3, [r7, #4]
8007aae: 681b ldr r3, [r3, #0]
8007ab0: 68fa ldr r2, [r7, #12]
8007ab2: 430a orrs r2, r1
8007ab4: 601a str r2, [r3, #0]
}
8007ab6: bf00 nop
8007ab8: 3714 adds r7, #20
8007aba: 46bd mov sp, r7
8007abc: f85d 7b04 ldr.w r7, [sp], #4
8007ac0: 4770 bx lr
8007ac2: bf00 nop
8007ac4: 080067ff .word 0x080067ff
8007ac8: 08006c45 .word 0x08006c45
8007acc: 080069e5 .word 0x080069e5
08007ad0 <I2C_Disable_IRQ>:
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
* @retval None
*/
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
8007ad0: b480 push {r7}
8007ad2: b085 sub sp, #20
8007ad4: af00 add r7, sp, #0
8007ad6: 6078 str r0, [r7, #4]
8007ad8: 460b mov r3, r1
8007ada: 807b strh r3, [r7, #2]
uint32_t tmpisr = 0U;
8007adc: 2300 movs r3, #0
8007ade: 60fb str r3, [r7, #12]
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
8007ae0: 887b ldrh r3, [r7, #2]
8007ae2: f003 0301 and.w r3, r3, #1
8007ae6: 2b00 cmp r3, #0
8007ae8: d00f beq.n 8007b0a <I2C_Disable_IRQ+0x3a>
{
/* Disable TC and TXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
8007aea: 68fb ldr r3, [r7, #12]
8007aec: f043 0342 orr.w r3, r3, #66 @ 0x42
8007af0: 60fb str r3, [r7, #12]
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
8007af2: 687b ldr r3, [r7, #4]
8007af4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007af8: b2db uxtb r3, r3
8007afa: f003 0328 and.w r3, r3, #40 @ 0x28
8007afe: 2b28 cmp r3, #40 @ 0x28
8007b00: d003 beq.n 8007b0a <I2C_Disable_IRQ+0x3a>
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
8007b02: 68fb ldr r3, [r7, #12]
8007b04: f043 03b0 orr.w r3, r3, #176 @ 0xb0
8007b08: 60fb str r3, [r7, #12]
}
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
8007b0a: 887b ldrh r3, [r7, #2]
8007b0c: f003 0302 and.w r3, r3, #2
8007b10: 2b00 cmp r3, #0
8007b12: d00f beq.n 8007b34 <I2C_Disable_IRQ+0x64>
{
/* Disable TC and RXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
8007b14: 68fb ldr r3, [r7, #12]
8007b16: f043 0344 orr.w r3, r3, #68 @ 0x44
8007b1a: 60fb str r3, [r7, #12]
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
8007b1c: 687b ldr r3, [r7, #4]
8007b1e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007b22: b2db uxtb r3, r3
8007b24: f003 0328 and.w r3, r3, #40 @ 0x28
8007b28: 2b28 cmp r3, #40 @ 0x28
8007b2a: d003 beq.n 8007b34 <I2C_Disable_IRQ+0x64>
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
8007b2c: 68fb ldr r3, [r7, #12]
8007b2e: f043 03b0 orr.w r3, r3, #176 @ 0xb0
8007b32: 60fb str r3, [r7, #12]
}
}
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
8007b34: f9b7 3002 ldrsh.w r3, [r7, #2]
8007b38: 2b00 cmp r3, #0
8007b3a: da03 bge.n 8007b44 <I2C_Disable_IRQ+0x74>
{
/* Disable ADDR, NACK and STOP interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
8007b3c: 68fb ldr r3, [r7, #12]
8007b3e: f043 03b8 orr.w r3, r3, #184 @ 0xb8
8007b42: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
8007b44: 887b ldrh r3, [r7, #2]
8007b46: 2b10 cmp r3, #16
8007b48: d103 bne.n 8007b52 <I2C_Disable_IRQ+0x82>
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
8007b4a: 68fb ldr r3, [r7, #12]
8007b4c: f043 0390 orr.w r3, r3, #144 @ 0x90
8007b50: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
8007b52: 887b ldrh r3, [r7, #2]
8007b54: 2b20 cmp r3, #32
8007b56: d103 bne.n 8007b60 <I2C_Disable_IRQ+0x90>
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
8007b58: 68fb ldr r3, [r7, #12]
8007b5a: f043 0320 orr.w r3, r3, #32
8007b5e: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_RELOAD_IT)
8007b60: 887b ldrh r3, [r7, #2]
8007b62: 2b40 cmp r3, #64 @ 0x40
8007b64: d103 bne.n 8007b6e <I2C_Disable_IRQ+0x9e>
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
8007b66: 68fb ldr r3, [r7, #12]
8007b68: f043 0340 orr.w r3, r3, #64 @ 0x40
8007b6c: 60fb str r3, [r7, #12]
}
/* Disable interrupts only at the end */
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_I2C_DISABLE_IT(hi2c, tmpisr);
8007b6e: 687b ldr r3, [r7, #4]
8007b70: 681b ldr r3, [r3, #0]
8007b72: 6819 ldr r1, [r3, #0]
8007b74: 68fb ldr r3, [r7, #12]
8007b76: 43da mvns r2, r3
8007b78: 687b ldr r3, [r7, #4]
8007b7a: 681b ldr r3, [r3, #0]
8007b7c: 400a ands r2, r1
8007b7e: 601a str r2, [r3, #0]
}
8007b80: bf00 nop
8007b82: 3714 adds r7, #20
8007b84: 46bd mov sp, r7
8007b86: f85d 7b04 ldr.w r7, [sp], #4
8007b8a: 4770 bx lr
08007b8c <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
8007b8c: b480 push {r7}
8007b8e: b083 sub sp, #12
8007b90: af00 add r7, sp, #0
8007b92: 6078 str r0, [r7, #4]
8007b94: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8007b96: 687b ldr r3, [r7, #4]
8007b98: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007b9c: b2db uxtb r3, r3
8007b9e: 2b20 cmp r3, #32
8007ba0: d138 bne.n 8007c14 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8007ba2: 687b ldr r3, [r7, #4]
8007ba4: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8007ba8: 2b01 cmp r3, #1
8007baa: d101 bne.n 8007bb0 <HAL_I2CEx_ConfigAnalogFilter+0x24>
8007bac: 2302 movs r3, #2
8007bae: e032 b.n 8007c16 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
8007bb0: 687b ldr r3, [r7, #4]
8007bb2: 2201 movs r2, #1
8007bb4: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8007bb8: 687b ldr r3, [r7, #4]
8007bba: 2224 movs r2, #36 @ 0x24
8007bbc: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8007bc0: 687b ldr r3, [r7, #4]
8007bc2: 681b ldr r3, [r3, #0]
8007bc4: 681a ldr r2, [r3, #0]
8007bc6: 687b ldr r3, [r7, #4]
8007bc8: 681b ldr r3, [r3, #0]
8007bca: f022 0201 bic.w r2, r2, #1
8007bce: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8007bd0: 687b ldr r3, [r7, #4]
8007bd2: 681b ldr r3, [r3, #0]
8007bd4: 681a ldr r2, [r3, #0]
8007bd6: 687b ldr r3, [r7, #4]
8007bd8: 681b ldr r3, [r3, #0]
8007bda: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8007bde: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
8007be0: 687b ldr r3, [r7, #4]
8007be2: 681b ldr r3, [r3, #0]
8007be4: 6819 ldr r1, [r3, #0]
8007be6: 687b ldr r3, [r7, #4]
8007be8: 681b ldr r3, [r3, #0]
8007bea: 683a ldr r2, [r7, #0]
8007bec: 430a orrs r2, r1
8007bee: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8007bf0: 687b ldr r3, [r7, #4]
8007bf2: 681b ldr r3, [r3, #0]
8007bf4: 681a ldr r2, [r3, #0]
8007bf6: 687b ldr r3, [r7, #4]
8007bf8: 681b ldr r3, [r3, #0]
8007bfa: f042 0201 orr.w r2, r2, #1
8007bfe: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8007c00: 687b ldr r3, [r7, #4]
8007c02: 2220 movs r2, #32
8007c04: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007c08: 687b ldr r3, [r7, #4]
8007c0a: 2200 movs r2, #0
8007c0c: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8007c10: 2300 movs r3, #0
8007c12: e000 b.n 8007c16 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8007c14: 2302 movs r3, #2
}
}
8007c16: 4618 mov r0, r3
8007c18: 370c adds r7, #12
8007c1a: 46bd mov sp, r7
8007c1c: f85d 7b04 ldr.w r7, [sp], #4
8007c20: 4770 bx lr
08007c22 <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
8007c22: b480 push {r7}
8007c24: b085 sub sp, #20
8007c26: af00 add r7, sp, #0
8007c28: 6078 str r0, [r7, #4]
8007c2a: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8007c2c: 687b ldr r3, [r7, #4]
8007c2e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007c32: b2db uxtb r3, r3
8007c34: 2b20 cmp r3, #32
8007c36: d139 bne.n 8007cac <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8007c38: 687b ldr r3, [r7, #4]
8007c3a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8007c3e: 2b01 cmp r3, #1
8007c40: d101 bne.n 8007c46 <HAL_I2CEx_ConfigDigitalFilter+0x24>
8007c42: 2302 movs r3, #2
8007c44: e033 b.n 8007cae <HAL_I2CEx_ConfigDigitalFilter+0x8c>
8007c46: 687b ldr r3, [r7, #4]
8007c48: 2201 movs r2, #1
8007c4a: f883 2040 strb.w r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8007c4e: 687b ldr r3, [r7, #4]
8007c50: 2224 movs r2, #36 @ 0x24
8007c52: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8007c56: 687b ldr r3, [r7, #4]
8007c58: 681b ldr r3, [r3, #0]
8007c5a: 681a ldr r2, [r3, #0]
8007c5c: 687b ldr r3, [r7, #4]
8007c5e: 681b ldr r3, [r3, #0]
8007c60: f022 0201 bic.w r2, r2, #1
8007c64: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
8007c66: 687b ldr r3, [r7, #4]
8007c68: 681b ldr r3, [r3, #0]
8007c6a: 681b ldr r3, [r3, #0]
8007c6c: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
8007c6e: 68fb ldr r3, [r7, #12]
8007c70: f423 6370 bic.w r3, r3, #3840 @ 0xf00
8007c74: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
8007c76: 683b ldr r3, [r7, #0]
8007c78: 021b lsls r3, r3, #8
8007c7a: 68fa ldr r2, [r7, #12]
8007c7c: 4313 orrs r3, r2
8007c7e: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
8007c80: 687b ldr r3, [r7, #4]
8007c82: 681b ldr r3, [r3, #0]
8007c84: 68fa ldr r2, [r7, #12]
8007c86: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8007c88: 687b ldr r3, [r7, #4]
8007c8a: 681b ldr r3, [r3, #0]
8007c8c: 681a ldr r2, [r3, #0]
8007c8e: 687b ldr r3, [r7, #4]
8007c90: 681b ldr r3, [r3, #0]
8007c92: f042 0201 orr.w r2, r2, #1
8007c96: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8007c98: 687b ldr r3, [r7, #4]
8007c9a: 2220 movs r2, #32
8007c9c: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007ca0: 687b ldr r3, [r7, #4]
8007ca2: 2200 movs r2, #0
8007ca4: f883 2040 strb.w r2, [r3, #64] @ 0x40
return HAL_OK;
8007ca8: 2300 movs r3, #0
8007caa: e000 b.n 8007cae <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
8007cac: 2302 movs r3, #2
}
}
8007cae: 4618 mov r0, r3
8007cb0: 3714 adds r7, #20
8007cb2: 46bd mov sp, r7
8007cb4: f85d 7b04 ldr.w r7, [sp], #4
8007cb8: 4770 bx lr
...
08007cbc <HAL_IPCC_Init>:
* @brief Initialize the IPCC peripheral.
* @param hipcc IPCC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc)
{
8007cbc: b580 push {r7, lr}
8007cbe: b084 sub sp, #16
8007cc0: af00 add r7, sp, #0
8007cc2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef err = HAL_OK;
8007cc4: 2300 movs r3, #0
8007cc6: 73fb strb r3, [r7, #15]
/* Check the IPCC handle allocation */
if (hipcc != NULL)
8007cc8: 687b ldr r3, [r7, #4]
8007cca: 2b00 cmp r3, #0
8007ccc: d01e beq.n 8007d0c <HAL_IPCC_Init+0x50>
{
/* Check the parameters */
assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
8007cce: 4b13 ldr r3, [pc, #76] @ (8007d1c <HAL_IPCC_Init+0x60>)
8007cd0: 60bb str r3, [r7, #8]
if (hipcc->State == HAL_IPCC_STATE_RESET)
8007cd2: 687b ldr r3, [r7, #4]
8007cd4: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8007cd8: b2db uxtb r3, r3
8007cda: 2b00 cmp r3, #0
8007cdc: d102 bne.n 8007ce4 <HAL_IPCC_Init+0x28>
{
/* Init the low level hardware : CLOCK, NVIC */
HAL_IPCC_MspInit(hipcc);
8007cde: 6878 ldr r0, [r7, #4]
8007ce0: f7fc ff66 bl 8004bb0 <HAL_IPCC_MspInit>
}
/* Reset all registers of the current cpu to default state */
IPCC_Reset_Register(currentInstance);
8007ce4: 68b8 ldr r0, [r7, #8]
8007ce6: f000 f85b bl 8007da0 <IPCC_Reset_Register>
/* Activate the interrupts */
currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE);
8007cea: 68bb ldr r3, [r7, #8]
8007cec: 681b ldr r3, [r3, #0]
8007cee: f043 1201 orr.w r2, r3, #65537 @ 0x10001
8007cf2: 68bb ldr r3, [r7, #8]
8007cf4: 601a str r2, [r3, #0]
/* Clear callback pointers */
IPCC_SetDefaultCallbacks(hipcc);
8007cf6: 6878 ldr r0, [r7, #4]
8007cf8: f000 f82c bl 8007d54 <IPCC_SetDefaultCallbacks>
/* Reset all callback notification request */
hipcc->callbackRequest = 0;
8007cfc: 687b ldr r3, [r7, #4]
8007cfe: 2200 movs r2, #0
8007d00: 635a str r2, [r3, #52] @ 0x34
hipcc->State = HAL_IPCC_STATE_READY;
8007d02: 687b ldr r3, [r7, #4]
8007d04: 2201 movs r2, #1
8007d06: f883 2038 strb.w r2, [r3, #56] @ 0x38
8007d0a: e001 b.n 8007d10 <HAL_IPCC_Init+0x54>
}
else
{
err = HAL_ERROR;
8007d0c: 2301 movs r3, #1
8007d0e: 73fb strb r3, [r7, #15]
}
return err;
8007d10: 7bfb ldrb r3, [r7, #15]
}
8007d12: 4618 mov r0, r3
8007d14: 3710 adds r7, #16
8007d16: 46bd mov sp, r7
8007d18: bd80 pop {r7, pc}
8007d1a: bf00 nop
8007d1c: 58000c00 .word 0x58000c00
08007d20 <HAL_IPCC_RxCallback>:
* @arg IPCC_CHANNEL_5: IPCC Channel 5
* @arg IPCC_CHANNEL_6: IPCC Channel 6
* @param ChannelDir Channel direction
*/
__weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
{
8007d20: b480 push {r7}
8007d22: b085 sub sp, #20
8007d24: af00 add r7, sp, #0
8007d26: 60f8 str r0, [r7, #12]
8007d28: 60b9 str r1, [r7, #8]
8007d2a: 4613 mov r3, r2
8007d2c: 71fb strb r3, [r7, #7]
UNUSED(ChannelDir);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IPCC_RxCallback can be implemented in the user file
*/
}
8007d2e: bf00 nop
8007d30: 3714 adds r7, #20
8007d32: 46bd mov sp, r7
8007d34: f85d 7b04 ldr.w r7, [sp], #4
8007d38: 4770 bx lr
08007d3a <HAL_IPCC_TxCallback>:
* @arg IPCC_CHANNEL_5: IPCC Channel 5
* @arg IPCC_CHANNEL_6: IPCC Channel 6
* @param ChannelDir Channel direction
*/
__weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
{
8007d3a: b480 push {r7}
8007d3c: b085 sub sp, #20
8007d3e: af00 add r7, sp, #0
8007d40: 60f8 str r0, [r7, #12]
8007d42: 60b9 str r1, [r7, #8]
8007d44: 4613 mov r3, r2
8007d46: 71fb strb r3, [r7, #7]
UNUSED(ChannelDir);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IPCC_TxCallback can be implemented in the user file
*/
}
8007d48: bf00 nop
8007d4a: 3714 adds r7, #20
8007d4c: 46bd mov sp, r7
8007d4e: f85d 7b04 ldr.w r7, [sp], #4
8007d52: 4770 bx lr
08007d54 <IPCC_SetDefaultCallbacks>:
/**
* @brief Reset all callbacks of the handle to NULL.
* @param hipcc IPCC handle
*/
void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc)
{
8007d54: b480 push {r7}
8007d56: b085 sub sp, #20
8007d58: af00 add r7, sp, #0
8007d5a: 6078 str r0, [r7, #4]
uint32_t i;
/* Set all callbacks to default */
for (i = 0; i < IPCC_CHANNEL_NUMBER; i++)
8007d5c: 2300 movs r3, #0
8007d5e: 60fb str r3, [r7, #12]
8007d60: e00f b.n 8007d82 <IPCC_SetDefaultCallbacks+0x2e>
{
hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback;
8007d62: 687a ldr r2, [r7, #4]
8007d64: 68fb ldr r3, [r7, #12]
8007d66: 009b lsls r3, r3, #2
8007d68: 4413 add r3, r2
8007d6a: 4a0b ldr r2, [pc, #44] @ (8007d98 <IPCC_SetDefaultCallbacks+0x44>)
8007d6c: 605a str r2, [r3, #4]
hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback;
8007d6e: 687a ldr r2, [r7, #4]
8007d70: 68fb ldr r3, [r7, #12]
8007d72: 3306 adds r3, #6
8007d74: 009b lsls r3, r3, #2
8007d76: 4413 add r3, r2
8007d78: 4a08 ldr r2, [pc, #32] @ (8007d9c <IPCC_SetDefaultCallbacks+0x48>)
8007d7a: 605a str r2, [r3, #4]
for (i = 0; i < IPCC_CHANNEL_NUMBER; i++)
8007d7c: 68fb ldr r3, [r7, #12]
8007d7e: 3301 adds r3, #1
8007d80: 60fb str r3, [r7, #12]
8007d82: 68fb ldr r3, [r7, #12]
8007d84: 2b05 cmp r3, #5
8007d86: d9ec bls.n 8007d62 <IPCC_SetDefaultCallbacks+0xe>
}
}
8007d88: bf00 nop
8007d8a: bf00 nop
8007d8c: 3714 adds r7, #20
8007d8e: 46bd mov sp, r7
8007d90: f85d 7b04 ldr.w r7, [sp], #4
8007d94: 4770 bx lr
8007d96: bf00 nop
8007d98: 08007d21 .word 0x08007d21
8007d9c: 08007d3b .word 0x08007d3b
08007da0 <IPCC_Reset_Register>:
/**
* @brief Reset IPCC register to default value for the concerned instance.
* @param Instance pointer to register
*/
void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance)
{
8007da0: b480 push {r7}
8007da2: b083 sub sp, #12
8007da4: af00 add r7, sp, #0
8007da6: 6078 str r0, [r7, #4]
/* Disable RX and TX interrupts */
Instance->CR = 0x00000000U;
8007da8: 687b ldr r3, [r7, #4]
8007daa: 2200 movs r2, #0
8007dac: 601a str r2, [r3, #0]
/* Mask RX and TX interrupts */
Instance->MR = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF);
8007dae: 687b ldr r3, [r7, #4]
8007db0: f04f 123f mov.w r2, #4128831 @ 0x3f003f
8007db4: 605a str r2, [r3, #4]
/* Clear RX status */
Instance->SCR = IPCC_ALL_RX_BUF;
8007db6: 687b ldr r3, [r7, #4]
8007db8: 223f movs r2, #63 @ 0x3f
8007dba: 609a str r2, [r3, #8]
}
8007dbc: bf00 nop
8007dbe: 370c adds r7, #12
8007dc0: 46bd mov sp, r7
8007dc2: f85d 7b04 ldr.w r7, [sp], #4
8007dc6: 4770 bx lr
08007dc8 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
8007dc8: b580 push {r7, lr}
8007dca: b084 sub sp, #16
8007dcc: af00 add r7, sp, #0
8007dce: 6078 str r0, [r7, #4]
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
8007dd0: 687b ldr r3, [r7, #4]
8007dd2: 2b00 cmp r3, #0
8007dd4: d101 bne.n 8007dda <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8007dd6: 2301 movs r3, #1
8007dd8: e0c0 b.n 8007f5c <HAL_PCD_Init+0x194>
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
8007dda: 687b ldr r3, [r7, #4]
8007ddc: f893 3291 ldrb.w r3, [r3, #657] @ 0x291
8007de0: b2db uxtb r3, r3
8007de2: 2b00 cmp r3, #0
8007de4: d106 bne.n 8007df4 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8007de6: 687b ldr r3, [r7, #4]
8007de8: 2200 movs r2, #0
8007dea: f883 2290 strb.w r2, [r3, #656] @ 0x290
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
8007dee: 6878 ldr r0, [r7, #4]
8007df0: f00f f9f2 bl 80171d8 <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8007df4: 687b ldr r3, [r7, #4]
8007df6: 2203 movs r2, #3
8007df8: f883 2291 strb.w r2, [r3, #657] @ 0x291
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
8007dfc: 687b ldr r3, [r7, #4]
8007dfe: 681b ldr r3, [r3, #0]
8007e00: 4618 mov r0, r3
8007e02: f005 fc5c bl 800d6be <USB_DisableGlobalInt>
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8007e06: 2300 movs r3, #0
8007e08: 73fb strb r3, [r7, #15]
8007e0a: e03e b.n 8007e8a <HAL_PCD_Init+0xc2>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
8007e0c: 7bfa ldrb r2, [r7, #15]
8007e0e: 6879 ldr r1, [r7, #4]
8007e10: 4613 mov r3, r2
8007e12: 009b lsls r3, r3, #2
8007e14: 4413 add r3, r2
8007e16: 00db lsls r3, r3, #3
8007e18: 440b add r3, r1
8007e1a: 3311 adds r3, #17
8007e1c: 2201 movs r2, #1
8007e1e: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
8007e20: 7bfa ldrb r2, [r7, #15]
8007e22: 6879 ldr r1, [r7, #4]
8007e24: 4613 mov r3, r2
8007e26: 009b lsls r3, r3, #2
8007e28: 4413 add r3, r2
8007e2a: 00db lsls r3, r3, #3
8007e2c: 440b add r3, r1
8007e2e: 3310 adds r3, #16
8007e30: 7bfa ldrb r2, [r7, #15]
8007e32: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8007e34: 7bfa ldrb r2, [r7, #15]
8007e36: 6879 ldr r1, [r7, #4]
8007e38: 4613 mov r3, r2
8007e3a: 009b lsls r3, r3, #2
8007e3c: 4413 add r3, r2
8007e3e: 00db lsls r3, r3, #3
8007e40: 440b add r3, r1
8007e42: 3313 adds r3, #19
8007e44: 2200 movs r2, #0
8007e46: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
8007e48: 7bfa ldrb r2, [r7, #15]
8007e4a: 6879 ldr r1, [r7, #4]
8007e4c: 4613 mov r3, r2
8007e4e: 009b lsls r3, r3, #2
8007e50: 4413 add r3, r2
8007e52: 00db lsls r3, r3, #3
8007e54: 440b add r3, r1
8007e56: 3320 adds r3, #32
8007e58: 2200 movs r2, #0
8007e5a: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
8007e5c: 7bfa ldrb r2, [r7, #15]
8007e5e: 6879 ldr r1, [r7, #4]
8007e60: 4613 mov r3, r2
8007e62: 009b lsls r3, r3, #2
8007e64: 4413 add r3, r2
8007e66: 00db lsls r3, r3, #3
8007e68: 440b add r3, r1
8007e6a: 3324 adds r3, #36 @ 0x24
8007e6c: 2200 movs r2, #0
8007e6e: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8007e70: 7bfb ldrb r3, [r7, #15]
8007e72: 6879 ldr r1, [r7, #4]
8007e74: 1c5a adds r2, r3, #1
8007e76: 4613 mov r3, r2
8007e78: 009b lsls r3, r3, #2
8007e7a: 4413 add r3, r2
8007e7c: 00db lsls r3, r3, #3
8007e7e: 440b add r3, r1
8007e80: 2200 movs r2, #0
8007e82: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8007e84: 7bfb ldrb r3, [r7, #15]
8007e86: 3301 adds r3, #1
8007e88: 73fb strb r3, [r7, #15]
8007e8a: 687b ldr r3, [r7, #4]
8007e8c: 791b ldrb r3, [r3, #4]
8007e8e: 7bfa ldrb r2, [r7, #15]
8007e90: 429a cmp r2, r3
8007e92: d3bb bcc.n 8007e0c <HAL_PCD_Init+0x44>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8007e94: 2300 movs r3, #0
8007e96: 73fb strb r3, [r7, #15]
8007e98: e044 b.n 8007f24 <HAL_PCD_Init+0x15c>
{
hpcd->OUT_ep[i].is_in = 0U;
8007e9a: 7bfa ldrb r2, [r7, #15]
8007e9c: 6879 ldr r1, [r7, #4]
8007e9e: 4613 mov r3, r2
8007ea0: 009b lsls r3, r3, #2
8007ea2: 4413 add r3, r2
8007ea4: 00db lsls r3, r3, #3
8007ea6: 440b add r3, r1
8007ea8: f203 1351 addw r3, r3, #337 @ 0x151
8007eac: 2200 movs r2, #0
8007eae: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8007eb0: 7bfa ldrb r2, [r7, #15]
8007eb2: 6879 ldr r1, [r7, #4]
8007eb4: 4613 mov r3, r2
8007eb6: 009b lsls r3, r3, #2
8007eb8: 4413 add r3, r2
8007eba: 00db lsls r3, r3, #3
8007ebc: 440b add r3, r1
8007ebe: f503 73a8 add.w r3, r3, #336 @ 0x150
8007ec2: 7bfa ldrb r2, [r7, #15]
8007ec4: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8007ec6: 7bfa ldrb r2, [r7, #15]
8007ec8: 6879 ldr r1, [r7, #4]
8007eca: 4613 mov r3, r2
8007ecc: 009b lsls r3, r3, #2
8007ece: 4413 add r3, r2
8007ed0: 00db lsls r3, r3, #3
8007ed2: 440b add r3, r1
8007ed4: f203 1353 addw r3, r3, #339 @ 0x153
8007ed8: 2200 movs r2, #0
8007eda: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
8007edc: 7bfa ldrb r2, [r7, #15]
8007ede: 6879 ldr r1, [r7, #4]
8007ee0: 4613 mov r3, r2
8007ee2: 009b lsls r3, r3, #2
8007ee4: 4413 add r3, r2
8007ee6: 00db lsls r3, r3, #3
8007ee8: 440b add r3, r1
8007eea: f503 73b0 add.w r3, r3, #352 @ 0x160
8007eee: 2200 movs r2, #0
8007ef0: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8007ef2: 7bfa ldrb r2, [r7, #15]
8007ef4: 6879 ldr r1, [r7, #4]
8007ef6: 4613 mov r3, r2
8007ef8: 009b lsls r3, r3, #2
8007efa: 4413 add r3, r2
8007efc: 00db lsls r3, r3, #3
8007efe: 440b add r3, r1
8007f00: f503 73b2 add.w r3, r3, #356 @ 0x164
8007f04: 2200 movs r2, #0
8007f06: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8007f08: 7bfa ldrb r2, [r7, #15]
8007f0a: 6879 ldr r1, [r7, #4]
8007f0c: 4613 mov r3, r2
8007f0e: 009b lsls r3, r3, #2
8007f10: 4413 add r3, r2
8007f12: 00db lsls r3, r3, #3
8007f14: 440b add r3, r1
8007f16: f503 73b4 add.w r3, r3, #360 @ 0x168
8007f1a: 2200 movs r2, #0
8007f1c: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8007f1e: 7bfb ldrb r3, [r7, #15]
8007f20: 3301 adds r3, #1
8007f22: 73fb strb r3, [r7, #15]
8007f24: 687b ldr r3, [r7, #4]
8007f26: 791b ldrb r3, [r3, #4]
8007f28: 7bfa ldrb r2, [r7, #15]
8007f2a: 429a cmp r2, r3
8007f2c: d3b5 bcc.n 8007e9a <HAL_PCD_Init+0xd2>
}
/* Init Device */
(void)USB_DevInit(hpcd->Instance, hpcd->Init);
8007f2e: 687b ldr r3, [r7, #4]
8007f30: 6818 ldr r0, [r3, #0]
8007f32: 687b ldr r3, [r7, #4]
8007f34: 3304 adds r3, #4
8007f36: e893 0006 ldmia.w r3, {r1, r2}
8007f3a: f005 fbdb bl 800d6f4 <USB_DevInit>
hpcd->USB_Address = 0U;
8007f3e: 687b ldr r3, [r7, #4]
8007f40: 2200 movs r2, #0
8007f42: 731a strb r2, [r3, #12]
hpcd->State = HAL_PCD_STATE_READY;
8007f44: 687b ldr r3, [r7, #4]
8007f46: 2201 movs r2, #1
8007f48: f883 2291 strb.w r2, [r3, #657] @ 0x291
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
8007f4c: 687b ldr r3, [r7, #4]
8007f4e: 7a9b ldrb r3, [r3, #10]
8007f50: 2b01 cmp r3, #1
8007f52: d102 bne.n 8007f5a <HAL_PCD_Init+0x192>
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
8007f54: 6878 ldr r0, [r7, #4]
8007f56: f001 fc4f bl 80097f8 <HAL_PCDEx_ActivateLPM>
}
return HAL_OK;
8007f5a: 2300 movs r3, #0
}
8007f5c: 4618 mov r0, r3
8007f5e: 3710 adds r7, #16
8007f60: 46bd mov sp, r7
8007f62: bd80 pop {r7, pc}
08007f64 <HAL_PCD_Start>:
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
8007f64: b580 push {r7, lr}
8007f66: b082 sub sp, #8
8007f68: af00 add r7, sp, #0
8007f6a: 6078 str r0, [r7, #4]
__HAL_LOCK(hpcd);
8007f6c: 687b ldr r3, [r7, #4]
8007f6e: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8007f72: 2b01 cmp r3, #1
8007f74: d101 bne.n 8007f7a <HAL_PCD_Start+0x16>
8007f76: 2302 movs r3, #2
8007f78: e012 b.n 8007fa0 <HAL_PCD_Start+0x3c>
8007f7a: 687b ldr r3, [r7, #4]
8007f7c: 2201 movs r2, #1
8007f7e: f883 2290 strb.w r2, [r3, #656] @ 0x290
__HAL_PCD_ENABLE(hpcd);
8007f82: 687b ldr r3, [r7, #4]
8007f84: 681b ldr r3, [r3, #0]
8007f86: 4618 mov r0, r3
8007f88: f005 fb82 bl 800d690 <USB_EnableGlobalInt>
(void)USB_DevConnect(hpcd->Instance);
8007f8c: 687b ldr r3, [r7, #4]
8007f8e: 681b ldr r3, [r3, #0]
8007f90: 4618 mov r0, r3
8007f92: f007 f95f bl 800f254 <USB_DevConnect>
__HAL_UNLOCK(hpcd);
8007f96: 687b ldr r3, [r7, #4]
8007f98: 2200 movs r2, #0
8007f9a: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8007f9e: 2300 movs r3, #0
}
8007fa0: 4618 mov r0, r3
8007fa2: 3708 adds r7, #8
8007fa4: 46bd mov sp, r7
8007fa6: bd80 pop {r7, pc}
08007fa8 <HAL_PCD_IRQHandler>:
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
8007fa8: b580 push {r7, lr}
8007faa: b084 sub sp, #16
8007fac: af00 add r7, sp, #0
8007fae: 6078 str r0, [r7, #4]
uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
8007fb0: 687b ldr r3, [r7, #4]
8007fb2: 681b ldr r3, [r3, #0]
8007fb4: 4618 mov r0, r3
8007fb6: f007 f964 bl 800f282 <USB_ReadInterrupts>
8007fba: 60f8 str r0, [r7, #12]
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
8007fbc: 68fb ldr r3, [r7, #12]
8007fbe: f403 4300 and.w r3, r3, #32768 @ 0x8000
8007fc2: 2b00 cmp r3, #0
8007fc4: d003 beq.n 8007fce <HAL_PCD_IRQHandler+0x26>
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
8007fc6: 6878 ldr r0, [r7, #4]
8007fc8: f000 fb06 bl 80085d8 <PCD_EP_ISR_Handler>
return;
8007fcc: e110 b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
}
if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
8007fce: 68fb ldr r3, [r7, #12]
8007fd0: f403 6380 and.w r3, r3, #1024 @ 0x400
8007fd4: 2b00 cmp r3, #0
8007fd6: d013 beq.n 8008000 <HAL_PCD_IRQHandler+0x58>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
8007fd8: 687b ldr r3, [r7, #4]
8007fda: 681b ldr r3, [r3, #0]
8007fdc: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8007fe0: b29a uxth r2, r3
8007fe2: 687b ldr r3, [r7, #4]
8007fe4: 681b ldr r3, [r3, #0]
8007fe6: f422 6280 bic.w r2, r2, #1024 @ 0x400
8007fea: b292 uxth r2, r2
8007fec: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
8007ff0: 6878 ldr r0, [r7, #4]
8007ff2: f00f f9a4 bl 801733e <HAL_PCD_ResetCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
8007ff6: 2100 movs r1, #0
8007ff8: 6878 ldr r0, [r7, #4]
8007ffa: f000 f8fc bl 80081f6 <HAL_PCD_SetAddress>
return;
8007ffe: e0f7 b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
}
if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
8008000: 68fb ldr r3, [r7, #12]
8008002: f403 4380 and.w r3, r3, #16384 @ 0x4000
8008006: 2b00 cmp r3, #0
8008008: d00c beq.n 8008024 <HAL_PCD_IRQHandler+0x7c>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
800800a: 687b ldr r3, [r7, #4]
800800c: 681b ldr r3, [r3, #0]
800800e: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8008012: b29a uxth r2, r3
8008014: 687b ldr r3, [r7, #4]
8008016: 681b ldr r3, [r3, #0]
8008018: f422 4280 bic.w r2, r2, #16384 @ 0x4000
800801c: b292 uxth r2, r2
800801e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8008022: e0e5 b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
}
if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
8008024: 68fb ldr r3, [r7, #12]
8008026: f403 5300 and.w r3, r3, #8192 @ 0x2000
800802a: 2b00 cmp r3, #0
800802c: d00c beq.n 8008048 <HAL_PCD_IRQHandler+0xa0>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
800802e: 687b ldr r3, [r7, #4]
8008030: 681b ldr r3, [r3, #0]
8008032: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8008036: b29a uxth r2, r3
8008038: 687b ldr r3, [r7, #4]
800803a: 681b ldr r3, [r3, #0]
800803c: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8008040: b292 uxth r2, r2
8008042: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
8008046: e0d3 b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
}
if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
8008048: 68fb ldr r3, [r7, #12]
800804a: f403 5380 and.w r3, r3, #4096 @ 0x1000
800804e: 2b00 cmp r3, #0
8008050: d034 beq.n 80080bc <HAL_PCD_IRQHandler+0x114>
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
8008052: 687b ldr r3, [r7, #4]
8008054: 681b ldr r3, [r3, #0]
8008056: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
800805a: b29a uxth r2, r3
800805c: 687b ldr r3, [r7, #4]
800805e: 681b ldr r3, [r3, #0]
8008060: f022 0204 bic.w r2, r2, #4
8008064: b292 uxth r2, r2
8008066: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
800806a: 687b ldr r3, [r7, #4]
800806c: 681b ldr r3, [r3, #0]
800806e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8008072: b29a uxth r2, r3
8008074: 687b ldr r3, [r7, #4]
8008076: 681b ldr r3, [r3, #0]
8008078: f022 0208 bic.w r2, r2, #8
800807c: b292 uxth r2, r2
800807e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
if (hpcd->LPM_State == LPM_L1)
8008082: 687b ldr r3, [r7, #4]
8008084: f893 32c8 ldrb.w r3, [r3, #712] @ 0x2c8
8008088: 2b01 cmp r3, #1
800808a: d107 bne.n 800809c <HAL_PCD_IRQHandler+0xf4>
{
hpcd->LPM_State = LPM_L0;
800808c: 687b ldr r3, [r7, #4]
800808e: 2200 movs r2, #0
8008090: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
8008094: 2100 movs r1, #0
8008096: 6878 ldr r0, [r7, #4]
8008098: f00f fb46 bl 8017728 <HAL_PCDEx_LPM_Callback>
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
800809c: 6878 ldr r0, [r7, #4]
800809e: f00f f987 bl 80173b0 <HAL_PCD_ResumeCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
80080a2: 687b ldr r3, [r7, #4]
80080a4: 681b ldr r3, [r3, #0]
80080a6: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80080aa: b29a uxth r2, r3
80080ac: 687b ldr r3, [r7, #4]
80080ae: 681b ldr r3, [r3, #0]
80080b0: f422 5280 bic.w r2, r2, #4096 @ 0x1000
80080b4: b292 uxth r2, r2
80080b6: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
80080ba: e099 b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
}
if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
80080bc: 68fb ldr r3, [r7, #12]
80080be: f403 6300 and.w r3, r3, #2048 @ 0x800
80080c2: 2b00 cmp r3, #0
80080c4: d027 beq.n 8008116 <HAL_PCD_IRQHandler+0x16e>
{
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
80080c6: 687b ldr r3, [r7, #4]
80080c8: 681b ldr r3, [r3, #0]
80080ca: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
80080ce: b29a uxth r2, r3
80080d0: 687b ldr r3, [r7, #4]
80080d2: 681b ldr r3, [r3, #0]
80080d4: f042 0208 orr.w r2, r2, #8
80080d8: b292 uxth r2, r2
80080da: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
80080de: 687b ldr r3, [r7, #4]
80080e0: 681b ldr r3, [r3, #0]
80080e2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80080e6: b29a uxth r2, r3
80080e8: 687b ldr r3, [r7, #4]
80080ea: 681b ldr r3, [r3, #0]
80080ec: f422 6200 bic.w r2, r2, #2048 @ 0x800
80080f0: b292 uxth r2, r2
80080f2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
80080f6: 687b ldr r3, [r7, #4]
80080f8: 681b ldr r3, [r3, #0]
80080fa: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
80080fe: b29a uxth r2, r3
8008100: 687b ldr r3, [r7, #4]
8008102: 681b ldr r3, [r3, #0]
8008104: f042 0204 orr.w r2, r2, #4
8008108: b292 uxth r2, r2
800810a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
800810e: 6878 ldr r0, [r7, #4]
8008110: f00f f934 bl 801737c <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
8008114: e06c b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
}
/* Handle LPM Interrupt */
if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ)
8008116: 68fb ldr r3, [r7, #12]
8008118: f003 0380 and.w r3, r3, #128 @ 0x80
800811c: 2b00 cmp r3, #0
800811e: d040 beq.n 80081a2 <HAL_PCD_IRQHandler+0x1fa>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
8008120: 687b ldr r3, [r7, #4]
8008122: 681b ldr r3, [r3, #0]
8008124: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8008128: b29a uxth r2, r3
800812a: 687b ldr r3, [r7, #4]
800812c: 681b ldr r3, [r3, #0]
800812e: f022 0280 bic.w r2, r2, #128 @ 0x80
8008132: b292 uxth r2, r2
8008134: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
if (hpcd->LPM_State == LPM_L0)
8008138: 687b ldr r3, [r7, #4]
800813a: f893 32c8 ldrb.w r3, [r3, #712] @ 0x2c8
800813e: 2b00 cmp r3, #0
8008140: d12b bne.n 800819a <HAL_PCD_IRQHandler+0x1f2>
{
/* Force suspend and low-power mode before going to L1 state*/
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
8008142: 687b ldr r3, [r7, #4]
8008144: 681b ldr r3, [r3, #0]
8008146: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
800814a: b29a uxth r2, r3
800814c: 687b ldr r3, [r7, #4]
800814e: 681b ldr r3, [r3, #0]
8008150: f042 0204 orr.w r2, r2, #4
8008154: b292 uxth r2, r2
8008156: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
800815a: 687b ldr r3, [r7, #4]
800815c: 681b ldr r3, [r3, #0]
800815e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
8008162: b29a uxth r2, r3
8008164: 687b ldr r3, [r7, #4]
8008166: 681b ldr r3, [r3, #0]
8008168: f042 0208 orr.w r2, r2, #8
800816c: b292 uxth r2, r2
800816e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
hpcd->LPM_State = LPM_L1;
8008172: 687b ldr r3, [r7, #4]
8008174: 2201 movs r2, #1
8008176: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8
hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
800817a: 687b ldr r3, [r7, #4]
800817c: 681b ldr r3, [r3, #0]
800817e: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54
8008182: b29b uxth r3, r3
8008184: 089b lsrs r3, r3, #2
8008186: f003 023c and.w r2, r3, #60 @ 0x3c
800818a: 687b ldr r3, [r7, #4]
800818c: f8c3 22cc str.w r2, [r3, #716] @ 0x2cc
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
8008190: 2101 movs r1, #1
8008192: 6878 ldr r0, [r7, #4]
8008194: f00f fac8 bl 8017728 <HAL_PCDEx_LPM_Callback>
#else
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
return;
8008198: e02a b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
HAL_PCD_SuspendCallback(hpcd);
800819a: 6878 ldr r0, [r7, #4]
800819c: f00f f8ee bl 801737c <HAL_PCD_SuspendCallback>
return;
80081a0: e026 b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
}
if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
80081a2: 68fb ldr r3, [r7, #12]
80081a4: f403 7300 and.w r3, r3, #512 @ 0x200
80081a8: 2b00 cmp r3, #0
80081aa: d00f beq.n 80081cc <HAL_PCD_IRQHandler+0x224>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
80081ac: 687b ldr r3, [r7, #4]
80081ae: 681b ldr r3, [r3, #0]
80081b0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80081b4: b29a uxth r2, r3
80081b6: 687b ldr r3, [r7, #4]
80081b8: 681b ldr r3, [r3, #0]
80081ba: f422 7200 bic.w r2, r2, #512 @ 0x200
80081be: b292 uxth r2, r2
80081c0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
80081c4: 6878 ldr r0, [r7, #4]
80081c6: f00f f8ac bl 8017322 <HAL_PCD_SOFCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
80081ca: e011 b.n 80081f0 <HAL_PCD_IRQHandler+0x248>
}
if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
80081cc: 68fb ldr r3, [r7, #12]
80081ce: f403 7380 and.w r3, r3, #256 @ 0x100
80081d2: 2b00 cmp r3, #0
80081d4: d00c beq.n 80081f0 <HAL_PCD_IRQHandler+0x248>
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
80081d6: 687b ldr r3, [r7, #4]
80081d8: 681b ldr r3, [r3, #0]
80081da: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80081de: b29a uxth r2, r3
80081e0: 687b ldr r3, [r7, #4]
80081e2: 681b ldr r3, [r3, #0]
80081e4: f422 7280 bic.w r2, r2, #256 @ 0x100
80081e8: b292 uxth r2, r2
80081ea: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
return;
80081ee: bf00 nop
}
}
80081f0: 3710 adds r7, #16
80081f2: 46bd mov sp, r7
80081f4: bd80 pop {r7, pc}
080081f6 <HAL_PCD_SetAddress>:
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
80081f6: b580 push {r7, lr}
80081f8: b082 sub sp, #8
80081fa: af00 add r7, sp, #0
80081fc: 6078 str r0, [r7, #4]
80081fe: 460b mov r3, r1
8008200: 70fb strb r3, [r7, #3]
__HAL_LOCK(hpcd);
8008202: 687b ldr r3, [r7, #4]
8008204: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8008208: 2b01 cmp r3, #1
800820a: d101 bne.n 8008210 <HAL_PCD_SetAddress+0x1a>
800820c: 2302 movs r3, #2
800820e: e012 b.n 8008236 <HAL_PCD_SetAddress+0x40>
8008210: 687b ldr r3, [r7, #4]
8008212: 2201 movs r2, #1
8008214: f883 2290 strb.w r2, [r3, #656] @ 0x290
hpcd->USB_Address = address;
8008218: 687b ldr r3, [r7, #4]
800821a: 78fa ldrb r2, [r7, #3]
800821c: 731a strb r2, [r3, #12]
(void)USB_SetDevAddress(hpcd->Instance, address);
800821e: 687b ldr r3, [r7, #4]
8008220: 681b ldr r3, [r3, #0]
8008222: 78fa ldrb r2, [r7, #3]
8008224: 4611 mov r1, r2
8008226: 4618 mov r0, r3
8008228: f007 f800 bl 800f22c <USB_SetDevAddress>
__HAL_UNLOCK(hpcd);
800822c: 687b ldr r3, [r7, #4]
800822e: 2200 movs r2, #0
8008230: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8008234: 2300 movs r3, #0
}
8008236: 4618 mov r0, r3
8008238: 3708 adds r7, #8
800823a: 46bd mov sp, r7
800823c: bd80 pop {r7, pc}
0800823e <HAL_PCD_EP_Open>:
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
800823e: b580 push {r7, lr}
8008240: b084 sub sp, #16
8008242: af00 add r7, sp, #0
8008244: 6078 str r0, [r7, #4]
8008246: 4608 mov r0, r1
8008248: 4611 mov r1, r2
800824a: 461a mov r2, r3
800824c: 4603 mov r3, r0
800824e: 70fb strb r3, [r7, #3]
8008250: 460b mov r3, r1
8008252: 803b strh r3, [r7, #0]
8008254: 4613 mov r3, r2
8008256: 70bb strb r3, [r7, #2]
HAL_StatusTypeDef ret = HAL_OK;
8008258: 2300 movs r3, #0
800825a: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
800825c: f997 3003 ldrsb.w r3, [r7, #3]
8008260: 2b00 cmp r3, #0
8008262: da0e bge.n 8008282 <HAL_PCD_EP_Open+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8008264: 78fb ldrb r3, [r7, #3]
8008266: f003 0207 and.w r2, r3, #7
800826a: 4613 mov r3, r2
800826c: 009b lsls r3, r3, #2
800826e: 4413 add r3, r2
8008270: 00db lsls r3, r3, #3
8008272: 3310 adds r3, #16
8008274: 687a ldr r2, [r7, #4]
8008276: 4413 add r3, r2
8008278: 60fb str r3, [r7, #12]
ep->is_in = 1U;
800827a: 68fb ldr r3, [r7, #12]
800827c: 2201 movs r2, #1
800827e: 705a strb r2, [r3, #1]
8008280: e00e b.n 80082a0 <HAL_PCD_EP_Open+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8008282: 78fb ldrb r3, [r7, #3]
8008284: f003 0207 and.w r2, r3, #7
8008288: 4613 mov r3, r2
800828a: 009b lsls r3, r3, #2
800828c: 4413 add r3, r2
800828e: 00db lsls r3, r3, #3
8008290: f503 73a8 add.w r3, r3, #336 @ 0x150
8008294: 687a ldr r2, [r7, #4]
8008296: 4413 add r3, r2
8008298: 60fb str r3, [r7, #12]
ep->is_in = 0U;
800829a: 68fb ldr r3, [r7, #12]
800829c: 2200 movs r2, #0
800829e: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
80082a0: 78fb ldrb r3, [r7, #3]
80082a2: f003 0307 and.w r3, r3, #7
80082a6: b2da uxtb r2, r3
80082a8: 68fb ldr r3, [r7, #12]
80082aa: 701a strb r2, [r3, #0]
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
80082ac: 883b ldrh r3, [r7, #0]
80082ae: f3c3 020a ubfx r2, r3, #0, #11
80082b2: 68fb ldr r3, [r7, #12]
80082b4: 611a str r2, [r3, #16]
ep->type = ep_type;
80082b6: 68fb ldr r3, [r7, #12]
80082b8: 78ba ldrb r2, [r7, #2]
80082ba: 70da strb r2, [r3, #3]
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
80082bc: 78bb ldrb r3, [r7, #2]
80082be: 2b02 cmp r3, #2
80082c0: d102 bne.n 80082c8 <HAL_PCD_EP_Open+0x8a>
{
ep->data_pid_start = 0U;
80082c2: 68fb ldr r3, [r7, #12]
80082c4: 2200 movs r2, #0
80082c6: 711a strb r2, [r3, #4]
}
__HAL_LOCK(hpcd);
80082c8: 687b ldr r3, [r7, #4]
80082ca: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
80082ce: 2b01 cmp r3, #1
80082d0: d101 bne.n 80082d6 <HAL_PCD_EP_Open+0x98>
80082d2: 2302 movs r3, #2
80082d4: e00e b.n 80082f4 <HAL_PCD_EP_Open+0xb6>
80082d6: 687b ldr r3, [r7, #4]
80082d8: 2201 movs r2, #1
80082da: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
80082de: 687b ldr r3, [r7, #4]
80082e0: 681b ldr r3, [r3, #0]
80082e2: 68f9 ldr r1, [r7, #12]
80082e4: 4618 mov r0, r3
80082e6: f005 fa23 bl 800d730 <USB_ActivateEndpoint>
__HAL_UNLOCK(hpcd);
80082ea: 687b ldr r3, [r7, #4]
80082ec: 2200 movs r2, #0
80082ee: f883 2290 strb.w r2, [r3, #656] @ 0x290
return ret;
80082f2: 7afb ldrb r3, [r7, #11]
}
80082f4: 4618 mov r0, r3
80082f6: 3710 adds r7, #16
80082f8: 46bd mov sp, r7
80082fa: bd80 pop {r7, pc}
080082fc <HAL_PCD_EP_Close>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
80082fc: b580 push {r7, lr}
80082fe: b084 sub sp, #16
8008300: af00 add r7, sp, #0
8008302: 6078 str r0, [r7, #4]
8008304: 460b mov r3, r1
8008306: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8008308: f997 3003 ldrsb.w r3, [r7, #3]
800830c: 2b00 cmp r3, #0
800830e: da0e bge.n 800832e <HAL_PCD_EP_Close+0x32>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8008310: 78fb ldrb r3, [r7, #3]
8008312: f003 0207 and.w r2, r3, #7
8008316: 4613 mov r3, r2
8008318: 009b lsls r3, r3, #2
800831a: 4413 add r3, r2
800831c: 00db lsls r3, r3, #3
800831e: 3310 adds r3, #16
8008320: 687a ldr r2, [r7, #4]
8008322: 4413 add r3, r2
8008324: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8008326: 68fb ldr r3, [r7, #12]
8008328: 2201 movs r2, #1
800832a: 705a strb r2, [r3, #1]
800832c: e00e b.n 800834c <HAL_PCD_EP_Close+0x50>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
800832e: 78fb ldrb r3, [r7, #3]
8008330: f003 0207 and.w r2, r3, #7
8008334: 4613 mov r3, r2
8008336: 009b lsls r3, r3, #2
8008338: 4413 add r3, r2
800833a: 00db lsls r3, r3, #3
800833c: f503 73a8 add.w r3, r3, #336 @ 0x150
8008340: 687a ldr r2, [r7, #4]
8008342: 4413 add r3, r2
8008344: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8008346: 68fb ldr r3, [r7, #12]
8008348: 2200 movs r2, #0
800834a: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
800834c: 78fb ldrb r3, [r7, #3]
800834e: f003 0307 and.w r3, r3, #7
8008352: b2da uxtb r2, r3
8008354: 68fb ldr r3, [r7, #12]
8008356: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8008358: 687b ldr r3, [r7, #4]
800835a: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
800835e: 2b01 cmp r3, #1
8008360: d101 bne.n 8008366 <HAL_PCD_EP_Close+0x6a>
8008362: 2302 movs r3, #2
8008364: e00e b.n 8008384 <HAL_PCD_EP_Close+0x88>
8008366: 687b ldr r3, [r7, #4]
8008368: 2201 movs r2, #1
800836a: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
800836e: 687b ldr r3, [r7, #4]
8008370: 681b ldr r3, [r3, #0]
8008372: 68f9 ldr r1, [r7, #12]
8008374: 4618 mov r0, r3
8008376: f005 fec3 bl 800e100 <USB_DeactivateEndpoint>
__HAL_UNLOCK(hpcd);
800837a: 687b ldr r3, [r7, #4]
800837c: 2200 movs r2, #0
800837e: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8008382: 2300 movs r3, #0
}
8008384: 4618 mov r0, r3
8008386: 3710 adds r7, #16
8008388: 46bd mov sp, r7
800838a: bd80 pop {r7, pc}
0800838c <HAL_PCD_EP_Receive>:
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
800838c: b580 push {r7, lr}
800838e: b086 sub sp, #24
8008390: af00 add r7, sp, #0
8008392: 60f8 str r0, [r7, #12]
8008394: 607a str r2, [r7, #4]
8008396: 603b str r3, [r7, #0]
8008398: 460b mov r3, r1
800839a: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
800839c: 7afb ldrb r3, [r7, #11]
800839e: f003 0207 and.w r2, r3, #7
80083a2: 4613 mov r3, r2
80083a4: 009b lsls r3, r3, #2
80083a6: 4413 add r3, r2
80083a8: 00db lsls r3, r3, #3
80083aa: f503 73a8 add.w r3, r3, #336 @ 0x150
80083ae: 68fa ldr r2, [r7, #12]
80083b0: 4413 add r3, r2
80083b2: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
80083b4: 697b ldr r3, [r7, #20]
80083b6: 687a ldr r2, [r7, #4]
80083b8: 615a str r2, [r3, #20]
ep->xfer_len = len;
80083ba: 697b ldr r3, [r7, #20]
80083bc: 683a ldr r2, [r7, #0]
80083be: 619a str r2, [r3, #24]
ep->xfer_count = 0U;
80083c0: 697b ldr r3, [r7, #20]
80083c2: 2200 movs r2, #0
80083c4: 61da str r2, [r3, #28]
ep->is_in = 0U;
80083c6: 697b ldr r3, [r7, #20]
80083c8: 2200 movs r2, #0
80083ca: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
80083cc: 7afb ldrb r3, [r7, #11]
80083ce: f003 0307 and.w r3, r3, #7
80083d2: b2da uxtb r2, r3
80083d4: 697b ldr r3, [r7, #20]
80083d6: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
80083d8: 68fb ldr r3, [r7, #12]
80083da: 681b ldr r3, [r3, #0]
80083dc: 6979 ldr r1, [r7, #20]
80083de: 4618 mov r0, r3
80083e0: f006 f87b bl 800e4da <USB_EPStartXfer>
return HAL_OK;
80083e4: 2300 movs r3, #0
}
80083e6: 4618 mov r0, r3
80083e8: 3718 adds r7, #24
80083ea: 46bd mov sp, r7
80083ec: bd80 pop {r7, pc}
080083ee <HAL_PCD_EP_GetRxCount>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
80083ee: b480 push {r7}
80083f0: b083 sub sp, #12
80083f2: af00 add r7, sp, #0
80083f4: 6078 str r0, [r7, #4]
80083f6: 460b mov r3, r1
80083f8: 70fb strb r3, [r7, #3]
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
80083fa: 78fb ldrb r3, [r7, #3]
80083fc: f003 0207 and.w r2, r3, #7
8008400: 6879 ldr r1, [r7, #4]
8008402: 4613 mov r3, r2
8008404: 009b lsls r3, r3, #2
8008406: 4413 add r3, r2
8008408: 00db lsls r3, r3, #3
800840a: 440b add r3, r1
800840c: f503 73b6 add.w r3, r3, #364 @ 0x16c
8008410: 681b ldr r3, [r3, #0]
}
8008412: 4618 mov r0, r3
8008414: 370c adds r7, #12
8008416: 46bd mov sp, r7
8008418: f85d 7b04 ldr.w r7, [sp], #4
800841c: 4770 bx lr
0800841e <HAL_PCD_EP_Transmit>:
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
800841e: b580 push {r7, lr}
8008420: b086 sub sp, #24
8008422: af00 add r7, sp, #0
8008424: 60f8 str r0, [r7, #12]
8008426: 607a str r2, [r7, #4]
8008428: 603b str r3, [r7, #0]
800842a: 460b mov r3, r1
800842c: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800842e: 7afb ldrb r3, [r7, #11]
8008430: f003 0207 and.w r2, r3, #7
8008434: 4613 mov r3, r2
8008436: 009b lsls r3, r3, #2
8008438: 4413 add r3, r2
800843a: 00db lsls r3, r3, #3
800843c: 3310 adds r3, #16
800843e: 68fa ldr r2, [r7, #12]
8008440: 4413 add r3, r2
8008442: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
8008444: 697b ldr r3, [r7, #20]
8008446: 687a ldr r2, [r7, #4]
8008448: 615a str r2, [r3, #20]
ep->xfer_len = len;
800844a: 697b ldr r3, [r7, #20]
800844c: 683a ldr r2, [r7, #0]
800844e: 619a str r2, [r3, #24]
ep->xfer_fill_db = 1U;
8008450: 697b ldr r3, [r7, #20]
8008452: 2201 movs r2, #1
8008454: f883 2024 strb.w r2, [r3, #36] @ 0x24
ep->xfer_len_db = len;
8008458: 697b ldr r3, [r7, #20]
800845a: 683a ldr r2, [r7, #0]
800845c: 621a str r2, [r3, #32]
ep->xfer_count = 0U;
800845e: 697b ldr r3, [r7, #20]
8008460: 2200 movs r2, #0
8008462: 61da str r2, [r3, #28]
ep->is_in = 1U;
8008464: 697b ldr r3, [r7, #20]
8008466: 2201 movs r2, #1
8008468: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
800846a: 7afb ldrb r3, [r7, #11]
800846c: f003 0307 and.w r3, r3, #7
8008470: b2da uxtb r2, r3
8008472: 697b ldr r3, [r7, #20]
8008474: 701a strb r2, [r3, #0]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8008476: 68fb ldr r3, [r7, #12]
8008478: 681b ldr r3, [r3, #0]
800847a: 6979 ldr r1, [r7, #20]
800847c: 4618 mov r0, r3
800847e: f006 f82c bl 800e4da <USB_EPStartXfer>
return HAL_OK;
8008482: 2300 movs r3, #0
}
8008484: 4618 mov r0, r3
8008486: 3718 adds r7, #24
8008488: 46bd mov sp, r7
800848a: bd80 pop {r7, pc}
0800848c <HAL_PCD_EP_SetStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
800848c: b580 push {r7, lr}
800848e: b084 sub sp, #16
8008490: af00 add r7, sp, #0
8008492: 6078 str r0, [r7, #4]
8008494: 460b mov r3, r1
8008496: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
8008498: 78fb ldrb r3, [r7, #3]
800849a: f003 0307 and.w r3, r3, #7
800849e: 687a ldr r2, [r7, #4]
80084a0: 7912 ldrb r2, [r2, #4]
80084a2: 4293 cmp r3, r2
80084a4: d901 bls.n 80084aa <HAL_PCD_EP_SetStall+0x1e>
{
return HAL_ERROR;
80084a6: 2301 movs r3, #1
80084a8: e03e b.n 8008528 <HAL_PCD_EP_SetStall+0x9c>
}
if ((0x80U & ep_addr) == 0x80U)
80084aa: f997 3003 ldrsb.w r3, [r7, #3]
80084ae: 2b00 cmp r3, #0
80084b0: da0e bge.n 80084d0 <HAL_PCD_EP_SetStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
80084b2: 78fb ldrb r3, [r7, #3]
80084b4: f003 0207 and.w r2, r3, #7
80084b8: 4613 mov r3, r2
80084ba: 009b lsls r3, r3, #2
80084bc: 4413 add r3, r2
80084be: 00db lsls r3, r3, #3
80084c0: 3310 adds r3, #16
80084c2: 687a ldr r2, [r7, #4]
80084c4: 4413 add r3, r2
80084c6: 60fb str r3, [r7, #12]
ep->is_in = 1U;
80084c8: 68fb ldr r3, [r7, #12]
80084ca: 2201 movs r2, #1
80084cc: 705a strb r2, [r3, #1]
80084ce: e00c b.n 80084ea <HAL_PCD_EP_SetStall+0x5e>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
80084d0: 78fa ldrb r2, [r7, #3]
80084d2: 4613 mov r3, r2
80084d4: 009b lsls r3, r3, #2
80084d6: 4413 add r3, r2
80084d8: 00db lsls r3, r3, #3
80084da: f503 73a8 add.w r3, r3, #336 @ 0x150
80084de: 687a ldr r2, [r7, #4]
80084e0: 4413 add r3, r2
80084e2: 60fb str r3, [r7, #12]
ep->is_in = 0U;
80084e4: 68fb ldr r3, [r7, #12]
80084e6: 2200 movs r2, #0
80084e8: 705a strb r2, [r3, #1]
}
ep->is_stall = 1U;
80084ea: 68fb ldr r3, [r7, #12]
80084ec: 2201 movs r2, #1
80084ee: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
80084f0: 78fb ldrb r3, [r7, #3]
80084f2: f003 0307 and.w r3, r3, #7
80084f6: b2da uxtb r2, r3
80084f8: 68fb ldr r3, [r7, #12]
80084fa: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
80084fc: 687b ldr r3, [r7, #4]
80084fe: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
8008502: 2b01 cmp r3, #1
8008504: d101 bne.n 800850a <HAL_PCD_EP_SetStall+0x7e>
8008506: 2302 movs r3, #2
8008508: e00e b.n 8008528 <HAL_PCD_EP_SetStall+0x9c>
800850a: 687b ldr r3, [r7, #4]
800850c: 2201 movs r2, #1
800850e: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPSetStall(hpcd->Instance, ep);
8008512: 687b ldr r3, [r7, #4]
8008514: 681b ldr r3, [r3, #0]
8008516: 68f9 ldr r1, [r7, #12]
8008518: 4618 mov r0, r3
800851a: f006 fd8d bl 800f038 <USB_EPSetStall>
__HAL_UNLOCK(hpcd);
800851e: 687b ldr r3, [r7, #4]
8008520: 2200 movs r2, #0
8008522: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
8008526: 2300 movs r3, #0
}
8008528: 4618 mov r0, r3
800852a: 3710 adds r7, #16
800852c: 46bd mov sp, r7
800852e: bd80 pop {r7, pc}
08008530 <HAL_PCD_EP_ClrStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8008530: b580 push {r7, lr}
8008532: b084 sub sp, #16
8008534: af00 add r7, sp, #0
8008536: 6078 str r0, [r7, #4]
8008538: 460b mov r3, r1
800853a: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
800853c: 78fb ldrb r3, [r7, #3]
800853e: f003 030f and.w r3, r3, #15
8008542: 687a ldr r2, [r7, #4]
8008544: 7912 ldrb r2, [r2, #4]
8008546: 4293 cmp r3, r2
8008548: d901 bls.n 800854e <HAL_PCD_EP_ClrStall+0x1e>
{
return HAL_ERROR;
800854a: 2301 movs r3, #1
800854c: e040 b.n 80085d0 <HAL_PCD_EP_ClrStall+0xa0>
}
if ((0x80U & ep_addr) == 0x80U)
800854e: f997 3003 ldrsb.w r3, [r7, #3]
8008552: 2b00 cmp r3, #0
8008554: da0e bge.n 8008574 <HAL_PCD_EP_ClrStall+0x44>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8008556: 78fb ldrb r3, [r7, #3]
8008558: f003 0207 and.w r2, r3, #7
800855c: 4613 mov r3, r2
800855e: 009b lsls r3, r3, #2
8008560: 4413 add r3, r2
8008562: 00db lsls r3, r3, #3
8008564: 3310 adds r3, #16
8008566: 687a ldr r2, [r7, #4]
8008568: 4413 add r3, r2
800856a: 60fb str r3, [r7, #12]
ep->is_in = 1U;
800856c: 68fb ldr r3, [r7, #12]
800856e: 2201 movs r2, #1
8008570: 705a strb r2, [r3, #1]
8008572: e00e b.n 8008592 <HAL_PCD_EP_ClrStall+0x62>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8008574: 78fb ldrb r3, [r7, #3]
8008576: f003 0207 and.w r2, r3, #7
800857a: 4613 mov r3, r2
800857c: 009b lsls r3, r3, #2
800857e: 4413 add r3, r2
8008580: 00db lsls r3, r3, #3
8008582: f503 73a8 add.w r3, r3, #336 @ 0x150
8008586: 687a ldr r2, [r7, #4]
8008588: 4413 add r3, r2
800858a: 60fb str r3, [r7, #12]
ep->is_in = 0U;
800858c: 68fb ldr r3, [r7, #12]
800858e: 2200 movs r2, #0
8008590: 705a strb r2, [r3, #1]
}
ep->is_stall = 0U;
8008592: 68fb ldr r3, [r7, #12]
8008594: 2200 movs r2, #0
8008596: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8008598: 78fb ldrb r3, [r7, #3]
800859a: f003 0307 and.w r3, r3, #7
800859e: b2da uxtb r2, r3
80085a0: 68fb ldr r3, [r7, #12]
80085a2: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
80085a4: 687b ldr r3, [r7, #4]
80085a6: f893 3290 ldrb.w r3, [r3, #656] @ 0x290
80085aa: 2b01 cmp r3, #1
80085ac: d101 bne.n 80085b2 <HAL_PCD_EP_ClrStall+0x82>
80085ae: 2302 movs r3, #2
80085b0: e00e b.n 80085d0 <HAL_PCD_EP_ClrStall+0xa0>
80085b2: 687b ldr r3, [r7, #4]
80085b4: 2201 movs r2, #1
80085b6: f883 2290 strb.w r2, [r3, #656] @ 0x290
(void)USB_EPClearStall(hpcd->Instance, ep);
80085ba: 687b ldr r3, [r7, #4]
80085bc: 681b ldr r3, [r3, #0]
80085be: 68f9 ldr r1, [r7, #12]
80085c0: 4618 mov r0, r3
80085c2: f006 fd8a bl 800f0da <USB_EPClearStall>
__HAL_UNLOCK(hpcd);
80085c6: 687b ldr r3, [r7, #4]
80085c8: 2200 movs r2, #0
80085ca: f883 2290 strb.w r2, [r3, #656] @ 0x290
return HAL_OK;
80085ce: 2300 movs r3, #0
}
80085d0: 4618 mov r0, r3
80085d2: 3710 adds r7, #16
80085d4: 46bd mov sp, r7
80085d6: bd80 pop {r7, pc}
080085d8 <PCD_EP_ISR_Handler>:
* @brief This function handles PCD Endpoint interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
80085d8: b580 push {r7, lr}
80085da: b094 sub sp, #80 @ 0x50
80085dc: af00 add r7, sp, #0
80085de: 6078 str r0, [r7, #4]
#if (USE_USB_DOUBLE_BUFFER != 1U)
count = 0U;
#endif /* USE_USB_DOUBLE_BUFFER */
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
80085e0: e374 b.n 8008ccc <PCD_EP_ISR_Handler+0x6f4>
{
wIstr = hpcd->Instance->ISTR;
80085e2: 687b ldr r3, [r7, #4]
80085e4: 681b ldr r3, [r3, #0]
80085e6: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
80085ea: f8a7 3042 strh.w r3, [r7, #66] @ 0x42
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
80085ee: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
80085f2: b2db uxtb r3, r3
80085f4: f003 030f and.w r3, r3, #15
80085f8: f887 3041 strb.w r3, [r7, #65] @ 0x41
if (epindex == 0U)
80085fc: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
8008600: 2b00 cmp r3, #0
8008602: f040 8143 bne.w 800888c <PCD_EP_ISR_Handler+0x2b4>
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
8008606: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42
800860a: f003 0310 and.w r3, r3, #16
800860e: 2b00 cmp r3, #0
8008610: d14c bne.n 80086ac <PCD_EP_ISR_Handler+0xd4>
{
/* DIR = 0 */
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8008612: 687b ldr r3, [r7, #4]
8008614: 681b ldr r3, [r3, #0]
8008616: 881b ldrh r3, [r3, #0]
8008618: b29b uxth r3, r3
800861a: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
800861e: f023 0370 bic.w r3, r3, #112 @ 0x70
8008622: 817b strh r3, [r7, #10]
8008624: 687b ldr r3, [r7, #4]
8008626: 681a ldr r2, [r3, #0]
8008628: 897b ldrh r3, [r7, #10]
800862a: ea6f 4343 mvn.w r3, r3, lsl #17
800862e: ea6f 4353 mvn.w r3, r3, lsr #17
8008632: b29b uxth r3, r3
8008634: 8013 strh r3, [r2, #0]
ep = &hpcd->IN_ep[0];
8008636: 687b ldr r3, [r7, #4]
8008638: 3310 adds r3, #16
800863a: 64bb str r3, [r7, #72] @ 0x48
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
800863c: 687b ldr r3, [r7, #4]
800863e: 681b ldr r3, [r3, #0]
8008640: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008644: b29b uxth r3, r3
8008646: 461a mov r2, r3
8008648: 6cbb ldr r3, [r7, #72] @ 0x48
800864a: 781b ldrb r3, [r3, #0]
800864c: 00db lsls r3, r3, #3
800864e: 4413 add r3, r2
8008650: 687a ldr r2, [r7, #4]
8008652: 6812 ldr r2, [r2, #0]
8008654: 4413 add r3, r2
8008656: f203 4302 addw r3, r3, #1026 @ 0x402
800865a: 881b ldrh r3, [r3, #0]
800865c: f3c3 0209 ubfx r2, r3, #0, #10
8008660: 6cbb ldr r3, [r7, #72] @ 0x48
8008662: 61da str r2, [r3, #28]
ep->xfer_buff += ep->xfer_count;
8008664: 6cbb ldr r3, [r7, #72] @ 0x48
8008666: 695a ldr r2, [r3, #20]
8008668: 6cbb ldr r3, [r7, #72] @ 0x48
800866a: 69db ldr r3, [r3, #28]
800866c: 441a add r2, r3
800866e: 6cbb ldr r3, [r7, #72] @ 0x48
8008670: 615a str r2, [r3, #20]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, 0U);
#else
HAL_PCD_DataInStageCallback(hpcd, 0U);
8008672: 2100 movs r1, #0
8008674: 6878 ldr r0, [r7, #4]
8008676: f00e fe3a bl 80172ee <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
800867a: 687b ldr r3, [r7, #4]
800867c: 7b1b ldrb r3, [r3, #12]
800867e: b2db uxtb r3, r3
8008680: 2b00 cmp r3, #0
8008682: f000 8323 beq.w 8008ccc <PCD_EP_ISR_Handler+0x6f4>
8008686: 6cbb ldr r3, [r7, #72] @ 0x48
8008688: 699b ldr r3, [r3, #24]
800868a: 2b00 cmp r3, #0
800868c: f040 831e bne.w 8008ccc <PCD_EP_ISR_Handler+0x6f4>
{
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
8008690: 687b ldr r3, [r7, #4]
8008692: 7b1b ldrb r3, [r3, #12]
8008694: b2db uxtb r3, r3
8008696: f063 037f orn r3, r3, #127 @ 0x7f
800869a: b2da uxtb r2, r3
800869c: 687b ldr r3, [r7, #4]
800869e: 681b ldr r3, [r3, #0]
80086a0: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
hpcd->USB_Address = 0U;
80086a4: 687b ldr r3, [r7, #4]
80086a6: 2200 movs r2, #0
80086a8: 731a strb r2, [r3, #12]
80086aa: e30f b.n 8008ccc <PCD_EP_ISR_Handler+0x6f4>
{
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
80086ac: 687b ldr r3, [r7, #4]
80086ae: f503 73a8 add.w r3, r3, #336 @ 0x150
80086b2: 64bb str r3, [r7, #72] @ 0x48
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
80086b4: 687b ldr r3, [r7, #4]
80086b6: 681b ldr r3, [r3, #0]
80086b8: 881b ldrh r3, [r3, #0]
80086ba: 87fb strh r3, [r7, #62] @ 0x3e
if ((wEPVal & USB_EP_SETUP) != 0U)
80086bc: 8ffb ldrh r3, [r7, #62] @ 0x3e
80086be: f403 6300 and.w r3, r3, #2048 @ 0x800
80086c2: 2b00 cmp r3, #0
80086c4: d07b beq.n 80087be <PCD_EP_ISR_Handler+0x1e6>
{
/* Get SETUP Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
80086c6: 687b ldr r3, [r7, #4]
80086c8: 681b ldr r3, [r3, #0]
80086ca: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80086ce: b29b uxth r3, r3
80086d0: 461a mov r2, r3
80086d2: 6cbb ldr r3, [r7, #72] @ 0x48
80086d4: 781b ldrb r3, [r3, #0]
80086d6: 00db lsls r3, r3, #3
80086d8: 4413 add r3, r2
80086da: 687a ldr r2, [r7, #4]
80086dc: 6812 ldr r2, [r2, #0]
80086de: 4413 add r3, r2
80086e0: f203 4306 addw r3, r3, #1030 @ 0x406
80086e4: 881b ldrh r3, [r3, #0]
80086e6: f3c3 0209 ubfx r2, r3, #0, #10
80086ea: 6cbb ldr r3, [r7, #72] @ 0x48
80086ec: 61da str r2, [r3, #28]
if (ep->xfer_count != 8U)
80086ee: 6cbb ldr r3, [r7, #72] @ 0x48
80086f0: 69db ldr r3, [r3, #28]
80086f2: 2b08 cmp r3, #8
80086f4: d044 beq.n 8008780 <PCD_EP_ISR_Handler+0x1a8>
{
/* Set Stall condition for EP0 IN/OUT */
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL);
80086f6: 687b ldr r3, [r7, #4]
80086f8: 681b ldr r3, [r3, #0]
80086fa: 881b ldrh r3, [r3, #0]
80086fc: b29b uxth r3, r3
80086fe: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008702: f023 0370 bic.w r3, r3, #112 @ 0x70
8008706: 823b strh r3, [r7, #16]
8008708: 8a3b ldrh r3, [r7, #16]
800870a: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800870e: 823b strh r3, [r7, #16]
8008710: 687b ldr r3, [r7, #4]
8008712: 681a ldr r2, [r3, #0]
8008714: 8a3b ldrh r3, [r7, #16]
8008716: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800871a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800871e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008722: f043 0380 orr.w r3, r3, #128 @ 0x80
8008726: b29b uxth r3, r3
8008728: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL);
800872a: 687b ldr r3, [r7, #4]
800872c: 681b ldr r3, [r3, #0]
800872e: 881b ldrh r3, [r3, #0]
8008730: b29b uxth r3, r3
8008732: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008736: f023 0340 bic.w r3, r3, #64 @ 0x40
800873a: 81fb strh r3, [r7, #14]
800873c: 89fb ldrh r3, [r7, #14]
800873e: f083 0310 eor.w r3, r3, #16
8008742: 81fb strh r3, [r7, #14]
8008744: 687b ldr r3, [r7, #4]
8008746: 681a ldr r2, [r3, #0]
8008748: 89fb ldrh r3, [r7, #14]
800874a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800874e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008752: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008756: f043 0380 orr.w r3, r3, #128 @ 0x80
800875a: b29b uxth r3, r3
800875c: 8013 strh r3, [r2, #0]
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
800875e: 687b ldr r3, [r7, #4]
8008760: 681b ldr r3, [r3, #0]
8008762: 881b ldrh r3, [r3, #0]
8008764: b29a uxth r2, r3
8008766: f640 738f movw r3, #3983 @ 0xf8f
800876a: 4013 ands r3, r2
800876c: 81bb strh r3, [r7, #12]
800876e: 687b ldr r3, [r7, #4]
8008770: 681b ldr r3, [r3, #0]
8008772: 89ba ldrh r2, [r7, #12]
8008774: f042 0280 orr.w r2, r2, #128 @ 0x80
8008778: b292 uxth r2, r2
800877a: 801a strh r2, [r3, #0]
return HAL_OK;
800877c: 2300 movs r3, #0
800877e: e2af b.n 8008ce0 <PCD_EP_ISR_Handler+0x708>
}
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
8008780: 687b ldr r3, [r7, #4]
8008782: 6818 ldr r0, [r3, #0]
8008784: 687b ldr r3, [r7, #4]
8008786: f503 7126 add.w r1, r3, #664 @ 0x298
800878a: 6cbb ldr r3, [r7, #72] @ 0x48
800878c: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
800878e: 6cbb ldr r3, [r7, #72] @ 0x48
8008790: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
8008792: b29b uxth r3, r3
8008794: f006 fdc8 bl 800f328 <USB_ReadPMA>
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8008798: 687b ldr r3, [r7, #4]
800879a: 681b ldr r3, [r3, #0]
800879c: 881b ldrh r3, [r3, #0]
800879e: b29a uxth r2, r3
80087a0: f640 738f movw r3, #3983 @ 0xf8f
80087a4: 4013 ands r3, r2
80087a6: 827b strh r3, [r7, #18]
80087a8: 687b ldr r3, [r7, #4]
80087aa: 681b ldr r3, [r3, #0]
80087ac: 8a7a ldrh r2, [r7, #18]
80087ae: f042 0280 orr.w r2, r2, #128 @ 0x80
80087b2: b292 uxth r2, r2
80087b4: 801a strh r2, [r3, #0]
/* Process SETUP Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
80087b6: 6878 ldr r0, [r7, #4]
80087b8: f00e fd6c bl 8017294 <HAL_PCD_SetupStageCallback>
80087bc: e286 b.n 8008ccc <PCD_EP_ISR_Handler+0x6f4>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
80087be: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e
80087c2: 2b00 cmp r3, #0
80087c4: f280 8282 bge.w 8008ccc <PCD_EP_ISR_Handler+0x6f4>
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
80087c8: 687b ldr r3, [r7, #4]
80087ca: 681b ldr r3, [r3, #0]
80087cc: 881b ldrh r3, [r3, #0]
80087ce: b29a uxth r2, r3
80087d0: f640 738f movw r3, #3983 @ 0xf8f
80087d4: 4013 ands r3, r2
80087d6: 82fb strh r3, [r7, #22]
80087d8: 687b ldr r3, [r7, #4]
80087da: 681b ldr r3, [r3, #0]
80087dc: 8afa ldrh r2, [r7, #22]
80087de: f042 0280 orr.w r2, r2, #128 @ 0x80
80087e2: b292 uxth r2, r2
80087e4: 801a strh r2, [r3, #0]
/* Get Control Data OUT Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
80087e6: 687b ldr r3, [r7, #4]
80087e8: 681b ldr r3, [r3, #0]
80087ea: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80087ee: b29b uxth r3, r3
80087f0: 461a mov r2, r3
80087f2: 6cbb ldr r3, [r7, #72] @ 0x48
80087f4: 781b ldrb r3, [r3, #0]
80087f6: 00db lsls r3, r3, #3
80087f8: 4413 add r3, r2
80087fa: 687a ldr r2, [r7, #4]
80087fc: 6812 ldr r2, [r2, #0]
80087fe: 4413 add r3, r2
8008800: f203 4306 addw r3, r3, #1030 @ 0x406
8008804: 881b ldrh r3, [r3, #0]
8008806: f3c3 0209 ubfx r2, r3, #0, #10
800880a: 6cbb ldr r3, [r7, #72] @ 0x48
800880c: 61da str r2, [r3, #28]
if (ep->xfer_count == 0U)
800880e: 6cbb ldr r3, [r7, #72] @ 0x48
8008810: 69db ldr r3, [r3, #28]
8008812: 2b00 cmp r3, #0
8008814: d11e bne.n 8008854 <PCD_EP_ISR_Handler+0x27c>
{
/* Status phase re-arm for next setup */
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
8008816: 687b ldr r3, [r7, #4]
8008818: 681b ldr r3, [r3, #0]
800881a: 881b ldrh r3, [r3, #0]
800881c: b29b uxth r3, r3
800881e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008822: f023 0370 bic.w r3, r3, #112 @ 0x70
8008826: 82bb strh r3, [r7, #20]
8008828: 8abb ldrh r3, [r7, #20]
800882a: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800882e: 82bb strh r3, [r7, #20]
8008830: 8abb ldrh r3, [r7, #20]
8008832: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008836: 82bb strh r3, [r7, #20]
8008838: 687b ldr r3, [r7, #4]
800883a: 681a ldr r2, [r3, #0]
800883c: 8abb ldrh r3, [r7, #20]
800883e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008842: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008846: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800884a: f043 0380 orr.w r3, r3, #128 @ 0x80
800884e: b29b uxth r3, r3
8008850: 8013 strh r3, [r2, #0]
8008852: e23b b.n 8008ccc <PCD_EP_ISR_Handler+0x6f4>
}
else
{
if (ep->xfer_buff != 0U)
8008854: 6cbb ldr r3, [r7, #72] @ 0x48
8008856: 695b ldr r3, [r3, #20]
8008858: 2b00 cmp r3, #0
800885a: f000 8237 beq.w 8008ccc <PCD_EP_ISR_Handler+0x6f4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
800885e: 687b ldr r3, [r7, #4]
8008860: 6818 ldr r0, [r3, #0]
8008862: 6cbb ldr r3, [r7, #72] @ 0x48
8008864: 6959 ldr r1, [r3, #20]
8008866: 6cbb ldr r3, [r7, #72] @ 0x48
8008868: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */
800886a: 6cbb ldr r3, [r7, #72] @ 0x48
800886c: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
800886e: b29b uxth r3, r3
8008870: f006 fd5a bl 800f328 <USB_ReadPMA>
ep->xfer_buff += ep->xfer_count;
8008874: 6cbb ldr r3, [r7, #72] @ 0x48
8008876: 695a ldr r2, [r3, #20]
8008878: 6cbb ldr r3, [r7, #72] @ 0x48
800887a: 69db ldr r3, [r3, #28]
800887c: 441a add r2, r3
800887e: 6cbb ldr r3, [r7, #72] @ 0x48
8008880: 615a str r2, [r3, #20]
/* Process Control Data OUT Packet */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U);
#else
HAL_PCD_DataOutStageCallback(hpcd, 0U);
8008882: 2100 movs r1, #0
8008884: 6878 ldr r0, [r7, #4]
8008886: f00e fd17 bl 80172b8 <HAL_PCD_DataOutStageCallback>
800888a: e21f b.n 8008ccc <PCD_EP_ISR_Handler+0x6f4>
}
else
{
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
800888c: 687b ldr r3, [r7, #4]
800888e: 681b ldr r3, [r3, #0]
8008890: 461a mov r2, r3
8008892: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
8008896: 009b lsls r3, r3, #2
8008898: 4413 add r3, r2
800889a: 881b ldrh r3, [r3, #0]
800889c: 87fb strh r3, [r7, #62] @ 0x3e
if ((wEPVal & USB_EP_CTR_RX) != 0U)
800889e: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e
80088a2: 2b00 cmp r3, #0
80088a4: f280 80f5 bge.w 8008a92 <PCD_EP_ISR_Handler+0x4ba>
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
80088a8: 687b ldr r3, [r7, #4]
80088aa: 681b ldr r3, [r3, #0]
80088ac: 461a mov r2, r3
80088ae: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
80088b2: 009b lsls r3, r3, #2
80088b4: 4413 add r3, r2
80088b6: 881b ldrh r3, [r3, #0]
80088b8: b29a uxth r2, r3
80088ba: f640 738f movw r3, #3983 @ 0xf8f
80088be: 4013 ands r3, r2
80088c0: f8a7 3046 strh.w r3, [r7, #70] @ 0x46
80088c4: 687b ldr r3, [r7, #4]
80088c6: 681b ldr r3, [r3, #0]
80088c8: 461a mov r2, r3
80088ca: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
80088ce: 009b lsls r3, r3, #2
80088d0: 4413 add r3, r2
80088d2: f8b7 2046 ldrh.w r2, [r7, #70] @ 0x46
80088d6: f042 0280 orr.w r2, r2, #128 @ 0x80
80088da: b292 uxth r2, r2
80088dc: 801a strh r2, [r3, #0]
ep = &hpcd->OUT_ep[epindex];
80088de: f897 2041 ldrb.w r2, [r7, #65] @ 0x41
80088e2: 4613 mov r3, r2
80088e4: 009b lsls r3, r3, #2
80088e6: 4413 add r3, r2
80088e8: 00db lsls r3, r3, #3
80088ea: f503 73a8 add.w r3, r3, #336 @ 0x150
80088ee: 687a ldr r2, [r7, #4]
80088f0: 4413 add r3, r2
80088f2: 64bb str r3, [r7, #72] @ 0x48
/* OUT Single Buffering */
if (ep->doublebuffer == 0U)
80088f4: 6cbb ldr r3, [r7, #72] @ 0x48
80088f6: 7b1b ldrb r3, [r3, #12]
80088f8: 2b00 cmp r3, #0
80088fa: d123 bne.n 8008944 <PCD_EP_ISR_Handler+0x36c>
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
80088fc: 687b ldr r3, [r7, #4]
80088fe: 681b ldr r3, [r3, #0]
8008900: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008904: b29b uxth r3, r3
8008906: 461a mov r2, r3
8008908: 6cbb ldr r3, [r7, #72] @ 0x48
800890a: 781b ldrb r3, [r3, #0]
800890c: 00db lsls r3, r3, #3
800890e: 4413 add r3, r2
8008910: 687a ldr r2, [r7, #4]
8008912: 6812 ldr r2, [r2, #0]
8008914: 4413 add r3, r2
8008916: f203 4306 addw r3, r3, #1030 @ 0x406
800891a: 881b ldrh r3, [r3, #0]
800891c: f3c3 0309 ubfx r3, r3, #0, #10
8008920: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
if (count != 0U)
8008924: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8008928: 2b00 cmp r3, #0
800892a: f000 808d beq.w 8008a48 <PCD_EP_ISR_Handler+0x470>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
800892e: 687b ldr r3, [r7, #4]
8008930: 6818 ldr r0, [r3, #0]
8008932: 6cbb ldr r3, [r7, #72] @ 0x48
8008934: 6959 ldr r1, [r3, #20]
8008936: 6cbb ldr r3, [r7, #72] @ 0x48
8008938: 88da ldrh r2, [r3, #6]
800893a: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
800893e: f006 fcf3 bl 800f328 <USB_ReadPMA>
8008942: e081 b.n 8008a48 <PCD_EP_ISR_Handler+0x470>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
if (ep->type == EP_TYPE_BULK)
8008944: 6cbb ldr r3, [r7, #72] @ 0x48
8008946: 78db ldrb r3, [r3, #3]
8008948: 2b02 cmp r3, #2
800894a: d109 bne.n 8008960 <PCD_EP_ISR_Handler+0x388>
{
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
800894c: 8ffb ldrh r3, [r7, #62] @ 0x3e
800894e: 461a mov r2, r3
8008950: 6cb9 ldr r1, [r7, #72] @ 0x48
8008952: 6878 ldr r0, [r7, #4]
8008954: f000 f9c8 bl 8008ce8 <HAL_PCD_EP_DB_Receive>
8008958: 4603 mov r3, r0
800895a: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
800895e: e073 b.n 8008a48 <PCD_EP_ISR_Handler+0x470>
}
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
8008960: 687b ldr r3, [r7, #4]
8008962: 681b ldr r3, [r3, #0]
8008964: 461a mov r2, r3
8008966: 6cbb ldr r3, [r7, #72] @ 0x48
8008968: 781b ldrb r3, [r3, #0]
800896a: 009b lsls r3, r3, #2
800896c: 4413 add r3, r2
800896e: 881b ldrh r3, [r3, #0]
8008970: b29b uxth r3, r3
8008972: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008976: f023 0370 bic.w r3, r3, #112 @ 0x70
800897a: f8a7 3044 strh.w r3, [r7, #68] @ 0x44
800897e: 687b ldr r3, [r7, #4]
8008980: 681b ldr r3, [r3, #0]
8008982: 461a mov r2, r3
8008984: 6cbb ldr r3, [r7, #72] @ 0x48
8008986: 781b ldrb r3, [r3, #0]
8008988: 009b lsls r3, r3, #2
800898a: 441a add r2, r3
800898c: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44
8008990: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008994: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008998: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800899c: f043 03c0 orr.w r3, r3, #192 @ 0xc0
80089a0: b29b uxth r3, r3
80089a2: 8013 strh r3, [r2, #0]
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
80089a4: 687b ldr r3, [r7, #4]
80089a6: 681b ldr r3, [r3, #0]
80089a8: 461a mov r2, r3
80089aa: 6cbb ldr r3, [r7, #72] @ 0x48
80089ac: 781b ldrb r3, [r3, #0]
80089ae: 009b lsls r3, r3, #2
80089b0: 4413 add r3, r2
80089b2: 881b ldrh r3, [r3, #0]
80089b4: b29b uxth r3, r3
80089b6: f403 4380 and.w r3, r3, #16384 @ 0x4000
80089ba: 2b00 cmp r3, #0
80089bc: d022 beq.n 8008a04 <PCD_EP_ISR_Handler+0x42c>
{
/* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
80089be: 687b ldr r3, [r7, #4]
80089c0: 681b ldr r3, [r3, #0]
80089c2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80089c6: b29b uxth r3, r3
80089c8: 461a mov r2, r3
80089ca: 6cbb ldr r3, [r7, #72] @ 0x48
80089cc: 781b ldrb r3, [r3, #0]
80089ce: 00db lsls r3, r3, #3
80089d0: 4413 add r3, r2
80089d2: 687a ldr r2, [r7, #4]
80089d4: 6812 ldr r2, [r2, #0]
80089d6: 4413 add r3, r2
80089d8: f203 4302 addw r3, r3, #1026 @ 0x402
80089dc: 881b ldrh r3, [r3, #0]
80089de: f3c3 0309 ubfx r3, r3, #0, #10
80089e2: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
if (count != 0U)
80089e6: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
80089ea: 2b00 cmp r3, #0
80089ec: d02c beq.n 8008a48 <PCD_EP_ISR_Handler+0x470>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
80089ee: 687b ldr r3, [r7, #4]
80089f0: 6818 ldr r0, [r3, #0]
80089f2: 6cbb ldr r3, [r7, #72] @ 0x48
80089f4: 6959 ldr r1, [r3, #20]
80089f6: 6cbb ldr r3, [r7, #72] @ 0x48
80089f8: 891a ldrh r2, [r3, #8]
80089fa: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
80089fe: f006 fc93 bl 800f328 <USB_ReadPMA>
8008a02: e021 b.n 8008a48 <PCD_EP_ISR_Handler+0x470>
}
}
else
{
/* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8008a04: 687b ldr r3, [r7, #4]
8008a06: 681b ldr r3, [r3, #0]
8008a08: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008a0c: b29b uxth r3, r3
8008a0e: 461a mov r2, r3
8008a10: 6cbb ldr r3, [r7, #72] @ 0x48
8008a12: 781b ldrb r3, [r3, #0]
8008a14: 00db lsls r3, r3, #3
8008a16: 4413 add r3, r2
8008a18: 687a ldr r2, [r7, #4]
8008a1a: 6812 ldr r2, [r2, #0]
8008a1c: 4413 add r3, r2
8008a1e: f203 4306 addw r3, r3, #1030 @ 0x406
8008a22: 881b ldrh r3, [r3, #0]
8008a24: f3c3 0309 ubfx r3, r3, #0, #10
8008a28: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
if (count != 0U)
8008a2c: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8008a30: 2b00 cmp r3, #0
8008a32: d009 beq.n 8008a48 <PCD_EP_ISR_Handler+0x470>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8008a34: 687b ldr r3, [r7, #4]
8008a36: 6818 ldr r0, [r3, #0]
8008a38: 6cbb ldr r3, [r7, #72] @ 0x48
8008a3a: 6959 ldr r1, [r3, #20]
8008a3c: 6cbb ldr r3, [r7, #72] @ 0x48
8008a3e: 895a ldrh r2, [r3, #10]
8008a40: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8008a44: f006 fc70 bl 800f328 <USB_ReadPMA>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
8008a48: 6cbb ldr r3, [r7, #72] @ 0x48
8008a4a: 69da ldr r2, [r3, #28]
8008a4c: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8008a50: 441a add r2, r3
8008a52: 6cbb ldr r3, [r7, #72] @ 0x48
8008a54: 61da str r2, [r3, #28]
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
8008a56: 6cbb ldr r3, [r7, #72] @ 0x48
8008a58: 699b ldr r3, [r3, #24]
8008a5a: 2b00 cmp r3, #0
8008a5c: d005 beq.n 8008a6a <PCD_EP_ISR_Handler+0x492>
8008a5e: f8b7 204e ldrh.w r2, [r7, #78] @ 0x4e
8008a62: 6cbb ldr r3, [r7, #72] @ 0x48
8008a64: 691b ldr r3, [r3, #16]
8008a66: 429a cmp r2, r3
8008a68: d206 bcs.n 8008a78 <PCD_EP_ISR_Handler+0x4a0>
{
/* RX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
8008a6a: 6cbb ldr r3, [r7, #72] @ 0x48
8008a6c: 781b ldrb r3, [r3, #0]
8008a6e: 4619 mov r1, r3
8008a70: 6878 ldr r0, [r7, #4]
8008a72: f00e fc21 bl 80172b8 <HAL_PCD_DataOutStageCallback>
8008a76: e00c b.n 8008a92 <PCD_EP_ISR_Handler+0x4ba>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
ep->xfer_buff += count;
8008a78: 6cbb ldr r3, [r7, #72] @ 0x48
8008a7a: 695a ldr r2, [r3, #20]
8008a7c: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8008a80: 441a add r2, r3
8008a82: 6cbb ldr r3, [r7, #72] @ 0x48
8008a84: 615a str r2, [r3, #20]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8008a86: 687b ldr r3, [r7, #4]
8008a88: 681b ldr r3, [r3, #0]
8008a8a: 6cb9 ldr r1, [r7, #72] @ 0x48
8008a8c: 4618 mov r0, r3
8008a8e: f005 fd24 bl 800e4da <USB_EPStartXfer>
}
}
if ((wEPVal & USB_EP_CTR_TX) != 0U)
8008a92: 8ffb ldrh r3, [r7, #62] @ 0x3e
8008a94: f003 0380 and.w r3, r3, #128 @ 0x80
8008a98: 2b00 cmp r3, #0
8008a9a: f000 8117 beq.w 8008ccc <PCD_EP_ISR_Handler+0x6f4>
{
ep = &hpcd->IN_ep[epindex];
8008a9e: f897 2041 ldrb.w r2, [r7, #65] @ 0x41
8008aa2: 4613 mov r3, r2
8008aa4: 009b lsls r3, r3, #2
8008aa6: 4413 add r3, r2
8008aa8: 00db lsls r3, r3, #3
8008aaa: 3310 adds r3, #16
8008aac: 687a ldr r2, [r7, #4]
8008aae: 4413 add r3, r2
8008ab0: 64bb str r3, [r7, #72] @ 0x48
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
8008ab2: 687b ldr r3, [r7, #4]
8008ab4: 681b ldr r3, [r3, #0]
8008ab6: 461a mov r2, r3
8008ab8: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
8008abc: 009b lsls r3, r3, #2
8008abe: 4413 add r3, r2
8008ac0: 881b ldrh r3, [r3, #0]
8008ac2: b29b uxth r3, r3
8008ac4: f423 43e1 bic.w r3, r3, #28800 @ 0x7080
8008ac8: f023 0370 bic.w r3, r3, #112 @ 0x70
8008acc: 87bb strh r3, [r7, #60] @ 0x3c
8008ace: 687b ldr r3, [r7, #4]
8008ad0: 681b ldr r3, [r3, #0]
8008ad2: 461a mov r2, r3
8008ad4: f897 3041 ldrb.w r3, [r7, #65] @ 0x41
8008ad8: 009b lsls r3, r3, #2
8008ada: 441a add r2, r3
8008adc: 8fbb ldrh r3, [r7, #60] @ 0x3c
8008ade: ea6f 4343 mvn.w r3, r3, lsl #17
8008ae2: ea6f 4353 mvn.w r3, r3, lsr #17
8008ae6: b29b uxth r3, r3
8008ae8: 8013 strh r3, [r2, #0]
if (ep->type == EP_TYPE_ISOC)
8008aea: 6cbb ldr r3, [r7, #72] @ 0x48
8008aec: 78db ldrb r3, [r3, #3]
8008aee: 2b01 cmp r3, #1
8008af0: f040 80a1 bne.w 8008c36 <PCD_EP_ISR_Handler+0x65e>
{
ep->xfer_len = 0U;
8008af4: 6cbb ldr r3, [r7, #72] @ 0x48
8008af6: 2200 movs r2, #0
8008af8: 619a str r2, [r3, #24]
#if (USE_USB_DOUBLE_BUFFER == 1U)
if (ep->doublebuffer != 0U)
8008afa: 6cbb ldr r3, [r7, #72] @ 0x48
8008afc: 7b1b ldrb r3, [r3, #12]
8008afe: 2b00 cmp r3, #0
8008b00: f000 8092 beq.w 8008c28 <PCD_EP_ISR_Handler+0x650>
{
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8008b04: 8ffb ldrh r3, [r7, #62] @ 0x3e
8008b06: f003 0340 and.w r3, r3, #64 @ 0x40
8008b0a: 2b00 cmp r3, #0
8008b0c: d046 beq.n 8008b9c <PCD_EP_ISR_Handler+0x5c4>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8008b0e: 6cbb ldr r3, [r7, #72] @ 0x48
8008b10: 785b ldrb r3, [r3, #1]
8008b12: 2b00 cmp r3, #0
8008b14: d126 bne.n 8008b64 <PCD_EP_ISR_Handler+0x58c>
8008b16: 687b ldr r3, [r7, #4]
8008b18: 681b ldr r3, [r3, #0]
8008b1a: 61fb str r3, [r7, #28]
8008b1c: 687b ldr r3, [r7, #4]
8008b1e: 681b ldr r3, [r3, #0]
8008b20: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008b24: b29b uxth r3, r3
8008b26: 461a mov r2, r3
8008b28: 69fb ldr r3, [r7, #28]
8008b2a: 4413 add r3, r2
8008b2c: 61fb str r3, [r7, #28]
8008b2e: 6cbb ldr r3, [r7, #72] @ 0x48
8008b30: 781b ldrb r3, [r3, #0]
8008b32: 00da lsls r2, r3, #3
8008b34: 69fb ldr r3, [r7, #28]
8008b36: 4413 add r3, r2
8008b38: f203 4302 addw r3, r3, #1026 @ 0x402
8008b3c: 61bb str r3, [r7, #24]
8008b3e: 69bb ldr r3, [r7, #24]
8008b40: 881b ldrh r3, [r3, #0]
8008b42: b29b uxth r3, r3
8008b44: f3c3 0309 ubfx r3, r3, #0, #10
8008b48: b29a uxth r2, r3
8008b4a: 69bb ldr r3, [r7, #24]
8008b4c: 801a strh r2, [r3, #0]
8008b4e: 69bb ldr r3, [r7, #24]
8008b50: 881b ldrh r3, [r3, #0]
8008b52: b29b uxth r3, r3
8008b54: ea6f 4343 mvn.w r3, r3, lsl #17
8008b58: ea6f 4353 mvn.w r3, r3, lsr #17
8008b5c: b29a uxth r2, r3
8008b5e: 69bb ldr r3, [r7, #24]
8008b60: 801a strh r2, [r3, #0]
8008b62: e061 b.n 8008c28 <PCD_EP_ISR_Handler+0x650>
8008b64: 6cbb ldr r3, [r7, #72] @ 0x48
8008b66: 785b ldrb r3, [r3, #1]
8008b68: 2b01 cmp r3, #1
8008b6a: d15d bne.n 8008c28 <PCD_EP_ISR_Handler+0x650>
8008b6c: 687b ldr r3, [r7, #4]
8008b6e: 681b ldr r3, [r3, #0]
8008b70: 627b str r3, [r7, #36] @ 0x24
8008b72: 687b ldr r3, [r7, #4]
8008b74: 681b ldr r3, [r3, #0]
8008b76: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008b7a: b29b uxth r3, r3
8008b7c: 461a mov r2, r3
8008b7e: 6a7b ldr r3, [r7, #36] @ 0x24
8008b80: 4413 add r3, r2
8008b82: 627b str r3, [r7, #36] @ 0x24
8008b84: 6cbb ldr r3, [r7, #72] @ 0x48
8008b86: 781b ldrb r3, [r3, #0]
8008b88: 00da lsls r2, r3, #3
8008b8a: 6a7b ldr r3, [r7, #36] @ 0x24
8008b8c: 4413 add r3, r2
8008b8e: f203 4302 addw r3, r3, #1026 @ 0x402
8008b92: 623b str r3, [r7, #32]
8008b94: 6a3b ldr r3, [r7, #32]
8008b96: 2200 movs r2, #0
8008b98: 801a strh r2, [r3, #0]
8008b9a: e045 b.n 8008c28 <PCD_EP_ISR_Handler+0x650>
}
else
{
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8008b9c: 687b ldr r3, [r7, #4]
8008b9e: 681b ldr r3, [r3, #0]
8008ba0: 637b str r3, [r7, #52] @ 0x34
8008ba2: 6cbb ldr r3, [r7, #72] @ 0x48
8008ba4: 785b ldrb r3, [r3, #1]
8008ba6: 2b00 cmp r3, #0
8008ba8: d126 bne.n 8008bf8 <PCD_EP_ISR_Handler+0x620>
8008baa: 687b ldr r3, [r7, #4]
8008bac: 681b ldr r3, [r3, #0]
8008bae: 62fb str r3, [r7, #44] @ 0x2c
8008bb0: 687b ldr r3, [r7, #4]
8008bb2: 681b ldr r3, [r3, #0]
8008bb4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008bb8: b29b uxth r3, r3
8008bba: 461a mov r2, r3
8008bbc: 6afb ldr r3, [r7, #44] @ 0x2c
8008bbe: 4413 add r3, r2
8008bc0: 62fb str r3, [r7, #44] @ 0x2c
8008bc2: 6cbb ldr r3, [r7, #72] @ 0x48
8008bc4: 781b ldrb r3, [r3, #0]
8008bc6: 00da lsls r2, r3, #3
8008bc8: 6afb ldr r3, [r7, #44] @ 0x2c
8008bca: 4413 add r3, r2
8008bcc: f203 4306 addw r3, r3, #1030 @ 0x406
8008bd0: 62bb str r3, [r7, #40] @ 0x28
8008bd2: 6abb ldr r3, [r7, #40] @ 0x28
8008bd4: 881b ldrh r3, [r3, #0]
8008bd6: b29b uxth r3, r3
8008bd8: f3c3 0309 ubfx r3, r3, #0, #10
8008bdc: b29a uxth r2, r3
8008bde: 6abb ldr r3, [r7, #40] @ 0x28
8008be0: 801a strh r2, [r3, #0]
8008be2: 6abb ldr r3, [r7, #40] @ 0x28
8008be4: 881b ldrh r3, [r3, #0]
8008be6: b29b uxth r3, r3
8008be8: ea6f 4343 mvn.w r3, r3, lsl #17
8008bec: ea6f 4353 mvn.w r3, r3, lsr #17
8008bf0: b29a uxth r2, r3
8008bf2: 6abb ldr r3, [r7, #40] @ 0x28
8008bf4: 801a strh r2, [r3, #0]
8008bf6: e017 b.n 8008c28 <PCD_EP_ISR_Handler+0x650>
8008bf8: 6cbb ldr r3, [r7, #72] @ 0x48
8008bfa: 785b ldrb r3, [r3, #1]
8008bfc: 2b01 cmp r3, #1
8008bfe: d113 bne.n 8008c28 <PCD_EP_ISR_Handler+0x650>
8008c00: 687b ldr r3, [r7, #4]
8008c02: 681b ldr r3, [r3, #0]
8008c04: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008c08: b29b uxth r3, r3
8008c0a: 461a mov r2, r3
8008c0c: 6b7b ldr r3, [r7, #52] @ 0x34
8008c0e: 4413 add r3, r2
8008c10: 637b str r3, [r7, #52] @ 0x34
8008c12: 6cbb ldr r3, [r7, #72] @ 0x48
8008c14: 781b ldrb r3, [r3, #0]
8008c16: 00da lsls r2, r3, #3
8008c18: 6b7b ldr r3, [r7, #52] @ 0x34
8008c1a: 4413 add r3, r2
8008c1c: f203 4306 addw r3, r3, #1030 @ 0x406
8008c20: 633b str r3, [r7, #48] @ 0x30
8008c22: 6b3b ldr r3, [r7, #48] @ 0x30
8008c24: 2200 movs r2, #0
8008c26: 801a strh r2, [r3, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8008c28: 6cbb ldr r3, [r7, #72] @ 0x48
8008c2a: 781b ldrb r3, [r3, #0]
8008c2c: 4619 mov r1, r3
8008c2e: 6878 ldr r0, [r7, #4]
8008c30: f00e fb5d bl 80172ee <HAL_PCD_DataInStageCallback>
8008c34: e04a b.n 8008ccc <PCD_EP_ISR_Handler+0x6f4>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Manage Single Buffer Transaction */
if ((wEPVal & USB_EP_KIND) == 0U)
8008c36: 8ffb ldrh r3, [r7, #62] @ 0x3e
8008c38: f403 7380 and.w r3, r3, #256 @ 0x100
8008c3c: 2b00 cmp r3, #0
8008c3e: d13f bne.n 8008cc0 <PCD_EP_ISR_Handler+0x6e8>
{
/* Multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
8008c40: 687b ldr r3, [r7, #4]
8008c42: 681b ldr r3, [r3, #0]
8008c44: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008c48: b29b uxth r3, r3
8008c4a: 461a mov r2, r3
8008c4c: 6cbb ldr r3, [r7, #72] @ 0x48
8008c4e: 781b ldrb r3, [r3, #0]
8008c50: 00db lsls r3, r3, #3
8008c52: 4413 add r3, r2
8008c54: 687a ldr r2, [r7, #4]
8008c56: 6812 ldr r2, [r2, #0]
8008c58: 4413 add r3, r2
8008c5a: f203 4302 addw r3, r3, #1026 @ 0x402
8008c5e: 881b ldrh r3, [r3, #0]
8008c60: f3c3 0309 ubfx r3, r3, #0, #10
8008c64: 877b strh r3, [r7, #58] @ 0x3a
if (ep->xfer_len > TxPctSize)
8008c66: 6cbb ldr r3, [r7, #72] @ 0x48
8008c68: 699a ldr r2, [r3, #24]
8008c6a: 8f7b ldrh r3, [r7, #58] @ 0x3a
8008c6c: 429a cmp r2, r3
8008c6e: d906 bls.n 8008c7e <PCD_EP_ISR_Handler+0x6a6>
{
ep->xfer_len -= TxPctSize;
8008c70: 6cbb ldr r3, [r7, #72] @ 0x48
8008c72: 699a ldr r2, [r3, #24]
8008c74: 8f7b ldrh r3, [r7, #58] @ 0x3a
8008c76: 1ad2 subs r2, r2, r3
8008c78: 6cbb ldr r3, [r7, #72] @ 0x48
8008c7a: 619a str r2, [r3, #24]
8008c7c: e002 b.n 8008c84 <PCD_EP_ISR_Handler+0x6ac>
}
else
{
ep->xfer_len = 0U;
8008c7e: 6cbb ldr r3, [r7, #72] @ 0x48
8008c80: 2200 movs r2, #0
8008c82: 619a str r2, [r3, #24]
}
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
8008c84: 6cbb ldr r3, [r7, #72] @ 0x48
8008c86: 699b ldr r3, [r3, #24]
8008c88: 2b00 cmp r3, #0
8008c8a: d106 bne.n 8008c9a <PCD_EP_ISR_Handler+0x6c2>
{
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8008c8c: 6cbb ldr r3, [r7, #72] @ 0x48
8008c8e: 781b ldrb r3, [r3, #0]
8008c90: 4619 mov r1, r3
8008c92: 6878 ldr r0, [r7, #4]
8008c94: f00e fb2b bl 80172ee <HAL_PCD_DataInStageCallback>
8008c98: e018 b.n 8008ccc <PCD_EP_ISR_Handler+0x6f4>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Transfer is not yet Done */
ep->xfer_buff += TxPctSize;
8008c9a: 6cbb ldr r3, [r7, #72] @ 0x48
8008c9c: 695a ldr r2, [r3, #20]
8008c9e: 8f7b ldrh r3, [r7, #58] @ 0x3a
8008ca0: 441a add r2, r3
8008ca2: 6cbb ldr r3, [r7, #72] @ 0x48
8008ca4: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8008ca6: 6cbb ldr r3, [r7, #72] @ 0x48
8008ca8: 69da ldr r2, [r3, #28]
8008caa: 8f7b ldrh r3, [r7, #58] @ 0x3a
8008cac: 441a add r2, r3
8008cae: 6cbb ldr r3, [r7, #72] @ 0x48
8008cb0: 61da str r2, [r3, #28]
(void)USB_EPStartXfer(hpcd->Instance, ep);
8008cb2: 687b ldr r3, [r7, #4]
8008cb4: 681b ldr r3, [r3, #0]
8008cb6: 6cb9 ldr r1, [r7, #72] @ 0x48
8008cb8: 4618 mov r0, r3
8008cba: f005 fc0e bl 800e4da <USB_EPStartXfer>
8008cbe: e005 b.n 8008ccc <PCD_EP_ISR_Handler+0x6f4>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
8008cc0: 8ffb ldrh r3, [r7, #62] @ 0x3e
8008cc2: 461a mov r2, r3
8008cc4: 6cb9 ldr r1, [r7, #72] @ 0x48
8008cc6: 6878 ldr r0, [r7, #4]
8008cc8: f000 f917 bl 8008efa <HAL_PCD_EP_DB_Transmit>
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8008ccc: 687b ldr r3, [r7, #4]
8008cce: 681b ldr r3, [r3, #0]
8008cd0: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
8008cd4: b29b uxth r3, r3
8008cd6: b21b sxth r3, r3
8008cd8: 2b00 cmp r3, #0
8008cda: f6ff ac82 blt.w 80085e2 <PCD_EP_ISR_Handler+0xa>
}
}
}
}
return HAL_OK;
8008cde: 2300 movs r3, #0
}
8008ce0: 4618 mov r0, r3
8008ce2: 3750 adds r7, #80 @ 0x50
8008ce4: 46bd mov sp, r7
8008ce6: bd80 pop {r7, pc}
08008ce8 <HAL_PCD_EP_DB_Receive>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
8008ce8: b580 push {r7, lr}
8008cea: b088 sub sp, #32
8008cec: af00 add r7, sp, #0
8008cee: 60f8 str r0, [r7, #12]
8008cf0: 60b9 str r1, [r7, #8]
8008cf2: 4613 mov r3, r2
8008cf4: 80fb strh r3, [r7, #6]
uint16_t count;
/* Manage Buffer0 OUT */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
8008cf6: 88fb ldrh r3, [r7, #6]
8008cf8: f403 4380 and.w r3, r3, #16384 @ 0x4000
8008cfc: 2b00 cmp r3, #0
8008cfe: d07c beq.n 8008dfa <HAL_PCD_EP_DB_Receive+0x112>
{
/* Get count of received Data on buffer0 */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8008d00: 68fb ldr r3, [r7, #12]
8008d02: 681b ldr r3, [r3, #0]
8008d04: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008d08: b29b uxth r3, r3
8008d0a: 461a mov r2, r3
8008d0c: 68bb ldr r3, [r7, #8]
8008d0e: 781b ldrb r3, [r3, #0]
8008d10: 00db lsls r3, r3, #3
8008d12: 4413 add r3, r2
8008d14: 68fa ldr r2, [r7, #12]
8008d16: 6812 ldr r2, [r2, #0]
8008d18: 4413 add r3, r2
8008d1a: f203 4302 addw r3, r3, #1026 @ 0x402
8008d1e: 881b ldrh r3, [r3, #0]
8008d20: f3c3 0309 ubfx r3, r3, #0, #10
8008d24: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
8008d26: 68bb ldr r3, [r7, #8]
8008d28: 699a ldr r2, [r3, #24]
8008d2a: 8b7b ldrh r3, [r7, #26]
8008d2c: 429a cmp r2, r3
8008d2e: d306 bcc.n 8008d3e <HAL_PCD_EP_DB_Receive+0x56>
{
ep->xfer_len -= count;
8008d30: 68bb ldr r3, [r7, #8]
8008d32: 699a ldr r2, [r3, #24]
8008d34: 8b7b ldrh r3, [r7, #26]
8008d36: 1ad2 subs r2, r2, r3
8008d38: 68bb ldr r3, [r7, #8]
8008d3a: 619a str r2, [r3, #24]
8008d3c: e002 b.n 8008d44 <HAL_PCD_EP_DB_Receive+0x5c>
}
else
{
ep->xfer_len = 0U;
8008d3e: 68bb ldr r3, [r7, #8]
8008d40: 2200 movs r2, #0
8008d42: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
8008d44: 68bb ldr r3, [r7, #8]
8008d46: 699b ldr r3, [r3, #24]
8008d48: 2b00 cmp r3, #0
8008d4a: d123 bne.n 8008d94 <HAL_PCD_EP_DB_Receive+0xac>
{
/* Set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
8008d4c: 68fb ldr r3, [r7, #12]
8008d4e: 681b ldr r3, [r3, #0]
8008d50: 461a mov r2, r3
8008d52: 68bb ldr r3, [r7, #8]
8008d54: 781b ldrb r3, [r3, #0]
8008d56: 009b lsls r3, r3, #2
8008d58: 4413 add r3, r2
8008d5a: 881b ldrh r3, [r3, #0]
8008d5c: b29b uxth r3, r3
8008d5e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008d62: f023 0370 bic.w r3, r3, #112 @ 0x70
8008d66: 833b strh r3, [r7, #24]
8008d68: 8b3b ldrh r3, [r7, #24]
8008d6a: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008d6e: 833b strh r3, [r7, #24]
8008d70: 68fb ldr r3, [r7, #12]
8008d72: 681b ldr r3, [r3, #0]
8008d74: 461a mov r2, r3
8008d76: 68bb ldr r3, [r7, #8]
8008d78: 781b ldrb r3, [r3, #0]
8008d7a: 009b lsls r3, r3, #2
8008d7c: 441a add r2, r3
8008d7e: 8b3b ldrh r3, [r7, #24]
8008d80: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008d84: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008d88: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008d8c: f043 0380 orr.w r3, r3, #128 @ 0x80
8008d90: b29b uxth r3, r3
8008d92: 8013 strh r3, [r2, #0]
}
/* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8008d94: 88fb ldrh r3, [r7, #6]
8008d96: f003 0340 and.w r3, r3, #64 @ 0x40
8008d9a: 2b00 cmp r3, #0
8008d9c: d01f beq.n 8008dde <HAL_PCD_EP_DB_Receive+0xf6>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
8008d9e: 68fb ldr r3, [r7, #12]
8008da0: 681b ldr r3, [r3, #0]
8008da2: 461a mov r2, r3
8008da4: 68bb ldr r3, [r7, #8]
8008da6: 781b ldrb r3, [r3, #0]
8008da8: 009b lsls r3, r3, #2
8008daa: 4413 add r3, r2
8008dac: 881b ldrh r3, [r3, #0]
8008dae: b29b uxth r3, r3
8008db0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008db4: f023 0370 bic.w r3, r3, #112 @ 0x70
8008db8: 82fb strh r3, [r7, #22]
8008dba: 68fb ldr r3, [r7, #12]
8008dbc: 681b ldr r3, [r3, #0]
8008dbe: 461a mov r2, r3
8008dc0: 68bb ldr r3, [r7, #8]
8008dc2: 781b ldrb r3, [r3, #0]
8008dc4: 009b lsls r3, r3, #2
8008dc6: 441a add r2, r3
8008dc8: 8afb ldrh r3, [r7, #22]
8008dca: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008dce: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008dd2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008dd6: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8008dda: b29b uxth r3, r3
8008ddc: 8013 strh r3, [r2, #0]
}
if (count != 0U)
8008dde: 8b7b ldrh r3, [r7, #26]
8008de0: 2b00 cmp r3, #0
8008de2: f000 8085 beq.w 8008ef0 <HAL_PCD_EP_DB_Receive+0x208>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
8008de6: 68fb ldr r3, [r7, #12]
8008de8: 6818 ldr r0, [r3, #0]
8008dea: 68bb ldr r3, [r7, #8]
8008dec: 6959 ldr r1, [r3, #20]
8008dee: 68bb ldr r3, [r7, #8]
8008df0: 891a ldrh r2, [r3, #8]
8008df2: 8b7b ldrh r3, [r7, #26]
8008df4: f006 fa98 bl 800f328 <USB_ReadPMA>
8008df8: e07a b.n 8008ef0 <HAL_PCD_EP_DB_Receive+0x208>
}
/* Manage Buffer 1 DTOG_RX=0 */
else
{
/* Get count of received data */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8008dfa: 68fb ldr r3, [r7, #12]
8008dfc: 681b ldr r3, [r3, #0]
8008dfe: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008e02: b29b uxth r3, r3
8008e04: 461a mov r2, r3
8008e06: 68bb ldr r3, [r7, #8]
8008e08: 781b ldrb r3, [r3, #0]
8008e0a: 00db lsls r3, r3, #3
8008e0c: 4413 add r3, r2
8008e0e: 68fa ldr r2, [r7, #12]
8008e10: 6812 ldr r2, [r2, #0]
8008e12: 4413 add r3, r2
8008e14: f203 4306 addw r3, r3, #1030 @ 0x406
8008e18: 881b ldrh r3, [r3, #0]
8008e1a: f3c3 0309 ubfx r3, r3, #0, #10
8008e1e: 837b strh r3, [r7, #26]
if (ep->xfer_len >= count)
8008e20: 68bb ldr r3, [r7, #8]
8008e22: 699a ldr r2, [r3, #24]
8008e24: 8b7b ldrh r3, [r7, #26]
8008e26: 429a cmp r2, r3
8008e28: d306 bcc.n 8008e38 <HAL_PCD_EP_DB_Receive+0x150>
{
ep->xfer_len -= count;
8008e2a: 68bb ldr r3, [r7, #8]
8008e2c: 699a ldr r2, [r3, #24]
8008e2e: 8b7b ldrh r3, [r7, #26]
8008e30: 1ad2 subs r2, r2, r3
8008e32: 68bb ldr r3, [r7, #8]
8008e34: 619a str r2, [r3, #24]
8008e36: e002 b.n 8008e3e <HAL_PCD_EP_DB_Receive+0x156>
}
else
{
ep->xfer_len = 0U;
8008e38: 68bb ldr r3, [r7, #8]
8008e3a: 2200 movs r2, #0
8008e3c: 619a str r2, [r3, #24]
}
if (ep->xfer_len == 0U)
8008e3e: 68bb ldr r3, [r7, #8]
8008e40: 699b ldr r3, [r3, #24]
8008e42: 2b00 cmp r3, #0
8008e44: d123 bne.n 8008e8e <HAL_PCD_EP_DB_Receive+0x1a6>
{
/* Set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
8008e46: 68fb ldr r3, [r7, #12]
8008e48: 681b ldr r3, [r3, #0]
8008e4a: 461a mov r2, r3
8008e4c: 68bb ldr r3, [r7, #8]
8008e4e: 781b ldrb r3, [r3, #0]
8008e50: 009b lsls r3, r3, #2
8008e52: 4413 add r3, r2
8008e54: 881b ldrh r3, [r3, #0]
8008e56: b29b uxth r3, r3
8008e58: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008e5c: f023 0370 bic.w r3, r3, #112 @ 0x70
8008e60: 83fb strh r3, [r7, #30]
8008e62: 8bfb ldrh r3, [r7, #30]
8008e64: f483 5300 eor.w r3, r3, #8192 @ 0x2000
8008e68: 83fb strh r3, [r7, #30]
8008e6a: 68fb ldr r3, [r7, #12]
8008e6c: 681b ldr r3, [r3, #0]
8008e6e: 461a mov r2, r3
8008e70: 68bb ldr r3, [r7, #8]
8008e72: 781b ldrb r3, [r3, #0]
8008e74: 009b lsls r3, r3, #2
8008e76: 441a add r2, r3
8008e78: 8bfb ldrh r3, [r7, #30]
8008e7a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008e7e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008e82: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008e86: f043 0380 orr.w r3, r3, #128 @ 0x80
8008e8a: b29b uxth r3, r3
8008e8c: 8013 strh r3, [r2, #0]
}
/* Need to FreeUser Buffer */
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
8008e8e: 88fb ldrh r3, [r7, #6]
8008e90: f003 0340 and.w r3, r3, #64 @ 0x40
8008e94: 2b00 cmp r3, #0
8008e96: d11f bne.n 8008ed8 <HAL_PCD_EP_DB_Receive+0x1f0>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
8008e98: 68fb ldr r3, [r7, #12]
8008e9a: 681b ldr r3, [r3, #0]
8008e9c: 461a mov r2, r3
8008e9e: 68bb ldr r3, [r7, #8]
8008ea0: 781b ldrb r3, [r3, #0]
8008ea2: 009b lsls r3, r3, #2
8008ea4: 4413 add r3, r2
8008ea6: 881b ldrh r3, [r3, #0]
8008ea8: b29b uxth r3, r3
8008eaa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008eae: f023 0370 bic.w r3, r3, #112 @ 0x70
8008eb2: 83bb strh r3, [r7, #28]
8008eb4: 68fb ldr r3, [r7, #12]
8008eb6: 681b ldr r3, [r3, #0]
8008eb8: 461a mov r2, r3
8008eba: 68bb ldr r3, [r7, #8]
8008ebc: 781b ldrb r3, [r3, #0]
8008ebe: 009b lsls r3, r3, #2
8008ec0: 441a add r2, r3
8008ec2: 8bbb ldrh r3, [r7, #28]
8008ec4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8008ec8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8008ecc: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8008ed0: f043 03c0 orr.w r3, r3, #192 @ 0xc0
8008ed4: b29b uxth r3, r3
8008ed6: 8013 strh r3, [r2, #0]
}
if (count != 0U)
8008ed8: 8b7b ldrh r3, [r7, #26]
8008eda: 2b00 cmp r3, #0
8008edc: d008 beq.n 8008ef0 <HAL_PCD_EP_DB_Receive+0x208>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8008ede: 68fb ldr r3, [r7, #12]
8008ee0: 6818 ldr r0, [r3, #0]
8008ee2: 68bb ldr r3, [r7, #8]
8008ee4: 6959 ldr r1, [r3, #20]
8008ee6: 68bb ldr r3, [r7, #8]
8008ee8: 895a ldrh r2, [r3, #10]
8008eea: 8b7b ldrh r3, [r7, #26]
8008eec: f006 fa1c bl 800f328 <USB_ReadPMA>
}
}
return count;
8008ef0: 8b7b ldrh r3, [r7, #26]
}
8008ef2: 4618 mov r0, r3
8008ef4: 3720 adds r7, #32
8008ef6: 46bd mov sp, r7
8008ef8: bd80 pop {r7, pc}
08008efa <HAL_PCD_EP_DB_Transmit>:
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
8008efa: b580 push {r7, lr}
8008efc: b0a6 sub sp, #152 @ 0x98
8008efe: af00 add r7, sp, #0
8008f00: 60f8 str r0, [r7, #12]
8008f02: 60b9 str r1, [r7, #8]
8008f04: 4613 mov r3, r2
8008f06: 80fb strh r3, [r7, #6]
uint32_t len;
uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
8008f08: 88fb ldrh r3, [r7, #6]
8008f0a: f003 0340 and.w r3, r3, #64 @ 0x40
8008f0e: 2b00 cmp r3, #0
8008f10: f000 81f7 beq.w 8009302 <HAL_PCD_EP_DB_Transmit+0x408>
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8008f14: 68fb ldr r3, [r7, #12]
8008f16: 681b ldr r3, [r3, #0]
8008f18: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008f1c: b29b uxth r3, r3
8008f1e: 461a mov r2, r3
8008f20: 68bb ldr r3, [r7, #8]
8008f22: 781b ldrb r3, [r3, #0]
8008f24: 00db lsls r3, r3, #3
8008f26: 4413 add r3, r2
8008f28: 68fa ldr r2, [r7, #12]
8008f2a: 6812 ldr r2, [r2, #0]
8008f2c: 4413 add r3, r2
8008f2e: f203 4302 addw r3, r3, #1026 @ 0x402
8008f32: 881b ldrh r3, [r3, #0]
8008f34: f3c3 0309 ubfx r3, r3, #0, #10
8008f38: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
if (ep->xfer_len > TxPctSize)
8008f3c: 68bb ldr r3, [r7, #8]
8008f3e: 699a ldr r2, [r3, #24]
8008f40: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8008f44: 429a cmp r2, r3
8008f46: d907 bls.n 8008f58 <HAL_PCD_EP_DB_Transmit+0x5e>
{
ep->xfer_len -= TxPctSize;
8008f48: 68bb ldr r3, [r7, #8]
8008f4a: 699a ldr r2, [r3, #24]
8008f4c: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8008f50: 1ad2 subs r2, r2, r3
8008f52: 68bb ldr r3, [r7, #8]
8008f54: 619a str r2, [r3, #24]
8008f56: e002 b.n 8008f5e <HAL_PCD_EP_DB_Transmit+0x64>
}
else
{
ep->xfer_len = 0U;
8008f58: 68bb ldr r3, [r7, #8]
8008f5a: 2200 movs r2, #0
8008f5c: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
8008f5e: 68bb ldr r3, [r7, #8]
8008f60: 699b ldr r3, [r3, #24]
8008f62: 2b00 cmp r3, #0
8008f64: f040 80e1 bne.w 800912a <HAL_PCD_EP_DB_Transmit+0x230>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8008f68: 68bb ldr r3, [r7, #8]
8008f6a: 785b ldrb r3, [r3, #1]
8008f6c: 2b00 cmp r3, #0
8008f6e: d126 bne.n 8008fbe <HAL_PCD_EP_DB_Transmit+0xc4>
8008f70: 68fb ldr r3, [r7, #12]
8008f72: 681b ldr r3, [r3, #0]
8008f74: 633b str r3, [r7, #48] @ 0x30
8008f76: 68fb ldr r3, [r7, #12]
8008f78: 681b ldr r3, [r3, #0]
8008f7a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008f7e: b29b uxth r3, r3
8008f80: 461a mov r2, r3
8008f82: 6b3b ldr r3, [r7, #48] @ 0x30
8008f84: 4413 add r3, r2
8008f86: 633b str r3, [r7, #48] @ 0x30
8008f88: 68bb ldr r3, [r7, #8]
8008f8a: 781b ldrb r3, [r3, #0]
8008f8c: 00da lsls r2, r3, #3
8008f8e: 6b3b ldr r3, [r7, #48] @ 0x30
8008f90: 4413 add r3, r2
8008f92: f203 4302 addw r3, r3, #1026 @ 0x402
8008f96: 62fb str r3, [r7, #44] @ 0x2c
8008f98: 6afb ldr r3, [r7, #44] @ 0x2c
8008f9a: 881b ldrh r3, [r3, #0]
8008f9c: b29b uxth r3, r3
8008f9e: f3c3 0309 ubfx r3, r3, #0, #10
8008fa2: b29a uxth r2, r3
8008fa4: 6afb ldr r3, [r7, #44] @ 0x2c
8008fa6: 801a strh r2, [r3, #0]
8008fa8: 6afb ldr r3, [r7, #44] @ 0x2c
8008faa: 881b ldrh r3, [r3, #0]
8008fac: b29b uxth r3, r3
8008fae: ea6f 4343 mvn.w r3, r3, lsl #17
8008fb2: ea6f 4353 mvn.w r3, r3, lsr #17
8008fb6: b29a uxth r2, r3
8008fb8: 6afb ldr r3, [r7, #44] @ 0x2c
8008fba: 801a strh r2, [r3, #0]
8008fbc: e01a b.n 8008ff4 <HAL_PCD_EP_DB_Transmit+0xfa>
8008fbe: 68bb ldr r3, [r7, #8]
8008fc0: 785b ldrb r3, [r3, #1]
8008fc2: 2b01 cmp r3, #1
8008fc4: d116 bne.n 8008ff4 <HAL_PCD_EP_DB_Transmit+0xfa>
8008fc6: 68fb ldr r3, [r7, #12]
8008fc8: 681b ldr r3, [r3, #0]
8008fca: 63bb str r3, [r7, #56] @ 0x38
8008fcc: 68fb ldr r3, [r7, #12]
8008fce: 681b ldr r3, [r3, #0]
8008fd0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8008fd4: b29b uxth r3, r3
8008fd6: 461a mov r2, r3
8008fd8: 6bbb ldr r3, [r7, #56] @ 0x38
8008fda: 4413 add r3, r2
8008fdc: 63bb str r3, [r7, #56] @ 0x38
8008fde: 68bb ldr r3, [r7, #8]
8008fe0: 781b ldrb r3, [r3, #0]
8008fe2: 00da lsls r2, r3, #3
8008fe4: 6bbb ldr r3, [r7, #56] @ 0x38
8008fe6: 4413 add r3, r2
8008fe8: f203 4302 addw r3, r3, #1026 @ 0x402
8008fec: 637b str r3, [r7, #52] @ 0x34
8008fee: 6b7b ldr r3, [r7, #52] @ 0x34
8008ff0: 2200 movs r2, #0
8008ff2: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8008ff4: 68fb ldr r3, [r7, #12]
8008ff6: 681b ldr r3, [r3, #0]
8008ff8: 62bb str r3, [r7, #40] @ 0x28
8008ffa: 68bb ldr r3, [r7, #8]
8008ffc: 785b ldrb r3, [r3, #1]
8008ffe: 2b00 cmp r3, #0
8009000: d126 bne.n 8009050 <HAL_PCD_EP_DB_Transmit+0x156>
8009002: 68fb ldr r3, [r7, #12]
8009004: 681b ldr r3, [r3, #0]
8009006: 623b str r3, [r7, #32]
8009008: 68fb ldr r3, [r7, #12]
800900a: 681b ldr r3, [r3, #0]
800900c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009010: b29b uxth r3, r3
8009012: 461a mov r2, r3
8009014: 6a3b ldr r3, [r7, #32]
8009016: 4413 add r3, r2
8009018: 623b str r3, [r7, #32]
800901a: 68bb ldr r3, [r7, #8]
800901c: 781b ldrb r3, [r3, #0]
800901e: 00da lsls r2, r3, #3
8009020: 6a3b ldr r3, [r7, #32]
8009022: 4413 add r3, r2
8009024: f203 4306 addw r3, r3, #1030 @ 0x406
8009028: 61fb str r3, [r7, #28]
800902a: 69fb ldr r3, [r7, #28]
800902c: 881b ldrh r3, [r3, #0]
800902e: b29b uxth r3, r3
8009030: f3c3 0309 ubfx r3, r3, #0, #10
8009034: b29a uxth r2, r3
8009036: 69fb ldr r3, [r7, #28]
8009038: 801a strh r2, [r3, #0]
800903a: 69fb ldr r3, [r7, #28]
800903c: 881b ldrh r3, [r3, #0]
800903e: b29b uxth r3, r3
8009040: ea6f 4343 mvn.w r3, r3, lsl #17
8009044: ea6f 4353 mvn.w r3, r3, lsr #17
8009048: b29a uxth r2, r3
800904a: 69fb ldr r3, [r7, #28]
800904c: 801a strh r2, [r3, #0]
800904e: e017 b.n 8009080 <HAL_PCD_EP_DB_Transmit+0x186>
8009050: 68bb ldr r3, [r7, #8]
8009052: 785b ldrb r3, [r3, #1]
8009054: 2b01 cmp r3, #1
8009056: d113 bne.n 8009080 <HAL_PCD_EP_DB_Transmit+0x186>
8009058: 68fb ldr r3, [r7, #12]
800905a: 681b ldr r3, [r3, #0]
800905c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009060: b29b uxth r3, r3
8009062: 461a mov r2, r3
8009064: 6abb ldr r3, [r7, #40] @ 0x28
8009066: 4413 add r3, r2
8009068: 62bb str r3, [r7, #40] @ 0x28
800906a: 68bb ldr r3, [r7, #8]
800906c: 781b ldrb r3, [r3, #0]
800906e: 00da lsls r2, r3, #3
8009070: 6abb ldr r3, [r7, #40] @ 0x28
8009072: 4413 add r3, r2
8009074: f203 4306 addw r3, r3, #1030 @ 0x406
8009078: 627b str r3, [r7, #36] @ 0x24
800907a: 6a7b ldr r3, [r7, #36] @ 0x24
800907c: 2200 movs r2, #0
800907e: 801a strh r2, [r3, #0]
if (ep->type == EP_TYPE_BULK)
8009080: 68bb ldr r3, [r7, #8]
8009082: 78db ldrb r3, [r3, #3]
8009084: 2b02 cmp r3, #2
8009086: d123 bne.n 80090d0 <HAL_PCD_EP_DB_Transmit+0x1d6>
{
/* Set Bulk endpoint in NAK state */
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
8009088: 68fb ldr r3, [r7, #12]
800908a: 681b ldr r3, [r3, #0]
800908c: 461a mov r2, r3
800908e: 68bb ldr r3, [r7, #8]
8009090: 781b ldrb r3, [r3, #0]
8009092: 009b lsls r3, r3, #2
8009094: 4413 add r3, r2
8009096: 881b ldrh r3, [r3, #0]
8009098: b29b uxth r3, r3
800909a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800909e: f023 0340 bic.w r3, r3, #64 @ 0x40
80090a2: 837b strh r3, [r7, #26]
80090a4: 8b7b ldrh r3, [r7, #26]
80090a6: f083 0320 eor.w r3, r3, #32
80090aa: 837b strh r3, [r7, #26]
80090ac: 68fb ldr r3, [r7, #12]
80090ae: 681b ldr r3, [r3, #0]
80090b0: 461a mov r2, r3
80090b2: 68bb ldr r3, [r7, #8]
80090b4: 781b ldrb r3, [r3, #0]
80090b6: 009b lsls r3, r3, #2
80090b8: 441a add r2, r3
80090ba: 8b7b ldrh r3, [r7, #26]
80090bc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80090c0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80090c4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80090c8: f043 0380 orr.w r3, r3, #128 @ 0x80
80090cc: b29b uxth r3, r3
80090ce: 8013 strh r3, [r2, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
80090d0: 68bb ldr r3, [r7, #8]
80090d2: 781b ldrb r3, [r3, #0]
80090d4: 4619 mov r1, r3
80090d6: 68f8 ldr r0, [r7, #12]
80090d8: f00e f909 bl 80172ee <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
80090dc: 88fb ldrh r3, [r7, #6]
80090de: f403 4380 and.w r3, r3, #16384 @ 0x4000
80090e2: 2b00 cmp r3, #0
80090e4: d01f beq.n 8009126 <HAL_PCD_EP_DB_Transmit+0x22c>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
80090e6: 68fb ldr r3, [r7, #12]
80090e8: 681b ldr r3, [r3, #0]
80090ea: 461a mov r2, r3
80090ec: 68bb ldr r3, [r7, #8]
80090ee: 781b ldrb r3, [r3, #0]
80090f0: 009b lsls r3, r3, #2
80090f2: 4413 add r3, r2
80090f4: 881b ldrh r3, [r3, #0]
80090f6: b29b uxth r3, r3
80090f8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80090fc: f023 0370 bic.w r3, r3, #112 @ 0x70
8009100: 833b strh r3, [r7, #24]
8009102: 68fb ldr r3, [r7, #12]
8009104: 681b ldr r3, [r3, #0]
8009106: 461a mov r2, r3
8009108: 68bb ldr r3, [r7, #8]
800910a: 781b ldrb r3, [r3, #0]
800910c: 009b lsls r3, r3, #2
800910e: 441a add r2, r3
8009110: 8b3b ldrh r3, [r7, #24]
8009112: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8009116: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800911a: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800911e: f043 0380 orr.w r3, r3, #128 @ 0x80
8009122: b29b uxth r3, r3
8009124: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8009126: 2300 movs r3, #0
8009128: e31f b.n 800976a <HAL_PCD_EP_DB_Transmit+0x870>
}
else /* Transfer is not yet Done */
{
/* Need to Free USB Buffer */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
800912a: 88fb ldrh r3, [r7, #6]
800912c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8009130: 2b00 cmp r3, #0
8009132: d021 beq.n 8009178 <HAL_PCD_EP_DB_Transmit+0x27e>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
8009134: 68fb ldr r3, [r7, #12]
8009136: 681b ldr r3, [r3, #0]
8009138: 461a mov r2, r3
800913a: 68bb ldr r3, [r7, #8]
800913c: 781b ldrb r3, [r3, #0]
800913e: 009b lsls r3, r3, #2
8009140: 4413 add r3, r2
8009142: 881b ldrh r3, [r3, #0]
8009144: b29b uxth r3, r3
8009146: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800914a: f023 0370 bic.w r3, r3, #112 @ 0x70
800914e: f8a7 304e strh.w r3, [r7, #78] @ 0x4e
8009152: 68fb ldr r3, [r7, #12]
8009154: 681b ldr r3, [r3, #0]
8009156: 461a mov r2, r3
8009158: 68bb ldr r3, [r7, #8]
800915a: 781b ldrb r3, [r3, #0]
800915c: 009b lsls r3, r3, #2
800915e: 441a add r2, r3
8009160: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e
8009164: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8009168: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800916c: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8009170: f043 0380 orr.w r3, r3, #128 @ 0x80
8009174: b29b uxth r3, r3
8009176: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
8009178: 68bb ldr r3, [r7, #8]
800917a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
800917e: 2b01 cmp r3, #1
8009180: f040 82ca bne.w 8009718 <HAL_PCD_EP_DB_Transmit+0x81e>
{
ep->xfer_buff += TxPctSize;
8009184: 68bb ldr r3, [r7, #8]
8009186: 695a ldr r2, [r3, #20]
8009188: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
800918c: 441a add r2, r3
800918e: 68bb ldr r3, [r7, #8]
8009190: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
8009192: 68bb ldr r3, [r7, #8]
8009194: 69da ldr r2, [r3, #28]
8009196: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
800919a: 441a add r2, r3
800919c: 68bb ldr r3, [r7, #8]
800919e: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
80091a0: 68bb ldr r3, [r7, #8]
80091a2: 6a1a ldr r2, [r3, #32]
80091a4: 68bb ldr r3, [r7, #8]
80091a6: 691b ldr r3, [r3, #16]
80091a8: 429a cmp r2, r3
80091aa: d309 bcc.n 80091c0 <HAL_PCD_EP_DB_Transmit+0x2c6>
{
len = ep->maxpacket;
80091ac: 68bb ldr r3, [r7, #8]
80091ae: 691b ldr r3, [r3, #16]
80091b0: 65bb str r3, [r7, #88] @ 0x58
ep->xfer_len_db -= len;
80091b2: 68bb ldr r3, [r7, #8]
80091b4: 6a1a ldr r2, [r3, #32]
80091b6: 6dbb ldr r3, [r7, #88] @ 0x58
80091b8: 1ad2 subs r2, r2, r3
80091ba: 68bb ldr r3, [r7, #8]
80091bc: 621a str r2, [r3, #32]
80091be: e015 b.n 80091ec <HAL_PCD_EP_DB_Transmit+0x2f2>
}
else if (ep->xfer_len_db == 0U)
80091c0: 68bb ldr r3, [r7, #8]
80091c2: 6a1b ldr r3, [r3, #32]
80091c4: 2b00 cmp r3, #0
80091c6: d107 bne.n 80091d8 <HAL_PCD_EP_DB_Transmit+0x2de>
{
len = TxPctSize;
80091c8: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80091cc: 65bb str r3, [r7, #88] @ 0x58
ep->xfer_fill_db = 0U;
80091ce: 68bb ldr r3, [r7, #8]
80091d0: 2200 movs r2, #0
80091d2: f883 2024 strb.w r2, [r3, #36] @ 0x24
80091d6: e009 b.n 80091ec <HAL_PCD_EP_DB_Transmit+0x2f2>
}
else
{
ep->xfer_fill_db = 0U;
80091d8: 68bb ldr r3, [r7, #8]
80091da: 2200 movs r2, #0
80091dc: f883 2024 strb.w r2, [r3, #36] @ 0x24
len = ep->xfer_len_db;
80091e0: 68bb ldr r3, [r7, #8]
80091e2: 6a1b ldr r3, [r3, #32]
80091e4: 65bb str r3, [r7, #88] @ 0x58
ep->xfer_len_db = 0U;
80091e6: 68bb ldr r3, [r7, #8]
80091e8: 2200 movs r2, #0
80091ea: 621a str r2, [r3, #32]
}
/* Write remaining Data to Buffer */
/* Set the Double buffer counter for pma buffer0 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
80091ec: 68bb ldr r3, [r7, #8]
80091ee: 785b ldrb r3, [r3, #1]
80091f0: 2b00 cmp r3, #0
80091f2: d15f bne.n 80092b4 <HAL_PCD_EP_DB_Transmit+0x3ba>
80091f4: 68fb ldr r3, [r7, #12]
80091f6: 681b ldr r3, [r3, #0]
80091f8: 643b str r3, [r7, #64] @ 0x40
80091fa: 68fb ldr r3, [r7, #12]
80091fc: 681b ldr r3, [r3, #0]
80091fe: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009202: b29b uxth r3, r3
8009204: 461a mov r2, r3
8009206: 6c3b ldr r3, [r7, #64] @ 0x40
8009208: 4413 add r3, r2
800920a: 643b str r3, [r7, #64] @ 0x40
800920c: 68bb ldr r3, [r7, #8]
800920e: 781b ldrb r3, [r3, #0]
8009210: 00da lsls r2, r3, #3
8009212: 6c3b ldr r3, [r7, #64] @ 0x40
8009214: 4413 add r3, r2
8009216: f203 4302 addw r3, r3, #1026 @ 0x402
800921a: 63fb str r3, [r7, #60] @ 0x3c
800921c: 6bfb ldr r3, [r7, #60] @ 0x3c
800921e: 881b ldrh r3, [r3, #0]
8009220: b29b uxth r3, r3
8009222: f3c3 0309 ubfx r3, r3, #0, #10
8009226: b29a uxth r2, r3
8009228: 6bfb ldr r3, [r7, #60] @ 0x3c
800922a: 801a strh r2, [r3, #0]
800922c: 6dbb ldr r3, [r7, #88] @ 0x58
800922e: 2b00 cmp r3, #0
8009230: d10a bne.n 8009248 <HAL_PCD_EP_DB_Transmit+0x34e>
8009232: 6bfb ldr r3, [r7, #60] @ 0x3c
8009234: 881b ldrh r3, [r3, #0]
8009236: b29b uxth r3, r3
8009238: ea6f 4343 mvn.w r3, r3, lsl #17
800923c: ea6f 4353 mvn.w r3, r3, lsr #17
8009240: b29a uxth r2, r3
8009242: 6bfb ldr r3, [r7, #60] @ 0x3c
8009244: 801a strh r2, [r3, #0]
8009246: e051 b.n 80092ec <HAL_PCD_EP_DB_Transmit+0x3f2>
8009248: 6dbb ldr r3, [r7, #88] @ 0x58
800924a: 2b3e cmp r3, #62 @ 0x3e
800924c: d816 bhi.n 800927c <HAL_PCD_EP_DB_Transmit+0x382>
800924e: 6dbb ldr r3, [r7, #88] @ 0x58
8009250: 085b lsrs r3, r3, #1
8009252: 653b str r3, [r7, #80] @ 0x50
8009254: 6dbb ldr r3, [r7, #88] @ 0x58
8009256: f003 0301 and.w r3, r3, #1
800925a: 2b00 cmp r3, #0
800925c: d002 beq.n 8009264 <HAL_PCD_EP_DB_Transmit+0x36a>
800925e: 6d3b ldr r3, [r7, #80] @ 0x50
8009260: 3301 adds r3, #1
8009262: 653b str r3, [r7, #80] @ 0x50
8009264: 6bfb ldr r3, [r7, #60] @ 0x3c
8009266: 881b ldrh r3, [r3, #0]
8009268: b29a uxth r2, r3
800926a: 6d3b ldr r3, [r7, #80] @ 0x50
800926c: b29b uxth r3, r3
800926e: 029b lsls r3, r3, #10
8009270: b29b uxth r3, r3
8009272: 4313 orrs r3, r2
8009274: b29a uxth r2, r3
8009276: 6bfb ldr r3, [r7, #60] @ 0x3c
8009278: 801a strh r2, [r3, #0]
800927a: e037 b.n 80092ec <HAL_PCD_EP_DB_Transmit+0x3f2>
800927c: 6dbb ldr r3, [r7, #88] @ 0x58
800927e: 095b lsrs r3, r3, #5
8009280: 653b str r3, [r7, #80] @ 0x50
8009282: 6dbb ldr r3, [r7, #88] @ 0x58
8009284: f003 031f and.w r3, r3, #31
8009288: 2b00 cmp r3, #0
800928a: d102 bne.n 8009292 <HAL_PCD_EP_DB_Transmit+0x398>
800928c: 6d3b ldr r3, [r7, #80] @ 0x50
800928e: 3b01 subs r3, #1
8009290: 653b str r3, [r7, #80] @ 0x50
8009292: 6bfb ldr r3, [r7, #60] @ 0x3c
8009294: 881b ldrh r3, [r3, #0]
8009296: b29a uxth r2, r3
8009298: 6d3b ldr r3, [r7, #80] @ 0x50
800929a: b29b uxth r3, r3
800929c: 029b lsls r3, r3, #10
800929e: b29b uxth r3, r3
80092a0: 4313 orrs r3, r2
80092a2: b29b uxth r3, r3
80092a4: ea6f 4343 mvn.w r3, r3, lsl #17
80092a8: ea6f 4353 mvn.w r3, r3, lsr #17
80092ac: b29a uxth r2, r3
80092ae: 6bfb ldr r3, [r7, #60] @ 0x3c
80092b0: 801a strh r2, [r3, #0]
80092b2: e01b b.n 80092ec <HAL_PCD_EP_DB_Transmit+0x3f2>
80092b4: 68bb ldr r3, [r7, #8]
80092b6: 785b ldrb r3, [r3, #1]
80092b8: 2b01 cmp r3, #1
80092ba: d117 bne.n 80092ec <HAL_PCD_EP_DB_Transmit+0x3f2>
80092bc: 68fb ldr r3, [r7, #12]
80092be: 681b ldr r3, [r3, #0]
80092c0: 64bb str r3, [r7, #72] @ 0x48
80092c2: 68fb ldr r3, [r7, #12]
80092c4: 681b ldr r3, [r3, #0]
80092c6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80092ca: b29b uxth r3, r3
80092cc: 461a mov r2, r3
80092ce: 6cbb ldr r3, [r7, #72] @ 0x48
80092d0: 4413 add r3, r2
80092d2: 64bb str r3, [r7, #72] @ 0x48
80092d4: 68bb ldr r3, [r7, #8]
80092d6: 781b ldrb r3, [r3, #0]
80092d8: 00da lsls r2, r3, #3
80092da: 6cbb ldr r3, [r7, #72] @ 0x48
80092dc: 4413 add r3, r2
80092de: f203 4302 addw r3, r3, #1026 @ 0x402
80092e2: 647b str r3, [r7, #68] @ 0x44
80092e4: 6dbb ldr r3, [r7, #88] @ 0x58
80092e6: b29a uxth r2, r3
80092e8: 6c7b ldr r3, [r7, #68] @ 0x44
80092ea: 801a strh r2, [r3, #0]
/* Copy user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
80092ec: 68fb ldr r3, [r7, #12]
80092ee: 6818 ldr r0, [r3, #0]
80092f0: 68bb ldr r3, [r7, #8]
80092f2: 6959 ldr r1, [r3, #20]
80092f4: 68bb ldr r3, [r7, #8]
80092f6: 891a ldrh r2, [r3, #8]
80092f8: 6dbb ldr r3, [r7, #88] @ 0x58
80092fa: b29b uxth r3, r3
80092fc: f005 ffd1 bl 800f2a2 <USB_WritePMA>
8009300: e20a b.n 8009718 <HAL_PCD_EP_DB_Transmit+0x81e>
}
}
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8009302: 68fb ldr r3, [r7, #12]
8009304: 681b ldr r3, [r3, #0]
8009306: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800930a: b29b uxth r3, r3
800930c: 461a mov r2, r3
800930e: 68bb ldr r3, [r7, #8]
8009310: 781b ldrb r3, [r3, #0]
8009312: 00db lsls r3, r3, #3
8009314: 4413 add r3, r2
8009316: 68fa ldr r2, [r7, #12]
8009318: 6812 ldr r2, [r2, #0]
800931a: 4413 add r3, r2
800931c: f203 4306 addw r3, r3, #1030 @ 0x406
8009320: 881b ldrh r3, [r3, #0]
8009322: f3c3 0309 ubfx r3, r3, #0, #10
8009326: f8a7 3096 strh.w r3, [r7, #150] @ 0x96
if (ep->xfer_len >= TxPctSize)
800932a: 68bb ldr r3, [r7, #8]
800932c: 699a ldr r2, [r3, #24]
800932e: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
8009332: 429a cmp r2, r3
8009334: d307 bcc.n 8009346 <HAL_PCD_EP_DB_Transmit+0x44c>
{
ep->xfer_len -= TxPctSize;
8009336: 68bb ldr r3, [r7, #8]
8009338: 699a ldr r2, [r3, #24]
800933a: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
800933e: 1ad2 subs r2, r2, r3
8009340: 68bb ldr r3, [r7, #8]
8009342: 619a str r2, [r3, #24]
8009344: e002 b.n 800934c <HAL_PCD_EP_DB_Transmit+0x452>
}
else
{
ep->xfer_len = 0U;
8009346: 68bb ldr r3, [r7, #8]
8009348: 2200 movs r2, #0
800934a: 619a str r2, [r3, #24]
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
800934c: 68bb ldr r3, [r7, #8]
800934e: 699b ldr r3, [r3, #24]
8009350: 2b00 cmp r3, #0
8009352: f040 80f6 bne.w 8009542 <HAL_PCD_EP_DB_Transmit+0x648>
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
8009356: 68bb ldr r3, [r7, #8]
8009358: 785b ldrb r3, [r3, #1]
800935a: 2b00 cmp r3, #0
800935c: d126 bne.n 80093ac <HAL_PCD_EP_DB_Transmit+0x4b2>
800935e: 68fb ldr r3, [r7, #12]
8009360: 681b ldr r3, [r3, #0]
8009362: 677b str r3, [r7, #116] @ 0x74
8009364: 68fb ldr r3, [r7, #12]
8009366: 681b ldr r3, [r3, #0]
8009368: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800936c: b29b uxth r3, r3
800936e: 461a mov r2, r3
8009370: 6f7b ldr r3, [r7, #116] @ 0x74
8009372: 4413 add r3, r2
8009374: 677b str r3, [r7, #116] @ 0x74
8009376: 68bb ldr r3, [r7, #8]
8009378: 781b ldrb r3, [r3, #0]
800937a: 00da lsls r2, r3, #3
800937c: 6f7b ldr r3, [r7, #116] @ 0x74
800937e: 4413 add r3, r2
8009380: f203 4302 addw r3, r3, #1026 @ 0x402
8009384: 673b str r3, [r7, #112] @ 0x70
8009386: 6f3b ldr r3, [r7, #112] @ 0x70
8009388: 881b ldrh r3, [r3, #0]
800938a: b29b uxth r3, r3
800938c: f3c3 0309 ubfx r3, r3, #0, #10
8009390: b29a uxth r2, r3
8009392: 6f3b ldr r3, [r7, #112] @ 0x70
8009394: 801a strh r2, [r3, #0]
8009396: 6f3b ldr r3, [r7, #112] @ 0x70
8009398: 881b ldrh r3, [r3, #0]
800939a: b29b uxth r3, r3
800939c: ea6f 4343 mvn.w r3, r3, lsl #17
80093a0: ea6f 4353 mvn.w r3, r3, lsr #17
80093a4: b29a uxth r2, r3
80093a6: 6f3b ldr r3, [r7, #112] @ 0x70
80093a8: 801a strh r2, [r3, #0]
80093aa: e01a b.n 80093e2 <HAL_PCD_EP_DB_Transmit+0x4e8>
80093ac: 68bb ldr r3, [r7, #8]
80093ae: 785b ldrb r3, [r3, #1]
80093b0: 2b01 cmp r3, #1
80093b2: d116 bne.n 80093e2 <HAL_PCD_EP_DB_Transmit+0x4e8>
80093b4: 68fb ldr r3, [r7, #12]
80093b6: 681b ldr r3, [r3, #0]
80093b8: 67fb str r3, [r7, #124] @ 0x7c
80093ba: 68fb ldr r3, [r7, #12]
80093bc: 681b ldr r3, [r3, #0]
80093be: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80093c2: b29b uxth r3, r3
80093c4: 461a mov r2, r3
80093c6: 6ffb ldr r3, [r7, #124] @ 0x7c
80093c8: 4413 add r3, r2
80093ca: 67fb str r3, [r7, #124] @ 0x7c
80093cc: 68bb ldr r3, [r7, #8]
80093ce: 781b ldrb r3, [r3, #0]
80093d0: 00da lsls r2, r3, #3
80093d2: 6ffb ldr r3, [r7, #124] @ 0x7c
80093d4: 4413 add r3, r2
80093d6: f203 4302 addw r3, r3, #1026 @ 0x402
80093da: 67bb str r3, [r7, #120] @ 0x78
80093dc: 6fbb ldr r3, [r7, #120] @ 0x78
80093de: 2200 movs r2, #0
80093e0: 801a strh r2, [r3, #0]
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
80093e2: 68fb ldr r3, [r7, #12]
80093e4: 681b ldr r3, [r3, #0]
80093e6: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80093ea: 68bb ldr r3, [r7, #8]
80093ec: 785b ldrb r3, [r3, #1]
80093ee: 2b00 cmp r3, #0
80093f0: d12f bne.n 8009452 <HAL_PCD_EP_DB_Transmit+0x558>
80093f2: 68fb ldr r3, [r7, #12]
80093f4: 681b ldr r3, [r3, #0]
80093f6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
80093fa: 68fb ldr r3, [r7, #12]
80093fc: 681b ldr r3, [r3, #0]
80093fe: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009402: b29b uxth r3, r3
8009404: 461a mov r2, r3
8009406: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800940a: 4413 add r3, r2
800940c: f8c7 308c str.w r3, [r7, #140] @ 0x8c
8009410: 68bb ldr r3, [r7, #8]
8009412: 781b ldrb r3, [r3, #0]
8009414: 00da lsls r2, r3, #3
8009416: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800941a: 4413 add r3, r2
800941c: f203 4306 addw r3, r3, #1030 @ 0x406
8009420: f8c7 3088 str.w r3, [r7, #136] @ 0x88
8009424: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8009428: 881b ldrh r3, [r3, #0]
800942a: b29b uxth r3, r3
800942c: f3c3 0309 ubfx r3, r3, #0, #10
8009430: b29a uxth r2, r3
8009432: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8009436: 801a strh r2, [r3, #0]
8009438: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
800943c: 881b ldrh r3, [r3, #0]
800943e: b29b uxth r3, r3
8009440: ea6f 4343 mvn.w r3, r3, lsl #17
8009444: ea6f 4353 mvn.w r3, r3, lsr #17
8009448: b29a uxth r2, r3
800944a: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
800944e: 801a strh r2, [r3, #0]
8009450: e01c b.n 800948c <HAL_PCD_EP_DB_Transmit+0x592>
8009452: 68bb ldr r3, [r7, #8]
8009454: 785b ldrb r3, [r3, #1]
8009456: 2b01 cmp r3, #1
8009458: d118 bne.n 800948c <HAL_PCD_EP_DB_Transmit+0x592>
800945a: 68fb ldr r3, [r7, #12]
800945c: 681b ldr r3, [r3, #0]
800945e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009462: b29b uxth r3, r3
8009464: 461a mov r2, r3
8009466: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800946a: 4413 add r3, r2
800946c: f8c7 3084 str.w r3, [r7, #132] @ 0x84
8009470: 68bb ldr r3, [r7, #8]
8009472: 781b ldrb r3, [r3, #0]
8009474: 00da lsls r2, r3, #3
8009476: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800947a: 4413 add r3, r2
800947c: f203 4306 addw r3, r3, #1030 @ 0x406
8009480: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8009484: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8009488: 2200 movs r2, #0
800948a: 801a strh r2, [r3, #0]
if (ep->type == EP_TYPE_BULK)
800948c: 68bb ldr r3, [r7, #8]
800948e: 78db ldrb r3, [r3, #3]
8009490: 2b02 cmp r3, #2
8009492: d127 bne.n 80094e4 <HAL_PCD_EP_DB_Transmit+0x5ea>
{
/* Set Bulk endpoint in NAK state */
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
8009494: 68fb ldr r3, [r7, #12]
8009496: 681b ldr r3, [r3, #0]
8009498: 461a mov r2, r3
800949a: 68bb ldr r3, [r7, #8]
800949c: 781b ldrb r3, [r3, #0]
800949e: 009b lsls r3, r3, #2
80094a0: 4413 add r3, r2
80094a2: 881b ldrh r3, [r3, #0]
80094a4: b29b uxth r3, r3
80094a6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80094aa: f023 0340 bic.w r3, r3, #64 @ 0x40
80094ae: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
80094b2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
80094b6: f083 0320 eor.w r3, r3, #32
80094ba: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
80094be: 68fb ldr r3, [r7, #12]
80094c0: 681b ldr r3, [r3, #0]
80094c2: 461a mov r2, r3
80094c4: 68bb ldr r3, [r7, #8]
80094c6: 781b ldrb r3, [r3, #0]
80094c8: 009b lsls r3, r3, #2
80094ca: 441a add r2, r3
80094cc: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
80094d0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80094d4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80094d8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80094dc: f043 0380 orr.w r3, r3, #128 @ 0x80
80094e0: b29b uxth r3, r3
80094e2: 8013 strh r3, [r2, #0]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
80094e4: 68bb ldr r3, [r7, #8]
80094e6: 781b ldrb r3, [r3, #0]
80094e8: 4619 mov r1, r3
80094ea: 68f8 ldr r0, [r7, #12]
80094ec: f00d feff bl 80172ee <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
80094f0: 88fb ldrh r3, [r7, #6]
80094f2: f403 4380 and.w r3, r3, #16384 @ 0x4000
80094f6: 2b00 cmp r3, #0
80094f8: d121 bne.n 800953e <HAL_PCD_EP_DB_Transmit+0x644>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
80094fa: 68fb ldr r3, [r7, #12]
80094fc: 681b ldr r3, [r3, #0]
80094fe: 461a mov r2, r3
8009500: 68bb ldr r3, [r7, #8]
8009502: 781b ldrb r3, [r3, #0]
8009504: 009b lsls r3, r3, #2
8009506: 4413 add r3, r2
8009508: 881b ldrh r3, [r3, #0]
800950a: b29b uxth r3, r3
800950c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8009510: f023 0370 bic.w r3, r3, #112 @ 0x70
8009514: f8a7 3092 strh.w r3, [r7, #146] @ 0x92
8009518: 68fb ldr r3, [r7, #12]
800951a: 681b ldr r3, [r3, #0]
800951c: 461a mov r2, r3
800951e: 68bb ldr r3, [r7, #8]
8009520: 781b ldrb r3, [r3, #0]
8009522: 009b lsls r3, r3, #2
8009524: 441a add r2, r3
8009526: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
800952a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800952e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8009532: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8009536: f043 0380 orr.w r3, r3, #128 @ 0x80
800953a: b29b uxth r3, r3
800953c: 8013 strh r3, [r2, #0]
}
return HAL_OK;
800953e: 2300 movs r3, #0
8009540: e113 b.n 800976a <HAL_PCD_EP_DB_Transmit+0x870>
}
else /* Transfer is not yet Done */
{
/* Need to Free USB Buffer */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
8009542: 88fb ldrh r3, [r7, #6]
8009544: f403 4380 and.w r3, r3, #16384 @ 0x4000
8009548: 2b00 cmp r3, #0
800954a: d121 bne.n 8009590 <HAL_PCD_EP_DB_Transmit+0x696>
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
800954c: 68fb ldr r3, [r7, #12]
800954e: 681b ldr r3, [r3, #0]
8009550: 461a mov r2, r3
8009552: 68bb ldr r3, [r7, #8]
8009554: 781b ldrb r3, [r3, #0]
8009556: 009b lsls r3, r3, #2
8009558: 4413 add r3, r2
800955a: 881b ldrh r3, [r3, #0]
800955c: b29b uxth r3, r3
800955e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8009562: f023 0370 bic.w r3, r3, #112 @ 0x70
8009566: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
800956a: 68fb ldr r3, [r7, #12]
800956c: 681b ldr r3, [r3, #0]
800956e: 461a mov r2, r3
8009570: 68bb ldr r3, [r7, #8]
8009572: 781b ldrb r3, [r3, #0]
8009574: 009b lsls r3, r3, #2
8009576: 441a add r2, r3
8009578: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
800957c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8009580: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
8009584: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8009588: f043 0380 orr.w r3, r3, #128 @ 0x80
800958c: b29b uxth r3, r3
800958e: 8013 strh r3, [r2, #0]
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
8009590: 68bb ldr r3, [r7, #8]
8009592: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8009596: 2b01 cmp r3, #1
8009598: f040 80be bne.w 8009718 <HAL_PCD_EP_DB_Transmit+0x81e>
{
ep->xfer_buff += TxPctSize;
800959c: 68bb ldr r3, [r7, #8]
800959e: 695a ldr r2, [r3, #20]
80095a0: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80095a4: 441a add r2, r3
80095a6: 68bb ldr r3, [r7, #8]
80095a8: 615a str r2, [r3, #20]
ep->xfer_count += TxPctSize;
80095aa: 68bb ldr r3, [r7, #8]
80095ac: 69da ldr r2, [r3, #28]
80095ae: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80095b2: 441a add r2, r3
80095b4: 68bb ldr r3, [r7, #8]
80095b6: 61da str r2, [r3, #28]
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
80095b8: 68bb ldr r3, [r7, #8]
80095ba: 6a1a ldr r2, [r3, #32]
80095bc: 68bb ldr r3, [r7, #8]
80095be: 691b ldr r3, [r3, #16]
80095c0: 429a cmp r2, r3
80095c2: d309 bcc.n 80095d8 <HAL_PCD_EP_DB_Transmit+0x6de>
{
len = ep->maxpacket;
80095c4: 68bb ldr r3, [r7, #8]
80095c6: 691b ldr r3, [r3, #16]
80095c8: 65bb str r3, [r7, #88] @ 0x58
ep->xfer_len_db -= len;
80095ca: 68bb ldr r3, [r7, #8]
80095cc: 6a1a ldr r2, [r3, #32]
80095ce: 6dbb ldr r3, [r7, #88] @ 0x58
80095d0: 1ad2 subs r2, r2, r3
80095d2: 68bb ldr r3, [r7, #8]
80095d4: 621a str r2, [r3, #32]
80095d6: e015 b.n 8009604 <HAL_PCD_EP_DB_Transmit+0x70a>
}
else if (ep->xfer_len_db == 0U)
80095d8: 68bb ldr r3, [r7, #8]
80095da: 6a1b ldr r3, [r3, #32]
80095dc: 2b00 cmp r3, #0
80095de: d107 bne.n 80095f0 <HAL_PCD_EP_DB_Transmit+0x6f6>
{
len = TxPctSize;
80095e0: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96
80095e4: 65bb str r3, [r7, #88] @ 0x58
ep->xfer_fill_db = 0U;
80095e6: 68bb ldr r3, [r7, #8]
80095e8: 2200 movs r2, #0
80095ea: f883 2024 strb.w r2, [r3, #36] @ 0x24
80095ee: e009 b.n 8009604 <HAL_PCD_EP_DB_Transmit+0x70a>
}
else
{
len = ep->xfer_len_db;
80095f0: 68bb ldr r3, [r7, #8]
80095f2: 6a1b ldr r3, [r3, #32]
80095f4: 65bb str r3, [r7, #88] @ 0x58
ep->xfer_len_db = 0U;
80095f6: 68bb ldr r3, [r7, #8]
80095f8: 2200 movs r2, #0
80095fa: 621a str r2, [r3, #32]
ep->xfer_fill_db = 0;
80095fc: 68bb ldr r3, [r7, #8]
80095fe: 2200 movs r2, #0
8009600: f883 2024 strb.w r2, [r3, #36] @ 0x24
}
/* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
8009604: 68fb ldr r3, [r7, #12]
8009606: 681b ldr r3, [r3, #0]
8009608: 65fb str r3, [r7, #92] @ 0x5c
800960a: 68bb ldr r3, [r7, #8]
800960c: 785b ldrb r3, [r3, #1]
800960e: 2b00 cmp r3, #0
8009610: d15f bne.n 80096d2 <HAL_PCD_EP_DB_Transmit+0x7d8>
8009612: 68fb ldr r3, [r7, #12]
8009614: 681b ldr r3, [r3, #0]
8009616: 66bb str r3, [r7, #104] @ 0x68
8009618: 68fb ldr r3, [r7, #12]
800961a: 681b ldr r3, [r3, #0]
800961c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
8009620: b29b uxth r3, r3
8009622: 461a mov r2, r3
8009624: 6ebb ldr r3, [r7, #104] @ 0x68
8009626: 4413 add r3, r2
8009628: 66bb str r3, [r7, #104] @ 0x68
800962a: 68bb ldr r3, [r7, #8]
800962c: 781b ldrb r3, [r3, #0]
800962e: 00da lsls r2, r3, #3
8009630: 6ebb ldr r3, [r7, #104] @ 0x68
8009632: 4413 add r3, r2
8009634: f203 4306 addw r3, r3, #1030 @ 0x406
8009638: 667b str r3, [r7, #100] @ 0x64
800963a: 6e7b ldr r3, [r7, #100] @ 0x64
800963c: 881b ldrh r3, [r3, #0]
800963e: b29b uxth r3, r3
8009640: f3c3 0309 ubfx r3, r3, #0, #10
8009644: b29a uxth r2, r3
8009646: 6e7b ldr r3, [r7, #100] @ 0x64
8009648: 801a strh r2, [r3, #0]
800964a: 6dbb ldr r3, [r7, #88] @ 0x58
800964c: 2b00 cmp r3, #0
800964e: d10a bne.n 8009666 <HAL_PCD_EP_DB_Transmit+0x76c>
8009650: 6e7b ldr r3, [r7, #100] @ 0x64
8009652: 881b ldrh r3, [r3, #0]
8009654: b29b uxth r3, r3
8009656: ea6f 4343 mvn.w r3, r3, lsl #17
800965a: ea6f 4353 mvn.w r3, r3, lsr #17
800965e: b29a uxth r2, r3
8009660: 6e7b ldr r3, [r7, #100] @ 0x64
8009662: 801a strh r2, [r3, #0]
8009664: e04e b.n 8009704 <HAL_PCD_EP_DB_Transmit+0x80a>
8009666: 6dbb ldr r3, [r7, #88] @ 0x58
8009668: 2b3e cmp r3, #62 @ 0x3e
800966a: d816 bhi.n 800969a <HAL_PCD_EP_DB_Transmit+0x7a0>
800966c: 6dbb ldr r3, [r7, #88] @ 0x58
800966e: 085b lsrs r3, r3, #1
8009670: 663b str r3, [r7, #96] @ 0x60
8009672: 6dbb ldr r3, [r7, #88] @ 0x58
8009674: f003 0301 and.w r3, r3, #1
8009678: 2b00 cmp r3, #0
800967a: d002 beq.n 8009682 <HAL_PCD_EP_DB_Transmit+0x788>
800967c: 6e3b ldr r3, [r7, #96] @ 0x60
800967e: 3301 adds r3, #1
8009680: 663b str r3, [r7, #96] @ 0x60
8009682: 6e7b ldr r3, [r7, #100] @ 0x64
8009684: 881b ldrh r3, [r3, #0]
8009686: b29a uxth r2, r3
8009688: 6e3b ldr r3, [r7, #96] @ 0x60
800968a: b29b uxth r3, r3
800968c: 029b lsls r3, r3, #10
800968e: b29b uxth r3, r3
8009690: 4313 orrs r3, r2
8009692: b29a uxth r2, r3
8009694: 6e7b ldr r3, [r7, #100] @ 0x64
8009696: 801a strh r2, [r3, #0]
8009698: e034 b.n 8009704 <HAL_PCD_EP_DB_Transmit+0x80a>
800969a: 6dbb ldr r3, [r7, #88] @ 0x58
800969c: 095b lsrs r3, r3, #5
800969e: 663b str r3, [r7, #96] @ 0x60
80096a0: 6dbb ldr r3, [r7, #88] @ 0x58
80096a2: f003 031f and.w r3, r3, #31
80096a6: 2b00 cmp r3, #0
80096a8: d102 bne.n 80096b0 <HAL_PCD_EP_DB_Transmit+0x7b6>
80096aa: 6e3b ldr r3, [r7, #96] @ 0x60
80096ac: 3b01 subs r3, #1
80096ae: 663b str r3, [r7, #96] @ 0x60
80096b0: 6e7b ldr r3, [r7, #100] @ 0x64
80096b2: 881b ldrh r3, [r3, #0]
80096b4: b29a uxth r2, r3
80096b6: 6e3b ldr r3, [r7, #96] @ 0x60
80096b8: b29b uxth r3, r3
80096ba: 029b lsls r3, r3, #10
80096bc: b29b uxth r3, r3
80096be: 4313 orrs r3, r2
80096c0: b29b uxth r3, r3
80096c2: ea6f 4343 mvn.w r3, r3, lsl #17
80096c6: ea6f 4353 mvn.w r3, r3, lsr #17
80096ca: b29a uxth r2, r3
80096cc: 6e7b ldr r3, [r7, #100] @ 0x64
80096ce: 801a strh r2, [r3, #0]
80096d0: e018 b.n 8009704 <HAL_PCD_EP_DB_Transmit+0x80a>
80096d2: 68bb ldr r3, [r7, #8]
80096d4: 785b ldrb r3, [r3, #1]
80096d6: 2b01 cmp r3, #1
80096d8: d114 bne.n 8009704 <HAL_PCD_EP_DB_Transmit+0x80a>
80096da: 68fb ldr r3, [r7, #12]
80096dc: 681b ldr r3, [r3, #0]
80096de: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
80096e2: b29b uxth r3, r3
80096e4: 461a mov r2, r3
80096e6: 6dfb ldr r3, [r7, #92] @ 0x5c
80096e8: 4413 add r3, r2
80096ea: 65fb str r3, [r7, #92] @ 0x5c
80096ec: 68bb ldr r3, [r7, #8]
80096ee: 781b ldrb r3, [r3, #0]
80096f0: 00da lsls r2, r3, #3
80096f2: 6dfb ldr r3, [r7, #92] @ 0x5c
80096f4: 4413 add r3, r2
80096f6: f203 4306 addw r3, r3, #1030 @ 0x406
80096fa: 66fb str r3, [r7, #108] @ 0x6c
80096fc: 6dbb ldr r3, [r7, #88] @ 0x58
80096fe: b29a uxth r2, r3
8009700: 6efb ldr r3, [r7, #108] @ 0x6c
8009702: 801a strh r2, [r3, #0]
/* Copy the user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
8009704: 68fb ldr r3, [r7, #12]
8009706: 6818 ldr r0, [r3, #0]
8009708: 68bb ldr r3, [r7, #8]
800970a: 6959 ldr r1, [r3, #20]
800970c: 68bb ldr r3, [r7, #8]
800970e: 895a ldrh r2, [r3, #10]
8009710: 6dbb ldr r3, [r7, #88] @ 0x58
8009712: b29b uxth r3, r3
8009714: f005 fdc5 bl 800f2a2 <USB_WritePMA>
}
}
}
/* Enable endpoint IN */
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
8009718: 68fb ldr r3, [r7, #12]
800971a: 681b ldr r3, [r3, #0]
800971c: 461a mov r2, r3
800971e: 68bb ldr r3, [r7, #8]
8009720: 781b ldrb r3, [r3, #0]
8009722: 009b lsls r3, r3, #2
8009724: 4413 add r3, r2
8009726: 881b ldrh r3, [r3, #0]
8009728: b29b uxth r3, r3
800972a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800972e: f023 0340 bic.w r3, r3, #64 @ 0x40
8009732: 82fb strh r3, [r7, #22]
8009734: 8afb ldrh r3, [r7, #22]
8009736: f083 0310 eor.w r3, r3, #16
800973a: 82fb strh r3, [r7, #22]
800973c: 8afb ldrh r3, [r7, #22]
800973e: f083 0320 eor.w r3, r3, #32
8009742: 82fb strh r3, [r7, #22]
8009744: 68fb ldr r3, [r7, #12]
8009746: 681b ldr r3, [r3, #0]
8009748: 461a mov r2, r3
800974a: 68bb ldr r3, [r7, #8]
800974c: 781b ldrb r3, [r3, #0]
800974e: 009b lsls r3, r3, #2
8009750: 441a add r2, r3
8009752: 8afb ldrh r3, [r7, #22]
8009754: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
8009758: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800975c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8009760: f043 0380 orr.w r3, r3, #128 @ 0x80
8009764: b29b uxth r3, r3
8009766: 8013 strh r3, [r2, #0]
return HAL_OK;
8009768: 2300 movs r3, #0
}
800976a: 4618 mov r0, r3
800976c: 3798 adds r7, #152 @ 0x98
800976e: 46bd mov sp, r7
8009770: bd80 pop {r7, pc}
08009772 <HAL_PCDEx_PMAConfig>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
8009772: b480 push {r7}
8009774: b087 sub sp, #28
8009776: af00 add r7, sp, #0
8009778: 60f8 str r0, [r7, #12]
800977a: 607b str r3, [r7, #4]
800977c: 460b mov r3, r1
800977e: 817b strh r3, [r7, #10]
8009780: 4613 mov r3, r2
8009782: 813b strh r3, [r7, #8]
PCD_EPTypeDef *ep;
/* Initialize ep structure */
if ((0x80U & ep_addr) == 0x80U)
8009784: 897b ldrh r3, [r7, #10]
8009786: f003 0380 and.w r3, r3, #128 @ 0x80
800978a: b29b uxth r3, r3
800978c: 2b00 cmp r3, #0
800978e: d00b beq.n 80097a8 <HAL_PCDEx_PMAConfig+0x36>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8009790: 897b ldrh r3, [r7, #10]
8009792: f003 0207 and.w r2, r3, #7
8009796: 4613 mov r3, r2
8009798: 009b lsls r3, r3, #2
800979a: 4413 add r3, r2
800979c: 00db lsls r3, r3, #3
800979e: 3310 adds r3, #16
80097a0: 68fa ldr r2, [r7, #12]
80097a2: 4413 add r3, r2
80097a4: 617b str r3, [r7, #20]
80097a6: e009 b.n 80097bc <HAL_PCDEx_PMAConfig+0x4a>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
80097a8: 897a ldrh r2, [r7, #10]
80097aa: 4613 mov r3, r2
80097ac: 009b lsls r3, r3, #2
80097ae: 4413 add r3, r2
80097b0: 00db lsls r3, r3, #3
80097b2: f503 73a8 add.w r3, r3, #336 @ 0x150
80097b6: 68fa ldr r2, [r7, #12]
80097b8: 4413 add r3, r2
80097ba: 617b str r3, [r7, #20]
}
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
80097bc: 893b ldrh r3, [r7, #8]
80097be: 2b00 cmp r3, #0
80097c0: d107 bne.n 80097d2 <HAL_PCDEx_PMAConfig+0x60>
{
/* Single Buffer */
ep->doublebuffer = 0U;
80097c2: 697b ldr r3, [r7, #20]
80097c4: 2200 movs r2, #0
80097c6: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
80097c8: 687b ldr r3, [r7, #4]
80097ca: b29a uxth r2, r3
80097cc: 697b ldr r3, [r7, #20]
80097ce: 80da strh r2, [r3, #6]
80097d0: e00b b.n 80097ea <HAL_PCDEx_PMAConfig+0x78>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
ep->doublebuffer = 1U;
80097d2: 697b ldr r3, [r7, #20]
80097d4: 2201 movs r2, #1
80097d6: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
80097d8: 687b ldr r3, [r7, #4]
80097da: b29a uxth r2, r3
80097dc: 697b ldr r3, [r7, #20]
80097de: 811a strh r2, [r3, #8]
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
80097e0: 687b ldr r3, [r7, #4]
80097e2: 0c1b lsrs r3, r3, #16
80097e4: b29a uxth r2, r3
80097e6: 697b ldr r3, [r7, #20]
80097e8: 815a strh r2, [r3, #10]
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
80097ea: 2300 movs r3, #0
}
80097ec: 4618 mov r0, r3
80097ee: 371c adds r7, #28
80097f0: 46bd mov sp, r7
80097f2: f85d 7b04 ldr.w r7, [sp], #4
80097f6: 4770 bx lr
080097f8 <HAL_PCDEx_ActivateLPM>:
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
80097f8: b480 push {r7}
80097fa: b085 sub sp, #20
80097fc: af00 add r7, sp, #0
80097fe: 6078 str r0, [r7, #4]
USB_TypeDef *USBx = hpcd->Instance;
8009800: 687b ldr r3, [r7, #4]
8009802: 681b ldr r3, [r3, #0]
8009804: 60fb str r3, [r7, #12]
hpcd->lpm_active = 1U;
8009806: 687b ldr r3, [r7, #4]
8009808: 2201 movs r2, #1
800980a: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
hpcd->LPM_State = LPM_L0;
800980e: 687b ldr r3, [r7, #4]
8009810: 2200 movs r2, #0
8009812: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8
USBx->LPMCSR |= USB_LPMCSR_LMPEN;
8009816: 68fb ldr r3, [r7, #12]
8009818: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54
800981c: b29b uxth r3, r3
800981e: f043 0301 orr.w r3, r3, #1
8009822: b29a uxth r2, r3
8009824: 68fb ldr r3, [r7, #12]
8009826: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
USBx->LPMCSR |= USB_LPMCSR_LPMACK;
800982a: 68fb ldr r3, [r7, #12]
800982c: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54
8009830: b29b uxth r3, r3
8009832: f043 0302 orr.w r3, r3, #2
8009836: b29a uxth r2, r3
8009838: 68fb ldr r3, [r7, #12]
800983a: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
return HAL_OK;
800983e: 2300 movs r3, #0
}
8009840: 4618 mov r0, r3
8009842: 3714 adds r7, #20
8009844: 46bd mov sp, r7
8009846: f85d 7b04 ldr.w r7, [sp], #4
800984a: 4770 bx lr
0800984c <HAL_PWR_EnableBkUpAccess>:
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
* back-up domain.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
800984c: b480 push {r7}
800984e: af00 add r7, sp, #0
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8009850: 4b05 ldr r3, [pc, #20] @ (8009868 <HAL_PWR_EnableBkUpAccess+0x1c>)
8009852: 681b ldr r3, [r3, #0]
8009854: 4a04 ldr r2, [pc, #16] @ (8009868 <HAL_PWR_EnableBkUpAccess+0x1c>)
8009856: f443 7380 orr.w r3, r3, #256 @ 0x100
800985a: 6013 str r3, [r2, #0]
}
800985c: bf00 nop
800985e: 46bd mov sp, r7
8009860: f85d 7b04 ldr.w r7, [sp], #4
8009864: 4770 bx lr
8009866: bf00 nop
8009868: 58000400 .word 0x58000400
0800986c <HAL_PWREx_GetVoltageRange>:
/**
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
800986c: b480 push {r7}
800986e: af00 add r7, sp, #0
return (PWR->CR1 & PWR_CR1_VOS);
8009870: 4b04 ldr r3, [pc, #16] @ (8009884 <HAL_PWREx_GetVoltageRange+0x18>)
8009872: 681b ldr r3, [r3, #0]
8009874: f403 63c0 and.w r3, r3, #1536 @ 0x600
}
8009878: 4618 mov r0, r3
800987a: 46bd mov sp, r7
800987c: f85d 7b04 ldr.w r7, [sp], #4
8009880: 4770 bx lr
8009882: bf00 nop
8009884: 58000400 .word 0x58000400
08009888 <HAL_PWREx_EnableVddUSB>:
* @brief Enable VDDUSB supply.
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
* @retval None
*/
void HAL_PWREx_EnableVddUSB(void)
{
8009888: b480 push {r7}
800988a: af00 add r7, sp, #0
SET_BIT(PWR->CR2, PWR_CR2_USV);
800988c: 4b05 ldr r3, [pc, #20] @ (80098a4 <HAL_PWREx_EnableVddUSB+0x1c>)
800988e: 685b ldr r3, [r3, #4]
8009890: 4a04 ldr r2, [pc, #16] @ (80098a4 <HAL_PWREx_EnableVddUSB+0x1c>)
8009892: f443 6380 orr.w r3, r3, #1024 @ 0x400
8009896: 6053 str r3, [r2, #4]
}
8009898: bf00 nop
800989a: 46bd mov sp, r7
800989c: f85d 7b04 ldr.w r7, [sp], #4
80098a0: 4770 bx lr
80098a2: bf00 nop
80098a4: 58000400 .word 0x58000400
080098a8 <LL_RCC_HSE_IsEnabledDiv2>:
{
80098a8: b480 push {r7}
80098aa: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL);
80098ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80098b0: 681b ldr r3, [r3, #0]
80098b2: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80098b6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80098ba: d101 bne.n 80098c0 <LL_RCC_HSE_IsEnabledDiv2+0x18>
80098bc: 2301 movs r3, #1
80098be: e000 b.n 80098c2 <LL_RCC_HSE_IsEnabledDiv2+0x1a>
80098c0: 2300 movs r3, #0
}
80098c2: 4618 mov r0, r3
80098c4: 46bd mov sp, r7
80098c6: f85d 7b04 ldr.w r7, [sp], #4
80098ca: 4770 bx lr
080098cc <LL_RCC_HSE_Enable>:
{
80098cc: b480 push {r7}
80098ce: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEON);
80098d0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80098d4: 681b ldr r3, [r3, #0]
80098d6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
80098da: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80098de: 6013 str r3, [r2, #0]
}
80098e0: bf00 nop
80098e2: 46bd mov sp, r7
80098e4: f85d 7b04 ldr.w r7, [sp], #4
80098e8: 4770 bx lr
080098ea <LL_RCC_HSE_Disable>:
{
80098ea: b480 push {r7}
80098ec: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
80098ee: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80098f2: 681b ldr r3, [r3, #0]
80098f4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
80098f8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80098fc: 6013 str r3, [r2, #0]
}
80098fe: bf00 nop
8009900: 46bd mov sp, r7
8009902: f85d 7b04 ldr.w r7, [sp], #4
8009906: 4770 bx lr
08009908 <LL_RCC_HSE_IsReady>:
{
8009908: b480 push {r7}
800990a: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
800990c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009910: 681b ldr r3, [r3, #0]
8009912: f403 3300 and.w r3, r3, #131072 @ 0x20000
8009916: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
800991a: d101 bne.n 8009920 <LL_RCC_HSE_IsReady+0x18>
800991c: 2301 movs r3, #1
800991e: e000 b.n 8009922 <LL_RCC_HSE_IsReady+0x1a>
8009920: 2300 movs r3, #0
}
8009922: 4618 mov r0, r3
8009924: 46bd mov sp, r7
8009926: f85d 7b04 ldr.w r7, [sp], #4
800992a: 4770 bx lr
0800992c <LL_RCC_HSI_Enable>:
{
800992c: b480 push {r7}
800992e: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSION);
8009930: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009934: 681b ldr r3, [r3, #0]
8009936: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800993a: f443 7380 orr.w r3, r3, #256 @ 0x100
800993e: 6013 str r3, [r2, #0]
}
8009940: bf00 nop
8009942: 46bd mov sp, r7
8009944: f85d 7b04 ldr.w r7, [sp], #4
8009948: 4770 bx lr
0800994a <LL_RCC_HSI_Disable>:
{
800994a: b480 push {r7}
800994c: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_HSION);
800994e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009952: 681b ldr r3, [r3, #0]
8009954: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009958: f423 7380 bic.w r3, r3, #256 @ 0x100
800995c: 6013 str r3, [r2, #0]
}
800995e: bf00 nop
8009960: 46bd mov sp, r7
8009962: f85d 7b04 ldr.w r7, [sp], #4
8009966: 4770 bx lr
08009968 <LL_RCC_HSI_IsReady>:
{
8009968: b480 push {r7}
800996a: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
800996c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009970: 681b ldr r3, [r3, #0]
8009972: f403 6380 and.w r3, r3, #1024 @ 0x400
8009976: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800997a: d101 bne.n 8009980 <LL_RCC_HSI_IsReady+0x18>
800997c: 2301 movs r3, #1
800997e: e000 b.n 8009982 <LL_RCC_HSI_IsReady+0x1a>
8009980: 2300 movs r3, #0
}
8009982: 4618 mov r0, r3
8009984: 46bd mov sp, r7
8009986: f85d 7b04 ldr.w r7, [sp], #4
800998a: 4770 bx lr
0800998c <LL_RCC_HSI_SetCalibTrimming>:
{
800998c: b480 push {r7}
800998e: b083 sub sp, #12
8009990: af00 add r7, sp, #0
8009992: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
8009994: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009998: 685b ldr r3, [r3, #4]
800999a: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
800999e: 687b ldr r3, [r7, #4]
80099a0: 061b lsls r3, r3, #24
80099a2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
80099a6: 4313 orrs r3, r2
80099a8: 604b str r3, [r1, #4]
}
80099aa: bf00 nop
80099ac: 370c adds r7, #12
80099ae: 46bd mov sp, r7
80099b0: f85d 7b04 ldr.w r7, [sp], #4
80099b4: 4770 bx lr
080099b6 <LL_RCC_HSI48_Enable>:
{
80099b6: b480 push {r7}
80099b8: af00 add r7, sp, #0
SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
80099ba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80099be: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
80099c2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
80099c6: f043 0301 orr.w r3, r3, #1
80099ca: f8c2 3098 str.w r3, [r2, #152] @ 0x98
}
80099ce: bf00 nop
80099d0: 46bd mov sp, r7
80099d2: f85d 7b04 ldr.w r7, [sp], #4
80099d6: 4770 bx lr
080099d8 <LL_RCC_HSI48_Disable>:
{
80099d8: b480 push {r7}
80099da: af00 add r7, sp, #0
CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
80099dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80099e0: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
80099e4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
80099e8: f023 0301 bic.w r3, r3, #1
80099ec: f8c2 3098 str.w r3, [r2, #152] @ 0x98
}
80099f0: bf00 nop
80099f2: 46bd mov sp, r7
80099f4: f85d 7b04 ldr.w r7, [sp], #4
80099f8: 4770 bx lr
080099fa <LL_RCC_HSI48_IsReady>:
{
80099fa: b480 push {r7}
80099fc: af00 add r7, sp, #0
return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
80099fe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009a02: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8009a06: f003 0302 and.w r3, r3, #2
8009a0a: 2b02 cmp r3, #2
8009a0c: d101 bne.n 8009a12 <LL_RCC_HSI48_IsReady+0x18>
8009a0e: 2301 movs r3, #1
8009a10: e000 b.n 8009a14 <LL_RCC_HSI48_IsReady+0x1a>
8009a12: 2300 movs r3, #0
}
8009a14: 4618 mov r0, r3
8009a16: 46bd mov sp, r7
8009a18: f85d 7b04 ldr.w r7, [sp], #4
8009a1c: 4770 bx lr
08009a1e <LL_RCC_LSE_Enable>:
{
8009a1e: b480 push {r7}
8009a20: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
8009a22: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009a26: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8009a2a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009a2e: f043 0301 orr.w r3, r3, #1
8009a32: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
8009a36: bf00 nop
8009a38: 46bd mov sp, r7
8009a3a: f85d 7b04 ldr.w r7, [sp], #4
8009a3e: 4770 bx lr
08009a40 <LL_RCC_LSE_Disable>:
{
8009a40: b480 push {r7}
8009a42: af00 add r7, sp, #0
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
8009a44: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009a48: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8009a4c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009a50: f023 0301 bic.w r3, r3, #1
8009a54: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
8009a58: bf00 nop
8009a5a: 46bd mov sp, r7
8009a5c: f85d 7b04 ldr.w r7, [sp], #4
8009a60: 4770 bx lr
08009a62 <LL_RCC_LSE_EnableBypass>:
{
8009a62: b480 push {r7}
8009a64: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
8009a66: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009a6a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8009a6e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009a72: f043 0304 orr.w r3, r3, #4
8009a76: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
8009a7a: bf00 nop
8009a7c: 46bd mov sp, r7
8009a7e: f85d 7b04 ldr.w r7, [sp], #4
8009a82: 4770 bx lr
08009a84 <LL_RCC_LSE_DisableBypass>:
{
8009a84: b480 push {r7}
8009a86: af00 add r7, sp, #0
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
8009a88: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009a8c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8009a90: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009a94: f023 0304 bic.w r3, r3, #4
8009a98: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
8009a9c: bf00 nop
8009a9e: 46bd mov sp, r7
8009aa0: f85d 7b04 ldr.w r7, [sp], #4
8009aa4: 4770 bx lr
08009aa6 <LL_RCC_LSE_IsReady>:
{
8009aa6: b480 push {r7}
8009aa8: af00 add r7, sp, #0
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
8009aaa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009aae: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8009ab2: f003 0302 and.w r3, r3, #2
8009ab6: 2b02 cmp r3, #2
8009ab8: d101 bne.n 8009abe <LL_RCC_LSE_IsReady+0x18>
8009aba: 2301 movs r3, #1
8009abc: e000 b.n 8009ac0 <LL_RCC_LSE_IsReady+0x1a>
8009abe: 2300 movs r3, #0
}
8009ac0: 4618 mov r0, r3
8009ac2: 46bd mov sp, r7
8009ac4: f85d 7b04 ldr.w r7, [sp], #4
8009ac8: 4770 bx lr
08009aca <LL_RCC_LSI1_Enable>:
{
8009aca: b480 push {r7}
8009acc: af00 add r7, sp, #0
SET_BIT(RCC->CSR, RCC_CSR_LSI1ON);
8009ace: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009ad2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8009ad6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009ada: f043 0301 orr.w r3, r3, #1
8009ade: f8c2 3094 str.w r3, [r2, #148] @ 0x94
}
8009ae2: bf00 nop
8009ae4: 46bd mov sp, r7
8009ae6: f85d 7b04 ldr.w r7, [sp], #4
8009aea: 4770 bx lr
08009aec <LL_RCC_LSI1_Disable>:
{
8009aec: b480 push {r7}
8009aee: af00 add r7, sp, #0
CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON);
8009af0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009af4: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8009af8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009afc: f023 0301 bic.w r3, r3, #1
8009b00: f8c2 3094 str.w r3, [r2, #148] @ 0x94
}
8009b04: bf00 nop
8009b06: 46bd mov sp, r7
8009b08: f85d 7b04 ldr.w r7, [sp], #4
8009b0c: 4770 bx lr
08009b0e <LL_RCC_LSI1_IsReady>:
{
8009b0e: b480 push {r7}
8009b10: af00 add r7, sp, #0
return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL);
8009b12: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009b16: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8009b1a: f003 0302 and.w r3, r3, #2
8009b1e: 2b02 cmp r3, #2
8009b20: d101 bne.n 8009b26 <LL_RCC_LSI1_IsReady+0x18>
8009b22: 2301 movs r3, #1
8009b24: e000 b.n 8009b28 <LL_RCC_LSI1_IsReady+0x1a>
8009b26: 2300 movs r3, #0
}
8009b28: 4618 mov r0, r3
8009b2a: 46bd mov sp, r7
8009b2c: f85d 7b04 ldr.w r7, [sp], #4
8009b30: 4770 bx lr
08009b32 <LL_RCC_LSI2_Enable>:
{
8009b32: b480 push {r7}
8009b34: af00 add r7, sp, #0
SET_BIT(RCC->CSR, RCC_CSR_LSI2ON);
8009b36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009b3a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8009b3e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009b42: f043 0304 orr.w r3, r3, #4
8009b46: f8c2 3094 str.w r3, [r2, #148] @ 0x94
}
8009b4a: bf00 nop
8009b4c: 46bd mov sp, r7
8009b4e: f85d 7b04 ldr.w r7, [sp], #4
8009b52: 4770 bx lr
08009b54 <LL_RCC_LSI2_Disable>:
{
8009b54: b480 push {r7}
8009b56: af00 add r7, sp, #0
CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON);
8009b58: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009b5c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8009b60: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009b64: f023 0304 bic.w r3, r3, #4
8009b68: f8c2 3094 str.w r3, [r2, #148] @ 0x94
}
8009b6c: bf00 nop
8009b6e: 46bd mov sp, r7
8009b70: f85d 7b04 ldr.w r7, [sp], #4
8009b74: 4770 bx lr
08009b76 <LL_RCC_LSI2_IsReady>:
{
8009b76: b480 push {r7}
8009b78: af00 add r7, sp, #0
return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL);
8009b7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009b7e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8009b82: f003 0308 and.w r3, r3, #8
8009b86: 2b08 cmp r3, #8
8009b88: d101 bne.n 8009b8e <LL_RCC_LSI2_IsReady+0x18>
8009b8a: 2301 movs r3, #1
8009b8c: e000 b.n 8009b90 <LL_RCC_LSI2_IsReady+0x1a>
8009b8e: 2300 movs r3, #0
}
8009b90: 4618 mov r0, r3
8009b92: 46bd mov sp, r7
8009b94: f85d 7b04 ldr.w r7, [sp], #4
8009b98: 4770 bx lr
08009b9a <LL_RCC_LSI2_SetTrimming>:
{
8009b9a: b480 push {r7}
8009b9c: b083 sub sp, #12
8009b9e: af00 add r7, sp, #0
8009ba0: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos);
8009ba2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009ba6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8009baa: f423 6270 bic.w r2, r3, #3840 @ 0xf00
8009bae: 687b ldr r3, [r7, #4]
8009bb0: 021b lsls r3, r3, #8
8009bb2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009bb6: 4313 orrs r3, r2
8009bb8: f8c1 3094 str.w r3, [r1, #148] @ 0x94
}
8009bbc: bf00 nop
8009bbe: 370c adds r7, #12
8009bc0: 46bd mov sp, r7
8009bc2: f85d 7b04 ldr.w r7, [sp], #4
8009bc6: 4770 bx lr
08009bc8 <LL_RCC_MSI_Enable>:
{
8009bc8: b480 push {r7}
8009bca: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSION);
8009bcc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009bd0: 681b ldr r3, [r3, #0]
8009bd2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009bd6: f043 0301 orr.w r3, r3, #1
8009bda: 6013 str r3, [r2, #0]
}
8009bdc: bf00 nop
8009bde: 46bd mov sp, r7
8009be0: f85d 7b04 ldr.w r7, [sp], #4
8009be4: 4770 bx lr
08009be6 <LL_RCC_MSI_Disable>:
{
8009be6: b480 push {r7}
8009be8: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_MSION);
8009bea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009bee: 681b ldr r3, [r3, #0]
8009bf0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009bf4: f023 0301 bic.w r3, r3, #1
8009bf8: 6013 str r3, [r2, #0]
}
8009bfa: bf00 nop
8009bfc: 46bd mov sp, r7
8009bfe: f85d 7b04 ldr.w r7, [sp], #4
8009c02: 4770 bx lr
08009c04 <LL_RCC_MSI_IsReady>:
{
8009c04: b480 push {r7}
8009c06: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL);
8009c08: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009c0c: 681b ldr r3, [r3, #0]
8009c0e: f003 0302 and.w r3, r3, #2
8009c12: 2b02 cmp r3, #2
8009c14: d101 bne.n 8009c1a <LL_RCC_MSI_IsReady+0x16>
8009c16: 2301 movs r3, #1
8009c18: e000 b.n 8009c1c <LL_RCC_MSI_IsReady+0x18>
8009c1a: 2300 movs r3, #0
}
8009c1c: 4618 mov r0, r3
8009c1e: 46bd mov sp, r7
8009c20: f85d 7b04 ldr.w r7, [sp], #4
8009c24: 4770 bx lr
08009c26 <LL_RCC_MSI_SetRange>:
{
8009c26: b480 push {r7}
8009c28: b083 sub sp, #12
8009c2a: af00 add r7, sp, #0
8009c2c: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
8009c2e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009c32: 681b ldr r3, [r3, #0]
8009c34: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8009c38: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009c3c: 687b ldr r3, [r7, #4]
8009c3e: 4313 orrs r3, r2
8009c40: 600b str r3, [r1, #0]
}
8009c42: bf00 nop
8009c44: 370c adds r7, #12
8009c46: 46bd mov sp, r7
8009c48: f85d 7b04 ldr.w r7, [sp], #4
8009c4c: 4770 bx lr
08009c4e <LL_RCC_MSI_GetRange>:
{
8009c4e: b480 push {r7}
8009c50: b083 sub sp, #12
8009c52: af00 add r7, sp, #0
uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);
8009c54: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009c58: 681b ldr r3, [r3, #0]
8009c5a: f003 03f0 and.w r3, r3, #240 @ 0xf0
8009c5e: 607b str r3, [r7, #4]
if (msiRange > LL_RCC_MSIRANGE_11)
8009c60: 687b ldr r3, [r7, #4]
8009c62: 2bb0 cmp r3, #176 @ 0xb0
8009c64: d901 bls.n 8009c6a <LL_RCC_MSI_GetRange+0x1c>
msiRange = LL_RCC_MSIRANGE_11;
8009c66: 23b0 movs r3, #176 @ 0xb0
8009c68: 607b str r3, [r7, #4]
return msiRange;
8009c6a: 687b ldr r3, [r7, #4]
}
8009c6c: 4618 mov r0, r3
8009c6e: 370c adds r7, #12
8009c70: 46bd mov sp, r7
8009c72: f85d 7b04 ldr.w r7, [sp], #4
8009c76: 4770 bx lr
08009c78 <LL_RCC_MSI_SetCalibTrimming>:
{
8009c78: b480 push {r7}
8009c7a: b083 sub sp, #12
8009c7c: af00 add r7, sp, #0
8009c7e: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
8009c80: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009c84: 685b ldr r3, [r3, #4]
8009c86: f423 427f bic.w r2, r3, #65280 @ 0xff00
8009c8a: 687b ldr r3, [r7, #4]
8009c8c: 021b lsls r3, r3, #8
8009c8e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009c92: 4313 orrs r3, r2
8009c94: 604b str r3, [r1, #4]
}
8009c96: bf00 nop
8009c98: 370c adds r7, #12
8009c9a: 46bd mov sp, r7
8009c9c: f85d 7b04 ldr.w r7, [sp], #4
8009ca0: 4770 bx lr
08009ca2 <LL_RCC_SetSysClkSource>:
{
8009ca2: b480 push {r7}
8009ca4: b083 sub sp, #12
8009ca6: af00 add r7, sp, #0
8009ca8: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
8009caa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009cae: 689b ldr r3, [r3, #8]
8009cb0: f023 0203 bic.w r2, r3, #3
8009cb4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009cb8: 687b ldr r3, [r7, #4]
8009cba: 4313 orrs r3, r2
8009cbc: 608b str r3, [r1, #8]
}
8009cbe: bf00 nop
8009cc0: 370c adds r7, #12
8009cc2: 46bd mov sp, r7
8009cc4: f85d 7b04 ldr.w r7, [sp], #4
8009cc8: 4770 bx lr
08009cca <LL_RCC_GetSysClkSource>:
{
8009cca: b480 push {r7}
8009ccc: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
8009cce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009cd2: 689b ldr r3, [r3, #8]
8009cd4: f003 030c and.w r3, r3, #12
}
8009cd8: 4618 mov r0, r3
8009cda: 46bd mov sp, r7
8009cdc: f85d 7b04 ldr.w r7, [sp], #4
8009ce0: 4770 bx lr
08009ce2 <LL_RCC_SetAHBPrescaler>:
{
8009ce2: b480 push {r7}
8009ce4: b083 sub sp, #12
8009ce6: af00 add r7, sp, #0
8009ce8: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
8009cea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009cee: 689b ldr r3, [r3, #8]
8009cf0: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8009cf4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009cf8: 687b ldr r3, [r7, #4]
8009cfa: 4313 orrs r3, r2
8009cfc: 608b str r3, [r1, #8]
}
8009cfe: bf00 nop
8009d00: 370c adds r7, #12
8009d02: 46bd mov sp, r7
8009d04: f85d 7b04 ldr.w r7, [sp], #4
8009d08: 4770 bx lr
08009d0a <LL_C2_RCC_SetAHBPrescaler>:
{
8009d0a: b480 push {r7}
8009d0c: b083 sub sp, #12
8009d0e: af00 add r7, sp, #0
8009d10: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler);
8009d12: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009d16: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
8009d1a: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8009d1e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009d22: 687b ldr r3, [r7, #4]
8009d24: 4313 orrs r3, r2
8009d26: f8c1 3108 str.w r3, [r1, #264] @ 0x108
}
8009d2a: bf00 nop
8009d2c: 370c adds r7, #12
8009d2e: 46bd mov sp, r7
8009d30: f85d 7b04 ldr.w r7, [sp], #4
8009d34: 4770 bx lr
08009d36 <LL_RCC_SetAHB4Prescaler>:
{
8009d36: b480 push {r7}
8009d38: b083 sub sp, #12
8009d3a: af00 add r7, sp, #0
8009d3c: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4);
8009d3e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009d42: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
8009d46: f023 020f bic.w r2, r3, #15
8009d4a: 687b ldr r3, [r7, #4]
8009d4c: 091b lsrs r3, r3, #4
8009d4e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009d52: 4313 orrs r3, r2
8009d54: f8c1 3108 str.w r3, [r1, #264] @ 0x108
}
8009d58: bf00 nop
8009d5a: 370c adds r7, #12
8009d5c: 46bd mov sp, r7
8009d5e: f85d 7b04 ldr.w r7, [sp], #4
8009d62: 4770 bx lr
08009d64 <LL_RCC_SetAPB1Prescaler>:
{
8009d64: b480 push {r7}
8009d66: b083 sub sp, #12
8009d68: af00 add r7, sp, #0
8009d6a: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
8009d6c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009d70: 689b ldr r3, [r3, #8]
8009d72: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8009d76: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009d7a: 687b ldr r3, [r7, #4]
8009d7c: 4313 orrs r3, r2
8009d7e: 608b str r3, [r1, #8]
}
8009d80: bf00 nop
8009d82: 370c adds r7, #12
8009d84: 46bd mov sp, r7
8009d86: f85d 7b04 ldr.w r7, [sp], #4
8009d8a: 4770 bx lr
08009d8c <LL_RCC_SetAPB2Prescaler>:
{
8009d8c: b480 push {r7}
8009d8e: b083 sub sp, #12
8009d90: af00 add r7, sp, #0
8009d92: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
8009d94: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009d98: 689b ldr r3, [r3, #8]
8009d9a: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8009d9e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8009da2: 687b ldr r3, [r7, #4]
8009da4: 4313 orrs r3, r2
8009da6: 608b str r3, [r1, #8]
}
8009da8: bf00 nop
8009daa: 370c adds r7, #12
8009dac: 46bd mov sp, r7
8009dae: f85d 7b04 ldr.w r7, [sp], #4
8009db2: 4770 bx lr
08009db4 <LL_RCC_GetAHBPrescaler>:
{
8009db4: b480 push {r7}
8009db6: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
8009db8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009dbc: 689b ldr r3, [r3, #8]
8009dbe: f003 03f0 and.w r3, r3, #240 @ 0xf0
}
8009dc2: 4618 mov r0, r3
8009dc4: 46bd mov sp, r7
8009dc6: f85d 7b04 ldr.w r7, [sp], #4
8009dca: 4770 bx lr
08009dcc <LL_C2_RCC_GetAHBPrescaler>:
{
8009dcc: b480 push {r7}
8009dce: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE));
8009dd0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009dd4: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
8009dd8: f003 03f0 and.w r3, r3, #240 @ 0xf0
}
8009ddc: 4618 mov r0, r3
8009dde: 46bd mov sp, r7
8009de0: f85d 7b04 ldr.w r7, [sp], #4
8009de4: 4770 bx lr
08009de6 <LL_RCC_GetAHB4Prescaler>:
{
8009de6: b480 push {r7}
8009de8: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4);
8009dea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009dee: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
8009df2: 011b lsls r3, r3, #4
8009df4: f003 03f0 and.w r3, r3, #240 @ 0xf0
}
8009df8: 4618 mov r0, r3
8009dfa: 46bd mov sp, r7
8009dfc: f85d 7b04 ldr.w r7, [sp], #4
8009e00: 4770 bx lr
08009e02 <LL_RCC_GetAPB1Prescaler>:
{
8009e02: b480 push {r7}
8009e04: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
8009e06: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009e0a: 689b ldr r3, [r3, #8]
8009e0c: f403 63e0 and.w r3, r3, #1792 @ 0x700
}
8009e10: 4618 mov r0, r3
8009e12: 46bd mov sp, r7
8009e14: f85d 7b04 ldr.w r7, [sp], #4
8009e18: 4770 bx lr
08009e1a <LL_RCC_GetAPB2Prescaler>:
{
8009e1a: b480 push {r7}
8009e1c: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
8009e1e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009e22: 689b ldr r3, [r3, #8]
8009e24: f403 5360 and.w r3, r3, #14336 @ 0x3800
}
8009e28: 4618 mov r0, r3
8009e2a: 46bd mov sp, r7
8009e2c: f85d 7b04 ldr.w r7, [sp], #4
8009e30: 4770 bx lr
08009e32 <LL_RCC_PLL_Enable>:
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
8009e32: b480 push {r7}
8009e34: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_PLLON);
8009e36: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009e3a: 681b ldr r3, [r3, #0]
8009e3c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009e40: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8009e44: 6013 str r3, [r2, #0]
}
8009e46: bf00 nop
8009e48: 46bd mov sp, r7
8009e4a: f85d 7b04 ldr.w r7, [sp], #4
8009e4e: 4770 bx lr
08009e50 <LL_RCC_PLL_Disable>:
* @note Cannot be disabled if the PLL clock is used as the system clock
* @rmtoll CR PLLON LL_RCC_PLL_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
{
8009e50: b480 push {r7}
8009e52: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
8009e54: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009e58: 681b ldr r3, [r3, #0]
8009e5a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8009e5e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8009e62: 6013 str r3, [r2, #0]
}
8009e64: bf00 nop
8009e66: 46bd mov sp, r7
8009e68: f85d 7b04 ldr.w r7, [sp], #4
8009e6c: 4770 bx lr
08009e6e <LL_RCC_PLL_IsReady>:
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
8009e6e: b480 push {r7}
8009e70: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
8009e72: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009e76: 681b ldr r3, [r3, #0]
8009e78: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8009e7c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8009e80: d101 bne.n 8009e86 <LL_RCC_PLL_IsReady+0x18>
8009e82: 2301 movs r3, #1
8009e84: e000 b.n 8009e88 <LL_RCC_PLL_IsReady+0x1a>
8009e86: 2300 movs r3, #0
}
8009e88: 4618 mov r0, r3
8009e8a: 46bd mov sp, r7
8009e8c: f85d 7b04 ldr.w r7, [sp], #4
8009e90: 4770 bx lr
08009e92 <LL_RCC_PLL_GetN>:
* @brief Get Main PLL multiplication factor for VCO
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
* @retval Between 6 and 127
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
{
8009e92: b480 push {r7}
8009e94: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8009e96: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009e9a: 68db ldr r3, [r3, #12]
8009e9c: 0a1b lsrs r3, r3, #8
8009e9e: f003 037f and.w r3, r3, #127 @ 0x7f
}
8009ea2: 4618 mov r0, r3
8009ea4: 46bd mov sp, r7
8009ea6: f85d 7b04 ldr.w r7, [sp], #4
8009eaa: 4770 bx lr
08009eac <LL_RCC_PLL_GetR>:
* @arg @ref LL_RCC_PLLR_DIV_6
* @arg @ref LL_RCC_PLLR_DIV_7
* @arg @ref LL_RCC_PLLR_DIV_8
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
{
8009eac: b480 push {r7}
8009eae: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
8009eb0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009eb4: 68db ldr r3, [r3, #12]
8009eb6: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000
}
8009eba: 4618 mov r0, r3
8009ebc: 46bd mov sp, r7
8009ebe: f85d 7b04 ldr.w r7, [sp], #4
8009ec2: 4770 bx lr
08009ec4 <LL_RCC_PLL_GetDivider>:
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
{
8009ec4: b480 push {r7}
8009ec6: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
8009ec8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009ecc: 68db ldr r3, [r3, #12]
8009ece: f003 0370 and.w r3, r3, #112 @ 0x70
}
8009ed2: 4618 mov r0, r3
8009ed4: 46bd mov sp, r7
8009ed6: f85d 7b04 ldr.w r7, [sp], #4
8009eda: 4770 bx lr
08009edc <LL_RCC_PLL_GetMainSource>:
* @arg @ref LL_RCC_PLLSOURCE_MSI
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
{
8009edc: b480 push {r7}
8009ede: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
8009ee0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009ee4: 68db ldr r3, [r3, #12]
8009ee6: f003 0303 and.w r3, r3, #3
}
8009eea: 4618 mov r0, r3
8009eec: 46bd mov sp, r7
8009eee: f85d 7b04 ldr.w r7, [sp], #4
8009ef2: 4770 bx lr
08009ef4 <LL_RCC_IsActiveFlag_HPRE>:
* @brief Check if HCLK1 prescaler flag value has been applied or not
* @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void)
{
8009ef4: b480 push {r7}
8009ef6: af00 add r7, sp, #0
return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL);
8009ef8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009efc: 689b ldr r3, [r3, #8]
8009efe: f403 3380 and.w r3, r3, #65536 @ 0x10000
8009f02: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8009f06: d101 bne.n 8009f0c <LL_RCC_IsActiveFlag_HPRE+0x18>
8009f08: 2301 movs r3, #1
8009f0a: e000 b.n 8009f0e <LL_RCC_IsActiveFlag_HPRE+0x1a>
8009f0c: 2300 movs r3, #0
}
8009f0e: 4618 mov r0, r3
8009f10: 46bd mov sp, r7
8009f12: f85d 7b04 ldr.w r7, [sp], #4
8009f16: 4770 bx lr
08009f18 <LL_RCC_IsActiveFlag_C2HPRE>:
* @brief Check if HCLK2 prescaler flag value has been applied or not
* @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void)
{
8009f18: b480 push {r7}
8009f1a: af00 add r7, sp, #0
return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL);
8009f1c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009f20: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
8009f24: f403 3300 and.w r3, r3, #131072 @ 0x20000
8009f28: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8009f2c: d101 bne.n 8009f32 <LL_RCC_IsActiveFlag_C2HPRE+0x1a>
8009f2e: 2301 movs r3, #1
8009f30: e000 b.n 8009f34 <LL_RCC_IsActiveFlag_C2HPRE+0x1c>
8009f32: 2300 movs r3, #0
}
8009f34: 4618 mov r0, r3
8009f36: 46bd mov sp, r7
8009f38: f85d 7b04 ldr.w r7, [sp], #4
8009f3c: 4770 bx lr
08009f3e <LL_RCC_IsActiveFlag_SHDHPRE>:
* @brief Check if HCLK4 prescaler flag value has been applied or not
* @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void)
{
8009f3e: b480 push {r7}
8009f40: af00 add r7, sp, #0
return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL);
8009f42: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009f46: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108
8009f4a: f403 3380 and.w r3, r3, #65536 @ 0x10000
8009f4e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8009f52: d101 bne.n 8009f58 <LL_RCC_IsActiveFlag_SHDHPRE+0x1a>
8009f54: 2301 movs r3, #1
8009f56: e000 b.n 8009f5a <LL_RCC_IsActiveFlag_SHDHPRE+0x1c>
8009f58: 2300 movs r3, #0
}
8009f5a: 4618 mov r0, r3
8009f5c: 46bd mov sp, r7
8009f5e: f85d 7b04 ldr.w r7, [sp], #4
8009f62: 4770 bx lr
08009f64 <LL_RCC_IsActiveFlag_PPRE1>:
* @brief Check if PLCK1 prescaler flag value has been applied or not
* @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void)
{
8009f64: b480 push {r7}
8009f66: af00 add r7, sp, #0
return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL);
8009f68: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009f6c: 689b ldr r3, [r3, #8]
8009f6e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8009f72: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8009f76: d101 bne.n 8009f7c <LL_RCC_IsActiveFlag_PPRE1+0x18>
8009f78: 2301 movs r3, #1
8009f7a: e000 b.n 8009f7e <LL_RCC_IsActiveFlag_PPRE1+0x1a>
8009f7c: 2300 movs r3, #0
}
8009f7e: 4618 mov r0, r3
8009f80: 46bd mov sp, r7
8009f82: f85d 7b04 ldr.w r7, [sp], #4
8009f86: 4770 bx lr
08009f88 <LL_RCC_IsActiveFlag_PPRE2>:
* @brief Check if PLCK2 prescaler flag value has been applied or not
* @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void)
{
8009f88: b480 push {r7}
8009f8a: af00 add r7, sp, #0
return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL);
8009f8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
8009f90: 689b ldr r3, [r3, #8]
8009f92: f403 2380 and.w r3, r3, #262144 @ 0x40000
8009f96: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8009f9a: d101 bne.n 8009fa0 <LL_RCC_IsActiveFlag_PPRE2+0x18>
8009f9c: 2301 movs r3, #1
8009f9e: e000 b.n 8009fa2 <LL_RCC_IsActiveFlag_PPRE2+0x1a>
8009fa0: 2300 movs r3, #0
}
8009fa2: 4618 mov r0, r3
8009fa4: 46bd mov sp, r7
8009fa6: f85d 7b04 ldr.w r7, [sp], #4
8009faa: 4770 bx lr
08009fac <HAL_RCC_OscConfig>:
* @note The PLL is not disabled when used as system clock.
* @note The PLL source is not updated when used as PLLSAI1 clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8009fac: b590 push {r4, r7, lr}
8009fae: b08d sub sp, #52 @ 0x34
8009fb0: af00 add r7, sp, #0
8009fb2: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8009fb4: 687b ldr r3, [r7, #4]
8009fb6: 2b00 cmp r3, #0
8009fb8: d101 bne.n 8009fbe <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8009fba: 2301 movs r3, #1
8009fbc: e363 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*----------------------------- MSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8009fbe: 687b ldr r3, [r7, #4]
8009fc0: 681b ldr r3, [r3, #0]
8009fc2: f003 0320 and.w r3, r3, #32
8009fc6: 2b00 cmp r3, #0
8009fc8: f000 808d beq.w 800a0e6 <HAL_RCC_OscConfig+0x13a>
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* When the MSI is used as system clock it will not be disabled */
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8009fcc: f7ff fe7d bl 8009cca <LL_RCC_GetSysClkSource>
8009fd0: 62f8 str r0, [r7, #44] @ 0x2c
const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
8009fd2: f7ff ff83 bl 8009edc <LL_RCC_PLL_GetMainSource>
8009fd6: 62b8 str r0, [r7, #40] @ 0x28
if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) ||
8009fd8: 6afb ldr r3, [r7, #44] @ 0x2c
8009fda: 2b00 cmp r3, #0
8009fdc: d005 beq.n 8009fea <HAL_RCC_OscConfig+0x3e>
8009fde: 6afb ldr r3, [r7, #44] @ 0x2c
8009fe0: 2b0c cmp r3, #12
8009fe2: d147 bne.n 800a074 <HAL_RCC_OscConfig+0xc8>
((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_MSI)))
8009fe4: 6abb ldr r3, [r7, #40] @ 0x28
8009fe6: 2b01 cmp r3, #1
8009fe8: d144 bne.n 800a074 <HAL_RCC_OscConfig+0xc8>
{
if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)
8009fea: 687b ldr r3, [r7, #4]
8009fec: 69db ldr r3, [r3, #28]
8009fee: 2b00 cmp r3, #0
8009ff0: d101 bne.n 8009ff6 <HAL_RCC_OscConfig+0x4a>
{
return HAL_ERROR;
8009ff2: 2301 movs r3, #1
8009ff4: e347 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
else
{
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the AHB4 clock
and the supply voltage of the device. */
if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
8009ff6: 687b ldr r3, [r7, #4]
8009ff8: 6a5c ldr r4, [r3, #36] @ 0x24
8009ffa: f7ff fe28 bl 8009c4e <LL_RCC_MSI_GetRange>
8009ffe: 4603 mov r3, r0
800a000: 429c cmp r4, r3
800a002: d914 bls.n 800a02e <HAL_RCC_OscConfig+0x82>
{
/* First increase number of wait states update if necessary */
if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
800a004: 687b ldr r3, [r7, #4]
800a006: 6a5b ldr r3, [r3, #36] @ 0x24
800a008: 4618 mov r0, r3
800a00a: f000 fd4b bl 800aaa4 <RCC_SetFlashLatencyFromMSIRange>
800a00e: 4603 mov r3, r0
800a010: 2b00 cmp r3, #0
800a012: d001 beq.n 800a018 <HAL_RCC_OscConfig+0x6c>
{
return HAL_ERROR;
800a014: 2301 movs r3, #1
800a016: e336 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
800a018: 687b ldr r3, [r7, #4]
800a01a: 6a5b ldr r3, [r3, #36] @ 0x24
800a01c: 4618 mov r0, r3
800a01e: f7ff fe02 bl 8009c26 <LL_RCC_MSI_SetRange>
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
800a022: 687b ldr r3, [r7, #4]
800a024: 6a1b ldr r3, [r3, #32]
800a026: 4618 mov r0, r3
800a028: f7ff fe26 bl 8009c78 <LL_RCC_MSI_SetCalibTrimming>
800a02c: e013 b.n 800a056 <HAL_RCC_OscConfig+0xaa>
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
800a02e: 687b ldr r3, [r7, #4]
800a030: 6a5b ldr r3, [r3, #36] @ 0x24
800a032: 4618 mov r0, r3
800a034: f7ff fdf7 bl 8009c26 <LL_RCC_MSI_SetRange>
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
800a038: 687b ldr r3, [r7, #4]
800a03a: 6a1b ldr r3, [r3, #32]
800a03c: 4618 mov r0, r3
800a03e: f7ff fe1b bl 8009c78 <LL_RCC_MSI_SetCalibTrimming>
/* Decrease number of wait states update if necessary */
if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
800a042: 687b ldr r3, [r7, #4]
800a044: 6a5b ldr r3, [r3, #36] @ 0x24
800a046: 4618 mov r0, r3
800a048: f000 fd2c bl 800aaa4 <RCC_SetFlashLatencyFromMSIRange>
800a04c: 4603 mov r3, r0
800a04e: 2b00 cmp r3, #0
800a050: d001 beq.n 800a056 <HAL_RCC_OscConfig+0xaa>
{
return HAL_ERROR;
800a052: 2301 movs r3, #1
800a054: e317 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetHCLKFreq();
800a056: f000 fcc9 bl 800a9ec <HAL_RCC_GetHCLKFreq>
800a05a: 4603 mov r3, r0
800a05c: 4aa4 ldr r2, [pc, #656] @ (800a2f0 <HAL_RCC_OscConfig+0x344>)
800a05e: 6013 str r3, [r2, #0]
if (HAL_InitTick(uwTickPrio) != HAL_OK)
800a060: 4ba4 ldr r3, [pc, #656] @ (800a2f4 <HAL_RCC_OscConfig+0x348>)
800a062: 681b ldr r3, [r3, #0]
800a064: 4618 mov r0, r3
800a066: f7fa ff21 bl 8004eac <HAL_InitTick>
800a06a: 4603 mov r3, r0
800a06c: 2b00 cmp r3, #0
800a06e: d039 beq.n 800a0e4 <HAL_RCC_OscConfig+0x138>
{
return HAL_ERROR;
800a070: 2301 movs r3, #1
800a072: e308 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
}
}
else
{
/* Check the MSI State */
if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
800a074: 687b ldr r3, [r7, #4]
800a076: 69db ldr r3, [r3, #28]
800a078: 2b00 cmp r3, #0
800a07a: d01e beq.n 800a0ba <HAL_RCC_OscConfig+0x10e>
{
/* Enable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
800a07c: f7ff fda4 bl 8009bc8 <LL_RCC_MSI_Enable>
/* Get timeout */
tickstart = HAL_GetTick();
800a080: f7fb f970 bl 8005364 <HAL_GetTick>
800a084: 6278 str r0, [r7, #36] @ 0x24
/* Wait till MSI is ready */
while (LL_RCC_MSI_IsReady() == 0U)
800a086: e008 b.n 800a09a <HAL_RCC_OscConfig+0xee>
{
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
800a088: f7fb f96c bl 8005364 <HAL_GetTick>
800a08c: 4602 mov r2, r0
800a08e: 6a7b ldr r3, [r7, #36] @ 0x24
800a090: 1ad3 subs r3, r2, r3
800a092: 2b02 cmp r3, #2
800a094: d901 bls.n 800a09a <HAL_RCC_OscConfig+0xee>
{
return HAL_TIMEOUT;
800a096: 2303 movs r3, #3
800a098: e2f5 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_MSI_IsReady() == 0U)
800a09a: f7ff fdb3 bl 8009c04 <LL_RCC_MSI_IsReady>
800a09e: 4603 mov r3, r0
800a0a0: 2b00 cmp r3, #0
800a0a2: d0f1 beq.n 800a088 <HAL_RCC_OscConfig+0xdc>
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
800a0a4: 687b ldr r3, [r7, #4]
800a0a6: 6a5b ldr r3, [r3, #36] @ 0x24
800a0a8: 4618 mov r0, r3
800a0aa: f7ff fdbc bl 8009c26 <LL_RCC_MSI_SetRange>
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
800a0ae: 687b ldr r3, [r7, #4]
800a0b0: 6a1b ldr r3, [r3, #32]
800a0b2: 4618 mov r0, r3
800a0b4: f7ff fde0 bl 8009c78 <LL_RCC_MSI_SetCalibTrimming>
800a0b8: e015 b.n 800a0e6 <HAL_RCC_OscConfig+0x13a>
}
else
{
/* Disable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
800a0ba: f7ff fd94 bl 8009be6 <LL_RCC_MSI_Disable>
/* Get timeout */
tickstart = HAL_GetTick();
800a0be: f7fb f951 bl 8005364 <HAL_GetTick>
800a0c2: 6278 str r0, [r7, #36] @ 0x24
/* Wait till MSI is disabled */
while (LL_RCC_MSI_IsReady() != 0U)
800a0c4: e008 b.n 800a0d8 <HAL_RCC_OscConfig+0x12c>
{
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
800a0c6: f7fb f94d bl 8005364 <HAL_GetTick>
800a0ca: 4602 mov r2, r0
800a0cc: 6a7b ldr r3, [r7, #36] @ 0x24
800a0ce: 1ad3 subs r3, r2, r3
800a0d0: 2b02 cmp r3, #2
800a0d2: d901 bls.n 800a0d8 <HAL_RCC_OscConfig+0x12c>
{
return HAL_TIMEOUT;
800a0d4: 2303 movs r3, #3
800a0d6: e2d6 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_MSI_IsReady() != 0U)
800a0d8: f7ff fd94 bl 8009c04 <LL_RCC_MSI_IsReady>
800a0dc: 4603 mov r3, r0
800a0de: 2b00 cmp r3, #0
800a0e0: d1f1 bne.n 800a0c6 <HAL_RCC_OscConfig+0x11a>
800a0e2: e000 b.n 800a0e6 <HAL_RCC_OscConfig+0x13a>
if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)
800a0e4: bf00 nop
}
}
}
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800a0e6: 687b ldr r3, [r7, #4]
800a0e8: 681b ldr r3, [r3, #0]
800a0ea: f003 0301 and.w r3, r3, #1
800a0ee: 2b00 cmp r3, #0
800a0f0: d047 beq.n 800a182 <HAL_RCC_OscConfig+0x1d6>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800a0f2: f7ff fdea bl 8009cca <LL_RCC_GetSysClkSource>
800a0f6: 6238 str r0, [r7, #32]
const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
800a0f8: f7ff fef0 bl 8009edc <LL_RCC_PLL_GetMainSource>
800a0fc: 61f8 str r0, [r7, #28]
if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) ||
800a0fe: 6a3b ldr r3, [r7, #32]
800a100: 2b08 cmp r3, #8
800a102: d005 beq.n 800a110 <HAL_RCC_OscConfig+0x164>
800a104: 6a3b ldr r3, [r7, #32]
800a106: 2b0c cmp r3, #12
800a108: d108 bne.n 800a11c <HAL_RCC_OscConfig+0x170>
((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSE)))
800a10a: 69fb ldr r3, [r7, #28]
800a10c: 2b03 cmp r3, #3
800a10e: d105 bne.n 800a11c <HAL_RCC_OscConfig+0x170>
{
if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
800a110: 687b ldr r3, [r7, #4]
800a112: 685b ldr r3, [r3, #4]
800a114: 2b00 cmp r3, #0
800a116: d134 bne.n 800a182 <HAL_RCC_OscConfig+0x1d6>
{
return HAL_ERROR;
800a118: 2301 movs r3, #1
800a11a: e2b4 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800a11c: 687b ldr r3, [r7, #4]
800a11e: 685b ldr r3, [r3, #4]
800a120: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800a124: d102 bne.n 800a12c <HAL_RCC_OscConfig+0x180>
800a126: f7ff fbd1 bl 80098cc <LL_RCC_HSE_Enable>
800a12a: e001 b.n 800a130 <HAL_RCC_OscConfig+0x184>
800a12c: f7ff fbdd bl 80098ea <LL_RCC_HSE_Disable>
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800a130: 687b ldr r3, [r7, #4]
800a132: 685b ldr r3, [r3, #4]
800a134: 2b00 cmp r3, #0
800a136: d012 beq.n 800a15e <HAL_RCC_OscConfig+0x1b2>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a138: f7fb f914 bl 8005364 <HAL_GetTick>
800a13c: 6278 str r0, [r7, #36] @ 0x24
/* Wait till HSE is ready */
while (LL_RCC_HSE_IsReady() == 0U)
800a13e: e008 b.n 800a152 <HAL_RCC_OscConfig+0x1a6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800a140: f7fb f910 bl 8005364 <HAL_GetTick>
800a144: 4602 mov r2, r0
800a146: 6a7b ldr r3, [r7, #36] @ 0x24
800a148: 1ad3 subs r3, r2, r3
800a14a: 2b64 cmp r3, #100 @ 0x64
800a14c: d901 bls.n 800a152 <HAL_RCC_OscConfig+0x1a6>
{
return HAL_TIMEOUT;
800a14e: 2303 movs r3, #3
800a150: e299 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_HSE_IsReady() == 0U)
800a152: f7ff fbd9 bl 8009908 <LL_RCC_HSE_IsReady>
800a156: 4603 mov r3, r0
800a158: 2b00 cmp r3, #0
800a15a: d0f1 beq.n 800a140 <HAL_RCC_OscConfig+0x194>
800a15c: e011 b.n 800a182 <HAL_RCC_OscConfig+0x1d6>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a15e: f7fb f901 bl 8005364 <HAL_GetTick>
800a162: 6278 str r0, [r7, #36] @ 0x24
/* Wait till HSE is disabled */
while (LL_RCC_HSE_IsReady() != 0U)
800a164: e008 b.n 800a178 <HAL_RCC_OscConfig+0x1cc>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800a166: f7fb f8fd bl 8005364 <HAL_GetTick>
800a16a: 4602 mov r2, r0
800a16c: 6a7b ldr r3, [r7, #36] @ 0x24
800a16e: 1ad3 subs r3, r2, r3
800a170: 2b64 cmp r3, #100 @ 0x64
800a172: d901 bls.n 800a178 <HAL_RCC_OscConfig+0x1cc>
{
return HAL_TIMEOUT;
800a174: 2303 movs r3, #3
800a176: e286 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_HSE_IsReady() != 0U)
800a178: f7ff fbc6 bl 8009908 <LL_RCC_HSE_IsReady>
800a17c: 4603 mov r3, r0
800a17e: 2b00 cmp r3, #0
800a180: d1f1 bne.n 800a166 <HAL_RCC_OscConfig+0x1ba>
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800a182: 687b ldr r3, [r7, #4]
800a184: 681b ldr r3, [r3, #0]
800a186: f003 0302 and.w r3, r3, #2
800a18a: 2b00 cmp r3, #0
800a18c: d04c beq.n 800a228 <HAL_RCC_OscConfig+0x27c>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800a18e: f7ff fd9c bl 8009cca <LL_RCC_GetSysClkSource>
800a192: 61b8 str r0, [r7, #24]
const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
800a194: f7ff fea2 bl 8009edc <LL_RCC_PLL_GetMainSource>
800a198: 6178 str r0, [r7, #20]
if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) ||
800a19a: 69bb ldr r3, [r7, #24]
800a19c: 2b04 cmp r3, #4
800a19e: d005 beq.n 800a1ac <HAL_RCC_OscConfig+0x200>
800a1a0: 69bb ldr r3, [r7, #24]
800a1a2: 2b0c cmp r3, #12
800a1a4: d10e bne.n 800a1c4 <HAL_RCC_OscConfig+0x218>
((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSI)))
800a1a6: 697b ldr r3, [r7, #20]
800a1a8: 2b02 cmp r3, #2
800a1aa: d10b bne.n 800a1c4 <HAL_RCC_OscConfig+0x218>
{
/* When HSI is used as system clock it will not be disabled */
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
800a1ac: 687b ldr r3, [r7, #4]
800a1ae: 68db ldr r3, [r3, #12]
800a1b0: 2b00 cmp r3, #0
800a1b2: d101 bne.n 800a1b8 <HAL_RCC_OscConfig+0x20c>
{
return HAL_ERROR;
800a1b4: 2301 movs r3, #1
800a1b6: e266 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800a1b8: 687b ldr r3, [r7, #4]
800a1ba: 691b ldr r3, [r3, #16]
800a1bc: 4618 mov r0, r3
800a1be: f7ff fbe5 bl 800998c <LL_RCC_HSI_SetCalibTrimming>
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
800a1c2: e031 b.n 800a228 <HAL_RCC_OscConfig+0x27c>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800a1c4: 687b ldr r3, [r7, #4]
800a1c6: 68db ldr r3, [r3, #12]
800a1c8: 2b00 cmp r3, #0
800a1ca: d019 beq.n 800a200 <HAL_RCC_OscConfig+0x254>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800a1cc: f7ff fbae bl 800992c <LL_RCC_HSI_Enable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a1d0: f7fb f8c8 bl 8005364 <HAL_GetTick>
800a1d4: 6278 str r0, [r7, #36] @ 0x24
/* Wait till HSI is ready */
while (LL_RCC_HSI_IsReady() == 0U)
800a1d6: e008 b.n 800a1ea <HAL_RCC_OscConfig+0x23e>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800a1d8: f7fb f8c4 bl 8005364 <HAL_GetTick>
800a1dc: 4602 mov r2, r0
800a1de: 6a7b ldr r3, [r7, #36] @ 0x24
800a1e0: 1ad3 subs r3, r2, r3
800a1e2: 2b02 cmp r3, #2
800a1e4: d901 bls.n 800a1ea <HAL_RCC_OscConfig+0x23e>
{
return HAL_TIMEOUT;
800a1e6: 2303 movs r3, #3
800a1e8: e24d b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_HSI_IsReady() == 0U)
800a1ea: f7ff fbbd bl 8009968 <LL_RCC_HSI_IsReady>
800a1ee: 4603 mov r3, r0
800a1f0: 2b00 cmp r3, #0
800a1f2: d0f1 beq.n 800a1d8 <HAL_RCC_OscConfig+0x22c>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800a1f4: 687b ldr r3, [r7, #4]
800a1f6: 691b ldr r3, [r3, #16]
800a1f8: 4618 mov r0, r3
800a1fa: f7ff fbc7 bl 800998c <LL_RCC_HSI_SetCalibTrimming>
800a1fe: e013 b.n 800a228 <HAL_RCC_OscConfig+0x27c>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800a200: f7ff fba3 bl 800994a <LL_RCC_HSI_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a204: f7fb f8ae bl 8005364 <HAL_GetTick>
800a208: 6278 str r0, [r7, #36] @ 0x24
/* Wait till HSI is disabled */
while (LL_RCC_HSI_IsReady() != 0U)
800a20a: e008 b.n 800a21e <HAL_RCC_OscConfig+0x272>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800a20c: f7fb f8aa bl 8005364 <HAL_GetTick>
800a210: 4602 mov r2, r0
800a212: 6a7b ldr r3, [r7, #36] @ 0x24
800a214: 1ad3 subs r3, r2, r3
800a216: 2b02 cmp r3, #2
800a218: d901 bls.n 800a21e <HAL_RCC_OscConfig+0x272>
{
return HAL_TIMEOUT;
800a21a: 2303 movs r3, #3
800a21c: e233 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_HSI_IsReady() != 0U)
800a21e: f7ff fba3 bl 8009968 <LL_RCC_HSI_IsReady>
800a222: 4603 mov r3, r0
800a224: 2b00 cmp r3, #0
800a226: d1f1 bne.n 800a20c <HAL_RCC_OscConfig+0x260>
}
}
}
/*------------------------------ LSI Configuration (LSI1 or LSI2) -------------------------*/
if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
800a228: 687b ldr r3, [r7, #4]
800a22a: 681b ldr r3, [r3, #0]
800a22c: f003 0308 and.w r3, r3, #8
800a230: 2b00 cmp r3, #0
800a232: d106 bne.n 800a242 <HAL_RCC_OscConfig+0x296>
(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2))
800a234: 687b ldr r3, [r7, #4]
800a236: 681b ldr r3, [r3, #0]
800a238: f003 0310 and.w r3, r3, #16
if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
800a23c: 2b00 cmp r3, #0
800a23e: f000 80a3 beq.w 800a388 <HAL_RCC_OscConfig+0x3dc>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
800a242: 687b ldr r3, [r7, #4]
800a244: 695b ldr r3, [r3, #20]
800a246: 2b00 cmp r3, #0
800a248: d076 beq.n 800a338 <HAL_RCC_OscConfig+0x38c>
{
/*------------------------------ LSI2 selected by default (when Switch ON) -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2)
800a24a: 687b ldr r3, [r7, #4]
800a24c: 681b ldr r3, [r3, #0]
800a24e: f003 0310 and.w r3, r3, #16
800a252: 2b00 cmp r3, #0
800a254: d046 beq.n 800a2e4 <HAL_RCC_OscConfig+0x338>
{
assert_param(IS_RCC_LSI2_CALIBRATION_VALUE(RCC_OscInitStruct->LSI2CalibrationValue));
/* 1. Check LSI1 state and enable if required */
if (LL_RCC_LSI1_IsReady() == 0U)
800a256: f7ff fc5a bl 8009b0e <LL_RCC_LSI1_IsReady>
800a25a: 4603 mov r3, r0
800a25c: 2b00 cmp r3, #0
800a25e: d113 bne.n 800a288 <HAL_RCC_OscConfig+0x2dc>
{
/* This is required to enable LSI1 before enabling LSI2 */
__HAL_RCC_LSI1_ENABLE();
800a260: f7ff fc33 bl 8009aca <LL_RCC_LSI1_Enable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a264: f7fb f87e bl 8005364 <HAL_GetTick>
800a268: 6278 str r0, [r7, #36] @ 0x24
/* Wait till LSI1 is ready */
while (LL_RCC_LSI1_IsReady() == 0U)
800a26a: e008 b.n 800a27e <HAL_RCC_OscConfig+0x2d2>
{
if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
800a26c: f7fb f87a bl 8005364 <HAL_GetTick>
800a270: 4602 mov r2, r0
800a272: 6a7b ldr r3, [r7, #36] @ 0x24
800a274: 1ad3 subs r3, r2, r3
800a276: 2b02 cmp r3, #2
800a278: d901 bls.n 800a27e <HAL_RCC_OscConfig+0x2d2>
{
return HAL_TIMEOUT;
800a27a: 2303 movs r3, #3
800a27c: e203 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSI1_IsReady() == 0U)
800a27e: f7ff fc46 bl 8009b0e <LL_RCC_LSI1_IsReady>
800a282: 4603 mov r3, r0
800a284: 2b00 cmp r3, #0
800a286: d0f1 beq.n 800a26c <HAL_RCC_OscConfig+0x2c0>
}
}
}
/* 2. Enable the Internal Low Speed oscillator (LSI2) and set trimming value */
__HAL_RCC_LSI2_ENABLE();
800a288: f7ff fc53 bl 8009b32 <LL_RCC_LSI2_Enable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a28c: f7fb f86a bl 8005364 <HAL_GetTick>
800a290: 6278 str r0, [r7, #36] @ 0x24
/* Wait till LSI2 is ready */
while (LL_RCC_LSI2_IsReady() == 0U)
800a292: e008 b.n 800a2a6 <HAL_RCC_OscConfig+0x2fa>
{
if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
800a294: f7fb f866 bl 8005364 <HAL_GetTick>
800a298: 4602 mov r2, r0
800a29a: 6a7b ldr r3, [r7, #36] @ 0x24
800a29c: 1ad3 subs r3, r2, r3
800a29e: 2b03 cmp r3, #3
800a2a0: d901 bls.n 800a2a6 <HAL_RCC_OscConfig+0x2fa>
{
return HAL_TIMEOUT;
800a2a2: 2303 movs r3, #3
800a2a4: e1ef b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSI2_IsReady() == 0U)
800a2a6: f7ff fc66 bl 8009b76 <LL_RCC_LSI2_IsReady>
800a2aa: 4603 mov r3, r0
800a2ac: 2b00 cmp r3, #0
800a2ae: d0f1 beq.n 800a294 <HAL_RCC_OscConfig+0x2e8>
}
}
/* Adjusts the Internal Low Spee oscillator (LSI2) calibration value */
__HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->LSI2CalibrationValue);
800a2b0: 687b ldr r3, [r7, #4]
800a2b2: 699b ldr r3, [r3, #24]
800a2b4: 4618 mov r0, r3
800a2b6: f7ff fc70 bl 8009b9a <LL_RCC_LSI2_SetTrimming>
/* 3. Disable LSI1 */
/* LSI1 was initially not enable, require to disable it */
__HAL_RCC_LSI1_DISABLE();
800a2ba: f7ff fc17 bl 8009aec <LL_RCC_LSI1_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a2be: f7fb f851 bl 8005364 <HAL_GetTick>
800a2c2: 6278 str r0, [r7, #36] @ 0x24
/* Wait till LSI1 is disabled */
while (LL_RCC_LSI1_IsReady() != 0U)
800a2c4: e008 b.n 800a2d8 <HAL_RCC_OscConfig+0x32c>
{
if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
800a2c6: f7fb f84d bl 8005364 <HAL_GetTick>
800a2ca: 4602 mov r2, r0
800a2cc: 6a7b ldr r3, [r7, #36] @ 0x24
800a2ce: 1ad3 subs r3, r2, r3
800a2d0: 2b02 cmp r3, #2
800a2d2: d901 bls.n 800a2d8 <HAL_RCC_OscConfig+0x32c>
{
return HAL_TIMEOUT;
800a2d4: 2303 movs r3, #3
800a2d6: e1d6 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSI1_IsReady() != 0U)
800a2d8: f7ff fc19 bl 8009b0e <LL_RCC_LSI1_IsReady>
800a2dc: 4603 mov r3, r0
800a2de: 2b00 cmp r3, #0
800a2e0: d1f1 bne.n 800a2c6 <HAL_RCC_OscConfig+0x31a>
800a2e2: e051 b.n 800a388 <HAL_RCC_OscConfig+0x3dc>
else
{
/*------------------------------ LSI1 selected (only if LSI2 OFF)-------------------------*/
/* 1. Enable the Internal Low Speed oscillator (LSI1). */
__HAL_RCC_LSI1_ENABLE();
800a2e4: f7ff fbf1 bl 8009aca <LL_RCC_LSI1_Enable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a2e8: f7fb f83c bl 8005364 <HAL_GetTick>
800a2ec: 6278 str r0, [r7, #36] @ 0x24
/* Wait till LSI1 is ready */
while (LL_RCC_LSI1_IsReady() == 0U)
800a2ee: e00c b.n 800a30a <HAL_RCC_OscConfig+0x35e>
800a2f0: 2000000c .word 0x2000000c
800a2f4: 20000010 .word 0x20000010
{
if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
800a2f8: f7fb f834 bl 8005364 <HAL_GetTick>
800a2fc: 4602 mov r2, r0
800a2fe: 6a7b ldr r3, [r7, #36] @ 0x24
800a300: 1ad3 subs r3, r2, r3
800a302: 2b02 cmp r3, #2
800a304: d901 bls.n 800a30a <HAL_RCC_OscConfig+0x35e>
{
return HAL_TIMEOUT;
800a306: 2303 movs r3, #3
800a308: e1bd b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSI1_IsReady() == 0U)
800a30a: f7ff fc00 bl 8009b0e <LL_RCC_LSI1_IsReady>
800a30e: 4603 mov r3, r0
800a310: 2b00 cmp r3, #0
800a312: d0f1 beq.n 800a2f8 <HAL_RCC_OscConfig+0x34c>
}
}
/*2. Switch OFF LSI2*/
/* Disable the Internal Low Speed oscillator (LSI2). */
__HAL_RCC_LSI2_DISABLE();
800a314: f7ff fc1e bl 8009b54 <LL_RCC_LSI2_Disable>
/* Wait till LSI2 is disabled */
while (LL_RCC_LSI2_IsReady() != 0U)
800a318: e008 b.n 800a32c <HAL_RCC_OscConfig+0x380>
{
if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
800a31a: f7fb f823 bl 8005364 <HAL_GetTick>
800a31e: 4602 mov r2, r0
800a320: 6a7b ldr r3, [r7, #36] @ 0x24
800a322: 1ad3 subs r3, r2, r3
800a324: 2b03 cmp r3, #3
800a326: d901 bls.n 800a32c <HAL_RCC_OscConfig+0x380>
{
return HAL_TIMEOUT;
800a328: 2303 movs r3, #3
800a32a: e1ac b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSI2_IsReady() != 0U)
800a32c: f7ff fc23 bl 8009b76 <LL_RCC_LSI2_IsReady>
800a330: 4603 mov r3, r0
800a332: 2b00 cmp r3, #0
800a334: d1f1 bne.n 800a31a <HAL_RCC_OscConfig+0x36e>
800a336: e027 b.n 800a388 <HAL_RCC_OscConfig+0x3dc>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI2). */
__HAL_RCC_LSI2_DISABLE();
800a338: f7ff fc0c bl 8009b54 <LL_RCC_LSI2_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a33c: f7fb f812 bl 8005364 <HAL_GetTick>
800a340: 6278 str r0, [r7, #36] @ 0x24
/* Wait till LSI2 is disabled */
while (LL_RCC_LSI2_IsReady() != 0U)
800a342: e008 b.n 800a356 <HAL_RCC_OscConfig+0x3aa>
{
if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
800a344: f7fb f80e bl 8005364 <HAL_GetTick>
800a348: 4602 mov r2, r0
800a34a: 6a7b ldr r3, [r7, #36] @ 0x24
800a34c: 1ad3 subs r3, r2, r3
800a34e: 2b03 cmp r3, #3
800a350: d901 bls.n 800a356 <HAL_RCC_OscConfig+0x3aa>
{
return HAL_TIMEOUT;
800a352: 2303 movs r3, #3
800a354: e197 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSI2_IsReady() != 0U)
800a356: f7ff fc0e bl 8009b76 <LL_RCC_LSI2_IsReady>
800a35a: 4603 mov r3, r0
800a35c: 2b00 cmp r3, #0
800a35e: d1f1 bne.n 800a344 <HAL_RCC_OscConfig+0x398>
}
}
/* Disable the Internal Low Speed oscillator (LSI1). */
__HAL_RCC_LSI1_DISABLE();
800a360: f7ff fbc4 bl 8009aec <LL_RCC_LSI1_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a364: f7fa fffe bl 8005364 <HAL_GetTick>
800a368: 6278 str r0, [r7, #36] @ 0x24
/* Wait till LSI1 is disabled */
while (LL_RCC_LSI1_IsReady() != 0U)
800a36a: e008 b.n 800a37e <HAL_RCC_OscConfig+0x3d2>
{
if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
800a36c: f7fa fffa bl 8005364 <HAL_GetTick>
800a370: 4602 mov r2, r0
800a372: 6a7b ldr r3, [r7, #36] @ 0x24
800a374: 1ad3 subs r3, r2, r3
800a376: 2b02 cmp r3, #2
800a378: d901 bls.n 800a37e <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
800a37a: 2303 movs r3, #3
800a37c: e183 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSI1_IsReady() != 0U)
800a37e: f7ff fbc6 bl 8009b0e <LL_RCC_LSI1_IsReady>
800a382: 4603 mov r3, r0
800a384: 2b00 cmp r3, #0
800a386: d1f1 bne.n 800a36c <HAL_RCC_OscConfig+0x3c0>
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800a388: 687b ldr r3, [r7, #4]
800a38a: 681b ldr r3, [r3, #0]
800a38c: f003 0304 and.w r3, r3, #4
800a390: 2b00 cmp r3, #0
800a392: d05b beq.n 800a44c <HAL_RCC_OscConfig+0x4a0>
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800a394: 4ba7 ldr r3, [pc, #668] @ (800a634 <HAL_RCC_OscConfig+0x688>)
800a396: 681b ldr r3, [r3, #0]
800a398: f403 7380 and.w r3, r3, #256 @ 0x100
800a39c: 2b00 cmp r3, #0
800a39e: d114 bne.n 800a3ca <HAL_RCC_OscConfig+0x41e>
{
/* Enable write access to Backup domain */
HAL_PWR_EnableBkUpAccess();
800a3a0: f7ff fa54 bl 800984c <HAL_PWR_EnableBkUpAccess>
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800a3a4: f7fa ffde bl 8005364 <HAL_GetTick>
800a3a8: 6278 str r0, [r7, #36] @ 0x24
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800a3aa: e008 b.n 800a3be <HAL_RCC_OscConfig+0x412>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800a3ac: f7fa ffda bl 8005364 <HAL_GetTick>
800a3b0: 4602 mov r2, r0
800a3b2: 6a7b ldr r3, [r7, #36] @ 0x24
800a3b4: 1ad3 subs r3, r2, r3
800a3b6: 2b02 cmp r3, #2
800a3b8: d901 bls.n 800a3be <HAL_RCC_OscConfig+0x412>
{
return HAL_TIMEOUT;
800a3ba: 2303 movs r3, #3
800a3bc: e163 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800a3be: 4b9d ldr r3, [pc, #628] @ (800a634 <HAL_RCC_OscConfig+0x688>)
800a3c0: 681b ldr r3, [r3, #0]
800a3c2: f403 7380 and.w r3, r3, #256 @ 0x100
800a3c6: 2b00 cmp r3, #0
800a3c8: d0f0 beq.n 800a3ac <HAL_RCC_OscConfig+0x400>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
800a3ca: 687b ldr r3, [r7, #4]
800a3cc: 689b ldr r3, [r3, #8]
800a3ce: 2b01 cmp r3, #1
800a3d0: d102 bne.n 800a3d8 <HAL_RCC_OscConfig+0x42c>
800a3d2: f7ff fb24 bl 8009a1e <LL_RCC_LSE_Enable>
800a3d6: e00c b.n 800a3f2 <HAL_RCC_OscConfig+0x446>
800a3d8: 687b ldr r3, [r7, #4]
800a3da: 689b ldr r3, [r3, #8]
800a3dc: 2b05 cmp r3, #5
800a3de: d104 bne.n 800a3ea <HAL_RCC_OscConfig+0x43e>
800a3e0: f7ff fb3f bl 8009a62 <LL_RCC_LSE_EnableBypass>
800a3e4: f7ff fb1b bl 8009a1e <LL_RCC_LSE_Enable>
800a3e8: e003 b.n 800a3f2 <HAL_RCC_OscConfig+0x446>
800a3ea: f7ff fb29 bl 8009a40 <LL_RCC_LSE_Disable>
800a3ee: f7ff fb49 bl 8009a84 <LL_RCC_LSE_DisableBypass>
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
800a3f2: 687b ldr r3, [r7, #4]
800a3f4: 689b ldr r3, [r3, #8]
800a3f6: 2b00 cmp r3, #0
800a3f8: d014 beq.n 800a424 <HAL_RCC_OscConfig+0x478>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a3fa: f7fa ffb3 bl 8005364 <HAL_GetTick>
800a3fe: 6278 str r0, [r7, #36] @ 0x24
/* Wait till LSE is ready */
while (LL_RCC_LSE_IsReady() == 0U)
800a400: e00a b.n 800a418 <HAL_RCC_OscConfig+0x46c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800a402: f7fa ffaf bl 8005364 <HAL_GetTick>
800a406: 4602 mov r2, r0
800a408: 6a7b ldr r3, [r7, #36] @ 0x24
800a40a: 1ad3 subs r3, r2, r3
800a40c: f241 3288 movw r2, #5000 @ 0x1388
800a410: 4293 cmp r3, r2
800a412: d901 bls.n 800a418 <HAL_RCC_OscConfig+0x46c>
{
return HAL_TIMEOUT;
800a414: 2303 movs r3, #3
800a416: e136 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSE_IsReady() == 0U)
800a418: f7ff fb45 bl 8009aa6 <LL_RCC_LSE_IsReady>
800a41c: 4603 mov r3, r0
800a41e: 2b00 cmp r3, #0
800a420: d0ef beq.n 800a402 <HAL_RCC_OscConfig+0x456>
800a422: e013 b.n 800a44c <HAL_RCC_OscConfig+0x4a0>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a424: f7fa ff9e bl 8005364 <HAL_GetTick>
800a428: 6278 str r0, [r7, #36] @ 0x24
/* Wait till LSE is disabled */
while (LL_RCC_LSE_IsReady() != 0U)
800a42a: e00a b.n 800a442 <HAL_RCC_OscConfig+0x496>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800a42c: f7fa ff9a bl 8005364 <HAL_GetTick>
800a430: 4602 mov r2, r0
800a432: 6a7b ldr r3, [r7, #36] @ 0x24
800a434: 1ad3 subs r3, r2, r3
800a436: f241 3288 movw r2, #5000 @ 0x1388
800a43a: 4293 cmp r3, r2
800a43c: d901 bls.n 800a442 <HAL_RCC_OscConfig+0x496>
{
return HAL_TIMEOUT;
800a43e: 2303 movs r3, #3
800a440: e121 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_LSE_IsReady() != 0U)
800a442: f7ff fb30 bl 8009aa6 <LL_RCC_LSE_IsReady>
800a446: 4603 mov r3, r0
800a448: 2b00 cmp r3, #0
800a44a: d1ef bne.n 800a42c <HAL_RCC_OscConfig+0x480>
}
}
#if defined(RCC_HSI48_SUPPORT)
/*------------------------------ HSI48 Configuration -----------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
800a44c: 687b ldr r3, [r7, #4]
800a44e: 681b ldr r3, [r3, #0]
800a450: f003 0340 and.w r3, r3, #64 @ 0x40
800a454: 2b00 cmp r3, #0
800a456: d02c beq.n 800a4b2 <HAL_RCC_OscConfig+0x506>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the HSI State */
if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
800a458: 687b ldr r3, [r7, #4]
800a45a: 6a9b ldr r3, [r3, #40] @ 0x28
800a45c: 2b00 cmp r3, #0
800a45e: d014 beq.n 800a48a <HAL_RCC_OscConfig+0x4de>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
800a460: f7ff faa9 bl 80099b6 <LL_RCC_HSI48_Enable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a464: f7fa ff7e bl 8005364 <HAL_GetTick>
800a468: 6278 str r0, [r7, #36] @ 0x24
/* Wait till HSI48 is ready */
while (LL_RCC_HSI48_IsReady() == 0U)
800a46a: e008 b.n 800a47e <HAL_RCC_OscConfig+0x4d2>
{
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
800a46c: f7fa ff7a bl 8005364 <HAL_GetTick>
800a470: 4602 mov r2, r0
800a472: 6a7b ldr r3, [r7, #36] @ 0x24
800a474: 1ad3 subs r3, r2, r3
800a476: 2b02 cmp r3, #2
800a478: d901 bls.n 800a47e <HAL_RCC_OscConfig+0x4d2>
{
return HAL_TIMEOUT;
800a47a: 2303 movs r3, #3
800a47c: e103 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_HSI48_IsReady() == 0U)
800a47e: f7ff fabc bl 80099fa <LL_RCC_HSI48_IsReady>
800a482: 4603 mov r3, r0
800a484: 2b00 cmp r3, #0
800a486: d0f1 beq.n 800a46c <HAL_RCC_OscConfig+0x4c0>
800a488: e013 b.n 800a4b2 <HAL_RCC_OscConfig+0x506>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
800a48a: f7ff faa5 bl 80099d8 <LL_RCC_HSI48_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a48e: f7fa ff69 bl 8005364 <HAL_GetTick>
800a492: 6278 str r0, [r7, #36] @ 0x24
/* Wait till HSI48 is disabled */
while (LL_RCC_HSI48_IsReady() != 0U)
800a494: e008 b.n 800a4a8 <HAL_RCC_OscConfig+0x4fc>
{
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
800a496: f7fa ff65 bl 8005364 <HAL_GetTick>
800a49a: 4602 mov r2, r0
800a49c: 6a7b ldr r3, [r7, #36] @ 0x24
800a49e: 1ad3 subs r3, r2, r3
800a4a0: 2b02 cmp r3, #2
800a4a2: d901 bls.n 800a4a8 <HAL_RCC_OscConfig+0x4fc>
{
return HAL_TIMEOUT;
800a4a4: 2303 movs r3, #3
800a4a6: e0ee b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (LL_RCC_HSI48_IsReady() != 0U)
800a4a8: f7ff faa7 bl 80099fa <LL_RCC_HSI48_IsReady>
800a4ac: 4603 mov r3, r0
800a4ae: 2b00 cmp r3, #0
800a4b0: d1f1 bne.n 800a496 <HAL_RCC_OscConfig+0x4ea>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
800a4b2: 687b ldr r3, [r7, #4]
800a4b4: 6adb ldr r3, [r3, #44] @ 0x2c
800a4b6: 2b00 cmp r3, #0
800a4b8: f000 80e4 beq.w 800a684 <HAL_RCC_OscConfig+0x6d8>
{
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800a4bc: f7ff fc05 bl 8009cca <LL_RCC_GetSysClkSource>
800a4c0: 6138 str r0, [r7, #16]
const uint32_t temp_pllconfig = RCC->PLLCFGR;
800a4c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a4c6: 68db ldr r3, [r3, #12]
800a4c8: 60fb str r3, [r7, #12]
/* PLL On ? */
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
800a4ca: 687b ldr r3, [r7, #4]
800a4cc: 6adb ldr r3, [r3, #44] @ 0x2c
800a4ce: 2b02 cmp r3, #2
800a4d0: f040 80b4 bne.w 800a63c <HAL_RCC_OscConfig+0x690>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Do nothing if PLL configuration is unchanged */
if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800a4d4: 68fb ldr r3, [r7, #12]
800a4d6: f003 0203 and.w r2, r3, #3
800a4da: 687b ldr r3, [r7, #4]
800a4dc: 6b1b ldr r3, [r3, #48] @ 0x30
800a4de: 429a cmp r2, r3
800a4e0: d123 bne.n 800a52a <HAL_RCC_OscConfig+0x57e>
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
800a4e2: 68fb ldr r3, [r7, #12]
800a4e4: f003 0270 and.w r2, r3, #112 @ 0x70
800a4e8: 687b ldr r3, [r7, #4]
800a4ea: 6b5b ldr r3, [r3, #52] @ 0x34
if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800a4ec: 429a cmp r2, r3
800a4ee: d11c bne.n 800a52a <HAL_RCC_OscConfig+0x57e>
((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
800a4f0: 68fb ldr r3, [r7, #12]
800a4f2: 0a1b lsrs r3, r3, #8
800a4f4: f003 027f and.w r2, r3, #127 @ 0x7f
800a4f8: 687b ldr r3, [r7, #4]
800a4fa: 6b9b ldr r3, [r3, #56] @ 0x38
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
800a4fc: 429a cmp r2, r3
800a4fe: d114 bne.n 800a52a <HAL_RCC_OscConfig+0x57e>
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
800a500: 68fb ldr r3, [r7, #12]
800a502: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000
800a506: 687b ldr r3, [r7, #4]
800a508: 6bdb ldr r3, [r3, #60] @ 0x3c
((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
800a50a: 429a cmp r2, r3
800a50c: d10d bne.n 800a52a <HAL_RCC_OscConfig+0x57e>
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
800a50e: 68fb ldr r3, [r7, #12]
800a510: f003 6260 and.w r2, r3, #234881024 @ 0xe000000
800a514: 687b ldr r3, [r7, #4]
800a516: 6c1b ldr r3, [r3, #64] @ 0x40
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
800a518: 429a cmp r2, r3
800a51a: d106 bne.n 800a52a <HAL_RCC_OscConfig+0x57e>
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
800a51c: 68fb ldr r3, [r7, #12]
800a51e: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000
800a522: 687b ldr r3, [r7, #4]
800a524: 6c5b ldr r3, [r3, #68] @ 0x44
(READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
800a526: 429a cmp r2, r3
800a528: d05d beq.n 800a5e6 <HAL_RCC_OscConfig+0x63a>
{
/* Check if the PLL is used as system clock or not */
if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800a52a: 693b ldr r3, [r7, #16]
800a52c: 2b0c cmp r3, #12
800a52e: d058 beq.n 800a5e2 <HAL_RCC_OscConfig+0x636>
{
#if defined(SAI1)
/* Check if main PLL can be updated */
/* Not possible if the source is shared by other enabled PLLSAIx */
if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
800a530: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a534: 681b ldr r3, [r3, #0]
800a536: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
800a53a: 2b00 cmp r3, #0
800a53c: d001 beq.n 800a542 <HAL_RCC_OscConfig+0x596>
{
return HAL_ERROR;
800a53e: 2301 movs r3, #1
800a540: e0a1 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
}
else
#endif /* SAI1 */
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800a542: f7ff fc85 bl 8009e50 <LL_RCC_PLL_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a546: f7fa ff0d bl 8005364 <HAL_GetTick>
800a54a: 6278 str r0, [r7, #36] @ 0x24
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
800a54c: e008 b.n 800a560 <HAL_RCC_OscConfig+0x5b4>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800a54e: f7fa ff09 bl 8005364 <HAL_GetTick>
800a552: 4602 mov r2, r0
800a554: 6a7b ldr r3, [r7, #36] @ 0x24
800a556: 1ad3 subs r3, r2, r3
800a558: 2b02 cmp r3, #2
800a55a: d901 bls.n 800a560 <HAL_RCC_OscConfig+0x5b4>
{
return HAL_TIMEOUT;
800a55c: 2303 movs r3, #3
800a55e: e092 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
800a560: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a564: 681b ldr r3, [r3, #0]
800a566: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800a56a: 2b00 cmp r3, #0
800a56c: d1ef bne.n 800a54e <HAL_RCC_OscConfig+0x5a2>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
800a56e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a572: 68da ldr r2, [r3, #12]
800a574: 4b30 ldr r3, [pc, #192] @ (800a638 <HAL_RCC_OscConfig+0x68c>)
800a576: 4013 ands r3, r2
800a578: 687a ldr r2, [r7, #4]
800a57a: 6b11 ldr r1, [r2, #48] @ 0x30
800a57c: 687a ldr r2, [r7, #4]
800a57e: 6b52 ldr r2, [r2, #52] @ 0x34
800a580: 4311 orrs r1, r2
800a582: 687a ldr r2, [r7, #4]
800a584: 6b92 ldr r2, [r2, #56] @ 0x38
800a586: 0212 lsls r2, r2, #8
800a588: 4311 orrs r1, r2
800a58a: 687a ldr r2, [r7, #4]
800a58c: 6bd2 ldr r2, [r2, #60] @ 0x3c
800a58e: 4311 orrs r1, r2
800a590: 687a ldr r2, [r7, #4]
800a592: 6c12 ldr r2, [r2, #64] @ 0x40
800a594: 4311 orrs r1, r2
800a596: 687a ldr r2, [r7, #4]
800a598: 6c52 ldr r2, [r2, #68] @ 0x44
800a59a: 430a orrs r2, r1
800a59c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800a5a0: 4313 orrs r3, r2
800a5a2: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800a5a4: f7ff fc45 bl 8009e32 <LL_RCC_PLL_Enable>
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
800a5a8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a5ac: 68db ldr r3, [r3, #12]
800a5ae: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800a5b2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800a5b6: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a5b8: f7fa fed4 bl 8005364 <HAL_GetTick>
800a5bc: 6278 str r0, [r7, #36] @ 0x24
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800a5be: e008 b.n 800a5d2 <HAL_RCC_OscConfig+0x626>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800a5c0: f7fa fed0 bl 8005364 <HAL_GetTick>
800a5c4: 4602 mov r2, r0
800a5c6: 6a7b ldr r3, [r7, #36] @ 0x24
800a5c8: 1ad3 subs r3, r2, r3
800a5ca: 2b02 cmp r3, #2
800a5cc: d901 bls.n 800a5d2 <HAL_RCC_OscConfig+0x626>
{
return HAL_TIMEOUT;
800a5ce: 2303 movs r3, #3
800a5d0: e059 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800a5d2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a5d6: 681b ldr r3, [r3, #0]
800a5d8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800a5dc: 2b00 cmp r3, #0
800a5de: d0ef beq.n 800a5c0 <HAL_RCC_OscConfig+0x614>
if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800a5e0: e050 b.n 800a684 <HAL_RCC_OscConfig+0x6d8>
}
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
800a5e2: 2301 movs r3, #1
800a5e4: e04f b.n 800a686 <HAL_RCC_OscConfig+0x6da>
}
else
{
/* PLL configuration is unchanged */
/* Re-enable PLL if it was disabled (ie. low power mode) */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800a5e6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a5ea: 681b ldr r3, [r3, #0]
800a5ec: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800a5f0: 2b00 cmp r3, #0
800a5f2: d147 bne.n 800a684 <HAL_RCC_OscConfig+0x6d8>
{
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800a5f4: f7ff fc1d bl 8009e32 <LL_RCC_PLL_Enable>
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
800a5f8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a5fc: 68db ldr r3, [r3, #12]
800a5fe: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800a602: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800a606: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a608: f7fa feac bl 8005364 <HAL_GetTick>
800a60c: 6278 str r0, [r7, #36] @ 0x24
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800a60e: e008 b.n 800a622 <HAL_RCC_OscConfig+0x676>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800a610: f7fa fea8 bl 8005364 <HAL_GetTick>
800a614: 4602 mov r2, r0
800a616: 6a7b ldr r3, [r7, #36] @ 0x24
800a618: 1ad3 subs r3, r2, r3
800a61a: 2b02 cmp r3, #2
800a61c: d901 bls.n 800a622 <HAL_RCC_OscConfig+0x676>
{
return HAL_TIMEOUT;
800a61e: 2303 movs r3, #3
800a620: e031 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800a622: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a626: 681b ldr r3, [r3, #0]
800a628: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800a62c: 2b00 cmp r3, #0
800a62e: d0ef beq.n 800a610 <HAL_RCC_OscConfig+0x664>
800a630: e028 b.n 800a684 <HAL_RCC_OscConfig+0x6d8>
800a632: bf00 nop
800a634: 58000400 .word 0x58000400
800a638: 11c1808c .word 0x11c1808c
}
}
else
{
/* Check that PLL is not used as system clock or not */
if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800a63c: 693b ldr r3, [r7, #16]
800a63e: 2b0c cmp r3, #12
800a640: d01e beq.n 800a680 <HAL_RCC_OscConfig+0x6d4>
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800a642: f7ff fc05 bl 8009e50 <LL_RCC_PLL_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a646: f7fa fe8d bl 8005364 <HAL_GetTick>
800a64a: 6278 str r0, [r7, #36] @ 0x24
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
800a64c: e008 b.n 800a660 <HAL_RCC_OscConfig+0x6b4>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800a64e: f7fa fe89 bl 8005364 <HAL_GetTick>
800a652: 4602 mov r2, r0
800a654: 6a7b ldr r3, [r7, #36] @ 0x24
800a656: 1ad3 subs r3, r2, r3
800a658: 2b02 cmp r3, #2
800a65a: d901 bls.n 800a660 <HAL_RCC_OscConfig+0x6b4>
{
return HAL_TIMEOUT;
800a65c: 2303 movs r3, #3
800a65e: e012 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
800a660: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a664: 681b ldr r3, [r3, #0]
800a666: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800a66a: 2b00 cmp r3, #0
800a66c: d1ef bne.n 800a64e <HAL_RCC_OscConfig+0x6a2>
}
}
/* Disable the PLL source and outputs to save power when PLL is off */
#if defined(SAI1) && defined(USB)
CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN));
800a66e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800a672: 68da ldr r2, [r3, #12]
800a674: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800a678: 4b05 ldr r3, [pc, #20] @ (800a690 <HAL_RCC_OscConfig+0x6e4>)
800a67a: 4013 ands r3, r2
800a67c: 60cb str r3, [r1, #12]
800a67e: e001 b.n 800a684 <HAL_RCC_OscConfig+0x6d8>
#endif /* SAI1 && USB */
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
800a680: 2301 movs r3, #1
800a682: e000 b.n 800a686 <HAL_RCC_OscConfig+0x6da>
}
}
}
return HAL_OK;
800a684: 2300 movs r3, #0
}
800a686: 4618 mov r0, r3
800a688: 3734 adds r7, #52 @ 0x34
800a68a: 46bd mov sp, r7
800a68c: bd90 pop {r4, r7, pc}
800a68e: bf00 nop
800a690: eefefffc .word 0xeefefffc
0800a694 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
800a694: b580 push {r7, lr}
800a696: b084 sub sp, #16
800a698: af00 add r7, sp, #0
800a69a: 6078 str r0, [r7, #4]
800a69c: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
800a69e: 687b ldr r3, [r7, #4]
800a6a0: 2b00 cmp r3, #0
800a6a2: d101 bne.n 800a6a8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
800a6a4: 2301 movs r3, #1
800a6a6: e12d b.n 800a904 <HAL_RCC_ClockConfig+0x270>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the FLASH clock
(HCLK4) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800a6a8: 4b98 ldr r3, [pc, #608] @ (800a90c <HAL_RCC_ClockConfig+0x278>)
800a6aa: 681b ldr r3, [r3, #0]
800a6ac: f003 0307 and.w r3, r3, #7
800a6b0: 683a ldr r2, [r7, #0]
800a6b2: 429a cmp r2, r3
800a6b4: d91b bls.n 800a6ee <HAL_RCC_ClockConfig+0x5a>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800a6b6: 4b95 ldr r3, [pc, #596] @ (800a90c <HAL_RCC_ClockConfig+0x278>)
800a6b8: 681b ldr r3, [r3, #0]
800a6ba: f023 0207 bic.w r2, r3, #7
800a6be: 4993 ldr r1, [pc, #588] @ (800a90c <HAL_RCC_ClockConfig+0x278>)
800a6c0: 683b ldr r3, [r7, #0]
800a6c2: 4313 orrs r3, r2
800a6c4: 600b str r3, [r1, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a6c6: f7fa fe4d bl 8005364 <HAL_GetTick>
800a6ca: 60f8 str r0, [r7, #12]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
while (__HAL_FLASH_GET_LATENCY() != FLatency)
800a6cc: e008 b.n 800a6e0 <HAL_RCC_ClockConfig+0x4c>
{
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
800a6ce: f7fa fe49 bl 8005364 <HAL_GetTick>
800a6d2: 4602 mov r2, r0
800a6d4: 68fb ldr r3, [r7, #12]
800a6d6: 1ad3 subs r3, r2, r3
800a6d8: 2b02 cmp r3, #2
800a6da: d901 bls.n 800a6e0 <HAL_RCC_ClockConfig+0x4c>
{
return HAL_TIMEOUT;
800a6dc: 2303 movs r3, #3
800a6de: e111 b.n 800a904 <HAL_RCC_ClockConfig+0x270>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
800a6e0: 4b8a ldr r3, [pc, #552] @ (800a90c <HAL_RCC_ClockConfig+0x278>)
800a6e2: 681b ldr r3, [r3, #0]
800a6e4: f003 0307 and.w r3, r3, #7
800a6e8: 683a ldr r2, [r7, #0]
800a6ea: 429a cmp r2, r3
800a6ec: d1ef bne.n 800a6ce <HAL_RCC_ClockConfig+0x3a>
}
}
}
/*-------------------------- HCLK1 Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800a6ee: 687b ldr r3, [r7, #4]
800a6f0: 681b ldr r3, [r3, #0]
800a6f2: f003 0302 and.w r3, r3, #2
800a6f6: 2b00 cmp r3, #0
800a6f8: d016 beq.n 800a728 <HAL_RCC_ClockConfig+0x94>
{
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider));
LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider);
800a6fa: 687b ldr r3, [r7, #4]
800a6fc: 689b ldr r3, [r3, #8]
800a6fe: 4618 mov r0, r3
800a700: f7ff faef bl 8009ce2 <LL_RCC_SetAHBPrescaler>
/* HCLK1 prescaler flag when value applied */
tickstart = HAL_GetTick();
800a704: f7fa fe2e bl 8005364 <HAL_GetTick>
800a708: 60f8 str r0, [r7, #12]
while (LL_RCC_IsActiveFlag_HPRE() == 0U)
800a70a: e008 b.n 800a71e <HAL_RCC_ClockConfig+0x8a>
{
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
800a70c: f7fa fe2a bl 8005364 <HAL_GetTick>
800a710: 4602 mov r2, r0
800a712: 68fb ldr r3, [r7, #12]
800a714: 1ad3 subs r3, r2, r3
800a716: 2b02 cmp r3, #2
800a718: d901 bls.n 800a71e <HAL_RCC_ClockConfig+0x8a>
{
return HAL_TIMEOUT;
800a71a: 2303 movs r3, #3
800a71c: e0f2 b.n 800a904 <HAL_RCC_ClockConfig+0x270>
while (LL_RCC_IsActiveFlag_HPRE() == 0U)
800a71e: f7ff fbe9 bl 8009ef4 <LL_RCC_IsActiveFlag_HPRE>
800a722: 4603 mov r3, r0
800a724: 2b00 cmp r3, #0
800a726: d0f1 beq.n 800a70c <HAL_RCC_ClockConfig+0x78>
}
}
}
/*-------------------------- HCLK2 Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2)
800a728: 687b ldr r3, [r7, #4]
800a72a: 681b ldr r3, [r3, #0]
800a72c: f003 0320 and.w r3, r3, #32
800a730: 2b00 cmp r3, #0
800a732: d016 beq.n 800a762 <HAL_RCC_ClockConfig+0xce>
{
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider));
LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider);
800a734: 687b ldr r3, [r7, #4]
800a736: 695b ldr r3, [r3, #20]
800a738: 4618 mov r0, r3
800a73a: f7ff fae6 bl 8009d0a <LL_C2_RCC_SetAHBPrescaler>
/* HCLK2 prescaler flag when value applied */
tickstart = HAL_GetTick();
800a73e: f7fa fe11 bl 8005364 <HAL_GetTick>
800a742: 60f8 str r0, [r7, #12]
while (LL_RCC_IsActiveFlag_C2HPRE() == 0U)
800a744: e008 b.n 800a758 <HAL_RCC_ClockConfig+0xc4>
{
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
800a746: f7fa fe0d bl 8005364 <HAL_GetTick>
800a74a: 4602 mov r2, r0
800a74c: 68fb ldr r3, [r7, #12]
800a74e: 1ad3 subs r3, r2, r3
800a750: 2b02 cmp r3, #2
800a752: d901 bls.n 800a758 <HAL_RCC_ClockConfig+0xc4>
{
return HAL_TIMEOUT;
800a754: 2303 movs r3, #3
800a756: e0d5 b.n 800a904 <HAL_RCC_ClockConfig+0x270>
while (LL_RCC_IsActiveFlag_C2HPRE() == 0U)
800a758: f7ff fbde bl 8009f18 <LL_RCC_IsActiveFlag_C2HPRE>
800a75c: 4603 mov r3, r0
800a75e: 2b00 cmp r3, #0
800a760: d0f1 beq.n 800a746 <HAL_RCC_ClockConfig+0xb2>
}
}
}
/*-------------------------- HCLK4 Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK4) == RCC_CLOCKTYPE_HCLK4)
800a762: 687b ldr r3, [r7, #4]
800a764: 681b ldr r3, [r3, #0]
800a766: f003 0340 and.w r3, r3, #64 @ 0x40
800a76a: 2b00 cmp r3, #0
800a76c: d016 beq.n 800a79c <HAL_RCC_ClockConfig+0x108>
{
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK4Divider));
LL_RCC_SetAHB4Prescaler(RCC_ClkInitStruct->AHBCLK4Divider);
800a76e: 687b ldr r3, [r7, #4]
800a770: 699b ldr r3, [r3, #24]
800a772: 4618 mov r0, r3
800a774: f7ff fadf bl 8009d36 <LL_RCC_SetAHB4Prescaler>
/* AHB shared prescaler flag when value applied */
tickstart = HAL_GetTick();
800a778: f7fa fdf4 bl 8005364 <HAL_GetTick>
800a77c: 60f8 str r0, [r7, #12]
while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U)
800a77e: e008 b.n 800a792 <HAL_RCC_ClockConfig+0xfe>
{
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
800a780: f7fa fdf0 bl 8005364 <HAL_GetTick>
800a784: 4602 mov r2, r0
800a786: 68fb ldr r3, [r7, #12]
800a788: 1ad3 subs r3, r2, r3
800a78a: 2b02 cmp r3, #2
800a78c: d901 bls.n 800a792 <HAL_RCC_ClockConfig+0xfe>
{
return HAL_TIMEOUT;
800a78e: 2303 movs r3, #3
800a790: e0b8 b.n 800a904 <HAL_RCC_ClockConfig+0x270>
while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U)
800a792: f7ff fbd4 bl 8009f3e <LL_RCC_IsActiveFlag_SHDHPRE>
800a796: 4603 mov r3, r0
800a798: 2b00 cmp r3, #0
800a79a: d0f1 beq.n 800a780 <HAL_RCC_ClockConfig+0xec>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800a79c: 687b ldr r3, [r7, #4]
800a79e: 681b ldr r3, [r3, #0]
800a7a0: f003 0304 and.w r3, r3, #4
800a7a4: 2b00 cmp r3, #0
800a7a6: d016 beq.n 800a7d6 <HAL_RCC_ClockConfig+0x142>
{
assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider));
LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider);
800a7a8: 687b ldr r3, [r7, #4]
800a7aa: 68db ldr r3, [r3, #12]
800a7ac: 4618 mov r0, r3
800a7ae: f7ff fad9 bl 8009d64 <LL_RCC_SetAPB1Prescaler>
/* APB1 prescaler flag when value applied */
tickstart = HAL_GetTick();
800a7b2: f7fa fdd7 bl 8005364 <HAL_GetTick>
800a7b6: 60f8 str r0, [r7, #12]
while (LL_RCC_IsActiveFlag_PPRE1() == 0U)
800a7b8: e008 b.n 800a7cc <HAL_RCC_ClockConfig+0x138>
{
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
800a7ba: f7fa fdd3 bl 8005364 <HAL_GetTick>
800a7be: 4602 mov r2, r0
800a7c0: 68fb ldr r3, [r7, #12]
800a7c2: 1ad3 subs r3, r2, r3
800a7c4: 2b02 cmp r3, #2
800a7c6: d901 bls.n 800a7cc <HAL_RCC_ClockConfig+0x138>
{
return HAL_TIMEOUT;
800a7c8: 2303 movs r3, #3
800a7ca: e09b b.n 800a904 <HAL_RCC_ClockConfig+0x270>
while (LL_RCC_IsActiveFlag_PPRE1() == 0U)
800a7cc: f7ff fbca bl 8009f64 <LL_RCC_IsActiveFlag_PPRE1>
800a7d0: 4603 mov r3, r0
800a7d2: 2b00 cmp r3, #0
800a7d4: d0f1 beq.n 800a7ba <HAL_RCC_ClockConfig+0x126>
}
}
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800a7d6: 687b ldr r3, [r7, #4]
800a7d8: 681b ldr r3, [r3, #0]
800a7da: f003 0308 and.w r3, r3, #8
800a7de: 2b00 cmp r3, #0
800a7e0: d017 beq.n 800a812 <HAL_RCC_ClockConfig+0x17e>
{
assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider));
LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U);
800a7e2: 687b ldr r3, [r7, #4]
800a7e4: 691b ldr r3, [r3, #16]
800a7e6: 00db lsls r3, r3, #3
800a7e8: 4618 mov r0, r3
800a7ea: f7ff facf bl 8009d8c <LL_RCC_SetAPB2Prescaler>
/* APB2 prescaler flag when value applied */
tickstart = HAL_GetTick();
800a7ee: f7fa fdb9 bl 8005364 <HAL_GetTick>
800a7f2: 60f8 str r0, [r7, #12]
while (LL_RCC_IsActiveFlag_PPRE2() == 0U)
800a7f4: e008 b.n 800a808 <HAL_RCC_ClockConfig+0x174>
{
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
800a7f6: f7fa fdb5 bl 8005364 <HAL_GetTick>
800a7fa: 4602 mov r2, r0
800a7fc: 68fb ldr r3, [r7, #12]
800a7fe: 1ad3 subs r3, r2, r3
800a800: 2b02 cmp r3, #2
800a802: d901 bls.n 800a808 <HAL_RCC_ClockConfig+0x174>
{
return HAL_TIMEOUT;
800a804: 2303 movs r3, #3
800a806: e07d b.n 800a904 <HAL_RCC_ClockConfig+0x270>
while (LL_RCC_IsActiveFlag_PPRE2() == 0U)
800a808: f7ff fbbe bl 8009f88 <LL_RCC_IsActiveFlag_PPRE2>
800a80c: 4603 mov r3, r0
800a80e: 2b00 cmp r3, #0
800a810: d0f1 beq.n 800a7f6 <HAL_RCC_ClockConfig+0x162>
}
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800a812: 687b ldr r3, [r7, #4]
800a814: 681b ldr r3, [r3, #0]
800a816: f003 0301 and.w r3, r3, #1
800a81a: 2b00 cmp r3, #0
800a81c: d043 beq.n 800a8a6 <HAL_RCC_ClockConfig+0x212>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800a81e: 687b ldr r3, [r7, #4]
800a820: 685b ldr r3, [r3, #4]
800a822: 2b02 cmp r3, #2
800a824: d106 bne.n 800a834 <HAL_RCC_ClockConfig+0x1a0>
{
/* Check the HSE ready flag */
if (LL_RCC_HSE_IsReady() == 0U)
800a826: f7ff f86f bl 8009908 <LL_RCC_HSE_IsReady>
800a82a: 4603 mov r3, r0
800a82c: 2b00 cmp r3, #0
800a82e: d11e bne.n 800a86e <HAL_RCC_ClockConfig+0x1da>
{
return HAL_ERROR;
800a830: 2301 movs r3, #1
800a832: e067 b.n 800a904 <HAL_RCC_ClockConfig+0x270>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800a834: 687b ldr r3, [r7, #4]
800a836: 685b ldr r3, [r3, #4]
800a838: 2b03 cmp r3, #3
800a83a: d106 bne.n 800a84a <HAL_RCC_ClockConfig+0x1b6>
{
/* Check the PLL ready flag */
if (LL_RCC_PLL_IsReady() == 0U)
800a83c: f7ff fb17 bl 8009e6e <LL_RCC_PLL_IsReady>
800a840: 4603 mov r3, r0
800a842: 2b00 cmp r3, #0
800a844: d113 bne.n 800a86e <HAL_RCC_ClockConfig+0x1da>
{
return HAL_ERROR;
800a846: 2301 movs r3, #1
800a848: e05c b.n 800a904 <HAL_RCC_ClockConfig+0x270>
}
}
/* MSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
800a84a: 687b ldr r3, [r7, #4]
800a84c: 685b ldr r3, [r3, #4]
800a84e: 2b00 cmp r3, #0
800a850: d106 bne.n 800a860 <HAL_RCC_ClockConfig+0x1cc>
{
/* Check the MSI ready flag */
if (LL_RCC_MSI_IsReady() == 0U)
800a852: f7ff f9d7 bl 8009c04 <LL_RCC_MSI_IsReady>
800a856: 4603 mov r3, r0
800a858: 2b00 cmp r3, #0
800a85a: d108 bne.n 800a86e <HAL_RCC_ClockConfig+0x1da>
{
return HAL_ERROR;
800a85c: 2301 movs r3, #1
800a85e: e051 b.n 800a904 <HAL_RCC_ClockConfig+0x270>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (LL_RCC_HSI_IsReady() == 0U)
800a860: f7ff f882 bl 8009968 <LL_RCC_HSI_IsReady>
800a864: 4603 mov r3, r0
800a866: 2b00 cmp r3, #0
800a868: d101 bne.n 800a86e <HAL_RCC_ClockConfig+0x1da>
{
return HAL_ERROR;
800a86a: 2301 movs r3, #1
800a86c: e04a b.n 800a904 <HAL_RCC_ClockConfig+0x270>
}
}
/* apply system clock switch */
LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource);
800a86e: 687b ldr r3, [r7, #4]
800a870: 685b ldr r3, [r3, #4]
800a872: 4618 mov r0, r3
800a874: f7ff fa15 bl 8009ca2 <LL_RCC_SetSysClkSource>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a878: f7fa fd74 bl 8005364 <HAL_GetTick>
800a87c: 60f8 str r0, [r7, #12]
/* check system clock source switch status */
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800a87e: e00a b.n 800a896 <HAL_RCC_ClockConfig+0x202>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800a880: f7fa fd70 bl 8005364 <HAL_GetTick>
800a884: 4602 mov r2, r0
800a886: 68fb ldr r3, [r7, #12]
800a888: 1ad3 subs r3, r2, r3
800a88a: f241 3288 movw r2, #5000 @ 0x1388
800a88e: 4293 cmp r3, r2
800a890: d901 bls.n 800a896 <HAL_RCC_ClockConfig+0x202>
{
return HAL_TIMEOUT;
800a892: 2303 movs r3, #3
800a894: e036 b.n 800a904 <HAL_RCC_ClockConfig+0x270>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800a896: f7ff fa18 bl 8009cca <LL_RCC_GetSysClkSource>
800a89a: 4602 mov r2, r0
800a89c: 687b ldr r3, [r7, #4]
800a89e: 685b ldr r3, [r3, #4]
800a8a0: 009b lsls r3, r3, #2
800a8a2: 429a cmp r2, r3
800a8a4: d1ec bne.n 800a880 <HAL_RCC_ClockConfig+0x1ec>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
800a8a6: 4b19 ldr r3, [pc, #100] @ (800a90c <HAL_RCC_ClockConfig+0x278>)
800a8a8: 681b ldr r3, [r3, #0]
800a8aa: f003 0307 and.w r3, r3, #7
800a8ae: 683a ldr r2, [r7, #0]
800a8b0: 429a cmp r2, r3
800a8b2: d21b bcs.n 800a8ec <HAL_RCC_ClockConfig+0x258>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800a8b4: 4b15 ldr r3, [pc, #84] @ (800a90c <HAL_RCC_ClockConfig+0x278>)
800a8b6: 681b ldr r3, [r3, #0]
800a8b8: f023 0207 bic.w r2, r3, #7
800a8bc: 4913 ldr r1, [pc, #76] @ (800a90c <HAL_RCC_ClockConfig+0x278>)
800a8be: 683b ldr r3, [r7, #0]
800a8c0: 4313 orrs r3, r2
800a8c2: 600b str r3, [r1, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800a8c4: f7fa fd4e bl 8005364 <HAL_GetTick>
800a8c8: 60f8 str r0, [r7, #12]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
while (__HAL_FLASH_GET_LATENCY() != FLatency)
800a8ca: e008 b.n 800a8de <HAL_RCC_ClockConfig+0x24a>
{
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
800a8cc: f7fa fd4a bl 8005364 <HAL_GetTick>
800a8d0: 4602 mov r2, r0
800a8d2: 68fb ldr r3, [r7, #12]
800a8d4: 1ad3 subs r3, r2, r3
800a8d6: 2b02 cmp r3, #2
800a8d8: d901 bls.n 800a8de <HAL_RCC_ClockConfig+0x24a>
{
return HAL_TIMEOUT;
800a8da: 2303 movs r3, #3
800a8dc: e012 b.n 800a904 <HAL_RCC_ClockConfig+0x270>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
800a8de: 4b0b ldr r3, [pc, #44] @ (800a90c <HAL_RCC_ClockConfig+0x278>)
800a8e0: 681b ldr r3, [r3, #0]
800a8e2: f003 0307 and.w r3, r3, #7
800a8e6: 683a ldr r2, [r7, #0]
800a8e8: 429a cmp r2, r3
800a8ea: d1ef bne.n 800a8cc <HAL_RCC_ClockConfig+0x238>
}
/*---------------------------------------------------------------------------*/
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetHCLKFreq();
800a8ec: f000 f87e bl 800a9ec <HAL_RCC_GetHCLKFreq>
800a8f0: 4603 mov r3, r0
800a8f2: 4a07 ldr r2, [pc, #28] @ (800a910 <HAL_RCC_ClockConfig+0x27c>)
800a8f4: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(HAL_GetTickPrio());
800a8f6: f7fa fd41 bl 800537c <HAL_GetTickPrio>
800a8fa: 4603 mov r3, r0
800a8fc: 4618 mov r0, r3
800a8fe: f7fa fad5 bl 8004eac <HAL_InitTick>
800a902: 4603 mov r3, r0
}
800a904: 4618 mov r0, r3
800a906: 3710 adds r7, #16
800a908: 46bd mov sp, r7
800a90a: bd80 pop {r7, pc}
800a90c: 58004000 .word 0x58004000
800a910: 2000000c .word 0x2000000c
0800a914 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800a914: b590 push {r4, r7, lr}
800a916: b085 sub sp, #20
800a918: af00 add r7, sp, #0
uint32_t pllsource;
uint32_t sysclockfreq;
uint32_t pllinputfreq;
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800a91a: f7ff f9d6 bl 8009cca <LL_RCC_GetSysClkSource>
800a91e: 6078 str r0, [r7, #4]
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI)
800a920: 687b ldr r3, [r7, #4]
800a922: 2b00 cmp r3, #0
800a924: d10a bne.n 800a93c <HAL_RCC_GetSysClockFreq+0x28>
{
/* Retrieve MSI frequency range in HZ*/
/* MSI used as system clock source */
sysclockfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
800a926: f7ff f992 bl 8009c4e <LL_RCC_MSI_GetRange>
800a92a: 4603 mov r3, r0
800a92c: 091b lsrs r3, r3, #4
800a92e: f003 030f and.w r3, r3, #15
800a932: 4a2b ldr r2, [pc, #172] @ (800a9e0 <HAL_RCC_GetSysClockFreq+0xcc>)
800a934: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800a938: 60fb str r3, [r7, #12]
800a93a: e04b b.n 800a9d4 <HAL_RCC_GetSysClockFreq+0xc0>
}
else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
800a93c: 687b ldr r3, [r7, #4]
800a93e: 2b04 cmp r3, #4
800a940: d102 bne.n 800a948 <HAL_RCC_GetSysClockFreq+0x34>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
800a942: 4b28 ldr r3, [pc, #160] @ (800a9e4 <HAL_RCC_GetSysClockFreq+0xd0>)
800a944: 60fb str r3, [r7, #12]
800a946: e045 b.n 800a9d4 <HAL_RCC_GetSysClockFreq+0xc0>
}
else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)
800a948: 687b ldr r3, [r7, #4]
800a94a: 2b08 cmp r3, #8
800a94c: d10a bne.n 800a964 <HAL_RCC_GetSysClockFreq+0x50>
{
/* HSE used as system clock source */
if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
800a94e: f7fe ffab bl 80098a8 <LL_RCC_HSE_IsEnabledDiv2>
800a952: 4603 mov r3, r0
800a954: 2b01 cmp r3, #1
800a956: d102 bne.n 800a95e <HAL_RCC_GetSysClockFreq+0x4a>
{
sysclockfreq = HSE_VALUE / 2U;
800a958: 4b22 ldr r3, [pc, #136] @ (800a9e4 <HAL_RCC_GetSysClockFreq+0xd0>)
800a95a: 60fb str r3, [r7, #12]
800a95c: e03a b.n 800a9d4 <HAL_RCC_GetSysClockFreq+0xc0>
}
else
{
sysclockfreq = HSE_VALUE;
800a95e: 4b22 ldr r3, [pc, #136] @ (800a9e8 <HAL_RCC_GetSysClockFreq+0xd4>)
800a960: 60fb str r3, [r7, #12]
800a962: e037 b.n 800a9d4 <HAL_RCC_GetSysClockFreq+0xc0>
}
}
else
{
/* PLL used as system clock source */
pllsource = LL_RCC_PLL_GetMainSource();
800a964: f7ff faba bl 8009edc <LL_RCC_PLL_GetMainSource>
800a968: 6038 str r0, [r7, #0]
switch (pllsource)
800a96a: 683b ldr r3, [r7, #0]
800a96c: 2b02 cmp r3, #2
800a96e: d003 beq.n 800a978 <HAL_RCC_GetSysClockFreq+0x64>
800a970: 683b ldr r3, [r7, #0]
800a972: 2b03 cmp r3, #3
800a974: d003 beq.n 800a97e <HAL_RCC_GetSysClockFreq+0x6a>
800a976: e00d b.n 800a994 <HAL_RCC_GetSysClockFreq+0x80>
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE;
800a978: 4b1a ldr r3, [pc, #104] @ (800a9e4 <HAL_RCC_GetSysClockFreq+0xd0>)
800a97a: 60bb str r3, [r7, #8]
break;
800a97c: e015 b.n 800a9aa <HAL_RCC_GetSysClockFreq+0x96>
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
800a97e: f7fe ff93 bl 80098a8 <LL_RCC_HSE_IsEnabledDiv2>
800a982: 4603 mov r3, r0
800a984: 2b01 cmp r3, #1
800a986: d102 bne.n 800a98e <HAL_RCC_GetSysClockFreq+0x7a>
{
pllinputfreq = HSE_VALUE / 2U;
800a988: 4b16 ldr r3, [pc, #88] @ (800a9e4 <HAL_RCC_GetSysClockFreq+0xd0>)
800a98a: 60bb str r3, [r7, #8]
}
else
{
pllinputfreq = HSE_VALUE;
}
break;
800a98c: e00d b.n 800a9aa <HAL_RCC_GetSysClockFreq+0x96>
pllinputfreq = HSE_VALUE;
800a98e: 4b16 ldr r3, [pc, #88] @ (800a9e8 <HAL_RCC_GetSysClockFreq+0xd4>)
800a990: 60bb str r3, [r7, #8]
break;
800a992: e00a b.n 800a9aa <HAL_RCC_GetSysClockFreq+0x96>
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default:
pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
800a994: f7ff f95b bl 8009c4e <LL_RCC_MSI_GetRange>
800a998: 4603 mov r3, r0
800a99a: 091b lsrs r3, r3, #4
800a99c: f003 030f and.w r3, r3, #15
800a9a0: 4a0f ldr r2, [pc, #60] @ (800a9e0 <HAL_RCC_GetSysClockFreq+0xcc>)
800a9a2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800a9a6: 60bb str r3, [r7, #8]
break;
800a9a8: bf00 nop
}
sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(),
800a9aa: f7ff fa72 bl 8009e92 <LL_RCC_PLL_GetN>
800a9ae: 4602 mov r2, r0
800a9b0: 68bb ldr r3, [r7, #8]
800a9b2: fb03 f402 mul.w r4, r3, r2
800a9b6: f7ff fa85 bl 8009ec4 <LL_RCC_PLL_GetDivider>
800a9ba: 4603 mov r3, r0
800a9bc: 091b lsrs r3, r3, #4
800a9be: 3301 adds r3, #1
800a9c0: fbb4 f4f3 udiv r4, r4, r3
800a9c4: f7ff fa72 bl 8009eac <LL_RCC_PLL_GetR>
800a9c8: 4603 mov r3, r0
800a9ca: 0f5b lsrs r3, r3, #29
800a9cc: 3301 adds r3, #1
800a9ce: fbb4 f3f3 udiv r3, r4, r3
800a9d2: 60fb str r3, [r7, #12]
LL_RCC_PLL_GetR());
}
return sysclockfreq;
800a9d4: 68fb ldr r3, [r7, #12]
}
800a9d6: 4618 mov r0, r3
800a9d8: 3714 adds r7, #20
800a9da: 46bd mov sp, r7
800a9dc: bd90 pop {r4, r7, pc}
800a9de: bf00 nop
800a9e0: 0801c778 .word 0x0801c778
800a9e4: 00f42400 .word 0x00f42400
800a9e8: 01e84800 .word 0x01e84800
0800a9ec <HAL_RCC_GetHCLKFreq>:
/**
* @brief Return the HCLK frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
800a9ec: b598 push {r3, r4, r7, lr}
800a9ee: af00 add r7, sp, #0
/* Get SysClock and Compute HCLK1 frequency ---------------------------*/
return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler())));
800a9f0: f7ff ff90 bl 800a914 <HAL_RCC_GetSysClockFreq>
800a9f4: 4604 mov r4, r0
800a9f6: f7ff f9dd bl 8009db4 <LL_RCC_GetAHBPrescaler>
800a9fa: 4603 mov r3, r0
800a9fc: 091b lsrs r3, r3, #4
800a9fe: f003 030f and.w r3, r3, #15
800aa02: 4a03 ldr r2, [pc, #12] @ (800aa10 <HAL_RCC_GetHCLKFreq+0x24>)
800aa04: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800aa08: fbb4 f3f3 udiv r3, r4, r3
}
800aa0c: 4618 mov r0, r3
800aa0e: bd98 pop {r3, r4, r7, pc}
800aa10: 0801c718 .word 0x0801c718
0800aa14 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
800aa14: b598 push {r3, r4, r7, lr}
800aa16: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler())));
800aa18: f7ff ffe8 bl 800a9ec <HAL_RCC_GetHCLKFreq>
800aa1c: 4604 mov r4, r0
800aa1e: f7ff f9fc bl 8009e1a <LL_RCC_GetAPB2Prescaler>
800aa22: 4603 mov r3, r0
800aa24: 0adb lsrs r3, r3, #11
800aa26: f003 0307 and.w r3, r3, #7
800aa2a: 4a04 ldr r2, [pc, #16] @ (800aa3c <HAL_RCC_GetPCLK2Freq+0x28>)
800aa2c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800aa30: f003 031f and.w r3, r3, #31
800aa34: fa24 f303 lsr.w r3, r4, r3
}
800aa38: 4618 mov r0, r3
800aa3a: bd98 pop {r3, r4, r7, pc}
800aa3c: 0801c758 .word 0x0801c758
0800aa40 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
800aa40: b580 push {r7, lr}
800aa42: b082 sub sp, #8
800aa44: af00 add r7, sp, #0
800aa46: 6078 str r0, [r7, #4]
800aa48: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(RCC_ClkInitStruct != (void *)NULL);
assert_param(pFLatency != (void *)NULL);
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 |
800aa4a: 687b ldr r3, [r7, #4]
800aa4c: 226f movs r2, #111 @ 0x6f
800aa4e: 601a str r2, [r3, #0]
RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4);
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = LL_RCC_GetSysClkSource();
800aa50: f7ff f93b bl 8009cca <LL_RCC_GetSysClkSource>
800aa54: 4602 mov r2, r0
800aa56: 687b ldr r3, [r7, #4]
800aa58: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = LL_RCC_GetAHBPrescaler();
800aa5a: f7ff f9ab bl 8009db4 <LL_RCC_GetAHBPrescaler>
800aa5e: 4602 mov r2, r0
800aa60: 687b ldr r3, [r7, #4]
800aa62: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = LL_RCC_GetAPB1Prescaler();
800aa64: f7ff f9cd bl 8009e02 <LL_RCC_GetAPB1Prescaler>
800aa68: 4602 mov r2, r0
800aa6a: 687b ldr r3, [r7, #4]
800aa6c: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = LL_RCC_GetAPB2Prescaler();
800aa6e: f7ff f9d4 bl 8009e1a <LL_RCC_GetAPB2Prescaler>
800aa72: 4602 mov r2, r0
800aa74: 687b ldr r3, [r7, #4]
800aa76: 611a str r2, [r3, #16]
/* Get the AHBCLK2Divider configuration ------------------------------------*/
RCC_ClkInitStruct->AHBCLK2Divider = LL_C2_RCC_GetAHBPrescaler();
800aa78: f7ff f9a8 bl 8009dcc <LL_C2_RCC_GetAHBPrescaler>
800aa7c: 4602 mov r2, r0
800aa7e: 687b ldr r3, [r7, #4]
800aa80: 615a str r2, [r3, #20]
/* Get the AHBCLK4Divider configuration ------------------------------------*/
RCC_ClkInitStruct->AHBCLK4Divider = LL_RCC_GetAHB4Prescaler();
800aa82: f7ff f9b0 bl 8009de6 <LL_RCC_GetAHB4Prescaler>
800aa86: 4602 mov r2, r0
800aa88: 687b ldr r3, [r7, #4]
800aa8a: 619a str r2, [r3, #24]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = __HAL_FLASH_GET_LATENCY();
800aa8c: 4b04 ldr r3, [pc, #16] @ (800aaa0 <HAL_RCC_GetClockConfig+0x60>)
800aa8e: 681b ldr r3, [r3, #0]
800aa90: f003 0207 and.w r2, r3, #7
800aa94: 683b ldr r3, [r7, #0]
800aa96: 601a str r2, [r3, #0]
}
800aa98: bf00 nop
800aa9a: 3708 adds r7, #8
800aa9c: 46bd mov sp, r7
800aa9e: bd80 pop {r7, pc}
800aaa0: 58004000 .word 0x58004000
0800aaa4 <RCC_SetFlashLatencyFromMSIRange>:
voltage range.
* @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range)
{
800aaa4: b590 push {r4, r7, lr}
800aaa6: b085 sub sp, #20
800aaa8: af00 add r7, sp, #0
800aaaa: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range));
/* MSI frequency range in Hz */
if (MSI_Range > RCC_MSIRANGE_11)
800aaac: 687b ldr r3, [r7, #4]
800aaae: 2bb0 cmp r3, #176 @ 0xb0
800aab0: d903 bls.n 800aaba <RCC_SetFlashLatencyFromMSIRange+0x16>
{
msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11);
800aab2: 4b15 ldr r3, [pc, #84] @ (800ab08 <RCC_SetFlashLatencyFromMSIRange+0x64>)
800aab4: 6adb ldr r3, [r3, #44] @ 0x2c
800aab6: 60fb str r3, [r7, #12]
800aab8: e007 b.n 800aaca <RCC_SetFlashLatencyFromMSIRange+0x26>
}
else
{
msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range);
800aaba: 687b ldr r3, [r7, #4]
800aabc: 091b lsrs r3, r3, #4
800aabe: f003 030f and.w r3, r3, #15
800aac2: 4a11 ldr r2, [pc, #68] @ (800ab08 <RCC_SetFlashLatencyFromMSIRange+0x64>)
800aac4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800aac8: 60fb str r3, [r7, #12]
}
flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler());
800aaca: f7ff f98c bl 8009de6 <LL_RCC_GetAHB4Prescaler>
800aace: 4603 mov r3, r0
800aad0: 091b lsrs r3, r3, #4
800aad2: f003 030f and.w r3, r3, #15
800aad6: 4a0d ldr r2, [pc, #52] @ (800ab0c <RCC_SetFlashLatencyFromMSIRange+0x68>)
800aad8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800aadc: 68fa ldr r2, [r7, #12]
800aade: fbb2 f3f3 udiv r3, r2, r3
800aae2: 60bb str r3, [r7, #8]
#if defined(PWR_CR1_VOS)
return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange());
800aae4: 68bb ldr r3, [r7, #8]
800aae6: 4a0a ldr r2, [pc, #40] @ (800ab10 <RCC_SetFlashLatencyFromMSIRange+0x6c>)
800aae8: fba2 2303 umull r2, r3, r2, r3
800aaec: 0c9c lsrs r4, r3, #18
800aaee: f7fe febd bl 800986c <HAL_PWREx_GetVoltageRange>
800aaf2: 4603 mov r3, r0
800aaf4: 4619 mov r1, r3
800aaf6: 4620 mov r0, r4
800aaf8: f000 f80c bl 800ab14 <RCC_SetFlashLatency>
800aafc: 4603 mov r3, r0
#else
return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1);
#endif /* PWR_CR1_VOS */
}
800aafe: 4618 mov r0, r3
800ab00: 3714 adds r7, #20
800ab02: 46bd mov sp, r7
800ab04: bd90 pop {r4, r7, pc}
800ab06: bf00 nop
800ab08: 0801c778 .word 0x0801c778
800ab0c: 0801c718 .word 0x0801c718
800ab10: 431bde83 .word 0x431bde83
0800ab14 <RCC_SetFlashLatency>:
* @param Flash_ClkSrcFreq Flash Clock Source (in MHz)
* @param VCORE_Voltage Current Vcore voltage (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2)
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage)
{
800ab14: b590 push {r4, r7, lr}
800ab16: b093 sub sp, #76 @ 0x4c
800ab18: af00 add r7, sp, #0
800ab1a: 6078 str r0, [r7, #4]
800ab1c: 6039 str r1, [r7, #0]
/* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */
const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL};
800ab1e: 4b37 ldr r3, [pc, #220] @ (800abfc <RCC_SetFlashLatency+0xe8>)
800ab20: f107 0428 add.w r4, r7, #40 @ 0x28
800ab24: cb0f ldmia r3, {r0, r1, r2, r3}
800ab26: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(PWR_CR1_VOS)
/* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */
const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL};
800ab2a: 4a35 ldr r2, [pc, #212] @ (800ac00 <RCC_SetFlashLatency+0xec>)
800ab2c: f107 031c add.w r3, r7, #28
800ab30: ca07 ldmia r2, {r0, r1, r2}
800ab32: e883 0007 stmia.w r3, {r0, r1, r2}
#endif /* PWR_CR1_VOS */
/* Flash Latency range */
const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3};
800ab36: 4b33 ldr r3, [pc, #204] @ (800ac04 <RCC_SetFlashLatency+0xf0>)
800ab38: f107 040c add.w r4, r7, #12
800ab3c: cb0f ldmia r3, {r0, r1, r2, r3}
800ab3e: e884 000f stmia.w r4, {r0, r1, r2, r3}
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
800ab42: 2300 movs r3, #0
800ab44: 647b str r3, [r7, #68] @ 0x44
uint32_t tickstart;
#if defined(PWR_CR1_VOS)
if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1)
800ab46: 683b ldr r3, [r7, #0]
800ab48: f5b3 7f00 cmp.w r3, #512 @ 0x200
800ab4c: d11a bne.n 800ab84 <RCC_SetFlashLatency+0x70>
{
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
800ab4e: 2300 movs r3, #0
800ab50: 643b str r3, [r7, #64] @ 0x40
800ab52: e013 b.n 800ab7c <RCC_SetFlashLatency+0x68>
{
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index])
800ab54: 6c3b ldr r3, [r7, #64] @ 0x40
800ab56: 009b lsls r3, r3, #2
800ab58: 3348 adds r3, #72 @ 0x48
800ab5a: 443b add r3, r7
800ab5c: f853 3c20 ldr.w r3, [r3, #-32]
800ab60: 687a ldr r2, [r7, #4]
800ab62: 429a cmp r2, r3
800ab64: d807 bhi.n 800ab76 <RCC_SetFlashLatency+0x62>
{
latency = FLASH_LATENCY_RANGE[index];
800ab66: 6c3b ldr r3, [r7, #64] @ 0x40
800ab68: 009b lsls r3, r3, #2
800ab6a: 3348 adds r3, #72 @ 0x48
800ab6c: 443b add r3, r7
800ab6e: f853 3c3c ldr.w r3, [r3, #-60]
800ab72: 647b str r3, [r7, #68] @ 0x44
break;
800ab74: e020 b.n 800abb8 <RCC_SetFlashLatency+0xa4>
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
800ab76: 6c3b ldr r3, [r7, #64] @ 0x40
800ab78: 3301 adds r3, #1
800ab7a: 643b str r3, [r7, #64] @ 0x40
800ab7c: 6c3b ldr r3, [r7, #64] @ 0x40
800ab7e: 2b03 cmp r3, #3
800ab80: d9e8 bls.n 800ab54 <RCC_SetFlashLatency+0x40>
800ab82: e019 b.n 800abb8 <RCC_SetFlashLatency+0xa4>
}
}
}
else /* PWR_REGULATOR_VOLTAGE_SCALE2 */
{
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++)
800ab84: 2300 movs r3, #0
800ab86: 63fb str r3, [r7, #60] @ 0x3c
800ab88: e013 b.n 800abb2 <RCC_SetFlashLatency+0x9e>
{
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index])
800ab8a: 6bfb ldr r3, [r7, #60] @ 0x3c
800ab8c: 009b lsls r3, r3, #2
800ab8e: 3348 adds r3, #72 @ 0x48
800ab90: 443b add r3, r7
800ab92: f853 3c2c ldr.w r3, [r3, #-44]
800ab96: 687a ldr r2, [r7, #4]
800ab98: 429a cmp r2, r3
800ab9a: d807 bhi.n 800abac <RCC_SetFlashLatency+0x98>
{
latency = FLASH_LATENCY_RANGE[index];
800ab9c: 6bfb ldr r3, [r7, #60] @ 0x3c
800ab9e: 009b lsls r3, r3, #2
800aba0: 3348 adds r3, #72 @ 0x48
800aba2: 443b add r3, r7
800aba4: f853 3c3c ldr.w r3, [r3, #-60]
800aba8: 647b str r3, [r7, #68] @ 0x44
break;
800abaa: e005 b.n 800abb8 <RCC_SetFlashLatency+0xa4>
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++)
800abac: 6bfb ldr r3, [r7, #60] @ 0x3c
800abae: 3301 adds r3, #1
800abb0: 63fb str r3, [r7, #60] @ 0x3c
800abb2: 6bfb ldr r3, [r7, #60] @ 0x3c
800abb4: 2b02 cmp r3, #2
800abb6: d9e8 bls.n 800ab8a <RCC_SetFlashLatency+0x76>
break;
}
}
#endif /* PWR_CR1_VOS */
__HAL_FLASH_SET_LATENCY(latency);
800abb8: 4b13 ldr r3, [pc, #76] @ (800ac08 <RCC_SetFlashLatency+0xf4>)
800abba: 681b ldr r3, [r3, #0]
800abbc: f023 0207 bic.w r2, r3, #7
800abc0: 4911 ldr r1, [pc, #68] @ (800ac08 <RCC_SetFlashLatency+0xf4>)
800abc2: 6c7b ldr r3, [r7, #68] @ 0x44
800abc4: 4313 orrs r3, r2
800abc6: 600b str r3, [r1, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800abc8: f7fa fbcc bl 8005364 <HAL_GetTick>
800abcc: 63b8 str r0, [r7, #56] @ 0x38
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
while (__HAL_FLASH_GET_LATENCY() != latency)
800abce: e008 b.n 800abe2 <RCC_SetFlashLatency+0xce>
{
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
800abd0: f7fa fbc8 bl 8005364 <HAL_GetTick>
800abd4: 4602 mov r2, r0
800abd6: 6bbb ldr r3, [r7, #56] @ 0x38
800abd8: 1ad3 subs r3, r2, r3
800abda: 2b02 cmp r3, #2
800abdc: d901 bls.n 800abe2 <RCC_SetFlashLatency+0xce>
{
return HAL_TIMEOUT;
800abde: 2303 movs r3, #3
800abe0: e007 b.n 800abf2 <RCC_SetFlashLatency+0xde>
while (__HAL_FLASH_GET_LATENCY() != latency)
800abe2: 4b09 ldr r3, [pc, #36] @ (800ac08 <RCC_SetFlashLatency+0xf4>)
800abe4: 681b ldr r3, [r3, #0]
800abe6: f003 0307 and.w r3, r3, #7
800abea: 6c7a ldr r2, [r7, #68] @ 0x44
800abec: 429a cmp r2, r3
800abee: d1ef bne.n 800abd0 <RCC_SetFlashLatency+0xbc>
}
}
return HAL_OK;
800abf0: 2300 movs r3, #0
}
800abf2: 4618 mov r0, r3
800abf4: 374c adds r7, #76 @ 0x4c
800abf6: 46bd mov sp, r7
800abf8: bd90 pop {r4, r7, pc}
800abfa: bf00 nop
800abfc: 0801c49c .word 0x0801c49c
800ac00: 0801c4ac .word 0x0801c4ac
800ac04: 0801c4b8 .word 0x0801c4b8
800ac08: 58004000 .word 0x58004000
0800ac0c <LL_RCC_LSE_IsEnabled>:
{
800ac0c: b480 push {r7}
800ac0e: af00 add r7, sp, #0
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL);
800ac10: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ac14: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800ac18: f003 0301 and.w r3, r3, #1
800ac1c: 2b01 cmp r3, #1
800ac1e: d101 bne.n 800ac24 <LL_RCC_LSE_IsEnabled+0x18>
800ac20: 2301 movs r3, #1
800ac22: e000 b.n 800ac26 <LL_RCC_LSE_IsEnabled+0x1a>
800ac24: 2300 movs r3, #0
}
800ac26: 4618 mov r0, r3
800ac28: 46bd mov sp, r7
800ac2a: f85d 7b04 ldr.w r7, [sp], #4
800ac2e: 4770 bx lr
0800ac30 <LL_RCC_LSE_IsReady>:
{
800ac30: b480 push {r7}
800ac32: af00 add r7, sp, #0
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
800ac34: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ac38: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800ac3c: f003 0302 and.w r3, r3, #2
800ac40: 2b02 cmp r3, #2
800ac42: d101 bne.n 800ac48 <LL_RCC_LSE_IsReady+0x18>
800ac44: 2301 movs r3, #1
800ac46: e000 b.n 800ac4a <LL_RCC_LSE_IsReady+0x1a>
800ac48: 2300 movs r3, #0
}
800ac4a: 4618 mov r0, r3
800ac4c: 46bd mov sp, r7
800ac4e: f85d 7b04 ldr.w r7, [sp], #4
800ac52: 4770 bx lr
0800ac54 <LL_RCC_MSI_EnablePLLMode>:
{
800ac54: b480 push {r7}
800ac56: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
800ac58: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ac5c: 681b ldr r3, [r3, #0]
800ac5e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800ac62: f043 0304 orr.w r3, r3, #4
800ac66: 6013 str r3, [r2, #0]
}
800ac68: bf00 nop
800ac6a: 46bd mov sp, r7
800ac6c: f85d 7b04 ldr.w r7, [sp], #4
800ac70: 4770 bx lr
0800ac72 <LL_RCC_SetRFWKPClockSource>:
{
800ac72: b480 push {r7}
800ac74: b083 sub sp, #12
800ac76: af00 add r7, sp, #0
800ac78: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source);
800ac7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ac7e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800ac82: f423 4240 bic.w r2, r3, #49152 @ 0xc000
800ac86: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800ac8a: 687b ldr r3, [r7, #4]
800ac8c: 4313 orrs r3, r2
800ac8e: f8c1 3094 str.w r3, [r1, #148] @ 0x94
}
800ac92: bf00 nop
800ac94: 370c adds r7, #12
800ac96: 46bd mov sp, r7
800ac98: f85d 7b04 ldr.w r7, [sp], #4
800ac9c: 4770 bx lr
0800ac9e <LL_RCC_SetSMPSClockSource>:
{
800ac9e: b480 push {r7}
800aca0: b083 sub sp, #12
800aca2: af00 add r7, sp, #0
800aca4: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource);
800aca6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800acaa: 6a5b ldr r3, [r3, #36] @ 0x24
800acac: f023 0203 bic.w r2, r3, #3
800acb0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800acb4: 687b ldr r3, [r7, #4]
800acb6: 4313 orrs r3, r2
800acb8: 624b str r3, [r1, #36] @ 0x24
}
800acba: bf00 nop
800acbc: 370c adds r7, #12
800acbe: 46bd mov sp, r7
800acc0: f85d 7b04 ldr.w r7, [sp], #4
800acc4: 4770 bx lr
0800acc6 <LL_RCC_SetSMPSPrescaler>:
{
800acc6: b480 push {r7}
800acc8: b083 sub sp, #12
800acca: af00 add r7, sp, #0
800accc: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler);
800acce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800acd2: 6a5b ldr r3, [r3, #36] @ 0x24
800acd4: f023 0230 bic.w r2, r3, #48 @ 0x30
800acd8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800acdc: 687b ldr r3, [r7, #4]
800acde: 4313 orrs r3, r2
800ace0: 624b str r3, [r1, #36] @ 0x24
}
800ace2: bf00 nop
800ace4: 370c adds r7, #12
800ace6: 46bd mov sp, r7
800ace8: f85d 7b04 ldr.w r7, [sp], #4
800acec: 4770 bx lr
0800acee <LL_RCC_SetUSARTClockSource>:
{
800acee: b480 push {r7}
800acf0: b083 sub sp, #12
800acf2: af00 add r7, sp, #0
800acf4: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource);
800acf6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800acfa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800acfe: f023 0203 bic.w r2, r3, #3
800ad02: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800ad06: 687b ldr r3, [r7, #4]
800ad08: 4313 orrs r3, r2
800ad0a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
800ad0e: bf00 nop
800ad10: 370c adds r7, #12
800ad12: 46bd mov sp, r7
800ad14: f85d 7b04 ldr.w r7, [sp], #4
800ad18: 4770 bx lr
0800ad1a <LL_RCC_SetLPUARTClockSource>:
{
800ad1a: b480 push {r7}
800ad1c: b083 sub sp, #12
800ad1e: af00 add r7, sp, #0
800ad20: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
800ad22: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ad26: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800ad2a: f423 6240 bic.w r2, r3, #3072 @ 0xc00
800ad2e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800ad32: 687b ldr r3, [r7, #4]
800ad34: 4313 orrs r3, r2
800ad36: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
800ad3a: bf00 nop
800ad3c: 370c adds r7, #12
800ad3e: 46bd mov sp, r7
800ad40: f85d 7b04 ldr.w r7, [sp], #4
800ad44: 4770 bx lr
0800ad46 <LL_RCC_SetI2CClockSource>:
{
800ad46: b480 push {r7}
800ad48: b083 sub sp, #12
800ad4a: af00 add r7, sp, #0
800ad4c: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U));
800ad4e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ad52: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
800ad56: 687b ldr r3, [r7, #4]
800ad58: 091b lsrs r3, r3, #4
800ad5a: f403 237f and.w r3, r3, #1044480 @ 0xff000
800ad5e: 43db mvns r3, r3
800ad60: 401a ands r2, r3
800ad62: 687b ldr r3, [r7, #4]
800ad64: 011b lsls r3, r3, #4
800ad66: f403 237f and.w r3, r3, #1044480 @ 0xff000
800ad6a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800ad6e: 4313 orrs r3, r2
800ad70: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
800ad74: bf00 nop
800ad76: 370c adds r7, #12
800ad78: 46bd mov sp, r7
800ad7a: f85d 7b04 ldr.w r7, [sp], #4
800ad7e: 4770 bx lr
0800ad80 <LL_RCC_SetLPTIMClockSource>:
{
800ad80: b480 push {r7}
800ad82: b083 sub sp, #12
800ad84: af00 add r7, sp, #0
800ad86: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
800ad88: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ad8c: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
800ad90: 687b ldr r3, [r7, #4]
800ad92: 0c1b lsrs r3, r3, #16
800ad94: 041b lsls r3, r3, #16
800ad96: 43db mvns r3, r3
800ad98: 401a ands r2, r3
800ad9a: 687b ldr r3, [r7, #4]
800ad9c: 041b lsls r3, r3, #16
800ad9e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800ada2: 4313 orrs r3, r2
800ada4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
800ada8: bf00 nop
800adaa: 370c adds r7, #12
800adac: 46bd mov sp, r7
800adae: f85d 7b04 ldr.w r7, [sp], #4
800adb2: 4770 bx lr
0800adb4 <LL_RCC_SetSAIClockSource>:
{
800adb4: b480 push {r7}
800adb6: b083 sub sp, #12
800adb8: af00 add r7, sp, #0
800adba: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
800adbc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800adc0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800adc4: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
800adc8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800adcc: 687b ldr r3, [r7, #4]
800adce: 4313 orrs r3, r2
800add0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
800add4: bf00 nop
800add6: 370c adds r7, #12
800add8: 46bd mov sp, r7
800adda: f85d 7b04 ldr.w r7, [sp], #4
800adde: 4770 bx lr
0800ade0 <LL_RCC_SetRNGClockSource>:
{
800ade0: b480 push {r7}
800ade2: b083 sub sp, #12
800ade4: af00 add r7, sp, #0
800ade6: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
800ade8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800adec: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800adf0: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000
800adf4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800adf8: 687b ldr r3, [r7, #4]
800adfa: 4313 orrs r3, r2
800adfc: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
800ae00: bf00 nop
800ae02: 370c adds r7, #12
800ae04: 46bd mov sp, r7
800ae06: f85d 7b04 ldr.w r7, [sp], #4
800ae0a: 4770 bx lr
0800ae0c <LL_RCC_SetCLK48ClockSource>:
{
800ae0c: b480 push {r7}
800ae0e: b083 sub sp, #12
800ae10: af00 add r7, sp, #0
800ae12: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource);
800ae14: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ae18: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800ae1c: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
800ae20: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800ae24: 687b ldr r3, [r7, #4]
800ae26: 4313 orrs r3, r2
800ae28: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
800ae2c: bf00 nop
800ae2e: 370c adds r7, #12
800ae30: 46bd mov sp, r7
800ae32: f85d 7b04 ldr.w r7, [sp], #4
800ae36: 4770 bx lr
0800ae38 <LL_RCC_SetUSBClockSource>:
{
800ae38: b580 push {r7, lr}
800ae3a: b082 sub sp, #8
800ae3c: af00 add r7, sp, #0
800ae3e: 6078 str r0, [r7, #4]
LL_RCC_SetCLK48ClockSource(USBxSource);
800ae40: 6878 ldr r0, [r7, #4]
800ae42: f7ff ffe3 bl 800ae0c <LL_RCC_SetCLK48ClockSource>
}
800ae46: bf00 nop
800ae48: 3708 adds r7, #8
800ae4a: 46bd mov sp, r7
800ae4c: bd80 pop {r7, pc}
0800ae4e <LL_RCC_SetADCClockSource>:
{
800ae4e: b480 push {r7}
800ae50: b083 sub sp, #12
800ae52: af00 add r7, sp, #0
800ae54: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
800ae56: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ae5a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800ae5e: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
800ae62: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800ae66: 687b ldr r3, [r7, #4]
800ae68: 4313 orrs r3, r2
800ae6a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
800ae6e: bf00 nop
800ae70: 370c adds r7, #12
800ae72: 46bd mov sp, r7
800ae74: f85d 7b04 ldr.w r7, [sp], #4
800ae78: 4770 bx lr
0800ae7a <LL_RCC_SetRTCClockSource>:
{
800ae7a: b480 push {r7}
800ae7c: b083 sub sp, #12
800ae7e: af00 add r7, sp, #0
800ae80: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
800ae82: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800ae86: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800ae8a: f423 7240 bic.w r2, r3, #768 @ 0x300
800ae8e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800ae92: 687b ldr r3, [r7, #4]
800ae94: 4313 orrs r3, r2
800ae96: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
800ae9a: bf00 nop
800ae9c: 370c adds r7, #12
800ae9e: 46bd mov sp, r7
800aea0: f85d 7b04 ldr.w r7, [sp], #4
800aea4: 4770 bx lr
0800aea6 <LL_RCC_GetRTCClockSource>:
{
800aea6: b480 push {r7}
800aea8: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
800aeaa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800aeae: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800aeb2: f403 7340 and.w r3, r3, #768 @ 0x300
}
800aeb6: 4618 mov r0, r3
800aeb8: 46bd mov sp, r7
800aeba: f85d 7b04 ldr.w r7, [sp], #4
800aebe: 4770 bx lr
0800aec0 <LL_RCC_ForceBackupDomainReset>:
{
800aec0: b480 push {r7}
800aec2: af00 add r7, sp, #0
SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
800aec4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800aec8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800aecc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800aed0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800aed4: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
800aed8: bf00 nop
800aeda: 46bd mov sp, r7
800aedc: f85d 7b04 ldr.w r7, [sp], #4
800aee0: 4770 bx lr
0800aee2 <LL_RCC_ReleaseBackupDomainReset>:
{
800aee2: b480 push {r7}
800aee4: af00 add r7, sp, #0
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
800aee6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800aeea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800aeee: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800aef2: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800aef6: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
800aefa: bf00 nop
800aefc: 46bd mov sp, r7
800aefe: f85d 7b04 ldr.w r7, [sp], #4
800af02: 4770 bx lr
0800af04 <LL_RCC_PLLSAI1_Enable>:
{
800af04: b480 push {r7}
800af06: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
800af08: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800af0c: 681b ldr r3, [r3, #0]
800af0e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800af12: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
800af16: 6013 str r3, [r2, #0]
}
800af18: bf00 nop
800af1a: 46bd mov sp, r7
800af1c: f85d 7b04 ldr.w r7, [sp], #4
800af20: 4770 bx lr
0800af22 <LL_RCC_PLLSAI1_Disable>:
{
800af22: b480 push {r7}
800af24: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
800af26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800af2a: 681b ldr r3, [r3, #0]
800af2c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800af30: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
800af34: 6013 str r3, [r2, #0]
}
800af36: bf00 nop
800af38: 46bd mov sp, r7
800af3a: f85d 7b04 ldr.w r7, [sp], #4
800af3e: 4770 bx lr
0800af40 <LL_RCC_PLLSAI1_IsReady>:
{
800af40: b480 push {r7}
800af42: af00 add r7, sp, #0
return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL);
800af44: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800af48: 681b ldr r3, [r3, #0]
800af4a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
800af4e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
800af52: d101 bne.n 800af58 <LL_RCC_PLLSAI1_IsReady+0x18>
800af54: 2301 movs r3, #1
800af56: e000 b.n 800af5a <LL_RCC_PLLSAI1_IsReady+0x1a>
800af58: 2300 movs r3, #0
}
800af5a: 4618 mov r0, r3
800af5c: 46bd mov sp, r7
800af5e: f85d 7b04 ldr.w r7, [sp], #4
800af62: 4770 bx lr
0800af64 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
800af64: b580 push {r7, lr}
800af66: b088 sub sp, #32
800af68: af00 add r7, sp, #0
800af6a: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
800af6c: 2300 movs r3, #0
800af6e: 77fb strb r3, [r7, #31]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
800af70: 2300 movs r3, #0
800af72: 77bb strb r3, [r7, #30]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
800af74: 687b ldr r3, [r7, #4]
800af76: 681b ldr r3, [r3, #0]
800af78: f003 0340 and.w r3, r3, #64 @ 0x40
800af7c: 2b00 cmp r3, #0
800af7e: d034 beq.n 800afea <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
switch (PeriphClkInit->Sai1ClockSelection)
800af80: 687b ldr r3, [r7, #4]
800af82: 6b1b ldr r3, [r3, #48] @ 0x30
800af84: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
800af88: d021 beq.n 800afce <HAL_RCCEx_PeriphCLKConfig+0x6a>
800af8a: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
800af8e: d81b bhi.n 800afc8 <HAL_RCCEx_PeriphCLKConfig+0x64>
800af90: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
800af94: d01d beq.n 800afd2 <HAL_RCCEx_PeriphCLKConfig+0x6e>
800af96: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
800af9a: d815 bhi.n 800afc8 <HAL_RCCEx_PeriphCLKConfig+0x64>
800af9c: 2b00 cmp r3, #0
800af9e: d00b beq.n 800afb8 <HAL_RCCEx_PeriphCLKConfig+0x54>
800afa0: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
800afa4: d110 bne.n 800afc8 <HAL_RCCEx_PeriphCLKConfig+0x64>
{
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1 */
/* Enable SAI1 Clock output generated form System PLL . */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI1CLK);
800afa6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800afaa: 68db ldr r3, [r3, #12]
800afac: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800afb0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800afb4: 60d3 str r3, [r2, #12]
/* SAI1 clock source config set later after clock selection check */
break;
800afb6: e00d b.n 800afd4 <HAL_RCCEx_PeriphCLKConfig+0x70>
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */
/* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1));
800afb8: 687b ldr r3, [r7, #4]
800afba: 3304 adds r3, #4
800afbc: 4618 mov r0, r3
800afbe: f000 f94d bl 800b25c <RCCEx_PLLSAI1_ConfigNP>
800afc2: 4603 mov r3, r0
800afc4: 77fb strb r3, [r7, #31]
/* SAI1 clock source config set later after clock selection check */
break;
800afc6: e005 b.n 800afd4 <HAL_RCCEx_PeriphCLKConfig+0x70>
case RCC_SAI1CLKSOURCE_HSI:
break;
default:
ret = HAL_ERROR;
800afc8: 2301 movs r3, #1
800afca: 77fb strb r3, [r7, #31]
break;
800afcc: e002 b.n 800afd4 <HAL_RCCEx_PeriphCLKConfig+0x70>
break;
800afce: bf00 nop
800afd0: e000 b.n 800afd4 <HAL_RCCEx_PeriphCLKConfig+0x70>
break;
800afd2: bf00 nop
}
if (ret == HAL_OK)
800afd4: 7ffb ldrb r3, [r7, #31]
800afd6: 2b00 cmp r3, #0
800afd8: d105 bne.n 800afe6 <HAL_RCCEx_PeriphCLKConfig+0x82>
{
/* Set the source of SAI1 clock*/
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
800afda: 687b ldr r3, [r7, #4]
800afdc: 6b1b ldr r3, [r3, #48] @ 0x30
800afde: 4618 mov r0, r3
800afe0: f7ff fee8 bl 800adb4 <LL_RCC_SetSAIClockSource>
800afe4: e001 b.n 800afea <HAL_RCCEx_PeriphCLKConfig+0x86>
}
else
{
/* set overall return value */
status = ret;
800afe6: 7ffb ldrb r3, [r7, #31]
800afe8: 77bb strb r3, [r7, #30]
}
}
#endif /* SAI1 */
/*-------------------------- RTC clock source configuration ----------------------*/
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
800afea: 687b ldr r3, [r7, #4]
800afec: 681b ldr r3, [r3, #0]
800afee: f403 6300 and.w r3, r3, #2048 @ 0x800
800aff2: 2b00 cmp r3, #0
800aff4: d046 beq.n 800b084 <HAL_RCCEx_PeriphCLKConfig+0x120>
{
uint32_t rtcclocksource = LL_RCC_GetRTCClockSource();
800aff6: f7ff ff56 bl 800aea6 <LL_RCC_GetRTCClockSource>
800affa: 61b8 str r0, [r7, #24]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Configure the clock source only if a different source is expected */
if (rtcclocksource != PeriphClkInit->RTCClockSelection)
800affc: 687b ldr r3, [r7, #4]
800affe: 6c1b ldr r3, [r3, #64] @ 0x40
800b000: 69ba ldr r2, [r7, #24]
800b002: 429a cmp r2, r3
800b004: d03c beq.n 800b080 <HAL_RCCEx_PeriphCLKConfig+0x11c>
{
/* Enable write access to Backup domain */
HAL_PWR_EnableBkUpAccess();
800b006: f7fe fc21 bl 800984c <HAL_PWR_EnableBkUpAccess>
/* If a clock source is not yet selected */
if (rtcclocksource == RCC_RTCCLKSOURCE_NONE)
800b00a: 69bb ldr r3, [r7, #24]
800b00c: 2b00 cmp r3, #0
800b00e: d105 bne.n 800b01c <HAL_RCCEx_PeriphCLKConfig+0xb8>
{
/* Directly set the configuration of the clock source selection */
LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection);
800b010: 687b ldr r3, [r7, #4]
800b012: 6c1b ldr r3, [r3, #64] @ 0x40
800b014: 4618 mov r0, r3
800b016: f7ff ff30 bl 800ae7a <LL_RCC_SetRTCClockSource>
800b01a: e02e b.n 800b07a <HAL_RCCEx_PeriphCLKConfig+0x116>
}
else /* A clock source is already selected */
{
/* Store the content of BDCR register before the reset of Backup Domain */
uint32_t bdcr = LL_RCC_ReadReg(BDCR);
800b01c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b020: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800b024: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
LL_RCC_ForceBackupDomainReset();
800b026: f7ff ff4b bl 800aec0 <LL_RCC_ForceBackupDomainReset>
LL_RCC_ReleaseBackupDomainReset();
800b02a: f7ff ff5a bl 800aee2 <LL_RCC_ReleaseBackupDomainReset>
/* Set the value of the clock source selection */
MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection);
800b02e: 697b ldr r3, [r7, #20]
800b030: f423 7240 bic.w r2, r3, #768 @ 0x300
800b034: 687b ldr r3, [r7, #4]
800b036: 6c1b ldr r3, [r3, #64] @ 0x40
800b038: 4313 orrs r3, r2
800b03a: 617b str r3, [r7, #20]
/* Restore the content of BDCR register */
LL_RCC_WriteReg(BDCR, bdcr);
800b03c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800b040: 697b ldr r3, [r7, #20]
800b042: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (LL_RCC_LSE_IsEnabled() == 1U)
800b046: f7ff fde1 bl 800ac0c <LL_RCC_LSE_IsEnabled>
800b04a: 4603 mov r3, r0
800b04c: 2b01 cmp r3, #1
800b04e: d114 bne.n 800b07a <HAL_RCCEx_PeriphCLKConfig+0x116>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800b050: f7fa f988 bl 8005364 <HAL_GetTick>
800b054: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (LL_RCC_LSE_IsReady() != 1U)
800b056: e00b b.n 800b070 <HAL_RCCEx_PeriphCLKConfig+0x10c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800b058: f7fa f984 bl 8005364 <HAL_GetTick>
800b05c: 4602 mov r2, r0
800b05e: 693b ldr r3, [r7, #16]
800b060: 1ad3 subs r3, r2, r3
800b062: f241 3288 movw r2, #5000 @ 0x1388
800b066: 4293 cmp r3, r2
800b068: d902 bls.n 800b070 <HAL_RCCEx_PeriphCLKConfig+0x10c>
{
ret = HAL_TIMEOUT;
800b06a: 2303 movs r3, #3
800b06c: 77fb strb r3, [r7, #31]
break;
800b06e: e004 b.n 800b07a <HAL_RCCEx_PeriphCLKConfig+0x116>
while (LL_RCC_LSE_IsReady() != 1U)
800b070: f7ff fdde bl 800ac30 <LL_RCC_LSE_IsReady>
800b074: 4603 mov r3, r0
800b076: 2b01 cmp r3, #1
800b078: d1ee bne.n 800b058 <HAL_RCCEx_PeriphCLKConfig+0xf4>
}
}
}
/* set overall return value */
status = ret;
800b07a: 7ffb ldrb r3, [r7, #31]
800b07c: 77bb strb r3, [r7, #30]
800b07e: e001 b.n 800b084 <HAL_RCCEx_PeriphCLKConfig+0x120>
}
else
{
/* set overall return value */
status = ret;
800b080: 7ffb ldrb r3, [r7, #31]
800b082: 77bb strb r3, [r7, #30]
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
800b084: 687b ldr r3, [r7, #4]
800b086: 681b ldr r3, [r3, #0]
800b088: f003 0301 and.w r3, r3, #1
800b08c: 2b00 cmp r3, #0
800b08e: d004 beq.n 800b09a <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
800b090: 687b ldr r3, [r7, #4]
800b092: 699b ldr r3, [r3, #24]
800b094: 4618 mov r0, r3
800b096: f7ff fe2a bl 800acee <LL_RCC_SetUSARTClockSource>
}
#if defined(LPUART1)
/*-------------------------- LPUART1 clock source configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
800b09a: 687b ldr r3, [r7, #4]
800b09c: 681b ldr r3, [r3, #0]
800b09e: f003 0302 and.w r3, r3, #2
800b0a2: 2b00 cmp r3, #0
800b0a4: d004 beq.n 800b0b0 <HAL_RCCEx_PeriphCLKConfig+0x14c>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
800b0a6: 687b ldr r3, [r7, #4]
800b0a8: 69db ldr r3, [r3, #28]
800b0aa: 4618 mov r0, r3
800b0ac: f7ff fe35 bl 800ad1a <LL_RCC_SetLPUARTClockSource>
}
#endif /* LPUART1 */
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
800b0b0: 687b ldr r3, [r7, #4]
800b0b2: 681b ldr r3, [r3, #0]
800b0b4: f003 0310 and.w r3, r3, #16
800b0b8: 2b00 cmp r3, #0
800b0ba: d004 beq.n 800b0c6 <HAL_RCCEx_PeriphCLKConfig+0x162>
{
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
800b0bc: 687b ldr r3, [r7, #4]
800b0be: 6a9b ldr r3, [r3, #40] @ 0x28
800b0c0: 4618 mov r0, r3
800b0c2: f7ff fe5d bl 800ad80 <LL_RCC_SetLPTIMClockSource>
}
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
800b0c6: 687b ldr r3, [r7, #4]
800b0c8: 681b ldr r3, [r3, #0]
800b0ca: f003 0320 and.w r3, r3, #32
800b0ce: 2b00 cmp r3, #0
800b0d0: d004 beq.n 800b0dc <HAL_RCCEx_PeriphCLKConfig+0x178>
{
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
800b0d2: 687b ldr r3, [r7, #4]
800b0d4: 6adb ldr r3, [r3, #44] @ 0x2c
800b0d6: 4618 mov r0, r3
800b0d8: f7ff fe52 bl 800ad80 <LL_RCC_SetLPTIMClockSource>
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
800b0dc: 687b ldr r3, [r7, #4]
800b0de: 681b ldr r3, [r3, #0]
800b0e0: f003 0304 and.w r3, r3, #4
800b0e4: 2b00 cmp r3, #0
800b0e6: d004 beq.n 800b0f2 <HAL_RCCEx_PeriphCLKConfig+0x18e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
800b0e8: 687b ldr r3, [r7, #4]
800b0ea: 6a1b ldr r3, [r3, #32]
800b0ec: 4618 mov r0, r3
800b0ee: f7ff fe2a bl 800ad46 <LL_RCC_SetI2CClockSource>
}
#if defined(I2C3)
/*-------------------------- I2C3 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
800b0f2: 687b ldr r3, [r7, #4]
800b0f4: 681b ldr r3, [r3, #0]
800b0f6: f003 0308 and.w r3, r3, #8
800b0fa: 2b00 cmp r3, #0
800b0fc: d004 beq.n 800b108 <HAL_RCCEx_PeriphCLKConfig+0x1a4>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
800b0fe: 687b ldr r3, [r7, #4]
800b100: 6a5b ldr r3, [r3, #36] @ 0x24
800b102: 4618 mov r0, r3
800b104: f7ff fe1f bl 800ad46 <LL_RCC_SetI2CClockSource>
}
#endif /* I2C3 */
#if defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
800b108: 687b ldr r3, [r7, #4]
800b10a: 681b ldr r3, [r3, #0]
800b10c: f403 7380 and.w r3, r3, #256 @ 0x100
800b110: 2b00 cmp r3, #0
800b112: d022 beq.n 800b15a <HAL_RCCEx_PeriphCLKConfig+0x1f6>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
800b114: 687b ldr r3, [r7, #4]
800b116: 6b5b ldr r3, [r3, #52] @ 0x34
800b118: 4618 mov r0, r3
800b11a: f7ff fe8d bl 800ae38 <LL_RCC_SetUSBClockSource>
if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
800b11e: 687b ldr r3, [r7, #4]
800b120: 6b5b ldr r3, [r3, #52] @ 0x34
800b122: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
800b126: d107 bne.n 800b138 <HAL_RCCEx_PeriphCLKConfig+0x1d4>
{
/* Enable PLLQ output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK);
800b128: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b12c: 68db ldr r3, [r3, #12]
800b12e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800b132: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800b136: 60d3 str r3, [r2, #12]
}
#if defined(SAI1)
if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
800b138: 687b ldr r3, [r7, #4]
800b13a: 6b5b ldr r3, [r3, #52] @ 0x34
800b13c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
800b140: d10b bne.n 800b15a <HAL_RCCEx_PeriphCLKConfig+0x1f6>
{
/* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
800b142: 687b ldr r3, [r7, #4]
800b144: 3304 adds r3, #4
800b146: 4618 mov r0, r3
800b148: f000 f8e3 bl 800b312 <RCCEx_PLLSAI1_ConfigNQ>
800b14c: 4603 mov r3, r0
800b14e: 77fb strb r3, [r7, #31]
if (ret != HAL_OK)
800b150: 7ffb ldrb r3, [r7, #31]
800b152: 2b00 cmp r3, #0
800b154: d001 beq.n 800b15a <HAL_RCCEx_PeriphCLKConfig+0x1f6>
{
/* set overall return value */
status = ret;
800b156: 7ffb ldrb r3, [r7, #31]
800b158: 77bb strb r3, [r7, #30]
#endif /* SAI1 */
}
#endif /* USB */
/*-------------------------- RNG clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
800b15a: 687b ldr r3, [r7, #4]
800b15c: 681b ldr r3, [r3, #0]
800b15e: f403 7300 and.w r3, r3, #512 @ 0x200
800b162: 2b00 cmp r3, #0
800b164: d02b beq.n 800b1be <HAL_RCCEx_PeriphCLKConfig+0x25a>
{
/* Check the parameters */
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
/* Configure the RNG clock source */
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
800b166: 687b ldr r3, [r7, #4]
800b168: 6b9b ldr r3, [r3, #56] @ 0x38
800b16a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800b16e: d008 beq.n 800b182 <HAL_RCCEx_PeriphCLKConfig+0x21e>
800b170: 687b ldr r3, [r7, #4]
800b172: 6b9b ldr r3, [r3, #56] @ 0x38
800b174: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
800b178: d003 beq.n 800b182 <HAL_RCCEx_PeriphCLKConfig+0x21e>
800b17a: 687b ldr r3, [r7, #4]
800b17c: 6b9b ldr r3, [r3, #56] @ 0x38
800b17e: 2b00 cmp r3, #0
800b180: d105 bne.n 800b18e <HAL_RCCEx_PeriphCLKConfig+0x22a>
800b182: 687b ldr r3, [r7, #4]
800b184: 6b9b ldr r3, [r3, #56] @ 0x38
800b186: 4618 mov r0, r3
800b188: f7ff fe2a bl 800ade0 <LL_RCC_SetRNGClockSource>
800b18c: e00a b.n 800b1a4 <HAL_RCCEx_PeriphCLKConfig+0x240>
800b18e: 687b ldr r3, [r7, #4]
800b190: 6b9b ldr r3, [r3, #56] @ 0x38
800b192: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800b196: 60fb str r3, [r7, #12]
800b198: 2000 movs r0, #0
800b19a: f7ff fe21 bl 800ade0 <LL_RCC_SetRNGClockSource>
800b19e: 68f8 ldr r0, [r7, #12]
800b1a0: f7ff fe34 bl 800ae0c <LL_RCC_SetCLK48ClockSource>
if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
800b1a4: 687b ldr r3, [r7, #4]
800b1a6: 6b9b ldr r3, [r3, #56] @ 0x38
800b1a8: f1b3 5fc0 cmp.w r3, #402653184 @ 0x18000000
800b1ac: d107 bne.n 800b1be <HAL_RCCEx_PeriphCLKConfig+0x25a>
{
/* Enable PLLQ output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK);
800b1ae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b1b2: 68db ldr r3, [r3, #12]
800b1b4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800b1b8: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800b1bc: 60d3 str r3, [r2, #12]
}
}
/*-------------------------- ADC clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
800b1be: 687b ldr r3, [r7, #4]
800b1c0: 681b ldr r3, [r3, #0]
800b1c2: f403 6380 and.w r3, r3, #1024 @ 0x400
800b1c6: 2b00 cmp r3, #0
800b1c8: d022 beq.n 800b210 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
800b1ca: 687b ldr r3, [r7, #4]
800b1cc: 6bdb ldr r3, [r3, #60] @ 0x3c
800b1ce: 4618 mov r0, r3
800b1d0: f7ff fe3d bl 800ae4e <LL_RCC_SetADCClockSource>
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL)
800b1d4: 687b ldr r3, [r7, #4]
800b1d6: 6bdb ldr r3, [r3, #60] @ 0x3c
800b1d8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
800b1dc: d107 bne.n 800b1ee <HAL_RCCEx_PeriphCLKConfig+0x28a>
{
/* Enable RCC_PLL_RNGCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
800b1de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b1e2: 68db ldr r3, [r3, #12]
800b1e4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
800b1e8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800b1ec: 60d3 str r3, [r2, #12]
}
#if defined(SAI1)
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
800b1ee: 687b ldr r3, [r7, #4]
800b1f0: 6bdb ldr r3, [r3, #60] @ 0x3c
800b1f2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800b1f6: d10b bne.n 800b210 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
{
/* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1));
800b1f8: 687b ldr r3, [r7, #4]
800b1fa: 3304 adds r3, #4
800b1fc: 4618 mov r0, r3
800b1fe: f000 f8e3 bl 800b3c8 <RCCEx_PLLSAI1_ConfigNR>
800b202: 4603 mov r3, r0
800b204: 77fb strb r3, [r7, #31]
if (ret != HAL_OK)
800b206: 7ffb ldrb r3, [r7, #31]
800b208: 2b00 cmp r3, #0
800b20a: d001 beq.n 800b210 <HAL_RCCEx_PeriphCLKConfig+0x2ac>
{
/* set overall return value */
status = ret;
800b20c: 7ffb ldrb r3, [r7, #31]
800b20e: 77bb strb r3, [r7, #30]
}
#endif /* SAI1 */
}
/*-------------------------- RFWKP clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)
800b210: 687b ldr r3, [r7, #4]
800b212: 681b ldr r3, [r3, #0]
800b214: f403 5380 and.w r3, r3, #4096 @ 0x1000
800b218: 2b00 cmp r3, #0
800b21a: d004 beq.n 800b226 <HAL_RCCEx_PeriphCLKConfig+0x2c2>
{
/* Check the parameters */
assert_param(IS_RCC_RFWKPCLKSOURCE(PeriphClkInit->RFWakeUpClockSelection));
/* Configure the RFWKP interface clock source */
__HAL_RCC_RFWAKEUP_CONFIG(PeriphClkInit->RFWakeUpClockSelection);
800b21c: 687b ldr r3, [r7, #4]
800b21e: 6c5b ldr r3, [r3, #68] @ 0x44
800b220: 4618 mov r0, r3
800b222: f7ff fd26 bl 800ac72 <LL_RCC_SetRFWKPClockSource>
}
#if defined(RCC_SMPS_SUPPORT)
/*-------------------------- SMPS clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)
800b226: 687b ldr r3, [r7, #4]
800b228: 681b ldr r3, [r3, #0]
800b22a: f403 5300 and.w r3, r3, #8192 @ 0x2000
800b22e: 2b00 cmp r3, #0
800b230: d009 beq.n 800b246 <HAL_RCCEx_PeriphCLKConfig+0x2e2>
/* Check the parameters */
assert_param(IS_RCC_SMPSCLKDIV(PeriphClkInit->SmpsDivSelection));
assert_param(IS_RCC_SMPSCLKSOURCE(PeriphClkInit->SmpsClockSelection));
/* Configure the SMPS interface clock division factor */
__HAL_RCC_SMPS_DIV_CONFIG(PeriphClkInit->SmpsDivSelection);
800b232: 687b ldr r3, [r7, #4]
800b234: 6cdb ldr r3, [r3, #76] @ 0x4c
800b236: 4618 mov r0, r3
800b238: f7ff fd45 bl 800acc6 <LL_RCC_SetSMPSPrescaler>
/* Configure the SMPS interface clock source */
__HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection);
800b23c: 687b ldr r3, [r7, #4]
800b23e: 6c9b ldr r3, [r3, #72] @ 0x48
800b240: 4618 mov r0, r3
800b242: f7ff fd2c bl 800ac9e <LL_RCC_SetSMPSClockSource>
}
#endif /* RCC_SMPS_SUPPORT */
return status;
800b246: 7fbb ldrb r3, [r7, #30]
}
800b248: 4618 mov r0, r3
800b24a: 3720 adds r7, #32
800b24c: 46bd mov sp, r7
800b24e: bd80 pop {r7, pc}
0800b250 <HAL_RCCEx_EnableMSIPLLMode>:
* @note Prior to enable the PLL-mode of the MSI for automatic hardware
* calibration LSE oscillator is to be enabled with @ref HAL_RCC_OscConfig().
* @retval None
*/
void HAL_RCCEx_EnableMSIPLLMode(void)
{
800b250: b580 push {r7, lr}
800b252: af00 add r7, sp, #0
LL_RCC_MSI_EnablePLLMode() ;
800b254: f7ff fcfe bl 800ac54 <LL_RCC_MSI_EnablePLLMode>
}
800b258: bf00 nop
800b25a: bd80 pop {r7, pc}
0800b25c <RCCEx_PLLSAI1_ConfigNP>:
* @note PLLSAI1 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1)
{
800b25c: b580 push {r7, lr}
800b25e: b084 sub sp, #16
800b260: af00 add r7, sp, #0
800b262: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
800b264: 2300 movs r3, #0
800b266: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
assert_param(IS_RCC_PLLP_VALUE(PLLSAI1->PLLP));
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
/* Disable the PLLSAI1 */
__HAL_RCC_PLLSAI1_DISABLE();
800b268: f7ff fe5b bl 800af22 <LL_RCC_PLLSAI1_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800b26c: f7fa f87a bl 8005364 <HAL_GetTick>
800b270: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready to be updated */
while (LL_RCC_PLLSAI1_IsReady() != 0U)
800b272: e009 b.n 800b288 <RCCEx_PLLSAI1_ConfigNP+0x2c>
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
800b274: f7fa f876 bl 8005364 <HAL_GetTick>
800b278: 4602 mov r2, r0
800b27a: 68bb ldr r3, [r7, #8]
800b27c: 1ad3 subs r3, r2, r3
800b27e: 2b02 cmp r3, #2
800b280: d902 bls.n 800b288 <RCCEx_PLLSAI1_ConfigNP+0x2c>
{
status = HAL_TIMEOUT;
800b282: 2303 movs r3, #3
800b284: 73fb strb r3, [r7, #15]
break;
800b286: e004 b.n 800b292 <RCCEx_PLLSAI1_ConfigNP+0x36>
while (LL_RCC_PLLSAI1_IsReady() != 0U)
800b288: f7ff fe5a bl 800af40 <LL_RCC_PLLSAI1_IsReady>
800b28c: 4603 mov r3, r0
800b28e: 2b00 cmp r3, #0
800b290: d1f0 bne.n 800b274 <RCCEx_PLLSAI1_ConfigNP+0x18>
}
}
if (status == HAL_OK)
800b292: 7bfb ldrb r3, [r7, #15]
800b294: 2b00 cmp r3, #0
800b296: d137 bne.n 800b308 <RCCEx_PLLSAI1_ConfigNP+0xac>
{
/* Configure the PLLSAI1 Multiplication factor N */
__HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
800b298: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b29c: 691b ldr r3, [r3, #16]
800b29e: f423 42fe bic.w r2, r3, #32512 @ 0x7f00
800b2a2: 687b ldr r3, [r7, #4]
800b2a4: 681b ldr r3, [r3, #0]
800b2a6: 021b lsls r3, r3, #8
800b2a8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b2ac: 4313 orrs r3, r2
800b2ae: 610b str r3, [r1, #16]
/* Configure the PLLSAI1 Division factor P */
__HAL_RCC_PLLSAI1_DIVP_CONFIG(PLLSAI1->PLLP);
800b2b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b2b4: 691b ldr r3, [r3, #16]
800b2b6: f423 1278 bic.w r2, r3, #4063232 @ 0x3e0000
800b2ba: 687b ldr r3, [r7, #4]
800b2bc: 685b ldr r3, [r3, #4]
800b2be: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b2c2: 4313 orrs r3, r2
800b2c4: 610b str r3, [r1, #16]
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
__HAL_RCC_PLLSAI1_ENABLE();
800b2c6: f7ff fe1d bl 800af04 <LL_RCC_PLLSAI1_Enable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800b2ca: f7fa f84b bl 8005364 <HAL_GetTick>
800b2ce: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready */
while (LL_RCC_PLLSAI1_IsReady() != 1U)
800b2d0: e009 b.n 800b2e6 <RCCEx_PLLSAI1_ConfigNP+0x8a>
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
800b2d2: f7fa f847 bl 8005364 <HAL_GetTick>
800b2d6: 4602 mov r2, r0
800b2d8: 68bb ldr r3, [r7, #8]
800b2da: 1ad3 subs r3, r2, r3
800b2dc: 2b02 cmp r3, #2
800b2de: d902 bls.n 800b2e6 <RCCEx_PLLSAI1_ConfigNP+0x8a>
{
status = HAL_TIMEOUT;
800b2e0: 2303 movs r3, #3
800b2e2: 73fb strb r3, [r7, #15]
break;
800b2e4: e004 b.n 800b2f0 <RCCEx_PLLSAI1_ConfigNP+0x94>
while (LL_RCC_PLLSAI1_IsReady() != 1U)
800b2e6: f7ff fe2b bl 800af40 <LL_RCC_PLLSAI1_IsReady>
800b2ea: 4603 mov r3, r0
800b2ec: 2b01 cmp r3, #1
800b2ee: d1f0 bne.n 800b2d2 <RCCEx_PLLSAI1_ConfigNP+0x76>
}
}
if (status == HAL_OK)
800b2f0: 7bfb ldrb r3, [r7, #15]
800b2f2: 2b00 cmp r3, #0
800b2f4: d108 bne.n 800b308 <RCCEx_PLLSAI1_ConfigNP+0xac>
{
/* Configure the PLLSAI1 Clock output(s) */
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
800b2f6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b2fa: 691a ldr r2, [r3, #16]
800b2fc: 687b ldr r3, [r7, #4]
800b2fe: 691b ldr r3, [r3, #16]
800b300: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b304: 4313 orrs r3, r2
800b306: 610b str r3, [r1, #16]
}
}
return status;
800b308: 7bfb ldrb r3, [r7, #15]
}
800b30a: 4618 mov r0, r3
800b30c: 3710 adds r7, #16
800b30e: 46bd mov sp, r7
800b310: bd80 pop {r7, pc}
0800b312 <RCCEx_PLLSAI1_ConfigNQ>:
* @note PLLSAI1 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1)
{
800b312: b580 push {r7, lr}
800b314: b084 sub sp, #16
800b316: af00 add r7, sp, #0
800b318: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
800b31a: 2300 movs r3, #0
800b31c: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
assert_param(IS_RCC_PLLQ_VALUE(PLLSAI1->PLLQ));
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
/* Disable the PLLSAI1 */
__HAL_RCC_PLLSAI1_DISABLE();
800b31e: f7ff fe00 bl 800af22 <LL_RCC_PLLSAI1_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800b322: f7fa f81f bl 8005364 <HAL_GetTick>
800b326: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready to be updated */
while (LL_RCC_PLLSAI1_IsReady() != 0U)
800b328: e009 b.n 800b33e <RCCEx_PLLSAI1_ConfigNQ+0x2c>
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
800b32a: f7fa f81b bl 8005364 <HAL_GetTick>
800b32e: 4602 mov r2, r0
800b330: 68bb ldr r3, [r7, #8]
800b332: 1ad3 subs r3, r2, r3
800b334: 2b02 cmp r3, #2
800b336: d902 bls.n 800b33e <RCCEx_PLLSAI1_ConfigNQ+0x2c>
{
status = HAL_TIMEOUT;
800b338: 2303 movs r3, #3
800b33a: 73fb strb r3, [r7, #15]
break;
800b33c: e004 b.n 800b348 <RCCEx_PLLSAI1_ConfigNQ+0x36>
while (LL_RCC_PLLSAI1_IsReady() != 0U)
800b33e: f7ff fdff bl 800af40 <LL_RCC_PLLSAI1_IsReady>
800b342: 4603 mov r3, r0
800b344: 2b00 cmp r3, #0
800b346: d1f0 bne.n 800b32a <RCCEx_PLLSAI1_ConfigNQ+0x18>
}
}
if (status == HAL_OK)
800b348: 7bfb ldrb r3, [r7, #15]
800b34a: 2b00 cmp r3, #0
800b34c: d137 bne.n 800b3be <RCCEx_PLLSAI1_ConfigNQ+0xac>
{
/* Configure the PLLSAI1 Multiplication factor N */
__HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
800b34e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b352: 691b ldr r3, [r3, #16]
800b354: f423 42fe bic.w r2, r3, #32512 @ 0x7f00
800b358: 687b ldr r3, [r7, #4]
800b35a: 681b ldr r3, [r3, #0]
800b35c: 021b lsls r3, r3, #8
800b35e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b362: 4313 orrs r3, r2
800b364: 610b str r3, [r1, #16]
/* Configure the PLLSAI1 Division factor Q */
__HAL_RCC_PLLSAI1_DIVQ_CONFIG(PLLSAI1->PLLQ);
800b366: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b36a: 691b ldr r3, [r3, #16]
800b36c: f023 6260 bic.w r2, r3, #234881024 @ 0xe000000
800b370: 687b ldr r3, [r7, #4]
800b372: 689b ldr r3, [r3, #8]
800b374: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b378: 4313 orrs r3, r2
800b37a: 610b str r3, [r1, #16]
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
__HAL_RCC_PLLSAI1_ENABLE();
800b37c: f7ff fdc2 bl 800af04 <LL_RCC_PLLSAI1_Enable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800b380: f7f9 fff0 bl 8005364 <HAL_GetTick>
800b384: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready */
while (LL_RCC_PLLSAI1_IsReady() != 1U)
800b386: e009 b.n 800b39c <RCCEx_PLLSAI1_ConfigNQ+0x8a>
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
800b388: f7f9 ffec bl 8005364 <HAL_GetTick>
800b38c: 4602 mov r2, r0
800b38e: 68bb ldr r3, [r7, #8]
800b390: 1ad3 subs r3, r2, r3
800b392: 2b02 cmp r3, #2
800b394: d902 bls.n 800b39c <RCCEx_PLLSAI1_ConfigNQ+0x8a>
{
status = HAL_TIMEOUT;
800b396: 2303 movs r3, #3
800b398: 73fb strb r3, [r7, #15]
break;
800b39a: e004 b.n 800b3a6 <RCCEx_PLLSAI1_ConfigNQ+0x94>
while (LL_RCC_PLLSAI1_IsReady() != 1U)
800b39c: f7ff fdd0 bl 800af40 <LL_RCC_PLLSAI1_IsReady>
800b3a0: 4603 mov r3, r0
800b3a2: 2b01 cmp r3, #1
800b3a4: d1f0 bne.n 800b388 <RCCEx_PLLSAI1_ConfigNQ+0x76>
}
}
if (status == HAL_OK)
800b3a6: 7bfb ldrb r3, [r7, #15]
800b3a8: 2b00 cmp r3, #0
800b3aa: d108 bne.n 800b3be <RCCEx_PLLSAI1_ConfigNQ+0xac>
{
/* Configure the PLLSAI1 Clock output(s) */
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
800b3ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b3b0: 691a ldr r2, [r3, #16]
800b3b2: 687b ldr r3, [r7, #4]
800b3b4: 691b ldr r3, [r3, #16]
800b3b6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b3ba: 4313 orrs r3, r2
800b3bc: 610b str r3, [r1, #16]
}
}
return status;
800b3be: 7bfb ldrb r3, [r7, #15]
}
800b3c0: 4618 mov r0, r3
800b3c2: 3710 adds r7, #16
800b3c4: 46bd mov sp, r7
800b3c6: bd80 pop {r7, pc}
0800b3c8 <RCCEx_PLLSAI1_ConfigNR>:
* @note PLLSAI1 is temporary disable to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1)
{
800b3c8: b580 push {r7, lr}
800b3ca: b084 sub sp, #16
800b3cc: af00 add r7, sp, #0
800b3ce: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
800b3d0: 2300 movs r3, #0
800b3d2: 73fb strb r3, [r7, #15]
assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
assert_param(IS_RCC_PLLR_VALUE(PLLSAI1->PLLR));
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
/* Disable the PLLSAI1 */
__HAL_RCC_PLLSAI1_DISABLE();
800b3d4: f7ff fda5 bl 800af22 <LL_RCC_PLLSAI1_Disable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800b3d8: f7f9 ffc4 bl 8005364 <HAL_GetTick>
800b3dc: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready to be updated */
while (LL_RCC_PLLSAI1_IsReady() != 0U)
800b3de: e009 b.n 800b3f4 <RCCEx_PLLSAI1_ConfigNR+0x2c>
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
800b3e0: f7f9 ffc0 bl 8005364 <HAL_GetTick>
800b3e4: 4602 mov r2, r0
800b3e6: 68bb ldr r3, [r7, #8]
800b3e8: 1ad3 subs r3, r2, r3
800b3ea: 2b02 cmp r3, #2
800b3ec: d902 bls.n 800b3f4 <RCCEx_PLLSAI1_ConfigNR+0x2c>
{
status = HAL_TIMEOUT;
800b3ee: 2303 movs r3, #3
800b3f0: 73fb strb r3, [r7, #15]
break;
800b3f2: e004 b.n 800b3fe <RCCEx_PLLSAI1_ConfigNR+0x36>
while (LL_RCC_PLLSAI1_IsReady() != 0U)
800b3f4: f7ff fda4 bl 800af40 <LL_RCC_PLLSAI1_IsReady>
800b3f8: 4603 mov r3, r0
800b3fa: 2b00 cmp r3, #0
800b3fc: d1f0 bne.n 800b3e0 <RCCEx_PLLSAI1_ConfigNR+0x18>
}
}
if (status == HAL_OK)
800b3fe: 7bfb ldrb r3, [r7, #15]
800b400: 2b00 cmp r3, #0
800b402: d137 bne.n 800b474 <RCCEx_PLLSAI1_ConfigNR+0xac>
{
/* Configure the PLLSAI1 Multiplication factor N */
__HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
800b404: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b408: 691b ldr r3, [r3, #16]
800b40a: f423 42fe bic.w r2, r3, #32512 @ 0x7f00
800b40e: 687b ldr r3, [r7, #4]
800b410: 681b ldr r3, [r3, #0]
800b412: 021b lsls r3, r3, #8
800b414: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b418: 4313 orrs r3, r2
800b41a: 610b str r3, [r1, #16]
/* Configure the PLLSAI1 Division factor R */
__HAL_RCC_PLLSAI1_DIVR_CONFIG(PLLSAI1->PLLR);
800b41c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b420: 691b ldr r3, [r3, #16]
800b422: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000
800b426: 687b ldr r3, [r7, #4]
800b428: 68db ldr r3, [r3, #12]
800b42a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b42e: 4313 orrs r3, r2
800b430: 610b str r3, [r1, #16]
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
__HAL_RCC_PLLSAI1_ENABLE();
800b432: f7ff fd67 bl 800af04 <LL_RCC_PLLSAI1_Enable>
/* Get Start Tick*/
tickstart = HAL_GetTick();
800b436: f7f9 ff95 bl 8005364 <HAL_GetTick>
800b43a: 60b8 str r0, [r7, #8]
/* Wait till PLLSAI1 is ready */
while (LL_RCC_PLLSAI1_IsReady() != 1U)
800b43c: e009 b.n 800b452 <RCCEx_PLLSAI1_ConfigNR+0x8a>
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
800b43e: f7f9 ff91 bl 8005364 <HAL_GetTick>
800b442: 4602 mov r2, r0
800b444: 68bb ldr r3, [r7, #8]
800b446: 1ad3 subs r3, r2, r3
800b448: 2b02 cmp r3, #2
800b44a: d902 bls.n 800b452 <RCCEx_PLLSAI1_ConfigNR+0x8a>
{
status = HAL_TIMEOUT;
800b44c: 2303 movs r3, #3
800b44e: 73fb strb r3, [r7, #15]
break;
800b450: e004 b.n 800b45c <RCCEx_PLLSAI1_ConfigNR+0x94>
while (LL_RCC_PLLSAI1_IsReady() != 1U)
800b452: f7ff fd75 bl 800af40 <LL_RCC_PLLSAI1_IsReady>
800b456: 4603 mov r3, r0
800b458: 2b01 cmp r3, #1
800b45a: d1f0 bne.n 800b43e <RCCEx_PLLSAI1_ConfigNR+0x76>
}
}
if (status == HAL_OK)
800b45c: 7bfb ldrb r3, [r7, #15]
800b45e: 2b00 cmp r3, #0
800b460: d108 bne.n 800b474 <RCCEx_PLLSAI1_ConfigNR+0xac>
{
/* Configure the PLLSAI1 Clock output(s) */
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
800b462: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
800b466: 691a ldr r2, [r3, #16]
800b468: 687b ldr r3, [r7, #4]
800b46a: 691b ldr r3, [r3, #16]
800b46c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
800b470: 4313 orrs r3, r2
800b472: 610b str r3, [r1, #16]
}
}
return status;
800b474: 7bfb ldrb r3, [r7, #15]
}
800b476: 4618 mov r0, r3
800b478: 3710 adds r7, #16
800b47a: 46bd mov sp, r7
800b47c: bd80 pop {r7, pc}
0800b47e <HAL_RTC_Init>:
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
800b47e: b580 push {r7, lr}
800b480: b084 sub sp, #16
800b482: af00 add r7, sp, #0
800b484: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status;
/* Check RTC handler validity */
if (hrtc == NULL)
800b486: 687b ldr r3, [r7, #4]
800b488: 2b00 cmp r3, #0
800b48a: d101 bne.n 800b490 <HAL_RTC_Init+0x12>
{
return HAL_ERROR;
800b48c: 2301 movs r3, #1
800b48e: e07a b.n 800b586 <HAL_RTC_Init+0x108>
{
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
}
}
#else /* USE_HAL_RTC_REGISTER_CALLBACKS */
if (hrtc->State == HAL_RTC_STATE_RESET)
800b490: 687b ldr r3, [r7, #4]
800b492: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
800b496: b2db uxtb r3, r3
800b498: 2b00 cmp r3, #0
800b49a: d106 bne.n 800b4aa <HAL_RTC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
800b49c: 687b ldr r3, [r7, #4]
800b49e: 2200 movs r2, #0
800b4a0: f883 2020 strb.w r2, [r3, #32]
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
800b4a4: 6878 ldr r0, [r7, #4]
800b4a6: f7f9 fba7 bl 8004bf8 <HAL_RTC_MspInit>
}
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
800b4aa: 687b ldr r3, [r7, #4]
800b4ac: 2202 movs r2, #2
800b4ae: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Check whether the calendar needs to be initialized */
if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
800b4b2: 687b ldr r3, [r7, #4]
800b4b4: 681b ldr r3, [r3, #0]
800b4b6: 68db ldr r3, [r3, #12]
800b4b8: f003 0310 and.w r3, r3, #16
800b4bc: 2b10 cmp r3, #16
800b4be: d058 beq.n 800b572 <HAL_RTC_Init+0xf4>
{
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
800b4c0: 687b ldr r3, [r7, #4]
800b4c2: 681b ldr r3, [r3, #0]
800b4c4: 22ca movs r2, #202 @ 0xca
800b4c6: 625a str r2, [r3, #36] @ 0x24
800b4c8: 687b ldr r3, [r7, #4]
800b4ca: 681b ldr r3, [r3, #0]
800b4cc: 2253 movs r2, #83 @ 0x53
800b4ce: 625a str r2, [r3, #36] @ 0x24
/* Enter Initialization mode */
status = RTC_EnterInitMode(hrtc);
800b4d0: 6878 ldr r0, [r7, #4]
800b4d2: f000 f883 bl 800b5dc <RTC_EnterInitMode>
800b4d6: 4603 mov r3, r0
800b4d8: 73fb strb r3, [r7, #15]
if (status == HAL_OK)
800b4da: 7bfb ldrb r3, [r7, #15]
800b4dc: 2b00 cmp r3, #0
800b4de: d12c bne.n 800b53a <HAL_RTC_Init+0xbc>
{
/* Clear RTC_CR FMT, OSEL and POL Bits */
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
800b4e0: 687b ldr r3, [r7, #4]
800b4e2: 681b ldr r3, [r3, #0]
800b4e4: 689b ldr r3, [r3, #8]
800b4e6: 687a ldr r2, [r7, #4]
800b4e8: 6812 ldr r2, [r2, #0]
800b4ea: f423 03e0 bic.w r3, r3, #7340032 @ 0x700000
800b4ee: f023 0340 bic.w r3, r3, #64 @ 0x40
800b4f2: 6093 str r3, [r2, #8]
/* Set RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
800b4f4: 687b ldr r3, [r7, #4]
800b4f6: 681b ldr r3, [r3, #0]
800b4f8: 6899 ldr r1, [r3, #8]
800b4fa: 687b ldr r3, [r7, #4]
800b4fc: 685a ldr r2, [r3, #4]
800b4fe: 687b ldr r3, [r7, #4]
800b500: 691b ldr r3, [r3, #16]
800b502: 431a orrs r2, r3
800b504: 687b ldr r3, [r7, #4]
800b506: 699b ldr r3, [r3, #24]
800b508: 431a orrs r2, r3
800b50a: 687b ldr r3, [r7, #4]
800b50c: 681b ldr r3, [r3, #0]
800b50e: 430a orrs r2, r1
800b510: 609a str r2, [r3, #8]
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
800b512: 687b ldr r3, [r7, #4]
800b514: 681b ldr r3, [r3, #0]
800b516: 687a ldr r2, [r7, #4]
800b518: 68d2 ldr r2, [r2, #12]
800b51a: 611a str r2, [r3, #16]
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
800b51c: 687b ldr r3, [r7, #4]
800b51e: 681b ldr r3, [r3, #0]
800b520: 6919 ldr r1, [r3, #16]
800b522: 687b ldr r3, [r7, #4]
800b524: 689b ldr r3, [r3, #8]
800b526: 041a lsls r2, r3, #16
800b528: 687b ldr r3, [r7, #4]
800b52a: 681b ldr r3, [r3, #0]
800b52c: 430a orrs r2, r1
800b52e: 611a str r2, [r3, #16]
/* Exit Initialization mode */
status = RTC_ExitInitMode(hrtc);
800b530: 6878 ldr r0, [r7, #4]
800b532: f000 f88b bl 800b64c <RTC_ExitInitMode>
800b536: 4603 mov r3, r0
800b538: 73fb strb r3, [r7, #15]
}
if (status == HAL_OK)
800b53a: 7bfb ldrb r3, [r7, #15]
800b53c: 2b00 cmp r3, #0
800b53e: d113 bne.n 800b568 <HAL_RTC_Init+0xea>
{
#if defined(RTC_OR_ALARMOUTTYPE)
hrtc->Instance->OR &= (uint32_t)~(RTC_OUTPUT_TYPE_PUSHPULL | RTC_OUTPUT_REMAP_POS1);
800b540: 687b ldr r3, [r7, #4]
800b542: 681b ldr r3, [r3, #0]
800b544: 6cda ldr r2, [r3, #76] @ 0x4c
800b546: 687b ldr r3, [r7, #4]
800b548: 681b ldr r3, [r3, #0]
800b54a: f022 0203 bic.w r2, r2, #3
800b54e: 64da str r2, [r3, #76] @ 0x4c
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
800b550: 687b ldr r3, [r7, #4]
800b552: 681b ldr r3, [r3, #0]
800b554: 6cd9 ldr r1, [r3, #76] @ 0x4c
800b556: 687b ldr r3, [r7, #4]
800b558: 69da ldr r2, [r3, #28]
800b55a: 687b ldr r3, [r7, #4]
800b55c: 695b ldr r3, [r3, #20]
800b55e: 431a orrs r2, r3
800b560: 687b ldr r3, [r7, #4]
800b562: 681b ldr r3, [r3, #0]
800b564: 430a orrs r2, r1
800b566: 64da str r2, [r3, #76] @ 0x4c
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutRemap);
#endif /* RTC_OR_ALARMOUTTYPE */
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
800b568: 687b ldr r3, [r7, #4]
800b56a: 681b ldr r3, [r3, #0]
800b56c: 22ff movs r2, #255 @ 0xff
800b56e: 625a str r2, [r3, #36] @ 0x24
800b570: e001 b.n 800b576 <HAL_RTC_Init+0xf8>
}
else
{
/* The calendar is already initialized */
status = HAL_OK;
800b572: 2300 movs r3, #0
800b574: 73fb strb r3, [r7, #15]
}
if (status == HAL_OK)
800b576: 7bfb ldrb r3, [r7, #15]
800b578: 2b00 cmp r3, #0
800b57a: d103 bne.n 800b584 <HAL_RTC_Init+0x106>
{
hrtc->State = HAL_RTC_STATE_READY;
800b57c: 687b ldr r3, [r7, #4]
800b57e: 2201 movs r2, #1
800b580: f883 2021 strb.w r2, [r3, #33] @ 0x21
}
return status;
800b584: 7bfb ldrb r3, [r7, #15]
}
800b586: 4618 mov r0, r3
800b588: 3710 adds r7, #16
800b58a: 46bd mov sp, r7
800b58c: bd80 pop {r7, pc}
...
0800b590 <HAL_RTC_WaitForSynchro>:
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
{
800b590: b580 push {r7, lr}
800b592: b084 sub sp, #16
800b594: af00 add r7, sp, #0
800b596: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
800b598: 2300 movs r3, #0
800b59a: 60fb str r3, [r7, #12]
/* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK));
800b59c: 687b ldr r3, [r7, #4]
800b59e: 681b ldr r3, [r3, #0]
800b5a0: 4a0d ldr r2, [pc, #52] @ (800b5d8 <HAL_RTC_WaitForSynchro+0x48>)
800b5a2: 60da str r2, [r3, #12]
/* Get tick */
tickstart = HAL_GetTick();
800b5a4: f7f9 fede bl 8005364 <HAL_GetTick>
800b5a8: 60f8 str r0, [r7, #12]
/* Wait the registers to be synchronised */
while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
800b5aa: e009 b.n 800b5c0 <HAL_RTC_WaitForSynchro+0x30>
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
800b5ac: f7f9 feda bl 8005364 <HAL_GetTick>
800b5b0: 4602 mov r2, r0
800b5b2: 68fb ldr r3, [r7, #12]
800b5b4: 1ad3 subs r3, r2, r3
800b5b6: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
800b5ba: d901 bls.n 800b5c0 <HAL_RTC_WaitForSynchro+0x30>
{
return HAL_TIMEOUT;
800b5bc: 2303 movs r3, #3
800b5be: e007 b.n 800b5d0 <HAL_RTC_WaitForSynchro+0x40>
while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
800b5c0: 687b ldr r3, [r7, #4]
800b5c2: 681b ldr r3, [r3, #0]
800b5c4: 68db ldr r3, [r3, #12]
800b5c6: f003 0320 and.w r3, r3, #32
800b5ca: 2b00 cmp r3, #0
800b5cc: d0ee beq.n 800b5ac <HAL_RTC_WaitForSynchro+0x1c>
}
}
return HAL_OK;
800b5ce: 2300 movs r3, #0
}
800b5d0: 4618 mov r0, r3
800b5d2: 3710 adds r7, #16
800b5d4: 46bd mov sp, r7
800b5d6: bd80 pop {r7, pc}
800b5d8: 0001ff5f .word 0x0001ff5f
0800b5dc <RTC_EnterInitMode>:
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
800b5dc: b580 push {r7, lr}
800b5de: b084 sub sp, #16
800b5e0: af00 add r7, sp, #0
800b5e2: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
800b5e4: 2300 movs r3, #0
800b5e6: 60bb str r3, [r7, #8]
HAL_StatusTypeDef status = HAL_OK;
800b5e8: 2300 movs r3, #0
800b5ea: 73fb strb r3, [r7, #15]
/* Check that Initialization mode is not already set */
if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U)
800b5ec: 687b ldr r3, [r7, #4]
800b5ee: 681b ldr r3, [r3, #0]
800b5f0: 68db ldr r3, [r3, #12]
800b5f2: f003 0340 and.w r3, r3, #64 @ 0x40
800b5f6: 2b00 cmp r3, #0
800b5f8: d123 bne.n 800b642 <RTC_EnterInitMode+0x66>
{
/* Set INIT bit to enter Initialization mode */
SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
800b5fa: 687b ldr r3, [r7, #4]
800b5fc: 681b ldr r3, [r3, #0]
800b5fe: 68da ldr r2, [r3, #12]
800b600: 687b ldr r3, [r7, #4]
800b602: 681b ldr r3, [r3, #0]
800b604: f042 0280 orr.w r2, r2, #128 @ 0x80
800b608: 60da str r2, [r3, #12]
/* Get tick */
tickstart = HAL_GetTick();
800b60a: f7f9 feab bl 8005364 <HAL_GetTick>
800b60e: 60b8 str r0, [r7, #8]
/* Wait till RTC is in INIT state and if timeout is reached exit */
while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR))
800b610: e00d b.n 800b62e <RTC_EnterInitMode+0x52>
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
800b612: f7f9 fea7 bl 8005364 <HAL_GetTick>
800b616: 4602 mov r2, r0
800b618: 68bb ldr r3, [r7, #8]
800b61a: 1ad3 subs r3, r2, r3
800b61c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
800b620: d905 bls.n 800b62e <RTC_EnterInitMode+0x52>
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
800b622: 687b ldr r3, [r7, #4]
800b624: 2204 movs r2, #4
800b626: f883 2021 strb.w r2, [r3, #33] @ 0x21
status = HAL_ERROR;
800b62a: 2301 movs r3, #1
800b62c: 73fb strb r3, [r7, #15]
while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR))
800b62e: 687b ldr r3, [r7, #4]
800b630: 681b ldr r3, [r3, #0]
800b632: 68db ldr r3, [r3, #12]
800b634: f003 0340 and.w r3, r3, #64 @ 0x40
800b638: 2b00 cmp r3, #0
800b63a: d102 bne.n 800b642 <RTC_EnterInitMode+0x66>
800b63c: 7bfb ldrb r3, [r7, #15]
800b63e: 2b01 cmp r3, #1
800b640: d1e7 bne.n 800b612 <RTC_EnterInitMode+0x36>
}
}
}
return status;
800b642: 7bfb ldrb r3, [r7, #15]
}
800b644: 4618 mov r0, r3
800b646: 3710 adds r7, #16
800b648: 46bd mov sp, r7
800b64a: bd80 pop {r7, pc}
0800b64c <RTC_ExitInitMode>:
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
{
800b64c: b580 push {r7, lr}
800b64e: b084 sub sp, #16
800b650: af00 add r7, sp, #0
800b652: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800b654: 2300 movs r3, #0
800b656: 73fb strb r3, [r7, #15]
/* Clear INIT bit to exit Initialization mode */
CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
800b658: 687b ldr r3, [r7, #4]
800b65a: 681b ldr r3, [r3, #0]
800b65c: 68da ldr r2, [r3, #12]
800b65e: 687b ldr r3, [r7, #4]
800b660: 681b ldr r3, [r3, #0]
800b662: f022 0280 bic.w r2, r2, #128 @ 0x80
800b666: 60da str r2, [r3, #12]
/* If CR_BYPSHAD bit = 0, wait for synchro */
if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U)
800b668: 687b ldr r3, [r7, #4]
800b66a: 681b ldr r3, [r3, #0]
800b66c: 689b ldr r3, [r3, #8]
800b66e: f003 0320 and.w r3, r3, #32
800b672: 2b00 cmp r3, #0
800b674: d10b bne.n 800b68e <RTC_ExitInitMode+0x42>
{
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
800b676: 6878 ldr r0, [r7, #4]
800b678: f7ff ff8a bl 800b590 <HAL_RTC_WaitForSynchro>
800b67c: 4603 mov r3, r0
800b67e: 2b00 cmp r3, #0
800b680: d005 beq.n 800b68e <RTC_ExitInitMode+0x42>
{
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
800b682: 687b ldr r3, [r7, #4]
800b684: 2204 movs r2, #4
800b686: f883 2021 strb.w r2, [r3, #33] @ 0x21
status = HAL_ERROR;
800b68a: 2301 movs r3, #1
800b68c: 73fb strb r3, [r7, #15]
}
}
return status;
800b68e: 7bfb ldrb r3, [r7, #15]
}
800b690: 4618 mov r0, r3
800b692: 3710 adds r7, #16
800b694: 46bd mov sp, r7
800b696: bd80 pop {r7, pc}
0800b698 <HAL_RTCEx_SetWakeUpTimer_IT>:
* @param WakeUpCounter Wakeup counter
* @param WakeUpClock Wakeup clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
800b698: b480 push {r7}
800b69a: b087 sub sp, #28
800b69c: af00 add r7, sp, #0
800b69e: 60f8 str r0, [r7, #12]
800b6a0: 60b9 str r1, [r7, #8]
800b6a2: 607a str r2, [r7, #4]
__IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
800b6a4: 4b5f ldr r3, [pc, #380] @ (800b824 <HAL_RTCEx_SetWakeUpTimer_IT+0x18c>)
800b6a6: 681b ldr r3, [r3, #0]
800b6a8: 4a5f ldr r2, [pc, #380] @ (800b828 <HAL_RTCEx_SetWakeUpTimer_IT+0x190>)
800b6aa: fba2 2303 umull r2, r3, r2, r3
800b6ae: 0adb lsrs r3, r3, #11
800b6b0: f44f 727a mov.w r2, #1000 @ 0x3e8
800b6b4: fb02 f303 mul.w r3, r2, r3
800b6b8: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
800b6ba: 68fb ldr r3, [r7, #12]
800b6bc: f893 3020 ldrb.w r3, [r3, #32]
800b6c0: 2b01 cmp r3, #1
800b6c2: d101 bne.n 800b6c8 <HAL_RTCEx_SetWakeUpTimer_IT+0x30>
800b6c4: 2302 movs r3, #2
800b6c6: e0a7 b.n 800b818 <HAL_RTCEx_SetWakeUpTimer_IT+0x180>
800b6c8: 68fb ldr r3, [r7, #12]
800b6ca: 2201 movs r2, #1
800b6cc: f883 2020 strb.w r2, [r3, #32]
hrtc->State = HAL_RTC_STATE_BUSY;
800b6d0: 68fb ldr r3, [r7, #12]
800b6d2: 2202 movs r2, #2
800b6d4: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
800b6d8: 68fb ldr r3, [r7, #12]
800b6da: 681b ldr r3, [r3, #0]
800b6dc: 22ca movs r2, #202 @ 0xca
800b6de: 625a str r2, [r3, #36] @ 0x24
800b6e0: 68fb ldr r3, [r7, #12]
800b6e2: 681b ldr r3, [r3, #0]
800b6e4: 2253 movs r2, #83 @ 0x53
800b6e6: 625a str r2, [r3, #36] @ 0x24
/* Check RTC WUTWF flag is reset only when wakeup timer enabled */
if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
800b6e8: 68fb ldr r3, [r7, #12]
800b6ea: 681b ldr r3, [r3, #0]
800b6ec: 689b ldr r3, [r3, #8]
800b6ee: f403 6380 and.w r3, r3, #1024 @ 0x400
800b6f2: 2b00 cmp r3, #0
800b6f4: d01a beq.n 800b72c <HAL_RTCEx_SetWakeUpTimer_IT+0x94>
{
/* Wait till RTC WUTWF flag is reset and if timeout is reached exit */
do
{
count = count - 1U;
800b6f6: 697b ldr r3, [r7, #20]
800b6f8: 3b01 subs r3, #1
800b6fa: 617b str r3, [r7, #20]
if (count == 0U)
800b6fc: 697b ldr r3, [r7, #20]
800b6fe: 2b00 cmp r3, #0
800b700: d10d bne.n 800b71e <HAL_RTCEx_SetWakeUpTimer_IT+0x86>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
800b702: 68fb ldr r3, [r7, #12]
800b704: 681b ldr r3, [r3, #0]
800b706: 22ff movs r2, #255 @ 0xff
800b708: 625a str r2, [r3, #36] @ 0x24
hrtc->State = HAL_RTC_STATE_TIMEOUT;
800b70a: 68fb ldr r3, [r7, #12]
800b70c: 2203 movs r2, #3
800b70e: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
800b712: 68fb ldr r3, [r7, #12]
800b714: 2200 movs r2, #0
800b716: f883 2020 strb.w r2, [r3, #32]
return HAL_TIMEOUT;
800b71a: 2303 movs r3, #3
800b71c: e07c b.n 800b818 <HAL_RTCEx_SetWakeUpTimer_IT+0x180>
}
} while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U);
800b71e: 68fb ldr r3, [r7, #12]
800b720: 681b ldr r3, [r3, #0]
800b722: 68db ldr r3, [r3, #12]
800b724: f003 0304 and.w r3, r3, #4
800b728: 2b00 cmp r3, #0
800b72a: d1e4 bne.n 800b6f6 <HAL_RTCEx_SetWakeUpTimer_IT+0x5e>
}
/* Disable the Wakeup timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
800b72c: 68fb ldr r3, [r7, #12]
800b72e: 681b ldr r3, [r3, #0]
800b730: 689a ldr r2, [r3, #8]
800b732: 68fb ldr r3, [r7, #12]
800b734: 681b ldr r3, [r3, #0]
800b736: f422 6280 bic.w r2, r2, #1024 @ 0x400
800b73a: 609a str r2, [r3, #8]
/* Clear the Wakeup flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
800b73c: 68fb ldr r3, [r7, #12]
800b73e: 681b ldr r3, [r3, #0]
800b740: 68db ldr r3, [r3, #12]
800b742: b2da uxtb r2, r3
800b744: 68fb ldr r3, [r7, #12]
800b746: 681b ldr r3, [r3, #0]
800b748: f462 6290 orn r2, r2, #1152 @ 0x480
800b74c: 60da str r2, [r3, #12]
/* Reload the counter */
count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
800b74e: 4b35 ldr r3, [pc, #212] @ (800b824 <HAL_RTCEx_SetWakeUpTimer_IT+0x18c>)
800b750: 681b ldr r3, [r3, #0]
800b752: 4a35 ldr r2, [pc, #212] @ (800b828 <HAL_RTCEx_SetWakeUpTimer_IT+0x190>)
800b754: fba2 2303 umull r2, r3, r2, r3
800b758: 0adb lsrs r3, r3, #11
800b75a: f44f 727a mov.w r2, #1000 @ 0x3e8
800b75e: fb02 f303 mul.w r3, r2, r3
800b762: 617b str r3, [r7, #20]
/* Wait till RTC WUTWF flag is set and if timeout is reached exit */
do
{
count = count - 1U;
800b764: 697b ldr r3, [r7, #20]
800b766: 3b01 subs r3, #1
800b768: 617b str r3, [r7, #20]
if (count == 0U)
800b76a: 697b ldr r3, [r7, #20]
800b76c: 2b00 cmp r3, #0
800b76e: d10d bne.n 800b78c <HAL_RTCEx_SetWakeUpTimer_IT+0xf4>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
800b770: 68fb ldr r3, [r7, #12]
800b772: 681b ldr r3, [r3, #0]
800b774: 22ff movs r2, #255 @ 0xff
800b776: 625a str r2, [r3, #36] @ 0x24
hrtc->State = HAL_RTC_STATE_TIMEOUT;
800b778: 68fb ldr r3, [r7, #12]
800b77a: 2203 movs r2, #3
800b77c: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
800b780: 68fb ldr r3, [r7, #12]
800b782: 2200 movs r2, #0
800b784: f883 2020 strb.w r2, [r3, #32]
return HAL_TIMEOUT;
800b788: 2303 movs r3, #3
800b78a: e045 b.n 800b818 <HAL_RTCEx_SetWakeUpTimer_IT+0x180>
}
} while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U);
800b78c: 68fb ldr r3, [r7, #12]
800b78e: 681b ldr r3, [r3, #0]
800b790: 68db ldr r3, [r3, #12]
800b792: f003 0304 and.w r3, r3, #4
800b796: 2b00 cmp r3, #0
800b798: d0e4 beq.n 800b764 <HAL_RTCEx_SetWakeUpTimer_IT+0xcc>
/* Clear the Wakeup Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
800b79a: 68fb ldr r3, [r7, #12]
800b79c: 681b ldr r3, [r3, #0]
800b79e: 689a ldr r2, [r3, #8]
800b7a0: 68fb ldr r3, [r7, #12]
800b7a2: 681b ldr r3, [r3, #0]
800b7a4: f022 0207 bic.w r2, r2, #7
800b7a8: 609a str r2, [r3, #8]
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
800b7aa: 68fb ldr r3, [r7, #12]
800b7ac: 681b ldr r3, [r3, #0]
800b7ae: 6899 ldr r1, [r3, #8]
800b7b0: 68fb ldr r3, [r7, #12]
800b7b2: 681b ldr r3, [r3, #0]
800b7b4: 687a ldr r2, [r7, #4]
800b7b6: 430a orrs r2, r1
800b7b8: 609a str r2, [r3, #8]
/* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
800b7ba: 68fb ldr r3, [r7, #12]
800b7bc: 681b ldr r3, [r3, #0]
800b7be: 68ba ldr r2, [r7, #8]
800b7c0: 615a str r2, [r3, #20]
/* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
800b7c2: 4b1a ldr r3, [pc, #104] @ (800b82c <HAL_RTCEx_SetWakeUpTimer_IT+0x194>)
800b7c4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800b7c8: 4a18 ldr r2, [pc, #96] @ (800b82c <HAL_RTCEx_SetWakeUpTimer_IT+0x194>)
800b7ca: f443 2300 orr.w r3, r3, #524288 @ 0x80000
800b7ce: f8c2 3080 str.w r3, [r2, #128] @ 0x80
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
800b7d2: 4b16 ldr r3, [pc, #88] @ (800b82c <HAL_RTCEx_SetWakeUpTimer_IT+0x194>)
800b7d4: 681b ldr r3, [r3, #0]
800b7d6: 4a15 ldr r2, [pc, #84] @ (800b82c <HAL_RTCEx_SetWakeUpTimer_IT+0x194>)
800b7d8: f443 2300 orr.w r3, r3, #524288 @ 0x80000
800b7dc: 6013 str r3, [r2, #0]
/* Configure the interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
800b7de: 68fb ldr r3, [r7, #12]
800b7e0: 681b ldr r3, [r3, #0]
800b7e2: 689a ldr r2, [r3, #8]
800b7e4: 68fb ldr r3, [r7, #12]
800b7e6: 681b ldr r3, [r3, #0]
800b7e8: f442 4280 orr.w r2, r2, #16384 @ 0x4000
800b7ec: 609a str r2, [r3, #8]
/* Enable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
800b7ee: 68fb ldr r3, [r7, #12]
800b7f0: 681b ldr r3, [r3, #0]
800b7f2: 689a ldr r2, [r3, #8]
800b7f4: 68fb ldr r3, [r7, #12]
800b7f6: 681b ldr r3, [r3, #0]
800b7f8: f442 6280 orr.w r2, r2, #1024 @ 0x400
800b7fc: 609a str r2, [r3, #8]
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
800b7fe: 68fb ldr r3, [r7, #12]
800b800: 681b ldr r3, [r3, #0]
800b802: 22ff movs r2, #255 @ 0xff
800b804: 625a str r2, [r3, #36] @ 0x24
hrtc->State = HAL_RTC_STATE_READY;
800b806: 68fb ldr r3, [r7, #12]
800b808: 2201 movs r2, #1
800b80a: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
800b80e: 68fb ldr r3, [r7, #12]
800b810: 2200 movs r2, #0
800b812: f883 2020 strb.w r2, [r3, #32]
return HAL_OK;
800b816: 2300 movs r3, #0
}
800b818: 4618 mov r0, r3
800b81a: 371c adds r7, #28
800b81c: 46bd mov sp, r7
800b81e: f85d 7b04 ldr.w r7, [sp], #4
800b822: 4770 bx lr
800b824: 2000000c .word 0x2000000c
800b828: 10624dd3 .word 0x10624dd3
800b82c: 58000800 .word 0x58000800
0800b830 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
800b830: b580 push {r7, lr}
800b832: b084 sub sp, #16
800b834: af00 add r7, sp, #0
800b836: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
800b838: 687b ldr r3, [r7, #4]
800b83a: 2b00 cmp r3, #0
800b83c: d101 bne.n 800b842 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
800b83e: 2301 movs r3, #1
800b840: e095 b.n 800b96e <HAL_SPI_Init+0x13e>
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
800b842: 687b ldr r3, [r7, #4]
800b844: 6a5b ldr r3, [r3, #36] @ 0x24
800b846: 2b00 cmp r3, #0
800b848: d108 bne.n 800b85c <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
800b84a: 687b ldr r3, [r7, #4]
800b84c: 685b ldr r3, [r3, #4]
800b84e: f5b3 7f82 cmp.w r3, #260 @ 0x104
800b852: d009 beq.n 800b868 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
800b854: 687b ldr r3, [r7, #4]
800b856: 2200 movs r2, #0
800b858: 61da str r2, [r3, #28]
800b85a: e005 b.n 800b868 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
800b85c: 687b ldr r3, [r7, #4]
800b85e: 2200 movs r2, #0
800b860: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
800b862: 687b ldr r3, [r7, #4]
800b864: 2200 movs r2, #0
800b866: 615a str r2, [r3, #20]
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
800b868: 687b ldr r3, [r7, #4]
800b86a: 2200 movs r2, #0
800b86c: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
800b86e: 687b ldr r3, [r7, #4]
800b870: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
800b874: b2db uxtb r3, r3
800b876: 2b00 cmp r3, #0
800b878: d106 bne.n 800b888 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
800b87a: 687b ldr r3, [r7, #4]
800b87c: 2200 movs r2, #0
800b87e: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
800b882: 6878 ldr r0, [r7, #4]
800b884: f7f9 f9ee bl 8004c64 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
800b888: 687b ldr r3, [r7, #4]
800b88a: 2202 movs r2, #2
800b88c: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
800b890: 687b ldr r3, [r7, #4]
800b892: 681b ldr r3, [r3, #0]
800b894: 681a ldr r2, [r3, #0]
800b896: 687b ldr r3, [r7, #4]
800b898: 681b ldr r3, [r3, #0]
800b89a: f022 0240 bic.w r2, r2, #64 @ 0x40
800b89e: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
800b8a0: 687b ldr r3, [r7, #4]
800b8a2: 68db ldr r3, [r3, #12]
800b8a4: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
800b8a8: d902 bls.n 800b8b0 <HAL_SPI_Init+0x80>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
800b8aa: 2300 movs r3, #0
800b8ac: 60fb str r3, [r7, #12]
800b8ae: e002 b.n 800b8b6 <HAL_SPI_Init+0x86>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
800b8b0: f44f 5380 mov.w r3, #4096 @ 0x1000
800b8b4: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
800b8b6: 687b ldr r3, [r7, #4]
800b8b8: 68db ldr r3, [r3, #12]
800b8ba: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
800b8be: d007 beq.n 800b8d0 <HAL_SPI_Init+0xa0>
800b8c0: 687b ldr r3, [r7, #4]
800b8c2: 68db ldr r3, [r3, #12]
800b8c4: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
800b8c8: d002 beq.n 800b8d0 <HAL_SPI_Init+0xa0>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
800b8ca: 687b ldr r3, [r7, #4]
800b8cc: 2200 movs r2, #0
800b8ce: 629a str r2, [r3, #40] @ 0x28
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
800b8d0: 687b ldr r3, [r7, #4]
800b8d2: 685b ldr r3, [r3, #4]
800b8d4: f403 7282 and.w r2, r3, #260 @ 0x104
800b8d8: 687b ldr r3, [r7, #4]
800b8da: 689b ldr r3, [r3, #8]
800b8dc: f403 4304 and.w r3, r3, #33792 @ 0x8400
800b8e0: 431a orrs r2, r3
800b8e2: 687b ldr r3, [r7, #4]
800b8e4: 691b ldr r3, [r3, #16]
800b8e6: f003 0302 and.w r3, r3, #2
800b8ea: 431a orrs r2, r3
800b8ec: 687b ldr r3, [r7, #4]
800b8ee: 695b ldr r3, [r3, #20]
800b8f0: f003 0301 and.w r3, r3, #1
800b8f4: 431a orrs r2, r3
800b8f6: 687b ldr r3, [r7, #4]
800b8f8: 699b ldr r3, [r3, #24]
800b8fa: f403 7300 and.w r3, r3, #512 @ 0x200
800b8fe: 431a orrs r2, r3
800b900: 687b ldr r3, [r7, #4]
800b902: 69db ldr r3, [r3, #28]
800b904: f003 0338 and.w r3, r3, #56 @ 0x38
800b908: 431a orrs r2, r3
800b90a: 687b ldr r3, [r7, #4]
800b90c: 6a1b ldr r3, [r3, #32]
800b90e: f003 0380 and.w r3, r3, #128 @ 0x80
800b912: ea42 0103 orr.w r1, r2, r3
800b916: 687b ldr r3, [r7, #4]
800b918: 6a9b ldr r3, [r3, #40] @ 0x28
800b91a: f403 5200 and.w r2, r3, #8192 @ 0x2000
800b91e: 687b ldr r3, [r7, #4]
800b920: 681b ldr r3, [r3, #0]
800b922: 430a orrs r2, r1
800b924: 601a str r2, [r3, #0]
}
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
800b926: 687b ldr r3, [r7, #4]
800b928: 699b ldr r3, [r3, #24]
800b92a: 0c1b lsrs r3, r3, #16
800b92c: f003 0204 and.w r2, r3, #4
800b930: 687b ldr r3, [r7, #4]
800b932: 6a5b ldr r3, [r3, #36] @ 0x24
800b934: f003 0310 and.w r3, r3, #16
800b938: 431a orrs r2, r3
800b93a: 687b ldr r3, [r7, #4]
800b93c: 6b5b ldr r3, [r3, #52] @ 0x34
800b93e: f003 0308 and.w r3, r3, #8
800b942: 431a orrs r2, r3
800b944: 687b ldr r3, [r7, #4]
800b946: 68db ldr r3, [r3, #12]
800b948: f403 6370 and.w r3, r3, #3840 @ 0xf00
800b94c: ea42 0103 orr.w r1, r2, r3
800b950: 68fb ldr r3, [r7, #12]
800b952: f403 5280 and.w r2, r3, #4096 @ 0x1000
800b956: 687b ldr r3, [r7, #4]
800b958: 681b ldr r3, [r3, #0]
800b95a: 430a orrs r2, r1
800b95c: 605a str r2, [r3, #4]
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800b95e: 687b ldr r3, [r7, #4]
800b960: 2200 movs r2, #0
800b962: 661a str r2, [r3, #96] @ 0x60
hspi->State = HAL_SPI_STATE_READY;
800b964: 687b ldr r3, [r7, #4]
800b966: 2201 movs r2, #1
800b968: f883 205d strb.w r2, [r3, #93] @ 0x5d
return HAL_OK;
800b96c: 2300 movs r3, #0
}
800b96e: 4618 mov r0, r3
800b970: 3710 adds r7, #16
800b972: 46bd mov sp, r7
800b974: bd80 pop {r7, pc}
0800b976 <HAL_SPI_Transmit>:
* @param Size amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration in ms
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800b976: b580 push {r7, lr}
800b978: b088 sub sp, #32
800b97a: af00 add r7, sp, #0
800b97c: 60f8 str r0, [r7, #12]
800b97e: 60b9 str r1, [r7, #8]
800b980: 603b str r3, [r7, #0]
800b982: 4613 mov r3, r2
800b984: 80fb strh r3, [r7, #6]
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800b986: f7f9 fced bl 8005364 <HAL_GetTick>
800b98a: 61f8 str r0, [r7, #28]
initial_TxXferCount = Size;
800b98c: 88fb ldrh r3, [r7, #6]
800b98e: 837b strh r3, [r7, #26]
if (hspi->State != HAL_SPI_STATE_READY)
800b990: 68fb ldr r3, [r7, #12]
800b992: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
800b996: b2db uxtb r3, r3
800b998: 2b01 cmp r3, #1
800b99a: d001 beq.n 800b9a0 <HAL_SPI_Transmit+0x2a>
{
return HAL_BUSY;
800b99c: 2302 movs r3, #2
800b99e: e15c b.n 800bc5a <HAL_SPI_Transmit+0x2e4>
}
if ((pData == NULL) || (Size == 0U))
800b9a0: 68bb ldr r3, [r7, #8]
800b9a2: 2b00 cmp r3, #0
800b9a4: d002 beq.n 800b9ac <HAL_SPI_Transmit+0x36>
800b9a6: 88fb ldrh r3, [r7, #6]
800b9a8: 2b00 cmp r3, #0
800b9aa: d101 bne.n 800b9b0 <HAL_SPI_Transmit+0x3a>
{
return HAL_ERROR;
800b9ac: 2301 movs r3, #1
800b9ae: e154 b.n 800bc5a <HAL_SPI_Transmit+0x2e4>
}
/* Process Locked */
__HAL_LOCK(hspi);
800b9b0: 68fb ldr r3, [r7, #12]
800b9b2: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
800b9b6: 2b01 cmp r3, #1
800b9b8: d101 bne.n 800b9be <HAL_SPI_Transmit+0x48>
800b9ba: 2302 movs r3, #2
800b9bc: e14d b.n 800bc5a <HAL_SPI_Transmit+0x2e4>
800b9be: 68fb ldr r3, [r7, #12]
800b9c0: 2201 movs r2, #1
800b9c2: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
800b9c6: 68fb ldr r3, [r7, #12]
800b9c8: 2203 movs r2, #3
800b9ca: f883 205d strb.w r2, [r3, #93] @ 0x5d
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800b9ce: 68fb ldr r3, [r7, #12]
800b9d0: 2200 movs r2, #0
800b9d2: 661a str r2, [r3, #96] @ 0x60
hspi->pTxBuffPtr = (const uint8_t *)pData;
800b9d4: 68fb ldr r3, [r7, #12]
800b9d6: 68ba ldr r2, [r7, #8]
800b9d8: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferSize = Size;
800b9da: 68fb ldr r3, [r7, #12]
800b9dc: 88fa ldrh r2, [r7, #6]
800b9de: 879a strh r2, [r3, #60] @ 0x3c
hspi->TxXferCount = Size;
800b9e0: 68fb ldr r3, [r7, #12]
800b9e2: 88fa ldrh r2, [r7, #6]
800b9e4: 87da strh r2, [r3, #62] @ 0x3e
/*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
800b9e6: 68fb ldr r3, [r7, #12]
800b9e8: 2200 movs r2, #0
800b9ea: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferSize = 0U;
800b9ec: 68fb ldr r3, [r7, #12]
800b9ee: 2200 movs r2, #0
800b9f0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hspi->RxXferCount = 0U;
800b9f4: 68fb ldr r3, [r7, #12]
800b9f6: 2200 movs r2, #0
800b9f8: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
hspi->TxISR = NULL;
800b9fc: 68fb ldr r3, [r7, #12]
800b9fe: 2200 movs r2, #0
800ba00: 651a str r2, [r3, #80] @ 0x50
hspi->RxISR = NULL;
800ba02: 68fb ldr r3, [r7, #12]
800ba04: 2200 movs r2, #0
800ba06: 64da str r2, [r3, #76] @ 0x4c
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
800ba08: 68fb ldr r3, [r7, #12]
800ba0a: 689b ldr r3, [r3, #8]
800ba0c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800ba10: d10f bne.n 800ba32 <HAL_SPI_Transmit+0xbc>
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
800ba12: 68fb ldr r3, [r7, #12]
800ba14: 681b ldr r3, [r3, #0]
800ba16: 681a ldr r2, [r3, #0]
800ba18: 68fb ldr r3, [r7, #12]
800ba1a: 681b ldr r3, [r3, #0]
800ba1c: f022 0240 bic.w r2, r2, #64 @ 0x40
800ba20: 601a str r2, [r3, #0]
SPI_1LINE_TX(hspi);
800ba22: 68fb ldr r3, [r7, #12]
800ba24: 681b ldr r3, [r3, #0]
800ba26: 681a ldr r2, [r3, #0]
800ba28: 68fb ldr r3, [r7, #12]
800ba2a: 681b ldr r3, [r3, #0]
800ba2c: f442 4280 orr.w r2, r2, #16384 @ 0x4000
800ba30: 601a str r2, [r3, #0]
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
800ba32: 68fb ldr r3, [r7, #12]
800ba34: 681b ldr r3, [r3, #0]
800ba36: 681b ldr r3, [r3, #0]
800ba38: f003 0340 and.w r3, r3, #64 @ 0x40
800ba3c: 2b40 cmp r3, #64 @ 0x40
800ba3e: d007 beq.n 800ba50 <HAL_SPI_Transmit+0xda>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
800ba40: 68fb ldr r3, [r7, #12]
800ba42: 681b ldr r3, [r3, #0]
800ba44: 681a ldr r2, [r3, #0]
800ba46: 68fb ldr r3, [r7, #12]
800ba48: 681b ldr r3, [r3, #0]
800ba4a: f042 0240 orr.w r2, r2, #64 @ 0x40
800ba4e: 601a str r2, [r3, #0]
}
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
800ba50: 68fb ldr r3, [r7, #12]
800ba52: 68db ldr r3, [r3, #12]
800ba54: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
800ba58: d952 bls.n 800bb00 <HAL_SPI_Transmit+0x18a>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
800ba5a: 68fb ldr r3, [r7, #12]
800ba5c: 685b ldr r3, [r3, #4]
800ba5e: 2b00 cmp r3, #0
800ba60: d002 beq.n 800ba68 <HAL_SPI_Transmit+0xf2>
800ba62: 8b7b ldrh r3, [r7, #26]
800ba64: 2b01 cmp r3, #1
800ba66: d145 bne.n 800baf4 <HAL_SPI_Transmit+0x17e>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800ba68: 68fb ldr r3, [r7, #12]
800ba6a: 6b9b ldr r3, [r3, #56] @ 0x38
800ba6c: 881a ldrh r2, [r3, #0]
800ba6e: 68fb ldr r3, [r7, #12]
800ba70: 681b ldr r3, [r3, #0]
800ba72: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800ba74: 68fb ldr r3, [r7, #12]
800ba76: 6b9b ldr r3, [r3, #56] @ 0x38
800ba78: 1c9a adds r2, r3, #2
800ba7a: 68fb ldr r3, [r7, #12]
800ba7c: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800ba7e: 68fb ldr r3, [r7, #12]
800ba80: 8fdb ldrh r3, [r3, #62] @ 0x3e
800ba82: b29b uxth r3, r3
800ba84: 3b01 subs r3, #1
800ba86: b29a uxth r2, r3
800ba88: 68fb ldr r3, [r7, #12]
800ba8a: 87da strh r2, [r3, #62] @ 0x3e
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
800ba8c: e032 b.n 800baf4 <HAL_SPI_Transmit+0x17e>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
800ba8e: 68fb ldr r3, [r7, #12]
800ba90: 681b ldr r3, [r3, #0]
800ba92: 689b ldr r3, [r3, #8]
800ba94: f003 0302 and.w r3, r3, #2
800ba98: 2b02 cmp r3, #2
800ba9a: d112 bne.n 800bac2 <HAL_SPI_Transmit+0x14c>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800ba9c: 68fb ldr r3, [r7, #12]
800ba9e: 6b9b ldr r3, [r3, #56] @ 0x38
800baa0: 881a ldrh r2, [r3, #0]
800baa2: 68fb ldr r3, [r7, #12]
800baa4: 681b ldr r3, [r3, #0]
800baa6: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800baa8: 68fb ldr r3, [r7, #12]
800baaa: 6b9b ldr r3, [r3, #56] @ 0x38
800baac: 1c9a adds r2, r3, #2
800baae: 68fb ldr r3, [r7, #12]
800bab0: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800bab2: 68fb ldr r3, [r7, #12]
800bab4: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bab6: b29b uxth r3, r3
800bab8: 3b01 subs r3, #1
800baba: b29a uxth r2, r3
800babc: 68fb ldr r3, [r7, #12]
800babe: 87da strh r2, [r3, #62] @ 0x3e
800bac0: e018 b.n 800baf4 <HAL_SPI_Transmit+0x17e>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
800bac2: f7f9 fc4f bl 8005364 <HAL_GetTick>
800bac6: 4602 mov r2, r0
800bac8: 69fb ldr r3, [r7, #28]
800baca: 1ad3 subs r3, r2, r3
800bacc: 683a ldr r2, [r7, #0]
800bace: 429a cmp r2, r3
800bad0: d803 bhi.n 800bada <HAL_SPI_Transmit+0x164>
800bad2: 683b ldr r3, [r7, #0]
800bad4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800bad8: d102 bne.n 800bae0 <HAL_SPI_Transmit+0x16a>
800bada: 683b ldr r3, [r7, #0]
800badc: 2b00 cmp r3, #0
800bade: d109 bne.n 800baf4 <HAL_SPI_Transmit+0x17e>
{
hspi->State = HAL_SPI_STATE_READY;
800bae0: 68fb ldr r3, [r7, #12]
800bae2: 2201 movs r2, #1
800bae4: f883 205d strb.w r2, [r3, #93] @ 0x5d
__HAL_UNLOCK(hspi);
800bae8: 68fb ldr r3, [r7, #12]
800baea: 2200 movs r2, #0
800baec: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
800baf0: 2303 movs r3, #3
800baf2: e0b2 b.n 800bc5a <HAL_SPI_Transmit+0x2e4>
while (hspi->TxXferCount > 0U)
800baf4: 68fb ldr r3, [r7, #12]
800baf6: 8fdb ldrh r3, [r3, #62] @ 0x3e
800baf8: b29b uxth r3, r3
800bafa: 2b00 cmp r3, #0
800bafc: d1c7 bne.n 800ba8e <HAL_SPI_Transmit+0x118>
800bafe: e083 b.n 800bc08 <HAL_SPI_Transmit+0x292>
}
}
/* Transmit data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
800bb00: 68fb ldr r3, [r7, #12]
800bb02: 685b ldr r3, [r3, #4]
800bb04: 2b00 cmp r3, #0
800bb06: d002 beq.n 800bb0e <HAL_SPI_Transmit+0x198>
800bb08: 8b7b ldrh r3, [r7, #26]
800bb0a: 2b01 cmp r3, #1
800bb0c: d177 bne.n 800bbfe <HAL_SPI_Transmit+0x288>
{
if (hspi->TxXferCount > 1U)
800bb0e: 68fb ldr r3, [r7, #12]
800bb10: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bb12: b29b uxth r3, r3
800bb14: 2b01 cmp r3, #1
800bb16: d912 bls.n 800bb3e <HAL_SPI_Transmit+0x1c8>
{
/* write on the data register in packing mode */
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800bb18: 68fb ldr r3, [r7, #12]
800bb1a: 6b9b ldr r3, [r3, #56] @ 0x38
800bb1c: 881a ldrh r2, [r3, #0]
800bb1e: 68fb ldr r3, [r7, #12]
800bb20: 681b ldr r3, [r3, #0]
800bb22: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800bb24: 68fb ldr r3, [r7, #12]
800bb26: 6b9b ldr r3, [r3, #56] @ 0x38
800bb28: 1c9a adds r2, r3, #2
800bb2a: 68fb ldr r3, [r7, #12]
800bb2c: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount -= 2U;
800bb2e: 68fb ldr r3, [r7, #12]
800bb30: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bb32: b29b uxth r3, r3
800bb34: 3b02 subs r3, #2
800bb36: b29a uxth r2, r3
800bb38: 68fb ldr r3, [r7, #12]
800bb3a: 87da strh r2, [r3, #62] @ 0x3e
800bb3c: e05f b.n 800bbfe <HAL_SPI_Transmit+0x288>
}
else
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
800bb3e: 68fb ldr r3, [r7, #12]
800bb40: 6b9a ldr r2, [r3, #56] @ 0x38
800bb42: 68fb ldr r3, [r7, #12]
800bb44: 681b ldr r3, [r3, #0]
800bb46: 330c adds r3, #12
800bb48: 7812 ldrb r2, [r2, #0]
800bb4a: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr ++;
800bb4c: 68fb ldr r3, [r7, #12]
800bb4e: 6b9b ldr r3, [r3, #56] @ 0x38
800bb50: 1c5a adds r2, r3, #1
800bb52: 68fb ldr r3, [r7, #12]
800bb54: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800bb56: 68fb ldr r3, [r7, #12]
800bb58: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bb5a: b29b uxth r3, r3
800bb5c: 3b01 subs r3, #1
800bb5e: b29a uxth r2, r3
800bb60: 68fb ldr r3, [r7, #12]
800bb62: 87da strh r2, [r3, #62] @ 0x3e
}
}
while (hspi->TxXferCount > 0U)
800bb64: e04b b.n 800bbfe <HAL_SPI_Transmit+0x288>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
800bb66: 68fb ldr r3, [r7, #12]
800bb68: 681b ldr r3, [r3, #0]
800bb6a: 689b ldr r3, [r3, #8]
800bb6c: f003 0302 and.w r3, r3, #2
800bb70: 2b02 cmp r3, #2
800bb72: d12b bne.n 800bbcc <HAL_SPI_Transmit+0x256>
{
if (hspi->TxXferCount > 1U)
800bb74: 68fb ldr r3, [r7, #12]
800bb76: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bb78: b29b uxth r3, r3
800bb7a: 2b01 cmp r3, #1
800bb7c: d912 bls.n 800bba4 <HAL_SPI_Transmit+0x22e>
{
/* write on the data register in packing mode */
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800bb7e: 68fb ldr r3, [r7, #12]
800bb80: 6b9b ldr r3, [r3, #56] @ 0x38
800bb82: 881a ldrh r2, [r3, #0]
800bb84: 68fb ldr r3, [r7, #12]
800bb86: 681b ldr r3, [r3, #0]
800bb88: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800bb8a: 68fb ldr r3, [r7, #12]
800bb8c: 6b9b ldr r3, [r3, #56] @ 0x38
800bb8e: 1c9a adds r2, r3, #2
800bb90: 68fb ldr r3, [r7, #12]
800bb92: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount -= 2U;
800bb94: 68fb ldr r3, [r7, #12]
800bb96: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bb98: b29b uxth r3, r3
800bb9a: 3b02 subs r3, #2
800bb9c: b29a uxth r2, r3
800bb9e: 68fb ldr r3, [r7, #12]
800bba0: 87da strh r2, [r3, #62] @ 0x3e
800bba2: e02c b.n 800bbfe <HAL_SPI_Transmit+0x288>
}
else
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
800bba4: 68fb ldr r3, [r7, #12]
800bba6: 6b9a ldr r2, [r3, #56] @ 0x38
800bba8: 68fb ldr r3, [r7, #12]
800bbaa: 681b ldr r3, [r3, #0]
800bbac: 330c adds r3, #12
800bbae: 7812 ldrb r2, [r2, #0]
800bbb0: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
800bbb2: 68fb ldr r3, [r7, #12]
800bbb4: 6b9b ldr r3, [r3, #56] @ 0x38
800bbb6: 1c5a adds r2, r3, #1
800bbb8: 68fb ldr r3, [r7, #12]
800bbba: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800bbbc: 68fb ldr r3, [r7, #12]
800bbbe: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bbc0: b29b uxth r3, r3
800bbc2: 3b01 subs r3, #1
800bbc4: b29a uxth r2, r3
800bbc6: 68fb ldr r3, [r7, #12]
800bbc8: 87da strh r2, [r3, #62] @ 0x3e
800bbca: e018 b.n 800bbfe <HAL_SPI_Transmit+0x288>
}
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
800bbcc: f7f9 fbca bl 8005364 <HAL_GetTick>
800bbd0: 4602 mov r2, r0
800bbd2: 69fb ldr r3, [r7, #28]
800bbd4: 1ad3 subs r3, r2, r3
800bbd6: 683a ldr r2, [r7, #0]
800bbd8: 429a cmp r2, r3
800bbda: d803 bhi.n 800bbe4 <HAL_SPI_Transmit+0x26e>
800bbdc: 683b ldr r3, [r7, #0]
800bbde: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800bbe2: d102 bne.n 800bbea <HAL_SPI_Transmit+0x274>
800bbe4: 683b ldr r3, [r7, #0]
800bbe6: 2b00 cmp r3, #0
800bbe8: d109 bne.n 800bbfe <HAL_SPI_Transmit+0x288>
{
hspi->State = HAL_SPI_STATE_READY;
800bbea: 68fb ldr r3, [r7, #12]
800bbec: 2201 movs r2, #1
800bbee: f883 205d strb.w r2, [r3, #93] @ 0x5d
__HAL_UNLOCK(hspi);
800bbf2: 68fb ldr r3, [r7, #12]
800bbf4: 2200 movs r2, #0
800bbf6: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
800bbfa: 2303 movs r3, #3
800bbfc: e02d b.n 800bc5a <HAL_SPI_Transmit+0x2e4>
while (hspi->TxXferCount > 0U)
800bbfe: 68fb ldr r3, [r7, #12]
800bc00: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bc02: b29b uxth r3, r3
800bc04: 2b00 cmp r3, #0
800bc06: d1ae bne.n 800bb66 <HAL_SPI_Transmit+0x1f0>
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
800bc08: 69fa ldr r2, [r7, #28]
800bc0a: 6839 ldr r1, [r7, #0]
800bc0c: 68f8 ldr r0, [r7, #12]
800bc0e: f000 fe43 bl 800c898 <SPI_EndRxTxTransaction>
800bc12: 4603 mov r3, r0
800bc14: 2b00 cmp r3, #0
800bc16: d002 beq.n 800bc1e <HAL_SPI_Transmit+0x2a8>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
800bc18: 68fb ldr r3, [r7, #12]
800bc1a: 2220 movs r2, #32
800bc1c: 661a str r2, [r3, #96] @ 0x60
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
800bc1e: 68fb ldr r3, [r7, #12]
800bc20: 689b ldr r3, [r3, #8]
800bc22: 2b00 cmp r3, #0
800bc24: d10a bne.n 800bc3c <HAL_SPI_Transmit+0x2c6>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
800bc26: 2300 movs r3, #0
800bc28: 617b str r3, [r7, #20]
800bc2a: 68fb ldr r3, [r7, #12]
800bc2c: 681b ldr r3, [r3, #0]
800bc2e: 68db ldr r3, [r3, #12]
800bc30: 617b str r3, [r7, #20]
800bc32: 68fb ldr r3, [r7, #12]
800bc34: 681b ldr r3, [r3, #0]
800bc36: 689b ldr r3, [r3, #8]
800bc38: 617b str r3, [r7, #20]
800bc3a: 697b ldr r3, [r7, #20]
}
hspi->State = HAL_SPI_STATE_READY;
800bc3c: 68fb ldr r3, [r7, #12]
800bc3e: 2201 movs r2, #1
800bc40: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
800bc44: 68fb ldr r3, [r7, #12]
800bc46: 2200 movs r2, #0
800bc48: f883 205c strb.w r2, [r3, #92] @ 0x5c
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
800bc4c: 68fb ldr r3, [r7, #12]
800bc4e: 6e1b ldr r3, [r3, #96] @ 0x60
800bc50: 2b00 cmp r3, #0
800bc52: d001 beq.n 800bc58 <HAL_SPI_Transmit+0x2e2>
{
return HAL_ERROR;
800bc54: 2301 movs r3, #1
800bc56: e000 b.n 800bc5a <HAL_SPI_Transmit+0x2e4>
}
else
{
return HAL_OK;
800bc58: 2300 movs r3, #0
}
}
800bc5a: 4618 mov r0, r3
800bc5c: 3720 adds r7, #32
800bc5e: 46bd mov sp, r7
800bc60: bd80 pop {r7, pc}
0800bc62 <HAL_SPI_TransmitReceive>:
* @param Timeout Timeout duration in ms
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout)
{
800bc62: b580 push {r7, lr}
800bc64: b08a sub sp, #40 @ 0x28
800bc66: af00 add r7, sp, #0
800bc68: 60f8 str r0, [r7, #12]
800bc6a: 60b9 str r1, [r7, #8]
800bc6c: 607a str r2, [r7, #4]
800bc6e: 807b strh r3, [r7, #2]
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
800bc70: 2301 movs r3, #1
800bc72: 627b str r3, [r7, #36] @ 0x24
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800bc74: f7f9 fb76 bl 8005364 <HAL_GetTick>
800bc78: 6238 str r0, [r7, #32]
/* Init temporary variables */
tmp_state = hspi->State;
800bc7a: 68fb ldr r3, [r7, #12]
800bc7c: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
800bc80: 77fb strb r3, [r7, #31]
tmp_mode = hspi->Init.Mode;
800bc82: 68fb ldr r3, [r7, #12]
800bc84: 685b ldr r3, [r3, #4]
800bc86: 61bb str r3, [r7, #24]
initial_TxXferCount = Size;
800bc88: 887b ldrh r3, [r7, #2]
800bc8a: 82fb strh r3, [r7, #22]
initial_RxXferCount = Size;
800bc8c: 887b ldrh r3, [r7, #2]
800bc8e: 82bb strh r3, [r7, #20]
#if (USE_SPI_CRC != 0U)
spi_cr1 = READ_REG(hspi->Instance->CR1);
spi_cr2 = READ_REG(hspi->Instance->CR2);
#endif /* USE_SPI_CRC */
if (!((tmp_state == HAL_SPI_STATE_READY) || \
800bc90: 7ffb ldrb r3, [r7, #31]
800bc92: 2b01 cmp r3, #1
800bc94: d00c beq.n 800bcb0 <HAL_SPI_TransmitReceive+0x4e>
800bc96: 69bb ldr r3, [r7, #24]
800bc98: f5b3 7f82 cmp.w r3, #260 @ 0x104
800bc9c: d106 bne.n 800bcac <HAL_SPI_TransmitReceive+0x4a>
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
800bc9e: 68fb ldr r3, [r7, #12]
800bca0: 689b ldr r3, [r3, #8]
800bca2: 2b00 cmp r3, #0
800bca4: d102 bne.n 800bcac <HAL_SPI_TransmitReceive+0x4a>
800bca6: 7ffb ldrb r3, [r7, #31]
800bca8: 2b04 cmp r3, #4
800bcaa: d001 beq.n 800bcb0 <HAL_SPI_TransmitReceive+0x4e>
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
return HAL_BUSY;
800bcac: 2302 movs r3, #2
800bcae: e1f3 b.n 800c098 <HAL_SPI_TransmitReceive+0x436>
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
800bcb0: 68bb ldr r3, [r7, #8]
800bcb2: 2b00 cmp r3, #0
800bcb4: d005 beq.n 800bcc2 <HAL_SPI_TransmitReceive+0x60>
800bcb6: 687b ldr r3, [r7, #4]
800bcb8: 2b00 cmp r3, #0
800bcba: d002 beq.n 800bcc2 <HAL_SPI_TransmitReceive+0x60>
800bcbc: 887b ldrh r3, [r7, #2]
800bcbe: 2b00 cmp r3, #0
800bcc0: d101 bne.n 800bcc6 <HAL_SPI_TransmitReceive+0x64>
{
return HAL_ERROR;
800bcc2: 2301 movs r3, #1
800bcc4: e1e8 b.n 800c098 <HAL_SPI_TransmitReceive+0x436>
}
/* Process Locked */
__HAL_LOCK(hspi);
800bcc6: 68fb ldr r3, [r7, #12]
800bcc8: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
800bccc: 2b01 cmp r3, #1
800bcce: d101 bne.n 800bcd4 <HAL_SPI_TransmitReceive+0x72>
800bcd0: 2302 movs r3, #2
800bcd2: e1e1 b.n 800c098 <HAL_SPI_TransmitReceive+0x436>
800bcd4: 68fb ldr r3, [r7, #12]
800bcd6: 2201 movs r2, #1
800bcd8: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
800bcdc: 68fb ldr r3, [r7, #12]
800bcde: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
800bce2: b2db uxtb r3, r3
800bce4: 2b04 cmp r3, #4
800bce6: d003 beq.n 800bcf0 <HAL_SPI_TransmitReceive+0x8e>
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
800bce8: 68fb ldr r3, [r7, #12]
800bcea: 2205 movs r2, #5
800bcec: f883 205d strb.w r2, [r3, #93] @ 0x5d
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800bcf0: 68fb ldr r3, [r7, #12]
800bcf2: 2200 movs r2, #0
800bcf4: 661a str r2, [r3, #96] @ 0x60
hspi->pRxBuffPtr = (uint8_t *)pRxData;
800bcf6: 68fb ldr r3, [r7, #12]
800bcf8: 687a ldr r2, [r7, #4]
800bcfa: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferCount = Size;
800bcfc: 68fb ldr r3, [r7, #12]
800bcfe: 887a ldrh r2, [r7, #2]
800bd00: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
hspi->RxXferSize = Size;
800bd04: 68fb ldr r3, [r7, #12]
800bd06: 887a ldrh r2, [r7, #2]
800bd08: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
800bd0c: 68fb ldr r3, [r7, #12]
800bd0e: 68ba ldr r2, [r7, #8]
800bd10: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount = Size;
800bd12: 68fb ldr r3, [r7, #12]
800bd14: 887a ldrh r2, [r7, #2]
800bd16: 87da strh r2, [r3, #62] @ 0x3e
hspi->TxXferSize = Size;
800bd18: 68fb ldr r3, [r7, #12]
800bd1a: 887a ldrh r2, [r7, #2]
800bd1c: 879a strh r2, [r3, #60] @ 0x3c
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
800bd1e: 68fb ldr r3, [r7, #12]
800bd20: 2200 movs r2, #0
800bd22: 64da str r2, [r3, #76] @ 0x4c
hspi->TxISR = NULL;
800bd24: 68fb ldr r3, [r7, #12]
800bd26: 2200 movs r2, #0
800bd28: 651a str r2, [r3, #80] @ 0x50
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Set the Rx Fifo threshold */
if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
800bd2a: 68fb ldr r3, [r7, #12]
800bd2c: 68db ldr r3, [r3, #12]
800bd2e: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
800bd32: d802 bhi.n 800bd3a <HAL_SPI_TransmitReceive+0xd8>
800bd34: 8abb ldrh r3, [r7, #20]
800bd36: 2b01 cmp r3, #1
800bd38: d908 bls.n 800bd4c <HAL_SPI_TransmitReceive+0xea>
{
/* Set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
800bd3a: 68fb ldr r3, [r7, #12]
800bd3c: 681b ldr r3, [r3, #0]
800bd3e: 685a ldr r2, [r3, #4]
800bd40: 68fb ldr r3, [r7, #12]
800bd42: 681b ldr r3, [r3, #0]
800bd44: f422 5280 bic.w r2, r2, #4096 @ 0x1000
800bd48: 605a str r2, [r3, #4]
800bd4a: e007 b.n 800bd5c <HAL_SPI_TransmitReceive+0xfa>
}
else
{
/* Set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
800bd4c: 68fb ldr r3, [r7, #12]
800bd4e: 681b ldr r3, [r3, #0]
800bd50: 685a ldr r2, [r3, #4]
800bd52: 68fb ldr r3, [r7, #12]
800bd54: 681b ldr r3, [r3, #0]
800bd56: f442 5280 orr.w r2, r2, #4096 @ 0x1000
800bd5a: 605a str r2, [r3, #4]
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
800bd5c: 68fb ldr r3, [r7, #12]
800bd5e: 681b ldr r3, [r3, #0]
800bd60: 681b ldr r3, [r3, #0]
800bd62: f003 0340 and.w r3, r3, #64 @ 0x40
800bd66: 2b40 cmp r3, #64 @ 0x40
800bd68: d007 beq.n 800bd7a <HAL_SPI_TransmitReceive+0x118>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
800bd6a: 68fb ldr r3, [r7, #12]
800bd6c: 681b ldr r3, [r3, #0]
800bd6e: 681a ldr r2, [r3, #0]
800bd70: 68fb ldr r3, [r7, #12]
800bd72: 681b ldr r3, [r3, #0]
800bd74: f042 0240 orr.w r2, r2, #64 @ 0x40
800bd78: 601a str r2, [r3, #0]
}
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
800bd7a: 68fb ldr r3, [r7, #12]
800bd7c: 68db ldr r3, [r3, #12]
800bd7e: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
800bd82: f240 8083 bls.w 800be8c <HAL_SPI_TransmitReceive+0x22a>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
800bd86: 68fb ldr r3, [r7, #12]
800bd88: 685b ldr r3, [r3, #4]
800bd8a: 2b00 cmp r3, #0
800bd8c: d002 beq.n 800bd94 <HAL_SPI_TransmitReceive+0x132>
800bd8e: 8afb ldrh r3, [r7, #22]
800bd90: 2b01 cmp r3, #1
800bd92: d16f bne.n 800be74 <HAL_SPI_TransmitReceive+0x212>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800bd94: 68fb ldr r3, [r7, #12]
800bd96: 6b9b ldr r3, [r3, #56] @ 0x38
800bd98: 881a ldrh r2, [r3, #0]
800bd9a: 68fb ldr r3, [r7, #12]
800bd9c: 681b ldr r3, [r3, #0]
800bd9e: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800bda0: 68fb ldr r3, [r7, #12]
800bda2: 6b9b ldr r3, [r3, #56] @ 0x38
800bda4: 1c9a adds r2, r3, #2
800bda6: 68fb ldr r3, [r7, #12]
800bda8: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800bdaa: 68fb ldr r3, [r7, #12]
800bdac: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bdae: b29b uxth r3, r3
800bdb0: 3b01 subs r3, #1
800bdb2: b29a uxth r2, r3
800bdb4: 68fb ldr r3, [r7, #12]
800bdb6: 87da strh r2, [r3, #62] @ 0x3e
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
800bdb8: e05c b.n 800be74 <HAL_SPI_TransmitReceive+0x212>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
800bdba: 68fb ldr r3, [r7, #12]
800bdbc: 681b ldr r3, [r3, #0]
800bdbe: 689b ldr r3, [r3, #8]
800bdc0: f003 0302 and.w r3, r3, #2
800bdc4: 2b02 cmp r3, #2
800bdc6: d11b bne.n 800be00 <HAL_SPI_TransmitReceive+0x19e>
800bdc8: 68fb ldr r3, [r7, #12]
800bdca: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bdcc: b29b uxth r3, r3
800bdce: 2b00 cmp r3, #0
800bdd0: d016 beq.n 800be00 <HAL_SPI_TransmitReceive+0x19e>
800bdd2: 6a7b ldr r3, [r7, #36] @ 0x24
800bdd4: 2b01 cmp r3, #1
800bdd6: d113 bne.n 800be00 <HAL_SPI_TransmitReceive+0x19e>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800bdd8: 68fb ldr r3, [r7, #12]
800bdda: 6b9b ldr r3, [r3, #56] @ 0x38
800bddc: 881a ldrh r2, [r3, #0]
800bdde: 68fb ldr r3, [r7, #12]
800bde0: 681b ldr r3, [r3, #0]
800bde2: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800bde4: 68fb ldr r3, [r7, #12]
800bde6: 6b9b ldr r3, [r3, #56] @ 0x38
800bde8: 1c9a adds r2, r3, #2
800bdea: 68fb ldr r3, [r7, #12]
800bdec: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800bdee: 68fb ldr r3, [r7, #12]
800bdf0: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bdf2: b29b uxth r3, r3
800bdf4: 3b01 subs r3, #1
800bdf6: b29a uxth r2, r3
800bdf8: 68fb ldr r3, [r7, #12]
800bdfa: 87da strh r2, [r3, #62] @ 0x3e
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
800bdfc: 2300 movs r3, #0
800bdfe: 627b str r3, [r7, #36] @ 0x24
}
#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
800be00: 68fb ldr r3, [r7, #12]
800be02: 681b ldr r3, [r3, #0]
800be04: 689b ldr r3, [r3, #8]
800be06: f003 0301 and.w r3, r3, #1
800be0a: 2b01 cmp r3, #1
800be0c: d11c bne.n 800be48 <HAL_SPI_TransmitReceive+0x1e6>
800be0e: 68fb ldr r3, [r7, #12]
800be10: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800be14: b29b uxth r3, r3
800be16: 2b00 cmp r3, #0
800be18: d016 beq.n 800be48 <HAL_SPI_TransmitReceive+0x1e6>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
800be1a: 68fb ldr r3, [r7, #12]
800be1c: 681b ldr r3, [r3, #0]
800be1e: 68da ldr r2, [r3, #12]
800be20: 68fb ldr r3, [r7, #12]
800be22: 6c1b ldr r3, [r3, #64] @ 0x40
800be24: b292 uxth r2, r2
800be26: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
800be28: 68fb ldr r3, [r7, #12]
800be2a: 6c1b ldr r3, [r3, #64] @ 0x40
800be2c: 1c9a adds r2, r3, #2
800be2e: 68fb ldr r3, [r7, #12]
800be30: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferCount--;
800be32: 68fb ldr r3, [r7, #12]
800be34: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800be38: b29b uxth r3, r3
800be3a: 3b01 subs r3, #1
800be3c: b29a uxth r2, r3
800be3e: 68fb ldr r3, [r7, #12]
800be40: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
800be44: 2301 movs r3, #1
800be46: 627b str r3, [r7, #36] @ 0x24
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
800be48: f7f9 fa8c bl 8005364 <HAL_GetTick>
800be4c: 4602 mov r2, r0
800be4e: 6a3b ldr r3, [r7, #32]
800be50: 1ad3 subs r3, r2, r3
800be52: 6b3a ldr r2, [r7, #48] @ 0x30
800be54: 429a cmp r2, r3
800be56: d80d bhi.n 800be74 <HAL_SPI_TransmitReceive+0x212>
800be58: 6b3b ldr r3, [r7, #48] @ 0x30
800be5a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800be5e: d009 beq.n 800be74 <HAL_SPI_TransmitReceive+0x212>
{
hspi->State = HAL_SPI_STATE_READY;
800be60: 68fb ldr r3, [r7, #12]
800be62: 2201 movs r2, #1
800be64: f883 205d strb.w r2, [r3, #93] @ 0x5d
__HAL_UNLOCK(hspi);
800be68: 68fb ldr r3, [r7, #12]
800be6a: 2200 movs r2, #0
800be6c: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
800be70: 2303 movs r3, #3
800be72: e111 b.n 800c098 <HAL_SPI_TransmitReceive+0x436>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
800be74: 68fb ldr r3, [r7, #12]
800be76: 8fdb ldrh r3, [r3, #62] @ 0x3e
800be78: b29b uxth r3, r3
800be7a: 2b00 cmp r3, #0
800be7c: d19d bne.n 800bdba <HAL_SPI_TransmitReceive+0x158>
800be7e: 68fb ldr r3, [r7, #12]
800be80: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800be84: b29b uxth r3, r3
800be86: 2b00 cmp r3, #0
800be88: d197 bne.n 800bdba <HAL_SPI_TransmitReceive+0x158>
800be8a: e0e5 b.n 800c058 <HAL_SPI_TransmitReceive+0x3f6>
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
800be8c: 68fb ldr r3, [r7, #12]
800be8e: 685b ldr r3, [r3, #4]
800be90: 2b00 cmp r3, #0
800be92: d003 beq.n 800be9c <HAL_SPI_TransmitReceive+0x23a>
800be94: 8afb ldrh r3, [r7, #22]
800be96: 2b01 cmp r3, #1
800be98: f040 80d1 bne.w 800c03e <HAL_SPI_TransmitReceive+0x3dc>
{
if (hspi->TxXferCount > 1U)
800be9c: 68fb ldr r3, [r7, #12]
800be9e: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bea0: b29b uxth r3, r3
800bea2: 2b01 cmp r3, #1
800bea4: d912 bls.n 800becc <HAL_SPI_TransmitReceive+0x26a>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800bea6: 68fb ldr r3, [r7, #12]
800bea8: 6b9b ldr r3, [r3, #56] @ 0x38
800beaa: 881a ldrh r2, [r3, #0]
800beac: 68fb ldr r3, [r7, #12]
800beae: 681b ldr r3, [r3, #0]
800beb0: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800beb2: 68fb ldr r3, [r7, #12]
800beb4: 6b9b ldr r3, [r3, #56] @ 0x38
800beb6: 1c9a adds r2, r3, #2
800beb8: 68fb ldr r3, [r7, #12]
800beba: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount -= 2U;
800bebc: 68fb ldr r3, [r7, #12]
800bebe: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bec0: b29b uxth r3, r3
800bec2: 3b02 subs r3, #2
800bec4: b29a uxth r2, r3
800bec6: 68fb ldr r3, [r7, #12]
800bec8: 87da strh r2, [r3, #62] @ 0x3e
800beca: e0b8 b.n 800c03e <HAL_SPI_TransmitReceive+0x3dc>
}
else
{
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
800becc: 68fb ldr r3, [r7, #12]
800bece: 6b9a ldr r2, [r3, #56] @ 0x38
800bed0: 68fb ldr r3, [r7, #12]
800bed2: 681b ldr r3, [r3, #0]
800bed4: 330c adds r3, #12
800bed6: 7812 ldrb r2, [r2, #0]
800bed8: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
800beda: 68fb ldr r3, [r7, #12]
800bedc: 6b9b ldr r3, [r3, #56] @ 0x38
800bede: 1c5a adds r2, r3, #1
800bee0: 68fb ldr r3, [r7, #12]
800bee2: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800bee4: 68fb ldr r3, [r7, #12]
800bee6: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bee8: b29b uxth r3, r3
800beea: 3b01 subs r3, #1
800beec: b29a uxth r2, r3
800beee: 68fb ldr r3, [r7, #12]
800bef0: 87da strh r2, [r3, #62] @ 0x3e
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
}
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
800bef2: e0a4 b.n 800c03e <HAL_SPI_TransmitReceive+0x3dc>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
800bef4: 68fb ldr r3, [r7, #12]
800bef6: 681b ldr r3, [r3, #0]
800bef8: 689b ldr r3, [r3, #8]
800befa: f003 0302 and.w r3, r3, #2
800befe: 2b02 cmp r3, #2
800bf00: d134 bne.n 800bf6c <HAL_SPI_TransmitReceive+0x30a>
800bf02: 68fb ldr r3, [r7, #12]
800bf04: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bf06: b29b uxth r3, r3
800bf08: 2b00 cmp r3, #0
800bf0a: d02f beq.n 800bf6c <HAL_SPI_TransmitReceive+0x30a>
800bf0c: 6a7b ldr r3, [r7, #36] @ 0x24
800bf0e: 2b01 cmp r3, #1
800bf10: d12c bne.n 800bf6c <HAL_SPI_TransmitReceive+0x30a>
{
if (hspi->TxXferCount > 1U)
800bf12: 68fb ldr r3, [r7, #12]
800bf14: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bf16: b29b uxth r3, r3
800bf18: 2b01 cmp r3, #1
800bf1a: d912 bls.n 800bf42 <HAL_SPI_TransmitReceive+0x2e0>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800bf1c: 68fb ldr r3, [r7, #12]
800bf1e: 6b9b ldr r3, [r3, #56] @ 0x38
800bf20: 881a ldrh r2, [r3, #0]
800bf22: 68fb ldr r3, [r7, #12]
800bf24: 681b ldr r3, [r3, #0]
800bf26: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800bf28: 68fb ldr r3, [r7, #12]
800bf2a: 6b9b ldr r3, [r3, #56] @ 0x38
800bf2c: 1c9a adds r2, r3, #2
800bf2e: 68fb ldr r3, [r7, #12]
800bf30: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount -= 2U;
800bf32: 68fb ldr r3, [r7, #12]
800bf34: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bf36: b29b uxth r3, r3
800bf38: 3b02 subs r3, #2
800bf3a: b29a uxth r2, r3
800bf3c: 68fb ldr r3, [r7, #12]
800bf3e: 87da strh r2, [r3, #62] @ 0x3e
800bf40: e012 b.n 800bf68 <HAL_SPI_TransmitReceive+0x306>
}
else
{
*(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
800bf42: 68fb ldr r3, [r7, #12]
800bf44: 6b9a ldr r2, [r3, #56] @ 0x38
800bf46: 68fb ldr r3, [r7, #12]
800bf48: 681b ldr r3, [r3, #0]
800bf4a: 330c adds r3, #12
800bf4c: 7812 ldrb r2, [r2, #0]
800bf4e: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
800bf50: 68fb ldr r3, [r7, #12]
800bf52: 6b9b ldr r3, [r3, #56] @ 0x38
800bf54: 1c5a adds r2, r3, #1
800bf56: 68fb ldr r3, [r7, #12]
800bf58: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800bf5a: 68fb ldr r3, [r7, #12]
800bf5c: 8fdb ldrh r3, [r3, #62] @ 0x3e
800bf5e: b29b uxth r3, r3
800bf60: 3b01 subs r3, #1
800bf62: b29a uxth r2, r3
800bf64: 68fb ldr r3, [r7, #12]
800bf66: 87da strh r2, [r3, #62] @ 0x3e
}
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
800bf68: 2300 movs r3, #0
800bf6a: 627b str r3, [r7, #36] @ 0x24
}
#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
800bf6c: 68fb ldr r3, [r7, #12]
800bf6e: 681b ldr r3, [r3, #0]
800bf70: 689b ldr r3, [r3, #8]
800bf72: f003 0301 and.w r3, r3, #1
800bf76: 2b01 cmp r3, #1
800bf78: d148 bne.n 800c00c <HAL_SPI_TransmitReceive+0x3aa>
800bf7a: 68fb ldr r3, [r7, #12]
800bf7c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800bf80: b29b uxth r3, r3
800bf82: 2b00 cmp r3, #0
800bf84: d042 beq.n 800c00c <HAL_SPI_TransmitReceive+0x3aa>
{
if (hspi->RxXferCount > 1U)
800bf86: 68fb ldr r3, [r7, #12]
800bf88: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800bf8c: b29b uxth r3, r3
800bf8e: 2b01 cmp r3, #1
800bf90: d923 bls.n 800bfda <HAL_SPI_TransmitReceive+0x378>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
800bf92: 68fb ldr r3, [r7, #12]
800bf94: 681b ldr r3, [r3, #0]
800bf96: 68da ldr r2, [r3, #12]
800bf98: 68fb ldr r3, [r7, #12]
800bf9a: 6c1b ldr r3, [r3, #64] @ 0x40
800bf9c: b292 uxth r2, r2
800bf9e: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
800bfa0: 68fb ldr r3, [r7, #12]
800bfa2: 6c1b ldr r3, [r3, #64] @ 0x40
800bfa4: 1c9a adds r2, r3, #2
800bfa6: 68fb ldr r3, [r7, #12]
800bfa8: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferCount -= 2U;
800bfaa: 68fb ldr r3, [r7, #12]
800bfac: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800bfb0: b29b uxth r3, r3
800bfb2: 3b02 subs r3, #2
800bfb4: b29a uxth r2, r3
800bfb6: 68fb ldr r3, [r7, #12]
800bfb8: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
if (hspi->RxXferCount <= 1U)
800bfbc: 68fb ldr r3, [r7, #12]
800bfbe: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800bfc2: b29b uxth r3, r3
800bfc4: 2b01 cmp r3, #1
800bfc6: d81f bhi.n 800c008 <HAL_SPI_TransmitReceive+0x3a6>
{
/* Set RX Fifo threshold before to switch on 8 bit data size */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
800bfc8: 68fb ldr r3, [r7, #12]
800bfca: 681b ldr r3, [r3, #0]
800bfcc: 685a ldr r2, [r3, #4]
800bfce: 68fb ldr r3, [r7, #12]
800bfd0: 681b ldr r3, [r3, #0]
800bfd2: f442 5280 orr.w r2, r2, #4096 @ 0x1000
800bfd6: 605a str r2, [r3, #4]
800bfd8: e016 b.n 800c008 <HAL_SPI_TransmitReceive+0x3a6>
}
}
else
{
(*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
800bfda: 68fb ldr r3, [r7, #12]
800bfdc: 681b ldr r3, [r3, #0]
800bfde: f103 020c add.w r2, r3, #12
800bfe2: 68fb ldr r3, [r7, #12]
800bfe4: 6c1b ldr r3, [r3, #64] @ 0x40
800bfe6: 7812 ldrb r2, [r2, #0]
800bfe8: b2d2 uxtb r2, r2
800bfea: 701a strb r2, [r3, #0]
hspi->pRxBuffPtr++;
800bfec: 68fb ldr r3, [r7, #12]
800bfee: 6c1b ldr r3, [r3, #64] @ 0x40
800bff0: 1c5a adds r2, r3, #1
800bff2: 68fb ldr r3, [r7, #12]
800bff4: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferCount--;
800bff6: 68fb ldr r3, [r7, #12]
800bff8: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800bffc: b29b uxth r3, r3
800bffe: 3b01 subs r3, #1
800c000: b29a uxth r2, r3
800c002: 68fb ldr r3, [r7, #12]
800c004: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
}
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
800c008: 2301 movs r3, #1
800c00a: 627b str r3, [r7, #36] @ 0x24
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
800c00c: f7f9 f9aa bl 8005364 <HAL_GetTick>
800c010: 4602 mov r2, r0
800c012: 6a3b ldr r3, [r7, #32]
800c014: 1ad3 subs r3, r2, r3
800c016: 6b3a ldr r2, [r7, #48] @ 0x30
800c018: 429a cmp r2, r3
800c01a: d803 bhi.n 800c024 <HAL_SPI_TransmitReceive+0x3c2>
800c01c: 6b3b ldr r3, [r7, #48] @ 0x30
800c01e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800c022: d102 bne.n 800c02a <HAL_SPI_TransmitReceive+0x3c8>
800c024: 6b3b ldr r3, [r7, #48] @ 0x30
800c026: 2b00 cmp r3, #0
800c028: d109 bne.n 800c03e <HAL_SPI_TransmitReceive+0x3dc>
{
hspi->State = HAL_SPI_STATE_READY;
800c02a: 68fb ldr r3, [r7, #12]
800c02c: 2201 movs r2, #1
800c02e: f883 205d strb.w r2, [r3, #93] @ 0x5d
__HAL_UNLOCK(hspi);
800c032: 68fb ldr r3, [r7, #12]
800c034: 2200 movs r2, #0
800c036: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
800c03a: 2303 movs r3, #3
800c03c: e02c b.n 800c098 <HAL_SPI_TransmitReceive+0x436>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
800c03e: 68fb ldr r3, [r7, #12]
800c040: 8fdb ldrh r3, [r3, #62] @ 0x3e
800c042: b29b uxth r3, r3
800c044: 2b00 cmp r3, #0
800c046: f47f af55 bne.w 800bef4 <HAL_SPI_TransmitReceive+0x292>
800c04a: 68fb ldr r3, [r7, #12]
800c04c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800c050: b29b uxth r3, r3
800c052: 2b00 cmp r3, #0
800c054: f47f af4e bne.w 800bef4 <HAL_SPI_TransmitReceive+0x292>
return HAL_ERROR;
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
800c058: 6a3a ldr r2, [r7, #32]
800c05a: 6b39 ldr r1, [r7, #48] @ 0x30
800c05c: 68f8 ldr r0, [r7, #12]
800c05e: f000 fc1b bl 800c898 <SPI_EndRxTxTransaction>
800c062: 4603 mov r3, r0
800c064: 2b00 cmp r3, #0
800c066: d008 beq.n 800c07a <HAL_SPI_TransmitReceive+0x418>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
800c068: 68fb ldr r3, [r7, #12]
800c06a: 2220 movs r2, #32
800c06c: 661a str r2, [r3, #96] @ 0x60
__HAL_UNLOCK(hspi);
800c06e: 68fb ldr r3, [r7, #12]
800c070: 2200 movs r2, #0
800c072: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_ERROR;
800c076: 2301 movs r3, #1
800c078: e00e b.n 800c098 <HAL_SPI_TransmitReceive+0x436>
}
hspi->State = HAL_SPI_STATE_READY;
800c07a: 68fb ldr r3, [r7, #12]
800c07c: 2201 movs r2, #1
800c07e: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Unlock the process */
__HAL_UNLOCK(hspi);
800c082: 68fb ldr r3, [r7, #12]
800c084: 2200 movs r2, #0
800c086: f883 205c strb.w r2, [r3, #92] @ 0x5c
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
800c08a: 68fb ldr r3, [r7, #12]
800c08c: 6e1b ldr r3, [r3, #96] @ 0x60
800c08e: 2b00 cmp r3, #0
800c090: d001 beq.n 800c096 <HAL_SPI_TransmitReceive+0x434>
{
return HAL_ERROR;
800c092: 2301 movs r3, #1
800c094: e000 b.n 800c098 <HAL_SPI_TransmitReceive+0x436>
}
else
{
return HAL_OK;
800c096: 2300 movs r3, #0
}
}
800c098: 4618 mov r0, r3
800c09a: 3728 adds r7, #40 @ 0x28
800c09c: 46bd mov sp, r7
800c09e: bd80 pop {r7, pc}
0800c0a0 <HAL_SPI_TransmitReceive_DMA>:
* @param Size amount of data elements (u8 or u16) to be sent and received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
800c0a0: b580 push {r7, lr}
800c0a2: b086 sub sp, #24
800c0a4: af00 add r7, sp, #0
800c0a6: 60f8 str r0, [r7, #12]
800c0a8: 60b9 str r1, [r7, #8]
800c0aa: 607a str r2, [r7, #4]
800c0ac: 807b strh r3, [r7, #2]
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Init temporary variables */
tmp_state = hspi->State;
800c0ae: 68fb ldr r3, [r7, #12]
800c0b0: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
800c0b4: 75fb strb r3, [r7, #23]
tmp_mode = hspi->Init.Mode;
800c0b6: 68fb ldr r3, [r7, #12]
800c0b8: 685b ldr r3, [r3, #4]
800c0ba: 613b str r3, [r7, #16]
if (!((tmp_state == HAL_SPI_STATE_READY) ||
800c0bc: 7dfb ldrb r3, [r7, #23]
800c0be: 2b01 cmp r3, #1
800c0c0: d00c beq.n 800c0dc <HAL_SPI_TransmitReceive_DMA+0x3c>
800c0c2: 693b ldr r3, [r7, #16]
800c0c4: f5b3 7f82 cmp.w r3, #260 @ 0x104
800c0c8: d106 bne.n 800c0d8 <HAL_SPI_TransmitReceive_DMA+0x38>
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
800c0ca: 68fb ldr r3, [r7, #12]
800c0cc: 689b ldr r3, [r3, #8]
800c0ce: 2b00 cmp r3, #0
800c0d0: d102 bne.n 800c0d8 <HAL_SPI_TransmitReceive_DMA+0x38>
800c0d2: 7dfb ldrb r3, [r7, #23]
800c0d4: 2b04 cmp r3, #4
800c0d6: d001 beq.n 800c0dc <HAL_SPI_TransmitReceive_DMA+0x3c>
(tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
return HAL_BUSY;
800c0d8: 2302 movs r3, #2
800c0da: e158 b.n 800c38e <HAL_SPI_TransmitReceive_DMA+0x2ee>
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
800c0dc: 68bb ldr r3, [r7, #8]
800c0de: 2b00 cmp r3, #0
800c0e0: d005 beq.n 800c0ee <HAL_SPI_TransmitReceive_DMA+0x4e>
800c0e2: 687b ldr r3, [r7, #4]
800c0e4: 2b00 cmp r3, #0
800c0e6: d002 beq.n 800c0ee <HAL_SPI_TransmitReceive_DMA+0x4e>
800c0e8: 887b ldrh r3, [r7, #2]
800c0ea: 2b00 cmp r3, #0
800c0ec: d101 bne.n 800c0f2 <HAL_SPI_TransmitReceive_DMA+0x52>
{
return HAL_ERROR;
800c0ee: 2301 movs r3, #1
800c0f0: e14d b.n 800c38e <HAL_SPI_TransmitReceive_DMA+0x2ee>
}
/* Process locked */
__HAL_LOCK(hspi);
800c0f2: 68fb ldr r3, [r7, #12]
800c0f4: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
800c0f8: 2b01 cmp r3, #1
800c0fa: d101 bne.n 800c100 <HAL_SPI_TransmitReceive_DMA+0x60>
800c0fc: 2302 movs r3, #2
800c0fe: e146 b.n 800c38e <HAL_SPI_TransmitReceive_DMA+0x2ee>
800c100: 68fb ldr r3, [r7, #12]
800c102: 2201 movs r2, #1
800c104: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
800c108: 68fb ldr r3, [r7, #12]
800c10a: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
800c10e: b2db uxtb r3, r3
800c110: 2b04 cmp r3, #4
800c112: d003 beq.n 800c11c <HAL_SPI_TransmitReceive_DMA+0x7c>
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
800c114: 68fb ldr r3, [r7, #12]
800c116: 2205 movs r2, #5
800c118: f883 205d strb.w r2, [r3, #93] @ 0x5d
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800c11c: 68fb ldr r3, [r7, #12]
800c11e: 2200 movs r2, #0
800c120: 661a str r2, [r3, #96] @ 0x60
hspi->pTxBuffPtr = (const uint8_t *)pTxData;
800c122: 68fb ldr r3, [r7, #12]
800c124: 68ba ldr r2, [r7, #8]
800c126: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferSize = Size;
800c128: 68fb ldr r3, [r7, #12]
800c12a: 887a ldrh r2, [r7, #2]
800c12c: 879a strh r2, [r3, #60] @ 0x3c
hspi->TxXferCount = Size;
800c12e: 68fb ldr r3, [r7, #12]
800c130: 887a ldrh r2, [r7, #2]
800c132: 87da strh r2, [r3, #62] @ 0x3e
hspi->pRxBuffPtr = (uint8_t *)pRxData;
800c134: 68fb ldr r3, [r7, #12]
800c136: 687a ldr r2, [r7, #4]
800c138: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferSize = Size;
800c13a: 68fb ldr r3, [r7, #12]
800c13c: 887a ldrh r2, [r7, #2]
800c13e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hspi->RxXferCount = Size;
800c142: 68fb ldr r3, [r7, #12]
800c144: 887a ldrh r2, [r7, #2]
800c146: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
/* Init field not used in handle to zero */
hspi->RxISR = NULL;
800c14a: 68fb ldr r3, [r7, #12]
800c14c: 2200 movs r2, #0
800c14e: 64da str r2, [r3, #76] @ 0x4c
hspi->TxISR = NULL;
800c150: 68fb ldr r3, [r7, #12]
800c152: 2200 movs r2, #0
800c154: 651a str r2, [r3, #80] @ 0x50
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Reset the threshold bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
800c156: 68fb ldr r3, [r7, #12]
800c158: 681b ldr r3, [r3, #0]
800c15a: 685a ldr r2, [r3, #4]
800c15c: 68fb ldr r3, [r7, #12]
800c15e: 681b ldr r3, [r3, #0]
800c160: f422 42c0 bic.w r2, r2, #24576 @ 0x6000
800c164: 605a str r2, [r3, #4]
/* The packing mode management is enabled by the DMA settings according the spi data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
800c166: 68fb ldr r3, [r7, #12]
800c168: 68db ldr r3, [r3, #12]
800c16a: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
800c16e: d908 bls.n 800c182 <HAL_SPI_TransmitReceive_DMA+0xe2>
{
/* Set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
800c170: 68fb ldr r3, [r7, #12]
800c172: 681b ldr r3, [r3, #0]
800c174: 685a ldr r2, [r3, #4]
800c176: 68fb ldr r3, [r7, #12]
800c178: 681b ldr r3, [r3, #0]
800c17a: f422 5280 bic.w r2, r2, #4096 @ 0x1000
800c17e: 605a str r2, [r3, #4]
800c180: e06f b.n 800c262 <HAL_SPI_TransmitReceive_DMA+0x1c2>
}
else
{
/* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
800c182: 68fb ldr r3, [r7, #12]
800c184: 681b ldr r3, [r3, #0]
800c186: 685a ldr r2, [r3, #4]
800c188: 68fb ldr r3, [r7, #12]
800c18a: 681b ldr r3, [r3, #0]
800c18c: f442 5280 orr.w r2, r2, #4096 @ 0x1000
800c190: 605a str r2, [r3, #4]
if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
800c192: 68fb ldr r3, [r7, #12]
800c194: 6d5b ldr r3, [r3, #84] @ 0x54
800c196: 699b ldr r3, [r3, #24]
800c198: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800c19c: d126 bne.n 800c1ec <HAL_SPI_TransmitReceive_DMA+0x14c>
{
if ((hspi->TxXferSize & 0x1U) == 0x0U)
800c19e: 68fb ldr r3, [r7, #12]
800c1a0: 8f9b ldrh r3, [r3, #60] @ 0x3c
800c1a2: f003 0301 and.w r3, r3, #1
800c1a6: 2b00 cmp r3, #0
800c1a8: d10f bne.n 800c1ca <HAL_SPI_TransmitReceive_DMA+0x12a>
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
800c1aa: 68fb ldr r3, [r7, #12]
800c1ac: 681b ldr r3, [r3, #0]
800c1ae: 685a ldr r2, [r3, #4]
800c1b0: 68fb ldr r3, [r7, #12]
800c1b2: 681b ldr r3, [r3, #0]
800c1b4: f422 4280 bic.w r2, r2, #16384 @ 0x4000
800c1b8: 605a str r2, [r3, #4]
hspi->TxXferCount = hspi->TxXferCount >> 1U;
800c1ba: 68fb ldr r3, [r7, #12]
800c1bc: 8fdb ldrh r3, [r3, #62] @ 0x3e
800c1be: b29b uxth r3, r3
800c1c0: 085b lsrs r3, r3, #1
800c1c2: b29a uxth r2, r3
800c1c4: 68fb ldr r3, [r7, #12]
800c1c6: 87da strh r2, [r3, #62] @ 0x3e
800c1c8: e010 b.n 800c1ec <HAL_SPI_TransmitReceive_DMA+0x14c>
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
800c1ca: 68fb ldr r3, [r7, #12]
800c1cc: 681b ldr r3, [r3, #0]
800c1ce: 685a ldr r2, [r3, #4]
800c1d0: 68fb ldr r3, [r7, #12]
800c1d2: 681b ldr r3, [r3, #0]
800c1d4: f442 4280 orr.w r2, r2, #16384 @ 0x4000
800c1d8: 605a str r2, [r3, #4]
hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
800c1da: 68fb ldr r3, [r7, #12]
800c1dc: 8fdb ldrh r3, [r3, #62] @ 0x3e
800c1de: b29b uxth r3, r3
800c1e0: 085b lsrs r3, r3, #1
800c1e2: b29b uxth r3, r3
800c1e4: 3301 adds r3, #1
800c1e6: b29a uxth r2, r3
800c1e8: 68fb ldr r3, [r7, #12]
800c1ea: 87da strh r2, [r3, #62] @ 0x3e
}
}
if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
800c1ec: 68fb ldr r3, [r7, #12]
800c1ee: 6d9b ldr r3, [r3, #88] @ 0x58
800c1f0: 699b ldr r3, [r3, #24]
800c1f2: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800c1f6: d134 bne.n 800c262 <HAL_SPI_TransmitReceive_DMA+0x1c2>
{
/* Set RX Fifo threshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
800c1f8: 68fb ldr r3, [r7, #12]
800c1fa: 681b ldr r3, [r3, #0]
800c1fc: 685a ldr r2, [r3, #4]
800c1fe: 68fb ldr r3, [r7, #12]
800c200: 681b ldr r3, [r3, #0]
800c202: f422 5280 bic.w r2, r2, #4096 @ 0x1000
800c206: 605a str r2, [r3, #4]
if ((hspi->RxXferCount & 0x1U) == 0x0U)
800c208: 68fb ldr r3, [r7, #12]
800c20a: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800c20e: b29b uxth r3, r3
800c210: f003 0301 and.w r3, r3, #1
800c214: 2b00 cmp r3, #0
800c216: d111 bne.n 800c23c <HAL_SPI_TransmitReceive_DMA+0x19c>
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
800c218: 68fb ldr r3, [r7, #12]
800c21a: 681b ldr r3, [r3, #0]
800c21c: 685a ldr r2, [r3, #4]
800c21e: 68fb ldr r3, [r7, #12]
800c220: 681b ldr r3, [r3, #0]
800c222: f422 5200 bic.w r2, r2, #8192 @ 0x2000
800c226: 605a str r2, [r3, #4]
hspi->RxXferCount = hspi->RxXferCount >> 1U;
800c228: 68fb ldr r3, [r7, #12]
800c22a: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800c22e: b29b uxth r3, r3
800c230: 085b lsrs r3, r3, #1
800c232: b29a uxth r2, r3
800c234: 68fb ldr r3, [r7, #12]
800c236: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
800c23a: e012 b.n 800c262 <HAL_SPI_TransmitReceive_DMA+0x1c2>
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
800c23c: 68fb ldr r3, [r7, #12]
800c23e: 681b ldr r3, [r3, #0]
800c240: 685a ldr r2, [r3, #4]
800c242: 68fb ldr r3, [r7, #12]
800c244: 681b ldr r3, [r3, #0]
800c246: f442 5200 orr.w r2, r2, #8192 @ 0x2000
800c24a: 605a str r2, [r3, #4]
hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
800c24c: 68fb ldr r3, [r7, #12]
800c24e: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800c252: b29b uxth r3, r3
800c254: 085b lsrs r3, r3, #1
800c256: b29b uxth r3, r3
800c258: 3301 adds r3, #1
800c25a: b29a uxth r2, r3
800c25c: 68fb ldr r3, [r7, #12]
800c25e: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
}
}
}
/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
if (hspi->State == HAL_SPI_STATE_BUSY_RX)
800c262: 68fb ldr r3, [r7, #12]
800c264: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
800c268: b2db uxtb r3, r3
800c26a: 2b04 cmp r3, #4
800c26c: d108 bne.n 800c280 <HAL_SPI_TransmitReceive_DMA+0x1e0>
{
/* Set the SPI Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
800c26e: 68fb ldr r3, [r7, #12]
800c270: 6d9b ldr r3, [r3, #88] @ 0x58
800c272: 4a49 ldr r2, [pc, #292] @ (800c398 <HAL_SPI_TransmitReceive_DMA+0x2f8>)
800c274: 631a str r2, [r3, #48] @ 0x30
hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
800c276: 68fb ldr r3, [r7, #12]
800c278: 6d9b ldr r3, [r3, #88] @ 0x58
800c27a: 4a48 ldr r2, [pc, #288] @ (800c39c <HAL_SPI_TransmitReceive_DMA+0x2fc>)
800c27c: 62da str r2, [r3, #44] @ 0x2c
800c27e: e007 b.n 800c290 <HAL_SPI_TransmitReceive_DMA+0x1f0>
}
else
{
/* Set the SPI Tx/Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
800c280: 68fb ldr r3, [r7, #12]
800c282: 6d9b ldr r3, [r3, #88] @ 0x58
800c284: 4a46 ldr r2, [pc, #280] @ (800c3a0 <HAL_SPI_TransmitReceive_DMA+0x300>)
800c286: 631a str r2, [r3, #48] @ 0x30
hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
800c288: 68fb ldr r3, [r7, #12]
800c28a: 6d9b ldr r3, [r3, #88] @ 0x58
800c28c: 4a45 ldr r2, [pc, #276] @ (800c3a4 <HAL_SPI_TransmitReceive_DMA+0x304>)
800c28e: 62da str r2, [r3, #44] @ 0x2c
}
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
800c290: 68fb ldr r3, [r7, #12]
800c292: 6d9b ldr r3, [r3, #88] @ 0x58
800c294: 4a44 ldr r2, [pc, #272] @ (800c3a8 <HAL_SPI_TransmitReceive_DMA+0x308>)
800c296: 635a str r2, [r3, #52] @ 0x34
/* Set the DMA AbortCpltCallback */
hspi->hdmarx->XferAbortCallback = NULL;
800c298: 68fb ldr r3, [r7, #12]
800c29a: 6d9b ldr r3, [r3, #88] @ 0x58
800c29c: 2200 movs r2, #0
800c29e: 639a str r2, [r3, #56] @ 0x38
/* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
800c2a0: 68fb ldr r3, [r7, #12]
800c2a2: 6d98 ldr r0, [r3, #88] @ 0x58
800c2a4: 68fb ldr r3, [r7, #12]
800c2a6: 681b ldr r3, [r3, #0]
800c2a8: 330c adds r3, #12
800c2aa: 4619 mov r1, r3
800c2ac: 68fb ldr r3, [r7, #12]
800c2ae: 6c1b ldr r3, [r3, #64] @ 0x40
800c2b0: 461a mov r2, r3
hspi->RxXferCount))
800c2b2: 68fb ldr r3, [r7, #12]
800c2b4: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46
800c2b8: b29b uxth r3, r3
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
800c2ba: f7f9 fa7d bl 80057b8 <HAL_DMA_Start_IT>
800c2be: 4603 mov r3, r0
800c2c0: 2b00 cmp r3, #0
800c2c2: d00b beq.n 800c2dc <HAL_SPI_TransmitReceive_DMA+0x23c>
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
800c2c4: 68fb ldr r3, [r7, #12]
800c2c6: 6e1b ldr r3, [r3, #96] @ 0x60
800c2c8: f043 0210 orr.w r2, r3, #16
800c2cc: 68fb ldr r3, [r7, #12]
800c2ce: 661a str r2, [r3, #96] @ 0x60
/* Process Unlocked */
__HAL_UNLOCK(hspi);
800c2d0: 68fb ldr r3, [r7, #12]
800c2d2: 2200 movs r2, #0
800c2d4: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_ERROR;
800c2d8: 2301 movs r3, #1
800c2da: e058 b.n 800c38e <HAL_SPI_TransmitReceive_DMA+0x2ee>
}
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
800c2dc: 68fb ldr r3, [r7, #12]
800c2de: 681b ldr r3, [r3, #0]
800c2e0: 685a ldr r2, [r3, #4]
800c2e2: 68fb ldr r3, [r7, #12]
800c2e4: 681b ldr r3, [r3, #0]
800c2e6: f042 0201 orr.w r2, r2, #1
800c2ea: 605a str r2, [r3, #4]
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
hspi->hdmatx->XferHalfCpltCallback = NULL;
800c2ec: 68fb ldr r3, [r7, #12]
800c2ee: 6d5b ldr r3, [r3, #84] @ 0x54
800c2f0: 2200 movs r2, #0
800c2f2: 631a str r2, [r3, #48] @ 0x30
hspi->hdmatx->XferCpltCallback = NULL;
800c2f4: 68fb ldr r3, [r7, #12]
800c2f6: 6d5b ldr r3, [r3, #84] @ 0x54
800c2f8: 2200 movs r2, #0
800c2fa: 62da str r2, [r3, #44] @ 0x2c
hspi->hdmatx->XferErrorCallback = NULL;
800c2fc: 68fb ldr r3, [r7, #12]
800c2fe: 6d5b ldr r3, [r3, #84] @ 0x54
800c300: 2200 movs r2, #0
800c302: 635a str r2, [r3, #52] @ 0x34
hspi->hdmatx->XferAbortCallback = NULL;
800c304: 68fb ldr r3, [r7, #12]
800c306: 6d5b ldr r3, [r3, #84] @ 0x54
800c308: 2200 movs r2, #0
800c30a: 639a str r2, [r3, #56] @ 0x38
/* Enable the Tx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
800c30c: 68fb ldr r3, [r7, #12]
800c30e: 6d58 ldr r0, [r3, #84] @ 0x54
800c310: 68fb ldr r3, [r7, #12]
800c312: 6b9b ldr r3, [r3, #56] @ 0x38
800c314: 4619 mov r1, r3
800c316: 68fb ldr r3, [r7, #12]
800c318: 681b ldr r3, [r3, #0]
800c31a: 330c adds r3, #12
800c31c: 461a mov r2, r3
hspi->TxXferCount))
800c31e: 68fb ldr r3, [r7, #12]
800c320: 8fdb ldrh r3, [r3, #62] @ 0x3e
800c322: b29b uxth r3, r3
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
800c324: f7f9 fa48 bl 80057b8 <HAL_DMA_Start_IT>
800c328: 4603 mov r3, r0
800c32a: 2b00 cmp r3, #0
800c32c: d00b beq.n 800c346 <HAL_SPI_TransmitReceive_DMA+0x2a6>
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
800c32e: 68fb ldr r3, [r7, #12]
800c330: 6e1b ldr r3, [r3, #96] @ 0x60
800c332: f043 0210 orr.w r2, r3, #16
800c336: 68fb ldr r3, [r7, #12]
800c338: 661a str r2, [r3, #96] @ 0x60
/* Process Unlocked */
__HAL_UNLOCK(hspi);
800c33a: 68fb ldr r3, [r7, #12]
800c33c: 2200 movs r2, #0
800c33e: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_ERROR;
800c342: 2301 movs r3, #1
800c344: e023 b.n 800c38e <HAL_SPI_TransmitReceive_DMA+0x2ee>
}
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
800c346: 68fb ldr r3, [r7, #12]
800c348: 681b ldr r3, [r3, #0]
800c34a: 681b ldr r3, [r3, #0]
800c34c: f003 0340 and.w r3, r3, #64 @ 0x40
800c350: 2b40 cmp r3, #64 @ 0x40
800c352: d007 beq.n 800c364 <HAL_SPI_TransmitReceive_DMA+0x2c4>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
800c354: 68fb ldr r3, [r7, #12]
800c356: 681b ldr r3, [r3, #0]
800c358: 681a ldr r2, [r3, #0]
800c35a: 68fb ldr r3, [r7, #12]
800c35c: 681b ldr r3, [r3, #0]
800c35e: f042 0240 orr.w r2, r2, #64 @ 0x40
800c362: 601a str r2, [r3, #0]
}
/* Process Unlocked */
__HAL_UNLOCK(hspi);
800c364: 68fb ldr r3, [r7, #12]
800c366: 2200 movs r2, #0
800c368: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
800c36c: 68fb ldr r3, [r7, #12]
800c36e: 681b ldr r3, [r3, #0]
800c370: 685a ldr r2, [r3, #4]
800c372: 68fb ldr r3, [r7, #12]
800c374: 681b ldr r3, [r3, #0]
800c376: f042 0220 orr.w r2, r2, #32
800c37a: 605a str r2, [r3, #4]
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
800c37c: 68fb ldr r3, [r7, #12]
800c37e: 681b ldr r3, [r3, #0]
800c380: 685a ldr r2, [r3, #4]
800c382: 68fb ldr r3, [r7, #12]
800c384: 681b ldr r3, [r3, #0]
800c386: f042 0202 orr.w r2, r2, #2
800c38a: 605a str r2, [r3, #4]
return HAL_OK;
800c38c: 2300 movs r3, #0
}
800c38e: 4618 mov r0, r3
800c390: 3718 adds r7, #24
800c392: 46bd mov sp, r7
800c394: bd80 pop {r7, pc}
800c396: bf00 nop
800c398: 0800c535 .word 0x0800c535
800c39c: 0800c3fd .word 0x0800c3fd
800c3a0: 0800c551 .word 0x0800c551
800c3a4: 0800c4a5 .word 0x0800c4a5
800c3a8: 0800c56d .word 0x0800c56d
0800c3ac <HAL_SPI_RxCpltCallback>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
800c3ac: b480 push {r7}
800c3ae: b083 sub sp, #12
800c3b0: af00 add r7, sp, #0
800c3b2: 6078 str r0, [r7, #4]
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_RxCpltCallback should be implemented in the user file
*/
}
800c3b4: bf00 nop
800c3b6: 370c adds r7, #12
800c3b8: 46bd mov sp, r7
800c3ba: f85d 7b04 ldr.w r7, [sp], #4
800c3be: 4770 bx lr
0800c3c0 <HAL_SPI_RxHalfCpltCallback>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
800c3c0: b480 push {r7}
800c3c2: b083 sub sp, #12
800c3c4: af00 add r7, sp, #0
800c3c6: 6078 str r0, [r7, #4]
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
*/
}
800c3c8: bf00 nop
800c3ca: 370c adds r7, #12
800c3cc: 46bd mov sp, r7
800c3ce: f85d 7b04 ldr.w r7, [sp], #4
800c3d2: 4770 bx lr
0800c3d4 <HAL_SPI_TxRxHalfCpltCallback>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
800c3d4: b480 push {r7}
800c3d6: b083 sub sp, #12
800c3d8: af00 add r7, sp, #0
800c3da: 6078 str r0, [r7, #4]
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
*/
}
800c3dc: bf00 nop
800c3de: 370c adds r7, #12
800c3e0: 46bd mov sp, r7
800c3e2: f85d 7b04 ldr.w r7, [sp], #4
800c3e6: 4770 bx lr
0800c3e8 <HAL_SPI_ErrorCallback>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
800c3e8: b480 push {r7}
800c3ea: b083 sub sp, #12
800c3ec: af00 add r7, sp, #0
800c3ee: 6078 str r0, [r7, #4]
the HAL_SPI_ErrorCallback should be implemented in the user file
*/
/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
and user can use HAL_SPI_GetError() API to check the latest error occurred
*/
}
800c3f0: bf00 nop
800c3f2: 370c adds r7, #12
800c3f4: 46bd mov sp, r7
800c3f6: f85d 7b04 ldr.w r7, [sp], #4
800c3fa: 4770 bx lr
0800c3fc <SPI_DMAReceiveCplt>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
800c3fc: b580 push {r7, lr}
800c3fe: b084 sub sp, #16
800c400: af00 add r7, sp, #0
800c402: 6078 str r0, [r7, #4]
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
800c404: 687b ldr r3, [r7, #4]
800c406: 6a9b ldr r3, [r3, #40] @ 0x28
800c408: 60fb str r3, [r7, #12]
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800c40a: f7f8 ffab bl 8005364 <HAL_GetTick>
800c40e: 60b8 str r0, [r7, #8]
/* DMA Normal Mode */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
800c410: 687b ldr r3, [r7, #4]
800c412: 681b ldr r3, [r3, #0]
800c414: 681b ldr r3, [r3, #0]
800c416: f003 0320 and.w r3, r3, #32
800c41a: 2b20 cmp r3, #32
800c41c: d03c beq.n 800c498 <SPI_DMAReceiveCplt+0x9c>
{
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
800c41e: 68fb ldr r3, [r7, #12]
800c420: 681b ldr r3, [r3, #0]
800c422: 685a ldr r2, [r3, #4]
800c424: 68fb ldr r3, [r7, #12]
800c426: 681b ldr r3, [r3, #0]
800c428: f022 0220 bic.w r2, r2, #32
800c42c: 605a str r2, [r3, #4]
}
}
#endif /* USE_SPI_CRC */
/* Check if we are in Master RX 2 line mode */
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
800c42e: 68fb ldr r3, [r7, #12]
800c430: 689b ldr r3, [r3, #8]
800c432: 2b00 cmp r3, #0
800c434: d10d bne.n 800c452 <SPI_DMAReceiveCplt+0x56>
800c436: 68fb ldr r3, [r7, #12]
800c438: 685b ldr r3, [r3, #4]
800c43a: f5b3 7f82 cmp.w r3, #260 @ 0x104
800c43e: d108 bne.n 800c452 <SPI_DMAReceiveCplt+0x56>
{
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
800c440: 68fb ldr r3, [r7, #12]
800c442: 681b ldr r3, [r3, #0]
800c444: 685a ldr r2, [r3, #4]
800c446: 68fb ldr r3, [r7, #12]
800c448: 681b ldr r3, [r3, #0]
800c44a: f022 0203 bic.w r2, r2, #3
800c44e: 605a str r2, [r3, #4]
800c450: e007 b.n 800c462 <SPI_DMAReceiveCplt+0x66>
}
else
{
/* Normal case */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
800c452: 68fb ldr r3, [r7, #12]
800c454: 681b ldr r3, [r3, #0]
800c456: 685a ldr r2, [r3, #4]
800c458: 68fb ldr r3, [r7, #12]
800c45a: 681b ldr r3, [r3, #0]
800c45c: f022 0201 bic.w r2, r2, #1
800c460: 605a str r2, [r3, #4]
}
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
800c462: 68ba ldr r2, [r7, #8]
800c464: 2164 movs r1, #100 @ 0x64
800c466: 68f8 ldr r0, [r7, #12]
800c468: f000 f9be bl 800c7e8 <SPI_EndRxTransaction>
800c46c: 4603 mov r3, r0
800c46e: 2b00 cmp r3, #0
800c470: d002 beq.n 800c478 <SPI_DMAReceiveCplt+0x7c>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
800c472: 68fb ldr r3, [r7, #12]
800c474: 2220 movs r2, #32
800c476: 661a str r2, [r3, #96] @ 0x60
}
hspi->RxXferCount = 0U;
800c478: 68fb ldr r3, [r7, #12]
800c47a: 2200 movs r2, #0
800c47c: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
hspi->State = HAL_SPI_STATE_READY;
800c480: 68fb ldr r3, [r7, #12]
800c482: 2201 movs r2, #1
800c484: f883 205d strb.w r2, [r3, #93] @ 0x5d
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
800c488: 68fb ldr r3, [r7, #12]
800c48a: 6e1b ldr r3, [r3, #96] @ 0x60
800c48c: 2b00 cmp r3, #0
800c48e: d003 beq.n 800c498 <SPI_DMAReceiveCplt+0x9c>
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
800c490: 68f8 ldr r0, [r7, #12]
800c492: f7ff ffa9 bl 800c3e8 <HAL_SPI_ErrorCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
800c496: e002 b.n 800c49e <SPI_DMAReceiveCplt+0xa2>
}
/* Call user Rx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->RxCpltCallback(hspi);
#else
HAL_SPI_RxCpltCallback(hspi);
800c498: 68f8 ldr r0, [r7, #12]
800c49a: f7ff ff87 bl 800c3ac <HAL_SPI_RxCpltCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
800c49e: 3710 adds r7, #16
800c4a0: 46bd mov sp, r7
800c4a2: bd80 pop {r7, pc}
0800c4a4 <SPI_DMATransmitReceiveCplt>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
800c4a4: b580 push {r7, lr}
800c4a6: b084 sub sp, #16
800c4a8: af00 add r7, sp, #0
800c4aa: 6078 str r0, [r7, #4]
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
800c4ac: 687b ldr r3, [r7, #4]
800c4ae: 6a9b ldr r3, [r3, #40] @ 0x28
800c4b0: 60fb str r3, [r7, #12]
__IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800c4b2: f7f8 ff57 bl 8005364 <HAL_GetTick>
800c4b6: 60b8 str r0, [r7, #8]
/* DMA Normal Mode */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
800c4b8: 687b ldr r3, [r7, #4]
800c4ba: 681b ldr r3, [r3, #0]
800c4bc: 681b ldr r3, [r3, #0]
800c4be: f003 0320 and.w r3, r3, #32
800c4c2: 2b20 cmp r3, #32
800c4c4: d030 beq.n 800c528 <SPI_DMATransmitReceiveCplt+0x84>
{
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
800c4c6: 68fb ldr r3, [r7, #12]
800c4c8: 681b ldr r3, [r3, #0]
800c4ca: 685a ldr r2, [r3, #4]
800c4cc: 68fb ldr r3, [r7, #12]
800c4ce: 681b ldr r3, [r3, #0]
800c4d0: f022 0220 bic.w r2, r2, #32
800c4d4: 605a str r2, [r3, #4]
}
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
800c4d6: 68ba ldr r2, [r7, #8]
800c4d8: 2164 movs r1, #100 @ 0x64
800c4da: 68f8 ldr r0, [r7, #12]
800c4dc: f000 f9dc bl 800c898 <SPI_EndRxTxTransaction>
800c4e0: 4603 mov r3, r0
800c4e2: 2b00 cmp r3, #0
800c4e4: d005 beq.n 800c4f2 <SPI_DMATransmitReceiveCplt+0x4e>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800c4e6: 68fb ldr r3, [r7, #12]
800c4e8: 6e1b ldr r3, [r3, #96] @ 0x60
800c4ea: f043 0220 orr.w r2, r3, #32
800c4ee: 68fb ldr r3, [r7, #12]
800c4f0: 661a str r2, [r3, #96] @ 0x60
}
/* Disable Rx/Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
800c4f2: 68fb ldr r3, [r7, #12]
800c4f4: 681b ldr r3, [r3, #0]
800c4f6: 685a ldr r2, [r3, #4]
800c4f8: 68fb ldr r3, [r7, #12]
800c4fa: 681b ldr r3, [r3, #0]
800c4fc: f022 0203 bic.w r2, r2, #3
800c500: 605a str r2, [r3, #4]
hspi->TxXferCount = 0U;
800c502: 68fb ldr r3, [r7, #12]
800c504: 2200 movs r2, #0
800c506: 87da strh r2, [r3, #62] @ 0x3e
hspi->RxXferCount = 0U;
800c508: 68fb ldr r3, [r7, #12]
800c50a: 2200 movs r2, #0
800c50c: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
hspi->State = HAL_SPI_STATE_READY;
800c510: 68fb ldr r3, [r7, #12]
800c512: 2201 movs r2, #1
800c514: f883 205d strb.w r2, [r3, #93] @ 0x5d
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
800c518: 68fb ldr r3, [r7, #12]
800c51a: 6e1b ldr r3, [r3, #96] @ 0x60
800c51c: 2b00 cmp r3, #0
800c51e: d003 beq.n 800c528 <SPI_DMATransmitReceiveCplt+0x84>
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
800c520: 68f8 ldr r0, [r7, #12]
800c522: f7ff ff61 bl 800c3e8 <HAL_SPI_ErrorCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
800c526: e002 b.n 800c52e <SPI_DMATransmitReceiveCplt+0x8a>
}
/* Call user TxRx complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->TxRxCpltCallback(hspi);
#else
HAL_SPI_TxRxCpltCallback(hspi);
800c528: 68f8 ldr r0, [r7, #12]
800c52a: f7f7 fef7 bl 800431c <HAL_SPI_TxRxCpltCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
800c52e: 3710 adds r7, #16
800c530: 46bd mov sp, r7
800c532: bd80 pop {r7, pc}
0800c534 <SPI_DMAHalfReceiveCplt>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
800c534: b580 push {r7, lr}
800c536: b084 sub sp, #16
800c538: af00 add r7, sp, #0
800c53a: 6078 str r0, [r7, #4]
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
800c53c: 687b ldr r3, [r7, #4]
800c53e: 6a9b ldr r3, [r3, #40] @ 0x28
800c540: 60fb str r3, [r7, #12]
/* Call user Rx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->RxHalfCpltCallback(hspi);
#else
HAL_SPI_RxHalfCpltCallback(hspi);
800c542: 68f8 ldr r0, [r7, #12]
800c544: f7ff ff3c bl 800c3c0 <HAL_SPI_RxHalfCpltCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
800c548: bf00 nop
800c54a: 3710 adds r7, #16
800c54c: 46bd mov sp, r7
800c54e: bd80 pop {r7, pc}
0800c550 <SPI_DMAHalfTransmitReceiveCplt>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
800c550: b580 push {r7, lr}
800c552: b084 sub sp, #16
800c554: af00 add r7, sp, #0
800c556: 6078 str r0, [r7, #4]
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
800c558: 687b ldr r3, [r7, #4]
800c55a: 6a9b ldr r3, [r3, #40] @ 0x28
800c55c: 60fb str r3, [r7, #12]
/* Call user TxRx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->TxRxHalfCpltCallback(hspi);
#else
HAL_SPI_TxRxHalfCpltCallback(hspi);
800c55e: 68f8 ldr r0, [r7, #12]
800c560: f7ff ff38 bl 800c3d4 <HAL_SPI_TxRxHalfCpltCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
800c564: bf00 nop
800c566: 3710 adds r7, #16
800c568: 46bd mov sp, r7
800c56a: bd80 pop {r7, pc}
0800c56c <SPI_DMAError>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
800c56c: b580 push {r7, lr}
800c56e: b084 sub sp, #16
800c570: af00 add r7, sp, #0
800c572: 6078 str r0, [r7, #4]
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
800c574: 687b ldr r3, [r7, #4]
800c576: 6a9b ldr r3, [r3, #40] @ 0x28
800c578: 60fb str r3, [r7, #12]
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
800c57a: 68fb ldr r3, [r7, #12]
800c57c: 681b ldr r3, [r3, #0]
800c57e: 685a ldr r2, [r3, #4]
800c580: 68fb ldr r3, [r7, #12]
800c582: 681b ldr r3, [r3, #0]
800c584: f022 0203 bic.w r2, r2, #3
800c588: 605a str r2, [r3, #4]
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
800c58a: 68fb ldr r3, [r7, #12]
800c58c: 6e1b ldr r3, [r3, #96] @ 0x60
800c58e: f043 0210 orr.w r2, r3, #16
800c592: 68fb ldr r3, [r7, #12]
800c594: 661a str r2, [r3, #96] @ 0x60
hspi->State = HAL_SPI_STATE_READY;
800c596: 68fb ldr r3, [r7, #12]
800c598: 2201 movs r2, #1
800c59a: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
800c59e: 68f8 ldr r0, [r7, #12]
800c5a0: f7ff ff22 bl 800c3e8 <HAL_SPI_ErrorCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
800c5a4: bf00 nop
800c5a6: 3710 adds r7, #16
800c5a8: 46bd mov sp, r7
800c5aa: bd80 pop {r7, pc}
0800c5ac <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
800c5ac: b580 push {r7, lr}
800c5ae: b088 sub sp, #32
800c5b0: af00 add r7, sp, #0
800c5b2: 60f8 str r0, [r7, #12]
800c5b4: 60b9 str r1, [r7, #8]
800c5b6: 603b str r3, [r7, #0]
800c5b8: 4613 mov r3, r2
800c5ba: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
800c5bc: f7f8 fed2 bl 8005364 <HAL_GetTick>
800c5c0: 4602 mov r2, r0
800c5c2: 6abb ldr r3, [r7, #40] @ 0x28
800c5c4: 1a9b subs r3, r3, r2
800c5c6: 683a ldr r2, [r7, #0]
800c5c8: 4413 add r3, r2
800c5ca: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
800c5cc: f7f8 feca bl 8005364 <HAL_GetTick>
800c5d0: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
800c5d2: 4b39 ldr r3, [pc, #228] @ (800c6b8 <SPI_WaitFlagStateUntilTimeout+0x10c>)
800c5d4: 681b ldr r3, [r3, #0]
800c5d6: 015b lsls r3, r3, #5
800c5d8: 0d1b lsrs r3, r3, #20
800c5da: 69fa ldr r2, [r7, #28]
800c5dc: fb02 f303 mul.w r3, r2, r3
800c5e0: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
800c5e2: e055 b.n 800c690 <SPI_WaitFlagStateUntilTimeout+0xe4>
{
if (Timeout != HAL_MAX_DELAY)
800c5e4: 683b ldr r3, [r7, #0]
800c5e6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800c5ea: d051 beq.n 800c690 <SPI_WaitFlagStateUntilTimeout+0xe4>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
800c5ec: f7f8 feba bl 8005364 <HAL_GetTick>
800c5f0: 4602 mov r2, r0
800c5f2: 69bb ldr r3, [r7, #24]
800c5f4: 1ad3 subs r3, r2, r3
800c5f6: 69fa ldr r2, [r7, #28]
800c5f8: 429a cmp r2, r3
800c5fa: d902 bls.n 800c602 <SPI_WaitFlagStateUntilTimeout+0x56>
800c5fc: 69fb ldr r3, [r7, #28]
800c5fe: 2b00 cmp r3, #0
800c600: d13d bne.n 800c67e <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
800c602: 68fb ldr r3, [r7, #12]
800c604: 681b ldr r3, [r3, #0]
800c606: 685a ldr r2, [r3, #4]
800c608: 68fb ldr r3, [r7, #12]
800c60a: 681b ldr r3, [r3, #0]
800c60c: f022 02e0 bic.w r2, r2, #224 @ 0xe0
800c610: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
800c612: 68fb ldr r3, [r7, #12]
800c614: 685b ldr r3, [r3, #4]
800c616: f5b3 7f82 cmp.w r3, #260 @ 0x104
800c61a: d111 bne.n 800c640 <SPI_WaitFlagStateUntilTimeout+0x94>
800c61c: 68fb ldr r3, [r7, #12]
800c61e: 689b ldr r3, [r3, #8]
800c620: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800c624: d004 beq.n 800c630 <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
800c626: 68fb ldr r3, [r7, #12]
800c628: 689b ldr r3, [r3, #8]
800c62a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800c62e: d107 bne.n 800c640 <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
800c630: 68fb ldr r3, [r7, #12]
800c632: 681b ldr r3, [r3, #0]
800c634: 681a ldr r2, [r3, #0]
800c636: 68fb ldr r3, [r7, #12]
800c638: 681b ldr r3, [r3, #0]
800c63a: f022 0240 bic.w r2, r2, #64 @ 0x40
800c63e: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
800c640: 68fb ldr r3, [r7, #12]
800c642: 6a9b ldr r3, [r3, #40] @ 0x28
800c644: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800c648: d10f bne.n 800c66a <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
800c64a: 68fb ldr r3, [r7, #12]
800c64c: 681b ldr r3, [r3, #0]
800c64e: 681a ldr r2, [r3, #0]
800c650: 68fb ldr r3, [r7, #12]
800c652: 681b ldr r3, [r3, #0]
800c654: f422 5200 bic.w r2, r2, #8192 @ 0x2000
800c658: 601a str r2, [r3, #0]
800c65a: 68fb ldr r3, [r7, #12]
800c65c: 681b ldr r3, [r3, #0]
800c65e: 681a ldr r2, [r3, #0]
800c660: 68fb ldr r3, [r7, #12]
800c662: 681b ldr r3, [r3, #0]
800c664: f442 5200 orr.w r2, r2, #8192 @ 0x2000
800c668: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
800c66a: 68fb ldr r3, [r7, #12]
800c66c: 2201 movs r2, #1
800c66e: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
800c672: 68fb ldr r3, [r7, #12]
800c674: 2200 movs r2, #0
800c676: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
800c67a: 2303 movs r3, #3
800c67c: e018 b.n 800c6b0 <SPI_WaitFlagStateUntilTimeout+0x104>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
800c67e: 697b ldr r3, [r7, #20]
800c680: 2b00 cmp r3, #0
800c682: d102 bne.n 800c68a <SPI_WaitFlagStateUntilTimeout+0xde>
{
tmp_timeout = 0U;
800c684: 2300 movs r3, #0
800c686: 61fb str r3, [r7, #28]
800c688: e002 b.n 800c690 <SPI_WaitFlagStateUntilTimeout+0xe4>
}
else
{
count--;
800c68a: 697b ldr r3, [r7, #20]
800c68c: 3b01 subs r3, #1
800c68e: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
800c690: 68fb ldr r3, [r7, #12]
800c692: 681b ldr r3, [r3, #0]
800c694: 689a ldr r2, [r3, #8]
800c696: 68bb ldr r3, [r7, #8]
800c698: 4013 ands r3, r2
800c69a: 68ba ldr r2, [r7, #8]
800c69c: 429a cmp r2, r3
800c69e: bf0c ite eq
800c6a0: 2301 moveq r3, #1
800c6a2: 2300 movne r3, #0
800c6a4: b2db uxtb r3, r3
800c6a6: 461a mov r2, r3
800c6a8: 79fb ldrb r3, [r7, #7]
800c6aa: 429a cmp r2, r3
800c6ac: d19a bne.n 800c5e4 <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
}
return HAL_OK;
800c6ae: 2300 movs r3, #0
}
800c6b0: 4618 mov r0, r3
800c6b2: 3720 adds r7, #32
800c6b4: 46bd mov sp, r7
800c6b6: bd80 pop {r7, pc}
800c6b8: 2000000c .word 0x2000000c
0800c6bc <SPI_WaitFifoStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
800c6bc: b580 push {r7, lr}
800c6be: b08a sub sp, #40 @ 0x28
800c6c0: af00 add r7, sp, #0
800c6c2: 60f8 str r0, [r7, #12]
800c6c4: 60b9 str r1, [r7, #8]
800c6c6: 607a str r2, [r7, #4]
800c6c8: 603b str r3, [r7, #0]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
__IO const uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
800c6ca: 2300 movs r3, #0
800c6cc: 75fb strb r3, [r7, #23]
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
800c6ce: f7f8 fe49 bl 8005364 <HAL_GetTick>
800c6d2: 4602 mov r2, r0
800c6d4: 6b3b ldr r3, [r7, #48] @ 0x30
800c6d6: 1a9b subs r3, r3, r2
800c6d8: 683a ldr r2, [r7, #0]
800c6da: 4413 add r3, r2
800c6dc: 627b str r3, [r7, #36] @ 0x24
tmp_tickstart = HAL_GetTick();
800c6de: f7f8 fe41 bl 8005364 <HAL_GetTick>
800c6e2: 6238 str r0, [r7, #32]
/* Initialize the 8bit temporary pointer */
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
800c6e4: 68fb ldr r3, [r7, #12]
800c6e6: 681b ldr r3, [r3, #0]
800c6e8: 330c adds r3, #12
800c6ea: 61fb str r3, [r7, #28]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
800c6ec: 4b3d ldr r3, [pc, #244] @ (800c7e4 <SPI_WaitFifoStateUntilTimeout+0x128>)
800c6ee: 681a ldr r2, [r3, #0]
800c6f0: 4613 mov r3, r2
800c6f2: 009b lsls r3, r3, #2
800c6f4: 4413 add r3, r2
800c6f6: 00da lsls r2, r3, #3
800c6f8: 1ad3 subs r3, r2, r3
800c6fa: 0d1b lsrs r3, r3, #20
800c6fc: 6a7a ldr r2, [r7, #36] @ 0x24
800c6fe: fb02 f303 mul.w r3, r2, r3
800c702: 61bb str r3, [r7, #24]
while ((hspi->Instance->SR & Fifo) != State)
800c704: e061 b.n 800c7ca <SPI_WaitFifoStateUntilTimeout+0x10e>
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
800c706: 68bb ldr r3, [r7, #8]
800c708: f5b3 6fc0 cmp.w r3, #1536 @ 0x600
800c70c: d107 bne.n 800c71e <SPI_WaitFifoStateUntilTimeout+0x62>
800c70e: 687b ldr r3, [r7, #4]
800c710: 2b00 cmp r3, #0
800c712: d104 bne.n 800c71e <SPI_WaitFifoStateUntilTimeout+0x62>
{
/* Flush Data Register by a blank read */
tmpreg8 = *ptmpreg8;
800c714: 69fb ldr r3, [r7, #28]
800c716: 781b ldrb r3, [r3, #0]
800c718: b2db uxtb r3, r3
800c71a: 75fb strb r3, [r7, #23]
/* To avoid GCC warning */
UNUSED(tmpreg8);
800c71c: 7dfb ldrb r3, [r7, #23]
}
if (Timeout != HAL_MAX_DELAY)
800c71e: 683b ldr r3, [r7, #0]
800c720: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800c724: d051 beq.n 800c7ca <SPI_WaitFifoStateUntilTimeout+0x10e>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
800c726: f7f8 fe1d bl 8005364 <HAL_GetTick>
800c72a: 4602 mov r2, r0
800c72c: 6a3b ldr r3, [r7, #32]
800c72e: 1ad3 subs r3, r2, r3
800c730: 6a7a ldr r2, [r7, #36] @ 0x24
800c732: 429a cmp r2, r3
800c734: d902 bls.n 800c73c <SPI_WaitFifoStateUntilTimeout+0x80>
800c736: 6a7b ldr r3, [r7, #36] @ 0x24
800c738: 2b00 cmp r3, #0
800c73a: d13d bne.n 800c7b8 <SPI_WaitFifoStateUntilTimeout+0xfc>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
800c73c: 68fb ldr r3, [r7, #12]
800c73e: 681b ldr r3, [r3, #0]
800c740: 685a ldr r2, [r3, #4]
800c742: 68fb ldr r3, [r7, #12]
800c744: 681b ldr r3, [r3, #0]
800c746: f022 02e0 bic.w r2, r2, #224 @ 0xe0
800c74a: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
800c74c: 68fb ldr r3, [r7, #12]
800c74e: 685b ldr r3, [r3, #4]
800c750: f5b3 7f82 cmp.w r3, #260 @ 0x104
800c754: d111 bne.n 800c77a <SPI_WaitFifoStateUntilTimeout+0xbe>
800c756: 68fb ldr r3, [r7, #12]
800c758: 689b ldr r3, [r3, #8]
800c75a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800c75e: d004 beq.n 800c76a <SPI_WaitFifoStateUntilTimeout+0xae>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
800c760: 68fb ldr r3, [r7, #12]
800c762: 689b ldr r3, [r3, #8]
800c764: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800c768: d107 bne.n 800c77a <SPI_WaitFifoStateUntilTimeout+0xbe>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
800c76a: 68fb ldr r3, [r7, #12]
800c76c: 681b ldr r3, [r3, #0]
800c76e: 681a ldr r2, [r3, #0]
800c770: 68fb ldr r3, [r7, #12]
800c772: 681b ldr r3, [r3, #0]
800c774: f022 0240 bic.w r2, r2, #64 @ 0x40
800c778: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
800c77a: 68fb ldr r3, [r7, #12]
800c77c: 6a9b ldr r3, [r3, #40] @ 0x28
800c77e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800c782: d10f bne.n 800c7a4 <SPI_WaitFifoStateUntilTimeout+0xe8>
{
SPI_RESET_CRC(hspi);
800c784: 68fb ldr r3, [r7, #12]
800c786: 681b ldr r3, [r3, #0]
800c788: 681a ldr r2, [r3, #0]
800c78a: 68fb ldr r3, [r7, #12]
800c78c: 681b ldr r3, [r3, #0]
800c78e: f422 5200 bic.w r2, r2, #8192 @ 0x2000
800c792: 601a str r2, [r3, #0]
800c794: 68fb ldr r3, [r7, #12]
800c796: 681b ldr r3, [r3, #0]
800c798: 681a ldr r2, [r3, #0]
800c79a: 68fb ldr r3, [r7, #12]
800c79c: 681b ldr r3, [r3, #0]
800c79e: f442 5200 orr.w r2, r2, #8192 @ 0x2000
800c7a2: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
800c7a4: 68fb ldr r3, [r7, #12]
800c7a6: 2201 movs r2, #1
800c7a8: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
800c7ac: 68fb ldr r3, [r7, #12]
800c7ae: 2200 movs r2, #0
800c7b0: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
800c7b4: 2303 movs r3, #3
800c7b6: e011 b.n 800c7dc <SPI_WaitFifoStateUntilTimeout+0x120>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
800c7b8: 69bb ldr r3, [r7, #24]
800c7ba: 2b00 cmp r3, #0
800c7bc: d102 bne.n 800c7c4 <SPI_WaitFifoStateUntilTimeout+0x108>
{
tmp_timeout = 0U;
800c7be: 2300 movs r3, #0
800c7c0: 627b str r3, [r7, #36] @ 0x24
800c7c2: e002 b.n 800c7ca <SPI_WaitFifoStateUntilTimeout+0x10e>
}
else
{
count--;
800c7c4: 69bb ldr r3, [r7, #24]
800c7c6: 3b01 subs r3, #1
800c7c8: 61bb str r3, [r7, #24]
while ((hspi->Instance->SR & Fifo) != State)
800c7ca: 68fb ldr r3, [r7, #12]
800c7cc: 681b ldr r3, [r3, #0]
800c7ce: 689a ldr r2, [r3, #8]
800c7d0: 68bb ldr r3, [r7, #8]
800c7d2: 4013 ands r3, r2
800c7d4: 687a ldr r2, [r7, #4]
800c7d6: 429a cmp r2, r3
800c7d8: d195 bne.n 800c706 <SPI_WaitFifoStateUntilTimeout+0x4a>
}
}
}
return HAL_OK;
800c7da: 2300 movs r3, #0
}
800c7dc: 4618 mov r0, r3
800c7de: 3728 adds r7, #40 @ 0x28
800c7e0: 46bd mov sp, r7
800c7e2: bd80 pop {r7, pc}
800c7e4: 2000000c .word 0x2000000c
0800c7e8 <SPI_EndRxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
800c7e8: b580 push {r7, lr}
800c7ea: b086 sub sp, #24
800c7ec: af02 add r7, sp, #8
800c7ee: 60f8 str r0, [r7, #12]
800c7f0: 60b9 str r1, [r7, #8]
800c7f2: 607a str r2, [r7, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
800c7f4: 68fb ldr r3, [r7, #12]
800c7f6: 685b ldr r3, [r3, #4]
800c7f8: f5b3 7f82 cmp.w r3, #260 @ 0x104
800c7fc: d111 bne.n 800c822 <SPI_EndRxTransaction+0x3a>
800c7fe: 68fb ldr r3, [r7, #12]
800c800: 689b ldr r3, [r3, #8]
800c802: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800c806: d004 beq.n 800c812 <SPI_EndRxTransaction+0x2a>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
800c808: 68fb ldr r3, [r7, #12]
800c80a: 689b ldr r3, [r3, #8]
800c80c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800c810: d107 bne.n 800c822 <SPI_EndRxTransaction+0x3a>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
800c812: 68fb ldr r3, [r7, #12]
800c814: 681b ldr r3, [r3, #0]
800c816: 681a ldr r2, [r3, #0]
800c818: 68fb ldr r3, [r7, #12]
800c81a: 681b ldr r3, [r3, #0]
800c81c: f022 0240 bic.w r2, r2, #64 @ 0x40
800c820: 601a str r2, [r3, #0]
}
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
800c822: 687b ldr r3, [r7, #4]
800c824: 9300 str r3, [sp, #0]
800c826: 68bb ldr r3, [r7, #8]
800c828: 2200 movs r2, #0
800c82a: 2180 movs r1, #128 @ 0x80
800c82c: 68f8 ldr r0, [r7, #12]
800c82e: f7ff febd bl 800c5ac <SPI_WaitFlagStateUntilTimeout>
800c832: 4603 mov r3, r0
800c834: 2b00 cmp r3, #0
800c836: d007 beq.n 800c848 <SPI_EndRxTransaction+0x60>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800c838: 68fb ldr r3, [r7, #12]
800c83a: 6e1b ldr r3, [r3, #96] @ 0x60
800c83c: f043 0220 orr.w r2, r3, #32
800c840: 68fb ldr r3, [r7, #12]
800c842: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
800c844: 2303 movs r3, #3
800c846: e023 b.n 800c890 <SPI_EndRxTransaction+0xa8>
}
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
800c848: 68fb ldr r3, [r7, #12]
800c84a: 685b ldr r3, [r3, #4]
800c84c: f5b3 7f82 cmp.w r3, #260 @ 0x104
800c850: d11d bne.n 800c88e <SPI_EndRxTransaction+0xa6>
800c852: 68fb ldr r3, [r7, #12]
800c854: 689b ldr r3, [r3, #8]
800c856: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800c85a: d004 beq.n 800c866 <SPI_EndRxTransaction+0x7e>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
800c85c: 68fb ldr r3, [r7, #12]
800c85e: 689b ldr r3, [r3, #8]
800c860: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800c864: d113 bne.n 800c88e <SPI_EndRxTransaction+0xa6>
{
/* Empty the FRLVL fifo */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
800c866: 687b ldr r3, [r7, #4]
800c868: 9300 str r3, [sp, #0]
800c86a: 68bb ldr r3, [r7, #8]
800c86c: 2200 movs r2, #0
800c86e: f44f 61c0 mov.w r1, #1536 @ 0x600
800c872: 68f8 ldr r0, [r7, #12]
800c874: f7ff ff22 bl 800c6bc <SPI_WaitFifoStateUntilTimeout>
800c878: 4603 mov r3, r0
800c87a: 2b00 cmp r3, #0
800c87c: d007 beq.n 800c88e <SPI_EndRxTransaction+0xa6>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800c87e: 68fb ldr r3, [r7, #12]
800c880: 6e1b ldr r3, [r3, #96] @ 0x60
800c882: f043 0220 orr.w r2, r3, #32
800c886: 68fb ldr r3, [r7, #12]
800c888: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
800c88a: 2303 movs r3, #3
800c88c: e000 b.n 800c890 <SPI_EndRxTransaction+0xa8>
}
}
return HAL_OK;
800c88e: 2300 movs r3, #0
}
800c890: 4618 mov r0, r3
800c892: 3710 adds r7, #16
800c894: 46bd mov sp, r7
800c896: bd80 pop {r7, pc}
0800c898 <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
800c898: b580 push {r7, lr}
800c89a: b086 sub sp, #24
800c89c: af02 add r7, sp, #8
800c89e: 60f8 str r0, [r7, #12]
800c8a0: 60b9 str r1, [r7, #8]
800c8a2: 607a str r2, [r7, #4]
/* Control if the TX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
800c8a4: 687b ldr r3, [r7, #4]
800c8a6: 9300 str r3, [sp, #0]
800c8a8: 68bb ldr r3, [r7, #8]
800c8aa: 2200 movs r2, #0
800c8ac: f44f 51c0 mov.w r1, #6144 @ 0x1800
800c8b0: 68f8 ldr r0, [r7, #12]
800c8b2: f7ff ff03 bl 800c6bc <SPI_WaitFifoStateUntilTimeout>
800c8b6: 4603 mov r3, r0
800c8b8: 2b00 cmp r3, #0
800c8ba: d007 beq.n 800c8cc <SPI_EndRxTxTransaction+0x34>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800c8bc: 68fb ldr r3, [r7, #12]
800c8be: 6e1b ldr r3, [r3, #96] @ 0x60
800c8c0: f043 0220 orr.w r2, r3, #32
800c8c4: 68fb ldr r3, [r7, #12]
800c8c6: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
800c8c8: 2303 movs r3, #3
800c8ca: e027 b.n 800c91c <SPI_EndRxTxTransaction+0x84>
}
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
800c8cc: 687b ldr r3, [r7, #4]
800c8ce: 9300 str r3, [sp, #0]
800c8d0: 68bb ldr r3, [r7, #8]
800c8d2: 2200 movs r2, #0
800c8d4: 2180 movs r1, #128 @ 0x80
800c8d6: 68f8 ldr r0, [r7, #12]
800c8d8: f7ff fe68 bl 800c5ac <SPI_WaitFlagStateUntilTimeout>
800c8dc: 4603 mov r3, r0
800c8de: 2b00 cmp r3, #0
800c8e0: d007 beq.n 800c8f2 <SPI_EndRxTxTransaction+0x5a>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800c8e2: 68fb ldr r3, [r7, #12]
800c8e4: 6e1b ldr r3, [r3, #96] @ 0x60
800c8e6: f043 0220 orr.w r2, r3, #32
800c8ea: 68fb ldr r3, [r7, #12]
800c8ec: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
800c8ee: 2303 movs r3, #3
800c8f0: e014 b.n 800c91c <SPI_EndRxTxTransaction+0x84>
}
/* Control if the RX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
800c8f2: 687b ldr r3, [r7, #4]
800c8f4: 9300 str r3, [sp, #0]
800c8f6: 68bb ldr r3, [r7, #8]
800c8f8: 2200 movs r2, #0
800c8fa: f44f 61c0 mov.w r1, #1536 @ 0x600
800c8fe: 68f8 ldr r0, [r7, #12]
800c900: f7ff fedc bl 800c6bc <SPI_WaitFifoStateUntilTimeout>
800c904: 4603 mov r3, r0
800c906: 2b00 cmp r3, #0
800c908: d007 beq.n 800c91a <SPI_EndRxTxTransaction+0x82>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800c90a: 68fb ldr r3, [r7, #12]
800c90c: 6e1b ldr r3, [r3, #96] @ 0x60
800c90e: f043 0220 orr.w r2, r3, #32
800c912: 68fb ldr r3, [r7, #12]
800c914: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
800c916: 2303 movs r3, #3
800c918: e000 b.n 800c91c <SPI_EndRxTxTransaction+0x84>
}
return HAL_OK;
800c91a: 2300 movs r3, #0
}
800c91c: 4618 mov r0, r3
800c91e: 3710 adds r7, #16
800c920: 46bd mov sp, r7
800c922: bd80 pop {r7, pc}
0800c924 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
800c924: b580 push {r7, lr}
800c926: b082 sub sp, #8
800c928: af00 add r7, sp, #0
800c92a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800c92c: 687b ldr r3, [r7, #4]
800c92e: 2b00 cmp r3, #0
800c930: d101 bne.n 800c936 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
800c932: 2301 movs r3, #1
800c934: e049 b.n 800c9ca <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800c936: 687b ldr r3, [r7, #4]
800c938: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
800c93c: b2db uxtb r3, r3
800c93e: 2b00 cmp r3, #0
800c940: d106 bne.n 800c950 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
800c942: 687b ldr r3, [r7, #4]
800c944: 2200 movs r2, #0
800c946: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
800c94a: 6878 ldr r0, [r7, #4]
800c94c: f000 f841 bl 800c9d2 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800c950: 687b ldr r3, [r7, #4]
800c952: 2202 movs r2, #2
800c954: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800c958: 687b ldr r3, [r7, #4]
800c95a: 681a ldr r2, [r3, #0]
800c95c: 687b ldr r3, [r7, #4]
800c95e: 3304 adds r3, #4
800c960: 4619 mov r1, r3
800c962: 4610 mov r0, r2
800c964: f000 fb28 bl 800cfb8 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800c968: 687b ldr r3, [r7, #4]
800c96a: 2201 movs r2, #1
800c96c: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800c970: 687b ldr r3, [r7, #4]
800c972: 2201 movs r2, #1
800c974: f883 203e strb.w r2, [r3, #62] @ 0x3e
800c978: 687b ldr r3, [r7, #4]
800c97a: 2201 movs r2, #1
800c97c: f883 203f strb.w r2, [r3, #63] @ 0x3f
800c980: 687b ldr r3, [r7, #4]
800c982: 2201 movs r2, #1
800c984: f883 2040 strb.w r2, [r3, #64] @ 0x40
800c988: 687b ldr r3, [r7, #4]
800c98a: 2201 movs r2, #1
800c98c: f883 2041 strb.w r2, [r3, #65] @ 0x41
800c990: 687b ldr r3, [r7, #4]
800c992: 2201 movs r2, #1
800c994: f883 2042 strb.w r2, [r3, #66] @ 0x42
800c998: 687b ldr r3, [r7, #4]
800c99a: 2201 movs r2, #1
800c99c: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800c9a0: 687b ldr r3, [r7, #4]
800c9a2: 2201 movs r2, #1
800c9a4: f883 2044 strb.w r2, [r3, #68] @ 0x44
800c9a8: 687b ldr r3, [r7, #4]
800c9aa: 2201 movs r2, #1
800c9ac: f883 2045 strb.w r2, [r3, #69] @ 0x45
800c9b0: 687b ldr r3, [r7, #4]
800c9b2: 2201 movs r2, #1
800c9b4: f883 2046 strb.w r2, [r3, #70] @ 0x46
800c9b8: 687b ldr r3, [r7, #4]
800c9ba: 2201 movs r2, #1
800c9bc: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
800c9c0: 687b ldr r3, [r7, #4]
800c9c2: 2201 movs r2, #1
800c9c4: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
800c9c8: 2300 movs r3, #0
}
800c9ca: 4618 mov r0, r3
800c9cc: 3708 adds r7, #8
800c9ce: 46bd mov sp, r7
800c9d0: bd80 pop {r7, pc}
0800c9d2 <HAL_TIM_Base_MspInit>:
* @brief Initializes the TIM Base MSP.
* @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
800c9d2: b480 push {r7}
800c9d4: b083 sub sp, #12
800c9d6: af00 add r7, sp, #0
800c9d8: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
800c9da: bf00 nop
800c9dc: 370c adds r7, #12
800c9de: 46bd mov sp, r7
800c9e0: f85d 7b04 ldr.w r7, [sp], #4
800c9e4: 4770 bx lr
...
0800c9e8 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
800c9e8: b480 push {r7}
800c9ea: b085 sub sp, #20
800c9ec: af00 add r7, sp, #0
800c9ee: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
800c9f0: 687b ldr r3, [r7, #4]
800c9f2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
800c9f6: b2db uxtb r3, r3
800c9f8: 2b01 cmp r3, #1
800c9fa: d001 beq.n 800ca00 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
800c9fc: 2301 movs r3, #1
800c9fe: e036 b.n 800ca6e <HAL_TIM_Base_Start_IT+0x86>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800ca00: 687b ldr r3, [r7, #4]
800ca02: 2202 movs r2, #2
800ca04: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
800ca08: 687b ldr r3, [r7, #4]
800ca0a: 681b ldr r3, [r3, #0]
800ca0c: 68da ldr r2, [r3, #12]
800ca0e: 687b ldr r3, [r7, #4]
800ca10: 681b ldr r3, [r3, #0]
800ca12: f042 0201 orr.w r2, r2, #1
800ca16: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800ca18: 687b ldr r3, [r7, #4]
800ca1a: 681b ldr r3, [r3, #0]
800ca1c: 4a17 ldr r2, [pc, #92] @ (800ca7c <HAL_TIM_Base_Start_IT+0x94>)
800ca1e: 4293 cmp r3, r2
800ca20: d004 beq.n 800ca2c <HAL_TIM_Base_Start_IT+0x44>
800ca22: 687b ldr r3, [r7, #4]
800ca24: 681b ldr r3, [r3, #0]
800ca26: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800ca2a: d115 bne.n 800ca58 <HAL_TIM_Base_Start_IT+0x70>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
800ca2c: 687b ldr r3, [r7, #4]
800ca2e: 681b ldr r3, [r3, #0]
800ca30: 689a ldr r2, [r3, #8]
800ca32: 4b13 ldr r3, [pc, #76] @ (800ca80 <HAL_TIM_Base_Start_IT+0x98>)
800ca34: 4013 ands r3, r2
800ca36: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800ca38: 68fb ldr r3, [r7, #12]
800ca3a: 2b06 cmp r3, #6
800ca3c: d015 beq.n 800ca6a <HAL_TIM_Base_Start_IT+0x82>
800ca3e: 68fb ldr r3, [r7, #12]
800ca40: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800ca44: d011 beq.n 800ca6a <HAL_TIM_Base_Start_IT+0x82>
{
__HAL_TIM_ENABLE(htim);
800ca46: 687b ldr r3, [r7, #4]
800ca48: 681b ldr r3, [r3, #0]
800ca4a: 681a ldr r2, [r3, #0]
800ca4c: 687b ldr r3, [r7, #4]
800ca4e: 681b ldr r3, [r3, #0]
800ca50: f042 0201 orr.w r2, r2, #1
800ca54: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800ca56: e008 b.n 800ca6a <HAL_TIM_Base_Start_IT+0x82>
}
}
else
{
__HAL_TIM_ENABLE(htim);
800ca58: 687b ldr r3, [r7, #4]
800ca5a: 681b ldr r3, [r3, #0]
800ca5c: 681a ldr r2, [r3, #0]
800ca5e: 687b ldr r3, [r7, #4]
800ca60: 681b ldr r3, [r3, #0]
800ca62: f042 0201 orr.w r2, r2, #1
800ca66: 601a str r2, [r3, #0]
800ca68: e000 b.n 800ca6c <HAL_TIM_Base_Start_IT+0x84>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800ca6a: bf00 nop
}
/* Return function status */
return HAL_OK;
800ca6c: 2300 movs r3, #0
}
800ca6e: 4618 mov r0, r3
800ca70: 3714 adds r7, #20
800ca72: 46bd mov sp, r7
800ca74: f85d 7b04 ldr.w r7, [sp], #4
800ca78: 4770 bx lr
800ca7a: bf00 nop
800ca7c: 40012c00 .word 0x40012c00
800ca80: 00010007 .word 0x00010007
0800ca84 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
800ca84: b580 push {r7, lr}
800ca86: b082 sub sp, #8
800ca88: af00 add r7, sp, #0
800ca8a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800ca8c: 687b ldr r3, [r7, #4]
800ca8e: 2b00 cmp r3, #0
800ca90: d101 bne.n 800ca96 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
800ca92: 2301 movs r3, #1
800ca94: e049 b.n 800cb2a <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800ca96: 687b ldr r3, [r7, #4]
800ca98: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
800ca9c: b2db uxtb r3, r3
800ca9e: 2b00 cmp r3, #0
800caa0: d106 bne.n 800cab0 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
800caa2: 687b ldr r3, [r7, #4]
800caa4: 2200 movs r2, #0
800caa6: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
800caaa: 6878 ldr r0, [r7, #4]
800caac: f7f8 f9ac bl 8004e08 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800cab0: 687b ldr r3, [r7, #4]
800cab2: 2202 movs r2, #2
800cab4: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800cab8: 687b ldr r3, [r7, #4]
800caba: 681a ldr r2, [r3, #0]
800cabc: 687b ldr r3, [r7, #4]
800cabe: 3304 adds r3, #4
800cac0: 4619 mov r1, r3
800cac2: 4610 mov r0, r2
800cac4: f000 fa78 bl 800cfb8 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800cac8: 687b ldr r3, [r7, #4]
800caca: 2201 movs r2, #1
800cacc: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800cad0: 687b ldr r3, [r7, #4]
800cad2: 2201 movs r2, #1
800cad4: f883 203e strb.w r2, [r3, #62] @ 0x3e
800cad8: 687b ldr r3, [r7, #4]
800cada: 2201 movs r2, #1
800cadc: f883 203f strb.w r2, [r3, #63] @ 0x3f
800cae0: 687b ldr r3, [r7, #4]
800cae2: 2201 movs r2, #1
800cae4: f883 2040 strb.w r2, [r3, #64] @ 0x40
800cae8: 687b ldr r3, [r7, #4]
800caea: 2201 movs r2, #1
800caec: f883 2041 strb.w r2, [r3, #65] @ 0x41
800caf0: 687b ldr r3, [r7, #4]
800caf2: 2201 movs r2, #1
800caf4: f883 2042 strb.w r2, [r3, #66] @ 0x42
800caf8: 687b ldr r3, [r7, #4]
800cafa: 2201 movs r2, #1
800cafc: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800cb00: 687b ldr r3, [r7, #4]
800cb02: 2201 movs r2, #1
800cb04: f883 2044 strb.w r2, [r3, #68] @ 0x44
800cb08: 687b ldr r3, [r7, #4]
800cb0a: 2201 movs r2, #1
800cb0c: f883 2045 strb.w r2, [r3, #69] @ 0x45
800cb10: 687b ldr r3, [r7, #4]
800cb12: 2201 movs r2, #1
800cb14: f883 2046 strb.w r2, [r3, #70] @ 0x46
800cb18: 687b ldr r3, [r7, #4]
800cb1a: 2201 movs r2, #1
800cb1c: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
800cb20: 687b ldr r3, [r7, #4]
800cb22: 2201 movs r2, #1
800cb24: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
800cb28: 2300 movs r3, #0
}
800cb2a: 4618 mov r0, r3
800cb2c: 3708 adds r7, #8
800cb2e: 46bd mov sp, r7
800cb30: bd80 pop {r7, pc}
0800cb32 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
800cb32: b580 push {r7, lr}
800cb34: b084 sub sp, #16
800cb36: af00 add r7, sp, #0
800cb38: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
800cb3a: 687b ldr r3, [r7, #4]
800cb3c: 681b ldr r3, [r3, #0]
800cb3e: 68db ldr r3, [r3, #12]
800cb40: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
800cb42: 687b ldr r3, [r7, #4]
800cb44: 681b ldr r3, [r3, #0]
800cb46: 691b ldr r3, [r3, #16]
800cb48: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
800cb4a: 68bb ldr r3, [r7, #8]
800cb4c: f003 0302 and.w r3, r3, #2
800cb50: 2b00 cmp r3, #0
800cb52: d020 beq.n 800cb96 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
800cb54: 68fb ldr r3, [r7, #12]
800cb56: f003 0302 and.w r3, r3, #2
800cb5a: 2b00 cmp r3, #0
800cb5c: d01b beq.n 800cb96 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
800cb5e: 687b ldr r3, [r7, #4]
800cb60: 681b ldr r3, [r3, #0]
800cb62: f06f 0202 mvn.w r2, #2
800cb66: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
800cb68: 687b ldr r3, [r7, #4]
800cb6a: 2201 movs r2, #1
800cb6c: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
800cb6e: 687b ldr r3, [r7, #4]
800cb70: 681b ldr r3, [r3, #0]
800cb72: 699b ldr r3, [r3, #24]
800cb74: f003 0303 and.w r3, r3, #3
800cb78: 2b00 cmp r3, #0
800cb7a: d003 beq.n 800cb84 <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800cb7c: 6878 ldr r0, [r7, #4]
800cb7e: f000 f9fd bl 800cf7c <HAL_TIM_IC_CaptureCallback>
800cb82: e005 b.n 800cb90 <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800cb84: 6878 ldr r0, [r7, #4]
800cb86: f000 f9ef bl 800cf68 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800cb8a: 6878 ldr r0, [r7, #4]
800cb8c: f000 fa00 bl 800cf90 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800cb90: 687b ldr r3, [r7, #4]
800cb92: 2200 movs r2, #0
800cb94: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
800cb96: 68bb ldr r3, [r7, #8]
800cb98: f003 0304 and.w r3, r3, #4
800cb9c: 2b00 cmp r3, #0
800cb9e: d020 beq.n 800cbe2 <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
800cba0: 68fb ldr r3, [r7, #12]
800cba2: f003 0304 and.w r3, r3, #4
800cba6: 2b00 cmp r3, #0
800cba8: d01b beq.n 800cbe2 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
800cbaa: 687b ldr r3, [r7, #4]
800cbac: 681b ldr r3, [r3, #0]
800cbae: f06f 0204 mvn.w r2, #4
800cbb2: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
800cbb4: 687b ldr r3, [r7, #4]
800cbb6: 2202 movs r2, #2
800cbb8: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
800cbba: 687b ldr r3, [r7, #4]
800cbbc: 681b ldr r3, [r3, #0]
800cbbe: 699b ldr r3, [r3, #24]
800cbc0: f403 7340 and.w r3, r3, #768 @ 0x300
800cbc4: 2b00 cmp r3, #0
800cbc6: d003 beq.n 800cbd0 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800cbc8: 6878 ldr r0, [r7, #4]
800cbca: f000 f9d7 bl 800cf7c <HAL_TIM_IC_CaptureCallback>
800cbce: e005 b.n 800cbdc <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800cbd0: 6878 ldr r0, [r7, #4]
800cbd2: f000 f9c9 bl 800cf68 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800cbd6: 6878 ldr r0, [r7, #4]
800cbd8: f000 f9da bl 800cf90 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800cbdc: 687b ldr r3, [r7, #4]
800cbde: 2200 movs r2, #0
800cbe0: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
800cbe2: 68bb ldr r3, [r7, #8]
800cbe4: f003 0308 and.w r3, r3, #8
800cbe8: 2b00 cmp r3, #0
800cbea: d020 beq.n 800cc2e <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
800cbec: 68fb ldr r3, [r7, #12]
800cbee: f003 0308 and.w r3, r3, #8
800cbf2: 2b00 cmp r3, #0
800cbf4: d01b beq.n 800cc2e <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
800cbf6: 687b ldr r3, [r7, #4]
800cbf8: 681b ldr r3, [r3, #0]
800cbfa: f06f 0208 mvn.w r2, #8
800cbfe: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
800cc00: 687b ldr r3, [r7, #4]
800cc02: 2204 movs r2, #4
800cc04: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
800cc06: 687b ldr r3, [r7, #4]
800cc08: 681b ldr r3, [r3, #0]
800cc0a: 69db ldr r3, [r3, #28]
800cc0c: f003 0303 and.w r3, r3, #3
800cc10: 2b00 cmp r3, #0
800cc12: d003 beq.n 800cc1c <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800cc14: 6878 ldr r0, [r7, #4]
800cc16: f000 f9b1 bl 800cf7c <HAL_TIM_IC_CaptureCallback>
800cc1a: e005 b.n 800cc28 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800cc1c: 6878 ldr r0, [r7, #4]
800cc1e: f000 f9a3 bl 800cf68 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800cc22: 6878 ldr r0, [r7, #4]
800cc24: f000 f9b4 bl 800cf90 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800cc28: 687b ldr r3, [r7, #4]
800cc2a: 2200 movs r2, #0
800cc2c: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
800cc2e: 68bb ldr r3, [r7, #8]
800cc30: f003 0310 and.w r3, r3, #16
800cc34: 2b00 cmp r3, #0
800cc36: d020 beq.n 800cc7a <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
800cc38: 68fb ldr r3, [r7, #12]
800cc3a: f003 0310 and.w r3, r3, #16
800cc3e: 2b00 cmp r3, #0
800cc40: d01b beq.n 800cc7a <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
800cc42: 687b ldr r3, [r7, #4]
800cc44: 681b ldr r3, [r3, #0]
800cc46: f06f 0210 mvn.w r2, #16
800cc4a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
800cc4c: 687b ldr r3, [r7, #4]
800cc4e: 2208 movs r2, #8
800cc50: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
800cc52: 687b ldr r3, [r7, #4]
800cc54: 681b ldr r3, [r3, #0]
800cc56: 69db ldr r3, [r3, #28]
800cc58: f403 7340 and.w r3, r3, #768 @ 0x300
800cc5c: 2b00 cmp r3, #0
800cc5e: d003 beq.n 800cc68 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800cc60: 6878 ldr r0, [r7, #4]
800cc62: f000 f98b bl 800cf7c <HAL_TIM_IC_CaptureCallback>
800cc66: e005 b.n 800cc74 <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800cc68: 6878 ldr r0, [r7, #4]
800cc6a: f000 f97d bl 800cf68 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800cc6e: 6878 ldr r0, [r7, #4]
800cc70: f000 f98e bl 800cf90 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800cc74: 687b ldr r3, [r7, #4]
800cc76: 2200 movs r2, #0
800cc78: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
800cc7a: 68bb ldr r3, [r7, #8]
800cc7c: f003 0301 and.w r3, r3, #1
800cc80: 2b00 cmp r3, #0
800cc82: d00c beq.n 800cc9e <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
800cc84: 68fb ldr r3, [r7, #12]
800cc86: f003 0301 and.w r3, r3, #1
800cc8a: 2b00 cmp r3, #0
800cc8c: d007 beq.n 800cc9e <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
800cc8e: 687b ldr r3, [r7, #4]
800cc90: 681b ldr r3, [r3, #0]
800cc92: f06f 0201 mvn.w r2, #1
800cc96: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
800cc98: 6878 ldr r0, [r7, #4]
800cc9a: f7f7 fb27 bl 80042ec <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
800cc9e: 68bb ldr r3, [r7, #8]
800cca0: f003 0380 and.w r3, r3, #128 @ 0x80
800cca4: 2b00 cmp r3, #0
800cca6: d104 bne.n 800ccb2 <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
800cca8: 68bb ldr r3, [r7, #8]
800ccaa: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
800ccae: 2b00 cmp r3, #0
800ccb0: d00c beq.n 800cccc <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
800ccb2: 68fb ldr r3, [r7, #12]
800ccb4: f003 0380 and.w r3, r3, #128 @ 0x80
800ccb8: 2b00 cmp r3, #0
800ccba: d007 beq.n 800cccc <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
800ccbc: 687b ldr r3, [r7, #4]
800ccbe: 681b ldr r3, [r3, #0]
800ccc0: f46f 5202 mvn.w r2, #8320 @ 0x2080
800ccc4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
800ccc6: 6878 ldr r0, [r7, #4]
800ccc8: f000 fcce bl 800d668 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
800cccc: 68bb ldr r3, [r7, #8]
800ccce: f403 7380 and.w r3, r3, #256 @ 0x100
800ccd2: 2b00 cmp r3, #0
800ccd4: d00c beq.n 800ccf0 <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
800ccd6: 68fb ldr r3, [r7, #12]
800ccd8: f003 0380 and.w r3, r3, #128 @ 0x80
800ccdc: 2b00 cmp r3, #0
800ccde: d007 beq.n 800ccf0 <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
800cce0: 687b ldr r3, [r7, #4]
800cce2: 681b ldr r3, [r3, #0]
800cce4: f46f 7280 mvn.w r2, #256 @ 0x100
800cce8: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
800ccea: 6878 ldr r0, [r7, #4]
800ccec: f000 fcc6 bl 800d67c <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
800ccf0: 68bb ldr r3, [r7, #8]
800ccf2: f003 0340 and.w r3, r3, #64 @ 0x40
800ccf6: 2b00 cmp r3, #0
800ccf8: d00c beq.n 800cd14 <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
800ccfa: 68fb ldr r3, [r7, #12]
800ccfc: f003 0340 and.w r3, r3, #64 @ 0x40
800cd00: 2b00 cmp r3, #0
800cd02: d007 beq.n 800cd14 <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
800cd04: 687b ldr r3, [r7, #4]
800cd06: 681b ldr r3, [r3, #0]
800cd08: f06f 0240 mvn.w r2, #64 @ 0x40
800cd0c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
800cd0e: 6878 ldr r0, [r7, #4]
800cd10: f000 f948 bl 800cfa4 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
800cd14: 68bb ldr r3, [r7, #8]
800cd16: f003 0320 and.w r3, r3, #32
800cd1a: 2b00 cmp r3, #0
800cd1c: d00c beq.n 800cd38 <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
800cd1e: 68fb ldr r3, [r7, #12]
800cd20: f003 0320 and.w r3, r3, #32
800cd24: 2b00 cmp r3, #0
800cd26: d007 beq.n 800cd38 <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
800cd28: 687b ldr r3, [r7, #4]
800cd2a: 681b ldr r3, [r3, #0]
800cd2c: f06f 0220 mvn.w r2, #32
800cd30: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
800cd32: 6878 ldr r0, [r7, #4]
800cd34: f000 fc8e bl 800d654 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
800cd38: bf00 nop
800cd3a: 3710 adds r7, #16
800cd3c: 46bd mov sp, r7
800cd3e: bd80 pop {r7, pc}
0800cd40 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
800cd40: b580 push {r7, lr}
800cd42: b086 sub sp, #24
800cd44: af00 add r7, sp, #0
800cd46: 60f8 str r0, [r7, #12]
800cd48: 60b9 str r1, [r7, #8]
800cd4a: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800cd4c: 2300 movs r3, #0
800cd4e: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
800cd50: 68fb ldr r3, [r7, #12]
800cd52: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800cd56: 2b01 cmp r3, #1
800cd58: d101 bne.n 800cd5e <HAL_TIM_PWM_ConfigChannel+0x1e>
800cd5a: 2302 movs r3, #2
800cd5c: e0ff b.n 800cf5e <HAL_TIM_PWM_ConfigChannel+0x21e>
800cd5e: 68fb ldr r3, [r7, #12]
800cd60: 2201 movs r2, #1
800cd62: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
800cd66: 687b ldr r3, [r7, #4]
800cd68: 2b14 cmp r3, #20
800cd6a: f200 80f0 bhi.w 800cf4e <HAL_TIM_PWM_ConfigChannel+0x20e>
800cd6e: a201 add r2, pc, #4 @ (adr r2, 800cd74 <HAL_TIM_PWM_ConfigChannel+0x34>)
800cd70: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800cd74: 0800cdc9 .word 0x0800cdc9
800cd78: 0800cf4f .word 0x0800cf4f
800cd7c: 0800cf4f .word 0x0800cf4f
800cd80: 0800cf4f .word 0x0800cf4f
800cd84: 0800ce09 .word 0x0800ce09
800cd88: 0800cf4f .word 0x0800cf4f
800cd8c: 0800cf4f .word 0x0800cf4f
800cd90: 0800cf4f .word 0x0800cf4f
800cd94: 0800ce4b .word 0x0800ce4b
800cd98: 0800cf4f .word 0x0800cf4f
800cd9c: 0800cf4f .word 0x0800cf4f
800cda0: 0800cf4f .word 0x0800cf4f
800cda4: 0800ce8b .word 0x0800ce8b
800cda8: 0800cf4f .word 0x0800cf4f
800cdac: 0800cf4f .word 0x0800cf4f
800cdb0: 0800cf4f .word 0x0800cf4f
800cdb4: 0800cecd .word 0x0800cecd
800cdb8: 0800cf4f .word 0x0800cf4f
800cdbc: 0800cf4f .word 0x0800cf4f
800cdc0: 0800cf4f .word 0x0800cf4f
800cdc4: 0800cf0d .word 0x0800cf0d
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
800cdc8: 68fb ldr r3, [r7, #12]
800cdca: 681b ldr r3, [r3, #0]
800cdcc: 68b9 ldr r1, [r7, #8]
800cdce: 4618 mov r0, r3
800cdd0: f000 f95c bl 800d08c <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
800cdd4: 68fb ldr r3, [r7, #12]
800cdd6: 681b ldr r3, [r3, #0]
800cdd8: 699a ldr r2, [r3, #24]
800cdda: 68fb ldr r3, [r7, #12]
800cddc: 681b ldr r3, [r3, #0]
800cdde: f042 0208 orr.w r2, r2, #8
800cde2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
800cde4: 68fb ldr r3, [r7, #12]
800cde6: 681b ldr r3, [r3, #0]
800cde8: 699a ldr r2, [r3, #24]
800cdea: 68fb ldr r3, [r7, #12]
800cdec: 681b ldr r3, [r3, #0]
800cdee: f022 0204 bic.w r2, r2, #4
800cdf2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
800cdf4: 68fb ldr r3, [r7, #12]
800cdf6: 681b ldr r3, [r3, #0]
800cdf8: 6999 ldr r1, [r3, #24]
800cdfa: 68bb ldr r3, [r7, #8]
800cdfc: 691a ldr r2, [r3, #16]
800cdfe: 68fb ldr r3, [r7, #12]
800ce00: 681b ldr r3, [r3, #0]
800ce02: 430a orrs r2, r1
800ce04: 619a str r2, [r3, #24]
break;
800ce06: e0a5 b.n 800cf54 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
800ce08: 68fb ldr r3, [r7, #12]
800ce0a: 681b ldr r3, [r3, #0]
800ce0c: 68b9 ldr r1, [r7, #8]
800ce0e: 4618 mov r0, r3
800ce10: f000 f9ba bl 800d188 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
800ce14: 68fb ldr r3, [r7, #12]
800ce16: 681b ldr r3, [r3, #0]
800ce18: 699a ldr r2, [r3, #24]
800ce1a: 68fb ldr r3, [r7, #12]
800ce1c: 681b ldr r3, [r3, #0]
800ce1e: f442 6200 orr.w r2, r2, #2048 @ 0x800
800ce22: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
800ce24: 68fb ldr r3, [r7, #12]
800ce26: 681b ldr r3, [r3, #0]
800ce28: 699a ldr r2, [r3, #24]
800ce2a: 68fb ldr r3, [r7, #12]
800ce2c: 681b ldr r3, [r3, #0]
800ce2e: f422 6280 bic.w r2, r2, #1024 @ 0x400
800ce32: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
800ce34: 68fb ldr r3, [r7, #12]
800ce36: 681b ldr r3, [r3, #0]
800ce38: 6999 ldr r1, [r3, #24]
800ce3a: 68bb ldr r3, [r7, #8]
800ce3c: 691b ldr r3, [r3, #16]
800ce3e: 021a lsls r2, r3, #8
800ce40: 68fb ldr r3, [r7, #12]
800ce42: 681b ldr r3, [r3, #0]
800ce44: 430a orrs r2, r1
800ce46: 619a str r2, [r3, #24]
break;
800ce48: e084 b.n 800cf54 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
800ce4a: 68fb ldr r3, [r7, #12]
800ce4c: 681b ldr r3, [r3, #0]
800ce4e: 68b9 ldr r1, [r7, #8]
800ce50: 4618 mov r0, r3
800ce52: f000 fa15 bl 800d280 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800ce56: 68fb ldr r3, [r7, #12]
800ce58: 681b ldr r3, [r3, #0]
800ce5a: 69da ldr r2, [r3, #28]
800ce5c: 68fb ldr r3, [r7, #12]
800ce5e: 681b ldr r3, [r3, #0]
800ce60: f042 0208 orr.w r2, r2, #8
800ce64: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800ce66: 68fb ldr r3, [r7, #12]
800ce68: 681b ldr r3, [r3, #0]
800ce6a: 69da ldr r2, [r3, #28]
800ce6c: 68fb ldr r3, [r7, #12]
800ce6e: 681b ldr r3, [r3, #0]
800ce70: f022 0204 bic.w r2, r2, #4
800ce74: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800ce76: 68fb ldr r3, [r7, #12]
800ce78: 681b ldr r3, [r3, #0]
800ce7a: 69d9 ldr r1, [r3, #28]
800ce7c: 68bb ldr r3, [r7, #8]
800ce7e: 691a ldr r2, [r3, #16]
800ce80: 68fb ldr r3, [r7, #12]
800ce82: 681b ldr r3, [r3, #0]
800ce84: 430a orrs r2, r1
800ce86: 61da str r2, [r3, #28]
break;
800ce88: e064 b.n 800cf54 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800ce8a: 68fb ldr r3, [r7, #12]
800ce8c: 681b ldr r3, [r3, #0]
800ce8e: 68b9 ldr r1, [r7, #8]
800ce90: 4618 mov r0, r3
800ce92: f000 fa6f bl 800d374 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800ce96: 68fb ldr r3, [r7, #12]
800ce98: 681b ldr r3, [r3, #0]
800ce9a: 69da ldr r2, [r3, #28]
800ce9c: 68fb ldr r3, [r7, #12]
800ce9e: 681b ldr r3, [r3, #0]
800cea0: f442 6200 orr.w r2, r2, #2048 @ 0x800
800cea4: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
800cea6: 68fb ldr r3, [r7, #12]
800cea8: 681b ldr r3, [r3, #0]
800ceaa: 69da ldr r2, [r3, #28]
800ceac: 68fb ldr r3, [r7, #12]
800ceae: 681b ldr r3, [r3, #0]
800ceb0: f422 6280 bic.w r2, r2, #1024 @ 0x400
800ceb4: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800ceb6: 68fb ldr r3, [r7, #12]
800ceb8: 681b ldr r3, [r3, #0]
800ceba: 69d9 ldr r1, [r3, #28]
800cebc: 68bb ldr r3, [r7, #8]
800cebe: 691b ldr r3, [r3, #16]
800cec0: 021a lsls r2, r3, #8
800cec2: 68fb ldr r3, [r7, #12]
800cec4: 681b ldr r3, [r3, #0]
800cec6: 430a orrs r2, r1
800cec8: 61da str r2, [r3, #28]
break;
800ceca: e043 b.n 800cf54 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
800cecc: 68fb ldr r3, [r7, #12]
800cece: 681b ldr r3, [r3, #0]
800ced0: 68b9 ldr r1, [r7, #8]
800ced2: 4618 mov r0, r3
800ced4: f000 faac bl 800d430 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
800ced8: 68fb ldr r3, [r7, #12]
800ceda: 681b ldr r3, [r3, #0]
800cedc: 6d5a ldr r2, [r3, #84] @ 0x54
800cede: 68fb ldr r3, [r7, #12]
800cee0: 681b ldr r3, [r3, #0]
800cee2: f042 0208 orr.w r2, r2, #8
800cee6: 655a str r2, [r3, #84] @ 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
800cee8: 68fb ldr r3, [r7, #12]
800ceea: 681b ldr r3, [r3, #0]
800ceec: 6d5a ldr r2, [r3, #84] @ 0x54
800ceee: 68fb ldr r3, [r7, #12]
800cef0: 681b ldr r3, [r3, #0]
800cef2: f022 0204 bic.w r2, r2, #4
800cef6: 655a str r2, [r3, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
800cef8: 68fb ldr r3, [r7, #12]
800cefa: 681b ldr r3, [r3, #0]
800cefc: 6d59 ldr r1, [r3, #84] @ 0x54
800cefe: 68bb ldr r3, [r7, #8]
800cf00: 691a ldr r2, [r3, #16]
800cf02: 68fb ldr r3, [r7, #12]
800cf04: 681b ldr r3, [r3, #0]
800cf06: 430a orrs r2, r1
800cf08: 655a str r2, [r3, #84] @ 0x54
break;
800cf0a: e023 b.n 800cf54 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
800cf0c: 68fb ldr r3, [r7, #12]
800cf0e: 681b ldr r3, [r3, #0]
800cf10: 68b9 ldr r1, [r7, #8]
800cf12: 4618 mov r0, r3
800cf14: f000 fae4 bl 800d4e0 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
800cf18: 68fb ldr r3, [r7, #12]
800cf1a: 681b ldr r3, [r3, #0]
800cf1c: 6d5a ldr r2, [r3, #84] @ 0x54
800cf1e: 68fb ldr r3, [r7, #12]
800cf20: 681b ldr r3, [r3, #0]
800cf22: f442 6200 orr.w r2, r2, #2048 @ 0x800
800cf26: 655a str r2, [r3, #84] @ 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
800cf28: 68fb ldr r3, [r7, #12]
800cf2a: 681b ldr r3, [r3, #0]
800cf2c: 6d5a ldr r2, [r3, #84] @ 0x54
800cf2e: 68fb ldr r3, [r7, #12]
800cf30: 681b ldr r3, [r3, #0]
800cf32: f422 6280 bic.w r2, r2, #1024 @ 0x400
800cf36: 655a str r2, [r3, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
800cf38: 68fb ldr r3, [r7, #12]
800cf3a: 681b ldr r3, [r3, #0]
800cf3c: 6d59 ldr r1, [r3, #84] @ 0x54
800cf3e: 68bb ldr r3, [r7, #8]
800cf40: 691b ldr r3, [r3, #16]
800cf42: 021a lsls r2, r3, #8
800cf44: 68fb ldr r3, [r7, #12]
800cf46: 681b ldr r3, [r3, #0]
800cf48: 430a orrs r2, r1
800cf4a: 655a str r2, [r3, #84] @ 0x54
break;
800cf4c: e002 b.n 800cf54 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
status = HAL_ERROR;
800cf4e: 2301 movs r3, #1
800cf50: 75fb strb r3, [r7, #23]
break;
800cf52: bf00 nop
}
__HAL_UNLOCK(htim);
800cf54: 68fb ldr r3, [r7, #12]
800cf56: 2200 movs r2, #0
800cf58: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
800cf5c: 7dfb ldrb r3, [r7, #23]
}
800cf5e: 4618 mov r0, r3
800cf60: 3718 adds r7, #24
800cf62: 46bd mov sp, r7
800cf64: bd80 pop {r7, pc}
800cf66: bf00 nop
0800cf68 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
800cf68: b480 push {r7}
800cf6a: b083 sub sp, #12
800cf6c: af00 add r7, sp, #0
800cf6e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
800cf70: bf00 nop
800cf72: 370c adds r7, #12
800cf74: 46bd mov sp, r7
800cf76: f85d 7b04 ldr.w r7, [sp], #4
800cf7a: 4770 bx lr
0800cf7c <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
800cf7c: b480 push {r7}
800cf7e: b083 sub sp, #12
800cf80: af00 add r7, sp, #0
800cf82: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
800cf84: bf00 nop
800cf86: 370c adds r7, #12
800cf88: 46bd mov sp, r7
800cf8a: f85d 7b04 ldr.w r7, [sp], #4
800cf8e: 4770 bx lr
0800cf90 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
800cf90: b480 push {r7}
800cf92: b083 sub sp, #12
800cf94: af00 add r7, sp, #0
800cf96: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
800cf98: bf00 nop
800cf9a: 370c adds r7, #12
800cf9c: 46bd mov sp, r7
800cf9e: f85d 7b04 ldr.w r7, [sp], #4
800cfa2: 4770 bx lr
0800cfa4 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
800cfa4: b480 push {r7}
800cfa6: b083 sub sp, #12
800cfa8: af00 add r7, sp, #0
800cfaa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800cfac: bf00 nop
800cfae: 370c adds r7, #12
800cfb0: 46bd mov sp, r7
800cfb2: f85d 7b04 ldr.w r7, [sp], #4
800cfb6: 4770 bx lr
0800cfb8 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
800cfb8: b480 push {r7}
800cfba: b085 sub sp, #20
800cfbc: af00 add r7, sp, #0
800cfbe: 6078 str r0, [r7, #4]
800cfc0: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800cfc2: 687b ldr r3, [r7, #4]
800cfc4: 681b ldr r3, [r3, #0]
800cfc6: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800cfc8: 687b ldr r3, [r7, #4]
800cfca: 4a2d ldr r2, [pc, #180] @ (800d080 <TIM_Base_SetConfig+0xc8>)
800cfcc: 4293 cmp r3, r2
800cfce: d003 beq.n 800cfd8 <TIM_Base_SetConfig+0x20>
800cfd0: 687b ldr r3, [r7, #4]
800cfd2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800cfd6: d108 bne.n 800cfea <TIM_Base_SetConfig+0x32>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800cfd8: 68fb ldr r3, [r7, #12]
800cfda: f023 0370 bic.w r3, r3, #112 @ 0x70
800cfde: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
800cfe0: 683b ldr r3, [r7, #0]
800cfe2: 685b ldr r3, [r3, #4]
800cfe4: 68fa ldr r2, [r7, #12]
800cfe6: 4313 orrs r3, r2
800cfe8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800cfea: 687b ldr r3, [r7, #4]
800cfec: 4a24 ldr r2, [pc, #144] @ (800d080 <TIM_Base_SetConfig+0xc8>)
800cfee: 4293 cmp r3, r2
800cff0: d00b beq.n 800d00a <TIM_Base_SetConfig+0x52>
800cff2: 687b ldr r3, [r7, #4]
800cff4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800cff8: d007 beq.n 800d00a <TIM_Base_SetConfig+0x52>
800cffa: 687b ldr r3, [r7, #4]
800cffc: 4a21 ldr r2, [pc, #132] @ (800d084 <TIM_Base_SetConfig+0xcc>)
800cffe: 4293 cmp r3, r2
800d000: d003 beq.n 800d00a <TIM_Base_SetConfig+0x52>
800d002: 687b ldr r3, [r7, #4]
800d004: 4a20 ldr r2, [pc, #128] @ (800d088 <TIM_Base_SetConfig+0xd0>)
800d006: 4293 cmp r3, r2
800d008: d108 bne.n 800d01c <TIM_Base_SetConfig+0x64>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800d00a: 68fb ldr r3, [r7, #12]
800d00c: f423 7340 bic.w r3, r3, #768 @ 0x300
800d010: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800d012: 683b ldr r3, [r7, #0]
800d014: 68db ldr r3, [r3, #12]
800d016: 68fa ldr r2, [r7, #12]
800d018: 4313 orrs r3, r2
800d01a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800d01c: 68fb ldr r3, [r7, #12]
800d01e: f023 0280 bic.w r2, r3, #128 @ 0x80
800d022: 683b ldr r3, [r7, #0]
800d024: 695b ldr r3, [r3, #20]
800d026: 4313 orrs r3, r2
800d028: 60fb str r3, [r7, #12]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
800d02a: 683b ldr r3, [r7, #0]
800d02c: 689a ldr r2, [r3, #8]
800d02e: 687b ldr r3, [r7, #4]
800d030: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
800d032: 683b ldr r3, [r7, #0]
800d034: 681a ldr r2, [r3, #0]
800d036: 687b ldr r3, [r7, #4]
800d038: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
800d03a: 687b ldr r3, [r7, #4]
800d03c: 4a10 ldr r2, [pc, #64] @ (800d080 <TIM_Base_SetConfig+0xc8>)
800d03e: 4293 cmp r3, r2
800d040: d007 beq.n 800d052 <TIM_Base_SetConfig+0x9a>
800d042: 687b ldr r3, [r7, #4]
800d044: 4a0f ldr r2, [pc, #60] @ (800d084 <TIM_Base_SetConfig+0xcc>)
800d046: 4293 cmp r3, r2
800d048: d003 beq.n 800d052 <TIM_Base_SetConfig+0x9a>
800d04a: 687b ldr r3, [r7, #4]
800d04c: 4a0e ldr r2, [pc, #56] @ (800d088 <TIM_Base_SetConfig+0xd0>)
800d04e: 4293 cmp r3, r2
800d050: d103 bne.n 800d05a <TIM_Base_SetConfig+0xa2>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
800d052: 683b ldr r3, [r7, #0]
800d054: 691a ldr r2, [r3, #16]
800d056: 687b ldr r3, [r7, #4]
800d058: 631a str r2, [r3, #48] @ 0x30
}
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
800d05a: 687b ldr r3, [r7, #4]
800d05c: 681b ldr r3, [r3, #0]
800d05e: f043 0204 orr.w r2, r3, #4
800d062: 687b ldr r3, [r7, #4]
800d064: 601a str r2, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800d066: 687b ldr r3, [r7, #4]
800d068: 2201 movs r2, #1
800d06a: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
800d06c: 687b ldr r3, [r7, #4]
800d06e: 68fa ldr r2, [r7, #12]
800d070: 601a str r2, [r3, #0]
}
800d072: bf00 nop
800d074: 3714 adds r7, #20
800d076: 46bd mov sp, r7
800d078: f85d 7b04 ldr.w r7, [sp], #4
800d07c: 4770 bx lr
800d07e: bf00 nop
800d080: 40012c00 .word 0x40012c00
800d084: 40014400 .word 0x40014400
800d088: 40014800 .word 0x40014800
0800d08c <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800d08c: b480 push {r7}
800d08e: b087 sub sp, #28
800d090: af00 add r7, sp, #0
800d092: 6078 str r0, [r7, #4]
800d094: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800d096: 687b ldr r3, [r7, #4]
800d098: 6a1b ldr r3, [r3, #32]
800d09a: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
800d09c: 687b ldr r3, [r7, #4]
800d09e: 6a1b ldr r3, [r3, #32]
800d0a0: f023 0201 bic.w r2, r3, #1
800d0a4: 687b ldr r3, [r7, #4]
800d0a6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800d0a8: 687b ldr r3, [r7, #4]
800d0aa: 685b ldr r3, [r3, #4]
800d0ac: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800d0ae: 687b ldr r3, [r7, #4]
800d0b0: 699b ldr r3, [r3, #24]
800d0b2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
800d0b4: 68fb ldr r3, [r7, #12]
800d0b6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800d0ba: f023 0370 bic.w r3, r3, #112 @ 0x70
800d0be: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
800d0c0: 68fb ldr r3, [r7, #12]
800d0c2: f023 0303 bic.w r3, r3, #3
800d0c6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800d0c8: 683b ldr r3, [r7, #0]
800d0ca: 681b ldr r3, [r3, #0]
800d0cc: 68fa ldr r2, [r7, #12]
800d0ce: 4313 orrs r3, r2
800d0d0: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800d0d2: 697b ldr r3, [r7, #20]
800d0d4: f023 0302 bic.w r3, r3, #2
800d0d8: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800d0da: 683b ldr r3, [r7, #0]
800d0dc: 689b ldr r3, [r3, #8]
800d0de: 697a ldr r2, [r7, #20]
800d0e0: 4313 orrs r3, r2
800d0e2: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
800d0e4: 687b ldr r3, [r7, #4]
800d0e6: 4a25 ldr r2, [pc, #148] @ (800d17c <TIM_OC1_SetConfig+0xf0>)
800d0e8: 4293 cmp r3, r2
800d0ea: d007 beq.n 800d0fc <TIM_OC1_SetConfig+0x70>
800d0ec: 687b ldr r3, [r7, #4]
800d0ee: 4a24 ldr r2, [pc, #144] @ (800d180 <TIM_OC1_SetConfig+0xf4>)
800d0f0: 4293 cmp r3, r2
800d0f2: d003 beq.n 800d0fc <TIM_OC1_SetConfig+0x70>
800d0f4: 687b ldr r3, [r7, #4]
800d0f6: 4a23 ldr r2, [pc, #140] @ (800d184 <TIM_OC1_SetConfig+0xf8>)
800d0f8: 4293 cmp r3, r2
800d0fa: d10e bne.n 800d11a <TIM_OC1_SetConfig+0x8e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Disable the Channel 1N: Reset the CC1NE Bit */
TIMx->CCER &= ~TIM_CCER_CC1NE;
800d0fc: 687b ldr r3, [r7, #4]
800d0fe: 6a1b ldr r3, [r3, #32]
800d100: f023 0204 bic.w r2, r3, #4
800d104: 687b ldr r3, [r7, #4]
800d106: 621a str r2, [r3, #32]
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
800d108: 697b ldr r3, [r7, #20]
800d10a: f023 0308 bic.w r3, r3, #8
800d10e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
800d110: 683b ldr r3, [r7, #0]
800d112: 68db ldr r3, [r3, #12]
800d114: 697a ldr r2, [r7, #20]
800d116: 4313 orrs r3, r2
800d118: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800d11a: 687b ldr r3, [r7, #4]
800d11c: 4a17 ldr r2, [pc, #92] @ (800d17c <TIM_OC1_SetConfig+0xf0>)
800d11e: 4293 cmp r3, r2
800d120: d007 beq.n 800d132 <TIM_OC1_SetConfig+0xa6>
800d122: 687b ldr r3, [r7, #4]
800d124: 4a17 ldr r2, [pc, #92] @ (800d184 <TIM_OC1_SetConfig+0xf8>)
800d126: 4293 cmp r3, r2
800d128: d003 beq.n 800d132 <TIM_OC1_SetConfig+0xa6>
800d12a: 687b ldr r3, [r7, #4]
800d12c: 4a14 ldr r2, [pc, #80] @ (800d180 <TIM_OC1_SetConfig+0xf4>)
800d12e: 4293 cmp r3, r2
800d130: d111 bne.n 800d156 <TIM_OC1_SetConfig+0xca>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
800d132: 693b ldr r3, [r7, #16]
800d134: f423 7380 bic.w r3, r3, #256 @ 0x100
800d138: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800d13a: 693b ldr r3, [r7, #16]
800d13c: f423 7300 bic.w r3, r3, #512 @ 0x200
800d140: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
800d142: 683b ldr r3, [r7, #0]
800d144: 695b ldr r3, [r3, #20]
800d146: 693a ldr r2, [r7, #16]
800d148: 4313 orrs r3, r2
800d14a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
800d14c: 683b ldr r3, [r7, #0]
800d14e: 699b ldr r3, [r3, #24]
800d150: 693a ldr r2, [r7, #16]
800d152: 4313 orrs r3, r2
800d154: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800d156: 687b ldr r3, [r7, #4]
800d158: 693a ldr r2, [r7, #16]
800d15a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800d15c: 687b ldr r3, [r7, #4]
800d15e: 68fa ldr r2, [r7, #12]
800d160: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
800d162: 683b ldr r3, [r7, #0]
800d164: 685a ldr r2, [r3, #4]
800d166: 687b ldr r3, [r7, #4]
800d168: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800d16a: 687b ldr r3, [r7, #4]
800d16c: 697a ldr r2, [r7, #20]
800d16e: 621a str r2, [r3, #32]
}
800d170: bf00 nop
800d172: 371c adds r7, #28
800d174: 46bd mov sp, r7
800d176: f85d 7b04 ldr.w r7, [sp], #4
800d17a: 4770 bx lr
800d17c: 40012c00 .word 0x40012c00
800d180: 40014800 .word 0x40014800
800d184: 40014400 .word 0x40014400
0800d188 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800d188: b480 push {r7}
800d18a: b087 sub sp, #28
800d18c: af00 add r7, sp, #0
800d18e: 6078 str r0, [r7, #4]
800d190: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800d192: 687b ldr r3, [r7, #4]
800d194: 6a1b ldr r3, [r3, #32]
800d196: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800d198: 687b ldr r3, [r7, #4]
800d19a: 6a1b ldr r3, [r3, #32]
800d19c: f023 0210 bic.w r2, r3, #16
800d1a0: 687b ldr r3, [r7, #4]
800d1a2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800d1a4: 687b ldr r3, [r7, #4]
800d1a6: 685b ldr r3, [r3, #4]
800d1a8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800d1aa: 687b ldr r3, [r7, #4]
800d1ac: 699b ldr r3, [r3, #24]
800d1ae: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
800d1b0: 68fb ldr r3, [r7, #12]
800d1b2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800d1b6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800d1ba: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
800d1bc: 68fb ldr r3, [r7, #12]
800d1be: f423 7340 bic.w r3, r3, #768 @ 0x300
800d1c2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800d1c4: 683b ldr r3, [r7, #0]
800d1c6: 681b ldr r3, [r3, #0]
800d1c8: 021b lsls r3, r3, #8
800d1ca: 68fa ldr r2, [r7, #12]
800d1cc: 4313 orrs r3, r2
800d1ce: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
800d1d0: 697b ldr r3, [r7, #20]
800d1d2: f023 0320 bic.w r3, r3, #32
800d1d6: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
800d1d8: 683b ldr r3, [r7, #0]
800d1da: 689b ldr r3, [r3, #8]
800d1dc: 011b lsls r3, r3, #4
800d1de: 697a ldr r2, [r7, #20]
800d1e0: 4313 orrs r3, r2
800d1e2: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800d1e4: 687b ldr r3, [r7, #4]
800d1e6: 4a23 ldr r2, [pc, #140] @ (800d274 <TIM_OC2_SetConfig+0xec>)
800d1e8: 4293 cmp r3, r2
800d1ea: d10f bne.n 800d20c <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Disable the Channel 2N: Reset the CC2NE Bit */
TIMx->CCER &= ~TIM_CCER_CC2NE;
800d1ec: 687b ldr r3, [r7, #4]
800d1ee: 6a1b ldr r3, [r3, #32]
800d1f0: f023 0240 bic.w r2, r3, #64 @ 0x40
800d1f4: 687b ldr r3, [r7, #4]
800d1f6: 621a str r2, [r3, #32]
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
800d1f8: 697b ldr r3, [r7, #20]
800d1fa: f023 0380 bic.w r3, r3, #128 @ 0x80
800d1fe: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
800d200: 683b ldr r3, [r7, #0]
800d202: 68db ldr r3, [r3, #12]
800d204: 011b lsls r3, r3, #4
800d206: 697a ldr r2, [r7, #20]
800d208: 4313 orrs r3, r2
800d20a: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800d20c: 687b ldr r3, [r7, #4]
800d20e: 4a19 ldr r2, [pc, #100] @ (800d274 <TIM_OC2_SetConfig+0xec>)
800d210: 4293 cmp r3, r2
800d212: d007 beq.n 800d224 <TIM_OC2_SetConfig+0x9c>
800d214: 687b ldr r3, [r7, #4]
800d216: 4a18 ldr r2, [pc, #96] @ (800d278 <TIM_OC2_SetConfig+0xf0>)
800d218: 4293 cmp r3, r2
800d21a: d003 beq.n 800d224 <TIM_OC2_SetConfig+0x9c>
800d21c: 687b ldr r3, [r7, #4]
800d21e: 4a17 ldr r2, [pc, #92] @ (800d27c <TIM_OC2_SetConfig+0xf4>)
800d220: 4293 cmp r3, r2
800d222: d113 bne.n 800d24c <TIM_OC2_SetConfig+0xc4>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
800d224: 693b ldr r3, [r7, #16]
800d226: f423 6380 bic.w r3, r3, #1024 @ 0x400
800d22a: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
800d22c: 693b ldr r3, [r7, #16]
800d22e: f423 6300 bic.w r3, r3, #2048 @ 0x800
800d232: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
800d234: 683b ldr r3, [r7, #0]
800d236: 695b ldr r3, [r3, #20]
800d238: 009b lsls r3, r3, #2
800d23a: 693a ldr r2, [r7, #16]
800d23c: 4313 orrs r3, r2
800d23e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
800d240: 683b ldr r3, [r7, #0]
800d242: 699b ldr r3, [r3, #24]
800d244: 009b lsls r3, r3, #2
800d246: 693a ldr r2, [r7, #16]
800d248: 4313 orrs r3, r2
800d24a: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800d24c: 687b ldr r3, [r7, #4]
800d24e: 693a ldr r2, [r7, #16]
800d250: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800d252: 687b ldr r3, [r7, #4]
800d254: 68fa ldr r2, [r7, #12]
800d256: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
800d258: 683b ldr r3, [r7, #0]
800d25a: 685a ldr r2, [r3, #4]
800d25c: 687b ldr r3, [r7, #4]
800d25e: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800d260: 687b ldr r3, [r7, #4]
800d262: 697a ldr r2, [r7, #20]
800d264: 621a str r2, [r3, #32]
}
800d266: bf00 nop
800d268: 371c adds r7, #28
800d26a: 46bd mov sp, r7
800d26c: f85d 7b04 ldr.w r7, [sp], #4
800d270: 4770 bx lr
800d272: bf00 nop
800d274: 40012c00 .word 0x40012c00
800d278: 40014400 .word 0x40014400
800d27c: 40014800 .word 0x40014800
0800d280 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800d280: b480 push {r7}
800d282: b087 sub sp, #28
800d284: af00 add r7, sp, #0
800d286: 6078 str r0, [r7, #4]
800d288: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800d28a: 687b ldr r3, [r7, #4]
800d28c: 6a1b ldr r3, [r3, #32]
800d28e: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
800d290: 687b ldr r3, [r7, #4]
800d292: 6a1b ldr r3, [r3, #32]
800d294: f423 7280 bic.w r2, r3, #256 @ 0x100
800d298: 687b ldr r3, [r7, #4]
800d29a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800d29c: 687b ldr r3, [r7, #4]
800d29e: 685b ldr r3, [r3, #4]
800d2a0: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800d2a2: 687b ldr r3, [r7, #4]
800d2a4: 69db ldr r3, [r3, #28]
800d2a6: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
800d2a8: 68fb ldr r3, [r7, #12]
800d2aa: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800d2ae: f023 0370 bic.w r3, r3, #112 @ 0x70
800d2b2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
800d2b4: 68fb ldr r3, [r7, #12]
800d2b6: f023 0303 bic.w r3, r3, #3
800d2ba: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800d2bc: 683b ldr r3, [r7, #0]
800d2be: 681b ldr r3, [r3, #0]
800d2c0: 68fa ldr r2, [r7, #12]
800d2c2: 4313 orrs r3, r2
800d2c4: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800d2c6: 697b ldr r3, [r7, #20]
800d2c8: f423 7300 bic.w r3, r3, #512 @ 0x200
800d2cc: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
800d2ce: 683b ldr r3, [r7, #0]
800d2d0: 689b ldr r3, [r3, #8]
800d2d2: 021b lsls r3, r3, #8
800d2d4: 697a ldr r2, [r7, #20]
800d2d6: 4313 orrs r3, r2
800d2d8: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800d2da: 687b ldr r3, [r7, #4]
800d2dc: 4a22 ldr r2, [pc, #136] @ (800d368 <TIM_OC3_SetConfig+0xe8>)
800d2de: 4293 cmp r3, r2
800d2e0: d10f bne.n 800d302 <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Disable the Channel 3N: Reset the CC3NE Bit */
TIMx->CCER &= ~TIM_CCER_CC3NE;
800d2e2: 687b ldr r3, [r7, #4]
800d2e4: 6a1b ldr r3, [r3, #32]
800d2e6: f423 6280 bic.w r2, r3, #1024 @ 0x400
800d2ea: 687b ldr r3, [r7, #4]
800d2ec: 621a str r2, [r3, #32]
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
800d2ee: 697b ldr r3, [r7, #20]
800d2f0: f423 6300 bic.w r3, r3, #2048 @ 0x800
800d2f4: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
800d2f6: 683b ldr r3, [r7, #0]
800d2f8: 68db ldr r3, [r3, #12]
800d2fa: 021b lsls r3, r3, #8
800d2fc: 697a ldr r2, [r7, #20]
800d2fe: 4313 orrs r3, r2
800d300: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800d302: 687b ldr r3, [r7, #4]
800d304: 4a18 ldr r2, [pc, #96] @ (800d368 <TIM_OC3_SetConfig+0xe8>)
800d306: 4293 cmp r3, r2
800d308: d007 beq.n 800d31a <TIM_OC3_SetConfig+0x9a>
800d30a: 687b ldr r3, [r7, #4]
800d30c: 4a17 ldr r2, [pc, #92] @ (800d36c <TIM_OC3_SetConfig+0xec>)
800d30e: 4293 cmp r3, r2
800d310: d003 beq.n 800d31a <TIM_OC3_SetConfig+0x9a>
800d312: 687b ldr r3, [r7, #4]
800d314: 4a16 ldr r2, [pc, #88] @ (800d370 <TIM_OC3_SetConfig+0xf0>)
800d316: 4293 cmp r3, r2
800d318: d113 bne.n 800d342 <TIM_OC3_SetConfig+0xc2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800d31a: 693b ldr r3, [r7, #16]
800d31c: f423 5380 bic.w r3, r3, #4096 @ 0x1000
800d320: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
800d322: 693b ldr r3, [r7, #16]
800d324: f423 5300 bic.w r3, r3, #8192 @ 0x2000
800d328: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800d32a: 683b ldr r3, [r7, #0]
800d32c: 695b ldr r3, [r3, #20]
800d32e: 011b lsls r3, r3, #4
800d330: 693a ldr r2, [r7, #16]
800d332: 4313 orrs r3, r2
800d334: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
800d336: 683b ldr r3, [r7, #0]
800d338: 699b ldr r3, [r3, #24]
800d33a: 011b lsls r3, r3, #4
800d33c: 693a ldr r2, [r7, #16]
800d33e: 4313 orrs r3, r2
800d340: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800d342: 687b ldr r3, [r7, #4]
800d344: 693a ldr r2, [r7, #16]
800d346: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800d348: 687b ldr r3, [r7, #4]
800d34a: 68fa ldr r2, [r7, #12]
800d34c: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800d34e: 683b ldr r3, [r7, #0]
800d350: 685a ldr r2, [r3, #4]
800d352: 687b ldr r3, [r7, #4]
800d354: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800d356: 687b ldr r3, [r7, #4]
800d358: 697a ldr r2, [r7, #20]
800d35a: 621a str r2, [r3, #32]
}
800d35c: bf00 nop
800d35e: 371c adds r7, #28
800d360: 46bd mov sp, r7
800d362: f85d 7b04 ldr.w r7, [sp], #4
800d366: 4770 bx lr
800d368: 40012c00 .word 0x40012c00
800d36c: 40014400 .word 0x40014400
800d370: 40014800 .word 0x40014800
0800d374 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800d374: b480 push {r7}
800d376: b087 sub sp, #28
800d378: af00 add r7, sp, #0
800d37a: 6078 str r0, [r7, #4]
800d37c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800d37e: 687b ldr r3, [r7, #4]
800d380: 6a1b ldr r3, [r3, #32]
800d382: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
800d384: 687b ldr r3, [r7, #4]
800d386: 6a1b ldr r3, [r3, #32]
800d388: f423 5280 bic.w r2, r3, #4096 @ 0x1000
800d38c: 687b ldr r3, [r7, #4]
800d38e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800d390: 687b ldr r3, [r7, #4]
800d392: 685b ldr r3, [r3, #4]
800d394: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800d396: 687b ldr r3, [r7, #4]
800d398: 69db ldr r3, [r3, #28]
800d39a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
800d39c: 68fb ldr r3, [r7, #12]
800d39e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800d3a2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800d3a6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
800d3a8: 68fb ldr r3, [r7, #12]
800d3aa: f423 7340 bic.w r3, r3, #768 @ 0x300
800d3ae: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800d3b0: 683b ldr r3, [r7, #0]
800d3b2: 681b ldr r3, [r3, #0]
800d3b4: 021b lsls r3, r3, #8
800d3b6: 68fa ldr r2, [r7, #12]
800d3b8: 4313 orrs r3, r2
800d3ba: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
800d3bc: 693b ldr r3, [r7, #16]
800d3be: f423 5300 bic.w r3, r3, #8192 @ 0x2000
800d3c2: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
800d3c4: 683b ldr r3, [r7, #0]
800d3c6: 689b ldr r3, [r3, #8]
800d3c8: 031b lsls r3, r3, #12
800d3ca: 693a ldr r2, [r7, #16]
800d3cc: 4313 orrs r3, r2
800d3ce: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800d3d0: 687b ldr r3, [r7, #4]
800d3d2: 4a14 ldr r2, [pc, #80] @ (800d424 <TIM_OC4_SetConfig+0xb0>)
800d3d4: 4293 cmp r3, r2
800d3d6: d007 beq.n 800d3e8 <TIM_OC4_SetConfig+0x74>
800d3d8: 687b ldr r3, [r7, #4]
800d3da: 4a13 ldr r2, [pc, #76] @ (800d428 <TIM_OC4_SetConfig+0xb4>)
800d3dc: 4293 cmp r3, r2
800d3de: d003 beq.n 800d3e8 <TIM_OC4_SetConfig+0x74>
800d3e0: 687b ldr r3, [r7, #4]
800d3e2: 4a12 ldr r2, [pc, #72] @ (800d42c <TIM_OC4_SetConfig+0xb8>)
800d3e4: 4293 cmp r3, r2
800d3e6: d109 bne.n 800d3fc <TIM_OC4_SetConfig+0x88>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
800d3e8: 697b ldr r3, [r7, #20]
800d3ea: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800d3ee: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
800d3f0: 683b ldr r3, [r7, #0]
800d3f2: 695b ldr r3, [r3, #20]
800d3f4: 019b lsls r3, r3, #6
800d3f6: 697a ldr r2, [r7, #20]
800d3f8: 4313 orrs r3, r2
800d3fa: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800d3fc: 687b ldr r3, [r7, #4]
800d3fe: 697a ldr r2, [r7, #20]
800d400: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800d402: 687b ldr r3, [r7, #4]
800d404: 68fa ldr r2, [r7, #12]
800d406: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
800d408: 683b ldr r3, [r7, #0]
800d40a: 685a ldr r2, [r3, #4]
800d40c: 687b ldr r3, [r7, #4]
800d40e: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800d410: 687b ldr r3, [r7, #4]
800d412: 693a ldr r2, [r7, #16]
800d414: 621a str r2, [r3, #32]
}
800d416: bf00 nop
800d418: 371c adds r7, #28
800d41a: 46bd mov sp, r7
800d41c: f85d 7b04 ldr.w r7, [sp], #4
800d420: 4770 bx lr
800d422: bf00 nop
800d424: 40012c00 .word 0x40012c00
800d428: 40014400 .word 0x40014400
800d42c: 40014800 .word 0x40014800
0800d430 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
800d430: b480 push {r7}
800d432: b087 sub sp, #28
800d434: af00 add r7, sp, #0
800d436: 6078 str r0, [r7, #4]
800d438: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800d43a: 687b ldr r3, [r7, #4]
800d43c: 6a1b ldr r3, [r3, #32]
800d43e: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
800d440: 687b ldr r3, [r7, #4]
800d442: 6a1b ldr r3, [r3, #32]
800d444: f423 3280 bic.w r2, r3, #65536 @ 0x10000
800d448: 687b ldr r3, [r7, #4]
800d44a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800d44c: 687b ldr r3, [r7, #4]
800d44e: 685b ldr r3, [r3, #4]
800d450: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800d452: 687b ldr r3, [r7, #4]
800d454: 6d5b ldr r3, [r3, #84] @ 0x54
800d456: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
800d458: 68fb ldr r3, [r7, #12]
800d45a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800d45e: f023 0370 bic.w r3, r3, #112 @ 0x70
800d462: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800d464: 683b ldr r3, [r7, #0]
800d466: 681b ldr r3, [r3, #0]
800d468: 68fa ldr r2, [r7, #12]
800d46a: 4313 orrs r3, r2
800d46c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
800d46e: 693b ldr r3, [r7, #16]
800d470: f423 3300 bic.w r3, r3, #131072 @ 0x20000
800d474: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
800d476: 683b ldr r3, [r7, #0]
800d478: 689b ldr r3, [r3, #8]
800d47a: 041b lsls r3, r3, #16
800d47c: 693a ldr r2, [r7, #16]
800d47e: 4313 orrs r3, r2
800d480: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800d482: 687b ldr r3, [r7, #4]
800d484: 4a13 ldr r2, [pc, #76] @ (800d4d4 <TIM_OC5_SetConfig+0xa4>)
800d486: 4293 cmp r3, r2
800d488: d007 beq.n 800d49a <TIM_OC5_SetConfig+0x6a>
800d48a: 687b ldr r3, [r7, #4]
800d48c: 4a12 ldr r2, [pc, #72] @ (800d4d8 <TIM_OC5_SetConfig+0xa8>)
800d48e: 4293 cmp r3, r2
800d490: d003 beq.n 800d49a <TIM_OC5_SetConfig+0x6a>
800d492: 687b ldr r3, [r7, #4]
800d494: 4a11 ldr r2, [pc, #68] @ (800d4dc <TIM_OC5_SetConfig+0xac>)
800d496: 4293 cmp r3, r2
800d498: d109 bne.n 800d4ae <TIM_OC5_SetConfig+0x7e>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
800d49a: 697b ldr r3, [r7, #20]
800d49c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800d4a0: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
800d4a2: 683b ldr r3, [r7, #0]
800d4a4: 695b ldr r3, [r3, #20]
800d4a6: 021b lsls r3, r3, #8
800d4a8: 697a ldr r2, [r7, #20]
800d4aa: 4313 orrs r3, r2
800d4ac: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800d4ae: 687b ldr r3, [r7, #4]
800d4b0: 697a ldr r2, [r7, #20]
800d4b2: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800d4b4: 687b ldr r3, [r7, #4]
800d4b6: 68fa ldr r2, [r7, #12]
800d4b8: 655a str r2, [r3, #84] @ 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
800d4ba: 683b ldr r3, [r7, #0]
800d4bc: 685a ldr r2, [r3, #4]
800d4be: 687b ldr r3, [r7, #4]
800d4c0: 659a str r2, [r3, #88] @ 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800d4c2: 687b ldr r3, [r7, #4]
800d4c4: 693a ldr r2, [r7, #16]
800d4c6: 621a str r2, [r3, #32]
}
800d4c8: bf00 nop
800d4ca: 371c adds r7, #28
800d4cc: 46bd mov sp, r7
800d4ce: f85d 7b04 ldr.w r7, [sp], #4
800d4d2: 4770 bx lr
800d4d4: 40012c00 .word 0x40012c00
800d4d8: 40014400 .word 0x40014400
800d4dc: 40014800 .word 0x40014800
0800d4e0 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
800d4e0: b480 push {r7}
800d4e2: b087 sub sp, #28
800d4e4: af00 add r7, sp, #0
800d4e6: 6078 str r0, [r7, #4]
800d4e8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800d4ea: 687b ldr r3, [r7, #4]
800d4ec: 6a1b ldr r3, [r3, #32]
800d4ee: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
800d4f0: 687b ldr r3, [r7, #4]
800d4f2: 6a1b ldr r3, [r3, #32]
800d4f4: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
800d4f8: 687b ldr r3, [r7, #4]
800d4fa: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800d4fc: 687b ldr r3, [r7, #4]
800d4fe: 685b ldr r3, [r3, #4]
800d500: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800d502: 687b ldr r3, [r7, #4]
800d504: 6d5b ldr r3, [r3, #84] @ 0x54
800d506: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
800d508: 68fb ldr r3, [r7, #12]
800d50a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800d50e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800d512: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800d514: 683b ldr r3, [r7, #0]
800d516: 681b ldr r3, [r3, #0]
800d518: 021b lsls r3, r3, #8
800d51a: 68fa ldr r2, [r7, #12]
800d51c: 4313 orrs r3, r2
800d51e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
800d520: 693b ldr r3, [r7, #16]
800d522: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
800d526: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
800d528: 683b ldr r3, [r7, #0]
800d52a: 689b ldr r3, [r3, #8]
800d52c: 051b lsls r3, r3, #20
800d52e: 693a ldr r2, [r7, #16]
800d530: 4313 orrs r3, r2
800d532: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800d534: 687b ldr r3, [r7, #4]
800d536: 4a14 ldr r2, [pc, #80] @ (800d588 <TIM_OC6_SetConfig+0xa8>)
800d538: 4293 cmp r3, r2
800d53a: d007 beq.n 800d54c <TIM_OC6_SetConfig+0x6c>
800d53c: 687b ldr r3, [r7, #4]
800d53e: 4a13 ldr r2, [pc, #76] @ (800d58c <TIM_OC6_SetConfig+0xac>)
800d540: 4293 cmp r3, r2
800d542: d003 beq.n 800d54c <TIM_OC6_SetConfig+0x6c>
800d544: 687b ldr r3, [r7, #4]
800d546: 4a12 ldr r2, [pc, #72] @ (800d590 <TIM_OC6_SetConfig+0xb0>)
800d548: 4293 cmp r3, r2
800d54a: d109 bne.n 800d560 <TIM_OC6_SetConfig+0x80>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
800d54c: 697b ldr r3, [r7, #20]
800d54e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800d552: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
800d554: 683b ldr r3, [r7, #0]
800d556: 695b ldr r3, [r3, #20]
800d558: 029b lsls r3, r3, #10
800d55a: 697a ldr r2, [r7, #20]
800d55c: 4313 orrs r3, r2
800d55e: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800d560: 687b ldr r3, [r7, #4]
800d562: 697a ldr r2, [r7, #20]
800d564: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800d566: 687b ldr r3, [r7, #4]
800d568: 68fa ldr r2, [r7, #12]
800d56a: 655a str r2, [r3, #84] @ 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
800d56c: 683b ldr r3, [r7, #0]
800d56e: 685a ldr r2, [r3, #4]
800d570: 687b ldr r3, [r7, #4]
800d572: 65da str r2, [r3, #92] @ 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800d574: 687b ldr r3, [r7, #4]
800d576: 693a ldr r2, [r7, #16]
800d578: 621a str r2, [r3, #32]
}
800d57a: bf00 nop
800d57c: 371c adds r7, #28
800d57e: 46bd mov sp, r7
800d580: f85d 7b04 ldr.w r7, [sp], #4
800d584: 4770 bx lr
800d586: bf00 nop
800d588: 40012c00 .word 0x40012c00
800d58c: 40014400 .word 0x40014400
800d590: 40014800 .word 0x40014800
0800d594 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
800d594: b480 push {r7}
800d596: b085 sub sp, #20
800d598: af00 add r7, sp, #0
800d59a: 6078 str r0, [r7, #4]
800d59c: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
800d59e: 687b ldr r3, [r7, #4]
800d5a0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800d5a4: 2b01 cmp r3, #1
800d5a6: d101 bne.n 800d5ac <HAL_TIMEx_MasterConfigSynchronization+0x18>
800d5a8: 2302 movs r3, #2
800d5aa: e04a b.n 800d642 <HAL_TIMEx_MasterConfigSynchronization+0xae>
800d5ac: 687b ldr r3, [r7, #4]
800d5ae: 2201 movs r2, #1
800d5b0: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
800d5b4: 687b ldr r3, [r7, #4]
800d5b6: 2202 movs r2, #2
800d5b8: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
800d5bc: 687b ldr r3, [r7, #4]
800d5be: 681b ldr r3, [r3, #0]
800d5c0: 685b ldr r3, [r3, #4]
800d5c2: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800d5c4: 687b ldr r3, [r7, #4]
800d5c6: 681b ldr r3, [r3, #0]
800d5c8: 689b ldr r3, [r3, #8]
800d5ca: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
800d5cc: 687b ldr r3, [r7, #4]
800d5ce: 681b ldr r3, [r3, #0]
800d5d0: 4a1f ldr r2, [pc, #124] @ (800d650 <HAL_TIMEx_MasterConfigSynchronization+0xbc>)
800d5d2: 4293 cmp r3, r2
800d5d4: d108 bne.n 800d5e8 <HAL_TIMEx_MasterConfigSynchronization+0x54>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
800d5d6: 68fb ldr r3, [r7, #12]
800d5d8: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
800d5dc: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
800d5de: 683b ldr r3, [r7, #0]
800d5e0: 685b ldr r3, [r3, #4]
800d5e2: 68fa ldr r2, [r7, #12]
800d5e4: 4313 orrs r3, r2
800d5e6: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
800d5e8: 68fb ldr r3, [r7, #12]
800d5ea: f023 0370 bic.w r3, r3, #112 @ 0x70
800d5ee: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800d5f0: 683b ldr r3, [r7, #0]
800d5f2: 681b ldr r3, [r3, #0]
800d5f4: 68fa ldr r2, [r7, #12]
800d5f6: 4313 orrs r3, r2
800d5f8: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
800d5fa: 687b ldr r3, [r7, #4]
800d5fc: 681b ldr r3, [r3, #0]
800d5fe: 68fa ldr r2, [r7, #12]
800d600: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800d602: 687b ldr r3, [r7, #4]
800d604: 681b ldr r3, [r3, #0]
800d606: 4a12 ldr r2, [pc, #72] @ (800d650 <HAL_TIMEx_MasterConfigSynchronization+0xbc>)
800d608: 4293 cmp r3, r2
800d60a: d004 beq.n 800d616 <HAL_TIMEx_MasterConfigSynchronization+0x82>
800d60c: 687b ldr r3, [r7, #4]
800d60e: 681b ldr r3, [r3, #0]
800d610: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800d614: d10c bne.n 800d630 <HAL_TIMEx_MasterConfigSynchronization+0x9c>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800d616: 68bb ldr r3, [r7, #8]
800d618: f023 0380 bic.w r3, r3, #128 @ 0x80
800d61c: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800d61e: 683b ldr r3, [r7, #0]
800d620: 689b ldr r3, [r3, #8]
800d622: 68ba ldr r2, [r7, #8]
800d624: 4313 orrs r3, r2
800d626: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800d628: 687b ldr r3, [r7, #4]
800d62a: 681b ldr r3, [r3, #0]
800d62c: 68ba ldr r2, [r7, #8]
800d62e: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
800d630: 687b ldr r3, [r7, #4]
800d632: 2201 movs r2, #1
800d634: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
800d638: 687b ldr r3, [r7, #4]
800d63a: 2200 movs r2, #0
800d63c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
800d640: 2300 movs r3, #0
}
800d642: 4618 mov r0, r3
800d644: 3714 adds r7, #20
800d646: 46bd mov sp, r7
800d648: f85d 7b04 ldr.w r7, [sp], #4
800d64c: 4770 bx lr
800d64e: bf00 nop
800d650: 40012c00 .word 0x40012c00
0800d654 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
800d654: b480 push {r7}
800d656: b083 sub sp, #12
800d658: af00 add r7, sp, #0
800d65a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
800d65c: bf00 nop
800d65e: 370c adds r7, #12
800d660: 46bd mov sp, r7
800d662: f85d 7b04 ldr.w r7, [sp], #4
800d666: 4770 bx lr
0800d668 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
800d668: b480 push {r7}
800d66a: b083 sub sp, #12
800d66c: af00 add r7, sp, #0
800d66e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
800d670: bf00 nop
800d672: 370c adds r7, #12
800d674: 46bd mov sp, r7
800d676: f85d 7b04 ldr.w r7, [sp], #4
800d67a: 4770 bx lr
0800d67c <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
800d67c: b480 push {r7}
800d67e: b083 sub sp, #12
800d680: af00 add r7, sp, #0
800d682: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
800d684: bf00 nop
800d686: 370c adds r7, #12
800d688: 46bd mov sp, r7
800d68a: f85d 7b04 ldr.w r7, [sp], #4
800d68e: 4770 bx lr
0800d690 <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
800d690: b480 push {r7}
800d692: b085 sub sp, #20
800d694: af00 add r7, sp, #0
800d696: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Clear pending interrupts */
USBx->ISTR = 0U;
800d698: 687b ldr r3, [r7, #4]
800d69a: 2200 movs r2, #0
800d69c: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
800d6a0: f64b 7380 movw r3, #49024 @ 0xbf80
800d6a4: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM | USB_CNTR_L1REQM;
/* Set interrupt mask */
USBx->CNTR = (uint16_t)winterruptmask;
800d6a6: 68fb ldr r3, [r7, #12]
800d6a8: b29a uxth r2, r3
800d6aa: 687b ldr r3, [r7, #4]
800d6ac: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
800d6b0: 2300 movs r3, #0
}
800d6b2: 4618 mov r0, r3
800d6b4: 3714 adds r7, #20
800d6b6: 46bd mov sp, r7
800d6b8: f85d 7b04 ldr.w r7, [sp], #4
800d6bc: 4770 bx lr
0800d6be <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
800d6be: b480 push {r7}
800d6c0: b085 sub sp, #20
800d6c2: af00 add r7, sp, #0
800d6c4: 6078 str r0, [r7, #4]
uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
800d6c6: f64b 7380 movw r3, #49024 @ 0xbf80
800d6ca: 60fb str r3, [r7, #12]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM | USB_CNTR_L1REQM;
/* Clear interrupt mask */
USBx->CNTR &= (uint16_t)(~winterruptmask);
800d6cc: 687b ldr r3, [r7, #4]
800d6ce: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40
800d6d2: b29a uxth r2, r3
800d6d4: 68fb ldr r3, [r7, #12]
800d6d6: b29b uxth r3, r3
800d6d8: 43db mvns r3, r3
800d6da: b29b uxth r3, r3
800d6dc: 4013 ands r3, r2
800d6de: b29a uxth r2, r3
800d6e0: 687b ldr r3, [r7, #4]
800d6e2: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
return HAL_OK;
800d6e6: 2300 movs r3, #0
}
800d6e8: 4618 mov r0, r3
800d6ea: 3714 adds r7, #20
800d6ec: 46bd mov sp, r7
800d6ee: f85d 7b04 ldr.w r7, [sp], #4
800d6f2: 4770 bx lr
0800d6f4 <USB_DevInit>:
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
800d6f4: b480 push {r7}
800d6f6: b085 sub sp, #20
800d6f8: af00 add r7, sp, #0
800d6fa: 60f8 str r0, [r7, #12]
800d6fc: 1d3b adds r3, r7, #4
800d6fe: e883 0006 stmia.w r3, {r1, r2}
/* Prevent unused argument(s) compilation warning */
UNUSED(cfg);
/* Init Device */
/* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
800d702: 68fb ldr r3, [r7, #12]
800d704: 2201 movs r2, #1
800d706: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* CNTR_FRES = 0 */
USBx->CNTR = 0U;
800d70a: 68fb ldr r3, [r7, #12]
800d70c: 2200 movs r2, #0
800d70e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40
/* Clear pending interrupts */
USBx->ISTR = 0U;
800d712: 68fb ldr r3, [r7, #12]
800d714: 2200 movs r2, #0
800d716: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
800d71a: 68fb ldr r3, [r7, #12]
800d71c: 2200 movs r2, #0
800d71e: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
return HAL_OK;
800d722: 2300 movs r3, #0
}
800d724: 4618 mov r0, r3
800d726: 3714 adds r7, #20
800d728: 46bd mov sp, r7
800d72a: f85d 7b04 ldr.w r7, [sp], #4
800d72e: 4770 bx lr
0800d730 <USB_ActivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
800d730: b480 push {r7}
800d732: b0a7 sub sp, #156 @ 0x9c
800d734: af00 add r7, sp, #0
800d736: 6078 str r0, [r7, #4]
800d738: 6039 str r1, [r7, #0]
HAL_StatusTypeDef ret = HAL_OK;
800d73a: 2300 movs r3, #0
800d73c: f887 3097 strb.w r3, [r7, #151] @ 0x97
uint16_t wEpRegVal;
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
800d740: 687a ldr r2, [r7, #4]
800d742: 683b ldr r3, [r7, #0]
800d744: 781b ldrb r3, [r3, #0]
800d746: 009b lsls r3, r3, #2
800d748: 4413 add r3, r2
800d74a: 881b ldrh r3, [r3, #0]
800d74c: b29b uxth r3, r3
800d74e: f423 43ec bic.w r3, r3, #30208 @ 0x7600
800d752: f023 0370 bic.w r3, r3, #112 @ 0x70
800d756: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
/* initialize Endpoint */
switch (ep->type)
800d75a: 683b ldr r3, [r7, #0]
800d75c: 78db ldrb r3, [r3, #3]
800d75e: 2b03 cmp r3, #3
800d760: d81f bhi.n 800d7a2 <USB_ActivateEndpoint+0x72>
800d762: a201 add r2, pc, #4 @ (adr r2, 800d768 <USB_ActivateEndpoint+0x38>)
800d764: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800d768: 0800d779 .word 0x0800d779
800d76c: 0800d795 .word 0x0800d795
800d770: 0800d7ab .word 0x0800d7ab
800d774: 0800d787 .word 0x0800d787
{
case EP_TYPE_CTRL:
wEpRegVal |= USB_EP_CONTROL;
800d778: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
800d77c: f443 7300 orr.w r3, r3, #512 @ 0x200
800d780: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
break;
800d784: e012 b.n 800d7ac <USB_ActivateEndpoint+0x7c>
case EP_TYPE_BULK:
wEpRegVal |= USB_EP_BULK;
break;
case EP_TYPE_INTR:
wEpRegVal |= USB_EP_INTERRUPT;
800d786: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
800d78a: f443 63c0 orr.w r3, r3, #1536 @ 0x600
800d78e: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
break;
800d792: e00b b.n 800d7ac <USB_ActivateEndpoint+0x7c>
case EP_TYPE_ISOC:
wEpRegVal |= USB_EP_ISOCHRONOUS;
800d794: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
800d798: f443 6380 orr.w r3, r3, #1024 @ 0x400
800d79c: f8a7 3094 strh.w r3, [r7, #148] @ 0x94
break;
800d7a0: e004 b.n 800d7ac <USB_ActivateEndpoint+0x7c>
default:
ret = HAL_ERROR;
800d7a2: 2301 movs r3, #1
800d7a4: f887 3097 strb.w r3, [r7, #151] @ 0x97
break;
800d7a8: e000 b.n 800d7ac <USB_ActivateEndpoint+0x7c>
break;
800d7aa: bf00 nop
}
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
800d7ac: 687a ldr r2, [r7, #4]
800d7ae: 683b ldr r3, [r7, #0]
800d7b0: 781b ldrb r3, [r3, #0]
800d7b2: 009b lsls r3, r3, #2
800d7b4: 441a add r2, r3
800d7b6: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94
800d7ba: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800d7be: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800d7c2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800d7c6: f043 0380 orr.w r3, r3, #128 @ 0x80
800d7ca: b29b uxth r3, r3
800d7cc: 8013 strh r3, [r2, #0]
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
800d7ce: 687a ldr r2, [r7, #4]
800d7d0: 683b ldr r3, [r7, #0]
800d7d2: 781b ldrb r3, [r3, #0]
800d7d4: 009b lsls r3, r3, #2
800d7d6: 4413 add r3, r2
800d7d8: 881b ldrh r3, [r3, #0]
800d7da: b29b uxth r3, r3
800d7dc: b21b sxth r3, r3
800d7de: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800d7e2: f023 0370 bic.w r3, r3, #112 @ 0x70
800d7e6: b21a sxth r2, r3
800d7e8: 683b ldr r3, [r7, #0]
800d7ea: 781b ldrb r3, [r3, #0]
800d7ec: b21b sxth r3, r3
800d7ee: 4313 orrs r3, r2
800d7f0: b21b sxth r3, r3
800d7f2: f8a7 3086 strh.w r3, [r7, #134] @ 0x86
800d7f6: 687a ldr r2, [r7, #4]
800d7f8: 683b ldr r3, [r7, #0]
800d7fa: 781b ldrb r3, [r3, #0]
800d7fc: 009b lsls r3, r3, #2
800d7fe: 441a add r2, r3
800d800: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86
800d804: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800d808: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800d80c: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800d810: f043 0380 orr.w r3, r3, #128 @ 0x80
800d814: b29b uxth r3, r3
800d816: 8013 strh r3, [r2, #0]
if (ep->doublebuffer == 0U)
800d818: 683b ldr r3, [r7, #0]
800d81a: 7b1b ldrb r3, [r3, #12]
800d81c: 2b00 cmp r3, #0
800d81e: f040 8180 bne.w 800db22 <USB_ActivateEndpoint+0x3f2>
{
if (ep->is_in != 0U)
800d822: 683b ldr r3, [r7, #0]
800d824: 785b ldrb r3, [r3, #1]
800d826: 2b00 cmp r3, #0
800d828: f000 8084 beq.w 800d934 <USB_ActivateEndpoint+0x204>
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
800d82c: 687b ldr r3, [r7, #4]
800d82e: 61bb str r3, [r7, #24]
800d830: 687b ldr r3, [r7, #4]
800d832: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800d836: b29b uxth r3, r3
800d838: 461a mov r2, r3
800d83a: 69bb ldr r3, [r7, #24]
800d83c: 4413 add r3, r2
800d83e: 61bb str r3, [r7, #24]
800d840: 683b ldr r3, [r7, #0]
800d842: 781b ldrb r3, [r3, #0]
800d844: 00da lsls r2, r3, #3
800d846: 69bb ldr r3, [r7, #24]
800d848: 4413 add r3, r2
800d84a: f503 6380 add.w r3, r3, #1024 @ 0x400
800d84e: 617b str r3, [r7, #20]
800d850: 683b ldr r3, [r7, #0]
800d852: 88db ldrh r3, [r3, #6]
800d854: 085b lsrs r3, r3, #1
800d856: b29b uxth r3, r3
800d858: 005b lsls r3, r3, #1
800d85a: b29a uxth r2, r3
800d85c: 697b ldr r3, [r7, #20]
800d85e: 801a strh r2, [r3, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800d860: 687a ldr r2, [r7, #4]
800d862: 683b ldr r3, [r7, #0]
800d864: 781b ldrb r3, [r3, #0]
800d866: 009b lsls r3, r3, #2
800d868: 4413 add r3, r2
800d86a: 881b ldrh r3, [r3, #0]
800d86c: 827b strh r3, [r7, #18]
800d86e: 8a7b ldrh r3, [r7, #18]
800d870: f003 0340 and.w r3, r3, #64 @ 0x40
800d874: 2b00 cmp r3, #0
800d876: d01b beq.n 800d8b0 <USB_ActivateEndpoint+0x180>
800d878: 687a ldr r2, [r7, #4]
800d87a: 683b ldr r3, [r7, #0]
800d87c: 781b ldrb r3, [r3, #0]
800d87e: 009b lsls r3, r3, #2
800d880: 4413 add r3, r2
800d882: 881b ldrh r3, [r3, #0]
800d884: b29b uxth r3, r3
800d886: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800d88a: f023 0370 bic.w r3, r3, #112 @ 0x70
800d88e: 823b strh r3, [r7, #16]
800d890: 687a ldr r2, [r7, #4]
800d892: 683b ldr r3, [r7, #0]
800d894: 781b ldrb r3, [r3, #0]
800d896: 009b lsls r3, r3, #2
800d898: 441a add r2, r3
800d89a: 8a3b ldrh r3, [r7, #16]
800d89c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800d8a0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800d8a4: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800d8a8: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800d8ac: b29b uxth r3, r3
800d8ae: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800d8b0: 683b ldr r3, [r7, #0]
800d8b2: 78db ldrb r3, [r3, #3]
800d8b4: 2b01 cmp r3, #1
800d8b6: d020 beq.n 800d8fa <USB_ActivateEndpoint+0x1ca>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
800d8b8: 687a ldr r2, [r7, #4]
800d8ba: 683b ldr r3, [r7, #0]
800d8bc: 781b ldrb r3, [r3, #0]
800d8be: 009b lsls r3, r3, #2
800d8c0: 4413 add r3, r2
800d8c2: 881b ldrh r3, [r3, #0]
800d8c4: b29b uxth r3, r3
800d8c6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800d8ca: f023 0340 bic.w r3, r3, #64 @ 0x40
800d8ce: 81bb strh r3, [r7, #12]
800d8d0: 89bb ldrh r3, [r7, #12]
800d8d2: f083 0320 eor.w r3, r3, #32
800d8d6: 81bb strh r3, [r7, #12]
800d8d8: 687a ldr r2, [r7, #4]
800d8da: 683b ldr r3, [r7, #0]
800d8dc: 781b ldrb r3, [r3, #0]
800d8de: 009b lsls r3, r3, #2
800d8e0: 441a add r2, r3
800d8e2: 89bb ldrh r3, [r7, #12]
800d8e4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800d8e8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800d8ec: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800d8f0: f043 0380 orr.w r3, r3, #128 @ 0x80
800d8f4: b29b uxth r3, r3
800d8f6: 8013 strh r3, [r2, #0]
800d8f8: e3f9 b.n 800e0ee <USB_ActivateEndpoint+0x9be>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800d8fa: 687a ldr r2, [r7, #4]
800d8fc: 683b ldr r3, [r7, #0]
800d8fe: 781b ldrb r3, [r3, #0]
800d900: 009b lsls r3, r3, #2
800d902: 4413 add r3, r2
800d904: 881b ldrh r3, [r3, #0]
800d906: b29b uxth r3, r3
800d908: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800d90c: f023 0340 bic.w r3, r3, #64 @ 0x40
800d910: 81fb strh r3, [r7, #14]
800d912: 687a ldr r2, [r7, #4]
800d914: 683b ldr r3, [r7, #0]
800d916: 781b ldrb r3, [r3, #0]
800d918: 009b lsls r3, r3, #2
800d91a: 441a add r2, r3
800d91c: 89fb ldrh r3, [r7, #14]
800d91e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800d922: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800d926: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800d92a: f043 0380 orr.w r3, r3, #128 @ 0x80
800d92e: b29b uxth r3, r3
800d930: 8013 strh r3, [r2, #0]
800d932: e3dc b.n 800e0ee <USB_ActivateEndpoint+0x9be>
}
}
else
{
/* Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
800d934: 687b ldr r3, [r7, #4]
800d936: 633b str r3, [r7, #48] @ 0x30
800d938: 687b ldr r3, [r7, #4]
800d93a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800d93e: b29b uxth r3, r3
800d940: 461a mov r2, r3
800d942: 6b3b ldr r3, [r7, #48] @ 0x30
800d944: 4413 add r3, r2
800d946: 633b str r3, [r7, #48] @ 0x30
800d948: 683b ldr r3, [r7, #0]
800d94a: 781b ldrb r3, [r3, #0]
800d94c: 00da lsls r2, r3, #3
800d94e: 6b3b ldr r3, [r7, #48] @ 0x30
800d950: 4413 add r3, r2
800d952: f203 4304 addw r3, r3, #1028 @ 0x404
800d956: 62fb str r3, [r7, #44] @ 0x2c
800d958: 683b ldr r3, [r7, #0]
800d95a: 88db ldrh r3, [r3, #6]
800d95c: 085b lsrs r3, r3, #1
800d95e: b29b uxth r3, r3
800d960: 005b lsls r3, r3, #1
800d962: b29a uxth r2, r3
800d964: 6afb ldr r3, [r7, #44] @ 0x2c
800d966: 801a strh r2, [r3, #0]
/* Set the endpoint Receive buffer counter */
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
800d968: 687b ldr r3, [r7, #4]
800d96a: 62bb str r3, [r7, #40] @ 0x28
800d96c: 687b ldr r3, [r7, #4]
800d96e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800d972: b29b uxth r3, r3
800d974: 461a mov r2, r3
800d976: 6abb ldr r3, [r7, #40] @ 0x28
800d978: 4413 add r3, r2
800d97a: 62bb str r3, [r7, #40] @ 0x28
800d97c: 683b ldr r3, [r7, #0]
800d97e: 781b ldrb r3, [r3, #0]
800d980: 00da lsls r2, r3, #3
800d982: 6abb ldr r3, [r7, #40] @ 0x28
800d984: 4413 add r3, r2
800d986: f203 4306 addw r3, r3, #1030 @ 0x406
800d98a: 627b str r3, [r7, #36] @ 0x24
800d98c: 6a7b ldr r3, [r7, #36] @ 0x24
800d98e: 881b ldrh r3, [r3, #0]
800d990: b29b uxth r3, r3
800d992: f3c3 0309 ubfx r3, r3, #0, #10
800d996: b29a uxth r2, r3
800d998: 6a7b ldr r3, [r7, #36] @ 0x24
800d99a: 801a strh r2, [r3, #0]
800d99c: 683b ldr r3, [r7, #0]
800d99e: 691b ldr r3, [r3, #16]
800d9a0: 2b00 cmp r3, #0
800d9a2: d10a bne.n 800d9ba <USB_ActivateEndpoint+0x28a>
800d9a4: 6a7b ldr r3, [r7, #36] @ 0x24
800d9a6: 881b ldrh r3, [r3, #0]
800d9a8: b29b uxth r3, r3
800d9aa: ea6f 4343 mvn.w r3, r3, lsl #17
800d9ae: ea6f 4353 mvn.w r3, r3, lsr #17
800d9b2: b29a uxth r2, r3
800d9b4: 6a7b ldr r3, [r7, #36] @ 0x24
800d9b6: 801a strh r2, [r3, #0]
800d9b8: e041 b.n 800da3e <USB_ActivateEndpoint+0x30e>
800d9ba: 683b ldr r3, [r7, #0]
800d9bc: 691b ldr r3, [r3, #16]
800d9be: 2b3e cmp r3, #62 @ 0x3e
800d9c0: d81c bhi.n 800d9fc <USB_ActivateEndpoint+0x2cc>
800d9c2: 683b ldr r3, [r7, #0]
800d9c4: 691b ldr r3, [r3, #16]
800d9c6: 085b lsrs r3, r3, #1
800d9c8: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800d9cc: 683b ldr r3, [r7, #0]
800d9ce: 691b ldr r3, [r3, #16]
800d9d0: f003 0301 and.w r3, r3, #1
800d9d4: 2b00 cmp r3, #0
800d9d6: d004 beq.n 800d9e2 <USB_ActivateEndpoint+0x2b2>
800d9d8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800d9dc: 3301 adds r3, #1
800d9de: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800d9e2: 6a7b ldr r3, [r7, #36] @ 0x24
800d9e4: 881b ldrh r3, [r3, #0]
800d9e6: b29a uxth r2, r3
800d9e8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800d9ec: b29b uxth r3, r3
800d9ee: 029b lsls r3, r3, #10
800d9f0: b29b uxth r3, r3
800d9f2: 4313 orrs r3, r2
800d9f4: b29a uxth r2, r3
800d9f6: 6a7b ldr r3, [r7, #36] @ 0x24
800d9f8: 801a strh r2, [r3, #0]
800d9fa: e020 b.n 800da3e <USB_ActivateEndpoint+0x30e>
800d9fc: 683b ldr r3, [r7, #0]
800d9fe: 691b ldr r3, [r3, #16]
800da00: 095b lsrs r3, r3, #5
800da02: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800da06: 683b ldr r3, [r7, #0]
800da08: 691b ldr r3, [r3, #16]
800da0a: f003 031f and.w r3, r3, #31
800da0e: 2b00 cmp r3, #0
800da10: d104 bne.n 800da1c <USB_ActivateEndpoint+0x2ec>
800da12: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800da16: 3b01 subs r3, #1
800da18: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800da1c: 6a7b ldr r3, [r7, #36] @ 0x24
800da1e: 881b ldrh r3, [r3, #0]
800da20: b29a uxth r2, r3
800da22: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800da26: b29b uxth r3, r3
800da28: 029b lsls r3, r3, #10
800da2a: b29b uxth r3, r3
800da2c: 4313 orrs r3, r2
800da2e: b29b uxth r3, r3
800da30: ea6f 4343 mvn.w r3, r3, lsl #17
800da34: ea6f 4353 mvn.w r3, r3, lsr #17
800da38: b29a uxth r2, r3
800da3a: 6a7b ldr r3, [r7, #36] @ 0x24
800da3c: 801a strh r2, [r3, #0]
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800da3e: 687a ldr r2, [r7, #4]
800da40: 683b ldr r3, [r7, #0]
800da42: 781b ldrb r3, [r3, #0]
800da44: 009b lsls r3, r3, #2
800da46: 4413 add r3, r2
800da48: 881b ldrh r3, [r3, #0]
800da4a: 847b strh r3, [r7, #34] @ 0x22
800da4c: 8c7b ldrh r3, [r7, #34] @ 0x22
800da4e: f403 4380 and.w r3, r3, #16384 @ 0x4000
800da52: 2b00 cmp r3, #0
800da54: d01b beq.n 800da8e <USB_ActivateEndpoint+0x35e>
800da56: 687a ldr r2, [r7, #4]
800da58: 683b ldr r3, [r7, #0]
800da5a: 781b ldrb r3, [r3, #0]
800da5c: 009b lsls r3, r3, #2
800da5e: 4413 add r3, r2
800da60: 881b ldrh r3, [r3, #0]
800da62: b29b uxth r3, r3
800da64: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800da68: f023 0370 bic.w r3, r3, #112 @ 0x70
800da6c: 843b strh r3, [r7, #32]
800da6e: 687a ldr r2, [r7, #4]
800da70: 683b ldr r3, [r7, #0]
800da72: 781b ldrb r3, [r3, #0]
800da74: 009b lsls r3, r3, #2
800da76: 441a add r2, r3
800da78: 8c3b ldrh r3, [r7, #32]
800da7a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800da7e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800da82: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800da86: f043 0380 orr.w r3, r3, #128 @ 0x80
800da8a: b29b uxth r3, r3
800da8c: 8013 strh r3, [r2, #0]
if (ep->num == 0U)
800da8e: 683b ldr r3, [r7, #0]
800da90: 781b ldrb r3, [r3, #0]
800da92: 2b00 cmp r3, #0
800da94: d124 bne.n 800dae0 <USB_ActivateEndpoint+0x3b0>
{
/* Configure VALID status for EP0 */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
800da96: 687a ldr r2, [r7, #4]
800da98: 683b ldr r3, [r7, #0]
800da9a: 781b ldrb r3, [r3, #0]
800da9c: 009b lsls r3, r3, #2
800da9e: 4413 add r3, r2
800daa0: 881b ldrh r3, [r3, #0]
800daa2: b29b uxth r3, r3
800daa4: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800daa8: f023 0370 bic.w r3, r3, #112 @ 0x70
800daac: 83bb strh r3, [r7, #28]
800daae: 8bbb ldrh r3, [r7, #28]
800dab0: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800dab4: 83bb strh r3, [r7, #28]
800dab6: 8bbb ldrh r3, [r7, #28]
800dab8: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800dabc: 83bb strh r3, [r7, #28]
800dabe: 687a ldr r2, [r7, #4]
800dac0: 683b ldr r3, [r7, #0]
800dac2: 781b ldrb r3, [r3, #0]
800dac4: 009b lsls r3, r3, #2
800dac6: 441a add r2, r3
800dac8: 8bbb ldrh r3, [r7, #28]
800daca: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800dace: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800dad2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800dad6: f043 0380 orr.w r3, r3, #128 @ 0x80
800dada: b29b uxth r3, r3
800dadc: 8013 strh r3, [r2, #0]
800dade: e306 b.n 800e0ee <USB_ActivateEndpoint+0x9be>
}
else
{
/* Configure NAK status for OUT Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
800dae0: 687a ldr r2, [r7, #4]
800dae2: 683b ldr r3, [r7, #0]
800dae4: 781b ldrb r3, [r3, #0]
800dae6: 009b lsls r3, r3, #2
800dae8: 4413 add r3, r2
800daea: 881b ldrh r3, [r3, #0]
800daec: b29b uxth r3, r3
800daee: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800daf2: f023 0370 bic.w r3, r3, #112 @ 0x70
800daf6: 83fb strh r3, [r7, #30]
800daf8: 8bfb ldrh r3, [r7, #30]
800dafa: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800dafe: 83fb strh r3, [r7, #30]
800db00: 687a ldr r2, [r7, #4]
800db02: 683b ldr r3, [r7, #0]
800db04: 781b ldrb r3, [r3, #0]
800db06: 009b lsls r3, r3, #2
800db08: 441a add r2, r3
800db0a: 8bfb ldrh r3, [r7, #30]
800db0c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800db10: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800db14: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800db18: f043 0380 orr.w r3, r3, #128 @ 0x80
800db1c: b29b uxth r3, r3
800db1e: 8013 strh r3, [r2, #0]
800db20: e2e5 b.n 800e0ee <USB_ActivateEndpoint+0x9be>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->type == EP_TYPE_BULK)
800db22: 683b ldr r3, [r7, #0]
800db24: 78db ldrb r3, [r3, #3]
800db26: 2b02 cmp r3, #2
800db28: d11e bne.n 800db68 <USB_ActivateEndpoint+0x438>
{
/* Set bulk endpoint as double buffered */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
800db2a: 687a ldr r2, [r7, #4]
800db2c: 683b ldr r3, [r7, #0]
800db2e: 781b ldrb r3, [r3, #0]
800db30: 009b lsls r3, r3, #2
800db32: 4413 add r3, r2
800db34: 881b ldrh r3, [r3, #0]
800db36: b29b uxth r3, r3
800db38: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800db3c: f023 0370 bic.w r3, r3, #112 @ 0x70
800db40: f8a7 3082 strh.w r3, [r7, #130] @ 0x82
800db44: 687a ldr r2, [r7, #4]
800db46: 683b ldr r3, [r7, #0]
800db48: 781b ldrb r3, [r3, #0]
800db4a: 009b lsls r3, r3, #2
800db4c: 441a add r2, r3
800db4e: f8b7 3082 ldrh.w r3, [r7, #130] @ 0x82
800db52: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800db56: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800db5a: f443 4301 orr.w r3, r3, #33024 @ 0x8100
800db5e: f043 0380 orr.w r3, r3, #128 @ 0x80
800db62: b29b uxth r3, r3
800db64: 8013 strh r3, [r2, #0]
800db66: e01d b.n 800dba4 <USB_ActivateEndpoint+0x474>
}
else
{
/* Set the ISOC endpoint in double buffer mode */
PCD_CLEAR_EP_KIND(USBx, ep->num);
800db68: 687a ldr r2, [r7, #4]
800db6a: 683b ldr r3, [r7, #0]
800db6c: 781b ldrb r3, [r3, #0]
800db6e: 009b lsls r3, r3, #2
800db70: 4413 add r3, r2
800db72: 881b ldrh r3, [r3, #0]
800db74: b29b uxth r3, r3
800db76: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
800db7a: f023 0370 bic.w r3, r3, #112 @ 0x70
800db7e: f8a7 3084 strh.w r3, [r7, #132] @ 0x84
800db82: 687a ldr r2, [r7, #4]
800db84: 683b ldr r3, [r7, #0]
800db86: 781b ldrb r3, [r3, #0]
800db88: 009b lsls r3, r3, #2
800db8a: 441a add r2, r3
800db8c: f8b7 3084 ldrh.w r3, [r7, #132] @ 0x84
800db90: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800db94: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800db98: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800db9c: f043 0380 orr.w r3, r3, #128 @ 0x80
800dba0: b29b uxth r3, r3
800dba2: 8013 strh r3, [r2, #0]
}
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
800dba4: 687b ldr r3, [r7, #4]
800dba6: 67fb str r3, [r7, #124] @ 0x7c
800dba8: 687b ldr r3, [r7, #4]
800dbaa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800dbae: b29b uxth r3, r3
800dbb0: 461a mov r2, r3
800dbb2: 6ffb ldr r3, [r7, #124] @ 0x7c
800dbb4: 4413 add r3, r2
800dbb6: 67fb str r3, [r7, #124] @ 0x7c
800dbb8: 683b ldr r3, [r7, #0]
800dbba: 781b ldrb r3, [r3, #0]
800dbbc: 00da lsls r2, r3, #3
800dbbe: 6ffb ldr r3, [r7, #124] @ 0x7c
800dbc0: 4413 add r3, r2
800dbc2: f503 6380 add.w r3, r3, #1024 @ 0x400
800dbc6: 67bb str r3, [r7, #120] @ 0x78
800dbc8: 683b ldr r3, [r7, #0]
800dbca: 891b ldrh r3, [r3, #8]
800dbcc: 085b lsrs r3, r3, #1
800dbce: b29b uxth r3, r3
800dbd0: 005b lsls r3, r3, #1
800dbd2: b29a uxth r2, r3
800dbd4: 6fbb ldr r3, [r7, #120] @ 0x78
800dbd6: 801a strh r2, [r3, #0]
800dbd8: 687b ldr r3, [r7, #4]
800dbda: 677b str r3, [r7, #116] @ 0x74
800dbdc: 687b ldr r3, [r7, #4]
800dbde: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800dbe2: b29b uxth r3, r3
800dbe4: 461a mov r2, r3
800dbe6: 6f7b ldr r3, [r7, #116] @ 0x74
800dbe8: 4413 add r3, r2
800dbea: 677b str r3, [r7, #116] @ 0x74
800dbec: 683b ldr r3, [r7, #0]
800dbee: 781b ldrb r3, [r3, #0]
800dbf0: 00da lsls r2, r3, #3
800dbf2: 6f7b ldr r3, [r7, #116] @ 0x74
800dbf4: 4413 add r3, r2
800dbf6: f203 4304 addw r3, r3, #1028 @ 0x404
800dbfa: 673b str r3, [r7, #112] @ 0x70
800dbfc: 683b ldr r3, [r7, #0]
800dbfe: 895b ldrh r3, [r3, #10]
800dc00: 085b lsrs r3, r3, #1
800dc02: b29b uxth r3, r3
800dc04: 005b lsls r3, r3, #1
800dc06: b29a uxth r2, r3
800dc08: 6f3b ldr r3, [r7, #112] @ 0x70
800dc0a: 801a strh r2, [r3, #0]
if (ep->is_in == 0U)
800dc0c: 683b ldr r3, [r7, #0]
800dc0e: 785b ldrb r3, [r3, #1]
800dc10: 2b00 cmp r3, #0
800dc12: f040 81af bne.w 800df74 <USB_ActivateEndpoint+0x844>
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800dc16: 687a ldr r2, [r7, #4]
800dc18: 683b ldr r3, [r7, #0]
800dc1a: 781b ldrb r3, [r3, #0]
800dc1c: 009b lsls r3, r3, #2
800dc1e: 4413 add r3, r2
800dc20: 881b ldrh r3, [r3, #0]
800dc22: f8a7 3060 strh.w r3, [r7, #96] @ 0x60
800dc26: f8b7 3060 ldrh.w r3, [r7, #96] @ 0x60
800dc2a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800dc2e: 2b00 cmp r3, #0
800dc30: d01d beq.n 800dc6e <USB_ActivateEndpoint+0x53e>
800dc32: 687a ldr r2, [r7, #4]
800dc34: 683b ldr r3, [r7, #0]
800dc36: 781b ldrb r3, [r3, #0]
800dc38: 009b lsls r3, r3, #2
800dc3a: 4413 add r3, r2
800dc3c: 881b ldrh r3, [r3, #0]
800dc3e: b29b uxth r3, r3
800dc40: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800dc44: f023 0370 bic.w r3, r3, #112 @ 0x70
800dc48: f8a7 305e strh.w r3, [r7, #94] @ 0x5e
800dc4c: 687a ldr r2, [r7, #4]
800dc4e: 683b ldr r3, [r7, #0]
800dc50: 781b ldrb r3, [r3, #0]
800dc52: 009b lsls r3, r3, #2
800dc54: 441a add r2, r3
800dc56: f8b7 305e ldrh.w r3, [r7, #94] @ 0x5e
800dc5a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800dc5e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800dc62: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800dc66: f043 0380 orr.w r3, r3, #128 @ 0x80
800dc6a: b29b uxth r3, r3
800dc6c: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800dc6e: 687a ldr r2, [r7, #4]
800dc70: 683b ldr r3, [r7, #0]
800dc72: 781b ldrb r3, [r3, #0]
800dc74: 009b lsls r3, r3, #2
800dc76: 4413 add r3, r2
800dc78: 881b ldrh r3, [r3, #0]
800dc7a: f8a7 305c strh.w r3, [r7, #92] @ 0x5c
800dc7e: f8b7 305c ldrh.w r3, [r7, #92] @ 0x5c
800dc82: f003 0340 and.w r3, r3, #64 @ 0x40
800dc86: 2b00 cmp r3, #0
800dc88: d01d beq.n 800dcc6 <USB_ActivateEndpoint+0x596>
800dc8a: 687a ldr r2, [r7, #4]
800dc8c: 683b ldr r3, [r7, #0]
800dc8e: 781b ldrb r3, [r3, #0]
800dc90: 009b lsls r3, r3, #2
800dc92: 4413 add r3, r2
800dc94: 881b ldrh r3, [r3, #0]
800dc96: b29b uxth r3, r3
800dc98: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800dc9c: f023 0370 bic.w r3, r3, #112 @ 0x70
800dca0: f8a7 305a strh.w r3, [r7, #90] @ 0x5a
800dca4: 687a ldr r2, [r7, #4]
800dca6: 683b ldr r3, [r7, #0]
800dca8: 781b ldrb r3, [r3, #0]
800dcaa: 009b lsls r3, r3, #2
800dcac: 441a add r2, r3
800dcae: f8b7 305a ldrh.w r3, [r7, #90] @ 0x5a
800dcb2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800dcb6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800dcba: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800dcbe: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800dcc2: b29b uxth r3, r3
800dcc4: 8013 strh r3, [r2, #0]
/* Set endpoint RX count */
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
800dcc6: 683b ldr r3, [r7, #0]
800dcc8: 785b ldrb r3, [r3, #1]
800dcca: 2b00 cmp r3, #0
800dccc: d16b bne.n 800dda6 <USB_ActivateEndpoint+0x676>
800dcce: 687b ldr r3, [r7, #4]
800dcd0: 64fb str r3, [r7, #76] @ 0x4c
800dcd2: 687b ldr r3, [r7, #4]
800dcd4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800dcd8: b29b uxth r3, r3
800dcda: 461a mov r2, r3
800dcdc: 6cfb ldr r3, [r7, #76] @ 0x4c
800dcde: 4413 add r3, r2
800dce0: 64fb str r3, [r7, #76] @ 0x4c
800dce2: 683b ldr r3, [r7, #0]
800dce4: 781b ldrb r3, [r3, #0]
800dce6: 00da lsls r2, r3, #3
800dce8: 6cfb ldr r3, [r7, #76] @ 0x4c
800dcea: 4413 add r3, r2
800dcec: f203 4302 addw r3, r3, #1026 @ 0x402
800dcf0: 64bb str r3, [r7, #72] @ 0x48
800dcf2: 6cbb ldr r3, [r7, #72] @ 0x48
800dcf4: 881b ldrh r3, [r3, #0]
800dcf6: b29b uxth r3, r3
800dcf8: f3c3 0309 ubfx r3, r3, #0, #10
800dcfc: b29a uxth r2, r3
800dcfe: 6cbb ldr r3, [r7, #72] @ 0x48
800dd00: 801a strh r2, [r3, #0]
800dd02: 683b ldr r3, [r7, #0]
800dd04: 691b ldr r3, [r3, #16]
800dd06: 2b00 cmp r3, #0
800dd08: d10a bne.n 800dd20 <USB_ActivateEndpoint+0x5f0>
800dd0a: 6cbb ldr r3, [r7, #72] @ 0x48
800dd0c: 881b ldrh r3, [r3, #0]
800dd0e: b29b uxth r3, r3
800dd10: ea6f 4343 mvn.w r3, r3, lsl #17
800dd14: ea6f 4353 mvn.w r3, r3, lsr #17
800dd18: b29a uxth r2, r3
800dd1a: 6cbb ldr r3, [r7, #72] @ 0x48
800dd1c: 801a strh r2, [r3, #0]
800dd1e: e05d b.n 800dddc <USB_ActivateEndpoint+0x6ac>
800dd20: 683b ldr r3, [r7, #0]
800dd22: 691b ldr r3, [r3, #16]
800dd24: 2b3e cmp r3, #62 @ 0x3e
800dd26: d81c bhi.n 800dd62 <USB_ActivateEndpoint+0x632>
800dd28: 683b ldr r3, [r7, #0]
800dd2a: 691b ldr r3, [r3, #16]
800dd2c: 085b lsrs r3, r3, #1
800dd2e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
800dd32: 683b ldr r3, [r7, #0]
800dd34: 691b ldr r3, [r3, #16]
800dd36: f003 0301 and.w r3, r3, #1
800dd3a: 2b00 cmp r3, #0
800dd3c: d004 beq.n 800dd48 <USB_ActivateEndpoint+0x618>
800dd3e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800dd42: 3301 adds r3, #1
800dd44: f8c7 308c str.w r3, [r7, #140] @ 0x8c
800dd48: 6cbb ldr r3, [r7, #72] @ 0x48
800dd4a: 881b ldrh r3, [r3, #0]
800dd4c: b29a uxth r2, r3
800dd4e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800dd52: b29b uxth r3, r3
800dd54: 029b lsls r3, r3, #10
800dd56: b29b uxth r3, r3
800dd58: 4313 orrs r3, r2
800dd5a: b29a uxth r2, r3
800dd5c: 6cbb ldr r3, [r7, #72] @ 0x48
800dd5e: 801a strh r2, [r3, #0]
800dd60: e03c b.n 800dddc <USB_ActivateEndpoint+0x6ac>
800dd62: 683b ldr r3, [r7, #0]
800dd64: 691b ldr r3, [r3, #16]
800dd66: 095b lsrs r3, r3, #5
800dd68: f8c7 308c str.w r3, [r7, #140] @ 0x8c
800dd6c: 683b ldr r3, [r7, #0]
800dd6e: 691b ldr r3, [r3, #16]
800dd70: f003 031f and.w r3, r3, #31
800dd74: 2b00 cmp r3, #0
800dd76: d104 bne.n 800dd82 <USB_ActivateEndpoint+0x652>
800dd78: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800dd7c: 3b01 subs r3, #1
800dd7e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
800dd82: 6cbb ldr r3, [r7, #72] @ 0x48
800dd84: 881b ldrh r3, [r3, #0]
800dd86: b29a uxth r2, r3
800dd88: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
800dd8c: b29b uxth r3, r3
800dd8e: 029b lsls r3, r3, #10
800dd90: b29b uxth r3, r3
800dd92: 4313 orrs r3, r2
800dd94: b29b uxth r3, r3
800dd96: ea6f 4343 mvn.w r3, r3, lsl #17
800dd9a: ea6f 4353 mvn.w r3, r3, lsr #17
800dd9e: b29a uxth r2, r3
800dda0: 6cbb ldr r3, [r7, #72] @ 0x48
800dda2: 801a strh r2, [r3, #0]
800dda4: e01a b.n 800dddc <USB_ActivateEndpoint+0x6ac>
800dda6: 683b ldr r3, [r7, #0]
800dda8: 785b ldrb r3, [r3, #1]
800ddaa: 2b01 cmp r3, #1
800ddac: d116 bne.n 800dddc <USB_ActivateEndpoint+0x6ac>
800ddae: 687b ldr r3, [r7, #4]
800ddb0: 657b str r3, [r7, #84] @ 0x54
800ddb2: 687b ldr r3, [r7, #4]
800ddb4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800ddb8: b29b uxth r3, r3
800ddba: 461a mov r2, r3
800ddbc: 6d7b ldr r3, [r7, #84] @ 0x54
800ddbe: 4413 add r3, r2
800ddc0: 657b str r3, [r7, #84] @ 0x54
800ddc2: 683b ldr r3, [r7, #0]
800ddc4: 781b ldrb r3, [r3, #0]
800ddc6: 00da lsls r2, r3, #3
800ddc8: 6d7b ldr r3, [r7, #84] @ 0x54
800ddca: 4413 add r3, r2
800ddcc: f203 4302 addw r3, r3, #1026 @ 0x402
800ddd0: 653b str r3, [r7, #80] @ 0x50
800ddd2: 683b ldr r3, [r7, #0]
800ddd4: 691b ldr r3, [r3, #16]
800ddd6: b29a uxth r2, r3
800ddd8: 6d3b ldr r3, [r7, #80] @ 0x50
800ddda: 801a strh r2, [r3, #0]
800dddc: 687b ldr r3, [r7, #4]
800ddde: 647b str r3, [r7, #68] @ 0x44
800dde0: 683b ldr r3, [r7, #0]
800dde2: 785b ldrb r3, [r3, #1]
800dde4: 2b00 cmp r3, #0
800dde6: d16b bne.n 800dec0 <USB_ActivateEndpoint+0x790>
800dde8: 687b ldr r3, [r7, #4]
800ddea: 63fb str r3, [r7, #60] @ 0x3c
800ddec: 687b ldr r3, [r7, #4]
800ddee: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800ddf2: b29b uxth r3, r3
800ddf4: 461a mov r2, r3
800ddf6: 6bfb ldr r3, [r7, #60] @ 0x3c
800ddf8: 4413 add r3, r2
800ddfa: 63fb str r3, [r7, #60] @ 0x3c
800ddfc: 683b ldr r3, [r7, #0]
800ddfe: 781b ldrb r3, [r3, #0]
800de00: 00da lsls r2, r3, #3
800de02: 6bfb ldr r3, [r7, #60] @ 0x3c
800de04: 4413 add r3, r2
800de06: f203 4306 addw r3, r3, #1030 @ 0x406
800de0a: 63bb str r3, [r7, #56] @ 0x38
800de0c: 6bbb ldr r3, [r7, #56] @ 0x38
800de0e: 881b ldrh r3, [r3, #0]
800de10: b29b uxth r3, r3
800de12: f3c3 0309 ubfx r3, r3, #0, #10
800de16: b29a uxth r2, r3
800de18: 6bbb ldr r3, [r7, #56] @ 0x38
800de1a: 801a strh r2, [r3, #0]
800de1c: 683b ldr r3, [r7, #0]
800de1e: 691b ldr r3, [r3, #16]
800de20: 2b00 cmp r3, #0
800de22: d10a bne.n 800de3a <USB_ActivateEndpoint+0x70a>
800de24: 6bbb ldr r3, [r7, #56] @ 0x38
800de26: 881b ldrh r3, [r3, #0]
800de28: b29b uxth r3, r3
800de2a: ea6f 4343 mvn.w r3, r3, lsl #17
800de2e: ea6f 4353 mvn.w r3, r3, lsr #17
800de32: b29a uxth r2, r3
800de34: 6bbb ldr r3, [r7, #56] @ 0x38
800de36: 801a strh r2, [r3, #0]
800de38: e05b b.n 800def2 <USB_ActivateEndpoint+0x7c2>
800de3a: 683b ldr r3, [r7, #0]
800de3c: 691b ldr r3, [r3, #16]
800de3e: 2b3e cmp r3, #62 @ 0x3e
800de40: d81c bhi.n 800de7c <USB_ActivateEndpoint+0x74c>
800de42: 683b ldr r3, [r7, #0]
800de44: 691b ldr r3, [r3, #16]
800de46: 085b lsrs r3, r3, #1
800de48: f8c7 3088 str.w r3, [r7, #136] @ 0x88
800de4c: 683b ldr r3, [r7, #0]
800de4e: 691b ldr r3, [r3, #16]
800de50: f003 0301 and.w r3, r3, #1
800de54: 2b00 cmp r3, #0
800de56: d004 beq.n 800de62 <USB_ActivateEndpoint+0x732>
800de58: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
800de5c: 3301 adds r3, #1
800de5e: f8c7 3088 str.w r3, [r7, #136] @ 0x88
800de62: 6bbb ldr r3, [r7, #56] @ 0x38
800de64: 881b ldrh r3, [r3, #0]
800de66: b29a uxth r2, r3
800de68: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
800de6c: b29b uxth r3, r3
800de6e: 029b lsls r3, r3, #10
800de70: b29b uxth r3, r3
800de72: 4313 orrs r3, r2
800de74: b29a uxth r2, r3
800de76: 6bbb ldr r3, [r7, #56] @ 0x38
800de78: 801a strh r2, [r3, #0]
800de7a: e03a b.n 800def2 <USB_ActivateEndpoint+0x7c2>
800de7c: 683b ldr r3, [r7, #0]
800de7e: 691b ldr r3, [r3, #16]
800de80: 095b lsrs r3, r3, #5
800de82: f8c7 3088 str.w r3, [r7, #136] @ 0x88
800de86: 683b ldr r3, [r7, #0]
800de88: 691b ldr r3, [r3, #16]
800de8a: f003 031f and.w r3, r3, #31
800de8e: 2b00 cmp r3, #0
800de90: d104 bne.n 800de9c <USB_ActivateEndpoint+0x76c>
800de92: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
800de96: 3b01 subs r3, #1
800de98: f8c7 3088 str.w r3, [r7, #136] @ 0x88
800de9c: 6bbb ldr r3, [r7, #56] @ 0x38
800de9e: 881b ldrh r3, [r3, #0]
800dea0: b29a uxth r2, r3
800dea2: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
800dea6: b29b uxth r3, r3
800dea8: 029b lsls r3, r3, #10
800deaa: b29b uxth r3, r3
800deac: 4313 orrs r3, r2
800deae: b29b uxth r3, r3
800deb0: ea6f 4343 mvn.w r3, r3, lsl #17
800deb4: ea6f 4353 mvn.w r3, r3, lsr #17
800deb8: b29a uxth r2, r3
800deba: 6bbb ldr r3, [r7, #56] @ 0x38
800debc: 801a strh r2, [r3, #0]
800debe: e018 b.n 800def2 <USB_ActivateEndpoint+0x7c2>
800dec0: 683b ldr r3, [r7, #0]
800dec2: 785b ldrb r3, [r3, #1]
800dec4: 2b01 cmp r3, #1
800dec6: d114 bne.n 800def2 <USB_ActivateEndpoint+0x7c2>
800dec8: 687b ldr r3, [r7, #4]
800deca: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800dece: b29b uxth r3, r3
800ded0: 461a mov r2, r3
800ded2: 6c7b ldr r3, [r7, #68] @ 0x44
800ded4: 4413 add r3, r2
800ded6: 647b str r3, [r7, #68] @ 0x44
800ded8: 683b ldr r3, [r7, #0]
800deda: 781b ldrb r3, [r3, #0]
800dedc: 00da lsls r2, r3, #3
800dede: 6c7b ldr r3, [r7, #68] @ 0x44
800dee0: 4413 add r3, r2
800dee2: f203 4306 addw r3, r3, #1030 @ 0x406
800dee6: 643b str r3, [r7, #64] @ 0x40
800dee8: 683b ldr r3, [r7, #0]
800deea: 691b ldr r3, [r3, #16]
800deec: b29a uxth r2, r3
800deee: 6c3b ldr r3, [r7, #64] @ 0x40
800def0: 801a strh r2, [r3, #0]
/* Set endpoint RX to valid state */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
800def2: 687a ldr r2, [r7, #4]
800def4: 683b ldr r3, [r7, #0]
800def6: 781b ldrb r3, [r3, #0]
800def8: 009b lsls r3, r3, #2
800defa: 4413 add r3, r2
800defc: 881b ldrh r3, [r3, #0]
800defe: b29b uxth r3, r3
800df00: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800df04: f023 0370 bic.w r3, r3, #112 @ 0x70
800df08: 86fb strh r3, [r7, #54] @ 0x36
800df0a: 8efb ldrh r3, [r7, #54] @ 0x36
800df0c: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800df10: 86fb strh r3, [r7, #54] @ 0x36
800df12: 8efb ldrh r3, [r7, #54] @ 0x36
800df14: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800df18: 86fb strh r3, [r7, #54] @ 0x36
800df1a: 687a ldr r2, [r7, #4]
800df1c: 683b ldr r3, [r7, #0]
800df1e: 781b ldrb r3, [r3, #0]
800df20: 009b lsls r3, r3, #2
800df22: 441a add r2, r3
800df24: 8efb ldrh r3, [r7, #54] @ 0x36
800df26: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800df2a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800df2e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800df32: f043 0380 orr.w r3, r3, #128 @ 0x80
800df36: b29b uxth r3, r3
800df38: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800df3a: 687a ldr r2, [r7, #4]
800df3c: 683b ldr r3, [r7, #0]
800df3e: 781b ldrb r3, [r3, #0]
800df40: 009b lsls r3, r3, #2
800df42: 4413 add r3, r2
800df44: 881b ldrh r3, [r3, #0]
800df46: b29b uxth r3, r3
800df48: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800df4c: f023 0340 bic.w r3, r3, #64 @ 0x40
800df50: 86bb strh r3, [r7, #52] @ 0x34
800df52: 687a ldr r2, [r7, #4]
800df54: 683b ldr r3, [r7, #0]
800df56: 781b ldrb r3, [r3, #0]
800df58: 009b lsls r3, r3, #2
800df5a: 441a add r2, r3
800df5c: 8ebb ldrh r3, [r7, #52] @ 0x34
800df5e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800df62: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800df66: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800df6a: f043 0380 orr.w r3, r3, #128 @ 0x80
800df6e: b29b uxth r3, r3
800df70: 8013 strh r3, [r2, #0]
800df72: e0bc b.n 800e0ee <USB_ActivateEndpoint+0x9be>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800df74: 687a ldr r2, [r7, #4]
800df76: 683b ldr r3, [r7, #0]
800df78: 781b ldrb r3, [r3, #0]
800df7a: 009b lsls r3, r3, #2
800df7c: 4413 add r3, r2
800df7e: 881b ldrh r3, [r3, #0]
800df80: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
800df84: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
800df88: f403 4380 and.w r3, r3, #16384 @ 0x4000
800df8c: 2b00 cmp r3, #0
800df8e: d01d beq.n 800dfcc <USB_ActivateEndpoint+0x89c>
800df90: 687a ldr r2, [r7, #4]
800df92: 683b ldr r3, [r7, #0]
800df94: 781b ldrb r3, [r3, #0]
800df96: 009b lsls r3, r3, #2
800df98: 4413 add r3, r2
800df9a: 881b ldrh r3, [r3, #0]
800df9c: b29b uxth r3, r3
800df9e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800dfa2: f023 0370 bic.w r3, r3, #112 @ 0x70
800dfa6: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
800dfaa: 687a ldr r2, [r7, #4]
800dfac: 683b ldr r3, [r7, #0]
800dfae: 781b ldrb r3, [r3, #0]
800dfb0: 009b lsls r3, r3, #2
800dfb2: 441a add r2, r3
800dfb4: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
800dfb8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800dfbc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800dfc0: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800dfc4: f043 0380 orr.w r3, r3, #128 @ 0x80
800dfc8: b29b uxth r3, r3
800dfca: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800dfcc: 687a ldr r2, [r7, #4]
800dfce: 683b ldr r3, [r7, #0]
800dfd0: 781b ldrb r3, [r3, #0]
800dfd2: 009b lsls r3, r3, #2
800dfd4: 4413 add r3, r2
800dfd6: 881b ldrh r3, [r3, #0]
800dfd8: f8a7 306a strh.w r3, [r7, #106] @ 0x6a
800dfdc: f8b7 306a ldrh.w r3, [r7, #106] @ 0x6a
800dfe0: f003 0340 and.w r3, r3, #64 @ 0x40
800dfe4: 2b00 cmp r3, #0
800dfe6: d01d beq.n 800e024 <USB_ActivateEndpoint+0x8f4>
800dfe8: 687a ldr r2, [r7, #4]
800dfea: 683b ldr r3, [r7, #0]
800dfec: 781b ldrb r3, [r3, #0]
800dfee: 009b lsls r3, r3, #2
800dff0: 4413 add r3, r2
800dff2: 881b ldrh r3, [r3, #0]
800dff4: b29b uxth r3, r3
800dff6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800dffa: f023 0370 bic.w r3, r3, #112 @ 0x70
800dffe: f8a7 3068 strh.w r3, [r7, #104] @ 0x68
800e002: 687a ldr r2, [r7, #4]
800e004: 683b ldr r3, [r7, #0]
800e006: 781b ldrb r3, [r3, #0]
800e008: 009b lsls r3, r3, #2
800e00a: 441a add r2, r3
800e00c: f8b7 3068 ldrh.w r3, [r7, #104] @ 0x68
800e010: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e014: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e018: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e01c: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800e020: b29b uxth r3, r3
800e022: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800e024: 683b ldr r3, [r7, #0]
800e026: 78db ldrb r3, [r3, #3]
800e028: 2b01 cmp r3, #1
800e02a: d024 beq.n 800e076 <USB_ActivateEndpoint+0x946>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
800e02c: 687a ldr r2, [r7, #4]
800e02e: 683b ldr r3, [r7, #0]
800e030: 781b ldrb r3, [r3, #0]
800e032: 009b lsls r3, r3, #2
800e034: 4413 add r3, r2
800e036: 881b ldrh r3, [r3, #0]
800e038: b29b uxth r3, r3
800e03a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e03e: f023 0340 bic.w r3, r3, #64 @ 0x40
800e042: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
800e046: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
800e04a: f083 0320 eor.w r3, r3, #32
800e04e: f8a7 3064 strh.w r3, [r7, #100] @ 0x64
800e052: 687a ldr r2, [r7, #4]
800e054: 683b ldr r3, [r7, #0]
800e056: 781b ldrb r3, [r3, #0]
800e058: 009b lsls r3, r3, #2
800e05a: 441a add r2, r3
800e05c: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64
800e060: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e064: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e068: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e06c: f043 0380 orr.w r3, r3, #128 @ 0x80
800e070: b29b uxth r3, r3
800e072: 8013 strh r3, [r2, #0]
800e074: e01d b.n 800e0b2 <USB_ActivateEndpoint+0x982>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800e076: 687a ldr r2, [r7, #4]
800e078: 683b ldr r3, [r7, #0]
800e07a: 781b ldrb r3, [r3, #0]
800e07c: 009b lsls r3, r3, #2
800e07e: 4413 add r3, r2
800e080: 881b ldrh r3, [r3, #0]
800e082: b29b uxth r3, r3
800e084: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e088: f023 0340 bic.w r3, r3, #64 @ 0x40
800e08c: f8a7 3066 strh.w r3, [r7, #102] @ 0x66
800e090: 687a ldr r2, [r7, #4]
800e092: 683b ldr r3, [r7, #0]
800e094: 781b ldrb r3, [r3, #0]
800e096: 009b lsls r3, r3, #2
800e098: 441a add r2, r3
800e09a: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66
800e09e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e0a2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e0a6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e0aa: f043 0380 orr.w r3, r3, #128 @ 0x80
800e0ae: b29b uxth r3, r3
800e0b0: 8013 strh r3, [r2, #0]
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
800e0b2: 687a ldr r2, [r7, #4]
800e0b4: 683b ldr r3, [r7, #0]
800e0b6: 781b ldrb r3, [r3, #0]
800e0b8: 009b lsls r3, r3, #2
800e0ba: 4413 add r3, r2
800e0bc: 881b ldrh r3, [r3, #0]
800e0be: b29b uxth r3, r3
800e0c0: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800e0c4: f023 0370 bic.w r3, r3, #112 @ 0x70
800e0c8: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
800e0cc: 687a ldr r2, [r7, #4]
800e0ce: 683b ldr r3, [r7, #0]
800e0d0: 781b ldrb r3, [r3, #0]
800e0d2: 009b lsls r3, r3, #2
800e0d4: 441a add r2, r3
800e0d6: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
800e0da: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e0de: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e0e2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e0e6: f043 0380 orr.w r3, r3, #128 @ 0x80
800e0ea: b29b uxth r3, r3
800e0ec: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return ret;
800e0ee: f897 3097 ldrb.w r3, [r7, #151] @ 0x97
}
800e0f2: 4618 mov r0, r3
800e0f4: 379c adds r7, #156 @ 0x9c
800e0f6: 46bd mov sp, r7
800e0f8: f85d 7b04 ldr.w r7, [sp], #4
800e0fc: 4770 bx lr
800e0fe: bf00 nop
0800e100 <USB_DeactivateEndpoint>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
800e100: b480 push {r7}
800e102: b08d sub sp, #52 @ 0x34
800e104: af00 add r7, sp, #0
800e106: 6078 str r0, [r7, #4]
800e108: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
800e10a: 683b ldr r3, [r7, #0]
800e10c: 7b1b ldrb r3, [r3, #12]
800e10e: 2b00 cmp r3, #0
800e110: f040 808e bne.w 800e230 <USB_DeactivateEndpoint+0x130>
{
if (ep->is_in != 0U)
800e114: 683b ldr r3, [r7, #0]
800e116: 785b ldrb r3, [r3, #1]
800e118: 2b00 cmp r3, #0
800e11a: d044 beq.n 800e1a6 <USB_DeactivateEndpoint+0xa6>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800e11c: 687a ldr r2, [r7, #4]
800e11e: 683b ldr r3, [r7, #0]
800e120: 781b ldrb r3, [r3, #0]
800e122: 009b lsls r3, r3, #2
800e124: 4413 add r3, r2
800e126: 881b ldrh r3, [r3, #0]
800e128: 81bb strh r3, [r7, #12]
800e12a: 89bb ldrh r3, [r7, #12]
800e12c: f003 0340 and.w r3, r3, #64 @ 0x40
800e130: 2b00 cmp r3, #0
800e132: d01b beq.n 800e16c <USB_DeactivateEndpoint+0x6c>
800e134: 687a ldr r2, [r7, #4]
800e136: 683b ldr r3, [r7, #0]
800e138: 781b ldrb r3, [r3, #0]
800e13a: 009b lsls r3, r3, #2
800e13c: 4413 add r3, r2
800e13e: 881b ldrh r3, [r3, #0]
800e140: b29b uxth r3, r3
800e142: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e146: f023 0370 bic.w r3, r3, #112 @ 0x70
800e14a: 817b strh r3, [r7, #10]
800e14c: 687a ldr r2, [r7, #4]
800e14e: 683b ldr r3, [r7, #0]
800e150: 781b ldrb r3, [r3, #0]
800e152: 009b lsls r3, r3, #2
800e154: 441a add r2, r3
800e156: 897b ldrh r3, [r7, #10]
800e158: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e15c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e160: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e164: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800e168: b29b uxth r3, r3
800e16a: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800e16c: 687a ldr r2, [r7, #4]
800e16e: 683b ldr r3, [r7, #0]
800e170: 781b ldrb r3, [r3, #0]
800e172: 009b lsls r3, r3, #2
800e174: 4413 add r3, r2
800e176: 881b ldrh r3, [r3, #0]
800e178: b29b uxth r3, r3
800e17a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e17e: f023 0340 bic.w r3, r3, #64 @ 0x40
800e182: 813b strh r3, [r7, #8]
800e184: 687a ldr r2, [r7, #4]
800e186: 683b ldr r3, [r7, #0]
800e188: 781b ldrb r3, [r3, #0]
800e18a: 009b lsls r3, r3, #2
800e18c: 441a add r2, r3
800e18e: 893b ldrh r3, [r7, #8]
800e190: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e194: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e198: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e19c: f043 0380 orr.w r3, r3, #128 @ 0x80
800e1a0: b29b uxth r3, r3
800e1a2: 8013 strh r3, [r2, #0]
800e1a4: e192 b.n 800e4cc <USB_DeactivateEndpoint+0x3cc>
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800e1a6: 687a ldr r2, [r7, #4]
800e1a8: 683b ldr r3, [r7, #0]
800e1aa: 781b ldrb r3, [r3, #0]
800e1ac: 009b lsls r3, r3, #2
800e1ae: 4413 add r3, r2
800e1b0: 881b ldrh r3, [r3, #0]
800e1b2: 827b strh r3, [r7, #18]
800e1b4: 8a7b ldrh r3, [r7, #18]
800e1b6: f403 4380 and.w r3, r3, #16384 @ 0x4000
800e1ba: 2b00 cmp r3, #0
800e1bc: d01b beq.n 800e1f6 <USB_DeactivateEndpoint+0xf6>
800e1be: 687a ldr r2, [r7, #4]
800e1c0: 683b ldr r3, [r7, #0]
800e1c2: 781b ldrb r3, [r3, #0]
800e1c4: 009b lsls r3, r3, #2
800e1c6: 4413 add r3, r2
800e1c8: 881b ldrh r3, [r3, #0]
800e1ca: b29b uxth r3, r3
800e1cc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e1d0: f023 0370 bic.w r3, r3, #112 @ 0x70
800e1d4: 823b strh r3, [r7, #16]
800e1d6: 687a ldr r2, [r7, #4]
800e1d8: 683b ldr r3, [r7, #0]
800e1da: 781b ldrb r3, [r3, #0]
800e1dc: 009b lsls r3, r3, #2
800e1de: 441a add r2, r3
800e1e0: 8a3b ldrh r3, [r7, #16]
800e1e2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e1e6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e1ea: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800e1ee: f043 0380 orr.w r3, r3, #128 @ 0x80
800e1f2: b29b uxth r3, r3
800e1f4: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
800e1f6: 687a ldr r2, [r7, #4]
800e1f8: 683b ldr r3, [r7, #0]
800e1fa: 781b ldrb r3, [r3, #0]
800e1fc: 009b lsls r3, r3, #2
800e1fe: 4413 add r3, r2
800e200: 881b ldrh r3, [r3, #0]
800e202: b29b uxth r3, r3
800e204: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800e208: f023 0370 bic.w r3, r3, #112 @ 0x70
800e20c: 81fb strh r3, [r7, #14]
800e20e: 687a ldr r2, [r7, #4]
800e210: 683b ldr r3, [r7, #0]
800e212: 781b ldrb r3, [r3, #0]
800e214: 009b lsls r3, r3, #2
800e216: 441a add r2, r3
800e218: 89fb ldrh r3, [r7, #14]
800e21a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e21e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e222: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e226: f043 0380 orr.w r3, r3, #128 @ 0x80
800e22a: b29b uxth r3, r3
800e22c: 8013 strh r3, [r2, #0]
800e22e: e14d b.n 800e4cc <USB_DeactivateEndpoint+0x3cc>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
if (ep->is_in == 0U)
800e230: 683b ldr r3, [r7, #0]
800e232: 785b ldrb r3, [r3, #1]
800e234: 2b00 cmp r3, #0
800e236: f040 80a5 bne.w 800e384 <USB_DeactivateEndpoint+0x284>
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800e23a: 687a ldr r2, [r7, #4]
800e23c: 683b ldr r3, [r7, #0]
800e23e: 781b ldrb r3, [r3, #0]
800e240: 009b lsls r3, r3, #2
800e242: 4413 add r3, r2
800e244: 881b ldrh r3, [r3, #0]
800e246: 843b strh r3, [r7, #32]
800e248: 8c3b ldrh r3, [r7, #32]
800e24a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800e24e: 2b00 cmp r3, #0
800e250: d01b beq.n 800e28a <USB_DeactivateEndpoint+0x18a>
800e252: 687a ldr r2, [r7, #4]
800e254: 683b ldr r3, [r7, #0]
800e256: 781b ldrb r3, [r3, #0]
800e258: 009b lsls r3, r3, #2
800e25a: 4413 add r3, r2
800e25c: 881b ldrh r3, [r3, #0]
800e25e: b29b uxth r3, r3
800e260: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e264: f023 0370 bic.w r3, r3, #112 @ 0x70
800e268: 83fb strh r3, [r7, #30]
800e26a: 687a ldr r2, [r7, #4]
800e26c: 683b ldr r3, [r7, #0]
800e26e: 781b ldrb r3, [r3, #0]
800e270: 009b lsls r3, r3, #2
800e272: 441a add r2, r3
800e274: 8bfb ldrh r3, [r7, #30]
800e276: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e27a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e27e: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800e282: f043 0380 orr.w r3, r3, #128 @ 0x80
800e286: b29b uxth r3, r3
800e288: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800e28a: 687a ldr r2, [r7, #4]
800e28c: 683b ldr r3, [r7, #0]
800e28e: 781b ldrb r3, [r3, #0]
800e290: 009b lsls r3, r3, #2
800e292: 4413 add r3, r2
800e294: 881b ldrh r3, [r3, #0]
800e296: 83bb strh r3, [r7, #28]
800e298: 8bbb ldrh r3, [r7, #28]
800e29a: f003 0340 and.w r3, r3, #64 @ 0x40
800e29e: 2b00 cmp r3, #0
800e2a0: d01b beq.n 800e2da <USB_DeactivateEndpoint+0x1da>
800e2a2: 687a ldr r2, [r7, #4]
800e2a4: 683b ldr r3, [r7, #0]
800e2a6: 781b ldrb r3, [r3, #0]
800e2a8: 009b lsls r3, r3, #2
800e2aa: 4413 add r3, r2
800e2ac: 881b ldrh r3, [r3, #0]
800e2ae: b29b uxth r3, r3
800e2b0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e2b4: f023 0370 bic.w r3, r3, #112 @ 0x70
800e2b8: 837b strh r3, [r7, #26]
800e2ba: 687a ldr r2, [r7, #4]
800e2bc: 683b ldr r3, [r7, #0]
800e2be: 781b ldrb r3, [r3, #0]
800e2c0: 009b lsls r3, r3, #2
800e2c2: 441a add r2, r3
800e2c4: 8b7b ldrh r3, [r7, #26]
800e2c6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e2ca: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e2ce: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e2d2: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800e2d6: b29b uxth r3, r3
800e2d8: 8013 strh r3, [r2, #0]
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(USBx, ep->num);
800e2da: 687a ldr r2, [r7, #4]
800e2dc: 683b ldr r3, [r7, #0]
800e2de: 781b ldrb r3, [r3, #0]
800e2e0: 009b lsls r3, r3, #2
800e2e2: 4413 add r3, r2
800e2e4: 881b ldrh r3, [r3, #0]
800e2e6: b29b uxth r3, r3
800e2e8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e2ec: f023 0370 bic.w r3, r3, #112 @ 0x70
800e2f0: 833b strh r3, [r7, #24]
800e2f2: 687a ldr r2, [r7, #4]
800e2f4: 683b ldr r3, [r7, #0]
800e2f6: 781b ldrb r3, [r3, #0]
800e2f8: 009b lsls r3, r3, #2
800e2fa: 441a add r2, r3
800e2fc: 8b3b ldrh r3, [r7, #24]
800e2fe: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e302: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e306: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e30a: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800e30e: b29b uxth r3, r3
800e310: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
800e312: 687a ldr r2, [r7, #4]
800e314: 683b ldr r3, [r7, #0]
800e316: 781b ldrb r3, [r3, #0]
800e318: 009b lsls r3, r3, #2
800e31a: 4413 add r3, r2
800e31c: 881b ldrh r3, [r3, #0]
800e31e: b29b uxth r3, r3
800e320: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800e324: f023 0370 bic.w r3, r3, #112 @ 0x70
800e328: 82fb strh r3, [r7, #22]
800e32a: 687a ldr r2, [r7, #4]
800e32c: 683b ldr r3, [r7, #0]
800e32e: 781b ldrb r3, [r3, #0]
800e330: 009b lsls r3, r3, #2
800e332: 441a add r2, r3
800e334: 8afb ldrh r3, [r7, #22]
800e336: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e33a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e33e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e342: f043 0380 orr.w r3, r3, #128 @ 0x80
800e346: b29b uxth r3, r3
800e348: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800e34a: 687a ldr r2, [r7, #4]
800e34c: 683b ldr r3, [r7, #0]
800e34e: 781b ldrb r3, [r3, #0]
800e350: 009b lsls r3, r3, #2
800e352: 4413 add r3, r2
800e354: 881b ldrh r3, [r3, #0]
800e356: b29b uxth r3, r3
800e358: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e35c: f023 0340 bic.w r3, r3, #64 @ 0x40
800e360: 82bb strh r3, [r7, #20]
800e362: 687a ldr r2, [r7, #4]
800e364: 683b ldr r3, [r7, #0]
800e366: 781b ldrb r3, [r3, #0]
800e368: 009b lsls r3, r3, #2
800e36a: 441a add r2, r3
800e36c: 8abb ldrh r3, [r7, #20]
800e36e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e372: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e376: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e37a: f043 0380 orr.w r3, r3, #128 @ 0x80
800e37e: b29b uxth r3, r3
800e380: 8013 strh r3, [r2, #0]
800e382: e0a3 b.n 800e4cc <USB_DeactivateEndpoint+0x3cc>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800e384: 687a ldr r2, [r7, #4]
800e386: 683b ldr r3, [r7, #0]
800e388: 781b ldrb r3, [r3, #0]
800e38a: 009b lsls r3, r3, #2
800e38c: 4413 add r3, r2
800e38e: 881b ldrh r3, [r3, #0]
800e390: 85fb strh r3, [r7, #46] @ 0x2e
800e392: 8dfb ldrh r3, [r7, #46] @ 0x2e
800e394: f403 4380 and.w r3, r3, #16384 @ 0x4000
800e398: 2b00 cmp r3, #0
800e39a: d01b beq.n 800e3d4 <USB_DeactivateEndpoint+0x2d4>
800e39c: 687a ldr r2, [r7, #4]
800e39e: 683b ldr r3, [r7, #0]
800e3a0: 781b ldrb r3, [r3, #0]
800e3a2: 009b lsls r3, r3, #2
800e3a4: 4413 add r3, r2
800e3a6: 881b ldrh r3, [r3, #0]
800e3a8: b29b uxth r3, r3
800e3aa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e3ae: f023 0370 bic.w r3, r3, #112 @ 0x70
800e3b2: 85bb strh r3, [r7, #44] @ 0x2c
800e3b4: 687a ldr r2, [r7, #4]
800e3b6: 683b ldr r3, [r7, #0]
800e3b8: 781b ldrb r3, [r3, #0]
800e3ba: 009b lsls r3, r3, #2
800e3bc: 441a add r2, r3
800e3be: 8dbb ldrh r3, [r7, #44] @ 0x2c
800e3c0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e3c4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e3c8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800e3cc: f043 0380 orr.w r3, r3, #128 @ 0x80
800e3d0: b29b uxth r3, r3
800e3d2: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800e3d4: 687a ldr r2, [r7, #4]
800e3d6: 683b ldr r3, [r7, #0]
800e3d8: 781b ldrb r3, [r3, #0]
800e3da: 009b lsls r3, r3, #2
800e3dc: 4413 add r3, r2
800e3de: 881b ldrh r3, [r3, #0]
800e3e0: 857b strh r3, [r7, #42] @ 0x2a
800e3e2: 8d7b ldrh r3, [r7, #42] @ 0x2a
800e3e4: f003 0340 and.w r3, r3, #64 @ 0x40
800e3e8: 2b00 cmp r3, #0
800e3ea: d01b beq.n 800e424 <USB_DeactivateEndpoint+0x324>
800e3ec: 687a ldr r2, [r7, #4]
800e3ee: 683b ldr r3, [r7, #0]
800e3f0: 781b ldrb r3, [r3, #0]
800e3f2: 009b lsls r3, r3, #2
800e3f4: 4413 add r3, r2
800e3f6: 881b ldrh r3, [r3, #0]
800e3f8: b29b uxth r3, r3
800e3fa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e3fe: f023 0370 bic.w r3, r3, #112 @ 0x70
800e402: 853b strh r3, [r7, #40] @ 0x28
800e404: 687a ldr r2, [r7, #4]
800e406: 683b ldr r3, [r7, #0]
800e408: 781b ldrb r3, [r3, #0]
800e40a: 009b lsls r3, r3, #2
800e40c: 441a add r2, r3
800e40e: 8d3b ldrh r3, [r7, #40] @ 0x28
800e410: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e414: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e418: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e41c: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800e420: b29b uxth r3, r3
800e422: 8013 strh r3, [r2, #0]
PCD_RX_DTOG(USBx, ep->num);
800e424: 687a ldr r2, [r7, #4]
800e426: 683b ldr r3, [r7, #0]
800e428: 781b ldrb r3, [r3, #0]
800e42a: 009b lsls r3, r3, #2
800e42c: 4413 add r3, r2
800e42e: 881b ldrh r3, [r3, #0]
800e430: b29b uxth r3, r3
800e432: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e436: f023 0370 bic.w r3, r3, #112 @ 0x70
800e43a: 84fb strh r3, [r7, #38] @ 0x26
800e43c: 687a ldr r2, [r7, #4]
800e43e: 683b ldr r3, [r7, #0]
800e440: 781b ldrb r3, [r3, #0]
800e442: 009b lsls r3, r3, #2
800e444: 441a add r2, r3
800e446: 8cfb ldrh r3, [r7, #38] @ 0x26
800e448: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e44c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e450: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800e454: f043 0380 orr.w r3, r3, #128 @ 0x80
800e458: b29b uxth r3, r3
800e45a: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800e45c: 687a ldr r2, [r7, #4]
800e45e: 683b ldr r3, [r7, #0]
800e460: 781b ldrb r3, [r3, #0]
800e462: 009b lsls r3, r3, #2
800e464: 4413 add r3, r2
800e466: 881b ldrh r3, [r3, #0]
800e468: b29b uxth r3, r3
800e46a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e46e: f023 0340 bic.w r3, r3, #64 @ 0x40
800e472: 84bb strh r3, [r7, #36] @ 0x24
800e474: 687a ldr r2, [r7, #4]
800e476: 683b ldr r3, [r7, #0]
800e478: 781b ldrb r3, [r3, #0]
800e47a: 009b lsls r3, r3, #2
800e47c: 441a add r2, r3
800e47e: 8cbb ldrh r3, [r7, #36] @ 0x24
800e480: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e484: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e488: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e48c: f043 0380 orr.w r3, r3, #128 @ 0x80
800e490: b29b uxth r3, r3
800e492: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
800e494: 687a ldr r2, [r7, #4]
800e496: 683b ldr r3, [r7, #0]
800e498: 781b ldrb r3, [r3, #0]
800e49a: 009b lsls r3, r3, #2
800e49c: 4413 add r3, r2
800e49e: 881b ldrh r3, [r3, #0]
800e4a0: b29b uxth r3, r3
800e4a2: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800e4a6: f023 0370 bic.w r3, r3, #112 @ 0x70
800e4aa: 847b strh r3, [r7, #34] @ 0x22
800e4ac: 687a ldr r2, [r7, #4]
800e4ae: 683b ldr r3, [r7, #0]
800e4b0: 781b ldrb r3, [r3, #0]
800e4b2: 009b lsls r3, r3, #2
800e4b4: 441a add r2, r3
800e4b6: 8c7b ldrh r3, [r7, #34] @ 0x22
800e4b8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e4bc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e4c0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800e4c4: f043 0380 orr.w r3, r3, #128 @ 0x80
800e4c8: b29b uxth r3, r3
800e4ca: 8013 strh r3, [r2, #0]
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
800e4cc: 2300 movs r3, #0
}
800e4ce: 4618 mov r0, r3
800e4d0: 3734 adds r7, #52 @ 0x34
800e4d2: 46bd mov sp, r7
800e4d4: f85d 7b04 ldr.w r7, [sp], #4
800e4d8: 4770 bx lr
0800e4da <USB_EPStartXfer>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
800e4da: b580 push {r7, lr}
800e4dc: b0ac sub sp, #176 @ 0xb0
800e4de: af00 add r7, sp, #0
800e4e0: 6078 str r0, [r7, #4]
800e4e2: 6039 str r1, [r7, #0]
uint16_t pmabuffer;
uint16_t wEPVal;
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* IN endpoint */
if (ep->is_in == 1U)
800e4e4: 683b ldr r3, [r7, #0]
800e4e6: 785b ldrb r3, [r3, #1]
800e4e8: 2b01 cmp r3, #1
800e4ea: f040 84ca bne.w 800ee82 <USB_EPStartXfer+0x9a8>
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
800e4ee: 683b ldr r3, [r7, #0]
800e4f0: 699a ldr r2, [r3, #24]
800e4f2: 683b ldr r3, [r7, #0]
800e4f4: 691b ldr r3, [r3, #16]
800e4f6: 429a cmp r2, r3
800e4f8: d904 bls.n 800e504 <USB_EPStartXfer+0x2a>
{
len = ep->maxpacket;
800e4fa: 683b ldr r3, [r7, #0]
800e4fc: 691b ldr r3, [r3, #16]
800e4fe: f8c7 30ac str.w r3, [r7, #172] @ 0xac
800e502: e003 b.n 800e50c <USB_EPStartXfer+0x32>
}
else
{
len = ep->xfer_len;
800e504: 683b ldr r3, [r7, #0]
800e506: 699b ldr r3, [r3, #24]
800e508: f8c7 30ac str.w r3, [r7, #172] @ 0xac
}
/* configure and validate Tx endpoint */
if (ep->doublebuffer == 0U)
800e50c: 683b ldr r3, [r7, #0]
800e50e: 7b1b ldrb r3, [r3, #12]
800e510: 2b00 cmp r3, #0
800e512: d122 bne.n 800e55a <USB_EPStartXfer+0x80>
{
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
800e514: 683b ldr r3, [r7, #0]
800e516: 6959 ldr r1, [r3, #20]
800e518: 683b ldr r3, [r7, #0]
800e51a: 88da ldrh r2, [r3, #6]
800e51c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e520: b29b uxth r3, r3
800e522: 6878 ldr r0, [r7, #4]
800e524: f000 febd bl 800f2a2 <USB_WritePMA>
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
800e528: 687b ldr r3, [r7, #4]
800e52a: 613b str r3, [r7, #16]
800e52c: 687b ldr r3, [r7, #4]
800e52e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800e532: b29b uxth r3, r3
800e534: 461a mov r2, r3
800e536: 693b ldr r3, [r7, #16]
800e538: 4413 add r3, r2
800e53a: 613b str r3, [r7, #16]
800e53c: 683b ldr r3, [r7, #0]
800e53e: 781b ldrb r3, [r3, #0]
800e540: 00da lsls r2, r3, #3
800e542: 693b ldr r3, [r7, #16]
800e544: 4413 add r3, r2
800e546: f203 4302 addw r3, r3, #1026 @ 0x402
800e54a: 60fb str r3, [r7, #12]
800e54c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e550: b29a uxth r2, r3
800e552: 68fb ldr r3, [r7, #12]
800e554: 801a strh r2, [r3, #0]
800e556: f000 bc6f b.w 800ee38 <USB_EPStartXfer+0x95e>
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* double buffer bulk management */
if (ep->type == EP_TYPE_BULK)
800e55a: 683b ldr r3, [r7, #0]
800e55c: 78db ldrb r3, [r3, #3]
800e55e: 2b02 cmp r3, #2
800e560: f040 831e bne.w 800eba0 <USB_EPStartXfer+0x6c6>
{
if (ep->xfer_len_db > ep->maxpacket)
800e564: 683b ldr r3, [r7, #0]
800e566: 6a1a ldr r2, [r3, #32]
800e568: 683b ldr r3, [r7, #0]
800e56a: 691b ldr r3, [r3, #16]
800e56c: 429a cmp r2, r3
800e56e: f240 82cf bls.w 800eb10 <USB_EPStartXfer+0x636>
{
/* enable double buffer */
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
800e572: 687a ldr r2, [r7, #4]
800e574: 683b ldr r3, [r7, #0]
800e576: 781b ldrb r3, [r3, #0]
800e578: 009b lsls r3, r3, #2
800e57a: 4413 add r3, r2
800e57c: 881b ldrh r3, [r3, #0]
800e57e: b29b uxth r3, r3
800e580: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800e584: f023 0370 bic.w r3, r3, #112 @ 0x70
800e588: f8a7 3056 strh.w r3, [r7, #86] @ 0x56
800e58c: 687a ldr r2, [r7, #4]
800e58e: 683b ldr r3, [r7, #0]
800e590: 781b ldrb r3, [r3, #0]
800e592: 009b lsls r3, r3, #2
800e594: 441a add r2, r3
800e596: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56
800e59a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800e59e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800e5a2: f443 4301 orr.w r3, r3, #33024 @ 0x8100
800e5a6: f043 0380 orr.w r3, r3, #128 @ 0x80
800e5aa: b29b uxth r3, r3
800e5ac: 8013 strh r3, [r2, #0]
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
800e5ae: 683b ldr r3, [r7, #0]
800e5b0: 6a1a ldr r2, [r3, #32]
800e5b2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e5b6: 1ad2 subs r2, r2, r3
800e5b8: 683b ldr r3, [r7, #0]
800e5ba: 621a str r2, [r3, #32]
/* Fill the two first buffer in the Buffer0 & Buffer1 */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
800e5bc: 687a ldr r2, [r7, #4]
800e5be: 683b ldr r3, [r7, #0]
800e5c0: 781b ldrb r3, [r3, #0]
800e5c2: 009b lsls r3, r3, #2
800e5c4: 4413 add r3, r2
800e5c6: 881b ldrh r3, [r3, #0]
800e5c8: b29b uxth r3, r3
800e5ca: f003 0340 and.w r3, r3, #64 @ 0x40
800e5ce: 2b00 cmp r3, #0
800e5d0: f000 814f beq.w 800e872 <USB_EPStartXfer+0x398>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
800e5d4: 687b ldr r3, [r7, #4]
800e5d6: 633b str r3, [r7, #48] @ 0x30
800e5d8: 683b ldr r3, [r7, #0]
800e5da: 785b ldrb r3, [r3, #1]
800e5dc: 2b00 cmp r3, #0
800e5de: d16b bne.n 800e6b8 <USB_EPStartXfer+0x1de>
800e5e0: 687b ldr r3, [r7, #4]
800e5e2: 62bb str r3, [r7, #40] @ 0x28
800e5e4: 687b ldr r3, [r7, #4]
800e5e6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800e5ea: b29b uxth r3, r3
800e5ec: 461a mov r2, r3
800e5ee: 6abb ldr r3, [r7, #40] @ 0x28
800e5f0: 4413 add r3, r2
800e5f2: 62bb str r3, [r7, #40] @ 0x28
800e5f4: 683b ldr r3, [r7, #0]
800e5f6: 781b ldrb r3, [r3, #0]
800e5f8: 00da lsls r2, r3, #3
800e5fa: 6abb ldr r3, [r7, #40] @ 0x28
800e5fc: 4413 add r3, r2
800e5fe: f203 4306 addw r3, r3, #1030 @ 0x406
800e602: 627b str r3, [r7, #36] @ 0x24
800e604: 6a7b ldr r3, [r7, #36] @ 0x24
800e606: 881b ldrh r3, [r3, #0]
800e608: b29b uxth r3, r3
800e60a: f3c3 0309 ubfx r3, r3, #0, #10
800e60e: b29a uxth r2, r3
800e610: 6a7b ldr r3, [r7, #36] @ 0x24
800e612: 801a strh r2, [r3, #0]
800e614: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e618: 2b00 cmp r3, #0
800e61a: d10a bne.n 800e632 <USB_EPStartXfer+0x158>
800e61c: 6a7b ldr r3, [r7, #36] @ 0x24
800e61e: 881b ldrh r3, [r3, #0]
800e620: b29b uxth r3, r3
800e622: ea6f 4343 mvn.w r3, r3, lsl #17
800e626: ea6f 4353 mvn.w r3, r3, lsr #17
800e62a: b29a uxth r2, r3
800e62c: 6a7b ldr r3, [r7, #36] @ 0x24
800e62e: 801a strh r2, [r3, #0]
800e630: e05b b.n 800e6ea <USB_EPStartXfer+0x210>
800e632: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e636: 2b3e cmp r3, #62 @ 0x3e
800e638: d81c bhi.n 800e674 <USB_EPStartXfer+0x19a>
800e63a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e63e: 085b lsrs r3, r3, #1
800e640: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
800e644: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e648: f003 0301 and.w r3, r3, #1
800e64c: 2b00 cmp r3, #0
800e64e: d004 beq.n 800e65a <USB_EPStartXfer+0x180>
800e650: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800e654: 3301 adds r3, #1
800e656: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
800e65a: 6a7b ldr r3, [r7, #36] @ 0x24
800e65c: 881b ldrh r3, [r3, #0]
800e65e: b29a uxth r2, r3
800e660: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800e664: b29b uxth r3, r3
800e666: 029b lsls r3, r3, #10
800e668: b29b uxth r3, r3
800e66a: 4313 orrs r3, r2
800e66c: b29a uxth r2, r3
800e66e: 6a7b ldr r3, [r7, #36] @ 0x24
800e670: 801a strh r2, [r3, #0]
800e672: e03a b.n 800e6ea <USB_EPStartXfer+0x210>
800e674: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e678: 095b lsrs r3, r3, #5
800e67a: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
800e67e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e682: f003 031f and.w r3, r3, #31
800e686: 2b00 cmp r3, #0
800e688: d104 bne.n 800e694 <USB_EPStartXfer+0x1ba>
800e68a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800e68e: 3b01 subs r3, #1
800e690: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
800e694: 6a7b ldr r3, [r7, #36] @ 0x24
800e696: 881b ldrh r3, [r3, #0]
800e698: b29a uxth r2, r3
800e69a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800e69e: b29b uxth r3, r3
800e6a0: 029b lsls r3, r3, #10
800e6a2: b29b uxth r3, r3
800e6a4: 4313 orrs r3, r2
800e6a6: b29b uxth r3, r3
800e6a8: ea6f 4343 mvn.w r3, r3, lsl #17
800e6ac: ea6f 4353 mvn.w r3, r3, lsr #17
800e6b0: b29a uxth r2, r3
800e6b2: 6a7b ldr r3, [r7, #36] @ 0x24
800e6b4: 801a strh r2, [r3, #0]
800e6b6: e018 b.n 800e6ea <USB_EPStartXfer+0x210>
800e6b8: 683b ldr r3, [r7, #0]
800e6ba: 785b ldrb r3, [r3, #1]
800e6bc: 2b01 cmp r3, #1
800e6be: d114 bne.n 800e6ea <USB_EPStartXfer+0x210>
800e6c0: 687b ldr r3, [r7, #4]
800e6c2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800e6c6: b29b uxth r3, r3
800e6c8: 461a mov r2, r3
800e6ca: 6b3b ldr r3, [r7, #48] @ 0x30
800e6cc: 4413 add r3, r2
800e6ce: 633b str r3, [r7, #48] @ 0x30
800e6d0: 683b ldr r3, [r7, #0]
800e6d2: 781b ldrb r3, [r3, #0]
800e6d4: 00da lsls r2, r3, #3
800e6d6: 6b3b ldr r3, [r7, #48] @ 0x30
800e6d8: 4413 add r3, r2
800e6da: f203 4306 addw r3, r3, #1030 @ 0x406
800e6de: 62fb str r3, [r7, #44] @ 0x2c
800e6e0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e6e4: b29a uxth r2, r3
800e6e6: 6afb ldr r3, [r7, #44] @ 0x2c
800e6e8: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
800e6ea: 683b ldr r3, [r7, #0]
800e6ec: 895b ldrh r3, [r3, #10]
800e6ee: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800e6f2: 683b ldr r3, [r7, #0]
800e6f4: 6959 ldr r1, [r3, #20]
800e6f6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e6fa: b29b uxth r3, r3
800e6fc: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800e700: 6878 ldr r0, [r7, #4]
800e702: f000 fdce bl 800f2a2 <USB_WritePMA>
ep->xfer_buff += len;
800e706: 683b ldr r3, [r7, #0]
800e708: 695a ldr r2, [r3, #20]
800e70a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e70e: 441a add r2, r3
800e710: 683b ldr r3, [r7, #0]
800e712: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
800e714: 683b ldr r3, [r7, #0]
800e716: 6a1a ldr r2, [r3, #32]
800e718: 683b ldr r3, [r7, #0]
800e71a: 691b ldr r3, [r3, #16]
800e71c: 429a cmp r2, r3
800e71e: d907 bls.n 800e730 <USB_EPStartXfer+0x256>
{
ep->xfer_len_db -= len;
800e720: 683b ldr r3, [r7, #0]
800e722: 6a1a ldr r2, [r3, #32]
800e724: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e728: 1ad2 subs r2, r2, r3
800e72a: 683b ldr r3, [r7, #0]
800e72c: 621a str r2, [r3, #32]
800e72e: e006 b.n 800e73e <USB_EPStartXfer+0x264>
}
else
{
len = ep->xfer_len_db;
800e730: 683b ldr r3, [r7, #0]
800e732: 6a1b ldr r3, [r3, #32]
800e734: f8c7 30ac str.w r3, [r7, #172] @ 0xac
ep->xfer_len_db = 0U;
800e738: 683b ldr r3, [r7, #0]
800e73a: 2200 movs r2, #0
800e73c: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
800e73e: 683b ldr r3, [r7, #0]
800e740: 785b ldrb r3, [r3, #1]
800e742: 2b00 cmp r3, #0
800e744: d16b bne.n 800e81e <USB_EPStartXfer+0x344>
800e746: 687b ldr r3, [r7, #4]
800e748: 61bb str r3, [r7, #24]
800e74a: 687b ldr r3, [r7, #4]
800e74c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800e750: b29b uxth r3, r3
800e752: 461a mov r2, r3
800e754: 69bb ldr r3, [r7, #24]
800e756: 4413 add r3, r2
800e758: 61bb str r3, [r7, #24]
800e75a: 683b ldr r3, [r7, #0]
800e75c: 781b ldrb r3, [r3, #0]
800e75e: 00da lsls r2, r3, #3
800e760: 69bb ldr r3, [r7, #24]
800e762: 4413 add r3, r2
800e764: f203 4302 addw r3, r3, #1026 @ 0x402
800e768: 617b str r3, [r7, #20]
800e76a: 697b ldr r3, [r7, #20]
800e76c: 881b ldrh r3, [r3, #0]
800e76e: b29b uxth r3, r3
800e770: f3c3 0309 ubfx r3, r3, #0, #10
800e774: b29a uxth r2, r3
800e776: 697b ldr r3, [r7, #20]
800e778: 801a strh r2, [r3, #0]
800e77a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e77e: 2b00 cmp r3, #0
800e780: d10a bne.n 800e798 <USB_EPStartXfer+0x2be>
800e782: 697b ldr r3, [r7, #20]
800e784: 881b ldrh r3, [r3, #0]
800e786: b29b uxth r3, r3
800e788: ea6f 4343 mvn.w r3, r3, lsl #17
800e78c: ea6f 4353 mvn.w r3, r3, lsr #17
800e790: b29a uxth r2, r3
800e792: 697b ldr r3, [r7, #20]
800e794: 801a strh r2, [r3, #0]
800e796: e05d b.n 800e854 <USB_EPStartXfer+0x37a>
800e798: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e79c: 2b3e cmp r3, #62 @ 0x3e
800e79e: d81c bhi.n 800e7da <USB_EPStartXfer+0x300>
800e7a0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e7a4: 085b lsrs r3, r3, #1
800e7a6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
800e7aa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e7ae: f003 0301 and.w r3, r3, #1
800e7b2: 2b00 cmp r3, #0
800e7b4: d004 beq.n 800e7c0 <USB_EPStartXfer+0x2e6>
800e7b6: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
800e7ba: 3301 adds r3, #1
800e7bc: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
800e7c0: 697b ldr r3, [r7, #20]
800e7c2: 881b ldrh r3, [r3, #0]
800e7c4: b29a uxth r2, r3
800e7c6: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
800e7ca: b29b uxth r3, r3
800e7cc: 029b lsls r3, r3, #10
800e7ce: b29b uxth r3, r3
800e7d0: 4313 orrs r3, r2
800e7d2: b29a uxth r2, r3
800e7d4: 697b ldr r3, [r7, #20]
800e7d6: 801a strh r2, [r3, #0]
800e7d8: e03c b.n 800e854 <USB_EPStartXfer+0x37a>
800e7da: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e7de: 095b lsrs r3, r3, #5
800e7e0: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
800e7e4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e7e8: f003 031f and.w r3, r3, #31
800e7ec: 2b00 cmp r3, #0
800e7ee: d104 bne.n 800e7fa <USB_EPStartXfer+0x320>
800e7f0: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
800e7f4: 3b01 subs r3, #1
800e7f6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
800e7fa: 697b ldr r3, [r7, #20]
800e7fc: 881b ldrh r3, [r3, #0]
800e7fe: b29a uxth r2, r3
800e800: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
800e804: b29b uxth r3, r3
800e806: 029b lsls r3, r3, #10
800e808: b29b uxth r3, r3
800e80a: 4313 orrs r3, r2
800e80c: b29b uxth r3, r3
800e80e: ea6f 4343 mvn.w r3, r3, lsl #17
800e812: ea6f 4353 mvn.w r3, r3, lsr #17
800e816: b29a uxth r2, r3
800e818: 697b ldr r3, [r7, #20]
800e81a: 801a strh r2, [r3, #0]
800e81c: e01a b.n 800e854 <USB_EPStartXfer+0x37a>
800e81e: 683b ldr r3, [r7, #0]
800e820: 785b ldrb r3, [r3, #1]
800e822: 2b01 cmp r3, #1
800e824: d116 bne.n 800e854 <USB_EPStartXfer+0x37a>
800e826: 687b ldr r3, [r7, #4]
800e828: 623b str r3, [r7, #32]
800e82a: 687b ldr r3, [r7, #4]
800e82c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800e830: b29b uxth r3, r3
800e832: 461a mov r2, r3
800e834: 6a3b ldr r3, [r7, #32]
800e836: 4413 add r3, r2
800e838: 623b str r3, [r7, #32]
800e83a: 683b ldr r3, [r7, #0]
800e83c: 781b ldrb r3, [r3, #0]
800e83e: 00da lsls r2, r3, #3
800e840: 6a3b ldr r3, [r7, #32]
800e842: 4413 add r3, r2
800e844: f203 4302 addw r3, r3, #1026 @ 0x402
800e848: 61fb str r3, [r7, #28]
800e84a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e84e: b29a uxth r2, r3
800e850: 69fb ldr r3, [r7, #28]
800e852: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
800e854: 683b ldr r3, [r7, #0]
800e856: 891b ldrh r3, [r3, #8]
800e858: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800e85c: 683b ldr r3, [r7, #0]
800e85e: 6959 ldr r1, [r3, #20]
800e860: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e864: b29b uxth r3, r3
800e866: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800e86a: 6878 ldr r0, [r7, #4]
800e86c: f000 fd19 bl 800f2a2 <USB_WritePMA>
800e870: e2e2 b.n 800ee38 <USB_EPStartXfer+0x95e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
800e872: 683b ldr r3, [r7, #0]
800e874: 785b ldrb r3, [r3, #1]
800e876: 2b00 cmp r3, #0
800e878: d16b bne.n 800e952 <USB_EPStartXfer+0x478>
800e87a: 687b ldr r3, [r7, #4]
800e87c: 64bb str r3, [r7, #72] @ 0x48
800e87e: 687b ldr r3, [r7, #4]
800e880: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800e884: b29b uxth r3, r3
800e886: 461a mov r2, r3
800e888: 6cbb ldr r3, [r7, #72] @ 0x48
800e88a: 4413 add r3, r2
800e88c: 64bb str r3, [r7, #72] @ 0x48
800e88e: 683b ldr r3, [r7, #0]
800e890: 781b ldrb r3, [r3, #0]
800e892: 00da lsls r2, r3, #3
800e894: 6cbb ldr r3, [r7, #72] @ 0x48
800e896: 4413 add r3, r2
800e898: f203 4302 addw r3, r3, #1026 @ 0x402
800e89c: 647b str r3, [r7, #68] @ 0x44
800e89e: 6c7b ldr r3, [r7, #68] @ 0x44
800e8a0: 881b ldrh r3, [r3, #0]
800e8a2: b29b uxth r3, r3
800e8a4: f3c3 0309 ubfx r3, r3, #0, #10
800e8a8: b29a uxth r2, r3
800e8aa: 6c7b ldr r3, [r7, #68] @ 0x44
800e8ac: 801a strh r2, [r3, #0]
800e8ae: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e8b2: 2b00 cmp r3, #0
800e8b4: d10a bne.n 800e8cc <USB_EPStartXfer+0x3f2>
800e8b6: 6c7b ldr r3, [r7, #68] @ 0x44
800e8b8: 881b ldrh r3, [r3, #0]
800e8ba: b29b uxth r3, r3
800e8bc: ea6f 4343 mvn.w r3, r3, lsl #17
800e8c0: ea6f 4353 mvn.w r3, r3, lsr #17
800e8c4: b29a uxth r2, r3
800e8c6: 6c7b ldr r3, [r7, #68] @ 0x44
800e8c8: 801a strh r2, [r3, #0]
800e8ca: e05d b.n 800e988 <USB_EPStartXfer+0x4ae>
800e8cc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e8d0: 2b3e cmp r3, #62 @ 0x3e
800e8d2: d81c bhi.n 800e90e <USB_EPStartXfer+0x434>
800e8d4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e8d8: 085b lsrs r3, r3, #1
800e8da: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
800e8de: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e8e2: f003 0301 and.w r3, r3, #1
800e8e6: 2b00 cmp r3, #0
800e8e8: d004 beq.n 800e8f4 <USB_EPStartXfer+0x41a>
800e8ea: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800e8ee: 3301 adds r3, #1
800e8f0: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
800e8f4: 6c7b ldr r3, [r7, #68] @ 0x44
800e8f6: 881b ldrh r3, [r3, #0]
800e8f8: b29a uxth r2, r3
800e8fa: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800e8fe: b29b uxth r3, r3
800e900: 029b lsls r3, r3, #10
800e902: b29b uxth r3, r3
800e904: 4313 orrs r3, r2
800e906: b29a uxth r2, r3
800e908: 6c7b ldr r3, [r7, #68] @ 0x44
800e90a: 801a strh r2, [r3, #0]
800e90c: e03c b.n 800e988 <USB_EPStartXfer+0x4ae>
800e90e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e912: 095b lsrs r3, r3, #5
800e914: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
800e918: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e91c: f003 031f and.w r3, r3, #31
800e920: 2b00 cmp r3, #0
800e922: d104 bne.n 800e92e <USB_EPStartXfer+0x454>
800e924: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800e928: 3b01 subs r3, #1
800e92a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
800e92e: 6c7b ldr r3, [r7, #68] @ 0x44
800e930: 881b ldrh r3, [r3, #0]
800e932: b29a uxth r2, r3
800e934: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800e938: b29b uxth r3, r3
800e93a: 029b lsls r3, r3, #10
800e93c: b29b uxth r3, r3
800e93e: 4313 orrs r3, r2
800e940: b29b uxth r3, r3
800e942: ea6f 4343 mvn.w r3, r3, lsl #17
800e946: ea6f 4353 mvn.w r3, r3, lsr #17
800e94a: b29a uxth r2, r3
800e94c: 6c7b ldr r3, [r7, #68] @ 0x44
800e94e: 801a strh r2, [r3, #0]
800e950: e01a b.n 800e988 <USB_EPStartXfer+0x4ae>
800e952: 683b ldr r3, [r7, #0]
800e954: 785b ldrb r3, [r3, #1]
800e956: 2b01 cmp r3, #1
800e958: d116 bne.n 800e988 <USB_EPStartXfer+0x4ae>
800e95a: 687b ldr r3, [r7, #4]
800e95c: 653b str r3, [r7, #80] @ 0x50
800e95e: 687b ldr r3, [r7, #4]
800e960: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800e964: b29b uxth r3, r3
800e966: 461a mov r2, r3
800e968: 6d3b ldr r3, [r7, #80] @ 0x50
800e96a: 4413 add r3, r2
800e96c: 653b str r3, [r7, #80] @ 0x50
800e96e: 683b ldr r3, [r7, #0]
800e970: 781b ldrb r3, [r3, #0]
800e972: 00da lsls r2, r3, #3
800e974: 6d3b ldr r3, [r7, #80] @ 0x50
800e976: 4413 add r3, r2
800e978: f203 4302 addw r3, r3, #1026 @ 0x402
800e97c: 64fb str r3, [r7, #76] @ 0x4c
800e97e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e982: b29a uxth r2, r3
800e984: 6cfb ldr r3, [r7, #76] @ 0x4c
800e986: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
800e988: 683b ldr r3, [r7, #0]
800e98a: 891b ldrh r3, [r3, #8]
800e98c: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800e990: 683b ldr r3, [r7, #0]
800e992: 6959 ldr r1, [r3, #20]
800e994: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e998: b29b uxth r3, r3
800e99a: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800e99e: 6878 ldr r0, [r7, #4]
800e9a0: f000 fc7f bl 800f2a2 <USB_WritePMA>
ep->xfer_buff += len;
800e9a4: 683b ldr r3, [r7, #0]
800e9a6: 695a ldr r2, [r3, #20]
800e9a8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e9ac: 441a add r2, r3
800e9ae: 683b ldr r3, [r7, #0]
800e9b0: 615a str r2, [r3, #20]
if (ep->xfer_len_db > ep->maxpacket)
800e9b2: 683b ldr r3, [r7, #0]
800e9b4: 6a1a ldr r2, [r3, #32]
800e9b6: 683b ldr r3, [r7, #0]
800e9b8: 691b ldr r3, [r3, #16]
800e9ba: 429a cmp r2, r3
800e9bc: d907 bls.n 800e9ce <USB_EPStartXfer+0x4f4>
{
ep->xfer_len_db -= len;
800e9be: 683b ldr r3, [r7, #0]
800e9c0: 6a1a ldr r2, [r3, #32]
800e9c2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800e9c6: 1ad2 subs r2, r2, r3
800e9c8: 683b ldr r3, [r7, #0]
800e9ca: 621a str r2, [r3, #32]
800e9cc: e006 b.n 800e9dc <USB_EPStartXfer+0x502>
}
else
{
len = ep->xfer_len_db;
800e9ce: 683b ldr r3, [r7, #0]
800e9d0: 6a1b ldr r3, [r3, #32]
800e9d2: f8c7 30ac str.w r3, [r7, #172] @ 0xac
ep->xfer_len_db = 0U;
800e9d6: 683b ldr r3, [r7, #0]
800e9d8: 2200 movs r2, #0
800e9da: 621a str r2, [r3, #32]
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
800e9dc: 687b ldr r3, [r7, #4]
800e9de: 643b str r3, [r7, #64] @ 0x40
800e9e0: 683b ldr r3, [r7, #0]
800e9e2: 785b ldrb r3, [r3, #1]
800e9e4: 2b00 cmp r3, #0
800e9e6: d16b bne.n 800eac0 <USB_EPStartXfer+0x5e6>
800e9e8: 687b ldr r3, [r7, #4]
800e9ea: 63bb str r3, [r7, #56] @ 0x38
800e9ec: 687b ldr r3, [r7, #4]
800e9ee: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800e9f2: b29b uxth r3, r3
800e9f4: 461a mov r2, r3
800e9f6: 6bbb ldr r3, [r7, #56] @ 0x38
800e9f8: 4413 add r3, r2
800e9fa: 63bb str r3, [r7, #56] @ 0x38
800e9fc: 683b ldr r3, [r7, #0]
800e9fe: 781b ldrb r3, [r3, #0]
800ea00: 00da lsls r2, r3, #3
800ea02: 6bbb ldr r3, [r7, #56] @ 0x38
800ea04: 4413 add r3, r2
800ea06: f203 4306 addw r3, r3, #1030 @ 0x406
800ea0a: 637b str r3, [r7, #52] @ 0x34
800ea0c: 6b7b ldr r3, [r7, #52] @ 0x34
800ea0e: 881b ldrh r3, [r3, #0]
800ea10: b29b uxth r3, r3
800ea12: f3c3 0309 ubfx r3, r3, #0, #10
800ea16: b29a uxth r2, r3
800ea18: 6b7b ldr r3, [r7, #52] @ 0x34
800ea1a: 801a strh r2, [r3, #0]
800ea1c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ea20: 2b00 cmp r3, #0
800ea22: d10a bne.n 800ea3a <USB_EPStartXfer+0x560>
800ea24: 6b7b ldr r3, [r7, #52] @ 0x34
800ea26: 881b ldrh r3, [r3, #0]
800ea28: b29b uxth r3, r3
800ea2a: ea6f 4343 mvn.w r3, r3, lsl #17
800ea2e: ea6f 4353 mvn.w r3, r3, lsr #17
800ea32: b29a uxth r2, r3
800ea34: 6b7b ldr r3, [r7, #52] @ 0x34
800ea36: 801a strh r2, [r3, #0]
800ea38: e05b b.n 800eaf2 <USB_EPStartXfer+0x618>
800ea3a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ea3e: 2b3e cmp r3, #62 @ 0x3e
800ea40: d81c bhi.n 800ea7c <USB_EPStartXfer+0x5a2>
800ea42: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ea46: 085b lsrs r3, r3, #1
800ea48: f8c7 309c str.w r3, [r7, #156] @ 0x9c
800ea4c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ea50: f003 0301 and.w r3, r3, #1
800ea54: 2b00 cmp r3, #0
800ea56: d004 beq.n 800ea62 <USB_EPStartXfer+0x588>
800ea58: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800ea5c: 3301 adds r3, #1
800ea5e: f8c7 309c str.w r3, [r7, #156] @ 0x9c
800ea62: 6b7b ldr r3, [r7, #52] @ 0x34
800ea64: 881b ldrh r3, [r3, #0]
800ea66: b29a uxth r2, r3
800ea68: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800ea6c: b29b uxth r3, r3
800ea6e: 029b lsls r3, r3, #10
800ea70: b29b uxth r3, r3
800ea72: 4313 orrs r3, r2
800ea74: b29a uxth r2, r3
800ea76: 6b7b ldr r3, [r7, #52] @ 0x34
800ea78: 801a strh r2, [r3, #0]
800ea7a: e03a b.n 800eaf2 <USB_EPStartXfer+0x618>
800ea7c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ea80: 095b lsrs r3, r3, #5
800ea82: f8c7 309c str.w r3, [r7, #156] @ 0x9c
800ea86: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ea8a: f003 031f and.w r3, r3, #31
800ea8e: 2b00 cmp r3, #0
800ea90: d104 bne.n 800ea9c <USB_EPStartXfer+0x5c2>
800ea92: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800ea96: 3b01 subs r3, #1
800ea98: f8c7 309c str.w r3, [r7, #156] @ 0x9c
800ea9c: 6b7b ldr r3, [r7, #52] @ 0x34
800ea9e: 881b ldrh r3, [r3, #0]
800eaa0: b29a uxth r2, r3
800eaa2: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800eaa6: b29b uxth r3, r3
800eaa8: 029b lsls r3, r3, #10
800eaaa: b29b uxth r3, r3
800eaac: 4313 orrs r3, r2
800eaae: b29b uxth r3, r3
800eab0: ea6f 4343 mvn.w r3, r3, lsl #17
800eab4: ea6f 4353 mvn.w r3, r3, lsr #17
800eab8: b29a uxth r2, r3
800eaba: 6b7b ldr r3, [r7, #52] @ 0x34
800eabc: 801a strh r2, [r3, #0]
800eabe: e018 b.n 800eaf2 <USB_EPStartXfer+0x618>
800eac0: 683b ldr r3, [r7, #0]
800eac2: 785b ldrb r3, [r3, #1]
800eac4: 2b01 cmp r3, #1
800eac6: d114 bne.n 800eaf2 <USB_EPStartXfer+0x618>
800eac8: 687b ldr r3, [r7, #4]
800eaca: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800eace: b29b uxth r3, r3
800ead0: 461a mov r2, r3
800ead2: 6c3b ldr r3, [r7, #64] @ 0x40
800ead4: 4413 add r3, r2
800ead6: 643b str r3, [r7, #64] @ 0x40
800ead8: 683b ldr r3, [r7, #0]
800eada: 781b ldrb r3, [r3, #0]
800eadc: 00da lsls r2, r3, #3
800eade: 6c3b ldr r3, [r7, #64] @ 0x40
800eae0: 4413 add r3, r2
800eae2: f203 4306 addw r3, r3, #1030 @ 0x406
800eae6: 63fb str r3, [r7, #60] @ 0x3c
800eae8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800eaec: b29a uxth r2, r3
800eaee: 6bfb ldr r3, [r7, #60] @ 0x3c
800eaf0: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
800eaf2: 683b ldr r3, [r7, #0]
800eaf4: 895b ldrh r3, [r3, #10]
800eaf6: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800eafa: 683b ldr r3, [r7, #0]
800eafc: 6959 ldr r1, [r3, #20]
800eafe: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800eb02: b29b uxth r3, r3
800eb04: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800eb08: 6878 ldr r0, [r7, #4]
800eb0a: f000 fbca bl 800f2a2 <USB_WritePMA>
800eb0e: e193 b.n 800ee38 <USB_EPStartXfer+0x95e>
}
}
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
800eb10: 683b ldr r3, [r7, #0]
800eb12: 6a1b ldr r3, [r3, #32]
800eb14: f8c7 30ac str.w r3, [r7, #172] @ 0xac
/* disable double buffer mode for Bulk endpoint */
PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
800eb18: 687a ldr r2, [r7, #4]
800eb1a: 683b ldr r3, [r7, #0]
800eb1c: 781b ldrb r3, [r3, #0]
800eb1e: 009b lsls r3, r3, #2
800eb20: 4413 add r3, r2
800eb22: 881b ldrh r3, [r3, #0]
800eb24: b29b uxth r3, r3
800eb26: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
800eb2a: f023 0370 bic.w r3, r3, #112 @ 0x70
800eb2e: f8a7 3062 strh.w r3, [r7, #98] @ 0x62
800eb32: 687a ldr r2, [r7, #4]
800eb34: 683b ldr r3, [r7, #0]
800eb36: 781b ldrb r3, [r3, #0]
800eb38: 009b lsls r3, r3, #2
800eb3a: 441a add r2, r3
800eb3c: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62
800eb40: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800eb44: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800eb48: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800eb4c: f043 0380 orr.w r3, r3, #128 @ 0x80
800eb50: b29b uxth r3, r3
800eb52: 8013 strh r3, [r2, #0]
/* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
800eb54: 687b ldr r3, [r7, #4]
800eb56: 65fb str r3, [r7, #92] @ 0x5c
800eb58: 687b ldr r3, [r7, #4]
800eb5a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800eb5e: b29b uxth r3, r3
800eb60: 461a mov r2, r3
800eb62: 6dfb ldr r3, [r7, #92] @ 0x5c
800eb64: 4413 add r3, r2
800eb66: 65fb str r3, [r7, #92] @ 0x5c
800eb68: 683b ldr r3, [r7, #0]
800eb6a: 781b ldrb r3, [r3, #0]
800eb6c: 00da lsls r2, r3, #3
800eb6e: 6dfb ldr r3, [r7, #92] @ 0x5c
800eb70: 4413 add r3, r2
800eb72: f203 4302 addw r3, r3, #1026 @ 0x402
800eb76: 65bb str r3, [r7, #88] @ 0x58
800eb78: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800eb7c: b29a uxth r2, r3
800eb7e: 6dbb ldr r3, [r7, #88] @ 0x58
800eb80: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
800eb82: 683b ldr r3, [r7, #0]
800eb84: 891b ldrh r3, [r3, #8]
800eb86: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800eb8a: 683b ldr r3, [r7, #0]
800eb8c: 6959 ldr r1, [r3, #20]
800eb8e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800eb92: b29b uxth r3, r3
800eb94: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800eb98: 6878 ldr r0, [r7, #4]
800eb9a: f000 fb82 bl 800f2a2 <USB_WritePMA>
800eb9e: e14b b.n 800ee38 <USB_EPStartXfer+0x95e>
}
}
else /* Manage isochronous double buffer IN mode */
{
/* Each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
800eba0: 683b ldr r3, [r7, #0]
800eba2: 6a1a ldr r2, [r3, #32]
800eba4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800eba8: 1ad2 subs r2, r2, r3
800ebaa: 683b ldr r3, [r7, #0]
800ebac: 621a str r2, [r3, #32]
/* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
800ebae: 687a ldr r2, [r7, #4]
800ebb0: 683b ldr r3, [r7, #0]
800ebb2: 781b ldrb r3, [r3, #0]
800ebb4: 009b lsls r3, r3, #2
800ebb6: 4413 add r3, r2
800ebb8: 881b ldrh r3, [r3, #0]
800ebba: b29b uxth r3, r3
800ebbc: f003 0340 and.w r3, r3, #64 @ 0x40
800ebc0: 2b00 cmp r3, #0
800ebc2: f000 809a beq.w 800ecfa <USB_EPStartXfer+0x820>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
800ebc6: 687b ldr r3, [r7, #4]
800ebc8: 673b str r3, [r7, #112] @ 0x70
800ebca: 683b ldr r3, [r7, #0]
800ebcc: 785b ldrb r3, [r3, #1]
800ebce: 2b00 cmp r3, #0
800ebd0: d16b bne.n 800ecaa <USB_EPStartXfer+0x7d0>
800ebd2: 687b ldr r3, [r7, #4]
800ebd4: 66bb str r3, [r7, #104] @ 0x68
800ebd6: 687b ldr r3, [r7, #4]
800ebd8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800ebdc: b29b uxth r3, r3
800ebde: 461a mov r2, r3
800ebe0: 6ebb ldr r3, [r7, #104] @ 0x68
800ebe2: 4413 add r3, r2
800ebe4: 66bb str r3, [r7, #104] @ 0x68
800ebe6: 683b ldr r3, [r7, #0]
800ebe8: 781b ldrb r3, [r3, #0]
800ebea: 00da lsls r2, r3, #3
800ebec: 6ebb ldr r3, [r7, #104] @ 0x68
800ebee: 4413 add r3, r2
800ebf0: f203 4306 addw r3, r3, #1030 @ 0x406
800ebf4: 667b str r3, [r7, #100] @ 0x64
800ebf6: 6e7b ldr r3, [r7, #100] @ 0x64
800ebf8: 881b ldrh r3, [r3, #0]
800ebfa: b29b uxth r3, r3
800ebfc: f3c3 0309 ubfx r3, r3, #0, #10
800ec00: b29a uxth r2, r3
800ec02: 6e7b ldr r3, [r7, #100] @ 0x64
800ec04: 801a strh r2, [r3, #0]
800ec06: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ec0a: 2b00 cmp r3, #0
800ec0c: d10a bne.n 800ec24 <USB_EPStartXfer+0x74a>
800ec0e: 6e7b ldr r3, [r7, #100] @ 0x64
800ec10: 881b ldrh r3, [r3, #0]
800ec12: b29b uxth r3, r3
800ec14: ea6f 4343 mvn.w r3, r3, lsl #17
800ec18: ea6f 4353 mvn.w r3, r3, lsr #17
800ec1c: b29a uxth r2, r3
800ec1e: 6e7b ldr r3, [r7, #100] @ 0x64
800ec20: 801a strh r2, [r3, #0]
800ec22: e05b b.n 800ecdc <USB_EPStartXfer+0x802>
800ec24: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ec28: 2b3e cmp r3, #62 @ 0x3e
800ec2a: d81c bhi.n 800ec66 <USB_EPStartXfer+0x78c>
800ec2c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ec30: 085b lsrs r3, r3, #1
800ec32: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800ec36: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ec3a: f003 0301 and.w r3, r3, #1
800ec3e: 2b00 cmp r3, #0
800ec40: d004 beq.n 800ec4c <USB_EPStartXfer+0x772>
800ec42: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800ec46: 3301 adds r3, #1
800ec48: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800ec4c: 6e7b ldr r3, [r7, #100] @ 0x64
800ec4e: 881b ldrh r3, [r3, #0]
800ec50: b29a uxth r2, r3
800ec52: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800ec56: b29b uxth r3, r3
800ec58: 029b lsls r3, r3, #10
800ec5a: b29b uxth r3, r3
800ec5c: 4313 orrs r3, r2
800ec5e: b29a uxth r2, r3
800ec60: 6e7b ldr r3, [r7, #100] @ 0x64
800ec62: 801a strh r2, [r3, #0]
800ec64: e03a b.n 800ecdc <USB_EPStartXfer+0x802>
800ec66: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ec6a: 095b lsrs r3, r3, #5
800ec6c: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800ec70: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ec74: f003 031f and.w r3, r3, #31
800ec78: 2b00 cmp r3, #0
800ec7a: d104 bne.n 800ec86 <USB_EPStartXfer+0x7ac>
800ec7c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800ec80: 3b01 subs r3, #1
800ec82: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800ec86: 6e7b ldr r3, [r7, #100] @ 0x64
800ec88: 881b ldrh r3, [r3, #0]
800ec8a: b29a uxth r2, r3
800ec8c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800ec90: b29b uxth r3, r3
800ec92: 029b lsls r3, r3, #10
800ec94: b29b uxth r3, r3
800ec96: 4313 orrs r3, r2
800ec98: b29b uxth r3, r3
800ec9a: ea6f 4343 mvn.w r3, r3, lsl #17
800ec9e: ea6f 4353 mvn.w r3, r3, lsr #17
800eca2: b29a uxth r2, r3
800eca4: 6e7b ldr r3, [r7, #100] @ 0x64
800eca6: 801a strh r2, [r3, #0]
800eca8: e018 b.n 800ecdc <USB_EPStartXfer+0x802>
800ecaa: 683b ldr r3, [r7, #0]
800ecac: 785b ldrb r3, [r3, #1]
800ecae: 2b01 cmp r3, #1
800ecb0: d114 bne.n 800ecdc <USB_EPStartXfer+0x802>
800ecb2: 687b ldr r3, [r7, #4]
800ecb4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800ecb8: b29b uxth r3, r3
800ecba: 461a mov r2, r3
800ecbc: 6f3b ldr r3, [r7, #112] @ 0x70
800ecbe: 4413 add r3, r2
800ecc0: 673b str r3, [r7, #112] @ 0x70
800ecc2: 683b ldr r3, [r7, #0]
800ecc4: 781b ldrb r3, [r3, #0]
800ecc6: 00da lsls r2, r3, #3
800ecc8: 6f3b ldr r3, [r7, #112] @ 0x70
800ecca: 4413 add r3, r2
800eccc: f203 4306 addw r3, r3, #1030 @ 0x406
800ecd0: 66fb str r3, [r7, #108] @ 0x6c
800ecd2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ecd6: b29a uxth r2, r3
800ecd8: 6efb ldr r3, [r7, #108] @ 0x6c
800ecda: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
800ecdc: 683b ldr r3, [r7, #0]
800ecde: 895b ldrh r3, [r3, #10]
800ece0: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800ece4: 683b ldr r3, [r7, #0]
800ece6: 6959 ldr r1, [r3, #20]
800ece8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ecec: b29b uxth r3, r3
800ecee: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800ecf2: 6878 ldr r0, [r7, #4]
800ecf4: f000 fad5 bl 800f2a2 <USB_WritePMA>
800ecf8: e09e b.n 800ee38 <USB_EPStartXfer+0x95e>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
800ecfa: 683b ldr r3, [r7, #0]
800ecfc: 785b ldrb r3, [r3, #1]
800ecfe: 2b00 cmp r3, #0
800ed00: d16b bne.n 800edda <USB_EPStartXfer+0x900>
800ed02: 687b ldr r3, [r7, #4]
800ed04: 67fb str r3, [r7, #124] @ 0x7c
800ed06: 687b ldr r3, [r7, #4]
800ed08: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800ed0c: b29b uxth r3, r3
800ed0e: 461a mov r2, r3
800ed10: 6ffb ldr r3, [r7, #124] @ 0x7c
800ed12: 4413 add r3, r2
800ed14: 67fb str r3, [r7, #124] @ 0x7c
800ed16: 683b ldr r3, [r7, #0]
800ed18: 781b ldrb r3, [r3, #0]
800ed1a: 00da lsls r2, r3, #3
800ed1c: 6ffb ldr r3, [r7, #124] @ 0x7c
800ed1e: 4413 add r3, r2
800ed20: f203 4302 addw r3, r3, #1026 @ 0x402
800ed24: 67bb str r3, [r7, #120] @ 0x78
800ed26: 6fbb ldr r3, [r7, #120] @ 0x78
800ed28: 881b ldrh r3, [r3, #0]
800ed2a: b29b uxth r3, r3
800ed2c: f3c3 0309 ubfx r3, r3, #0, #10
800ed30: b29a uxth r2, r3
800ed32: 6fbb ldr r3, [r7, #120] @ 0x78
800ed34: 801a strh r2, [r3, #0]
800ed36: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ed3a: 2b00 cmp r3, #0
800ed3c: d10a bne.n 800ed54 <USB_EPStartXfer+0x87a>
800ed3e: 6fbb ldr r3, [r7, #120] @ 0x78
800ed40: 881b ldrh r3, [r3, #0]
800ed42: b29b uxth r3, r3
800ed44: ea6f 4343 mvn.w r3, r3, lsl #17
800ed48: ea6f 4353 mvn.w r3, r3, lsr #17
800ed4c: b29a uxth r2, r3
800ed4e: 6fbb ldr r3, [r7, #120] @ 0x78
800ed50: 801a strh r2, [r3, #0]
800ed52: e063 b.n 800ee1c <USB_EPStartXfer+0x942>
800ed54: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ed58: 2b3e cmp r3, #62 @ 0x3e
800ed5a: d81c bhi.n 800ed96 <USB_EPStartXfer+0x8bc>
800ed5c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ed60: 085b lsrs r3, r3, #1
800ed62: f8c7 3094 str.w r3, [r7, #148] @ 0x94
800ed66: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ed6a: f003 0301 and.w r3, r3, #1
800ed6e: 2b00 cmp r3, #0
800ed70: d004 beq.n 800ed7c <USB_EPStartXfer+0x8a2>
800ed72: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
800ed76: 3301 adds r3, #1
800ed78: f8c7 3094 str.w r3, [r7, #148] @ 0x94
800ed7c: 6fbb ldr r3, [r7, #120] @ 0x78
800ed7e: 881b ldrh r3, [r3, #0]
800ed80: b29a uxth r2, r3
800ed82: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
800ed86: b29b uxth r3, r3
800ed88: 029b lsls r3, r3, #10
800ed8a: b29b uxth r3, r3
800ed8c: 4313 orrs r3, r2
800ed8e: b29a uxth r2, r3
800ed90: 6fbb ldr r3, [r7, #120] @ 0x78
800ed92: 801a strh r2, [r3, #0]
800ed94: e042 b.n 800ee1c <USB_EPStartXfer+0x942>
800ed96: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ed9a: 095b lsrs r3, r3, #5
800ed9c: f8c7 3094 str.w r3, [r7, #148] @ 0x94
800eda0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800eda4: f003 031f and.w r3, r3, #31
800eda8: 2b00 cmp r3, #0
800edaa: d104 bne.n 800edb6 <USB_EPStartXfer+0x8dc>
800edac: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
800edb0: 3b01 subs r3, #1
800edb2: f8c7 3094 str.w r3, [r7, #148] @ 0x94
800edb6: 6fbb ldr r3, [r7, #120] @ 0x78
800edb8: 881b ldrh r3, [r3, #0]
800edba: b29a uxth r2, r3
800edbc: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
800edc0: b29b uxth r3, r3
800edc2: 029b lsls r3, r3, #10
800edc4: b29b uxth r3, r3
800edc6: 4313 orrs r3, r2
800edc8: b29b uxth r3, r3
800edca: ea6f 4343 mvn.w r3, r3, lsl #17
800edce: ea6f 4353 mvn.w r3, r3, lsr #17
800edd2: b29a uxth r2, r3
800edd4: 6fbb ldr r3, [r7, #120] @ 0x78
800edd6: 801a strh r2, [r3, #0]
800edd8: e020 b.n 800ee1c <USB_EPStartXfer+0x942>
800edda: 683b ldr r3, [r7, #0]
800eddc: 785b ldrb r3, [r3, #1]
800edde: 2b01 cmp r3, #1
800ede0: d11c bne.n 800ee1c <USB_EPStartXfer+0x942>
800ede2: 687b ldr r3, [r7, #4]
800ede4: f8c7 3084 str.w r3, [r7, #132] @ 0x84
800ede8: 687b ldr r3, [r7, #4]
800edea: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50
800edee: b29b uxth r3, r3
800edf0: 461a mov r2, r3
800edf2: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800edf6: 4413 add r3, r2
800edf8: f8c7 3084 str.w r3, [r7, #132] @ 0x84
800edfc: 683b ldr r3, [r7, #0]
800edfe: 781b ldrb r3, [r3, #0]
800ee00: 00da lsls r2, r3, #3
800ee02: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800ee06: 4413 add r3, r2
800ee08: f203 4302 addw r3, r3, #1026 @ 0x402
800ee0c: f8c7 3080 str.w r3, [r7, #128] @ 0x80
800ee10: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ee14: b29a uxth r2, r3
800ee16: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
800ee1a: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr0;
800ee1c: 683b ldr r3, [r7, #0]
800ee1e: 891b ldrh r3, [r3, #8]
800ee20: f8a7 3076 strh.w r3, [r7, #118] @ 0x76
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
800ee24: 683b ldr r3, [r7, #0]
800ee26: 6959 ldr r1, [r3, #20]
800ee28: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800ee2c: b29b uxth r3, r3
800ee2e: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76
800ee32: 6878 ldr r0, [r7, #4]
800ee34: f000 fa35 bl 800f2a2 <USB_WritePMA>
}
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
800ee38: 687a ldr r2, [r7, #4]
800ee3a: 683b ldr r3, [r7, #0]
800ee3c: 781b ldrb r3, [r3, #0]
800ee3e: 009b lsls r3, r3, #2
800ee40: 4413 add r3, r2
800ee42: 881b ldrh r3, [r3, #0]
800ee44: b29b uxth r3, r3
800ee46: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800ee4a: f023 0340 bic.w r3, r3, #64 @ 0x40
800ee4e: 817b strh r3, [r7, #10]
800ee50: 897b ldrh r3, [r7, #10]
800ee52: f083 0310 eor.w r3, r3, #16
800ee56: 817b strh r3, [r7, #10]
800ee58: 897b ldrh r3, [r7, #10]
800ee5a: f083 0320 eor.w r3, r3, #32
800ee5e: 817b strh r3, [r7, #10]
800ee60: 687a ldr r2, [r7, #4]
800ee62: 683b ldr r3, [r7, #0]
800ee64: 781b ldrb r3, [r3, #0]
800ee66: 009b lsls r3, r3, #2
800ee68: 441a add r2, r3
800ee6a: 897b ldrh r3, [r7, #10]
800ee6c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800ee70: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800ee74: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800ee78: f043 0380 orr.w r3, r3, #128 @ 0x80
800ee7c: b29b uxth r3, r3
800ee7e: 8013 strh r3, [r2, #0]
800ee80: e0d5 b.n 800f02e <USB_EPStartXfer+0xb54>
}
else /* OUT endpoint */
{
if (ep->doublebuffer == 0U)
800ee82: 683b ldr r3, [r7, #0]
800ee84: 7b1b ldrb r3, [r3, #12]
800ee86: 2b00 cmp r3, #0
800ee88: d156 bne.n 800ef38 <USB_EPStartXfer+0xa5e>
{
if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL))
800ee8a: 683b ldr r3, [r7, #0]
800ee8c: 699b ldr r3, [r3, #24]
800ee8e: 2b00 cmp r3, #0
800ee90: d122 bne.n 800eed8 <USB_EPStartXfer+0x9fe>
800ee92: 683b ldr r3, [r7, #0]
800ee94: 78db ldrb r3, [r3, #3]
800ee96: 2b00 cmp r3, #0
800ee98: d11e bne.n 800eed8 <USB_EPStartXfer+0x9fe>
{
/* This is a status out stage set the OUT_STATUS */
PCD_SET_OUT_STATUS(USBx, ep->num);
800ee9a: 687a ldr r2, [r7, #4]
800ee9c: 683b ldr r3, [r7, #0]
800ee9e: 781b ldrb r3, [r3, #0]
800eea0: 009b lsls r3, r3, #2
800eea2: 4413 add r3, r2
800eea4: 881b ldrh r3, [r3, #0]
800eea6: b29b uxth r3, r3
800eea8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800eeac: f023 0370 bic.w r3, r3, #112 @ 0x70
800eeb0: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
800eeb4: 687a ldr r2, [r7, #4]
800eeb6: 683b ldr r3, [r7, #0]
800eeb8: 781b ldrb r3, [r3, #0]
800eeba: 009b lsls r3, r3, #2
800eebc: 441a add r2, r3
800eebe: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
800eec2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800eec6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800eeca: f443 4301 orr.w r3, r3, #33024 @ 0x8100
800eece: f043 0380 orr.w r3, r3, #128 @ 0x80
800eed2: b29b uxth r3, r3
800eed4: 8013 strh r3, [r2, #0]
800eed6: e01d b.n 800ef14 <USB_EPStartXfer+0xa3a>
}
else
{
PCD_CLEAR_OUT_STATUS(USBx, ep->num);
800eed8: 687a ldr r2, [r7, #4]
800eeda: 683b ldr r3, [r7, #0]
800eedc: 781b ldrb r3, [r3, #0]
800eede: 009b lsls r3, r3, #2
800eee0: 4413 add r3, r2
800eee2: 881b ldrh r3, [r3, #0]
800eee4: b29b uxth r3, r3
800eee6: f423 43e2 bic.w r3, r3, #28928 @ 0x7100
800eeea: f023 0370 bic.w r3, r3, #112 @ 0x70
800eeee: f8a7 308c strh.w r3, [r7, #140] @ 0x8c
800eef2: 687a ldr r2, [r7, #4]
800eef4: 683b ldr r3, [r7, #0]
800eef6: 781b ldrb r3, [r3, #0]
800eef8: 009b lsls r3, r3, #2
800eefa: 441a add r2, r3
800eefc: f8b7 308c ldrh.w r3, [r7, #140] @ 0x8c
800ef00: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800ef04: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800ef08: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800ef0c: f043 0380 orr.w r3, r3, #128 @ 0x80
800ef10: b29b uxth r3, r3
800ef12: 8013 strh r3, [r2, #0]
}
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
800ef14: 683b ldr r3, [r7, #0]
800ef16: 699a ldr r2, [r3, #24]
800ef18: 683b ldr r3, [r7, #0]
800ef1a: 691b ldr r3, [r3, #16]
800ef1c: 429a cmp r2, r3
800ef1e: d907 bls.n 800ef30 <USB_EPStartXfer+0xa56>
{
ep->xfer_len -= ep->maxpacket;
800ef20: 683b ldr r3, [r7, #0]
800ef22: 699a ldr r2, [r3, #24]
800ef24: 683b ldr r3, [r7, #0]
800ef26: 691b ldr r3, [r3, #16]
800ef28: 1ad2 subs r2, r2, r3
800ef2a: 683b ldr r3, [r7, #0]
800ef2c: 619a str r2, [r3, #24]
800ef2e: e054 b.n 800efda <USB_EPStartXfer+0xb00>
}
else
{
ep->xfer_len = 0U;
800ef30: 683b ldr r3, [r7, #0]
800ef32: 2200 movs r2, #0
800ef34: 619a str r2, [r3, #24]
800ef36: e050 b.n 800efda <USB_EPStartXfer+0xb00>
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
800ef38: 683b ldr r3, [r7, #0]
800ef3a: 78db ldrb r3, [r3, #3]
800ef3c: 2b02 cmp r3, #2
800ef3e: d142 bne.n 800efc6 <USB_EPStartXfer+0xaec>
{
/* Coming from ISR */
if (ep->xfer_count != 0U)
800ef40: 683b ldr r3, [r7, #0]
800ef42: 69db ldr r3, [r3, #28]
800ef44: 2b00 cmp r3, #0
800ef46: d048 beq.n 800efda <USB_EPStartXfer+0xb00>
{
/* Update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
800ef48: 687a ldr r2, [r7, #4]
800ef4a: 683b ldr r3, [r7, #0]
800ef4c: 781b ldrb r3, [r3, #0]
800ef4e: 009b lsls r3, r3, #2
800ef50: 4413 add r3, r2
800ef52: 881b ldrh r3, [r3, #0]
800ef54: f8a7 3092 strh.w r3, [r7, #146] @ 0x92
/* Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
800ef58: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
800ef5c: f403 4380 and.w r3, r3, #16384 @ 0x4000
800ef60: 2b00 cmp r3, #0
800ef62: d005 beq.n 800ef70 <USB_EPStartXfer+0xa96>
800ef64: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
800ef68: f003 0340 and.w r3, r3, #64 @ 0x40
800ef6c: 2b00 cmp r3, #0
800ef6e: d10b bne.n 800ef88 <USB_EPStartXfer+0xaae>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
800ef70: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
800ef74: f403 4380 and.w r3, r3, #16384 @ 0x4000
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
800ef78: 2b00 cmp r3, #0
800ef7a: d12e bne.n 800efda <USB_EPStartXfer+0xb00>
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
800ef7c: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92
800ef80: f003 0340 and.w r3, r3, #64 @ 0x40
800ef84: 2b00 cmp r3, #0
800ef86: d128 bne.n 800efda <USB_EPStartXfer+0xb00>
{
PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
800ef88: 687a ldr r2, [r7, #4]
800ef8a: 683b ldr r3, [r7, #0]
800ef8c: 781b ldrb r3, [r3, #0]
800ef8e: 009b lsls r3, r3, #2
800ef90: 4413 add r3, r2
800ef92: 881b ldrh r3, [r3, #0]
800ef94: b29b uxth r3, r3
800ef96: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800ef9a: f023 0370 bic.w r3, r3, #112 @ 0x70
800ef9e: f8a7 3090 strh.w r3, [r7, #144] @ 0x90
800efa2: 687a ldr r2, [r7, #4]
800efa4: 683b ldr r3, [r7, #0]
800efa6: 781b ldrb r3, [r3, #0]
800efa8: 009b lsls r3, r3, #2
800efaa: 441a add r2, r3
800efac: f8b7 3090 ldrh.w r3, [r7, #144] @ 0x90
800efb0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800efb4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800efb8: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800efbc: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800efc0: b29b uxth r3, r3
800efc2: 8013 strh r3, [r2, #0]
800efc4: e009 b.n 800efda <USB_EPStartXfer+0xb00>
}
}
}
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
800efc6: 683b ldr r3, [r7, #0]
800efc8: 78db ldrb r3, [r3, #3]
800efca: 2b01 cmp r3, #1
800efcc: d103 bne.n 800efd6 <USB_EPStartXfer+0xafc>
{
/* Only single packet transfer supported in FS */
ep->xfer_len = 0U;
800efce: 683b ldr r3, [r7, #0]
800efd0: 2200 movs r2, #0
800efd2: 619a str r2, [r3, #24]
800efd4: e001 b.n 800efda <USB_EPStartXfer+0xb00>
}
else
{
return HAL_ERROR;
800efd6: 2301 movs r3, #1
800efd8: e02a b.n 800f030 <USB_EPStartXfer+0xb56>
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
800efda: 687a ldr r2, [r7, #4]
800efdc: 683b ldr r3, [r7, #0]
800efde: 781b ldrb r3, [r3, #0]
800efe0: 009b lsls r3, r3, #2
800efe2: 4413 add r3, r2
800efe4: 881b ldrh r3, [r3, #0]
800efe6: b29b uxth r3, r3
800efe8: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800efec: f023 0370 bic.w r3, r3, #112 @ 0x70
800eff0: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
800eff4: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
800eff8: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800effc: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
800f000: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
800f004: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800f008: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
800f00c: 687a ldr r2, [r7, #4]
800f00e: 683b ldr r3, [r7, #0]
800f010: 781b ldrb r3, [r3, #0]
800f012: 009b lsls r3, r3, #2
800f014: 441a add r2, r3
800f016: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
800f01a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800f01e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800f022: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800f026: f043 0380 orr.w r3, r3, #128 @ 0x80
800f02a: b29b uxth r3, r3
800f02c: 8013 strh r3, [r2, #0]
}
return HAL_OK;
800f02e: 2300 movs r3, #0
}
800f030: 4618 mov r0, r3
800f032: 37b0 adds r7, #176 @ 0xb0
800f034: 46bd mov sp, r7
800f036: bd80 pop {r7, pc}
0800f038 <USB_EPSetStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
800f038: b480 push {r7}
800f03a: b085 sub sp, #20
800f03c: af00 add r7, sp, #0
800f03e: 6078 str r0, [r7, #4]
800f040: 6039 str r1, [r7, #0]
if (ep->is_in != 0U)
800f042: 683b ldr r3, [r7, #0]
800f044: 785b ldrb r3, [r3, #1]
800f046: 2b00 cmp r3, #0
800f048: d020 beq.n 800f08c <USB_EPSetStall+0x54>
{
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
800f04a: 687a ldr r2, [r7, #4]
800f04c: 683b ldr r3, [r7, #0]
800f04e: 781b ldrb r3, [r3, #0]
800f050: 009b lsls r3, r3, #2
800f052: 4413 add r3, r2
800f054: 881b ldrh r3, [r3, #0]
800f056: b29b uxth r3, r3
800f058: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800f05c: f023 0340 bic.w r3, r3, #64 @ 0x40
800f060: 81bb strh r3, [r7, #12]
800f062: 89bb ldrh r3, [r7, #12]
800f064: f083 0310 eor.w r3, r3, #16
800f068: 81bb strh r3, [r7, #12]
800f06a: 687a ldr r2, [r7, #4]
800f06c: 683b ldr r3, [r7, #0]
800f06e: 781b ldrb r3, [r3, #0]
800f070: 009b lsls r3, r3, #2
800f072: 441a add r2, r3
800f074: 89bb ldrh r3, [r7, #12]
800f076: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800f07a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800f07e: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800f082: f043 0380 orr.w r3, r3, #128 @ 0x80
800f086: b29b uxth r3, r3
800f088: 8013 strh r3, [r2, #0]
800f08a: e01f b.n 800f0cc <USB_EPSetStall+0x94>
}
else
{
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
800f08c: 687a ldr r2, [r7, #4]
800f08e: 683b ldr r3, [r7, #0]
800f090: 781b ldrb r3, [r3, #0]
800f092: 009b lsls r3, r3, #2
800f094: 4413 add r3, r2
800f096: 881b ldrh r3, [r3, #0]
800f098: b29b uxth r3, r3
800f09a: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800f09e: f023 0370 bic.w r3, r3, #112 @ 0x70
800f0a2: 81fb strh r3, [r7, #14]
800f0a4: 89fb ldrh r3, [r7, #14]
800f0a6: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800f0aa: 81fb strh r3, [r7, #14]
800f0ac: 687a ldr r2, [r7, #4]
800f0ae: 683b ldr r3, [r7, #0]
800f0b0: 781b ldrb r3, [r3, #0]
800f0b2: 009b lsls r3, r3, #2
800f0b4: 441a add r2, r3
800f0b6: 89fb ldrh r3, [r7, #14]
800f0b8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800f0bc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800f0c0: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800f0c4: f043 0380 orr.w r3, r3, #128 @ 0x80
800f0c8: b29b uxth r3, r3
800f0ca: 8013 strh r3, [r2, #0]
}
return HAL_OK;
800f0cc: 2300 movs r3, #0
}
800f0ce: 4618 mov r0, r3
800f0d0: 3714 adds r7, #20
800f0d2: 46bd mov sp, r7
800f0d4: f85d 7b04 ldr.w r7, [sp], #4
800f0d8: 4770 bx lr
0800f0da <USB_EPClearStall>:
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
800f0da: b480 push {r7}
800f0dc: b087 sub sp, #28
800f0de: af00 add r7, sp, #0
800f0e0: 6078 str r0, [r7, #4]
800f0e2: 6039 str r1, [r7, #0]
if (ep->is_in != 0U)
800f0e4: 683b ldr r3, [r7, #0]
800f0e6: 785b ldrb r3, [r3, #1]
800f0e8: 2b00 cmp r3, #0
800f0ea: d04c beq.n 800f186 <USB_EPClearStall+0xac>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800f0ec: 687a ldr r2, [r7, #4]
800f0ee: 683b ldr r3, [r7, #0]
800f0f0: 781b ldrb r3, [r3, #0]
800f0f2: 009b lsls r3, r3, #2
800f0f4: 4413 add r3, r2
800f0f6: 881b ldrh r3, [r3, #0]
800f0f8: 823b strh r3, [r7, #16]
800f0fa: 8a3b ldrh r3, [r7, #16]
800f0fc: f003 0340 and.w r3, r3, #64 @ 0x40
800f100: 2b00 cmp r3, #0
800f102: d01b beq.n 800f13c <USB_EPClearStall+0x62>
800f104: 687a ldr r2, [r7, #4]
800f106: 683b ldr r3, [r7, #0]
800f108: 781b ldrb r3, [r3, #0]
800f10a: 009b lsls r3, r3, #2
800f10c: 4413 add r3, r2
800f10e: 881b ldrh r3, [r3, #0]
800f110: b29b uxth r3, r3
800f112: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800f116: f023 0370 bic.w r3, r3, #112 @ 0x70
800f11a: 81fb strh r3, [r7, #14]
800f11c: 687a ldr r2, [r7, #4]
800f11e: 683b ldr r3, [r7, #0]
800f120: 781b ldrb r3, [r3, #0]
800f122: 009b lsls r3, r3, #2
800f124: 441a add r2, r3
800f126: 89fb ldrh r3, [r7, #14]
800f128: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800f12c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800f130: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800f134: f043 03c0 orr.w r3, r3, #192 @ 0xc0
800f138: b29b uxth r3, r3
800f13a: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800f13c: 683b ldr r3, [r7, #0]
800f13e: 78db ldrb r3, [r3, #3]
800f140: 2b01 cmp r3, #1
800f142: d06c beq.n 800f21e <USB_EPClearStall+0x144>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
800f144: 687a ldr r2, [r7, #4]
800f146: 683b ldr r3, [r7, #0]
800f148: 781b ldrb r3, [r3, #0]
800f14a: 009b lsls r3, r3, #2
800f14c: 4413 add r3, r2
800f14e: 881b ldrh r3, [r3, #0]
800f150: b29b uxth r3, r3
800f152: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800f156: f023 0340 bic.w r3, r3, #64 @ 0x40
800f15a: 81bb strh r3, [r7, #12]
800f15c: 89bb ldrh r3, [r7, #12]
800f15e: f083 0320 eor.w r3, r3, #32
800f162: 81bb strh r3, [r7, #12]
800f164: 687a ldr r2, [r7, #4]
800f166: 683b ldr r3, [r7, #0]
800f168: 781b ldrb r3, [r3, #0]
800f16a: 009b lsls r3, r3, #2
800f16c: 441a add r2, r3
800f16e: 89bb ldrh r3, [r7, #12]
800f170: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800f174: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800f178: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800f17c: f043 0380 orr.w r3, r3, #128 @ 0x80
800f180: b29b uxth r3, r3
800f182: 8013 strh r3, [r2, #0]
800f184: e04b b.n 800f21e <USB_EPClearStall+0x144>
}
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
800f186: 687a ldr r2, [r7, #4]
800f188: 683b ldr r3, [r7, #0]
800f18a: 781b ldrb r3, [r3, #0]
800f18c: 009b lsls r3, r3, #2
800f18e: 4413 add r3, r2
800f190: 881b ldrh r3, [r3, #0]
800f192: 82fb strh r3, [r7, #22]
800f194: 8afb ldrh r3, [r7, #22]
800f196: f403 4380 and.w r3, r3, #16384 @ 0x4000
800f19a: 2b00 cmp r3, #0
800f19c: d01b beq.n 800f1d6 <USB_EPClearStall+0xfc>
800f19e: 687a ldr r2, [r7, #4]
800f1a0: 683b ldr r3, [r7, #0]
800f1a2: 781b ldrb r3, [r3, #0]
800f1a4: 009b lsls r3, r3, #2
800f1a6: 4413 add r3, r2
800f1a8: 881b ldrh r3, [r3, #0]
800f1aa: b29b uxth r3, r3
800f1ac: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800f1b0: f023 0370 bic.w r3, r3, #112 @ 0x70
800f1b4: 82bb strh r3, [r7, #20]
800f1b6: 687a ldr r2, [r7, #4]
800f1b8: 683b ldr r3, [r7, #0]
800f1ba: 781b ldrb r3, [r3, #0]
800f1bc: 009b lsls r3, r3, #2
800f1be: 441a add r2, r3
800f1c0: 8abb ldrh r3, [r7, #20]
800f1c2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800f1c6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800f1ca: f443 4340 orr.w r3, r3, #49152 @ 0xc000
800f1ce: f043 0380 orr.w r3, r3, #128 @ 0x80
800f1d2: b29b uxth r3, r3
800f1d4: 8013 strh r3, [r2, #0]
/* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
800f1d6: 687a ldr r2, [r7, #4]
800f1d8: 683b ldr r3, [r7, #0]
800f1da: 781b ldrb r3, [r3, #0]
800f1dc: 009b lsls r3, r3, #2
800f1de: 4413 add r3, r2
800f1e0: 881b ldrh r3, [r3, #0]
800f1e2: b29b uxth r3, r3
800f1e4: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800f1e8: f023 0370 bic.w r3, r3, #112 @ 0x70
800f1ec: 827b strh r3, [r7, #18]
800f1ee: 8a7b ldrh r3, [r7, #18]
800f1f0: f483 5380 eor.w r3, r3, #4096 @ 0x1000
800f1f4: 827b strh r3, [r7, #18]
800f1f6: 8a7b ldrh r3, [r7, #18]
800f1f8: f483 5300 eor.w r3, r3, #8192 @ 0x2000
800f1fc: 827b strh r3, [r7, #18]
800f1fe: 687a ldr r2, [r7, #4]
800f200: 683b ldr r3, [r7, #0]
800f202: 781b ldrb r3, [r3, #0]
800f204: 009b lsls r3, r3, #2
800f206: 441a add r2, r3
800f208: 8a7b ldrh r3, [r7, #18]
800f20a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
800f20e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
800f212: f443 4300 orr.w r3, r3, #32768 @ 0x8000
800f216: f043 0380 orr.w r3, r3, #128 @ 0x80
800f21a: b29b uxth r3, r3
800f21c: 8013 strh r3, [r2, #0]
}
return HAL_OK;
800f21e: 2300 movs r3, #0
}
800f220: 4618 mov r0, r3
800f222: 371c adds r7, #28
800f224: 46bd mov sp, r7
800f226: f85d 7b04 ldr.w r7, [sp], #4
800f22a: 4770 bx lr
0800f22c <USB_SetDevAddress>:
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
{
800f22c: b480 push {r7}
800f22e: b083 sub sp, #12
800f230: af00 add r7, sp, #0
800f232: 6078 str r0, [r7, #4]
800f234: 460b mov r3, r1
800f236: 70fb strb r3, [r7, #3]
if (address == 0U)
800f238: 78fb ldrb r3, [r7, #3]
800f23a: 2b00 cmp r3, #0
800f23c: d103 bne.n 800f246 <USB_SetDevAddress+0x1a>
{
/* set device address and enable function */
USBx->DADDR = (uint16_t)USB_DADDR_EF;
800f23e: 687b ldr r3, [r7, #4]
800f240: 2280 movs r2, #128 @ 0x80
800f242: f8a3 204c strh.w r2, [r3, #76] @ 0x4c
}
return HAL_OK;
800f246: 2300 movs r3, #0
}
800f248: 4618 mov r0, r3
800f24a: 370c adds r7, #12
800f24c: 46bd mov sp, r7
800f24e: f85d 7b04 ldr.w r7, [sp], #4
800f252: 4770 bx lr
0800f254 <USB_DevConnect>:
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
800f254: b480 push {r7}
800f256: b083 sub sp, #12
800f258: af00 add r7, sp, #0
800f25a: 6078 str r0, [r7, #4]
/* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
800f25c: 687b ldr r3, [r7, #4]
800f25e: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
800f262: b29b uxth r3, r3
800f264: ea6f 4343 mvn.w r3, r3, lsl #17
800f268: ea6f 4353 mvn.w r3, r3, lsr #17
800f26c: b29a uxth r2, r3
800f26e: 687b ldr r3, [r7, #4]
800f270: f8a3 2058 strh.w r2, [r3, #88] @ 0x58
return HAL_OK;
800f274: 2300 movs r3, #0
}
800f276: 4618 mov r0, r3
800f278: 370c adds r7, #12
800f27a: 46bd mov sp, r7
800f27c: f85d 7b04 ldr.w r7, [sp], #4
800f280: 4770 bx lr
0800f282 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
{
800f282: b480 push {r7}
800f284: b085 sub sp, #20
800f286: af00 add r7, sp, #0
800f288: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->ISTR;
800f28a: 687b ldr r3, [r7, #4]
800f28c: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44
800f290: b29b uxth r3, r3
800f292: 60fb str r3, [r7, #12]
return tmpreg;
800f294: 68fb ldr r3, [r7, #12]
}
800f296: 4618 mov r0, r3
800f298: 3714 adds r7, #20
800f29a: 46bd mov sp, r7
800f29c: f85d 7b04 ldr.w r7, [sp], #4
800f2a0: 4770 bx lr
0800f2a2 <USB_WritePMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
800f2a2: b480 push {r7}
800f2a4: b08b sub sp, #44 @ 0x2c
800f2a6: af00 add r7, sp, #0
800f2a8: 60f8 str r0, [r7, #12]
800f2aa: 60b9 str r1, [r7, #8]
800f2ac: 4611 mov r1, r2
800f2ae: 461a mov r2, r3
800f2b0: 460b mov r3, r1
800f2b2: 80fb strh r3, [r7, #6]
800f2b4: 4613 mov r3, r2
800f2b6: 80bb strh r3, [r7, #4]
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
800f2b8: 88bb ldrh r3, [r7, #4]
800f2ba: 3301 adds r3, #1
800f2bc: 085b lsrs r3, r3, #1
800f2be: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
800f2c0: 68fb ldr r3, [r7, #12]
800f2c2: 617b str r3, [r7, #20]
uint32_t count;
uint16_t WrVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
800f2c4: 68bb ldr r3, [r7, #8]
800f2c6: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
800f2c8: 88fa ldrh r2, [r7, #6]
800f2ca: 697b ldr r3, [r7, #20]
800f2cc: 4413 add r3, r2
800f2ce: f503 6380 add.w r3, r3, #1024 @ 0x400
800f2d2: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
800f2d4: 69bb ldr r3, [r7, #24]
800f2d6: 627b str r3, [r7, #36] @ 0x24
800f2d8: e01c b.n 800f314 <USB_WritePMA+0x72>
{
WrVal = pBuf[0];
800f2da: 69fb ldr r3, [r7, #28]
800f2dc: 781b ldrb r3, [r3, #0]
800f2de: 827b strh r3, [r7, #18]
WrVal |= (uint16_t)pBuf[1] << 8;
800f2e0: 69fb ldr r3, [r7, #28]
800f2e2: 3301 adds r3, #1
800f2e4: 781b ldrb r3, [r3, #0]
800f2e6: b21b sxth r3, r3
800f2e8: 021b lsls r3, r3, #8
800f2ea: b21a sxth r2, r3
800f2ec: f9b7 3012 ldrsh.w r3, [r7, #18]
800f2f0: 4313 orrs r3, r2
800f2f2: b21b sxth r3, r3
800f2f4: 827b strh r3, [r7, #18]
*pdwVal = (WrVal & 0xFFFFU);
800f2f6: 6a3b ldr r3, [r7, #32]
800f2f8: 8a7a ldrh r2, [r7, #18]
800f2fa: 801a strh r2, [r3, #0]
pdwVal++;
800f2fc: 6a3b ldr r3, [r7, #32]
800f2fe: 3302 adds r3, #2
800f300: 623b str r3, [r7, #32]
#if PMA_ACCESS > 1U
pdwVal++;
#endif /* PMA_ACCESS */
pBuf++;
800f302: 69fb ldr r3, [r7, #28]
800f304: 3301 adds r3, #1
800f306: 61fb str r3, [r7, #28]
pBuf++;
800f308: 69fb ldr r3, [r7, #28]
800f30a: 3301 adds r3, #1
800f30c: 61fb str r3, [r7, #28]
for (count = n; count != 0U; count--)
800f30e: 6a7b ldr r3, [r7, #36] @ 0x24
800f310: 3b01 subs r3, #1
800f312: 627b str r3, [r7, #36] @ 0x24
800f314: 6a7b ldr r3, [r7, #36] @ 0x24
800f316: 2b00 cmp r3, #0
800f318: d1df bne.n 800f2da <USB_WritePMA+0x38>
}
}
800f31a: bf00 nop
800f31c: bf00 nop
800f31e: 372c adds r7, #44 @ 0x2c
800f320: 46bd mov sp, r7
800f322: f85d 7b04 ldr.w r7, [sp], #4
800f326: 4770 bx lr
0800f328 <USB_ReadPMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
800f328: b480 push {r7}
800f32a: b08b sub sp, #44 @ 0x2c
800f32c: af00 add r7, sp, #0
800f32e: 60f8 str r0, [r7, #12]
800f330: 60b9 str r1, [r7, #8]
800f332: 4611 mov r1, r2
800f334: 461a mov r2, r3
800f336: 460b mov r3, r1
800f338: 80fb strh r3, [r7, #6]
800f33a: 4613 mov r3, r2
800f33c: 80bb strh r3, [r7, #4]
uint32_t n = (uint32_t)wNBytes >> 1;
800f33e: 88bb ldrh r3, [r7, #4]
800f340: 085b lsrs r3, r3, #1
800f342: b29b uxth r3, r3
800f344: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
800f346: 68fb ldr r3, [r7, #12]
800f348: 617b str r3, [r7, #20]
uint32_t count;
uint32_t RdVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
800f34a: 68bb ldr r3, [r7, #8]
800f34c: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
800f34e: 88fa ldrh r2, [r7, #6]
800f350: 697b ldr r3, [r7, #20]
800f352: 4413 add r3, r2
800f354: f503 6380 add.w r3, r3, #1024 @ 0x400
800f358: 623b str r3, [r7, #32]
for (count = n; count != 0U; count--)
800f35a: 69bb ldr r3, [r7, #24]
800f35c: 627b str r3, [r7, #36] @ 0x24
800f35e: e018 b.n 800f392 <USB_ReadPMA+0x6a>
{
RdVal = *(__IO uint16_t *)pdwVal;
800f360: 6a3b ldr r3, [r7, #32]
800f362: 881b ldrh r3, [r3, #0]
800f364: b29b uxth r3, r3
800f366: 613b str r3, [r7, #16]
pdwVal++;
800f368: 6a3b ldr r3, [r7, #32]
800f36a: 3302 adds r3, #2
800f36c: 623b str r3, [r7, #32]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
800f36e: 693b ldr r3, [r7, #16]
800f370: b2da uxtb r2, r3
800f372: 69fb ldr r3, [r7, #28]
800f374: 701a strb r2, [r3, #0]
pBuf++;
800f376: 69fb ldr r3, [r7, #28]
800f378: 3301 adds r3, #1
800f37a: 61fb str r3, [r7, #28]
*pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
800f37c: 693b ldr r3, [r7, #16]
800f37e: 0a1b lsrs r3, r3, #8
800f380: b2da uxtb r2, r3
800f382: 69fb ldr r3, [r7, #28]
800f384: 701a strb r2, [r3, #0]
pBuf++;
800f386: 69fb ldr r3, [r7, #28]
800f388: 3301 adds r3, #1
800f38a: 61fb str r3, [r7, #28]
for (count = n; count != 0U; count--)
800f38c: 6a7b ldr r3, [r7, #36] @ 0x24
800f38e: 3b01 subs r3, #1
800f390: 627b str r3, [r7, #36] @ 0x24
800f392: 6a7b ldr r3, [r7, #36] @ 0x24
800f394: 2b00 cmp r3, #0
800f396: d1e3 bne.n 800f360 <USB_ReadPMA+0x38>
#if PMA_ACCESS > 1U
pdwVal++;
#endif /* PMA_ACCESS */
}
if ((wNBytes % 2U) != 0U)
800f398: 88bb ldrh r3, [r7, #4]
800f39a: f003 0301 and.w r3, r3, #1
800f39e: b29b uxth r3, r3
800f3a0: 2b00 cmp r3, #0
800f3a2: d007 beq.n 800f3b4 <USB_ReadPMA+0x8c>
{
RdVal = *pdwVal;
800f3a4: 6a3b ldr r3, [r7, #32]
800f3a6: 881b ldrh r3, [r3, #0]
800f3a8: b29b uxth r3, r3
800f3aa: 613b str r3, [r7, #16]
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
800f3ac: 693b ldr r3, [r7, #16]
800f3ae: b2da uxtb r2, r3
800f3b0: 69fb ldr r3, [r7, #28]
800f3b2: 701a strb r2, [r3, #0]
}
}
800f3b4: bf00 nop
800f3b6: 372c adds r7, #44 @ 0x2c
800f3b8: 46bd mov sp, r7
800f3ba: f85d 7b04 ldr.w r7, [sp], #4
800f3be: 4770 bx lr
0800f3c0 <USBD_CDC_Init>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800f3c0: b580 push {r7, lr}
800f3c2: b084 sub sp, #16
800f3c4: af00 add r7, sp, #0
800f3c6: 6078 str r0, [r7, #4]
800f3c8: 460b mov r3, r1
800f3ca: 70fb strb r3, [r7, #3]
UNUSED(cfgidx);
USBD_CDC_HandleTypeDef *hcdc;
hcdc = (USBD_CDC_HandleTypeDef *)USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
800f3cc: f44f 7007 mov.w r0, #540 @ 0x21c
800f3d0: f008 f9e0 bl 8017794 <USBD_static_malloc>
800f3d4: 60f8 str r0, [r7, #12]
if (hcdc == NULL)
800f3d6: 68fb ldr r3, [r7, #12]
800f3d8: 2b00 cmp r3, #0
800f3da: d109 bne.n 800f3f0 <USBD_CDC_Init+0x30>
{
pdev->pClassDataCmsit[pdev->classId] = NULL;
800f3dc: 687b ldr r3, [r7, #4]
800f3de: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f3e2: 687b ldr r3, [r7, #4]
800f3e4: 32b0 adds r2, #176 @ 0xb0
800f3e6: 2100 movs r1, #0
800f3e8: f843 1022 str.w r1, [r3, r2, lsl #2]
return (uint8_t)USBD_EMEM;
800f3ec: 2302 movs r3, #2
800f3ee: e0d4 b.n 800f59a <USBD_CDC_Init+0x1da>
}
(void)USBD_memset(hcdc, 0, sizeof(USBD_CDC_HandleTypeDef));
800f3f0: f44f 7207 mov.w r2, #540 @ 0x21c
800f3f4: 2100 movs r1, #0
800f3f6: 68f8 ldr r0, [r7, #12]
800f3f8: f009 faec bl 80189d4 <memset>
pdev->pClassDataCmsit[pdev->classId] = (void *)hcdc;
800f3fc: 687b ldr r3, [r7, #4]
800f3fe: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f402: 687b ldr r3, [r7, #4]
800f404: 32b0 adds r2, #176 @ 0xb0
800f406: 68f9 ldr r1, [r7, #12]
800f408: f843 1022 str.w r1, [r3, r2, lsl #2]
pdev->pClassData = pdev->pClassDataCmsit[pdev->classId];
800f40c: 687b ldr r3, [r7, #4]
800f40e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f412: 687b ldr r3, [r7, #4]
800f414: 32b0 adds r2, #176 @ 0xb0
800f416: f853 2022 ldr.w r2, [r3, r2, lsl #2]
800f41a: 687b ldr r3, [r7, #4]
800f41c: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId);
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId);
CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
#endif /* USE_USBD_COMPOSITE */
if (pdev->dev_speed == USBD_SPEED_HIGH)
800f420: 687b ldr r3, [r7, #4]
800f422: 7c1b ldrb r3, [r3, #16]
800f424: 2b00 cmp r3, #0
800f426: d138 bne.n 800f49a <USBD_CDC_Init+0xda>
{
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK,
800f428: 4b5e ldr r3, [pc, #376] @ (800f5a4 <USBD_CDC_Init+0x1e4>)
800f42a: 7819 ldrb r1, [r3, #0]
800f42c: f44f 7300 mov.w r3, #512 @ 0x200
800f430: 2202 movs r2, #2
800f432: 6878 ldr r0, [r7, #4]
800f434: f008 f855 bl 80174e2 <USBD_LL_OpenEP>
CDC_DATA_HS_IN_PACKET_SIZE);
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U;
800f438: 4b5a ldr r3, [pc, #360] @ (800f5a4 <USBD_CDC_Init+0x1e4>)
800f43a: 781b ldrb r3, [r3, #0]
800f43c: f003 020f and.w r2, r3, #15
800f440: 6879 ldr r1, [r7, #4]
800f442: 4613 mov r3, r2
800f444: 009b lsls r3, r3, #2
800f446: 4413 add r3, r2
800f448: 009b lsls r3, r3, #2
800f44a: 440b add r3, r1
800f44c: 3323 adds r3, #35 @ 0x23
800f44e: 2201 movs r2, #1
800f450: 701a strb r2, [r3, #0]
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK,
800f452: 4b55 ldr r3, [pc, #340] @ (800f5a8 <USBD_CDC_Init+0x1e8>)
800f454: 7819 ldrb r1, [r3, #0]
800f456: f44f 7300 mov.w r3, #512 @ 0x200
800f45a: 2202 movs r2, #2
800f45c: 6878 ldr r0, [r7, #4]
800f45e: f008 f840 bl 80174e2 <USBD_LL_OpenEP>
CDC_DATA_HS_OUT_PACKET_SIZE);
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U;
800f462: 4b51 ldr r3, [pc, #324] @ (800f5a8 <USBD_CDC_Init+0x1e8>)
800f464: 781b ldrb r3, [r3, #0]
800f466: f003 020f and.w r2, r3, #15
800f46a: 6879 ldr r1, [r7, #4]
800f46c: 4613 mov r3, r2
800f46e: 009b lsls r3, r3, #2
800f470: 4413 add r3, r2
800f472: 009b lsls r3, r3, #2
800f474: 440b add r3, r1
800f476: f203 1363 addw r3, r3, #355 @ 0x163
800f47a: 2201 movs r2, #1
800f47c: 701a strb r2, [r3, #0]
/* Set bInterval for CDC CMD Endpoint */
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_HS_BINTERVAL;
800f47e: 4b4b ldr r3, [pc, #300] @ (800f5ac <USBD_CDC_Init+0x1ec>)
800f480: 781b ldrb r3, [r3, #0]
800f482: f003 020f and.w r2, r3, #15
800f486: 6879 ldr r1, [r7, #4]
800f488: 4613 mov r3, r2
800f48a: 009b lsls r3, r3, #2
800f48c: 4413 add r3, r2
800f48e: 009b lsls r3, r3, #2
800f490: 440b add r3, r1
800f492: 331c adds r3, #28
800f494: 2210 movs r2, #16
800f496: 601a str r2, [r3, #0]
800f498: e035 b.n 800f506 <USBD_CDC_Init+0x146>
}
else
{
/* Open EP IN */
(void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK,
800f49a: 4b42 ldr r3, [pc, #264] @ (800f5a4 <USBD_CDC_Init+0x1e4>)
800f49c: 7819 ldrb r1, [r3, #0]
800f49e: 2340 movs r3, #64 @ 0x40
800f4a0: 2202 movs r2, #2
800f4a2: 6878 ldr r0, [r7, #4]
800f4a4: f008 f81d bl 80174e2 <USBD_LL_OpenEP>
CDC_DATA_FS_IN_PACKET_SIZE);
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U;
800f4a8: 4b3e ldr r3, [pc, #248] @ (800f5a4 <USBD_CDC_Init+0x1e4>)
800f4aa: 781b ldrb r3, [r3, #0]
800f4ac: f003 020f and.w r2, r3, #15
800f4b0: 6879 ldr r1, [r7, #4]
800f4b2: 4613 mov r3, r2
800f4b4: 009b lsls r3, r3, #2
800f4b6: 4413 add r3, r2
800f4b8: 009b lsls r3, r3, #2
800f4ba: 440b add r3, r1
800f4bc: 3323 adds r3, #35 @ 0x23
800f4be: 2201 movs r2, #1
800f4c0: 701a strb r2, [r3, #0]
/* Open EP OUT */
(void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK,
800f4c2: 4b39 ldr r3, [pc, #228] @ (800f5a8 <USBD_CDC_Init+0x1e8>)
800f4c4: 7819 ldrb r1, [r3, #0]
800f4c6: 2340 movs r3, #64 @ 0x40
800f4c8: 2202 movs r2, #2
800f4ca: 6878 ldr r0, [r7, #4]
800f4cc: f008 f809 bl 80174e2 <USBD_LL_OpenEP>
CDC_DATA_FS_OUT_PACKET_SIZE);
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U;
800f4d0: 4b35 ldr r3, [pc, #212] @ (800f5a8 <USBD_CDC_Init+0x1e8>)
800f4d2: 781b ldrb r3, [r3, #0]
800f4d4: f003 020f and.w r2, r3, #15
800f4d8: 6879 ldr r1, [r7, #4]
800f4da: 4613 mov r3, r2
800f4dc: 009b lsls r3, r3, #2
800f4de: 4413 add r3, r2
800f4e0: 009b lsls r3, r3, #2
800f4e2: 440b add r3, r1
800f4e4: f203 1363 addw r3, r3, #355 @ 0x163
800f4e8: 2201 movs r2, #1
800f4ea: 701a strb r2, [r3, #0]
/* Set bInterval for CMD Endpoint */
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_FS_BINTERVAL;
800f4ec: 4b2f ldr r3, [pc, #188] @ (800f5ac <USBD_CDC_Init+0x1ec>)
800f4ee: 781b ldrb r3, [r3, #0]
800f4f0: f003 020f and.w r2, r3, #15
800f4f4: 6879 ldr r1, [r7, #4]
800f4f6: 4613 mov r3, r2
800f4f8: 009b lsls r3, r3, #2
800f4fa: 4413 add r3, r2
800f4fc: 009b lsls r3, r3, #2
800f4fe: 440b add r3, r1
800f500: 331c adds r3, #28
800f502: 2210 movs r2, #16
800f504: 601a str r2, [r3, #0]
}
/* Open Command IN EP */
(void)USBD_LL_OpenEP(pdev, CDCCmdEpAdd, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
800f506: 4b29 ldr r3, [pc, #164] @ (800f5ac <USBD_CDC_Init+0x1ec>)
800f508: 7819 ldrb r1, [r3, #0]
800f50a: 2308 movs r3, #8
800f50c: 2203 movs r2, #3
800f50e: 6878 ldr r0, [r7, #4]
800f510: f007 ffe7 bl 80174e2 <USBD_LL_OpenEP>
pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 1U;
800f514: 4b25 ldr r3, [pc, #148] @ (800f5ac <USBD_CDC_Init+0x1ec>)
800f516: 781b ldrb r3, [r3, #0]
800f518: f003 020f and.w r2, r3, #15
800f51c: 6879 ldr r1, [r7, #4]
800f51e: 4613 mov r3, r2
800f520: 009b lsls r3, r3, #2
800f522: 4413 add r3, r2
800f524: 009b lsls r3, r3, #2
800f526: 440b add r3, r1
800f528: 3323 adds r3, #35 @ 0x23
800f52a: 2201 movs r2, #1
800f52c: 701a strb r2, [r3, #0]
hcdc->RxBuffer = NULL;
800f52e: 68fb ldr r3, [r7, #12]
800f530: 2200 movs r2, #0
800f532: f8c3 2204 str.w r2, [r3, #516] @ 0x204
/* Init physical Interface components */
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Init();
800f536: 687b ldr r3, [r7, #4]
800f538: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800f53c: 687a ldr r2, [r7, #4]
800f53e: 33b0 adds r3, #176 @ 0xb0
800f540: 009b lsls r3, r3, #2
800f542: 4413 add r3, r2
800f544: 685b ldr r3, [r3, #4]
800f546: 681b ldr r3, [r3, #0]
800f548: 4798 blx r3
/* Init Xfer states */
hcdc->TxState = 0U;
800f54a: 68fb ldr r3, [r7, #12]
800f54c: 2200 movs r2, #0
800f54e: f8c3 2214 str.w r2, [r3, #532] @ 0x214
hcdc->RxState = 0U;
800f552: 68fb ldr r3, [r7, #12]
800f554: 2200 movs r2, #0
800f556: f8c3 2218 str.w r2, [r3, #536] @ 0x218
if (hcdc->RxBuffer == NULL)
800f55a: 68fb ldr r3, [r7, #12]
800f55c: f8d3 3204 ldr.w r3, [r3, #516] @ 0x204
800f560: 2b00 cmp r3, #0
800f562: d101 bne.n 800f568 <USBD_CDC_Init+0x1a8>
{
return (uint8_t)USBD_EMEM;
800f564: 2302 movs r3, #2
800f566: e018 b.n 800f59a <USBD_CDC_Init+0x1da>
}
if (pdev->dev_speed == USBD_SPEED_HIGH)
800f568: 687b ldr r3, [r7, #4]
800f56a: 7c1b ldrb r3, [r3, #16]
800f56c: 2b00 cmp r3, #0
800f56e: d10a bne.n 800f586 <USBD_CDC_Init+0x1c6>
{
/* Prepare Out endpoint to receive next packet */
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
800f570: 4b0d ldr r3, [pc, #52] @ (800f5a8 <USBD_CDC_Init+0x1e8>)
800f572: 7819 ldrb r1, [r3, #0]
800f574: 68fb ldr r3, [r7, #12]
800f576: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
800f57a: f44f 7300 mov.w r3, #512 @ 0x200
800f57e: 6878 ldr r0, [r7, #4]
800f580: f008 f89e bl 80176c0 <USBD_LL_PrepareReceive>
800f584: e008 b.n 800f598 <USBD_CDC_Init+0x1d8>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
800f586: 4b08 ldr r3, [pc, #32] @ (800f5a8 <USBD_CDC_Init+0x1e8>)
800f588: 7819 ldrb r1, [r3, #0]
800f58a: 68fb ldr r3, [r7, #12]
800f58c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
800f590: 2340 movs r3, #64 @ 0x40
800f592: 6878 ldr r0, [r7, #4]
800f594: f008 f894 bl 80176c0 <USBD_LL_PrepareReceive>
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return (uint8_t)USBD_OK;
800f598: 2300 movs r3, #0
}
800f59a: 4618 mov r0, r3
800f59c: 3710 adds r7, #16
800f59e: 46bd mov sp, r7
800f5a0: bd80 pop {r7, pc}
800f5a2: bf00 nop
800f5a4: 2000009f .word 0x2000009f
800f5a8: 200000a0 .word 0x200000a0
800f5ac: 200000a1 .word 0x200000a1
0800f5b0 <USBD_CDC_DeInit>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800f5b0: b580 push {r7, lr}
800f5b2: b082 sub sp, #8
800f5b4: af00 add r7, sp, #0
800f5b6: 6078 str r0, [r7, #4]
800f5b8: 460b mov r3, r1
800f5ba: 70fb strb r3, [r7, #3]
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId);
CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId);
#endif /* USE_USBD_COMPOSITE */
/* Close EP IN */
(void)USBD_LL_CloseEP(pdev, CDCInEpAdd);
800f5bc: 4b3a ldr r3, [pc, #232] @ (800f6a8 <USBD_CDC_DeInit+0xf8>)
800f5be: 781b ldrb r3, [r3, #0]
800f5c0: 4619 mov r1, r3
800f5c2: 6878 ldr r0, [r7, #4]
800f5c4: f007 ffb3 bl 801752e <USBD_LL_CloseEP>
pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 0U;
800f5c8: 4b37 ldr r3, [pc, #220] @ (800f6a8 <USBD_CDC_DeInit+0xf8>)
800f5ca: 781b ldrb r3, [r3, #0]
800f5cc: f003 020f and.w r2, r3, #15
800f5d0: 6879 ldr r1, [r7, #4]
800f5d2: 4613 mov r3, r2
800f5d4: 009b lsls r3, r3, #2
800f5d6: 4413 add r3, r2
800f5d8: 009b lsls r3, r3, #2
800f5da: 440b add r3, r1
800f5dc: 3323 adds r3, #35 @ 0x23
800f5de: 2200 movs r2, #0
800f5e0: 701a strb r2, [r3, #0]
/* Close EP OUT */
(void)USBD_LL_CloseEP(pdev, CDCOutEpAdd);
800f5e2: 4b32 ldr r3, [pc, #200] @ (800f6ac <USBD_CDC_DeInit+0xfc>)
800f5e4: 781b ldrb r3, [r3, #0]
800f5e6: 4619 mov r1, r3
800f5e8: 6878 ldr r0, [r7, #4]
800f5ea: f007 ffa0 bl 801752e <USBD_LL_CloseEP>
pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 0U;
800f5ee: 4b2f ldr r3, [pc, #188] @ (800f6ac <USBD_CDC_DeInit+0xfc>)
800f5f0: 781b ldrb r3, [r3, #0]
800f5f2: f003 020f and.w r2, r3, #15
800f5f6: 6879 ldr r1, [r7, #4]
800f5f8: 4613 mov r3, r2
800f5fa: 009b lsls r3, r3, #2
800f5fc: 4413 add r3, r2
800f5fe: 009b lsls r3, r3, #2
800f600: 440b add r3, r1
800f602: f203 1363 addw r3, r3, #355 @ 0x163
800f606: 2200 movs r2, #0
800f608: 701a strb r2, [r3, #0]
/* Close Command IN EP */
(void)USBD_LL_CloseEP(pdev, CDCCmdEpAdd);
800f60a: 4b29 ldr r3, [pc, #164] @ (800f6b0 <USBD_CDC_DeInit+0x100>)
800f60c: 781b ldrb r3, [r3, #0]
800f60e: 4619 mov r1, r3
800f610: 6878 ldr r0, [r7, #4]
800f612: f007 ff8c bl 801752e <USBD_LL_CloseEP>
pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 0U;
800f616: 4b26 ldr r3, [pc, #152] @ (800f6b0 <USBD_CDC_DeInit+0x100>)
800f618: 781b ldrb r3, [r3, #0]
800f61a: f003 020f and.w r2, r3, #15
800f61e: 6879 ldr r1, [r7, #4]
800f620: 4613 mov r3, r2
800f622: 009b lsls r3, r3, #2
800f624: 4413 add r3, r2
800f626: 009b lsls r3, r3, #2
800f628: 440b add r3, r1
800f62a: 3323 adds r3, #35 @ 0x23
800f62c: 2200 movs r2, #0
800f62e: 701a strb r2, [r3, #0]
pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = 0U;
800f630: 4b1f ldr r3, [pc, #124] @ (800f6b0 <USBD_CDC_DeInit+0x100>)
800f632: 781b ldrb r3, [r3, #0]
800f634: f003 020f and.w r2, r3, #15
800f638: 6879 ldr r1, [r7, #4]
800f63a: 4613 mov r3, r2
800f63c: 009b lsls r3, r3, #2
800f63e: 4413 add r3, r2
800f640: 009b lsls r3, r3, #2
800f642: 440b add r3, r1
800f644: 331c adds r3, #28
800f646: 2200 movs r2, #0
800f648: 601a str r2, [r3, #0]
/* DeInit physical Interface components */
if (pdev->pClassDataCmsit[pdev->classId] != NULL)
800f64a: 687b ldr r3, [r7, #4]
800f64c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f650: 687b ldr r3, [r7, #4]
800f652: 32b0 adds r2, #176 @ 0xb0
800f654: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800f658: 2b00 cmp r3, #0
800f65a: d01f beq.n 800f69c <USBD_CDC_DeInit+0xec>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->DeInit();
800f65c: 687b ldr r3, [r7, #4]
800f65e: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800f662: 687a ldr r2, [r7, #4]
800f664: 33b0 adds r3, #176 @ 0xb0
800f666: 009b lsls r3, r3, #2
800f668: 4413 add r3, r2
800f66a: 685b ldr r3, [r3, #4]
800f66c: 685b ldr r3, [r3, #4]
800f66e: 4798 blx r3
(void)USBD_free(pdev->pClassDataCmsit[pdev->classId]);
800f670: 687b ldr r3, [r7, #4]
800f672: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f676: 687b ldr r3, [r7, #4]
800f678: 32b0 adds r2, #176 @ 0xb0
800f67a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800f67e: 4618 mov r0, r3
800f680: f008 f896 bl 80177b0 <USBD_static_free>
pdev->pClassDataCmsit[pdev->classId] = NULL;
800f684: 687b ldr r3, [r7, #4]
800f686: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f68a: 687b ldr r3, [r7, #4]
800f68c: 32b0 adds r2, #176 @ 0xb0
800f68e: 2100 movs r1, #0
800f690: f843 1022 str.w r1, [r3, r2, lsl #2]
pdev->pClassData = NULL;
800f694: 687b ldr r3, [r7, #4]
800f696: 2200 movs r2, #0
800f698: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc
}
return (uint8_t)USBD_OK;
800f69c: 2300 movs r3, #0
}
800f69e: 4618 mov r0, r3
800f6a0: 3708 adds r7, #8
800f6a2: 46bd mov sp, r7
800f6a4: bd80 pop {r7, pc}
800f6a6: bf00 nop
800f6a8: 2000009f .word 0x2000009f
800f6ac: 200000a0 .word 0x200000a0
800f6b0: 200000a1 .word 0x200000a1
0800f6b4 <USBD_CDC_Setup>:
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800f6b4: b580 push {r7, lr}
800f6b6: b086 sub sp, #24
800f6b8: af00 add r7, sp, #0
800f6ba: 6078 str r0, [r7, #4]
800f6bc: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
800f6be: 687b ldr r3, [r7, #4]
800f6c0: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f6c4: 687b ldr r3, [r7, #4]
800f6c6: 32b0 adds r2, #176 @ 0xb0
800f6c8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800f6cc: 613b str r3, [r7, #16]
uint16_t len;
uint8_t ifalt = 0U;
800f6ce: 2300 movs r3, #0
800f6d0: 737b strb r3, [r7, #13]
uint16_t status_info = 0U;
800f6d2: 2300 movs r3, #0
800f6d4: 817b strh r3, [r7, #10]
USBD_StatusTypeDef ret = USBD_OK;
800f6d6: 2300 movs r3, #0
800f6d8: 75fb strb r3, [r7, #23]
if (hcdc == NULL)
800f6da: 693b ldr r3, [r7, #16]
800f6dc: 2b00 cmp r3, #0
800f6de: d101 bne.n 800f6e4 <USBD_CDC_Setup+0x30>
{
return (uint8_t)USBD_FAIL;
800f6e0: 2303 movs r3, #3
800f6e2: e0bf b.n 800f864 <USBD_CDC_Setup+0x1b0>
}
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800f6e4: 683b ldr r3, [r7, #0]
800f6e6: 781b ldrb r3, [r3, #0]
800f6e8: f003 0360 and.w r3, r3, #96 @ 0x60
800f6ec: 2b00 cmp r3, #0
800f6ee: d050 beq.n 800f792 <USBD_CDC_Setup+0xde>
800f6f0: 2b20 cmp r3, #32
800f6f2: f040 80af bne.w 800f854 <USBD_CDC_Setup+0x1a0>
{
case USB_REQ_TYPE_CLASS:
if (req->wLength != 0U)
800f6f6: 683b ldr r3, [r7, #0]
800f6f8: 88db ldrh r3, [r3, #6]
800f6fa: 2b00 cmp r3, #0
800f6fc: d03a beq.n 800f774 <USBD_CDC_Setup+0xc0>
{
if ((req->bmRequest & 0x80U) != 0U)
800f6fe: 683b ldr r3, [r7, #0]
800f700: 781b ldrb r3, [r3, #0]
800f702: b25b sxtb r3, r3
800f704: 2b00 cmp r3, #0
800f706: da1b bge.n 800f740 <USBD_CDC_Setup+0x8c>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
800f708: 687b ldr r3, [r7, #4]
800f70a: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800f70e: 687a ldr r2, [r7, #4]
800f710: 33b0 adds r3, #176 @ 0xb0
800f712: 009b lsls r3, r3, #2
800f714: 4413 add r3, r2
800f716: 685b ldr r3, [r3, #4]
800f718: 689b ldr r3, [r3, #8]
800f71a: 683a ldr r2, [r7, #0]
800f71c: 7850 ldrb r0, [r2, #1]
(uint8_t *)hcdc->data,
800f71e: 6939 ldr r1, [r7, #16]
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
800f720: 683a ldr r2, [r7, #0]
800f722: 88d2 ldrh r2, [r2, #6]
800f724: 4798 blx r3
req->wLength);
len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength);
800f726: 683b ldr r3, [r7, #0]
800f728: 88db ldrh r3, [r3, #6]
800f72a: 2b07 cmp r3, #7
800f72c: bf28 it cs
800f72e: 2307 movcs r3, #7
800f730: 81fb strh r3, [r7, #14]
(void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len);
800f732: 693b ldr r3, [r7, #16]
800f734: 89fa ldrh r2, [r7, #14]
800f736: 4619 mov r1, r3
800f738: 6878 ldr r0, [r7, #4]
800f73a: f001 fd41 bl 80111c0 <USBD_CtlSendData>
else
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
(uint8_t *)req, 0U);
}
break;
800f73e: e090 b.n 800f862 <USBD_CDC_Setup+0x1ae>
hcdc->CmdOpCode = req->bRequest;
800f740: 683b ldr r3, [r7, #0]
800f742: 785a ldrb r2, [r3, #1]
800f744: 693b ldr r3, [r7, #16]
800f746: f883 2200 strb.w r2, [r3, #512] @ 0x200
hcdc->CmdLength = (uint8_t)MIN(req->wLength, USB_MAX_EP0_SIZE);
800f74a: 683b ldr r3, [r7, #0]
800f74c: 88db ldrh r3, [r3, #6]
800f74e: 2b3f cmp r3, #63 @ 0x3f
800f750: d803 bhi.n 800f75a <USBD_CDC_Setup+0xa6>
800f752: 683b ldr r3, [r7, #0]
800f754: 88db ldrh r3, [r3, #6]
800f756: b2da uxtb r2, r3
800f758: e000 b.n 800f75c <USBD_CDC_Setup+0xa8>
800f75a: 2240 movs r2, #64 @ 0x40
800f75c: 693b ldr r3, [r7, #16]
800f75e: f883 2201 strb.w r2, [r3, #513] @ 0x201
(void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, hcdc->CmdLength);
800f762: 6939 ldr r1, [r7, #16]
800f764: 693b ldr r3, [r7, #16]
800f766: f893 3201 ldrb.w r3, [r3, #513] @ 0x201
800f76a: 461a mov r2, r3
800f76c: 6878 ldr r0, [r7, #4]
800f76e: f001 fd56 bl 801121e <USBD_CtlPrepareRx>
break;
800f772: e076 b.n 800f862 <USBD_CDC_Setup+0x1ae>
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest,
800f774: 687b ldr r3, [r7, #4]
800f776: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800f77a: 687a ldr r2, [r7, #4]
800f77c: 33b0 adds r3, #176 @ 0xb0
800f77e: 009b lsls r3, r3, #2
800f780: 4413 add r3, r2
800f782: 685b ldr r3, [r3, #4]
800f784: 689b ldr r3, [r3, #8]
800f786: 683a ldr r2, [r7, #0]
800f788: 7850 ldrb r0, [r2, #1]
800f78a: 2200 movs r2, #0
800f78c: 6839 ldr r1, [r7, #0]
800f78e: 4798 blx r3
break;
800f790: e067 b.n 800f862 <USBD_CDC_Setup+0x1ae>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
800f792: 683b ldr r3, [r7, #0]
800f794: 785b ldrb r3, [r3, #1]
800f796: 2b0b cmp r3, #11
800f798: d851 bhi.n 800f83e <USBD_CDC_Setup+0x18a>
800f79a: a201 add r2, pc, #4 @ (adr r2, 800f7a0 <USBD_CDC_Setup+0xec>)
800f79c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800f7a0: 0800f7d1 .word 0x0800f7d1
800f7a4: 0800f84d .word 0x0800f84d
800f7a8: 0800f83f .word 0x0800f83f
800f7ac: 0800f83f .word 0x0800f83f
800f7b0: 0800f83f .word 0x0800f83f
800f7b4: 0800f83f .word 0x0800f83f
800f7b8: 0800f83f .word 0x0800f83f
800f7bc: 0800f83f .word 0x0800f83f
800f7c0: 0800f83f .word 0x0800f83f
800f7c4: 0800f83f .word 0x0800f83f
800f7c8: 0800f7fb .word 0x0800f7fb
800f7cc: 0800f825 .word 0x0800f825
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800f7d0: 687b ldr r3, [r7, #4]
800f7d2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800f7d6: b2db uxtb r3, r3
800f7d8: 2b03 cmp r3, #3
800f7da: d107 bne.n 800f7ec <USBD_CDC_Setup+0x138>
{
(void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U);
800f7dc: f107 030a add.w r3, r7, #10
800f7e0: 2202 movs r2, #2
800f7e2: 4619 mov r1, r3
800f7e4: 6878 ldr r0, [r7, #4]
800f7e6: f001 fceb bl 80111c0 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
800f7ea: e032 b.n 800f852 <USBD_CDC_Setup+0x19e>
USBD_CtlError(pdev, req);
800f7ec: 6839 ldr r1, [r7, #0]
800f7ee: 6878 ldr r0, [r7, #4]
800f7f0: f001 fc69 bl 80110c6 <USBD_CtlError>
ret = USBD_FAIL;
800f7f4: 2303 movs r3, #3
800f7f6: 75fb strb r3, [r7, #23]
break;
800f7f8: e02b b.n 800f852 <USBD_CDC_Setup+0x19e>
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
800f7fa: 687b ldr r3, [r7, #4]
800f7fc: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800f800: b2db uxtb r3, r3
800f802: 2b03 cmp r3, #3
800f804: d107 bne.n 800f816 <USBD_CDC_Setup+0x162>
{
(void)USBD_CtlSendData(pdev, &ifalt, 1U);
800f806: f107 030d add.w r3, r7, #13
800f80a: 2201 movs r2, #1
800f80c: 4619 mov r1, r3
800f80e: 6878 ldr r0, [r7, #4]
800f810: f001 fcd6 bl 80111c0 <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
800f814: e01d b.n 800f852 <USBD_CDC_Setup+0x19e>
USBD_CtlError(pdev, req);
800f816: 6839 ldr r1, [r7, #0]
800f818: 6878 ldr r0, [r7, #4]
800f81a: f001 fc54 bl 80110c6 <USBD_CtlError>
ret = USBD_FAIL;
800f81e: 2303 movs r3, #3
800f820: 75fb strb r3, [r7, #23]
break;
800f822: e016 b.n 800f852 <USBD_CDC_Setup+0x19e>
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state != USBD_STATE_CONFIGURED)
800f824: 687b ldr r3, [r7, #4]
800f826: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
800f82a: b2db uxtb r3, r3
800f82c: 2b03 cmp r3, #3
800f82e: d00f beq.n 800f850 <USBD_CDC_Setup+0x19c>
{
USBD_CtlError(pdev, req);
800f830: 6839 ldr r1, [r7, #0]
800f832: 6878 ldr r0, [r7, #4]
800f834: f001 fc47 bl 80110c6 <USBD_CtlError>
ret = USBD_FAIL;
800f838: 2303 movs r3, #3
800f83a: 75fb strb r3, [r7, #23]
}
break;
800f83c: e008 b.n 800f850 <USBD_CDC_Setup+0x19c>
case USB_REQ_CLEAR_FEATURE:
break;
default:
USBD_CtlError(pdev, req);
800f83e: 6839 ldr r1, [r7, #0]
800f840: 6878 ldr r0, [r7, #4]
800f842: f001 fc40 bl 80110c6 <USBD_CtlError>
ret = USBD_FAIL;
800f846: 2303 movs r3, #3
800f848: 75fb strb r3, [r7, #23]
break;
800f84a: e002 b.n 800f852 <USBD_CDC_Setup+0x19e>
break;
800f84c: bf00 nop
800f84e: e008 b.n 800f862 <USBD_CDC_Setup+0x1ae>
break;
800f850: bf00 nop
}
break;
800f852: e006 b.n 800f862 <USBD_CDC_Setup+0x1ae>
default:
USBD_CtlError(pdev, req);
800f854: 6839 ldr r1, [r7, #0]
800f856: 6878 ldr r0, [r7, #4]
800f858: f001 fc35 bl 80110c6 <USBD_CtlError>
ret = USBD_FAIL;
800f85c: 2303 movs r3, #3
800f85e: 75fb strb r3, [r7, #23]
break;
800f860: bf00 nop
}
return (uint8_t)ret;
800f862: 7dfb ldrb r3, [r7, #23]
}
800f864: 4618 mov r0, r3
800f866: 3718 adds r7, #24
800f868: 46bd mov sp, r7
800f86a: bd80 pop {r7, pc}
0800f86c <USBD_CDC_DataIn>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
800f86c: b580 push {r7, lr}
800f86e: b084 sub sp, #16
800f870: af00 add r7, sp, #0
800f872: 6078 str r0, [r7, #4]
800f874: 460b mov r3, r1
800f876: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc;
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef *)pdev->pData;
800f878: 687b ldr r3, [r7, #4]
800f87a: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
800f87e: 60fb str r3, [r7, #12]
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
800f880: 687b ldr r3, [r7, #4]
800f882: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f886: 687b ldr r3, [r7, #4]
800f888: 32b0 adds r2, #176 @ 0xb0
800f88a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800f88e: 2b00 cmp r3, #0
800f890: d101 bne.n 800f896 <USBD_CDC_DataIn+0x2a>
{
return (uint8_t)USBD_FAIL;
800f892: 2303 movs r3, #3
800f894: e065 b.n 800f962 <USBD_CDC_DataIn+0xf6>
}
hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
800f896: 687b ldr r3, [r7, #4]
800f898: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f89c: 687b ldr r3, [r7, #4]
800f89e: 32b0 adds r2, #176 @ 0xb0
800f8a0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800f8a4: 60bb str r3, [r7, #8]
if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) &&
800f8a6: 78fb ldrb r3, [r7, #3]
800f8a8: f003 020f and.w r2, r3, #15
800f8ac: 6879 ldr r1, [r7, #4]
800f8ae: 4613 mov r3, r2
800f8b0: 009b lsls r3, r3, #2
800f8b2: 4413 add r3, r2
800f8b4: 009b lsls r3, r3, #2
800f8b6: 440b add r3, r1
800f8b8: 3314 adds r3, #20
800f8ba: 681b ldr r3, [r3, #0]
800f8bc: 2b00 cmp r3, #0
800f8be: d02f beq.n 800f920 <USBD_CDC_DataIn+0xb4>
((pdev->ep_in[epnum & 0xFU].total_length % hpcd->IN_ep[epnum & 0xFU].maxpacket) == 0U))
800f8c0: 78fb ldrb r3, [r7, #3]
800f8c2: f003 020f and.w r2, r3, #15
800f8c6: 6879 ldr r1, [r7, #4]
800f8c8: 4613 mov r3, r2
800f8ca: 009b lsls r3, r3, #2
800f8cc: 4413 add r3, r2
800f8ce: 009b lsls r3, r3, #2
800f8d0: 440b add r3, r1
800f8d2: 3314 adds r3, #20
800f8d4: 681a ldr r2, [r3, #0]
800f8d6: 78fb ldrb r3, [r7, #3]
800f8d8: f003 010f and.w r1, r3, #15
800f8dc: 68f8 ldr r0, [r7, #12]
800f8de: 460b mov r3, r1
800f8e0: 009b lsls r3, r3, #2
800f8e2: 440b add r3, r1
800f8e4: 00db lsls r3, r3, #3
800f8e6: 4403 add r3, r0
800f8e8: 3320 adds r3, #32
800f8ea: 681b ldr r3, [r3, #0]
800f8ec: fbb2 f1f3 udiv r1, r2, r3
800f8f0: fb01 f303 mul.w r3, r1, r3
800f8f4: 1ad3 subs r3, r2, r3
if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) &&
800f8f6: 2b00 cmp r3, #0
800f8f8: d112 bne.n 800f920 <USBD_CDC_DataIn+0xb4>
{
/* Update the packet total length */
pdev->ep_in[epnum & 0xFU].total_length = 0U;
800f8fa: 78fb ldrb r3, [r7, #3]
800f8fc: f003 020f and.w r2, r3, #15
800f900: 6879 ldr r1, [r7, #4]
800f902: 4613 mov r3, r2
800f904: 009b lsls r3, r3, #2
800f906: 4413 add r3, r2
800f908: 009b lsls r3, r3, #2
800f90a: 440b add r3, r1
800f90c: 3314 adds r3, #20
800f90e: 2200 movs r2, #0
800f910: 601a str r2, [r3, #0]
/* Send ZLP */
(void)USBD_LL_Transmit(pdev, epnum, NULL, 0U);
800f912: 78f9 ldrb r1, [r7, #3]
800f914: 2300 movs r3, #0
800f916: 2200 movs r2, #0
800f918: 6878 ldr r0, [r7, #4]
800f91a: f007 feb0 bl 801767e <USBD_LL_Transmit>
800f91e: e01f b.n 800f960 <USBD_CDC_DataIn+0xf4>
}
else
{
hcdc->TxState = 0U;
800f920: 68bb ldr r3, [r7, #8]
800f922: 2200 movs r2, #0
800f924: f8c3 2214 str.w r2, [r3, #532] @ 0x214
if (((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt != NULL)
800f928: 687b ldr r3, [r7, #4]
800f92a: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800f92e: 687a ldr r2, [r7, #4]
800f930: 33b0 adds r3, #176 @ 0xb0
800f932: 009b lsls r3, r3, #2
800f934: 4413 add r3, r2
800f936: 685b ldr r3, [r3, #4]
800f938: 691b ldr r3, [r3, #16]
800f93a: 2b00 cmp r3, #0
800f93c: d010 beq.n 800f960 <USBD_CDC_DataIn+0xf4>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum);
800f93e: 687b ldr r3, [r7, #4]
800f940: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800f944: 687a ldr r2, [r7, #4]
800f946: 33b0 adds r3, #176 @ 0xb0
800f948: 009b lsls r3, r3, #2
800f94a: 4413 add r3, r2
800f94c: 685b ldr r3, [r3, #4]
800f94e: 691b ldr r3, [r3, #16]
800f950: 68ba ldr r2, [r7, #8]
800f952: f8d2 0208 ldr.w r0, [r2, #520] @ 0x208
800f956: 68ba ldr r2, [r7, #8]
800f958: f502 7104 add.w r1, r2, #528 @ 0x210
800f95c: 78fa ldrb r2, [r7, #3]
800f95e: 4798 blx r3
}
}
return (uint8_t)USBD_OK;
800f960: 2300 movs r3, #0
}
800f962: 4618 mov r0, r3
800f964: 3710 adds r7, #16
800f966: 46bd mov sp, r7
800f968: bd80 pop {r7, pc}
0800f96a <USBD_CDC_DataOut>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
800f96a: b580 push {r7, lr}
800f96c: b084 sub sp, #16
800f96e: af00 add r7, sp, #0
800f970: 6078 str r0, [r7, #4]
800f972: 460b mov r3, r1
800f974: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
800f976: 687b ldr r3, [r7, #4]
800f978: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f97c: 687b ldr r3, [r7, #4]
800f97e: 32b0 adds r2, #176 @ 0xb0
800f980: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800f984: 60fb str r3, [r7, #12]
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
800f986: 687b ldr r3, [r7, #4]
800f988: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f98c: 687b ldr r3, [r7, #4]
800f98e: 32b0 adds r2, #176 @ 0xb0
800f990: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800f994: 2b00 cmp r3, #0
800f996: d101 bne.n 800f99c <USBD_CDC_DataOut+0x32>
{
return (uint8_t)USBD_FAIL;
800f998: 2303 movs r3, #3
800f99a: e01a b.n 800f9d2 <USBD_CDC_DataOut+0x68>
}
/* Get the received data length */
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
800f99c: 78fb ldrb r3, [r7, #3]
800f99e: 4619 mov r1, r3
800f9a0: 6878 ldr r0, [r7, #4]
800f9a2: f007 feae bl 8017702 <USBD_LL_GetRxDataSize>
800f9a6: 4602 mov r2, r0
800f9a8: 68fb ldr r3, [r7, #12]
800f9aa: f8c3 220c str.w r2, [r3, #524] @ 0x20c
/* USB data will be immediately processed, this allow next USB traffic being
NAKed till the end of the application Xfer */
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Receive(hcdc->RxBuffer, &hcdc->RxLength);
800f9ae: 687b ldr r3, [r7, #4]
800f9b0: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800f9b4: 687a ldr r2, [r7, #4]
800f9b6: 33b0 adds r3, #176 @ 0xb0
800f9b8: 009b lsls r3, r3, #2
800f9ba: 4413 add r3, r2
800f9bc: 685b ldr r3, [r3, #4]
800f9be: 68db ldr r3, [r3, #12]
800f9c0: 68fa ldr r2, [r7, #12]
800f9c2: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204
800f9c6: 68fa ldr r2, [r7, #12]
800f9c8: f502 7203 add.w r2, r2, #524 @ 0x20c
800f9cc: 4611 mov r1, r2
800f9ce: 4798 blx r3
return (uint8_t)USBD_OK;
800f9d0: 2300 movs r3, #0
}
800f9d2: 4618 mov r0, r3
800f9d4: 3710 adds r7, #16
800f9d6: 46bd mov sp, r7
800f9d8: bd80 pop {r7, pc}
0800f9da <USBD_CDC_EP0_RxReady>:
* Handle EP0 Rx Ready event
* @param pdev: device instance
* @retval status
*/
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
800f9da: b580 push {r7, lr}
800f9dc: b084 sub sp, #16
800f9de: af00 add r7, sp, #0
800f9e0: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
800f9e2: 687b ldr r3, [r7, #4]
800f9e4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800f9e8: 687b ldr r3, [r7, #4]
800f9ea: 32b0 adds r2, #176 @ 0xb0
800f9ec: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800f9f0: 60fb str r3, [r7, #12]
if (hcdc == NULL)
800f9f2: 68fb ldr r3, [r7, #12]
800f9f4: 2b00 cmp r3, #0
800f9f6: d101 bne.n 800f9fc <USBD_CDC_EP0_RxReady+0x22>
{
return (uint8_t)USBD_FAIL;
800f9f8: 2303 movs r3, #3
800f9fa: e024 b.n 800fa46 <USBD_CDC_EP0_RxReady+0x6c>
}
if ((pdev->pUserData[pdev->classId] != NULL) && (hcdc->CmdOpCode != 0xFFU))
800f9fc: 687b ldr r3, [r7, #4]
800f9fe: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800fa02: 687a ldr r2, [r7, #4]
800fa04: 33b0 adds r3, #176 @ 0xb0
800fa06: 009b lsls r3, r3, #2
800fa08: 4413 add r3, r2
800fa0a: 685b ldr r3, [r3, #4]
800fa0c: 2b00 cmp r3, #0
800fa0e: d019 beq.n 800fa44 <USBD_CDC_EP0_RxReady+0x6a>
800fa10: 68fb ldr r3, [r7, #12]
800fa12: f893 3200 ldrb.w r3, [r3, #512] @ 0x200
800fa16: 2bff cmp r3, #255 @ 0xff
800fa18: d014 beq.n 800fa44 <USBD_CDC_EP0_RxReady+0x6a>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode,
800fa1a: 687b ldr r3, [r7, #4]
800fa1c: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800fa20: 687a ldr r2, [r7, #4]
800fa22: 33b0 adds r3, #176 @ 0xb0
800fa24: 009b lsls r3, r3, #2
800fa26: 4413 add r3, r2
800fa28: 685b ldr r3, [r3, #4]
800fa2a: 689b ldr r3, [r3, #8]
800fa2c: 68fa ldr r2, [r7, #12]
800fa2e: f892 0200 ldrb.w r0, [r2, #512] @ 0x200
(uint8_t *)hcdc->data,
800fa32: 68f9 ldr r1, [r7, #12]
(uint16_t)hcdc->CmdLength);
800fa34: 68fa ldr r2, [r7, #12]
800fa36: f892 2201 ldrb.w r2, [r2, #513] @ 0x201
((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode,
800fa3a: 4798 blx r3
hcdc->CmdOpCode = 0xFFU;
800fa3c: 68fb ldr r3, [r7, #12]
800fa3e: 22ff movs r2, #255 @ 0xff
800fa40: f883 2200 strb.w r2, [r3, #512] @ 0x200
}
return (uint8_t)USBD_OK;
800fa44: 2300 movs r3, #0
}
800fa46: 4618 mov r0, r3
800fa48: 3710 adds r7, #16
800fa4a: 46bd mov sp, r7
800fa4c: bd80 pop {r7, pc}
...
0800fa50 <USBD_CDC_GetFSCfgDesc>:
* Return configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
{
800fa50: b580 push {r7, lr}
800fa52: b086 sub sp, #24
800fa54: af00 add r7, sp, #0
800fa56: 6078 str r0, [r7, #4]
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
800fa58: 2182 movs r1, #130 @ 0x82
800fa5a: 4818 ldr r0, [pc, #96] @ (800fabc <USBD_CDC_GetFSCfgDesc+0x6c>)
800fa5c: f000 fcd0 bl 8010400 <USBD_GetEpDesc>
800fa60: 6178 str r0, [r7, #20]
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
800fa62: 2101 movs r1, #1
800fa64: 4815 ldr r0, [pc, #84] @ (800fabc <USBD_CDC_GetFSCfgDesc+0x6c>)
800fa66: f000 fccb bl 8010400 <USBD_GetEpDesc>
800fa6a: 6138 str r0, [r7, #16]
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
800fa6c: 2181 movs r1, #129 @ 0x81
800fa6e: 4813 ldr r0, [pc, #76] @ (800fabc <USBD_CDC_GetFSCfgDesc+0x6c>)
800fa70: f000 fcc6 bl 8010400 <USBD_GetEpDesc>
800fa74: 60f8 str r0, [r7, #12]
if (pEpCmdDesc != NULL)
800fa76: 697b ldr r3, [r7, #20]
800fa78: 2b00 cmp r3, #0
800fa7a: d002 beq.n 800fa82 <USBD_CDC_GetFSCfgDesc+0x32>
{
pEpCmdDesc->bInterval = CDC_FS_BINTERVAL;
800fa7c: 697b ldr r3, [r7, #20]
800fa7e: 2210 movs r2, #16
800fa80: 719a strb r2, [r3, #6]
}
if (pEpOutDesc != NULL)
800fa82: 693b ldr r3, [r7, #16]
800fa84: 2b00 cmp r3, #0
800fa86: d006 beq.n 800fa96 <USBD_CDC_GetFSCfgDesc+0x46>
{
pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
800fa88: 693b ldr r3, [r7, #16]
800fa8a: 2200 movs r2, #0
800fa8c: f042 0240 orr.w r2, r2, #64 @ 0x40
800fa90: 711a strb r2, [r3, #4]
800fa92: 2200 movs r2, #0
800fa94: 715a strb r2, [r3, #5]
}
if (pEpInDesc != NULL)
800fa96: 68fb ldr r3, [r7, #12]
800fa98: 2b00 cmp r3, #0
800fa9a: d006 beq.n 800faaa <USBD_CDC_GetFSCfgDesc+0x5a>
{
pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
800fa9c: 68fb ldr r3, [r7, #12]
800fa9e: 2200 movs r2, #0
800faa0: f042 0240 orr.w r2, r2, #64 @ 0x40
800faa4: 711a strb r2, [r3, #4]
800faa6: 2200 movs r2, #0
800faa8: 715a strb r2, [r3, #5]
}
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
800faaa: 687b ldr r3, [r7, #4]
800faac: 2243 movs r2, #67 @ 0x43
800faae: 801a strh r2, [r3, #0]
return USBD_CDC_CfgDesc;
800fab0: 4b02 ldr r3, [pc, #8] @ (800fabc <USBD_CDC_GetFSCfgDesc+0x6c>)
}
800fab2: 4618 mov r0, r3
800fab4: 3718 adds r7, #24
800fab6: 46bd mov sp, r7
800fab8: bd80 pop {r7, pc}
800faba: bf00 nop
800fabc: 2000005c .word 0x2000005c
0800fac0 <USBD_CDC_GetHSCfgDesc>:
* Return configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
{
800fac0: b580 push {r7, lr}
800fac2: b086 sub sp, #24
800fac4: af00 add r7, sp, #0
800fac6: 6078 str r0, [r7, #4]
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
800fac8: 2182 movs r1, #130 @ 0x82
800faca: 4818 ldr r0, [pc, #96] @ (800fb2c <USBD_CDC_GetHSCfgDesc+0x6c>)
800facc: f000 fc98 bl 8010400 <USBD_GetEpDesc>
800fad0: 6178 str r0, [r7, #20]
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
800fad2: 2101 movs r1, #1
800fad4: 4815 ldr r0, [pc, #84] @ (800fb2c <USBD_CDC_GetHSCfgDesc+0x6c>)
800fad6: f000 fc93 bl 8010400 <USBD_GetEpDesc>
800fada: 6138 str r0, [r7, #16]
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
800fadc: 2181 movs r1, #129 @ 0x81
800fade: 4813 ldr r0, [pc, #76] @ (800fb2c <USBD_CDC_GetHSCfgDesc+0x6c>)
800fae0: f000 fc8e bl 8010400 <USBD_GetEpDesc>
800fae4: 60f8 str r0, [r7, #12]
if (pEpCmdDesc != NULL)
800fae6: 697b ldr r3, [r7, #20]
800fae8: 2b00 cmp r3, #0
800faea: d002 beq.n 800faf2 <USBD_CDC_GetHSCfgDesc+0x32>
{
pEpCmdDesc->bInterval = CDC_HS_BINTERVAL;
800faec: 697b ldr r3, [r7, #20]
800faee: 2210 movs r2, #16
800faf0: 719a strb r2, [r3, #6]
}
if (pEpOutDesc != NULL)
800faf2: 693b ldr r3, [r7, #16]
800faf4: 2b00 cmp r3, #0
800faf6: d006 beq.n 800fb06 <USBD_CDC_GetHSCfgDesc+0x46>
{
pEpOutDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE;
800faf8: 693b ldr r3, [r7, #16]
800fafa: 2200 movs r2, #0
800fafc: 711a strb r2, [r3, #4]
800fafe: 2200 movs r2, #0
800fb00: f042 0202 orr.w r2, r2, #2
800fb04: 715a strb r2, [r3, #5]
}
if (pEpInDesc != NULL)
800fb06: 68fb ldr r3, [r7, #12]
800fb08: 2b00 cmp r3, #0
800fb0a: d006 beq.n 800fb1a <USBD_CDC_GetHSCfgDesc+0x5a>
{
pEpInDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE;
800fb0c: 68fb ldr r3, [r7, #12]
800fb0e: 2200 movs r2, #0
800fb10: 711a strb r2, [r3, #4]
800fb12: 2200 movs r2, #0
800fb14: f042 0202 orr.w r2, r2, #2
800fb18: 715a strb r2, [r3, #5]
}
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
800fb1a: 687b ldr r3, [r7, #4]
800fb1c: 2243 movs r2, #67 @ 0x43
800fb1e: 801a strh r2, [r3, #0]
return USBD_CDC_CfgDesc;
800fb20: 4b02 ldr r3, [pc, #8] @ (800fb2c <USBD_CDC_GetHSCfgDesc+0x6c>)
}
800fb22: 4618 mov r0, r3
800fb24: 3718 adds r7, #24
800fb26: 46bd mov sp, r7
800fb28: bd80 pop {r7, pc}
800fb2a: bf00 nop
800fb2c: 2000005c .word 0x2000005c
0800fb30 <USBD_CDC_GetOtherSpeedCfgDesc>:
* Return configuration descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
{
800fb30: b580 push {r7, lr}
800fb32: b086 sub sp, #24
800fb34: af00 add r7, sp, #0
800fb36: 6078 str r0, [r7, #4]
USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP);
800fb38: 2182 movs r1, #130 @ 0x82
800fb3a: 4818 ldr r0, [pc, #96] @ (800fb9c <USBD_CDC_GetOtherSpeedCfgDesc+0x6c>)
800fb3c: f000 fc60 bl 8010400 <USBD_GetEpDesc>
800fb40: 6178 str r0, [r7, #20]
USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP);
800fb42: 2101 movs r1, #1
800fb44: 4815 ldr r0, [pc, #84] @ (800fb9c <USBD_CDC_GetOtherSpeedCfgDesc+0x6c>)
800fb46: f000 fc5b bl 8010400 <USBD_GetEpDesc>
800fb4a: 6138 str r0, [r7, #16]
USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP);
800fb4c: 2181 movs r1, #129 @ 0x81
800fb4e: 4813 ldr r0, [pc, #76] @ (800fb9c <USBD_CDC_GetOtherSpeedCfgDesc+0x6c>)
800fb50: f000 fc56 bl 8010400 <USBD_GetEpDesc>
800fb54: 60f8 str r0, [r7, #12]
if (pEpCmdDesc != NULL)
800fb56: 697b ldr r3, [r7, #20]
800fb58: 2b00 cmp r3, #0
800fb5a: d002 beq.n 800fb62 <USBD_CDC_GetOtherSpeedCfgDesc+0x32>
{
pEpCmdDesc->bInterval = CDC_FS_BINTERVAL;
800fb5c: 697b ldr r3, [r7, #20]
800fb5e: 2210 movs r2, #16
800fb60: 719a strb r2, [r3, #6]
}
if (pEpOutDesc != NULL)
800fb62: 693b ldr r3, [r7, #16]
800fb64: 2b00 cmp r3, #0
800fb66: d006 beq.n 800fb76 <USBD_CDC_GetOtherSpeedCfgDesc+0x46>
{
pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
800fb68: 693b ldr r3, [r7, #16]
800fb6a: 2200 movs r2, #0
800fb6c: f042 0240 orr.w r2, r2, #64 @ 0x40
800fb70: 711a strb r2, [r3, #4]
800fb72: 2200 movs r2, #0
800fb74: 715a strb r2, [r3, #5]
}
if (pEpInDesc != NULL)
800fb76: 68fb ldr r3, [r7, #12]
800fb78: 2b00 cmp r3, #0
800fb7a: d006 beq.n 800fb8a <USBD_CDC_GetOtherSpeedCfgDesc+0x5a>
{
pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE;
800fb7c: 68fb ldr r3, [r7, #12]
800fb7e: 2200 movs r2, #0
800fb80: f042 0240 orr.w r2, r2, #64 @ 0x40
800fb84: 711a strb r2, [r3, #4]
800fb86: 2200 movs r2, #0
800fb88: 715a strb r2, [r3, #5]
}
*length = (uint16_t)sizeof(USBD_CDC_CfgDesc);
800fb8a: 687b ldr r3, [r7, #4]
800fb8c: 2243 movs r2, #67 @ 0x43
800fb8e: 801a strh r2, [r3, #0]
return USBD_CDC_CfgDesc;
800fb90: 4b02 ldr r3, [pc, #8] @ (800fb9c <USBD_CDC_GetOtherSpeedCfgDesc+0x6c>)
}
800fb92: 4618 mov r0, r3
800fb94: 3718 adds r7, #24
800fb96: 46bd mov sp, r7
800fb98: bd80 pop {r7, pc}
800fb9a: bf00 nop
800fb9c: 2000005c .word 0x2000005c
0800fba0 <USBD_CDC_GetDeviceQualifierDescriptor>:
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
{
800fba0: b480 push {r7}
800fba2: b083 sub sp, #12
800fba4: af00 add r7, sp, #0
800fba6: 6078 str r0, [r7, #4]
*length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc);
800fba8: 687b ldr r3, [r7, #4]
800fbaa: 220a movs r2, #10
800fbac: 801a strh r2, [r3, #0]
return USBD_CDC_DeviceQualifierDesc;
800fbae: 4b03 ldr r3, [pc, #12] @ (800fbbc <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
}
800fbb0: 4618 mov r0, r3
800fbb2: 370c adds r7, #12
800fbb4: 46bd mov sp, r7
800fbb6: f85d 7b04 ldr.w r7, [sp], #4
800fbba: 4770 bx lr
800fbbc: 20000018 .word 0x20000018
0800fbc0 <USBD_CDC_RegisterInterface>:
* @param fops: CD Interface callback
* @retval status
*/
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CDC_ItfTypeDef *fops)
{
800fbc0: b480 push {r7}
800fbc2: b083 sub sp, #12
800fbc4: af00 add r7, sp, #0
800fbc6: 6078 str r0, [r7, #4]
800fbc8: 6039 str r1, [r7, #0]
if (fops == NULL)
800fbca: 683b ldr r3, [r7, #0]
800fbcc: 2b00 cmp r3, #0
800fbce: d101 bne.n 800fbd4 <USBD_CDC_RegisterInterface+0x14>
{
return (uint8_t)USBD_FAIL;
800fbd0: 2303 movs r3, #3
800fbd2: e009 b.n 800fbe8 <USBD_CDC_RegisterInterface+0x28>
}
pdev->pUserData[pdev->classId] = fops;
800fbd4: 687b ldr r3, [r7, #4]
800fbd6: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4
800fbda: 687a ldr r2, [r7, #4]
800fbdc: 33b0 adds r3, #176 @ 0xb0
800fbde: 009b lsls r3, r3, #2
800fbe0: 4413 add r3, r2
800fbe2: 683a ldr r2, [r7, #0]
800fbe4: 605a str r2, [r3, #4]
return (uint8_t)USBD_OK;
800fbe6: 2300 movs r3, #0
}
800fbe8: 4618 mov r0, r3
800fbea: 370c adds r7, #12
800fbec: 46bd mov sp, r7
800fbee: f85d 7b04 ldr.w r7, [sp], #4
800fbf2: 4770 bx lr
0800fbf4 <USBD_CDC_SetTxBuffer>:
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
#else
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff, uint32_t length)
{
800fbf4: b480 push {r7}
800fbf6: b087 sub sp, #28
800fbf8: af00 add r7, sp, #0
800fbfa: 60f8 str r0, [r7, #12]
800fbfc: 60b9 str r1, [r7, #8]
800fbfe: 607a str r2, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
800fc00: 68fb ldr r3, [r7, #12]
800fc02: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800fc06: 68fb ldr r3, [r7, #12]
800fc08: 32b0 adds r2, #176 @ 0xb0
800fc0a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800fc0e: 617b str r3, [r7, #20]
#endif /* USE_USBD_COMPOSITE */
if (hcdc == NULL)
800fc10: 697b ldr r3, [r7, #20]
800fc12: 2b00 cmp r3, #0
800fc14: d101 bne.n 800fc1a <USBD_CDC_SetTxBuffer+0x26>
{
return (uint8_t)USBD_FAIL;
800fc16: 2303 movs r3, #3
800fc18: e008 b.n 800fc2c <USBD_CDC_SetTxBuffer+0x38>
}
hcdc->TxBuffer = pbuff;
800fc1a: 697b ldr r3, [r7, #20]
800fc1c: 68ba ldr r2, [r7, #8]
800fc1e: f8c3 2208 str.w r2, [r3, #520] @ 0x208
hcdc->TxLength = length;
800fc22: 697b ldr r3, [r7, #20]
800fc24: 687a ldr r2, [r7, #4]
800fc26: f8c3 2210 str.w r2, [r3, #528] @ 0x210
return (uint8_t)USBD_OK;
800fc2a: 2300 movs r3, #0
}
800fc2c: 4618 mov r0, r3
800fc2e: 371c adds r7, #28
800fc30: 46bd mov sp, r7
800fc32: f85d 7b04 ldr.w r7, [sp], #4
800fc36: 4770 bx lr
0800fc38 <USBD_CDC_SetRxBuffer>:
* @param pdev: device instance
* @param pbuff: Rx Buffer
* @retval status
*/
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff)
{
800fc38: b480 push {r7}
800fc3a: b085 sub sp, #20
800fc3c: af00 add r7, sp, #0
800fc3e: 6078 str r0, [r7, #4]
800fc40: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
800fc42: 687b ldr r3, [r7, #4]
800fc44: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800fc48: 687b ldr r3, [r7, #4]
800fc4a: 32b0 adds r2, #176 @ 0xb0
800fc4c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800fc50: 60fb str r3, [r7, #12]
if (hcdc == NULL)
800fc52: 68fb ldr r3, [r7, #12]
800fc54: 2b00 cmp r3, #0
800fc56: d101 bne.n 800fc5c <USBD_CDC_SetRxBuffer+0x24>
{
return (uint8_t)USBD_FAIL;
800fc58: 2303 movs r3, #3
800fc5a: e004 b.n 800fc66 <USBD_CDC_SetRxBuffer+0x2e>
}
hcdc->RxBuffer = pbuff;
800fc5c: 68fb ldr r3, [r7, #12]
800fc5e: 683a ldr r2, [r7, #0]
800fc60: f8c3 2204 str.w r2, [r3, #516] @ 0x204
return (uint8_t)USBD_OK;
800fc64: 2300 movs r3, #0
}
800fc66: 4618 mov r0, r3
800fc68: 3714 adds r7, #20
800fc6a: 46bd mov sp, r7
800fc6c: f85d 7b04 ldr.w r7, [sp], #4
800fc70: 4770 bx lr
...
0800fc74 <USBD_CDC_TransmitPacket>:
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t ClassId)
{
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId];
#else
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
{
800fc74: b580 push {r7, lr}
800fc76: b084 sub sp, #16
800fc78: af00 add r7, sp, #0
800fc7a: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
800fc7c: 687b ldr r3, [r7, #4]
800fc7e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800fc82: 687b ldr r3, [r7, #4]
800fc84: 32b0 adds r2, #176 @ 0xb0
800fc86: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800fc8a: 60bb str r3, [r7, #8]
#endif /* USE_USBD_COMPOSITE */
USBD_StatusTypeDef ret = USBD_BUSY;
800fc8c: 2301 movs r3, #1
800fc8e: 73fb strb r3, [r7, #15]
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, ClassId);
#endif /* USE_USBD_COMPOSITE */
if (hcdc == NULL)
800fc90: 68bb ldr r3, [r7, #8]
800fc92: 2b00 cmp r3, #0
800fc94: d101 bne.n 800fc9a <USBD_CDC_TransmitPacket+0x26>
{
return (uint8_t)USBD_FAIL;
800fc96: 2303 movs r3, #3
800fc98: e025 b.n 800fce6 <USBD_CDC_TransmitPacket+0x72>
}
if (hcdc->TxState == 0U)
800fc9a: 68bb ldr r3, [r7, #8]
800fc9c: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
800fca0: 2b00 cmp r3, #0
800fca2: d11f bne.n 800fce4 <USBD_CDC_TransmitPacket+0x70>
{
/* Tx Transfer in progress */
hcdc->TxState = 1U;
800fca4: 68bb ldr r3, [r7, #8]
800fca6: 2201 movs r2, #1
800fca8: f8c3 2214 str.w r2, [r3, #532] @ 0x214
/* Update the packet total length */
pdev->ep_in[CDCInEpAdd & 0xFU].total_length = hcdc->TxLength;
800fcac: 4b10 ldr r3, [pc, #64] @ (800fcf0 <USBD_CDC_TransmitPacket+0x7c>)
800fcae: 781b ldrb r3, [r3, #0]
800fcb0: f003 020f and.w r2, r3, #15
800fcb4: 68bb ldr r3, [r7, #8]
800fcb6: f8d3 1210 ldr.w r1, [r3, #528] @ 0x210
800fcba: 6878 ldr r0, [r7, #4]
800fcbc: 4613 mov r3, r2
800fcbe: 009b lsls r3, r3, #2
800fcc0: 4413 add r3, r2
800fcc2: 009b lsls r3, r3, #2
800fcc4: 4403 add r3, r0
800fcc6: 3314 adds r3, #20
800fcc8: 6019 str r1, [r3, #0]
/* Transmit next packet */
(void)USBD_LL_Transmit(pdev, CDCInEpAdd, hcdc->TxBuffer, hcdc->TxLength);
800fcca: 4b09 ldr r3, [pc, #36] @ (800fcf0 <USBD_CDC_TransmitPacket+0x7c>)
800fccc: 7819 ldrb r1, [r3, #0]
800fcce: 68bb ldr r3, [r7, #8]
800fcd0: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208
800fcd4: 68bb ldr r3, [r7, #8]
800fcd6: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210
800fcda: 6878 ldr r0, [r7, #4]
800fcdc: f007 fccf bl 801767e <USBD_LL_Transmit>
ret = USBD_OK;
800fce0: 2300 movs r3, #0
800fce2: 73fb strb r3, [r7, #15]
}
return (uint8_t)ret;
800fce4: 7bfb ldrb r3, [r7, #15]
}
800fce6: 4618 mov r0, r3
800fce8: 3710 adds r7, #16
800fcea: 46bd mov sp, r7
800fcec: bd80 pop {r7, pc}
800fcee: bf00 nop
800fcf0: 2000009f .word 0x2000009f
0800fcf4 <USBD_CDC_ReceivePacket>:
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
{
800fcf4: b580 push {r7, lr}
800fcf6: b084 sub sp, #16
800fcf8: af00 add r7, sp, #0
800fcfa: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId];
800fcfc: 687b ldr r3, [r7, #4]
800fcfe: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800fd02: 687b ldr r3, [r7, #4]
800fd04: 32b0 adds r2, #176 @ 0xb0
800fd06: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800fd0a: 60fb str r3, [r7, #12]
#ifdef USE_USBD_COMPOSITE
/* Get the Endpoints addresses allocated for this class instance */
CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId);
#endif /* USE_USBD_COMPOSITE */
if (pdev->pClassDataCmsit[pdev->classId] == NULL)
800fd0c: 687b ldr r3, [r7, #4]
800fd0e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800fd12: 687b ldr r3, [r7, #4]
800fd14: 32b0 adds r2, #176 @ 0xb0
800fd16: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800fd1a: 2b00 cmp r3, #0
800fd1c: d101 bne.n 800fd22 <USBD_CDC_ReceivePacket+0x2e>
{
return (uint8_t)USBD_FAIL;
800fd1e: 2303 movs r3, #3
800fd20: e018 b.n 800fd54 <USBD_CDC_ReceivePacket+0x60>
}
if (pdev->dev_speed == USBD_SPEED_HIGH)
800fd22: 687b ldr r3, [r7, #4]
800fd24: 7c1b ldrb r3, [r3, #16]
800fd26: 2b00 cmp r3, #0
800fd28: d10a bne.n 800fd40 <USBD_CDC_ReceivePacket+0x4c>
{
/* Prepare Out endpoint to receive next packet */
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
800fd2a: 4b0c ldr r3, [pc, #48] @ (800fd5c <USBD_CDC_ReceivePacket+0x68>)
800fd2c: 7819 ldrb r1, [r3, #0]
800fd2e: 68fb ldr r3, [r7, #12]
800fd30: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
800fd34: f44f 7300 mov.w r3, #512 @ 0x200
800fd38: 6878 ldr r0, [r7, #4]
800fd3a: f007 fcc1 bl 80176c0 <USBD_LL_PrepareReceive>
800fd3e: e008 b.n 800fd52 <USBD_CDC_ReceivePacket+0x5e>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
(void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer,
800fd40: 4b06 ldr r3, [pc, #24] @ (800fd5c <USBD_CDC_ReceivePacket+0x68>)
800fd42: 7819 ldrb r1, [r3, #0]
800fd44: 68fb ldr r3, [r7, #12]
800fd46: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
800fd4a: 2340 movs r3, #64 @ 0x40
800fd4c: 6878 ldr r0, [r7, #4]
800fd4e: f007 fcb7 bl 80176c0 <USBD_LL_PrepareReceive>
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return (uint8_t)USBD_OK;
800fd52: 2300 movs r3, #0
}
800fd54: 4618 mov r0, r3
800fd56: 3710 adds r7, #16
800fd58: 46bd mov sp, r7
800fd5a: bd80 pop {r7, pc}
800fd5c: 200000a0 .word 0x200000a0
0800fd60 <USBD_Init>:
* @param id: Low level core index
* @retval status: USBD Status
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
800fd60: b580 push {r7, lr}
800fd62: b086 sub sp, #24
800fd64: af00 add r7, sp, #0
800fd66: 60f8 str r0, [r7, #12]
800fd68: 60b9 str r1, [r7, #8]
800fd6a: 4613 mov r3, r2
800fd6c: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef ret;
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
800fd6e: 68fb ldr r3, [r7, #12]
800fd70: 2b00 cmp r3, #0
800fd72: d101 bne.n 800fd78 <USBD_Init+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle");
#endif /* (USBD_DEBUG_LEVEL > 1U) */
return USBD_FAIL;
800fd74: 2303 movs r3, #3
800fd76: e01f b.n 800fdb8 <USBD_Init+0x58>
pdev->NumClasses = 0;
pdev->classId = 0;
}
#else
/* Unlink previous class*/
pdev->pClass[0] = NULL;
800fd78: 68fb ldr r3, [r7, #12]
800fd7a: 2200 movs r2, #0
800fd7c: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
pdev->pUserData[0] = NULL;
800fd80: 68fb ldr r3, [r7, #12]
800fd82: 2200 movs r2, #0
800fd84: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4
#endif /* USE_USBD_COMPOSITE */
pdev->pConfDesc = NULL;
800fd88: 68fb ldr r3, [r7, #12]
800fd8a: 2200 movs r2, #0
800fd8c: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
/* Assign USBD Descriptors */
if (pdesc != NULL)
800fd90: 68bb ldr r3, [r7, #8]
800fd92: 2b00 cmp r3, #0
800fd94: d003 beq.n 800fd9e <USBD_Init+0x3e>
{
pdev->pDesc = pdesc;
800fd96: 68fb ldr r3, [r7, #12]
800fd98: 68ba ldr r2, [r7, #8]
800fd9a: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4
}
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
800fd9e: 68fb ldr r3, [r7, #12]
800fda0: 2201 movs r2, #1
800fda2: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->id = id;
800fda6: 68fb ldr r3, [r7, #12]
800fda8: 79fa ldrb r2, [r7, #7]
800fdaa: 701a strb r2, [r3, #0]
/* Initialize low level driver */
ret = USBD_LL_Init(pdev);
800fdac: 68f8 ldr r0, [r7, #12]
800fdae: f007 fb1b bl 80173e8 <USBD_LL_Init>
800fdb2: 4603 mov r3, r0
800fdb4: 75fb strb r3, [r7, #23]
return ret;
800fdb6: 7dfb ldrb r3, [r7, #23]
}
800fdb8: 4618 mov r0, r3
800fdba: 3718 adds r7, #24
800fdbc: 46bd mov sp, r7
800fdbe: bd80 pop {r7, pc}
0800fdc0 <USBD_RegisterClass>:
* @param pdev: Device Handle
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
800fdc0: b580 push {r7, lr}
800fdc2: b084 sub sp, #16
800fdc4: af00 add r7, sp, #0
800fdc6: 6078 str r0, [r7, #4]
800fdc8: 6039 str r1, [r7, #0]
uint16_t len = 0U;
800fdca: 2300 movs r3, #0
800fdcc: 81fb strh r3, [r7, #14]
if (pclass == NULL)
800fdce: 683b ldr r3, [r7, #0]
800fdd0: 2b00 cmp r3, #0
800fdd2: d101 bne.n 800fdd8 <USBD_RegisterClass+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif /* (USBD_DEBUG_LEVEL > 1U) */
return USBD_FAIL;
800fdd4: 2303 movs r3, #3
800fdd6: e025 b.n 800fe24 <USBD_RegisterClass+0x64>
}
/* link the class to the USB Device handle */
pdev->pClass[0] = pclass;
800fdd8: 687b ldr r3, [r7, #4]
800fdda: 683a ldr r2, [r7, #0]
800fddc: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8
if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL)
{
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len);
}
#else /* Default USE_USB_FS */
if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL)
800fde0: 687b ldr r3, [r7, #4]
800fde2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800fde6: 687b ldr r3, [r7, #4]
800fde8: 32ae adds r2, #174 @ 0xae
800fdea: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800fdee: 6adb ldr r3, [r3, #44] @ 0x2c
800fdf0: 2b00 cmp r3, #0
800fdf2: d00f beq.n 800fe14 <USBD_RegisterClass+0x54>
{
pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len);
800fdf4: 687b ldr r3, [r7, #4]
800fdf6: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
800fdfa: 687b ldr r3, [r7, #4]
800fdfc: 32ae adds r2, #174 @ 0xae
800fdfe: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800fe02: 6adb ldr r3, [r3, #44] @ 0x2c
800fe04: f107 020e add.w r2, r7, #14
800fe08: 4610 mov r0, r2
800fe0a: 4798 blx r3
800fe0c: 4602 mov r2, r0
800fe0e: 687b ldr r3, [r7, #4]
800fe10: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0
}
#endif /* USE_USB_FS */
/* Increment the NumClasses */
pdev->NumClasses++;
800fe14: 687b ldr r3, [r7, #4]
800fe16: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
800fe1a: 1c5a adds r2, r3, #1
800fe1c: 687b ldr r3, [r7, #4]
800fe1e: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8
return USBD_OK;
800fe22: 2300 movs r3, #0
}
800fe24: 4618 mov r0, r3
800fe26: 3710 adds r7, #16
800fe28: 46bd mov sp, r7
800fe2a: bd80 pop {r7, pc}
0800fe2c <USBD_Start>:
* Start the USB Device Core.
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
800fe2c: b580 push {r7, lr}
800fe2e: b082 sub sp, #8
800fe30: af00 add r7, sp, #0
800fe32: 6078 str r0, [r7, #4]
#ifdef USE_USBD_COMPOSITE
pdev->classId = 0U;
#endif /* USE_USBD_COMPOSITE */
/* Start the low level driver */
return USBD_LL_Start(pdev);
800fe34: 6878 ldr r0, [r7, #4]
800fe36: f007 fb39 bl 80174ac <USBD_LL_Start>
800fe3a: 4603 mov r3, r0
}
800fe3c: 4618 mov r0, r3
800fe3e: 3708 adds r7, #8
800fe40: 46bd mov sp, r7
800fe42: bd80 pop {r7, pc}
0800fe44 <USBD_RunTestMode>:
* Launch test mode process
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
800fe44: b480 push {r7}
800fe46: b083 sub sp, #12
800fe48: af00 add r7, sp, #0
800fe4a: 6078 str r0, [r7, #4]
return ret;
#else
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
800fe4c: 2300 movs r3, #0
#endif /* USBD_HS_TESTMODE_ENABLE */
}
800fe4e: 4618 mov r0, r3
800fe50: 370c adds r7, #12
800fe52: 46bd mov sp, r7
800fe54: f85d 7b04 ldr.w r7, [sp], #4
800fe58: 4770 bx lr
0800fe5a <USBD_SetClassConfig>:
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800fe5a: b580 push {r7, lr}
800fe5c: b084 sub sp, #16
800fe5e: af00 add r7, sp, #0
800fe60: 6078 str r0, [r7, #4]
800fe62: 460b mov r3, r1
800fe64: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_OK;
800fe66: 2300 movs r3, #0
800fe68: 73fb strb r3, [r7, #15]
}
}
}
}
#else
if (pdev->pClass[0] != NULL)
800fe6a: 687b ldr r3, [r7, #4]
800fe6c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800fe70: 2b00 cmp r3, #0
800fe72: d009 beq.n 800fe88 <USBD_SetClassConfig+0x2e>
{
/* Set configuration and Start the Class */
ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx);
800fe74: 687b ldr r3, [r7, #4]
800fe76: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800fe7a: 681b ldr r3, [r3, #0]
800fe7c: 78fa ldrb r2, [r7, #3]
800fe7e: 4611 mov r1, r2
800fe80: 6878 ldr r0, [r7, #4]
800fe82: 4798 blx r3
800fe84: 4603 mov r3, r0
800fe86: 73fb strb r3, [r7, #15]
}
#endif /* USE_USBD_COMPOSITE */
return ret;
800fe88: 7bfb ldrb r3, [r7, #15]
}
800fe8a: 4618 mov r0, r3
800fe8c: 3710 adds r7, #16
800fe8e: 46bd mov sp, r7
800fe90: bd80 pop {r7, pc}
0800fe92 <USBD_ClrClassConfig>:
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800fe92: b580 push {r7, lr}
800fe94: b084 sub sp, #16
800fe96: af00 add r7, sp, #0
800fe98: 6078 str r0, [r7, #4]
800fe9a: 460b mov r3, r1
800fe9c: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_OK;
800fe9e: 2300 movs r3, #0
800fea0: 73fb strb r3, [r7, #15]
}
}
}
#else
/* Clear configuration and De-initialize the Class process */
if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U)
800fea2: 687b ldr r3, [r7, #4]
800fea4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
800fea8: 685b ldr r3, [r3, #4]
800feaa: 78fa ldrb r2, [r7, #3]
800feac: 4611 mov r1, r2
800feae: 6878 ldr r0, [r7, #4]
800feb0: 4798 blx r3
800feb2: 4603 mov r3, r0
800feb4: 2b00 cmp r3, #0
800feb6: d001 beq.n 800febc <USBD_ClrClassConfig+0x2a>
{
ret = USBD_FAIL;
800feb8: 2303 movs r3, #3
800feba: 73fb strb r3, [r7, #15]
}
#endif /* USE_USBD_COMPOSITE */
return ret;
800febc: 7bfb ldrb r3, [r7, #15]
}
800febe: 4618 mov r0, r3
800fec0: 3710 adds r7, #16
800fec2: 46bd mov sp, r7
800fec4: bd80 pop {r7, pc}
0800fec6 <USBD_LL_SetupStage>:
* @param pdev: device instance
* @param psetup: setup packet buffer pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
800fec6: b580 push {r7, lr}
800fec8: b084 sub sp, #16
800feca: af00 add r7, sp, #0
800fecc: 6078 str r0, [r7, #4]
800fece: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret;
USBD_ParseSetupRequest(&pdev->request, psetup);
800fed0: 687b ldr r3, [r7, #4]
800fed2: f203 23aa addw r3, r3, #682 @ 0x2aa
800fed6: 6839 ldr r1, [r7, #0]
800fed8: 4618 mov r0, r3
800feda: f001 f8ba bl 8011052 <USBD_ParseSetupRequest>
pdev->ep0_state = USBD_EP0_SETUP;
800fede: 687b ldr r3, [r7, #4]
800fee0: 2201 movs r2, #1
800fee2: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep0_data_len = pdev->request.wLength;
800fee6: 687b ldr r3, [r7, #4]
800fee8: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0
800feec: 461a mov r2, r3
800feee: 687b ldr r3, [r7, #4]
800fef0: f8c3 2298 str.w r2, [r3, #664] @ 0x298
switch (pdev->request.bmRequest & 0x1FU)
800fef4: 687b ldr r3, [r7, #4]
800fef6: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
800fefa: f003 031f and.w r3, r3, #31
800fefe: 2b02 cmp r3, #2
800ff00: d01a beq.n 800ff38 <USBD_LL_SetupStage+0x72>
800ff02: 2b02 cmp r3, #2
800ff04: d822 bhi.n 800ff4c <USBD_LL_SetupStage+0x86>
800ff06: 2b00 cmp r3, #0
800ff08: d002 beq.n 800ff10 <USBD_LL_SetupStage+0x4a>
800ff0a: 2b01 cmp r3, #1
800ff0c: d00a beq.n 800ff24 <USBD_LL_SetupStage+0x5e>
800ff0e: e01d b.n 800ff4c <USBD_LL_SetupStage+0x86>
{
case USB_REQ_RECIPIENT_DEVICE:
ret = USBD_StdDevReq(pdev, &pdev->request);
800ff10: 687b ldr r3, [r7, #4]
800ff12: f203 23aa addw r3, r3, #682 @ 0x2aa
800ff16: 4619 mov r1, r3
800ff18: 6878 ldr r0, [r7, #4]
800ff1a: f000 fae5 bl 80104e8 <USBD_StdDevReq>
800ff1e: 4603 mov r3, r0
800ff20: 73fb strb r3, [r7, #15]
break;
800ff22: e020 b.n 800ff66 <USBD_LL_SetupStage+0xa0>
case USB_REQ_RECIPIENT_INTERFACE:
ret = USBD_StdItfReq(pdev, &pdev->request);
800ff24: 687b ldr r3, [r7, #4]
800ff26: f203 23aa addw r3, r3, #682 @ 0x2aa
800ff2a: 4619 mov r1, r3
800ff2c: 6878 ldr r0, [r7, #4]
800ff2e: f000 fb4d bl 80105cc <USBD_StdItfReq>
800ff32: 4603 mov r3, r0
800ff34: 73fb strb r3, [r7, #15]
break;
800ff36: e016 b.n 800ff66 <USBD_LL_SetupStage+0xa0>
case USB_REQ_RECIPIENT_ENDPOINT:
ret = USBD_StdEPReq(pdev, &pdev->request);
800ff38: 687b ldr r3, [r7, #4]
800ff3a: f203 23aa addw r3, r3, #682 @ 0x2aa
800ff3e: 4619 mov r1, r3
800ff40: 6878 ldr r0, [r7, #4]
800ff42: f000 fbaf bl 80106a4 <USBD_StdEPReq>
800ff46: 4603 mov r3, r0
800ff48: 73fb strb r3, [r7, #15]
break;
800ff4a: e00c b.n 800ff66 <USBD_LL_SetupStage+0xa0>
default:
ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
800ff4c: 687b ldr r3, [r7, #4]
800ff4e: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
800ff52: f023 037f bic.w r3, r3, #127 @ 0x7f
800ff56: b2db uxtb r3, r3
800ff58: 4619 mov r1, r3
800ff5a: 6878 ldr r0, [r7, #4]
800ff5c: f007 fb06 bl 801756c <USBD_LL_StallEP>
800ff60: 4603 mov r3, r0
800ff62: 73fb strb r3, [r7, #15]
break;
800ff64: bf00 nop
}
return ret;
800ff66: 7bfb ldrb r3, [r7, #15]
}
800ff68: 4618 mov r0, r3
800ff6a: 3710 adds r7, #16
800ff6c: 46bd mov sp, r7
800ff6e: bd80 pop {r7, pc}
0800ff70 <USBD_LL_DataOutStage>:
* @param pdata: data pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
800ff70: b580 push {r7, lr}
800ff72: b086 sub sp, #24
800ff74: af00 add r7, sp, #0
800ff76: 60f8 str r0, [r7, #12]
800ff78: 460b mov r3, r1
800ff7a: 607a str r2, [r7, #4]
800ff7c: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
USBD_StatusTypeDef ret = USBD_OK;
800ff7e: 2300 movs r3, #0
800ff80: 75fb strb r3, [r7, #23]
uint8_t idx;
UNUSED(pdata);
if (epnum == 0U)
800ff82: 7afb ldrb r3, [r7, #11]
800ff84: 2b00 cmp r3, #0
800ff86: d177 bne.n 8010078 <USBD_LL_DataOutStage+0x108>
{
pep = &pdev->ep_out[0];
800ff88: 68fb ldr r3, [r7, #12]
800ff8a: f503 73aa add.w r3, r3, #340 @ 0x154
800ff8e: 613b str r3, [r7, #16]
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
800ff90: 68fb ldr r3, [r7, #12]
800ff92: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
800ff96: 2b03 cmp r3, #3
800ff98: f040 80a1 bne.w 80100de <USBD_LL_DataOutStage+0x16e>
{
if (pep->rem_length > pep->maxpacket)
800ff9c: 693b ldr r3, [r7, #16]
800ff9e: 685b ldr r3, [r3, #4]
800ffa0: 693a ldr r2, [r7, #16]
800ffa2: 8992 ldrh r2, [r2, #12]
800ffa4: 4293 cmp r3, r2
800ffa6: d91c bls.n 800ffe2 <USBD_LL_DataOutStage+0x72>
{
pep->rem_length -= pep->maxpacket;
800ffa8: 693b ldr r3, [r7, #16]
800ffaa: 685b ldr r3, [r3, #4]
800ffac: 693a ldr r2, [r7, #16]
800ffae: 8992 ldrh r2, [r2, #12]
800ffb0: 1a9a subs r2, r3, r2
800ffb2: 693b ldr r3, [r7, #16]
800ffb4: 605a str r2, [r3, #4]
pep->pbuffer += pep->maxpacket;
800ffb6: 693b ldr r3, [r7, #16]
800ffb8: 691b ldr r3, [r3, #16]
800ffba: 693a ldr r2, [r7, #16]
800ffbc: 8992 ldrh r2, [r2, #12]
800ffbe: 441a add r2, r3
800ffc0: 693b ldr r3, [r7, #16]
800ffc2: 611a str r2, [r3, #16]
(void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket));
800ffc4: 693b ldr r3, [r7, #16]
800ffc6: 6919 ldr r1, [r3, #16]
800ffc8: 693b ldr r3, [r7, #16]
800ffca: 899b ldrh r3, [r3, #12]
800ffcc: 461a mov r2, r3
800ffce: 693b ldr r3, [r7, #16]
800ffd0: 685b ldr r3, [r3, #4]
800ffd2: 4293 cmp r3, r2
800ffd4: bf38 it cc
800ffd6: 4613 movcc r3, r2
800ffd8: 461a mov r2, r3
800ffda: 68f8 ldr r0, [r7, #12]
800ffdc: f001 f940 bl 8011260 <USBD_CtlContinueRx>
800ffe0: e07d b.n 80100de <USBD_LL_DataOutStage+0x16e>
}
else
{
/* Find the class ID relative to the current request */
switch (pdev->request.bmRequest & 0x1FU)
800ffe2: 68fb ldr r3, [r7, #12]
800ffe4: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa
800ffe8: f003 031f and.w r3, r3, #31
800ffec: 2b02 cmp r3, #2
800ffee: d014 beq.n 801001a <USBD_LL_DataOutStage+0xaa>
800fff0: 2b02 cmp r3, #2
800fff2: d81d bhi.n 8010030 <USBD_LL_DataOutStage+0xc0>
800fff4: 2b00 cmp r3, #0
800fff6: d002 beq.n 800fffe <USBD_LL_DataOutStage+0x8e>
800fff8: 2b01 cmp r3, #1
800fffa: d003 beq.n 8010004 <USBD_LL_DataOutStage+0x94>
800fffc: e018 b.n 8010030 <USBD_LL_DataOutStage+0xc0>
{
case USB_REQ_RECIPIENT_DEVICE:
/* Device requests must be managed by the first instantiated class
(or duplicated by all classes for simplicity) */
idx = 0U;
800fffe: 2300 movs r3, #0
8010000: 75bb strb r3, [r7, #22]
break;
8010002: e018 b.n 8010036 <USBD_LL_DataOutStage+0xc6>
case USB_REQ_RECIPIENT_INTERFACE:
idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex));
8010004: 68fb ldr r3, [r7, #12]
8010006: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
801000a: b2db uxtb r3, r3
801000c: 4619 mov r1, r3
801000e: 68f8 ldr r0, [r7, #12]
8010010: f000 f9dc bl 80103cc <USBD_CoreFindIF>
8010014: 4603 mov r3, r0
8010016: 75bb strb r3, [r7, #22]
break;
8010018: e00d b.n 8010036 <USBD_LL_DataOutStage+0xc6>
case USB_REQ_RECIPIENT_ENDPOINT:
idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex));
801001a: 68fb ldr r3, [r7, #12]
801001c: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae
8010020: b2db uxtb r3, r3
8010022: 4619 mov r1, r3
8010024: 68f8 ldr r0, [r7, #12]
8010026: f000 f9de bl 80103e6 <USBD_CoreFindEP>
801002a: 4603 mov r3, r0
801002c: 75bb strb r3, [r7, #22]
break;
801002e: e002 b.n 8010036 <USBD_LL_DataOutStage+0xc6>
default:
/* Back to the first class in case of doubt */
idx = 0U;
8010030: 2300 movs r3, #0
8010032: 75bb strb r3, [r7, #22]
break;
8010034: bf00 nop
}
if (idx < USBD_MAX_SUPPORTED_CLASS)
8010036: 7dbb ldrb r3, [r7, #22]
8010038: 2b00 cmp r3, #0
801003a: d119 bne.n 8010070 <USBD_LL_DataOutStage+0x100>
{
/* Setup the class ID and route the request to the relative class function */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
801003c: 68fb ldr r3, [r7, #12]
801003e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010042: b2db uxtb r3, r3
8010044: 2b03 cmp r3, #3
8010046: d113 bne.n 8010070 <USBD_LL_DataOutStage+0x100>
{
if (pdev->pClass[idx]->EP0_RxReady != NULL)
8010048: 7dba ldrb r2, [r7, #22]
801004a: 68fb ldr r3, [r7, #12]
801004c: 32ae adds r2, #174 @ 0xae
801004e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8010052: 691b ldr r3, [r3, #16]
8010054: 2b00 cmp r3, #0
8010056: d00b beq.n 8010070 <USBD_LL_DataOutStage+0x100>
{
pdev->classId = idx;
8010058: 7dba ldrb r2, [r7, #22]
801005a: 68fb ldr r3, [r7, #12]
801005c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
pdev->pClass[idx]->EP0_RxReady(pdev);
8010060: 7dba ldrb r2, [r7, #22]
8010062: 68fb ldr r3, [r7, #12]
8010064: 32ae adds r2, #174 @ 0xae
8010066: f853 3022 ldr.w r3, [r3, r2, lsl #2]
801006a: 691b ldr r3, [r3, #16]
801006c: 68f8 ldr r0, [r7, #12]
801006e: 4798 blx r3
}
}
}
(void)USBD_CtlSendStatus(pdev);
8010070: 68f8 ldr r0, [r7, #12]
8010072: f001 f906 bl 8011282 <USBD_CtlSendStatus>
8010076: e032 b.n 80100de <USBD_LL_DataOutStage+0x16e>
}
}
else
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU));
8010078: 7afb ldrb r3, [r7, #11]
801007a: f003 037f and.w r3, r3, #127 @ 0x7f
801007e: b2db uxtb r3, r3
8010080: 4619 mov r1, r3
8010082: 68f8 ldr r0, [r7, #12]
8010084: f000 f9af bl 80103e6 <USBD_CoreFindEP>
8010088: 4603 mov r3, r0
801008a: 75bb strb r3, [r7, #22]
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
801008c: 7dbb ldrb r3, [r7, #22]
801008e: 2bff cmp r3, #255 @ 0xff
8010090: d025 beq.n 80100de <USBD_LL_DataOutStage+0x16e>
8010092: 7dbb ldrb r3, [r7, #22]
8010094: 2b00 cmp r3, #0
8010096: d122 bne.n 80100de <USBD_LL_DataOutStage+0x16e>
{
/* Call the class data out function to manage the request */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8010098: 68fb ldr r3, [r7, #12]
801009a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
801009e: b2db uxtb r3, r3
80100a0: 2b03 cmp r3, #3
80100a2: d117 bne.n 80100d4 <USBD_LL_DataOutStage+0x164>
{
if (pdev->pClass[idx]->DataOut != NULL)
80100a4: 7dba ldrb r2, [r7, #22]
80100a6: 68fb ldr r3, [r7, #12]
80100a8: 32ae adds r2, #174 @ 0xae
80100aa: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80100ae: 699b ldr r3, [r3, #24]
80100b0: 2b00 cmp r3, #0
80100b2: d00f beq.n 80100d4 <USBD_LL_DataOutStage+0x164>
{
pdev->classId = idx;
80100b4: 7dba ldrb r2, [r7, #22]
80100b6: 68fb ldr r3, [r7, #12]
80100b8: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum);
80100bc: 7dba ldrb r2, [r7, #22]
80100be: 68fb ldr r3, [r7, #12]
80100c0: 32ae adds r2, #174 @ 0xae
80100c2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80100c6: 699b ldr r3, [r3, #24]
80100c8: 7afa ldrb r2, [r7, #11]
80100ca: 4611 mov r1, r2
80100cc: 68f8 ldr r0, [r7, #12]
80100ce: 4798 blx r3
80100d0: 4603 mov r3, r0
80100d2: 75fb strb r3, [r7, #23]
}
}
if (ret != USBD_OK)
80100d4: 7dfb ldrb r3, [r7, #23]
80100d6: 2b00 cmp r3, #0
80100d8: d001 beq.n 80100de <USBD_LL_DataOutStage+0x16e>
{
return ret;
80100da: 7dfb ldrb r3, [r7, #23]
80100dc: e000 b.n 80100e0 <USBD_LL_DataOutStage+0x170>
}
}
}
return USBD_OK;
80100de: 2300 movs r3, #0
}
80100e0: 4618 mov r0, r3
80100e2: 3718 adds r7, #24
80100e4: 46bd mov sp, r7
80100e6: bd80 pop {r7, pc}
080100e8 <USBD_LL_DataInStage>:
* @param pdata: data pointer
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
80100e8: b580 push {r7, lr}
80100ea: b086 sub sp, #24
80100ec: af00 add r7, sp, #0
80100ee: 60f8 str r0, [r7, #12]
80100f0: 460b mov r3, r1
80100f2: 607a str r2, [r7, #4]
80100f4: 72fb strb r3, [r7, #11]
USBD_StatusTypeDef ret;
uint8_t idx;
UNUSED(pdata);
if (epnum == 0U)
80100f6: 7afb ldrb r3, [r7, #11]
80100f8: 2b00 cmp r3, #0
80100fa: d178 bne.n 80101ee <USBD_LL_DataInStage+0x106>
{
pep = &pdev->ep_in[0];
80100fc: 68fb ldr r3, [r7, #12]
80100fe: 3314 adds r3, #20
8010100: 613b str r3, [r7, #16]
if (pdev->ep0_state == USBD_EP0_DATA_IN)
8010102: 68fb ldr r3, [r7, #12]
8010104: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294
8010108: 2b02 cmp r3, #2
801010a: d163 bne.n 80101d4 <USBD_LL_DataInStage+0xec>
{
if (pep->rem_length > pep->maxpacket)
801010c: 693b ldr r3, [r7, #16]
801010e: 685b ldr r3, [r3, #4]
8010110: 693a ldr r2, [r7, #16]
8010112: 8992 ldrh r2, [r2, #12]
8010114: 4293 cmp r3, r2
8010116: d91c bls.n 8010152 <USBD_LL_DataInStage+0x6a>
{
pep->rem_length -= pep->maxpacket;
8010118: 693b ldr r3, [r7, #16]
801011a: 685b ldr r3, [r3, #4]
801011c: 693a ldr r2, [r7, #16]
801011e: 8992 ldrh r2, [r2, #12]
8010120: 1a9a subs r2, r3, r2
8010122: 693b ldr r3, [r7, #16]
8010124: 605a str r2, [r3, #4]
pep->pbuffer += pep->maxpacket;
8010126: 693b ldr r3, [r7, #16]
8010128: 691b ldr r3, [r3, #16]
801012a: 693a ldr r2, [r7, #16]
801012c: 8992 ldrh r2, [r2, #12]
801012e: 441a add r2, r3
8010130: 693b ldr r3, [r7, #16]
8010132: 611a str r2, [r3, #16]
(void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length);
8010134: 693b ldr r3, [r7, #16]
8010136: 6919 ldr r1, [r3, #16]
8010138: 693b ldr r3, [r7, #16]
801013a: 685b ldr r3, [r3, #4]
801013c: 461a mov r2, r3
801013e: 68f8 ldr r0, [r7, #12]
8010140: f001 f85c bl 80111fc <USBD_CtlContinueSendData>
/* Prepare endpoint for premature end of transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8010144: 2300 movs r3, #0
8010146: 2200 movs r2, #0
8010148: 2100 movs r1, #0
801014a: 68f8 ldr r0, [r7, #12]
801014c: f007 fab8 bl 80176c0 <USBD_LL_PrepareReceive>
8010150: e040 b.n 80101d4 <USBD_LL_DataInStage+0xec>
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->maxpacket == pep->rem_length) &&
8010152: 693b ldr r3, [r7, #16]
8010154: 899b ldrh r3, [r3, #12]
8010156: 461a mov r2, r3
8010158: 693b ldr r3, [r7, #16]
801015a: 685b ldr r3, [r3, #4]
801015c: 429a cmp r2, r3
801015e: d11c bne.n 801019a <USBD_LL_DataInStage+0xb2>
(pep->total_length >= pep->maxpacket) &&
8010160: 693b ldr r3, [r7, #16]
8010162: 681b ldr r3, [r3, #0]
8010164: 693a ldr r2, [r7, #16]
8010166: 8992 ldrh r2, [r2, #12]
if ((pep->maxpacket == pep->rem_length) &&
8010168: 4293 cmp r3, r2
801016a: d316 bcc.n 801019a <USBD_LL_DataInStage+0xb2>
(pep->total_length < pdev->ep0_data_len))
801016c: 693b ldr r3, [r7, #16]
801016e: 681a ldr r2, [r3, #0]
8010170: 68fb ldr r3, [r7, #12]
8010172: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298
(pep->total_length >= pep->maxpacket) &&
8010176: 429a cmp r2, r3
8010178: d20f bcs.n 801019a <USBD_LL_DataInStage+0xb2>
{
(void)USBD_CtlContinueSendData(pdev, NULL, 0U);
801017a: 2200 movs r2, #0
801017c: 2100 movs r1, #0
801017e: 68f8 ldr r0, [r7, #12]
8010180: f001 f83c bl 80111fc <USBD_CtlContinueSendData>
pdev->ep0_data_len = 0U;
8010184: 68fb ldr r3, [r7, #12]
8010186: 2200 movs r2, #0
8010188: f8c3 2298 str.w r2, [r3, #664] @ 0x298
/* Prepare endpoint for premature end of transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
801018c: 2300 movs r3, #0
801018e: 2200 movs r2, #0
8010190: 2100 movs r1, #0
8010192: 68f8 ldr r0, [r7, #12]
8010194: f007 fa94 bl 80176c0 <USBD_LL_PrepareReceive>
8010198: e01c b.n 80101d4 <USBD_LL_DataInStage+0xec>
}
else
{
if (pdev->dev_state == USBD_STATE_CONFIGURED)
801019a: 68fb ldr r3, [r7, #12]
801019c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80101a0: b2db uxtb r3, r3
80101a2: 2b03 cmp r3, #3
80101a4: d10f bne.n 80101c6 <USBD_LL_DataInStage+0xde>
{
if (pdev->pClass[0]->EP0_TxSent != NULL)
80101a6: 68fb ldr r3, [r7, #12]
80101a8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80101ac: 68db ldr r3, [r3, #12]
80101ae: 2b00 cmp r3, #0
80101b0: d009 beq.n 80101c6 <USBD_LL_DataInStage+0xde>
{
pdev->classId = 0U;
80101b2: 68fb ldr r3, [r7, #12]
80101b4: 2200 movs r2, #0
80101b6: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
pdev->pClass[0]->EP0_TxSent(pdev);
80101ba: 68fb ldr r3, [r7, #12]
80101bc: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80101c0: 68db ldr r3, [r3, #12]
80101c2: 68f8 ldr r0, [r7, #12]
80101c4: 4798 blx r3
}
}
(void)USBD_LL_StallEP(pdev, 0x80U);
80101c6: 2180 movs r1, #128 @ 0x80
80101c8: 68f8 ldr r0, [r7, #12]
80101ca: f007 f9cf bl 801756c <USBD_LL_StallEP>
(void)USBD_CtlReceiveStatus(pdev);
80101ce: 68f8 ldr r0, [r7, #12]
80101d0: f001 f86a bl 80112a8 <USBD_CtlReceiveStatus>
}
}
}
if (pdev->dev_test_mode != 0U)
80101d4: 68fb ldr r3, [r7, #12]
80101d6: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0
80101da: 2b00 cmp r3, #0
80101dc: d03a beq.n 8010254 <USBD_LL_DataInStage+0x16c>
{
(void)USBD_RunTestMode(pdev);
80101de: 68f8 ldr r0, [r7, #12]
80101e0: f7ff fe30 bl 800fe44 <USBD_RunTestMode>
pdev->dev_test_mode = 0U;
80101e4: 68fb ldr r3, [r7, #12]
80101e6: 2200 movs r2, #0
80101e8: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
80101ec: e032 b.n 8010254 <USBD_LL_DataInStage+0x16c>
}
}
else
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U));
80101ee: 7afb ldrb r3, [r7, #11]
80101f0: f063 037f orn r3, r3, #127 @ 0x7f
80101f4: b2db uxtb r3, r3
80101f6: 4619 mov r1, r3
80101f8: 68f8 ldr r0, [r7, #12]
80101fa: f000 f8f4 bl 80103e6 <USBD_CoreFindEP>
80101fe: 4603 mov r3, r0
8010200: 75fb strb r3, [r7, #23]
if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
8010202: 7dfb ldrb r3, [r7, #23]
8010204: 2bff cmp r3, #255 @ 0xff
8010206: d025 beq.n 8010254 <USBD_LL_DataInStage+0x16c>
8010208: 7dfb ldrb r3, [r7, #23]
801020a: 2b00 cmp r3, #0
801020c: d122 bne.n 8010254 <USBD_LL_DataInStage+0x16c>
{
/* Call the class data out function to manage the request */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
801020e: 68fb ldr r3, [r7, #12]
8010210: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010214: b2db uxtb r3, r3
8010216: 2b03 cmp r3, #3
8010218: d11c bne.n 8010254 <USBD_LL_DataInStage+0x16c>
{
if (pdev->pClass[idx]->DataIn != NULL)
801021a: 7dfa ldrb r2, [r7, #23]
801021c: 68fb ldr r3, [r7, #12]
801021e: 32ae adds r2, #174 @ 0xae
8010220: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8010224: 695b ldr r3, [r3, #20]
8010226: 2b00 cmp r3, #0
8010228: d014 beq.n 8010254 <USBD_LL_DataInStage+0x16c>
{
pdev->classId = idx;
801022a: 7dfa ldrb r2, [r7, #23]
801022c: 68fb ldr r3, [r7, #12]
801022e: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum);
8010232: 7dfa ldrb r2, [r7, #23]
8010234: 68fb ldr r3, [r7, #12]
8010236: 32ae adds r2, #174 @ 0xae
8010238: f853 3022 ldr.w r3, [r3, r2, lsl #2]
801023c: 695b ldr r3, [r3, #20]
801023e: 7afa ldrb r2, [r7, #11]
8010240: 4611 mov r1, r2
8010242: 68f8 ldr r0, [r7, #12]
8010244: 4798 blx r3
8010246: 4603 mov r3, r0
8010248: 75bb strb r3, [r7, #22]
if (ret != USBD_OK)
801024a: 7dbb ldrb r3, [r7, #22]
801024c: 2b00 cmp r3, #0
801024e: d001 beq.n 8010254 <USBD_LL_DataInStage+0x16c>
{
return ret;
8010250: 7dbb ldrb r3, [r7, #22]
8010252: e000 b.n 8010256 <USBD_LL_DataInStage+0x16e>
}
}
}
}
return USBD_OK;
8010254: 2300 movs r3, #0
}
8010256: 4618 mov r0, r3
8010258: 3718 adds r7, #24
801025a: 46bd mov sp, r7
801025c: bd80 pop {r7, pc}
0801025e <USBD_LL_Reset>:
* Handle Reset event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
801025e: b580 push {r7, lr}
8010260: b084 sub sp, #16
8010262: af00 add r7, sp, #0
8010264: 6078 str r0, [r7, #4]
USBD_StatusTypeDef ret = USBD_OK;
8010266: 2300 movs r3, #0
8010268: 73fb strb r3, [r7, #15]
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
801026a: 687b ldr r3, [r7, #4]
801026c: 2201 movs r2, #1
801026e: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->ep0_state = USBD_EP0_IDLE;
8010272: 687b ldr r3, [r7, #4]
8010274: 2200 movs r2, #0
8010276: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->dev_config = 0U;
801027a: 687b ldr r3, [r7, #4]
801027c: 2200 movs r2, #0
801027e: 605a str r2, [r3, #4]
pdev->dev_remote_wakeup = 0U;
8010280: 687b ldr r3, [r7, #4]
8010282: 2200 movs r2, #0
8010284: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
pdev->dev_test_mode = 0U;
8010288: 687b ldr r3, [r7, #4]
801028a: 2200 movs r2, #0
801028c: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
}
}
}
#else
if (pdev->pClass[0] != NULL)
8010290: 687b ldr r3, [r7, #4]
8010292: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8010296: 2b00 cmp r3, #0
8010298: d014 beq.n 80102c4 <USBD_LL_Reset+0x66>
{
if (pdev->pClass[0]->DeInit != NULL)
801029a: 687b ldr r3, [r7, #4]
801029c: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80102a0: 685b ldr r3, [r3, #4]
80102a2: 2b00 cmp r3, #0
80102a4: d00e beq.n 80102c4 <USBD_LL_Reset+0x66>
{
if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK)
80102a6: 687b ldr r3, [r7, #4]
80102a8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80102ac: 685b ldr r3, [r3, #4]
80102ae: 687a ldr r2, [r7, #4]
80102b0: 6852 ldr r2, [r2, #4]
80102b2: b2d2 uxtb r2, r2
80102b4: 4611 mov r1, r2
80102b6: 6878 ldr r0, [r7, #4]
80102b8: 4798 blx r3
80102ba: 4603 mov r3, r0
80102bc: 2b00 cmp r3, #0
80102be: d001 beq.n 80102c4 <USBD_LL_Reset+0x66>
{
ret = USBD_FAIL;
80102c0: 2303 movs r3, #3
80102c2: 73fb strb r3, [r7, #15]
}
}
#endif /* USE_USBD_COMPOSITE */
/* Open EP0 OUT */
(void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
80102c4: 2340 movs r3, #64 @ 0x40
80102c6: 2200 movs r2, #0
80102c8: 2100 movs r1, #0
80102ca: 6878 ldr r0, [r7, #4]
80102cc: f007 f909 bl 80174e2 <USBD_LL_OpenEP>
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
80102d0: 687b ldr r3, [r7, #4]
80102d2: 2201 movs r2, #1
80102d4: f883 2163 strb.w r2, [r3, #355] @ 0x163
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
80102d8: 687b ldr r3, [r7, #4]
80102da: 2240 movs r2, #64 @ 0x40
80102dc: f8a3 2160 strh.w r2, [r3, #352] @ 0x160
/* Open EP0 IN */
(void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
80102e0: 2340 movs r3, #64 @ 0x40
80102e2: 2200 movs r2, #0
80102e4: 2180 movs r1, #128 @ 0x80
80102e6: 6878 ldr r0, [r7, #4]
80102e8: f007 f8fb bl 80174e2 <USBD_LL_OpenEP>
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
80102ec: 687b ldr r3, [r7, #4]
80102ee: 2201 movs r2, #1
80102f0: f883 2023 strb.w r2, [r3, #35] @ 0x23
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
80102f4: 687b ldr r3, [r7, #4]
80102f6: 2240 movs r2, #64 @ 0x40
80102f8: 841a strh r2, [r3, #32]
return ret;
80102fa: 7bfb ldrb r3, [r7, #15]
}
80102fc: 4618 mov r0, r3
80102fe: 3710 adds r7, #16
8010300: 46bd mov sp, r7
8010302: bd80 pop {r7, pc}
08010304 <USBD_LL_SetSpeed>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{
8010304: b480 push {r7}
8010306: b083 sub sp, #12
8010308: af00 add r7, sp, #0
801030a: 6078 str r0, [r7, #4]
801030c: 460b mov r3, r1
801030e: 70fb strb r3, [r7, #3]
pdev->dev_speed = speed;
8010310: 687b ldr r3, [r7, #4]
8010312: 78fa ldrb r2, [r7, #3]
8010314: 741a strb r2, [r3, #16]
return USBD_OK;
8010316: 2300 movs r3, #0
}
8010318: 4618 mov r0, r3
801031a: 370c adds r7, #12
801031c: 46bd mov sp, r7
801031e: f85d 7b04 ldr.w r7, [sp], #4
8010322: 4770 bx lr
08010324 <USBD_LL_Suspend>:
* Handle Suspend event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
8010324: b480 push {r7}
8010326: b083 sub sp, #12
8010328: af00 add r7, sp, #0
801032a: 6078 str r0, [r7, #4]
if (pdev->dev_state != USBD_STATE_SUSPENDED)
801032c: 687b ldr r3, [r7, #4]
801032e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010332: b2db uxtb r3, r3
8010334: 2b04 cmp r3, #4
8010336: d006 beq.n 8010346 <USBD_LL_Suspend+0x22>
{
pdev->dev_old_state = pdev->dev_state;
8010338: 687b ldr r3, [r7, #4]
801033a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
801033e: b2da uxtb r2, r3
8010340: 687b ldr r3, [r7, #4]
8010342: f883 229d strb.w r2, [r3, #669] @ 0x29d
}
pdev->dev_state = USBD_STATE_SUSPENDED;
8010346: 687b ldr r3, [r7, #4]
8010348: 2204 movs r2, #4
801034a: f883 229c strb.w r2, [r3, #668] @ 0x29c
return USBD_OK;
801034e: 2300 movs r3, #0
}
8010350: 4618 mov r0, r3
8010352: 370c adds r7, #12
8010354: 46bd mov sp, r7
8010356: f85d 7b04 ldr.w r7, [sp], #4
801035a: 4770 bx lr
0801035c <USBD_LL_Resume>:
* Handle Resume event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{
801035c: b480 push {r7}
801035e: b083 sub sp, #12
8010360: af00 add r7, sp, #0
8010362: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_SUSPENDED)
8010364: 687b ldr r3, [r7, #4]
8010366: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
801036a: b2db uxtb r3, r3
801036c: 2b04 cmp r3, #4
801036e: d106 bne.n 801037e <USBD_LL_Resume+0x22>
{
pdev->dev_state = pdev->dev_old_state;
8010370: 687b ldr r3, [r7, #4]
8010372: f893 329d ldrb.w r3, [r3, #669] @ 0x29d
8010376: b2da uxtb r2, r3
8010378: 687b ldr r3, [r7, #4]
801037a: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
return USBD_OK;
801037e: 2300 movs r3, #0
}
8010380: 4618 mov r0, r3
8010382: 370c adds r7, #12
8010384: 46bd mov sp, r7
8010386: f85d 7b04 ldr.w r7, [sp], #4
801038a: 4770 bx lr
0801038c <USBD_LL_SOF>:
* Handle SOF event
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{
801038c: b580 push {r7, lr}
801038e: b082 sub sp, #8
8010390: af00 add r7, sp, #0
8010392: 6078 str r0, [r7, #4]
/* The SOF event can be distributed for all classes that support it */
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8010394: 687b ldr r3, [r7, #4]
8010396: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
801039a: b2db uxtb r3, r3
801039c: 2b03 cmp r3, #3
801039e: d110 bne.n 80103c2 <USBD_LL_SOF+0x36>
}
}
}
}
#else
if (pdev->pClass[0] != NULL)
80103a0: 687b ldr r3, [r7, #4]
80103a2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80103a6: 2b00 cmp r3, #0
80103a8: d00b beq.n 80103c2 <USBD_LL_SOF+0x36>
{
if (pdev->pClass[0]->SOF != NULL)
80103aa: 687b ldr r3, [r7, #4]
80103ac: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80103b0: 69db ldr r3, [r3, #28]
80103b2: 2b00 cmp r3, #0
80103b4: d005 beq.n 80103c2 <USBD_LL_SOF+0x36>
{
(void)pdev->pClass[0]->SOF(pdev);
80103b6: 687b ldr r3, [r7, #4]
80103b8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
80103bc: 69db ldr r3, [r3, #28]
80103be: 6878 ldr r0, [r7, #4]
80103c0: 4798 blx r3
}
}
#endif /* USE_USBD_COMPOSITE */
}
return USBD_OK;
80103c2: 2300 movs r3, #0
}
80103c4: 4618 mov r0, r3
80103c6: 3708 adds r7, #8
80103c8: 46bd mov sp, r7
80103ca: bd80 pop {r7, pc}
080103cc <USBD_CoreFindIF>:
* @param pdev: device instance
* @param index : selected interface number
* @retval index of the class using the selected interface number. OxFF if no class found.
*/
uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index)
{
80103cc: b480 push {r7}
80103ce: b083 sub sp, #12
80103d0: af00 add r7, sp, #0
80103d2: 6078 str r0, [r7, #4]
80103d4: 460b mov r3, r1
80103d6: 70fb strb r3, [r7, #3]
return 0xFFU;
#else
UNUSED(pdev);
UNUSED(index);
return 0x00U;
80103d8: 2300 movs r3, #0
#endif /* USE_USBD_COMPOSITE */
}
80103da: 4618 mov r0, r3
80103dc: 370c adds r7, #12
80103de: 46bd mov sp, r7
80103e0: f85d 7b04 ldr.w r7, [sp], #4
80103e4: 4770 bx lr
080103e6 <USBD_CoreFindEP>:
* @param pdev: device instance
* @param index : selected endpoint number
* @retval index of the class using the selected endpoint number. 0xFF if no class found.
*/
uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index)
{
80103e6: b480 push {r7}
80103e8: b083 sub sp, #12
80103ea: af00 add r7, sp, #0
80103ec: 6078 str r0, [r7, #4]
80103ee: 460b mov r3, r1
80103f0: 70fb strb r3, [r7, #3]
return 0xFFU;
#else
UNUSED(pdev);
UNUSED(index);
return 0x00U;
80103f2: 2300 movs r3, #0
#endif /* USE_USBD_COMPOSITE */
}
80103f4: 4618 mov r0, r3
80103f6: 370c adds r7, #12
80103f8: 46bd mov sp, r7
80103fa: f85d 7b04 ldr.w r7, [sp], #4
80103fe: 4770 bx lr
08010400 <USBD_GetEpDesc>:
* @param pConfDesc: pointer to Bos descriptor
* @param EpAddr: endpoint address
* @retval pointer to video endpoint descriptor
*/
void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr)
{
8010400: b580 push {r7, lr}
8010402: b086 sub sp, #24
8010404: af00 add r7, sp, #0
8010406: 6078 str r0, [r7, #4]
8010408: 460b mov r3, r1
801040a: 70fb strb r3, [r7, #3]
USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc;
801040c: 687b ldr r3, [r7, #4]
801040e: 617b str r3, [r7, #20]
USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc;
8010410: 687b ldr r3, [r7, #4]
8010412: 60fb str r3, [r7, #12]
USBD_EpDescTypeDef *pEpDesc = NULL;
8010414: 2300 movs r3, #0
8010416: 613b str r3, [r7, #16]
uint16_t ptr;
if (desc->wTotalLength > desc->bLength)
8010418: 68fb ldr r3, [r7, #12]
801041a: 885b ldrh r3, [r3, #2]
801041c: b29b uxth r3, r3
801041e: 68fa ldr r2, [r7, #12]
8010420: 7812 ldrb r2, [r2, #0]
8010422: 4293 cmp r3, r2
8010424: d91f bls.n 8010466 <USBD_GetEpDesc+0x66>
{
ptr = desc->bLength;
8010426: 68fb ldr r3, [r7, #12]
8010428: 781b ldrb r3, [r3, #0]
801042a: 817b strh r3, [r7, #10]
while (ptr < desc->wTotalLength)
801042c: e013 b.n 8010456 <USBD_GetEpDesc+0x56>
{
pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr);
801042e: f107 030a add.w r3, r7, #10
8010432: 4619 mov r1, r3
8010434: 6978 ldr r0, [r7, #20]
8010436: f000 f81b bl 8010470 <USBD_GetNextDesc>
801043a: 6178 str r0, [r7, #20]
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
801043c: 697b ldr r3, [r7, #20]
801043e: 785b ldrb r3, [r3, #1]
8010440: 2b05 cmp r3, #5
8010442: d108 bne.n 8010456 <USBD_GetEpDesc+0x56>
{
pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc;
8010444: 697b ldr r3, [r7, #20]
8010446: 613b str r3, [r7, #16]
if (pEpDesc->bEndpointAddress == EpAddr)
8010448: 693b ldr r3, [r7, #16]
801044a: 789b ldrb r3, [r3, #2]
801044c: 78fa ldrb r2, [r7, #3]
801044e: 429a cmp r2, r3
8010450: d008 beq.n 8010464 <USBD_GetEpDesc+0x64>
{
break;
}
else
{
pEpDesc = NULL;
8010452: 2300 movs r3, #0
8010454: 613b str r3, [r7, #16]
while (ptr < desc->wTotalLength)
8010456: 68fb ldr r3, [r7, #12]
8010458: 885b ldrh r3, [r3, #2]
801045a: b29a uxth r2, r3
801045c: 897b ldrh r3, [r7, #10]
801045e: 429a cmp r2, r3
8010460: d8e5 bhi.n 801042e <USBD_GetEpDesc+0x2e>
8010462: e000 b.n 8010466 <USBD_GetEpDesc+0x66>
break;
8010464: bf00 nop
}
}
}
}
return (void *)pEpDesc;
8010466: 693b ldr r3, [r7, #16]
}
8010468: 4618 mov r0, r3
801046a: 3718 adds r7, #24
801046c: 46bd mov sp, r7
801046e: bd80 pop {r7, pc}
08010470 <USBD_GetNextDesc>:
* @param buf: Buffer where the descriptor is available
* @param ptr: data pointer inside the descriptor
* @retval next header
*/
USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
{
8010470: b480 push {r7}
8010472: b085 sub sp, #20
8010474: af00 add r7, sp, #0
8010476: 6078 str r0, [r7, #4]
8010478: 6039 str r1, [r7, #0]
USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf;
801047a: 687b ldr r3, [r7, #4]
801047c: 60fb str r3, [r7, #12]
*ptr += pnext->bLength;
801047e: 683b ldr r3, [r7, #0]
8010480: 881b ldrh r3, [r3, #0]
8010482: 68fa ldr r2, [r7, #12]
8010484: 7812 ldrb r2, [r2, #0]
8010486: 4413 add r3, r2
8010488: b29a uxth r2, r3
801048a: 683b ldr r3, [r7, #0]
801048c: 801a strh r2, [r3, #0]
pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength);
801048e: 68fb ldr r3, [r7, #12]
8010490: 781b ldrb r3, [r3, #0]
8010492: 461a mov r2, r3
8010494: 687b ldr r3, [r7, #4]
8010496: 4413 add r3, r2
8010498: 60fb str r3, [r7, #12]
return (pnext);
801049a: 68fb ldr r3, [r7, #12]
}
801049c: 4618 mov r0, r3
801049e: 3714 adds r7, #20
80104a0: 46bd mov sp, r7
80104a2: f85d 7b04 ldr.w r7, [sp], #4
80104a6: 4770 bx lr
080104a8 <SWAPBYTE>:
/** @defgroup USBD_DEF_Exported_Macros
* @{
*/
__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr)
{
80104a8: b480 push {r7}
80104aa: b087 sub sp, #28
80104ac: af00 add r7, sp, #0
80104ae: 6078 str r0, [r7, #4]
uint16_t _SwapVal;
uint16_t _Byte1;
uint16_t _Byte2;
uint8_t *_pbuff = addr;
80104b0: 687b ldr r3, [r7, #4]
80104b2: 617b str r3, [r7, #20]
_Byte1 = *(uint8_t *)_pbuff;
80104b4: 697b ldr r3, [r7, #20]
80104b6: 781b ldrb r3, [r3, #0]
80104b8: 827b strh r3, [r7, #18]
_pbuff++;
80104ba: 697b ldr r3, [r7, #20]
80104bc: 3301 adds r3, #1
80104be: 617b str r3, [r7, #20]
_Byte2 = *(uint8_t *)_pbuff;
80104c0: 697b ldr r3, [r7, #20]
80104c2: 781b ldrb r3, [r3, #0]
80104c4: 823b strh r3, [r7, #16]
_SwapVal = (_Byte2 << 8) | _Byte1;
80104c6: f9b7 3010 ldrsh.w r3, [r7, #16]
80104ca: 021b lsls r3, r3, #8
80104cc: b21a sxth r2, r3
80104ce: f9b7 3012 ldrsh.w r3, [r7, #18]
80104d2: 4313 orrs r3, r2
80104d4: b21b sxth r3, r3
80104d6: 81fb strh r3, [r7, #14]
return _SwapVal;
80104d8: 89fb ldrh r3, [r7, #14]
}
80104da: 4618 mov r0, r3
80104dc: 371c adds r7, #28
80104de: 46bd mov sp, r7
80104e0: f85d 7b04 ldr.w r7, [sp], #4
80104e4: 4770 bx lr
...
080104e8 <USBD_StdDevReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80104e8: b580 push {r7, lr}
80104ea: b084 sub sp, #16
80104ec: af00 add r7, sp, #0
80104ee: 6078 str r0, [r7, #4]
80104f0: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
80104f2: 2300 movs r3, #0
80104f4: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
80104f6: 683b ldr r3, [r7, #0]
80104f8: 781b ldrb r3, [r3, #0]
80104fa: f003 0360 and.w r3, r3, #96 @ 0x60
80104fe: 2b40 cmp r3, #64 @ 0x40
8010500: d005 beq.n 801050e <USBD_StdDevReq+0x26>
8010502: 2b40 cmp r3, #64 @ 0x40
8010504: d857 bhi.n 80105b6 <USBD_StdDevReq+0xce>
8010506: 2b00 cmp r3, #0
8010508: d00f beq.n 801052a <USBD_StdDevReq+0x42>
801050a: 2b20 cmp r3, #32
801050c: d153 bne.n 80105b6 <USBD_StdDevReq+0xce>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req);
801050e: 687b ldr r3, [r7, #4]
8010510: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4
8010514: 687b ldr r3, [r7, #4]
8010516: 32ae adds r2, #174 @ 0xae
8010518: f853 3022 ldr.w r3, [r3, r2, lsl #2]
801051c: 689b ldr r3, [r3, #8]
801051e: 6839 ldr r1, [r7, #0]
8010520: 6878 ldr r0, [r7, #4]
8010522: 4798 blx r3
8010524: 4603 mov r3, r0
8010526: 73fb strb r3, [r7, #15]
break;
8010528: e04a b.n 80105c0 <USBD_StdDevReq+0xd8>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
801052a: 683b ldr r3, [r7, #0]
801052c: 785b ldrb r3, [r3, #1]
801052e: 2b09 cmp r3, #9
8010530: d83b bhi.n 80105aa <USBD_StdDevReq+0xc2>
8010532: a201 add r2, pc, #4 @ (adr r2, 8010538 <USBD_StdDevReq+0x50>)
8010534: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8010538: 0801058d .word 0x0801058d
801053c: 080105a1 .word 0x080105a1
8010540: 080105ab .word 0x080105ab
8010544: 08010597 .word 0x08010597
8010548: 080105ab .word 0x080105ab
801054c: 0801056b .word 0x0801056b
8010550: 08010561 .word 0x08010561
8010554: 080105ab .word 0x080105ab
8010558: 08010583 .word 0x08010583
801055c: 08010575 .word 0x08010575
{
case USB_REQ_GET_DESCRIPTOR:
USBD_GetDescriptor(pdev, req);
8010560: 6839 ldr r1, [r7, #0]
8010562: 6878 ldr r0, [r7, #4]
8010564: f000 fa3e bl 80109e4 <USBD_GetDescriptor>
break;
8010568: e024 b.n 80105b4 <USBD_StdDevReq+0xcc>
case USB_REQ_SET_ADDRESS:
USBD_SetAddress(pdev, req);
801056a: 6839 ldr r1, [r7, #0]
801056c: 6878 ldr r0, [r7, #4]
801056e: f000 fbcd bl 8010d0c <USBD_SetAddress>
break;
8010572: e01f b.n 80105b4 <USBD_StdDevReq+0xcc>
case USB_REQ_SET_CONFIGURATION:
ret = USBD_SetConfig(pdev, req);
8010574: 6839 ldr r1, [r7, #0]
8010576: 6878 ldr r0, [r7, #4]
8010578: f000 fc0c bl 8010d94 <USBD_SetConfig>
801057c: 4603 mov r3, r0
801057e: 73fb strb r3, [r7, #15]
break;
8010580: e018 b.n 80105b4 <USBD_StdDevReq+0xcc>
case USB_REQ_GET_CONFIGURATION:
USBD_GetConfig(pdev, req);
8010582: 6839 ldr r1, [r7, #0]
8010584: 6878 ldr r0, [r7, #4]
8010586: f000 fcaf bl 8010ee8 <USBD_GetConfig>
break;
801058a: e013 b.n 80105b4 <USBD_StdDevReq+0xcc>
case USB_REQ_GET_STATUS:
USBD_GetStatus(pdev, req);
801058c: 6839 ldr r1, [r7, #0]
801058e: 6878 ldr r0, [r7, #4]
8010590: f000 fce0 bl 8010f54 <USBD_GetStatus>
break;
8010594: e00e b.n 80105b4 <USBD_StdDevReq+0xcc>
case USB_REQ_SET_FEATURE:
USBD_SetFeature(pdev, req);
8010596: 6839 ldr r1, [r7, #0]
8010598: 6878 ldr r0, [r7, #4]
801059a: f000 fd0f bl 8010fbc <USBD_SetFeature>
break;
801059e: e009 b.n 80105b4 <USBD_StdDevReq+0xcc>
case USB_REQ_CLEAR_FEATURE:
USBD_ClrFeature(pdev, req);
80105a0: 6839 ldr r1, [r7, #0]
80105a2: 6878 ldr r0, [r7, #4]
80105a4: f000 fd33 bl 801100e <USBD_ClrFeature>
break;
80105a8: e004 b.n 80105b4 <USBD_StdDevReq+0xcc>
default:
USBD_CtlError(pdev, req);
80105aa: 6839 ldr r1, [r7, #0]
80105ac: 6878 ldr r0, [r7, #4]
80105ae: f000 fd8a bl 80110c6 <USBD_CtlError>
break;
80105b2: bf00 nop
}
break;
80105b4: e004 b.n 80105c0 <USBD_StdDevReq+0xd8>
default:
USBD_CtlError(pdev, req);
80105b6: 6839 ldr r1, [r7, #0]
80105b8: 6878 ldr r0, [r7, #4]
80105ba: f000 fd84 bl 80110c6 <USBD_CtlError>
break;
80105be: bf00 nop
}
return ret;
80105c0: 7bfb ldrb r3, [r7, #15]
}
80105c2: 4618 mov r0, r3
80105c4: 3710 adds r7, #16
80105c6: 46bd mov sp, r7
80105c8: bd80 pop {r7, pc}
80105ca: bf00 nop
080105cc <USBD_StdItfReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80105cc: b580 push {r7, lr}
80105ce: b084 sub sp, #16
80105d0: af00 add r7, sp, #0
80105d2: 6078 str r0, [r7, #4]
80105d4: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
80105d6: 2300 movs r3, #0
80105d8: 73fb strb r3, [r7, #15]
uint8_t idx;
switch (req->bmRequest & USB_REQ_TYPE_MASK)
80105da: 683b ldr r3, [r7, #0]
80105dc: 781b ldrb r3, [r3, #0]
80105de: f003 0360 and.w r3, r3, #96 @ 0x60
80105e2: 2b40 cmp r3, #64 @ 0x40
80105e4: d005 beq.n 80105f2 <USBD_StdItfReq+0x26>
80105e6: 2b40 cmp r3, #64 @ 0x40
80105e8: d852 bhi.n 8010690 <USBD_StdItfReq+0xc4>
80105ea: 2b00 cmp r3, #0
80105ec: d001 beq.n 80105f2 <USBD_StdItfReq+0x26>
80105ee: 2b20 cmp r3, #32
80105f0: d14e bne.n 8010690 <USBD_StdItfReq+0xc4>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
case USB_REQ_TYPE_STANDARD:
switch (pdev->dev_state)
80105f2: 687b ldr r3, [r7, #4]
80105f4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80105f8: b2db uxtb r3, r3
80105fa: 3b01 subs r3, #1
80105fc: 2b02 cmp r3, #2
80105fe: d840 bhi.n 8010682 <USBD_StdItfReq+0xb6>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
8010600: 683b ldr r3, [r7, #0]
8010602: 889b ldrh r3, [r3, #4]
8010604: b2db uxtb r3, r3
8010606: 2b01 cmp r3, #1
8010608: d836 bhi.n 8010678 <USBD_StdItfReq+0xac>
{
/* Get the class index relative to this interface */
idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex));
801060a: 683b ldr r3, [r7, #0]
801060c: 889b ldrh r3, [r3, #4]
801060e: b2db uxtb r3, r3
8010610: 4619 mov r1, r3
8010612: 6878 ldr r0, [r7, #4]
8010614: f7ff feda bl 80103cc <USBD_CoreFindIF>
8010618: 4603 mov r3, r0
801061a: 73bb strb r3, [r7, #14]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
801061c: 7bbb ldrb r3, [r7, #14]
801061e: 2bff cmp r3, #255 @ 0xff
8010620: d01d beq.n 801065e <USBD_StdItfReq+0x92>
8010622: 7bbb ldrb r3, [r7, #14]
8010624: 2b00 cmp r3, #0
8010626: d11a bne.n 801065e <USBD_StdItfReq+0x92>
{
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
8010628: 7bba ldrb r2, [r7, #14]
801062a: 687b ldr r3, [r7, #4]
801062c: 32ae adds r2, #174 @ 0xae
801062e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8010632: 689b ldr r3, [r3, #8]
8010634: 2b00 cmp r3, #0
8010636: d00f beq.n 8010658 <USBD_StdItfReq+0x8c>
{
pdev->classId = idx;
8010638: 7bba ldrb r2, [r7, #14]
801063a: 687b ldr r3, [r7, #4]
801063c: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
8010640: 7bba ldrb r2, [r7, #14]
8010642: 687b ldr r3, [r7, #4]
8010644: 32ae adds r2, #174 @ 0xae
8010646: f853 3022 ldr.w r3, [r3, r2, lsl #2]
801064a: 689b ldr r3, [r3, #8]
801064c: 6839 ldr r1, [r7, #0]
801064e: 6878 ldr r0, [r7, #4]
8010650: 4798 blx r3
8010652: 4603 mov r3, r0
8010654: 73fb strb r3, [r7, #15]
if (pdev->pClass[idx]->Setup != NULL)
8010656: e004 b.n 8010662 <USBD_StdItfReq+0x96>
}
else
{
/* should never reach this condition */
ret = USBD_FAIL;
8010658: 2303 movs r3, #3
801065a: 73fb strb r3, [r7, #15]
if (pdev->pClass[idx]->Setup != NULL)
801065c: e001 b.n 8010662 <USBD_StdItfReq+0x96>
}
}
else
{
/* No relative interface found */
ret = USBD_FAIL;
801065e: 2303 movs r3, #3
8010660: 73fb strb r3, [r7, #15]
}
if ((req->wLength == 0U) && (ret == USBD_OK))
8010662: 683b ldr r3, [r7, #0]
8010664: 88db ldrh r3, [r3, #6]
8010666: 2b00 cmp r3, #0
8010668: d110 bne.n 801068c <USBD_StdItfReq+0xc0>
801066a: 7bfb ldrb r3, [r7, #15]
801066c: 2b00 cmp r3, #0
801066e: d10d bne.n 801068c <USBD_StdItfReq+0xc0>
{
(void)USBD_CtlSendStatus(pdev);
8010670: 6878 ldr r0, [r7, #4]
8010672: f000 fe06 bl 8011282 <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8010676: e009 b.n 801068c <USBD_StdItfReq+0xc0>
USBD_CtlError(pdev, req);
8010678: 6839 ldr r1, [r7, #0]
801067a: 6878 ldr r0, [r7, #4]
801067c: f000 fd23 bl 80110c6 <USBD_CtlError>
break;
8010680: e004 b.n 801068c <USBD_StdItfReq+0xc0>
default:
USBD_CtlError(pdev, req);
8010682: 6839 ldr r1, [r7, #0]
8010684: 6878 ldr r0, [r7, #4]
8010686: f000 fd1e bl 80110c6 <USBD_CtlError>
break;
801068a: e000 b.n 801068e <USBD_StdItfReq+0xc2>
break;
801068c: bf00 nop
}
break;
801068e: e004 b.n 801069a <USBD_StdItfReq+0xce>
default:
USBD_CtlError(pdev, req);
8010690: 6839 ldr r1, [r7, #0]
8010692: 6878 ldr r0, [r7, #4]
8010694: f000 fd17 bl 80110c6 <USBD_CtlError>
break;
8010698: bf00 nop
}
return ret;
801069a: 7bfb ldrb r3, [r7, #15]
}
801069c: 4618 mov r0, r3
801069e: 3710 adds r7, #16
80106a0: 46bd mov sp, r7
80106a2: bd80 pop {r7, pc}
080106a4 <USBD_StdEPReq>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80106a4: b580 push {r7, lr}
80106a6: b084 sub sp, #16
80106a8: af00 add r7, sp, #0
80106aa: 6078 str r0, [r7, #4]
80106ac: 6039 str r1, [r7, #0]
USBD_EndpointTypeDef *pep;
uint8_t ep_addr;
uint8_t idx;
USBD_StatusTypeDef ret = USBD_OK;
80106ae: 2300 movs r3, #0
80106b0: 73fb strb r3, [r7, #15]
ep_addr = LOBYTE(req->wIndex);
80106b2: 683b ldr r3, [r7, #0]
80106b4: 889b ldrh r3, [r3, #4]
80106b6: 73bb strb r3, [r7, #14]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
80106b8: 683b ldr r3, [r7, #0]
80106ba: 781b ldrb r3, [r3, #0]
80106bc: f003 0360 and.w r3, r3, #96 @ 0x60
80106c0: 2b40 cmp r3, #64 @ 0x40
80106c2: d007 beq.n 80106d4 <USBD_StdEPReq+0x30>
80106c4: 2b40 cmp r3, #64 @ 0x40
80106c6: f200 8181 bhi.w 80109cc <USBD_StdEPReq+0x328>
80106ca: 2b00 cmp r3, #0
80106cc: d02a beq.n 8010724 <USBD_StdEPReq+0x80>
80106ce: 2b20 cmp r3, #32
80106d0: f040 817c bne.w 80109cc <USBD_StdEPReq+0x328>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
/* Get the class index relative to this endpoint */
idx = USBD_CoreFindEP(pdev, ep_addr);
80106d4: 7bbb ldrb r3, [r7, #14]
80106d6: 4619 mov r1, r3
80106d8: 6878 ldr r0, [r7, #4]
80106da: f7ff fe84 bl 80103e6 <USBD_CoreFindEP>
80106de: 4603 mov r3, r0
80106e0: 737b strb r3, [r7, #13]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
80106e2: 7b7b ldrb r3, [r7, #13]
80106e4: 2bff cmp r3, #255 @ 0xff
80106e6: f000 8176 beq.w 80109d6 <USBD_StdEPReq+0x332>
80106ea: 7b7b ldrb r3, [r7, #13]
80106ec: 2b00 cmp r3, #0
80106ee: f040 8172 bne.w 80109d6 <USBD_StdEPReq+0x332>
{
pdev->classId = idx;
80106f2: 7b7a ldrb r2, [r7, #13]
80106f4: 687b ldr r3, [r7, #4]
80106f6: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
80106fa: 7b7a ldrb r2, [r7, #13]
80106fc: 687b ldr r3, [r7, #4]
80106fe: 32ae adds r2, #174 @ 0xae
8010700: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8010704: 689b ldr r3, [r3, #8]
8010706: 2b00 cmp r3, #0
8010708: f000 8165 beq.w 80109d6 <USBD_StdEPReq+0x332>
{
ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req);
801070c: 7b7a ldrb r2, [r7, #13]
801070e: 687b ldr r3, [r7, #4]
8010710: 32ae adds r2, #174 @ 0xae
8010712: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8010716: 689b ldr r3, [r3, #8]
8010718: 6839 ldr r1, [r7, #0]
801071a: 6878 ldr r0, [r7, #4]
801071c: 4798 blx r3
801071e: 4603 mov r3, r0
8010720: 73fb strb r3, [r7, #15]
}
}
break;
8010722: e158 b.n 80109d6 <USBD_StdEPReq+0x332>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8010724: 683b ldr r3, [r7, #0]
8010726: 785b ldrb r3, [r3, #1]
8010728: 2b03 cmp r3, #3
801072a: d008 beq.n 801073e <USBD_StdEPReq+0x9a>
801072c: 2b03 cmp r3, #3
801072e: f300 8147 bgt.w 80109c0 <USBD_StdEPReq+0x31c>
8010732: 2b00 cmp r3, #0
8010734: f000 809b beq.w 801086e <USBD_StdEPReq+0x1ca>
8010738: 2b01 cmp r3, #1
801073a: d03c beq.n 80107b6 <USBD_StdEPReq+0x112>
801073c: e140 b.n 80109c0 <USBD_StdEPReq+0x31c>
{
case USB_REQ_SET_FEATURE:
switch (pdev->dev_state)
801073e: 687b ldr r3, [r7, #4]
8010740: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010744: b2db uxtb r3, r3
8010746: 2b02 cmp r3, #2
8010748: d002 beq.n 8010750 <USBD_StdEPReq+0xac>
801074a: 2b03 cmp r3, #3
801074c: d016 beq.n 801077c <USBD_StdEPReq+0xd8>
801074e: e02c b.n 80107aa <USBD_StdEPReq+0x106>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8010750: 7bbb ldrb r3, [r7, #14]
8010752: 2b00 cmp r3, #0
8010754: d00d beq.n 8010772 <USBD_StdEPReq+0xce>
8010756: 7bbb ldrb r3, [r7, #14]
8010758: 2b80 cmp r3, #128 @ 0x80
801075a: d00a beq.n 8010772 <USBD_StdEPReq+0xce>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
801075c: 7bbb ldrb r3, [r7, #14]
801075e: 4619 mov r1, r3
8010760: 6878 ldr r0, [r7, #4]
8010762: f006 ff03 bl 801756c <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0x80U);
8010766: 2180 movs r1, #128 @ 0x80
8010768: 6878 ldr r0, [r7, #4]
801076a: f006 feff bl 801756c <USBD_LL_StallEP>
801076e: bf00 nop
}
else
{
USBD_CtlError(pdev, req);
}
break;
8010770: e020 b.n 80107b4 <USBD_StdEPReq+0x110>
USBD_CtlError(pdev, req);
8010772: 6839 ldr r1, [r7, #0]
8010774: 6878 ldr r0, [r7, #4]
8010776: f000 fca6 bl 80110c6 <USBD_CtlError>
break;
801077a: e01b b.n 80107b4 <USBD_StdEPReq+0x110>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
801077c: 683b ldr r3, [r7, #0]
801077e: 885b ldrh r3, [r3, #2]
8010780: 2b00 cmp r3, #0
8010782: d10e bne.n 80107a2 <USBD_StdEPReq+0xfe>
{
if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U))
8010784: 7bbb ldrb r3, [r7, #14]
8010786: 2b00 cmp r3, #0
8010788: d00b beq.n 80107a2 <USBD_StdEPReq+0xfe>
801078a: 7bbb ldrb r3, [r7, #14]
801078c: 2b80 cmp r3, #128 @ 0x80
801078e: d008 beq.n 80107a2 <USBD_StdEPReq+0xfe>
8010790: 683b ldr r3, [r7, #0]
8010792: 88db ldrh r3, [r3, #6]
8010794: 2b00 cmp r3, #0
8010796: d104 bne.n 80107a2 <USBD_StdEPReq+0xfe>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
8010798: 7bbb ldrb r3, [r7, #14]
801079a: 4619 mov r1, r3
801079c: 6878 ldr r0, [r7, #4]
801079e: f006 fee5 bl 801756c <USBD_LL_StallEP>
}
}
(void)USBD_CtlSendStatus(pdev);
80107a2: 6878 ldr r0, [r7, #4]
80107a4: f000 fd6d bl 8011282 <USBD_CtlSendStatus>
break;
80107a8: e004 b.n 80107b4 <USBD_StdEPReq+0x110>
default:
USBD_CtlError(pdev, req);
80107aa: 6839 ldr r1, [r7, #0]
80107ac: 6878 ldr r0, [r7, #4]
80107ae: f000 fc8a bl 80110c6 <USBD_CtlError>
break;
80107b2: bf00 nop
}
break;
80107b4: e109 b.n 80109ca <USBD_StdEPReq+0x326>
case USB_REQ_CLEAR_FEATURE:
switch (pdev->dev_state)
80107b6: 687b ldr r3, [r7, #4]
80107b8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
80107bc: b2db uxtb r3, r3
80107be: 2b02 cmp r3, #2
80107c0: d002 beq.n 80107c8 <USBD_StdEPReq+0x124>
80107c2: 2b03 cmp r3, #3
80107c4: d016 beq.n 80107f4 <USBD_StdEPReq+0x150>
80107c6: e04b b.n 8010860 <USBD_StdEPReq+0x1bc>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
80107c8: 7bbb ldrb r3, [r7, #14]
80107ca: 2b00 cmp r3, #0
80107cc: d00d beq.n 80107ea <USBD_StdEPReq+0x146>
80107ce: 7bbb ldrb r3, [r7, #14]
80107d0: 2b80 cmp r3, #128 @ 0x80
80107d2: d00a beq.n 80107ea <USBD_StdEPReq+0x146>
{
(void)USBD_LL_StallEP(pdev, ep_addr);
80107d4: 7bbb ldrb r3, [r7, #14]
80107d6: 4619 mov r1, r3
80107d8: 6878 ldr r0, [r7, #4]
80107da: f006 fec7 bl 801756c <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0x80U);
80107de: 2180 movs r1, #128 @ 0x80
80107e0: 6878 ldr r0, [r7, #4]
80107e2: f006 fec3 bl 801756c <USBD_LL_StallEP>
80107e6: bf00 nop
}
else
{
USBD_CtlError(pdev, req);
}
break;
80107e8: e040 b.n 801086c <USBD_StdEPReq+0x1c8>
USBD_CtlError(pdev, req);
80107ea: 6839 ldr r1, [r7, #0]
80107ec: 6878 ldr r0, [r7, #4]
80107ee: f000 fc6a bl 80110c6 <USBD_CtlError>
break;
80107f2: e03b b.n 801086c <USBD_StdEPReq+0x1c8>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
80107f4: 683b ldr r3, [r7, #0]
80107f6: 885b ldrh r3, [r3, #2]
80107f8: 2b00 cmp r3, #0
80107fa: d136 bne.n 801086a <USBD_StdEPReq+0x1c6>
{
if ((ep_addr & 0x7FU) != 0x00U)
80107fc: 7bbb ldrb r3, [r7, #14]
80107fe: f003 037f and.w r3, r3, #127 @ 0x7f
8010802: 2b00 cmp r3, #0
8010804: d004 beq.n 8010810 <USBD_StdEPReq+0x16c>
{
(void)USBD_LL_ClearStallEP(pdev, ep_addr);
8010806: 7bbb ldrb r3, [r7, #14]
8010808: 4619 mov r1, r3
801080a: 6878 ldr r0, [r7, #4]
801080c: f006 fecd bl 80175aa <USBD_LL_ClearStallEP>
}
(void)USBD_CtlSendStatus(pdev);
8010810: 6878 ldr r0, [r7, #4]
8010812: f000 fd36 bl 8011282 <USBD_CtlSendStatus>
/* Get the class index relative to this interface */
idx = USBD_CoreFindEP(pdev, ep_addr);
8010816: 7bbb ldrb r3, [r7, #14]
8010818: 4619 mov r1, r3
801081a: 6878 ldr r0, [r7, #4]
801081c: f7ff fde3 bl 80103e6 <USBD_CoreFindEP>
8010820: 4603 mov r3, r0
8010822: 737b strb r3, [r7, #13]
if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS))
8010824: 7b7b ldrb r3, [r7, #13]
8010826: 2bff cmp r3, #255 @ 0xff
8010828: d01f beq.n 801086a <USBD_StdEPReq+0x1c6>
801082a: 7b7b ldrb r3, [r7, #13]
801082c: 2b00 cmp r3, #0
801082e: d11c bne.n 801086a <USBD_StdEPReq+0x1c6>
{
pdev->classId = idx;
8010830: 7b7a ldrb r2, [r7, #13]
8010832: 687b ldr r3, [r7, #4]
8010834: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4
/* Call the class data out function to manage the request */
if (pdev->pClass[idx]->Setup != NULL)
8010838: 7b7a ldrb r2, [r7, #13]
801083a: 687b ldr r3, [r7, #4]
801083c: 32ae adds r2, #174 @ 0xae
801083e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8010842: 689b ldr r3, [r3, #8]
8010844: 2b00 cmp r3, #0
8010846: d010 beq.n 801086a <USBD_StdEPReq+0x1c6>
{
ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req));
8010848: 7b7a ldrb r2, [r7, #13]
801084a: 687b ldr r3, [r7, #4]
801084c: 32ae adds r2, #174 @ 0xae
801084e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8010852: 689b ldr r3, [r3, #8]
8010854: 6839 ldr r1, [r7, #0]
8010856: 6878 ldr r0, [r7, #4]
8010858: 4798 blx r3
801085a: 4603 mov r3, r0
801085c: 73fb strb r3, [r7, #15]
}
}
}
break;
801085e: e004 b.n 801086a <USBD_StdEPReq+0x1c6>
default:
USBD_CtlError(pdev, req);
8010860: 6839 ldr r1, [r7, #0]
8010862: 6878 ldr r0, [r7, #4]
8010864: f000 fc2f bl 80110c6 <USBD_CtlError>
break;
8010868: e000 b.n 801086c <USBD_StdEPReq+0x1c8>
break;
801086a: bf00 nop
}
break;
801086c: e0ad b.n 80109ca <USBD_StdEPReq+0x326>
case USB_REQ_GET_STATUS:
switch (pdev->dev_state)
801086e: 687b ldr r3, [r7, #4]
8010870: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010874: b2db uxtb r3, r3
8010876: 2b02 cmp r3, #2
8010878: d002 beq.n 8010880 <USBD_StdEPReq+0x1dc>
801087a: 2b03 cmp r3, #3
801087c: d033 beq.n 80108e6 <USBD_StdEPReq+0x242>
801087e: e099 b.n 80109b4 <USBD_StdEPReq+0x310>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8010880: 7bbb ldrb r3, [r7, #14]
8010882: 2b00 cmp r3, #0
8010884: d007 beq.n 8010896 <USBD_StdEPReq+0x1f2>
8010886: 7bbb ldrb r3, [r7, #14]
8010888: 2b80 cmp r3, #128 @ 0x80
801088a: d004 beq.n 8010896 <USBD_StdEPReq+0x1f2>
{
USBD_CtlError(pdev, req);
801088c: 6839 ldr r1, [r7, #0]
801088e: 6878 ldr r0, [r7, #4]
8010890: f000 fc19 bl 80110c6 <USBD_CtlError>
break;
8010894: e093 b.n 80109be <USBD_StdEPReq+0x31a>
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8010896: f997 300e ldrsb.w r3, [r7, #14]
801089a: 2b00 cmp r3, #0
801089c: da0b bge.n 80108b6 <USBD_StdEPReq+0x212>
801089e: 7bbb ldrb r3, [r7, #14]
80108a0: f003 027f and.w r2, r3, #127 @ 0x7f
80108a4: 4613 mov r3, r2
80108a6: 009b lsls r3, r3, #2
80108a8: 4413 add r3, r2
80108aa: 009b lsls r3, r3, #2
80108ac: 3310 adds r3, #16
80108ae: 687a ldr r2, [r7, #4]
80108b0: 4413 add r3, r2
80108b2: 3304 adds r3, #4
80108b4: e00b b.n 80108ce <USBD_StdEPReq+0x22a>
&pdev->ep_out[ep_addr & 0x7FU];
80108b6: 7bbb ldrb r3, [r7, #14]
80108b8: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
80108bc: 4613 mov r3, r2
80108be: 009b lsls r3, r3, #2
80108c0: 4413 add r3, r2
80108c2: 009b lsls r3, r3, #2
80108c4: f503 73a8 add.w r3, r3, #336 @ 0x150
80108c8: 687a ldr r2, [r7, #4]
80108ca: 4413 add r3, r2
80108cc: 3304 adds r3, #4
80108ce: 60bb str r3, [r7, #8]
pep->status = 0x0000U;
80108d0: 68bb ldr r3, [r7, #8]
80108d2: 2200 movs r2, #0
80108d4: 739a strb r2, [r3, #14]
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
80108d6: 68bb ldr r3, [r7, #8]
80108d8: 330e adds r3, #14
80108da: 2202 movs r2, #2
80108dc: 4619 mov r1, r3
80108de: 6878 ldr r0, [r7, #4]
80108e0: f000 fc6e bl 80111c0 <USBD_CtlSendData>
break;
80108e4: e06b b.n 80109be <USBD_StdEPReq+0x31a>
case USBD_STATE_CONFIGURED:
if ((ep_addr & 0x80U) == 0x80U)
80108e6: f997 300e ldrsb.w r3, [r7, #14]
80108ea: 2b00 cmp r3, #0
80108ec: da11 bge.n 8010912 <USBD_StdEPReq+0x26e>
{
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
80108ee: 7bbb ldrb r3, [r7, #14]
80108f0: f003 020f and.w r2, r3, #15
80108f4: 6879 ldr r1, [r7, #4]
80108f6: 4613 mov r3, r2
80108f8: 009b lsls r3, r3, #2
80108fa: 4413 add r3, r2
80108fc: 009b lsls r3, r3, #2
80108fe: 440b add r3, r1
8010900: 3323 adds r3, #35 @ 0x23
8010902: 781b ldrb r3, [r3, #0]
8010904: 2b00 cmp r3, #0
8010906: d117 bne.n 8010938 <USBD_StdEPReq+0x294>
{
USBD_CtlError(pdev, req);
8010908: 6839 ldr r1, [r7, #0]
801090a: 6878 ldr r0, [r7, #4]
801090c: f000 fbdb bl 80110c6 <USBD_CtlError>
break;
8010910: e055 b.n 80109be <USBD_StdEPReq+0x31a>
}
}
else
{
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
8010912: 7bbb ldrb r3, [r7, #14]
8010914: f003 020f and.w r2, r3, #15
8010918: 6879 ldr r1, [r7, #4]
801091a: 4613 mov r3, r2
801091c: 009b lsls r3, r3, #2
801091e: 4413 add r3, r2
8010920: 009b lsls r3, r3, #2
8010922: 440b add r3, r1
8010924: f203 1363 addw r3, r3, #355 @ 0x163
8010928: 781b ldrb r3, [r3, #0]
801092a: 2b00 cmp r3, #0
801092c: d104 bne.n 8010938 <USBD_StdEPReq+0x294>
{
USBD_CtlError(pdev, req);
801092e: 6839 ldr r1, [r7, #0]
8010930: 6878 ldr r0, [r7, #4]
8010932: f000 fbc8 bl 80110c6 <USBD_CtlError>
break;
8010936: e042 b.n 80109be <USBD_StdEPReq+0x31a>
}
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8010938: f997 300e ldrsb.w r3, [r7, #14]
801093c: 2b00 cmp r3, #0
801093e: da0b bge.n 8010958 <USBD_StdEPReq+0x2b4>
8010940: 7bbb ldrb r3, [r7, #14]
8010942: f003 027f and.w r2, r3, #127 @ 0x7f
8010946: 4613 mov r3, r2
8010948: 009b lsls r3, r3, #2
801094a: 4413 add r3, r2
801094c: 009b lsls r3, r3, #2
801094e: 3310 adds r3, #16
8010950: 687a ldr r2, [r7, #4]
8010952: 4413 add r3, r2
8010954: 3304 adds r3, #4
8010956: e00b b.n 8010970 <USBD_StdEPReq+0x2cc>
&pdev->ep_out[ep_addr & 0x7FU];
8010958: 7bbb ldrb r3, [r7, #14]
801095a: f003 027f and.w r2, r3, #127 @ 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
801095e: 4613 mov r3, r2
8010960: 009b lsls r3, r3, #2
8010962: 4413 add r3, r2
8010964: 009b lsls r3, r3, #2
8010966: f503 73a8 add.w r3, r3, #336 @ 0x150
801096a: 687a ldr r2, [r7, #4]
801096c: 4413 add r3, r2
801096e: 3304 adds r3, #4
8010970: 60bb str r3, [r7, #8]
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
8010972: 7bbb ldrb r3, [r7, #14]
8010974: 2b00 cmp r3, #0
8010976: d002 beq.n 801097e <USBD_StdEPReq+0x2da>
8010978: 7bbb ldrb r3, [r7, #14]
801097a: 2b80 cmp r3, #128 @ 0x80
801097c: d103 bne.n 8010986 <USBD_StdEPReq+0x2e2>
{
pep->status = 0x0000U;
801097e: 68bb ldr r3, [r7, #8]
8010980: 2200 movs r2, #0
8010982: 739a strb r2, [r3, #14]
8010984: e00e b.n 80109a4 <USBD_StdEPReq+0x300>
}
else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U)
8010986: 7bbb ldrb r3, [r7, #14]
8010988: 4619 mov r1, r3
801098a: 6878 ldr r0, [r7, #4]
801098c: f006 fe2c bl 80175e8 <USBD_LL_IsStallEP>
8010990: 4603 mov r3, r0
8010992: 2b00 cmp r3, #0
8010994: d003 beq.n 801099e <USBD_StdEPReq+0x2fa>
{
pep->status = 0x0001U;
8010996: 68bb ldr r3, [r7, #8]
8010998: 2201 movs r2, #1
801099a: 739a strb r2, [r3, #14]
801099c: e002 b.n 80109a4 <USBD_StdEPReq+0x300>
}
else
{
pep->status = 0x0000U;
801099e: 68bb ldr r3, [r7, #8]
80109a0: 2200 movs r2, #0
80109a2: 739a strb r2, [r3, #14]
}
(void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U);
80109a4: 68bb ldr r3, [r7, #8]
80109a6: 330e adds r3, #14
80109a8: 2202 movs r2, #2
80109aa: 4619 mov r1, r3
80109ac: 6878 ldr r0, [r7, #4]
80109ae: f000 fc07 bl 80111c0 <USBD_CtlSendData>
break;
80109b2: e004 b.n 80109be <USBD_StdEPReq+0x31a>
default:
USBD_CtlError(pdev, req);
80109b4: 6839 ldr r1, [r7, #0]
80109b6: 6878 ldr r0, [r7, #4]
80109b8: f000 fb85 bl 80110c6 <USBD_CtlError>
break;
80109bc: bf00 nop
}
break;
80109be: e004 b.n 80109ca <USBD_StdEPReq+0x326>
default:
USBD_CtlError(pdev, req);
80109c0: 6839 ldr r1, [r7, #0]
80109c2: 6878 ldr r0, [r7, #4]
80109c4: f000 fb7f bl 80110c6 <USBD_CtlError>
break;
80109c8: bf00 nop
}
break;
80109ca: e005 b.n 80109d8 <USBD_StdEPReq+0x334>
default:
USBD_CtlError(pdev, req);
80109cc: 6839 ldr r1, [r7, #0]
80109ce: 6878 ldr r0, [r7, #4]
80109d0: f000 fb79 bl 80110c6 <USBD_CtlError>
break;
80109d4: e000 b.n 80109d8 <USBD_StdEPReq+0x334>
break;
80109d6: bf00 nop
}
return ret;
80109d8: 7bfb ldrb r3, [r7, #15]
}
80109da: 4618 mov r0, r3
80109dc: 3710 adds r7, #16
80109de: 46bd mov sp, r7
80109e0: bd80 pop {r7, pc}
...
080109e4 <USBD_GetDescriptor>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80109e4: b580 push {r7, lr}
80109e6: b084 sub sp, #16
80109e8: af00 add r7, sp, #0
80109ea: 6078 str r0, [r7, #4]
80109ec: 6039 str r1, [r7, #0]
uint16_t len = 0U;
80109ee: 2300 movs r3, #0
80109f0: 813b strh r3, [r7, #8]
uint8_t *pbuf = NULL;
80109f2: 2300 movs r3, #0
80109f4: 60fb str r3, [r7, #12]
uint8_t err = 0U;
80109f6: 2300 movs r3, #0
80109f8: 72fb strb r3, [r7, #11]
switch (req->wValue >> 8)
80109fa: 683b ldr r3, [r7, #0]
80109fc: 885b ldrh r3, [r3, #2]
80109fe: 0a1b lsrs r3, r3, #8
8010a00: b29b uxth r3, r3
8010a02: 3b01 subs r3, #1
8010a04: 2b0e cmp r3, #14
8010a06: f200 8152 bhi.w 8010cae <USBD_GetDescriptor+0x2ca>
8010a0a: a201 add r2, pc, #4 @ (adr r2, 8010a10 <USBD_GetDescriptor+0x2c>)
8010a0c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8010a10: 08010a81 .word 0x08010a81
8010a14: 08010a99 .word 0x08010a99
8010a18: 08010ad9 .word 0x08010ad9
8010a1c: 08010caf .word 0x08010caf
8010a20: 08010caf .word 0x08010caf
8010a24: 08010c4f .word 0x08010c4f
8010a28: 08010c7b .word 0x08010c7b
8010a2c: 08010caf .word 0x08010caf
8010a30: 08010caf .word 0x08010caf
8010a34: 08010caf .word 0x08010caf
8010a38: 08010caf .word 0x08010caf
8010a3c: 08010caf .word 0x08010caf
8010a40: 08010caf .word 0x08010caf
8010a44: 08010caf .word 0x08010caf
8010a48: 08010a4d .word 0x08010a4d
{
#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U))
case USB_DESC_TYPE_BOS:
if (pdev->pDesc->GetBOSDescriptor != NULL)
8010a4c: 687b ldr r3, [r7, #4]
8010a4e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010a52: 69db ldr r3, [r3, #28]
8010a54: 2b00 cmp r3, #0
8010a56: d00b beq.n 8010a70 <USBD_GetDescriptor+0x8c>
{
pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
8010a58: 687b ldr r3, [r7, #4]
8010a5a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010a5e: 69db ldr r3, [r3, #28]
8010a60: 687a ldr r2, [r7, #4]
8010a62: 7c12 ldrb r2, [r2, #16]
8010a64: f107 0108 add.w r1, r7, #8
8010a68: 4610 mov r0, r2
8010a6a: 4798 blx r3
8010a6c: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010a6e: e126 b.n 8010cbe <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
8010a70: 6839 ldr r1, [r7, #0]
8010a72: 6878 ldr r0, [r7, #4]
8010a74: f000 fb27 bl 80110c6 <USBD_CtlError>
err++;
8010a78: 7afb ldrb r3, [r7, #11]
8010a7a: 3301 adds r3, #1
8010a7c: 72fb strb r3, [r7, #11]
break;
8010a7e: e11e b.n 8010cbe <USBD_GetDescriptor+0x2da>
#endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */
case USB_DESC_TYPE_DEVICE:
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
8010a80: 687b ldr r3, [r7, #4]
8010a82: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010a86: 681b ldr r3, [r3, #0]
8010a88: 687a ldr r2, [r7, #4]
8010a8a: 7c12 ldrb r2, [r2, #16]
8010a8c: f107 0108 add.w r1, r7, #8
8010a90: 4610 mov r0, r2
8010a92: 4798 blx r3
8010a94: 60f8 str r0, [r7, #12]
break;
8010a96: e112 b.n 8010cbe <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8010a98: 687b ldr r3, [r7, #4]
8010a9a: 7c1b ldrb r3, [r3, #16]
8010a9c: 2b00 cmp r3, #0
8010a9e: d10d bne.n 8010abc <USBD_GetDescriptor+0xd8>
pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len);
8010aa0: 687b ldr r3, [r7, #4]
8010aa2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8010aa6: 6a9b ldr r3, [r3, #40] @ 0x28
8010aa8: f107 0208 add.w r2, r7, #8
8010aac: 4610 mov r0, r2
8010aae: 4798 blx r3
8010ab0: 60f8 str r0, [r7, #12]
}
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
8010ab2: 68fb ldr r3, [r7, #12]
8010ab4: 3301 adds r3, #1
8010ab6: 2202 movs r2, #2
8010ab8: 701a strb r2, [r3, #0]
{
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
}
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
}
break;
8010aba: e100 b.n 8010cbe <USBD_GetDescriptor+0x2da>
pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len);
8010abc: 687b ldr r3, [r7, #4]
8010abe: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8010ac2: 6adb ldr r3, [r3, #44] @ 0x2c
8010ac4: f107 0208 add.w r2, r7, #8
8010ac8: 4610 mov r0, r2
8010aca: 4798 blx r3
8010acc: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
8010ace: 68fb ldr r3, [r7, #12]
8010ad0: 3301 adds r3, #1
8010ad2: 2202 movs r2, #2
8010ad4: 701a strb r2, [r3, #0]
break;
8010ad6: e0f2 b.n 8010cbe <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_STRING:
switch ((uint8_t)(req->wValue))
8010ad8: 683b ldr r3, [r7, #0]
8010ada: 885b ldrh r3, [r3, #2]
8010adc: b2db uxtb r3, r3
8010ade: 2b05 cmp r3, #5
8010ae0: f200 80ac bhi.w 8010c3c <USBD_GetDescriptor+0x258>
8010ae4: a201 add r2, pc, #4 @ (adr r2, 8010aec <USBD_GetDescriptor+0x108>)
8010ae6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8010aea: bf00 nop
8010aec: 08010b05 .word 0x08010b05
8010af0: 08010b39 .word 0x08010b39
8010af4: 08010b6d .word 0x08010b6d
8010af8: 08010ba1 .word 0x08010ba1
8010afc: 08010bd5 .word 0x08010bd5
8010b00: 08010c09 .word 0x08010c09
{
case USBD_IDX_LANGID_STR:
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
8010b04: 687b ldr r3, [r7, #4]
8010b06: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010b0a: 685b ldr r3, [r3, #4]
8010b0c: 2b00 cmp r3, #0
8010b0e: d00b beq.n 8010b28 <USBD_GetDescriptor+0x144>
{
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
8010b10: 687b ldr r3, [r7, #4]
8010b12: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010b16: 685b ldr r3, [r3, #4]
8010b18: 687a ldr r2, [r7, #4]
8010b1a: 7c12 ldrb r2, [r2, #16]
8010b1c: f107 0108 add.w r1, r7, #8
8010b20: 4610 mov r0, r2
8010b22: 4798 blx r3
8010b24: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010b26: e091 b.n 8010c4c <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8010b28: 6839 ldr r1, [r7, #0]
8010b2a: 6878 ldr r0, [r7, #4]
8010b2c: f000 facb bl 80110c6 <USBD_CtlError>
err++;
8010b30: 7afb ldrb r3, [r7, #11]
8010b32: 3301 adds r3, #1
8010b34: 72fb strb r3, [r7, #11]
break;
8010b36: e089 b.n 8010c4c <USBD_GetDescriptor+0x268>
case USBD_IDX_MFC_STR:
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
8010b38: 687b ldr r3, [r7, #4]
8010b3a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010b3e: 689b ldr r3, [r3, #8]
8010b40: 2b00 cmp r3, #0
8010b42: d00b beq.n 8010b5c <USBD_GetDescriptor+0x178>
{
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
8010b44: 687b ldr r3, [r7, #4]
8010b46: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010b4a: 689b ldr r3, [r3, #8]
8010b4c: 687a ldr r2, [r7, #4]
8010b4e: 7c12 ldrb r2, [r2, #16]
8010b50: f107 0108 add.w r1, r7, #8
8010b54: 4610 mov r0, r2
8010b56: 4798 blx r3
8010b58: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010b5a: e077 b.n 8010c4c <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8010b5c: 6839 ldr r1, [r7, #0]
8010b5e: 6878 ldr r0, [r7, #4]
8010b60: f000 fab1 bl 80110c6 <USBD_CtlError>
err++;
8010b64: 7afb ldrb r3, [r7, #11]
8010b66: 3301 adds r3, #1
8010b68: 72fb strb r3, [r7, #11]
break;
8010b6a: e06f b.n 8010c4c <USBD_GetDescriptor+0x268>
case USBD_IDX_PRODUCT_STR:
if (pdev->pDesc->GetProductStrDescriptor != NULL)
8010b6c: 687b ldr r3, [r7, #4]
8010b6e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010b72: 68db ldr r3, [r3, #12]
8010b74: 2b00 cmp r3, #0
8010b76: d00b beq.n 8010b90 <USBD_GetDescriptor+0x1ac>
{
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
8010b78: 687b ldr r3, [r7, #4]
8010b7a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010b7e: 68db ldr r3, [r3, #12]
8010b80: 687a ldr r2, [r7, #4]
8010b82: 7c12 ldrb r2, [r2, #16]
8010b84: f107 0108 add.w r1, r7, #8
8010b88: 4610 mov r0, r2
8010b8a: 4798 blx r3
8010b8c: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010b8e: e05d b.n 8010c4c <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8010b90: 6839 ldr r1, [r7, #0]
8010b92: 6878 ldr r0, [r7, #4]
8010b94: f000 fa97 bl 80110c6 <USBD_CtlError>
err++;
8010b98: 7afb ldrb r3, [r7, #11]
8010b9a: 3301 adds r3, #1
8010b9c: 72fb strb r3, [r7, #11]
break;
8010b9e: e055 b.n 8010c4c <USBD_GetDescriptor+0x268>
case USBD_IDX_SERIAL_STR:
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
8010ba0: 687b ldr r3, [r7, #4]
8010ba2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010ba6: 691b ldr r3, [r3, #16]
8010ba8: 2b00 cmp r3, #0
8010baa: d00b beq.n 8010bc4 <USBD_GetDescriptor+0x1e0>
{
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
8010bac: 687b ldr r3, [r7, #4]
8010bae: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010bb2: 691b ldr r3, [r3, #16]
8010bb4: 687a ldr r2, [r7, #4]
8010bb6: 7c12 ldrb r2, [r2, #16]
8010bb8: f107 0108 add.w r1, r7, #8
8010bbc: 4610 mov r0, r2
8010bbe: 4798 blx r3
8010bc0: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010bc2: e043 b.n 8010c4c <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8010bc4: 6839 ldr r1, [r7, #0]
8010bc6: 6878 ldr r0, [r7, #4]
8010bc8: f000 fa7d bl 80110c6 <USBD_CtlError>
err++;
8010bcc: 7afb ldrb r3, [r7, #11]
8010bce: 3301 adds r3, #1
8010bd0: 72fb strb r3, [r7, #11]
break;
8010bd2: e03b b.n 8010c4c <USBD_GetDescriptor+0x268>
case USBD_IDX_CONFIG_STR:
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
8010bd4: 687b ldr r3, [r7, #4]
8010bd6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010bda: 695b ldr r3, [r3, #20]
8010bdc: 2b00 cmp r3, #0
8010bde: d00b beq.n 8010bf8 <USBD_GetDescriptor+0x214>
{
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
8010be0: 687b ldr r3, [r7, #4]
8010be2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010be6: 695b ldr r3, [r3, #20]
8010be8: 687a ldr r2, [r7, #4]
8010bea: 7c12 ldrb r2, [r2, #16]
8010bec: f107 0108 add.w r1, r7, #8
8010bf0: 4610 mov r0, r2
8010bf2: 4798 blx r3
8010bf4: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010bf6: e029 b.n 8010c4c <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8010bf8: 6839 ldr r1, [r7, #0]
8010bfa: 6878 ldr r0, [r7, #4]
8010bfc: f000 fa63 bl 80110c6 <USBD_CtlError>
err++;
8010c00: 7afb ldrb r3, [r7, #11]
8010c02: 3301 adds r3, #1
8010c04: 72fb strb r3, [r7, #11]
break;
8010c06: e021 b.n 8010c4c <USBD_GetDescriptor+0x268>
case USBD_IDX_INTERFACE_STR:
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
8010c08: 687b ldr r3, [r7, #4]
8010c0a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010c0e: 699b ldr r3, [r3, #24]
8010c10: 2b00 cmp r3, #0
8010c12: d00b beq.n 8010c2c <USBD_GetDescriptor+0x248>
{
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
8010c14: 687b ldr r3, [r7, #4]
8010c16: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4
8010c1a: 699b ldr r3, [r3, #24]
8010c1c: 687a ldr r2, [r7, #4]
8010c1e: 7c12 ldrb r2, [r2, #16]
8010c20: f107 0108 add.w r1, r7, #8
8010c24: 4610 mov r0, r2
8010c26: 4798 blx r3
8010c28: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010c2a: e00f b.n 8010c4c <USBD_GetDescriptor+0x268>
USBD_CtlError(pdev, req);
8010c2c: 6839 ldr r1, [r7, #0]
8010c2e: 6878 ldr r0, [r7, #4]
8010c30: f000 fa49 bl 80110c6 <USBD_CtlError>
err++;
8010c34: 7afb ldrb r3, [r7, #11]
8010c36: 3301 adds r3, #1
8010c38: 72fb strb r3, [r7, #11]
break;
8010c3a: e007 b.n 8010c4c <USBD_GetDescriptor+0x268>
err++;
}
#endif /* USBD_SUPPORT_USER_STRING_DESC */
#if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U))
USBD_CtlError(pdev, req);
8010c3c: 6839 ldr r1, [r7, #0]
8010c3e: 6878 ldr r0, [r7, #4]
8010c40: f000 fa41 bl 80110c6 <USBD_CtlError>
err++;
8010c44: 7afb ldrb r3, [r7, #11]
8010c46: 3301 adds r3, #1
8010c48: 72fb strb r3, [r7, #11]
#endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */
break;
8010c4a: bf00 nop
}
break;
8010c4c: e037 b.n 8010cbe <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_DEVICE_QUALIFIER:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8010c4e: 687b ldr r3, [r7, #4]
8010c50: 7c1b ldrb r3, [r3, #16]
8010c52: 2b00 cmp r3, #0
8010c54: d109 bne.n 8010c6a <USBD_GetDescriptor+0x286>
pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len);
8010c56: 687b ldr r3, [r7, #4]
8010c58: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8010c5c: 6b5b ldr r3, [r3, #52] @ 0x34
8010c5e: f107 0208 add.w r2, r7, #8
8010c62: 4610 mov r0, r2
8010c64: 4798 blx r3
8010c66: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010c68: e029 b.n 8010cbe <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
8010c6a: 6839 ldr r1, [r7, #0]
8010c6c: 6878 ldr r0, [r7, #4]
8010c6e: f000 fa2a bl 80110c6 <USBD_CtlError>
err++;
8010c72: 7afb ldrb r3, [r7, #11]
8010c74: 3301 adds r3, #1
8010c76: 72fb strb r3, [r7, #11]
break;
8010c78: e021 b.n 8010cbe <USBD_GetDescriptor+0x2da>
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8010c7a: 687b ldr r3, [r7, #4]
8010c7c: 7c1b ldrb r3, [r3, #16]
8010c7e: 2b00 cmp r3, #0
8010c80: d10d bne.n 8010c9e <USBD_GetDescriptor+0x2ba>
pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len);
}
else
#endif /* USE_USBD_COMPOSITE */
{
pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len);
8010c82: 687b ldr r3, [r7, #4]
8010c84: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8
8010c88: 6b1b ldr r3, [r3, #48] @ 0x30
8010c8a: f107 0208 add.w r2, r7, #8
8010c8e: 4610 mov r0, r2
8010c90: 4798 blx r3
8010c92: 60f8 str r0, [r7, #12]
}
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
8010c94: 68fb ldr r3, [r7, #12]
8010c96: 3301 adds r3, #1
8010c98: 2207 movs r2, #7
8010c9a: 701a strb r2, [r3, #0]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8010c9c: e00f b.n 8010cbe <USBD_GetDescriptor+0x2da>
USBD_CtlError(pdev, req);
8010c9e: 6839 ldr r1, [r7, #0]
8010ca0: 6878 ldr r0, [r7, #4]
8010ca2: f000 fa10 bl 80110c6 <USBD_CtlError>
err++;
8010ca6: 7afb ldrb r3, [r7, #11]
8010ca8: 3301 adds r3, #1
8010caa: 72fb strb r3, [r7, #11]
break;
8010cac: e007 b.n 8010cbe <USBD_GetDescriptor+0x2da>
default:
USBD_CtlError(pdev, req);
8010cae: 6839 ldr r1, [r7, #0]
8010cb0: 6878 ldr r0, [r7, #4]
8010cb2: f000 fa08 bl 80110c6 <USBD_CtlError>
err++;
8010cb6: 7afb ldrb r3, [r7, #11]
8010cb8: 3301 adds r3, #1
8010cba: 72fb strb r3, [r7, #11]
break;
8010cbc: bf00 nop
}
if (err != 0U)
8010cbe: 7afb ldrb r3, [r7, #11]
8010cc0: 2b00 cmp r3, #0
8010cc2: d11e bne.n 8010d02 <USBD_GetDescriptor+0x31e>
{
return;
}
if (req->wLength != 0U)
8010cc4: 683b ldr r3, [r7, #0]
8010cc6: 88db ldrh r3, [r3, #6]
8010cc8: 2b00 cmp r3, #0
8010cca: d016 beq.n 8010cfa <USBD_GetDescriptor+0x316>
{
if (len != 0U)
8010ccc: 893b ldrh r3, [r7, #8]
8010cce: 2b00 cmp r3, #0
8010cd0: d00e beq.n 8010cf0 <USBD_GetDescriptor+0x30c>
{
len = MIN(len, req->wLength);
8010cd2: 683b ldr r3, [r7, #0]
8010cd4: 88da ldrh r2, [r3, #6]
8010cd6: 893b ldrh r3, [r7, #8]
8010cd8: 4293 cmp r3, r2
8010cda: bf28 it cs
8010cdc: 4613 movcs r3, r2
8010cde: b29b uxth r3, r3
8010ce0: 813b strh r3, [r7, #8]
(void)USBD_CtlSendData(pdev, pbuf, len);
8010ce2: 893b ldrh r3, [r7, #8]
8010ce4: 461a mov r2, r3
8010ce6: 68f9 ldr r1, [r7, #12]
8010ce8: 6878 ldr r0, [r7, #4]
8010cea: f000 fa69 bl 80111c0 <USBD_CtlSendData>
8010cee: e009 b.n 8010d04 <USBD_GetDescriptor+0x320>
}
else
{
USBD_CtlError(pdev, req);
8010cf0: 6839 ldr r1, [r7, #0]
8010cf2: 6878 ldr r0, [r7, #4]
8010cf4: f000 f9e7 bl 80110c6 <USBD_CtlError>
8010cf8: e004 b.n 8010d04 <USBD_GetDescriptor+0x320>
}
}
else
{
(void)USBD_CtlSendStatus(pdev);
8010cfa: 6878 ldr r0, [r7, #4]
8010cfc: f000 fac1 bl 8011282 <USBD_CtlSendStatus>
8010d00: e000 b.n 8010d04 <USBD_GetDescriptor+0x320>
return;
8010d02: bf00 nop
}
}
8010d04: 3710 adds r7, #16
8010d06: 46bd mov sp, r7
8010d08: bd80 pop {r7, pc}
8010d0a: bf00 nop
08010d0c <USBD_SetAddress>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8010d0c: b580 push {r7, lr}
8010d0e: b084 sub sp, #16
8010d10: af00 add r7, sp, #0
8010d12: 6078 str r0, [r7, #4]
8010d14: 6039 str r1, [r7, #0]
uint8_t dev_addr;
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
8010d16: 683b ldr r3, [r7, #0]
8010d18: 889b ldrh r3, [r3, #4]
8010d1a: 2b00 cmp r3, #0
8010d1c: d131 bne.n 8010d82 <USBD_SetAddress+0x76>
8010d1e: 683b ldr r3, [r7, #0]
8010d20: 88db ldrh r3, [r3, #6]
8010d22: 2b00 cmp r3, #0
8010d24: d12d bne.n 8010d82 <USBD_SetAddress+0x76>
8010d26: 683b ldr r3, [r7, #0]
8010d28: 885b ldrh r3, [r3, #2]
8010d2a: 2b7f cmp r3, #127 @ 0x7f
8010d2c: d829 bhi.n 8010d82 <USBD_SetAddress+0x76>
{
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
8010d2e: 683b ldr r3, [r7, #0]
8010d30: 885b ldrh r3, [r3, #2]
8010d32: b2db uxtb r3, r3
8010d34: f003 037f and.w r3, r3, #127 @ 0x7f
8010d38: 73fb strb r3, [r7, #15]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8010d3a: 687b ldr r3, [r7, #4]
8010d3c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010d40: b2db uxtb r3, r3
8010d42: 2b03 cmp r3, #3
8010d44: d104 bne.n 8010d50 <USBD_SetAddress+0x44>
{
USBD_CtlError(pdev, req);
8010d46: 6839 ldr r1, [r7, #0]
8010d48: 6878 ldr r0, [r7, #4]
8010d4a: f000 f9bc bl 80110c6 <USBD_CtlError>
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8010d4e: e01d b.n 8010d8c <USBD_SetAddress+0x80>
}
else
{
pdev->dev_address = dev_addr;
8010d50: 687b ldr r3, [r7, #4]
8010d52: 7bfa ldrb r2, [r7, #15]
8010d54: f883 229e strb.w r2, [r3, #670] @ 0x29e
(void)USBD_LL_SetUSBAddress(pdev, dev_addr);
8010d58: 7bfb ldrb r3, [r7, #15]
8010d5a: 4619 mov r1, r3
8010d5c: 6878 ldr r0, [r7, #4]
8010d5e: f006 fc6f bl 8017640 <USBD_LL_SetUSBAddress>
(void)USBD_CtlSendStatus(pdev);
8010d62: 6878 ldr r0, [r7, #4]
8010d64: f000 fa8d bl 8011282 <USBD_CtlSendStatus>
if (dev_addr != 0U)
8010d68: 7bfb ldrb r3, [r7, #15]
8010d6a: 2b00 cmp r3, #0
8010d6c: d004 beq.n 8010d78 <USBD_SetAddress+0x6c>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
8010d6e: 687b ldr r3, [r7, #4]
8010d70: 2202 movs r2, #2
8010d72: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8010d76: e009 b.n 8010d8c <USBD_SetAddress+0x80>
}
else
{
pdev->dev_state = USBD_STATE_DEFAULT;
8010d78: 687b ldr r3, [r7, #4]
8010d7a: 2201 movs r2, #1
8010d7c: f883 229c strb.w r2, [r3, #668] @ 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8010d80: e004 b.n 8010d8c <USBD_SetAddress+0x80>
}
}
}
else
{
USBD_CtlError(pdev, req);
8010d82: 6839 ldr r1, [r7, #0]
8010d84: 6878 ldr r0, [r7, #4]
8010d86: f000 f99e bl 80110c6 <USBD_CtlError>
}
}
8010d8a: bf00 nop
8010d8c: bf00 nop
8010d8e: 3710 adds r7, #16
8010d90: 46bd mov sp, r7
8010d92: bd80 pop {r7, pc}
08010d94 <USBD_SetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8010d94: b580 push {r7, lr}
8010d96: b084 sub sp, #16
8010d98: af00 add r7, sp, #0
8010d9a: 6078 str r0, [r7, #4]
8010d9c: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8010d9e: 2300 movs r3, #0
8010da0: 73fb strb r3, [r7, #15]
static uint8_t cfgidx;
cfgidx = (uint8_t)(req->wValue);
8010da2: 683b ldr r3, [r7, #0]
8010da4: 885b ldrh r3, [r3, #2]
8010da6: b2da uxtb r2, r3
8010da8: 4b4e ldr r3, [pc, #312] @ (8010ee4 <USBD_SetConfig+0x150>)
8010daa: 701a strb r2, [r3, #0]
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
8010dac: 4b4d ldr r3, [pc, #308] @ (8010ee4 <USBD_SetConfig+0x150>)
8010dae: 781b ldrb r3, [r3, #0]
8010db0: 2b01 cmp r3, #1
8010db2: d905 bls.n 8010dc0 <USBD_SetConfig+0x2c>
{
USBD_CtlError(pdev, req);
8010db4: 6839 ldr r1, [r7, #0]
8010db6: 6878 ldr r0, [r7, #4]
8010db8: f000 f985 bl 80110c6 <USBD_CtlError>
return USBD_FAIL;
8010dbc: 2303 movs r3, #3
8010dbe: e08c b.n 8010eda <USBD_SetConfig+0x146>
}
switch (pdev->dev_state)
8010dc0: 687b ldr r3, [r7, #4]
8010dc2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010dc6: b2db uxtb r3, r3
8010dc8: 2b02 cmp r3, #2
8010dca: d002 beq.n 8010dd2 <USBD_SetConfig+0x3e>
8010dcc: 2b03 cmp r3, #3
8010dce: d029 beq.n 8010e24 <USBD_SetConfig+0x90>
8010dd0: e075 b.n 8010ebe <USBD_SetConfig+0x12a>
{
case USBD_STATE_ADDRESSED:
if (cfgidx != 0U)
8010dd2: 4b44 ldr r3, [pc, #272] @ (8010ee4 <USBD_SetConfig+0x150>)
8010dd4: 781b ldrb r3, [r3, #0]
8010dd6: 2b00 cmp r3, #0
8010dd8: d020 beq.n 8010e1c <USBD_SetConfig+0x88>
{
pdev->dev_config = cfgidx;
8010dda: 4b42 ldr r3, [pc, #264] @ (8010ee4 <USBD_SetConfig+0x150>)
8010ddc: 781b ldrb r3, [r3, #0]
8010dde: 461a mov r2, r3
8010de0: 687b ldr r3, [r7, #4]
8010de2: 605a str r2, [r3, #4]
ret = USBD_SetClassConfig(pdev, cfgidx);
8010de4: 4b3f ldr r3, [pc, #252] @ (8010ee4 <USBD_SetConfig+0x150>)
8010de6: 781b ldrb r3, [r3, #0]
8010de8: 4619 mov r1, r3
8010dea: 6878 ldr r0, [r7, #4]
8010dec: f7ff f835 bl 800fe5a <USBD_SetClassConfig>
8010df0: 4603 mov r3, r0
8010df2: 73fb strb r3, [r7, #15]
if (ret != USBD_OK)
8010df4: 7bfb ldrb r3, [r7, #15]
8010df6: 2b00 cmp r3, #0
8010df8: d008 beq.n 8010e0c <USBD_SetConfig+0x78>
{
USBD_CtlError(pdev, req);
8010dfa: 6839 ldr r1, [r7, #0]
8010dfc: 6878 ldr r0, [r7, #4]
8010dfe: f000 f962 bl 80110c6 <USBD_CtlError>
pdev->dev_state = USBD_STATE_ADDRESSED;
8010e02: 687b ldr r3, [r7, #4]
8010e04: 2202 movs r2, #2
8010e06: f883 229c strb.w r2, [r3, #668] @ 0x29c
}
else
{
(void)USBD_CtlSendStatus(pdev);
}
break;
8010e0a: e065 b.n 8010ed8 <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
8010e0c: 6878 ldr r0, [r7, #4]
8010e0e: f000 fa38 bl 8011282 <USBD_CtlSendStatus>
pdev->dev_state = USBD_STATE_CONFIGURED;
8010e12: 687b ldr r3, [r7, #4]
8010e14: 2203 movs r2, #3
8010e16: f883 229c strb.w r2, [r3, #668] @ 0x29c
break;
8010e1a: e05d b.n 8010ed8 <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
8010e1c: 6878 ldr r0, [r7, #4]
8010e1e: f000 fa30 bl 8011282 <USBD_CtlSendStatus>
break;
8010e22: e059 b.n 8010ed8 <USBD_SetConfig+0x144>
case USBD_STATE_CONFIGURED:
if (cfgidx == 0U)
8010e24: 4b2f ldr r3, [pc, #188] @ (8010ee4 <USBD_SetConfig+0x150>)
8010e26: 781b ldrb r3, [r3, #0]
8010e28: 2b00 cmp r3, #0
8010e2a: d112 bne.n 8010e52 <USBD_SetConfig+0xbe>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
8010e2c: 687b ldr r3, [r7, #4]
8010e2e: 2202 movs r2, #2
8010e30: f883 229c strb.w r2, [r3, #668] @ 0x29c
pdev->dev_config = cfgidx;
8010e34: 4b2b ldr r3, [pc, #172] @ (8010ee4 <USBD_SetConfig+0x150>)
8010e36: 781b ldrb r3, [r3, #0]
8010e38: 461a mov r2, r3
8010e3a: 687b ldr r3, [r7, #4]
8010e3c: 605a str r2, [r3, #4]
(void)USBD_ClrClassConfig(pdev, cfgidx);
8010e3e: 4b29 ldr r3, [pc, #164] @ (8010ee4 <USBD_SetConfig+0x150>)
8010e40: 781b ldrb r3, [r3, #0]
8010e42: 4619 mov r1, r3
8010e44: 6878 ldr r0, [r7, #4]
8010e46: f7ff f824 bl 800fe92 <USBD_ClrClassConfig>
(void)USBD_CtlSendStatus(pdev);
8010e4a: 6878 ldr r0, [r7, #4]
8010e4c: f000 fa19 bl 8011282 <USBD_CtlSendStatus>
}
else
{
(void)USBD_CtlSendStatus(pdev);
}
break;
8010e50: e042 b.n 8010ed8 <USBD_SetConfig+0x144>
else if (cfgidx != pdev->dev_config)
8010e52: 4b24 ldr r3, [pc, #144] @ (8010ee4 <USBD_SetConfig+0x150>)
8010e54: 781b ldrb r3, [r3, #0]
8010e56: 461a mov r2, r3
8010e58: 687b ldr r3, [r7, #4]
8010e5a: 685b ldr r3, [r3, #4]
8010e5c: 429a cmp r2, r3
8010e5e: d02a beq.n 8010eb6 <USBD_SetConfig+0x122>
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
8010e60: 687b ldr r3, [r7, #4]
8010e62: 685b ldr r3, [r3, #4]
8010e64: b2db uxtb r3, r3
8010e66: 4619 mov r1, r3
8010e68: 6878 ldr r0, [r7, #4]
8010e6a: f7ff f812 bl 800fe92 <USBD_ClrClassConfig>
pdev->dev_config = cfgidx;
8010e6e: 4b1d ldr r3, [pc, #116] @ (8010ee4 <USBD_SetConfig+0x150>)
8010e70: 781b ldrb r3, [r3, #0]
8010e72: 461a mov r2, r3
8010e74: 687b ldr r3, [r7, #4]
8010e76: 605a str r2, [r3, #4]
ret = USBD_SetClassConfig(pdev, cfgidx);
8010e78: 4b1a ldr r3, [pc, #104] @ (8010ee4 <USBD_SetConfig+0x150>)
8010e7a: 781b ldrb r3, [r3, #0]
8010e7c: 4619 mov r1, r3
8010e7e: 6878 ldr r0, [r7, #4]
8010e80: f7fe ffeb bl 800fe5a <USBD_SetClassConfig>
8010e84: 4603 mov r3, r0
8010e86: 73fb strb r3, [r7, #15]
if (ret != USBD_OK)
8010e88: 7bfb ldrb r3, [r7, #15]
8010e8a: 2b00 cmp r3, #0
8010e8c: d00f beq.n 8010eae <USBD_SetConfig+0x11a>
USBD_CtlError(pdev, req);
8010e8e: 6839 ldr r1, [r7, #0]
8010e90: 6878 ldr r0, [r7, #4]
8010e92: f000 f918 bl 80110c6 <USBD_CtlError>
(void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
8010e96: 687b ldr r3, [r7, #4]
8010e98: 685b ldr r3, [r3, #4]
8010e9a: b2db uxtb r3, r3
8010e9c: 4619 mov r1, r3
8010e9e: 6878 ldr r0, [r7, #4]
8010ea0: f7fe fff7 bl 800fe92 <USBD_ClrClassConfig>
pdev->dev_state = USBD_STATE_ADDRESSED;
8010ea4: 687b ldr r3, [r7, #4]
8010ea6: 2202 movs r2, #2
8010ea8: f883 229c strb.w r2, [r3, #668] @ 0x29c
break;
8010eac: e014 b.n 8010ed8 <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
8010eae: 6878 ldr r0, [r7, #4]
8010eb0: f000 f9e7 bl 8011282 <USBD_CtlSendStatus>
break;
8010eb4: e010 b.n 8010ed8 <USBD_SetConfig+0x144>
(void)USBD_CtlSendStatus(pdev);
8010eb6: 6878 ldr r0, [r7, #4]
8010eb8: f000 f9e3 bl 8011282 <USBD_CtlSendStatus>
break;
8010ebc: e00c b.n 8010ed8 <USBD_SetConfig+0x144>
default:
USBD_CtlError(pdev, req);
8010ebe: 6839 ldr r1, [r7, #0]
8010ec0: 6878 ldr r0, [r7, #4]
8010ec2: f000 f900 bl 80110c6 <USBD_CtlError>
(void)USBD_ClrClassConfig(pdev, cfgidx);
8010ec6: 4b07 ldr r3, [pc, #28] @ (8010ee4 <USBD_SetConfig+0x150>)
8010ec8: 781b ldrb r3, [r3, #0]
8010eca: 4619 mov r1, r3
8010ecc: 6878 ldr r0, [r7, #4]
8010ece: f7fe ffe0 bl 800fe92 <USBD_ClrClassConfig>
ret = USBD_FAIL;
8010ed2: 2303 movs r3, #3
8010ed4: 73fb strb r3, [r7, #15]
break;
8010ed6: bf00 nop
}
return ret;
8010ed8: 7bfb ldrb r3, [r7, #15]
}
8010eda: 4618 mov r0, r3
8010edc: 3710 adds r7, #16
8010ede: 46bd mov sp, r7
8010ee0: bd80 pop {r7, pc}
8010ee2: bf00 nop
8010ee4: 20000784 .word 0x20000784
08010ee8 <USBD_GetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8010ee8: b580 push {r7, lr}
8010eea: b082 sub sp, #8
8010eec: af00 add r7, sp, #0
8010eee: 6078 str r0, [r7, #4]
8010ef0: 6039 str r1, [r7, #0]
if (req->wLength != 1U)
8010ef2: 683b ldr r3, [r7, #0]
8010ef4: 88db ldrh r3, [r3, #6]
8010ef6: 2b01 cmp r3, #1
8010ef8: d004 beq.n 8010f04 <USBD_GetConfig+0x1c>
{
USBD_CtlError(pdev, req);
8010efa: 6839 ldr r1, [r7, #0]
8010efc: 6878 ldr r0, [r7, #4]
8010efe: f000 f8e2 bl 80110c6 <USBD_CtlError>
default:
USBD_CtlError(pdev, req);
break;
}
}
}
8010f02: e023 b.n 8010f4c <USBD_GetConfig+0x64>
switch (pdev->dev_state)
8010f04: 687b ldr r3, [r7, #4]
8010f06: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010f0a: b2db uxtb r3, r3
8010f0c: 2b02 cmp r3, #2
8010f0e: dc02 bgt.n 8010f16 <USBD_GetConfig+0x2e>
8010f10: 2b00 cmp r3, #0
8010f12: dc03 bgt.n 8010f1c <USBD_GetConfig+0x34>
8010f14: e015 b.n 8010f42 <USBD_GetConfig+0x5a>
8010f16: 2b03 cmp r3, #3
8010f18: d00b beq.n 8010f32 <USBD_GetConfig+0x4a>
8010f1a: e012 b.n 8010f42 <USBD_GetConfig+0x5a>
pdev->dev_default_config = 0U;
8010f1c: 687b ldr r3, [r7, #4]
8010f1e: 2200 movs r2, #0
8010f20: 609a str r2, [r3, #8]
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U);
8010f22: 687b ldr r3, [r7, #4]
8010f24: 3308 adds r3, #8
8010f26: 2201 movs r2, #1
8010f28: 4619 mov r1, r3
8010f2a: 6878 ldr r0, [r7, #4]
8010f2c: f000 f948 bl 80111c0 <USBD_CtlSendData>
break;
8010f30: e00c b.n 8010f4c <USBD_GetConfig+0x64>
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U);
8010f32: 687b ldr r3, [r7, #4]
8010f34: 3304 adds r3, #4
8010f36: 2201 movs r2, #1
8010f38: 4619 mov r1, r3
8010f3a: 6878 ldr r0, [r7, #4]
8010f3c: f000 f940 bl 80111c0 <USBD_CtlSendData>
break;
8010f40: e004 b.n 8010f4c <USBD_GetConfig+0x64>
USBD_CtlError(pdev, req);
8010f42: 6839 ldr r1, [r7, #0]
8010f44: 6878 ldr r0, [r7, #4]
8010f46: f000 f8be bl 80110c6 <USBD_CtlError>
break;
8010f4a: bf00 nop
}
8010f4c: bf00 nop
8010f4e: 3708 adds r7, #8
8010f50: 46bd mov sp, r7
8010f52: bd80 pop {r7, pc}
08010f54 <USBD_GetStatus>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8010f54: b580 push {r7, lr}
8010f56: b082 sub sp, #8
8010f58: af00 add r7, sp, #0
8010f5a: 6078 str r0, [r7, #4]
8010f5c: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
8010f5e: 687b ldr r3, [r7, #4]
8010f60: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
8010f64: b2db uxtb r3, r3
8010f66: 3b01 subs r3, #1
8010f68: 2b02 cmp r3, #2
8010f6a: d81e bhi.n 8010faa <USBD_GetStatus+0x56>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wLength != 0x2U)
8010f6c: 683b ldr r3, [r7, #0]
8010f6e: 88db ldrh r3, [r3, #6]
8010f70: 2b02 cmp r3, #2
8010f72: d004 beq.n 8010f7e <USBD_GetStatus+0x2a>
{
USBD_CtlError(pdev, req);
8010f74: 6839 ldr r1, [r7, #0]
8010f76: 6878 ldr r0, [r7, #4]
8010f78: f000 f8a5 bl 80110c6 <USBD_CtlError>
break;
8010f7c: e01a b.n 8010fb4 <USBD_GetStatus+0x60>
}
#if (USBD_SELF_POWERED == 1U)
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
8010f7e: 687b ldr r3, [r7, #4]
8010f80: 2201 movs r2, #1
8010f82: 60da str r2, [r3, #12]
#else
pdev->dev_config_status = 0U;
#endif /* USBD_SELF_POWERED */
if (pdev->dev_remote_wakeup != 0U)
8010f84: 687b ldr r3, [r7, #4]
8010f86: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4
8010f8a: 2b00 cmp r3, #0
8010f8c: d005 beq.n 8010f9a <USBD_GetStatus+0x46>
{
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
8010f8e: 687b ldr r3, [r7, #4]
8010f90: 68db ldr r3, [r3, #12]
8010f92: f043 0202 orr.w r2, r3, #2
8010f96: 687b ldr r3, [r7, #4]
8010f98: 60da str r2, [r3, #12]
}
(void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U);
8010f9a: 687b ldr r3, [r7, #4]
8010f9c: 330c adds r3, #12
8010f9e: 2202 movs r2, #2
8010fa0: 4619 mov r1, r3
8010fa2: 6878 ldr r0, [r7, #4]
8010fa4: f000 f90c bl 80111c0 <USBD_CtlSendData>
break;
8010fa8: e004 b.n 8010fb4 <USBD_GetStatus+0x60>
default:
USBD_CtlError(pdev, req);
8010faa: 6839 ldr r1, [r7, #0]
8010fac: 6878 ldr r0, [r7, #4]
8010fae: f000 f88a bl 80110c6 <USBD_CtlError>
break;
8010fb2: bf00 nop
}
}
8010fb4: bf00 nop
8010fb6: 3708 adds r7, #8
8010fb8: 46bd mov sp, r7
8010fba: bd80 pop {r7, pc}
08010fbc <USBD_SetFeature>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8010fbc: b580 push {r7, lr}
8010fbe: b082 sub sp, #8
8010fc0: af00 add r7, sp, #0
8010fc2: 6078 str r0, [r7, #4]
8010fc4: 6039 str r1, [r7, #0]
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
8010fc6: 683b ldr r3, [r7, #0]
8010fc8: 885b ldrh r3, [r3, #2]
8010fca: 2b01 cmp r3, #1
8010fcc: d107 bne.n 8010fde <USBD_SetFeature+0x22>
{
pdev->dev_remote_wakeup = 1U;
8010fce: 687b ldr r3, [r7, #4]
8010fd0: 2201 movs r2, #1
8010fd2: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
(void)USBD_CtlSendStatus(pdev);
8010fd6: 6878 ldr r0, [r7, #4]
8010fd8: f000 f953 bl 8011282 <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
}
8010fdc: e013 b.n 8011006 <USBD_SetFeature+0x4a>
else if (req->wValue == USB_FEATURE_TEST_MODE)
8010fde: 683b ldr r3, [r7, #0]
8010fe0: 885b ldrh r3, [r3, #2]
8010fe2: 2b02 cmp r3, #2
8010fe4: d10b bne.n 8010ffe <USBD_SetFeature+0x42>
pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8);
8010fe6: 683b ldr r3, [r7, #0]
8010fe8: 889b ldrh r3, [r3, #4]
8010fea: 0a1b lsrs r3, r3, #8
8010fec: b29b uxth r3, r3
8010fee: b2da uxtb r2, r3
8010ff0: 687b ldr r3, [r7, #4]
8010ff2: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0
(void)USBD_CtlSendStatus(pdev);
8010ff6: 6878 ldr r0, [r7, #4]
8010ff8: f000 f943 bl 8011282 <USBD_CtlSendStatus>
}
8010ffc: e003 b.n 8011006 <USBD_SetFeature+0x4a>
USBD_CtlError(pdev, req);
8010ffe: 6839 ldr r1, [r7, #0]
8011000: 6878 ldr r0, [r7, #4]
8011002: f000 f860 bl 80110c6 <USBD_CtlError>
}
8011006: bf00 nop
8011008: 3708 adds r7, #8
801100a: 46bd mov sp, r7
801100c: bd80 pop {r7, pc}
0801100e <USBD_ClrFeature>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
801100e: b580 push {r7, lr}
8011010: b082 sub sp, #8
8011012: af00 add r7, sp, #0
8011014: 6078 str r0, [r7, #4]
8011016: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
8011018: 687b ldr r3, [r7, #4]
801101a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c
801101e: b2db uxtb r3, r3
8011020: 3b01 subs r3, #1
8011022: 2b02 cmp r3, #2
8011024: d80b bhi.n 801103e <USBD_ClrFeature+0x30>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
8011026: 683b ldr r3, [r7, #0]
8011028: 885b ldrh r3, [r3, #2]
801102a: 2b01 cmp r3, #1
801102c: d10c bne.n 8011048 <USBD_ClrFeature+0x3a>
{
pdev->dev_remote_wakeup = 0U;
801102e: 687b ldr r3, [r7, #4]
8011030: 2200 movs r2, #0
8011032: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4
(void)USBD_CtlSendStatus(pdev);
8011036: 6878 ldr r0, [r7, #4]
8011038: f000 f923 bl 8011282 <USBD_CtlSendStatus>
}
break;
801103c: e004 b.n 8011048 <USBD_ClrFeature+0x3a>
default:
USBD_CtlError(pdev, req);
801103e: 6839 ldr r1, [r7, #0]
8011040: 6878 ldr r0, [r7, #4]
8011042: f000 f840 bl 80110c6 <USBD_CtlError>
break;
8011046: e000 b.n 801104a <USBD_ClrFeature+0x3c>
break;
8011048: bf00 nop
}
}
801104a: bf00 nop
801104c: 3708 adds r7, #8
801104e: 46bd mov sp, r7
8011050: bd80 pop {r7, pc}
08011052 <USBD_ParseSetupRequest>:
* @param req: usb request
* @param pdata: setup data pointer
* @retval None
*/
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
{
8011052: b580 push {r7, lr}
8011054: b084 sub sp, #16
8011056: af00 add r7, sp, #0
8011058: 6078 str r0, [r7, #4]
801105a: 6039 str r1, [r7, #0]
uint8_t *pbuff = pdata;
801105c: 683b ldr r3, [r7, #0]
801105e: 60fb str r3, [r7, #12]
req->bmRequest = *(uint8_t *)(pbuff);
8011060: 68fb ldr r3, [r7, #12]
8011062: 781a ldrb r2, [r3, #0]
8011064: 687b ldr r3, [r7, #4]
8011066: 701a strb r2, [r3, #0]
pbuff++;
8011068: 68fb ldr r3, [r7, #12]
801106a: 3301 adds r3, #1
801106c: 60fb str r3, [r7, #12]
req->bRequest = *(uint8_t *)(pbuff);
801106e: 68fb ldr r3, [r7, #12]
8011070: 781a ldrb r2, [r3, #0]
8011072: 687b ldr r3, [r7, #4]
8011074: 705a strb r2, [r3, #1]
pbuff++;
8011076: 68fb ldr r3, [r7, #12]
8011078: 3301 adds r3, #1
801107a: 60fb str r3, [r7, #12]
req->wValue = SWAPBYTE(pbuff);
801107c: 68f8 ldr r0, [r7, #12]
801107e: f7ff fa13 bl 80104a8 <SWAPBYTE>
8011082: 4603 mov r3, r0
8011084: 461a mov r2, r3
8011086: 687b ldr r3, [r7, #4]
8011088: 805a strh r2, [r3, #2]
pbuff++;
801108a: 68fb ldr r3, [r7, #12]
801108c: 3301 adds r3, #1
801108e: 60fb str r3, [r7, #12]
pbuff++;
8011090: 68fb ldr r3, [r7, #12]
8011092: 3301 adds r3, #1
8011094: 60fb str r3, [r7, #12]
req->wIndex = SWAPBYTE(pbuff);
8011096: 68f8 ldr r0, [r7, #12]
8011098: f7ff fa06 bl 80104a8 <SWAPBYTE>
801109c: 4603 mov r3, r0
801109e: 461a mov r2, r3
80110a0: 687b ldr r3, [r7, #4]
80110a2: 809a strh r2, [r3, #4]
pbuff++;
80110a4: 68fb ldr r3, [r7, #12]
80110a6: 3301 adds r3, #1
80110a8: 60fb str r3, [r7, #12]
pbuff++;
80110aa: 68fb ldr r3, [r7, #12]
80110ac: 3301 adds r3, #1
80110ae: 60fb str r3, [r7, #12]
req->wLength = SWAPBYTE(pbuff);
80110b0: 68f8 ldr r0, [r7, #12]
80110b2: f7ff f9f9 bl 80104a8 <SWAPBYTE>
80110b6: 4603 mov r3, r0
80110b8: 461a mov r2, r3
80110ba: 687b ldr r3, [r7, #4]
80110bc: 80da strh r2, [r3, #6]
}
80110be: bf00 nop
80110c0: 3710 adds r7, #16
80110c2: 46bd mov sp, r7
80110c4: bd80 pop {r7, pc}
080110c6 <USBD_CtlError>:
* @param pdev: device instance
* @param req: usb request
* @retval None
*/
void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80110c6: b580 push {r7, lr}
80110c8: b082 sub sp, #8
80110ca: af00 add r7, sp, #0
80110cc: 6078 str r0, [r7, #4]
80110ce: 6039 str r1, [r7, #0]
UNUSED(req);
(void)USBD_LL_StallEP(pdev, 0x80U);
80110d0: 2180 movs r1, #128 @ 0x80
80110d2: 6878 ldr r0, [r7, #4]
80110d4: f006 fa4a bl 801756c <USBD_LL_StallEP>
(void)USBD_LL_StallEP(pdev, 0U);
80110d8: 2100 movs r1, #0
80110da: 6878 ldr r0, [r7, #4]
80110dc: f006 fa46 bl 801756c <USBD_LL_StallEP>
}
80110e0: bf00 nop
80110e2: 3708 adds r7, #8
80110e4: 46bd mov sp, r7
80110e6: bd80 pop {r7, pc}
080110e8 <USBD_GetString>:
* @param unicode : Formatted string buffer (unicode)
* @param len : descriptor length
* @retval None
*/
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
{
80110e8: b580 push {r7, lr}
80110ea: b086 sub sp, #24
80110ec: af00 add r7, sp, #0
80110ee: 60f8 str r0, [r7, #12]
80110f0: 60b9 str r1, [r7, #8]
80110f2: 607a str r2, [r7, #4]
uint8_t idx = 0U;
80110f4: 2300 movs r3, #0
80110f6: 75fb strb r3, [r7, #23]
uint8_t *pdesc;
if (desc == NULL)
80110f8: 68fb ldr r3, [r7, #12]
80110fa: 2b00 cmp r3, #0
80110fc: d042 beq.n 8011184 <USBD_GetString+0x9c>
{
return;
}
pdesc = desc;
80110fe: 68fb ldr r3, [r7, #12]
8011100: 613b str r3, [r7, #16]
*len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U);
8011102: 6938 ldr r0, [r7, #16]
8011104: f000 f842 bl 801118c <USBD_GetLen>
8011108: 4603 mov r3, r0
801110a: 3301 adds r3, #1
801110c: 005b lsls r3, r3, #1
801110e: f5b3 7f00 cmp.w r3, #512 @ 0x200
8011112: d808 bhi.n 8011126 <USBD_GetString+0x3e>
8011114: 6938 ldr r0, [r7, #16]
8011116: f000 f839 bl 801118c <USBD_GetLen>
801111a: 4603 mov r3, r0
801111c: 3301 adds r3, #1
801111e: b29b uxth r3, r3
8011120: 005b lsls r3, r3, #1
8011122: b29a uxth r2, r3
8011124: e001 b.n 801112a <USBD_GetString+0x42>
8011126: f44f 7200 mov.w r2, #512 @ 0x200
801112a: 687b ldr r3, [r7, #4]
801112c: 801a strh r2, [r3, #0]
unicode[idx] = *(uint8_t *)len;
801112e: 7dfb ldrb r3, [r7, #23]
8011130: 68ba ldr r2, [r7, #8]
8011132: 4413 add r3, r2
8011134: 687a ldr r2, [r7, #4]
8011136: 7812 ldrb r2, [r2, #0]
8011138: 701a strb r2, [r3, #0]
idx++;
801113a: 7dfb ldrb r3, [r7, #23]
801113c: 3301 adds r3, #1
801113e: 75fb strb r3, [r7, #23]
unicode[idx] = USB_DESC_TYPE_STRING;
8011140: 7dfb ldrb r3, [r7, #23]
8011142: 68ba ldr r2, [r7, #8]
8011144: 4413 add r3, r2
8011146: 2203 movs r2, #3
8011148: 701a strb r2, [r3, #0]
idx++;
801114a: 7dfb ldrb r3, [r7, #23]
801114c: 3301 adds r3, #1
801114e: 75fb strb r3, [r7, #23]
while (*pdesc != (uint8_t)'\0')
8011150: e013 b.n 801117a <USBD_GetString+0x92>
{
unicode[idx] = *pdesc;
8011152: 7dfb ldrb r3, [r7, #23]
8011154: 68ba ldr r2, [r7, #8]
8011156: 4413 add r3, r2
8011158: 693a ldr r2, [r7, #16]
801115a: 7812 ldrb r2, [r2, #0]
801115c: 701a strb r2, [r3, #0]
pdesc++;
801115e: 693b ldr r3, [r7, #16]
8011160: 3301 adds r3, #1
8011162: 613b str r3, [r7, #16]
idx++;
8011164: 7dfb ldrb r3, [r7, #23]
8011166: 3301 adds r3, #1
8011168: 75fb strb r3, [r7, #23]
unicode[idx] = 0U;
801116a: 7dfb ldrb r3, [r7, #23]
801116c: 68ba ldr r2, [r7, #8]
801116e: 4413 add r3, r2
8011170: 2200 movs r2, #0
8011172: 701a strb r2, [r3, #0]
idx++;
8011174: 7dfb ldrb r3, [r7, #23]
8011176: 3301 adds r3, #1
8011178: 75fb strb r3, [r7, #23]
while (*pdesc != (uint8_t)'\0')
801117a: 693b ldr r3, [r7, #16]
801117c: 781b ldrb r3, [r3, #0]
801117e: 2b00 cmp r3, #0
8011180: d1e7 bne.n 8011152 <USBD_GetString+0x6a>
8011182: e000 b.n 8011186 <USBD_GetString+0x9e>
return;
8011184: bf00 nop
}
}
8011186: 3718 adds r7, #24
8011188: 46bd mov sp, r7
801118a: bd80 pop {r7, pc}
0801118c <USBD_GetLen>:
* return the string length
* @param buf : pointer to the ascii string buffer
* @retval string length
*/
static uint8_t USBD_GetLen(uint8_t *buf)
{
801118c: b480 push {r7}
801118e: b085 sub sp, #20
8011190: af00 add r7, sp, #0
8011192: 6078 str r0, [r7, #4]
uint8_t len = 0U;
8011194: 2300 movs r3, #0
8011196: 73fb strb r3, [r7, #15]
uint8_t *pbuff = buf;
8011198: 687b ldr r3, [r7, #4]
801119a: 60bb str r3, [r7, #8]
while (*pbuff != (uint8_t)'\0')
801119c: e005 b.n 80111aa <USBD_GetLen+0x1e>
{
len++;
801119e: 7bfb ldrb r3, [r7, #15]
80111a0: 3301 adds r3, #1
80111a2: 73fb strb r3, [r7, #15]
pbuff++;
80111a4: 68bb ldr r3, [r7, #8]
80111a6: 3301 adds r3, #1
80111a8: 60bb str r3, [r7, #8]
while (*pbuff != (uint8_t)'\0')
80111aa: 68bb ldr r3, [r7, #8]
80111ac: 781b ldrb r3, [r3, #0]
80111ae: 2b00 cmp r3, #0
80111b0: d1f5 bne.n 801119e <USBD_GetLen+0x12>
}
return len;
80111b2: 7bfb ldrb r3, [r7, #15]
}
80111b4: 4618 mov r0, r3
80111b6: 3714 adds r7, #20
80111b8: 46bd mov sp, r7
80111ba: f85d 7b04 ldr.w r7, [sp], #4
80111be: 4770 bx lr
080111c0 <USBD_CtlSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
80111c0: b580 push {r7, lr}
80111c2: b084 sub sp, #16
80111c4: af00 add r7, sp, #0
80111c6: 60f8 str r0, [r7, #12]
80111c8: 60b9 str r1, [r7, #8]
80111ca: 607a str r2, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
80111cc: 68fb ldr r3, [r7, #12]
80111ce: 2202 movs r2, #2
80111d0: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_in[0].total_length = len;
80111d4: 68fb ldr r3, [r7, #12]
80111d6: 687a ldr r2, [r7, #4]
80111d8: 615a str r2, [r3, #20]
pdev->ep_in[0].pbuffer = pbuf;
80111da: 68fb ldr r3, [r7, #12]
80111dc: 68ba ldr r2, [r7, #8]
80111de: 625a str r2, [r3, #36] @ 0x24
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
pdev->ep_in[0].rem_length = 0U;
#else
pdev->ep_in[0].rem_length = len;
80111e0: 68fb ldr r3, [r7, #12]
80111e2: 687a ldr r2, [r7, #4]
80111e4: 619a str r2, [r3, #24]
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
/* Start the transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
80111e6: 687b ldr r3, [r7, #4]
80111e8: 68ba ldr r2, [r7, #8]
80111ea: 2100 movs r1, #0
80111ec: 68f8 ldr r0, [r7, #12]
80111ee: f006 fa46 bl 801767e <USBD_LL_Transmit>
return USBD_OK;
80111f2: 2300 movs r3, #0
}
80111f4: 4618 mov r0, r3
80111f6: 3710 adds r7, #16
80111f8: 46bd mov sp, r7
80111fa: bd80 pop {r7, pc}
080111fc <USBD_CtlContinueSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
80111fc: b580 push {r7, lr}
80111fe: b084 sub sp, #16
8011200: af00 add r7, sp, #0
8011202: 60f8 str r0, [r7, #12]
8011204: 60b9 str r1, [r7, #8]
8011206: 607a str r2, [r7, #4]
/* Start the next transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
8011208: 687b ldr r3, [r7, #4]
801120a: 68ba ldr r2, [r7, #8]
801120c: 2100 movs r1, #0
801120e: 68f8 ldr r0, [r7, #12]
8011210: f006 fa35 bl 801767e <USBD_LL_Transmit>
return USBD_OK;
8011214: 2300 movs r3, #0
}
8011216: 4618 mov r0, r3
8011218: 3710 adds r7, #16
801121a: 46bd mov sp, r7
801121c: bd80 pop {r7, pc}
0801121e <USBD_CtlPrepareRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
801121e: b580 push {r7, lr}
8011220: b084 sub sp, #16
8011222: af00 add r7, sp, #0
8011224: 60f8 str r0, [r7, #12]
8011226: 60b9 str r1, [r7, #8]
8011228: 607a str r2, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
801122a: 68fb ldr r3, [r7, #12]
801122c: 2203 movs r2, #3
801122e: f8c3 2294 str.w r2, [r3, #660] @ 0x294
pdev->ep_out[0].total_length = len;
8011232: 68fb ldr r3, [r7, #12]
8011234: 687a ldr r2, [r7, #4]
8011236: f8c3 2154 str.w r2, [r3, #340] @ 0x154
pdev->ep_out[0].pbuffer = pbuf;
801123a: 68fb ldr r3, [r7, #12]
801123c: 68ba ldr r2, [r7, #8]
801123e: f8c3 2164 str.w r2, [r3, #356] @ 0x164
#ifdef USBD_AVOID_PACKET_SPLIT_MPS
pdev->ep_out[0].rem_length = 0U;
#else
pdev->ep_out[0].rem_length = len;
8011242: 68fb ldr r3, [r7, #12]
8011244: 687a ldr r2, [r7, #4]
8011246: f8c3 2158 str.w r2, [r3, #344] @ 0x158
#endif /* USBD_AVOID_PACKET_SPLIT_MPS */
/* Start the transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
801124a: 687b ldr r3, [r7, #4]
801124c: 68ba ldr r2, [r7, #8]
801124e: 2100 movs r1, #0
8011250: 68f8 ldr r0, [r7, #12]
8011252: f006 fa35 bl 80176c0 <USBD_LL_PrepareReceive>
return USBD_OK;
8011256: 2300 movs r3, #0
}
8011258: 4618 mov r0, r3
801125a: 3710 adds r7, #16
801125c: 46bd mov sp, r7
801125e: bd80 pop {r7, pc}
08011260 <USBD_CtlContinueRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint32_t len)
{
8011260: b580 push {r7, lr}
8011262: b084 sub sp, #16
8011264: af00 add r7, sp, #0
8011266: 60f8 str r0, [r7, #12]
8011268: 60b9 str r1, [r7, #8]
801126a: 607a str r2, [r7, #4]
(void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
801126c: 687b ldr r3, [r7, #4]
801126e: 68ba ldr r2, [r7, #8]
8011270: 2100 movs r1, #0
8011272: 68f8 ldr r0, [r7, #12]
8011274: f006 fa24 bl 80176c0 <USBD_LL_PrepareReceive>
return USBD_OK;
8011278: 2300 movs r3, #0
}
801127a: 4618 mov r0, r3
801127c: 3710 adds r7, #16
801127e: 46bd mov sp, r7
8011280: bd80 pop {r7, pc}
08011282 <USBD_CtlSendStatus>:
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
8011282: b580 push {r7, lr}
8011284: b082 sub sp, #8
8011286: af00 add r7, sp, #0
8011288: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
801128a: 687b ldr r3, [r7, #4]
801128c: 2204 movs r2, #4
801128e: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
(void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
8011292: 2300 movs r3, #0
8011294: 2200 movs r2, #0
8011296: 2100 movs r1, #0
8011298: 6878 ldr r0, [r7, #4]
801129a: f006 f9f0 bl 801767e <USBD_LL_Transmit>
return USBD_OK;
801129e: 2300 movs r3, #0
}
80112a0: 4618 mov r0, r3
80112a2: 3708 adds r7, #8
80112a4: 46bd mov sp, r7
80112a6: bd80 pop {r7, pc}
080112a8 <USBD_CtlReceiveStatus>:
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
80112a8: b580 push {r7, lr}
80112aa: b082 sub sp, #8
80112ac: af00 add r7, sp, #0
80112ae: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
80112b0: 687b ldr r3, [r7, #4]
80112b2: 2205 movs r2, #5
80112b4: f8c3 2294 str.w r2, [r3, #660] @ 0x294
/* Start the transfer */
(void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
80112b8: 2300 movs r3, #0
80112ba: 2200 movs r2, #0
80112bc: 2100 movs r1, #0
80112be: 6878 ldr r0, [r7, #4]
80112c0: f006 f9fe bl 80176c0 <USBD_LL_PrepareReceive>
return USBD_OK;
80112c4: 2300 movs r3, #0
}
80112c6: 4618 mov r0, r3
80112c8: 3708 adds r7, #8
80112ca: 46bd mov sp, r7
80112cc: bd80 pop {r7, pc}
080112ce <SHCI_C2_DEBUG_Init>:
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket )
{
80112ce: b580 push {r7, lr}
80112d0: b088 sub sp, #32
80112d2: af00 add r7, sp, #0
80112d4: 6078 str r0, [r7, #4]
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
80112d6: f107 030c add.w r3, r7, #12
80112da: 61fb str r3, [r7, #28]
shci_send( SHCI_OPCODE_C2_DEBUG_INIT,
sizeof( SHCI_C2_DEBUG_init_Cmd_Param_t ),
(uint8_t*)&pCmdPacket->Param,
80112dc: 687b ldr r3, [r7, #4]
80112de: f103 020c add.w r2, r3, #12
shci_send( SHCI_OPCODE_C2_DEBUG_INIT,
80112e2: 69fb ldr r3, [r7, #28]
80112e4: 210f movs r1, #15
80112e6: f64f 4068 movw r0, #64616 @ 0xfc68
80112ea: f000 f935 bl 8011558 <shci_send>
p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
80112ee: 69fb ldr r3, [r7, #28]
80112f0: 330b adds r3, #11
80112f2: 78db ldrb r3, [r3, #3]
}
80112f4: 4618 mov r0, r3
80112f6: 3720 adds r7, #32
80112f8: 46bd mov sp, r7
80112fa: bd80 pop {r7, pc}
080112fc <SHCI_C2_Config>:
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket)
{
80112fc: b580 push {r7, lr}
80112fe: b088 sub sp, #32
8011300: af00 add r7, sp, #0
8011302: 6078 str r0, [r7, #4]
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
8011304: f107 030c add.w r3, r7, #12
8011308: 61fb str r3, [r7, #28]
shci_send( SHCI_OPCODE_C2_CONFIG,
801130a: 69fb ldr r3, [r7, #28]
801130c: 687a ldr r2, [r7, #4]
801130e: 2110 movs r1, #16
8011310: f64f 4075 movw r0, #64629 @ 0xfc75
8011314: f000 f920 bl 8011558 <shci_send>
sizeof(SHCI_C2_CONFIG_Cmd_Param_t),
(uint8_t*)pCmdPacket,
p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
8011318: 69fb ldr r3, [r7, #28]
801131a: 330b adds r3, #11
801131c: 78db ldrb r3, [r3, #3]
}
801131e: 4618 mov r0, r3
8011320: 3720 adds r7, #32
8011322: 46bd mov sp, r7
8011324: bd80 pop {r7, pc}
...
08011328 <SHCI_GetWirelessFwInfo>:
* Local System COMMAND
* These commands are NOT sent to the CPU2
*/
SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo )
{
8011328: b480 push {r7}
801132a: b08b sub sp, #44 @ 0x2c
801132c: af00 add r7, sp, #0
801132e: 6078 str r0, [r7, #4]
uint32_t ipccdba = 0;
8011330: 2300 movs r3, #0
8011332: 613b str r3, [r7, #16]
MB_RefTable_t * p_RefTable = NULL;
8011334: 2300 movs r3, #0
8011336: 60fb str r3, [r7, #12]
uint32_t wireless_firmware_version = 0;
8011338: 2300 movs r3, #0
801133a: 627b str r3, [r7, #36] @ 0x24
uint32_t wireless_firmware_memorySize = 0;
801133c: 2300 movs r3, #0
801133e: 623b str r3, [r7, #32]
uint32_t wireless_firmware_infoStack = 0;
8011340: 2300 movs r3, #0
8011342: 61fb str r3, [r7, #28]
MB_FUS_DeviceInfoTable_t * p_fus_device_info_table = NULL;
8011344: 2300 movs r3, #0
8011346: 60bb str r3, [r7, #8]
uint32_t fus_version = 0;
8011348: 2300 movs r3, #0
801134a: 61bb str r3, [r7, #24]
uint32_t fus_memorySize = 0;
801134c: 2300 movs r3, #0
801134e: 617b str r3, [r7, #20]
ipccdba = READ_BIT( FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA );
8011350: 4b4a ldr r3, [pc, #296] @ (801147c <SHCI_GetWirelessFwInfo+0x154>)
8011352: 6bdb ldr r3, [r3, #60] @ 0x3c
8011354: f3c3 030d ubfx r3, r3, #0, #14
8011358: 613b str r3, [r7, #16]
/**
* The Device Info Table mapping depends on which firmware is running on CPU2.
* If the FUS is running on CPU2, FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD shall be written in the table.
* Otherwise, it means the Wireless Firmware is running on the CPU2
*/
p_fus_device_info_table = (MB_FUS_DeviceInfoTable_t*)(*(uint32_t*)((ipccdba<<2) + SRAM2A_BASE));
801135a: 693b ldr r3, [r7, #16]
801135c: 009b lsls r3, r3, #2
801135e: f103 5300 add.w r3, r3, #536870912 @ 0x20000000
8011362: f503 3340 add.w r3, r3, #196608 @ 0x30000
8011366: 681b ldr r3, [r3, #0]
8011368: 60bb str r3, [r7, #8]
if(p_fus_device_info_table->DeviceInfoTableState == FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD)
801136a: 68bb ldr r3, [r7, #8]
801136c: 681b ldr r3, [r3, #0]
801136e: 4a44 ldr r2, [pc, #272] @ (8011480 <SHCI_GetWirelessFwInfo+0x158>)
8011370: 4293 cmp r3, r2
8011372: d10f bne.n 8011394 <SHCI_GetWirelessFwInfo+0x6c>
/* The FUS is running on CPU2 */
/**
* Retrieve the WirelessFwInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
wireless_firmware_version = p_fus_device_info_table->WirelessStackVersion;
8011374: 68bb ldr r3, [r7, #8]
8011376: 695b ldr r3, [r3, #20]
8011378: 627b str r3, [r7, #36] @ 0x24
wireless_firmware_memorySize = p_fus_device_info_table->WirelessStackMemorySize;
801137a: 68bb ldr r3, [r7, #8]
801137c: 699b ldr r3, [r3, #24]
801137e: 623b str r3, [r7, #32]
wireless_firmware_infoStack = p_fus_device_info_table->WirelessFirmwareBleInfo;
8011380: 68bb ldr r3, [r7, #8]
8011382: 69db ldr r3, [r3, #28]
8011384: 61fb str r3, [r7, #28]
/**
* Retrieve the FusInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
fus_version = p_fus_device_info_table->FusVersion;
8011386: 68bb ldr r3, [r7, #8]
8011388: 68db ldr r3, [r3, #12]
801138a: 61bb str r3, [r7, #24]
fus_memorySize = p_fus_device_info_table->FusMemorySize;
801138c: 68bb ldr r3, [r7, #8]
801138e: 691b ldr r3, [r3, #16]
8011390: 617b str r3, [r7, #20]
8011392: e01a b.n 80113ca <SHCI_GetWirelessFwInfo+0xa2>
}
else
{
/* The Wireless Firmware is running on CPU2 */
p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE);
8011394: 693b ldr r3, [r7, #16]
8011396: 009b lsls r3, r3, #2
8011398: f103 5300 add.w r3, r3, #536870912 @ 0x20000000
801139c: f503 3340 add.w r3, r3, #196608 @ 0x30000
80113a0: 60fb str r3, [r7, #12]
/**
* Retrieve the WirelessFwInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
wireless_firmware_version = p_RefTable->p_device_info_table->WirelessFwInfoTable.Version;
80113a2: 68fb ldr r3, [r7, #12]
80113a4: 681b ldr r3, [r3, #0]
80113a6: 691b ldr r3, [r3, #16]
80113a8: 627b str r3, [r7, #36] @ 0x24
wireless_firmware_memorySize = p_RefTable->p_device_info_table->WirelessFwInfoTable.MemorySize;
80113aa: 68fb ldr r3, [r7, #12]
80113ac: 681b ldr r3, [r3, #0]
80113ae: 695b ldr r3, [r3, #20]
80113b0: 623b str r3, [r7, #32]
wireless_firmware_infoStack = p_RefTable->p_device_info_table->WirelessFwInfoTable.InfoStack;
80113b2: 68fb ldr r3, [r7, #12]
80113b4: 681b ldr r3, [r3, #0]
80113b6: 699b ldr r3, [r3, #24]
80113b8: 61fb str r3, [r7, #28]
/**
* Retrieve the FusInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
fus_version = p_RefTable->p_device_info_table->FusInfoTable.Version;
80113ba: 68fb ldr r3, [r7, #12]
80113bc: 681b ldr r3, [r3, #0]
80113be: 685b ldr r3, [r3, #4]
80113c0: 61bb str r3, [r7, #24]
fus_memorySize = p_RefTable->p_device_info_table->FusInfoTable.MemorySize;
80113c2: 68fb ldr r3, [r7, #12]
80113c4: 681b ldr r3, [r3, #0]
80113c6: 689b ldr r3, [r3, #8]
80113c8: 617b str r3, [r7, #20]
/**
* Retrieve the WirelessFwInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
pWirelessInfo->VersionMajor = ((wireless_firmware_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET);
80113ca: 6a7b ldr r3, [r7, #36] @ 0x24
80113cc: 0e1b lsrs r3, r3, #24
80113ce: b2da uxtb r2, r3
80113d0: 687b ldr r3, [r7, #4]
80113d2: 701a strb r2, [r3, #0]
pWirelessInfo->VersionMinor = ((wireless_firmware_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET);
80113d4: 6a7b ldr r3, [r7, #36] @ 0x24
80113d6: 0c1b lsrs r3, r3, #16
80113d8: b2da uxtb r2, r3
80113da: 687b ldr r3, [r7, #4]
80113dc: 705a strb r2, [r3, #1]
pWirelessInfo->VersionSub = ((wireless_firmware_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET);
80113de: 6a7b ldr r3, [r7, #36] @ 0x24
80113e0: 0a1b lsrs r3, r3, #8
80113e2: b2da uxtb r2, r3
80113e4: 687b ldr r3, [r7, #4]
80113e6: 709a strb r2, [r3, #2]
pWirelessInfo->VersionBranch = ((wireless_firmware_version & INFO_VERSION_BRANCH_MASK) >> INFO_VERSION_BRANCH_OFFSET);
80113e8: 6a7b ldr r3, [r7, #36] @ 0x24
80113ea: 091b lsrs r3, r3, #4
80113ec: b2db uxtb r3, r3
80113ee: f003 030f and.w r3, r3, #15
80113f2: b2da uxtb r2, r3
80113f4: 687b ldr r3, [r7, #4]
80113f6: 70da strb r2, [r3, #3]
pWirelessInfo->VersionReleaseType = ((wireless_firmware_version & INFO_VERSION_TYPE_MASK) >> INFO_VERSION_TYPE_OFFSET);
80113f8: 6a7b ldr r3, [r7, #36] @ 0x24
80113fa: b2db uxtb r3, r3
80113fc: f003 030f and.w r3, r3, #15
8011400: b2da uxtb r2, r3
8011402: 687b ldr r3, [r7, #4]
8011404: 711a strb r2, [r3, #4]
pWirelessInfo->MemorySizeSram2B = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET);
8011406: 6a3b ldr r3, [r7, #32]
8011408: 0e1b lsrs r3, r3, #24
801140a: b2da uxtb r2, r3
801140c: 687b ldr r3, [r7, #4]
801140e: 715a strb r2, [r3, #5]
pWirelessInfo->MemorySizeSram2A = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET);
8011410: 6a3b ldr r3, [r7, #32]
8011412: 0c1b lsrs r3, r3, #16
8011414: b2da uxtb r2, r3
8011416: 687b ldr r3, [r7, #4]
8011418: 719a strb r2, [r3, #6]
pWirelessInfo->MemorySizeSram1 = ((wireless_firmware_memorySize & INFO_SIZE_SRAM1_MASK) >> INFO_SIZE_SRAM1_OFFSET);
801141a: 6a3b ldr r3, [r7, #32]
801141c: 0a1b lsrs r3, r3, #8
801141e: b2da uxtb r2, r3
8011420: 687b ldr r3, [r7, #4]
8011422: 71da strb r2, [r3, #7]
pWirelessInfo->MemorySizeFlash = ((wireless_firmware_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET);
8011424: 6a3b ldr r3, [r7, #32]
8011426: b2da uxtb r2, r3
8011428: 687b ldr r3, [r7, #4]
801142a: 721a strb r2, [r3, #8]
pWirelessInfo->StackType = ((wireless_firmware_infoStack & INFO_STACK_TYPE_MASK) >> INFO_STACK_TYPE_OFFSET);
801142c: 69fb ldr r3, [r7, #28]
801142e: b2da uxtb r2, r3
8011430: 687b ldr r3, [r7, #4]
8011432: 725a strb r2, [r3, #9]
/**
* Retrieve the FusInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
pWirelessInfo->FusVersionMajor = ((fus_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET);
8011434: 69bb ldr r3, [r7, #24]
8011436: 0e1b lsrs r3, r3, #24
8011438: b2da uxtb r2, r3
801143a: 687b ldr r3, [r7, #4]
801143c: 729a strb r2, [r3, #10]
pWirelessInfo->FusVersionMinor = ((fus_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET);
801143e: 69bb ldr r3, [r7, #24]
8011440: 0c1b lsrs r3, r3, #16
8011442: b2da uxtb r2, r3
8011444: 687b ldr r3, [r7, #4]
8011446: 72da strb r2, [r3, #11]
pWirelessInfo->FusVersionSub = ((fus_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET);
8011448: 69bb ldr r3, [r7, #24]
801144a: 0a1b lsrs r3, r3, #8
801144c: b2da uxtb r2, r3
801144e: 687b ldr r3, [r7, #4]
8011450: 731a strb r2, [r3, #12]
pWirelessInfo->FusMemorySizeSram2B = ((fus_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET);
8011452: 697b ldr r3, [r7, #20]
8011454: 0e1b lsrs r3, r3, #24
8011456: b2da uxtb r2, r3
8011458: 687b ldr r3, [r7, #4]
801145a: 735a strb r2, [r3, #13]
pWirelessInfo->FusMemorySizeSram2A = ((fus_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET);
801145c: 697b ldr r3, [r7, #20]
801145e: 0c1b lsrs r3, r3, #16
8011460: b2da uxtb r2, r3
8011462: 687b ldr r3, [r7, #4]
8011464: 739a strb r2, [r3, #14]
pWirelessInfo->FusMemorySizeFlash = ((fus_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET);
8011466: 697b ldr r3, [r7, #20]
8011468: b2da uxtb r2, r3
801146a: 687b ldr r3, [r7, #4]
801146c: 73da strb r2, [r3, #15]
return (SHCI_Success);
801146e: 2300 movs r3, #0
}
8011470: 4618 mov r0, r3
8011472: 372c adds r7, #44 @ 0x2c
8011474: 46bd mov sp, r7
8011476: f85d 7b04 ldr.w r7, [sp], #4
801147a: 4770 bx lr
801147c: 58004000 .word 0x58004000
8011480: a94656b9 .word 0xa94656b9
08011484 <shci_init>:
static void TlUserEvtReceived(TL_EvtPacket_t *shcievt);
static void TlInit( TL_CmdPacket_t * p_cmdbuffer );
/* Interface ------- ---------------------------------------------------------*/
void shci_init(void(* UserEvtRx)(void* pData), void* pConf)
{
8011484: b580 push {r7, lr}
8011486: b082 sub sp, #8
8011488: af00 add r7, sp, #0
801148a: 6078 str r0, [r7, #4]
801148c: 6039 str r1, [r7, #0]
StatusNotCallBackFunction = ((SHCI_TL_HciInitConf_t *)pConf)->StatusNotCallBack;
801148e: 683b ldr r3, [r7, #0]
8011490: 685b ldr r3, [r3, #4]
8011492: 4a08 ldr r2, [pc, #32] @ (80114b4 <shci_init+0x30>)
8011494: 6013 str r3, [r2, #0]
shciContext.UserEvtRx = UserEvtRx;
8011496: 4a08 ldr r2, [pc, #32] @ (80114b8 <shci_init+0x34>)
8011498: 687b ldr r3, [r7, #4]
801149a: 61d3 str r3, [r2, #28]
shci_register_io_bus (&shciContext.io);
801149c: 4806 ldr r0, [pc, #24] @ (80114b8 <shci_init+0x34>)
801149e: f000 f915 bl 80116cc <shci_register_io_bus>
TlInit((TL_CmdPacket_t *)(((SHCI_TL_HciInitConf_t *)pConf)->p_cmdbuffer));
80114a2: 683b ldr r3, [r7, #0]
80114a4: 681b ldr r3, [r3, #0]
80114a6: 4618 mov r0, r3
80114a8: f000 f898 bl 80115dc <TlInit>
return;
80114ac: bf00 nop
}
80114ae: 3708 adds r7, #8
80114b0: 46bd mov sp, r7
80114b2: bd80 pop {r7, pc}
80114b4: 200007a8 .word 0x200007a8
80114b8: 20000788 .word 0x20000788
080114bc <shci_user_evt_proc>:
void shci_user_evt_proc(void)
{
80114bc: b580 push {r7, lr}
80114be: b084 sub sp, #16
80114c0: af00 add r7, sp, #0
/**
* It is more secure to use LST_remove_head()/LST_insert_head() compare to LST_get_next_node()/LST_remove_node()
* in case the user overwrite the header where the next/prev pointers are located
*/
if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable))
80114c2: 4822 ldr r0, [pc, #136] @ (801154c <shci_user_evt_proc+0x90>)
80114c4: f000 fb52 bl 8011b6c <LST_is_empty>
80114c8: 4603 mov r3, r0
80114ca: 2b00 cmp r3, #0
80114cc: d12b bne.n 8011526 <shci_user_evt_proc+0x6a>
80114ce: 4b20 ldr r3, [pc, #128] @ (8011550 <shci_user_evt_proc+0x94>)
80114d0: 781b ldrb r3, [r3, #0]
80114d2: 2b00 cmp r3, #0
80114d4: d027 beq.n 8011526 <shci_user_evt_proc+0x6a>
{
LST_remove_head ( &SHciAsynchEventQueue, (tListNode **)&phcievtbuffer );
80114d6: f107 030c add.w r3, r7, #12
80114da: 4619 mov r1, r3
80114dc: 481b ldr r0, [pc, #108] @ (801154c <shci_user_evt_proc+0x90>)
80114de: f000 fbd4 bl 8011c8a <LST_remove_head>
if (shciContext.UserEvtRx != NULL)
80114e2: 4b1c ldr r3, [pc, #112] @ (8011554 <shci_user_evt_proc+0x98>)
80114e4: 69db ldr r3, [r3, #28]
80114e6: 2b00 cmp r3, #0
80114e8: d00c beq.n 8011504 <shci_user_evt_proc+0x48>
{
UserEvtRxParam.pckt = phcievtbuffer;
80114ea: 68fb ldr r3, [r7, #12]
80114ec: 60bb str r3, [r7, #8]
UserEvtRxParam.status = SHCI_TL_UserEventFlow_Enable;
80114ee: 2301 movs r3, #1
80114f0: 713b strb r3, [r7, #4]
shciContext.UserEvtRx((void *)&UserEvtRxParam);
80114f2: 4b18 ldr r3, [pc, #96] @ (8011554 <shci_user_evt_proc+0x98>)
80114f4: 69db ldr r3, [r3, #28]
80114f6: 1d3a adds r2, r7, #4
80114f8: 4610 mov r0, r2
80114fa: 4798 blx r3
SHCI_TL_UserEventFlow = UserEvtRxParam.status;
80114fc: 793a ldrb r2, [r7, #4]
80114fe: 4b14 ldr r3, [pc, #80] @ (8011550 <shci_user_evt_proc+0x94>)
8011500: 701a strb r2, [r3, #0]
8011502: e002 b.n 801150a <shci_user_evt_proc+0x4e>
}
else
{
SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable;
8011504: 4b12 ldr r3, [pc, #72] @ (8011550 <shci_user_evt_proc+0x94>)
8011506: 2201 movs r2, #1
8011508: 701a strb r2, [r3, #0]
}
if(SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable)
801150a: 4b11 ldr r3, [pc, #68] @ (8011550 <shci_user_evt_proc+0x94>)
801150c: 781b ldrb r3, [r3, #0]
801150e: 2b00 cmp r3, #0
8011510: d004 beq.n 801151c <shci_user_evt_proc+0x60>
{
TL_MM_EvtDone( phcievtbuffer );
8011512: 68fb ldr r3, [r7, #12]
8011514: 4618 mov r0, r3
8011516: f000 fa25 bl 8011964 <TL_MM_EvtDone>
801151a: e004 b.n 8011526 <shci_user_evt_proc+0x6a>
else
{
/**
* put back the event in the queue
*/
LST_insert_head ( &SHciAsynchEventQueue, (tListNode *)phcievtbuffer );
801151c: 68fb ldr r3, [r7, #12]
801151e: 4619 mov r1, r3
8011520: 480a ldr r0, [pc, #40] @ (801154c <shci_user_evt_proc+0x90>)
8011522: f000 fb45 bl 8011bb0 <LST_insert_head>
}
}
if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable))
8011526: 4809 ldr r0, [pc, #36] @ (801154c <shci_user_evt_proc+0x90>)
8011528: f000 fb20 bl 8011b6c <LST_is_empty>
801152c: 4603 mov r3, r0
801152e: 2b00 cmp r3, #0
8011530: d107 bne.n 8011542 <shci_user_evt_proc+0x86>
8011532: 4b07 ldr r3, [pc, #28] @ (8011550 <shci_user_evt_proc+0x94>)
8011534: 781b ldrb r3, [r3, #0]
8011536: 2b00 cmp r3, #0
8011538: d003 beq.n 8011542 <shci_user_evt_proc+0x86>
{
shci_notify_asynch_evt((void*) &SHciAsynchEventQueue);
801153a: 4804 ldr r0, [pc, #16] @ (801154c <shci_user_evt_proc+0x90>)
801153c: f7f0 f956 bl 80017ec <shci_notify_asynch_evt>
}
return;
8011540: bf00 nop
8011542: bf00 nop
}
8011544: 3710 adds r7, #16
8011546: 46bd mov sp, r7
8011548: bd80 pop {r7, pc}
801154a: bf00 nop
801154c: 200002d8 .word 0x200002d8
8011550: 200002e8 .word 0x200002e8
8011554: 20000788 .word 0x20000788
08011558 <shci_send>:
return;
}
void shci_send( uint16_t cmd_code, uint8_t len_cmd_payload, uint8_t * p_cmd_payload, TL_EvtPacket_t * p_rsp )
{
8011558: b580 push {r7, lr}
801155a: b084 sub sp, #16
801155c: af00 add r7, sp, #0
801155e: 60ba str r2, [r7, #8]
8011560: 607b str r3, [r7, #4]
8011562: 4603 mov r3, r0
8011564: 81fb strh r3, [r7, #14]
8011566: 460b mov r3, r1
8011568: 737b strb r3, [r7, #13]
Cmd_SetStatus(SHCI_TL_CmdBusy);
801156a: 2000 movs r0, #0
801156c: f000 f868 bl 8011640 <Cmd_SetStatus>
pCmdBuffer->cmdserial.cmd.cmdcode = cmd_code;
8011570: 4b17 ldr r3, [pc, #92] @ (80115d0 <shci_send+0x78>)
8011572: 681b ldr r3, [r3, #0]
8011574: 89fa ldrh r2, [r7, #14]
8011576: f8a3 2009 strh.w r2, [r3, #9]
pCmdBuffer->cmdserial.cmd.plen = len_cmd_payload;
801157a: 4b15 ldr r3, [pc, #84] @ (80115d0 <shci_send+0x78>)
801157c: 681b ldr r3, [r3, #0]
801157e: 7b7a ldrb r2, [r7, #13]
8011580: 72da strb r2, [r3, #11]
memcpy(pCmdBuffer->cmdserial.cmd.payload, p_cmd_payload, len_cmd_payload );
8011582: 4b13 ldr r3, [pc, #76] @ (80115d0 <shci_send+0x78>)
8011584: 681b ldr r3, [r3, #0]
8011586: 330c adds r3, #12
8011588: 7b7a ldrb r2, [r7, #13]
801158a: 68b9 ldr r1, [r7, #8]
801158c: 4618 mov r0, r3
801158e: f007 faa0 bl 8018ad2 <memcpy>
CmdRspStatusFlag = SHCI_TL_CMD_RESP_WAIT;
8011592: 4b10 ldr r3, [pc, #64] @ (80115d4 <shci_send+0x7c>)
8011594: 2201 movs r2, #1
8011596: 701a strb r2, [r3, #0]
shciContext.io.Send(0,0);
8011598: 4b0f ldr r3, [pc, #60] @ (80115d8 <shci_send+0x80>)
801159a: 691b ldr r3, [r3, #16]
801159c: 2100 movs r1, #0
801159e: 2000 movs r0, #0
80115a0: 4798 blx r3
shci_cmd_resp_wait(SHCI_TL_DEFAULT_TIMEOUT);
80115a2: f248 00e8 movw r0, #33000 @ 0x80e8
80115a6: f7f0 f941 bl 800182c <shci_cmd_resp_wait>
/**
* The command complete of a system command does not have the header
* It starts immediately with the evtserial field
*/
memcpy( &(p_rsp->evtserial), pCmdBuffer, ((TL_EvtSerial_t*)pCmdBuffer)->evt.plen + TL_EVT_HDR_SIZE );
80115aa: 687b ldr r3, [r7, #4]
80115ac: f103 0008 add.w r0, r3, #8
80115b0: 4b07 ldr r3, [pc, #28] @ (80115d0 <shci_send+0x78>)
80115b2: 6819 ldr r1, [r3, #0]
80115b4: 4b06 ldr r3, [pc, #24] @ (80115d0 <shci_send+0x78>)
80115b6: 681b ldr r3, [r3, #0]
80115b8: 789b ldrb r3, [r3, #2]
80115ba: 3303 adds r3, #3
80115bc: 461a mov r2, r3
80115be: f007 fa88 bl 8018ad2 <memcpy>
Cmd_SetStatus(SHCI_TL_CmdAvailable);
80115c2: 2001 movs r0, #1
80115c4: f000 f83c bl 8011640 <Cmd_SetStatus>
return;
80115c8: bf00 nop
}
80115ca: 3710 adds r7, #16
80115cc: 46bd mov sp, r7
80115ce: bd80 pop {r7, pc}
80115d0: 200002e4 .word 0x200002e4
80115d4: 200007ac .word 0x200007ac
80115d8: 20000788 .word 0x20000788
080115dc <TlInit>:
/* Private functions ---------------------------------------------------------*/
static void TlInit( TL_CmdPacket_t * p_cmdbuffer )
{
80115dc: b580 push {r7, lr}
80115de: b086 sub sp, #24
80115e0: af00 add r7, sp, #0
80115e2: 6078 str r0, [r7, #4]
TL_SYS_InitConf_t Conf;
pCmdBuffer = p_cmdbuffer;
80115e4: 4a10 ldr r2, [pc, #64] @ (8011628 <TlInit+0x4c>)
80115e6: 687b ldr r3, [r7, #4]
80115e8: 6013 str r3, [r2, #0]
LST_init_head (&SHciAsynchEventQueue);
80115ea: 4810 ldr r0, [pc, #64] @ (801162c <TlInit+0x50>)
80115ec: f000 faae bl 8011b4c <LST_init_head>
Cmd_SetStatus(SHCI_TL_CmdAvailable);
80115f0: 2001 movs r0, #1
80115f2: f000 f825 bl 8011640 <Cmd_SetStatus>
SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable;
80115f6: 4b0e ldr r3, [pc, #56] @ (8011630 <TlInit+0x54>)
80115f8: 2201 movs r2, #1
80115fa: 701a strb r2, [r3, #0]
/* Initialize low level driver */
if (shciContext.io.Init)
80115fc: 4b0d ldr r3, [pc, #52] @ (8011634 <TlInit+0x58>)
80115fe: 681b ldr r3, [r3, #0]
8011600: 2b00 cmp r3, #0
8011602: d00c beq.n 801161e <TlInit+0x42>
{
Conf.p_cmdbuffer = (uint8_t *)p_cmdbuffer;
8011604: 687b ldr r3, [r7, #4]
8011606: 617b str r3, [r7, #20]
Conf.IoBusCallBackCmdEvt = TlCmdEvtReceived;
8011608: 4b0b ldr r3, [pc, #44] @ (8011638 <TlInit+0x5c>)
801160a: 60fb str r3, [r7, #12]
Conf.IoBusCallBackUserEvt = TlUserEvtReceived;
801160c: 4b0b ldr r3, [pc, #44] @ (801163c <TlInit+0x60>)
801160e: 613b str r3, [r7, #16]
shciContext.io.Init(&Conf);
8011610: 4b08 ldr r3, [pc, #32] @ (8011634 <TlInit+0x58>)
8011612: 681b ldr r3, [r3, #0]
8011614: f107 020c add.w r2, r7, #12
8011618: 4610 mov r0, r2
801161a: 4798 blx r3
}
return;
801161c: bf00 nop
801161e: bf00 nop
}
8011620: 3718 adds r7, #24
8011622: 46bd mov sp, r7
8011624: bd80 pop {r7, pc}
8011626: bf00 nop
8011628: 200002e4 .word 0x200002e4
801162c: 200002d8 .word 0x200002d8
8011630: 200002e8 .word 0x200002e8
8011634: 20000788 .word 0x20000788
8011638: 08011691 .word 0x08011691
801163c: 080116a9 .word 0x080116a9
08011640 <Cmd_SetStatus>:
static void Cmd_SetStatus(SHCI_TL_CmdStatus_t shcicmdstatus)
{
8011640: b580 push {r7, lr}
8011642: b082 sub sp, #8
8011644: af00 add r7, sp, #0
8011646: 4603 mov r3, r0
8011648: 71fb strb r3, [r7, #7]
if(shcicmdstatus == SHCI_TL_CmdBusy)
801164a: 79fb ldrb r3, [r7, #7]
801164c: 2b00 cmp r3, #0
801164e: d10b bne.n 8011668 <Cmd_SetStatus+0x28>
{
if(StatusNotCallBackFunction != 0)
8011650: 4b0d ldr r3, [pc, #52] @ (8011688 <Cmd_SetStatus+0x48>)
8011652: 681b ldr r3, [r3, #0]
8011654: 2b00 cmp r3, #0
8011656: d003 beq.n 8011660 <Cmd_SetStatus+0x20>
{
StatusNotCallBackFunction( SHCI_TL_CmdBusy );
8011658: 4b0b ldr r3, [pc, #44] @ (8011688 <Cmd_SetStatus+0x48>)
801165a: 681b ldr r3, [r3, #0]
801165c: 2000 movs r0, #0
801165e: 4798 blx r3
}
SHCICmdStatus = SHCI_TL_CmdBusy;
8011660: 4b0a ldr r3, [pc, #40] @ (801168c <Cmd_SetStatus+0x4c>)
8011662: 2200 movs r2, #0
8011664: 701a strb r2, [r3, #0]
{
StatusNotCallBackFunction( SHCI_TL_CmdAvailable );
}
}
return;
8011666: e00b b.n 8011680 <Cmd_SetStatus+0x40>
SHCICmdStatus = SHCI_TL_CmdAvailable;
8011668: 4b08 ldr r3, [pc, #32] @ (801168c <Cmd_SetStatus+0x4c>)
801166a: 2201 movs r2, #1
801166c: 701a strb r2, [r3, #0]
if(StatusNotCallBackFunction != 0)
801166e: 4b06 ldr r3, [pc, #24] @ (8011688 <Cmd_SetStatus+0x48>)
8011670: 681b ldr r3, [r3, #0]
8011672: 2b00 cmp r3, #0
8011674: d004 beq.n 8011680 <Cmd_SetStatus+0x40>
StatusNotCallBackFunction( SHCI_TL_CmdAvailable );
8011676: 4b04 ldr r3, [pc, #16] @ (8011688 <Cmd_SetStatus+0x48>)
8011678: 681b ldr r3, [r3, #0]
801167a: 2001 movs r0, #1
801167c: 4798 blx r3
return;
801167e: bf00 nop
8011680: bf00 nop
}
8011682: 3708 adds r7, #8
8011684: 46bd mov sp, r7
8011686: bd80 pop {r7, pc}
8011688: 200007a8 .word 0x200007a8
801168c: 200002e0 .word 0x200002e0
08011690 <TlCmdEvtReceived>:
static void TlCmdEvtReceived(TL_EvtPacket_t *shcievt)
{
8011690: b580 push {r7, lr}
8011692: b082 sub sp, #8
8011694: af00 add r7, sp, #0
8011696: 6078 str r0, [r7, #4]
(void)(shcievt);
shci_cmd_resp_release(0); /**< Notify the application the Cmd response has been received */
8011698: 2000 movs r0, #0
801169a: f7f0 f8b7 bl 800180c <shci_cmd_resp_release>
return;
801169e: bf00 nop
}
80116a0: 3708 adds r7, #8
80116a2: 46bd mov sp, r7
80116a4: bd80 pop {r7, pc}
...
080116a8 <TlUserEvtReceived>:
static void TlUserEvtReceived(TL_EvtPacket_t *shcievt)
{
80116a8: b580 push {r7, lr}
80116aa: b082 sub sp, #8
80116ac: af00 add r7, sp, #0
80116ae: 6078 str r0, [r7, #4]
LST_insert_tail(&SHciAsynchEventQueue, (tListNode *)shcievt);
80116b0: 6879 ldr r1, [r7, #4]
80116b2: 4805 ldr r0, [pc, #20] @ (80116c8 <TlUserEvtReceived+0x20>)
80116b4: f000 faa2 bl 8011bfc <LST_insert_tail>
shci_notify_asynch_evt((void*) &SHciAsynchEventQueue); /**< Notify the application a full HCI event has been received */
80116b8: 4803 ldr r0, [pc, #12] @ (80116c8 <TlUserEvtReceived+0x20>)
80116ba: f7f0 f897 bl 80017ec <shci_notify_asynch_evt>
return;
80116be: bf00 nop
}
80116c0: 3708 adds r7, #8
80116c2: 46bd mov sp, r7
80116c4: bd80 pop {r7, pc}
80116c6: bf00 nop
80116c8: 200002d8 .word 0x200002d8
080116cc <shci_register_io_bus>:
#include "shci_tl.h"
#include "tl.h"
void shci_register_io_bus(tSHciIO* fops)
{
80116cc: b480 push {r7}
80116ce: b083 sub sp, #12
80116d0: af00 add r7, sp, #0
80116d2: 6078 str r0, [r7, #4]
/* Register IO bus services */
fops->Init = TL_SYS_Init;
80116d4: 687b ldr r3, [r7, #4]
80116d6: 4a05 ldr r2, [pc, #20] @ (80116ec <shci_register_io_bus+0x20>)
80116d8: 601a str r2, [r3, #0]
fops->Send = TL_SYS_SendCmd;
80116da: 687b ldr r3, [r7, #4]
80116dc: 4a04 ldr r2, [pc, #16] @ (80116f0 <shci_register_io_bus+0x24>)
80116de: 611a str r2, [r3, #16]
return;
80116e0: bf00 nop
}
80116e2: 370c adds r7, #12
80116e4: 46bd mov sp, r7
80116e6: f85d 7b04 ldr.w r7, [sp], #4
80116ea: 4770 bx lr
80116ec: 080117f1 .word 0x080117f1
80116f0: 08011845 .word 0x08011845
080116f4 <TL_Enable>:
/******************************************************************************
* GENERAL - refer to AN5289 for functions description.
******************************************************************************/
void TL_Enable( void )
{
80116f4: b580 push {r7, lr}
80116f6: af00 add r7, sp, #0
HW_IPCC_Enable();
80116f8: f005 fa0c bl 8016b14 <HW_IPCC_Enable>
return;
80116fc: bf00 nop
}
80116fe: bd80 pop {r7, pc}
08011700 <TL_Init>:
void TL_Init( void )
{
8011700: b580 push {r7, lr}
8011702: af00 add r7, sp, #0
TL_RefTable.p_device_info_table = &TL_DeviceInfoTable;
8011704: 4b10 ldr r3, [pc, #64] @ (8011748 <TL_Init+0x48>)
8011706: 4a11 ldr r2, [pc, #68] @ (801174c <TL_Init+0x4c>)
8011708: 601a str r2, [r3, #0]
TL_RefTable.p_ble_table = &TL_BleTable;
801170a: 4b0f ldr r3, [pc, #60] @ (8011748 <TL_Init+0x48>)
801170c: 4a10 ldr r2, [pc, #64] @ (8011750 <TL_Init+0x50>)
801170e: 605a str r2, [r3, #4]
TL_RefTable.p_thread_table = &TL_ThreadTable;
8011710: 4b0d ldr r3, [pc, #52] @ (8011748 <TL_Init+0x48>)
8011712: 4a10 ldr r2, [pc, #64] @ (8011754 <TL_Init+0x54>)
8011714: 609a str r2, [r3, #8]
TL_RefTable.p_lld_tests_table = &TL_LldTestsTable;
8011716: 4b0c ldr r3, [pc, #48] @ (8011748 <TL_Init+0x48>)
8011718: 4a0f ldr r2, [pc, #60] @ (8011758 <TL_Init+0x58>)
801171a: 621a str r2, [r3, #32]
TL_RefTable.p_ble_lld_table = &TL_BleLldTable;
801171c: 4b0a ldr r3, [pc, #40] @ (8011748 <TL_Init+0x48>)
801171e: 4a0f ldr r2, [pc, #60] @ (801175c <TL_Init+0x5c>)
8011720: 625a str r2, [r3, #36] @ 0x24
TL_RefTable.p_sys_table = &TL_SysTable;
8011722: 4b09 ldr r3, [pc, #36] @ (8011748 <TL_Init+0x48>)
8011724: 4a0e ldr r2, [pc, #56] @ (8011760 <TL_Init+0x60>)
8011726: 60da str r2, [r3, #12]
TL_RefTable.p_mem_manager_table = &TL_MemManagerTable;
8011728: 4b07 ldr r3, [pc, #28] @ (8011748 <TL_Init+0x48>)
801172a: 4a0e ldr r2, [pc, #56] @ (8011764 <TL_Init+0x64>)
801172c: 611a str r2, [r3, #16]
TL_RefTable.p_traces_table = &TL_TracesTable;
801172e: 4b06 ldr r3, [pc, #24] @ (8011748 <TL_Init+0x48>)
8011730: 4a0d ldr r2, [pc, #52] @ (8011768 <TL_Init+0x68>)
8011732: 615a str r2, [r3, #20]
TL_RefTable.p_mac_802_15_4_table = &TL_Mac_802_15_4_Table;
8011734: 4b04 ldr r3, [pc, #16] @ (8011748 <TL_Init+0x48>)
8011736: 4a0d ldr r2, [pc, #52] @ (801176c <TL_Init+0x6c>)
8011738: 619a str r2, [r3, #24]
TL_RefTable.p_zigbee_table = &TL_Zigbee_Table;
801173a: 4b03 ldr r3, [pc, #12] @ (8011748 <TL_Init+0x48>)
801173c: 4a0c ldr r2, [pc, #48] @ (8011770 <TL_Init+0x70>)
801173e: 61da str r2, [r3, #28]
HW_IPCC_Init();
8011740: f005 f9fc bl 8016b3c <HW_IPCC_Init>
return;
8011744: bf00 nop
}
8011746: bd80 pop {r7, pc}
8011748: 20030000 .word 0x20030000
801174c: 20030028 .word 0x20030028
8011750: 20030048 .word 0x20030048
8011754: 20030058 .word 0x20030058
8011758: 20030068 .word 0x20030068
801175c: 20030070 .word 0x20030070
8011760: 20030078 .word 0x20030078
8011764: 20030080 .word 0x20030080
8011768: 2003009c .word 0x2003009c
801176c: 200300a0 .word 0x200300a0
8011770: 200300ac .word 0x200300ac
08011774 <HW_IPCC_BLE_RxEvtNot>:
return 0;
}
void HW_IPCC_BLE_RxEvtNot(void)
{
8011774: b580 push {r7, lr}
8011776: b082 sub sp, #8
8011778: af00 add r7, sp, #0
TL_EvtPacket_t *phcievt;
while(LST_is_empty(&EvtQueue) == FALSE)
801177a: e01c b.n 80117b6 <HW_IPCC_BLE_RxEvtNot+0x42>
{
LST_remove_head (&EvtQueue, (tListNode **)&phcievt);
801177c: 1d3b adds r3, r7, #4
801177e: 4619 mov r1, r3
8011780: 4812 ldr r0, [pc, #72] @ (80117cc <HW_IPCC_BLE_RxEvtNot+0x58>)
8011782: f000 fa82 bl 8011c8a <LST_remove_head>
if ( ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CS_OPCODE) || ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CC_OPCODE ) )
8011786: 687b ldr r3, [r7, #4]
8011788: 7a5b ldrb r3, [r3, #9]
801178a: 2b0f cmp r3, #15
801178c: d003 beq.n 8011796 <HW_IPCC_BLE_RxEvtNot+0x22>
801178e: 687b ldr r3, [r7, #4]
8011790: 7a5b ldrb r3, [r3, #9]
8011792: 2b0e cmp r3, #14
8011794: d105 bne.n 80117a2 <HW_IPCC_BLE_RxEvtNot+0x2e>
{
OutputDbgTrace(TL_MB_BLE_CMD_RSP, (uint8_t*)phcievt);
8011796: 687b ldr r3, [r7, #4]
8011798: 4619 mov r1, r3
801179a: 2002 movs r0, #2
801179c: f000 f950 bl 8011a40 <OutputDbgTrace>
80117a0: e004 b.n 80117ac <HW_IPCC_BLE_RxEvtNot+0x38>
}
else
{
OutputDbgTrace(TL_MB_BLE_ASYNCH_EVT, (uint8_t*)phcievt);
80117a2: 687b ldr r3, [r7, #4]
80117a4: 4619 mov r1, r3
80117a6: 2005 movs r0, #5
80117a8: f000 f94a bl 8011a40 <OutputDbgTrace>
}
BLE_IoBusEvtCallBackFunction(phcievt);
80117ac: 4b08 ldr r3, [pc, #32] @ (80117d0 <HW_IPCC_BLE_RxEvtNot+0x5c>)
80117ae: 681b ldr r3, [r3, #0]
80117b0: 687a ldr r2, [r7, #4]
80117b2: 4610 mov r0, r2
80117b4: 4798 blx r3
while(LST_is_empty(&EvtQueue) == FALSE)
80117b6: 4805 ldr r0, [pc, #20] @ (80117cc <HW_IPCC_BLE_RxEvtNot+0x58>)
80117b8: f000 f9d8 bl 8011b6c <LST_is_empty>
80117bc: 4603 mov r3, r0
80117be: 2b00 cmp r3, #0
80117c0: d0dc beq.n 801177c <HW_IPCC_BLE_RxEvtNot+0x8>
}
return;
80117c2: bf00 nop
}
80117c4: 3708 adds r7, #8
80117c6: 46bd mov sp, r7
80117c8: bd80 pop {r7, pc}
80117ca: bf00 nop
80117cc: 200300c8 .word 0x200300c8
80117d0: 200007b8 .word 0x200007b8
080117d4 <HW_IPCC_BLE_AclDataAckNot>:
return 0;
}
void HW_IPCC_BLE_AclDataAckNot(void)
{
80117d4: b580 push {r7, lr}
80117d6: af00 add r7, sp, #0
OutputDbgTrace(TL_MB_ACL_DATA_RSP, (uint8_t*)NULL);
80117d8: 2100 movs r1, #0
80117da: 2004 movs r0, #4
80117dc: f000 f930 bl 8011a40 <OutputDbgTrace>
BLE_IoBusAclDataTxAck( );
80117e0: 4b02 ldr r3, [pc, #8] @ (80117ec <HW_IPCC_BLE_AclDataAckNot+0x18>)
80117e2: 681b ldr r3, [r3, #0]
80117e4: 4798 blx r3
return;
80117e6: bf00 nop
}
80117e8: bd80 pop {r7, pc}
80117ea: bf00 nop
80117ec: 200007bc .word 0x200007bc
080117f0 <TL_SYS_Init>:
/******************************************************************************
* SYSTEM
******************************************************************************/
int32_t TL_SYS_Init( void* pConf )
{
80117f0: b580 push {r7, lr}
80117f2: b084 sub sp, #16
80117f4: af00 add r7, sp, #0
80117f6: 6078 str r0, [r7, #4]
MB_SysTable_t * p_systable;
TL_SYS_InitConf_t *pInitHciConf = (TL_SYS_InitConf_t *) pConf;
80117f8: 687b ldr r3, [r7, #4]
80117fa: 60fb str r3, [r7, #12]
LST_init_head (&SystemEvtQueue);
80117fc: 480d ldr r0, [pc, #52] @ (8011834 <TL_SYS_Init+0x44>)
80117fe: f000 f9a5 bl 8011b4c <LST_init_head>
p_systable = TL_RefTable.p_sys_table;
8011802: 4b0d ldr r3, [pc, #52] @ (8011838 <TL_SYS_Init+0x48>)
8011804: 68db ldr r3, [r3, #12]
8011806: 60bb str r3, [r7, #8]
p_systable->pcmd_buffer = pInitHciConf->p_cmdbuffer;
8011808: 68fb ldr r3, [r7, #12]
801180a: 689a ldr r2, [r3, #8]
801180c: 68bb ldr r3, [r7, #8]
801180e: 601a str r2, [r3, #0]
p_systable->sys_queue = (uint8_t*)&SystemEvtQueue;
8011810: 68bb ldr r3, [r7, #8]
8011812: 4a08 ldr r2, [pc, #32] @ (8011834 <TL_SYS_Init+0x44>)
8011814: 605a str r2, [r3, #4]
HW_IPCC_SYS_Init();
8011816: f005 f9cf bl 8016bb8 <HW_IPCC_SYS_Init>
SYS_CMD_IoBusCallBackFunction = pInitHciConf->IoBusCallBackCmdEvt;
801181a: 68fb ldr r3, [r7, #12]
801181c: 681b ldr r3, [r3, #0]
801181e: 4a07 ldr r2, [pc, #28] @ (801183c <TL_SYS_Init+0x4c>)
8011820: 6013 str r3, [r2, #0]
SYS_EVT_IoBusCallBackFunction = pInitHciConf->IoBusCallBackUserEvt;
8011822: 68fb ldr r3, [r7, #12]
8011824: 685b ldr r3, [r3, #4]
8011826: 4a06 ldr r2, [pc, #24] @ (8011840 <TL_SYS_Init+0x50>)
8011828: 6013 str r3, [r2, #0]
return 0;
801182a: 2300 movs r3, #0
}
801182c: 4618 mov r0, r3
801182e: 3710 adds r7, #16
8011830: 46bd mov sp, r7
8011832: bd80 pop {r7, pc}
8011834: 200300d0 .word 0x200300d0
8011838: 20030000 .word 0x20030000
801183c: 200007c0 .word 0x200007c0
8011840: 200007c4 .word 0x200007c4
08011844 <TL_SYS_SendCmd>:
int32_t TL_SYS_SendCmd( uint8_t* buffer, uint16_t size )
{
8011844: b580 push {r7, lr}
8011846: b082 sub sp, #8
8011848: af00 add r7, sp, #0
801184a: 6078 str r0, [r7, #4]
801184c: 460b mov r3, r1
801184e: 807b strh r3, [r7, #2]
(void)(buffer);
(void)(size);
((TL_CmdPacket_t *)(TL_RefTable.p_sys_table->pcmd_buffer))->cmdserial.type = TL_SYSCMD_PKT_TYPE;
8011850: 4b09 ldr r3, [pc, #36] @ (8011878 <TL_SYS_SendCmd+0x34>)
8011852: 68db ldr r3, [r3, #12]
8011854: 681b ldr r3, [r3, #0]
8011856: 2210 movs r2, #16
8011858: 721a strb r2, [r3, #8]
OutputDbgTrace(TL_MB_SYS_CMD, TL_RefTable.p_sys_table->pcmd_buffer);
801185a: 4b07 ldr r3, [pc, #28] @ (8011878 <TL_SYS_SendCmd+0x34>)
801185c: 68db ldr r3, [r3, #12]
801185e: 681b ldr r3, [r3, #0]
8011860: 4619 mov r1, r3
8011862: 2006 movs r0, #6
8011864: f000 f8ec bl 8011a40 <OutputDbgTrace>
HW_IPCC_SYS_SendCmd();
8011868: f005 f9c0 bl 8016bec <HW_IPCC_SYS_SendCmd>
return 0;
801186c: 2300 movs r3, #0
}
801186e: 4618 mov r0, r3
8011870: 3708 adds r7, #8
8011872: 46bd mov sp, r7
8011874: bd80 pop {r7, pc}
8011876: bf00 nop
8011878: 20030000 .word 0x20030000
0801187c <HW_IPCC_SYS_CmdEvtNot>:
void HW_IPCC_SYS_CmdEvtNot(void)
{
801187c: b580 push {r7, lr}
801187e: af00 add r7, sp, #0
OutputDbgTrace(TL_MB_SYS_CMD_RSP, (uint8_t*)(TL_RefTable.p_sys_table->pcmd_buffer) );
8011880: 4b07 ldr r3, [pc, #28] @ (80118a0 <HW_IPCC_SYS_CmdEvtNot+0x24>)
8011882: 68db ldr r3, [r3, #12]
8011884: 681b ldr r3, [r3, #0]
8011886: 4619 mov r1, r3
8011888: 2007 movs r0, #7
801188a: f000 f8d9 bl 8011a40 <OutputDbgTrace>
SYS_CMD_IoBusCallBackFunction( (TL_EvtPacket_t*)(TL_RefTable.p_sys_table->pcmd_buffer) );
801188e: 4b05 ldr r3, [pc, #20] @ (80118a4 <HW_IPCC_SYS_CmdEvtNot+0x28>)
8011890: 681b ldr r3, [r3, #0]
8011892: 4a03 ldr r2, [pc, #12] @ (80118a0 <HW_IPCC_SYS_CmdEvtNot+0x24>)
8011894: 68d2 ldr r2, [r2, #12]
8011896: 6812 ldr r2, [r2, #0]
8011898: 4610 mov r0, r2
801189a: 4798 blx r3
return;
801189c: bf00 nop
}
801189e: bd80 pop {r7, pc}
80118a0: 20030000 .word 0x20030000
80118a4: 200007c0 .word 0x200007c0
080118a8 <HW_IPCC_SYS_EvtNot>:
void HW_IPCC_SYS_EvtNot( void )
{
80118a8: b580 push {r7, lr}
80118aa: b082 sub sp, #8
80118ac: af00 add r7, sp, #0
TL_EvtPacket_t *p_evt;
while(LST_is_empty(&SystemEvtQueue) == FALSE)
80118ae: e00e b.n 80118ce <HW_IPCC_SYS_EvtNot+0x26>
{
LST_remove_head (&SystemEvtQueue, (tListNode **)&p_evt);
80118b0: 1d3b adds r3, r7, #4
80118b2: 4619 mov r1, r3
80118b4: 480b ldr r0, [pc, #44] @ (80118e4 <HW_IPCC_SYS_EvtNot+0x3c>)
80118b6: f000 f9e8 bl 8011c8a <LST_remove_head>
OutputDbgTrace(TL_MB_SYS_ASYNCH_EVT, (uint8_t*)p_evt );
80118ba: 687b ldr r3, [r7, #4]
80118bc: 4619 mov r1, r3
80118be: 2008 movs r0, #8
80118c0: f000 f8be bl 8011a40 <OutputDbgTrace>
SYS_EVT_IoBusCallBackFunction( p_evt );
80118c4: 4b08 ldr r3, [pc, #32] @ (80118e8 <HW_IPCC_SYS_EvtNot+0x40>)
80118c6: 681b ldr r3, [r3, #0]
80118c8: 687a ldr r2, [r7, #4]
80118ca: 4610 mov r0, r2
80118cc: 4798 blx r3
while(LST_is_empty(&SystemEvtQueue) == FALSE)
80118ce: 4805 ldr r0, [pc, #20] @ (80118e4 <HW_IPCC_SYS_EvtNot+0x3c>)
80118d0: f000 f94c bl 8011b6c <LST_is_empty>
80118d4: 4603 mov r3, r0
80118d6: 2b00 cmp r3, #0
80118d8: d0ea beq.n 80118b0 <HW_IPCC_SYS_EvtNot+0x8>
}
return;
80118da: bf00 nop
}
80118dc: 3708 adds r7, #8
80118de: 46bd mov sp, r7
80118e0: bd80 pop {r7, pc}
80118e2: bf00 nop
80118e4: 200300d0 .word 0x200300d0
80118e8: 200007c4 .word 0x200007c4
080118ec <TL_MM_Init>:
/******************************************************************************
* MEMORY MANAGER
******************************************************************************/
void TL_MM_Init( TL_MM_Config_t *p_Config )
{
80118ec: b580 push {r7, lr}
80118ee: b082 sub sp, #8
80118f0: af00 add r7, sp, #0
80118f2: 6078 str r0, [r7, #4]
static MB_MemManagerTable_t * p_mem_manager_table;
LST_init_head (&FreeBufQueue);
80118f4: 4817 ldr r0, [pc, #92] @ (8011954 <TL_MM_Init+0x68>)
80118f6: f000 f929 bl 8011b4c <LST_init_head>
LST_init_head (&LocalFreeBufQueue);
80118fa: 4817 ldr r0, [pc, #92] @ (8011958 <TL_MM_Init+0x6c>)
80118fc: f000 f926 bl 8011b4c <LST_init_head>
p_mem_manager_table = TL_RefTable.p_mem_manager_table;
8011900: 4b16 ldr r3, [pc, #88] @ (801195c <TL_MM_Init+0x70>)
8011902: 691b ldr r3, [r3, #16]
8011904: 4a16 ldr r2, [pc, #88] @ (8011960 <TL_MM_Init+0x74>)
8011906: 6013 str r3, [r2, #0]
p_mem_manager_table->blepool = p_Config->p_AsynchEvtPool;
8011908: 4b15 ldr r3, [pc, #84] @ (8011960 <TL_MM_Init+0x74>)
801190a: 681b ldr r3, [r3, #0]
801190c: 687a ldr r2, [r7, #4]
801190e: 6892 ldr r2, [r2, #8]
8011910: 609a str r2, [r3, #8]
p_mem_manager_table->blepoolsize = p_Config->AsynchEvtPoolSize;
8011912: 4b13 ldr r3, [pc, #76] @ (8011960 <TL_MM_Init+0x74>)
8011914: 681b ldr r3, [r3, #0]
8011916: 687a ldr r2, [r7, #4]
8011918: 68d2 ldr r2, [r2, #12]
801191a: 60da str r2, [r3, #12]
p_mem_manager_table->pevt_free_buffer_queue = (uint8_t*)&FreeBufQueue;
801191c: 4b10 ldr r3, [pc, #64] @ (8011960 <TL_MM_Init+0x74>)
801191e: 681b ldr r3, [r3, #0]
8011920: 4a0c ldr r2, [pc, #48] @ (8011954 <TL_MM_Init+0x68>)
8011922: 611a str r2, [r3, #16]
p_mem_manager_table->spare_ble_buffer = p_Config->p_BleSpareEvtBuffer;
8011924: 4b0e ldr r3, [pc, #56] @ (8011960 <TL_MM_Init+0x74>)
8011926: 681b ldr r3, [r3, #0]
8011928: 687a ldr r2, [r7, #4]
801192a: 6812 ldr r2, [r2, #0]
801192c: 601a str r2, [r3, #0]
p_mem_manager_table->spare_sys_buffer = p_Config->p_SystemSpareEvtBuffer;
801192e: 4b0c ldr r3, [pc, #48] @ (8011960 <TL_MM_Init+0x74>)
8011930: 681b ldr r3, [r3, #0]
8011932: 687a ldr r2, [r7, #4]
8011934: 6852 ldr r2, [r2, #4]
8011936: 605a str r2, [r3, #4]
p_mem_manager_table->traces_evt_pool = p_Config->p_TracesEvtPool;
8011938: 4b09 ldr r3, [pc, #36] @ (8011960 <TL_MM_Init+0x74>)
801193a: 681b ldr r3, [r3, #0]
801193c: 687a ldr r2, [r7, #4]
801193e: 6912 ldr r2, [r2, #16]
8011940: 615a str r2, [r3, #20]
p_mem_manager_table->tracespoolsize = p_Config->TracesEvtPoolSize;
8011942: 4b07 ldr r3, [pc, #28] @ (8011960 <TL_MM_Init+0x74>)
8011944: 681b ldr r3, [r3, #0]
8011946: 687a ldr r2, [r7, #4]
8011948: 6952 ldr r2, [r2, #20]
801194a: 619a str r2, [r3, #24]
return;
801194c: bf00 nop
}
801194e: 3708 adds r7, #8
8011950: 46bd mov sp, r7
8011952: bd80 pop {r7, pc}
8011954: 200300b8 .word 0x200300b8
8011958: 200007b0 .word 0x200007b0
801195c: 20030000 .word 0x20030000
8011960: 200007c8 .word 0x200007c8
08011964 <TL_MM_EvtDone>:
void TL_MM_EvtDone(TL_EvtPacket_t * phcievt)
{
8011964: b580 push {r7, lr}
8011966: b082 sub sp, #8
8011968: af00 add r7, sp, #0
801196a: 6078 str r0, [r7, #4]
LST_insert_tail(&LocalFreeBufQueue, (tListNode *)phcievt);
801196c: 6879 ldr r1, [r7, #4]
801196e: 4807 ldr r0, [pc, #28] @ (801198c <TL_MM_EvtDone+0x28>)
8011970: f000 f944 bl 8011bfc <LST_insert_tail>
OutputDbgTrace(TL_MB_MM_RELEASE_BUFFER, (uint8_t*)phcievt);
8011974: 6879 ldr r1, [r7, #4]
8011976: 2000 movs r0, #0
8011978: f000 f862 bl 8011a40 <OutputDbgTrace>
HW_IPCC_MM_SendFreeBuf( SendFreeBuf );
801197c: 4804 ldr r0, [pc, #16] @ (8011990 <TL_MM_EvtDone+0x2c>)
801197e: f005 f97b bl 8016c78 <HW_IPCC_MM_SendFreeBuf>
return;
8011982: bf00 nop
}
8011984: 3708 adds r7, #8
8011986: 46bd mov sp, r7
8011988: bd80 pop {r7, pc}
801198a: bf00 nop
801198c: 200007b0 .word 0x200007b0
8011990: 08011995 .word 0x08011995
08011994 <SendFreeBuf>:
static void SendFreeBuf( void )
{
8011994: b580 push {r7, lr}
8011996: b082 sub sp, #8
8011998: af00 add r7, sp, #0
tListNode *p_node;
while ( FALSE == LST_is_empty (&LocalFreeBufQueue) )
801199a: e00c b.n 80119b6 <SendFreeBuf+0x22>
{
LST_remove_head( &LocalFreeBufQueue, (tListNode **)&p_node );
801199c: 1d3b adds r3, r7, #4
801199e: 4619 mov r1, r3
80119a0: 480a ldr r0, [pc, #40] @ (80119cc <SendFreeBuf+0x38>)
80119a2: f000 f972 bl 8011c8a <LST_remove_head>
LST_insert_tail( (tListNode*)(TL_RefTable.p_mem_manager_table->pevt_free_buffer_queue), p_node );
80119a6: 4b0a ldr r3, [pc, #40] @ (80119d0 <SendFreeBuf+0x3c>)
80119a8: 691b ldr r3, [r3, #16]
80119aa: 691b ldr r3, [r3, #16]
80119ac: 687a ldr r2, [r7, #4]
80119ae: 4611 mov r1, r2
80119b0: 4618 mov r0, r3
80119b2: f000 f923 bl 8011bfc <LST_insert_tail>
while ( FALSE == LST_is_empty (&LocalFreeBufQueue) )
80119b6: 4805 ldr r0, [pc, #20] @ (80119cc <SendFreeBuf+0x38>)
80119b8: f000 f8d8 bl 8011b6c <LST_is_empty>
80119bc: 4603 mov r3, r0
80119be: 2b00 cmp r3, #0
80119c0: d0ec beq.n 801199c <SendFreeBuf+0x8>
}
return;
80119c2: bf00 nop
}
80119c4: 3708 adds r7, #8
80119c6: 46bd mov sp, r7
80119c8: bd80 pop {r7, pc}
80119ca: bf00 nop
80119cc: 200007b0 .word 0x200007b0
80119d0: 20030000 .word 0x20030000
080119d4 <TL_TRACES_Init>:
/******************************************************************************
* TRACES
******************************************************************************/
void TL_TRACES_Init( void )
{
80119d4: b580 push {r7, lr}
80119d6: af00 add r7, sp, #0
LST_init_head (&TracesEvtQueue);
80119d8: 4805 ldr r0, [pc, #20] @ (80119f0 <TL_TRACES_Init+0x1c>)
80119da: f000 f8b7 bl 8011b4c <LST_init_head>
TL_RefTable.p_traces_table->traces_queue = (uint8_t*)&TracesEvtQueue;
80119de: 4b05 ldr r3, [pc, #20] @ (80119f4 <TL_TRACES_Init+0x20>)
80119e0: 695b ldr r3, [r3, #20]
80119e2: 4a03 ldr r2, [pc, #12] @ (80119f0 <TL_TRACES_Init+0x1c>)
80119e4: 601a str r2, [r3, #0]
HW_IPCC_TRACES_Init();
80119e6: f005 f999 bl 8016d1c <HW_IPCC_TRACES_Init>
return;
80119ea: bf00 nop
}
80119ec: bd80 pop {r7, pc}
80119ee: bf00 nop
80119f0: 200300c0 .word 0x200300c0
80119f4: 20030000 .word 0x20030000
080119f8 <HW_IPCC_TRACES_EvtNot>:
void HW_IPCC_TRACES_EvtNot(void)
{
80119f8: b580 push {r7, lr}
80119fa: b082 sub sp, #8
80119fc: af00 add r7, sp, #0
TL_EvtPacket_t *phcievt;
while(LST_is_empty(&TracesEvtQueue) == FALSE)
80119fe: e008 b.n 8011a12 <HW_IPCC_TRACES_EvtNot+0x1a>
{
LST_remove_head (&TracesEvtQueue, (tListNode **)&phcievt);
8011a00: 1d3b adds r3, r7, #4
8011a02: 4619 mov r1, r3
8011a04: 4808 ldr r0, [pc, #32] @ (8011a28 <HW_IPCC_TRACES_EvtNot+0x30>)
8011a06: f000 f940 bl 8011c8a <LST_remove_head>
TL_TRACES_EvtReceived( phcievt );
8011a0a: 687b ldr r3, [r7, #4]
8011a0c: 4618 mov r0, r3
8011a0e: f000 f80d bl 8011a2c <TL_TRACES_EvtReceived>
while(LST_is_empty(&TracesEvtQueue) == FALSE)
8011a12: 4805 ldr r0, [pc, #20] @ (8011a28 <HW_IPCC_TRACES_EvtNot+0x30>)
8011a14: f000 f8aa bl 8011b6c <LST_is_empty>
8011a18: 4603 mov r3, r0
8011a1a: 2b00 cmp r3, #0
8011a1c: d0f0 beq.n 8011a00 <HW_IPCC_TRACES_EvtNot+0x8>
}
return;
8011a1e: bf00 nop
}
8011a20: 3708 adds r7, #8
8011a22: 46bd mov sp, r7
8011a24: bd80 pop {r7, pc}
8011a26: bf00 nop
8011a28: 200300c0 .word 0x200300c0
08011a2c <TL_TRACES_EvtReceived>:
__WEAK void TL_TRACES_EvtReceived( TL_EvtPacket_t * hcievt )
{
8011a2c: b480 push {r7}
8011a2e: b083 sub sp, #12
8011a30: af00 add r7, sp, #0
8011a32: 6078 str r0, [r7, #4]
(void)(hcievt);
}
8011a34: bf00 nop
8011a36: 370c adds r7, #12
8011a38: 46bd mov sp, r7
8011a3a: f85d 7b04 ldr.w r7, [sp], #4
8011a3e: 4770 bx lr
08011a40 <OutputDbgTrace>:
/******************************************************************************
* DEBUG INFORMATION
******************************************************************************/
static void OutputDbgTrace(TL_MB_PacketType_t packet_type, uint8_t* buffer)
{
8011a40: b480 push {r7}
8011a42: b087 sub sp, #28
8011a44: af00 add r7, sp, #0
8011a46: 4603 mov r3, r0
8011a48: 6039 str r1, [r7, #0]
8011a4a: 71fb strb r3, [r7, #7]
TL_EvtPacket_t *p_evt_packet;
TL_CmdPacket_t *p_cmd_packet;
TL_AclDataPacket_t *p_acldata_packet;
TL_EvtSerial_t *p_cmd_rsp_packet;
switch(packet_type)
8011a4c: 79fb ldrb r3, [r7, #7]
8011a4e: 2b08 cmp r3, #8
8011a50: d84c bhi.n 8011aec <OutputDbgTrace+0xac>
8011a52: a201 add r2, pc, #4 @ (adr r2, 8011a58 <OutputDbgTrace+0x18>)
8011a54: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8011a58: 08011a7d .word 0x08011a7d
8011a5c: 08011aa1 .word 0x08011aa1
8011a60: 08011aad .word 0x08011aad
8011a64: 08011aa7 .word 0x08011aa7
8011a68: 08011aed .word 0x08011aed
8011a6c: 08011ac1 .word 0x08011ac1
8011a70: 08011acd .word 0x08011acd
8011a74: 08011ad3 .word 0x08011ad3
8011a78: 08011ae1 .word 0x08011ae1
{
case TL_MB_MM_RELEASE_BUFFER:
p_evt_packet = (TL_EvtPacket_t*)buffer;
8011a7c: 683b ldr r3, [r7, #0]
8011a7e: 617b str r3, [r7, #20]
switch(p_evt_packet->evtserial.evt.evtcode)
8011a80: 697b ldr r3, [r7, #20]
8011a82: 7a5b ldrb r3, [r3, #9]
8011a84: 2bff cmp r3, #255 @ 0xff
8011a86: d005 beq.n 8011a94 <OutputDbgTrace+0x54>
8011a88: 2bff cmp r3, #255 @ 0xff
8011a8a: dc05 bgt.n 8011a98 <OutputDbgTrace+0x58>
8011a8c: 2b0e cmp r3, #14
8011a8e: d005 beq.n 8011a9c <OutputDbgTrace+0x5c>
8011a90: 2b0f cmp r3, #15
break;
default:
TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet);
break;
8011a92: e001 b.n 8011a98 <OutputDbgTrace+0x58>
break;
8011a94: bf00 nop
8011a96: e02a b.n 8011aee <OutputDbgTrace+0xae>
break;
8011a98: bf00 nop
8011a9a: e028 b.n 8011aee <OutputDbgTrace+0xae>
break;
8011a9c: bf00 nop
}
TL_MM_DBG_MSG("\r\n");
break;
8011a9e: e026 b.n 8011aee <OutputDbgTrace+0xae>
case TL_MB_BLE_CMD:
p_cmd_packet = (TL_CmdPacket_t*)buffer;
8011aa0: 683b ldr r3, [r7, #0]
8011aa2: 60fb str r3, [r7, #12]
TL_HCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, "");
}
TL_HCI_CMD_DBG_MSG("\r\n");
TL_HCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE);
break;
8011aa4: e023 b.n 8011aee <OutputDbgTrace+0xae>
case TL_MB_ACL_DATA:
(void)p_acldata_packet;
p_acldata_packet = (TL_AclDataPacket_t*)buffer;
8011aa6: 683b ldr r3, [r7, #0]
8011aa8: 60bb str r3, [r7, #8]
TL_HCI_CMD_DBG_MSG(" payload:");
TL_HCI_CMD_DBG_BUF(p_acldata_packet->AclDataSerial.acl_data, p_acldata_packet->AclDataSerial.length, "");
}*/
TL_HCI_CMD_DBG_MSG("\r\n");
/*TL_HCI_CMD_DBG_RAW(&p_acldata_packet->AclDataSerial, p_acldata_packet->AclDataSerial.length+TL_CMD_HDR_SIZE);*/
break;
8011aaa: e020 b.n 8011aee <OutputDbgTrace+0xae>
TL_HCI_CMD_DBG_MSG(" ACL Data Tx Ack received");
TL_HCI_CMD_DBG_MSG("\r\n");
break;
case TL_MB_BLE_CMD_RSP:
p_evt_packet = (TL_EvtPacket_t*)buffer;
8011aac: 683b ldr r3, [r7, #0]
8011aae: 617b str r3, [r7, #20]
switch(p_evt_packet->evtserial.evt.evtcode)
8011ab0: 697b ldr r3, [r7, #20]
8011ab2: 7a5b ldrb r3, [r3, #9]
8011ab4: 2b0e cmp r3, #14
8011ab6: d001 beq.n 8011abc <OutputDbgTrace+0x7c>
8011ab8: 2b0f cmp r3, #15
}
break;
default:
TL_HCI_CMD_DBG_MSG("unknown ble rsp received: %02X", p_evt_packet->evtserial.evt.evtcode);
break;
8011aba: e000 b.n 8011abe <OutputDbgTrace+0x7e>
break;
8011abc: bf00 nop
}
TL_HCI_CMD_DBG_MSG("\r\n");
TL_HCI_CMD_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
break;
8011abe: e016 b.n 8011aee <OutputDbgTrace+0xae>
case TL_MB_BLE_ASYNCH_EVT:
p_evt_packet = (TL_EvtPacket_t*)buffer;
8011ac0: 683b ldr r3, [r7, #0]
8011ac2: 617b str r3, [r7, #20]
if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE)
8011ac4: 697b ldr r3, [r7, #20]
8011ac6: 7a5b ldrb r3, [r3, #9]
8011ac8: 2bff cmp r3, #255 @ 0xff
}
TL_HCI_EVT_DBG_MSG("\r\n");
TL_HCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
break;
8011aca: e010 b.n 8011aee <OutputDbgTrace+0xae>
case TL_MB_SYS_CMD:
p_cmd_packet = (TL_CmdPacket_t*)buffer;
8011acc: 683b ldr r3, [r7, #0]
8011ace: 60fb str r3, [r7, #12]
TL_SHCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, "");
}
TL_SHCI_CMD_DBG_MSG("\r\n");
TL_SHCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE);
break;
8011ad0: e00d b.n 8011aee <OutputDbgTrace+0xae>
case TL_MB_SYS_CMD_RSP:
p_cmd_rsp_packet = (TL_EvtSerial_t*)buffer;
8011ad2: 683b ldr r3, [r7, #0]
8011ad4: 613b str r3, [r7, #16]
switch(p_cmd_rsp_packet->evt.evtcode)
8011ad6: 693b ldr r3, [r7, #16]
8011ad8: 785b ldrb r3, [r3, #1]
8011ada: 2b0e cmp r3, #14
}
break;
default:
TL_SHCI_CMD_DBG_MSG("unknown sys rsp received: %02X", p_cmd_rsp_packet->evt.evtcode);
break;
8011adc: bf00 nop
}
TL_SHCI_CMD_DBG_MSG("\r\n");
TL_SHCI_CMD_DBG_RAW(&p_cmd_rsp_packet->evt, p_cmd_rsp_packet->evt.plen+TL_EVT_HDR_SIZE);
break;
8011ade: e006 b.n 8011aee <OutputDbgTrace+0xae>
case TL_MB_SYS_ASYNCH_EVT:
p_evt_packet = (TL_EvtPacket_t*)buffer;
8011ae0: 683b ldr r3, [r7, #0]
8011ae2: 617b str r3, [r7, #20]
if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE)
8011ae4: 697b ldr r3, [r7, #20]
8011ae6: 7a5b ldrb r3, [r3, #9]
8011ae8: 2bff cmp r3, #255 @ 0xff
}
TL_SHCI_EVT_DBG_MSG("\r\n");
TL_SHCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
break;
8011aea: e000 b.n 8011aee <OutputDbgTrace+0xae>
default:
break;
8011aec: bf00 nop
}
return;
8011aee: bf00 nop
}
8011af0: 371c adds r7, #28
8011af2: 46bd mov sp, r7
8011af4: f85d 7b04 ldr.w r7, [sp], #4
8011af8: 4770 bx lr
8011afa: bf00 nop
08011afc <OTP_Read>:
/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Functions Definition ------------------------------------------------------*/
uint8_t * OTP_Read( uint8_t id )
{
8011afc: b480 push {r7}
8011afe: b085 sub sp, #20
8011b00: af00 add r7, sp, #0
8011b02: 4603 mov r3, r0
8011b04: 71fb strb r3, [r7, #7]
uint8_t *p_id;
p_id = (uint8_t*)(CFG_OTP_END_ADRESS - 7) ;
8011b06: 4b0f ldr r3, [pc, #60] @ (8011b44 <OTP_Read+0x48>)
8011b08: 60fb str r3, [r7, #12]
while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) )
8011b0a: e002 b.n 8011b12 <OTP_Read+0x16>
{
p_id -= 8 ;
8011b0c: 68fb ldr r3, [r7, #12]
8011b0e: 3b08 subs r3, #8
8011b10: 60fb str r3, [r7, #12]
while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) )
8011b12: 68fb ldr r3, [r7, #12]
8011b14: 3307 adds r3, #7
8011b16: 781b ldrb r3, [r3, #0]
8011b18: 79fa ldrb r2, [r7, #7]
8011b1a: 429a cmp r2, r3
8011b1c: d003 beq.n 8011b26 <OTP_Read+0x2a>
8011b1e: 68fb ldr r3, [r7, #12]
8011b20: 4a09 ldr r2, [pc, #36] @ (8011b48 <OTP_Read+0x4c>)
8011b22: 4293 cmp r3, r2
8011b24: d1f2 bne.n 8011b0c <OTP_Read+0x10>
}
if((*( p_id + 7 )) != id)
8011b26: 68fb ldr r3, [r7, #12]
8011b28: 3307 adds r3, #7
8011b2a: 781b ldrb r3, [r3, #0]
8011b2c: 79fa ldrb r2, [r7, #7]
8011b2e: 429a cmp r2, r3
8011b30: d001 beq.n 8011b36 <OTP_Read+0x3a>
{
p_id = 0 ;
8011b32: 2300 movs r3, #0
8011b34: 60fb str r3, [r7, #12]
}
return p_id ;
8011b36: 68fb ldr r3, [r7, #12]
}
8011b38: 4618 mov r0, r3
8011b3a: 3714 adds r7, #20
8011b3c: 46bd mov sp, r7
8011b3e: f85d 7b04 ldr.w r7, [sp], #4
8011b42: 4770 bx lr
8011b44: 1fff73f8 .word 0x1fff73f8
8011b48: 1fff7000 .word 0x1fff7000
08011b4c <LST_init_head>:
/******************************************************************************
* Function Definitions
******************************************************************************/
void LST_init_head (tListNode * listHead)
{
8011b4c: b480 push {r7}
8011b4e: b083 sub sp, #12
8011b50: af00 add r7, sp, #0
8011b52: 6078 str r0, [r7, #4]
listHead->next = listHead;
8011b54: 687b ldr r3, [r7, #4]
8011b56: 687a ldr r2, [r7, #4]
8011b58: 601a str r2, [r3, #0]
listHead->prev = listHead;
8011b5a: 687b ldr r3, [r7, #4]
8011b5c: 687a ldr r2, [r7, #4]
8011b5e: 605a str r2, [r3, #4]
}
8011b60: bf00 nop
8011b62: 370c adds r7, #12
8011b64: 46bd mov sp, r7
8011b66: f85d 7b04 ldr.w r7, [sp], #4
8011b6a: 4770 bx lr
08011b6c <LST_is_empty>:
uint8_t LST_is_empty (tListNode * listHead)
{
8011b6c: b480 push {r7}
8011b6e: b087 sub sp, #28
8011b70: af00 add r7, sp, #0
8011b72: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8011b74: f3ef 8310 mrs r3, PRIMASK
8011b78: 60fb str r3, [r7, #12]
return(result);
8011b7a: 68fb ldr r3, [r7, #12]
uint32_t primask_bit;
uint8_t return_value;
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
8011b7c: 613b str r3, [r7, #16]
__ASM volatile ("cpsid i" : : : "memory");
8011b7e: b672 cpsid i
}
8011b80: bf00 nop
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
if(listHead->next == listHead)
8011b82: 687b ldr r3, [r7, #4]
8011b84: 681b ldr r3, [r3, #0]
8011b86: 687a ldr r2, [r7, #4]
8011b88: 429a cmp r2, r3
8011b8a: d102 bne.n 8011b92 <LST_is_empty+0x26>
{
return_value = TRUE;
8011b8c: 2301 movs r3, #1
8011b8e: 75fb strb r3, [r7, #23]
8011b90: e001 b.n 8011b96 <LST_is_empty+0x2a>
}
else
{
return_value = FALSE;
8011b92: 2300 movs r3, #0
8011b94: 75fb strb r3, [r7, #23]
8011b96: 693b ldr r3, [r7, #16]
8011b98: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8011b9a: 68bb ldr r3, [r7, #8]
8011b9c: f383 8810 msr PRIMASK, r3
}
8011ba0: bf00 nop
}
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
return return_value;
8011ba2: 7dfb ldrb r3, [r7, #23]
}
8011ba4: 4618 mov r0, r3
8011ba6: 371c adds r7, #28
8011ba8: 46bd mov sp, r7
8011baa: f85d 7b04 ldr.w r7, [sp], #4
8011bae: 4770 bx lr
08011bb0 <LST_insert_head>:
void LST_insert_head (tListNode * listHead, tListNode * node)
{
8011bb0: b480 push {r7}
8011bb2: b087 sub sp, #28
8011bb4: af00 add r7, sp, #0
8011bb6: 6078 str r0, [r7, #4]
8011bb8: 6039 str r1, [r7, #0]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8011bba: f3ef 8310 mrs r3, PRIMASK
8011bbe: 60fb str r3, [r7, #12]
return(result);
8011bc0: 68fb ldr r3, [r7, #12]
uint32_t primask_bit;
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
8011bc2: 617b str r3, [r7, #20]
__ASM volatile ("cpsid i" : : : "memory");
8011bc4: b672 cpsid i
}
8011bc6: bf00 nop
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
node->next = listHead->next;
8011bc8: 687b ldr r3, [r7, #4]
8011bca: 681a ldr r2, [r3, #0]
8011bcc: 683b ldr r3, [r7, #0]
8011bce: 601a str r2, [r3, #0]
node->prev = listHead;
8011bd0: 683b ldr r3, [r7, #0]
8011bd2: 687a ldr r2, [r7, #4]
8011bd4: 605a str r2, [r3, #4]
listHead->next = node;
8011bd6: 687b ldr r3, [r7, #4]
8011bd8: 683a ldr r2, [r7, #0]
8011bda: 601a str r2, [r3, #0]
(node->next)->prev = node;
8011bdc: 683b ldr r3, [r7, #0]
8011bde: 681b ldr r3, [r3, #0]
8011be0: 683a ldr r2, [r7, #0]
8011be2: 605a str r2, [r3, #4]
8011be4: 697b ldr r3, [r7, #20]
8011be6: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8011be8: 693b ldr r3, [r7, #16]
8011bea: f383 8810 msr PRIMASK, r3
}
8011bee: bf00 nop
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
}
8011bf0: bf00 nop
8011bf2: 371c adds r7, #28
8011bf4: 46bd mov sp, r7
8011bf6: f85d 7b04 ldr.w r7, [sp], #4
8011bfa: 4770 bx lr
08011bfc <LST_insert_tail>:
void LST_insert_tail (tListNode * listHead, tListNode * node)
{
8011bfc: b480 push {r7}
8011bfe: b087 sub sp, #28
8011c00: af00 add r7, sp, #0
8011c02: 6078 str r0, [r7, #4]
8011c04: 6039 str r1, [r7, #0]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8011c06: f3ef 8310 mrs r3, PRIMASK
8011c0a: 60fb str r3, [r7, #12]
return(result);
8011c0c: 68fb ldr r3, [r7, #12]
uint32_t primask_bit;
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
8011c0e: 617b str r3, [r7, #20]
__ASM volatile ("cpsid i" : : : "memory");
8011c10: b672 cpsid i
}
8011c12: bf00 nop
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
node->next = listHead;
8011c14: 683b ldr r3, [r7, #0]
8011c16: 687a ldr r2, [r7, #4]
8011c18: 601a str r2, [r3, #0]
node->prev = listHead->prev;
8011c1a: 687b ldr r3, [r7, #4]
8011c1c: 685a ldr r2, [r3, #4]
8011c1e: 683b ldr r3, [r7, #0]
8011c20: 605a str r2, [r3, #4]
listHead->prev = node;
8011c22: 687b ldr r3, [r7, #4]
8011c24: 683a ldr r2, [r7, #0]
8011c26: 605a str r2, [r3, #4]
(node->prev)->next = node;
8011c28: 683b ldr r3, [r7, #0]
8011c2a: 685b ldr r3, [r3, #4]
8011c2c: 683a ldr r2, [r7, #0]
8011c2e: 601a str r2, [r3, #0]
8011c30: 697b ldr r3, [r7, #20]
8011c32: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8011c34: 693b ldr r3, [r7, #16]
8011c36: f383 8810 msr PRIMASK, r3
}
8011c3a: bf00 nop
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
}
8011c3c: bf00 nop
8011c3e: 371c adds r7, #28
8011c40: 46bd mov sp, r7
8011c42: f85d 7b04 ldr.w r7, [sp], #4
8011c46: 4770 bx lr
08011c48 <LST_remove_node>:
void LST_remove_node (tListNode * node)
{
8011c48: b480 push {r7}
8011c4a: b087 sub sp, #28
8011c4c: af00 add r7, sp, #0
8011c4e: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8011c50: f3ef 8310 mrs r3, PRIMASK
8011c54: 60fb str r3, [r7, #12]
return(result);
8011c56: 68fb ldr r3, [r7, #12]
uint32_t primask_bit;
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
8011c58: 617b str r3, [r7, #20]
__ASM volatile ("cpsid i" : : : "memory");
8011c5a: b672 cpsid i
}
8011c5c: bf00 nop
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
(node->prev)->next = node->next;
8011c5e: 687b ldr r3, [r7, #4]
8011c60: 685b ldr r3, [r3, #4]
8011c62: 687a ldr r2, [r7, #4]
8011c64: 6812 ldr r2, [r2, #0]
8011c66: 601a str r2, [r3, #0]
(node->next)->prev = node->prev;
8011c68: 687b ldr r3, [r7, #4]
8011c6a: 681b ldr r3, [r3, #0]
8011c6c: 687a ldr r2, [r7, #4]
8011c6e: 6852 ldr r2, [r2, #4]
8011c70: 605a str r2, [r3, #4]
8011c72: 697b ldr r3, [r7, #20]
8011c74: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8011c76: 693b ldr r3, [r7, #16]
8011c78: f383 8810 msr PRIMASK, r3
}
8011c7c: bf00 nop
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
}
8011c7e: bf00 nop
8011c80: 371c adds r7, #28
8011c82: 46bd mov sp, r7
8011c84: f85d 7b04 ldr.w r7, [sp], #4
8011c88: 4770 bx lr
08011c8a <LST_remove_head>:
void LST_remove_head (tListNode * listHead, tListNode ** node )
{
8011c8a: b580 push {r7, lr}
8011c8c: b086 sub sp, #24
8011c8e: af00 add r7, sp, #0
8011c90: 6078 str r0, [r7, #4]
8011c92: 6039 str r1, [r7, #0]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8011c94: f3ef 8310 mrs r3, PRIMASK
8011c98: 60fb str r3, [r7, #12]
return(result);
8011c9a: 68fb ldr r3, [r7, #12]
uint32_t primask_bit;
primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */
8011c9c: 617b str r3, [r7, #20]
__ASM volatile ("cpsid i" : : : "memory");
8011c9e: b672 cpsid i
}
8011ca0: bf00 nop
__disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/
*node = listHead->next;
8011ca2: 687b ldr r3, [r7, #4]
8011ca4: 681a ldr r2, [r3, #0]
8011ca6: 683b ldr r3, [r7, #0]
8011ca8: 601a str r2, [r3, #0]
LST_remove_node (listHead->next);
8011caa: 687b ldr r3, [r7, #4]
8011cac: 681b ldr r3, [r3, #0]
8011cae: 4618 mov r0, r3
8011cb0: f7ff ffca bl 8011c48 <LST_remove_node>
8011cb4: 697b ldr r3, [r7, #20]
8011cb6: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8011cb8: 693b ldr r3, [r7, #16]
8011cba: f383 8810 msr PRIMASK, r3
}
8011cbe: bf00 nop
__set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/
}
8011cc0: bf00 nop
8011cc2: 3718 adds r7, #24
8011cc4: 46bd mov sp, r7
8011cc6: bd80 pop {r7, pc}
08011cc8 <__NVIC_SetPriority>:
{
8011cc8: b480 push {r7}
8011cca: b083 sub sp, #12
8011ccc: af00 add r7, sp, #0
8011cce: 4603 mov r3, r0
8011cd0: 6039 str r1, [r7, #0]
8011cd2: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8011cd4: f997 3007 ldrsb.w r3, [r7, #7]
8011cd8: 2b00 cmp r3, #0
8011cda: db0a blt.n 8011cf2 <__NVIC_SetPriority+0x2a>
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8011cdc: 683b ldr r3, [r7, #0]
8011cde: b2da uxtb r2, r3
8011ce0: 490c ldr r1, [pc, #48] @ (8011d14 <__NVIC_SetPriority+0x4c>)
8011ce2: f997 3007 ldrsb.w r3, [r7, #7]
8011ce6: 0112 lsls r2, r2, #4
8011ce8: b2d2 uxtb r2, r2
8011cea: 440b add r3, r1
8011cec: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
8011cf0: e00a b.n 8011d08 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8011cf2: 683b ldr r3, [r7, #0]
8011cf4: b2da uxtb r2, r3
8011cf6: 4908 ldr r1, [pc, #32] @ (8011d18 <__NVIC_SetPriority+0x50>)
8011cf8: 79fb ldrb r3, [r7, #7]
8011cfa: f003 030f and.w r3, r3, #15
8011cfe: 3b04 subs r3, #4
8011d00: 0112 lsls r2, r2, #4
8011d02: b2d2 uxtb r2, r2
8011d04: 440b add r3, r1
8011d06: 761a strb r2, [r3, #24]
}
8011d08: bf00 nop
8011d0a: 370c adds r7, #12
8011d0c: 46bd mov sp, r7
8011d0e: f85d 7b04 ldr.w r7, [sp], #4
8011d12: 4770 bx lr
8011d14: e000e100 .word 0xe000e100
8011d18: e000ed00 .word 0xe000ed00
08011d1c <SysTick_Handler>:
/*
SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
8011d1c: b580 push {r7, lr}
8011d1e: af00 add r7, sp, #0
#if (configUSE_TICKLESS_IDLE == 0)
/* Clear overflow flag */
SysTick->CTRL;
8011d20: 4b05 ldr r3, [pc, #20] @ (8011d38 <SysTick_Handler+0x1c>)
8011d22: 681b ldr r3, [r3, #0]
#endif
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
8011d24: f002 ff62 bl 8014bec <xTaskGetSchedulerState>
8011d28: 4603 mov r3, r0
8011d2a: 2b01 cmp r3, #1
8011d2c: d001 beq.n 8011d32 <SysTick_Handler+0x16>
/* Call tick handler */
xPortSysTickHandler();
8011d2e: f004 fb0b bl 8016348 <xPortSysTickHandler>
}
}
8011d32: bf00 nop
8011d34: bd80 pop {r7, pc}
8011d36: bf00 nop
8011d38: e000e010 .word 0xe000e010
08011d3c <SVC_Setup>:
#endif /* SysTick */
/*
Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
8011d3c: b580 push {r7, lr}
8011d3e: af00 add r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
/* Service Call interrupt might be configured before kernel start */
/* and when its priority is lower or equal to BASEPRI, svc instruction */
/* causes a Hard Fault. */
NVIC_SetPriority (SVCall_IRQn, 0U);
8011d40: 2100 movs r1, #0
8011d42: f06f 0004 mvn.w r0, #4
8011d46: f7ff ffbf bl 8011cc8 <__NVIC_SetPriority>
#endif
}
8011d4a: bf00 nop
8011d4c: bd80 pop {r7, pc}
08011d4e <IRQ_Context>:
#endif
/*
Determine if CPU executes from interrupt context or if interrupts are masked.
*/
__STATIC_INLINE uint32_t IRQ_Context (void) {
8011d4e: b580 push {r7, lr}
8011d50: b086 sub sp, #24
8011d52: af00 add r7, sp, #0
uint32_t irq;
BaseType_t state;
irq = 0U;
8011d54: 2300 movs r3, #0
8011d56: 617b str r3, [r7, #20]
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
8011d58: f3ef 8305 mrs r3, IPSR
8011d5c: 60fb str r3, [r7, #12]
return(result);
8011d5e: 68fb ldr r3, [r7, #12]
if (IS_IRQ_MODE()) {
8011d60: 2b00 cmp r3, #0
8011d62: d002 beq.n 8011d6a <IRQ_Context+0x1c>
/* Called from interrupt context */
irq = 1U;
8011d64: 2301 movs r3, #1
8011d66: 617b str r3, [r7, #20]
8011d68: e013 b.n 8011d92 <IRQ_Context+0x44>
}
else {
/* Get FreeRTOS scheduler state */
state = xTaskGetSchedulerState();
8011d6a: f002 ff3f bl 8014bec <xTaskGetSchedulerState>
8011d6e: 6138 str r0, [r7, #16]
if (state != taskSCHEDULER_NOT_STARTED) {
8011d70: 693b ldr r3, [r7, #16]
8011d72: 2b01 cmp r3, #1
8011d74: d00d beq.n 8011d92 <IRQ_Context+0x44>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8011d76: f3ef 8310 mrs r3, PRIMASK
8011d7a: 60bb str r3, [r7, #8]
return(result);
8011d7c: 68bb ldr r3, [r7, #8]
/* Scheduler was started */
if (IS_IRQ_MASKED()) {
8011d7e: 2b00 cmp r3, #0
8011d80: d105 bne.n 8011d8e <IRQ_Context+0x40>
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
8011d82: f3ef 8311 mrs r3, BASEPRI
8011d86: 607b str r3, [r7, #4]
return(result);
8011d88: 687b ldr r3, [r7, #4]
8011d8a: 2b00 cmp r3, #0
8011d8c: d001 beq.n 8011d92 <IRQ_Context+0x44>
/* Interrupts are masked */
irq = 1U;
8011d8e: 2301 movs r3, #1
8011d90: 617b str r3, [r7, #20]
}
}
}
/* Return context, 0: thread context, 1: IRQ context */
return (irq);
8011d92: 697b ldr r3, [r7, #20]
}
8011d94: 4618 mov r0, r3
8011d96: 3718 adds r7, #24
8011d98: 46bd mov sp, r7
8011d9a: bd80 pop {r7, pc}
08011d9c <osKernelInitialize>:
/* ==== Kernel Management Functions ==== */
/*
Initialize the RTOS Kernel.
*/
osStatus_t osKernelInitialize (void) {
8011d9c: b580 push {r7, lr}
8011d9e: b082 sub sp, #8
8011da0: af00 add r7, sp, #0
osStatus_t stat;
BaseType_t state;
if (IRQ_Context() != 0U) {
8011da2: f7ff ffd4 bl 8011d4e <IRQ_Context>
8011da6: 4603 mov r3, r0
8011da8: 2b00 cmp r3, #0
8011daa: d003 beq.n 8011db4 <osKernelInitialize+0x18>
stat = osErrorISR;
8011dac: f06f 0305 mvn.w r3, #5
8011db0: 607b str r3, [r7, #4]
8011db2: e012 b.n 8011dda <osKernelInitialize+0x3e>
}
else {
state = xTaskGetSchedulerState();
8011db4: f002 ff1a bl 8014bec <xTaskGetSchedulerState>
8011db8: 6038 str r0, [r7, #0]
/* Initialize if scheduler not started and not initialized before */
if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelInactive)) {
8011dba: 683b ldr r3, [r7, #0]
8011dbc: 2b01 cmp r3, #1
8011dbe: d109 bne.n 8011dd4 <osKernelInitialize+0x38>
8011dc0: 4b08 ldr r3, [pc, #32] @ (8011de4 <osKernelInitialize+0x48>)
8011dc2: 681b ldr r3, [r3, #0]
8011dc4: 2b00 cmp r3, #0
8011dc6: d105 bne.n 8011dd4 <osKernelInitialize+0x38>
#endif
#if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
/* Initialize the memory regions when using heap_5 variant */
vPortDefineHeapRegions (configHEAP_5_REGIONS);
#endif
KernelState = osKernelReady;
8011dc8: 4b06 ldr r3, [pc, #24] @ (8011de4 <osKernelInitialize+0x48>)
8011dca: 2201 movs r2, #1
8011dcc: 601a str r2, [r3, #0]
stat = osOK;
8011dce: 2300 movs r3, #0
8011dd0: 607b str r3, [r7, #4]
8011dd2: e002 b.n 8011dda <osKernelInitialize+0x3e>
} else {
stat = osError;
8011dd4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8011dd8: 607b str r3, [r7, #4]
}
}
/* Return execution status */
return (stat);
8011dda: 687b ldr r3, [r7, #4]
}
8011ddc: 4618 mov r0, r3
8011dde: 3708 adds r7, #8
8011de0: 46bd mov sp, r7
8011de2: bd80 pop {r7, pc}
8011de4: 200007cc .word 0x200007cc
08011de8 <osKernelStart>:
}
/*
Start the RTOS Kernel scheduler.
*/
osStatus_t osKernelStart (void) {
8011de8: b580 push {r7, lr}
8011dea: b082 sub sp, #8
8011dec: af00 add r7, sp, #0
osStatus_t stat;
BaseType_t state;
if (IRQ_Context() != 0U) {
8011dee: f7ff ffae bl 8011d4e <IRQ_Context>
8011df2: 4603 mov r3, r0
8011df4: 2b00 cmp r3, #0
8011df6: d003 beq.n 8011e00 <osKernelStart+0x18>
stat = osErrorISR;
8011df8: f06f 0305 mvn.w r3, #5
8011dfc: 607b str r3, [r7, #4]
8011dfe: e016 b.n 8011e2e <osKernelStart+0x46>
}
else {
state = xTaskGetSchedulerState();
8011e00: f002 fef4 bl 8014bec <xTaskGetSchedulerState>
8011e04: 6038 str r0, [r7, #0]
/* Start scheduler if initialized and not started before */
if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelReady)) {
8011e06: 683b ldr r3, [r7, #0]
8011e08: 2b01 cmp r3, #1
8011e0a: d10d bne.n 8011e28 <osKernelStart+0x40>
8011e0c: 4b0a ldr r3, [pc, #40] @ (8011e38 <osKernelStart+0x50>)
8011e0e: 681b ldr r3, [r3, #0]
8011e10: 2b01 cmp r3, #1
8011e12: d109 bne.n 8011e28 <osKernelStart+0x40>
/* Ensure SVC priority is at the reset value */
SVC_Setup();
8011e14: f7ff ff92 bl 8011d3c <SVC_Setup>
/* Change state to ensure correct API flow */
KernelState = osKernelRunning;
8011e18: 4b07 ldr r3, [pc, #28] @ (8011e38 <osKernelStart+0x50>)
8011e1a: 2202 movs r2, #2
8011e1c: 601a str r2, [r3, #0]
/* Start the kernel scheduler */
vTaskStartScheduler();
8011e1e: f002 f92b bl 8014078 <vTaskStartScheduler>
stat = osOK;
8011e22: 2300 movs r3, #0
8011e24: 607b str r3, [r7, #4]
8011e26: e002 b.n 8011e2e <osKernelStart+0x46>
} else {
stat = osError;
8011e28: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8011e2c: 607b str r3, [r7, #4]
}
}
/* Return execution status */
return (stat);
8011e2e: 687b ldr r3, [r7, #4]
}
8011e30: 4618 mov r0, r3
8011e32: 3708 adds r7, #8
8011e34: 46bd mov sp, r7
8011e36: bd80 pop {r7, pc}
8011e38: 200007cc .word 0x200007cc
08011e3c <osThreadNew>:
Limitations:
- The memory for control block and stack must be provided in the osThreadAttr_t
structure in order to allocate object statically.
- Attribute osThreadJoinable is not supported, NULL is returned if used.
*/
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
8011e3c: b580 push {r7, lr}
8011e3e: b08e sub sp, #56 @ 0x38
8011e40: af04 add r7, sp, #16
8011e42: 60f8 str r0, [r7, #12]
8011e44: 60b9 str r1, [r7, #8]
8011e46: 607a str r2, [r7, #4]
uint32_t stack;
TaskHandle_t hTask;
UBaseType_t prio;
int32_t mem;
hTask = NULL;
8011e48: 2300 movs r3, #0
8011e4a: 617b str r3, [r7, #20]
if ((IRQ_Context() == 0U) && (func != NULL)) {
8011e4c: f7ff ff7f bl 8011d4e <IRQ_Context>
8011e50: 4603 mov r3, r0
8011e52: 2b00 cmp r3, #0
8011e54: d17f bne.n 8011f56 <osThreadNew+0x11a>
8011e56: 68fb ldr r3, [r7, #12]
8011e58: 2b00 cmp r3, #0
8011e5a: d07c beq.n 8011f56 <osThreadNew+0x11a>
stack = configMINIMAL_STACK_SIZE;
8011e5c: f44f 7300 mov.w r3, #512 @ 0x200
8011e60: 623b str r3, [r7, #32]
prio = (UBaseType_t)osPriorityNormal;
8011e62: 2318 movs r3, #24
8011e64: 61fb str r3, [r7, #28]
name = NULL;
8011e66: 2300 movs r3, #0
8011e68: 627b str r3, [r7, #36] @ 0x24
mem = -1;
8011e6a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8011e6e: 61bb str r3, [r7, #24]
if (attr != NULL) {
8011e70: 687b ldr r3, [r7, #4]
8011e72: 2b00 cmp r3, #0
8011e74: d045 beq.n 8011f02 <osThreadNew+0xc6>
if (attr->name != NULL) {
8011e76: 687b ldr r3, [r7, #4]
8011e78: 681b ldr r3, [r3, #0]
8011e7a: 2b00 cmp r3, #0
8011e7c: d002 beq.n 8011e84 <osThreadNew+0x48>
name = attr->name;
8011e7e: 687b ldr r3, [r7, #4]
8011e80: 681b ldr r3, [r3, #0]
8011e82: 627b str r3, [r7, #36] @ 0x24
}
if (attr->priority != osPriorityNone) {
8011e84: 687b ldr r3, [r7, #4]
8011e86: 699b ldr r3, [r3, #24]
8011e88: 2b00 cmp r3, #0
8011e8a: d002 beq.n 8011e92 <osThreadNew+0x56>
prio = (UBaseType_t)attr->priority;
8011e8c: 687b ldr r3, [r7, #4]
8011e8e: 699b ldr r3, [r3, #24]
8011e90: 61fb str r3, [r7, #28]
}
if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
8011e92: 69fb ldr r3, [r7, #28]
8011e94: 2b00 cmp r3, #0
8011e96: d008 beq.n 8011eaa <osThreadNew+0x6e>
8011e98: 69fb ldr r3, [r7, #28]
8011e9a: 2b38 cmp r3, #56 @ 0x38
8011e9c: d805 bhi.n 8011eaa <osThreadNew+0x6e>
8011e9e: 687b ldr r3, [r7, #4]
8011ea0: 685b ldr r3, [r3, #4]
8011ea2: f003 0301 and.w r3, r3, #1
8011ea6: 2b00 cmp r3, #0
8011ea8: d001 beq.n 8011eae <osThreadNew+0x72>
/* Invalid priority or unsupported osThreadJoinable attribute used */
return (NULL);
8011eaa: 2300 movs r3, #0
8011eac: e054 b.n 8011f58 <osThreadNew+0x11c>
}
if (attr->stack_size > 0U) {
8011eae: 687b ldr r3, [r7, #4]
8011eb0: 695b ldr r3, [r3, #20]
8011eb2: 2b00 cmp r3, #0
8011eb4: d003 beq.n 8011ebe <osThreadNew+0x82>
/* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */
/* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
stack = attr->stack_size / sizeof(StackType_t);
8011eb6: 687b ldr r3, [r7, #4]
8011eb8: 695b ldr r3, [r3, #20]
8011eba: 089b lsrs r3, r3, #2
8011ebc: 623b str r3, [r7, #32]
}
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
8011ebe: 687b ldr r3, [r7, #4]
8011ec0: 689b ldr r3, [r3, #8]
8011ec2: 2b00 cmp r3, #0
8011ec4: d00e beq.n 8011ee4 <osThreadNew+0xa8>
8011ec6: 687b ldr r3, [r7, #4]
8011ec8: 68db ldr r3, [r3, #12]
8011eca: 2b5b cmp r3, #91 @ 0x5b
8011ecc: d90a bls.n 8011ee4 <osThreadNew+0xa8>
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
8011ece: 687b ldr r3, [r7, #4]
8011ed0: 691b ldr r3, [r3, #16]
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
8011ed2: 2b00 cmp r3, #0
8011ed4: d006 beq.n 8011ee4 <osThreadNew+0xa8>
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
8011ed6: 687b ldr r3, [r7, #4]
8011ed8: 695b ldr r3, [r3, #20]
8011eda: 2b00 cmp r3, #0
8011edc: d002 beq.n 8011ee4 <osThreadNew+0xa8>
/* The memory for control block and stack is provided, use static object */
mem = 1;
8011ede: 2301 movs r3, #1
8011ee0: 61bb str r3, [r7, #24]
8011ee2: e010 b.n 8011f06 <osThreadNew+0xca>
}
else {
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
8011ee4: 687b ldr r3, [r7, #4]
8011ee6: 689b ldr r3, [r3, #8]
8011ee8: 2b00 cmp r3, #0
8011eea: d10c bne.n 8011f06 <osThreadNew+0xca>
8011eec: 687b ldr r3, [r7, #4]
8011eee: 68db ldr r3, [r3, #12]
8011ef0: 2b00 cmp r3, #0
8011ef2: d108 bne.n 8011f06 <osThreadNew+0xca>
8011ef4: 687b ldr r3, [r7, #4]
8011ef6: 691b ldr r3, [r3, #16]
8011ef8: 2b00 cmp r3, #0
8011efa: d104 bne.n 8011f06 <osThreadNew+0xca>
/* Control block and stack memory will be allocated from the dynamic pool */
mem = 0;
8011efc: 2300 movs r3, #0
8011efe: 61bb str r3, [r7, #24]
8011f00: e001 b.n 8011f06 <osThreadNew+0xca>
}
}
}
else {
mem = 0;
8011f02: 2300 movs r3, #0
8011f04: 61bb str r3, [r7, #24]
}
if (mem == 1) {
8011f06: 69bb ldr r3, [r7, #24]
8011f08: 2b01 cmp r3, #1
8011f0a: d110 bne.n 8011f2e <osThreadNew+0xf2>
#if (configSUPPORT_STATIC_ALLOCATION == 1)
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
8011f0c: 687b ldr r3, [r7, #4]
8011f0e: 691b ldr r3, [r3, #16]
(StaticTask_t *)attr->cb_mem);
8011f10: 687a ldr r2, [r7, #4]
8011f12: 6892 ldr r2, [r2, #8]
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
8011f14: 9202 str r2, [sp, #8]
8011f16: 9301 str r3, [sp, #4]
8011f18: 69fb ldr r3, [r7, #28]
8011f1a: 9300 str r3, [sp, #0]
8011f1c: 68bb ldr r3, [r7, #8]
8011f1e: 6a3a ldr r2, [r7, #32]
8011f20: 6a79 ldr r1, [r7, #36] @ 0x24
8011f22: 68f8 ldr r0, [r7, #12]
8011f24: f001 fe9a bl 8013c5c <xTaskCreateStatic>
8011f28: 4603 mov r3, r0
8011f2a: 617b str r3, [r7, #20]
8011f2c: e013 b.n 8011f56 <osThreadNew+0x11a>
#endif
}
else {
if (mem == 0) {
8011f2e: 69bb ldr r3, [r7, #24]
8011f30: 2b00 cmp r3, #0
8011f32: d110 bne.n 8011f56 <osThreadNew+0x11a>
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
if (xTaskCreate ((TaskFunction_t)func, name, (configSTACK_DEPTH_TYPE)stack, argument, prio, &hTask) != pdPASS) {
8011f34: 6a3b ldr r3, [r7, #32]
8011f36: b29a uxth r2, r3
8011f38: f107 0314 add.w r3, r7, #20
8011f3c: 9301 str r3, [sp, #4]
8011f3e: 69fb ldr r3, [r7, #28]
8011f40: 9300 str r3, [sp, #0]
8011f42: 68bb ldr r3, [r7, #8]
8011f44: 6a79 ldr r1, [r7, #36] @ 0x24
8011f46: 68f8 ldr r0, [r7, #12]
8011f48: f001 feed bl 8013d26 <xTaskCreate>
8011f4c: 4603 mov r3, r0
8011f4e: 2b01 cmp r3, #1
8011f50: d001 beq.n 8011f56 <osThreadNew+0x11a>
hTask = NULL;
8011f52: 2300 movs r3, #0
8011f54: 617b str r3, [r7, #20]
}
}
}
/* Return thread ID */
return ((osThreadId_t)hTask);
8011f56: 697b ldr r3, [r7, #20]
}
8011f58: 4618 mov r0, r3
8011f5a: 3728 adds r7, #40 @ 0x28
8011f5c: 46bd mov sp, r7
8011f5e: bd80 pop {r7, pc}
08011f60 <osThreadGetId>:
}
/*
Return the thread ID of the current running thread.
*/
osThreadId_t osThreadGetId (void) {
8011f60: b580 push {r7, lr}
8011f62: b082 sub sp, #8
8011f64: af00 add r7, sp, #0
osThreadId_t id;
id = (osThreadId_t)xTaskGetCurrentTaskHandle();
8011f66: f002 fe31 bl 8014bcc <xTaskGetCurrentTaskHandle>
8011f6a: 6078 str r0, [r7, #4]
/* Return thread ID */
return (id);
8011f6c: 687b ldr r3, [r7, #4]
}
8011f6e: 4618 mov r0, r3
8011f70: 3708 adds r7, #8
8011f72: 46bd mov sp, r7
8011f74: bd80 pop {r7, pc}
...
08011f78 <osThreadFlagsSet>:
#if (configUSE_OS2_THREAD_FLAGS == 1)
/*
Set the specified Thread Flags of a thread.
*/
uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
8011f78: b580 push {r7, lr}
8011f7a: b088 sub sp, #32
8011f7c: af02 add r7, sp, #8
8011f7e: 6078 str r0, [r7, #4]
8011f80: 6039 str r1, [r7, #0]
TaskHandle_t hTask = (TaskHandle_t)thread_id;
8011f82: 687b ldr r3, [r7, #4]
8011f84: 617b str r3, [r7, #20]
uint32_t rflags;
BaseType_t yield;
if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) {
8011f86: 697b ldr r3, [r7, #20]
8011f88: 2b00 cmp r3, #0
8011f8a: d002 beq.n 8011f92 <osThreadFlagsSet+0x1a>
8011f8c: 683b ldr r3, [r7, #0]
8011f8e: 2b00 cmp r3, #0
8011f90: da03 bge.n 8011f9a <osThreadFlagsSet+0x22>
rflags = (uint32_t)osErrorParameter;
8011f92: f06f 0303 mvn.w r3, #3
8011f96: 613b str r3, [r7, #16]
8011f98: e03c b.n 8012014 <osThreadFlagsSet+0x9c>
}
else {
rflags = (uint32_t)osError;
8011f9a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8011f9e: 613b str r3, [r7, #16]
if (IRQ_Context() != 0U) {
8011fa0: f7ff fed5 bl 8011d4e <IRQ_Context>
8011fa4: 4603 mov r3, r0
8011fa6: 2b00 cmp r3, #0
8011fa8: d023 beq.n 8011ff2 <osThreadFlagsSet+0x7a>
yield = pdFALSE;
8011faa: 2300 movs r3, #0
8011fac: 60fb str r3, [r7, #12]
(void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield);
8011fae: f107 030c add.w r3, r7, #12
8011fb2: 9301 str r3, [sp, #4]
8011fb4: 2300 movs r3, #0
8011fb6: 9300 str r3, [sp, #0]
8011fb8: 2301 movs r3, #1
8011fba: 683a ldr r2, [r7, #0]
8011fbc: 2100 movs r1, #0
8011fbe: 6978 ldr r0, [r7, #20]
8011fc0: f003 fa3a bl 8015438 <xTaskGenericNotifyFromISR>
(void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL);
8011fc4: 2300 movs r3, #0
8011fc6: 9301 str r3, [sp, #4]
8011fc8: f107 0310 add.w r3, r7, #16
8011fcc: 9300 str r3, [sp, #0]
8011fce: 2300 movs r3, #0
8011fd0: 2200 movs r2, #0
8011fd2: 2100 movs r1, #0
8011fd4: 6978 ldr r0, [r7, #20]
8011fd6: f003 fa2f bl 8015438 <xTaskGenericNotifyFromISR>
portYIELD_FROM_ISR (yield);
8011fda: 68fb ldr r3, [r7, #12]
8011fdc: 2b00 cmp r3, #0
8011fde: d019 beq.n 8012014 <osThreadFlagsSet+0x9c>
8011fe0: 4b0f ldr r3, [pc, #60] @ (8012020 <osThreadFlagsSet+0xa8>)
8011fe2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8011fe6: 601a str r2, [r3, #0]
8011fe8: f3bf 8f4f dsb sy
8011fec: f3bf 8f6f isb sy
8011ff0: e010 b.n 8012014 <osThreadFlagsSet+0x9c>
}
else {
(void)xTaskNotify (hTask, flags, eSetBits);
8011ff2: 2300 movs r3, #0
8011ff4: 9300 str r3, [sp, #0]
8011ff6: 2301 movs r3, #1
8011ff8: 683a ldr r2, [r7, #0]
8011ffa: 2100 movs r1, #0
8011ffc: 6978 ldr r0, [r7, #20]
8011ffe: f003 f8ed bl 80151dc <xTaskGenericNotify>
(void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags);
8012002: f107 0310 add.w r3, r7, #16
8012006: 9300 str r3, [sp, #0]
8012008: 2300 movs r3, #0
801200a: 2200 movs r2, #0
801200c: 2100 movs r1, #0
801200e: 6978 ldr r0, [r7, #20]
8012010: f003 f8e4 bl 80151dc <xTaskGenericNotify>
}
}
/* Return flags after setting */
return (rflags);
8012014: 693b ldr r3, [r7, #16]
}
8012016: 4618 mov r0, r3
8012018: 3718 adds r7, #24
801201a: 46bd mov sp, r7
801201c: bd80 pop {r7, pc}
801201e: bf00 nop
8012020: e000ed04 .word 0xe000ed04
08012024 <osThreadFlagsWait>:
}
/*
Wait for one or more Thread Flags of the current running thread to become signaled.
*/
uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
8012024: b580 push {r7, lr}
8012026: b08e sub sp, #56 @ 0x38
8012028: af02 add r7, sp, #8
801202a: 60f8 str r0, [r7, #12]
801202c: 60b9 str r1, [r7, #8]
801202e: 607a str r2, [r7, #4]
uint32_t rflags, nval;
uint32_t clear;
TickType_t t0, td, tout;
BaseType_t rval;
if (IRQ_Context() != 0U) {
8012030: f7ff fe8d bl 8011d4e <IRQ_Context>
8012034: 4603 mov r3, r0
8012036: 2b00 cmp r3, #0
8012038: d003 beq.n 8012042 <osThreadFlagsWait+0x1e>
rflags = (uint32_t)osErrorISR;
801203a: f06f 0305 mvn.w r3, #5
801203e: 62fb str r3, [r7, #44] @ 0x2c
8012040: e06e b.n 8012120 <osThreadFlagsWait+0xfc>
}
else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {
8012042: 68fb ldr r3, [r7, #12]
8012044: 2b00 cmp r3, #0
8012046: da03 bge.n 8012050 <osThreadFlagsWait+0x2c>
rflags = (uint32_t)osErrorParameter;
8012048: f06f 0303 mvn.w r3, #3
801204c: 62fb str r3, [r7, #44] @ 0x2c
801204e: e067 b.n 8012120 <osThreadFlagsWait+0xfc>
}
else {
if ((options & osFlagsNoClear) == osFlagsNoClear) {
8012050: 68bb ldr r3, [r7, #8]
8012052: f003 0302 and.w r3, r3, #2
8012056: 2b00 cmp r3, #0
8012058: d002 beq.n 8012060 <osThreadFlagsWait+0x3c>
clear = 0U;
801205a: 2300 movs r3, #0
801205c: 62bb str r3, [r7, #40] @ 0x28
801205e: e001 b.n 8012064 <osThreadFlagsWait+0x40>
} else {
clear = flags;
8012060: 68fb ldr r3, [r7, #12]
8012062: 62bb str r3, [r7, #40] @ 0x28
}
rflags = 0U;
8012064: 2300 movs r3, #0
8012066: 62fb str r3, [r7, #44] @ 0x2c
tout = timeout;
8012068: 687b ldr r3, [r7, #4]
801206a: 627b str r3, [r7, #36] @ 0x24
t0 = xTaskGetTickCount();
801206c: f002 f97c bl 8014368 <xTaskGetTickCount>
8012070: 6238 str r0, [r7, #32]
do {
rval = xTaskNotifyWait (0, clear, &nval, tout);
8012072: f107 0214 add.w r2, r7, #20
8012076: 6a7b ldr r3, [r7, #36] @ 0x24
8012078: 9300 str r3, [sp, #0]
801207a: 4613 mov r3, r2
801207c: 6aba ldr r2, [r7, #40] @ 0x28
801207e: 2100 movs r1, #0
8012080: 2000 movs r0, #0
8012082: f003 f825 bl 80150d0 <xTaskGenericNotifyWait>
8012086: 61f8 str r0, [r7, #28]
if (rval == pdPASS) {
8012088: 69fb ldr r3, [r7, #28]
801208a: 2b01 cmp r3, #1
801208c: d137 bne.n 80120fe <osThreadFlagsWait+0xda>
rflags &= flags;
801208e: 6afa ldr r2, [r7, #44] @ 0x2c
8012090: 68fb ldr r3, [r7, #12]
8012092: 4013 ands r3, r2
8012094: 62fb str r3, [r7, #44] @ 0x2c
rflags |= nval;
8012096: 697b ldr r3, [r7, #20]
8012098: 6afa ldr r2, [r7, #44] @ 0x2c
801209a: 4313 orrs r3, r2
801209c: 62fb str r3, [r7, #44] @ 0x2c
if ((options & osFlagsWaitAll) == osFlagsWaitAll) {
801209e: 68bb ldr r3, [r7, #8]
80120a0: f003 0301 and.w r3, r3, #1
80120a4: 2b00 cmp r3, #0
80120a6: d00c beq.n 80120c2 <osThreadFlagsWait+0x9e>
if ((flags & rflags) == flags) {
80120a8: 68fa ldr r2, [r7, #12]
80120aa: 6afb ldr r3, [r7, #44] @ 0x2c
80120ac: 4013 ands r3, r2
80120ae: 68fa ldr r2, [r7, #12]
80120b0: 429a cmp r2, r3
80120b2: d032 beq.n 801211a <osThreadFlagsWait+0xf6>
break;
} else {
if (timeout == 0U) {
80120b4: 687b ldr r3, [r7, #4]
80120b6: 2b00 cmp r3, #0
80120b8: d10f bne.n 80120da <osThreadFlagsWait+0xb6>
rflags = (uint32_t)osErrorResource;
80120ba: f06f 0302 mvn.w r3, #2
80120be: 62fb str r3, [r7, #44] @ 0x2c
break;
80120c0: e02e b.n 8012120 <osThreadFlagsWait+0xfc>
}
}
}
else {
if ((flags & rflags) != 0) {
80120c2: 68fa ldr r2, [r7, #12]
80120c4: 6afb ldr r3, [r7, #44] @ 0x2c
80120c6: 4013 ands r3, r2
80120c8: 2b00 cmp r3, #0
80120ca: d128 bne.n 801211e <osThreadFlagsWait+0xfa>
break;
} else {
if (timeout == 0U) {
80120cc: 687b ldr r3, [r7, #4]
80120ce: 2b00 cmp r3, #0
80120d0: d103 bne.n 80120da <osThreadFlagsWait+0xb6>
rflags = (uint32_t)osErrorResource;
80120d2: f06f 0302 mvn.w r3, #2
80120d6: 62fb str r3, [r7, #44] @ 0x2c
break;
80120d8: e022 b.n 8012120 <osThreadFlagsWait+0xfc>
}
}
}
/* Update timeout */
td = xTaskGetTickCount() - t0;
80120da: f002 f945 bl 8014368 <xTaskGetTickCount>
80120de: 4602 mov r2, r0
80120e0: 6a3b ldr r3, [r7, #32]
80120e2: 1ad3 subs r3, r2, r3
80120e4: 61bb str r3, [r7, #24]
if (td > timeout) {
80120e6: 69ba ldr r2, [r7, #24]
80120e8: 687b ldr r3, [r7, #4]
80120ea: 429a cmp r2, r3
80120ec: d902 bls.n 80120f4 <osThreadFlagsWait+0xd0>
tout = 0;
80120ee: 2300 movs r3, #0
80120f0: 627b str r3, [r7, #36] @ 0x24
80120f2: e00e b.n 8012112 <osThreadFlagsWait+0xee>
} else {
tout = timeout - td;
80120f4: 687a ldr r2, [r7, #4]
80120f6: 69bb ldr r3, [r7, #24]
80120f8: 1ad3 subs r3, r2, r3
80120fa: 627b str r3, [r7, #36] @ 0x24
80120fc: e009 b.n 8012112 <osThreadFlagsWait+0xee>
}
}
else {
if (timeout == 0) {
80120fe: 687b ldr r3, [r7, #4]
8012100: 2b00 cmp r3, #0
8012102: d103 bne.n 801210c <osThreadFlagsWait+0xe8>
rflags = (uint32_t)osErrorResource;
8012104: f06f 0302 mvn.w r3, #2
8012108: 62fb str r3, [r7, #44] @ 0x2c
801210a: e002 b.n 8012112 <osThreadFlagsWait+0xee>
} else {
rflags = (uint32_t)osErrorTimeout;
801210c: f06f 0301 mvn.w r3, #1
8012110: 62fb str r3, [r7, #44] @ 0x2c
}
}
}
while (rval != pdFAIL);
8012112: 69fb ldr r3, [r7, #28]
8012114: 2b00 cmp r3, #0
8012116: d1ac bne.n 8012072 <osThreadFlagsWait+0x4e>
8012118: e002 b.n 8012120 <osThreadFlagsWait+0xfc>
break;
801211a: bf00 nop
801211c: e000 b.n 8012120 <osThreadFlagsWait+0xfc>
break;
801211e: bf00 nop
}
/* Return flags before clearing */
return (rflags);
8012120: 6afb ldr r3, [r7, #44] @ 0x2c
}
8012122: 4618 mov r0, r3
8012124: 3730 adds r7, #48 @ 0x30
8012126: 46bd mov sp, r7
8012128: bd80 pop {r7, pc}
0801212a <osDelay>:
/* ==== Generic Wait Functions ==== */
/*
Wait for Timeout (Time Delay).
*/
osStatus_t osDelay (uint32_t ticks) {
801212a: b580 push {r7, lr}
801212c: b084 sub sp, #16
801212e: af00 add r7, sp, #0
8012130: 6078 str r0, [r7, #4]
osStatus_t stat;
if (IRQ_Context() != 0U) {
8012132: f7ff fe0c bl 8011d4e <IRQ_Context>
8012136: 4603 mov r3, r0
8012138: 2b00 cmp r3, #0
801213a: d003 beq.n 8012144 <osDelay+0x1a>
stat = osErrorISR;
801213c: f06f 0305 mvn.w r3, #5
8012140: 60fb str r3, [r7, #12]
8012142: e007 b.n 8012154 <osDelay+0x2a>
}
else {
stat = osOK;
8012144: 2300 movs r3, #0
8012146: 60fb str r3, [r7, #12]
if (ticks != 0U) {
8012148: 687b ldr r3, [r7, #4]
801214a: 2b00 cmp r3, #0
801214c: d002 beq.n 8012154 <osDelay+0x2a>
vTaskDelay(ticks);
801214e: 6878 ldr r0, [r7, #4]
8012150: f001 ff5c bl 801400c <vTaskDelay>
}
}
/* Return execution status */
return (stat);
8012154: 68fb ldr r3, [r7, #12]
}
8012156: 4618 mov r0, r3
8012158: 3710 adds r7, #16
801215a: 46bd mov sp, r7
801215c: bd80 pop {r7, pc}
0801215e <osMutexNew>:
Limitations:
- Priority inherit protocol is used by default, osMutexPrioInherit attribute is ignored.
- Robust mutex is not supported, NULL is returned if used.
*/
osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
801215e: b580 push {r7, lr}
8012160: b086 sub sp, #24
8012162: af00 add r7, sp, #0
8012164: 6078 str r0, [r7, #4]
SemaphoreHandle_t hMutex;
uint32_t type;
uint32_t rmtx;
int32_t mem;
hMutex = NULL;
8012166: 2300 movs r3, #0
8012168: 617b str r3, [r7, #20]
if (IRQ_Context() == 0U) {
801216a: f7ff fdf0 bl 8011d4e <IRQ_Context>
801216e: 4603 mov r3, r0
8012170: 2b00 cmp r3, #0
8012172: d174 bne.n 801225e <osMutexNew+0x100>
if (attr != NULL) {
8012174: 687b ldr r3, [r7, #4]
8012176: 2b00 cmp r3, #0
8012178: d003 beq.n 8012182 <osMutexNew+0x24>
type = attr->attr_bits;
801217a: 687b ldr r3, [r7, #4]
801217c: 685b ldr r3, [r3, #4]
801217e: 613b str r3, [r7, #16]
8012180: e001 b.n 8012186 <osMutexNew+0x28>
} else {
type = 0U;
8012182: 2300 movs r3, #0
8012184: 613b str r3, [r7, #16]
}
if ((type & osMutexRecursive) == osMutexRecursive) {
8012186: 693b ldr r3, [r7, #16]
8012188: f003 0301 and.w r3, r3, #1
801218c: 2b00 cmp r3, #0
801218e: d002 beq.n 8012196 <osMutexNew+0x38>
rmtx = 1U;
8012190: 2301 movs r3, #1
8012192: 60fb str r3, [r7, #12]
8012194: e001 b.n 801219a <osMutexNew+0x3c>
} else {
rmtx = 0U;
8012196: 2300 movs r3, #0
8012198: 60fb str r3, [r7, #12]
}
if ((type & osMutexRobust) != osMutexRobust) {
801219a: 693b ldr r3, [r7, #16]
801219c: f003 0308 and.w r3, r3, #8
80121a0: 2b00 cmp r3, #0
80121a2: d15c bne.n 801225e <osMutexNew+0x100>
mem = -1;
80121a4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
80121a8: 60bb str r3, [r7, #8]
if (attr != NULL) {
80121aa: 687b ldr r3, [r7, #4]
80121ac: 2b00 cmp r3, #0
80121ae: d015 beq.n 80121dc <osMutexNew+0x7e>
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
80121b0: 687b ldr r3, [r7, #4]
80121b2: 689b ldr r3, [r3, #8]
80121b4: 2b00 cmp r3, #0
80121b6: d006 beq.n 80121c6 <osMutexNew+0x68>
80121b8: 687b ldr r3, [r7, #4]
80121ba: 68db ldr r3, [r3, #12]
80121bc: 2b4f cmp r3, #79 @ 0x4f
80121be: d902 bls.n 80121c6 <osMutexNew+0x68>
/* The memory for control block is provided, use static object */
mem = 1;
80121c0: 2301 movs r3, #1
80121c2: 60bb str r3, [r7, #8]
80121c4: e00c b.n 80121e0 <osMutexNew+0x82>
}
else {
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
80121c6: 687b ldr r3, [r7, #4]
80121c8: 689b ldr r3, [r3, #8]
80121ca: 2b00 cmp r3, #0
80121cc: d108 bne.n 80121e0 <osMutexNew+0x82>
80121ce: 687b ldr r3, [r7, #4]
80121d0: 68db ldr r3, [r3, #12]
80121d2: 2b00 cmp r3, #0
80121d4: d104 bne.n 80121e0 <osMutexNew+0x82>
/* Control block will be allocated from the dynamic pool */
mem = 0;
80121d6: 2300 movs r3, #0
80121d8: 60bb str r3, [r7, #8]
80121da: e001 b.n 80121e0 <osMutexNew+0x82>
}
}
}
else {
mem = 0;
80121dc: 2300 movs r3, #0
80121de: 60bb str r3, [r7, #8]
}
if (mem == 1) {
80121e0: 68bb ldr r3, [r7, #8]
80121e2: 2b01 cmp r3, #1
80121e4: d112 bne.n 801220c <osMutexNew+0xae>
#if (configSUPPORT_STATIC_ALLOCATION == 1)
if (rmtx != 0U) {
80121e6: 68fb ldr r3, [r7, #12]
80121e8: 2b00 cmp r3, #0
80121ea: d007 beq.n 80121fc <osMutexNew+0x9e>
#if (configUSE_RECURSIVE_MUTEXES == 1)
hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);
80121ec: 687b ldr r3, [r7, #4]
80121ee: 689b ldr r3, [r3, #8]
80121f0: 4619 mov r1, r3
80121f2: 2004 movs r0, #4
80121f4: f000 fd63 bl 8012cbe <xQueueCreateMutexStatic>
80121f8: 6178 str r0, [r7, #20]
80121fa: e016 b.n 801222a <osMutexNew+0xcc>
#endif
}
else {
hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);
80121fc: 687b ldr r3, [r7, #4]
80121fe: 689b ldr r3, [r3, #8]
8012200: 4619 mov r1, r3
8012202: 2001 movs r0, #1
8012204: f000 fd5b bl 8012cbe <xQueueCreateMutexStatic>
8012208: 6178 str r0, [r7, #20]
801220a: e00e b.n 801222a <osMutexNew+0xcc>
}
#endif
}
else {
if (mem == 0) {
801220c: 68bb ldr r3, [r7, #8]
801220e: 2b00 cmp r3, #0
8012210: d10b bne.n 801222a <osMutexNew+0xcc>
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
if (rmtx != 0U) {
8012212: 68fb ldr r3, [r7, #12]
8012214: 2b00 cmp r3, #0
8012216: d004 beq.n 8012222 <osMutexNew+0xc4>
#if (configUSE_RECURSIVE_MUTEXES == 1)
hMutex = xSemaphoreCreateRecursiveMutex ();
8012218: 2004 movs r0, #4
801221a: f000 fd38 bl 8012c8e <xQueueCreateMutex>
801221e: 6178 str r0, [r7, #20]
8012220: e003 b.n 801222a <osMutexNew+0xcc>
#endif
} else {
hMutex = xSemaphoreCreateMutex ();
8012222: 2001 movs r0, #1
8012224: f000 fd33 bl 8012c8e <xQueueCreateMutex>
8012228: 6178 str r0, [r7, #20]
#endif
}
}
#if (configQUEUE_REGISTRY_SIZE > 0)
if (hMutex != NULL) {
801222a: 697b ldr r3, [r7, #20]
801222c: 2b00 cmp r3, #0
801222e: d00c beq.n 801224a <osMutexNew+0xec>
if ((attr != NULL) && (attr->name != NULL)) {
8012230: 687b ldr r3, [r7, #4]
8012232: 2b00 cmp r3, #0
8012234: d009 beq.n 801224a <osMutexNew+0xec>
8012236: 687b ldr r3, [r7, #4]
8012238: 681b ldr r3, [r3, #0]
801223a: 2b00 cmp r3, #0
801223c: d005 beq.n 801224a <osMutexNew+0xec>
/* Only non-NULL name objects are added to the Queue Registry */
vQueueAddToRegistry (hMutex, attr->name);
801223e: 687b ldr r3, [r7, #4]
8012240: 681b ldr r3, [r3, #0]
8012242: 4619 mov r1, r3
8012244: 6978 ldr r0, [r7, #20]
8012246: f001 fc4b bl 8013ae0 <vQueueAddToRegistry>
}
}
#endif
if ((hMutex != NULL) && (rmtx != 0U)) {
801224a: 697b ldr r3, [r7, #20]
801224c: 2b00 cmp r3, #0
801224e: d006 beq.n 801225e <osMutexNew+0x100>
8012250: 68fb ldr r3, [r7, #12]
8012252: 2b00 cmp r3, #0
8012254: d003 beq.n 801225e <osMutexNew+0x100>
/* Set LSB as 'recursive mutex flag' */
hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);
8012256: 697b ldr r3, [r7, #20]
8012258: f043 0301 orr.w r3, r3, #1
801225c: 617b str r3, [r7, #20]
}
}
}
/* Return mutex ID */
return ((osMutexId_t)hMutex);
801225e: 697b ldr r3, [r7, #20]
}
8012260: 4618 mov r0, r3
8012262: 3718 adds r7, #24
8012264: 46bd mov sp, r7
8012266: bd80 pop {r7, pc}
08012268 <osMutexAcquire>:
/*
Acquire a Mutex or timeout if it is locked.
*/
osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
8012268: b580 push {r7, lr}
801226a: b086 sub sp, #24
801226c: af00 add r7, sp, #0
801226e: 6078 str r0, [r7, #4]
8012270: 6039 str r1, [r7, #0]
SemaphoreHandle_t hMutex;
osStatus_t stat;
uint32_t rmtx;
hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
8012272: 687b ldr r3, [r7, #4]
8012274: f023 0301 bic.w r3, r3, #1
8012278: 613b str r3, [r7, #16]
/* Extract recursive mutex flag */
rmtx = (uint32_t)mutex_id & 1U;
801227a: 687b ldr r3, [r7, #4]
801227c: f003 0301 and.w r3, r3, #1
8012280: 60fb str r3, [r7, #12]
stat = osOK;
8012282: 2300 movs r3, #0
8012284: 617b str r3, [r7, #20]
if (IRQ_Context() != 0U) {
8012286: f7ff fd62 bl 8011d4e <IRQ_Context>
801228a: 4603 mov r3, r0
801228c: 2b00 cmp r3, #0
801228e: d003 beq.n 8012298 <osMutexAcquire+0x30>
stat = osErrorISR;
8012290: f06f 0305 mvn.w r3, #5
8012294: 617b str r3, [r7, #20]
8012296: e02c b.n 80122f2 <osMutexAcquire+0x8a>
}
else if (hMutex == NULL) {
8012298: 693b ldr r3, [r7, #16]
801229a: 2b00 cmp r3, #0
801229c: d103 bne.n 80122a6 <osMutexAcquire+0x3e>
stat = osErrorParameter;
801229e: f06f 0303 mvn.w r3, #3
80122a2: 617b str r3, [r7, #20]
80122a4: e025 b.n 80122f2 <osMutexAcquire+0x8a>
}
else {
if (rmtx != 0U) {
80122a6: 68fb ldr r3, [r7, #12]
80122a8: 2b00 cmp r3, #0
80122aa: d011 beq.n 80122d0 <osMutexAcquire+0x68>
#if (configUSE_RECURSIVE_MUTEXES == 1)
if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {
80122ac: 6839 ldr r1, [r7, #0]
80122ae: 6938 ldr r0, [r7, #16]
80122b0: f000 fd55 bl 8012d5e <xQueueTakeMutexRecursive>
80122b4: 4603 mov r3, r0
80122b6: 2b01 cmp r3, #1
80122b8: d01b beq.n 80122f2 <osMutexAcquire+0x8a>
if (timeout != 0U) {
80122ba: 683b ldr r3, [r7, #0]
80122bc: 2b00 cmp r3, #0
80122be: d003 beq.n 80122c8 <osMutexAcquire+0x60>
stat = osErrorTimeout;
80122c0: f06f 0301 mvn.w r3, #1
80122c4: 617b str r3, [r7, #20]
80122c6: e014 b.n 80122f2 <osMutexAcquire+0x8a>
} else {
stat = osErrorResource;
80122c8: f06f 0302 mvn.w r3, #2
80122cc: 617b str r3, [r7, #20]
80122ce: e010 b.n 80122f2 <osMutexAcquire+0x8a>
}
}
#endif
}
else {
if (xSemaphoreTake (hMutex, timeout) != pdPASS) {
80122d0: 6839 ldr r1, [r7, #0]
80122d2: 6938 ldr r0, [r7, #16]
80122d4: f001 f91e bl 8013514 <xQueueSemaphoreTake>
80122d8: 4603 mov r3, r0
80122da: 2b01 cmp r3, #1
80122dc: d009 beq.n 80122f2 <osMutexAcquire+0x8a>
if (timeout != 0U) {
80122de: 683b ldr r3, [r7, #0]
80122e0: 2b00 cmp r3, #0
80122e2: d003 beq.n 80122ec <osMutexAcquire+0x84>
stat = osErrorTimeout;
80122e4: f06f 0301 mvn.w r3, #1
80122e8: 617b str r3, [r7, #20]
80122ea: e002 b.n 80122f2 <osMutexAcquire+0x8a>
} else {
stat = osErrorResource;
80122ec: f06f 0302 mvn.w r3, #2
80122f0: 617b str r3, [r7, #20]
}
}
}
/* Return execution status */
return (stat);
80122f2: 697b ldr r3, [r7, #20]
}
80122f4: 4618 mov r0, r3
80122f6: 3718 adds r7, #24
80122f8: 46bd mov sp, r7
80122fa: bd80 pop {r7, pc}
080122fc <osMutexRelease>:
/*
Release a Mutex that was acquired by osMutexAcquire.
*/
osStatus_t osMutexRelease (osMutexId_t mutex_id) {
80122fc: b580 push {r7, lr}
80122fe: b086 sub sp, #24
8012300: af00 add r7, sp, #0
8012302: 6078 str r0, [r7, #4]
SemaphoreHandle_t hMutex;
osStatus_t stat;
uint32_t rmtx;
hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
8012304: 687b ldr r3, [r7, #4]
8012306: f023 0301 bic.w r3, r3, #1
801230a: 613b str r3, [r7, #16]
/* Extract recursive mutex flag */
rmtx = (uint32_t)mutex_id & 1U;
801230c: 687b ldr r3, [r7, #4]
801230e: f003 0301 and.w r3, r3, #1
8012312: 60fb str r3, [r7, #12]
stat = osOK;
8012314: 2300 movs r3, #0
8012316: 617b str r3, [r7, #20]
if (IRQ_Context() != 0U) {
8012318: f7ff fd19 bl 8011d4e <IRQ_Context>
801231c: 4603 mov r3, r0
801231e: 2b00 cmp r3, #0
8012320: d003 beq.n 801232a <osMutexRelease+0x2e>
stat = osErrorISR;
8012322: f06f 0305 mvn.w r3, #5
8012326: 617b str r3, [r7, #20]
8012328: e01f b.n 801236a <osMutexRelease+0x6e>
}
else if (hMutex == NULL) {
801232a: 693b ldr r3, [r7, #16]
801232c: 2b00 cmp r3, #0
801232e: d103 bne.n 8012338 <osMutexRelease+0x3c>
stat = osErrorParameter;
8012330: f06f 0303 mvn.w r3, #3
8012334: 617b str r3, [r7, #20]
8012336: e018 b.n 801236a <osMutexRelease+0x6e>
}
else {
if (rmtx != 0U) {
8012338: 68fb ldr r3, [r7, #12]
801233a: 2b00 cmp r3, #0
801233c: d009 beq.n 8012352 <osMutexRelease+0x56>
#if (configUSE_RECURSIVE_MUTEXES == 1)
if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {
801233e: 6938 ldr r0, [r7, #16]
8012340: f000 fcd8 bl 8012cf4 <xQueueGiveMutexRecursive>
8012344: 4603 mov r3, r0
8012346: 2b01 cmp r3, #1
8012348: d00f beq.n 801236a <osMutexRelease+0x6e>
stat = osErrorResource;
801234a: f06f 0302 mvn.w r3, #2
801234e: 617b str r3, [r7, #20]
8012350: e00b b.n 801236a <osMutexRelease+0x6e>
}
#endif
}
else {
if (xSemaphoreGive (hMutex) != pdPASS) {
8012352: 2300 movs r3, #0
8012354: 2200 movs r2, #0
8012356: 2100 movs r1, #0
8012358: 6938 ldr r0, [r7, #16]
801235a: f000 fd99 bl 8012e90 <xQueueGenericSend>
801235e: 4603 mov r3, r0
8012360: 2b01 cmp r3, #1
8012362: d002 beq.n 801236a <osMutexRelease+0x6e>
stat = osErrorResource;
8012364: f06f 0302 mvn.w r3, #2
8012368: 617b str r3, [r7, #20]
}
}
}
/* Return execution status */
return (stat);
801236a: 697b ldr r3, [r7, #20]
}
801236c: 4618 mov r0, r3
801236e: 3718 adds r7, #24
8012370: 46bd mov sp, r7
8012372: bd80 pop {r7, pc}
08012374 <osSemaphoreNew>:
/* ==== Semaphore Management Functions ==== */
/*
Create and Initialize a Semaphore object.
*/
osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
8012374: b580 push {r7, lr}
8012376: b088 sub sp, #32
8012378: af02 add r7, sp, #8
801237a: 60f8 str r0, [r7, #12]
801237c: 60b9 str r1, [r7, #8]
801237e: 607a str r2, [r7, #4]
SemaphoreHandle_t hSemaphore;
int32_t mem;
hSemaphore = NULL;
8012380: 2300 movs r3, #0
8012382: 617b str r3, [r7, #20]
if ((IRQ_Context() == 0U) && (max_count > 0U) && (initial_count <= max_count)) {
8012384: f7ff fce3 bl 8011d4e <IRQ_Context>
8012388: 4603 mov r3, r0
801238a: 2b00 cmp r3, #0
801238c: d175 bne.n 801247a <osSemaphoreNew+0x106>
801238e: 68fb ldr r3, [r7, #12]
8012390: 2b00 cmp r3, #0
8012392: d072 beq.n 801247a <osSemaphoreNew+0x106>
8012394: 68ba ldr r2, [r7, #8]
8012396: 68fb ldr r3, [r7, #12]
8012398: 429a cmp r2, r3
801239a: d86e bhi.n 801247a <osSemaphoreNew+0x106>
mem = -1;
801239c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
80123a0: 613b str r3, [r7, #16]
if (attr != NULL) {
80123a2: 687b ldr r3, [r7, #4]
80123a4: 2b00 cmp r3, #0
80123a6: d015 beq.n 80123d4 <osSemaphoreNew+0x60>
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
80123a8: 687b ldr r3, [r7, #4]
80123aa: 689b ldr r3, [r3, #8]
80123ac: 2b00 cmp r3, #0
80123ae: d006 beq.n 80123be <osSemaphoreNew+0x4a>
80123b0: 687b ldr r3, [r7, #4]
80123b2: 68db ldr r3, [r3, #12]
80123b4: 2b4f cmp r3, #79 @ 0x4f
80123b6: d902 bls.n 80123be <osSemaphoreNew+0x4a>
/* The memory for control block is provided, use static object */
mem = 1;
80123b8: 2301 movs r3, #1
80123ba: 613b str r3, [r7, #16]
80123bc: e00c b.n 80123d8 <osSemaphoreNew+0x64>
}
else {
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
80123be: 687b ldr r3, [r7, #4]
80123c0: 689b ldr r3, [r3, #8]
80123c2: 2b00 cmp r3, #0
80123c4: d108 bne.n 80123d8 <osSemaphoreNew+0x64>
80123c6: 687b ldr r3, [r7, #4]
80123c8: 68db ldr r3, [r3, #12]
80123ca: 2b00 cmp r3, #0
80123cc: d104 bne.n 80123d8 <osSemaphoreNew+0x64>
/* Control block will be allocated from the dynamic pool */
mem = 0;
80123ce: 2300 movs r3, #0
80123d0: 613b str r3, [r7, #16]
80123d2: e001 b.n 80123d8 <osSemaphoreNew+0x64>
}
}
}
else {
mem = 0;
80123d4: 2300 movs r3, #0
80123d6: 613b str r3, [r7, #16]
}
if (mem != -1) {
80123d8: 693b ldr r3, [r7, #16]
80123da: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80123de: d04c beq.n 801247a <osSemaphoreNew+0x106>
if (max_count == 1U) {
80123e0: 68fb ldr r3, [r7, #12]
80123e2: 2b01 cmp r3, #1
80123e4: d128 bne.n 8012438 <osSemaphoreNew+0xc4>
if (mem == 1) {
80123e6: 693b ldr r3, [r7, #16]
80123e8: 2b01 cmp r3, #1
80123ea: d10a bne.n 8012402 <osSemaphoreNew+0x8e>
#if (configSUPPORT_STATIC_ALLOCATION == 1)
hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem);
80123ec: 687b ldr r3, [r7, #4]
80123ee: 689b ldr r3, [r3, #8]
80123f0: 2203 movs r2, #3
80123f2: 9200 str r2, [sp, #0]
80123f4: 2200 movs r2, #0
80123f6: 2100 movs r1, #0
80123f8: 2001 movs r0, #1
80123fa: f000 fb57 bl 8012aac <xQueueGenericCreateStatic>
80123fe: 6178 str r0, [r7, #20]
8012400: e005 b.n 801240e <osSemaphoreNew+0x9a>
#endif
}
else {
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
hSemaphore = xSemaphoreCreateBinary();
8012402: 2203 movs r2, #3
8012404: 2100 movs r1, #0
8012406: 2001 movs r0, #1
8012408: f000 fbb1 bl 8012b6e <xQueueGenericCreate>
801240c: 6178 str r0, [r7, #20]
#endif
}
if ((hSemaphore != NULL) && (initial_count != 0U)) {
801240e: 697b ldr r3, [r7, #20]
8012410: 2b00 cmp r3, #0
8012412: d022 beq.n 801245a <osSemaphoreNew+0xe6>
8012414: 68bb ldr r3, [r7, #8]
8012416: 2b00 cmp r3, #0
8012418: d01f beq.n 801245a <osSemaphoreNew+0xe6>
if (xSemaphoreGive (hSemaphore) != pdPASS) {
801241a: 2300 movs r3, #0
801241c: 2200 movs r2, #0
801241e: 2100 movs r1, #0
8012420: 6978 ldr r0, [r7, #20]
8012422: f000 fd35 bl 8012e90 <xQueueGenericSend>
8012426: 4603 mov r3, r0
8012428: 2b01 cmp r3, #1
801242a: d016 beq.n 801245a <osSemaphoreNew+0xe6>
vSemaphoreDelete (hSemaphore);
801242c: 6978 ldr r0, [r7, #20]
801242e: f001 fa0b bl 8013848 <vQueueDelete>
hSemaphore = NULL;
8012432: 2300 movs r3, #0
8012434: 617b str r3, [r7, #20]
8012436: e010 b.n 801245a <osSemaphoreNew+0xe6>
}
}
}
else {
if (mem == 1) {
8012438: 693b ldr r3, [r7, #16]
801243a: 2b01 cmp r3, #1
801243c: d108 bne.n 8012450 <osSemaphoreNew+0xdc>
#if (configSUPPORT_STATIC_ALLOCATION == 1)
hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem);
801243e: 687b ldr r3, [r7, #4]
8012440: 689b ldr r3, [r3, #8]
8012442: 461a mov r2, r3
8012444: 68b9 ldr r1, [r7, #8]
8012446: 68f8 ldr r0, [r7, #12]
8012448: f000 fcc0 bl 8012dcc <xQueueCreateCountingSemaphoreStatic>
801244c: 6178 str r0, [r7, #20]
801244e: e004 b.n 801245a <osSemaphoreNew+0xe6>
#endif
}
else {
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
hSemaphore = xSemaphoreCreateCounting (max_count, initial_count);
8012450: 68b9 ldr r1, [r7, #8]
8012452: 68f8 ldr r0, [r7, #12]
8012454: f000 fced bl 8012e32 <xQueueCreateCountingSemaphore>
8012458: 6178 str r0, [r7, #20]
#endif
}
}
#if (configQUEUE_REGISTRY_SIZE > 0)
if (hSemaphore != NULL) {
801245a: 697b ldr r3, [r7, #20]
801245c: 2b00 cmp r3, #0
801245e: d00c beq.n 801247a <osSemaphoreNew+0x106>
if ((attr != NULL) && (attr->name != NULL)) {
8012460: 687b ldr r3, [r7, #4]
8012462: 2b00 cmp r3, #0
8012464: d009 beq.n 801247a <osSemaphoreNew+0x106>
8012466: 687b ldr r3, [r7, #4]
8012468: 681b ldr r3, [r3, #0]
801246a: 2b00 cmp r3, #0
801246c: d005 beq.n 801247a <osSemaphoreNew+0x106>
/* Only non-NULL name objects are added to the Queue Registry */
vQueueAddToRegistry (hSemaphore, attr->name);
801246e: 687b ldr r3, [r7, #4]
8012470: 681b ldr r3, [r3, #0]
8012472: 4619 mov r1, r3
8012474: 6978 ldr r0, [r7, #20]
8012476: f001 fb33 bl 8013ae0 <vQueueAddToRegistry>
#endif
}
}
/* Return semaphore ID */
return ((osSemaphoreId_t)hSemaphore);
801247a: 697b ldr r3, [r7, #20]
}
801247c: 4618 mov r0, r3
801247e: 3718 adds r7, #24
8012480: 46bd mov sp, r7
8012482: bd80 pop {r7, pc}
08012484 <osSemaphoreAcquire>:
/*
Acquire a Semaphore token or timeout if no tokens are available.
*/
osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
8012484: b580 push {r7, lr}
8012486: b086 sub sp, #24
8012488: af00 add r7, sp, #0
801248a: 6078 str r0, [r7, #4]
801248c: 6039 str r1, [r7, #0]
SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
801248e: 687b ldr r3, [r7, #4]
8012490: 613b str r3, [r7, #16]
osStatus_t stat;
BaseType_t yield;
stat = osOK;
8012492: 2300 movs r3, #0
8012494: 617b str r3, [r7, #20]
if (hSemaphore == NULL) {
8012496: 693b ldr r3, [r7, #16]
8012498: 2b00 cmp r3, #0
801249a: d103 bne.n 80124a4 <osSemaphoreAcquire+0x20>
stat = osErrorParameter;
801249c: f06f 0303 mvn.w r3, #3
80124a0: 617b str r3, [r7, #20]
80124a2: e038 b.n 8012516 <osSemaphoreAcquire+0x92>
}
else if (IRQ_Context() != 0U) {
80124a4: f7ff fc53 bl 8011d4e <IRQ_Context>
80124a8: 4603 mov r3, r0
80124aa: 2b00 cmp r3, #0
80124ac: d022 beq.n 80124f4 <osSemaphoreAcquire+0x70>
if (timeout != 0U) {
80124ae: 683b ldr r3, [r7, #0]
80124b0: 2b00 cmp r3, #0
80124b2: d003 beq.n 80124bc <osSemaphoreAcquire+0x38>
stat = osErrorParameter;
80124b4: f06f 0303 mvn.w r3, #3
80124b8: 617b str r3, [r7, #20]
80124ba: e02c b.n 8012516 <osSemaphoreAcquire+0x92>
}
else {
yield = pdFALSE;
80124bc: 2300 movs r3, #0
80124be: 60fb str r3, [r7, #12]
if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) {
80124c0: f107 030c add.w r3, r7, #12
80124c4: 461a mov r2, r3
80124c6: 2100 movs r1, #0
80124c8: 6938 ldr r0, [r7, #16]
80124ca: f001 f923 bl 8013714 <xQueueReceiveFromISR>
80124ce: 4603 mov r3, r0
80124d0: 2b01 cmp r3, #1
80124d2: d003 beq.n 80124dc <osSemaphoreAcquire+0x58>
stat = osErrorResource;
80124d4: f06f 0302 mvn.w r3, #2
80124d8: 617b str r3, [r7, #20]
80124da: e01c b.n 8012516 <osSemaphoreAcquire+0x92>
} else {
portYIELD_FROM_ISR (yield);
80124dc: 68fb ldr r3, [r7, #12]
80124de: 2b00 cmp r3, #0
80124e0: d019 beq.n 8012516 <osSemaphoreAcquire+0x92>
80124e2: 4b0f ldr r3, [pc, #60] @ (8012520 <osSemaphoreAcquire+0x9c>)
80124e4: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80124e8: 601a str r2, [r3, #0]
80124ea: f3bf 8f4f dsb sy
80124ee: f3bf 8f6f isb sy
80124f2: e010 b.n 8012516 <osSemaphoreAcquire+0x92>
}
}
}
else {
if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) {
80124f4: 6839 ldr r1, [r7, #0]
80124f6: 6938 ldr r0, [r7, #16]
80124f8: f001 f80c bl 8013514 <xQueueSemaphoreTake>
80124fc: 4603 mov r3, r0
80124fe: 2b01 cmp r3, #1
8012500: d009 beq.n 8012516 <osSemaphoreAcquire+0x92>
if (timeout != 0U) {
8012502: 683b ldr r3, [r7, #0]
8012504: 2b00 cmp r3, #0
8012506: d003 beq.n 8012510 <osSemaphoreAcquire+0x8c>
stat = osErrorTimeout;
8012508: f06f 0301 mvn.w r3, #1
801250c: 617b str r3, [r7, #20]
801250e: e002 b.n 8012516 <osSemaphoreAcquire+0x92>
} else {
stat = osErrorResource;
8012510: f06f 0302 mvn.w r3, #2
8012514: 617b str r3, [r7, #20]
}
}
}
/* Return execution status */
return (stat);
8012516: 697b ldr r3, [r7, #20]
}
8012518: 4618 mov r0, r3
801251a: 3718 adds r7, #24
801251c: 46bd mov sp, r7
801251e: bd80 pop {r7, pc}
8012520: e000ed04 .word 0xe000ed04
08012524 <osSemaphoreRelease>:
/*
Release a Semaphore token up to the initial maximum count.
*/
osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {
8012524: b580 push {r7, lr}
8012526: b086 sub sp, #24
8012528: af00 add r7, sp, #0
801252a: 6078 str r0, [r7, #4]
SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
801252c: 687b ldr r3, [r7, #4]
801252e: 613b str r3, [r7, #16]
osStatus_t stat;
BaseType_t yield;
stat = osOK;
8012530: 2300 movs r3, #0
8012532: 617b str r3, [r7, #20]
if (hSemaphore == NULL) {
8012534: 693b ldr r3, [r7, #16]
8012536: 2b00 cmp r3, #0
8012538: d103 bne.n 8012542 <osSemaphoreRelease+0x1e>
stat = osErrorParameter;
801253a: f06f 0303 mvn.w r3, #3
801253e: 617b str r3, [r7, #20]
8012540: e02b b.n 801259a <osSemaphoreRelease+0x76>
}
else if (IRQ_Context() != 0U) {
8012542: f7ff fc04 bl 8011d4e <IRQ_Context>
8012546: 4603 mov r3, r0
8012548: 2b00 cmp r3, #0
801254a: d01a beq.n 8012582 <osSemaphoreRelease+0x5e>
yield = pdFALSE;
801254c: 2300 movs r3, #0
801254e: 60fb str r3, [r7, #12]
if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) {
8012550: f107 030c add.w r3, r7, #12
8012554: 4619 mov r1, r3
8012556: 6938 ldr r0, [r7, #16]
8012558: f000 fe52 bl 8013200 <xQueueGiveFromISR>
801255c: 4603 mov r3, r0
801255e: 2b01 cmp r3, #1
8012560: d003 beq.n 801256a <osSemaphoreRelease+0x46>
stat = osErrorResource;
8012562: f06f 0302 mvn.w r3, #2
8012566: 617b str r3, [r7, #20]
8012568: e017 b.n 801259a <osSemaphoreRelease+0x76>
} else {
portYIELD_FROM_ISR (yield);
801256a: 68fb ldr r3, [r7, #12]
801256c: 2b00 cmp r3, #0
801256e: d014 beq.n 801259a <osSemaphoreRelease+0x76>
8012570: 4b0c ldr r3, [pc, #48] @ (80125a4 <osSemaphoreRelease+0x80>)
8012572: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8012576: 601a str r2, [r3, #0]
8012578: f3bf 8f4f dsb sy
801257c: f3bf 8f6f isb sy
8012580: e00b b.n 801259a <osSemaphoreRelease+0x76>
}
}
else {
if (xSemaphoreGive (hSemaphore) != pdPASS) {
8012582: 2300 movs r3, #0
8012584: 2200 movs r2, #0
8012586: 2100 movs r1, #0
8012588: 6938 ldr r0, [r7, #16]
801258a: f000 fc81 bl 8012e90 <xQueueGenericSend>
801258e: 4603 mov r3, r0
8012590: 2b01 cmp r3, #1
8012592: d002 beq.n 801259a <osSemaphoreRelease+0x76>
stat = osErrorResource;
8012594: f06f 0302 mvn.w r3, #2
8012598: 617b str r3, [r7, #20]
}
}
/* Return execution status */
return (stat);
801259a: 697b ldr r3, [r7, #20]
}
801259c: 4618 mov r0, r3
801259e: 3718 adds r7, #24
80125a0: 46bd mov sp, r7
80125a2: bd80 pop {r7, pc}
80125a4: e000ed04 .word 0xe000ed04
080125a8 <osMessageQueueNew>:
Limitations:
- The memory for control block and and message data must be provided in the
osThreadAttr_t structure in order to allocate object statically.
*/
osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
80125a8: b580 push {r7, lr}
80125aa: b088 sub sp, #32
80125ac: af02 add r7, sp, #8
80125ae: 60f8 str r0, [r7, #12]
80125b0: 60b9 str r1, [r7, #8]
80125b2: 607a str r2, [r7, #4]
QueueHandle_t hQueue;
int32_t mem;
hQueue = NULL;
80125b4: 2300 movs r3, #0
80125b6: 617b str r3, [r7, #20]
if ((IRQ_Context() == 0U) && (msg_count > 0U) && (msg_size > 0U)) {
80125b8: f7ff fbc9 bl 8011d4e <IRQ_Context>
80125bc: 4603 mov r3, r0
80125be: 2b00 cmp r3, #0
80125c0: d15f bne.n 8012682 <osMessageQueueNew+0xda>
80125c2: 68fb ldr r3, [r7, #12]
80125c4: 2b00 cmp r3, #0
80125c6: d05c beq.n 8012682 <osMessageQueueNew+0xda>
80125c8: 68bb ldr r3, [r7, #8]
80125ca: 2b00 cmp r3, #0
80125cc: d059 beq.n 8012682 <osMessageQueueNew+0xda>
mem = -1;
80125ce: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
80125d2: 613b str r3, [r7, #16]
if (attr != NULL) {
80125d4: 687b ldr r3, [r7, #4]
80125d6: 2b00 cmp r3, #0
80125d8: d029 beq.n 801262e <osMessageQueueNew+0x86>
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
80125da: 687b ldr r3, [r7, #4]
80125dc: 689b ldr r3, [r3, #8]
80125de: 2b00 cmp r3, #0
80125e0: d012 beq.n 8012608 <osMessageQueueNew+0x60>
80125e2: 687b ldr r3, [r7, #4]
80125e4: 68db ldr r3, [r3, #12]
80125e6: 2b4f cmp r3, #79 @ 0x4f
80125e8: d90e bls.n 8012608 <osMessageQueueNew+0x60>
(attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
80125ea: 687b ldr r3, [r7, #4]
80125ec: 691b ldr r3, [r3, #16]
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
80125ee: 2b00 cmp r3, #0
80125f0: d00a beq.n 8012608 <osMessageQueueNew+0x60>
(attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
80125f2: 687b ldr r3, [r7, #4]
80125f4: 695a ldr r2, [r3, #20]
80125f6: 68fb ldr r3, [r7, #12]
80125f8: 68b9 ldr r1, [r7, #8]
80125fa: fb01 f303 mul.w r3, r1, r3
80125fe: 429a cmp r2, r3
8012600: d302 bcc.n 8012608 <osMessageQueueNew+0x60>
/* The memory for control block and message data is provided, use static object */
mem = 1;
8012602: 2301 movs r3, #1
8012604: 613b str r3, [r7, #16]
8012606: e014 b.n 8012632 <osMessageQueueNew+0x8a>
}
else {
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
8012608: 687b ldr r3, [r7, #4]
801260a: 689b ldr r3, [r3, #8]
801260c: 2b00 cmp r3, #0
801260e: d110 bne.n 8012632 <osMessageQueueNew+0x8a>
8012610: 687b ldr r3, [r7, #4]
8012612: 68db ldr r3, [r3, #12]
8012614: 2b00 cmp r3, #0
8012616: d10c bne.n 8012632 <osMessageQueueNew+0x8a>
(attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
8012618: 687b ldr r3, [r7, #4]
801261a: 691b ldr r3, [r3, #16]
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
801261c: 2b00 cmp r3, #0
801261e: d108 bne.n 8012632 <osMessageQueueNew+0x8a>
(attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
8012620: 687b ldr r3, [r7, #4]
8012622: 695b ldr r3, [r3, #20]
8012624: 2b00 cmp r3, #0
8012626: d104 bne.n 8012632 <osMessageQueueNew+0x8a>
/* Control block will be allocated from the dynamic pool */
mem = 0;
8012628: 2300 movs r3, #0
801262a: 613b str r3, [r7, #16]
801262c: e001 b.n 8012632 <osMessageQueueNew+0x8a>
}
}
}
else {
mem = 0;
801262e: 2300 movs r3, #0
8012630: 613b str r3, [r7, #16]
}
if (mem == 1) {
8012632: 693b ldr r3, [r7, #16]
8012634: 2b01 cmp r3, #1
8012636: d10b bne.n 8012650 <osMessageQueueNew+0xa8>
#if (configSUPPORT_STATIC_ALLOCATION == 1)
hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);
8012638: 687b ldr r3, [r7, #4]
801263a: 691a ldr r2, [r3, #16]
801263c: 687b ldr r3, [r7, #4]
801263e: 689b ldr r3, [r3, #8]
8012640: 2100 movs r1, #0
8012642: 9100 str r1, [sp, #0]
8012644: 68b9 ldr r1, [r7, #8]
8012646: 68f8 ldr r0, [r7, #12]
8012648: f000 fa30 bl 8012aac <xQueueGenericCreateStatic>
801264c: 6178 str r0, [r7, #20]
801264e: e008 b.n 8012662 <osMessageQueueNew+0xba>
#endif
}
else {
if (mem == 0) {
8012650: 693b ldr r3, [r7, #16]
8012652: 2b00 cmp r3, #0
8012654: d105 bne.n 8012662 <osMessageQueueNew+0xba>
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
hQueue = xQueueCreate (msg_count, msg_size);
8012656: 2200 movs r2, #0
8012658: 68b9 ldr r1, [r7, #8]
801265a: 68f8 ldr r0, [r7, #12]
801265c: f000 fa87 bl 8012b6e <xQueueGenericCreate>
8012660: 6178 str r0, [r7, #20]
#endif
}
}
#if (configQUEUE_REGISTRY_SIZE > 0)
if (hQueue != NULL) {
8012662: 697b ldr r3, [r7, #20]
8012664: 2b00 cmp r3, #0
8012666: d00c beq.n 8012682 <osMessageQueueNew+0xda>
if ((attr != NULL) && (attr->name != NULL)) {
8012668: 687b ldr r3, [r7, #4]
801266a: 2b00 cmp r3, #0
801266c: d009 beq.n 8012682 <osMessageQueueNew+0xda>
801266e: 687b ldr r3, [r7, #4]
8012670: 681b ldr r3, [r3, #0]
8012672: 2b00 cmp r3, #0
8012674: d005 beq.n 8012682 <osMessageQueueNew+0xda>
/* Only non-NULL name objects are added to the Queue Registry */
vQueueAddToRegistry (hQueue, attr->name);
8012676: 687b ldr r3, [r7, #4]
8012678: 681b ldr r3, [r3, #0]
801267a: 4619 mov r1, r3
801267c: 6978 ldr r0, [r7, #20]
801267e: f001 fa2f bl 8013ae0 <vQueueAddToRegistry>
#endif
}
/* Return message queue ID */
return ((osMessageQueueId_t)hQueue);
8012682: 697b ldr r3, [r7, #20]
}
8012684: 4618 mov r0, r3
8012686: 3718 adds r7, #24
8012688: 46bd mov sp, r7
801268a: bd80 pop {r7, pc}
0801268c <osMessageQueuePut>:
Put a Message into a Queue or timeout if Queue is full.
Limitations:
- Message priority is ignored
*/
osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
801268c: b580 push {r7, lr}
801268e: b088 sub sp, #32
8012690: af00 add r7, sp, #0
8012692: 60f8 str r0, [r7, #12]
8012694: 60b9 str r1, [r7, #8]
8012696: 603b str r3, [r7, #0]
8012698: 4613 mov r3, r2
801269a: 71fb strb r3, [r7, #7]
QueueHandle_t hQueue = (QueueHandle_t)mq_id;
801269c: 68fb ldr r3, [r7, #12]
801269e: 61bb str r3, [r7, #24]
osStatus_t stat;
BaseType_t yield;
(void)msg_prio; /* Message priority is ignored */
stat = osOK;
80126a0: 2300 movs r3, #0
80126a2: 61fb str r3, [r7, #28]
if (IRQ_Context() != 0U) {
80126a4: f7ff fb53 bl 8011d4e <IRQ_Context>
80126a8: 4603 mov r3, r0
80126aa: 2b00 cmp r3, #0
80126ac: d028 beq.n 8012700 <osMessageQueuePut+0x74>
if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
80126ae: 69bb ldr r3, [r7, #24]
80126b0: 2b00 cmp r3, #0
80126b2: d005 beq.n 80126c0 <osMessageQueuePut+0x34>
80126b4: 68bb ldr r3, [r7, #8]
80126b6: 2b00 cmp r3, #0
80126b8: d002 beq.n 80126c0 <osMessageQueuePut+0x34>
80126ba: 683b ldr r3, [r7, #0]
80126bc: 2b00 cmp r3, #0
80126be: d003 beq.n 80126c8 <osMessageQueuePut+0x3c>
stat = osErrorParameter;
80126c0: f06f 0303 mvn.w r3, #3
80126c4: 61fb str r3, [r7, #28]
80126c6: e038 b.n 801273a <osMessageQueuePut+0xae>
}
else {
yield = pdFALSE;
80126c8: 2300 movs r3, #0
80126ca: 617b str r3, [r7, #20]
if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {
80126cc: f107 0214 add.w r2, r7, #20
80126d0: 2300 movs r3, #0
80126d2: 68b9 ldr r1, [r7, #8]
80126d4: 69b8 ldr r0, [r7, #24]
80126d6: f000 fcdd bl 8013094 <xQueueGenericSendFromISR>
80126da: 4603 mov r3, r0
80126dc: 2b01 cmp r3, #1
80126de: d003 beq.n 80126e8 <osMessageQueuePut+0x5c>
stat = osErrorResource;
80126e0: f06f 0302 mvn.w r3, #2
80126e4: 61fb str r3, [r7, #28]
80126e6: e028 b.n 801273a <osMessageQueuePut+0xae>
} else {
portYIELD_FROM_ISR (yield);
80126e8: 697b ldr r3, [r7, #20]
80126ea: 2b00 cmp r3, #0
80126ec: d025 beq.n 801273a <osMessageQueuePut+0xae>
80126ee: 4b15 ldr r3, [pc, #84] @ (8012744 <osMessageQueuePut+0xb8>)
80126f0: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80126f4: 601a str r2, [r3, #0]
80126f6: f3bf 8f4f dsb sy
80126fa: f3bf 8f6f isb sy
80126fe: e01c b.n 801273a <osMessageQueuePut+0xae>
}
}
}
else {
if ((hQueue == NULL) || (msg_ptr == NULL)) {
8012700: 69bb ldr r3, [r7, #24]
8012702: 2b00 cmp r3, #0
8012704: d002 beq.n 801270c <osMessageQueuePut+0x80>
8012706: 68bb ldr r3, [r7, #8]
8012708: 2b00 cmp r3, #0
801270a: d103 bne.n 8012714 <osMessageQueuePut+0x88>
stat = osErrorParameter;
801270c: f06f 0303 mvn.w r3, #3
8012710: 61fb str r3, [r7, #28]
8012712: e012 b.n 801273a <osMessageQueuePut+0xae>
}
else {
if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
8012714: 2300 movs r3, #0
8012716: 683a ldr r2, [r7, #0]
8012718: 68b9 ldr r1, [r7, #8]
801271a: 69b8 ldr r0, [r7, #24]
801271c: f000 fbb8 bl 8012e90 <xQueueGenericSend>
8012720: 4603 mov r3, r0
8012722: 2b01 cmp r3, #1
8012724: d009 beq.n 801273a <osMessageQueuePut+0xae>
if (timeout != 0U) {
8012726: 683b ldr r3, [r7, #0]
8012728: 2b00 cmp r3, #0
801272a: d003 beq.n 8012734 <osMessageQueuePut+0xa8>
stat = osErrorTimeout;
801272c: f06f 0301 mvn.w r3, #1
8012730: 61fb str r3, [r7, #28]
8012732: e002 b.n 801273a <osMessageQueuePut+0xae>
} else {
stat = osErrorResource;
8012734: f06f 0302 mvn.w r3, #2
8012738: 61fb str r3, [r7, #28]
}
}
}
/* Return execution status */
return (stat);
801273a: 69fb ldr r3, [r7, #28]
}
801273c: 4618 mov r0, r3
801273e: 3720 adds r7, #32
8012740: 46bd mov sp, r7
8012742: bd80 pop {r7, pc}
8012744: e000ed04 .word 0xe000ed04
08012748 <osMessageQueueGet>:
Get a Message from a Queue or timeout if Queue is empty.
Limitations:
- Message priority is ignored
*/
osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
8012748: b580 push {r7, lr}
801274a: b088 sub sp, #32
801274c: af00 add r7, sp, #0
801274e: 60f8 str r0, [r7, #12]
8012750: 60b9 str r1, [r7, #8]
8012752: 607a str r2, [r7, #4]
8012754: 603b str r3, [r7, #0]
QueueHandle_t hQueue = (QueueHandle_t)mq_id;
8012756: 68fb ldr r3, [r7, #12]
8012758: 61bb str r3, [r7, #24]
osStatus_t stat;
BaseType_t yield;
(void)msg_prio; /* Message priority is ignored */
stat = osOK;
801275a: 2300 movs r3, #0
801275c: 61fb str r3, [r7, #28]
if (IRQ_Context() != 0U) {
801275e: f7ff faf6 bl 8011d4e <IRQ_Context>
8012762: 4603 mov r3, r0
8012764: 2b00 cmp r3, #0
8012766: d028 beq.n 80127ba <osMessageQueueGet+0x72>
if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
8012768: 69bb ldr r3, [r7, #24]
801276a: 2b00 cmp r3, #0
801276c: d005 beq.n 801277a <osMessageQueueGet+0x32>
801276e: 68bb ldr r3, [r7, #8]
8012770: 2b00 cmp r3, #0
8012772: d002 beq.n 801277a <osMessageQueueGet+0x32>
8012774: 683b ldr r3, [r7, #0]
8012776: 2b00 cmp r3, #0
8012778: d003 beq.n 8012782 <osMessageQueueGet+0x3a>
stat = osErrorParameter;
801277a: f06f 0303 mvn.w r3, #3
801277e: 61fb str r3, [r7, #28]
8012780: e037 b.n 80127f2 <osMessageQueueGet+0xaa>
}
else {
yield = pdFALSE;
8012782: 2300 movs r3, #0
8012784: 617b str r3, [r7, #20]
if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {
8012786: f107 0314 add.w r3, r7, #20
801278a: 461a mov r2, r3
801278c: 68b9 ldr r1, [r7, #8]
801278e: 69b8 ldr r0, [r7, #24]
8012790: f000 ffc0 bl 8013714 <xQueueReceiveFromISR>
8012794: 4603 mov r3, r0
8012796: 2b01 cmp r3, #1
8012798: d003 beq.n 80127a2 <osMessageQueueGet+0x5a>
stat = osErrorResource;
801279a: f06f 0302 mvn.w r3, #2
801279e: 61fb str r3, [r7, #28]
80127a0: e027 b.n 80127f2 <osMessageQueueGet+0xaa>
} else {
portYIELD_FROM_ISR (yield);
80127a2: 697b ldr r3, [r7, #20]
80127a4: 2b00 cmp r3, #0
80127a6: d024 beq.n 80127f2 <osMessageQueueGet+0xaa>
80127a8: 4b14 ldr r3, [pc, #80] @ (80127fc <osMessageQueueGet+0xb4>)
80127aa: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80127ae: 601a str r2, [r3, #0]
80127b0: f3bf 8f4f dsb sy
80127b4: f3bf 8f6f isb sy
80127b8: e01b b.n 80127f2 <osMessageQueueGet+0xaa>
}
}
}
else {
if ((hQueue == NULL) || (msg_ptr == NULL)) {
80127ba: 69bb ldr r3, [r7, #24]
80127bc: 2b00 cmp r3, #0
80127be: d002 beq.n 80127c6 <osMessageQueueGet+0x7e>
80127c0: 68bb ldr r3, [r7, #8]
80127c2: 2b00 cmp r3, #0
80127c4: d103 bne.n 80127ce <osMessageQueueGet+0x86>
stat = osErrorParameter;
80127c6: f06f 0303 mvn.w r3, #3
80127ca: 61fb str r3, [r7, #28]
80127cc: e011 b.n 80127f2 <osMessageQueueGet+0xaa>
}
else {
if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
80127ce: 683a ldr r2, [r7, #0]
80127d0: 68b9 ldr r1, [r7, #8]
80127d2: 69b8 ldr r0, [r7, #24]
80127d4: f000 fdbc bl 8013350 <xQueueReceive>
80127d8: 4603 mov r3, r0
80127da: 2b01 cmp r3, #1
80127dc: d009 beq.n 80127f2 <osMessageQueueGet+0xaa>
if (timeout != 0U) {
80127de: 683b ldr r3, [r7, #0]
80127e0: 2b00 cmp r3, #0
80127e2: d003 beq.n 80127ec <osMessageQueueGet+0xa4>
stat = osErrorTimeout;
80127e4: f06f 0301 mvn.w r3, #1
80127e8: 61fb str r3, [r7, #28]
80127ea: e002 b.n 80127f2 <osMessageQueueGet+0xaa>
} else {
stat = osErrorResource;
80127ec: f06f 0302 mvn.w r3, #2
80127f0: 61fb str r3, [r7, #28]
}
}
}
/* Return execution status */
return (stat);
80127f2: 69fb ldr r3, [r7, #28]
}
80127f4: 4618 mov r0, r3
80127f6: 3720 adds r7, #32
80127f8: 46bd mov sp, r7
80127fa: bd80 pop {r7, pc}
80127fc: e000ed04 .word 0xe000ed04
08012800 <vApplicationGetIdleTaskMemory>:
#if (configSUPPORT_STATIC_ALLOCATION == 1)
/*
vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
8012800: b480 push {r7}
8012802: b085 sub sp, #20
8012804: af00 add r7, sp, #0
8012806: 60f8 str r0, [r7, #12]
8012808: 60b9 str r1, [r7, #8]
801280a: 607a str r2, [r7, #4]
/* Idle task control block and stack */
static StaticTask_t Idle_TCB;
static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
*ppxIdleTaskTCBBuffer = &Idle_TCB;
801280c: 68fb ldr r3, [r7, #12]
801280e: 4a07 ldr r2, [pc, #28] @ (801282c <vApplicationGetIdleTaskMemory+0x2c>)
8012810: 601a str r2, [r3, #0]
*ppxIdleTaskStackBuffer = &Idle_Stack[0];
8012812: 68bb ldr r3, [r7, #8]
8012814: 4a06 ldr r2, [pc, #24] @ (8012830 <vApplicationGetIdleTaskMemory+0x30>)
8012816: 601a str r2, [r3, #0]
*pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
8012818: 687b ldr r3, [r7, #4]
801281a: f44f 7200 mov.w r2, #512 @ 0x200
801281e: 601a str r2, [r3, #0]
}
8012820: bf00 nop
8012822: 3714 adds r7, #20
8012824: 46bd mov sp, r7
8012826: f85d 7b04 ldr.w r7, [sp], #4
801282a: 4770 bx lr
801282c: 200007d0 .word 0x200007d0
8012830: 2000082c .word 0x2000082c
08012834 <vApplicationGetTimerTaskMemory>:
/*
vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
8012834: b480 push {r7}
8012836: b085 sub sp, #20
8012838: af00 add r7, sp, #0
801283a: 60f8 str r0, [r7, #12]
801283c: 60b9 str r1, [r7, #8]
801283e: 607a str r2, [r7, #4]
/* Timer task control block and stack */
static StaticTask_t Timer_TCB;
static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
*ppxTimerTaskTCBBuffer = &Timer_TCB;
8012840: 68fb ldr r3, [r7, #12]
8012842: 4a07 ldr r2, [pc, #28] @ (8012860 <vApplicationGetTimerTaskMemory+0x2c>)
8012844: 601a str r2, [r3, #0]
*ppxTimerTaskStackBuffer = &Timer_Stack[0];
8012846: 68bb ldr r3, [r7, #8]
8012848: 4a06 ldr r2, [pc, #24] @ (8012864 <vApplicationGetTimerTaskMemory+0x30>)
801284a: 601a str r2, [r3, #0]
*pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
801284c: 687b ldr r3, [r7, #4]
801284e: f44f 6280 mov.w r2, #1024 @ 0x400
8012852: 601a str r2, [r3, #0]
}
8012854: bf00 nop
8012856: 3714 adds r7, #20
8012858: 46bd mov sp, r7
801285a: f85d 7b04 ldr.w r7, [sp], #4
801285e: 4770 bx lr
8012860: 2000102c .word 0x2000102c
8012864: 20001088 .word 0x20001088
08012868 <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
8012868: b480 push {r7}
801286a: b083 sub sp, #12
801286c: af00 add r7, sp, #0
801286e: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
* end of the list. To initialise the list the list end is inserted
* as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8012870: 687b ldr r3, [r7, #4]
8012872: f103 0208 add.w r2, r3, #8
8012876: 687b ldr r3, [r7, #4]
8012878: 605a str r2, [r3, #4]
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
/* The list end value is the highest possible value in the list to
* ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
801287a: 687b ldr r3, [r7, #4]
801287c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8012880: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
* when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8012882: 687b ldr r3, [r7, #4]
8012884: f103 0208 add.w r2, r3, #8
8012888: 687b ldr r3, [r7, #4]
801288a: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
801288c: 687b ldr r3, [r7, #4]
801288e: f103 0208 add.w r2, r3, #8
8012892: 687b ldr r3, [r7, #4]
8012894: 611a str r2, [r3, #16]
pxList->xListEnd.pxContainer = NULL;
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
}
#endif
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
8012896: 687b ldr r3, [r7, #4]
8012898: 2200 movs r2, #0
801289a: 601a str r2, [r3, #0]
/* Write known values into the list if
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
801289c: bf00 nop
801289e: 370c adds r7, #12
80128a0: 46bd mov sp, r7
80128a2: f85d 7b04 ldr.w r7, [sp], #4
80128a6: 4770 bx lr
080128a8 <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
80128a8: b480 push {r7}
80128aa: b083 sub sp, #12
80128ac: af00 add r7, sp, #0
80128ae: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
80128b0: 687b ldr r3, [r7, #4]
80128b2: 2200 movs r2, #0
80128b4: 611a str r2, [r3, #16]
/* Write known values into the list item if
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
80128b6: bf00 nop
80128b8: 370c adds r7, #12
80128ba: 46bd mov sp, r7
80128bc: f85d 7b04 ldr.w r7, [sp], #4
80128c0: 4770 bx lr
080128c2 <vListInsert>:
}
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList,
ListItem_t * const pxNewListItem )
{
80128c2: b480 push {r7}
80128c4: b085 sub sp, #20
80128c6: af00 add r7, sp, #0
80128c8: 6078 str r0, [r7, #4]
80128ca: 6039 str r1, [r7, #0]
ListItem_t * pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
80128cc: 683b ldr r3, [r7, #0]
80128ce: 681b ldr r3, [r3, #0]
80128d0: 60bb str r3, [r7, #8]
* new list item should be placed after it. This ensures that TCBs which are
* stored in ready lists (all of which have the same xItemValue value) get a
* share of the CPU. However, if the xItemValue is the same as the back marker
* the iteration loop below will not end. Therefore the value is checked
* first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
80128d2: 68bb ldr r3, [r7, #8]
80128d4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80128d8: d103 bne.n 80128e2 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
80128da: 687b ldr r3, [r7, #4]
80128dc: 691b ldr r3, [r3, #16]
80128de: 60fb str r3, [r7, #12]
80128e0: e00c b.n 80128fc <vListInsert+0x3a>
* 5) If the FreeRTOS port supports interrupt nesting then ensure that
* the priority of the tick interrupt is at or below
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
80128e2: 687b ldr r3, [r7, #4]
80128e4: 3308 adds r3, #8
80128e6: 60fb str r3, [r7, #12]
80128e8: e002 b.n 80128f0 <vListInsert+0x2e>
80128ea: 68fb ldr r3, [r7, #12]
80128ec: 685b ldr r3, [r3, #4]
80128ee: 60fb str r3, [r7, #12]
80128f0: 68fb ldr r3, [r7, #12]
80128f2: 685b ldr r3, [r3, #4]
80128f4: 681b ldr r3, [r3, #0]
80128f6: 68ba ldr r2, [r7, #8]
80128f8: 429a cmp r2, r3
80128fa: d2f6 bcs.n 80128ea <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
* insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
80128fc: 68fb ldr r3, [r7, #12]
80128fe: 685a ldr r2, [r3, #4]
8012900: 683b ldr r3, [r7, #0]
8012902: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
8012904: 683b ldr r3, [r7, #0]
8012906: 685b ldr r3, [r3, #4]
8012908: 683a ldr r2, [r7, #0]
801290a: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
801290c: 683b ldr r3, [r7, #0]
801290e: 68fa ldr r2, [r7, #12]
8012910: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
8012912: 68fb ldr r3, [r7, #12]
8012914: 683a ldr r2, [r7, #0]
8012916: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
* item later. */
pxNewListItem->pxContainer = pxList;
8012918: 683b ldr r3, [r7, #0]
801291a: 687a ldr r2, [r7, #4]
801291c: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
801291e: 687b ldr r3, [r7, #4]
8012920: 681b ldr r3, [r3, #0]
8012922: 1c5a adds r2, r3, #1
8012924: 687b ldr r3, [r7, #4]
8012926: 601a str r2, [r3, #0]
}
8012928: bf00 nop
801292a: 3714 adds r7, #20
801292c: 46bd mov sp, r7
801292e: f85d 7b04 ldr.w r7, [sp], #4
8012932: 4770 bx lr
08012934 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
8012934: b480 push {r7}
8012936: b085 sub sp, #20
8012938: af00 add r7, sp, #0
801293a: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
* item. */
List_t * const pxList = pxItemToRemove->pxContainer;
801293c: 687b ldr r3, [r7, #4]
801293e: 691b ldr r3, [r3, #16]
8012940: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
8012942: 687b ldr r3, [r7, #4]
8012944: 685b ldr r3, [r3, #4]
8012946: 687a ldr r2, [r7, #4]
8012948: 6892 ldr r2, [r2, #8]
801294a: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
801294c: 687b ldr r3, [r7, #4]
801294e: 689b ldr r3, [r3, #8]
8012950: 687a ldr r2, [r7, #4]
8012952: 6852 ldr r2, [r2, #4]
8012954: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
8012956: 68fb ldr r3, [r7, #12]
8012958: 685b ldr r3, [r3, #4]
801295a: 687a ldr r2, [r7, #4]
801295c: 429a cmp r2, r3
801295e: d103 bne.n 8012968 <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
8012960: 687b ldr r3, [r7, #4]
8012962: 689a ldr r2, [r3, #8]
8012964: 68fb ldr r3, [r7, #12]
8012966: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
8012968: 687b ldr r3, [r7, #4]
801296a: 2200 movs r2, #0
801296c: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
801296e: 68fb ldr r3, [r7, #12]
8012970: 681b ldr r3, [r3, #0]
8012972: 1e5a subs r2, r3, #1
8012974: 68fb ldr r3, [r7, #12]
8012976: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
8012978: 68fb ldr r3, [r7, #12]
801297a: 681b ldr r3, [r3, #0]
}
801297c: 4618 mov r0, r3
801297e: 3714 adds r7, #20
8012980: 46bd mov sp, r7
8012982: f85d 7b04 ldr.w r7, [sp], #4
8012986: 4770 bx lr
08012988 <xQueueGenericReset>:
} while( 0 )
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
BaseType_t xNewQueue )
{
8012988: b580 push {r7, lr}
801298a: b086 sub sp, #24
801298c: af00 add r7, sp, #0
801298e: 6078 str r0, [r7, #4]
8012990: 6039 str r1, [r7, #0]
BaseType_t xReturn = pdPASS;
8012992: 2301 movs r3, #1
8012994: 617b str r3, [r7, #20]
Queue_t * const pxQueue = xQueue;
8012996: 687b ldr r3, [r7, #4]
8012998: 613b str r3, [r7, #16]
configASSERT( pxQueue );
801299a: 693b ldr r3, [r7, #16]
801299c: 2b00 cmp r3, #0
801299e: d10b bne.n 80129b8 <xQueueGenericReset+0x30>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
80129a0: f04f 0350 mov.w r3, #80 @ 0x50
80129a4: f383 8811 msr BASEPRI, r3
80129a8: f3bf 8f6f isb sy
80129ac: f3bf 8f4f dsb sy
80129b0: 60fb str r3, [r7, #12]
" msr basepri, %0 \n"\
" isb \n"\
" dsb \n"\
: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
80129b2: bf00 nop
80129b4: bf00 nop
80129b6: e7fd b.n 80129b4 <xQueueGenericReset+0x2c>
if( ( pxQueue != NULL ) &&
80129b8: 693b ldr r3, [r7, #16]
80129ba: 2b00 cmp r3, #0
80129bc: d05d beq.n 8012a7a <xQueueGenericReset+0xf2>
( pxQueue->uxLength >= 1U ) &&
80129be: 693b ldr r3, [r7, #16]
80129c0: 6bdb ldr r3, [r3, #60] @ 0x3c
if( ( pxQueue != NULL ) &&
80129c2: 2b00 cmp r3, #0
80129c4: d059 beq.n 8012a7a <xQueueGenericReset+0xf2>
/* Check for multiplication overflow. */
( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) )
80129c6: 693b ldr r3, [r7, #16]
80129c8: 6c1a ldr r2, [r3, #64] @ 0x40
80129ca: 693b ldr r3, [r7, #16]
80129cc: 6bdb ldr r3, [r3, #60] @ 0x3c
80129ce: 2100 movs r1, #0
80129d0: fba3 2302 umull r2, r3, r3, r2
80129d4: 2b00 cmp r3, #0
80129d6: d000 beq.n 80129da <xQueueGenericReset+0x52>
80129d8: 2101 movs r1, #1
80129da: 460b mov r3, r1
( pxQueue->uxLength >= 1U ) &&
80129dc: 2b00 cmp r3, #0
80129de: d14c bne.n 8012a7a <xQueueGenericReset+0xf2>
{
taskENTER_CRITICAL();
80129e0: f003 fc1e bl 8016220 <vPortEnterCritical>
{
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
80129e4: 693b ldr r3, [r7, #16]
80129e6: 681a ldr r2, [r3, #0]
80129e8: 693b ldr r3, [r7, #16]
80129ea: 6bdb ldr r3, [r3, #60] @ 0x3c
80129ec: 6939 ldr r1, [r7, #16]
80129ee: 6c09 ldr r1, [r1, #64] @ 0x40
80129f0: fb01 f303 mul.w r3, r1, r3
80129f4: 441a add r2, r3
80129f6: 693b ldr r3, [r7, #16]
80129f8: 609a str r2, [r3, #8]
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
80129fa: 693b ldr r3, [r7, #16]
80129fc: 2200 movs r2, #0
80129fe: 639a str r2, [r3, #56] @ 0x38
pxQueue->pcWriteTo = pxQueue->pcHead;
8012a00: 693b ldr r3, [r7, #16]
8012a02: 681a ldr r2, [r3, #0]
8012a04: 693b ldr r3, [r7, #16]
8012a06: 605a str r2, [r3, #4]
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8012a08: 693b ldr r3, [r7, #16]
8012a0a: 681a ldr r2, [r3, #0]
8012a0c: 693b ldr r3, [r7, #16]
8012a0e: 6bdb ldr r3, [r3, #60] @ 0x3c
8012a10: 3b01 subs r3, #1
8012a12: 6939 ldr r1, [r7, #16]
8012a14: 6c09 ldr r1, [r1, #64] @ 0x40
8012a16: fb01 f303 mul.w r3, r1, r3
8012a1a: 441a add r2, r3
8012a1c: 693b ldr r3, [r7, #16]
8012a1e: 60da str r2, [r3, #12]
pxQueue->cRxLock = queueUNLOCKED;
8012a20: 693b ldr r3, [r7, #16]
8012a22: 22ff movs r2, #255 @ 0xff
8012a24: f883 2044 strb.w r2, [r3, #68] @ 0x44
pxQueue->cTxLock = queueUNLOCKED;
8012a28: 693b ldr r3, [r7, #16]
8012a2a: 22ff movs r2, #255 @ 0xff
8012a2c: f883 2045 strb.w r2, [r3, #69] @ 0x45
if( xNewQueue == pdFALSE )
8012a30: 683b ldr r3, [r7, #0]
8012a32: 2b00 cmp r3, #0
8012a34: d114 bne.n 8012a60 <xQueueGenericReset+0xd8>
/* If there are tasks blocked waiting to read from the queue, then
* the tasks will remain blocked as after this function exits the queue
* will still be empty. If there are tasks blocked waiting to write to
* the queue, then one should be unblocked as after this function exits
* it will be possible to write to it. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8012a36: 693b ldr r3, [r7, #16]
8012a38: 691b ldr r3, [r3, #16]
8012a3a: 2b00 cmp r3, #0
8012a3c: d01a beq.n 8012a74 <xQueueGenericReset+0xec>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8012a3e: 693b ldr r3, [r7, #16]
8012a40: 3310 adds r3, #16
8012a42: 4618 mov r0, r3
8012a44: f001 fe8e bl 8014764 <xTaskRemoveFromEventList>
8012a48: 4603 mov r3, r0
8012a4a: 2b00 cmp r3, #0
8012a4c: d012 beq.n 8012a74 <xQueueGenericReset+0xec>
{
queueYIELD_IF_USING_PREEMPTION();
8012a4e: 4b16 ldr r3, [pc, #88] @ (8012aa8 <xQueueGenericReset+0x120>)
8012a50: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8012a54: 601a str r2, [r3, #0]
8012a56: f3bf 8f4f dsb sy
8012a5a: f3bf 8f6f isb sy
8012a5e: e009 b.n 8012a74 <xQueueGenericReset+0xec>
}
}
else
{
/* Ensure the event queues start in the correct state. */
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
8012a60: 693b ldr r3, [r7, #16]
8012a62: 3310 adds r3, #16
8012a64: 4618 mov r0, r3
8012a66: f7ff feff bl 8012868 <vListInitialise>
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
8012a6a: 693b ldr r3, [r7, #16]
8012a6c: 3324 adds r3, #36 @ 0x24
8012a6e: 4618 mov r0, r3
8012a70: f7ff fefa bl 8012868 <vListInitialise>
}
}
taskEXIT_CRITICAL();
8012a74: f003 fc06 bl 8016284 <vPortExitCritical>
8012a78: e001 b.n 8012a7e <xQueueGenericReset+0xf6>
}
else
{
xReturn = pdFAIL;
8012a7a: 2300 movs r3, #0
8012a7c: 617b str r3, [r7, #20]
}
configASSERT( xReturn != pdFAIL );
8012a7e: 697b ldr r3, [r7, #20]
8012a80: 2b00 cmp r3, #0
8012a82: d10b bne.n 8012a9c <xQueueGenericReset+0x114>
__asm volatile
8012a84: f04f 0350 mov.w r3, #80 @ 0x50
8012a88: f383 8811 msr BASEPRI, r3
8012a8c: f3bf 8f6f isb sy
8012a90: f3bf 8f4f dsb sy
8012a94: 60bb str r3, [r7, #8]
}
8012a96: bf00 nop
8012a98: bf00 nop
8012a9a: e7fd b.n 8012a98 <xQueueGenericReset+0x110>
/* A value is returned for calling semantic consistency with previous
* versions. */
return xReturn;
8012a9c: 697b ldr r3, [r7, #20]
}
8012a9e: 4618 mov r0, r3
8012aa0: 3718 adds r7, #24
8012aa2: 46bd mov sp, r7
8012aa4: bd80 pop {r7, pc}
8012aa6: bf00 nop
8012aa8: e000ed04 .word 0xe000ed04
08012aac <xQueueGenericCreateStatic>:
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
const UBaseType_t uxItemSize,
uint8_t * pucQueueStorage,
StaticQueue_t * pxStaticQueue,
const uint8_t ucQueueType )
{
8012aac: b580 push {r7, lr}
8012aae: b08c sub sp, #48 @ 0x30
8012ab0: af02 add r7, sp, #8
8012ab2: 60f8 str r0, [r7, #12]
8012ab4: 60b9 str r1, [r7, #8]
8012ab6: 607a str r2, [r7, #4]
8012ab8: 603b str r3, [r7, #0]
Queue_t * pxNewQueue = NULL;
8012aba: 2300 movs r3, #0
8012abc: 627b str r3, [r7, #36] @ 0x24
/* The StaticQueue_t structure and the queue storage area must be
* supplied. */
configASSERT( pxStaticQueue );
8012abe: 683b ldr r3, [r7, #0]
8012ac0: 2b00 cmp r3, #0
8012ac2: d10b bne.n 8012adc <xQueueGenericCreateStatic+0x30>
__asm volatile
8012ac4: f04f 0350 mov.w r3, #80 @ 0x50
8012ac8: f383 8811 msr BASEPRI, r3
8012acc: f3bf 8f6f isb sy
8012ad0: f3bf 8f4f dsb sy
8012ad4: 623b str r3, [r7, #32]
}
8012ad6: bf00 nop
8012ad8: bf00 nop
8012ada: e7fd b.n 8012ad8 <xQueueGenericCreateStatic+0x2c>
if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
8012adc: 68fb ldr r3, [r7, #12]
8012ade: 2b00 cmp r3, #0
8012ae0: d031 beq.n 8012b46 <xQueueGenericCreateStatic+0x9a>
8012ae2: 683b ldr r3, [r7, #0]
8012ae4: 2b00 cmp r3, #0
8012ae6: d02e beq.n 8012b46 <xQueueGenericCreateStatic+0x9a>
( pxStaticQueue != NULL ) &&
8012ae8: 687b ldr r3, [r7, #4]
8012aea: 2b00 cmp r3, #0
8012aec: d002 beq.n 8012af4 <xQueueGenericCreateStatic+0x48>
/* A queue storage area should be provided if the item size is not 0, and
* should not be provided if the item size is 0. */
( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) &&
8012aee: 68bb ldr r3, [r7, #8]
8012af0: 2b00 cmp r3, #0
8012af2: d028 beq.n 8012b46 <xQueueGenericCreateStatic+0x9a>
8012af4: 687b ldr r3, [r7, #4]
8012af6: 2b00 cmp r3, #0
8012af8: d102 bne.n 8012b00 <xQueueGenericCreateStatic+0x54>
( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) )
8012afa: 68bb ldr r3, [r7, #8]
8012afc: 2b00 cmp r3, #0
8012afe: d122 bne.n 8012b46 <xQueueGenericCreateStatic+0x9a>
#if ( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
* variable of type StaticQueue_t or StaticSemaphore_t equals the size of
* the real queue and semaphore structures. */
volatile size_t xSize = sizeof( StaticQueue_t );
8012b00: 2350 movs r3, #80 @ 0x50
8012b02: 617b str r3, [r7, #20]
/* This assertion cannot be branch covered in unit tests */
configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */
8012b04: 697b ldr r3, [r7, #20]
8012b06: 2b50 cmp r3, #80 @ 0x50
8012b08: d00b beq.n 8012b22 <xQueueGenericCreateStatic+0x76>
__asm volatile
8012b0a: f04f 0350 mov.w r3, #80 @ 0x50
8012b0e: f383 8811 msr BASEPRI, r3
8012b12: f3bf 8f6f isb sy
8012b16: f3bf 8f4f dsb sy
8012b1a: 61fb str r3, [r7, #28]
}
8012b1c: bf00 nop
8012b1e: bf00 nop
8012b20: e7fd b.n 8012b1e <xQueueGenericCreateStatic+0x72>
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
8012b22: 697b ldr r3, [r7, #20]
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
* The address of a statically allocated storage area was also passed in
* but is already set. */
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
8012b24: 683b ldr r3, [r7, #0]
8012b26: 627b str r3, [r7, #36] @ 0x24
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* Queues can be allocated wither statically or dynamically, so
* note this queue was allocated statically in case the queue is
* later deleted. */
pxNewQueue->ucStaticallyAllocated = pdTRUE;
8012b28: 6a7b ldr r3, [r7, #36] @ 0x24
8012b2a: 2201 movs r2, #1
8012b2c: f883 2046 strb.w r2, [r3, #70] @ 0x46
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
8012b30: f897 2030 ldrb.w r2, [r7, #48] @ 0x30
8012b34: 6a7b ldr r3, [r7, #36] @ 0x24
8012b36: 9300 str r3, [sp, #0]
8012b38: 4613 mov r3, r2
8012b3a: 687a ldr r2, [r7, #4]
8012b3c: 68b9 ldr r1, [r7, #8]
8012b3e: 68f8 ldr r0, [r7, #12]
8012b40: f000 f868 bl 8012c14 <prvInitialiseNewQueue>
8012b44: e00e b.n 8012b64 <xQueueGenericCreateStatic+0xb8>
}
else
{
configASSERT( pxNewQueue );
8012b46: 6a7b ldr r3, [r7, #36] @ 0x24
8012b48: 2b00 cmp r3, #0
8012b4a: d10b bne.n 8012b64 <xQueueGenericCreateStatic+0xb8>
__asm volatile
8012b4c: f04f 0350 mov.w r3, #80 @ 0x50
8012b50: f383 8811 msr BASEPRI, r3
8012b54: f3bf 8f6f isb sy
8012b58: f3bf 8f4f dsb sy
8012b5c: 61bb str r3, [r7, #24]
}
8012b5e: bf00 nop
8012b60: bf00 nop
8012b62: e7fd b.n 8012b60 <xQueueGenericCreateStatic+0xb4>
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
8012b64: 6a7b ldr r3, [r7, #36] @ 0x24
}
8012b66: 4618 mov r0, r3
8012b68: 3728 adds r7, #40 @ 0x28
8012b6a: 46bd mov sp, r7
8012b6c: bd80 pop {r7, pc}
08012b6e <xQueueGenericCreate>:
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
const UBaseType_t uxItemSize,
const uint8_t ucQueueType )
{
8012b6e: b580 push {r7, lr}
8012b70: b08a sub sp, #40 @ 0x28
8012b72: af02 add r7, sp, #8
8012b74: 60f8 str r0, [r7, #12]
8012b76: 60b9 str r1, [r7, #8]
8012b78: 4613 mov r3, r2
8012b7a: 71fb strb r3, [r7, #7]
Queue_t * pxNewQueue = NULL;
8012b7c: 2300 movs r3, #0
8012b7e: 61fb str r3, [r7, #28]
size_t xQueueSizeInBytes;
uint8_t * pucQueueStorage;
if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
8012b80: 68fb ldr r3, [r7, #12]
8012b82: 2b00 cmp r3, #0
8012b84: d032 beq.n 8012bec <xQueueGenericCreate+0x7e>
/* Check for multiplication overflow. */
( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
8012b86: 2100 movs r1, #0
8012b88: 68ba ldr r2, [r7, #8]
8012b8a: 68fb ldr r3, [r7, #12]
8012b8c: fba3 2302 umull r2, r3, r3, r2
8012b90: 2b00 cmp r3, #0
8012b92: d000 beq.n 8012b96 <xQueueGenericCreate+0x28>
8012b94: 2101 movs r1, #1
8012b96: 460b mov r3, r1
if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
8012b98: 2b00 cmp r3, #0
8012b9a: d127 bne.n 8012bec <xQueueGenericCreate+0x7e>
/* Check for addition overflow. */
( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )
8012b9c: 68fb ldr r3, [r7, #12]
8012b9e: 68ba ldr r2, [r7, #8]
8012ba0: fb02 f303 mul.w r3, r2, r3
( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
8012ba4: f113 0f51 cmn.w r3, #81 @ 0x51
8012ba8: d820 bhi.n 8012bec <xQueueGenericCreate+0x7e>
{
/* Allocate enough space to hold the maximum number of items that
* can be in the queue at any time. It is valid for uxItemSize to be
* zero in the case the queue is used as a semaphore. */
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8012baa: 68fb ldr r3, [r7, #12]
8012bac: 68ba ldr r2, [r7, #8]
8012bae: fb02 f303 mul.w r3, r2, r3
8012bb2: 61bb str r3, [r7, #24]
* alignment requirements of the Queue_t structure - which in this case
* is an int8_t *. Therefore, whenever the stack alignment requirements
* are greater than or equal to the pointer to char requirements the cast
* is safe. In other cases alignment requirements are not strict (one or
* two bytes). */
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
8012bb4: 69bb ldr r3, [r7, #24]
8012bb6: 3350 adds r3, #80 @ 0x50
8012bb8: 4618 mov r0, r3
8012bba: f003 fc59 bl 8016470 <pvPortMalloc>
8012bbe: 61f8 str r0, [r7, #28]
if( pxNewQueue != NULL )
8012bc0: 69fb ldr r3, [r7, #28]
8012bc2: 2b00 cmp r3, #0
8012bc4: d021 beq.n 8012c0a <xQueueGenericCreate+0x9c>
{
/* Jump past the queue structure to find the location of the queue
* storage area. */
pucQueueStorage = ( uint8_t * ) pxNewQueue;
8012bc6: 69fb ldr r3, [r7, #28]
8012bc8: 617b str r3, [r7, #20]
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8012bca: 697b ldr r3, [r7, #20]
8012bcc: 3350 adds r3, #80 @ 0x50
8012bce: 617b str r3, [r7, #20]
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
{
/* Queues can be created either statically or dynamically, so
* note this task was created dynamically in case it is later
* deleted. */
pxNewQueue->ucStaticallyAllocated = pdFALSE;
8012bd0: 69fb ldr r3, [r7, #28]
8012bd2: 2200 movs r2, #0
8012bd4: f883 2046 strb.w r2, [r3, #70] @ 0x46
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
8012bd8: 79fa ldrb r2, [r7, #7]
8012bda: 69fb ldr r3, [r7, #28]
8012bdc: 9300 str r3, [sp, #0]
8012bde: 4613 mov r3, r2
8012be0: 697a ldr r2, [r7, #20]
8012be2: 68b9 ldr r1, [r7, #8]
8012be4: 68f8 ldr r0, [r7, #12]
8012be6: f000 f815 bl 8012c14 <prvInitialiseNewQueue>
if( pxNewQueue != NULL )
8012bea: e00e b.n 8012c0a <xQueueGenericCreate+0x9c>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
configASSERT( pxNewQueue );
8012bec: 69fb ldr r3, [r7, #28]
8012bee: 2b00 cmp r3, #0
8012bf0: d10b bne.n 8012c0a <xQueueGenericCreate+0x9c>
__asm volatile
8012bf2: f04f 0350 mov.w r3, #80 @ 0x50
8012bf6: f383 8811 msr BASEPRI, r3
8012bfa: f3bf 8f6f isb sy
8012bfe: f3bf 8f4f dsb sy
8012c02: 613b str r3, [r7, #16]
}
8012c04: bf00 nop
8012c06: bf00 nop
8012c08: e7fd b.n 8012c06 <xQueueGenericCreate+0x98>
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
8012c0a: 69fb ldr r3, [r7, #28]
}
8012c0c: 4618 mov r0, r3
8012c0e: 3720 adds r7, #32
8012c10: 46bd mov sp, r7
8012c12: bd80 pop {r7, pc}
08012c14 <prvInitialiseNewQueue>:
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
const UBaseType_t uxItemSize,
uint8_t * pucQueueStorage,
const uint8_t ucQueueType,
Queue_t * pxNewQueue )
{
8012c14: b580 push {r7, lr}
8012c16: b084 sub sp, #16
8012c18: af00 add r7, sp, #0
8012c1a: 60f8 str r0, [r7, #12]
8012c1c: 60b9 str r1, [r7, #8]
8012c1e: 607a str r2, [r7, #4]
8012c20: 70fb strb r3, [r7, #3]
/* Remove compiler warnings about unused parameters should
* configUSE_TRACE_FACILITY not be set to 1. */
( void ) ucQueueType;
if( uxItemSize == ( UBaseType_t ) 0 )
8012c22: 68bb ldr r3, [r7, #8]
8012c24: 2b00 cmp r3, #0
8012c26: d103 bne.n 8012c30 <prvInitialiseNewQueue+0x1c>
{
/* No RAM was allocated for the queue storage area, but PC head cannot
* be set to NULL because NULL is used as a key to say the queue is used as
* a mutex. Therefore just set pcHead to point to the queue as a benign
* value that is known to be within the memory map. */
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
8012c28: 69bb ldr r3, [r7, #24]
8012c2a: 69ba ldr r2, [r7, #24]
8012c2c: 601a str r2, [r3, #0]
8012c2e: e002 b.n 8012c36 <prvInitialiseNewQueue+0x22>
}
else
{
/* Set the head to the start of the queue storage area. */
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
8012c30: 69bb ldr r3, [r7, #24]
8012c32: 687a ldr r2, [r7, #4]
8012c34: 601a str r2, [r3, #0]
}
/* Initialise the queue members as described where the queue type is
* defined. */
pxNewQueue->uxLength = uxQueueLength;
8012c36: 69bb ldr r3, [r7, #24]
8012c38: 68fa ldr r2, [r7, #12]
8012c3a: 63da str r2, [r3, #60] @ 0x3c
pxNewQueue->uxItemSize = uxItemSize;
8012c3c: 69bb ldr r3, [r7, #24]
8012c3e: 68ba ldr r2, [r7, #8]
8012c40: 641a str r2, [r3, #64] @ 0x40
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
8012c42: 2101 movs r1, #1
8012c44: 69b8 ldr r0, [r7, #24]
8012c46: f7ff fe9f bl 8012988 <xQueueGenericReset>
#if ( configUSE_TRACE_FACILITY == 1 )
{
pxNewQueue->ucQueueType = ucQueueType;
8012c4a: 69bb ldr r3, [r7, #24]
8012c4c: 78fa ldrb r2, [r7, #3]
8012c4e: f883 204c strb.w r2, [r3, #76] @ 0x4c
pxNewQueue->pxQueueSetContainer = NULL;
}
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
}
8012c52: bf00 nop
8012c54: 3710 adds r7, #16
8012c56: 46bd mov sp, r7
8012c58: bd80 pop {r7, pc}
08012c5a <prvInitialiseMutex>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
static void prvInitialiseMutex( Queue_t * pxNewQueue )
{
8012c5a: b580 push {r7, lr}
8012c5c: b082 sub sp, #8
8012c5e: af00 add r7, sp, #0
8012c60: 6078 str r0, [r7, #4]
if( pxNewQueue != NULL )
8012c62: 687b ldr r3, [r7, #4]
8012c64: 2b00 cmp r3, #0
8012c66: d00e beq.n 8012c86 <prvInitialiseMutex+0x2c>
{
/* The queue create function will set all the queue structure members
* correctly for a generic queue, but this function is creating a
* mutex. Overwrite those members that need to be set differently -
* in particular the information required for priority inheritance. */
pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
8012c68: 687b ldr r3, [r7, #4]
8012c6a: 2200 movs r2, #0
8012c6c: 609a str r2, [r3, #8]
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
8012c6e: 687b ldr r3, [r7, #4]
8012c70: 2200 movs r2, #0
8012c72: 601a str r2, [r3, #0]
/* In case this is a recursive mutex. */
pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
8012c74: 687b ldr r3, [r7, #4]
8012c76: 2200 movs r2, #0
8012c78: 60da str r2, [r3, #12]
traceCREATE_MUTEX( pxNewQueue );
/* Start with the semaphore in the expected state. */
( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
8012c7a: 2300 movs r3, #0
8012c7c: 2200 movs r2, #0
8012c7e: 2100 movs r1, #0
8012c80: 6878 ldr r0, [r7, #4]
8012c82: f000 f905 bl 8012e90 <xQueueGenericSend>
}
else
{
traceCREATE_MUTEX_FAILED();
}
}
8012c86: bf00 nop
8012c88: 3708 adds r7, #8
8012c8a: 46bd mov sp, r7
8012c8c: bd80 pop {r7, pc}
08012c8e <xQueueCreateMutex>:
/*-----------------------------------------------------------*/
#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
{
8012c8e: b580 push {r7, lr}
8012c90: b086 sub sp, #24
8012c92: af00 add r7, sp, #0
8012c94: 4603 mov r3, r0
8012c96: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
8012c98: 2301 movs r3, #1
8012c9a: 617b str r3, [r7, #20]
8012c9c: 2300 movs r3, #0
8012c9e: 613b str r3, [r7, #16]
xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
8012ca0: 79fb ldrb r3, [r7, #7]
8012ca2: 461a mov r2, r3
8012ca4: 6939 ldr r1, [r7, #16]
8012ca6: 6978 ldr r0, [r7, #20]
8012ca8: f7ff ff61 bl 8012b6e <xQueueGenericCreate>
8012cac: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
8012cae: 68f8 ldr r0, [r7, #12]
8012cb0: f7ff ffd3 bl 8012c5a <prvInitialiseMutex>
return xNewQueue;
8012cb4: 68fb ldr r3, [r7, #12]
}
8012cb6: 4618 mov r0, r3
8012cb8: 3718 adds r7, #24
8012cba: 46bd mov sp, r7
8012cbc: bd80 pop {r7, pc}
08012cbe <xQueueCreateMutexStatic>:
#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
StaticQueue_t * pxStaticQueue )
{
8012cbe: b580 push {r7, lr}
8012cc0: b088 sub sp, #32
8012cc2: af02 add r7, sp, #8
8012cc4: 4603 mov r3, r0
8012cc6: 6039 str r1, [r7, #0]
8012cc8: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
8012cca: 2301 movs r3, #1
8012ccc: 617b str r3, [r7, #20]
8012cce: 2300 movs r3, #0
8012cd0: 613b str r3, [r7, #16]
/* Prevent compiler warnings about unused parameters if
* configUSE_TRACE_FACILITY does not equal 1. */
( void ) ucQueueType;
xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
8012cd2: 79fb ldrb r3, [r7, #7]
8012cd4: 9300 str r3, [sp, #0]
8012cd6: 683b ldr r3, [r7, #0]
8012cd8: 2200 movs r2, #0
8012cda: 6939 ldr r1, [r7, #16]
8012cdc: 6978 ldr r0, [r7, #20]
8012cde: f7ff fee5 bl 8012aac <xQueueGenericCreateStatic>
8012ce2: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
8012ce4: 68f8 ldr r0, [r7, #12]
8012ce6: f7ff ffb8 bl 8012c5a <prvInitialiseMutex>
return xNewQueue;
8012cea: 68fb ldr r3, [r7, #12]
}
8012cec: 4618 mov r0, r3
8012cee: 3718 adds r7, #24
8012cf0: 46bd mov sp, r7
8012cf2: bd80 pop {r7, pc}
08012cf4 <xQueueGiveMutexRecursive>:
/*-----------------------------------------------------------*/
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
{
8012cf4: b590 push {r4, r7, lr}
8012cf6: b087 sub sp, #28
8012cf8: af00 add r7, sp, #0
8012cfa: 6078 str r0, [r7, #4]
BaseType_t xReturn;
Queue_t * const pxMutex = ( Queue_t * ) xMutex;
8012cfc: 687b ldr r3, [r7, #4]
8012cfe: 613b str r3, [r7, #16]
configASSERT( pxMutex );
8012d00: 693b ldr r3, [r7, #16]
8012d02: 2b00 cmp r3, #0
8012d04: d10b bne.n 8012d1e <xQueueGiveMutexRecursive+0x2a>
__asm volatile
8012d06: f04f 0350 mov.w r3, #80 @ 0x50
8012d0a: f383 8811 msr BASEPRI, r3
8012d0e: f3bf 8f6f isb sy
8012d12: f3bf 8f4f dsb sy
8012d16: 60fb str r3, [r7, #12]
}
8012d18: bf00 nop
8012d1a: bf00 nop
8012d1c: e7fd b.n 8012d1a <xQueueGiveMutexRecursive+0x26>
* change outside of this task. If this task does not hold the mutex then
* pxMutexHolder can never coincidentally equal the tasks handle, and as
* this is the only condition we are interested in it does not matter if
* pxMutexHolder is accessed simultaneously by another task. Therefore no
* mutual exclusion is required to test the pxMutexHolder variable. */
if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
8012d1e: 693b ldr r3, [r7, #16]
8012d20: 689c ldr r4, [r3, #8]
8012d22: f001 ff53 bl 8014bcc <xTaskGetCurrentTaskHandle>
8012d26: 4603 mov r3, r0
8012d28: 429c cmp r4, r3
8012d2a: d111 bne.n 8012d50 <xQueueGiveMutexRecursive+0x5c>
/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
* the task handle, therefore no underflow check is required. Also,
* uxRecursiveCallCount is only modified by the mutex holder, and as
* there can only be one, no mutual exclusion is required to modify the
* uxRecursiveCallCount member. */
( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
8012d2c: 693b ldr r3, [r7, #16]
8012d2e: 68db ldr r3, [r3, #12]
8012d30: 1e5a subs r2, r3, #1
8012d32: 693b ldr r3, [r7, #16]
8012d34: 60da str r2, [r3, #12]
/* Has the recursive call count unwound to 0? */
if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
8012d36: 693b ldr r3, [r7, #16]
8012d38: 68db ldr r3, [r3, #12]
8012d3a: 2b00 cmp r3, #0
8012d3c: d105 bne.n 8012d4a <xQueueGiveMutexRecursive+0x56>
{
/* Return the mutex. This will automatically unblock any other
* task that might be waiting to access the mutex. */
( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
8012d3e: 2300 movs r3, #0
8012d40: 2200 movs r2, #0
8012d42: 2100 movs r1, #0
8012d44: 6938 ldr r0, [r7, #16]
8012d46: f000 f8a3 bl 8012e90 <xQueueGenericSend>
else
{
mtCOVERAGE_TEST_MARKER();
}
xReturn = pdPASS;
8012d4a: 2301 movs r3, #1
8012d4c: 617b str r3, [r7, #20]
8012d4e: e001 b.n 8012d54 <xQueueGiveMutexRecursive+0x60>
}
else
{
/* The mutex cannot be given because the calling task is not the
* holder. */
xReturn = pdFAIL;
8012d50: 2300 movs r3, #0
8012d52: 617b str r3, [r7, #20]
traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
}
return xReturn;
8012d54: 697b ldr r3, [r7, #20]
}
8012d56: 4618 mov r0, r3
8012d58: 371c adds r7, #28
8012d5a: 46bd mov sp, r7
8012d5c: bd90 pop {r4, r7, pc}
08012d5e <xQueueTakeMutexRecursive>:
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
TickType_t xTicksToWait )
{
8012d5e: b590 push {r4, r7, lr}
8012d60: b087 sub sp, #28
8012d62: af00 add r7, sp, #0
8012d64: 6078 str r0, [r7, #4]
8012d66: 6039 str r1, [r7, #0]
BaseType_t xReturn;
Queue_t * const pxMutex = ( Queue_t * ) xMutex;
8012d68: 687b ldr r3, [r7, #4]
8012d6a: 613b str r3, [r7, #16]
configASSERT( pxMutex );
8012d6c: 693b ldr r3, [r7, #16]
8012d6e: 2b00 cmp r3, #0
8012d70: d10b bne.n 8012d8a <xQueueTakeMutexRecursive+0x2c>
__asm volatile
8012d72: f04f 0350 mov.w r3, #80 @ 0x50
8012d76: f383 8811 msr BASEPRI, r3
8012d7a: f3bf 8f6f isb sy
8012d7e: f3bf 8f4f dsb sy
8012d82: 60fb str r3, [r7, #12]
}
8012d84: bf00 nop
8012d86: bf00 nop
8012d88: e7fd b.n 8012d86 <xQueueTakeMutexRecursive+0x28>
/* Comments regarding mutual exclusion as per those within
* xQueueGiveMutexRecursive(). */
traceTAKE_MUTEX_RECURSIVE( pxMutex );
if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
8012d8a: 693b ldr r3, [r7, #16]
8012d8c: 689c ldr r4, [r3, #8]
8012d8e: f001 ff1d bl 8014bcc <xTaskGetCurrentTaskHandle>
8012d92: 4603 mov r3, r0
8012d94: 429c cmp r4, r3
8012d96: d107 bne.n 8012da8 <xQueueTakeMutexRecursive+0x4a>
{
( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
8012d98: 693b ldr r3, [r7, #16]
8012d9a: 68db ldr r3, [r3, #12]
8012d9c: 1c5a adds r2, r3, #1
8012d9e: 693b ldr r3, [r7, #16]
8012da0: 60da str r2, [r3, #12]
xReturn = pdPASS;
8012da2: 2301 movs r3, #1
8012da4: 617b str r3, [r7, #20]
8012da6: e00c b.n 8012dc2 <xQueueTakeMutexRecursive+0x64>
}
else
{
xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
8012da8: 6839 ldr r1, [r7, #0]
8012daa: 6938 ldr r0, [r7, #16]
8012dac: f000 fbb2 bl 8013514 <xQueueSemaphoreTake>
8012db0: 6178 str r0, [r7, #20]
/* pdPASS will only be returned if the mutex was successfully
* obtained. The calling task may have entered the Blocked state
* before reaching here. */
if( xReturn != pdFAIL )
8012db2: 697b ldr r3, [r7, #20]
8012db4: 2b00 cmp r3, #0
8012db6: d004 beq.n 8012dc2 <xQueueTakeMutexRecursive+0x64>
{
( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
8012db8: 693b ldr r3, [r7, #16]
8012dba: 68db ldr r3, [r3, #12]
8012dbc: 1c5a adds r2, r3, #1
8012dbe: 693b ldr r3, [r7, #16]
8012dc0: 60da str r2, [r3, #12]
{
traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
}
}
return xReturn;
8012dc2: 697b ldr r3, [r7, #20]
}
8012dc4: 4618 mov r0, r3
8012dc6: 371c adds r7, #28
8012dc8: 46bd mov sp, r7
8012dca: bd90 pop {r4, r7, pc}
08012dcc <xQueueCreateCountingSemaphoreStatic>:
#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
const UBaseType_t uxInitialCount,
StaticQueue_t * pxStaticQueue )
{
8012dcc: b580 push {r7, lr}
8012dce: b088 sub sp, #32
8012dd0: af02 add r7, sp, #8
8012dd2: 60f8 str r0, [r7, #12]
8012dd4: 60b9 str r1, [r7, #8]
8012dd6: 607a str r2, [r7, #4]
QueueHandle_t xHandle = NULL;
8012dd8: 2300 movs r3, #0
8012dda: 617b str r3, [r7, #20]
if( ( uxMaxCount != 0 ) &&
8012ddc: 68fb ldr r3, [r7, #12]
8012dde: 2b00 cmp r3, #0
8012de0: d013 beq.n 8012e0a <xQueueCreateCountingSemaphoreStatic+0x3e>
8012de2: 68ba ldr r2, [r7, #8]
8012de4: 68fb ldr r3, [r7, #12]
8012de6: 429a cmp r2, r3
8012de8: d80f bhi.n 8012e0a <xQueueCreateCountingSemaphoreStatic+0x3e>
( uxInitialCount <= uxMaxCount ) )
{
xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
8012dea: 2302 movs r3, #2
8012dec: 9300 str r3, [sp, #0]
8012dee: 687b ldr r3, [r7, #4]
8012df0: 2200 movs r2, #0
8012df2: 2100 movs r1, #0
8012df4: 68f8 ldr r0, [r7, #12]
8012df6: f7ff fe59 bl 8012aac <xQueueGenericCreateStatic>
8012dfa: 6178 str r0, [r7, #20]
if( xHandle != NULL )
8012dfc: 697b ldr r3, [r7, #20]
8012dfe: 2b00 cmp r3, #0
8012e00: d012 beq.n 8012e28 <xQueueCreateCountingSemaphoreStatic+0x5c>
{
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
8012e02: 697b ldr r3, [r7, #20]
8012e04: 68ba ldr r2, [r7, #8]
8012e06: 639a str r2, [r3, #56] @ 0x38
if( xHandle != NULL )
8012e08: e00e b.n 8012e28 <xQueueCreateCountingSemaphoreStatic+0x5c>
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
}
else
{
configASSERT( xHandle );
8012e0a: 697b ldr r3, [r7, #20]
8012e0c: 2b00 cmp r3, #0
8012e0e: d10b bne.n 8012e28 <xQueueCreateCountingSemaphoreStatic+0x5c>
__asm volatile
8012e10: f04f 0350 mov.w r3, #80 @ 0x50
8012e14: f383 8811 msr BASEPRI, r3
8012e18: f3bf 8f6f isb sy
8012e1c: f3bf 8f4f dsb sy
8012e20: 613b str r3, [r7, #16]
}
8012e22: bf00 nop
8012e24: bf00 nop
8012e26: e7fd b.n 8012e24 <xQueueCreateCountingSemaphoreStatic+0x58>
mtCOVERAGE_TEST_MARKER();
}
return xHandle;
8012e28: 697b ldr r3, [r7, #20]
}
8012e2a: 4618 mov r0, r3
8012e2c: 3718 adds r7, #24
8012e2e: 46bd mov sp, r7
8012e30: bd80 pop {r7, pc}
08012e32 <xQueueCreateCountingSemaphore>:
#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
const UBaseType_t uxInitialCount )
{
8012e32: b580 push {r7, lr}
8012e34: b084 sub sp, #16
8012e36: af00 add r7, sp, #0
8012e38: 6078 str r0, [r7, #4]
8012e3a: 6039 str r1, [r7, #0]
QueueHandle_t xHandle = NULL;
8012e3c: 2300 movs r3, #0
8012e3e: 60fb str r3, [r7, #12]
if( ( uxMaxCount != 0 ) &&
8012e40: 687b ldr r3, [r7, #4]
8012e42: 2b00 cmp r3, #0
8012e44: d010 beq.n 8012e68 <xQueueCreateCountingSemaphore+0x36>
8012e46: 683a ldr r2, [r7, #0]
8012e48: 687b ldr r3, [r7, #4]
8012e4a: 429a cmp r2, r3
8012e4c: d80c bhi.n 8012e68 <xQueueCreateCountingSemaphore+0x36>
( uxInitialCount <= uxMaxCount ) )
{
xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
8012e4e: 2202 movs r2, #2
8012e50: 2100 movs r1, #0
8012e52: 6878 ldr r0, [r7, #4]
8012e54: f7ff fe8b bl 8012b6e <xQueueGenericCreate>
8012e58: 60f8 str r0, [r7, #12]
if( xHandle != NULL )
8012e5a: 68fb ldr r3, [r7, #12]
8012e5c: 2b00 cmp r3, #0
8012e5e: d012 beq.n 8012e86 <xQueueCreateCountingSemaphore+0x54>
{
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
8012e60: 68fb ldr r3, [r7, #12]
8012e62: 683a ldr r2, [r7, #0]
8012e64: 639a str r2, [r3, #56] @ 0x38
if( xHandle != NULL )
8012e66: e00e b.n 8012e86 <xQueueCreateCountingSemaphore+0x54>
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
}
else
{
configASSERT( xHandle );
8012e68: 68fb ldr r3, [r7, #12]
8012e6a: 2b00 cmp r3, #0
8012e6c: d10b bne.n 8012e86 <xQueueCreateCountingSemaphore+0x54>
__asm volatile
8012e6e: f04f 0350 mov.w r3, #80 @ 0x50
8012e72: f383 8811 msr BASEPRI, r3
8012e76: f3bf 8f6f isb sy
8012e7a: f3bf 8f4f dsb sy
8012e7e: 60bb str r3, [r7, #8]
}
8012e80: bf00 nop
8012e82: bf00 nop
8012e84: e7fd b.n 8012e82 <xQueueCreateCountingSemaphore+0x50>
mtCOVERAGE_TEST_MARKER();
}
return xHandle;
8012e86: 68fb ldr r3, [r7, #12]
}
8012e88: 4618 mov r0, r3
8012e8a: 3710 adds r7, #16
8012e8c: 46bd mov sp, r7
8012e8e: bd80 pop {r7, pc}
08012e90 <xQueueGenericSend>:
BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
const void * const pvItemToQueue,
TickType_t xTicksToWait,
const BaseType_t xCopyPosition )
{
8012e90: b580 push {r7, lr}
8012e92: b08e sub sp, #56 @ 0x38
8012e94: af00 add r7, sp, #0
8012e96: 60f8 str r0, [r7, #12]
8012e98: 60b9 str r1, [r7, #8]
8012e9a: 607a str r2, [r7, #4]
8012e9c: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
8012e9e: 2300 movs r3, #0
8012ea0: 637b str r3, [r7, #52] @ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8012ea2: 68fb ldr r3, [r7, #12]
8012ea4: 633b str r3, [r7, #48] @ 0x30
configASSERT( pxQueue );
8012ea6: 6b3b ldr r3, [r7, #48] @ 0x30
8012ea8: 2b00 cmp r3, #0
8012eaa: d10b bne.n 8012ec4 <xQueueGenericSend+0x34>
__asm volatile
8012eac: f04f 0350 mov.w r3, #80 @ 0x50
8012eb0: f383 8811 msr BASEPRI, r3
8012eb4: f3bf 8f6f isb sy
8012eb8: f3bf 8f4f dsb sy
8012ebc: 62bb str r3, [r7, #40] @ 0x28
}
8012ebe: bf00 nop
8012ec0: bf00 nop
8012ec2: e7fd b.n 8012ec0 <xQueueGenericSend+0x30>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
8012ec4: 68bb ldr r3, [r7, #8]
8012ec6: 2b00 cmp r3, #0
8012ec8: d103 bne.n 8012ed2 <xQueueGenericSend+0x42>
8012eca: 6b3b ldr r3, [r7, #48] @ 0x30
8012ecc: 6c1b ldr r3, [r3, #64] @ 0x40
8012ece: 2b00 cmp r3, #0
8012ed0: d101 bne.n 8012ed6 <xQueueGenericSend+0x46>
8012ed2: 2301 movs r3, #1
8012ed4: e000 b.n 8012ed8 <xQueueGenericSend+0x48>
8012ed6: 2300 movs r3, #0
8012ed8: 2b00 cmp r3, #0
8012eda: d10b bne.n 8012ef4 <xQueueGenericSend+0x64>
__asm volatile
8012edc: f04f 0350 mov.w r3, #80 @ 0x50
8012ee0: f383 8811 msr BASEPRI, r3
8012ee4: f3bf 8f6f isb sy
8012ee8: f3bf 8f4f dsb sy
8012eec: 627b str r3, [r7, #36] @ 0x24
}
8012eee: bf00 nop
8012ef0: bf00 nop
8012ef2: e7fd b.n 8012ef0 <xQueueGenericSend+0x60>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
8012ef4: 683b ldr r3, [r7, #0]
8012ef6: 2b02 cmp r3, #2
8012ef8: d103 bne.n 8012f02 <xQueueGenericSend+0x72>
8012efa: 6b3b ldr r3, [r7, #48] @ 0x30
8012efc: 6bdb ldr r3, [r3, #60] @ 0x3c
8012efe: 2b01 cmp r3, #1
8012f00: d101 bne.n 8012f06 <xQueueGenericSend+0x76>
8012f02: 2301 movs r3, #1
8012f04: e000 b.n 8012f08 <xQueueGenericSend+0x78>
8012f06: 2300 movs r3, #0
8012f08: 2b00 cmp r3, #0
8012f0a: d10b bne.n 8012f24 <xQueueGenericSend+0x94>
__asm volatile
8012f0c: f04f 0350 mov.w r3, #80 @ 0x50
8012f10: f383 8811 msr BASEPRI, r3
8012f14: f3bf 8f6f isb sy
8012f18: f3bf 8f4f dsb sy
8012f1c: 623b str r3, [r7, #32]
}
8012f1e: bf00 nop
8012f20: bf00 nop
8012f22: e7fd b.n 8012f20 <xQueueGenericSend+0x90>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
8012f24: f001 fe62 bl 8014bec <xTaskGetSchedulerState>
8012f28: 4603 mov r3, r0
8012f2a: 2b00 cmp r3, #0
8012f2c: d102 bne.n 8012f34 <xQueueGenericSend+0xa4>
8012f2e: 687b ldr r3, [r7, #4]
8012f30: 2b00 cmp r3, #0
8012f32: d101 bne.n 8012f38 <xQueueGenericSend+0xa8>
8012f34: 2301 movs r3, #1
8012f36: e000 b.n 8012f3a <xQueueGenericSend+0xaa>
8012f38: 2300 movs r3, #0
8012f3a: 2b00 cmp r3, #0
8012f3c: d10b bne.n 8012f56 <xQueueGenericSend+0xc6>
__asm volatile
8012f3e: f04f 0350 mov.w r3, #80 @ 0x50
8012f42: f383 8811 msr BASEPRI, r3
8012f46: f3bf 8f6f isb sy
8012f4a: f3bf 8f4f dsb sy
8012f4e: 61fb str r3, [r7, #28]
}
8012f50: bf00 nop
8012f52: bf00 nop
8012f54: e7fd b.n 8012f52 <xQueueGenericSend+0xc2>
/*lint -save -e904 This function relaxes the coding standard somewhat to
* allow return statements within the function itself. This is done in the
* interest of execution time efficiency. */
for( ; ; )
{
taskENTER_CRITICAL();
8012f56: f003 f963 bl 8016220 <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
* highest priority task wanting to access the queue. If the head item
* in the queue is to be overwritten then it does not matter if the
* queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
8012f5a: 6b3b ldr r3, [r7, #48] @ 0x30
8012f5c: 6b9a ldr r2, [r3, #56] @ 0x38
8012f5e: 6b3b ldr r3, [r7, #48] @ 0x30
8012f60: 6bdb ldr r3, [r3, #60] @ 0x3c
8012f62: 429a cmp r2, r3
8012f64: d302 bcc.n 8012f6c <xQueueGenericSend+0xdc>
8012f66: 683b ldr r3, [r7, #0]
8012f68: 2b02 cmp r3, #2
8012f6a: d129 bne.n 8012fc0 <xQueueGenericSend+0x130>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
8012f6c: 683a ldr r2, [r7, #0]
8012f6e: 68b9 ldr r1, [r7, #8]
8012f70: 6b38 ldr r0, [r7, #48] @ 0x30
8012f72: f000 fca5 bl 80138c0 <prvCopyDataToQueue>
8012f76: 62f8 str r0, [r7, #44] @ 0x2c
/* If there was a task waiting for data to arrive on the
* queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
8012f78: 6b3b ldr r3, [r7, #48] @ 0x30
8012f7a: 6a5b ldr r3, [r3, #36] @ 0x24
8012f7c: 2b00 cmp r3, #0
8012f7e: d010 beq.n 8012fa2 <xQueueGenericSend+0x112>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8012f80: 6b3b ldr r3, [r7, #48] @ 0x30
8012f82: 3324 adds r3, #36 @ 0x24
8012f84: 4618 mov r0, r3
8012f86: f001 fbed bl 8014764 <xTaskRemoveFromEventList>
8012f8a: 4603 mov r3, r0
8012f8c: 2b00 cmp r3, #0
8012f8e: d013 beq.n 8012fb8 <xQueueGenericSend+0x128>
{
/* The unblocked task has a priority higher than
* our own so yield immediately. Yes it is ok to do
* this from within the critical section - the kernel
* takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
8012f90: 4b3f ldr r3, [pc, #252] @ (8013090 <xQueueGenericSend+0x200>)
8012f92: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8012f96: 601a str r2, [r3, #0]
8012f98: f3bf 8f4f dsb sy
8012f9c: f3bf 8f6f isb sy
8012fa0: e00a b.n 8012fb8 <xQueueGenericSend+0x128>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
8012fa2: 6afb ldr r3, [r7, #44] @ 0x2c
8012fa4: 2b00 cmp r3, #0
8012fa6: d007 beq.n 8012fb8 <xQueueGenericSend+0x128>
{
/* This path is a special case that will only get
* executed if the task was holding multiple mutexes and
* the mutexes were given back in an order that is
* different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
8012fa8: 4b39 ldr r3, [pc, #228] @ (8013090 <xQueueGenericSend+0x200>)
8012faa: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8012fae: 601a str r2, [r3, #0]
8012fb0: f3bf 8f4f dsb sy
8012fb4: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
8012fb8: f003 f964 bl 8016284 <vPortExitCritical>
return pdPASS;
8012fbc: 2301 movs r3, #1
8012fbe: e063 b.n 8013088 <xQueueGenericSend+0x1f8>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
8012fc0: 687b ldr r3, [r7, #4]
8012fc2: 2b00 cmp r3, #0
8012fc4: d103 bne.n 8012fce <xQueueGenericSend+0x13e>
{
/* The queue was full and no block time is specified (or
* the block time has expired) so leave now. */
taskEXIT_CRITICAL();
8012fc6: f003 f95d bl 8016284 <vPortExitCritical>
/* Return to the original privilege level before exiting
* the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
8012fca: 2300 movs r3, #0
8012fcc: e05c b.n 8013088 <xQueueGenericSend+0x1f8>
}
else if( xEntryTimeSet == pdFALSE )
8012fce: 6b7b ldr r3, [r7, #52] @ 0x34
8012fd0: 2b00 cmp r3, #0
8012fd2: d106 bne.n 8012fe2 <xQueueGenericSend+0x152>
{
/* The queue was full and a block time was specified so
* configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
8012fd4: f107 0314 add.w r3, r7, #20
8012fd8: 4618 mov r0, r3
8012fda: f001 fc9b bl 8014914 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
8012fde: 2301 movs r3, #1
8012fe0: 637b str r3, [r7, #52] @ 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
8012fe2: f003 f94f bl 8016284 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
* now the critical section has been exited. */
vTaskSuspendAll();
8012fe6: f001 f8b3 bl 8014150 <vTaskSuspendAll>
prvLockQueue( pxQueue );
8012fea: f003 f919 bl 8016220 <vPortEnterCritical>
8012fee: 6b3b ldr r3, [r7, #48] @ 0x30
8012ff0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8012ff4: b25b sxtb r3, r3
8012ff6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8012ffa: d103 bne.n 8013004 <xQueueGenericSend+0x174>
8012ffc: 6b3b ldr r3, [r7, #48] @ 0x30
8012ffe: 2200 movs r2, #0
8013000: f883 2044 strb.w r2, [r3, #68] @ 0x44
8013004: 6b3b ldr r3, [r7, #48] @ 0x30
8013006: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
801300a: b25b sxtb r3, r3
801300c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8013010: d103 bne.n 801301a <xQueueGenericSend+0x18a>
8013012: 6b3b ldr r3, [r7, #48] @ 0x30
8013014: 2200 movs r2, #0
8013016: f883 2045 strb.w r2, [r3, #69] @ 0x45
801301a: f003 f933 bl 8016284 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
801301e: 1d3a adds r2, r7, #4
8013020: f107 0314 add.w r3, r7, #20
8013024: 4611 mov r1, r2
8013026: 4618 mov r0, r3
8013028: f001 fc8a bl 8014940 <xTaskCheckForTimeOut>
801302c: 4603 mov r3, r0
801302e: 2b00 cmp r3, #0
8013030: d124 bne.n 801307c <xQueueGenericSend+0x1ec>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
8013032: 6b38 ldr r0, [r7, #48] @ 0x30
8013034: f000 fd3c bl 8013ab0 <prvIsQueueFull>
8013038: 4603 mov r3, r0
801303a: 2b00 cmp r3, #0
801303c: d018 beq.n 8013070 <xQueueGenericSend+0x1e0>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
801303e: 6b3b ldr r3, [r7, #48] @ 0x30
8013040: 3310 adds r3, #16
8013042: 687a ldr r2, [r7, #4]
8013044: 4611 mov r1, r2
8013046: 4618 mov r0, r3
8013048: f001 fb20 bl 801468c <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
* event list. It is possible that interrupts occurring now
* remove this task from the event list again - but as the
* scheduler is suspended the task will go onto the pending
* ready list instead of the actual ready list. */
prvUnlockQueue( pxQueue );
801304c: 6b38 ldr r0, [r7, #48] @ 0x30
801304e: f000 fcc7 bl 80139e0 <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
* ready list into the ready list - so it is feasible that this
* task is already in the ready list before it yields - in which
* case the yield will not cause a context switch unless there
* is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
8013052: f001 f88b bl 801416c <xTaskResumeAll>
8013056: 4603 mov r3, r0
8013058: 2b00 cmp r3, #0
801305a: f47f af7c bne.w 8012f56 <xQueueGenericSend+0xc6>
{
portYIELD_WITHIN_API();
801305e: 4b0c ldr r3, [pc, #48] @ (8013090 <xQueueGenericSend+0x200>)
8013060: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8013064: 601a str r2, [r3, #0]
8013066: f3bf 8f4f dsb sy
801306a: f3bf 8f6f isb sy
801306e: e772 b.n 8012f56 <xQueueGenericSend+0xc6>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
8013070: 6b38 ldr r0, [r7, #48] @ 0x30
8013072: f000 fcb5 bl 80139e0 <prvUnlockQueue>
( void ) xTaskResumeAll();
8013076: f001 f879 bl 801416c <xTaskResumeAll>
801307a: e76c b.n 8012f56 <xQueueGenericSend+0xc6>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
801307c: 6b38 ldr r0, [r7, #48] @ 0x30
801307e: f000 fcaf bl 80139e0 <prvUnlockQueue>
( void ) xTaskResumeAll();
8013082: f001 f873 bl 801416c <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
8013086: 2300 movs r3, #0
}
} /*lint -restore */
}
8013088: 4618 mov r0, r3
801308a: 3738 adds r7, #56 @ 0x38
801308c: 46bd mov sp, r7
801308e: bd80 pop {r7, pc}
8013090: e000ed04 .word 0xe000ed04
08013094 <xQueueGenericSendFromISR>:
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
const void * const pvItemToQueue,
BaseType_t * const pxHigherPriorityTaskWoken,
const BaseType_t xCopyPosition )
{
8013094: b580 push {r7, lr}
8013096: b092 sub sp, #72 @ 0x48
8013098: af00 add r7, sp, #0
801309a: 60f8 str r0, [r7, #12]
801309c: 60b9 str r1, [r7, #8]
801309e: 607a str r2, [r7, #4]
80130a0: 603b str r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
80130a2: 68fb ldr r3, [r7, #12]
80130a4: 643b str r3, [r7, #64] @ 0x40
configASSERT( pxQueue );
80130a6: 6c3b ldr r3, [r7, #64] @ 0x40
80130a8: 2b00 cmp r3, #0
80130aa: d10b bne.n 80130c4 <xQueueGenericSendFromISR+0x30>
__asm volatile
80130ac: f04f 0350 mov.w r3, #80 @ 0x50
80130b0: f383 8811 msr BASEPRI, r3
80130b4: f3bf 8f6f isb sy
80130b8: f3bf 8f4f dsb sy
80130bc: 62fb str r3, [r7, #44] @ 0x2c
}
80130be: bf00 nop
80130c0: bf00 nop
80130c2: e7fd b.n 80130c0 <xQueueGenericSendFromISR+0x2c>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
80130c4: 68bb ldr r3, [r7, #8]
80130c6: 2b00 cmp r3, #0
80130c8: d103 bne.n 80130d2 <xQueueGenericSendFromISR+0x3e>
80130ca: 6c3b ldr r3, [r7, #64] @ 0x40
80130cc: 6c1b ldr r3, [r3, #64] @ 0x40
80130ce: 2b00 cmp r3, #0
80130d0: d101 bne.n 80130d6 <xQueueGenericSendFromISR+0x42>
80130d2: 2301 movs r3, #1
80130d4: e000 b.n 80130d8 <xQueueGenericSendFromISR+0x44>
80130d6: 2300 movs r3, #0
80130d8: 2b00 cmp r3, #0
80130da: d10b bne.n 80130f4 <xQueueGenericSendFromISR+0x60>
__asm volatile
80130dc: f04f 0350 mov.w r3, #80 @ 0x50
80130e0: f383 8811 msr BASEPRI, r3
80130e4: f3bf 8f6f isb sy
80130e8: f3bf 8f4f dsb sy
80130ec: 62bb str r3, [r7, #40] @ 0x28
}
80130ee: bf00 nop
80130f0: bf00 nop
80130f2: e7fd b.n 80130f0 <xQueueGenericSendFromISR+0x5c>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
80130f4: 683b ldr r3, [r7, #0]
80130f6: 2b02 cmp r3, #2
80130f8: d103 bne.n 8013102 <xQueueGenericSendFromISR+0x6e>
80130fa: 6c3b ldr r3, [r7, #64] @ 0x40
80130fc: 6bdb ldr r3, [r3, #60] @ 0x3c
80130fe: 2b01 cmp r3, #1
8013100: d101 bne.n 8013106 <xQueueGenericSendFromISR+0x72>
8013102: 2301 movs r3, #1
8013104: e000 b.n 8013108 <xQueueGenericSendFromISR+0x74>
8013106: 2300 movs r3, #0
8013108: 2b00 cmp r3, #0
801310a: d10b bne.n 8013124 <xQueueGenericSendFromISR+0x90>
__asm volatile
801310c: f04f 0350 mov.w r3, #80 @ 0x50
8013110: f383 8811 msr BASEPRI, r3
8013114: f3bf 8f6f isb sy
8013118: f3bf 8f4f dsb sy
801311c: 627b str r3, [r7, #36] @ 0x24
}
801311e: bf00 nop
8013120: bf00 nop
8013122: e7fd b.n 8013120 <xQueueGenericSendFromISR+0x8c>
* that have been assigned a priority at or (logically) below the maximum
* system call interrupt priority. FreeRTOS maintains a separate interrupt
* safe API to ensure interrupt entry is as fast and as simple as possible.
* More information (albeit Cortex-M specific) is provided on the following
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
8013124: f003 f962 bl 80163ec <vPortValidateInterruptPriority>
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
8013128: f3ef 8211 mrs r2, BASEPRI
801312c: f04f 0350 mov.w r3, #80 @ 0x50
8013130: f383 8811 msr BASEPRI, r3
8013134: f3bf 8f6f isb sy
8013138: f3bf 8f4f dsb sy
801313c: 623a str r2, [r7, #32]
801313e: 61fb str r3, [r7, #28]
: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
* warnings. */
return ulOriginalBASEPRI;
8013140: 6a3b ldr r3, [r7, #32]
/* Similar to xQueueGenericSend, except without blocking if there is no room
* in the queue. Also don't directly wake a task that was blocked on a queue
* read, instead return a flag to say whether a context switch is required or
* not (i.e. has a task with a higher priority than us been woken by this
* post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
8013142: 63fb str r3, [r7, #60] @ 0x3c
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
8013144: 6c3b ldr r3, [r7, #64] @ 0x40
8013146: 6b9a ldr r2, [r3, #56] @ 0x38
8013148: 6c3b ldr r3, [r7, #64] @ 0x40
801314a: 6bdb ldr r3, [r3, #60] @ 0x3c
801314c: 429a cmp r2, r3
801314e: d302 bcc.n 8013156 <xQueueGenericSendFromISR+0xc2>
8013150: 683b ldr r3, [r7, #0]
8013152: 2b02 cmp r3, #2
8013154: d147 bne.n 80131e6 <xQueueGenericSendFromISR+0x152>
{
const int8_t cTxLock = pxQueue->cTxLock;
8013156: 6c3b ldr r3, [r7, #64] @ 0x40
8013158: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
801315c: f887 303b strb.w r3, [r7, #59] @ 0x3b
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
8013160: 6c3b ldr r3, [r7, #64] @ 0x40
8013162: 6b9b ldr r3, [r3, #56] @ 0x38
8013164: 637b str r3, [r7, #52] @ 0x34
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
* semaphore or mutex. That means prvCopyDataToQueue() cannot result
* in a task disinheriting a priority and prvCopyDataToQueue() can be
* called here even though the disinherit function does not check if
* the scheduler is suspended before accessing the ready lists. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
8013166: 683a ldr r2, [r7, #0]
8013168: 68b9 ldr r1, [r7, #8]
801316a: 6c38 ldr r0, [r7, #64] @ 0x40
801316c: f000 fba8 bl 80138c0 <prvCopyDataToQueue>
/* The event list is not altered if the queue is locked. This will
* be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
8013170: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b
8013174: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8013178: d112 bne.n 80131a0 <xQueueGenericSendFromISR+0x10c>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
801317a: 6c3b ldr r3, [r7, #64] @ 0x40
801317c: 6a5b ldr r3, [r3, #36] @ 0x24
801317e: 2b00 cmp r3, #0
8013180: d02e beq.n 80131e0 <xQueueGenericSendFromISR+0x14c>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8013182: 6c3b ldr r3, [r7, #64] @ 0x40
8013184: 3324 adds r3, #36 @ 0x24
8013186: 4618 mov r0, r3
8013188: f001 faec bl 8014764 <xTaskRemoveFromEventList>
801318c: 4603 mov r3, r0
801318e: 2b00 cmp r3, #0
8013190: d026 beq.n 80131e0 <xQueueGenericSendFromISR+0x14c>
{
/* The task waiting has a higher priority so record that a
* context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
8013192: 687b ldr r3, [r7, #4]
8013194: 2b00 cmp r3, #0
8013196: d023 beq.n 80131e0 <xQueueGenericSendFromISR+0x14c>
{
*pxHigherPriorityTaskWoken = pdTRUE;
8013198: 687b ldr r3, [r7, #4]
801319a: 2201 movs r2, #1
801319c: 601a str r2, [r3, #0]
801319e: e01f b.n 80131e0 <xQueueGenericSendFromISR+0x14c>
}
else
{
/* Increment the lock count so the task that unlocks the queue
* knows that data was posted while it was locked. */
prvIncrementQueueTxLock( pxQueue, cTxLock );
80131a0: f001 f8f2 bl 8014388 <uxTaskGetNumberOfTasks>
80131a4: 6338 str r0, [r7, #48] @ 0x30
80131a6: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b
80131aa: 6b3a ldr r2, [r7, #48] @ 0x30
80131ac: 429a cmp r2, r3
80131ae: d917 bls.n 80131e0 <xQueueGenericSendFromISR+0x14c>
80131b0: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b
80131b4: 2b7f cmp r3, #127 @ 0x7f
80131b6: d10b bne.n 80131d0 <xQueueGenericSendFromISR+0x13c>
__asm volatile
80131b8: f04f 0350 mov.w r3, #80 @ 0x50
80131bc: f383 8811 msr BASEPRI, r3
80131c0: f3bf 8f6f isb sy
80131c4: f3bf 8f4f dsb sy
80131c8: 61bb str r3, [r7, #24]
}
80131ca: bf00 nop
80131cc: bf00 nop
80131ce: e7fd b.n 80131cc <xQueueGenericSendFromISR+0x138>
80131d0: f897 303b ldrb.w r3, [r7, #59] @ 0x3b
80131d4: 3301 adds r3, #1
80131d6: b2db uxtb r3, r3
80131d8: b25a sxtb r2, r3
80131da: 6c3b ldr r3, [r7, #64] @ 0x40
80131dc: f883 2045 strb.w r2, [r3, #69] @ 0x45
}
xReturn = pdPASS;
80131e0: 2301 movs r3, #1
80131e2: 647b str r3, [r7, #68] @ 0x44
{
80131e4: e001 b.n 80131ea <xQueueGenericSendFromISR+0x156>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
80131e6: 2300 movs r3, #0
80131e8: 647b str r3, [r7, #68] @ 0x44
80131ea: 6bfb ldr r3, [r7, #60] @ 0x3c
80131ec: 617b str r3, [r7, #20]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
80131ee: 697b ldr r3, [r7, #20]
80131f0: f383 8811 msr BASEPRI, r3
(
" msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
);
}
80131f4: bf00 nop
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
80131f6: 6c7b ldr r3, [r7, #68] @ 0x44
}
80131f8: 4618 mov r0, r3
80131fa: 3748 adds r7, #72 @ 0x48
80131fc: 46bd mov sp, r7
80131fe: bd80 pop {r7, pc}
08013200 <xQueueGiveFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
BaseType_t * const pxHigherPriorityTaskWoken )
{
8013200: b580 push {r7, lr}
8013202: b090 sub sp, #64 @ 0x40
8013204: af00 add r7, sp, #0
8013206: 6078 str r0, [r7, #4]
8013208: 6039 str r1, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
801320a: 687b ldr r3, [r7, #4]
801320c: 63bb str r3, [r7, #56] @ 0x38
* item size is 0. Don't directly wake a task that was blocked on a queue
* read, instead return a flag to say whether a context switch is required or
* not (i.e. has a task with a higher priority than us been woken by this
* post). */
configASSERT( pxQueue );
801320e: 6bbb ldr r3, [r7, #56] @ 0x38
8013210: 2b00 cmp r3, #0
8013212: d10b bne.n 801322c <xQueueGiveFromISR+0x2c>
__asm volatile
8013214: f04f 0350 mov.w r3, #80 @ 0x50
8013218: f383 8811 msr BASEPRI, r3
801321c: f3bf 8f6f isb sy
8013220: f3bf 8f4f dsb sy
8013224: 627b str r3, [r7, #36] @ 0x24
}
8013226: bf00 nop
8013228: bf00 nop
801322a: e7fd b.n 8013228 <xQueueGiveFromISR+0x28>
/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
* if the item size is not 0. */
configASSERT( pxQueue->uxItemSize == 0 );
801322c: 6bbb ldr r3, [r7, #56] @ 0x38
801322e: 6c1b ldr r3, [r3, #64] @ 0x40
8013230: 2b00 cmp r3, #0
8013232: d00b beq.n 801324c <xQueueGiveFromISR+0x4c>
__asm volatile
8013234: f04f 0350 mov.w r3, #80 @ 0x50
8013238: f383 8811 msr BASEPRI, r3
801323c: f3bf 8f6f isb sy
8013240: f3bf 8f4f dsb sy
8013244: 623b str r3, [r7, #32]
}
8013246: bf00 nop
8013248: bf00 nop
801324a: e7fd b.n 8013248 <xQueueGiveFromISR+0x48>
/* Normally a mutex would not be given from an interrupt, especially if
* there is a mutex holder, as priority inheritance makes no sense for an
* interrupts, only tasks. */
configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
801324c: 6bbb ldr r3, [r7, #56] @ 0x38
801324e: 681b ldr r3, [r3, #0]
8013250: 2b00 cmp r3, #0
8013252: d103 bne.n 801325c <xQueueGiveFromISR+0x5c>
8013254: 6bbb ldr r3, [r7, #56] @ 0x38
8013256: 689b ldr r3, [r3, #8]
8013258: 2b00 cmp r3, #0
801325a: d101 bne.n 8013260 <xQueueGiveFromISR+0x60>
801325c: 2301 movs r3, #1
801325e: e000 b.n 8013262 <xQueueGiveFromISR+0x62>
8013260: 2300 movs r3, #0
8013262: 2b00 cmp r3, #0
8013264: d10b bne.n 801327e <xQueueGiveFromISR+0x7e>
__asm volatile
8013266: f04f 0350 mov.w r3, #80 @ 0x50
801326a: f383 8811 msr BASEPRI, r3
801326e: f3bf 8f6f isb sy
8013272: f3bf 8f4f dsb sy
8013276: 61fb str r3, [r7, #28]
}
8013278: bf00 nop
801327a: bf00 nop
801327c: e7fd b.n 801327a <xQueueGiveFromISR+0x7a>
* that have been assigned a priority at or (logically) below the maximum
* system call interrupt priority. FreeRTOS maintains a separate interrupt
* safe API to ensure interrupt entry is as fast and as simple as possible.
* More information (albeit Cortex-M specific) is provided on the following
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
801327e: f003 f8b5 bl 80163ec <vPortValidateInterruptPriority>
__asm volatile
8013282: f3ef 8211 mrs r2, BASEPRI
8013286: f04f 0350 mov.w r3, #80 @ 0x50
801328a: f383 8811 msr BASEPRI, r3
801328e: f3bf 8f6f isb sy
8013292: f3bf 8f4f dsb sy
8013296: 61ba str r2, [r7, #24]
8013298: 617b str r3, [r7, #20]
return ulOriginalBASEPRI;
801329a: 69bb ldr r3, [r7, #24]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
801329c: 637b str r3, [r7, #52] @ 0x34
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
801329e: 6bbb ldr r3, [r7, #56] @ 0x38
80132a0: 6b9b ldr r3, [r3, #56] @ 0x38
80132a2: 633b str r3, [r7, #48] @ 0x30
/* When the queue is used to implement a semaphore no data is ever
* moved through the queue but it is still valid to see if the queue 'has
* space'. */
if( uxMessagesWaiting < pxQueue->uxLength )
80132a4: 6bbb ldr r3, [r7, #56] @ 0x38
80132a6: 6bdb ldr r3, [r3, #60] @ 0x3c
80132a8: 6b3a ldr r2, [r7, #48] @ 0x30
80132aa: 429a cmp r2, r3
80132ac: d243 bcs.n 8013336 <xQueueGiveFromISR+0x136>
{
const int8_t cTxLock = pxQueue->cTxLock;
80132ae: 6bbb ldr r3, [r7, #56] @ 0x38
80132b0: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80132b4: f887 302f strb.w r3, [r7, #47] @ 0x2f
* holder - and if there is a mutex holder then the mutex cannot be
* given from an ISR. As this is the ISR version of the function it
* can be assumed there is no mutex holder and no need to determine if
* priority disinheritance is needed. Simply increase the count of
* messages (semaphores) available. */
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
80132b8: 6b3b ldr r3, [r7, #48] @ 0x30
80132ba: 1c5a adds r2, r3, #1
80132bc: 6bbb ldr r3, [r7, #56] @ 0x38
80132be: 639a str r2, [r3, #56] @ 0x38
/* The event list is not altered if the queue is locked. This will
* be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
80132c0: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
80132c4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80132c8: d112 bne.n 80132f0 <xQueueGiveFromISR+0xf0>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
80132ca: 6bbb ldr r3, [r7, #56] @ 0x38
80132cc: 6a5b ldr r3, [r3, #36] @ 0x24
80132ce: 2b00 cmp r3, #0
80132d0: d02e beq.n 8013330 <xQueueGiveFromISR+0x130>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
80132d2: 6bbb ldr r3, [r7, #56] @ 0x38
80132d4: 3324 adds r3, #36 @ 0x24
80132d6: 4618 mov r0, r3
80132d8: f001 fa44 bl 8014764 <xTaskRemoveFromEventList>
80132dc: 4603 mov r3, r0
80132de: 2b00 cmp r3, #0
80132e0: d026 beq.n 8013330 <xQueueGiveFromISR+0x130>
{
/* The task waiting has a higher priority so record that a
* context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
80132e2: 683b ldr r3, [r7, #0]
80132e4: 2b00 cmp r3, #0
80132e6: d023 beq.n 8013330 <xQueueGiveFromISR+0x130>
{
*pxHigherPriorityTaskWoken = pdTRUE;
80132e8: 683b ldr r3, [r7, #0]
80132ea: 2201 movs r2, #1
80132ec: 601a str r2, [r3, #0]
80132ee: e01f b.n 8013330 <xQueueGiveFromISR+0x130>
}
else
{
/* Increment the lock count so the task that unlocks the queue
* knows that data was posted while it was locked. */
prvIncrementQueueTxLock( pxQueue, cTxLock );
80132f0: f001 f84a bl 8014388 <uxTaskGetNumberOfTasks>
80132f4: 62b8 str r0, [r7, #40] @ 0x28
80132f6: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
80132fa: 6aba ldr r2, [r7, #40] @ 0x28
80132fc: 429a cmp r2, r3
80132fe: d917 bls.n 8013330 <xQueueGiveFromISR+0x130>
8013300: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
8013304: 2b7f cmp r3, #127 @ 0x7f
8013306: d10b bne.n 8013320 <xQueueGiveFromISR+0x120>
__asm volatile
8013308: f04f 0350 mov.w r3, #80 @ 0x50
801330c: f383 8811 msr BASEPRI, r3
8013310: f3bf 8f6f isb sy
8013314: f3bf 8f4f dsb sy
8013318: 613b str r3, [r7, #16]
}
801331a: bf00 nop
801331c: bf00 nop
801331e: e7fd b.n 801331c <xQueueGiveFromISR+0x11c>
8013320: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
8013324: 3301 adds r3, #1
8013326: b2db uxtb r3, r3
8013328: b25a sxtb r2, r3
801332a: 6bbb ldr r3, [r7, #56] @ 0x38
801332c: f883 2045 strb.w r2, [r3, #69] @ 0x45
}
xReturn = pdPASS;
8013330: 2301 movs r3, #1
8013332: 63fb str r3, [r7, #60] @ 0x3c
8013334: e001 b.n 801333a <xQueueGiveFromISR+0x13a>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
8013336: 2300 movs r3, #0
8013338: 63fb str r3, [r7, #60] @ 0x3c
801333a: 6b7b ldr r3, [r7, #52] @ 0x34
801333c: 60fb str r3, [r7, #12]
__asm volatile
801333e: 68fb ldr r3, [r7, #12]
8013340: f383 8811 msr BASEPRI, r3
}
8013344: bf00 nop
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
8013346: 6bfb ldr r3, [r7, #60] @ 0x3c
}
8013348: 4618 mov r0, r3
801334a: 3740 adds r7, #64 @ 0x40
801334c: 46bd mov sp, r7
801334e: bd80 pop {r7, pc}
08013350 <xQueueReceive>:
/*-----------------------------------------------------------*/
BaseType_t xQueueReceive( QueueHandle_t xQueue,
void * const pvBuffer,
TickType_t xTicksToWait )
{
8013350: b580 push {r7, lr}
8013352: b08c sub sp, #48 @ 0x30
8013354: af00 add r7, sp, #0
8013356: 60f8 str r0, [r7, #12]
8013358: 60b9 str r1, [r7, #8]
801335a: 607a str r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
801335c: 2300 movs r3, #0
801335e: 62fb str r3, [r7, #44] @ 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8013360: 68fb ldr r3, [r7, #12]
8013362: 62bb str r3, [r7, #40] @ 0x28
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
8013364: 6abb ldr r3, [r7, #40] @ 0x28
8013366: 2b00 cmp r3, #0
8013368: d10b bne.n 8013382 <xQueueReceive+0x32>
__asm volatile
801336a: f04f 0350 mov.w r3, #80 @ 0x50
801336e: f383 8811 msr BASEPRI, r3
8013372: f3bf 8f6f isb sy
8013376: f3bf 8f4f dsb sy
801337a: 623b str r3, [r7, #32]
}
801337c: bf00 nop
801337e: bf00 nop
8013380: e7fd b.n 801337e <xQueueReceive+0x2e>
/* The buffer into which data is received can only be NULL if the data size
* is zero (so no data is copied into the buffer). */
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
8013382: 68bb ldr r3, [r7, #8]
8013384: 2b00 cmp r3, #0
8013386: d103 bne.n 8013390 <xQueueReceive+0x40>
8013388: 6abb ldr r3, [r7, #40] @ 0x28
801338a: 6c1b ldr r3, [r3, #64] @ 0x40
801338c: 2b00 cmp r3, #0
801338e: d101 bne.n 8013394 <xQueueReceive+0x44>
8013390: 2301 movs r3, #1
8013392: e000 b.n 8013396 <xQueueReceive+0x46>
8013394: 2300 movs r3, #0
8013396: 2b00 cmp r3, #0
8013398: d10b bne.n 80133b2 <xQueueReceive+0x62>
__asm volatile
801339a: f04f 0350 mov.w r3, #80 @ 0x50
801339e: f383 8811 msr BASEPRI, r3
80133a2: f3bf 8f6f isb sy
80133a6: f3bf 8f4f dsb sy
80133aa: 61fb str r3, [r7, #28]
}
80133ac: bf00 nop
80133ae: bf00 nop
80133b0: e7fd b.n 80133ae <xQueueReceive+0x5e>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
80133b2: f001 fc1b bl 8014bec <xTaskGetSchedulerState>
80133b6: 4603 mov r3, r0
80133b8: 2b00 cmp r3, #0
80133ba: d102 bne.n 80133c2 <xQueueReceive+0x72>
80133bc: 687b ldr r3, [r7, #4]
80133be: 2b00 cmp r3, #0
80133c0: d101 bne.n 80133c6 <xQueueReceive+0x76>
80133c2: 2301 movs r3, #1
80133c4: e000 b.n 80133c8 <xQueueReceive+0x78>
80133c6: 2300 movs r3, #0
80133c8: 2b00 cmp r3, #0
80133ca: d10b bne.n 80133e4 <xQueueReceive+0x94>
__asm volatile
80133cc: f04f 0350 mov.w r3, #80 @ 0x50
80133d0: f383 8811 msr BASEPRI, r3
80133d4: f3bf 8f6f isb sy
80133d8: f3bf 8f4f dsb sy
80133dc: 61bb str r3, [r7, #24]
}
80133de: bf00 nop
80133e0: bf00 nop
80133e2: e7fd b.n 80133e0 <xQueueReceive+0x90>
/*lint -save -e904 This function relaxes the coding standard somewhat to
* allow return statements within the function itself. This is done in the
* interest of execution time efficiency. */
for( ; ; )
{
taskENTER_CRITICAL();
80133e4: f002 ff1c bl 8016220 <vPortEnterCritical>
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
80133e8: 6abb ldr r3, [r7, #40] @ 0x28
80133ea: 6b9b ldr r3, [r3, #56] @ 0x38
80133ec: 627b str r3, [r7, #36] @ 0x24
/* Is there data in the queue now? To be running the calling task
* must be the highest priority task wanting to access the queue. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
80133ee: 6a7b ldr r3, [r7, #36] @ 0x24
80133f0: 2b00 cmp r3, #0
80133f2: d01f beq.n 8013434 <xQueueReceive+0xe4>
{
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
80133f4: 68b9 ldr r1, [r7, #8]
80133f6: 6ab8 ldr r0, [r7, #40] @ 0x28
80133f8: f000 facc bl 8013994 <prvCopyDataFromQueue>
traceQUEUE_RECEIVE( pxQueue );
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
80133fc: 6a7b ldr r3, [r7, #36] @ 0x24
80133fe: 1e5a subs r2, r3, #1
8013400: 6abb ldr r3, [r7, #40] @ 0x28
8013402: 639a str r2, [r3, #56] @ 0x38
/* There is now space in the queue, were any tasks waiting to
* post to the queue? If so, unblock the highest priority waiting
* task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8013404: 6abb ldr r3, [r7, #40] @ 0x28
8013406: 691b ldr r3, [r3, #16]
8013408: 2b00 cmp r3, #0
801340a: d00f beq.n 801342c <xQueueReceive+0xdc>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
801340c: 6abb ldr r3, [r7, #40] @ 0x28
801340e: 3310 adds r3, #16
8013410: 4618 mov r0, r3
8013412: f001 f9a7 bl 8014764 <xTaskRemoveFromEventList>
8013416: 4603 mov r3, r0
8013418: 2b00 cmp r3, #0
801341a: d007 beq.n 801342c <xQueueReceive+0xdc>
{
queueYIELD_IF_USING_PREEMPTION();
801341c: 4b3c ldr r3, [pc, #240] @ (8013510 <xQueueReceive+0x1c0>)
801341e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8013422: 601a str r2, [r3, #0]
8013424: f3bf 8f4f dsb sy
8013428: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
801342c: f002 ff2a bl 8016284 <vPortExitCritical>
return pdPASS;
8013430: 2301 movs r3, #1
8013432: e069 b.n 8013508 <xQueueReceive+0x1b8>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
8013434: 687b ldr r3, [r7, #4]
8013436: 2b00 cmp r3, #0
8013438: d103 bne.n 8013442 <xQueueReceive+0xf2>
{
/* The queue was empty and no block time is specified (or
* the block time has expired) so leave now. */
taskEXIT_CRITICAL();
801343a: f002 ff23 bl 8016284 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
801343e: 2300 movs r3, #0
8013440: e062 b.n 8013508 <xQueueReceive+0x1b8>
}
else if( xEntryTimeSet == pdFALSE )
8013442: 6afb ldr r3, [r7, #44] @ 0x2c
8013444: 2b00 cmp r3, #0
8013446: d106 bne.n 8013456 <xQueueReceive+0x106>
{
/* The queue was empty and a block time was specified so
* configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
8013448: f107 0310 add.w r3, r7, #16
801344c: 4618 mov r0, r3
801344e: f001 fa61 bl 8014914 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
8013452: 2301 movs r3, #1
8013454: 62fb str r3, [r7, #44] @ 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
8013456: f002 ff15 bl 8016284 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
* now the critical section has been exited. */
vTaskSuspendAll();
801345a: f000 fe79 bl 8014150 <vTaskSuspendAll>
prvLockQueue( pxQueue );
801345e: f002 fedf bl 8016220 <vPortEnterCritical>
8013462: 6abb ldr r3, [r7, #40] @ 0x28
8013464: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8013468: b25b sxtb r3, r3
801346a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
801346e: d103 bne.n 8013478 <xQueueReceive+0x128>
8013470: 6abb ldr r3, [r7, #40] @ 0x28
8013472: 2200 movs r2, #0
8013474: f883 2044 strb.w r2, [r3, #68] @ 0x44
8013478: 6abb ldr r3, [r7, #40] @ 0x28
801347a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
801347e: b25b sxtb r3, r3
8013480: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8013484: d103 bne.n 801348e <xQueueReceive+0x13e>
8013486: 6abb ldr r3, [r7, #40] @ 0x28
8013488: 2200 movs r2, #0
801348a: f883 2045 strb.w r2, [r3, #69] @ 0x45
801348e: f002 fef9 bl 8016284 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
8013492: 1d3a adds r2, r7, #4
8013494: f107 0310 add.w r3, r7, #16
8013498: 4611 mov r1, r2
801349a: 4618 mov r0, r3
801349c: f001 fa50 bl 8014940 <xTaskCheckForTimeOut>
80134a0: 4603 mov r3, r0
80134a2: 2b00 cmp r3, #0
80134a4: d123 bne.n 80134ee <xQueueReceive+0x19e>
{
/* The timeout has not expired. If the queue is still empty place
* the task on the list of tasks waiting to receive from the queue. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
80134a6: 6ab8 ldr r0, [r7, #40] @ 0x28
80134a8: f000 faec bl 8013a84 <prvIsQueueEmpty>
80134ac: 4603 mov r3, r0
80134ae: 2b00 cmp r3, #0
80134b0: d017 beq.n 80134e2 <xQueueReceive+0x192>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
80134b2: 6abb ldr r3, [r7, #40] @ 0x28
80134b4: 3324 adds r3, #36 @ 0x24
80134b6: 687a ldr r2, [r7, #4]
80134b8: 4611 mov r1, r2
80134ba: 4618 mov r0, r3
80134bc: f001 f8e6 bl 801468c <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
80134c0: 6ab8 ldr r0, [r7, #40] @ 0x28
80134c2: f000 fa8d bl 80139e0 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
80134c6: f000 fe51 bl 801416c <xTaskResumeAll>
80134ca: 4603 mov r3, r0
80134cc: 2b00 cmp r3, #0
80134ce: d189 bne.n 80133e4 <xQueueReceive+0x94>
{
portYIELD_WITHIN_API();
80134d0: 4b0f ldr r3, [pc, #60] @ (8013510 <xQueueReceive+0x1c0>)
80134d2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80134d6: 601a str r2, [r3, #0]
80134d8: f3bf 8f4f dsb sy
80134dc: f3bf 8f6f isb sy
80134e0: e780 b.n 80133e4 <xQueueReceive+0x94>
}
else
{
/* The queue contains data again. Loop back to try and read the
* data. */
prvUnlockQueue( pxQueue );
80134e2: 6ab8 ldr r0, [r7, #40] @ 0x28
80134e4: f000 fa7c bl 80139e0 <prvUnlockQueue>
( void ) xTaskResumeAll();
80134e8: f000 fe40 bl 801416c <xTaskResumeAll>
80134ec: e77a b.n 80133e4 <xQueueReceive+0x94>
}
else
{
/* Timed out. If there is no data in the queue exit, otherwise loop
* back and attempt to read the data. */
prvUnlockQueue( pxQueue );
80134ee: 6ab8 ldr r0, [r7, #40] @ 0x28
80134f0: f000 fa76 bl 80139e0 <prvUnlockQueue>
( void ) xTaskResumeAll();
80134f4: f000 fe3a bl 801416c <xTaskResumeAll>
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
80134f8: 6ab8 ldr r0, [r7, #40] @ 0x28
80134fa: f000 fac3 bl 8013a84 <prvIsQueueEmpty>
80134fe: 4603 mov r3, r0
8013500: 2b00 cmp r3, #0
8013502: f43f af6f beq.w 80133e4 <xQueueReceive+0x94>
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
8013506: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
8013508: 4618 mov r0, r3
801350a: 3730 adds r7, #48 @ 0x30
801350c: 46bd mov sp, r7
801350e: bd80 pop {r7, pc}
8013510: e000ed04 .word 0xe000ed04
08013514 <xQueueSemaphoreTake>:
/*-----------------------------------------------------------*/
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
TickType_t xTicksToWait )
{
8013514: b580 push {r7, lr}
8013516: b08c sub sp, #48 @ 0x30
8013518: af00 add r7, sp, #0
801351a: 6078 str r0, [r7, #4]
801351c: 6039 str r1, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE;
801351e: 2300 movs r3, #0
8013520: 62fb str r3, [r7, #44] @ 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8013522: 687b ldr r3, [r7, #4]
8013524: 627b str r3, [r7, #36] @ 0x24
#if ( configUSE_MUTEXES == 1 )
BaseType_t xInheritanceOccurred = pdFALSE;
8013526: 2300 movs r3, #0
8013528: 62bb str r3, [r7, #40] @ 0x28
#endif
/* Check the queue pointer is not NULL. */
configASSERT( ( pxQueue ) );
801352a: 6a7b ldr r3, [r7, #36] @ 0x24
801352c: 2b00 cmp r3, #0
801352e: d10b bne.n 8013548 <xQueueSemaphoreTake+0x34>
__asm volatile
8013530: f04f 0350 mov.w r3, #80 @ 0x50
8013534: f383 8811 msr BASEPRI, r3
8013538: f3bf 8f6f isb sy
801353c: f3bf 8f4f dsb sy
8013540: 61bb str r3, [r7, #24]
}
8013542: bf00 nop
8013544: bf00 nop
8013546: e7fd b.n 8013544 <xQueueSemaphoreTake+0x30>
/* Check this really is a semaphore, in which case the item size will be
* 0. */
configASSERT( pxQueue->uxItemSize == 0 );
8013548: 6a7b ldr r3, [r7, #36] @ 0x24
801354a: 6c1b ldr r3, [r3, #64] @ 0x40
801354c: 2b00 cmp r3, #0
801354e: d00b beq.n 8013568 <xQueueSemaphoreTake+0x54>
__asm volatile
8013550: f04f 0350 mov.w r3, #80 @ 0x50
8013554: f383 8811 msr BASEPRI, r3
8013558: f3bf 8f6f isb sy
801355c: f3bf 8f4f dsb sy
8013560: 617b str r3, [r7, #20]
}
8013562: bf00 nop
8013564: bf00 nop
8013566: e7fd b.n 8013564 <xQueueSemaphoreTake+0x50>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
8013568: f001 fb40 bl 8014bec <xTaskGetSchedulerState>
801356c: 4603 mov r3, r0
801356e: 2b00 cmp r3, #0
8013570: d102 bne.n 8013578 <xQueueSemaphoreTake+0x64>
8013572: 683b ldr r3, [r7, #0]
8013574: 2b00 cmp r3, #0
8013576: d101 bne.n 801357c <xQueueSemaphoreTake+0x68>
8013578: 2301 movs r3, #1
801357a: e000 b.n 801357e <xQueueSemaphoreTake+0x6a>
801357c: 2300 movs r3, #0
801357e: 2b00 cmp r3, #0
8013580: d10b bne.n 801359a <xQueueSemaphoreTake+0x86>
__asm volatile
8013582: f04f 0350 mov.w r3, #80 @ 0x50
8013586: f383 8811 msr BASEPRI, r3
801358a: f3bf 8f6f isb sy
801358e: f3bf 8f4f dsb sy
8013592: 613b str r3, [r7, #16]
}
8013594: bf00 nop
8013596: bf00 nop
8013598: e7fd b.n 8013596 <xQueueSemaphoreTake+0x82>
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
* statements within the function itself. This is done in the interest
* of execution time efficiency. */
for( ; ; )
{
taskENTER_CRITICAL();
801359a: f002 fe41 bl 8016220 <vPortEnterCritical>
{
/* Semaphores are queues with an item size of 0, and where the
* number of messages in the queue is the semaphore's count value. */
const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
801359e: 6a7b ldr r3, [r7, #36] @ 0x24
80135a0: 6b9b ldr r3, [r3, #56] @ 0x38
80135a2: 623b str r3, [r7, #32]
/* Is there data in the queue now? To be running the calling task
* must be the highest priority task wanting to access the queue. */
if( uxSemaphoreCount > ( UBaseType_t ) 0 )
80135a4: 6a3b ldr r3, [r7, #32]
80135a6: 2b00 cmp r3, #0
80135a8: d024 beq.n 80135f4 <xQueueSemaphoreTake+0xe0>
{
traceQUEUE_RECEIVE( pxQueue );
/* Semaphores are queues with a data size of zero and where the
* messages waiting is the semaphore's count. Reduce the count. */
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
80135aa: 6a3b ldr r3, [r7, #32]
80135ac: 1e5a subs r2, r3, #1
80135ae: 6a7b ldr r3, [r7, #36] @ 0x24
80135b0: 639a str r2, [r3, #56] @ 0x38
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
80135b2: 6a7b ldr r3, [r7, #36] @ 0x24
80135b4: 681b ldr r3, [r3, #0]
80135b6: 2b00 cmp r3, #0
80135b8: d104 bne.n 80135c4 <xQueueSemaphoreTake+0xb0>
{
/* Record the information required to implement
* priority inheritance should it become necessary. */
pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
80135ba: f001 fd09 bl 8014fd0 <pvTaskIncrementMutexHeldCount>
80135be: 4602 mov r2, r0
80135c0: 6a7b ldr r3, [r7, #36] @ 0x24
80135c2: 609a str r2, [r3, #8]
}
#endif /* configUSE_MUTEXES */
/* Check to see if other tasks are blocked waiting to give the
* semaphore, and if so, unblock the highest priority such task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
80135c4: 6a7b ldr r3, [r7, #36] @ 0x24
80135c6: 691b ldr r3, [r3, #16]
80135c8: 2b00 cmp r3, #0
80135ca: d00f beq.n 80135ec <xQueueSemaphoreTake+0xd8>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
80135cc: 6a7b ldr r3, [r7, #36] @ 0x24
80135ce: 3310 adds r3, #16
80135d0: 4618 mov r0, r3
80135d2: f001 f8c7 bl 8014764 <xTaskRemoveFromEventList>
80135d6: 4603 mov r3, r0
80135d8: 2b00 cmp r3, #0
80135da: d007 beq.n 80135ec <xQueueSemaphoreTake+0xd8>
{
queueYIELD_IF_USING_PREEMPTION();
80135dc: 4b4c ldr r3, [pc, #304] @ (8013710 <xQueueSemaphoreTake+0x1fc>)
80135de: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80135e2: 601a str r2, [r3, #0]
80135e4: f3bf 8f4f dsb sy
80135e8: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
80135ec: f002 fe4a bl 8016284 <vPortExitCritical>
return pdPASS;
80135f0: 2301 movs r3, #1
80135f2: e089 b.n 8013708 <xQueueSemaphoreTake+0x1f4>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
80135f4: 683b ldr r3, [r7, #0]
80135f6: 2b00 cmp r3, #0
80135f8: d103 bne.n 8013602 <xQueueSemaphoreTake+0xee>
{
/* The semaphore count was 0 and no block time is specified
* (or the block time has expired) so exit now. */
taskEXIT_CRITICAL();
80135fa: f002 fe43 bl 8016284 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
80135fe: 2300 movs r3, #0
8013600: e082 b.n 8013708 <xQueueSemaphoreTake+0x1f4>
}
else if( xEntryTimeSet == pdFALSE )
8013602: 6afb ldr r3, [r7, #44] @ 0x2c
8013604: 2b00 cmp r3, #0
8013606: d106 bne.n 8013616 <xQueueSemaphoreTake+0x102>
{
/* The semaphore count was 0 and a block time was specified
* so configure the timeout structure ready to block. */
vTaskInternalSetTimeOutState( &xTimeOut );
8013608: f107 0308 add.w r3, r7, #8
801360c: 4618 mov r0, r3
801360e: f001 f981 bl 8014914 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
8013612: 2301 movs r3, #1
8013614: 62fb str r3, [r7, #44] @ 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
8013616: f002 fe35 bl 8016284 <vPortExitCritical>
/* Interrupts and other tasks can give to and take from the semaphore
* now the critical section has been exited. */
vTaskSuspendAll();
801361a: f000 fd99 bl 8014150 <vTaskSuspendAll>
prvLockQueue( pxQueue );
801361e: f002 fdff bl 8016220 <vPortEnterCritical>
8013622: 6a7b ldr r3, [r7, #36] @ 0x24
8013624: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8013628: b25b sxtb r3, r3
801362a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
801362e: d103 bne.n 8013638 <xQueueSemaphoreTake+0x124>
8013630: 6a7b ldr r3, [r7, #36] @ 0x24
8013632: 2200 movs r2, #0
8013634: f883 2044 strb.w r2, [r3, #68] @ 0x44
8013638: 6a7b ldr r3, [r7, #36] @ 0x24
801363a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
801363e: b25b sxtb r3, r3
8013640: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8013644: d103 bne.n 801364e <xQueueSemaphoreTake+0x13a>
8013646: 6a7b ldr r3, [r7, #36] @ 0x24
8013648: 2200 movs r2, #0
801364a: f883 2045 strb.w r2, [r3, #69] @ 0x45
801364e: f002 fe19 bl 8016284 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
8013652: 463a mov r2, r7
8013654: f107 0308 add.w r3, r7, #8
8013658: 4611 mov r1, r2
801365a: 4618 mov r0, r3
801365c: f001 f970 bl 8014940 <xTaskCheckForTimeOut>
8013660: 4603 mov r3, r0
8013662: 2b00 cmp r3, #0
8013664: d132 bne.n 80136cc <xQueueSemaphoreTake+0x1b8>
{
/* A block time is specified and not expired. If the semaphore
* count is 0 then enter the Blocked state to wait for a semaphore to
* become available. As semaphores are implemented with queues the
* queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
8013666: 6a78 ldr r0, [r7, #36] @ 0x24
8013668: f000 fa0c bl 8013a84 <prvIsQueueEmpty>
801366c: 4603 mov r3, r0
801366e: 2b00 cmp r3, #0
8013670: d026 beq.n 80136c0 <xQueueSemaphoreTake+0x1ac>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
8013672: 6a7b ldr r3, [r7, #36] @ 0x24
8013674: 681b ldr r3, [r3, #0]
8013676: 2b00 cmp r3, #0
8013678: d109 bne.n 801368e <xQueueSemaphoreTake+0x17a>
{
taskENTER_CRITICAL();
801367a: f002 fdd1 bl 8016220 <vPortEnterCritical>
{
xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
801367e: 6a7b ldr r3, [r7, #36] @ 0x24
8013680: 689b ldr r3, [r3, #8]
8013682: 4618 mov r0, r3
8013684: f001 fad0 bl 8014c28 <xTaskPriorityInherit>
8013688: 62b8 str r0, [r7, #40] @ 0x28
}
taskEXIT_CRITICAL();
801368a: f002 fdfb bl 8016284 <vPortExitCritical>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* if ( configUSE_MUTEXES == 1 ) */
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
801368e: 6a7b ldr r3, [r7, #36] @ 0x24
8013690: 3324 adds r3, #36 @ 0x24
8013692: 683a ldr r2, [r7, #0]
8013694: 4611 mov r1, r2
8013696: 4618 mov r0, r3
8013698: f000 fff8 bl 801468c <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
801369c: 6a78 ldr r0, [r7, #36] @ 0x24
801369e: f000 f99f bl 80139e0 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
80136a2: f000 fd63 bl 801416c <xTaskResumeAll>
80136a6: 4603 mov r3, r0
80136a8: 2b00 cmp r3, #0
80136aa: f47f af76 bne.w 801359a <xQueueSemaphoreTake+0x86>
{
portYIELD_WITHIN_API();
80136ae: 4b18 ldr r3, [pc, #96] @ (8013710 <xQueueSemaphoreTake+0x1fc>)
80136b0: f04f 5280 mov.w r2, #268435456 @ 0x10000000
80136b4: 601a str r2, [r3, #0]
80136b6: f3bf 8f4f dsb sy
80136ba: f3bf 8f6f isb sy
80136be: e76c b.n 801359a <xQueueSemaphoreTake+0x86>
}
else
{
/* There was no timeout and the semaphore count was not 0, so
* attempt to take the semaphore again. */
prvUnlockQueue( pxQueue );
80136c0: 6a78 ldr r0, [r7, #36] @ 0x24
80136c2: f000 f98d bl 80139e0 <prvUnlockQueue>
( void ) xTaskResumeAll();
80136c6: f000 fd51 bl 801416c <xTaskResumeAll>
80136ca: e766 b.n 801359a <xQueueSemaphoreTake+0x86>
}
}
else
{
/* Timed out. */
prvUnlockQueue( pxQueue );
80136cc: 6a78 ldr r0, [r7, #36] @ 0x24
80136ce: f000 f987 bl 80139e0 <prvUnlockQueue>
( void ) xTaskResumeAll();
80136d2: f000 fd4b bl 801416c <xTaskResumeAll>
/* If the semaphore count is 0 exit now as the timeout has
* expired. Otherwise return to attempt to take the semaphore that is
* known to be available. As semaphores are implemented by queues the
* queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
80136d6: 6a78 ldr r0, [r7, #36] @ 0x24
80136d8: f000 f9d4 bl 8013a84 <prvIsQueueEmpty>
80136dc: 4603 mov r3, r0
80136de: 2b00 cmp r3, #0
80136e0: f43f af5b beq.w 801359a <xQueueSemaphoreTake+0x86>
#if ( configUSE_MUTEXES == 1 )
{
/* xInheritanceOccurred could only have be set if
* pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
* test the mutex type again to check it is actually a mutex. */
if( xInheritanceOccurred != pdFALSE )
80136e4: 6abb ldr r3, [r7, #40] @ 0x28
80136e6: 2b00 cmp r3, #0
80136e8: d00d beq.n 8013706 <xQueueSemaphoreTake+0x1f2>
{
taskENTER_CRITICAL();
80136ea: f002 fd99 bl 8016220 <vPortEnterCritical>
/* This task blocking on the mutex caused another
* task to inherit this task's priority. Now this task
* has timed out the priority should be disinherited
* again, but only as low as the next highest priority
* task that is waiting for the same mutex. */
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
80136ee: 6a78 ldr r0, [r7, #36] @ 0x24
80136f0: f000 f8ce bl 8013890 <prvGetDisinheritPriorityAfterTimeout>
80136f4: 61f8 str r0, [r7, #28]
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
80136f6: 6a7b ldr r3, [r7, #36] @ 0x24
80136f8: 689b ldr r3, [r3, #8]
80136fa: 69f9 ldr r1, [r7, #28]
80136fc: 4618 mov r0, r3
80136fe: f001 fbbb bl 8014e78 <vTaskPriorityDisinheritAfterTimeout>
}
taskEXIT_CRITICAL();
8013702: f002 fdbf bl 8016284 <vPortExitCritical>
}
}
#endif /* configUSE_MUTEXES */
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
8013706: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
8013708: 4618 mov r0, r3
801370a: 3730 adds r7, #48 @ 0x30
801370c: 46bd mov sp, r7
801370e: bd80 pop {r7, pc}
8013710: e000ed04 .word 0xe000ed04
08013714 <xQueueReceiveFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
void * const pvBuffer,
BaseType_t * const pxHigherPriorityTaskWoken )
{
8013714: b580 push {r7, lr}
8013716: b090 sub sp, #64 @ 0x40
8013718: af00 add r7, sp, #0
801371a: 60f8 str r0, [r7, #12]
801371c: 60b9 str r1, [r7, #8]
801371e: 607a str r2, [r7, #4]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
8013720: 68fb ldr r3, [r7, #12]
8013722: 63bb str r3, [r7, #56] @ 0x38
configASSERT( pxQueue );
8013724: 6bbb ldr r3, [r7, #56] @ 0x38
8013726: 2b00 cmp r3, #0
8013728: d10b bne.n 8013742 <xQueueReceiveFromISR+0x2e>
__asm volatile
801372a: f04f 0350 mov.w r3, #80 @ 0x50
801372e: f383 8811 msr BASEPRI, r3
8013732: f3bf 8f6f isb sy
8013736: f3bf 8f4f dsb sy
801373a: 627b str r3, [r7, #36] @ 0x24
}
801373c: bf00 nop
801373e: bf00 nop
8013740: e7fd b.n 801373e <xQueueReceiveFromISR+0x2a>
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
8013742: 68bb ldr r3, [r7, #8]
8013744: 2b00 cmp r3, #0
8013746: d103 bne.n 8013750 <xQueueReceiveFromISR+0x3c>
8013748: 6bbb ldr r3, [r7, #56] @ 0x38
801374a: 6c1b ldr r3, [r3, #64] @ 0x40
801374c: 2b00 cmp r3, #0
801374e: d101 bne.n 8013754 <xQueueReceiveFromISR+0x40>
8013750: 2301 movs r3, #1
8013752: e000 b.n 8013756 <xQueueReceiveFromISR+0x42>
8013754: 2300 movs r3, #0
8013756: 2b00 cmp r3, #0
8013758: d10b bne.n 8013772 <xQueueReceiveFromISR+0x5e>
__asm volatile
801375a: f04f 0350 mov.w r3, #80 @ 0x50
801375e: f383 8811 msr BASEPRI, r3
8013762: f3bf 8f6f isb sy
8013766: f3bf 8f4f dsb sy
801376a: 623b str r3, [r7, #32]
}
801376c: bf00 nop
801376e: bf00 nop
8013770: e7fd b.n 801376e <xQueueReceiveFromISR+0x5a>
* that have been assigned a priority at or (logically) below the maximum
* system call interrupt priority. FreeRTOS maintains a separate interrupt
* safe API to ensure interrupt entry is as fast and as simple as possible.
* More information (albeit Cortex-M specific) is provided on the following
* link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
8013772: f002 fe3b bl 80163ec <vPortValidateInterruptPriority>
__asm volatile
8013776: f3ef 8211 mrs r2, BASEPRI
801377a: f04f 0350 mov.w r3, #80 @ 0x50
801377e: f383 8811 msr BASEPRI, r3
8013782: f3bf 8f6f isb sy
8013786: f3bf 8f4f dsb sy
801378a: 61fa str r2, [r7, #28]
801378c: 61bb str r3, [r7, #24]
return ulOriginalBASEPRI;
801378e: 69fb ldr r3, [r7, #28]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
8013790: 637b str r3, [r7, #52] @ 0x34
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
8013792: 6bbb ldr r3, [r7, #56] @ 0x38
8013794: 6b9b ldr r3, [r3, #56] @ 0x38
8013796: 633b str r3, [r7, #48] @ 0x30
/* Cannot block in an ISR, so check there is data available. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
8013798: 6b3b ldr r3, [r7, #48] @ 0x30
801379a: 2b00 cmp r3, #0
801379c: d047 beq.n 801382e <xQueueReceiveFromISR+0x11a>
{
const int8_t cRxLock = pxQueue->cRxLock;
801379e: 6bbb ldr r3, [r7, #56] @ 0x38
80137a0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
80137a4: f887 302f strb.w r3, [r7, #47] @ 0x2f
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
prvCopyDataFromQueue( pxQueue, pvBuffer );
80137a8: 68b9 ldr r1, [r7, #8]
80137aa: 6bb8 ldr r0, [r7, #56] @ 0x38
80137ac: f000 f8f2 bl 8013994 <prvCopyDataFromQueue>
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
80137b0: 6b3b ldr r3, [r7, #48] @ 0x30
80137b2: 1e5a subs r2, r3, #1
80137b4: 6bbb ldr r3, [r7, #56] @ 0x38
80137b6: 639a str r2, [r3, #56] @ 0x38
/* If the queue is locked the event list will not be modified.
* Instead update the lock count so the task that unlocks the queue
* will know that an ISR has removed data while the queue was
* locked. */
if( cRxLock == queueUNLOCKED )
80137b8: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
80137bc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80137c0: d112 bne.n 80137e8 <xQueueReceiveFromISR+0xd4>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
80137c2: 6bbb ldr r3, [r7, #56] @ 0x38
80137c4: 691b ldr r3, [r3, #16]
80137c6: 2b00 cmp r3, #0
80137c8: d02e beq.n 8013828 <xQueueReceiveFromISR+0x114>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
80137ca: 6bbb ldr r3, [r7, #56] @ 0x38
80137cc: 3310 adds r3, #16
80137ce: 4618 mov r0, r3
80137d0: f000 ffc8 bl 8014764 <xTaskRemoveFromEventList>
80137d4: 4603 mov r3, r0
80137d6: 2b00 cmp r3, #0
80137d8: d026 beq.n 8013828 <xQueueReceiveFromISR+0x114>
{
/* The task waiting has a higher priority than us so
* force a context switch. */
if( pxHigherPriorityTaskWoken != NULL )
80137da: 687b ldr r3, [r7, #4]
80137dc: 2b00 cmp r3, #0
80137de: d023 beq.n 8013828 <xQueueReceiveFromISR+0x114>
{
*pxHigherPriorityTaskWoken = pdTRUE;
80137e0: 687b ldr r3, [r7, #4]
80137e2: 2201 movs r2, #1
80137e4: 601a str r2, [r3, #0]
80137e6: e01f b.n 8013828 <xQueueReceiveFromISR+0x114>
}
else
{
/* Increment the lock count so the task that unlocks the queue
* knows that data was removed while it was locked. */
prvIncrementQueueRxLock( pxQueue, cRxLock );
80137e8: f000 fdce bl 8014388 <uxTaskGetNumberOfTasks>
80137ec: 62b8 str r0, [r7, #40] @ 0x28
80137ee: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
80137f2: 6aba ldr r2, [r7, #40] @ 0x28
80137f4: 429a cmp r2, r3
80137f6: d917 bls.n 8013828 <xQueueReceiveFromISR+0x114>
80137f8: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f
80137fc: 2b7f cmp r3, #127 @ 0x7f
80137fe: d10b bne.n 8013818 <xQueueReceiveFromISR+0x104>
__asm volatile
8013800: f04f 0350 mov.w r3, #80 @ 0x50
8013804: f383 8811 msr BASEPRI, r3
8013808: f3bf 8f6f isb sy
801380c: f3bf 8f4f dsb sy
8013810: 617b str r3, [r7, #20]
}
8013812: bf00 nop
8013814: bf00 nop
8013816: e7fd b.n 8013814 <xQueueReceiveFromISR+0x100>
8013818: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
801381c: 3301 adds r3, #1
801381e: b2db uxtb r3, r3
8013820: b25a sxtb r2, r3
8013822: 6bbb ldr r3, [r7, #56] @ 0x38
8013824: f883 2044 strb.w r2, [r3, #68] @ 0x44
}
xReturn = pdPASS;
8013828: 2301 movs r3, #1
801382a: 63fb str r3, [r7, #60] @ 0x3c
801382c: e001 b.n 8013832 <xQueueReceiveFromISR+0x11e>
}
else
{
xReturn = pdFAIL;
801382e: 2300 movs r3, #0
8013830: 63fb str r3, [r7, #60] @ 0x3c
8013832: 6b7b ldr r3, [r7, #52] @ 0x34
8013834: 613b str r3, [r7, #16]
__asm volatile
8013836: 693b ldr r3, [r7, #16]
8013838: f383 8811 msr BASEPRI, r3
}
801383c: bf00 nop
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
801383e: 6bfb ldr r3, [r7, #60] @ 0x3c
}
8013840: 4618 mov r0, r3
8013842: 3740 adds r7, #64 @ 0x40
8013844: 46bd mov sp, r7
8013846: bd80 pop {r7, pc}
08013848 <vQueueDelete>:
return uxReturn;
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
/*-----------------------------------------------------------*/
void vQueueDelete( QueueHandle_t xQueue )
{
8013848: b580 push {r7, lr}
801384a: b084 sub sp, #16
801384c: af00 add r7, sp, #0
801384e: 6078 str r0, [r7, #4]
Queue_t * const pxQueue = xQueue;
8013850: 687b ldr r3, [r7, #4]
8013852: 60fb str r3, [r7, #12]
configASSERT( pxQueue );
8013854: 68fb ldr r3, [r7, #12]
8013856: 2b00 cmp r3, #0
8013858: d10b bne.n 8013872 <vQueueDelete+0x2a>
__asm volatile
801385a: f04f 0350 mov.w r3, #80 @ 0x50
801385e: f383 8811 msr BASEPRI, r3
8013862: f3bf 8f6f isb sy
8013866: f3bf 8f4f dsb sy
801386a: 60bb str r3, [r7, #8]
}
801386c: bf00 nop
801386e: bf00 nop
8013870: e7fd b.n 801386e <vQueueDelete+0x26>
traceQUEUE_DELETE( pxQueue );
#if ( configQUEUE_REGISTRY_SIZE > 0 )
{
vQueueUnregisterQueue( pxQueue );
8013872: 68f8 ldr r0, [r7, #12]
8013874: f000 f984 bl 8013b80 <vQueueUnregisterQueue>
}
#elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
{
/* The queue could have been allocated statically or dynamically, so
* check before attempting to free the memory. */
if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
8013878: 68fb ldr r3, [r7, #12]
801387a: f893 3046 ldrb.w r3, [r3, #70] @ 0x46
801387e: 2b00 cmp r3, #0
8013880: d102 bne.n 8013888 <vQueueDelete+0x40>
{
vPortFree( pxQueue );
8013882: 68f8 ldr r0, [r7, #12]
8013884: f002 fec0 bl 8016608 <vPortFree>
/* The queue must have been statically allocated, so is not going to be
* deleted. Avoid compiler warnings about the unused parameter. */
( void ) pxQueue;
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
8013888: bf00 nop
801388a: 3710 adds r7, #16
801388c: 46bd mov sp, r7
801388e: bd80 pop {r7, pc}
08013890 <prvGetDisinheritPriorityAfterTimeout>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
{
8013890: b480 push {r7}
8013892: b085 sub sp, #20
8013894: af00 add r7, sp, #0
8013896: 6078 str r0, [r7, #4]
* priority, but the waiting task times out, then the holder should
* disinherit the priority - but only down to the highest priority of any
* other tasks that are waiting for the same mutex. For this purpose,
* return the priority of the highest priority task that is waiting for the
* mutex. */
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
8013898: 687b ldr r3, [r7, #4]
801389a: 6a5b ldr r3, [r3, #36] @ 0x24
801389c: 2b00 cmp r3, #0
801389e: d006 beq.n 80138ae <prvGetDisinheritPriorityAfterTimeout+0x1e>
{
uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
80138a0: 687b ldr r3, [r7, #4]
80138a2: 6b1b ldr r3, [r3, #48] @ 0x30
80138a4: 681b ldr r3, [r3, #0]
80138a6: f1c3 0338 rsb r3, r3, #56 @ 0x38
80138aa: 60fb str r3, [r7, #12]
80138ac: e001 b.n 80138b2 <prvGetDisinheritPriorityAfterTimeout+0x22>
}
else
{
uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
80138ae: 2300 movs r3, #0
80138b0: 60fb str r3, [r7, #12]
}
return uxHighestPriorityOfWaitingTasks;
80138b2: 68fb ldr r3, [r7, #12]
}
80138b4: 4618 mov r0, r3
80138b6: 3714 adds r7, #20
80138b8: 46bd mov sp, r7
80138ba: f85d 7b04 ldr.w r7, [sp], #4
80138be: 4770 bx lr
080138c0 <prvCopyDataToQueue>:
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
const void * pvItemToQueue,
const BaseType_t xPosition )
{
80138c0: b580 push {r7, lr}
80138c2: b086 sub sp, #24
80138c4: af00 add r7, sp, #0
80138c6: 60f8 str r0, [r7, #12]
80138c8: 60b9 str r1, [r7, #8]
80138ca: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
80138cc: 2300 movs r3, #0
80138ce: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
80138d0: 68fb ldr r3, [r7, #12]
80138d2: 6b9b ldr r3, [r3, #56] @ 0x38
80138d4: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
80138d6: 68fb ldr r3, [r7, #12]
80138d8: 6c1b ldr r3, [r3, #64] @ 0x40
80138da: 2b00 cmp r3, #0
80138dc: d10d bne.n 80138fa <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
80138de: 68fb ldr r3, [r7, #12]
80138e0: 681b ldr r3, [r3, #0]
80138e2: 2b00 cmp r3, #0
80138e4: d14d bne.n 8013982 <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
80138e6: 68fb ldr r3, [r7, #12]
80138e8: 689b ldr r3, [r3, #8]
80138ea: 4618 mov r0, r3
80138ec: f001 fa2c bl 8014d48 <xTaskPriorityDisinherit>
80138f0: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
80138f2: 68fb ldr r3, [r7, #12]
80138f4: 2200 movs r2, #0
80138f6: 609a str r2, [r3, #8]
80138f8: e043 b.n 8013982 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
80138fa: 687b ldr r3, [r7, #4]
80138fc: 2b00 cmp r3, #0
80138fe: d119 bne.n 8013934 <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
8013900: 68fb ldr r3, [r7, #12]
8013902: 6858 ldr r0, [r3, #4]
8013904: 68fb ldr r3, [r7, #12]
8013906: 6c1b ldr r3, [r3, #64] @ 0x40
8013908: 461a mov r2, r3
801390a: 68b9 ldr r1, [r7, #8]
801390c: f005 f8e1 bl 8018ad2 <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
8013910: 68fb ldr r3, [r7, #12]
8013912: 685a ldr r2, [r3, #4]
8013914: 68fb ldr r3, [r7, #12]
8013916: 6c1b ldr r3, [r3, #64] @ 0x40
8013918: 441a add r2, r3
801391a: 68fb ldr r3, [r7, #12]
801391c: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
801391e: 68fb ldr r3, [r7, #12]
8013920: 685a ldr r2, [r3, #4]
8013922: 68fb ldr r3, [r7, #12]
8013924: 689b ldr r3, [r3, #8]
8013926: 429a cmp r2, r3
8013928: d32b bcc.n 8013982 <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
801392a: 68fb ldr r3, [r7, #12]
801392c: 681a ldr r2, [r3, #0]
801392e: 68fb ldr r3, [r7, #12]
8013930: 605a str r2, [r3, #4]
8013932: e026 b.n 8013982 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
8013934: 68fb ldr r3, [r7, #12]
8013936: 68d8 ldr r0, [r3, #12]
8013938: 68fb ldr r3, [r7, #12]
801393a: 6c1b ldr r3, [r3, #64] @ 0x40
801393c: 461a mov r2, r3
801393e: 68b9 ldr r1, [r7, #8]
8013940: f005 f8c7 bl 8018ad2 <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
8013944: 68fb ldr r3, [r7, #12]
8013946: 68da ldr r2, [r3, #12]
8013948: 68fb ldr r3, [r7, #12]
801394a: 6c1b ldr r3, [r3, #64] @ 0x40
801394c: 425b negs r3, r3
801394e: 441a add r2, r3
8013950: 68fb ldr r3, [r7, #12]
8013952: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
8013954: 68fb ldr r3, [r7, #12]
8013956: 68da ldr r2, [r3, #12]
8013958: 68fb ldr r3, [r7, #12]
801395a: 681b ldr r3, [r3, #0]
801395c: 429a cmp r2, r3
801395e: d207 bcs.n 8013970 <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
8013960: 68fb ldr r3, [r7, #12]
8013962: 689a ldr r2, [r3, #8]
8013964: 68fb ldr r3, [r7, #12]
8013966: 6c1b ldr r3, [r3, #64] @ 0x40
8013968: 425b negs r3, r3
801396a: 441a add r2, r3
801396c: 68fb ldr r3, [r7, #12]
801396e: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
8013970: 687b ldr r3, [r7, #4]
8013972: 2b02 cmp r3, #2
8013974: d105 bne.n 8013982 <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
8013976: 693b ldr r3, [r7, #16]
8013978: 2b00 cmp r3, #0
801397a: d002 beq.n 8013982 <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
* one from the recorded number of items in the queue so when
* one is added again below the number of recorded items remains
* correct. */
--uxMessagesWaiting;
801397c: 693b ldr r3, [r7, #16]
801397e: 3b01 subs r3, #1
8013980: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
8013982: 693b ldr r3, [r7, #16]
8013984: 1c5a adds r2, r3, #1
8013986: 68fb ldr r3, [r7, #12]
8013988: 639a str r2, [r3, #56] @ 0x38
return xReturn;
801398a: 697b ldr r3, [r7, #20]
}
801398c: 4618 mov r0, r3
801398e: 3718 adds r7, #24
8013990: 46bd mov sp, r7
8013992: bd80 pop {r7, pc}
08013994 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( Queue_t * const pxQueue,
void * const pvBuffer )
{
8013994: b580 push {r7, lr}
8013996: b082 sub sp, #8
8013998: af00 add r7, sp, #0
801399a: 6078 str r0, [r7, #4]
801399c: 6039 str r1, [r7, #0]
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
801399e: 687b ldr r3, [r7, #4]
80139a0: 6c1b ldr r3, [r3, #64] @ 0x40
80139a2: 2b00 cmp r3, #0
80139a4: d018 beq.n 80139d8 <prvCopyDataFromQueue+0x44>
{
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
80139a6: 687b ldr r3, [r7, #4]
80139a8: 68da ldr r2, [r3, #12]
80139aa: 687b ldr r3, [r7, #4]
80139ac: 6c1b ldr r3, [r3, #64] @ 0x40
80139ae: 441a add r2, r3
80139b0: 687b ldr r3, [r7, #4]
80139b2: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
80139b4: 687b ldr r3, [r7, #4]
80139b6: 68da ldr r2, [r3, #12]
80139b8: 687b ldr r3, [r7, #4]
80139ba: 689b ldr r3, [r3, #8]
80139bc: 429a cmp r2, r3
80139be: d303 bcc.n 80139c8 <prvCopyDataFromQueue+0x34>
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
80139c0: 687b ldr r3, [r7, #4]
80139c2: 681a ldr r2, [r3, #0]
80139c4: 687b ldr r3, [r7, #4]
80139c6: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
80139c8: 687b ldr r3, [r7, #4]
80139ca: 68d9 ldr r1, [r3, #12]
80139cc: 687b ldr r3, [r7, #4]
80139ce: 6c1b ldr r3, [r3, #64] @ 0x40
80139d0: 461a mov r2, r3
80139d2: 6838 ldr r0, [r7, #0]
80139d4: f005 f87d bl 8018ad2 <memcpy>
}
}
80139d8: bf00 nop
80139da: 3708 adds r7, #8
80139dc: 46bd mov sp, r7
80139de: bd80 pop {r7, pc}
080139e0 <prvUnlockQueue>:
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
80139e0: b580 push {r7, lr}
80139e2: b084 sub sp, #16
80139e4: af00 add r7, sp, #0
80139e6: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
* removed from the queue while the queue was locked. When a queue is
* locked items can be added or removed, but the event lists cannot be
* updated. */
taskENTER_CRITICAL();
80139e8: f002 fc1a bl 8016220 <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
80139ec: 687b ldr r3, [r7, #4]
80139ee: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
80139f2: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
80139f4: e011 b.n 8013a1a <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
* the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
80139f6: 687b ldr r3, [r7, #4]
80139f8: 6a5b ldr r3, [r3, #36] @ 0x24
80139fa: 2b00 cmp r3, #0
80139fc: d012 beq.n 8013a24 <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
80139fe: 687b ldr r3, [r7, #4]
8013a00: 3324 adds r3, #36 @ 0x24
8013a02: 4618 mov r0, r3
8013a04: f000 feae bl 8014764 <xTaskRemoveFromEventList>
8013a08: 4603 mov r3, r0
8013a0a: 2b00 cmp r3, #0
8013a0c: d001 beq.n 8013a12 <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
* a context switch is required. */
vTaskMissedYield();
8013a0e: f000 ffff bl 8014a10 <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
8013a12: 7bfb ldrb r3, [r7, #15]
8013a14: 3b01 subs r3, #1
8013a16: b2db uxtb r3, r3
8013a18: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
8013a1a: f997 300f ldrsb.w r3, [r7, #15]
8013a1e: 2b00 cmp r3, #0
8013a20: dce9 bgt.n 80139f6 <prvUnlockQueue+0x16>
8013a22: e000 b.n 8013a26 <prvUnlockQueue+0x46>
break;
8013a24: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
8013a26: 687b ldr r3, [r7, #4]
8013a28: 22ff movs r2, #255 @ 0xff
8013a2a: f883 2045 strb.w r2, [r3, #69] @ 0x45
}
taskEXIT_CRITICAL();
8013a2e: f002 fc29 bl 8016284 <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
8013a32: f002 fbf5 bl 8016220 <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
8013a36: 687b ldr r3, [r7, #4]
8013a38: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8013a3c: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
8013a3e: e011 b.n 8013a64 <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8013a40: 687b ldr r3, [r7, #4]
8013a42: 691b ldr r3, [r3, #16]
8013a44: 2b00 cmp r3, #0
8013a46: d012 beq.n 8013a6e <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8013a48: 687b ldr r3, [r7, #4]
8013a4a: 3310 adds r3, #16
8013a4c: 4618 mov r0, r3
8013a4e: f000 fe89 bl 8014764 <xTaskRemoveFromEventList>
8013a52: 4603 mov r3, r0
8013a54: 2b00 cmp r3, #0
8013a56: d001 beq.n 8013a5c <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
8013a58: f000 ffda bl 8014a10 <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
8013a5c: 7bbb ldrb r3, [r7, #14]
8013a5e: 3b01 subs r3, #1
8013a60: b2db uxtb r3, r3
8013a62: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
8013a64: f997 300e ldrsb.w r3, [r7, #14]
8013a68: 2b00 cmp r3, #0
8013a6a: dce9 bgt.n 8013a40 <prvUnlockQueue+0x60>
8013a6c: e000 b.n 8013a70 <prvUnlockQueue+0x90>
}
else
{
break;
8013a6e: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
8013a70: 687b ldr r3, [r7, #4]
8013a72: 22ff movs r2, #255 @ 0xff
8013a74: f883 2044 strb.w r2, [r3, #68] @ 0x44
}
taskEXIT_CRITICAL();
8013a78: f002 fc04 bl 8016284 <vPortExitCritical>
}
8013a7c: bf00 nop
8013a7e: 3710 adds r7, #16
8013a80: 46bd mov sp, r7
8013a82: bd80 pop {r7, pc}
08013a84 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue )
{
8013a84: b580 push {r7, lr}
8013a86: b084 sub sp, #16
8013a88: af00 add r7, sp, #0
8013a8a: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
8013a8c: f002 fbc8 bl 8016220 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
8013a90: 687b ldr r3, [r7, #4]
8013a92: 6b9b ldr r3, [r3, #56] @ 0x38
8013a94: 2b00 cmp r3, #0
8013a96: d102 bne.n 8013a9e <prvIsQueueEmpty+0x1a>
{
xReturn = pdTRUE;
8013a98: 2301 movs r3, #1
8013a9a: 60fb str r3, [r7, #12]
8013a9c: e001 b.n 8013aa2 <prvIsQueueEmpty+0x1e>
}
else
{
xReturn = pdFALSE;
8013a9e: 2300 movs r3, #0
8013aa0: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
8013aa2: f002 fbef bl 8016284 <vPortExitCritical>
return xReturn;
8013aa6: 68fb ldr r3, [r7, #12]
}
8013aa8: 4618 mov r0, r3
8013aaa: 3710 adds r7, #16
8013aac: 46bd mov sp, r7
8013aae: bd80 pop {r7, pc}
08013ab0 <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t * pxQueue )
{
8013ab0: b580 push {r7, lr}
8013ab2: b084 sub sp, #16
8013ab4: af00 add r7, sp, #0
8013ab6: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
8013ab8: f002 fbb2 bl 8016220 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
8013abc: 687b ldr r3, [r7, #4]
8013abe: 6b9a ldr r2, [r3, #56] @ 0x38
8013ac0: 687b ldr r3, [r7, #4]
8013ac2: 6bdb ldr r3, [r3, #60] @ 0x3c
8013ac4: 429a cmp r2, r3
8013ac6: d102 bne.n 8013ace <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
8013ac8: 2301 movs r3, #1
8013aca: 60fb str r3, [r7, #12]
8013acc: e001 b.n 8013ad2 <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
8013ace: 2300 movs r3, #0
8013ad0: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
8013ad2: f002 fbd7 bl 8016284 <vPortExitCritical>
return xReturn;
8013ad6: 68fb ldr r3, [r7, #12]
}
8013ad8: 4618 mov r0, r3
8013ada: 3710 adds r7, #16
8013adc: 46bd mov sp, r7
8013ade: bd80 pop {r7, pc}
08013ae0 <vQueueAddToRegistry>:
#if ( configQUEUE_REGISTRY_SIZE > 0 )
void vQueueAddToRegistry( QueueHandle_t xQueue,
const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
{
8013ae0: b480 push {r7}
8013ae2: b087 sub sp, #28
8013ae4: af00 add r7, sp, #0
8013ae6: 6078 str r0, [r7, #4]
8013ae8: 6039 str r1, [r7, #0]
UBaseType_t ux;
QueueRegistryItem_t * pxEntryToWrite = NULL;
8013aea: 2300 movs r3, #0
8013aec: 613b str r3, [r7, #16]
configASSERT( xQueue );
8013aee: 687b ldr r3, [r7, #4]
8013af0: 2b00 cmp r3, #0
8013af2: d10b bne.n 8013b0c <vQueueAddToRegistry+0x2c>
__asm volatile
8013af4: f04f 0350 mov.w r3, #80 @ 0x50
8013af8: f383 8811 msr BASEPRI, r3
8013afc: f3bf 8f6f isb sy
8013b00: f3bf 8f4f dsb sy
8013b04: 60fb str r3, [r7, #12]
}
8013b06: bf00 nop
8013b08: bf00 nop
8013b0a: e7fd b.n 8013b08 <vQueueAddToRegistry+0x28>
if( pcQueueName != NULL )
8013b0c: 683b ldr r3, [r7, #0]
8013b0e: 2b00 cmp r3, #0
8013b10: d024 beq.n 8013b5c <vQueueAddToRegistry+0x7c>
{
/* See if there is an empty space in the registry. A NULL name denotes
* a free slot. */
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
8013b12: 2300 movs r3, #0
8013b14: 617b str r3, [r7, #20]
8013b16: e01e b.n 8013b56 <vQueueAddToRegistry+0x76>
{
/* Replace an existing entry if the queue is already in the registry. */
if( xQueue == xQueueRegistry[ ux ].xHandle )
8013b18: 4a18 ldr r2, [pc, #96] @ (8013b7c <vQueueAddToRegistry+0x9c>)
8013b1a: 697b ldr r3, [r7, #20]
8013b1c: 00db lsls r3, r3, #3
8013b1e: 4413 add r3, r2
8013b20: 685b ldr r3, [r3, #4]
8013b22: 687a ldr r2, [r7, #4]
8013b24: 429a cmp r2, r3
8013b26: d105 bne.n 8013b34 <vQueueAddToRegistry+0x54>
{
pxEntryToWrite = &( xQueueRegistry[ ux ] );
8013b28: 697b ldr r3, [r7, #20]
8013b2a: 00db lsls r3, r3, #3
8013b2c: 4a13 ldr r2, [pc, #76] @ (8013b7c <vQueueAddToRegistry+0x9c>)
8013b2e: 4413 add r3, r2
8013b30: 613b str r3, [r7, #16]
break;
8013b32: e013 b.n 8013b5c <vQueueAddToRegistry+0x7c>
}
/* Otherwise, store in the next empty location */
else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) )
8013b34: 693b ldr r3, [r7, #16]
8013b36: 2b00 cmp r3, #0
8013b38: d10a bne.n 8013b50 <vQueueAddToRegistry+0x70>
8013b3a: 4a10 ldr r2, [pc, #64] @ (8013b7c <vQueueAddToRegistry+0x9c>)
8013b3c: 697b ldr r3, [r7, #20]
8013b3e: f852 3033 ldr.w r3, [r2, r3, lsl #3]
8013b42: 2b00 cmp r3, #0
8013b44: d104 bne.n 8013b50 <vQueueAddToRegistry+0x70>
{
pxEntryToWrite = &( xQueueRegistry[ ux ] );
8013b46: 697b ldr r3, [r7, #20]
8013b48: 00db lsls r3, r3, #3
8013b4a: 4a0c ldr r2, [pc, #48] @ (8013b7c <vQueueAddToRegistry+0x9c>)
8013b4c: 4413 add r3, r2
8013b4e: 613b str r3, [r7, #16]
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
8013b50: 697b ldr r3, [r7, #20]
8013b52: 3301 adds r3, #1
8013b54: 617b str r3, [r7, #20]
8013b56: 697b ldr r3, [r7, #20]
8013b58: 2b07 cmp r3, #7
8013b5a: d9dd bls.n 8013b18 <vQueueAddToRegistry+0x38>
mtCOVERAGE_TEST_MARKER();
}
}
}
if( pxEntryToWrite != NULL )
8013b5c: 693b ldr r3, [r7, #16]
8013b5e: 2b00 cmp r3, #0
8013b60: d005 beq.n 8013b6e <vQueueAddToRegistry+0x8e>
{
/* Store the information on this queue. */
pxEntryToWrite->pcQueueName = pcQueueName;
8013b62: 693b ldr r3, [r7, #16]
8013b64: 683a ldr r2, [r7, #0]
8013b66: 601a str r2, [r3, #0]
pxEntryToWrite->xHandle = xQueue;
8013b68: 693b ldr r3, [r7, #16]
8013b6a: 687a ldr r2, [r7, #4]
8013b6c: 605a str r2, [r3, #4]
traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
}
}
8013b6e: bf00 nop
8013b70: 371c adds r7, #28
8013b72: 46bd mov sp, r7
8013b74: f85d 7b04 ldr.w r7, [sp], #4
8013b78: 4770 bx lr
8013b7a: bf00 nop
8013b7c: 20002088 .word 0x20002088
08013b80 <vQueueUnregisterQueue>:
/*-----------------------------------------------------------*/
#if ( configQUEUE_REGISTRY_SIZE > 0 )
void vQueueUnregisterQueue( QueueHandle_t xQueue )
{
8013b80: b480 push {r7}
8013b82: b085 sub sp, #20
8013b84: af00 add r7, sp, #0
8013b86: 6078 str r0, [r7, #4]
UBaseType_t ux;
configASSERT( xQueue );
8013b88: 687b ldr r3, [r7, #4]
8013b8a: 2b00 cmp r3, #0
8013b8c: d10b bne.n 8013ba6 <vQueueUnregisterQueue+0x26>
__asm volatile
8013b8e: f04f 0350 mov.w r3, #80 @ 0x50
8013b92: f383 8811 msr BASEPRI, r3
8013b96: f3bf 8f6f isb sy
8013b9a: f3bf 8f4f dsb sy
8013b9e: 60bb str r3, [r7, #8]
}
8013ba0: bf00 nop
8013ba2: bf00 nop
8013ba4: e7fd b.n 8013ba2 <vQueueUnregisterQueue+0x22>
/* See if the handle of the queue being unregistered in actually in the
* registry. */
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
8013ba6: 2300 movs r3, #0
8013ba8: 60fb str r3, [r7, #12]
8013baa: e016 b.n 8013bda <vQueueUnregisterQueue+0x5a>
{
if( xQueueRegistry[ ux ].xHandle == xQueue )
8013bac: 4a10 ldr r2, [pc, #64] @ (8013bf0 <vQueueUnregisterQueue+0x70>)
8013bae: 68fb ldr r3, [r7, #12]
8013bb0: 00db lsls r3, r3, #3
8013bb2: 4413 add r3, r2
8013bb4: 685b ldr r3, [r3, #4]
8013bb6: 687a ldr r2, [r7, #4]
8013bb8: 429a cmp r2, r3
8013bba: d10b bne.n 8013bd4 <vQueueUnregisterQueue+0x54>
{
/* Set the name to NULL to show that this slot if free again. */
xQueueRegistry[ ux ].pcQueueName = NULL;
8013bbc: 4a0c ldr r2, [pc, #48] @ (8013bf0 <vQueueUnregisterQueue+0x70>)
8013bbe: 68fb ldr r3, [r7, #12]
8013bc0: 2100 movs r1, #0
8013bc2: f842 1033 str.w r1, [r2, r3, lsl #3]
/* Set the handle to NULL to ensure the same queue handle cannot
* appear in the registry twice if it is added, removed, then
* added again. */
xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
8013bc6: 4a0a ldr r2, [pc, #40] @ (8013bf0 <vQueueUnregisterQueue+0x70>)
8013bc8: 68fb ldr r3, [r7, #12]
8013bca: 00db lsls r3, r3, #3
8013bcc: 4413 add r3, r2
8013bce: 2200 movs r2, #0
8013bd0: 605a str r2, [r3, #4]
break;
8013bd2: e006 b.n 8013be2 <vQueueUnregisterQueue+0x62>
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
8013bd4: 68fb ldr r3, [r7, #12]
8013bd6: 3301 adds r3, #1
8013bd8: 60fb str r3, [r7, #12]
8013bda: 68fb ldr r3, [r7, #12]
8013bdc: 2b07 cmp r3, #7
8013bde: d9e5 bls.n 8013bac <vQueueUnregisterQueue+0x2c>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
8013be0: bf00 nop
8013be2: bf00 nop
8013be4: 3714 adds r7, #20
8013be6: 46bd mov sp, r7
8013be8: f85d 7b04 ldr.w r7, [sp], #4
8013bec: 4770 bx lr
8013bee: bf00 nop
8013bf0: 20002088 .word 0x20002088
08013bf4 <vQueueWaitForMessageRestricted>:
#if ( configUSE_TIMERS == 1 )
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
TickType_t xTicksToWait,
const BaseType_t xWaitIndefinitely )
{
8013bf4: b580 push {r7, lr}
8013bf6: b086 sub sp, #24
8013bf8: af00 add r7, sp, #0
8013bfa: 60f8 str r0, [r7, #12]
8013bfc: 60b9 str r1, [r7, #8]
8013bfe: 607a str r2, [r7, #4]
Queue_t * const pxQueue = xQueue;
8013c00: 68fb ldr r3, [r7, #12]
8013c02: 617b str r3, [r7, #20]
* will not actually cause the task to block, just place it on a blocked
* list. It will not block until the scheduler is unlocked - at which
* time a yield will be performed. If an item is added to the queue while
* the queue is locked, and the calling task blocks on the queue, then the
* calling task will be immediately unblocked when the queue is unlocked. */
prvLockQueue( pxQueue );
8013c04: f002 fb0c bl 8016220 <vPortEnterCritical>
8013c08: 697b ldr r3, [r7, #20]
8013c0a: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8013c0e: b25b sxtb r3, r3
8013c10: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8013c14: d103 bne.n 8013c1e <vQueueWaitForMessageRestricted+0x2a>
8013c16: 697b ldr r3, [r7, #20]
8013c18: 2200 movs r2, #0
8013c1a: f883 2044 strb.w r2, [r3, #68] @ 0x44
8013c1e: 697b ldr r3, [r7, #20]
8013c20: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
8013c24: b25b sxtb r3, r3
8013c26: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8013c2a: d103 bne.n 8013c34 <vQueueWaitForMessageRestricted+0x40>
8013c2c: 697b ldr r3, [r7, #20]
8013c2e: 2200 movs r2, #0
8013c30: f883 2045 strb.w r2, [r3, #69] @ 0x45
8013c34: f002 fb26 bl 8016284 <vPortExitCritical>
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
8013c38: 697b ldr r3, [r7, #20]
8013c3a: 6b9b ldr r3, [r3, #56] @ 0x38
8013c3c: 2b00 cmp r3, #0
8013c3e: d106 bne.n 8013c4e <vQueueWaitForMessageRestricted+0x5a>
{
/* There is nothing in the queue, block for the specified period. */
vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
8013c40: 697b ldr r3, [r7, #20]
8013c42: 3324 adds r3, #36 @ 0x24
8013c44: 687a ldr r2, [r7, #4]
8013c46: 68b9 ldr r1, [r7, #8]
8013c48: 4618 mov r0, r3
8013c4a: f000 fd45 bl 80146d8 <vTaskPlaceOnEventListRestricted>
else
{
mtCOVERAGE_TEST_MARKER();
}
prvUnlockQueue( pxQueue );
8013c4e: 6978 ldr r0, [r7, #20]
8013c50: f7ff fec6 bl 80139e0 <prvUnlockQueue>
}
8013c54: bf00 nop
8013c56: 3718 adds r7, #24
8013c58: 46bd mov sp, r7
8013c5a: bd80 pop {r7, pc}
08013c5c <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
8013c5c: b580 push {r7, lr}
8013c5e: b08e sub sp, #56 @ 0x38
8013c60: af04 add r7, sp, #16
8013c62: 60f8 str r0, [r7, #12]
8013c64: 60b9 str r1, [r7, #8]
8013c66: 607a str r2, [r7, #4]
8013c68: 603b str r3, [r7, #0]
TCB_t * pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
8013c6a: 6b7b ldr r3, [r7, #52] @ 0x34
8013c6c: 2b00 cmp r3, #0
8013c6e: d10b bne.n 8013c88 <xTaskCreateStatic+0x2c>
__asm volatile
8013c70: f04f 0350 mov.w r3, #80 @ 0x50
8013c74: f383 8811 msr BASEPRI, r3
8013c78: f3bf 8f6f isb sy
8013c7c: f3bf 8f4f dsb sy
8013c80: 623b str r3, [r7, #32]
}
8013c82: bf00 nop
8013c84: bf00 nop
8013c86: e7fd b.n 8013c84 <xTaskCreateStatic+0x28>
configASSERT( pxTaskBuffer != NULL );
8013c88: 6bbb ldr r3, [r7, #56] @ 0x38
8013c8a: 2b00 cmp r3, #0
8013c8c: d10b bne.n 8013ca6 <xTaskCreateStatic+0x4a>
__asm volatile
8013c8e: f04f 0350 mov.w r3, #80 @ 0x50
8013c92: f383 8811 msr BASEPRI, r3
8013c96: f3bf 8f6f isb sy
8013c9a: f3bf 8f4f dsb sy
8013c9e: 61fb str r3, [r7, #28]
}
8013ca0: bf00 nop
8013ca2: bf00 nop
8013ca4: e7fd b.n 8013ca2 <xTaskCreateStatic+0x46>
#if ( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
* variable of type StaticTask_t equals the size of the real task
* structure. */
volatile size_t xSize = sizeof( StaticTask_t );
8013ca6: 235c movs r3, #92 @ 0x5c
8013ca8: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
8013caa: 693b ldr r3, [r7, #16]
8013cac: 2b5c cmp r3, #92 @ 0x5c
8013cae: d00b beq.n 8013cc8 <xTaskCreateStatic+0x6c>
__asm volatile
8013cb0: f04f 0350 mov.w r3, #80 @ 0x50
8013cb4: f383 8811 msr BASEPRI, r3
8013cb8: f3bf 8f6f isb sy
8013cbc: f3bf 8f4f dsb sy
8013cc0: 61bb str r3, [r7, #24]
}
8013cc2: bf00 nop
8013cc4: bf00 nop
8013cc6: e7fd b.n 8013cc4 <xTaskCreateStatic+0x68>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
8013cc8: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
8013cca: 6bbb ldr r3, [r7, #56] @ 0x38
8013ccc: 2b00 cmp r3, #0
8013cce: d023 beq.n 8013d18 <xTaskCreateStatic+0xbc>
8013cd0: 6b7b ldr r3, [r7, #52] @ 0x34
8013cd2: 2b00 cmp r3, #0
8013cd4: d020 beq.n 8013d18 <xTaskCreateStatic+0xbc>
{
/* The memory used for the task's TCB and stack are passed into this
* function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
8013cd6: 6bbb ldr r3, [r7, #56] @ 0x38
8013cd8: 627b str r3, [r7, #36] @ 0x24
memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
8013cda: 225c movs r2, #92 @ 0x5c
8013cdc: 2100 movs r1, #0
8013cde: 6a78 ldr r0, [r7, #36] @ 0x24
8013ce0: f004 fe78 bl 80189d4 <memset>
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
8013ce4: 6a7b ldr r3, [r7, #36] @ 0x24
8013ce6: 6b7a ldr r2, [r7, #52] @ 0x34
8013ce8: 631a str r2, [r3, #48] @ 0x30
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
* task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
8013cea: 6a7b ldr r3, [r7, #36] @ 0x24
8013cec: 2202 movs r2, #2
8013cee: f883 2059 strb.w r2, [r3, #89] @ 0x59
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
8013cf2: 2300 movs r3, #0
8013cf4: 9303 str r3, [sp, #12]
8013cf6: 6a7b ldr r3, [r7, #36] @ 0x24
8013cf8: 9302 str r3, [sp, #8]
8013cfa: f107 0314 add.w r3, r7, #20
8013cfe: 9301 str r3, [sp, #4]
8013d00: 6b3b ldr r3, [r7, #48] @ 0x30
8013d02: 9300 str r3, [sp, #0]
8013d04: 683b ldr r3, [r7, #0]
8013d06: 687a ldr r2, [r7, #4]
8013d08: 68b9 ldr r1, [r7, #8]
8013d0a: 68f8 ldr r0, [r7, #12]
8013d0c: f000 f855 bl 8013dba <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
8013d10: 6a78 ldr r0, [r7, #36] @ 0x24
8013d12: f000 f8e3 bl 8013edc <prvAddNewTaskToReadyList>
8013d16: e001 b.n 8013d1c <xTaskCreateStatic+0xc0>
}
else
{
xReturn = NULL;
8013d18: 2300 movs r3, #0
8013d1a: 617b str r3, [r7, #20]
}
return xReturn;
8013d1c: 697b ldr r3, [r7, #20]
}
8013d1e: 4618 mov r0, r3
8013d20: 3728 adds r7, #40 @ 0x28
8013d22: 46bd mov sp, r7
8013d24: bd80 pop {r7, pc}
08013d26 <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
8013d26: b580 push {r7, lr}
8013d28: b08c sub sp, #48 @ 0x30
8013d2a: af04 add r7, sp, #16
8013d2c: 60f8 str r0, [r7, #12]
8013d2e: 60b9 str r1, [r7, #8]
8013d30: 603b str r3, [r7, #0]
8013d32: 4613 mov r3, r2
8013d34: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t * pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
8013d36: 88fb ldrh r3, [r7, #6]
8013d38: 009b lsls r3, r3, #2
8013d3a: 4618 mov r0, r3
8013d3c: f002 fb98 bl 8016470 <pvPortMalloc>
8013d40: 6178 str r0, [r7, #20]
if( pxStack != NULL )
8013d42: 697b ldr r3, [r7, #20]
8013d44: 2b00 cmp r3, #0
8013d46: d013 beq.n 8013d70 <xTaskCreate+0x4a>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
8013d48: 205c movs r0, #92 @ 0x5c
8013d4a: f002 fb91 bl 8016470 <pvPortMalloc>
8013d4e: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
8013d50: 69fb ldr r3, [r7, #28]
8013d52: 2b00 cmp r3, #0
8013d54: d008 beq.n 8013d68 <xTaskCreate+0x42>
{
memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
8013d56: 225c movs r2, #92 @ 0x5c
8013d58: 2100 movs r1, #0
8013d5a: 69f8 ldr r0, [r7, #28]
8013d5c: f004 fe3a bl 80189d4 <memset>
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
8013d60: 69fb ldr r3, [r7, #28]
8013d62: 697a ldr r2, [r7, #20]
8013d64: 631a str r2, [r3, #48] @ 0x30
8013d66: e005 b.n 8013d74 <xTaskCreate+0x4e>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
* it again. */
vPortFreeStack( pxStack );
8013d68: 6978 ldr r0, [r7, #20]
8013d6a: f002 fc4d bl 8016608 <vPortFree>
8013d6e: e001 b.n 8013d74 <xTaskCreate+0x4e>
}
}
else
{
pxNewTCB = NULL;
8013d70: 2300 movs r3, #0
8013d72: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
8013d74: 69fb ldr r3, [r7, #28]
8013d76: 2b00 cmp r3, #0
8013d78: d017 beq.n 8013daa <xTaskCreate+0x84>
{
#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
* task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
8013d7a: 69fb ldr r3, [r7, #28]
8013d7c: 2200 movs r2, #0
8013d7e: f883 2059 strb.w r2, [r3, #89] @ 0x59
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
8013d82: 88fa ldrh r2, [r7, #6]
8013d84: 2300 movs r3, #0
8013d86: 9303 str r3, [sp, #12]
8013d88: 69fb ldr r3, [r7, #28]
8013d8a: 9302 str r3, [sp, #8]
8013d8c: 6afb ldr r3, [r7, #44] @ 0x2c
8013d8e: 9301 str r3, [sp, #4]
8013d90: 6abb ldr r3, [r7, #40] @ 0x28
8013d92: 9300 str r3, [sp, #0]
8013d94: 683b ldr r3, [r7, #0]
8013d96: 68b9 ldr r1, [r7, #8]
8013d98: 68f8 ldr r0, [r7, #12]
8013d9a: f000 f80e bl 8013dba <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
8013d9e: 69f8 ldr r0, [r7, #28]
8013da0: f000 f89c bl 8013edc <prvAddNewTaskToReadyList>
xReturn = pdPASS;
8013da4: 2301 movs r3, #1
8013da6: 61bb str r3, [r7, #24]
8013da8: e002 b.n 8013db0 <xTaskCreate+0x8a>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
8013daa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8013dae: 61bb str r3, [r7, #24]
}
return xReturn;
8013db0: 69bb ldr r3, [r7, #24]
}
8013db2: 4618 mov r0, r3
8013db4: 3720 adds r7, #32
8013db6: 46bd mov sp, r7
8013db8: bd80 pop {r7, pc}
08013dba <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t * pxNewTCB,
const MemoryRegion_t * const xRegions )
{
8013dba: b580 push {r7, lr}
8013dbc: b088 sub sp, #32
8013dbe: af00 add r7, sp, #0
8013dc0: 60f8 str r0, [r7, #12]
8013dc2: 60b9 str r1, [r7, #8]
8013dc4: 607a str r2, [r7, #4]
8013dc6: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
8013dc8: 6b3b ldr r3, [r7, #48] @ 0x30
8013dca: 6b18 ldr r0, [r3, #48] @ 0x30
8013dcc: 687b ldr r3, [r7, #4]
8013dce: 009b lsls r3, r3, #2
8013dd0: 461a mov r2, r3
8013dd2: 21a5 movs r1, #165 @ 0xa5
8013dd4: f004 fdfe bl 80189d4 <memset>
* grows from high memory to low (as per the 80x86) or vice versa.
* portSTACK_GROWTH is used to make the result positive or negative as required
* by the port. */
#if ( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
8013dd8: 6b3b ldr r3, [r7, #48] @ 0x30
8013dda: 6b1a ldr r2, [r3, #48] @ 0x30
8013ddc: 687b ldr r3, [r7, #4]
8013dde: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000
8013de2: 3b01 subs r3, #1
8013de4: 009b lsls r3, r3, #2
8013de6: 4413 add r3, r2
8013de8: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
8013dea: 69bb ldr r3, [r7, #24]
8013dec: f023 0307 bic.w r3, r3, #7
8013df0: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
8013df2: 69bb ldr r3, [r7, #24]
8013df4: f003 0307 and.w r3, r3, #7
8013df8: 2b00 cmp r3, #0
8013dfa: d00b beq.n 8013e14 <prvInitialiseNewTask+0x5a>
__asm volatile
8013dfc: f04f 0350 mov.w r3, #80 @ 0x50
8013e00: f383 8811 msr BASEPRI, r3
8013e04: f3bf 8f6f isb sy
8013e08: f3bf 8f4f dsb sy
8013e0c: 617b str r3, [r7, #20]
}
8013e0e: bf00 nop
8013e10: bf00 nop
8013e12: e7fd b.n 8013e10 <prvInitialiseNewTask+0x56>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
8013e14: 68bb ldr r3, [r7, #8]
8013e16: 2b00 cmp r3, #0
8013e18: d01e beq.n 8013e58 <prvInitialiseNewTask+0x9e>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
8013e1a: 2300 movs r3, #0
8013e1c: 61fb str r3, [r7, #28]
8013e1e: e012 b.n 8013e46 <prvInitialiseNewTask+0x8c>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
8013e20: 68ba ldr r2, [r7, #8]
8013e22: 69fb ldr r3, [r7, #28]
8013e24: 4413 add r3, r2
8013e26: 7819 ldrb r1, [r3, #0]
8013e28: 6b3a ldr r2, [r7, #48] @ 0x30
8013e2a: 69fb ldr r3, [r7, #28]
8013e2c: 4413 add r3, r2
8013e2e: 3334 adds r3, #52 @ 0x34
8013e30: 460a mov r2, r1
8013e32: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
* configMAX_TASK_NAME_LEN characters just in case the memory after the
* string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
8013e34: 68ba ldr r2, [r7, #8]
8013e36: 69fb ldr r3, [r7, #28]
8013e38: 4413 add r3, r2
8013e3a: 781b ldrb r3, [r3, #0]
8013e3c: 2b00 cmp r3, #0
8013e3e: d006 beq.n 8013e4e <prvInitialiseNewTask+0x94>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
8013e40: 69fb ldr r3, [r7, #28]
8013e42: 3301 adds r3, #1
8013e44: 61fb str r3, [r7, #28]
8013e46: 69fb ldr r3, [r7, #28]
8013e48: 2b0f cmp r3, #15
8013e4a: d9e9 bls.n 8013e20 <prvInitialiseNewTask+0x66>
8013e4c: e000 b.n 8013e50 <prvInitialiseNewTask+0x96>
{
break;
8013e4e: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
* was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
8013e50: 6b3b ldr r3, [r7, #48] @ 0x30
8013e52: 2200 movs r2, #0
8013e54: f883 2043 strb.w r2, [r3, #67] @ 0x43
{
mtCOVERAGE_TEST_MARKER();
}
/* This is used as an array index so must ensure it's not too large. */
configASSERT( uxPriority < configMAX_PRIORITIES );
8013e58: 6abb ldr r3, [r7, #40] @ 0x28
8013e5a: 2b37 cmp r3, #55 @ 0x37
8013e5c: d90b bls.n 8013e76 <prvInitialiseNewTask+0xbc>
__asm volatile
8013e5e: f04f 0350 mov.w r3, #80 @ 0x50
8013e62: f383 8811 msr BASEPRI, r3
8013e66: f3bf 8f6f isb sy
8013e6a: f3bf 8f4f dsb sy
8013e6e: 613b str r3, [r7, #16]
}
8013e70: bf00 nop
8013e72: bf00 nop
8013e74: e7fd b.n 8013e72 <prvInitialiseNewTask+0xb8>
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
8013e76: 6abb ldr r3, [r7, #40] @ 0x28
8013e78: 2b37 cmp r3, #55 @ 0x37
8013e7a: d901 bls.n 8013e80 <prvInitialiseNewTask+0xc6>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
8013e7c: 2337 movs r3, #55 @ 0x37
8013e7e: 62bb str r3, [r7, #40] @ 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
8013e80: 6b3b ldr r3, [r7, #48] @ 0x30
8013e82: 6aba ldr r2, [r7, #40] @ 0x28
8013e84: 62da str r2, [r3, #44] @ 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
8013e86: 6b3b ldr r3, [r7, #48] @ 0x30
8013e88: 6aba ldr r2, [r7, #40] @ 0x28
8013e8a: 64da str r2, [r3, #76] @ 0x4c
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
8013e8c: 6b3b ldr r3, [r7, #48] @ 0x30
8013e8e: 3304 adds r3, #4
8013e90: 4618 mov r0, r3
8013e92: f7fe fd09 bl 80128a8 <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
8013e96: 6b3b ldr r3, [r7, #48] @ 0x30
8013e98: 3318 adds r3, #24
8013e9a: 4618 mov r0, r3
8013e9c: f7fe fd04 bl 80128a8 <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
* back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
8013ea0: 6b3b ldr r3, [r7, #48] @ 0x30
8013ea2: 6b3a ldr r2, [r7, #48] @ 0x30
8013ea4: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8013ea6: 6abb ldr r3, [r7, #40] @ 0x28
8013ea8: f1c3 0238 rsb r2, r3, #56 @ 0x38
8013eac: 6b3b ldr r3, [r7, #48] @ 0x30
8013eae: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
8013eb0: 6b3b ldr r3, [r7, #48] @ 0x30
8013eb2: 6b3a ldr r2, [r7, #48] @ 0x30
8013eb4: 625a str r2, [r3, #36] @ 0x24
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
8013eb6: 683a ldr r2, [r7, #0]
8013eb8: 68f9 ldr r1, [r7, #12]
8013eba: 69b8 ldr r0, [r7, #24]
8013ebc: f002 f866 bl 8015f8c <pxPortInitialiseStack>
8013ec0: 4602 mov r2, r0
8013ec2: 6b3b ldr r3, [r7, #48] @ 0x30
8013ec4: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
8013ec6: 6afb ldr r3, [r7, #44] @ 0x2c
8013ec8: 2b00 cmp r3, #0
8013eca: d002 beq.n 8013ed2 <prvInitialiseNewTask+0x118>
{
/* Pass the handle out in an anonymous way. The handle can be used to
* change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
8013ecc: 6afb ldr r3, [r7, #44] @ 0x2c
8013ece: 6b3a ldr r2, [r7, #48] @ 0x30
8013ed0: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8013ed2: bf00 nop
8013ed4: 3720 adds r7, #32
8013ed6: 46bd mov sp, r7
8013ed8: bd80 pop {r7, pc}
...
08013edc <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
{
8013edc: b580 push {r7, lr}
8013ede: b084 sub sp, #16
8013ee0: af00 add r7, sp, #0
8013ee2: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
* updated. */
taskENTER_CRITICAL();
8013ee4: f002 f99c bl 8016220 <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
8013ee8: 4b41 ldr r3, [pc, #260] @ (8013ff0 <prvAddNewTaskToReadyList+0x114>)
8013eea: 681b ldr r3, [r3, #0]
8013eec: 3301 adds r3, #1
8013eee: 4a40 ldr r2, [pc, #256] @ (8013ff0 <prvAddNewTaskToReadyList+0x114>)
8013ef0: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
8013ef2: 4b40 ldr r3, [pc, #256] @ (8013ff4 <prvAddNewTaskToReadyList+0x118>)
8013ef4: 681b ldr r3, [r3, #0]
8013ef6: 2b00 cmp r3, #0
8013ef8: d109 bne.n 8013f0e <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
* the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
8013efa: 4a3e ldr r2, [pc, #248] @ (8013ff4 <prvAddNewTaskToReadyList+0x118>)
8013efc: 687b ldr r3, [r7, #4]
8013efe: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
8013f00: 4b3b ldr r3, [pc, #236] @ (8013ff0 <prvAddNewTaskToReadyList+0x114>)
8013f02: 681b ldr r3, [r3, #0]
8013f04: 2b01 cmp r3, #1
8013f06: d110 bne.n 8013f2a <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
* initialisation required. We will not recover if this call
* fails, but we will report the failure. */
prvInitialiseTaskLists();
8013f08: f000 fda6 bl 8014a58 <prvInitialiseTaskLists>
8013f0c: e00d b.n 8013f2a <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
* current task if it is the highest priority task to be created
* so far. */
if( xSchedulerRunning == pdFALSE )
8013f0e: 4b3a ldr r3, [pc, #232] @ (8013ff8 <prvAddNewTaskToReadyList+0x11c>)
8013f10: 681b ldr r3, [r3, #0]
8013f12: 2b00 cmp r3, #0
8013f14: d109 bne.n 8013f2a <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
8013f16: 4b37 ldr r3, [pc, #220] @ (8013ff4 <prvAddNewTaskToReadyList+0x118>)
8013f18: 681b ldr r3, [r3, #0]
8013f1a: 6ada ldr r2, [r3, #44] @ 0x2c
8013f1c: 687b ldr r3, [r7, #4]
8013f1e: 6adb ldr r3, [r3, #44] @ 0x2c
8013f20: 429a cmp r2, r3
8013f22: d802 bhi.n 8013f2a <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
8013f24: 4a33 ldr r2, [pc, #204] @ (8013ff4 <prvAddNewTaskToReadyList+0x118>)
8013f26: 687b ldr r3, [r7, #4]
8013f28: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
8013f2a: 4b34 ldr r3, [pc, #208] @ (8013ffc <prvAddNewTaskToReadyList+0x120>)
8013f2c: 681b ldr r3, [r3, #0]
8013f2e: 3301 adds r3, #1
8013f30: 4a32 ldr r2, [pc, #200] @ (8013ffc <prvAddNewTaskToReadyList+0x120>)
8013f32: 6013 str r3, [r2, #0]
#if ( configUSE_TRACE_FACILITY == 1 )
{
/* Add a counter into the TCB for tracing only. */
pxNewTCB->uxTCBNumber = uxTaskNumber;
8013f34: 4b31 ldr r3, [pc, #196] @ (8013ffc <prvAddNewTaskToReadyList+0x120>)
8013f36: 681a ldr r2, [r3, #0]
8013f38: 687b ldr r3, [r7, #4]
8013f3a: 645a str r2, [r3, #68] @ 0x44
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
8013f3c: 687b ldr r3, [r7, #4]
8013f3e: 6ada ldr r2, [r3, #44] @ 0x2c
8013f40: 4b2f ldr r3, [pc, #188] @ (8014000 <prvAddNewTaskToReadyList+0x124>)
8013f42: 681b ldr r3, [r3, #0]
8013f44: 429a cmp r2, r3
8013f46: d903 bls.n 8013f50 <prvAddNewTaskToReadyList+0x74>
8013f48: 687b ldr r3, [r7, #4]
8013f4a: 6adb ldr r3, [r3, #44] @ 0x2c
8013f4c: 4a2c ldr r2, [pc, #176] @ (8014000 <prvAddNewTaskToReadyList+0x124>)
8013f4e: 6013 str r3, [r2, #0]
8013f50: 687b ldr r3, [r7, #4]
8013f52: 6ada ldr r2, [r3, #44] @ 0x2c
8013f54: 492b ldr r1, [pc, #172] @ (8014004 <prvAddNewTaskToReadyList+0x128>)
8013f56: 4613 mov r3, r2
8013f58: 009b lsls r3, r3, #2
8013f5a: 4413 add r3, r2
8013f5c: 009b lsls r3, r3, #2
8013f5e: 440b add r3, r1
8013f60: 3304 adds r3, #4
8013f62: 681b ldr r3, [r3, #0]
8013f64: 60fb str r3, [r7, #12]
8013f66: 687b ldr r3, [r7, #4]
8013f68: 68fa ldr r2, [r7, #12]
8013f6a: 609a str r2, [r3, #8]
8013f6c: 68fb ldr r3, [r7, #12]
8013f6e: 689a ldr r2, [r3, #8]
8013f70: 687b ldr r3, [r7, #4]
8013f72: 60da str r2, [r3, #12]
8013f74: 68fb ldr r3, [r7, #12]
8013f76: 689b ldr r3, [r3, #8]
8013f78: 687a ldr r2, [r7, #4]
8013f7a: 3204 adds r2, #4
8013f7c: 605a str r2, [r3, #4]
8013f7e: 687b ldr r3, [r7, #4]
8013f80: 1d1a adds r2, r3, #4
8013f82: 68fb ldr r3, [r7, #12]
8013f84: 609a str r2, [r3, #8]
8013f86: 687b ldr r3, [r7, #4]
8013f88: 6ada ldr r2, [r3, #44] @ 0x2c
8013f8a: 4613 mov r3, r2
8013f8c: 009b lsls r3, r3, #2
8013f8e: 4413 add r3, r2
8013f90: 009b lsls r3, r3, #2
8013f92: 4a1c ldr r2, [pc, #112] @ (8014004 <prvAddNewTaskToReadyList+0x128>)
8013f94: 441a add r2, r3
8013f96: 687b ldr r3, [r7, #4]
8013f98: 615a str r2, [r3, #20]
8013f9a: 687b ldr r3, [r7, #4]
8013f9c: 6ada ldr r2, [r3, #44] @ 0x2c
8013f9e: 4919 ldr r1, [pc, #100] @ (8014004 <prvAddNewTaskToReadyList+0x128>)
8013fa0: 4613 mov r3, r2
8013fa2: 009b lsls r3, r3, #2
8013fa4: 4413 add r3, r2
8013fa6: 009b lsls r3, r3, #2
8013fa8: 440b add r3, r1
8013faa: 681b ldr r3, [r3, #0]
8013fac: 1c59 adds r1, r3, #1
8013fae: 4815 ldr r0, [pc, #84] @ (8014004 <prvAddNewTaskToReadyList+0x128>)
8013fb0: 4613 mov r3, r2
8013fb2: 009b lsls r3, r3, #2
8013fb4: 4413 add r3, r2
8013fb6: 009b lsls r3, r3, #2
8013fb8: 4403 add r3, r0
8013fba: 6019 str r1, [r3, #0]
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
8013fbc: f002 f962 bl 8016284 <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
8013fc0: 4b0d ldr r3, [pc, #52] @ (8013ff8 <prvAddNewTaskToReadyList+0x11c>)
8013fc2: 681b ldr r3, [r3, #0]
8013fc4: 2b00 cmp r3, #0
8013fc6: d00e beq.n 8013fe6 <prvAddNewTaskToReadyList+0x10a>
{
/* If the created task is of a higher priority than the current task
* then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
8013fc8: 4b0a ldr r3, [pc, #40] @ (8013ff4 <prvAddNewTaskToReadyList+0x118>)
8013fca: 681b ldr r3, [r3, #0]
8013fcc: 6ada ldr r2, [r3, #44] @ 0x2c
8013fce: 687b ldr r3, [r7, #4]
8013fd0: 6adb ldr r3, [r3, #44] @ 0x2c
8013fd2: 429a cmp r2, r3
8013fd4: d207 bcs.n 8013fe6 <prvAddNewTaskToReadyList+0x10a>
{
taskYIELD_IF_USING_PREEMPTION();
8013fd6: 4b0c ldr r3, [pc, #48] @ (8014008 <prvAddNewTaskToReadyList+0x12c>)
8013fd8: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8013fdc: 601a str r2, [r3, #0]
8013fde: f3bf 8f4f dsb sy
8013fe2: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8013fe6: bf00 nop
8013fe8: 3710 adds r7, #16
8013fea: 46bd mov sp, r7
8013fec: bd80 pop {r7, pc}
8013fee: bf00 nop
8013ff0: 2000259c .word 0x2000259c
8013ff4: 200020c8 .word 0x200020c8
8013ff8: 200025a8 .word 0x200025a8
8013ffc: 200025b8 .word 0x200025b8
8014000: 200025a4 .word 0x200025a4
8014004: 200020cc .word 0x200020cc
8014008: e000ed04 .word 0xe000ed04
0801400c <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
801400c: b580 push {r7, lr}
801400e: b084 sub sp, #16
8014010: af00 add r7, sp, #0
8014012: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
8014014: 2300 movs r3, #0
8014016: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
8014018: 687b ldr r3, [r7, #4]
801401a: 2b00 cmp r3, #0
801401c: d018 beq.n 8014050 <vTaskDelay+0x44>
{
configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );
801401e: 4b14 ldr r3, [pc, #80] @ (8014070 <vTaskDelay+0x64>)
8014020: 681b ldr r3, [r3, #0]
8014022: 2b00 cmp r3, #0
8014024: d00b beq.n 801403e <vTaskDelay+0x32>
__asm volatile
8014026: f04f 0350 mov.w r3, #80 @ 0x50
801402a: f383 8811 msr BASEPRI, r3
801402e: f3bf 8f6f isb sy
8014032: f3bf 8f4f dsb sy
8014036: 60bb str r3, [r7, #8]
}
8014038: bf00 nop
801403a: bf00 nop
801403c: e7fd b.n 801403a <vTaskDelay+0x2e>
vTaskSuspendAll();
801403e: f000 f887 bl 8014150 <vTaskSuspendAll>
* list or removed from the blocked list until the scheduler
* is resumed.
*
* This task cannot be in an event list as it is the currently
* executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
8014042: 2100 movs r1, #0
8014044: 6878 ldr r0, [r7, #4]
8014046: f001 fc6b bl 8015920 <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
801404a: f000 f88f bl 801416c <xTaskResumeAll>
801404e: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
* have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
8014050: 68fb ldr r3, [r7, #12]
8014052: 2b00 cmp r3, #0
8014054: d107 bne.n 8014066 <vTaskDelay+0x5a>
{
portYIELD_WITHIN_API();
8014056: 4b07 ldr r3, [pc, #28] @ (8014074 <vTaskDelay+0x68>)
8014058: f04f 5280 mov.w r2, #268435456 @ 0x10000000
801405c: 601a str r2, [r3, #0]
801405e: f3bf 8f4f dsb sy
8014062: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8014066: bf00 nop
8014068: 3710 adds r7, #16
801406a: 46bd mov sp, r7
801406c: bd80 pop {r7, pc}
801406e: bf00 nop
8014070: 200025c4 .word 0x200025c4
8014074: e000ed04 .word 0xe000ed04
08014078 <vTaskStartScheduler>:
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
8014078: b580 push {r7, lr}
801407a: b08a sub sp, #40 @ 0x28
801407c: af04 add r7, sp, #16
BaseType_t xReturn;
/* Add the idle task at the lowest priority. */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t * pxIdleTaskTCBBuffer = NULL;
801407e: 2300 movs r3, #0
8014080: 60bb str r3, [r7, #8]
StackType_t * pxIdleTaskStackBuffer = NULL;
8014082: 2300 movs r3, #0
8014084: 607b str r3, [r7, #4]
uint32_t ulIdleTaskStackSize;
/* The Idle task is created using user provided RAM - obtain the
* address of the RAM then create the idle task. */
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
8014086: 463a mov r2, r7
8014088: 1d39 adds r1, r7, #4
801408a: f107 0308 add.w r3, r7, #8
801408e: 4618 mov r0, r3
8014090: f7fe fbb6 bl 8012800 <vApplicationGetIdleTaskMemory>
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
8014094: 6839 ldr r1, [r7, #0]
8014096: 687b ldr r3, [r7, #4]
8014098: 68ba ldr r2, [r7, #8]
801409a: 9202 str r2, [sp, #8]
801409c: 9301 str r3, [sp, #4]
801409e: 2300 movs r3, #0
80140a0: 9300 str r3, [sp, #0]
80140a2: 2300 movs r3, #0
80140a4: 460a mov r2, r1
80140a6: 4923 ldr r1, [pc, #140] @ (8014134 <vTaskStartScheduler+0xbc>)
80140a8: 4823 ldr r0, [pc, #140] @ (8014138 <vTaskStartScheduler+0xc0>)
80140aa: f7ff fdd7 bl 8013c5c <xTaskCreateStatic>
80140ae: 4603 mov r3, r0
80140b0: 4a22 ldr r2, [pc, #136] @ (801413c <vTaskStartScheduler+0xc4>)
80140b2: 6013 str r3, [r2, #0]
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
if( xIdleTaskHandle != NULL )
80140b4: 4b21 ldr r3, [pc, #132] @ (801413c <vTaskStartScheduler+0xc4>)
80140b6: 681b ldr r3, [r3, #0]
80140b8: 2b00 cmp r3, #0
80140ba: d002 beq.n 80140c2 <vTaskStartScheduler+0x4a>
{
xReturn = pdPASS;
80140bc: 2301 movs r3, #1
80140be: 617b str r3, [r7, #20]
80140c0: e001 b.n 80140c6 <vTaskStartScheduler+0x4e>
}
else
{
xReturn = pdFAIL;
80140c2: 2300 movs r3, #0
80140c4: 617b str r3, [r7, #20]
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
#if ( configUSE_TIMERS == 1 )
{
if( xReturn == pdPASS )
80140c6: 697b ldr r3, [r7, #20]
80140c8: 2b01 cmp r3, #1
80140ca: d102 bne.n 80140d2 <vTaskStartScheduler+0x5a>
{
xReturn = xTimerCreateTimerTask();
80140cc: f001 fc96 bl 80159fc <xTimerCreateTimerTask>
80140d0: 6178 str r0, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
80140d2: 697b ldr r3, [r7, #20]
80140d4: 2b01 cmp r3, #1
80140d6: d116 bne.n 8014106 <vTaskStartScheduler+0x8e>
__asm volatile
80140d8: f04f 0350 mov.w r3, #80 @ 0x50
80140dc: f383 8811 msr BASEPRI, r3
80140e0: f3bf 8f6f isb sy
80140e4: f3bf 8f4f dsb sy
80140e8: 613b str r3, [r7, #16]
}
80140ea: bf00 nop
* block specific to the task that will run first. */
configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
}
#endif
xNextTaskUnblockTime = portMAX_DELAY;
80140ec: 4b14 ldr r3, [pc, #80] @ (8014140 <vTaskStartScheduler+0xc8>)
80140ee: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80140f2: 601a str r2, [r3, #0]
xSchedulerRunning = pdTRUE;
80140f4: 4b13 ldr r3, [pc, #76] @ (8014144 <vTaskStartScheduler+0xcc>)
80140f6: 2201 movs r2, #1
80140f8: 601a str r2, [r3, #0]
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
80140fa: 4b13 ldr r3, [pc, #76] @ (8014148 <vTaskStartScheduler+0xd0>)
80140fc: 2200 movs r2, #0
80140fe: 601a str r2, [r3, #0]
traceTASK_SWITCHED_IN();
/* Setting up the timer tick is hardware specific and thus in the
* portable interface. */
xPortStartScheduler();
8014100: f001 ffd0 bl 80160a4 <xPortStartScheduler>
8014104: e00f b.n 8014126 <vTaskStartScheduler+0xae>
else
{
/* This line will only be reached if the kernel could not be started,
* because there was not enough FreeRTOS heap to create the idle task
* or the timer task. */
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
8014106: 697b ldr r3, [r7, #20]
8014108: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
801410c: d10b bne.n 8014126 <vTaskStartScheduler+0xae>
__asm volatile
801410e: f04f 0350 mov.w r3, #80 @ 0x50
8014112: f383 8811 msr BASEPRI, r3
8014116: f3bf 8f6f isb sy
801411a: f3bf 8f4f dsb sy
801411e: 60fb str r3, [r7, #12]
}
8014120: bf00 nop
8014122: bf00 nop
8014124: e7fd b.n 8014122 <vTaskStartScheduler+0xaa>
* meaning xIdleTaskHandle is not used anywhere else. */
( void ) xIdleTaskHandle;
/* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
* from getting optimized out as it is no longer used by the kernel. */
( void ) uxTopUsedPriority;
8014126: 4b09 ldr r3, [pc, #36] @ (801414c <vTaskStartScheduler+0xd4>)
8014128: 681b ldr r3, [r3, #0]
}
801412a: bf00 nop
801412c: 3718 adds r7, #24
801412e: 46bd mov sp, r7
8014130: bd80 pop {r7, pc}
8014132: bf00 nop
8014134: 0801c4c8 .word 0x0801c4c8
8014138: 08014a29 .word 0x08014a29
801413c: 200025c0 .word 0x200025c0
8014140: 200025bc .word 0x200025bc
8014144: 200025a8 .word 0x200025a8
8014148: 200025a0 .word 0x200025a0
801414c: 0801c7b8 .word 0x0801c7b8
08014150 <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
8014150: b480 push {r7}
8014152: af00 add r7, sp, #0
* do not otherwise exhibit real time behaviour. */
portSOFTWARE_BARRIER();
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
* is used to allow calls to vTaskSuspendAll() to nest. */
++uxSchedulerSuspended;
8014154: 4b04 ldr r3, [pc, #16] @ (8014168 <vTaskSuspendAll+0x18>)
8014156: 681b ldr r3, [r3, #0]
8014158: 3301 adds r3, #1
801415a: 4a03 ldr r2, [pc, #12] @ (8014168 <vTaskSuspendAll+0x18>)
801415c: 6013 str r3, [r2, #0]
/* Enforces ordering for ports and optimised compilers that may otherwise place
* the above increment elsewhere. */
portMEMORY_BARRIER();
}
801415e: bf00 nop
8014160: 46bd mov sp, r7
8014162: f85d 7b04 ldr.w r7, [sp], #4
8014166: 4770 bx lr
8014168: 200025c4 .word 0x200025c4
0801416c <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
801416c: b580 push {r7, lr}
801416e: b088 sub sp, #32
8014170: af00 add r7, sp, #0
TCB_t * pxTCB = NULL;
8014172: 2300 movs r3, #0
8014174: 61fb str r3, [r7, #28]
BaseType_t xAlreadyYielded = pdFALSE;
8014176: 2300 movs r3, #0
8014178: 61bb str r3, [r7, #24]
/* If uxSchedulerSuspended is zero then this function does not match a
* previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
801417a: 4b72 ldr r3, [pc, #456] @ (8014344 <xTaskResumeAll+0x1d8>)
801417c: 681b ldr r3, [r3, #0]
801417e: 2b00 cmp r3, #0
8014180: d10b bne.n 801419a <xTaskResumeAll+0x2e>
__asm volatile
8014182: f04f 0350 mov.w r3, #80 @ 0x50
8014186: f383 8811 msr BASEPRI, r3
801418a: f3bf 8f6f isb sy
801418e: f3bf 8f4f dsb sy
8014192: 607b str r3, [r7, #4]
}
8014194: bf00 nop
8014196: bf00 nop
8014198: e7fd b.n 8014196 <xTaskResumeAll+0x2a>
/* It is possible that an ISR caused a task to be removed from an event
* list while the scheduler was suspended. If this was the case then the
* removed task will have been added to the xPendingReadyList. Once the
* scheduler has been resumed it is safe to move all the pending ready
* tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
801419a: f002 f841 bl 8016220 <vPortEnterCritical>
{
--uxSchedulerSuspended;
801419e: 4b69 ldr r3, [pc, #420] @ (8014344 <xTaskResumeAll+0x1d8>)
80141a0: 681b ldr r3, [r3, #0]
80141a2: 3b01 subs r3, #1
80141a4: 4a67 ldr r2, [pc, #412] @ (8014344 <xTaskResumeAll+0x1d8>)
80141a6: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
80141a8: 4b66 ldr r3, [pc, #408] @ (8014344 <xTaskResumeAll+0x1d8>)
80141aa: 681b ldr r3, [r3, #0]
80141ac: 2b00 cmp r3, #0
80141ae: f040 80c1 bne.w 8014334 <xTaskResumeAll+0x1c8>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
80141b2: 4b65 ldr r3, [pc, #404] @ (8014348 <xTaskResumeAll+0x1dc>)
80141b4: 681b ldr r3, [r3, #0]
80141b6: 2b00 cmp r3, #0
80141b8: f000 80bc beq.w 8014334 <xTaskResumeAll+0x1c8>
{
/* Move any readied tasks from the pending list into the
* appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
80141bc: e08b b.n 80142d6 <xTaskResumeAll+0x16a>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
80141be: 4b63 ldr r3, [pc, #396] @ (801434c <xTaskResumeAll+0x1e0>)
80141c0: 68db ldr r3, [r3, #12]
80141c2: 68db ldr r3, [r3, #12]
80141c4: 61fb str r3, [r7, #28]
listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
80141c6: 69fb ldr r3, [r7, #28]
80141c8: 6a9b ldr r3, [r3, #40] @ 0x28
80141ca: 613b str r3, [r7, #16]
80141cc: 69fb ldr r3, [r7, #28]
80141ce: 69db ldr r3, [r3, #28]
80141d0: 69fa ldr r2, [r7, #28]
80141d2: 6a12 ldr r2, [r2, #32]
80141d4: 609a str r2, [r3, #8]
80141d6: 69fb ldr r3, [r7, #28]
80141d8: 6a1b ldr r3, [r3, #32]
80141da: 69fa ldr r2, [r7, #28]
80141dc: 69d2 ldr r2, [r2, #28]
80141de: 605a str r2, [r3, #4]
80141e0: 693b ldr r3, [r7, #16]
80141e2: 685a ldr r2, [r3, #4]
80141e4: 69fb ldr r3, [r7, #28]
80141e6: 3318 adds r3, #24
80141e8: 429a cmp r2, r3
80141ea: d103 bne.n 80141f4 <xTaskResumeAll+0x88>
80141ec: 69fb ldr r3, [r7, #28]
80141ee: 6a1a ldr r2, [r3, #32]
80141f0: 693b ldr r3, [r7, #16]
80141f2: 605a str r2, [r3, #4]
80141f4: 69fb ldr r3, [r7, #28]
80141f6: 2200 movs r2, #0
80141f8: 629a str r2, [r3, #40] @ 0x28
80141fa: 693b ldr r3, [r7, #16]
80141fc: 681b ldr r3, [r3, #0]
80141fe: 1e5a subs r2, r3, #1
8014200: 693b ldr r3, [r7, #16]
8014202: 601a str r2, [r3, #0]
portMEMORY_BARRIER();
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
8014204: 69fb ldr r3, [r7, #28]
8014206: 695b ldr r3, [r3, #20]
8014208: 60fb str r3, [r7, #12]
801420a: 69fb ldr r3, [r7, #28]
801420c: 689b ldr r3, [r3, #8]
801420e: 69fa ldr r2, [r7, #28]
8014210: 68d2 ldr r2, [r2, #12]
8014212: 609a str r2, [r3, #8]
8014214: 69fb ldr r3, [r7, #28]
8014216: 68db ldr r3, [r3, #12]
8014218: 69fa ldr r2, [r7, #28]
801421a: 6892 ldr r2, [r2, #8]
801421c: 605a str r2, [r3, #4]
801421e: 68fb ldr r3, [r7, #12]
8014220: 685a ldr r2, [r3, #4]
8014222: 69fb ldr r3, [r7, #28]
8014224: 3304 adds r3, #4
8014226: 429a cmp r2, r3
8014228: d103 bne.n 8014232 <xTaskResumeAll+0xc6>
801422a: 69fb ldr r3, [r7, #28]
801422c: 68da ldr r2, [r3, #12]
801422e: 68fb ldr r3, [r7, #12]
8014230: 605a str r2, [r3, #4]
8014232: 69fb ldr r3, [r7, #28]
8014234: 2200 movs r2, #0
8014236: 615a str r2, [r3, #20]
8014238: 68fb ldr r3, [r7, #12]
801423a: 681b ldr r3, [r3, #0]
801423c: 1e5a subs r2, r3, #1
801423e: 68fb ldr r3, [r7, #12]
8014240: 601a str r2, [r3, #0]
prvAddTaskToReadyList( pxTCB );
8014242: 69fb ldr r3, [r7, #28]
8014244: 6ada ldr r2, [r3, #44] @ 0x2c
8014246: 4b42 ldr r3, [pc, #264] @ (8014350 <xTaskResumeAll+0x1e4>)
8014248: 681b ldr r3, [r3, #0]
801424a: 429a cmp r2, r3
801424c: d903 bls.n 8014256 <xTaskResumeAll+0xea>
801424e: 69fb ldr r3, [r7, #28]
8014250: 6adb ldr r3, [r3, #44] @ 0x2c
8014252: 4a3f ldr r2, [pc, #252] @ (8014350 <xTaskResumeAll+0x1e4>)
8014254: 6013 str r3, [r2, #0]
8014256: 69fb ldr r3, [r7, #28]
8014258: 6ada ldr r2, [r3, #44] @ 0x2c
801425a: 493e ldr r1, [pc, #248] @ (8014354 <xTaskResumeAll+0x1e8>)
801425c: 4613 mov r3, r2
801425e: 009b lsls r3, r3, #2
8014260: 4413 add r3, r2
8014262: 009b lsls r3, r3, #2
8014264: 440b add r3, r1
8014266: 3304 adds r3, #4
8014268: 681b ldr r3, [r3, #0]
801426a: 60bb str r3, [r7, #8]
801426c: 69fb ldr r3, [r7, #28]
801426e: 68ba ldr r2, [r7, #8]
8014270: 609a str r2, [r3, #8]
8014272: 68bb ldr r3, [r7, #8]
8014274: 689a ldr r2, [r3, #8]
8014276: 69fb ldr r3, [r7, #28]
8014278: 60da str r2, [r3, #12]
801427a: 68bb ldr r3, [r7, #8]
801427c: 689b ldr r3, [r3, #8]
801427e: 69fa ldr r2, [r7, #28]
8014280: 3204 adds r2, #4
8014282: 605a str r2, [r3, #4]
8014284: 69fb ldr r3, [r7, #28]
8014286: 1d1a adds r2, r3, #4
8014288: 68bb ldr r3, [r7, #8]
801428a: 609a str r2, [r3, #8]
801428c: 69fb ldr r3, [r7, #28]
801428e: 6ada ldr r2, [r3, #44] @ 0x2c
8014290: 4613 mov r3, r2
8014292: 009b lsls r3, r3, #2
8014294: 4413 add r3, r2
8014296: 009b lsls r3, r3, #2
8014298: 4a2e ldr r2, [pc, #184] @ (8014354 <xTaskResumeAll+0x1e8>)
801429a: 441a add r2, r3
801429c: 69fb ldr r3, [r7, #28]
801429e: 615a str r2, [r3, #20]
80142a0: 69fb ldr r3, [r7, #28]
80142a2: 6ada ldr r2, [r3, #44] @ 0x2c
80142a4: 492b ldr r1, [pc, #172] @ (8014354 <xTaskResumeAll+0x1e8>)
80142a6: 4613 mov r3, r2
80142a8: 009b lsls r3, r3, #2
80142aa: 4413 add r3, r2
80142ac: 009b lsls r3, r3, #2
80142ae: 440b add r3, r1
80142b0: 681b ldr r3, [r3, #0]
80142b2: 1c59 adds r1, r3, #1
80142b4: 4827 ldr r0, [pc, #156] @ (8014354 <xTaskResumeAll+0x1e8>)
80142b6: 4613 mov r3, r2
80142b8: 009b lsls r3, r3, #2
80142ba: 4413 add r3, r2
80142bc: 009b lsls r3, r3, #2
80142be: 4403 add r3, r0
80142c0: 6019 str r1, [r3, #0]
/* If the moved task has a priority higher than the current
* task then a yield must be performed. */
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
80142c2: 69fb ldr r3, [r7, #28]
80142c4: 6ada ldr r2, [r3, #44] @ 0x2c
80142c6: 4b24 ldr r3, [pc, #144] @ (8014358 <xTaskResumeAll+0x1ec>)
80142c8: 681b ldr r3, [r3, #0]
80142ca: 6adb ldr r3, [r3, #44] @ 0x2c
80142cc: 429a cmp r2, r3
80142ce: d902 bls.n 80142d6 <xTaskResumeAll+0x16a>
{
xYieldPending = pdTRUE;
80142d0: 4b22 ldr r3, [pc, #136] @ (801435c <xTaskResumeAll+0x1f0>)
80142d2: 2201 movs r2, #1
80142d4: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
80142d6: 4b1d ldr r3, [pc, #116] @ (801434c <xTaskResumeAll+0x1e0>)
80142d8: 681b ldr r3, [r3, #0]
80142da: 2b00 cmp r3, #0
80142dc: f47f af6f bne.w 80141be <xTaskResumeAll+0x52>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
80142e0: 69fb ldr r3, [r7, #28]
80142e2: 2b00 cmp r3, #0
80142e4: d001 beq.n 80142ea <xTaskResumeAll+0x17e>
* which may have prevented the next unblock time from being
* re-calculated, in which case re-calculate it now. Mainly
* important for low power tickless implementations, where
* this can prevent an unnecessary exit from low power
* state. */
prvResetNextTaskUnblockTime();
80142e6: f000 fc55 bl 8014b94 <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
* they should be processed now. This ensures the tick count does
* not slip, and that any delayed tasks are resumed at the correct
* time. */
{
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
80142ea: 4b1d ldr r3, [pc, #116] @ (8014360 <xTaskResumeAll+0x1f4>)
80142ec: 681b ldr r3, [r3, #0]
80142ee: 617b str r3, [r7, #20]
if( xPendedCounts > ( TickType_t ) 0U )
80142f0: 697b ldr r3, [r7, #20]
80142f2: 2b00 cmp r3, #0
80142f4: d010 beq.n 8014318 <xTaskResumeAll+0x1ac>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
80142f6: f000 f853 bl 80143a0 <xTaskIncrementTick>
80142fa: 4603 mov r3, r0
80142fc: 2b00 cmp r3, #0
80142fe: d002 beq.n 8014306 <xTaskResumeAll+0x19a>
{
xYieldPending = pdTRUE;
8014300: 4b16 ldr r3, [pc, #88] @ (801435c <xTaskResumeAll+0x1f0>)
8014302: 2201 movs r2, #1
8014304: 601a str r2, [r3, #0]
else
{
mtCOVERAGE_TEST_MARKER();
}
--xPendedCounts;
8014306: 697b ldr r3, [r7, #20]
8014308: 3b01 subs r3, #1
801430a: 617b str r3, [r7, #20]
} while( xPendedCounts > ( TickType_t ) 0U );
801430c: 697b ldr r3, [r7, #20]
801430e: 2b00 cmp r3, #0
8014310: d1f1 bne.n 80142f6 <xTaskResumeAll+0x18a>
xPendedTicks = 0;
8014312: 4b13 ldr r3, [pc, #76] @ (8014360 <xTaskResumeAll+0x1f4>)
8014314: 2200 movs r2, #0
8014316: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
8014318: 4b10 ldr r3, [pc, #64] @ (801435c <xTaskResumeAll+0x1f0>)
801431a: 681b ldr r3, [r3, #0]
801431c: 2b00 cmp r3, #0
801431e: d009 beq.n 8014334 <xTaskResumeAll+0x1c8>
{
#if ( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
8014320: 2301 movs r3, #1
8014322: 61bb str r3, [r7, #24]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
8014324: 4b0f ldr r3, [pc, #60] @ (8014364 <xTaskResumeAll+0x1f8>)
8014326: f04f 5280 mov.w r2, #268435456 @ 0x10000000
801432a: 601a str r2, [r3, #0]
801432c: f3bf 8f4f dsb sy
8014330: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8014334: f001 ffa6 bl 8016284 <vPortExitCritical>
return xAlreadyYielded;
8014338: 69bb ldr r3, [r7, #24]
}
801433a: 4618 mov r0, r3
801433c: 3720 adds r7, #32
801433e: 46bd mov sp, r7
8014340: bd80 pop {r7, pc}
8014342: bf00 nop
8014344: 200025c4 .word 0x200025c4
8014348: 2000259c .word 0x2000259c
801434c: 2000255c .word 0x2000255c
8014350: 200025a4 .word 0x200025a4
8014354: 200020cc .word 0x200020cc
8014358: 200020c8 .word 0x200020c8
801435c: 200025b0 .word 0x200025b0
8014360: 200025ac .word 0x200025ac
8014364: e000ed04 .word 0xe000ed04
08014368 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCount( void )
{
8014368: b480 push {r7}
801436a: b083 sub sp, #12
801436c: af00 add r7, sp, #0
TickType_t xTicks;
/* Critical section required if running on a 16 bit processor. */
portTICK_TYPE_ENTER_CRITICAL();
{
xTicks = xTickCount;
801436e: 4b05 ldr r3, [pc, #20] @ (8014384 <xTaskGetTickCount+0x1c>)
8014370: 681b ldr r3, [r3, #0]
8014372: 607b str r3, [r7, #4]
}
portTICK_TYPE_EXIT_CRITICAL();
return xTicks;
8014374: 687b ldr r3, [r7, #4]
}
8014376: 4618 mov r0, r3
8014378: 370c adds r7, #12
801437a: 46bd mov sp, r7
801437c: f85d 7b04 ldr.w r7, [sp], #4
8014380: 4770 bx lr
8014382: bf00 nop
8014384: 200025a0 .word 0x200025a0
08014388 <uxTaskGetNumberOfTasks>:
return xReturn;
}
/*-----------------------------------------------------------*/
UBaseType_t uxTaskGetNumberOfTasks( void )
{
8014388: b480 push {r7}
801438a: af00 add r7, sp, #0
/* A critical section is not required because the variables are of type
* BaseType_t. */
return uxCurrentNumberOfTasks;
801438c: 4b03 ldr r3, [pc, #12] @ (801439c <uxTaskGetNumberOfTasks+0x14>)
801438e: 681b ldr r3, [r3, #0]
}
8014390: 4618 mov r0, r3
8014392: 46bd mov sp, r7
8014394: f85d 7b04 ldr.w r7, [sp], #4
8014398: 4770 bx lr
801439a: bf00 nop
801439c: 2000259c .word 0x2000259c
080143a0 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
80143a0: b580 push {r7, lr}
80143a2: b08a sub sp, #40 @ 0x28
80143a4: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
80143a6: 2300 movs r3, #0
80143a8: 627b str r3, [r7, #36] @ 0x24
/* Called by the portable layer each time a tick interrupt occurs.
* Increments the tick then checks to see if the new tick value will cause any
* tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
80143aa: 4b7e ldr r3, [pc, #504] @ (80145a4 <xTaskIncrementTick+0x204>)
80143ac: 681b ldr r3, [r3, #0]
80143ae: 2b00 cmp r3, #0
80143b0: f040 80ee bne.w 8014590 <xTaskIncrementTick+0x1f0>
{
/* Minor optimisation. The tick count cannot change in this
* block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
80143b4: 4b7c ldr r3, [pc, #496] @ (80145a8 <xTaskIncrementTick+0x208>)
80143b6: 681b ldr r3, [r3, #0]
80143b8: 3301 adds r3, #1
80143ba: 623b str r3, [r7, #32]
/* Increment the RTOS tick, switching the delayed and overflowed
* delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
80143bc: 4a7a ldr r2, [pc, #488] @ (80145a8 <xTaskIncrementTick+0x208>)
80143be: 6a3b ldr r3, [r7, #32]
80143c0: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
80143c2: 6a3b ldr r3, [r7, #32]
80143c4: 2b00 cmp r3, #0
80143c6: d121 bne.n 801440c <xTaskIncrementTick+0x6c>
{
taskSWITCH_DELAYED_LISTS();
80143c8: 4b78 ldr r3, [pc, #480] @ (80145ac <xTaskIncrementTick+0x20c>)
80143ca: 681b ldr r3, [r3, #0]
80143cc: 681b ldr r3, [r3, #0]
80143ce: 2b00 cmp r3, #0
80143d0: d00b beq.n 80143ea <xTaskIncrementTick+0x4a>
__asm volatile
80143d2: f04f 0350 mov.w r3, #80 @ 0x50
80143d6: f383 8811 msr BASEPRI, r3
80143da: f3bf 8f6f isb sy
80143de: f3bf 8f4f dsb sy
80143e2: 607b str r3, [r7, #4]
}
80143e4: bf00 nop
80143e6: bf00 nop
80143e8: e7fd b.n 80143e6 <xTaskIncrementTick+0x46>
80143ea: 4b70 ldr r3, [pc, #448] @ (80145ac <xTaskIncrementTick+0x20c>)
80143ec: 681b ldr r3, [r3, #0]
80143ee: 61fb str r3, [r7, #28]
80143f0: 4b6f ldr r3, [pc, #444] @ (80145b0 <xTaskIncrementTick+0x210>)
80143f2: 681b ldr r3, [r3, #0]
80143f4: 4a6d ldr r2, [pc, #436] @ (80145ac <xTaskIncrementTick+0x20c>)
80143f6: 6013 str r3, [r2, #0]
80143f8: 4a6d ldr r2, [pc, #436] @ (80145b0 <xTaskIncrementTick+0x210>)
80143fa: 69fb ldr r3, [r7, #28]
80143fc: 6013 str r3, [r2, #0]
80143fe: 4b6d ldr r3, [pc, #436] @ (80145b4 <xTaskIncrementTick+0x214>)
8014400: 681b ldr r3, [r3, #0]
8014402: 3301 adds r3, #1
8014404: 4a6b ldr r2, [pc, #428] @ (80145b4 <xTaskIncrementTick+0x214>)
8014406: 6013 str r3, [r2, #0]
8014408: f000 fbc4 bl 8014b94 <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
* the queue in the order of their wake time - meaning once one task
* has been found whose block time has not expired there is no need to
* look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
801440c: 4b6a ldr r3, [pc, #424] @ (80145b8 <xTaskIncrementTick+0x218>)
801440e: 681b ldr r3, [r3, #0]
8014410: 6a3a ldr r2, [r7, #32]
8014412: 429a cmp r2, r3
8014414: f0c0 80a7 bcc.w 8014566 <xTaskIncrementTick+0x1c6>
{
for( ; ; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8014418: 4b64 ldr r3, [pc, #400] @ (80145ac <xTaskIncrementTick+0x20c>)
801441a: 681b ldr r3, [r3, #0]
801441c: 681b ldr r3, [r3, #0]
801441e: 2b00 cmp r3, #0
8014420: d104 bne.n 801442c <xTaskIncrementTick+0x8c>
/* The delayed list is empty. Set xNextTaskUnblockTime
* to the maximum possible value so it is extremely
* unlikely that the
* if( xTickCount >= xNextTaskUnblockTime ) test will pass
* next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8014422: 4b65 ldr r3, [pc, #404] @ (80145b8 <xTaskIncrementTick+0x218>)
8014424: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8014428: 601a str r2, [r3, #0]
break;
801442a: e09c b.n 8014566 <xTaskIncrementTick+0x1c6>
{
/* The delayed list is not empty, get the value of the
* item at the head of the delayed list. This is the time
* at which the task at the head of the delayed list must
* be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
801442c: 4b5f ldr r3, [pc, #380] @ (80145ac <xTaskIncrementTick+0x20c>)
801442e: 681b ldr r3, [r3, #0]
8014430: 68db ldr r3, [r3, #12]
8014432: 68db ldr r3, [r3, #12]
8014434: 61bb str r3, [r7, #24]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
8014436: 69bb ldr r3, [r7, #24]
8014438: 685b ldr r3, [r3, #4]
801443a: 617b str r3, [r7, #20]
if( xConstTickCount < xItemValue )
801443c: 6a3a ldr r2, [r7, #32]
801443e: 697b ldr r3, [r7, #20]
8014440: 429a cmp r2, r3
8014442: d203 bcs.n 801444c <xTaskIncrementTick+0xac>
/* It is not time to unblock this item yet, but the
* item value is the time at which the task at the head
* of the blocked list must be removed from the Blocked
* state - so record the item value in
* xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
8014444: 4a5c ldr r2, [pc, #368] @ (80145b8 <xTaskIncrementTick+0x218>)
8014446: 697b ldr r3, [r7, #20]
8014448: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */
801444a: e08c b.n 8014566 <xTaskIncrementTick+0x1c6>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
801444c: 69bb ldr r3, [r7, #24]
801444e: 695b ldr r3, [r3, #20]
8014450: 613b str r3, [r7, #16]
8014452: 69bb ldr r3, [r7, #24]
8014454: 689b ldr r3, [r3, #8]
8014456: 69ba ldr r2, [r7, #24]
8014458: 68d2 ldr r2, [r2, #12]
801445a: 609a str r2, [r3, #8]
801445c: 69bb ldr r3, [r7, #24]
801445e: 68db ldr r3, [r3, #12]
8014460: 69ba ldr r2, [r7, #24]
8014462: 6892 ldr r2, [r2, #8]
8014464: 605a str r2, [r3, #4]
8014466: 693b ldr r3, [r7, #16]
8014468: 685a ldr r2, [r3, #4]
801446a: 69bb ldr r3, [r7, #24]
801446c: 3304 adds r3, #4
801446e: 429a cmp r2, r3
8014470: d103 bne.n 801447a <xTaskIncrementTick+0xda>
8014472: 69bb ldr r3, [r7, #24]
8014474: 68da ldr r2, [r3, #12]
8014476: 693b ldr r3, [r7, #16]
8014478: 605a str r2, [r3, #4]
801447a: 69bb ldr r3, [r7, #24]
801447c: 2200 movs r2, #0
801447e: 615a str r2, [r3, #20]
8014480: 693b ldr r3, [r7, #16]
8014482: 681b ldr r3, [r3, #0]
8014484: 1e5a subs r2, r3, #1
8014486: 693b ldr r3, [r7, #16]
8014488: 601a str r2, [r3, #0]
/* Is the task waiting on an event also? If so remove
* it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
801448a: 69bb ldr r3, [r7, #24]
801448c: 6a9b ldr r3, [r3, #40] @ 0x28
801448e: 2b00 cmp r3, #0
8014490: d01e beq.n 80144d0 <xTaskIncrementTick+0x130>
{
listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
8014492: 69bb ldr r3, [r7, #24]
8014494: 6a9b ldr r3, [r3, #40] @ 0x28
8014496: 60fb str r3, [r7, #12]
8014498: 69bb ldr r3, [r7, #24]
801449a: 69db ldr r3, [r3, #28]
801449c: 69ba ldr r2, [r7, #24]
801449e: 6a12 ldr r2, [r2, #32]
80144a0: 609a str r2, [r3, #8]
80144a2: 69bb ldr r3, [r7, #24]
80144a4: 6a1b ldr r3, [r3, #32]
80144a6: 69ba ldr r2, [r7, #24]
80144a8: 69d2 ldr r2, [r2, #28]
80144aa: 605a str r2, [r3, #4]
80144ac: 68fb ldr r3, [r7, #12]
80144ae: 685a ldr r2, [r3, #4]
80144b0: 69bb ldr r3, [r7, #24]
80144b2: 3318 adds r3, #24
80144b4: 429a cmp r2, r3
80144b6: d103 bne.n 80144c0 <xTaskIncrementTick+0x120>
80144b8: 69bb ldr r3, [r7, #24]
80144ba: 6a1a ldr r2, [r3, #32]
80144bc: 68fb ldr r3, [r7, #12]
80144be: 605a str r2, [r3, #4]
80144c0: 69bb ldr r3, [r7, #24]
80144c2: 2200 movs r2, #0
80144c4: 629a str r2, [r3, #40] @ 0x28
80144c6: 68fb ldr r3, [r7, #12]
80144c8: 681b ldr r3, [r3, #0]
80144ca: 1e5a subs r2, r3, #1
80144cc: 68fb ldr r3, [r7, #12]
80144ce: 601a str r2, [r3, #0]
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
* list. */
prvAddTaskToReadyList( pxTCB );
80144d0: 69bb ldr r3, [r7, #24]
80144d2: 6ada ldr r2, [r3, #44] @ 0x2c
80144d4: 4b39 ldr r3, [pc, #228] @ (80145bc <xTaskIncrementTick+0x21c>)
80144d6: 681b ldr r3, [r3, #0]
80144d8: 429a cmp r2, r3
80144da: d903 bls.n 80144e4 <xTaskIncrementTick+0x144>
80144dc: 69bb ldr r3, [r7, #24]
80144de: 6adb ldr r3, [r3, #44] @ 0x2c
80144e0: 4a36 ldr r2, [pc, #216] @ (80145bc <xTaskIncrementTick+0x21c>)
80144e2: 6013 str r3, [r2, #0]
80144e4: 69bb ldr r3, [r7, #24]
80144e6: 6ada ldr r2, [r3, #44] @ 0x2c
80144e8: 4935 ldr r1, [pc, #212] @ (80145c0 <xTaskIncrementTick+0x220>)
80144ea: 4613 mov r3, r2
80144ec: 009b lsls r3, r3, #2
80144ee: 4413 add r3, r2
80144f0: 009b lsls r3, r3, #2
80144f2: 440b add r3, r1
80144f4: 3304 adds r3, #4
80144f6: 681b ldr r3, [r3, #0]
80144f8: 60bb str r3, [r7, #8]
80144fa: 69bb ldr r3, [r7, #24]
80144fc: 68ba ldr r2, [r7, #8]
80144fe: 609a str r2, [r3, #8]
8014500: 68bb ldr r3, [r7, #8]
8014502: 689a ldr r2, [r3, #8]
8014504: 69bb ldr r3, [r7, #24]
8014506: 60da str r2, [r3, #12]
8014508: 68bb ldr r3, [r7, #8]
801450a: 689b ldr r3, [r3, #8]
801450c: 69ba ldr r2, [r7, #24]
801450e: 3204 adds r2, #4
8014510: 605a str r2, [r3, #4]
8014512: 69bb ldr r3, [r7, #24]
8014514: 1d1a adds r2, r3, #4
8014516: 68bb ldr r3, [r7, #8]
8014518: 609a str r2, [r3, #8]
801451a: 69bb ldr r3, [r7, #24]
801451c: 6ada ldr r2, [r3, #44] @ 0x2c
801451e: 4613 mov r3, r2
8014520: 009b lsls r3, r3, #2
8014522: 4413 add r3, r2
8014524: 009b lsls r3, r3, #2
8014526: 4a26 ldr r2, [pc, #152] @ (80145c0 <xTaskIncrementTick+0x220>)
8014528: 441a add r2, r3
801452a: 69bb ldr r3, [r7, #24]
801452c: 615a str r2, [r3, #20]
801452e: 69bb ldr r3, [r7, #24]
8014530: 6ada ldr r2, [r3, #44] @ 0x2c
8014532: 4923 ldr r1, [pc, #140] @ (80145c0 <xTaskIncrementTick+0x220>)
8014534: 4613 mov r3, r2
8014536: 009b lsls r3, r3, #2
8014538: 4413 add r3, r2
801453a: 009b lsls r3, r3, #2
801453c: 440b add r3, r1
801453e: 681b ldr r3, [r3, #0]
8014540: 1c59 adds r1, r3, #1
8014542: 481f ldr r0, [pc, #124] @ (80145c0 <xTaskIncrementTick+0x220>)
8014544: 4613 mov r3, r2
8014546: 009b lsls r3, r3, #2
8014548: 4413 add r3, r2
801454a: 009b lsls r3, r3, #2
801454c: 4403 add r3, r0
801454e: 6019 str r1, [r3, #0]
* task.
* The case of equal priority tasks sharing
* processing time (which happens when both
* preemption and time slicing are on) is
* handled below.*/
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
8014550: 69bb ldr r3, [r7, #24]
8014552: 6ada ldr r2, [r3, #44] @ 0x2c
8014554: 4b1b ldr r3, [pc, #108] @ (80145c4 <xTaskIncrementTick+0x224>)
8014556: 681b ldr r3, [r3, #0]
8014558: 6adb ldr r3, [r3, #44] @ 0x2c
801455a: 429a cmp r2, r3
801455c: f67f af5c bls.w 8014418 <xTaskIncrementTick+0x78>
{
xSwitchRequired = pdTRUE;
8014560: 2301 movs r3, #1
8014562: 627b str r3, [r7, #36] @ 0x24
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8014564: e758 b.n 8014418 <xTaskIncrementTick+0x78>
/* Tasks of equal priority to the currently running task will share
* processing time (time slice) if preemption is on, and the application
* writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
8014566: 4b17 ldr r3, [pc, #92] @ (80145c4 <xTaskIncrementTick+0x224>)
8014568: 681b ldr r3, [r3, #0]
801456a: 6ada ldr r2, [r3, #44] @ 0x2c
801456c: 4914 ldr r1, [pc, #80] @ (80145c0 <xTaskIncrementTick+0x220>)
801456e: 4613 mov r3, r2
8014570: 009b lsls r3, r3, #2
8014572: 4413 add r3, r2
8014574: 009b lsls r3, r3, #2
8014576: 440b add r3, r1
8014578: 681b ldr r3, [r3, #0]
801457a: 2b01 cmp r3, #1
801457c: d901 bls.n 8014582 <xTaskIncrementTick+0x1e2>
{
xSwitchRequired = pdTRUE;
801457e: 2301 movs r3, #1
8014580: 627b str r3, [r7, #36] @ 0x24
}
#endif /* configUSE_TICK_HOOK */
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
8014582: 4b11 ldr r3, [pc, #68] @ (80145c8 <xTaskIncrementTick+0x228>)
8014584: 681b ldr r3, [r3, #0]
8014586: 2b00 cmp r3, #0
8014588: d007 beq.n 801459a <xTaskIncrementTick+0x1fa>
{
xSwitchRequired = pdTRUE;
801458a: 2301 movs r3, #1
801458c: 627b str r3, [r7, #36] @ 0x24
801458e: e004 b.n 801459a <xTaskIncrementTick+0x1fa>
}
#endif /* configUSE_PREEMPTION */
}
else
{
++xPendedTicks;
8014590: 4b0e ldr r3, [pc, #56] @ (80145cc <xTaskIncrementTick+0x22c>)
8014592: 681b ldr r3, [r3, #0]
8014594: 3301 adds r3, #1
8014596: 4a0d ldr r2, [pc, #52] @ (80145cc <xTaskIncrementTick+0x22c>)
8014598: 6013 str r3, [r2, #0]
vApplicationTickHook();
}
#endif
}
return xSwitchRequired;
801459a: 6a7b ldr r3, [r7, #36] @ 0x24
}
801459c: 4618 mov r0, r3
801459e: 3728 adds r7, #40 @ 0x28
80145a0: 46bd mov sp, r7
80145a2: bd80 pop {r7, pc}
80145a4: 200025c4 .word 0x200025c4
80145a8: 200025a0 .word 0x200025a0
80145ac: 20002554 .word 0x20002554
80145b0: 20002558 .word 0x20002558
80145b4: 200025b4 .word 0x200025b4
80145b8: 200025bc .word 0x200025bc
80145bc: 200025a4 .word 0x200025a4
80145c0: 200020cc .word 0x200020cc
80145c4: 200020c8 .word 0x200020c8
80145c8: 200025b0 .word 0x200025b0
80145cc: 200025ac .word 0x200025ac
080145d0 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
80145d0: b480 push {r7}
80145d2: b085 sub sp, #20
80145d4: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
80145d6: 4b28 ldr r3, [pc, #160] @ (8014678 <vTaskSwitchContext+0xa8>)
80145d8: 681b ldr r3, [r3, #0]
80145da: 2b00 cmp r3, #0
80145dc: d003 beq.n 80145e6 <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
* switch. */
xYieldPending = pdTRUE;
80145de: 4b27 ldr r3, [pc, #156] @ (801467c <vTaskSwitchContext+0xac>)
80145e0: 2201 movs r2, #1
80145e2: 601a str r2, [r3, #0]
* Block specific to this task. */
configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
}
#endif
}
}
80145e4: e041 b.n 801466a <vTaskSwitchContext+0x9a>
xYieldPending = pdFALSE;
80145e6: 4b25 ldr r3, [pc, #148] @ (801467c <vTaskSwitchContext+0xac>)
80145e8: 2200 movs r2, #0
80145ea: 601a str r2, [r3, #0]
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
80145ec: 4b24 ldr r3, [pc, #144] @ (8014680 <vTaskSwitchContext+0xb0>)
80145ee: 681b ldr r3, [r3, #0]
80145f0: 60fb str r3, [r7, #12]
80145f2: e011 b.n 8014618 <vTaskSwitchContext+0x48>
80145f4: 68fb ldr r3, [r7, #12]
80145f6: 2b00 cmp r3, #0
80145f8: d10b bne.n 8014612 <vTaskSwitchContext+0x42>
__asm volatile
80145fa: f04f 0350 mov.w r3, #80 @ 0x50
80145fe: f383 8811 msr BASEPRI, r3
8014602: f3bf 8f6f isb sy
8014606: f3bf 8f4f dsb sy
801460a: 607b str r3, [r7, #4]
}
801460c: bf00 nop
801460e: bf00 nop
8014610: e7fd b.n 801460e <vTaskSwitchContext+0x3e>
8014612: 68fb ldr r3, [r7, #12]
8014614: 3b01 subs r3, #1
8014616: 60fb str r3, [r7, #12]
8014618: 491a ldr r1, [pc, #104] @ (8014684 <vTaskSwitchContext+0xb4>)
801461a: 68fa ldr r2, [r7, #12]
801461c: 4613 mov r3, r2
801461e: 009b lsls r3, r3, #2
8014620: 4413 add r3, r2
8014622: 009b lsls r3, r3, #2
8014624: 440b add r3, r1
8014626: 681b ldr r3, [r3, #0]
8014628: 2b00 cmp r3, #0
801462a: d0e3 beq.n 80145f4 <vTaskSwitchContext+0x24>
801462c: 68fa ldr r2, [r7, #12]
801462e: 4613 mov r3, r2
8014630: 009b lsls r3, r3, #2
8014632: 4413 add r3, r2
8014634: 009b lsls r3, r3, #2
8014636: 4a13 ldr r2, [pc, #76] @ (8014684 <vTaskSwitchContext+0xb4>)
8014638: 4413 add r3, r2
801463a: 60bb str r3, [r7, #8]
801463c: 68bb ldr r3, [r7, #8]
801463e: 685b ldr r3, [r3, #4]
8014640: 685a ldr r2, [r3, #4]
8014642: 68bb ldr r3, [r7, #8]
8014644: 605a str r2, [r3, #4]
8014646: 68bb ldr r3, [r7, #8]
8014648: 685a ldr r2, [r3, #4]
801464a: 68bb ldr r3, [r7, #8]
801464c: 3308 adds r3, #8
801464e: 429a cmp r2, r3
8014650: d103 bne.n 801465a <vTaskSwitchContext+0x8a>
8014652: 68bb ldr r3, [r7, #8]
8014654: 68da ldr r2, [r3, #12]
8014656: 68bb ldr r3, [r7, #8]
8014658: 605a str r2, [r3, #4]
801465a: 68bb ldr r3, [r7, #8]
801465c: 685b ldr r3, [r3, #4]
801465e: 68db ldr r3, [r3, #12]
8014660: 4a09 ldr r2, [pc, #36] @ (8014688 <vTaskSwitchContext+0xb8>)
8014662: 6013 str r3, [r2, #0]
8014664: 4a06 ldr r2, [pc, #24] @ (8014680 <vTaskSwitchContext+0xb0>)
8014666: 68fb ldr r3, [r7, #12]
8014668: 6013 str r3, [r2, #0]
}
801466a: bf00 nop
801466c: 3714 adds r7, #20
801466e: 46bd mov sp, r7
8014670: f85d 7b04 ldr.w r7, [sp], #4
8014674: 4770 bx lr
8014676: bf00 nop
8014678: 200025c4 .word 0x200025c4
801467c: 200025b0 .word 0x200025b0
8014680: 200025a4 .word 0x200025a4
8014684: 200020cc .word 0x200020cc
8014688: 200020c8 .word 0x200020c8
0801468c <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList,
const TickType_t xTicksToWait )
{
801468c: b580 push {r7, lr}
801468e: b084 sub sp, #16
8014690: af00 add r7, sp, #0
8014692: 6078 str r0, [r7, #4]
8014694: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
8014696: 687b ldr r3, [r7, #4]
8014698: 2b00 cmp r3, #0
801469a: d10b bne.n 80146b4 <vTaskPlaceOnEventList+0x28>
__asm volatile
801469c: f04f 0350 mov.w r3, #80 @ 0x50
80146a0: f383 8811 msr BASEPRI, r3
80146a4: f3bf 8f6f isb sy
80146a8: f3bf 8f4f dsb sy
80146ac: 60fb str r3, [r7, #12]
}
80146ae: bf00 nop
80146b0: bf00 nop
80146b2: e7fd b.n 80146b0 <vTaskPlaceOnEventList+0x24>
* xItemValue = ( configMAX_PRIORITIES - uxPriority )
* Therefore, the event list is sorted in descending priority order.
*
* The queue that contains the event list is locked, preventing
* simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
80146b4: 4b07 ldr r3, [pc, #28] @ (80146d4 <vTaskPlaceOnEventList+0x48>)
80146b6: 681b ldr r3, [r3, #0]
80146b8: 3318 adds r3, #24
80146ba: 4619 mov r1, r3
80146bc: 6878 ldr r0, [r7, #4]
80146be: f7fe f900 bl 80128c2 <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
80146c2: 2101 movs r1, #1
80146c4: 6838 ldr r0, [r7, #0]
80146c6: f001 f92b bl 8015920 <prvAddCurrentTaskToDelayedList>
}
80146ca: bf00 nop
80146cc: 3710 adds r7, #16
80146ce: 46bd mov sp, r7
80146d0: bd80 pop {r7, pc}
80146d2: bf00 nop
80146d4: 200020c8 .word 0x200020c8
080146d8 <vTaskPlaceOnEventListRestricted>:
#if ( configUSE_TIMERS == 1 )
void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
TickType_t xTicksToWait,
const BaseType_t xWaitIndefinitely )
{
80146d8: b580 push {r7, lr}
80146da: b086 sub sp, #24
80146dc: af00 add r7, sp, #0
80146de: 60f8 str r0, [r7, #12]
80146e0: 60b9 str r1, [r7, #8]
80146e2: 607a str r2, [r7, #4]
configASSERT( pxEventList );
80146e4: 68fb ldr r3, [r7, #12]
80146e6: 2b00 cmp r3, #0
80146e8: d10b bne.n 8014702 <vTaskPlaceOnEventListRestricted+0x2a>
__asm volatile
80146ea: f04f 0350 mov.w r3, #80 @ 0x50
80146ee: f383 8811 msr BASEPRI, r3
80146f2: f3bf 8f6f isb sy
80146f6: f3bf 8f4f dsb sy
80146fa: 613b str r3, [r7, #16]
}
80146fc: bf00 nop
80146fe: bf00 nop
8014700: e7fd b.n 80146fe <vTaskPlaceOnEventListRestricted+0x26>
/* Place the event list item of the TCB in the appropriate event list.
* In this case it is assume that this is the only task that is going to
* be waiting on this event list, so the faster vListInsertEnd() function
* can be used in place of vListInsert. */
listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );
8014702: 68fb ldr r3, [r7, #12]
8014704: 685b ldr r3, [r3, #4]
8014706: 617b str r3, [r7, #20]
8014708: 4b15 ldr r3, [pc, #84] @ (8014760 <vTaskPlaceOnEventListRestricted+0x88>)
801470a: 681b ldr r3, [r3, #0]
801470c: 697a ldr r2, [r7, #20]
801470e: 61da str r2, [r3, #28]
8014710: 4b13 ldr r3, [pc, #76] @ (8014760 <vTaskPlaceOnEventListRestricted+0x88>)
8014712: 681b ldr r3, [r3, #0]
8014714: 697a ldr r2, [r7, #20]
8014716: 6892 ldr r2, [r2, #8]
8014718: 621a str r2, [r3, #32]
801471a: 4b11 ldr r3, [pc, #68] @ (8014760 <vTaskPlaceOnEventListRestricted+0x88>)
801471c: 681a ldr r2, [r3, #0]
801471e: 697b ldr r3, [r7, #20]
8014720: 689b ldr r3, [r3, #8]
8014722: 3218 adds r2, #24
8014724: 605a str r2, [r3, #4]
8014726: 4b0e ldr r3, [pc, #56] @ (8014760 <vTaskPlaceOnEventListRestricted+0x88>)
8014728: 681b ldr r3, [r3, #0]
801472a: f103 0218 add.w r2, r3, #24
801472e: 697b ldr r3, [r7, #20]
8014730: 609a str r2, [r3, #8]
8014732: 4b0b ldr r3, [pc, #44] @ (8014760 <vTaskPlaceOnEventListRestricted+0x88>)
8014734: 681b ldr r3, [r3, #0]
8014736: 68fa ldr r2, [r7, #12]
8014738: 629a str r2, [r3, #40] @ 0x28
801473a: 68fb ldr r3, [r7, #12]
801473c: 681b ldr r3, [r3, #0]
801473e: 1c5a adds r2, r3, #1
8014740: 68fb ldr r3, [r7, #12]
8014742: 601a str r2, [r3, #0]
/* If the task should block indefinitely then set the block time to a
* value that will be recognised as an indefinite delay inside the
* prvAddCurrentTaskToDelayedList() function. */
if( xWaitIndefinitely != pdFALSE )
8014744: 687b ldr r3, [r7, #4]
8014746: 2b00 cmp r3, #0
8014748: d002 beq.n 8014750 <vTaskPlaceOnEventListRestricted+0x78>
{
xTicksToWait = portMAX_DELAY;
801474a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
801474e: 60bb str r3, [r7, #8]
}
traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
8014750: 6879 ldr r1, [r7, #4]
8014752: 68b8 ldr r0, [r7, #8]
8014754: f001 f8e4 bl 8015920 <prvAddCurrentTaskToDelayedList>
}
8014758: bf00 nop
801475a: 3718 adds r7, #24
801475c: 46bd mov sp, r7
801475e: bd80 pop {r7, pc}
8014760: 200020c8 .word 0x200020c8
08014764 <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
8014764: b480 push {r7}
8014766: b08b sub sp, #44 @ 0x2c
8014768: af00 add r7, sp, #0
801476a: 6078 str r0, [r7, #4]
* get called - the lock count on the queue will get modified instead. This
* means exclusive access to the event list is guaranteed here.
*
* This function assumes that a check has already been made to ensure that
* pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
801476c: 687b ldr r3, [r7, #4]
801476e: 68db ldr r3, [r3, #12]
8014770: 68db ldr r3, [r3, #12]
8014772: 623b str r3, [r7, #32]
configASSERT( pxUnblockedTCB );
8014774: 6a3b ldr r3, [r7, #32]
8014776: 2b00 cmp r3, #0
8014778: d10b bne.n 8014792 <xTaskRemoveFromEventList+0x2e>
__asm volatile
801477a: f04f 0350 mov.w r3, #80 @ 0x50
801477e: f383 8811 msr BASEPRI, r3
8014782: f3bf 8f6f isb sy
8014786: f3bf 8f4f dsb sy
801478a: 60fb str r3, [r7, #12]
}
801478c: bf00 nop
801478e: bf00 nop
8014790: e7fd b.n 801478e <xTaskRemoveFromEventList+0x2a>
listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) );
8014792: 6a3b ldr r3, [r7, #32]
8014794: 6a9b ldr r3, [r3, #40] @ 0x28
8014796: 61fb str r3, [r7, #28]
8014798: 6a3b ldr r3, [r7, #32]
801479a: 69db ldr r3, [r3, #28]
801479c: 6a3a ldr r2, [r7, #32]
801479e: 6a12 ldr r2, [r2, #32]
80147a0: 609a str r2, [r3, #8]
80147a2: 6a3b ldr r3, [r7, #32]
80147a4: 6a1b ldr r3, [r3, #32]
80147a6: 6a3a ldr r2, [r7, #32]
80147a8: 69d2 ldr r2, [r2, #28]
80147aa: 605a str r2, [r3, #4]
80147ac: 69fb ldr r3, [r7, #28]
80147ae: 685a ldr r2, [r3, #4]
80147b0: 6a3b ldr r3, [r7, #32]
80147b2: 3318 adds r3, #24
80147b4: 429a cmp r2, r3
80147b6: d103 bne.n 80147c0 <xTaskRemoveFromEventList+0x5c>
80147b8: 6a3b ldr r3, [r7, #32]
80147ba: 6a1a ldr r2, [r3, #32]
80147bc: 69fb ldr r3, [r7, #28]
80147be: 605a str r2, [r3, #4]
80147c0: 6a3b ldr r3, [r7, #32]
80147c2: 2200 movs r2, #0
80147c4: 629a str r2, [r3, #40] @ 0x28
80147c6: 69fb ldr r3, [r7, #28]
80147c8: 681b ldr r3, [r3, #0]
80147ca: 1e5a subs r2, r3, #1
80147cc: 69fb ldr r3, [r7, #28]
80147ce: 601a str r2, [r3, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
80147d0: 4b4a ldr r3, [pc, #296] @ (80148fc <xTaskRemoveFromEventList+0x198>)
80147d2: 681b ldr r3, [r3, #0]
80147d4: 2b00 cmp r3, #0
80147d6: d15f bne.n 8014898 <xTaskRemoveFromEventList+0x134>
{
listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );
80147d8: 6a3b ldr r3, [r7, #32]
80147da: 695b ldr r3, [r3, #20]
80147dc: 617b str r3, [r7, #20]
80147de: 6a3b ldr r3, [r7, #32]
80147e0: 689b ldr r3, [r3, #8]
80147e2: 6a3a ldr r2, [r7, #32]
80147e4: 68d2 ldr r2, [r2, #12]
80147e6: 609a str r2, [r3, #8]
80147e8: 6a3b ldr r3, [r7, #32]
80147ea: 68db ldr r3, [r3, #12]
80147ec: 6a3a ldr r2, [r7, #32]
80147ee: 6892 ldr r2, [r2, #8]
80147f0: 605a str r2, [r3, #4]
80147f2: 697b ldr r3, [r7, #20]
80147f4: 685a ldr r2, [r3, #4]
80147f6: 6a3b ldr r3, [r7, #32]
80147f8: 3304 adds r3, #4
80147fa: 429a cmp r2, r3
80147fc: d103 bne.n 8014806 <xTaskRemoveFromEventList+0xa2>
80147fe: 6a3b ldr r3, [r7, #32]
8014800: 68da ldr r2, [r3, #12]
8014802: 697b ldr r3, [r7, #20]
8014804: 605a str r2, [r3, #4]
8014806: 6a3b ldr r3, [r7, #32]
8014808: 2200 movs r2, #0
801480a: 615a str r2, [r3, #20]
801480c: 697b ldr r3, [r7, #20]
801480e: 681b ldr r3, [r3, #0]
8014810: 1e5a subs r2, r3, #1
8014812: 697b ldr r3, [r7, #20]
8014814: 601a str r2, [r3, #0]
prvAddTaskToReadyList( pxUnblockedTCB );
8014816: 6a3b ldr r3, [r7, #32]
8014818: 6ada ldr r2, [r3, #44] @ 0x2c
801481a: 4b39 ldr r3, [pc, #228] @ (8014900 <xTaskRemoveFromEventList+0x19c>)
801481c: 681b ldr r3, [r3, #0]
801481e: 429a cmp r2, r3
8014820: d903 bls.n 801482a <xTaskRemoveFromEventList+0xc6>
8014822: 6a3b ldr r3, [r7, #32]
8014824: 6adb ldr r3, [r3, #44] @ 0x2c
8014826: 4a36 ldr r2, [pc, #216] @ (8014900 <xTaskRemoveFromEventList+0x19c>)
8014828: 6013 str r3, [r2, #0]
801482a: 6a3b ldr r3, [r7, #32]
801482c: 6ada ldr r2, [r3, #44] @ 0x2c
801482e: 4935 ldr r1, [pc, #212] @ (8014904 <xTaskRemoveFromEventList+0x1a0>)
8014830: 4613 mov r3, r2
8014832: 009b lsls r3, r3, #2
8014834: 4413 add r3, r2
8014836: 009b lsls r3, r3, #2
8014838: 440b add r3, r1
801483a: 3304 adds r3, #4
801483c: 681b ldr r3, [r3, #0]
801483e: 613b str r3, [r7, #16]
8014840: 6a3b ldr r3, [r7, #32]
8014842: 693a ldr r2, [r7, #16]
8014844: 609a str r2, [r3, #8]
8014846: 693b ldr r3, [r7, #16]
8014848: 689a ldr r2, [r3, #8]
801484a: 6a3b ldr r3, [r7, #32]
801484c: 60da str r2, [r3, #12]
801484e: 693b ldr r3, [r7, #16]
8014850: 689b ldr r3, [r3, #8]
8014852: 6a3a ldr r2, [r7, #32]
8014854: 3204 adds r2, #4
8014856: 605a str r2, [r3, #4]
8014858: 6a3b ldr r3, [r7, #32]
801485a: 1d1a adds r2, r3, #4
801485c: 693b ldr r3, [r7, #16]
801485e: 609a str r2, [r3, #8]
8014860: 6a3b ldr r3, [r7, #32]
8014862: 6ada ldr r2, [r3, #44] @ 0x2c
8014864: 4613 mov r3, r2
8014866: 009b lsls r3, r3, #2
8014868: 4413 add r3, r2
801486a: 009b lsls r3, r3, #2
801486c: 4a25 ldr r2, [pc, #148] @ (8014904 <xTaskRemoveFromEventList+0x1a0>)
801486e: 441a add r2, r3
8014870: 6a3b ldr r3, [r7, #32]
8014872: 615a str r2, [r3, #20]
8014874: 6a3b ldr r3, [r7, #32]
8014876: 6ada ldr r2, [r3, #44] @ 0x2c
8014878: 4922 ldr r1, [pc, #136] @ (8014904 <xTaskRemoveFromEventList+0x1a0>)
801487a: 4613 mov r3, r2
801487c: 009b lsls r3, r3, #2
801487e: 4413 add r3, r2
8014880: 009b lsls r3, r3, #2
8014882: 440b add r3, r1
8014884: 681b ldr r3, [r3, #0]
8014886: 1c59 adds r1, r3, #1
8014888: 481e ldr r0, [pc, #120] @ (8014904 <xTaskRemoveFromEventList+0x1a0>)
801488a: 4613 mov r3, r2
801488c: 009b lsls r3, r3, #2
801488e: 4413 add r3, r2
8014890: 009b lsls r3, r3, #2
8014892: 4403 add r3, r0
8014894: 6019 str r1, [r3, #0]
8014896: e01b b.n 80148d0 <xTaskRemoveFromEventList+0x16c>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
* pending until the scheduler is resumed. */
listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
8014898: 4b1b ldr r3, [pc, #108] @ (8014908 <xTaskRemoveFromEventList+0x1a4>)
801489a: 685b ldr r3, [r3, #4]
801489c: 61bb str r3, [r7, #24]
801489e: 6a3b ldr r3, [r7, #32]
80148a0: 69ba ldr r2, [r7, #24]
80148a2: 61da str r2, [r3, #28]
80148a4: 69bb ldr r3, [r7, #24]
80148a6: 689a ldr r2, [r3, #8]
80148a8: 6a3b ldr r3, [r7, #32]
80148aa: 621a str r2, [r3, #32]
80148ac: 69bb ldr r3, [r7, #24]
80148ae: 689b ldr r3, [r3, #8]
80148b0: 6a3a ldr r2, [r7, #32]
80148b2: 3218 adds r2, #24
80148b4: 605a str r2, [r3, #4]
80148b6: 6a3b ldr r3, [r7, #32]
80148b8: f103 0218 add.w r2, r3, #24
80148bc: 69bb ldr r3, [r7, #24]
80148be: 609a str r2, [r3, #8]
80148c0: 6a3b ldr r3, [r7, #32]
80148c2: 4a11 ldr r2, [pc, #68] @ (8014908 <xTaskRemoveFromEventList+0x1a4>)
80148c4: 629a str r2, [r3, #40] @ 0x28
80148c6: 4b10 ldr r3, [pc, #64] @ (8014908 <xTaskRemoveFromEventList+0x1a4>)
80148c8: 681b ldr r3, [r3, #0]
80148ca: 3301 adds r3, #1
80148cc: 4a0e ldr r2, [pc, #56] @ (8014908 <xTaskRemoveFromEventList+0x1a4>)
80148ce: 6013 str r3, [r2, #0]
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
80148d0: 6a3b ldr r3, [r7, #32]
80148d2: 6ada ldr r2, [r3, #44] @ 0x2c
80148d4: 4b0d ldr r3, [pc, #52] @ (801490c <xTaskRemoveFromEventList+0x1a8>)
80148d6: 681b ldr r3, [r3, #0]
80148d8: 6adb ldr r3, [r3, #44] @ 0x2c
80148da: 429a cmp r2, r3
80148dc: d905 bls.n 80148ea <xTaskRemoveFromEventList+0x186>
{
/* Return true if the task removed from the event list has a higher
* priority than the calling task. This allows the calling task to know if
* it should force a context switch now. */
xReturn = pdTRUE;
80148de: 2301 movs r3, #1
80148e0: 627b str r3, [r7, #36] @ 0x24
/* Mark that a yield is pending in case the user is not using the
* "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
80148e2: 4b0b ldr r3, [pc, #44] @ (8014910 <xTaskRemoveFromEventList+0x1ac>)
80148e4: 2201 movs r2, #1
80148e6: 601a str r2, [r3, #0]
80148e8: e001 b.n 80148ee <xTaskRemoveFromEventList+0x18a>
}
else
{
xReturn = pdFALSE;
80148ea: 2300 movs r3, #0
80148ec: 627b str r3, [r7, #36] @ 0x24
}
return xReturn;
80148ee: 6a7b ldr r3, [r7, #36] @ 0x24
}
80148f0: 4618 mov r0, r3
80148f2: 372c adds r7, #44 @ 0x2c
80148f4: 46bd mov sp, r7
80148f6: f85d 7b04 ldr.w r7, [sp], #4
80148fa: 4770 bx lr
80148fc: 200025c4 .word 0x200025c4
8014900: 200025a4 .word 0x200025a4
8014904: 200020cc .word 0x200020cc
8014908: 2000255c .word 0x2000255c
801490c: 200020c8 .word 0x200020c8
8014910: 200025b0 .word 0x200025b0
08014914 <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
8014914: b480 push {r7}
8014916: b083 sub sp, #12
8014918: af00 add r7, sp, #0
801491a: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
801491c: 4b06 ldr r3, [pc, #24] @ (8014938 <vTaskInternalSetTimeOutState+0x24>)
801491e: 681a ldr r2, [r3, #0]
8014920: 687b ldr r3, [r7, #4]
8014922: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
8014924: 4b05 ldr r3, [pc, #20] @ (801493c <vTaskInternalSetTimeOutState+0x28>)
8014926: 681a ldr r2, [r3, #0]
8014928: 687b ldr r3, [r7, #4]
801492a: 605a str r2, [r3, #4]
}
801492c: bf00 nop
801492e: 370c adds r7, #12
8014930: 46bd mov sp, r7
8014932: f85d 7b04 ldr.w r7, [sp], #4
8014936: 4770 bx lr
8014938: 200025b4 .word 0x200025b4
801493c: 200025a0 .word 0x200025a0
08014940 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
TickType_t * const pxTicksToWait )
{
8014940: b580 push {r7, lr}
8014942: b088 sub sp, #32
8014944: af00 add r7, sp, #0
8014946: 6078 str r0, [r7, #4]
8014948: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
801494a: 687b ldr r3, [r7, #4]
801494c: 2b00 cmp r3, #0
801494e: d10b bne.n 8014968 <xTaskCheckForTimeOut+0x28>
__asm volatile
8014950: f04f 0350 mov.w r3, #80 @ 0x50
8014954: f383 8811 msr BASEPRI, r3
8014958: f3bf 8f6f isb sy
801495c: f3bf 8f4f dsb sy
8014960: 613b str r3, [r7, #16]
}
8014962: bf00 nop
8014964: bf00 nop
8014966: e7fd b.n 8014964 <xTaskCheckForTimeOut+0x24>
configASSERT( pxTicksToWait );
8014968: 683b ldr r3, [r7, #0]
801496a: 2b00 cmp r3, #0
801496c: d10b bne.n 8014986 <xTaskCheckForTimeOut+0x46>
__asm volatile
801496e: f04f 0350 mov.w r3, #80 @ 0x50
8014972: f383 8811 msr BASEPRI, r3
8014976: f3bf 8f6f isb sy
801497a: f3bf 8f4f dsb sy
801497e: 60fb str r3, [r7, #12]
}
8014980: bf00 nop
8014982: bf00 nop
8014984: e7fd b.n 8014982 <xTaskCheckForTimeOut+0x42>
taskENTER_CRITICAL();
8014986: f001 fc4b bl 8016220 <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
801498a: 4b1f ldr r3, [pc, #124] @ (8014a08 <xTaskCheckForTimeOut+0xc8>)
801498c: 681b ldr r3, [r3, #0]
801498e: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
8014990: 687b ldr r3, [r7, #4]
8014992: 685b ldr r3, [r3, #4]
8014994: 69ba ldr r2, [r7, #24]
8014996: 1ad3 subs r3, r2, r3
8014998: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
801499a: 683b ldr r3, [r7, #0]
801499c: 681b ldr r3, [r3, #0]
801499e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80149a2: d102 bne.n 80149aa <xTaskCheckForTimeOut+0x6a>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
* specified is the maximum block time then the task should block
* indefinitely, and therefore never time out. */
xReturn = pdFALSE;
80149a4: 2300 movs r3, #0
80149a6: 61fb str r3, [r7, #28]
80149a8: e026 b.n 80149f8 <xTaskCheckForTimeOut+0xb8>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
80149aa: 687b ldr r3, [r7, #4]
80149ac: 681a ldr r2, [r3, #0]
80149ae: 4b17 ldr r3, [pc, #92] @ (8014a0c <xTaskCheckForTimeOut+0xcc>)
80149b0: 681b ldr r3, [r3, #0]
80149b2: 429a cmp r2, r3
80149b4: d00a beq.n 80149cc <xTaskCheckForTimeOut+0x8c>
80149b6: 687b ldr r3, [r7, #4]
80149b8: 685b ldr r3, [r3, #4]
80149ba: 69ba ldr r2, [r7, #24]
80149bc: 429a cmp r2, r3
80149be: d305 bcc.n 80149cc <xTaskCheckForTimeOut+0x8c>
/* The tick count is greater than the time at which
* vTaskSetTimeout() was called, but has also overflowed since
* vTaskSetTimeOut() was called. It must have wrapped all the way
* around and gone past again. This passed since vTaskSetTimeout()
* was called. */
xReturn = pdTRUE;
80149c0: 2301 movs r3, #1
80149c2: 61fb str r3, [r7, #28]
*pxTicksToWait = ( TickType_t ) 0;
80149c4: 683b ldr r3, [r7, #0]
80149c6: 2200 movs r2, #0
80149c8: 601a str r2, [r3, #0]
80149ca: e015 b.n 80149f8 <xTaskCheckForTimeOut+0xb8>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
80149cc: 683b ldr r3, [r7, #0]
80149ce: 681b ldr r3, [r3, #0]
80149d0: 697a ldr r2, [r7, #20]
80149d2: 429a cmp r2, r3
80149d4: d20b bcs.n 80149ee <xTaskCheckForTimeOut+0xae>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
80149d6: 683b ldr r3, [r7, #0]
80149d8: 681a ldr r2, [r3, #0]
80149da: 697b ldr r3, [r7, #20]
80149dc: 1ad2 subs r2, r2, r3
80149de: 683b ldr r3, [r7, #0]
80149e0: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
80149e2: 6878 ldr r0, [r7, #4]
80149e4: f7ff ff96 bl 8014914 <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
80149e8: 2300 movs r3, #0
80149ea: 61fb str r3, [r7, #28]
80149ec: e004 b.n 80149f8 <xTaskCheckForTimeOut+0xb8>
}
else
{
*pxTicksToWait = ( TickType_t ) 0;
80149ee: 683b ldr r3, [r7, #0]
80149f0: 2200 movs r2, #0
80149f2: 601a str r2, [r3, #0]
xReturn = pdTRUE;
80149f4: 2301 movs r3, #1
80149f6: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
80149f8: f001 fc44 bl 8016284 <vPortExitCritical>
return xReturn;
80149fc: 69fb ldr r3, [r7, #28]
}
80149fe: 4618 mov r0, r3
8014a00: 3720 adds r7, #32
8014a02: 46bd mov sp, r7
8014a04: bd80 pop {r7, pc}
8014a06: bf00 nop
8014a08: 200025a0 .word 0x200025a0
8014a0c: 200025b4 .word 0x200025b4
08014a10 <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
8014a10: b480 push {r7}
8014a12: af00 add r7, sp, #0
xYieldPending = pdTRUE;
8014a14: 4b03 ldr r3, [pc, #12] @ (8014a24 <vTaskMissedYield+0x14>)
8014a16: 2201 movs r2, #1
8014a18: 601a str r2, [r3, #0]
}
8014a1a: bf00 nop
8014a1c: 46bd mov sp, r7
8014a1e: f85d 7b04 ldr.w r7, [sp], #4
8014a22: 4770 bx lr
8014a24: 200025b0 .word 0x200025b0
08014a28 <prvIdleTask>:
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
8014a28: b580 push {r7, lr}
8014a2a: b082 sub sp, #8
8014a2c: af00 add r7, sp, #0
8014a2e: 6078 str r0, [r7, #4]
for( ; ; )
{
/* See if any tasks have deleted themselves - if so then the idle task
* is responsible for freeing the deleted task's TCB and stack. */
prvCheckTasksWaitingTermination();
8014a30: f000 f852 bl 8014ad8 <prvCheckTasksWaitingTermination>
*
* A critical region is not required here as we are just reading from
* the list, and an occasional incorrect value will not matter. If
* the ready list at the idle priority contains more than one task
* then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
8014a34: 4b06 ldr r3, [pc, #24] @ (8014a50 <prvIdleTask+0x28>)
8014a36: 681b ldr r3, [r3, #0]
8014a38: 2b01 cmp r3, #1
8014a3a: d9f9 bls.n 8014a30 <prvIdleTask+0x8>
{
taskYIELD();
8014a3c: 4b05 ldr r3, [pc, #20] @ (8014a54 <prvIdleTask+0x2c>)
8014a3e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8014a42: 601a str r2, [r3, #0]
8014a44: f3bf 8f4f dsb sy
8014a48: f3bf 8f6f isb sy
prvCheckTasksWaitingTermination();
8014a4c: e7f0 b.n 8014a30 <prvIdleTask+0x8>
8014a4e: bf00 nop
8014a50: 200020cc .word 0x200020cc
8014a54: e000ed04 .word 0xe000ed04
08014a58 <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
8014a58: b580 push {r7, lr}
8014a5a: b082 sub sp, #8
8014a5c: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
8014a5e: 2300 movs r3, #0
8014a60: 607b str r3, [r7, #4]
8014a62: e00c b.n 8014a7e <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
8014a64: 687a ldr r2, [r7, #4]
8014a66: 4613 mov r3, r2
8014a68: 009b lsls r3, r3, #2
8014a6a: 4413 add r3, r2
8014a6c: 009b lsls r3, r3, #2
8014a6e: 4a12 ldr r2, [pc, #72] @ (8014ab8 <prvInitialiseTaskLists+0x60>)
8014a70: 4413 add r3, r2
8014a72: 4618 mov r0, r3
8014a74: f7fd fef8 bl 8012868 <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
8014a78: 687b ldr r3, [r7, #4]
8014a7a: 3301 adds r3, #1
8014a7c: 607b str r3, [r7, #4]
8014a7e: 687b ldr r3, [r7, #4]
8014a80: 2b37 cmp r3, #55 @ 0x37
8014a82: d9ef bls.n 8014a64 <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
8014a84: 480d ldr r0, [pc, #52] @ (8014abc <prvInitialiseTaskLists+0x64>)
8014a86: f7fd feef bl 8012868 <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
8014a8a: 480d ldr r0, [pc, #52] @ (8014ac0 <prvInitialiseTaskLists+0x68>)
8014a8c: f7fd feec bl 8012868 <vListInitialise>
vListInitialise( &xPendingReadyList );
8014a90: 480c ldr r0, [pc, #48] @ (8014ac4 <prvInitialiseTaskLists+0x6c>)
8014a92: f7fd fee9 bl 8012868 <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
8014a96: 480c ldr r0, [pc, #48] @ (8014ac8 <prvInitialiseTaskLists+0x70>)
8014a98: f7fd fee6 bl 8012868 <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
8014a9c: 480b ldr r0, [pc, #44] @ (8014acc <prvInitialiseTaskLists+0x74>)
8014a9e: f7fd fee3 bl 8012868 <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
* using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
8014aa2: 4b0b ldr r3, [pc, #44] @ (8014ad0 <prvInitialiseTaskLists+0x78>)
8014aa4: 4a05 ldr r2, [pc, #20] @ (8014abc <prvInitialiseTaskLists+0x64>)
8014aa6: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
8014aa8: 4b0a ldr r3, [pc, #40] @ (8014ad4 <prvInitialiseTaskLists+0x7c>)
8014aaa: 4a05 ldr r2, [pc, #20] @ (8014ac0 <prvInitialiseTaskLists+0x68>)
8014aac: 601a str r2, [r3, #0]
}
8014aae: bf00 nop
8014ab0: 3708 adds r7, #8
8014ab2: 46bd mov sp, r7
8014ab4: bd80 pop {r7, pc}
8014ab6: bf00 nop
8014ab8: 200020cc .word 0x200020cc
8014abc: 2000252c .word 0x2000252c
8014ac0: 20002540 .word 0x20002540
8014ac4: 2000255c .word 0x2000255c
8014ac8: 20002570 .word 0x20002570
8014acc: 20002588 .word 0x20002588
8014ad0: 20002554 .word 0x20002554
8014ad4: 20002558 .word 0x20002558
08014ad8 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
8014ad8: b580 push {r7, lr}
8014ada: b082 sub sp, #8
8014adc: af00 add r7, sp, #0
{
TCB_t * pxTCB;
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
* being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
8014ade: e019 b.n 8014b14 <prvCheckTasksWaitingTermination+0x3c>
{
taskENTER_CRITICAL();
8014ae0: f001 fb9e bl 8016220 <vPortEnterCritical>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8014ae4: 4b10 ldr r3, [pc, #64] @ (8014b28 <prvCheckTasksWaitingTermination+0x50>)
8014ae6: 68db ldr r3, [r3, #12]
8014ae8: 68db ldr r3, [r3, #12]
8014aea: 607b str r3, [r7, #4]
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8014aec: 687b ldr r3, [r7, #4]
8014aee: 3304 adds r3, #4
8014af0: 4618 mov r0, r3
8014af2: f7fd ff1f bl 8012934 <uxListRemove>
--uxCurrentNumberOfTasks;
8014af6: 4b0d ldr r3, [pc, #52] @ (8014b2c <prvCheckTasksWaitingTermination+0x54>)
8014af8: 681b ldr r3, [r3, #0]
8014afa: 3b01 subs r3, #1
8014afc: 4a0b ldr r2, [pc, #44] @ (8014b2c <prvCheckTasksWaitingTermination+0x54>)
8014afe: 6013 str r3, [r2, #0]
--uxDeletedTasksWaitingCleanUp;
8014b00: 4b0b ldr r3, [pc, #44] @ (8014b30 <prvCheckTasksWaitingTermination+0x58>)
8014b02: 681b ldr r3, [r3, #0]
8014b04: 3b01 subs r3, #1
8014b06: 4a0a ldr r2, [pc, #40] @ (8014b30 <prvCheckTasksWaitingTermination+0x58>)
8014b08: 6013 str r3, [r2, #0]
}
taskEXIT_CRITICAL();
8014b0a: f001 fbbb bl 8016284 <vPortExitCritical>
prvDeleteTCB( pxTCB );
8014b0e: 6878 ldr r0, [r7, #4]
8014b10: f000 f810 bl 8014b34 <prvDeleteTCB>
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
8014b14: 4b06 ldr r3, [pc, #24] @ (8014b30 <prvCheckTasksWaitingTermination+0x58>)
8014b16: 681b ldr r3, [r3, #0]
8014b18: 2b00 cmp r3, #0
8014b1a: d1e1 bne.n 8014ae0 <prvCheckTasksWaitingTermination+0x8>
}
}
#endif /* INCLUDE_vTaskDelete */
}
8014b1c: bf00 nop
8014b1e: bf00 nop
8014b20: 3708 adds r7, #8
8014b22: 46bd mov sp, r7
8014b24: bd80 pop {r7, pc}
8014b26: bf00 nop
8014b28: 20002570 .word 0x20002570
8014b2c: 2000259c .word 0x2000259c
8014b30: 20002584 .word 0x20002584
08014b34 <prvDeleteTCB>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( TCB_t * pxTCB )
{
8014b34: b580 push {r7, lr}
8014b36: b084 sub sp, #16
8014b38: af00 add r7, sp, #0
8014b3a: 6078 str r0, [r7, #4]
#elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
* check what was statically allocated before trying to free the
* memory. */
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
8014b3c: 687b ldr r3, [r7, #4]
8014b3e: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
8014b42: 2b00 cmp r3, #0
8014b44: d108 bne.n 8014b58 <prvDeleteTCB+0x24>
{
/* Both the stack and TCB were allocated dynamically, so both
* must be freed. */
vPortFreeStack( pxTCB->pxStack );
8014b46: 687b ldr r3, [r7, #4]
8014b48: 6b1b ldr r3, [r3, #48] @ 0x30
8014b4a: 4618 mov r0, r3
8014b4c: f001 fd5c bl 8016608 <vPortFree>
vPortFree( pxTCB );
8014b50: 6878 ldr r0, [r7, #4]
8014b52: f001 fd59 bl 8016608 <vPortFree>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
8014b56: e019 b.n 8014b8c <prvDeleteTCB+0x58>
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
8014b58: 687b ldr r3, [r7, #4]
8014b5a: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
8014b5e: 2b01 cmp r3, #1
8014b60: d103 bne.n 8014b6a <prvDeleteTCB+0x36>
vPortFree( pxTCB );
8014b62: 6878 ldr r0, [r7, #4]
8014b64: f001 fd50 bl 8016608 <vPortFree>
}
8014b68: e010 b.n 8014b8c <prvDeleteTCB+0x58>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
8014b6a: 687b ldr r3, [r7, #4]
8014b6c: f893 3059 ldrb.w r3, [r3, #89] @ 0x59
8014b70: 2b02 cmp r3, #2
8014b72: d00b beq.n 8014b8c <prvDeleteTCB+0x58>
__asm volatile
8014b74: f04f 0350 mov.w r3, #80 @ 0x50
8014b78: f383 8811 msr BASEPRI, r3
8014b7c: f3bf 8f6f isb sy
8014b80: f3bf 8f4f dsb sy
8014b84: 60fb str r3, [r7, #12]
}
8014b86: bf00 nop
8014b88: bf00 nop
8014b8a: e7fd b.n 8014b88 <prvDeleteTCB+0x54>
}
8014b8c: bf00 nop
8014b8e: 3710 adds r7, #16
8014b90: 46bd mov sp, r7
8014b92: bd80 pop {r7, pc}
08014b94 <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
8014b94: b480 push {r7}
8014b96: af00 add r7, sp, #0
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8014b98: 4b0a ldr r3, [pc, #40] @ (8014bc4 <prvResetNextTaskUnblockTime+0x30>)
8014b9a: 681b ldr r3, [r3, #0]
8014b9c: 681b ldr r3, [r3, #0]
8014b9e: 2b00 cmp r3, #0
8014ba0: d104 bne.n 8014bac <prvResetNextTaskUnblockTime+0x18>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
* the maximum possible value so it is extremely unlikely that the
* if( xTickCount >= xNextTaskUnblockTime ) test will pass until
* there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
8014ba2: 4b09 ldr r3, [pc, #36] @ (8014bc8 <prvResetNextTaskUnblockTime+0x34>)
8014ba4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8014ba8: 601a str r2, [r3, #0]
* the item at the head of the delayed list. This is the time at
* which the task at the head of the delayed list should be removed
* from the Blocked state. */
xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );
}
}
8014baa: e005 b.n 8014bb8 <prvResetNextTaskUnblockTime+0x24>
xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );
8014bac: 4b05 ldr r3, [pc, #20] @ (8014bc4 <prvResetNextTaskUnblockTime+0x30>)
8014bae: 681b ldr r3, [r3, #0]
8014bb0: 68db ldr r3, [r3, #12]
8014bb2: 681b ldr r3, [r3, #0]
8014bb4: 4a04 ldr r2, [pc, #16] @ (8014bc8 <prvResetNextTaskUnblockTime+0x34>)
8014bb6: 6013 str r3, [r2, #0]
}
8014bb8: bf00 nop
8014bba: 46bd mov sp, r7
8014bbc: f85d 7b04 ldr.w r7, [sp], #4
8014bc0: 4770 bx lr
8014bc2: bf00 nop
8014bc4: 20002554 .word 0x20002554
8014bc8: 200025bc .word 0x200025bc
08014bcc <xTaskGetCurrentTaskHandle>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
TaskHandle_t xTaskGetCurrentTaskHandle( void )
{
8014bcc: b480 push {r7}
8014bce: b083 sub sp, #12
8014bd0: af00 add r7, sp, #0
TaskHandle_t xReturn;
/* A critical section is not required as this is not called from
* an interrupt and the current TCB will always be the same for any
* individual execution thread. */
xReturn = pxCurrentTCB;
8014bd2: 4b05 ldr r3, [pc, #20] @ (8014be8 <xTaskGetCurrentTaskHandle+0x1c>)
8014bd4: 681b ldr r3, [r3, #0]
8014bd6: 607b str r3, [r7, #4]
return xReturn;
8014bd8: 687b ldr r3, [r7, #4]
}
8014bda: 4618 mov r0, r3
8014bdc: 370c adds r7, #12
8014bde: 46bd mov sp, r7
8014be0: f85d 7b04 ldr.w r7, [sp], #4
8014be4: 4770 bx lr
8014be6: bf00 nop
8014be8: 200020c8 .word 0x200020c8
08014bec <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
8014bec: b480 push {r7}
8014bee: b083 sub sp, #12
8014bf0: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
8014bf2: 4b0b ldr r3, [pc, #44] @ (8014c20 <xTaskGetSchedulerState+0x34>)
8014bf4: 681b ldr r3, [r3, #0]
8014bf6: 2b00 cmp r3, #0
8014bf8: d102 bne.n 8014c00 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
8014bfa: 2301 movs r3, #1
8014bfc: 607b str r3, [r7, #4]
8014bfe: e008 b.n 8014c12 <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
8014c00: 4b08 ldr r3, [pc, #32] @ (8014c24 <xTaskGetSchedulerState+0x38>)
8014c02: 681b ldr r3, [r3, #0]
8014c04: 2b00 cmp r3, #0
8014c06: d102 bne.n 8014c0e <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
8014c08: 2302 movs r3, #2
8014c0a: 607b str r3, [r7, #4]
8014c0c: e001 b.n 8014c12 <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
8014c0e: 2300 movs r3, #0
8014c10: 607b str r3, [r7, #4]
}
}
return xReturn;
8014c12: 687b ldr r3, [r7, #4]
}
8014c14: 4618 mov r0, r3
8014c16: 370c adds r7, #12
8014c18: 46bd mov sp, r7
8014c1a: f85d 7b04 ldr.w r7, [sp], #4
8014c1e: 4770 bx lr
8014c20: 200025a8 .word 0x200025a8
8014c24: 200025c4 .word 0x200025c4
08014c28 <xTaskPriorityInherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
{
8014c28: b580 push {r7, lr}
8014c2a: b086 sub sp, #24
8014c2c: af00 add r7, sp, #0
8014c2e: 6078 str r0, [r7, #4]
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
8014c30: 687b ldr r3, [r7, #4]
8014c32: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
8014c34: 2300 movs r3, #0
8014c36: 617b str r3, [r7, #20]
/* If the mutex was given back by an interrupt while the queue was
* locked then the mutex holder might now be NULL. _RB_ Is this still
* needed as interrupts can no longer use mutexes? */
if( pxMutexHolder != NULL )
8014c38: 687b ldr r3, [r7, #4]
8014c3a: 2b00 cmp r3, #0
8014c3c: d079 beq.n 8014d32 <xTaskPriorityInherit+0x10a>
{
/* If the holder of the mutex has a priority below the priority of
* the task attempting to obtain the mutex then it will temporarily
* inherit the priority of the task attempting to obtain the mutex. */
if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
8014c3e: 693b ldr r3, [r7, #16]
8014c40: 6ada ldr r2, [r3, #44] @ 0x2c
8014c42: 4b3e ldr r3, [pc, #248] @ (8014d3c <xTaskPriorityInherit+0x114>)
8014c44: 681b ldr r3, [r3, #0]
8014c46: 6adb ldr r3, [r3, #44] @ 0x2c
8014c48: 429a cmp r2, r3
8014c4a: d269 bcs.n 8014d20 <xTaskPriorityInherit+0xf8>
{
/* Adjust the mutex holder state to account for its new
* priority. Only reset the event list item value if the value is
* not being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
8014c4c: 693b ldr r3, [r7, #16]
8014c4e: 699b ldr r3, [r3, #24]
8014c50: 2b00 cmp r3, #0
8014c52: db06 blt.n 8014c62 <xTaskPriorityInherit+0x3a>
{
listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8014c54: 4b39 ldr r3, [pc, #228] @ (8014d3c <xTaskPriorityInherit+0x114>)
8014c56: 681b ldr r3, [r3, #0]
8014c58: 6adb ldr r3, [r3, #44] @ 0x2c
8014c5a: f1c3 0238 rsb r2, r3, #56 @ 0x38
8014c5e: 693b ldr r3, [r7, #16]
8014c60: 619a str r2, [r3, #24]
mtCOVERAGE_TEST_MARKER();
}
/* If the task being modified is in the ready state it will need
* to be moved into a new list. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
8014c62: 693b ldr r3, [r7, #16]
8014c64: 6959 ldr r1, [r3, #20]
8014c66: 693b ldr r3, [r7, #16]
8014c68: 6ada ldr r2, [r3, #44] @ 0x2c
8014c6a: 4613 mov r3, r2
8014c6c: 009b lsls r3, r3, #2
8014c6e: 4413 add r3, r2
8014c70: 009b lsls r3, r3, #2
8014c72: 4a33 ldr r2, [pc, #204] @ (8014d40 <xTaskPriorityInherit+0x118>)
8014c74: 4413 add r3, r2
8014c76: 4299 cmp r1, r3
8014c78: d14a bne.n 8014d10 <xTaskPriorityInherit+0xe8>
{
if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8014c7a: 693b ldr r3, [r7, #16]
8014c7c: 3304 adds r3, #4
8014c7e: 4618 mov r0, r3
8014c80: f7fd fe58 bl 8012934 <uxListRemove>
{
mtCOVERAGE_TEST_MARKER();
}
/* Inherit the priority before being moved into the new list. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
8014c84: 4b2d ldr r3, [pc, #180] @ (8014d3c <xTaskPriorityInherit+0x114>)
8014c86: 681b ldr r3, [r3, #0]
8014c88: 6ada ldr r2, [r3, #44] @ 0x2c
8014c8a: 693b ldr r3, [r7, #16]
8014c8c: 62da str r2, [r3, #44] @ 0x2c
prvAddTaskToReadyList( pxMutexHolderTCB );
8014c8e: 693b ldr r3, [r7, #16]
8014c90: 6ada ldr r2, [r3, #44] @ 0x2c
8014c92: 4b2c ldr r3, [pc, #176] @ (8014d44 <xTaskPriorityInherit+0x11c>)
8014c94: 681b ldr r3, [r3, #0]
8014c96: 429a cmp r2, r3
8014c98: d903 bls.n 8014ca2 <xTaskPriorityInherit+0x7a>
8014c9a: 693b ldr r3, [r7, #16]
8014c9c: 6adb ldr r3, [r3, #44] @ 0x2c
8014c9e: 4a29 ldr r2, [pc, #164] @ (8014d44 <xTaskPriorityInherit+0x11c>)
8014ca0: 6013 str r3, [r2, #0]
8014ca2: 693b ldr r3, [r7, #16]
8014ca4: 6ada ldr r2, [r3, #44] @ 0x2c
8014ca6: 4926 ldr r1, [pc, #152] @ (8014d40 <xTaskPriorityInherit+0x118>)
8014ca8: 4613 mov r3, r2
8014caa: 009b lsls r3, r3, #2
8014cac: 4413 add r3, r2
8014cae: 009b lsls r3, r3, #2
8014cb0: 440b add r3, r1
8014cb2: 3304 adds r3, #4
8014cb4: 681b ldr r3, [r3, #0]
8014cb6: 60fb str r3, [r7, #12]
8014cb8: 693b ldr r3, [r7, #16]
8014cba: 68fa ldr r2, [r7, #12]
8014cbc: 609a str r2, [r3, #8]
8014cbe: 68fb ldr r3, [r7, #12]
8014cc0: 689a ldr r2, [r3, #8]
8014cc2: 693b ldr r3, [r7, #16]
8014cc4: 60da str r2, [r3, #12]
8014cc6: 68fb ldr r3, [r7, #12]
8014cc8: 689b ldr r3, [r3, #8]
8014cca: 693a ldr r2, [r7, #16]
8014ccc: 3204 adds r2, #4
8014cce: 605a str r2, [r3, #4]
8014cd0: 693b ldr r3, [r7, #16]
8014cd2: 1d1a adds r2, r3, #4
8014cd4: 68fb ldr r3, [r7, #12]
8014cd6: 609a str r2, [r3, #8]
8014cd8: 693b ldr r3, [r7, #16]
8014cda: 6ada ldr r2, [r3, #44] @ 0x2c
8014cdc: 4613 mov r3, r2
8014cde: 009b lsls r3, r3, #2
8014ce0: 4413 add r3, r2
8014ce2: 009b lsls r3, r3, #2
8014ce4: 4a16 ldr r2, [pc, #88] @ (8014d40 <xTaskPriorityInherit+0x118>)
8014ce6: 441a add r2, r3
8014ce8: 693b ldr r3, [r7, #16]
8014cea: 615a str r2, [r3, #20]
8014cec: 693b ldr r3, [r7, #16]
8014cee: 6ada ldr r2, [r3, #44] @ 0x2c
8014cf0: 4913 ldr r1, [pc, #76] @ (8014d40 <xTaskPriorityInherit+0x118>)
8014cf2: 4613 mov r3, r2
8014cf4: 009b lsls r3, r3, #2
8014cf6: 4413 add r3, r2
8014cf8: 009b lsls r3, r3, #2
8014cfa: 440b add r3, r1
8014cfc: 681b ldr r3, [r3, #0]
8014cfe: 1c59 adds r1, r3, #1
8014d00: 480f ldr r0, [pc, #60] @ (8014d40 <xTaskPriorityInherit+0x118>)
8014d02: 4613 mov r3, r2
8014d04: 009b lsls r3, r3, #2
8014d06: 4413 add r3, r2
8014d08: 009b lsls r3, r3, #2
8014d0a: 4403 add r3, r0
8014d0c: 6019 str r1, [r3, #0]
8014d0e: e004 b.n 8014d1a <xTaskPriorityInherit+0xf2>
}
else
{
/* Just inherit the priority. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
8014d10: 4b0a ldr r3, [pc, #40] @ (8014d3c <xTaskPriorityInherit+0x114>)
8014d12: 681b ldr r3, [r3, #0]
8014d14: 6ada ldr r2, [r3, #44] @ 0x2c
8014d16: 693b ldr r3, [r7, #16]
8014d18: 62da str r2, [r3, #44] @ 0x2c
}
traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
/* Inheritance occurred. */
xReturn = pdTRUE;
8014d1a: 2301 movs r3, #1
8014d1c: 617b str r3, [r7, #20]
8014d1e: e008 b.n 8014d32 <xTaskPriorityInherit+0x10a>
}
else
{
if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
8014d20: 693b ldr r3, [r7, #16]
8014d22: 6cda ldr r2, [r3, #76] @ 0x4c
8014d24: 4b05 ldr r3, [pc, #20] @ (8014d3c <xTaskPriorityInherit+0x114>)
8014d26: 681b ldr r3, [r3, #0]
8014d28: 6adb ldr r3, [r3, #44] @ 0x2c
8014d2a: 429a cmp r2, r3
8014d2c: d201 bcs.n 8014d32 <xTaskPriorityInherit+0x10a>
* current priority of the mutex holder is not lower than the
* priority of the task attempting to take the mutex.
* Therefore the mutex holder must have already inherited a
* priority, but inheritance would have occurred if that had
* not been the case. */
xReturn = pdTRUE;
8014d2e: 2301 movs r3, #1
8014d30: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8014d32: 697b ldr r3, [r7, #20]
}
8014d34: 4618 mov r0, r3
8014d36: 3718 adds r7, #24
8014d38: 46bd mov sp, r7
8014d3a: bd80 pop {r7, pc}
8014d3c: 200020c8 .word 0x200020c8
8014d40: 200020cc .word 0x200020cc
8014d44: 200025a4 .word 0x200025a4
08014d48 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
8014d48: b580 push {r7, lr}
8014d4a: b088 sub sp, #32
8014d4c: af00 add r7, sp, #0
8014d4e: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
8014d50: 687b ldr r3, [r7, #4]
8014d52: 61bb str r3, [r7, #24]
BaseType_t xReturn = pdFALSE;
8014d54: 2300 movs r3, #0
8014d56: 61fb str r3, [r7, #28]
if( pxMutexHolder != NULL )
8014d58: 687b ldr r3, [r7, #4]
8014d5a: 2b00 cmp r3, #0
8014d5c: f000 8081 beq.w 8014e62 <xTaskPriorityDisinherit+0x11a>
{
/* A task can only have an inherited priority if it holds the mutex.
* If the mutex is held by a task then it cannot be given from an
* interrupt, and if a mutex is given by the holding task then it must
* be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
8014d60: 4b42 ldr r3, [pc, #264] @ (8014e6c <xTaskPriorityDisinherit+0x124>)
8014d62: 681b ldr r3, [r3, #0]
8014d64: 69ba ldr r2, [r7, #24]
8014d66: 429a cmp r2, r3
8014d68: d00b beq.n 8014d82 <xTaskPriorityDisinherit+0x3a>
__asm volatile
8014d6a: f04f 0350 mov.w r3, #80 @ 0x50
8014d6e: f383 8811 msr BASEPRI, r3
8014d72: f3bf 8f6f isb sy
8014d76: f3bf 8f4f dsb sy
8014d7a: 613b str r3, [r7, #16]
}
8014d7c: bf00 nop
8014d7e: bf00 nop
8014d80: e7fd b.n 8014d7e <xTaskPriorityDisinherit+0x36>
configASSERT( pxTCB->uxMutexesHeld );
8014d82: 69bb ldr r3, [r7, #24]
8014d84: 6d1b ldr r3, [r3, #80] @ 0x50
8014d86: 2b00 cmp r3, #0
8014d88: d10b bne.n 8014da2 <xTaskPriorityDisinherit+0x5a>
__asm volatile
8014d8a: f04f 0350 mov.w r3, #80 @ 0x50
8014d8e: f383 8811 msr BASEPRI, r3
8014d92: f3bf 8f6f isb sy
8014d96: f3bf 8f4f dsb sy
8014d9a: 60fb str r3, [r7, #12]
}
8014d9c: bf00 nop
8014d9e: bf00 nop
8014da0: e7fd b.n 8014d9e <xTaskPriorityDisinherit+0x56>
( pxTCB->uxMutexesHeld )--;
8014da2: 69bb ldr r3, [r7, #24]
8014da4: 6d1b ldr r3, [r3, #80] @ 0x50
8014da6: 1e5a subs r2, r3, #1
8014da8: 69bb ldr r3, [r7, #24]
8014daa: 651a str r2, [r3, #80] @ 0x50
/* Has the holder of the mutex inherited the priority of another
* task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
8014dac: 69bb ldr r3, [r7, #24]
8014dae: 6ada ldr r2, [r3, #44] @ 0x2c
8014db0: 69bb ldr r3, [r7, #24]
8014db2: 6cdb ldr r3, [r3, #76] @ 0x4c
8014db4: 429a cmp r2, r3
8014db6: d054 beq.n 8014e62 <xTaskPriorityDisinherit+0x11a>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
8014db8: 69bb ldr r3, [r7, #24]
8014dba: 6d1b ldr r3, [r3, #80] @ 0x50
8014dbc: 2b00 cmp r3, #0
8014dbe: d150 bne.n 8014e62 <xTaskPriorityDisinherit+0x11a>
/* A task can only have an inherited priority if it holds
* the mutex. If the mutex is held by a task then it cannot be
* given from an interrupt, and if a mutex is given by the
* holding task then it must be the running state task. Remove
* the holding task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8014dc0: 69bb ldr r3, [r7, #24]
8014dc2: 3304 adds r3, #4
8014dc4: 4618 mov r0, r3
8014dc6: f7fd fdb5 bl 8012934 <uxListRemove>
}
/* Disinherit the priority before adding the task into the
* new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
8014dca: 69bb ldr r3, [r7, #24]
8014dcc: 6cda ldr r2, [r3, #76] @ 0x4c
8014dce: 69bb ldr r3, [r7, #24]
8014dd0: 62da str r2, [r3, #44] @ 0x2c
/* Reset the event list item value. It cannot be in use for
* any other purpose if this task is running, and it must be
* running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8014dd2: 69bb ldr r3, [r7, #24]
8014dd4: 6adb ldr r3, [r3, #44] @ 0x2c
8014dd6: f1c3 0238 rsb r2, r3, #56 @ 0x38
8014dda: 69bb ldr r3, [r7, #24]
8014ddc: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
8014dde: 69bb ldr r3, [r7, #24]
8014de0: 6ada ldr r2, [r3, #44] @ 0x2c
8014de2: 4b23 ldr r3, [pc, #140] @ (8014e70 <xTaskPriorityDisinherit+0x128>)
8014de4: 681b ldr r3, [r3, #0]
8014de6: 429a cmp r2, r3
8014de8: d903 bls.n 8014df2 <xTaskPriorityDisinherit+0xaa>
8014dea: 69bb ldr r3, [r7, #24]
8014dec: 6adb ldr r3, [r3, #44] @ 0x2c
8014dee: 4a20 ldr r2, [pc, #128] @ (8014e70 <xTaskPriorityDisinherit+0x128>)
8014df0: 6013 str r3, [r2, #0]
8014df2: 69bb ldr r3, [r7, #24]
8014df4: 6ada ldr r2, [r3, #44] @ 0x2c
8014df6: 491f ldr r1, [pc, #124] @ (8014e74 <xTaskPriorityDisinherit+0x12c>)
8014df8: 4613 mov r3, r2
8014dfa: 009b lsls r3, r3, #2
8014dfc: 4413 add r3, r2
8014dfe: 009b lsls r3, r3, #2
8014e00: 440b add r3, r1
8014e02: 3304 adds r3, #4
8014e04: 681b ldr r3, [r3, #0]
8014e06: 617b str r3, [r7, #20]
8014e08: 69bb ldr r3, [r7, #24]
8014e0a: 697a ldr r2, [r7, #20]
8014e0c: 609a str r2, [r3, #8]
8014e0e: 697b ldr r3, [r7, #20]
8014e10: 689a ldr r2, [r3, #8]
8014e12: 69bb ldr r3, [r7, #24]
8014e14: 60da str r2, [r3, #12]
8014e16: 697b ldr r3, [r7, #20]
8014e18: 689b ldr r3, [r3, #8]
8014e1a: 69ba ldr r2, [r7, #24]
8014e1c: 3204 adds r2, #4
8014e1e: 605a str r2, [r3, #4]
8014e20: 69bb ldr r3, [r7, #24]
8014e22: 1d1a adds r2, r3, #4
8014e24: 697b ldr r3, [r7, #20]
8014e26: 609a str r2, [r3, #8]
8014e28: 69bb ldr r3, [r7, #24]
8014e2a: 6ada ldr r2, [r3, #44] @ 0x2c
8014e2c: 4613 mov r3, r2
8014e2e: 009b lsls r3, r3, #2
8014e30: 4413 add r3, r2
8014e32: 009b lsls r3, r3, #2
8014e34: 4a0f ldr r2, [pc, #60] @ (8014e74 <xTaskPriorityDisinherit+0x12c>)
8014e36: 441a add r2, r3
8014e38: 69bb ldr r3, [r7, #24]
8014e3a: 615a str r2, [r3, #20]
8014e3c: 69bb ldr r3, [r7, #24]
8014e3e: 6ada ldr r2, [r3, #44] @ 0x2c
8014e40: 490c ldr r1, [pc, #48] @ (8014e74 <xTaskPriorityDisinherit+0x12c>)
8014e42: 4613 mov r3, r2
8014e44: 009b lsls r3, r3, #2
8014e46: 4413 add r3, r2
8014e48: 009b lsls r3, r3, #2
8014e4a: 440b add r3, r1
8014e4c: 681b ldr r3, [r3, #0]
8014e4e: 1c59 adds r1, r3, #1
8014e50: 4808 ldr r0, [pc, #32] @ (8014e74 <xTaskPriorityDisinherit+0x12c>)
8014e52: 4613 mov r3, r2
8014e54: 009b lsls r3, r3, #2
8014e56: 4413 add r3, r2
8014e58: 009b lsls r3, r3, #2
8014e5a: 4403 add r3, r0
8014e5c: 6019 str r1, [r3, #0]
* in an order different to that in which they were taken.
* If a context switch did not occur when the first mutex was
* returned, even if a task was waiting on it, then a context
* switch should occur when the last mutex is returned whether
* a task is waiting on it or not. */
xReturn = pdTRUE;
8014e5e: 2301 movs r3, #1
8014e60: 61fb str r3, [r7, #28]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8014e62: 69fb ldr r3, [r7, #28]
}
8014e64: 4618 mov r0, r3
8014e66: 3720 adds r7, #32
8014e68: 46bd mov sp, r7
8014e6a: bd80 pop {r7, pc}
8014e6c: 200020c8 .word 0x200020c8
8014e70: 200025a4 .word 0x200025a4
8014e74: 200020cc .word 0x200020cc
08014e78 <vTaskPriorityDisinheritAfterTimeout>:
#if ( configUSE_MUTEXES == 1 )
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
UBaseType_t uxHighestPriorityWaitingTask )
{
8014e78: b580 push {r7, lr}
8014e7a: b08a sub sp, #40 @ 0x28
8014e7c: af00 add r7, sp, #0
8014e7e: 6078 str r0, [r7, #4]
8014e80: 6039 str r1, [r7, #0]
TCB_t * const pxTCB = pxMutexHolder;
8014e82: 687b ldr r3, [r7, #4]
8014e84: 623b str r3, [r7, #32]
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
8014e86: 2301 movs r3, #1
8014e88: 61fb str r3, [r7, #28]
if( pxMutexHolder != NULL )
8014e8a: 687b ldr r3, [r7, #4]
8014e8c: 2b00 cmp r3, #0
8014e8e: f000 8095 beq.w 8014fbc <vTaskPriorityDisinheritAfterTimeout+0x144>
{
/* If pxMutexHolder is not NULL then the holder must hold at least
* one mutex. */
configASSERT( pxTCB->uxMutexesHeld );
8014e92: 6a3b ldr r3, [r7, #32]
8014e94: 6d1b ldr r3, [r3, #80] @ 0x50
8014e96: 2b00 cmp r3, #0
8014e98: d10b bne.n 8014eb2 <vTaskPriorityDisinheritAfterTimeout+0x3a>
__asm volatile
8014e9a: f04f 0350 mov.w r3, #80 @ 0x50
8014e9e: f383 8811 msr BASEPRI, r3
8014ea2: f3bf 8f6f isb sy
8014ea6: f3bf 8f4f dsb sy
8014eaa: 613b str r3, [r7, #16]
}
8014eac: bf00 nop
8014eae: bf00 nop
8014eb0: e7fd b.n 8014eae <vTaskPriorityDisinheritAfterTimeout+0x36>
/* Determine the priority to which the priority of the task that
* holds the mutex should be set. This will be the greater of the
* holding task's base priority and the priority of the highest
* priority task that is waiting to obtain the mutex. */
if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
8014eb2: 6a3b ldr r3, [r7, #32]
8014eb4: 6cdb ldr r3, [r3, #76] @ 0x4c
8014eb6: 683a ldr r2, [r7, #0]
8014eb8: 429a cmp r2, r3
8014eba: d902 bls.n 8014ec2 <vTaskPriorityDisinheritAfterTimeout+0x4a>
{
uxPriorityToUse = uxHighestPriorityWaitingTask;
8014ebc: 683b ldr r3, [r7, #0]
8014ebe: 627b str r3, [r7, #36] @ 0x24
8014ec0: e002 b.n 8014ec8 <vTaskPriorityDisinheritAfterTimeout+0x50>
}
else
{
uxPriorityToUse = pxTCB->uxBasePriority;
8014ec2: 6a3b ldr r3, [r7, #32]
8014ec4: 6cdb ldr r3, [r3, #76] @ 0x4c
8014ec6: 627b str r3, [r7, #36] @ 0x24
}
/* Does the priority need to change? */
if( pxTCB->uxPriority != uxPriorityToUse )
8014ec8: 6a3b ldr r3, [r7, #32]
8014eca: 6adb ldr r3, [r3, #44] @ 0x2c
8014ecc: 6a7a ldr r2, [r7, #36] @ 0x24
8014ece: 429a cmp r2, r3
8014ed0: d074 beq.n 8014fbc <vTaskPriorityDisinheritAfterTimeout+0x144>
{
/* Only disinherit if no other mutexes are held. This is a
* simplification in the priority inheritance implementation. If
* the task that holds the mutex is also holding other mutexes then
* the other mutexes may have caused the priority inheritance. */
if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
8014ed2: 6a3b ldr r3, [r7, #32]
8014ed4: 6d1b ldr r3, [r3, #80] @ 0x50
8014ed6: 69fa ldr r2, [r7, #28]
8014ed8: 429a cmp r2, r3
8014eda: d16f bne.n 8014fbc <vTaskPriorityDisinheritAfterTimeout+0x144>
{
/* If a task has timed out because it already holds the
* mutex it was trying to obtain then it cannot of inherited
* its own priority. */
configASSERT( pxTCB != pxCurrentTCB );
8014edc: 4b39 ldr r3, [pc, #228] @ (8014fc4 <vTaskPriorityDisinheritAfterTimeout+0x14c>)
8014ede: 681b ldr r3, [r3, #0]
8014ee0: 6a3a ldr r2, [r7, #32]
8014ee2: 429a cmp r2, r3
8014ee4: d10b bne.n 8014efe <vTaskPriorityDisinheritAfterTimeout+0x86>
__asm volatile
8014ee6: f04f 0350 mov.w r3, #80 @ 0x50
8014eea: f383 8811 msr BASEPRI, r3
8014eee: f3bf 8f6f isb sy
8014ef2: f3bf 8f4f dsb sy
8014ef6: 60fb str r3, [r7, #12]
}
8014ef8: bf00 nop
8014efa: bf00 nop
8014efc: e7fd b.n 8014efa <vTaskPriorityDisinheritAfterTimeout+0x82>
/* Disinherit the priority, remembering the previous
* priority to facilitate determining the subject task's
* state. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse );
uxPriorityUsedOnEntry = pxTCB->uxPriority;
8014efe: 6a3b ldr r3, [r7, #32]
8014f00: 6adb ldr r3, [r3, #44] @ 0x2c
8014f02: 61bb str r3, [r7, #24]
pxTCB->uxPriority = uxPriorityToUse;
8014f04: 6a3b ldr r3, [r7, #32]
8014f06: 6a7a ldr r2, [r7, #36] @ 0x24
8014f08: 62da str r2, [r3, #44] @ 0x2c
/* Only reset the event list item value if the value is not
* being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
8014f0a: 6a3b ldr r3, [r7, #32]
8014f0c: 699b ldr r3, [r3, #24]
8014f0e: 2b00 cmp r3, #0
8014f10: db04 blt.n 8014f1c <vTaskPriorityDisinheritAfterTimeout+0xa4>
{
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8014f12: 6a7b ldr r3, [r7, #36] @ 0x24
8014f14: f1c3 0238 rsb r2, r3, #56 @ 0x38
8014f18: 6a3b ldr r3, [r7, #32]
8014f1a: 619a str r2, [r3, #24]
* then the task that holds the mutex could be in either the
* Ready, Blocked or Suspended states. Only remove the task
* from its current state list if it is in the Ready state as
* the task's priority is going to change and there is one
* Ready list per priority. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
8014f1c: 6a3b ldr r3, [r7, #32]
8014f1e: 6959 ldr r1, [r3, #20]
8014f20: 69ba ldr r2, [r7, #24]
8014f22: 4613 mov r3, r2
8014f24: 009b lsls r3, r3, #2
8014f26: 4413 add r3, r2
8014f28: 009b lsls r3, r3, #2
8014f2a: 4a27 ldr r2, [pc, #156] @ (8014fc8 <vTaskPriorityDisinheritAfterTimeout+0x150>)
8014f2c: 4413 add r3, r2
8014f2e: 4299 cmp r1, r3
8014f30: d144 bne.n 8014fbc <vTaskPriorityDisinheritAfterTimeout+0x144>
{
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8014f32: 6a3b ldr r3, [r7, #32]
8014f34: 3304 adds r3, #4
8014f36: 4618 mov r0, r3
8014f38: f7fd fcfc bl 8012934 <uxListRemove>
else
{
mtCOVERAGE_TEST_MARKER();
}
prvAddTaskToReadyList( pxTCB );
8014f3c: 6a3b ldr r3, [r7, #32]
8014f3e: 6ada ldr r2, [r3, #44] @ 0x2c
8014f40: 4b22 ldr r3, [pc, #136] @ (8014fcc <vTaskPriorityDisinheritAfterTimeout+0x154>)
8014f42: 681b ldr r3, [r3, #0]
8014f44: 429a cmp r2, r3
8014f46: d903 bls.n 8014f50 <vTaskPriorityDisinheritAfterTimeout+0xd8>
8014f48: 6a3b ldr r3, [r7, #32]
8014f4a: 6adb ldr r3, [r3, #44] @ 0x2c
8014f4c: 4a1f ldr r2, [pc, #124] @ (8014fcc <vTaskPriorityDisinheritAfterTimeout+0x154>)
8014f4e: 6013 str r3, [r2, #0]
8014f50: 6a3b ldr r3, [r7, #32]
8014f52: 6ada ldr r2, [r3, #44] @ 0x2c
8014f54: 491c ldr r1, [pc, #112] @ (8014fc8 <vTaskPriorityDisinheritAfterTimeout+0x150>)
8014f56: 4613 mov r3, r2
8014f58: 009b lsls r3, r3, #2
8014f5a: 4413 add r3, r2
8014f5c: 009b lsls r3, r3, #2
8014f5e: 440b add r3, r1
8014f60: 3304 adds r3, #4
8014f62: 681b ldr r3, [r3, #0]
8014f64: 617b str r3, [r7, #20]
8014f66: 6a3b ldr r3, [r7, #32]
8014f68: 697a ldr r2, [r7, #20]
8014f6a: 609a str r2, [r3, #8]
8014f6c: 697b ldr r3, [r7, #20]
8014f6e: 689a ldr r2, [r3, #8]
8014f70: 6a3b ldr r3, [r7, #32]
8014f72: 60da str r2, [r3, #12]
8014f74: 697b ldr r3, [r7, #20]
8014f76: 689b ldr r3, [r3, #8]
8014f78: 6a3a ldr r2, [r7, #32]
8014f7a: 3204 adds r2, #4
8014f7c: 605a str r2, [r3, #4]
8014f7e: 6a3b ldr r3, [r7, #32]
8014f80: 1d1a adds r2, r3, #4
8014f82: 697b ldr r3, [r7, #20]
8014f84: 609a str r2, [r3, #8]
8014f86: 6a3b ldr r3, [r7, #32]
8014f88: 6ada ldr r2, [r3, #44] @ 0x2c
8014f8a: 4613 mov r3, r2
8014f8c: 009b lsls r3, r3, #2
8014f8e: 4413 add r3, r2
8014f90: 009b lsls r3, r3, #2
8014f92: 4a0d ldr r2, [pc, #52] @ (8014fc8 <vTaskPriorityDisinheritAfterTimeout+0x150>)
8014f94: 441a add r2, r3
8014f96: 6a3b ldr r3, [r7, #32]
8014f98: 615a str r2, [r3, #20]
8014f9a: 6a3b ldr r3, [r7, #32]
8014f9c: 6ada ldr r2, [r3, #44] @ 0x2c
8014f9e: 490a ldr r1, [pc, #40] @ (8014fc8 <vTaskPriorityDisinheritAfterTimeout+0x150>)
8014fa0: 4613 mov r3, r2
8014fa2: 009b lsls r3, r3, #2
8014fa4: 4413 add r3, r2
8014fa6: 009b lsls r3, r3, #2
8014fa8: 440b add r3, r1
8014faa: 681b ldr r3, [r3, #0]
8014fac: 1c59 adds r1, r3, #1
8014fae: 4806 ldr r0, [pc, #24] @ (8014fc8 <vTaskPriorityDisinheritAfterTimeout+0x150>)
8014fb0: 4613 mov r3, r2
8014fb2: 009b lsls r3, r3, #2
8014fb4: 4413 add r3, r2
8014fb6: 009b lsls r3, r3, #2
8014fb8: 4403 add r3, r0
8014fba: 6019 str r1, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8014fbc: bf00 nop
8014fbe: 3728 adds r7, #40 @ 0x28
8014fc0: 46bd mov sp, r7
8014fc2: bd80 pop {r7, pc}
8014fc4: 200020c8 .word 0x200020c8
8014fc8: 200020cc .word 0x200020cc
8014fcc: 200025a4 .word 0x200025a4
08014fd0 <pvTaskIncrementMutexHeldCount>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
{
8014fd0: b480 push {r7}
8014fd2: af00 add r7, sp, #0
/* If xSemaphoreCreateMutex() is called before any tasks have been created
* then pxCurrentTCB will be NULL. */
if( pxCurrentTCB != NULL )
8014fd4: 4b07 ldr r3, [pc, #28] @ (8014ff4 <pvTaskIncrementMutexHeldCount+0x24>)
8014fd6: 681b ldr r3, [r3, #0]
8014fd8: 2b00 cmp r3, #0
8014fda: d004 beq.n 8014fe6 <pvTaskIncrementMutexHeldCount+0x16>
{
( pxCurrentTCB->uxMutexesHeld )++;
8014fdc: 4b05 ldr r3, [pc, #20] @ (8014ff4 <pvTaskIncrementMutexHeldCount+0x24>)
8014fde: 681b ldr r3, [r3, #0]
8014fe0: 6d1a ldr r2, [r3, #80] @ 0x50
8014fe2: 3201 adds r2, #1
8014fe4: 651a str r2, [r3, #80] @ 0x50
}
return pxCurrentTCB;
8014fe6: 4b03 ldr r3, [pc, #12] @ (8014ff4 <pvTaskIncrementMutexHeldCount+0x24>)
8014fe8: 681b ldr r3, [r3, #0]
}
8014fea: 4618 mov r0, r3
8014fec: 46bd mov sp, r7
8014fee: f85d 7b04 ldr.w r7, [sp], #4
8014ff2: 4770 bx lr
8014ff4: 200020c8 .word 0x200020c8
08014ff8 <ulTaskGenericNotifyTake>:
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait,
BaseType_t xClearCountOnExit,
TickType_t xTicksToWait )
{
8014ff8: b580 push {r7, lr}
8014ffa: b086 sub sp, #24
8014ffc: af00 add r7, sp, #0
8014ffe: 60f8 str r0, [r7, #12]
8015000: 60b9 str r1, [r7, #8]
8015002: 607a str r2, [r7, #4]
uint32_t ulReturn;
configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
8015004: 68fb ldr r3, [r7, #12]
8015006: 2b00 cmp r3, #0
8015008: d00b beq.n 8015022 <ulTaskGenericNotifyTake+0x2a>
__asm volatile
801500a: f04f 0350 mov.w r3, #80 @ 0x50
801500e: f383 8811 msr BASEPRI, r3
8015012: f3bf 8f6f isb sy
8015016: f3bf 8f4f dsb sy
801501a: 613b str r3, [r7, #16]
}
801501c: bf00 nop
801501e: bf00 nop
8015020: e7fd b.n 801501e <ulTaskGenericNotifyTake+0x26>
taskENTER_CRITICAL();
8015022: f001 f8fd bl 8016220 <vPortEnterCritical>
{
/* Only block if the notification count is not already non-zero. */
if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL )
8015026: 4b28 ldr r3, [pc, #160] @ (80150c8 <ulTaskGenericNotifyTake+0xd0>)
8015028: 681a ldr r2, [r3, #0]
801502a: 68fb ldr r3, [r7, #12]
801502c: 3314 adds r3, #20
801502e: 009b lsls r3, r3, #2
8015030: 4413 add r3, r2
8015032: 685b ldr r3, [r3, #4]
8015034: 2b00 cmp r3, #0
8015036: d115 bne.n 8015064 <ulTaskGenericNotifyTake+0x6c>
{
/* Mark this task as waiting for a notification. */
pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
8015038: 4b23 ldr r3, [pc, #140] @ (80150c8 <ulTaskGenericNotifyTake+0xd0>)
801503a: 681a ldr r2, [r3, #0]
801503c: 68fb ldr r3, [r7, #12]
801503e: 4413 add r3, r2
8015040: 3358 adds r3, #88 @ 0x58
8015042: 2201 movs r2, #1
8015044: 701a strb r2, [r3, #0]
if( xTicksToWait > ( TickType_t ) 0 )
8015046: 687b ldr r3, [r7, #4]
8015048: 2b00 cmp r3, #0
801504a: d00b beq.n 8015064 <ulTaskGenericNotifyTake+0x6c>
{
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
801504c: 2101 movs r1, #1
801504e: 6878 ldr r0, [r7, #4]
8015050: f000 fc66 bl 8015920 <prvAddCurrentTaskToDelayedList>
/* All ports are written to allow a yield in a critical
* section (some will yield immediately, others wait until the
* critical section exits) - but it is not something that
* application code should ever do. */
portYIELD_WITHIN_API();
8015054: 4b1d ldr r3, [pc, #116] @ (80150cc <ulTaskGenericNotifyTake+0xd4>)
8015056: f04f 5280 mov.w r2, #268435456 @ 0x10000000
801505a: 601a str r2, [r3, #0]
801505c: f3bf 8f4f dsb sy
8015060: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8015064: f001 f90e bl 8016284 <vPortExitCritical>
taskENTER_CRITICAL();
8015068: f001 f8da bl 8016220 <vPortEnterCritical>
{
traceTASK_NOTIFY_TAKE( uxIndexToWait );
ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
801506c: 4b16 ldr r3, [pc, #88] @ (80150c8 <ulTaskGenericNotifyTake+0xd0>)
801506e: 681a ldr r2, [r3, #0]
8015070: 68fb ldr r3, [r7, #12]
8015072: 3314 adds r3, #20
8015074: 009b lsls r3, r3, #2
8015076: 4413 add r3, r2
8015078: 685b ldr r3, [r3, #4]
801507a: 617b str r3, [r7, #20]
if( ulReturn != 0UL )
801507c: 697b ldr r3, [r7, #20]
801507e: 2b00 cmp r3, #0
8015080: d014 beq.n 80150ac <ulTaskGenericNotifyTake+0xb4>
{
if( xClearCountOnExit != pdFALSE )
8015082: 68bb ldr r3, [r7, #8]
8015084: 2b00 cmp r3, #0
8015086: d008 beq.n 801509a <ulTaskGenericNotifyTake+0xa2>
{
pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL;
8015088: 4b0f ldr r3, [pc, #60] @ (80150c8 <ulTaskGenericNotifyTake+0xd0>)
801508a: 681a ldr r2, [r3, #0]
801508c: 68fb ldr r3, [r7, #12]
801508e: 3314 adds r3, #20
8015090: 009b lsls r3, r3, #2
8015092: 4413 add r3, r2
8015094: 2200 movs r2, #0
8015096: 605a str r2, [r3, #4]
8015098: e008 b.n 80150ac <ulTaskGenericNotifyTake+0xb4>
}
else
{
pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1;
801509a: 4b0b ldr r3, [pc, #44] @ (80150c8 <ulTaskGenericNotifyTake+0xd0>)
801509c: 6819 ldr r1, [r3, #0]
801509e: 697b ldr r3, [r7, #20]
80150a0: 1e5a subs r2, r3, #1
80150a2: 68fb ldr r3, [r7, #12]
80150a4: 3314 adds r3, #20
80150a6: 009b lsls r3, r3, #2
80150a8: 440b add r3, r1
80150aa: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
80150ac: 4b06 ldr r3, [pc, #24] @ (80150c8 <ulTaskGenericNotifyTake+0xd0>)
80150ae: 681a ldr r2, [r3, #0]
80150b0: 68fb ldr r3, [r7, #12]
80150b2: 4413 add r3, r2
80150b4: 3358 adds r3, #88 @ 0x58
80150b6: 2200 movs r2, #0
80150b8: 701a strb r2, [r3, #0]
}
taskEXIT_CRITICAL();
80150ba: f001 f8e3 bl 8016284 <vPortExitCritical>
return ulReturn;
80150be: 697b ldr r3, [r7, #20]
}
80150c0: 4618 mov r0, r3
80150c2: 3718 adds r7, #24
80150c4: 46bd mov sp, r7
80150c6: bd80 pop {r7, pc}
80150c8: 200020c8 .word 0x200020c8
80150cc: e000ed04 .word 0xe000ed04
080150d0 <xTaskGenericNotifyWait>:
BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait,
uint32_t ulBitsToClearOnEntry,
uint32_t ulBitsToClearOnExit,
uint32_t * pulNotificationValue,
TickType_t xTicksToWait )
{
80150d0: b580 push {r7, lr}
80150d2: b086 sub sp, #24
80150d4: af00 add r7, sp, #0
80150d6: 60f8 str r0, [r7, #12]
80150d8: 60b9 str r1, [r7, #8]
80150da: 607a str r2, [r7, #4]
80150dc: 603b str r3, [r7, #0]
BaseType_t xReturn;
configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
80150de: 68fb ldr r3, [r7, #12]
80150e0: 2b00 cmp r3, #0
80150e2: d00b beq.n 80150fc <xTaskGenericNotifyWait+0x2c>
__asm volatile
80150e4: f04f 0350 mov.w r3, #80 @ 0x50
80150e8: f383 8811 msr BASEPRI, r3
80150ec: f3bf 8f6f isb sy
80150f0: f3bf 8f4f dsb sy
80150f4: 613b str r3, [r7, #16]
}
80150f6: bf00 nop
80150f8: bf00 nop
80150fa: e7fd b.n 80150f8 <xTaskGenericNotifyWait+0x28>
taskENTER_CRITICAL();
80150fc: f001 f890 bl 8016220 <vPortEnterCritical>
{
/* Only block if a notification is not already pending. */
if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
8015100: 4b34 ldr r3, [pc, #208] @ (80151d4 <xTaskGenericNotifyWait+0x104>)
8015102: 681a ldr r2, [r3, #0]
8015104: 68fb ldr r3, [r7, #12]
8015106: 4413 add r3, r2
8015108: 3358 adds r3, #88 @ 0x58
801510a: 781b ldrb r3, [r3, #0]
801510c: b2db uxtb r3, r3
801510e: 2b02 cmp r3, #2
8015110: d024 beq.n 801515c <xTaskGenericNotifyWait+0x8c>
{
/* Clear bits in the task's notification value as bits may get
* set by the notifying task or interrupt. This can be used to
* clear the value to zero. */
pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry;
8015112: 4b30 ldr r3, [pc, #192] @ (80151d4 <xTaskGenericNotifyWait+0x104>)
8015114: 681a ldr r2, [r3, #0]
8015116: 68fb ldr r3, [r7, #12]
8015118: 3314 adds r3, #20
801511a: 009b lsls r3, r3, #2
801511c: 4413 add r3, r2
801511e: 6859 ldr r1, [r3, #4]
8015120: 68bb ldr r3, [r7, #8]
8015122: 43db mvns r3, r3
8015124: 4019 ands r1, r3
8015126: 68fb ldr r3, [r7, #12]
8015128: 3314 adds r3, #20
801512a: 009b lsls r3, r3, #2
801512c: 4413 add r3, r2
801512e: 6059 str r1, [r3, #4]
/* Mark this task as waiting for a notification. */
pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
8015130: 4b28 ldr r3, [pc, #160] @ (80151d4 <xTaskGenericNotifyWait+0x104>)
8015132: 681a ldr r2, [r3, #0]
8015134: 68fb ldr r3, [r7, #12]
8015136: 4413 add r3, r2
8015138: 3358 adds r3, #88 @ 0x58
801513a: 2201 movs r2, #1
801513c: 701a strb r2, [r3, #0]
if( xTicksToWait > ( TickType_t ) 0 )
801513e: 6a3b ldr r3, [r7, #32]
8015140: 2b00 cmp r3, #0
8015142: d00b beq.n 801515c <xTaskGenericNotifyWait+0x8c>
{
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
8015144: 2101 movs r1, #1
8015146: 6a38 ldr r0, [r7, #32]
8015148: f000 fbea bl 8015920 <prvAddCurrentTaskToDelayedList>
/* All ports are written to allow a yield in a critical
* section (some will yield immediately, others wait until the
* critical section exits) - but it is not something that
* application code should ever do. */
portYIELD_WITHIN_API();
801514c: 4b22 ldr r3, [pc, #136] @ (80151d8 <xTaskGenericNotifyWait+0x108>)
801514e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8015152: 601a str r2, [r3, #0]
8015154: f3bf 8f4f dsb sy
8015158: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
801515c: f001 f892 bl 8016284 <vPortExitCritical>
taskENTER_CRITICAL();
8015160: f001 f85e bl 8016220 <vPortEnterCritical>
{
traceTASK_NOTIFY_WAIT( uxIndexToWait );
if( pulNotificationValue != NULL )
8015164: 683b ldr r3, [r7, #0]
8015166: 2b00 cmp r3, #0
8015168: d008 beq.n 801517c <xTaskGenericNotifyWait+0xac>
{
/* Output the current notification value, which may or may not
* have changed. */
*pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
801516a: 4b1a ldr r3, [pc, #104] @ (80151d4 <xTaskGenericNotifyWait+0x104>)
801516c: 681a ldr r2, [r3, #0]
801516e: 68fb ldr r3, [r7, #12]
8015170: 3314 adds r3, #20
8015172: 009b lsls r3, r3, #2
8015174: 4413 add r3, r2
8015176: 685a ldr r2, [r3, #4]
8015178: 683b ldr r3, [r7, #0]
801517a: 601a str r2, [r3, #0]
/* If ucNotifyValue is set then either the task never entered the
* blocked state (because a notification was already pending) or the
* task unblocked because of a notification. Otherwise the task
* unblocked because of a timeout. */
if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
801517c: 4b15 ldr r3, [pc, #84] @ (80151d4 <xTaskGenericNotifyWait+0x104>)
801517e: 681a ldr r2, [r3, #0]
8015180: 68fb ldr r3, [r7, #12]
8015182: 4413 add r3, r2
8015184: 3358 adds r3, #88 @ 0x58
8015186: 781b ldrb r3, [r3, #0]
8015188: b2db uxtb r3, r3
801518a: 2b02 cmp r3, #2
801518c: d002 beq.n 8015194 <xTaskGenericNotifyWait+0xc4>
{
/* A notification was not received. */
xReturn = pdFALSE;
801518e: 2300 movs r3, #0
8015190: 617b str r3, [r7, #20]
8015192: e010 b.n 80151b6 <xTaskGenericNotifyWait+0xe6>
}
else
{
/* A notification was already pending or a notification was
* received while the task was waiting. */
pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit;
8015194: 4b0f ldr r3, [pc, #60] @ (80151d4 <xTaskGenericNotifyWait+0x104>)
8015196: 681a ldr r2, [r3, #0]
8015198: 68fb ldr r3, [r7, #12]
801519a: 3314 adds r3, #20
801519c: 009b lsls r3, r3, #2
801519e: 4413 add r3, r2
80151a0: 6859 ldr r1, [r3, #4]
80151a2: 687b ldr r3, [r7, #4]
80151a4: 43db mvns r3, r3
80151a6: 4019 ands r1, r3
80151a8: 68fb ldr r3, [r7, #12]
80151aa: 3314 adds r3, #20
80151ac: 009b lsls r3, r3, #2
80151ae: 4413 add r3, r2
80151b0: 6059 str r1, [r3, #4]
xReturn = pdTRUE;
80151b2: 2301 movs r3, #1
80151b4: 617b str r3, [r7, #20]
}
pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
80151b6: 4b07 ldr r3, [pc, #28] @ (80151d4 <xTaskGenericNotifyWait+0x104>)
80151b8: 681a ldr r2, [r3, #0]
80151ba: 68fb ldr r3, [r7, #12]
80151bc: 4413 add r3, r2
80151be: 3358 adds r3, #88 @ 0x58
80151c0: 2200 movs r2, #0
80151c2: 701a strb r2, [r3, #0]
}
taskEXIT_CRITICAL();
80151c4: f001 f85e bl 8016284 <vPortExitCritical>
return xReturn;
80151c8: 697b ldr r3, [r7, #20]
}
80151ca: 4618 mov r0, r3
80151cc: 3718 adds r7, #24
80151ce: 46bd mov sp, r7
80151d0: bd80 pop {r7, pc}
80151d2: bf00 nop
80151d4: 200020c8 .word 0x200020c8
80151d8: e000ed04 .word 0xe000ed04
080151dc <xTaskGenericNotify>:
BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
UBaseType_t uxIndexToNotify,
uint32_t ulValue,
eNotifyAction eAction,
uint32_t * pulPreviousNotificationValue )
{
80151dc: b580 push {r7, lr}
80151de: b08e sub sp, #56 @ 0x38
80151e0: af00 add r7, sp, #0
80151e2: 60f8 str r0, [r7, #12]
80151e4: 60b9 str r1, [r7, #8]
80151e6: 607a str r2, [r7, #4]
80151e8: 70fb strb r3, [r7, #3]
TCB_t * pxTCB;
BaseType_t xReturn = pdPASS;
80151ea: 2301 movs r3, #1
80151ec: 637b str r3, [r7, #52] @ 0x34
uint8_t ucOriginalNotifyState;
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
80151ee: 68bb ldr r3, [r7, #8]
80151f0: 2b00 cmp r3, #0
80151f2: d00b beq.n 801520c <xTaskGenericNotify+0x30>
__asm volatile
80151f4: f04f 0350 mov.w r3, #80 @ 0x50
80151f8: f383 8811 msr BASEPRI, r3
80151fc: f3bf 8f6f isb sy
8015200: f3bf 8f4f dsb sy
8015204: 623b str r3, [r7, #32]
}
8015206: bf00 nop
8015208: bf00 nop
801520a: e7fd b.n 8015208 <xTaskGenericNotify+0x2c>
configASSERT( xTaskToNotify );
801520c: 68fb ldr r3, [r7, #12]
801520e: 2b00 cmp r3, #0
8015210: d10b bne.n 801522a <xTaskGenericNotify+0x4e>
__asm volatile
8015212: f04f 0350 mov.w r3, #80 @ 0x50
8015216: f383 8811 msr BASEPRI, r3
801521a: f3bf 8f6f isb sy
801521e: f3bf 8f4f dsb sy
8015222: 61fb str r3, [r7, #28]
}
8015224: bf00 nop
8015226: bf00 nop
8015228: e7fd b.n 8015226 <xTaskGenericNotify+0x4a>
pxTCB = xTaskToNotify;
801522a: 68fb ldr r3, [r7, #12]
801522c: 633b str r3, [r7, #48] @ 0x30
taskENTER_CRITICAL();
801522e: f000 fff7 bl 8016220 <vPortEnterCritical>
{
if( pulPreviousNotificationValue != NULL )
8015232: 6c3b ldr r3, [r7, #64] @ 0x40
8015234: 2b00 cmp r3, #0
8015236: d007 beq.n 8015248 <xTaskGenericNotify+0x6c>
{
*pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
8015238: 6b3a ldr r2, [r7, #48] @ 0x30
801523a: 68bb ldr r3, [r7, #8]
801523c: 3314 adds r3, #20
801523e: 009b lsls r3, r3, #2
8015240: 4413 add r3, r2
8015242: 685a ldr r2, [r3, #4]
8015244: 6c3b ldr r3, [r7, #64] @ 0x40
8015246: 601a str r2, [r3, #0]
}
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
8015248: 6b3a ldr r2, [r7, #48] @ 0x30
801524a: 68bb ldr r3, [r7, #8]
801524c: 4413 add r3, r2
801524e: 3358 adds r3, #88 @ 0x58
8015250: 781b ldrb r3, [r3, #0]
8015252: f887 302f strb.w r3, [r7, #47] @ 0x2f
pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
8015256: 6b3a ldr r2, [r7, #48] @ 0x30
8015258: 68bb ldr r3, [r7, #8]
801525a: 4413 add r3, r2
801525c: 3358 adds r3, #88 @ 0x58
801525e: 2202 movs r2, #2
8015260: 701a strb r2, [r3, #0]
switch( eAction )
8015262: 78fb ldrb r3, [r7, #3]
8015264: 2b04 cmp r3, #4
8015266: d841 bhi.n 80152ec <xTaskGenericNotify+0x110>
8015268: a201 add r2, pc, #4 @ (adr r2, 8015270 <xTaskGenericNotify+0x94>)
801526a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
801526e: bf00 nop
8015270: 0801530d .word 0x0801530d
8015274: 08015285 .word 0x08015285
8015278: 080152a3 .word 0x080152a3
801527c: 080152bf .word 0x080152bf
8015280: 080152cf .word 0x080152cf
{
case eSetBits:
pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
8015284: 6b3a ldr r2, [r7, #48] @ 0x30
8015286: 68bb ldr r3, [r7, #8]
8015288: 3314 adds r3, #20
801528a: 009b lsls r3, r3, #2
801528c: 4413 add r3, r2
801528e: 685a ldr r2, [r3, #4]
8015290: 687b ldr r3, [r7, #4]
8015292: 431a orrs r2, r3
8015294: 6b39 ldr r1, [r7, #48] @ 0x30
8015296: 68bb ldr r3, [r7, #8]
8015298: 3314 adds r3, #20
801529a: 009b lsls r3, r3, #2
801529c: 440b add r3, r1
801529e: 605a str r2, [r3, #4]
break;
80152a0: e037 b.n 8015312 <xTaskGenericNotify+0x136>
case eIncrement:
( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
80152a2: 6b3a ldr r2, [r7, #48] @ 0x30
80152a4: 68bb ldr r3, [r7, #8]
80152a6: 3314 adds r3, #20
80152a8: 009b lsls r3, r3, #2
80152aa: 4413 add r3, r2
80152ac: 685b ldr r3, [r3, #4]
80152ae: 1c5a adds r2, r3, #1
80152b0: 6b39 ldr r1, [r7, #48] @ 0x30
80152b2: 68bb ldr r3, [r7, #8]
80152b4: 3314 adds r3, #20
80152b6: 009b lsls r3, r3, #2
80152b8: 440b add r3, r1
80152ba: 605a str r2, [r3, #4]
break;
80152bc: e029 b.n 8015312 <xTaskGenericNotify+0x136>
case eSetValueWithOverwrite:
pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
80152be: 6b3a ldr r2, [r7, #48] @ 0x30
80152c0: 68bb ldr r3, [r7, #8]
80152c2: 3314 adds r3, #20
80152c4: 009b lsls r3, r3, #2
80152c6: 4413 add r3, r2
80152c8: 687a ldr r2, [r7, #4]
80152ca: 605a str r2, [r3, #4]
break;
80152cc: e021 b.n 8015312 <xTaskGenericNotify+0x136>
case eSetValueWithoutOverwrite:
if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
80152ce: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
80152d2: 2b02 cmp r3, #2
80152d4: d007 beq.n 80152e6 <xTaskGenericNotify+0x10a>
{
pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
80152d6: 6b3a ldr r2, [r7, #48] @ 0x30
80152d8: 68bb ldr r3, [r7, #8]
80152da: 3314 adds r3, #20
80152dc: 009b lsls r3, r3, #2
80152de: 4413 add r3, r2
80152e0: 687a ldr r2, [r7, #4]
80152e2: 605a str r2, [r3, #4]
{
/* The value could not be written to the task. */
xReturn = pdFAIL;
}
break;
80152e4: e015 b.n 8015312 <xTaskGenericNotify+0x136>
xReturn = pdFAIL;
80152e6: 2300 movs r3, #0
80152e8: 637b str r3, [r7, #52] @ 0x34
break;
80152ea: e012 b.n 8015312 <xTaskGenericNotify+0x136>
default:
/* Should not get here if all enums are handled.
* Artificially force an assert by testing a value the
* compiler can't assume is const. */
configASSERT( xTickCount == ( TickType_t ) 0 );
80152ec: 4b4d ldr r3, [pc, #308] @ (8015424 <xTaskGenericNotify+0x248>)
80152ee: 681b ldr r3, [r3, #0]
80152f0: 2b00 cmp r3, #0
80152f2: d00d beq.n 8015310 <xTaskGenericNotify+0x134>
__asm volatile
80152f4: f04f 0350 mov.w r3, #80 @ 0x50
80152f8: f383 8811 msr BASEPRI, r3
80152fc: f3bf 8f6f isb sy
8015300: f3bf 8f4f dsb sy
8015304: 61bb str r3, [r7, #24]
}
8015306: bf00 nop
8015308: bf00 nop
801530a: e7fd b.n 8015308 <xTaskGenericNotify+0x12c>
break;
801530c: bf00 nop
801530e: e000 b.n 8015312 <xTaskGenericNotify+0x136>
break;
8015310: bf00 nop
traceTASK_NOTIFY( uxIndexToNotify );
/* If the task is in the blocked state specifically to wait for a
* notification then unblock it now. */
if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
8015312: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
8015316: 2b01 cmp r3, #1
8015318: d17d bne.n 8015416 <xTaskGenericNotify+0x23a>
{
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
801531a: 6b3b ldr r3, [r7, #48] @ 0x30
801531c: 695b ldr r3, [r3, #20]
801531e: 62bb str r3, [r7, #40] @ 0x28
8015320: 6b3b ldr r3, [r7, #48] @ 0x30
8015322: 689b ldr r3, [r3, #8]
8015324: 6b3a ldr r2, [r7, #48] @ 0x30
8015326: 68d2 ldr r2, [r2, #12]
8015328: 609a str r2, [r3, #8]
801532a: 6b3b ldr r3, [r7, #48] @ 0x30
801532c: 68db ldr r3, [r3, #12]
801532e: 6b3a ldr r2, [r7, #48] @ 0x30
8015330: 6892 ldr r2, [r2, #8]
8015332: 605a str r2, [r3, #4]
8015334: 6abb ldr r3, [r7, #40] @ 0x28
8015336: 685a ldr r2, [r3, #4]
8015338: 6b3b ldr r3, [r7, #48] @ 0x30
801533a: 3304 adds r3, #4
801533c: 429a cmp r2, r3
801533e: d103 bne.n 8015348 <xTaskGenericNotify+0x16c>
8015340: 6b3b ldr r3, [r7, #48] @ 0x30
8015342: 68da ldr r2, [r3, #12]
8015344: 6abb ldr r3, [r7, #40] @ 0x28
8015346: 605a str r2, [r3, #4]
8015348: 6b3b ldr r3, [r7, #48] @ 0x30
801534a: 2200 movs r2, #0
801534c: 615a str r2, [r3, #20]
801534e: 6abb ldr r3, [r7, #40] @ 0x28
8015350: 681b ldr r3, [r3, #0]
8015352: 1e5a subs r2, r3, #1
8015354: 6abb ldr r3, [r7, #40] @ 0x28
8015356: 601a str r2, [r3, #0]
prvAddTaskToReadyList( pxTCB );
8015358: 6b3b ldr r3, [r7, #48] @ 0x30
801535a: 6ada ldr r2, [r3, #44] @ 0x2c
801535c: 4b32 ldr r3, [pc, #200] @ (8015428 <xTaskGenericNotify+0x24c>)
801535e: 681b ldr r3, [r3, #0]
8015360: 429a cmp r2, r3
8015362: d903 bls.n 801536c <xTaskGenericNotify+0x190>
8015364: 6b3b ldr r3, [r7, #48] @ 0x30
8015366: 6adb ldr r3, [r3, #44] @ 0x2c
8015368: 4a2f ldr r2, [pc, #188] @ (8015428 <xTaskGenericNotify+0x24c>)
801536a: 6013 str r3, [r2, #0]
801536c: 6b3b ldr r3, [r7, #48] @ 0x30
801536e: 6ada ldr r2, [r3, #44] @ 0x2c
8015370: 492e ldr r1, [pc, #184] @ (801542c <xTaskGenericNotify+0x250>)
8015372: 4613 mov r3, r2
8015374: 009b lsls r3, r3, #2
8015376: 4413 add r3, r2
8015378: 009b lsls r3, r3, #2
801537a: 440b add r3, r1
801537c: 3304 adds r3, #4
801537e: 681b ldr r3, [r3, #0]
8015380: 627b str r3, [r7, #36] @ 0x24
8015382: 6b3b ldr r3, [r7, #48] @ 0x30
8015384: 6a7a ldr r2, [r7, #36] @ 0x24
8015386: 609a str r2, [r3, #8]
8015388: 6a7b ldr r3, [r7, #36] @ 0x24
801538a: 689a ldr r2, [r3, #8]
801538c: 6b3b ldr r3, [r7, #48] @ 0x30
801538e: 60da str r2, [r3, #12]
8015390: 6a7b ldr r3, [r7, #36] @ 0x24
8015392: 689b ldr r3, [r3, #8]
8015394: 6b3a ldr r2, [r7, #48] @ 0x30
8015396: 3204 adds r2, #4
8015398: 605a str r2, [r3, #4]
801539a: 6b3b ldr r3, [r7, #48] @ 0x30
801539c: 1d1a adds r2, r3, #4
801539e: 6a7b ldr r3, [r7, #36] @ 0x24
80153a0: 609a str r2, [r3, #8]
80153a2: 6b3b ldr r3, [r7, #48] @ 0x30
80153a4: 6ada ldr r2, [r3, #44] @ 0x2c
80153a6: 4613 mov r3, r2
80153a8: 009b lsls r3, r3, #2
80153aa: 4413 add r3, r2
80153ac: 009b lsls r3, r3, #2
80153ae: 4a1f ldr r2, [pc, #124] @ (801542c <xTaskGenericNotify+0x250>)
80153b0: 441a add r2, r3
80153b2: 6b3b ldr r3, [r7, #48] @ 0x30
80153b4: 615a str r2, [r3, #20]
80153b6: 6b3b ldr r3, [r7, #48] @ 0x30
80153b8: 6ada ldr r2, [r3, #44] @ 0x2c
80153ba: 491c ldr r1, [pc, #112] @ (801542c <xTaskGenericNotify+0x250>)
80153bc: 4613 mov r3, r2
80153be: 009b lsls r3, r3, #2
80153c0: 4413 add r3, r2
80153c2: 009b lsls r3, r3, #2
80153c4: 440b add r3, r1
80153c6: 681b ldr r3, [r3, #0]
80153c8: 1c59 adds r1, r3, #1
80153ca: 4818 ldr r0, [pc, #96] @ (801542c <xTaskGenericNotify+0x250>)
80153cc: 4613 mov r3, r2
80153ce: 009b lsls r3, r3, #2
80153d0: 4413 add r3, r2
80153d2: 009b lsls r3, r3, #2
80153d4: 4403 add r3, r0
80153d6: 6019 str r1, [r3, #0]
/* The task should not have been on an event list. */
configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
80153d8: 6b3b ldr r3, [r7, #48] @ 0x30
80153da: 6a9b ldr r3, [r3, #40] @ 0x28
80153dc: 2b00 cmp r3, #0
80153de: d00b beq.n 80153f8 <xTaskGenericNotify+0x21c>
__asm volatile
80153e0: f04f 0350 mov.w r3, #80 @ 0x50
80153e4: f383 8811 msr BASEPRI, r3
80153e8: f3bf 8f6f isb sy
80153ec: f3bf 8f4f dsb sy
80153f0: 617b str r3, [r7, #20]
}
80153f2: bf00 nop
80153f4: bf00 nop
80153f6: e7fd b.n 80153f4 <xTaskGenericNotify+0x218>
* earliest possible time. */
prvResetNextTaskUnblockTime();
}
#endif
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
80153f8: 6b3b ldr r3, [r7, #48] @ 0x30
80153fa: 6ada ldr r2, [r3, #44] @ 0x2c
80153fc: 4b0c ldr r3, [pc, #48] @ (8015430 <xTaskGenericNotify+0x254>)
80153fe: 681b ldr r3, [r3, #0]
8015400: 6adb ldr r3, [r3, #44] @ 0x2c
8015402: 429a cmp r2, r3
8015404: d907 bls.n 8015416 <xTaskGenericNotify+0x23a>
{
/* The notified task has a priority above the currently
* executing task so a yield is required. */
taskYIELD_IF_USING_PREEMPTION();
8015406: 4b0b ldr r3, [pc, #44] @ (8015434 <xTaskGenericNotify+0x258>)
8015408: f04f 5280 mov.w r2, #268435456 @ 0x10000000
801540c: 601a str r2, [r3, #0]
801540e: f3bf 8f4f dsb sy
8015412: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8015416: f000 ff35 bl 8016284 <vPortExitCritical>
return xReturn;
801541a: 6b7b ldr r3, [r7, #52] @ 0x34
}
801541c: 4618 mov r0, r3
801541e: 3738 adds r7, #56 @ 0x38
8015420: 46bd mov sp, r7
8015422: bd80 pop {r7, pc}
8015424: 200025a0 .word 0x200025a0
8015428: 200025a4 .word 0x200025a4
801542c: 200020cc .word 0x200020cc
8015430: 200020c8 .word 0x200020c8
8015434: e000ed04 .word 0xe000ed04
08015438 <xTaskGenericNotifyFromISR>:
UBaseType_t uxIndexToNotify,
uint32_t ulValue,
eNotifyAction eAction,
uint32_t * pulPreviousNotificationValue,
BaseType_t * pxHigherPriorityTaskWoken )
{
8015438: b580 push {r7, lr}
801543a: b092 sub sp, #72 @ 0x48
801543c: af00 add r7, sp, #0
801543e: 60f8 str r0, [r7, #12]
8015440: 60b9 str r1, [r7, #8]
8015442: 607a str r2, [r7, #4]
8015444: 70fb strb r3, [r7, #3]
TCB_t * pxTCB;
uint8_t ucOriginalNotifyState;
BaseType_t xReturn = pdPASS;
8015446: 2301 movs r3, #1
8015448: 647b str r3, [r7, #68] @ 0x44
UBaseType_t uxSavedInterruptStatus;
configASSERT( xTaskToNotify );
801544a: 68fb ldr r3, [r7, #12]
801544c: 2b00 cmp r3, #0
801544e: d10b bne.n 8015468 <xTaskGenericNotifyFromISR+0x30>
__asm volatile
8015450: f04f 0350 mov.w r3, #80 @ 0x50
8015454: f383 8811 msr BASEPRI, r3
8015458: f3bf 8f6f isb sy
801545c: f3bf 8f4f dsb sy
8015460: 62bb str r3, [r7, #40] @ 0x28
}
8015462: bf00 nop
8015464: bf00 nop
8015466: e7fd b.n 8015464 <xTaskGenericNotifyFromISR+0x2c>
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
8015468: 68bb ldr r3, [r7, #8]
801546a: 2b00 cmp r3, #0
801546c: d00b beq.n 8015486 <xTaskGenericNotifyFromISR+0x4e>
__asm volatile
801546e: f04f 0350 mov.w r3, #80 @ 0x50
8015472: f383 8811 msr BASEPRI, r3
8015476: f3bf 8f6f isb sy
801547a: f3bf 8f4f dsb sy
801547e: 627b str r3, [r7, #36] @ 0x24
}
8015480: bf00 nop
8015482: bf00 nop
8015484: e7fd b.n 8015482 <xTaskGenericNotifyFromISR+0x4a>
* below the maximum system call interrupt priority. FreeRTOS maintains a
* separate interrupt safe API to ensure interrupt entry is as fast and as
* simple as possible. More information (albeit Cortex-M specific) is
* provided on the following link:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
8015486: f000 ffb1 bl 80163ec <vPortValidateInterruptPriority>
pxTCB = xTaskToNotify;
801548a: 68fb ldr r3, [r7, #12]
801548c: 643b str r3, [r7, #64] @ 0x40
__asm volatile
801548e: f3ef 8211 mrs r2, BASEPRI
8015492: f04f 0350 mov.w r3, #80 @ 0x50
8015496: f383 8811 msr BASEPRI, r3
801549a: f3bf 8f6f isb sy
801549e: f3bf 8f4f dsb sy
80154a2: 623a str r2, [r7, #32]
80154a4: 61fb str r3, [r7, #28]
return ulOriginalBASEPRI;
80154a6: 6a3b ldr r3, [r7, #32]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
80154a8: 63fb str r3, [r7, #60] @ 0x3c
{
if( pulPreviousNotificationValue != NULL )
80154aa: 6d3b ldr r3, [r7, #80] @ 0x50
80154ac: 2b00 cmp r3, #0
80154ae: d007 beq.n 80154c0 <xTaskGenericNotifyFromISR+0x88>
{
*pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
80154b0: 6c3a ldr r2, [r7, #64] @ 0x40
80154b2: 68bb ldr r3, [r7, #8]
80154b4: 3314 adds r3, #20
80154b6: 009b lsls r3, r3, #2
80154b8: 4413 add r3, r2
80154ba: 685a ldr r2, [r3, #4]
80154bc: 6d3b ldr r3, [r7, #80] @ 0x50
80154be: 601a str r2, [r3, #0]
}
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
80154c0: 6c3a ldr r2, [r7, #64] @ 0x40
80154c2: 68bb ldr r3, [r7, #8]
80154c4: 4413 add r3, r2
80154c6: 3358 adds r3, #88 @ 0x58
80154c8: 781b ldrb r3, [r3, #0]
80154ca: f887 303b strb.w r3, [r7, #59] @ 0x3b
pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
80154ce: 6c3a ldr r2, [r7, #64] @ 0x40
80154d0: 68bb ldr r3, [r7, #8]
80154d2: 4413 add r3, r2
80154d4: 3358 adds r3, #88 @ 0x58
80154d6: 2202 movs r2, #2
80154d8: 701a strb r2, [r3, #0]
switch( eAction )
80154da: 78fb ldrb r3, [r7, #3]
80154dc: 2b04 cmp r3, #4
80154de: d841 bhi.n 8015564 <xTaskGenericNotifyFromISR+0x12c>
80154e0: a201 add r2, pc, #4 @ (adr r2, 80154e8 <xTaskGenericNotifyFromISR+0xb0>)
80154e2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80154e6: bf00 nop
80154e8: 08015585 .word 0x08015585
80154ec: 080154fd .word 0x080154fd
80154f0: 0801551b .word 0x0801551b
80154f4: 08015537 .word 0x08015537
80154f8: 08015547 .word 0x08015547
{
case eSetBits:
pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
80154fc: 6c3a ldr r2, [r7, #64] @ 0x40
80154fe: 68bb ldr r3, [r7, #8]
8015500: 3314 adds r3, #20
8015502: 009b lsls r3, r3, #2
8015504: 4413 add r3, r2
8015506: 685a ldr r2, [r3, #4]
8015508: 687b ldr r3, [r7, #4]
801550a: 431a orrs r2, r3
801550c: 6c39 ldr r1, [r7, #64] @ 0x40
801550e: 68bb ldr r3, [r7, #8]
8015510: 3314 adds r3, #20
8015512: 009b lsls r3, r3, #2
8015514: 440b add r3, r1
8015516: 605a str r2, [r3, #4]
break;
8015518: e037 b.n 801558a <xTaskGenericNotifyFromISR+0x152>
case eIncrement:
( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
801551a: 6c3a ldr r2, [r7, #64] @ 0x40
801551c: 68bb ldr r3, [r7, #8]
801551e: 3314 adds r3, #20
8015520: 009b lsls r3, r3, #2
8015522: 4413 add r3, r2
8015524: 685b ldr r3, [r3, #4]
8015526: 1c5a adds r2, r3, #1
8015528: 6c39 ldr r1, [r7, #64] @ 0x40
801552a: 68bb ldr r3, [r7, #8]
801552c: 3314 adds r3, #20
801552e: 009b lsls r3, r3, #2
8015530: 440b add r3, r1
8015532: 605a str r2, [r3, #4]
break;
8015534: e029 b.n 801558a <xTaskGenericNotifyFromISR+0x152>
case eSetValueWithOverwrite:
pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
8015536: 6c3a ldr r2, [r7, #64] @ 0x40
8015538: 68bb ldr r3, [r7, #8]
801553a: 3314 adds r3, #20
801553c: 009b lsls r3, r3, #2
801553e: 4413 add r3, r2
8015540: 687a ldr r2, [r7, #4]
8015542: 605a str r2, [r3, #4]
break;
8015544: e021 b.n 801558a <xTaskGenericNotifyFromISR+0x152>
case eSetValueWithoutOverwrite:
if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
8015546: f897 303b ldrb.w r3, [r7, #59] @ 0x3b
801554a: 2b02 cmp r3, #2
801554c: d007 beq.n 801555e <xTaskGenericNotifyFromISR+0x126>
{
pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
801554e: 6c3a ldr r2, [r7, #64] @ 0x40
8015550: 68bb ldr r3, [r7, #8]
8015552: 3314 adds r3, #20
8015554: 009b lsls r3, r3, #2
8015556: 4413 add r3, r2
8015558: 687a ldr r2, [r7, #4]
801555a: 605a str r2, [r3, #4]
{
/* The value could not be written to the task. */
xReturn = pdFAIL;
}
break;
801555c: e015 b.n 801558a <xTaskGenericNotifyFromISR+0x152>
xReturn = pdFAIL;
801555e: 2300 movs r3, #0
8015560: 647b str r3, [r7, #68] @ 0x44
break;
8015562: e012 b.n 801558a <xTaskGenericNotifyFromISR+0x152>
default:
/* Should not get here if all enums are handled.
* Artificially force an assert by testing a value the
* compiler can't assume is const. */
configASSERT( xTickCount == ( TickType_t ) 0 );
8015564: 4b61 ldr r3, [pc, #388] @ (80156ec <xTaskGenericNotifyFromISR+0x2b4>)
8015566: 681b ldr r3, [r3, #0]
8015568: 2b00 cmp r3, #0
801556a: d00d beq.n 8015588 <xTaskGenericNotifyFromISR+0x150>
__asm volatile
801556c: f04f 0350 mov.w r3, #80 @ 0x50
8015570: f383 8811 msr BASEPRI, r3
8015574: f3bf 8f6f isb sy
8015578: f3bf 8f4f dsb sy
801557c: 61bb str r3, [r7, #24]
}
801557e: bf00 nop
8015580: bf00 nop
8015582: e7fd b.n 8015580 <xTaskGenericNotifyFromISR+0x148>
break;
8015584: bf00 nop
8015586: e000 b.n 801558a <xTaskGenericNotifyFromISR+0x152>
break;
8015588: bf00 nop
traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify );
/* If the task is in the blocked state specifically to wait for a
* notification then unblock it now. */
if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
801558a: f897 303b ldrb.w r3, [r7, #59] @ 0x3b
801558e: 2b01 cmp r3, #1
8015590: f040 80a0 bne.w 80156d4 <xTaskGenericNotifyFromISR+0x29c>
{
/* The task should not have been on an event list. */
configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
8015594: 6c3b ldr r3, [r7, #64] @ 0x40
8015596: 6a9b ldr r3, [r3, #40] @ 0x28
8015598: 2b00 cmp r3, #0
801559a: d00b beq.n 80155b4 <xTaskGenericNotifyFromISR+0x17c>
__asm volatile
801559c: f04f 0350 mov.w r3, #80 @ 0x50
80155a0: f383 8811 msr BASEPRI, r3
80155a4: f3bf 8f6f isb sy
80155a8: f3bf 8f4f dsb sy
80155ac: 617b str r3, [r7, #20]
}
80155ae: bf00 nop
80155b0: bf00 nop
80155b2: e7fd b.n 80155b0 <xTaskGenericNotifyFromISR+0x178>
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
80155b4: 4b4e ldr r3, [pc, #312] @ (80156f0 <xTaskGenericNotifyFromISR+0x2b8>)
80155b6: 681b ldr r3, [r3, #0]
80155b8: 2b00 cmp r3, #0
80155ba: d15f bne.n 801567c <xTaskGenericNotifyFromISR+0x244>
{
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
80155bc: 6c3b ldr r3, [r7, #64] @ 0x40
80155be: 695b ldr r3, [r3, #20]
80155c0: 633b str r3, [r7, #48] @ 0x30
80155c2: 6c3b ldr r3, [r7, #64] @ 0x40
80155c4: 689b ldr r3, [r3, #8]
80155c6: 6c3a ldr r2, [r7, #64] @ 0x40
80155c8: 68d2 ldr r2, [r2, #12]
80155ca: 609a str r2, [r3, #8]
80155cc: 6c3b ldr r3, [r7, #64] @ 0x40
80155ce: 68db ldr r3, [r3, #12]
80155d0: 6c3a ldr r2, [r7, #64] @ 0x40
80155d2: 6892 ldr r2, [r2, #8]
80155d4: 605a str r2, [r3, #4]
80155d6: 6b3b ldr r3, [r7, #48] @ 0x30
80155d8: 685a ldr r2, [r3, #4]
80155da: 6c3b ldr r3, [r7, #64] @ 0x40
80155dc: 3304 adds r3, #4
80155de: 429a cmp r2, r3
80155e0: d103 bne.n 80155ea <xTaskGenericNotifyFromISR+0x1b2>
80155e2: 6c3b ldr r3, [r7, #64] @ 0x40
80155e4: 68da ldr r2, [r3, #12]
80155e6: 6b3b ldr r3, [r7, #48] @ 0x30
80155e8: 605a str r2, [r3, #4]
80155ea: 6c3b ldr r3, [r7, #64] @ 0x40
80155ec: 2200 movs r2, #0
80155ee: 615a str r2, [r3, #20]
80155f0: 6b3b ldr r3, [r7, #48] @ 0x30
80155f2: 681b ldr r3, [r3, #0]
80155f4: 1e5a subs r2, r3, #1
80155f6: 6b3b ldr r3, [r7, #48] @ 0x30
80155f8: 601a str r2, [r3, #0]
prvAddTaskToReadyList( pxTCB );
80155fa: 6c3b ldr r3, [r7, #64] @ 0x40
80155fc: 6ada ldr r2, [r3, #44] @ 0x2c
80155fe: 4b3d ldr r3, [pc, #244] @ (80156f4 <xTaskGenericNotifyFromISR+0x2bc>)
8015600: 681b ldr r3, [r3, #0]
8015602: 429a cmp r2, r3
8015604: d903 bls.n 801560e <xTaskGenericNotifyFromISR+0x1d6>
8015606: 6c3b ldr r3, [r7, #64] @ 0x40
8015608: 6adb ldr r3, [r3, #44] @ 0x2c
801560a: 4a3a ldr r2, [pc, #232] @ (80156f4 <xTaskGenericNotifyFromISR+0x2bc>)
801560c: 6013 str r3, [r2, #0]
801560e: 6c3b ldr r3, [r7, #64] @ 0x40
8015610: 6ada ldr r2, [r3, #44] @ 0x2c
8015612: 4939 ldr r1, [pc, #228] @ (80156f8 <xTaskGenericNotifyFromISR+0x2c0>)
8015614: 4613 mov r3, r2
8015616: 009b lsls r3, r3, #2
8015618: 4413 add r3, r2
801561a: 009b lsls r3, r3, #2
801561c: 440b add r3, r1
801561e: 3304 adds r3, #4
8015620: 681b ldr r3, [r3, #0]
8015622: 62fb str r3, [r7, #44] @ 0x2c
8015624: 6c3b ldr r3, [r7, #64] @ 0x40
8015626: 6afa ldr r2, [r7, #44] @ 0x2c
8015628: 609a str r2, [r3, #8]
801562a: 6afb ldr r3, [r7, #44] @ 0x2c
801562c: 689a ldr r2, [r3, #8]
801562e: 6c3b ldr r3, [r7, #64] @ 0x40
8015630: 60da str r2, [r3, #12]
8015632: 6afb ldr r3, [r7, #44] @ 0x2c
8015634: 689b ldr r3, [r3, #8]
8015636: 6c3a ldr r2, [r7, #64] @ 0x40
8015638: 3204 adds r2, #4
801563a: 605a str r2, [r3, #4]
801563c: 6c3b ldr r3, [r7, #64] @ 0x40
801563e: 1d1a adds r2, r3, #4
8015640: 6afb ldr r3, [r7, #44] @ 0x2c
8015642: 609a str r2, [r3, #8]
8015644: 6c3b ldr r3, [r7, #64] @ 0x40
8015646: 6ada ldr r2, [r3, #44] @ 0x2c
8015648: 4613 mov r3, r2
801564a: 009b lsls r3, r3, #2
801564c: 4413 add r3, r2
801564e: 009b lsls r3, r3, #2
8015650: 4a29 ldr r2, [pc, #164] @ (80156f8 <xTaskGenericNotifyFromISR+0x2c0>)
8015652: 441a add r2, r3
8015654: 6c3b ldr r3, [r7, #64] @ 0x40
8015656: 615a str r2, [r3, #20]
8015658: 6c3b ldr r3, [r7, #64] @ 0x40
801565a: 6ada ldr r2, [r3, #44] @ 0x2c
801565c: 4926 ldr r1, [pc, #152] @ (80156f8 <xTaskGenericNotifyFromISR+0x2c0>)
801565e: 4613 mov r3, r2
8015660: 009b lsls r3, r3, #2
8015662: 4413 add r3, r2
8015664: 009b lsls r3, r3, #2
8015666: 440b add r3, r1
8015668: 681b ldr r3, [r3, #0]
801566a: 1c59 adds r1, r3, #1
801566c: 4822 ldr r0, [pc, #136] @ (80156f8 <xTaskGenericNotifyFromISR+0x2c0>)
801566e: 4613 mov r3, r2
8015670: 009b lsls r3, r3, #2
8015672: 4413 add r3, r2
8015674: 009b lsls r3, r3, #2
8015676: 4403 add r3, r0
8015678: 6019 str r1, [r3, #0]
801567a: e01b b.n 80156b4 <xTaskGenericNotifyFromISR+0x27c>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold
* this task pending until the scheduler is resumed. */
listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
801567c: 4b1f ldr r3, [pc, #124] @ (80156fc <xTaskGenericNotifyFromISR+0x2c4>)
801567e: 685b ldr r3, [r3, #4]
8015680: 637b str r3, [r7, #52] @ 0x34
8015682: 6c3b ldr r3, [r7, #64] @ 0x40
8015684: 6b7a ldr r2, [r7, #52] @ 0x34
8015686: 61da str r2, [r3, #28]
8015688: 6b7b ldr r3, [r7, #52] @ 0x34
801568a: 689a ldr r2, [r3, #8]
801568c: 6c3b ldr r3, [r7, #64] @ 0x40
801568e: 621a str r2, [r3, #32]
8015690: 6b7b ldr r3, [r7, #52] @ 0x34
8015692: 689b ldr r3, [r3, #8]
8015694: 6c3a ldr r2, [r7, #64] @ 0x40
8015696: 3218 adds r2, #24
8015698: 605a str r2, [r3, #4]
801569a: 6c3b ldr r3, [r7, #64] @ 0x40
801569c: f103 0218 add.w r2, r3, #24
80156a0: 6b7b ldr r3, [r7, #52] @ 0x34
80156a2: 609a str r2, [r3, #8]
80156a4: 6c3b ldr r3, [r7, #64] @ 0x40
80156a6: 4a15 ldr r2, [pc, #84] @ (80156fc <xTaskGenericNotifyFromISR+0x2c4>)
80156a8: 629a str r2, [r3, #40] @ 0x28
80156aa: 4b14 ldr r3, [pc, #80] @ (80156fc <xTaskGenericNotifyFromISR+0x2c4>)
80156ac: 681b ldr r3, [r3, #0]
80156ae: 3301 adds r3, #1
80156b0: 4a12 ldr r2, [pc, #72] @ (80156fc <xTaskGenericNotifyFromISR+0x2c4>)
80156b2: 6013 str r3, [r2, #0]
}
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
80156b4: 6c3b ldr r3, [r7, #64] @ 0x40
80156b6: 6ada ldr r2, [r3, #44] @ 0x2c
80156b8: 4b11 ldr r3, [pc, #68] @ (8015700 <xTaskGenericNotifyFromISR+0x2c8>)
80156ba: 681b ldr r3, [r3, #0]
80156bc: 6adb ldr r3, [r3, #44] @ 0x2c
80156be: 429a cmp r2, r3
80156c0: d908 bls.n 80156d4 <xTaskGenericNotifyFromISR+0x29c>
{
/* The notified task has a priority above the currently
* executing task so a yield is required. */
if( pxHigherPriorityTaskWoken != NULL )
80156c2: 6d7b ldr r3, [r7, #84] @ 0x54
80156c4: 2b00 cmp r3, #0
80156c6: d002 beq.n 80156ce <xTaskGenericNotifyFromISR+0x296>
{
*pxHigherPriorityTaskWoken = pdTRUE;
80156c8: 6d7b ldr r3, [r7, #84] @ 0x54
80156ca: 2201 movs r2, #1
80156cc: 601a str r2, [r3, #0]
}
/* Mark that a yield is pending in case the user is not
* using the "xHigherPriorityTaskWoken" parameter to an ISR
* safe FreeRTOS function. */
xYieldPending = pdTRUE;
80156ce: 4b0d ldr r3, [pc, #52] @ (8015704 <xTaskGenericNotifyFromISR+0x2cc>)
80156d0: 2201 movs r2, #1
80156d2: 601a str r2, [r3, #0]
80156d4: 6bfb ldr r3, [r7, #60] @ 0x3c
80156d6: 613b str r3, [r7, #16]
__asm volatile
80156d8: 693b ldr r3, [r7, #16]
80156da: f383 8811 msr BASEPRI, r3
}
80156de: bf00 nop
}
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
80156e0: 6c7b ldr r3, [r7, #68] @ 0x44
}
80156e2: 4618 mov r0, r3
80156e4: 3748 adds r7, #72 @ 0x48
80156e6: 46bd mov sp, r7
80156e8: bd80 pop {r7, pc}
80156ea: bf00 nop
80156ec: 200025a0 .word 0x200025a0
80156f0: 200025c4 .word 0x200025c4
80156f4: 200025a4 .word 0x200025a4
80156f8: 200020cc .word 0x200020cc
80156fc: 2000255c .word 0x2000255c
8015700: 200020c8 .word 0x200020c8
8015704: 200025b0 .word 0x200025b0
08015708 <vTaskGenericNotifyGiveFromISR>:
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
UBaseType_t uxIndexToNotify,
BaseType_t * pxHigherPriorityTaskWoken )
{
8015708: b580 push {r7, lr}
801570a: b090 sub sp, #64 @ 0x40
801570c: af00 add r7, sp, #0
801570e: 60f8 str r0, [r7, #12]
8015710: 60b9 str r1, [r7, #8]
8015712: 607a str r2, [r7, #4]
TCB_t * pxTCB;
uint8_t ucOriginalNotifyState;
UBaseType_t uxSavedInterruptStatus;
configASSERT( xTaskToNotify );
8015714: 68fb ldr r3, [r7, #12]
8015716: 2b00 cmp r3, #0
8015718: d10b bne.n 8015732 <vTaskGenericNotifyGiveFromISR+0x2a>
__asm volatile
801571a: f04f 0350 mov.w r3, #80 @ 0x50
801571e: f383 8811 msr BASEPRI, r3
8015722: f3bf 8f6f isb sy
8015726: f3bf 8f4f dsb sy
801572a: 627b str r3, [r7, #36] @ 0x24
}
801572c: bf00 nop
801572e: bf00 nop
8015730: e7fd b.n 801572e <vTaskGenericNotifyGiveFromISR+0x26>
configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
8015732: 68bb ldr r3, [r7, #8]
8015734: 2b00 cmp r3, #0
8015736: d00b beq.n 8015750 <vTaskGenericNotifyGiveFromISR+0x48>
__asm volatile
8015738: f04f 0350 mov.w r3, #80 @ 0x50
801573c: f383 8811 msr BASEPRI, r3
8015740: f3bf 8f6f isb sy
8015744: f3bf 8f4f dsb sy
8015748: 623b str r3, [r7, #32]
}
801574a: bf00 nop
801574c: bf00 nop
801574e: e7fd b.n 801574c <vTaskGenericNotifyGiveFromISR+0x44>
* below the maximum system call interrupt priority. FreeRTOS maintains a
* separate interrupt safe API to ensure interrupt entry is as fast and as
* simple as possible. More information (albeit Cortex-M specific) is
* provided on the following link:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
8015750: f000 fe4c bl 80163ec <vPortValidateInterruptPriority>
pxTCB = xTaskToNotify;
8015754: 68fb ldr r3, [r7, #12]
8015756: 63fb str r3, [r7, #60] @ 0x3c
__asm volatile
8015758: f3ef 8211 mrs r2, BASEPRI
801575c: f04f 0350 mov.w r3, #80 @ 0x50
8015760: f383 8811 msr BASEPRI, r3
8015764: f3bf 8f6f isb sy
8015768: f3bf 8f4f dsb sy
801576c: 61fa str r2, [r7, #28]
801576e: 61bb str r3, [r7, #24]
return ulOriginalBASEPRI;
8015770: 69fb ldr r3, [r7, #28]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
8015772: 63bb str r3, [r7, #56] @ 0x38
{
ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
8015774: 6bfa ldr r2, [r7, #60] @ 0x3c
8015776: 68bb ldr r3, [r7, #8]
8015778: 4413 add r3, r2
801577a: 3358 adds r3, #88 @ 0x58
801577c: 781b ldrb r3, [r3, #0]
801577e: f887 3037 strb.w r3, [r7, #55] @ 0x37
pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
8015782: 6bfa ldr r2, [r7, #60] @ 0x3c
8015784: 68bb ldr r3, [r7, #8]
8015786: 4413 add r3, r2
8015788: 3358 adds r3, #88 @ 0x58
801578a: 2202 movs r2, #2
801578c: 701a strb r2, [r3, #0]
/* 'Giving' is equivalent to incrementing a count in a counting
* semaphore. */
( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
801578e: 6bfa ldr r2, [r7, #60] @ 0x3c
8015790: 68bb ldr r3, [r7, #8]
8015792: 3314 adds r3, #20
8015794: 009b lsls r3, r3, #2
8015796: 4413 add r3, r2
8015798: 685b ldr r3, [r3, #4]
801579a: 1c5a adds r2, r3, #1
801579c: 6bf9 ldr r1, [r7, #60] @ 0x3c
801579e: 68bb ldr r3, [r7, #8]
80157a0: 3314 adds r3, #20
80157a2: 009b lsls r3, r3, #2
80157a4: 440b add r3, r1
80157a6: 605a str r2, [r3, #4]
traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify );
/* If the task is in the blocked state specifically to wait for a
* notification then unblock it now. */
if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
80157a8: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
80157ac: 2b01 cmp r3, #1
80157ae: f040 80a0 bne.w 80158f2 <vTaskGenericNotifyGiveFromISR+0x1ea>
{
/* The task should not have been on an event list. */
configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
80157b2: 6bfb ldr r3, [r7, #60] @ 0x3c
80157b4: 6a9b ldr r3, [r3, #40] @ 0x28
80157b6: 2b00 cmp r3, #0
80157b8: d00b beq.n 80157d2 <vTaskGenericNotifyGiveFromISR+0xca>
__asm volatile
80157ba: f04f 0350 mov.w r3, #80 @ 0x50
80157be: f383 8811 msr BASEPRI, r3
80157c2: f3bf 8f6f isb sy
80157c6: f3bf 8f4f dsb sy
80157ca: 617b str r3, [r7, #20]
}
80157cc: bf00 nop
80157ce: bf00 nop
80157d0: e7fd b.n 80157ce <vTaskGenericNotifyGiveFromISR+0xc6>
if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
80157d2: 4b4d ldr r3, [pc, #308] @ (8015908 <vTaskGenericNotifyGiveFromISR+0x200>)
80157d4: 681b ldr r3, [r3, #0]
80157d6: 2b00 cmp r3, #0
80157d8: d15f bne.n 801589a <vTaskGenericNotifyGiveFromISR+0x192>
{
listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
80157da: 6bfb ldr r3, [r7, #60] @ 0x3c
80157dc: 695b ldr r3, [r3, #20]
80157de: 62fb str r3, [r7, #44] @ 0x2c
80157e0: 6bfb ldr r3, [r7, #60] @ 0x3c
80157e2: 689b ldr r3, [r3, #8]
80157e4: 6bfa ldr r2, [r7, #60] @ 0x3c
80157e6: 68d2 ldr r2, [r2, #12]
80157e8: 609a str r2, [r3, #8]
80157ea: 6bfb ldr r3, [r7, #60] @ 0x3c
80157ec: 68db ldr r3, [r3, #12]
80157ee: 6bfa ldr r2, [r7, #60] @ 0x3c
80157f0: 6892 ldr r2, [r2, #8]
80157f2: 605a str r2, [r3, #4]
80157f4: 6afb ldr r3, [r7, #44] @ 0x2c
80157f6: 685a ldr r2, [r3, #4]
80157f8: 6bfb ldr r3, [r7, #60] @ 0x3c
80157fa: 3304 adds r3, #4
80157fc: 429a cmp r2, r3
80157fe: d103 bne.n 8015808 <vTaskGenericNotifyGiveFromISR+0x100>
8015800: 6bfb ldr r3, [r7, #60] @ 0x3c
8015802: 68da ldr r2, [r3, #12]
8015804: 6afb ldr r3, [r7, #44] @ 0x2c
8015806: 605a str r2, [r3, #4]
8015808: 6bfb ldr r3, [r7, #60] @ 0x3c
801580a: 2200 movs r2, #0
801580c: 615a str r2, [r3, #20]
801580e: 6afb ldr r3, [r7, #44] @ 0x2c
8015810: 681b ldr r3, [r3, #0]
8015812: 1e5a subs r2, r3, #1
8015814: 6afb ldr r3, [r7, #44] @ 0x2c
8015816: 601a str r2, [r3, #0]
prvAddTaskToReadyList( pxTCB );
8015818: 6bfb ldr r3, [r7, #60] @ 0x3c
801581a: 6ada ldr r2, [r3, #44] @ 0x2c
801581c: 4b3b ldr r3, [pc, #236] @ (801590c <vTaskGenericNotifyGiveFromISR+0x204>)
801581e: 681b ldr r3, [r3, #0]
8015820: 429a cmp r2, r3
8015822: d903 bls.n 801582c <vTaskGenericNotifyGiveFromISR+0x124>
8015824: 6bfb ldr r3, [r7, #60] @ 0x3c
8015826: 6adb ldr r3, [r3, #44] @ 0x2c
8015828: 4a38 ldr r2, [pc, #224] @ (801590c <vTaskGenericNotifyGiveFromISR+0x204>)
801582a: 6013 str r3, [r2, #0]
801582c: 6bfb ldr r3, [r7, #60] @ 0x3c
801582e: 6ada ldr r2, [r3, #44] @ 0x2c
8015830: 4937 ldr r1, [pc, #220] @ (8015910 <vTaskGenericNotifyGiveFromISR+0x208>)
8015832: 4613 mov r3, r2
8015834: 009b lsls r3, r3, #2
8015836: 4413 add r3, r2
8015838: 009b lsls r3, r3, #2
801583a: 440b add r3, r1
801583c: 3304 adds r3, #4
801583e: 681b ldr r3, [r3, #0]
8015840: 62bb str r3, [r7, #40] @ 0x28
8015842: 6bfb ldr r3, [r7, #60] @ 0x3c
8015844: 6aba ldr r2, [r7, #40] @ 0x28
8015846: 609a str r2, [r3, #8]
8015848: 6abb ldr r3, [r7, #40] @ 0x28
801584a: 689a ldr r2, [r3, #8]
801584c: 6bfb ldr r3, [r7, #60] @ 0x3c
801584e: 60da str r2, [r3, #12]
8015850: 6abb ldr r3, [r7, #40] @ 0x28
8015852: 689b ldr r3, [r3, #8]
8015854: 6bfa ldr r2, [r7, #60] @ 0x3c
8015856: 3204 adds r2, #4
8015858: 605a str r2, [r3, #4]
801585a: 6bfb ldr r3, [r7, #60] @ 0x3c
801585c: 1d1a adds r2, r3, #4
801585e: 6abb ldr r3, [r7, #40] @ 0x28
8015860: 609a str r2, [r3, #8]
8015862: 6bfb ldr r3, [r7, #60] @ 0x3c
8015864: 6ada ldr r2, [r3, #44] @ 0x2c
8015866: 4613 mov r3, r2
8015868: 009b lsls r3, r3, #2
801586a: 4413 add r3, r2
801586c: 009b lsls r3, r3, #2
801586e: 4a28 ldr r2, [pc, #160] @ (8015910 <vTaskGenericNotifyGiveFromISR+0x208>)
8015870: 441a add r2, r3
8015872: 6bfb ldr r3, [r7, #60] @ 0x3c
8015874: 615a str r2, [r3, #20]
8015876: 6bfb ldr r3, [r7, #60] @ 0x3c
8015878: 6ada ldr r2, [r3, #44] @ 0x2c
801587a: 4925 ldr r1, [pc, #148] @ (8015910 <vTaskGenericNotifyGiveFromISR+0x208>)
801587c: 4613 mov r3, r2
801587e: 009b lsls r3, r3, #2
8015880: 4413 add r3, r2
8015882: 009b lsls r3, r3, #2
8015884: 440b add r3, r1
8015886: 681b ldr r3, [r3, #0]
8015888: 1c59 adds r1, r3, #1
801588a: 4821 ldr r0, [pc, #132] @ (8015910 <vTaskGenericNotifyGiveFromISR+0x208>)
801588c: 4613 mov r3, r2
801588e: 009b lsls r3, r3, #2
8015890: 4413 add r3, r2
8015892: 009b lsls r3, r3, #2
8015894: 4403 add r3, r0
8015896: 6019 str r1, [r3, #0]
8015898: e01b b.n 80158d2 <vTaskGenericNotifyGiveFromISR+0x1ca>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold
* this task pending until the scheduler is resumed. */
listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
801589a: 4b1e ldr r3, [pc, #120] @ (8015914 <vTaskGenericNotifyGiveFromISR+0x20c>)
801589c: 685b ldr r3, [r3, #4]
801589e: 633b str r3, [r7, #48] @ 0x30
80158a0: 6bfb ldr r3, [r7, #60] @ 0x3c
80158a2: 6b3a ldr r2, [r7, #48] @ 0x30
80158a4: 61da str r2, [r3, #28]
80158a6: 6b3b ldr r3, [r7, #48] @ 0x30
80158a8: 689a ldr r2, [r3, #8]
80158aa: 6bfb ldr r3, [r7, #60] @ 0x3c
80158ac: 621a str r2, [r3, #32]
80158ae: 6b3b ldr r3, [r7, #48] @ 0x30
80158b0: 689b ldr r3, [r3, #8]
80158b2: 6bfa ldr r2, [r7, #60] @ 0x3c
80158b4: 3218 adds r2, #24
80158b6: 605a str r2, [r3, #4]
80158b8: 6bfb ldr r3, [r7, #60] @ 0x3c
80158ba: f103 0218 add.w r2, r3, #24
80158be: 6b3b ldr r3, [r7, #48] @ 0x30
80158c0: 609a str r2, [r3, #8]
80158c2: 6bfb ldr r3, [r7, #60] @ 0x3c
80158c4: 4a13 ldr r2, [pc, #76] @ (8015914 <vTaskGenericNotifyGiveFromISR+0x20c>)
80158c6: 629a str r2, [r3, #40] @ 0x28
80158c8: 4b12 ldr r3, [pc, #72] @ (8015914 <vTaskGenericNotifyGiveFromISR+0x20c>)
80158ca: 681b ldr r3, [r3, #0]
80158cc: 3301 adds r3, #1
80158ce: 4a11 ldr r2, [pc, #68] @ (8015914 <vTaskGenericNotifyGiveFromISR+0x20c>)
80158d0: 6013 str r3, [r2, #0]
}
if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
80158d2: 6bfb ldr r3, [r7, #60] @ 0x3c
80158d4: 6ada ldr r2, [r3, #44] @ 0x2c
80158d6: 4b10 ldr r3, [pc, #64] @ (8015918 <vTaskGenericNotifyGiveFromISR+0x210>)
80158d8: 681b ldr r3, [r3, #0]
80158da: 6adb ldr r3, [r3, #44] @ 0x2c
80158dc: 429a cmp r2, r3
80158de: d908 bls.n 80158f2 <vTaskGenericNotifyGiveFromISR+0x1ea>
{
/* The notified task has a priority above the currently
* executing task so a yield is required. */
if( pxHigherPriorityTaskWoken != NULL )
80158e0: 687b ldr r3, [r7, #4]
80158e2: 2b00 cmp r3, #0
80158e4: d002 beq.n 80158ec <vTaskGenericNotifyGiveFromISR+0x1e4>
{
*pxHigherPriorityTaskWoken = pdTRUE;
80158e6: 687b ldr r3, [r7, #4]
80158e8: 2201 movs r2, #1
80158ea: 601a str r2, [r3, #0]
}
/* Mark that a yield is pending in case the user is not
* using the "xHigherPriorityTaskWoken" parameter in an ISR
* safe FreeRTOS function. */
xYieldPending = pdTRUE;
80158ec: 4b0b ldr r3, [pc, #44] @ (801591c <vTaskGenericNotifyGiveFromISR+0x214>)
80158ee: 2201 movs r2, #1
80158f0: 601a str r2, [r3, #0]
80158f2: 6bbb ldr r3, [r7, #56] @ 0x38
80158f4: 613b str r3, [r7, #16]
__asm volatile
80158f6: 693b ldr r3, [r7, #16]
80158f8: f383 8811 msr BASEPRI, r3
}
80158fc: bf00 nop
mtCOVERAGE_TEST_MARKER();
}
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
}
80158fe: bf00 nop
8015900: 3740 adds r7, #64 @ 0x40
8015902: 46bd mov sp, r7
8015904: bd80 pop {r7, pc}
8015906: bf00 nop
8015908: 200025c4 .word 0x200025c4
801590c: 200025a4 .word 0x200025a4
8015910: 200020cc .word 0x200020cc
8015914: 2000255c .word 0x2000255c
8015918: 200020c8 .word 0x200020c8
801591c: 200025b0 .word 0x200025b0
08015920 <prvAddCurrentTaskToDelayedList>:
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
const BaseType_t xCanBlockIndefinitely )
{
8015920: b580 push {r7, lr}
8015922: b086 sub sp, #24
8015924: af00 add r7, sp, #0
8015926: 6078 str r0, [r7, #4]
8015928: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
801592a: 4b2e ldr r3, [pc, #184] @ (80159e4 <prvAddCurrentTaskToDelayedList+0xc4>)
801592c: 681b ldr r3, [r3, #0]
801592e: 617b str r3, [r7, #20]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
* as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8015930: 4b2d ldr r3, [pc, #180] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
8015932: 681b ldr r3, [r3, #0]
8015934: 3304 adds r3, #4
8015936: 4618 mov r0, r3
8015938: f7fc fffc bl 8012934 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
801593c: 687b ldr r3, [r7, #4]
801593e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8015942: d124 bne.n 801598e <prvAddCurrentTaskToDelayedList+0x6e>
8015944: 683b ldr r3, [r7, #0]
8015946: 2b00 cmp r3, #0
8015948: d021 beq.n 801598e <prvAddCurrentTaskToDelayedList+0x6e>
{
/* Add the task to the suspended task list instead of a delayed task
* list to ensure it is not woken by a timing event. It will block
* indefinitely. */
listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
801594a: 4b28 ldr r3, [pc, #160] @ (80159ec <prvAddCurrentTaskToDelayedList+0xcc>)
801594c: 685b ldr r3, [r3, #4]
801594e: 613b str r3, [r7, #16]
8015950: 4b25 ldr r3, [pc, #148] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
8015952: 681b ldr r3, [r3, #0]
8015954: 693a ldr r2, [r7, #16]
8015956: 609a str r2, [r3, #8]
8015958: 4b23 ldr r3, [pc, #140] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
801595a: 681b ldr r3, [r3, #0]
801595c: 693a ldr r2, [r7, #16]
801595e: 6892 ldr r2, [r2, #8]
8015960: 60da str r2, [r3, #12]
8015962: 4b21 ldr r3, [pc, #132] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
8015964: 681a ldr r2, [r3, #0]
8015966: 693b ldr r3, [r7, #16]
8015968: 689b ldr r3, [r3, #8]
801596a: 3204 adds r2, #4
801596c: 605a str r2, [r3, #4]
801596e: 4b1e ldr r3, [pc, #120] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
8015970: 681b ldr r3, [r3, #0]
8015972: 1d1a adds r2, r3, #4
8015974: 693b ldr r3, [r7, #16]
8015976: 609a str r2, [r3, #8]
8015978: 4b1b ldr r3, [pc, #108] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
801597a: 681b ldr r3, [r3, #0]
801597c: 4a1b ldr r2, [pc, #108] @ (80159ec <prvAddCurrentTaskToDelayedList+0xcc>)
801597e: 615a str r2, [r3, #20]
8015980: 4b1a ldr r3, [pc, #104] @ (80159ec <prvAddCurrentTaskToDelayedList+0xcc>)
8015982: 681b ldr r3, [r3, #0]
8015984: 3301 adds r3, #1
8015986: 4a19 ldr r2, [pc, #100] @ (80159ec <prvAddCurrentTaskToDelayedList+0xcc>)
8015988: 6013 str r3, [r2, #0]
801598a: bf00 nop
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
801598c: e026 b.n 80159dc <prvAddCurrentTaskToDelayedList+0xbc>
xTimeToWake = xConstTickCount + xTicksToWait;
801598e: 697a ldr r2, [r7, #20]
8015990: 687b ldr r3, [r7, #4]
8015992: 4413 add r3, r2
8015994: 60fb str r3, [r7, #12]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
8015996: 4b14 ldr r3, [pc, #80] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
8015998: 681b ldr r3, [r3, #0]
801599a: 68fa ldr r2, [r7, #12]
801599c: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
801599e: 68fa ldr r2, [r7, #12]
80159a0: 697b ldr r3, [r7, #20]
80159a2: 429a cmp r2, r3
80159a4: d209 bcs.n 80159ba <prvAddCurrentTaskToDelayedList+0x9a>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
80159a6: 4b12 ldr r3, [pc, #72] @ (80159f0 <prvAddCurrentTaskToDelayedList+0xd0>)
80159a8: 681a ldr r2, [r3, #0]
80159aa: 4b0f ldr r3, [pc, #60] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
80159ac: 681b ldr r3, [r3, #0]
80159ae: 3304 adds r3, #4
80159b0: 4619 mov r1, r3
80159b2: 4610 mov r0, r2
80159b4: f7fc ff85 bl 80128c2 <vListInsert>
}
80159b8: e010 b.n 80159dc <prvAddCurrentTaskToDelayedList+0xbc>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
80159ba: 4b0e ldr r3, [pc, #56] @ (80159f4 <prvAddCurrentTaskToDelayedList+0xd4>)
80159bc: 681a ldr r2, [r3, #0]
80159be: 4b0a ldr r3, [pc, #40] @ (80159e8 <prvAddCurrentTaskToDelayedList+0xc8>)
80159c0: 681b ldr r3, [r3, #0]
80159c2: 3304 adds r3, #4
80159c4: 4619 mov r1, r3
80159c6: 4610 mov r0, r2
80159c8: f7fc ff7b bl 80128c2 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
80159cc: 4b0a ldr r3, [pc, #40] @ (80159f8 <prvAddCurrentTaskToDelayedList+0xd8>)
80159ce: 681b ldr r3, [r3, #0]
80159d0: 68fa ldr r2, [r7, #12]
80159d2: 429a cmp r2, r3
80159d4: d202 bcs.n 80159dc <prvAddCurrentTaskToDelayedList+0xbc>
xNextTaskUnblockTime = xTimeToWake;
80159d6: 4a08 ldr r2, [pc, #32] @ (80159f8 <prvAddCurrentTaskToDelayedList+0xd8>)
80159d8: 68fb ldr r3, [r7, #12]
80159da: 6013 str r3, [r2, #0]
}
80159dc: bf00 nop
80159de: 3718 adds r7, #24
80159e0: 46bd mov sp, r7
80159e2: bd80 pop {r7, pc}
80159e4: 200025a0 .word 0x200025a0
80159e8: 200020c8 .word 0x200020c8
80159ec: 20002588 .word 0x20002588
80159f0: 20002558 .word 0x20002558
80159f4: 20002554 .word 0x20002554
80159f8: 200025bc .word 0x200025bc
080159fc <xTimerCreateTimerTask>:
TimerCallbackFunction_t pxCallbackFunction,
Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
BaseType_t xTimerCreateTimerTask( void )
{
80159fc: b580 push {r7, lr}
80159fe: b08a sub sp, #40 @ 0x28
8015a00: af04 add r7, sp, #16
BaseType_t xReturn = pdFAIL;
8015a02: 2300 movs r3, #0
8015a04: 617b str r3, [r7, #20]
/* This function is called when the scheduler is started if
* configUSE_TIMERS is set to 1. Check that the infrastructure used by the
* timer service task has been created/initialised. If timers have already
* been created then the initialisation will already have been performed. */
prvCheckForValidListAndQueue();
8015a06: f000 fa81 bl 8015f0c <prvCheckForValidListAndQueue>
if( xTimerQueue != NULL )
8015a0a: 4b1d ldr r3, [pc, #116] @ (8015a80 <xTimerCreateTimerTask+0x84>)
8015a0c: 681b ldr r3, [r3, #0]
8015a0e: 2b00 cmp r3, #0
8015a10: d021 beq.n 8015a56 <xTimerCreateTimerTask+0x5a>
{
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t * pxTimerTaskTCBBuffer = NULL;
8015a12: 2300 movs r3, #0
8015a14: 60fb str r3, [r7, #12]
StackType_t * pxTimerTaskStackBuffer = NULL;
8015a16: 2300 movs r3, #0
8015a18: 60bb str r3, [r7, #8]
uint32_t ulTimerTaskStackSize;
vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
8015a1a: 1d3a adds r2, r7, #4
8015a1c: f107 0108 add.w r1, r7, #8
8015a20: f107 030c add.w r3, r7, #12
8015a24: 4618 mov r0, r3
8015a26: f7fc ff05 bl 8012834 <vApplicationGetTimerTaskMemory>
xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
8015a2a: 6879 ldr r1, [r7, #4]
8015a2c: 68bb ldr r3, [r7, #8]
8015a2e: 68fa ldr r2, [r7, #12]
8015a30: 9202 str r2, [sp, #8]
8015a32: 9301 str r3, [sp, #4]
8015a34: 2302 movs r3, #2
8015a36: 9300 str r3, [sp, #0]
8015a38: 2300 movs r3, #0
8015a3a: 460a mov r2, r1
8015a3c: 4911 ldr r1, [pc, #68] @ (8015a84 <xTimerCreateTimerTask+0x88>)
8015a3e: 4812 ldr r0, [pc, #72] @ (8015a88 <xTimerCreateTimerTask+0x8c>)
8015a40: f7fe f90c bl 8013c5c <xTaskCreateStatic>
8015a44: 4603 mov r3, r0
8015a46: 4a11 ldr r2, [pc, #68] @ (8015a8c <xTimerCreateTimerTask+0x90>)
8015a48: 6013 str r3, [r2, #0]
NULL,
( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
pxTimerTaskStackBuffer,
pxTimerTaskTCBBuffer );
if( xTimerTaskHandle != NULL )
8015a4a: 4b10 ldr r3, [pc, #64] @ (8015a8c <xTimerCreateTimerTask+0x90>)
8015a4c: 681b ldr r3, [r3, #0]
8015a4e: 2b00 cmp r3, #0
8015a50: d001 beq.n 8015a56 <xTimerCreateTimerTask+0x5a>
{
xReturn = pdPASS;
8015a52: 2301 movs r3, #1
8015a54: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
configASSERT( xReturn );
8015a56: 697b ldr r3, [r7, #20]
8015a58: 2b00 cmp r3, #0
8015a5a: d10b bne.n 8015a74 <xTimerCreateTimerTask+0x78>
__asm volatile
8015a5c: f04f 0350 mov.w r3, #80 @ 0x50
8015a60: f383 8811 msr BASEPRI, r3
8015a64: f3bf 8f6f isb sy
8015a68: f3bf 8f4f dsb sy
8015a6c: 613b str r3, [r7, #16]
}
8015a6e: bf00 nop
8015a70: bf00 nop
8015a72: e7fd b.n 8015a70 <xTimerCreateTimerTask+0x74>
return xReturn;
8015a74: 697b ldr r3, [r7, #20]
}
8015a76: 4618 mov r0, r3
8015a78: 3718 adds r7, #24
8015a7a: 46bd mov sp, r7
8015a7c: bd80 pop {r7, pc}
8015a7e: bf00 nop
8015a80: 200025f8 .word 0x200025f8
8015a84: 0801c4d0 .word 0x0801c4d0
8015a88: 08015b35 .word 0x08015b35
8015a8c: 200025fc .word 0x200025fc
08015a90 <prvReloadTimer>:
/*-----------------------------------------------------------*/
static void prvReloadTimer( Timer_t * const pxTimer,
TickType_t xExpiredTime,
const TickType_t xTimeNow )
{
8015a90: b580 push {r7, lr}
8015a92: b084 sub sp, #16
8015a94: af00 add r7, sp, #0
8015a96: 60f8 str r0, [r7, #12]
8015a98: 60b9 str r1, [r7, #8]
8015a9a: 607a str r2, [r7, #4]
/* Insert the timer into the appropriate list for the next expiry time.
* If the next expiry time has already passed, advance the expiry time,
* call the callback function, and try again. */
while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE )
8015a9c: e008 b.n 8015ab0 <prvReloadTimer+0x20>
{
/* Advance the expiry time. */
xExpiredTime += pxTimer->xTimerPeriodInTicks;
8015a9e: 68fb ldr r3, [r7, #12]
8015aa0: 699b ldr r3, [r3, #24]
8015aa2: 68ba ldr r2, [r7, #8]
8015aa4: 4413 add r3, r2
8015aa6: 60bb str r3, [r7, #8]
/* Call the timer callback. */
traceTIMER_EXPIRED( pxTimer );
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8015aa8: 68fb ldr r3, [r7, #12]
8015aaa: 6a1b ldr r3, [r3, #32]
8015aac: 68f8 ldr r0, [r7, #12]
8015aae: 4798 blx r3
while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE )
8015ab0: 68fb ldr r3, [r7, #12]
8015ab2: 699a ldr r2, [r3, #24]
8015ab4: 68bb ldr r3, [r7, #8]
8015ab6: 18d1 adds r1, r2, r3
8015ab8: 68bb ldr r3, [r7, #8]
8015aba: 687a ldr r2, [r7, #4]
8015abc: 68f8 ldr r0, [r7, #12]
8015abe: f000 f8df bl 8015c80 <prvInsertTimerInActiveList>
8015ac2: 4603 mov r3, r0
8015ac4: 2b00 cmp r3, #0
8015ac6: d1ea bne.n 8015a9e <prvReloadTimer+0xe>
}
}
8015ac8: bf00 nop
8015aca: bf00 nop
8015acc: 3710 adds r7, #16
8015ace: 46bd mov sp, r7
8015ad0: bd80 pop {r7, pc}
...
08015ad4 <prvProcessExpiredTimer>:
/*-----------------------------------------------------------*/
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
const TickType_t xTimeNow )
{
8015ad4: b580 push {r7, lr}
8015ad6: b084 sub sp, #16
8015ad8: af00 add r7, sp, #0
8015ada: 6078 str r0, [r7, #4]
8015adc: 6039 str r1, [r7, #0]
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8015ade: 4b14 ldr r3, [pc, #80] @ (8015b30 <prvProcessExpiredTimer+0x5c>)
8015ae0: 681b ldr r3, [r3, #0]
8015ae2: 68db ldr r3, [r3, #12]
8015ae4: 68db ldr r3, [r3, #12]
8015ae6: 60fb str r3, [r7, #12]
/* Remove the timer from the list of active timers. A check has already
* been performed to ensure the list is not empty. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8015ae8: 68fb ldr r3, [r7, #12]
8015aea: 3304 adds r3, #4
8015aec: 4618 mov r0, r3
8015aee: f7fc ff21 bl 8012934 <uxListRemove>
/* If the timer is an auto-reload timer then calculate the next
* expiry time and re-insert the timer in the list of active timers. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
8015af2: 68fb ldr r3, [r7, #12]
8015af4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015af8: f003 0304 and.w r3, r3, #4
8015afc: 2b00 cmp r3, #0
8015afe: d005 beq.n 8015b0c <prvProcessExpiredTimer+0x38>
{
prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow );
8015b00: 683a ldr r2, [r7, #0]
8015b02: 6879 ldr r1, [r7, #4]
8015b04: 68f8 ldr r0, [r7, #12]
8015b06: f7ff ffc3 bl 8015a90 <prvReloadTimer>
8015b0a: e008 b.n 8015b1e <prvProcessExpiredTimer+0x4a>
}
else
{
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
8015b0c: 68fb ldr r3, [r7, #12]
8015b0e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015b12: f023 0301 bic.w r3, r3, #1
8015b16: b2da uxtb r2, r3
8015b18: 68fb ldr r3, [r7, #12]
8015b1a: f883 2028 strb.w r2, [r3, #40] @ 0x28
}
/* Call the timer callback. */
traceTIMER_EXPIRED( pxTimer );
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8015b1e: 68fb ldr r3, [r7, #12]
8015b20: 6a1b ldr r3, [r3, #32]
8015b22: 68f8 ldr r0, [r7, #12]
8015b24: 4798 blx r3
}
8015b26: bf00 nop
8015b28: 3710 adds r7, #16
8015b2a: 46bd mov sp, r7
8015b2c: bd80 pop {r7, pc}
8015b2e: bf00 nop
8015b30: 200025f0 .word 0x200025f0
08015b34 <prvTimerTask>:
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
8015b34: b580 push {r7, lr}
8015b36: b084 sub sp, #16
8015b38: af00 add r7, sp, #0
8015b3a: 6078 str r0, [r7, #4]
for( ; ; )
{
/* Query the timers list to see if it contains any timers, and if so,
* obtain the time at which the next timer will expire. */
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
8015b3c: f107 0308 add.w r3, r7, #8
8015b40: 4618 mov r0, r3
8015b42: f000 f859 bl 8015bf8 <prvGetNextExpireTime>
8015b46: 60f8 str r0, [r7, #12]
/* If a timer has expired, process it. Otherwise, block this task
* until either a timer does expire, or a command is received. */
prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
8015b48: 68bb ldr r3, [r7, #8]
8015b4a: 4619 mov r1, r3
8015b4c: 68f8 ldr r0, [r7, #12]
8015b4e: f000 f805 bl 8015b5c <prvProcessTimerOrBlockTask>
/* Empty the command queue. */
prvProcessReceivedCommands();
8015b52: f000 f8d7 bl 8015d04 <prvProcessReceivedCommands>
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
8015b56: bf00 nop
8015b58: e7f0 b.n 8015b3c <prvTimerTask+0x8>
...
08015b5c <prvProcessTimerOrBlockTask>:
}
/*-----------------------------------------------------------*/
static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
BaseType_t xListWasEmpty )
{
8015b5c: b580 push {r7, lr}
8015b5e: b084 sub sp, #16
8015b60: af00 add r7, sp, #0
8015b62: 6078 str r0, [r7, #4]
8015b64: 6039 str r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;
vTaskSuspendAll();
8015b66: f7fe faf3 bl 8014150 <vTaskSuspendAll>
/* Obtain the time now to make an assessment as to whether the timer
* has expired or not. If obtaining the time causes the lists to switch
* then don't process this timer as any timers that remained in the list
* when the lists were switched will have been processed within the
* prvSampleTimeNow() function. */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
8015b6a: f107 0308 add.w r3, r7, #8
8015b6e: 4618 mov r0, r3
8015b70: f000 f866 bl 8015c40 <prvSampleTimeNow>
8015b74: 60f8 str r0, [r7, #12]
if( xTimerListsWereSwitched == pdFALSE )
8015b76: 68bb ldr r3, [r7, #8]
8015b78: 2b00 cmp r3, #0
8015b7a: d130 bne.n 8015bde <prvProcessTimerOrBlockTask+0x82>
{
/* The tick count has not overflowed, has the timer expired? */
if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
8015b7c: 683b ldr r3, [r7, #0]
8015b7e: 2b00 cmp r3, #0
8015b80: d10a bne.n 8015b98 <prvProcessTimerOrBlockTask+0x3c>
8015b82: 687a ldr r2, [r7, #4]
8015b84: 68fb ldr r3, [r7, #12]
8015b86: 429a cmp r2, r3
8015b88: d806 bhi.n 8015b98 <prvProcessTimerOrBlockTask+0x3c>
{
( void ) xTaskResumeAll();
8015b8a: f7fe faef bl 801416c <xTaskResumeAll>
prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
8015b8e: 68f9 ldr r1, [r7, #12]
8015b90: 6878 ldr r0, [r7, #4]
8015b92: f7ff ff9f bl 8015ad4 <prvProcessExpiredTimer>
else
{
( void ) xTaskResumeAll();
}
}
}
8015b96: e024 b.n 8015be2 <prvProcessTimerOrBlockTask+0x86>
if( xListWasEmpty != pdFALSE )
8015b98: 683b ldr r3, [r7, #0]
8015b9a: 2b00 cmp r3, #0
8015b9c: d008 beq.n 8015bb0 <prvProcessTimerOrBlockTask+0x54>
xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
8015b9e: 4b13 ldr r3, [pc, #76] @ (8015bec <prvProcessTimerOrBlockTask+0x90>)
8015ba0: 681b ldr r3, [r3, #0]
8015ba2: 681b ldr r3, [r3, #0]
8015ba4: 2b00 cmp r3, #0
8015ba6: d101 bne.n 8015bac <prvProcessTimerOrBlockTask+0x50>
8015ba8: 2301 movs r3, #1
8015baa: e000 b.n 8015bae <prvProcessTimerOrBlockTask+0x52>
8015bac: 2300 movs r3, #0
8015bae: 603b str r3, [r7, #0]
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
8015bb0: 4b0f ldr r3, [pc, #60] @ (8015bf0 <prvProcessTimerOrBlockTask+0x94>)
8015bb2: 6818 ldr r0, [r3, #0]
8015bb4: 687a ldr r2, [r7, #4]
8015bb6: 68fb ldr r3, [r7, #12]
8015bb8: 1ad3 subs r3, r2, r3
8015bba: 683a ldr r2, [r7, #0]
8015bbc: 4619 mov r1, r3
8015bbe: f7fe f819 bl 8013bf4 <vQueueWaitForMessageRestricted>
if( xTaskResumeAll() == pdFALSE )
8015bc2: f7fe fad3 bl 801416c <xTaskResumeAll>
8015bc6: 4603 mov r3, r0
8015bc8: 2b00 cmp r3, #0
8015bca: d10a bne.n 8015be2 <prvProcessTimerOrBlockTask+0x86>
portYIELD_WITHIN_API();
8015bcc: 4b09 ldr r3, [pc, #36] @ (8015bf4 <prvProcessTimerOrBlockTask+0x98>)
8015bce: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8015bd2: 601a str r2, [r3, #0]
8015bd4: f3bf 8f4f dsb sy
8015bd8: f3bf 8f6f isb sy
}
8015bdc: e001 b.n 8015be2 <prvProcessTimerOrBlockTask+0x86>
( void ) xTaskResumeAll();
8015bde: f7fe fac5 bl 801416c <xTaskResumeAll>
}
8015be2: bf00 nop
8015be4: 3710 adds r7, #16
8015be6: 46bd mov sp, r7
8015be8: bd80 pop {r7, pc}
8015bea: bf00 nop
8015bec: 200025f4 .word 0x200025f4
8015bf0: 200025f8 .word 0x200025f8
8015bf4: e000ed04 .word 0xe000ed04
08015bf8 <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/
static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
8015bf8: b480 push {r7}
8015bfa: b085 sub sp, #20
8015bfc: af00 add r7, sp, #0
8015bfe: 6078 str r0, [r7, #4]
* the timer with the nearest expiry time will expire. If there are no
* active timers then just set the next expire time to 0. That will cause
* this task to unblock when the tick count overflows, at which point the
* timer lists will be switched and the next expiry time can be
* re-assessed. */
*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
8015c00: 4b0e ldr r3, [pc, #56] @ (8015c3c <prvGetNextExpireTime+0x44>)
8015c02: 681b ldr r3, [r3, #0]
8015c04: 681b ldr r3, [r3, #0]
8015c06: 2b00 cmp r3, #0
8015c08: d101 bne.n 8015c0e <prvGetNextExpireTime+0x16>
8015c0a: 2201 movs r2, #1
8015c0c: e000 b.n 8015c10 <prvGetNextExpireTime+0x18>
8015c0e: 2200 movs r2, #0
8015c10: 687b ldr r3, [r7, #4]
8015c12: 601a str r2, [r3, #0]
if( *pxListWasEmpty == pdFALSE )
8015c14: 687b ldr r3, [r7, #4]
8015c16: 681b ldr r3, [r3, #0]
8015c18: 2b00 cmp r3, #0
8015c1a: d105 bne.n 8015c28 <prvGetNextExpireTime+0x30>
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
8015c1c: 4b07 ldr r3, [pc, #28] @ (8015c3c <prvGetNextExpireTime+0x44>)
8015c1e: 681b ldr r3, [r3, #0]
8015c20: 68db ldr r3, [r3, #12]
8015c22: 681b ldr r3, [r3, #0]
8015c24: 60fb str r3, [r7, #12]
8015c26: e001 b.n 8015c2c <prvGetNextExpireTime+0x34>
}
else
{
/* Ensure the task unblocks when the tick count rolls over. */
xNextExpireTime = ( TickType_t ) 0U;
8015c28: 2300 movs r3, #0
8015c2a: 60fb str r3, [r7, #12]
}
return xNextExpireTime;
8015c2c: 68fb ldr r3, [r7, #12]
}
8015c2e: 4618 mov r0, r3
8015c30: 3714 adds r7, #20
8015c32: 46bd mov sp, r7
8015c34: f85d 7b04 ldr.w r7, [sp], #4
8015c38: 4770 bx lr
8015c3a: bf00 nop
8015c3c: 200025f0 .word 0x200025f0
08015c40 <prvSampleTimeNow>:
/*-----------------------------------------------------------*/
static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
8015c40: b580 push {r7, lr}
8015c42: b084 sub sp, #16
8015c44: af00 add r7, sp, #0
8015c46: 6078 str r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
xTimeNow = xTaskGetTickCount();
8015c48: f7fe fb8e bl 8014368 <xTaskGetTickCount>
8015c4c: 60f8 str r0, [r7, #12]
if( xTimeNow < xLastTime )
8015c4e: 4b0b ldr r3, [pc, #44] @ (8015c7c <prvSampleTimeNow+0x3c>)
8015c50: 681b ldr r3, [r3, #0]
8015c52: 68fa ldr r2, [r7, #12]
8015c54: 429a cmp r2, r3
8015c56: d205 bcs.n 8015c64 <prvSampleTimeNow+0x24>
{
prvSwitchTimerLists();
8015c58: f000 f932 bl 8015ec0 <prvSwitchTimerLists>
*pxTimerListsWereSwitched = pdTRUE;
8015c5c: 687b ldr r3, [r7, #4]
8015c5e: 2201 movs r2, #1
8015c60: 601a str r2, [r3, #0]
8015c62: e002 b.n 8015c6a <prvSampleTimeNow+0x2a>
}
else
{
*pxTimerListsWereSwitched = pdFALSE;
8015c64: 687b ldr r3, [r7, #4]
8015c66: 2200 movs r2, #0
8015c68: 601a str r2, [r3, #0]
}
xLastTime = xTimeNow;
8015c6a: 4a04 ldr r2, [pc, #16] @ (8015c7c <prvSampleTimeNow+0x3c>)
8015c6c: 68fb ldr r3, [r7, #12]
8015c6e: 6013 str r3, [r2, #0]
return xTimeNow;
8015c70: 68fb ldr r3, [r7, #12]
}
8015c72: 4618 mov r0, r3
8015c74: 3710 adds r7, #16
8015c76: 46bd mov sp, r7
8015c78: bd80 pop {r7, pc}
8015c7a: bf00 nop
8015c7c: 20002600 .word 0x20002600
08015c80 <prvInsertTimerInActiveList>:
static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
const TickType_t xNextExpiryTime,
const TickType_t xTimeNow,
const TickType_t xCommandTime )
{
8015c80: b580 push {r7, lr}
8015c82: b086 sub sp, #24
8015c84: af00 add r7, sp, #0
8015c86: 60f8 str r0, [r7, #12]
8015c88: 60b9 str r1, [r7, #8]
8015c8a: 607a str r2, [r7, #4]
8015c8c: 603b str r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
8015c8e: 2300 movs r3, #0
8015c90: 617b str r3, [r7, #20]
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
8015c92: 68fb ldr r3, [r7, #12]
8015c94: 68ba ldr r2, [r7, #8]
8015c96: 605a str r2, [r3, #4]
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
8015c98: 68fb ldr r3, [r7, #12]
8015c9a: 68fa ldr r2, [r7, #12]
8015c9c: 611a str r2, [r3, #16]
if( xNextExpiryTime <= xTimeNow )
8015c9e: 68ba ldr r2, [r7, #8]
8015ca0: 687b ldr r3, [r7, #4]
8015ca2: 429a cmp r2, r3
8015ca4: d812 bhi.n 8015ccc <prvInsertTimerInActiveList+0x4c>
{
/* Has the expiry time elapsed between the command to start/reset a
* timer was issued, and the time the command was processed? */
if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8015ca6: 687a ldr r2, [r7, #4]
8015ca8: 683b ldr r3, [r7, #0]
8015caa: 1ad2 subs r2, r2, r3
8015cac: 68fb ldr r3, [r7, #12]
8015cae: 699b ldr r3, [r3, #24]
8015cb0: 429a cmp r2, r3
8015cb2: d302 bcc.n 8015cba <prvInsertTimerInActiveList+0x3a>
{
/* The time between a command being issued and the command being
* processed actually exceeds the timers period. */
xProcessTimerNow = pdTRUE;
8015cb4: 2301 movs r3, #1
8015cb6: 617b str r3, [r7, #20]
8015cb8: e01b b.n 8015cf2 <prvInsertTimerInActiveList+0x72>
}
else
{
vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
8015cba: 4b10 ldr r3, [pc, #64] @ (8015cfc <prvInsertTimerInActiveList+0x7c>)
8015cbc: 681a ldr r2, [r3, #0]
8015cbe: 68fb ldr r3, [r7, #12]
8015cc0: 3304 adds r3, #4
8015cc2: 4619 mov r1, r3
8015cc4: 4610 mov r0, r2
8015cc6: f7fc fdfc bl 80128c2 <vListInsert>
8015cca: e012 b.n 8015cf2 <prvInsertTimerInActiveList+0x72>
}
}
else
{
if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
8015ccc: 687a ldr r2, [r7, #4]
8015cce: 683b ldr r3, [r7, #0]
8015cd0: 429a cmp r2, r3
8015cd2: d206 bcs.n 8015ce2 <prvInsertTimerInActiveList+0x62>
8015cd4: 68ba ldr r2, [r7, #8]
8015cd6: 683b ldr r3, [r7, #0]
8015cd8: 429a cmp r2, r3
8015cda: d302 bcc.n 8015ce2 <prvInsertTimerInActiveList+0x62>
{
/* If, since the command was issued, the tick count has overflowed
* but the expiry time has not, then the timer must have already passed
* its expiry time and should be processed immediately. */
xProcessTimerNow = pdTRUE;
8015cdc: 2301 movs r3, #1
8015cde: 617b str r3, [r7, #20]
8015ce0: e007 b.n 8015cf2 <prvInsertTimerInActiveList+0x72>
}
else
{
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
8015ce2: 4b07 ldr r3, [pc, #28] @ (8015d00 <prvInsertTimerInActiveList+0x80>)
8015ce4: 681a ldr r2, [r3, #0]
8015ce6: 68fb ldr r3, [r7, #12]
8015ce8: 3304 adds r3, #4
8015cea: 4619 mov r1, r3
8015cec: 4610 mov r0, r2
8015cee: f7fc fde8 bl 80128c2 <vListInsert>
}
}
return xProcessTimerNow;
8015cf2: 697b ldr r3, [r7, #20]
}
8015cf4: 4618 mov r0, r3
8015cf6: 3718 adds r7, #24
8015cf8: 46bd mov sp, r7
8015cfa: bd80 pop {r7, pc}
8015cfc: 200025f4 .word 0x200025f4
8015d00: 200025f0 .word 0x200025f0
08015d04 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/
static void prvProcessReceivedCommands( void )
{
8015d04: b580 push {r7, lr}
8015d06: b08a sub sp, #40 @ 0x28
8015d08: af00 add r7, sp, #0
DaemonTaskMessage_t xMessage;
Timer_t * pxTimer;
BaseType_t xTimerListsWereSwitched;
TickType_t xTimeNow;
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
8015d0a: e0c7 b.n 8015e9c <prvProcessReceivedCommands+0x198>
{
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
{
/* Negative commands are pended function calls rather than timer
* commands. */
if( xMessage.xMessageID < ( BaseType_t ) 0 )
8015d0c: 687b ldr r3, [r7, #4]
8015d0e: 2b00 cmp r3, #0
8015d10: da19 bge.n 8015d46 <prvProcessReceivedCommands+0x42>
{
const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
8015d12: 1d3b adds r3, r7, #4
8015d14: 3304 adds r3, #4
8015d16: 627b str r3, [r7, #36] @ 0x24
/* The timer uses the xCallbackParameters member to request a
* callback be executed. Check the callback is not NULL. */
configASSERT( pxCallback );
8015d18: 6a7b ldr r3, [r7, #36] @ 0x24
8015d1a: 2b00 cmp r3, #0
8015d1c: d10b bne.n 8015d36 <prvProcessReceivedCommands+0x32>
__asm volatile
8015d1e: f04f 0350 mov.w r3, #80 @ 0x50
8015d22: f383 8811 msr BASEPRI, r3
8015d26: f3bf 8f6f isb sy
8015d2a: f3bf 8f4f dsb sy
8015d2e: 61bb str r3, [r7, #24]
}
8015d30: bf00 nop
8015d32: bf00 nop
8015d34: e7fd b.n 8015d32 <prvProcessReceivedCommands+0x2e>
/* Call the function. */
pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
8015d36: 6a7b ldr r3, [r7, #36] @ 0x24
8015d38: 681b ldr r3, [r3, #0]
8015d3a: 6a7a ldr r2, [r7, #36] @ 0x24
8015d3c: 6850 ldr r0, [r2, #4]
8015d3e: 6a7a ldr r2, [r7, #36] @ 0x24
8015d40: 6892 ldr r2, [r2, #8]
8015d42: 4611 mov r1, r2
8015d44: 4798 blx r3
}
#endif /* INCLUDE_xTimerPendFunctionCall */
/* Commands that are positive are timer commands rather than pended
* function calls. */
if( xMessage.xMessageID >= ( BaseType_t ) 0 )
8015d46: 687b ldr r3, [r7, #4]
8015d48: 2b00 cmp r3, #0
8015d4a: f2c0 80a7 blt.w 8015e9c <prvProcessReceivedCommands+0x198>
{
/* The messages uses the xTimerParameters member to work on a
* software timer. */
pxTimer = xMessage.u.xTimerParameters.pxTimer;
8015d4e: 68fb ldr r3, [r7, #12]
8015d50: 623b str r3, [r7, #32]
if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
8015d52: 6a3b ldr r3, [r7, #32]
8015d54: 695b ldr r3, [r3, #20]
8015d56: 2b00 cmp r3, #0
8015d58: d004 beq.n 8015d64 <prvProcessReceivedCommands+0x60>
{
/* The timer is in a list, remove it. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8015d5a: 6a3b ldr r3, [r7, #32]
8015d5c: 3304 adds r3, #4
8015d5e: 4618 mov r0, r3
8015d60: f7fc fde8 bl 8012934 <uxListRemove>
* it must be present in the function call. prvSampleTimeNow() must be
* called after the message is received from xTimerQueue so there is no
* possibility of a higher priority task adding a message to the message
* queue with a time that is ahead of the timer daemon task (because it
* pre-empted the timer daemon task after the xTimeNow value was set). */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
8015d64: 463b mov r3, r7
8015d66: 4618 mov r0, r3
8015d68: f7ff ff6a bl 8015c40 <prvSampleTimeNow>
8015d6c: 61f8 str r0, [r7, #28]
switch( xMessage.xMessageID )
8015d6e: 687b ldr r3, [r7, #4]
8015d70: 3b01 subs r3, #1
8015d72: 2b08 cmp r3, #8
8015d74: f200 808f bhi.w 8015e96 <prvProcessReceivedCommands+0x192>
8015d78: a201 add r2, pc, #4 @ (adr r2, 8015d80 <prvProcessReceivedCommands+0x7c>)
8015d7a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8015d7e: bf00 nop
8015d80: 08015da5 .word 0x08015da5
8015d84: 08015da5 .word 0x08015da5
8015d88: 08015e0d .word 0x08015e0d
8015d8c: 08015e21 .word 0x08015e21
8015d90: 08015e6d .word 0x08015e6d
8015d94: 08015da5 .word 0x08015da5
8015d98: 08015da5 .word 0x08015da5
8015d9c: 08015e0d .word 0x08015e0d
8015da0: 08015e21 .word 0x08015e21
case tmrCOMMAND_START:
case tmrCOMMAND_START_FROM_ISR:
case tmrCOMMAND_RESET:
case tmrCOMMAND_RESET_FROM_ISR:
/* Start or restart a timer. */
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
8015da4: 6a3b ldr r3, [r7, #32]
8015da6: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015daa: f043 0301 orr.w r3, r3, #1
8015dae: b2da uxtb r2, r3
8015db0: 6a3b ldr r3, [r7, #32]
8015db2: f883 2028 strb.w r2, [r3, #40] @ 0x28
if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
8015db6: 68ba ldr r2, [r7, #8]
8015db8: 6a3b ldr r3, [r7, #32]
8015dba: 699b ldr r3, [r3, #24]
8015dbc: 18d1 adds r1, r2, r3
8015dbe: 68bb ldr r3, [r7, #8]
8015dc0: 69fa ldr r2, [r7, #28]
8015dc2: 6a38 ldr r0, [r7, #32]
8015dc4: f7ff ff5c bl 8015c80 <prvInsertTimerInActiveList>
8015dc8: 4603 mov r3, r0
8015dca: 2b00 cmp r3, #0
8015dcc: d065 beq.n 8015e9a <prvProcessReceivedCommands+0x196>
{
/* The timer expired before it was added to the active
* timer list. Process it now. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
8015dce: 6a3b ldr r3, [r7, #32]
8015dd0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015dd4: f003 0304 and.w r3, r3, #4
8015dd8: 2b00 cmp r3, #0
8015dda: d009 beq.n 8015df0 <prvProcessReceivedCommands+0xec>
{
prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
8015ddc: 68ba ldr r2, [r7, #8]
8015dde: 6a3b ldr r3, [r7, #32]
8015de0: 699b ldr r3, [r3, #24]
8015de2: 4413 add r3, r2
8015de4: 69fa ldr r2, [r7, #28]
8015de6: 4619 mov r1, r3
8015de8: 6a38 ldr r0, [r7, #32]
8015dea: f7ff fe51 bl 8015a90 <prvReloadTimer>
8015dee: e008 b.n 8015e02 <prvProcessReceivedCommands+0xfe>
}
else
{
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
8015df0: 6a3b ldr r3, [r7, #32]
8015df2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015df6: f023 0301 bic.w r3, r3, #1
8015dfa: b2da uxtb r2, r3
8015dfc: 6a3b ldr r3, [r7, #32]
8015dfe: f883 2028 strb.w r2, [r3, #40] @ 0x28
}
/* Call the timer callback. */
traceTIMER_EXPIRED( pxTimer );
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8015e02: 6a3b ldr r3, [r7, #32]
8015e04: 6a1b ldr r3, [r3, #32]
8015e06: 6a38 ldr r0, [r7, #32]
8015e08: 4798 blx r3
else
{
mtCOVERAGE_TEST_MARKER();
}
break;
8015e0a: e046 b.n 8015e9a <prvProcessReceivedCommands+0x196>
case tmrCOMMAND_STOP:
case tmrCOMMAND_STOP_FROM_ISR:
/* The timer has already been removed from the active list. */
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
8015e0c: 6a3b ldr r3, [r7, #32]
8015e0e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015e12: f023 0301 bic.w r3, r3, #1
8015e16: b2da uxtb r2, r3
8015e18: 6a3b ldr r3, [r7, #32]
8015e1a: f883 2028 strb.w r2, [r3, #40] @ 0x28
break;
8015e1e: e03d b.n 8015e9c <prvProcessReceivedCommands+0x198>
case tmrCOMMAND_CHANGE_PERIOD:
case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
8015e20: 6a3b ldr r3, [r7, #32]
8015e22: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015e26: f043 0301 orr.w r3, r3, #1
8015e2a: b2da uxtb r2, r3
8015e2c: 6a3b ldr r3, [r7, #32]
8015e2e: f883 2028 strb.w r2, [r3, #40] @ 0x28
pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
8015e32: 68ba ldr r2, [r7, #8]
8015e34: 6a3b ldr r3, [r7, #32]
8015e36: 619a str r2, [r3, #24]
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
8015e38: 6a3b ldr r3, [r7, #32]
8015e3a: 699b ldr r3, [r3, #24]
8015e3c: 2b00 cmp r3, #0
8015e3e: d10b bne.n 8015e58 <prvProcessReceivedCommands+0x154>
__asm volatile
8015e40: f04f 0350 mov.w r3, #80 @ 0x50
8015e44: f383 8811 msr BASEPRI, r3
8015e48: f3bf 8f6f isb sy
8015e4c: f3bf 8f4f dsb sy
8015e50: 617b str r3, [r7, #20]
}
8015e52: bf00 nop
8015e54: bf00 nop
8015e56: e7fd b.n 8015e54 <prvProcessReceivedCommands+0x150>
* be longer or shorter than the old one. The command time is
* therefore set to the current time, and as the period cannot
* be zero the next expiry time can only be in the future,
* meaning (unlike for the xTimerStart() case above) there is
* no fail case that needs to be handled here. */
( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
8015e58: 6a3b ldr r3, [r7, #32]
8015e5a: 699a ldr r2, [r3, #24]
8015e5c: 69fb ldr r3, [r7, #28]
8015e5e: 18d1 adds r1, r2, r3
8015e60: 69fb ldr r3, [r7, #28]
8015e62: 69fa ldr r2, [r7, #28]
8015e64: 6a38 ldr r0, [r7, #32]
8015e66: f7ff ff0b bl 8015c80 <prvInsertTimerInActiveList>
break;
8015e6a: e017 b.n 8015e9c <prvProcessReceivedCommands+0x198>
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* The timer has already been removed from the active list,
* just free up the memory if the memory was dynamically
* allocated. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
8015e6c: 6a3b ldr r3, [r7, #32]
8015e6e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015e72: f003 0302 and.w r3, r3, #2
8015e76: 2b00 cmp r3, #0
8015e78: d103 bne.n 8015e82 <prvProcessReceivedCommands+0x17e>
{
vPortFree( pxTimer );
8015e7a: 6a38 ldr r0, [r7, #32]
8015e7c: f000 fbc4 bl 8016608 <vPortFree>
* no need to free the memory - just mark the timer as
* "not active". */
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
break;
8015e80: e00c b.n 8015e9c <prvProcessReceivedCommands+0x198>
pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
8015e82: 6a3b ldr r3, [r7, #32]
8015e84: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8015e88: f023 0301 bic.w r3, r3, #1
8015e8c: b2da uxtb r2, r3
8015e8e: 6a3b ldr r3, [r7, #32]
8015e90: f883 2028 strb.w r2, [r3, #40] @ 0x28
break;
8015e94: e002 b.n 8015e9c <prvProcessReceivedCommands+0x198>
default:
/* Don't expect to get here. */
break;
8015e96: bf00 nop
8015e98: e000 b.n 8015e9c <prvProcessReceivedCommands+0x198>
break;
8015e9a: bf00 nop
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
8015e9c: 4b07 ldr r3, [pc, #28] @ (8015ebc <prvProcessReceivedCommands+0x1b8>)
8015e9e: 681b ldr r3, [r3, #0]
8015ea0: 1d39 adds r1, r7, #4
8015ea2: 2200 movs r2, #0
8015ea4: 4618 mov r0, r3
8015ea6: f7fd fa53 bl 8013350 <xQueueReceive>
8015eaa: 4603 mov r3, r0
8015eac: 2b00 cmp r3, #0
8015eae: f47f af2d bne.w 8015d0c <prvProcessReceivedCommands+0x8>
}
}
}
}
8015eb2: bf00 nop
8015eb4: bf00 nop
8015eb6: 3728 adds r7, #40 @ 0x28
8015eb8: 46bd mov sp, r7
8015eba: bd80 pop {r7, pc}
8015ebc: 200025f8 .word 0x200025f8
08015ec0 <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/
static void prvSwitchTimerLists( void )
{
8015ec0: b580 push {r7, lr}
8015ec2: b082 sub sp, #8
8015ec4: af00 add r7, sp, #0
/* The tick count has overflowed. The timer lists must be switched.
* If there are any timers still referenced from the current timer list
* then they must have expired and should be processed before the lists
* are switched. */
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
8015ec6: e009 b.n 8015edc <prvSwitchTimerLists+0x1c>
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
8015ec8: 4b0e ldr r3, [pc, #56] @ (8015f04 <prvSwitchTimerLists+0x44>)
8015eca: 681b ldr r3, [r3, #0]
8015ecc: 68db ldr r3, [r3, #12]
8015ece: 681b ldr r3, [r3, #0]
8015ed0: 603b str r3, [r7, #0]
/* Process the expired timer. For auto-reload timers, be careful to
* process only expirations that occur on the current list. Further
* expirations must wait until after the lists are switched. */
prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW );
8015ed2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8015ed6: 6838 ldr r0, [r7, #0]
8015ed8: f7ff fdfc bl 8015ad4 <prvProcessExpiredTimer>
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
8015edc: 4b09 ldr r3, [pc, #36] @ (8015f04 <prvSwitchTimerLists+0x44>)
8015ede: 681b ldr r3, [r3, #0]
8015ee0: 681b ldr r3, [r3, #0]
8015ee2: 2b00 cmp r3, #0
8015ee4: d1f0 bne.n 8015ec8 <prvSwitchTimerLists+0x8>
}
pxTemp = pxCurrentTimerList;
8015ee6: 4b07 ldr r3, [pc, #28] @ (8015f04 <prvSwitchTimerLists+0x44>)
8015ee8: 681b ldr r3, [r3, #0]
8015eea: 607b str r3, [r7, #4]
pxCurrentTimerList = pxOverflowTimerList;
8015eec: 4b06 ldr r3, [pc, #24] @ (8015f08 <prvSwitchTimerLists+0x48>)
8015eee: 681b ldr r3, [r3, #0]
8015ef0: 4a04 ldr r2, [pc, #16] @ (8015f04 <prvSwitchTimerLists+0x44>)
8015ef2: 6013 str r3, [r2, #0]
pxOverflowTimerList = pxTemp;
8015ef4: 4a04 ldr r2, [pc, #16] @ (8015f08 <prvSwitchTimerLists+0x48>)
8015ef6: 687b ldr r3, [r7, #4]
8015ef8: 6013 str r3, [r2, #0]
}
8015efa: bf00 nop
8015efc: 3708 adds r7, #8
8015efe: 46bd mov sp, r7
8015f00: bd80 pop {r7, pc}
8015f02: bf00 nop
8015f04: 200025f0 .word 0x200025f0
8015f08: 200025f4 .word 0x200025f4
08015f0c <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/
static void prvCheckForValidListAndQueue( void )
{
8015f0c: b580 push {r7, lr}
8015f0e: b082 sub sp, #8
8015f10: af02 add r7, sp, #8
/* Check that the list from which active timers are referenced, and the
* queue used to communicate with the timer service, have been
* initialised. */
taskENTER_CRITICAL();
8015f12: f000 f985 bl 8016220 <vPortEnterCritical>
{
if( xTimerQueue == NULL )
8015f16: 4b15 ldr r3, [pc, #84] @ (8015f6c <prvCheckForValidListAndQueue+0x60>)
8015f18: 681b ldr r3, [r3, #0]
8015f1a: 2b00 cmp r3, #0
8015f1c: d120 bne.n 8015f60 <prvCheckForValidListAndQueue+0x54>
{
vListInitialise( &xActiveTimerList1 );
8015f1e: 4814 ldr r0, [pc, #80] @ (8015f70 <prvCheckForValidListAndQueue+0x64>)
8015f20: f7fc fca2 bl 8012868 <vListInitialise>
vListInitialise( &xActiveTimerList2 );
8015f24: 4813 ldr r0, [pc, #76] @ (8015f74 <prvCheckForValidListAndQueue+0x68>)
8015f26: f7fc fc9f bl 8012868 <vListInitialise>
pxCurrentTimerList = &xActiveTimerList1;
8015f2a: 4b13 ldr r3, [pc, #76] @ (8015f78 <prvCheckForValidListAndQueue+0x6c>)
8015f2c: 4a10 ldr r2, [pc, #64] @ (8015f70 <prvCheckForValidListAndQueue+0x64>)
8015f2e: 601a str r2, [r3, #0]
pxOverflowTimerList = &xActiveTimerList2;
8015f30: 4b12 ldr r3, [pc, #72] @ (8015f7c <prvCheckForValidListAndQueue+0x70>)
8015f32: 4a10 ldr r2, [pc, #64] @ (8015f74 <prvCheckForValidListAndQueue+0x68>)
8015f34: 601a str r2, [r3, #0]
/* The timer queue is allocated statically in case
* configSUPPORT_DYNAMIC_ALLOCATION is 0. */
PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
8015f36: 2300 movs r3, #0
8015f38: 9300 str r3, [sp, #0]
8015f3a: 4b11 ldr r3, [pc, #68] @ (8015f80 <prvCheckForValidListAndQueue+0x74>)
8015f3c: 4a11 ldr r2, [pc, #68] @ (8015f84 <prvCheckForValidListAndQueue+0x78>)
8015f3e: 2110 movs r1, #16
8015f40: 200a movs r0, #10
8015f42: f7fc fdb3 bl 8012aac <xQueueGenericCreateStatic>
8015f46: 4603 mov r3, r0
8015f48: 4a08 ldr r2, [pc, #32] @ (8015f6c <prvCheckForValidListAndQueue+0x60>)
8015f4a: 6013 str r3, [r2, #0]
}
#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
#if ( configQUEUE_REGISTRY_SIZE > 0 )
{
if( xTimerQueue != NULL )
8015f4c: 4b07 ldr r3, [pc, #28] @ (8015f6c <prvCheckForValidListAndQueue+0x60>)
8015f4e: 681b ldr r3, [r3, #0]
8015f50: 2b00 cmp r3, #0
8015f52: d005 beq.n 8015f60 <prvCheckForValidListAndQueue+0x54>
{
vQueueAddToRegistry( xTimerQueue, "TmrQ" );
8015f54: 4b05 ldr r3, [pc, #20] @ (8015f6c <prvCheckForValidListAndQueue+0x60>)
8015f56: 681b ldr r3, [r3, #0]
8015f58: 490b ldr r1, [pc, #44] @ (8015f88 <prvCheckForValidListAndQueue+0x7c>)
8015f5a: 4618 mov r0, r3
8015f5c: f7fd fdc0 bl 8013ae0 <vQueueAddToRegistry>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8015f60: f000 f990 bl 8016284 <vPortExitCritical>
}
8015f64: bf00 nop
8015f66: 46bd mov sp, r7
8015f68: bd80 pop {r7, pc}
8015f6a: bf00 nop
8015f6c: 200025f8 .word 0x200025f8
8015f70: 200025c8 .word 0x200025c8
8015f74: 200025dc .word 0x200025dc
8015f78: 200025f0 .word 0x200025f0
8015f7c: 200025f4 .word 0x200025f4
8015f80: 200026a4 .word 0x200026a4
8015f84: 20002604 .word 0x20002604
8015f88: 0801c4d8 .word 0x0801c4d8
08015f8c <pxPortInitialiseStack>:
* See header file for description.
*/
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
8015f8c: b480 push {r7}
8015f8e: b085 sub sp, #20
8015f90: af00 add r7, sp, #0
8015f92: 60f8 str r0, [r7, #12]
8015f94: 60b9 str r1, [r7, #8]
8015f96: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
* interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
* of interrupts, and to ensure alignment. */
pxTopOfStack--;
8015f98: 68fb ldr r3, [r7, #12]
8015f9a: 3b04 subs r3, #4
8015f9c: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
8015f9e: 68fb ldr r3, [r7, #12]
8015fa0: f04f 7280 mov.w r2, #16777216 @ 0x1000000
8015fa4: 601a str r2, [r3, #0]
pxTopOfStack--;
8015fa6: 68fb ldr r3, [r7, #12]
8015fa8: 3b04 subs r3, #4
8015faa: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
8015fac: 68bb ldr r3, [r7, #8]
8015fae: f023 0201 bic.w r2, r3, #1
8015fb2: 68fb ldr r3, [r7, #12]
8015fb4: 601a str r2, [r3, #0]
pxTopOfStack--;
8015fb6: 68fb ldr r3, [r7, #12]
8015fb8: 3b04 subs r3, #4
8015fba: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
8015fbc: 4a0c ldr r2, [pc, #48] @ (8015ff0 <pxPortInitialiseStack+0x64>)
8015fbe: 68fb ldr r3, [r7, #12]
8015fc0: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
8015fc2: 68fb ldr r3, [r7, #12]
8015fc4: 3b14 subs r3, #20
8015fc6: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
8015fc8: 687a ldr r2, [r7, #4]
8015fca: 68fb ldr r3, [r7, #12]
8015fcc: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
* own exec return value. */
pxTopOfStack--;
8015fce: 68fb ldr r3, [r7, #12]
8015fd0: 3b04 subs r3, #4
8015fd2: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
8015fd4: 68fb ldr r3, [r7, #12]
8015fd6: f06f 0202 mvn.w r2, #2
8015fda: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
8015fdc: 68fb ldr r3, [r7, #12]
8015fde: 3b20 subs r3, #32
8015fe0: 60fb str r3, [r7, #12]
return pxTopOfStack;
8015fe2: 68fb ldr r3, [r7, #12]
}
8015fe4: 4618 mov r0, r3
8015fe6: 3714 adds r7, #20
8015fe8: 46bd mov sp, r7
8015fea: f85d 7b04 ldr.w r7, [sp], #4
8015fee: 4770 bx lr
8015ff0: 08015ff5 .word 0x08015ff5
08015ff4 <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
8015ff4: b480 push {r7}
8015ff6: b085 sub sp, #20
8015ff8: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
8015ffa: 2300 movs r3, #0
8015ffc: 607b str r3, [r7, #4]
* its caller as there is nothing to return to. If a task wants to exit it
* should instead call vTaskDelete( NULL ).
*
* Artificially force an assert() to be triggered if configASSERT() is
* defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
8015ffe: 4b13 ldr r3, [pc, #76] @ (801604c <prvTaskExitError+0x58>)
8016000: 681b ldr r3, [r3, #0]
8016002: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8016006: d00b beq.n 8016020 <prvTaskExitError+0x2c>
__asm volatile
8016008: f04f 0350 mov.w r3, #80 @ 0x50
801600c: f383 8811 msr BASEPRI, r3
8016010: f3bf 8f6f isb sy
8016014: f3bf 8f4f dsb sy
8016018: 60fb str r3, [r7, #12]
}
801601a: bf00 nop
801601c: bf00 nop
801601e: e7fd b.n 801601c <prvTaskExitError+0x28>
__asm volatile
8016020: f04f 0350 mov.w r3, #80 @ 0x50
8016024: f383 8811 msr BASEPRI, r3
8016028: f3bf 8f6f isb sy
801602c: f3bf 8f4f dsb sy
8016030: 60bb str r3, [r7, #8]
}
8016032: bf00 nop
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
8016034: bf00 nop
8016036: 687b ldr r3, [r7, #4]
8016038: 2b00 cmp r3, #0
801603a: d0fc beq.n 8016036 <prvTaskExitError+0x42>
* about code appearing after this function is called - making ulDummy
* volatile makes the compiler think the function could return and
* therefore not output an 'unreachable code' warning for code that appears
* after it. */
}
}
801603c: bf00 nop
801603e: bf00 nop
8016040: 3714 adds r7, #20
8016042: 46bd mov sp, r7
8016044: f85d 7b04 ldr.w r7, [sp], #4
8016048: 4770 bx lr
801604a: bf00 nop
801604c: 200000a4 .word 0x200000a4
08016050 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
8016050: 4b07 ldr r3, [pc, #28] @ (8016070 <pxCurrentTCBConst2>)
8016052: 6819 ldr r1, [r3, #0]
8016054: 6808 ldr r0, [r1, #0]
8016056: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
801605a: f380 8809 msr PSP, r0
801605e: f3bf 8f6f isb sy
8016062: f04f 0000 mov.w r0, #0
8016066: f380 8811 msr BASEPRI, r0
801606a: 4770 bx lr
801606c: f3af 8000 nop.w
08016070 <pxCurrentTCBConst2>:
8016070: 200020c8 .word 0x200020c8
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
8016074: bf00 nop
8016076: bf00 nop
08016078 <prvPortStartFirstTask>:
{
/* Start the first task. This also clears the bit that indicates the FPU is
* in use in case the FPU was used before the scheduler was started - which
* would otherwise result in the unnecessary leaving of space in the SVC stack
* for lazy saving of FPU registers. */
__asm volatile (
8016078: 4808 ldr r0, [pc, #32] @ (801609c <prvPortStartFirstTask+0x24>)
801607a: 6800 ldr r0, [r0, #0]
801607c: 6800 ldr r0, [r0, #0]
801607e: f380 8808 msr MSP, r0
8016082: f04f 0000 mov.w r0, #0
8016086: f380 8814 msr CONTROL, r0
801608a: b662 cpsie i
801608c: b661 cpsie f
801608e: f3bf 8f4f dsb sy
8016092: f3bf 8f6f isb sy
8016096: df00 svc 0
8016098: bf00 nop
801609a: 0000 .short 0x0000
801609c: e000ed08 .word 0xe000ed08
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
" .ltorg \n"
);
}
80160a0: bf00 nop
80160a2: bf00 nop
080160a4 <xPortStartScheduler>:
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
80160a4: b580 push {r7, lr}
80160a6: b088 sub sp, #32
80160a8: af00 add r7, sp, #0
/* This port can be used on all revisions of the Cortex-M7 core other than
* the r0p1 parts. r0p1 parts should use the port from the
* /source/portable/GCC/ARM_CM7/r0p1 directory. */
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
80160aa: 4b54 ldr r3, [pc, #336] @ (80161fc <xPortStartScheduler+0x158>)
80160ac: 681b ldr r3, [r3, #0]
80160ae: 4a54 ldr r2, [pc, #336] @ (8016200 <xPortStartScheduler+0x15c>)
80160b0: 4293 cmp r3, r2
80160b2: d10b bne.n 80160cc <xPortStartScheduler+0x28>
__asm volatile
80160b4: f04f 0350 mov.w r3, #80 @ 0x50
80160b8: f383 8811 msr BASEPRI, r3
80160bc: f3bf 8f6f isb sy
80160c0: f3bf 8f4f dsb sy
80160c4: 617b str r3, [r7, #20]
}
80160c6: bf00 nop
80160c8: bf00 nop
80160ca: e7fd b.n 80160c8 <xPortStartScheduler+0x24>
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
80160cc: 4b4b ldr r3, [pc, #300] @ (80161fc <xPortStartScheduler+0x158>)
80160ce: 681b ldr r3, [r3, #0]
80160d0: 4a4c ldr r2, [pc, #304] @ (8016204 <xPortStartScheduler+0x160>)
80160d2: 4293 cmp r3, r2
80160d4: d10b bne.n 80160ee <xPortStartScheduler+0x4a>
__asm volatile
80160d6: f04f 0350 mov.w r3, #80 @ 0x50
80160da: f383 8811 msr BASEPRI, r3
80160de: f3bf 8f6f isb sy
80160e2: f3bf 8f4f dsb sy
80160e6: 61bb str r3, [r7, #24]
}
80160e8: bf00 nop
80160ea: bf00 nop
80160ec: e7fd b.n 80160ea <xPortStartScheduler+0x46>
#if ( configASSERT_DEFINED == 1 )
{
volatile uint8_t ucOriginalPriority;
volatile uint32_t ulImplementedPrioBits = 0;
80160ee: 2300 movs r3, #0
80160f0: 607b str r3, [r7, #4]
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
80160f2: 4b45 ldr r3, [pc, #276] @ (8016208 <xPortStartScheduler+0x164>)
80160f4: 61fb str r3, [r7, #28]
* functions can be called. ISR safe functions are those that end in
* "FromISR". FreeRTOS maintains separate thread and ISR API functions to
* ensure interrupt entry is as fast and simple as possible.
*
* Save the interrupt priority value that is about to be clobbered. */
ucOriginalPriority = *pucFirstUserPriorityRegister;
80160f6: 69fb ldr r3, [r7, #28]
80160f8: 781b ldrb r3, [r3, #0]
80160fa: b2db uxtb r3, r3
80160fc: 72fb strb r3, [r7, #11]
/* Determine the number of priority bits available. First write to all
* possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
80160fe: 69fb ldr r3, [r7, #28]
8016100: 22ff movs r2, #255 @ 0xff
8016102: 701a strb r2, [r3, #0]
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
8016104: 69fb ldr r3, [r7, #28]
8016106: 781b ldrb r3, [r3, #0]
8016108: b2db uxtb r3, r3
801610a: 70fb strb r3, [r7, #3]
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
801610c: 78fb ldrb r3, [r7, #3]
801610e: b2db uxtb r3, r3
8016110: f003 0350 and.w r3, r3, #80 @ 0x50
8016114: b2da uxtb r2, r3
8016116: 4b3d ldr r3, [pc, #244] @ (801620c <xPortStartScheduler+0x168>)
8016118: 701a strb r2, [r3, #0]
* accounting for the number of priority bits supported by the
* hardware. A priority of 0 is invalid because setting the BASEPRI
* register to 0 unmasks all interrupts, and interrupts with priority 0
* cannot be masked using BASEPRI.
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( ucMaxSysCallPriority );
801611a: 4b3c ldr r3, [pc, #240] @ (801620c <xPortStartScheduler+0x168>)
801611c: 781b ldrb r3, [r3, #0]
801611e: 2b00 cmp r3, #0
8016120: d10b bne.n 801613a <xPortStartScheduler+0x96>
__asm volatile
8016122: f04f 0350 mov.w r3, #80 @ 0x50
8016126: f383 8811 msr BASEPRI, r3
801612a: f3bf 8f6f isb sy
801612e: f3bf 8f4f dsb sy
8016132: 613b str r3, [r7, #16]
}
8016134: bf00 nop
8016136: bf00 nop
8016138: e7fd b.n 8016136 <xPortStartScheduler+0x92>
/* Check that the bits not implemented in hardware are zero in
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
801613a: 78fb ldrb r3, [r7, #3]
801613c: b2db uxtb r3, r3
801613e: 43db mvns r3, r3
8016140: f003 0350 and.w r3, r3, #80 @ 0x50
8016144: 2b00 cmp r3, #0
8016146: d013 beq.n 8016170 <xPortStartScheduler+0xcc>
__asm volatile
8016148: f04f 0350 mov.w r3, #80 @ 0x50
801614c: f383 8811 msr BASEPRI, r3
8016150: f3bf 8f6f isb sy
8016154: f3bf 8f4f dsb sy
8016158: 60fb str r3, [r7, #12]
}
801615a: bf00 nop
801615c: bf00 nop
801615e: e7fd b.n 801615c <xPortStartScheduler+0xb8>
/* Calculate the maximum acceptable priority group value for the number
* of bits read back. */
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
ulImplementedPrioBits++;
8016160: 687b ldr r3, [r7, #4]
8016162: 3301 adds r3, #1
8016164: 607b str r3, [r7, #4]
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
8016166: 78fb ldrb r3, [r7, #3]
8016168: b2db uxtb r3, r3
801616a: 005b lsls r3, r3, #1
801616c: b2db uxtb r3, r3
801616e: 70fb strb r3, [r7, #3]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
8016170: 78fb ldrb r3, [r7, #3]
8016172: b2db uxtb r3, r3
8016174: f003 0380 and.w r3, r3, #128 @ 0x80
8016178: 2b80 cmp r3, #128 @ 0x80
801617a: d0f1 beq.n 8016160 <xPortStartScheduler+0xbc>
}
if( ulImplementedPrioBits == 8 )
801617c: 687b ldr r3, [r7, #4]
801617e: 2b08 cmp r3, #8
8016180: d103 bne.n 801618a <xPortStartScheduler+0xe6>
*
* The following assert ensures that the sub-priority bit in the
* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
* confusion. */
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
ulMaxPRIGROUPValue = 0;
8016182: 4b23 ldr r3, [pc, #140] @ (8016210 <xPortStartScheduler+0x16c>)
8016184: 2200 movs r2, #0
8016186: 601a str r2, [r3, #0]
8016188: e004 b.n 8016194 <xPortStartScheduler+0xf0>
}
else
{
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
801618a: 687b ldr r3, [r7, #4]
801618c: f1c3 0307 rsb r3, r3, #7
8016190: 4a1f ldr r2, [pc, #124] @ (8016210 <xPortStartScheduler+0x16c>)
8016192: 6013 str r3, [r2, #0]
}
/* Shift the priority group value back to its position within the AIRCR
* register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
8016194: 4b1e ldr r3, [pc, #120] @ (8016210 <xPortStartScheduler+0x16c>)
8016196: 681b ldr r3, [r3, #0]
8016198: 021b lsls r3, r3, #8
801619a: 4a1d ldr r2, [pc, #116] @ (8016210 <xPortStartScheduler+0x16c>)
801619c: 6013 str r3, [r2, #0]
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
801619e: 4b1c ldr r3, [pc, #112] @ (8016210 <xPortStartScheduler+0x16c>)
80161a0: 681b ldr r3, [r3, #0]
80161a2: f403 63e0 and.w r3, r3, #1792 @ 0x700
80161a6: 4a1a ldr r2, [pc, #104] @ (8016210 <xPortStartScheduler+0x16c>)
80161a8: 6013 str r3, [r2, #0]
/* Restore the clobbered interrupt priority register to its original
* value. */
*pucFirstUserPriorityRegister = ucOriginalPriority;
80161aa: 7afb ldrb r3, [r7, #11]
80161ac: b2da uxtb r2, r3
80161ae: 69fb ldr r3, [r7, #28]
80161b0: 701a strb r2, [r3, #0]
}
#endif /* configASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
80161b2: 4b18 ldr r3, [pc, #96] @ (8016214 <xPortStartScheduler+0x170>)
80161b4: 681b ldr r3, [r3, #0]
80161b6: 4a17 ldr r2, [pc, #92] @ (8016214 <xPortStartScheduler+0x170>)
80161b8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000
80161bc: 6013 str r3, [r2, #0]
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
80161be: 4b15 ldr r3, [pc, #84] @ (8016214 <xPortStartScheduler+0x170>)
80161c0: 681b ldr r3, [r3, #0]
80161c2: 4a14 ldr r2, [pc, #80] @ (8016214 <xPortStartScheduler+0x170>)
80161c4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000
80161c8: 6013 str r3, [r2, #0]
/* Start the timer that generates the tick ISR. Interrupts are disabled
* here already. */
vPortSetupTimerInterrupt();
80161ca: f000 f8df bl 801638c <vPortSetupTimerInterrupt>
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
80161ce: 4b12 ldr r3, [pc, #72] @ (8016218 <xPortStartScheduler+0x174>)
80161d0: 2200 movs r2, #0
80161d2: 601a str r2, [r3, #0]
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
80161d4: f000 f8fe bl 80163d4 <vPortEnableVFP>
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
80161d8: 4b10 ldr r3, [pc, #64] @ (801621c <xPortStartScheduler+0x178>)
80161da: 681b ldr r3, [r3, #0]
80161dc: 4a0f ldr r2, [pc, #60] @ (801621c <xPortStartScheduler+0x178>)
80161de: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000
80161e2: 6013 str r3, [r2, #0]
/* Start the first task. */
prvPortStartFirstTask();
80161e4: f7ff ff48 bl 8016078 <prvPortStartFirstTask>
* exit error function to prevent compiler warnings about a static function
* not being called in the case that the application writer overrides this
* functionality by defining configTASK_RETURN_ADDRESS. Call
* vTaskSwitchContext() so link time optimisation does not remove the
* symbol. */
vTaskSwitchContext();
80161e8: f7fe f9f2 bl 80145d0 <vTaskSwitchContext>
prvTaskExitError();
80161ec: f7ff ff02 bl 8015ff4 <prvTaskExitError>
/* Should not get here! */
return 0;
80161f0: 2300 movs r3, #0
}
80161f2: 4618 mov r0, r3
80161f4: 3720 adds r7, #32
80161f6: 46bd mov sp, r7
80161f8: bd80 pop {r7, pc}
80161fa: bf00 nop
80161fc: e000ed00 .word 0xe000ed00
8016200: 410fc271 .word 0x410fc271
8016204: 410fc270 .word 0x410fc270
8016208: e000e400 .word 0xe000e400
801620c: 200026f4 .word 0x200026f4
8016210: 200026f8 .word 0x200026f8
8016214: e000ed20 .word 0xe000ed20
8016218: 200000a4 .word 0x200000a4
801621c: e000ef34 .word 0xe000ef34
08016220 <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
8016220: b480 push {r7}
8016222: b083 sub sp, #12
8016224: af00 add r7, sp, #0
__asm volatile
8016226: f04f 0350 mov.w r3, #80 @ 0x50
801622a: f383 8811 msr BASEPRI, r3
801622e: f3bf 8f6f isb sy
8016232: f3bf 8f4f dsb sy
8016236: 607b str r3, [r7, #4]
}
8016238: bf00 nop
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
801623a: 4b10 ldr r3, [pc, #64] @ (801627c <vPortEnterCritical+0x5c>)
801623c: 681b ldr r3, [r3, #0]
801623e: 3301 adds r3, #1
8016240: 4a0e ldr r2, [pc, #56] @ (801627c <vPortEnterCritical+0x5c>)
8016242: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
* assert() if it is being called from an interrupt context. Only API
* functions that end in "FromISR" can be used in an interrupt. Only assert if
* the critical nesting count is 1 to protect against recursive calls if the
* assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
8016244: 4b0d ldr r3, [pc, #52] @ (801627c <vPortEnterCritical+0x5c>)
8016246: 681b ldr r3, [r3, #0]
8016248: 2b01 cmp r3, #1
801624a: d110 bne.n 801626e <vPortEnterCritical+0x4e>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
801624c: 4b0c ldr r3, [pc, #48] @ (8016280 <vPortEnterCritical+0x60>)
801624e: 681b ldr r3, [r3, #0]
8016250: b2db uxtb r3, r3
8016252: 2b00 cmp r3, #0
8016254: d00b beq.n 801626e <vPortEnterCritical+0x4e>
__asm volatile
8016256: f04f 0350 mov.w r3, #80 @ 0x50
801625a: f383 8811 msr BASEPRI, r3
801625e: f3bf 8f6f isb sy
8016262: f3bf 8f4f dsb sy
8016266: 603b str r3, [r7, #0]
}
8016268: bf00 nop
801626a: bf00 nop
801626c: e7fd b.n 801626a <vPortEnterCritical+0x4a>
}
}
801626e: bf00 nop
8016270: 370c adds r7, #12
8016272: 46bd mov sp, r7
8016274: f85d 7b04 ldr.w r7, [sp], #4
8016278: 4770 bx lr
801627a: bf00 nop
801627c: 200000a4 .word 0x200000a4
8016280: e000ed04 .word 0xe000ed04
08016284 <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
8016284: b480 push {r7}
8016286: b083 sub sp, #12
8016288: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
801628a: 4b12 ldr r3, [pc, #72] @ (80162d4 <vPortExitCritical+0x50>)
801628c: 681b ldr r3, [r3, #0]
801628e: 2b00 cmp r3, #0
8016290: d10b bne.n 80162aa <vPortExitCritical+0x26>
__asm volatile
8016292: f04f 0350 mov.w r3, #80 @ 0x50
8016296: f383 8811 msr BASEPRI, r3
801629a: f3bf 8f6f isb sy
801629e: f3bf 8f4f dsb sy
80162a2: 607b str r3, [r7, #4]
}
80162a4: bf00 nop
80162a6: bf00 nop
80162a8: e7fd b.n 80162a6 <vPortExitCritical+0x22>
uxCriticalNesting--;
80162aa: 4b0a ldr r3, [pc, #40] @ (80162d4 <vPortExitCritical+0x50>)
80162ac: 681b ldr r3, [r3, #0]
80162ae: 3b01 subs r3, #1
80162b0: 4a08 ldr r2, [pc, #32] @ (80162d4 <vPortExitCritical+0x50>)
80162b2: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
80162b4: 4b07 ldr r3, [pc, #28] @ (80162d4 <vPortExitCritical+0x50>)
80162b6: 681b ldr r3, [r3, #0]
80162b8: 2b00 cmp r3, #0
80162ba: d105 bne.n 80162c8 <vPortExitCritical+0x44>
80162bc: 2300 movs r3, #0
80162be: 603b str r3, [r7, #0]
__asm volatile
80162c0: 683b ldr r3, [r7, #0]
80162c2: f383 8811 msr BASEPRI, r3
}
80162c6: bf00 nop
{
portENABLE_INTERRUPTS();
}
}
80162c8: bf00 nop
80162ca: 370c adds r7, #12
80162cc: 46bd mov sp, r7
80162ce: f85d 7b04 ldr.w r7, [sp], #4
80162d2: 4770 bx lr
80162d4: 200000a4 .word 0x200000a4
...
080162e0 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
80162e0: f3ef 8009 mrs r0, PSP
80162e4: f3bf 8f6f isb sy
80162e8: 4b15 ldr r3, [pc, #84] @ (8016340 <pxCurrentTCBConst>)
80162ea: 681a ldr r2, [r3, #0]
80162ec: f01e 0f10 tst.w lr, #16
80162f0: bf08 it eq
80162f2: ed20 8a10 vstmdbeq r0!, {s16-s31}
80162f6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
80162fa: 6010 str r0, [r2, #0]
80162fc: b409 push {r0, r3}
80162fe: f04f 0050 mov.w r0, #80 @ 0x50
8016302: f380 8811 msr BASEPRI, r0
8016306: f3bf 8f4f dsb sy
801630a: f3bf 8f6f isb sy
801630e: f7fe f95f bl 80145d0 <vTaskSwitchContext>
8016312: f04f 0000 mov.w r0, #0
8016316: f380 8811 msr BASEPRI, r0
801631a: bc09 pop {r0, r3}
801631c: 6819 ldr r1, [r3, #0]
801631e: 6808 ldr r0, [r1, #0]
8016320: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8016324: f01e 0f10 tst.w lr, #16
8016328: bf08 it eq
801632a: ecb0 8a10 vldmiaeq r0!, {s16-s31}
801632e: f380 8809 msr PSP, r0
8016332: f3bf 8f6f isb sy
8016336: 4770 bx lr
8016338: f3af 8000 nop.w
801633c: f3af 8000 nop.w
08016340 <pxCurrentTCBConst>:
8016340: 200020c8 .word 0x200020c8
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
);
}
8016344: bf00 nop
8016346: bf00 nop
08016348 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
8016348: b580 push {r7, lr}
801634a: b082 sub sp, #8
801634c: af00 add r7, sp, #0
__asm volatile
801634e: f04f 0350 mov.w r3, #80 @ 0x50
8016352: f383 8811 msr BASEPRI, r3
8016356: f3bf 8f6f isb sy
801635a: f3bf 8f4f dsb sy
801635e: 607b str r3, [r7, #4]
}
8016360: bf00 nop
* save and then restore the interrupt mask value as its value is already
* known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
8016362: f7fe f81d bl 80143a0 <xTaskIncrementTick>
8016366: 4603 mov r3, r0
8016368: 2b00 cmp r3, #0
801636a: d003 beq.n 8016374 <xPortSysTickHandler+0x2c>
{
/* A context switch is required. Context switching is performed in
* the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
801636c: 4b06 ldr r3, [pc, #24] @ (8016388 <xPortSysTickHandler+0x40>)
801636e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8016372: 601a str r2, [r3, #0]
8016374: 2300 movs r3, #0
8016376: 603b str r3, [r7, #0]
__asm volatile
8016378: 683b ldr r3, [r7, #0]
801637a: f383 8811 msr BASEPRI, r3
}
801637e: bf00 nop
}
}
portENABLE_INTERRUPTS();
}
8016380: bf00 nop
8016382: 3708 adds r7, #8
8016384: 46bd mov sp, r7
8016386: bd80 pop {r7, pc}
8016388: e000ed04 .word 0xe000ed04
0801638c <vPortSetupTimerInterrupt>:
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
{
801638c: b480 push {r7}
801638e: af00 add r7, sp, #0
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
8016390: 4b0b ldr r3, [pc, #44] @ (80163c0 <vPortSetupTimerInterrupt+0x34>)
8016392: 2200 movs r2, #0
8016394: 601a str r2, [r3, #0]
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
8016396: 4b0b ldr r3, [pc, #44] @ (80163c4 <vPortSetupTimerInterrupt+0x38>)
8016398: 2200 movs r2, #0
801639a: 601a str r2, [r3, #0]
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
801639c: 4b0a ldr r3, [pc, #40] @ (80163c8 <vPortSetupTimerInterrupt+0x3c>)
801639e: 681b ldr r3, [r3, #0]
80163a0: 4a0a ldr r2, [pc, #40] @ (80163cc <vPortSetupTimerInterrupt+0x40>)
80163a2: fba2 2303 umull r2, r3, r2, r3
80163a6: 099b lsrs r3, r3, #6
80163a8: 4a09 ldr r2, [pc, #36] @ (80163d0 <vPortSetupTimerInterrupt+0x44>)
80163aa: 3b01 subs r3, #1
80163ac: 6013 str r3, [r2, #0]
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
80163ae: 4b04 ldr r3, [pc, #16] @ (80163c0 <vPortSetupTimerInterrupt+0x34>)
80163b0: 2207 movs r2, #7
80163b2: 601a str r2, [r3, #0]
}
80163b4: bf00 nop
80163b6: 46bd mov sp, r7
80163b8: f85d 7b04 ldr.w r7, [sp], #4
80163bc: 4770 bx lr
80163be: bf00 nop
80163c0: e000e010 .word 0xe000e010
80163c4: e000e018 .word 0xe000e018
80163c8: 2000000c .word 0x2000000c
80163cc: 10624dd3 .word 0x10624dd3
80163d0: e000e014 .word 0xe000e014
080163d4 <vPortEnableVFP>:
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
80163d4: f8df 000c ldr.w r0, [pc, #12] @ 80163e4 <vPortEnableVFP+0x10>
80163d8: 6801 ldr r1, [r0, #0]
80163da: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80163de: 6001 str r1, [r0, #0]
80163e0: 4770 bx lr
80163e2: 0000 .short 0x0000
80163e4: e000ed88 .word 0xe000ed88
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 \n"
" .ltorg \n"
);
}
80163e8: bf00 nop
80163ea: bf00 nop
080163ec <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/
#if ( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
80163ec: b480 push {r7}
80163ee: b085 sub sp, #20
80163f0: af00 add r7, sp, #0
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
80163f2: f3ef 8305 mrs r3, IPSR
80163f6: 60fb str r3, [r7, #12]
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
80163f8: 68fb ldr r3, [r7, #12]
80163fa: 2b0f cmp r3, #15
80163fc: d915 bls.n 801642a <vPortValidateInterruptPriority+0x3e>
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
80163fe: 4a18 ldr r2, [pc, #96] @ (8016460 <vPortValidateInterruptPriority+0x74>)
8016400: 68fb ldr r3, [r7, #12]
8016402: 4413 add r3, r2
8016404: 781b ldrb r3, [r3, #0]
8016406: 72fb strb r3, [r7, #11]
* interrupt entry is as fast and simple as possible.
*
* The following links provide detailed information:
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
* https://www.FreeRTOS.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
8016408: 4b16 ldr r3, [pc, #88] @ (8016464 <vPortValidateInterruptPriority+0x78>)
801640a: 781b ldrb r3, [r3, #0]
801640c: 7afa ldrb r2, [r7, #11]
801640e: 429a cmp r2, r3
8016410: d20b bcs.n 801642a <vPortValidateInterruptPriority+0x3e>
__asm volatile
8016412: f04f 0350 mov.w r3, #80 @ 0x50
8016416: f383 8811 msr BASEPRI, r3
801641a: f3bf 8f6f isb sy
801641e: f3bf 8f4f dsb sy
8016422: 607b str r3, [r7, #4]
}
8016424: bf00 nop
8016426: bf00 nop
8016428: e7fd b.n 8016426 <vPortValidateInterruptPriority+0x3a>
* configuration then the correct setting can be achieved on all Cortex-M
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
* scheduler. Note however that some vendor specific peripheral libraries
* assume a non-zero priority group setting, in which cases using a value
* of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
801642a: 4b0f ldr r3, [pc, #60] @ (8016468 <vPortValidateInterruptPriority+0x7c>)
801642c: 681b ldr r3, [r3, #0]
801642e: f403 62e0 and.w r2, r3, #1792 @ 0x700
8016432: 4b0e ldr r3, [pc, #56] @ (801646c <vPortValidateInterruptPriority+0x80>)
8016434: 681b ldr r3, [r3, #0]
8016436: 429a cmp r2, r3
8016438: d90b bls.n 8016452 <vPortValidateInterruptPriority+0x66>
__asm volatile
801643a: f04f 0350 mov.w r3, #80 @ 0x50
801643e: f383 8811 msr BASEPRI, r3
8016442: f3bf 8f6f isb sy
8016446: f3bf 8f4f dsb sy
801644a: 603b str r3, [r7, #0]
}
801644c: bf00 nop
801644e: bf00 nop
8016450: e7fd b.n 801644e <vPortValidateInterruptPriority+0x62>
}
8016452: bf00 nop
8016454: 3714 adds r7, #20
8016456: 46bd mov sp, r7
8016458: f85d 7b04 ldr.w r7, [sp], #4
801645c: 4770 bx lr
801645e: bf00 nop
8016460: e000e3f0 .word 0xe000e3f0
8016464: 200026f4 .word 0x200026f4
8016468: e000ed0c .word 0xe000ed0c
801646c: 200026f8 .word 0x200026f8
08016470 <pvPortMalloc>:
PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
/*-----------------------------------------------------------*/
void * pvPortMalloc( size_t xWantedSize )
{
8016470: b580 push {r7, lr}
8016472: b08a sub sp, #40 @ 0x28
8016474: af00 add r7, sp, #0
8016476: 6078 str r0, [r7, #4]
BlockLink_t * pxBlock;
BlockLink_t * pxPreviousBlock;
BlockLink_t * pxNewBlockLink;
void * pvReturn = NULL;
8016478: 2300 movs r3, #0
801647a: 61fb str r3, [r7, #28]
size_t xAdditionalRequiredSize;
vTaskSuspendAll();
801647c: f7fd fe68 bl 8014150 <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
* initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
8016480: 4b5c ldr r3, [pc, #368] @ (80165f4 <pvPortMalloc+0x184>)
8016482: 681b ldr r3, [r3, #0]
8016484: 2b00 cmp r3, #0
8016486: d101 bne.n 801648c <pvPortMalloc+0x1c>
{
prvHeapInit();
8016488: f000 f918 bl 80166bc <prvHeapInit>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xWantedSize > 0 )
801648c: 687b ldr r3, [r7, #4]
801648e: 2b00 cmp r3, #0
8016490: d022 beq.n 80164d8 <pvPortMalloc+0x68>
{
/* The wanted size must be increased so it can contain a BlockLink_t
* structure in addition to the requested amount of bytes. */
if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 )
8016492: 2308 movs r3, #8
8016494: 43db mvns r3, r3
8016496: 687a ldr r2, [r7, #4]
8016498: 429a cmp r2, r3
801649a: d81b bhi.n 80164d4 <pvPortMalloc+0x64>
{
xWantedSize += xHeapStructSize;
801649c: 2208 movs r2, #8
801649e: 687b ldr r3, [r7, #4]
80164a0: 4413 add r3, r2
80164a2: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
* of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
80164a4: 687b ldr r3, [r7, #4]
80164a6: f003 0307 and.w r3, r3, #7
80164aa: 2b00 cmp r3, #0
80164ac: d014 beq.n 80164d8 <pvPortMalloc+0x68>
{
/* Byte alignment required. */
xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK );
80164ae: 687b ldr r3, [r7, #4]
80164b0: f003 0307 and.w r3, r3, #7
80164b4: f1c3 0308 rsb r3, r3, #8
80164b8: 61bb str r3, [r7, #24]
if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 )
80164ba: 69bb ldr r3, [r7, #24]
80164bc: 43db mvns r3, r3
80164be: 687a ldr r2, [r7, #4]
80164c0: 429a cmp r2, r3
80164c2: d804 bhi.n 80164ce <pvPortMalloc+0x5e>
{
xWantedSize += xAdditionalRequiredSize;
80164c4: 687a ldr r2, [r7, #4]
80164c6: 69bb ldr r3, [r7, #24]
80164c8: 4413 add r3, r2
80164ca: 607b str r3, [r7, #4]
80164cc: e004 b.n 80164d8 <pvPortMalloc+0x68>
}
else
{
xWantedSize = 0;
80164ce: 2300 movs r3, #0
80164d0: 607b str r3, [r7, #4]
80164d2: e001 b.n 80164d8 <pvPortMalloc+0x68>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
xWantedSize = 0;
80164d4: 2300 movs r3, #0
80164d6: 607b str r3, [r7, #4]
/* Check the block size we are trying to allocate is not so large that the
* top bit is set. The top bit of the block size member of the BlockLink_t
* structure is used to determine who owns the block - the application or
* the kernel, so it must be free. */
if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 )
80164d8: 687b ldr r3, [r7, #4]
80164da: 2b00 cmp r3, #0
80164dc: db71 blt.n 80165c2 <pvPortMalloc+0x152>
{
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
80164de: 687b ldr r3, [r7, #4]
80164e0: 2b00 cmp r3, #0
80164e2: d06e beq.n 80165c2 <pvPortMalloc+0x152>
80164e4: 4b44 ldr r3, [pc, #272] @ (80165f8 <pvPortMalloc+0x188>)
80164e6: 681b ldr r3, [r3, #0]
80164e8: 687a ldr r2, [r7, #4]
80164ea: 429a cmp r2, r3
80164ec: d869 bhi.n 80165c2 <pvPortMalloc+0x152>
{
/* Traverse the list from the start (lowest address) block until
* one of adequate size is found. */
pxPreviousBlock = &xStart;
80164ee: 4b43 ldr r3, [pc, #268] @ (80165fc <pvPortMalloc+0x18c>)
80164f0: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
80164f2: 4b42 ldr r3, [pc, #264] @ (80165fc <pvPortMalloc+0x18c>)
80164f4: 681b ldr r3, [r3, #0]
80164f6: 627b str r3, [r7, #36] @ 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
80164f8: e004 b.n 8016504 <pvPortMalloc+0x94>
{
pxPreviousBlock = pxBlock;
80164fa: 6a7b ldr r3, [r7, #36] @ 0x24
80164fc: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
80164fe: 6a7b ldr r3, [r7, #36] @ 0x24
8016500: 681b ldr r3, [r3, #0]
8016502: 627b str r3, [r7, #36] @ 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
8016504: 6a7b ldr r3, [r7, #36] @ 0x24
8016506: 685b ldr r3, [r3, #4]
8016508: 687a ldr r2, [r7, #4]
801650a: 429a cmp r2, r3
801650c: d903 bls.n 8016516 <pvPortMalloc+0xa6>
801650e: 6a7b ldr r3, [r7, #36] @ 0x24
8016510: 681b ldr r3, [r3, #0]
8016512: 2b00 cmp r3, #0
8016514: d1f1 bne.n 80164fa <pvPortMalloc+0x8a>
}
/* If the end marker was reached then a block of adequate size
* was not found. */
if( pxBlock != pxEnd )
8016516: 4b37 ldr r3, [pc, #220] @ (80165f4 <pvPortMalloc+0x184>)
8016518: 681b ldr r3, [r3, #0]
801651a: 6a7a ldr r2, [r7, #36] @ 0x24
801651c: 429a cmp r2, r3
801651e: d050 beq.n 80165c2 <pvPortMalloc+0x152>
{
/* Return the memory space pointed to - jumping over the
* BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
8016520: 6a3b ldr r3, [r7, #32]
8016522: 681b ldr r3, [r3, #0]
8016524: 2208 movs r2, #8
8016526: 4413 add r3, r2
8016528: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
* of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
801652a: 6a7b ldr r3, [r7, #36] @ 0x24
801652c: 681a ldr r2, [r3, #0]
801652e: 6a3b ldr r3, [r7, #32]
8016530: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
* two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
8016532: 6a7b ldr r3, [r7, #36] @ 0x24
8016534: 685a ldr r2, [r3, #4]
8016536: 687b ldr r3, [r7, #4]
8016538: 1ad2 subs r2, r2, r3
801653a: 2308 movs r3, #8
801653c: 005b lsls r3, r3, #1
801653e: 429a cmp r2, r3
8016540: d920 bls.n 8016584 <pvPortMalloc+0x114>
{
/* This block is to be split into two. Create a new
* block following the number of bytes requested. The void
* cast is used to prevent byte alignment warnings from the
* compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
8016542: 6a7a ldr r2, [r7, #36] @ 0x24
8016544: 687b ldr r3, [r7, #4]
8016546: 4413 add r3, r2
8016548: 617b str r3, [r7, #20]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
801654a: 697b ldr r3, [r7, #20]
801654c: f003 0307 and.w r3, r3, #7
8016550: 2b00 cmp r3, #0
8016552: d00b beq.n 801656c <pvPortMalloc+0xfc>
__asm volatile
8016554: f04f 0350 mov.w r3, #80 @ 0x50
8016558: f383 8811 msr BASEPRI, r3
801655c: f3bf 8f6f isb sy
8016560: f3bf 8f4f dsb sy
8016564: 613b str r3, [r7, #16]
}
8016566: bf00 nop
8016568: bf00 nop
801656a: e7fd b.n 8016568 <pvPortMalloc+0xf8>
/* Calculate the sizes of two blocks split from the
* single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
801656c: 6a7b ldr r3, [r7, #36] @ 0x24
801656e: 685a ldr r2, [r3, #4]
8016570: 687b ldr r3, [r7, #4]
8016572: 1ad2 subs r2, r2, r3
8016574: 697b ldr r3, [r7, #20]
8016576: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
8016578: 6a7b ldr r3, [r7, #36] @ 0x24
801657a: 687a ldr r2, [r7, #4]
801657c: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
801657e: 6978 ldr r0, [r7, #20]
8016580: f000 f8f8 bl 8016774 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
8016584: 4b1c ldr r3, [pc, #112] @ (80165f8 <pvPortMalloc+0x188>)
8016586: 681a ldr r2, [r3, #0]
8016588: 6a7b ldr r3, [r7, #36] @ 0x24
801658a: 685b ldr r3, [r3, #4]
801658c: 1ad3 subs r3, r2, r3
801658e: 4a1a ldr r2, [pc, #104] @ (80165f8 <pvPortMalloc+0x188>)
8016590: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
8016592: 4b19 ldr r3, [pc, #100] @ (80165f8 <pvPortMalloc+0x188>)
8016594: 681a ldr r2, [r3, #0]
8016596: 4b1a ldr r3, [pc, #104] @ (8016600 <pvPortMalloc+0x190>)
8016598: 681b ldr r3, [r3, #0]
801659a: 429a cmp r2, r3
801659c: d203 bcs.n 80165a6 <pvPortMalloc+0x136>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
801659e: 4b16 ldr r3, [pc, #88] @ (80165f8 <pvPortMalloc+0x188>)
80165a0: 681b ldr r3, [r3, #0]
80165a2: 4a17 ldr r2, [pc, #92] @ (8016600 <pvPortMalloc+0x190>)
80165a4: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
* by the application and has no "next" block. */
heapALLOCATE_BLOCK( pxBlock );
80165a6: 6a7b ldr r3, [r7, #36] @ 0x24
80165a8: 685b ldr r3, [r3, #4]
80165aa: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
80165ae: 6a7b ldr r3, [r7, #36] @ 0x24
80165b0: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
80165b2: 6a7b ldr r3, [r7, #36] @ 0x24
80165b4: 2200 movs r2, #0
80165b6: 601a str r2, [r3, #0]
xNumberOfSuccessfulAllocations++;
80165b8: 4b12 ldr r3, [pc, #72] @ (8016604 <pvPortMalloc+0x194>)
80165ba: 681b ldr r3, [r3, #0]
80165bc: 3301 adds r3, #1
80165be: 4a11 ldr r2, [pc, #68] @ (8016604 <pvPortMalloc+0x194>)
80165c0: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
80165c2: f7fd fdd3 bl 801416c <xTaskResumeAll>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
80165c6: 69fb ldr r3, [r7, #28]
80165c8: f003 0307 and.w r3, r3, #7
80165cc: 2b00 cmp r3, #0
80165ce: d00b beq.n 80165e8 <pvPortMalloc+0x178>
__asm volatile
80165d0: f04f 0350 mov.w r3, #80 @ 0x50
80165d4: f383 8811 msr BASEPRI, r3
80165d8: f3bf 8f6f isb sy
80165dc: f3bf 8f4f dsb sy
80165e0: 60fb str r3, [r7, #12]
}
80165e2: bf00 nop
80165e4: bf00 nop
80165e6: e7fd b.n 80165e4 <pvPortMalloc+0x174>
return pvReturn;
80165e8: 69fb ldr r3, [r7, #28]
}
80165ea: 4618 mov r0, r3
80165ec: 3728 adds r7, #40 @ 0x28
80165ee: 46bd mov sp, r7
80165f0: bd80 pop {r7, pc}
80165f2: bf00 nop
80165f4: 20012104 .word 0x20012104
80165f8: 20012108 .word 0x20012108
80165fc: 200120fc .word 0x200120fc
8016600: 2001210c .word 0x2001210c
8016604: 20012110 .word 0x20012110
08016608 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void * pv )
{
8016608: b580 push {r7, lr}
801660a: b086 sub sp, #24
801660c: af00 add r7, sp, #0
801660e: 6078 str r0, [r7, #4]
uint8_t * puc = ( uint8_t * ) pv;
8016610: 687b ldr r3, [r7, #4]
8016612: 617b str r3, [r7, #20]
BlockLink_t * pxLink;
if( pv != NULL )
8016614: 687b ldr r3, [r7, #4]
8016616: 2b00 cmp r3, #0
8016618: d047 beq.n 80166aa <vPortFree+0xa2>
{
/* The memory being freed will have an BlockLink_t structure immediately
* before it. */
puc -= xHeapStructSize;
801661a: 2308 movs r3, #8
801661c: 425b negs r3, r3
801661e: 697a ldr r2, [r7, #20]
8016620: 4413 add r3, r2
8016622: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
8016624: 697b ldr r3, [r7, #20]
8016626: 613b str r3, [r7, #16]
configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 );
8016628: 693b ldr r3, [r7, #16]
801662a: 685b ldr r3, [r3, #4]
801662c: 2b00 cmp r3, #0
801662e: db0b blt.n 8016648 <vPortFree+0x40>
__asm volatile
8016630: f04f 0350 mov.w r3, #80 @ 0x50
8016634: f383 8811 msr BASEPRI, r3
8016638: f3bf 8f6f isb sy
801663c: f3bf 8f4f dsb sy
8016640: 60fb str r3, [r7, #12]
}
8016642: bf00 nop
8016644: bf00 nop
8016646: e7fd b.n 8016644 <vPortFree+0x3c>
configASSERT( pxLink->pxNextFreeBlock == NULL );
8016648: 693b ldr r3, [r7, #16]
801664a: 681b ldr r3, [r3, #0]
801664c: 2b00 cmp r3, #0
801664e: d00b beq.n 8016668 <vPortFree+0x60>
__asm volatile
8016650: f04f 0350 mov.w r3, #80 @ 0x50
8016654: f383 8811 msr BASEPRI, r3
8016658: f3bf 8f6f isb sy
801665c: f3bf 8f4f dsb sy
8016660: 60bb str r3, [r7, #8]
}
8016662: bf00 nop
8016664: bf00 nop
8016666: e7fd b.n 8016664 <vPortFree+0x5c>
if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 )
8016668: 693b ldr r3, [r7, #16]
801666a: 685b ldr r3, [r3, #4]
801666c: 2b00 cmp r3, #0
801666e: da1c bge.n 80166aa <vPortFree+0xa2>
{
if( pxLink->pxNextFreeBlock == NULL )
8016670: 693b ldr r3, [r7, #16]
8016672: 681b ldr r3, [r3, #0]
8016674: 2b00 cmp r3, #0
8016676: d118 bne.n 80166aa <vPortFree+0xa2>
{
/* The block is being returned to the heap - it is no longer
* allocated. */
heapFREE_BLOCK( pxLink );
8016678: 693b ldr r3, [r7, #16]
801667a: 685b ldr r3, [r3, #4]
801667c: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8016680: 693b ldr r3, [r7, #16]
8016682: 605a str r2, [r3, #4]
{
( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize );
}
#endif
vTaskSuspendAll();
8016684: f7fd fd64 bl 8014150 <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
8016688: 693b ldr r3, [r7, #16]
801668a: 685a ldr r2, [r3, #4]
801668c: 4b09 ldr r3, [pc, #36] @ (80166b4 <vPortFree+0xac>)
801668e: 681b ldr r3, [r3, #0]
8016690: 4413 add r3, r2
8016692: 4a08 ldr r2, [pc, #32] @ (80166b4 <vPortFree+0xac>)
8016694: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
8016696: 6938 ldr r0, [r7, #16]
8016698: f000 f86c bl 8016774 <prvInsertBlockIntoFreeList>
xNumberOfSuccessfulFrees++;
801669c: 4b06 ldr r3, [pc, #24] @ (80166b8 <vPortFree+0xb0>)
801669e: 681b ldr r3, [r3, #0]
80166a0: 3301 adds r3, #1
80166a2: 4a05 ldr r2, [pc, #20] @ (80166b8 <vPortFree+0xb0>)
80166a4: 6013 str r3, [r2, #0]
}
( void ) xTaskResumeAll();
80166a6: f7fd fd61 bl 801416c <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
80166aa: bf00 nop
80166ac: 3718 adds r7, #24
80166ae: 46bd mov sp, r7
80166b0: bd80 pop {r7, pc}
80166b2: bf00 nop
80166b4: 20012108 .word 0x20012108
80166b8: 20012114 .word 0x20012114
080166bc <prvHeapInit>:
return pv;
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
{
80166bc: b480 push {r7}
80166be: b085 sub sp, #20
80166c0: af00 add r7, sp, #0
BlockLink_t * pxFirstFreeBlock;
uint8_t * pucAlignedHeap;
portPOINTER_SIZE_TYPE uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
80166c2: f44f 437a mov.w r3, #64000 @ 0xfa00
80166c6: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap;
80166c8: 4b25 ldr r3, [pc, #148] @ (8016760 <prvHeapInit+0xa4>)
80166ca: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
80166cc: 68fb ldr r3, [r7, #12]
80166ce: f003 0307 and.w r3, r3, #7
80166d2: 2b00 cmp r3, #0
80166d4: d00c beq.n 80166f0 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
80166d6: 68fb ldr r3, [r7, #12]
80166d8: 3307 adds r3, #7
80166da: 60fb str r3, [r7, #12]
uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
80166dc: 68fb ldr r3, [r7, #12]
80166de: f023 0307 bic.w r3, r3, #7
80166e2: 60fb str r3, [r7, #12]
xTotalHeapSize -= ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap );
80166e4: 68ba ldr r2, [r7, #8]
80166e6: 68fb ldr r3, [r7, #12]
80166e8: 1ad3 subs r3, r2, r3
80166ea: 4a1d ldr r2, [pc, #116] @ (8016760 <prvHeapInit+0xa4>)
80166ec: 4413 add r3, r2
80166ee: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
80166f0: 68fb ldr r3, [r7, #12]
80166f2: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
* blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
80166f4: 4a1b ldr r2, [pc, #108] @ (8016764 <prvHeapInit+0xa8>)
80166f6: 687b ldr r3, [r7, #4]
80166f8: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
80166fa: 4b1a ldr r3, [pc, #104] @ (8016764 <prvHeapInit+0xa8>)
80166fc: 2200 movs r2, #0
80166fe: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
* at the end of the heap space. */
uxAddress = ( portPOINTER_SIZE_TYPE ) ( pucAlignedHeap + xTotalHeapSize );
8016700: 687a ldr r2, [r7, #4]
8016702: 68bb ldr r3, [r7, #8]
8016704: 4413 add r3, r2
8016706: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
8016708: 2208 movs r2, #8
801670a: 68fb ldr r3, [r7, #12]
801670c: 1a9b subs r3, r3, r2
801670e: 60fb str r3, [r7, #12]
uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK );
8016710: 68fb ldr r3, [r7, #12]
8016712: f023 0307 bic.w r3, r3, #7
8016716: 60fb str r3, [r7, #12]
pxEnd = ( BlockLink_t * ) uxAddress;
8016718: 68fb ldr r3, [r7, #12]
801671a: 4a13 ldr r2, [pc, #76] @ (8016768 <prvHeapInit+0xac>)
801671c: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
801671e: 4b12 ldr r3, [pc, #72] @ (8016768 <prvHeapInit+0xac>)
8016720: 681b ldr r3, [r3, #0]
8016722: 2200 movs r2, #0
8016724: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
8016726: 4b10 ldr r3, [pc, #64] @ (8016768 <prvHeapInit+0xac>)
8016728: 681b ldr r3, [r3, #0]
801672a: 2200 movs r2, #0
801672c: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
* entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap;
801672e: 687b ldr r3, [r7, #4]
8016730: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock );
8016732: 683b ldr r3, [r7, #0]
8016734: 68fa ldr r2, [r7, #12]
8016736: 1ad2 subs r2, r2, r3
8016738: 683b ldr r3, [r7, #0]
801673a: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
801673c: 4b0a ldr r3, [pc, #40] @ (8016768 <prvHeapInit+0xac>)
801673e: 681a ldr r2, [r3, #0]
8016740: 683b ldr r3, [r7, #0]
8016742: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
8016744: 683b ldr r3, [r7, #0]
8016746: 685b ldr r3, [r3, #4]
8016748: 4a08 ldr r2, [pc, #32] @ (801676c <prvHeapInit+0xb0>)
801674a: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
801674c: 683b ldr r3, [r7, #0]
801674e: 685b ldr r3, [r3, #4]
8016750: 4a07 ldr r2, [pc, #28] @ (8016770 <prvHeapInit+0xb4>)
8016752: 6013 str r3, [r2, #0]
}
8016754: bf00 nop
8016756: 3714 adds r7, #20
8016758: 46bd mov sp, r7
801675a: f85d 7b04 ldr.w r7, [sp], #4
801675e: 4770 bx lr
8016760: 200026fc .word 0x200026fc
8016764: 200120fc .word 0x200120fc
8016768: 20012104 .word 0x20012104
801676c: 2001210c .word 0x2001210c
8016770: 20012108 .word 0x20012108
08016774 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */
{
8016774: b480 push {r7}
8016776: b085 sub sp, #20
8016778: af00 add r7, sp, #0
801677a: 6078 str r0, [r7, #4]
BlockLink_t * pxIterator;
uint8_t * puc;
/* Iterate through the list until a block is found that has a higher address
* than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
801677c: 4b28 ldr r3, [pc, #160] @ (8016820 <prvInsertBlockIntoFreeList+0xac>)
801677e: 60fb str r3, [r7, #12]
8016780: e002 b.n 8016788 <prvInsertBlockIntoFreeList+0x14>
8016782: 68fb ldr r3, [r7, #12]
8016784: 681b ldr r3, [r3, #0]
8016786: 60fb str r3, [r7, #12]
8016788: 68fb ldr r3, [r7, #12]
801678a: 681b ldr r3, [r3, #0]
801678c: 687a ldr r2, [r7, #4]
801678e: 429a cmp r2, r3
8016790: d8f7 bhi.n 8016782 <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
* make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
8016792: 68fb ldr r3, [r7, #12]
8016794: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
8016796: 68fb ldr r3, [r7, #12]
8016798: 685b ldr r3, [r3, #4]
801679a: 68ba ldr r2, [r7, #8]
801679c: 4413 add r3, r2
801679e: 687a ldr r2, [r7, #4]
80167a0: 429a cmp r2, r3
80167a2: d108 bne.n 80167b6 <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
80167a4: 68fb ldr r3, [r7, #12]
80167a6: 685a ldr r2, [r3, #4]
80167a8: 687b ldr r3, [r7, #4]
80167aa: 685b ldr r3, [r3, #4]
80167ac: 441a add r2, r3
80167ae: 68fb ldr r3, [r7, #12]
80167b0: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
80167b2: 68fb ldr r3, [r7, #12]
80167b4: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
* make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
80167b6: 687b ldr r3, [r7, #4]
80167b8: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
80167ba: 687b ldr r3, [r7, #4]
80167bc: 685b ldr r3, [r3, #4]
80167be: 68ba ldr r2, [r7, #8]
80167c0: 441a add r2, r3
80167c2: 68fb ldr r3, [r7, #12]
80167c4: 681b ldr r3, [r3, #0]
80167c6: 429a cmp r2, r3
80167c8: d118 bne.n 80167fc <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
80167ca: 68fb ldr r3, [r7, #12]
80167cc: 681a ldr r2, [r3, #0]
80167ce: 4b15 ldr r3, [pc, #84] @ (8016824 <prvInsertBlockIntoFreeList+0xb0>)
80167d0: 681b ldr r3, [r3, #0]
80167d2: 429a cmp r2, r3
80167d4: d00d beq.n 80167f2 <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
80167d6: 687b ldr r3, [r7, #4]
80167d8: 685a ldr r2, [r3, #4]
80167da: 68fb ldr r3, [r7, #12]
80167dc: 681b ldr r3, [r3, #0]
80167de: 685b ldr r3, [r3, #4]
80167e0: 441a add r2, r3
80167e2: 687b ldr r3, [r7, #4]
80167e4: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
80167e6: 68fb ldr r3, [r7, #12]
80167e8: 681b ldr r3, [r3, #0]
80167ea: 681a ldr r2, [r3, #0]
80167ec: 687b ldr r3, [r7, #4]
80167ee: 601a str r2, [r3, #0]
80167f0: e008 b.n 8016804 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
80167f2: 4b0c ldr r3, [pc, #48] @ (8016824 <prvInsertBlockIntoFreeList+0xb0>)
80167f4: 681a ldr r2, [r3, #0]
80167f6: 687b ldr r3, [r7, #4]
80167f8: 601a str r2, [r3, #0]
80167fa: e003 b.n 8016804 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
80167fc: 68fb ldr r3, [r7, #12]
80167fe: 681a ldr r2, [r3, #0]
8016800: 687b ldr r3, [r7, #4]
8016802: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
* before and the block after, then it's pxNextFreeBlock pointer will have
* already been set, and should not be set here as that would make it point
* to itself. */
if( pxIterator != pxBlockToInsert )
8016804: 68fa ldr r2, [r7, #12]
8016806: 687b ldr r3, [r7, #4]
8016808: 429a cmp r2, r3
801680a: d002 beq.n 8016812 <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
801680c: 68fb ldr r3, [r7, #12]
801680e: 687a ldr r2, [r7, #4]
8016810: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8016812: bf00 nop
8016814: 3714 adds r7, #20
8016816: 46bd mov sp, r7
8016818: f85d 7b04 ldr.w r7, [sp], #4
801681c: 4770 bx lr
801681e: bf00 nop
8016820: 200120fc .word 0x200120fc
8016824: 20012104 .word 0x20012104
08016828 <LL_PWR_EnableBootC2>:
{
8016828: b480 push {r7}
801682a: af00 add r7, sp, #0
SET_BIT(PWR->CR4, PWR_CR4_C2BOOT);
801682c: 4b05 ldr r3, [pc, #20] @ (8016844 <LL_PWR_EnableBootC2+0x1c>)
801682e: 68db ldr r3, [r3, #12]
8016830: 4a04 ldr r2, [pc, #16] @ (8016844 <LL_PWR_EnableBootC2+0x1c>)
8016832: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8016836: 60d3 str r3, [r2, #12]
}
8016838: bf00 nop
801683a: 46bd mov sp, r7
801683c: f85d 7b04 ldr.w r7, [sp], #4
8016840: 4770 bx lr
8016842: bf00 nop
8016844: 58000400 .word 0x58000400
08016848 <LL_C2_EXTI_EnableEvent_32_63>:
{
8016848: b480 push {r7}
801684a: b083 sub sp, #12
801684c: af00 add r7, sp, #0
801684e: 6078 str r0, [r7, #4]
SET_BIT(EXTI->C2EMR2, ExtiLine);
8016850: 4b06 ldr r3, [pc, #24] @ (801686c <LL_C2_EXTI_EnableEvent_32_63+0x24>)
8016852: f8d3 20d4 ldr.w r2, [r3, #212] @ 0xd4
8016856: 4905 ldr r1, [pc, #20] @ (801686c <LL_C2_EXTI_EnableEvent_32_63+0x24>)
8016858: 687b ldr r3, [r7, #4]
801685a: 4313 orrs r3, r2
801685c: f8c1 30d4 str.w r3, [r1, #212] @ 0xd4
}
8016860: bf00 nop
8016862: 370c adds r7, #12
8016864: 46bd mov sp, r7
8016866: f85d 7b04 ldr.w r7, [sp], #4
801686a: 4770 bx lr
801686c: 58000800 .word 0x58000800
08016870 <LL_EXTI_EnableRisingTrig_32_63>:
* @arg @ref LL_EXTI_LINE_41
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
{
8016870: b480 push {r7}
8016872: b083 sub sp, #12
8016874: af00 add r7, sp, #0
8016876: 6078 str r0, [r7, #4]
SET_BIT(EXTI->RTSR2, ExtiLine);
8016878: 4b05 ldr r3, [pc, #20] @ (8016890 <LL_EXTI_EnableRisingTrig_32_63+0x20>)
801687a: 6a1a ldr r2, [r3, #32]
801687c: 4904 ldr r1, [pc, #16] @ (8016890 <LL_EXTI_EnableRisingTrig_32_63+0x20>)
801687e: 687b ldr r3, [r7, #4]
8016880: 4313 orrs r3, r2
8016882: 620b str r3, [r1, #32]
}
8016884: bf00 nop
8016886: 370c adds r7, #12
8016888: 46bd mov sp, r7
801688a: f85d 7b04 ldr.w r7, [sp], #4
801688e: 4770 bx lr
8016890: 58000800 .word 0x58000800
08016894 <LL_AHB3_GRP1_EnableClock>:
{
8016894: b480 push {r7}
8016896: b085 sub sp, #20
8016898: af00 add r7, sp, #0
801689a: 6078 str r0, [r7, #4]
SET_BIT(RCC->AHB3ENR, Periphs);
801689c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80168a0: 6d1a ldr r2, [r3, #80] @ 0x50
80168a2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
80168a6: 687b ldr r3, [r7, #4]
80168a8: 4313 orrs r3, r2
80168aa: 650b str r3, [r1, #80] @ 0x50
tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
80168ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80168b0: 6d1a ldr r2, [r3, #80] @ 0x50
80168b2: 687b ldr r3, [r7, #4]
80168b4: 4013 ands r3, r2
80168b6: 60fb str r3, [r7, #12]
(void)tmpreg;
80168b8: 68fb ldr r3, [r7, #12]
}
80168ba: bf00 nop
80168bc: 3714 adds r7, #20
80168be: 46bd mov sp, r7
80168c0: f85d 7b04 ldr.w r7, [sp], #4
80168c4: 4770 bx lr
080168c6 <LL_C2_AHB3_GRP1_EnableClock>:
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
* @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
* @retval None
*/
__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
{
80168c6: b480 push {r7}
80168c8: b085 sub sp, #20
80168ca: af00 add r7, sp, #0
80168cc: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg;
SET_BIT(RCC->C2AHB3ENR, Periphs);
80168ce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80168d2: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150
80168d6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
80168da: 687b ldr r3, [r7, #4]
80168dc: 4313 orrs r3, r2
80168de: f8c1 3150 str.w r3, [r1, #336] @ 0x150
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs);
80168e2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80168e6: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150
80168ea: 687b ldr r3, [r7, #4]
80168ec: 4013 ands r3, r2
80168ee: 60fb str r3, [r7, #12]
(void)tmpreg;
80168f0: 68fb ldr r3, [r7, #12]
}
80168f2: bf00 nop
80168f4: 3714 adds r7, #20
80168f6: 46bd mov sp, r7
80168f8: f85d 7b04 ldr.w r7, [sp], #4
80168fc: 4770 bx lr
080168fe <LL_C1_IPCC_EnableIT_TXF>:
* @rmtoll C1CR TXFIE LL_C1_IPCC_EnableIT_TXF
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
{
80168fe: b480 push {r7}
8016900: b083 sub sp, #12
8016902: af00 add r7, sp, #0
8016904: 6078 str r0, [r7, #4]
SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
8016906: 687b ldr r3, [r7, #4]
8016908: 681b ldr r3, [r3, #0]
801690a: f443 3280 orr.w r2, r3, #65536 @ 0x10000
801690e: 687b ldr r3, [r7, #4]
8016910: 601a str r2, [r3, #0]
}
8016912: bf00 nop
8016914: 370c adds r7, #12
8016916: 46bd mov sp, r7
8016918: f85d 7b04 ldr.w r7, [sp], #4
801691c: 4770 bx lr
0801691e <LL_C1_IPCC_EnableIT_RXO>:
* @rmtoll C1CR RXOIE LL_C1_IPCC_EnableIT_RXO
* @param IPCCx IPCC Instance.
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
{
801691e: b480 push {r7}
8016920: b083 sub sp, #12
8016922: af00 add r7, sp, #0
8016924: 6078 str r0, [r7, #4]
SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
8016926: 687b ldr r3, [r7, #4]
8016928: 681b ldr r3, [r3, #0]
801692a: f043 0201 orr.w r2, r3, #1
801692e: 687b ldr r3, [r7, #4]
8016930: 601a str r2, [r3, #0]
}
8016932: bf00 nop
8016934: 370c adds r7, #12
8016936: 46bd mov sp, r7
8016938: f85d 7b04 ldr.w r7, [sp], #4
801693c: 4770 bx lr
0801693e <LL_C1_IPCC_EnableTransmitChannel>:
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
801693e: b480 push {r7}
8016940: b083 sub sp, #12
8016942: af00 add r7, sp, #0
8016944: 6078 str r0, [r7, #4]
8016946: 6039 str r1, [r7, #0]
CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
8016948: 687b ldr r3, [r7, #4]
801694a: 685a ldr r2, [r3, #4]
801694c: 683b ldr r3, [r7, #0]
801694e: 041b lsls r3, r3, #16
8016950: 43db mvns r3, r3
8016952: 401a ands r2, r3
8016954: 687b ldr r3, [r7, #4]
8016956: 605a str r2, [r3, #4]
}
8016958: bf00 nop
801695a: 370c adds r7, #12
801695c: 46bd mov sp, r7
801695e: f85d 7b04 ldr.w r7, [sp], #4
8016962: 4770 bx lr
08016964 <LL_C1_IPCC_DisableTransmitChannel>:
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
8016964: b480 push {r7}
8016966: b083 sub sp, #12
8016968: af00 add r7, sp, #0
801696a: 6078 str r0, [r7, #4]
801696c: 6039 str r1, [r7, #0]
SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
801696e: 687b ldr r3, [r7, #4]
8016970: 685a ldr r2, [r3, #4]
8016972: 683b ldr r3, [r7, #0]
8016974: 041b lsls r3, r3, #16
8016976: 431a orrs r2, r3
8016978: 687b ldr r3, [r7, #4]
801697a: 605a str r2, [r3, #4]
}
801697c: bf00 nop
801697e: 370c adds r7, #12
8016980: 46bd mov sp, r7
8016982: f85d 7b04 ldr.w r7, [sp], #4
8016986: 4770 bx lr
08016988 <LL_C1_IPCC_EnableReceiveChannel>:
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
8016988: b480 push {r7}
801698a: b083 sub sp, #12
801698c: af00 add r7, sp, #0
801698e: 6078 str r0, [r7, #4]
8016990: 6039 str r1, [r7, #0]
CLEAR_BIT(IPCCx->C1MR, Channel);
8016992: 687b ldr r3, [r7, #4]
8016994: 685a ldr r2, [r3, #4]
8016996: 683b ldr r3, [r7, #0]
8016998: 43db mvns r3, r3
801699a: 401a ands r2, r3
801699c: 687b ldr r3, [r7, #4]
801699e: 605a str r2, [r3, #4]
}
80169a0: bf00 nop
80169a2: 370c adds r7, #12
80169a4: 46bd mov sp, r7
80169a6: f85d 7b04 ldr.w r7, [sp], #4
80169aa: 4770 bx lr
080169ac <LL_C1_IPCC_ClearFlag_CHx>:
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
80169ac: b480 push {r7}
80169ae: b083 sub sp, #12
80169b0: af00 add r7, sp, #0
80169b2: 6078 str r0, [r7, #4]
80169b4: 6039 str r1, [r7, #0]
WRITE_REG(IPCCx->C1SCR, Channel);
80169b6: 687b ldr r3, [r7, #4]
80169b8: 683a ldr r2, [r7, #0]
80169ba: 609a str r2, [r3, #8]
}
80169bc: bf00 nop
80169be: 370c adds r7, #12
80169c0: 46bd mov sp, r7
80169c2: f85d 7b04 ldr.w r7, [sp], #4
80169c6: 4770 bx lr
080169c8 <LL_C1_IPCC_SetFlag_CHx>:
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval None
*/
__STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
{
80169c8: b480 push {r7}
80169ca: b083 sub sp, #12
80169cc: af00 add r7, sp, #0
80169ce: 6078 str r0, [r7, #4]
80169d0: 6039 str r1, [r7, #0]
WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos);
80169d2: 683b ldr r3, [r7, #0]
80169d4: 041a lsls r2, r3, #16
80169d6: 687b ldr r3, [r7, #4]
80169d8: 609a str r2, [r3, #8]
}
80169da: bf00 nop
80169dc: 370c adds r7, #12
80169de: 46bd mov sp, r7
80169e0: f85d 7b04 ldr.w r7, [sp], #4
80169e4: 4770 bx lr
080169e6 <LL_C1_IPCC_IsActiveFlag_CHx>:
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
{
80169e6: b480 push {r7}
80169e8: b083 sub sp, #12
80169ea: af00 add r7, sp, #0
80169ec: 6078 str r0, [r7, #4]
80169ee: 6039 str r1, [r7, #0]
return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL);
80169f0: 687b ldr r3, [r7, #4]
80169f2: 68da ldr r2, [r3, #12]
80169f4: 683b ldr r3, [r7, #0]
80169f6: 4013 ands r3, r2
80169f8: 683a ldr r2, [r7, #0]
80169fa: 429a cmp r2, r3
80169fc: d101 bne.n 8016a02 <LL_C1_IPCC_IsActiveFlag_CHx+0x1c>
80169fe: 2301 movs r3, #1
8016a00: e000 b.n 8016a04 <LL_C1_IPCC_IsActiveFlag_CHx+0x1e>
8016a02: 2300 movs r3, #0
}
8016a04: 4618 mov r0, r3
8016a06: 370c adds r7, #12
8016a08: 46bd mov sp, r7
8016a0a: f85d 7b04 ldr.w r7, [sp], #4
8016a0e: 4770 bx lr
08016a10 <LL_C2_IPCC_IsActiveFlag_CHx>:
* @arg @ref LL_IPCC_CHANNEL_5
* @arg @ref LL_IPCC_CHANNEL_6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
{
8016a10: b480 push {r7}
8016a12: b083 sub sp, #12
8016a14: af00 add r7, sp, #0
8016a16: 6078 str r0, [r7, #4]
8016a18: 6039 str r1, [r7, #0]
return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL);
8016a1a: 687b ldr r3, [r7, #4]
8016a1c: 69da ldr r2, [r3, #28]
8016a1e: 683b ldr r3, [r7, #0]
8016a20: 4013 ands r3, r2
8016a22: 683a ldr r2, [r7, #0]
8016a24: 429a cmp r2, r3
8016a26: d101 bne.n 8016a2c <LL_C2_IPCC_IsActiveFlag_CHx+0x1c>
8016a28: 2301 movs r3, #1
8016a2a: e000 b.n 8016a2e <LL_C2_IPCC_IsActiveFlag_CHx+0x1e>
8016a2c: 2300 movs r3, #0
}
8016a2e: 4618 mov r0, r3
8016a30: 370c adds r7, #12
8016a32: 46bd mov sp, r7
8016a34: f85d 7b04 ldr.w r7, [sp], #4
8016a38: 4770 bx lr
...
08016a3c <HW_IPCC_Rx_Handler>:
/******************************************************************************
* INTERRUPT HANDLER
******************************************************************************/
void HW_IPCC_Rx_Handler( void )
{
8016a3c: b580 push {r7, lr}
8016a3e: af00 add r7, sp, #0
if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
8016a40: 2102 movs r1, #2
8016a42: 4818 ldr r0, [pc, #96] @ (8016aa4 <HW_IPCC_Rx_Handler+0x68>)
8016a44: f7ff ffe4 bl 8016a10 <LL_C2_IPCC_IsActiveFlag_CHx>
8016a48: 4603 mov r3, r0
8016a4a: 2b00 cmp r3, #0
8016a4c: d008 beq.n 8016a60 <HW_IPCC_Rx_Handler+0x24>
8016a4e: 4b15 ldr r3, [pc, #84] @ (8016aa4 <HW_IPCC_Rx_Handler+0x68>)
8016a50: 685b ldr r3, [r3, #4]
8016a52: f003 0302 and.w r3, r3, #2
8016a56: 2b00 cmp r3, #0
8016a58: d102 bne.n 8016a60 <HW_IPCC_Rx_Handler+0x24>
{
HW_IPCC_SYS_EvtHandler();
8016a5a: f000 f901 bl 8016c60 <HW_IPCC_SYS_EvtHandler>
8016a5e: e01e b.n 8016a9e <HW_IPCC_Rx_Handler+0x62>
else if (HW_IPCC_RX_PENDING( HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL ))
{
HW_IPCC_ZIGBEE_StackM0RequestHandler();
}
#endif /* ZIGBEE_WB */
else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
8016a60: 2101 movs r1, #1
8016a62: 4810 ldr r0, [pc, #64] @ (8016aa4 <HW_IPCC_Rx_Handler+0x68>)
8016a64: f7ff ffd4 bl 8016a10 <LL_C2_IPCC_IsActiveFlag_CHx>
8016a68: 4603 mov r3, r0
8016a6a: 2b00 cmp r3, #0
8016a6c: d008 beq.n 8016a80 <HW_IPCC_Rx_Handler+0x44>
8016a6e: 4b0d ldr r3, [pc, #52] @ (8016aa4 <HW_IPCC_Rx_Handler+0x68>)
8016a70: 685b ldr r3, [r3, #4]
8016a72: f003 0301 and.w r3, r3, #1
8016a76: 2b00 cmp r3, #0
8016a78: d102 bne.n 8016a80 <HW_IPCC_Rx_Handler+0x44>
{
HW_IPCC_BLE_EvtHandler();
8016a7a: f000 f875 bl 8016b68 <HW_IPCC_BLE_EvtHandler>
8016a7e: e00e b.n 8016a9e <HW_IPCC_Rx_Handler+0x62>
}
else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
8016a80: 2108 movs r1, #8
8016a82: 4808 ldr r0, [pc, #32] @ (8016aa4 <HW_IPCC_Rx_Handler+0x68>)
8016a84: f7ff ffc4 bl 8016a10 <LL_C2_IPCC_IsActiveFlag_CHx>
8016a88: 4603 mov r3, r0
8016a8a: 2b00 cmp r3, #0
8016a8c: d008 beq.n 8016aa0 <HW_IPCC_Rx_Handler+0x64>
8016a8e: 4b05 ldr r3, [pc, #20] @ (8016aa4 <HW_IPCC_Rx_Handler+0x68>)
8016a90: 685b ldr r3, [r3, #4]
8016a92: f003 0308 and.w r3, r3, #8
8016a96: 2b00 cmp r3, #0
8016a98: d102 bne.n 8016aa0 <HW_IPCC_Rx_Handler+0x64>
{
HW_IPCC_TRACES_EvtHandler();
8016a9a: f000 f959 bl 8016d50 <HW_IPCC_TRACES_EvtHandler>
}
return;
8016a9e: bf00 nop
8016aa0: bf00 nop
}
8016aa2: bd80 pop {r7, pc}
8016aa4: 58000c00 .word 0x58000c00
08016aa8 <HW_IPCC_Tx_Handler>:
void HW_IPCC_Tx_Handler( void )
{
8016aa8: b580 push {r7, lr}
8016aaa: af00 add r7, sp, #0
if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
8016aac: 2102 movs r1, #2
8016aae: 4818 ldr r0, [pc, #96] @ (8016b10 <HW_IPCC_Tx_Handler+0x68>)
8016ab0: f7ff ff99 bl 80169e6 <LL_C1_IPCC_IsActiveFlag_CHx>
8016ab4: 4603 mov r3, r0
8016ab6: 2b00 cmp r3, #0
8016ab8: d108 bne.n 8016acc <HW_IPCC_Tx_Handler+0x24>
8016aba: 4b15 ldr r3, [pc, #84] @ (8016b10 <HW_IPCC_Tx_Handler+0x68>)
8016abc: 685b ldr r3, [r3, #4]
8016abe: f403 3300 and.w r3, r3, #131072 @ 0x20000
8016ac2: 2b00 cmp r3, #0
8016ac4: d102 bne.n 8016acc <HW_IPCC_Tx_Handler+0x24>
{
HW_IPCC_SYS_CmdEvtHandler();
8016ac6: f000 f8af bl 8016c28 <HW_IPCC_SYS_CmdEvtHandler>
8016aca: e01e b.n 8016b0a <HW_IPCC_Tx_Handler+0x62>
if (HW_IPCC_TX_PENDING( HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL ))
{
HW_IPCC_ZIGBEE_CmdEvtHandler();
}
#endif /* ZIGBEE_WB */
else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
8016acc: 2108 movs r1, #8
8016ace: 4810 ldr r0, [pc, #64] @ (8016b10 <HW_IPCC_Tx_Handler+0x68>)
8016ad0: f7ff ff89 bl 80169e6 <LL_C1_IPCC_IsActiveFlag_CHx>
8016ad4: 4603 mov r3, r0
8016ad6: 2b00 cmp r3, #0
8016ad8: d108 bne.n 8016aec <HW_IPCC_Tx_Handler+0x44>
8016ada: 4b0d ldr r3, [pc, #52] @ (8016b10 <HW_IPCC_Tx_Handler+0x68>)
8016adc: 685b ldr r3, [r3, #4]
8016ade: f403 2300 and.w r3, r3, #524288 @ 0x80000
8016ae2: 2b00 cmp r3, #0
8016ae4: d102 bne.n 8016aec <HW_IPCC_Tx_Handler+0x44>
{
HW_IPCC_MM_FreeBufHandler();
8016ae6: f000 f8f5 bl 8016cd4 <HW_IPCC_MM_FreeBufHandler>
8016aea: e00e b.n 8016b0a <HW_IPCC_Tx_Handler+0x62>
}
else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
8016aec: 2120 movs r1, #32
8016aee: 4808 ldr r0, [pc, #32] @ (8016b10 <HW_IPCC_Tx_Handler+0x68>)
8016af0: f7ff ff79 bl 80169e6 <LL_C1_IPCC_IsActiveFlag_CHx>
8016af4: 4603 mov r3, r0
8016af6: 2b00 cmp r3, #0
8016af8: d108 bne.n 8016b0c <HW_IPCC_Tx_Handler+0x64>
8016afa: 4b05 ldr r3, [pc, #20] @ (8016b10 <HW_IPCC_Tx_Handler+0x68>)
8016afc: 685b ldr r3, [r3, #4]
8016afe: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8016b02: 2b00 cmp r3, #0
8016b04: d102 bne.n 8016b0c <HW_IPCC_Tx_Handler+0x64>
{
HW_IPCC_BLE_AclDataEvtHandler();
8016b06: f000 f83b bl 8016b80 <HW_IPCC_BLE_AclDataEvtHandler>
}
return;
8016b0a: bf00 nop
8016b0c: bf00 nop
}
8016b0e: bd80 pop {r7, pc}
8016b10: 58000c00 .word 0x58000c00
08016b14 <HW_IPCC_Enable>:
/******************************************************************************
* GENERAL
******************************************************************************/
void HW_IPCC_Enable( void )
{
8016b14: b580 push {r7, lr}
8016b16: af00 add r7, sp, #0
/**
* Such as IPCC IP available to the CPU2, it is required to keep the IPCC clock running
* when FUS is running on CPU2 and CPU1 enters deep sleep mode
*/
LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC);
8016b18: f44f 1080 mov.w r0, #1048576 @ 0x100000
8016b1c: f7ff fed3 bl 80168c6 <LL_C2_AHB3_GRP1_EnableClock>
/**
* When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
*/
LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 );
8016b20: f44f 7000 mov.w r0, #512 @ 0x200
8016b24: f7ff fea4 bl 8016870 <LL_EXTI_EnableRisingTrig_32_63>
/* It is required to have at least a system clock cycle before a SEV after LL_EXTI_EnableRisingTrig_32_63() */
LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 );
8016b28: f44f 7000 mov.w r0, #512 @ 0x200
8016b2c: f7ff fe8c bl 8016848 <LL_C2_EXTI_EnableEvent_32_63>
* When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware.
* This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect.
* When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect
* So, by default, the application shall both set the event flag and set the C2BOOT bit.
*/
__SEV( ); /* Set the internal event flag and send an event to the CPU2 */
8016b30: bf40 sev
__WFE( ); /* Clear the internal event flag */
8016b32: bf20 wfe
LL_PWR_EnableBootC2( );
8016b34: f7ff fe78 bl 8016828 <LL_PWR_EnableBootC2>
return;
8016b38: bf00 nop
}
8016b3a: bd80 pop {r7, pc}
08016b3c <HW_IPCC_Init>:
void HW_IPCC_Init( void )
{
8016b3c: b580 push {r7, lr}
8016b3e: af00 add r7, sp, #0
LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
8016b40: f44f 1080 mov.w r0, #1048576 @ 0x100000
8016b44: f7ff fea6 bl 8016894 <LL_AHB3_GRP1_EnableClock>
LL_C1_IPCC_EnableIT_RXO( IPCC );
8016b48: 4806 ldr r0, [pc, #24] @ (8016b64 <HW_IPCC_Init+0x28>)
8016b4a: f7ff fee8 bl 801691e <LL_C1_IPCC_EnableIT_RXO>
LL_C1_IPCC_EnableIT_TXF( IPCC );
8016b4e: 4805 ldr r0, [pc, #20] @ (8016b64 <HW_IPCC_Init+0x28>)
8016b50: f7ff fed5 bl 80168fe <LL_C1_IPCC_EnableIT_TXF>
HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
8016b54: 202c movs r0, #44 @ 0x2c
8016b56: f7ee fd4f bl 80055f8 <HAL_NVIC_EnableIRQ>
HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
8016b5a: 202d movs r0, #45 @ 0x2d
8016b5c: f7ee fd4c bl 80055f8 <HAL_NVIC_EnableIRQ>
return;
8016b60: bf00 nop
}
8016b62: bd80 pop {r7, pc}
8016b64: 58000c00 .word 0x58000c00
08016b68 <HW_IPCC_BLE_EvtHandler>:
return;
}
static void HW_IPCC_BLE_EvtHandler( void )
{
8016b68: b580 push {r7, lr}
8016b6a: af00 add r7, sp, #0
HW_IPCC_BLE_RxEvtNot();
8016b6c: f7fa fe02 bl 8011774 <HW_IPCC_BLE_RxEvtNot>
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
8016b70: 2101 movs r1, #1
8016b72: 4802 ldr r0, [pc, #8] @ (8016b7c <HW_IPCC_BLE_EvtHandler+0x14>)
8016b74: f7ff ff1a bl 80169ac <LL_C1_IPCC_ClearFlag_CHx>
return;
8016b78: bf00 nop
}
8016b7a: bd80 pop {r7, pc}
8016b7c: 58000c00 .word 0x58000c00
08016b80 <HW_IPCC_BLE_AclDataEvtHandler>:
return;
}
static void HW_IPCC_BLE_AclDataEvtHandler( void )
{
8016b80: b580 push {r7, lr}
8016b82: b084 sub sp, #16
8016b84: af00 add r7, sp, #0
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8016b86: f3ef 8310 mrs r3, PRIMASK
8016b8a: 607b str r3, [r7, #4]
return(result);
8016b8c: 687b ldr r3, [r7, #4]
UTILS_ENTER_CRITICAL_SECTION();
8016b8e: 60fb str r3, [r7, #12]
__ASM volatile ("cpsid i" : : : "memory");
8016b90: b672 cpsid i
}
8016b92: bf00 nop
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
8016b94: 2120 movs r1, #32
8016b96: 4807 ldr r0, [pc, #28] @ (8016bb4 <HW_IPCC_BLE_AclDataEvtHandler+0x34>)
8016b98: f7ff fee4 bl 8016964 <LL_C1_IPCC_DisableTransmitChannel>
8016b9c: 68fb ldr r3, [r7, #12]
8016b9e: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8016ba0: 68bb ldr r3, [r7, #8]
8016ba2: f383 8810 msr PRIMASK, r3
}
8016ba6: bf00 nop
UTILS_EXIT_CRITICAL_SECTION();
HW_IPCC_BLE_AclDataAckNot();
8016ba8: f7fa fe14 bl 80117d4 <HW_IPCC_BLE_AclDataAckNot>
return;
8016bac: bf00 nop
}
8016bae: 3710 adds r7, #16
8016bb0: 46bd mov sp, r7
8016bb2: bd80 pop {r7, pc}
8016bb4: 58000c00 .word 0x58000c00
08016bb8 <HW_IPCC_SYS_Init>:
/******************************************************************************
* SYSTEM
******************************************************************************/
void HW_IPCC_SYS_Init( void )
{
8016bb8: b580 push {r7, lr}
8016bba: b084 sub sp, #16
8016bbc: af00 add r7, sp, #0
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8016bbe: f3ef 8310 mrs r3, PRIMASK
8016bc2: 607b str r3, [r7, #4]
return(result);
8016bc4: 687b ldr r3, [r7, #4]
UTILS_ENTER_CRITICAL_SECTION();
8016bc6: 60fb str r3, [r7, #12]
__ASM volatile ("cpsid i" : : : "memory");
8016bc8: b672 cpsid i
}
8016bca: bf00 nop
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
8016bcc: 2102 movs r1, #2
8016bce: 4806 ldr r0, [pc, #24] @ (8016be8 <HW_IPCC_SYS_Init+0x30>)
8016bd0: f7ff feda bl 8016988 <LL_C1_IPCC_EnableReceiveChannel>
8016bd4: 68fb ldr r3, [r7, #12]
8016bd6: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8016bd8: 68bb ldr r3, [r7, #8]
8016bda: f383 8810 msr PRIMASK, r3
}
8016bde: bf00 nop
UTILS_EXIT_CRITICAL_SECTION();
return;
8016be0: bf00 nop
}
8016be2: 3710 adds r7, #16
8016be4: 46bd mov sp, r7
8016be6: bd80 pop {r7, pc}
8016be8: 58000c00 .word 0x58000c00
08016bec <HW_IPCC_SYS_SendCmd>:
void HW_IPCC_SYS_SendCmd( void )
{
8016bec: b580 push {r7, lr}
8016bee: b084 sub sp, #16
8016bf0: af00 add r7, sp, #0
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
8016bf2: 2102 movs r1, #2
8016bf4: 480b ldr r0, [pc, #44] @ (8016c24 <HW_IPCC_SYS_SendCmd+0x38>)
8016bf6: f7ff fee7 bl 80169c8 <LL_C1_IPCC_SetFlag_CHx>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8016bfa: f3ef 8310 mrs r3, PRIMASK
8016bfe: 607b str r3, [r7, #4]
return(result);
8016c00: 687b ldr r3, [r7, #4]
UTILS_ENTER_CRITICAL_SECTION();
8016c02: 60fb str r3, [r7, #12]
__ASM volatile ("cpsid i" : : : "memory");
8016c04: b672 cpsid i
}
8016c06: bf00 nop
LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
8016c08: 2102 movs r1, #2
8016c0a: 4806 ldr r0, [pc, #24] @ (8016c24 <HW_IPCC_SYS_SendCmd+0x38>)
8016c0c: f7ff fe97 bl 801693e <LL_C1_IPCC_EnableTransmitChannel>
8016c10: 68fb ldr r3, [r7, #12]
8016c12: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8016c14: 68bb ldr r3, [r7, #8]
8016c16: f383 8810 msr PRIMASK, r3
}
8016c1a: bf00 nop
UTILS_EXIT_CRITICAL_SECTION();
return;
8016c1c: bf00 nop
}
8016c1e: 3710 adds r7, #16
8016c20: 46bd mov sp, r7
8016c22: bd80 pop {r7, pc}
8016c24: 58000c00 .word 0x58000c00
08016c28 <HW_IPCC_SYS_CmdEvtHandler>:
static void HW_IPCC_SYS_CmdEvtHandler( void )
{
8016c28: b580 push {r7, lr}
8016c2a: b084 sub sp, #16
8016c2c: af00 add r7, sp, #0
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8016c2e: f3ef 8310 mrs r3, PRIMASK
8016c32: 607b str r3, [r7, #4]
return(result);
8016c34: 687b ldr r3, [r7, #4]
UTILS_ENTER_CRITICAL_SECTION();
8016c36: 60fb str r3, [r7, #12]
__ASM volatile ("cpsid i" : : : "memory");
8016c38: b672 cpsid i
}
8016c3a: bf00 nop
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
8016c3c: 2102 movs r1, #2
8016c3e: 4807 ldr r0, [pc, #28] @ (8016c5c <HW_IPCC_SYS_CmdEvtHandler+0x34>)
8016c40: f7ff fe90 bl 8016964 <LL_C1_IPCC_DisableTransmitChannel>
8016c44: 68fb ldr r3, [r7, #12]
8016c46: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8016c48: 68bb ldr r3, [r7, #8]
8016c4a: f383 8810 msr PRIMASK, r3
}
8016c4e: bf00 nop
UTILS_EXIT_CRITICAL_SECTION();
HW_IPCC_SYS_CmdEvtNot();
8016c50: f7fa fe14 bl 801187c <HW_IPCC_SYS_CmdEvtNot>
return;
8016c54: bf00 nop
}
8016c56: 3710 adds r7, #16
8016c58: 46bd mov sp, r7
8016c5a: bd80 pop {r7, pc}
8016c5c: 58000c00 .word 0x58000c00
08016c60 <HW_IPCC_SYS_EvtHandler>:
static void HW_IPCC_SYS_EvtHandler( void )
{
8016c60: b580 push {r7, lr}
8016c62: af00 add r7, sp, #0
HW_IPCC_SYS_EvtNot();
8016c64: f7fa fe20 bl 80118a8 <HW_IPCC_SYS_EvtNot>
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
8016c68: 2102 movs r1, #2
8016c6a: 4802 ldr r0, [pc, #8] @ (8016c74 <HW_IPCC_SYS_EvtHandler+0x14>)
8016c6c: f7ff fe9e bl 80169ac <LL_C1_IPCC_ClearFlag_CHx>
return;
8016c70: bf00 nop
}
8016c72: bd80 pop {r7, pc}
8016c74: 58000c00 .word 0x58000c00
08016c78 <HW_IPCC_MM_SendFreeBuf>:
/******************************************************************************
* MEMORY MANAGER
******************************************************************************/
void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
{
8016c78: b580 push {r7, lr}
8016c7a: b086 sub sp, #24
8016c7c: af00 add r7, sp, #0
8016c7e: 6078 str r0, [r7, #4]
if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
8016c80: 2108 movs r1, #8
8016c82: 4812 ldr r0, [pc, #72] @ (8016ccc <HW_IPCC_MM_SendFreeBuf+0x54>)
8016c84: f7ff feaf bl 80169e6 <LL_C1_IPCC_IsActiveFlag_CHx>
8016c88: 4603 mov r3, r0
8016c8a: 2b00 cmp r3, #0
8016c8c: d013 beq.n 8016cb6 <HW_IPCC_MM_SendFreeBuf+0x3e>
{
FreeBufCb = cb;
8016c8e: 4a10 ldr r2, [pc, #64] @ (8016cd0 <HW_IPCC_MM_SendFreeBuf+0x58>)
8016c90: 687b ldr r3, [r7, #4]
8016c92: 6013 str r3, [r2, #0]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8016c94: f3ef 8310 mrs r3, PRIMASK
8016c98: 60fb str r3, [r7, #12]
return(result);
8016c9a: 68fb ldr r3, [r7, #12]
UTILS_ENTER_CRITICAL_SECTION();
8016c9c: 617b str r3, [r7, #20]
__ASM volatile ("cpsid i" : : : "memory");
8016c9e: b672 cpsid i
}
8016ca0: bf00 nop
LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
8016ca2: 2108 movs r1, #8
8016ca4: 4809 ldr r0, [pc, #36] @ (8016ccc <HW_IPCC_MM_SendFreeBuf+0x54>)
8016ca6: f7ff fe4a bl 801693e <LL_C1_IPCC_EnableTransmitChannel>
8016caa: 697b ldr r3, [r7, #20]
8016cac: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8016cae: 693b ldr r3, [r7, #16]
8016cb0: f383 8810 msr PRIMASK, r3
}
8016cb4: e005 b.n 8016cc2 <HW_IPCC_MM_SendFreeBuf+0x4a>
UTILS_EXIT_CRITICAL_SECTION();
}
else
{
cb();
8016cb6: 687b ldr r3, [r7, #4]
8016cb8: 4798 blx r3
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
8016cba: 2108 movs r1, #8
8016cbc: 4803 ldr r0, [pc, #12] @ (8016ccc <HW_IPCC_MM_SendFreeBuf+0x54>)
8016cbe: f7ff fe83 bl 80169c8 <LL_C1_IPCC_SetFlag_CHx>
}
return;
8016cc2: bf00 nop
}
8016cc4: 3718 adds r7, #24
8016cc6: 46bd mov sp, r7
8016cc8: bd80 pop {r7, pc}
8016cca: bf00 nop
8016ccc: 58000c00 .word 0x58000c00
8016cd0: 20012118 .word 0x20012118
08016cd4 <HW_IPCC_MM_FreeBufHandler>:
static void HW_IPCC_MM_FreeBufHandler( void )
{
8016cd4: b580 push {r7, lr}
8016cd6: b084 sub sp, #16
8016cd8: af00 add r7, sp, #0
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8016cda: f3ef 8310 mrs r3, PRIMASK
8016cde: 607b str r3, [r7, #4]
return(result);
8016ce0: 687b ldr r3, [r7, #4]
UTILS_ENTER_CRITICAL_SECTION();
8016ce2: 60fb str r3, [r7, #12]
__ASM volatile ("cpsid i" : : : "memory");
8016ce4: b672 cpsid i
}
8016ce6: bf00 nop
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
8016ce8: 2108 movs r1, #8
8016cea: 480a ldr r0, [pc, #40] @ (8016d14 <HW_IPCC_MM_FreeBufHandler+0x40>)
8016cec: f7ff fe3a bl 8016964 <LL_C1_IPCC_DisableTransmitChannel>
8016cf0: 68fb ldr r3, [r7, #12]
8016cf2: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8016cf4: 68bb ldr r3, [r7, #8]
8016cf6: f383 8810 msr PRIMASK, r3
}
8016cfa: bf00 nop
UTILS_EXIT_CRITICAL_SECTION();
FreeBufCb();
8016cfc: 4b06 ldr r3, [pc, #24] @ (8016d18 <HW_IPCC_MM_FreeBufHandler+0x44>)
8016cfe: 681b ldr r3, [r3, #0]
8016d00: 4798 blx r3
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
8016d02: 2108 movs r1, #8
8016d04: 4803 ldr r0, [pc, #12] @ (8016d14 <HW_IPCC_MM_FreeBufHandler+0x40>)
8016d06: f7ff fe5f bl 80169c8 <LL_C1_IPCC_SetFlag_CHx>
return;
8016d0a: bf00 nop
}
8016d0c: 3710 adds r7, #16
8016d0e: 46bd mov sp, r7
8016d10: bd80 pop {r7, pc}
8016d12: bf00 nop
8016d14: 58000c00 .word 0x58000c00
8016d18: 20012118 .word 0x20012118
08016d1c <HW_IPCC_TRACES_Init>:
/******************************************************************************
* TRACES
******************************************************************************/
void HW_IPCC_TRACES_Init( void )
{
8016d1c: b580 push {r7, lr}
8016d1e: b084 sub sp, #16
8016d20: af00 add r7, sp, #0
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8016d22: f3ef 8310 mrs r3, PRIMASK
8016d26: 607b str r3, [r7, #4]
return(result);
8016d28: 687b ldr r3, [r7, #4]
UTILS_ENTER_CRITICAL_SECTION();
8016d2a: 60fb str r3, [r7, #12]
__ASM volatile ("cpsid i" : : : "memory");
8016d2c: b672 cpsid i
}
8016d2e: bf00 nop
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
8016d30: 2108 movs r1, #8
8016d32: 4806 ldr r0, [pc, #24] @ (8016d4c <HW_IPCC_TRACES_Init+0x30>)
8016d34: f7ff fe28 bl 8016988 <LL_C1_IPCC_EnableReceiveChannel>
8016d38: 68fb ldr r3, [r7, #12]
8016d3a: 60bb str r3, [r7, #8]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8016d3c: 68bb ldr r3, [r7, #8]
8016d3e: f383 8810 msr PRIMASK, r3
}
8016d42: bf00 nop
UTILS_EXIT_CRITICAL_SECTION();
return;
8016d44: bf00 nop
}
8016d46: 3710 adds r7, #16
8016d48: 46bd mov sp, r7
8016d4a: bd80 pop {r7, pc}
8016d4c: 58000c00 .word 0x58000c00
08016d50 <HW_IPCC_TRACES_EvtHandler>:
static void HW_IPCC_TRACES_EvtHandler( void )
{
8016d50: b580 push {r7, lr}
8016d52: af00 add r7, sp, #0
HW_IPCC_TRACES_EvtNot();
8016d54: f7fa fe50 bl 80119f8 <HW_IPCC_TRACES_EvtNot>
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
8016d58: 2108 movs r1, #8
8016d5a: 4802 ldr r0, [pc, #8] @ (8016d64 <HW_IPCC_TRACES_EvtHandler+0x14>)
8016d5c: f7ff fe26 bl 80169ac <LL_C1_IPCC_ClearFlag_CHx>
return;
8016d60: bf00 nop
}
8016d62: bd80 pop {r7, pc}
8016d64: 58000c00 .word 0x58000c00
08016d68 <MX_USB_Device_Init>:
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void MX_USB_Device_Init(void)
{
8016d68: b580 push {r7, lr}
8016d6a: af00 add r7, sp, #0
/* USER CODE BEGIN USB_Device_Init_PreTreatment */
/* USER CODE END USB_Device_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &CDC_Desc, DEVICE_FS) != USBD_OK) {
8016d6c: 2200 movs r2, #0
8016d6e: 4912 ldr r1, [pc, #72] @ (8016db8 <MX_USB_Device_Init+0x50>)
8016d70: 4812 ldr r0, [pc, #72] @ (8016dbc <MX_USB_Device_Init+0x54>)
8016d72: f7f8 fff5 bl 800fd60 <USBD_Init>
8016d76: 4603 mov r3, r0
8016d78: 2b00 cmp r3, #0
8016d7a: d001 beq.n 8016d80 <MX_USB_Device_Init+0x18>
Error_Handler();
8016d7c: f7ed fac8 bl 8004310 <Error_Handler>
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) {
8016d80: 490f ldr r1, [pc, #60] @ (8016dc0 <MX_USB_Device_Init+0x58>)
8016d82: 480e ldr r0, [pc, #56] @ (8016dbc <MX_USB_Device_Init+0x54>)
8016d84: f7f9 f81c bl 800fdc0 <USBD_RegisterClass>
8016d88: 4603 mov r3, r0
8016d8a: 2b00 cmp r3, #0
8016d8c: d001 beq.n 8016d92 <MX_USB_Device_Init+0x2a>
Error_Handler();
8016d8e: f7ed fabf bl 8004310 <Error_Handler>
}
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) {
8016d92: 490c ldr r1, [pc, #48] @ (8016dc4 <MX_USB_Device_Init+0x5c>)
8016d94: 4809 ldr r0, [pc, #36] @ (8016dbc <MX_USB_Device_Init+0x54>)
8016d96: f7f8 ff13 bl 800fbc0 <USBD_CDC_RegisterInterface>
8016d9a: 4603 mov r3, r0
8016d9c: 2b00 cmp r3, #0
8016d9e: d001 beq.n 8016da4 <MX_USB_Device_Init+0x3c>
Error_Handler();
8016da0: f7ed fab6 bl 8004310 <Error_Handler>
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK) {
8016da4: 4805 ldr r0, [pc, #20] @ (8016dbc <MX_USB_Device_Init+0x54>)
8016da6: f7f9 f841 bl 800fe2c <USBD_Start>
8016daa: 4603 mov r3, r0
8016dac: 2b00 cmp r3, #0
8016dae: d001 beq.n 8016db4 <MX_USB_Device_Init+0x4c>
Error_Handler();
8016db0: f7ed faae bl 8004310 <Error_Handler>
}
/* USER CODE BEGIN USB_Device_Init_PostTreatment */
/* USER CODE END USB_Device_Init_PostTreatment */
}
8016db4: bf00 nop
8016db6: bd80 pop {r7, pc}
8016db8: 200000bc .word 0x200000bc
8016dbc: 2001211c .word 0x2001211c
8016dc0: 20000024 .word 0x20000024
8016dc4: 200000a8 .word 0x200000a8
08016dc8 <CDC_Init_FS>:
/**
* @brief Initializes the CDC media low layer over the FS USB IP
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Init_FS(void)
{
8016dc8: b580 push {r7, lr}
8016dca: af00 add r7, sp, #0
/* USER CODE BEGIN 3 */
/* Set Application Buffers */
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
8016dcc: 2200 movs r2, #0
8016dce: 4905 ldr r1, [pc, #20] @ (8016de4 <CDC_Init_FS+0x1c>)
8016dd0: 4805 ldr r0, [pc, #20] @ (8016de8 <CDC_Init_FS+0x20>)
8016dd2: f7f8 ff0f bl 800fbf4 <USBD_CDC_SetTxBuffer>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
8016dd6: 4905 ldr r1, [pc, #20] @ (8016dec <CDC_Init_FS+0x24>)
8016dd8: 4803 ldr r0, [pc, #12] @ (8016de8 <CDC_Init_FS+0x20>)
8016dda: f7f8 ff2d bl 800fc38 <USBD_CDC_SetRxBuffer>
return (USBD_OK);
8016dde: 2300 movs r3, #0
/* USER CODE END 3 */
}
8016de0: 4618 mov r0, r3
8016de2: bd80 pop {r7, pc}
8016de4: 20012bf8 .word 0x20012bf8
8016de8: 2001211c .word 0x2001211c
8016dec: 200123f8 .word 0x200123f8
08016df0 <CDC_DeInit_FS>:
/**
* @brief DeInitializes the CDC media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_DeInit_FS(void)
{
8016df0: b480 push {r7}
8016df2: af00 add r7, sp, #0
/* USER CODE BEGIN 4 */
return (USBD_OK);
8016df4: 2300 movs r3, #0
/* USER CODE END 4 */
}
8016df6: 4618 mov r0, r3
8016df8: 46bd mov sp, r7
8016dfa: f85d 7b04 ldr.w r7, [sp], #4
8016dfe: 4770 bx lr
08016e00 <CDC_Control_FS>:
* @param pbuf: Buffer containing command data (request parameters)
* @param length: Number of data to be sent (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
{
8016e00: b480 push {r7}
8016e02: b083 sub sp, #12
8016e04: af00 add r7, sp, #0
8016e06: 4603 mov r3, r0
8016e08: 6039 str r1, [r7, #0]
8016e0a: 71fb strb r3, [r7, #7]
8016e0c: 4613 mov r3, r2
8016e0e: 80bb strh r3, [r7, #4]
/* USER CODE BEGIN 5 */
switch(cmd)
8016e10: 79fb ldrb r3, [r7, #7]
8016e12: 2b23 cmp r3, #35 @ 0x23
8016e14: d84a bhi.n 8016eac <CDC_Control_FS+0xac>
8016e16: a201 add r2, pc, #4 @ (adr r2, 8016e1c <CDC_Control_FS+0x1c>)
8016e18: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8016e1c: 08016ead .word 0x08016ead
8016e20: 08016ead .word 0x08016ead
8016e24: 08016ead .word 0x08016ead
8016e28: 08016ead .word 0x08016ead
8016e2c: 08016ead .word 0x08016ead
8016e30: 08016ead .word 0x08016ead
8016e34: 08016ead .word 0x08016ead
8016e38: 08016ead .word 0x08016ead
8016e3c: 08016ead .word 0x08016ead
8016e40: 08016ead .word 0x08016ead
8016e44: 08016ead .word 0x08016ead
8016e48: 08016ead .word 0x08016ead
8016e4c: 08016ead .word 0x08016ead
8016e50: 08016ead .word 0x08016ead
8016e54: 08016ead .word 0x08016ead
8016e58: 08016ead .word 0x08016ead
8016e5c: 08016ead .word 0x08016ead
8016e60: 08016ead .word 0x08016ead
8016e64: 08016ead .word 0x08016ead
8016e68: 08016ead .word 0x08016ead
8016e6c: 08016ead .word 0x08016ead
8016e70: 08016ead .word 0x08016ead
8016e74: 08016ead .word 0x08016ead
8016e78: 08016ead .word 0x08016ead
8016e7c: 08016ead .word 0x08016ead
8016e80: 08016ead .word 0x08016ead
8016e84: 08016ead .word 0x08016ead
8016e88: 08016ead .word 0x08016ead
8016e8c: 08016ead .word 0x08016ead
8016e90: 08016ead .word 0x08016ead
8016e94: 08016ead .word 0x08016ead
8016e98: 08016ead .word 0x08016ead
8016e9c: 08016ead .word 0x08016ead
8016ea0: 08016ead .word 0x08016ead
8016ea4: 08016ead .word 0x08016ead
8016ea8: 08016ead .word 0x08016ead
case CDC_SEND_BREAK:
break;
default:
break;
8016eac: bf00 nop
}
return (USBD_OK);
8016eae: 2300 movs r3, #0
/* USER CODE END 5 */
}
8016eb0: 4618 mov r0, r3
8016eb2: 370c adds r7, #12
8016eb4: 46bd mov sp, r7
8016eb6: f85d 7b04 ldr.w r7, [sp], #4
8016eba: 4770 bx lr
08016ebc <CDC_Receive_FS>:
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
{
8016ebc: b580 push {r7, lr}
8016ebe: b082 sub sp, #8
8016ec0: af00 add r7, sp, #0
8016ec2: 6078 str r0, [r7, #4]
8016ec4: 6039 str r1, [r7, #0]
/* USER CODE BEGIN 6 */
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
8016ec6: 6879 ldr r1, [r7, #4]
8016ec8: 4805 ldr r0, [pc, #20] @ (8016ee0 <CDC_Receive_FS+0x24>)
8016eca: f7f8 feb5 bl 800fc38 <USBD_CDC_SetRxBuffer>
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
8016ece: 4804 ldr r0, [pc, #16] @ (8016ee0 <CDC_Receive_FS+0x24>)
8016ed0: f7f8 ff10 bl 800fcf4 <USBD_CDC_ReceivePacket>
return (USBD_OK);
8016ed4: 2300 movs r3, #0
/* USER CODE END 6 */
}
8016ed6: 4618 mov r0, r3
8016ed8: 3708 adds r7, #8
8016eda: 46bd mov sp, r7
8016edc: bd80 pop {r7, pc}
8016ede: bf00 nop
8016ee0: 2001211c .word 0x2001211c
08016ee4 <CDC_Transmit_FS>:
* @param Buf: Buffer of data to be sent
* @param Len: Number of data to be sent (in bytes)
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
*/
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
{
8016ee4: b580 push {r7, lr}
8016ee6: b084 sub sp, #16
8016ee8: af00 add r7, sp, #0
8016eea: 6078 str r0, [r7, #4]
8016eec: 460b mov r3, r1
8016eee: 807b strh r3, [r7, #2]
uint8_t result = USBD_OK;
8016ef0: 2300 movs r3, #0
8016ef2: 73fb strb r3, [r7, #15]
/* USER CODE BEGIN 7 */
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
8016ef4: 4b0d ldr r3, [pc, #52] @ (8016f2c <CDC_Transmit_FS+0x48>)
8016ef6: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc
8016efa: 60bb str r3, [r7, #8]
if (hcdc->TxState != 0){
8016efc: 68bb ldr r3, [r7, #8]
8016efe: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214
8016f02: 2b00 cmp r3, #0
8016f04: d001 beq.n 8016f0a <CDC_Transmit_FS+0x26>
return USBD_BUSY;
8016f06: 2301 movs r3, #1
8016f08: e00b b.n 8016f22 <CDC_Transmit_FS+0x3e>
}
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
8016f0a: 887b ldrh r3, [r7, #2]
8016f0c: 461a mov r2, r3
8016f0e: 6879 ldr r1, [r7, #4]
8016f10: 4806 ldr r0, [pc, #24] @ (8016f2c <CDC_Transmit_FS+0x48>)
8016f12: f7f8 fe6f bl 800fbf4 <USBD_CDC_SetTxBuffer>
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
8016f16: 4805 ldr r0, [pc, #20] @ (8016f2c <CDC_Transmit_FS+0x48>)
8016f18: f7f8 feac bl 800fc74 <USBD_CDC_TransmitPacket>
8016f1c: 4603 mov r3, r0
8016f1e: 73fb strb r3, [r7, #15]
/* USER CODE END 7 */
return result;
8016f20: 7bfb ldrb r3, [r7, #15]
}
8016f22: 4618 mov r0, r3
8016f24: 3710 adds r7, #16
8016f26: 46bd mov sp, r7
8016f28: bd80 pop {r7, pc}
8016f2a: bf00 nop
8016f2c: 2001211c .word 0x2001211c
08016f30 <CDC_TransmitCplt_FS>:
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum)
{
8016f30: b480 push {r7}
8016f32: b087 sub sp, #28
8016f34: af00 add r7, sp, #0
8016f36: 60f8 str r0, [r7, #12]
8016f38: 60b9 str r1, [r7, #8]
8016f3a: 4613 mov r3, r2
8016f3c: 71fb strb r3, [r7, #7]
uint8_t result = USBD_OK;
8016f3e: 2300 movs r3, #0
8016f40: 75fb strb r3, [r7, #23]
/* USER CODE BEGIN 13 */
UNUSED(Buf);
UNUSED(Len);
UNUSED(epnum);
/* USER CODE END 13 */
return result;
8016f42: f997 3017 ldrsb.w r3, [r7, #23]
}
8016f46: 4618 mov r0, r3
8016f48: 371c adds r7, #28
8016f4a: 46bd mov sp, r7
8016f4c: f85d 7b04 ldr.w r7, [sp], #4
8016f50: 4770 bx lr
...
08016f54 <USBD_CDC_DeviceDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_CDC_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8016f54: b480 push {r7}
8016f56: b083 sub sp, #12
8016f58: af00 add r7, sp, #0
8016f5a: 4603 mov r3, r0
8016f5c: 6039 str r1, [r7, #0]
8016f5e: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_CDC_DeviceDesc);
8016f60: 683b ldr r3, [r7, #0]
8016f62: 2212 movs r2, #18
8016f64: 801a strh r2, [r3, #0]
return USBD_CDC_DeviceDesc;
8016f66: 4b03 ldr r3, [pc, #12] @ (8016f74 <USBD_CDC_DeviceDescriptor+0x20>)
}
8016f68: 4618 mov r0, r3
8016f6a: 370c adds r7, #12
8016f6c: 46bd mov sp, r7
8016f6e: f85d 7b04 ldr.w r7, [sp], #4
8016f72: 4770 bx lr
8016f74: 200000dc .word 0x200000dc
08016f78 <USBD_CDC_LangIDStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_CDC_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8016f78: b480 push {r7}
8016f7a: b083 sub sp, #12
8016f7c: af00 add r7, sp, #0
8016f7e: 4603 mov r3, r0
8016f80: 6039 str r1, [r7, #0]
8016f82: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
8016f84: 683b ldr r3, [r7, #0]
8016f86: 2204 movs r2, #4
8016f88: 801a strh r2, [r3, #0]
return USBD_LangIDDesc;
8016f8a: 4b03 ldr r3, [pc, #12] @ (8016f98 <USBD_CDC_LangIDStrDescriptor+0x20>)
}
8016f8c: 4618 mov r0, r3
8016f8e: 370c adds r7, #12
8016f90: 46bd mov sp, r7
8016f92: f85d 7b04 ldr.w r7, [sp], #4
8016f96: 4770 bx lr
8016f98: 200000f0 .word 0x200000f0
08016f9c <USBD_CDC_ProductStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_CDC_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8016f9c: b580 push {r7, lr}
8016f9e: b082 sub sp, #8
8016fa0: af00 add r7, sp, #0
8016fa2: 4603 mov r3, r0
8016fa4: 6039 str r1, [r7, #0]
8016fa6: 71fb strb r3, [r7, #7]
if(speed == 0)
8016fa8: 79fb ldrb r3, [r7, #7]
8016faa: 2b00 cmp r3, #0
8016fac: d105 bne.n 8016fba <USBD_CDC_ProductStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
8016fae: 683a ldr r2, [r7, #0]
8016fb0: 4907 ldr r1, [pc, #28] @ (8016fd0 <USBD_CDC_ProductStrDescriptor+0x34>)
8016fb2: 4808 ldr r0, [pc, #32] @ (8016fd4 <USBD_CDC_ProductStrDescriptor+0x38>)
8016fb4: f7fa f898 bl 80110e8 <USBD_GetString>
8016fb8: e004 b.n 8016fc4 <USBD_CDC_ProductStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length);
8016fba: 683a ldr r2, [r7, #0]
8016fbc: 4904 ldr r1, [pc, #16] @ (8016fd0 <USBD_CDC_ProductStrDescriptor+0x34>)
8016fbe: 4805 ldr r0, [pc, #20] @ (8016fd4 <USBD_CDC_ProductStrDescriptor+0x38>)
8016fc0: f7fa f892 bl 80110e8 <USBD_GetString>
}
return USBD_StrDesc;
8016fc4: 4b02 ldr r3, [pc, #8] @ (8016fd0 <USBD_CDC_ProductStrDescriptor+0x34>)
}
8016fc6: 4618 mov r0, r3
8016fc8: 3708 adds r7, #8
8016fca: 46bd mov sp, r7
8016fcc: bd80 pop {r7, pc}
8016fce: bf00 nop
8016fd0: 200133f8 .word 0x200133f8
8016fd4: 0801c4e0 .word 0x0801c4e0
08016fd8 <USBD_CDC_ManufacturerStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_CDC_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8016fd8: b580 push {r7, lr}
8016fda: b082 sub sp, #8
8016fdc: af00 add r7, sp, #0
8016fde: 4603 mov r3, r0
8016fe0: 6039 str r1, [r7, #0]
8016fe2: 71fb strb r3, [r7, #7]
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
8016fe4: 683a ldr r2, [r7, #0]
8016fe6: 4904 ldr r1, [pc, #16] @ (8016ff8 <USBD_CDC_ManufacturerStrDescriptor+0x20>)
8016fe8: 4804 ldr r0, [pc, #16] @ (8016ffc <USBD_CDC_ManufacturerStrDescriptor+0x24>)
8016fea: f7fa f87d bl 80110e8 <USBD_GetString>
return USBD_StrDesc;
8016fee: 4b02 ldr r3, [pc, #8] @ (8016ff8 <USBD_CDC_ManufacturerStrDescriptor+0x20>)
}
8016ff0: 4618 mov r0, r3
8016ff2: 3708 adds r7, #8
8016ff4: 46bd mov sp, r7
8016ff6: bd80 pop {r7, pc}
8016ff8: 200133f8 .word 0x200133f8
8016ffc: 0801c4f8 .word 0x0801c4f8
08017000 <USBD_CDC_SerialStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_CDC_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8017000: b580 push {r7, lr}
8017002: b082 sub sp, #8
8017004: af00 add r7, sp, #0
8017006: 4603 mov r3, r0
8017008: 6039 str r1, [r7, #0]
801700a: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
801700c: 683b ldr r3, [r7, #0]
801700e: 221a movs r2, #26
8017010: 801a strh r2, [r3, #0]
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
8017012: f000 f843 bl 801709c <Get_SerialNum>
/* USER CODE BEGIN USBD_CDC_SerialStrDescriptor */
/* USER CODE END USBD_CDC_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
8017016: 4b02 ldr r3, [pc, #8] @ (8017020 <USBD_CDC_SerialStrDescriptor+0x20>)
}
8017018: 4618 mov r0, r3
801701a: 3708 adds r7, #8
801701c: 46bd mov sp, r7
801701e: bd80 pop {r7, pc}
8017020: 200000f4 .word 0x200000f4
08017024 <USBD_CDC_ConfigStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_CDC_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8017024: b580 push {r7, lr}
8017026: b082 sub sp, #8
8017028: af00 add r7, sp, #0
801702a: 4603 mov r3, r0
801702c: 6039 str r1, [r7, #0]
801702e: 71fb strb r3, [r7, #7]
if(speed == USBD_SPEED_HIGH)
8017030: 79fb ldrb r3, [r7, #7]
8017032: 2b00 cmp r3, #0
8017034: d105 bne.n 8017042 <USBD_CDC_ConfigStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
8017036: 683a ldr r2, [r7, #0]
8017038: 4907 ldr r1, [pc, #28] @ (8017058 <USBD_CDC_ConfigStrDescriptor+0x34>)
801703a: 4808 ldr r0, [pc, #32] @ (801705c <USBD_CDC_ConfigStrDescriptor+0x38>)
801703c: f7fa f854 bl 80110e8 <USBD_GetString>
8017040: e004 b.n 801704c <USBD_CDC_ConfigStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length);
8017042: 683a ldr r2, [r7, #0]
8017044: 4904 ldr r1, [pc, #16] @ (8017058 <USBD_CDC_ConfigStrDescriptor+0x34>)
8017046: 4805 ldr r0, [pc, #20] @ (801705c <USBD_CDC_ConfigStrDescriptor+0x38>)
8017048: f7fa f84e bl 80110e8 <USBD_GetString>
}
return USBD_StrDesc;
801704c: 4b02 ldr r3, [pc, #8] @ (8017058 <USBD_CDC_ConfigStrDescriptor+0x34>)
}
801704e: 4618 mov r0, r3
8017050: 3708 adds r7, #8
8017052: 46bd mov sp, r7
8017054: bd80 pop {r7, pc}
8017056: bf00 nop
8017058: 200133f8 .word 0x200133f8
801705c: 0801c50c .word 0x0801c50c
08017060 <USBD_CDC_InterfaceStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_CDC_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8017060: b580 push {r7, lr}
8017062: b082 sub sp, #8
8017064: af00 add r7, sp, #0
8017066: 4603 mov r3, r0
8017068: 6039 str r1, [r7, #0]
801706a: 71fb strb r3, [r7, #7]
if(speed == 0)
801706c: 79fb ldrb r3, [r7, #7]
801706e: 2b00 cmp r3, #0
8017070: d105 bne.n 801707e <USBD_CDC_InterfaceStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
8017072: 683a ldr r2, [r7, #0]
8017074: 4907 ldr r1, [pc, #28] @ (8017094 <USBD_CDC_InterfaceStrDescriptor+0x34>)
8017076: 4808 ldr r0, [pc, #32] @ (8017098 <USBD_CDC_InterfaceStrDescriptor+0x38>)
8017078: f7fa f836 bl 80110e8 <USBD_GetString>
801707c: e004 b.n 8017088 <USBD_CDC_InterfaceStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length);
801707e: 683a ldr r2, [r7, #0]
8017080: 4904 ldr r1, [pc, #16] @ (8017094 <USBD_CDC_InterfaceStrDescriptor+0x34>)
8017082: 4805 ldr r0, [pc, #20] @ (8017098 <USBD_CDC_InterfaceStrDescriptor+0x38>)
8017084: f7fa f830 bl 80110e8 <USBD_GetString>
}
return USBD_StrDesc;
8017088: 4b02 ldr r3, [pc, #8] @ (8017094 <USBD_CDC_InterfaceStrDescriptor+0x34>)
}
801708a: 4618 mov r0, r3
801708c: 3708 adds r7, #8
801708e: 46bd mov sp, r7
8017090: bd80 pop {r7, pc}
8017092: bf00 nop
8017094: 200133f8 .word 0x200133f8
8017098: 0801c518 .word 0x0801c518
0801709c <Get_SerialNum>:
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
801709c: b580 push {r7, lr}
801709e: b084 sub sp, #16
80170a0: af00 add r7, sp, #0
uint32_t deviceserial0;
uint32_t deviceserial1;
uint32_t deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
80170a2: 4b0f ldr r3, [pc, #60] @ (80170e0 <Get_SerialNum+0x44>)
80170a4: 681b ldr r3, [r3, #0]
80170a6: 60fb str r3, [r7, #12]
deviceserial1 = *(uint32_t *) DEVICE_ID2;
80170a8: 4b0e ldr r3, [pc, #56] @ (80170e4 <Get_SerialNum+0x48>)
80170aa: 681b ldr r3, [r3, #0]
80170ac: 60bb str r3, [r7, #8]
deviceserial2 = *(uint32_t *) DEVICE_ID3;
80170ae: 4b0e ldr r3, [pc, #56] @ (80170e8 <Get_SerialNum+0x4c>)
80170b0: 681b ldr r3, [r3, #0]
80170b2: 607b str r3, [r7, #4]
deviceserial0 += deviceserial2;
80170b4: 68fa ldr r2, [r7, #12]
80170b6: 687b ldr r3, [r7, #4]
80170b8: 4413 add r3, r2
80170ba: 60fb str r3, [r7, #12]
if (deviceserial0 != 0)
80170bc: 68fb ldr r3, [r7, #12]
80170be: 2b00 cmp r3, #0
80170c0: d009 beq.n 80170d6 <Get_SerialNum+0x3a>
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
80170c2: 2208 movs r2, #8
80170c4: 4909 ldr r1, [pc, #36] @ (80170ec <Get_SerialNum+0x50>)
80170c6: 68f8 ldr r0, [r7, #12]
80170c8: f000 f814 bl 80170f4 <IntToUnicode>
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
80170cc: 2204 movs r2, #4
80170ce: 4908 ldr r1, [pc, #32] @ (80170f0 <Get_SerialNum+0x54>)
80170d0: 68b8 ldr r0, [r7, #8]
80170d2: f000 f80f bl 80170f4 <IntToUnicode>
}
}
80170d6: bf00 nop
80170d8: 3710 adds r7, #16
80170da: 46bd mov sp, r7
80170dc: bd80 pop {r7, pc}
80170de: bf00 nop
80170e0: 1fff7590 .word 0x1fff7590
80170e4: 1fff7594 .word 0x1fff7594
80170e8: 1fff7598 .word 0x1fff7598
80170ec: 200000f6 .word 0x200000f6
80170f0: 20000106 .word 0x20000106
080170f4 <IntToUnicode>:
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
80170f4: b480 push {r7}
80170f6: b087 sub sp, #28
80170f8: af00 add r7, sp, #0
80170fa: 60f8 str r0, [r7, #12]
80170fc: 60b9 str r1, [r7, #8]
80170fe: 4613 mov r3, r2
8017100: 71fb strb r3, [r7, #7]
uint8_t idx = 0;
8017102: 2300 movs r3, #0
8017104: 75fb strb r3, [r7, #23]
for (idx = 0; idx < len; idx++)
8017106: 2300 movs r3, #0
8017108: 75fb strb r3, [r7, #23]
801710a: e027 b.n 801715c <IntToUnicode+0x68>
{
if (((value >> 28)) < 0xA)
801710c: 68fb ldr r3, [r7, #12]
801710e: 0f1b lsrs r3, r3, #28
8017110: 2b09 cmp r3, #9
8017112: d80b bhi.n 801712c <IntToUnicode+0x38>
{
pbuf[2 * idx] = (value >> 28) + '0';
8017114: 68fb ldr r3, [r7, #12]
8017116: 0f1b lsrs r3, r3, #28
8017118: b2da uxtb r2, r3
801711a: 7dfb ldrb r3, [r7, #23]
801711c: 005b lsls r3, r3, #1
801711e: 4619 mov r1, r3
8017120: 68bb ldr r3, [r7, #8]
8017122: 440b add r3, r1
8017124: 3230 adds r2, #48 @ 0x30
8017126: b2d2 uxtb r2, r2
8017128: 701a strb r2, [r3, #0]
801712a: e00a b.n 8017142 <IntToUnicode+0x4e>
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
801712c: 68fb ldr r3, [r7, #12]
801712e: 0f1b lsrs r3, r3, #28
8017130: b2da uxtb r2, r3
8017132: 7dfb ldrb r3, [r7, #23]
8017134: 005b lsls r3, r3, #1
8017136: 4619 mov r1, r3
8017138: 68bb ldr r3, [r7, #8]
801713a: 440b add r3, r1
801713c: 3237 adds r2, #55 @ 0x37
801713e: b2d2 uxtb r2, r2
8017140: 701a strb r2, [r3, #0]
}
value = value << 4;
8017142: 68fb ldr r3, [r7, #12]
8017144: 011b lsls r3, r3, #4
8017146: 60fb str r3, [r7, #12]
pbuf[2 * idx + 1] = 0;
8017148: 7dfb ldrb r3, [r7, #23]
801714a: 005b lsls r3, r3, #1
801714c: 3301 adds r3, #1
801714e: 68ba ldr r2, [r7, #8]
8017150: 4413 add r3, r2
8017152: 2200 movs r2, #0
8017154: 701a strb r2, [r3, #0]
for (idx = 0; idx < len; idx++)
8017156: 7dfb ldrb r3, [r7, #23]
8017158: 3301 adds r3, #1
801715a: 75fb strb r3, [r7, #23]
801715c: 7dfa ldrb r2, [r7, #23]
801715e: 79fb ldrb r3, [r7, #7]
8017160: 429a cmp r2, r3
8017162: d3d3 bcc.n 801710c <IntToUnicode+0x18>
}
}
8017164: bf00 nop
8017166: bf00 nop
8017168: 371c adds r7, #28
801716a: 46bd mov sp, r7
801716c: f85d 7b04 ldr.w r7, [sp], #4
8017170: 4770 bx lr
08017172 <LL_AHB2_GRP1_EnableClock>:
{
8017172: b480 push {r7}
8017174: b085 sub sp, #20
8017176: af00 add r7, sp, #0
8017178: 6078 str r0, [r7, #4]
SET_BIT(RCC->AHB2ENR, Periphs);
801717a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
801717e: 6cda ldr r2, [r3, #76] @ 0x4c
8017180: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
8017184: 687b ldr r3, [r7, #4]
8017186: 4313 orrs r3, r2
8017188: 64cb str r3, [r1, #76] @ 0x4c
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
801718a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
801718e: 6cda ldr r2, [r3, #76] @ 0x4c
8017190: 687b ldr r3, [r7, #4]
8017192: 4013 ands r3, r2
8017194: 60fb str r3, [r7, #12]
(void)tmpreg;
8017196: 68fb ldr r3, [r7, #12]
}
8017198: bf00 nop
801719a: 3714 adds r7, #20
801719c: 46bd mov sp, r7
801719e: f85d 7b04 ldr.w r7, [sp], #4
80171a2: 4770 bx lr
080171a4 <LL_APB1_GRP1_EnableClock>:
{
80171a4: b480 push {r7}
80171a6: b085 sub sp, #20
80171a8: af00 add r7, sp, #0
80171aa: 6078 str r0, [r7, #4]
SET_BIT(RCC->APB1ENR1, Periphs);
80171ac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80171b0: 6d9a ldr r2, [r3, #88] @ 0x58
80171b2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000
80171b6: 687b ldr r3, [r7, #4]
80171b8: 4313 orrs r3, r2
80171ba: 658b str r3, [r1, #88] @ 0x58
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
80171bc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000
80171c0: 6d9a ldr r2, [r3, #88] @ 0x58
80171c2: 687b ldr r3, [r7, #4]
80171c4: 4013 ands r3, r2
80171c6: 60fb str r3, [r7, #12]
(void)tmpreg;
80171c8: 68fb ldr r3, [r7, #12]
}
80171ca: bf00 nop
80171cc: 3714 adds r7, #20
80171ce: 46bd mov sp, r7
80171d0: f85d 7b04 ldr.w r7, [sp], #4
80171d4: 4770 bx lr
...
080171d8 <HAL_PCD_MspInit>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
#else
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
80171d8: b580 push {r7, lr}
80171da: b09c sub sp, #112 @ 0x70
80171dc: af00 add r7, sp, #0
80171de: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80171e0: f107 035c add.w r3, r7, #92 @ 0x5c
80171e4: 2200 movs r2, #0
80171e6: 601a str r2, [r3, #0]
80171e8: 605a str r2, [r3, #4]
80171ea: 609a str r2, [r3, #8]
80171ec: 60da str r2, [r3, #12]
80171ee: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
80171f0: f107 030c add.w r3, r7, #12
80171f4: 2250 movs r2, #80 @ 0x50
80171f6: 2100 movs r1, #0
80171f8: 4618 mov r0, r3
80171fa: f001 fbeb bl 80189d4 <memset>
if(pcdHandle->Instance==USB)
80171fe: 687b ldr r3, [r7, #4]
8017200: 681b ldr r3, [r3, #0]
8017202: 4a23 ldr r2, [pc, #140] @ (8017290 <HAL_PCD_MspInit+0xb8>)
8017204: 4293 cmp r3, r2
8017206: d13e bne.n 8017286 <HAL_PCD_MspInit+0xae>
/* USER CODE END USB_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
8017208: f44f 7380 mov.w r3, #256 @ 0x100
801720c: 60fb str r3, [r7, #12]
PeriphClkInitStruct.PLLSAI1.PLLN = 24;
801720e: 2318 movs r3, #24
8017210: 613b str r3, [r7, #16]
PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2;
8017212: f44f 3300 mov.w r3, #131072 @ 0x20000
8017216: 617b str r3, [r7, #20]
PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2;
8017218: f04f 7300 mov.w r3, #33554432 @ 0x2000000
801721c: 61bb str r3, [r7, #24]
PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2;
801721e: f04f 5300 mov.w r3, #536870912 @ 0x20000000
8017222: 61fb str r3, [r7, #28]
PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK;
8017224: f04f 7380 mov.w r3, #16777216 @ 0x1000000
8017228: 623b str r3, [r7, #32]
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
801722a: f04f 6380 mov.w r3, #67108864 @ 0x4000000
801722e: 643b str r3, [r7, #64] @ 0x40
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8017230: f107 030c add.w r3, r7, #12
8017234: 4618 mov r0, r3
8017236: f7f3 fe95 bl 800af64 <HAL_RCCEx_PeriphCLKConfig>
801723a: 4603 mov r3, r0
801723c: 2b00 cmp r3, #0
801723e: d001 beq.n 8017244 <HAL_PCD_MspInit+0x6c>
{
Error_Handler();
8017240: f7ed f866 bl 8004310 <Error_Handler>
}
__HAL_RCC_GPIOA_CLK_ENABLE();
8017244: 2001 movs r0, #1
8017246: f7ff ff94 bl 8017172 <LL_AHB2_GRP1_EnableClock>
/**USB GPIO Configuration
PA11 ------> USB_DM
PA12 ------> USB_DP
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
801724a: f44f 53c0 mov.w r3, #6144 @ 0x1800
801724e: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8017250: 2302 movs r3, #2
8017252: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Pull = GPIO_NOPULL;
8017254: 2300 movs r3, #0
8017256: 667b str r3, [r7, #100] @ 0x64
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8017258: 2300 movs r3, #0
801725a: 66bb str r3, [r7, #104] @ 0x68
GPIO_InitStruct.Alternate = GPIO_AF10_USB;
801725c: 230a movs r3, #10
801725e: 66fb str r3, [r7, #108] @ 0x6c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8017260: f107 035c add.w r3, r7, #92 @ 0x5c
8017264: 4619 mov r1, r3
8017266: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
801726a: f7ee fcdf bl 8005c2c <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
801726e: f04f 6080 mov.w r0, #67108864 @ 0x4000000
8017272: f7ff ff97 bl 80171a4 <LL_APB1_GRP1_EnableClock>
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(USB_LP_IRQn, 5, 0);
8017276: 2200 movs r2, #0
8017278: 2105 movs r1, #5
801727a: 2014 movs r0, #20
801727c: f7ee f9a2 bl 80055c4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_IRQn);
8017280: 2014 movs r0, #20
8017282: f7ee f9b9 bl 80055f8 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USB_MspInit 1 */
/* USER CODE END USB_MspInit 1 */
}
}
8017286: bf00 nop
8017288: 3770 adds r7, #112 @ 0x70
801728a: 46bd mov sp, r7
801728c: bd80 pop {r7, pc}
801728e: bf00 nop
8017290: 40006800 .word 0x40006800
08017294 <HAL_PCD_SetupStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8017294: b580 push {r7, lr}
8017296: b082 sub sp, #8
8017298: af00 add r7, sp, #0
801729a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */
/* USER CODE END HAL_PCD_SetupStageCallback_PreTreatment */
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
801729c: 687b ldr r3, [r7, #4]
801729e: f8d3 22d8 ldr.w r2, [r3, #728] @ 0x2d8
80172a2: 687b ldr r3, [r7, #4]
80172a4: f503 7326 add.w r3, r3, #664 @ 0x298
80172a8: 4619 mov r1, r3
80172aa: 4610 mov r0, r2
80172ac: f7f8 fe0b bl 800fec6 <USBD_LL_SetupStage>
/* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */
/* USER CODE END HAL_PCD_SetupStageCallback_PostTreatment */
}
80172b0: bf00 nop
80172b2: 3708 adds r7, #8
80172b4: 46bd mov sp, r7
80172b6: bd80 pop {r7, pc}
080172b8 <HAL_PCD_DataOutStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
80172b8: b580 push {r7, lr}
80172ba: b082 sub sp, #8
80172bc: af00 add r7, sp, #0
80172be: 6078 str r0, [r7, #4]
80172c0: 460b mov r3, r1
80172c2: 70fb strb r3, [r7, #3]
/* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */
/* USER CODE END HAL_PCD_DataOutStageCallback_PreTreatment */
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
80172c4: 687b ldr r3, [r7, #4]
80172c6: f8d3 02d8 ldr.w r0, [r3, #728] @ 0x2d8
80172ca: 78fa ldrb r2, [r7, #3]
80172cc: 6879 ldr r1, [r7, #4]
80172ce: 4613 mov r3, r2
80172d0: 009b lsls r3, r3, #2
80172d2: 4413 add r3, r2
80172d4: 00db lsls r3, r3, #3
80172d6: 440b add r3, r1
80172d8: f503 73b2 add.w r3, r3, #356 @ 0x164
80172dc: 681a ldr r2, [r3, #0]
80172de: 78fb ldrb r3, [r7, #3]
80172e0: 4619 mov r1, r3
80172e2: f7f8 fe45 bl 800ff70 <USBD_LL_DataOutStage>
/* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */
/* USER CODE END HAL_PCD_DataOutStageCallback_PostTreatment */
}
80172e6: bf00 nop
80172e8: 3708 adds r7, #8
80172ea: 46bd mov sp, r7
80172ec: bd80 pop {r7, pc}
080172ee <HAL_PCD_DataInStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
80172ee: b580 push {r7, lr}
80172f0: b082 sub sp, #8
80172f2: af00 add r7, sp, #0
80172f4: 6078 str r0, [r7, #4]
80172f6: 460b mov r3, r1
80172f8: 70fb strb r3, [r7, #3]
/* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */
/* USER CODE END HAL_PCD_DataInStageCallback_PreTreatment */
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
80172fa: 687b ldr r3, [r7, #4]
80172fc: f8d3 02d8 ldr.w r0, [r3, #728] @ 0x2d8
8017300: 78fa ldrb r2, [r7, #3]
8017302: 6879 ldr r1, [r7, #4]
8017304: 4613 mov r3, r2
8017306: 009b lsls r3, r3, #2
8017308: 4413 add r3, r2
801730a: 00db lsls r3, r3, #3
801730c: 440b add r3, r1
801730e: 3324 adds r3, #36 @ 0x24
8017310: 681a ldr r2, [r3, #0]
8017312: 78fb ldrb r3, [r7, #3]
8017314: 4619 mov r1, r3
8017316: f7f8 fee7 bl 80100e8 <USBD_LL_DataInStage>
/* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment */
/* USER CODE END HAL_PCD_DataInStageCallback_PostTreatment */
}
801731a: bf00 nop
801731c: 3708 adds r7, #8
801731e: 46bd mov sp, r7
8017320: bd80 pop {r7, pc}
08017322 <HAL_PCD_SOFCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8017322: b580 push {r7, lr}
8017324: b082 sub sp, #8
8017326: af00 add r7, sp, #0
8017328: 6078 str r0, [r7, #4]
/* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */
/* USER CODE END HAL_PCD_SOFCallback_PreTreatment */
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
801732a: 687b ldr r3, [r7, #4]
801732c: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
8017330: 4618 mov r0, r3
8017332: f7f9 f82b bl 801038c <USBD_LL_SOF>
/* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */
/* USER CODE END HAL_PCD_SOFCallback_PostTreatment */
}
8017336: bf00 nop
8017338: 3708 adds r7, #8
801733a: 46bd mov sp, r7
801733c: bd80 pop {r7, pc}
0801733e <HAL_PCD_ResetCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
801733e: b580 push {r7, lr}
8017340: b084 sub sp, #16
8017342: af00 add r7, sp, #0
8017344: 6078 str r0, [r7, #4]
/* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */
/* USER CODE END HAL_PCD_ResetCallback_PreTreatment */
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
8017346: 2301 movs r3, #1
8017348: 73fb strb r3, [r7, #15]
if ( hpcd->Init.speed != PCD_SPEED_FULL)
801734a: 687b ldr r3, [r7, #4]
801734c: 795b ldrb r3, [r3, #5]
801734e: 2b02 cmp r3, #2
8017350: d001 beq.n 8017356 <HAL_PCD_ResetCallback+0x18>
{
Error_Handler();
8017352: f7ec ffdd bl 8004310 <Error_Handler>
}
/* Set Speed. */
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
8017356: 687b ldr r3, [r7, #4]
8017358: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
801735c: 7bfa ldrb r2, [r7, #15]
801735e: 4611 mov r1, r2
8017360: 4618 mov r0, r3
8017362: f7f8 ffcf bl 8010304 <USBD_LL_SetSpeed>
/* Reset Device. */
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
8017366: 687b ldr r3, [r7, #4]
8017368: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
801736c: 4618 mov r0, r3
801736e: f7f8 ff76 bl 801025e <USBD_LL_Reset>
/* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */
/* USER CODE END HAL_PCD_ResetCallback_PostTreatment */
}
8017372: bf00 nop
8017374: 3710 adds r7, #16
8017376: 46bd mov sp, r7
8017378: bd80 pop {r7, pc}
...
0801737c <HAL_PCD_SuspendCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
801737c: b580 push {r7, lr}
801737e: b082 sub sp, #8
8017380: af00 add r7, sp, #0
8017382: 6078 str r0, [r7, #4]
/* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */
/* USER CODE END HAL_PCD_SuspendCallback_PreTreatment */
/* Inform USB library that core enters in suspend Mode. */
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
8017384: 687b ldr r3, [r7, #4]
8017386: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
801738a: 4618 mov r0, r3
801738c: f7f8 ffca bl 8010324 <USBD_LL_Suspend>
/* Enter in STOP mode. */
/* USER CODE BEGIN 2 */
if (hpcd->Init.low_power_enable)
8017390: 687b ldr r3, [r7, #4]
8017392: 7a5b ldrb r3, [r3, #9]
8017394: 2b00 cmp r3, #0
8017396: d005 beq.n 80173a4 <HAL_PCD_SuspendCallback+0x28>
{
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
8017398: 4b04 ldr r3, [pc, #16] @ (80173ac <HAL_PCD_SuspendCallback+0x30>)
801739a: 691b ldr r3, [r3, #16]
801739c: 4a03 ldr r2, [pc, #12] @ (80173ac <HAL_PCD_SuspendCallback+0x30>)
801739e: f043 0306 orr.w r3, r3, #6
80173a2: 6113 str r3, [r2, #16]
}
/* USER CODE END 2 */
/* USER CODE BEGIN HAL_PCD_SuspendCallback_PostTreatment */
/* USER CODE END HAL_PCD_SuspendCallback_PostTreatment */
}
80173a4: bf00 nop
80173a6: 3708 adds r7, #8
80173a8: 46bd mov sp, r7
80173aa: bd80 pop {r7, pc}
80173ac: e000ed00 .word 0xe000ed00
080173b0 <HAL_PCD_ResumeCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
80173b0: b580 push {r7, lr}
80173b2: b082 sub sp, #8
80173b4: af00 add r7, sp, #0
80173b6: 6078 str r0, [r7, #4]
/* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */
/* USER CODE END HAL_PCD_ResumeCallback_PreTreatment */
/* USER CODE BEGIN 3 */
if (hpcd->Init.low_power_enable)
80173b8: 687b ldr r3, [r7, #4]
80173ba: 7a5b ldrb r3, [r3, #9]
80173bc: 2b00 cmp r3, #0
80173be: d007 beq.n 80173d0 <HAL_PCD_ResumeCallback+0x20>
{
/* Reset SLEEPDEEP bit of Cortex System Control Register. */
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
80173c0: 4b08 ldr r3, [pc, #32] @ (80173e4 <HAL_PCD_ResumeCallback+0x34>)
80173c2: 691b ldr r3, [r3, #16]
80173c4: 4a07 ldr r2, [pc, #28] @ (80173e4 <HAL_PCD_ResumeCallback+0x34>)
80173c6: f023 0306 bic.w r3, r3, #6
80173ca: 6113 str r3, [r2, #16]
SystemClockConfig_Resume();
80173cc: f000 f9fa bl 80177c4 <SystemClockConfig_Resume>
}
/* USER CODE END 3 */
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
80173d0: 687b ldr r3, [r7, #4]
80173d2: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
80173d6: 4618 mov r0, r3
80173d8: f7f8 ffc0 bl 801035c <USBD_LL_Resume>
/* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */
/* USER CODE END HAL_PCD_ResumeCallback_PostTreatment */
}
80173dc: bf00 nop
80173de: 3708 adds r7, #8
80173e0: 46bd mov sp, r7
80173e2: bd80 pop {r7, pc}
80173e4: e000ed00 .word 0xe000ed00
080173e8 <USBD_LL_Init>:
* @brief Initializes the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
{
80173e8: b580 push {r7, lr}
80173ea: b082 sub sp, #8
80173ec: af00 add r7, sp, #0
80173ee: 6078 str r0, [r7, #4]
/* Init USB Ip. */
hpcd_USB_FS.pData = pdev;
80173f0: 4a2c ldr r2, [pc, #176] @ (80174a4 <USBD_LL_Init+0xbc>)
80173f2: 687b ldr r3, [r7, #4]
80173f4: f8c2 32d8 str.w r3, [r2, #728] @ 0x2d8
/* Link the driver to the stack. */
pdev->pData = &hpcd_USB_FS;
80173f8: 687b ldr r3, [r7, #4]
80173fa: 4a2a ldr r2, [pc, #168] @ (80174a4 <USBD_LL_Init+0xbc>)
80173fc: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8
/* Enable USB power on Pwrctrl CR2 register. */
HAL_PWREx_EnableVddUSB();
8017400: f7f2 fa42 bl 8009888 <HAL_PWREx_EnableVddUSB>
hpcd_USB_FS.Instance = USB;
8017404: 4b27 ldr r3, [pc, #156] @ (80174a4 <USBD_LL_Init+0xbc>)
8017406: 4a28 ldr r2, [pc, #160] @ (80174a8 <USBD_LL_Init+0xc0>)
8017408: 601a str r2, [r3, #0]
hpcd_USB_FS.Init.dev_endpoints = 8;
801740a: 4b26 ldr r3, [pc, #152] @ (80174a4 <USBD_LL_Init+0xbc>)
801740c: 2208 movs r2, #8
801740e: 711a strb r2, [r3, #4]
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
8017410: 4b24 ldr r3, [pc, #144] @ (80174a4 <USBD_LL_Init+0xbc>)
8017412: 2202 movs r2, #2
8017414: 715a strb r2, [r3, #5]
hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
8017416: 4b23 ldr r3, [pc, #140] @ (80174a4 <USBD_LL_Init+0xbc>)
8017418: 2202 movs r2, #2
801741a: 71da strb r2, [r3, #7]
hpcd_USB_FS.Init.Sof_enable = DISABLE;
801741c: 4b21 ldr r3, [pc, #132] @ (80174a4 <USBD_LL_Init+0xbc>)
801741e: 2200 movs r2, #0
8017420: 721a strb r2, [r3, #8]
hpcd_USB_FS.Init.low_power_enable = DISABLE;
8017422: 4b20 ldr r3, [pc, #128] @ (80174a4 <USBD_LL_Init+0xbc>)
8017424: 2200 movs r2, #0
8017426: 725a strb r2, [r3, #9]
hpcd_USB_FS.Init.lpm_enable = DISABLE;
8017428: 4b1e ldr r3, [pc, #120] @ (80174a4 <USBD_LL_Init+0xbc>)
801742a: 2200 movs r2, #0
801742c: 729a strb r2, [r3, #10]
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
801742e: 4b1d ldr r3, [pc, #116] @ (80174a4 <USBD_LL_Init+0xbc>)
8017430: 2200 movs r2, #0
8017432: 72da strb r2, [r3, #11]
/* register Msp Callbacks (before the Init) */
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPINIT_CB_ID, PCD_MspInit);
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPDEINIT_CB_ID, PCD_MspDeInit);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
8017434: 481b ldr r0, [pc, #108] @ (80174a4 <USBD_LL_Init+0xbc>)
8017436: f7f0 fcc7 bl 8007dc8 <HAL_PCD_Init>
801743a: 4603 mov r3, r0
801743c: 2b00 cmp r3, #0
801743e: d001 beq.n 8017444 <USBD_LL_Init+0x5c>
{
Error_Handler( );
8017440: f7ec ff66 bl 8004310 <Error_Handler>
/* USER CODE BEGIN RegisterCallBackSecondPart */
/* USER CODE END RegisterCallBackSecondPart */
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* USER CODE BEGIN EndPoint_Configuration */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
8017444: 687b ldr r3, [r7, #4]
8017446: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
801744a: 2318 movs r3, #24
801744c: 2200 movs r2, #0
801744e: 2100 movs r1, #0
8017450: f7f2 f98f bl 8009772 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
8017454: 687b ldr r3, [r7, #4]
8017456: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
801745a: 2358 movs r3, #88 @ 0x58
801745c: 2200 movs r2, #0
801745e: 2180 movs r1, #128 @ 0x80
8017460: f7f2 f987 bl 8009772 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration */
/* USER CODE BEGIN EndPoint_Configuration_CDC */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
8017464: 687b ldr r3, [r7, #4]
8017466: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
801746a: 23c0 movs r3, #192 @ 0xc0
801746c: 2200 movs r2, #0
801746e: 2181 movs r1, #129 @ 0x81
8017470: f7f2 f97f bl 8009772 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
8017474: 687b ldr r3, [r7, #4]
8017476: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
801747a: f44f 7388 mov.w r3, #272 @ 0x110
801747e: 2200 movs r2, #0
8017480: 2101 movs r1, #1
8017482: f7f2 f976 bl 8009772 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
8017486: 687b ldr r3, [r7, #4]
8017488: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
801748c: f44f 7380 mov.w r3, #256 @ 0x100
8017490: 2200 movs r2, #0
8017492: 2182 movs r1, #130 @ 0x82
8017494: f7f2 f96d bl 8009772 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration_CDC */
return USBD_OK;
8017498: 2300 movs r3, #0
}
801749a: 4618 mov r0, r3
801749c: 3708 adds r7, #8
801749e: 46bd mov sp, r7
80174a0: bd80 pop {r7, pc}
80174a2: bf00 nop
80174a4: 200135f8 .word 0x200135f8
80174a8: 40006800 .word 0x40006800
080174ac <USBD_LL_Start>:
* @brief Starts the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
80174ac: b580 push {r7, lr}
80174ae: b084 sub sp, #16
80174b0: af00 add r7, sp, #0
80174b2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
80174b4: 2300 movs r3, #0
80174b6: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
80174b8: 2300 movs r3, #0
80174ba: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_Start(pdev->pData);
80174bc: 687b ldr r3, [r7, #4]
80174be: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
80174c2: 4618 mov r0, r3
80174c4: f7f0 fd4e bl 8007f64 <HAL_PCD_Start>
80174c8: 4603 mov r3, r0
80174ca: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
80174cc: 7bfb ldrb r3, [r7, #15]
80174ce: 4618 mov r0, r3
80174d0: f000 f97e bl 80177d0 <USBD_Get_USB_Status>
80174d4: 4603 mov r3, r0
80174d6: 73bb strb r3, [r7, #14]
return usb_status;
80174d8: 7bbb ldrb r3, [r7, #14]
}
80174da: 4618 mov r0, r3
80174dc: 3710 adds r7, #16
80174de: 46bd mov sp, r7
80174e0: bd80 pop {r7, pc}
080174e2 <USBD_LL_OpenEP>:
* @param ep_type: Endpoint type
* @param ep_mps: Endpoint max packet size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
{
80174e2: b580 push {r7, lr}
80174e4: b084 sub sp, #16
80174e6: af00 add r7, sp, #0
80174e8: 6078 str r0, [r7, #4]
80174ea: 4608 mov r0, r1
80174ec: 4611 mov r1, r2
80174ee: 461a mov r2, r3
80174f0: 4603 mov r3, r0
80174f2: 70fb strb r3, [r7, #3]
80174f4: 460b mov r3, r1
80174f6: 70bb strb r3, [r7, #2]
80174f8: 4613 mov r3, r2
80174fa: 803b strh r3, [r7, #0]
HAL_StatusTypeDef hal_status = HAL_OK;
80174fc: 2300 movs r3, #0
80174fe: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8017500: 2300 movs r3, #0
8017502: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
8017504: 687b ldr r3, [r7, #4]
8017506: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
801750a: 78bb ldrb r3, [r7, #2]
801750c: 883a ldrh r2, [r7, #0]
801750e: 78f9 ldrb r1, [r7, #3]
8017510: f7f0 fe95 bl 800823e <HAL_PCD_EP_Open>
8017514: 4603 mov r3, r0
8017516: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8017518: 7bfb ldrb r3, [r7, #15]
801751a: 4618 mov r0, r3
801751c: f000 f958 bl 80177d0 <USBD_Get_USB_Status>
8017520: 4603 mov r3, r0
8017522: 73bb strb r3, [r7, #14]
return usb_status;
8017524: 7bbb ldrb r3, [r7, #14]
}
8017526: 4618 mov r0, r3
8017528: 3710 adds r7, #16
801752a: 46bd mov sp, r7
801752c: bd80 pop {r7, pc}
0801752e <USBD_LL_CloseEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
801752e: b580 push {r7, lr}
8017530: b084 sub sp, #16
8017532: af00 add r7, sp, #0
8017534: 6078 str r0, [r7, #4]
8017536: 460b mov r3, r1
8017538: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
801753a: 2300 movs r3, #0
801753c: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
801753e: 2300 movs r3, #0
8017540: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
8017542: 687b ldr r3, [r7, #4]
8017544: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8017548: 78fa ldrb r2, [r7, #3]
801754a: 4611 mov r1, r2
801754c: 4618 mov r0, r3
801754e: f7f0 fed5 bl 80082fc <HAL_PCD_EP_Close>
8017552: 4603 mov r3, r0
8017554: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8017556: 7bfb ldrb r3, [r7, #15]
8017558: 4618 mov r0, r3
801755a: f000 f939 bl 80177d0 <USBD_Get_USB_Status>
801755e: 4603 mov r3, r0
8017560: 73bb strb r3, [r7, #14]
return usb_status;
8017562: 7bbb ldrb r3, [r7, #14]
}
8017564: 4618 mov r0, r3
8017566: 3710 adds r7, #16
8017568: 46bd mov sp, r7
801756a: bd80 pop {r7, pc}
0801756c <USBD_LL_StallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
801756c: b580 push {r7, lr}
801756e: b084 sub sp, #16
8017570: af00 add r7, sp, #0
8017572: 6078 str r0, [r7, #4]
8017574: 460b mov r3, r1
8017576: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8017578: 2300 movs r3, #0
801757a: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
801757c: 2300 movs r3, #0
801757e: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
8017580: 687b ldr r3, [r7, #4]
8017582: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8017586: 78fa ldrb r2, [r7, #3]
8017588: 4611 mov r1, r2
801758a: 4618 mov r0, r3
801758c: f7f0 ff7e bl 800848c <HAL_PCD_EP_SetStall>
8017590: 4603 mov r3, r0
8017592: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8017594: 7bfb ldrb r3, [r7, #15]
8017596: 4618 mov r0, r3
8017598: f000 f91a bl 80177d0 <USBD_Get_USB_Status>
801759c: 4603 mov r3, r0
801759e: 73bb strb r3, [r7, #14]
return usb_status;
80175a0: 7bbb ldrb r3, [r7, #14]
}
80175a2: 4618 mov r0, r3
80175a4: 3710 adds r7, #16
80175a6: 46bd mov sp, r7
80175a8: bd80 pop {r7, pc}
080175aa <USBD_LL_ClearStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
80175aa: b580 push {r7, lr}
80175ac: b084 sub sp, #16
80175ae: af00 add r7, sp, #0
80175b0: 6078 str r0, [r7, #4]
80175b2: 460b mov r3, r1
80175b4: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
80175b6: 2300 movs r3, #0
80175b8: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
80175ba: 2300 movs r3, #0
80175bc: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
80175be: 687b ldr r3, [r7, #4]
80175c0: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
80175c4: 78fa ldrb r2, [r7, #3]
80175c6: 4611 mov r1, r2
80175c8: 4618 mov r0, r3
80175ca: f7f0 ffb1 bl 8008530 <HAL_PCD_EP_ClrStall>
80175ce: 4603 mov r3, r0
80175d0: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
80175d2: 7bfb ldrb r3, [r7, #15]
80175d4: 4618 mov r0, r3
80175d6: f000 f8fb bl 80177d0 <USBD_Get_USB_Status>
80175da: 4603 mov r3, r0
80175dc: 73bb strb r3, [r7, #14]
return usb_status;
80175de: 7bbb ldrb r3, [r7, #14]
}
80175e0: 4618 mov r0, r3
80175e2: 3710 adds r7, #16
80175e4: 46bd mov sp, r7
80175e6: bd80 pop {r7, pc}
080175e8 <USBD_LL_IsStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Stall (1: Yes, 0: No)
*/
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
80175e8: b480 push {r7}
80175ea: b085 sub sp, #20
80175ec: af00 add r7, sp, #0
80175ee: 6078 str r0, [r7, #4]
80175f0: 460b mov r3, r1
80175f2: 70fb strb r3, [r7, #3]
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
80175f4: 687b ldr r3, [r7, #4]
80175f6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
80175fa: 60fb str r3, [r7, #12]
if((ep_addr & 0x80) == 0x80)
80175fc: f997 3003 ldrsb.w r3, [r7, #3]
8017600: 2b00 cmp r3, #0
8017602: da0b bge.n 801761c <USBD_LL_IsStallEP+0x34>
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
8017604: 78fb ldrb r3, [r7, #3]
8017606: f003 027f and.w r2, r3, #127 @ 0x7f
801760a: 68f9 ldr r1, [r7, #12]
801760c: 4613 mov r3, r2
801760e: 009b lsls r3, r3, #2
8017610: 4413 add r3, r2
8017612: 00db lsls r3, r3, #3
8017614: 440b add r3, r1
8017616: 3312 adds r3, #18
8017618: 781b ldrb r3, [r3, #0]
801761a: e00b b.n 8017634 <USBD_LL_IsStallEP+0x4c>
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
801761c: 78fb ldrb r3, [r7, #3]
801761e: f003 027f and.w r2, r3, #127 @ 0x7f
8017622: 68f9 ldr r1, [r7, #12]
8017624: 4613 mov r3, r2
8017626: 009b lsls r3, r3, #2
8017628: 4413 add r3, r2
801762a: 00db lsls r3, r3, #3
801762c: 440b add r3, r1
801762e: f503 73a9 add.w r3, r3, #338 @ 0x152
8017632: 781b ldrb r3, [r3, #0]
}
}
8017634: 4618 mov r0, r3
8017636: 3714 adds r7, #20
8017638: 46bd mov sp, r7
801763a: f85d 7b04 ldr.w r7, [sp], #4
801763e: 4770 bx lr
08017640 <USBD_LL_SetUSBAddress>:
* @param pdev: Device handle
* @param dev_addr: Device address
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
{
8017640: b580 push {r7, lr}
8017642: b084 sub sp, #16
8017644: af00 add r7, sp, #0
8017646: 6078 str r0, [r7, #4]
8017648: 460b mov r3, r1
801764a: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
801764c: 2300 movs r3, #0
801764e: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8017650: 2300 movs r3, #0
8017652: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
8017654: 687b ldr r3, [r7, #4]
8017656: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
801765a: 78fa ldrb r2, [r7, #3]
801765c: 4611 mov r1, r2
801765e: 4618 mov r0, r3
8017660: f7f0 fdc9 bl 80081f6 <HAL_PCD_SetAddress>
8017664: 4603 mov r3, r0
8017666: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8017668: 7bfb ldrb r3, [r7, #15]
801766a: 4618 mov r0, r3
801766c: f000 f8b0 bl 80177d0 <USBD_Get_USB_Status>
8017670: 4603 mov r3, r0
8017672: 73bb strb r3, [r7, #14]
return usb_status;
8017674: 7bbb ldrb r3, [r7, #14]
}
8017676: 4618 mov r0, r3
8017678: 3710 adds r7, #16
801767a: 46bd mov sp, r7
801767c: bd80 pop {r7, pc}
0801767e <USBD_LL_Transmit>:
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
{
801767e: b580 push {r7, lr}
8017680: b086 sub sp, #24
8017682: af00 add r7, sp, #0
8017684: 60f8 str r0, [r7, #12]
8017686: 607a str r2, [r7, #4]
8017688: 603b str r3, [r7, #0]
801768a: 460b mov r3, r1
801768c: 72fb strb r3, [r7, #11]
HAL_StatusTypeDef hal_status = HAL_OK;
801768e: 2300 movs r3, #0
8017690: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
8017692: 2300 movs r3, #0
8017694: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
8017696: 68fb ldr r3, [r7, #12]
8017698: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
801769c: 7af9 ldrb r1, [r7, #11]
801769e: 683b ldr r3, [r7, #0]
80176a0: 687a ldr r2, [r7, #4]
80176a2: f7f0 febc bl 800841e <HAL_PCD_EP_Transmit>
80176a6: 4603 mov r3, r0
80176a8: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
80176aa: 7dfb ldrb r3, [r7, #23]
80176ac: 4618 mov r0, r3
80176ae: f000 f88f bl 80177d0 <USBD_Get_USB_Status>
80176b2: 4603 mov r3, r0
80176b4: 75bb strb r3, [r7, #22]
return usb_status;
80176b6: 7dbb ldrb r3, [r7, #22]
}
80176b8: 4618 mov r0, r3
80176ba: 3718 adds r7, #24
80176bc: 46bd mov sp, r7
80176be: bd80 pop {r7, pc}
080176c0 <USBD_LL_PrepareReceive>:
* @param pbuf: Pointer to data to be received
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
{
80176c0: b580 push {r7, lr}
80176c2: b086 sub sp, #24
80176c4: af00 add r7, sp, #0
80176c6: 60f8 str r0, [r7, #12]
80176c8: 607a str r2, [r7, #4]
80176ca: 603b str r3, [r7, #0]
80176cc: 460b mov r3, r1
80176ce: 72fb strb r3, [r7, #11]
HAL_StatusTypeDef hal_status = HAL_OK;
80176d0: 2300 movs r3, #0
80176d2: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
80176d4: 2300 movs r3, #0
80176d6: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
80176d8: 68fb ldr r3, [r7, #12]
80176da: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8
80176de: 7af9 ldrb r1, [r7, #11]
80176e0: 683b ldr r3, [r7, #0]
80176e2: 687a ldr r2, [r7, #4]
80176e4: f7f0 fe52 bl 800838c <HAL_PCD_EP_Receive>
80176e8: 4603 mov r3, r0
80176ea: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
80176ec: 7dfb ldrb r3, [r7, #23]
80176ee: 4618 mov r0, r3
80176f0: f000 f86e bl 80177d0 <USBD_Get_USB_Status>
80176f4: 4603 mov r3, r0
80176f6: 75bb strb r3, [r7, #22]
return usb_status;
80176f8: 7dbb ldrb r3, [r7, #22]
}
80176fa: 4618 mov r0, r3
80176fc: 3718 adds r7, #24
80176fe: 46bd mov sp, r7
8017700: bd80 pop {r7, pc}
08017702 <USBD_LL_GetRxDataSize>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Received Data Size
*/
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8017702: b580 push {r7, lr}
8017704: b082 sub sp, #8
8017706: af00 add r7, sp, #0
8017708: 6078 str r0, [r7, #4]
801770a: 460b mov r3, r1
801770c: 70fb strb r3, [r7, #3]
return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
801770e: 687b ldr r3, [r7, #4]
8017710: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8
8017714: 78fa ldrb r2, [r7, #3]
8017716: 4611 mov r1, r2
8017718: 4618 mov r0, r3
801771a: f7f0 fe68 bl 80083ee <HAL_PCD_EP_GetRxCount>
801771e: 4603 mov r3, r0
}
8017720: 4618 mov r0, r3
8017722: 3708 adds r7, #8
8017724: 46bd mov sp, r7
8017726: bd80 pop {r7, pc}
08017728 <HAL_PCDEx_LPM_Callback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
#else
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8017728: b580 push {r7, lr}
801772a: b082 sub sp, #8
801772c: af00 add r7, sp, #0
801772e: 6078 str r0, [r7, #4]
8017730: 460b mov r3, r1
8017732: 70fb strb r3, [r7, #3]
/* USER CODE BEGIN LPM_Callback */
switch (msg)
8017734: 78fb ldrb r3, [r7, #3]
8017736: 2b00 cmp r3, #0
8017738: d002 beq.n 8017740 <HAL_PCDEx_LPM_Callback+0x18>
801773a: 2b01 cmp r3, #1
801773c: d013 beq.n 8017766 <HAL_PCDEx_LPM_Callback+0x3e>
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
}
break;
}
/* USER CODE END LPM_Callback */
}
801773e: e023 b.n 8017788 <HAL_PCDEx_LPM_Callback+0x60>
if (hpcd->Init.low_power_enable)
8017740: 687b ldr r3, [r7, #4]
8017742: 7a5b ldrb r3, [r3, #9]
8017744: 2b00 cmp r3, #0
8017746: d007 beq.n 8017758 <HAL_PCDEx_LPM_Callback+0x30>
SystemClockConfig_Resume();
8017748: f000 f83c bl 80177c4 <SystemClockConfig_Resume>
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
801774c: 4b10 ldr r3, [pc, #64] @ (8017790 <HAL_PCDEx_LPM_Callback+0x68>)
801774e: 691b ldr r3, [r3, #16]
8017750: 4a0f ldr r2, [pc, #60] @ (8017790 <HAL_PCDEx_LPM_Callback+0x68>)
8017752: f023 0306 bic.w r3, r3, #6
8017756: 6113 str r3, [r2, #16]
USBD_LL_Resume(hpcd->pData);
8017758: 687b ldr r3, [r7, #4]
801775a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
801775e: 4618 mov r0, r3
8017760: f7f8 fdfc bl 801035c <USBD_LL_Resume>
break;
8017764: e010 b.n 8017788 <HAL_PCDEx_LPM_Callback+0x60>
USBD_LL_Suspend(hpcd->pData);
8017766: 687b ldr r3, [r7, #4]
8017768: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8
801776c: 4618 mov r0, r3
801776e: f7f8 fdd9 bl 8010324 <USBD_LL_Suspend>
if (hpcd->Init.low_power_enable)
8017772: 687b ldr r3, [r7, #4]
8017774: 7a5b ldrb r3, [r3, #9]
8017776: 2b00 cmp r3, #0
8017778: d005 beq.n 8017786 <HAL_PCDEx_LPM_Callback+0x5e>
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
801777a: 4b05 ldr r3, [pc, #20] @ (8017790 <HAL_PCDEx_LPM_Callback+0x68>)
801777c: 691b ldr r3, [r3, #16]
801777e: 4a04 ldr r2, [pc, #16] @ (8017790 <HAL_PCDEx_LPM_Callback+0x68>)
8017780: f043 0306 orr.w r3, r3, #6
8017784: 6113 str r3, [r2, #16]
break;
8017786: bf00 nop
}
8017788: bf00 nop
801778a: 3708 adds r7, #8
801778c: 46bd mov sp, r7
801778e: bd80 pop {r7, pc}
8017790: e000ed00 .word 0xe000ed00
08017794 <USBD_static_malloc>:
* @brief Static single allocation.
* @param size: Size of allocated memory
* @retval None
*/
void *USBD_static_malloc(uint32_t size)
{
8017794: b480 push {r7}
8017796: b083 sub sp, #12
8017798: af00 add r7, sp, #0
801779a: 6078 str r0, [r7, #4]
UNUSED(size);
static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
return mem;
801779c: 4b03 ldr r3, [pc, #12] @ (80177ac <USBD_static_malloc+0x18>)
}
801779e: 4618 mov r0, r3
80177a0: 370c adds r7, #12
80177a2: 46bd mov sp, r7
80177a4: f85d 7b04 ldr.w r7, [sp], #4
80177a8: 4770 bx lr
80177aa: bf00 nop
80177ac: 200138d4 .word 0x200138d4
080177b0 <USBD_static_free>:
* @brief Dummy memory free
* @param p: Pointer to allocated memory address
* @retval None
*/
void USBD_static_free(void *p)
{
80177b0: b480 push {r7}
80177b2: b083 sub sp, #12
80177b4: af00 add r7, sp, #0
80177b6: 6078 str r0, [r7, #4]
UNUSED(p);
}
80177b8: bf00 nop
80177ba: 370c adds r7, #12
80177bc: 46bd mov sp, r7
80177be: f85d 7b04 ldr.w r7, [sp], #4
80177c2: 4770 bx lr
080177c4 <SystemClockConfig_Resume>:
* @brief Configures system clock after wake-up from USB resume callBack:
* enable HSI, PLL and select PLL as system clock source.
* @retval None
*/
static void SystemClockConfig_Resume(void)
{
80177c4: b580 push {r7, lr}
80177c6: af00 add r7, sp, #0
SystemClock_Config();
80177c8: f7ec f8e2 bl 8003990 <SystemClock_Config>
}
80177cc: bf00 nop
80177ce: bd80 pop {r7, pc}
080177d0 <USBD_Get_USB_Status>:
* @brief Returns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
{
80177d0: b480 push {r7}
80177d2: b085 sub sp, #20
80177d4: af00 add r7, sp, #0
80177d6: 4603 mov r3, r0
80177d8: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef usb_status = USBD_OK;
80177da: 2300 movs r3, #0
80177dc: 73fb strb r3, [r7, #15]
switch (hal_status)
80177de: 79fb ldrb r3, [r7, #7]
80177e0: 2b03 cmp r3, #3
80177e2: d817 bhi.n 8017814 <USBD_Get_USB_Status+0x44>
80177e4: a201 add r2, pc, #4 @ (adr r2, 80177ec <USBD_Get_USB_Status+0x1c>)
80177e6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80177ea: bf00 nop
80177ec: 080177fd .word 0x080177fd
80177f0: 08017803 .word 0x08017803
80177f4: 08017809 .word 0x08017809
80177f8: 0801780f .word 0x0801780f
{
case HAL_OK :
usb_status = USBD_OK;
80177fc: 2300 movs r3, #0
80177fe: 73fb strb r3, [r7, #15]
break;
8017800: e00b b.n 801781a <USBD_Get_USB_Status+0x4a>
case HAL_ERROR :
usb_status = USBD_FAIL;
8017802: 2303 movs r3, #3
8017804: 73fb strb r3, [r7, #15]
break;
8017806: e008 b.n 801781a <USBD_Get_USB_Status+0x4a>
case HAL_BUSY :
usb_status = USBD_BUSY;
8017808: 2301 movs r3, #1
801780a: 73fb strb r3, [r7, #15]
break;
801780c: e005 b.n 801781a <USBD_Get_USB_Status+0x4a>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
801780e: 2303 movs r3, #3
8017810: 73fb strb r3, [r7, #15]
break;
8017812: e002 b.n 801781a <USBD_Get_USB_Status+0x4a>
default :
usb_status = USBD_FAIL;
8017814: 2303 movs r3, #3
8017816: 73fb strb r3, [r7, #15]
break;
8017818: bf00 nop
}
return usb_status;
801781a: 7bfb ldrb r3, [r7, #15]
}
801781c: 4618 mov r0, r3
801781e: 3714 adds r7, #20
8017820: 46bd mov sp, r7
8017822: f85d 7b04 ldr.w r7, [sp], #4
8017826: 4770 bx lr
08017828 <UTIL_LPM_Init>:
/** @addtogroup TINY_LPM_Exported_function
* @{
*/
void UTIL_LPM_Init( void )
{
8017828: b480 push {r7}
801782a: af00 add r7, sp, #0
StopModeDisable = UTIL_LPM_NO_BIT_SET;
801782c: 4b05 ldr r3, [pc, #20] @ (8017844 <UTIL_LPM_Init+0x1c>)
801782e: 2200 movs r2, #0
8017830: 601a str r2, [r3, #0]
OffModeDisable = UTIL_LPM_NO_BIT_SET;
8017832: 4b05 ldr r3, [pc, #20] @ (8017848 <UTIL_LPM_Init+0x20>)
8017834: 2200 movs r2, #0
8017836: 601a str r2, [r3, #0]
UTIL_LPM_INIT_CRITICAL_SECTION( );
}
8017838: bf00 nop
801783a: 46bd mov sp, r7
801783c: f85d 7b04 ldr.w r7, [sp], #4
8017840: 4770 bx lr
8017842: bf00 nop
8017844: 20013af4 .word 0x20013af4
8017848: 20013af8 .word 0x20013af8
0801784c <UTIL_LPM_SetOffMode>:
UTIL_LPM_EXIT_CRITICAL_SECTION( );
}
void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state )
{
801784c: b480 push {r7}
801784e: b087 sub sp, #28
8017850: af00 add r7, sp, #0
8017852: 6078 str r0, [r7, #4]
8017854: 460b mov r3, r1
8017856: 70fb strb r3, [r7, #3]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8017858: f3ef 8310 mrs r3, PRIMASK
801785c: 613b str r3, [r7, #16]
return(result);
801785e: 693b ldr r3, [r7, #16]
UTIL_LPM_ENTER_CRITICAL_SECTION( );
8017860: 617b str r3, [r7, #20]
__ASM volatile ("cpsid i" : : : "memory");
8017862: b672 cpsid i
}
8017864: bf00 nop
switch(state)
8017866: 78fb ldrb r3, [r7, #3]
8017868: 2b00 cmp r3, #0
801786a: d008 beq.n 801787e <UTIL_LPM_SetOffMode+0x32>
801786c: 2b01 cmp r3, #1
801786e: d10e bne.n 801788e <UTIL_LPM_SetOffMode+0x42>
{
case UTIL_LPM_DISABLE:
{
OffModeDisable |= lpm_id_bm;
8017870: 4b0d ldr r3, [pc, #52] @ (80178a8 <UTIL_LPM_SetOffMode+0x5c>)
8017872: 681a ldr r2, [r3, #0]
8017874: 687b ldr r3, [r7, #4]
8017876: 4313 orrs r3, r2
8017878: 4a0b ldr r2, [pc, #44] @ (80178a8 <UTIL_LPM_SetOffMode+0x5c>)
801787a: 6013 str r3, [r2, #0]
break;
801787c: e008 b.n 8017890 <UTIL_LPM_SetOffMode+0x44>
}
case UTIL_LPM_ENABLE:
{
OffModeDisable &= ( ~lpm_id_bm );
801787e: 687b ldr r3, [r7, #4]
8017880: 43da mvns r2, r3
8017882: 4b09 ldr r3, [pc, #36] @ (80178a8 <UTIL_LPM_SetOffMode+0x5c>)
8017884: 681b ldr r3, [r3, #0]
8017886: 4013 ands r3, r2
8017888: 4a07 ldr r2, [pc, #28] @ (80178a8 <UTIL_LPM_SetOffMode+0x5c>)
801788a: 6013 str r3, [r2, #0]
break;
801788c: e000 b.n 8017890 <UTIL_LPM_SetOffMode+0x44>
}
default :
{
break;
801788e: bf00 nop
8017890: 697b ldr r3, [r7, #20]
8017892: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8017894: 68fb ldr r3, [r7, #12]
8017896: f383 8810 msr PRIMASK, r3
}
801789a: bf00 nop
}
}
UTIL_LPM_EXIT_CRITICAL_SECTION( );
}
801789c: bf00 nop
801789e: 371c adds r7, #28
80178a0: 46bd mov sp, r7
80178a2: f85d 7b04 ldr.w r7, [sp], #4
80178a6: 4770 bx lr
80178a8: 20013af8 .word 0x20013af8
080178ac <__cvt>:
80178ac: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
80178b0: ec57 6b10 vmov r6, r7, d0
80178b4: 2f00 cmp r7, #0
80178b6: 460c mov r4, r1
80178b8: 4619 mov r1, r3
80178ba: 463b mov r3, r7
80178bc: bfbb ittet lt
80178be: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000
80178c2: 461f movlt r7, r3
80178c4: 2300 movge r3, #0
80178c6: 232d movlt r3, #45 @ 0x2d
80178c8: 700b strb r3, [r1, #0]
80178ca: 9b0d ldr r3, [sp, #52] @ 0x34
80178cc: f8dd a030 ldr.w sl, [sp, #48] @ 0x30
80178d0: 4691 mov r9, r2
80178d2: f023 0820 bic.w r8, r3, #32
80178d6: bfbc itt lt
80178d8: 4632 movlt r2, r6
80178da: 4616 movlt r6, r2
80178dc: f1b8 0f46 cmp.w r8, #70 @ 0x46
80178e0: d005 beq.n 80178ee <__cvt+0x42>
80178e2: f1b8 0f45 cmp.w r8, #69 @ 0x45
80178e6: d100 bne.n 80178ea <__cvt+0x3e>
80178e8: 3401 adds r4, #1
80178ea: 2102 movs r1, #2
80178ec: e000 b.n 80178f0 <__cvt+0x44>
80178ee: 2103 movs r1, #3
80178f0: ab03 add r3, sp, #12
80178f2: 9301 str r3, [sp, #4]
80178f4: ab02 add r3, sp, #8
80178f6: 9300 str r3, [sp, #0]
80178f8: ec47 6b10 vmov d0, r6, r7
80178fc: 4653 mov r3, sl
80178fe: 4622 mov r2, r4
8017900: f001 f986 bl 8018c10 <_dtoa_r>
8017904: f1b8 0f47 cmp.w r8, #71 @ 0x47
8017908: 4605 mov r5, r0
801790a: d119 bne.n 8017940 <__cvt+0x94>
801790c: f019 0f01 tst.w r9, #1
8017910: d00e beq.n 8017930 <__cvt+0x84>
8017912: eb00 0904 add.w r9, r0, r4
8017916: 2200 movs r2, #0
8017918: 2300 movs r3, #0
801791a: 4630 mov r0, r6
801791c: 4639 mov r1, r7
801791e: f7e9 f8ab bl 8000a78 <__aeabi_dcmpeq>
8017922: b108 cbz r0, 8017928 <__cvt+0x7c>
8017924: f8cd 900c str.w r9, [sp, #12]
8017928: 2230 movs r2, #48 @ 0x30
801792a: 9b03 ldr r3, [sp, #12]
801792c: 454b cmp r3, r9
801792e: d31e bcc.n 801796e <__cvt+0xc2>
8017930: 9b03 ldr r3, [sp, #12]
8017932: 9a0e ldr r2, [sp, #56] @ 0x38
8017934: 1b5b subs r3, r3, r5
8017936: 4628 mov r0, r5
8017938: 6013 str r3, [r2, #0]
801793a: b004 add sp, #16
801793c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8017940: f1b8 0f46 cmp.w r8, #70 @ 0x46
8017944: eb00 0904 add.w r9, r0, r4
8017948: d1e5 bne.n 8017916 <__cvt+0x6a>
801794a: 7803 ldrb r3, [r0, #0]
801794c: 2b30 cmp r3, #48 @ 0x30
801794e: d10a bne.n 8017966 <__cvt+0xba>
8017950: 2200 movs r2, #0
8017952: 2300 movs r3, #0
8017954: 4630 mov r0, r6
8017956: 4639 mov r1, r7
8017958: f7e9 f88e bl 8000a78 <__aeabi_dcmpeq>
801795c: b918 cbnz r0, 8017966 <__cvt+0xba>
801795e: f1c4 0401 rsb r4, r4, #1
8017962: f8ca 4000 str.w r4, [sl]
8017966: f8da 3000 ldr.w r3, [sl]
801796a: 4499 add r9, r3
801796c: e7d3 b.n 8017916 <__cvt+0x6a>
801796e: 1c59 adds r1, r3, #1
8017970: 9103 str r1, [sp, #12]
8017972: 701a strb r2, [r3, #0]
8017974: e7d9 b.n 801792a <__cvt+0x7e>
08017976 <__exponent>:
8017976: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8017978: 2900 cmp r1, #0
801797a: bfba itte lt
801797c: 4249 neglt r1, r1
801797e: 232d movlt r3, #45 @ 0x2d
8017980: 232b movge r3, #43 @ 0x2b
8017982: 2909 cmp r1, #9
8017984: 7002 strb r2, [r0, #0]
8017986: 7043 strb r3, [r0, #1]
8017988: dd29 ble.n 80179de <__exponent+0x68>
801798a: f10d 0407 add.w r4, sp, #7
801798e: 4625 mov r5, r4
8017990: 270a movs r7, #10
8017992: 4622 mov r2, r4
8017994: fbb1 f6f7 udiv r6, r1, r7
8017998: fb07 1316 mls r3, r7, r6, r1
801799c: 3330 adds r3, #48 @ 0x30
801799e: f802 3c01 strb.w r3, [r2, #-1]
80179a2: 460b mov r3, r1
80179a4: 2b63 cmp r3, #99 @ 0x63
80179a6: f104 34ff add.w r4, r4, #4294967295 @ 0xffffffff
80179aa: 4631 mov r1, r6
80179ac: dcf1 bgt.n 8017992 <__exponent+0x1c>
80179ae: 3130 adds r1, #48 @ 0x30
80179b0: 1e93 subs r3, r2, #2
80179b2: f804 1c01 strb.w r1, [r4, #-1]
80179b6: 1c41 adds r1, r0, #1
80179b8: 461c mov r4, r3
80179ba: 42ab cmp r3, r5
80179bc: d30a bcc.n 80179d4 <__exponent+0x5e>
80179be: f10d 0309 add.w r3, sp, #9
80179c2: 1a9b subs r3, r3, r2
80179c4: 42a5 cmp r5, r4
80179c6: bf38 it cc
80179c8: 2300 movcc r3, #0
80179ca: 1c82 adds r2, r0, #2
80179cc: 4413 add r3, r2
80179ce: 1a18 subs r0, r3, r0
80179d0: b003 add sp, #12
80179d2: bdf0 pop {r4, r5, r6, r7, pc}
80179d4: f813 6b01 ldrb.w r6, [r3], #1
80179d8: f801 6f01 strb.w r6, [r1, #1]!
80179dc: e7ed b.n 80179ba <__exponent+0x44>
80179de: 2330 movs r3, #48 @ 0x30
80179e0: 3130 adds r1, #48 @ 0x30
80179e2: 7083 strb r3, [r0, #2]
80179e4: 70c1 strb r1, [r0, #3]
80179e6: 1d03 adds r3, r0, #4
80179e8: e7f1 b.n 80179ce <__exponent+0x58>
...
080179ec <_printf_float>:
80179ec: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
80179f0: b08d sub sp, #52 @ 0x34
80179f2: 460c mov r4, r1
80179f4: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
80179f8: 4616 mov r6, r2
80179fa: 461f mov r7, r3
80179fc: 4605 mov r5, r0
80179fe: f000 fff1 bl 80189e4 <_localeconv_r>
8017a02: 6803 ldr r3, [r0, #0]
8017a04: 9306 str r3, [sp, #24]
8017a06: 4618 mov r0, r3
8017a08: f7e8 fc0a bl 8000220 <strlen>
8017a0c: 2300 movs r3, #0
8017a0e: 930a str r3, [sp, #40] @ 0x28
8017a10: f8d8 3000 ldr.w r3, [r8]
8017a14: f894 a018 ldrb.w sl, [r4, #24]
8017a18: f8d4 b000 ldr.w fp, [r4]
8017a1c: 9007 str r0, [sp, #28]
8017a1e: 3307 adds r3, #7
8017a20: f023 0307 bic.w r3, r3, #7
8017a24: ecb3 7b02 vldmia r3!, {d7}
8017a28: ed8d 7b04 vstr d7, [sp, #16]
8017a2c: f8c8 3000 str.w r3, [r8]
8017a30: e9dd 8304 ldrd r8, r3, [sp, #16]
8017a34: f023 4900 bic.w r9, r3, #2147483648 @ 0x80000000
8017a38: ed84 7b12 vstr d7, [r4, #72] @ 0x48
8017a3c: 4b9c ldr r3, [pc, #624] @ (8017cb0 <_printf_float+0x2c4>)
8017a3e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8017a42: 4640 mov r0, r8
8017a44: 4649 mov r1, r9
8017a46: f7e9 f849 bl 8000adc <__aeabi_dcmpun>
8017a4a: bb70 cbnz r0, 8017aaa <_printf_float+0xbe>
8017a4c: 4b98 ldr r3, [pc, #608] @ (8017cb0 <_printf_float+0x2c4>)
8017a4e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8017a52: 4640 mov r0, r8
8017a54: 4649 mov r1, r9
8017a56: f7e9 f823 bl 8000aa0 <__aeabi_dcmple>
8017a5a: bb30 cbnz r0, 8017aaa <_printf_float+0xbe>
8017a5c: e9dd 0104 ldrd r0, r1, [sp, #16]
8017a60: 2200 movs r2, #0
8017a62: 2300 movs r3, #0
8017a64: f7e9 f812 bl 8000a8c <__aeabi_dcmplt>
8017a68: b110 cbz r0, 8017a70 <_printf_float+0x84>
8017a6a: 232d movs r3, #45 @ 0x2d
8017a6c: f884 3043 strb.w r3, [r4, #67] @ 0x43
8017a70: 4a90 ldr r2, [pc, #576] @ (8017cb4 <_printf_float+0x2c8>)
8017a72: 4b91 ldr r3, [pc, #580] @ (8017cb8 <_printf_float+0x2cc>)
8017a74: f1ba 0f47 cmp.w sl, #71 @ 0x47
8017a78: bf8c ite hi
8017a7a: 4690 movhi r8, r2
8017a7c: 4698 movls r8, r3
8017a7e: 2303 movs r3, #3
8017a80: 6123 str r3, [r4, #16]
8017a82: f02b 0304 bic.w r3, fp, #4
8017a86: 6023 str r3, [r4, #0]
8017a88: f04f 0900 mov.w r9, #0
8017a8c: 9700 str r7, [sp, #0]
8017a8e: 4633 mov r3, r6
8017a90: aa0b add r2, sp, #44 @ 0x2c
8017a92: 4621 mov r1, r4
8017a94: 4628 mov r0, r5
8017a96: f000 f9d1 bl 8017e3c <_printf_common>
8017a9a: 3001 adds r0, #1
8017a9c: f040 808c bne.w 8017bb8 <_printf_float+0x1cc>
8017aa0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8017aa4: b00d add sp, #52 @ 0x34
8017aa6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8017aaa: e9dd 2304 ldrd r2, r3, [sp, #16]
8017aae: 4610 mov r0, r2
8017ab0: 4619 mov r1, r3
8017ab2: f7e9 f813 bl 8000adc <__aeabi_dcmpun>
8017ab6: b140 cbz r0, 8017aca <_printf_float+0xde>
8017ab8: 9b05 ldr r3, [sp, #20]
8017aba: 4a80 ldr r2, [pc, #512] @ (8017cbc <_printf_float+0x2d0>)
8017abc: 2b00 cmp r3, #0
8017abe: bfbc itt lt
8017ac0: 232d movlt r3, #45 @ 0x2d
8017ac2: f884 3043 strblt.w r3, [r4, #67] @ 0x43
8017ac6: 4b7e ldr r3, [pc, #504] @ (8017cc0 <_printf_float+0x2d4>)
8017ac8: e7d4 b.n 8017a74 <_printf_float+0x88>
8017aca: 6863 ldr r3, [r4, #4]
8017acc: 1c5a adds r2, r3, #1
8017ace: f00a 09df and.w r9, sl, #223 @ 0xdf
8017ad2: d13b bne.n 8017b4c <_printf_float+0x160>
8017ad4: 2306 movs r3, #6
8017ad6: 6063 str r3, [r4, #4]
8017ad8: f44b 6280 orr.w r2, fp, #1024 @ 0x400
8017adc: 2300 movs r3, #0
8017ade: 6022 str r2, [r4, #0]
8017ae0: 9303 str r3, [sp, #12]
8017ae2: ab0a add r3, sp, #40 @ 0x28
8017ae4: e9cd a301 strd sl, r3, [sp, #4]
8017ae8: ab09 add r3, sp, #36 @ 0x24
8017aea: 9300 str r3, [sp, #0]
8017aec: 6861 ldr r1, [r4, #4]
8017aee: ed9d 0b04 vldr d0, [sp, #16]
8017af2: f10d 0323 add.w r3, sp, #35 @ 0x23
8017af6: 4628 mov r0, r5
8017af8: f7ff fed8 bl 80178ac <__cvt>
8017afc: f1b9 0f47 cmp.w r9, #71 @ 0x47
8017b00: 9909 ldr r1, [sp, #36] @ 0x24
8017b02: 4680 mov r8, r0
8017b04: d129 bne.n 8017b5a <_printf_float+0x16e>
8017b06: 1cc8 adds r0, r1, #3
8017b08: db02 blt.n 8017b10 <_printf_float+0x124>
8017b0a: 6863 ldr r3, [r4, #4]
8017b0c: 428b cmp r3, r1
8017b0e: da41 bge.n 8017b94 <_printf_float+0x1a8>
8017b10: f1aa 0a02 sub.w sl, sl, #2
8017b14: fa5f fa8a uxtb.w sl, sl
8017b18: 3901 subs r1, #1
8017b1a: 4652 mov r2, sl
8017b1c: f104 0050 add.w r0, r4, #80 @ 0x50
8017b20: 9109 str r1, [sp, #36] @ 0x24
8017b22: f7ff ff28 bl 8017976 <__exponent>
8017b26: 9a0a ldr r2, [sp, #40] @ 0x28
8017b28: 1813 adds r3, r2, r0
8017b2a: 2a01 cmp r2, #1
8017b2c: 4681 mov r9, r0
8017b2e: 6123 str r3, [r4, #16]
8017b30: dc02 bgt.n 8017b38 <_printf_float+0x14c>
8017b32: 6822 ldr r2, [r4, #0]
8017b34: 07d2 lsls r2, r2, #31
8017b36: d501 bpl.n 8017b3c <_printf_float+0x150>
8017b38: 3301 adds r3, #1
8017b3a: 6123 str r3, [r4, #16]
8017b3c: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
8017b40: 2b00 cmp r3, #0
8017b42: d0a3 beq.n 8017a8c <_printf_float+0xa0>
8017b44: 232d movs r3, #45 @ 0x2d
8017b46: f884 3043 strb.w r3, [r4, #67] @ 0x43
8017b4a: e79f b.n 8017a8c <_printf_float+0xa0>
8017b4c: f1b9 0f47 cmp.w r9, #71 @ 0x47
8017b50: d1c2 bne.n 8017ad8 <_printf_float+0xec>
8017b52: 2b00 cmp r3, #0
8017b54: d1c0 bne.n 8017ad8 <_printf_float+0xec>
8017b56: 2301 movs r3, #1
8017b58: e7bd b.n 8017ad6 <_printf_float+0xea>
8017b5a: f1ba 0f65 cmp.w sl, #101 @ 0x65
8017b5e: d9db bls.n 8017b18 <_printf_float+0x12c>
8017b60: f1ba 0f66 cmp.w sl, #102 @ 0x66
8017b64: d118 bne.n 8017b98 <_printf_float+0x1ac>
8017b66: 2900 cmp r1, #0
8017b68: 6863 ldr r3, [r4, #4]
8017b6a: dd0b ble.n 8017b84 <_printf_float+0x198>
8017b6c: 6121 str r1, [r4, #16]
8017b6e: b913 cbnz r3, 8017b76 <_printf_float+0x18a>
8017b70: 6822 ldr r2, [r4, #0]
8017b72: 07d0 lsls r0, r2, #31
8017b74: d502 bpl.n 8017b7c <_printf_float+0x190>
8017b76: 3301 adds r3, #1
8017b78: 440b add r3, r1
8017b7a: 6123 str r3, [r4, #16]
8017b7c: 65a1 str r1, [r4, #88] @ 0x58
8017b7e: f04f 0900 mov.w r9, #0
8017b82: e7db b.n 8017b3c <_printf_float+0x150>
8017b84: b913 cbnz r3, 8017b8c <_printf_float+0x1a0>
8017b86: 6822 ldr r2, [r4, #0]
8017b88: 07d2 lsls r2, r2, #31
8017b8a: d501 bpl.n 8017b90 <_printf_float+0x1a4>
8017b8c: 3302 adds r3, #2
8017b8e: e7f4 b.n 8017b7a <_printf_float+0x18e>
8017b90: 2301 movs r3, #1
8017b92: e7f2 b.n 8017b7a <_printf_float+0x18e>
8017b94: f04f 0a67 mov.w sl, #103 @ 0x67
8017b98: 9b0a ldr r3, [sp, #40] @ 0x28
8017b9a: 428b cmp r3, r1
8017b9c: dc05 bgt.n 8017baa <_printf_float+0x1be>
8017b9e: 6823 ldr r3, [r4, #0]
8017ba0: 6121 str r1, [r4, #16]
8017ba2: 07d8 lsls r0, r3, #31
8017ba4: d5ea bpl.n 8017b7c <_printf_float+0x190>
8017ba6: 1c4b adds r3, r1, #1
8017ba8: e7e7 b.n 8017b7a <_printf_float+0x18e>
8017baa: 2900 cmp r1, #0
8017bac: bfd4 ite le
8017bae: f1c1 0202 rsble r2, r1, #2
8017bb2: 2201 movgt r2, #1
8017bb4: 4413 add r3, r2
8017bb6: e7e0 b.n 8017b7a <_printf_float+0x18e>
8017bb8: 6823 ldr r3, [r4, #0]
8017bba: 055a lsls r2, r3, #21
8017bbc: d407 bmi.n 8017bce <_printf_float+0x1e2>
8017bbe: 6923 ldr r3, [r4, #16]
8017bc0: 4642 mov r2, r8
8017bc2: 4631 mov r1, r6
8017bc4: 4628 mov r0, r5
8017bc6: 47b8 blx r7
8017bc8: 3001 adds r0, #1
8017bca: d12b bne.n 8017c24 <_printf_float+0x238>
8017bcc: e768 b.n 8017aa0 <_printf_float+0xb4>
8017bce: f1ba 0f65 cmp.w sl, #101 @ 0x65
8017bd2: f240 80dd bls.w 8017d90 <_printf_float+0x3a4>
8017bd6: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
8017bda: 2200 movs r2, #0
8017bdc: 2300 movs r3, #0
8017bde: f7e8 ff4b bl 8000a78 <__aeabi_dcmpeq>
8017be2: 2800 cmp r0, #0
8017be4: d033 beq.n 8017c4e <_printf_float+0x262>
8017be6: 4a37 ldr r2, [pc, #220] @ (8017cc4 <_printf_float+0x2d8>)
8017be8: 2301 movs r3, #1
8017bea: 4631 mov r1, r6
8017bec: 4628 mov r0, r5
8017bee: 47b8 blx r7
8017bf0: 3001 adds r0, #1
8017bf2: f43f af55 beq.w 8017aa0 <_printf_float+0xb4>
8017bf6: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
8017bfa: 4543 cmp r3, r8
8017bfc: db02 blt.n 8017c04 <_printf_float+0x218>
8017bfe: 6823 ldr r3, [r4, #0]
8017c00: 07d8 lsls r0, r3, #31
8017c02: d50f bpl.n 8017c24 <_printf_float+0x238>
8017c04: e9dd 2306 ldrd r2, r3, [sp, #24]
8017c08: 4631 mov r1, r6
8017c0a: 4628 mov r0, r5
8017c0c: 47b8 blx r7
8017c0e: 3001 adds r0, #1
8017c10: f43f af46 beq.w 8017aa0 <_printf_float+0xb4>
8017c14: f04f 0900 mov.w r9, #0
8017c18: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
8017c1c: f104 0a1a add.w sl, r4, #26
8017c20: 45c8 cmp r8, r9
8017c22: dc09 bgt.n 8017c38 <_printf_float+0x24c>
8017c24: 6823 ldr r3, [r4, #0]
8017c26: 079b lsls r3, r3, #30
8017c28: f100 8103 bmi.w 8017e32 <_printf_float+0x446>
8017c2c: 68e0 ldr r0, [r4, #12]
8017c2e: 9b0b ldr r3, [sp, #44] @ 0x2c
8017c30: 4298 cmp r0, r3
8017c32: bfb8 it lt
8017c34: 4618 movlt r0, r3
8017c36: e735 b.n 8017aa4 <_printf_float+0xb8>
8017c38: 2301 movs r3, #1
8017c3a: 4652 mov r2, sl
8017c3c: 4631 mov r1, r6
8017c3e: 4628 mov r0, r5
8017c40: 47b8 blx r7
8017c42: 3001 adds r0, #1
8017c44: f43f af2c beq.w 8017aa0 <_printf_float+0xb4>
8017c48: f109 0901 add.w r9, r9, #1
8017c4c: e7e8 b.n 8017c20 <_printf_float+0x234>
8017c4e: 9b09 ldr r3, [sp, #36] @ 0x24
8017c50: 2b00 cmp r3, #0
8017c52: dc39 bgt.n 8017cc8 <_printf_float+0x2dc>
8017c54: 4a1b ldr r2, [pc, #108] @ (8017cc4 <_printf_float+0x2d8>)
8017c56: 2301 movs r3, #1
8017c58: 4631 mov r1, r6
8017c5a: 4628 mov r0, r5
8017c5c: 47b8 blx r7
8017c5e: 3001 adds r0, #1
8017c60: f43f af1e beq.w 8017aa0 <_printf_float+0xb4>
8017c64: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
8017c68: ea59 0303 orrs.w r3, r9, r3
8017c6c: d102 bne.n 8017c74 <_printf_float+0x288>
8017c6e: 6823 ldr r3, [r4, #0]
8017c70: 07d9 lsls r1, r3, #31
8017c72: d5d7 bpl.n 8017c24 <_printf_float+0x238>
8017c74: e9dd 2306 ldrd r2, r3, [sp, #24]
8017c78: 4631 mov r1, r6
8017c7a: 4628 mov r0, r5
8017c7c: 47b8 blx r7
8017c7e: 3001 adds r0, #1
8017c80: f43f af0e beq.w 8017aa0 <_printf_float+0xb4>
8017c84: f04f 0a00 mov.w sl, #0
8017c88: f104 0b1a add.w fp, r4, #26
8017c8c: 9b09 ldr r3, [sp, #36] @ 0x24
8017c8e: 425b negs r3, r3
8017c90: 4553 cmp r3, sl
8017c92: dc01 bgt.n 8017c98 <_printf_float+0x2ac>
8017c94: 464b mov r3, r9
8017c96: e793 b.n 8017bc0 <_printf_float+0x1d4>
8017c98: 2301 movs r3, #1
8017c9a: 465a mov r2, fp
8017c9c: 4631 mov r1, r6
8017c9e: 4628 mov r0, r5
8017ca0: 47b8 blx r7
8017ca2: 3001 adds r0, #1
8017ca4: f43f aefc beq.w 8017aa0 <_printf_float+0xb4>
8017ca8: f10a 0a01 add.w sl, sl, #1
8017cac: e7ee b.n 8017c8c <_printf_float+0x2a0>
8017cae: bf00 nop
8017cb0: 7fefffff .word 0x7fefffff
8017cb4: 0801c7c0 .word 0x0801c7c0
8017cb8: 0801c7bc .word 0x0801c7bc
8017cbc: 0801c7c8 .word 0x0801c7c8
8017cc0: 0801c7c4 .word 0x0801c7c4
8017cc4: 0801c7cc .word 0x0801c7cc
8017cc8: 6da3 ldr r3, [r4, #88] @ 0x58
8017cca: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
8017cce: 4553 cmp r3, sl
8017cd0: bfa8 it ge
8017cd2: 4653 movge r3, sl
8017cd4: 2b00 cmp r3, #0
8017cd6: 4699 mov r9, r3
8017cd8: dc36 bgt.n 8017d48 <_printf_float+0x35c>
8017cda: f04f 0b00 mov.w fp, #0
8017cde: ea29 79e9 bic.w r9, r9, r9, asr #31
8017ce2: f104 021a add.w r2, r4, #26
8017ce6: 6da3 ldr r3, [r4, #88] @ 0x58
8017ce8: 9304 str r3, [sp, #16]
8017cea: eba3 0309 sub.w r3, r3, r9
8017cee: 455b cmp r3, fp
8017cf0: dc31 bgt.n 8017d56 <_printf_float+0x36a>
8017cf2: 9b09 ldr r3, [sp, #36] @ 0x24
8017cf4: 459a cmp sl, r3
8017cf6: dc3a bgt.n 8017d6e <_printf_float+0x382>
8017cf8: 6823 ldr r3, [r4, #0]
8017cfa: 07da lsls r2, r3, #31
8017cfc: d437 bmi.n 8017d6e <_printf_float+0x382>
8017cfe: 9b09 ldr r3, [sp, #36] @ 0x24
8017d00: ebaa 0903 sub.w r9, sl, r3
8017d04: 9b04 ldr r3, [sp, #16]
8017d06: ebaa 0303 sub.w r3, sl, r3
8017d0a: 4599 cmp r9, r3
8017d0c: bfa8 it ge
8017d0e: 4699 movge r9, r3
8017d10: f1b9 0f00 cmp.w r9, #0
8017d14: dc33 bgt.n 8017d7e <_printf_float+0x392>
8017d16: f04f 0800 mov.w r8, #0
8017d1a: ea29 79e9 bic.w r9, r9, r9, asr #31
8017d1e: f104 0b1a add.w fp, r4, #26
8017d22: 9b09 ldr r3, [sp, #36] @ 0x24
8017d24: ebaa 0303 sub.w r3, sl, r3
8017d28: eba3 0309 sub.w r3, r3, r9
8017d2c: 4543 cmp r3, r8
8017d2e: f77f af79 ble.w 8017c24 <_printf_float+0x238>
8017d32: 2301 movs r3, #1
8017d34: 465a mov r2, fp
8017d36: 4631 mov r1, r6
8017d38: 4628 mov r0, r5
8017d3a: 47b8 blx r7
8017d3c: 3001 adds r0, #1
8017d3e: f43f aeaf beq.w 8017aa0 <_printf_float+0xb4>
8017d42: f108 0801 add.w r8, r8, #1
8017d46: e7ec b.n 8017d22 <_printf_float+0x336>
8017d48: 4642 mov r2, r8
8017d4a: 4631 mov r1, r6
8017d4c: 4628 mov r0, r5
8017d4e: 47b8 blx r7
8017d50: 3001 adds r0, #1
8017d52: d1c2 bne.n 8017cda <_printf_float+0x2ee>
8017d54: e6a4 b.n 8017aa0 <_printf_float+0xb4>
8017d56: 2301 movs r3, #1
8017d58: 4631 mov r1, r6
8017d5a: 4628 mov r0, r5
8017d5c: 9204 str r2, [sp, #16]
8017d5e: 47b8 blx r7
8017d60: 3001 adds r0, #1
8017d62: f43f ae9d beq.w 8017aa0 <_printf_float+0xb4>
8017d66: 9a04 ldr r2, [sp, #16]
8017d68: f10b 0b01 add.w fp, fp, #1
8017d6c: e7bb b.n 8017ce6 <_printf_float+0x2fa>
8017d6e: e9dd 2306 ldrd r2, r3, [sp, #24]
8017d72: 4631 mov r1, r6
8017d74: 4628 mov r0, r5
8017d76: 47b8 blx r7
8017d78: 3001 adds r0, #1
8017d7a: d1c0 bne.n 8017cfe <_printf_float+0x312>
8017d7c: e690 b.n 8017aa0 <_printf_float+0xb4>
8017d7e: 9a04 ldr r2, [sp, #16]
8017d80: 464b mov r3, r9
8017d82: 4442 add r2, r8
8017d84: 4631 mov r1, r6
8017d86: 4628 mov r0, r5
8017d88: 47b8 blx r7
8017d8a: 3001 adds r0, #1
8017d8c: d1c3 bne.n 8017d16 <_printf_float+0x32a>
8017d8e: e687 b.n 8017aa0 <_printf_float+0xb4>
8017d90: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
8017d94: f1ba 0f01 cmp.w sl, #1
8017d98: dc01 bgt.n 8017d9e <_printf_float+0x3b2>
8017d9a: 07db lsls r3, r3, #31
8017d9c: d536 bpl.n 8017e0c <_printf_float+0x420>
8017d9e: 2301 movs r3, #1
8017da0: 4642 mov r2, r8
8017da2: 4631 mov r1, r6
8017da4: 4628 mov r0, r5
8017da6: 47b8 blx r7
8017da8: 3001 adds r0, #1
8017daa: f43f ae79 beq.w 8017aa0 <_printf_float+0xb4>
8017dae: e9dd 2306 ldrd r2, r3, [sp, #24]
8017db2: 4631 mov r1, r6
8017db4: 4628 mov r0, r5
8017db6: 47b8 blx r7
8017db8: 3001 adds r0, #1
8017dba: f43f ae71 beq.w 8017aa0 <_printf_float+0xb4>
8017dbe: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
8017dc2: 2200 movs r2, #0
8017dc4: 2300 movs r3, #0
8017dc6: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
8017dca: f7e8 fe55 bl 8000a78 <__aeabi_dcmpeq>
8017dce: b9c0 cbnz r0, 8017e02 <_printf_float+0x416>
8017dd0: 4653 mov r3, sl
8017dd2: f108 0201 add.w r2, r8, #1
8017dd6: 4631 mov r1, r6
8017dd8: 4628 mov r0, r5
8017dda: 47b8 blx r7
8017ddc: 3001 adds r0, #1
8017dde: d10c bne.n 8017dfa <_printf_float+0x40e>
8017de0: e65e b.n 8017aa0 <_printf_float+0xb4>
8017de2: 2301 movs r3, #1
8017de4: 465a mov r2, fp
8017de6: 4631 mov r1, r6
8017de8: 4628 mov r0, r5
8017dea: 47b8 blx r7
8017dec: 3001 adds r0, #1
8017dee: f43f ae57 beq.w 8017aa0 <_printf_float+0xb4>
8017df2: f108 0801 add.w r8, r8, #1
8017df6: 45d0 cmp r8, sl
8017df8: dbf3 blt.n 8017de2 <_printf_float+0x3f6>
8017dfa: 464b mov r3, r9
8017dfc: f104 0250 add.w r2, r4, #80 @ 0x50
8017e00: e6df b.n 8017bc2 <_printf_float+0x1d6>
8017e02: f04f 0800 mov.w r8, #0
8017e06: f104 0b1a add.w fp, r4, #26
8017e0a: e7f4 b.n 8017df6 <_printf_float+0x40a>
8017e0c: 2301 movs r3, #1
8017e0e: 4642 mov r2, r8
8017e10: e7e1 b.n 8017dd6 <_printf_float+0x3ea>
8017e12: 2301 movs r3, #1
8017e14: 464a mov r2, r9
8017e16: 4631 mov r1, r6
8017e18: 4628 mov r0, r5
8017e1a: 47b8 blx r7
8017e1c: 3001 adds r0, #1
8017e1e: f43f ae3f beq.w 8017aa0 <_printf_float+0xb4>
8017e22: f108 0801 add.w r8, r8, #1
8017e26: 68e3 ldr r3, [r4, #12]
8017e28: 990b ldr r1, [sp, #44] @ 0x2c
8017e2a: 1a5b subs r3, r3, r1
8017e2c: 4543 cmp r3, r8
8017e2e: dcf0 bgt.n 8017e12 <_printf_float+0x426>
8017e30: e6fc b.n 8017c2c <_printf_float+0x240>
8017e32: f04f 0800 mov.w r8, #0
8017e36: f104 0919 add.w r9, r4, #25
8017e3a: e7f4 b.n 8017e26 <_printf_float+0x43a>
08017e3c <_printf_common>:
8017e3c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8017e40: 4616 mov r6, r2
8017e42: 4698 mov r8, r3
8017e44: 688a ldr r2, [r1, #8]
8017e46: 690b ldr r3, [r1, #16]
8017e48: f8dd 9020 ldr.w r9, [sp, #32]
8017e4c: 4293 cmp r3, r2
8017e4e: bfb8 it lt
8017e50: 4613 movlt r3, r2
8017e52: 6033 str r3, [r6, #0]
8017e54: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
8017e58: 4607 mov r7, r0
8017e5a: 460c mov r4, r1
8017e5c: b10a cbz r2, 8017e62 <_printf_common+0x26>
8017e5e: 3301 adds r3, #1
8017e60: 6033 str r3, [r6, #0]
8017e62: 6823 ldr r3, [r4, #0]
8017e64: 0699 lsls r1, r3, #26
8017e66: bf42 ittt mi
8017e68: 6833 ldrmi r3, [r6, #0]
8017e6a: 3302 addmi r3, #2
8017e6c: 6033 strmi r3, [r6, #0]
8017e6e: 6825 ldr r5, [r4, #0]
8017e70: f015 0506 ands.w r5, r5, #6
8017e74: d106 bne.n 8017e84 <_printf_common+0x48>
8017e76: f104 0a19 add.w sl, r4, #25
8017e7a: 68e3 ldr r3, [r4, #12]
8017e7c: 6832 ldr r2, [r6, #0]
8017e7e: 1a9b subs r3, r3, r2
8017e80: 42ab cmp r3, r5
8017e82: dc26 bgt.n 8017ed2 <_printf_common+0x96>
8017e84: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
8017e88: 6822 ldr r2, [r4, #0]
8017e8a: 3b00 subs r3, #0
8017e8c: bf18 it ne
8017e8e: 2301 movne r3, #1
8017e90: 0692 lsls r2, r2, #26
8017e92: d42b bmi.n 8017eec <_printf_common+0xb0>
8017e94: f104 0243 add.w r2, r4, #67 @ 0x43
8017e98: 4641 mov r1, r8
8017e9a: 4638 mov r0, r7
8017e9c: 47c8 blx r9
8017e9e: 3001 adds r0, #1
8017ea0: d01e beq.n 8017ee0 <_printf_common+0xa4>
8017ea2: 6823 ldr r3, [r4, #0]
8017ea4: 6922 ldr r2, [r4, #16]
8017ea6: f003 0306 and.w r3, r3, #6
8017eaa: 2b04 cmp r3, #4
8017eac: bf02 ittt eq
8017eae: 68e5 ldreq r5, [r4, #12]
8017eb0: 6833 ldreq r3, [r6, #0]
8017eb2: 1aed subeq r5, r5, r3
8017eb4: 68a3 ldr r3, [r4, #8]
8017eb6: bf0c ite eq
8017eb8: ea25 75e5 biceq.w r5, r5, r5, asr #31
8017ebc: 2500 movne r5, #0
8017ebe: 4293 cmp r3, r2
8017ec0: bfc4 itt gt
8017ec2: 1a9b subgt r3, r3, r2
8017ec4: 18ed addgt r5, r5, r3
8017ec6: 2600 movs r6, #0
8017ec8: 341a adds r4, #26
8017eca: 42b5 cmp r5, r6
8017ecc: d11a bne.n 8017f04 <_printf_common+0xc8>
8017ece: 2000 movs r0, #0
8017ed0: e008 b.n 8017ee4 <_printf_common+0xa8>
8017ed2: 2301 movs r3, #1
8017ed4: 4652 mov r2, sl
8017ed6: 4641 mov r1, r8
8017ed8: 4638 mov r0, r7
8017eda: 47c8 blx r9
8017edc: 3001 adds r0, #1
8017ede: d103 bne.n 8017ee8 <_printf_common+0xac>
8017ee0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8017ee4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8017ee8: 3501 adds r5, #1
8017eea: e7c6 b.n 8017e7a <_printf_common+0x3e>
8017eec: 18e1 adds r1, r4, r3
8017eee: 1c5a adds r2, r3, #1
8017ef0: 2030 movs r0, #48 @ 0x30
8017ef2: f881 0043 strb.w r0, [r1, #67] @ 0x43
8017ef6: 4422 add r2, r4
8017ef8: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
8017efc: f882 1043 strb.w r1, [r2, #67] @ 0x43
8017f00: 3302 adds r3, #2
8017f02: e7c7 b.n 8017e94 <_printf_common+0x58>
8017f04: 2301 movs r3, #1
8017f06: 4622 mov r2, r4
8017f08: 4641 mov r1, r8
8017f0a: 4638 mov r0, r7
8017f0c: 47c8 blx r9
8017f0e: 3001 adds r0, #1
8017f10: d0e6 beq.n 8017ee0 <_printf_common+0xa4>
8017f12: 3601 adds r6, #1
8017f14: e7d9 b.n 8017eca <_printf_common+0x8e>
...
08017f18 <_printf_i>:
8017f18: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
8017f1c: 7e0d ldrb r5, [r1, #24]
8017f1e: b085 sub sp, #20
8017f20: 2d78 cmp r5, #120 @ 0x78
8017f22: 4690 mov r8, r2
8017f24: 9e0c ldr r6, [sp, #48] @ 0x30
8017f26: 4607 mov r7, r0
8017f28: 460c mov r4, r1
8017f2a: 4699 mov r9, r3
8017f2c: f101 0243 add.w r2, r1, #67 @ 0x43
8017f30: d807 bhi.n 8017f42 <_printf_i+0x2a>
8017f32: 2d62 cmp r5, #98 @ 0x62
8017f34: d80a bhi.n 8017f4c <_printf_i+0x34>
8017f36: 2d00 cmp r5, #0
8017f38: f000 80d7 beq.w 80180ea <_printf_i+0x1d2>
8017f3c: 2d58 cmp r5, #88 @ 0x58
8017f3e: f000 80bc beq.w 80180ba <_printf_i+0x1a2>
8017f42: f104 0642 add.w r6, r4, #66 @ 0x42
8017f46: f884 5042 strb.w r5, [r4, #66] @ 0x42
8017f4a: e03b b.n 8017fc4 <_printf_i+0xac>
8017f4c: f1a5 0363 sub.w r3, r5, #99 @ 0x63
8017f50: 2b15 cmp r3, #21
8017f52: d8f6 bhi.n 8017f42 <_printf_i+0x2a>
8017f54: a101 add r1, pc, #4 @ (adr r1, 8017f5c <_printf_i+0x44>)
8017f56: f851 f023 ldr.w pc, [r1, r3, lsl #2]
8017f5a: bf00 nop
8017f5c: 08017fb5 .word 0x08017fb5
8017f60: 08017fc9 .word 0x08017fc9
8017f64: 08017f43 .word 0x08017f43
8017f68: 08017f43 .word 0x08017f43
8017f6c: 08017f43 .word 0x08017f43
8017f70: 08017f43 .word 0x08017f43
8017f74: 08017fc9 .word 0x08017fc9
8017f78: 08017f43 .word 0x08017f43
8017f7c: 08017f43 .word 0x08017f43
8017f80: 08017f43 .word 0x08017f43
8017f84: 08017f43 .word 0x08017f43
8017f88: 080180d1 .word 0x080180d1
8017f8c: 08017ff3 .word 0x08017ff3
8017f90: 08018083 .word 0x08018083
8017f94: 08017f43 .word 0x08017f43
8017f98: 08017f43 .word 0x08017f43
8017f9c: 080180f3 .word 0x080180f3
8017fa0: 08017f43 .word 0x08017f43
8017fa4: 08017ff3 .word 0x08017ff3
8017fa8: 08017f43 .word 0x08017f43
8017fac: 08017f43 .word 0x08017f43
8017fb0: 0801808b .word 0x0801808b
8017fb4: 6833 ldr r3, [r6, #0]
8017fb6: 1d1a adds r2, r3, #4
8017fb8: 681b ldr r3, [r3, #0]
8017fba: 6032 str r2, [r6, #0]
8017fbc: f104 0642 add.w r6, r4, #66 @ 0x42
8017fc0: f884 3042 strb.w r3, [r4, #66] @ 0x42
8017fc4: 2301 movs r3, #1
8017fc6: e0a1 b.n 801810c <_printf_i+0x1f4>
8017fc8: 6833 ldr r3, [r6, #0]
8017fca: 6820 ldr r0, [r4, #0]
8017fcc: 1d19 adds r1, r3, #4
8017fce: 6031 str r1, [r6, #0]
8017fd0: 0606 lsls r6, r0, #24
8017fd2: d501 bpl.n 8017fd8 <_printf_i+0xc0>
8017fd4: 681d ldr r5, [r3, #0]
8017fd6: e003 b.n 8017fe0 <_printf_i+0xc8>
8017fd8: 0645 lsls r5, r0, #25
8017fda: d5fb bpl.n 8017fd4 <_printf_i+0xbc>
8017fdc: f9b3 5000 ldrsh.w r5, [r3]
8017fe0: 2d00 cmp r5, #0
8017fe2: da03 bge.n 8017fec <_printf_i+0xd4>
8017fe4: 232d movs r3, #45 @ 0x2d
8017fe6: 426d negs r5, r5
8017fe8: f884 3043 strb.w r3, [r4, #67] @ 0x43
8017fec: 485b ldr r0, [pc, #364] @ (801815c <_printf_i+0x244>)
8017fee: 230a movs r3, #10
8017ff0: e011 b.n 8018016 <_printf_i+0xfe>
8017ff2: 6821 ldr r1, [r4, #0]
8017ff4: 6833 ldr r3, [r6, #0]
8017ff6: 0608 lsls r0, r1, #24
8017ff8: f853 5b04 ldr.w r5, [r3], #4
8017ffc: d402 bmi.n 8018004 <_printf_i+0xec>
8017ffe: 0649 lsls r1, r1, #25
8018000: bf48 it mi
8018002: b2ad uxthmi r5, r5
8018004: 6033 str r3, [r6, #0]
8018006: 7e23 ldrb r3, [r4, #24]
8018008: 4854 ldr r0, [pc, #336] @ (801815c <_printf_i+0x244>)
801800a: 2b6f cmp r3, #111 @ 0x6f
801800c: d15c bne.n 80180c8 <_printf_i+0x1b0>
801800e: 2308 movs r3, #8
8018010: 2100 movs r1, #0
8018012: f884 1043 strb.w r1, [r4, #67] @ 0x43
8018016: 6866 ldr r6, [r4, #4]
8018018: 60a6 str r6, [r4, #8]
801801a: 2e00 cmp r6, #0
801801c: db05 blt.n 801802a <_printf_i+0x112>
801801e: 6821 ldr r1, [r4, #0]
8018020: 432e orrs r6, r5
8018022: f021 0104 bic.w r1, r1, #4
8018026: 6021 str r1, [r4, #0]
8018028: d050 beq.n 80180cc <_printf_i+0x1b4>
801802a: 4616 mov r6, r2
801802c: fbb5 f1f3 udiv r1, r5, r3
8018030: fb03 5c11 mls ip, r3, r1, r5
8018034: f810 c00c ldrb.w ip, [r0, ip]
8018038: f806 cd01 strb.w ip, [r6, #-1]!
801803c: 46ac mov ip, r5
801803e: 4563 cmp r3, ip
8018040: 460d mov r5, r1
8018042: d9f3 bls.n 801802c <_printf_i+0x114>
8018044: 2b08 cmp r3, #8
8018046: d10b bne.n 8018060 <_printf_i+0x148>
8018048: 6823 ldr r3, [r4, #0]
801804a: 07db lsls r3, r3, #31
801804c: d508 bpl.n 8018060 <_printf_i+0x148>
801804e: 6923 ldr r3, [r4, #16]
8018050: 6861 ldr r1, [r4, #4]
8018052: 4299 cmp r1, r3
8018054: bfde ittt le
8018056: 2330 movle r3, #48 @ 0x30
8018058: f806 3c01 strble.w r3, [r6, #-1]
801805c: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
8018060: 1b92 subs r2, r2, r6
8018062: 6122 str r2, [r4, #16]
8018064: f8cd 9000 str.w r9, [sp]
8018068: 4643 mov r3, r8
801806a: aa03 add r2, sp, #12
801806c: 4621 mov r1, r4
801806e: 4638 mov r0, r7
8018070: f7ff fee4 bl 8017e3c <_printf_common>
8018074: 3001 adds r0, #1
8018076: d14e bne.n 8018116 <_printf_i+0x1fe>
8018078: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
801807c: b005 add sp, #20
801807e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
8018082: 6823 ldr r3, [r4, #0]
8018084: f043 0320 orr.w r3, r3, #32
8018088: 6023 str r3, [r4, #0]
801808a: 4835 ldr r0, [pc, #212] @ (8018160 <_printf_i+0x248>)
801808c: 2578 movs r5, #120 @ 0x78
801808e: f884 5045 strb.w r5, [r4, #69] @ 0x45
8018092: 6823 ldr r3, [r4, #0]
8018094: 6831 ldr r1, [r6, #0]
8018096: f013 0f80 tst.w r3, #128 @ 0x80
801809a: f851 5b04 ldr.w r5, [r1], #4
801809e: d103 bne.n 80180a8 <_printf_i+0x190>
80180a0: f013 0f40 tst.w r3, #64 @ 0x40
80180a4: bf18 it ne
80180a6: b2ad uxthne r5, r5
80180a8: 6031 str r1, [r6, #0]
80180aa: 07d9 lsls r1, r3, #31
80180ac: bf44 itt mi
80180ae: f043 0320 orrmi.w r3, r3, #32
80180b2: 6023 strmi r3, [r4, #0]
80180b4: b11d cbz r5, 80180be <_printf_i+0x1a6>
80180b6: 2310 movs r3, #16
80180b8: e7aa b.n 8018010 <_printf_i+0xf8>
80180ba: 4828 ldr r0, [pc, #160] @ (801815c <_printf_i+0x244>)
80180bc: e7e7 b.n 801808e <_printf_i+0x176>
80180be: 6823 ldr r3, [r4, #0]
80180c0: f023 0320 bic.w r3, r3, #32
80180c4: 6023 str r3, [r4, #0]
80180c6: e7f6 b.n 80180b6 <_printf_i+0x19e>
80180c8: 230a movs r3, #10
80180ca: e7a1 b.n 8018010 <_printf_i+0xf8>
80180cc: 4616 mov r6, r2
80180ce: e7b9 b.n 8018044 <_printf_i+0x12c>
80180d0: 6833 ldr r3, [r6, #0]
80180d2: 6825 ldr r5, [r4, #0]
80180d4: 6961 ldr r1, [r4, #20]
80180d6: 1d18 adds r0, r3, #4
80180d8: 6030 str r0, [r6, #0]
80180da: 062e lsls r6, r5, #24
80180dc: 681b ldr r3, [r3, #0]
80180de: d501 bpl.n 80180e4 <_printf_i+0x1cc>
80180e0: 6019 str r1, [r3, #0]
80180e2: e002 b.n 80180ea <_printf_i+0x1d2>
80180e4: 0668 lsls r0, r5, #25
80180e6: d5fb bpl.n 80180e0 <_printf_i+0x1c8>
80180e8: 8019 strh r1, [r3, #0]
80180ea: 2300 movs r3, #0
80180ec: 6123 str r3, [r4, #16]
80180ee: 4616 mov r6, r2
80180f0: e7b8 b.n 8018064 <_printf_i+0x14c>
80180f2: 6833 ldr r3, [r6, #0]
80180f4: 1d1a adds r2, r3, #4
80180f6: 6032 str r2, [r6, #0]
80180f8: 681e ldr r6, [r3, #0]
80180fa: 6862 ldr r2, [r4, #4]
80180fc: 2100 movs r1, #0
80180fe: 4630 mov r0, r6
8018100: f7e8 f83e bl 8000180 <memchr>
8018104: b108 cbz r0, 801810a <_printf_i+0x1f2>
8018106: 1b80 subs r0, r0, r6
8018108: 6060 str r0, [r4, #4]
801810a: 6863 ldr r3, [r4, #4]
801810c: 6123 str r3, [r4, #16]
801810e: 2300 movs r3, #0
8018110: f884 3043 strb.w r3, [r4, #67] @ 0x43
8018114: e7a6 b.n 8018064 <_printf_i+0x14c>
8018116: 6923 ldr r3, [r4, #16]
8018118: 4632 mov r2, r6
801811a: 4641 mov r1, r8
801811c: 4638 mov r0, r7
801811e: 47c8 blx r9
8018120: 3001 adds r0, #1
8018122: d0a9 beq.n 8018078 <_printf_i+0x160>
8018124: 6823 ldr r3, [r4, #0]
8018126: 079b lsls r3, r3, #30
8018128: d413 bmi.n 8018152 <_printf_i+0x23a>
801812a: 68e0 ldr r0, [r4, #12]
801812c: 9b03 ldr r3, [sp, #12]
801812e: 4298 cmp r0, r3
8018130: bfb8 it lt
8018132: 4618 movlt r0, r3
8018134: e7a2 b.n 801807c <_printf_i+0x164>
8018136: 2301 movs r3, #1
8018138: 4632 mov r2, r6
801813a: 4641 mov r1, r8
801813c: 4638 mov r0, r7
801813e: 47c8 blx r9
8018140: 3001 adds r0, #1
8018142: d099 beq.n 8018078 <_printf_i+0x160>
8018144: 3501 adds r5, #1
8018146: 68e3 ldr r3, [r4, #12]
8018148: 9903 ldr r1, [sp, #12]
801814a: 1a5b subs r3, r3, r1
801814c: 42ab cmp r3, r5
801814e: dcf2 bgt.n 8018136 <_printf_i+0x21e>
8018150: e7eb b.n 801812a <_printf_i+0x212>
8018152: 2500 movs r5, #0
8018154: f104 0619 add.w r6, r4, #25
8018158: e7f5 b.n 8018146 <_printf_i+0x22e>
801815a: bf00 nop
801815c: 0801c7ce .word 0x0801c7ce
8018160: 0801c7df .word 0x0801c7df
08018164 <_scanf_float>:
8018164: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8018168: b087 sub sp, #28
801816a: 4691 mov r9, r2
801816c: 9303 str r3, [sp, #12]
801816e: 688b ldr r3, [r1, #8]
8018170: 1e5a subs r2, r3, #1
8018172: f5b2 7fae cmp.w r2, #348 @ 0x15c
8018176: bf81 itttt hi
8018178: f46f 75ae mvnhi.w r5, #348 @ 0x15c
801817c: eb03 0b05 addhi.w fp, r3, r5
8018180: f240 135d movwhi r3, #349 @ 0x15d
8018184: 608b strhi r3, [r1, #8]
8018186: 680b ldr r3, [r1, #0]
8018188: 460a mov r2, r1
801818a: f04f 0500 mov.w r5, #0
801818e: f443 63f0 orr.w r3, r3, #1920 @ 0x780
8018192: f842 3b1c str.w r3, [r2], #28
8018196: e9cd 5504 strd r5, r5, [sp, #16]
801819a: 4680 mov r8, r0
801819c: 460c mov r4, r1
801819e: bf98 it ls
80181a0: f04f 0b00 movls.w fp, #0
80181a4: 9201 str r2, [sp, #4]
80181a6: 4616 mov r6, r2
80181a8: 46aa mov sl, r5
80181aa: 462f mov r7, r5
80181ac: 9502 str r5, [sp, #8]
80181ae: 68a2 ldr r2, [r4, #8]
80181b0: b15a cbz r2, 80181ca <_scanf_float+0x66>
80181b2: f8d9 3000 ldr.w r3, [r9]
80181b6: 781b ldrb r3, [r3, #0]
80181b8: 2b4e cmp r3, #78 @ 0x4e
80181ba: d863 bhi.n 8018284 <_scanf_float+0x120>
80181bc: 2b40 cmp r3, #64 @ 0x40
80181be: d83b bhi.n 8018238 <_scanf_float+0xd4>
80181c0: f1a3 012b sub.w r1, r3, #43 @ 0x2b
80181c4: b2c8 uxtb r0, r1
80181c6: 280e cmp r0, #14
80181c8: d939 bls.n 801823e <_scanf_float+0xda>
80181ca: b11f cbz r7, 80181d4 <_scanf_float+0x70>
80181cc: 6823 ldr r3, [r4, #0]
80181ce: f423 7380 bic.w r3, r3, #256 @ 0x100
80181d2: 6023 str r3, [r4, #0]
80181d4: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
80181d8: f1ba 0f01 cmp.w sl, #1
80181dc: f200 8114 bhi.w 8018408 <_scanf_float+0x2a4>
80181e0: 9b01 ldr r3, [sp, #4]
80181e2: 429e cmp r6, r3
80181e4: f200 8105 bhi.w 80183f2 <_scanf_float+0x28e>
80181e8: 2001 movs r0, #1
80181ea: b007 add sp, #28
80181ec: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
80181f0: f1a3 0261 sub.w r2, r3, #97 @ 0x61
80181f4: 2a0d cmp r2, #13
80181f6: d8e8 bhi.n 80181ca <_scanf_float+0x66>
80181f8: a101 add r1, pc, #4 @ (adr r1, 8018200 <_scanf_float+0x9c>)
80181fa: f851 f022 ldr.w pc, [r1, r2, lsl #2]
80181fe: bf00 nop
8018200: 08018349 .word 0x08018349
8018204: 080181cb .word 0x080181cb
8018208: 080181cb .word 0x080181cb
801820c: 080181cb .word 0x080181cb
8018210: 080183a5 .word 0x080183a5
8018214: 0801837f .word 0x0801837f
8018218: 080181cb .word 0x080181cb
801821c: 080181cb .word 0x080181cb
8018220: 08018357 .word 0x08018357
8018224: 080181cb .word 0x080181cb
8018228: 080181cb .word 0x080181cb
801822c: 080181cb .word 0x080181cb
8018230: 080181cb .word 0x080181cb
8018234: 08018313 .word 0x08018313
8018238: f1a3 0241 sub.w r2, r3, #65 @ 0x41
801823c: e7da b.n 80181f4 <_scanf_float+0x90>
801823e: 290e cmp r1, #14
8018240: d8c3 bhi.n 80181ca <_scanf_float+0x66>
8018242: a001 add r0, pc, #4 @ (adr r0, 8018248 <_scanf_float+0xe4>)
8018244: f850 f021 ldr.w pc, [r0, r1, lsl #2]
8018248: 08018303 .word 0x08018303
801824c: 080181cb .word 0x080181cb
8018250: 08018303 .word 0x08018303
8018254: 08018393 .word 0x08018393
8018258: 080181cb .word 0x080181cb
801825c: 080182a5 .word 0x080182a5
8018260: 080182e9 .word 0x080182e9
8018264: 080182e9 .word 0x080182e9
8018268: 080182e9 .word 0x080182e9
801826c: 080182e9 .word 0x080182e9
8018270: 080182e9 .word 0x080182e9
8018274: 080182e9 .word 0x080182e9
8018278: 080182e9 .word 0x080182e9
801827c: 080182e9 .word 0x080182e9
8018280: 080182e9 .word 0x080182e9
8018284: 2b6e cmp r3, #110 @ 0x6e
8018286: d809 bhi.n 801829c <_scanf_float+0x138>
8018288: 2b60 cmp r3, #96 @ 0x60
801828a: d8b1 bhi.n 80181f0 <_scanf_float+0x8c>
801828c: 2b54 cmp r3, #84 @ 0x54
801828e: d07b beq.n 8018388 <_scanf_float+0x224>
8018290: 2b59 cmp r3, #89 @ 0x59
8018292: d19a bne.n 80181ca <_scanf_float+0x66>
8018294: 2d07 cmp r5, #7
8018296: d198 bne.n 80181ca <_scanf_float+0x66>
8018298: 2508 movs r5, #8
801829a: e02f b.n 80182fc <_scanf_float+0x198>
801829c: 2b74 cmp r3, #116 @ 0x74
801829e: d073 beq.n 8018388 <_scanf_float+0x224>
80182a0: 2b79 cmp r3, #121 @ 0x79
80182a2: e7f6 b.n 8018292 <_scanf_float+0x12e>
80182a4: 6821 ldr r1, [r4, #0]
80182a6: 05c8 lsls r0, r1, #23
80182a8: d51e bpl.n 80182e8 <_scanf_float+0x184>
80182aa: f021 0180 bic.w r1, r1, #128 @ 0x80
80182ae: 6021 str r1, [r4, #0]
80182b0: 3701 adds r7, #1
80182b2: f1bb 0f00 cmp.w fp, #0
80182b6: d003 beq.n 80182c0 <_scanf_float+0x15c>
80182b8: 3201 adds r2, #1
80182ba: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff
80182be: 60a2 str r2, [r4, #8]
80182c0: 68a3 ldr r3, [r4, #8]
80182c2: 3b01 subs r3, #1
80182c4: 60a3 str r3, [r4, #8]
80182c6: 6923 ldr r3, [r4, #16]
80182c8: 3301 adds r3, #1
80182ca: 6123 str r3, [r4, #16]
80182cc: f8d9 3004 ldr.w r3, [r9, #4]
80182d0: 3b01 subs r3, #1
80182d2: 2b00 cmp r3, #0
80182d4: f8c9 3004 str.w r3, [r9, #4]
80182d8: f340 8082 ble.w 80183e0 <_scanf_float+0x27c>
80182dc: f8d9 3000 ldr.w r3, [r9]
80182e0: 3301 adds r3, #1
80182e2: f8c9 3000 str.w r3, [r9]
80182e6: e762 b.n 80181ae <_scanf_float+0x4a>
80182e8: eb1a 0105 adds.w r1, sl, r5
80182ec: f47f af6d bne.w 80181ca <_scanf_float+0x66>
80182f0: 6822 ldr r2, [r4, #0]
80182f2: f422 72c0 bic.w r2, r2, #384 @ 0x180
80182f6: 6022 str r2, [r4, #0]
80182f8: 460d mov r5, r1
80182fa: 468a mov sl, r1
80182fc: f806 3b01 strb.w r3, [r6], #1
8018300: e7de b.n 80182c0 <_scanf_float+0x15c>
8018302: 6822 ldr r2, [r4, #0]
8018304: 0610 lsls r0, r2, #24
8018306: f57f af60 bpl.w 80181ca <_scanf_float+0x66>
801830a: f022 0280 bic.w r2, r2, #128 @ 0x80
801830e: 6022 str r2, [r4, #0]
8018310: e7f4 b.n 80182fc <_scanf_float+0x198>
8018312: f1ba 0f00 cmp.w sl, #0
8018316: d10c bne.n 8018332 <_scanf_float+0x1ce>
8018318: b977 cbnz r7, 8018338 <_scanf_float+0x1d4>
801831a: 6822 ldr r2, [r4, #0]
801831c: f402 61e0 and.w r1, r2, #1792 @ 0x700
8018320: f5b1 6fe0 cmp.w r1, #1792 @ 0x700
8018324: d108 bne.n 8018338 <_scanf_float+0x1d4>
8018326: f422 62f0 bic.w r2, r2, #1920 @ 0x780
801832a: 6022 str r2, [r4, #0]
801832c: f04f 0a01 mov.w sl, #1
8018330: e7e4 b.n 80182fc <_scanf_float+0x198>
8018332: f1ba 0f02 cmp.w sl, #2
8018336: d050 beq.n 80183da <_scanf_float+0x276>
8018338: 2d01 cmp r5, #1
801833a: d002 beq.n 8018342 <_scanf_float+0x1de>
801833c: 2d04 cmp r5, #4
801833e: f47f af44 bne.w 80181ca <_scanf_float+0x66>
8018342: 3501 adds r5, #1
8018344: b2ed uxtb r5, r5
8018346: e7d9 b.n 80182fc <_scanf_float+0x198>
8018348: f1ba 0f01 cmp.w sl, #1
801834c: f47f af3d bne.w 80181ca <_scanf_float+0x66>
8018350: f04f 0a02 mov.w sl, #2
8018354: e7d2 b.n 80182fc <_scanf_float+0x198>
8018356: b975 cbnz r5, 8018376 <_scanf_float+0x212>
8018358: 2f00 cmp r7, #0
801835a: f47f af37 bne.w 80181cc <_scanf_float+0x68>
801835e: 6822 ldr r2, [r4, #0]
8018360: f402 61e0 and.w r1, r2, #1792 @ 0x700
8018364: f5b1 6fe0 cmp.w r1, #1792 @ 0x700
8018368: f040 8102 bne.w 8018570 <_scanf_float+0x40c>
801836c: f422 62f0 bic.w r2, r2, #1920 @ 0x780
8018370: 6022 str r2, [r4, #0]
8018372: 2501 movs r5, #1
8018374: e7c2 b.n 80182fc <_scanf_float+0x198>
8018376: 2d03 cmp r5, #3
8018378: d0e3 beq.n 8018342 <_scanf_float+0x1de>
801837a: 2d05 cmp r5, #5
801837c: e7df b.n 801833e <_scanf_float+0x1da>
801837e: 2d02 cmp r5, #2
8018380: f47f af23 bne.w 80181ca <_scanf_float+0x66>
8018384: 2503 movs r5, #3
8018386: e7b9 b.n 80182fc <_scanf_float+0x198>
8018388: 2d06 cmp r5, #6
801838a: f47f af1e bne.w 80181ca <_scanf_float+0x66>
801838e: 2507 movs r5, #7
8018390: e7b4 b.n 80182fc <_scanf_float+0x198>
8018392: 6822 ldr r2, [r4, #0]
8018394: 0591 lsls r1, r2, #22
8018396: f57f af18 bpl.w 80181ca <_scanf_float+0x66>
801839a: f422 7220 bic.w r2, r2, #640 @ 0x280
801839e: 6022 str r2, [r4, #0]
80183a0: 9702 str r7, [sp, #8]
80183a2: e7ab b.n 80182fc <_scanf_float+0x198>
80183a4: 6822 ldr r2, [r4, #0]
80183a6: f402 61a0 and.w r1, r2, #1280 @ 0x500
80183aa: f5b1 6f80 cmp.w r1, #1024 @ 0x400
80183ae: d005 beq.n 80183bc <_scanf_float+0x258>
80183b0: 0550 lsls r0, r2, #21
80183b2: f57f af0a bpl.w 80181ca <_scanf_float+0x66>
80183b6: 2f00 cmp r7, #0
80183b8: f000 80da beq.w 8018570 <_scanf_float+0x40c>
80183bc: 0591 lsls r1, r2, #22
80183be: bf58 it pl
80183c0: 9902 ldrpl r1, [sp, #8]
80183c2: f422 62f0 bic.w r2, r2, #1920 @ 0x780
80183c6: bf58 it pl
80183c8: 1a79 subpl r1, r7, r1
80183ca: f442 72c0 orr.w r2, r2, #384 @ 0x180
80183ce: bf58 it pl
80183d0: e9cd 1604 strdpl r1, r6, [sp, #16]
80183d4: 6022 str r2, [r4, #0]
80183d6: 2700 movs r7, #0
80183d8: e790 b.n 80182fc <_scanf_float+0x198>
80183da: f04f 0a03 mov.w sl, #3
80183de: e78d b.n 80182fc <_scanf_float+0x198>
80183e0: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180
80183e4: 4649 mov r1, r9
80183e6: 4640 mov r0, r8
80183e8: 4798 blx r3
80183ea: 2800 cmp r0, #0
80183ec: f43f aedf beq.w 80181ae <_scanf_float+0x4a>
80183f0: e6eb b.n 80181ca <_scanf_float+0x66>
80183f2: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
80183f6: f816 1d01 ldrb.w r1, [r6, #-1]!
80183fa: 464a mov r2, r9
80183fc: 4640 mov r0, r8
80183fe: 4798 blx r3
8018400: 6923 ldr r3, [r4, #16]
8018402: 3b01 subs r3, #1
8018404: 6123 str r3, [r4, #16]
8018406: e6eb b.n 80181e0 <_scanf_float+0x7c>
8018408: 1e6b subs r3, r5, #1
801840a: 2b06 cmp r3, #6
801840c: d824 bhi.n 8018458 <_scanf_float+0x2f4>
801840e: 2d02 cmp r5, #2
8018410: d836 bhi.n 8018480 <_scanf_float+0x31c>
8018412: 9b01 ldr r3, [sp, #4]
8018414: 429e cmp r6, r3
8018416: f67f aee7 bls.w 80181e8 <_scanf_float+0x84>
801841a: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
801841e: f816 1d01 ldrb.w r1, [r6, #-1]!
8018422: 464a mov r2, r9
8018424: 4640 mov r0, r8
8018426: 4798 blx r3
8018428: 6923 ldr r3, [r4, #16]
801842a: 3b01 subs r3, #1
801842c: 6123 str r3, [r4, #16]
801842e: e7f0 b.n 8018412 <_scanf_float+0x2ae>
8018430: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
8018434: f81b 1d01 ldrb.w r1, [fp, #-1]!
8018438: 464a mov r2, r9
801843a: 4640 mov r0, r8
801843c: 4798 blx r3
801843e: 6923 ldr r3, [r4, #16]
8018440: 3b01 subs r3, #1
8018442: 6123 str r3, [r4, #16]
8018444: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
8018448: fa5f fa8a uxtb.w sl, sl
801844c: f1ba 0f02 cmp.w sl, #2
8018450: d1ee bne.n 8018430 <_scanf_float+0x2cc>
8018452: 3d03 subs r5, #3
8018454: b2ed uxtb r5, r5
8018456: 1b76 subs r6, r6, r5
8018458: 6823 ldr r3, [r4, #0]
801845a: 05da lsls r2, r3, #23
801845c: d530 bpl.n 80184c0 <_scanf_float+0x35c>
801845e: 055d lsls r5, r3, #21
8018460: d511 bpl.n 8018486 <_scanf_float+0x322>
8018462: 9b01 ldr r3, [sp, #4]
8018464: 429e cmp r6, r3
8018466: f67f aebf bls.w 80181e8 <_scanf_float+0x84>
801846a: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
801846e: f816 1d01 ldrb.w r1, [r6, #-1]!
8018472: 464a mov r2, r9
8018474: 4640 mov r0, r8
8018476: 4798 blx r3
8018478: 6923 ldr r3, [r4, #16]
801847a: 3b01 subs r3, #1
801847c: 6123 str r3, [r4, #16]
801847e: e7f0 b.n 8018462 <_scanf_float+0x2fe>
8018480: 46aa mov sl, r5
8018482: 46b3 mov fp, r6
8018484: e7de b.n 8018444 <_scanf_float+0x2e0>
8018486: f816 1c01 ldrb.w r1, [r6, #-1]
801848a: 6923 ldr r3, [r4, #16]
801848c: 2965 cmp r1, #101 @ 0x65
801848e: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff
8018492: f106 35ff add.w r5, r6, #4294967295 @ 0xffffffff
8018496: 6123 str r3, [r4, #16]
8018498: d00c beq.n 80184b4 <_scanf_float+0x350>
801849a: 2945 cmp r1, #69 @ 0x45
801849c: d00a beq.n 80184b4 <_scanf_float+0x350>
801849e: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
80184a2: 464a mov r2, r9
80184a4: 4640 mov r0, r8
80184a6: 4798 blx r3
80184a8: 6923 ldr r3, [r4, #16]
80184aa: f816 1c02 ldrb.w r1, [r6, #-2]
80184ae: 3b01 subs r3, #1
80184b0: 1eb5 subs r5, r6, #2
80184b2: 6123 str r3, [r4, #16]
80184b4: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c
80184b8: 464a mov r2, r9
80184ba: 4640 mov r0, r8
80184bc: 4798 blx r3
80184be: 462e mov r6, r5
80184c0: 6822 ldr r2, [r4, #0]
80184c2: f012 0210 ands.w r2, r2, #16
80184c6: d001 beq.n 80184cc <_scanf_float+0x368>
80184c8: 2000 movs r0, #0
80184ca: e68e b.n 80181ea <_scanf_float+0x86>
80184cc: 7032 strb r2, [r6, #0]
80184ce: 6823 ldr r3, [r4, #0]
80184d0: f403 63c0 and.w r3, r3, #1536 @ 0x600
80184d4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80184d8: d124 bne.n 8018524 <_scanf_float+0x3c0>
80184da: 9b02 ldr r3, [sp, #8]
80184dc: 429f cmp r7, r3
80184de: d00a beq.n 80184f6 <_scanf_float+0x392>
80184e0: 1bda subs r2, r3, r7
80184e2: f204 136f addw r3, r4, #367 @ 0x16f
80184e6: 429e cmp r6, r3
80184e8: bf28 it cs
80184ea: f504 76b7 addcs.w r6, r4, #366 @ 0x16e
80184ee: 4921 ldr r1, [pc, #132] @ (8018574 <_scanf_float+0x410>)
80184f0: 4630 mov r0, r6
80184f2: f000 f977 bl 80187e4 <siprintf>
80184f6: 9901 ldr r1, [sp, #4]
80184f8: 2200 movs r2, #0
80184fa: 4640 mov r0, r8
80184fc: f002 fd18 bl 801af30 <_strtod_r>
8018500: 9b03 ldr r3, [sp, #12]
8018502: 6821 ldr r1, [r4, #0]
8018504: 681b ldr r3, [r3, #0]
8018506: 0788 lsls r0, r1, #30
8018508: ec57 6b10 vmov r6, r7, d0
801850c: f103 0204 add.w r2, r3, #4
8018510: d515 bpl.n 801853e <_scanf_float+0x3da>
8018512: 9903 ldr r1, [sp, #12]
8018514: 600a str r2, [r1, #0]
8018516: 681b ldr r3, [r3, #0]
8018518: e9c3 6700 strd r6, r7, [r3]
801851c: 68e3 ldr r3, [r4, #12]
801851e: 3301 adds r3, #1
8018520: 60e3 str r3, [r4, #12]
8018522: e7d1 b.n 80184c8 <_scanf_float+0x364>
8018524: 9b04 ldr r3, [sp, #16]
8018526: 2b00 cmp r3, #0
8018528: d0e5 beq.n 80184f6 <_scanf_float+0x392>
801852a: 9905 ldr r1, [sp, #20]
801852c: 230a movs r3, #10
801852e: 3101 adds r1, #1
8018530: 4640 mov r0, r8
8018532: f002 fd7d bl 801b030 <_strtol_r>
8018536: 9b04 ldr r3, [sp, #16]
8018538: 9e05 ldr r6, [sp, #20]
801853a: 1ac2 subs r2, r0, r3
801853c: e7d1 b.n 80184e2 <_scanf_float+0x37e>
801853e: f011 0f04 tst.w r1, #4
8018542: 9903 ldr r1, [sp, #12]
8018544: 600a str r2, [r1, #0]
8018546: d1e6 bne.n 8018516 <_scanf_float+0x3b2>
8018548: 681d ldr r5, [r3, #0]
801854a: 4632 mov r2, r6
801854c: 463b mov r3, r7
801854e: 4630 mov r0, r6
8018550: 4639 mov r1, r7
8018552: f7e8 fac3 bl 8000adc <__aeabi_dcmpun>
8018556: b128 cbz r0, 8018564 <_scanf_float+0x400>
8018558: 4807 ldr r0, [pc, #28] @ (8018578 <_scanf_float+0x414>)
801855a: f000 fac9 bl 8018af0 <nanf>
801855e: ed85 0a00 vstr s0, [r5]
8018562: e7db b.n 801851c <_scanf_float+0x3b8>
8018564: 4630 mov r0, r6
8018566: 4639 mov r1, r7
8018568: f7e8 fb16 bl 8000b98 <__aeabi_d2f>
801856c: 6028 str r0, [r5, #0]
801856e: e7d5 b.n 801851c <_scanf_float+0x3b8>
8018570: 2700 movs r7, #0
8018572: e62f b.n 80181d4 <_scanf_float+0x70>
8018574: 0801c7f0 .word 0x0801c7f0
8018578: 0801c931 .word 0x0801c931
0801857c <std>:
801857c: 2300 movs r3, #0
801857e: b510 push {r4, lr}
8018580: 4604 mov r4, r0
8018582: e9c0 3300 strd r3, r3, [r0]
8018586: e9c0 3304 strd r3, r3, [r0, #16]
801858a: 6083 str r3, [r0, #8]
801858c: 8181 strh r1, [r0, #12]
801858e: 6643 str r3, [r0, #100] @ 0x64
8018590: 81c2 strh r2, [r0, #14]
8018592: 6183 str r3, [r0, #24]
8018594: 4619 mov r1, r3
8018596: 2208 movs r2, #8
8018598: 305c adds r0, #92 @ 0x5c
801859a: f000 fa1b bl 80189d4 <memset>
801859e: 4b0d ldr r3, [pc, #52] @ (80185d4 <std+0x58>)
80185a0: 6263 str r3, [r4, #36] @ 0x24
80185a2: 4b0d ldr r3, [pc, #52] @ (80185d8 <std+0x5c>)
80185a4: 62a3 str r3, [r4, #40] @ 0x28
80185a6: 4b0d ldr r3, [pc, #52] @ (80185dc <std+0x60>)
80185a8: 62e3 str r3, [r4, #44] @ 0x2c
80185aa: 4b0d ldr r3, [pc, #52] @ (80185e0 <std+0x64>)
80185ac: 6323 str r3, [r4, #48] @ 0x30
80185ae: 4b0d ldr r3, [pc, #52] @ (80185e4 <std+0x68>)
80185b0: 6224 str r4, [r4, #32]
80185b2: 429c cmp r4, r3
80185b4: d006 beq.n 80185c4 <std+0x48>
80185b6: f103 0268 add.w r2, r3, #104 @ 0x68
80185ba: 4294 cmp r4, r2
80185bc: d002 beq.n 80185c4 <std+0x48>
80185be: 33d0 adds r3, #208 @ 0xd0
80185c0: 429c cmp r4, r3
80185c2: d105 bne.n 80185d0 <std+0x54>
80185c4: f104 0058 add.w r0, r4, #88 @ 0x58
80185c8: e8bd 4010 ldmia.w sp!, {r4, lr}
80185cc: f000 ba7e b.w 8018acc <__retarget_lock_init_recursive>
80185d0: bd10 pop {r4, pc}
80185d2: bf00 nop
80185d4: 08018829 .word 0x08018829
80185d8: 0801884b .word 0x0801884b
80185dc: 08018883 .word 0x08018883
80185e0: 080188a9 .word 0x080188a9
80185e4: 20013afc .word 0x20013afc
080185e8 <stdio_exit_handler>:
80185e8: 4a02 ldr r2, [pc, #8] @ (80185f4 <stdio_exit_handler+0xc>)
80185ea: 4903 ldr r1, [pc, #12] @ (80185f8 <stdio_exit_handler+0x10>)
80185ec: 4803 ldr r0, [pc, #12] @ (80185fc <stdio_exit_handler+0x14>)
80185ee: f000 b86b b.w 80186c8 <_fwalk_sglue>
80185f2: bf00 nop
80185f4: 20000110 .word 0x20000110
80185f8: 0801b665 .word 0x0801b665
80185fc: 20000120 .word 0x20000120
08018600 <cleanup_stdio>:
8018600: 6841 ldr r1, [r0, #4]
8018602: 4b0c ldr r3, [pc, #48] @ (8018634 <cleanup_stdio+0x34>)
8018604: 4299 cmp r1, r3
8018606: b510 push {r4, lr}
8018608: 4604 mov r4, r0
801860a: d001 beq.n 8018610 <cleanup_stdio+0x10>
801860c: f003 f82a bl 801b664 <_fflush_r>
8018610: 68a1 ldr r1, [r4, #8]
8018612: 4b09 ldr r3, [pc, #36] @ (8018638 <cleanup_stdio+0x38>)
8018614: 4299 cmp r1, r3
8018616: d002 beq.n 801861e <cleanup_stdio+0x1e>
8018618: 4620 mov r0, r4
801861a: f003 f823 bl 801b664 <_fflush_r>
801861e: 68e1 ldr r1, [r4, #12]
8018620: 4b06 ldr r3, [pc, #24] @ (801863c <cleanup_stdio+0x3c>)
8018622: 4299 cmp r1, r3
8018624: d004 beq.n 8018630 <cleanup_stdio+0x30>
8018626: 4620 mov r0, r4
8018628: e8bd 4010 ldmia.w sp!, {r4, lr}
801862c: f003 b81a b.w 801b664 <_fflush_r>
8018630: bd10 pop {r4, pc}
8018632: bf00 nop
8018634: 20013afc .word 0x20013afc
8018638: 20013b64 .word 0x20013b64
801863c: 20013bcc .word 0x20013bcc
08018640 <global_stdio_init.part.0>:
8018640: 4b0c ldr r3, [pc, #48] @ (8018674 <global_stdio_init.part.0+0x34>)
8018642: 4a0d ldr r2, [pc, #52] @ (8018678 <global_stdio_init.part.0+0x38>)
8018644: 480d ldr r0, [pc, #52] @ (801867c <global_stdio_init.part.0+0x3c>)
8018646: b510 push {r4, lr}
8018648: 2104 movs r1, #4
801864a: 601a str r2, [r3, #0]
801864c: 2200 movs r2, #0
801864e: f7ff ff95 bl 801857c <std>
8018652: 4b0a ldr r3, [pc, #40] @ (801867c <global_stdio_init.part.0+0x3c>)
8018654: 2201 movs r2, #1
8018656: 461c mov r4, r3
8018658: 2109 movs r1, #9
801865a: f103 0068 add.w r0, r3, #104 @ 0x68
801865e: f7ff ff8d bl 801857c <std>
8018662: f104 00d0 add.w r0, r4, #208 @ 0xd0
8018666: 2202 movs r2, #2
8018668: e8bd 4010 ldmia.w sp!, {r4, lr}
801866c: 2112 movs r1, #18
801866e: f7ff bf85 b.w 801857c <std>
8018672: bf00 nop
8018674: 20013c34 .word 0x20013c34
8018678: 080185e9 .word 0x080185e9
801867c: 20013afc .word 0x20013afc
08018680 <__sfp_lock_acquire>:
8018680: 4801 ldr r0, [pc, #4] @ (8018688 <__sfp_lock_acquire+0x8>)
8018682: f000 ba24 b.w 8018ace <__retarget_lock_acquire_recursive>
8018686: bf00 nop
8018688: 20013c3d .word 0x20013c3d
0801868c <__sfp_lock_release>:
801868c: 4801 ldr r0, [pc, #4] @ (8018694 <__sfp_lock_release+0x8>)
801868e: f000 ba1f b.w 8018ad0 <__retarget_lock_release_recursive>
8018692: bf00 nop
8018694: 20013c3d .word 0x20013c3d
08018698 <__sinit>:
8018698: b510 push {r4, lr}
801869a: 4604 mov r4, r0
801869c: f7ff fff0 bl 8018680 <__sfp_lock_acquire>
80186a0: 6a23 ldr r3, [r4, #32]
80186a2: b11b cbz r3, 80186ac <__sinit+0x14>
80186a4: e8bd 4010 ldmia.w sp!, {r4, lr}
80186a8: f7ff bff0 b.w 801868c <__sfp_lock_release>
80186ac: 4b04 ldr r3, [pc, #16] @ (80186c0 <__sinit+0x28>)
80186ae: 6223 str r3, [r4, #32]
80186b0: 4b04 ldr r3, [pc, #16] @ (80186c4 <__sinit+0x2c>)
80186b2: 681b ldr r3, [r3, #0]
80186b4: 2b00 cmp r3, #0
80186b6: d1f5 bne.n 80186a4 <__sinit+0xc>
80186b8: f7ff ffc2 bl 8018640 <global_stdio_init.part.0>
80186bc: e7f2 b.n 80186a4 <__sinit+0xc>
80186be: bf00 nop
80186c0: 08018601 .word 0x08018601
80186c4: 20013c34 .word 0x20013c34
080186c8 <_fwalk_sglue>:
80186c8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
80186cc: 4607 mov r7, r0
80186ce: 4688 mov r8, r1
80186d0: 4614 mov r4, r2
80186d2: 2600 movs r6, #0
80186d4: e9d4 9501 ldrd r9, r5, [r4, #4]
80186d8: f1b9 0901 subs.w r9, r9, #1
80186dc: d505 bpl.n 80186ea <_fwalk_sglue+0x22>
80186de: 6824 ldr r4, [r4, #0]
80186e0: 2c00 cmp r4, #0
80186e2: d1f7 bne.n 80186d4 <_fwalk_sglue+0xc>
80186e4: 4630 mov r0, r6
80186e6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
80186ea: 89ab ldrh r3, [r5, #12]
80186ec: 2b01 cmp r3, #1
80186ee: d907 bls.n 8018700 <_fwalk_sglue+0x38>
80186f0: f9b5 300e ldrsh.w r3, [r5, #14]
80186f4: 3301 adds r3, #1
80186f6: d003 beq.n 8018700 <_fwalk_sglue+0x38>
80186f8: 4629 mov r1, r5
80186fa: 4638 mov r0, r7
80186fc: 47c0 blx r8
80186fe: 4306 orrs r6, r0
8018700: 3568 adds r5, #104 @ 0x68
8018702: e7e9 b.n 80186d8 <_fwalk_sglue+0x10>
08018704 <iprintf>:
8018704: b40f push {r0, r1, r2, r3}
8018706: b507 push {r0, r1, r2, lr}
8018708: 4906 ldr r1, [pc, #24] @ (8018724 <iprintf+0x20>)
801870a: ab04 add r3, sp, #16
801870c: 6808 ldr r0, [r1, #0]
801870e: f853 2b04 ldr.w r2, [r3], #4
8018712: 6881 ldr r1, [r0, #8]
8018714: 9301 str r3, [sp, #4]
8018716: f002 fe0f bl 801b338 <_vfiprintf_r>
801871a: b003 add sp, #12
801871c: f85d eb04 ldr.w lr, [sp], #4
8018720: b004 add sp, #16
8018722: 4770 bx lr
8018724: 2000011c .word 0x2000011c
08018728 <_puts_r>:
8018728: 6a03 ldr r3, [r0, #32]
801872a: b570 push {r4, r5, r6, lr}
801872c: 6884 ldr r4, [r0, #8]
801872e: 4605 mov r5, r0
8018730: 460e mov r6, r1
8018732: b90b cbnz r3, 8018738 <_puts_r+0x10>
8018734: f7ff ffb0 bl 8018698 <__sinit>
8018738: 6e63 ldr r3, [r4, #100] @ 0x64
801873a: 07db lsls r3, r3, #31
801873c: d405 bmi.n 801874a <_puts_r+0x22>
801873e: 89a3 ldrh r3, [r4, #12]
8018740: 0598 lsls r0, r3, #22
8018742: d402 bmi.n 801874a <_puts_r+0x22>
8018744: 6da0 ldr r0, [r4, #88] @ 0x58
8018746: f000 f9c2 bl 8018ace <__retarget_lock_acquire_recursive>
801874a: 89a3 ldrh r3, [r4, #12]
801874c: 0719 lsls r1, r3, #28
801874e: d502 bpl.n 8018756 <_puts_r+0x2e>
8018750: 6923 ldr r3, [r4, #16]
8018752: 2b00 cmp r3, #0
8018754: d135 bne.n 80187c2 <_puts_r+0x9a>
8018756: 4621 mov r1, r4
8018758: 4628 mov r0, r5
801875a: f000 f8e7 bl 801892c <__swsetup_r>
801875e: b380 cbz r0, 80187c2 <_puts_r+0x9a>
8018760: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff
8018764: 6e63 ldr r3, [r4, #100] @ 0x64
8018766: 07da lsls r2, r3, #31
8018768: d405 bmi.n 8018776 <_puts_r+0x4e>
801876a: 89a3 ldrh r3, [r4, #12]
801876c: 059b lsls r3, r3, #22
801876e: d402 bmi.n 8018776 <_puts_r+0x4e>
8018770: 6da0 ldr r0, [r4, #88] @ 0x58
8018772: f000 f9ad bl 8018ad0 <__retarget_lock_release_recursive>
8018776: 4628 mov r0, r5
8018778: bd70 pop {r4, r5, r6, pc}
801877a: 2b00 cmp r3, #0
801877c: da04 bge.n 8018788 <_puts_r+0x60>
801877e: 69a2 ldr r2, [r4, #24]
8018780: 4293 cmp r3, r2
8018782: db17 blt.n 80187b4 <_puts_r+0x8c>
8018784: 290a cmp r1, #10
8018786: d015 beq.n 80187b4 <_puts_r+0x8c>
8018788: 6823 ldr r3, [r4, #0]
801878a: 1c5a adds r2, r3, #1
801878c: 6022 str r2, [r4, #0]
801878e: 7019 strb r1, [r3, #0]
8018790: 68a3 ldr r3, [r4, #8]
8018792: f816 1f01 ldrb.w r1, [r6, #1]!
8018796: 3b01 subs r3, #1
8018798: 60a3 str r3, [r4, #8]
801879a: 2900 cmp r1, #0
801879c: d1ed bne.n 801877a <_puts_r+0x52>
801879e: 2b00 cmp r3, #0
80187a0: da11 bge.n 80187c6 <_puts_r+0x9e>
80187a2: 4622 mov r2, r4
80187a4: 210a movs r1, #10
80187a6: 4628 mov r0, r5
80187a8: f000 f882 bl 80188b0 <__swbuf_r>
80187ac: 3001 adds r0, #1
80187ae: d0d7 beq.n 8018760 <_puts_r+0x38>
80187b0: 250a movs r5, #10
80187b2: e7d7 b.n 8018764 <_puts_r+0x3c>
80187b4: 4622 mov r2, r4
80187b6: 4628 mov r0, r5
80187b8: f000 f87a bl 80188b0 <__swbuf_r>
80187bc: 3001 adds r0, #1
80187be: d1e7 bne.n 8018790 <_puts_r+0x68>
80187c0: e7ce b.n 8018760 <_puts_r+0x38>
80187c2: 3e01 subs r6, #1
80187c4: e7e4 b.n 8018790 <_puts_r+0x68>
80187c6: 6823 ldr r3, [r4, #0]
80187c8: 1c5a adds r2, r3, #1
80187ca: 6022 str r2, [r4, #0]
80187cc: 220a movs r2, #10
80187ce: 701a strb r2, [r3, #0]
80187d0: e7ee b.n 80187b0 <_puts_r+0x88>
...
080187d4 <puts>:
80187d4: 4b02 ldr r3, [pc, #8] @ (80187e0 <puts+0xc>)
80187d6: 4601 mov r1, r0
80187d8: 6818 ldr r0, [r3, #0]
80187da: f7ff bfa5 b.w 8018728 <_puts_r>
80187de: bf00 nop
80187e0: 2000011c .word 0x2000011c
080187e4 <siprintf>:
80187e4: b40e push {r1, r2, r3}
80187e6: b510 push {r4, lr}
80187e8: b09d sub sp, #116 @ 0x74
80187ea: ab1f add r3, sp, #124 @ 0x7c
80187ec: 9002 str r0, [sp, #8]
80187ee: 9006 str r0, [sp, #24]
80187f0: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
80187f4: 480a ldr r0, [pc, #40] @ (8018820 <siprintf+0x3c>)
80187f6: 9107 str r1, [sp, #28]
80187f8: 9104 str r1, [sp, #16]
80187fa: 490a ldr r1, [pc, #40] @ (8018824 <siprintf+0x40>)
80187fc: f853 2b04 ldr.w r2, [r3], #4
8018800: 9105 str r1, [sp, #20]
8018802: 2400 movs r4, #0
8018804: a902 add r1, sp, #8
8018806: 6800 ldr r0, [r0, #0]
8018808: 9301 str r3, [sp, #4]
801880a: 941b str r4, [sp, #108] @ 0x6c
801880c: f002 fc72 bl 801b0f4 <_svfiprintf_r>
8018810: 9b02 ldr r3, [sp, #8]
8018812: 701c strb r4, [r3, #0]
8018814: b01d add sp, #116 @ 0x74
8018816: e8bd 4010 ldmia.w sp!, {r4, lr}
801881a: b003 add sp, #12
801881c: 4770 bx lr
801881e: bf00 nop
8018820: 2000011c .word 0x2000011c
8018824: ffff0208 .word 0xffff0208
08018828 <__sread>:
8018828: b510 push {r4, lr}
801882a: 460c mov r4, r1
801882c: f9b1 100e ldrsh.w r1, [r1, #14]
8018830: f000 f8fe bl 8018a30 <_read_r>
8018834: 2800 cmp r0, #0
8018836: bfab itete ge
8018838: 6d63 ldrge r3, [r4, #84] @ 0x54
801883a: 89a3 ldrhlt r3, [r4, #12]
801883c: 181b addge r3, r3, r0
801883e: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
8018842: bfac ite ge
8018844: 6563 strge r3, [r4, #84] @ 0x54
8018846: 81a3 strhlt r3, [r4, #12]
8018848: bd10 pop {r4, pc}
0801884a <__swrite>:
801884a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801884e: 461f mov r7, r3
8018850: 898b ldrh r3, [r1, #12]
8018852: 05db lsls r3, r3, #23
8018854: 4605 mov r5, r0
8018856: 460c mov r4, r1
8018858: 4616 mov r6, r2
801885a: d505 bpl.n 8018868 <__swrite+0x1e>
801885c: f9b1 100e ldrsh.w r1, [r1, #14]
8018860: 2302 movs r3, #2
8018862: 2200 movs r2, #0
8018864: f000 f8d2 bl 8018a0c <_lseek_r>
8018868: 89a3 ldrh r3, [r4, #12]
801886a: f9b4 100e ldrsh.w r1, [r4, #14]
801886e: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8018872: 81a3 strh r3, [r4, #12]
8018874: 4632 mov r2, r6
8018876: 463b mov r3, r7
8018878: 4628 mov r0, r5
801887a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
801887e: f000 b8e9 b.w 8018a54 <_write_r>
08018882 <__sseek>:
8018882: b510 push {r4, lr}
8018884: 460c mov r4, r1
8018886: f9b1 100e ldrsh.w r1, [r1, #14]
801888a: f000 f8bf bl 8018a0c <_lseek_r>
801888e: f9b4 300c ldrsh.w r3, [r4, #12]
8018892: 1c42 adds r2, r0, #1
8018894: bf0b itete eq
8018896: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
801889a: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
801889e: 81a3 strheq r3, [r4, #12]
80188a0: 81a3 strhne r3, [r4, #12]
80188a2: bf18 it ne
80188a4: 6560 strne r0, [r4, #84] @ 0x54
80188a6: bd10 pop {r4, pc}
080188a8 <__sclose>:
80188a8: f9b1 100e ldrsh.w r1, [r1, #14]
80188ac: f000 b89e b.w 80189ec <_close_r>
080188b0 <__swbuf_r>:
80188b0: b5f8 push {r3, r4, r5, r6, r7, lr}
80188b2: 460e mov r6, r1
80188b4: 4614 mov r4, r2
80188b6: 4605 mov r5, r0
80188b8: b118 cbz r0, 80188c2 <__swbuf_r+0x12>
80188ba: 6a03 ldr r3, [r0, #32]
80188bc: b90b cbnz r3, 80188c2 <__swbuf_r+0x12>
80188be: f7ff feeb bl 8018698 <__sinit>
80188c2: 69a3 ldr r3, [r4, #24]
80188c4: 60a3 str r3, [r4, #8]
80188c6: 89a3 ldrh r3, [r4, #12]
80188c8: 071a lsls r2, r3, #28
80188ca: d501 bpl.n 80188d0 <__swbuf_r+0x20>
80188cc: 6923 ldr r3, [r4, #16]
80188ce: b943 cbnz r3, 80188e2 <__swbuf_r+0x32>
80188d0: 4621 mov r1, r4
80188d2: 4628 mov r0, r5
80188d4: f000 f82a bl 801892c <__swsetup_r>
80188d8: b118 cbz r0, 80188e2 <__swbuf_r+0x32>
80188da: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
80188de: 4638 mov r0, r7
80188e0: bdf8 pop {r3, r4, r5, r6, r7, pc}
80188e2: 6823 ldr r3, [r4, #0]
80188e4: 6922 ldr r2, [r4, #16]
80188e6: 1a98 subs r0, r3, r2
80188e8: 6963 ldr r3, [r4, #20]
80188ea: b2f6 uxtb r6, r6
80188ec: 4283 cmp r3, r0
80188ee: 4637 mov r7, r6
80188f0: dc05 bgt.n 80188fe <__swbuf_r+0x4e>
80188f2: 4621 mov r1, r4
80188f4: 4628 mov r0, r5
80188f6: f002 feb5 bl 801b664 <_fflush_r>
80188fa: 2800 cmp r0, #0
80188fc: d1ed bne.n 80188da <__swbuf_r+0x2a>
80188fe: 68a3 ldr r3, [r4, #8]
8018900: 3b01 subs r3, #1
8018902: 60a3 str r3, [r4, #8]
8018904: 6823 ldr r3, [r4, #0]
8018906: 1c5a adds r2, r3, #1
8018908: 6022 str r2, [r4, #0]
801890a: 701e strb r6, [r3, #0]
801890c: 6962 ldr r2, [r4, #20]
801890e: 1c43 adds r3, r0, #1
8018910: 429a cmp r2, r3
8018912: d004 beq.n 801891e <__swbuf_r+0x6e>
8018914: 89a3 ldrh r3, [r4, #12]
8018916: 07db lsls r3, r3, #31
8018918: d5e1 bpl.n 80188de <__swbuf_r+0x2e>
801891a: 2e0a cmp r6, #10
801891c: d1df bne.n 80188de <__swbuf_r+0x2e>
801891e: 4621 mov r1, r4
8018920: 4628 mov r0, r5
8018922: f002 fe9f bl 801b664 <_fflush_r>
8018926: 2800 cmp r0, #0
8018928: d0d9 beq.n 80188de <__swbuf_r+0x2e>
801892a: e7d6 b.n 80188da <__swbuf_r+0x2a>
0801892c <__swsetup_r>:
801892c: b538 push {r3, r4, r5, lr}
801892e: 4b28 ldr r3, [pc, #160] @ (80189d0 <__swsetup_r+0xa4>)
8018930: 4605 mov r5, r0
8018932: 6818 ldr r0, [r3, #0]
8018934: 460c mov r4, r1
8018936: b118 cbz r0, 8018940 <__swsetup_r+0x14>
8018938: 6a03 ldr r3, [r0, #32]
801893a: b90b cbnz r3, 8018940 <__swsetup_r+0x14>
801893c: f7ff feac bl 8018698 <__sinit>
8018940: f9b4 300c ldrsh.w r3, [r4, #12]
8018944: 071a lsls r2, r3, #28
8018946: d421 bmi.n 801898c <__swsetup_r+0x60>
8018948: 06d8 lsls r0, r3, #27
801894a: d407 bmi.n 801895c <__swsetup_r+0x30>
801894c: 2209 movs r2, #9
801894e: 602a str r2, [r5, #0]
8018950: f043 0340 orr.w r3, r3, #64 @ 0x40
8018954: 81a3 strh r3, [r4, #12]
8018956: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
801895a: e030 b.n 80189be <__swsetup_r+0x92>
801895c: 0759 lsls r1, r3, #29
801895e: d512 bpl.n 8018986 <__swsetup_r+0x5a>
8018960: 6b61 ldr r1, [r4, #52] @ 0x34
8018962: b141 cbz r1, 8018976 <__swsetup_r+0x4a>
8018964: f104 0344 add.w r3, r4, #68 @ 0x44
8018968: 4299 cmp r1, r3
801896a: d002 beq.n 8018972 <__swsetup_r+0x46>
801896c: 4628 mov r0, r5
801896e: f000 ff2b bl 80197c8 <_free_r>
8018972: 2300 movs r3, #0
8018974: 6363 str r3, [r4, #52] @ 0x34
8018976: 2200 movs r2, #0
8018978: f9b4 300c ldrsh.w r3, [r4, #12]
801897c: 6062 str r2, [r4, #4]
801897e: 6922 ldr r2, [r4, #16]
8018980: 6022 str r2, [r4, #0]
8018982: f023 0324 bic.w r3, r3, #36 @ 0x24
8018986: f043 0308 orr.w r3, r3, #8
801898a: 81a3 strh r3, [r4, #12]
801898c: 6922 ldr r2, [r4, #16]
801898e: b93a cbnz r2, 80189a0 <__swsetup_r+0x74>
8018990: 059a lsls r2, r3, #22
8018992: d501 bpl.n 8018998 <__swsetup_r+0x6c>
8018994: 0618 lsls r0, r3, #24
8018996: d503 bpl.n 80189a0 <__swsetup_r+0x74>
8018998: 4621 mov r1, r4
801899a: 4628 mov r0, r5
801899c: f002 feae bl 801b6fc <__smakebuf_r>
80189a0: f9b4 300c ldrsh.w r3, [r4, #12]
80189a4: f013 0201 ands.w r2, r3, #1
80189a8: d00a beq.n 80189c0 <__swsetup_r+0x94>
80189aa: 2200 movs r2, #0
80189ac: 60a2 str r2, [r4, #8]
80189ae: 6962 ldr r2, [r4, #20]
80189b0: 4252 negs r2, r2
80189b2: 61a2 str r2, [r4, #24]
80189b4: 6922 ldr r2, [r4, #16]
80189b6: b942 cbnz r2, 80189ca <__swsetup_r+0x9e>
80189b8: f013 0080 ands.w r0, r3, #128 @ 0x80
80189bc: d1c8 bne.n 8018950 <__swsetup_r+0x24>
80189be: bd38 pop {r3, r4, r5, pc}
80189c0: 0799 lsls r1, r3, #30
80189c2: bf58 it pl
80189c4: 6962 ldrpl r2, [r4, #20]
80189c6: 60a2 str r2, [r4, #8]
80189c8: e7f4 b.n 80189b4 <__swsetup_r+0x88>
80189ca: 2000 movs r0, #0
80189cc: e7f7 b.n 80189be <__swsetup_r+0x92>
80189ce: bf00 nop
80189d0: 2000011c .word 0x2000011c
080189d4 <memset>:
80189d4: 4402 add r2, r0
80189d6: 4603 mov r3, r0
80189d8: 4293 cmp r3, r2
80189da: d100 bne.n 80189de <memset+0xa>
80189dc: 4770 bx lr
80189de: f803 1b01 strb.w r1, [r3], #1
80189e2: e7f9 b.n 80189d8 <memset+0x4>
080189e4 <_localeconv_r>:
80189e4: 4800 ldr r0, [pc, #0] @ (80189e8 <_localeconv_r+0x4>)
80189e6: 4770 bx lr
80189e8: 2000025c .word 0x2000025c
080189ec <_close_r>:
80189ec: b538 push {r3, r4, r5, lr}
80189ee: 4d06 ldr r5, [pc, #24] @ (8018a08 <_close_r+0x1c>)
80189f0: 2300 movs r3, #0
80189f2: 4604 mov r4, r0
80189f4: 4608 mov r0, r1
80189f6: 602b str r3, [r5, #0]
80189f8: f7ec fb8a bl 8005110 <_close>
80189fc: 1c43 adds r3, r0, #1
80189fe: d102 bne.n 8018a06 <_close_r+0x1a>
8018a00: 682b ldr r3, [r5, #0]
8018a02: b103 cbz r3, 8018a06 <_close_r+0x1a>
8018a04: 6023 str r3, [r4, #0]
8018a06: bd38 pop {r3, r4, r5, pc}
8018a08: 20013c38 .word 0x20013c38
08018a0c <_lseek_r>:
8018a0c: b538 push {r3, r4, r5, lr}
8018a0e: 4d07 ldr r5, [pc, #28] @ (8018a2c <_lseek_r+0x20>)
8018a10: 4604 mov r4, r0
8018a12: 4608 mov r0, r1
8018a14: 4611 mov r1, r2
8018a16: 2200 movs r2, #0
8018a18: 602a str r2, [r5, #0]
8018a1a: 461a mov r2, r3
8018a1c: f7ec fb9f bl 800515e <_lseek>
8018a20: 1c43 adds r3, r0, #1
8018a22: d102 bne.n 8018a2a <_lseek_r+0x1e>
8018a24: 682b ldr r3, [r5, #0]
8018a26: b103 cbz r3, 8018a2a <_lseek_r+0x1e>
8018a28: 6023 str r3, [r4, #0]
8018a2a: bd38 pop {r3, r4, r5, pc}
8018a2c: 20013c38 .word 0x20013c38
08018a30 <_read_r>:
8018a30: b538 push {r3, r4, r5, lr}
8018a32: 4d07 ldr r5, [pc, #28] @ (8018a50 <_read_r+0x20>)
8018a34: 4604 mov r4, r0
8018a36: 4608 mov r0, r1
8018a38: 4611 mov r1, r2
8018a3a: 2200 movs r2, #0
8018a3c: 602a str r2, [r5, #0]
8018a3e: 461a mov r2, r3
8018a40: f7ec fb49 bl 80050d6 <_read>
8018a44: 1c43 adds r3, r0, #1
8018a46: d102 bne.n 8018a4e <_read_r+0x1e>
8018a48: 682b ldr r3, [r5, #0]
8018a4a: b103 cbz r3, 8018a4e <_read_r+0x1e>
8018a4c: 6023 str r3, [r4, #0]
8018a4e: bd38 pop {r3, r4, r5, pc}
8018a50: 20013c38 .word 0x20013c38
08018a54 <_write_r>:
8018a54: b538 push {r3, r4, r5, lr}
8018a56: 4d07 ldr r5, [pc, #28] @ (8018a74 <_write_r+0x20>)
8018a58: 4604 mov r4, r0
8018a5a: 4608 mov r0, r1
8018a5c: 4611 mov r1, r2
8018a5e: 2200 movs r2, #0
8018a60: 602a str r2, [r5, #0]
8018a62: 461a mov r2, r3
8018a64: f7ea ff06 bl 8003874 <_write>
8018a68: 1c43 adds r3, r0, #1
8018a6a: d102 bne.n 8018a72 <_write_r+0x1e>
8018a6c: 682b ldr r3, [r5, #0]
8018a6e: b103 cbz r3, 8018a72 <_write_r+0x1e>
8018a70: 6023 str r3, [r4, #0]
8018a72: bd38 pop {r3, r4, r5, pc}
8018a74: 20013c38 .word 0x20013c38
08018a78 <__errno>:
8018a78: 4b01 ldr r3, [pc, #4] @ (8018a80 <__errno+0x8>)
8018a7a: 6818 ldr r0, [r3, #0]
8018a7c: 4770 bx lr
8018a7e: bf00 nop
8018a80: 2000011c .word 0x2000011c
08018a84 <__libc_init_array>:
8018a84: b570 push {r4, r5, r6, lr}
8018a86: 4b0d ldr r3, [pc, #52] @ (8018abc <__libc_init_array+0x38>)
8018a88: 4d0d ldr r5, [pc, #52] @ (8018ac0 <__libc_init_array+0x3c>)
8018a8a: 1b5b subs r3, r3, r5
8018a8c: 109c asrs r4, r3, #2
8018a8e: 2600 movs r6, #0
8018a90: 42a6 cmp r6, r4
8018a92: d109 bne.n 8018aa8 <__libc_init_array+0x24>
8018a94: f003 faf0 bl 801c078 <_init>
8018a98: 4d0a ldr r5, [pc, #40] @ (8018ac4 <__libc_init_array+0x40>)
8018a9a: 4b0b ldr r3, [pc, #44] @ (8018ac8 <__libc_init_array+0x44>)
8018a9c: 1b5b subs r3, r3, r5
8018a9e: 109c asrs r4, r3, #2
8018aa0: 2600 movs r6, #0
8018aa2: 42a6 cmp r6, r4
8018aa4: d105 bne.n 8018ab2 <__libc_init_array+0x2e>
8018aa6: bd70 pop {r4, r5, r6, pc}
8018aa8: f855 3b04 ldr.w r3, [r5], #4
8018aac: 4798 blx r3
8018aae: 3601 adds r6, #1
8018ab0: e7ee b.n 8018a90 <__libc_init_array+0xc>
8018ab2: f855 3b04 ldr.w r3, [r5], #4
8018ab6: 4798 blx r3
8018ab8: 3601 adds r6, #1
8018aba: e7f2 b.n 8018aa2 <__libc_init_array+0x1e>
8018abc: 0801cbec .word 0x0801cbec
8018ac0: 0801cbec .word 0x0801cbec
8018ac4: 0801cbec .word 0x0801cbec
8018ac8: 0801cbf0 .word 0x0801cbf0
08018acc <__retarget_lock_init_recursive>:
8018acc: 4770 bx lr
08018ace <__retarget_lock_acquire_recursive>:
8018ace: 4770 bx lr
08018ad0 <__retarget_lock_release_recursive>:
8018ad0: 4770 bx lr
08018ad2 <memcpy>:
8018ad2: 440a add r2, r1
8018ad4: 4291 cmp r1, r2
8018ad6: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
8018ada: d100 bne.n 8018ade <memcpy+0xc>
8018adc: 4770 bx lr
8018ade: b510 push {r4, lr}
8018ae0: f811 4b01 ldrb.w r4, [r1], #1
8018ae4: f803 4f01 strb.w r4, [r3, #1]!
8018ae8: 4291 cmp r1, r2
8018aea: d1f9 bne.n 8018ae0 <memcpy+0xe>
8018aec: bd10 pop {r4, pc}
...
08018af0 <nanf>:
8018af0: ed9f 0a01 vldr s0, [pc, #4] @ 8018af8 <nanf+0x8>
8018af4: 4770 bx lr
8018af6: bf00 nop
8018af8: 7fc00000 .word 0x7fc00000
08018afc <quorem>:
8018afc: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
8018b00: 6903 ldr r3, [r0, #16]
8018b02: 690c ldr r4, [r1, #16]
8018b04: 42a3 cmp r3, r4
8018b06: 4607 mov r7, r0
8018b08: db7e blt.n 8018c08 <quorem+0x10c>
8018b0a: 3c01 subs r4, #1
8018b0c: f101 0814 add.w r8, r1, #20
8018b10: 00a3 lsls r3, r4, #2
8018b12: f100 0514 add.w r5, r0, #20
8018b16: 9300 str r3, [sp, #0]
8018b18: eb05 0384 add.w r3, r5, r4, lsl #2
8018b1c: 9301 str r3, [sp, #4]
8018b1e: f858 3024 ldr.w r3, [r8, r4, lsl #2]
8018b22: f855 2024 ldr.w r2, [r5, r4, lsl #2]
8018b26: 3301 adds r3, #1
8018b28: 429a cmp r2, r3
8018b2a: eb08 0984 add.w r9, r8, r4, lsl #2
8018b2e: fbb2 f6f3 udiv r6, r2, r3
8018b32: d32e bcc.n 8018b92 <quorem+0x96>
8018b34: f04f 0a00 mov.w sl, #0
8018b38: 46c4 mov ip, r8
8018b3a: 46ae mov lr, r5
8018b3c: 46d3 mov fp, sl
8018b3e: f85c 3b04 ldr.w r3, [ip], #4
8018b42: b298 uxth r0, r3
8018b44: fb06 a000 mla r0, r6, r0, sl
8018b48: 0c02 lsrs r2, r0, #16
8018b4a: 0c1b lsrs r3, r3, #16
8018b4c: fb06 2303 mla r3, r6, r3, r2
8018b50: f8de 2000 ldr.w r2, [lr]
8018b54: b280 uxth r0, r0
8018b56: b292 uxth r2, r2
8018b58: 1a12 subs r2, r2, r0
8018b5a: 445a add r2, fp
8018b5c: f8de 0000 ldr.w r0, [lr]
8018b60: ea4f 4a13 mov.w sl, r3, lsr #16
8018b64: b29b uxth r3, r3
8018b66: ebc3 4322 rsb r3, r3, r2, asr #16
8018b6a: eb03 4310 add.w r3, r3, r0, lsr #16
8018b6e: b292 uxth r2, r2
8018b70: ea42 4203 orr.w r2, r2, r3, lsl #16
8018b74: 45e1 cmp r9, ip
8018b76: f84e 2b04 str.w r2, [lr], #4
8018b7a: ea4f 4b23 mov.w fp, r3, asr #16
8018b7e: d2de bcs.n 8018b3e <quorem+0x42>
8018b80: 9b00 ldr r3, [sp, #0]
8018b82: 58eb ldr r3, [r5, r3]
8018b84: b92b cbnz r3, 8018b92 <quorem+0x96>
8018b86: 9b01 ldr r3, [sp, #4]
8018b88: 3b04 subs r3, #4
8018b8a: 429d cmp r5, r3
8018b8c: 461a mov r2, r3
8018b8e: d32f bcc.n 8018bf0 <quorem+0xf4>
8018b90: 613c str r4, [r7, #16]
8018b92: 4638 mov r0, r7
8018b94: f001 f9de bl 8019f54 <__mcmp>
8018b98: 2800 cmp r0, #0
8018b9a: db25 blt.n 8018be8 <quorem+0xec>
8018b9c: 4629 mov r1, r5
8018b9e: 2000 movs r0, #0
8018ba0: f858 2b04 ldr.w r2, [r8], #4
8018ba4: f8d1 c000 ldr.w ip, [r1]
8018ba8: fa1f fe82 uxth.w lr, r2
8018bac: fa1f f38c uxth.w r3, ip
8018bb0: eba3 030e sub.w r3, r3, lr
8018bb4: 4403 add r3, r0
8018bb6: 0c12 lsrs r2, r2, #16
8018bb8: ebc2 4223 rsb r2, r2, r3, asr #16
8018bbc: eb02 421c add.w r2, r2, ip, lsr #16
8018bc0: b29b uxth r3, r3
8018bc2: ea43 4302 orr.w r3, r3, r2, lsl #16
8018bc6: 45c1 cmp r9, r8
8018bc8: f841 3b04 str.w r3, [r1], #4
8018bcc: ea4f 4022 mov.w r0, r2, asr #16
8018bd0: d2e6 bcs.n 8018ba0 <quorem+0xa4>
8018bd2: f855 2024 ldr.w r2, [r5, r4, lsl #2]
8018bd6: eb05 0384 add.w r3, r5, r4, lsl #2
8018bda: b922 cbnz r2, 8018be6 <quorem+0xea>
8018bdc: 3b04 subs r3, #4
8018bde: 429d cmp r5, r3
8018be0: 461a mov r2, r3
8018be2: d30b bcc.n 8018bfc <quorem+0x100>
8018be4: 613c str r4, [r7, #16]
8018be6: 3601 adds r6, #1
8018be8: 4630 mov r0, r6
8018bea: b003 add sp, #12
8018bec: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8018bf0: 6812 ldr r2, [r2, #0]
8018bf2: 3b04 subs r3, #4
8018bf4: 2a00 cmp r2, #0
8018bf6: d1cb bne.n 8018b90 <quorem+0x94>
8018bf8: 3c01 subs r4, #1
8018bfa: e7c6 b.n 8018b8a <quorem+0x8e>
8018bfc: 6812 ldr r2, [r2, #0]
8018bfe: 3b04 subs r3, #4
8018c00: 2a00 cmp r2, #0
8018c02: d1ef bne.n 8018be4 <quorem+0xe8>
8018c04: 3c01 subs r4, #1
8018c06: e7ea b.n 8018bde <quorem+0xe2>
8018c08: 2000 movs r0, #0
8018c0a: e7ee b.n 8018bea <quorem+0xee>
8018c0c: 0000 movs r0, r0
...
08018c10 <_dtoa_r>:
8018c10: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8018c14: b099 sub sp, #100 @ 0x64
8018c16: ed8d 0b0e vstr d0, [sp, #56] @ 0x38
8018c1a: 920c str r2, [sp, #48] @ 0x30
8018c1c: 69c2 ldr r2, [r0, #28]
8018c1e: 9c22 ldr r4, [sp, #136] @ 0x88
8018c20: 910a str r1, [sp, #40] @ 0x28
8018c22: ec57 6b10 vmov r6, r7, d0
8018c26: 4681 mov r9, r0
8018c28: 9313 str r3, [sp, #76] @ 0x4c
8018c2a: b982 cbnz r2, 8018c4e <_dtoa_r+0x3e>
8018c2c: 2010 movs r0, #16
8018c2e: f000 fe15 bl 801985c <malloc>
8018c32: 4602 mov r2, r0
8018c34: f8c9 001c str.w r0, [r9, #28]
8018c38: b920 cbnz r0, 8018c44 <_dtoa_r+0x34>
8018c3a: 4bab ldr r3, [pc, #684] @ (8018ee8 <_dtoa_r+0x2d8>)
8018c3c: 21ef movs r1, #239 @ 0xef
8018c3e: 48ab ldr r0, [pc, #684] @ (8018eec <_dtoa_r+0x2dc>)
8018c40: f002 fdfa bl 801b838 <__assert_func>
8018c44: 2300 movs r3, #0
8018c46: e9c0 3301 strd r3, r3, [r0, #4]
8018c4a: 6003 str r3, [r0, #0]
8018c4c: 60c3 str r3, [r0, #12]
8018c4e: 6811 ldr r1, [r2, #0]
8018c50: b159 cbz r1, 8018c6a <_dtoa_r+0x5a>
8018c52: 6852 ldr r2, [r2, #4]
8018c54: 604a str r2, [r1, #4]
8018c56: 2301 movs r3, #1
8018c58: 4093 lsls r3, r2
8018c5a: 608b str r3, [r1, #8]
8018c5c: 4648 mov r0, r9
8018c5e: f000 fef1 bl 8019a44 <_Bfree>
8018c62: f8d9 301c ldr.w r3, [r9, #28]
8018c66: 2200 movs r2, #0
8018c68: 601a str r2, [r3, #0]
8018c6a: f1b7 0800 subs.w r8, r7, #0
8018c6e: bfb5 itete lt
8018c70: 2301 movlt r3, #1
8018c72: 2300 movge r3, #0
8018c74: 6023 strlt r3, [r4, #0]
8018c76: 6023 strge r3, [r4, #0]
8018c78: 4b9d ldr r3, [pc, #628] @ (8018ef0 <_dtoa_r+0x2e0>)
8018c7a: bfbc itt lt
8018c7c: f028 4800 biclt.w r8, r8, #2147483648 @ 0x80000000
8018c80: f8cd 803c strlt.w r8, [sp, #60] @ 0x3c
8018c84: ea33 0308 bics.w r3, r3, r8
8018c88: d11a bne.n 8018cc0 <_dtoa_r+0xb0>
8018c8a: 9a13 ldr r2, [sp, #76] @ 0x4c
8018c8c: f3c8 0813 ubfx r8, r8, #0, #20
8018c90: f242 730f movw r3, #9999 @ 0x270f
8018c94: ea58 0806 orrs.w r8, r8, r6
8018c98: 6013 str r3, [r2, #0]
8018c9a: f000 8568 beq.w 801976e <_dtoa_r+0xb5e>
8018c9e: 9b23 ldr r3, [sp, #140] @ 0x8c
8018ca0: b953 cbnz r3, 8018cb8 <_dtoa_r+0xa8>
8018ca2: 4b94 ldr r3, [pc, #592] @ (8018ef4 <_dtoa_r+0x2e4>)
8018ca4: e021 b.n 8018cea <_dtoa_r+0xda>
8018ca6: 4b94 ldr r3, [pc, #592] @ (8018ef8 <_dtoa_r+0x2e8>)
8018ca8: 9300 str r3, [sp, #0]
8018caa: 3308 adds r3, #8
8018cac: 9a23 ldr r2, [sp, #140] @ 0x8c
8018cae: 6013 str r3, [r2, #0]
8018cb0: 9800 ldr r0, [sp, #0]
8018cb2: b019 add sp, #100 @ 0x64
8018cb4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8018cb8: 4b8e ldr r3, [pc, #568] @ (8018ef4 <_dtoa_r+0x2e4>)
8018cba: 9300 str r3, [sp, #0]
8018cbc: 3303 adds r3, #3
8018cbe: e7f5 b.n 8018cac <_dtoa_r+0x9c>
8018cc0: ed9d 7b0e vldr d7, [sp, #56] @ 0x38
8018cc4: 2200 movs r2, #0
8018cc6: ec51 0b17 vmov r0, r1, d7
8018cca: 2300 movs r3, #0
8018ccc: ed8d 7b06 vstr d7, [sp, #24]
8018cd0: f7e7 fed2 bl 8000a78 <__aeabi_dcmpeq>
8018cd4: 4682 mov sl, r0
8018cd6: b150 cbz r0, 8018cee <_dtoa_r+0xde>
8018cd8: 9a13 ldr r2, [sp, #76] @ 0x4c
8018cda: 2301 movs r3, #1
8018cdc: 6013 str r3, [r2, #0]
8018cde: 9b23 ldr r3, [sp, #140] @ 0x8c
8018ce0: b113 cbz r3, 8018ce8 <_dtoa_r+0xd8>
8018ce2: 9a23 ldr r2, [sp, #140] @ 0x8c
8018ce4: 4b85 ldr r3, [pc, #532] @ (8018efc <_dtoa_r+0x2ec>)
8018ce6: 6013 str r3, [r2, #0]
8018ce8: 4b85 ldr r3, [pc, #532] @ (8018f00 <_dtoa_r+0x2f0>)
8018cea: 9300 str r3, [sp, #0]
8018cec: e7e0 b.n 8018cb0 <_dtoa_r+0xa0>
8018cee: ed9d 0b06 vldr d0, [sp, #24]
8018cf2: aa16 add r2, sp, #88 @ 0x58
8018cf4: a917 add r1, sp, #92 @ 0x5c
8018cf6: 4648 mov r0, r9
8018cf8: f001 fa50 bl 801a19c <__d2b>
8018cfc: ea5f 5418 movs.w r4, r8, lsr #20
8018d00: 9d16 ldr r5, [sp, #88] @ 0x58
8018d02: 9001 str r0, [sp, #4]
8018d04: d079 beq.n 8018dfa <_dtoa_r+0x1ea>
8018d06: 9b07 ldr r3, [sp, #28]
8018d08: f8cd a050 str.w sl, [sp, #80] @ 0x50
8018d0c: f3c3 0313 ubfx r3, r3, #0, #20
8018d10: e9dd 0106 ldrd r0, r1, [sp, #24]
8018d14: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000
8018d18: f443 1340 orr.w r3, r3, #3145728 @ 0x300000
8018d1c: f2a4 34ff subw r4, r4, #1023 @ 0x3ff
8018d20: 4619 mov r1, r3
8018d22: 2200 movs r2, #0
8018d24: 4b77 ldr r3, [pc, #476] @ (8018f04 <_dtoa_r+0x2f4>)
8018d26: f7e7 fa87 bl 8000238 <__aeabi_dsub>
8018d2a: a369 add r3, pc, #420 @ (adr r3, 8018ed0 <_dtoa_r+0x2c0>)
8018d2c: e9d3 2300 ldrd r2, r3, [r3]
8018d30: f7e7 fc3a bl 80005a8 <__aeabi_dmul>
8018d34: a368 add r3, pc, #416 @ (adr r3, 8018ed8 <_dtoa_r+0x2c8>)
8018d36: e9d3 2300 ldrd r2, r3, [r3]
8018d3a: f7e7 fa7f bl 800023c <__adddf3>
8018d3e: 4606 mov r6, r0
8018d40: 4620 mov r0, r4
8018d42: 460f mov r7, r1
8018d44: f7e7 fbc6 bl 80004d4 <__aeabi_i2d>
8018d48: a365 add r3, pc, #404 @ (adr r3, 8018ee0 <_dtoa_r+0x2d0>)
8018d4a: e9d3 2300 ldrd r2, r3, [r3]
8018d4e: f7e7 fc2b bl 80005a8 <__aeabi_dmul>
8018d52: 4602 mov r2, r0
8018d54: 460b mov r3, r1
8018d56: 4630 mov r0, r6
8018d58: 4639 mov r1, r7
8018d5a: f7e7 fa6f bl 800023c <__adddf3>
8018d5e: 4606 mov r6, r0
8018d60: 460f mov r7, r1
8018d62: f7e7 fed1 bl 8000b08 <__aeabi_d2iz>
8018d66: 2200 movs r2, #0
8018d68: 4680 mov r8, r0
8018d6a: 2300 movs r3, #0
8018d6c: 4630 mov r0, r6
8018d6e: 4639 mov r1, r7
8018d70: f7e7 fe8c bl 8000a8c <__aeabi_dcmplt>
8018d74: b148 cbz r0, 8018d8a <_dtoa_r+0x17a>
8018d76: 4640 mov r0, r8
8018d78: f7e7 fbac bl 80004d4 <__aeabi_i2d>
8018d7c: 4632 mov r2, r6
8018d7e: 463b mov r3, r7
8018d80: f7e7 fe7a bl 8000a78 <__aeabi_dcmpeq>
8018d84: b908 cbnz r0, 8018d8a <_dtoa_r+0x17a>
8018d86: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
8018d8a: f1b8 0f16 cmp.w r8, #22
8018d8e: d851 bhi.n 8018e34 <_dtoa_r+0x224>
8018d90: 4b5d ldr r3, [pc, #372] @ (8018f08 <_dtoa_r+0x2f8>)
8018d92: eb03 03c8 add.w r3, r3, r8, lsl #3
8018d96: e9d3 2300 ldrd r2, r3, [r3]
8018d9a: e9dd 0106 ldrd r0, r1, [sp, #24]
8018d9e: f7e7 fe75 bl 8000a8c <__aeabi_dcmplt>
8018da2: 2800 cmp r0, #0
8018da4: d048 beq.n 8018e38 <_dtoa_r+0x228>
8018da6: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
8018daa: 2300 movs r3, #0
8018dac: 9312 str r3, [sp, #72] @ 0x48
8018dae: 1b2d subs r5, r5, r4
8018db0: 1e6b subs r3, r5, #1
8018db2: 9308 str r3, [sp, #32]
8018db4: bf43 ittte mi
8018db6: 2300 movmi r3, #0
8018db8: f1c5 0701 rsbmi r7, r5, #1
8018dbc: 9308 strmi r3, [sp, #32]
8018dbe: 2700 movpl r7, #0
8018dc0: f1b8 0f00 cmp.w r8, #0
8018dc4: db3a blt.n 8018e3c <_dtoa_r+0x22c>
8018dc6: 9b08 ldr r3, [sp, #32]
8018dc8: f8cd 8034 str.w r8, [sp, #52] @ 0x34
8018dcc: 4443 add r3, r8
8018dce: 9308 str r3, [sp, #32]
8018dd0: 2300 movs r3, #0
8018dd2: 9309 str r3, [sp, #36] @ 0x24
8018dd4: 9b0a ldr r3, [sp, #40] @ 0x28
8018dd6: 2b09 cmp r3, #9
8018dd8: d862 bhi.n 8018ea0 <_dtoa_r+0x290>
8018dda: 2b05 cmp r3, #5
8018ddc: bfc4 itt gt
8018dde: 3b04 subgt r3, #4
8018de0: 930a strgt r3, [sp, #40] @ 0x28
8018de2: 9b0a ldr r3, [sp, #40] @ 0x28
8018de4: f1a3 0302 sub.w r3, r3, #2
8018de8: bfcc ite gt
8018dea: 2400 movgt r4, #0
8018dec: 2401 movle r4, #1
8018dee: 2b03 cmp r3, #3
8018df0: d862 bhi.n 8018eb8 <_dtoa_r+0x2a8>
8018df2: e8df f003 tbb [pc, r3]
8018df6: 5351 .short 0x5351
8018df8: 2b36 .short 0x2b36
8018dfa: 9c17 ldr r4, [sp, #92] @ 0x5c
8018dfc: 442c add r4, r5
8018dfe: f204 4332 addw r3, r4, #1074 @ 0x432
8018e02: 2b20 cmp r3, #32
8018e04: bfc1 itttt gt
8018e06: f1c3 0340 rsbgt r3, r3, #64 @ 0x40
8018e0a: fa08 f803 lslgt.w r8, r8, r3
8018e0e: f204 4312 addwgt r3, r4, #1042 @ 0x412
8018e12: fa26 f303 lsrgt.w r3, r6, r3
8018e16: bfd6 itet le
8018e18: f1c3 0320 rsble r3, r3, #32
8018e1c: ea48 0003 orrgt.w r0, r8, r3
8018e20: fa06 f003 lslle.w r0, r6, r3
8018e24: f7e7 fb46 bl 80004b4 <__aeabi_ui2d>
8018e28: 2201 movs r2, #1
8018e2a: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000
8018e2e: 3c01 subs r4, #1
8018e30: 9214 str r2, [sp, #80] @ 0x50
8018e32: e775 b.n 8018d20 <_dtoa_r+0x110>
8018e34: 2301 movs r3, #1
8018e36: e7b9 b.n 8018dac <_dtoa_r+0x19c>
8018e38: 9012 str r0, [sp, #72] @ 0x48
8018e3a: e7b8 b.n 8018dae <_dtoa_r+0x19e>
8018e3c: f1c8 0300 rsb r3, r8, #0
8018e40: 9309 str r3, [sp, #36] @ 0x24
8018e42: 2300 movs r3, #0
8018e44: eba7 0708 sub.w r7, r7, r8
8018e48: 930d str r3, [sp, #52] @ 0x34
8018e4a: e7c3 b.n 8018dd4 <_dtoa_r+0x1c4>
8018e4c: 2301 movs r3, #1
8018e4e: 930b str r3, [sp, #44] @ 0x2c
8018e50: 9b0c ldr r3, [sp, #48] @ 0x30
8018e52: 4443 add r3, r8
8018e54: 9305 str r3, [sp, #20]
8018e56: 3301 adds r3, #1
8018e58: 2b01 cmp r3, #1
8018e5a: 9304 str r3, [sp, #16]
8018e5c: bfb8 it lt
8018e5e: 2301 movlt r3, #1
8018e60: e006 b.n 8018e70 <_dtoa_r+0x260>
8018e62: 2301 movs r3, #1
8018e64: 930b str r3, [sp, #44] @ 0x2c
8018e66: 9b0c ldr r3, [sp, #48] @ 0x30
8018e68: 2b00 cmp r3, #0
8018e6a: dd28 ble.n 8018ebe <_dtoa_r+0x2ae>
8018e6c: e9cd 3304 strd r3, r3, [sp, #16]
8018e70: f8d9 001c ldr.w r0, [r9, #28]
8018e74: 2100 movs r1, #0
8018e76: 2204 movs r2, #4
8018e78: f102 0514 add.w r5, r2, #20
8018e7c: 429d cmp r5, r3
8018e7e: d923 bls.n 8018ec8 <_dtoa_r+0x2b8>
8018e80: 6041 str r1, [r0, #4]
8018e82: 4648 mov r0, r9
8018e84: f000 fda0 bl 80199c8 <_Balloc>
8018e88: 9000 str r0, [sp, #0]
8018e8a: 2800 cmp r0, #0
8018e8c: d140 bne.n 8018f10 <_dtoa_r+0x300>
8018e8e: 4b1f ldr r3, [pc, #124] @ (8018f0c <_dtoa_r+0x2fc>)
8018e90: 4602 mov r2, r0
8018e92: f240 11af movw r1, #431 @ 0x1af
8018e96: e6d2 b.n 8018c3e <_dtoa_r+0x2e>
8018e98: 2300 movs r3, #0
8018e9a: e7e3 b.n 8018e64 <_dtoa_r+0x254>
8018e9c: 2300 movs r3, #0
8018e9e: e7d6 b.n 8018e4e <_dtoa_r+0x23e>
8018ea0: 2401 movs r4, #1
8018ea2: 2300 movs r3, #0
8018ea4: e9cd 340a strd r3, r4, [sp, #40] @ 0x28
8018ea8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
8018eac: e9cd 3304 strd r3, r3, [sp, #16]
8018eb0: 2200 movs r2, #0
8018eb2: 2312 movs r3, #18
8018eb4: 920c str r2, [sp, #48] @ 0x30
8018eb6: e7db b.n 8018e70 <_dtoa_r+0x260>
8018eb8: 2301 movs r3, #1
8018eba: 930b str r3, [sp, #44] @ 0x2c
8018ebc: e7f4 b.n 8018ea8 <_dtoa_r+0x298>
8018ebe: 2301 movs r3, #1
8018ec0: e9cd 3304 strd r3, r3, [sp, #16]
8018ec4: 461a mov r2, r3
8018ec6: e7f5 b.n 8018eb4 <_dtoa_r+0x2a4>
8018ec8: 3101 adds r1, #1
8018eca: 0052 lsls r2, r2, #1
8018ecc: e7d4 b.n 8018e78 <_dtoa_r+0x268>
8018ece: bf00 nop
8018ed0: 636f4361 .word 0x636f4361
8018ed4: 3fd287a7 .word 0x3fd287a7
8018ed8: 8b60c8b3 .word 0x8b60c8b3
8018edc: 3fc68a28 .word 0x3fc68a28
8018ee0: 509f79fb .word 0x509f79fb
8018ee4: 3fd34413 .word 0x3fd34413
8018ee8: 0801c802 .word 0x0801c802
8018eec: 0801c819 .word 0x0801c819
8018ef0: 7ff00000 .word 0x7ff00000
8018ef4: 0801c7fe .word 0x0801c7fe
8018ef8: 0801c7f5 .word 0x0801c7f5
8018efc: 0801c7cd .word 0x0801c7cd
8018f00: 0801c7cc .word 0x0801c7cc
8018f04: 3ff80000 .word 0x3ff80000
8018f08: 0801c9c8 .word 0x0801c9c8
8018f0c: 0801c871 .word 0x0801c871
8018f10: f8d9 301c ldr.w r3, [r9, #28]
8018f14: 9a00 ldr r2, [sp, #0]
8018f16: 601a str r2, [r3, #0]
8018f18: 9b04 ldr r3, [sp, #16]
8018f1a: 2b0e cmp r3, #14
8018f1c: f200 80a1 bhi.w 8019062 <_dtoa_r+0x452>
8018f20: 2c00 cmp r4, #0
8018f22: f000 809e beq.w 8019062 <_dtoa_r+0x452>
8018f26: f1b8 0f00 cmp.w r8, #0
8018f2a: dd36 ble.n 8018f9a <_dtoa_r+0x38a>
8018f2c: 4b9e ldr r3, [pc, #632] @ (80191a8 <_dtoa_r+0x598>)
8018f2e: f008 020f and.w r2, r8, #15
8018f32: eb03 03c2 add.w r3, r3, r2, lsl #3
8018f36: f418 7f80 tst.w r8, #256 @ 0x100
8018f3a: e9d3 ab00 ldrd sl, fp, [r3]
8018f3e: ea4f 1528 mov.w r5, r8, asr #4
8018f42: d016 beq.n 8018f72 <_dtoa_r+0x362>
8018f44: 4b99 ldr r3, [pc, #612] @ (80191ac <_dtoa_r+0x59c>)
8018f46: e9dd 0106 ldrd r0, r1, [sp, #24]
8018f4a: e9d3 2308 ldrd r2, r3, [r3, #32]
8018f4e: f7e7 fc55 bl 80007fc <__aeabi_ddiv>
8018f52: e9cd 0102 strd r0, r1, [sp, #8]
8018f56: f005 050f and.w r5, r5, #15
8018f5a: 2403 movs r4, #3
8018f5c: 4e93 ldr r6, [pc, #588] @ (80191ac <_dtoa_r+0x59c>)
8018f5e: b975 cbnz r5, 8018f7e <_dtoa_r+0x36e>
8018f60: e9dd 0102 ldrd r0, r1, [sp, #8]
8018f64: 4652 mov r2, sl
8018f66: 465b mov r3, fp
8018f68: f7e7 fc48 bl 80007fc <__aeabi_ddiv>
8018f6c: 4682 mov sl, r0
8018f6e: 468b mov fp, r1
8018f70: e02d b.n 8018fce <_dtoa_r+0x3be>
8018f72: ed9d 7b06 vldr d7, [sp, #24]
8018f76: 2402 movs r4, #2
8018f78: ed8d 7b02 vstr d7, [sp, #8]
8018f7c: e7ee b.n 8018f5c <_dtoa_r+0x34c>
8018f7e: 07e9 lsls r1, r5, #31
8018f80: d508 bpl.n 8018f94 <_dtoa_r+0x384>
8018f82: 4650 mov r0, sl
8018f84: 4659 mov r1, fp
8018f86: e9d6 2300 ldrd r2, r3, [r6]
8018f8a: f7e7 fb0d bl 80005a8 <__aeabi_dmul>
8018f8e: 3401 adds r4, #1
8018f90: 4682 mov sl, r0
8018f92: 468b mov fp, r1
8018f94: 106d asrs r5, r5, #1
8018f96: 3608 adds r6, #8
8018f98: e7e1 b.n 8018f5e <_dtoa_r+0x34e>
8018f9a: f000 80ad beq.w 80190f8 <_dtoa_r+0x4e8>
8018f9e: f1c8 0500 rsb r5, r8, #0
8018fa2: 4b81 ldr r3, [pc, #516] @ (80191a8 <_dtoa_r+0x598>)
8018fa4: 4e81 ldr r6, [pc, #516] @ (80191ac <_dtoa_r+0x59c>)
8018fa6: f005 020f and.w r2, r5, #15
8018faa: eb03 03c2 add.w r3, r3, r2, lsl #3
8018fae: e9d3 2300 ldrd r2, r3, [r3]
8018fb2: e9dd 0106 ldrd r0, r1, [sp, #24]
8018fb6: f7e7 faf7 bl 80005a8 <__aeabi_dmul>
8018fba: 112d asrs r5, r5, #4
8018fbc: 4682 mov sl, r0
8018fbe: 468b mov fp, r1
8018fc0: 2300 movs r3, #0
8018fc2: 2402 movs r4, #2
8018fc4: 2d00 cmp r5, #0
8018fc6: f040 808c bne.w 80190e2 <_dtoa_r+0x4d2>
8018fca: 2b00 cmp r3, #0
8018fcc: d1ce bne.n 8018f6c <_dtoa_r+0x35c>
8018fce: 9b12 ldr r3, [sp, #72] @ 0x48
8018fd0: 2b00 cmp r3, #0
8018fd2: f000 8095 beq.w 8019100 <_dtoa_r+0x4f0>
8018fd6: 4b76 ldr r3, [pc, #472] @ (80191b0 <_dtoa_r+0x5a0>)
8018fd8: 2200 movs r2, #0
8018fda: 4650 mov r0, sl
8018fdc: 4659 mov r1, fp
8018fde: f7e7 fd55 bl 8000a8c <__aeabi_dcmplt>
8018fe2: 2800 cmp r0, #0
8018fe4: f000 808c beq.w 8019100 <_dtoa_r+0x4f0>
8018fe8: 9b04 ldr r3, [sp, #16]
8018fea: 2b00 cmp r3, #0
8018fec: f000 8088 beq.w 8019100 <_dtoa_r+0x4f0>
8018ff0: 9b05 ldr r3, [sp, #20]
8018ff2: 2b00 cmp r3, #0
8018ff4: dd35 ble.n 8019062 <_dtoa_r+0x452>
8018ff6: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff
8018ffa: 9302 str r3, [sp, #8]
8018ffc: 4650 mov r0, sl
8018ffe: 4659 mov r1, fp
8019000: 4b6c ldr r3, [pc, #432] @ (80191b4 <_dtoa_r+0x5a4>)
8019002: 2200 movs r2, #0
8019004: f7e7 fad0 bl 80005a8 <__aeabi_dmul>
8019008: 9e05 ldr r6, [sp, #20]
801900a: 4682 mov sl, r0
801900c: 468b mov fp, r1
801900e: 3401 adds r4, #1
8019010: 4620 mov r0, r4
8019012: f7e7 fa5f bl 80004d4 <__aeabi_i2d>
8019016: 4652 mov r2, sl
8019018: 465b mov r3, fp
801901a: f7e7 fac5 bl 80005a8 <__aeabi_dmul>
801901e: 4b66 ldr r3, [pc, #408] @ (80191b8 <_dtoa_r+0x5a8>)
8019020: 2200 movs r2, #0
8019022: f7e7 f90b bl 800023c <__adddf3>
8019026: 4604 mov r4, r0
8019028: f1a1 7550 sub.w r5, r1, #54525952 @ 0x3400000
801902c: e9cd 4510 strd r4, r5, [sp, #64] @ 0x40
8019030: 2e00 cmp r6, #0
8019032: d169 bne.n 8019108 <_dtoa_r+0x4f8>
8019034: 4b61 ldr r3, [pc, #388] @ (80191bc <_dtoa_r+0x5ac>)
8019036: 2200 movs r2, #0
8019038: 4650 mov r0, sl
801903a: 4659 mov r1, fp
801903c: f7e7 f8fc bl 8000238 <__aeabi_dsub>
8019040: 4622 mov r2, r4
8019042: 462b mov r3, r5
8019044: 4682 mov sl, r0
8019046: 468b mov fp, r1
8019048: f7e7 fd3e bl 8000ac8 <__aeabi_dcmpgt>
801904c: 2800 cmp r0, #0
801904e: f040 8294 bne.w 801957a <_dtoa_r+0x96a>
8019052: 4622 mov r2, r4
8019054: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000
8019058: 4650 mov r0, sl
801905a: 4659 mov r1, fp
801905c: f7e7 fd16 bl 8000a8c <__aeabi_dcmplt>
8019060: bb20 cbnz r0, 80190ac <_dtoa_r+0x49c>
8019062: 9b17 ldr r3, [sp, #92] @ 0x5c
8019064: 2b00 cmp r3, #0
8019066: f2c0 8160 blt.w 801932a <_dtoa_r+0x71a>
801906a: f1b8 0f0e cmp.w r8, #14
801906e: f300 815c bgt.w 801932a <_dtoa_r+0x71a>
8019072: 4b4d ldr r3, [pc, #308] @ (80191a8 <_dtoa_r+0x598>)
8019074: eb03 03c8 add.w r3, r3, r8, lsl #3
8019078: e9d3 ab00 ldrd sl, fp, [r3]
801907c: 9b0c ldr r3, [sp, #48] @ 0x30
801907e: 2b00 cmp r3, #0
8019080: f280 80ee bge.w 8019260 <_dtoa_r+0x650>
8019084: 9b04 ldr r3, [sp, #16]
8019086: 2b00 cmp r3, #0
8019088: f300 80ea bgt.w 8019260 <_dtoa_r+0x650>
801908c: d10e bne.n 80190ac <_dtoa_r+0x49c>
801908e: 4b4b ldr r3, [pc, #300] @ (80191bc <_dtoa_r+0x5ac>)
8019090: 2200 movs r2, #0
8019092: 4650 mov r0, sl
8019094: 4659 mov r1, fp
8019096: f7e7 fa87 bl 80005a8 <__aeabi_dmul>
801909a: 4602 mov r2, r0
801909c: 460b mov r3, r1
801909e: e9dd 0106 ldrd r0, r1, [sp, #24]
80190a2: f7e7 fcfd bl 8000aa0 <__aeabi_dcmple>
80190a6: 2800 cmp r0, #0
80190a8: f000 826a beq.w 8019580 <_dtoa_r+0x970>
80190ac: 2500 movs r5, #0
80190ae: 462c mov r4, r5
80190b0: 9b0c ldr r3, [sp, #48] @ 0x30
80190b2: 9e00 ldr r6, [sp, #0]
80190b4: 43db mvns r3, r3
80190b6: 9302 str r3, [sp, #8]
80190b8: 4627 mov r7, r4
80190ba: 2400 movs r4, #0
80190bc: 4629 mov r1, r5
80190be: 4648 mov r0, r9
80190c0: f000 fcc0 bl 8019a44 <_Bfree>
80190c4: 2f00 cmp r7, #0
80190c6: f000 80c1 beq.w 801924c <_dtoa_r+0x63c>
80190ca: b12c cbz r4, 80190d8 <_dtoa_r+0x4c8>
80190cc: 42bc cmp r4, r7
80190ce: d003 beq.n 80190d8 <_dtoa_r+0x4c8>
80190d0: 4621 mov r1, r4
80190d2: 4648 mov r0, r9
80190d4: f000 fcb6 bl 8019a44 <_Bfree>
80190d8: 4639 mov r1, r7
80190da: 4648 mov r0, r9
80190dc: f000 fcb2 bl 8019a44 <_Bfree>
80190e0: e0b4 b.n 801924c <_dtoa_r+0x63c>
80190e2: 07ea lsls r2, r5, #31
80190e4: d505 bpl.n 80190f2 <_dtoa_r+0x4e2>
80190e6: e9d6 2300 ldrd r2, r3, [r6]
80190ea: f7e7 fa5d bl 80005a8 <__aeabi_dmul>
80190ee: 3401 adds r4, #1
80190f0: 2301 movs r3, #1
80190f2: 106d asrs r5, r5, #1
80190f4: 3608 adds r6, #8
80190f6: e765 b.n 8018fc4 <_dtoa_r+0x3b4>
80190f8: e9dd ab06 ldrd sl, fp, [sp, #24]
80190fc: 2402 movs r4, #2
80190fe: e766 b.n 8018fce <_dtoa_r+0x3be>
8019100: 9e04 ldr r6, [sp, #16]
8019102: f8cd 8008 str.w r8, [sp, #8]
8019106: e783 b.n 8019010 <_dtoa_r+0x400>
8019108: 4b27 ldr r3, [pc, #156] @ (80191a8 <_dtoa_r+0x598>)
801910a: eb03 03c6 add.w r3, r3, r6, lsl #3
801910e: e953 0102 ldrd r0, r1, [r3, #-8]
8019112: 9b0b ldr r3, [sp, #44] @ 0x2c
8019114: 2b00 cmp r3, #0
8019116: d055 beq.n 80191c4 <_dtoa_r+0x5b4>
8019118: 4602 mov r2, r0
801911a: 460b mov r3, r1
801911c: 2000 movs r0, #0
801911e: 4928 ldr r1, [pc, #160] @ (80191c0 <_dtoa_r+0x5b0>)
8019120: f7e7 fb6c bl 80007fc <__aeabi_ddiv>
8019124: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
8019128: f7e7 f886 bl 8000238 <__aeabi_dsub>
801912c: 9b00 ldr r3, [sp, #0]
801912e: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40
8019132: 199d adds r5, r3, r6
8019134: 461e mov r6, r3
8019136: 4659 mov r1, fp
8019138: 4650 mov r0, sl
801913a: f7e7 fce5 bl 8000b08 <__aeabi_d2iz>
801913e: 4604 mov r4, r0
8019140: f7e7 f9c8 bl 80004d4 <__aeabi_i2d>
8019144: 4602 mov r2, r0
8019146: 460b mov r3, r1
8019148: 4650 mov r0, sl
801914a: 4659 mov r1, fp
801914c: f7e7 f874 bl 8000238 <__aeabi_dsub>
8019150: 3430 adds r4, #48 @ 0x30
8019152: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
8019156: f806 4b01 strb.w r4, [r6], #1
801915a: 4682 mov sl, r0
801915c: 468b mov fp, r1
801915e: f7e7 fc95 bl 8000a8c <__aeabi_dcmplt>
8019162: 2800 cmp r0, #0
8019164: d172 bne.n 801924c <_dtoa_r+0x63c>
8019166: 4652 mov r2, sl
8019168: 465b mov r3, fp
801916a: 4911 ldr r1, [pc, #68] @ (80191b0 <_dtoa_r+0x5a0>)
801916c: 2000 movs r0, #0
801916e: f7e7 f863 bl 8000238 <__aeabi_dsub>
8019172: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
8019176: f7e7 fc89 bl 8000a8c <__aeabi_dcmplt>
801917a: 2800 cmp r0, #0
801917c: f040 80b6 bne.w 80192ec <_dtoa_r+0x6dc>
8019180: 42ae cmp r6, r5
8019182: f43f af6e beq.w 8019062 <_dtoa_r+0x452>
8019186: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40
801918a: 4b0a ldr r3, [pc, #40] @ (80191b4 <_dtoa_r+0x5a4>)
801918c: 2200 movs r2, #0
801918e: f7e7 fa0b bl 80005a8 <__aeabi_dmul>
8019192: 4b08 ldr r3, [pc, #32] @ (80191b4 <_dtoa_r+0x5a4>)
8019194: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40
8019198: 2200 movs r2, #0
801919a: 4650 mov r0, sl
801919c: 4659 mov r1, fp
801919e: f7e7 fa03 bl 80005a8 <__aeabi_dmul>
80191a2: 4682 mov sl, r0
80191a4: 468b mov fp, r1
80191a6: e7c6 b.n 8019136 <_dtoa_r+0x526>
80191a8: 0801c9c8 .word 0x0801c9c8
80191ac: 0801c9a0 .word 0x0801c9a0
80191b0: 3ff00000 .word 0x3ff00000
80191b4: 40240000 .word 0x40240000
80191b8: 401c0000 .word 0x401c0000
80191bc: 40140000 .word 0x40140000
80191c0: 3fe00000 .word 0x3fe00000
80191c4: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
80191c8: f7e7 f9ee bl 80005a8 <__aeabi_dmul>
80191cc: 9b00 ldr r3, [sp, #0]
80191ce: 9d00 ldr r5, [sp, #0]
80191d0: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40
80191d4: 4433 add r3, r6
80191d6: 9315 str r3, [sp, #84] @ 0x54
80191d8: 4659 mov r1, fp
80191da: 4650 mov r0, sl
80191dc: f7e7 fc94 bl 8000b08 <__aeabi_d2iz>
80191e0: 4604 mov r4, r0
80191e2: f7e7 f977 bl 80004d4 <__aeabi_i2d>
80191e6: 3430 adds r4, #48 @ 0x30
80191e8: 460b mov r3, r1
80191ea: 4602 mov r2, r0
80191ec: 4659 mov r1, fp
80191ee: 4650 mov r0, sl
80191f0: f7e7 f822 bl 8000238 <__aeabi_dsub>
80191f4: f805 4b01 strb.w r4, [r5], #1
80191f8: 9b15 ldr r3, [sp, #84] @ 0x54
80191fa: 429d cmp r5, r3
80191fc: 4682 mov sl, r0
80191fe: 468b mov fp, r1
8019200: d127 bne.n 8019252 <_dtoa_r+0x642>
8019202: 9b00 ldr r3, [sp, #0]
8019204: 2200 movs r2, #0
8019206: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40
801920a: 441e add r6, r3
801920c: 4bb3 ldr r3, [pc, #716] @ (80194dc <_dtoa_r+0x8cc>)
801920e: f7e7 f815 bl 800023c <__adddf3>
8019212: 4602 mov r2, r0
8019214: 460b mov r3, r1
8019216: 4650 mov r0, sl
8019218: 4659 mov r1, fp
801921a: f7e7 fc55 bl 8000ac8 <__aeabi_dcmpgt>
801921e: 2800 cmp r0, #0
8019220: d164 bne.n 80192ec <_dtoa_r+0x6dc>
8019222: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40
8019226: 49ad ldr r1, [pc, #692] @ (80194dc <_dtoa_r+0x8cc>)
8019228: 2000 movs r0, #0
801922a: f7e7 f805 bl 8000238 <__aeabi_dsub>
801922e: 4602 mov r2, r0
8019230: 460b mov r3, r1
8019232: 4650 mov r0, sl
8019234: 4659 mov r1, fp
8019236: f7e7 fc29 bl 8000a8c <__aeabi_dcmplt>
801923a: 2800 cmp r0, #0
801923c: f43f af11 beq.w 8019062 <_dtoa_r+0x452>
8019240: 4633 mov r3, r6
8019242: f816 2d01 ldrb.w r2, [r6, #-1]!
8019246: 2a30 cmp r2, #48 @ 0x30
8019248: d0fa beq.n 8019240 <_dtoa_r+0x630>
801924a: 461e mov r6, r3
801924c: f8dd 8008 ldr.w r8, [sp, #8]
8019250: e03a b.n 80192c8 <_dtoa_r+0x6b8>
8019252: 4ba3 ldr r3, [pc, #652] @ (80194e0 <_dtoa_r+0x8d0>)
8019254: 2200 movs r2, #0
8019256: f7e7 f9a7 bl 80005a8 <__aeabi_dmul>
801925a: 4682 mov sl, r0
801925c: 468b mov fp, r1
801925e: e7bb b.n 80191d8 <_dtoa_r+0x5c8>
8019260: 9e00 ldr r6, [sp, #0]
8019262: 4652 mov r2, sl
8019264: 465b mov r3, fp
8019266: e9dd 0106 ldrd r0, r1, [sp, #24]
801926a: f7e7 fac7 bl 80007fc <__aeabi_ddiv>
801926e: f7e7 fc4b bl 8000b08 <__aeabi_d2iz>
8019272: 4607 mov r7, r0
8019274: f7e7 f92e bl 80004d4 <__aeabi_i2d>
8019278: 4652 mov r2, sl
801927a: 465b mov r3, fp
801927c: f7e7 f994 bl 80005a8 <__aeabi_dmul>
8019280: 4602 mov r2, r0
8019282: 460b mov r3, r1
8019284: e9dd 0106 ldrd r0, r1, [sp, #24]
8019288: f7e6 ffd6 bl 8000238 <__aeabi_dsub>
801928c: f107 0c30 add.w ip, r7, #48 @ 0x30
8019290: 9c00 ldr r4, [sp, #0]
8019292: f806 cb01 strb.w ip, [r6], #1
8019296: eba6 0c04 sub.w ip, r6, r4
801929a: 9c04 ldr r4, [sp, #16]
801929c: 4564 cmp r4, ip
801929e: 4602 mov r2, r0
80192a0: 460b mov r3, r1
80192a2: d133 bne.n 801930c <_dtoa_r+0x6fc>
80192a4: f7e6 ffca bl 800023c <__adddf3>
80192a8: 4652 mov r2, sl
80192aa: 465b mov r3, fp
80192ac: 4604 mov r4, r0
80192ae: 460d mov r5, r1
80192b0: f7e7 fc0a bl 8000ac8 <__aeabi_dcmpgt>
80192b4: b9c0 cbnz r0, 80192e8 <_dtoa_r+0x6d8>
80192b6: 4652 mov r2, sl
80192b8: 465b mov r3, fp
80192ba: 4620 mov r0, r4
80192bc: 4629 mov r1, r5
80192be: f7e7 fbdb bl 8000a78 <__aeabi_dcmpeq>
80192c2: b108 cbz r0, 80192c8 <_dtoa_r+0x6b8>
80192c4: 07fb lsls r3, r7, #31
80192c6: d40f bmi.n 80192e8 <_dtoa_r+0x6d8>
80192c8: 9901 ldr r1, [sp, #4]
80192ca: 4648 mov r0, r9
80192cc: f000 fbba bl 8019a44 <_Bfree>
80192d0: 2300 movs r3, #0
80192d2: 9a13 ldr r2, [sp, #76] @ 0x4c
80192d4: 7033 strb r3, [r6, #0]
80192d6: f108 0301 add.w r3, r8, #1
80192da: 6013 str r3, [r2, #0]
80192dc: 9b23 ldr r3, [sp, #140] @ 0x8c
80192de: 2b00 cmp r3, #0
80192e0: f43f ace6 beq.w 8018cb0 <_dtoa_r+0xa0>
80192e4: 601e str r6, [r3, #0]
80192e6: e4e3 b.n 8018cb0 <_dtoa_r+0xa0>
80192e8: f8cd 8008 str.w r8, [sp, #8]
80192ec: 4633 mov r3, r6
80192ee: 461e mov r6, r3
80192f0: f813 2d01 ldrb.w r2, [r3, #-1]!
80192f4: 2a39 cmp r2, #57 @ 0x39
80192f6: d106 bne.n 8019306 <_dtoa_r+0x6f6>
80192f8: 9a00 ldr r2, [sp, #0]
80192fa: 429a cmp r2, r3
80192fc: d1f7 bne.n 80192ee <_dtoa_r+0x6de>
80192fe: 9a02 ldr r2, [sp, #8]
8019300: 3201 adds r2, #1
8019302: 9202 str r2, [sp, #8]
8019304: 2230 movs r2, #48 @ 0x30
8019306: 3201 adds r2, #1
8019308: 701a strb r2, [r3, #0]
801930a: e79f b.n 801924c <_dtoa_r+0x63c>
801930c: 4b74 ldr r3, [pc, #464] @ (80194e0 <_dtoa_r+0x8d0>)
801930e: 2200 movs r2, #0
8019310: f7e7 f94a bl 80005a8 <__aeabi_dmul>
8019314: 4602 mov r2, r0
8019316: 460b mov r3, r1
8019318: e9cd 2306 strd r2, r3, [sp, #24]
801931c: 2200 movs r2, #0
801931e: 2300 movs r3, #0
8019320: f7e7 fbaa bl 8000a78 <__aeabi_dcmpeq>
8019324: 2800 cmp r0, #0
8019326: d09c beq.n 8019262 <_dtoa_r+0x652>
8019328: e7ce b.n 80192c8 <_dtoa_r+0x6b8>
801932a: 9a0b ldr r2, [sp, #44] @ 0x2c
801932c: 2a00 cmp r2, #0
801932e: f000 80e3 beq.w 80194f8 <_dtoa_r+0x8e8>
8019332: 9a0a ldr r2, [sp, #40] @ 0x28
8019334: 2a01 cmp r2, #1
8019336: f300 80c2 bgt.w 80194be <_dtoa_r+0x8ae>
801933a: 9a14 ldr r2, [sp, #80] @ 0x50
801933c: 2a00 cmp r2, #0
801933e: f000 80ba beq.w 80194b6 <_dtoa_r+0x8a6>
8019342: f203 4333 addw r3, r3, #1075 @ 0x433
8019346: 9d09 ldr r5, [sp, #36] @ 0x24
8019348: 463e mov r6, r7
801934a: 9a08 ldr r2, [sp, #32]
801934c: 2101 movs r1, #1
801934e: 441a add r2, r3
8019350: 4648 mov r0, r9
8019352: 441f add r7, r3
8019354: 9208 str r2, [sp, #32]
8019356: f000 fc73 bl 8019c40 <__i2b>
801935a: 4604 mov r4, r0
801935c: b156 cbz r6, 8019374 <_dtoa_r+0x764>
801935e: 9b08 ldr r3, [sp, #32]
8019360: 2b00 cmp r3, #0
8019362: dd07 ble.n 8019374 <_dtoa_r+0x764>
8019364: 42b3 cmp r3, r6
8019366: 9a08 ldr r2, [sp, #32]
8019368: bfa8 it ge
801936a: 4633 movge r3, r6
801936c: 1aff subs r7, r7, r3
801936e: 1af6 subs r6, r6, r3
8019370: 1ad3 subs r3, r2, r3
8019372: 9308 str r3, [sp, #32]
8019374: 9b09 ldr r3, [sp, #36] @ 0x24
8019376: b30b cbz r3, 80193bc <_dtoa_r+0x7ac>
8019378: 9b0b ldr r3, [sp, #44] @ 0x2c
801937a: 2b00 cmp r3, #0
801937c: f000 80c3 beq.w 8019506 <_dtoa_r+0x8f6>
8019380: 2d00 cmp r5, #0
8019382: f000 80bd beq.w 8019500 <_dtoa_r+0x8f0>
8019386: 4621 mov r1, r4
8019388: 462a mov r2, r5
801938a: 4648 mov r0, r9
801938c: f000 fd18 bl 8019dc0 <__pow5mult>
8019390: 9a01 ldr r2, [sp, #4]
8019392: 4601 mov r1, r0
8019394: 4604 mov r4, r0
8019396: 4648 mov r0, r9
8019398: f000 fc68 bl 8019c6c <__multiply>
801939c: 9901 ldr r1, [sp, #4]
801939e: 4682 mov sl, r0
80193a0: 4648 mov r0, r9
80193a2: f000 fb4f bl 8019a44 <_Bfree>
80193a6: 9b09 ldr r3, [sp, #36] @ 0x24
80193a8: 1b5b subs r3, r3, r5
80193aa: 9309 str r3, [sp, #36] @ 0x24
80193ac: f000 80ae beq.w 801950c <_dtoa_r+0x8fc>
80193b0: 9a09 ldr r2, [sp, #36] @ 0x24
80193b2: 4651 mov r1, sl
80193b4: 4648 mov r0, r9
80193b6: f000 fd03 bl 8019dc0 <__pow5mult>
80193ba: 9001 str r0, [sp, #4]
80193bc: 2101 movs r1, #1
80193be: 4648 mov r0, r9
80193c0: f000 fc3e bl 8019c40 <__i2b>
80193c4: 9b0d ldr r3, [sp, #52] @ 0x34
80193c6: 4605 mov r5, r0
80193c8: 2b00 cmp r3, #0
80193ca: f000 81d7 beq.w 801977c <_dtoa_r+0xb6c>
80193ce: 461a mov r2, r3
80193d0: 4601 mov r1, r0
80193d2: 4648 mov r0, r9
80193d4: f000 fcf4 bl 8019dc0 <__pow5mult>
80193d8: 9b0a ldr r3, [sp, #40] @ 0x28
80193da: 2b01 cmp r3, #1
80193dc: 4605 mov r5, r0
80193de: f300 809d bgt.w 801951c <_dtoa_r+0x90c>
80193e2: 9b0e ldr r3, [sp, #56] @ 0x38
80193e4: 2b00 cmp r3, #0
80193e6: f040 8094 bne.w 8019512 <_dtoa_r+0x902>
80193ea: 9b0f ldr r3, [sp, #60] @ 0x3c
80193ec: f3c3 0313 ubfx r3, r3, #0, #20
80193f0: 2b00 cmp r3, #0
80193f2: f040 808e bne.w 8019512 <_dtoa_r+0x902>
80193f6: 9b0f ldr r3, [sp, #60] @ 0x3c
80193f8: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
80193fc: 0d1b lsrs r3, r3, #20
80193fe: 051b lsls r3, r3, #20
8019400: 2b00 cmp r3, #0
8019402: f000 8089 beq.w 8019518 <_dtoa_r+0x908>
8019406: 9b08 ldr r3, [sp, #32]
8019408: 3301 adds r3, #1
801940a: 3701 adds r7, #1
801940c: 9308 str r3, [sp, #32]
801940e: f04f 0a01 mov.w sl, #1
8019412: 9b0d ldr r3, [sp, #52] @ 0x34
8019414: 2b00 cmp r3, #0
8019416: f000 81b7 beq.w 8019788 <_dtoa_r+0xb78>
801941a: 692b ldr r3, [r5, #16]
801941c: eb05 0383 add.w r3, r5, r3, lsl #2
8019420: 6918 ldr r0, [r3, #16]
8019422: f000 fbc1 bl 8019ba8 <__hi0bits>
8019426: f1c0 0020 rsb r0, r0, #32
801942a: 9b08 ldr r3, [sp, #32]
801942c: 4418 add r0, r3
801942e: f010 001f ands.w r0, r0, #31
8019432: d07e beq.n 8019532 <_dtoa_r+0x922>
8019434: f1c0 0320 rsb r3, r0, #32
8019438: 2b04 cmp r3, #4
801943a: dd72 ble.n 8019522 <_dtoa_r+0x912>
801943c: 9b08 ldr r3, [sp, #32]
801943e: f1c0 001c rsb r0, r0, #28
8019442: 4403 add r3, r0
8019444: 4407 add r7, r0
8019446: 4406 add r6, r0
8019448: 9308 str r3, [sp, #32]
801944a: 2f00 cmp r7, #0
801944c: dd05 ble.n 801945a <_dtoa_r+0x84a>
801944e: 9901 ldr r1, [sp, #4]
8019450: 463a mov r2, r7
8019452: 4648 mov r0, r9
8019454: f000 fd10 bl 8019e78 <__lshift>
8019458: 9001 str r0, [sp, #4]
801945a: 9b08 ldr r3, [sp, #32]
801945c: 2b00 cmp r3, #0
801945e: dd05 ble.n 801946c <_dtoa_r+0x85c>
8019460: 4629 mov r1, r5
8019462: 461a mov r2, r3
8019464: 4648 mov r0, r9
8019466: f000 fd07 bl 8019e78 <__lshift>
801946a: 4605 mov r5, r0
801946c: 9b12 ldr r3, [sp, #72] @ 0x48
801946e: 2b00 cmp r3, #0
8019470: d061 beq.n 8019536 <_dtoa_r+0x926>
8019472: 9801 ldr r0, [sp, #4]
8019474: 4629 mov r1, r5
8019476: f000 fd6d bl 8019f54 <__mcmp>
801947a: 2800 cmp r0, #0
801947c: da5b bge.n 8019536 <_dtoa_r+0x926>
801947e: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff
8019482: 9302 str r3, [sp, #8]
8019484: 9901 ldr r1, [sp, #4]
8019486: 2300 movs r3, #0
8019488: 220a movs r2, #10
801948a: 4648 mov r0, r9
801948c: f000 fafc bl 8019a88 <__multadd>
8019490: 9b0b ldr r3, [sp, #44] @ 0x2c
8019492: 9001 str r0, [sp, #4]
8019494: 2b00 cmp r3, #0
8019496: f000 8179 beq.w 801978c <_dtoa_r+0xb7c>
801949a: 2300 movs r3, #0
801949c: 4621 mov r1, r4
801949e: 220a movs r2, #10
80194a0: 4648 mov r0, r9
80194a2: f000 faf1 bl 8019a88 <__multadd>
80194a6: 9b05 ldr r3, [sp, #20]
80194a8: 2b00 cmp r3, #0
80194aa: 4604 mov r4, r0
80194ac: dc72 bgt.n 8019594 <_dtoa_r+0x984>
80194ae: 9b0a ldr r3, [sp, #40] @ 0x28
80194b0: 2b02 cmp r3, #2
80194b2: dc49 bgt.n 8019548 <_dtoa_r+0x938>
80194b4: e06e b.n 8019594 <_dtoa_r+0x984>
80194b6: 9b16 ldr r3, [sp, #88] @ 0x58
80194b8: f1c3 0336 rsb r3, r3, #54 @ 0x36
80194bc: e743 b.n 8019346 <_dtoa_r+0x736>
80194be: 9b04 ldr r3, [sp, #16]
80194c0: 1e5d subs r5, r3, #1
80194c2: 9b09 ldr r3, [sp, #36] @ 0x24
80194c4: 42ab cmp r3, r5
80194c6: db0d blt.n 80194e4 <_dtoa_r+0x8d4>
80194c8: 1b5d subs r5, r3, r5
80194ca: 9b04 ldr r3, [sp, #16]
80194cc: 2b00 cmp r3, #0
80194ce: f6bf af3b bge.w 8019348 <_dtoa_r+0x738>
80194d2: 9b04 ldr r3, [sp, #16]
80194d4: 1afe subs r6, r7, r3
80194d6: 2300 movs r3, #0
80194d8: e737 b.n 801934a <_dtoa_r+0x73a>
80194da: bf00 nop
80194dc: 3fe00000 .word 0x3fe00000
80194e0: 40240000 .word 0x40240000
80194e4: 9b09 ldr r3, [sp, #36] @ 0x24
80194e6: 9a0d ldr r2, [sp, #52] @ 0x34
80194e8: 9509 str r5, [sp, #36] @ 0x24
80194ea: 1aeb subs r3, r5, r3
80194ec: 441a add r2, r3
80194ee: 920d str r2, [sp, #52] @ 0x34
80194f0: 9b04 ldr r3, [sp, #16]
80194f2: 463e mov r6, r7
80194f4: 2500 movs r5, #0
80194f6: e728 b.n 801934a <_dtoa_r+0x73a>
80194f8: 9d09 ldr r5, [sp, #36] @ 0x24
80194fa: 9c0b ldr r4, [sp, #44] @ 0x2c
80194fc: 463e mov r6, r7
80194fe: e72d b.n 801935c <_dtoa_r+0x74c>
8019500: f8dd a004 ldr.w sl, [sp, #4]
8019504: e754 b.n 80193b0 <_dtoa_r+0x7a0>
8019506: 9a09 ldr r2, [sp, #36] @ 0x24
8019508: 9901 ldr r1, [sp, #4]
801950a: e753 b.n 80193b4 <_dtoa_r+0x7a4>
801950c: f8cd a004 str.w sl, [sp, #4]
8019510: e754 b.n 80193bc <_dtoa_r+0x7ac>
8019512: f04f 0a00 mov.w sl, #0
8019516: e77c b.n 8019412 <_dtoa_r+0x802>
8019518: 469a mov sl, r3
801951a: e77a b.n 8019412 <_dtoa_r+0x802>
801951c: f04f 0a00 mov.w sl, #0
8019520: e77b b.n 801941a <_dtoa_r+0x80a>
8019522: d092 beq.n 801944a <_dtoa_r+0x83a>
8019524: 9a08 ldr r2, [sp, #32]
8019526: 331c adds r3, #28
8019528: 441a add r2, r3
801952a: 441f add r7, r3
801952c: 441e add r6, r3
801952e: 9208 str r2, [sp, #32]
8019530: e78b b.n 801944a <_dtoa_r+0x83a>
8019532: 4603 mov r3, r0
8019534: e7f6 b.n 8019524 <_dtoa_r+0x914>
8019536: 9b04 ldr r3, [sp, #16]
8019538: f8cd 8008 str.w r8, [sp, #8]
801953c: 2b00 cmp r3, #0
801953e: dc23 bgt.n 8019588 <_dtoa_r+0x978>
8019540: 9305 str r3, [sp, #20]
8019542: 9b0a ldr r3, [sp, #40] @ 0x28
8019544: 2b02 cmp r3, #2
8019546: dd21 ble.n 801958c <_dtoa_r+0x97c>
8019548: 9b05 ldr r3, [sp, #20]
801954a: 2b00 cmp r3, #0
801954c: f47f adb0 bne.w 80190b0 <_dtoa_r+0x4a0>
8019550: 4629 mov r1, r5
8019552: 2205 movs r2, #5
8019554: 4648 mov r0, r9
8019556: f000 fa97 bl 8019a88 <__multadd>
801955a: 4601 mov r1, r0
801955c: 4605 mov r5, r0
801955e: 9801 ldr r0, [sp, #4]
8019560: f000 fcf8 bl 8019f54 <__mcmp>
8019564: 2800 cmp r0, #0
8019566: f77f ada3 ble.w 80190b0 <_dtoa_r+0x4a0>
801956a: 9e00 ldr r6, [sp, #0]
801956c: 2331 movs r3, #49 @ 0x31
801956e: f806 3b01 strb.w r3, [r6], #1
8019572: 9b02 ldr r3, [sp, #8]
8019574: 3301 adds r3, #1
8019576: 9302 str r3, [sp, #8]
8019578: e59e b.n 80190b8 <_dtoa_r+0x4a8>
801957a: 4635 mov r5, r6
801957c: 462c mov r4, r5
801957e: e7f4 b.n 801956a <_dtoa_r+0x95a>
8019580: 9d04 ldr r5, [sp, #16]
8019582: f8cd 8008 str.w r8, [sp, #8]
8019586: e7f9 b.n 801957c <_dtoa_r+0x96c>
8019588: 9b04 ldr r3, [sp, #16]
801958a: 9305 str r3, [sp, #20]
801958c: 9b0b ldr r3, [sp, #44] @ 0x2c
801958e: 2b00 cmp r3, #0
8019590: f000 8100 beq.w 8019794 <_dtoa_r+0xb84>
8019594: 2e00 cmp r6, #0
8019596: dd05 ble.n 80195a4 <_dtoa_r+0x994>
8019598: 4621 mov r1, r4
801959a: 4632 mov r2, r6
801959c: 4648 mov r0, r9
801959e: f000 fc6b bl 8019e78 <__lshift>
80195a2: 4604 mov r4, r0
80195a4: f1ba 0f00 cmp.w sl, #0
80195a8: d05a beq.n 8019660 <_dtoa_r+0xa50>
80195aa: 6861 ldr r1, [r4, #4]
80195ac: 4648 mov r0, r9
80195ae: f000 fa0b bl 80199c8 <_Balloc>
80195b2: 4606 mov r6, r0
80195b4: b928 cbnz r0, 80195c2 <_dtoa_r+0x9b2>
80195b6: 4b82 ldr r3, [pc, #520] @ (80197c0 <_dtoa_r+0xbb0>)
80195b8: 4602 mov r2, r0
80195ba: f240 21ef movw r1, #751 @ 0x2ef
80195be: f7ff bb3e b.w 8018c3e <_dtoa_r+0x2e>
80195c2: 6922 ldr r2, [r4, #16]
80195c4: 3202 adds r2, #2
80195c6: 0092 lsls r2, r2, #2
80195c8: f104 010c add.w r1, r4, #12
80195cc: 300c adds r0, #12
80195ce: f7ff fa80 bl 8018ad2 <memcpy>
80195d2: 2201 movs r2, #1
80195d4: 4631 mov r1, r6
80195d6: 4648 mov r0, r9
80195d8: f000 fc4e bl 8019e78 <__lshift>
80195dc: 4607 mov r7, r0
80195de: 9b00 ldr r3, [sp, #0]
80195e0: 9a00 ldr r2, [sp, #0]
80195e2: f103 0b01 add.w fp, r3, #1
80195e6: 9b05 ldr r3, [sp, #20]
80195e8: 4413 add r3, r2
80195ea: 9306 str r3, [sp, #24]
80195ec: 9b0e ldr r3, [sp, #56] @ 0x38
80195ee: f003 0301 and.w r3, r3, #1
80195f2: 9308 str r3, [sp, #32]
80195f4: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff
80195f8: 4629 mov r1, r5
80195fa: 9801 ldr r0, [sp, #4]
80195fc: 9304 str r3, [sp, #16]
80195fe: f7ff fa7d bl 8018afc <quorem>
8019602: 4621 mov r1, r4
8019604: 9005 str r0, [sp, #20]
8019606: f100 0a30 add.w sl, r0, #48 @ 0x30
801960a: 9801 ldr r0, [sp, #4]
801960c: f000 fca2 bl 8019f54 <__mcmp>
8019610: 463a mov r2, r7
8019612: 4680 mov r8, r0
8019614: 4629 mov r1, r5
8019616: 4648 mov r0, r9
8019618: f000 fcb8 bl 8019f8c <__mdiff>
801961c: 68c2 ldr r2, [r0, #12]
801961e: 4606 mov r6, r0
8019620: bb02 cbnz r2, 8019664 <_dtoa_r+0xa54>
8019622: 4601 mov r1, r0
8019624: 9801 ldr r0, [sp, #4]
8019626: f000 fc95 bl 8019f54 <__mcmp>
801962a: 4602 mov r2, r0
801962c: 4631 mov r1, r6
801962e: 4648 mov r0, r9
8019630: 9209 str r2, [sp, #36] @ 0x24
8019632: f000 fa07 bl 8019a44 <_Bfree>
8019636: e9dd 2309 ldrd r2, r3, [sp, #36] @ 0x24
801963a: ea42 0103 orr.w r1, r2, r3
801963e: 9b08 ldr r3, [sp, #32]
8019640: 4319 orrs r1, r3
8019642: 465e mov r6, fp
8019644: d110 bne.n 8019668 <_dtoa_r+0xa58>
8019646: f1ba 0f39 cmp.w sl, #57 @ 0x39
801964a: d02b beq.n 80196a4 <_dtoa_r+0xa94>
801964c: f1b8 0f00 cmp.w r8, #0
8019650: dd02 ble.n 8019658 <_dtoa_r+0xa48>
8019652: 9b05 ldr r3, [sp, #20]
8019654: f103 0a31 add.w sl, r3, #49 @ 0x31
8019658: 9b04 ldr r3, [sp, #16]
801965a: f883 a000 strb.w sl, [r3]
801965e: e52d b.n 80190bc <_dtoa_r+0x4ac>
8019660: 4627 mov r7, r4
8019662: e7bc b.n 80195de <_dtoa_r+0x9ce>
8019664: 2201 movs r2, #1
8019666: e7e1 b.n 801962c <_dtoa_r+0xa1c>
8019668: f1b8 0f00 cmp.w r8, #0
801966c: db06 blt.n 801967c <_dtoa_r+0xa6c>
801966e: 9b0a ldr r3, [sp, #40] @ 0x28
8019670: ea48 0803 orr.w r8, r8, r3
8019674: 9b08 ldr r3, [sp, #32]
8019676: ea58 0803 orrs.w r8, r8, r3
801967a: d120 bne.n 80196be <_dtoa_r+0xaae>
801967c: 2a00 cmp r2, #0
801967e: ddeb ble.n 8019658 <_dtoa_r+0xa48>
8019680: 9901 ldr r1, [sp, #4]
8019682: 2201 movs r2, #1
8019684: 4648 mov r0, r9
8019686: f000 fbf7 bl 8019e78 <__lshift>
801968a: 4629 mov r1, r5
801968c: 9001 str r0, [sp, #4]
801968e: f000 fc61 bl 8019f54 <__mcmp>
8019692: 2800 cmp r0, #0
8019694: dc03 bgt.n 801969e <_dtoa_r+0xa8e>
8019696: d1df bne.n 8019658 <_dtoa_r+0xa48>
8019698: f01a 0f01 tst.w sl, #1
801969c: d0dc beq.n 8019658 <_dtoa_r+0xa48>
801969e: f1ba 0f39 cmp.w sl, #57 @ 0x39
80196a2: d1d6 bne.n 8019652 <_dtoa_r+0xa42>
80196a4: 9a04 ldr r2, [sp, #16]
80196a6: 2339 movs r3, #57 @ 0x39
80196a8: 7013 strb r3, [r2, #0]
80196aa: 4633 mov r3, r6
80196ac: 461e mov r6, r3
80196ae: 3b01 subs r3, #1
80196b0: f816 2c01 ldrb.w r2, [r6, #-1]
80196b4: 2a39 cmp r2, #57 @ 0x39
80196b6: d052 beq.n 801975e <_dtoa_r+0xb4e>
80196b8: 3201 adds r2, #1
80196ba: 701a strb r2, [r3, #0]
80196bc: e4fe b.n 80190bc <_dtoa_r+0x4ac>
80196be: 2a00 cmp r2, #0
80196c0: dd07 ble.n 80196d2 <_dtoa_r+0xac2>
80196c2: f1ba 0f39 cmp.w sl, #57 @ 0x39
80196c6: d0ed beq.n 80196a4 <_dtoa_r+0xa94>
80196c8: 9a04 ldr r2, [sp, #16]
80196ca: f10a 0301 add.w r3, sl, #1
80196ce: 7013 strb r3, [r2, #0]
80196d0: e4f4 b.n 80190bc <_dtoa_r+0x4ac>
80196d2: 9b06 ldr r3, [sp, #24]
80196d4: f80b ac01 strb.w sl, [fp, #-1]
80196d8: 455b cmp r3, fp
80196da: d02a beq.n 8019732 <_dtoa_r+0xb22>
80196dc: 9901 ldr r1, [sp, #4]
80196de: 2300 movs r3, #0
80196e0: 220a movs r2, #10
80196e2: 4648 mov r0, r9
80196e4: f000 f9d0 bl 8019a88 <__multadd>
80196e8: 42bc cmp r4, r7
80196ea: 9001 str r0, [sp, #4]
80196ec: f04f 0300 mov.w r3, #0
80196f0: f04f 020a mov.w r2, #10
80196f4: 4621 mov r1, r4
80196f6: 4648 mov r0, r9
80196f8: d106 bne.n 8019708 <_dtoa_r+0xaf8>
80196fa: f000 f9c5 bl 8019a88 <__multadd>
80196fe: 4604 mov r4, r0
8019700: 4607 mov r7, r0
8019702: f10b 0b01 add.w fp, fp, #1
8019706: e775 b.n 80195f4 <_dtoa_r+0x9e4>
8019708: f000 f9be bl 8019a88 <__multadd>
801970c: 4639 mov r1, r7
801970e: 4604 mov r4, r0
8019710: 2300 movs r3, #0
8019712: 220a movs r2, #10
8019714: 4648 mov r0, r9
8019716: f000 f9b7 bl 8019a88 <__multadd>
801971a: 4607 mov r7, r0
801971c: e7f1 b.n 8019702 <_dtoa_r+0xaf2>
801971e: 9b05 ldr r3, [sp, #20]
8019720: 1e5e subs r6, r3, #1
8019722: 2b00 cmp r3, #0
8019724: 9b00 ldr r3, [sp, #0]
8019726: bfd8 it le
8019728: 2600 movle r6, #0
801972a: 1c5a adds r2, r3, #1
801972c: 4627 mov r7, r4
801972e: 4416 add r6, r2
8019730: 2400 movs r4, #0
8019732: 9901 ldr r1, [sp, #4]
8019734: 2201 movs r2, #1
8019736: 4648 mov r0, r9
8019738: f000 fb9e bl 8019e78 <__lshift>
801973c: 4629 mov r1, r5
801973e: 9001 str r0, [sp, #4]
8019740: f000 fc08 bl 8019f54 <__mcmp>
8019744: 2800 cmp r0, #0
8019746: dcb0 bgt.n 80196aa <_dtoa_r+0xa9a>
8019748: d102 bne.n 8019750 <_dtoa_r+0xb40>
801974a: f01a 0f01 tst.w sl, #1
801974e: d1ac bne.n 80196aa <_dtoa_r+0xa9a>
8019750: 4633 mov r3, r6
8019752: 461e mov r6, r3
8019754: f813 2d01 ldrb.w r2, [r3, #-1]!
8019758: 2a30 cmp r2, #48 @ 0x30
801975a: d0fa beq.n 8019752 <_dtoa_r+0xb42>
801975c: e4ae b.n 80190bc <_dtoa_r+0x4ac>
801975e: 9a00 ldr r2, [sp, #0]
8019760: 429a cmp r2, r3
8019762: d1a3 bne.n 80196ac <_dtoa_r+0xa9c>
8019764: 9b02 ldr r3, [sp, #8]
8019766: 3301 adds r3, #1
8019768: 9302 str r3, [sp, #8]
801976a: 2331 movs r3, #49 @ 0x31
801976c: e7af b.n 80196ce <_dtoa_r+0xabe>
801976e: 9b23 ldr r3, [sp, #140] @ 0x8c
8019770: 2b00 cmp r3, #0
8019772: f47f aa98 bne.w 8018ca6 <_dtoa_r+0x96>
8019776: 4b13 ldr r3, [pc, #76] @ (80197c4 <_dtoa_r+0xbb4>)
8019778: f7ff bab7 b.w 8018cea <_dtoa_r+0xda>
801977c: 9b0a ldr r3, [sp, #40] @ 0x28
801977e: 2b01 cmp r3, #1
8019780: f77f ae2f ble.w 80193e2 <_dtoa_r+0x7d2>
8019784: f8dd a034 ldr.w sl, [sp, #52] @ 0x34
8019788: 2001 movs r0, #1
801978a: e64e b.n 801942a <_dtoa_r+0x81a>
801978c: 9b05 ldr r3, [sp, #20]
801978e: 2b00 cmp r3, #0
8019790: f77f aed7 ble.w 8019542 <_dtoa_r+0x932>
8019794: 9e00 ldr r6, [sp, #0]
8019796: 9801 ldr r0, [sp, #4]
8019798: 4629 mov r1, r5
801979a: f7ff f9af bl 8018afc <quorem>
801979e: f100 0a30 add.w sl, r0, #48 @ 0x30
80197a2: 9b00 ldr r3, [sp, #0]
80197a4: f806 ab01 strb.w sl, [r6], #1
80197a8: 1af2 subs r2, r6, r3
80197aa: 9b05 ldr r3, [sp, #20]
80197ac: 4293 cmp r3, r2
80197ae: ddb6 ble.n 801971e <_dtoa_r+0xb0e>
80197b0: 9901 ldr r1, [sp, #4]
80197b2: 2300 movs r3, #0
80197b4: 220a movs r2, #10
80197b6: 4648 mov r0, r9
80197b8: f000 f966 bl 8019a88 <__multadd>
80197bc: 9001 str r0, [sp, #4]
80197be: e7ea b.n 8019796 <_dtoa_r+0xb86>
80197c0: 0801c871 .word 0x0801c871
80197c4: 0801c7f5 .word 0x0801c7f5
080197c8 <_free_r>:
80197c8: b538 push {r3, r4, r5, lr}
80197ca: 4605 mov r5, r0
80197cc: 2900 cmp r1, #0
80197ce: d041 beq.n 8019854 <_free_r+0x8c>
80197d0: f851 3c04 ldr.w r3, [r1, #-4]
80197d4: 1f0c subs r4, r1, #4
80197d6: 2b00 cmp r3, #0
80197d8: bfb8 it lt
80197da: 18e4 addlt r4, r4, r3
80197dc: f000 f8e8 bl 80199b0 <__malloc_lock>
80197e0: 4a1d ldr r2, [pc, #116] @ (8019858 <_free_r+0x90>)
80197e2: 6813 ldr r3, [r2, #0]
80197e4: b933 cbnz r3, 80197f4 <_free_r+0x2c>
80197e6: 6063 str r3, [r4, #4]
80197e8: 6014 str r4, [r2, #0]
80197ea: 4628 mov r0, r5
80197ec: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
80197f0: f000 b8e4 b.w 80199bc <__malloc_unlock>
80197f4: 42a3 cmp r3, r4
80197f6: d908 bls.n 801980a <_free_r+0x42>
80197f8: 6820 ldr r0, [r4, #0]
80197fa: 1821 adds r1, r4, r0
80197fc: 428b cmp r3, r1
80197fe: bf01 itttt eq
8019800: 6819 ldreq r1, [r3, #0]
8019802: 685b ldreq r3, [r3, #4]
8019804: 1809 addeq r1, r1, r0
8019806: 6021 streq r1, [r4, #0]
8019808: e7ed b.n 80197e6 <_free_r+0x1e>
801980a: 461a mov r2, r3
801980c: 685b ldr r3, [r3, #4]
801980e: b10b cbz r3, 8019814 <_free_r+0x4c>
8019810: 42a3 cmp r3, r4
8019812: d9fa bls.n 801980a <_free_r+0x42>
8019814: 6811 ldr r1, [r2, #0]
8019816: 1850 adds r0, r2, r1
8019818: 42a0 cmp r0, r4
801981a: d10b bne.n 8019834 <_free_r+0x6c>
801981c: 6820 ldr r0, [r4, #0]
801981e: 4401 add r1, r0
8019820: 1850 adds r0, r2, r1
8019822: 4283 cmp r3, r0
8019824: 6011 str r1, [r2, #0]
8019826: d1e0 bne.n 80197ea <_free_r+0x22>
8019828: 6818 ldr r0, [r3, #0]
801982a: 685b ldr r3, [r3, #4]
801982c: 6053 str r3, [r2, #4]
801982e: 4408 add r0, r1
8019830: 6010 str r0, [r2, #0]
8019832: e7da b.n 80197ea <_free_r+0x22>
8019834: d902 bls.n 801983c <_free_r+0x74>
8019836: 230c movs r3, #12
8019838: 602b str r3, [r5, #0]
801983a: e7d6 b.n 80197ea <_free_r+0x22>
801983c: 6820 ldr r0, [r4, #0]
801983e: 1821 adds r1, r4, r0
8019840: 428b cmp r3, r1
8019842: bf04 itt eq
8019844: 6819 ldreq r1, [r3, #0]
8019846: 685b ldreq r3, [r3, #4]
8019848: 6063 str r3, [r4, #4]
801984a: bf04 itt eq
801984c: 1809 addeq r1, r1, r0
801984e: 6021 streq r1, [r4, #0]
8019850: 6054 str r4, [r2, #4]
8019852: e7ca b.n 80197ea <_free_r+0x22>
8019854: bd38 pop {r3, r4, r5, pc}
8019856: bf00 nop
8019858: 20013c44 .word 0x20013c44
0801985c <malloc>:
801985c: 4b02 ldr r3, [pc, #8] @ (8019868 <malloc+0xc>)
801985e: 4601 mov r1, r0
8019860: 6818 ldr r0, [r3, #0]
8019862: f000 b825 b.w 80198b0 <_malloc_r>
8019866: bf00 nop
8019868: 2000011c .word 0x2000011c
0801986c <sbrk_aligned>:
801986c: b570 push {r4, r5, r6, lr}
801986e: 4e0f ldr r6, [pc, #60] @ (80198ac <sbrk_aligned+0x40>)
8019870: 460c mov r4, r1
8019872: 6831 ldr r1, [r6, #0]
8019874: 4605 mov r5, r0
8019876: b911 cbnz r1, 801987e <sbrk_aligned+0x12>
8019878: f001 ffc6 bl 801b808 <_sbrk_r>
801987c: 6030 str r0, [r6, #0]
801987e: 4621 mov r1, r4
8019880: 4628 mov r0, r5
8019882: f001 ffc1 bl 801b808 <_sbrk_r>
8019886: 1c43 adds r3, r0, #1
8019888: d103 bne.n 8019892 <sbrk_aligned+0x26>
801988a: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
801988e: 4620 mov r0, r4
8019890: bd70 pop {r4, r5, r6, pc}
8019892: 1cc4 adds r4, r0, #3
8019894: f024 0403 bic.w r4, r4, #3
8019898: 42a0 cmp r0, r4
801989a: d0f8 beq.n 801988e <sbrk_aligned+0x22>
801989c: 1a21 subs r1, r4, r0
801989e: 4628 mov r0, r5
80198a0: f001 ffb2 bl 801b808 <_sbrk_r>
80198a4: 3001 adds r0, #1
80198a6: d1f2 bne.n 801988e <sbrk_aligned+0x22>
80198a8: e7ef b.n 801988a <sbrk_aligned+0x1e>
80198aa: bf00 nop
80198ac: 20013c40 .word 0x20013c40
080198b0 <_malloc_r>:
80198b0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
80198b4: 1ccd adds r5, r1, #3
80198b6: f025 0503 bic.w r5, r5, #3
80198ba: 3508 adds r5, #8
80198bc: 2d0c cmp r5, #12
80198be: bf38 it cc
80198c0: 250c movcc r5, #12
80198c2: 2d00 cmp r5, #0
80198c4: 4606 mov r6, r0
80198c6: db01 blt.n 80198cc <_malloc_r+0x1c>
80198c8: 42a9 cmp r1, r5
80198ca: d904 bls.n 80198d6 <_malloc_r+0x26>
80198cc: 230c movs r3, #12
80198ce: 6033 str r3, [r6, #0]
80198d0: 2000 movs r0, #0
80198d2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
80198d6: f8df 80d4 ldr.w r8, [pc, #212] @ 80199ac <_malloc_r+0xfc>
80198da: f000 f869 bl 80199b0 <__malloc_lock>
80198de: f8d8 3000 ldr.w r3, [r8]
80198e2: 461c mov r4, r3
80198e4: bb44 cbnz r4, 8019938 <_malloc_r+0x88>
80198e6: 4629 mov r1, r5
80198e8: 4630 mov r0, r6
80198ea: f7ff ffbf bl 801986c <sbrk_aligned>
80198ee: 1c43 adds r3, r0, #1
80198f0: 4604 mov r4, r0
80198f2: d158 bne.n 80199a6 <_malloc_r+0xf6>
80198f4: f8d8 4000 ldr.w r4, [r8]
80198f8: 4627 mov r7, r4
80198fa: 2f00 cmp r7, #0
80198fc: d143 bne.n 8019986 <_malloc_r+0xd6>
80198fe: 2c00 cmp r4, #0
8019900: d04b beq.n 801999a <_malloc_r+0xea>
8019902: 6823 ldr r3, [r4, #0]
8019904: 4639 mov r1, r7
8019906: 4630 mov r0, r6
8019908: eb04 0903 add.w r9, r4, r3
801990c: f001 ff7c bl 801b808 <_sbrk_r>
8019910: 4581 cmp r9, r0
8019912: d142 bne.n 801999a <_malloc_r+0xea>
8019914: 6821 ldr r1, [r4, #0]
8019916: 1a6d subs r5, r5, r1
8019918: 4629 mov r1, r5
801991a: 4630 mov r0, r6
801991c: f7ff ffa6 bl 801986c <sbrk_aligned>
8019920: 3001 adds r0, #1
8019922: d03a beq.n 801999a <_malloc_r+0xea>
8019924: 6823 ldr r3, [r4, #0]
8019926: 442b add r3, r5
8019928: 6023 str r3, [r4, #0]
801992a: f8d8 3000 ldr.w r3, [r8]
801992e: 685a ldr r2, [r3, #4]
8019930: bb62 cbnz r2, 801998c <_malloc_r+0xdc>
8019932: f8c8 7000 str.w r7, [r8]
8019936: e00f b.n 8019958 <_malloc_r+0xa8>
8019938: 6822 ldr r2, [r4, #0]
801993a: 1b52 subs r2, r2, r5
801993c: d420 bmi.n 8019980 <_malloc_r+0xd0>
801993e: 2a0b cmp r2, #11
8019940: d917 bls.n 8019972 <_malloc_r+0xc2>
8019942: 1961 adds r1, r4, r5
8019944: 42a3 cmp r3, r4
8019946: 6025 str r5, [r4, #0]
8019948: bf18 it ne
801994a: 6059 strne r1, [r3, #4]
801994c: 6863 ldr r3, [r4, #4]
801994e: bf08 it eq
8019950: f8c8 1000 streq.w r1, [r8]
8019954: 5162 str r2, [r4, r5]
8019956: 604b str r3, [r1, #4]
8019958: 4630 mov r0, r6
801995a: f000 f82f bl 80199bc <__malloc_unlock>
801995e: f104 000b add.w r0, r4, #11
8019962: 1d23 adds r3, r4, #4
8019964: f020 0007 bic.w r0, r0, #7
8019968: 1ac2 subs r2, r0, r3
801996a: bf1c itt ne
801996c: 1a1b subne r3, r3, r0
801996e: 50a3 strne r3, [r4, r2]
8019970: e7af b.n 80198d2 <_malloc_r+0x22>
8019972: 6862 ldr r2, [r4, #4]
8019974: 42a3 cmp r3, r4
8019976: bf0c ite eq
8019978: f8c8 2000 streq.w r2, [r8]
801997c: 605a strne r2, [r3, #4]
801997e: e7eb b.n 8019958 <_malloc_r+0xa8>
8019980: 4623 mov r3, r4
8019982: 6864 ldr r4, [r4, #4]
8019984: e7ae b.n 80198e4 <_malloc_r+0x34>
8019986: 463c mov r4, r7
8019988: 687f ldr r7, [r7, #4]
801998a: e7b6 b.n 80198fa <_malloc_r+0x4a>
801998c: 461a mov r2, r3
801998e: 685b ldr r3, [r3, #4]
8019990: 42a3 cmp r3, r4
8019992: d1fb bne.n 801998c <_malloc_r+0xdc>
8019994: 2300 movs r3, #0
8019996: 6053 str r3, [r2, #4]
8019998: e7de b.n 8019958 <_malloc_r+0xa8>
801999a: 230c movs r3, #12
801999c: 6033 str r3, [r6, #0]
801999e: 4630 mov r0, r6
80199a0: f000 f80c bl 80199bc <__malloc_unlock>
80199a4: e794 b.n 80198d0 <_malloc_r+0x20>
80199a6: 6005 str r5, [r0, #0]
80199a8: e7d6 b.n 8019958 <_malloc_r+0xa8>
80199aa: bf00 nop
80199ac: 20013c44 .word 0x20013c44
080199b0 <__malloc_lock>:
80199b0: 4801 ldr r0, [pc, #4] @ (80199b8 <__malloc_lock+0x8>)
80199b2: f7ff b88c b.w 8018ace <__retarget_lock_acquire_recursive>
80199b6: bf00 nop
80199b8: 20013c3c .word 0x20013c3c
080199bc <__malloc_unlock>:
80199bc: 4801 ldr r0, [pc, #4] @ (80199c4 <__malloc_unlock+0x8>)
80199be: f7ff b887 b.w 8018ad0 <__retarget_lock_release_recursive>
80199c2: bf00 nop
80199c4: 20013c3c .word 0x20013c3c
080199c8 <_Balloc>:
80199c8: b570 push {r4, r5, r6, lr}
80199ca: 69c4 ldr r4, [r0, #28]
80199cc: 4605 mov r5, r0
80199ce: 460e mov r6, r1
80199d0: b984 cbnz r4, 80199f4 <_Balloc+0x2c>
80199d2: 2010 movs r0, #16
80199d4: f7ff ff42 bl 801985c <malloc>
80199d8: 4604 mov r4, r0
80199da: 61e8 str r0, [r5, #28]
80199dc: b928 cbnz r0, 80199ea <_Balloc+0x22>
80199de: 4602 mov r2, r0
80199e0: 4b16 ldr r3, [pc, #88] @ (8019a3c <_Balloc+0x74>)
80199e2: 4817 ldr r0, [pc, #92] @ (8019a40 <_Balloc+0x78>)
80199e4: 216b movs r1, #107 @ 0x6b
80199e6: f001 ff27 bl 801b838 <__assert_func>
80199ea: 2300 movs r3, #0
80199ec: e9c0 3301 strd r3, r3, [r0, #4]
80199f0: 6003 str r3, [r0, #0]
80199f2: 60c3 str r3, [r0, #12]
80199f4: 68e3 ldr r3, [r4, #12]
80199f6: b953 cbnz r3, 8019a0e <_Balloc+0x46>
80199f8: 2221 movs r2, #33 @ 0x21
80199fa: 2104 movs r1, #4
80199fc: 4628 mov r0, r5
80199fe: f001 ff39 bl 801b874 <_calloc_r>
8019a02: 69eb ldr r3, [r5, #28]
8019a04: 60e0 str r0, [r4, #12]
8019a06: 68db ldr r3, [r3, #12]
8019a08: b90b cbnz r3, 8019a0e <_Balloc+0x46>
8019a0a: 2000 movs r0, #0
8019a0c: bd70 pop {r4, r5, r6, pc}
8019a0e: f853 0026 ldr.w r0, [r3, r6, lsl #2]
8019a12: b130 cbz r0, 8019a22 <_Balloc+0x5a>
8019a14: 6802 ldr r2, [r0, #0]
8019a16: f843 2026 str.w r2, [r3, r6, lsl #2]
8019a1a: 2300 movs r3, #0
8019a1c: e9c0 3303 strd r3, r3, [r0, #12]
8019a20: e7f4 b.n 8019a0c <_Balloc+0x44>
8019a22: 2101 movs r1, #1
8019a24: fa01 f406 lsl.w r4, r1, r6
8019a28: 1d62 adds r2, r4, #5
8019a2a: 0092 lsls r2, r2, #2
8019a2c: 4628 mov r0, r5
8019a2e: f001 ff21 bl 801b874 <_calloc_r>
8019a32: 2800 cmp r0, #0
8019a34: d0e9 beq.n 8019a0a <_Balloc+0x42>
8019a36: e9c0 6401 strd r6, r4, [r0, #4]
8019a3a: e7ee b.n 8019a1a <_Balloc+0x52>
8019a3c: 0801c802 .word 0x0801c802
8019a40: 0801c882 .word 0x0801c882
08019a44 <_Bfree>:
8019a44: b570 push {r4, r5, r6, lr}
8019a46: 69c6 ldr r6, [r0, #28]
8019a48: 4605 mov r5, r0
8019a4a: 460c mov r4, r1
8019a4c: b976 cbnz r6, 8019a6c <_Bfree+0x28>
8019a4e: 2010 movs r0, #16
8019a50: f7ff ff04 bl 801985c <malloc>
8019a54: 4602 mov r2, r0
8019a56: 61e8 str r0, [r5, #28]
8019a58: b920 cbnz r0, 8019a64 <_Bfree+0x20>
8019a5a: 4b09 ldr r3, [pc, #36] @ (8019a80 <_Bfree+0x3c>)
8019a5c: 4809 ldr r0, [pc, #36] @ (8019a84 <_Bfree+0x40>)
8019a5e: 218f movs r1, #143 @ 0x8f
8019a60: f001 feea bl 801b838 <__assert_func>
8019a64: e9c0 6601 strd r6, r6, [r0, #4]
8019a68: 6006 str r6, [r0, #0]
8019a6a: 60c6 str r6, [r0, #12]
8019a6c: b13c cbz r4, 8019a7e <_Bfree+0x3a>
8019a6e: 69eb ldr r3, [r5, #28]
8019a70: 6862 ldr r2, [r4, #4]
8019a72: 68db ldr r3, [r3, #12]
8019a74: f853 1022 ldr.w r1, [r3, r2, lsl #2]
8019a78: 6021 str r1, [r4, #0]
8019a7a: f843 4022 str.w r4, [r3, r2, lsl #2]
8019a7e: bd70 pop {r4, r5, r6, pc}
8019a80: 0801c802 .word 0x0801c802
8019a84: 0801c882 .word 0x0801c882
08019a88 <__multadd>:
8019a88: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8019a8c: 690d ldr r5, [r1, #16]
8019a8e: 4607 mov r7, r0
8019a90: 460c mov r4, r1
8019a92: 461e mov r6, r3
8019a94: f101 0c14 add.w ip, r1, #20
8019a98: 2000 movs r0, #0
8019a9a: f8dc 3000 ldr.w r3, [ip]
8019a9e: b299 uxth r1, r3
8019aa0: fb02 6101 mla r1, r2, r1, r6
8019aa4: 0c1e lsrs r6, r3, #16
8019aa6: 0c0b lsrs r3, r1, #16
8019aa8: fb02 3306 mla r3, r2, r6, r3
8019aac: b289 uxth r1, r1
8019aae: 3001 adds r0, #1
8019ab0: eb01 4103 add.w r1, r1, r3, lsl #16
8019ab4: 4285 cmp r5, r0
8019ab6: f84c 1b04 str.w r1, [ip], #4
8019aba: ea4f 4613 mov.w r6, r3, lsr #16
8019abe: dcec bgt.n 8019a9a <__multadd+0x12>
8019ac0: b30e cbz r6, 8019b06 <__multadd+0x7e>
8019ac2: 68a3 ldr r3, [r4, #8]
8019ac4: 42ab cmp r3, r5
8019ac6: dc19 bgt.n 8019afc <__multadd+0x74>
8019ac8: 6861 ldr r1, [r4, #4]
8019aca: 4638 mov r0, r7
8019acc: 3101 adds r1, #1
8019ace: f7ff ff7b bl 80199c8 <_Balloc>
8019ad2: 4680 mov r8, r0
8019ad4: b928 cbnz r0, 8019ae2 <__multadd+0x5a>
8019ad6: 4602 mov r2, r0
8019ad8: 4b0c ldr r3, [pc, #48] @ (8019b0c <__multadd+0x84>)
8019ada: 480d ldr r0, [pc, #52] @ (8019b10 <__multadd+0x88>)
8019adc: 21ba movs r1, #186 @ 0xba
8019ade: f001 feab bl 801b838 <__assert_func>
8019ae2: 6922 ldr r2, [r4, #16]
8019ae4: 3202 adds r2, #2
8019ae6: f104 010c add.w r1, r4, #12
8019aea: 0092 lsls r2, r2, #2
8019aec: 300c adds r0, #12
8019aee: f7fe fff0 bl 8018ad2 <memcpy>
8019af2: 4621 mov r1, r4
8019af4: 4638 mov r0, r7
8019af6: f7ff ffa5 bl 8019a44 <_Bfree>
8019afa: 4644 mov r4, r8
8019afc: eb04 0385 add.w r3, r4, r5, lsl #2
8019b00: 3501 adds r5, #1
8019b02: 615e str r6, [r3, #20]
8019b04: 6125 str r5, [r4, #16]
8019b06: 4620 mov r0, r4
8019b08: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8019b0c: 0801c871 .word 0x0801c871
8019b10: 0801c882 .word 0x0801c882
08019b14 <__s2b>:
8019b14: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8019b18: 460c mov r4, r1
8019b1a: 4615 mov r5, r2
8019b1c: 461f mov r7, r3
8019b1e: 2209 movs r2, #9
8019b20: 3308 adds r3, #8
8019b22: 4606 mov r6, r0
8019b24: fb93 f3f2 sdiv r3, r3, r2
8019b28: 2100 movs r1, #0
8019b2a: 2201 movs r2, #1
8019b2c: 429a cmp r2, r3
8019b2e: db09 blt.n 8019b44 <__s2b+0x30>
8019b30: 4630 mov r0, r6
8019b32: f7ff ff49 bl 80199c8 <_Balloc>
8019b36: b940 cbnz r0, 8019b4a <__s2b+0x36>
8019b38: 4602 mov r2, r0
8019b3a: 4b19 ldr r3, [pc, #100] @ (8019ba0 <__s2b+0x8c>)
8019b3c: 4819 ldr r0, [pc, #100] @ (8019ba4 <__s2b+0x90>)
8019b3e: 21d3 movs r1, #211 @ 0xd3
8019b40: f001 fe7a bl 801b838 <__assert_func>
8019b44: 0052 lsls r2, r2, #1
8019b46: 3101 adds r1, #1
8019b48: e7f0 b.n 8019b2c <__s2b+0x18>
8019b4a: 9b08 ldr r3, [sp, #32]
8019b4c: 6143 str r3, [r0, #20]
8019b4e: 2d09 cmp r5, #9
8019b50: f04f 0301 mov.w r3, #1
8019b54: 6103 str r3, [r0, #16]
8019b56: dd16 ble.n 8019b86 <__s2b+0x72>
8019b58: f104 0809 add.w r8, r4, #9
8019b5c: 46c1 mov r9, r8
8019b5e: 442c add r4, r5
8019b60: f819 3b01 ldrb.w r3, [r9], #1
8019b64: 4601 mov r1, r0
8019b66: 3b30 subs r3, #48 @ 0x30
8019b68: 220a movs r2, #10
8019b6a: 4630 mov r0, r6
8019b6c: f7ff ff8c bl 8019a88 <__multadd>
8019b70: 45a1 cmp r9, r4
8019b72: d1f5 bne.n 8019b60 <__s2b+0x4c>
8019b74: 44a8 add r8, r5
8019b76: f1a8 0408 sub.w r4, r8, #8
8019b7a: 1b2d subs r5, r5, r4
8019b7c: 1963 adds r3, r4, r5
8019b7e: 429f cmp r7, r3
8019b80: dc04 bgt.n 8019b8c <__s2b+0x78>
8019b82: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8019b86: 340a adds r4, #10
8019b88: 2509 movs r5, #9
8019b8a: e7f6 b.n 8019b7a <__s2b+0x66>
8019b8c: f814 3b01 ldrb.w r3, [r4], #1
8019b90: 4601 mov r1, r0
8019b92: 3b30 subs r3, #48 @ 0x30
8019b94: 220a movs r2, #10
8019b96: 4630 mov r0, r6
8019b98: f7ff ff76 bl 8019a88 <__multadd>
8019b9c: e7ee b.n 8019b7c <__s2b+0x68>
8019b9e: bf00 nop
8019ba0: 0801c871 .word 0x0801c871
8019ba4: 0801c882 .word 0x0801c882
08019ba8 <__hi0bits>:
8019ba8: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
8019bac: 4603 mov r3, r0
8019bae: bf36 itet cc
8019bb0: 0403 lslcc r3, r0, #16
8019bb2: 2000 movcs r0, #0
8019bb4: 2010 movcc r0, #16
8019bb6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8019bba: bf3c itt cc
8019bbc: 021b lslcc r3, r3, #8
8019bbe: 3008 addcc r0, #8
8019bc0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8019bc4: bf3c itt cc
8019bc6: 011b lslcc r3, r3, #4
8019bc8: 3004 addcc r0, #4
8019bca: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8019bce: bf3c itt cc
8019bd0: 009b lslcc r3, r3, #2
8019bd2: 3002 addcc r0, #2
8019bd4: 2b00 cmp r3, #0
8019bd6: db05 blt.n 8019be4 <__hi0bits+0x3c>
8019bd8: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
8019bdc: f100 0001 add.w r0, r0, #1
8019be0: bf08 it eq
8019be2: 2020 moveq r0, #32
8019be4: 4770 bx lr
08019be6 <__lo0bits>:
8019be6: 6803 ldr r3, [r0, #0]
8019be8: 4602 mov r2, r0
8019bea: f013 0007 ands.w r0, r3, #7
8019bee: d00b beq.n 8019c08 <__lo0bits+0x22>
8019bf0: 07d9 lsls r1, r3, #31
8019bf2: d421 bmi.n 8019c38 <__lo0bits+0x52>
8019bf4: 0798 lsls r0, r3, #30
8019bf6: bf49 itett mi
8019bf8: 085b lsrmi r3, r3, #1
8019bfa: 089b lsrpl r3, r3, #2
8019bfc: 2001 movmi r0, #1
8019bfe: 6013 strmi r3, [r2, #0]
8019c00: bf5c itt pl
8019c02: 6013 strpl r3, [r2, #0]
8019c04: 2002 movpl r0, #2
8019c06: 4770 bx lr
8019c08: b299 uxth r1, r3
8019c0a: b909 cbnz r1, 8019c10 <__lo0bits+0x2a>
8019c0c: 0c1b lsrs r3, r3, #16
8019c0e: 2010 movs r0, #16
8019c10: b2d9 uxtb r1, r3
8019c12: b909 cbnz r1, 8019c18 <__lo0bits+0x32>
8019c14: 3008 adds r0, #8
8019c16: 0a1b lsrs r3, r3, #8
8019c18: 0719 lsls r1, r3, #28
8019c1a: bf04 itt eq
8019c1c: 091b lsreq r3, r3, #4
8019c1e: 3004 addeq r0, #4
8019c20: 0799 lsls r1, r3, #30
8019c22: bf04 itt eq
8019c24: 089b lsreq r3, r3, #2
8019c26: 3002 addeq r0, #2
8019c28: 07d9 lsls r1, r3, #31
8019c2a: d403 bmi.n 8019c34 <__lo0bits+0x4e>
8019c2c: 085b lsrs r3, r3, #1
8019c2e: f100 0001 add.w r0, r0, #1
8019c32: d003 beq.n 8019c3c <__lo0bits+0x56>
8019c34: 6013 str r3, [r2, #0]
8019c36: 4770 bx lr
8019c38: 2000 movs r0, #0
8019c3a: 4770 bx lr
8019c3c: 2020 movs r0, #32
8019c3e: 4770 bx lr
08019c40 <__i2b>:
8019c40: b510 push {r4, lr}
8019c42: 460c mov r4, r1
8019c44: 2101 movs r1, #1
8019c46: f7ff febf bl 80199c8 <_Balloc>
8019c4a: 4602 mov r2, r0
8019c4c: b928 cbnz r0, 8019c5a <__i2b+0x1a>
8019c4e: 4b05 ldr r3, [pc, #20] @ (8019c64 <__i2b+0x24>)
8019c50: 4805 ldr r0, [pc, #20] @ (8019c68 <__i2b+0x28>)
8019c52: f240 1145 movw r1, #325 @ 0x145
8019c56: f001 fdef bl 801b838 <__assert_func>
8019c5a: 2301 movs r3, #1
8019c5c: 6144 str r4, [r0, #20]
8019c5e: 6103 str r3, [r0, #16]
8019c60: bd10 pop {r4, pc}
8019c62: bf00 nop
8019c64: 0801c871 .word 0x0801c871
8019c68: 0801c882 .word 0x0801c882
08019c6c <__multiply>:
8019c6c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8019c70: f8d1 9010 ldr.w r9, [r1, #16]
8019c74: f8d2 a010 ldr.w sl, [r2, #16]
8019c78: 45d1 cmp r9, sl
8019c7a: b085 sub sp, #20
8019c7c: 4688 mov r8, r1
8019c7e: 4614 mov r4, r2
8019c80: db04 blt.n 8019c8c <__multiply+0x20>
8019c82: 4653 mov r3, sl
8019c84: 460c mov r4, r1
8019c86: 46ca mov sl, r9
8019c88: 4690 mov r8, r2
8019c8a: 4699 mov r9, r3
8019c8c: 68a3 ldr r3, [r4, #8]
8019c8e: 6861 ldr r1, [r4, #4]
8019c90: eb0a 0609 add.w r6, sl, r9
8019c94: 42b3 cmp r3, r6
8019c96: bfb8 it lt
8019c98: 3101 addlt r1, #1
8019c9a: f7ff fe95 bl 80199c8 <_Balloc>
8019c9e: b930 cbnz r0, 8019cae <__multiply+0x42>
8019ca0: 4602 mov r2, r0
8019ca2: 4b45 ldr r3, [pc, #276] @ (8019db8 <__multiply+0x14c>)
8019ca4: 4845 ldr r0, [pc, #276] @ (8019dbc <__multiply+0x150>)
8019ca6: f44f 71b1 mov.w r1, #354 @ 0x162
8019caa: f001 fdc5 bl 801b838 <__assert_func>
8019cae: f100 0514 add.w r5, r0, #20
8019cb2: eb05 0786 add.w r7, r5, r6, lsl #2
8019cb6: 462b mov r3, r5
8019cb8: 2200 movs r2, #0
8019cba: 42bb cmp r3, r7
8019cbc: d31f bcc.n 8019cfe <__multiply+0x92>
8019cbe: f104 0c14 add.w ip, r4, #20
8019cc2: f108 0114 add.w r1, r8, #20
8019cc6: eb0c 038a add.w r3, ip, sl, lsl #2
8019cca: eb01 0289 add.w r2, r1, r9, lsl #2
8019cce: 9202 str r2, [sp, #8]
8019cd0: 1b1a subs r2, r3, r4
8019cd2: 3a15 subs r2, #21
8019cd4: f022 0203 bic.w r2, r2, #3
8019cd8: 3415 adds r4, #21
8019cda: 429c cmp r4, r3
8019cdc: bf88 it hi
8019cde: 2200 movhi r2, #0
8019ce0: 9201 str r2, [sp, #4]
8019ce2: 9a02 ldr r2, [sp, #8]
8019ce4: 9103 str r1, [sp, #12]
8019ce6: 428a cmp r2, r1
8019ce8: d80c bhi.n 8019d04 <__multiply+0x98>
8019cea: 2e00 cmp r6, #0
8019cec: dd03 ble.n 8019cf6 <__multiply+0x8a>
8019cee: f857 3d04 ldr.w r3, [r7, #-4]!
8019cf2: 2b00 cmp r3, #0
8019cf4: d05d beq.n 8019db2 <__multiply+0x146>
8019cf6: 6106 str r6, [r0, #16]
8019cf8: b005 add sp, #20
8019cfa: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8019cfe: f843 2b04 str.w r2, [r3], #4
8019d02: e7da b.n 8019cba <__multiply+0x4e>
8019d04: f8b1 a000 ldrh.w sl, [r1]
8019d08: f1ba 0f00 cmp.w sl, #0
8019d0c: d024 beq.n 8019d58 <__multiply+0xec>
8019d0e: 46e0 mov r8, ip
8019d10: 46a9 mov r9, r5
8019d12: f04f 0e00 mov.w lr, #0
8019d16: f858 2b04 ldr.w r2, [r8], #4
8019d1a: f8d9 4000 ldr.w r4, [r9]
8019d1e: fa1f fb82 uxth.w fp, r2
8019d22: b2a4 uxth r4, r4
8019d24: fb0a 440b mla r4, sl, fp, r4
8019d28: ea4f 4b12 mov.w fp, r2, lsr #16
8019d2c: f8d9 2000 ldr.w r2, [r9]
8019d30: 4474 add r4, lr
8019d32: ea4f 4e12 mov.w lr, r2, lsr #16
8019d36: fb0a e20b mla r2, sl, fp, lr
8019d3a: eb02 4214 add.w r2, r2, r4, lsr #16
8019d3e: b2a4 uxth r4, r4
8019d40: ea44 4402 orr.w r4, r4, r2, lsl #16
8019d44: 4543 cmp r3, r8
8019d46: f849 4b04 str.w r4, [r9], #4
8019d4a: ea4f 4e12 mov.w lr, r2, lsr #16
8019d4e: d8e2 bhi.n 8019d16 <__multiply+0xaa>
8019d50: 9a01 ldr r2, [sp, #4]
8019d52: 18aa adds r2, r5, r2
8019d54: f8c2 e004 str.w lr, [r2, #4]
8019d58: 9a03 ldr r2, [sp, #12]
8019d5a: f8b2 8002 ldrh.w r8, [r2, #2]
8019d5e: 3104 adds r1, #4
8019d60: f1b8 0f00 cmp.w r8, #0
8019d64: d023 beq.n 8019dae <__multiply+0x142>
8019d66: 682a ldr r2, [r5, #0]
8019d68: 46e6 mov lr, ip
8019d6a: 4691 mov r9, r2
8019d6c: 46aa mov sl, r5
8019d6e: f04f 0b00 mov.w fp, #0
8019d72: f8be 4000 ldrh.w r4, [lr]
8019d76: fb08 b404 mla r4, r8, r4, fp
8019d7a: eb04 4419 add.w r4, r4, r9, lsr #16
8019d7e: b292 uxth r2, r2
8019d80: ea42 4204 orr.w r2, r2, r4, lsl #16
8019d84: f84a 2b04 str.w r2, [sl], #4
8019d88: f85e 2b04 ldr.w r2, [lr], #4
8019d8c: f8da 9000 ldr.w r9, [sl]
8019d90: ea4f 4b12 mov.w fp, r2, lsr #16
8019d94: fa1f f289 uxth.w r2, r9
8019d98: fb08 220b mla r2, r8, fp, r2
8019d9c: eb02 4214 add.w r2, r2, r4, lsr #16
8019da0: 4573 cmp r3, lr
8019da2: ea4f 4b12 mov.w fp, r2, lsr #16
8019da6: d8e4 bhi.n 8019d72 <__multiply+0x106>
8019da8: 9c01 ldr r4, [sp, #4]
8019daa: 192c adds r4, r5, r4
8019dac: 6062 str r2, [r4, #4]
8019dae: 3504 adds r5, #4
8019db0: e797 b.n 8019ce2 <__multiply+0x76>
8019db2: 3e01 subs r6, #1
8019db4: e799 b.n 8019cea <__multiply+0x7e>
8019db6: bf00 nop
8019db8: 0801c871 .word 0x0801c871
8019dbc: 0801c882 .word 0x0801c882
08019dc0 <__pow5mult>:
8019dc0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8019dc4: 4617 mov r7, r2
8019dc6: f012 0203 ands.w r2, r2, #3
8019dca: 4680 mov r8, r0
8019dcc: 460d mov r5, r1
8019dce: d007 beq.n 8019de0 <__pow5mult+0x20>
8019dd0: 4c26 ldr r4, [pc, #152] @ (8019e6c <__pow5mult+0xac>)
8019dd2: 3a01 subs r2, #1
8019dd4: 2300 movs r3, #0
8019dd6: f854 2022 ldr.w r2, [r4, r2, lsl #2]
8019dda: f7ff fe55 bl 8019a88 <__multadd>
8019dde: 4605 mov r5, r0
8019de0: 10bf asrs r7, r7, #2
8019de2: d03f beq.n 8019e64 <__pow5mult+0xa4>
8019de4: f8d8 401c ldr.w r4, [r8, #28]
8019de8: b994 cbnz r4, 8019e10 <__pow5mult+0x50>
8019dea: 2010 movs r0, #16
8019dec: f7ff fd36 bl 801985c <malloc>
8019df0: 4604 mov r4, r0
8019df2: f8c8 001c str.w r0, [r8, #28]
8019df6: b930 cbnz r0, 8019e06 <__pow5mult+0x46>
8019df8: 4602 mov r2, r0
8019dfa: 4b1d ldr r3, [pc, #116] @ (8019e70 <__pow5mult+0xb0>)
8019dfc: 481d ldr r0, [pc, #116] @ (8019e74 <__pow5mult+0xb4>)
8019dfe: f240 11b3 movw r1, #435 @ 0x1b3
8019e02: f001 fd19 bl 801b838 <__assert_func>
8019e06: 2300 movs r3, #0
8019e08: e9c0 3301 strd r3, r3, [r0, #4]
8019e0c: 6003 str r3, [r0, #0]
8019e0e: 60c3 str r3, [r0, #12]
8019e10: 68a6 ldr r6, [r4, #8]
8019e12: b946 cbnz r6, 8019e26 <__pow5mult+0x66>
8019e14: f240 2171 movw r1, #625 @ 0x271
8019e18: 4640 mov r0, r8
8019e1a: f7ff ff11 bl 8019c40 <__i2b>
8019e1e: 2300 movs r3, #0
8019e20: 60a0 str r0, [r4, #8]
8019e22: 4606 mov r6, r0
8019e24: 6003 str r3, [r0, #0]
8019e26: 462c mov r4, r5
8019e28: f04f 0900 mov.w r9, #0
8019e2c: f007 0301 and.w r3, r7, #1
8019e30: 107f asrs r7, r7, #1
8019e32: b153 cbz r3, 8019e4a <__pow5mult+0x8a>
8019e34: 4629 mov r1, r5
8019e36: 4632 mov r2, r6
8019e38: 4640 mov r0, r8
8019e3a: f7ff ff17 bl 8019c6c <__multiply>
8019e3e: 4621 mov r1, r4
8019e40: 4605 mov r5, r0
8019e42: 4640 mov r0, r8
8019e44: f7ff fdfe bl 8019a44 <_Bfree>
8019e48: b167 cbz r7, 8019e64 <__pow5mult+0xa4>
8019e4a: 6830 ldr r0, [r6, #0]
8019e4c: b938 cbnz r0, 8019e5e <__pow5mult+0x9e>
8019e4e: 4632 mov r2, r6
8019e50: 4631 mov r1, r6
8019e52: 4640 mov r0, r8
8019e54: f7ff ff0a bl 8019c6c <__multiply>
8019e58: 6030 str r0, [r6, #0]
8019e5a: f8c0 9000 str.w r9, [r0]
8019e5e: 4606 mov r6, r0
8019e60: 462c mov r4, r5
8019e62: e7e3 b.n 8019e2c <__pow5mult+0x6c>
8019e64: 4628 mov r0, r5
8019e66: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8019e6a: bf00 nop
8019e6c: 0801c994 .word 0x0801c994
8019e70: 0801c802 .word 0x0801c802
8019e74: 0801c882 .word 0x0801c882
08019e78 <__lshift>:
8019e78: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
8019e7c: 460c mov r4, r1
8019e7e: 6849 ldr r1, [r1, #4]
8019e80: 6923 ldr r3, [r4, #16]
8019e82: eb03 1862 add.w r8, r3, r2, asr #5
8019e86: 68a3 ldr r3, [r4, #8]
8019e88: 4607 mov r7, r0
8019e8a: 4615 mov r5, r2
8019e8c: ea4f 1a62 mov.w sl, r2, asr #5
8019e90: f108 0901 add.w r9, r8, #1
8019e94: 454b cmp r3, r9
8019e96: db0b blt.n 8019eb0 <__lshift+0x38>
8019e98: 4638 mov r0, r7
8019e9a: f7ff fd95 bl 80199c8 <_Balloc>
8019e9e: 4606 mov r6, r0
8019ea0: b948 cbnz r0, 8019eb6 <__lshift+0x3e>
8019ea2: 4602 mov r2, r0
8019ea4: 4b29 ldr r3, [pc, #164] @ (8019f4c <__lshift+0xd4>)
8019ea6: 482a ldr r0, [pc, #168] @ (8019f50 <__lshift+0xd8>)
8019ea8: f44f 71ef mov.w r1, #478 @ 0x1de
8019eac: f001 fcc4 bl 801b838 <__assert_func>
8019eb0: 3101 adds r1, #1
8019eb2: 005b lsls r3, r3, #1
8019eb4: e7ee b.n 8019e94 <__lshift+0x1c>
8019eb6: 2300 movs r3, #0
8019eb8: f100 0c14 add.w ip, r0, #20
8019ebc: f100 0210 add.w r2, r0, #16
8019ec0: 4619 mov r1, r3
8019ec2: 4553 cmp r3, sl
8019ec4: db35 blt.n 8019f32 <__lshift+0xba>
8019ec6: 6922 ldr r2, [r4, #16]
8019ec8: ea2a 7aea bic.w sl, sl, sl, asr #31
8019ecc: eb0c 0c8a add.w ip, ip, sl, lsl #2
8019ed0: f104 0314 add.w r3, r4, #20
8019ed4: f015 0e1f ands.w lr, r5, #31
8019ed8: 4661 mov r1, ip
8019eda: eb03 0282 add.w r2, r3, r2, lsl #2
8019ede: d02c beq.n 8019f3a <__lshift+0xc2>
8019ee0: f1ce 0a20 rsb sl, lr, #32
8019ee4: 2500 movs r5, #0
8019ee6: 6818 ldr r0, [r3, #0]
8019ee8: 468b mov fp, r1
8019eea: fa00 f00e lsl.w r0, r0, lr
8019eee: 4328 orrs r0, r5
8019ef0: f8cb 0000 str.w r0, [fp]
8019ef4: f853 5b04 ldr.w r5, [r3], #4
8019ef8: 429a cmp r2, r3
8019efa: f101 0104 add.w r1, r1, #4
8019efe: fa25 f50a lsr.w r5, r5, sl
8019f02: d8f0 bhi.n 8019ee6 <__lshift+0x6e>
8019f04: 1b13 subs r3, r2, r4
8019f06: 3b15 subs r3, #21
8019f08: f023 0303 bic.w r3, r3, #3
8019f0c: f104 0115 add.w r1, r4, #21
8019f10: 428a cmp r2, r1
8019f12: bf38 it cc
8019f14: 2300 movcc r3, #0
8019f16: 449c add ip, r3
8019f18: f8cc 5004 str.w r5, [ip, #4]
8019f1c: b905 cbnz r5, 8019f20 <__lshift+0xa8>
8019f1e: 46c1 mov r9, r8
8019f20: 4638 mov r0, r7
8019f22: f8c6 9010 str.w r9, [r6, #16]
8019f26: 4621 mov r1, r4
8019f28: f7ff fd8c bl 8019a44 <_Bfree>
8019f2c: 4630 mov r0, r6
8019f2e: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
8019f32: f842 1f04 str.w r1, [r2, #4]!
8019f36: 3301 adds r3, #1
8019f38: e7c3 b.n 8019ec2 <__lshift+0x4a>
8019f3a: f853 5b04 ldr.w r5, [r3], #4
8019f3e: 600d str r5, [r1, #0]
8019f40: 429a cmp r2, r3
8019f42: f101 0104 add.w r1, r1, #4
8019f46: d8f8 bhi.n 8019f3a <__lshift+0xc2>
8019f48: e7e9 b.n 8019f1e <__lshift+0xa6>
8019f4a: bf00 nop
8019f4c: 0801c871 .word 0x0801c871
8019f50: 0801c882 .word 0x0801c882
08019f54 <__mcmp>:
8019f54: 690a ldr r2, [r1, #16]
8019f56: 4603 mov r3, r0
8019f58: 6900 ldr r0, [r0, #16]
8019f5a: 1a80 subs r0, r0, r2
8019f5c: b530 push {r4, r5, lr}
8019f5e: d10e bne.n 8019f7e <__mcmp+0x2a>
8019f60: 3314 adds r3, #20
8019f62: 3114 adds r1, #20
8019f64: eb03 0482 add.w r4, r3, r2, lsl #2
8019f68: eb01 0182 add.w r1, r1, r2, lsl #2
8019f6c: f854 5d04 ldr.w r5, [r4, #-4]!
8019f70: f851 2d04 ldr.w r2, [r1, #-4]!
8019f74: 4295 cmp r5, r2
8019f76: d003 beq.n 8019f80 <__mcmp+0x2c>
8019f78: d205 bcs.n 8019f86 <__mcmp+0x32>
8019f7a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8019f7e: bd30 pop {r4, r5, pc}
8019f80: 42a3 cmp r3, r4
8019f82: d3f3 bcc.n 8019f6c <__mcmp+0x18>
8019f84: e7fb b.n 8019f7e <__mcmp+0x2a>
8019f86: 2001 movs r0, #1
8019f88: e7f9 b.n 8019f7e <__mcmp+0x2a>
...
08019f8c <__mdiff>:
8019f8c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
8019f90: 468a mov sl, r1
8019f92: 4606 mov r6, r0
8019f94: 4611 mov r1, r2
8019f96: 4650 mov r0, sl
8019f98: 4614 mov r4, r2
8019f9a: f7ff ffdb bl 8019f54 <__mcmp>
8019f9e: 1e05 subs r5, r0, #0
8019fa0: d112 bne.n 8019fc8 <__mdiff+0x3c>
8019fa2: 4629 mov r1, r5
8019fa4: 4630 mov r0, r6
8019fa6: f7ff fd0f bl 80199c8 <_Balloc>
8019faa: 4602 mov r2, r0
8019fac: b928 cbnz r0, 8019fba <__mdiff+0x2e>
8019fae: 4b41 ldr r3, [pc, #260] @ (801a0b4 <__mdiff+0x128>)
8019fb0: f240 2137 movw r1, #567 @ 0x237
8019fb4: 4840 ldr r0, [pc, #256] @ (801a0b8 <__mdiff+0x12c>)
8019fb6: f001 fc3f bl 801b838 <__assert_func>
8019fba: 2301 movs r3, #1
8019fbc: e9c0 3504 strd r3, r5, [r0, #16]
8019fc0: 4610 mov r0, r2
8019fc2: b003 add sp, #12
8019fc4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8019fc8: bfbc itt lt
8019fca: 4653 movlt r3, sl
8019fcc: 46a2 movlt sl, r4
8019fce: 4630 mov r0, r6
8019fd0: f8da 1004 ldr.w r1, [sl, #4]
8019fd4: bfba itte lt
8019fd6: 461c movlt r4, r3
8019fd8: 2501 movlt r5, #1
8019fda: 2500 movge r5, #0
8019fdc: f7ff fcf4 bl 80199c8 <_Balloc>
8019fe0: 4602 mov r2, r0
8019fe2: b918 cbnz r0, 8019fec <__mdiff+0x60>
8019fe4: 4b33 ldr r3, [pc, #204] @ (801a0b4 <__mdiff+0x128>)
8019fe6: f240 2145 movw r1, #581 @ 0x245
8019fea: e7e3 b.n 8019fb4 <__mdiff+0x28>
8019fec: f8da 7010 ldr.w r7, [sl, #16]
8019ff0: 6926 ldr r6, [r4, #16]
8019ff2: 60c5 str r5, [r0, #12]
8019ff4: f10a 0914 add.w r9, sl, #20
8019ff8: f104 0e14 add.w lr, r4, #20
8019ffc: f100 0514 add.w r5, r0, #20
801a000: f10a 0310 add.w r3, sl, #16
801a004: eb09 0887 add.w r8, r9, r7, lsl #2
801a008: eb0e 0686 add.w r6, lr, r6, lsl #2
801a00c: 9301 str r3, [sp, #4]
801a00e: 46ab mov fp, r5
801a010: f04f 0c00 mov.w ip, #0
801a014: 9b01 ldr r3, [sp, #4]
801a016: f85e 0b04 ldr.w r0, [lr], #4
801a01a: f853 af04 ldr.w sl, [r3, #4]!
801a01e: 9301 str r3, [sp, #4]
801a020: fa1f f38a uxth.w r3, sl
801a024: 4619 mov r1, r3
801a026: b283 uxth r3, r0
801a028: 1acb subs r3, r1, r3
801a02a: 0c00 lsrs r0, r0, #16
801a02c: 4463 add r3, ip
801a02e: ebc0 401a rsb r0, r0, sl, lsr #16
801a032: eb00 4023 add.w r0, r0, r3, asr #16
801a036: b29b uxth r3, r3
801a038: ea43 4300 orr.w r3, r3, r0, lsl #16
801a03c: 4576 cmp r6, lr
801a03e: f84b 3b04 str.w r3, [fp], #4
801a042: ea4f 4c20 mov.w ip, r0, asr #16
801a046: d8e5 bhi.n 801a014 <__mdiff+0x88>
801a048: 1b33 subs r3, r6, r4
801a04a: 3b15 subs r3, #21
801a04c: 3415 adds r4, #21
801a04e: f023 0303 bic.w r3, r3, #3
801a052: 42a6 cmp r6, r4
801a054: bf38 it cc
801a056: 2300 movcc r3, #0
801a058: 18e8 adds r0, r5, r3
801a05a: 444b add r3, r9
801a05c: 1d1c adds r4, r3, #4
801a05e: 3004 adds r0, #4
801a060: 4626 mov r6, r4
801a062: eba5 0509 sub.w r5, r5, r9
801a066: 4546 cmp r6, r8
801a068: eb06 0e05 add.w lr, r6, r5
801a06c: d30e bcc.n 801a08c <__mdiff+0x100>
801a06e: f108 0103 add.w r1, r8, #3
801a072: 1b09 subs r1, r1, r4
801a074: f021 0103 bic.w r1, r1, #3
801a078: 3301 adds r3, #1
801a07a: 4598 cmp r8, r3
801a07c: bf38 it cc
801a07e: 2100 movcc r1, #0
801a080: 4401 add r1, r0
801a082: f851 3d04 ldr.w r3, [r1, #-4]!
801a086: b19b cbz r3, 801a0b0 <__mdiff+0x124>
801a088: 6117 str r7, [r2, #16]
801a08a: e799 b.n 8019fc0 <__mdiff+0x34>
801a08c: f856 1b04 ldr.w r1, [r6], #4
801a090: 46e2 mov sl, ip
801a092: ea4f 4911 mov.w r9, r1, lsr #16
801a096: fa1c fc81 uxtah ip, ip, r1
801a09a: 4451 add r1, sl
801a09c: eb09 492c add.w r9, r9, ip, asr #16
801a0a0: b289 uxth r1, r1
801a0a2: ea41 4109 orr.w r1, r1, r9, lsl #16
801a0a6: ea4f 4c29 mov.w ip, r9, asr #16
801a0aa: f8ce 1000 str.w r1, [lr]
801a0ae: e7da b.n 801a066 <__mdiff+0xda>
801a0b0: 3f01 subs r7, #1
801a0b2: e7e6 b.n 801a082 <__mdiff+0xf6>
801a0b4: 0801c871 .word 0x0801c871
801a0b8: 0801c882 .word 0x0801c882
0801a0bc <__ulp>:
801a0bc: b082 sub sp, #8
801a0be: ed8d 0b00 vstr d0, [sp]
801a0c2: 9a01 ldr r2, [sp, #4]
801a0c4: 4b0f ldr r3, [pc, #60] @ (801a104 <__ulp+0x48>)
801a0c6: 4013 ands r3, r2
801a0c8: f1a3 7350 sub.w r3, r3, #54525952 @ 0x3400000
801a0cc: 2b00 cmp r3, #0
801a0ce: dc08 bgt.n 801a0e2 <__ulp+0x26>
801a0d0: 425b negs r3, r3
801a0d2: f1b3 7fa0 cmp.w r3, #20971520 @ 0x1400000
801a0d6: ea4f 5223 mov.w r2, r3, asr #20
801a0da: da04 bge.n 801a0e6 <__ulp+0x2a>
801a0dc: f44f 2300 mov.w r3, #524288 @ 0x80000
801a0e0: 4113 asrs r3, r2
801a0e2: 2200 movs r2, #0
801a0e4: e008 b.n 801a0f8 <__ulp+0x3c>
801a0e6: f1a2 0314 sub.w r3, r2, #20
801a0ea: 2b1e cmp r3, #30
801a0ec: bfda itte le
801a0ee: f04f 4200 movle.w r2, #2147483648 @ 0x80000000
801a0f2: 40da lsrle r2, r3
801a0f4: 2201 movgt r2, #1
801a0f6: 2300 movs r3, #0
801a0f8: 4619 mov r1, r3
801a0fa: 4610 mov r0, r2
801a0fc: ec41 0b10 vmov d0, r0, r1
801a100: b002 add sp, #8
801a102: 4770 bx lr
801a104: 7ff00000 .word 0x7ff00000
0801a108 <__b2d>:
801a108: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801a10c: 6906 ldr r6, [r0, #16]
801a10e: f100 0814 add.w r8, r0, #20
801a112: eb08 0686 add.w r6, r8, r6, lsl #2
801a116: 1f37 subs r7, r6, #4
801a118: f856 2c04 ldr.w r2, [r6, #-4]
801a11c: 4610 mov r0, r2
801a11e: f7ff fd43 bl 8019ba8 <__hi0bits>
801a122: f1c0 0320 rsb r3, r0, #32
801a126: 280a cmp r0, #10
801a128: 600b str r3, [r1, #0]
801a12a: 491b ldr r1, [pc, #108] @ (801a198 <__b2d+0x90>)
801a12c: dc15 bgt.n 801a15a <__b2d+0x52>
801a12e: f1c0 0c0b rsb ip, r0, #11
801a132: fa22 f30c lsr.w r3, r2, ip
801a136: 45b8 cmp r8, r7
801a138: ea43 0501 orr.w r5, r3, r1
801a13c: bf34 ite cc
801a13e: f856 3c08 ldrcc.w r3, [r6, #-8]
801a142: 2300 movcs r3, #0
801a144: 3015 adds r0, #21
801a146: fa02 f000 lsl.w r0, r2, r0
801a14a: fa23 f30c lsr.w r3, r3, ip
801a14e: 4303 orrs r3, r0
801a150: 461c mov r4, r3
801a152: ec45 4b10 vmov d0, r4, r5
801a156: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
801a15a: 45b8 cmp r8, r7
801a15c: bf3a itte cc
801a15e: f856 3c08 ldrcc.w r3, [r6, #-8]
801a162: f1a6 0708 subcc.w r7, r6, #8
801a166: 2300 movcs r3, #0
801a168: 380b subs r0, #11
801a16a: d012 beq.n 801a192 <__b2d+0x8a>
801a16c: f1c0 0120 rsb r1, r0, #32
801a170: fa23 f401 lsr.w r4, r3, r1
801a174: 4082 lsls r2, r0
801a176: 4322 orrs r2, r4
801a178: 4547 cmp r7, r8
801a17a: f042 557f orr.w r5, r2, #1069547520 @ 0x3fc00000
801a17e: bf8c ite hi
801a180: f857 2c04 ldrhi.w r2, [r7, #-4]
801a184: 2200 movls r2, #0
801a186: 4083 lsls r3, r0
801a188: 40ca lsrs r2, r1
801a18a: f445 1540 orr.w r5, r5, #3145728 @ 0x300000
801a18e: 4313 orrs r3, r2
801a190: e7de b.n 801a150 <__b2d+0x48>
801a192: ea42 0501 orr.w r5, r2, r1
801a196: e7db b.n 801a150 <__b2d+0x48>
801a198: 3ff00000 .word 0x3ff00000
0801a19c <__d2b>:
801a19c: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
801a1a0: 460f mov r7, r1
801a1a2: 2101 movs r1, #1
801a1a4: ec59 8b10 vmov r8, r9, d0
801a1a8: 4616 mov r6, r2
801a1aa: f7ff fc0d bl 80199c8 <_Balloc>
801a1ae: 4604 mov r4, r0
801a1b0: b930 cbnz r0, 801a1c0 <__d2b+0x24>
801a1b2: 4602 mov r2, r0
801a1b4: 4b23 ldr r3, [pc, #140] @ (801a244 <__d2b+0xa8>)
801a1b6: 4824 ldr r0, [pc, #144] @ (801a248 <__d2b+0xac>)
801a1b8: f240 310f movw r1, #783 @ 0x30f
801a1bc: f001 fb3c bl 801b838 <__assert_func>
801a1c0: f3c9 550a ubfx r5, r9, #20, #11
801a1c4: f3c9 0313 ubfx r3, r9, #0, #20
801a1c8: b10d cbz r5, 801a1ce <__d2b+0x32>
801a1ca: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
801a1ce: 9301 str r3, [sp, #4]
801a1d0: f1b8 0300 subs.w r3, r8, #0
801a1d4: d023 beq.n 801a21e <__d2b+0x82>
801a1d6: 4668 mov r0, sp
801a1d8: 9300 str r3, [sp, #0]
801a1da: f7ff fd04 bl 8019be6 <__lo0bits>
801a1de: 9900 ldr r1, [sp, #0]
801a1e0: b1d8 cbz r0, 801a21a <__d2b+0x7e>
801a1e2: 9a01 ldr r2, [sp, #4]
801a1e4: f1c0 0320 rsb r3, r0, #32
801a1e8: fa02 f303 lsl.w r3, r2, r3
801a1ec: 430b orrs r3, r1
801a1ee: 40c2 lsrs r2, r0
801a1f0: 6163 str r3, [r4, #20]
801a1f2: 9201 str r2, [sp, #4]
801a1f4: 9b01 ldr r3, [sp, #4]
801a1f6: 61a3 str r3, [r4, #24]
801a1f8: 2b00 cmp r3, #0
801a1fa: bf0c ite eq
801a1fc: 2201 moveq r2, #1
801a1fe: 2202 movne r2, #2
801a200: 6122 str r2, [r4, #16]
801a202: b1a5 cbz r5, 801a22e <__d2b+0x92>
801a204: f2a5 4533 subw r5, r5, #1075 @ 0x433
801a208: 4405 add r5, r0
801a20a: 603d str r5, [r7, #0]
801a20c: f1c0 0035 rsb r0, r0, #53 @ 0x35
801a210: 6030 str r0, [r6, #0]
801a212: 4620 mov r0, r4
801a214: b003 add sp, #12
801a216: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
801a21a: 6161 str r1, [r4, #20]
801a21c: e7ea b.n 801a1f4 <__d2b+0x58>
801a21e: a801 add r0, sp, #4
801a220: f7ff fce1 bl 8019be6 <__lo0bits>
801a224: 9b01 ldr r3, [sp, #4]
801a226: 6163 str r3, [r4, #20]
801a228: 3020 adds r0, #32
801a22a: 2201 movs r2, #1
801a22c: e7e8 b.n 801a200 <__d2b+0x64>
801a22e: eb04 0382 add.w r3, r4, r2, lsl #2
801a232: f2a0 4032 subw r0, r0, #1074 @ 0x432
801a236: 6038 str r0, [r7, #0]
801a238: 6918 ldr r0, [r3, #16]
801a23a: f7ff fcb5 bl 8019ba8 <__hi0bits>
801a23e: ebc0 1042 rsb r0, r0, r2, lsl #5
801a242: e7e5 b.n 801a210 <__d2b+0x74>
801a244: 0801c871 .word 0x0801c871
801a248: 0801c882 .word 0x0801c882
0801a24c <__ratio>:
801a24c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
801a250: b085 sub sp, #20
801a252: e9cd 1000 strd r1, r0, [sp]
801a256: a902 add r1, sp, #8
801a258: f7ff ff56 bl 801a108 <__b2d>
801a25c: 9800 ldr r0, [sp, #0]
801a25e: a903 add r1, sp, #12
801a260: ec55 4b10 vmov r4, r5, d0
801a264: f7ff ff50 bl 801a108 <__b2d>
801a268: 9b01 ldr r3, [sp, #4]
801a26a: 6919 ldr r1, [r3, #16]
801a26c: 9b00 ldr r3, [sp, #0]
801a26e: 691b ldr r3, [r3, #16]
801a270: 1ac9 subs r1, r1, r3
801a272: e9dd 3202 ldrd r3, r2, [sp, #8]
801a276: 1a9b subs r3, r3, r2
801a278: ec5b ab10 vmov sl, fp, d0
801a27c: eb03 1341 add.w r3, r3, r1, lsl #5
801a280: 2b00 cmp r3, #0
801a282: bfce itee gt
801a284: 462a movgt r2, r5
801a286: ebc3 3303 rsble r3, r3, r3, lsl #12
801a28a: 465a movle r2, fp
801a28c: 462f mov r7, r5
801a28e: 46d9 mov r9, fp
801a290: bfcc ite gt
801a292: eb02 5703 addgt.w r7, r2, r3, lsl #20
801a296: eb02 5903 addle.w r9, r2, r3, lsl #20
801a29a: 464b mov r3, r9
801a29c: 4652 mov r2, sl
801a29e: 4620 mov r0, r4
801a2a0: 4639 mov r1, r7
801a2a2: f7e6 faab bl 80007fc <__aeabi_ddiv>
801a2a6: ec41 0b10 vmov d0, r0, r1
801a2aa: b005 add sp, #20
801a2ac: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
0801a2b0 <__copybits>:
801a2b0: 3901 subs r1, #1
801a2b2: b570 push {r4, r5, r6, lr}
801a2b4: 1149 asrs r1, r1, #5
801a2b6: 6914 ldr r4, [r2, #16]
801a2b8: 3101 adds r1, #1
801a2ba: f102 0314 add.w r3, r2, #20
801a2be: eb00 0181 add.w r1, r0, r1, lsl #2
801a2c2: eb03 0484 add.w r4, r3, r4, lsl #2
801a2c6: 1f05 subs r5, r0, #4
801a2c8: 42a3 cmp r3, r4
801a2ca: d30c bcc.n 801a2e6 <__copybits+0x36>
801a2cc: 1aa3 subs r3, r4, r2
801a2ce: 3b11 subs r3, #17
801a2d0: f023 0303 bic.w r3, r3, #3
801a2d4: 3211 adds r2, #17
801a2d6: 4294 cmp r4, r2
801a2d8: bf38 it cc
801a2da: 2300 movcc r3, #0
801a2dc: 4418 add r0, r3
801a2de: 2300 movs r3, #0
801a2e0: 4288 cmp r0, r1
801a2e2: d305 bcc.n 801a2f0 <__copybits+0x40>
801a2e4: bd70 pop {r4, r5, r6, pc}
801a2e6: f853 6b04 ldr.w r6, [r3], #4
801a2ea: f845 6f04 str.w r6, [r5, #4]!
801a2ee: e7eb b.n 801a2c8 <__copybits+0x18>
801a2f0: f840 3b04 str.w r3, [r0], #4
801a2f4: e7f4 b.n 801a2e0 <__copybits+0x30>
0801a2f6 <__any_on>:
801a2f6: f100 0214 add.w r2, r0, #20
801a2fa: 6900 ldr r0, [r0, #16]
801a2fc: 114b asrs r3, r1, #5
801a2fe: 4298 cmp r0, r3
801a300: b510 push {r4, lr}
801a302: db11 blt.n 801a328 <__any_on+0x32>
801a304: dd0a ble.n 801a31c <__any_on+0x26>
801a306: f011 011f ands.w r1, r1, #31
801a30a: d007 beq.n 801a31c <__any_on+0x26>
801a30c: f852 4023 ldr.w r4, [r2, r3, lsl #2]
801a310: fa24 f001 lsr.w r0, r4, r1
801a314: fa00 f101 lsl.w r1, r0, r1
801a318: 428c cmp r4, r1
801a31a: d10b bne.n 801a334 <__any_on+0x3e>
801a31c: eb02 0383 add.w r3, r2, r3, lsl #2
801a320: 4293 cmp r3, r2
801a322: d803 bhi.n 801a32c <__any_on+0x36>
801a324: 2000 movs r0, #0
801a326: bd10 pop {r4, pc}
801a328: 4603 mov r3, r0
801a32a: e7f7 b.n 801a31c <__any_on+0x26>
801a32c: f853 1d04 ldr.w r1, [r3, #-4]!
801a330: 2900 cmp r1, #0
801a332: d0f5 beq.n 801a320 <__any_on+0x2a>
801a334: 2001 movs r0, #1
801a336: e7f6 b.n 801a326 <__any_on+0x30>
0801a338 <sulp>:
801a338: b570 push {r4, r5, r6, lr}
801a33a: 4604 mov r4, r0
801a33c: 460d mov r5, r1
801a33e: ec45 4b10 vmov d0, r4, r5
801a342: 4616 mov r6, r2
801a344: f7ff feba bl 801a0bc <__ulp>
801a348: ec51 0b10 vmov r0, r1, d0
801a34c: b17e cbz r6, 801a36e <sulp+0x36>
801a34e: f3c5 530a ubfx r3, r5, #20, #11
801a352: f1c3 036b rsb r3, r3, #107 @ 0x6b
801a356: 2b00 cmp r3, #0
801a358: dd09 ble.n 801a36e <sulp+0x36>
801a35a: 051b lsls r3, r3, #20
801a35c: f103 557f add.w r5, r3, #1069547520 @ 0x3fc00000
801a360: 2400 movs r4, #0
801a362: f505 1540 add.w r5, r5, #3145728 @ 0x300000
801a366: 4622 mov r2, r4
801a368: 462b mov r3, r5
801a36a: f7e6 f91d bl 80005a8 <__aeabi_dmul>
801a36e: ec41 0b10 vmov d0, r0, r1
801a372: bd70 pop {r4, r5, r6, pc}
801a374: 0000 movs r0, r0
...
0801a378 <_strtod_l>:
801a378: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
801a37c: b09d sub sp, #116 @ 0x74
801a37e: 460e mov r6, r1
801a380: 9215 str r2, [sp, #84] @ 0x54
801a382: 2200 movs r2, #0
801a384: 9004 str r0, [sp, #16]
801a386: 9218 str r2, [sp, #96] @ 0x60
801a388: f04f 0800 mov.w r8, #0
801a38c: f04f 0900 mov.w r9, #0
801a390: 9117 str r1, [sp, #92] @ 0x5c
801a392: 780a ldrb r2, [r1, #0]
801a394: 2a2b cmp r2, #43 @ 0x2b
801a396: 460d mov r5, r1
801a398: f101 0101 add.w r1, r1, #1
801a39c: d01d beq.n 801a3da <_strtod_l+0x62>
801a39e: d80b bhi.n 801a3b8 <_strtod_l+0x40>
801a3a0: 2a0d cmp r2, #13
801a3a2: d806 bhi.n 801a3b2 <_strtod_l+0x3a>
801a3a4: 2a08 cmp r2, #8
801a3a6: d8f3 bhi.n 801a390 <_strtod_l+0x18>
801a3a8: b17a cbz r2, 801a3ca <_strtod_l+0x52>
801a3aa: 2300 movs r3, #0
801a3ac: 930b str r3, [sp, #44] @ 0x2c
801a3ae: 469a mov sl, r3
801a3b0: e083 b.n 801a4ba <_strtod_l+0x142>
801a3b2: 2a20 cmp r2, #32
801a3b4: d0ec beq.n 801a390 <_strtod_l+0x18>
801a3b6: e7f8 b.n 801a3aa <_strtod_l+0x32>
801a3b8: 2a2d cmp r2, #45 @ 0x2d
801a3ba: d110 bne.n 801a3de <_strtod_l+0x66>
801a3bc: 2201 movs r2, #1
801a3be: 1c69 adds r1, r5, #1
801a3c0: 9117 str r1, [sp, #92] @ 0x5c
801a3c2: 920b str r2, [sp, #44] @ 0x2c
801a3c4: 786a ldrb r2, [r5, #1]
801a3c6: 2a00 cmp r2, #0
801a3c8: d137 bne.n 801a43a <_strtod_l+0xc2>
801a3ca: 9b15 ldr r3, [sp, #84] @ 0x54
801a3cc: 9617 str r6, [sp, #92] @ 0x5c
801a3ce: 2b00 cmp r3, #0
801a3d0: f040 8595 bne.w 801aefe <_strtod_l+0xb86>
801a3d4: 4642 mov r2, r8
801a3d6: 464b mov r3, r9
801a3d8: e02a b.n 801a430 <_strtod_l+0xb8>
801a3da: 2200 movs r2, #0
801a3dc: e7ef b.n 801a3be <_strtod_l+0x46>
801a3de: 2100 movs r1, #0
801a3e0: 910b str r1, [sp, #44] @ 0x2c
801a3e2: 2a30 cmp r2, #48 @ 0x30
801a3e4: f040 809b bne.w 801a51e <_strtod_l+0x1a6>
801a3e8: 786a ldrb r2, [r5, #1]
801a3ea: f002 02df and.w r2, r2, #223 @ 0xdf
801a3ee: 2a58 cmp r2, #88 @ 0x58
801a3f0: d15a bne.n 801a4a8 <_strtod_l+0x130>
801a3f2: 9302 str r3, [sp, #8]
801a3f4: 9b0b ldr r3, [sp, #44] @ 0x2c
801a3f6: 9301 str r3, [sp, #4]
801a3f8: ab18 add r3, sp, #96 @ 0x60
801a3fa: 9300 str r3, [sp, #0]
801a3fc: 4a81 ldr r2, [pc, #516] @ (801a604 <_strtod_l+0x28c>)
801a3fe: 9804 ldr r0, [sp, #16]
801a400: ab19 add r3, sp, #100 @ 0x64
801a402: a917 add r1, sp, #92 @ 0x5c
801a404: f001 fab2 bl 801b96c <__gethex>
801a408: f010 060f ands.w r6, r0, #15
801a40c: 4604 mov r4, r0
801a40e: d005 beq.n 801a41c <_strtod_l+0xa4>
801a410: 2e06 cmp r6, #6
801a412: d114 bne.n 801a43e <_strtod_l+0xc6>
801a414: 3501 adds r5, #1
801a416: 2300 movs r3, #0
801a418: 9517 str r5, [sp, #92] @ 0x5c
801a41a: 930b str r3, [sp, #44] @ 0x2c
801a41c: 9b15 ldr r3, [sp, #84] @ 0x54
801a41e: 2b00 cmp r3, #0
801a420: f040 856f bne.w 801af02 <_strtod_l+0xb8a>
801a424: 9b0b ldr r3, [sp, #44] @ 0x2c
801a426: 2b00 cmp r3, #0
801a428: d0d4 beq.n 801a3d4 <_strtod_l+0x5c>
801a42a: 4642 mov r2, r8
801a42c: f109 4300 add.w r3, r9, #2147483648 @ 0x80000000
801a430: ec43 2b10 vmov d0, r2, r3
801a434: b01d add sp, #116 @ 0x74
801a436: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
801a43a: 460d mov r5, r1
801a43c: e7d1 b.n 801a3e2 <_strtod_l+0x6a>
801a43e: 9a18 ldr r2, [sp, #96] @ 0x60
801a440: b13a cbz r2, 801a452 <_strtod_l+0xda>
801a442: 2135 movs r1, #53 @ 0x35
801a444: a81a add r0, sp, #104 @ 0x68
801a446: f7ff ff33 bl 801a2b0 <__copybits>
801a44a: 9918 ldr r1, [sp, #96] @ 0x60
801a44c: 9804 ldr r0, [sp, #16]
801a44e: f7ff faf9 bl 8019a44 <_Bfree>
801a452: 3e01 subs r6, #1
801a454: 2e04 cmp r6, #4
801a456: d806 bhi.n 801a466 <_strtod_l+0xee>
801a458: e8df f006 tbb [pc, r6]
801a45c: 211e0314 .word 0x211e0314
801a460: 14 .byte 0x14
801a461: 00 .byte 0x00
801a462: e9dd 891a ldrd r8, r9, [sp, #104] @ 0x68
801a466: 05e0 lsls r0, r4, #23
801a468: bf48 it mi
801a46a: f049 4900 orrmi.w r9, r9, #2147483648 @ 0x80000000
801a46e: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
801a472: 0d1b lsrs r3, r3, #20
801a474: 051b lsls r3, r3, #20
801a476: 2b00 cmp r3, #0
801a478: d1d0 bne.n 801a41c <_strtod_l+0xa4>
801a47a: f7fe fafd bl 8018a78 <__errno>
801a47e: 2322 movs r3, #34 @ 0x22
801a480: 6003 str r3, [r0, #0]
801a482: e7cb b.n 801a41c <_strtod_l+0xa4>
801a484: e9dd 831a ldrd r8, r3, [sp, #104] @ 0x68
801a488: 9a19 ldr r2, [sp, #100] @ 0x64
801a48a: f423 1380 bic.w r3, r3, #1048576 @ 0x100000
801a48e: f202 4233 addw r2, r2, #1075 @ 0x433
801a492: ea43 5902 orr.w r9, r3, r2, lsl #20
801a496: e7e6 b.n 801a466 <_strtod_l+0xee>
801a498: f8df 9170 ldr.w r9, [pc, #368] @ 801a60c <_strtod_l+0x294>
801a49c: e7e3 b.n 801a466 <_strtod_l+0xee>
801a49e: f06f 4900 mvn.w r9, #2147483648 @ 0x80000000
801a4a2: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff
801a4a6: e7de b.n 801a466 <_strtod_l+0xee>
801a4a8: 3501 adds r5, #1
801a4aa: 9517 str r5, [sp, #92] @ 0x5c
801a4ac: 782b ldrb r3, [r5, #0]
801a4ae: 2b30 cmp r3, #48 @ 0x30
801a4b0: d0fa beq.n 801a4a8 <_strtod_l+0x130>
801a4b2: 2b00 cmp r3, #0
801a4b4: d0b2 beq.n 801a41c <_strtod_l+0xa4>
801a4b6: f04f 0a01 mov.w sl, #1
801a4ba: 2700 movs r7, #0
801a4bc: 462b mov r3, r5
801a4be: 970e str r7, [sp, #56] @ 0x38
801a4c0: 46bb mov fp, r7
801a4c2: 210a movs r1, #10
801a4c4: 4618 mov r0, r3
801a4c6: f813 4b01 ldrb.w r4, [r3], #1
801a4ca: f1a4 0230 sub.w r2, r4, #48 @ 0x30
801a4ce: 2a09 cmp r2, #9
801a4d0: d928 bls.n 801a524 <_strtod_l+0x1ac>
801a4d2: 494d ldr r1, [pc, #308] @ (801a608 <_strtod_l+0x290>)
801a4d4: 2201 movs r2, #1
801a4d6: f001 f963 bl 801b7a0 <strncmp>
801a4da: 2800 cmp r0, #0
801a4dc: d034 beq.n 801a548 <_strtod_l+0x1d0>
801a4de: 2000 movs r0, #0
801a4e0: e9cd 0006 strd r0, r0, [sp, #24]
801a4e4: 4622 mov r2, r4
801a4e6: 465c mov r4, fp
801a4e8: 2a65 cmp r2, #101 @ 0x65
801a4ea: d001 beq.n 801a4f0 <_strtod_l+0x178>
801a4ec: 2a45 cmp r2, #69 @ 0x45
801a4ee: d114 bne.n 801a51a <_strtod_l+0x1a2>
801a4f0: b924 cbnz r4, 801a4fc <_strtod_l+0x184>
801a4f2: ea5a 0300 orrs.w r3, sl, r0
801a4f6: f43f af68 beq.w 801a3ca <_strtod_l+0x52>
801a4fa: 2400 movs r4, #0
801a4fc: 9e17 ldr r6, [sp, #92] @ 0x5c
801a4fe: 1c73 adds r3, r6, #1
801a500: 9317 str r3, [sp, #92] @ 0x5c
801a502: 7872 ldrb r2, [r6, #1]
801a504: 2a2b cmp r2, #43 @ 0x2b
801a506: d073 beq.n 801a5f0 <_strtod_l+0x278>
801a508: 2a2d cmp r2, #45 @ 0x2d
801a50a: d077 beq.n 801a5fc <_strtod_l+0x284>
801a50c: f04f 0c00 mov.w ip, #0
801a510: f1a2 0330 sub.w r3, r2, #48 @ 0x30
801a514: 2b09 cmp r3, #9
801a516: d97f bls.n 801a618 <_strtod_l+0x2a0>
801a518: 9617 str r6, [sp, #92] @ 0x5c
801a51a: 2300 movs r3, #0
801a51c: e09e b.n 801a65c <_strtod_l+0x2e4>
801a51e: f04f 0a00 mov.w sl, #0
801a522: e7ca b.n 801a4ba <_strtod_l+0x142>
801a524: f1bb 0f08 cmp.w fp, #8
801a528: bfd8 it le
801a52a: 9a0e ldrle r2, [sp, #56] @ 0x38
801a52c: 9317 str r3, [sp, #92] @ 0x5c
801a52e: bfdb ittet le
801a530: fb01 4202 mlale r2, r1, r2, r4
801a534: 3a30 suble r2, #48 @ 0x30
801a536: fb01 4207 mlagt r2, r1, r7, r4
801a53a: 920e strle r2, [sp, #56] @ 0x38
801a53c: bfc8 it gt
801a53e: f1a2 0730 subgt.w r7, r2, #48 @ 0x30
801a542: f10b 0b01 add.w fp, fp, #1
801a546: e7bd b.n 801a4c4 <_strtod_l+0x14c>
801a548: 9b17 ldr r3, [sp, #92] @ 0x5c
801a54a: 1c5a adds r2, r3, #1
801a54c: 9217 str r2, [sp, #92] @ 0x5c
801a54e: 785a ldrb r2, [r3, #1]
801a550: f1bb 0f00 cmp.w fp, #0
801a554: d033 beq.n 801a5be <_strtod_l+0x246>
801a556: 9006 str r0, [sp, #24]
801a558: 465c mov r4, fp
801a55a: f1a2 0330 sub.w r3, r2, #48 @ 0x30
801a55e: 2b09 cmp r3, #9
801a560: d912 bls.n 801a588 <_strtod_l+0x210>
801a562: 2301 movs r3, #1
801a564: 9307 str r3, [sp, #28]
801a566: e7bf b.n 801a4e8 <_strtod_l+0x170>
801a568: 9b17 ldr r3, [sp, #92] @ 0x5c
801a56a: 1c5a adds r2, r3, #1
801a56c: 9217 str r2, [sp, #92] @ 0x5c
801a56e: 785a ldrb r2, [r3, #1]
801a570: 3001 adds r0, #1
801a572: 2a30 cmp r2, #48 @ 0x30
801a574: d0f8 beq.n 801a568 <_strtod_l+0x1f0>
801a576: f1a2 0331 sub.w r3, r2, #49 @ 0x31
801a57a: 2b08 cmp r3, #8
801a57c: f200 84c6 bhi.w 801af0c <_strtod_l+0xb94>
801a580: 9006 str r0, [sp, #24]
801a582: 9d17 ldr r5, [sp, #92] @ 0x5c
801a584: 2000 movs r0, #0
801a586: 4604 mov r4, r0
801a588: 3a30 subs r2, #48 @ 0x30
801a58a: f100 0301 add.w r3, r0, #1
801a58e: d010 beq.n 801a5b2 <_strtod_l+0x23a>
801a590: 9906 ldr r1, [sp, #24]
801a592: 4419 add r1, r3
801a594: 9106 str r1, [sp, #24]
801a596: 4420 add r0, r4
801a598: 230a movs r3, #10
801a59a: 42a0 cmp r0, r4
801a59c: d111 bne.n 801a5c2 <_strtod_l+0x24a>
801a59e: 2808 cmp r0, #8
801a5a0: f100 0401 add.w r4, r0, #1
801a5a4: dc19 bgt.n 801a5da <_strtod_l+0x262>
801a5a6: 990e ldr r1, [sp, #56] @ 0x38
801a5a8: 230a movs r3, #10
801a5aa: fb03 2301 mla r3, r3, r1, r2
801a5ae: 930e str r3, [sp, #56] @ 0x38
801a5b0: 2300 movs r3, #0
801a5b2: 9a17 ldr r2, [sp, #92] @ 0x5c
801a5b4: 1c51 adds r1, r2, #1
801a5b6: 9117 str r1, [sp, #92] @ 0x5c
801a5b8: 7852 ldrb r2, [r2, #1]
801a5ba: 4618 mov r0, r3
801a5bc: e7cd b.n 801a55a <_strtod_l+0x1e2>
801a5be: 4658 mov r0, fp
801a5c0: e7d7 b.n 801a572 <_strtod_l+0x1fa>
801a5c2: 2c08 cmp r4, #8
801a5c4: f104 0401 add.w r4, r4, #1
801a5c8: dc03 bgt.n 801a5d2 <_strtod_l+0x25a>
801a5ca: 990e ldr r1, [sp, #56] @ 0x38
801a5cc: 4359 muls r1, r3
801a5ce: 910e str r1, [sp, #56] @ 0x38
801a5d0: e7e3 b.n 801a59a <_strtod_l+0x222>
801a5d2: 2c10 cmp r4, #16
801a5d4: bfd8 it le
801a5d6: 435f mulle r7, r3
801a5d8: e7df b.n 801a59a <_strtod_l+0x222>
801a5da: 280f cmp r0, #15
801a5dc: bfdc itt le
801a5de: 230a movle r3, #10
801a5e0: fb03 2707 mlale r7, r3, r7, r2
801a5e4: e7e4 b.n 801a5b0 <_strtod_l+0x238>
801a5e6: 2100 movs r1, #0
801a5e8: 2301 movs r3, #1
801a5ea: e9cd 1306 strd r1, r3, [sp, #24]
801a5ee: e780 b.n 801a4f2 <_strtod_l+0x17a>
801a5f0: f04f 0c00 mov.w ip, #0
801a5f4: 1cb3 adds r3, r6, #2
801a5f6: 9317 str r3, [sp, #92] @ 0x5c
801a5f8: 78b2 ldrb r2, [r6, #2]
801a5fa: e789 b.n 801a510 <_strtod_l+0x198>
801a5fc: f04f 0c01 mov.w ip, #1
801a600: e7f8 b.n 801a5f4 <_strtod_l+0x27c>
801a602: bf00 nop
801a604: 0801caa4 .word 0x0801caa4
801a608: 0801c8db .word 0x0801c8db
801a60c: 7ff00000 .word 0x7ff00000
801a610: 9b17 ldr r3, [sp, #92] @ 0x5c
801a612: 1c5a adds r2, r3, #1
801a614: 9217 str r2, [sp, #92] @ 0x5c
801a616: 785a ldrb r2, [r3, #1]
801a618: 2a30 cmp r2, #48 @ 0x30
801a61a: d0f9 beq.n 801a610 <_strtod_l+0x298>
801a61c: f1a2 0331 sub.w r3, r2, #49 @ 0x31
801a620: 2b08 cmp r3, #8
801a622: f63f af7a bhi.w 801a51a <_strtod_l+0x1a2>
801a626: 9b17 ldr r3, [sp, #92] @ 0x5c
801a628: 9305 str r3, [sp, #20]
801a62a: f1a2 0e30 sub.w lr, r2, #48 @ 0x30
801a62e: 3301 adds r3, #1
801a630: 9317 str r3, [sp, #92] @ 0x5c
801a632: 781a ldrb r2, [r3, #0]
801a634: f1a2 0130 sub.w r1, r2, #48 @ 0x30
801a638: 2909 cmp r1, #9
801a63a: d93c bls.n 801a6b6 <_strtod_l+0x33e>
801a63c: 9905 ldr r1, [sp, #20]
801a63e: 1a5b subs r3, r3, r1
801a640: 2b08 cmp r3, #8
801a642: f644 631f movw r3, #19999 @ 0x4e1f
801a646: dc3c bgt.n 801a6c2 <_strtod_l+0x34a>
801a648: 459e cmp lr, r3
801a64a: 4671 mov r1, lr
801a64c: bfa8 it ge
801a64e: 4619 movge r1, r3
801a650: 9105 str r1, [sp, #20]
801a652: f1bc 0f00 cmp.w ip, #0
801a656: d002 beq.n 801a65e <_strtod_l+0x2e6>
801a658: 9b05 ldr r3, [sp, #20]
801a65a: 425b negs r3, r3
801a65c: 9305 str r3, [sp, #20]
801a65e: 2c00 cmp r4, #0
801a660: d150 bne.n 801a704 <_strtod_l+0x38c>
801a662: ea5a 0000 orrs.w r0, sl, r0
801a666: f47f aed9 bne.w 801a41c <_strtod_l+0xa4>
801a66a: 9b07 ldr r3, [sp, #28]
801a66c: 2b00 cmp r3, #0
801a66e: f47f aeac bne.w 801a3ca <_strtod_l+0x52>
801a672: 2a69 cmp r2, #105 @ 0x69
801a674: d029 beq.n 801a6ca <_strtod_l+0x352>
801a676: dc26 bgt.n 801a6c6 <_strtod_l+0x34e>
801a678: 2a49 cmp r2, #73 @ 0x49
801a67a: d026 beq.n 801a6ca <_strtod_l+0x352>
801a67c: 2a4e cmp r2, #78 @ 0x4e
801a67e: f47f aea4 bne.w 801a3ca <_strtod_l+0x52>
801a682: 49a1 ldr r1, [pc, #644] @ (801a908 <_strtod_l+0x590>)
801a684: a817 add r0, sp, #92 @ 0x5c
801a686: f001 fb93 bl 801bdb0 <__match>
801a68a: 2800 cmp r0, #0
801a68c: f43f ae9d beq.w 801a3ca <_strtod_l+0x52>
801a690: 9b17 ldr r3, [sp, #92] @ 0x5c
801a692: 781b ldrb r3, [r3, #0]
801a694: 2b28 cmp r3, #40 @ 0x28
801a696: d12f bne.n 801a6f8 <_strtod_l+0x380>
801a698: 499c ldr r1, [pc, #624] @ (801a90c <_strtod_l+0x594>)
801a69a: aa1a add r2, sp, #104 @ 0x68
801a69c: a817 add r0, sp, #92 @ 0x5c
801a69e: f001 fb9b bl 801bdd8 <__hexnan>
801a6a2: 2805 cmp r0, #5
801a6a4: d128 bne.n 801a6f8 <_strtod_l+0x380>
801a6a6: 9b1b ldr r3, [sp, #108] @ 0x6c
801a6a8: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68
801a6ac: f043 49ff orr.w r9, r3, #2139095040 @ 0x7f800000
801a6b0: f449 09e0 orr.w r9, r9, #7340032 @ 0x700000
801a6b4: e6b2 b.n 801a41c <_strtod_l+0xa4>
801a6b6: 210a movs r1, #10
801a6b8: fb01 220e mla r2, r1, lr, r2
801a6bc: f1a2 0e30 sub.w lr, r2, #48 @ 0x30
801a6c0: e7b5 b.n 801a62e <_strtod_l+0x2b6>
801a6c2: 9305 str r3, [sp, #20]
801a6c4: e7c5 b.n 801a652 <_strtod_l+0x2da>
801a6c6: 2a6e cmp r2, #110 @ 0x6e
801a6c8: e7d9 b.n 801a67e <_strtod_l+0x306>
801a6ca: 4991 ldr r1, [pc, #580] @ (801a910 <_strtod_l+0x598>)
801a6cc: a817 add r0, sp, #92 @ 0x5c
801a6ce: f001 fb6f bl 801bdb0 <__match>
801a6d2: 2800 cmp r0, #0
801a6d4: f43f ae79 beq.w 801a3ca <_strtod_l+0x52>
801a6d8: 9b17 ldr r3, [sp, #92] @ 0x5c
801a6da: 498e ldr r1, [pc, #568] @ (801a914 <_strtod_l+0x59c>)
801a6dc: 3b01 subs r3, #1
801a6de: a817 add r0, sp, #92 @ 0x5c
801a6e0: 9317 str r3, [sp, #92] @ 0x5c
801a6e2: f001 fb65 bl 801bdb0 <__match>
801a6e6: b910 cbnz r0, 801a6ee <_strtod_l+0x376>
801a6e8: 9b17 ldr r3, [sp, #92] @ 0x5c
801a6ea: 3301 adds r3, #1
801a6ec: 9317 str r3, [sp, #92] @ 0x5c
801a6ee: f8df 9234 ldr.w r9, [pc, #564] @ 801a924 <_strtod_l+0x5ac>
801a6f2: f04f 0800 mov.w r8, #0
801a6f6: e691 b.n 801a41c <_strtod_l+0xa4>
801a6f8: 4887 ldr r0, [pc, #540] @ (801a918 <_strtod_l+0x5a0>)
801a6fa: f001 f895 bl 801b828 <nan>
801a6fe: ec59 8b10 vmov r8, r9, d0
801a702: e68b b.n 801a41c <_strtod_l+0xa4>
801a704: e9dd 3205 ldrd r3, r2, [sp, #20]
801a708: 980e ldr r0, [sp, #56] @ 0x38
801a70a: 1a9b subs r3, r3, r2
801a70c: f1bb 0f00 cmp.w fp, #0
801a710: bf08 it eq
801a712: 46a3 moveq fp, r4
801a714: 2c10 cmp r4, #16
801a716: 930a str r3, [sp, #40] @ 0x28
801a718: 46a2 mov sl, r4
801a71a: bfa8 it ge
801a71c: f04f 0a10 movge.w sl, #16
801a720: f7e5 fec8 bl 80004b4 <__aeabi_ui2d>
801a724: 2c09 cmp r4, #9
801a726: 4680 mov r8, r0
801a728: 4689 mov r9, r1
801a72a: dc13 bgt.n 801a754 <_strtod_l+0x3dc>
801a72c: 9b0a ldr r3, [sp, #40] @ 0x28
801a72e: 2b00 cmp r3, #0
801a730: f43f ae74 beq.w 801a41c <_strtod_l+0xa4>
801a734: 9b0a ldr r3, [sp, #40] @ 0x28
801a736: dd73 ble.n 801a820 <_strtod_l+0x4a8>
801a738: 2b16 cmp r3, #22
801a73a: dc5a bgt.n 801a7f2 <_strtod_l+0x47a>
801a73c: 4977 ldr r1, [pc, #476] @ (801a91c <_strtod_l+0x5a4>)
801a73e: eb01 01c3 add.w r1, r1, r3, lsl #3
801a742: e9d1 0100 ldrd r0, r1, [r1]
801a746: 4642 mov r2, r8
801a748: 464b mov r3, r9
801a74a: f7e5 ff2d bl 80005a8 <__aeabi_dmul>
801a74e: 4680 mov r8, r0
801a750: 4689 mov r9, r1
801a752: e663 b.n 801a41c <_strtod_l+0xa4>
801a754: 4b71 ldr r3, [pc, #452] @ (801a91c <_strtod_l+0x5a4>)
801a756: eb03 03ca add.w r3, r3, sl, lsl #3
801a75a: e953 2312 ldrd r2, r3, [r3, #-72] @ 0x48
801a75e: f7e5 ff23 bl 80005a8 <__aeabi_dmul>
801a762: 4680 mov r8, r0
801a764: 4638 mov r0, r7
801a766: 4689 mov r9, r1
801a768: f7e5 fea4 bl 80004b4 <__aeabi_ui2d>
801a76c: 4602 mov r2, r0
801a76e: 460b mov r3, r1
801a770: 4640 mov r0, r8
801a772: 4649 mov r1, r9
801a774: f7e5 fd62 bl 800023c <__adddf3>
801a778: 2c0f cmp r4, #15
801a77a: 4680 mov r8, r0
801a77c: 4689 mov r9, r1
801a77e: ddd5 ble.n 801a72c <_strtod_l+0x3b4>
801a780: 9b0a ldr r3, [sp, #40] @ 0x28
801a782: eba4 0a0a sub.w sl, r4, sl
801a786: 449a add sl, r3
801a788: f1ba 0f00 cmp.w sl, #0
801a78c: f340 8097 ble.w 801a8be <_strtod_l+0x546>
801a790: f02a 060f bic.w r6, sl, #15
801a794: f01a 0a0f ands.w sl, sl, #15
801a798: d151 bne.n 801a83e <_strtod_l+0x4c6>
801a79a: f5b6 7f9a cmp.w r6, #308 @ 0x134
801a79e: dc5e bgt.n 801a85e <_strtod_l+0x4e6>
801a7a0: 2300 movs r3, #0
801a7a2: f8df a17c ldr.w sl, [pc, #380] @ 801a920 <_strtod_l+0x5a8>
801a7a6: 1136 asrs r6, r6, #4
801a7a8: 4640 mov r0, r8
801a7aa: 4649 mov r1, r9
801a7ac: 461f mov r7, r3
801a7ae: 2e01 cmp r6, #1
801a7b0: d179 bne.n 801a8a6 <_strtod_l+0x52e>
801a7b2: b10b cbz r3, 801a7b8 <_strtod_l+0x440>
801a7b4: 4680 mov r8, r0
801a7b6: 4689 mov r9, r1
801a7b8: 4959 ldr r1, [pc, #356] @ (801a920 <_strtod_l+0x5a8>)
801a7ba: f1a9 7954 sub.w r9, r9, #55574528 @ 0x3500000
801a7be: eb01 01c7 add.w r1, r1, r7, lsl #3
801a7c2: 4642 mov r2, r8
801a7c4: 464b mov r3, r9
801a7c6: e9d1 0100 ldrd r0, r1, [r1]
801a7ca: f7e5 feed bl 80005a8 <__aeabi_dmul>
801a7ce: 4b55 ldr r3, [pc, #340] @ (801a924 <_strtod_l+0x5ac>)
801a7d0: 460a mov r2, r1
801a7d2: 400b ands r3, r1
801a7d4: 4954 ldr r1, [pc, #336] @ (801a928 <_strtod_l+0x5b0>)
801a7d6: 428b cmp r3, r1
801a7d8: 4680 mov r8, r0
801a7da: d840 bhi.n 801a85e <_strtod_l+0x4e6>
801a7dc: f5a1 1180 sub.w r1, r1, #1048576 @ 0x100000
801a7e0: 428b cmp r3, r1
801a7e2: bf86 itte hi
801a7e4: f8df 9144 ldrhi.w r9, [pc, #324] @ 801a92c <_strtod_l+0x5b4>
801a7e8: f04f 38ff movhi.w r8, #4294967295 @ 0xffffffff
801a7ec: f102 7954 addls.w r9, r2, #55574528 @ 0x3500000
801a7f0: e032 b.n 801a858 <_strtod_l+0x4e0>
801a7f2: 9a0a ldr r2, [sp, #40] @ 0x28
801a7f4: f1c4 0325 rsb r3, r4, #37 @ 0x25
801a7f8: 4293 cmp r3, r2
801a7fa: dbc1 blt.n 801a780 <_strtod_l+0x408>
801a7fc: 4d47 ldr r5, [pc, #284] @ (801a91c <_strtod_l+0x5a4>)
801a7fe: f1c4 040f rsb r4, r4, #15
801a802: eb05 01c4 add.w r1, r5, r4, lsl #3
801a806: 4642 mov r2, r8
801a808: 464b mov r3, r9
801a80a: e9d1 0100 ldrd r0, r1, [r1]
801a80e: f7e5 fecb bl 80005a8 <__aeabi_dmul>
801a812: 9b0a ldr r3, [sp, #40] @ 0x28
801a814: 1b1c subs r4, r3, r4
801a816: eb05 05c4 add.w r5, r5, r4, lsl #3
801a81a: e9d5 2300 ldrd r2, r3, [r5]
801a81e: e794 b.n 801a74a <_strtod_l+0x3d2>
801a820: 3316 adds r3, #22
801a822: dbad blt.n 801a780 <_strtod_l+0x408>
801a824: e9dd 2305 ldrd r2, r3, [sp, #20]
801a828: 1a9a subs r2, r3, r2
801a82a: 4b3c ldr r3, [pc, #240] @ (801a91c <_strtod_l+0x5a4>)
801a82c: eb03 03c2 add.w r3, r3, r2, lsl #3
801a830: e9d3 2300 ldrd r2, r3, [r3]
801a834: 4640 mov r0, r8
801a836: 4649 mov r1, r9
801a838: f7e5 ffe0 bl 80007fc <__aeabi_ddiv>
801a83c: e787 b.n 801a74e <_strtod_l+0x3d6>
801a83e: 4937 ldr r1, [pc, #220] @ (801a91c <_strtod_l+0x5a4>)
801a840: eb01 01ca add.w r1, r1, sl, lsl #3
801a844: 4642 mov r2, r8
801a846: 464b mov r3, r9
801a848: e9d1 0100 ldrd r0, r1, [r1]
801a84c: f7e5 feac bl 80005a8 <__aeabi_dmul>
801a850: 4680 mov r8, r0
801a852: 4689 mov r9, r1
801a854: 2e00 cmp r6, #0
801a856: d1a0 bne.n 801a79a <_strtod_l+0x422>
801a858: 2300 movs r3, #0
801a85a: 9307 str r3, [sp, #28]
801a85c: e0a0 b.n 801a9a0 <_strtod_l+0x628>
801a85e: 2400 movs r4, #0
801a860: 9405 str r4, [sp, #20]
801a862: 940e str r4, [sp, #56] @ 0x38
801a864: 9406 str r4, [sp, #24]
801a866: 9a04 ldr r2, [sp, #16]
801a868: f8df 90b8 ldr.w r9, [pc, #184] @ 801a924 <_strtod_l+0x5ac>
801a86c: 2322 movs r3, #34 @ 0x22
801a86e: 6013 str r3, [r2, #0]
801a870: f04f 0800 mov.w r8, #0
801a874: 9b0e ldr r3, [sp, #56] @ 0x38
801a876: 2b00 cmp r3, #0
801a878: f43f add0 beq.w 801a41c <_strtod_l+0xa4>
801a87c: 9918 ldr r1, [sp, #96] @ 0x60
801a87e: 9804 ldr r0, [sp, #16]
801a880: f7ff f8e0 bl 8019a44 <_Bfree>
801a884: 9906 ldr r1, [sp, #24]
801a886: 9804 ldr r0, [sp, #16]
801a888: f7ff f8dc bl 8019a44 <_Bfree>
801a88c: e9dd 0104 ldrd r0, r1, [sp, #16]
801a890: f7ff f8d8 bl 8019a44 <_Bfree>
801a894: 990e ldr r1, [sp, #56] @ 0x38
801a896: 9804 ldr r0, [sp, #16]
801a898: f7ff f8d4 bl 8019a44 <_Bfree>
801a89c: 9804 ldr r0, [sp, #16]
801a89e: 4621 mov r1, r4
801a8a0: f7ff f8d0 bl 8019a44 <_Bfree>
801a8a4: e5ba b.n 801a41c <_strtod_l+0xa4>
801a8a6: 07f2 lsls r2, r6, #31
801a8a8: d504 bpl.n 801a8b4 <_strtod_l+0x53c>
801a8aa: e9da 2300 ldrd r2, r3, [sl]
801a8ae: f7e5 fe7b bl 80005a8 <__aeabi_dmul>
801a8b2: 2301 movs r3, #1
801a8b4: 3701 adds r7, #1
801a8b6: 1076 asrs r6, r6, #1
801a8b8: f10a 0a08 add.w sl, sl, #8
801a8bc: e777 b.n 801a7ae <_strtod_l+0x436>
801a8be: d0cb beq.n 801a858 <_strtod_l+0x4e0>
801a8c0: f1ca 0a00 rsb sl, sl, #0
801a8c4: ea4f 162a mov.w r6, sl, asr #4
801a8c8: f01a 0a0f ands.w sl, sl, #15
801a8cc: d10d bne.n 801a8ea <_strtod_l+0x572>
801a8ce: 2e1f cmp r6, #31
801a8d0: dd2e ble.n 801a930 <_strtod_l+0x5b8>
801a8d2: 2400 movs r4, #0
801a8d4: 9405 str r4, [sp, #20]
801a8d6: 940e str r4, [sp, #56] @ 0x38
801a8d8: 9406 str r4, [sp, #24]
801a8da: 9a04 ldr r2, [sp, #16]
801a8dc: 2322 movs r3, #34 @ 0x22
801a8de: f04f 0800 mov.w r8, #0
801a8e2: f04f 0900 mov.w r9, #0
801a8e6: 6013 str r3, [r2, #0]
801a8e8: e7c4 b.n 801a874 <_strtod_l+0x4fc>
801a8ea: 4b0c ldr r3, [pc, #48] @ (801a91c <_strtod_l+0x5a4>)
801a8ec: eb03 03ca add.w r3, r3, sl, lsl #3
801a8f0: 4640 mov r0, r8
801a8f2: 4649 mov r1, r9
801a8f4: e9d3 2300 ldrd r2, r3, [r3]
801a8f8: f7e5 ff80 bl 80007fc <__aeabi_ddiv>
801a8fc: 4680 mov r8, r0
801a8fe: 4689 mov r9, r1
801a900: 2e00 cmp r6, #0
801a902: d0a9 beq.n 801a858 <_strtod_l+0x4e0>
801a904: e7e3 b.n 801a8ce <_strtod_l+0x556>
801a906: bf00 nop
801a908: 0801c7c9 .word 0x0801c7c9
801a90c: 0801ca90 .word 0x0801ca90
801a910: 0801c7c1 .word 0x0801c7c1
801a914: 0801c7f8 .word 0x0801c7f8
801a918: 0801c931 .word 0x0801c931
801a91c: 0801c9c8 .word 0x0801c9c8
801a920: 0801c9a0 .word 0x0801c9a0
801a924: 7ff00000 .word 0x7ff00000
801a928: 7ca00000 .word 0x7ca00000
801a92c: 7fefffff .word 0x7fefffff
801a930: f016 0310 ands.w r3, r6, #16
801a934: bf18 it ne
801a936: 236a movne r3, #106 @ 0x6a
801a938: 4f76 ldr r7, [pc, #472] @ (801ab14 <_strtod_l+0x79c>)
801a93a: 9307 str r3, [sp, #28]
801a93c: 4640 mov r0, r8
801a93e: 4649 mov r1, r9
801a940: 2300 movs r3, #0
801a942: 07f2 lsls r2, r6, #31
801a944: d504 bpl.n 801a950 <_strtod_l+0x5d8>
801a946: e9d7 2300 ldrd r2, r3, [r7]
801a94a: f7e5 fe2d bl 80005a8 <__aeabi_dmul>
801a94e: 2301 movs r3, #1
801a950: 1076 asrs r6, r6, #1
801a952: f107 0708 add.w r7, r7, #8
801a956: d1f4 bne.n 801a942 <_strtod_l+0x5ca>
801a958: b10b cbz r3, 801a95e <_strtod_l+0x5e6>
801a95a: 4680 mov r8, r0
801a95c: 4689 mov r9, r1
801a95e: 9b07 ldr r3, [sp, #28]
801a960: b1b3 cbz r3, 801a990 <_strtod_l+0x618>
801a962: f3c9 520a ubfx r2, r9, #20, #11
801a966: f1c2 036b rsb r3, r2, #107 @ 0x6b
801a96a: 2b00 cmp r3, #0
801a96c: 4649 mov r1, r9
801a96e: dd0f ble.n 801a990 <_strtod_l+0x618>
801a970: 2b1f cmp r3, #31
801a972: dd57 ble.n 801aa24 <_strtod_l+0x6ac>
801a974: 2b34 cmp r3, #52 @ 0x34
801a976: bfde ittt le
801a978: f04f 33ff movle.w r3, #4294967295 @ 0xffffffff
801a97c: f1c2 024b rsble r2, r2, #75 @ 0x4b
801a980: 4093 lslle r3, r2
801a982: f04f 0800 mov.w r8, #0
801a986: bfcc ite gt
801a988: f04f 795c movgt.w r9, #57671680 @ 0x3700000
801a98c: ea03 0901 andle.w r9, r3, r1
801a990: 2200 movs r2, #0
801a992: 2300 movs r3, #0
801a994: 4640 mov r0, r8
801a996: 4649 mov r1, r9
801a998: f7e6 f86e bl 8000a78 <__aeabi_dcmpeq>
801a99c: 2800 cmp r0, #0
801a99e: d198 bne.n 801a8d2 <_strtod_l+0x55a>
801a9a0: 9b0e ldr r3, [sp, #56] @ 0x38
801a9a2: 9300 str r3, [sp, #0]
801a9a4: 9804 ldr r0, [sp, #16]
801a9a6: 4623 mov r3, r4
801a9a8: 465a mov r2, fp
801a9aa: 4629 mov r1, r5
801a9ac: f7ff f8b2 bl 8019b14 <__s2b>
801a9b0: 900e str r0, [sp, #56] @ 0x38
801a9b2: 2800 cmp r0, #0
801a9b4: f43f af53 beq.w 801a85e <_strtod_l+0x4e6>
801a9b8: e9dd 2305 ldrd r2, r3, [sp, #20]
801a9bc: 1a9b subs r3, r3, r2
801a9be: 9a0a ldr r2, [sp, #40] @ 0x28
801a9c0: 2a00 cmp r2, #0
801a9c2: bfa8 it ge
801a9c4: 2300 movge r3, #0
801a9c6: 9312 str r3, [sp, #72] @ 0x48
801a9c8: 2400 movs r4, #0
801a9ca: ea22 73e2 bic.w r3, r2, r2, asr #31
801a9ce: 9314 str r3, [sp, #80] @ 0x50
801a9d0: 9405 str r4, [sp, #20]
801a9d2: 9b0e ldr r3, [sp, #56] @ 0x38
801a9d4: 9804 ldr r0, [sp, #16]
801a9d6: 6859 ldr r1, [r3, #4]
801a9d8: f7fe fff6 bl 80199c8 <_Balloc>
801a9dc: 9006 str r0, [sp, #24]
801a9de: 2800 cmp r0, #0
801a9e0: f43f af41 beq.w 801a866 <_strtod_l+0x4ee>
801a9e4: 9b0e ldr r3, [sp, #56] @ 0x38
801a9e6: 691a ldr r2, [r3, #16]
801a9e8: 3202 adds r2, #2
801a9ea: f103 010c add.w r1, r3, #12
801a9ee: 0092 lsls r2, r2, #2
801a9f0: 300c adds r0, #12
801a9f2: f7fe f86e bl 8018ad2 <memcpy>
801a9f6: ec49 8b10 vmov d0, r8, r9
801a9fa: 9804 ldr r0, [sp, #16]
801a9fc: aa1a add r2, sp, #104 @ 0x68
801a9fe: a919 add r1, sp, #100 @ 0x64
801aa00: e9cd 890c strd r8, r9, [sp, #48] @ 0x30
801aa04: f7ff fbca bl 801a19c <__d2b>
801aa08: 9018 str r0, [sp, #96] @ 0x60
801aa0a: 2800 cmp r0, #0
801aa0c: f43f af2b beq.w 801a866 <_strtod_l+0x4ee>
801aa10: 9804 ldr r0, [sp, #16]
801aa12: 2101 movs r1, #1
801aa14: f7ff f914 bl 8019c40 <__i2b>
801aa18: 9005 str r0, [sp, #20]
801aa1a: 4603 mov r3, r0
801aa1c: b948 cbnz r0, 801aa32 <_strtod_l+0x6ba>
801aa1e: 2300 movs r3, #0
801aa20: 9305 str r3, [sp, #20]
801aa22: e720 b.n 801a866 <_strtod_l+0x4ee>
801aa24: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
801aa28: fa02 f303 lsl.w r3, r2, r3
801aa2c: ea03 0808 and.w r8, r3, r8
801aa30: e7ae b.n 801a990 <_strtod_l+0x618>
801aa32: 9d19 ldr r5, [sp, #100] @ 0x64
801aa34: 9a1a ldr r2, [sp, #104] @ 0x68
801aa36: 2d00 cmp r5, #0
801aa38: bfab itete ge
801aa3a: 9b12 ldrge r3, [sp, #72] @ 0x48
801aa3c: 9b14 ldrlt r3, [sp, #80] @ 0x50
801aa3e: 9e14 ldrge r6, [sp, #80] @ 0x50
801aa40: 9f12 ldrlt r7, [sp, #72] @ 0x48
801aa42: bfac ite ge
801aa44: 18ef addge r7, r5, r3
801aa46: 1b5e sublt r6, r3, r5
801aa48: 9b07 ldr r3, [sp, #28]
801aa4a: 1aed subs r5, r5, r3
801aa4c: 4415 add r5, r2
801aa4e: 4b32 ldr r3, [pc, #200] @ (801ab18 <_strtod_l+0x7a0>)
801aa50: 3d01 subs r5, #1
801aa52: 429d cmp r5, r3
801aa54: f1c2 0236 rsb r2, r2, #54 @ 0x36
801aa58: da4f bge.n 801aafa <_strtod_l+0x782>
801aa5a: 1b5b subs r3, r3, r5
801aa5c: 2b1f cmp r3, #31
801aa5e: eba2 0203 sub.w r2, r2, r3
801aa62: f04f 0101 mov.w r1, #1
801aa66: dc3c bgt.n 801aae2 <_strtod_l+0x76a>
801aa68: fa01 fa03 lsl.w sl, r1, r3
801aa6c: f04f 0b00 mov.w fp, #0
801aa70: 18bd adds r5, r7, r2
801aa72: 9b07 ldr r3, [sp, #28]
801aa74: 42af cmp r7, r5
801aa76: 4416 add r6, r2
801aa78: 441e add r6, r3
801aa7a: 463b mov r3, r7
801aa7c: bfa8 it ge
801aa7e: 462b movge r3, r5
801aa80: 42b3 cmp r3, r6
801aa82: bfa8 it ge
801aa84: 4633 movge r3, r6
801aa86: 2b00 cmp r3, #0
801aa88: bfc2 ittt gt
801aa8a: 1aed subgt r5, r5, r3
801aa8c: 1af6 subgt r6, r6, r3
801aa8e: 1aff subgt r7, r7, r3
801aa90: 9b12 ldr r3, [sp, #72] @ 0x48
801aa92: 2b00 cmp r3, #0
801aa94: dd16 ble.n 801aac4 <_strtod_l+0x74c>
801aa96: e9dd 0104 ldrd r0, r1, [sp, #16]
801aa9a: 461a mov r2, r3
801aa9c: f7ff f990 bl 8019dc0 <__pow5mult>
801aaa0: 9005 str r0, [sp, #20]
801aaa2: 2800 cmp r0, #0
801aaa4: d0bb beq.n 801aa1e <_strtod_l+0x6a6>
801aaa6: 4601 mov r1, r0
801aaa8: 9a18 ldr r2, [sp, #96] @ 0x60
801aaaa: 9804 ldr r0, [sp, #16]
801aaac: f7ff f8de bl 8019c6c <__multiply>
801aab0: 900f str r0, [sp, #60] @ 0x3c
801aab2: 2800 cmp r0, #0
801aab4: f43f aed7 beq.w 801a866 <_strtod_l+0x4ee>
801aab8: 9918 ldr r1, [sp, #96] @ 0x60
801aaba: 9804 ldr r0, [sp, #16]
801aabc: f7fe ffc2 bl 8019a44 <_Bfree>
801aac0: 9b0f ldr r3, [sp, #60] @ 0x3c
801aac2: 9318 str r3, [sp, #96] @ 0x60
801aac4: 2d00 cmp r5, #0
801aac6: dc1b bgt.n 801ab00 <_strtod_l+0x788>
801aac8: 9b0a ldr r3, [sp, #40] @ 0x28
801aaca: 2b00 cmp r3, #0
801aacc: dd26 ble.n 801ab1c <_strtod_l+0x7a4>
801aace: 9a14 ldr r2, [sp, #80] @ 0x50
801aad0: 9906 ldr r1, [sp, #24]
801aad2: 9804 ldr r0, [sp, #16]
801aad4: f7ff f974 bl 8019dc0 <__pow5mult>
801aad8: 9006 str r0, [sp, #24]
801aada: b9f8 cbnz r0, 801ab1c <_strtod_l+0x7a4>
801aadc: 2300 movs r3, #0
801aade: 9306 str r3, [sp, #24]
801aae0: e6c1 b.n 801a866 <_strtod_l+0x4ee>
801aae2: f1c5 457f rsb r5, r5, #4278190080 @ 0xff000000
801aae6: f505 057f add.w r5, r5, #16711680 @ 0xff0000
801aaea: f505 457b add.w r5, r5, #64256 @ 0xfb00
801aaee: 35e2 adds r5, #226 @ 0xe2
801aaf0: fa01 fb05 lsl.w fp, r1, r5
801aaf4: f04f 0a01 mov.w sl, #1
801aaf8: e7ba b.n 801aa70 <_strtod_l+0x6f8>
801aafa: f04f 0b00 mov.w fp, #0
801aafe: e7f9 b.n 801aaf4 <_strtod_l+0x77c>
801ab00: 9918 ldr r1, [sp, #96] @ 0x60
801ab02: 9804 ldr r0, [sp, #16]
801ab04: 462a mov r2, r5
801ab06: f7ff f9b7 bl 8019e78 <__lshift>
801ab0a: 9018 str r0, [sp, #96] @ 0x60
801ab0c: 2800 cmp r0, #0
801ab0e: d1db bne.n 801aac8 <_strtod_l+0x750>
801ab10: e6a9 b.n 801a866 <_strtod_l+0x4ee>
801ab12: bf00 nop
801ab14: 0801cab8 .word 0x0801cab8
801ab18: fffffc02 .word 0xfffffc02
801ab1c: 2e00 cmp r6, #0
801ab1e: dd07 ble.n 801ab30 <_strtod_l+0x7b8>
801ab20: 9906 ldr r1, [sp, #24]
801ab22: 9804 ldr r0, [sp, #16]
801ab24: 4632 mov r2, r6
801ab26: f7ff f9a7 bl 8019e78 <__lshift>
801ab2a: 9006 str r0, [sp, #24]
801ab2c: 2800 cmp r0, #0
801ab2e: d0d5 beq.n 801aadc <_strtod_l+0x764>
801ab30: 2f00 cmp r7, #0
801ab32: dd08 ble.n 801ab46 <_strtod_l+0x7ce>
801ab34: e9dd 0104 ldrd r0, r1, [sp, #16]
801ab38: 463a mov r2, r7
801ab3a: f7ff f99d bl 8019e78 <__lshift>
801ab3e: 9005 str r0, [sp, #20]
801ab40: 2800 cmp r0, #0
801ab42: f43f ae90 beq.w 801a866 <_strtod_l+0x4ee>
801ab46: 9a06 ldr r2, [sp, #24]
801ab48: 9918 ldr r1, [sp, #96] @ 0x60
801ab4a: 9804 ldr r0, [sp, #16]
801ab4c: f7ff fa1e bl 8019f8c <__mdiff>
801ab50: 4604 mov r4, r0
801ab52: 2800 cmp r0, #0
801ab54: f43f ae87 beq.w 801a866 <_strtod_l+0x4ee>
801ab58: 68c3 ldr r3, [r0, #12]
801ab5a: 930f str r3, [sp, #60] @ 0x3c
801ab5c: 2300 movs r3, #0
801ab5e: 9905 ldr r1, [sp, #20]
801ab60: 60c3 str r3, [r0, #12]
801ab62: f7ff f9f7 bl 8019f54 <__mcmp>
801ab66: 2800 cmp r0, #0
801ab68: da3c bge.n 801abe4 <_strtod_l+0x86c>
801ab6a: 9b0f ldr r3, [sp, #60] @ 0x3c
801ab6c: ea53 0308 orrs.w r3, r3, r8
801ab70: d15e bne.n 801ac30 <_strtod_l+0x8b8>
801ab72: f3c9 0313 ubfx r3, r9, #0, #20
801ab76: 464d mov r5, r9
801ab78: 2b00 cmp r3, #0
801ab7a: d159 bne.n 801ac30 <_strtod_l+0x8b8>
801ab7c: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
801ab80: 0d1b lsrs r3, r3, #20
801ab82: 051b lsls r3, r3, #20
801ab84: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000
801ab88: d952 bls.n 801ac30 <_strtod_l+0x8b8>
801ab8a: 6963 ldr r3, [r4, #20]
801ab8c: b913 cbnz r3, 801ab94 <_strtod_l+0x81c>
801ab8e: 6923 ldr r3, [r4, #16]
801ab90: 2b01 cmp r3, #1
801ab92: dd4d ble.n 801ac30 <_strtod_l+0x8b8>
801ab94: 4621 mov r1, r4
801ab96: 2201 movs r2, #1
801ab98: 9804 ldr r0, [sp, #16]
801ab9a: f7ff f96d bl 8019e78 <__lshift>
801ab9e: 9905 ldr r1, [sp, #20]
801aba0: 4604 mov r4, r0
801aba2: f7ff f9d7 bl 8019f54 <__mcmp>
801aba6: 2800 cmp r0, #0
801aba8: dd42 ble.n 801ac30 <_strtod_l+0x8b8>
801abaa: 4bad ldr r3, [pc, #692] @ (801ae60 <_strtod_l+0xae8>)
801abac: 9a07 ldr r2, [sp, #28]
801abae: 402b ands r3, r5
801abb0: 2a00 cmp r2, #0
801abb2: d05f beq.n 801ac74 <_strtod_l+0x8fc>
801abb4: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000
801abb8: d85c bhi.n 801ac74 <_strtod_l+0x8fc>
801abba: f1b3 7f5c cmp.w r3, #57671680 @ 0x3700000
801abbe: f67f ae8c bls.w 801a8da <_strtod_l+0x562>
801abc2: 4ba8 ldr r3, [pc, #672] @ (801ae64 <_strtod_l+0xaec>)
801abc4: 4640 mov r0, r8
801abc6: 4649 mov r1, r9
801abc8: 2200 movs r2, #0
801abca: f7e5 fced bl 80005a8 <__aeabi_dmul>
801abce: 4ba4 ldr r3, [pc, #656] @ (801ae60 <_strtod_l+0xae8>)
801abd0: 400b ands r3, r1
801abd2: 4680 mov r8, r0
801abd4: 4689 mov r9, r1
801abd6: 2b00 cmp r3, #0
801abd8: f47f ae50 bne.w 801a87c <_strtod_l+0x504>
801abdc: 9a04 ldr r2, [sp, #16]
801abde: 2322 movs r3, #34 @ 0x22
801abe0: 6013 str r3, [r2, #0]
801abe2: e64b b.n 801a87c <_strtod_l+0x504>
801abe4: 464d mov r5, r9
801abe6: d162 bne.n 801acae <_strtod_l+0x936>
801abe8: 9a0f ldr r2, [sp, #60] @ 0x3c
801abea: f3c9 0313 ubfx r3, r9, #0, #20
801abee: b342 cbz r2, 801ac42 <_strtod_l+0x8ca>
801abf0: 4a9d ldr r2, [pc, #628] @ (801ae68 <_strtod_l+0xaf0>)
801abf2: 4293 cmp r3, r2
801abf4: d128 bne.n 801ac48 <_strtod_l+0x8d0>
801abf6: 9b07 ldr r3, [sp, #28]
801abf8: 4641 mov r1, r8
801abfa: b1eb cbz r3, 801ac38 <_strtod_l+0x8c0>
801abfc: 4b98 ldr r3, [pc, #608] @ (801ae60 <_strtod_l+0xae8>)
801abfe: 402b ands r3, r5
801ac00: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000
801ac04: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
801ac08: d819 bhi.n 801ac3e <_strtod_l+0x8c6>
801ac0a: 0d1b lsrs r3, r3, #20
801ac0c: f1c3 036b rsb r3, r3, #107 @ 0x6b
801ac10: fa02 f303 lsl.w r3, r2, r3
801ac14: 4299 cmp r1, r3
801ac16: d117 bne.n 801ac48 <_strtod_l+0x8d0>
801ac18: 4b94 ldr r3, [pc, #592] @ (801ae6c <_strtod_l+0xaf4>)
801ac1a: 429d cmp r5, r3
801ac1c: d102 bne.n 801ac24 <_strtod_l+0x8ac>
801ac1e: 3101 adds r1, #1
801ac20: f43f ae21 beq.w 801a866 <_strtod_l+0x4ee>
801ac24: 4b8e ldr r3, [pc, #568] @ (801ae60 <_strtod_l+0xae8>)
801ac26: 402b ands r3, r5
801ac28: f503 1980 add.w r9, r3, #1048576 @ 0x100000
801ac2c: f04f 0800 mov.w r8, #0
801ac30: 9b07 ldr r3, [sp, #28]
801ac32: 2b00 cmp r3, #0
801ac34: d1c5 bne.n 801abc2 <_strtod_l+0x84a>
801ac36: e621 b.n 801a87c <_strtod_l+0x504>
801ac38: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
801ac3c: e7ea b.n 801ac14 <_strtod_l+0x89c>
801ac3e: 4613 mov r3, r2
801ac40: e7e8 b.n 801ac14 <_strtod_l+0x89c>
801ac42: ea53 0308 orrs.w r3, r3, r8
801ac46: d0b0 beq.n 801abaa <_strtod_l+0x832>
801ac48: f1bb 0f00 cmp.w fp, #0
801ac4c: d01b beq.n 801ac86 <_strtod_l+0x90e>
801ac4e: ea1b 0f05 tst.w fp, r5
801ac52: d0ed beq.n 801ac30 <_strtod_l+0x8b8>
801ac54: 9b0f ldr r3, [sp, #60] @ 0x3c
801ac56: 9a07 ldr r2, [sp, #28]
801ac58: 4640 mov r0, r8
801ac5a: 4649 mov r1, r9
801ac5c: b1b3 cbz r3, 801ac8c <_strtod_l+0x914>
801ac5e: f7ff fb6b bl 801a338 <sulp>
801ac62: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30
801ac66: ec53 2b10 vmov r2, r3, d0
801ac6a: f7e5 fae7 bl 800023c <__adddf3>
801ac6e: 4680 mov r8, r0
801ac70: 4689 mov r9, r1
801ac72: e7dd b.n 801ac30 <_strtod_l+0x8b8>
801ac74: f5a3 1380 sub.w r3, r3, #1048576 @ 0x100000
801ac78: ea6f 5913 mvn.w r9, r3, lsr #20
801ac7c: ea6f 5909 mvn.w r9, r9, lsl #20
801ac80: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff
801ac84: e7d4 b.n 801ac30 <_strtod_l+0x8b8>
801ac86: ea1a 0f08 tst.w sl, r8
801ac8a: e7e2 b.n 801ac52 <_strtod_l+0x8da>
801ac8c: f7ff fb54 bl 801a338 <sulp>
801ac90: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30
801ac94: ec53 2b10 vmov r2, r3, d0
801ac98: f7e5 face bl 8000238 <__aeabi_dsub>
801ac9c: 2200 movs r2, #0
801ac9e: 2300 movs r3, #0
801aca0: 4680 mov r8, r0
801aca2: 4689 mov r9, r1
801aca4: f7e5 fee8 bl 8000a78 <__aeabi_dcmpeq>
801aca8: 2800 cmp r0, #0
801acaa: d0c1 beq.n 801ac30 <_strtod_l+0x8b8>
801acac: e615 b.n 801a8da <_strtod_l+0x562>
801acae: 9905 ldr r1, [sp, #20]
801acb0: 4620 mov r0, r4
801acb2: f7ff facb bl 801a24c <__ratio>
801acb6: ec57 6b10 vmov r6, r7, d0
801acba: 2200 movs r2, #0
801acbc: f04f 4380 mov.w r3, #1073741824 @ 0x40000000
801acc0: 4630 mov r0, r6
801acc2: 4639 mov r1, r7
801acc4: f7e5 feec bl 8000aa0 <__aeabi_dcmple>
801acc8: 2800 cmp r0, #0
801acca: d070 beq.n 801adae <_strtod_l+0xa36>
801accc: 9b0f ldr r3, [sp, #60] @ 0x3c
801acce: 2b00 cmp r3, #0
801acd0: d17b bne.n 801adca <_strtod_l+0xa52>
801acd2: f1b8 0f00 cmp.w r8, #0
801acd6: d156 bne.n 801ad86 <_strtod_l+0xa0e>
801acd8: f3c9 0313 ubfx r3, r9, #0, #20
801acdc: 2b00 cmp r3, #0
801acde: d158 bne.n 801ad92 <_strtod_l+0xa1a>
801ace0: 4b63 ldr r3, [pc, #396] @ (801ae70 <_strtod_l+0xaf8>)
801ace2: 2200 movs r2, #0
801ace4: 4630 mov r0, r6
801ace6: 4639 mov r1, r7
801ace8: f7e5 fed0 bl 8000a8c <__aeabi_dcmplt>
801acec: 2800 cmp r0, #0
801acee: d159 bne.n 801ada4 <_strtod_l+0xa2c>
801acf0: 4b60 ldr r3, [pc, #384] @ (801ae74 <_strtod_l+0xafc>)
801acf2: 2200 movs r2, #0
801acf4: 4630 mov r0, r6
801acf6: 4639 mov r1, r7
801acf8: f7e5 fc56 bl 80005a8 <__aeabi_dmul>
801acfc: 4682 mov sl, r0
801acfe: 468b mov fp, r1
801ad00: f10b 4300 add.w r3, fp, #2147483648 @ 0x80000000
801ad04: f8cd a020 str.w sl, [sp, #32]
801ad08: 9309 str r3, [sp, #36] @ 0x24
801ad0a: 4b55 ldr r3, [pc, #340] @ (801ae60 <_strtod_l+0xae8>)
801ad0c: 4a54 ldr r2, [pc, #336] @ (801ae60 <_strtod_l+0xae8>)
801ad0e: 402b ands r3, r5
801ad10: 9313 str r3, [sp, #76] @ 0x4c
801ad12: 4b59 ldr r3, [pc, #356] @ (801ae78 <_strtod_l+0xb00>)
801ad14: 402a ands r2, r5
801ad16: 429a cmp r2, r3
801ad18: e9dd 6708 ldrd r6, r7, [sp, #32]
801ad1c: f040 80b0 bne.w 801ae80 <_strtod_l+0xb08>
801ad20: f1a5 7954 sub.w r9, r5, #55574528 @ 0x3500000
801ad24: ec49 8b10 vmov d0, r8, r9
801ad28: f7ff f9c8 bl 801a0bc <__ulp>
801ad2c: e9dd 2308 ldrd r2, r3, [sp, #32]
801ad30: ec51 0b10 vmov r0, r1, d0
801ad34: f7e5 fc38 bl 80005a8 <__aeabi_dmul>
801ad38: 4642 mov r2, r8
801ad3a: 464b mov r3, r9
801ad3c: f7e5 fa7e bl 800023c <__adddf3>
801ad40: 4d47 ldr r5, [pc, #284] @ (801ae60 <_strtod_l+0xae8>)
801ad42: 4a4e ldr r2, [pc, #312] @ (801ae7c <_strtod_l+0xb04>)
801ad44: 400d ands r5, r1
801ad46: 4295 cmp r5, r2
801ad48: 4680 mov r8, r0
801ad4a: d945 bls.n 801add8 <_strtod_l+0xa60>
801ad4c: 9a0d ldr r2, [sp, #52] @ 0x34
801ad4e: 4b47 ldr r3, [pc, #284] @ (801ae6c <_strtod_l+0xaf4>)
801ad50: 429a cmp r2, r3
801ad52: d103 bne.n 801ad5c <_strtod_l+0x9e4>
801ad54: 9b0c ldr r3, [sp, #48] @ 0x30
801ad56: 3301 adds r3, #1
801ad58: f43f ad85 beq.w 801a866 <_strtod_l+0x4ee>
801ad5c: f8df 910c ldr.w r9, [pc, #268] @ 801ae6c <_strtod_l+0xaf4>
801ad60: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff
801ad64: 9918 ldr r1, [sp, #96] @ 0x60
801ad66: 9804 ldr r0, [sp, #16]
801ad68: f7fe fe6c bl 8019a44 <_Bfree>
801ad6c: 9906 ldr r1, [sp, #24]
801ad6e: 9804 ldr r0, [sp, #16]
801ad70: f7fe fe68 bl 8019a44 <_Bfree>
801ad74: e9dd 0104 ldrd r0, r1, [sp, #16]
801ad78: f7fe fe64 bl 8019a44 <_Bfree>
801ad7c: 9804 ldr r0, [sp, #16]
801ad7e: 4621 mov r1, r4
801ad80: f7fe fe60 bl 8019a44 <_Bfree>
801ad84: e625 b.n 801a9d2 <_strtod_l+0x65a>
801ad86: f1b8 0f01 cmp.w r8, #1
801ad8a: d102 bne.n 801ad92 <_strtod_l+0xa1a>
801ad8c: 2d00 cmp r5, #0
801ad8e: f43f ada4 beq.w 801a8da <_strtod_l+0x562>
801ad92: ed9f 7b2b vldr d7, [pc, #172] @ 801ae40 <_strtod_l+0xac8>
801ad96: f8df b0d8 ldr.w fp, [pc, #216] @ 801ae70 <_strtod_l+0xaf8>
801ad9a: ed8d 7b08 vstr d7, [sp, #32]
801ad9e: f04f 0a00 mov.w sl, #0
801ada2: e7b2 b.n 801ad0a <_strtod_l+0x992>
801ada4: f8df b0cc ldr.w fp, [pc, #204] @ 801ae74 <_strtod_l+0xafc>
801ada8: f04f 0a00 mov.w sl, #0
801adac: e7a8 b.n 801ad00 <_strtod_l+0x988>
801adae: 4b31 ldr r3, [pc, #196] @ (801ae74 <_strtod_l+0xafc>)
801adb0: 2200 movs r2, #0
801adb2: 4630 mov r0, r6
801adb4: 4639 mov r1, r7
801adb6: f7e5 fbf7 bl 80005a8 <__aeabi_dmul>
801adba: 9b0f ldr r3, [sp, #60] @ 0x3c
801adbc: 4682 mov sl, r0
801adbe: 468b mov fp, r1
801adc0: 2b00 cmp r3, #0
801adc2: d09d beq.n 801ad00 <_strtod_l+0x988>
801adc4: e9cd ab08 strd sl, fp, [sp, #32]
801adc8: e79f b.n 801ad0a <_strtod_l+0x992>
801adca: ed9f 7b1f vldr d7, [pc, #124] @ 801ae48 <_strtod_l+0xad0>
801adce: ed8d 7b08 vstr d7, [sp, #32]
801add2: ec5b ab17 vmov sl, fp, d7
801add6: e798 b.n 801ad0a <_strtod_l+0x992>
801add8: f101 7954 add.w r9, r1, #55574528 @ 0x3500000
801addc: 9b07 ldr r3, [sp, #28]
801adde: 2b00 cmp r3, #0
801ade0: d1c0 bne.n 801ad64 <_strtod_l+0x9ec>
801ade2: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
801ade6: 9a13 ldr r2, [sp, #76] @ 0x4c
801ade8: 0d1b lsrs r3, r3, #20
801adea: 051b lsls r3, r3, #20
801adec: 429a cmp r2, r3
801adee: d1b9 bne.n 801ad64 <_strtod_l+0x9ec>
801adf0: 4650 mov r0, sl
801adf2: 4659 mov r1, fp
801adf4: f7e5 ff20 bl 8000c38 <__aeabi_d2lz>
801adf8: f7e5 fba8 bl 800054c <__aeabi_l2d>
801adfc: 4602 mov r2, r0
801adfe: 460b mov r3, r1
801ae00: 4650 mov r0, sl
801ae02: 4659 mov r1, fp
801ae04: f7e5 fa18 bl 8000238 <__aeabi_dsub>
801ae08: 9a0f ldr r2, [sp, #60] @ 0x3c
801ae0a: f3c9 0313 ubfx r3, r9, #0, #20
801ae0e: ea43 0308 orr.w r3, r3, r8
801ae12: 4313 orrs r3, r2
801ae14: 4606 mov r6, r0
801ae16: 460f mov r7, r1
801ae18: d06b beq.n 801aef2 <_strtod_l+0xb7a>
801ae1a: a30d add r3, pc, #52 @ (adr r3, 801ae50 <_strtod_l+0xad8>)
801ae1c: e9d3 2300 ldrd r2, r3, [r3]
801ae20: f7e5 fe34 bl 8000a8c <__aeabi_dcmplt>
801ae24: 2800 cmp r0, #0
801ae26: f47f ad29 bne.w 801a87c <_strtod_l+0x504>
801ae2a: a30b add r3, pc, #44 @ (adr r3, 801ae58 <_strtod_l+0xae0>)
801ae2c: e9d3 2300 ldrd r2, r3, [r3]
801ae30: 4630 mov r0, r6
801ae32: 4639 mov r1, r7
801ae34: f7e5 fe48 bl 8000ac8 <__aeabi_dcmpgt>
801ae38: 2800 cmp r0, #0
801ae3a: d093 beq.n 801ad64 <_strtod_l+0x9ec>
801ae3c: e51e b.n 801a87c <_strtod_l+0x504>
801ae3e: bf00 nop
801ae40: 00000000 .word 0x00000000
801ae44: bff00000 .word 0xbff00000
801ae48: 00000000 .word 0x00000000
801ae4c: 3ff00000 .word 0x3ff00000
801ae50: 94a03595 .word 0x94a03595
801ae54: 3fdfffff .word 0x3fdfffff
801ae58: 35afe535 .word 0x35afe535
801ae5c: 3fe00000 .word 0x3fe00000
801ae60: 7ff00000 .word 0x7ff00000
801ae64: 39500000 .word 0x39500000
801ae68: 000fffff .word 0x000fffff
801ae6c: 7fefffff .word 0x7fefffff
801ae70: 3ff00000 .word 0x3ff00000
801ae74: 3fe00000 .word 0x3fe00000
801ae78: 7fe00000 .word 0x7fe00000
801ae7c: 7c9fffff .word 0x7c9fffff
801ae80: 9b07 ldr r3, [sp, #28]
801ae82: b313 cbz r3, 801aeca <_strtod_l+0xb52>
801ae84: 9b13 ldr r3, [sp, #76] @ 0x4c
801ae86: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000
801ae8a: d81e bhi.n 801aeca <_strtod_l+0xb52>
801ae8c: a324 add r3, pc, #144 @ (adr r3, 801af20 <_strtod_l+0xba8>)
801ae8e: e9d3 2300 ldrd r2, r3, [r3]
801ae92: 4650 mov r0, sl
801ae94: 4659 mov r1, fp
801ae96: f7e5 fe03 bl 8000aa0 <__aeabi_dcmple>
801ae9a: b190 cbz r0, 801aec2 <_strtod_l+0xb4a>
801ae9c: 4659 mov r1, fp
801ae9e: 4650 mov r0, sl
801aea0: f7e5 fe5a bl 8000b58 <__aeabi_d2uiz>
801aea4: 2801 cmp r0, #1
801aea6: bf38 it cc
801aea8: 2001 movcc r0, #1
801aeaa: f7e5 fb03 bl 80004b4 <__aeabi_ui2d>
801aeae: 9b0f ldr r3, [sp, #60] @ 0x3c
801aeb0: 4682 mov sl, r0
801aeb2: 468b mov fp, r1
801aeb4: b9d3 cbnz r3, 801aeec <_strtod_l+0xb74>
801aeb6: f101 4300 add.w r3, r1, #2147483648 @ 0x80000000
801aeba: 9010 str r0, [sp, #64] @ 0x40
801aebc: 9311 str r3, [sp, #68] @ 0x44
801aebe: e9dd 6710 ldrd r6, r7, [sp, #64] @ 0x40
801aec2: 9a13 ldr r2, [sp, #76] @ 0x4c
801aec4: f107 63d6 add.w r3, r7, #112197632 @ 0x6b00000
801aec8: 1a9f subs r7, r3, r2
801aeca: ed9d 0b0c vldr d0, [sp, #48] @ 0x30
801aece: f7ff f8f5 bl 801a0bc <__ulp>
801aed2: 4630 mov r0, r6
801aed4: ec53 2b10 vmov r2, r3, d0
801aed8: 4639 mov r1, r7
801aeda: f7e5 fb65 bl 80005a8 <__aeabi_dmul>
801aede: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30
801aee2: f7e5 f9ab bl 800023c <__adddf3>
801aee6: 4680 mov r8, r0
801aee8: 4689 mov r9, r1
801aeea: e777 b.n 801addc <_strtod_l+0xa64>
801aeec: e9cd ab10 strd sl, fp, [sp, #64] @ 0x40
801aef0: e7e5 b.n 801aebe <_strtod_l+0xb46>
801aef2: a30d add r3, pc, #52 @ (adr r3, 801af28 <_strtod_l+0xbb0>)
801aef4: e9d3 2300 ldrd r2, r3, [r3]
801aef8: f7e5 fdc8 bl 8000a8c <__aeabi_dcmplt>
801aefc: e79c b.n 801ae38 <_strtod_l+0xac0>
801aefe: 2300 movs r3, #0
801af00: 930b str r3, [sp, #44] @ 0x2c
801af02: 9a15 ldr r2, [sp, #84] @ 0x54
801af04: 9b17 ldr r3, [sp, #92] @ 0x5c
801af06: 6013 str r3, [r2, #0]
801af08: f7ff ba8c b.w 801a424 <_strtod_l+0xac>
801af0c: 2a65 cmp r2, #101 @ 0x65
801af0e: f43f ab6a beq.w 801a5e6 <_strtod_l+0x26e>
801af12: 2a45 cmp r2, #69 @ 0x45
801af14: f43f ab67 beq.w 801a5e6 <_strtod_l+0x26e>
801af18: 2301 movs r3, #1
801af1a: 9307 str r3, [sp, #28]
801af1c: f7ff bba1 b.w 801a662 <_strtod_l+0x2ea>
801af20: ffc00000 .word 0xffc00000
801af24: 41dfffff .word 0x41dfffff
801af28: 94a03595 .word 0x94a03595
801af2c: 3fcfffff .word 0x3fcfffff
0801af30 <_strtod_r>:
801af30: 4b01 ldr r3, [pc, #4] @ (801af38 <_strtod_r+0x8>)
801af32: f7ff ba21 b.w 801a378 <_strtod_l>
801af36: bf00 nop
801af38: 2000016c .word 0x2000016c
0801af3c <_strtol_l.isra.0>:
801af3c: 2b24 cmp r3, #36 @ 0x24
801af3e: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
801af42: 4686 mov lr, r0
801af44: 4690 mov r8, r2
801af46: d801 bhi.n 801af4c <_strtol_l.isra.0+0x10>
801af48: 2b01 cmp r3, #1
801af4a: d106 bne.n 801af5a <_strtol_l.isra.0+0x1e>
801af4c: f7fd fd94 bl 8018a78 <__errno>
801af50: 2316 movs r3, #22
801af52: 6003 str r3, [r0, #0]
801af54: 2000 movs r0, #0
801af56: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
801af5a: 4834 ldr r0, [pc, #208] @ (801b02c <_strtol_l.isra.0+0xf0>)
801af5c: 460d mov r5, r1
801af5e: 462a mov r2, r5
801af60: f815 4b01 ldrb.w r4, [r5], #1
801af64: 5d06 ldrb r6, [r0, r4]
801af66: f016 0608 ands.w r6, r6, #8
801af6a: d1f8 bne.n 801af5e <_strtol_l.isra.0+0x22>
801af6c: 2c2d cmp r4, #45 @ 0x2d
801af6e: d110 bne.n 801af92 <_strtol_l.isra.0+0x56>
801af70: 782c ldrb r4, [r5, #0]
801af72: 2601 movs r6, #1
801af74: 1c95 adds r5, r2, #2
801af76: f033 0210 bics.w r2, r3, #16
801af7a: d115 bne.n 801afa8 <_strtol_l.isra.0+0x6c>
801af7c: 2c30 cmp r4, #48 @ 0x30
801af7e: d10d bne.n 801af9c <_strtol_l.isra.0+0x60>
801af80: 782a ldrb r2, [r5, #0]
801af82: f002 02df and.w r2, r2, #223 @ 0xdf
801af86: 2a58 cmp r2, #88 @ 0x58
801af88: d108 bne.n 801af9c <_strtol_l.isra.0+0x60>
801af8a: 786c ldrb r4, [r5, #1]
801af8c: 3502 adds r5, #2
801af8e: 2310 movs r3, #16
801af90: e00a b.n 801afa8 <_strtol_l.isra.0+0x6c>
801af92: 2c2b cmp r4, #43 @ 0x2b
801af94: bf04 itt eq
801af96: 782c ldrbeq r4, [r5, #0]
801af98: 1c95 addeq r5, r2, #2
801af9a: e7ec b.n 801af76 <_strtol_l.isra.0+0x3a>
801af9c: 2b00 cmp r3, #0
801af9e: d1f6 bne.n 801af8e <_strtol_l.isra.0+0x52>
801afa0: 2c30 cmp r4, #48 @ 0x30
801afa2: bf14 ite ne
801afa4: 230a movne r3, #10
801afa6: 2308 moveq r3, #8
801afa8: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000
801afac: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff
801afb0: 2200 movs r2, #0
801afb2: fbbc f9f3 udiv r9, ip, r3
801afb6: 4610 mov r0, r2
801afb8: fb03 ca19 mls sl, r3, r9, ip
801afbc: f1a4 0730 sub.w r7, r4, #48 @ 0x30
801afc0: 2f09 cmp r7, #9
801afc2: d80f bhi.n 801afe4 <_strtol_l.isra.0+0xa8>
801afc4: 463c mov r4, r7
801afc6: 42a3 cmp r3, r4
801afc8: dd1b ble.n 801b002 <_strtol_l.isra.0+0xc6>
801afca: 1c57 adds r7, r2, #1
801afcc: d007 beq.n 801afde <_strtol_l.isra.0+0xa2>
801afce: 4581 cmp r9, r0
801afd0: d314 bcc.n 801affc <_strtol_l.isra.0+0xc0>
801afd2: d101 bne.n 801afd8 <_strtol_l.isra.0+0x9c>
801afd4: 45a2 cmp sl, r4
801afd6: db11 blt.n 801affc <_strtol_l.isra.0+0xc0>
801afd8: fb00 4003 mla r0, r0, r3, r4
801afdc: 2201 movs r2, #1
801afde: f815 4b01 ldrb.w r4, [r5], #1
801afe2: e7eb b.n 801afbc <_strtol_l.isra.0+0x80>
801afe4: f1a4 0741 sub.w r7, r4, #65 @ 0x41
801afe8: 2f19 cmp r7, #25
801afea: d801 bhi.n 801aff0 <_strtol_l.isra.0+0xb4>
801afec: 3c37 subs r4, #55 @ 0x37
801afee: e7ea b.n 801afc6 <_strtol_l.isra.0+0x8a>
801aff0: f1a4 0761 sub.w r7, r4, #97 @ 0x61
801aff4: 2f19 cmp r7, #25
801aff6: d804 bhi.n 801b002 <_strtol_l.isra.0+0xc6>
801aff8: 3c57 subs r4, #87 @ 0x57
801affa: e7e4 b.n 801afc6 <_strtol_l.isra.0+0x8a>
801affc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
801b000: e7ed b.n 801afde <_strtol_l.isra.0+0xa2>
801b002: 1c53 adds r3, r2, #1
801b004: d108 bne.n 801b018 <_strtol_l.isra.0+0xdc>
801b006: 2322 movs r3, #34 @ 0x22
801b008: f8ce 3000 str.w r3, [lr]
801b00c: 4660 mov r0, ip
801b00e: f1b8 0f00 cmp.w r8, #0
801b012: d0a0 beq.n 801af56 <_strtol_l.isra.0+0x1a>
801b014: 1e69 subs r1, r5, #1
801b016: e006 b.n 801b026 <_strtol_l.isra.0+0xea>
801b018: b106 cbz r6, 801b01c <_strtol_l.isra.0+0xe0>
801b01a: 4240 negs r0, r0
801b01c: f1b8 0f00 cmp.w r8, #0
801b020: d099 beq.n 801af56 <_strtol_l.isra.0+0x1a>
801b022: 2a00 cmp r2, #0
801b024: d1f6 bne.n 801b014 <_strtol_l.isra.0+0xd8>
801b026: f8c8 1000 str.w r1, [r8]
801b02a: e794 b.n 801af56 <_strtol_l.isra.0+0x1a>
801b02c: 0801cae1 .word 0x0801cae1
0801b030 <_strtol_r>:
801b030: f7ff bf84 b.w 801af3c <_strtol_l.isra.0>
0801b034 <__ssputs_r>:
801b034: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
801b038: 688e ldr r6, [r1, #8]
801b03a: 461f mov r7, r3
801b03c: 42be cmp r6, r7
801b03e: 4682 mov sl, r0
801b040: 460c mov r4, r1
801b042: 4690 mov r8, r2
801b044: 4633 mov r3, r6
801b046: d853 bhi.n 801b0f0 <__ssputs_r+0xbc>
801b048: f9b1 000c ldrsh.w r0, [r1, #12]
801b04c: f410 6f90 tst.w r0, #1152 @ 0x480
801b050: d02b beq.n 801b0aa <__ssputs_r+0x76>
801b052: 6965 ldr r5, [r4, #20]
801b054: 6823 ldr r3, [r4, #0]
801b056: 6909 ldr r1, [r1, #16]
801b058: eb05 0545 add.w r5, r5, r5, lsl #1
801b05c: eba3 0901 sub.w r9, r3, r1
801b060: eb05 75d5 add.w r5, r5, r5, lsr #31
801b064: 1c7b adds r3, r7, #1
801b066: 106d asrs r5, r5, #1
801b068: 444b add r3, r9
801b06a: 42ab cmp r3, r5
801b06c: 462a mov r2, r5
801b06e: bf84 itt hi
801b070: 461d movhi r5, r3
801b072: 462a movhi r2, r5
801b074: 0543 lsls r3, r0, #21
801b076: d527 bpl.n 801b0c8 <__ssputs_r+0x94>
801b078: 4611 mov r1, r2
801b07a: 4650 mov r0, sl
801b07c: f7fe fc18 bl 80198b0 <_malloc_r>
801b080: 4606 mov r6, r0
801b082: b358 cbz r0, 801b0dc <__ssputs_r+0xa8>
801b084: 6921 ldr r1, [r4, #16]
801b086: 464a mov r2, r9
801b088: f7fd fd23 bl 8018ad2 <memcpy>
801b08c: 89a3 ldrh r3, [r4, #12]
801b08e: f423 6390 bic.w r3, r3, #1152 @ 0x480
801b092: f043 0380 orr.w r3, r3, #128 @ 0x80
801b096: 81a3 strh r3, [r4, #12]
801b098: 6126 str r6, [r4, #16]
801b09a: 6165 str r5, [r4, #20]
801b09c: 444e add r6, r9
801b09e: eba5 0509 sub.w r5, r5, r9
801b0a2: 6026 str r6, [r4, #0]
801b0a4: 60a5 str r5, [r4, #8]
801b0a6: 463e mov r6, r7
801b0a8: 463b mov r3, r7
801b0aa: 461f mov r7, r3
801b0ac: 6820 ldr r0, [r4, #0]
801b0ae: 463a mov r2, r7
801b0b0: 4641 mov r1, r8
801b0b2: f000 fb5c bl 801b76e <memmove>
801b0b6: 68a3 ldr r3, [r4, #8]
801b0b8: 1b9b subs r3, r3, r6
801b0ba: 60a3 str r3, [r4, #8]
801b0bc: 6823 ldr r3, [r4, #0]
801b0be: 443b add r3, r7
801b0c0: 6023 str r3, [r4, #0]
801b0c2: 2000 movs r0, #0
801b0c4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
801b0c8: 4650 mov r0, sl
801b0ca: f000 ff34 bl 801bf36 <_realloc_r>
801b0ce: 4606 mov r6, r0
801b0d0: 2800 cmp r0, #0
801b0d2: d1e1 bne.n 801b098 <__ssputs_r+0x64>
801b0d4: 6921 ldr r1, [r4, #16]
801b0d6: 4650 mov r0, sl
801b0d8: f7fe fb76 bl 80197c8 <_free_r>
801b0dc: 230c movs r3, #12
801b0de: f8ca 3000 str.w r3, [sl]
801b0e2: 89a3 ldrh r3, [r4, #12]
801b0e4: f043 0340 orr.w r3, r3, #64 @ 0x40
801b0e8: 81a3 strh r3, [r4, #12]
801b0ea: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
801b0ee: e7e9 b.n 801b0c4 <__ssputs_r+0x90>
801b0f0: 463e mov r6, r7
801b0f2: e7db b.n 801b0ac <__ssputs_r+0x78>
0801b0f4 <_svfiprintf_r>:
801b0f4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
801b0f8: 461f mov r7, r3
801b0fa: 898b ldrh r3, [r1, #12]
801b0fc: 061b lsls r3, r3, #24
801b0fe: b09c sub sp, #112 @ 0x70
801b100: 4606 mov r6, r0
801b102: 460d mov r5, r1
801b104: 4614 mov r4, r2
801b106: d510 bpl.n 801b12a <_svfiprintf_r+0x36>
801b108: 690b ldr r3, [r1, #16]
801b10a: b973 cbnz r3, 801b12a <_svfiprintf_r+0x36>
801b10c: 2140 movs r1, #64 @ 0x40
801b10e: f7fe fbcf bl 80198b0 <_malloc_r>
801b112: 6028 str r0, [r5, #0]
801b114: 6128 str r0, [r5, #16]
801b116: b930 cbnz r0, 801b126 <_svfiprintf_r+0x32>
801b118: 230c movs r3, #12
801b11a: 6033 str r3, [r6, #0]
801b11c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
801b120: b01c add sp, #112 @ 0x70
801b122: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
801b126: 2340 movs r3, #64 @ 0x40
801b128: 616b str r3, [r5, #20]
801b12a: 2300 movs r3, #0
801b12c: 9309 str r3, [sp, #36] @ 0x24
801b12e: 2320 movs r3, #32
801b130: f88d 3029 strb.w r3, [sp, #41] @ 0x29
801b134: 9703 str r7, [sp, #12]
801b136: 2330 movs r3, #48 @ 0x30
801b138: 4f65 ldr r7, [pc, #404] @ (801b2d0 <_svfiprintf_r+0x1dc>)
801b13a: f88d 302a strb.w r3, [sp, #42] @ 0x2a
801b13e: f04f 0801 mov.w r8, #1
801b142: 4623 mov r3, r4
801b144: 4699 mov r9, r3
801b146: f813 2b01 ldrb.w r2, [r3], #1
801b14a: b10a cbz r2, 801b150 <_svfiprintf_r+0x5c>
801b14c: 2a25 cmp r2, #37 @ 0x25
801b14e: d1f9 bne.n 801b144 <_svfiprintf_r+0x50>
801b150: ebb9 0a04 subs.w sl, r9, r4
801b154: d00b beq.n 801b16e <_svfiprintf_r+0x7a>
801b156: 4653 mov r3, sl
801b158: 4622 mov r2, r4
801b15a: 4629 mov r1, r5
801b15c: 4630 mov r0, r6
801b15e: f7ff ff69 bl 801b034 <__ssputs_r>
801b162: 3001 adds r0, #1
801b164: f000 80a4 beq.w 801b2b0 <_svfiprintf_r+0x1bc>
801b168: 9a09 ldr r2, [sp, #36] @ 0x24
801b16a: 4452 add r2, sl
801b16c: 9209 str r2, [sp, #36] @ 0x24
801b16e: f899 3000 ldrb.w r3, [r9]
801b172: 2b00 cmp r3, #0
801b174: f000 809c beq.w 801b2b0 <_svfiprintf_r+0x1bc>
801b178: 2300 movs r3, #0
801b17a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
801b17e: e9cd 2305 strd r2, r3, [sp, #20]
801b182: f109 0901 add.w r9, r9, #1
801b186: 9304 str r3, [sp, #16]
801b188: 9307 str r3, [sp, #28]
801b18a: f88d 3053 strb.w r3, [sp, #83] @ 0x53
801b18e: 931a str r3, [sp, #104] @ 0x68
801b190: 464c mov r4, r9
801b192: 484f ldr r0, [pc, #316] @ (801b2d0 <_svfiprintf_r+0x1dc>)
801b194: f814 1b01 ldrb.w r1, [r4], #1
801b198: 2205 movs r2, #5
801b19a: f7e4 fff1 bl 8000180 <memchr>
801b19e: 9b04 ldr r3, [sp, #16]
801b1a0: b9d0 cbnz r0, 801b1d8 <_svfiprintf_r+0xe4>
801b1a2: 06d8 lsls r0, r3, #27
801b1a4: bf44 itt mi
801b1a6: 2220 movmi r2, #32
801b1a8: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53
801b1ac: 0719 lsls r1, r3, #28
801b1ae: bf44 itt mi
801b1b0: 222b movmi r2, #43 @ 0x2b
801b1b2: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53
801b1b6: f899 2000 ldrb.w r2, [r9]
801b1ba: 2a2a cmp r2, #42 @ 0x2a
801b1bc: d013 beq.n 801b1e6 <_svfiprintf_r+0xf2>
801b1be: 9a07 ldr r2, [sp, #28]
801b1c0: 464c mov r4, r9
801b1c2: 2000 movs r0, #0
801b1c4: f04f 0c0a mov.w ip, #10
801b1c8: 4621 mov r1, r4
801b1ca: f811 3b01 ldrb.w r3, [r1], #1
801b1ce: 3b30 subs r3, #48 @ 0x30
801b1d0: 2b09 cmp r3, #9
801b1d2: d949 bls.n 801b268 <_svfiprintf_r+0x174>
801b1d4: b968 cbnz r0, 801b1f2 <_svfiprintf_r+0xfe>
801b1d6: e013 b.n 801b200 <_svfiprintf_r+0x10c>
801b1d8: 1bc0 subs r0, r0, r7
801b1da: fa08 f000 lsl.w r0, r8, r0
801b1de: 4318 orrs r0, r3
801b1e0: 9004 str r0, [sp, #16]
801b1e2: 46a1 mov r9, r4
801b1e4: e7d4 b.n 801b190 <_svfiprintf_r+0x9c>
801b1e6: 9a03 ldr r2, [sp, #12]
801b1e8: 1d11 adds r1, r2, #4
801b1ea: 6812 ldr r2, [r2, #0]
801b1ec: 9103 str r1, [sp, #12]
801b1ee: 2a00 cmp r2, #0
801b1f0: db01 blt.n 801b1f6 <_svfiprintf_r+0x102>
801b1f2: 9207 str r2, [sp, #28]
801b1f4: e004 b.n 801b200 <_svfiprintf_r+0x10c>
801b1f6: 4252 negs r2, r2
801b1f8: f043 0302 orr.w r3, r3, #2
801b1fc: 9207 str r2, [sp, #28]
801b1fe: 9304 str r3, [sp, #16]
801b200: 7823 ldrb r3, [r4, #0]
801b202: 2b2e cmp r3, #46 @ 0x2e
801b204: d10a bne.n 801b21c <_svfiprintf_r+0x128>
801b206: 7863 ldrb r3, [r4, #1]
801b208: 2b2a cmp r3, #42 @ 0x2a
801b20a: d132 bne.n 801b272 <_svfiprintf_r+0x17e>
801b20c: 9b03 ldr r3, [sp, #12]
801b20e: 1d1a adds r2, r3, #4
801b210: 681b ldr r3, [r3, #0]
801b212: 9203 str r2, [sp, #12]
801b214: ea43 73e3 orr.w r3, r3, r3, asr #31
801b218: 3402 adds r4, #2
801b21a: 9305 str r3, [sp, #20]
801b21c: f8df 90c0 ldr.w r9, [pc, #192] @ 801b2e0 <_svfiprintf_r+0x1ec>
801b220: 7821 ldrb r1, [r4, #0]
801b222: 2203 movs r2, #3
801b224: 4648 mov r0, r9
801b226: f7e4 ffab bl 8000180 <memchr>
801b22a: b138 cbz r0, 801b23c <_svfiprintf_r+0x148>
801b22c: 9b04 ldr r3, [sp, #16]
801b22e: eba0 0009 sub.w r0, r0, r9
801b232: 2240 movs r2, #64 @ 0x40
801b234: 4082 lsls r2, r0
801b236: 4313 orrs r3, r2
801b238: 3401 adds r4, #1
801b23a: 9304 str r3, [sp, #16]
801b23c: f814 1b01 ldrb.w r1, [r4], #1
801b240: 4824 ldr r0, [pc, #144] @ (801b2d4 <_svfiprintf_r+0x1e0>)
801b242: f88d 1028 strb.w r1, [sp, #40] @ 0x28
801b246: 2206 movs r2, #6
801b248: f7e4 ff9a bl 8000180 <memchr>
801b24c: 2800 cmp r0, #0
801b24e: d035 beq.n 801b2bc <_svfiprintf_r+0x1c8>
801b250: 4821 ldr r0, [pc, #132] @ (801b2d8 <_svfiprintf_r+0x1e4>)
801b252: bb18 cbnz r0, 801b29c <_svfiprintf_r+0x1a8>
801b254: 9b03 ldr r3, [sp, #12]
801b256: 3307 adds r3, #7
801b258: f023 0307 bic.w r3, r3, #7
801b25c: 3308 adds r3, #8
801b25e: 9303 str r3, [sp, #12]
801b260: 9b09 ldr r3, [sp, #36] @ 0x24
801b262: 4403 add r3, r0
801b264: 9309 str r3, [sp, #36] @ 0x24
801b266: e76c b.n 801b142 <_svfiprintf_r+0x4e>
801b268: fb0c 3202 mla r2, ip, r2, r3
801b26c: 460c mov r4, r1
801b26e: 2001 movs r0, #1
801b270: e7aa b.n 801b1c8 <_svfiprintf_r+0xd4>
801b272: 2300 movs r3, #0
801b274: 3401 adds r4, #1
801b276: 9305 str r3, [sp, #20]
801b278: 4619 mov r1, r3
801b27a: f04f 0c0a mov.w ip, #10
801b27e: 4620 mov r0, r4
801b280: f810 2b01 ldrb.w r2, [r0], #1
801b284: 3a30 subs r2, #48 @ 0x30
801b286: 2a09 cmp r2, #9
801b288: d903 bls.n 801b292 <_svfiprintf_r+0x19e>
801b28a: 2b00 cmp r3, #0
801b28c: d0c6 beq.n 801b21c <_svfiprintf_r+0x128>
801b28e: 9105 str r1, [sp, #20]
801b290: e7c4 b.n 801b21c <_svfiprintf_r+0x128>
801b292: fb0c 2101 mla r1, ip, r1, r2
801b296: 4604 mov r4, r0
801b298: 2301 movs r3, #1
801b29a: e7f0 b.n 801b27e <_svfiprintf_r+0x18a>
801b29c: ab03 add r3, sp, #12
801b29e: 9300 str r3, [sp, #0]
801b2a0: 462a mov r2, r5
801b2a2: 4b0e ldr r3, [pc, #56] @ (801b2dc <_svfiprintf_r+0x1e8>)
801b2a4: a904 add r1, sp, #16
801b2a6: 4630 mov r0, r6
801b2a8: f7fc fba0 bl 80179ec <_printf_float>
801b2ac: 1c42 adds r2, r0, #1
801b2ae: d1d7 bne.n 801b260 <_svfiprintf_r+0x16c>
801b2b0: 89ab ldrh r3, [r5, #12]
801b2b2: 065b lsls r3, r3, #25
801b2b4: f53f af32 bmi.w 801b11c <_svfiprintf_r+0x28>
801b2b8: 9809 ldr r0, [sp, #36] @ 0x24
801b2ba: e731 b.n 801b120 <_svfiprintf_r+0x2c>
801b2bc: ab03 add r3, sp, #12
801b2be: 9300 str r3, [sp, #0]
801b2c0: 462a mov r2, r5
801b2c2: 4b06 ldr r3, [pc, #24] @ (801b2dc <_svfiprintf_r+0x1e8>)
801b2c4: a904 add r1, sp, #16
801b2c6: 4630 mov r0, r6
801b2c8: f7fc fe26 bl 8017f18 <_printf_i>
801b2cc: e7ee b.n 801b2ac <_svfiprintf_r+0x1b8>
801b2ce: bf00 nop
801b2d0: 0801c8dd .word 0x0801c8dd
801b2d4: 0801c8e7 .word 0x0801c8e7
801b2d8: 080179ed .word 0x080179ed
801b2dc: 0801b035 .word 0x0801b035
801b2e0: 0801c8e3 .word 0x0801c8e3
0801b2e4 <__sfputc_r>:
801b2e4: 6893 ldr r3, [r2, #8]
801b2e6: 3b01 subs r3, #1
801b2e8: 2b00 cmp r3, #0
801b2ea: b410 push {r4}
801b2ec: 6093 str r3, [r2, #8]
801b2ee: da08 bge.n 801b302 <__sfputc_r+0x1e>
801b2f0: 6994 ldr r4, [r2, #24]
801b2f2: 42a3 cmp r3, r4
801b2f4: db01 blt.n 801b2fa <__sfputc_r+0x16>
801b2f6: 290a cmp r1, #10
801b2f8: d103 bne.n 801b302 <__sfputc_r+0x1e>
801b2fa: f85d 4b04 ldr.w r4, [sp], #4
801b2fe: f7fd bad7 b.w 80188b0 <__swbuf_r>
801b302: 6813 ldr r3, [r2, #0]
801b304: 1c58 adds r0, r3, #1
801b306: 6010 str r0, [r2, #0]
801b308: 7019 strb r1, [r3, #0]
801b30a: 4608 mov r0, r1
801b30c: f85d 4b04 ldr.w r4, [sp], #4
801b310: 4770 bx lr
0801b312 <__sfputs_r>:
801b312: b5f8 push {r3, r4, r5, r6, r7, lr}
801b314: 4606 mov r6, r0
801b316: 460f mov r7, r1
801b318: 4614 mov r4, r2
801b31a: 18d5 adds r5, r2, r3
801b31c: 42ac cmp r4, r5
801b31e: d101 bne.n 801b324 <__sfputs_r+0x12>
801b320: 2000 movs r0, #0
801b322: e007 b.n 801b334 <__sfputs_r+0x22>
801b324: f814 1b01 ldrb.w r1, [r4], #1
801b328: 463a mov r2, r7
801b32a: 4630 mov r0, r6
801b32c: f7ff ffda bl 801b2e4 <__sfputc_r>
801b330: 1c43 adds r3, r0, #1
801b332: d1f3 bne.n 801b31c <__sfputs_r+0xa>
801b334: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
0801b338 <_vfiprintf_r>:
801b338: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
801b33c: 460d mov r5, r1
801b33e: b09c sub sp, #112 @ 0x70
801b340: 4614 mov r4, r2
801b342: 461f mov r7, r3
801b344: 4606 mov r6, r0
801b346: b118 cbz r0, 801b350 <_vfiprintf_r+0x18>
801b348: 6a03 ldr r3, [r0, #32]
801b34a: b90b cbnz r3, 801b350 <_vfiprintf_r+0x18>
801b34c: f7fd f9a4 bl 8018698 <__sinit>
801b350: 6e6b ldr r3, [r5, #100] @ 0x64
801b352: 07d9 lsls r1, r3, #31
801b354: d405 bmi.n 801b362 <_vfiprintf_r+0x2a>
801b356: 89ab ldrh r3, [r5, #12]
801b358: 059a lsls r2, r3, #22
801b35a: d402 bmi.n 801b362 <_vfiprintf_r+0x2a>
801b35c: 6da8 ldr r0, [r5, #88] @ 0x58
801b35e: f7fd fbb6 bl 8018ace <__retarget_lock_acquire_recursive>
801b362: 89ab ldrh r3, [r5, #12]
801b364: 071b lsls r3, r3, #28
801b366: d501 bpl.n 801b36c <_vfiprintf_r+0x34>
801b368: 692b ldr r3, [r5, #16]
801b36a: b99b cbnz r3, 801b394 <_vfiprintf_r+0x5c>
801b36c: 4629 mov r1, r5
801b36e: 4630 mov r0, r6
801b370: f7fd fadc bl 801892c <__swsetup_r>
801b374: b170 cbz r0, 801b394 <_vfiprintf_r+0x5c>
801b376: 6e6b ldr r3, [r5, #100] @ 0x64
801b378: 07dc lsls r4, r3, #31
801b37a: d504 bpl.n 801b386 <_vfiprintf_r+0x4e>
801b37c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
801b380: b01c add sp, #112 @ 0x70
801b382: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
801b386: 89ab ldrh r3, [r5, #12]
801b388: 0598 lsls r0, r3, #22
801b38a: d4f7 bmi.n 801b37c <_vfiprintf_r+0x44>
801b38c: 6da8 ldr r0, [r5, #88] @ 0x58
801b38e: f7fd fb9f bl 8018ad0 <__retarget_lock_release_recursive>
801b392: e7f3 b.n 801b37c <_vfiprintf_r+0x44>
801b394: 2300 movs r3, #0
801b396: 9309 str r3, [sp, #36] @ 0x24
801b398: 2320 movs r3, #32
801b39a: f88d 3029 strb.w r3, [sp, #41] @ 0x29
801b39e: 9703 str r7, [sp, #12]
801b3a0: 2330 movs r3, #48 @ 0x30
801b3a2: 4f6a ldr r7, [pc, #424] @ (801b54c <_vfiprintf_r+0x214>)
801b3a4: f88d 302a strb.w r3, [sp, #42] @ 0x2a
801b3a8: f04f 0801 mov.w r8, #1
801b3ac: 4623 mov r3, r4
801b3ae: 4699 mov r9, r3
801b3b0: f813 2b01 ldrb.w r2, [r3], #1
801b3b4: b10a cbz r2, 801b3ba <_vfiprintf_r+0x82>
801b3b6: 2a25 cmp r2, #37 @ 0x25
801b3b8: d1f9 bne.n 801b3ae <_vfiprintf_r+0x76>
801b3ba: ebb9 0a04 subs.w sl, r9, r4
801b3be: d00b beq.n 801b3d8 <_vfiprintf_r+0xa0>
801b3c0: 4653 mov r3, sl
801b3c2: 4622 mov r2, r4
801b3c4: 4629 mov r1, r5
801b3c6: 4630 mov r0, r6
801b3c8: f7ff ffa3 bl 801b312 <__sfputs_r>
801b3cc: 3001 adds r0, #1
801b3ce: f000 80a4 beq.w 801b51a <_vfiprintf_r+0x1e2>
801b3d2: 9a09 ldr r2, [sp, #36] @ 0x24
801b3d4: 4452 add r2, sl
801b3d6: 9209 str r2, [sp, #36] @ 0x24
801b3d8: f899 3000 ldrb.w r3, [r9]
801b3dc: 2b00 cmp r3, #0
801b3de: f000 809c beq.w 801b51a <_vfiprintf_r+0x1e2>
801b3e2: 2300 movs r3, #0
801b3e4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
801b3e8: e9cd 2305 strd r2, r3, [sp, #20]
801b3ec: f109 0901 add.w r9, r9, #1
801b3f0: 9304 str r3, [sp, #16]
801b3f2: 9307 str r3, [sp, #28]
801b3f4: f88d 3053 strb.w r3, [sp, #83] @ 0x53
801b3f8: 931a str r3, [sp, #104] @ 0x68
801b3fa: 464c mov r4, r9
801b3fc: 4853 ldr r0, [pc, #332] @ (801b54c <_vfiprintf_r+0x214>)
801b3fe: f814 1b01 ldrb.w r1, [r4], #1
801b402: 2205 movs r2, #5
801b404: f7e4 febc bl 8000180 <memchr>
801b408: 9b04 ldr r3, [sp, #16]
801b40a: b9d0 cbnz r0, 801b442 <_vfiprintf_r+0x10a>
801b40c: 06d9 lsls r1, r3, #27
801b40e: bf44 itt mi
801b410: 2220 movmi r2, #32
801b412: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53
801b416: 071a lsls r2, r3, #28
801b418: bf44 itt mi
801b41a: 222b movmi r2, #43 @ 0x2b
801b41c: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53
801b420: f899 2000 ldrb.w r2, [r9]
801b424: 2a2a cmp r2, #42 @ 0x2a
801b426: d013 beq.n 801b450 <_vfiprintf_r+0x118>
801b428: 9a07 ldr r2, [sp, #28]
801b42a: 464c mov r4, r9
801b42c: 2000 movs r0, #0
801b42e: f04f 0c0a mov.w ip, #10
801b432: 4621 mov r1, r4
801b434: f811 3b01 ldrb.w r3, [r1], #1
801b438: 3b30 subs r3, #48 @ 0x30
801b43a: 2b09 cmp r3, #9
801b43c: d949 bls.n 801b4d2 <_vfiprintf_r+0x19a>
801b43e: b968 cbnz r0, 801b45c <_vfiprintf_r+0x124>
801b440: e013 b.n 801b46a <_vfiprintf_r+0x132>
801b442: 1bc0 subs r0, r0, r7
801b444: fa08 f000 lsl.w r0, r8, r0
801b448: 4318 orrs r0, r3
801b44a: 9004 str r0, [sp, #16]
801b44c: 46a1 mov r9, r4
801b44e: e7d4 b.n 801b3fa <_vfiprintf_r+0xc2>
801b450: 9a03 ldr r2, [sp, #12]
801b452: 1d11 adds r1, r2, #4
801b454: 6812 ldr r2, [r2, #0]
801b456: 9103 str r1, [sp, #12]
801b458: 2a00 cmp r2, #0
801b45a: db01 blt.n 801b460 <_vfiprintf_r+0x128>
801b45c: 9207 str r2, [sp, #28]
801b45e: e004 b.n 801b46a <_vfiprintf_r+0x132>
801b460: 4252 negs r2, r2
801b462: f043 0302 orr.w r3, r3, #2
801b466: 9207 str r2, [sp, #28]
801b468: 9304 str r3, [sp, #16]
801b46a: 7823 ldrb r3, [r4, #0]
801b46c: 2b2e cmp r3, #46 @ 0x2e
801b46e: d10a bne.n 801b486 <_vfiprintf_r+0x14e>
801b470: 7863 ldrb r3, [r4, #1]
801b472: 2b2a cmp r3, #42 @ 0x2a
801b474: d132 bne.n 801b4dc <_vfiprintf_r+0x1a4>
801b476: 9b03 ldr r3, [sp, #12]
801b478: 1d1a adds r2, r3, #4
801b47a: 681b ldr r3, [r3, #0]
801b47c: 9203 str r2, [sp, #12]
801b47e: ea43 73e3 orr.w r3, r3, r3, asr #31
801b482: 3402 adds r4, #2
801b484: 9305 str r3, [sp, #20]
801b486: f8df 90d4 ldr.w r9, [pc, #212] @ 801b55c <_vfiprintf_r+0x224>
801b48a: 7821 ldrb r1, [r4, #0]
801b48c: 2203 movs r2, #3
801b48e: 4648 mov r0, r9
801b490: f7e4 fe76 bl 8000180 <memchr>
801b494: b138 cbz r0, 801b4a6 <_vfiprintf_r+0x16e>
801b496: 9b04 ldr r3, [sp, #16]
801b498: eba0 0009 sub.w r0, r0, r9
801b49c: 2240 movs r2, #64 @ 0x40
801b49e: 4082 lsls r2, r0
801b4a0: 4313 orrs r3, r2
801b4a2: 3401 adds r4, #1
801b4a4: 9304 str r3, [sp, #16]
801b4a6: f814 1b01 ldrb.w r1, [r4], #1
801b4aa: 4829 ldr r0, [pc, #164] @ (801b550 <_vfiprintf_r+0x218>)
801b4ac: f88d 1028 strb.w r1, [sp, #40] @ 0x28
801b4b0: 2206 movs r2, #6
801b4b2: f7e4 fe65 bl 8000180 <memchr>
801b4b6: 2800 cmp r0, #0
801b4b8: d03e beq.n 801b538 <_vfiprintf_r+0x200>
801b4ba: 4826 ldr r0, [pc, #152] @ (801b554 <_vfiprintf_r+0x21c>)
801b4bc: bb18 cbnz r0, 801b506 <_vfiprintf_r+0x1ce>
801b4be: 9b03 ldr r3, [sp, #12]
801b4c0: 3307 adds r3, #7
801b4c2: f023 0307 bic.w r3, r3, #7
801b4c6: 3308 adds r3, #8
801b4c8: 9303 str r3, [sp, #12]
801b4ca: 9b09 ldr r3, [sp, #36] @ 0x24
801b4cc: 4403 add r3, r0
801b4ce: 9309 str r3, [sp, #36] @ 0x24
801b4d0: e76c b.n 801b3ac <_vfiprintf_r+0x74>
801b4d2: fb0c 3202 mla r2, ip, r2, r3
801b4d6: 460c mov r4, r1
801b4d8: 2001 movs r0, #1
801b4da: e7aa b.n 801b432 <_vfiprintf_r+0xfa>
801b4dc: 2300 movs r3, #0
801b4de: 3401 adds r4, #1
801b4e0: 9305 str r3, [sp, #20]
801b4e2: 4619 mov r1, r3
801b4e4: f04f 0c0a mov.w ip, #10
801b4e8: 4620 mov r0, r4
801b4ea: f810 2b01 ldrb.w r2, [r0], #1
801b4ee: 3a30 subs r2, #48 @ 0x30
801b4f0: 2a09 cmp r2, #9
801b4f2: d903 bls.n 801b4fc <_vfiprintf_r+0x1c4>
801b4f4: 2b00 cmp r3, #0
801b4f6: d0c6 beq.n 801b486 <_vfiprintf_r+0x14e>
801b4f8: 9105 str r1, [sp, #20]
801b4fa: e7c4 b.n 801b486 <_vfiprintf_r+0x14e>
801b4fc: fb0c 2101 mla r1, ip, r1, r2
801b500: 4604 mov r4, r0
801b502: 2301 movs r3, #1
801b504: e7f0 b.n 801b4e8 <_vfiprintf_r+0x1b0>
801b506: ab03 add r3, sp, #12
801b508: 9300 str r3, [sp, #0]
801b50a: 462a mov r2, r5
801b50c: 4b12 ldr r3, [pc, #72] @ (801b558 <_vfiprintf_r+0x220>)
801b50e: a904 add r1, sp, #16
801b510: 4630 mov r0, r6
801b512: f7fc fa6b bl 80179ec <_printf_float>
801b516: 1c43 adds r3, r0, #1
801b518: d1d7 bne.n 801b4ca <_vfiprintf_r+0x192>
801b51a: 6e6b ldr r3, [r5, #100] @ 0x64
801b51c: 07d9 lsls r1, r3, #31
801b51e: d405 bmi.n 801b52c <_vfiprintf_r+0x1f4>
801b520: 89ab ldrh r3, [r5, #12]
801b522: 059a lsls r2, r3, #22
801b524: d402 bmi.n 801b52c <_vfiprintf_r+0x1f4>
801b526: 6da8 ldr r0, [r5, #88] @ 0x58
801b528: f7fd fad2 bl 8018ad0 <__retarget_lock_release_recursive>
801b52c: 89ab ldrh r3, [r5, #12]
801b52e: 065b lsls r3, r3, #25
801b530: f53f af24 bmi.w 801b37c <_vfiprintf_r+0x44>
801b534: 9809 ldr r0, [sp, #36] @ 0x24
801b536: e723 b.n 801b380 <_vfiprintf_r+0x48>
801b538: ab03 add r3, sp, #12
801b53a: 9300 str r3, [sp, #0]
801b53c: 462a mov r2, r5
801b53e: 4b06 ldr r3, [pc, #24] @ (801b558 <_vfiprintf_r+0x220>)
801b540: a904 add r1, sp, #16
801b542: 4630 mov r0, r6
801b544: f7fc fce8 bl 8017f18 <_printf_i>
801b548: e7e5 b.n 801b516 <_vfiprintf_r+0x1de>
801b54a: bf00 nop
801b54c: 0801c8dd .word 0x0801c8dd
801b550: 0801c8e7 .word 0x0801c8e7
801b554: 080179ed .word 0x080179ed
801b558: 0801b313 .word 0x0801b313
801b55c: 0801c8e3 .word 0x0801c8e3
0801b560 <__sflush_r>:
801b560: f9b1 200c ldrsh.w r2, [r1, #12]
801b564: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801b568: 0716 lsls r6, r2, #28
801b56a: 4605 mov r5, r0
801b56c: 460c mov r4, r1
801b56e: d451 bmi.n 801b614 <__sflush_r+0xb4>
801b570: 684b ldr r3, [r1, #4]
801b572: 2b00 cmp r3, #0
801b574: dc02 bgt.n 801b57c <__sflush_r+0x1c>
801b576: 6c0b ldr r3, [r1, #64] @ 0x40
801b578: 2b00 cmp r3, #0
801b57a: dd49 ble.n 801b610 <__sflush_r+0xb0>
801b57c: 6ae6 ldr r6, [r4, #44] @ 0x2c
801b57e: 2e00 cmp r6, #0
801b580: d046 beq.n 801b610 <__sflush_r+0xb0>
801b582: 2300 movs r3, #0
801b584: f412 5280 ands.w r2, r2, #4096 @ 0x1000
801b588: 682f ldr r7, [r5, #0]
801b58a: 602b str r3, [r5, #0]
801b58c: d031 beq.n 801b5f2 <__sflush_r+0x92>
801b58e: 6d62 ldr r2, [r4, #84] @ 0x54
801b590: 89a3 ldrh r3, [r4, #12]
801b592: 0759 lsls r1, r3, #29
801b594: d505 bpl.n 801b5a2 <__sflush_r+0x42>
801b596: 6863 ldr r3, [r4, #4]
801b598: 1ad2 subs r2, r2, r3
801b59a: 6b63 ldr r3, [r4, #52] @ 0x34
801b59c: b10b cbz r3, 801b5a2 <__sflush_r+0x42>
801b59e: 6c23 ldr r3, [r4, #64] @ 0x40
801b5a0: 1ad2 subs r2, r2, r3
801b5a2: 2300 movs r3, #0
801b5a4: 6ae6 ldr r6, [r4, #44] @ 0x2c
801b5a6: 6a21 ldr r1, [r4, #32]
801b5a8: 4628 mov r0, r5
801b5aa: 47b0 blx r6
801b5ac: 1c42 adds r2, r0, #1
801b5ae: f9b4 300c ldrsh.w r3, [r4, #12]
801b5b2: d106 bne.n 801b5c2 <__sflush_r+0x62>
801b5b4: 6829 ldr r1, [r5, #0]
801b5b6: 291d cmp r1, #29
801b5b8: d846 bhi.n 801b648 <__sflush_r+0xe8>
801b5ba: 4a29 ldr r2, [pc, #164] @ (801b660 <__sflush_r+0x100>)
801b5bc: 40ca lsrs r2, r1
801b5be: 07d6 lsls r6, r2, #31
801b5c0: d542 bpl.n 801b648 <__sflush_r+0xe8>
801b5c2: 2200 movs r2, #0
801b5c4: 6062 str r2, [r4, #4]
801b5c6: 04d9 lsls r1, r3, #19
801b5c8: 6922 ldr r2, [r4, #16]
801b5ca: 6022 str r2, [r4, #0]
801b5cc: d504 bpl.n 801b5d8 <__sflush_r+0x78>
801b5ce: 1c42 adds r2, r0, #1
801b5d0: d101 bne.n 801b5d6 <__sflush_r+0x76>
801b5d2: 682b ldr r3, [r5, #0]
801b5d4: b903 cbnz r3, 801b5d8 <__sflush_r+0x78>
801b5d6: 6560 str r0, [r4, #84] @ 0x54
801b5d8: 6b61 ldr r1, [r4, #52] @ 0x34
801b5da: 602f str r7, [r5, #0]
801b5dc: b1c1 cbz r1, 801b610 <__sflush_r+0xb0>
801b5de: f104 0344 add.w r3, r4, #68 @ 0x44
801b5e2: 4299 cmp r1, r3
801b5e4: d002 beq.n 801b5ec <__sflush_r+0x8c>
801b5e6: 4628 mov r0, r5
801b5e8: f7fe f8ee bl 80197c8 <_free_r>
801b5ec: 2300 movs r3, #0
801b5ee: 6363 str r3, [r4, #52] @ 0x34
801b5f0: e00e b.n 801b610 <__sflush_r+0xb0>
801b5f2: 6a21 ldr r1, [r4, #32]
801b5f4: 2301 movs r3, #1
801b5f6: 4628 mov r0, r5
801b5f8: 47b0 blx r6
801b5fa: 4602 mov r2, r0
801b5fc: 1c50 adds r0, r2, #1
801b5fe: d1c7 bne.n 801b590 <__sflush_r+0x30>
801b600: 682b ldr r3, [r5, #0]
801b602: 2b00 cmp r3, #0
801b604: d0c4 beq.n 801b590 <__sflush_r+0x30>
801b606: 2b1d cmp r3, #29
801b608: d001 beq.n 801b60e <__sflush_r+0xae>
801b60a: 2b16 cmp r3, #22
801b60c: d11a bne.n 801b644 <__sflush_r+0xe4>
801b60e: 602f str r7, [r5, #0]
801b610: 2000 movs r0, #0
801b612: e01e b.n 801b652 <__sflush_r+0xf2>
801b614: 690f ldr r7, [r1, #16]
801b616: 2f00 cmp r7, #0
801b618: d0fa beq.n 801b610 <__sflush_r+0xb0>
801b61a: 0793 lsls r3, r2, #30
801b61c: 680e ldr r6, [r1, #0]
801b61e: bf08 it eq
801b620: 694b ldreq r3, [r1, #20]
801b622: 600f str r7, [r1, #0]
801b624: bf18 it ne
801b626: 2300 movne r3, #0
801b628: eba6 0807 sub.w r8, r6, r7
801b62c: 608b str r3, [r1, #8]
801b62e: f1b8 0f00 cmp.w r8, #0
801b632: dded ble.n 801b610 <__sflush_r+0xb0>
801b634: 6a21 ldr r1, [r4, #32]
801b636: 6aa6 ldr r6, [r4, #40] @ 0x28
801b638: 4643 mov r3, r8
801b63a: 463a mov r2, r7
801b63c: 4628 mov r0, r5
801b63e: 47b0 blx r6
801b640: 2800 cmp r0, #0
801b642: dc08 bgt.n 801b656 <__sflush_r+0xf6>
801b644: f9b4 300c ldrsh.w r3, [r4, #12]
801b648: f043 0340 orr.w r3, r3, #64 @ 0x40
801b64c: 81a3 strh r3, [r4, #12]
801b64e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
801b652: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
801b656: 4407 add r7, r0
801b658: eba8 0800 sub.w r8, r8, r0
801b65c: e7e7 b.n 801b62e <__sflush_r+0xce>
801b65e: bf00 nop
801b660: 20400001 .word 0x20400001
0801b664 <_fflush_r>:
801b664: b538 push {r3, r4, r5, lr}
801b666: 690b ldr r3, [r1, #16]
801b668: 4605 mov r5, r0
801b66a: 460c mov r4, r1
801b66c: b913 cbnz r3, 801b674 <_fflush_r+0x10>
801b66e: 2500 movs r5, #0
801b670: 4628 mov r0, r5
801b672: bd38 pop {r3, r4, r5, pc}
801b674: b118 cbz r0, 801b67e <_fflush_r+0x1a>
801b676: 6a03 ldr r3, [r0, #32]
801b678: b90b cbnz r3, 801b67e <_fflush_r+0x1a>
801b67a: f7fd f80d bl 8018698 <__sinit>
801b67e: f9b4 300c ldrsh.w r3, [r4, #12]
801b682: 2b00 cmp r3, #0
801b684: d0f3 beq.n 801b66e <_fflush_r+0xa>
801b686: 6e62 ldr r2, [r4, #100] @ 0x64
801b688: 07d0 lsls r0, r2, #31
801b68a: d404 bmi.n 801b696 <_fflush_r+0x32>
801b68c: 0599 lsls r1, r3, #22
801b68e: d402 bmi.n 801b696 <_fflush_r+0x32>
801b690: 6da0 ldr r0, [r4, #88] @ 0x58
801b692: f7fd fa1c bl 8018ace <__retarget_lock_acquire_recursive>
801b696: 4628 mov r0, r5
801b698: 4621 mov r1, r4
801b69a: f7ff ff61 bl 801b560 <__sflush_r>
801b69e: 6e63 ldr r3, [r4, #100] @ 0x64
801b6a0: 07da lsls r2, r3, #31
801b6a2: 4605 mov r5, r0
801b6a4: d4e4 bmi.n 801b670 <_fflush_r+0xc>
801b6a6: 89a3 ldrh r3, [r4, #12]
801b6a8: 059b lsls r3, r3, #22
801b6aa: d4e1 bmi.n 801b670 <_fflush_r+0xc>
801b6ac: 6da0 ldr r0, [r4, #88] @ 0x58
801b6ae: f7fd fa0f bl 8018ad0 <__retarget_lock_release_recursive>
801b6b2: e7dd b.n 801b670 <_fflush_r+0xc>
0801b6b4 <__swhatbuf_r>:
801b6b4: b570 push {r4, r5, r6, lr}
801b6b6: 460c mov r4, r1
801b6b8: f9b1 100e ldrsh.w r1, [r1, #14]
801b6bc: 2900 cmp r1, #0
801b6be: b096 sub sp, #88 @ 0x58
801b6c0: 4615 mov r5, r2
801b6c2: 461e mov r6, r3
801b6c4: da0a bge.n 801b6dc <__swhatbuf_r+0x28>
801b6c6: 89a1 ldrh r1, [r4, #12]
801b6c8: f011 0180 ands.w r1, r1, #128 @ 0x80
801b6cc: d113 bne.n 801b6f6 <__swhatbuf_r+0x42>
801b6ce: f44f 6280 mov.w r2, #1024 @ 0x400
801b6d2: 2000 movs r0, #0
801b6d4: 6031 str r1, [r6, #0]
801b6d6: 602a str r2, [r5, #0]
801b6d8: b016 add sp, #88 @ 0x58
801b6da: bd70 pop {r4, r5, r6, pc}
801b6dc: 466a mov r2, sp
801b6de: f000 f871 bl 801b7c4 <_fstat_r>
801b6e2: 2800 cmp r0, #0
801b6e4: dbef blt.n 801b6c6 <__swhatbuf_r+0x12>
801b6e6: 9901 ldr r1, [sp, #4]
801b6e8: f401 4170 and.w r1, r1, #61440 @ 0xf000
801b6ec: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
801b6f0: 4259 negs r1, r3
801b6f2: 4159 adcs r1, r3
801b6f4: e7eb b.n 801b6ce <__swhatbuf_r+0x1a>
801b6f6: 2100 movs r1, #0
801b6f8: 2240 movs r2, #64 @ 0x40
801b6fa: e7ea b.n 801b6d2 <__swhatbuf_r+0x1e>
0801b6fc <__smakebuf_r>:
801b6fc: 898b ldrh r3, [r1, #12]
801b6fe: b573 push {r0, r1, r4, r5, r6, lr}
801b700: 079e lsls r6, r3, #30
801b702: 4605 mov r5, r0
801b704: 460c mov r4, r1
801b706: d507 bpl.n 801b718 <__smakebuf_r+0x1c>
801b708: f104 0347 add.w r3, r4, #71 @ 0x47
801b70c: 6023 str r3, [r4, #0]
801b70e: 6123 str r3, [r4, #16]
801b710: 2301 movs r3, #1
801b712: 6163 str r3, [r4, #20]
801b714: b002 add sp, #8
801b716: bd70 pop {r4, r5, r6, pc}
801b718: ab01 add r3, sp, #4
801b71a: 466a mov r2, sp
801b71c: f7ff ffca bl 801b6b4 <__swhatbuf_r>
801b720: 9e00 ldr r6, [sp, #0]
801b722: 4628 mov r0, r5
801b724: 4631 mov r1, r6
801b726: f7fe f8c3 bl 80198b0 <_malloc_r>
801b72a: f9b4 300c ldrsh.w r3, [r4, #12]
801b72e: b938 cbnz r0, 801b740 <__smakebuf_r+0x44>
801b730: 059a lsls r2, r3, #22
801b732: d4ef bmi.n 801b714 <__smakebuf_r+0x18>
801b734: f023 0303 bic.w r3, r3, #3
801b738: f043 0302 orr.w r3, r3, #2
801b73c: 81a3 strh r3, [r4, #12]
801b73e: e7e3 b.n 801b708 <__smakebuf_r+0xc>
801b740: f043 0380 orr.w r3, r3, #128 @ 0x80
801b744: 81a3 strh r3, [r4, #12]
801b746: 9b01 ldr r3, [sp, #4]
801b748: 6020 str r0, [r4, #0]
801b74a: e9c4 0604 strd r0, r6, [r4, #16]
801b74e: 2b00 cmp r3, #0
801b750: d0e0 beq.n 801b714 <__smakebuf_r+0x18>
801b752: f9b4 100e ldrsh.w r1, [r4, #14]
801b756: 4628 mov r0, r5
801b758: f000 f846 bl 801b7e8 <_isatty_r>
801b75c: 2800 cmp r0, #0
801b75e: d0d9 beq.n 801b714 <__smakebuf_r+0x18>
801b760: 89a3 ldrh r3, [r4, #12]
801b762: f023 0303 bic.w r3, r3, #3
801b766: f043 0301 orr.w r3, r3, #1
801b76a: 81a3 strh r3, [r4, #12]
801b76c: e7d2 b.n 801b714 <__smakebuf_r+0x18>
0801b76e <memmove>:
801b76e: 4288 cmp r0, r1
801b770: b510 push {r4, lr}
801b772: eb01 0402 add.w r4, r1, r2
801b776: d902 bls.n 801b77e <memmove+0x10>
801b778: 4284 cmp r4, r0
801b77a: 4623 mov r3, r4
801b77c: d807 bhi.n 801b78e <memmove+0x20>
801b77e: 1e43 subs r3, r0, #1
801b780: 42a1 cmp r1, r4
801b782: d007 beq.n 801b794 <memmove+0x26>
801b784: f811 2b01 ldrb.w r2, [r1], #1
801b788: f803 2f01 strb.w r2, [r3, #1]!
801b78c: e7f8 b.n 801b780 <memmove+0x12>
801b78e: 4402 add r2, r0
801b790: 4282 cmp r2, r0
801b792: d100 bne.n 801b796 <memmove+0x28>
801b794: bd10 pop {r4, pc}
801b796: f813 1d01 ldrb.w r1, [r3, #-1]!
801b79a: f802 1d01 strb.w r1, [r2, #-1]!
801b79e: e7f7 b.n 801b790 <memmove+0x22>
0801b7a0 <strncmp>:
801b7a0: b510 push {r4, lr}
801b7a2: b16a cbz r2, 801b7c0 <strncmp+0x20>
801b7a4: 3901 subs r1, #1
801b7a6: 1884 adds r4, r0, r2
801b7a8: f810 2b01 ldrb.w r2, [r0], #1
801b7ac: f811 3f01 ldrb.w r3, [r1, #1]!
801b7b0: 429a cmp r2, r3
801b7b2: d103 bne.n 801b7bc <strncmp+0x1c>
801b7b4: 42a0 cmp r0, r4
801b7b6: d001 beq.n 801b7bc <strncmp+0x1c>
801b7b8: 2a00 cmp r2, #0
801b7ba: d1f5 bne.n 801b7a8 <strncmp+0x8>
801b7bc: 1ad0 subs r0, r2, r3
801b7be: bd10 pop {r4, pc}
801b7c0: 4610 mov r0, r2
801b7c2: e7fc b.n 801b7be <strncmp+0x1e>
0801b7c4 <_fstat_r>:
801b7c4: b538 push {r3, r4, r5, lr}
801b7c6: 4d07 ldr r5, [pc, #28] @ (801b7e4 <_fstat_r+0x20>)
801b7c8: 2300 movs r3, #0
801b7ca: 4604 mov r4, r0
801b7cc: 4608 mov r0, r1
801b7ce: 4611 mov r1, r2
801b7d0: 602b str r3, [r5, #0]
801b7d2: f7e9 fca9 bl 8005128 <_fstat>
801b7d6: 1c43 adds r3, r0, #1
801b7d8: d102 bne.n 801b7e0 <_fstat_r+0x1c>
801b7da: 682b ldr r3, [r5, #0]
801b7dc: b103 cbz r3, 801b7e0 <_fstat_r+0x1c>
801b7de: 6023 str r3, [r4, #0]
801b7e0: bd38 pop {r3, r4, r5, pc}
801b7e2: bf00 nop
801b7e4: 20013c38 .word 0x20013c38
0801b7e8 <_isatty_r>:
801b7e8: b538 push {r3, r4, r5, lr}
801b7ea: 4d06 ldr r5, [pc, #24] @ (801b804 <_isatty_r+0x1c>)
801b7ec: 2300 movs r3, #0
801b7ee: 4604 mov r4, r0
801b7f0: 4608 mov r0, r1
801b7f2: 602b str r3, [r5, #0]
801b7f4: f7e9 fca8 bl 8005148 <_isatty>
801b7f8: 1c43 adds r3, r0, #1
801b7fa: d102 bne.n 801b802 <_isatty_r+0x1a>
801b7fc: 682b ldr r3, [r5, #0]
801b7fe: b103 cbz r3, 801b802 <_isatty_r+0x1a>
801b800: 6023 str r3, [r4, #0]
801b802: bd38 pop {r3, r4, r5, pc}
801b804: 20013c38 .word 0x20013c38
0801b808 <_sbrk_r>:
801b808: b538 push {r3, r4, r5, lr}
801b80a: 4d06 ldr r5, [pc, #24] @ (801b824 <_sbrk_r+0x1c>)
801b80c: 2300 movs r3, #0
801b80e: 4604 mov r4, r0
801b810: 4608 mov r0, r1
801b812: 602b str r3, [r5, #0]
801b814: f7e9 fcb0 bl 8005178 <_sbrk>
801b818: 1c43 adds r3, r0, #1
801b81a: d102 bne.n 801b822 <_sbrk_r+0x1a>
801b81c: 682b ldr r3, [r5, #0]
801b81e: b103 cbz r3, 801b822 <_sbrk_r+0x1a>
801b820: 6023 str r3, [r4, #0]
801b822: bd38 pop {r3, r4, r5, pc}
801b824: 20013c38 .word 0x20013c38
0801b828 <nan>:
801b828: ed9f 0b01 vldr d0, [pc, #4] @ 801b830 <nan+0x8>
801b82c: 4770 bx lr
801b82e: bf00 nop
801b830: 00000000 .word 0x00000000
801b834: 7ff80000 .word 0x7ff80000
0801b838 <__assert_func>:
801b838: b51f push {r0, r1, r2, r3, r4, lr}
801b83a: 4614 mov r4, r2
801b83c: 461a mov r2, r3
801b83e: 4b09 ldr r3, [pc, #36] @ (801b864 <__assert_func+0x2c>)
801b840: 681b ldr r3, [r3, #0]
801b842: 4605 mov r5, r0
801b844: 68d8 ldr r0, [r3, #12]
801b846: b14c cbz r4, 801b85c <__assert_func+0x24>
801b848: 4b07 ldr r3, [pc, #28] @ (801b868 <__assert_func+0x30>)
801b84a: 9100 str r1, [sp, #0]
801b84c: e9cd 3401 strd r3, r4, [sp, #4]
801b850: 4906 ldr r1, [pc, #24] @ (801b86c <__assert_func+0x34>)
801b852: 462b mov r3, r5
801b854: f000 fbaa bl 801bfac <fiprintf>
801b858: f000 fbba bl 801bfd0 <abort>
801b85c: 4b04 ldr r3, [pc, #16] @ (801b870 <__assert_func+0x38>)
801b85e: 461c mov r4, r3
801b860: e7f3 b.n 801b84a <__assert_func+0x12>
801b862: bf00 nop
801b864: 2000011c .word 0x2000011c
801b868: 0801c8f6 .word 0x0801c8f6
801b86c: 0801c903 .word 0x0801c903
801b870: 0801c931 .word 0x0801c931
0801b874 <_calloc_r>:
801b874: b570 push {r4, r5, r6, lr}
801b876: fba1 5402 umull r5, r4, r1, r2
801b87a: b934 cbnz r4, 801b88a <_calloc_r+0x16>
801b87c: 4629 mov r1, r5
801b87e: f7fe f817 bl 80198b0 <_malloc_r>
801b882: 4606 mov r6, r0
801b884: b928 cbnz r0, 801b892 <_calloc_r+0x1e>
801b886: 4630 mov r0, r6
801b888: bd70 pop {r4, r5, r6, pc}
801b88a: 220c movs r2, #12
801b88c: 6002 str r2, [r0, #0]
801b88e: 2600 movs r6, #0
801b890: e7f9 b.n 801b886 <_calloc_r+0x12>
801b892: 462a mov r2, r5
801b894: 4621 mov r1, r4
801b896: f7fd f89d bl 80189d4 <memset>
801b89a: e7f4 b.n 801b886 <_calloc_r+0x12>
0801b89c <rshift>:
801b89c: 6903 ldr r3, [r0, #16]
801b89e: ebb3 1f61 cmp.w r3, r1, asr #5
801b8a2: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
801b8a6: ea4f 1261 mov.w r2, r1, asr #5
801b8aa: f100 0414 add.w r4, r0, #20
801b8ae: dd45 ble.n 801b93c <rshift+0xa0>
801b8b0: f011 011f ands.w r1, r1, #31
801b8b4: eb04 0683 add.w r6, r4, r3, lsl #2
801b8b8: eb04 0582 add.w r5, r4, r2, lsl #2
801b8bc: d10c bne.n 801b8d8 <rshift+0x3c>
801b8be: f100 0710 add.w r7, r0, #16
801b8c2: 4629 mov r1, r5
801b8c4: 42b1 cmp r1, r6
801b8c6: d334 bcc.n 801b932 <rshift+0x96>
801b8c8: 1a9b subs r3, r3, r2
801b8ca: 009b lsls r3, r3, #2
801b8cc: 1eea subs r2, r5, #3
801b8ce: 4296 cmp r6, r2
801b8d0: bf38 it cc
801b8d2: 2300 movcc r3, #0
801b8d4: 4423 add r3, r4
801b8d6: e015 b.n 801b904 <rshift+0x68>
801b8d8: f854 7022 ldr.w r7, [r4, r2, lsl #2]
801b8dc: f1c1 0820 rsb r8, r1, #32
801b8e0: 40cf lsrs r7, r1
801b8e2: f105 0e04 add.w lr, r5, #4
801b8e6: 46a1 mov r9, r4
801b8e8: 4576 cmp r6, lr
801b8ea: 46f4 mov ip, lr
801b8ec: d815 bhi.n 801b91a <rshift+0x7e>
801b8ee: 1a9a subs r2, r3, r2
801b8f0: 0092 lsls r2, r2, #2
801b8f2: 3a04 subs r2, #4
801b8f4: 3501 adds r5, #1
801b8f6: 42ae cmp r6, r5
801b8f8: bf38 it cc
801b8fa: 2200 movcc r2, #0
801b8fc: 18a3 adds r3, r4, r2
801b8fe: 50a7 str r7, [r4, r2]
801b900: b107 cbz r7, 801b904 <rshift+0x68>
801b902: 3304 adds r3, #4
801b904: 1b1a subs r2, r3, r4
801b906: 42a3 cmp r3, r4
801b908: ea4f 02a2 mov.w r2, r2, asr #2
801b90c: bf08 it eq
801b90e: 2300 moveq r3, #0
801b910: 6102 str r2, [r0, #16]
801b912: bf08 it eq
801b914: 6143 streq r3, [r0, #20]
801b916: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
801b91a: f8dc c000 ldr.w ip, [ip]
801b91e: fa0c fc08 lsl.w ip, ip, r8
801b922: ea4c 0707 orr.w r7, ip, r7
801b926: f849 7b04 str.w r7, [r9], #4
801b92a: f85e 7b04 ldr.w r7, [lr], #4
801b92e: 40cf lsrs r7, r1
801b930: e7da b.n 801b8e8 <rshift+0x4c>
801b932: f851 cb04 ldr.w ip, [r1], #4
801b936: f847 cf04 str.w ip, [r7, #4]!
801b93a: e7c3 b.n 801b8c4 <rshift+0x28>
801b93c: 4623 mov r3, r4
801b93e: e7e1 b.n 801b904 <rshift+0x68>
0801b940 <__hexdig_fun>:
801b940: f1a0 0330 sub.w r3, r0, #48 @ 0x30
801b944: 2b09 cmp r3, #9
801b946: d802 bhi.n 801b94e <__hexdig_fun+0xe>
801b948: 3820 subs r0, #32
801b94a: b2c0 uxtb r0, r0
801b94c: 4770 bx lr
801b94e: f1a0 0361 sub.w r3, r0, #97 @ 0x61
801b952: 2b05 cmp r3, #5
801b954: d801 bhi.n 801b95a <__hexdig_fun+0x1a>
801b956: 3847 subs r0, #71 @ 0x47
801b958: e7f7 b.n 801b94a <__hexdig_fun+0xa>
801b95a: f1a0 0341 sub.w r3, r0, #65 @ 0x41
801b95e: 2b05 cmp r3, #5
801b960: d801 bhi.n 801b966 <__hexdig_fun+0x26>
801b962: 3827 subs r0, #39 @ 0x27
801b964: e7f1 b.n 801b94a <__hexdig_fun+0xa>
801b966: 2000 movs r0, #0
801b968: 4770 bx lr
...
0801b96c <__gethex>:
801b96c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
801b970: b085 sub sp, #20
801b972: 468a mov sl, r1
801b974: 9302 str r3, [sp, #8]
801b976: 680b ldr r3, [r1, #0]
801b978: 9001 str r0, [sp, #4]
801b97a: 4690 mov r8, r2
801b97c: 1c9c adds r4, r3, #2
801b97e: 46a1 mov r9, r4
801b980: f814 0b01 ldrb.w r0, [r4], #1
801b984: 2830 cmp r0, #48 @ 0x30
801b986: d0fa beq.n 801b97e <__gethex+0x12>
801b988: eba9 0303 sub.w r3, r9, r3
801b98c: f1a3 0b02 sub.w fp, r3, #2
801b990: f7ff ffd6 bl 801b940 <__hexdig_fun>
801b994: 4605 mov r5, r0
801b996: 2800 cmp r0, #0
801b998: d168 bne.n 801ba6c <__gethex+0x100>
801b99a: 49a0 ldr r1, [pc, #640] @ (801bc1c <__gethex+0x2b0>)
801b99c: 2201 movs r2, #1
801b99e: 4648 mov r0, r9
801b9a0: f7ff fefe bl 801b7a0 <strncmp>
801b9a4: 4607 mov r7, r0
801b9a6: 2800 cmp r0, #0
801b9a8: d167 bne.n 801ba7a <__gethex+0x10e>
801b9aa: f899 0001 ldrb.w r0, [r9, #1]
801b9ae: 4626 mov r6, r4
801b9b0: f7ff ffc6 bl 801b940 <__hexdig_fun>
801b9b4: 2800 cmp r0, #0
801b9b6: d062 beq.n 801ba7e <__gethex+0x112>
801b9b8: 4623 mov r3, r4
801b9ba: 7818 ldrb r0, [r3, #0]
801b9bc: 2830 cmp r0, #48 @ 0x30
801b9be: 4699 mov r9, r3
801b9c0: f103 0301 add.w r3, r3, #1
801b9c4: d0f9 beq.n 801b9ba <__gethex+0x4e>
801b9c6: f7ff ffbb bl 801b940 <__hexdig_fun>
801b9ca: fab0 f580 clz r5, r0
801b9ce: 096d lsrs r5, r5, #5
801b9d0: f04f 0b01 mov.w fp, #1
801b9d4: 464a mov r2, r9
801b9d6: 4616 mov r6, r2
801b9d8: 3201 adds r2, #1
801b9da: 7830 ldrb r0, [r6, #0]
801b9dc: f7ff ffb0 bl 801b940 <__hexdig_fun>
801b9e0: 2800 cmp r0, #0
801b9e2: d1f8 bne.n 801b9d6 <__gethex+0x6a>
801b9e4: 498d ldr r1, [pc, #564] @ (801bc1c <__gethex+0x2b0>)
801b9e6: 2201 movs r2, #1
801b9e8: 4630 mov r0, r6
801b9ea: f7ff fed9 bl 801b7a0 <strncmp>
801b9ee: 2800 cmp r0, #0
801b9f0: d13f bne.n 801ba72 <__gethex+0x106>
801b9f2: b944 cbnz r4, 801ba06 <__gethex+0x9a>
801b9f4: 1c74 adds r4, r6, #1
801b9f6: 4622 mov r2, r4
801b9f8: 4616 mov r6, r2
801b9fa: 3201 adds r2, #1
801b9fc: 7830 ldrb r0, [r6, #0]
801b9fe: f7ff ff9f bl 801b940 <__hexdig_fun>
801ba02: 2800 cmp r0, #0
801ba04: d1f8 bne.n 801b9f8 <__gethex+0x8c>
801ba06: 1ba4 subs r4, r4, r6
801ba08: 00a7 lsls r7, r4, #2
801ba0a: 7833 ldrb r3, [r6, #0]
801ba0c: f003 03df and.w r3, r3, #223 @ 0xdf
801ba10: 2b50 cmp r3, #80 @ 0x50
801ba12: d13e bne.n 801ba92 <__gethex+0x126>
801ba14: 7873 ldrb r3, [r6, #1]
801ba16: 2b2b cmp r3, #43 @ 0x2b
801ba18: d033 beq.n 801ba82 <__gethex+0x116>
801ba1a: 2b2d cmp r3, #45 @ 0x2d
801ba1c: d034 beq.n 801ba88 <__gethex+0x11c>
801ba1e: 1c71 adds r1, r6, #1
801ba20: 2400 movs r4, #0
801ba22: 7808 ldrb r0, [r1, #0]
801ba24: f7ff ff8c bl 801b940 <__hexdig_fun>
801ba28: 1e43 subs r3, r0, #1
801ba2a: b2db uxtb r3, r3
801ba2c: 2b18 cmp r3, #24
801ba2e: d830 bhi.n 801ba92 <__gethex+0x126>
801ba30: f1a0 0210 sub.w r2, r0, #16
801ba34: f811 0f01 ldrb.w r0, [r1, #1]!
801ba38: f7ff ff82 bl 801b940 <__hexdig_fun>
801ba3c: f100 3cff add.w ip, r0, #4294967295 @ 0xffffffff
801ba40: fa5f fc8c uxtb.w ip, ip
801ba44: f1bc 0f18 cmp.w ip, #24
801ba48: f04f 030a mov.w r3, #10
801ba4c: d91e bls.n 801ba8c <__gethex+0x120>
801ba4e: b104 cbz r4, 801ba52 <__gethex+0xe6>
801ba50: 4252 negs r2, r2
801ba52: 4417 add r7, r2
801ba54: f8ca 1000 str.w r1, [sl]
801ba58: b1ed cbz r5, 801ba96 <__gethex+0x12a>
801ba5a: f1bb 0f00 cmp.w fp, #0
801ba5e: bf0c ite eq
801ba60: 2506 moveq r5, #6
801ba62: 2500 movne r5, #0
801ba64: 4628 mov r0, r5
801ba66: b005 add sp, #20
801ba68: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
801ba6c: 2500 movs r5, #0
801ba6e: 462c mov r4, r5
801ba70: e7b0 b.n 801b9d4 <__gethex+0x68>
801ba72: 2c00 cmp r4, #0
801ba74: d1c7 bne.n 801ba06 <__gethex+0x9a>
801ba76: 4627 mov r7, r4
801ba78: e7c7 b.n 801ba0a <__gethex+0x9e>
801ba7a: 464e mov r6, r9
801ba7c: 462f mov r7, r5
801ba7e: 2501 movs r5, #1
801ba80: e7c3 b.n 801ba0a <__gethex+0x9e>
801ba82: 2400 movs r4, #0
801ba84: 1cb1 adds r1, r6, #2
801ba86: e7cc b.n 801ba22 <__gethex+0xb6>
801ba88: 2401 movs r4, #1
801ba8a: e7fb b.n 801ba84 <__gethex+0x118>
801ba8c: fb03 0002 mla r0, r3, r2, r0
801ba90: e7ce b.n 801ba30 <__gethex+0xc4>
801ba92: 4631 mov r1, r6
801ba94: e7de b.n 801ba54 <__gethex+0xe8>
801ba96: eba6 0309 sub.w r3, r6, r9
801ba9a: 3b01 subs r3, #1
801ba9c: 4629 mov r1, r5
801ba9e: 2b07 cmp r3, #7
801baa0: dc0a bgt.n 801bab8 <__gethex+0x14c>
801baa2: 9801 ldr r0, [sp, #4]
801baa4: f7fd ff90 bl 80199c8 <_Balloc>
801baa8: 4604 mov r4, r0
801baaa: b940 cbnz r0, 801babe <__gethex+0x152>
801baac: 4b5c ldr r3, [pc, #368] @ (801bc20 <__gethex+0x2b4>)
801baae: 4602 mov r2, r0
801bab0: 21e4 movs r1, #228 @ 0xe4
801bab2: 485c ldr r0, [pc, #368] @ (801bc24 <__gethex+0x2b8>)
801bab4: f7ff fec0 bl 801b838 <__assert_func>
801bab8: 3101 adds r1, #1
801baba: 105b asrs r3, r3, #1
801babc: e7ef b.n 801ba9e <__gethex+0x132>
801babe: f100 0a14 add.w sl, r0, #20
801bac2: 2300 movs r3, #0
801bac4: 4655 mov r5, sl
801bac6: 469b mov fp, r3
801bac8: 45b1 cmp r9, r6
801baca: d337 bcc.n 801bb3c <__gethex+0x1d0>
801bacc: f845 bb04 str.w fp, [r5], #4
801bad0: eba5 050a sub.w r5, r5, sl
801bad4: 10ad asrs r5, r5, #2
801bad6: 6125 str r5, [r4, #16]
801bad8: 4658 mov r0, fp
801bada: f7fe f865 bl 8019ba8 <__hi0bits>
801bade: 016d lsls r5, r5, #5
801bae0: f8d8 6000 ldr.w r6, [r8]
801bae4: 1a2d subs r5, r5, r0
801bae6: 42b5 cmp r5, r6
801bae8: dd54 ble.n 801bb94 <__gethex+0x228>
801baea: 1bad subs r5, r5, r6
801baec: 4629 mov r1, r5
801baee: 4620 mov r0, r4
801baf0: f7fe fc01 bl 801a2f6 <__any_on>
801baf4: 4681 mov r9, r0
801baf6: b178 cbz r0, 801bb18 <__gethex+0x1ac>
801baf8: 1e6b subs r3, r5, #1
801bafa: 1159 asrs r1, r3, #5
801bafc: f003 021f and.w r2, r3, #31
801bb00: f85a 1021 ldr.w r1, [sl, r1, lsl #2]
801bb04: f04f 0901 mov.w r9, #1
801bb08: fa09 f202 lsl.w r2, r9, r2
801bb0c: 420a tst r2, r1
801bb0e: d003 beq.n 801bb18 <__gethex+0x1ac>
801bb10: 454b cmp r3, r9
801bb12: dc36 bgt.n 801bb82 <__gethex+0x216>
801bb14: f04f 0902 mov.w r9, #2
801bb18: 4629 mov r1, r5
801bb1a: 4620 mov r0, r4
801bb1c: f7ff febe bl 801b89c <rshift>
801bb20: 442f add r7, r5
801bb22: f8d8 3008 ldr.w r3, [r8, #8]
801bb26: 42bb cmp r3, r7
801bb28: da42 bge.n 801bbb0 <__gethex+0x244>
801bb2a: 9801 ldr r0, [sp, #4]
801bb2c: 4621 mov r1, r4
801bb2e: f7fd ff89 bl 8019a44 <_Bfree>
801bb32: 9a0e ldr r2, [sp, #56] @ 0x38
801bb34: 2300 movs r3, #0
801bb36: 6013 str r3, [r2, #0]
801bb38: 25a3 movs r5, #163 @ 0xa3
801bb3a: e793 b.n 801ba64 <__gethex+0xf8>
801bb3c: f816 2d01 ldrb.w r2, [r6, #-1]!
801bb40: 2a2e cmp r2, #46 @ 0x2e
801bb42: d012 beq.n 801bb6a <__gethex+0x1fe>
801bb44: 2b20 cmp r3, #32
801bb46: d104 bne.n 801bb52 <__gethex+0x1e6>
801bb48: f845 bb04 str.w fp, [r5], #4
801bb4c: f04f 0b00 mov.w fp, #0
801bb50: 465b mov r3, fp
801bb52: 7830 ldrb r0, [r6, #0]
801bb54: 9303 str r3, [sp, #12]
801bb56: f7ff fef3 bl 801b940 <__hexdig_fun>
801bb5a: 9b03 ldr r3, [sp, #12]
801bb5c: f000 000f and.w r0, r0, #15
801bb60: 4098 lsls r0, r3
801bb62: ea4b 0b00 orr.w fp, fp, r0
801bb66: 3304 adds r3, #4
801bb68: e7ae b.n 801bac8 <__gethex+0x15c>
801bb6a: 45b1 cmp r9, r6
801bb6c: d8ea bhi.n 801bb44 <__gethex+0x1d8>
801bb6e: 492b ldr r1, [pc, #172] @ (801bc1c <__gethex+0x2b0>)
801bb70: 9303 str r3, [sp, #12]
801bb72: 2201 movs r2, #1
801bb74: 4630 mov r0, r6
801bb76: f7ff fe13 bl 801b7a0 <strncmp>
801bb7a: 9b03 ldr r3, [sp, #12]
801bb7c: 2800 cmp r0, #0
801bb7e: d1e1 bne.n 801bb44 <__gethex+0x1d8>
801bb80: e7a2 b.n 801bac8 <__gethex+0x15c>
801bb82: 1ea9 subs r1, r5, #2
801bb84: 4620 mov r0, r4
801bb86: f7fe fbb6 bl 801a2f6 <__any_on>
801bb8a: 2800 cmp r0, #0
801bb8c: d0c2 beq.n 801bb14 <__gethex+0x1a8>
801bb8e: f04f 0903 mov.w r9, #3
801bb92: e7c1 b.n 801bb18 <__gethex+0x1ac>
801bb94: da09 bge.n 801bbaa <__gethex+0x23e>
801bb96: 1b75 subs r5, r6, r5
801bb98: 4621 mov r1, r4
801bb9a: 9801 ldr r0, [sp, #4]
801bb9c: 462a mov r2, r5
801bb9e: f7fe f96b bl 8019e78 <__lshift>
801bba2: 1b7f subs r7, r7, r5
801bba4: 4604 mov r4, r0
801bba6: f100 0a14 add.w sl, r0, #20
801bbaa: f04f 0900 mov.w r9, #0
801bbae: e7b8 b.n 801bb22 <__gethex+0x1b6>
801bbb0: f8d8 5004 ldr.w r5, [r8, #4]
801bbb4: 42bd cmp r5, r7
801bbb6: dd6f ble.n 801bc98 <__gethex+0x32c>
801bbb8: 1bed subs r5, r5, r7
801bbba: 42ae cmp r6, r5
801bbbc: dc34 bgt.n 801bc28 <__gethex+0x2bc>
801bbbe: f8d8 300c ldr.w r3, [r8, #12]
801bbc2: 2b02 cmp r3, #2
801bbc4: d022 beq.n 801bc0c <__gethex+0x2a0>
801bbc6: 2b03 cmp r3, #3
801bbc8: d024 beq.n 801bc14 <__gethex+0x2a8>
801bbca: 2b01 cmp r3, #1
801bbcc: d115 bne.n 801bbfa <__gethex+0x28e>
801bbce: 42ae cmp r6, r5
801bbd0: d113 bne.n 801bbfa <__gethex+0x28e>
801bbd2: 2e01 cmp r6, #1
801bbd4: d10b bne.n 801bbee <__gethex+0x282>
801bbd6: 9a02 ldr r2, [sp, #8]
801bbd8: f8d8 3004 ldr.w r3, [r8, #4]
801bbdc: 6013 str r3, [r2, #0]
801bbde: 2301 movs r3, #1
801bbe0: 6123 str r3, [r4, #16]
801bbe2: f8ca 3000 str.w r3, [sl]
801bbe6: 9b0e ldr r3, [sp, #56] @ 0x38
801bbe8: 2562 movs r5, #98 @ 0x62
801bbea: 601c str r4, [r3, #0]
801bbec: e73a b.n 801ba64 <__gethex+0xf8>
801bbee: 1e71 subs r1, r6, #1
801bbf0: 4620 mov r0, r4
801bbf2: f7fe fb80 bl 801a2f6 <__any_on>
801bbf6: 2800 cmp r0, #0
801bbf8: d1ed bne.n 801bbd6 <__gethex+0x26a>
801bbfa: 9801 ldr r0, [sp, #4]
801bbfc: 4621 mov r1, r4
801bbfe: f7fd ff21 bl 8019a44 <_Bfree>
801bc02: 9a0e ldr r2, [sp, #56] @ 0x38
801bc04: 2300 movs r3, #0
801bc06: 6013 str r3, [r2, #0]
801bc08: 2550 movs r5, #80 @ 0x50
801bc0a: e72b b.n 801ba64 <__gethex+0xf8>
801bc0c: 9b0f ldr r3, [sp, #60] @ 0x3c
801bc0e: 2b00 cmp r3, #0
801bc10: d1f3 bne.n 801bbfa <__gethex+0x28e>
801bc12: e7e0 b.n 801bbd6 <__gethex+0x26a>
801bc14: 9b0f ldr r3, [sp, #60] @ 0x3c
801bc16: 2b00 cmp r3, #0
801bc18: d1dd bne.n 801bbd6 <__gethex+0x26a>
801bc1a: e7ee b.n 801bbfa <__gethex+0x28e>
801bc1c: 0801c8db .word 0x0801c8db
801bc20: 0801c871 .word 0x0801c871
801bc24: 0801c932 .word 0x0801c932
801bc28: 1e6f subs r7, r5, #1
801bc2a: f1b9 0f00 cmp.w r9, #0
801bc2e: d130 bne.n 801bc92 <__gethex+0x326>
801bc30: b127 cbz r7, 801bc3c <__gethex+0x2d0>
801bc32: 4639 mov r1, r7
801bc34: 4620 mov r0, r4
801bc36: f7fe fb5e bl 801a2f6 <__any_on>
801bc3a: 4681 mov r9, r0
801bc3c: 117a asrs r2, r7, #5
801bc3e: 2301 movs r3, #1
801bc40: f85a 2022 ldr.w r2, [sl, r2, lsl #2]
801bc44: f007 071f and.w r7, r7, #31
801bc48: 40bb lsls r3, r7
801bc4a: 4213 tst r3, r2
801bc4c: 4629 mov r1, r5
801bc4e: 4620 mov r0, r4
801bc50: bf18 it ne
801bc52: f049 0902 orrne.w r9, r9, #2
801bc56: f7ff fe21 bl 801b89c <rshift>
801bc5a: f8d8 7004 ldr.w r7, [r8, #4]
801bc5e: 1b76 subs r6, r6, r5
801bc60: 2502 movs r5, #2
801bc62: f1b9 0f00 cmp.w r9, #0
801bc66: d047 beq.n 801bcf8 <__gethex+0x38c>
801bc68: f8d8 300c ldr.w r3, [r8, #12]
801bc6c: 2b02 cmp r3, #2
801bc6e: d015 beq.n 801bc9c <__gethex+0x330>
801bc70: 2b03 cmp r3, #3
801bc72: d017 beq.n 801bca4 <__gethex+0x338>
801bc74: 2b01 cmp r3, #1
801bc76: d109 bne.n 801bc8c <__gethex+0x320>
801bc78: f019 0f02 tst.w r9, #2
801bc7c: d006 beq.n 801bc8c <__gethex+0x320>
801bc7e: f8da 3000 ldr.w r3, [sl]
801bc82: ea49 0903 orr.w r9, r9, r3
801bc86: f019 0f01 tst.w r9, #1
801bc8a: d10e bne.n 801bcaa <__gethex+0x33e>
801bc8c: f045 0510 orr.w r5, r5, #16
801bc90: e032 b.n 801bcf8 <__gethex+0x38c>
801bc92: f04f 0901 mov.w r9, #1
801bc96: e7d1 b.n 801bc3c <__gethex+0x2d0>
801bc98: 2501 movs r5, #1
801bc9a: e7e2 b.n 801bc62 <__gethex+0x2f6>
801bc9c: 9b0f ldr r3, [sp, #60] @ 0x3c
801bc9e: f1c3 0301 rsb r3, r3, #1
801bca2: 930f str r3, [sp, #60] @ 0x3c
801bca4: 9b0f ldr r3, [sp, #60] @ 0x3c
801bca6: 2b00 cmp r3, #0
801bca8: d0f0 beq.n 801bc8c <__gethex+0x320>
801bcaa: f8d4 b010 ldr.w fp, [r4, #16]
801bcae: f104 0314 add.w r3, r4, #20
801bcb2: ea4f 0a8b mov.w sl, fp, lsl #2
801bcb6: eb03 018b add.w r1, r3, fp, lsl #2
801bcba: f04f 0c00 mov.w ip, #0
801bcbe: 4618 mov r0, r3
801bcc0: f853 2b04 ldr.w r2, [r3], #4
801bcc4: f1b2 3fff cmp.w r2, #4294967295 @ 0xffffffff
801bcc8: d01b beq.n 801bd02 <__gethex+0x396>
801bcca: 3201 adds r2, #1
801bccc: 6002 str r2, [r0, #0]
801bcce: 2d02 cmp r5, #2
801bcd0: f104 0314 add.w r3, r4, #20
801bcd4: d13c bne.n 801bd50 <__gethex+0x3e4>
801bcd6: f8d8 2000 ldr.w r2, [r8]
801bcda: 3a01 subs r2, #1
801bcdc: 42b2 cmp r2, r6
801bcde: d109 bne.n 801bcf4 <__gethex+0x388>
801bce0: 1171 asrs r1, r6, #5
801bce2: 2201 movs r2, #1
801bce4: f853 3021 ldr.w r3, [r3, r1, lsl #2]
801bce8: f006 061f and.w r6, r6, #31
801bcec: fa02 f606 lsl.w r6, r2, r6
801bcf0: 421e tst r6, r3
801bcf2: d13a bne.n 801bd6a <__gethex+0x3fe>
801bcf4: f045 0520 orr.w r5, r5, #32
801bcf8: 9b0e ldr r3, [sp, #56] @ 0x38
801bcfa: 601c str r4, [r3, #0]
801bcfc: 9b02 ldr r3, [sp, #8]
801bcfe: 601f str r7, [r3, #0]
801bd00: e6b0 b.n 801ba64 <__gethex+0xf8>
801bd02: 4299 cmp r1, r3
801bd04: f843 cc04 str.w ip, [r3, #-4]
801bd08: d8d9 bhi.n 801bcbe <__gethex+0x352>
801bd0a: 68a3 ldr r3, [r4, #8]
801bd0c: 459b cmp fp, r3
801bd0e: db17 blt.n 801bd40 <__gethex+0x3d4>
801bd10: 6861 ldr r1, [r4, #4]
801bd12: 9801 ldr r0, [sp, #4]
801bd14: 3101 adds r1, #1
801bd16: f7fd fe57 bl 80199c8 <_Balloc>
801bd1a: 4681 mov r9, r0
801bd1c: b918 cbnz r0, 801bd26 <__gethex+0x3ba>
801bd1e: 4b1a ldr r3, [pc, #104] @ (801bd88 <__gethex+0x41c>)
801bd20: 4602 mov r2, r0
801bd22: 2184 movs r1, #132 @ 0x84
801bd24: e6c5 b.n 801bab2 <__gethex+0x146>
801bd26: 6922 ldr r2, [r4, #16]
801bd28: 3202 adds r2, #2
801bd2a: f104 010c add.w r1, r4, #12
801bd2e: 0092 lsls r2, r2, #2
801bd30: 300c adds r0, #12
801bd32: f7fc fece bl 8018ad2 <memcpy>
801bd36: 4621 mov r1, r4
801bd38: 9801 ldr r0, [sp, #4]
801bd3a: f7fd fe83 bl 8019a44 <_Bfree>
801bd3e: 464c mov r4, r9
801bd40: 6923 ldr r3, [r4, #16]
801bd42: 1c5a adds r2, r3, #1
801bd44: eb04 0383 add.w r3, r4, r3, lsl #2
801bd48: 6122 str r2, [r4, #16]
801bd4a: 2201 movs r2, #1
801bd4c: 615a str r2, [r3, #20]
801bd4e: e7be b.n 801bcce <__gethex+0x362>
801bd50: 6922 ldr r2, [r4, #16]
801bd52: 455a cmp r2, fp
801bd54: dd0b ble.n 801bd6e <__gethex+0x402>
801bd56: 2101 movs r1, #1
801bd58: 4620 mov r0, r4
801bd5a: f7ff fd9f bl 801b89c <rshift>
801bd5e: f8d8 3008 ldr.w r3, [r8, #8]
801bd62: 3701 adds r7, #1
801bd64: 42bb cmp r3, r7
801bd66: f6ff aee0 blt.w 801bb2a <__gethex+0x1be>
801bd6a: 2501 movs r5, #1
801bd6c: e7c2 b.n 801bcf4 <__gethex+0x388>
801bd6e: f016 061f ands.w r6, r6, #31
801bd72: d0fa beq.n 801bd6a <__gethex+0x3fe>
801bd74: 4453 add r3, sl
801bd76: f1c6 0620 rsb r6, r6, #32
801bd7a: f853 0c04 ldr.w r0, [r3, #-4]
801bd7e: f7fd ff13 bl 8019ba8 <__hi0bits>
801bd82: 42b0 cmp r0, r6
801bd84: dbe7 blt.n 801bd56 <__gethex+0x3ea>
801bd86: e7f0 b.n 801bd6a <__gethex+0x3fe>
801bd88: 0801c871 .word 0x0801c871
0801bd8c <L_shift>:
801bd8c: f1c2 0208 rsb r2, r2, #8
801bd90: 0092 lsls r2, r2, #2
801bd92: b570 push {r4, r5, r6, lr}
801bd94: f1c2 0620 rsb r6, r2, #32
801bd98: 6843 ldr r3, [r0, #4]
801bd9a: 6804 ldr r4, [r0, #0]
801bd9c: fa03 f506 lsl.w r5, r3, r6
801bda0: 432c orrs r4, r5
801bda2: 40d3 lsrs r3, r2
801bda4: 6004 str r4, [r0, #0]
801bda6: f840 3f04 str.w r3, [r0, #4]!
801bdaa: 4288 cmp r0, r1
801bdac: d3f4 bcc.n 801bd98 <L_shift+0xc>
801bdae: bd70 pop {r4, r5, r6, pc}
0801bdb0 <__match>:
801bdb0: b530 push {r4, r5, lr}
801bdb2: 6803 ldr r3, [r0, #0]
801bdb4: 3301 adds r3, #1
801bdb6: f811 4b01 ldrb.w r4, [r1], #1
801bdba: b914 cbnz r4, 801bdc2 <__match+0x12>
801bdbc: 6003 str r3, [r0, #0]
801bdbe: 2001 movs r0, #1
801bdc0: bd30 pop {r4, r5, pc}
801bdc2: f813 2b01 ldrb.w r2, [r3], #1
801bdc6: f1a2 0541 sub.w r5, r2, #65 @ 0x41
801bdca: 2d19 cmp r5, #25
801bdcc: bf98 it ls
801bdce: 3220 addls r2, #32
801bdd0: 42a2 cmp r2, r4
801bdd2: d0f0 beq.n 801bdb6 <__match+0x6>
801bdd4: 2000 movs r0, #0
801bdd6: e7f3 b.n 801bdc0 <__match+0x10>
0801bdd8 <__hexnan>:
801bdd8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
801bddc: 680b ldr r3, [r1, #0]
801bdde: 6801 ldr r1, [r0, #0]
801bde0: 115e asrs r6, r3, #5
801bde2: eb02 0686 add.w r6, r2, r6, lsl #2
801bde6: f013 031f ands.w r3, r3, #31
801bdea: b087 sub sp, #28
801bdec: bf18 it ne
801bdee: 3604 addne r6, #4
801bdf0: 2500 movs r5, #0
801bdf2: 1f37 subs r7, r6, #4
801bdf4: 4682 mov sl, r0
801bdf6: 4690 mov r8, r2
801bdf8: 9301 str r3, [sp, #4]
801bdfa: f846 5c04 str.w r5, [r6, #-4]
801bdfe: 46b9 mov r9, r7
801be00: 463c mov r4, r7
801be02: 9502 str r5, [sp, #8]
801be04: 46ab mov fp, r5
801be06: 784a ldrb r2, [r1, #1]
801be08: 1c4b adds r3, r1, #1
801be0a: 9303 str r3, [sp, #12]
801be0c: b342 cbz r2, 801be60 <__hexnan+0x88>
801be0e: 4610 mov r0, r2
801be10: 9105 str r1, [sp, #20]
801be12: 9204 str r2, [sp, #16]
801be14: f7ff fd94 bl 801b940 <__hexdig_fun>
801be18: 2800 cmp r0, #0
801be1a: d153 bne.n 801bec4 <__hexnan+0xec>
801be1c: 9a04 ldr r2, [sp, #16]
801be1e: 9905 ldr r1, [sp, #20]
801be20: 2a20 cmp r2, #32
801be22: d818 bhi.n 801be56 <__hexnan+0x7e>
801be24: 9b02 ldr r3, [sp, #8]
801be26: 459b cmp fp, r3
801be28: dd13 ble.n 801be52 <__hexnan+0x7a>
801be2a: 454c cmp r4, r9
801be2c: d206 bcs.n 801be3c <__hexnan+0x64>
801be2e: 2d07 cmp r5, #7
801be30: dc04 bgt.n 801be3c <__hexnan+0x64>
801be32: 462a mov r2, r5
801be34: 4649 mov r1, r9
801be36: 4620 mov r0, r4
801be38: f7ff ffa8 bl 801bd8c <L_shift>
801be3c: 4544 cmp r4, r8
801be3e: d954 bls.n 801beea <__hexnan+0x112>
801be40: 2300 movs r3, #0
801be42: f1a4 0904 sub.w r9, r4, #4
801be46: f844 3c04 str.w r3, [r4, #-4]
801be4a: f8cd b008 str.w fp, [sp, #8]
801be4e: 464c mov r4, r9
801be50: 461d mov r5, r3
801be52: 9903 ldr r1, [sp, #12]
801be54: e7d7 b.n 801be06 <__hexnan+0x2e>
801be56: 2a29 cmp r2, #41 @ 0x29
801be58: d159 bne.n 801bf0e <__hexnan+0x136>
801be5a: 3102 adds r1, #2
801be5c: f8ca 1000 str.w r1, [sl]
801be60: f1bb 0f00 cmp.w fp, #0
801be64: d053 beq.n 801bf0e <__hexnan+0x136>
801be66: 454c cmp r4, r9
801be68: d206 bcs.n 801be78 <__hexnan+0xa0>
801be6a: 2d07 cmp r5, #7
801be6c: dc04 bgt.n 801be78 <__hexnan+0xa0>
801be6e: 462a mov r2, r5
801be70: 4649 mov r1, r9
801be72: 4620 mov r0, r4
801be74: f7ff ff8a bl 801bd8c <L_shift>
801be78: 4544 cmp r4, r8
801be7a: d938 bls.n 801beee <__hexnan+0x116>
801be7c: f1a8 0204 sub.w r2, r8, #4
801be80: 4623 mov r3, r4
801be82: f853 1b04 ldr.w r1, [r3], #4
801be86: f842 1f04 str.w r1, [r2, #4]!
801be8a: 429f cmp r7, r3
801be8c: d2f9 bcs.n 801be82 <__hexnan+0xaa>
801be8e: 1b3b subs r3, r7, r4
801be90: f023 0303 bic.w r3, r3, #3
801be94: 3401 adds r4, #1
801be96: 3e03 subs r6, #3
801be98: 42b4 cmp r4, r6
801be9a: bf88 it hi
801be9c: 2300 movhi r3, #0
801be9e: f108 0204 add.w r2, r8, #4
801bea2: 4413 add r3, r2
801bea4: 2100 movs r1, #0
801bea6: 461a mov r2, r3
801bea8: 3304 adds r3, #4
801beaa: 429f cmp r7, r3
801beac: 6011 str r1, [r2, #0]
801beae: d2fa bcs.n 801bea6 <__hexnan+0xce>
801beb0: 683b ldr r3, [r7, #0]
801beb2: b91b cbnz r3, 801bebc <__hexnan+0xe4>
801beb4: 4547 cmp r7, r8
801beb6: d128 bne.n 801bf0a <__hexnan+0x132>
801beb8: 2301 movs r3, #1
801beba: 603b str r3, [r7, #0]
801bebc: 2005 movs r0, #5
801bebe: b007 add sp, #28
801bec0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
801bec4: 3501 adds r5, #1
801bec6: 2d08 cmp r5, #8
801bec8: f10b 0b01 add.w fp, fp, #1
801becc: dd06 ble.n 801bedc <__hexnan+0x104>
801bece: 4544 cmp r4, r8
801bed0: d9bf bls.n 801be52 <__hexnan+0x7a>
801bed2: 2300 movs r3, #0
801bed4: f844 3c04 str.w r3, [r4, #-4]
801bed8: 2501 movs r5, #1
801beda: 3c04 subs r4, #4
801bedc: 6822 ldr r2, [r4, #0]
801bede: f000 000f and.w r0, r0, #15
801bee2: ea40 1002 orr.w r0, r0, r2, lsl #4
801bee6: 6020 str r0, [r4, #0]
801bee8: e7b3 b.n 801be52 <__hexnan+0x7a>
801beea: 2508 movs r5, #8
801beec: e7b1 b.n 801be52 <__hexnan+0x7a>
801beee: 9b01 ldr r3, [sp, #4]
801bef0: 2b00 cmp r3, #0
801bef2: d0dd beq.n 801beb0 <__hexnan+0xd8>
801bef4: f1c3 0320 rsb r3, r3, #32
801bef8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
801befc: 40da lsrs r2, r3
801befe: f856 3c04 ldr.w r3, [r6, #-4]
801bf02: 4013 ands r3, r2
801bf04: f846 3c04 str.w r3, [r6, #-4]
801bf08: e7d2 b.n 801beb0 <__hexnan+0xd8>
801bf0a: 3f04 subs r7, #4
801bf0c: e7d0 b.n 801beb0 <__hexnan+0xd8>
801bf0e: 2004 movs r0, #4
801bf10: e7d5 b.n 801bebe <__hexnan+0xe6>
0801bf12 <__ascii_mbtowc>:
801bf12: b082 sub sp, #8
801bf14: b901 cbnz r1, 801bf18 <__ascii_mbtowc+0x6>
801bf16: a901 add r1, sp, #4
801bf18: b142 cbz r2, 801bf2c <__ascii_mbtowc+0x1a>
801bf1a: b14b cbz r3, 801bf30 <__ascii_mbtowc+0x1e>
801bf1c: 7813 ldrb r3, [r2, #0]
801bf1e: 600b str r3, [r1, #0]
801bf20: 7812 ldrb r2, [r2, #0]
801bf22: 1e10 subs r0, r2, #0
801bf24: bf18 it ne
801bf26: 2001 movne r0, #1
801bf28: b002 add sp, #8
801bf2a: 4770 bx lr
801bf2c: 4610 mov r0, r2
801bf2e: e7fb b.n 801bf28 <__ascii_mbtowc+0x16>
801bf30: f06f 0001 mvn.w r0, #1
801bf34: e7f8 b.n 801bf28 <__ascii_mbtowc+0x16>
0801bf36 <_realloc_r>:
801bf36: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801bf3a: 4607 mov r7, r0
801bf3c: 4614 mov r4, r2
801bf3e: 460d mov r5, r1
801bf40: b921 cbnz r1, 801bf4c <_realloc_r+0x16>
801bf42: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
801bf46: 4611 mov r1, r2
801bf48: f7fd bcb2 b.w 80198b0 <_malloc_r>
801bf4c: b92a cbnz r2, 801bf5a <_realloc_r+0x24>
801bf4e: f7fd fc3b bl 80197c8 <_free_r>
801bf52: 4625 mov r5, r4
801bf54: 4628 mov r0, r5
801bf56: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
801bf5a: f000 f840 bl 801bfde <_malloc_usable_size_r>
801bf5e: 4284 cmp r4, r0
801bf60: 4606 mov r6, r0
801bf62: d802 bhi.n 801bf6a <_realloc_r+0x34>
801bf64: ebb4 0f50 cmp.w r4, r0, lsr #1
801bf68: d8f4 bhi.n 801bf54 <_realloc_r+0x1e>
801bf6a: 4621 mov r1, r4
801bf6c: 4638 mov r0, r7
801bf6e: f7fd fc9f bl 80198b0 <_malloc_r>
801bf72: 4680 mov r8, r0
801bf74: b908 cbnz r0, 801bf7a <_realloc_r+0x44>
801bf76: 4645 mov r5, r8
801bf78: e7ec b.n 801bf54 <_realloc_r+0x1e>
801bf7a: 42b4 cmp r4, r6
801bf7c: 4622 mov r2, r4
801bf7e: 4629 mov r1, r5
801bf80: bf28 it cs
801bf82: 4632 movcs r2, r6
801bf84: f7fc fda5 bl 8018ad2 <memcpy>
801bf88: 4629 mov r1, r5
801bf8a: 4638 mov r0, r7
801bf8c: f7fd fc1c bl 80197c8 <_free_r>
801bf90: e7f1 b.n 801bf76 <_realloc_r+0x40>
0801bf92 <__ascii_wctomb>:
801bf92: 4603 mov r3, r0
801bf94: 4608 mov r0, r1
801bf96: b141 cbz r1, 801bfaa <__ascii_wctomb+0x18>
801bf98: 2aff cmp r2, #255 @ 0xff
801bf9a: d904 bls.n 801bfa6 <__ascii_wctomb+0x14>
801bf9c: 228a movs r2, #138 @ 0x8a
801bf9e: 601a str r2, [r3, #0]
801bfa0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
801bfa4: 4770 bx lr
801bfa6: 700a strb r2, [r1, #0]
801bfa8: 2001 movs r0, #1
801bfaa: 4770 bx lr
0801bfac <fiprintf>:
801bfac: b40e push {r1, r2, r3}
801bfae: b503 push {r0, r1, lr}
801bfb0: 4601 mov r1, r0
801bfb2: ab03 add r3, sp, #12
801bfb4: 4805 ldr r0, [pc, #20] @ (801bfcc <fiprintf+0x20>)
801bfb6: f853 2b04 ldr.w r2, [r3], #4
801bfba: 6800 ldr r0, [r0, #0]
801bfbc: 9301 str r3, [sp, #4]
801bfbe: f7ff f9bb bl 801b338 <_vfiprintf_r>
801bfc2: b002 add sp, #8
801bfc4: f85d eb04 ldr.w lr, [sp], #4
801bfc8: b003 add sp, #12
801bfca: 4770 bx lr
801bfcc: 2000011c .word 0x2000011c
0801bfd0 <abort>:
801bfd0: b508 push {r3, lr}
801bfd2: 2006 movs r0, #6
801bfd4: f000 f834 bl 801c040 <raise>
801bfd8: 2001 movs r0, #1
801bfda: f7e9 f871 bl 80050c0 <_exit>
0801bfde <_malloc_usable_size_r>:
801bfde: f851 3c04 ldr.w r3, [r1, #-4]
801bfe2: 1f18 subs r0, r3, #4
801bfe4: 2b00 cmp r3, #0
801bfe6: bfbc itt lt
801bfe8: 580b ldrlt r3, [r1, r0]
801bfea: 18c0 addlt r0, r0, r3
801bfec: 4770 bx lr
0801bfee <_raise_r>:
801bfee: 291f cmp r1, #31
801bff0: b538 push {r3, r4, r5, lr}
801bff2: 4605 mov r5, r0
801bff4: 460c mov r4, r1
801bff6: d904 bls.n 801c002 <_raise_r+0x14>
801bff8: 2316 movs r3, #22
801bffa: 6003 str r3, [r0, #0]
801bffc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
801c000: bd38 pop {r3, r4, r5, pc}
801c002: 6bc2 ldr r2, [r0, #60] @ 0x3c
801c004: b112 cbz r2, 801c00c <_raise_r+0x1e>
801c006: f852 3021 ldr.w r3, [r2, r1, lsl #2]
801c00a: b94b cbnz r3, 801c020 <_raise_r+0x32>
801c00c: 4628 mov r0, r5
801c00e: f000 f831 bl 801c074 <_getpid_r>
801c012: 4622 mov r2, r4
801c014: 4601 mov r1, r0
801c016: 4628 mov r0, r5
801c018: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
801c01c: f000 b818 b.w 801c050 <_kill_r>
801c020: 2b01 cmp r3, #1
801c022: d00a beq.n 801c03a <_raise_r+0x4c>
801c024: 1c59 adds r1, r3, #1
801c026: d103 bne.n 801c030 <_raise_r+0x42>
801c028: 2316 movs r3, #22
801c02a: 6003 str r3, [r0, #0]
801c02c: 2001 movs r0, #1
801c02e: e7e7 b.n 801c000 <_raise_r+0x12>
801c030: 2100 movs r1, #0
801c032: f842 1024 str.w r1, [r2, r4, lsl #2]
801c036: 4620 mov r0, r4
801c038: 4798 blx r3
801c03a: 2000 movs r0, #0
801c03c: e7e0 b.n 801c000 <_raise_r+0x12>
...
0801c040 <raise>:
801c040: 4b02 ldr r3, [pc, #8] @ (801c04c <raise+0xc>)
801c042: 4601 mov r1, r0
801c044: 6818 ldr r0, [r3, #0]
801c046: f7ff bfd2 b.w 801bfee <_raise_r>
801c04a: bf00 nop
801c04c: 2000011c .word 0x2000011c
0801c050 <_kill_r>:
801c050: b538 push {r3, r4, r5, lr}
801c052: 4d07 ldr r5, [pc, #28] @ (801c070 <_kill_r+0x20>)
801c054: 2300 movs r3, #0
801c056: 4604 mov r4, r0
801c058: 4608 mov r0, r1
801c05a: 4611 mov r1, r2
801c05c: 602b str r3, [r5, #0]
801c05e: f7e9 f81f bl 80050a0 <_kill>
801c062: 1c43 adds r3, r0, #1
801c064: d102 bne.n 801c06c <_kill_r+0x1c>
801c066: 682b ldr r3, [r5, #0]
801c068: b103 cbz r3, 801c06c <_kill_r+0x1c>
801c06a: 6023 str r3, [r4, #0]
801c06c: bd38 pop {r3, r4, r5, pc}
801c06e: bf00 nop
801c070: 20013c38 .word 0x20013c38
0801c074 <_getpid_r>:
801c074: f7e9 b80c b.w 8005090 <_getpid>
0801c078 <_init>:
801c078: b5f8 push {r3, r4, r5, r6, r7, lr}
801c07a: bf00 nop
801c07c: bcf8 pop {r3, r4, r5, r6, r7}
801c07e: bc08 pop {r3}
801c080: 469e mov lr, r3
801c082: 4770 bx lr
0801c084 <_fini>:
801c084: b5f8 push {r3, r4, r5, r6, r7, lr}
801c086: bf00 nop
801c088: bcf8 pop {r3, r4, r5, r6, r7}
801c08a: bc08 pop {r3}
801c08c: 469e mov lr, r3
801c08e: 4770 bx lr
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