627 lines
18 KiB
C
627 lines
18 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file app_entry.c
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* @author MCD Application Team
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* @brief Entry point of the application
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "app_common.h"
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#include "main.h"
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#include "app_entry.h"
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#include "ble.h"
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#include "tl.h"
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#include "cmsis_os.h"
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#include "shci_tl.h"
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#include "stm32_lpm.h"
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#include "app_debug.h"
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#include "dbg_trace.h"
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#include "shci.h"
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#include "otp.h"
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/* Private includes -----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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/* USER CODE END Includes */
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/* Private typedef -----------------------------------------------------------*/
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extern RTC_HandleTypeDef hrtc;
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/* USER CODE BEGIN PTD */
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/* USER CODE END PTD */
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/* Private defines -----------------------------------------------------------*/
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#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4U*DIVC((sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE), 4U))
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/* USER CODE BEGIN PD */
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/* USER CODE END PD */
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/* Private macros ------------------------------------------------------------*/
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/* USER CODE BEGIN PM */
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/* USER CODE END PM */
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/* Private variables ---------------------------------------------------------*/
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PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
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PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
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PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255U];
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PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
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/* USER CODE BEGIN PV */
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/* USER CODE END PV */
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/* Global variables ----------------------------------------------------------*/
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osMutexId_t MtxShciId;
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osSemaphoreId_t SemShciId;
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osThreadId_t ShciUserEvtProcessId;
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const osThreadAttr_t ShciUserEvtProcess_attr = {
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.name = CFG_SHCI_USER_EVT_PROCESS_NAME,
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.attr_bits = CFG_SHCI_USER_EVT_PROCESS_ATTR_BITS,
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.cb_mem = CFG_SHCI_USER_EVT_PROCESS_CB_MEM,
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.cb_size = CFG_SHCI_USER_EVT_PROCESS_CB_SIZE,
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.stack_mem = CFG_SHCI_USER_EVT_PROCESS_STACK_MEM,
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.priority = CFG_SHCI_USER_EVT_PROCESS_PRIORITY,
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.stack_size = CFG_SHCI_USER_EVT_PROCESS_STACK_SIZE
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};
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/* Private functions prototypes-----------------------------------------------*/
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static void ShciUserEvtProcess(void *argument);
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static void Config_HSE(void);
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static void Reset_Device(void);
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#if (CFG_HW_RESET_BY_FW == 1)
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static void Reset_IPCC(void);
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static void Reset_BackupDomain(void);
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#endif /* CFG_HW_RESET_BY_FW == 1*/
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static void System_Init(void);
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static void SystemPower_Config(void);
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static void appe_Tl_Init(void);
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static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status);
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static void APPE_SysUserEvtRx(void * pPayload);
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static void APPE_SysEvtReadyProcessing(void * pPayload);
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static void APPE_SysEvtError(void * pPayload);
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static void Init_Rtc(void);
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__WEAK void APP_BLE_Init(void);
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/* USER CODE BEGIN PFP */
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/* USER CODE END PFP */
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/* Functions Definition ------------------------------------------------------*/
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void MX_APPE_Config(void)
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{
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/**
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* The OPTVERR flag is wrongly set at power on
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* It shall be cleared before using any HAL_FLASH_xxx() api
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*/
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
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/**
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* Reset some configurations so that the system behave in the same way
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* when either out of nReset or Power On
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*/
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Reset_Device();
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/* Configure HSE Tuning */
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Config_HSE();
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return;
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}
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void MX_APPE_Init(void)
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{
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System_Init(); /**< System initialization */
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SystemPower_Config(); /**< Configure the system Power Mode */
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HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */
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/* USER CODE BEGIN APPE_Init_1 */
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/* USER CODE END APPE_Init_1 */
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appe_Tl_Init(); /* Initialize all transport layers */
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/**
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* From now, the application is waiting for the ready event (VS_HCI_C2_Ready)
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* received on the system channel before starting the Stack
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* This system event is received with APPE_SysUserEvtRx()
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*/
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/* USER CODE BEGIN APPE_Init_2 */
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/* USER CODE END APPE_Init_2 */
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return;
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}
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void Init_Smps(void)
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{
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#if (CFG_USE_SMPS != 0)
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/**
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* Configure and enable SMPS
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*
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* The SMPS configuration is not yet supported by CubeMx
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* when SMPS output voltage is set to 1.4V, the RF output power is limited to 3.7dBm
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* the SMPS output voltage shall be increased for higher RF output power
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*/
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LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
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LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
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LL_PWR_SMPS_Enable();
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#endif /* CFG_USE_SMPS != 0 */
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return;
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}
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void Init_Exti(void)
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{
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/* Enable IPCC(36), HSEM(38) wakeup interrupts on CPU1 */
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LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_36 | LL_EXTI_LINE_38);
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return;
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}
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/* USER CODE BEGIN FD */
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/* USER CODE END FD */
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/*************************************************************
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*
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* LOCAL FUNCTIONS
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*
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*************************************************************/
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static void Reset_Device(void)
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{
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#if (CFG_HW_RESET_BY_FW == 1)
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Reset_BackupDomain();
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Reset_IPCC();
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#endif /* CFG_HW_RESET_BY_FW == 1 */
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return;
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}
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#if (CFG_HW_RESET_BY_FW == 1)
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static void Reset_BackupDomain(void)
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{
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if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
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{
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HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
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/**
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* Write twice the value to flush the APB-AHB bridge
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* This bit shall be written in the register before writing the next one
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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}
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return;
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}
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static void Reset_IPCC(void)
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{
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
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LL_C1_IPCC_ClearFlag_CHx(
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IPCC,
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LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
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| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
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LL_C2_IPCC_ClearFlag_CHx(
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IPCC,
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LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
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| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
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LL_C1_IPCC_DisableTransmitChannel(
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IPCC,
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LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
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| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
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LL_C2_IPCC_DisableTransmitChannel(
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IPCC,
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LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
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| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
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LL_C1_IPCC_DisableReceiveChannel(
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IPCC,
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LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
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| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
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LL_C2_IPCC_DisableReceiveChannel(
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IPCC,
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LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
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| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
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return;
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}
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#endif /* CFG_HW_RESET_BY_FW == 1 */
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static void Config_HSE(void)
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{
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OTP_ID0_t * p_otp;
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/**
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* Read HSE_Tuning from OTP
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*/
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p_otp = (OTP_ID0_t *) OTP_Read(0);
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if (p_otp)
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{
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LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
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}
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return;
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}
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static void System_Init(void)
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{
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Init_Smps();
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Init_Exti();
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Init_Rtc();
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return;
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}
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static void Init_Rtc(void)
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{
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/* Disable RTC registers write protection */
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LL_RTC_DisableWriteProtection(RTC);
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LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER);
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/* Enable RTC registers write protection */
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LL_RTC_EnableWriteProtection(RTC);
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return;
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}
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/**
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* @brief Configure the system for power optimization
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*
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* @note This API configures the system to be ready for low power mode
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*
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* @param None
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* @retval None
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*/
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static void SystemPower_Config(void)
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{
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/**
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* Select HSI as system clock source after Wake Up from Stop mode
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*/
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LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
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/* Initialize low power manager */
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UTIL_LPM_Init();
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/* Initialize the CPU2 reset value before starting CPU2 with C2BOOT */
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LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
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#if (CFG_USB_INTERFACE_ENABLE != 0)
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/**
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* Enable USB power
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*/
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HAL_PWREx_EnableVddUSB();
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#endif /* CFG_USB_INTERFACE_ENABLE != 0 */
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return;
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}
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static void appe_Tl_Init(void)
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{
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TL_MM_Config_t tl_mm_config;
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SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf;
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/**< Reference table initialization */
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TL_Init();
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MtxShciId = osMutexNew(NULL);
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SemShciId = osSemaphoreNew(1, 0, NULL); /*< Create the semaphore and make it busy at initialization */
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/** FreeRTOS system task creation */
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ShciUserEvtProcessId = osThreadNew(ShciUserEvtProcess, NULL, &ShciUserEvtProcess_attr);
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/**< System channel initialization */
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SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer;
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SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot;
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shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf);
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/**< Memory Manager channel initialization */
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tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
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tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
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tl_mm_config.p_AsynchEvtPool = EvtPool;
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tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
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TL_MM_Init(&tl_mm_config);
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TL_Enable();
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return;
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}
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__WEAK void APP_BLE_Init(void)
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{
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}
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static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status)
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{
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switch (status)
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{
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case SHCI_TL_CmdBusy:
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osMutexAcquire(MtxShciId, osWaitForever);
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break;
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case SHCI_TL_CmdAvailable:
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osMutexRelease(MtxShciId);
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break;
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default:
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break;
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}
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return;
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}
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/**
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* The type of the payload for a system user event is tSHCI_UserEvtRxParam
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* When the system event is both :
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* - a ready event (subevtcode = SHCI_SUB_EVT_CODE_READY)
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* - reported by the FUS (sysevt_ready_rsp == FUS_FW_RUNNING)
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* The buffer shall not be released
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* (eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable)
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* When the status is not filled, the buffer is released by default
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*/
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static void APPE_SysUserEvtRx(void * pPayload)
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{
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TL_AsynchEvt_t *p_sys_event;
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WirelessFwInfo_t WirelessInfo;
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p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
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switch(p_sys_event->subevtcode)
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{
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case SHCI_SUB_EVT_CODE_READY:
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/* Read the firmware version of both the wireless firmware and the FUS */
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SHCI_GetWirelessFwInfo(&WirelessInfo);
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APP_DBG_MSG("Wireless Firmware version %d.%d.%d\n", WirelessInfo.VersionMajor, WirelessInfo.VersionMinor, WirelessInfo.VersionSub);
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APP_DBG_MSG("Wireless Firmware build %d\n", WirelessInfo.VersionReleaseType);
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APP_DBG_MSG("FUS version %d.%d.%d\n", WirelessInfo.FusVersionMajor, WirelessInfo.FusVersionMinor, WirelessInfo.FusVersionSub);
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APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY\n\r");
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APPE_SysEvtReadyProcessing(pPayload);
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break;
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case SHCI_SUB_EVT_ERROR_NOTIF:
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APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF \n\r");
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APPE_SysEvtError(pPayload);
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break;
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case SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE:
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APP_DBG_MSG(">>== SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE -- BLE NVM RAM HAS BEEN UPDATED BY CPU2 \n");
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APP_DBG_MSG(" - StartAddress = %lx , Size = %ld\n",
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((SHCI_C2_BleNvmRamUpdate_Evt_t*)p_sys_event->payload)->StartAddress,
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((SHCI_C2_BleNvmRamUpdate_Evt_t*)p_sys_event->payload)->Size);
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break;
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case SHCI_SUB_EVT_NVM_START_WRITE:
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APP_DBG_MSG("==>> SHCI_SUB_EVT_NVM_START_WRITE : NumberOfWords = %ld\n",
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((SHCI_C2_NvmStartWrite_Evt_t*)p_sys_event->payload)->NumberOfWords);
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break;
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case SHCI_SUB_EVT_NVM_END_WRITE:
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APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_WRITE\n\r");
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break;
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case SHCI_SUB_EVT_NVM_START_ERASE:
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APP_DBG_MSG("==>>SHCI_SUB_EVT_NVM_START_ERASE : NumberOfSectors = %ld\n",
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((SHCI_C2_NvmStartErase_Evt_t*)p_sys_event->payload)->NumberOfSectors);
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break;
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case SHCI_SUB_EVT_NVM_END_ERASE:
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APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_ERASE\n\r");
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break;
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default:
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break;
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}
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return;
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}
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/**
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* @brief Notify a system error coming from the M0 firmware
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* @param ErrorCode : errorCode detected by the M0 firmware
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*
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* @retval None
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*/
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static void APPE_SysEvtError(void * pPayload)
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{
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TL_AsynchEvt_t *p_sys_event;
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SCHI_SystemErrCode_t *p_sys_error_code;
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p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
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p_sys_error_code = (SCHI_SystemErrCode_t*) p_sys_event->payload;
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APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON %x \n\r",(*p_sys_error_code));
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if ((*p_sys_error_code) == ERR_BLE_INIT)
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{
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/* Error during BLE stack initialization */
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APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - ERR_BLE_INIT \n");
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}
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else
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{
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APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - BLE ERROR \n");
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}
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return;
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}
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static void APPE_SysEvtReadyProcessing(void * pPayload)
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{
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TL_AsynchEvt_t *p_sys_event;
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SHCI_C2_Ready_Evt_t *p_sys_ready_event;
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SHCI_C2_CONFIG_Cmd_Param_t config_param = {0};
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uint32_t RevisionID=0;
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uint32_t DeviceID=0;
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p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload);
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p_sys_ready_event = (SHCI_C2_Ready_Evt_t*) p_sys_event->payload;
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if (p_sys_ready_event->sysevt_ready_rsp == WIRELESS_FW_RUNNING)
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{
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/**
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* The wireless firmware is running on the CPU2
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*/
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APP_DBG_MSG(">>== WIRELESS_FW_RUNNING \n");
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|
/* Traces channel initialization */
|
|
APPD_EnableCPU2();
|
|
|
|
/* Enable all events Notification */
|
|
config_param.PayloadCmdSize = SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE;
|
|
config_param.EvtMask1 = SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE
|
|
+ SHCI_C2_CONFIG_EVTMASK1_BIT1_BLE_NVM_RAM_UPDATE_ENABLE
|
|
+ SHCI_C2_CONFIG_EVTMASK1_BIT2_THREAD_NVM_RAM_UPDATE_ENABLE
|
|
+ SHCI_C2_CONFIG_EVTMASK1_BIT3_NVM_START_WRITE_ENABLE
|
|
+ SHCI_C2_CONFIG_EVTMASK1_BIT4_NVM_END_WRITE_ENABLE
|
|
+ SHCI_C2_CONFIG_EVTMASK1_BIT5_NVM_START_ERASE_ENABLE
|
|
+ SHCI_C2_CONFIG_EVTMASK1_BIT6_NVM_END_ERASE_ENABLE;
|
|
|
|
/* Read revision identifier */
|
|
/**
|
|
* @brief Return the device revision identifier
|
|
* @note This field indicates the revision of the device.
|
|
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
|
|
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
|
|
*/
|
|
RevisionID = LL_DBGMCU_GetRevisionID();
|
|
|
|
APP_DBG_MSG(">>== DBGMCU_GetRevisionID= %lx \n\r", RevisionID);
|
|
|
|
config_param.RevisionID = (uint16_t)RevisionID;
|
|
|
|
DeviceID = LL_DBGMCU_GetDeviceID();
|
|
APP_DBG_MSG(">>== DBGMCU_GetDeviceID= %lx \n\r", DeviceID);
|
|
config_param.DeviceID = (uint16_t)DeviceID;
|
|
(void)SHCI_C2_Config(&config_param);
|
|
|
|
APP_BLE_Init();
|
|
UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE);
|
|
}
|
|
else if (p_sys_ready_event->sysevt_ready_rsp == FUS_FW_RUNNING)
|
|
{
|
|
/**
|
|
* The FUS firmware is running on the CPU2
|
|
* In the scope of this application, there should be no case when we get here
|
|
*/
|
|
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - FUS_FW_RUNNING \n\r");
|
|
|
|
/* The packet shall not be released as this is not supported by the FUS */
|
|
((tSHCI_UserEvtRxParam*)pPayload)->status = SHCI_TL_UserEventFlow_Disable;
|
|
}
|
|
else
|
|
{
|
|
APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - UNEXPECTED CASE \n\r");
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
/*************************************************************
|
|
*
|
|
* FREERTOS WRAPPER FUNCTIONS
|
|
*
|
|
*************************************************************/
|
|
static void ShciUserEvtProcess(void *argument)
|
|
{
|
|
UNUSED(argument);
|
|
for(;;)
|
|
{
|
|
/* USER CODE BEGIN SHCI_USER_EVT_PROCESS_1 */
|
|
|
|
/* USER CODE END SHCI_USER_EVT_PROCESS_1 */
|
|
osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever);
|
|
shci_user_evt_proc();
|
|
/* USER CODE BEGIN SHCI_USER_EVT_PROCESS_2 */
|
|
|
|
/* USER CODE END SHCI_USER_EVT_PROCESS_2 */
|
|
}
|
|
}
|
|
|
|
/* USER CODE BEGIN FD_LOCAL_FUNCTIONS */
|
|
|
|
/* USER CODE END FD_LOCAL_FUNCTIONS */
|
|
|
|
/*************************************************************
|
|
*
|
|
* WRAP FUNCTIONS
|
|
*
|
|
*************************************************************/
|
|
void HAL_Delay(uint32_t Delay)
|
|
{
|
|
uint32_t tickstart = HAL_GetTick();
|
|
uint32_t wait = Delay;
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
{
|
|
wait += HAL_GetTickFreq();
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
{
|
|
/************************************************************************************
|
|
* ENTER SLEEP MODE
|
|
***********************************************************************************/
|
|
LL_LPM_EnableSleep(); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
|
|
|
|
/**
|
|
* This option is used to ensure that store operations are completed
|
|
*/
|
|
#if defined (__CC_ARM) || defined (__ARMCC_VERSION)
|
|
__force_stores();
|
|
#endif /* __ARMCC_VERSION */
|
|
|
|
__WFI();
|
|
}
|
|
}
|
|
|
|
void shci_notify_asynch_evt(void* pdata)
|
|
{
|
|
UNUSED(pdata);
|
|
osThreadFlagsSet(ShciUserEvtProcessId, 1);
|
|
return;
|
|
}
|
|
|
|
void shci_cmd_resp_release(uint32_t flag)
|
|
{
|
|
UNUSED(flag);
|
|
osSemaphoreRelease(SemShciId);
|
|
return;
|
|
}
|
|
|
|
void shci_cmd_resp_wait(uint32_t timeout)
|
|
{
|
|
UNUSED(timeout);
|
|
osSemaphoreAcquire(SemShciId, osWaitForever);
|
|
return;
|
|
}
|
|
|
|
/* USER CODE BEGIN FD_WRAP_FUNCTIONS */
|
|
|
|
/* USER CODE END FD_WRAP_FUNCTIONS */
|