174 lines
5.2 KiB
C
174 lines
5.2 KiB
C
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/**
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******************************************************************************
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* @file stm32wbxx_ll_pwr.c
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* @author MCD Application Team
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* @brief PWR LL module driver.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32wbxx_ll_pwr.h"
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#include "stm32wbxx_ll_bus.h"
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/** @addtogroup STM32WBxx_LL_Driver
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* @{
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*/
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#if defined(PWR)
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/** @defgroup PWR_LL PWR
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup PWR_LL_Private_Constants PWR Private Constants
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* @{
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*/
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/* Definitions of PWR registers reset value */
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#define PWR_CR1_RESET_VALUE (0x00000200)
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#define PWR_CR2_RESET_VALUE (0x00000000)
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#define PWR_CR3_RESET_VALUE (0x00008000)
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#define PWR_CR4_RESET_VALUE (0x00000000)
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#define PWR_CR5_RESET_VALUE (0x00004272)
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#define PWR_PUCRA_RESET_VALUE (0x00000000)
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#define PWR_PDCRA_RESET_VALUE (0x00000000)
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#define PWR_PUCRB_RESET_VALUE (0x00000000)
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#define PWR_PDCRB_RESET_VALUE (0x00000000)
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#define PWR_PUCRC_RESET_VALUE (0x00000000)
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#define PWR_PDCRC_RESET_VALUE (0x00000000)
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#define PWR_PUCRD_RESET_VALUE (0x00000000)
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#define PWR_PDCRD_RESET_VALUE (0x00000000)
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#define PWR_PUCRE_RESET_VALUE (0x00000000)
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#define PWR_PDCRE_RESET_VALUE (0x00000000)
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#define PWR_PUCRH_RESET_VALUE (0x00000000)
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#define PWR_PDCRH_RESET_VALUE (0x00000000)
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#define PWR_C2CR1_RESET_VALUE (0x00000000)
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#define PWR_C2CR3_RESET_VALUE (0x00008000)
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup PWR_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup PWR_LL_EF_Init
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* @{
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*/
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/**
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* @brief De-initialize the PWR registers to their default reset values.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: PWR registers are de-initialized
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* - ERROR: not applicable
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*/
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ErrorStatus LL_PWR_DeInit(void)
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{
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/* Apply reset values to all PWR registers */
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LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE);
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LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE);
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LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE);
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LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE);
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LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE);
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LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE);
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LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE);
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LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE);
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LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
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LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE);
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LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE);
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#if defined(GPIOD)
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LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE);
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LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE);
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#endif /* GPIOD */
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LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE);
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LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE);
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LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE);
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LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE);
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LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE);
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LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
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/* Clear all flags */
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#if defined(PWR_CR3_E802A) && defined(PWR_CR5_SMPSEN)
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LL_PWR_WriteReg(SCR,
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LL_PWR_SCR_CC2HF
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| LL_PWR_SCR_CBLEAF
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| LL_PWR_SCR_CCRPEF
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| LL_PWR_SCR_C802AF
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| LL_PWR_SCR_C802WUF
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| LL_PWR_SCR_CBLEWUF
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| LL_PWR_SCR_CBORHF
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| LL_PWR_SCR_CSMPSFBF
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| LL_PWR_SCR_CWUF);
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#elif defined(PWR_CR3_E802A)
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LL_PWR_WriteReg(SCR,
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LL_PWR_SCR_CC2HF
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| LL_PWR_SCR_CBLEAF
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| LL_PWR_SCR_CCRPEF
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| LL_PWR_SCR_C802AF
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| LL_PWR_SCR_C802WUF
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| LL_PWR_SCR_CBLEWUF
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| LL_PWR_SCR_CWUF);
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#elif defined(PWR_CR5_SMPSEN)
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LL_PWR_WriteReg(SCR,
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LL_PWR_SCR_CC2HF
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| LL_PWR_SCR_CBLEAF
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| LL_PWR_SCR_CCRPEF
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| LL_PWR_SCR_CBLEWUF
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| LL_PWR_SCR_CBORHF
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| LL_PWR_SCR_CSMPSFBF
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| LL_PWR_SCR_CWUF);
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#else
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LL_PWR_WriteReg(SCR,
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LL_PWR_SCR_CC2HF
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| LL_PWR_SCR_CBLEAF
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| LL_PWR_SCR_CCRPEF
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| LL_PWR_SCR_CBLEWUF
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| LL_PWR_SCR_CWUF);
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#endif
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LL_PWR_WriteReg(EXTSCR,
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LL_PWR_EXTSCR_CCRPF
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| LL_PWR_EXTSCR_C2CSSF
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| LL_PWR_EXTSCR_C1CSSF
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);
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return SUCCESS;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* PWR */
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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