Trinity Devboard PCB V1.0 Firmware. FreeRTOS is setup and the MCU reads IMU data over SPI fand Magnetometer data over I2C, each with a seperate task. Sensordata is then run though MadgwickAHRS and send over USB as serial packet data to use in trinity visualizer. Bare minimum functionality works and is replicated from the first prototype.
This commit is contained in:
+196
@@ -0,0 +1,196 @@
|
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/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
*
|
||||
* Project: CMSIS NN Library
|
||||
* Title: arm_nnexamples_cifar10.cpp
|
||||
*
|
||||
* Description: Convolutional Neural Network Example
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M7
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Arm LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @ingroup groupExamples
|
||||
*/
|
||||
|
||||
/**
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||||
* @defgroup CNNExample Convolutional Neural Network Example
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||||
*
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||||
* \par Description:
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||||
* \par
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||||
* Demonstrates a convolutional neural network (CNN) example with the use of convolution,
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* ReLU activation, pooling and fully-connected functions.
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*
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* \par Model definition:
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* \par
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* The CNN used in this example is based on CIFAR-10 example from Caffe [1].
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* The neural network consists
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* of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a
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* fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will
|
||||
* be classified into one of the 10 output classes.
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* This example model implementation needs 32.3 KB to store weights, 40 KB for activations and
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* 3.1 KB for storing the \c im2col data.
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*
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* \image html CIFAR10_CNN.gif "Neural Network model definition"
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*
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* \par Variables Description:
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||||
* \par
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* \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices
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||||
* \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays
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||||
* \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases
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||||
* \li \c input_data points to the input image data
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* \li \c output_data points to the classification output
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||||
* \li \c col_buffer is a buffer to store the \c im2col output
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* \li \c scratch_buffer is used to store the activation data (intermediate layer outputs)
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||||
*
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||||
* \par CMSIS DSP Software Library Functions Used:
|
||||
* \par
|
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* - arm_convolve_HWC_q7_RGB()
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* - arm_convolve_HWC_q7_fast()
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* - arm_relu_q7()
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* - arm_maxpool_q7_HWC()
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||||
* - arm_avepool_q7_HWC()
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||||
* - arm_fully_connected_q7_opt()
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||||
* - arm_fully_connected_q7()
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||||
*
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||||
* <b> Refer </b>
|
||||
* \link arm_nnexamples_cifar10.cpp \endlink
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*
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* \par [1] https://github.com/BVLC/caffe
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include "arm_math.h"
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#include "arm_nnexamples_cifar10_parameter.h"
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#include "arm_nnexamples_cifar10_weights.h"
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|
||||
#include "arm_nnfunctions.h"
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||||
#include "arm_nnexamples_cifar10_inputs.h"
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||||
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
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||||
#ifdef RTE_Compiler_EventRecorder
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||||
#include "EventRecorder.h"
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||||
#endif
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#endif
|
||||
|
||||
// include the input and weights
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|
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static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT;
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||||
static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS;
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||||
|
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static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT;
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||||
static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS;
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||||
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||||
static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT;
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||||
static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS;
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||||
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||||
static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT;
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||||
static q7_t ip1_bias[IP1_OUT] = IP1_BIAS;
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/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */
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uint8_t image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA;
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q7_t output_data[IP1_OUT];
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||||
//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer)
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q7_t col_buffer[2 * 5 * 5 * 32 * 2];
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||||
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||||
q7_t scratch_buffer[32 * 32 * 10 * 4];
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||||
|
||||
int main()
|
||||
{
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||||
#ifdef RTE_Compiler_EventRecorder
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||||
EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder
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||||
#endif
|
||||
|
||||
printf("start execution\n");
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||||
/* start the execution */
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||||
|
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q7_t *img_buffer1 = scratch_buffer;
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q7_t *img_buffer2 = img_buffer1 + 32 * 32 * 32;
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||||
|
||||
/* input pre-processing */
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int mean_data[3] = INPUT_MEAN_SHIFT;
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unsigned int scale_data[3] = INPUT_RIGHT_SHIFT;
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||||
for (int i=0;i<32*32*3; i+=3) {
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img_buffer2[i] = (q7_t)__SSAT( ((((int)image_data[i] - mean_data[0])<<7) + (0x1<<(scale_data[0]-1)))
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||||
>> scale_data[0], 8);
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img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1)))
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||||
>> scale_data[1], 8);
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||||
img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1)))
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||||
>> scale_data[2], 8);
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||||
}
|
||||
|
||||
// conv1 img_buffer2 -> img_buffer1
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||||
arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING,
|
||||
CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM,
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||||
(q15_t *) col_buffer, NULL);
|
||||
|
||||
arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH);
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||||
|
||||
// pool1 img_buffer1 -> img_buffer2
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||||
arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM,
|
||||
POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2);
|
||||
|
||||
// conv2 img_buffer2 -> img_buffer1
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||||
arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM,
|
||||
CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1,
|
||||
CONV2_OUT_DIM, (q15_t *) col_buffer, NULL);
|
||||
|
||||
arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH);
|
||||
|
||||
// pool2 img_buffer1 -> img_buffer2
|
||||
arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM,
|
||||
POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2);
|
||||
|
||||
// conv3 img_buffer2 -> img_buffer1
|
||||
arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM,
|
||||
CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1,
|
||||
CONV3_OUT_DIM, (q15_t *) col_buffer, NULL);
|
||||
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||||
arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH);
|
||||
|
||||
// pool3 img_buffer-> img_buffer2
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||||
arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM,
|
||||
POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2);
|
||||
|
||||
arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias,
|
||||
output_data, (q15_t *) img_buffer1);
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||||
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||||
arm_softmax_q7(output_data, 10, output_data);
|
||||
|
||||
for (int i = 0; i < 10; i++)
|
||||
{
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||||
printf("%d: %d\n", i, output_data[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
+6
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@@ -0,0 +1,43 @@
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||||
#define CONV1_IM_DIM 32
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||||
#define CONV1_IM_CH 3
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||||
#define CONV1_KER_DIM 5
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||||
#define CONV1_PADDING 2
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||||
#define CONV1_STRIDE 1
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||||
#define CONV1_OUT_CH 32
|
||||
#define CONV1_OUT_DIM 32
|
||||
|
||||
#define POOL1_KER_DIM 3
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||||
#define POOL1_STRIDE 2
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||||
#define POOL1_PADDING 0
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||||
#define POOL1_OUT_DIM 16
|
||||
|
||||
#define CONV2_IM_DIM 16
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||||
#define CONV2_IM_CH 32
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||||
#define CONV2_KER_DIM 5
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||||
#define CONV2_PADDING 2
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||||
#define CONV2_STRIDE 1
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||||
#define CONV2_OUT_CH 16
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||||
#define CONV2_OUT_DIM 16
|
||||
|
||||
#define POOL2_KER_DIM 3
|
||||
#define POOL2_STRIDE 2
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||||
#define POOL2_PADDING 0
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||||
#define POOL2_OUT_DIM 8
|
||||
|
||||
#define CONV3_IM_DIM 8
|
||||
#define CONV3_IM_CH 16
|
||||
#define CONV3_KER_DIM 5
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||||
#define CONV3_PADDING 2
|
||||
#define CONV3_STRIDE 1
|
||||
#define CONV3_OUT_CH 32
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||||
#define CONV3_OUT_DIM 8
|
||||
|
||||
#define POOL3_KER_DIM 3
|
||||
#define POOL3_STRIDE 2
|
||||
#define POOL3_PADDING 0
|
||||
#define POOL3_OUT_DIM 4
|
||||
|
||||
#define IP1_DIM 4*4*32
|
||||
#define IP1_IM_DIM 4
|
||||
#define IP1_IM_CH 32
|
||||
#define IP1_OUT 10
|
||||
+26
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@@ -0,0 +1,7 @@
|
||||
CMSIS NN Lib example arm_nnexample_cifar10 for
|
||||
Cortex-M0, Cortex-M3, Cortex-M4 and Cortex-M7.
|
||||
|
||||
The example is configured for IAR Embedded Workbench for ARM Simulator.
|
||||
|
||||
When changing target, remember to change the ARM_MATH_CMx and __FPU_PRESENT
|
||||
Preprocessor defines for C/C++ Compiler
|
||||
@@ -0,0 +1,221 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
*
|
||||
* Project: CMSIS NN Library
|
||||
* Title: arm_nnexamples_gru.cpp
|
||||
*
|
||||
* Description: Gated Recurrent Unit Example
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M7
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Arm LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @ingroup groupExamples
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GRUExample Gated Recurrent Unit Example
|
||||
*
|
||||
* \par Description:
|
||||
* \par
|
||||
* Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected,
|
||||
* Tanh/Sigmoid activation functions.
|
||||
*
|
||||
* \par Model definition:
|
||||
* \par
|
||||
* GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden
|
||||
* state.
|
||||
* \par
|
||||
* The computation can be summarized as:
|
||||
* <pre>z[t] = sigmoid( W_z ⋅ {h[t-1],x[t]} )
|
||||
* r[t] = sigmoid( W_r ⋅ {h[t-1],x[t]} )
|
||||
* n[t] = tanh( W_n ⋅ [r[t] × {h[t-1], x[t]} )
|
||||
* h[t] = (1 - z[t]) × h[t-1] + z[t] × n[t] </pre>
|
||||
* \image html GRU.gif "Gate Recurrent Unit Diagram"
|
||||
*
|
||||
* \par Variables Description:
|
||||
* \par
|
||||
* \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n).
|
||||
* \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays
|
||||
* \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history
|
||||
*
|
||||
* \par
|
||||
* The buffer is allocated as:
|
||||
* \par
|
||||
* | reset | input | history | update | hidden_state |
|
||||
* \par
|
||||
* In this way, the concatination is automatically done since (reset, input) and (input, history)
|
||||
* are physically concatinated in memory.
|
||||
* \par
|
||||
* The ordering of the weight matrix should be adjusted accordingly.
|
||||
*
|
||||
*
|
||||
*
|
||||
* \par CMSIS DSP Software Library Functions Used:
|
||||
* \par
|
||||
* - arm_fully_connected_mat_q7_vec_q15_opt()
|
||||
* - arm_nn_activations_direct_q15()
|
||||
* - arm_mult_q15()
|
||||
* - arm_offset_q15()
|
||||
* - arm_sub_q15()
|
||||
* - arm_copy_q15()
|
||||
*
|
||||
* <b> Refer </b>
|
||||
* \link arm_nnexamples_gru.cpp \endlink
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <math.h>
|
||||
#include "arm_nnexamples_gru_test_data.h"
|
||||
#include "arm_math.h"
|
||||
#include "arm_nnfunctions.h"
|
||||
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
|
||||
#ifdef RTE_Compiler_EventRecorder
|
||||
#include "EventRecorder.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define DIM_HISTORY 32
|
||||
#define DIM_INPUT 32
|
||||
#define DIM_VEC 64
|
||||
|
||||
#define USE_X4
|
||||
|
||||
#ifndef USE_X4
|
||||
static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2;
|
||||
static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2;
|
||||
static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2;
|
||||
#else
|
||||
static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4;
|
||||
static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4;
|
||||
static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4;
|
||||
#endif
|
||||
|
||||
static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS;
|
||||
static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS;
|
||||
static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS;
|
||||
|
||||
static q15_t test_input1[DIM_INPUT] = INPUT_DATA1;
|
||||
static q15_t test_input2[DIM_INPUT] = INPUT_DATA2;
|
||||
static q15_t test_history[DIM_HISTORY] = HISTORY_DATA;
|
||||
|
||||
q15_t scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT];
|
||||
|
||||
void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size,
|
||||
q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state,
|
||||
q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state)
|
||||
{
|
||||
q15_t *reset = scratch_input;
|
||||
q15_t *input = scratch_input + history_size;
|
||||
q15_t *history = scratch_input + history_size + input_size;
|
||||
q15_t *update = scratch_input + 2 * history_size + input_size;
|
||||
q15_t *hidden_state = scratch_input + 3 * history_size + input_size;
|
||||
|
||||
// reset gate calculation
|
||||
// the range of the output can be adjusted with bias_shift and output_shift
|
||||
#ifndef USE_X4
|
||||
arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset,
|
||||
reset, NULL);
|
||||
#else
|
||||
arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15,
|
||||
bias_reset, reset, NULL);
|
||||
#endif
|
||||
// sigmoid function, the size of the integer bit-width should be consistent with out_shift
|
||||
arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID);
|
||||
arm_mult_q15(history, reset, reset, history_size);
|
||||
|
||||
// update gate calculation
|
||||
// the range of the output can be adjusted with bias_shift and output_shift
|
||||
#ifndef USE_X4
|
||||
arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15,
|
||||
bias_update, update, NULL);
|
||||
#else
|
||||
arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15,
|
||||
bias_update, update, NULL);
|
||||
#endif
|
||||
|
||||
// sigmoid function, the size of the integer bit-width should be consistent with out_shift
|
||||
arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID);
|
||||
|
||||
// hidden state calculation
|
||||
#ifndef USE_X4
|
||||
arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15,
|
||||
bias_hidden_state, hidden_state, NULL);
|
||||
#else
|
||||
arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15,
|
||||
bias_hidden_state, hidden_state, NULL);
|
||||
#endif
|
||||
|
||||
// tanh function, the size of the integer bit-width should be consistent with out_shift
|
||||
arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH);
|
||||
arm_mult_q15(update, hidden_state, hidden_state, history_size);
|
||||
|
||||
// we calculate z - 1 here
|
||||
// so final addition becomes substraction
|
||||
arm_offset_q15(update, 0x8000, update, history_size);
|
||||
// multiply history
|
||||
arm_mult_q15(history, update, update, history_size);
|
||||
// calculate history_out
|
||||
arm_sub_q15(hidden_state, update, history, history_size);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
#ifdef RTE_Compiler_EventRecorder
|
||||
EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder
|
||||
#endif
|
||||
|
||||
printf("Start GRU execution\n");
|
||||
int input_size = DIM_INPUT;
|
||||
int history_size = DIM_HISTORY;
|
||||
|
||||
// copy over the input data
|
||||
arm_copy_q15(test_input1, scratch_buffer + history_size, input_size);
|
||||
arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size);
|
||||
|
||||
gru_example(scratch_buffer, input_size, history_size,
|
||||
update_gate_weights, reset_gate_weights, hidden_state_weights,
|
||||
update_gate_bias, reset_gate_bias, hidden_state_bias);
|
||||
printf("Complete first iteration on GRU\n");
|
||||
|
||||
arm_copy_q15(test_input2, scratch_buffer + history_size, input_size);
|
||||
gru_example(scratch_buffer, input_size, history_size,
|
||||
update_gate_weights, reset_gate_weights, hidden_state_weights,
|
||||
update_gate_bias, reset_gate_bias, hidden_state_bias);
|
||||
printf("Complete second iteration on GRU\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
+23
File diff suppressed because one or more lines are too long
@@ -0,0 +1,7 @@
|
||||
CMSIS NN Lib example arm_nnexample_gru0 for
|
||||
Cortex-M0, Cortex-M3, Cortex-M4 and Cortex-M7.
|
||||
|
||||
The example is configured for IAR Embedded Workbench for ARM Simulator.
|
||||
|
||||
When changing target, remember to change the ARM_MATH_CMx and __FPU_PRESENT
|
||||
Preprocessor defines for C/C++ Compiler
|
||||
Reference in New Issue
Block a user