Trinity_Devboard_V2.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0001d2e8 08000140 08000140 00001140 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000cc8 0801d428 0801d428 0001e428 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 0801e0f0 0801e0f0 0001f0f0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0801e0f8 0801e0f8 0001f0f8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 0801e0fc 0801e0fc 0001f0fc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 000002d0 20000008 0801e100 00020008 2**2 CONTENTS, ALLOC, LOAD, DATA 7 SYSTEM_DRIVER_CONTEXT 00000011 200002d8 0801e3d0 000202d8 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .bss 0001395c 200002ec 0801e3e1 000202ec 2**2 ALLOC 9 ._user_heap_stack 00000600 20013c48 0801e3e1 00020c48 2**0 ALLOC 10 .ARM.attributes 00000030 00000000 00000000 0002194a 2**0 CONTENTS, READONLY 11 MAPPING_TABLE 00000028 20030000 20030000 00022000 2**2 ALLOC 12 MB_MEM1 000000b0 20030028 20030028 00022000 2**2 ALLOC 13 .MB_MEM2 00000872 200300d8 0801e3e1 000210d8 2**2 CONTENTS, ALLOC, LOAD, DATA 14 .debug_info 0003a3c8 00000000 00000000 0002197a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_abbrev 00008612 00000000 00000000 0005bd42 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_aranges 00003650 00000000 00000000 00064358 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_rnglists 00002962 00000000 00000000 000679a8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_macro 000318d9 00000000 00000000 0006a30a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line 0003b3c3 00000000 00000000 0009bbe3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .debug_str 0011291c 00000000 00000000 000d6fa6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .comment 00000043 00000000 00000000 001e98c2 2**0 CONTENTS, READONLY 22 .debug_frame 0000ee1c 00000000 00000000 001e9908 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 23 .debug_line_str 00000061 00000000 00000000 001f8724 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000140 <__do_global_dtors_aux>: 8000140: b510 push {r4, lr} 8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>) 8000144: 7823 ldrb r3, [r4, #0] 8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16> 8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>) 800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12> 800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>) 800014e: f3af 8000 nop.w 8000152: 2301 movs r3, #1 8000154: 7023 strb r3, [r4, #0] 8000156: bd10 pop {r4, pc} 8000158: 200002ec .word 0x200002ec 800015c: 00000000 .word 0x00000000 8000160: 0801d410 .word 0x0801d410 08000164 : 8000164: b508 push {r3, lr} 8000166: 4b03 ldr r3, [pc, #12] @ (8000174 ) 8000168: b11b cbz r3, 8000172 800016a: 4903 ldr r1, [pc, #12] @ (8000178 ) 800016c: 4803 ldr r0, [pc, #12] @ (800017c ) 800016e: f3af 8000 nop.w 8000172: bd08 pop {r3, pc} 8000174: 00000000 .word 0x00000000 8000178: 200002f0 .word 0x200002f0 800017c: 0801d410 .word 0x0801d410 08000180 : 8000180: f001 01ff and.w r1, r1, #255 @ 0xff 8000184: 2a10 cmp r2, #16 8000186: db2b blt.n 80001e0 8000188: f010 0f07 tst.w r0, #7 800018c: d008 beq.n 80001a0 800018e: f810 3b01 ldrb.w r3, [r0], #1 8000192: 3a01 subs r2, #1 8000194: 428b cmp r3, r1 8000196: d02d beq.n 80001f4 8000198: f010 0f07 tst.w r0, #7 800019c: b342 cbz r2, 80001f0 800019e: d1f6 bne.n 800018e 80001a0: b4f0 push {r4, r5, r6, r7} 80001a2: ea41 2101 orr.w r1, r1, r1, lsl #8 80001a6: ea41 4101 orr.w r1, r1, r1, lsl #16 80001aa: f022 0407 bic.w r4, r2, #7 80001ae: f07f 0700 mvns.w r7, #0 80001b2: 2300 movs r3, #0 80001b4: e8f0 5602 ldrd r5, r6, [r0], #8 80001b8: 3c08 subs r4, #8 80001ba: ea85 0501 eor.w r5, r5, r1 80001be: ea86 0601 eor.w r6, r6, r1 80001c2: fa85 f547 uadd8 r5, r5, r7 80001c6: faa3 f587 sel r5, r3, r7 80001ca: fa86 f647 uadd8 r6, r6, r7 80001ce: faa5 f687 sel r6, r5, r7 80001d2: b98e cbnz r6, 80001f8 80001d4: d1ee bne.n 80001b4 80001d6: bcf0 pop {r4, r5, r6, r7} 80001d8: f001 01ff and.w r1, r1, #255 @ 0xff 80001dc: f002 0207 and.w r2, r2, #7 80001e0: b132 cbz r2, 80001f0 80001e2: f810 3b01 ldrb.w r3, [r0], #1 80001e6: 3a01 subs r2, #1 80001e8: ea83 0301 eor.w r3, r3, r1 80001ec: b113 cbz r3, 80001f4 80001ee: d1f8 bne.n 80001e2 80001f0: 2000 movs r0, #0 80001f2: 4770 bx lr 80001f4: 3801 subs r0, #1 80001f6: 4770 bx lr 80001f8: 2d00 cmp r5, #0 80001fa: bf06 itte eq 80001fc: 4635 moveq r5, r6 80001fe: 3803 subeq r0, #3 8000200: 3807 subne r0, #7 8000202: f015 0f01 tst.w r5, #1 8000206: d107 bne.n 8000218 8000208: 3001 adds r0, #1 800020a: f415 7f80 tst.w r5, #256 @ 0x100 800020e: bf02 ittt eq 8000210: 3001 addeq r0, #1 8000212: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000216: 3001 addeq r0, #1 8000218: bcf0 pop {r4, r5, r6, r7} 800021a: 3801 subs r0, #1 800021c: 4770 bx lr 800021e: bf00 nop 08000220 : 8000220: 4603 mov r3, r0 8000222: f813 2b01 ldrb.w r2, [r3], #1 8000226: 2a00 cmp r2, #0 8000228: d1fb bne.n 8000222 800022a: 1a18 subs r0, r3, r0 800022c: 3801 subs r0, #1 800022e: 4770 bx lr 08000230 <__aeabi_drsub>: 8000230: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 8000234: e002 b.n 800023c <__adddf3> 8000236: bf00 nop 08000238 <__aeabi_dsub>: 8000238: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 0800023c <__adddf3>: 800023c: b530 push {r4, r5, lr} 800023e: ea4f 0441 mov.w r4, r1, lsl #1 8000242: ea4f 0543 mov.w r5, r3, lsl #1 8000246: ea94 0f05 teq r4, r5 800024a: bf08 it eq 800024c: ea90 0f02 teqeq r0, r2 8000250: bf1f itttt ne 8000252: ea54 0c00 orrsne.w ip, r4, r0 8000256: ea55 0c02 orrsne.w ip, r5, r2 800025a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800025e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000262: f000 80e2 beq.w 800042a <__adddf3+0x1ee> 8000266: ea4f 5454 mov.w r4, r4, lsr #21 800026a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800026e: bfb8 it lt 8000270: 426d neglt r5, r5 8000272: dd0c ble.n 800028e <__adddf3+0x52> 8000274: 442c add r4, r5 8000276: ea80 0202 eor.w r2, r0, r2 800027a: ea81 0303 eor.w r3, r1, r3 800027e: ea82 0000 eor.w r0, r2, r0 8000282: ea83 0101 eor.w r1, r3, r1 8000286: ea80 0202 eor.w r2, r0, r2 800028a: ea81 0303 eor.w r3, r1, r3 800028e: 2d36 cmp r5, #54 @ 0x36 8000290: bf88 it hi 8000292: bd30 pophi {r4, r5, pc} 8000294: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8000298: ea4f 3101 mov.w r1, r1, lsl #12 800029c: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80002a0: ea4c 3111 orr.w r1, ip, r1, lsr #12 80002a4: d002 beq.n 80002ac <__adddf3+0x70> 80002a6: 4240 negs r0, r0 80002a8: eb61 0141 sbc.w r1, r1, r1, lsl #1 80002ac: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80002b0: ea4f 3303 mov.w r3, r3, lsl #12 80002b4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002b8: d002 beq.n 80002c0 <__adddf3+0x84> 80002ba: 4252 negs r2, r2 80002bc: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002c0: ea94 0f05 teq r4, r5 80002c4: f000 80a7 beq.w 8000416 <__adddf3+0x1da> 80002c8: f1a4 0401 sub.w r4, r4, #1 80002cc: f1d5 0e20 rsbs lr, r5, #32 80002d0: db0d blt.n 80002ee <__adddf3+0xb2> 80002d2: fa02 fc0e lsl.w ip, r2, lr 80002d6: fa22 f205 lsr.w r2, r2, r5 80002da: 1880 adds r0, r0, r2 80002dc: f141 0100 adc.w r1, r1, #0 80002e0: fa03 f20e lsl.w r2, r3, lr 80002e4: 1880 adds r0, r0, r2 80002e6: fa43 f305 asr.w r3, r3, r5 80002ea: 4159 adcs r1, r3 80002ec: e00e b.n 800030c <__adddf3+0xd0> 80002ee: f1a5 0520 sub.w r5, r5, #32 80002f2: f10e 0e20 add.w lr, lr, #32 80002f6: 2a01 cmp r2, #1 80002f8: fa03 fc0e lsl.w ip, r3, lr 80002fc: bf28 it cs 80002fe: f04c 0c02 orrcs.w ip, ip, #2 8000302: fa43 f305 asr.w r3, r3, r5 8000306: 18c0 adds r0, r0, r3 8000308: eb51 71e3 adcs.w r1, r1, r3, asr #31 800030c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000310: d507 bpl.n 8000322 <__adddf3+0xe6> 8000312: f04f 0e00 mov.w lr, #0 8000316: f1dc 0c00 rsbs ip, ip, #0 800031a: eb7e 0000 sbcs.w r0, lr, r0 800031e: eb6e 0101 sbc.w r1, lr, r1 8000322: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 8000326: d31b bcc.n 8000360 <__adddf3+0x124> 8000328: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 800032c: d30c bcc.n 8000348 <__adddf3+0x10c> 800032e: 0849 lsrs r1, r1, #1 8000330: ea5f 0030 movs.w r0, r0, rrx 8000334: ea4f 0c3c mov.w ip, ip, rrx 8000338: f104 0401 add.w r4, r4, #1 800033c: ea4f 5244 mov.w r2, r4, lsl #21 8000340: f512 0f80 cmn.w r2, #4194304 @ 0x400000 8000344: f080 809a bcs.w 800047c <__adddf3+0x240> 8000348: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 800034c: bf08 it eq 800034e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000352: f150 0000 adcs.w r0, r0, #0 8000356: eb41 5104 adc.w r1, r1, r4, lsl #20 800035a: ea41 0105 orr.w r1, r1, r5 800035e: bd30 pop {r4, r5, pc} 8000360: ea5f 0c4c movs.w ip, ip, lsl #1 8000364: 4140 adcs r0, r0 8000366: eb41 0101 adc.w r1, r1, r1 800036a: 3c01 subs r4, #1 800036c: bf28 it cs 800036e: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 8000372: d2e9 bcs.n 8000348 <__adddf3+0x10c> 8000374: f091 0f00 teq r1, #0 8000378: bf04 itt eq 800037a: 4601 moveq r1, r0 800037c: 2000 moveq r0, #0 800037e: fab1 f381 clz r3, r1 8000382: bf08 it eq 8000384: 3320 addeq r3, #32 8000386: f1a3 030b sub.w r3, r3, #11 800038a: f1b3 0220 subs.w r2, r3, #32 800038e: da0c bge.n 80003aa <__adddf3+0x16e> 8000390: 320c adds r2, #12 8000392: dd08 ble.n 80003a6 <__adddf3+0x16a> 8000394: f102 0c14 add.w ip, r2, #20 8000398: f1c2 020c rsb r2, r2, #12 800039c: fa01 f00c lsl.w r0, r1, ip 80003a0: fa21 f102 lsr.w r1, r1, r2 80003a4: e00c b.n 80003c0 <__adddf3+0x184> 80003a6: f102 0214 add.w r2, r2, #20 80003aa: bfd8 it le 80003ac: f1c2 0c20 rsble ip, r2, #32 80003b0: fa01 f102 lsl.w r1, r1, r2 80003b4: fa20 fc0c lsr.w ip, r0, ip 80003b8: bfdc itt le 80003ba: ea41 010c orrle.w r1, r1, ip 80003be: 4090 lslle r0, r2 80003c0: 1ae4 subs r4, r4, r3 80003c2: bfa2 ittt ge 80003c4: eb01 5104 addge.w r1, r1, r4, lsl #20 80003c8: 4329 orrge r1, r5 80003ca: bd30 popge {r4, r5, pc} 80003cc: ea6f 0404 mvn.w r4, r4 80003d0: 3c1f subs r4, #31 80003d2: da1c bge.n 800040e <__adddf3+0x1d2> 80003d4: 340c adds r4, #12 80003d6: dc0e bgt.n 80003f6 <__adddf3+0x1ba> 80003d8: f104 0414 add.w r4, r4, #20 80003dc: f1c4 0220 rsb r2, r4, #32 80003e0: fa20 f004 lsr.w r0, r0, r4 80003e4: fa01 f302 lsl.w r3, r1, r2 80003e8: ea40 0003 orr.w r0, r0, r3 80003ec: fa21 f304 lsr.w r3, r1, r4 80003f0: ea45 0103 orr.w r1, r5, r3 80003f4: bd30 pop {r4, r5, pc} 80003f6: f1c4 040c rsb r4, r4, #12 80003fa: f1c4 0220 rsb r2, r4, #32 80003fe: fa20 f002 lsr.w r0, r0, r2 8000402: fa01 f304 lsl.w r3, r1, r4 8000406: ea40 0003 orr.w r0, r0, r3 800040a: 4629 mov r1, r5 800040c: bd30 pop {r4, r5, pc} 800040e: fa21 f004 lsr.w r0, r1, r4 8000412: 4629 mov r1, r5 8000414: bd30 pop {r4, r5, pc} 8000416: f094 0f00 teq r4, #0 800041a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 800041e: bf06 itte eq 8000420: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 8000424: 3401 addeq r4, #1 8000426: 3d01 subne r5, #1 8000428: e74e b.n 80002c8 <__adddf3+0x8c> 800042a: ea7f 5c64 mvns.w ip, r4, asr #21 800042e: bf18 it ne 8000430: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000434: d029 beq.n 800048a <__adddf3+0x24e> 8000436: ea94 0f05 teq r4, r5 800043a: bf08 it eq 800043c: ea90 0f02 teqeq r0, r2 8000440: d005 beq.n 800044e <__adddf3+0x212> 8000442: ea54 0c00 orrs.w ip, r4, r0 8000446: bf04 itt eq 8000448: 4619 moveq r1, r3 800044a: 4610 moveq r0, r2 800044c: bd30 pop {r4, r5, pc} 800044e: ea91 0f03 teq r1, r3 8000452: bf1e ittt ne 8000454: 2100 movne r1, #0 8000456: 2000 movne r0, #0 8000458: bd30 popne {r4, r5, pc} 800045a: ea5f 5c54 movs.w ip, r4, lsr #21 800045e: d105 bne.n 800046c <__adddf3+0x230> 8000460: 0040 lsls r0, r0, #1 8000462: 4149 adcs r1, r1 8000464: bf28 it cs 8000466: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 800046a: bd30 pop {r4, r5, pc} 800046c: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8000470: bf3c itt cc 8000472: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 8000476: bd30 popcc {r4, r5, pc} 8000478: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800047c: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8000480: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8000484: f04f 0000 mov.w r0, #0 8000488: bd30 pop {r4, r5, pc} 800048a: ea7f 5c64 mvns.w ip, r4, asr #21 800048e: bf1a itte ne 8000490: 4619 movne r1, r3 8000492: 4610 movne r0, r2 8000494: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000498: bf1c itt ne 800049a: 460b movne r3, r1 800049c: 4602 movne r2, r0 800049e: ea50 3401 orrs.w r4, r0, r1, lsl #12 80004a2: bf06 itte eq 80004a4: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80004a8: ea91 0f03 teqeq r1, r3 80004ac: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80004b0: bd30 pop {r4, r5, pc} 80004b2: bf00 nop 080004b4 <__aeabi_ui2d>: 80004b4: f090 0f00 teq r0, #0 80004b8: bf04 itt eq 80004ba: 2100 moveq r1, #0 80004bc: 4770 bxeq lr 80004be: b530 push {r4, r5, lr} 80004c0: f44f 6480 mov.w r4, #1024 @ 0x400 80004c4: f104 0432 add.w r4, r4, #50 @ 0x32 80004c8: f04f 0500 mov.w r5, #0 80004cc: f04f 0100 mov.w r1, #0 80004d0: e750 b.n 8000374 <__adddf3+0x138> 80004d2: bf00 nop 080004d4 <__aeabi_i2d>: 80004d4: f090 0f00 teq r0, #0 80004d8: bf04 itt eq 80004da: 2100 moveq r1, #0 80004dc: 4770 bxeq lr 80004de: b530 push {r4, r5, lr} 80004e0: f44f 6480 mov.w r4, #1024 @ 0x400 80004e4: f104 0432 add.w r4, r4, #50 @ 0x32 80004e8: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80004ec: bf48 it mi 80004ee: 4240 negmi r0, r0 80004f0: f04f 0100 mov.w r1, #0 80004f4: e73e b.n 8000374 <__adddf3+0x138> 80004f6: bf00 nop 080004f8 <__aeabi_f2d>: 80004f8: 0042 lsls r2, r0, #1 80004fa: ea4f 01e2 mov.w r1, r2, asr #3 80004fe: ea4f 0131 mov.w r1, r1, rrx 8000502: ea4f 7002 mov.w r0, r2, lsl #28 8000506: bf1f itttt ne 8000508: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 800050c: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8000510: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 8000514: 4770 bxne lr 8000516: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 800051a: bf08 it eq 800051c: 4770 bxeq lr 800051e: f093 4f7f teq r3, #4278190080 @ 0xff000000 8000522: bf04 itt eq 8000524: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8000528: 4770 bxeq lr 800052a: b530 push {r4, r5, lr} 800052c: f44f 7460 mov.w r4, #896 @ 0x380 8000530: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000534: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8000538: e71c b.n 8000374 <__adddf3+0x138> 800053a: bf00 nop 0800053c <__aeabi_ul2d>: 800053c: ea50 0201 orrs.w r2, r0, r1 8000540: bf08 it eq 8000542: 4770 bxeq lr 8000544: b530 push {r4, r5, lr} 8000546: f04f 0500 mov.w r5, #0 800054a: e00a b.n 8000562 <__aeabi_l2d+0x16> 0800054c <__aeabi_l2d>: 800054c: ea50 0201 orrs.w r2, r0, r1 8000550: bf08 it eq 8000552: 4770 bxeq lr 8000554: b530 push {r4, r5, lr} 8000556: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 800055a: d502 bpl.n 8000562 <__aeabi_l2d+0x16> 800055c: 4240 negs r0, r0 800055e: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000562: f44f 6480 mov.w r4, #1024 @ 0x400 8000566: f104 0432 add.w r4, r4, #50 @ 0x32 800056a: ea5f 5c91 movs.w ip, r1, lsr #22 800056e: f43f aed8 beq.w 8000322 <__adddf3+0xe6> 8000572: f04f 0203 mov.w r2, #3 8000576: ea5f 0cdc movs.w ip, ip, lsr #3 800057a: bf18 it ne 800057c: 3203 addne r2, #3 800057e: ea5f 0cdc movs.w ip, ip, lsr #3 8000582: bf18 it ne 8000584: 3203 addne r2, #3 8000586: eb02 02dc add.w r2, r2, ip, lsr #3 800058a: f1c2 0320 rsb r3, r2, #32 800058e: fa00 fc03 lsl.w ip, r0, r3 8000592: fa20 f002 lsr.w r0, r0, r2 8000596: fa01 fe03 lsl.w lr, r1, r3 800059a: ea40 000e orr.w r0, r0, lr 800059e: fa21 f102 lsr.w r1, r1, r2 80005a2: 4414 add r4, r2 80005a4: e6bd b.n 8000322 <__adddf3+0xe6> 80005a6: bf00 nop 080005a8 <__aeabi_dmul>: 80005a8: b570 push {r4, r5, r6, lr} 80005aa: f04f 0cff mov.w ip, #255 @ 0xff 80005ae: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80005b2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80005b6: bf1d ittte ne 80005b8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005bc: ea94 0f0c teqne r4, ip 80005c0: ea95 0f0c teqne r5, ip 80005c4: f000 f8de bleq 8000784 <__aeabi_dmul+0x1dc> 80005c8: 442c add r4, r5 80005ca: ea81 0603 eor.w r6, r1, r3 80005ce: ea21 514c bic.w r1, r1, ip, lsl #21 80005d2: ea23 534c bic.w r3, r3, ip, lsl #21 80005d6: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005da: bf18 it ne 80005dc: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005e0: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80005e4: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80005e8: d038 beq.n 800065c <__aeabi_dmul+0xb4> 80005ea: fba0 ce02 umull ip, lr, r0, r2 80005ee: f04f 0500 mov.w r5, #0 80005f2: fbe1 e502 umlal lr, r5, r1, r2 80005f6: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 80005fa: fbe0 e503 umlal lr, r5, r0, r3 80005fe: f04f 0600 mov.w r6, #0 8000602: fbe1 5603 umlal r5, r6, r1, r3 8000606: f09c 0f00 teq ip, #0 800060a: bf18 it ne 800060c: f04e 0e01 orrne.w lr, lr, #1 8000610: f1a4 04ff sub.w r4, r4, #255 @ 0xff 8000614: f5b6 7f00 cmp.w r6, #512 @ 0x200 8000618: f564 7440 sbc.w r4, r4, #768 @ 0x300 800061c: d204 bcs.n 8000628 <__aeabi_dmul+0x80> 800061e: ea5f 0e4e movs.w lr, lr, lsl #1 8000622: 416d adcs r5, r5 8000624: eb46 0606 adc.w r6, r6, r6 8000628: ea42 21c6 orr.w r1, r2, r6, lsl #11 800062c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000630: ea4f 20c5 mov.w r0, r5, lsl #11 8000634: ea40 505e orr.w r0, r0, lr, lsr #21 8000638: ea4f 2ece mov.w lr, lr, lsl #11 800063c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8000640: bf88 it hi 8000642: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 8000646: d81e bhi.n 8000686 <__aeabi_dmul+0xde> 8000648: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 800064c: bf08 it eq 800064e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000652: f150 0000 adcs.w r0, r0, #0 8000656: eb41 5104 adc.w r1, r1, r4, lsl #20 800065a: bd70 pop {r4, r5, r6, pc} 800065c: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8000660: ea46 0101 orr.w r1, r6, r1 8000664: ea40 0002 orr.w r0, r0, r2 8000668: ea81 0103 eor.w r1, r1, r3 800066c: ebb4 045c subs.w r4, r4, ip, lsr #1 8000670: bfc2 ittt gt 8000672: ebd4 050c rsbsgt r5, r4, ip 8000676: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800067a: bd70 popgt {r4, r5, r6, pc} 800067c: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000680: f04f 0e00 mov.w lr, #0 8000684: 3c01 subs r4, #1 8000686: f300 80ab bgt.w 80007e0 <__aeabi_dmul+0x238> 800068a: f114 0f36 cmn.w r4, #54 @ 0x36 800068e: bfde ittt le 8000690: 2000 movle r0, #0 8000692: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 8000696: bd70 pople {r4, r5, r6, pc} 8000698: f1c4 0400 rsb r4, r4, #0 800069c: 3c20 subs r4, #32 800069e: da35 bge.n 800070c <__aeabi_dmul+0x164> 80006a0: 340c adds r4, #12 80006a2: dc1b bgt.n 80006dc <__aeabi_dmul+0x134> 80006a4: f104 0414 add.w r4, r4, #20 80006a8: f1c4 0520 rsb r5, r4, #32 80006ac: fa00 f305 lsl.w r3, r0, r5 80006b0: fa20 f004 lsr.w r0, r0, r4 80006b4: fa01 f205 lsl.w r2, r1, r5 80006b8: ea40 0002 orr.w r0, r0, r2 80006bc: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80006c0: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80006c4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006c8: fa21 f604 lsr.w r6, r1, r4 80006cc: eb42 0106 adc.w r1, r2, r6 80006d0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006d4: bf08 it eq 80006d6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006da: bd70 pop {r4, r5, r6, pc} 80006dc: f1c4 040c rsb r4, r4, #12 80006e0: f1c4 0520 rsb r5, r4, #32 80006e4: fa00 f304 lsl.w r3, r0, r4 80006e8: fa20 f005 lsr.w r0, r0, r5 80006ec: fa01 f204 lsl.w r2, r1, r4 80006f0: ea40 0002 orr.w r0, r0, r2 80006f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80006f8: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006fc: f141 0100 adc.w r1, r1, #0 8000700: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000704: bf08 it eq 8000706: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800070a: bd70 pop {r4, r5, r6, pc} 800070c: f1c4 0520 rsb r5, r4, #32 8000710: fa00 f205 lsl.w r2, r0, r5 8000714: ea4e 0e02 orr.w lr, lr, r2 8000718: fa20 f304 lsr.w r3, r0, r4 800071c: fa01 f205 lsl.w r2, r1, r5 8000720: ea43 0302 orr.w r3, r3, r2 8000724: fa21 f004 lsr.w r0, r1, r4 8000728: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 800072c: fa21 f204 lsr.w r2, r1, r4 8000730: ea20 0002 bic.w r0, r0, r2 8000734: eb00 70d3 add.w r0, r0, r3, lsr #31 8000738: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800073c: bf08 it eq 800073e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000742: bd70 pop {r4, r5, r6, pc} 8000744: f094 0f00 teq r4, #0 8000748: d10f bne.n 800076a <__aeabi_dmul+0x1c2> 800074a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 800074e: 0040 lsls r0, r0, #1 8000750: eb41 0101 adc.w r1, r1, r1 8000754: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000758: bf08 it eq 800075a: 3c01 subeq r4, #1 800075c: d0f7 beq.n 800074e <__aeabi_dmul+0x1a6> 800075e: ea41 0106 orr.w r1, r1, r6 8000762: f095 0f00 teq r5, #0 8000766: bf18 it ne 8000768: 4770 bxne lr 800076a: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 800076e: 0052 lsls r2, r2, #1 8000770: eb43 0303 adc.w r3, r3, r3 8000774: f413 1f80 tst.w r3, #1048576 @ 0x100000 8000778: bf08 it eq 800077a: 3d01 subeq r5, #1 800077c: d0f7 beq.n 800076e <__aeabi_dmul+0x1c6> 800077e: ea43 0306 orr.w r3, r3, r6 8000782: 4770 bx lr 8000784: ea94 0f0c teq r4, ip 8000788: ea0c 5513 and.w r5, ip, r3, lsr #20 800078c: bf18 it ne 800078e: ea95 0f0c teqne r5, ip 8000792: d00c beq.n 80007ae <__aeabi_dmul+0x206> 8000794: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000798: bf18 it ne 800079a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 800079e: d1d1 bne.n 8000744 <__aeabi_dmul+0x19c> 80007a0: ea81 0103 eor.w r1, r1, r3 80007a4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80007a8: f04f 0000 mov.w r0, #0 80007ac: bd70 pop {r4, r5, r6, pc} 80007ae: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007b2: bf06 itte eq 80007b4: 4610 moveq r0, r2 80007b6: 4619 moveq r1, r3 80007b8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007bc: d019 beq.n 80007f2 <__aeabi_dmul+0x24a> 80007be: ea94 0f0c teq r4, ip 80007c2: d102 bne.n 80007ca <__aeabi_dmul+0x222> 80007c4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007c8: d113 bne.n 80007f2 <__aeabi_dmul+0x24a> 80007ca: ea95 0f0c teq r5, ip 80007ce: d105 bne.n 80007dc <__aeabi_dmul+0x234> 80007d0: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007d4: bf1c itt ne 80007d6: 4610 movne r0, r2 80007d8: 4619 movne r1, r3 80007da: d10a bne.n 80007f2 <__aeabi_dmul+0x24a> 80007dc: ea81 0103 eor.w r1, r1, r3 80007e0: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80007e4: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80007e8: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80007ec: f04f 0000 mov.w r0, #0 80007f0: bd70 pop {r4, r5, r6, pc} 80007f2: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80007f6: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 80007fa: bd70 pop {r4, r5, r6, pc} 080007fc <__aeabi_ddiv>: 80007fc: b570 push {r4, r5, r6, lr} 80007fe: f04f 0cff mov.w ip, #255 @ 0xff 8000802: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 8000806: ea1c 5411 ands.w r4, ip, r1, lsr #20 800080a: bf1d ittte ne 800080c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000810: ea94 0f0c teqne r4, ip 8000814: ea95 0f0c teqne r5, ip 8000818: f000 f8a7 bleq 800096a <__aeabi_ddiv+0x16e> 800081c: eba4 0405 sub.w r4, r4, r5 8000820: ea81 0e03 eor.w lr, r1, r3 8000824: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000828: ea4f 3101 mov.w r1, r1, lsl #12 800082c: f000 8088 beq.w 8000940 <__aeabi_ddiv+0x144> 8000830: ea4f 3303 mov.w r3, r3, lsl #12 8000834: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8000838: ea45 1313 orr.w r3, r5, r3, lsr #4 800083c: ea43 6312 orr.w r3, r3, r2, lsr #24 8000840: ea4f 2202 mov.w r2, r2, lsl #8 8000844: ea45 1511 orr.w r5, r5, r1, lsr #4 8000848: ea45 6510 orr.w r5, r5, r0, lsr #24 800084c: ea4f 2600 mov.w r6, r0, lsl #8 8000850: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 8000854: 429d cmp r5, r3 8000856: bf08 it eq 8000858: 4296 cmpeq r6, r2 800085a: f144 04fd adc.w r4, r4, #253 @ 0xfd 800085e: f504 7440 add.w r4, r4, #768 @ 0x300 8000862: d202 bcs.n 800086a <__aeabi_ddiv+0x6e> 8000864: 085b lsrs r3, r3, #1 8000866: ea4f 0232 mov.w r2, r2, rrx 800086a: 1ab6 subs r6, r6, r2 800086c: eb65 0503 sbc.w r5, r5, r3 8000870: 085b lsrs r3, r3, #1 8000872: ea4f 0232 mov.w r2, r2, rrx 8000876: f44f 1080 mov.w r0, #1048576 @ 0x100000 800087a: f44f 2c00 mov.w ip, #524288 @ 0x80000 800087e: ebb6 0e02 subs.w lr, r6, r2 8000882: eb75 0e03 sbcs.w lr, r5, r3 8000886: bf22 ittt cs 8000888: 1ab6 subcs r6, r6, r2 800088a: 4675 movcs r5, lr 800088c: ea40 000c orrcs.w r0, r0, ip 8000890: 085b lsrs r3, r3, #1 8000892: ea4f 0232 mov.w r2, r2, rrx 8000896: ebb6 0e02 subs.w lr, r6, r2 800089a: eb75 0e03 sbcs.w lr, r5, r3 800089e: bf22 ittt cs 80008a0: 1ab6 subcs r6, r6, r2 80008a2: 4675 movcs r5, lr 80008a4: ea40 005c orrcs.w r0, r0, ip, lsr #1 80008a8: 085b lsrs r3, r3, #1 80008aa: ea4f 0232 mov.w r2, r2, rrx 80008ae: ebb6 0e02 subs.w lr, r6, r2 80008b2: eb75 0e03 sbcs.w lr, r5, r3 80008b6: bf22 ittt cs 80008b8: 1ab6 subcs r6, r6, r2 80008ba: 4675 movcs r5, lr 80008bc: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008c0: 085b lsrs r3, r3, #1 80008c2: ea4f 0232 mov.w r2, r2, rrx 80008c6: ebb6 0e02 subs.w lr, r6, r2 80008ca: eb75 0e03 sbcs.w lr, r5, r3 80008ce: bf22 ittt cs 80008d0: 1ab6 subcs r6, r6, r2 80008d2: 4675 movcs r5, lr 80008d4: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008d8: ea55 0e06 orrs.w lr, r5, r6 80008dc: d018 beq.n 8000910 <__aeabi_ddiv+0x114> 80008de: ea4f 1505 mov.w r5, r5, lsl #4 80008e2: ea45 7516 orr.w r5, r5, r6, lsr #28 80008e6: ea4f 1606 mov.w r6, r6, lsl #4 80008ea: ea4f 03c3 mov.w r3, r3, lsl #3 80008ee: ea43 7352 orr.w r3, r3, r2, lsr #29 80008f2: ea4f 02c2 mov.w r2, r2, lsl #3 80008f6: ea5f 1c1c movs.w ip, ip, lsr #4 80008fa: d1c0 bne.n 800087e <__aeabi_ddiv+0x82> 80008fc: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000900: d10b bne.n 800091a <__aeabi_ddiv+0x11e> 8000902: ea41 0100 orr.w r1, r1, r0 8000906: f04f 0000 mov.w r0, #0 800090a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 800090e: e7b6 b.n 800087e <__aeabi_ddiv+0x82> 8000910: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000914: bf04 itt eq 8000916: 4301 orreq r1, r0 8000918: 2000 moveq r0, #0 800091a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 800091e: bf88 it hi 8000920: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 8000924: f63f aeaf bhi.w 8000686 <__aeabi_dmul+0xde> 8000928: ebb5 0c03 subs.w ip, r5, r3 800092c: bf04 itt eq 800092e: ebb6 0c02 subseq.w ip, r6, r2 8000932: ea5f 0c50 movseq.w ip, r0, lsr #1 8000936: f150 0000 adcs.w r0, r0, #0 800093a: eb41 5104 adc.w r1, r1, r4, lsl #20 800093e: bd70 pop {r4, r5, r6, pc} 8000940: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 8000944: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000948: eb14 045c adds.w r4, r4, ip, lsr #1 800094c: bfc2 ittt gt 800094e: ebd4 050c rsbsgt r5, r4, ip 8000952: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000956: bd70 popgt {r4, r5, r6, pc} 8000958: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 800095c: f04f 0e00 mov.w lr, #0 8000960: 3c01 subs r4, #1 8000962: e690 b.n 8000686 <__aeabi_dmul+0xde> 8000964: ea45 0e06 orr.w lr, r5, r6 8000968: e68d b.n 8000686 <__aeabi_dmul+0xde> 800096a: ea0c 5513 and.w r5, ip, r3, lsr #20 800096e: ea94 0f0c teq r4, ip 8000972: bf08 it eq 8000974: ea95 0f0c teqeq r5, ip 8000978: f43f af3b beq.w 80007f2 <__aeabi_dmul+0x24a> 800097c: ea94 0f0c teq r4, ip 8000980: d10a bne.n 8000998 <__aeabi_ddiv+0x19c> 8000982: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000986: f47f af34 bne.w 80007f2 <__aeabi_dmul+0x24a> 800098a: ea95 0f0c teq r5, ip 800098e: f47f af25 bne.w 80007dc <__aeabi_dmul+0x234> 8000992: 4610 mov r0, r2 8000994: 4619 mov r1, r3 8000996: e72c b.n 80007f2 <__aeabi_dmul+0x24a> 8000998: ea95 0f0c teq r5, ip 800099c: d106 bne.n 80009ac <__aeabi_ddiv+0x1b0> 800099e: ea52 3503 orrs.w r5, r2, r3, lsl #12 80009a2: f43f aefd beq.w 80007a0 <__aeabi_dmul+0x1f8> 80009a6: 4610 mov r0, r2 80009a8: 4619 mov r1, r3 80009aa: e722 b.n 80007f2 <__aeabi_dmul+0x24a> 80009ac: ea50 0641 orrs.w r6, r0, r1, lsl #1 80009b0: bf18 it ne 80009b2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80009b6: f47f aec5 bne.w 8000744 <__aeabi_dmul+0x19c> 80009ba: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009be: f47f af0d bne.w 80007dc <__aeabi_dmul+0x234> 80009c2: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009c6: f47f aeeb bne.w 80007a0 <__aeabi_dmul+0x1f8> 80009ca: e712 b.n 80007f2 <__aeabi_dmul+0x24a> 080009cc <__gedf2>: 80009cc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80009d0: e006 b.n 80009e0 <__cmpdf2+0x4> 80009d2: bf00 nop 080009d4 <__ledf2>: 80009d4: f04f 0c01 mov.w ip, #1 80009d8: e002 b.n 80009e0 <__cmpdf2+0x4> 80009da: bf00 nop 080009dc <__cmpdf2>: 80009dc: f04f 0c01 mov.w ip, #1 80009e0: f84d cd04 str.w ip, [sp, #-4]! 80009e4: ea4f 0c41 mov.w ip, r1, lsl #1 80009e8: ea7f 5c6c mvns.w ip, ip, asr #21 80009ec: ea4f 0c43 mov.w ip, r3, lsl #1 80009f0: bf18 it ne 80009f2: ea7f 5c6c mvnsne.w ip, ip, asr #21 80009f6: d01b beq.n 8000a30 <__cmpdf2+0x54> 80009f8: b001 add sp, #4 80009fa: ea50 0c41 orrs.w ip, r0, r1, lsl #1 80009fe: bf0c ite eq 8000a00: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8000a04: ea91 0f03 teqne r1, r3 8000a08: bf02 ittt eq 8000a0a: ea90 0f02 teqeq r0, r2 8000a0e: 2000 moveq r0, #0 8000a10: 4770 bxeq lr 8000a12: f110 0f00 cmn.w r0, #0 8000a16: ea91 0f03 teq r1, r3 8000a1a: bf58 it pl 8000a1c: 4299 cmppl r1, r3 8000a1e: bf08 it eq 8000a20: 4290 cmpeq r0, r2 8000a22: bf2c ite cs 8000a24: 17d8 asrcs r0, r3, #31 8000a26: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a2a: f040 0001 orr.w r0, r0, #1 8000a2e: 4770 bx lr 8000a30: ea4f 0c41 mov.w ip, r1, lsl #1 8000a34: ea7f 5c6c mvns.w ip, ip, asr #21 8000a38: d102 bne.n 8000a40 <__cmpdf2+0x64> 8000a3a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a3e: d107 bne.n 8000a50 <__cmpdf2+0x74> 8000a40: ea4f 0c43 mov.w ip, r3, lsl #1 8000a44: ea7f 5c6c mvns.w ip, ip, asr #21 8000a48: d1d6 bne.n 80009f8 <__cmpdf2+0x1c> 8000a4a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a4e: d0d3 beq.n 80009f8 <__cmpdf2+0x1c> 8000a50: f85d 0b04 ldr.w r0, [sp], #4 8000a54: 4770 bx lr 8000a56: bf00 nop 08000a58 <__aeabi_cdrcmple>: 8000a58: 4684 mov ip, r0 8000a5a: 4610 mov r0, r2 8000a5c: 4662 mov r2, ip 8000a5e: 468c mov ip, r1 8000a60: 4619 mov r1, r3 8000a62: 4663 mov r3, ip 8000a64: e000 b.n 8000a68 <__aeabi_cdcmpeq> 8000a66: bf00 nop 08000a68 <__aeabi_cdcmpeq>: 8000a68: b501 push {r0, lr} 8000a6a: f7ff ffb7 bl 80009dc <__cmpdf2> 8000a6e: 2800 cmp r0, #0 8000a70: bf48 it mi 8000a72: f110 0f00 cmnmi.w r0, #0 8000a76: bd01 pop {r0, pc} 08000a78 <__aeabi_dcmpeq>: 8000a78: f84d ed08 str.w lr, [sp, #-8]! 8000a7c: f7ff fff4 bl 8000a68 <__aeabi_cdcmpeq> 8000a80: bf0c ite eq 8000a82: 2001 moveq r0, #1 8000a84: 2000 movne r0, #0 8000a86: f85d fb08 ldr.w pc, [sp], #8 8000a8a: bf00 nop 08000a8c <__aeabi_dcmplt>: 8000a8c: f84d ed08 str.w lr, [sp, #-8]! 8000a90: f7ff ffea bl 8000a68 <__aeabi_cdcmpeq> 8000a94: bf34 ite cc 8000a96: 2001 movcc r0, #1 8000a98: 2000 movcs r0, #0 8000a9a: f85d fb08 ldr.w pc, [sp], #8 8000a9e: bf00 nop 08000aa0 <__aeabi_dcmple>: 8000aa0: f84d ed08 str.w lr, [sp, #-8]! 8000aa4: f7ff ffe0 bl 8000a68 <__aeabi_cdcmpeq> 8000aa8: bf94 ite ls 8000aaa: 2001 movls r0, #1 8000aac: 2000 movhi r0, #0 8000aae: f85d fb08 ldr.w pc, [sp], #8 8000ab2: bf00 nop 08000ab4 <__aeabi_dcmpge>: 8000ab4: f84d ed08 str.w lr, [sp, #-8]! 8000ab8: f7ff ffce bl 8000a58 <__aeabi_cdrcmple> 8000abc: bf94 ite ls 8000abe: 2001 movls r0, #1 8000ac0: 2000 movhi r0, #0 8000ac2: f85d fb08 ldr.w pc, [sp], #8 8000ac6: bf00 nop 08000ac8 <__aeabi_dcmpgt>: 8000ac8: f84d ed08 str.w lr, [sp, #-8]! 8000acc: f7ff ffc4 bl 8000a58 <__aeabi_cdrcmple> 8000ad0: bf34 ite cc 8000ad2: 2001 movcc r0, #1 8000ad4: 2000 movcs r0, #0 8000ad6: f85d fb08 ldr.w pc, [sp], #8 8000ada: bf00 nop 08000adc <__aeabi_dcmpun>: 8000adc: ea4f 0c41 mov.w ip, r1, lsl #1 8000ae0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ae4: d102 bne.n 8000aec <__aeabi_dcmpun+0x10> 8000ae6: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000aea: d10a bne.n 8000b02 <__aeabi_dcmpun+0x26> 8000aec: ea4f 0c43 mov.w ip, r3, lsl #1 8000af0: ea7f 5c6c mvns.w ip, ip, asr #21 8000af4: d102 bne.n 8000afc <__aeabi_dcmpun+0x20> 8000af6: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000afa: d102 bne.n 8000b02 <__aeabi_dcmpun+0x26> 8000afc: f04f 0000 mov.w r0, #0 8000b00: 4770 bx lr 8000b02: f04f 0001 mov.w r0, #1 8000b06: 4770 bx lr 08000b08 <__aeabi_d2iz>: 8000b08: ea4f 0241 mov.w r2, r1, lsl #1 8000b0c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8000b10: d215 bcs.n 8000b3e <__aeabi_d2iz+0x36> 8000b12: d511 bpl.n 8000b38 <__aeabi_d2iz+0x30> 8000b14: f46f 7378 mvn.w r3, #992 @ 0x3e0 8000b18: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b1c: d912 bls.n 8000b44 <__aeabi_d2iz+0x3c> 8000b1e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b22: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8000b26: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b2a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8000b2e: fa23 f002 lsr.w r0, r3, r2 8000b32: bf18 it ne 8000b34: 4240 negne r0, r0 8000b36: 4770 bx lr 8000b38: f04f 0000 mov.w r0, #0 8000b3c: 4770 bx lr 8000b3e: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b42: d105 bne.n 8000b50 <__aeabi_d2iz+0x48> 8000b44: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8000b48: bf08 it eq 8000b4a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8000b4e: 4770 bx lr 8000b50: f04f 0000 mov.w r0, #0 8000b54: 4770 bx lr 8000b56: bf00 nop 08000b58 <__aeabi_d2uiz>: 8000b58: 004a lsls r2, r1, #1 8000b5a: d211 bcs.n 8000b80 <__aeabi_d2uiz+0x28> 8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8000b60: d211 bcs.n 8000b86 <__aeabi_d2uiz+0x2e> 8000b62: d50d bpl.n 8000b80 <__aeabi_d2uiz+0x28> 8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0 8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b6c: d40e bmi.n 8000b8c <__aeabi_d2uiz+0x34> 8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b7a: fa23 f002 lsr.w r0, r3, r2 8000b7e: 4770 bx lr 8000b80: f04f 0000 mov.w r0, #0 8000b84: 4770 bx lr 8000b86: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b8a: d102 bne.n 8000b92 <__aeabi_d2uiz+0x3a> 8000b8c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8000b90: 4770 bx lr 8000b92: f04f 0000 mov.w r0, #0 8000b96: 4770 bx lr 08000b98 <__aeabi_d2f>: 8000b98: ea4f 0241 mov.w r2, r1, lsl #1 8000b9c: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8000ba0: bf24 itt cs 8000ba2: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8000ba6: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8000baa: d90d bls.n 8000bc8 <__aeabi_d2f+0x30> 8000bac: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8000bb0: ea4f 02c0 mov.w r2, r0, lsl #3 8000bb4: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000bb8: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8000bbc: eb40 0083 adc.w r0, r0, r3, lsl #2 8000bc0: bf08 it eq 8000bc2: f020 0001 biceq.w r0, r0, #1 8000bc6: 4770 bx lr 8000bc8: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8000bcc: d121 bne.n 8000c12 <__aeabi_d2f+0x7a> 8000bce: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8000bd2: bfbc itt lt 8000bd4: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8000bd8: 4770 bxlt lr 8000bda: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000bde: ea4f 5252 mov.w r2, r2, lsr #21 8000be2: f1c2 0218 rsb r2, r2, #24 8000be6: f1c2 0c20 rsb ip, r2, #32 8000bea: fa10 f30c lsls.w r3, r0, ip 8000bee: fa20 f002 lsr.w r0, r0, r2 8000bf2: bf18 it ne 8000bf4: f040 0001 orrne.w r0, r0, #1 8000bf8: ea4f 23c1 mov.w r3, r1, lsl #11 8000bfc: ea4f 23d3 mov.w r3, r3, lsr #11 8000c00: fa03 fc0c lsl.w ip, r3, ip 8000c04: ea40 000c orr.w r0, r0, ip 8000c08: fa23 f302 lsr.w r3, r3, r2 8000c0c: ea4f 0343 mov.w r3, r3, lsl #1 8000c10: e7cc b.n 8000bac <__aeabi_d2f+0x14> 8000c12: ea7f 5362 mvns.w r3, r2, asr #21 8000c16: d107 bne.n 8000c28 <__aeabi_d2f+0x90> 8000c18: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000c1c: bf1e ittt ne 8000c1e: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8000c22: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8000c26: 4770 bxne lr 8000c28: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8000c2c: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8000c30: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000c34: 4770 bx lr 8000c36: bf00 nop 08000c38 <__aeabi_d2lz>: 8000c38: b538 push {r3, r4, r5, lr} 8000c3a: 2200 movs r2, #0 8000c3c: 2300 movs r3, #0 8000c3e: 4604 mov r4, r0 8000c40: 460d mov r5, r1 8000c42: f7ff ff23 bl 8000a8c <__aeabi_dcmplt> 8000c46: b928 cbnz r0, 8000c54 <__aeabi_d2lz+0x1c> 8000c48: 4620 mov r0, r4 8000c4a: 4629 mov r1, r5 8000c4c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8000c50: f000 b80a b.w 8000c68 <__aeabi_d2ulz> 8000c54: 4620 mov r0, r4 8000c56: f105 4100 add.w r1, r5, #2147483648 @ 0x80000000 8000c5a: f000 f805 bl 8000c68 <__aeabi_d2ulz> 8000c5e: 4240 negs r0, r0 8000c60: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000c64: bd38 pop {r3, r4, r5, pc} 8000c66: bf00 nop 08000c68 <__aeabi_d2ulz>: 8000c68: b5d0 push {r4, r6, r7, lr} 8000c6a: 4b0c ldr r3, [pc, #48] @ (8000c9c <__aeabi_d2ulz+0x34>) 8000c6c: 2200 movs r2, #0 8000c6e: 4606 mov r6, r0 8000c70: 460f mov r7, r1 8000c72: f7ff fc99 bl 80005a8 <__aeabi_dmul> 8000c76: f7ff ff6f bl 8000b58 <__aeabi_d2uiz> 8000c7a: 4604 mov r4, r0 8000c7c: f7ff fc1a bl 80004b4 <__aeabi_ui2d> 8000c80: 4b07 ldr r3, [pc, #28] @ (8000ca0 <__aeabi_d2ulz+0x38>) 8000c82: 2200 movs r2, #0 8000c84: f7ff fc90 bl 80005a8 <__aeabi_dmul> 8000c88: 4602 mov r2, r0 8000c8a: 460b mov r3, r1 8000c8c: 4630 mov r0, r6 8000c8e: 4639 mov r1, r7 8000c90: f7ff fad2 bl 8000238 <__aeabi_dsub> 8000c94: f7ff ff60 bl 8000b58 <__aeabi_d2uiz> 8000c98: 4621 mov r1, r4 8000c9a: bdd0 pop {r4, r6, r7, pc} 8000c9c: 3df00000 .word 0x3df00000 8000ca0: 41f00000 .word 0x41f00000 08000ca4 : float invSqrt(float x); //==================================================================================================== // Functions void MadgwickAHRS_init (MadgwickAHRS_Filter* filter, float beta, float sample_freq) { 8000ca4: b480 push {r7} 8000ca6: b085 sub sp, #20 8000ca8: af00 add r7, sp, #0 8000caa: 60f8 str r0, [r7, #12] 8000cac: ed87 0a02 vstr s0, [r7, #8] 8000cb0: edc7 0a01 vstr s1, [r7, #4] filter->q[0] = 1.0f; // qw 8000cb4: 68fb ldr r3, [r7, #12] 8000cb6: f04f 527e mov.w r2, #1065353216 @ 0x3f800000 8000cba: 601a str r2, [r3, #0] filter->q[1] = 0.0f; // qx 8000cbc: 68fb ldr r3, [r7, #12] 8000cbe: f04f 0200 mov.w r2, #0 8000cc2: 605a str r2, [r3, #4] filter->q[2] = 0.0f; // qy 8000cc4: 68fb ldr r3, [r7, #12] 8000cc6: f04f 0200 mov.w r2, #0 8000cca: 609a str r2, [r3, #8] filter->q[3] = 0.0f; // qz 8000ccc: 68fb ldr r3, [r7, #12] 8000cce: f04f 0200 mov.w r2, #0 8000cd2: 60da str r2, [r3, #12] filter->beta = beta; 8000cd4: 68fb ldr r3, [r7, #12] 8000cd6: 68ba ldr r2, [r7, #8] 8000cd8: 611a str r2, [r3, #16] filter->sample_freq = sample_freq; 8000cda: 68fb ldr r3, [r7, #12] 8000cdc: 687a ldr r2, [r7, #4] 8000cde: 615a str r2, [r3, #20] } 8000ce0: bf00 nop 8000ce2: 3714 adds r7, #20 8000ce4: 46bd mov sp, r7 8000ce6: f85d 7b04 ldr.w r7, [sp], #4 8000cea: 4770 bx lr 08000cec : //--------------------------------------------------------------------------------------------------- // AHRS algorithm update void MadgwickAHRS_update(MadgwickAHRS_Filter* filter, float gx, float gy, float gz, float ax, float ay, float az, float mx, float my, float mz) { 8000cec: b580 push {r7, lr} 8000cee: b0b2 sub sp, #200 @ 0xc8 8000cf0: af00 add r7, sp, #0 8000cf2: 6278 str r0, [r7, #36] @ 0x24 8000cf4: ed87 0a08 vstr s0, [r7, #32] 8000cf8: edc7 0a07 vstr s1, [r7, #28] 8000cfc: ed87 1a06 vstr s2, [r7, #24] 8000d00: edc7 1a05 vstr s3, [r7, #20] 8000d04: ed87 2a04 vstr s4, [r7, #16] 8000d08: edc7 2a03 vstr s5, [r7, #12] 8000d0c: ed87 3a02 vstr s6, [r7, #8] 8000d10: edc7 3a01 vstr s7, [r7, #4] 8000d14: ed87 4a00 vstr s8, [r7] float q[4] = {filter->q[0], filter->q[1], filter->q[2], filter->q[3]}; 8000d18: 6a7b ldr r3, [r7, #36] @ 0x24 8000d1a: 681b ldr r3, [r3, #0] 8000d1c: 63fb str r3, [r7, #60] @ 0x3c 8000d1e: 6a7b ldr r3, [r7, #36] @ 0x24 8000d20: 685b ldr r3, [r3, #4] 8000d22: 643b str r3, [r7, #64] @ 0x40 8000d24: 6a7b ldr r3, [r7, #36] @ 0x24 8000d26: 689b ldr r3, [r3, #8] 8000d28: 647b str r3, [r7, #68] @ 0x44 8000d2a: 6a7b ldr r3, [r7, #36] @ 0x24 8000d2c: 68db ldr r3, [r3, #12] 8000d2e: 64bb str r3, [r7, #72] @ 0x48 float qDot[4]; float hx, hy; float _2q0mx, _2q0my, _2q0mz, _2q1mx, _2bx, _2bz, _4bx, _4bz, _2q0, _2q1, _2q2, _2q3, _2q0q2, _2q2q3, q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; // Use IMU algorithm if magnetometer measurement invalid (avoids NaN in magnetometer normalisation) if((mx == 0.0f) && (my == 0.0f) && (mz == 0.0f)) { 8000d30: edd7 7a02 vldr s15, [r7, #8] 8000d34: eef5 7a40 vcmp.f32 s15, #0.0 8000d38: eef1 fa10 vmrs APSR_nzcv, fpscr 8000d3c: d11e bne.n 8000d7c 8000d3e: edd7 7a01 vldr s15, [r7, #4] 8000d42: eef5 7a40 vcmp.f32 s15, #0.0 8000d46: eef1 fa10 vmrs APSR_nzcv, fpscr 8000d4a: d117 bne.n 8000d7c 8000d4c: edd7 7a00 vldr s15, [r7] 8000d50: eef5 7a40 vcmp.f32 s15, #0.0 8000d54: eef1 fa10 vmrs APSR_nzcv, fpscr 8000d58: d110 bne.n 8000d7c MadgwickAHRS_update_IMU(filter, gx, gy, gz, ax, ay, az); 8000d5a: edd7 2a03 vldr s5, [r7, #12] 8000d5e: ed97 2a04 vldr s4, [r7, #16] 8000d62: edd7 1a05 vldr s3, [r7, #20] 8000d66: ed97 1a06 vldr s2, [r7, #24] 8000d6a: edd7 0a07 vldr s1, [r7, #28] 8000d6e: ed97 0a08 vldr s0, [r7, #32] 8000d72: 6a78 ldr r0, [r7, #36] @ 0x24 8000d74: f000 fe6f bl 8001a56 8000d78: f000 be6a b.w 8001a50 return; } // Rate of change of quaternion from gyroscope qDot[0] = 0.5f * (-q[1] * gx - q[2] * gy - q[3] * gz); 8000d7c: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8000d80: eeb1 7a67 vneg.f32 s14, s15 8000d84: edd7 7a08 vldr s15, [r7, #32] 8000d88: ee27 7a27 vmul.f32 s14, s14, s15 8000d8c: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8000d90: edd7 7a07 vldr s15, [r7, #28] 8000d94: ee66 7aa7 vmul.f32 s15, s13, s15 8000d98: ee37 7a67 vsub.f32 s14, s14, s15 8000d9c: edd7 6a12 vldr s13, [r7, #72] @ 0x48 8000da0: edd7 7a06 vldr s15, [r7, #24] 8000da4: ee66 7aa7 vmul.f32 s15, s13, s15 8000da8: ee77 7a67 vsub.f32 s15, s14, s15 8000dac: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8000db0: ee67 7a87 vmul.f32 s15, s15, s14 8000db4: edc7 7a0b vstr s15, [r7, #44] @ 0x2c qDot[1] = 0.5f * (q[0] * gx + q[2] * gz - q[3] * gy); 8000db8: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8000dbc: edd7 7a08 vldr s15, [r7, #32] 8000dc0: ee27 7a27 vmul.f32 s14, s14, s15 8000dc4: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8000dc8: edd7 7a06 vldr s15, [r7, #24] 8000dcc: ee66 7aa7 vmul.f32 s15, s13, s15 8000dd0: ee37 7a27 vadd.f32 s14, s14, s15 8000dd4: edd7 6a12 vldr s13, [r7, #72] @ 0x48 8000dd8: edd7 7a07 vldr s15, [r7, #28] 8000ddc: ee66 7aa7 vmul.f32 s15, s13, s15 8000de0: ee77 7a67 vsub.f32 s15, s14, s15 8000de4: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8000de8: ee67 7a87 vmul.f32 s15, s15, s14 8000dec: edc7 7a0c vstr s15, [r7, #48] @ 0x30 qDot[2] = 0.5f * (q[0] * gy - q[1] * gz + q[3] * gx); 8000df0: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8000df4: edd7 7a07 vldr s15, [r7, #28] 8000df8: ee27 7a27 vmul.f32 s14, s14, s15 8000dfc: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8000e00: edd7 7a06 vldr s15, [r7, #24] 8000e04: ee66 7aa7 vmul.f32 s15, s13, s15 8000e08: ee37 7a67 vsub.f32 s14, s14, s15 8000e0c: edd7 6a12 vldr s13, [r7, #72] @ 0x48 8000e10: edd7 7a08 vldr s15, [r7, #32] 8000e14: ee66 7aa7 vmul.f32 s15, s13, s15 8000e18: ee77 7a27 vadd.f32 s15, s14, s15 8000e1c: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8000e20: ee67 7a87 vmul.f32 s15, s15, s14 8000e24: edc7 7a0d vstr s15, [r7, #52] @ 0x34 qDot[3] = 0.5f * (q[0] * gz + q[1] * gy - q[2] * gx); 8000e28: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8000e2c: edd7 7a06 vldr s15, [r7, #24] 8000e30: ee27 7a27 vmul.f32 s14, s14, s15 8000e34: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8000e38: edd7 7a07 vldr s15, [r7, #28] 8000e3c: ee66 7aa7 vmul.f32 s15, s13, s15 8000e40: ee37 7a27 vadd.f32 s14, s14, s15 8000e44: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8000e48: edd7 7a08 vldr s15, [r7, #32] 8000e4c: ee66 7aa7 vmul.f32 s15, s13, s15 8000e50: ee77 7a67 vsub.f32 s15, s14, s15 8000e54: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8000e58: ee67 7a87 vmul.f32 s15, s15, s14 8000e5c: edc7 7a0e vstr s15, [r7, #56] @ 0x38 // Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation) if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) { 8000e60: edd7 7a05 vldr s15, [r7, #20] 8000e64: eef5 7a40 vcmp.f32 s15, #0.0 8000e68: eef1 fa10 vmrs APSR_nzcv, fpscr 8000e6c: d10e bne.n 8000e8c 8000e6e: edd7 7a04 vldr s15, [r7, #16] 8000e72: eef5 7a40 vcmp.f32 s15, #0.0 8000e76: eef1 fa10 vmrs APSR_nzcv, fpscr 8000e7a: d107 bne.n 8000e8c 8000e7c: edd7 7a03 vldr s15, [r7, #12] 8000e80: eef5 7a40 vcmp.f32 s15, #0.0 8000e84: eef1 fa10 vmrs APSR_nzcv, fpscr 8000e88: f000 854e beq.w 8001928 // Normalise accelerometer measurement recipNorm = invSqrt(ax * ax + ay * ay + az * az); 8000e8c: edd7 7a05 vldr s15, [r7, #20] 8000e90: ee27 7aa7 vmul.f32 s14, s15, s15 8000e94: edd7 7a04 vldr s15, [r7, #16] 8000e98: ee67 7aa7 vmul.f32 s15, s15, s15 8000e9c: ee37 7a27 vadd.f32 s14, s14, s15 8000ea0: edd7 7a03 vldr s15, [r7, #12] 8000ea4: ee67 7aa7 vmul.f32 s15, s15, s15 8000ea8: ee77 7a27 vadd.f32 s15, s14, s15 8000eac: eeb0 0a67 vmov.f32 s0, s15 8000eb0: f001 f8d4 bl 800205c 8000eb4: ed87 0a31 vstr s0, [r7, #196] @ 0xc4 ax *= recipNorm; 8000eb8: ed97 7a05 vldr s14, [r7, #20] 8000ebc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000ec0: ee67 7a27 vmul.f32 s15, s14, s15 8000ec4: edc7 7a05 vstr s15, [r7, #20] ay *= recipNorm; 8000ec8: ed97 7a04 vldr s14, [r7, #16] 8000ecc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000ed0: ee67 7a27 vmul.f32 s15, s14, s15 8000ed4: edc7 7a04 vstr s15, [r7, #16] az *= recipNorm; 8000ed8: ed97 7a03 vldr s14, [r7, #12] 8000edc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000ee0: ee67 7a27 vmul.f32 s15, s14, s15 8000ee4: edc7 7a03 vstr s15, [r7, #12] // Normalise magnetometer measurement recipNorm = invSqrt(mx * mx + my * my + mz * mz); 8000ee8: edd7 7a02 vldr s15, [r7, #8] 8000eec: ee27 7aa7 vmul.f32 s14, s15, s15 8000ef0: edd7 7a01 vldr s15, [r7, #4] 8000ef4: ee67 7aa7 vmul.f32 s15, s15, s15 8000ef8: ee37 7a27 vadd.f32 s14, s14, s15 8000efc: edd7 7a00 vldr s15, [r7] 8000f00: ee67 7aa7 vmul.f32 s15, s15, s15 8000f04: ee77 7a27 vadd.f32 s15, s14, s15 8000f08: eeb0 0a67 vmov.f32 s0, s15 8000f0c: f001 f8a6 bl 800205c 8000f10: ed87 0a31 vstr s0, [r7, #196] @ 0xc4 mx *= recipNorm; 8000f14: ed97 7a02 vldr s14, [r7, #8] 8000f18: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000f1c: ee67 7a27 vmul.f32 s15, s14, s15 8000f20: edc7 7a02 vstr s15, [r7, #8] my *= recipNorm; 8000f24: ed97 7a01 vldr s14, [r7, #4] 8000f28: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000f2c: ee67 7a27 vmul.f32 s15, s14, s15 8000f30: edc7 7a01 vstr s15, [r7, #4] mz *= recipNorm; 8000f34: ed97 7a00 vldr s14, [r7] 8000f38: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000f3c: ee67 7a27 vmul.f32 s15, s14, s15 8000f40: edc7 7a00 vstr s15, [r7] // Auxiliary variables to avoid repeated arithmetic _2q0mx = 2.0f * q[0] * mx; 8000f44: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000f48: ee77 7aa7 vadd.f32 s15, s15, s15 8000f4c: ed97 7a02 vldr s14, [r7, #8] 8000f50: ee67 7a27 vmul.f32 s15, s14, s15 8000f54: edc7 7a30 vstr s15, [r7, #192] @ 0xc0 _2q0my = 2.0f * q[0] * my; 8000f58: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000f5c: ee77 7aa7 vadd.f32 s15, s15, s15 8000f60: ed97 7a01 vldr s14, [r7, #4] 8000f64: ee67 7a27 vmul.f32 s15, s14, s15 8000f68: edc7 7a2f vstr s15, [r7, #188] @ 0xbc _2q0mz = 2.0f * q[0] * mz; 8000f6c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000f70: ee77 7aa7 vadd.f32 s15, s15, s15 8000f74: ed97 7a00 vldr s14, [r7] 8000f78: ee67 7a27 vmul.f32 s15, s14, s15 8000f7c: edc7 7a2e vstr s15, [r7, #184] @ 0xb8 _2q1mx = 2.0f * q[1] * mx; 8000f80: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8000f84: ee77 7aa7 vadd.f32 s15, s15, s15 8000f88: ed97 7a02 vldr s14, [r7, #8] 8000f8c: ee67 7a27 vmul.f32 s15, s14, s15 8000f90: edc7 7a2d vstr s15, [r7, #180] @ 0xb4 _2q0 = 2.0f * q[0]; 8000f94: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000f98: ee77 7aa7 vadd.f32 s15, s15, s15 8000f9c: edc7 7a2c vstr s15, [r7, #176] @ 0xb0 _2q1 = 2.0f * q[1]; 8000fa0: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8000fa4: ee77 7aa7 vadd.f32 s15, s15, s15 8000fa8: edc7 7a2b vstr s15, [r7, #172] @ 0xac _2q2 = 2.0f * q[2]; 8000fac: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8000fb0: ee77 7aa7 vadd.f32 s15, s15, s15 8000fb4: edc7 7a2a vstr s15, [r7, #168] @ 0xa8 _2q3 = 2.0f * q[3]; 8000fb8: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8000fbc: ee77 7aa7 vadd.f32 s15, s15, s15 8000fc0: edc7 7a29 vstr s15, [r7, #164] @ 0xa4 _2q0q2 = 2.0f * q[0] * q[2]; 8000fc4: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000fc8: ee37 7aa7 vadd.f32 s14, s15, s15 8000fcc: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8000fd0: ee67 7a27 vmul.f32 s15, s14, s15 8000fd4: edc7 7a28 vstr s15, [r7, #160] @ 0xa0 _2q2q3 = 2.0f * q[2] * q[3]; 8000fd8: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8000fdc: ee37 7aa7 vadd.f32 s14, s15, s15 8000fe0: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8000fe4: ee67 7a27 vmul.f32 s15, s14, s15 8000fe8: edc7 7a27 vstr s15, [r7, #156] @ 0x9c q0q0 = q[0] * q[0]; 8000fec: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8000ff0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000ff4: ee67 7a27 vmul.f32 s15, s14, s15 8000ff8: edc7 7a26 vstr s15, [r7, #152] @ 0x98 q0q1 = q[0] * q[1]; 8000ffc: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001000: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001004: ee67 7a27 vmul.f32 s15, s14, s15 8001008: edc7 7a25 vstr s15, [r7, #148] @ 0x94 q0q2 = q[0] * q[2]; 800100c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001010: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001014: ee67 7a27 vmul.f32 s15, s14, s15 8001018: edc7 7a24 vstr s15, [r7, #144] @ 0x90 q0q3 = q[0] * q[3]; 800101c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001020: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001024: ee67 7a27 vmul.f32 s15, s14, s15 8001028: edc7 7a23 vstr s15, [r7, #140] @ 0x8c q1q1 = q[1] * q[1]; 800102c: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001030: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001034: ee67 7a27 vmul.f32 s15, s14, s15 8001038: edc7 7a22 vstr s15, [r7, #136] @ 0x88 q1q2 = q[1] * q[2]; 800103c: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001040: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001044: ee67 7a27 vmul.f32 s15, s14, s15 8001048: edc7 7a21 vstr s15, [r7, #132] @ 0x84 q1q3 = q[1] * q[3]; 800104c: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001050: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001054: ee67 7a27 vmul.f32 s15, s14, s15 8001058: edc7 7a20 vstr s15, [r7, #128] @ 0x80 q2q2 = q[2] * q[2]; 800105c: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001060: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001064: ee67 7a27 vmul.f32 s15, s14, s15 8001068: edc7 7a1f vstr s15, [r7, #124] @ 0x7c q2q3 = q[2] * q[3]; 800106c: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001070: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001074: ee67 7a27 vmul.f32 s15, s14, s15 8001078: edc7 7a1e vstr s15, [r7, #120] @ 0x78 q3q3 = q[3] * q[3]; 800107c: ed97 7a12 vldr s14, [r7, #72] @ 0x48 8001080: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001084: ee67 7a27 vmul.f32 s15, s14, s15 8001088: edc7 7a1d vstr s15, [r7, #116] @ 0x74 // Reference direction of Earth's magnetic field hx = mx * q0q0 - _2q0my * q[3] + _2q0mz * q[2] + mx * q1q1 + _2q1 * my * q[2] + _2q1 * mz * q[3] - mx * q2q2 - mx * q3q3; 800108c: ed97 7a02 vldr s14, [r7, #8] 8001090: edd7 7a26 vldr s15, [r7, #152] @ 0x98 8001094: ee27 7a27 vmul.f32 s14, s14, s15 8001098: edd7 6a12 vldr s13, [r7, #72] @ 0x48 800109c: edd7 7a2f vldr s15, [r7, #188] @ 0xbc 80010a0: ee66 7aa7 vmul.f32 s15, s13, s15 80010a4: ee37 7a67 vsub.f32 s14, s14, s15 80010a8: edd7 6a11 vldr s13, [r7, #68] @ 0x44 80010ac: edd7 7a2e vldr s15, [r7, #184] @ 0xb8 80010b0: ee66 7aa7 vmul.f32 s15, s13, s15 80010b4: ee37 7a27 vadd.f32 s14, s14, s15 80010b8: edd7 6a02 vldr s13, [r7, #8] 80010bc: edd7 7a22 vldr s15, [r7, #136] @ 0x88 80010c0: ee66 7aa7 vmul.f32 s15, s13, s15 80010c4: ee37 7a27 vadd.f32 s14, s14, s15 80010c8: edd7 6a2b vldr s13, [r7, #172] @ 0xac 80010cc: edd7 7a01 vldr s15, [r7, #4] 80010d0: ee66 6aa7 vmul.f32 s13, s13, s15 80010d4: edd7 7a11 vldr s15, [r7, #68] @ 0x44 80010d8: ee66 7aa7 vmul.f32 s15, s13, s15 80010dc: ee37 7a27 vadd.f32 s14, s14, s15 80010e0: edd7 6a2b vldr s13, [r7, #172] @ 0xac 80010e4: edd7 7a00 vldr s15, [r7] 80010e8: ee66 6aa7 vmul.f32 s13, s13, s15 80010ec: edd7 7a12 vldr s15, [r7, #72] @ 0x48 80010f0: ee66 7aa7 vmul.f32 s15, s13, s15 80010f4: ee37 7a27 vadd.f32 s14, s14, s15 80010f8: edd7 6a02 vldr s13, [r7, #8] 80010fc: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 8001100: ee66 7aa7 vmul.f32 s15, s13, s15 8001104: ee37 7a67 vsub.f32 s14, s14, s15 8001108: edd7 6a02 vldr s13, [r7, #8] 800110c: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001110: ee66 7aa7 vmul.f32 s15, s13, s15 8001114: ee77 7a67 vsub.f32 s15, s14, s15 8001118: edc7 7a1c vstr s15, [r7, #112] @ 0x70 hy = _2q0mx * q[3] + my * q0q0 - _2q0mz * q[1] + _2q1mx * q[2] - my * q1q1 + my * q2q2 + _2q2 * mz * q[3] - my * q3q3; 800111c: ed97 7a12 vldr s14, [r7, #72] @ 0x48 8001120: edd7 7a30 vldr s15, [r7, #192] @ 0xc0 8001124: ee27 7a27 vmul.f32 s14, s14, s15 8001128: edd7 6a01 vldr s13, [r7, #4] 800112c: edd7 7a26 vldr s15, [r7, #152] @ 0x98 8001130: ee66 7aa7 vmul.f32 s15, s13, s15 8001134: ee37 7a27 vadd.f32 s14, s14, s15 8001138: edd7 6a10 vldr s13, [r7, #64] @ 0x40 800113c: edd7 7a2e vldr s15, [r7, #184] @ 0xb8 8001140: ee66 7aa7 vmul.f32 s15, s13, s15 8001144: ee37 7a67 vsub.f32 s14, s14, s15 8001148: edd7 6a11 vldr s13, [r7, #68] @ 0x44 800114c: edd7 7a2d vldr s15, [r7, #180] @ 0xb4 8001150: ee66 7aa7 vmul.f32 s15, s13, s15 8001154: ee37 7a27 vadd.f32 s14, s14, s15 8001158: edd7 6a01 vldr s13, [r7, #4] 800115c: edd7 7a22 vldr s15, [r7, #136] @ 0x88 8001160: ee66 7aa7 vmul.f32 s15, s13, s15 8001164: ee37 7a67 vsub.f32 s14, s14, s15 8001168: edd7 6a01 vldr s13, [r7, #4] 800116c: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 8001170: ee66 7aa7 vmul.f32 s15, s13, s15 8001174: ee37 7a27 vadd.f32 s14, s14, s15 8001178: edd7 6a2a vldr s13, [r7, #168] @ 0xa8 800117c: edd7 7a00 vldr s15, [r7] 8001180: ee66 6aa7 vmul.f32 s13, s13, s15 8001184: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001188: ee66 7aa7 vmul.f32 s15, s13, s15 800118c: ee37 7a27 vadd.f32 s14, s14, s15 8001190: edd7 6a01 vldr s13, [r7, #4] 8001194: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001198: ee66 7aa7 vmul.f32 s15, s13, s15 800119c: ee77 7a67 vsub.f32 s15, s14, s15 80011a0: edc7 7a1b vstr s15, [r7, #108] @ 0x6c _2bx = sqrt(hx * hx + hy * hy); 80011a4: edd7 7a1c vldr s15, [r7, #112] @ 0x70 80011a8: ee27 7aa7 vmul.f32 s14, s15, s15 80011ac: edd7 7a1b vldr s15, [r7, #108] @ 0x6c 80011b0: ee67 7aa7 vmul.f32 s15, s15, s15 80011b4: ee77 7a27 vadd.f32 s15, s14, s15 80011b8: ee17 0a90 vmov r0, s15 80011bc: f7ff f99c bl 80004f8 <__aeabi_f2d> 80011c0: 4602 mov r2, r0 80011c2: 460b mov r3, r1 80011c4: ec43 2b10 vmov d0, r2, r3 80011c8: f01b fff6 bl 801d1b8 80011cc: ec53 2b10 vmov r2, r3, d0 80011d0: 4610 mov r0, r2 80011d2: 4619 mov r1, r3 80011d4: f7ff fce0 bl 8000b98 <__aeabi_d2f> 80011d8: 4603 mov r3, r0 80011da: 66bb str r3, [r7, #104] @ 0x68 _2bz = -_2q0mx * q[2] + _2q0my * q[1] + mz * q0q0 + _2q1mx * q[3] - mz * q1q1 + _2q2 * my * q[3] - mz * q2q2 + mz * q3q3; 80011dc: edd7 7a30 vldr s15, [r7, #192] @ 0xc0 80011e0: eeb1 7a67 vneg.f32 s14, s15 80011e4: edd7 7a11 vldr s15, [r7, #68] @ 0x44 80011e8: ee27 7a27 vmul.f32 s14, s14, s15 80011ec: edd7 6a10 vldr s13, [r7, #64] @ 0x40 80011f0: edd7 7a2f vldr s15, [r7, #188] @ 0xbc 80011f4: ee66 7aa7 vmul.f32 s15, s13, s15 80011f8: ee37 7a27 vadd.f32 s14, s14, s15 80011fc: edd7 6a00 vldr s13, [r7] 8001200: edd7 7a26 vldr s15, [r7, #152] @ 0x98 8001204: ee66 7aa7 vmul.f32 s15, s13, s15 8001208: ee37 7a27 vadd.f32 s14, s14, s15 800120c: edd7 6a12 vldr s13, [r7, #72] @ 0x48 8001210: edd7 7a2d vldr s15, [r7, #180] @ 0xb4 8001214: ee66 7aa7 vmul.f32 s15, s13, s15 8001218: ee37 7a27 vadd.f32 s14, s14, s15 800121c: edd7 6a00 vldr s13, [r7] 8001220: edd7 7a22 vldr s15, [r7, #136] @ 0x88 8001224: ee66 7aa7 vmul.f32 s15, s13, s15 8001228: ee37 7a67 vsub.f32 s14, s14, s15 800122c: edd7 6a2a vldr s13, [r7, #168] @ 0xa8 8001230: edd7 7a01 vldr s15, [r7, #4] 8001234: ee66 6aa7 vmul.f32 s13, s13, s15 8001238: edd7 7a12 vldr s15, [r7, #72] @ 0x48 800123c: ee66 7aa7 vmul.f32 s15, s13, s15 8001240: ee37 7a27 vadd.f32 s14, s14, s15 8001244: edd7 6a00 vldr s13, [r7] 8001248: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 800124c: ee66 7aa7 vmul.f32 s15, s13, s15 8001250: ee37 7a67 vsub.f32 s14, s14, s15 8001254: edd7 6a00 vldr s13, [r7] 8001258: edd7 7a1d vldr s15, [r7, #116] @ 0x74 800125c: ee66 7aa7 vmul.f32 s15, s13, s15 8001260: ee77 7a27 vadd.f32 s15, s14, s15 8001264: edc7 7a19 vstr s15, [r7, #100] @ 0x64 _4bx = 2.0f * _2bx; 8001268: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800126c: ee77 7aa7 vadd.f32 s15, s15, s15 8001270: edc7 7a18 vstr s15, [r7, #96] @ 0x60 _4bz = 2.0f * _2bz; 8001274: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001278: ee77 7aa7 vadd.f32 s15, s15, s15 800127c: edc7 7a17 vstr s15, [r7, #92] @ 0x5c // Gradient decent algorithm corrective step s0 = -_2q2 * (2.0f * q1q3 - _2q0q2 - ax) + _2q1 * (2.0f * q0q1 + _2q2q3 - ay) - _2bz * q[2] * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (-_2bx * q[3] + _2bz * q[1]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + _2bx * q[2] * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz); 8001280: edd7 7a2a vldr s15, [r7, #168] @ 0xa8 8001284: eeb1 7a67 vneg.f32 s14, s15 8001288: edd7 7a20 vldr s15, [r7, #128] @ 0x80 800128c: ee77 6aa7 vadd.f32 s13, s15, s15 8001290: edd7 7a28 vldr s15, [r7, #160] @ 0xa0 8001294: ee76 6ae7 vsub.f32 s13, s13, s15 8001298: edd7 7a05 vldr s15, [r7, #20] 800129c: ee76 7ae7 vsub.f32 s15, s13, s15 80012a0: ee27 7a27 vmul.f32 s14, s14, s15 80012a4: edd7 7a25 vldr s15, [r7, #148] @ 0x94 80012a8: ee77 6aa7 vadd.f32 s13, s15, s15 80012ac: edd7 7a27 vldr s15, [r7, #156] @ 0x9c 80012b0: ee76 6aa7 vadd.f32 s13, s13, s15 80012b4: edd7 7a04 vldr s15, [r7, #16] 80012b8: ee76 6ae7 vsub.f32 s13, s13, s15 80012bc: edd7 7a2b vldr s15, [r7, #172] @ 0xac 80012c0: ee66 7aa7 vmul.f32 s15, s13, s15 80012c4: ee37 7a27 vadd.f32 s14, s14, s15 80012c8: edd7 6a11 vldr s13, [r7, #68] @ 0x44 80012cc: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80012d0: ee66 6aa7 vmul.f32 s13, s13, s15 80012d4: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 80012d8: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80012dc: ee36 6a67 vsub.f32 s12, s12, s15 80012e0: edd7 7a1d vldr s15, [r7, #116] @ 0x74 80012e4: ee36 6a67 vsub.f32 s12, s12, s15 80012e8: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80012ec: ee26 6a27 vmul.f32 s12, s12, s15 80012f0: edd7 5a20 vldr s11, [r7, #128] @ 0x80 80012f4: edd7 7a24 vldr s15, [r7, #144] @ 0x90 80012f8: ee75 5ae7 vsub.f32 s11, s11, s15 80012fc: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001300: ee65 7aa7 vmul.f32 s15, s11, s15 8001304: ee36 6a27 vadd.f32 s12, s12, s15 8001308: edd7 7a02 vldr s15, [r7, #8] 800130c: ee76 7a67 vsub.f32 s15, s12, s15 8001310: ee66 7aa7 vmul.f32 s15, s13, s15 8001314: ee37 7a67 vsub.f32 s14, s14, s15 8001318: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800131c: eef1 6a67 vneg.f32 s13, s15 8001320: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001324: ee66 6aa7 vmul.f32 s13, s13, s15 8001328: ed97 6a10 vldr s12, [r7, #64] @ 0x40 800132c: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001330: ee66 7a27 vmul.f32 s15, s12, s15 8001334: ee76 6aa7 vadd.f32 s13, s13, s15 8001338: ed97 6a21 vldr s12, [r7, #132] @ 0x84 800133c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001340: ee36 6a67 vsub.f32 s12, s12, s15 8001344: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001348: ee26 6a27 vmul.f32 s12, s12, s15 800134c: edd7 5a25 vldr s11, [r7, #148] @ 0x94 8001350: edd7 7a1e vldr s15, [r7, #120] @ 0x78 8001354: ee75 5aa7 vadd.f32 s11, s11, s15 8001358: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800135c: ee65 7aa7 vmul.f32 s15, s11, s15 8001360: ee36 6a27 vadd.f32 s12, s12, s15 8001364: edd7 7a01 vldr s15, [r7, #4] 8001368: ee76 7a67 vsub.f32 s15, s12, s15 800136c: ee66 7aa7 vmul.f32 s15, s13, s15 8001370: ee37 7a27 vadd.f32 s14, s14, s15 8001374: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8001378: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800137c: ee66 6aa7 vmul.f32 s13, s13, s15 8001380: ed97 6a24 vldr s12, [r7, #144] @ 0x90 8001384: edd7 7a20 vldr s15, [r7, #128] @ 0x80 8001388: ee36 6a27 vadd.f32 s12, s12, s15 800138c: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001390: ee26 6a27 vmul.f32 s12, s12, s15 8001394: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5 8001398: edd7 7a22 vldr s15, [r7, #136] @ 0x88 800139c: ee75 5ae7 vsub.f32 s11, s11, s15 80013a0: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80013a4: ee75 5ae7 vsub.f32 s11, s11, s15 80013a8: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80013ac: ee65 7aa7 vmul.f32 s15, s11, s15 80013b0: ee36 6a27 vadd.f32 s12, s12, s15 80013b4: edd7 7a00 vldr s15, [r7] 80013b8: ee76 7a67 vsub.f32 s15, s12, s15 80013bc: ee66 7aa7 vmul.f32 s15, s13, s15 80013c0: ee77 7a27 vadd.f32 s15, s14, s15 80013c4: edc7 7a16 vstr s15, [r7, #88] @ 0x58 s1 = _2q3 * (2.0f * q1q3 - _2q0q2 - ax) + _2q0 * (2.0f * q0q1 + _2q2q3 - ay) - 4.0f * q[1] * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) + _2bz * q[3] * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (_2bx * q[2] + _2bz * q[0]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + (_2bx * q[3] - _4bz * q[1]) * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz); 80013c8: edd7 7a20 vldr s15, [r7, #128] @ 0x80 80013cc: ee37 7aa7 vadd.f32 s14, s15, s15 80013d0: edd7 7a28 vldr s15, [r7, #160] @ 0xa0 80013d4: ee37 7a67 vsub.f32 s14, s14, s15 80013d8: edd7 7a05 vldr s15, [r7, #20] 80013dc: ee37 7a67 vsub.f32 s14, s14, s15 80013e0: edd7 7a29 vldr s15, [r7, #164] @ 0xa4 80013e4: ee27 7a27 vmul.f32 s14, s14, s15 80013e8: edd7 7a25 vldr s15, [r7, #148] @ 0x94 80013ec: ee77 6aa7 vadd.f32 s13, s15, s15 80013f0: edd7 7a27 vldr s15, [r7, #156] @ 0x9c 80013f4: ee76 6aa7 vadd.f32 s13, s13, s15 80013f8: edd7 7a04 vldr s15, [r7, #16] 80013fc: ee76 6ae7 vsub.f32 s13, s13, s15 8001400: edd7 7a2c vldr s15, [r7, #176] @ 0xb0 8001404: ee66 7aa7 vmul.f32 s15, s13, s15 8001408: ee37 7a27 vadd.f32 s14, s14, s15 800140c: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001410: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0 8001414: ee67 6aa6 vmul.f32 s13, s15, s13 8001418: edd7 7a22 vldr s15, [r7, #136] @ 0x88 800141c: ee77 7aa7 vadd.f32 s15, s15, s15 8001420: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0 8001424: ee36 6a67 vsub.f32 s12, s12, s15 8001428: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 800142c: ee77 7aa7 vadd.f32 s15, s15, s15 8001430: ee36 6a67 vsub.f32 s12, s12, s15 8001434: edd7 7a03 vldr s15, [r7, #12] 8001438: ee76 7a67 vsub.f32 s15, s12, s15 800143c: ee66 7aa7 vmul.f32 s15, s13, s15 8001440: ee37 7a67 vsub.f32 s14, s14, s15 8001444: edd7 6a12 vldr s13, [r7, #72] @ 0x48 8001448: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800144c: ee66 6aa7 vmul.f32 s13, s13, s15 8001450: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 8001454: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 8001458: ee36 6a67 vsub.f32 s12, s12, s15 800145c: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001460: ee36 6a67 vsub.f32 s12, s12, s15 8001464: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001468: ee26 6a27 vmul.f32 s12, s12, s15 800146c: edd7 5a20 vldr s11, [r7, #128] @ 0x80 8001470: edd7 7a24 vldr s15, [r7, #144] @ 0x90 8001474: ee75 5ae7 vsub.f32 s11, s11, s15 8001478: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800147c: ee65 7aa7 vmul.f32 s15, s11, s15 8001480: ee36 6a27 vadd.f32 s12, s12, s15 8001484: edd7 7a02 vldr s15, [r7, #8] 8001488: ee76 7a67 vsub.f32 s15, s12, s15 800148c: ee66 7aa7 vmul.f32 s15, s13, s15 8001490: ee37 7a27 vadd.f32 s14, s14, s15 8001494: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8001498: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800149c: ee66 6aa7 vmul.f32 s13, s13, s15 80014a0: ed97 6a0f vldr s12, [r7, #60] @ 0x3c 80014a4: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80014a8: ee66 7a27 vmul.f32 s15, s12, s15 80014ac: ee76 6aa7 vadd.f32 s13, s13, s15 80014b0: ed97 6a21 vldr s12, [r7, #132] @ 0x84 80014b4: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 80014b8: ee36 6a67 vsub.f32 s12, s12, s15 80014bc: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80014c0: ee26 6a27 vmul.f32 s12, s12, s15 80014c4: edd7 5a25 vldr s11, [r7, #148] @ 0x94 80014c8: edd7 7a1e vldr s15, [r7, #120] @ 0x78 80014cc: ee75 5aa7 vadd.f32 s11, s11, s15 80014d0: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80014d4: ee65 7aa7 vmul.f32 s15, s11, s15 80014d8: ee36 6a27 vadd.f32 s12, s12, s15 80014dc: edd7 7a01 vldr s15, [r7, #4] 80014e0: ee76 7a67 vsub.f32 s15, s12, s15 80014e4: ee66 7aa7 vmul.f32 s15, s13, s15 80014e8: ee37 7a27 vadd.f32 s14, s14, s15 80014ec: edd7 6a12 vldr s13, [r7, #72] @ 0x48 80014f0: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80014f4: ee66 6aa7 vmul.f32 s13, s13, s15 80014f8: ed97 6a10 vldr s12, [r7, #64] @ 0x40 80014fc: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8001500: ee66 7a27 vmul.f32 s15, s12, s15 8001504: ee76 6ae7 vsub.f32 s13, s13, s15 8001508: ed97 6a24 vldr s12, [r7, #144] @ 0x90 800150c: edd7 7a20 vldr s15, [r7, #128] @ 0x80 8001510: ee36 6a27 vadd.f32 s12, s12, s15 8001514: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001518: ee26 6a27 vmul.f32 s12, s12, s15 800151c: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5 8001520: edd7 7a22 vldr s15, [r7, #136] @ 0x88 8001524: ee75 5ae7 vsub.f32 s11, s11, s15 8001528: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 800152c: ee75 5ae7 vsub.f32 s11, s11, s15 8001530: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001534: ee65 7aa7 vmul.f32 s15, s11, s15 8001538: ee36 6a27 vadd.f32 s12, s12, s15 800153c: edd7 7a00 vldr s15, [r7] 8001540: ee76 7a67 vsub.f32 s15, s12, s15 8001544: ee66 7aa7 vmul.f32 s15, s13, s15 8001548: ee77 7a27 vadd.f32 s15, s14, s15 800154c: edc7 7a15 vstr s15, [r7, #84] @ 0x54 s2 = -_2q0 * (2.0f * q1q3 - _2q0q2 - ax) + _2q3 * (2.0f * q0q1 + _2q2q3 - ay) - 4.0f * q[2] * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) + (-_4bx * q[2] - _2bz * q[0]) * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (_2bx * q[1] + _2bz * q[3]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + (_2bx * q[0] - _4bz * q[2]) * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz); 8001550: edd7 7a2c vldr s15, [r7, #176] @ 0xb0 8001554: eeb1 7a67 vneg.f32 s14, s15 8001558: edd7 7a20 vldr s15, [r7, #128] @ 0x80 800155c: ee77 6aa7 vadd.f32 s13, s15, s15 8001560: edd7 7a28 vldr s15, [r7, #160] @ 0xa0 8001564: ee76 6ae7 vsub.f32 s13, s13, s15 8001568: edd7 7a05 vldr s15, [r7, #20] 800156c: ee76 7ae7 vsub.f32 s15, s13, s15 8001570: ee27 7a27 vmul.f32 s14, s14, s15 8001574: edd7 7a25 vldr s15, [r7, #148] @ 0x94 8001578: ee77 6aa7 vadd.f32 s13, s15, s15 800157c: edd7 7a27 vldr s15, [r7, #156] @ 0x9c 8001580: ee76 6aa7 vadd.f32 s13, s13, s15 8001584: edd7 7a04 vldr s15, [r7, #16] 8001588: ee76 6ae7 vsub.f32 s13, s13, s15 800158c: edd7 7a29 vldr s15, [r7, #164] @ 0xa4 8001590: ee66 7aa7 vmul.f32 s15, s13, s15 8001594: ee37 7a27 vadd.f32 s14, s14, s15 8001598: edd7 7a11 vldr s15, [r7, #68] @ 0x44 800159c: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0 80015a0: ee67 6aa6 vmul.f32 s13, s15, s13 80015a4: edd7 7a22 vldr s15, [r7, #136] @ 0x88 80015a8: ee77 7aa7 vadd.f32 s15, s15, s15 80015ac: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0 80015b0: ee36 6a67 vsub.f32 s12, s12, s15 80015b4: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80015b8: ee77 7aa7 vadd.f32 s15, s15, s15 80015bc: ee36 6a67 vsub.f32 s12, s12, s15 80015c0: edd7 7a03 vldr s15, [r7, #12] 80015c4: ee76 7a67 vsub.f32 s15, s12, s15 80015c8: ee66 7aa7 vmul.f32 s15, s13, s15 80015cc: ee37 7a67 vsub.f32 s14, s14, s15 80015d0: edd7 7a18 vldr s15, [r7, #96] @ 0x60 80015d4: eef1 6a67 vneg.f32 s13, s15 80015d8: edd7 7a11 vldr s15, [r7, #68] @ 0x44 80015dc: ee66 6aa7 vmul.f32 s13, s13, s15 80015e0: ed97 6a0f vldr s12, [r7, #60] @ 0x3c 80015e4: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80015e8: ee66 7a27 vmul.f32 s15, s12, s15 80015ec: ee76 6ae7 vsub.f32 s13, s13, s15 80015f0: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 80015f4: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80015f8: ee36 6a67 vsub.f32 s12, s12, s15 80015fc: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001600: ee36 6a67 vsub.f32 s12, s12, s15 8001604: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001608: ee26 6a27 vmul.f32 s12, s12, s15 800160c: edd7 5a20 vldr s11, [r7, #128] @ 0x80 8001610: edd7 7a24 vldr s15, [r7, #144] @ 0x90 8001614: ee75 5ae7 vsub.f32 s11, s11, s15 8001618: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800161c: ee65 7aa7 vmul.f32 s15, s11, s15 8001620: ee36 6a27 vadd.f32 s12, s12, s15 8001624: edd7 7a02 vldr s15, [r7, #8] 8001628: ee76 7a67 vsub.f32 s15, s12, s15 800162c: ee66 7aa7 vmul.f32 s15, s13, s15 8001630: ee37 7a27 vadd.f32 s14, s14, s15 8001634: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8001638: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800163c: ee66 6aa7 vmul.f32 s13, s13, s15 8001640: ed97 6a12 vldr s12, [r7, #72] @ 0x48 8001644: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001648: ee66 7a27 vmul.f32 s15, s12, s15 800164c: ee76 6aa7 vadd.f32 s13, s13, s15 8001650: ed97 6a21 vldr s12, [r7, #132] @ 0x84 8001654: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001658: ee36 6a67 vsub.f32 s12, s12, s15 800165c: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001660: ee26 6a27 vmul.f32 s12, s12, s15 8001664: edd7 5a25 vldr s11, [r7, #148] @ 0x94 8001668: edd7 7a1e vldr s15, [r7, #120] @ 0x78 800166c: ee75 5aa7 vadd.f32 s11, s11, s15 8001670: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001674: ee65 7aa7 vmul.f32 s15, s11, s15 8001678: ee36 6a27 vadd.f32 s12, s12, s15 800167c: edd7 7a01 vldr s15, [r7, #4] 8001680: ee76 7a67 vsub.f32 s15, s12, s15 8001684: ee66 7aa7 vmul.f32 s15, s13, s15 8001688: ee37 7a27 vadd.f32 s14, s14, s15 800168c: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001690: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001694: ee66 6aa7 vmul.f32 s13, s13, s15 8001698: ed97 6a11 vldr s12, [r7, #68] @ 0x44 800169c: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 80016a0: ee66 7a27 vmul.f32 s15, s12, s15 80016a4: ee76 6ae7 vsub.f32 s13, s13, s15 80016a8: ed97 6a24 vldr s12, [r7, #144] @ 0x90 80016ac: edd7 7a20 vldr s15, [r7, #128] @ 0x80 80016b0: ee36 6a27 vadd.f32 s12, s12, s15 80016b4: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80016b8: ee26 6a27 vmul.f32 s12, s12, s15 80016bc: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5 80016c0: edd7 7a22 vldr s15, [r7, #136] @ 0x88 80016c4: ee75 5ae7 vsub.f32 s11, s11, s15 80016c8: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80016cc: ee75 5ae7 vsub.f32 s11, s11, s15 80016d0: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80016d4: ee65 7aa7 vmul.f32 s15, s11, s15 80016d8: ee36 6a27 vadd.f32 s12, s12, s15 80016dc: edd7 7a00 vldr s15, [r7] 80016e0: ee76 7a67 vsub.f32 s15, s12, s15 80016e4: ee66 7aa7 vmul.f32 s15, s13, s15 80016e8: ee77 7a27 vadd.f32 s15, s14, s15 80016ec: edc7 7a14 vstr s15, [r7, #80] @ 0x50 s3 = _2q1 * (2.0f * q1q3 - _2q0q2 - ax) + _2q2 * (2.0f * q0q1 + _2q2q3 - ay) + (-_4bx * q[3] + _2bz * q[1]) * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (-_2bx * q[0] + _2bz * q[2]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + _2bx * q[1] * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz); 80016f0: edd7 7a20 vldr s15, [r7, #128] @ 0x80 80016f4: ee37 7aa7 vadd.f32 s14, s15, s15 80016f8: edd7 7a28 vldr s15, [r7, #160] @ 0xa0 80016fc: ee37 7a67 vsub.f32 s14, s14, s15 8001700: edd7 7a05 vldr s15, [r7, #20] 8001704: ee37 7a67 vsub.f32 s14, s14, s15 8001708: edd7 7a2b vldr s15, [r7, #172] @ 0xac 800170c: ee27 7a27 vmul.f32 s14, s14, s15 8001710: edd7 7a25 vldr s15, [r7, #148] @ 0x94 8001714: ee77 6aa7 vadd.f32 s13, s15, s15 8001718: edd7 7a27 vldr s15, [r7, #156] @ 0x9c 800171c: ee76 6aa7 vadd.f32 s13, s13, s15 8001720: edd7 7a04 vldr s15, [r7, #16] 8001724: ee76 6ae7 vsub.f32 s13, s13, s15 8001728: edd7 7a2a vldr s15, [r7, #168] @ 0xa8 800172c: ee66 7aa7 vmul.f32 s15, s13, s15 8001730: ee37 7a27 vadd.f32 s14, s14, s15 8001734: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8001738: eef1 6a67 vneg.f32 s13, s15 800173c: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001740: ee66 6aa7 vmul.f32 s13, s13, s15 8001744: ed97 6a10 vldr s12, [r7, #64] @ 0x40 8001748: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800174c: ee66 7a27 vmul.f32 s15, s12, s15 8001750: ee76 6aa7 vadd.f32 s13, s13, s15 8001754: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 8001758: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 800175c: ee36 6a67 vsub.f32 s12, s12, s15 8001760: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001764: ee36 6a67 vsub.f32 s12, s12, s15 8001768: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800176c: ee26 6a27 vmul.f32 s12, s12, s15 8001770: edd7 5a20 vldr s11, [r7, #128] @ 0x80 8001774: edd7 7a24 vldr s15, [r7, #144] @ 0x90 8001778: ee75 5ae7 vsub.f32 s11, s11, s15 800177c: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001780: ee65 7aa7 vmul.f32 s15, s11, s15 8001784: ee36 6a27 vadd.f32 s12, s12, s15 8001788: edd7 7a02 vldr s15, [r7, #8] 800178c: ee76 7a67 vsub.f32 s15, s12, s15 8001790: ee66 7aa7 vmul.f32 s15, s13, s15 8001794: ee37 7a27 vadd.f32 s14, s14, s15 8001798: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800179c: eef1 6a67 vneg.f32 s13, s15 80017a0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 80017a4: ee66 6aa7 vmul.f32 s13, s13, s15 80017a8: ed97 6a11 vldr s12, [r7, #68] @ 0x44 80017ac: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80017b0: ee66 7a27 vmul.f32 s15, s12, s15 80017b4: ee76 6aa7 vadd.f32 s13, s13, s15 80017b8: ed97 6a21 vldr s12, [r7, #132] @ 0x84 80017bc: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 80017c0: ee36 6a67 vsub.f32 s12, s12, s15 80017c4: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80017c8: ee26 6a27 vmul.f32 s12, s12, s15 80017cc: edd7 5a25 vldr s11, [r7, #148] @ 0x94 80017d0: edd7 7a1e vldr s15, [r7, #120] @ 0x78 80017d4: ee75 5aa7 vadd.f32 s11, s11, s15 80017d8: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80017dc: ee65 7aa7 vmul.f32 s15, s11, s15 80017e0: ee36 6a27 vadd.f32 s12, s12, s15 80017e4: edd7 7a01 vldr s15, [r7, #4] 80017e8: ee76 7a67 vsub.f32 s15, s12, s15 80017ec: ee66 7aa7 vmul.f32 s15, s13, s15 80017f0: ee37 7a27 vadd.f32 s14, s14, s15 80017f4: edd7 6a10 vldr s13, [r7, #64] @ 0x40 80017f8: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80017fc: ee66 6aa7 vmul.f32 s13, s13, s15 8001800: ed97 6a24 vldr s12, [r7, #144] @ 0x90 8001804: edd7 7a20 vldr s15, [r7, #128] @ 0x80 8001808: ee36 6a27 vadd.f32 s12, s12, s15 800180c: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001810: ee26 6a27 vmul.f32 s12, s12, s15 8001814: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5 8001818: edd7 7a22 vldr s15, [r7, #136] @ 0x88 800181c: ee75 5ae7 vsub.f32 s11, s11, s15 8001820: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 8001824: ee75 5ae7 vsub.f32 s11, s11, s15 8001828: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800182c: ee65 7aa7 vmul.f32 s15, s11, s15 8001830: ee36 6a27 vadd.f32 s12, s12, s15 8001834: edd7 7a00 vldr s15, [r7] 8001838: ee76 7a67 vsub.f32 s15, s12, s15 800183c: ee66 7aa7 vmul.f32 s15, s13, s15 8001840: ee77 7a27 vadd.f32 s15, s14, s15 8001844: edc7 7a13 vstr s15, [r7, #76] @ 0x4c recipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude 8001848: edd7 7a16 vldr s15, [r7, #88] @ 0x58 800184c: ee27 7aa7 vmul.f32 s14, s15, s15 8001850: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001854: ee67 7aa7 vmul.f32 s15, s15, s15 8001858: ee37 7a27 vadd.f32 s14, s14, s15 800185c: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001860: ee67 7aa7 vmul.f32 s15, s15, s15 8001864: ee37 7a27 vadd.f32 s14, s14, s15 8001868: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 800186c: ee67 7aa7 vmul.f32 s15, s15, s15 8001870: ee77 7a27 vadd.f32 s15, s14, s15 8001874: eeb0 0a67 vmov.f32 s0, s15 8001878: f000 fbf0 bl 800205c 800187c: ed87 0a31 vstr s0, [r7, #196] @ 0xc4 s0 *= recipNorm; 8001880: ed97 7a16 vldr s14, [r7, #88] @ 0x58 8001884: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001888: ee67 7a27 vmul.f32 s15, s14, s15 800188c: edc7 7a16 vstr s15, [r7, #88] @ 0x58 s1 *= recipNorm; 8001890: ed97 7a15 vldr s14, [r7, #84] @ 0x54 8001894: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001898: ee67 7a27 vmul.f32 s15, s14, s15 800189c: edc7 7a15 vstr s15, [r7, #84] @ 0x54 s2 *= recipNorm; 80018a0: ed97 7a14 vldr s14, [r7, #80] @ 0x50 80018a4: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 80018a8: ee67 7a27 vmul.f32 s15, s14, s15 80018ac: edc7 7a14 vstr s15, [r7, #80] @ 0x50 s3 *= recipNorm; 80018b0: ed97 7a13 vldr s14, [r7, #76] @ 0x4c 80018b4: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 80018b8: ee67 7a27 vmul.f32 s15, s14, s15 80018bc: edc7 7a13 vstr s15, [r7, #76] @ 0x4c // Apply feedback step qDot[0] -= filter->beta * s0; 80018c0: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 80018c4: 6a7b ldr r3, [r7, #36] @ 0x24 80018c6: edd3 6a04 vldr s13, [r3, #16] 80018ca: edd7 7a16 vldr s15, [r7, #88] @ 0x58 80018ce: ee66 7aa7 vmul.f32 s15, s13, s15 80018d2: ee77 7a67 vsub.f32 s15, s14, s15 80018d6: edc7 7a0b vstr s15, [r7, #44] @ 0x2c qDot[1] -= filter->beta * s1; 80018da: ed97 7a0c vldr s14, [r7, #48] @ 0x30 80018de: 6a7b ldr r3, [r7, #36] @ 0x24 80018e0: edd3 6a04 vldr s13, [r3, #16] 80018e4: edd7 7a15 vldr s15, [r7, #84] @ 0x54 80018e8: ee66 7aa7 vmul.f32 s15, s13, s15 80018ec: ee77 7a67 vsub.f32 s15, s14, s15 80018f0: edc7 7a0c vstr s15, [r7, #48] @ 0x30 qDot[2] -= filter->beta * s2; 80018f4: ed97 7a0d vldr s14, [r7, #52] @ 0x34 80018f8: 6a7b ldr r3, [r7, #36] @ 0x24 80018fa: edd3 6a04 vldr s13, [r3, #16] 80018fe: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001902: ee66 7aa7 vmul.f32 s15, s13, s15 8001906: ee77 7a67 vsub.f32 s15, s14, s15 800190a: edc7 7a0d vstr s15, [r7, #52] @ 0x34 qDot[3] -= filter->beta * s3; 800190e: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8001912: 6a7b ldr r3, [r7, #36] @ 0x24 8001914: edd3 6a04 vldr s13, [r3, #16] 8001918: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 800191c: ee66 7aa7 vmul.f32 s15, s13, s15 8001920: ee77 7a67 vsub.f32 s15, s14, s15 8001924: edc7 7a0e vstr s15, [r7, #56] @ 0x38 } // Integrate rate of change of quaternion to yield quaternion q[0] += qDot[0] * (1.0f / filter->sample_freq); 8001928: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 800192c: edd7 6a0b vldr s13, [r7, #44] @ 0x2c 8001930: 6a7b ldr r3, [r7, #36] @ 0x24 8001932: ed93 6a05 vldr s12, [r3, #20] 8001936: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 800193a: eec5 7a86 vdiv.f32 s15, s11, s12 800193e: ee66 7aa7 vmul.f32 s15, s13, s15 8001942: ee77 7a27 vadd.f32 s15, s14, s15 8001946: edc7 7a0f vstr s15, [r7, #60] @ 0x3c q[1] += qDot[1] * (1.0f / filter->sample_freq); 800194a: ed97 7a10 vldr s14, [r7, #64] @ 0x40 800194e: edd7 6a0c vldr s13, [r7, #48] @ 0x30 8001952: 6a7b ldr r3, [r7, #36] @ 0x24 8001954: ed93 6a05 vldr s12, [r3, #20] 8001958: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 800195c: eec5 7a86 vdiv.f32 s15, s11, s12 8001960: ee66 7aa7 vmul.f32 s15, s13, s15 8001964: ee77 7a27 vadd.f32 s15, s14, s15 8001968: edc7 7a10 vstr s15, [r7, #64] @ 0x40 q[2] += qDot[2] * (1.0f / filter->sample_freq); 800196c: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001970: edd7 6a0d vldr s13, [r7, #52] @ 0x34 8001974: 6a7b ldr r3, [r7, #36] @ 0x24 8001976: ed93 6a05 vldr s12, [r3, #20] 800197a: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 800197e: eec5 7a86 vdiv.f32 s15, s11, s12 8001982: ee66 7aa7 vmul.f32 s15, s13, s15 8001986: ee77 7a27 vadd.f32 s15, s14, s15 800198a: edc7 7a11 vstr s15, [r7, #68] @ 0x44 q[3] += qDot[3] * (1.0f / filter->sample_freq); 800198e: ed97 7a12 vldr s14, [r7, #72] @ 0x48 8001992: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8001996: 6a7b ldr r3, [r7, #36] @ 0x24 8001998: ed93 6a05 vldr s12, [r3, #20] 800199c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 80019a0: eec5 7a86 vdiv.f32 s15, s11, s12 80019a4: ee66 7aa7 vmul.f32 s15, s13, s15 80019a8: ee77 7a27 vadd.f32 s15, s14, s15 80019ac: edc7 7a12 vstr s15, [r7, #72] @ 0x48 // Normalise quaternion recipNorm = invSqrt(q[0] * q[0] + q[1] * q[1] + q[2] * q[2] + q[3] * q[3]); 80019b0: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 80019b4: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 80019b8: ee27 7a27 vmul.f32 s14, s14, s15 80019bc: edd7 6a10 vldr s13, [r7, #64] @ 0x40 80019c0: edd7 7a10 vldr s15, [r7, #64] @ 0x40 80019c4: ee66 7aa7 vmul.f32 s15, s13, s15 80019c8: ee37 7a27 vadd.f32 s14, s14, s15 80019cc: edd7 6a11 vldr s13, [r7, #68] @ 0x44 80019d0: edd7 7a11 vldr s15, [r7, #68] @ 0x44 80019d4: ee66 7aa7 vmul.f32 s15, s13, s15 80019d8: ee37 7a27 vadd.f32 s14, s14, s15 80019dc: edd7 6a12 vldr s13, [r7, #72] @ 0x48 80019e0: edd7 7a12 vldr s15, [r7, #72] @ 0x48 80019e4: ee66 7aa7 vmul.f32 s15, s13, s15 80019e8: ee77 7a27 vadd.f32 s15, s14, s15 80019ec: eeb0 0a67 vmov.f32 s0, s15 80019f0: f000 fb34 bl 800205c 80019f4: ed87 0a31 vstr s0, [r7, #196] @ 0xc4 q[0] *= recipNorm; 80019f8: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 80019fc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001a00: ee67 7a27 vmul.f32 s15, s14, s15 8001a04: edc7 7a0f vstr s15, [r7, #60] @ 0x3c q[1] *= recipNorm; 8001a08: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001a0c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001a10: ee67 7a27 vmul.f32 s15, s14, s15 8001a14: edc7 7a10 vstr s15, [r7, #64] @ 0x40 q[2] *= recipNorm; 8001a18: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001a1c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001a20: ee67 7a27 vmul.f32 s15, s14, s15 8001a24: edc7 7a11 vstr s15, [r7, #68] @ 0x44 q[3] *= recipNorm; 8001a28: ed97 7a12 vldr s14, [r7, #72] @ 0x48 8001a2c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001a30: ee67 7a27 vmul.f32 s15, s14, s15 8001a34: edc7 7a12 vstr s15, [r7, #72] @ 0x48 // Update filter state filter->q[0] = q[0]; 8001a38: 6bfa ldr r2, [r7, #60] @ 0x3c 8001a3a: 6a7b ldr r3, [r7, #36] @ 0x24 8001a3c: 601a str r2, [r3, #0] filter->q[1] = q[1]; 8001a3e: 6c3a ldr r2, [r7, #64] @ 0x40 8001a40: 6a7b ldr r3, [r7, #36] @ 0x24 8001a42: 605a str r2, [r3, #4] filter->q[2] = q[2]; 8001a44: 6c7a ldr r2, [r7, #68] @ 0x44 8001a46: 6a7b ldr r3, [r7, #36] @ 0x24 8001a48: 609a str r2, [r3, #8] filter->q[3] = q[3]; 8001a4a: 6cba ldr r2, [r7, #72] @ 0x48 8001a4c: 6a7b ldr r3, [r7, #36] @ 0x24 8001a4e: 60da str r2, [r3, #12] } 8001a50: 37c8 adds r7, #200 @ 0xc8 8001a52: 46bd mov sp, r7 8001a54: bd80 pop {r7, pc} 08001a56 : //--------------------------------------------------------------------------------------------------- // IMU algorithm update void MadgwickAHRS_update_IMU(MadgwickAHRS_Filter* filter, float gx, float gy, float gz, float ax, float ay, float az) { 8001a56: b580 push {r7, lr} 8001a58: b0a2 sub sp, #136 @ 0x88 8001a5a: af00 add r7, sp, #0 8001a5c: 61f8 str r0, [r7, #28] 8001a5e: ed87 0a06 vstr s0, [r7, #24] 8001a62: edc7 0a05 vstr s1, [r7, #20] 8001a66: ed87 1a04 vstr s2, [r7, #16] 8001a6a: edc7 1a03 vstr s3, [r7, #12] 8001a6e: ed87 2a02 vstr s4, [r7, #8] 8001a72: edc7 2a01 vstr s5, [r7, #4] float q[4] = {filter->q[0], filter->q[1], filter->q[2], filter->q[3]}; 8001a76: 69fb ldr r3, [r7, #28] 8001a78: 681b ldr r3, [r3, #0] 8001a7a: 633b str r3, [r7, #48] @ 0x30 8001a7c: 69fb ldr r3, [r7, #28] 8001a7e: 685b ldr r3, [r3, #4] 8001a80: 637b str r3, [r7, #52] @ 0x34 8001a82: 69fb ldr r3, [r7, #28] 8001a84: 689b ldr r3, [r3, #8] 8001a86: 63bb str r3, [r7, #56] @ 0x38 8001a88: 69fb ldr r3, [r7, #28] 8001a8a: 68db ldr r3, [r3, #12] 8001a8c: 63fb str r3, [r7, #60] @ 0x3c float s0, s1, s2, s3; float qDot[4]; float _2q0, _2q1, _2q2, _2q3, _4q0, _4q1, _4q2 ,_8q1, _8q2, q0q0, q1q1, q2q2, q3q3; // Rate of change of quaternion from gyroscope qDot[0] = 0.5f * (-q[1] * gx - q[2] * gy - q[3] * gz); 8001a8e: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001a92: eeb1 7a67 vneg.f32 s14, s15 8001a96: edd7 7a06 vldr s15, [r7, #24] 8001a9a: ee27 7a27 vmul.f32 s14, s14, s15 8001a9e: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8001aa2: edd7 7a05 vldr s15, [r7, #20] 8001aa6: ee66 7aa7 vmul.f32 s15, s13, s15 8001aaa: ee37 7a67 vsub.f32 s14, s14, s15 8001aae: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001ab2: edd7 7a04 vldr s15, [r7, #16] 8001ab6: ee66 7aa7 vmul.f32 s15, s13, s15 8001aba: ee77 7a67 vsub.f32 s15, s14, s15 8001abe: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8001ac2: ee67 7a87 vmul.f32 s15, s15, s14 8001ac6: edc7 7a08 vstr s15, [r7, #32] qDot[1] = 0.5f * (q[0] * gx + q[2] * gz - q[3] * gy); 8001aca: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8001ace: edd7 7a06 vldr s15, [r7, #24] 8001ad2: ee27 7a27 vmul.f32 s14, s14, s15 8001ad6: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8001ada: edd7 7a04 vldr s15, [r7, #16] 8001ade: ee66 7aa7 vmul.f32 s15, s13, s15 8001ae2: ee37 7a27 vadd.f32 s14, s14, s15 8001ae6: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001aea: edd7 7a05 vldr s15, [r7, #20] 8001aee: ee66 7aa7 vmul.f32 s15, s13, s15 8001af2: ee77 7a67 vsub.f32 s15, s14, s15 8001af6: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8001afa: ee67 7a87 vmul.f32 s15, s15, s14 8001afe: edc7 7a09 vstr s15, [r7, #36] @ 0x24 qDot[2] = 0.5f * (q[0] * gy - q[1] * gz + q[3] * gx); 8001b02: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8001b06: edd7 7a05 vldr s15, [r7, #20] 8001b0a: ee27 7a27 vmul.f32 s14, s14, s15 8001b0e: edd7 6a0d vldr s13, [r7, #52] @ 0x34 8001b12: edd7 7a04 vldr s15, [r7, #16] 8001b16: ee66 7aa7 vmul.f32 s15, s13, s15 8001b1a: ee37 7a67 vsub.f32 s14, s14, s15 8001b1e: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001b22: edd7 7a06 vldr s15, [r7, #24] 8001b26: ee66 7aa7 vmul.f32 s15, s13, s15 8001b2a: ee77 7a27 vadd.f32 s15, s14, s15 8001b2e: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8001b32: ee67 7a87 vmul.f32 s15, s15, s14 8001b36: edc7 7a0a vstr s15, [r7, #40] @ 0x28 qDot[3] = 0.5f * (q[0] * gz + q[1] * gy - q[2] * gx); 8001b3a: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8001b3e: edd7 7a04 vldr s15, [r7, #16] 8001b42: ee27 7a27 vmul.f32 s14, s14, s15 8001b46: edd7 6a0d vldr s13, [r7, #52] @ 0x34 8001b4a: edd7 7a05 vldr s15, [r7, #20] 8001b4e: ee66 7aa7 vmul.f32 s15, s13, s15 8001b52: ee37 7a27 vadd.f32 s14, s14, s15 8001b56: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8001b5a: edd7 7a06 vldr s15, [r7, #24] 8001b5e: ee66 7aa7 vmul.f32 s15, s13, s15 8001b62: ee77 7a67 vsub.f32 s15, s14, s15 8001b66: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8001b6a: ee67 7a87 vmul.f32 s15, s15, s14 8001b6e: edc7 7a0b vstr s15, [r7, #44] @ 0x2c // Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation) if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) { 8001b72: edd7 7a03 vldr s15, [r7, #12] 8001b76: eef5 7a40 vcmp.f32 s15, #0.0 8001b7a: eef1 fa10 vmrs APSR_nzcv, fpscr 8001b7e: d10e bne.n 8001b9e 8001b80: edd7 7a02 vldr s15, [r7, #8] 8001b84: eef5 7a40 vcmp.f32 s15, #0.0 8001b88: eef1 fa10 vmrs APSR_nzcv, fpscr 8001b8c: d107 bne.n 8001b9e 8001b8e: edd7 7a01 vldr s15, [r7, #4] 8001b92: eef5 7a40 vcmp.f32 s15, #0.0 8001b96: eef1 fa10 vmrs APSR_nzcv, fpscr 8001b9a: f000 81c6 beq.w 8001f2a // Normalise accelerometer measurement recipNorm = invSqrt(ax * ax + ay * ay + az * az); 8001b9e: edd7 7a03 vldr s15, [r7, #12] 8001ba2: ee27 7aa7 vmul.f32 s14, s15, s15 8001ba6: edd7 7a02 vldr s15, [r7, #8] 8001baa: ee67 7aa7 vmul.f32 s15, s15, s15 8001bae: ee37 7a27 vadd.f32 s14, s14, s15 8001bb2: edd7 7a01 vldr s15, [r7, #4] 8001bb6: ee67 7aa7 vmul.f32 s15, s15, s15 8001bba: ee77 7a27 vadd.f32 s15, s14, s15 8001bbe: eeb0 0a67 vmov.f32 s0, s15 8001bc2: f000 fa4b bl 800205c 8001bc6: ed87 0a21 vstr s0, [r7, #132] @ 0x84 ax *= recipNorm; 8001bca: ed97 7a03 vldr s14, [r7, #12] 8001bce: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8001bd2: ee67 7a27 vmul.f32 s15, s14, s15 8001bd6: edc7 7a03 vstr s15, [r7, #12] ay *= recipNorm; 8001bda: ed97 7a02 vldr s14, [r7, #8] 8001bde: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8001be2: ee67 7a27 vmul.f32 s15, s14, s15 8001be6: edc7 7a02 vstr s15, [r7, #8] az *= recipNorm; 8001bea: ed97 7a01 vldr s14, [r7, #4] 8001bee: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8001bf2: ee67 7a27 vmul.f32 s15, s14, s15 8001bf6: edc7 7a01 vstr s15, [r7, #4] // Auxiliary variables to avoid repeated arithmetic _2q0 = 2.0f * q[0]; 8001bfa: edd7 7a0c vldr s15, [r7, #48] @ 0x30 8001bfe: ee77 7aa7 vadd.f32 s15, s15, s15 8001c02: edc7 7a20 vstr s15, [r7, #128] @ 0x80 _2q1 = 2.0f * q[1]; 8001c06: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001c0a: ee77 7aa7 vadd.f32 s15, s15, s15 8001c0e: edc7 7a1f vstr s15, [r7, #124] @ 0x7c _2q2 = 2.0f * q[2]; 8001c12: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001c16: ee77 7aa7 vadd.f32 s15, s15, s15 8001c1a: edc7 7a1e vstr s15, [r7, #120] @ 0x78 _2q3 = 2.0f * q[3]; 8001c1e: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001c22: ee77 7aa7 vadd.f32 s15, s15, s15 8001c26: edc7 7a1d vstr s15, [r7, #116] @ 0x74 _4q0 = 4.0f * q[0]; 8001c2a: edd7 7a0c vldr s15, [r7, #48] @ 0x30 8001c2e: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001c32: ee67 7a87 vmul.f32 s15, s15, s14 8001c36: edc7 7a1c vstr s15, [r7, #112] @ 0x70 _4q1 = 4.0f * q[1]; 8001c3a: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001c3e: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001c42: ee67 7a87 vmul.f32 s15, s15, s14 8001c46: edc7 7a1b vstr s15, [r7, #108] @ 0x6c _4q2 = 4.0f * q[2]; 8001c4a: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001c4e: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001c52: ee67 7a87 vmul.f32 s15, s15, s14 8001c56: edc7 7a1a vstr s15, [r7, #104] @ 0x68 _8q1 = 8.0f * q[1]; 8001c5a: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001c5e: eeb2 7a00 vmov.f32 s14, #32 @ 0x41000000 8.0 8001c62: ee67 7a87 vmul.f32 s15, s15, s14 8001c66: edc7 7a19 vstr s15, [r7, #100] @ 0x64 _8q2 = 8.0f * q[2]; 8001c6a: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001c6e: eeb2 7a00 vmov.f32 s14, #32 @ 0x41000000 8.0 8001c72: ee67 7a87 vmul.f32 s15, s15, s14 8001c76: edc7 7a18 vstr s15, [r7, #96] @ 0x60 q0q0 = q[0] * q[0]; 8001c7a: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8001c7e: edd7 7a0c vldr s15, [r7, #48] @ 0x30 8001c82: ee67 7a27 vmul.f32 s15, s14, s15 8001c86: edc7 7a17 vstr s15, [r7, #92] @ 0x5c q1q1 = q[1] * q[1]; 8001c8a: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8001c8e: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001c92: ee67 7a27 vmul.f32 s15, s14, s15 8001c96: edc7 7a16 vstr s15, [r7, #88] @ 0x58 q2q2 = q[2] * q[2]; 8001c9a: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8001c9e: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001ca2: ee67 7a27 vmul.f32 s15, s14, s15 8001ca6: edc7 7a15 vstr s15, [r7, #84] @ 0x54 q3q3 = q[3] * q[3]; 8001caa: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001cae: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001cb2: ee67 7a27 vmul.f32 s15, s14, s15 8001cb6: edc7 7a14 vstr s15, [r7, #80] @ 0x50 // Gradient decent algorithm corrective step s0 = _4q0 * q2q2 + _2q2 * ax + _4q0 * q1q1 - _2q1 * ay; 8001cba: ed97 7a1c vldr s14, [r7, #112] @ 0x70 8001cbe: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001cc2: ee27 7a27 vmul.f32 s14, s14, s15 8001cc6: edd7 6a1e vldr s13, [r7, #120] @ 0x78 8001cca: edd7 7a03 vldr s15, [r7, #12] 8001cce: ee66 7aa7 vmul.f32 s15, s13, s15 8001cd2: ee37 7a27 vadd.f32 s14, s14, s15 8001cd6: edd7 6a1c vldr s13, [r7, #112] @ 0x70 8001cda: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8001cde: ee66 7aa7 vmul.f32 s15, s13, s15 8001ce2: ee37 7a27 vadd.f32 s14, s14, s15 8001ce6: edd7 6a1f vldr s13, [r7, #124] @ 0x7c 8001cea: edd7 7a02 vldr s15, [r7, #8] 8001cee: ee66 7aa7 vmul.f32 s15, s13, s15 8001cf2: ee77 7a67 vsub.f32 s15, s14, s15 8001cf6: edc7 7a13 vstr s15, [r7, #76] @ 0x4c s1 = _4q1 * q3q3 - _2q3 * ax + 4.0f * q0q0 * q[1] - _2q0 * ay - _4q1 + _8q1 * q1q1 + _8q1 * q2q2 + _4q1 * az; 8001cfa: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8001cfe: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001d02: ee27 7a27 vmul.f32 s14, s14, s15 8001d06: edd7 6a1d vldr s13, [r7, #116] @ 0x74 8001d0a: edd7 7a03 vldr s15, [r7, #12] 8001d0e: ee66 7aa7 vmul.f32 s15, s13, s15 8001d12: ee37 7a67 vsub.f32 s14, s14, s15 8001d16: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8001d1a: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0 8001d1e: ee67 6aa6 vmul.f32 s13, s15, s13 8001d22: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001d26: ee66 7aa7 vmul.f32 s15, s13, s15 8001d2a: ee37 7a27 vadd.f32 s14, s14, s15 8001d2e: edd7 6a20 vldr s13, [r7, #128] @ 0x80 8001d32: edd7 7a02 vldr s15, [r7, #8] 8001d36: ee66 7aa7 vmul.f32 s15, s13, s15 8001d3a: ee37 7a67 vsub.f32 s14, s14, s15 8001d3e: edd7 7a1b vldr s15, [r7, #108] @ 0x6c 8001d42: ee37 7a67 vsub.f32 s14, s14, s15 8001d46: edd7 6a19 vldr s13, [r7, #100] @ 0x64 8001d4a: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8001d4e: ee66 7aa7 vmul.f32 s15, s13, s15 8001d52: ee37 7a27 vadd.f32 s14, s14, s15 8001d56: edd7 6a19 vldr s13, [r7, #100] @ 0x64 8001d5a: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001d5e: ee66 7aa7 vmul.f32 s15, s13, s15 8001d62: ee37 7a27 vadd.f32 s14, s14, s15 8001d66: edd7 6a1b vldr s13, [r7, #108] @ 0x6c 8001d6a: edd7 7a01 vldr s15, [r7, #4] 8001d6e: ee66 7aa7 vmul.f32 s15, s13, s15 8001d72: ee77 7a27 vadd.f32 s15, s14, s15 8001d76: edc7 7a12 vstr s15, [r7, #72] @ 0x48 s2 = 4.0f * q0q0 * q[2] + _2q0 * ax + _4q2 * q3q3 - _2q3 * ay - _4q2 + _8q2 * q1q1 + _8q2 * q2q2 + _4q2 * az; 8001d7a: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8001d7e: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001d82: ee27 7a87 vmul.f32 s14, s15, s14 8001d86: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001d8a: ee27 7a27 vmul.f32 s14, s14, s15 8001d8e: edd7 6a20 vldr s13, [r7, #128] @ 0x80 8001d92: edd7 7a03 vldr s15, [r7, #12] 8001d96: ee66 7aa7 vmul.f32 s15, s13, s15 8001d9a: ee37 7a27 vadd.f32 s14, s14, s15 8001d9e: edd7 6a1a vldr s13, [r7, #104] @ 0x68 8001da2: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001da6: ee66 7aa7 vmul.f32 s15, s13, s15 8001daa: ee37 7a27 vadd.f32 s14, s14, s15 8001dae: edd7 6a1d vldr s13, [r7, #116] @ 0x74 8001db2: edd7 7a02 vldr s15, [r7, #8] 8001db6: ee66 7aa7 vmul.f32 s15, s13, s15 8001dba: ee37 7a67 vsub.f32 s14, s14, s15 8001dbe: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001dc2: ee37 7a67 vsub.f32 s14, s14, s15 8001dc6: edd7 6a18 vldr s13, [r7, #96] @ 0x60 8001dca: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8001dce: ee66 7aa7 vmul.f32 s15, s13, s15 8001dd2: ee37 7a27 vadd.f32 s14, s14, s15 8001dd6: edd7 6a18 vldr s13, [r7, #96] @ 0x60 8001dda: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001dde: ee66 7aa7 vmul.f32 s15, s13, s15 8001de2: ee37 7a27 vadd.f32 s14, s14, s15 8001de6: edd7 6a1a vldr s13, [r7, #104] @ 0x68 8001dea: edd7 7a01 vldr s15, [r7, #4] 8001dee: ee66 7aa7 vmul.f32 s15, s13, s15 8001df2: ee77 7a27 vadd.f32 s15, s14, s15 8001df6: edc7 7a11 vstr s15, [r7, #68] @ 0x44 s3 = 4.0f * q1q1 * q[3] - _2q1 * ax + 4.0f * q2q2 * q[3] - _2q2 * ay; 8001dfa: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8001dfe: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001e02: ee27 7a87 vmul.f32 s14, s15, s14 8001e06: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001e0a: ee27 7a27 vmul.f32 s14, s14, s15 8001e0e: edd7 6a1f vldr s13, [r7, #124] @ 0x7c 8001e12: edd7 7a03 vldr s15, [r7, #12] 8001e16: ee66 7aa7 vmul.f32 s15, s13, s15 8001e1a: ee37 7a67 vsub.f32 s14, s14, s15 8001e1e: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001e22: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0 8001e26: ee67 6aa6 vmul.f32 s13, s15, s13 8001e2a: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001e2e: ee66 7aa7 vmul.f32 s15, s13, s15 8001e32: ee37 7a27 vadd.f32 s14, s14, s15 8001e36: edd7 6a1e vldr s13, [r7, #120] @ 0x78 8001e3a: edd7 7a02 vldr s15, [r7, #8] 8001e3e: ee66 7aa7 vmul.f32 s15, s13, s15 8001e42: ee77 7a67 vsub.f32 s15, s14, s15 8001e46: edc7 7a10 vstr s15, [r7, #64] @ 0x40 recipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude 8001e4a: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 8001e4e: ee27 7aa7 vmul.f32 s14, s15, s15 8001e52: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001e56: ee67 7aa7 vmul.f32 s15, s15, s15 8001e5a: ee37 7a27 vadd.f32 s14, s14, s15 8001e5e: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001e62: ee67 7aa7 vmul.f32 s15, s15, s15 8001e66: ee37 7a27 vadd.f32 s14, s14, s15 8001e6a: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001e6e: ee67 7aa7 vmul.f32 s15, s15, s15 8001e72: ee77 7a27 vadd.f32 s15, s14, s15 8001e76: eeb0 0a67 vmov.f32 s0, s15 8001e7a: f000 f8ef bl 800205c 8001e7e: ed87 0a21 vstr s0, [r7, #132] @ 0x84 s0 *= recipNorm; 8001e82: ed97 7a13 vldr s14, [r7, #76] @ 0x4c 8001e86: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8001e8a: ee67 7a27 vmul.f32 s15, s14, s15 8001e8e: edc7 7a13 vstr s15, [r7, #76] @ 0x4c s1 *= recipNorm; 8001e92: ed97 7a12 vldr s14, [r7, #72] @ 0x48 8001e96: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8001e9a: ee67 7a27 vmul.f32 s15, s14, s15 8001e9e: edc7 7a12 vstr s15, [r7, #72] @ 0x48 s2 *= recipNorm; 8001ea2: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001ea6: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8001eaa: ee67 7a27 vmul.f32 s15, s14, s15 8001eae: edc7 7a11 vstr s15, [r7, #68] @ 0x44 s3 *= recipNorm; 8001eb2: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001eb6: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8001eba: ee67 7a27 vmul.f32 s15, s14, s15 8001ebe: edc7 7a10 vstr s15, [r7, #64] @ 0x40 // Apply feedback step qDot[0] -= filter->beta * s0; 8001ec2: ed97 7a08 vldr s14, [r7, #32] 8001ec6: 69fb ldr r3, [r7, #28] 8001ec8: edd3 6a04 vldr s13, [r3, #16] 8001ecc: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 8001ed0: ee66 7aa7 vmul.f32 s15, s13, s15 8001ed4: ee77 7a67 vsub.f32 s15, s14, s15 8001ed8: edc7 7a08 vstr s15, [r7, #32] qDot[1] -= filter->beta * s1; 8001edc: ed97 7a09 vldr s14, [r7, #36] @ 0x24 8001ee0: 69fb ldr r3, [r7, #28] 8001ee2: edd3 6a04 vldr s13, [r3, #16] 8001ee6: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001eea: ee66 7aa7 vmul.f32 s15, s13, s15 8001eee: ee77 7a67 vsub.f32 s15, s14, s15 8001ef2: edc7 7a09 vstr s15, [r7, #36] @ 0x24 qDot[2] -= filter->beta * s2; 8001ef6: ed97 7a0a vldr s14, [r7, #40] @ 0x28 8001efa: 69fb ldr r3, [r7, #28] 8001efc: edd3 6a04 vldr s13, [r3, #16] 8001f00: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001f04: ee66 7aa7 vmul.f32 s15, s13, s15 8001f08: ee77 7a67 vsub.f32 s15, s14, s15 8001f0c: edc7 7a0a vstr s15, [r7, #40] @ 0x28 qDot[3] -= filter->beta * s3; 8001f10: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 8001f14: 69fb ldr r3, [r7, #28] 8001f16: edd3 6a04 vldr s13, [r3, #16] 8001f1a: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001f1e: ee66 7aa7 vmul.f32 s15, s13, s15 8001f22: ee77 7a67 vsub.f32 s15, s14, s15 8001f26: edc7 7a0b vstr s15, [r7, #44] @ 0x2c } // Integrate rate of change of quaternion to yield quaternion q[0] += qDot[0] * (1.0f / filter->sample_freq); 8001f2a: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8001f2e: edd7 6a08 vldr s13, [r7, #32] 8001f32: 69fb ldr r3, [r7, #28] 8001f34: ed93 6a05 vldr s12, [r3, #20] 8001f38: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8001f3c: eec5 7a86 vdiv.f32 s15, s11, s12 8001f40: ee66 7aa7 vmul.f32 s15, s13, s15 8001f44: ee77 7a27 vadd.f32 s15, s14, s15 8001f48: edc7 7a0c vstr s15, [r7, #48] @ 0x30 q[1] += qDot[1] * (1.0f / filter->sample_freq); 8001f4c: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8001f50: edd7 6a09 vldr s13, [r7, #36] @ 0x24 8001f54: 69fb ldr r3, [r7, #28] 8001f56: ed93 6a05 vldr s12, [r3, #20] 8001f5a: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8001f5e: eec5 7a86 vdiv.f32 s15, s11, s12 8001f62: ee66 7aa7 vmul.f32 s15, s13, s15 8001f66: ee77 7a27 vadd.f32 s15, s14, s15 8001f6a: edc7 7a0d vstr s15, [r7, #52] @ 0x34 q[2] += qDot[2] * (1.0f / filter->sample_freq); 8001f6e: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8001f72: edd7 6a0a vldr s13, [r7, #40] @ 0x28 8001f76: 69fb ldr r3, [r7, #28] 8001f78: ed93 6a05 vldr s12, [r3, #20] 8001f7c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8001f80: eec5 7a86 vdiv.f32 s15, s11, s12 8001f84: ee66 7aa7 vmul.f32 s15, s13, s15 8001f88: ee77 7a27 vadd.f32 s15, s14, s15 8001f8c: edc7 7a0e vstr s15, [r7, #56] @ 0x38 q[3] += qDot[3] * (1.0f / filter->sample_freq); 8001f90: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001f94: edd7 6a0b vldr s13, [r7, #44] @ 0x2c 8001f98: 69fb ldr r3, [r7, #28] 8001f9a: ed93 6a05 vldr s12, [r3, #20] 8001f9e: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8001fa2: eec5 7a86 vdiv.f32 s15, s11, s12 8001fa6: ee66 7aa7 vmul.f32 s15, s13, s15 8001faa: ee77 7a27 vadd.f32 s15, s14, s15 8001fae: edc7 7a0f vstr s15, [r7, #60] @ 0x3c // Normalise quaternion recipNorm = invSqrt(q[0] * q[0] + q[1] * q[1] + q[2] * q[2] + q[3] * q[3]); 8001fb2: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8001fb6: edd7 7a0c vldr s15, [r7, #48] @ 0x30 8001fba: ee27 7a27 vmul.f32 s14, s14, s15 8001fbe: edd7 6a0d vldr s13, [r7, #52] @ 0x34 8001fc2: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001fc6: ee66 7aa7 vmul.f32 s15, s13, s15 8001fca: ee37 7a27 vadd.f32 s14, s14, s15 8001fce: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8001fd2: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001fd6: ee66 7aa7 vmul.f32 s15, s13, s15 8001fda: ee37 7a27 vadd.f32 s14, s14, s15 8001fde: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001fe2: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001fe6: ee66 7aa7 vmul.f32 s15, s13, s15 8001fea: ee77 7a27 vadd.f32 s15, s14, s15 8001fee: eeb0 0a67 vmov.f32 s0, s15 8001ff2: f000 f833 bl 800205c 8001ff6: ed87 0a21 vstr s0, [r7, #132] @ 0x84 q[0] *= recipNorm; 8001ffa: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8001ffe: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8002002: ee67 7a27 vmul.f32 s15, s14, s15 8002006: edc7 7a0c vstr s15, [r7, #48] @ 0x30 q[1] *= recipNorm; 800200a: ed97 7a0d vldr s14, [r7, #52] @ 0x34 800200e: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8002012: ee67 7a27 vmul.f32 s15, s14, s15 8002016: edc7 7a0d vstr s15, [r7, #52] @ 0x34 q[2] *= recipNorm; 800201a: ed97 7a0e vldr s14, [r7, #56] @ 0x38 800201e: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8002022: ee67 7a27 vmul.f32 s15, s14, s15 8002026: edc7 7a0e vstr s15, [r7, #56] @ 0x38 q[3] *= recipNorm; 800202a: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 800202e: edd7 7a21 vldr s15, [r7, #132] @ 0x84 8002032: ee67 7a27 vmul.f32 s15, s14, s15 8002036: edc7 7a0f vstr s15, [r7, #60] @ 0x3c // Update filter state filter->q[0] = q[0]; 800203a: 6b3a ldr r2, [r7, #48] @ 0x30 800203c: 69fb ldr r3, [r7, #28] 800203e: 601a str r2, [r3, #0] filter->q[1] = q[1]; 8002040: 6b7a ldr r2, [r7, #52] @ 0x34 8002042: 69fb ldr r3, [r7, #28] 8002044: 605a str r2, [r3, #4] filter->q[2] = q[2]; 8002046: 6bba ldr r2, [r7, #56] @ 0x38 8002048: 69fb ldr r3, [r7, #28] 800204a: 609a str r2, [r3, #8] filter->q[3] = q[3]; 800204c: 6bfa ldr r2, [r7, #60] @ 0x3c 800204e: 69fb ldr r3, [r7, #28] 8002050: 60da str r2, [r3, #12] } 8002052: bf00 nop 8002054: 3788 adds r7, #136 @ 0x88 8002056: 46bd mov sp, r7 8002058: bd80 pop {r7, pc} ... 0800205c : //--------------------------------------------------------------------------------------------------- // Fast inverse square-root // See: http://en.wikipedia.org/wiki/Fast_inverse_square_root float invSqrt(float x) { 800205c: b480 push {r7} 800205e: b087 sub sp, #28 8002060: af00 add r7, sp, #0 8002062: ed87 0a01 vstr s0, [r7, #4] float halfx = 0.5f * x; 8002066: edd7 7a01 vldr s15, [r7, #4] 800206a: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 800206e: ee67 7a87 vmul.f32 s15, s15, s14 8002072: edc7 7a05 vstr s15, [r7, #20] float y = x; 8002076: 687b ldr r3, [r7, #4] 8002078: 613b str r3, [r7, #16] long i = *(long*)&y; 800207a: f107 0310 add.w r3, r7, #16 800207e: 681b ldr r3, [r3, #0] 8002080: 60fb str r3, [r7, #12] i = 0x5f3759df - (i>>1); 8002082: 68fb ldr r3, [r7, #12] 8002084: 105a asrs r2, r3, #1 8002086: 4b12 ldr r3, [pc, #72] @ (80020d0 ) 8002088: 1a9b subs r3, r3, r2 800208a: 60fb str r3, [r7, #12] y = *(float*)&i; 800208c: f107 030c add.w r3, r7, #12 8002090: 681b ldr r3, [r3, #0] 8002092: 613b str r3, [r7, #16] y = y * (1.5f - (halfx * y * y)); 8002094: ed97 7a04 vldr s14, [r7, #16] 8002098: edd7 7a05 vldr s15, [r7, #20] 800209c: ee27 7a27 vmul.f32 s14, s14, s15 80020a0: edd7 7a04 vldr s15, [r7, #16] 80020a4: ee67 7a27 vmul.f32 s15, s14, s15 80020a8: eeb7 7a08 vmov.f32 s14, #120 @ 0x3fc00000 1.5 80020ac: ee37 7a67 vsub.f32 s14, s14, s15 80020b0: edd7 7a04 vldr s15, [r7, #16] 80020b4: ee67 7a27 vmul.f32 s15, s14, s15 80020b8: edc7 7a04 vstr s15, [r7, #16] return y; 80020bc: 693b ldr r3, [r7, #16] 80020be: ee07 3a90 vmov s15, r3 } 80020c2: eeb0 0a67 vmov.f32 s0, s15 80020c6: 371c adds r7, #28 80020c8: 46bd mov sp, r7 80020ca: f85d 7b04 ldr.w r7, [sp], #4 80020ce: 4770 bx lr 80020d0: 5f3759df .word 0x5f3759df 080020d4 : /* USER CODE END APPD_Init */ return; } void APPD_EnableCPU2( void ) { 80020d4: b5b0 push {r4, r5, r7, lr} 80020d6: b088 sub sp, #32 80020d8: af00 add r7, sp, #0 /* USER CODE BEGIN APPD_EnableCPU2 */ SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket = 80020da: 4b0b ldr r3, [pc, #44] @ (8002108 ) 80020dc: 1d3c adds r4, r7, #4 80020de: 461d mov r5, r3 80020e0: cd0f ldmia r5!, {r0, r1, r2, r3} 80020e2: c40f stmia r4!, {r0, r1, r2, r3} 80020e4: e895 0007 ldmia.w r5, {r0, r1, r2} 80020e8: c403 stmia r4!, {r0, r1} 80020ea: 8022 strh r2, [r4, #0] 80020ec: 3402 adds r4, #2 80020ee: 0c13 lsrs r3, r2, #16 80020f0: 7023 strb r3, [r4, #0] NBR_OF_TRACES_CONFIG_PARAMETERS, NBR_OF_GENERAL_CONFIG_PARAMETERS} }; /**< Traces channel initialization */ TL_TRACES_Init( ); 80020f2: f010 fd0d bl 8012b10 /** GPIO DEBUG Initialization */ SHCI_C2_DEBUG_Init( &DebugCmdPacket ); 80020f6: 1d3b adds r3, r7, #4 80020f8: 4618 mov r0, r3 80020fa: f010 f986 bl 801240a /* USER CODE END APPD_EnableCPU2 */ return; 80020fe: bf00 nop } 8002100: 3720 adds r7, #32 8002102: 46bd mov sp, r7 8002104: bdb0 pop {r4, r5, r7, pc} 8002106: bf00 nop 8002108: 0801d428 .word 0x0801d428 0800210c : * * (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx * @retval None */ __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode) { 800210c: b480 push {r7} 800210e: b083 sub sp, #12 8002110: af00 add r7, sp, #0 8002112: 6078 str r0, [r7, #4] MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode); 8002114: 4b07 ldr r3, [pc, #28] @ (8002134 ) 8002116: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800211a: f023 0207 bic.w r2, r3, #7 800211e: 4905 ldr r1, [pc, #20] @ (8002134 ) 8002120: 687b ldr r3, [r7, #4] 8002122: 4313 orrs r3, r2 8002124: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } 8002128: bf00 nop 800212a: 370c adds r7, #12 800212c: 46bd mov sp, r7 800212e: f85d 7b04 ldr.w r7, [sp], #4 8002132: 4770 bx lr 8002134: 58000400 .word 0x58000400 08002138 : * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) { 8002138: b480 push {r7} 800213a: b083 sub sp, #12 800213c: af00 add r7, sp, #0 800213e: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR2, ExtiLine); 8002140: 4b06 ldr r3, [pc, #24] @ (800215c ) 8002142: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 8002146: 4905 ldr r1, [pc, #20] @ (800215c ) 8002148: 687b ldr r3, [r7, #4] 800214a: 4313 orrs r3, r2 800214c: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 8002150: bf00 nop 8002152: 370c adds r7, #12 8002154: 46bd mov sp, r7 8002156: f85d 7b04 ldr.w r7, [sp], #4 800215a: 4770 bx lr 800215c: 58000800 .word 0x58000800 08002160 : * @rmtoll HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning * @param Value Between Min_Data = 0 and Max_Data = 63 * @retval None */ __STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value) { 8002160: b480 push {r7} 8002162: b083 sub sp, #12 8002164: af00 add r7, sp, #0 8002166: 6078 str r0, [r7, #4] WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY); 8002168: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800216c: 4a0a ldr r2, [pc, #40] @ (8002198 ) 800216e: f8c3 209c str.w r2, [r3, #156] @ 0x9c MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos); 8002172: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002176: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800217a: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800217e: 687b ldr r3, [r7, #4] 8002180: 021b lsls r3, r3, #8 8002182: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002186: 4313 orrs r3, r2 8002188: f8c1 309c str.w r3, [r1, #156] @ 0x9c } 800218c: bf00 nop 800218e: 370c adds r7, #12 8002190: 46bd mov sp, r7 8002192: f85d 7b04 ldr.w r7, [sp], #4 8002196: 4770 bx lr 8002198: cafecafe .word 0xcafecafe 0800219c : * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI * @retval None */ __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) { 800219c: b480 push {r7} 800219e: b083 sub sp, #12 80021a0: af00 add r7, sp, #0 80021a2: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); 80021a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80021a8: 689b ldr r3, [r3, #8] 80021aa: f423 4200 bic.w r2, r3, #32768 @ 0x8000 80021ae: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80021b2: 687b ldr r3, [r7, #4] 80021b4: 4313 orrs r3, r2 80021b6: 608b str r3, [r1, #8] } 80021b8: bf00 nop 80021ba: 370c adds r7, #12 80021bc: 46bd mov sp, r7 80021be: f85d 7b04 ldr.w r7, [sp], #4 80021c2: 4770 bx lr 080021c4 : * @note For STM32WBxxxx devices, the device ID is 0x495 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID * @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495) */ __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) { 80021c4: b480 push {r7} 80021c6: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); 80021c8: 4b04 ldr r3, [pc, #16] @ (80021dc ) 80021ca: 681b ldr r3, [r3, #0] 80021cc: f3c3 030b ubfx r3, r3, #0, #12 } 80021d0: 4618 mov r0, r3 80021d2: 46bd mov sp, r7 80021d4: f85d 7b04 ldr.w r7, [sp], #4 80021d8: 4770 bx lr 80021da: bf00 nop 80021dc: e0042000 .word 0xe0042000 080021e0 : * @note This field indicates the revision of the device. * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF */ __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) { 80021e0: b480 push {r7} 80021e2: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); 80021e4: 4b04 ldr r3, [pc, #16] @ (80021f8 ) 80021e6: 681b ldr r3, [r3, #0] 80021e8: 0c1b lsrs r3, r3, #16 80021ea: b29b uxth r3, r3 } 80021ec: 4618 mov r0, r3 80021ee: 46bd mov sp, r7 80021f0: f85d 7b04 ldr.w r7, [sp], #4 80021f4: 4770 bx lr 80021f6: bf00 nop 80021f8: e0042000 .word 0xe0042000 080021fc : * @rmtoll WPR KEY LL_RTC_EnableWriteProtection * @param RTCx RTC Instance * @retval None */ __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) { 80021fc: b480 push {r7} 80021fe: b083 sub sp, #12 8002200: af00 add r7, sp, #0 8002202: 6078 str r0, [r7, #4] WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); 8002204: 687b ldr r3, [r7, #4] 8002206: 22ff movs r2, #255 @ 0xff 8002208: 625a str r2, [r3, #36] @ 0x24 } 800220a: bf00 nop 800220c: 370c adds r7, #12 800220e: 46bd mov sp, r7 8002210: f85d 7b04 ldr.w r7, [sp], #4 8002214: 4770 bx lr 08002216 : * @rmtoll WPR KEY LL_RTC_DisableWriteProtection * @param RTCx RTC Instance * @retval None */ __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) { 8002216: b480 push {r7} 8002218: b083 sub sp, #12 800221a: af00 add r7, sp, #0 800221c: 6078 str r0, [r7, #4] WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); 800221e: 687b ldr r3, [r7, #4] 8002220: 22ca movs r2, #202 @ 0xca 8002222: 625a str r2, [r3, #36] @ 0x24 WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); 8002224: 687b ldr r3, [r7, #4] 8002226: 2253 movs r2, #83 @ 0x53 8002228: 625a str r2, [r3, #36] @ 0x24 } 800222a: bf00 nop 800222c: 370c adds r7, #12 800222e: 46bd mov sp, r7 8002230: f85d 7b04 ldr.w r7, [sp], #4 8002234: 4770 bx lr 08002236 : * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT * @retval None */ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) { 8002236: b480 push {r7} 8002238: b083 sub sp, #12 800223a: af00 add r7, sp, #0 800223c: 6078 str r0, [r7, #4] 800223e: 6039 str r1, [r7, #0] MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); 8002240: 687b ldr r3, [r7, #4] 8002242: 689b ldr r3, [r3, #8] 8002244: f023 0207 bic.w r2, r3, #7 8002248: 683b ldr r3, [r7, #0] 800224a: 431a orrs r2, r3 800224c: 687b ldr r3, [r7, #4] 800224e: 609a str r2, [r3, #8] } 8002250: bf00 nop 8002252: 370c adds r7, #12 8002254: 46bd mov sp, r7 8002256: f85d 7b04 ldr.w r7, [sp], #4 800225a: 4770 bx lr 0800225c : /* USER CODE END PFP */ /* Functions Definition ------------------------------------------------------*/ void MX_APPE_Config(void) { 800225c: b580 push {r7, lr} 800225e: af00 add r7, sp, #0 /** * The OPTVERR flag is wrongly set at power on * It shall be cleared before using any HAL_FLASH_xxx() api */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); 8002260: 4b04 ldr r3, [pc, #16] @ (8002274 ) 8002262: f44f 4200 mov.w r2, #32768 @ 0x8000 8002266: 611a str r2, [r3, #16] /** * Reset some configurations so that the system behave in the same way * when either out of nReset or Power On */ Reset_Device(); 8002268: f000 f824 bl 80022b4 /* Configure HSE Tuning */ Config_HSE(); 800226c: f000 f829 bl 80022c2 return; 8002270: bf00 nop } 8002272: bd80 pop {r7, pc} 8002274: 58004000 .word 0x58004000 08002278 : void MX_APPE_Init(void) { 8002278: b580 push {r7, lr} 800227a: af00 add r7, sp, #0 System_Init(); /**< System initialization */ 800227c: f000 f835 bl 80022ea SystemPower_Config(); /**< Configure the system Power Mode */ 8002280: f000 f84e bl 8002320 HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */ 8002284: 4903 ldr r1, [pc, #12] @ (8002294 ) 8002286: 2000 movs r0, #0 8002288: f001 ffd0 bl 800422c /* USER CODE BEGIN APPE_Init_1 */ /* USER CODE END APPE_Init_1 */ appe_Tl_Init(); /* Initialize all transport layers */ 800228c: f000 f856 bl 800233c */ /* USER CODE BEGIN APPE_Init_2 */ /* USER CODE END APPE_Init_2 */ return; 8002290: bf00 nop } 8002292: bd80 pop {r7, pc} 8002294: 20000504 .word 0x20000504 08002298 : void Init_Smps(void) { 8002298: b480 push {r7} 800229a: af00 add r7, sp, #0 LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA); LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40); LL_PWR_SMPS_Enable(); #endif /* CFG_USE_SMPS != 0 */ return; 800229c: bf00 nop } 800229e: 46bd mov sp, r7 80022a0: f85d 7b04 ldr.w r7, [sp], #4 80022a4: 4770 bx lr 080022a6 : void Init_Exti(void) { 80022a6: b580 push {r7, lr} 80022a8: af00 add r7, sp, #0 /* Enable IPCC(36), HSEM(38) wakeup interrupts on CPU1 */ LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_36 | LL_EXTI_LINE_38); 80022aa: 2050 movs r0, #80 @ 0x50 80022ac: f7ff ff44 bl 8002138 return; 80022b0: bf00 nop } 80022b2: bd80 pop {r7, pc} 080022b4 : * * LOCAL FUNCTIONS * *************************************************************/ static void Reset_Device(void) { 80022b4: b480 push {r7} 80022b6: af00 add r7, sp, #0 Reset_BackupDomain(); Reset_IPCC(); #endif /* CFG_HW_RESET_BY_FW == 1 */ return; 80022b8: bf00 nop } 80022ba: 46bd mov sp, r7 80022bc: f85d 7b04 ldr.w r7, [sp], #4 80022c0: 4770 bx lr 080022c2 : return; } #endif /* CFG_HW_RESET_BY_FW == 1 */ static void Config_HSE(void) { 80022c2: b580 push {r7, lr} 80022c4: b082 sub sp, #8 80022c6: af00 add r7, sp, #0 OTP_ID0_t * p_otp; /** * Read HSE_Tuning from OTP */ p_otp = (OTP_ID0_t *) OTP_Read(0); 80022c8: 2000 movs r0, #0 80022ca: f010 fcb5 bl 8012c38 80022ce: 6078 str r0, [r7, #4] if (p_otp) 80022d0: 687b ldr r3, [r7, #4] 80022d2: 2b00 cmp r3, #0 80022d4: d005 beq.n 80022e2 { LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning); 80022d6: 687b ldr r3, [r7, #4] 80022d8: 799b ldrb r3, [r3, #6] 80022da: 4618 mov r0, r3 80022dc: f7ff ff40 bl 8002160 } return; 80022e0: bf00 nop 80022e2: bf00 nop } 80022e4: 3708 adds r7, #8 80022e6: 46bd mov sp, r7 80022e8: bd80 pop {r7, pc} 080022ea : static void System_Init(void) { 80022ea: b580 push {r7, lr} 80022ec: af00 add r7, sp, #0 Init_Smps(); 80022ee: f7ff ffd3 bl 8002298 Init_Exti(); 80022f2: f7ff ffd8 bl 80022a6 Init_Rtc(); 80022f6: f000 f803 bl 8002300 return; 80022fa: bf00 nop } 80022fc: bd80 pop {r7, pc} ... 08002300 : static void Init_Rtc(void) { 8002300: b580 push {r7, lr} 8002302: af00 add r7, sp, #0 /* Disable RTC registers write protection */ LL_RTC_DisableWriteProtection(RTC); 8002304: 4805 ldr r0, [pc, #20] @ (800231c ) 8002306: f7ff ff86 bl 8002216 LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER); 800230a: 2100 movs r1, #0 800230c: 4803 ldr r0, [pc, #12] @ (800231c ) 800230e: f7ff ff92 bl 8002236 /* Enable RTC registers write protection */ LL_RTC_EnableWriteProtection(RTC); 8002312: 4802 ldr r0, [pc, #8] @ (800231c ) 8002314: f7ff ff72 bl 80021fc return; 8002318: bf00 nop } 800231a: bd80 pop {r7, pc} 800231c: 40002800 .word 0x40002800 08002320 : * * @param None * @retval None */ static void SystemPower_Config(void) { 8002320: b580 push {r7, lr} 8002322: af00 add r7, sp, #0 /** * Select HSI as system clock source after Wake Up from Stop mode */ LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI); 8002324: f44f 4000 mov.w r0, #32768 @ 0x8000 8002328: f7ff ff38 bl 800219c /* Initialize low power manager */ UTIL_LPM_Init(); 800232c: f016 fb1c bl 8018968 /* Initialize the CPU2 reset value before starting CPU2 with C2BOOT */ LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN); 8002330: 2004 movs r0, #4 8002332: f7ff feeb bl 800210c * Enable USB power */ HAL_PWREx_EnableVddUSB(); #endif /* CFG_USB_INTERFACE_ENABLE != 0 */ return; 8002336: bf00 nop } 8002338: bd80 pop {r7, pc} ... 0800233c : static void appe_Tl_Init(void) { 800233c: b580 push {r7, lr} 800233e: b088 sub sp, #32 8002340: af00 add r7, sp, #0 TL_MM_Config_t tl_mm_config; SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf; /**< Reference table initialization */ TL_Init(); 8002342: f010 fa7b bl 801283c MtxShciId = osMutexNew(NULL); 8002346: 2000 movs r0, #0 8002348: f010 ffa7 bl 801329a 800234c: 4603 mov r3, r0 800234e: 4a17 ldr r2, [pc, #92] @ (80023ac ) 8002350: 6013 str r3, [r2, #0] SemShciId = osSemaphoreNew(1, 0, NULL); /*< Create the semaphore and make it busy at initialization */ 8002352: 2200 movs r2, #0 8002354: 2100 movs r1, #0 8002356: 2001 movs r0, #1 8002358: f011 f8aa bl 80134b0 800235c: 4603 mov r3, r0 800235e: 4a14 ldr r2, [pc, #80] @ (80023b0 ) 8002360: 6013 str r3, [r2, #0] /** FreeRTOS system task creation */ ShciUserEvtProcessId = osThreadNew(ShciUserEvtProcess, NULL, &ShciUserEvtProcess_attr); 8002362: 4a14 ldr r2, [pc, #80] @ (80023b4 ) 8002364: 2100 movs r1, #0 8002366: 4814 ldr r0, [pc, #80] @ (80023b8 ) 8002368: f010 fe06 bl 8012f78 800236c: 4603 mov r3, r0 800236e: 4a13 ldr r2, [pc, #76] @ (80023bc ) 8002370: 6013 str r3, [r2, #0] /**< System channel initialization */ SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer; 8002372: 4b13 ldr r3, [pc, #76] @ (80023c0 ) 8002374: 603b str r3, [r7, #0] SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot; 8002376: 4b13 ldr r3, [pc, #76] @ (80023c4 ) 8002378: 607b str r3, [r7, #4] shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf); 800237a: 463b mov r3, r7 800237c: 4619 mov r1, r3 800237e: 4812 ldr r0, [pc, #72] @ (80023c8 ) 8002380: f010 f91e bl 80125c0 /**< Memory Manager channel initialization */ tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer; 8002384: 4b11 ldr r3, [pc, #68] @ (80023cc ) 8002386: 60bb str r3, [r7, #8] tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer; 8002388: 4b11 ldr r3, [pc, #68] @ (80023d0 ) 800238a: 60fb str r3, [r7, #12] tl_mm_config.p_AsynchEvtPool = EvtPool; 800238c: 4b11 ldr r3, [pc, #68] @ (80023d4 ) 800238e: 613b str r3, [r7, #16] tl_mm_config.AsynchEvtPoolSize = POOL_SIZE; 8002390: f240 533c movw r3, #1340 @ 0x53c 8002394: 617b str r3, [r7, #20] TL_MM_Init(&tl_mm_config); 8002396: f107 0308 add.w r3, r7, #8 800239a: 4618 mov r0, r3 800239c: f010 fb44 bl 8012a28 TL_Enable(); 80023a0: f010 fa46 bl 8012830 return; 80023a4: bf00 nop } 80023a6: 3720 adds r7, #32 80023a8: 46bd mov sp, r7 80023aa: bd80 pop {r7, pc} 80023ac: 20000308 .word 0x20000308 80023b0: 2000030c .word 0x2000030c 80023b4: 0801db4c .word 0x0801db4c 80023b8: 0800253b .word 0x0800253b 80023bc: 20000310 .word 0x20000310 80023c0: 20030628 .word 0x20030628 80023c4: 080023e9 .word 0x080023e9 80023c8: 08002429 .word 0x08002429 80023cc: 20030840 .word 0x20030840 80023d0: 20030734 .word 0x20030734 80023d4: 200300ec .word 0x200300ec 080023d8 : __WEAK void APP_BLE_Init(void) { 80023d8: b480 push {r7} 80023da: af00 add r7, sp, #0 } 80023dc: bf00 nop 80023de: 46bd mov sp, r7 80023e0: f85d 7b04 ldr.w r7, [sp], #4 80023e4: 4770 bx lr ... 080023e8 : static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status) { 80023e8: b580 push {r7, lr} 80023ea: b082 sub sp, #8 80023ec: af00 add r7, sp, #0 80023ee: 4603 mov r3, r0 80023f0: 71fb strb r3, [r7, #7] switch (status) 80023f2: 79fb ldrb r3, [r7, #7] 80023f4: 2b00 cmp r3, #0 80023f6: d002 beq.n 80023fe 80023f8: 2b01 cmp r3, #1 80023fa: d008 beq.n 800240e case SHCI_TL_CmdAvailable: osMutexRelease(MtxShciId); break; default: break; 80023fc: e00d b.n 800241a osMutexAcquire(MtxShciId, osWaitForever); 80023fe: 4b09 ldr r3, [pc, #36] @ (8002424 ) 8002400: 681b ldr r3, [r3, #0] 8002402: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002406: 4618 mov r0, r3 8002408: f010 ffcc bl 80133a4 break; 800240c: e005 b.n 800241a osMutexRelease(MtxShciId); 800240e: 4b05 ldr r3, [pc, #20] @ (8002424 ) 8002410: 681b ldr r3, [r3, #0] 8002412: 4618 mov r0, r3 8002414: f011 f810 bl 8013438 break; 8002418: bf00 nop } return; 800241a: bf00 nop } 800241c: 3708 adds r7, #8 800241e: 46bd mov sp, r7 8002420: bd80 pop {r7, pc} 8002422: bf00 nop 8002424: 20000308 .word 0x20000308 08002428 : * The buffer shall not be released * (eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable) * When the status is not filled, the buffer is released by default */ static void APPE_SysUserEvtRx(void * pPayload) { 8002428: b580 push {r7, lr} 800242a: b088 sub sp, #32 800242c: af00 add r7, sp, #0 800242e: 6078 str r0, [r7, #4] TL_AsynchEvt_t *p_sys_event; WirelessFwInfo_t WirelessInfo; p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); 8002430: 687b ldr r3, [r7, #4] 8002432: 685b ldr r3, [r3, #4] 8002434: 330b adds r3, #11 8002436: 61fb str r3, [r7, #28] switch(p_sys_event->subevtcode) 8002438: 69fb ldr r3, [r7, #28] 800243a: 881b ldrh r3, [r3, #0] 800243c: b29b uxth r3, r3 800243e: f5a3 4312 sub.w r3, r3, #37376 @ 0x9200 8002442: 2b07 cmp r3, #7 8002444: d81f bhi.n 8002486 8002446: a201 add r2, pc, #4 @ (adr r2, 800244c ) 8002448: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800244c: 0800246d .word 0x0800246d 8002450: 0800247f .word 0x0800247f 8002454: 08002487 .word 0x08002487 8002458: 08002487 .word 0x08002487 800245c: 08002487 .word 0x08002487 8002460: 08002487 .word 0x08002487 8002464: 08002487 .word 0x08002487 8002468: 08002487 .word 0x08002487 { case SHCI_SUB_EVT_CODE_READY: /* Read the firmware version of both the wireless firmware and the FUS */ SHCI_GetWirelessFwInfo(&WirelessInfo); 800246c: f107 030c add.w r3, r7, #12 8002470: 4618 mov r0, r3 8002472: f00f fff7 bl 8012464 APP_DBG_MSG("Wireless Firmware version %d.%d.%d\n", WirelessInfo.VersionMajor, WirelessInfo.VersionMinor, WirelessInfo.VersionSub); APP_DBG_MSG("Wireless Firmware build %d\n", WirelessInfo.VersionReleaseType); APP_DBG_MSG("FUS version %d.%d.%d\n", WirelessInfo.FusVersionMajor, WirelessInfo.FusVersionMinor, WirelessInfo.FusVersionSub); APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY\n\r"); APPE_SysEvtReadyProcessing(pPayload); 8002476: 6878 ldr r0, [r7, #4] 8002478: f000 f81b bl 80024b2 break; 800247c: e004 b.n 8002488 case SHCI_SUB_EVT_ERROR_NOTIF: APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF \n\r"); APPE_SysEvtError(pPayload); 800247e: 6878 ldr r0, [r7, #4] 8002480: f000 f806 bl 8002490 break; 8002484: e000 b.n 8002488 case SHCI_SUB_EVT_NVM_END_ERASE: APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_ERASE\n\r"); break; default: break; 8002486: bf00 nop } return; 8002488: bf00 nop } 800248a: 3720 adds r7, #32 800248c: 46bd mov sp, r7 800248e: bd80 pop {r7, pc} 08002490 : * @param ErrorCode : errorCode detected by the M0 firmware * * @retval None */ static void APPE_SysEvtError(void * pPayload) { 8002490: b480 push {r7} 8002492: b085 sub sp, #20 8002494: af00 add r7, sp, #0 8002496: 6078 str r0, [r7, #4] TL_AsynchEvt_t *p_sys_event; SCHI_SystemErrCode_t *p_sys_error_code; p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); 8002498: 687b ldr r3, [r7, #4] 800249a: 685b ldr r3, [r3, #4] 800249c: 330b adds r3, #11 800249e: 60fb str r3, [r7, #12] p_sys_error_code = (SCHI_SystemErrCode_t*) p_sys_event->payload; 80024a0: 68fb ldr r3, [r7, #12] 80024a2: 3302 adds r3, #2 80024a4: 60bb str r3, [r7, #8] } else { APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - BLE ERROR \n"); } return; 80024a6: bf00 nop } 80024a8: 3714 adds r7, #20 80024aa: 46bd mov sp, r7 80024ac: f85d 7b04 ldr.w r7, [sp], #4 80024b0: 4770 bx lr 080024b2 : static void APPE_SysEvtReadyProcessing(void * pPayload) { 80024b2: b580 push {r7, lr} 80024b4: b08a sub sp, #40 @ 0x28 80024b6: af00 add r7, sp, #0 80024b8: 6078 str r0, [r7, #4] TL_AsynchEvt_t *p_sys_event; SHCI_C2_Ready_Evt_t *p_sys_ready_event; SHCI_C2_CONFIG_Cmd_Param_t config_param = {0}; 80024ba: f107 0308 add.w r3, r7, #8 80024be: 2200 movs r2, #0 80024c0: 601a str r2, [r3, #0] 80024c2: 605a str r2, [r3, #4] 80024c4: 609a str r2, [r3, #8] 80024c6: 60da str r2, [r3, #12] uint32_t RevisionID=0; 80024c8: 2300 movs r3, #0 80024ca: 627b str r3, [r7, #36] @ 0x24 uint32_t DeviceID=0; 80024cc: 2300 movs r3, #0 80024ce: 623b str r3, [r7, #32] p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); 80024d0: 687b ldr r3, [r7, #4] 80024d2: 685b ldr r3, [r3, #4] 80024d4: 330b adds r3, #11 80024d6: 61fb str r3, [r7, #28] p_sys_ready_event = (SHCI_C2_Ready_Evt_t*) p_sys_event->payload; 80024d8: 69fb ldr r3, [r7, #28] 80024da: 3302 adds r3, #2 80024dc: 61bb str r3, [r7, #24] if (p_sys_ready_event->sysevt_ready_rsp == WIRELESS_FW_RUNNING) 80024de: 69bb ldr r3, [r7, #24] 80024e0: 781b ldrb r3, [r3, #0] 80024e2: 2b00 cmp r3, #0 80024e4: d11d bne.n 8002522 * The wireless firmware is running on the CPU2 */ APP_DBG_MSG(">>== WIRELESS_FW_RUNNING \n"); /* Traces channel initialization */ APPD_EnableCPU2(); 80024e6: f7ff fdf5 bl 80020d4 /* Enable all events Notification */ config_param.PayloadCmdSize = SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE; 80024ea: 230f movs r3, #15 80024ec: 723b strb r3, [r7, #8] config_param.EvtMask1 = SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE 80024ee: 237f movs r3, #127 @ 0x7f 80024f0: 72bb strb r3, [r7, #10] * @brief Return the device revision identifier * @note This field indicates the revision of the device. * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF */ RevisionID = LL_DBGMCU_GetRevisionID(); 80024f2: f7ff fe75 bl 80021e0 80024f6: 6278 str r0, [r7, #36] @ 0x24 APP_DBG_MSG(">>== DBGMCU_GetRevisionID= %lx \n\r", RevisionID); config_param.RevisionID = (uint16_t)RevisionID; 80024f8: 6a7b ldr r3, [r7, #36] @ 0x24 80024fa: b29b uxth r3, r3 80024fc: 82bb strh r3, [r7, #20] DeviceID = LL_DBGMCU_GetDeviceID(); 80024fe: f7ff fe61 bl 80021c4 8002502: 6238 str r0, [r7, #32] APP_DBG_MSG(">>== DBGMCU_GetDeviceID= %lx \n\r", DeviceID); config_param.DeviceID = (uint16_t)DeviceID; 8002504: 6a3b ldr r3, [r7, #32] 8002506: b29b uxth r3, r3 8002508: 82fb strh r3, [r7, #22] (void)SHCI_C2_Config(&config_param); 800250a: f107 0308 add.w r3, r7, #8 800250e: 4618 mov r0, r3 8002510: f00f ff92 bl 8012438 APP_BLE_Init(); 8002514: f7ff ff60 bl 80023d8 UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE); 8002518: 2100 movs r1, #0 800251a: 2001 movs r0, #1 800251c: f016 fa36 bl 801898c else { APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - UNEXPECTED CASE \n\r"); } return; 8002520: e007 b.n 8002532 else if (p_sys_ready_event->sysevt_ready_rsp == FUS_FW_RUNNING) 8002522: 69bb ldr r3, [r7, #24] 8002524: 781b ldrb r3, [r3, #0] 8002526: 2b01 cmp r3, #1 8002528: d103 bne.n 8002532 ((tSHCI_UserEvtRxParam*)pPayload)->status = SHCI_TL_UserEventFlow_Disable; 800252a: 687b ldr r3, [r7, #4] 800252c: 2200 movs r2, #0 800252e: 701a strb r2, [r3, #0] return; 8002530: bf00 nop 8002532: bf00 nop } 8002534: 3728 adds r7, #40 @ 0x28 8002536: 46bd mov sp, r7 8002538: bd80 pop {r7, pc} 0800253a : * * FREERTOS WRAPPER FUNCTIONS * *************************************************************/ static void ShciUserEvtProcess(void *argument) { 800253a: b580 push {r7, lr} 800253c: b082 sub sp, #8 800253e: af00 add r7, sp, #0 8002540: 6078 str r0, [r7, #4] for(;;) { /* USER CODE BEGIN SHCI_USER_EVT_PROCESS_1 */ /* USER CODE END SHCI_USER_EVT_PROCESS_1 */ osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever); 8002542: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8002546: 2100 movs r1, #0 8002548: 2001 movs r0, #1 800254a: f010 fe09 bl 8013160 shci_user_evt_proc(); 800254e: f010 f853 bl 80125f8 osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever); 8002552: bf00 nop 8002554: e7f5 b.n 8002542 ... 08002558 : __WFI(); } } void shci_notify_asynch_evt(void* pdata) { 8002558: b580 push {r7, lr} 800255a: b082 sub sp, #8 800255c: af00 add r7, sp, #0 800255e: 6078 str r0, [r7, #4] UNUSED(pdata); osThreadFlagsSet(ShciUserEvtProcessId, 1); 8002560: 4b04 ldr r3, [pc, #16] @ (8002574 ) 8002562: 681b ldr r3, [r3, #0] 8002564: 2101 movs r1, #1 8002566: 4618 mov r0, r3 8002568: f010 fda4 bl 80130b4 return; 800256c: bf00 nop } 800256e: 3708 adds r7, #8 8002570: 46bd mov sp, r7 8002572: bd80 pop {r7, pc} 8002574: 20000310 .word 0x20000310 08002578 : void shci_cmd_resp_release(uint32_t flag) { 8002578: b580 push {r7, lr} 800257a: b082 sub sp, #8 800257c: af00 add r7, sp, #0 800257e: 6078 str r0, [r7, #4] UNUSED(flag); osSemaphoreRelease(SemShciId); 8002580: 4b04 ldr r3, [pc, #16] @ (8002594 ) 8002582: 681b ldr r3, [r3, #0] 8002584: 4618 mov r0, r3 8002586: f011 f86b bl 8013660 return; 800258a: bf00 nop } 800258c: 3708 adds r7, #8 800258e: 46bd mov sp, r7 8002590: bd80 pop {r7, pc} 8002592: bf00 nop 8002594: 2000030c .word 0x2000030c 08002598 : void shci_cmd_resp_wait(uint32_t timeout) { 8002598: b580 push {r7, lr} 800259a: b082 sub sp, #8 800259c: af00 add r7, sp, #0 800259e: 6078 str r0, [r7, #4] UNUSED(timeout); osSemaphoreAcquire(SemShciId, osWaitForever); 80025a0: 4b05 ldr r3, [pc, #20] @ (80025b8 ) 80025a2: 681b ldr r3, [r3, #0] 80025a4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80025a8: 4618 mov r0, r3 80025aa: f011 f809 bl 80135c0 return; 80025ae: bf00 nop } 80025b0: 3708 adds r7, #8 80025b2: 46bd mov sp, r7 80025b4: bd80 pop {r7, pc} 80025b6: bf00 nop 80025b8: 2000030c .word 0x2000030c 080025bc : /*! * @brief This API is the entry point. Call this API before using other APIs. */ int8_t bmm350_init(struct bmm350_dev *dev) { 80025bc: b580 push {r7, lr} 80025be: b084 sub sp, #16 80025c0: af00 add r7, sp, #0 80025c2: 6078 str r0, [r7, #4] /* Variable to store the function result */ int8_t rslt; /* Variable to get chip id */ uint8_t chip_id = BMM350_DISABLE; 80025c4: 2300 movs r3, #0 80025c6: 73bb strb r3, [r7, #14] /* Variable to store the command to power-off the OTP */ uint8_t otp_cmd = BMM350_OTP_CMD_PWR_OFF_OTP; 80025c8: 2380 movs r3, #128 @ 0x80 80025ca: 737b strb r3, [r7, #13] /* Variable to store soft-reset command */ uint8_t soft_reset; /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 80025cc: 6878 ldr r0, [r7, #4] 80025ce: f000 fd8a bl 80030e6 80025d2: 4603 mov r3, r0 80025d4: 73fb strb r3, [r7, #15] /* Proceed if null check is fine */ if (rslt == BMM350_OK) 80025d6: f997 300f ldrsb.w r3, [r7, #15] 80025da: 2b00 cmp r3, #0 80025dc: d173 bne.n 80026c6 { dev->chip_id = 0; 80025de: 687b ldr r3, [r7, #4] 80025e0: 2200 movs r2, #0 80025e2: 711a strb r2, [r3, #4] /* Assign axis_en with all axis enabled (BMM350_EN_XYZ_MSK) */ dev->axis_en = BMM350_EN_XYZ_MSK; 80025e4: 687b ldr r3, [r7, #4] 80025e6: 2207 movs r2, #7 80025e8: 755a strb r2, [r3, #21] rslt = bmm350_delay_us(BMM350_START_UP_TIME_FROM_POR, dev); 80025ea: 6879 ldr r1, [r7, #4] 80025ec: f640 30b8 movw r0, #3000 @ 0xbb8 80025f0: f000 f8f8 bl 80027e4 80025f4: 4603 mov r3, r0 80025f6: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80025f8: f997 300f ldrsb.w r3, [r7, #15] 80025fc: 2b00 cmp r3, #0 80025fe: d115 bne.n 800262c { /* Soft-reset */ soft_reset = BMM350_CMD_SOFTRESET; 8002600: 23b6 movs r3, #182 @ 0xb6 8002602: 733b strb r3, [r7, #12] /* Set the command in the command register */ rslt = bmm350_set_regs(BMM350_REG_CMD, &soft_reset, 1, dev); 8002604: f107 010c add.w r1, r7, #12 8002608: 687b ldr r3, [r7, #4] 800260a: 2201 movs r2, #1 800260c: 207e movs r0, #126 @ 0x7e 800260e: f000 f860 bl 80026d2 8002612: 4603 mov r3, r0 8002614: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002616: f997 300f ldrsb.w r3, [r7, #15] 800261a: 2b00 cmp r3, #0 800261c: d106 bne.n 800262c { rslt = bmm350_delay_us(BMM350_SOFT_RESET_DELAY, dev); 800261e: 6879 ldr r1, [r7, #4] 8002620: f645 50c0 movw r0, #24000 @ 0x5dc0 8002624: f000 f8de bl 80027e4 8002628: 4603 mov r3, r0 800262a: 73fb strb r3, [r7, #15] } } if (rslt == BMM350_OK) 800262c: f997 300f ldrsb.w r3, [r7, #15] 8002630: 2b00 cmp r3, #0 8002632: d10f bne.n 8002654 { /* Chip ID of the sensor is read */ rslt = bmm350_get_regs(BMM350_REG_CHIP_ID, &chip_id, 1, dev); 8002634: f107 010e add.w r1, r7, #14 8002638: 687b ldr r3, [r7, #4] 800263a: 2201 movs r2, #1 800263c: 2000 movs r0, #0 800263e: f000 f87c bl 800273a 8002642: 4603 mov r3, r0 8002644: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002646: f997 300f ldrsb.w r3, [r7, #15] 800264a: 2b00 cmp r3, #0 800264c: d102 bne.n 8002654 { /* Assign chip_id to dev->chip_id */ dev->chip_id = chip_id; 800264e: 7bba ldrb r2, [r7, #14] 8002650: 687b ldr r3, [r7, #4] 8002652: 711a strb r2, [r3, #4] } } /* Check for chip id validity */ if ((rslt == BMM350_OK) && (dev->chip_id == BMM350_CHIP_ID)) 8002654: f997 300f ldrsb.w r3, [r7, #15] 8002658: 2b00 cmp r3, #0 800265a: d130 bne.n 80026be 800265c: 687b ldr r3, [r7, #4] 800265e: 791b ldrb r3, [r3, #4] 8002660: 2b33 cmp r3, #51 @ 0x33 8002662: d12c bne.n 80026be { /* Download OTP memory */ rslt = otp_dump_after_boot(dev); 8002664: 6878 ldr r0, [r7, #4] 8002666: f001 f913 bl 8003890 800266a: 4603 mov r3, r0 800266c: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 800266e: f997 300f ldrsb.w r3, [r7, #15] 8002672: 2b00 cmp r3, #0 8002674: d126 bne.n 80026c4 { /* Power off OTP */ rslt = bmm350_set_regs(BMM350_REG_OTP_CMD_REG, &otp_cmd, 1, dev); 8002676: f107 010d add.w r1, r7, #13 800267a: 687b ldr r3, [r7, #4] 800267c: 2201 movs r2, #1 800267e: 2050 movs r0, #80 @ 0x50 8002680: f000 f827 bl 80026d2 8002684: 4603 mov r3, r0 8002686: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002688: f997 300f ldrsb.w r3, [r7, #15] 800268c: 2b00 cmp r3, #0 800268e: d119 bne.n 80026c4 { if (dev->boot_done_status != BMM350_BOOT_NOT_DONE) 8002690: 687b ldr r3, [r7, #4] 8002692: f893 30ac ldrb.w r3, [r3, #172] @ 0xac 8002696: 2b00 cmp r3, #0 8002698: d003 beq.n 80026a2 { dev->boot_done_status = BMM350_BOOT_NOT_DONE; 800269a: 687b ldr r3, [r7, #4] 800269c: 2200 movs r2, #0 800269e: f883 20ac strb.w r2, [r3, #172] @ 0xac } rslt = bmm350_magnetic_reset_and_wait(dev); 80026a2: 6878 ldr r0, [r7, #4] 80026a4: f000 fa98 bl 8002bd8 80026a8: 4603 mov r3, r0 80026aa: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80026ac: f997 300f ldrsb.w r3, [r7, #15] 80026b0: 2b00 cmp r3, #0 80026b2: d107 bne.n 80026c4 { dev->boot_done_status = BMM350_BOOT_DONE; 80026b4: 687b ldr r3, [r7, #4] 80026b6: 2201 movs r2, #1 80026b8: f883 20ac strb.w r2, [r3, #172] @ 0xac if (rslt == BMM350_OK) 80026bc: e002 b.n 80026c4 } } } else { rslt = BMM350_E_DEV_NOT_FOUND; 80026be: 23fd movs r3, #253 @ 0xfd 80026c0: 73fb strb r3, [r7, #15] 80026c2: e000 b.n 80026c6 if (rslt == BMM350_OK) 80026c4: bf00 nop } } return rslt; 80026c6: f997 300f ldrsb.w r3, [r7, #15] } 80026ca: 4618 mov r0, r3 80026cc: 3710 adds r7, #16 80026ce: 46bd mov sp, r7 80026d0: bd80 pop {r7, pc} 080026d2 : /*! * @brief This API writes the given data to the register address * of the sensor. */ int8_t bmm350_set_regs(uint8_t reg_addr, const uint8_t *reg_data, uint16_t len, struct bmm350_dev *dev) { 80026d2: b590 push {r4, r7, lr} 80026d4: b087 sub sp, #28 80026d6: af00 add r7, sp, #0 80026d8: 60b9 str r1, [r7, #8] 80026da: 607b str r3, [r7, #4] 80026dc: 4603 mov r3, r0 80026de: 73fb strb r3, [r7, #15] 80026e0: 4613 mov r3, r2 80026e2: 81bb strh r3, [r7, #12] /* Variable to store the function result */ int8_t rslt; /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 80026e4: 6878 ldr r0, [r7, #4] 80026e6: f000 fcfe bl 80030e6 80026ea: 4603 mov r3, r0 80026ec: 75fb strb r3, [r7, #23] /* Proceed if null check is fine */ if ((rslt == BMM350_OK) && (reg_data != NULL) && (len != 0)) 80026ee: f997 3017 ldrsb.w r3, [r7, #23] 80026f2: 2b00 cmp r3, #0 80026f4: d119 bne.n 800272a 80026f6: 68bb ldr r3, [r7, #8] 80026f8: 2b00 cmp r3, #0 80026fa: d016 beq.n 800272a 80026fc: 89bb ldrh r3, [r7, #12] 80026fe: 2b00 cmp r3, #0 8002700: d013 beq.n 800272a { /* Write the data to the reg_addr */ dev->intf_rslt = dev->write(reg_addr, reg_data, len, dev->intf_ptr); 8002702: 687b ldr r3, [r7, #4] 8002704: 68dc ldr r4, [r3, #12] 8002706: 89ba ldrh r2, [r7, #12] 8002708: 687b ldr r3, [r7, #4] 800270a: 681b ldr r3, [r3, #0] 800270c: 7bf8 ldrb r0, [r7, #15] 800270e: 68b9 ldr r1, [r7, #8] 8002710: 47a0 blx r4 8002712: 4603 mov r3, r0 8002714: 461a mov r2, r3 8002716: 687b ldr r3, [r7, #4] 8002718: 751a strb r2, [r3, #20] if (dev->intf_rslt != BMM350_INTF_RET_SUCCESS) 800271a: 687b ldr r3, [r7, #4] 800271c: f993 3014 ldrsb.w r3, [r3, #20] 8002720: 2b00 cmp r3, #0 8002722: d004 beq.n 800272e { rslt = BMM350_E_COM_FAIL; 8002724: 23fe movs r3, #254 @ 0xfe 8002726: 75fb strb r3, [r7, #23] if (dev->intf_rslt != BMM350_INTF_RET_SUCCESS) 8002728: e001 b.n 800272e } } else { rslt = BMM350_E_NULL_PTR; 800272a: 23ff movs r3, #255 @ 0xff 800272c: 75fb strb r3, [r7, #23] } return rslt; 800272e: f997 3017 ldrsb.w r3, [r7, #23] } 8002732: 4618 mov r0, r3 8002734: 371c adds r7, #28 8002736: 46bd mov sp, r7 8002738: bd90 pop {r4, r7, pc} 0800273a : /*! * @brief This API reads the data from the given register address of sensor. */ int8_t bmm350_get_regs(uint8_t reg_addr, uint8_t *reg_data, uint16_t len, struct bmm350_dev *dev) { 800273a: b590 push {r4, r7, lr} 800273c: b0a7 sub sp, #156 @ 0x9c 800273e: af00 add r7, sp, #0 8002740: 60b9 str r1, [r7, #8] 8002742: 607b str r3, [r7, #4] 8002744: 4603 mov r3, r0 8002746: 73fb strb r3, [r7, #15] 8002748: 4613 mov r3, r2 800274a: 81bb strh r3, [r7, #12] /* Variable to store the function result */ int8_t rslt; /* Variable to define temporary length */ uint16_t temp_len = len + BMM350_DUMMY_BYTES; 800274c: 89bb ldrh r3, [r7, #12] 800274e: 3302 adds r3, #2 8002750: f8a7 3092 strh.w r3, [r7, #146] @ 0x92 /* Variable to define temporary buffer */ uint8_t temp_buf[BMM350_READ_BUFFER_LENGTH]; /* Variable to define loop */ uint16_t index = 0; 8002754: 2300 movs r3, #0 8002756: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 800275a: 6878 ldr r0, [r7, #4] 800275c: f000 fcc3 bl 80030e6 8002760: 4603 mov r3, r0 8002762: f887 3097 strb.w r3, [r7, #151] @ 0x97 /* Proceed if null check is fine */ if ((rslt == BMM350_OK) && (reg_data != NULL)) 8002766: f997 3097 ldrsb.w r3, [r7, #151] @ 0x97 800276a: 2b00 cmp r3, #0 800276c: d131 bne.n 80027d2 800276e: 68bb ldr r3, [r7, #8] 8002770: 2b00 cmp r3, #0 8002772: d02e beq.n 80027d2 { /* Read the data from the reg_addr */ dev->intf_rslt = dev->read(reg_addr, temp_buf, temp_len, dev->intf_ptr); 8002774: 687b ldr r3, [r7, #4] 8002776: 689c ldr r4, [r3, #8] 8002778: f8b7 2092 ldrh.w r2, [r7, #146] @ 0x92 800277c: 687b ldr r3, [r7, #4] 800277e: 681b ldr r3, [r3, #0] 8002780: f107 0110 add.w r1, r7, #16 8002784: 7bf8 ldrb r0, [r7, #15] 8002786: 47a0 blx r4 8002788: 4603 mov r3, r0 800278a: 461a mov r2, r3 800278c: 687b ldr r3, [r7, #4] 800278e: 751a strb r2, [r3, #20] if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS) 8002790: 687b ldr r3, [r7, #4] 8002792: f993 3014 ldrsb.w r3, [r3, #20] 8002796: 2b00 cmp r3, #0 8002798: d117 bne.n 80027ca { /* Copy data after dummy byte indices */ while (index < len) 800279a: e010 b.n 80027be { reg_data[index] = temp_buf[index + BMM350_DUMMY_BYTES]; 800279c: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 80027a0: 1c9a adds r2, r3, #2 80027a2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 80027a6: 68b9 ldr r1, [r7, #8] 80027a8: 440b add r3, r1 80027aa: 3298 adds r2, #152 @ 0x98 80027ac: 443a add r2, r7 80027ae: f812 2c88 ldrb.w r2, [r2, #-136] 80027b2: 701a strb r2, [r3, #0] index++; 80027b4: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 80027b8: 3301 adds r3, #1 80027ba: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 while (index < len) 80027be: f8b7 2094 ldrh.w r2, [r7, #148] @ 0x94 80027c2: 89bb ldrh r3, [r7, #12] 80027c4: 429a cmp r2, r3 80027c6: d3e9 bcc.n 800279c if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS) 80027c8: e006 b.n 80027d8 } } else { rslt = BMM350_E_COM_FAIL; 80027ca: 23fe movs r3, #254 @ 0xfe 80027cc: f887 3097 strb.w r3, [r7, #151] @ 0x97 if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS) 80027d0: e002 b.n 80027d8 } } else { rslt = BMM350_E_NULL_PTR; 80027d2: 23ff movs r3, #255 @ 0xff 80027d4: f887 3097 strb.w r3, [r7, #151] @ 0x97 } return rslt; 80027d8: f997 3097 ldrsb.w r3, [r7, #151] @ 0x97 } 80027dc: 4618 mov r0, r3 80027de: 379c adds r7, #156 @ 0x9c 80027e0: 46bd mov sp, r7 80027e2: bd90 pop {r4, r7, pc} 080027e4 : /*! * @brief This function provides the delay for required time (Microsecond) as per the input provided in some of the * APIs. */ int8_t bmm350_delay_us(uint32_t period_us, const struct bmm350_dev *dev) { 80027e4: b580 push {r7, lr} 80027e6: b084 sub sp, #16 80027e8: af00 add r7, sp, #0 80027ea: 6078 str r0, [r7, #4] 80027ec: 6039 str r1, [r7, #0] /* Variable to store the function result */ int8_t rslt; /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 80027ee: 6838 ldr r0, [r7, #0] 80027f0: f000 fc79 bl 80030e6 80027f4: 4603 mov r3, r0 80027f6: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80027f8: f997 300f ldrsb.w r3, [r7, #15] 80027fc: 2b00 cmp r3, #0 80027fe: d106 bne.n 800280e { dev->delay_us(period_us, dev->intf_ptr); 8002800: 683b ldr r3, [r7, #0] 8002802: 691b ldr r3, [r3, #16] 8002804: 683a ldr r2, [r7, #0] 8002806: 6812 ldr r2, [r2, #0] 8002808: 4611 mov r1, r2 800280a: 6878 ldr r0, [r7, #4] 800280c: 4798 blx r3 } return rslt; 800280e: f997 300f ldrsb.w r3, [r7, #15] } 8002812: 4618 mov r0, r3 8002814: 3710 adds r7, #16 8002816: 46bd mov sp, r7 8002818: bd80 pop {r7, pc} 0800281a : /*! * @brief This API is used to set the power mode of the sensor */ int8_t bmm350_set_powermode(enum bmm350_power_modes powermode, struct bmm350_dev *dev) { 800281a: b580 push {r7, lr} 800281c: b084 sub sp, #16 800281e: af00 add r7, sp, #0 8002820: 4603 mov r3, r0 8002822: 6039 str r1, [r7, #0] 8002824: 71fb strb r3, [r7, #7] uint8_t last_pwr_mode; uint8_t reg_data; /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 8002826: 6838 ldr r0, [r7, #0] 8002828: f000 fc5d bl 80030e6 800282c: 4603 mov r3, r0 800282e: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002830: f997 300f ldrsb.w r3, [r7, #15] 8002834: 2b00 cmp r3, #0 8002836: d13c bne.n 80028b2 { rslt = bmm350_get_regs(BMM350_REG_PMU_CMD, &last_pwr_mode, 1, dev); 8002838: f107 010e add.w r1, r7, #14 800283c: 683b ldr r3, [r7, #0] 800283e: 2201 movs r2, #1 8002840: 2006 movs r0, #6 8002842: f7ff ff7a bl 800273a 8002846: 4603 mov r3, r0 8002848: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 800284a: f997 300f ldrsb.w r3, [r7, #15] 800284e: 2b00 cmp r3, #0 8002850: d12f bne.n 80028b2 { if (last_pwr_mode > BMM350_PMU_CMD_BR_FAST) 8002852: 7bbb ldrb r3, [r7, #14] 8002854: 2b08 cmp r3, #8 8002856: d901 bls.n 800285c { rslt = BMM350_E_INVALID_CONFIG; 8002858: 23fc movs r3, #252 @ 0xfc 800285a: 73fb strb r3, [r7, #15] } if ((rslt == BMM350_OK) && 800285c: f997 300f ldrsb.w r3, [r7, #15] 8002860: 2b00 cmp r3, #0 8002862: d11b bne.n 800289c ((last_pwr_mode == BMM350_PMU_CMD_NM) || (last_pwr_mode == BMM350_PMU_CMD_UPD_OAE))) 8002864: 7bbb ldrb r3, [r7, #14] if ((rslt == BMM350_OK) && 8002866: 2b01 cmp r3, #1 8002868: d002 beq.n 8002870 ((last_pwr_mode == BMM350_PMU_CMD_NM) || (last_pwr_mode == BMM350_PMU_CMD_UPD_OAE))) 800286a: 7bbb ldrb r3, [r7, #14] 800286c: 2b02 cmp r3, #2 800286e: d115 bne.n 800289c { reg_data = BMM350_PMU_CMD_SUS; 8002870: 2300 movs r3, #0 8002872: 737b strb r3, [r7, #13] /* Set PMU command configuration */ rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev); 8002874: f107 010d add.w r1, r7, #13 8002878: 683b ldr r3, [r7, #0] 800287a: 2201 movs r2, #1 800287c: 2006 movs r0, #6 800287e: f7ff ff28 bl 80026d2 8002882: 4603 mov r3, r0 8002884: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002886: f997 300f ldrsb.w r3, [r7, #15] 800288a: 2b00 cmp r3, #0 800288c: d106 bne.n 800289c { rslt = bmm350_delay_us(BMM350_GOTO_SUSPEND_DELAY, dev); 800288e: 6839 ldr r1, [r7, #0] 8002890: f241 7070 movw r0, #6000 @ 0x1770 8002894: f7ff ffa6 bl 80027e4 8002898: 4603 mov r3, r0 800289a: 73fb strb r3, [r7, #15] } } if (rslt == BMM350_OK) 800289c: f997 300f ldrsb.w r3, [r7, #15] 80028a0: 2b00 cmp r3, #0 80028a2: d106 bne.n 80028b2 { rslt = set_powermode(powermode, dev); 80028a4: 79fb ldrb r3, [r7, #7] 80028a6: 6839 ldr r1, [r7, #0] 80028a8: 4618 mov r0, r3 80028aa: f001 f831 bl 8003910 80028ae: 4603 mov r3, r0 80028b0: 73fb strb r3, [r7, #15] } } } return rslt; 80028b2: f997 300f ldrsb.w r3, [r7, #15] } 80028b6: 4618 mov r0, r3 80028b8: 3710 adds r7, #16 80028ba: 46bd mov sp, r7 80028bc: bd80 pop {r7, pc} 080028be : * @brief This API sets the ODR and averaging factor. */ int8_t bmm350_set_odr_performance(enum bmm350_data_rates odr, enum bmm350_performance_parameters performance, struct bmm350_dev *dev) { 80028be: b580 push {r7, lr} 80028c0: b084 sub sp, #16 80028c2: af00 add r7, sp, #0 80028c4: 4603 mov r3, r0 80028c6: 603a str r2, [r7, #0] 80028c8: 71fb strb r3, [r7, #7] 80028ca: 460b mov r3, r1 80028cc: 71bb strb r3, [r7, #6] /* Variable to store the function result */ int8_t rslt; /* Variable to get PMU command */ uint8_t reg_data = 0; 80028ce: 2300 movs r3, #0 80028d0: 737b strb r3, [r7, #13] enum bmm350_performance_parameters performance_fix = performance; 80028d2: 79bb ldrb r3, [r7, #6] 80028d4: 73bb strb r3, [r7, #14] /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 80028d6: 6838 ldr r0, [r7, #0] 80028d8: f000 fc05 bl 80030e6 80028dc: 4603 mov r3, r0 80028de: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80028e0: f997 300f ldrsb.w r3, [r7, #15] 80028e4: 2b00 cmp r3, #0 80028e6: d151 bne.n 800298c { /* Reduce the performance setting when too high for the chosen ODR */ if ((odr == BMM350_DATA_RATE_400HZ) && (performance >= BMM350_AVERAGING_2)) 80028e8: 79fb ldrb r3, [r7, #7] 80028ea: 2b02 cmp r3, #2 80028ec: d105 bne.n 80028fa 80028ee: 79bb ldrb r3, [r7, #6] 80028f0: 2b00 cmp r3, #0 80028f2: d002 beq.n 80028fa { performance_fix = BMM350_NO_AVERAGING; 80028f4: 2300 movs r3, #0 80028f6: 73bb strb r3, [r7, #14] 80028f8: e010 b.n 800291c } else if ((odr == BMM350_DATA_RATE_200HZ) && (performance >= BMM350_AVERAGING_4)) 80028fa: 79fb ldrb r3, [r7, #7] 80028fc: 2b03 cmp r3, #3 80028fe: d105 bne.n 800290c 8002900: 79bb ldrb r3, [r7, #6] 8002902: 2b01 cmp r3, #1 8002904: d902 bls.n 800290c { performance_fix = BMM350_AVERAGING_2; 8002906: 2301 movs r3, #1 8002908: 73bb strb r3, [r7, #14] 800290a: e007 b.n 800291c } else if ((odr == BMM350_DATA_RATE_100HZ) && (performance >= BMM350_AVERAGING_8)) 800290c: 79fb ldrb r3, [r7, #7] 800290e: 2b04 cmp r3, #4 8002910: d104 bne.n 800291c 8002912: 79bb ldrb r3, [r7, #6] 8002914: 2b02 cmp r3, #2 8002916: d901 bls.n 800291c { performance_fix = BMM350_AVERAGING_4; 8002918: 2302 movs r3, #2 800291a: 73bb strb r3, [r7, #14] } /* ODR is an enum taking the generated constants from the register map */ reg_data = ((uint8_t)odr & BMM350_ODR_MSK); 800291c: 79fb ldrb r3, [r7, #7] 800291e: f003 030f and.w r3, r3, #15 8002922: b2db uxtb r3, r3 8002924: 737b strb r3, [r7, #13] /* AVG / performance is an enum taking the generated constants from the register map */ reg_data = BMM350_SET_BITS(reg_data, BMM350_AVG, (uint8_t)performance_fix); 8002926: 7b7b ldrb r3, [r7, #13] 8002928: b25b sxtb r3, r3 800292a: f023 0330 bic.w r3, r3, #48 @ 0x30 800292e: b25a sxtb r2, r3 8002930: f997 300e ldrsb.w r3, [r7, #14] 8002934: 011b lsls r3, r3, #4 8002936: b25b sxtb r3, r3 8002938: f003 0330 and.w r3, r3, #48 @ 0x30 800293c: b25b sxtb r3, r3 800293e: 4313 orrs r3, r2 8002940: b25b sxtb r3, r3 8002942: b2db uxtb r3, r3 8002944: 737b strb r3, [r7, #13] /* Set PMU command configurations for ODR and performance */ rslt = bmm350_set_regs(BMM350_REG_PMU_CMD_AGGR_SET, ®_data, 1, dev); 8002946: f107 010d add.w r1, r7, #13 800294a: 683b ldr r3, [r7, #0] 800294c: 2201 movs r2, #1 800294e: 2004 movs r0, #4 8002950: f7ff febf bl 80026d2 8002954: 4603 mov r3, r0 8002956: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002958: f997 300f ldrsb.w r3, [r7, #15] 800295c: 2b00 cmp r3, #0 800295e: d115 bne.n 800298c { /* Set PMU command configurations to update odr and average */ reg_data = BMM350_PMU_CMD_UPD_OAE; 8002960: 2302 movs r3, #2 8002962: 737b strb r3, [r7, #13] /* Set PMU command configuration */ rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev); 8002964: f107 010d add.w r1, r7, #13 8002968: 683b ldr r3, [r7, #0] 800296a: 2201 movs r2, #1 800296c: 2006 movs r0, #6 800296e: f7ff feb0 bl 80026d2 8002972: 4603 mov r3, r0 8002974: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002976: f997 300f ldrsb.w r3, [r7, #15] 800297a: 2b00 cmp r3, #0 800297c: d106 bne.n 800298c { rslt = bmm350_delay_us(BMM350_UPD_OAE_DELAY, dev); 800297e: 6839 ldr r1, [r7, #0] 8002980: f44f 707a mov.w r0, #1000 @ 0x3e8 8002984: f7ff ff2e bl 80027e4 8002988: 4603 mov r3, r0 800298a: 73fb strb r3, [r7, #15] } } } return rslt; 800298c: f997 300f ldrsb.w r3, [r7, #15] } 8002990: 4618 mov r0, r3 8002992: 3710 adds r7, #16 8002994: 46bd mov sp, r7 8002996: bd80 pop {r7, pc} 08002998 : /*! * @brief This API is used to enable or disable the data ready interrupt */ int8_t bmm350_enable_interrupt(enum bmm350_interrupt_enable_disable enable_disable, struct bmm350_dev *dev) { 8002998: b580 push {r7, lr} 800299a: b084 sub sp, #16 800299c: af00 add r7, sp, #0 800299e: 4603 mov r3, r0 80029a0: 6039 str r1, [r7, #0] 80029a2: 71fb strb r3, [r7, #7] /* Variable to get interrupt control configuration */ uint8_t reg_data = 0; 80029a4: 2300 movs r3, #0 80029a6: 73bb strb r3, [r7, #14] /* Variable to store the function result */ int8_t rslt; /* Get interrupt control configuration */ rslt = bmm350_get_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev); 80029a8: f107 010e add.w r1, r7, #14 80029ac: 683b ldr r3, [r7, #0] 80029ae: 2201 movs r2, #1 80029b0: 202e movs r0, #46 @ 0x2e 80029b2: f7ff fec2 bl 800273a 80029b6: 4603 mov r3, r0 80029b8: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80029ba: f997 300f ldrsb.w r3, [r7, #15] 80029be: 2b00 cmp r3, #0 80029c0: d115 bne.n 80029ee { reg_data = BMM350_SET_BITS(reg_data, BMM350_DRDY_DATA_REG_EN, (uint8_t)enable_disable); 80029c2: 7bbb ldrb r3, [r7, #14] 80029c4: b25b sxtb r3, r3 80029c6: f003 037f and.w r3, r3, #127 @ 0x7f 80029ca: b25a sxtb r2, r3 80029cc: f997 3007 ldrsb.w r3, [r7, #7] 80029d0: 01db lsls r3, r3, #7 80029d2: b25b sxtb r3, r3 80029d4: 4313 orrs r3, r2 80029d6: b25b sxtb r3, r3 80029d8: b2db uxtb r3, r3 80029da: 73bb strb r3, [r7, #14] /* Finally transfer the interrupt configurations */ rslt = bmm350_set_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev); 80029dc: f107 010e add.w r1, r7, #14 80029e0: 683b ldr r3, [r7, #0] 80029e2: 2201 movs r2, #1 80029e4: 202e movs r0, #46 @ 0x2e 80029e6: f7ff fe74 bl 80026d2 80029ea: 4603 mov r3, r0 80029ec: 73fb strb r3, [r7, #15] } return rslt; 80029ee: f997 300f ldrsb.w r3, [r7, #15] } 80029f2: 4618 mov r0, r3 80029f4: 3710 adds r7, #16 80029f6: 46bd mov sp, r7 80029f8: bd80 pop {r7, pc} 080029fa : int8_t bmm350_configure_interrupt(enum bmm350_intr_latch latching, enum bmm350_intr_polarity polarity, enum bmm350_intr_drive drivertype, enum bmm350_intr_map map_nomap, struct bmm350_dev *dev) { 80029fa: b590 push {r4, r7, lr} 80029fc: b085 sub sp, #20 80029fe: af00 add r7, sp, #0 8002a00: 4604 mov r4, r0 8002a02: 4608 mov r0, r1 8002a04: 4611 mov r1, r2 8002a06: 461a mov r2, r3 8002a08: 4623 mov r3, r4 8002a0a: 71fb strb r3, [r7, #7] 8002a0c: 4603 mov r3, r0 8002a0e: 71bb strb r3, [r7, #6] 8002a10: 460b mov r3, r1 8002a12: 717b strb r3, [r7, #5] 8002a14: 4613 mov r3, r2 8002a16: 713b strb r3, [r7, #4] /* Variable to get interrupt control configuration */ uint8_t reg_data = 0; 8002a18: 2300 movs r3, #0 8002a1a: 73bb strb r3, [r7, #14] /* Variable to store the function result */ int8_t rslt; /* Get interrupt control configuration */ rslt = bmm350_get_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev); 8002a1c: f107 010e add.w r1, r7, #14 8002a20: 6a3b ldr r3, [r7, #32] 8002a22: 2201 movs r2, #1 8002a24: 202e movs r0, #46 @ 0x2e 8002a26: f7ff fe88 bl 800273a 8002a2a: 4603 mov r3, r0 8002a2c: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002a2e: f997 300f ldrsb.w r3, [r7, #15] 8002a32: 2b00 cmp r3, #0 8002a34: d146 bne.n 8002ac4 { reg_data = BMM350_SET_BITS_POS_0(reg_data, BMM350_INT_MODE, latching); 8002a36: 7bbb ldrb r3, [r7, #14] 8002a38: b25b sxtb r3, r3 8002a3a: f023 0301 bic.w r3, r3, #1 8002a3e: b25a sxtb r2, r3 8002a40: f997 3007 ldrsb.w r3, [r7, #7] 8002a44: f003 0301 and.w r3, r3, #1 8002a48: b25b sxtb r3, r3 8002a4a: 4313 orrs r3, r2 8002a4c: b25b sxtb r3, r3 8002a4e: b2db uxtb r3, r3 8002a50: 73bb strb r3, [r7, #14] reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_POL, polarity); 8002a52: 7bbb ldrb r3, [r7, #14] 8002a54: b25b sxtb r3, r3 8002a56: f023 0302 bic.w r3, r3, #2 8002a5a: b25a sxtb r2, r3 8002a5c: f997 3006 ldrsb.w r3, [r7, #6] 8002a60: 005b lsls r3, r3, #1 8002a62: b25b sxtb r3, r3 8002a64: f003 0302 and.w r3, r3, #2 8002a68: b25b sxtb r3, r3 8002a6a: 4313 orrs r3, r2 8002a6c: b25b sxtb r3, r3 8002a6e: b2db uxtb r3, r3 8002a70: 73bb strb r3, [r7, #14] reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_OD, drivertype); 8002a72: 7bbb ldrb r3, [r7, #14] 8002a74: b25b sxtb r3, r3 8002a76: f023 0304 bic.w r3, r3, #4 8002a7a: b25a sxtb r2, r3 8002a7c: f997 3005 ldrsb.w r3, [r7, #5] 8002a80: 009b lsls r3, r3, #2 8002a82: b25b sxtb r3, r3 8002a84: f003 0304 and.w r3, r3, #4 8002a88: b25b sxtb r3, r3 8002a8a: 4313 orrs r3, r2 8002a8c: b25b sxtb r3, r3 8002a8e: b2db uxtb r3, r3 8002a90: 73bb strb r3, [r7, #14] reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_OUTPUT_EN, map_nomap); 8002a92: 7bbb ldrb r3, [r7, #14] 8002a94: b25b sxtb r3, r3 8002a96: f023 0308 bic.w r3, r3, #8 8002a9a: b25a sxtb r2, r3 8002a9c: f997 3004 ldrsb.w r3, [r7, #4] 8002aa0: 00db lsls r3, r3, #3 8002aa2: b25b sxtb r3, r3 8002aa4: f003 0308 and.w r3, r3, #8 8002aa8: b25b sxtb r3, r3 8002aaa: 4313 orrs r3, r2 8002aac: b25b sxtb r3, r3 8002aae: b2db uxtb r3, r3 8002ab0: 73bb strb r3, [r7, #14] /* Finally transfer the interrupt configurations */ rslt = bmm350_set_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev); 8002ab2: f107 010e add.w r1, r7, #14 8002ab6: 6a3b ldr r3, [r7, #32] 8002ab8: 2201 movs r2, #1 8002aba: 202e movs r0, #46 @ 0x2e 8002abc: f7ff fe09 bl 80026d2 8002ac0: 4603 mov r3, r0 8002ac2: 73fb strb r3, [r7, #15] } return rslt; 8002ac4: f997 300f ldrsb.w r3, [r7, #15] } 8002ac8: 4618 mov r0, r3 8002aca: 3714 adds r7, #20 8002acc: 46bd mov sp, r7 8002ace: bd90 pop {r4, r7, pc} 08002ad0 : /*! * @brief This API is used to read uncompensated mag and temperature data. */ int8_t bmm350_read_uncomp_mag_temp_data(struct bmm350_raw_mag_data *raw_data, struct bmm350_dev *dev) { 8002ad0: b580 push {r7, lr} 8002ad2: b08a sub sp, #40 @ 0x28 8002ad4: af00 add r7, sp, #0 8002ad6: 6078 str r0, [r7, #4] 8002ad8: 6039 str r1, [r7, #0] /* Variable to store the function result */ int8_t rslt; uint8_t mag_data[12] = { 0 }; 8002ada: f107 0308 add.w r3, r7, #8 8002ade: 2200 movs r2, #0 8002ae0: 601a str r2, [r3, #0] 8002ae2: 605a str r2, [r3, #4] 8002ae4: 609a str r2, [r3, #8] uint32_t raw_mag_x, raw_mag_y, raw_mag_z, raw_temp; if (raw_data != NULL) 8002ae6: 687b ldr r3, [r7, #4] 8002ae8: 2b00 cmp r3, #0 8002aea: d06c beq.n 8002bc6 { /* Get uncompensated mag data */ rslt = bmm350_get_regs(BMM350_REG_MAG_X_XLSB, mag_data, BMM350_MAG_TEMP_DATA_LEN, dev); 8002aec: f107 0108 add.w r1, r7, #8 8002af0: 683b ldr r3, [r7, #0] 8002af2: 220c movs r2, #12 8002af4: 2031 movs r0, #49 @ 0x31 8002af6: f7ff fe20 bl 800273a 8002afa: 4603 mov r3, r0 8002afc: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (rslt == BMM350_OK) 8002b00: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 8002b04: 2b00 cmp r3, #0 8002b06: d161 bne.n 8002bcc { raw_mag_x = (uint32_t)mag_data[0] + ((uint32_t)mag_data[1] << 8) + ((uint32_t)mag_data[2] << 16); 8002b08: 7a3b ldrb r3, [r7, #8] 8002b0a: 461a mov r2, r3 8002b0c: 7a7b ldrb r3, [r7, #9] 8002b0e: 021b lsls r3, r3, #8 8002b10: 441a add r2, r3 8002b12: 7abb ldrb r3, [r7, #10] 8002b14: 041b lsls r3, r3, #16 8002b16: 4413 add r3, r2 8002b18: 623b str r3, [r7, #32] raw_mag_y = (uint32_t)mag_data[3] + ((uint32_t)mag_data[4] << 8) + ((uint32_t)mag_data[5] << 16); 8002b1a: 7afb ldrb r3, [r7, #11] 8002b1c: 461a mov r2, r3 8002b1e: 7b3b ldrb r3, [r7, #12] 8002b20: 021b lsls r3, r3, #8 8002b22: 441a add r2, r3 8002b24: 7b7b ldrb r3, [r7, #13] 8002b26: 041b lsls r3, r3, #16 8002b28: 4413 add r3, r2 8002b2a: 61fb str r3, [r7, #28] raw_mag_z = (uint32_t)mag_data[6] + ((uint32_t)mag_data[7] << 8) + ((uint32_t)mag_data[8] << 16); 8002b2c: 7bbb ldrb r3, [r7, #14] 8002b2e: 461a mov r2, r3 8002b30: 7bfb ldrb r3, [r7, #15] 8002b32: 021b lsls r3, r3, #8 8002b34: 441a add r2, r3 8002b36: 7c3b ldrb r3, [r7, #16] 8002b38: 041b lsls r3, r3, #16 8002b3a: 4413 add r3, r2 8002b3c: 61bb str r3, [r7, #24] raw_temp = (uint32_t)mag_data[9] + ((uint32_t)mag_data[10] << 8) + ((uint32_t)mag_data[11] << 16); 8002b3e: 7c7b ldrb r3, [r7, #17] 8002b40: 461a mov r2, r3 8002b42: 7cbb ldrb r3, [r7, #18] 8002b44: 021b lsls r3, r3, #8 8002b46: 441a add r2, r3 8002b48: 7cfb ldrb r3, [r7, #19] 8002b4a: 041b lsls r3, r3, #16 8002b4c: 4413 add r3, r2 8002b4e: 617b str r3, [r7, #20] if ((dev->axis_en & BMM350_EN_X_MSK) == BMM350_DISABLE) 8002b50: 683b ldr r3, [r7, #0] 8002b52: 7d5b ldrb r3, [r3, #21] 8002b54: f003 0301 and.w r3, r3, #1 8002b58: 2b00 cmp r3, #0 8002b5a: d103 bne.n 8002b64 { raw_data->raw_xdata = BMM350_DISABLE; 8002b5c: 687b ldr r3, [r7, #4] 8002b5e: 2200 movs r2, #0 8002b60: 601a str r2, [r3, #0] 8002b62: e006 b.n 8002b72 } else { raw_data->raw_xdata = fix_sign(raw_mag_x, BMM350_SIGNED_24_BIT); 8002b64: 2118 movs r1, #24 8002b66: 6a38 ldr r0, [r7, #32] 8002b68: f000 fade bl 8003128 8002b6c: 4602 mov r2, r0 8002b6e: 687b ldr r3, [r7, #4] 8002b70: 601a str r2, [r3, #0] } if ((dev->axis_en & BMM350_EN_Y_MSK) == BMM350_DISABLE) 8002b72: 683b ldr r3, [r7, #0] 8002b74: 7d5b ldrb r3, [r3, #21] 8002b76: f003 0302 and.w r3, r3, #2 8002b7a: 2b00 cmp r3, #0 8002b7c: d103 bne.n 8002b86 { raw_data->raw_ydata = BMM350_DISABLE; 8002b7e: 687b ldr r3, [r7, #4] 8002b80: 2200 movs r2, #0 8002b82: 605a str r2, [r3, #4] 8002b84: e006 b.n 8002b94 } else { raw_data->raw_ydata = fix_sign(raw_mag_y, BMM350_SIGNED_24_BIT); 8002b86: 2118 movs r1, #24 8002b88: 69f8 ldr r0, [r7, #28] 8002b8a: f000 facd bl 8003128 8002b8e: 4602 mov r2, r0 8002b90: 687b ldr r3, [r7, #4] 8002b92: 605a str r2, [r3, #4] } if ((dev->axis_en & BMM350_EN_Z_MSK) == BMM350_DISABLE) 8002b94: 683b ldr r3, [r7, #0] 8002b96: 7d5b ldrb r3, [r3, #21] 8002b98: f003 0304 and.w r3, r3, #4 8002b9c: 2b00 cmp r3, #0 8002b9e: d103 bne.n 8002ba8 { raw_data->raw_zdata = BMM350_DISABLE; 8002ba0: 687b ldr r3, [r7, #4] 8002ba2: 2200 movs r2, #0 8002ba4: 609a str r2, [r3, #8] 8002ba6: e006 b.n 8002bb6 } else { raw_data->raw_zdata = fix_sign(raw_mag_z, BMM350_SIGNED_24_BIT); 8002ba8: 2118 movs r1, #24 8002baa: 69b8 ldr r0, [r7, #24] 8002bac: f000 fabc bl 8003128 8002bb0: 4602 mov r2, r0 8002bb2: 687b ldr r3, [r7, #4] 8002bb4: 609a str r2, [r3, #8] } raw_data->raw_data_t = fix_sign(raw_temp, BMM350_SIGNED_24_BIT); 8002bb6: 2118 movs r1, #24 8002bb8: 6978 ldr r0, [r7, #20] 8002bba: f000 fab5 bl 8003128 8002bbe: 4602 mov r2, r0 8002bc0: 687b ldr r3, [r7, #4] 8002bc2: 60da str r2, [r3, #12] 8002bc4: e002 b.n 8002bcc } } else { rslt = BMM350_E_NULL_PTR; 8002bc6: 23ff movs r3, #255 @ 0xff 8002bc8: f887 3027 strb.w r3, [r7, #39] @ 0x27 } return rslt; 8002bcc: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 } 8002bd0: 4618 mov r0, r3 8002bd2: 3728 adds r7, #40 @ 0x28 8002bd4: 46bd mov sp, r7 8002bd6: bd80 pop {r7, pc} 08002bd8 : * @brief This API is used to perform the magnetic reset of the sensor * which is necessary after a field shock (400mT field applied to sensor). * It sends flux guide or bit reset to the device in suspend mode. */ int8_t bmm350_magnetic_reset_and_wait(struct bmm350_dev *dev) { 8002bd8: b580 push {r7, lr} 8002bda: b086 sub sp, #24 8002bdc: af00 add r7, sp, #0 8002bde: 6078 str r0, [r7, #4] /* Variable to store the function result */ int8_t rslt; uint8_t pmu_cmd = 0; 8002be0: 2300 movs r3, #0 8002be2: 757b strb r3, [r7, #21] struct bmm350_pmu_cmd_status_0 pmu_cmd_stat_0 = { 0 }; 8002be4: f107 030c add.w r3, r7, #12 8002be8: 2200 movs r2, #0 8002bea: 601a str r2, [r3, #0] 8002bec: 809a strh r2, [r3, #4] uint8_t restore_normal = BMM350_DISABLE; 8002bee: 2300 movs r3, #0 8002bf0: 75bb strb r3, [r7, #22] rslt = null_ptr_check(dev); 8002bf2: 6878 ldr r0, [r7, #4] 8002bf4: f000 fa77 bl 80030e6 8002bf8: 4603 mov r3, r0 8002bfa: 75fb strb r3, [r7, #23] if ((rslt == BMM350_OK) && (dev->mraw_override)) 8002bfc: f997 3017 ldrsb.w r3, [r7, #23] 8002c00: 2b00 cmp r3, #0 8002c02: d10c bne.n 8002c1e 8002c04: 687b ldr r3, [r7, #4] 8002c06: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 8002c0a: 2b00 cmp r3, #0 8002c0c: d007 beq.n 8002c1e { rslt = dev->mraw_override(dev); 8002c0e: 687b ldr r3, [r7, #4] 8002c10: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 8002c14: 6878 ldr r0, [r7, #4] 8002c16: 4798 blx r3 8002c18: 4603 mov r3, r0 8002c1a: 75fb strb r3, [r7, #23] 8002c1c: e081 b.n 8002d22 } else { /* Read PMU CMD status */ rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev); 8002c1e: f107 030c add.w r3, r7, #12 8002c22: 6879 ldr r1, [r7, #4] 8002c24: 4618 mov r0, r3 8002c26: f000 fa15 bl 8003054 8002c2a: 4603 mov r3, r0 8002c2c: 75fb strb r3, [r7, #23] /* Check the powermode is normal before performing magnetic reset */ if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pwr_mode_is_normal == BMM350_ENABLE)) 8002c2e: f997 3017 ldrsb.w r3, [r7, #23] 8002c32: 2b00 cmp r3, #0 8002c34: d10a bne.n 8002c4c 8002c36: 7bfb ldrb r3, [r7, #15] 8002c38: 2b01 cmp r3, #1 8002c3a: d107 bne.n 8002c4c { restore_normal = BMM350_ENABLE; 8002c3c: 2301 movs r3, #1 8002c3e: 75bb strb r3, [r7, #22] /* Reset can only be triggered in suspend */ rslt = bmm350_set_powermode(BMM350_SUSPEND_MODE, dev); 8002c40: 6879 ldr r1, [r7, #4] 8002c42: 2000 movs r0, #0 8002c44: f7ff fde9 bl 800281a 8002c48: 4603 mov r3, r0 8002c4a: 75fb strb r3, [r7, #23] } if (rslt == BMM350_OK) 8002c4c: f997 3017 ldrsb.w r3, [r7, #23] 8002c50: 2b00 cmp r3, #0 8002c52: d115 bne.n 8002c80 { /* Set BR to PMU_CMD register */ pmu_cmd = BMM350_PMU_CMD_BR; 8002c54: 2307 movs r3, #7 8002c56: 757b strb r3, [r7, #21] rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &pmu_cmd, 1, dev); 8002c58: f107 0115 add.w r1, r7, #21 8002c5c: 687b ldr r3, [r7, #4] 8002c5e: 2201 movs r2, #1 8002c60: 2006 movs r0, #6 8002c62: f7ff fd36 bl 80026d2 8002c66: 4603 mov r3, r0 8002c68: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 8002c6a: f997 3017 ldrsb.w r3, [r7, #23] 8002c6e: 2b00 cmp r3, #0 8002c70: d106 bne.n 8002c80 { rslt = bmm350_delay_us(BMM350_BR_DELAY, dev); 8002c72: 6879 ldr r1, [r7, #4] 8002c74: f243 60b0 movw r0, #14000 @ 0x36b0 8002c78: f7ff fdb4 bl 80027e4 8002c7c: 4603 mov r3, r0 8002c7e: 75fb strb r3, [r7, #23] } } if (rslt == BMM350_OK) 8002c80: f997 3017 ldrsb.w r3, [r7, #23] 8002c84: 2b00 cmp r3, #0 8002c86: d110 bne.n 8002caa { /* Verify if PMU_CMD_STATUS_0 register has BR set */ rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev); 8002c88: f107 030c add.w r3, r7, #12 8002c8c: 6879 ldr r1, [r7, #4] 8002c8e: 4618 mov r0, r3 8002c90: f000 f9e0 bl 8003054 8002c94: 4603 mov r3, r0 8002c96: 75fb strb r3, [r7, #23] if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pmu_cmd_value != BMM350_PMU_CMD_STATUS_0_BR)) 8002c98: f997 3017 ldrsb.w r3, [r7, #23] 8002c9c: 2b00 cmp r3, #0 8002c9e: d104 bne.n 8002caa 8002ca0: 7c7b ldrb r3, [r7, #17] 8002ca2: 2b07 cmp r3, #7 8002ca4: d001 beq.n 8002caa { rslt = BMM350_E_PMU_CMD_VALUE; 8002ca6: 23f0 movs r3, #240 @ 0xf0 8002ca8: 75fb strb r3, [r7, #23] } } if (rslt == BMM350_OK) 8002caa: f997 3017 ldrsb.w r3, [r7, #23] 8002cae: 2b00 cmp r3, #0 8002cb0: d115 bne.n 8002cde { /* Set FGR to PMU_CMD register */ pmu_cmd = BMM350_PMU_CMD_FGR; 8002cb2: 2305 movs r3, #5 8002cb4: 757b strb r3, [r7, #21] rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &pmu_cmd, 1, dev); 8002cb6: f107 0115 add.w r1, r7, #21 8002cba: 687b ldr r3, [r7, #4] 8002cbc: 2201 movs r2, #1 8002cbe: 2006 movs r0, #6 8002cc0: f7ff fd07 bl 80026d2 8002cc4: 4603 mov r3, r0 8002cc6: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 8002cc8: f997 3017 ldrsb.w r3, [r7, #23] 8002ccc: 2b00 cmp r3, #0 8002cce: d106 bne.n 8002cde { rslt = bmm350_delay_us(BMM350_FGR_DELAY, dev); 8002cd0: 6879 ldr r1, [r7, #4] 8002cd2: f244 6050 movw r0, #18000 @ 0x4650 8002cd6: f7ff fd85 bl 80027e4 8002cda: 4603 mov r3, r0 8002cdc: 75fb strb r3, [r7, #23] } } if (rslt == BMM350_OK) 8002cde: f997 3017 ldrsb.w r3, [r7, #23] 8002ce2: 2b00 cmp r3, #0 8002ce4: d110 bne.n 8002d08 { /* Verify if PMU_CMD_STATUS_0 register has FGR set */ rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev); 8002ce6: f107 030c add.w r3, r7, #12 8002cea: 6879 ldr r1, [r7, #4] 8002cec: 4618 mov r0, r3 8002cee: f000 f9b1 bl 8003054 8002cf2: 4603 mov r3, r0 8002cf4: 75fb strb r3, [r7, #23] if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pmu_cmd_value != BMM350_PMU_CMD_STATUS_0_FGR)) 8002cf6: f997 3017 ldrsb.w r3, [r7, #23] 8002cfa: 2b00 cmp r3, #0 8002cfc: d104 bne.n 8002d08 8002cfe: 7c7b ldrb r3, [r7, #17] 8002d00: 2b05 cmp r3, #5 8002d02: d001 beq.n 8002d08 { rslt = BMM350_E_PMU_CMD_VALUE; 8002d04: 23f0 movs r3, #240 @ 0xf0 8002d06: 75fb strb r3, [r7, #23] } } if ((rslt == BMM350_OK) && (restore_normal == BMM350_ENABLE)) 8002d08: f997 3017 ldrsb.w r3, [r7, #23] 8002d0c: 2b00 cmp r3, #0 8002d0e: d108 bne.n 8002d22 8002d10: 7dbb ldrb r3, [r7, #22] 8002d12: 2b01 cmp r3, #1 8002d14: d105 bne.n 8002d22 { rslt = bmm350_set_powermode(BMM350_NORMAL_MODE, dev); 8002d16: 6879 ldr r1, [r7, #4] 8002d18: 2001 movs r0, #1 8002d1a: f7ff fd7e bl 800281a 8002d1e: 4603 mov r3, r0 8002d20: 75fb strb r3, [r7, #23] } } return rslt; 8002d22: f997 3017 ldrsb.w r3, [r7, #23] } 8002d26: 4618 mov r0, r3 8002d28: 3718 adds r7, #24 8002d2a: 46bd mov sp, r7 8002d2c: bd80 pop {r7, pc} 08002d2e : /*! * @brief This API is used to perform compensation for raw magnetometer and temperature data. */ int8_t bmm350_get_compensated_mag_xyz_temp_data(struct bmm350_mag_temp_data *mag_temp_data, struct bmm350_dev *dev) { 8002d2e: b580 push {r7, lr} 8002d30: b096 sub sp, #88 @ 0x58 8002d32: af00 add r7, sp, #0 8002d34: 6078 str r0, [r7, #4] 8002d36: 6039 str r1, [r7, #0] /* Variable to store the function result */ int8_t rslt; uint8_t indx; float out_data[4] = { 0.0f }; 8002d38: f107 0338 add.w r3, r7, #56 @ 0x38 8002d3c: 2200 movs r2, #0 8002d3e: 601a str r2, [r3, #0] 8002d40: 605a str r2, [r3, #4] 8002d42: 609a str r2, [r3, #8] 8002d44: 60da str r2, [r3, #12] float dut_offset_coef[3], dut_sensit_coef[3], dut_tco[3], dut_tcs[3]; float cr_ax_comp_x, cr_ax_comp_y, cr_ax_comp_z; if (mag_temp_data != NULL) 8002d46: 687b ldr r3, [r7, #4] 8002d48: 2b00 cmp r3, #0 8002d4a: f000 817a beq.w 8003042 { /* Reads raw magnetic x,y and z axis along with temperature */ rslt = read_out_raw_data(out_data, dev); 8002d4e: f107 0338 add.w r3, r7, #56 @ 0x38 8002d52: 6839 ldr r1, [r7, #0] 8002d54: 4618 mov r0, r3 8002d56: f000 fc9f bl 8003698 8002d5a: 4603 mov r3, r0 8002d5c: f887 3057 strb.w r3, [r7, #87] @ 0x57 if (rslt == BMM350_OK) 8002d60: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57 8002d64: 2b00 cmp r3, #0 8002d66: f040 813a bne.w 8002fde { /* Apply compensation to temperature reading */ out_data[3] = (1 + dev->mag_comp.dut_sensit_coef.t_sens) * out_data[3] + 8002d6a: 683b ldr r3, [r7, #0] 8002d6c: edd3 7a0a vldr s15, [r3, #40] @ 0x28 8002d70: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8002d74: ee37 7a87 vadd.f32 s14, s15, s14 8002d78: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8002d7c: ee27 7a27 vmul.f32 s14, s14, s15 dev->mag_comp.dut_offset_coef.t_offs; 8002d80: 683b ldr r3, [r7, #0] 8002d82: edd3 7a06 vldr s15, [r3, #24] out_data[3] = (1 + dev->mag_comp.dut_sensit_coef.t_sens) * out_data[3] + 8002d86: ee77 7a27 vadd.f32 s15, s14, s15 8002d8a: edc7 7a11 vstr s15, [r7, #68] @ 0x44 /* Store magnetic compensation structure to an array */ dut_offset_coef[0] = dev->mag_comp.dut_offset_coef.offset_x; 8002d8e: 683b ldr r3, [r7, #0] 8002d90: 69db ldr r3, [r3, #28] 8002d92: 62fb str r3, [r7, #44] @ 0x2c dut_offset_coef[1] = dev->mag_comp.dut_offset_coef.offset_y; 8002d94: 683b ldr r3, [r7, #0] 8002d96: 6a1b ldr r3, [r3, #32] 8002d98: 633b str r3, [r7, #48] @ 0x30 dut_offset_coef[2] = dev->mag_comp.dut_offset_coef.offset_z; 8002d9a: 683b ldr r3, [r7, #0] 8002d9c: 6a5b ldr r3, [r3, #36] @ 0x24 8002d9e: 637b str r3, [r7, #52] @ 0x34 dut_sensit_coef[0] = dev->mag_comp.dut_sensit_coef.sens_x; 8002da0: 683b ldr r3, [r7, #0] 8002da2: 6adb ldr r3, [r3, #44] @ 0x2c 8002da4: 623b str r3, [r7, #32] dut_sensit_coef[1] = dev->mag_comp.dut_sensit_coef.sens_y; 8002da6: 683b ldr r3, [r7, #0] 8002da8: 6b1b ldr r3, [r3, #48] @ 0x30 8002daa: 627b str r3, [r7, #36] @ 0x24 dut_sensit_coef[2] = dev->mag_comp.dut_sensit_coef.sens_z; 8002dac: 683b ldr r3, [r7, #0] 8002dae: 6b5b ldr r3, [r3, #52] @ 0x34 8002db0: 62bb str r3, [r7, #40] @ 0x28 dut_tco[0] = dev->mag_comp.dut_tco.tco_x; 8002db2: 683b ldr r3, [r7, #0] 8002db4: 6b9b ldr r3, [r3, #56] @ 0x38 8002db6: 617b str r3, [r7, #20] dut_tco[1] = dev->mag_comp.dut_tco.tco_y; 8002db8: 683b ldr r3, [r7, #0] 8002dba: 6bdb ldr r3, [r3, #60] @ 0x3c 8002dbc: 61bb str r3, [r7, #24] dut_tco[2] = dev->mag_comp.dut_tco.tco_z; 8002dbe: 683b ldr r3, [r7, #0] 8002dc0: 6c1b ldr r3, [r3, #64] @ 0x40 8002dc2: 61fb str r3, [r7, #28] dut_tcs[0] = dev->mag_comp.dut_tcs.tcs_x; 8002dc4: 683b ldr r3, [r7, #0] 8002dc6: 6c5b ldr r3, [r3, #68] @ 0x44 8002dc8: 60bb str r3, [r7, #8] dut_tcs[1] = dev->mag_comp.dut_tcs.tcs_y; 8002dca: 683b ldr r3, [r7, #0] 8002dcc: 6c9b ldr r3, [r3, #72] @ 0x48 8002dce: 60fb str r3, [r7, #12] dut_tcs[2] = dev->mag_comp.dut_tcs.tcs_z; 8002dd0: 683b ldr r3, [r7, #0] 8002dd2: 6cdb ldr r3, [r3, #76] @ 0x4c 8002dd4: 613b str r3, [r7, #16] /* Compensate raw magnetic data */ for (indx = 0; indx < 3; indx++) 8002dd6: 2300 movs r3, #0 8002dd8: f887 3056 strb.w r3, [r7, #86] @ 0x56 8002ddc: e086 b.n 8002eec { out_data[indx] *= 1 + dut_sensit_coef[indx]; 8002dde: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002de2: 009b lsls r3, r3, #2 8002de4: 3358 adds r3, #88 @ 0x58 8002de6: 443b add r3, r7 8002de8: 3b20 subs r3, #32 8002dea: ed93 7a00 vldr s14, [r3] 8002dee: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002df2: 009b lsls r3, r3, #2 8002df4: 3358 adds r3, #88 @ 0x58 8002df6: 443b add r3, r7 8002df8: 3b38 subs r3, #56 @ 0x38 8002dfa: edd3 7a00 vldr s15, [r3] 8002dfe: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8002e02: ee77 7aa6 vadd.f32 s15, s15, s13 8002e06: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002e0a: ee67 7a27 vmul.f32 s15, s14, s15 8002e0e: 009b lsls r3, r3, #2 8002e10: 3358 adds r3, #88 @ 0x58 8002e12: 443b add r3, r7 8002e14: 3b20 subs r3, #32 8002e16: edc3 7a00 vstr s15, [r3] out_data[indx] += dut_offset_coef[indx]; 8002e1a: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002e1e: 009b lsls r3, r3, #2 8002e20: 3358 adds r3, #88 @ 0x58 8002e22: 443b add r3, r7 8002e24: 3b20 subs r3, #32 8002e26: ed93 7a00 vldr s14, [r3] 8002e2a: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002e2e: 009b lsls r3, r3, #2 8002e30: 3358 adds r3, #88 @ 0x58 8002e32: 443b add r3, r7 8002e34: 3b2c subs r3, #44 @ 0x2c 8002e36: edd3 7a00 vldr s15, [r3] 8002e3a: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002e3e: ee77 7a27 vadd.f32 s15, s14, s15 8002e42: 009b lsls r3, r3, #2 8002e44: 3358 adds r3, #88 @ 0x58 8002e46: 443b add r3, r7 8002e48: 3b20 subs r3, #32 8002e4a: edc3 7a00 vstr s15, [r3] out_data[indx] += dut_tco[indx] * (out_data[3] - dev->mag_comp.dut_t0); 8002e4e: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002e52: 009b lsls r3, r3, #2 8002e54: 3358 adds r3, #88 @ 0x58 8002e56: 443b add r3, r7 8002e58: 3b20 subs r3, #32 8002e5a: ed93 7a00 vldr s14, [r3] 8002e5e: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002e62: 009b lsls r3, r3, #2 8002e64: 3358 adds r3, #88 @ 0x58 8002e66: 443b add r3, r7 8002e68: 3b44 subs r3, #68 @ 0x44 8002e6a: edd3 6a00 vldr s13, [r3] 8002e6e: ed97 6a11 vldr s12, [r7, #68] @ 0x44 8002e72: 683b ldr r3, [r7, #0] 8002e74: edd3 7a14 vldr s15, [r3, #80] @ 0x50 8002e78: ee76 7a67 vsub.f32 s15, s12, s15 8002e7c: ee66 7aa7 vmul.f32 s15, s13, s15 8002e80: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002e84: ee77 7a27 vadd.f32 s15, s14, s15 8002e88: 009b lsls r3, r3, #2 8002e8a: 3358 adds r3, #88 @ 0x58 8002e8c: 443b add r3, r7 8002e8e: 3b20 subs r3, #32 8002e90: edc3 7a00 vstr s15, [r3] out_data[indx] /= 1 + dut_tcs[indx] * (out_data[3] - dev->mag_comp.dut_t0); 8002e94: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002e98: 009b lsls r3, r3, #2 8002e9a: 3358 adds r3, #88 @ 0x58 8002e9c: 443b add r3, r7 8002e9e: 3b20 subs r3, #32 8002ea0: edd3 6a00 vldr s13, [r3] 8002ea4: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002ea8: 009b lsls r3, r3, #2 8002eaa: 3358 adds r3, #88 @ 0x58 8002eac: 443b add r3, r7 8002eae: 3b50 subs r3, #80 @ 0x50 8002eb0: ed93 7a00 vldr s14, [r3] 8002eb4: ed97 6a11 vldr s12, [r7, #68] @ 0x44 8002eb8: 683b ldr r3, [r7, #0] 8002eba: edd3 7a14 vldr s15, [r3, #80] @ 0x50 8002ebe: ee76 7a67 vsub.f32 s15, s12, s15 8002ec2: ee67 7a27 vmul.f32 s15, s14, s15 8002ec6: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8002eca: ee37 7a87 vadd.f32 s14, s15, s14 8002ece: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002ed2: eec6 7a87 vdiv.f32 s15, s13, s14 8002ed6: 009b lsls r3, r3, #2 8002ed8: 3358 adds r3, #88 @ 0x58 8002eda: 443b add r3, r7 8002edc: 3b20 subs r3, #32 8002ede: edc3 7a00 vstr s15, [r3] for (indx = 0; indx < 3; indx++) 8002ee2: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002ee6: 3301 adds r3, #1 8002ee8: f887 3056 strb.w r3, [r7, #86] @ 0x56 8002eec: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002ef0: 2b02 cmp r3, #2 8002ef2: f67f af74 bls.w 8002dde } cr_ax_comp_x = (out_data[0] - dev->mag_comp.cross_axis.cross_x_y * out_data[1]) / 8002ef6: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8002efa: 683b ldr r3, [r7, #0] 8002efc: edd3 6a15 vldr s13, [r3, #84] @ 0x54 8002f00: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8002f04: ee66 7aa7 vmul.f32 s15, s13, s15 8002f08: ee77 6a67 vsub.f32 s13, s14, s15 (1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y); 8002f0c: 683b ldr r3, [r7, #0] 8002f0e: ed93 7a16 vldr s14, [r3, #88] @ 0x58 8002f12: 683b ldr r3, [r7, #0] 8002f14: edd3 7a15 vldr s15, [r3, #84] @ 0x54 8002f18: ee67 7a27 vmul.f32 s15, s14, s15 8002f1c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8002f20: ee37 7a67 vsub.f32 s14, s14, s15 cr_ax_comp_x = (out_data[0] - dev->mag_comp.cross_axis.cross_x_y * out_data[1]) / 8002f24: eec6 7a87 vdiv.f32 s15, s13, s14 8002f28: edc7 7a14 vstr s15, [r7, #80] @ 0x50 cr_ax_comp_y = (out_data[1] - dev->mag_comp.cross_axis.cross_y_x * out_data[0]) / 8002f2c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8002f30: 683b ldr r3, [r7, #0] 8002f32: edd3 6a16 vldr s13, [r3, #88] @ 0x58 8002f36: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8002f3a: ee66 7aa7 vmul.f32 s15, s13, s15 8002f3e: ee77 6a67 vsub.f32 s13, s14, s15 (1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y); 8002f42: 683b ldr r3, [r7, #0] 8002f44: ed93 7a16 vldr s14, [r3, #88] @ 0x58 8002f48: 683b ldr r3, [r7, #0] 8002f4a: edd3 7a15 vldr s15, [r3, #84] @ 0x54 8002f4e: ee67 7a27 vmul.f32 s15, s14, s15 8002f52: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8002f56: ee37 7a67 vsub.f32 s14, s14, s15 cr_ax_comp_y = (out_data[1] - dev->mag_comp.cross_axis.cross_y_x * out_data[0]) / 8002f5a: eec6 7a87 vdiv.f32 s15, s13, s14 8002f5e: edc7 7a13 vstr s15, [r7, #76] @ 0x4c cr_ax_comp_z = (out_data[2] + 8002f62: ed97 7a10 vldr s14, [r7, #64] @ 0x40 (out_data[0] * 8002f66: edd7 6a0e vldr s13, [r7, #56] @ 0x38 (dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_z_y - 8002f6a: 683b ldr r3, [r7, #0] 8002f6c: ed93 6a16 vldr s12, [r3, #88] @ 0x58 8002f70: 683b ldr r3, [r7, #0] 8002f72: edd3 7a18 vldr s15, [r3, #96] @ 0x60 8002f76: ee26 6a27 vmul.f32 s12, s12, s15 dev->mag_comp.cross_axis.cross_z_x) - out_data[1] * 8002f7a: 683b ldr r3, [r7, #0] 8002f7c: edd3 7a17 vldr s15, [r3, #92] @ 0x5c (dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_z_y - 8002f80: ee76 7a67 vsub.f32 s15, s12, s15 (out_data[0] * 8002f84: ee66 6aa7 vmul.f32 s13, s13, s15 dev->mag_comp.cross_axis.cross_z_x) - out_data[1] * 8002f88: ed97 6a0f vldr s12, [r7, #60] @ 0x3c (dev->mag_comp.cross_axis.cross_z_y - dev->mag_comp.cross_axis.cross_x_y * 8002f8c: 683b ldr r3, [r7, #0] 8002f8e: edd3 5a18 vldr s11, [r3, #96] @ 0x60 8002f92: 683b ldr r3, [r7, #0] 8002f94: ed93 5a15 vldr s10, [r3, #84] @ 0x54 dev->mag_comp.cross_axis.cross_z_x)) / 8002f98: 683b ldr r3, [r7, #0] 8002f9a: edd3 7a17 vldr s15, [r3, #92] @ 0x5c (dev->mag_comp.cross_axis.cross_z_y - dev->mag_comp.cross_axis.cross_x_y * 8002f9e: ee65 7a27 vmul.f32 s15, s10, s15 8002fa2: ee75 7ae7 vsub.f32 s15, s11, s15 dev->mag_comp.cross_axis.cross_z_x) - out_data[1] * 8002fa6: ee66 7a27 vmul.f32 s15, s12, s15 8002faa: ee36 6ae7 vsub.f32 s12, s13, s15 (1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y)); 8002fae: 683b ldr r3, [r7, #0] 8002fb0: edd3 6a16 vldr s13, [r3, #88] @ 0x58 8002fb4: 683b ldr r3, [r7, #0] 8002fb6: edd3 7a15 vldr s15, [r3, #84] @ 0x54 8002fba: ee66 7aa7 vmul.f32 s15, s13, s15 8002fbe: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8002fc2: ee76 6ae7 vsub.f32 s13, s13, s15 dev->mag_comp.cross_axis.cross_z_x)) / 8002fc6: eec6 7a26 vdiv.f32 s15, s12, s13 cr_ax_comp_z = 8002fca: ee77 7a27 vadd.f32 s15, s14, s15 8002fce: edc7 7a12 vstr s15, [r7, #72] @ 0x48 out_data[0] = cr_ax_comp_x; 8002fd2: 6d3b ldr r3, [r7, #80] @ 0x50 8002fd4: 63bb str r3, [r7, #56] @ 0x38 out_data[1] = cr_ax_comp_y; 8002fd6: 6cfb ldr r3, [r7, #76] @ 0x4c 8002fd8: 63fb str r3, [r7, #60] @ 0x3c out_data[2] = cr_ax_comp_z; 8002fda: 6cbb ldr r3, [r7, #72] @ 0x48 8002fdc: 643b str r3, [r7, #64] @ 0x40 } if (rslt == BMM350_OK) 8002fde: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57 8002fe2: 2b00 cmp r3, #0 8002fe4: d130 bne.n 8003048 { if ((dev->axis_en & BMM350_EN_X_MSK) == BMM350_DISABLE) 8002fe6: 683b ldr r3, [r7, #0] 8002fe8: 7d5b ldrb r3, [r3, #21] 8002fea: f003 0301 and.w r3, r3, #1 8002fee: 2b00 cmp r3, #0 8002ff0: d104 bne.n 8002ffc { mag_temp_data->x = BMM350_DISABLE; 8002ff2: 687b ldr r3, [r7, #4] 8002ff4: f04f 0200 mov.w r2, #0 8002ff8: 601a str r2, [r3, #0] 8002ffa: e002 b.n 8003002 } else { mag_temp_data->x = out_data[0]; 8002ffc: 6bba ldr r2, [r7, #56] @ 0x38 8002ffe: 687b ldr r3, [r7, #4] 8003000: 601a str r2, [r3, #0] } if ((dev->axis_en & BMM350_EN_Y_MSK) == BMM350_DISABLE) 8003002: 683b ldr r3, [r7, #0] 8003004: 7d5b ldrb r3, [r3, #21] 8003006: f003 0302 and.w r3, r3, #2 800300a: 2b00 cmp r3, #0 800300c: d104 bne.n 8003018 { mag_temp_data->y = BMM350_DISABLE; 800300e: 687b ldr r3, [r7, #4] 8003010: f04f 0200 mov.w r2, #0 8003014: 605a str r2, [r3, #4] 8003016: e002 b.n 800301e } else { mag_temp_data->y = out_data[1]; 8003018: 6bfa ldr r2, [r7, #60] @ 0x3c 800301a: 687b ldr r3, [r7, #4] 800301c: 605a str r2, [r3, #4] } if ((dev->axis_en & BMM350_EN_Z_MSK) == BMM350_DISABLE) 800301e: 683b ldr r3, [r7, #0] 8003020: 7d5b ldrb r3, [r3, #21] 8003022: f003 0304 and.w r3, r3, #4 8003026: 2b00 cmp r3, #0 8003028: d104 bne.n 8003034 { mag_temp_data->z = BMM350_DISABLE; 800302a: 687b ldr r3, [r7, #4] 800302c: f04f 0200 mov.w r2, #0 8003030: 609a str r2, [r3, #8] 8003032: e002 b.n 800303a } else { mag_temp_data->z = out_data[2]; 8003034: 6c3a ldr r2, [r7, #64] @ 0x40 8003036: 687b ldr r3, [r7, #4] 8003038: 609a str r2, [r3, #8] } mag_temp_data->temperature = out_data[3]; 800303a: 6c7a ldr r2, [r7, #68] @ 0x44 800303c: 687b ldr r3, [r7, #4] 800303e: 60da str r2, [r3, #12] 8003040: e002 b.n 8003048 } } else { rslt = BMM350_E_NULL_PTR; 8003042: 23ff movs r3, #255 @ 0xff 8003044: f887 3057 strb.w r3, [r7, #87] @ 0x57 } return rslt; 8003048: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57 } 800304c: 4618 mov r0, r3 800304e: 3758 adds r7, #88 @ 0x58 8003050: 46bd mov sp, r7 8003052: bd80 pop {r7, pc} 08003054 : /*! * @brief This API gets the PMU command status 0 value */ int8_t bmm350_get_pmu_cmd_status_0(struct bmm350_pmu_cmd_status_0 *pmu_cmd_stat_0, struct bmm350_dev *dev) { 8003054: b580 push {r7, lr} 8003056: b084 sub sp, #16 8003058: af00 add r7, sp, #0 800305a: 6078 str r0, [r7, #4] 800305c: 6039 str r1, [r7, #0] /* Variable to store the function result */ int8_t rslt; uint8_t reg_data; if (pmu_cmd_stat_0 != NULL) 800305e: 687b ldr r3, [r7, #4] 8003060: 2b00 cmp r3, #0 8003062: d038 beq.n 80030d6 { /* Get PMU command status 0 data */ rslt = bmm350_get_regs(BMM350_REG_PMU_CMD_STATUS_0, ®_data, 1, dev); 8003064: f107 010e add.w r1, r7, #14 8003068: 683b ldr r3, [r7, #0] 800306a: 2201 movs r2, #1 800306c: 2007 movs r0, #7 800306e: f7ff fb64 bl 800273a 8003072: 4603 mov r3, r0 8003074: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8003076: f997 300f ldrsb.w r3, [r7, #15] 800307a: 2b00 cmp r3, #0 800307c: d12d bne.n 80030da { pmu_cmd_stat_0->pmu_cmd_busy = BMM350_GET_BITS_POS_0(reg_data, BMM350_PMU_CMD_BUSY); 800307e: 7bbb ldrb r3, [r7, #14] 8003080: f003 0301 and.w r3, r3, #1 8003084: b2da uxtb r2, r3 8003086: 687b ldr r3, [r7, #4] 8003088: 701a strb r2, [r3, #0] pmu_cmd_stat_0->odr_ovwr = BMM350_GET_BITS(reg_data, BMM350_ODR_OVWR); 800308a: 7bbb ldrb r3, [r7, #14] 800308c: 105b asrs r3, r3, #1 800308e: b2db uxtb r3, r3 8003090: f003 0301 and.w r3, r3, #1 8003094: b2da uxtb r2, r3 8003096: 687b ldr r3, [r7, #4] 8003098: 705a strb r2, [r3, #1] pmu_cmd_stat_0->avr_ovwr = BMM350_GET_BITS(reg_data, BMM350_AVG_OVWR); 800309a: 7bbb ldrb r3, [r7, #14] 800309c: 109b asrs r3, r3, #2 800309e: b2db uxtb r3, r3 80030a0: f003 0301 and.w r3, r3, #1 80030a4: b2da uxtb r2, r3 80030a6: 687b ldr r3, [r7, #4] 80030a8: 709a strb r2, [r3, #2] pmu_cmd_stat_0->pwr_mode_is_normal = BMM350_GET_BITS(reg_data, BMM350_PWR_MODE_IS_NORMAL); 80030aa: 7bbb ldrb r3, [r7, #14] 80030ac: 10db asrs r3, r3, #3 80030ae: b2db uxtb r3, r3 80030b0: f003 0301 and.w r3, r3, #1 80030b4: b2da uxtb r2, r3 80030b6: 687b ldr r3, [r7, #4] 80030b8: 70da strb r2, [r3, #3] pmu_cmd_stat_0->cmd_is_illegal = BMM350_GET_BITS(reg_data, BMM350_CMD_IS_ILLEGAL); 80030ba: 7bbb ldrb r3, [r7, #14] 80030bc: 111b asrs r3, r3, #4 80030be: b2db uxtb r3, r3 80030c0: f003 0301 and.w r3, r3, #1 80030c4: b2da uxtb r2, r3 80030c6: 687b ldr r3, [r7, #4] 80030c8: 711a strb r2, [r3, #4] pmu_cmd_stat_0->pmu_cmd_value = BMM350_GET_BITS(reg_data, BMM350_PMU_CMD_VALUE); 80030ca: 7bbb ldrb r3, [r7, #14] 80030cc: 095b lsrs r3, r3, #5 80030ce: b2da uxtb r2, r3 80030d0: 687b ldr r3, [r7, #4] 80030d2: 715a strb r2, [r3, #5] 80030d4: e001 b.n 80030da } } else { rslt = BMM350_E_NULL_PTR; 80030d6: 23ff movs r3, #255 @ 0xff 80030d8: 73fb strb r3, [r7, #15] } return rslt; 80030da: f997 300f ldrsb.w r3, [r7, #15] } 80030de: 4618 mov r0, r3 80030e0: 3710 adds r7, #16 80030e2: 46bd mov sp, r7 80030e4: bd80 pop {r7, pc} 080030e6 : /*! * @brief This internal API is used to validate the device structure pointer for * null conditions. */ static int8_t null_ptr_check(const struct bmm350_dev *dev) { 80030e6: b480 push {r7} 80030e8: b085 sub sp, #20 80030ea: af00 add r7, sp, #0 80030ec: 6078 str r0, [r7, #4] /* Variable to store the function result */ int8_t rslt; if ((dev == NULL) || (dev->read == NULL) || (dev->write == NULL) || (dev->delay_us == NULL)) 80030ee: 687b ldr r3, [r7, #4] 80030f0: 2b00 cmp r3, #0 80030f2: d00b beq.n 800310c 80030f4: 687b ldr r3, [r7, #4] 80030f6: 689b ldr r3, [r3, #8] 80030f8: 2b00 cmp r3, #0 80030fa: d007 beq.n 800310c 80030fc: 687b ldr r3, [r7, #4] 80030fe: 68db ldr r3, [r3, #12] 8003100: 2b00 cmp r3, #0 8003102: d003 beq.n 800310c 8003104: 687b ldr r3, [r7, #4] 8003106: 691b ldr r3, [r3, #16] 8003108: 2b00 cmp r3, #0 800310a: d102 bne.n 8003112 { /* Device structure pointer is not valid */ rslt = BMM350_E_NULL_PTR; 800310c: 23ff movs r3, #255 @ 0xff 800310e: 73fb strb r3, [r7, #15] 8003110: e001 b.n 8003116 } else { /* Device structure is fine */ rslt = BMM350_OK; 8003112: 2300 movs r3, #0 8003114: 73fb strb r3, [r7, #15] } return rslt; 8003116: f997 300f ldrsb.w r3, [r7, #15] } 800311a: 4618 mov r0, r3 800311c: 3714 adds r7, #20 800311e: 46bd mov sp, r7 8003120: f85d 7b04 ldr.w r7, [sp], #4 8003124: 4770 bx lr ... 08003128 : /*! * @brief This internal API converts the raw data from the IC data registers to signed integer */ static int32_t fix_sign(uint32_t inval, int8_t number_of_bits) { 8003128: b480 push {r7} 800312a: b085 sub sp, #20 800312c: af00 add r7, sp, #0 800312e: 6078 str r0, [r7, #4] 8003130: 460b mov r3, r1 8003132: 70fb strb r3, [r7, #3] int32_t power = 0; 8003134: 2300 movs r3, #0 8003136: 60fb str r3, [r7, #12] int32_t retval; switch (number_of_bits) 8003138: f997 3003 ldrsb.w r3, [r7, #3] 800313c: 3b08 subs r3, #8 800313e: 2b10 cmp r3, #16 8003140: d837 bhi.n 80031b2 8003142: a201 add r2, pc, #4 @ (adr r2, 8003148 ) 8003144: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003148: 0800318d .word 0x0800318d 800314c: 080031b3 .word 0x080031b3 8003150: 080031b3 .word 0x080031b3 8003154: 080031b3 .word 0x080031b3 8003158: 08003193 .word 0x08003193 800315c: 080031b3 .word 0x080031b3 8003160: 080031b3 .word 0x080031b3 8003164: 080031b3 .word 0x080031b3 8003168: 0800319b .word 0x0800319b 800316c: 080031b3 .word 0x080031b3 8003170: 080031b3 .word 0x080031b3 8003174: 080031b3 .word 0x080031b3 8003178: 080031b3 .word 0x080031b3 800317c: 080031a3 .word 0x080031a3 8003180: 080031b3 .word 0x080031b3 8003184: 080031b3 .word 0x080031b3 8003188: 080031ab .word 0x080031ab { case BMM350_SIGNED_8_BIT: power = 128; /* 2^7 */ 800318c: 2380 movs r3, #128 @ 0x80 800318e: 60fb str r3, [r7, #12] break; 8003190: e012 b.n 80031b8 case BMM350_SIGNED_12_BIT: power = 2048; /* 2^11 */ 8003192: f44f 6300 mov.w r3, #2048 @ 0x800 8003196: 60fb str r3, [r7, #12] break; 8003198: e00e b.n 80031b8 case BMM350_SIGNED_16_BIT: power = 32768; /* 2^15 */ 800319a: f44f 4300 mov.w r3, #32768 @ 0x8000 800319e: 60fb str r3, [r7, #12] break; 80031a0: e00a b.n 80031b8 case BMM350_SIGNED_21_BIT: power = 1048576; /* 2^20 */ 80031a2: f44f 1380 mov.w r3, #1048576 @ 0x100000 80031a6: 60fb str r3, [r7, #12] break; 80031a8: e006 b.n 80031b8 case BMM350_SIGNED_24_BIT: power = 8388608; /* 2^23 */ 80031aa: f44f 0300 mov.w r3, #8388608 @ 0x800000 80031ae: 60fb str r3, [r7, #12] break; 80031b0: e002 b.n 80031b8 default: power = 0; 80031b2: 2300 movs r3, #0 80031b4: 60fb str r3, [r7, #12] break; 80031b6: bf00 nop } retval = (int32_t)inval; 80031b8: 687b ldr r3, [r7, #4] 80031ba: 60bb str r3, [r7, #8] if (retval >= power) 80031bc: 68ba ldr r2, [r7, #8] 80031be: 68fb ldr r3, [r7, #12] 80031c0: 429a cmp r2, r3 80031c2: db04 blt.n 80031ce { retval = retval - (power * 2); 80031c4: 68fb ldr r3, [r7, #12] 80031c6: 005b lsls r3, r3, #1 80031c8: 68ba ldr r2, [r7, #8] 80031ca: 1ad3 subs r3, r2, r3 80031cc: 60bb str r3, [r7, #8] } return retval; 80031ce: 68bb ldr r3, [r7, #8] } 80031d0: 4618 mov r0, r3 80031d2: 3714 adds r7, #20 80031d4: 46bd mov sp, r7 80031d6: f85d 7b04 ldr.w r7, [sp], #4 80031da: 4770 bx lr 080031dc : /*! * @brief This internal API is used to read OTP word */ static int8_t read_otp_word(uint8_t addr, uint16_t *lsb_msb, struct bmm350_dev *dev) { 80031dc: b580 push {r7, lr} 80031de: b086 sub sp, #24 80031e0: af00 add r7, sp, #0 80031e2: 4603 mov r3, r0 80031e4: 60b9 str r1, [r7, #8] 80031e6: 607a str r2, [r7, #4] 80031e8: 73fb strb r3, [r7, #15] /* Variable to store the function result */ int8_t rslt; uint8_t otp_cmd, otp_status = 0, otp_err = BMM350_OTP_STATUS_NO_ERROR, lsb = 0, msb = 0; 80031ea: 2300 movs r3, #0 80031ec: 753b strb r3, [r7, #20] 80031ee: 2300 movs r3, #0 80031f0: 75bb strb r3, [r7, #22] 80031f2: 2300 movs r3, #0 80031f4: 74fb strb r3, [r7, #19] 80031f6: 2300 movs r3, #0 80031f8: 74bb strb r3, [r7, #18] if (lsb_msb != NULL) 80031fa: 68bb ldr r3, [r7, #8] 80031fc: 2b00 cmp r3, #0 80031fe: f000 8087 beq.w 8003310 { /* Set OTP command at specified address */ otp_cmd = BMM350_OTP_CMD_DIR_READ | (addr & BMM350_OTP_WORD_ADDR_MSK); 8003202: f997 300f ldrsb.w r3, [r7, #15] 8003206: f003 031f and.w r3, r3, #31 800320a: b25b sxtb r3, r3 800320c: f043 0320 orr.w r3, r3, #32 8003210: b25b sxtb r3, r3 8003212: b2db uxtb r3, r3 8003214: 757b strb r3, [r7, #21] rslt = bmm350_set_regs(BMM350_REG_OTP_CMD_REG, &otp_cmd, 1, dev); 8003216: f107 0115 add.w r1, r7, #21 800321a: 687b ldr r3, [r7, #4] 800321c: 2201 movs r2, #1 800321e: 2050 movs r0, #80 @ 0x50 8003220: f7ff fa57 bl 80026d2 8003224: 4603 mov r3, r0 8003226: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 8003228: f997 3017 ldrsb.w r3, [r7, #23] 800322c: 2b00 cmp r3, #0 800322e: d14c bne.n 80032ca { do { rslt = bmm350_delay_us(300, dev); 8003230: 6879 ldr r1, [r7, #4] 8003232: f44f 7096 mov.w r0, #300 @ 0x12c 8003236: f7ff fad5 bl 80027e4 800323a: 4603 mov r3, r0 800323c: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 800323e: f997 3017 ldrsb.w r3, [r7, #23] 8003242: 2b00 cmp r3, #0 8003244: d10f bne.n 8003266 { /* Get OTP status */ rslt = bmm350_get_regs(BMM350_REG_OTP_STATUS_REG, &otp_status, 1, dev); 8003246: f107 0114 add.w r1, r7, #20 800324a: 687b ldr r3, [r7, #4] 800324c: 2201 movs r2, #1 800324e: 2055 movs r0, #85 @ 0x55 8003250: f7ff fa73 bl 800273a 8003254: 4603 mov r3, r0 8003256: 75fb strb r3, [r7, #23] otp_err = BMM350_OTP_STATUS_ERROR(otp_status); 8003258: 7d3b ldrb r3, [r7, #20] 800325a: f023 031f bic.w r3, r3, #31 800325e: 75bb strb r3, [r7, #22] if (otp_err != BMM350_OTP_STATUS_NO_ERROR) 8003260: 7dbb ldrb r3, [r7, #22] 8003262: 2b00 cmp r3, #0 8003264: d109 bne.n 800327a { break; } } } while ((!(otp_status & BMM350_OTP_STATUS_CMD_DONE)) && (rslt == BMM350_OK)); 8003266: 7d3b ldrb r3, [r7, #20] 8003268: f003 0301 and.w r3, r3, #1 800326c: 2b00 cmp r3, #0 800326e: d105 bne.n 800327c 8003270: f997 3017 ldrsb.w r3, [r7, #23] 8003274: 2b00 cmp r3, #0 8003276: d0db beq.n 8003230 8003278: e000 b.n 800327c break; 800327a: bf00 nop if (otp_err != BMM350_OTP_STATUS_NO_ERROR) 800327c: 7dbb ldrb r3, [r7, #22] 800327e: 2b00 cmp r3, #0 8003280: d023 beq.n 80032ca { switch (otp_err) 8003282: 7dbb ldrb r3, [r7, #22] 8003284: 2ba0 cmp r3, #160 @ 0xa0 8003286: d01a beq.n 80032be 8003288: 2ba0 cmp r3, #160 @ 0xa0 800328a: dc1b bgt.n 80032c4 800328c: 2b80 cmp r3, #128 @ 0x80 800328e: d013 beq.n 80032b8 8003290: 2b80 cmp r3, #128 @ 0x80 8003292: dc17 bgt.n 80032c4 8003294: 2b60 cmp r3, #96 @ 0x60 8003296: d00c beq.n 80032b2 8003298: 2b60 cmp r3, #96 @ 0x60 800329a: dc13 bgt.n 80032c4 800329c: 2b20 cmp r3, #32 800329e: d002 beq.n 80032a6 80032a0: 2b40 cmp r3, #64 @ 0x40 80032a2: d003 beq.n 80032ac 80032a4: e00e b.n 80032c4 { case BMM350_OTP_STATUS_BOOT_ERR: rslt = BMM350_E_OTP_BOOT; 80032a6: 23f7 movs r3, #247 @ 0xf7 80032a8: 75fb strb r3, [r7, #23] break; 80032aa: e00e b.n 80032ca case BMM350_OTP_STATUS_PAGE_RD_ERR: rslt = BMM350_E_OTP_PAGE_RD; 80032ac: 23f6 movs r3, #246 @ 0xf6 80032ae: 75fb strb r3, [r7, #23] break; 80032b0: e00b b.n 80032ca case BMM350_OTP_STATUS_PAGE_PRG_ERR: rslt = BMM350_E_OTP_PAGE_PRG; 80032b2: 23f5 movs r3, #245 @ 0xf5 80032b4: 75fb strb r3, [r7, #23] break; 80032b6: e008 b.n 80032ca case BMM350_OTP_STATUS_SIGN_ERR: rslt = BMM350_E_OTP_SIGN; 80032b8: 23f4 movs r3, #244 @ 0xf4 80032ba: 75fb strb r3, [r7, #23] break; 80032bc: e005 b.n 80032ca case BMM350_OTP_STATUS_INV_CMD_ERR: rslt = BMM350_E_OTP_INV_CMD; 80032be: 23f3 movs r3, #243 @ 0xf3 80032c0: 75fb strb r3, [r7, #23] break; 80032c2: e002 b.n 80032ca default: rslt = BMM350_E_OTP_UNDEFINED; 80032c4: 23f2 movs r3, #242 @ 0xf2 80032c6: 75fb strb r3, [r7, #23] break; 80032c8: bf00 nop } } } if (rslt == BMM350_OK) 80032ca: f997 3017 ldrsb.w r3, [r7, #23] 80032ce: 2b00 cmp r3, #0 80032d0: d120 bne.n 8003314 { /* Get OTP MSB data */ rslt = bmm350_get_regs(BMM350_REG_OTP_DATA_MSB_REG, &msb, 1, dev); 80032d2: f107 0112 add.w r1, r7, #18 80032d6: 687b ldr r3, [r7, #4] 80032d8: 2201 movs r2, #1 80032da: 2052 movs r0, #82 @ 0x52 80032dc: f7ff fa2d bl 800273a 80032e0: 4603 mov r3, r0 80032e2: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 80032e4: f997 3017 ldrsb.w r3, [r7, #23] 80032e8: 2b00 cmp r3, #0 80032ea: d113 bne.n 8003314 { /* Get OTP LSB data */ rslt = bmm350_get_regs(BMM350_REG_OTP_DATA_LSB_REG, &lsb, 1, dev); 80032ec: f107 0113 add.w r1, r7, #19 80032f0: 687b ldr r3, [r7, #4] 80032f2: 2201 movs r2, #1 80032f4: 2053 movs r0, #83 @ 0x53 80032f6: f7ff fa20 bl 800273a 80032fa: 4603 mov r3, r0 80032fc: 75fb strb r3, [r7, #23] *lsb_msb = ((uint16_t)(msb << 8) | lsb) & 0xFFFF; 80032fe: 7cbb ldrb r3, [r7, #18] 8003300: 021b lsls r3, r3, #8 8003302: b29b uxth r3, r3 8003304: 7cfa ldrb r2, [r7, #19] 8003306: 4313 orrs r3, r2 8003308: b29a uxth r2, r3 800330a: 68bb ldr r3, [r7, #8] 800330c: 801a strh r2, [r3, #0] 800330e: e001 b.n 8003314 } } } else { rslt = BMM350_E_NULL_PTR; 8003310: 23ff movs r3, #255 @ 0xff 8003312: 75fb strb r3, [r7, #23] } return rslt; 8003314: f997 3017 ldrsb.w r3, [r7, #23] } 8003318: 4618 mov r0, r3 800331a: 3718 adds r7, #24 800331c: 46bd mov sp, r7 800331e: bd80 pop {r7, pc} 08003320 : /*! * @brief This internal API is used to update magnetometer offset and sensitivity data. */ static void update_mag_off_sens(struct bmm350_dev *dev) { 8003320: b580 push {r7, lr} 8003322: b088 sub sp, #32 8003324: af00 add r7, sp, #0 8003326: 6078 str r0, [r7, #4] uint16_t off_x_lsb_msb, off_y_lsb_msb, off_z_lsb_msb, t_off = 0; 8003328: 2300 movs r3, #0 800332a: 83fb strh r3, [r7, #30] uint8_t sens_x, sens_y, sens_z, t_sens = 0; 800332c: 2300 movs r3, #0 800332e: 777b strb r3, [r7, #29] uint8_t tco_x, tco_y, tco_z = 0; 8003330: 2300 movs r3, #0 8003332: 773b strb r3, [r7, #28] uint8_t tcs_x, tcs_y, tcs_z = 0; 8003334: 2300 movs r3, #0 8003336: 76fb strb r3, [r7, #27] uint8_t cross_x_y, cross_y_x, cross_z_x, cross_z_y = 0; 8003338: 2300 movs r3, #0 800333a: 76bb strb r3, [r7, #26] off_x_lsb_msb = dev->otp_data[BMM350_MAG_OFFSET_X] & 0x0FFF; 800333c: 687b ldr r3, [r7, #4] 800333e: f8b3 3080 ldrh.w r3, [r3, #128] @ 0x80 8003342: f3c3 030b ubfx r3, r3, #0, #12 8003346: 833b strh r3, [r7, #24] off_y_lsb_msb = ((dev->otp_data[BMM350_MAG_OFFSET_X] & 0xF000) >> 4) + 8003348: 687b ldr r3, [r7, #4] 800334a: f8b3 3080 ldrh.w r3, [r3, #128] @ 0x80 800334e: 111b asrs r3, r3, #4 8003350: b21b sxth r3, r3 8003352: f403 6370 and.w r3, r3, #3840 @ 0xf00 8003356: b21a sxth r2, r3 (dev->otp_data[BMM350_MAG_OFFSET_Y] & BMM350_LSB_MASK); 8003358: 687b ldr r3, [r7, #4] 800335a: f8b3 3082 ldrh.w r3, [r3, #130] @ 0x82 800335e: b21b sxth r3, r3 8003360: b2db uxtb r3, r3 8003362: b21b sxth r3, r3 off_y_lsb_msb = ((dev->otp_data[BMM350_MAG_OFFSET_X] & 0xF000) >> 4) + 8003364: 4313 orrs r3, r2 8003366: b21b sxth r3, r3 8003368: 82fb strh r3, [r7, #22] off_z_lsb_msb = (dev->otp_data[BMM350_MAG_OFFSET_Y] & 0x0F00) + 800336a: 687b ldr r3, [r7, #4] 800336c: f8b3 3082 ldrh.w r3, [r3, #130] @ 0x82 8003370: b21b sxth r3, r3 8003372: f403 6370 and.w r3, r3, #3840 @ 0xf00 8003376: b21a sxth r2, r3 (dev->otp_data[BMM350_MAG_OFFSET_Z] & BMM350_LSB_MASK); 8003378: 687b ldr r3, [r7, #4] 800337a: f8b3 3084 ldrh.w r3, [r3, #132] @ 0x84 800337e: b21b sxth r3, r3 8003380: b2db uxtb r3, r3 8003382: b21b sxth r3, r3 off_z_lsb_msb = (dev->otp_data[BMM350_MAG_OFFSET_Y] & 0x0F00) + 8003384: 4313 orrs r3, r2 8003386: b21b sxth r3, r3 8003388: 82bb strh r3, [r7, #20] t_off = dev->otp_data[BMM350_TEMP_OFF_SENS] & BMM350_LSB_MASK; 800338a: 687b ldr r3, [r7, #4] 800338c: f8b3 307e ldrh.w r3, [r3, #126] @ 0x7e 8003390: b2db uxtb r3, r3 8003392: 83fb strh r3, [r7, #30] dev->mag_comp.dut_offset_coef.offset_z = f16_from_int(fix_sign(off_z_lsb_msb, BMM350_SIGNED_12_BIT)); dev->mag_comp.dut_offset_coef.t_offs = fixed_mul_A48_16(f16_from_int(fix_sign(t_off, BMM350_SIGNED_8_BIT)), A48_16_0_2); #else dev->mag_comp.dut_offset_coef.offset_x = fix_sign(off_x_lsb_msb, BMM350_SIGNED_12_BIT); 8003394: 8b3b ldrh r3, [r7, #24] 8003396: 210c movs r1, #12 8003398: 4618 mov r0, r3 800339a: f7ff fec5 bl 8003128 800339e: ee07 0a90 vmov s15, r0 80033a2: eef8 7ae7 vcvt.f32.s32 s15, s15 80033a6: 687b ldr r3, [r7, #4] 80033a8: edc3 7a07 vstr s15, [r3, #28] dev->mag_comp.dut_offset_coef.offset_y = fix_sign(off_y_lsb_msb, BMM350_SIGNED_12_BIT); 80033ac: 8afb ldrh r3, [r7, #22] 80033ae: 210c movs r1, #12 80033b0: 4618 mov r0, r3 80033b2: f7ff feb9 bl 8003128 80033b6: ee07 0a90 vmov s15, r0 80033ba: eef8 7ae7 vcvt.f32.s32 s15, s15 80033be: 687b ldr r3, [r7, #4] 80033c0: edc3 7a08 vstr s15, [r3, #32] dev->mag_comp.dut_offset_coef.offset_z = fix_sign(off_z_lsb_msb, BMM350_SIGNED_12_BIT); 80033c4: 8abb ldrh r3, [r7, #20] 80033c6: 210c movs r1, #12 80033c8: 4618 mov r0, r3 80033ca: f7ff fead bl 8003128 80033ce: ee07 0a90 vmov s15, r0 80033d2: eef8 7ae7 vcvt.f32.s32 s15, s15 80033d6: 687b ldr r3, [r7, #4] 80033d8: edc3 7a09 vstr s15, [r3, #36] @ 0x24 dev->mag_comp.dut_offset_coef.t_offs = fix_sign(t_off, BMM350_SIGNED_8_BIT) / 5.0f; 80033dc: 8bfb ldrh r3, [r7, #30] 80033de: 2108 movs r1, #8 80033e0: 4618 mov r0, r3 80033e2: f7ff fea1 bl 8003128 80033e6: ee07 0a90 vmov s15, r0 80033ea: eeb8 7ae7 vcvt.f32.s32 s14, s15 80033ee: eef1 6a04 vmov.f32 s13, #20 @ 0x40a00000 5.0 80033f2: eec7 7a26 vdiv.f32 s15, s14, s13 80033f6: 687b ldr r3, [r7, #4] 80033f8: edc3 7a06 vstr s15, [r3, #24] #endif sens_x = (dev->otp_data[BMM350_MAG_SENS_X] & BMM350_MSB_MASK) >> 8; 80033fc: 687b ldr r3, [r7, #4] 80033fe: f8b3 3084 ldrh.w r3, [r3, #132] @ 0x84 8003402: 0a1b lsrs r3, r3, #8 8003404: b29b uxth r3, r3 8003406: 74fb strb r3, [r7, #19] sens_y = (dev->otp_data[BMM350_MAG_SENS_Y] & BMM350_LSB_MASK); 8003408: 687b ldr r3, [r7, #4] 800340a: f8b3 3086 ldrh.w r3, [r3, #134] @ 0x86 800340e: 74bb strb r3, [r7, #18] sens_z = (dev->otp_data[BMM350_MAG_SENS_Z] & BMM350_MSB_MASK) >> 8; 8003410: 687b ldr r3, [r7, #4] 8003412: f8b3 3086 ldrh.w r3, [r3, #134] @ 0x86 8003416: 0a1b lsrs r3, r3, #8 8003418: b29b uxth r3, r3 800341a: 747b strb r3, [r7, #17] t_sens = (dev->otp_data[BMM350_TEMP_OFF_SENS] & BMM350_MSB_MASK) >> 8; 800341c: 687b ldr r3, [r7, #4] 800341e: f8b3 307e ldrh.w r3, [r3, #126] @ 0x7e 8003422: 0a1b lsrs r3, r3, #8 8003424: b29b uxth r3, r3 8003426: 777b strb r3, [r7, #29] A48_16_0_00390625); dev->mag_comp.dut_sensit_coef.t_sens = fixed_mul_A48_16(f16_from_int(fix_sign(t_sens, BMM350_SIGNED_8_BIT)), A48_16_0_001953125); #else dev->mag_comp.dut_sensit_coef.sens_x = fix_sign(sens_x, BMM350_SIGNED_8_BIT) / 256.0f; 8003428: 7cfb ldrb r3, [r7, #19] 800342a: 2108 movs r1, #8 800342c: 4618 mov r0, r3 800342e: f7ff fe7b bl 8003128 8003432: ee07 0a90 vmov s15, r0 8003436: eeb8 7ae7 vcvt.f32.s32 s14, s15 800343a: eddf 6a91 vldr s13, [pc, #580] @ 8003680 800343e: eec7 7a26 vdiv.f32 s15, s14, s13 8003442: 687b ldr r3, [r7, #4] 8003444: edc3 7a0b vstr s15, [r3, #44] @ 0x2c dev->mag_comp.dut_sensit_coef.sens_y = fix_sign(sens_y, BMM350_SIGNED_8_BIT) / 256.0f; 8003448: 7cbb ldrb r3, [r7, #18] 800344a: 2108 movs r1, #8 800344c: 4618 mov r0, r3 800344e: f7ff fe6b bl 8003128 8003452: ee07 0a90 vmov s15, r0 8003456: eeb8 7ae7 vcvt.f32.s32 s14, s15 800345a: eddf 6a89 vldr s13, [pc, #548] @ 8003680 800345e: eec7 7a26 vdiv.f32 s15, s14, s13 8003462: 687b ldr r3, [r7, #4] 8003464: edc3 7a0c vstr s15, [r3, #48] @ 0x30 dev->mag_comp.dut_sensit_coef.sens_z = fix_sign(sens_z, BMM350_SIGNED_8_BIT) / 256.0f; 8003468: 7c7b ldrb r3, [r7, #17] 800346a: 2108 movs r1, #8 800346c: 4618 mov r0, r3 800346e: f7ff fe5b bl 8003128 8003472: ee07 0a90 vmov s15, r0 8003476: eeb8 7ae7 vcvt.f32.s32 s14, s15 800347a: eddf 6a81 vldr s13, [pc, #516] @ 8003680 800347e: eec7 7a26 vdiv.f32 s15, s14, s13 8003482: 687b ldr r3, [r7, #4] 8003484: edc3 7a0d vstr s15, [r3, #52] @ 0x34 dev->mag_comp.dut_sensit_coef.t_sens = fix_sign(t_sens, BMM350_SIGNED_8_BIT) / 512.0f; 8003488: 7f7b ldrb r3, [r7, #29] 800348a: 2108 movs r1, #8 800348c: 4618 mov r0, r3 800348e: f7ff fe4b bl 8003128 8003492: ee07 0a90 vmov s15, r0 8003496: eeb8 7ae7 vcvt.f32.s32 s14, s15 800349a: eddf 6a7a vldr s13, [pc, #488] @ 8003684 800349e: eec7 7a26 vdiv.f32 s15, s14, s13 80034a2: 687b ldr r3, [r7, #4] 80034a4: edc3 7a0a vstr s15, [r3, #40] @ 0x28 #endif tco_x = (dev->otp_data[BMM350_MAG_TCO_X] & BMM350_LSB_MASK); 80034a8: 687b ldr r3, [r7, #4] 80034aa: f8b3 3088 ldrh.w r3, [r3, #136] @ 0x88 80034ae: 743b strb r3, [r7, #16] tco_y = (dev->otp_data[BMM350_MAG_TCO_Y] & BMM350_LSB_MASK); 80034b0: 687b ldr r3, [r7, #4] 80034b2: f8b3 308a ldrh.w r3, [r3, #138] @ 0x8a 80034b6: 73fb strb r3, [r7, #15] tco_z = (dev->otp_data[BMM350_MAG_TCO_Z] & BMM350_LSB_MASK); 80034b8: 687b ldr r3, [r7, #4] 80034ba: f8b3 308c ldrh.w r3, [r3, #140] @ 0x8c 80034be: 773b strb r3, [r7, #28] dev->mag_comp.dut_tco.tco_x = fixed_mul_A48_16(f16_from_int(fix_sign(tco_x, BMM350_SIGNED_8_BIT)), A48_16_0_03125); dev->mag_comp.dut_tco.tco_y = fixed_mul_A48_16(f16_from_int(fix_sign(tco_y, BMM350_SIGNED_8_BIT)), A48_16_0_03125); dev->mag_comp.dut_tco.tco_z = fixed_mul_A48_16(f16_from_int(fix_sign(tco_z, BMM350_SIGNED_8_BIT)), A48_16_0_03125); #else dev->mag_comp.dut_tco.tco_x = fix_sign(tco_x, BMM350_SIGNED_8_BIT) / 32.0f; 80034c0: 7c3b ldrb r3, [r7, #16] 80034c2: 2108 movs r1, #8 80034c4: 4618 mov r0, r3 80034c6: f7ff fe2f bl 8003128 80034ca: ee07 0a90 vmov s15, r0 80034ce: eeb8 7ae7 vcvt.f32.s32 s14, s15 80034d2: eddf 6a6d vldr s13, [pc, #436] @ 8003688 80034d6: eec7 7a26 vdiv.f32 s15, s14, s13 80034da: 687b ldr r3, [r7, #4] 80034dc: edc3 7a0e vstr s15, [r3, #56] @ 0x38 dev->mag_comp.dut_tco.tco_y = fix_sign(tco_y, BMM350_SIGNED_8_BIT) / 32.0f; 80034e0: 7bfb ldrb r3, [r7, #15] 80034e2: 2108 movs r1, #8 80034e4: 4618 mov r0, r3 80034e6: f7ff fe1f bl 8003128 80034ea: ee07 0a90 vmov s15, r0 80034ee: eeb8 7ae7 vcvt.f32.s32 s14, s15 80034f2: eddf 6a65 vldr s13, [pc, #404] @ 8003688 80034f6: eec7 7a26 vdiv.f32 s15, s14, s13 80034fa: 687b ldr r3, [r7, #4] 80034fc: edc3 7a0f vstr s15, [r3, #60] @ 0x3c dev->mag_comp.dut_tco.tco_z = fix_sign(tco_z, BMM350_SIGNED_8_BIT) / 32.0f; 8003500: 7f3b ldrb r3, [r7, #28] 8003502: 2108 movs r1, #8 8003504: 4618 mov r0, r3 8003506: f7ff fe0f bl 8003128 800350a: ee07 0a90 vmov s15, r0 800350e: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003512: eddf 6a5d vldr s13, [pc, #372] @ 8003688 8003516: eec7 7a26 vdiv.f32 s15, s14, s13 800351a: 687b ldr r3, [r7, #4] 800351c: edc3 7a10 vstr s15, [r3, #64] @ 0x40 #endif tcs_x = (dev->otp_data[BMM350_MAG_TCS_X] & BMM350_MSB_MASK) >> 8; 8003520: 687b ldr r3, [r7, #4] 8003522: f8b3 3088 ldrh.w r3, [r3, #136] @ 0x88 8003526: 0a1b lsrs r3, r3, #8 8003528: b29b uxth r3, r3 800352a: 73bb strb r3, [r7, #14] tcs_y = (dev->otp_data[BMM350_MAG_TCS_Y] & BMM350_MSB_MASK) >> 8; 800352c: 687b ldr r3, [r7, #4] 800352e: f8b3 308a ldrh.w r3, [r3, #138] @ 0x8a 8003532: 0a1b lsrs r3, r3, #8 8003534: b29b uxth r3, r3 8003536: 737b strb r3, [r7, #13] tcs_z = (dev->otp_data[BMM350_MAG_TCS_Z] & BMM350_MSB_MASK) >> 8; 8003538: 687b ldr r3, [r7, #4] 800353a: f8b3 308c ldrh.w r3, [r3, #140] @ 0x8c 800353e: 0a1b lsrs r3, r3, #8 8003540: b29b uxth r3, r3 8003542: 76fb strb r3, [r7, #27] A48_16_0_00006103515625); dev->mag_comp.dut_tcs.tcs_z = fixed_mul_A48_16(f16_from_int(fix_sign(tcs_z, BMM350_SIGNED_8_BIT)), A48_16_0_00006103515625); #else dev->mag_comp.dut_tcs.tcs_x = fix_sign(tcs_x, BMM350_SIGNED_8_BIT) / 16384.0f; 8003544: 7bbb ldrb r3, [r7, #14] 8003546: 2108 movs r1, #8 8003548: 4618 mov r0, r3 800354a: f7ff fded bl 8003128 800354e: ee07 0a90 vmov s15, r0 8003552: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003556: eddf 6a4d vldr s13, [pc, #308] @ 800368c 800355a: eec7 7a26 vdiv.f32 s15, s14, s13 800355e: 687b ldr r3, [r7, #4] 8003560: edc3 7a11 vstr s15, [r3, #68] @ 0x44 dev->mag_comp.dut_tcs.tcs_y = fix_sign(tcs_y, BMM350_SIGNED_8_BIT) / 16384.0f; 8003564: 7b7b ldrb r3, [r7, #13] 8003566: 2108 movs r1, #8 8003568: 4618 mov r0, r3 800356a: f7ff fddd bl 8003128 800356e: ee07 0a90 vmov s15, r0 8003572: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003576: eddf 6a45 vldr s13, [pc, #276] @ 800368c 800357a: eec7 7a26 vdiv.f32 s15, s14, s13 800357e: 687b ldr r3, [r7, #4] 8003580: edc3 7a12 vstr s15, [r3, #72] @ 0x48 dev->mag_comp.dut_tcs.tcs_z = fix_sign(tcs_z, BMM350_SIGNED_8_BIT) / 16384.0f; 8003584: 7efb ldrb r3, [r7, #27] 8003586: 2108 movs r1, #8 8003588: 4618 mov r0, r3 800358a: f7ff fdcd bl 8003128 800358e: ee07 0a90 vmov s15, r0 8003592: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003596: eddf 6a3d vldr s13, [pc, #244] @ 800368c 800359a: eec7 7a26 vdiv.f32 s15, s14, s13 800359e: 687b ldr r3, [r7, #4] 80035a0: edc3 7a13 vstr s15, [r3, #76] @ 0x4c dev->mag_comp.dut_t0 = fixed_add(fixed_mul_A48_16(f16_from_int(fix_sign(dev->otp_data[BMM350_MAG_DUT_T_0], BMM350_SIGNED_16_BIT)), A48_16_0_001953125), f16_from_int(23)); #else dev->mag_comp.dut_t0 = (fix_sign(dev->otp_data[BMM350_MAG_DUT_T_0], BMM350_SIGNED_16_BIT) / 512.0f) + 23.0f; 80035a4: 687b ldr r3, [r7, #4] 80035a6: f8b3 3094 ldrh.w r3, [r3, #148] @ 0x94 80035aa: 2110 movs r1, #16 80035ac: 4618 mov r0, r3 80035ae: f7ff fdbb bl 8003128 80035b2: ee07 0a90 vmov s15, r0 80035b6: eeb8 7ae7 vcvt.f32.s32 s14, s15 80035ba: eddf 6a32 vldr s13, [pc, #200] @ 8003684 80035be: eec7 7a26 vdiv.f32 s15, s14, s13 80035c2: eeb3 7a07 vmov.f32 s14, #55 @ 0x41b80000 23.0 80035c6: ee77 7a87 vadd.f32 s15, s15, s14 80035ca: 687b ldr r3, [r7, #4] 80035cc: edc3 7a14 vstr s15, [r3, #80] @ 0x50 #endif cross_x_y = (dev->otp_data[BMM350_CROSS_X_Y] & BMM350_LSB_MASK); 80035d0: 687b ldr r3, [r7, #4] 80035d2: f8b3 308e ldrh.w r3, [r3, #142] @ 0x8e 80035d6: 733b strb r3, [r7, #12] cross_y_x = (dev->otp_data[BMM350_CROSS_Y_X] & BMM350_MSB_MASK) >> 8; 80035d8: 687b ldr r3, [r7, #4] 80035da: f8b3 308e ldrh.w r3, [r3, #142] @ 0x8e 80035de: 0a1b lsrs r3, r3, #8 80035e0: b29b uxth r3, r3 80035e2: 72fb strb r3, [r7, #11] cross_z_x = (dev->otp_data[BMM350_CROSS_Z_X] & BMM350_LSB_MASK); 80035e4: 687b ldr r3, [r7, #4] 80035e6: f8b3 3090 ldrh.w r3, [r3, #144] @ 0x90 80035ea: 72bb strb r3, [r7, #10] cross_z_y = (dev->otp_data[BMM350_CROSS_Z_Y] & BMM350_MSB_MASK) >> 8; 80035ec: 687b ldr r3, [r7, #4] 80035ee: f8b3 3090 ldrh.w r3, [r3, #144] @ 0x90 80035f2: 0a1b lsrs r3, r3, #8 80035f4: b29b uxth r3, r3 80035f6: 76bb strb r3, [r7, #26] A48_16_0_00125); dev->mag_comp.cross_axis.cross_z_y = fixed_mul_A48_16(f16_from_int(fix_sign(cross_z_y, BMM350_SIGNED_8_BIT)), A48_16_0_00125); #else dev->mag_comp.cross_axis.cross_x_y = fix_sign(cross_x_y, BMM350_SIGNED_8_BIT) / 800.0f; 80035f8: 7b3b ldrb r3, [r7, #12] 80035fa: 2108 movs r1, #8 80035fc: 4618 mov r0, r3 80035fe: f7ff fd93 bl 8003128 8003602: ee07 0a90 vmov s15, r0 8003606: eeb8 7ae7 vcvt.f32.s32 s14, s15 800360a: eddf 6a21 vldr s13, [pc, #132] @ 8003690 800360e: eec7 7a26 vdiv.f32 s15, s14, s13 8003612: 687b ldr r3, [r7, #4] 8003614: edc3 7a15 vstr s15, [r3, #84] @ 0x54 dev->mag_comp.cross_axis.cross_y_x = fix_sign(cross_y_x, BMM350_SIGNED_8_BIT) / 800.0f; 8003618: 7afb ldrb r3, [r7, #11] 800361a: 2108 movs r1, #8 800361c: 4618 mov r0, r3 800361e: f7ff fd83 bl 8003128 8003622: ee07 0a90 vmov s15, r0 8003626: eeb8 7ae7 vcvt.f32.s32 s14, s15 800362a: eddf 6a19 vldr s13, [pc, #100] @ 8003690 800362e: eec7 7a26 vdiv.f32 s15, s14, s13 8003632: 687b ldr r3, [r7, #4] 8003634: edc3 7a16 vstr s15, [r3, #88] @ 0x58 dev->mag_comp.cross_axis.cross_z_x = fix_sign(cross_z_x, BMM350_SIGNED_8_BIT) / 800.0f; 8003638: 7abb ldrb r3, [r7, #10] 800363a: 2108 movs r1, #8 800363c: 4618 mov r0, r3 800363e: f7ff fd73 bl 8003128 8003642: ee07 0a90 vmov s15, r0 8003646: eeb8 7ae7 vcvt.f32.s32 s14, s15 800364a: eddf 6a11 vldr s13, [pc, #68] @ 8003690 800364e: eec7 7a26 vdiv.f32 s15, s14, s13 8003652: 687b ldr r3, [r7, #4] 8003654: edc3 7a17 vstr s15, [r3, #92] @ 0x5c dev->mag_comp.cross_axis.cross_z_y = fix_sign(cross_z_y, BMM350_SIGNED_8_BIT) / 800.0f; 8003658: 7ebb ldrb r3, [r7, #26] 800365a: 2108 movs r1, #8 800365c: 4618 mov r0, r3 800365e: f7ff fd63 bl 8003128 8003662: ee07 0a90 vmov s15, r0 8003666: eeb8 7ae7 vcvt.f32.s32 s14, s15 800366a: eddf 6a09 vldr s13, [pc, #36] @ 8003690 800366e: eec7 7a26 vdiv.f32 s15, s14, s13 8003672: 687b ldr r3, [r7, #4] 8003674: edc3 7a18 vstr s15, [r3, #96] @ 0x60 #endif } 8003678: bf00 nop 800367a: 3720 adds r7, #32 800367c: 46bd mov sp, r7 800367e: bd80 pop {r7, pc} 8003680: 43800000 .word 0x43800000 8003684: 44000000 .word 0x44000000 8003688: 42000000 .word 0x42000000 800368c: 46800000 .word 0x46800000 8003690: 44480000 .word 0x44480000 8003694: 00000000 .word 0x00000000 08003698 : return rslt; } #else static int8_t read_out_raw_data(float *out_data, struct bmm350_dev *dev) { 8003698: b590 push {r4, r7, lr} 800369a: b08d sub sp, #52 @ 0x34 800369c: af00 add r7, sp, #0 800369e: 6078 str r0, [r7, #4] 80036a0: 6039 str r1, [r7, #0] int8_t rslt; /* Float variable to convert mag lsb to uT and temp lsb to degC */ float lsb_to_ut_degc[4]; struct bmm350_raw_mag_data raw_data = { 0 }; 80036a2: f107 030c add.w r3, r7, #12 80036a6: 2200 movs r2, #0 80036a8: 601a str r2, [r3, #0] 80036aa: 605a str r2, [r3, #4] 80036ac: 609a str r2, [r3, #8] 80036ae: 60da str r2, [r3, #12] if (out_data != NULL) 80036b0: 687b ldr r3, [r7, #4] 80036b2: 2b00 cmp r3, #0 80036b4: d05b beq.n 800376e { rslt = bmm350_read_uncomp_mag_temp_data(&raw_data, dev); 80036b6: f107 030c add.w r3, r7, #12 80036ba: 6839 ldr r1, [r7, #0] 80036bc: 4618 mov r0, r3 80036be: f7ff fa07 bl 8002ad0 80036c2: 4603 mov r3, r0 80036c4: f887 302f strb.w r3, [r7, #47] @ 0x2f if (rslt == BMM350_OK) 80036c8: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 80036cc: 2b00 cmp r3, #0 80036ce: d151 bne.n 8003774 { /* Convert mag lsb to uT and temp lsb to degC */ update_default_coefiecents(lsb_to_ut_degc); 80036d0: f107 031c add.w r3, r7, #28 80036d4: 4618 mov r0, r3 80036d6: f000 f857 bl 8003788 out_data[0] = (float)raw_data.raw_xdata * lsb_to_ut_degc[0]; 80036da: 68fb ldr r3, [r7, #12] 80036dc: ee07 3a90 vmov s15, r3 80036e0: eeb8 7ae7 vcvt.f32.s32 s14, s15 80036e4: edd7 7a07 vldr s15, [r7, #28] 80036e8: ee67 7a27 vmul.f32 s15, s14, s15 80036ec: 687b ldr r3, [r7, #4] 80036ee: edc3 7a00 vstr s15, [r3] out_data[1] = (float)raw_data.raw_ydata * lsb_to_ut_degc[1]; 80036f2: 693b ldr r3, [r7, #16] 80036f4: ee07 3a90 vmov s15, r3 80036f8: eeb8 7ae7 vcvt.f32.s32 s14, s15 80036fc: edd7 7a08 vldr s15, [r7, #32] 8003700: 687b ldr r3, [r7, #4] 8003702: 3304 adds r3, #4 8003704: ee67 7a27 vmul.f32 s15, s14, s15 8003708: edc3 7a00 vstr s15, [r3] out_data[2] = (float)raw_data.raw_zdata * lsb_to_ut_degc[2]; 800370c: 697b ldr r3, [r7, #20] 800370e: ee07 3a90 vmov s15, r3 8003712: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003716: edd7 7a09 vldr s15, [r7, #36] @ 0x24 800371a: 687b ldr r3, [r7, #4] 800371c: 3308 adds r3, #8 800371e: ee67 7a27 vmul.f32 s15, s14, s15 8003722: edc3 7a00 vstr s15, [r3] out_data[3] = (float)raw_data.raw_data_t * lsb_to_ut_degc[3]; 8003726: 69bb ldr r3, [r7, #24] 8003728: ee07 3a90 vmov s15, r3 800372c: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003730: edd7 7a0a vldr s15, [r7, #40] @ 0x28 8003734: 687b ldr r3, [r7, #4] 8003736: 330c adds r3, #12 8003738: ee67 7a27 vmul.f32 s15, s14, s15 800373c: edc3 7a00 vstr s15, [r3] out_data[3] = (float)(out_data[3] - (1 * 25.49)); 8003740: 687b ldr r3, [r7, #4] 8003742: 330c adds r3, #12 8003744: 681b ldr r3, [r3, #0] 8003746: 4618 mov r0, r3 8003748: f7fc fed6 bl 80004f8 <__aeabi_f2d> 800374c: a30c add r3, pc, #48 @ (adr r3, 8003780 ) 800374e: e9d3 2300 ldrd r2, r3, [r3] 8003752: f7fc fd71 bl 8000238 <__aeabi_dsub> 8003756: 4602 mov r2, r0 8003758: 460b mov r3, r1 800375a: 4610 mov r0, r2 800375c: 4619 mov r1, r3 800375e: 687b ldr r3, [r7, #4] 8003760: f103 040c add.w r4, r3, #12 8003764: f7fd fa18 bl 8000b98 <__aeabi_d2f> 8003768: 4603 mov r3, r0 800376a: 6023 str r3, [r4, #0] 800376c: e002 b.n 8003774 } } else { rslt = BMM350_E_NULL_PTR; 800376e: 23ff movs r3, #255 @ 0xff 8003770: f887 302f strb.w r3, [r7, #47] @ 0x2f } return rslt; 8003774: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f } 8003778: 4618 mov r0, r3 800377a: 3734 adds r7, #52 @ 0x34 800377c: 46bd mov sp, r7 800377e: bd90 pop {r4, r7, pc} 8003780: a3d70a3d .word 0xa3d70a3d 8003784: 40397d70 .word 0x40397d70 08003788 : /*! * @brief This internal API is used to convert lsb to uT and degC. */ static void update_default_coefiecents(float *lsb_to_ut_degc) { 8003788: b480 push {r7} 800378a: b08b sub sp, #44 @ 0x2c 800378c: af00 add r7, sp, #0 800378e: 6078 str r0, [r7, #4] float bxy_sens, bz_sens, temp_sens, ina_xy_gain_trgt, ina_z_gain_trgt, adc_gain, lut_gain; float power; bxy_sens = 14.55f; 8003790: 4b36 ldr r3, [pc, #216] @ (800386c ) 8003792: 627b str r3, [r7, #36] @ 0x24 bz_sens = 9.0f; 8003794: 4b36 ldr r3, [pc, #216] @ (8003870 ) 8003796: 623b str r3, [r7, #32] temp_sens = 0.00204f; 8003798: 4b36 ldr r3, [pc, #216] @ (8003874 ) 800379a: 61fb str r3, [r7, #28] ina_xy_gain_trgt = 19.46f; 800379c: 4b36 ldr r3, [pc, #216] @ (8003878 ) 800379e: 61bb str r3, [r7, #24] ina_z_gain_trgt = 31.0; 80037a0: 4b36 ldr r3, [pc, #216] @ (800387c ) 80037a2: 617b str r3, [r7, #20] adc_gain = 1 / 1.5f; 80037a4: 4b36 ldr r3, [pc, #216] @ (8003880 ) 80037a6: 613b str r3, [r7, #16] lut_gain = 0.714607238769531f; 80037a8: 4b36 ldr r3, [pc, #216] @ (8003884 ) 80037aa: 60fb str r3, [r7, #12] power = (float)(1000000.0 / 1048576.0); 80037ac: 4b36 ldr r3, [pc, #216] @ (8003888 ) 80037ae: 60bb str r3, [r7, #8] lsb_to_ut_degc[0] = (power / (bxy_sens * ina_xy_gain_trgt * adc_gain * lut_gain)); 80037b0: ed97 7a09 vldr s14, [r7, #36] @ 0x24 80037b4: edd7 7a06 vldr s15, [r7, #24] 80037b8: ee27 7a27 vmul.f32 s14, s14, s15 80037bc: edd7 7a04 vldr s15, [r7, #16] 80037c0: ee27 7a27 vmul.f32 s14, s14, s15 80037c4: edd7 7a03 vldr s15, [r7, #12] 80037c8: ee27 7a27 vmul.f32 s14, s14, s15 80037cc: edd7 6a02 vldr s13, [r7, #8] 80037d0: eec6 7a87 vdiv.f32 s15, s13, s14 80037d4: 687b ldr r3, [r7, #4] 80037d6: edc3 7a00 vstr s15, [r3] lsb_to_ut_degc[1] = (power / (bxy_sens * ina_xy_gain_trgt * adc_gain * lut_gain)); 80037da: ed97 7a09 vldr s14, [r7, #36] @ 0x24 80037de: edd7 7a06 vldr s15, [r7, #24] 80037e2: ee27 7a27 vmul.f32 s14, s14, s15 80037e6: edd7 7a04 vldr s15, [r7, #16] 80037ea: ee27 7a27 vmul.f32 s14, s14, s15 80037ee: edd7 7a03 vldr s15, [r7, #12] 80037f2: ee27 7a27 vmul.f32 s14, s14, s15 80037f6: 687b ldr r3, [r7, #4] 80037f8: 3304 adds r3, #4 80037fa: edd7 6a02 vldr s13, [r7, #8] 80037fe: eec6 7a87 vdiv.f32 s15, s13, s14 8003802: edc3 7a00 vstr s15, [r3] lsb_to_ut_degc[2] = (power / (bz_sens * ina_z_gain_trgt * adc_gain * lut_gain)); 8003806: ed97 7a08 vldr s14, [r7, #32] 800380a: edd7 7a05 vldr s15, [r7, #20] 800380e: ee27 7a27 vmul.f32 s14, s14, s15 8003812: edd7 7a04 vldr s15, [r7, #16] 8003816: ee27 7a27 vmul.f32 s14, s14, s15 800381a: edd7 7a03 vldr s15, [r7, #12] 800381e: ee27 7a27 vmul.f32 s14, s14, s15 8003822: 687b ldr r3, [r7, #4] 8003824: 3308 adds r3, #8 8003826: edd7 6a02 vldr s13, [r7, #8] 800382a: eec6 7a87 vdiv.f32 s15, s13, s14 800382e: edc3 7a00 vstr s15, [r3] lsb_to_ut_degc[3] = 1 / (temp_sens * adc_gain * lut_gain * 1048576); 8003832: ed97 7a07 vldr s14, [r7, #28] 8003836: edd7 7a04 vldr s15, [r7, #16] 800383a: ee27 7a27 vmul.f32 s14, s14, s15 800383e: edd7 7a03 vldr s15, [r7, #12] 8003842: ee67 7a27 vmul.f32 s15, s14, s15 8003846: ed9f 7a11 vldr s14, [pc, #68] @ 800388c 800384a: ee27 7a87 vmul.f32 s14, s15, s14 800384e: 687b ldr r3, [r7, #4] 8003850: 330c adds r3, #12 8003852: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8003856: eec6 7a87 vdiv.f32 s15, s13, s14 800385a: edc3 7a00 vstr s15, [r3] } 800385e: bf00 nop 8003860: 372c adds r7, #44 @ 0x2c 8003862: 46bd mov sp, r7 8003864: f85d 7b04 ldr.w r7, [sp], #4 8003868: 4770 bx lr 800386a: bf00 nop 800386c: 4168cccd .word 0x4168cccd 8003870: 41100000 .word 0x41100000 8003874: 3b05b185 .word 0x3b05b185 8003878: 419bae14 .word 0x419bae14 800387c: 41f80000 .word 0x41f80000 8003880: 3f2aaaab .word 0x3f2aaaab 8003884: 3f36f080 .word 0x3f36f080 8003888: 3f742400 .word 0x3f742400 800388c: 49800000 .word 0x49800000 08003890 : /*! * @brief This internal API is used to read OTP data after boot in user mode. */ static int8_t otp_dump_after_boot(struct bmm350_dev *dev) { 8003890: b580 push {r7, lr} 8003892: b084 sub sp, #16 8003894: af00 add r7, sp, #0 8003896: 6078 str r0, [r7, #4] /* Variable to store the function result */ int8_t rslt; uint16_t otp_word = 0; 8003898: 2300 movs r3, #0 800389a: 81bb strh r3, [r7, #12] uint8_t indx; for (indx = 0; indx < BMM350_OTP_DATA_LENGTH; indx++) 800389c: 2300 movs r3, #0 800389e: 73bb strb r3, [r7, #14] 80038a0: e013 b.n 80038ca { rslt = read_otp_word(indx, &otp_word, dev); 80038a2: f107 010c add.w r1, r7, #12 80038a6: 7bbb ldrb r3, [r7, #14] 80038a8: 687a ldr r2, [r7, #4] 80038aa: 4618 mov r0, r3 80038ac: f7ff fc96 bl 80031dc 80038b0: 4603 mov r3, r0 80038b2: 73fb strb r3, [r7, #15] dev->otp_data[indx] = otp_word; 80038b4: 7bbb ldrb r3, [r7, #14] 80038b6: 89b9 ldrh r1, [r7, #12] 80038b8: 687a ldr r2, [r7, #4] 80038ba: 3330 adds r3, #48 @ 0x30 80038bc: 005b lsls r3, r3, #1 80038be: 4413 add r3, r2 80038c0: 460a mov r2, r1 80038c2: 809a strh r2, [r3, #4] for (indx = 0; indx < BMM350_OTP_DATA_LENGTH; indx++) 80038c4: 7bbb ldrb r3, [r7, #14] 80038c6: 3301 adds r3, #1 80038c8: 73bb strb r3, [r7, #14] 80038ca: 7bbb ldrb r3, [r7, #14] 80038cc: 2b1f cmp r3, #31 80038ce: d9e8 bls.n 80038a2 } dev->var_id = (dev->otp_data[30] & 0x7f00) >> 9; 80038d0: 687b ldr r3, [r7, #4] 80038d2: f8b3 30a0 ldrh.w r3, [r3, #160] @ 0xa0 80038d6: 125b asrs r3, r3, #9 80038d8: b2db uxtb r3, r3 80038da: f003 033f and.w r3, r3, #63 @ 0x3f 80038de: b2da uxtb r2, r3 80038e0: 687b ldr r3, [r7, #4] 80038e2: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 /* Set the default auto bit reset configuration */ dev->enable_auto_br = ((dev->var_id > BMM350_CURRENT_SHUTTLE_VARIANT_ID) ? BMM350_DISABLE : BMM350_ENABLE); 80038e6: 687b ldr r3, [r7, #4] 80038e8: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 80038ec: 2b11 cmp r3, #17 80038ee: bf94 ite ls 80038f0: 2301 movls r3, #1 80038f2: 2300 movhi r3, #0 80038f4: b2db uxtb r3, r3 80038f6: 461a mov r2, r3 80038f8: 687b ldr r3, [r7, #4] 80038fa: f883 20ad strb.w r2, [r3, #173] @ 0xad /* Update magnetometer offset and sensitivity data. */ update_mag_off_sens(dev); 80038fe: 6878 ldr r0, [r7, #4] 8003900: f7ff fd0e bl 8003320 return rslt; 8003904: f997 300f ldrsb.w r3, [r7, #15] } 8003908: 4618 mov r0, r3 800390a: 3710 adds r7, #16 800390c: 46bd mov sp, r7 800390e: bd80 pop {r7, pc} 08003910 : /*! * @brief This internal API is used to switch from suspend mode to normal mode or forced mode. */ static int8_t set_powermode(enum bmm350_power_modes powermode, struct bmm350_dev *dev) { 8003910: b590 push {r4, r7, lr} 8003912: b08f sub sp, #60 @ 0x3c 8003914: af00 add r7, sp, #0 8003916: 4603 mov r3, r0 8003918: 6039 str r1, [r7, #0] 800391a: 71fb strb r3, [r7, #7] /* Variable to store the function result */ int8_t rslt; uint8_t reg_data = powermode; 800391c: 79fb ldrb r3, [r7, #7] 800391e: f887 302f strb.w r3, [r7, #47] @ 0x2f uint8_t get_avg; /* Array to store suspend to forced mode delay */ uint32_t sus_to_forced_mode[4] = 8003922: 4b36 ldr r3, [pc, #216] @ (80039fc ) 8003924: f107 041c add.w r4, r7, #28 8003928: cb0f ldmia r3, {r0, r1, r2, r3} 800392a: e884 000f stmia.w r4, {r0, r1, r2, r3} { BMM350_SUS_TO_FORCEDMODE_NO_AVG_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_2_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_4_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_8_DELAY }; /* Array to store suspend to forced mode fast delay */ uint32_t sus_to_forced_mode_fast[4] = 800392e: 4b34 ldr r3, [pc, #208] @ (8003a00 ) 8003930: f107 040c add.w r4, r7, #12 8003934: cb0f ldmia r3, {r0, r1, r2, r3} 8003936: e884 000f stmia.w r4, {r0, r1, r2, r3} { BMM350_SUS_TO_FORCEDMODE_FAST_NO_AVG_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_2_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_4_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_8_DELAY }; uint8_t avg = 0; 800393a: 2300 movs r3, #0 800393c: f887 3036 strb.w r3, [r7, #54] @ 0x36 uint32_t delay_us = 0; 8003940: 2300 movs r3, #0 8003942: 633b str r3, [r7, #48] @ 0x30 rslt = null_ptr_check(dev); 8003944: 6838 ldr r0, [r7, #0] 8003946: f7ff fbce bl 80030e6 800394a: 4603 mov r3, r0 800394c: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (rslt == BMM350_OK) 8003950: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 8003954: 2b00 cmp r3, #0 8003956: d123 bne.n 80039a0 { /* Set PMU command configuration to desired power mode */ rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev); 8003958: f107 012f add.w r1, r7, #47 @ 0x2f 800395c: 683b ldr r3, [r7, #0] 800395e: 2201 movs r2, #1 8003960: 2006 movs r0, #6 8003962: f7fe feb6 bl 80026d2 8003966: 4603 mov r3, r0 8003968: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (rslt == BMM350_OK) 800396c: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 8003970: 2b00 cmp r3, #0 8003972: d115 bne.n 80039a0 { /* Get average configuration */ rslt = bmm350_get_regs(BMM350_REG_PMU_CMD_AGGR_SET, &get_avg, 1, dev); 8003974: f107 012e add.w r1, r7, #46 @ 0x2e 8003978: 683b ldr r3, [r7, #0] 800397a: 2201 movs r2, #1 800397c: 2004 movs r0, #4 800397e: f7fe fedc bl 800273a 8003982: 4603 mov r3, r0 8003984: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (rslt == BMM350_OK) 8003988: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 800398c: 2b00 cmp r3, #0 800398e: d107 bne.n 80039a0 { /* Mask the average value */ avg = ((get_avg & BMM350_AVG_MSK) >> BMM350_AVG_POS); 8003990: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8003994: 111b asrs r3, r3, #4 8003996: b2db uxtb r3, r3 8003998: f003 0303 and.w r3, r3, #3 800399c: f887 3036 strb.w r3, [r7, #54] @ 0x36 } } } if (rslt == BMM350_OK) 80039a0: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 80039a4: 2b00 cmp r3, #0 80039a6: d122 bne.n 80039ee { /* Check if desired power mode is normal mode */ if (powermode == BMM350_NORMAL_MODE) 80039a8: 79fb ldrb r3, [r7, #7] 80039aa: 2b01 cmp r3, #1 80039ac: d102 bne.n 80039b4 { delay_us = BMM350_SUSPEND_TO_NORMAL_DELAY; 80039ae: f249 4370 movw r3, #38000 @ 0x9470 80039b2: 633b str r3, [r7, #48] @ 0x30 } /* Check if desired power mode is forced mode */ if (powermode == BMM350_FORCED_MODE) 80039b4: 79fb ldrb r3, [r7, #7] 80039b6: 2b03 cmp r3, #3 80039b8: d107 bne.n 80039ca { /* Store delay based on averaging mode */ delay_us = sus_to_forced_mode[avg]; 80039ba: f897 3036 ldrb.w r3, [r7, #54] @ 0x36 80039be: 009b lsls r3, r3, #2 80039c0: 3338 adds r3, #56 @ 0x38 80039c2: 443b add r3, r7 80039c4: f853 3c1c ldr.w r3, [r3, #-28] 80039c8: 633b str r3, [r7, #48] @ 0x30 } /* Check if desired power mode is forced mode fast */ if (powermode == BMM350_FORCED_MODE_FAST) 80039ca: 79fb ldrb r3, [r7, #7] 80039cc: 2b04 cmp r3, #4 80039ce: d107 bne.n 80039e0 { /* Store delay based on averaging mode */ delay_us = sus_to_forced_mode_fast[avg]; 80039d0: f897 3036 ldrb.w r3, [r7, #54] @ 0x36 80039d4: 009b lsls r3, r3, #2 80039d6: 3338 adds r3, #56 @ 0x38 80039d8: 443b add r3, r7 80039da: f853 3c2c ldr.w r3, [r3, #-44] 80039de: 633b str r3, [r7, #48] @ 0x30 } /* Perform delay based on power mode */ rslt = bmm350_delay_us(delay_us, dev); 80039e0: 6839 ldr r1, [r7, #0] 80039e2: 6b38 ldr r0, [r7, #48] @ 0x30 80039e4: f7fe fefe bl 80027e4 80039e8: 4603 mov r3, r0 80039ea: f887 3037 strb.w r3, [r7, #55] @ 0x37 } return rslt; 80039ee: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 } 80039f2: 4618 mov r0, r3 80039f4: 373c adds r7, #60 @ 0x3c 80039f6: 46bd mov sp, r7 80039f8: bd90 pop {r4, r7, pc} 80039fa: bf00 nop 80039fc: 0801d45c .word 0x0801d45c 8003a00: 0801d46c .word 0x0801d46c 08003a04 : { 8003a04: b480 push {r7} 8003a06: b083 sub sp, #12 8003a08: af00 add r7, sp, #0 8003a0a: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR1, ExtiLine); 8003a0c: 4b06 ldr r3, [pc, #24] @ (8003a28 ) 8003a0e: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8003a12: 4905 ldr r1, [pc, #20] @ (8003a28 ) 8003a14: 687b ldr r3, [r7, #4] 8003a16: 4313 orrs r3, r2 8003a18: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } 8003a1c: bf00 nop 8003a1e: 370c adds r7, #12 8003a20: 46bd mov sp, r7 8003a22: f85d 7b04 ldr.w r7, [sp], #4 8003a26: 4770 bx lr 8003a28: 58000800 .word 0x58000800 08003a2c : * @arg @ref LL_EXTI_LINE_31 (*) * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) { 8003a2c: b480 push {r7} 8003a2e: b083 sub sp, #12 8003a30: af00 add r7, sp, #0 8003a32: 6078 str r0, [r7, #4] SET_BIT(EXTI->RTSR1, ExtiLine); 8003a34: 4b05 ldr r3, [pc, #20] @ (8003a4c ) 8003a36: 681a ldr r2, [r3, #0] 8003a38: 4904 ldr r1, [pc, #16] @ (8003a4c ) 8003a3a: 687b ldr r3, [r7, #4] 8003a3c: 4313 orrs r3, r2 8003a3e: 600b str r3, [r1, #0] } 8003a40: bf00 nop 8003a42: 370c adds r7, #12 8003a44: 46bd mov sp, r7 8003a46: f85d 7b04 ldr.w r7, [sp], #4 8003a4a: 4770 bx lr 8003a4c: 58000800 .word 0x58000800 08003a50 : * reliability of the value * @param None * @retval SSR value read */ static uint32_t ReadRtcSsrValue(void) { 8003a50: b480 push {r7} 8003a52: b083 sub sp, #12 8003a54: af00 add r7, sp, #0 uint32_t first_read; uint32_t second_read; first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); 8003a56: 4b0d ldr r3, [pc, #52] @ (8003a8c ) 8003a58: 6a9b ldr r3, [r3, #40] @ 0x28 8003a5a: b29b uxth r3, r3 8003a5c: 607b str r3, [r7, #4] second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); 8003a5e: 4b0b ldr r3, [pc, #44] @ (8003a8c ) 8003a60: 6a9b ldr r3, [r3, #40] @ 0x28 8003a62: b29b uxth r3, r3 8003a64: 603b str r3, [r7, #0] while(first_read != second_read) 8003a66: e005 b.n 8003a74 { first_read = second_read; 8003a68: 683b ldr r3, [r7, #0] 8003a6a: 607b str r3, [r7, #4] second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); 8003a6c: 4b07 ldr r3, [pc, #28] @ (8003a8c ) 8003a6e: 6a9b ldr r3, [r3, #40] @ 0x28 8003a70: b29b uxth r3, r3 8003a72: 603b str r3, [r7, #0] while(first_read != second_read) 8003a74: 687a ldr r2, [r7, #4] 8003a76: 683b ldr r3, [r7, #0] 8003a78: 429a cmp r2, r3 8003a7a: d1f5 bne.n 8003a68 } return second_read; 8003a7c: 683b ldr r3, [r7, #0] } 8003a7e: 4618 mov r0, r3 8003a80: 370c adds r7, #12 8003a82: 46bd mov sp, r7 8003a84: f85d 7b04 ldr.w r7, [sp], #4 8003a88: 4770 bx lr 8003a8a: bf00 nop 8003a8c: 40002800 .word 0x40002800 08003a90 : * @param TimerID: The ID of the Timer * @param RefTimerID: The ID of the Timer to be linked after * @retval None */ static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID) { 8003a90: b480 push {r7} 8003a92: b085 sub sp, #20 8003a94: af00 add r7, sp, #0 8003a96: 4603 mov r3, r0 8003a98: 460a mov r2, r1 8003a9a: 71fb strb r3, [r7, #7] 8003a9c: 4613 mov r3, r2 8003a9e: 71bb strb r3, [r7, #6] uint8_t next_id; next_id = aTimerContext[RefTimerID].NextID; 8003aa0: 79ba ldrb r2, [r7, #6] 8003aa2: 491d ldr r1, [pc, #116] @ (8003b18 ) 8003aa4: 4613 mov r3, r2 8003aa6: 005b lsls r3, r3, #1 8003aa8: 4413 add r3, r2 8003aaa: 00db lsls r3, r3, #3 8003aac: 440b add r3, r1 8003aae: 3315 adds r3, #21 8003ab0: 781b ldrb r3, [r3, #0] 8003ab2: 73fb strb r3, [r7, #15] if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8003ab4: 7bfb ldrb r3, [r7, #15] 8003ab6: 2b06 cmp r3, #6 8003ab8: d009 beq.n 8003ace { aTimerContext[next_id].PreviousID = TimerID; 8003aba: 7bfa ldrb r2, [r7, #15] 8003abc: 4916 ldr r1, [pc, #88] @ (8003b18 ) 8003abe: 4613 mov r3, r2 8003ac0: 005b lsls r3, r3, #1 8003ac2: 4413 add r3, r2 8003ac4: 00db lsls r3, r3, #3 8003ac6: 440b add r3, r1 8003ac8: 3314 adds r3, #20 8003aca: 79fa ldrb r2, [r7, #7] 8003acc: 701a strb r2, [r3, #0] } aTimerContext[TimerID].NextID = next_id; 8003ace: 79fa ldrb r2, [r7, #7] 8003ad0: 4911 ldr r1, [pc, #68] @ (8003b18 ) 8003ad2: 4613 mov r3, r2 8003ad4: 005b lsls r3, r3, #1 8003ad6: 4413 add r3, r2 8003ad8: 00db lsls r3, r3, #3 8003ada: 440b add r3, r1 8003adc: 3315 adds r3, #21 8003ade: 7bfa ldrb r2, [r7, #15] 8003ae0: 701a strb r2, [r3, #0] aTimerContext[TimerID].PreviousID = RefTimerID ; 8003ae2: 79fa ldrb r2, [r7, #7] 8003ae4: 490c ldr r1, [pc, #48] @ (8003b18 ) 8003ae6: 4613 mov r3, r2 8003ae8: 005b lsls r3, r3, #1 8003aea: 4413 add r3, r2 8003aec: 00db lsls r3, r3, #3 8003aee: 440b add r3, r1 8003af0: 3314 adds r3, #20 8003af2: 79ba ldrb r2, [r7, #6] 8003af4: 701a strb r2, [r3, #0] aTimerContext[RefTimerID].NextID = TimerID; 8003af6: 79ba ldrb r2, [r7, #6] 8003af8: 4907 ldr r1, [pc, #28] @ (8003b18 ) 8003afa: 4613 mov r3, r2 8003afc: 005b lsls r3, r3, #1 8003afe: 4413 add r3, r2 8003b00: 00db lsls r3, r3, #3 8003b02: 440b add r3, r1 8003b04: 3315 adds r3, #21 8003b06: 79fa ldrb r2, [r7, #7] 8003b08: 701a strb r2, [r3, #0] return; 8003b0a: bf00 nop } 8003b0c: 3714 adds r7, #20 8003b0e: 46bd mov sp, r7 8003b10: f85d 7b04 ldr.w r7, [sp], #4 8003b14: 4770 bx lr 8003b16: bf00 nop 8003b18: 20000314 .word 0x20000314 08003b1c : * @param TimerID: The ID of the Timer * @param RefTimerID: The ID of the Timer to be linked before * @retval None */ static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID) { 8003b1c: b480 push {r7} 8003b1e: b085 sub sp, #20 8003b20: af00 add r7, sp, #0 8003b22: 4603 mov r3, r0 8003b24: 460a mov r2, r1 8003b26: 71fb strb r3, [r7, #7] 8003b28: 4613 mov r3, r2 8003b2a: 71bb strb r3, [r7, #6] uint8_t previous_id; if(RefTimerID != CurrentRunningTimerID) 8003b2c: 4b29 ldr r3, [pc, #164] @ (8003bd4 ) 8003b2e: 781b ldrb r3, [r3, #0] 8003b30: b2db uxtb r3, r3 8003b32: 79ba ldrb r2, [r7, #6] 8003b34: 429a cmp r2, r3 8003b36: d032 beq.n 8003b9e { previous_id = aTimerContext[RefTimerID].PreviousID; 8003b38: 79ba ldrb r2, [r7, #6] 8003b3a: 4927 ldr r1, [pc, #156] @ (8003bd8 ) 8003b3c: 4613 mov r3, r2 8003b3e: 005b lsls r3, r3, #1 8003b40: 4413 add r3, r2 8003b42: 00db lsls r3, r3, #3 8003b44: 440b add r3, r1 8003b46: 3314 adds r3, #20 8003b48: 781b ldrb r3, [r3, #0] 8003b4a: 73fb strb r3, [r7, #15] aTimerContext[previous_id].NextID = TimerID; 8003b4c: 7bfa ldrb r2, [r7, #15] 8003b4e: 4922 ldr r1, [pc, #136] @ (8003bd8 ) 8003b50: 4613 mov r3, r2 8003b52: 005b lsls r3, r3, #1 8003b54: 4413 add r3, r2 8003b56: 00db lsls r3, r3, #3 8003b58: 440b add r3, r1 8003b5a: 3315 adds r3, #21 8003b5c: 79fa ldrb r2, [r7, #7] 8003b5e: 701a strb r2, [r3, #0] aTimerContext[TimerID].NextID = RefTimerID; 8003b60: 79fa ldrb r2, [r7, #7] 8003b62: 491d ldr r1, [pc, #116] @ (8003bd8 ) 8003b64: 4613 mov r3, r2 8003b66: 005b lsls r3, r3, #1 8003b68: 4413 add r3, r2 8003b6a: 00db lsls r3, r3, #3 8003b6c: 440b add r3, r1 8003b6e: 3315 adds r3, #21 8003b70: 79ba ldrb r2, [r7, #6] 8003b72: 701a strb r2, [r3, #0] aTimerContext[TimerID].PreviousID = previous_id ; 8003b74: 79fa ldrb r2, [r7, #7] 8003b76: 4918 ldr r1, [pc, #96] @ (8003bd8 ) 8003b78: 4613 mov r3, r2 8003b7a: 005b lsls r3, r3, #1 8003b7c: 4413 add r3, r2 8003b7e: 00db lsls r3, r3, #3 8003b80: 440b add r3, r1 8003b82: 3314 adds r3, #20 8003b84: 7bfa ldrb r2, [r7, #15] 8003b86: 701a strb r2, [r3, #0] aTimerContext[RefTimerID].PreviousID = TimerID; 8003b88: 79ba ldrb r2, [r7, #6] 8003b8a: 4913 ldr r1, [pc, #76] @ (8003bd8 ) 8003b8c: 4613 mov r3, r2 8003b8e: 005b lsls r3, r3, #1 8003b90: 4413 add r3, r2 8003b92: 00db lsls r3, r3, #3 8003b94: 440b add r3, r1 8003b96: 3314 adds r3, #20 8003b98: 79fa ldrb r2, [r7, #7] 8003b9a: 701a strb r2, [r3, #0] { aTimerContext[TimerID].NextID = RefTimerID; aTimerContext[RefTimerID].PreviousID = TimerID; } return; 8003b9c: e014 b.n 8003bc8 aTimerContext[TimerID].NextID = RefTimerID; 8003b9e: 79fa ldrb r2, [r7, #7] 8003ba0: 490d ldr r1, [pc, #52] @ (8003bd8 ) 8003ba2: 4613 mov r3, r2 8003ba4: 005b lsls r3, r3, #1 8003ba6: 4413 add r3, r2 8003ba8: 00db lsls r3, r3, #3 8003baa: 440b add r3, r1 8003bac: 3315 adds r3, #21 8003bae: 79ba ldrb r2, [r7, #6] 8003bb0: 701a strb r2, [r3, #0] aTimerContext[RefTimerID].PreviousID = TimerID; 8003bb2: 79ba ldrb r2, [r7, #6] 8003bb4: 4908 ldr r1, [pc, #32] @ (8003bd8 ) 8003bb6: 4613 mov r3, r2 8003bb8: 005b lsls r3, r3, #1 8003bba: 4413 add r3, r2 8003bbc: 00db lsls r3, r3, #3 8003bbe: 440b add r3, r1 8003bc0: 3314 adds r3, #20 8003bc2: 79fa ldrb r2, [r7, #7] 8003bc4: 701a strb r2, [r3, #0] return; 8003bc6: bf00 nop } 8003bc8: 3714 adds r7, #20 8003bca: 46bd mov sp, r7 8003bcc: f85d 7b04 ldr.w r7, [sp], #4 8003bd0: 4770 bx lr 8003bd2: bf00 nop 8003bd4: 200003a4 .word 0x200003a4 8003bd8: 20000314 .word 0x20000314 08003bdc : * @brief Insert a Timer in the list * @param TimerID: The ID of the Timer * @retval None */ static uint16_t linkTimer(uint8_t TimerID) { 8003bdc: b580 push {r7, lr} 8003bde: b084 sub sp, #16 8003be0: af00 add r7, sp, #0 8003be2: 4603 mov r3, r0 8003be4: 71fb strb r3, [r7, #7] uint32_t time_left; uint16_t time_elapsed; uint8_t timer_id_lookup; uint8_t next_id; if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8003be6: 4b4e ldr r3, [pc, #312] @ (8003d20 ) 8003be8: 781b ldrb r3, [r3, #0] 8003bea: b2db uxtb r3, r3 8003bec: 2b06 cmp r3, #6 8003bee: d118 bne.n 8003c22 { /** * No timer in the list */ PreviousRunningTimerID = CurrentRunningTimerID; 8003bf0: 4b4b ldr r3, [pc, #300] @ (8003d20 ) 8003bf2: 781b ldrb r3, [r3, #0] 8003bf4: b2da uxtb r2, r3 8003bf6: 4b4b ldr r3, [pc, #300] @ (8003d24 ) 8003bf8: 701a strb r2, [r3, #0] CurrentRunningTimerID = TimerID; 8003bfa: 4a49 ldr r2, [pc, #292] @ (8003d20 ) 8003bfc: 79fb ldrb r3, [r7, #7] 8003bfe: 7013 strb r3, [r2, #0] aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; 8003c00: 79fa ldrb r2, [r7, #7] 8003c02: 4949 ldr r1, [pc, #292] @ (8003d28 ) 8003c04: 4613 mov r3, r2 8003c06: 005b lsls r3, r3, #1 8003c08: 4413 add r3, r2 8003c0a: 00db lsls r3, r3, #3 8003c0c: 440b add r3, r1 8003c0e: 3315 adds r3, #21 8003c10: 2206 movs r2, #6 8003c12: 701a strb r2, [r3, #0] SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; 8003c14: 4b45 ldr r3, [pc, #276] @ (8003d2c ) 8003c16: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8003c1a: 601a str r2, [r3, #0] time_elapsed = 0; 8003c1c: 2300 movs r3, #0 8003c1e: 81fb strh r3, [r7, #14] 8003c20: e078 b.n 8003d14 } else { time_elapsed = ReturnTimeElapsed(); 8003c22: f000 f909 bl 8003e38 8003c26: 4603 mov r3, r0 8003c28: 81fb strh r3, [r7, #14] /** * update count of the timer to be linked */ aTimerContext[TimerID].CountLeft += time_elapsed; 8003c2a: 79fa ldrb r2, [r7, #7] 8003c2c: 493e ldr r1, [pc, #248] @ (8003d28 ) 8003c2e: 4613 mov r3, r2 8003c30: 005b lsls r3, r3, #1 8003c32: 4413 add r3, r2 8003c34: 00db lsls r3, r3, #3 8003c36: 440b add r3, r1 8003c38: 3308 adds r3, #8 8003c3a: 6819 ldr r1, [r3, #0] 8003c3c: 89fb ldrh r3, [r7, #14] 8003c3e: 79fa ldrb r2, [r7, #7] 8003c40: 4419 add r1, r3 8003c42: 4839 ldr r0, [pc, #228] @ (8003d28 ) 8003c44: 4613 mov r3, r2 8003c46: 005b lsls r3, r3, #1 8003c48: 4413 add r3, r2 8003c4a: 00db lsls r3, r3, #3 8003c4c: 4403 add r3, r0 8003c4e: 3308 adds r3, #8 8003c50: 6019 str r1, [r3, #0] time_left = aTimerContext[TimerID].CountLeft; 8003c52: 79fa ldrb r2, [r7, #7] 8003c54: 4934 ldr r1, [pc, #208] @ (8003d28 ) 8003c56: 4613 mov r3, r2 8003c58: 005b lsls r3, r3, #1 8003c5a: 4413 add r3, r2 8003c5c: 00db lsls r3, r3, #3 8003c5e: 440b add r3, r1 8003c60: 3308 adds r3, #8 8003c62: 681b ldr r3, [r3, #0] 8003c64: 60bb str r3, [r7, #8] /** * Search for index where the new timer shall be linked */ if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left) 8003c66: 4b2e ldr r3, [pc, #184] @ (8003d20 ) 8003c68: 781b ldrb r3, [r3, #0] 8003c6a: b2db uxtb r3, r3 8003c6c: 4619 mov r1, r3 8003c6e: 4a2e ldr r2, [pc, #184] @ (8003d28 ) 8003c70: 460b mov r3, r1 8003c72: 005b lsls r3, r3, #1 8003c74: 440b add r3, r1 8003c76: 00db lsls r3, r3, #3 8003c78: 4413 add r3, r2 8003c7a: 3308 adds r3, #8 8003c7c: 681b ldr r3, [r3, #0] 8003c7e: 68ba ldr r2, [r7, #8] 8003c80: 429a cmp r2, r3 8003c82: d337 bcc.n 8003cf4 { /** * Search for the ID after the first one */ timer_id_lookup = CurrentRunningTimerID; 8003c84: 4b26 ldr r3, [pc, #152] @ (8003d20 ) 8003c86: 781b ldrb r3, [r3, #0] 8003c88: 737b strb r3, [r7, #13] next_id = aTimerContext[timer_id_lookup].NextID; 8003c8a: 7b7a ldrb r2, [r7, #13] 8003c8c: 4926 ldr r1, [pc, #152] @ (8003d28 ) 8003c8e: 4613 mov r3, r2 8003c90: 005b lsls r3, r3, #1 8003c92: 4413 add r3, r2 8003c94: 00db lsls r3, r3, #3 8003c96: 440b add r3, r1 8003c98: 3315 adds r3, #21 8003c9a: 781b ldrb r3, [r3, #0] 8003c9c: 733b strb r3, [r7, #12] while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left)) 8003c9e: e013 b.n 8003cc8 { timer_id_lookup = aTimerContext[timer_id_lookup].NextID; 8003ca0: 7b7a ldrb r2, [r7, #13] 8003ca2: 4921 ldr r1, [pc, #132] @ (8003d28 ) 8003ca4: 4613 mov r3, r2 8003ca6: 005b lsls r3, r3, #1 8003ca8: 4413 add r3, r2 8003caa: 00db lsls r3, r3, #3 8003cac: 440b add r3, r1 8003cae: 3315 adds r3, #21 8003cb0: 781b ldrb r3, [r3, #0] 8003cb2: 737b strb r3, [r7, #13] next_id = aTimerContext[timer_id_lookup].NextID; 8003cb4: 7b7a ldrb r2, [r7, #13] 8003cb6: 491c ldr r1, [pc, #112] @ (8003d28 ) 8003cb8: 4613 mov r3, r2 8003cba: 005b lsls r3, r3, #1 8003cbc: 4413 add r3, r2 8003cbe: 00db lsls r3, r3, #3 8003cc0: 440b add r3, r1 8003cc2: 3315 adds r3, #21 8003cc4: 781b ldrb r3, [r3, #0] 8003cc6: 733b strb r3, [r7, #12] while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left)) 8003cc8: 7b3b ldrb r3, [r7, #12] 8003cca: 2b06 cmp r3, #6 8003ccc: d00b beq.n 8003ce6 8003cce: 7b3a ldrb r2, [r7, #12] 8003cd0: 4915 ldr r1, [pc, #84] @ (8003d28 ) 8003cd2: 4613 mov r3, r2 8003cd4: 005b lsls r3, r3, #1 8003cd6: 4413 add r3, r2 8003cd8: 00db lsls r3, r3, #3 8003cda: 440b add r3, r1 8003cdc: 3308 adds r3, #8 8003cde: 681b ldr r3, [r3, #0] 8003ce0: 68ba ldr r2, [r7, #8] 8003ce2: 429a cmp r2, r3 8003ce4: d2dc bcs.n 8003ca0 } /** * Link after the ID */ LinkTimerAfter(TimerID, timer_id_lookup); 8003ce6: 7b7a ldrb r2, [r7, #13] 8003ce8: 79fb ldrb r3, [r7, #7] 8003cea: 4611 mov r1, r2 8003cec: 4618 mov r0, r3 8003cee: f7ff fecf bl 8003a90 8003cf2: e00f b.n 8003d14 else { /** * Link before the first ID */ LinkTimerBefore(TimerID, CurrentRunningTimerID); 8003cf4: 4b0a ldr r3, [pc, #40] @ (8003d20 ) 8003cf6: 781b ldrb r3, [r3, #0] 8003cf8: b2da uxtb r2, r3 8003cfa: 79fb ldrb r3, [r7, #7] 8003cfc: 4611 mov r1, r2 8003cfe: 4618 mov r0, r3 8003d00: f7ff ff0c bl 8003b1c PreviousRunningTimerID = CurrentRunningTimerID; 8003d04: 4b06 ldr r3, [pc, #24] @ (8003d20 ) 8003d06: 781b ldrb r3, [r3, #0] 8003d08: b2da uxtb r2, r3 8003d0a: 4b06 ldr r3, [pc, #24] @ (8003d24 ) 8003d0c: 701a strb r2, [r3, #0] CurrentRunningTimerID = TimerID; 8003d0e: 4a04 ldr r2, [pc, #16] @ (8003d20 ) 8003d10: 79fb ldrb r3, [r7, #7] 8003d12: 7013 strb r3, [r2, #0] } } return time_elapsed; 8003d14: 89fb ldrh r3, [r7, #14] } 8003d16: 4618 mov r0, r3 8003d18: 3710 adds r7, #16 8003d1a: 46bd mov sp, r7 8003d1c: bd80 pop {r7, pc} 8003d1e: bf00 nop 8003d20: 200003a4 .word 0x200003a4 8003d24: 200003a5 .word 0x200003a5 8003d28: 20000314 .word 0x20000314 8003d2c: 200003a8 .word 0x200003a8 08003d30 : * @param TimerID: The ID of the Timer * @param RequestReadSSR: Request to read the SSR register or not * @retval None */ static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR) { 8003d30: b480 push {r7} 8003d32: b085 sub sp, #20 8003d34: af00 add r7, sp, #0 8003d36: 4603 mov r3, r0 8003d38: 460a mov r2, r1 8003d3a: 71fb strb r3, [r7, #7] 8003d3c: 4613 mov r3, r2 8003d3e: 71bb strb r3, [r7, #6] uint8_t previous_id; uint8_t next_id; if(TimerID == CurrentRunningTimerID) 8003d40: 4b39 ldr r3, [pc, #228] @ (8003e28 ) 8003d42: 781b ldrb r3, [r3, #0] 8003d44: b2db uxtb r3, r3 8003d46: 79fa ldrb r2, [r7, #7] 8003d48: 429a cmp r2, r3 8003d4a: d111 bne.n 8003d70 { PreviousRunningTimerID = CurrentRunningTimerID; 8003d4c: 4b36 ldr r3, [pc, #216] @ (8003e28 ) 8003d4e: 781b ldrb r3, [r3, #0] 8003d50: b2da uxtb r2, r3 8003d52: 4b36 ldr r3, [pc, #216] @ (8003e2c ) 8003d54: 701a strb r2, [r3, #0] CurrentRunningTimerID = aTimerContext[TimerID].NextID; 8003d56: 79fa ldrb r2, [r7, #7] 8003d58: 4935 ldr r1, [pc, #212] @ (8003e30 ) 8003d5a: 4613 mov r3, r2 8003d5c: 005b lsls r3, r3, #1 8003d5e: 4413 add r3, r2 8003d60: 00db lsls r3, r3, #3 8003d62: 440b add r3, r1 8003d64: 3315 adds r3, #21 8003d66: 781b ldrb r3, [r3, #0] 8003d68: b2da uxtb r2, r3 8003d6a: 4b2f ldr r3, [pc, #188] @ (8003e28 ) 8003d6c: 701a strb r2, [r3, #0] 8003d6e: e03e b.n 8003dee } else { previous_id = aTimerContext[TimerID].PreviousID; 8003d70: 79fa ldrb r2, [r7, #7] 8003d72: 492f ldr r1, [pc, #188] @ (8003e30 ) 8003d74: 4613 mov r3, r2 8003d76: 005b lsls r3, r3, #1 8003d78: 4413 add r3, r2 8003d7a: 00db lsls r3, r3, #3 8003d7c: 440b add r3, r1 8003d7e: 3314 adds r3, #20 8003d80: 781b ldrb r3, [r3, #0] 8003d82: 73fb strb r3, [r7, #15] next_id = aTimerContext[TimerID].NextID; 8003d84: 79fa ldrb r2, [r7, #7] 8003d86: 492a ldr r1, [pc, #168] @ (8003e30 ) 8003d88: 4613 mov r3, r2 8003d8a: 005b lsls r3, r3, #1 8003d8c: 4413 add r3, r2 8003d8e: 00db lsls r3, r3, #3 8003d90: 440b add r3, r1 8003d92: 3315 adds r3, #21 8003d94: 781b ldrb r3, [r3, #0] 8003d96: 73bb strb r3, [r7, #14] aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID; 8003d98: 79f9 ldrb r1, [r7, #7] 8003d9a: 7bfa ldrb r2, [r7, #15] 8003d9c: 4824 ldr r0, [pc, #144] @ (8003e30 ) 8003d9e: 460b mov r3, r1 8003da0: 005b lsls r3, r3, #1 8003da2: 440b add r3, r1 8003da4: 00db lsls r3, r3, #3 8003da6: 4403 add r3, r0 8003da8: 3315 adds r3, #21 8003daa: 781b ldrb r3, [r3, #0] 8003dac: b2d8 uxtb r0, r3 8003dae: 4920 ldr r1, [pc, #128] @ (8003e30 ) 8003db0: 4613 mov r3, r2 8003db2: 005b lsls r3, r3, #1 8003db4: 4413 add r3, r2 8003db6: 00db lsls r3, r3, #3 8003db8: 440b add r3, r1 8003dba: 3315 adds r3, #21 8003dbc: 4602 mov r2, r0 8003dbe: 701a strb r2, [r3, #0] if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8003dc0: 7bbb ldrb r3, [r7, #14] 8003dc2: 2b06 cmp r3, #6 8003dc4: d013 beq.n 8003dee { aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID; 8003dc6: 79f9 ldrb r1, [r7, #7] 8003dc8: 7bba ldrb r2, [r7, #14] 8003dca: 4819 ldr r0, [pc, #100] @ (8003e30 ) 8003dcc: 460b mov r3, r1 8003dce: 005b lsls r3, r3, #1 8003dd0: 440b add r3, r1 8003dd2: 00db lsls r3, r3, #3 8003dd4: 4403 add r3, r0 8003dd6: 3314 adds r3, #20 8003dd8: 781b ldrb r3, [r3, #0] 8003dda: b2d8 uxtb r0, r3 8003ddc: 4914 ldr r1, [pc, #80] @ (8003e30 ) 8003dde: 4613 mov r3, r2 8003de0: 005b lsls r3, r3, #1 8003de2: 4413 add r3, r2 8003de4: 00db lsls r3, r3, #3 8003de6: 440b add r3, r1 8003de8: 3314 adds r3, #20 8003dea: 4602 mov r2, r0 8003dec: 701a strb r2, [r3, #0] } /** * Timer is out of the list */ aTimerContext[TimerID].TimerIDStatus = TimerID_Created; 8003dee: 79fa ldrb r2, [r7, #7] 8003df0: 490f ldr r1, [pc, #60] @ (8003e30 ) 8003df2: 4613 mov r3, r2 8003df4: 005b lsls r3, r3, #1 8003df6: 4413 add r3, r2 8003df8: 00db lsls r3, r3, #3 8003dfa: 440b add r3, r1 8003dfc: 330c adds r3, #12 8003dfe: 2201 movs r2, #1 8003e00: 701a strb r2, [r3, #0] if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested)) 8003e02: 4b09 ldr r3, [pc, #36] @ (8003e28 ) 8003e04: 781b ldrb r3, [r3, #0] 8003e06: b2db uxtb r3, r3 8003e08: 2b06 cmp r3, #6 8003e0a: d107 bne.n 8003e1c 8003e0c: 79bb ldrb r3, [r7, #6] 8003e0e: 2b00 cmp r3, #0 8003e10: d104 bne.n 8003e1c { SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; 8003e12: 4b08 ldr r3, [pc, #32] @ (8003e34 ) 8003e14: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8003e18: 601a str r2, [r3, #0] } return; 8003e1a: bf00 nop 8003e1c: bf00 nop } 8003e1e: 3714 adds r7, #20 8003e20: 46bd mov sp, r7 8003e22: f85d 7b04 ldr.w r7, [sp], #4 8003e26: 4770 bx lr 8003e28: 200003a4 .word 0x200003a4 8003e2c: 200003a5 .word 0x200003a5 8003e30: 20000314 .word 0x20000314 8003e34: 200003a8 .word 0x200003a8 08003e38 : * since the time the timer has been started * @param None * @retval Time expired in Ticks */ static uint16_t ReturnTimeElapsed(void) { 8003e38: b580 push {r7, lr} 8003e3a: b082 sub sp, #8 8003e3c: af00 add r7, sp, #0 uint32_t return_value; uint32_t wrap_counter; if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE) 8003e3e: 4b1a ldr r3, [pc, #104] @ (8003ea8 ) 8003e40: 681b ldr r3, [r3, #0] 8003e42: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8003e46: d026 beq.n 8003e96 { return_value = ReadRtcSsrValue(); /**< Read SSR register first */ 8003e48: f7ff fe02 bl 8003a50 8003e4c: 6078 str r0, [r7, #4] if (SSRValueOnLastSetup >= return_value) 8003e4e: 4b16 ldr r3, [pc, #88] @ (8003ea8 ) 8003e50: 681b ldr r3, [r3, #0] 8003e52: 687a ldr r2, [r7, #4] 8003e54: 429a cmp r2, r3 8003e56: d805 bhi.n 8003e64 { return_value = SSRValueOnLastSetup - return_value; 8003e58: 4b13 ldr r3, [pc, #76] @ (8003ea8 ) 8003e5a: 681a ldr r2, [r3, #0] 8003e5c: 687b ldr r3, [r7, #4] 8003e5e: 1ad3 subs r3, r2, r3 8003e60: 607b str r3, [r7, #4] 8003e62: e00a b.n 8003e7a } else { wrap_counter = SynchPrescalerUserConfig - return_value; 8003e64: 4b11 ldr r3, [pc, #68] @ (8003eac ) 8003e66: 881b ldrh r3, [r3, #0] 8003e68: 461a mov r2, r3 8003e6a: 687b ldr r3, [r7, #4] 8003e6c: 1ad3 subs r3, r2, r3 8003e6e: 603b str r3, [r7, #0] return_value = SSRValueOnLastSetup + wrap_counter; 8003e70: 4b0d ldr r3, [pc, #52] @ (8003ea8 ) 8003e72: 681b ldr r3, [r3, #0] 8003e74: 683a ldr r2, [r7, #0] 8003e76: 4413 add r3, r2 8003e78: 607b str r3, [r7, #4] /** * At this stage, ReturnValue holds the number of ticks counted by SSR * Need to translate in number of ticks counted by the Wakeuptimer */ return_value = return_value*AsynchPrescalerUserConfig; 8003e7a: 4b0d ldr r3, [pc, #52] @ (8003eb0 ) 8003e7c: 781b ldrb r3, [r3, #0] 8003e7e: 461a mov r2, r3 8003e80: 687b ldr r3, [r7, #4] 8003e82: fb02 f303 mul.w r3, r2, r3 8003e86: 607b str r3, [r7, #4] return_value = return_value >> WakeupTimerDivider; 8003e88: 4b0a ldr r3, [pc, #40] @ (8003eb4 ) 8003e8a: 781b ldrb r3, [r3, #0] 8003e8c: 461a mov r2, r3 8003e8e: 687b ldr r3, [r7, #4] 8003e90: 40d3 lsrs r3, r2 8003e92: 607b str r3, [r7, #4] 8003e94: e001 b.n 8003e9a } else { return_value = 0; 8003e96: 2300 movs r3, #0 8003e98: 607b str r3, [r7, #4] } return (uint16_t)return_value; 8003e9a: 687b ldr r3, [r7, #4] 8003e9c: b29b uxth r3, r3 } 8003e9e: 4618 mov r0, r3 8003ea0: 3708 adds r7, #8 8003ea2: 46bd mov sp, r7 8003ea4: bd80 pop {r7, pc} 8003ea6: bf00 nop 8003ea8: 200003a8 .word 0x200003a8 8003eac: 200003b0 .word 0x200003b0 8003eb0: 200003ae .word 0x200003ae 8003eb4: 200003ad .word 0x200003ad 08003eb8 : * It assumes all condition are met to be allowed to write the wakeup counter * @param Value: Value to be written in the counter * @retval None */ static void RestartWakeupCounter(uint16_t Value) { 8003eb8: b580 push {r7, lr} 8003eba: b082 sub sp, #8 8003ebc: af00 add r7, sp, #0 8003ebe: 4603 mov r3, r0 8003ec0: 80fb strh r3, [r7, #6] * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF * FLAG when the new value will have to be written * __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); */ if(Value == 0) 8003ec2: 88fb ldrh r3, [r7, #6] 8003ec4: 2b00 cmp r3, #0 8003ec6: d108 bne.n 8003eda { SSRValueOnLastSetup = ReadRtcSsrValue(); 8003ec8: f7ff fdc2 bl 8003a50 8003ecc: 4603 mov r3, r0 8003ece: 4a21 ldr r2, [pc, #132] @ (8003f54 ) 8003ed0: 6013 str r3, [r2, #0] /** * Simulate that the Timer expired */ HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); 8003ed2: 2003 movs r0, #3 8003ed4: f002 fc32 bl 800673c __HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */ HW_TS_RTC_CountUpdated_AppNot(); } return ; 8003ed8: e039 b.n 8003f4e if((Value > 1) ||(WakeupTimerDivider != 1)) 8003eda: 88fb ldrh r3, [r7, #6] 8003edc: 2b01 cmp r3, #1 8003ede: d803 bhi.n 8003ee8 8003ee0: 4b1d ldr r3, [pc, #116] @ (8003f58 ) 8003ee2: 781b ldrb r3, [r3, #0] 8003ee4: 2b01 cmp r3, #1 8003ee6: d002 beq.n 8003eee Value -= 1; 8003ee8: 88fb ldrh r3, [r7, #6] 8003eea: 3b01 subs r3, #1 8003eec: 80fb strh r3, [r7, #6] while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET); 8003eee: bf00 nop 8003ef0: 4b1a ldr r3, [pc, #104] @ (8003f5c ) 8003ef2: 681b ldr r3, [r3, #0] 8003ef4: 68db ldr r3, [r3, #12] 8003ef6: f003 0304 and.w r3, r3, #4 8003efa: 2b00 cmp r3, #0 8003efc: d0f8 beq.n 8003ef0 __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ 8003efe: 4b17 ldr r3, [pc, #92] @ (8003f5c ) 8003f00: 681b ldr r3, [r3, #0] 8003f02: 68db ldr r3, [r3, #12] 8003f04: b2da uxtb r2, r3 8003f06: 4b15 ldr r3, [pc, #84] @ (8003f5c ) 8003f08: 681b ldr r3, [r3, #0] 8003f0a: f462 6290 orn r2, r2, #1152 @ 0x480 8003f0e: 60da str r2, [r3, #12] __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ 8003f10: 4b13 ldr r3, [pc, #76] @ (8003f60 ) 8003f12: f44f 2200 mov.w r2, #524288 @ 0x80000 8003f16: 60da str r2, [r3, #12] HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ 8003f18: 2003 movs r0, #3 8003f1a: f002 fc1d bl 8006758 MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value); 8003f1e: 4b11 ldr r3, [pc, #68] @ (8003f64 ) 8003f20: 695b ldr r3, [r3, #20] 8003f22: 0c1b lsrs r3, r3, #16 8003f24: 041b lsls r3, r3, #16 8003f26: 88fa ldrh r2, [r7, #6] 8003f28: 490e ldr r1, [pc, #56] @ (8003f64 ) 8003f2a: 4313 orrs r3, r2 8003f2c: 614b str r3, [r1, #20] SSRValueOnLastSetup = ReadRtcSsrValue(); 8003f2e: f7ff fd8f bl 8003a50 8003f32: 4603 mov r3, r0 8003f34: 4a07 ldr r2, [pc, #28] @ (8003f54 ) 8003f36: 6013 str r3, [r2, #0] __HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */ 8003f38: 4b08 ldr r3, [pc, #32] @ (8003f5c ) 8003f3a: 681b ldr r3, [r3, #0] 8003f3c: 689a ldr r2, [r3, #8] 8003f3e: 4b07 ldr r3, [pc, #28] @ (8003f5c ) 8003f40: 681b ldr r3, [r3, #0] 8003f42: f442 6280 orr.w r2, r2, #1024 @ 0x400 8003f46: 609a str r2, [r3, #8] HW_TS_RTC_CountUpdated_AppNot(); 8003f48: f3af 8000 nop.w return ; 8003f4c: bf00 nop } 8003f4e: 3708 adds r7, #8 8003f50: 46bd mov sp, r7 8003f52: bd80 pop {r7, pc} 8003f54: 200003a8 .word 0x200003a8 8003f58: 200003ad .word 0x200003ad 8003f5c: 20000504 .word 0x20000504 8003f60: 58000800 .word 0x58000800 8003f64: 40002800 .word 0x40002800 08003f68 : * 2) Setup the wakeuptimer * @param None * @retval None */ static void RescheduleTimerList(void) { 8003f68: b580 push {r7, lr} 8003f6a: b084 sub sp, #16 8003f6c: af00 add r7, sp, #0 /** * The wakeuptimer is disabled now to reduce the time to poll the WUTWF * FLAG when the new value will have to be written */ if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET) 8003f6e: 4b45 ldr r3, [pc, #276] @ (8004084 ) 8003f70: 689b ldr r3, [r3, #8] 8003f72: f403 6380 and.w r3, r3, #1024 @ 0x400 8003f76: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003f7a: d107 bne.n 8003f8c { /** * Wait for the flag to be back to 0 when the wakeup timer is enabled */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET); 8003f7c: bf00 nop 8003f7e: 4b42 ldr r3, [pc, #264] @ (8004088 ) 8003f80: 681b ldr r3, [r3, #0] 8003f82: 68db ldr r3, [r3, #12] 8003f84: f003 0304 and.w r3, r3, #4 8003f88: 2b00 cmp r3, #0 8003f8a: d1f8 bne.n 8003f7e } __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ 8003f8c: 4b3e ldr r3, [pc, #248] @ (8004088 ) 8003f8e: 681b ldr r3, [r3, #0] 8003f90: 689a ldr r2, [r3, #8] 8003f92: 4b3d ldr r3, [pc, #244] @ (8004088 ) 8003f94: 681b ldr r3, [r3, #0] 8003f96: f422 6280 bic.w r2, r2, #1024 @ 0x400 8003f9a: 609a str r2, [r3, #8] localTimerID = CurrentRunningTimerID; 8003f9c: 4b3b ldr r3, [pc, #236] @ (800408c ) 8003f9e: 781b ldrb r3, [r3, #0] 8003fa0: 73fb strb r3, [r7, #15] /** * Calculate what will be the value to write in the wakeuptimer */ timecountleft = aTimerContext[localTimerID].CountLeft; 8003fa2: 7bfa ldrb r2, [r7, #15] 8003fa4: 493a ldr r1, [pc, #232] @ (8004090 ) 8003fa6: 4613 mov r3, r2 8003fa8: 005b lsls r3, r3, #1 8003faa: 4413 add r3, r2 8003fac: 00db lsls r3, r3, #3 8003fae: 440b add r3, r1 8003fb0: 3308 adds r3, #8 8003fb2: 681b ldr r3, [r3, #0] 8003fb4: 60bb str r3, [r7, #8] /** * Read how much has been counted */ time_elapsed = ReturnTimeElapsed(); 8003fb6: f7ff ff3f bl 8003e38 8003fba: 4603 mov r3, r0 8003fbc: 80fb strh r3, [r7, #6] if(timecountleft < time_elapsed ) 8003fbe: 88fb ldrh r3, [r7, #6] 8003fc0: 68ba ldr r2, [r7, #8] 8003fc2: 429a cmp r2, r3 8003fc4: d205 bcs.n 8003fd2 { /** * There is no tick left to count */ wakeup_timer_value = 0; 8003fc6: 2300 movs r3, #0 8003fc8: 81bb strh r3, [r7, #12] WakeupTimerLimitation = WakeupTimerValue_LargeEnough; 8003fca: 4b32 ldr r3, [pc, #200] @ (8004094 ) 8003fcc: 2201 movs r2, #1 8003fce: 701a strb r2, [r3, #0] 8003fd0: e04d b.n 800406e } else { if(timecountleft > (time_elapsed + MaxWakeupTimerSetup)) 8003fd2: 88fb ldrh r3, [r7, #6] 8003fd4: 4a30 ldr r2, [pc, #192] @ (8004098 ) 8003fd6: 8812 ldrh r2, [r2, #0] 8003fd8: b292 uxth r2, r2 8003fda: 4413 add r3, r2 8003fdc: 461a mov r2, r3 8003fde: 68bb ldr r3, [r7, #8] 8003fe0: 4293 cmp r3, r2 8003fe2: d906 bls.n 8003ff2 { /** * The number of tick left is greater than the Wakeuptimer maximum value */ wakeup_timer_value = MaxWakeupTimerSetup; 8003fe4: 4b2c ldr r3, [pc, #176] @ (8004098 ) 8003fe6: 881b ldrh r3, [r3, #0] 8003fe8: 81bb strh r3, [r7, #12] WakeupTimerLimitation = WakeupTimerValue_Overpassed; 8003fea: 4b2a ldr r3, [pc, #168] @ (8004094 ) 8003fec: 2200 movs r2, #0 8003fee: 701a strb r2, [r3, #0] 8003ff0: e03d b.n 800406e } else { wakeup_timer_value = timecountleft - time_elapsed; 8003ff2: 68bb ldr r3, [r7, #8] 8003ff4: b29a uxth r2, r3 8003ff6: 88fb ldrh r3, [r7, #6] 8003ff8: 1ad3 subs r3, r2, r3 8003ffa: 81bb strh r3, [r7, #12] WakeupTimerLimitation = WakeupTimerValue_LargeEnough; 8003ffc: 4b25 ldr r3, [pc, #148] @ (8004094 ) 8003ffe: 2201 movs r2, #1 8004000: 701a strb r2, [r3, #0] } /** * update ticks left to be counted for each timer */ while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8004002: e034 b.n 800406e { if (aTimerContext[localTimerID].CountLeft < time_elapsed) 8004004: 7bfa ldrb r2, [r7, #15] 8004006: 4922 ldr r1, [pc, #136] @ (8004090 ) 8004008: 4613 mov r3, r2 800400a: 005b lsls r3, r3, #1 800400c: 4413 add r3, r2 800400e: 00db lsls r3, r3, #3 8004010: 440b add r3, r1 8004012: 3308 adds r3, #8 8004014: 681a ldr r2, [r3, #0] 8004016: 88fb ldrh r3, [r7, #6] 8004018: 429a cmp r2, r3 800401a: d20a bcs.n 8004032 { aTimerContext[localTimerID].CountLeft = 0; 800401c: 7bfa ldrb r2, [r7, #15] 800401e: 491c ldr r1, [pc, #112] @ (8004090 ) 8004020: 4613 mov r3, r2 8004022: 005b lsls r3, r3, #1 8004024: 4413 add r3, r2 8004026: 00db lsls r3, r3, #3 8004028: 440b add r3, r1 800402a: 3308 adds r3, #8 800402c: 2200 movs r2, #0 800402e: 601a str r2, [r3, #0] 8004030: e013 b.n 800405a } else { aTimerContext[localTimerID].CountLeft -= time_elapsed; 8004032: 7bfa ldrb r2, [r7, #15] 8004034: 4916 ldr r1, [pc, #88] @ (8004090 ) 8004036: 4613 mov r3, r2 8004038: 005b lsls r3, r3, #1 800403a: 4413 add r3, r2 800403c: 00db lsls r3, r3, #3 800403e: 440b add r3, r1 8004040: 3308 adds r3, #8 8004042: 6819 ldr r1, [r3, #0] 8004044: 88fb ldrh r3, [r7, #6] 8004046: 7bfa ldrb r2, [r7, #15] 8004048: 1ac9 subs r1, r1, r3 800404a: 4811 ldr r0, [pc, #68] @ (8004090 ) 800404c: 4613 mov r3, r2 800404e: 005b lsls r3, r3, #1 8004050: 4413 add r3, r2 8004052: 00db lsls r3, r3, #3 8004054: 4403 add r3, r0 8004056: 3308 adds r3, #8 8004058: 6019 str r1, [r3, #0] } localTimerID = aTimerContext[localTimerID].NextID; 800405a: 7bfa ldrb r2, [r7, #15] 800405c: 490c ldr r1, [pc, #48] @ (8004090 ) 800405e: 4613 mov r3, r2 8004060: 005b lsls r3, r3, #1 8004062: 4413 add r3, r2 8004064: 00db lsls r3, r3, #3 8004066: 440b add r3, r1 8004068: 3315 adds r3, #21 800406a: 781b ldrb r3, [r3, #0] 800406c: 73fb strb r3, [r7, #15] while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 800406e: 7bfb ldrb r3, [r7, #15] 8004070: 2b06 cmp r3, #6 8004072: d1c7 bne.n 8004004 } /** * Write next count */ RestartWakeupCounter(wakeup_timer_value); 8004074: 89bb ldrh r3, [r7, #12] 8004076: 4618 mov r0, r3 8004078: f7ff ff1e bl 8003eb8 return ; 800407c: bf00 nop } 800407e: 3710 adds r7, #16 8004080: 46bd mov sp, r7 8004082: bd80 pop {r7, pc} 8004084: 40002800 .word 0x40002800 8004088: 20000504 .word 0x20000504 800408c: 200003a4 .word 0x200003a4 8004090: 20000314 .word 0x20000314 8004094: 200003ac .word 0x200003ac 8004098: 200003b2 .word 0x200003b2 0800409c : * In order to ease maintainability, the unlock is done at the top and the lock at then end * in case some new implementation is coming in the future */ void HW_TS_RTC_Wakeup_Handler(void) { 800409c: b580 push {r7, lr} 800409e: b08a sub sp, #40 @ 0x28 80040a0: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80040a2: f3ef 8310 mrs r3, PRIMASK 80040a6: 617b str r3, [r7, #20] return(result); 80040a8: 697b ldr r3, [r7, #20] #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) uint32_t primask_bit; #endif #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 80040aa: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("cpsid i" : : : "memory"); 80040ac: b672 cpsid i } 80040ae: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ #endif /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 80040b0: 4b59 ldr r3, [pc, #356] @ (8004218 ) 80040b2: 681b ldr r3, [r3, #0] 80040b4: 22ca movs r2, #202 @ 0xca 80040b6: 625a str r2, [r3, #36] @ 0x24 80040b8: 4b57 ldr r3, [pc, #348] @ (8004218 ) 80040ba: 681b ldr r3, [r3, #0] 80040bc: 2253 movs r2, #83 @ 0x53 80040be: 625a str r2, [r3, #36] @ 0x24 /** * Disable the Wakeup Timer * This may speed up a bit the processing to wait the timer to be disabled * The timer is still counting 2 RTCCLK */ __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); 80040c0: 4b55 ldr r3, [pc, #340] @ (8004218 ) 80040c2: 681b ldr r3, [r3, #0] 80040c4: 689a ldr r2, [r3, #8] 80040c6: 4b54 ldr r3, [pc, #336] @ (8004218 ) 80040c8: 681b ldr r3, [r3, #0] 80040ca: f422 6280 bic.w r2, r2, #1024 @ 0x400 80040ce: 609a str r2, [r3, #8] local_current_running_timer_id = CurrentRunningTimerID; 80040d0: 4b52 ldr r3, [pc, #328] @ (800421c ) 80040d2: 781b ldrb r3, [r3, #0] 80040d4: f887 3023 strb.w r3, [r7, #35] @ 0x23 if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running) 80040d8: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 80040dc: 4950 ldr r1, [pc, #320] @ (8004220 ) 80040de: 4613 mov r3, r2 80040e0: 005b lsls r3, r3, #1 80040e2: 4413 add r3, r2 80040e4: 00db lsls r3, r3, #3 80040e6: 440b add r3, r1 80040e8: 330c adds r3, #12 80040ea: 781b ldrb r3, [r3, #0] 80040ec: b2db uxtb r3, r3 80040ee: 2b02 cmp r3, #2 80040f0: d16e bne.n 80041d0 { ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack; 80040f2: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 80040f6: 494a ldr r1, [pc, #296] @ (8004220 ) 80040f8: 4613 mov r3, r2 80040fa: 005b lsls r3, r3, #1 80040fc: 4413 add r3, r2 80040fe: 00db lsls r3, r3, #3 8004100: 440b add r3, r1 8004102: 681b ldr r3, [r3, #0] 8004104: 61fb str r3, [r7, #28] timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID; 8004106: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 800410a: 4945 ldr r1, [pc, #276] @ (8004220 ) 800410c: 4613 mov r3, r2 800410e: 005b lsls r3, r3, #1 8004110: 4413 add r3, r2 8004112: 00db lsls r3, r3, #3 8004114: 440b add r3, r1 8004116: 3310 adds r3, #16 8004118: 681b ldr r3, [r3, #0] 800411a: 61bb str r3, [r7, #24] * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick * to be left whereas the count is over * A more secure implementation has been done with a flag to state whereas the full count has been written * in the wakeuptimer or not */ if(WakeupTimerLimitation != WakeupTimerValue_Overpassed) 800411c: 4b41 ldr r3, [pc, #260] @ (8004224 ) 800411e: 781b ldrb r3, [r3, #0] 8004120: b2db uxtb r3, r3 8004122: 2b00 cmp r3, #0 8004124: d04c beq.n 80041c0 { if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated) 8004126: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 800412a: 493d ldr r1, [pc, #244] @ (8004220 ) 800412c: 4613 mov r3, r2 800412e: 005b lsls r3, r3, #1 8004130: 4413 add r3, r2 8004132: 00db lsls r3, r3, #3 8004134: 440b add r3, r1 8004136: 330d adds r3, #13 8004138: 781b ldrb r3, [r3, #0] 800413a: b2db uxtb r3, r3 800413c: 2b01 cmp r3, #1 800413e: d124 bne.n 800418a { UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested); 8004140: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 8004144: 2101 movs r1, #1 8004146: 4618 mov r0, r3 8004148: f7ff fdf2 bl 8003d30 800414c: 6a7b ldr r3, [r7, #36] @ 0x24 800414e: 613b str r3, [r7, #16] \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004150: 693b ldr r3, [r7, #16] 8004152: f383 8810 msr PRIMASK, r3 } 8004156: bf00 nop #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit); 8004158: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 800415c: 4930 ldr r1, [pc, #192] @ (8004220 ) 800415e: 4613 mov r3, r2 8004160: 005b lsls r3, r3, #1 8004162: 4413 add r3, r2 8004164: 00db lsls r3, r3, #3 8004166: 440b add r3, r1 8004168: 3304 adds r3, #4 800416a: 681a ldr r2, [r3, #0] 800416c: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 8004170: 4611 mov r1, r2 8004172: 4618 mov r0, r3 8004174: f000 f9b8 bl 80044e8 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 8004178: 4b27 ldr r3, [pc, #156] @ (8004218 ) 800417a: 681b ldr r3, [r3, #0] 800417c: 22ca movs r2, #202 @ 0xca 800417e: 625a str r2, [r3, #36] @ 0x24 8004180: 4b25 ldr r3, [pc, #148] @ (8004218 ) 8004182: 681b ldr r3, [r3, #0] 8004184: 2253 movs r2, #83 @ 0x53 8004186: 625a str r2, [r3, #36] @ 0x24 8004188: e012 b.n 80041b0 800418a: 6a7b ldr r3, [r7, #36] @ 0x24 800418c: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800418e: 68fb ldr r3, [r7, #12] 8004190: f383 8810 msr PRIMASK, r3 } 8004194: bf00 nop else { #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif HW_TS_Stop(local_current_running_timer_id); 8004196: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 800419a: 4618 mov r0, r3 800419c: f000 f920 bl 80043e0 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 80041a0: 4b1d ldr r3, [pc, #116] @ (8004218 ) 80041a2: 681b ldr r3, [r3, #0] 80041a4: 22ca movs r2, #202 @ 0xca 80041a6: 625a str r2, [r3, #36] @ 0x24 80041a8: 4b1b ldr r3, [pc, #108] @ (8004218 ) 80041aa: 681b ldr r3, [r3, #0] 80041ac: 2253 movs r2, #83 @ 0x53 80041ae: 625a str r2, [r3, #36] @ 0x24 } HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback); 80041b0: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 80041b4: 69fa ldr r2, [r7, #28] 80041b6: 4619 mov r1, r3 80041b8: 69b8 ldr r0, [r7, #24] 80041ba: f000 fa1b bl 80045f4 80041be: e022 b.n 8004206 } else { RescheduleTimerList(); 80041c0: f7ff fed2 bl 8003f68 80041c4: 6a7b ldr r3, [r7, #36] @ 0x24 80041c6: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80041c8: 68bb ldr r3, [r7, #8] 80041ca: f383 8810 msr PRIMASK, r3 } 80041ce: e01a b.n 8004206 /** * We should never end up in this case * However, if due to any bug in the timer server this is the case, the mistake may not impact the user. * We could just clean the interrupt flag and get out from this unexpected interrupt */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET); 80041d0: bf00 nop 80041d2: 4b11 ldr r3, [pc, #68] @ (8004218 ) 80041d4: 681b ldr r3, [r3, #0] 80041d6: 68db ldr r3, [r3, #12] 80041d8: f003 0304 and.w r3, r3, #4 80041dc: 2b00 cmp r3, #0 80041de: d0f8 beq.n 80041d2 * It takes 2 RTCCLK between the time the WUTE bit is disabled and the * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between * due to the autoreload feature */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ 80041e0: 4b0d ldr r3, [pc, #52] @ (8004218 ) 80041e2: 681b ldr r3, [r3, #0] 80041e4: 68db ldr r3, [r3, #12] 80041e6: b2da uxtb r2, r3 80041e8: 4b0b ldr r3, [pc, #44] @ (8004218 ) 80041ea: 681b ldr r3, [r3, #0] 80041ec: f462 6290 orn r2, r2, #1152 @ 0x480 80041f0: 60da str r2, [r3, #12] __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ 80041f2: 4b0d ldr r3, [pc, #52] @ (8004228 ) 80041f4: f44f 2200 mov.w r2, #524288 @ 0x80000 80041f8: 60da str r2, [r3, #12] 80041fa: 6a7b ldr r3, [r7, #36] @ 0x24 80041fc: 607b str r3, [r7, #4] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80041fe: 687b ldr r3, [r7, #4] 8004200: f383 8810 msr PRIMASK, r3 } 8004204: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); 8004206: 4b04 ldr r3, [pc, #16] @ (8004218 ) 8004208: 681b ldr r3, [r3, #0] 800420a: 22ff movs r2, #255 @ 0xff 800420c: 625a str r2, [r3, #36] @ 0x24 return; 800420e: bf00 nop } 8004210: 3728 adds r7, #40 @ 0x28 8004212: 46bd mov sp, r7 8004214: bd80 pop {r7, pc} 8004216: bf00 nop 8004218: 20000504 .word 0x20000504 800421c: 200003a4 .word 0x200003a4 8004220: 20000314 .word 0x20000314 8004224: 200003ac .word 0x200003ac 8004228: 58000800 .word 0x58000800 0800422c : void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *phrtc) { 800422c: b580 push {r7, lr} 800422e: b088 sub sp, #32 8004230: af00 add r7, sp, #0 8004232: 4603 mov r3, r0 8004234: 6039 str r1, [r7, #0] 8004236: 71fb strb r3, [r7, #7] uint8_t loop; uint32_t localmaxwakeuptimersetup; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 8004238: 4b5e ldr r3, [pc, #376] @ (80043b4 ) 800423a: 681b ldr r3, [r3, #0] 800423c: 22ca movs r2, #202 @ 0xca 800423e: 625a str r2, [r3, #36] @ 0x24 8004240: 4b5c ldr r3, [pc, #368] @ (80043b4 ) 8004242: 681b ldr r3, [r3, #0] 8004244: 2253 movs r2, #83 @ 0x53 8004246: 625a str r2, [r3, #36] @ 0x24 SET_BIT(RTC->CR, RTC_CR_BYPSHAD); 8004248: 4b5b ldr r3, [pc, #364] @ (80043b8 ) 800424a: 689b ldr r3, [r3, #8] 800424c: 4a5a ldr r2, [pc, #360] @ (80043b8 ) 800424e: f043 0320 orr.w r3, r3, #32 8004252: 6093 str r3, [r2, #8] /** * Readout the user config */ WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL)))); 8004254: 4b58 ldr r3, [pc, #352] @ (80043b8 ) 8004256: 689b ldr r3, [r3, #8] 8004258: b2db uxtb r3, r3 800425a: f003 0307 and.w r3, r3, #7 800425e: b2db uxtb r3, r3 8004260: f1c3 0304 rsb r3, r3, #4 8004264: b2da uxtb r2, r3 8004266: 4b55 ldr r3, [pc, #340] @ (80043bc ) 8004268: 701a strb r2, [r3, #0] AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1; 800426a: 4b53 ldr r3, [pc, #332] @ (80043b8 ) 800426c: 691b ldr r3, [r3, #16] 800426e: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 8004272: f44f 02fe mov.w r2, #8323072 @ 0x7f0000 8004276: 613a str r2, [r7, #16] uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004278: 693a ldr r2, [r7, #16] 800427a: fa92 f2a2 rbit r2, r2 800427e: 60fa str r2, [r7, #12] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8004280: 68fa ldr r2, [r7, #12] 8004282: 617a str r2, [r7, #20] optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8004284: 697a ldr r2, [r7, #20] 8004286: 2a00 cmp r2, #0 8004288: d101 bne.n 800428e { return 32U; 800428a: 2220 movs r2, #32 800428c: e003 b.n 8004296 } return __builtin_clz(value); 800428e: 697a ldr r2, [r7, #20] 8004290: fab2 f282 clz r2, r2 8004294: b2d2 uxtb r2, r2 8004296: 40d3 lsrs r3, r2 8004298: b2db uxtb r3, r3 800429a: 3301 adds r3, #1 800429c: b2da uxtb r2, r3 800429e: 4b48 ldr r3, [pc, #288] @ (80043c0 ) 80042a0: 701a strb r2, [r3, #0] SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1; 80042a2: 4b45 ldr r3, [pc, #276] @ (80043b8 ) 80042a4: 691b ldr r3, [r3, #16] 80042a6: b29b uxth r3, r3 80042a8: f3c3 030e ubfx r3, r3, #0, #15 80042ac: b29b uxth r3, r3 80042ae: 3301 adds r3, #1 80042b0: b29a uxth r2, r3 80042b2: 4b44 ldr r3, [pc, #272] @ (80043c4 ) 80042b4: 801a strh r2, [r3, #0] /** * Margin is taken to avoid wrong calculation when the wrap around is there and some * application interrupts may have delayed the reading */ localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider); 80042b6: 4b43 ldr r3, [pc, #268] @ (80043c4 ) 80042b8: 881b ldrh r3, [r3, #0] 80042ba: 3b01 subs r3, #1 80042bc: 4a40 ldr r2, [pc, #256] @ (80043c0 ) 80042be: 7812 ldrb r2, [r2, #0] 80042c0: fb02 f303 mul.w r3, r2, r3 80042c4: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 80042c8: 4a3c ldr r2, [pc, #240] @ (80043bc ) 80042ca: 7812 ldrb r2, [r2, #0] 80042cc: 40d3 lsrs r3, r2 80042ce: 61bb str r3, [r7, #24] if(localmaxwakeuptimersetup >= 0xFFFF) 80042d0: 69bb ldr r3, [r7, #24] 80042d2: f64f 72fe movw r2, #65534 @ 0xfffe 80042d6: 4293 cmp r3, r2 80042d8: d904 bls.n 80042e4 { MaxWakeupTimerSetup = 0xFFFF; 80042da: 4b3b ldr r3, [pc, #236] @ (80043c8 ) 80042dc: f64f 72ff movw r2, #65535 @ 0xffff 80042e0: 801a strh r2, [r3, #0] 80042e2: e003 b.n 80042ec } else { MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup; 80042e4: 69bb ldr r3, [r7, #24] 80042e6: b29a uxth r2, r3 80042e8: 4b37 ldr r3, [pc, #220] @ (80043c8 ) 80042ea: 801a strh r2, [r3, #0] } /** * Configure EXTI module */ LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); 80042ec: f44f 2000 mov.w r0, #524288 @ 0x80000 80042f0: f7ff fb9c bl 8003a2c LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); 80042f4: f44f 2000 mov.w r0, #524288 @ 0x80000 80042f8: f7ff fb84 bl 8003a04 if(TimerInitMode == hw_ts_InitMode_Full) 80042fc: 79fb ldrb r3, [r7, #7] 80042fe: 2b00 cmp r3, #0 8004300: d13d bne.n 800437e { WakeupTimerLimitation = WakeupTimerValue_LargeEnough; 8004302: 4b32 ldr r3, [pc, #200] @ (80043cc ) 8004304: 2201 movs r2, #1 8004306: 701a strb r2, [r3, #0] SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; 8004308: 4b31 ldr r3, [pc, #196] @ (80043d0 ) 800430a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800430e: 601a str r2, [r3, #0] /** * Initialize the timer server */ for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++) 8004310: 2300 movs r3, #0 8004312: 77fb strb r3, [r7, #31] 8004314: e00c b.n 8004330 { aTimerContext[loop].TimerIDStatus = TimerID_Free; 8004316: 7ffa ldrb r2, [r7, #31] 8004318: 492e ldr r1, [pc, #184] @ (80043d4 ) 800431a: 4613 mov r3, r2 800431c: 005b lsls r3, r3, #1 800431e: 4413 add r3, r2 8004320: 00db lsls r3, r3, #3 8004322: 440b add r3, r1 8004324: 330c adds r3, #12 8004326: 2200 movs r2, #0 8004328: 701a strb r2, [r3, #0] for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++) 800432a: 7ffb ldrb r3, [r7, #31] 800432c: 3301 adds r3, #1 800432e: 77fb strb r3, [r7, #31] 8004330: 7ffb ldrb r3, [r7, #31] 8004332: 2b05 cmp r3, #5 8004334: d9ef bls.n 8004316 } CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; /**< Set ID to non valid value */ 8004336: 4b28 ldr r3, [pc, #160] @ (80043d8 ) 8004338: 2206 movs r2, #6 800433a: 701a strb r2, [r3, #0] __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ 800433c: 4b1d ldr r3, [pc, #116] @ (80043b4 ) 800433e: 681b ldr r3, [r3, #0] 8004340: 689a ldr r2, [r3, #8] 8004342: 4b1c ldr r3, [pc, #112] @ (80043b4 ) 8004344: 681b ldr r3, [r3, #0] 8004346: f422 6280 bic.w r2, r2, #1024 @ 0x400 800434a: 609a str r2, [r3, #8] __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ 800434c: 4b19 ldr r3, [pc, #100] @ (80043b4 ) 800434e: 681b ldr r3, [r3, #0] 8004350: 68db ldr r3, [r3, #12] 8004352: b2da uxtb r2, r3 8004354: 4b17 ldr r3, [pc, #92] @ (80043b4 ) 8004356: 681b ldr r3, [r3, #0] 8004358: f462 6290 orn r2, r2, #1152 @ 0x480 800435c: 60da str r2, [r3, #12] __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ 800435e: 4b1f ldr r3, [pc, #124] @ (80043dc ) 8004360: f44f 2200 mov.w r2, #524288 @ 0x80000 8004364: 60da str r2, [r3, #12] HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ 8004366: 2003 movs r0, #3 8004368: f002 f9f6 bl 8006758 __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hrtc, RTC_IT_WUT); /**< Enable interrupt in RTC module */ 800436c: 4b11 ldr r3, [pc, #68] @ (80043b4 ) 800436e: 681b ldr r3, [r3, #0] 8004370: 689a ldr r2, [r3, #8] 8004372: 4b10 ldr r3, [pc, #64] @ (80043b4 ) 8004374: 681b ldr r3, [r3, #0] 8004376: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800437a: 609a str r2, [r3, #8] 800437c: e009 b.n 8004392 } else { if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTF) != RESET) 800437e: 4b0d ldr r3, [pc, #52] @ (80043b4 ) 8004380: 681b ldr r3, [r3, #0] 8004382: 68db ldr r3, [r3, #12] 8004384: f403 6380 and.w r3, r3, #1024 @ 0x400 8004388: 2b00 cmp r3, #0 800438a: d002 beq.n 8004392 { /** * Simulate that the Timer expired */ HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); 800438c: 2003 movs r0, #3 800438e: f002 f9d5 bl 800673c } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); 8004392: 4b08 ldr r3, [pc, #32] @ (80043b4 ) 8004394: 681b ldr r3, [r3, #0] 8004396: 22ff movs r2, #255 @ 0xff 8004398: 625a str r2, [r3, #36] @ 0x24 HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO); /**< Set NVIC priority */ 800439a: 2200 movs r2, #0 800439c: 2106 movs r1, #6 800439e: 2003 movs r0, #3 80043a0: f002 f996 bl 80066d0 HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ 80043a4: 2003 movs r0, #3 80043a6: f002 f9ad bl 8006704 return; 80043aa: bf00 nop } 80043ac: 3720 adds r7, #32 80043ae: 46bd mov sp, r7 80043b0: bd80 pop {r7, pc} 80043b2: bf00 nop 80043b4: 20000504 .word 0x20000504 80043b8: 40002800 .word 0x40002800 80043bc: 200003ad .word 0x200003ad 80043c0: 200003ae .word 0x200003ae 80043c4: 200003b0 .word 0x200003b0 80043c8: 200003b2 .word 0x200003b2 80043cc: 200003ac .word 0x200003ac 80043d0: 200003a8 .word 0x200003a8 80043d4: 20000314 .word 0x20000314 80043d8: 200003a4 .word 0x200003a4 80043dc: 58000800 .word 0x58000800 080043e0 : return; } void HW_TS_Stop(uint8_t timer_id) { 80043e0: b580 push {r7, lr} 80043e2: b086 sub sp, #24 80043e4: af00 add r7, sp, #0 80043e6: 4603 mov r3, r0 80043e8: 71fb strb r3, [r7, #7] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80043ea: f3ef 8310 mrs r3, PRIMASK 80043ee: 60fb str r3, [r7, #12] return(result); 80043f0: 68fb ldr r3, [r7, #12] #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) uint32_t primask_bit; #endif #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 80043f2: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 80043f4: b672 cpsid i } 80043f6: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ #endif HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */ 80043f8: 2003 movs r0, #3 80043fa: f002 f991 bl 8006720 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 80043fe: 4b34 ldr r3, [pc, #208] @ (80044d0 ) 8004400: 681b ldr r3, [r3, #0] 8004402: 22ca movs r2, #202 @ 0xca 8004404: 625a str r2, [r3, #36] @ 0x24 8004406: 4b32 ldr r3, [pc, #200] @ (80044d0 ) 8004408: 681b ldr r3, [r3, #0] 800440a: 2253 movs r2, #83 @ 0x53 800440c: 625a str r2, [r3, #36] @ 0x24 if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running) 800440e: 79fa ldrb r2, [r7, #7] 8004410: 4930 ldr r1, [pc, #192] @ (80044d4 ) 8004412: 4613 mov r3, r2 8004414: 005b lsls r3, r3, #1 8004416: 4413 add r3, r2 8004418: 00db lsls r3, r3, #3 800441a: 440b add r3, r1 800441c: 330c adds r3, #12 800441e: 781b ldrb r3, [r3, #0] 8004420: b2db uxtb r3, r3 8004422: 2b02 cmp r3, #2 8004424: d142 bne.n 80044ac { UnlinkTimer(timer_id, SSR_Read_Requested); 8004426: 79fb ldrb r3, [r7, #7] 8004428: 2100 movs r1, #0 800442a: 4618 mov r0, r3 800442c: f7ff fc80 bl 8003d30 localcurrentrunningtimerid = CurrentRunningTimerID; 8004430: 4b29 ldr r3, [pc, #164] @ (80044d8 ) 8004432: 781b ldrb r3, [r3, #0] 8004434: 74fb strb r3, [r7, #19] if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8004436: 7cfb ldrb r3, [r7, #19] 8004438: 2b06 cmp r3, #6 800443a: d12f bne.n 800449c */ /** * Disable the timer */ if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET) 800443c: 4b27 ldr r3, [pc, #156] @ (80044dc ) 800443e: 689b ldr r3, [r3, #8] 8004440: f403 6380 and.w r3, r3, #1024 @ 0x400 8004444: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004448: d107 bne.n 800445a { /** * Wait for the flag to be back to 0 when the wakeup timer is enabled */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET); 800444a: bf00 nop 800444c: 4b20 ldr r3, [pc, #128] @ (80044d0 ) 800444e: 681b ldr r3, [r3, #0] 8004450: 68db ldr r3, [r3, #12] 8004452: f003 0304 and.w r3, r3, #4 8004456: 2b00 cmp r3, #0 8004458: d1f8 bne.n 800444c } __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ 800445a: 4b1d ldr r3, [pc, #116] @ (80044d0 ) 800445c: 681b ldr r3, [r3, #0] 800445e: 689a ldr r2, [r3, #8] 8004460: 4b1b ldr r3, [pc, #108] @ (80044d0 ) 8004462: 681b ldr r3, [r3, #0] 8004464: f422 6280 bic.w r2, r2, #1024 @ 0x400 8004468: 609a str r2, [r3, #8] while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET); 800446a: bf00 nop 800446c: 4b18 ldr r3, [pc, #96] @ (80044d0 ) 800446e: 681b ldr r3, [r3, #0] 8004470: 68db ldr r3, [r3, #12] 8004472: f003 0304 and.w r3, r3, #4 8004476: 2b00 cmp r3, #0 8004478: d0f8 beq.n 800446c * It takes 2 RTCCLK between the time the WUTE bit is disabled and the * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between * due to the autoreload feature */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ 800447a: 4b15 ldr r3, [pc, #84] @ (80044d0 ) 800447c: 681b ldr r3, [r3, #0] 800447e: 68db ldr r3, [r3, #12] 8004480: b2da uxtb r2, r3 8004482: 4b13 ldr r3, [pc, #76] @ (80044d0 ) 8004484: 681b ldr r3, [r3, #0] 8004486: f462 6290 orn r2, r2, #1152 @ 0x480 800448a: 60da str r2, [r3, #12] __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ 800448c: 4b14 ldr r3, [pc, #80] @ (80044e0 ) 800448e: f44f 2200 mov.w r2, #524288 @ 0x80000 8004492: 60da str r2, [r3, #12] HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ 8004494: 2003 movs r0, #3 8004496: f002 f95f bl 8006758 800449a: e007 b.n 80044ac } else if(PreviousRunningTimerID != localcurrentrunningtimerid) 800449c: 4b11 ldr r3, [pc, #68] @ (80044e4 ) 800449e: 781b ldrb r3, [r3, #0] 80044a0: b2db uxtb r3, r3 80044a2: 7cfa ldrb r2, [r7, #19] 80044a4: 429a cmp r2, r3 80044a6: d001 beq.n 80044ac { RescheduleTimerList(); 80044a8: f7ff fd5e bl 8003f68 } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); 80044ac: 4b08 ldr r3, [pc, #32] @ (80044d0 ) 80044ae: 681b ldr r3, [r3, #0] 80044b0: 22ff movs r2, #255 @ 0xff 80044b2: 625a str r2, [r3, #36] @ 0x24 HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ 80044b4: 2003 movs r0, #3 80044b6: f002 f925 bl 8006704 80044ba: 697b ldr r3, [r7, #20] 80044bc: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80044be: 68bb ldr r3, [r7, #8] 80044c0: f383 8810 msr PRIMASK, r3 } 80044c4: bf00 nop #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif return; 80044c6: bf00 nop } 80044c8: 3718 adds r7, #24 80044ca: 46bd mov sp, r7 80044cc: bd80 pop {r7, pc} 80044ce: bf00 nop 80044d0: 20000504 .word 0x20000504 80044d4: 20000314 .word 0x20000314 80044d8: 200003a4 .word 0x200003a4 80044dc: 40002800 .word 0x40002800 80044e0: 58000800 .word 0x58000800 80044e4: 200003a5 .word 0x200003a5 080044e8 : void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks) { 80044e8: b580 push {r7, lr} 80044ea: b086 sub sp, #24 80044ec: af00 add r7, sp, #0 80044ee: 4603 mov r3, r0 80044f0: 6039 str r1, [r7, #0] 80044f2: 71fb strb r3, [r7, #7] #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) uint32_t primask_bit; #endif if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running) 80044f4: 79fa ldrb r2, [r7, #7] 80044f6: 493b ldr r1, [pc, #236] @ (80045e4 ) 80044f8: 4613 mov r3, r2 80044fa: 005b lsls r3, r3, #1 80044fc: 4413 add r3, r2 80044fe: 00db lsls r3, r3, #3 8004500: 440b add r3, r1 8004502: 330c adds r3, #12 8004504: 781b ldrb r3, [r3, #0] 8004506: b2db uxtb r3, r3 8004508: 2b02 cmp r3, #2 800450a: d103 bne.n 8004514 { HW_TS_Stop( timer_id ); 800450c: 79fb ldrb r3, [r7, #7] 800450e: 4618 mov r0, r3 8004510: f7ff ff66 bl 80043e0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004514: f3ef 8310 mrs r3, PRIMASK 8004518: 60fb str r3, [r7, #12] return(result); 800451a: 68fb ldr r3, [r7, #12] } #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 800451c: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800451e: b672 cpsid i } 8004520: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ #endif HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */ 8004522: 2003 movs r0, #3 8004524: f002 f8fc bl 8006720 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 8004528: 4b2f ldr r3, [pc, #188] @ (80045e8 ) 800452a: 681b ldr r3, [r3, #0] 800452c: 22ca movs r2, #202 @ 0xca 800452e: 625a str r2, [r3, #36] @ 0x24 8004530: 4b2d ldr r3, [pc, #180] @ (80045e8 ) 8004532: 681b ldr r3, [r3, #0] 8004534: 2253 movs r2, #83 @ 0x53 8004536: 625a str r2, [r3, #36] @ 0x24 aTimerContext[timer_id].TimerIDStatus = TimerID_Running; 8004538: 79fa ldrb r2, [r7, #7] 800453a: 492a ldr r1, [pc, #168] @ (80045e4 ) 800453c: 4613 mov r3, r2 800453e: 005b lsls r3, r3, #1 8004540: 4413 add r3, r2 8004542: 00db lsls r3, r3, #3 8004544: 440b add r3, r1 8004546: 330c adds r3, #12 8004548: 2202 movs r2, #2 800454a: 701a strb r2, [r3, #0] aTimerContext[timer_id].CountLeft = timeout_ticks; 800454c: 79fa ldrb r2, [r7, #7] 800454e: 4925 ldr r1, [pc, #148] @ (80045e4 ) 8004550: 4613 mov r3, r2 8004552: 005b lsls r3, r3, #1 8004554: 4413 add r3, r2 8004556: 00db lsls r3, r3, #3 8004558: 440b add r3, r1 800455a: 3308 adds r3, #8 800455c: 683a ldr r2, [r7, #0] 800455e: 601a str r2, [r3, #0] aTimerContext[timer_id].CounterInit = timeout_ticks; 8004560: 79fa ldrb r2, [r7, #7] 8004562: 4920 ldr r1, [pc, #128] @ (80045e4 ) 8004564: 4613 mov r3, r2 8004566: 005b lsls r3, r3, #1 8004568: 4413 add r3, r2 800456a: 00db lsls r3, r3, #3 800456c: 440b add r3, r1 800456e: 3304 adds r3, #4 8004570: 683a ldr r2, [r7, #0] 8004572: 601a str r2, [r3, #0] time_elapsed = linkTimer(timer_id); 8004574: 79fb ldrb r3, [r7, #7] 8004576: 4618 mov r0, r3 8004578: f7ff fb30 bl 8003bdc 800457c: 4603 mov r3, r0 800457e: 827b strh r3, [r7, #18] localcurrentrunningtimerid = CurrentRunningTimerID; 8004580: 4b1a ldr r3, [pc, #104] @ (80045ec ) 8004582: 781b ldrb r3, [r3, #0] 8004584: 747b strb r3, [r7, #17] if(PreviousRunningTimerID != localcurrentrunningtimerid) 8004586: 4b1a ldr r3, [pc, #104] @ (80045f0 ) 8004588: 781b ldrb r3, [r3, #0] 800458a: b2db uxtb r3, r3 800458c: 7c7a ldrb r2, [r7, #17] 800458e: 429a cmp r2, r3 8004590: d002 beq.n 8004598 { RescheduleTimerList(); 8004592: f7ff fce9 bl 8003f68 8004596: e013 b.n 80045c0 } else { aTimerContext[timer_id].CountLeft -= time_elapsed; 8004598: 79fa ldrb r2, [r7, #7] 800459a: 4912 ldr r1, [pc, #72] @ (80045e4 ) 800459c: 4613 mov r3, r2 800459e: 005b lsls r3, r3, #1 80045a0: 4413 add r3, r2 80045a2: 00db lsls r3, r3, #3 80045a4: 440b add r3, r1 80045a6: 3308 adds r3, #8 80045a8: 6819 ldr r1, [r3, #0] 80045aa: 8a7b ldrh r3, [r7, #18] 80045ac: 79fa ldrb r2, [r7, #7] 80045ae: 1ac9 subs r1, r1, r3 80045b0: 480c ldr r0, [pc, #48] @ (80045e4 ) 80045b2: 4613 mov r3, r2 80045b4: 005b lsls r3, r3, #1 80045b6: 4413 add r3, r2 80045b8: 00db lsls r3, r3, #3 80045ba: 4403 add r3, r0 80045bc: 3308 adds r3, #8 80045be: 6019 str r1, [r3, #0] } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); 80045c0: 4b09 ldr r3, [pc, #36] @ (80045e8 ) 80045c2: 681b ldr r3, [r3, #0] 80045c4: 22ff movs r2, #255 @ 0xff 80045c6: 625a str r2, [r3, #36] @ 0x24 HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ 80045c8: 2003 movs r0, #3 80045ca: f002 f89b bl 8006704 80045ce: 697b ldr r3, [r7, #20] 80045d0: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80045d2: 68bb ldr r3, [r7, #8] 80045d4: f383 8810 msr PRIMASK, r3 } 80045d8: bf00 nop #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif return; 80045da: bf00 nop } 80045dc: 3718 adds r7, #24 80045de: 46bd mov sp, r7 80045e0: bd80 pop {r7, pc} 80045e2: bf00 nop 80045e4: 20000314 .word 0x20000314 80045e8: 20000504 .word 0x20000504 80045ec: 200003a4 .word 0x200003a4 80045f0: 200003a5 .word 0x200003a5 080045f4 : return (return_value); } __weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack) { 80045f4: b580 push {r7, lr} 80045f6: b084 sub sp, #16 80045f8: af00 add r7, sp, #0 80045fa: 60f8 str r0, [r7, #12] 80045fc: 460b mov r3, r1 80045fe: 607a str r2, [r7, #4] 8004600: 72fb strb r3, [r7, #11] pTimerCallBack(); 8004602: 687b ldr r3, [r7, #4] 8004604: 4798 blx r3 return; 8004606: bf00 nop } 8004608: 3710 adds r7, #16 800460a: 46bd mov sp, r7 800460c: bd80 pop {r7, pc} 0800460e : \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { 800460e: b480 push {r7} 8004610: b083 sub sp, #12 8004612: af00 add r7, sp, #0 8004614: 6078 str r0, [r7, #4] if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 8004616: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 800461a: f8d3 3e80 ldr.w r3, [r3, #3712] @ 0xe80 800461e: f003 0301 and.w r3, r3, #1 8004622: 2b00 cmp r3, #0 8004624: d013 beq.n 800464e ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 8004626: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 800462a: f8d3 3e00 ldr.w r3, [r3, #3584] @ 0xe00 800462e: f003 0301 and.w r3, r3, #1 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 8004632: 2b00 cmp r3, #0 8004634: d00b beq.n 800464e { while (ITM->PORT[0U].u32 == 0UL) 8004636: e000 b.n 800463a { __NOP(); 8004638: bf00 nop while (ITM->PORT[0U].u32 == 0UL) 800463a: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 800463e: 681b ldr r3, [r3, #0] 8004640: 2b00 cmp r3, #0 8004642: d0f9 beq.n 8004638 } ITM->PORT[0U].u8 = (uint8_t)ch; 8004644: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 8004648: 687a ldr r2, [r7, #4] 800464a: b2d2 uxtb r2, r2 800464c: 701a strb r2, [r3, #0] } return (ch); 800464e: 687b ldr r3, [r7, #4] } 8004650: 4618 mov r0, r3 8004652: 370c adds r7, #12 8004654: 46bd mov sp, r7 8004656: f85d 7b04 ldr.w r7, [sp], #4 800465a: 4770 bx lr 0800465c : { 800465c: b480 push {r7} 800465e: b083 sub sp, #12 8004660: af00 add r7, sp, #0 8004662: 6078 str r0, [r7, #4] MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); 8004664: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8004668: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800466c: f023 0218 bic.w r2, r3, #24 8004670: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8004674: 687b ldr r3, [r7, #4] 8004676: 4313 orrs r3, r2 8004678: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 800467c: bf00 nop 800467e: 370c adds r7, #12 8004680: 46bd mov sp, r7 8004682: f85d 7b04 ldr.w r7, [sp], #4 8004686: 4770 bx lr 08004688 : * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) { 8004688: b480 push {r7} 800468a: b085 sub sp, #20 800468c: af00 add r7, sp, #0 800468e: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, Periphs); 8004690: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8004694: 6c9a ldr r2, [r3, #72] @ 0x48 8004696: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800469a: 687b ldr r3, [r7, #4] 800469c: 4313 orrs r3, r2 800469e: 648b str r3, [r1, #72] @ 0x48 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 80046a0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80046a4: 6c9a ldr r2, [r3, #72] @ 0x48 80046a6: 687b ldr r3, [r7, #4] 80046a8: 4013 ands r3, r2 80046aa: 60fb str r3, [r7, #12] (void)tmpreg; 80046ac: 68fb ldr r3, [r7, #12] } 80046ae: bf00 nop 80046b0: 3714 adds r7, #20 80046b2: 46bd mov sp, r7 80046b4: f85d 7b04 ldr.w r7, [sp], #4 80046b8: 4770 bx lr 080046ba : * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) { 80046ba: b480 push {r7} 80046bc: b085 sub sp, #20 80046be: af00 add r7, sp, #0 80046c0: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, Periphs); 80046c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80046c6: 6cda ldr r2, [r3, #76] @ 0x4c 80046c8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80046cc: 687b ldr r3, [r7, #4] 80046ce: 4313 orrs r3, r2 80046d0: 64cb str r3, [r1, #76] @ 0x4c /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 80046d2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80046d6: 6cda ldr r2, [r3, #76] @ 0x4c 80046d8: 687b ldr r3, [r7, #4] 80046da: 4013 ands r3, r2 80046dc: 60fb str r3, [r7, #12] (void)tmpreg; 80046de: 68fb ldr r3, [r7, #12] } 80046e0: bf00 nop 80046e2: 3714 adds r7, #20 80046e4: 46bd mov sp, r7 80046e6: f85d 7b04 ldr.w r7, [sp], #4 80046ea: 4770 bx lr 080046ec : * @param HSEMx HSEM Instance. * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 1 lock fail, 0 lock successful or already locked by same core */ __STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { 80046ec: b480 push {r7} 80046ee: b083 sub sp, #12 80046f0: af00 add r7, sp, #0 80046f2: 6078 str r0, [r7, #4] 80046f4: 6039 str r1, [r7, #0] return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); 80046f6: 687b ldr r3, [r7, #4] 80046f8: 683a ldr r2, [r7, #0] 80046fa: 3220 adds r2, #32 80046fc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8004700: 4a05 ldr r2, [pc, #20] @ (8004718 ) 8004702: 4293 cmp r3, r2 8004704: d001 beq.n 800470a 8004706: 2301 movs r3, #1 8004708: e000 b.n 800470c 800470a: 2300 movs r3, #0 } 800470c: 4618 mov r0, r3 800470e: 370c adds r7, #12 8004710: 46bd mov sp, r7 8004712: f85d 7b04 ldr.w r7, [sp], #4 8004716: 4770 bx lr 8004718: 80000400 .word 0x80000400 0800471c <_write>: /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ // implementation of printf() functionality through ITM int _write(int file, char *prt, int len) { 800471c: b580 push {r7, lr} 800471e: b086 sub sp, #24 8004720: af00 add r7, sp, #0 8004722: 60f8 str r0, [r7, #12] 8004724: 60b9 str r1, [r7, #8] 8004726: 607a str r2, [r7, #4] for (int i = 0; i < len; i++) { 8004728: 2300 movs r3, #0 800472a: 617b str r3, [r7, #20] 800472c: e009 b.n 8004742 <_write+0x26> ITM_SendChar(*prt++); 800472e: 68bb ldr r3, [r7, #8] 8004730: 1c5a adds r2, r3, #1 8004732: 60ba str r2, [r7, #8] 8004734: 781b ldrb r3, [r3, #0] 8004736: 4618 mov r0, r3 8004738: f7ff ff69 bl 800460e for (int i = 0; i < len; i++) { 800473c: 697b ldr r3, [r7, #20] 800473e: 3301 adds r3, #1 8004740: 617b str r3, [r7, #20] 8004742: 697a ldr r2, [r7, #20] 8004744: 687b ldr r3, [r7, #4] 8004746: 429a cmp r2, r3 8004748: dbf1 blt.n 800472e <_write+0x12> } return len; 800474a: 687b ldr r3, [r7, #4] } 800474c: 4618 mov r0, r3 800474e: 3718 adds r7, #24 8004750: 46bd mov sp, r7 8004752: bd80 pop {r7, pc} 08004754
: /** * @brief The application entry point. * @retval int */ int main(void) { 8004754: b580 push {r7, lr} 8004756: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8004758: f001 fe56 bl 8006408 /* Config code for STM32_WPAN (HSE Tuning must be done before system clock configuration) */ MX_APPE_Config(); 800475c: f7fd fd7e bl 800225c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8004760: f000 f86a bl 8004838 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 8004764: f000 f8de bl 8004924 /* IPCC initialisation */ MX_IPCC_Init(); 8004768: f000 f93c bl 80049e4 /* USER CODE BEGIN SysInit */ // Initialize DWT for the BMM350 delay function to work properly bmm_init_DWT(); 800476c: f001 f82e bl 80057cc /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8004770: f000 fa9e bl 8004cb0 MX_DMA_Init(); 8004774: f000 fa72 bl 8004c5c MX_I2C1_Init(); 8004778: f000 f8f4 bl 8004964 MX_SPI1_Init(); 800477c: f000 f982 bl 8004a84 MX_SPI2_Init(); 8004780: f000 f9be bl 8004b00 MX_TIM2_Init(); 8004784: f000 f9fa bl 8004b7c MX_RTC_Init(); 8004788: f000 f948 bl 8004a1c MX_RF_Init(); 800478c: f000 f93e bl 8004a0c /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 8004790: f00e fba2 bl 8012ed8 /* start timers, add new ones, ... */ /* USER CODE END RTOS_TIMERS */ /* Create the queue(s) */ /* creation of Q_ICM */ Q_ICMHandle = osMessageQueueNew (1, sizeof(ICM45686_Data), &Q_ICM_attributes); 8004794: 4a1a ldr r2, [pc, #104] @ (8004800 ) 8004796: 211c movs r1, #28 8004798: 2001 movs r0, #1 800479a: f00e ffa3 bl 80136e4 800479e: 4603 mov r3, r0 80047a0: 4a18 ldr r2, [pc, #96] @ (8004804 ) 80047a2: 6013 str r3, [r2, #0] /* creation of Q_BMM */ Q_BMMHandle = osMessageQueueNew (1, sizeof(struct bmm350_mag_temp_data), &Q_BMM_attributes); 80047a4: 4a18 ldr r2, [pc, #96] @ (8004808 ) 80047a6: 2110 movs r1, #16 80047a8: 2001 movs r0, #1 80047aa: f00e ff9b bl 80136e4 80047ae: 4603 mov r3, r0 80047b0: 4a16 ldr r2, [pc, #88] @ (800480c ) 80047b2: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of Task_DataAnalys */ Task_DataAnalysHandle = osThreadNew(Start_DataAnalysis, NULL, &Task_DataAnalys_attributes); 80047b4: 4a16 ldr r2, [pc, #88] @ (8004810 ) 80047b6: 2100 movs r1, #0 80047b8: 4816 ldr r0, [pc, #88] @ (8004814 ) 80047ba: f00e fbdd bl 8012f78 80047be: 4603 mov r3, r0 80047c0: 4a15 ldr r2, [pc, #84] @ (8004818 ) 80047c2: 6013 str r3, [r2, #0] /* creation of Task_ICM45686 */ Task_ICM45686Handle = osThreadNew(Start_ICM45686, NULL, &Task_ICM45686_attributes); 80047c4: 4a15 ldr r2, [pc, #84] @ (800481c ) 80047c6: 2100 movs r1, #0 80047c8: 4815 ldr r0, [pc, #84] @ (8004820 ) 80047ca: f00e fbd5 bl 8012f78 80047ce: 4603 mov r3, r0 80047d0: 4a14 ldr r2, [pc, #80] @ (8004824 ) 80047d2: 6013 str r3, [r2, #0] /* creation of Task_BMM350 */ Task_BMM350Handle = osThreadNew(Start_BMM350, NULL, &Task_BMM350_attributes); 80047d4: 4a14 ldr r2, [pc, #80] @ (8004828 ) 80047d6: 2100 movs r1, #0 80047d8: 4814 ldr r0, [pc, #80] @ (800482c ) 80047da: f00e fbcd bl 8012f78 80047de: 4603 mov r3, r0 80047e0: 4a13 ldr r2, [pc, #76] @ (8004830 ) 80047e2: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ while(LL_HSEM_1StepLock(HSEM, CFG_HW_CLK48_CONFIG_SEMID)); 80047e4: bf00 nop 80047e6: 2105 movs r1, #5 80047e8: 4812 ldr r0, [pc, #72] @ (8004834 ) 80047ea: f7ff ff7f bl 80046ec 80047ee: 4603 mov r3, r0 80047f0: 2b00 cmp r3, #0 80047f2: d1f8 bne.n 80047e6 /* Init code for STM32_WPAN */ MX_APPE_Init(); 80047f4: f7fd fd40 bl 8002278 /* Start scheduler */ osKernelStart(); 80047f8: f00e fb94 bl 8012f24 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 80047fc: bf00 nop 80047fe: e7fd b.n 80047fc 8004800: 0801dbdc .word 0x0801dbdc 8004804: 20000708 .word 0x20000708 8004808: 0801dbf4 .word 0x0801dbf4 800480c: 2000070c .word 0x2000070c 8004810: 0801db70 .word 0x0801db70 8004814: 08004d85 .word 0x08004d85 8004818: 200006fc .word 0x200006fc 800481c: 0801db94 .word 0x0801db94 8004820: 08004e59 .word 0x08004e59 8004824: 20000700 .word 0x20000700 8004828: 0801dbb8 .word 0x0801dbb8 800482c: 08005131 .word 0x08005131 8004830: 20000704 .word 0x20000704 8004834: 58001400 .word 0x58001400 08004838 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8004838: b580 push {r7, lr} 800483a: b09a sub sp, #104 @ 0x68 800483c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800483e: f107 0320 add.w r3, r7, #32 8004842: 2248 movs r2, #72 @ 0x48 8004844: 2100 movs r1, #0 8004846: 4618 mov r0, r3 8004848: f015 f964 bl 8019b14 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800484c: 1d3b adds r3, r7, #4 800484e: 2200 movs r2, #0 8004850: 601a str r2, [r3, #0] 8004852: 605a str r2, [r3, #4] 8004854: 609a str r2, [r3, #8] 8004856: 60da str r2, [r3, #12] 8004858: 611a str r2, [r3, #16] 800485a: 615a str r2, [r3, #20] 800485c: 619a str r2, [r3, #24] /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); 800485e: f006 f893 bl 800a988 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); 8004862: 2010 movs r0, #16 8004864: f7ff fefa bl 800465c /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8004868: 4b2d ldr r3, [pc, #180] @ (8004920 ) 800486a: 681b ldr r3, [r3, #0] 800486c: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8004870: 4a2b ldr r2, [pc, #172] @ (8004920 ) 8004872: f443 7300 orr.w r3, r3, #512 @ 0x200 8004876: 6013 str r3, [r2, #0] 8004878: 4b29 ldr r3, [pc, #164] @ (8004920 ) 800487a: 681b ldr r3, [r3, #0] 800487c: f403 63c0 and.w r3, r3, #1536 @ 0x600 8004880: 603b str r3, [r7, #0] 8004882: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI1 8004884: 232f movs r3, #47 @ 0x2f 8004886: 623b str r3, [r7, #32] |RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE |RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8004888: f44f 3380 mov.w r3, #65536 @ 0x10000 800488c: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800488e: 2301 movs r3, #1 8004890: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8004892: f44f 7380 mov.w r3, #256 @ 0x100 8004896: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.MSIState = RCC_MSI_ON; 8004898: 2301 movs r3, #1 800489a: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800489c: 2340 movs r3, #64 @ 0x40 800489e: 633b str r3, [r7, #48] @ 0x30 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; 80048a0: 2300 movs r3, #0 80048a2: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; 80048a4: 2360 movs r3, #96 @ 0x60 80048a6: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 80048a8: 2305 movs r3, #5 80048aa: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80048ac: 2302 movs r3, #2 80048ae: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; 80048b0: 2301 movs r3, #1 80048b2: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; 80048b4: 2300 movs r3, #0 80048b6: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLN = 32; 80048b8: 2320 movs r3, #32 80048ba: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 80048bc: f44f 3300 mov.w r3, #131072 @ 0x20000 80048c0: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 80048c2: f04f 5300 mov.w r3, #536870912 @ 0x20000000 80048c6: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 80048c8: f04f 7300 mov.w r3, #33554432 @ 0x2000000 80048cc: 663b str r3, [r7, #96] @ 0x60 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80048ce: f107 0320 add.w r3, r7, #32 80048d2: 4618 mov r0, r3 80048d4: f006 fc08 bl 800b0e8 80048d8: 4603 mov r3, r0 80048da: 2b00 cmp r3, #0 80048dc: d001 beq.n 80048e2 { Error_Handler(); 80048de: f000 fc9f bl 8005220 } /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2 80048e2: 236f movs r3, #111 @ 0x6f 80048e4: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80048e6: 2303 movs r3, #3 80048e8: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80048ea: 2300 movs r3, #0 80048ec: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80048ee: 2300 movs r3, #0 80048f0: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80048f2: 2300 movs r3, #0 80048f4: 617b str r3, [r7, #20] RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2; 80048f6: 2380 movs r3, #128 @ 0x80 80048f8: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; 80048fa: 2300 movs r3, #0 80048fc: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) 80048fe: 1d3b adds r3, r7, #4 8004900: 2103 movs r1, #3 8004902: 4618 mov r0, r3 8004904: f006 ff64 bl 800b7d0 8004908: 4603 mov r3, r0 800490a: 2b00 cmp r3, #0 800490c: d001 beq.n 8004912 { Error_Handler(); 800490e: f000 fc87 bl 8005220 } /** Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); 8004912: f007 fd3b bl 800c38c } 8004916: bf00 nop 8004918: 3768 adds r7, #104 @ 0x68 800491a: 46bd mov sp, r7 800491c: bd80 pop {r7, pc} 800491e: bf00 nop 8004920: 58000400 .word 0x58000400 08004924 : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 8004924: b580 push {r7, lr} 8004926: b094 sub sp, #80 @ 0x50 8004928: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 800492a: 463b mov r3, r7 800492c: 2250 movs r2, #80 @ 0x50 800492e: 2100 movs r1, #0 8004930: 4618 mov r0, r3 8004932: f015 f8ef bl 8019b14 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP; 8004936: f44f 5340 mov.w r3, #12288 @ 0x3000 800493a: 603b str r3, [r7, #0] PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_HSE_DIV1024; 800493c: f44f 4340 mov.w r3, #49152 @ 0xc000 8004940: 647b str r3, [r7, #68] @ 0x44 PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI; 8004942: 2300 movs r3, #0 8004944: 64bb str r3, [r7, #72] @ 0x48 PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1; 8004946: 2310 movs r3, #16 8004948: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800494a: 463b mov r3, r7 800494c: 4618 mov r0, r3 800494e: f007 fba7 bl 800c0a0 8004952: 4603 mov r3, r0 8004954: 2b00 cmp r3, #0 8004956: d001 beq.n 800495c { Error_Handler(); 8004958: f000 fc62 bl 8005220 } /* USER CODE BEGIN Smps */ /* USER CODE END Smps */ } 800495c: bf00 nop 800495e: 3750 adds r7, #80 @ 0x50 8004960: 46bd mov sp, r7 8004962: bd80 pop {r7, pc} 08004964 : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_Init(void) { 8004964: b580 push {r7, lr} 8004966: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8004968: 4b1b ldr r3, [pc, #108] @ (80049d8 ) 800496a: 4a1c ldr r2, [pc, #112] @ (80049dc ) 800496c: 601a str r2, [r3, #0] hi2c1.Init.Timing = 0x10B17DB5; 800496e: 4b1a ldr r3, [pc, #104] @ (80049d8 ) 8004970: 4a1b ldr r2, [pc, #108] @ (80049e0 ) 8004972: 605a str r2, [r3, #4] hi2c1.Init.OwnAddress1 = 0; 8004974: 4b18 ldr r3, [pc, #96] @ (80049d8 ) 8004976: 2200 movs r2, #0 8004978: 609a str r2, [r3, #8] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 800497a: 4b17 ldr r3, [pc, #92] @ (80049d8 ) 800497c: 2201 movs r2, #1 800497e: 60da str r2, [r3, #12] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8004980: 4b15 ldr r3, [pc, #84] @ (80049d8 ) 8004982: 2200 movs r2, #0 8004984: 611a str r2, [r3, #16] hi2c1.Init.OwnAddress2 = 0; 8004986: 4b14 ldr r3, [pc, #80] @ (80049d8 ) 8004988: 2200 movs r2, #0 800498a: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 800498c: 4b12 ldr r3, [pc, #72] @ (80049d8 ) 800498e: 2200 movs r2, #0 8004990: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8004992: 4b11 ldr r3, [pc, #68] @ (80049d8 ) 8004994: 2200 movs r2, #0 8004996: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8004998: 4b0f ldr r3, [pc, #60] @ (80049d8 ) 800499a: 2200 movs r2, #0 800499c: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 800499e: 480e ldr r0, [pc, #56] @ (80049d8 ) 80049a0: f002 fb8e bl 80070c0 80049a4: 4603 mov r3, r0 80049a6: 2b00 cmp r3, #0 80049a8: d001 beq.n 80049ae { Error_Handler(); 80049aa: f000 fc39 bl 8005220 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 80049ae: 2100 movs r1, #0 80049b0: 4809 ldr r0, [pc, #36] @ (80049d8 ) 80049b2: f004 f989 bl 8008cc8 80049b6: 4603 mov r3, r0 80049b8: 2b00 cmp r3, #0 80049ba: d001 beq.n 80049c0 { Error_Handler(); 80049bc: f000 fc30 bl 8005220 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 80049c0: 2100 movs r1, #0 80049c2: 4805 ldr r0, [pc, #20] @ (80049d8 ) 80049c4: f004 f9cb bl 8008d5e 80049c8: 4603 mov r3, r0 80049ca: 2b00 cmp r3, #0 80049cc: d001 beq.n 80049d2 { Error_Handler(); 80049ce: f000 fc27 bl 8005220 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 80049d2: bf00 nop 80049d4: bd80 pop {r7, pc} 80049d6: bf00 nop 80049d8: 200003b4 .word 0x200003b4 80049dc: 40005400 .word 0x40005400 80049e0: 10b17db5 .word 0x10b17db5 080049e4 : * @brief IPCC Initialization Function * @param None * @retval None */ static void MX_IPCC_Init(void) { 80049e4: b580 push {r7, lr} 80049e6: af00 add r7, sp, #0 /* USER CODE END IPCC_Init 0 */ /* USER CODE BEGIN IPCC_Init 1 */ /* USER CODE END IPCC_Init 1 */ hipcc.Instance = IPCC; 80049e8: 4b06 ldr r3, [pc, #24] @ (8004a04 ) 80049ea: 4a07 ldr r2, [pc, #28] @ (8004a08 ) 80049ec: 601a str r2, [r3, #0] if (HAL_IPCC_Init(&hipcc) != HAL_OK) 80049ee: 4805 ldr r0, [pc, #20] @ (8004a04 ) 80049f0: f004 fa02 bl 8008df8 80049f4: 4603 mov r3, r0 80049f6: 2b00 cmp r3, #0 80049f8: d001 beq.n 80049fe { Error_Handler(); 80049fa: f000 fc11 bl 8005220 } /* USER CODE BEGIN IPCC_Init 2 */ /* USER CODE END IPCC_Init 2 */ } 80049fe: bf00 nop 8004a00: bd80 pop {r7, pc} 8004a02: bf00 nop 8004a04: 200004c8 .word 0x200004c8 8004a08: 58000c00 .word 0x58000c00 08004a0c : * @brief RF Initialization Function * @param None * @retval None */ static void MX_RF_Init(void) { 8004a0c: b480 push {r7} 8004a0e: af00 add r7, sp, #0 /* USER CODE END RF_Init 1 */ /* USER CODE BEGIN RF_Init 2 */ /* USER CODE END RF_Init 2 */ } 8004a10: bf00 nop 8004a12: 46bd mov sp, r7 8004a14: f85d 7b04 ldr.w r7, [sp], #4 8004a18: 4770 bx lr ... 08004a1c : * @brief RTC Initialization Function * @param None * @retval None */ static void MX_RTC_Init(void) { 8004a1c: b580 push {r7, lr} 8004a1e: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 8004a20: 4b16 ldr r3, [pc, #88] @ (8004a7c ) 8004a22: 4a17 ldr r2, [pc, #92] @ (8004a80 ) 8004a24: 601a str r2, [r3, #0] hrtc.Init.HourFormat = RTC_HOURFORMAT_24; 8004a26: 4b15 ldr r3, [pc, #84] @ (8004a7c ) 8004a28: 2200 movs r2, #0 8004a2a: 605a str r2, [r3, #4] hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER; 8004a2c: 4b13 ldr r3, [pc, #76] @ (8004a7c ) 8004a2e: 220f movs r2, #15 8004a30: 609a str r2, [r3, #8] hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER; 8004a32: 4b12 ldr r3, [pc, #72] @ (8004a7c ) 8004a34: f647 72ff movw r2, #32767 @ 0x7fff 8004a38: 60da str r2, [r3, #12] hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; 8004a3a: 4b10 ldr r3, [pc, #64] @ (8004a7c ) 8004a3c: 2200 movs r2, #0 8004a3e: 611a str r2, [r3, #16] hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; 8004a40: 4b0e ldr r3, [pc, #56] @ (8004a7c ) 8004a42: 2200 movs r2, #0 8004a44: 619a str r2, [r3, #24] hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; 8004a46: 4b0d ldr r3, [pc, #52] @ (8004a7c ) 8004a48: 2200 movs r2, #0 8004a4a: 61da str r2, [r3, #28] hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; 8004a4c: 4b0b ldr r3, [pc, #44] @ (8004a7c ) 8004a4e: 2200 movs r2, #0 8004a50: 615a str r2, [r3, #20] if (HAL_RTC_Init(&hrtc) != HAL_OK) 8004a52: 480a ldr r0, [pc, #40] @ (8004a7c ) 8004a54: f007 fdb1 bl 800c5ba 8004a58: 4603 mov r3, r0 8004a5a: 2b00 cmp r3, #0 8004a5c: d001 beq.n 8004a62 { Error_Handler(); 8004a5e: f000 fbdf bl 8005220 } /** Enable the WakeUp */ if (HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 0, RTC_WAKEUPCLOCK_RTCCLK_DIV16) != HAL_OK) 8004a62: 2200 movs r2, #0 8004a64: 2100 movs r1, #0 8004a66: 4805 ldr r0, [pc, #20] @ (8004a7c ) 8004a68: f007 feb4 bl 800c7d4 8004a6c: 4603 mov r3, r0 8004a6e: 2b00 cmp r3, #0 8004a70: d001 beq.n 8004a76 { Error_Handler(); 8004a72: f000 fbd5 bl 8005220 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 8004a76: bf00 nop 8004a78: bd80 pop {r7, pc} 8004a7a: bf00 nop 8004a7c: 20000504 .word 0x20000504 8004a80: 40002800 .word 0x40002800 08004a84 : * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 8004a84: b580 push {r7, lr} 8004a86: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; 8004a88: 4b1b ldr r3, [pc, #108] @ (8004af8 ) 8004a8a: 4a1c ldr r2, [pc, #112] @ (8004afc ) 8004a8c: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 8004a8e: 4b1a ldr r3, [pc, #104] @ (8004af8 ) 8004a90: f44f 7282 mov.w r2, #260 @ 0x104 8004a94: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 8004a96: 4b18 ldr r3, [pc, #96] @ (8004af8 ) 8004a98: 2200 movs r2, #0 8004a9a: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 8004a9c: 4b16 ldr r3, [pc, #88] @ (8004af8 ) 8004a9e: f44f 62e0 mov.w r2, #1792 @ 0x700 8004aa2: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH; 8004aa4: 4b14 ldr r3, [pc, #80] @ (8004af8 ) 8004aa6: 2202 movs r2, #2 8004aa8: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_2EDGE; 8004aaa: 4b13 ldr r3, [pc, #76] @ (8004af8 ) 8004aac: 2201 movs r2, #1 8004aae: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_SOFT; 8004ab0: 4b11 ldr r3, [pc, #68] @ (8004af8 ) 8004ab2: f44f 7200 mov.w r2, #512 @ 0x200 8004ab6: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64; 8004ab8: 4b0f ldr r3, [pc, #60] @ (8004af8 ) 8004aba: 2228 movs r2, #40 @ 0x28 8004abc: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 8004abe: 4b0e ldr r3, [pc, #56] @ (8004af8 ) 8004ac0: 2200 movs r2, #0 8004ac2: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 8004ac4: 4b0c ldr r3, [pc, #48] @ (8004af8 ) 8004ac6: 2200 movs r2, #0 8004ac8: 625a str r2, [r3, #36] @ 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8004aca: 4b0b ldr r3, [pc, #44] @ (8004af8 ) 8004acc: 2200 movs r2, #0 8004ace: 629a str r2, [r3, #40] @ 0x28 hspi1.Init.CRCPolynomial = 7; 8004ad0: 4b09 ldr r3, [pc, #36] @ (8004af8 ) 8004ad2: 2207 movs r2, #7 8004ad4: 62da str r2, [r3, #44] @ 0x2c hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 8004ad6: 4b08 ldr r3, [pc, #32] @ (8004af8 ) 8004ad8: 2200 movs r2, #0 8004ada: 631a str r2, [r3, #48] @ 0x30 hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE; 8004adc: 4b06 ldr r3, [pc, #24] @ (8004af8 ) 8004ade: 2200 movs r2, #0 8004ae0: 635a str r2, [r3, #52] @ 0x34 if (HAL_SPI_Init(&hspi1) != HAL_OK) 8004ae2: 4805 ldr r0, [pc, #20] @ (8004af8 ) 8004ae4: f007 ff42 bl 800c96c 8004ae8: 4603 mov r3, r0 8004aea: 2b00 cmp r3, #0 8004aec: d001 beq.n 8004af2 { Error_Handler(); 8004aee: f000 fb97 bl 8005220 } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 8004af2: bf00 nop 8004af4: bd80 pop {r7, pc} 8004af6: bf00 nop 8004af8: 20000528 .word 0x20000528 8004afc: 40013000 .word 0x40013000 08004b00 : * @brief SPI2 Initialization Function * @param None * @retval None */ static void MX_SPI2_Init(void) { 8004b00: b580 push {r7, lr} 8004b02: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_Init 1 */ /* USER CODE END SPI2_Init 1 */ /* SPI2 parameter configuration*/ hspi2.Instance = SPI2; 8004b04: 4b1b ldr r3, [pc, #108] @ (8004b74 ) 8004b06: 4a1c ldr r2, [pc, #112] @ (8004b78 ) 8004b08: 601a str r2, [r3, #0] hspi2.Init.Mode = SPI_MODE_MASTER; 8004b0a: 4b1a ldr r3, [pc, #104] @ (8004b74 ) 8004b0c: f44f 7282 mov.w r2, #260 @ 0x104 8004b10: 605a str r2, [r3, #4] hspi2.Init.Direction = SPI_DIRECTION_2LINES; 8004b12: 4b18 ldr r3, [pc, #96] @ (8004b74 ) 8004b14: 2200 movs r2, #0 8004b16: 609a str r2, [r3, #8] hspi2.Init.DataSize = SPI_DATASIZE_4BIT; 8004b18: 4b16 ldr r3, [pc, #88] @ (8004b74 ) 8004b1a: f44f 7240 mov.w r2, #768 @ 0x300 8004b1e: 60da str r2, [r3, #12] hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 8004b20: 4b14 ldr r3, [pc, #80] @ (8004b74 ) 8004b22: 2200 movs r2, #0 8004b24: 611a str r2, [r3, #16] hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 8004b26: 4b13 ldr r3, [pc, #76] @ (8004b74 ) 8004b28: 2200 movs r2, #0 8004b2a: 615a str r2, [r3, #20] hspi2.Init.NSS = SPI_NSS_SOFT; 8004b2c: 4b11 ldr r3, [pc, #68] @ (8004b74 ) 8004b2e: f44f 7200 mov.w r2, #512 @ 0x200 8004b32: 619a str r2, [r3, #24] hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8004b34: 4b0f ldr r3, [pc, #60] @ (8004b74 ) 8004b36: 2200 movs r2, #0 8004b38: 61da str r2, [r3, #28] hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 8004b3a: 4b0e ldr r3, [pc, #56] @ (8004b74 ) 8004b3c: 2200 movs r2, #0 8004b3e: 621a str r2, [r3, #32] hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 8004b40: 4b0c ldr r3, [pc, #48] @ (8004b74 ) 8004b42: 2200 movs r2, #0 8004b44: 625a str r2, [r3, #36] @ 0x24 hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8004b46: 4b0b ldr r3, [pc, #44] @ (8004b74 ) 8004b48: 2200 movs r2, #0 8004b4a: 629a str r2, [r3, #40] @ 0x28 hspi2.Init.CRCPolynomial = 7; 8004b4c: 4b09 ldr r3, [pc, #36] @ (8004b74 ) 8004b4e: 2207 movs r2, #7 8004b50: 62da str r2, [r3, #44] @ 0x2c hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 8004b52: 4b08 ldr r3, [pc, #32] @ (8004b74 ) 8004b54: 2200 movs r2, #0 8004b56: 631a str r2, [r3, #48] @ 0x30 hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 8004b58: 4b06 ldr r3, [pc, #24] @ (8004b74 ) 8004b5a: 2208 movs r2, #8 8004b5c: 635a str r2, [r3, #52] @ 0x34 if (HAL_SPI_Init(&hspi2) != HAL_OK) 8004b5e: 4805 ldr r0, [pc, #20] @ (8004b74 ) 8004b60: f007 ff04 bl 800c96c 8004b64: 4603 mov r3, r0 8004b66: 2b00 cmp r3, #0 8004b68: d001 beq.n 8004b6e { Error_Handler(); 8004b6a: f000 fb59 bl 8005220 } /* USER CODE BEGIN SPI2_Init 2 */ /* USER CODE END SPI2_Init 2 */ } 8004b6e: bf00 nop 8004b70: bd80 pop {r7, pc} 8004b72: bf00 nop 8004b74: 2000058c .word 0x2000058c 8004b78: 40003800 .word 0x40003800 08004b7c : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 8004b7c: b580 push {r7, lr} 8004b7e: b08a sub sp, #40 @ 0x28 8004b80: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8004b82: f107 031c add.w r3, r7, #28 8004b86: 2200 movs r2, #0 8004b88: 601a str r2, [r3, #0] 8004b8a: 605a str r2, [r3, #4] 8004b8c: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8004b8e: 463b mov r3, r7 8004b90: 2200 movs r2, #0 8004b92: 601a str r2, [r3, #0] 8004b94: 605a str r2, [r3, #4] 8004b96: 609a str r2, [r3, #8] 8004b98: 60da str r2, [r3, #12] 8004b9a: 611a str r2, [r3, #16] 8004b9c: 615a str r2, [r3, #20] 8004b9e: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8004ba0: 4b2d ldr r3, [pc, #180] @ (8004c58 ) 8004ba2: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8004ba6: 601a str r2, [r3, #0] htim2.Init.Prescaler = 63; 8004ba8: 4b2b ldr r3, [pc, #172] @ (8004c58 ) 8004baa: 223f movs r2, #63 @ 0x3f 8004bac: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8004bae: 4b2a ldr r3, [pc, #168] @ (8004c58 ) 8004bb0: 2200 movs r2, #0 8004bb2: 609a str r2, [r3, #8] htim2.Init.Period = 999; 8004bb4: 4b28 ldr r3, [pc, #160] @ (8004c58 ) 8004bb6: f240 32e7 movw r2, #999 @ 0x3e7 8004bba: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8004bbc: 4b26 ldr r3, [pc, #152] @ (8004c58 ) 8004bbe: 2200 movs r2, #0 8004bc0: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8004bc2: 4b25 ldr r3, [pc, #148] @ (8004c58 ) 8004bc4: 2200 movs r2, #0 8004bc6: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 8004bc8: 4823 ldr r0, [pc, #140] @ (8004c58 ) 8004bca: f008 fff9 bl 800dbc0 8004bce: 4603 mov r3, r0 8004bd0: 2b00 cmp r3, #0 8004bd2: d001 beq.n 8004bd8 { Error_Handler(); 8004bd4: f000 fb24 bl 8005220 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8004bd8: 2300 movs r3, #0 8004bda: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8004bdc: 2300 movs r3, #0 8004bde: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8004be0: f107 031c add.w r3, r7, #28 8004be4: 4619 mov r1, r3 8004be6: 481c ldr r0, [pc, #112] @ (8004c58 ) 8004be8: f009 fd72 bl 800e6d0 8004bec: 4603 mov r3, r0 8004bee: 2b00 cmp r3, #0 8004bf0: d001 beq.n 8004bf6 { Error_Handler(); 8004bf2: f000 fb15 bl 8005220 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8004bf6: 2360 movs r3, #96 @ 0x60 8004bf8: 603b str r3, [r7, #0] sConfigOC.Pulse = 0; 8004bfa: 2300 movs r3, #0 8004bfc: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8004bfe: 2300 movs r3, #0 8004c00: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8004c02: 2300 movs r3, #0 8004c04: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8004c06: 463b mov r3, r7 8004c08: 2200 movs r2, #0 8004c0a: 4619 mov r1, r3 8004c0c: 4812 ldr r0, [pc, #72] @ (8004c58 ) 8004c0e: f009 f935 bl 800de7c 8004c12: 4603 mov r3, r0 8004c14: 2b00 cmp r3, #0 8004c16: d001 beq.n 8004c1c { Error_Handler(); 8004c18: f000 fb02 bl 8005220 } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8004c1c: 463b mov r3, r7 8004c1e: 2204 movs r2, #4 8004c20: 4619 mov r1, r3 8004c22: 480d ldr r0, [pc, #52] @ (8004c58 ) 8004c24: f009 f92a bl 800de7c 8004c28: 4603 mov r3, r0 8004c2a: 2b00 cmp r3, #0 8004c2c: d001 beq.n 8004c32 { Error_Handler(); 8004c2e: f000 faf7 bl 8005220 } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8004c32: 463b mov r3, r7 8004c34: 2208 movs r2, #8 8004c36: 4619 mov r1, r3 8004c38: 4807 ldr r0, [pc, #28] @ (8004c58 ) 8004c3a: f009 f91f bl 800de7c 8004c3e: 4603 mov r3, r0 8004c40: 2b00 cmp r3, #0 8004c42: d001 beq.n 8004c48 { Error_Handler(); 8004c44: f000 faec bl 8005220 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 8004c48: 4803 ldr r0, [pc, #12] @ (8004c58 ) 8004c4a: f001 f967 bl 8005f1c } 8004c4e: bf00 nop 8004c50: 3728 adds r7, #40 @ 0x28 8004c52: 46bd mov sp, r7 8004c54: bd80 pop {r7, pc} 8004c56: bf00 nop 8004c58: 200006b0 .word 0x200006b0 08004c5c : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8004c5c: b580 push {r7, lr} 8004c5e: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); 8004c60: 2004 movs r0, #4 8004c62: f7ff fd11 bl 8004688 __HAL_RCC_DMA1_CLK_ENABLE(); 8004c66: 2001 movs r0, #1 8004c68: f7ff fd0e bl 8004688 /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0); 8004c6c: 2200 movs r2, #0 8004c6e: 2105 movs r1, #5 8004c70: 200b movs r0, #11 8004c72: f001 fd2d bl 80066d0 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8004c76: 200b movs r0, #11 8004c78: f001 fd44 bl 8006704 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 5, 0); 8004c7c: 2200 movs r2, #0 8004c7e: 2105 movs r1, #5 8004c80: 200c movs r0, #12 8004c82: f001 fd25 bl 80066d0 HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 8004c86: 200c movs r0, #12 8004c88: f001 fd3c bl 8006704 /* DMA1_Channel3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 5, 0); 8004c8c: 2200 movs r2, #0 8004c8e: 2105 movs r1, #5 8004c90: 200d movs r0, #13 8004c92: f001 fd1d bl 80066d0 HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); 8004c96: 200d movs r0, #13 8004c98: f001 fd34 bl 8006704 /* DMA1_Channel4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 5, 0); 8004c9c: 2200 movs r2, #0 8004c9e: 2105 movs r1, #5 8004ca0: 200e movs r0, #14 8004ca2: f001 fd15 bl 80066d0 HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn); 8004ca6: 200e movs r0, #14 8004ca8: f001 fd2c bl 8006704 } 8004cac: bf00 nop 8004cae: bd80 pop {r7, pc} 08004cb0 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8004cb0: b580 push {r7, lr} 8004cb2: b086 sub sp, #24 8004cb4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004cb6: 1d3b adds r3, r7, #4 8004cb8: 2200 movs r2, #0 8004cba: 601a str r2, [r3, #0] 8004cbc: 605a str r2, [r3, #4] 8004cbe: 609a str r2, [r3, #8] 8004cc0: 60da str r2, [r3, #12] 8004cc2: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8004cc4: 2004 movs r0, #4 8004cc6: f7ff fcf8 bl 80046ba __HAL_RCC_GPIOB_CLK_ENABLE(); 8004cca: 2002 movs r0, #2 8004ccc: f7ff fcf5 bl 80046ba __HAL_RCC_GPIOA_CLK_ENABLE(); 8004cd0: 2001 movs r0, #1 8004cd2: f7ff fcf2 bl 80046ba /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIO_SPI1_IMU_CS_GPIO_Port, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); 8004cd6: 2201 movs r2, #1 8004cd8: 2108 movs r1, #8 8004cda: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8004cde: f002 f99b bl 8007018 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_SPI2_SD_CD_Pin|GPIO_SPI2_SD_CS_Pin, GPIO_PIN_SET); 8004ce2: 2201 movs r2, #1 8004ce4: 2160 movs r1, #96 @ 0x60 8004ce6: 4826 ldr r0, [pc, #152] @ (8004d80 ) 8004ce8: f002 f996 bl 8007018 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIO_SD_LDO_EN_GPIO_Port, GPIO_SD_LDO_EN_Pin, GPIO_PIN_RESET); 8004cec: 2200 movs r2, #0 8004cee: f44f 5180 mov.w r1, #4096 @ 0x1000 8004cf2: 4823 ldr r0, [pc, #140] @ (8004d80 ) 8004cf4: f002 f990 bl 8007018 /*Configure GPIO pin : GPIO_SPI1_IMU_CS_Pin */ GPIO_InitStruct.Pin = GPIO_SPI1_IMU_CS_Pin; 8004cf8: 2308 movs r3, #8 8004cfa: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8004cfc: 2301 movs r3, #1 8004cfe: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004d00: 2300 movs r3, #0 8004d02: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8004d04: 2303 movs r3, #3 8004d06: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIO_SPI1_IMU_CS_GPIO_Port, &GPIO_InitStruct); 8004d08: 1d3b adds r3, r7, #4 8004d0a: 4619 mov r1, r3 8004d0c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8004d10: f002 f812 bl 8006d38 /*Configure GPIO pins : GPIO_SPI2_SD_CD_Pin GPIO_SPI2_SD_CS_Pin GPIO_SD_LDO_EN_Pin */ GPIO_InitStruct.Pin = GPIO_SPI2_SD_CD_Pin|GPIO_SPI2_SD_CS_Pin|GPIO_SD_LDO_EN_Pin; 8004d14: f44f 5383 mov.w r3, #4192 @ 0x1060 8004d18: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8004d1a: 2301 movs r3, #1 8004d1c: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004d1e: 2300 movs r3, #0 8004d20: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8004d22: 2303 movs r3, #3 8004d24: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8004d26: 1d3b adds r3, r7, #4 8004d28: 4619 mov r1, r3 8004d2a: 4815 ldr r0, [pc, #84] @ (8004d80 ) 8004d2c: f002 f804 bl 8006d38 /*Configure GPIO pin : GPIO_IMU_INT_Pin */ GPIO_InitStruct.Pin = GPIO_IMU_INT_Pin; 8004d30: f44f 6380 mov.w r3, #1024 @ 0x400 8004d34: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8004d36: f44f 1388 mov.w r3, #1114112 @ 0x110000 8004d3a: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004d3c: 2300 movs r3, #0 8004d3e: 60fb str r3, [r7, #12] HAL_GPIO_Init(GPIO_IMU_INT_GPIO_Port, &GPIO_InitStruct); 8004d40: 1d3b adds r3, r7, #4 8004d42: 4619 mov r1, r3 8004d44: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8004d48: f001 fff6 bl 8006d38 /*Configure GPIO pin : GPIO_MAGN_INT_Pin */ GPIO_InitStruct.Pin = GPIO_MAGN_INT_Pin; 8004d4c: f44f 6300 mov.w r3, #2048 @ 0x800 8004d50: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8004d52: f44f 1388 mov.w r3, #1114112 @ 0x110000 8004d56: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004d58: 2300 movs r3, #0 8004d5a: 60fb str r3, [r7, #12] HAL_GPIO_Init(GPIO_MAGN_INT_GPIO_Port, &GPIO_InitStruct); 8004d5c: 1d3b adds r3, r7, #4 8004d5e: 4619 mov r1, r3 8004d60: 4807 ldr r0, [pc, #28] @ (8004d80 ) 8004d62: f001 ffe9 bl 8006d38 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 8004d66: 2200 movs r2, #0 8004d68: 2105 movs r1, #5 8004d6a: 2028 movs r0, #40 @ 0x28 8004d6c: f001 fcb0 bl 80066d0 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8004d70: 2028 movs r0, #40 @ 0x28 8004d72: f001 fcc7 bl 8006704 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8004d76: bf00 nop 8004d78: 3718 adds r7, #24 8004d7a: 46bd mov sp, r7 8004d7c: bd80 pop {r7, pc} 8004d7e: bf00 nop 8004d80: 48000800 .word 0x48000800 08004d84 : * @param argument: Not used * @retval None */ /* USER CODE END Header_Start_DataAnalysis */ void Start_DataAnalysis(void *argument) { 8004d84: b580 push {r7, lr} 8004d86: b0b2 sub sp, #200 @ 0xc8 8004d88: af00 add r7, sp, #0 8004d8a: 6078 str r0, [r7, #4] /* init code for USB_Device */ MX_USB_Device_Init(); 8004d8c: f013 f88c bl 8017ea8 char output_buffer[128]; ICM45686_Data imu_data; struct bmm350_mag_temp_data magn_data; // struct bmm350_raw_mag_data magn_data; QuaternionData Quat_Dat; Quat_Dat.StartByte = PACKET_START_BYTE; 8004d90: 23de movs r3, #222 @ 0xde 8004d92: 723b strb r3, [r7, #8] Quat_Dat.SensorAddress = BMM350_I2C_ADSEL_SET_LOW; 8004d94: 2314 movs r3, #20 8004d96: 727b strb r3, [r7, #9] Quat_Dat.EndByte = PACKET_END_BYTE; 8004d98: 23ad movs r3, #173 @ 0xad 8004d9a: 76bb strb r3, [r7, #26] MadgwickAHRS_init(&IMUQuat, 6400.0f, 0.15f); 8004d9c: eddf 0a29 vldr s1, [pc, #164] @ 8004e44 8004da0: ed9f 0a29 vldr s0, [pc, #164] @ 8004e48 8004da4: 4829 ldr r0, [pc, #164] @ (8004e4c ) 8004da6: f7fb ff7d bl 8000ca4 /* Infinite loop */ for(;;) { osMessageQueueGet(Q_BMMHandle, &magn_data, NULL, osWaitForever); 8004daa: 4b29 ldr r3, [pc, #164] @ (8004e50 ) 8004dac: 6818 ldr r0, [r3, #0] 8004dae: f107 011c add.w r1, r7, #28 8004db2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8004db6: 2200 movs r2, #0 8004db8: f00e fd64 bl 8013884 osMessageQueueGet(Q_ICMHandle, &imu_data, NULL, osWaitForever); 8004dbc: 4b25 ldr r3, [pc, #148] @ (8004e54 ) 8004dbe: 6818 ldr r0, [r3, #0] 8004dc0: f107 012c add.w r1, r7, #44 @ 0x2c 8004dc4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8004dc8: 2200 movs r2, #0 8004dca: f00e fd5b bl 8013884 MadgwickAHRS_update(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz 8004dce: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8004dd2: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8004dd6: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8004dda: ed97 6a0b vldr s12, [r7, #44] @ 0x2c 8004dde: edd7 5a0c vldr s11, [r7, #48] @ 0x30 8004de2: ed97 5a0d vldr s10, [r7, #52] @ 0x34 8004de6: edd7 4a07 vldr s9, [r7, #28] 8004dea: edd7 3a08 vldr s7, [r7, #32] 8004dee: ed97 4a09 vldr s8, [r7, #36] @ 0x24 8004df2: eeb0 3a64 vmov.f32 s6, s9 8004df6: eef0 2a45 vmov.f32 s5, s10 8004dfa: eeb0 2a65 vmov.f32 s4, s11 8004dfe: eef0 1a46 vmov.f32 s3, s12 8004e02: eeb0 1a66 vmov.f32 s2, s13 8004e06: eef0 0a47 vmov.f32 s1, s14 8004e0a: eeb0 0a67 vmov.f32 s0, s15 8004e0e: 480f ldr r0, [pc, #60] @ (8004e4c ) 8004e10: f7fb ff6c bl 8000cec // // MadgwickAHRS_update_IMU(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz // imu_data.processed_imu_data[0], imu_data.processed_imu_data[1], imu_data.processed_imu_data[2]); // ax, ay, yz) Quat_Dat.qw = IMUQuat.q[0]; 8004e14: 4b0d ldr r3, [pc, #52] @ (8004e4c ) 8004e16: 681b ldr r3, [r3, #0] 8004e18: f8c7 300a str.w r3, [r7, #10] Quat_Dat.qx = IMUQuat.q[1]; 8004e1c: 4b0b ldr r3, [pc, #44] @ (8004e4c ) 8004e1e: 685b ldr r3, [r3, #4] 8004e20: f8c7 300e str.w r3, [r7, #14] Quat_Dat.qy = IMUQuat.q[2]; 8004e24: 4b09 ldr r3, [pc, #36] @ (8004e4c ) 8004e26: 689b ldr r3, [r3, #8] 8004e28: f8c7 3012 str.w r3, [r7, #18] Quat_Dat.qz = IMUQuat.q[3]; 8004e2c: 4b07 ldr r3, [pc, #28] @ (8004e4c ) 8004e2e: 68db ldr r3, [r3, #12] 8004e30: f8c7 3016 str.w r3, [r7, #22] CDC_Transmit_FS((uint8_t*)&Quat_Dat, sizeof(Quat_Dat)); 8004e34: f107 0308 add.w r3, r7, #8 8004e38: 2113 movs r1, #19 8004e3a: 4618 mov r0, r3 8004e3c: f013 f8f2 bl 8018024 osMessageQueueGet(Q_BMMHandle, &magn_data, NULL, osWaitForever); 8004e40: bf00 nop 8004e42: e7b2 b.n 8004daa 8004e44: 3e19999a .word 0x3e19999a 8004e48: 45c80000 .word 0x45c80000 8004e4c: 20000710 .word 0x20000710 8004e50: 2000070c .word 0x2000070c 8004e54: 20000708 .word 0x20000708 08004e58 : * @param argument: Not used * @retval None */ /* USER CODE END Header_Start_ICM45686 */ void Start_ICM45686(void *argument) { 8004e58: b580 push {r7, lr} 8004e5a: b0a4 sub sp, #144 @ 0x90 8004e5c: af00 add r7, sp, #0 8004e5e: 6078 str r0, [r7, #4] /* USER CODE BEGIN Start_ICM45686 */ HAL_StatusTypeDef status; // char output_buffer[128]; xIMU_Task = osThreadGetId(); 8004e60: f00e f91c bl 801309c 8004e64: 4603 mov r3, r0 8004e66: 4aab ldr r2, [pc, #684] @ (8005114 ) 8004e68: 6013 str r3, [r2, #0] uint8_t raw_imu_data[15]; int16_t imu_sensor_data[7]; ICM45686_Data processed_data; ICM45686_HandleTypeDef imu; imu.hspi = &hspi1; 8004e6a: 4bab ldr r3, [pc, #684] @ (8005118 ) 8004e6c: 61fb str r3, [r7, #28] imu.GPIO_Port = GPIO_SPI1_IMU_CS_GPIO_Port; 8004e6e: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8004e72: 623b str r3, [r7, #32] imu.GPIO_Pin = GPIO_SPI1_IMU_CS_Pin; 8004e74: 2308 movs r3, #8 8004e76: 84bb strh r3, [r7, #36] @ 0x24 imu.acc_fs = ICM45686_ACC_FS_4G; 8004e78: 2330 movs r3, #48 @ 0x30 8004e7a: f887 3026 strb.w r3, [r7, #38] @ 0x26 imu.acc_ssf = ICM45686_ACC_SSF[ICM45686_ACC_FS_4G >> 4]; 8004e7e: f04f 438c mov.w r3, #1174405120 @ 0x46000000 8004e82: 62fb str r3, [r7, #44] @ 0x2c imu.gyro_fs = ICM45686_GYRO_FS_250DPS; 8004e84: 2340 movs r3, #64 @ 0x40 8004e86: f887 3027 strb.w r3, [r7, #39] @ 0x27 imu.gyro_ssf = ICM45686_GYRO_SSF[ICM45686_GYRO_FS_250DPS >> 4]; 8004e8a: 4ba4 ldr r3, [pc, #656] @ (800511c ) 8004e8c: 633b str r3, [r7, #48] @ 0x30 imu.odr = ICM45686_ODR_6_4kHz_LN ; 8004e8e: 2303 movs r3, #3 8004e90: f887 3028 strb.w r3, [r7, #40] @ 0x28 uint8_t tx[15] = {0x00}; 8004e94: f107 030c add.w r3, r7, #12 8004e98: 2200 movs r2, #0 8004e9a: 601a str r2, [r3, #0] 8004e9c: 605a str r2, [r3, #4] 8004e9e: 609a str r2, [r3, #8] 8004ea0: f8c3 200b str.w r2, [r3, #11] tx[0] = 0x00 | 0x80; 8004ea4: 2380 movs r3, #128 @ 0x80 8004ea6: 733b strb r3, [r7, #12] init_icm(&imu); 8004ea8: f107 031c add.w r3, r7, #28 8004eac: 4618 mov r0, r3 8004eae: f000 fb0b bl 80054c8 osDelay(50); 8004eb2: 2032 movs r0, #50 @ 0x32 8004eb4: f00e f9d7 bl 8013266 configure_interrupt_icm(&imu); 8004eb8: f107 031c add.w r3, r7, #28 8004ebc: 4618 mov r0, r3 8004ebe: f000 fc3f bl 8005740 enable_interrupt_icm(&imu); 8004ec2: f107 031c add.w r3, r7, #28 8004ec6: 4618 mov r0, r3 8004ec8: f000 fbf4 bl 80056b4 // osDelay(500); // calibrate_icm(&imu, 1000); /* Infinite loop */ for(;;) { ulTaskNotifyTake(pdFALSE, osWaitForever); 8004ecc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8004ed0: 2100 movs r1, #0 8004ed2: 2000 movs r0, #0 8004ed4: f011 f92e bl 8016134 status = read_icm_dma(&imu, tx, raw_imu_data, sizeof(tx)); 8004ed8: f107 0280 add.w r2, r7, #128 @ 0x80 8004edc: f107 010c add.w r1, r7, #12 8004ee0: f107 001c add.w r0, r7, #28 8004ee4: 230f movs r3, #15 8004ee6: f000 faac bl 8005442 8004eea: 4603 mov r3, r0 8004eec: f887 308f strb.w r3, [r7, #143] @ 0x8f if (status != HAL_OK) { 8004ef0: f897 308f ldrb.w r3, [r7, #143] @ 0x8f 8004ef4: 2b00 cmp r3, #0 8004ef6: d005 beq.n 8004f04 printf("Reading IMU sensordata failed: %d\n", status); 8004ef8: f897 308f ldrb.w r3, [r7, #143] @ 0x8f 8004efc: 4619 mov r1, r3 8004efe: 4888 ldr r0, [pc, #544] @ (8005120 ) 8004f00: f014 fca0 bl 8019844 } imu_sensor_data[0] = (int16_t)(raw_imu_data[1] << 8 | raw_imu_data[2]); // a_x 8004f04: f897 3081 ldrb.w r3, [r7, #129] @ 0x81 8004f08: b21b sxth r3, r3 8004f0a: 021b lsls r3, r3, #8 8004f0c: b21a sxth r2, r3 8004f0e: f897 3082 ldrb.w r3, [r7, #130] @ 0x82 8004f12: b21b sxth r3, r3 8004f14: 4313 orrs r3, r2 8004f16: b21b sxth r3, r3 8004f18: f8a7 3070 strh.w r3, [r7, #112] @ 0x70 imu_sensor_data[1] = (int16_t)(raw_imu_data[3] << 8 | raw_imu_data[4]); // a_y 8004f1c: f897 3083 ldrb.w r3, [r7, #131] @ 0x83 8004f20: b21b sxth r3, r3 8004f22: 021b lsls r3, r3, #8 8004f24: b21a sxth r2, r3 8004f26: f897 3084 ldrb.w r3, [r7, #132] @ 0x84 8004f2a: b21b sxth r3, r3 8004f2c: 4313 orrs r3, r2 8004f2e: b21b sxth r3, r3 8004f30: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 imu_sensor_data[2] = (int16_t)(raw_imu_data[5] << 8 | raw_imu_data[6]); // a_z 8004f34: f897 3085 ldrb.w r3, [r7, #133] @ 0x85 8004f38: b21b sxth r3, r3 8004f3a: 021b lsls r3, r3, #8 8004f3c: b21a sxth r2, r3 8004f3e: f897 3086 ldrb.w r3, [r7, #134] @ 0x86 8004f42: b21b sxth r3, r3 8004f44: 4313 orrs r3, r2 8004f46: b21b sxth r3, r3 8004f48: f8a7 3074 strh.w r3, [r7, #116] @ 0x74 imu_sensor_data[3] = (int16_t)(raw_imu_data[7] << 8 | raw_imu_data[8]); // g_x 8004f4c: f897 3087 ldrb.w r3, [r7, #135] @ 0x87 8004f50: b21b sxth r3, r3 8004f52: 021b lsls r3, r3, #8 8004f54: b21a sxth r2, r3 8004f56: f897 3088 ldrb.w r3, [r7, #136] @ 0x88 8004f5a: b21b sxth r3, r3 8004f5c: 4313 orrs r3, r2 8004f5e: b21b sxth r3, r3 8004f60: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 imu_sensor_data[4] = (int16_t)(raw_imu_data[9] << 8 | raw_imu_data[10]); // g_y 8004f64: f897 3089 ldrb.w r3, [r7, #137] @ 0x89 8004f68: b21b sxth r3, r3 8004f6a: 021b lsls r3, r3, #8 8004f6c: b21a sxth r2, r3 8004f6e: f897 308a ldrb.w r3, [r7, #138] @ 0x8a 8004f72: b21b sxth r3, r3 8004f74: 4313 orrs r3, r2 8004f76: b21b sxth r3, r3 8004f78: f8a7 3078 strh.w r3, [r7, #120] @ 0x78 imu_sensor_data[5] = (int16_t)(raw_imu_data[11] << 8 | raw_imu_data[12]); // g_z 8004f7c: f897 308b ldrb.w r3, [r7, #139] @ 0x8b 8004f80: b21b sxth r3, r3 8004f82: 021b lsls r3, r3, #8 8004f84: b21a sxth r2, r3 8004f86: f897 308c ldrb.w r3, [r7, #140] @ 0x8c 8004f8a: b21b sxth r3, r3 8004f8c: 4313 orrs r3, r2 8004f8e: b21b sxth r3, r3 8004f90: f8a7 307a strh.w r3, [r7, #122] @ 0x7a imu_sensor_data[6] = (int16_t)(raw_imu_data[13] << 8 | raw_imu_data[14]); // t 8004f94: f897 308d ldrb.w r3, [r7, #141] @ 0x8d 8004f98: b21b sxth r3, r3 8004f9a: 021b lsls r3, r3, #8 8004f9c: b21a sxth r2, r3 8004f9e: f897 308e ldrb.w r3, [r7, #142] @ 0x8e 8004fa2: b21b sxth r3, r3 8004fa4: 4313 orrs r3, r2 8004fa6: b21b sxth r3, r3 8004fa8: f8a7 307c strh.w r3, [r7, #124] @ 0x7c processed_data.processed_imu_data[0] = (float)imu_sensor_data[0] / (float)imu.acc_fs; 8004fac: f9b7 3070 ldrsh.w r3, [r7, #112] @ 0x70 8004fb0: ee07 3a90 vmov s15, r3 8004fb4: eef8 6ae7 vcvt.f32.s32 s13, s15 8004fb8: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8004fbc: ee07 3a90 vmov s15, r3 8004fc0: eeb8 7a67 vcvt.f32.u32 s14, s15 8004fc4: eec6 7a87 vdiv.f32 s15, s13, s14 8004fc8: edc7 7a15 vstr s15, [r7, #84] @ 0x54 processed_data.processed_imu_data[1] = (float)imu_sensor_data[1] / (float)imu.acc_fs; 8004fcc: f9b7 3072 ldrsh.w r3, [r7, #114] @ 0x72 8004fd0: ee07 3a90 vmov s15, r3 8004fd4: eef8 6ae7 vcvt.f32.s32 s13, s15 8004fd8: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8004fdc: ee07 3a90 vmov s15, r3 8004fe0: eeb8 7a67 vcvt.f32.u32 s14, s15 8004fe4: eec6 7a87 vdiv.f32 s15, s13, s14 8004fe8: edc7 7a16 vstr s15, [r7, #88] @ 0x58 processed_data.processed_imu_data[2] = (float)imu_sensor_data[2] / (float)imu.acc_fs; 8004fec: f9b7 3074 ldrsh.w r3, [r7, #116] @ 0x74 8004ff0: ee07 3a90 vmov s15, r3 8004ff4: eef8 6ae7 vcvt.f32.s32 s13, s15 8004ff8: f897 3026 ldrb.w r3, [r7, #38] @ 0x26 8004ffc: ee07 3a90 vmov s15, r3 8005000: eeb8 7a67 vcvt.f32.u32 s14, s15 8005004: eec6 7a87 vdiv.f32 s15, s13, s14 8005008: edc7 7a17 vstr s15, [r7, #92] @ 0x5c processed_data.processed_imu_data[3] = (float)imu_sensor_data[3] / (float)imu.gyro_ssf; 800500c: f9b7 3076 ldrsh.w r3, [r7, #118] @ 0x76 8005010: ee07 3a90 vmov s15, r3 8005014: eef8 6ae7 vcvt.f32.s32 s13, s15 8005018: ed97 7a0c vldr s14, [r7, #48] @ 0x30 800501c: eec6 7a87 vdiv.f32 s15, s13, s14 8005020: edc7 7a18 vstr s15, [r7, #96] @ 0x60 processed_data.processed_imu_data[4] = (float)imu_sensor_data[4] / (float)imu.gyro_ssf; 8005024: f9b7 3078 ldrsh.w r3, [r7, #120] @ 0x78 8005028: ee07 3a90 vmov s15, r3 800502c: eef8 6ae7 vcvt.f32.s32 s13, s15 8005030: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8005034: eec6 7a87 vdiv.f32 s15, s13, s14 8005038: edc7 7a19 vstr s15, [r7, #100] @ 0x64 processed_data.processed_imu_data[5] = (float)imu_sensor_data[5] / (float)imu.gyro_ssf; 800503c: f9b7 307a ldrsh.w r3, [r7, #122] @ 0x7a 8005040: ee07 3a90 vmov s15, r3 8005044: eef8 6ae7 vcvt.f32.s32 s13, s15 8005048: ed97 7a0c vldr s14, [r7, #48] @ 0x30 800504c: eec6 7a87 vdiv.f32 s15, s13, s14 8005050: edc7 7a1a vstr s15, [r7, #104] @ 0x68 processed_data.processed_imu_data[6] = (float)(imu_sensor_data[6] / 128.0 + 25.0); 8005054: f9b7 307c ldrsh.w r3, [r7, #124] @ 0x7c 8005058: 4618 mov r0, r3 800505a: f7fb fa3b bl 80004d4 <__aeabi_i2d> 800505e: f04f 0200 mov.w r2, #0 8005062: 4b30 ldr r3, [pc, #192] @ (8005124 ) 8005064: f7fb fbca bl 80007fc <__aeabi_ddiv> 8005068: 4602 mov r2, r0 800506a: 460b mov r3, r1 800506c: 4610 mov r0, r2 800506e: 4619 mov r1, r3 8005070: f04f 0200 mov.w r2, #0 8005074: 4b2c ldr r3, [pc, #176] @ (8005128 ) 8005076: f7fb f8e1 bl 800023c <__adddf3> 800507a: 4602 mov r2, r0 800507c: 460b mov r3, r1 800507e: 4610 mov r0, r2 8005080: 4619 mov r1, r3 8005082: f7fb fd89 bl 8000b98 <__aeabi_d2f> 8005086: 4603 mov r3, r0 8005088: 66fb str r3, [r7, #108] @ 0x6c if (imu.calibated) { 800508a: f897 3034 ldrb.w r3, [r7, #52] @ 0x34 800508e: 2b00 cmp r3, #0 8005090: d037 beq.n 8005102 processed_data.processed_imu_data[0] -= imu.imu_bias[0]; 8005092: ed97 7a15 vldr s14, [r7, #84] @ 0x54 8005096: edd7 7a0e vldr s15, [r7, #56] @ 0x38 800509a: ee77 7a67 vsub.f32 s15, s14, s15 800509e: edc7 7a15 vstr s15, [r7, #84] @ 0x54 processed_data.processed_imu_data[1] -= imu.imu_bias[1]; 80050a2: ed97 7a16 vldr s14, [r7, #88] @ 0x58 80050a6: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 80050aa: ee77 7a67 vsub.f32 s15, s14, s15 80050ae: edc7 7a16 vstr s15, [r7, #88] @ 0x58 processed_data.processed_imu_data[2] -= imu.imu_bias[2]; 80050b2: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 80050b6: edd7 7a10 vldr s15, [r7, #64] @ 0x40 80050ba: ee77 7a67 vsub.f32 s15, s14, s15 80050be: edc7 7a17 vstr s15, [r7, #92] @ 0x5c processed_data.processed_imu_data[3] -= imu.imu_bias[3]; 80050c2: ed97 7a18 vldr s14, [r7, #96] @ 0x60 80050c6: edd7 7a11 vldr s15, [r7, #68] @ 0x44 80050ca: ee77 7a67 vsub.f32 s15, s14, s15 80050ce: edc7 7a18 vstr s15, [r7, #96] @ 0x60 processed_data.processed_imu_data[4] -= imu.imu_bias[4]; 80050d2: ed97 7a19 vldr s14, [r7, #100] @ 0x64 80050d6: edd7 7a12 vldr s15, [r7, #72] @ 0x48 80050da: ee77 7a67 vsub.f32 s15, s14, s15 80050de: edc7 7a19 vstr s15, [r7, #100] @ 0x64 processed_data.processed_imu_data[5] -= imu.imu_bias[5]; 80050e2: ed97 7a1a vldr s14, [r7, #104] @ 0x68 80050e6: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 80050ea: ee77 7a67 vsub.f32 s15, s14, s15 80050ee: edc7 7a1a vstr s15, [r7, #104] @ 0x68 processed_data.processed_imu_data[6] -= imu.imu_bias[7]; 80050f2: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 80050f6: edd7 7a15 vldr s15, [r7, #84] @ 0x54 80050fa: ee77 7a67 vsub.f32 s15, s14, s15 80050fe: edc7 7a1b vstr s15, [r7, #108] @ 0x6c } osMessageQueuePut(Q_ICMHandle, &processed_data, 0, 5); 8005102: 4b0a ldr r3, [pc, #40] @ (800512c ) 8005104: 6818 ldr r0, [r3, #0] 8005106: f107 0154 add.w r1, r7, #84 @ 0x54 800510a: 2305 movs r3, #5 800510c: 2200 movs r2, #0 800510e: f00e fb5b bl 80137c8 ulTaskNotifyTake(pdFALSE, osWaitForever); 8005112: e6db b.n 8004ecc 8005114: 20000728 .word 0x20000728 8005118: 20000528 .word 0x20000528 800511c: 43030000 .word 0x43030000 8005120: 0801d4b8 .word 0x0801d4b8 8005124: 40600000 .word 0x40600000 8005128: 40390000 .word 0x40390000 800512c: 20000708 .word 0x20000708 08005130 : * @param argument: Not used * @retval None */ /* USER CODE END Header_Start_BMM350 */ void Start_BMM350(void *argument) { 8005130: b580 push {r7, lr} 8005132: b0b4 sub sp, #208 @ 0xd0 8005134: af00 add r7, sp, #0 8005136: 6078 str r0, [r7, #4] /* USER CODE BEGIN Start_BMM350 */ // HAL_StatusTypeDef status; // char output_buffer[128]; xMagn_Task = osThreadGetId(); 8005138: f00d ffb0 bl 801309c 800513c: 4603 mov r3, r0 800513e: 4a2a ldr r2, [pc, #168] @ (80051e8 ) 8005140: 6013 str r3, [r2, #0] // BMM struct bmm350_dev dev = {0x00}; 8005142: f107 031c add.w r3, r7, #28 8005146: 22b0 movs r2, #176 @ 0xb0 8005148: 2100 movs r1, #0 800514a: 4618 mov r0, r3 800514c: f014 fce2 bl 8019b14 int8_t rslt; struct bmm350_mag_temp_data mag_data; osDelay(500); 8005150: f44f 70fa mov.w r0, #500 @ 0x1f4 8005154: f00e f887 bl 8013266 // struct bmm350_raw_mag_data mag_data; // ODR: 200HZ, AVG: rslt = init_bmm(&dev); 8005158: f107 031c add.w r3, r7, #28 800515c: 4618 mov r0, r3 800515e: f000 fbd7 bl 8005910 8005162: 4603 mov r3, r0 8005164: f887 30cf strb.w r3, [r7, #207] @ 0xcf if (rslt != BMM350_OK) { 8005168: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 800516c: 2b00 cmp r3, #0 800516e: d00b beq.n 8005188 printf("BMM350 initialization failed: %d\n", rslt); 8005170: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 8005174: 4619 mov r1, r3 8005176: 481d ldr r0, [pc, #116] @ (80051ec ) 8005178: f014 fb64 bl 8019844 printf("Chip id: 0x%02X\n", dev.chip_id); 800517c: f897 3020 ldrb.w r3, [r7, #32] 8005180: 4619 mov r1, r3 8005182: 481b ldr r0, [pc, #108] @ (80051f0 ) 8005184: f014 fb5e bl 8019844 } rslt = bmm_configure_interrupt(&dev); 8005188: f107 031c add.w r3, r7, #28 800518c: 4618 mov r0, r3 800518e: f000 fc1d bl 80059cc 8005192: 4603 mov r3, r0 8005194: f887 30cf strb.w r3, [r7, #207] @ 0xcf if (rslt != BMM350_OK) { 8005198: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 800519c: 2b00 cmp r3, #0 800519e: d005 beq.n 80051ac printf("Configuring interrupt failed: %d\n", rslt); 80051a0: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 80051a4: 4619 mov r1, r3 80051a6: 4813 ldr r0, [pc, #76] @ (80051f4 ) 80051a8: f014 fb4c bl 8019844 // osDelay(200); /* Infinite loop */ for(;;) { // wait for the interrupt ulTaskNotifyTake(pdFALSE, osWaitForever); 80051ac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80051b0: 2100 movs r1, #0 80051b2: 2000 movs r0, #0 80051b4: f010 ffbe bl 8016134 // magnetometer rslt = bmm350_get_compensated_mag_xyz_temp_data(&mag_data, &dev); 80051b8: f107 021c add.w r2, r7, #28 80051bc: f107 030c add.w r3, r7, #12 80051c0: 4611 mov r1, r2 80051c2: 4618 mov r0, r3 80051c4: f7fd fdb3 bl 8002d2e 80051c8: 4603 mov r3, r0 80051ca: f887 30cf strb.w r3, [r7, #207] @ 0xcf // rslt = bmm350_read_uncomp_mag_temp_data(&mag_data, &dev); if (rslt == BMM350_OK) 80051ce: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 80051d2: 2b00 cmp r3, #0 80051d4: d1ea bne.n 80051ac { // sprintf(output_buffer, "X: %.2f uT, Y: %.2f uT, Z: %.2f uT, Temp: %.2f C\n", // mag_data.x, mag_data.y, mag_data.z, mag_data.temperature); // CDC_Transmit_FS((uint8_t*)output_buffer, (uint16_t)strlen(output_buffer)); osMessageQueuePut(Q_BMMHandle, &mag_data, 0, 5); 80051d6: 4b08 ldr r3, [pc, #32] @ (80051f8 ) 80051d8: 6818 ldr r0, [r3, #0] 80051da: f107 010c add.w r1, r7, #12 80051de: 2305 movs r3, #5 80051e0: 2200 movs r2, #0 80051e2: f00e faf1 bl 80137c8 ulTaskNotifyTake(pdFALSE, osWaitForever); 80051e6: e7e1 b.n 80051ac 80051e8: 2000072c .word 0x2000072c 80051ec: 0801d4dc .word 0x0801d4dc 80051f0: 0801d500 .word 0x0801d500 80051f4: 0801d514 .word 0x0801d514 80051f8: 2000070c .word 0x2000070c 080051fc : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80051fc: b580 push {r7, lr} 80051fe: b082 sub sp, #8 8005200: af00 add r7, sp, #0 8005202: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM16) 8005204: 687b ldr r3, [r7, #4] 8005206: 681b ldr r3, [r3, #0] 8005208: 4a04 ldr r2, [pc, #16] @ (800521c ) 800520a: 4293 cmp r3, r2 800520c: d101 bne.n 8005212 { HAL_IncTick(); 800520e: f001 f91b bl 8006448 } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } 8005212: bf00 nop 8005214: 3708 adds r7, #8 8005216: 46bd mov sp, r7 8005218: bd80 pop {r7, pc} 800521a: bf00 nop 800521c: 40014400 .word 0x40014400 08005220 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8005220: b480 push {r7} 8005222: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8005224: b672 cpsid i } 8005226: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8005228: bf00 nop 800522a: e7fd b.n 8005228 0800522c : osThreadId_t xIMU_Task = NULL; osThreadId_t xMagn_Task = NULL; //osThreadId_t xData_Task = NULL; void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { 800522c: b580 push {r7, lr} 800522e: b084 sub sp, #16 8005230: af00 add r7, sp, #0 8005232: 6078 str r0, [r7, #4] if (hspi->Instance == SPI1) { 8005234: 687b ldr r3, [r7, #4] 8005236: 681b ldr r3, [r3, #0] 8005238: 4a10 ldr r2, [pc, #64] @ (800527c ) 800523a: 4293 cmp r3, r2 800523c: d11a bne.n 8005274 HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); 800523e: 2201 movs r2, #1 8005240: 2108 movs r1, #8 8005242: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8005246: f001 fee7 bl 8007018 // notify the task that the data is ready BaseType_t xHigherPriorityTaskWoken = pdFALSE; 800524a: 2300 movs r3, #0 800524c: 60fb str r3, [r7, #12] vTaskNotifyGiveFromISR(xIMU_Task, &xHigherPriorityTaskWoken); 800524e: 4b0c ldr r3, [pc, #48] @ (8005280 ) 8005250: 681b ldr r3, [r3, #0] 8005252: f107 020c add.w r2, r7, #12 8005256: 2100 movs r1, #0 8005258: 4618 mov r0, r3 800525a: f011 faf3 bl 8016844 portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 800525e: 68fb ldr r3, [r7, #12] 8005260: 2b00 cmp r3, #0 8005262: d007 beq.n 8005274 8005264: 4b07 ldr r3, [pc, #28] @ (8005284 ) 8005266: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800526a: 601a str r2, [r3, #0] 800526c: f3bf 8f4f dsb sy 8005270: f3bf 8f6f isb sy } } 8005274: bf00 nop 8005276: 3710 adds r7, #16 8005278: 46bd mov sp, r7 800527a: bd80 pop {r7, pc} 800527c: 40013000 .word 0x40013000 8005280: 20000728 .word 0x20000728 8005284: e000ed04 .word 0xe000ed04 08005288 : void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *I2C_address) { 8005288: b580 push {r7, lr} 800528a: b084 sub sp, #16 800528c: af00 add r7, sp, #0 800528e: 6078 str r0, [r7, #4] // printf("HAL_I2C_MemRxCpltCallback"); if (I2C_address->Instance == I2C1) { 8005290: 687b ldr r3, [r7, #4] 8005292: 681b ldr r3, [r3, #0] 8005294: 4a0d ldr r2, [pc, #52] @ (80052cc ) 8005296: 4293 cmp r3, r2 8005298: d114 bne.n 80052c4 BaseType_t xHigherPriorityTaskWoken = pdFALSE; 800529a: 2300 movs r3, #0 800529c: 60fb str r3, [r7, #12] vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken); 800529e: 4b0c ldr r3, [pc, #48] @ (80052d0 ) 80052a0: 681b ldr r3, [r3, #0] 80052a2: f107 020c add.w r2, r7, #12 80052a6: 2100 movs r1, #0 80052a8: 4618 mov r0, r3 80052aa: f011 facb bl 8016844 portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 80052ae: 68fb ldr r3, [r7, #12] 80052b0: 2b00 cmp r3, #0 80052b2: d007 beq.n 80052c4 80052b4: 4b07 ldr r3, [pc, #28] @ (80052d4 ) 80052b6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80052ba: 601a str r2, [r3, #0] 80052bc: f3bf 8f4f dsb sy 80052c0: f3bf 8f6f isb sy } } 80052c4: bf00 nop 80052c6: 3710 adds r7, #16 80052c8: 46bd mov sp, r7 80052ca: bd80 pop {r7, pc} 80052cc: 40005400 .word 0x40005400 80052d0: 2000072c .word 0x2000072c 80052d4: e000ed04 .word 0xe000ed04 080052d8 : void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *I2C_address) { 80052d8: b580 push {r7, lr} 80052da: b084 sub sp, #16 80052dc: af00 add r7, sp, #0 80052de: 6078 str r0, [r7, #4] // printf("HAL_I2C_MemTxCpltCallback"); if (I2C_address->Instance == I2C1) { 80052e0: 687b ldr r3, [r7, #4] 80052e2: 681b ldr r3, [r3, #0] 80052e4: 4a0d ldr r2, [pc, #52] @ (800531c ) 80052e6: 4293 cmp r3, r2 80052e8: d114 bne.n 8005314 BaseType_t xHigherPriorityTaskWoken = pdFALSE; 80052ea: 2300 movs r3, #0 80052ec: 60fb str r3, [r7, #12] vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken); 80052ee: 4b0c ldr r3, [pc, #48] @ (8005320 ) 80052f0: 681b ldr r3, [r3, #0] 80052f2: f107 020c add.w r2, r7, #12 80052f6: 2100 movs r1, #0 80052f8: 4618 mov r0, r3 80052fa: f011 faa3 bl 8016844 portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 80052fe: 68fb ldr r3, [r7, #12] 8005300: 2b00 cmp r3, #0 8005302: d007 beq.n 8005314 8005304: 4b07 ldr r3, [pc, #28] @ (8005324 ) 8005306: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800530a: 601a str r2, [r3, #0] 800530c: f3bf 8f4f dsb sy 8005310: f3bf 8f6f isb sy } } 8005314: bf00 nop 8005316: 3710 adds r7, #16 8005318: 46bd mov sp, r7 800531a: bd80 pop {r7, pc} 800531c: 40005400 .word 0x40005400 8005320: 2000072c .word 0x2000072c 8005324: e000ed04 .word 0xe000ed04 08005328 : void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { 8005328: b580 push {r7, lr} 800532a: b084 sub sp, #16 800532c: af00 add r7, sp, #0 800532e: 6078 str r0, [r7, #4] if (hi2c->Instance == I2C1) { 8005330: 687b ldr r3, [r7, #4] 8005332: 681b ldr r3, [r3, #0] 8005334: 4a11 ldr r2, [pc, #68] @ (800537c ) 8005336: 4293 cmp r3, r2 8005338: d11c bne.n 8005374 BaseType_t xHigherPriorityTaskWoken = pdFALSE; 800533a: 2300 movs r3, #0 800533c: 60fb str r3, [r7, #12] printf("ErrorCallback: %ld\n", HAL_I2C_GetError(hi2c)); 800533e: 6878 ldr r0, [r7, #4] 8005340: f002 f9eb bl 800771a 8005344: 4603 mov r3, r0 8005346: 4619 mov r1, r3 8005348: 480d ldr r0, [pc, #52] @ (8005380 ) 800534a: f014 fa7b bl 8019844 vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken); 800534e: 4b0d ldr r3, [pc, #52] @ (8005384 ) 8005350: 681b ldr r3, [r3, #0] 8005352: f107 020c add.w r2, r7, #12 8005356: 2100 movs r1, #0 8005358: 4618 mov r0, r3 800535a: f011 fa73 bl 8016844 portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 800535e: 68fb ldr r3, [r7, #12] 8005360: 2b00 cmp r3, #0 8005362: d007 beq.n 8005374 8005364: 4b08 ldr r3, [pc, #32] @ (8005388 ) 8005366: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800536a: 601a str r2, [r3, #0] 800536c: f3bf 8f4f dsb sy 8005370: f3bf 8f6f isb sy } } 8005374: bf00 nop 8005376: 3710 adds r7, #16 8005378: 46bd mov sp, r7 800537a: bd80 pop {r7, pc} 800537c: 40005400 .word 0x40005400 8005380: 0801d538 .word 0x0801d538 8005384: 2000072c .word 0x2000072c 8005388: e000ed04 .word 0xe000ed04 0800538c : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 800538c: b580 push {r7, lr} 800538e: b084 sub sp, #16 8005390: af00 add r7, sp, #0 8005392: 4603 mov r3, r0 8005394: 80fb strh r3, [r7, #6] // was macht das? BaseType_t xHigherPriorityTaskWoken = pdFALSE; 8005396: 2300 movs r3, #0 8005398: 60fb str r3, [r7, #12] if (GPIO_Pin == GPIO_IMU_INT_Pin) { 800539a: 88fb ldrh r3, [r7, #6] 800539c: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80053a0: d107 bne.n 80053b2 vTaskNotifyGiveFromISR(xIMU_Task, &xHigherPriorityTaskWoken); 80053a2: 4b11 ldr r3, [pc, #68] @ (80053e8 ) 80053a4: 681b ldr r3, [r3, #0] 80053a6: f107 020c add.w r2, r7, #12 80053aa: 2100 movs r1, #0 80053ac: 4618 mov r0, r3 80053ae: f011 fa49 bl 8016844 // printf("Triggered ICM45686 EXTI\n"); } if (GPIO_Pin == GPIO_MAGN_INT_Pin) { 80053b2: 88fb ldrh r3, [r7, #6] 80053b4: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80053b8: d107 bne.n 80053ca vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken); 80053ba: 4b0c ldr r3, [pc, #48] @ (80053ec ) 80053bc: 681b ldr r3, [r3, #0] 80053be: f107 020c add.w r2, r7, #12 80053c2: 2100 movs r1, #0 80053c4: 4618 mov r0, r3 80053c6: f011 fa3d bl 8016844 // printf("Triggered BMM350 EXTI\n"); } // was macht das? portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 80053ca: 68fb ldr r3, [r7, #12] 80053cc: 2b00 cmp r3, #0 80053ce: d007 beq.n 80053e0 80053d0: 4b07 ldr r3, [pc, #28] @ (80053f0 ) 80053d2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80053d6: 601a str r2, [r3, #0] 80053d8: f3bf 8f4f dsb sy 80053dc: f3bf 8f6f isb sy } 80053e0: bf00 nop 80053e2: 3710 adds r7, #16 80053e4: 46bd mov sp, r7 80053e6: bd80 pop {r7, pc} 80053e8: 20000728 .word 0x20000728 80053ec: 2000072c .word 0x2000072c 80053f0: e000ed04 .word 0xe000ed04 080053f4 : // ICM 45686 HAL_StatusTypeDef read_icm (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint8_t rx[], uint16_t len_tx) { 80053f4: b580 push {r7, lr} 80053f6: b088 sub sp, #32 80053f8: af02 add r7, sp, #8 80053fa: 60f8 str r0, [r7, #12] 80053fc: 60b9 str r1, [r7, #8] 80053fe: 607a str r2, [r7, #4] 8005400: 807b strh r3, [r7, #2] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET); 8005402: 68fb ldr r3, [r7, #12] 8005404: 6858 ldr r0, [r3, #4] 8005406: 68fb ldr r3, [r7, #12] 8005408: 891b ldrh r3, [r3, #8] 800540a: 2200 movs r2, #0 800540c: 4619 mov r1, r3 800540e: f001 fe03 bl 8007018 HAL_StatusTypeDef status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, len_tx, 50); 8005412: 68fb ldr r3, [r7, #12] 8005414: 6818 ldr r0, [r3, #0] 8005416: 887b ldrh r3, [r7, #2] 8005418: 2232 movs r2, #50 @ 0x32 800541a: 9200 str r2, [sp, #0] 800541c: 687a ldr r2, [r7, #4] 800541e: 68b9 ldr r1, [r7, #8] 8005420: f007 fcbd bl 800cd9e 8005424: 4603 mov r3, r0 8005426: 75fb strb r3, [r7, #23] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_SET); 8005428: 68fb ldr r3, [r7, #12] 800542a: 6858 ldr r0, [r3, #4] 800542c: 68fb ldr r3, [r7, #12] 800542e: 891b ldrh r3, [r3, #8] 8005430: 2201 movs r2, #1 8005432: 4619 mov r1, r3 8005434: f001 fdf0 bl 8007018 return status; 8005438: 7dfb ldrb r3, [r7, #23] } 800543a: 4618 mov r0, r3 800543c: 3718 adds r7, #24 800543e: 46bd mov sp, r7 8005440: bd80 pop {r7, pc} 08005442 : HAL_StatusTypeDef read_icm_dma (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint8_t rx[], uint16_t len_tx) { 8005442: b580 push {r7, lr} 8005444: b086 sub sp, #24 8005446: af00 add r7, sp, #0 8005448: 60f8 str r0, [r7, #12] 800544a: 60b9 str r1, [r7, #8] 800544c: 607a str r2, [r7, #4] 800544e: 807b strh r3, [r7, #2] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET); 8005450: 68fb ldr r3, [r7, #12] 8005452: 6858 ldr r0, [r3, #4] 8005454: 68fb ldr r3, [r7, #12] 8005456: 891b ldrh r3, [r3, #8] 8005458: 2200 movs r2, #0 800545a: 4619 mov r1, r3 800545c: f001 fddc bl 8007018 HAL_StatusTypeDef status = HAL_SPI_TransmitReceive_DMA(imu->hspi, tx, rx, len_tx); 8005460: 68fb ldr r3, [r7, #12] 8005462: 6818 ldr r0, [r3, #0] 8005464: 887b ldrh r3, [r7, #2] 8005466: 687a ldr r2, [r7, #4] 8005468: 68b9 ldr r1, [r7, #8] 800546a: f007 feb7 bl 800d1dc 800546e: 4603 mov r3, r0 8005470: 75fb strb r3, [r7, #23] return status; 8005472: 7dfb ldrb r3, [r7, #23] } 8005474: 4618 mov r0, r3 8005476: 3718 adds r7, #24 8005478: 46bd mov sp, r7 800547a: bd80 pop {r7, pc} 0800547c : HAL_StatusTypeDef write_icm (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint16_t len_tx) { 800547c: b580 push {r7, lr} 800547e: b086 sub sp, #24 8005480: af00 add r7, sp, #0 8005482: 60f8 str r0, [r7, #12] 8005484: 60b9 str r1, [r7, #8] 8005486: 4613 mov r3, r2 8005488: 80fb strh r3, [r7, #6] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET); 800548a: 68fb ldr r3, [r7, #12] 800548c: 6858 ldr r0, [r3, #4] 800548e: 68fb ldr r3, [r7, #12] 8005490: 891b ldrh r3, [r3, #8] 8005492: 2200 movs r2, #0 8005494: 4619 mov r1, r3 8005496: f001 fdbf bl 8007018 HAL_StatusTypeDef status = HAL_SPI_Transmit(imu->hspi, tx, len_tx, 50); 800549a: 68fb ldr r3, [r7, #12] 800549c: 6818 ldr r0, [r3, #0] 800549e: 88fa ldrh r2, [r7, #6] 80054a0: 2332 movs r3, #50 @ 0x32 80054a2: 68b9 ldr r1, [r7, #8] 80054a4: f007 fb05 bl 800cab2 80054a8: 4603 mov r3, r0 80054aa: 75fb strb r3, [r7, #23] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_SET); 80054ac: 68fb ldr r3, [r7, #12] 80054ae: 6858 ldr r0, [r3, #4] 80054b0: 68fb ldr r3, [r7, #12] 80054b2: 891b ldrh r3, [r3, #8] 80054b4: 2201 movs r2, #1 80054b6: 4619 mov r1, r3 80054b8: f001 fdae bl 8007018 return status; 80054bc: 7dfb ldrb r3, [r7, #23] } 80054be: 4618 mov r0, r3 80054c0: 3718 adds r7, #24 80054c2: 46bd mov sp, r7 80054c4: bd80 pop {r7, pc} ... 080054c8 : void init_icm(ICM45686_HandleTypeDef *imu) { 80054c8: b580 push {r7, lr} 80054ca: b084 sub sp, #16 80054cc: af00 add r7, sp, #0 80054ce: 6078 str r0, [r7, #4] // EDMP??? uint8_t tx[2], rx[2]; HAL_StatusTypeDef status; printf("Initializing ICM45686\n"); 80054d0: 4869 ldr r0, [pc, #420] @ (8005678 ) 80054d2: f014 fa1f bl 8019914 // WHO AM tx[0] = ICM45686_WHO_AM_I | 0x80; 80054d6: 23f2 movs r3, #242 @ 0xf2 80054d8: 733b strb r3, [r7, #12] // HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET); // status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50); // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); status = read_icm(imu, tx, rx, sizeof(tx)); 80054da: f107 0208 add.w r2, r7, #8 80054de: f107 010c add.w r1, r7, #12 80054e2: 2302 movs r3, #2 80054e4: 6878 ldr r0, [r7, #4] 80054e6: f7ff ff85 bl 80053f4 80054ea: 4603 mov r3, r0 80054ec: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 80054ee: 7bfb ldrb r3, [r7, #15] 80054f0: 2b00 cmp r3, #0 80054f2: d005 beq.n 8005500 printf("Error in reading WHO AM I:%d\n", status); 80054f4: 7bfb ldrb r3, [r7, #15] 80054f6: 4619 mov r1, r3 80054f8: 4860 ldr r0, [pc, #384] @ (800567c ) 80054fa: f014 f9a3 bl 8019844 80054fe: e004 b.n 800550a } else { printf("WHO AM I (0xE9): 0x%02X \n", rx[1]); 8005500: 7a7b ldrb r3, [r7, #9] 8005502: 4619 mov r1, r3 8005504: 485e ldr r0, [pc, #376] @ (8005680 ) 8005506: f014 f99d bl 8019844 } // acc tx[0] = ICM45686_ACCEL_CONFIG0; 800550a: 231b movs r3, #27 800550c: 733b strb r3, [r7, #12] tx[1] = imu->acc_fs | imu->odr; 800550e: 687b ldr r3, [r7, #4] 8005510: 7a9a ldrb r2, [r3, #10] 8005512: 687b ldr r3, [r7, #4] 8005514: 7b1b ldrb r3, [r3, #12] 8005516: 4313 orrs r3, r2 8005518: b2db uxtb r3, r3 800551a: 737b strb r3, [r7, #13] // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET); // status = HAL_SPI_Transmit(imu->hspi, tx, sizeof(tx), 50); // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); status = write_icm(imu, tx, sizeof(tx)); 800551c: f107 030c add.w r3, r7, #12 8005520: 2202 movs r2, #2 8005522: 4619 mov r1, r3 8005524: 6878 ldr r0, [r7, #4] 8005526: f7ff ffa9 bl 800547c 800552a: 4603 mov r3, r0 800552c: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 800552e: 7bfb ldrb r3, [r7, #15] 8005530: 2b00 cmp r3, #0 8005532: d005 beq.n 8005540 printf("Error in setting ACCEL_CONFIG0:%d\n", status); 8005534: 7bfb ldrb r3, [r7, #15] 8005536: 4619 mov r1, r3 8005538: 4852 ldr r0, [pc, #328] @ (8005684 ) 800553a: f014 f983 bl 8019844 800553e: e004 b.n 800554a } else { printf("ACCEL_CONFIG0 wrote: 0x%02X \n", tx[1]); 8005540: 7b7b ldrb r3, [r7, #13] 8005542: 4619 mov r1, r3 8005544: 4850 ldr r0, [pc, #320] @ (8005688 ) 8005546: f014 f97d bl 8019844 } tx[0] = ICM45686_ACCEL_CONFIG0 | 0x80; 800554a: 239b movs r3, #155 @ 0x9b 800554c: 733b strb r3, [r7, #12] tx[1] = 0x00; 800554e: 2300 movs r3, #0 8005550: 737b strb r3, [r7, #13] // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET); // status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50); // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); status = read_icm(imu, tx, rx, sizeof(tx)); 8005552: f107 0208 add.w r2, r7, #8 8005556: f107 010c add.w r1, r7, #12 800555a: 2302 movs r3, #2 800555c: 6878 ldr r0, [r7, #4] 800555e: f7ff ff49 bl 80053f4 8005562: 4603 mov r3, r0 8005564: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005566: 7bfb ldrb r3, [r7, #15] 8005568: 2b00 cmp r3, #0 800556a: d005 beq.n 8005578 printf("Error reading ACCEL_CONFIG0:%d\n", status); 800556c: 7bfb ldrb r3, [r7, #15] 800556e: 4619 mov r1, r3 8005570: 4846 ldr r0, [pc, #280] @ (800568c ) 8005572: f014 f967 bl 8019844 8005576: e004 b.n 8005582 } else { printf("ACCEL_CONFIG0 read: 0x%02X \n", rx[1]); 8005578: 7a7b ldrb r3, [r7, #9] 800557a: 4619 mov r1, r3 800557c: 4844 ldr r0, [pc, #272] @ (8005690 ) 800557e: f014 f961 bl 8019844 } // gyro tx[0] = ICM45686_GYRO_CONFIG0; 8005582: 231c movs r3, #28 8005584: 733b strb r3, [r7, #12] tx[1] = imu->gyro_fs | imu->odr; 8005586: 687b ldr r3, [r7, #4] 8005588: 7ada ldrb r2, [r3, #11] 800558a: 687b ldr r3, [r7, #4] 800558c: 7b1b ldrb r3, [r3, #12] 800558e: 4313 orrs r3, r2 8005590: b2db uxtb r3, r3 8005592: 737b strb r3, [r7, #13] // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET); // status = HAL_SPI_Transmit(imu->hspi, tx, sizeof(tx), 50); // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); status = write_icm(imu, tx, sizeof(tx)); 8005594: f107 030c add.w r3, r7, #12 8005598: 2202 movs r2, #2 800559a: 4619 mov r1, r3 800559c: 6878 ldr r0, [r7, #4] 800559e: f7ff ff6d bl 800547c 80055a2: 4603 mov r3, r0 80055a4: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 80055a6: 7bfb ldrb r3, [r7, #15] 80055a8: 2b00 cmp r3, #0 80055aa: d005 beq.n 80055b8 printf("Error in setting GYRO_CONFIG0:%d\n", status); 80055ac: 7bfb ldrb r3, [r7, #15] 80055ae: 4619 mov r1, r3 80055b0: 4838 ldr r0, [pc, #224] @ (8005694 ) 80055b2: f014 f947 bl 8019844 80055b6: e004 b.n 80055c2 } else { printf("GYRO_CONFIG0 wrote: 0x%02X \n", tx[1]); 80055b8: 7b7b ldrb r3, [r7, #13] 80055ba: 4619 mov r1, r3 80055bc: 4836 ldr r0, [pc, #216] @ (8005698 ) 80055be: f014 f941 bl 8019844 } tx[0] = ICM45686_GYRO_CONFIG0 | 0x80; 80055c2: 239c movs r3, #156 @ 0x9c 80055c4: 733b strb r3, [r7, #12] tx[1] = 0x00; 80055c6: 2300 movs r3, #0 80055c8: 737b strb r3, [r7, #13] // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET); // status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50); // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); status = read_icm(imu, tx, rx, sizeof(tx)); 80055ca: f107 0208 add.w r2, r7, #8 80055ce: f107 010c add.w r1, r7, #12 80055d2: 2302 movs r3, #2 80055d4: 6878 ldr r0, [r7, #4] 80055d6: f7ff ff0d bl 80053f4 80055da: 4603 mov r3, r0 80055dc: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 80055de: 7bfb ldrb r3, [r7, #15] 80055e0: 2b00 cmp r3, #0 80055e2: d005 beq.n 80055f0 printf("Error reading GYRO_CONFIG0:%d\n", status); 80055e4: 7bfb ldrb r3, [r7, #15] 80055e6: 4619 mov r1, r3 80055e8: 482c ldr r0, [pc, #176] @ (800569c ) 80055ea: f014 f92b bl 8019844 80055ee: e004 b.n 80055fa } else { printf("GYRO_CONFIG0 read: 0x%02X \n", rx[1]); 80055f0: 7a7b ldrb r3, [r7, #9] 80055f2: 4619 mov r1, r3 80055f4: 482a ldr r0, [pc, #168] @ (80056a0 ) 80055f6: f014 f925 bl 8019844 } // power settings tx[0] = ICM45686_PWR_MGMT0; 80055fa: 2310 movs r3, #16 80055fc: 733b strb r3, [r7, #12] tx[1] = 0x0F; //0x10 | 0x03; 80055fe: 230f movs r3, #15 8005600: 737b strb r3, [r7, #13] // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET); // status = HAL_SPI_Transmit(imu->hspi, tx, sizeof(tx), 50); // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); status = write_icm(imu, tx, sizeof(tx)); 8005602: f107 030c add.w r3, r7, #12 8005606: 2202 movs r2, #2 8005608: 4619 mov r1, r3 800560a: 6878 ldr r0, [r7, #4] 800560c: f7ff ff36 bl 800547c 8005610: 4603 mov r3, r0 8005612: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005614: 7bfb ldrb r3, [r7, #15] 8005616: 2b00 cmp r3, #0 8005618: d005 beq.n 8005626 printf("Error in setting PWR_MGMT0:%d\n", status); 800561a: 7bfb ldrb r3, [r7, #15] 800561c: 4619 mov r1, r3 800561e: 4821 ldr r0, [pc, #132] @ (80056a4 ) 8005620: f014 f910 bl 8019844 8005624: e004 b.n 8005630 } else { printf("PWR_MGMT0 wrote: 0x%02X \n", tx[1]); 8005626: 7b7b ldrb r3, [r7, #13] 8005628: 4619 mov r1, r3 800562a: 481f ldr r0, [pc, #124] @ (80056a8 ) 800562c: f014 f90a bl 8019844 } tx[0] = ICM45686_PWR_MGMT0 | 0x80; 8005630: 2390 movs r3, #144 @ 0x90 8005632: 733b strb r3, [r7, #12] tx[1] = 0x00; 8005634: 2300 movs r3, #0 8005636: 737b strb r3, [r7, #13] // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_RESET); // status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, sizeof(tx), 50); // HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); status = read_icm(imu, tx, rx, sizeof(tx)); 8005638: f107 0208 add.w r2, r7, #8 800563c: f107 010c add.w r1, r7, #12 8005640: 2302 movs r3, #2 8005642: 6878 ldr r0, [r7, #4] 8005644: f7ff fed6 bl 80053f4 8005648: 4603 mov r3, r0 800564a: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 800564c: 7bfb ldrb r3, [r7, #15] 800564e: 2b00 cmp r3, #0 8005650: d005 beq.n 800565e printf("Error reading PWR_MGMT0:%d\n", status); 8005652: 7bfb ldrb r3, [r7, #15] 8005654: 4619 mov r1, r3 8005656: 4815 ldr r0, [pc, #84] @ (80056ac ) 8005658: f014 f8f4 bl 8019844 800565c: e004 b.n 8005668 } else { printf("PWR_MGMT0 read: 0x%02X \n", rx[1]); 800565e: 7a7b ldrb r3, [r7, #9] 8005660: 4619 mov r1, r3 8005662: 4813 ldr r0, [pc, #76] @ (80056b0 ) 8005664: f014 f8ee bl 8019844 } osDelay(250); 8005668: 20fa movs r0, #250 @ 0xfa 800566a: f00d fdfc bl 8013266 } 800566e: bf00 nop 8005670: 3710 adds r7, #16 8005672: 46bd mov sp, r7 8005674: bd80 pop {r7, pc} 8005676: bf00 nop 8005678: 0801d54c .word 0x0801d54c 800567c: 0801d564 .word 0x0801d564 8005680: 0801d584 .word 0x0801d584 8005684: 0801d5a0 .word 0x0801d5a0 8005688: 0801d5c4 .word 0x0801d5c4 800568c: 0801d5e4 .word 0x0801d5e4 8005690: 0801d604 .word 0x0801d604 8005694: 0801d624 .word 0x0801d624 8005698: 0801d648 .word 0x0801d648 800569c: 0801d668 .word 0x0801d668 80056a0: 0801d688 .word 0x0801d688 80056a4: 0801d6a4 .word 0x0801d6a4 80056a8: 0801d6c4 .word 0x0801d6c4 80056ac: 0801d6e0 .word 0x0801d6e0 80056b0: 0801d6fc .word 0x0801d6fc 080056b4 : imu->imu_bias[3], imu->imu_bias[4], imu->imu_bias[5], imu->imu_bias[6]); } void enable_interrupt_icm(ICM45686_HandleTypeDef *imu) { 80056b4: b580 push {r7, lr} 80056b6: b084 sub sp, #16 80056b8: af00 add r7, sp, #0 80056ba: 6078 str r0, [r7, #4] uint8_t tx[2], rx[2] = {0x00, 0x00}; 80056bc: 2300 movs r3, #0 80056be: 813b strh r3, [r7, #8] tx[0] = ICM45686_INT1_CONFIG0; 80056c0: 2316 movs r3, #22 80056c2: 733b strb r3, [r7, #12] tx[1] = 0x04; 80056c4: 2304 movs r3, #4 80056c6: 737b strb r3, [r7, #13] printf("Enabling IMU INT pin\n"); 80056c8: 4819 ldr r0, [pc, #100] @ (8005730 ) 80056ca: f014 f923 bl 8019914 HAL_StatusTypeDef status = write_icm(imu, tx, sizeof(tx)); 80056ce: f107 030c add.w r3, r7, #12 80056d2: 2202 movs r2, #2 80056d4: 4619 mov r1, r3 80056d6: 6878 ldr r0, [r7, #4] 80056d8: f7ff fed0 bl 800547c 80056dc: 4603 mov r3, r0 80056de: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 80056e0: 7bfb ldrb r3, [r7, #15] 80056e2: 2b00 cmp r3, #0 80056e4: d004 beq.n 80056f0 printf("Enabling of IMU INT failed: %d\n", status); 80056e6: 7bfb ldrb r3, [r7, #15] 80056e8: 4619 mov r1, r3 80056ea: 4812 ldr r0, [pc, #72] @ (8005734 ) 80056ec: f014 f8aa bl 8019844 } tx[0] = ICM45686_INT1_CONFIG0 | 0x80; 80056f0: 2396 movs r3, #150 @ 0x96 80056f2: 733b strb r3, [r7, #12] tx[1] = 0x00; 80056f4: 2300 movs r3, #0 80056f6: 737b strb r3, [r7, #13] status = read_icm(imu, tx, rx, sizeof(tx)); 80056f8: f107 0208 add.w r2, r7, #8 80056fc: f107 010c add.w r1, r7, #12 8005700: 2302 movs r3, #2 8005702: 6878 ldr r0, [r7, #4] 8005704: f7ff fe76 bl 80053f4 8005708: 4603 mov r3, r0 800570a: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 800570c: 7bfb ldrb r3, [r7, #15] 800570e: 2b00 cmp r3, #0 8005710: d005 beq.n 800571e printf("Reading IMU INT configuration0 failed: %d\n", status); 8005712: 7bfb ldrb r3, [r7, #15] 8005714: 4619 mov r1, r3 8005716: 4808 ldr r0, [pc, #32] @ (8005738 ) 8005718: f014 f894 bl 8019844 } else { printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]); } } 800571c: e004 b.n 8005728 printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]); 800571e: 7a7b ldrb r3, [r7, #9] 8005720: 4619 mov r1, r3 8005722: 4806 ldr r0, [pc, #24] @ (800573c ) 8005724: f014 f88e bl 8019844 } 8005728: bf00 nop 800572a: 3710 adds r7, #16 800572c: 46bd mov sp, r7 800572e: bd80 pop {r7, pc} 8005730: 0801d7a8 .word 0x0801d7a8 8005734: 0801d7c0 .word 0x0801d7c0 8005738: 0801d7e0 .word 0x0801d7e0 800573c: 0801d80c .word 0x0801d80c 08005740 : void configure_interrupt_icm (ICM45686_HandleTypeDef *imu) { 8005740: b580 push {r7, lr} 8005742: b084 sub sp, #16 8005744: af00 add r7, sp, #0 8005746: 6078 str r0, [r7, #4] uint8_t tx[2], rx[2] = {0x00, 0x00}; 8005748: 2300 movs r3, #0 800574a: 813b strh r3, [r7, #8] tx[0] = ICM45686_INT1_CONFIG2; 800574c: 2318 movs r3, #24 800574e: 733b strb r3, [r7, #12] tx[1] = 0x01; 8005750: 2301 movs r3, #1 8005752: 737b strb r3, [r7, #13] printf("Configuring IMU INT\n"); 8005754: 4819 ldr r0, [pc, #100] @ (80057bc ) 8005756: f014 f8dd bl 8019914 HAL_StatusTypeDef status = write_icm(imu, tx, sizeof(tx)); 800575a: f107 030c add.w r3, r7, #12 800575e: 2202 movs r2, #2 8005760: 4619 mov r1, r3 8005762: 6878 ldr r0, [r7, #4] 8005764: f7ff fe8a bl 800547c 8005768: 4603 mov r3, r0 800576a: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 800576c: 7bfb ldrb r3, [r7, #15] 800576e: 2b00 cmp r3, #0 8005770: d004 beq.n 800577c printf("Configuration of IMU INT failed: %d\n", status); 8005772: 7bfb ldrb r3, [r7, #15] 8005774: 4619 mov r1, r3 8005776: 4812 ldr r0, [pc, #72] @ (80057c0 ) 8005778: f014 f864 bl 8019844 } tx[0] = ICM45686_INT1_CONFIG2 | 0x80; 800577c: 2398 movs r3, #152 @ 0x98 800577e: 733b strb r3, [r7, #12] tx[1] = 0x00; 8005780: 2300 movs r3, #0 8005782: 737b strb r3, [r7, #13] status = read_icm(imu, tx, rx, sizeof(tx)); 8005784: f107 0208 add.w r2, r7, #8 8005788: f107 010c add.w r1, r7, #12 800578c: 2302 movs r3, #2 800578e: 6878 ldr r0, [r7, #4] 8005790: f7ff fe30 bl 80053f4 8005794: 4603 mov r3, r0 8005796: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005798: 7bfb ldrb r3, [r7, #15] 800579a: 2b00 cmp r3, #0 800579c: d005 beq.n 80057aa printf("Reading IMU INT configuration2 failed: %d\n", status); 800579e: 7bfb ldrb r3, [r7, #15] 80057a0: 4619 mov r1, r3 80057a2: 4808 ldr r0, [pc, #32] @ (80057c4 ) 80057a4: f014 f84e bl 8019844 } else { printf("INT1_CONFIG2 read: 0x%02X\n", rx[1]); } } 80057a8: e004 b.n 80057b4 printf("INT1_CONFIG2 read: 0x%02X\n", rx[1]); 80057aa: 7a7b ldrb r3, [r7, #9] 80057ac: 4619 mov r1, r3 80057ae: 4806 ldr r0, [pc, #24] @ (80057c8 ) 80057b0: f014 f848 bl 8019844 } 80057b4: bf00 nop 80057b6: 3710 adds r7, #16 80057b8: 46bd mov sp, r7 80057ba: bd80 pop {r7, pc} 80057bc: 0801d828 .word 0x0801d828 80057c0: 0801d83c .word 0x0801d83c 80057c4: 0801d864 .word 0x0801d864 80057c8: 0801d890 .word 0x0801d890 080057cc : // BMM350 void bmm_init_DWT(void){ 80057cc: b480 push {r7} 80057ce: af00 add r7, sp, #0 // Enable trace and debug block (TRCENA) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 80057d0: 4b09 ldr r3, [pc, #36] @ (80057f8 ) 80057d2: 68db ldr r3, [r3, #12] 80057d4: 4a08 ldr r2, [pc, #32] @ (80057f8 ) 80057d6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 80057da: 60d3 str r3, [r2, #12] // Reset cycle counter DWT->CYCCNT = 0; 80057dc: 4b07 ldr r3, [pc, #28] @ (80057fc ) 80057de: 2200 movs r2, #0 80057e0: 605a str r2, [r3, #4] // Enable the cycle counter DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; 80057e2: 4b06 ldr r3, [pc, #24] @ (80057fc ) 80057e4: 681b ldr r3, [r3, #0] 80057e6: 4a05 ldr r2, [pc, #20] @ (80057fc ) 80057e8: f043 0301 orr.w r3, r3, #1 80057ec: 6013 str r3, [r2, #0] } 80057ee: bf00 nop 80057f0: 46bd mov sp, r7 80057f2: f85d 7b04 ldr.w r7, [sp], #4 80057f6: 4770 bx lr 80057f8: e000edf0 .word 0xe000edf0 80057fc: e0001000 .word 0xe0001000 08005800 : BMM350_INTF_RET_TYPE bmm350_i2c_read(uint8_t reg_addr, uint8_t *reg_data, uint32_t length, void *intf_ptr){ 8005800: b580 push {r7, lr} 8005802: b088 sub sp, #32 8005804: af02 add r7, sp, #8 8005806: 60b9 str r1, [r7, #8] 8005808: 607a str r2, [r7, #4] 800580a: 603b str r3, [r7, #0] 800580c: 4603 mov r3, r0 800580e: 73fb strb r3, [r7, #15] // Extract I2C device address from intf_ptr uint8_t device_addr = *(uint8_t*)intf_ptr; 8005810: 683b ldr r3, [r7, #0] 8005812: 781b ldrb r3, [r3, #0] 8005814: 75fb strb r3, [r7, #23] // STM32 HAL: Write register address, then read data // Device address is left-shifted by 1 for STM32 HAL // if (HAL_I2C_Mem_Read(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, reg_data, length, HAL_I2C_TIMEOUT ) == HAL_OK) { if (HAL_I2C_Mem_Read_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, reg_data, length) == HAL_OK) { 8005816: 7dfb ldrb r3, [r7, #23] 8005818: b29b uxth r3, r3 800581a: 005b lsls r3, r3, #1 800581c: b299 uxth r1, r3 800581e: 7bfb ldrb r3, [r7, #15] 8005820: b29a uxth r2, r3 8005822: 687b ldr r3, [r7, #4] 8005824: b29b uxth r3, r3 8005826: 9301 str r3, [sp, #4] 8005828: 68bb ldr r3, [r7, #8] 800582a: 9300 str r3, [sp, #0] 800582c: 2301 movs r3, #1 800582e: 480b ldr r0, [pc, #44] @ (800585c ) 8005830: f001 fdc8 bl 80073c4 8005834: 4603 mov r3, r0 8005836: 2b00 cmp r3, #0 8005838: d109 bne.n 800584e if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) { 800583a: 220a movs r2, #10 800583c: 2101 movs r1, #1 800583e: 2000 movs r0, #0 8005840: f010 fc78 bl 8016134 8005844: 4603 mov r3, r0 8005846: 2b01 cmp r3, #1 8005848: d101 bne.n 800584e return BMM350_INTF_RET_SUCCESS; // 0 800584a: 2300 movs r3, #0 800584c: e001 b.n 8005852 } } return -1; // Communication failure 800584e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 8005852: 4618 mov r0, r3 8005854: 3718 adds r7, #24 8005856: 46bd mov sp, r7 8005858: bd80 pop {r7, pc} 800585a: bf00 nop 800585c: 200003b4 .word 0x200003b4 08005860 : BMM350_INTF_RET_TYPE bmm350_i2c_write(uint8_t reg_addr, const uint8_t *reg_data, uint32_t length, void *intf_ptr){ 8005860: b580 push {r7, lr} 8005862: b088 sub sp, #32 8005864: af02 add r7, sp, #8 8005866: 60b9 str r1, [r7, #8] 8005868: 607a str r2, [r7, #4] 800586a: 603b str r3, [r7, #0] 800586c: 4603 mov r3, r0 800586e: 73fb strb r3, [r7, #15] uint8_t device_addr = *(uint8_t*)intf_ptr; 8005870: 683b ldr r3, [r7, #0] 8005872: 781b ldrb r3, [r3, #0] 8005874: 75fb strb r3, [r7, #23] // uint8_t rslt = HAL_I2C_Mem_Write_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length); // printf("rslt write: %d\n", rslt); // // STM32 HAL: Write register address + data if (HAL_I2C_Mem_Write_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length) == HAL_OK) { 8005876: 7dfb ldrb r3, [r7, #23] 8005878: b29b uxth r3, r3 800587a: 005b lsls r3, r3, #1 800587c: b299 uxth r1, r3 800587e: 7bfb ldrb r3, [r7, #15] 8005880: b29a uxth r2, r3 8005882: 687b ldr r3, [r7, #4] 8005884: b29b uxth r3, r3 8005886: 9301 str r3, [sp, #4] 8005888: 68bb ldr r3, [r7, #8] 800588a: 9300 str r3, [sp, #0] 800588c: 2301 movs r3, #1 800588e: 480b ldr r0, [pc, #44] @ (80058bc ) 8005890: f001 fcb2 bl 80071f8 8005894: 4603 mov r3, r0 8005896: 2b00 cmp r3, #0 8005898: d109 bne.n 80058ae // if (HAL_I2C_Mem_Write(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length, HAL_I2C_TIMEOUT ) == HAL_OK) { // if (rslt == HAL_OK) { if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) { 800589a: 220a movs r2, #10 800589c: 2101 movs r1, #1 800589e: 2000 movs r0, #0 80058a0: f010 fc48 bl 8016134 80058a4: 4603 mov r3, r0 80058a6: 2b01 cmp r3, #1 80058a8: d101 bne.n 80058ae return BMM350_INTF_RET_SUCCESS; // 0 80058aa: 2300 movs r3, #0 80058ac: e001 b.n 80058b2 } } return -1; 80058ae: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 80058b2: 4618 mov r0, r3 80058b4: 3718 adds r7, #24 80058b6: 46bd mov sp, r7 80058b8: bd80 pop {r7, pc} 80058ba: bf00 nop 80058bc: 200003b4 .word 0x200003b4 080058c0 : void bmm350_delay(uint32_t period_us, void *intf_ptr){ 80058c0: b480 push {r7} 80058c2: b085 sub sp, #20 80058c4: af00 add r7, sp, #0 80058c6: 6078 str r0, [r7, #4] 80058c8: 6039 str r1, [r7, #0] (void)intf_ptr; // Unused // For STM32, use DWT cycle counter for accurate microsecond delays uint32_t start = DWT->CYCCNT; 80058ca: 4b0e ldr r3, [pc, #56] @ (8005904 ) 80058cc: 685b ldr r3, [r3, #4] 80058ce: 60fb str r3, [r7, #12] uint32_t cycles = period_us * (SystemCoreClock / 1000000); 80058d0: 4b0d ldr r3, [pc, #52] @ (8005908 ) 80058d2: 681b ldr r3, [r3, #0] 80058d4: 4a0d ldr r2, [pc, #52] @ (800590c ) 80058d6: fba2 2303 umull r2, r3, r2, r3 80058da: 0c9a lsrs r2, r3, #18 80058dc: 687b ldr r3, [r7, #4] 80058de: fb02 f303 mul.w r3, r2, r3 80058e2: 60bb str r3, [r7, #8] while ((DWT->CYCCNT - start) < cycles); 80058e4: bf00 nop 80058e6: 4b07 ldr r3, [pc, #28] @ (8005904 ) 80058e8: 685a ldr r2, [r3, #4] 80058ea: 68fb ldr r3, [r7, #12] 80058ec: 1ad3 subs r3, r2, r3 80058ee: 68ba ldr r2, [r7, #8] 80058f0: 429a cmp r2, r3 80058f2: d8f8 bhi.n 80058e6 } 80058f4: bf00 nop 80058f6: bf00 nop 80058f8: 3714 adds r7, #20 80058fa: 46bd mov sp, r7 80058fc: f85d 7b04 ldr.w r7, [sp], #4 8005900: 4770 bx lr 8005902: bf00 nop 8005904: e0001000 .word 0xe0001000 8005908: 2000000c .word 0x2000000c 800590c: 431bde83 .word 0x431bde83 08005910 : // Initialization function int8_t init_bmm(struct bmm350_dev *dev) { 8005910: b580 push {r7, lr} 8005912: b084 sub sp, #16 8005914: af00 add r7, sp, #0 8005916: 6078 str r0, [r7, #4] // Static variable to hold I2C device address // Must be static or global because dev.intf_ptr will point to it static uint8_t dev_addr = BMM350_I2C_ADSEL_SET_LOW; // Assign function pointers dev->read = bmm350_i2c_read; 8005918: 687b ldr r3, [r7, #4] 800591a: 4a23 ldr r2, [pc, #140] @ (80059a8 ) 800591c: 609a str r2, [r3, #8] dev->write = bmm350_i2c_write; 800591e: 687b ldr r3, [r7, #4] 8005920: 4a22 ldr r2, [pc, #136] @ (80059ac ) 8005922: 60da str r2, [r3, #12] dev->delay_us = bmm350_delay; 8005924: 687b ldr r3, [r7, #4] 8005926: 4a22 ldr r2, [pc, #136] @ (80059b0 ) 8005928: 611a str r2, [r3, #16] dev->intf_ptr = &dev_addr; 800592a: 687b ldr r3, [r7, #4] 800592c: 4a21 ldr r2, [pc, #132] @ (80059b4 ) 800592e: 601a str r2, [r3, #0] printf("Starting up and configuring BMM350\n"); 8005930: 4821 ldr r0, [pc, #132] @ (80059b8 ) 8005932: f013 ffef bl 8019914 // Initialize BMM350 driver rslt = bmm350_init(dev); 8005936: 6878 ldr r0, [r7, #4] 8005938: f7fc fe40 bl 80025bc 800593c: 4603 mov r3, r0 800593e: 73fb strb r3, [r7, #15] if (rslt != BMM350_OK) 8005940: f997 300f ldrsb.w r3, [r7, #15] 8005944: 2b00 cmp r3, #0 8005946: d002 beq.n 800594e { // Handle error: chip ID mismatch, communication failure, etc. return rslt; 8005948: f997 300f ldrsb.w r3, [r7, #15] 800594c: e027 b.n 800599e } printf("Initialization: %d\n", rslt); 800594e: f997 300f ldrsb.w r3, [r7, #15] 8005952: 4619 mov r1, r3 8005954: 4819 ldr r0, [pc, #100] @ (80059bc ) 8005956: f013 ff75 bl 8019844 printf("CHIP_ID (should be 0x33) - Read Register: 0x00 BMM350 Chip ID: 0x%X\n", dev->chip_id); 800595a: 687b ldr r3, [r7, #4] 800595c: 791b ldrb r3, [r3, #4] 800595e: 4619 mov r1, r3 8005960: 4817 ldr r0, [pc, #92] @ (80059c0 ) 8005962: f013 ff6f bl 8019844 // Set powermode, odr and avg rslt = bmm350_set_powermode(BMM350_NORMAL_MODE, dev); 8005966: 6879 ldr r1, [r7, #4] 8005968: 2001 movs r0, #1 800596a: f7fc ff56 bl 800281a 800596e: 4603 mov r3, r0 8005970: 73fb strb r3, [r7, #15] printf("Powermode (%d): %d\n", BMM350_NORMAL_MODE, rslt); 8005972: f997 300f ldrsb.w r3, [r7, #15] 8005976: 461a mov r2, r3 8005978: 2101 movs r1, #1 800597a: 4812 ldr r0, [pc, #72] @ (80059c4 ) 800597c: f013 ff62 bl 8019844 rslt = bmm350_set_odr_performance(BMM350_DATA_RATE_200HZ, BMM350_AVERAGING_2, dev); 8005980: 687a ldr r2, [r7, #4] 8005982: 2101 movs r1, #1 8005984: 2003 movs r0, #3 8005986: f7fc ff9a bl 80028be 800598a: 4603 mov r3, r0 800598c: 73fb strb r3, [r7, #15] printf("ODR(%d) and AVG(%d): %d\n", BMM350_DATA_RATE_200HZ, BMM350_AVERAGING_2, rslt); 800598e: f997 300f ldrsb.w r3, [r7, #15] 8005992: 2201 movs r2, #1 8005994: 2103 movs r1, #3 8005996: 480c ldr r0, [pc, #48] @ (80059c8 ) 8005998: f013 ff54 bl 8019844 // rslt = bmm350_enable_interrupt(BMM350_ENABLE_INTERRUPT, dev); // printf("Interrupt enable: %d", rslt); // rslt = bmm350_configure_interrupt(BMM350_LATCHED, BMM350_ACTIVE_HIGH, BMM350_INTR_OPEN_DRAIN, BMM350_MAP_TO_PIN, dev); // printf("Configure interrupt: %d", rslt); return BMM350_OK; 800599c: 2300 movs r3, #0 } 800599e: 4618 mov r0, r3 80059a0: 3710 adds r7, #16 80059a2: 46bd mov sp, r7 80059a4: bd80 pop {r7, pc} 80059a6: bf00 nop 80059a8: 08005801 .word 0x08005801 80059ac: 08005861 .word 0x08005861 80059b0: 080058c1 .word 0x080058c1 80059b4: 20000008 .word 0x20000008 80059b8: 0801d8ac .word 0x0801d8ac 80059bc: 0801d8d0 .word 0x0801d8d0 80059c0: 0801d8e4 .word 0x0801d8e4 80059c4: 0801d92c .word 0x0801d92c 80059c8: 0801d940 .word 0x0801d940 080059cc : int8_t bmm_configure_interrupt (struct bmm350_dev *dev) { 80059cc: b580 push {r7, lr} 80059ce: b086 sub sp, #24 80059d0: af02 add r7, sp, #8 80059d2: 6078 str r0, [r7, #4] int8_t rslt; rslt = bmm350_enable_interrupt(BMM350_ENABLE_INTERRUPT, dev); 80059d4: 6879 ldr r1, [r7, #4] 80059d6: 2001 movs r0, #1 80059d8: f7fc ffde bl 8002998 80059dc: 4603 mov r3, r0 80059de: 73fb strb r3, [r7, #15] printf("Interrupt enable: %d\n", rslt); 80059e0: f997 300f ldrsb.w r3, [r7, #15] 80059e4: 4619 mov r1, r3 80059e6: 480c ldr r0, [pc, #48] @ (8005a18 ) 80059e8: f013 ff2c bl 8019844 rslt = bmm350_configure_interrupt(BMM350_PULSED, BMM350_ACTIVE_HIGH, BMM350_INTR_PUSH_PULL, BMM350_MAP_TO_PIN, dev); 80059ec: 687b ldr r3, [r7, #4] 80059ee: 9300 str r3, [sp, #0] 80059f0: 2301 movs r3, #1 80059f2: 2201 movs r2, #1 80059f4: 2101 movs r1, #1 80059f6: 2000 movs r0, #0 80059f8: f7fc ffff bl 80029fa 80059fc: 4603 mov r3, r0 80059fe: 73fb strb r3, [r7, #15] printf("Configure interrupt: %d\n", rslt); 8005a00: f997 300f ldrsb.w r3, [r7, #15] 8005a04: 4619 mov r1, r3 8005a06: 4805 ldr r0, [pc, #20] @ (8005a1c ) 8005a08: f013 ff1c bl 8019844 return BMM350_OK; 8005a0c: 2300 movs r3, #0 } 8005a0e: 4618 mov r0, r3 8005a10: 3710 adds r7, #16 8005a12: 46bd mov sp, r7 8005a14: bd80 pop {r7, pc} 8005a16: bf00 nop 8005a18: 0801d95c .word 0x0801d95c 8005a1c: 0801d974 .word 0x0801d974 08005a20 : * @brief Enable RTC * @rmtoll BDCR RTCEN LL_RCC_EnableRTC * @retval None */ __STATIC_INLINE void LL_RCC_EnableRTC(void) { 8005a20: b480 push {r7} 8005a22: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 8005a24: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005a28: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005a2c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8005a30: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8005a34: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 8005a38: bf00 nop 8005a3a: 46bd mov sp, r7 8005a3c: f85d 7b04 ldr.w r7, [sp], #4 8005a40: 4770 bx lr 08005a42 : { 8005a42: b480 push {r7} 8005a44: b085 sub sp, #20 8005a46: af00 add r7, sp, #0 8005a48: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB2ENR, Periphs); 8005a4a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005a4e: 6cda ldr r2, [r3, #76] @ 0x4c 8005a50: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005a54: 687b ldr r3, [r7, #4] 8005a56: 4313 orrs r3, r2 8005a58: 64cb str r3, [r1, #76] @ 0x4c tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 8005a5a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005a5e: 6cda ldr r2, [r3, #76] @ 0x4c 8005a60: 687b ldr r3, [r7, #4] 8005a62: 4013 ands r3, r2 8005a64: 60fb str r3, [r7, #12] (void)tmpreg; 8005a66: 68fb ldr r3, [r7, #12] } 8005a68: bf00 nop 8005a6a: 3714 adds r7, #20 8005a6c: 46bd mov sp, r7 8005a6e: f85d 7b04 ldr.w r7, [sp], #4 8005a72: 4770 bx lr 08005a74 : * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) { 8005a74: b480 push {r7} 8005a76: b085 sub sp, #20 8005a78: af00 add r7, sp, #0 8005a7a: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, Periphs); 8005a7c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005a80: 6d1a ldr r2, [r3, #80] @ 0x50 8005a82: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005a86: 687b ldr r3, [r7, #4] 8005a88: 4313 orrs r3, r2 8005a8a: 650b str r3, [r1, #80] @ 0x50 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 8005a8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005a90: 6d1a ldr r2, [r3, #80] @ 0x50 8005a92: 687b ldr r3, [r7, #4] 8005a94: 4013 ands r3, r2 8005a96: 60fb str r3, [r7, #12] (void)tmpreg; 8005a98: 68fb ldr r3, [r7, #12] } 8005a9a: bf00 nop 8005a9c: 3714 adds r7, #20 8005a9e: 46bd mov sp, r7 8005aa0: f85d 7b04 ldr.w r7, [sp], #4 8005aa4: 4770 bx lr 08005aa6 : * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) { 8005aa6: b480 push {r7} 8005aa8: b085 sub sp, #20 8005aaa: af00 add r7, sp, #0 8005aac: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR1, Periphs); 8005aae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005ab2: 6d9a ldr r2, [r3, #88] @ 0x58 8005ab4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005ab8: 687b ldr r3, [r7, #4] 8005aba: 4313 orrs r3, r2 8005abc: 658b str r3, [r1, #88] @ 0x58 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 8005abe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005ac2: 6d9a ldr r2, [r3, #88] @ 0x58 8005ac4: 687b ldr r3, [r7, #4] 8005ac6: 4013 ands r3, r2 8005ac8: 60fb str r3, [r7, #12] (void)tmpreg; 8005aca: 68fb ldr r3, [r7, #12] } 8005acc: bf00 nop 8005ace: 3714 adds r7, #20 8005ad0: 46bd mov sp, r7 8005ad2: f85d 7b04 ldr.w r7, [sp], #4 8005ad6: 4770 bx lr 08005ad8 : * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { 8005ad8: b480 push {r7} 8005ada: b085 sub sp, #20 8005adc: af00 add r7, sp, #0 8005ade: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, Periphs); 8005ae0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005ae4: 6e1a ldr r2, [r3, #96] @ 0x60 8005ae6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005aea: 687b ldr r3, [r7, #4] 8005aec: 4313 orrs r3, r2 8005aee: 660b str r3, [r1, #96] @ 0x60 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 8005af0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005af4: 6e1a ldr r2, [r3, #96] @ 0x60 8005af6: 687b ldr r3, [r7, #4] 8005af8: 4013 ands r3, r2 8005afa: 60fb str r3, [r7, #12] (void)tmpreg; 8005afc: 68fb ldr r3, [r7, #12] } 8005afe: bf00 nop 8005b00: 3714 adds r7, #20 8005b02: 46bd mov sp, r7 8005b04: f85d 7b04 ldr.w r7, [sp], #4 8005b08: 4770 bx lr 08005b0a : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8005b0a: b580 push {r7, lr} 8005b0c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_HSEM_CLK_ENABLE(); 8005b0e: f44f 2000 mov.w r0, #524288 @ 0x80000 8005b12: f7ff ffaf bl 8005a74 HAL_PWREx_EnableVddUSB(); 8005b16: f004 ff55 bl 800a9c4 /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8005b1a: 2200 movs r2, #0 8005b1c: 210f movs r1, #15 8005b1e: f06f 0001 mvn.w r0, #1 8005b22: f000 fdd5 bl 80066d0 /* Peripheral interrupt init */ /* HSEM_IRQn interrupt configuration */ HAL_NVIC_SetPriority(HSEM_IRQn, 5, 0); 8005b26: 2200 movs r2, #0 8005b28: 2105 movs r1, #5 8005b2a: 202e movs r0, #46 @ 0x2e 8005b2c: f000 fdd0 bl 80066d0 HAL_NVIC_EnableIRQ(HSEM_IRQn); 8005b30: 202e movs r0, #46 @ 0x2e 8005b32: f000 fde7 bl 8006704 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8005b36: bf00 nop 8005b38: bd80 pop {r7, pc} ... 08005b3c : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8005b3c: b580 push {r7, lr} 8005b3e: b09c sub sp, #112 @ 0x70 8005b40: af00 add r7, sp, #0 8005b42: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005b44: f107 035c add.w r3, r7, #92 @ 0x5c 8005b48: 2200 movs r2, #0 8005b4a: 601a str r2, [r3, #0] 8005b4c: 605a str r2, [r3, #4] 8005b4e: 609a str r2, [r3, #8] 8005b50: 60da str r2, [r3, #12] 8005b52: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8005b54: f107 030c add.w r3, r7, #12 8005b58: 2250 movs r2, #80 @ 0x50 8005b5a: 2100 movs r1, #0 8005b5c: 4618 mov r0, r3 8005b5e: f013 ffd9 bl 8019b14 if(hi2c->Instance==I2C1) 8005b62: 687b ldr r3, [r7, #4] 8005b64: 681b ldr r3, [r3, #0] 8005b66: 4a49 ldr r2, [pc, #292] @ (8005c8c ) 8005b68: 4293 cmp r3, r2 8005b6a: f040 808b bne.w 8005c84 /* USER CODE END I2C1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1; 8005b6e: 2304 movs r3, #4 8005b70: 60fb str r3, [r7, #12] PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; 8005b72: f44f 3340 mov.w r3, #196608 @ 0x30000 8005b76: 62fb str r3, [r7, #44] @ 0x2c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8005b78: f107 030c add.w r3, r7, #12 8005b7c: 4618 mov r0, r3 8005b7e: f006 fa8f bl 800c0a0 8005b82: 4603 mov r3, r0 8005b84: 2b00 cmp r3, #0 8005b86: d001 beq.n 8005b8c { Error_Handler(); 8005b88: f7ff fb4a bl 8005220 } __HAL_RCC_GPIOB_CLK_ENABLE(); 8005b8c: 2002 movs r0, #2 8005b8e: f7ff ff58 bl 8005a42 /**I2C1 GPIO Configuration PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 8005b92: f44f 7340 mov.w r3, #768 @ 0x300 8005b96: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8005b98: 2312 movs r3, #18 8005b9a: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005b9c: 2300 movs r3, #0 8005b9e: 667b str r3, [r7, #100] @ 0x64 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005ba0: 2300 movs r3, #0 8005ba2: 66bb str r3, [r7, #104] @ 0x68 GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 8005ba4: 2304 movs r3, #4 8005ba6: 66fb str r3, [r7, #108] @ 0x6c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005ba8: f107 035c add.w r3, r7, #92 @ 0x5c 8005bac: 4619 mov r1, r3 8005bae: 4838 ldr r0, [pc, #224] @ (8005c90 ) 8005bb0: f001 f8c2 bl 8006d38 /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8005bb4: f44f 1000 mov.w r0, #2097152 @ 0x200000 8005bb8: f7ff ff75 bl 8005aa6 /* I2C1 DMA Init */ /* I2C1_TX Init */ hdma_i2c1_tx.Instance = DMA1_Channel3; 8005bbc: 4b35 ldr r3, [pc, #212] @ (8005c94 ) 8005bbe: 4a36 ldr r2, [pc, #216] @ (8005c98 ) 8005bc0: 601a str r2, [r3, #0] hdma_i2c1_tx.Init.Request = DMA_REQUEST_I2C1_TX; 8005bc2: 4b34 ldr r3, [pc, #208] @ (8005c94 ) 8005bc4: 220b movs r2, #11 8005bc6: 605a str r2, [r3, #4] hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8005bc8: 4b32 ldr r3, [pc, #200] @ (8005c94 ) 8005bca: 2210 movs r2, #16 8005bcc: 609a str r2, [r3, #8] hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8005bce: 4b31 ldr r3, [pc, #196] @ (8005c94 ) 8005bd0: 2200 movs r2, #0 8005bd2: 60da str r2, [r3, #12] hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE; 8005bd4: 4b2f ldr r3, [pc, #188] @ (8005c94 ) 8005bd6: 2280 movs r2, #128 @ 0x80 8005bd8: 611a str r2, [r3, #16] hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005bda: 4b2e ldr r3, [pc, #184] @ (8005c94 ) 8005bdc: 2200 movs r2, #0 8005bde: 615a str r2, [r3, #20] hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005be0: 4b2c ldr r3, [pc, #176] @ (8005c94 ) 8005be2: 2200 movs r2, #0 8005be4: 619a str r2, [r3, #24] hdma_i2c1_tx.Init.Mode = DMA_NORMAL; 8005be6: 4b2b ldr r3, [pc, #172] @ (8005c94 ) 8005be8: 2200 movs r2, #0 8005bea: 61da str r2, [r3, #28] hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_HIGH; 8005bec: 4b29 ldr r3, [pc, #164] @ (8005c94 ) 8005bee: f44f 5200 mov.w r2, #8192 @ 0x2000 8005bf2: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_i2c1_tx) != HAL_OK) 8005bf4: 4827 ldr r0, [pc, #156] @ (8005c94 ) 8005bf6: f000 fdbd bl 8006774 8005bfa: 4603 mov r3, r0 8005bfc: 2b00 cmp r3, #0 8005bfe: d001 beq.n 8005c04 { Error_Handler(); 8005c00: f7ff fb0e bl 8005220 } __HAL_LINKDMA(hi2c,hdmatx,hdma_i2c1_tx); 8005c04: 687b ldr r3, [r7, #4] 8005c06: 4a23 ldr r2, [pc, #140] @ (8005c94 ) 8005c08: 639a str r2, [r3, #56] @ 0x38 8005c0a: 4a22 ldr r2, [pc, #136] @ (8005c94 ) 8005c0c: 687b ldr r3, [r7, #4] 8005c0e: 6293 str r3, [r2, #40] @ 0x28 /* I2C1_RX Init */ hdma_i2c1_rx.Instance = DMA1_Channel4; 8005c10: 4b22 ldr r3, [pc, #136] @ (8005c9c ) 8005c12: 4a23 ldr r2, [pc, #140] @ (8005ca0 ) 8005c14: 601a str r2, [r3, #0] hdma_i2c1_rx.Init.Request = DMA_REQUEST_I2C1_RX; 8005c16: 4b21 ldr r3, [pc, #132] @ (8005c9c ) 8005c18: 220a movs r2, #10 8005c1a: 605a str r2, [r3, #4] hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8005c1c: 4b1f ldr r3, [pc, #124] @ (8005c9c ) 8005c1e: 2200 movs r2, #0 8005c20: 609a str r2, [r3, #8] hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8005c22: 4b1e ldr r3, [pc, #120] @ (8005c9c ) 8005c24: 2200 movs r2, #0 8005c26: 60da str r2, [r3, #12] hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE; 8005c28: 4b1c ldr r3, [pc, #112] @ (8005c9c ) 8005c2a: 2280 movs r2, #128 @ 0x80 8005c2c: 611a str r2, [r3, #16] hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005c2e: 4b1b ldr r3, [pc, #108] @ (8005c9c ) 8005c30: 2200 movs r2, #0 8005c32: 615a str r2, [r3, #20] hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005c34: 4b19 ldr r3, [pc, #100] @ (8005c9c ) 8005c36: 2200 movs r2, #0 8005c38: 619a str r2, [r3, #24] hdma_i2c1_rx.Init.Mode = DMA_NORMAL; 8005c3a: 4b18 ldr r3, [pc, #96] @ (8005c9c ) 8005c3c: 2200 movs r2, #0 8005c3e: 61da str r2, [r3, #28] hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_HIGH; 8005c40: 4b16 ldr r3, [pc, #88] @ (8005c9c ) 8005c42: f44f 5200 mov.w r2, #8192 @ 0x2000 8005c46: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_i2c1_rx) != HAL_OK) 8005c48: 4814 ldr r0, [pc, #80] @ (8005c9c ) 8005c4a: f000 fd93 bl 8006774 8005c4e: 4603 mov r3, r0 8005c50: 2b00 cmp r3, #0 8005c52: d001 beq.n 8005c58 { Error_Handler(); 8005c54: f7ff fae4 bl 8005220 } __HAL_LINKDMA(hi2c,hdmarx,hdma_i2c1_rx); 8005c58: 687b ldr r3, [r7, #4] 8005c5a: 4a10 ldr r2, [pc, #64] @ (8005c9c ) 8005c5c: 63da str r2, [r3, #60] @ 0x3c 8005c5e: 4a0f ldr r2, [pc, #60] @ (8005c9c ) 8005c60: 687b ldr r3, [r7, #4] 8005c62: 6293 str r3, [r2, #40] @ 0x28 /* I2C1 interrupt Init */ HAL_NVIC_SetPriority(I2C1_EV_IRQn, 5, 0); 8005c64: 2200 movs r2, #0 8005c66: 2105 movs r1, #5 8005c68: 201e movs r0, #30 8005c6a: f000 fd31 bl 80066d0 HAL_NVIC_EnableIRQ(I2C1_EV_IRQn); 8005c6e: 201e movs r0, #30 8005c70: f000 fd48 bl 8006704 HAL_NVIC_SetPriority(I2C1_ER_IRQn, 5, 0); 8005c74: 2200 movs r2, #0 8005c76: 2105 movs r1, #5 8005c78: 201f movs r0, #31 8005c7a: f000 fd29 bl 80066d0 HAL_NVIC_EnableIRQ(I2C1_ER_IRQn); 8005c7e: 201f movs r0, #31 8005c80: f000 fd40 bl 8006704 /* USER CODE END I2C1_MspInit 1 */ } } 8005c84: bf00 nop 8005c86: 3770 adds r7, #112 @ 0x70 8005c88: 46bd mov sp, r7 8005c8a: bd80 pop {r7, pc} 8005c8c: 40005400 .word 0x40005400 8005c90: 48000400 .word 0x48000400 8005c94: 20000408 .word 0x20000408 8005c98: 40020030 .word 0x40020030 8005c9c: 20000468 .word 0x20000468 8005ca0: 40020044 .word 0x40020044 08005ca4 : * This function configures the hardware resources used in this example * @param hipcc: IPCC handle pointer * @retval None */ void HAL_IPCC_MspInit(IPCC_HandleTypeDef* hipcc) { 8005ca4: b580 push {r7, lr} 8005ca6: b082 sub sp, #8 8005ca8: af00 add r7, sp, #0 8005caa: 6078 str r0, [r7, #4] if(hipcc->Instance==IPCC) 8005cac: 687b ldr r3, [r7, #4] 8005cae: 681b ldr r3, [r3, #0] 8005cb0: 4a0d ldr r2, [pc, #52] @ (8005ce8 ) 8005cb2: 4293 cmp r3, r2 8005cb4: d113 bne.n 8005cde { /* USER CODE BEGIN IPCC_MspInit 0 */ /* USER CODE END IPCC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_IPCC_CLK_ENABLE(); 8005cb6: f44f 1080 mov.w r0, #1048576 @ 0x100000 8005cba: f7ff fedb bl 8005a74 /* IPCC interrupt Init */ HAL_NVIC_SetPriority(IPCC_C1_RX_IRQn, 5, 0); 8005cbe: 2200 movs r2, #0 8005cc0: 2105 movs r1, #5 8005cc2: 202c movs r0, #44 @ 0x2c 8005cc4: f000 fd04 bl 80066d0 HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn); 8005cc8: 202c movs r0, #44 @ 0x2c 8005cca: f000 fd1b bl 8006704 HAL_NVIC_SetPriority(IPCC_C1_TX_IRQn, 5, 0); 8005cce: 2200 movs r2, #0 8005cd0: 2105 movs r1, #5 8005cd2: 202d movs r0, #45 @ 0x2d 8005cd4: f000 fcfc bl 80066d0 HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn); 8005cd8: 202d movs r0, #45 @ 0x2d 8005cda: f000 fd13 bl 8006704 /* USER CODE END IPCC_MspInit 1 */ } } 8005cde: bf00 nop 8005ce0: 3708 adds r7, #8 8005ce2: 46bd mov sp, r7 8005ce4: bd80 pop {r7, pc} 8005ce6: bf00 nop 8005ce8: 58000c00 .word 0x58000c00 08005cec : * This function configures the hardware resources used in this example * @param hrtc: RTC handle pointer * @retval None */ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { 8005cec: b580 push {r7, lr} 8005cee: b096 sub sp, #88 @ 0x58 8005cf0: af00 add r7, sp, #0 8005cf2: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8005cf4: f107 0308 add.w r3, r7, #8 8005cf8: 2250 movs r2, #80 @ 0x50 8005cfa: 2100 movs r1, #0 8005cfc: 4618 mov r0, r3 8005cfe: f013 ff09 bl 8019b14 if(hrtc->Instance==RTC) 8005d02: 687b ldr r3, [r7, #4] 8005d04: 681b ldr r3, [r3, #0] 8005d06: 4a13 ldr r2, [pc, #76] @ (8005d54 ) 8005d08: 4293 cmp r3, r2 8005d0a: d11f bne.n 8005d4c /* USER CODE END RTC_MspInit 0 */ /** Enable access to the backup domain */ HAL_PWR_EnableBkUpAccess(); 8005d0c: f004 fe3c bl 800a988 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; 8005d10: f44f 6300 mov.w r3, #2048 @ 0x800 8005d14: 60bb str r3, [r7, #8] PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; 8005d16: f44f 7300 mov.w r3, #512 @ 0x200 8005d1a: 64bb str r3, [r7, #72] @ 0x48 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8005d1c: f107 0308 add.w r3, r7, #8 8005d20: 4618 mov r0, r3 8005d22: f006 f9bd bl 800c0a0 8005d26: 4603 mov r3, r0 8005d28: 2b00 cmp r3, #0 8005d2a: d001 beq.n 8005d30 { Error_Handler(); 8005d2c: f7ff fa78 bl 8005220 } /* Peripheral clock enable */ __HAL_RCC_RTC_ENABLE(); 8005d30: f7ff fe76 bl 8005a20 __HAL_RCC_RTCAPB_CLK_ENABLE(); 8005d34: f44f 6080 mov.w r0, #1024 @ 0x400 8005d38: f7ff feb5 bl 8005aa6 /* RTC interrupt Init */ HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 5, 0); 8005d3c: 2200 movs r2, #0 8005d3e: 2105 movs r1, #5 8005d40: 2003 movs r0, #3 8005d42: f000 fcc5 bl 80066d0 HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); 8005d46: 2003 movs r0, #3 8005d48: f000 fcdc bl 8006704 /* USER CODE END RTC_MspInit 1 */ } } 8005d4c: bf00 nop 8005d4e: 3758 adds r7, #88 @ 0x58 8005d50: 46bd mov sp, r7 8005d52: bd80 pop {r7, pc} 8005d54: 40002800 .word 0x40002800 08005d58 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8005d58: b580 push {r7, lr} 8005d5a: b088 sub sp, #32 8005d5c: af00 add r7, sp, #0 8005d5e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005d60: f107 030c add.w r3, r7, #12 8005d64: 2200 movs r2, #0 8005d66: 601a str r2, [r3, #0] 8005d68: 605a str r2, [r3, #4] 8005d6a: 609a str r2, [r3, #8] 8005d6c: 60da str r2, [r3, #12] 8005d6e: 611a str r2, [r3, #16] if(hspi->Instance==SPI1) 8005d70: 687b ldr r3, [r7, #4] 8005d72: 681b ldr r3, [r3, #0] 8005d74: 4a5a ldr r2, [pc, #360] @ (8005ee0 ) 8005d76: 4293 cmp r3, r2 8005d78: d16c bne.n 8005e54 { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 8005d7a: f44f 5080 mov.w r0, #4096 @ 0x1000 8005d7e: f7ff feab bl 8005ad8 __HAL_RCC_GPIOA_CLK_ENABLE(); 8005d82: 2001 movs r0, #1 8005d84: f7ff fe5d bl 8005a42 /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = SPI1_IMU_SCK_Pin|SPI1_IMU_MISO_Pin|SPI1_IMU_MOSI_Pin; 8005d88: 23e0 movs r3, #224 @ 0xe0 8005d8a: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005d8c: 2302 movs r3, #2 8005d8e: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005d90: 2300 movs r3, #0 8005d92: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8005d94: 2302 movs r3, #2 8005d96: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; 8005d98: 2305 movs r3, #5 8005d9a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005d9c: f107 030c add.w r3, r7, #12 8005da0: 4619 mov r1, r3 8005da2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8005da6: f000 ffc7 bl 8006d38 /* SPI1 DMA Init */ /* SPI1_TX Init */ hdma_spi1_tx.Instance = DMA1_Channel1; 8005daa: 4b4e ldr r3, [pc, #312] @ (8005ee4 ) 8005dac: 4a4e ldr r2, [pc, #312] @ (8005ee8 ) 8005dae: 601a str r2, [r3, #0] hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX; 8005db0: 4b4c ldr r3, [pc, #304] @ (8005ee4 ) 8005db2: 2207 movs r2, #7 8005db4: 605a str r2, [r3, #4] hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8005db6: 4b4b ldr r3, [pc, #300] @ (8005ee4 ) 8005db8: 2210 movs r2, #16 8005dba: 609a str r2, [r3, #8] hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8005dbc: 4b49 ldr r3, [pc, #292] @ (8005ee4 ) 8005dbe: 2200 movs r2, #0 8005dc0: 60da str r2, [r3, #12] hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE; 8005dc2: 4b48 ldr r3, [pc, #288] @ (8005ee4 ) 8005dc4: 2280 movs r2, #128 @ 0x80 8005dc6: 611a str r2, [r3, #16] hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005dc8: 4b46 ldr r3, [pc, #280] @ (8005ee4 ) 8005dca: 2200 movs r2, #0 8005dcc: 615a str r2, [r3, #20] hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005dce: 4b45 ldr r3, [pc, #276] @ (8005ee4 ) 8005dd0: 2200 movs r2, #0 8005dd2: 619a str r2, [r3, #24] hdma_spi1_tx.Init.Mode = DMA_NORMAL; 8005dd4: 4b43 ldr r3, [pc, #268] @ (8005ee4 ) 8005dd6: 2200 movs r2, #0 8005dd8: 61da str r2, [r3, #28] hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH; 8005dda: 4b42 ldr r3, [pc, #264] @ (8005ee4 ) 8005ddc: f44f 5200 mov.w r2, #8192 @ 0x2000 8005de0: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) 8005de2: 4840 ldr r0, [pc, #256] @ (8005ee4 ) 8005de4: f000 fcc6 bl 8006774 8005de8: 4603 mov r3, r0 8005dea: 2b00 cmp r3, #0 8005dec: d001 beq.n 8005df2 { Error_Handler(); 8005dee: f7ff fa17 bl 8005220 } __HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx); 8005df2: 687b ldr r3, [r7, #4] 8005df4: 4a3b ldr r2, [pc, #236] @ (8005ee4 ) 8005df6: 655a str r2, [r3, #84] @ 0x54 8005df8: 4a3a ldr r2, [pc, #232] @ (8005ee4 ) 8005dfa: 687b ldr r3, [r7, #4] 8005dfc: 6293 str r3, [r2, #40] @ 0x28 /* SPI1_RX Init */ hdma_spi1_rx.Instance = DMA1_Channel2; 8005dfe: 4b3b ldr r3, [pc, #236] @ (8005eec ) 8005e00: 4a3b ldr r2, [pc, #236] @ (8005ef0 ) 8005e02: 601a str r2, [r3, #0] hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX; 8005e04: 4b39 ldr r3, [pc, #228] @ (8005eec ) 8005e06: 2206 movs r2, #6 8005e08: 605a str r2, [r3, #4] hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8005e0a: 4b38 ldr r3, [pc, #224] @ (8005eec ) 8005e0c: 2200 movs r2, #0 8005e0e: 609a str r2, [r3, #8] hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8005e10: 4b36 ldr r3, [pc, #216] @ (8005eec ) 8005e12: 2200 movs r2, #0 8005e14: 60da str r2, [r3, #12] hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE; 8005e16: 4b35 ldr r3, [pc, #212] @ (8005eec ) 8005e18: 2280 movs r2, #128 @ 0x80 8005e1a: 611a str r2, [r3, #16] hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005e1c: 4b33 ldr r3, [pc, #204] @ (8005eec ) 8005e1e: 2200 movs r2, #0 8005e20: 615a str r2, [r3, #20] hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005e22: 4b32 ldr r3, [pc, #200] @ (8005eec ) 8005e24: 2200 movs r2, #0 8005e26: 619a str r2, [r3, #24] hdma_spi1_rx.Init.Mode = DMA_NORMAL; 8005e28: 4b30 ldr r3, [pc, #192] @ (8005eec ) 8005e2a: 2200 movs r2, #0 8005e2c: 61da str r2, [r3, #28] hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH; 8005e2e: 4b2f ldr r3, [pc, #188] @ (8005eec ) 8005e30: f44f 5200 mov.w r2, #8192 @ 0x2000 8005e34: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) 8005e36: 482d ldr r0, [pc, #180] @ (8005eec ) 8005e38: f000 fc9c bl 8006774 8005e3c: 4603 mov r3, r0 8005e3e: 2b00 cmp r3, #0 8005e40: d001 beq.n 8005e46 { Error_Handler(); 8005e42: f7ff f9ed bl 8005220 } __HAL_LINKDMA(hspi,hdmarx,hdma_spi1_rx); 8005e46: 687b ldr r3, [r7, #4] 8005e48: 4a28 ldr r2, [pc, #160] @ (8005eec ) 8005e4a: 659a str r2, [r3, #88] @ 0x58 8005e4c: 4a27 ldr r2, [pc, #156] @ (8005eec ) 8005e4e: 687b ldr r3, [r7, #4] 8005e50: 6293 str r3, [r2, #40] @ 0x28 /* USER CODE BEGIN SPI2_MspInit 1 */ /* USER CODE END SPI2_MspInit 1 */ } } 8005e52: e040 b.n 8005ed6 else if(hspi->Instance==SPI2) 8005e54: 687b ldr r3, [r7, #4] 8005e56: 681b ldr r3, [r3, #0] 8005e58: 4a26 ldr r2, [pc, #152] @ (8005ef4 ) 8005e5a: 4293 cmp r3, r2 8005e5c: d13b bne.n 8005ed6 __HAL_RCC_SPI2_CLK_ENABLE(); 8005e5e: f44f 4080 mov.w r0, #16384 @ 0x4000 8005e62: f7ff fe20 bl 8005aa6 __HAL_RCC_GPIOC_CLK_ENABLE(); 8005e66: 2004 movs r0, #4 8005e68: f7ff fdeb bl 8005a42 __HAL_RCC_GPIOA_CLK_ENABLE(); 8005e6c: 2001 movs r0, #1 8005e6e: f7ff fde8 bl 8005a42 GPIO_InitStruct.Pin = SPI2_SD_MOSI_Pin; 8005e72: 2302 movs r3, #2 8005e74: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005e76: 2302 movs r3, #2 8005e78: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005e7a: 2300 movs r3, #0 8005e7c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8005e7e: 2303 movs r3, #3 8005e80: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF3_SPI2; 8005e82: 2303 movs r3, #3 8005e84: 61fb str r3, [r7, #28] HAL_GPIO_Init(SPI2_SD_MOSI_GPIO_Port, &GPIO_InitStruct); 8005e86: f107 030c add.w r3, r7, #12 8005e8a: 4619 mov r1, r3 8005e8c: 481a ldr r0, [pc, #104] @ (8005ef8 ) 8005e8e: f000 ff53 bl 8006d38 GPIO_InitStruct.Pin = SPI2_SD_MISO_Pin; 8005e92: 2304 movs r3, #4 8005e94: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005e96: 2302 movs r3, #2 8005e98: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005e9a: 2300 movs r3, #0 8005e9c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8005e9e: 2303 movs r3, #3 8005ea0: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 8005ea2: 2305 movs r3, #5 8005ea4: 61fb str r3, [r7, #28] HAL_GPIO_Init(SPI2_SD_MISO_GPIO_Port, &GPIO_InitStruct); 8005ea6: f107 030c add.w r3, r7, #12 8005eaa: 4619 mov r1, r3 8005eac: 4812 ldr r0, [pc, #72] @ (8005ef8 ) 8005eae: f000 ff43 bl 8006d38 GPIO_InitStruct.Pin = SPI2_SD_SCK_Pin; 8005eb2: f44f 7300 mov.w r3, #512 @ 0x200 8005eb6: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005eb8: 2302 movs r3, #2 8005eba: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005ebc: 2300 movs r3, #0 8005ebe: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8005ec0: 2303 movs r3, #3 8005ec2: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 8005ec4: 2305 movs r3, #5 8005ec6: 61fb str r3, [r7, #28] HAL_GPIO_Init(SPI2_SD_SCK_GPIO_Port, &GPIO_InitStruct); 8005ec8: f107 030c add.w r3, r7, #12 8005ecc: 4619 mov r1, r3 8005ece: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8005ed2: f000 ff31 bl 8006d38 } 8005ed6: bf00 nop 8005ed8: 3720 adds r7, #32 8005eda: 46bd mov sp, r7 8005edc: bd80 pop {r7, pc} 8005ede: bf00 nop 8005ee0: 40013000 .word 0x40013000 8005ee4: 200005f0 .word 0x200005f0 8005ee8: 40020008 .word 0x40020008 8005eec: 20000650 .word 0x20000650 8005ef0: 4002001c .word 0x4002001c 8005ef4: 40003800 .word 0x40003800 8005ef8: 48000800 .word 0x48000800 08005efc : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 8005efc: b580 push {r7, lr} 8005efe: b082 sub sp, #8 8005f00: af00 add r7, sp, #0 8005f02: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM2) 8005f04: 687b ldr r3, [r7, #4] 8005f06: 681b ldr r3, [r3, #0] 8005f08: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005f0c: d102 bne.n 8005f14 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8005f0e: 2001 movs r0, #1 8005f10: f7ff fdc9 bl 8005aa6 /* USER CODE END TIM2_MspInit 1 */ } } 8005f14: bf00 nop 8005f16: 3708 adds r7, #8 8005f18: 46bd mov sp, r7 8005f1a: bd80 pop {r7, pc} 08005f1c : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8005f1c: b580 push {r7, lr} 8005f1e: b088 sub sp, #32 8005f20: af00 add r7, sp, #0 8005f22: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005f24: f107 030c add.w r3, r7, #12 8005f28: 2200 movs r2, #0 8005f2a: 601a str r2, [r3, #0] 8005f2c: 605a str r2, [r3, #4] 8005f2e: 609a str r2, [r3, #8] 8005f30: 60da str r2, [r3, #12] 8005f32: 611a str r2, [r3, #16] if(htim->Instance==TIM2) 8005f34: 687b ldr r3, [r7, #4] 8005f36: 681b ldr r3, [r3, #0] 8005f38: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005f3c: d113 bne.n 8005f66 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8005f3e: 2001 movs r0, #1 8005f40: f7ff fd7f bl 8005a42 /**TIM2 GPIO Configuration PA0 ------> TIM2_CH1 PA1 ------> TIM2_CH2 PA2 ------> TIM2_CH3 */ GPIO_InitStruct.Pin = GPIO_CONNECT_LED_Pin|GPIO_STATUS_LED_Pin|GPIO_DEBUG_LED_Pin; 8005f44: 2307 movs r3, #7 8005f46: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005f48: 2302 movs r3, #2 8005f4a: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005f4c: 2300 movs r3, #0 8005f4e: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005f50: 2300 movs r3, #0 8005f52: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8005f54: 2301 movs r3, #1 8005f56: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005f58: f107 030c add.w r3, r7, #12 8005f5c: 4619 mov r1, r3 8005f5e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8005f62: f000 fee9 bl 8006d38 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8005f66: bf00 nop 8005f68: 3720 adds r7, #32 8005f6a: 46bd mov sp, r7 8005f6c: bd80 pop {r7, pc} 08005f6e : { 8005f6e: b480 push {r7} 8005f70: b085 sub sp, #20 8005f72: af00 add r7, sp, #0 8005f74: 6078 str r0, [r7, #4] SET_BIT(RCC->APB2ENR, Periphs); 8005f76: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005f7a: 6e1a ldr r2, [r3, #96] @ 0x60 8005f7c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005f80: 687b ldr r3, [r7, #4] 8005f82: 4313 orrs r3, r2 8005f84: 660b str r3, [r1, #96] @ 0x60 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 8005f86: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005f8a: 6e1a ldr r2, [r3, #96] @ 0x60 8005f8c: 687b ldr r3, [r7, #4] 8005f8e: 4013 ands r3, r2 8005f90: 60fb str r3, [r7, #12] (void)tmpreg; 8005f92: 68fb ldr r3, [r7, #12] } 8005f94: bf00 nop 8005f96: 3714 adds r7, #20 8005f98: 46bd mov sp, r7 8005f9a: f85d 7b04 ldr.w r7, [sp], #4 8005f9e: 4770 bx lr 08005fa0 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8005fa0: b580 push {r7, lr} 8005fa2: b08e sub sp, #56 @ 0x38 8005fa4: af00 add r7, sp, #0 8005fa6: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0; 8005fa8: 2300 movs r3, #0 8005faa: 633b str r3, [r7, #48] @ 0x30 uint32_t uwPrescalerValue = 0; 8005fac: 2300 movs r3, #0 8005fae: 62fb str r3, [r7, #44] @ 0x2c uint32_t pFLatency; HAL_StatusTypeDef status = HAL_OK; 8005fb0: 2300 movs r3, #0 8005fb2: f887 3037 strb.w r3, [r7, #55] @ 0x37 /*Configure the TIM16 IRQ priority */ HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority ,0); 8005fb6: 2200 movs r2, #0 8005fb8: 6879 ldr r1, [r7, #4] 8005fba: 2019 movs r0, #25 8005fbc: f000 fb88 bl 80066d0 /* Enable the TIM16 global Interrupt */ HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); 8005fc0: 2019 movs r0, #25 8005fc2: f000 fb9f bl 8006704 /* Enable TIM16 clock */ __HAL_RCC_TIM16_CLK_ENABLE(); 8005fc6: f44f 3000 mov.w r0, #131072 @ 0x20000 8005fca: f7ff ffd0 bl 8005f6e /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8005fce: f107 020c add.w r2, r7, #12 8005fd2: f107 0310 add.w r3, r7, #16 8005fd6: 4611 mov r1, r2 8005fd8: 4618 mov r0, r3 8005fda: f005 fdcf bl 800bb7c /* Compute TIM16 clock */ uwTimclock = HAL_RCC_GetPCLK2Freq(); 8005fde: f005 fdb7 bl 800bb50 8005fe2: 6338 str r0, [r7, #48] @ 0x30 /* Compute the prescaler value to have TIM16 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8005fe4: 6b3b ldr r3, [r7, #48] @ 0x30 8005fe6: 4a21 ldr r2, [pc, #132] @ (800606c ) 8005fe8: fba2 2303 umull r2, r3, r2, r3 8005fec: 0c9b lsrs r3, r3, #18 8005fee: 3b01 subs r3, #1 8005ff0: 62fb str r3, [r7, #44] @ 0x2c /* Initialize TIM16 */ htim16.Instance = TIM16; 8005ff2: 4b1f ldr r3, [pc, #124] @ (8006070 ) 8005ff4: 4a1f ldr r2, [pc, #124] @ (8006074 ) 8005ff6: 601a str r2, [r3, #0] * Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base. * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. * ClockDivision = 0 * Counter direction = Up */ htim16.Init.Period = (1000000U / 1000U) - 1U; 8005ff8: 4b1d ldr r3, [pc, #116] @ (8006070 ) 8005ffa: f240 32e7 movw r2, #999 @ 0x3e7 8005ffe: 60da str r2, [r3, #12] htim16.Init.Prescaler = uwPrescalerValue; 8006000: 4a1b ldr r2, [pc, #108] @ (8006070 ) 8006002: 6afb ldr r3, [r7, #44] @ 0x2c 8006004: 6053 str r3, [r2, #4] htim16.Init.ClockDivision = 0; 8006006: 4b1a ldr r3, [pc, #104] @ (8006070 ) 8006008: 2200 movs r2, #0 800600a: 611a str r2, [r3, #16] htim16.Init.CounterMode = TIM_COUNTERMODE_UP; 800600c: 4b18 ldr r3, [pc, #96] @ (8006070 ) 800600e: 2200 movs r2, #0 8006010: 609a str r2, [r3, #8] status = HAL_TIM_Base_Init(&htim16); 8006012: 4817 ldr r0, [pc, #92] @ (8006070 ) 8006014: f007 fd24 bl 800da60 8006018: 4603 mov r3, r0 800601a: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (status == HAL_OK) 800601e: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8006022: 2b00 cmp r3, #0 8006024: d11b bne.n 800605e /* Register callback */ HAL_TIM_RegisterCallback(&htim16, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&htim16); 8006026: 4812 ldr r0, [pc, #72] @ (8006070 ) 8006028: f007 fd7c bl 800db24 800602c: 4603 mov r3, r0 800602e: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (status == HAL_OK) 8006032: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8006036: 2b00 cmp r3, #0 8006038: d111 bne.n 800605e { /* Enable the TIM16 global Interrupt */ HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); 800603a: 2019 movs r0, #25 800603c: f000 fb62 bl 8006704 /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8006040: 687b ldr r3, [r7, #4] 8006042: 2b0f cmp r3, #15 8006044: d808 bhi.n 8006058 { /* Configure the TIM IRQ priority */ HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority, 0U); 8006046: 2200 movs r2, #0 8006048: 6879 ldr r1, [r7, #4] 800604a: 2019 movs r0, #25 800604c: f000 fb40 bl 80066d0 uwTickPrio = TickPriority; 8006050: 4a09 ldr r2, [pc, #36] @ (8006078 ) 8006052: 687b ldr r3, [r7, #4] 8006054: 6013 str r3, [r2, #0] 8006056: e002 b.n 800605e } else { status = HAL_ERROR; 8006058: 2301 movs r3, #1 800605a: f887 3037 strb.w r3, [r7, #55] @ 0x37 } } } /* Return function status */ return status; 800605e: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 } 8006062: 4618 mov r0, r3 8006064: 3738 adds r7, #56 @ 0x38 8006066: 46bd mov sp, r7 8006068: bd80 pop {r7, pc} 800606a: bf00 nop 800606c: 431bde83 .word 0x431bde83 8006070: 20000730 .word 0x20000730 8006074: 40014400 .word 0x40014400 8006078: 20000010 .word 0x20000010 0800607c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800607c: b480 push {r7} 800607e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8006080: bf00 nop 8006082: e7fd b.n 8006080 08006084 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8006084: b480 push {r7} 8006086: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8006088: bf00 nop 800608a: e7fd b.n 8006088 0800608c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800608c: b480 push {r7} 800608e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8006090: bf00 nop 8006092: e7fd b.n 8006090 08006094 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8006094: b480 push {r7} 8006096: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8006098: bf00 nop 800609a: e7fd b.n 8006098 0800609c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800609c: b480 push {r7} 800609e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80060a0: bf00 nop 80060a2: e7fd b.n 80060a0 080060a4 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80060a4: b480 push {r7} 80060a6: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80060a8: bf00 nop 80060aa: 46bd mov sp, r7 80060ac: f85d 7b04 ldr.w r7, [sp], #4 80060b0: 4770 bx lr 080060b2 : /** * @brief This function handles RTC wake-up interrupt through EXTI line 19. */ void RTC_WKUP_IRQHandler(void) { 80060b2: b580 push {r7, lr} 80060b4: af00 add r7, sp, #0 /* USER CODE BEGIN RTC_WKUP_IRQn 0 */ /* USER CODE END RTC_WKUP_IRQn 0 */ HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc); 80060b6: f7fd fff1 bl 800409c /* USER CODE BEGIN RTC_WKUP_IRQn 1 */ /* USER CODE END RTC_WKUP_IRQn 1 */ } 80060ba: bf00 nop 80060bc: bd80 pop {r7, pc} ... 080060c0 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 80060c0: b580 push {r7, lr} 80060c2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_spi1_tx); 80060c4: 4802 ldr r0, [pc, #8] @ (80060d0 ) 80060c6: f000 fcd7 bl 8006a78 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 80060ca: bf00 nop 80060cc: bd80 pop {r7, pc} 80060ce: bf00 nop 80060d0: 200005f0 .word 0x200005f0 080060d4 : /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { 80060d4: b580 push {r7, lr} 80060d6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_spi1_rx); 80060d8: 4802 ldr r0, [pc, #8] @ (80060e4 ) 80060da: f000 fccd bl 8006a78 /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } 80060de: bf00 nop 80060e0: bd80 pop {r7, pc} 80060e2: bf00 nop 80060e4: 20000650 .word 0x20000650 080060e8 : /** * @brief This function handles DMA1 channel3 global interrupt. */ void DMA1_Channel3_IRQHandler(void) { 80060e8: b580 push {r7, lr} 80060ea: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */ /* USER CODE END DMA1_Channel3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_i2c1_tx); 80060ec: 4802 ldr r0, [pc, #8] @ (80060f8 ) 80060ee: f000 fcc3 bl 8006a78 /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */ /* USER CODE END DMA1_Channel3_IRQn 1 */ } 80060f2: bf00 nop 80060f4: bd80 pop {r7, pc} 80060f6: bf00 nop 80060f8: 20000408 .word 0x20000408 080060fc : /** * @brief This function handles DMA1 channel4 global interrupt. */ void DMA1_Channel4_IRQHandler(void) { 80060fc: b580 push {r7, lr} 80060fe: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */ /* USER CODE END DMA1_Channel4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_i2c1_rx); 8006100: 4802 ldr r0, [pc, #8] @ (800610c ) 8006102: f000 fcb9 bl 8006a78 /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */ /* USER CODE END DMA1_Channel4_IRQn 1 */ } 8006106: bf00 nop 8006108: bd80 pop {r7, pc} 800610a: bf00 nop 800610c: 20000468 .word 0x20000468 08006110 : /** * @brief This function handles USB low priority interrupt, USB wake-up interrupt through EXTI line 28. */ void USB_LP_IRQHandler(void) { 8006110: b580 push {r7, lr} 8006112: af00 add r7, sp, #0 /* USER CODE BEGIN USB_LP_IRQn 0 */ /* USER CODE END USB_LP_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_FS); 8006114: 4802 ldr r0, [pc, #8] @ (8006120 ) 8006116: f002 ffe5 bl 80090e4 /* USER CODE BEGIN USB_LP_IRQn 1 */ /* USER CODE END USB_LP_IRQn 1 */ } 800611a: bf00 nop 800611c: bd80 pop {r7, pc} 800611e: bf00 nop 8006120: 200135f8 .word 0x200135f8 08006124 : /** * @brief This function handles TIM1 update interrupt and TIM16 global interrupt. */ void TIM1_UP_TIM16_IRQHandler(void) { 8006124: b580 push {r7, lr} 8006126: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */ /* USER CODE END TIM1_UP_TIM16_IRQn 0 */ HAL_TIM_IRQHandler(&htim16); 8006128: 4802 ldr r0, [pc, #8] @ (8006134 ) 800612a: f007 fda0 bl 800dc6e /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */ /* USER CODE END TIM1_UP_TIM16_IRQn 1 */ } 800612e: bf00 nop 8006130: bd80 pop {r7, pc} 8006132: bf00 nop 8006134: 20000730 .word 0x20000730 08006138 : /** * @brief This function handles I2C1 event interrupt. */ void I2C1_EV_IRQHandler(void) { 8006138: b580 push {r7, lr} 800613a: af00 add r7, sp, #0 /* USER CODE BEGIN I2C1_EV_IRQn 0 */ /* USER CODE END I2C1_EV_IRQn 0 */ HAL_I2C_EV_IRQHandler(&hi2c1); 800613c: 4802 ldr r0, [pc, #8] @ (8006148 ) 800613e: f001 fa27 bl 8007590 /* USER CODE BEGIN I2C1_EV_IRQn 1 */ /* USER CODE END I2C1_EV_IRQn 1 */ } 8006142: bf00 nop 8006144: bd80 pop {r7, pc} 8006146: bf00 nop 8006148: 200003b4 .word 0x200003b4 0800614c : /** * @brief This function handles I2C1 error interrupt. */ void I2C1_ER_IRQHandler(void) { 800614c: b580 push {r7, lr} 800614e: af00 add r7, sp, #0 /* USER CODE BEGIN I2C1_ER_IRQn 0 */ /* USER CODE END I2C1_ER_IRQn 0 */ HAL_I2C_ER_IRQHandler(&hi2c1); 8006150: 4802 ldr r0, [pc, #8] @ (800615c ) 8006152: f001 fa37 bl 80075c4 /* USER CODE BEGIN I2C1_ER_IRQn 1 */ /* USER CODE END I2C1_ER_IRQn 1 */ } 8006156: bf00 nop 8006158: bd80 pop {r7, pc} 800615a: bf00 nop 800615c: 200003b4 .word 0x200003b4 08006160 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8006160: b580 push {r7, lr} 8006162: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_IMU_INT_Pin); 8006164: f44f 6080 mov.w r0, #1024 @ 0x400 8006168: f000 ff6e bl 8007048 HAL_GPIO_EXTI_IRQHandler(GPIO_MAGN_INT_Pin); 800616c: f44f 6000 mov.w r0, #2048 @ 0x800 8006170: f000 ff6a bl 8007048 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 8006174: bf00 nop 8006176: bd80 pop {r7, pc} 08006178 : /** * @brief This function handles IPCC RX occupied interrupt. */ void IPCC_C1_RX_IRQHandler(void) { 8006178: b580 push {r7, lr} 800617a: af00 add r7, sp, #0 /* USER CODE BEGIN IPCC_C1_RX_IRQn 0 */ /* USER CODE END IPCC_C1_RX_IRQn 0 */ HAL_IPCC_RX_IRQHandler(&hipcc); 800617c: f011 fcfe bl 8017b7c /* USER CODE BEGIN IPCC_C1_RX_IRQn 1 */ /* USER CODE END IPCC_C1_RX_IRQn 1 */ } 8006180: bf00 nop 8006182: bd80 pop {r7, pc} 08006184 : /** * @brief This function handles IPCC TX free interrupt. */ void IPCC_C1_TX_IRQHandler(void) { 8006184: b580 push {r7, lr} 8006186: af00 add r7, sp, #0 /* USER CODE BEGIN IPCC_C1_TX_IRQn 0 */ /* USER CODE END IPCC_C1_TX_IRQn 0 */ HAL_IPCC_TX_IRQHandler(&hipcc); 8006188: f011 fd2e bl 8017be8 /* USER CODE BEGIN IPCC_C1_TX_IRQn 1 */ /* USER CODE END IPCC_C1_TX_IRQn 1 */ } 800618c: bf00 nop 800618e: bd80 pop {r7, pc} 08006190 : /** * @brief This function handles HSEM global interrupt. */ void HSEM_IRQHandler(void) { 8006190: b580 push {r7, lr} 8006192: af00 add r7, sp, #0 /* USER CODE BEGIN HSEM_IRQn 0 */ /* USER CODE END HSEM_IRQn 0 */ HAL_HSEM_IRQHandler(); 8006194: f000 ff70 bl 8007078 /* USER CODE BEGIN HSEM_IRQn 1 */ /* USER CODE END HSEM_IRQn 1 */ } 8006198: bf00 nop 800619a: bd80 pop {r7, pc} 0800619c <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800619c: b480 push {r7} 800619e: af00 add r7, sp, #0 return 1; 80061a0: 2301 movs r3, #1 } 80061a2: 4618 mov r0, r3 80061a4: 46bd mov sp, r7 80061a6: f85d 7b04 ldr.w r7, [sp], #4 80061aa: 4770 bx lr 080061ac <_kill>: int _kill(int pid, int sig) { 80061ac: b580 push {r7, lr} 80061ae: b082 sub sp, #8 80061b0: af00 add r7, sp, #0 80061b2: 6078 str r0, [r7, #4] 80061b4: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 80061b6: f013 fcff bl 8019bb8 <__errno> 80061ba: 4603 mov r3, r0 80061bc: 2216 movs r2, #22 80061be: 601a str r2, [r3, #0] return -1; 80061c0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 80061c4: 4618 mov r0, r3 80061c6: 3708 adds r7, #8 80061c8: 46bd mov sp, r7 80061ca: bd80 pop {r7, pc} 080061cc <_exit>: void _exit (int status) { 80061cc: b580 push {r7, lr} 80061ce: b082 sub sp, #8 80061d0: af00 add r7, sp, #0 80061d2: 6078 str r0, [r7, #4] _kill(status, -1); 80061d4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80061d8: 6878 ldr r0, [r7, #4] 80061da: f7ff ffe7 bl 80061ac <_kill> while (1) {} /* Make sure we hang here */ 80061de: bf00 nop 80061e0: e7fd b.n 80061de <_exit+0x12> 080061e2 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 80061e2: b580 push {r7, lr} 80061e4: b086 sub sp, #24 80061e6: af00 add r7, sp, #0 80061e8: 60f8 str r0, [r7, #12] 80061ea: 60b9 str r1, [r7, #8] 80061ec: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80061ee: 2300 movs r3, #0 80061f0: 617b str r3, [r7, #20] 80061f2: e00a b.n 800620a <_read+0x28> { *ptr++ = __io_getchar(); 80061f4: f3af 8000 nop.w 80061f8: 4601 mov r1, r0 80061fa: 68bb ldr r3, [r7, #8] 80061fc: 1c5a adds r2, r3, #1 80061fe: 60ba str r2, [r7, #8] 8006200: b2ca uxtb r2, r1 8006202: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8006204: 697b ldr r3, [r7, #20] 8006206: 3301 adds r3, #1 8006208: 617b str r3, [r7, #20] 800620a: 697a ldr r2, [r7, #20] 800620c: 687b ldr r3, [r7, #4] 800620e: 429a cmp r2, r3 8006210: dbf0 blt.n 80061f4 <_read+0x12> } return len; 8006212: 687b ldr r3, [r7, #4] } 8006214: 4618 mov r0, r3 8006216: 3718 adds r7, #24 8006218: 46bd mov sp, r7 800621a: bd80 pop {r7, pc} 0800621c <_close>: } return len; } int _close(int file) { 800621c: b480 push {r7} 800621e: b083 sub sp, #12 8006220: af00 add r7, sp, #0 8006222: 6078 str r0, [r7, #4] (void)file; return -1; 8006224: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 8006228: 4618 mov r0, r3 800622a: 370c adds r7, #12 800622c: 46bd mov sp, r7 800622e: f85d 7b04 ldr.w r7, [sp], #4 8006232: 4770 bx lr 08006234 <_fstat>: int _fstat(int file, struct stat *st) { 8006234: b480 push {r7} 8006236: b083 sub sp, #12 8006238: af00 add r7, sp, #0 800623a: 6078 str r0, [r7, #4] 800623c: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800623e: 683b ldr r3, [r7, #0] 8006240: f44f 5200 mov.w r2, #8192 @ 0x2000 8006244: 605a str r2, [r3, #4] return 0; 8006246: 2300 movs r3, #0 } 8006248: 4618 mov r0, r3 800624a: 370c adds r7, #12 800624c: 46bd mov sp, r7 800624e: f85d 7b04 ldr.w r7, [sp], #4 8006252: 4770 bx lr 08006254 <_isatty>: int _isatty(int file) { 8006254: b480 push {r7} 8006256: b083 sub sp, #12 8006258: af00 add r7, sp, #0 800625a: 6078 str r0, [r7, #4] (void)file; return 1; 800625c: 2301 movs r3, #1 } 800625e: 4618 mov r0, r3 8006260: 370c adds r7, #12 8006262: 46bd mov sp, r7 8006264: f85d 7b04 ldr.w r7, [sp], #4 8006268: 4770 bx lr 0800626a <_lseek>: int _lseek(int file, int ptr, int dir) { 800626a: b480 push {r7} 800626c: b085 sub sp, #20 800626e: af00 add r7, sp, #0 8006270: 60f8 str r0, [r7, #12] 8006272: 60b9 str r1, [r7, #8] 8006274: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 8006276: 2300 movs r3, #0 } 8006278: 4618 mov r0, r3 800627a: 3714 adds r7, #20 800627c: 46bd mov sp, r7 800627e: f85d 7b04 ldr.w r7, [sp], #4 8006282: 4770 bx lr 08006284 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8006284: b580 push {r7, lr} 8006286: b086 sub sp, #24 8006288: af00 add r7, sp, #0 800628a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800628c: 4a14 ldr r2, [pc, #80] @ (80062e0 <_sbrk+0x5c>) 800628e: 4b15 ldr r3, [pc, #84] @ (80062e4 <_sbrk+0x60>) 8006290: 1ad3 subs r3, r2, r3 8006292: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8006294: 697b ldr r3, [r7, #20] 8006296: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8006298: 4b13 ldr r3, [pc, #76] @ (80062e8 <_sbrk+0x64>) 800629a: 681b ldr r3, [r3, #0] 800629c: 2b00 cmp r3, #0 800629e: d102 bne.n 80062a6 <_sbrk+0x22> { __sbrk_heap_end = &_end; 80062a0: 4b11 ldr r3, [pc, #68] @ (80062e8 <_sbrk+0x64>) 80062a2: 4a12 ldr r2, [pc, #72] @ (80062ec <_sbrk+0x68>) 80062a4: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80062a6: 4b10 ldr r3, [pc, #64] @ (80062e8 <_sbrk+0x64>) 80062a8: 681a ldr r2, [r3, #0] 80062aa: 687b ldr r3, [r7, #4] 80062ac: 4413 add r3, r2 80062ae: 693a ldr r2, [r7, #16] 80062b0: 429a cmp r2, r3 80062b2: d207 bcs.n 80062c4 <_sbrk+0x40> { errno = ENOMEM; 80062b4: f013 fc80 bl 8019bb8 <__errno> 80062b8: 4603 mov r3, r0 80062ba: 220c movs r2, #12 80062bc: 601a str r2, [r3, #0] return (void *)-1; 80062be: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80062c2: e009 b.n 80062d8 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80062c4: 4b08 ldr r3, [pc, #32] @ (80062e8 <_sbrk+0x64>) 80062c6: 681b ldr r3, [r3, #0] 80062c8: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80062ca: 4b07 ldr r3, [pc, #28] @ (80062e8 <_sbrk+0x64>) 80062cc: 681a ldr r2, [r3, #0] 80062ce: 687b ldr r3, [r7, #4] 80062d0: 4413 add r3, r2 80062d2: 4a05 ldr r2, [pc, #20] @ (80062e8 <_sbrk+0x64>) 80062d4: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80062d6: 68fb ldr r3, [r7, #12] } 80062d8: 4618 mov r0, r3 80062da: 3718 adds r7, #24 80062dc: 46bd mov sp, r7 80062de: bd80 pop {r7, pc} 80062e0: 20030000 .word 0x20030000 80062e4: 00000400 .word 0x00000400 80062e8: 2000077c .word 0x2000077c 80062ec: 20013c48 .word 0x20013c48 080062f0 : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 80062f0: b480 push {r7} 80062f2: af00 add r7, sp, #0 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; #endif /* USER_VECT_TAB_ADDRESS */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */ 80062f4: 4b24 ldr r3, [pc, #144] @ (8006388 ) 80062f6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80062fa: 4a23 ldr r2, [pc, #140] @ (8006388 ) 80062fc: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8006300: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* FPU */ /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ RCC->CR |= RCC_CR_MSION; 8006304: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006308: 681b ldr r3, [r3, #0] 800630a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800630e: f043 0301 orr.w r3, r3, #1 8006312: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00070000U; 8006314: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006318: f44f 22e0 mov.w r2, #458752 @ 0x70000 800631c: 609a str r2, [r3, #8] /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */ RCC->CR &= (uint32_t)0xFAF6FEFBU; 800631e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006322: 681a ldr r2, [r3, #0] 8006324: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006328: 4b18 ldr r3, [pc, #96] @ (800638c ) 800632a: 4013 ands r3, r2 800632c: 600b str r3, [r1, #0] /*!< Reset LSI1 and LSI2 bits */ RCC->CSR &= (uint32_t)0xFFFFFFFAU; 800632e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006332: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8006336: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800633a: f023 0305 bic.w r3, r3, #5 800633e: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /*!< Reset HSI48ON bit */ RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; 8006342: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006346: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800634a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800634e: f023 0301 bic.w r3, r3, #1 8006352: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x22041000U; 8006356: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800635a: 4a0d ldr r2, [pc, #52] @ (8006390 ) 800635c: 60da str r2, [r3, #12] #if defined(STM32WB55xx) || defined(STM32WB5Mxx) /* Reset PLLSAI1CFGR register */ RCC->PLLSAI1CFGR = 0x22041000U; 800635e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006362: 4a0b ldr r2, [pc, #44] @ (8006390 ) 8006364: 611a str r2, [r3, #16] #endif /* STM32WB55xx || STM32WB5Mxx */ /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8006366: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800636a: 681b ldr r3, [r3, #0] 800636c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8006370: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8006374: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8006376: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800637a: 2200 movs r2, #0 800637c: 619a str r2, [r3, #24] } 800637e: bf00 nop 8006380: 46bd mov sp, r7 8006382: f85d 7b04 ldr.w r7, [sp], #4 8006386: 4770 bx lr 8006388: e000ed00 .word 0xe000ed00 800638c: faf6fefb .word 0xfaf6fefb 8006390: 22041000 .word 0x22041000 08006394 : bl LoopCopyDataInit .endm .section .text.data_initializers CopyDataInit: ldr r4, [r2, r3] 8006394: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8006396: 50c4 str r4, [r0, r3] adds r3, r3, #4 8006398: 3304 adds r3, #4 0800639a : LoopCopyDataInit: adds r4, r0, r3 800639a: 18c4 adds r4, r0, r3 cmp r4, r1 800639c: 428c cmp r4, r1 bcc CopyDataInit 800639e: d3f9 bcc.n 8006394 bx lr 80063a0: 4770 bx lr 080063a2 : FillZerobss: str r3, [r0] 80063a2: 6003 str r3, [r0, #0] adds r0, r0, #4 80063a4: 3004 adds r0, #4 080063a6 : LoopFillZerobss: cmp r0, r1 80063a6: 4288 cmp r0, r1 bcc FillZerobss 80063a8: d3fb bcc.n 80063a2 bx lr 80063aa: 4770 bx lr 080063ac : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 80063ac: 480c ldr r0, [pc, #48] @ (80063e0 ) mov sp, r0 /* set stack pointer */ 80063ae: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 80063b0: f7ff ff9e bl 80062f0 /* Copy the data segment initializers from flash to SRAM */ INIT_DATA _sdata, _edata, _sidata 80063b4: 480b ldr r0, [pc, #44] @ (80063e4 ) 80063b6: 490c ldr r1, [pc, #48] @ (80063e8 ) 80063b8: 4a0c ldr r2, [pc, #48] @ (80063ec ) 80063ba: 2300 movs r3, #0 80063bc: f7ff ffed bl 800639a INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2 80063c0: 480b ldr r0, [pc, #44] @ (80063f0 ) 80063c2: 490c ldr r1, [pc, #48] @ (80063f4 ) 80063c4: 4a0c ldr r2, [pc, #48] @ (80063f8 ) 80063c6: 2300 movs r3, #0 80063c8: f7ff ffe7 bl 800639a /* Zero fill the bss segments. */ INIT_BSS _sbss, _ebss 80063cc: 480b ldr r0, [pc, #44] @ (80063fc ) 80063ce: 490c ldr r1, [pc, #48] @ (8006400 ) 80063d0: 2300 movs r3, #0 80063d2: f7ff ffe8 bl 80063a6 /* Call static constructors */ bl __libc_init_array 80063d6: f013 fbf5 bl 8019bc4 <__libc_init_array> /* Call the application s entry point.*/ bl main 80063da: f7fe f9bb bl 8004754
080063de : LoopForever: b LoopForever 80063de: e7fe b.n 80063de ldr r0, =_estack 80063e0: 20030000 .word 0x20030000 INIT_DATA _sdata, _edata, _sidata 80063e4: 20000008 .word 0x20000008 80063e8: 200002d8 .word 0x200002d8 80063ec: 0801e100 .word 0x0801e100 INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2 80063f0: 200300d8 .word 0x200300d8 80063f4: 2003094a .word 0x2003094a 80063f8: 0801e3e1 .word 0x0801e3e1 INIT_BSS _sbss, _ebss 80063fc: 200002ec .word 0x200002ec 8006400: 20013c48 .word 0x20013c48 08006404 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8006404: e7fe b.n 8006404 ... 08006408 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8006408: b580 push {r7, lr} 800640a: b082 sub sp, #8 800640c: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 800640e: 2300 movs r3, #0 8006410: 71fb strb r3, [r7, #7] #if (DATA_CACHE_ENABLE == 0U) __HAL_FLASH_DATA_CACHE_DISABLE(); #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8006412: 4b0c ldr r3, [pc, #48] @ (8006444 ) 8006414: 681b ldr r3, [r3, #0] 8006416: 4a0b ldr r2, [pc, #44] @ (8006444 ) 8006418: f443 7380 orr.w r3, r3, #256 @ 0x100 800641c: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800641e: 2003 movs r0, #3 8006420: f000 f94b bl 80066ba /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8006424: 200f movs r0, #15 8006426: f7ff fdbb bl 8005fa0 800642a: 4603 mov r3, r0 800642c: 2b00 cmp r3, #0 800642e: d002 beq.n 8006436 { status = HAL_ERROR; 8006430: 2301 movs r3, #1 8006432: 71fb strb r3, [r7, #7] 8006434: e001 b.n 800643a } else { /* Init the low level hardware */ HAL_MspInit(); 8006436: f7ff fb68 bl 8005b0a } /* Return function status */ return status; 800643a: 79fb ldrb r3, [r7, #7] } 800643c: 4618 mov r0, r3 800643e: 3708 adds r7, #8 8006440: 46bd mov sp, r7 8006442: bd80 pop {r7, pc} 8006444: 58004000 .word 0x58004000 08006448 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8006448: b480 push {r7} 800644a: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 800644c: 4b06 ldr r3, [pc, #24] @ (8006468 ) 800644e: 781b ldrb r3, [r3, #0] 8006450: 461a mov r2, r3 8006452: 4b06 ldr r3, [pc, #24] @ (800646c ) 8006454: 681b ldr r3, [r3, #0] 8006456: 4413 add r3, r2 8006458: 4a04 ldr r2, [pc, #16] @ (800646c ) 800645a: 6013 str r3, [r2, #0] } 800645c: bf00 nop 800645e: 46bd mov sp, r7 8006460: f85d 7b04 ldr.w r7, [sp], #4 8006464: 4770 bx lr 8006466: bf00 nop 8006468: 20000014 .word 0x20000014 800646c: 20000780 .word 0x20000780 08006470 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8006470: b480 push {r7} 8006472: af00 add r7, sp, #0 return uwTick; 8006474: 4b03 ldr r3, [pc, #12] @ (8006484 ) 8006476: 681b ldr r3, [r3, #0] } 8006478: 4618 mov r0, r3 800647a: 46bd mov sp, r7 800647c: f85d 7b04 ldr.w r7, [sp], #4 8006480: 4770 bx lr 8006482: bf00 nop 8006484: 20000780 .word 0x20000780 08006488 : /** * @brief This function returns a tick priority. * @retval tick priority */ uint32_t HAL_GetTickPrio(void) { 8006488: b480 push {r7} 800648a: af00 add r7, sp, #0 return uwTickPrio; 800648c: 4b03 ldr r3, [pc, #12] @ (800649c ) 800648e: 681b ldr r3, [r3, #0] } 8006490: 4618 mov r0, r3 8006492: 46bd mov sp, r7 8006494: f85d 7b04 ldr.w r7, [sp], #4 8006498: 4770 bx lr 800649a: bf00 nop 800649c: 20000010 .word 0x20000010 080064a0 <__NVIC_SetPriorityGrouping>: { 80064a0: b480 push {r7} 80064a2: b085 sub sp, #20 80064a4: af00 add r7, sp, #0 80064a6: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80064a8: 687b ldr r3, [r7, #4] 80064aa: f003 0307 and.w r3, r3, #7 80064ae: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80064b0: 4b0c ldr r3, [pc, #48] @ (80064e4 <__NVIC_SetPriorityGrouping+0x44>) 80064b2: 68db ldr r3, [r3, #12] 80064b4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80064b6: 68ba ldr r2, [r7, #8] 80064b8: f64f 03ff movw r3, #63743 @ 0xf8ff 80064bc: 4013 ands r3, r2 80064be: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80064c0: 68fb ldr r3, [r7, #12] 80064c2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80064c4: 68bb ldr r3, [r7, #8] 80064c6: 4313 orrs r3, r2 reg_value = (reg_value | 80064c8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80064cc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80064d0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80064d2: 4a04 ldr r2, [pc, #16] @ (80064e4 <__NVIC_SetPriorityGrouping+0x44>) 80064d4: 68bb ldr r3, [r7, #8] 80064d6: 60d3 str r3, [r2, #12] } 80064d8: bf00 nop 80064da: 3714 adds r7, #20 80064dc: 46bd mov sp, r7 80064de: f85d 7b04 ldr.w r7, [sp], #4 80064e2: 4770 bx lr 80064e4: e000ed00 .word 0xe000ed00 080064e8 <__NVIC_GetPriorityGrouping>: { 80064e8: b480 push {r7} 80064ea: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80064ec: 4b04 ldr r3, [pc, #16] @ (8006500 <__NVIC_GetPriorityGrouping+0x18>) 80064ee: 68db ldr r3, [r3, #12] 80064f0: 0a1b lsrs r3, r3, #8 80064f2: f003 0307 and.w r3, r3, #7 } 80064f6: 4618 mov r0, r3 80064f8: 46bd mov sp, r7 80064fa: f85d 7b04 ldr.w r7, [sp], #4 80064fe: 4770 bx lr 8006500: e000ed00 .word 0xe000ed00 08006504 <__NVIC_EnableIRQ>: { 8006504: b480 push {r7} 8006506: b083 sub sp, #12 8006508: af00 add r7, sp, #0 800650a: 4603 mov r3, r0 800650c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800650e: f997 3007 ldrsb.w r3, [r7, #7] 8006512: 2b00 cmp r3, #0 8006514: db0b blt.n 800652e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8006516: 79fb ldrb r3, [r7, #7] 8006518: f003 021f and.w r2, r3, #31 800651c: 4907 ldr r1, [pc, #28] @ (800653c <__NVIC_EnableIRQ+0x38>) 800651e: f997 3007 ldrsb.w r3, [r7, #7] 8006522: 095b lsrs r3, r3, #5 8006524: 2001 movs r0, #1 8006526: fa00 f202 lsl.w r2, r0, r2 800652a: f841 2023 str.w r2, [r1, r3, lsl #2] } 800652e: bf00 nop 8006530: 370c adds r7, #12 8006532: 46bd mov sp, r7 8006534: f85d 7b04 ldr.w r7, [sp], #4 8006538: 4770 bx lr 800653a: bf00 nop 800653c: e000e100 .word 0xe000e100 08006540 <__NVIC_DisableIRQ>: { 8006540: b480 push {r7} 8006542: b083 sub sp, #12 8006544: af00 add r7, sp, #0 8006546: 4603 mov r3, r0 8006548: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800654a: f997 3007 ldrsb.w r3, [r7, #7] 800654e: 2b00 cmp r3, #0 8006550: db12 blt.n 8006578 <__NVIC_DisableIRQ+0x38> NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8006552: 79fb ldrb r3, [r7, #7] 8006554: f003 021f and.w r2, r3, #31 8006558: 490a ldr r1, [pc, #40] @ (8006584 <__NVIC_DisableIRQ+0x44>) 800655a: f997 3007 ldrsb.w r3, [r7, #7] 800655e: 095b lsrs r3, r3, #5 8006560: 2001 movs r0, #1 8006562: fa00 f202 lsl.w r2, r0, r2 8006566: 3320 adds r3, #32 8006568: f841 2023 str.w r2, [r1, r3, lsl #2] __ASM volatile ("dsb 0xF":::"memory"); 800656c: f3bf 8f4f dsb sy } 8006570: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8006572: f3bf 8f6f isb sy } 8006576: bf00 nop } 8006578: bf00 nop 800657a: 370c adds r7, #12 800657c: 46bd mov sp, r7 800657e: f85d 7b04 ldr.w r7, [sp], #4 8006582: 4770 bx lr 8006584: e000e100 .word 0xe000e100 08006588 <__NVIC_SetPendingIRQ>: { 8006588: b480 push {r7} 800658a: b083 sub sp, #12 800658c: af00 add r7, sp, #0 800658e: 4603 mov r3, r0 8006590: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8006592: f997 3007 ldrsb.w r3, [r7, #7] 8006596: 2b00 cmp r3, #0 8006598: db0c blt.n 80065b4 <__NVIC_SetPendingIRQ+0x2c> NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800659a: 79fb ldrb r3, [r7, #7] 800659c: f003 021f and.w r2, r3, #31 80065a0: 4907 ldr r1, [pc, #28] @ (80065c0 <__NVIC_SetPendingIRQ+0x38>) 80065a2: f997 3007 ldrsb.w r3, [r7, #7] 80065a6: 095b lsrs r3, r3, #5 80065a8: 2001 movs r0, #1 80065aa: fa00 f202 lsl.w r2, r0, r2 80065ae: 3340 adds r3, #64 @ 0x40 80065b0: f841 2023 str.w r2, [r1, r3, lsl #2] } 80065b4: bf00 nop 80065b6: 370c adds r7, #12 80065b8: 46bd mov sp, r7 80065ba: f85d 7b04 ldr.w r7, [sp], #4 80065be: 4770 bx lr 80065c0: e000e100 .word 0xe000e100 080065c4 <__NVIC_ClearPendingIRQ>: { 80065c4: b480 push {r7} 80065c6: b083 sub sp, #12 80065c8: af00 add r7, sp, #0 80065ca: 4603 mov r3, r0 80065cc: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80065ce: f997 3007 ldrsb.w r3, [r7, #7] 80065d2: 2b00 cmp r3, #0 80065d4: db0c blt.n 80065f0 <__NVIC_ClearPendingIRQ+0x2c> NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80065d6: 79fb ldrb r3, [r7, #7] 80065d8: f003 021f and.w r2, r3, #31 80065dc: 4907 ldr r1, [pc, #28] @ (80065fc <__NVIC_ClearPendingIRQ+0x38>) 80065de: f997 3007 ldrsb.w r3, [r7, #7] 80065e2: 095b lsrs r3, r3, #5 80065e4: 2001 movs r0, #1 80065e6: fa00 f202 lsl.w r2, r0, r2 80065ea: 3360 adds r3, #96 @ 0x60 80065ec: f841 2023 str.w r2, [r1, r3, lsl #2] } 80065f0: bf00 nop 80065f2: 370c adds r7, #12 80065f4: 46bd mov sp, r7 80065f6: f85d 7b04 ldr.w r7, [sp], #4 80065fa: 4770 bx lr 80065fc: e000e100 .word 0xe000e100 08006600 <__NVIC_SetPriority>: { 8006600: b480 push {r7} 8006602: b083 sub sp, #12 8006604: af00 add r7, sp, #0 8006606: 4603 mov r3, r0 8006608: 6039 str r1, [r7, #0] 800660a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800660c: f997 3007 ldrsb.w r3, [r7, #7] 8006610: 2b00 cmp r3, #0 8006612: db0a blt.n 800662a <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8006614: 683b ldr r3, [r7, #0] 8006616: b2da uxtb r2, r3 8006618: 490c ldr r1, [pc, #48] @ (800664c <__NVIC_SetPriority+0x4c>) 800661a: f997 3007 ldrsb.w r3, [r7, #7] 800661e: 0112 lsls r2, r2, #4 8006620: b2d2 uxtb r2, r2 8006622: 440b add r3, r1 8006624: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8006628: e00a b.n 8006640 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800662a: 683b ldr r3, [r7, #0] 800662c: b2da uxtb r2, r3 800662e: 4908 ldr r1, [pc, #32] @ (8006650 <__NVIC_SetPriority+0x50>) 8006630: 79fb ldrb r3, [r7, #7] 8006632: f003 030f and.w r3, r3, #15 8006636: 3b04 subs r3, #4 8006638: 0112 lsls r2, r2, #4 800663a: b2d2 uxtb r2, r2 800663c: 440b add r3, r1 800663e: 761a strb r2, [r3, #24] } 8006640: bf00 nop 8006642: 370c adds r7, #12 8006644: 46bd mov sp, r7 8006646: f85d 7b04 ldr.w r7, [sp], #4 800664a: 4770 bx lr 800664c: e000e100 .word 0xe000e100 8006650: e000ed00 .word 0xe000ed00 08006654 : { 8006654: b480 push {r7} 8006656: b089 sub sp, #36 @ 0x24 8006658: af00 add r7, sp, #0 800665a: 60f8 str r0, [r7, #12] 800665c: 60b9 str r1, [r7, #8] 800665e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8006660: 68fb ldr r3, [r7, #12] 8006662: f003 0307 and.w r3, r3, #7 8006666: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8006668: 69fb ldr r3, [r7, #28] 800666a: f1c3 0307 rsb r3, r3, #7 800666e: 2b04 cmp r3, #4 8006670: bf28 it cs 8006672: 2304 movcs r3, #4 8006674: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8006676: 69fb ldr r3, [r7, #28] 8006678: 3304 adds r3, #4 800667a: 2b06 cmp r3, #6 800667c: d902 bls.n 8006684 800667e: 69fb ldr r3, [r7, #28] 8006680: 3b03 subs r3, #3 8006682: e000 b.n 8006686 8006684: 2300 movs r3, #0 8006686: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8006688: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800668c: 69bb ldr r3, [r7, #24] 800668e: fa02 f303 lsl.w r3, r2, r3 8006692: 43da mvns r2, r3 8006694: 68bb ldr r3, [r7, #8] 8006696: 401a ands r2, r3 8006698: 697b ldr r3, [r7, #20] 800669a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800669c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80066a0: 697b ldr r3, [r7, #20] 80066a2: fa01 f303 lsl.w r3, r1, r3 80066a6: 43d9 mvns r1, r3 80066a8: 687b ldr r3, [r7, #4] 80066aa: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80066ac: 4313 orrs r3, r2 } 80066ae: 4618 mov r0, r3 80066b0: 3724 adds r7, #36 @ 0x24 80066b2: 46bd mov sp, r7 80066b4: f85d 7b04 ldr.w r7, [sp], #4 80066b8: 4770 bx lr 080066ba : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80066ba: b580 push {r7, lr} 80066bc: b082 sub sp, #8 80066be: af00 add r7, sp, #0 80066c0: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80066c2: 6878 ldr r0, [r7, #4] 80066c4: f7ff feec bl 80064a0 <__NVIC_SetPriorityGrouping> } 80066c8: bf00 nop 80066ca: 3708 adds r7, #8 80066cc: 46bd mov sp, r7 80066ce: bd80 pop {r7, pc} 080066d0 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80066d0: b580 push {r7, lr} 80066d2: b086 sub sp, #24 80066d4: af00 add r7, sp, #0 80066d6: 4603 mov r3, r0 80066d8: 60b9 str r1, [r7, #8] 80066da: 607a str r2, [r7, #4] 80066dc: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80066de: f7ff ff03 bl 80064e8 <__NVIC_GetPriorityGrouping> 80066e2: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80066e4: 687a ldr r2, [r7, #4] 80066e6: 68b9 ldr r1, [r7, #8] 80066e8: 6978 ldr r0, [r7, #20] 80066ea: f7ff ffb3 bl 8006654 80066ee: 4602 mov r2, r0 80066f0: f997 300f ldrsb.w r3, [r7, #15] 80066f4: 4611 mov r1, r2 80066f6: 4618 mov r0, r3 80066f8: f7ff ff82 bl 8006600 <__NVIC_SetPriority> } 80066fc: bf00 nop 80066fe: 3718 adds r7, #24 8006700: 46bd mov sp, r7 8006702: bd80 pop {r7, pc} 08006704 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8006704: b580 push {r7, lr} 8006706: b082 sub sp, #8 8006708: af00 add r7, sp, #0 800670a: 4603 mov r3, r0 800670c: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800670e: f997 3007 ldrsb.w r3, [r7, #7] 8006712: 4618 mov r0, r3 8006714: f7ff fef6 bl 8006504 <__NVIC_EnableIRQ> } 8006718: bf00 nop 800671a: 3708 adds r7, #8 800671c: 46bd mov sp, r7 800671e: bd80 pop {r7, pc} 08006720 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { 8006720: b580 push {r7, lr} 8006722: b082 sub sp, #8 8006724: af00 add r7, sp, #0 8006726: 4603 mov r3, r0 8006728: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); 800672a: f997 3007 ldrsb.w r3, [r7, #7] 800672e: 4618 mov r0, r3 8006730: f7ff ff06 bl 8006540 <__NVIC_DisableIRQ> } 8006734: bf00 nop 8006736: 3708 adds r7, #8 8006738: 46bd mov sp, r7 800673a: bd80 pop {r7, pc} 0800673c : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { 800673c: b580 push {r7, lr} 800673e: b082 sub sp, #8 8006740: af00 add r7, sp, #0 8006742: 4603 mov r3, r0 8006744: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); 8006746: f997 3007 ldrsb.w r3, [r7, #7] 800674a: 4618 mov r0, r3 800674c: f7ff ff1c bl 8006588 <__NVIC_SetPendingIRQ> } 8006750: bf00 nop 8006752: 3708 adds r7, #8 8006754: 46bd mov sp, r7 8006756: bd80 pop {r7, pc} 08006758 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { 8006758: b580 push {r7, lr} 800675a: b082 sub sp, #8 800675c: af00 add r7, sp, #0 800675e: 4603 mov r3, r0 8006760: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); 8006762: f997 3007 ldrsb.w r3, [r7, #7] 8006766: 4618 mov r0, r3 8006768: f7ff ff2c bl 80065c4 <__NVIC_ClearPendingIRQ> } 800676c: bf00 nop 800676e: 3708 adds r7, #8 8006770: 46bd mov sp, r7 8006772: bd80 pop {r7, pc} 08006774 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8006774: b580 push {r7, lr} 8006776: b084 sub sp, #16 8006778: af00 add r7, sp, #0 800677a: 6078 str r0, [r7, #4] uint32_t tmp; /* Check the DMA handle allocation */ if (hdma == NULL) 800677c: 687b ldr r3, [r7, #4] 800677e: 2b00 cmp r3, #0 8006780: d101 bne.n 8006786 { return HAL_ERROR; 8006782: 2301 movs r3, #1 8006784: e08e b.n 80068a4 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); #if defined(DMA2) /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 8006786: 687b ldr r3, [r7, #4] 8006788: 681b ldr r3, [r3, #0] 800678a: 461a mov r2, r3 800678c: 4b47 ldr r3, [pc, #284] @ (80068ac ) 800678e: 429a cmp r2, r3 8006790: d80f bhi.n 80067b2 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8006792: 687b ldr r3, [r7, #4] 8006794: 681b ldr r3, [r3, #0] 8006796: 461a mov r2, r3 8006798: 4b45 ldr r3, [pc, #276] @ (80068b0 ) 800679a: 4413 add r3, r2 800679c: 4a45 ldr r2, [pc, #276] @ (80068b4 ) 800679e: fba2 2303 umull r2, r3, r2, r3 80067a2: 091b lsrs r3, r3, #4 80067a4: 009a lsls r2, r3, #2 80067a6: 687b ldr r3, [r7, #4] 80067a8: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA1; 80067aa: 687b ldr r3, [r7, #4] 80067ac: 4a42 ldr r2, [pc, #264] @ (80068b8 ) 80067ae: 641a str r2, [r3, #64] @ 0x40 80067b0: e00e b.n 80067d0 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; 80067b2: 687b ldr r3, [r7, #4] 80067b4: 681b ldr r3, [r3, #0] 80067b6: 461a mov r2, r3 80067b8: 4b40 ldr r3, [pc, #256] @ (80068bc ) 80067ba: 4413 add r3, r2 80067bc: 4a3d ldr r2, [pc, #244] @ (80068b4 ) 80067be: fba2 2303 umull r2, r3, r2, r3 80067c2: 091b lsrs r3, r3, #4 80067c4: 009a lsls r2, r3, #2 80067c6: 687b ldr r3, [r7, #4] 80067c8: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA2; 80067ca: 687b ldr r3, [r7, #4] 80067cc: 4a3c ldr r2, [pc, #240] @ (80068c0 ) 80067ce: 641a str r2, [r3, #64] @ 0x40 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80067d0: 687b ldr r3, [r7, #4] 80067d2: 2202 movs r2, #2 80067d4: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Get the CR register value */ tmp = hdma->Instance->CCR; 80067d8: 687b ldr r3, [r7, #4] 80067da: 681b ldr r3, [r3, #0] 80067dc: 681b ldr r3, [r3, #0] 80067de: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | 80067e0: 68fb ldr r3, [r7, #12] 80067e2: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 80067e6: f023 0370 bic.w r3, r3, #112 @ 0x70 80067ea: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 80067ec: 687b ldr r3, [r7, #4] 80067ee: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 80067f0: 687b ldr r3, [r7, #4] 80067f2: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Direction | 80067f4: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80067f6: 687b ldr r3, [r7, #4] 80067f8: 691b ldr r3, [r3, #16] 80067fa: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80067fc: 687b ldr r3, [r7, #4] 80067fe: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8006800: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8006802: 687b ldr r3, [r7, #4] 8006804: 699b ldr r3, [r3, #24] 8006806: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8006808: 687b ldr r3, [r7, #4] 800680a: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800680c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800680e: 687b ldr r3, [r7, #4] 8006810: 6a1b ldr r3, [r3, #32] 8006812: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 8006814: 68fa ldr r2, [r7, #12] 8006816: 4313 orrs r3, r2 8006818: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 800681a: 687b ldr r3, [r7, #4] 800681c: 681b ldr r3, [r3, #0] 800681e: 68fa ldr r2, [r7, #12] 8006820: 601a str r2, [r3, #0] /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8006822: 6878 ldr r0, [r7, #4] 8006824: f000 fa24 bl 8006c70 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8006828: 687b ldr r3, [r7, #4] 800682a: 689b ldr r3, [r3, #8] 800682c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8006830: d102 bne.n 8006838 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8006832: 687b ldr r3, [r7, #4] 8006834: 2200 movs r2, #0 8006836: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8006838: 687b ldr r3, [r7, #4] 800683a: 685a ldr r2, [r3, #4] 800683c: 687b ldr r3, [r7, #4] 800683e: 6c9b ldr r3, [r3, #72] @ 0x48 8006840: f002 023f and.w r2, r2, #63 @ 0x3f 8006844: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006846: 687b ldr r3, [r7, #4] 8006848: 6cdb ldr r3, [r3, #76] @ 0x4c 800684a: 687a ldr r2, [r7, #4] 800684c: 6d12 ldr r2, [r2, #80] @ 0x50 800684e: 605a str r2, [r3, #4] if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 8006850: 687b ldr r3, [r7, #4] 8006852: 685b ldr r3, [r3, #4] 8006854: 2b00 cmp r3, #0 8006856: d010 beq.n 800687a 8006858: 687b ldr r3, [r7, #4] 800685a: 685b ldr r3, [r3, #4] 800685c: 2b04 cmp r3, #4 800685e: d80c bhi.n 800687a { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8006860: 6878 ldr r0, [r7, #4] 8006862: f000 fa43 bl 8006cec /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; 8006866: 687b ldr r3, [r7, #4] 8006868: 6d5b ldr r3, [r3, #84] @ 0x54 800686a: 2200 movs r2, #0 800686c: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800686e: 687b ldr r3, [r7, #4] 8006870: 6d9b ldr r3, [r3, #88] @ 0x58 8006872: 687a ldr r2, [r7, #4] 8006874: 6dd2 ldr r2, [r2, #92] @ 0x5c 8006876: 605a str r2, [r3, #4] 8006878: e008 b.n 800688c } else { hdma->DMAmuxRequestGen = 0U; 800687a: 687b ldr r3, [r7, #4] 800687c: 2200 movs r2, #0 800687e: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = 0U; 8006880: 687b ldr r3, [r7, #4] 8006882: 2200 movs r2, #0 8006884: 659a str r2, [r3, #88] @ 0x58 hdma->DMAmuxRequestGenStatusMask = 0U; 8006886: 687b ldr r3, [r7, #4] 8006888: 2200 movs r2, #0 800688a: 65da str r2, [r3, #92] @ 0x5c } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800688c: 687b ldr r3, [r7, #4] 800688e: 2200 movs r2, #0 8006890: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8006892: 687b ldr r3, [r7, #4] 8006894: 2201 movs r2, #1 8006896: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 800689a: 687b ldr r3, [r7, #4] 800689c: 2200 movs r2, #0 800689e: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_OK; 80068a2: 2300 movs r3, #0 } 80068a4: 4618 mov r0, r3 80068a6: 3710 adds r7, #16 80068a8: 46bd mov sp, r7 80068aa: bd80 pop {r7, pc} 80068ac: 40020407 .word 0x40020407 80068b0: bffdfff8 .word 0xbffdfff8 80068b4: cccccccd .word 0xcccccccd 80068b8: 40020000 .word 0x40020000 80068bc: bffdfbf8 .word 0xbffdfbf8 80068c0: 40020400 .word 0x40020400 080068c4 : * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80068c4: b580 push {r7, lr} 80068c6: b086 sub sp, #24 80068c8: af00 add r7, sp, #0 80068ca: 60f8 str r0, [r7, #12] 80068cc: 60b9 str r1, [r7, #8] 80068ce: 607a str r2, [r7, #4] 80068d0: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80068d2: 2300 movs r3, #0 80068d4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 80068d6: 68fb ldr r3, [r7, #12] 80068d8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 80068dc: 2b01 cmp r3, #1 80068de: d101 bne.n 80068e4 80068e0: 2302 movs r3, #2 80068e2: e066 b.n 80069b2 80068e4: 68fb ldr r3, [r7, #12] 80068e6: 2201 movs r2, #1 80068e8: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (HAL_DMA_STATE_READY == hdma->State) 80068ec: 68fb ldr r3, [r7, #12] 80068ee: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80068f2: b2db uxtb r3, r3 80068f4: 2b01 cmp r3, #1 80068f6: d155 bne.n 80069a4 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80068f8: 68fb ldr r3, [r7, #12] 80068fa: 2202 movs r2, #2 80068fc: f883 2025 strb.w r2, [r3, #37] @ 0x25 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8006900: 68fb ldr r3, [r7, #12] 8006902: 2200 movs r2, #0 8006904: 63da str r2, [r3, #60] @ 0x3c /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8006906: 68fb ldr r3, [r7, #12] 8006908: 681b ldr r3, [r3, #0] 800690a: 681a ldr r2, [r3, #0] 800690c: 68fb ldr r3, [r7, #12] 800690e: 681b ldr r3, [r3, #0] 8006910: f022 0201 bic.w r2, r2, #1 8006914: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8006916: 683b ldr r3, [r7, #0] 8006918: 687a ldr r2, [r7, #4] 800691a: 68b9 ldr r1, [r7, #8] 800691c: 68f8 ldr r0, [r7, #12] 800691e: f000 f968 bl 8006bf2 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) 8006922: 68fb ldr r3, [r7, #12] 8006924: 6b1b ldr r3, [r3, #48] @ 0x30 8006926: 2b00 cmp r3, #0 8006928: d008 beq.n 800693c { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800692a: 68fb ldr r3, [r7, #12] 800692c: 681b ldr r3, [r3, #0] 800692e: 681a ldr r2, [r3, #0] 8006930: 68fb ldr r3, [r7, #12] 8006932: 681b ldr r3, [r3, #0] 8006934: f042 020e orr.w r2, r2, #14 8006938: 601a str r2, [r3, #0] 800693a: e00f b.n 800695c } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800693c: 68fb ldr r3, [r7, #12] 800693e: 681b ldr r3, [r3, #0] 8006940: 681a ldr r2, [r3, #0] 8006942: 68fb ldr r3, [r7, #12] 8006944: 681b ldr r3, [r3, #0] 8006946: f022 0204 bic.w r2, r2, #4 800694a: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 800694c: 68fb ldr r3, [r7, #12] 800694e: 681b ldr r3, [r3, #0] 8006950: 681a ldr r2, [r3, #0] 8006952: 68fb ldr r3, [r7, #12] 8006954: 681b ldr r3, [r3, #0] 8006956: f042 020a orr.w r2, r2, #10 800695a: 601a str r2, [r3, #0] } /* Check if DMAMUX Synchronization is enabled*/ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 800695c: 68fb ldr r3, [r7, #12] 800695e: 6c9b ldr r3, [r3, #72] @ 0x48 8006960: 681b ldr r3, [r3, #0] 8006962: f403 3380 and.w r3, r3, #65536 @ 0x10000 8006966: 2b00 cmp r3, #0 8006968: d007 beq.n 800697a { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 800696a: 68fb ldr r3, [r7, #12] 800696c: 6c9b ldr r3, [r3, #72] @ 0x48 800696e: 681a ldr r2, [r3, #0] 8006970: 68fb ldr r3, [r7, #12] 8006972: 6c9b ldr r3, [r3, #72] @ 0x48 8006974: f442 7280 orr.w r2, r2, #256 @ 0x100 8006978: 601a str r2, [r3, #0] } if (hdma->DMAmuxRequestGen != 0U) 800697a: 68fb ldr r3, [r7, #12] 800697c: 6d5b ldr r3, [r3, #84] @ 0x54 800697e: 2b00 cmp r3, #0 8006980: d007 beq.n 8006992 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8006982: 68fb ldr r3, [r7, #12] 8006984: 6d5b ldr r3, [r3, #84] @ 0x54 8006986: 681a ldr r2, [r3, #0] 8006988: 68fb ldr r3, [r7, #12] 800698a: 6d5b ldr r3, [r3, #84] @ 0x54 800698c: f442 7280 orr.w r2, r2, #256 @ 0x100 8006990: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8006992: 68fb ldr r3, [r7, #12] 8006994: 681b ldr r3, [r3, #0] 8006996: 681a ldr r2, [r3, #0] 8006998: 68fb ldr r3, [r7, #12] 800699a: 681b ldr r3, [r3, #0] 800699c: f042 0201 orr.w r2, r2, #1 80069a0: 601a str r2, [r3, #0] 80069a2: e005 b.n 80069b0 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 80069a4: 68fb ldr r3, [r7, #12] 80069a6: 2200 movs r2, #0 80069a8: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Remain BUSY */ status = HAL_BUSY; 80069ac: 2302 movs r3, #2 80069ae: 75fb strb r3, [r7, #23] } return status; 80069b0: 7dfb ldrb r3, [r7, #23] } 80069b2: 4618 mov r0, r3 80069b4: 3718 adds r7, #24 80069b6: 46bd mov sp, r7 80069b8: bd80 pop {r7, pc} 080069ba : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80069ba: b580 push {r7, lr} 80069bc: b084 sub sp, #16 80069be: af00 add r7, sp, #0 80069c0: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80069c2: 2300 movs r3, #0 80069c4: 73fb strb r3, [r7, #15] if (HAL_DMA_STATE_BUSY != hdma->State) 80069c6: 687b ldr r3, [r7, #4] 80069c8: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80069cc: b2db uxtb r3, r3 80069ce: 2b02 cmp r3, #2 80069d0: d005 beq.n 80069de { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80069d2: 687b ldr r3, [r7, #4] 80069d4: 2204 movs r2, #4 80069d6: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 80069d8: 2301 movs r3, #1 80069da: 73fb strb r3, [r7, #15] 80069dc: e047 b.n 8006a6e } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80069de: 687b ldr r3, [r7, #4] 80069e0: 681b ldr r3, [r3, #0] 80069e2: 681a ldr r2, [r3, #0] 80069e4: 687b ldr r3, [r7, #4] 80069e6: 681b ldr r3, [r3, #0] 80069e8: f022 020e bic.w r2, r2, #14 80069ec: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80069ee: 687b ldr r3, [r7, #4] 80069f0: 681b ldr r3, [r3, #0] 80069f2: 681a ldr r2, [r3, #0] 80069f4: 687b ldr r3, [r7, #4] 80069f6: 681b ldr r3, [r3, #0] 80069f8: f022 0201 bic.w r2, r2, #1 80069fc: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80069fe: 687b ldr r3, [r7, #4] 8006a00: 6c9b ldr r3, [r3, #72] @ 0x48 8006a02: 681a ldr r2, [r3, #0] 8006a04: 687b ldr r3, [r7, #4] 8006a06: 6c9b ldr r3, [r3, #72] @ 0x48 8006a08: f422 7280 bic.w r2, r2, #256 @ 0x100 8006a0c: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 8006a0e: 687b ldr r3, [r7, #4] 8006a10: 6c5b ldr r3, [r3, #68] @ 0x44 8006a12: f003 021c and.w r2, r3, #28 8006a16: 687b ldr r3, [r7, #4] 8006a18: 6c1b ldr r3, [r3, #64] @ 0x40 8006a1a: 2101 movs r1, #1 8006a1c: fa01 f202 lsl.w r2, r1, r2 8006a20: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006a22: 687b ldr r3, [r7, #4] 8006a24: 6cdb ldr r3, [r3, #76] @ 0x4c 8006a26: 687a ldr r2, [r7, #4] 8006a28: 6d12 ldr r2, [r2, #80] @ 0x50 8006a2a: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 8006a2c: 687b ldr r3, [r7, #4] 8006a2e: 6d5b ldr r3, [r3, #84] @ 0x54 8006a30: 2b00 cmp r3, #0 8006a32: d00c beq.n 8006a4e { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8006a34: 687b ldr r3, [r7, #4] 8006a36: 6d5b ldr r3, [r3, #84] @ 0x54 8006a38: 681a ldr r2, [r3, #0] 8006a3a: 687b ldr r3, [r7, #4] 8006a3c: 6d5b ldr r3, [r3, #84] @ 0x54 8006a3e: f422 7280 bic.w r2, r2, #256 @ 0x100 8006a42: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8006a44: 687b ldr r3, [r7, #4] 8006a46: 6d9b ldr r3, [r3, #88] @ 0x58 8006a48: 687a ldr r2, [r7, #4] 8006a4a: 6dd2 ldr r2, [r2, #92] @ 0x5c 8006a4c: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8006a4e: 687b ldr r3, [r7, #4] 8006a50: 2201 movs r2, #1 8006a52: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006a56: 687b ldr r3, [r7, #4] 8006a58: 2200 movs r2, #0 8006a5a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 8006a5e: 687b ldr r3, [r7, #4] 8006a60: 6b9b ldr r3, [r3, #56] @ 0x38 8006a62: 2b00 cmp r3, #0 8006a64: d003 beq.n 8006a6e { hdma->XferAbortCallback(hdma); 8006a66: 687b ldr r3, [r7, #4] 8006a68: 6b9b ldr r3, [r3, #56] @ 0x38 8006a6a: 6878 ldr r0, [r7, #4] 8006a6c: 4798 blx r3 } } return status; 8006a6e: 7bfb ldrb r3, [r7, #15] } 8006a70: 4618 mov r0, r3 8006a72: 3710 adds r7, #16 8006a74: 46bd mov sp, r7 8006a76: bd80 pop {r7, pc} 08006a78 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8006a78: b580 push {r7, lr} 8006a7a: b084 sub sp, #16 8006a7c: af00 add r7, sp, #0 8006a7e: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8006a80: 687b ldr r3, [r7, #4] 8006a82: 6c1b ldr r3, [r3, #64] @ 0x40 8006a84: 681b ldr r3, [r3, #0] 8006a86: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8006a88: 687b ldr r3, [r7, #4] 8006a8a: 681b ldr r3, [r3, #0] 8006a8c: 681b ldr r3, [r3, #0] 8006a8e: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) 8006a90: 687b ldr r3, [r7, #4] 8006a92: 6c5b ldr r3, [r3, #68] @ 0x44 8006a94: f003 031c and.w r3, r3, #28 8006a98: 2204 movs r2, #4 8006a9a: 409a lsls r2, r3 8006a9c: 68fb ldr r3, [r7, #12] 8006a9e: 4013 ands r3, r2 8006aa0: 2b00 cmp r3, #0 8006aa2: d026 beq.n 8006af2 8006aa4: 68bb ldr r3, [r7, #8] 8006aa6: f003 0304 and.w r3, r3, #4 8006aaa: 2b00 cmp r3, #0 8006aac: d021 beq.n 8006af2 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8006aae: 687b ldr r3, [r7, #4] 8006ab0: 681b ldr r3, [r3, #0] 8006ab2: 681b ldr r3, [r3, #0] 8006ab4: f003 0320 and.w r3, r3, #32 8006ab8: 2b00 cmp r3, #0 8006aba: d107 bne.n 8006acc { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8006abc: 687b ldr r3, [r7, #4] 8006abe: 681b ldr r3, [r3, #0] 8006ac0: 681a ldr r2, [r3, #0] 8006ac2: 687b ldr r3, [r7, #4] 8006ac4: 681b ldr r3, [r3, #0] 8006ac6: f022 0204 bic.w r2, r2, #4 8006aca: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU)); 8006acc: 687b ldr r3, [r7, #4] 8006ace: 6c5b ldr r3, [r3, #68] @ 0x44 8006ad0: f003 021c and.w r2, r3, #28 8006ad4: 687b ldr r3, [r7, #4] 8006ad6: 6c1b ldr r3, [r3, #64] @ 0x40 8006ad8: 2104 movs r1, #4 8006ada: fa01 f202 lsl.w r2, r1, r2 8006ade: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) 8006ae0: 687b ldr r3, [r7, #4] 8006ae2: 6b1b ldr r3, [r3, #48] @ 0x30 8006ae4: 2b00 cmp r3, #0 8006ae6: d071 beq.n 8006bcc { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8006ae8: 687b ldr r3, [r7, #4] 8006aea: 6b1b ldr r3, [r3, #48] @ 0x30 8006aec: 6878 ldr r0, [r7, #4] 8006aee: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) 8006af0: e06c b.n 8006bcc } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) 8006af2: 687b ldr r3, [r7, #4] 8006af4: 6c5b ldr r3, [r3, #68] @ 0x44 8006af6: f003 031c and.w r3, r3, #28 8006afa: 2202 movs r2, #2 8006afc: 409a lsls r2, r3 8006afe: 68fb ldr r3, [r7, #12] 8006b00: 4013 ands r3, r2 8006b02: 2b00 cmp r3, #0 8006b04: d02e beq.n 8006b64 8006b06: 68bb ldr r3, [r7, #8] 8006b08: f003 0302 and.w r3, r3, #2 8006b0c: 2b00 cmp r3, #0 8006b0e: d029 beq.n 8006b64 { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8006b10: 687b ldr r3, [r7, #4] 8006b12: 681b ldr r3, [r3, #0] 8006b14: 681b ldr r3, [r3, #0] 8006b16: f003 0320 and.w r3, r3, #32 8006b1a: 2b00 cmp r3, #0 8006b1c: d10b bne.n 8006b36 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8006b1e: 687b ldr r3, [r7, #4] 8006b20: 681b ldr r3, [r3, #0] 8006b22: 681a ldr r2, [r3, #0] 8006b24: 687b ldr r3, [r7, #4] 8006b26: 681b ldr r3, [r3, #0] 8006b28: f022 020a bic.w r2, r2, #10 8006b2c: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8006b2e: 687b ldr r3, [r7, #4] 8006b30: 2201 movs r2, #1 8006b32: f883 2025 strb.w r2, [r3, #37] @ 0x25 } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU)); 8006b36: 687b ldr r3, [r7, #4] 8006b38: 6c5b ldr r3, [r3, #68] @ 0x44 8006b3a: f003 021c and.w r2, r3, #28 8006b3e: 687b ldr r3, [r7, #4] 8006b40: 6c1b ldr r3, [r3, #64] @ 0x40 8006b42: 2102 movs r1, #2 8006b44: fa01 f202 lsl.w r2, r1, r2 8006b48: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006b4a: 687b ldr r3, [r7, #4] 8006b4c: 2200 movs r2, #0 8006b4e: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->XferCpltCallback != NULL) 8006b52: 687b ldr r3, [r7, #4] 8006b54: 6adb ldr r3, [r3, #44] @ 0x2c 8006b56: 2b00 cmp r3, #0 8006b58: d038 beq.n 8006bcc { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8006b5a: 687b ldr r3, [r7, #4] 8006b5c: 6adb ldr r3, [r3, #44] @ 0x2c 8006b5e: 6878 ldr r0, [r7, #4] 8006b60: 4798 blx r3 if (hdma->XferCpltCallback != NULL) 8006b62: e033 b.n 8006bcc } } /* Transfer Error Interrupt management **************************************/ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) 8006b64: 687b ldr r3, [r7, #4] 8006b66: 6c5b ldr r3, [r3, #68] @ 0x44 8006b68: f003 031c and.w r3, r3, #28 8006b6c: 2208 movs r2, #8 8006b6e: 409a lsls r2, r3 8006b70: 68fb ldr r3, [r7, #12] 8006b72: 4013 ands r3, r2 8006b74: 2b00 cmp r3, #0 8006b76: d02a beq.n 8006bce 8006b78: 68bb ldr r3, [r7, #8] 8006b7a: f003 0308 and.w r3, r3, #8 8006b7e: 2b00 cmp r3, #0 8006b80: d025 beq.n 8006bce { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8006b82: 687b ldr r3, [r7, #4] 8006b84: 681b ldr r3, [r3, #0] 8006b86: 681a ldr r2, [r3, #0] 8006b88: 687b ldr r3, [r7, #4] 8006b8a: 681b ldr r3, [r3, #0] 8006b8c: f022 020e bic.w r2, r2, #14 8006b90: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 8006b92: 687b ldr r3, [r7, #4] 8006b94: 6c5b ldr r3, [r3, #68] @ 0x44 8006b96: f003 021c and.w r2, r3, #28 8006b9a: 687b ldr r3, [r7, #4] 8006b9c: 6c1b ldr r3, [r3, #64] @ 0x40 8006b9e: 2101 movs r1, #1 8006ba0: fa01 f202 lsl.w r2, r1, r2 8006ba4: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8006ba6: 687b ldr r3, [r7, #4] 8006ba8: 2201 movs r2, #1 8006baa: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8006bac: 687b ldr r3, [r7, #4] 8006bae: 2201 movs r2, #1 8006bb0: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006bb4: 687b ldr r3, [r7, #4] 8006bb6: 2200 movs r2, #0 8006bb8: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->XferErrorCallback != NULL) 8006bbc: 687b ldr r3, [r7, #4] 8006bbe: 6b5b ldr r3, [r3, #52] @ 0x34 8006bc0: 2b00 cmp r3, #0 8006bc2: d004 beq.n 8006bce { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8006bc4: 687b ldr r3, [r7, #4] 8006bc6: 6b5b ldr r3, [r3, #52] @ 0x34 8006bc8: 6878 ldr r0, [r7, #4] 8006bca: 4798 blx r3 } else { /* Nothing To Do */ } return; 8006bcc: bf00 nop 8006bce: bf00 nop } 8006bd0: 3710 adds r7, #16 8006bd2: 46bd mov sp, r7 8006bd4: bd80 pop {r7, pc} 08006bd6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { 8006bd6: b480 push {r7} 8006bd8: b083 sub sp, #12 8006bda: af00 add r7, sp, #0 8006bdc: 6078 str r0, [r7, #4] /* Return DMA handle state */ return hdma->State; 8006bde: 687b ldr r3, [r7, #4] 8006be0: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8006be4: b2db uxtb r3, r3 } 8006be6: 4618 mov r0, r3 8006be8: 370c adds r7, #12 8006bea: 46bd mov sp, r7 8006bec: f85d 7b04 ldr.w r7, [sp], #4 8006bf0: 4770 bx lr 08006bf2 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8006bf2: b480 push {r7} 8006bf4: b085 sub sp, #20 8006bf6: af00 add r7, sp, #0 8006bf8: 60f8 str r0, [r7, #12] 8006bfa: 60b9 str r1, [r7, #8] 8006bfc: 607a str r2, [r7, #4] 8006bfe: 603b str r3, [r7, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006c00: 68fb ldr r3, [r7, #12] 8006c02: 6cdb ldr r3, [r3, #76] @ 0x4c 8006c04: 68fa ldr r2, [r7, #12] 8006c06: 6d12 ldr r2, [r2, #80] @ 0x50 8006c08: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 8006c0a: 68fb ldr r3, [r7, #12] 8006c0c: 6d5b ldr r3, [r3, #84] @ 0x54 8006c0e: 2b00 cmp r3, #0 8006c10: d004 beq.n 8006c1c { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8006c12: 68fb ldr r3, [r7, #12] 8006c14: 6d9b ldr r3, [r3, #88] @ 0x58 8006c16: 68fa ldr r2, [r7, #12] 8006c18: 6dd2 ldr r2, [r2, #92] @ 0x5c 8006c1a: 605a str r2, [r3, #4] } /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 8006c1c: 68fb ldr r3, [r7, #12] 8006c1e: 6c5b ldr r3, [r3, #68] @ 0x44 8006c20: f003 021c and.w r2, r3, #28 8006c24: 68fb ldr r3, [r7, #12] 8006c26: 6c1b ldr r3, [r3, #64] @ 0x40 8006c28: 2101 movs r1, #1 8006c2a: fa01 f202 lsl.w r2, r1, r2 8006c2e: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8006c30: 68fb ldr r3, [r7, #12] 8006c32: 681b ldr r3, [r3, #0] 8006c34: 683a ldr r2, [r7, #0] 8006c36: 605a str r2, [r3, #4] /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8006c38: 68fb ldr r3, [r7, #12] 8006c3a: 689b ldr r3, [r3, #8] 8006c3c: 2b10 cmp r3, #16 8006c3e: d108 bne.n 8006c52 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8006c40: 68fb ldr r3, [r7, #12] 8006c42: 681b ldr r3, [r3, #0] 8006c44: 687a ldr r2, [r7, #4] 8006c46: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8006c48: 68fb ldr r3, [r7, #12] 8006c4a: 681b ldr r3, [r3, #0] 8006c4c: 68ba ldr r2, [r7, #8] 8006c4e: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8006c50: e007 b.n 8006c62 hdma->Instance->CPAR = SrcAddress; 8006c52: 68fb ldr r3, [r7, #12] 8006c54: 681b ldr r3, [r3, #0] 8006c56: 68ba ldr r2, [r7, #8] 8006c58: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8006c5a: 68fb ldr r3, [r7, #12] 8006c5c: 681b ldr r3, [r3, #0] 8006c5e: 687a ldr r2, [r7, #4] 8006c60: 60da str r2, [r3, #12] } 8006c62: bf00 nop 8006c64: 3714 adds r7, #20 8006c66: 46bd mov sp, r7 8006c68: f85d 7b04 ldr.w r7, [sp], #4 8006c6c: 4770 bx lr ... 08006c70 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 8006c70: b480 push {r7} 8006c72: b085 sub sp, #20 8006c74: af00 add r7, sp, #0 8006c76: 6078 str r0, [r7, #4] uint32_t channel_number; /* check if instance is not outside the DMA channel range */ #if defined(DMA2) if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8006c78: 687b ldr r3, [r7, #4] 8006c7a: 681b ldr r3, [r3, #0] 8006c7c: 461a mov r2, r3 8006c7e: 4b17 ldr r3, [pc, #92] @ (8006cdc ) 8006c80: 429a cmp r2, r3 8006c82: d80a bhi.n 8006c9a { /* DMA1 */ hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); 8006c84: 687b ldr r3, [r7, #4] 8006c86: 6c5b ldr r3, [r3, #68] @ 0x44 8006c88: 089b lsrs r3, r3, #2 8006c8a: 009b lsls r3, r3, #2 8006c8c: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 8006c90: f503 3302 add.w r3, r3, #133120 @ 0x20800 8006c94: 687a ldr r2, [r7, #4] 8006c96: 6493 str r3, [r2, #72] @ 0x48 8006c98: e007 b.n 8006caa } else { /* DMA2 */ hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); 8006c9a: 687b ldr r3, [r7, #4] 8006c9c: 6c5b ldr r3, [r3, #68] @ 0x44 8006c9e: 089b lsrs r3, r3, #2 8006ca0: 009a lsls r2, r3, #2 8006ca2: 4b0f ldr r3, [pc, #60] @ (8006ce0 ) 8006ca4: 4413 add r3, r2 8006ca6: 687a ldr r2, [r7, #4] 8006ca8: 6493 str r3, [r2, #72] @ 0x48 } #else /* DMA1 */ hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); #endif /* DMA2 */ channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 8006caa: 687b ldr r3, [r7, #4] 8006cac: 681b ldr r3, [r3, #0] 8006cae: b2db uxtb r3, r3 8006cb0: 3b08 subs r3, #8 8006cb2: 4a0c ldr r2, [pc, #48] @ (8006ce4 ) 8006cb4: fba2 2303 umull r2, r3, r2, r3 8006cb8: 091b lsrs r3, r3, #4 8006cba: 60fb str r3, [r7, #12] hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8006cbc: 687b ldr r3, [r7, #4] 8006cbe: 4a0a ldr r2, [pc, #40] @ (8006ce8 ) 8006cc0: 64da str r2, [r3, #76] @ 0x4c /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 8006cc2: 68fb ldr r3, [r7, #12] 8006cc4: f003 031f and.w r3, r3, #31 8006cc8: 2201 movs r2, #1 8006cca: 409a lsls r2, r3 8006ccc: 687b ldr r3, [r7, #4] 8006cce: 651a str r2, [r3, #80] @ 0x50 } 8006cd0: bf00 nop 8006cd2: 3714 adds r7, #20 8006cd4: 46bd mov sp, r7 8006cd6: f85d 7b04 ldr.w r7, [sp], #4 8006cda: 4770 bx lr 8006cdc: 40020407 .word 0x40020407 8006ce0: 4002081c .word 0x4002081c 8006ce4: cccccccd .word 0xcccccccd 8006ce8: 40020880 .word 0x40020880 08006cec : * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 8006cec: b480 push {r7} 8006cee: b085 sub sp, #20 8006cf0: af00 add r7, sp, #0 8006cf2: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8006cf4: 687b ldr r3, [r7, #4] 8006cf6: 685b ldr r3, [r3, #4] 8006cf8: f003 033f and.w r3, r3, #63 @ 0x3f 8006cfc: 60fb str r3, [r7, #12] /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8006cfe: 68fa ldr r2, [r7, #12] 8006d00: 4b0b ldr r3, [pc, #44] @ (8006d30 ) 8006d02: 4413 add r3, r2 8006d04: 009b lsls r3, r3, #2 8006d06: 461a mov r2, r3 8006d08: 687b ldr r3, [r7, #4] 8006d0a: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8006d0c: 687b ldr r3, [r7, #4] 8006d0e: 4a09 ldr r2, [pc, #36] @ (8006d34 ) 8006d10: 659a str r2, [r3, #88] @ 0x58 /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); 8006d12: 68fb ldr r3, [r7, #12] 8006d14: 3b01 subs r3, #1 8006d16: f003 0303 and.w r3, r3, #3 8006d1a: 2201 movs r2, #1 8006d1c: 409a lsls r2, r3 8006d1e: 687b ldr r3, [r7, #4] 8006d20: 65da str r2, [r3, #92] @ 0x5c } 8006d22: bf00 nop 8006d24: 3714 adds r7, #20 8006d26: 46bd mov sp, r7 8006d28: f85d 7b04 ldr.w r7, [sp], #4 8006d2c: 4770 bx lr 8006d2e: bf00 nop 8006d30: 1000823f .word 0x1000823f 8006d34: 40020940 .word 0x40020940 08006d38 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { 8006d38: b480 push {r7} 8006d3a: b087 sub sp, #28 8006d3c: af00 add r7, sp, #0 8006d3e: 6078 str r0, [r7, #4] 8006d40: 6039 str r1, [r7, #0] uint32_t position = 0x00UL; 8006d42: 2300 movs r3, #0 8006d44: 617b str r3, [r7, #20] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8006d46: e14c b.n 8006fe2 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8006d48: 683b ldr r3, [r7, #0] 8006d4a: 681a ldr r2, [r3, #0] 8006d4c: 2101 movs r1, #1 8006d4e: 697b ldr r3, [r7, #20] 8006d50: fa01 f303 lsl.w r3, r1, r3 8006d54: 4013 ands r3, r2 8006d56: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8006d58: 68fb ldr r3, [r7, #12] 8006d5a: 2b00 cmp r3, #0 8006d5c: f000 813e beq.w 8006fdc { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8006d60: 683b ldr r3, [r7, #0] 8006d62: 685b ldr r3, [r3, #4] 8006d64: f003 0303 and.w r3, r3, #3 8006d68: 2b01 cmp r3, #1 8006d6a: d005 beq.n 8006d78 8006d6c: 683b ldr r3, [r7, #0] 8006d6e: 685b ldr r3, [r3, #4] 8006d70: f003 0303 and.w r3, r3, #3 8006d74: 2b02 cmp r3, #2 8006d76: d130 bne.n 8006dda { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8006d78: 687b ldr r3, [r7, #4] 8006d7a: 689b ldr r3, [r3, #8] 8006d7c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); 8006d7e: 697b ldr r3, [r7, #20] 8006d80: 005b lsls r3, r3, #1 8006d82: 2203 movs r2, #3 8006d84: fa02 f303 lsl.w r3, r2, r3 8006d88: 43db mvns r3, r3 8006d8a: 693a ldr r2, [r7, #16] 8006d8c: 4013 ands r3, r2 8006d8e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8006d90: 683b ldr r3, [r7, #0] 8006d92: 68da ldr r2, [r3, #12] 8006d94: 697b ldr r3, [r7, #20] 8006d96: 005b lsls r3, r3, #1 8006d98: fa02 f303 lsl.w r3, r2, r3 8006d9c: 693a ldr r2, [r7, #16] 8006d9e: 4313 orrs r3, r2 8006da0: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8006da2: 687b ldr r3, [r7, #4] 8006da4: 693a ldr r2, [r7, #16] 8006da6: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8006da8: 687b ldr r3, [r7, #4] 8006daa: 685b ldr r3, [r3, #4] 8006dac: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8006dae: 2201 movs r2, #1 8006db0: 697b ldr r3, [r7, #20] 8006db2: fa02 f303 lsl.w r3, r2, r3 8006db6: 43db mvns r3, r3 8006db8: 693a ldr r2, [r7, #16] 8006dba: 4013 ands r3, r2 8006dbc: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8006dbe: 683b ldr r3, [r7, #0] 8006dc0: 685b ldr r3, [r3, #4] 8006dc2: 091b lsrs r3, r3, #4 8006dc4: f003 0201 and.w r2, r3, #1 8006dc8: 697b ldr r3, [r7, #20] 8006dca: fa02 f303 lsl.w r3, r2, r3 8006dce: 693a ldr r2, [r7, #16] 8006dd0: 4313 orrs r3, r2 8006dd2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8006dd4: 687b ldr r3, [r7, #4] 8006dd6: 693a ldr r2, [r7, #16] 8006dd8: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8006dda: 683b ldr r3, [r7, #0] 8006ddc: 685b ldr r3, [r3, #4] 8006dde: f003 0303 and.w r3, r3, #3 8006de2: 2b03 cmp r3, #3 8006de4: d017 beq.n 8006e16 { temp = GPIOx->PUPDR; 8006de6: 687b ldr r3, [r7, #4] 8006de8: 68db ldr r3, [r3, #12] 8006dea: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8006dec: 697b ldr r3, [r7, #20] 8006dee: 005b lsls r3, r3, #1 8006df0: 2203 movs r2, #3 8006df2: fa02 f303 lsl.w r3, r2, r3 8006df6: 43db mvns r3, r3 8006df8: 693a ldr r2, [r7, #16] 8006dfa: 4013 ands r3, r2 8006dfc: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8006dfe: 683b ldr r3, [r7, #0] 8006e00: 689a ldr r2, [r3, #8] 8006e02: 697b ldr r3, [r7, #20] 8006e04: 005b lsls r3, r3, #1 8006e06: fa02 f303 lsl.w r3, r2, r3 8006e0a: 693a ldr r2, [r7, #16] 8006e0c: 4313 orrs r3, r2 8006e0e: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8006e10: 687b ldr r3, [r7, #4] 8006e12: 693a ldr r2, [r7, #16] 8006e14: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8006e16: 683b ldr r3, [r7, #0] 8006e18: 685b ldr r3, [r3, #4] 8006e1a: f003 0303 and.w r3, r3, #3 8006e1e: 2b02 cmp r3, #2 8006e20: d123 bne.n 8006e6a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8006e22: 697b ldr r3, [r7, #20] 8006e24: 08da lsrs r2, r3, #3 8006e26: 687b ldr r3, [r7, #4] 8006e28: 3208 adds r2, #8 8006e2a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8006e2e: 613b str r3, [r7, #16] temp &= ~(0xFUL << ((position & 0x07UL) * 4UL)); 8006e30: 697b ldr r3, [r7, #20] 8006e32: f003 0307 and.w r3, r3, #7 8006e36: 009b lsls r3, r3, #2 8006e38: 220f movs r2, #15 8006e3a: fa02 f303 lsl.w r3, r2, r3 8006e3e: 43db mvns r3, r3 8006e40: 693a ldr r2, [r7, #16] 8006e42: 4013 ands r3, r2 8006e44: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8006e46: 683b ldr r3, [r7, #0] 8006e48: 691a ldr r2, [r3, #16] 8006e4a: 697b ldr r3, [r7, #20] 8006e4c: f003 0307 and.w r3, r3, #7 8006e50: 009b lsls r3, r3, #2 8006e52: fa02 f303 lsl.w r3, r2, r3 8006e56: 693a ldr r2, [r7, #16] 8006e58: 4313 orrs r3, r2 8006e5a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8006e5c: 697b ldr r3, [r7, #20] 8006e5e: 08da lsrs r2, r3, #3 8006e60: 687b ldr r3, [r7, #4] 8006e62: 3208 adds r2, #8 8006e64: 6939 ldr r1, [r7, #16] 8006e66: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8006e6a: 687b ldr r3, [r7, #4] 8006e6c: 681b ldr r3, [r3, #0] 8006e6e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); 8006e70: 697b ldr r3, [r7, #20] 8006e72: 005b lsls r3, r3, #1 8006e74: 2203 movs r2, #3 8006e76: fa02 f303 lsl.w r3, r2, r3 8006e7a: 43db mvns r3, r3 8006e7c: 693a ldr r2, [r7, #16] 8006e7e: 4013 ands r3, r2 8006e80: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8006e82: 683b ldr r3, [r7, #0] 8006e84: 685b ldr r3, [r3, #4] 8006e86: f003 0203 and.w r2, r3, #3 8006e8a: 697b ldr r3, [r7, #20] 8006e8c: 005b lsls r3, r3, #1 8006e8e: fa02 f303 lsl.w r3, r2, r3 8006e92: 693a ldr r2, [r7, #16] 8006e94: 4313 orrs r3, r2 8006e96: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8006e98: 687b ldr r3, [r7, #4] 8006e9a: 693a ldr r2, [r7, #16] 8006e9c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8006e9e: 683b ldr r3, [r7, #0] 8006ea0: 685b ldr r3, [r3, #4] 8006ea2: f403 3340 and.w r3, r3, #196608 @ 0x30000 8006ea6: 2b00 cmp r3, #0 8006ea8: f000 8098 beq.w 8006fdc { temp = SYSCFG->EXTICR[position >> 2u]; 8006eac: 4a54 ldr r2, [pc, #336] @ (8007000 ) 8006eae: 697b ldr r3, [r7, #20] 8006eb0: 089b lsrs r3, r3, #2 8006eb2: 3302 adds r3, #2 8006eb4: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8006eb8: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 8006eba: 697b ldr r3, [r7, #20] 8006ebc: f003 0303 and.w r3, r3, #3 8006ec0: 009b lsls r3, r3, #2 8006ec2: 220f movs r2, #15 8006ec4: fa02 f303 lsl.w r3, r2, r3 8006ec8: 43db mvns r3, r3 8006eca: 693a ldr r2, [r7, #16] 8006ecc: 4013 ands r3, r2 8006ece: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 8006ed0: 687b ldr r3, [r7, #4] 8006ed2: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 8006ed6: d019 beq.n 8006f0c 8006ed8: 687b ldr r3, [r7, #4] 8006eda: 4a4a ldr r2, [pc, #296] @ (8007004 ) 8006edc: 4293 cmp r3, r2 8006ede: d013 beq.n 8006f08 8006ee0: 687b ldr r3, [r7, #4] 8006ee2: 4a49 ldr r2, [pc, #292] @ (8007008 ) 8006ee4: 4293 cmp r3, r2 8006ee6: d00d beq.n 8006f04 8006ee8: 687b ldr r3, [r7, #4] 8006eea: 4a48 ldr r2, [pc, #288] @ (800700c ) 8006eec: 4293 cmp r3, r2 8006eee: d007 beq.n 8006f00 8006ef0: 687b ldr r3, [r7, #4] 8006ef2: 4a47 ldr r2, [pc, #284] @ (8007010 ) 8006ef4: 4293 cmp r3, r2 8006ef6: d101 bne.n 8006efc 8006ef8: 2304 movs r3, #4 8006efa: e008 b.n 8006f0e 8006efc: 2307 movs r3, #7 8006efe: e006 b.n 8006f0e 8006f00: 2303 movs r3, #3 8006f02: e004 b.n 8006f0e 8006f04: 2302 movs r3, #2 8006f06: e002 b.n 8006f0e 8006f08: 2301 movs r3, #1 8006f0a: e000 b.n 8006f0e 8006f0c: 2300 movs r3, #0 8006f0e: 697a ldr r2, [r7, #20] 8006f10: f002 0203 and.w r2, r2, #3 8006f14: 0092 lsls r2, r2, #2 8006f16: 4093 lsls r3, r2 8006f18: 693a ldr r2, [r7, #16] 8006f1a: 4313 orrs r3, r2 8006f1c: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 8006f1e: 4938 ldr r1, [pc, #224] @ (8007000 ) 8006f20: 697b ldr r3, [r7, #20] 8006f22: 089b lsrs r3, r3, #2 8006f24: 3302 adds r3, #2 8006f26: 693a ldr r2, [r7, #16] 8006f28: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8006f2c: 4b39 ldr r3, [pc, #228] @ (8007014 ) 8006f2e: 681b ldr r3, [r3, #0] 8006f30: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8006f32: 68fb ldr r3, [r7, #12] 8006f34: 43db mvns r3, r3 8006f36: 693a ldr r2, [r7, #16] 8006f38: 4013 ands r3, r2 8006f3a: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8006f3c: 683b ldr r3, [r7, #0] 8006f3e: 685b ldr r3, [r3, #4] 8006f40: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8006f44: 2b00 cmp r3, #0 8006f46: d003 beq.n 8006f50 { temp |= iocurrent; 8006f48: 693a ldr r2, [r7, #16] 8006f4a: 68fb ldr r3, [r7, #12] 8006f4c: 4313 orrs r3, r2 8006f4e: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8006f50: 4a30 ldr r2, [pc, #192] @ (8007014 ) 8006f52: 693b ldr r3, [r7, #16] 8006f54: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 8006f56: 4b2f ldr r3, [pc, #188] @ (8007014 ) 8006f58: 685b ldr r3, [r3, #4] 8006f5a: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8006f5c: 68fb ldr r3, [r7, #12] 8006f5e: 43db mvns r3, r3 8006f60: 693a ldr r2, [r7, #16] 8006f62: 4013 ands r3, r2 8006f64: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8006f66: 683b ldr r3, [r7, #0] 8006f68: 685b ldr r3, [r3, #4] 8006f6a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8006f6e: 2b00 cmp r3, #0 8006f70: d003 beq.n 8006f7a { temp |= iocurrent; 8006f72: 693a ldr r2, [r7, #16] 8006f74: 68fb ldr r3, [r7, #12] 8006f76: 4313 orrs r3, r2 8006f78: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8006f7a: 4a26 ldr r2, [pc, #152] @ (8007014 ) 8006f7c: 693b ldr r3, [r7, #16] 8006f7e: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR1; 8006f80: 4b24 ldr r3, [pc, #144] @ (8007014 ) 8006f82: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8006f86: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8006f88: 68fb ldr r3, [r7, #12] 8006f8a: 43db mvns r3, r3 8006f8c: 693a ldr r2, [r7, #16] 8006f8e: 4013 ands r3, r2 8006f90: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8006f92: 683b ldr r3, [r7, #0] 8006f94: 685b ldr r3, [r3, #4] 8006f96: f403 3380 and.w r3, r3, #65536 @ 0x10000 8006f9a: 2b00 cmp r3, #0 8006f9c: d003 beq.n 8006fa6 { temp |= iocurrent; 8006f9e: 693a ldr r2, [r7, #16] 8006fa0: 68fb ldr r3, [r7, #12] 8006fa2: 4313 orrs r3, r2 8006fa4: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 8006fa6: 4a1b ldr r2, [pc, #108] @ (8007014 ) 8006fa8: 693b ldr r3, [r7, #16] 8006faa: f8c2 3080 str.w r3, [r2, #128] @ 0x80 temp = EXTI->EMR1; 8006fae: 4b19 ldr r3, [pc, #100] @ (8007014 ) 8006fb0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8006fb4: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8006fb6: 68fb ldr r3, [r7, #12] 8006fb8: 43db mvns r3, r3 8006fba: 693a ldr r2, [r7, #16] 8006fbc: 4013 ands r3, r2 8006fbe: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8006fc0: 683b ldr r3, [r7, #0] 8006fc2: 685b ldr r3, [r3, #4] 8006fc4: f403 3300 and.w r3, r3, #131072 @ 0x20000 8006fc8: 2b00 cmp r3, #0 8006fca: d003 beq.n 8006fd4 { temp |= iocurrent; 8006fcc: 693a ldr r2, [r7, #16] 8006fce: 68fb ldr r3, [r7, #12] 8006fd0: 4313 orrs r3, r2 8006fd2: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8006fd4: 4a0f ldr r2, [pc, #60] @ (8007014 ) 8006fd6: 693b ldr r3, [r7, #16] 8006fd8: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } } position++; 8006fdc: 697b ldr r3, [r7, #20] 8006fde: 3301 adds r3, #1 8006fe0: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8006fe2: 683b ldr r3, [r7, #0] 8006fe4: 681a ldr r2, [r3, #0] 8006fe6: 697b ldr r3, [r7, #20] 8006fe8: fa22 f303 lsr.w r3, r2, r3 8006fec: 2b00 cmp r3, #0 8006fee: f47f aeab bne.w 8006d48 } } 8006ff2: bf00 nop 8006ff4: bf00 nop 8006ff6: 371c adds r7, #28 8006ff8: 46bd mov sp, r7 8006ffa: f85d 7b04 ldr.w r7, [sp], #4 8006ffe: 4770 bx lr 8007000: 40010000 .word 0x40010000 8007004: 48000400 .word 0x48000400 8007008: 48000800 .word 0x48000800 800700c: 48000c00 .word 0x48000c00 8007010: 48001000 .word 0x48001000 8007014: 58000800 .word 0x58000800 08007018 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8007018: b480 push {r7} 800701a: b083 sub sp, #12 800701c: af00 add r7, sp, #0 800701e: 6078 str r0, [r7, #4] 8007020: 460b mov r3, r1 8007022: 807b strh r3, [r7, #2] 8007024: 4613 mov r3, r2 8007026: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8007028: 787b ldrb r3, [r7, #1] 800702a: 2b00 cmp r3, #0 800702c: d003 beq.n 8007036 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 800702e: 887a ldrh r2, [r7, #2] 8007030: 687b ldr r3, [r7, #4] 8007032: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8007034: e002 b.n 800703c GPIOx->BRR = (uint32_t)GPIO_Pin; 8007036: 887a ldrh r2, [r7, #2] 8007038: 687b ldr r3, [r7, #4] 800703a: 629a str r2, [r3, #40] @ 0x28 } 800703c: bf00 nop 800703e: 370c adds r7, #12 8007040: 46bd mov sp, r7 8007042: f85d 7b04 ldr.w r7, [sp], #4 8007046: 4770 bx lr 08007048 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8007048: b580 push {r7, lr} 800704a: b082 sub sp, #8 800704c: af00 add r7, sp, #0 800704e: 4603 mov r3, r0 8007050: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 8007052: 4b08 ldr r3, [pc, #32] @ (8007074 ) 8007054: 68da ldr r2, [r3, #12] 8007056: 88fb ldrh r3, [r7, #6] 8007058: 4013 ands r3, r2 800705a: 2b00 cmp r3, #0 800705c: d006 beq.n 800706c { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800705e: 4a05 ldr r2, [pc, #20] @ (8007074 ) 8007060: 88fb ldrh r3, [r7, #6] 8007062: 60d3 str r3, [r2, #12] HAL_GPIO_EXTI_Callback(GPIO_Pin); 8007064: 88fb ldrh r3, [r7, #6] 8007066: 4618 mov r0, r3 8007068: f7fe f990 bl 800538c } } 800706c: bf00 nop 800706e: 3708 adds r7, #8 8007070: 46bd mov sp, r7 8007072: bd80 pop {r7, pc} 8007074: 58000800 .word 0x58000800 08007078 : /** * @brief This function handles HSEM interrupt request * @retval None */ void HAL_HSEM_IRQHandler(void) { 8007078: b580 push {r7, lr} 800707a: b082 sub sp, #8 800707c: af00 add r7, sp, #0 uint32_t statusreg; /* Get the list of masked freed semaphores*/ statusreg = HSEM_COMMON->MISR; 800707e: 4b0a ldr r3, [pc, #40] @ (80070a8 ) 8007080: 68db ldr r3, [r3, #12] 8007082: 607b str r3, [r7, #4] /*Disable Interrupts*/ HSEM_COMMON->IER &= ~((uint32_t)statusreg); 8007084: 4b08 ldr r3, [pc, #32] @ (80070a8 ) 8007086: 681a ldr r2, [r3, #0] 8007088: 687b ldr r3, [r7, #4] 800708a: 43db mvns r3, r3 800708c: 4906 ldr r1, [pc, #24] @ (80070a8 ) 800708e: 4013 ands r3, r2 8007090: 600b str r3, [r1, #0] /*Clear Flags*/ HSEM_COMMON->ICR = ((uint32_t)statusreg); 8007092: 4a05 ldr r2, [pc, #20] @ (80070a8 ) 8007094: 687b ldr r3, [r7, #4] 8007096: 6053 str r3, [r2, #4] /* Call FreeCallback */ HAL_HSEM_FreeCallback(statusreg); 8007098: 6878 ldr r0, [r7, #4] 800709a: f000 f807 bl 80070ac } 800709e: bf00 nop 80070a0: 3708 adds r7, #8 80070a2: 46bd mov sp, r7 80070a4: bd80 pop {r7, pc} 80070a6: bf00 nop 80070a8: 58001500 .word 0x58001500 080070ac : * @brief Semaphore Released Callback. * @param SemMask: Mask of Released semaphores * @retval None */ __weak void HAL_HSEM_FreeCallback(uint32_t SemMask) { 80070ac: b480 push {r7} 80070ae: b083 sub sp, #12 80070b0: af00 add r7, sp, #0 80070b2: 6078 str r0, [r7, #4] UNUSED(SemMask); /* NOTE : This function should not be modified, when the callback is needed, the HAL_HSEM_FreeCallback can be implemented in the user file */ } 80070b4: bf00 nop 80070b6: 370c adds r7, #12 80070b8: 46bd mov sp, r7 80070ba: f85d 7b04 ldr.w r7, [sp], #4 80070be: 4770 bx lr 080070c0 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 80070c0: b580 push {r7, lr} 80070c2: b082 sub sp, #8 80070c4: af00 add r7, sp, #0 80070c6: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 80070c8: 687b ldr r3, [r7, #4] 80070ca: 2b00 cmp r3, #0 80070cc: d101 bne.n 80070d2 { return HAL_ERROR; 80070ce: 2301 movs r3, #1 80070d0: e08d b.n 80071ee assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 80070d2: 687b ldr r3, [r7, #4] 80070d4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80070d8: b2db uxtb r3, r3 80070da: 2b00 cmp r3, #0 80070dc: d106 bne.n 80070ec { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 80070de: 687b ldr r3, [r7, #4] 80070e0: 2200 movs r2, #0 80070e2: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 80070e6: 6878 ldr r0, [r7, #4] 80070e8: f7fe fd28 bl 8005b3c #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 80070ec: 687b ldr r3, [r7, #4] 80070ee: 2224 movs r2, #36 @ 0x24 80070f0: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80070f4: 687b ldr r3, [r7, #4] 80070f6: 681b ldr r3, [r3, #0] 80070f8: 681a ldr r2, [r3, #0] 80070fa: 687b ldr r3, [r7, #4] 80070fc: 681b ldr r3, [r3, #0] 80070fe: f022 0201 bic.w r2, r2, #1 8007102: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 8007104: 687b ldr r3, [r7, #4] 8007106: 685a ldr r2, [r3, #4] 8007108: 687b ldr r3, [r7, #4] 800710a: 681b ldr r3, [r3, #0] 800710c: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000 8007110: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 8007112: 687b ldr r3, [r7, #4] 8007114: 681b ldr r3, [r3, #0] 8007116: 689a ldr r2, [r3, #8] 8007118: 687b ldr r3, [r7, #4] 800711a: 681b ldr r3, [r3, #0] 800711c: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8007120: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 8007122: 687b ldr r3, [r7, #4] 8007124: 68db ldr r3, [r3, #12] 8007126: 2b01 cmp r3, #1 8007128: d107 bne.n 800713a { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 800712a: 687b ldr r3, [r7, #4] 800712c: 689a ldr r2, [r3, #8] 800712e: 687b ldr r3, [r7, #4] 8007130: 681b ldr r3, [r3, #0] 8007132: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8007136: 609a str r2, [r3, #8] 8007138: e006 b.n 8007148 } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 800713a: 687b ldr r3, [r7, #4] 800713c: 689a ldr r2, [r3, #8] 800713e: 687b ldr r3, [r7, #4] 8007140: 681b ldr r3, [r3, #0] 8007142: f442 4204 orr.w r2, r2, #33792 @ 0x8400 8007146: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8007148: 687b ldr r3, [r7, #4] 800714a: 68db ldr r3, [r3, #12] 800714c: 2b02 cmp r3, #2 800714e: d108 bne.n 8007162 { SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8007150: 687b ldr r3, [r7, #4] 8007152: 681b ldr r3, [r3, #0] 8007154: 685a ldr r2, [r3, #4] 8007156: 687b ldr r3, [r7, #4] 8007158: 681b ldr r3, [r3, #0] 800715a: f442 6200 orr.w r2, r2, #2048 @ 0x800 800715e: 605a str r2, [r3, #4] 8007160: e007 b.n 8007172 } else { /* Clear the I2C ADD10 bit */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8007162: 687b ldr r3, [r7, #4] 8007164: 681b ldr r3, [r3, #0] 8007166: 685a ldr r2, [r3, #4] 8007168: 687b ldr r3, [r7, #4] 800716a: 681b ldr r3, [r3, #0] 800716c: f422 6200 bic.w r2, r2, #2048 @ 0x800 8007170: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 8007172: 687b ldr r3, [r7, #4] 8007174: 681b ldr r3, [r3, #0] 8007176: 685b ldr r3, [r3, #4] 8007178: 687a ldr r2, [r7, #4] 800717a: 6812 ldr r2, [r2, #0] 800717c: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8007180: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8007184: 6053 str r3, [r2, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8007186: 687b ldr r3, [r7, #4] 8007188: 681b ldr r3, [r3, #0] 800718a: 68da ldr r2, [r3, #12] 800718c: 687b ldr r3, [r7, #4] 800718e: 681b ldr r3, [r3, #0] 8007190: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8007194: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8007196: 687b ldr r3, [r7, #4] 8007198: 691a ldr r2, [r3, #16] 800719a: 687b ldr r3, [r7, #4] 800719c: 695b ldr r3, [r3, #20] 800719e: ea42 0103 orr.w r1, r2, r3 (hi2c->Init.OwnAddress2Masks << 8)); 80071a2: 687b ldr r3, [r7, #4] 80071a4: 699b ldr r3, [r3, #24] 80071a6: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 80071a8: 687b ldr r3, [r7, #4] 80071aa: 681b ldr r3, [r3, #0] 80071ac: 430a orrs r2, r1 80071ae: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 80071b0: 687b ldr r3, [r7, #4] 80071b2: 69d9 ldr r1, [r3, #28] 80071b4: 687b ldr r3, [r7, #4] 80071b6: 6a1a ldr r2, [r3, #32] 80071b8: 687b ldr r3, [r7, #4] 80071ba: 681b ldr r3, [r3, #0] 80071bc: 430a orrs r2, r1 80071be: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 80071c0: 687b ldr r3, [r7, #4] 80071c2: 681b ldr r3, [r3, #0] 80071c4: 681a ldr r2, [r3, #0] 80071c6: 687b ldr r3, [r7, #4] 80071c8: 681b ldr r3, [r3, #0] 80071ca: f042 0201 orr.w r2, r2, #1 80071ce: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80071d0: 687b ldr r3, [r7, #4] 80071d2: 2200 movs r2, #0 80071d4: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 80071d6: 687b ldr r3, [r7, #4] 80071d8: 2220 movs r2, #32 80071da: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 80071de: 687b ldr r3, [r7, #4] 80071e0: 2200 movs r2, #0 80071e2: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 80071e4: 687b ldr r3, [r7, #4] 80071e6: 2200 movs r2, #0 80071e8: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_OK; 80071ec: 2300 movs r3, #0 } 80071ee: 4618 mov r0, r3 80071f0: 3708 adds r7, #8 80071f2: 46bd mov sp, r7 80071f4: bd80 pop {r7, pc} ... 080071f8 : * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { 80071f8: b580 push {r7, lr} 80071fa: b088 sub sp, #32 80071fc: af02 add r7, sp, #8 80071fe: 60f8 str r0, [r7, #12] 8007200: 4608 mov r0, r1 8007202: 4611 mov r1, r2 8007204: 461a mov r2, r3 8007206: 4603 mov r3, r0 8007208: 817b strh r3, [r7, #10] 800720a: 460b mov r3, r1 800720c: 813b strh r3, [r7, #8] 800720e: 4613 mov r3, r2 8007210: 80fb strh r3, [r7, #6] HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 8007212: 68fb ldr r3, [r7, #12] 8007214: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007218: b2db uxtb r3, r3 800721a: 2b20 cmp r3, #32 800721c: f040 80c3 bne.w 80073a6 { if ((pData == NULL) || (Size == 0U)) 8007220: 6a3b ldr r3, [r7, #32] 8007222: 2b00 cmp r3, #0 8007224: d002 beq.n 800722c 8007226: 8cbb ldrh r3, [r7, #36] @ 0x24 8007228: 2b00 cmp r3, #0 800722a: d105 bne.n 8007238 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 800722c: 68fb ldr r3, [r7, #12] 800722e: f44f 7200 mov.w r2, #512 @ 0x200 8007232: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 8007234: 2301 movs r3, #1 8007236: e0b7 b.n 80073a8 } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) 8007238: 68fb ldr r3, [r7, #12] 800723a: 681b ldr r3, [r3, #0] 800723c: 699b ldr r3, [r3, #24] 800723e: f403 4300 and.w r3, r3, #32768 @ 0x8000 8007242: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8007246: d101 bne.n 800724c { return HAL_BUSY; 8007248: 2302 movs r3, #2 800724a: e0ad b.n 80073a8 } /* Process Locked */ __HAL_LOCK(hi2c); 800724c: 68fb ldr r3, [r7, #12] 800724e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8007252: 2b01 cmp r3, #1 8007254: d101 bne.n 800725a 8007256: 2302 movs r3, #2 8007258: e0a6 b.n 80073a8 800725a: 68fb ldr r3, [r7, #12] 800725c: 2201 movs r2, #1 800725e: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY_TX; 8007262: 68fb ldr r3, [r7, #12] 8007264: 2221 movs r2, #33 @ 0x21 8007266: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_MEM; 800726a: 68fb ldr r3, [r7, #12] 800726c: 2240 movs r2, #64 @ 0x40 800726e: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8007272: 68fb ldr r3, [r7, #12] 8007274: 2200 movs r2, #0 8007276: 645a str r2, [r3, #68] @ 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8007278: 68fb ldr r3, [r7, #12] 800727a: 6a3a ldr r2, [r7, #32] 800727c: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 800727e: 68fb ldr r3, [r7, #12] 8007280: 8cba ldrh r2, [r7, #36] @ 0x24 8007282: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8007284: 68fb ldr r3, [r7, #12] 8007286: 4a4a ldr r2, [pc, #296] @ (80073b0 ) 8007288: 62da str r2, [r3, #44] @ 0x2c hi2c->XferISR = I2C_Mem_ISR_DMA; 800728a: 68fb ldr r3, [r7, #12] 800728c: 4a49 ldr r2, [pc, #292] @ (80073b4 ) 800728e: 635a str r2, [r3, #52] @ 0x34 hi2c->Devaddress = DevAddress; 8007290: 897a ldrh r2, [r7, #10] 8007292: 68fb ldr r3, [r7, #12] 8007294: 64da str r2, [r3, #76] @ 0x4c if (hi2c->XferCount > MAX_NBYTE_SIZE) 8007296: 68fb ldr r3, [r7, #12] 8007298: 8d5b ldrh r3, [r3, #42] @ 0x2a 800729a: b29b uxth r3, r3 800729c: 2bff cmp r3, #255 @ 0xff 800729e: d903 bls.n 80072a8 { hi2c->XferSize = MAX_NBYTE_SIZE; 80072a0: 68fb ldr r3, [r7, #12] 80072a2: 22ff movs r2, #255 @ 0xff 80072a4: 851a strh r2, [r3, #40] @ 0x28 80072a6: e004 b.n 80072b2 } else { hi2c->XferSize = hi2c->XferCount; 80072a8: 68fb ldr r3, [r7, #12] 80072aa: 8d5b ldrh r3, [r3, #42] @ 0x2a 80072ac: b29a uxth r2, r3 80072ae: 68fb ldr r3, [r7, #12] 80072b0: 851a strh r2, [r3, #40] @ 0x28 } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 80072b2: 88fb ldrh r3, [r7, #6] 80072b4: 2b01 cmp r3, #1 80072b6: d109 bne.n 80072cc { /* Prefetch Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 80072b8: 893b ldrh r3, [r7, #8] 80072ba: b2da uxtb r2, r3 80072bc: 68fb ldr r3, [r7, #12] 80072be: 681b ldr r3, [r3, #0] 80072c0: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 80072c2: 68fb ldr r3, [r7, #12] 80072c4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80072c8: 651a str r2, [r3, #80] @ 0x50 80072ca: e00b b.n 80072e4 } /* If Memory address size is 16Bit */ else { /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); 80072cc: 893b ldrh r3, [r7, #8] 80072ce: 0a1b lsrs r3, r3, #8 80072d0: b29b uxth r3, r3 80072d2: b2da uxtb r2, r3 80072d4: 68fb ldr r3, [r7, #12] 80072d6: 681b ldr r3, [r3, #0] 80072d8: 629a str r2, [r3, #40] @ 0x28 /* Prepare Memaddress buffer for LSB part */ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); 80072da: 893b ldrh r3, [r7, #8] 80072dc: b2db uxtb r3, r3 80072de: 461a mov r2, r3 80072e0: 68fb ldr r3, [r7, #12] 80072e2: 651a str r2, [r3, #80] @ 0x50 } if (hi2c->hdmatx != NULL) 80072e4: 68fb ldr r3, [r7, #12] 80072e6: 6b9b ldr r3, [r3, #56] @ 0x38 80072e8: 2b00 cmp r3, #0 80072ea: d020 beq.n 800732e { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; 80072ec: 68fb ldr r3, [r7, #12] 80072ee: 6b9b ldr r3, [r3, #56] @ 0x38 80072f0: 4a31 ldr r2, [pc, #196] @ (80073b8 ) 80072f2: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 80072f4: 68fb ldr r3, [r7, #12] 80072f6: 6b9b ldr r3, [r3, #56] @ 0x38 80072f8: 4a30 ldr r2, [pc, #192] @ (80073bc ) 80072fa: 635a str r2, [r3, #52] @ 0x34 /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; 80072fc: 68fb ldr r3, [r7, #12] 80072fe: 6b9b ldr r3, [r3, #56] @ 0x38 8007300: 2200 movs r2, #0 8007302: 631a str r2, [r3, #48] @ 0x30 hi2c->hdmatx->XferAbortCallback = NULL; 8007304: 68fb ldr r3, [r7, #12] 8007306: 6b9b ldr r3, [r3, #56] @ 0x38 8007308: 2200 movs r2, #0 800730a: 639a str r2, [r3, #56] @ 0x38 /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, 800730c: 68fb ldr r3, [r7, #12] 800730e: 6b98 ldr r0, [r3, #56] @ 0x38 8007310: 6a39 ldr r1, [r7, #32] 8007312: 68fb ldr r3, [r7, #12] 8007314: 681b ldr r3, [r3, #0] 8007316: 3328 adds r3, #40 @ 0x28 8007318: 461a mov r2, r3 hi2c->XferSize); 800731a: 68fb ldr r3, [r7, #12] 800731c: 8d1b ldrh r3, [r3, #40] @ 0x28 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, 800731e: f7ff fad1 bl 80068c4 8007322: 4603 mov r3, r0 8007324: 75fb strb r3, [r7, #23] __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) 8007326: 7dfb ldrb r3, [r7, #23] 8007328: 2b00 cmp r3, #0 800732a: d128 bne.n 800737e 800732c: e013 b.n 8007356 hi2c->State = HAL_I2C_STATE_READY; 800732e: 68fb ldr r3, [r7, #12] 8007330: 2220 movs r2, #32 8007332: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8007336: 68fb ldr r3, [r7, #12] 8007338: 2200 movs r2, #0 800733a: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 800733e: 68fb ldr r3, [r7, #12] 8007340: 6c5b ldr r3, [r3, #68] @ 0x44 8007342: f043 0280 orr.w r2, r3, #128 @ 0x80 8007346: 68fb ldr r3, [r7, #12] 8007348: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(hi2c); 800734a: 68fb ldr r3, [r7, #12] 800734c: 2200 movs r2, #0 800734e: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 8007352: 2301 movs r3, #1 8007354: e028 b.n 80073a8 { /* Send Slave Address and Memory Address */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 8007356: 88fb ldrh r3, [r7, #6] 8007358: b2da uxtb r2, r3 800735a: 8979 ldrh r1, [r7, #10] 800735c: 4b18 ldr r3, [pc, #96] @ (80073c0 ) 800735e: 9300 str r3, [sp, #0] 8007360: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8007364: 68f8 ldr r0, [r7, #12] 8007366: f001 fb9b bl 8008aa0 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800736a: 68fb ldr r3, [r7, #12] 800736c: 2200 movs r2, #0 800736e: f883 2040 strb.w r2, [r3, #64] @ 0x40 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); 8007372: 2101 movs r1, #1 8007374: 68f8 ldr r0, [r7, #12] 8007376: f001 fbc5 bl 8008b04 __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; 800737a: 2300 movs r3, #0 800737c: e014 b.n 80073a8 hi2c->State = HAL_I2C_STATE_READY; 800737e: 68fb ldr r3, [r7, #12] 8007380: 2220 movs r2, #32 8007382: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8007386: 68fb ldr r3, [r7, #12] 8007388: 2200 movs r2, #0 800738a: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 800738e: 68fb ldr r3, [r7, #12] 8007390: 6c5b ldr r3, [r3, #68] @ 0x44 8007392: f043 0210 orr.w r2, r3, #16 8007396: 68fb ldr r3, [r7, #12] 8007398: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(hi2c); 800739a: 68fb ldr r3, [r7, #12] 800739c: 2200 movs r2, #0 800739e: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 80073a2: 2301 movs r3, #1 80073a4: e000 b.n 80073a8 } else { return HAL_BUSY; 80073a6: 2302 movs r3, #2 } } 80073a8: 4618 mov r0, r3 80073aa: 3718 adds r7, #24 80073ac: 46bd mov sp, r7 80073ae: bd80 pop {r7, pc} 80073b0: ffff0000 .word 0xffff0000 80073b4: 08007b21 .word 0x08007b21 80073b8: 0800890b .word 0x0800890b 80073bc: 08008a37 .word 0x08008a37 80073c0: 80002000 .word 0x80002000 080073c4 : * @param Size Amount of data to be read * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { 80073c4: b580 push {r7, lr} 80073c6: b088 sub sp, #32 80073c8: af02 add r7, sp, #8 80073ca: 60f8 str r0, [r7, #12] 80073cc: 4608 mov r0, r1 80073ce: 4611 mov r1, r2 80073d0: 461a mov r2, r3 80073d2: 4603 mov r3, r0 80073d4: 817b strh r3, [r7, #10] 80073d6: 460b mov r3, r1 80073d8: 813b strh r3, [r7, #8] 80073da: 4613 mov r3, r2 80073dc: 80fb strh r3, [r7, #6] HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 80073de: 68fb ldr r3, [r7, #12] 80073e0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80073e4: b2db uxtb r3, r3 80073e6: 2b20 cmp r3, #32 80073e8: f040 80c2 bne.w 8007570 { if ((pData == NULL) || (Size == 0U)) 80073ec: 6a3b ldr r3, [r7, #32] 80073ee: 2b00 cmp r3, #0 80073f0: d002 beq.n 80073f8 80073f2: 8cbb ldrh r3, [r7, #36] @ 0x24 80073f4: 2b00 cmp r3, #0 80073f6: d105 bne.n 8007404 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 80073f8: 68fb ldr r3, [r7, #12] 80073fa: f44f 7200 mov.w r2, #512 @ 0x200 80073fe: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 8007400: 2301 movs r3, #1 8007402: e0b6 b.n 8007572 } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) 8007404: 68fb ldr r3, [r7, #12] 8007406: 681b ldr r3, [r3, #0] 8007408: 699b ldr r3, [r3, #24] 800740a: f403 4300 and.w r3, r3, #32768 @ 0x8000 800740e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8007412: d101 bne.n 8007418 { return HAL_BUSY; 8007414: 2302 movs r3, #2 8007416: e0ac b.n 8007572 } /* Process Locked */ __HAL_LOCK(hi2c); 8007418: 68fb ldr r3, [r7, #12] 800741a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800741e: 2b01 cmp r3, #1 8007420: d101 bne.n 8007426 8007422: 2302 movs r3, #2 8007424: e0a5 b.n 8007572 8007426: 68fb ldr r3, [r7, #12] 8007428: 2201 movs r2, #1 800742a: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY_RX; 800742e: 68fb ldr r3, [r7, #12] 8007430: 2222 movs r2, #34 @ 0x22 8007432: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_MEM; 8007436: 68fb ldr r3, [r7, #12] 8007438: 2240 movs r2, #64 @ 0x40 800743a: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800743e: 68fb ldr r3, [r7, #12] 8007440: 2200 movs r2, #0 8007442: 645a str r2, [r3, #68] @ 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8007444: 68fb ldr r3, [r7, #12] 8007446: 6a3a ldr r2, [r7, #32] 8007448: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 800744a: 68fb ldr r3, [r7, #12] 800744c: 8cba ldrh r2, [r7, #36] @ 0x24 800744e: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8007450: 68fb ldr r3, [r7, #12] 8007452: 4a4a ldr r2, [pc, #296] @ (800757c ) 8007454: 62da str r2, [r3, #44] @ 0x2c hi2c->XferISR = I2C_Mem_ISR_DMA; 8007456: 68fb ldr r3, [r7, #12] 8007458: 4a49 ldr r2, [pc, #292] @ (8007580 ) 800745a: 635a str r2, [r3, #52] @ 0x34 hi2c->Devaddress = DevAddress; 800745c: 897a ldrh r2, [r7, #10] 800745e: 68fb ldr r3, [r7, #12] 8007460: 64da str r2, [r3, #76] @ 0x4c if (hi2c->XferCount > MAX_NBYTE_SIZE) 8007462: 68fb ldr r3, [r7, #12] 8007464: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007466: b29b uxth r3, r3 8007468: 2bff cmp r3, #255 @ 0xff 800746a: d903 bls.n 8007474 { hi2c->XferSize = MAX_NBYTE_SIZE; 800746c: 68fb ldr r3, [r7, #12] 800746e: 22ff movs r2, #255 @ 0xff 8007470: 851a strh r2, [r3, #40] @ 0x28 8007472: e004 b.n 800747e } else { hi2c->XferSize = hi2c->XferCount; 8007474: 68fb ldr r3, [r7, #12] 8007476: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007478: b29a uxth r2, r3 800747a: 68fb ldr r3, [r7, #12] 800747c: 851a strh r2, [r3, #40] @ 0x28 } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 800747e: 88fb ldrh r3, [r7, #6] 8007480: 2b01 cmp r3, #1 8007482: d109 bne.n 8007498 { /* Prefetch Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8007484: 893b ldrh r3, [r7, #8] 8007486: b2da uxtb r2, r3 8007488: 68fb ldr r3, [r7, #12] 800748a: 681b ldr r3, [r3, #0] 800748c: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 800748e: 68fb ldr r3, [r7, #12] 8007490: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007494: 651a str r2, [r3, #80] @ 0x50 8007496: e00b b.n 80074b0 } /* If Memory address size is 16Bit */ else { /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); 8007498: 893b ldrh r3, [r7, #8] 800749a: 0a1b lsrs r3, r3, #8 800749c: b29b uxth r3, r3 800749e: b2da uxtb r2, r3 80074a0: 68fb ldr r3, [r7, #12] 80074a2: 681b ldr r3, [r3, #0] 80074a4: 629a str r2, [r3, #40] @ 0x28 /* Prepare Memaddress buffer for LSB part */ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); 80074a6: 893b ldrh r3, [r7, #8] 80074a8: b2db uxtb r3, r3 80074aa: 461a mov r2, r3 80074ac: 68fb ldr r3, [r7, #12] 80074ae: 651a str r2, [r3, #80] @ 0x50 } if (hi2c->hdmarx != NULL) 80074b0: 68fb ldr r3, [r7, #12] 80074b2: 6bdb ldr r3, [r3, #60] @ 0x3c 80074b4: 2b00 cmp r3, #0 80074b6: d020 beq.n 80074fa { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; 80074b8: 68fb ldr r3, [r7, #12] 80074ba: 6bdb ldr r3, [r3, #60] @ 0x3c 80074bc: 4a31 ldr r2, [pc, #196] @ (8007584 ) 80074be: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 80074c0: 68fb ldr r3, [r7, #12] 80074c2: 6bdb ldr r3, [r3, #60] @ 0x3c 80074c4: 4a30 ldr r2, [pc, #192] @ (8007588 ) 80074c6: 635a str r2, [r3, #52] @ 0x34 /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; 80074c8: 68fb ldr r3, [r7, #12] 80074ca: 6bdb ldr r3, [r3, #60] @ 0x3c 80074cc: 2200 movs r2, #0 80074ce: 631a str r2, [r3, #48] @ 0x30 hi2c->hdmarx->XferAbortCallback = NULL; 80074d0: 68fb ldr r3, [r7, #12] 80074d2: 6bdb ldr r3, [r3, #60] @ 0x3c 80074d4: 2200 movs r2, #0 80074d6: 639a str r2, [r3, #56] @ 0x38 /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, 80074d8: 68fb ldr r3, [r7, #12] 80074da: 6bd8 ldr r0, [r3, #60] @ 0x3c 80074dc: 68fb ldr r3, [r7, #12] 80074de: 681b ldr r3, [r3, #0] 80074e0: 3324 adds r3, #36 @ 0x24 80074e2: 4619 mov r1, r3 80074e4: 6a3a ldr r2, [r7, #32] hi2c->XferSize); 80074e6: 68fb ldr r3, [r7, #12] 80074e8: 8d1b ldrh r3, [r3, #40] @ 0x28 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, 80074ea: f7ff f9eb bl 80068c4 80074ee: 4603 mov r3, r0 80074f0: 75fb strb r3, [r7, #23] __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) 80074f2: 7dfb ldrb r3, [r7, #23] 80074f4: 2b00 cmp r3, #0 80074f6: d127 bne.n 8007548 80074f8: e013 b.n 8007522 hi2c->State = HAL_I2C_STATE_READY; 80074fa: 68fb ldr r3, [r7, #12] 80074fc: 2220 movs r2, #32 80074fe: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8007502: 68fb ldr r3, [r7, #12] 8007504: 2200 movs r2, #0 8007506: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 800750a: 68fb ldr r3, [r7, #12] 800750c: 6c5b ldr r3, [r3, #68] @ 0x44 800750e: f043 0280 orr.w r2, r3, #128 @ 0x80 8007512: 68fb ldr r3, [r7, #12] 8007514: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(hi2c); 8007516: 68fb ldr r3, [r7, #12] 8007518: 2200 movs r2, #0 800751a: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 800751e: 2301 movs r3, #1 8007520: e027 b.n 8007572 { /* Send Slave Address and Memory Address */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 8007522: 88fb ldrh r3, [r7, #6] 8007524: b2da uxtb r2, r3 8007526: 8979 ldrh r1, [r7, #10] 8007528: 4b18 ldr r3, [pc, #96] @ (800758c ) 800752a: 9300 str r3, [sp, #0] 800752c: 2300 movs r3, #0 800752e: 68f8 ldr r0, [r7, #12] 8007530: f001 fab6 bl 8008aa0 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007534: 68fb ldr r3, [r7, #12] 8007536: 2200 movs r2, #0 8007538: f883 2040 strb.w r2, [r3, #64] @ 0x40 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); 800753c: 2101 movs r1, #1 800753e: 68f8 ldr r0, [r7, #12] 8007540: f001 fae0 bl 8008b04 __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; 8007544: 2300 movs r3, #0 8007546: e014 b.n 8007572 hi2c->State = HAL_I2C_STATE_READY; 8007548: 68fb ldr r3, [r7, #12] 800754a: 2220 movs r2, #32 800754c: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8007550: 68fb ldr r3, [r7, #12] 8007552: 2200 movs r2, #0 8007554: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 8007558: 68fb ldr r3, [r7, #12] 800755a: 6c5b ldr r3, [r3, #68] @ 0x44 800755c: f043 0210 orr.w r2, r3, #16 8007560: 68fb ldr r3, [r7, #12] 8007562: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(hi2c); 8007564: 68fb ldr r3, [r7, #12] 8007566: 2200 movs r2, #0 8007568: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 800756c: 2301 movs r3, #1 800756e: e000 b.n 8007572 } else { return HAL_BUSY; 8007570: 2302 movs r3, #2 } } 8007572: 4618 mov r0, r3 8007574: 3718 adds r7, #24 8007576: 46bd mov sp, r7 8007578: bd80 pop {r7, pc} 800757a: bf00 nop 800757c: ffff0000 .word 0xffff0000 8007580: 08007b21 .word 0x08007b21 8007584: 080089a1 .word 0x080089a1 8007588: 08008a37 .word 0x08008a37 800758c: 80002000 .word 0x80002000 08007590 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { 8007590: b580 push {r7, lr} 8007592: b084 sub sp, #16 8007594: af00 add r7, sp, #0 8007596: 6078 str r0, [r7, #4] /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8007598: 687b ldr r3, [r7, #4] 800759a: 681b ldr r3, [r3, #0] 800759c: 699b ldr r3, [r3, #24] 800759e: 60fb str r3, [r7, #12] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 80075a0: 687b ldr r3, [r7, #4] 80075a2: 681b ldr r3, [r3, #0] 80075a4: 681b ldr r3, [r3, #0] 80075a6: 60bb str r3, [r7, #8] /* I2C events treatment -------------------------------------*/ if (hi2c->XferISR != NULL) 80075a8: 687b ldr r3, [r7, #4] 80075aa: 6b5b ldr r3, [r3, #52] @ 0x34 80075ac: 2b00 cmp r3, #0 80075ae: d005 beq.n 80075bc { hi2c->XferISR(hi2c, itflags, itsources); 80075b0: 687b ldr r3, [r7, #4] 80075b2: 6b5b ldr r3, [r3, #52] @ 0x34 80075b4: 68ba ldr r2, [r7, #8] 80075b6: 68f9 ldr r1, [r7, #12] 80075b8: 6878 ldr r0, [r7, #4] 80075ba: 4798 blx r3 } } 80075bc: bf00 nop 80075be: 3710 adds r7, #16 80075c0: 46bd mov sp, r7 80075c2: bd80 pop {r7, pc} 080075c4 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { 80075c4: b580 push {r7, lr} 80075c6: b086 sub sp, #24 80075c8: af00 add r7, sp, #0 80075ca: 6078 str r0, [r7, #4] uint32_t itflags = READ_REG(hi2c->Instance->ISR); 80075cc: 687b ldr r3, [r7, #4] 80075ce: 681b ldr r3, [r3, #0] 80075d0: 699b ldr r3, [r3, #24] 80075d2: 617b str r3, [r7, #20] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 80075d4: 687b ldr r3, [r7, #4] 80075d6: 681b ldr r3, [r3, #0] 80075d8: 681b ldr r3, [r3, #0] 80075da: 613b str r3, [r7, #16] uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 80075dc: 697b ldr r3, [r7, #20] 80075de: 0a1b lsrs r3, r3, #8 80075e0: f003 0301 and.w r3, r3, #1 80075e4: 2b00 cmp r3, #0 80075e6: d010 beq.n 800760a (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 80075e8: 693b ldr r3, [r7, #16] 80075ea: 09db lsrs r3, r3, #7 80075ec: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 80075f0: 2b00 cmp r3, #0 80075f2: d00a beq.n 800760a { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; 80075f4: 687b ldr r3, [r7, #4] 80075f6: 6c5b ldr r3, [r3, #68] @ 0x44 80075f8: f043 0201 orr.w r2, r3, #1 80075fc: 687b ldr r3, [r7, #4] 80075fe: 645a str r2, [r3, #68] @ 0x44 /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 8007600: 687b ldr r3, [r7, #4] 8007602: 681b ldr r3, [r3, #0] 8007604: f44f 7280 mov.w r2, #256 @ 0x100 8007608: 61da str r2, [r3, #28] } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 800760a: 697b ldr r3, [r7, #20] 800760c: 0a9b lsrs r3, r3, #10 800760e: f003 0301 and.w r3, r3, #1 8007612: 2b00 cmp r3, #0 8007614: d010 beq.n 8007638 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8007616: 693b ldr r3, [r7, #16] 8007618: 09db lsrs r3, r3, #7 800761a: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 800761e: 2b00 cmp r3, #0 8007620: d00a beq.n 8007638 { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; 8007622: 687b ldr r3, [r7, #4] 8007624: 6c5b ldr r3, [r3, #68] @ 0x44 8007626: f043 0208 orr.w r2, r3, #8 800762a: 687b ldr r3, [r7, #4] 800762c: 645a str r2, [r3, #68] @ 0x44 /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 800762e: 687b ldr r3, [r7, #4] 8007630: 681b ldr r3, [r3, #0] 8007632: f44f 6280 mov.w r2, #1024 @ 0x400 8007636: 61da str r2, [r3, #28] } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 8007638: 697b ldr r3, [r7, #20] 800763a: 0a5b lsrs r3, r3, #9 800763c: f003 0301 and.w r3, r3, #1 8007640: 2b00 cmp r3, #0 8007642: d010 beq.n 8007666 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8007644: 693b ldr r3, [r7, #16] 8007646: 09db lsrs r3, r3, #7 8007648: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 800764c: 2b00 cmp r3, #0 800764e: d00a beq.n 8007666 { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; 8007650: 687b ldr r3, [r7, #4] 8007652: 6c5b ldr r3, [r3, #68] @ 0x44 8007654: f043 0202 orr.w r2, r3, #2 8007658: 687b ldr r3, [r7, #4] 800765a: 645a str r2, [r3, #68] @ 0x44 /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 800765c: 687b ldr r3, [r7, #4] 800765e: 681b ldr r3, [r3, #0] 8007660: f44f 7200 mov.w r2, #512 @ 0x200 8007664: 61da str r2, [r3, #28] } /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 8007666: 687b ldr r3, [r7, #4] 8007668: 6c5b ldr r3, [r3, #68] @ 0x44 800766a: 60fb str r3, [r7, #12] /* Call the Error Callback in case of Error detected */ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) 800766c: 68fb ldr r3, [r7, #12] 800766e: f003 030b and.w r3, r3, #11 8007672: 2b00 cmp r3, #0 8007674: d003 beq.n 800767e { I2C_ITError(hi2c, tmperror); 8007676: 68f9 ldr r1, [r7, #12] 8007678: 6878 ldr r0, [r7, #4] 800767a: f001 f80b bl 8008694 } } 800767e: bf00 nop 8007680: 3718 adds r7, #24 8007682: 46bd mov sp, r7 8007684: bd80 pop {r7, pc} 08007686 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { 8007686: b480 push {r7} 8007688: b083 sub sp, #12 800768a: af00 add r7, sp, #0 800768c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterTxCpltCallback could be implemented in the user file */ } 800768e: bf00 nop 8007690: 370c adds r7, #12 8007692: 46bd mov sp, r7 8007694: f85d 7b04 ldr.w r7, [sp], #4 8007698: 4770 bx lr 0800769a : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { 800769a: b480 push {r7} 800769c: b083 sub sp, #12 800769e: af00 add r7, sp, #0 80076a0: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } 80076a2: bf00 nop 80076a4: 370c adds r7, #12 80076a6: 46bd mov sp, r7 80076a8: f85d 7b04 ldr.w r7, [sp], #4 80076ac: 4770 bx lr 080076ae : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { 80076ae: b480 push {r7} 80076b0: b083 sub sp, #12 80076b2: af00 add r7, sp, #0 80076b4: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file */ } 80076b6: bf00 nop 80076b8: 370c adds r7, #12 80076ba: 46bd mov sp, r7 80076bc: f85d 7b04 ldr.w r7, [sp], #4 80076c0: 4770 bx lr 080076c2 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { 80076c2: b480 push {r7} 80076c4: b083 sub sp, #12 80076c6: af00 add r7, sp, #0 80076c8: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file */ } 80076ca: bf00 nop 80076cc: 370c adds r7, #12 80076ce: 46bd mov sp, r7 80076d0: f85d 7b04 ldr.w r7, [sp], #4 80076d4: 4770 bx lr 080076d6 : * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { 80076d6: b480 push {r7} 80076d8: b083 sub sp, #12 80076da: af00 add r7, sp, #0 80076dc: 6078 str r0, [r7, #4] 80076de: 460b mov r3, r1 80076e0: 70fb strb r3, [r7, #3] 80076e2: 4613 mov r3, r2 80076e4: 803b strh r3, [r7, #0] UNUSED(AddrMatchCode); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AddrCallback() could be implemented in the user file */ } 80076e6: bf00 nop 80076e8: 370c adds r7, #12 80076ea: 46bd mov sp, r7 80076ec: f85d 7b04 ldr.w r7, [sp], #4 80076f0: 4770 bx lr 080076f2 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { 80076f2: b480 push {r7} 80076f4: b083 sub sp, #12 80076f6: af00 add r7, sp, #0 80076f8: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ListenCpltCallback() could be implemented in the user file */ } 80076fa: bf00 nop 80076fc: 370c adds r7, #12 80076fe: 46bd mov sp, r7 8007700: f85d 7b04 ldr.w r7, [sp], #4 8007704: 4770 bx lr 08007706 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) { 8007706: b480 push {r7} 8007708: b083 sub sp, #12 800770a: af00 add r7, sp, #0 800770c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AbortCpltCallback could be implemented in the user file */ } 800770e: bf00 nop 8007710: 370c adds r7, #12 8007712: 46bd mov sp, r7 8007714: f85d 7b04 ldr.w r7, [sp], #4 8007718: 4770 bx lr 0800771a : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval I2C Error Code */ uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) { 800771a: b480 push {r7} 800771c: b083 sub sp, #12 800771e: af00 add r7, sp, #0 8007720: 6078 str r0, [r7, #4] return hi2c->ErrorCode; 8007722: 687b ldr r3, [r7, #4] 8007724: 6c5b ldr r3, [r3, #68] @ 0x44 } 8007726: 4618 mov r0, r3 8007728: 370c adds r7, #12 800772a: 46bd mov sp, r7 800772c: f85d 7b04 ldr.w r7, [sp], #4 8007730: 4770 bx lr 08007732 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8007732: b580 push {r7, lr} 8007734: b086 sub sp, #24 8007736: af00 add r7, sp, #0 8007738: 60f8 str r0, [r7, #12] 800773a: 60b9 str r1, [r7, #8] 800773c: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 800773e: 68fb ldr r3, [r7, #12] 8007740: 6adb ldr r3, [r3, #44] @ 0x2c 8007742: 617b str r3, [r7, #20] uint32_t tmpITFlags = ITFlags; 8007744: 68bb ldr r3, [r7, #8] 8007746: 613b str r3, [r7, #16] /* Process locked */ __HAL_LOCK(hi2c); 8007748: 68fb ldr r3, [r7, #12] 800774a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800774e: 2b01 cmp r3, #1 8007750: d101 bne.n 8007756 8007752: 2302 movs r3, #2 8007754: e0ed b.n 8007932 8007756: 68fb ldr r3, [r7, #12] 8007758: 2201 movs r2, #1 800775a: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 800775e: 693b ldr r3, [r7, #16] 8007760: 095b lsrs r3, r3, #5 8007762: f003 0301 and.w r3, r3, #1 8007766: 2b00 cmp r3, #0 8007768: d00a beq.n 8007780 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 800776a: 687b ldr r3, [r7, #4] 800776c: 095b lsrs r3, r3, #5 800776e: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007772: 2b00 cmp r3, #0 8007774: d004 beq.n 8007780 { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); 8007776: 6939 ldr r1, [r7, #16] 8007778: 68f8 ldr r0, [r7, #12] 800777a: f000 fdcb bl 8008314 800777e: e0d3 b.n 8007928 } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8007780: 693b ldr r3, [r7, #16] 8007782: 091b lsrs r3, r3, #4 8007784: f003 0301 and.w r3, r3, #1 8007788: 2b00 cmp r3, #0 800778a: d04d beq.n 8007828 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 800778c: 687b ldr r3, [r7, #4] 800778e: 091b lsrs r3, r3, #4 8007790: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8007794: 2b00 cmp r3, #0 8007796: d047 beq.n 8007828 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 8007798: 68fb ldr r3, [r7, #12] 800779a: 8d5b ldrh r3, [r3, #42] @ 0x2a 800779c: b29b uxth r3, r3 800779e: 2b00 cmp r3, #0 80077a0: d128 bne.n 80077f4 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 80077a2: 68fb ldr r3, [r7, #12] 80077a4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80077a8: b2db uxtb r3, r3 80077aa: 2b28 cmp r3, #40 @ 0x28 80077ac: d108 bne.n 80077c0 80077ae: 697b ldr r3, [r7, #20] 80077b0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80077b4: d104 bne.n 80077c0 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 80077b6: 6939 ldr r1, [r7, #16] 80077b8: 68f8 ldr r0, [r7, #12] 80077ba: f000 ff15 bl 80085e8 80077be: e032 b.n 8007826 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 80077c0: 68fb ldr r3, [r7, #12] 80077c2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80077c6: b2db uxtb r3, r3 80077c8: 2b29 cmp r3, #41 @ 0x29 80077ca: d10e bne.n 80077ea 80077cc: 697b ldr r3, [r7, #20] 80077ce: f513 3f80 cmn.w r3, #65536 @ 0x10000 80077d2: d00a beq.n 80077ea { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80077d4: 68fb ldr r3, [r7, #12] 80077d6: 681b ldr r3, [r3, #0] 80077d8: 2210 movs r2, #16 80077da: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80077dc: 68f8 ldr r0, [r7, #12] 80077de: f001 f870 bl 80088c2 /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 80077e2: 68f8 ldr r0, [r7, #12] 80077e4: f000 fc6e bl 80080c4 80077e8: e01d b.n 8007826 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80077ea: 68fb ldr r3, [r7, #12] 80077ec: 681b ldr r3, [r3, #0] 80077ee: 2210 movs r2, #16 80077f0: 61da str r2, [r3, #28] if (hi2c->XferCount == 0U) 80077f2: e096 b.n 8007922 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80077f4: 68fb ldr r3, [r7, #12] 80077f6: 681b ldr r3, [r3, #0] 80077f8: 2210 movs r2, #16 80077fa: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80077fc: 68fb ldr r3, [r7, #12] 80077fe: 6c5b ldr r3, [r3, #68] @ 0x44 8007800: f043 0204 orr.w r2, r3, #4 8007804: 68fb ldr r3, [r7, #12] 8007806: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8007808: 697b ldr r3, [r7, #20] 800780a: 2b00 cmp r3, #0 800780c: d004 beq.n 8007818 800780e: 697b ldr r3, [r7, #20] 8007810: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8007814: f040 8085 bne.w 8007922 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8007818: 68fb ldr r3, [r7, #12] 800781a: 6c5b ldr r3, [r3, #68] @ 0x44 800781c: 4619 mov r1, r3 800781e: 68f8 ldr r0, [r7, #12] 8007820: f000 ff38 bl 8008694 if (hi2c->XferCount == 0U) 8007824: e07d b.n 8007922 8007826: e07c b.n 8007922 } } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 8007828: 693b ldr r3, [r7, #16] 800782a: 089b lsrs r3, r3, #2 800782c: f003 0301 and.w r3, r3, #1 8007830: 2b00 cmp r3, #0 8007832: d030 beq.n 8007896 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) 8007834: 687b ldr r3, [r7, #4] 8007836: 089b lsrs r3, r3, #2 8007838: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 800783c: 2b00 cmp r3, #0 800783e: d02a beq.n 8007896 { if (hi2c->XferCount > 0U) 8007840: 68fb ldr r3, [r7, #12] 8007842: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007844: b29b uxth r3, r3 8007846: 2b00 cmp r3, #0 8007848: d018 beq.n 800787c { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 800784a: 68fb ldr r3, [r7, #12] 800784c: 681b ldr r3, [r3, #0] 800784e: 6a5a ldr r2, [r3, #36] @ 0x24 8007850: 68fb ldr r3, [r7, #12] 8007852: 6a5b ldr r3, [r3, #36] @ 0x24 8007854: b2d2 uxtb r2, r2 8007856: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8007858: 68fb ldr r3, [r7, #12] 800785a: 6a5b ldr r3, [r3, #36] @ 0x24 800785c: 1c5a adds r2, r3, #1 800785e: 68fb ldr r3, [r7, #12] 8007860: 625a str r2, [r3, #36] @ 0x24 hi2c->XferSize--; 8007862: 68fb ldr r3, [r7, #12] 8007864: 8d1b ldrh r3, [r3, #40] @ 0x28 8007866: 3b01 subs r3, #1 8007868: b29a uxth r2, r3 800786a: 68fb ldr r3, [r7, #12] 800786c: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 800786e: 68fb ldr r3, [r7, #12] 8007870: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007872: b29b uxth r3, r3 8007874: 3b01 subs r3, #1 8007876: b29a uxth r2, r3 8007878: 68fb ldr r3, [r7, #12] 800787a: 855a strh r2, [r3, #42] @ 0x2a } if ((hi2c->XferCount == 0U) && \ 800787c: 68fb ldr r3, [r7, #12] 800787e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007880: b29b uxth r3, r3 8007882: 2b00 cmp r3, #0 8007884: d14f bne.n 8007926 8007886: 697b ldr r3, [r7, #20] 8007888: f513 3f80 cmn.w r3, #65536 @ 0x10000 800788c: d04b beq.n 8007926 (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 800788e: 68f8 ldr r0, [r7, #12] 8007890: f000 fc18 bl 80080c4 if ((hi2c->XferCount == 0U) && \ 8007894: e047 b.n 8007926 } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 8007896: 693b ldr r3, [r7, #16] 8007898: 08db lsrs r3, r3, #3 800789a: f003 0301 and.w r3, r3, #1 800789e: 2b00 cmp r3, #0 80078a0: d00a beq.n 80078b8 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 80078a2: 687b ldr r3, [r7, #4] 80078a4: 08db lsrs r3, r3, #3 80078a6: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 80078aa: 2b00 cmp r3, #0 80078ac: d004 beq.n 80078b8 { I2C_ITAddrCplt(hi2c, tmpITFlags); 80078ae: 6939 ldr r1, [r7, #16] 80078b0: 68f8 ldr r0, [r7, #12] 80078b2: f000 fb46 bl 8007f42 80078b6: e037 b.n 8007928 } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 80078b8: 693b ldr r3, [r7, #16] 80078ba: 085b lsrs r3, r3, #1 80078bc: f003 0301 and.w r3, r3, #1 80078c0: 2b00 cmp r3, #0 80078c2: d031 beq.n 8007928 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 80078c4: 687b ldr r3, [r7, #4] 80078c6: 085b lsrs r3, r3, #1 80078c8: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 80078cc: 2b00 cmp r3, #0 80078ce: d02b beq.n 8007928 { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) 80078d0: 68fb ldr r3, [r7, #12] 80078d2: 8d5b ldrh r3, [r3, #42] @ 0x2a 80078d4: b29b uxth r3, r3 80078d6: 2b00 cmp r3, #0 80078d8: d018 beq.n 800790c { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 80078da: 68fb ldr r3, [r7, #12] 80078dc: 6a5b ldr r3, [r3, #36] @ 0x24 80078de: 781a ldrb r2, [r3, #0] 80078e0: 68fb ldr r3, [r7, #12] 80078e2: 681b ldr r3, [r3, #0] 80078e4: 629a str r2, [r3, #40] @ 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80078e6: 68fb ldr r3, [r7, #12] 80078e8: 6a5b ldr r3, [r3, #36] @ 0x24 80078ea: 1c5a adds r2, r3, #1 80078ec: 68fb ldr r3, [r7, #12] 80078ee: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount--; 80078f0: 68fb ldr r3, [r7, #12] 80078f2: 8d5b ldrh r3, [r3, #42] @ 0x2a 80078f4: b29b uxth r3, r3 80078f6: 3b01 subs r3, #1 80078f8: b29a uxth r2, r3 80078fa: 68fb ldr r3, [r7, #12] 80078fc: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize--; 80078fe: 68fb ldr r3, [r7, #12] 8007900: 8d1b ldrh r3, [r3, #40] @ 0x28 8007902: 3b01 subs r3, #1 8007904: b29a uxth r2, r3 8007906: 68fb ldr r3, [r7, #12] 8007908: 851a strh r2, [r3, #40] @ 0x28 800790a: e00d b.n 8007928 } else { if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) 800790c: 697b ldr r3, [r7, #20] 800790e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8007912: d002 beq.n 800791a 8007914: 697b ldr r3, [r7, #20] 8007916: 2b00 cmp r3, #0 8007918: d106 bne.n 8007928 { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 800791a: 68f8 ldr r0, [r7, #12] 800791c: f000 fbd2 bl 80080c4 8007920: e002 b.n 8007928 if (hi2c->XferCount == 0U) 8007922: bf00 nop 8007924: e000 b.n 8007928 if ((hi2c->XferCount == 0U) && \ 8007926: bf00 nop { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007928: 68fb ldr r3, [r7, #12] 800792a: 2200 movs r2, #0 800792c: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8007930: 2300 movs r3, #0 } 8007932: 4618 mov r0, r3 8007934: 3718 adds r7, #24 8007936: 46bd mov sp, r7 8007938: bd80 pop {r7, pc} 0800793a : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 800793a: b580 push {r7, lr} 800793c: b088 sub sp, #32 800793e: af02 add r7, sp, #8 8007940: 60f8 str r0, [r7, #12] 8007942: 60b9 str r1, [r7, #8] 8007944: 607a str r2, [r7, #4] uint16_t devaddress; uint32_t xfermode; /* Process Locked */ __HAL_LOCK(hi2c); 8007946: 68fb ldr r3, [r7, #12] 8007948: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800794c: 2b01 cmp r3, #1 800794e: d101 bne.n 8007954 8007950: 2302 movs r3, #2 8007952: e0e1 b.n 8007b18 8007954: 68fb ldr r3, [r7, #12] 8007956: 2201 movs r2, #1 8007958: f883 2040 strb.w r2, [r3, #64] @ 0x40 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 800795c: 68bb ldr r3, [r7, #8] 800795e: 091b lsrs r3, r3, #4 8007960: f003 0301 and.w r3, r3, #1 8007964: 2b00 cmp r3, #0 8007966: d017 beq.n 8007998 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8007968: 687b ldr r3, [r7, #4] 800796a: 091b lsrs r3, r3, #4 800796c: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8007970: 2b00 cmp r3, #0 8007972: d011 beq.n 8007998 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007974: 68fb ldr r3, [r7, #12] 8007976: 681b ldr r3, [r3, #0] 8007978: 2210 movs r2, #16 800797a: 61da str r2, [r3, #28] /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 800797c: 68fb ldr r3, [r7, #12] 800797e: 6c5b ldr r3, [r3, #68] @ 0x44 8007980: f043 0204 orr.w r2, r3, #4 8007984: 68fb ldr r3, [r7, #12] 8007986: 645a str r2, [r3, #68] @ 0x44 /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8007988: 2120 movs r1, #32 800798a: 68f8 ldr r0, [r7, #12] 800798c: f001 f8ba bl 8008b04 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8007990: 68f8 ldr r0, [r7, #12] 8007992: f000 ff96 bl 80088c2 8007996: e0ba b.n 8007b0e } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8007998: 68bb ldr r3, [r7, #8] 800799a: 09db lsrs r3, r3, #7 800799c: f003 0301 and.w r3, r3, #1 80079a0: 2b00 cmp r3, #0 80079a2: d072 beq.n 8007a8a (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 80079a4: 687b ldr r3, [r7, #4] 80079a6: 099b lsrs r3, r3, #6 80079a8: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 80079ac: 2b00 cmp r3, #0 80079ae: d06c beq.n 8007a8a { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); 80079b0: 68fb ldr r3, [r7, #12] 80079b2: 681b ldr r3, [r3, #0] 80079b4: 681a ldr r2, [r3, #0] 80079b6: 68fb ldr r3, [r7, #12] 80079b8: 681b ldr r3, [r3, #0] 80079ba: f022 0240 bic.w r2, r2, #64 @ 0x40 80079be: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 80079c0: 68fb ldr r3, [r7, #12] 80079c2: 8d5b ldrh r3, [r3, #42] @ 0x2a 80079c4: b29b uxth r3, r3 80079c6: 2b00 cmp r3, #0 80079c8: d04e beq.n 8007a68 { /* Recover Slave address */ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); 80079ca: 68fb ldr r3, [r7, #12] 80079cc: 681b ldr r3, [r3, #0] 80079ce: 685b ldr r3, [r3, #4] 80079d0: b29b uxth r3, r3 80079d2: f3c3 0309 ubfx r3, r3, #0, #10 80079d6: 827b strh r3, [r7, #18] /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 80079d8: 68fb ldr r3, [r7, #12] 80079da: 8d5b ldrh r3, [r3, #42] @ 0x2a 80079dc: b29b uxth r3, r3 80079de: 2bff cmp r3, #255 @ 0xff 80079e0: d906 bls.n 80079f0 { hi2c->XferSize = MAX_NBYTE_SIZE; 80079e2: 68fb ldr r3, [r7, #12] 80079e4: 22ff movs r2, #255 @ 0xff 80079e6: 851a strh r2, [r3, #40] @ 0x28 xfermode = I2C_RELOAD_MODE; 80079e8: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80079ec: 617b str r3, [r7, #20] 80079ee: e010 b.n 8007a12 } else { hi2c->XferSize = hi2c->XferCount; 80079f0: 68fb ldr r3, [r7, #12] 80079f2: 8d5b ldrh r3, [r3, #42] @ 0x2a 80079f4: b29a uxth r2, r3 80079f6: 68fb ldr r3, [r7, #12] 80079f8: 851a strh r2, [r3, #40] @ 0x28 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 80079fa: 68fb ldr r3, [r7, #12] 80079fc: 6adb ldr r3, [r3, #44] @ 0x2c 80079fe: f513 3f80 cmn.w r3, #65536 @ 0x10000 8007a02: d003 beq.n 8007a0c { xfermode = hi2c->XferOptions; 8007a04: 68fb ldr r3, [r7, #12] 8007a06: 6adb ldr r3, [r3, #44] @ 0x2c 8007a08: 617b str r3, [r7, #20] 8007a0a: e002 b.n 8007a12 } else { xfermode = I2C_AUTOEND_MODE; 8007a0c: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8007a10: 617b str r3, [r7, #20] } } /* Set the new XferSize in Nbytes register */ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); 8007a12: 68fb ldr r3, [r7, #12] 8007a14: 8d1b ldrh r3, [r3, #40] @ 0x28 8007a16: b2da uxtb r2, r3 8007a18: 8a79 ldrh r1, [r7, #18] 8007a1a: 2300 movs r3, #0 8007a1c: 9300 str r3, [sp, #0] 8007a1e: 697b ldr r3, [r7, #20] 8007a20: 68f8 ldr r0, [r7, #12] 8007a22: f001 f83d bl 8008aa0 /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8007a26: 68fb ldr r3, [r7, #12] 8007a28: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007a2a: b29a uxth r2, r3 8007a2c: 68fb ldr r3, [r7, #12] 8007a2e: 8d1b ldrh r3, [r3, #40] @ 0x28 8007a30: 1ad3 subs r3, r2, r3 8007a32: b29a uxth r2, r3 8007a34: 68fb ldr r3, [r7, #12] 8007a36: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8007a38: 68fb ldr r3, [r7, #12] 8007a3a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007a3e: b2db uxtb r3, r3 8007a40: 2b22 cmp r3, #34 @ 0x22 8007a42: d108 bne.n 8007a56 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8007a44: 68fb ldr r3, [r7, #12] 8007a46: 681b ldr r3, [r3, #0] 8007a48: 681a ldr r2, [r3, #0] 8007a4a: 68fb ldr r3, [r7, #12] 8007a4c: 681b ldr r3, [r3, #0] 8007a4e: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8007a52: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8007a54: e05b b.n 8007b0e } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 8007a56: 68fb ldr r3, [r7, #12] 8007a58: 681b ldr r3, [r3, #0] 8007a5a: 681a ldr r2, [r3, #0] 8007a5c: 68fb ldr r3, [r7, #12] 8007a5e: 681b ldr r3, [r3, #0] 8007a60: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8007a64: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8007a66: e052 b.n 8007b0e } } else { /* Call TxCpltCallback() if no stop mode is set */ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 8007a68: 68fb ldr r3, [r7, #12] 8007a6a: 681b ldr r3, [r3, #0] 8007a6c: 685b ldr r3, [r3, #4] 8007a6e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007a72: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8007a76: d003 beq.n 8007a80 { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); 8007a78: 68f8 ldr r0, [r7, #12] 8007a7a: f000 fae6 bl 800804a if (hi2c->XferCount != 0U) 8007a7e: e046 b.n 8007b0e } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 8007a80: 2140 movs r1, #64 @ 0x40 8007a82: 68f8 ldr r0, [r7, #12] 8007a84: f000 fe06 bl 8008694 if (hi2c->XferCount != 0U) 8007a88: e041 b.n 8007b0e } } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8007a8a: 68bb ldr r3, [r7, #8] 8007a8c: 099b lsrs r3, r3, #6 8007a8e: f003 0301 and.w r3, r3, #1 8007a92: 2b00 cmp r3, #0 8007a94: d029 beq.n 8007aea (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8007a96: 687b ldr r3, [r7, #4] 8007a98: 099b lsrs r3, r3, #6 8007a9a: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8007a9e: 2b00 cmp r3, #0 8007aa0: d023 beq.n 8007aea { if (hi2c->XferCount == 0U) 8007aa2: 68fb ldr r3, [r7, #12] 8007aa4: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007aa6: b29b uxth r3, r3 8007aa8: 2b00 cmp r3, #0 8007aaa: d119 bne.n 8007ae0 { if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 8007aac: 68fb ldr r3, [r7, #12] 8007aae: 681b ldr r3, [r3, #0] 8007ab0: 685b ldr r3, [r3, #4] 8007ab2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007ab6: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8007aba: d027 beq.n 8007b0c { /* Generate a stop condition in case of no transfer option */ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) 8007abc: 68fb ldr r3, [r7, #12] 8007abe: 6adb ldr r3, [r3, #44] @ 0x2c 8007ac0: f513 3f80 cmn.w r3, #65536 @ 0x10000 8007ac4: d108 bne.n 8007ad8 { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; 8007ac6: 68fb ldr r3, [r7, #12] 8007ac8: 681b ldr r3, [r3, #0] 8007aca: 685a ldr r2, [r3, #4] 8007acc: 68fb ldr r3, [r7, #12] 8007ace: 681b ldr r3, [r3, #0] 8007ad0: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8007ad4: 605a str r2, [r3, #4] if (hi2c->XferCount == 0U) 8007ad6: e019 b.n 8007b0c } else { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); 8007ad8: 68f8 ldr r0, [r7, #12] 8007ada: f000 fab6 bl 800804a if (hi2c->XferCount == 0U) 8007ade: e015 b.n 8007b0c } else { /* Wrong size Status regarding TC flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 8007ae0: 2140 movs r1, #64 @ 0x40 8007ae2: 68f8 ldr r0, [r7, #12] 8007ae4: f000 fdd6 bl 8008694 if (hi2c->XferCount == 0U) 8007ae8: e010 b.n 8007b0c } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007aea: 68bb ldr r3, [r7, #8] 8007aec: 095b lsrs r3, r3, #5 8007aee: f003 0301 and.w r3, r3, #1 8007af2: 2b00 cmp r3, #0 8007af4: d00b beq.n 8007b0e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8007af6: 687b ldr r3, [r7, #4] 8007af8: 095b lsrs r3, r3, #5 8007afa: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007afe: 2b00 cmp r3, #0 8007b00: d005 beq.n 8007b0e { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); 8007b02: 68b9 ldr r1, [r7, #8] 8007b04: 68f8 ldr r0, [r7, #12] 8007b06: f000 fb3b bl 8008180 8007b0a: e000 b.n 8007b0e if (hi2c->XferCount == 0U) 8007b0c: bf00 nop { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007b0e: 68fb ldr r3, [r7, #12] 8007b10: 2200 movs r2, #0 8007b12: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8007b16: 2300 movs r3, #0 } 8007b18: 4618 mov r0, r3 8007b1a: 3718 adds r7, #24 8007b1c: 46bd mov sp, r7 8007b1e: bd80 pop {r7, pc} 08007b20 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8007b20: b580 push {r7, lr} 8007b22: b088 sub sp, #32 8007b24: af02 add r7, sp, #8 8007b26: 60f8 str r0, [r7, #12] 8007b28: 60b9 str r1, [r7, #8] 8007b2a: 607a str r2, [r7, #4] uint32_t direction = I2C_GENERATE_START_WRITE; 8007b2c: 4b92 ldr r3, [pc, #584] @ (8007d78 ) 8007b2e: 617b str r3, [r7, #20] /* Process Locked */ __HAL_LOCK(hi2c); 8007b30: 68fb ldr r3, [r7, #12] 8007b32: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8007b36: 2b01 cmp r3, #1 8007b38: d101 bne.n 8007b3e 8007b3a: 2302 movs r3, #2 8007b3c: e118 b.n 8007d70 8007b3e: 68fb ldr r3, [r7, #12] 8007b40: 2201 movs r2, #1 8007b42: f883 2040 strb.w r2, [r3, #64] @ 0x40 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8007b46: 68bb ldr r3, [r7, #8] 8007b48: 091b lsrs r3, r3, #4 8007b4a: f003 0301 and.w r3, r3, #1 8007b4e: 2b00 cmp r3, #0 8007b50: d017 beq.n 8007b82 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8007b52: 687b ldr r3, [r7, #4] 8007b54: 091b lsrs r3, r3, #4 8007b56: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8007b5a: 2b00 cmp r3, #0 8007b5c: d011 beq.n 8007b82 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007b5e: 68fb ldr r3, [r7, #12] 8007b60: 681b ldr r3, [r3, #0] 8007b62: 2210 movs r2, #16 8007b64: 61da str r2, [r3, #28] /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8007b66: 68fb ldr r3, [r7, #12] 8007b68: 6c5b ldr r3, [r3, #68] @ 0x44 8007b6a: f043 0204 orr.w r2, r3, #4 8007b6e: 68fb ldr r3, [r7, #12] 8007b70: 645a str r2, [r3, #68] @ 0x44 /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8007b72: 2120 movs r1, #32 8007b74: 68f8 ldr r0, [r7, #12] 8007b76: f000 ffc5 bl 8008b04 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8007b7a: 68f8 ldr r0, [r7, #12] 8007b7c: f000 fea1 bl 80088c2 8007b80: e0f1 b.n 8007d66 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ 8007b82: 68bb ldr r3, [r7, #8] 8007b84: 085b lsrs r3, r3, #1 8007b86: f003 0301 and.w r3, r3, #1 8007b8a: 2b00 cmp r3, #0 8007b8c: d00f beq.n 8007bae (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 8007b8e: 687b ldr r3, [r7, #4] 8007b90: 085b lsrs r3, r3, #1 8007b92: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ 8007b96: 2b00 cmp r3, #0 8007b98: d009 beq.n 8007bae { /* Write LSB part of Memory Address */ hi2c->Instance->TXDR = hi2c->Memaddress; 8007b9a: 68fb ldr r3, [r7, #12] 8007b9c: 681b ldr r3, [r3, #0] 8007b9e: 68fa ldr r2, [r7, #12] 8007ba0: 6d12 ldr r2, [r2, #80] @ 0x50 8007ba2: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 8007ba4: 68fb ldr r3, [r7, #12] 8007ba6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007baa: 651a str r2, [r3, #80] @ 0x50 8007bac: e0db b.n 8007d66 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8007bae: 68bb ldr r3, [r7, #8] 8007bb0: 09db lsrs r3, r3, #7 8007bb2: f003 0301 and.w r3, r3, #1 8007bb6: 2b00 cmp r3, #0 8007bb8: d060 beq.n 8007c7c (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8007bba: 687b ldr r3, [r7, #4] 8007bbc: 099b lsrs r3, r3, #6 8007bbe: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8007bc2: 2b00 cmp r3, #0 8007bc4: d05a beq.n 8007c7c { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8007bc6: 2101 movs r1, #1 8007bc8: 68f8 ldr r0, [r7, #12] 8007bca: f001 f81f bl 8008c0c /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); 8007bce: 2110 movs r1, #16 8007bd0: 68f8 ldr r0, [r7, #12] 8007bd2: f000 ff97 bl 8008b04 if (hi2c->XferCount != 0U) 8007bd6: 68fb ldr r3, [r7, #12] 8007bd8: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007bda: b29b uxth r3, r3 8007bdc: 2b00 cmp r3, #0 8007bde: d048 beq.n 8007c72 { /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8007be0: 68fb ldr r3, [r7, #12] 8007be2: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007be4: b29b uxth r3, r3 8007be6: 2bff cmp r3, #255 @ 0xff 8007be8: d910 bls.n 8007c0c { hi2c->XferSize = MAX_NBYTE_SIZE; 8007bea: 68fb ldr r3, [r7, #12] 8007bec: 22ff movs r2, #255 @ 0xff 8007bee: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8007bf0: 68fb ldr r3, [r7, #12] 8007bf2: 6cdb ldr r3, [r3, #76] @ 0x4c 8007bf4: b299 uxth r1, r3 8007bf6: 68fb ldr r3, [r7, #12] 8007bf8: 8d1b ldrh r3, [r3, #40] @ 0x28 8007bfa: b2da uxtb r2, r3 8007bfc: 2300 movs r3, #0 8007bfe: 9300 str r3, [sp, #0] 8007c00: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8007c04: 68f8 ldr r0, [r7, #12] 8007c06: f000 ff4b bl 8008aa0 8007c0a: e011 b.n 8007c30 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 8007c0c: 68fb ldr r3, [r7, #12] 8007c0e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007c10: b29a uxth r2, r3 8007c12: 68fb ldr r3, [r7, #12] 8007c14: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8007c16: 68fb ldr r3, [r7, #12] 8007c18: 6cdb ldr r3, [r3, #76] @ 0x4c 8007c1a: b299 uxth r1, r3 8007c1c: 68fb ldr r3, [r7, #12] 8007c1e: 8d1b ldrh r3, [r3, #40] @ 0x28 8007c20: b2da uxtb r2, r3 8007c22: 2300 movs r3, #0 8007c24: 9300 str r3, [sp, #0] 8007c26: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8007c2a: 68f8 ldr r0, [r7, #12] 8007c2c: f000 ff38 bl 8008aa0 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8007c30: 68fb ldr r3, [r7, #12] 8007c32: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007c34: b29a uxth r2, r3 8007c36: 68fb ldr r3, [r7, #12] 8007c38: 8d1b ldrh r3, [r3, #40] @ 0x28 8007c3a: 1ad3 subs r3, r2, r3 8007c3c: b29a uxth r2, r3 8007c3e: 68fb ldr r3, [r7, #12] 8007c40: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8007c42: 68fb ldr r3, [r7, #12] 8007c44: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007c48: b2db uxtb r3, r3 8007c4a: 2b22 cmp r3, #34 @ 0x22 8007c4c: d108 bne.n 8007c60 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8007c4e: 68fb ldr r3, [r7, #12] 8007c50: 681b ldr r3, [r3, #0] 8007c52: 681a ldr r2, [r3, #0] 8007c54: 68fb ldr r3, [r7, #12] 8007c56: 681b ldr r3, [r3, #0] 8007c58: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8007c5c: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8007c5e: e082 b.n 8007d66 } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 8007c60: 68fb ldr r3, [r7, #12] 8007c62: 681b ldr r3, [r3, #0] 8007c64: 681a ldr r2, [r3, #0] 8007c66: 68fb ldr r3, [r7, #12] 8007c68: 681b ldr r3, [r3, #0] 8007c6a: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8007c6e: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8007c70: e079 b.n 8007d66 } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 8007c72: 2140 movs r1, #64 @ 0x40 8007c74: 68f8 ldr r0, [r7, #12] 8007c76: f000 fd0d bl 8008694 if (hi2c->XferCount != 0U) 8007c7a: e074 b.n 8007d66 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8007c7c: 68bb ldr r3, [r7, #8] 8007c7e: 099b lsrs r3, r3, #6 8007c80: f003 0301 and.w r3, r3, #1 8007c84: 2b00 cmp r3, #0 8007c86: d05e beq.n 8007d46 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8007c88: 687b ldr r3, [r7, #4] 8007c8a: 099b lsrs r3, r3, #6 8007c8c: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8007c90: 2b00 cmp r3, #0 8007c92: d058 beq.n 8007d46 { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8007c94: 2101 movs r1, #1 8007c96: 68f8 ldr r0, [r7, #12] 8007c98: f000 ffb8 bl 8008c0c /* Enable only Error and NACK interrupt for data transfer */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); 8007c9c: 2110 movs r1, #16 8007c9e: 68f8 ldr r0, [r7, #12] 8007ca0: f000 ff30 bl 8008b04 if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8007ca4: 68fb ldr r3, [r7, #12] 8007ca6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007caa: b2db uxtb r3, r3 8007cac: 2b22 cmp r3, #34 @ 0x22 8007cae: d101 bne.n 8007cb4 { direction = I2C_GENERATE_START_READ; 8007cb0: 4b32 ldr r3, [pc, #200] @ (8007d7c ) 8007cb2: 617b str r3, [r7, #20] } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8007cb4: 68fb ldr r3, [r7, #12] 8007cb6: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007cb8: b29b uxth r3, r3 8007cba: 2bff cmp r3, #255 @ 0xff 8007cbc: d910 bls.n 8007ce0 { hi2c->XferSize = MAX_NBYTE_SIZE; 8007cbe: 68fb ldr r3, [r7, #12] 8007cc0: 22ff movs r2, #255 @ 0xff 8007cc2: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8007cc4: 68fb ldr r3, [r7, #12] 8007cc6: 6cdb ldr r3, [r3, #76] @ 0x4c 8007cc8: b299 uxth r1, r3 8007cca: 68fb ldr r3, [r7, #12] 8007ccc: 8d1b ldrh r3, [r3, #40] @ 0x28 8007cce: b2da uxtb r2, r3 8007cd0: 697b ldr r3, [r7, #20] 8007cd2: 9300 str r3, [sp, #0] 8007cd4: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8007cd8: 68f8 ldr r0, [r7, #12] 8007cda: f000 fee1 bl 8008aa0 8007cde: e011 b.n 8007d04 I2C_RELOAD_MODE, direction); } else { hi2c->XferSize = hi2c->XferCount; 8007ce0: 68fb ldr r3, [r7, #12] 8007ce2: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007ce4: b29a uxth r2, r3 8007ce6: 68fb ldr r3, [r7, #12] 8007ce8: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8007cea: 68fb ldr r3, [r7, #12] 8007cec: 6cdb ldr r3, [r3, #76] @ 0x4c 8007cee: b299 uxth r1, r3 8007cf0: 68fb ldr r3, [r7, #12] 8007cf2: 8d1b ldrh r3, [r3, #40] @ 0x28 8007cf4: b2da uxtb r2, r3 8007cf6: 697b ldr r3, [r7, #20] 8007cf8: 9300 str r3, [sp, #0] 8007cfa: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8007cfe: 68f8 ldr r0, [r7, #12] 8007d00: f000 fece bl 8008aa0 I2C_AUTOEND_MODE, direction); } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8007d04: 68fb ldr r3, [r7, #12] 8007d06: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007d08: b29a uxth r2, r3 8007d0a: 68fb ldr r3, [r7, #12] 8007d0c: 8d1b ldrh r3, [r3, #40] @ 0x28 8007d0e: 1ad3 subs r3, r2, r3 8007d10: b29a uxth r2, r3 8007d12: 68fb ldr r3, [r7, #12] 8007d14: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8007d16: 68fb ldr r3, [r7, #12] 8007d18: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007d1c: b2db uxtb r3, r3 8007d1e: 2b22 cmp r3, #34 @ 0x22 8007d20: d108 bne.n 8007d34 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8007d22: 68fb ldr r3, [r7, #12] 8007d24: 681b ldr r3, [r3, #0] 8007d26: 681a ldr r2, [r3, #0] 8007d28: 68fb ldr r3, [r7, #12] 8007d2a: 681b ldr r3, [r3, #0] 8007d2c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8007d30: 601a str r2, [r3, #0] if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8007d32: e018 b.n 8007d66 } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 8007d34: 68fb ldr r3, [r7, #12] 8007d36: 681b ldr r3, [r3, #0] 8007d38: 681a ldr r2, [r3, #0] 8007d3a: 68fb ldr r3, [r7, #12] 8007d3c: 681b ldr r3, [r3, #0] 8007d3e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8007d42: 601a str r2, [r3, #0] if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8007d44: e00f b.n 8007d66 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007d46: 68bb ldr r3, [r7, #8] 8007d48: 095b lsrs r3, r3, #5 8007d4a: f003 0301 and.w r3, r3, #1 8007d4e: 2b00 cmp r3, #0 8007d50: d009 beq.n 8007d66 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8007d52: 687b ldr r3, [r7, #4] 8007d54: 095b lsrs r3, r3, #5 8007d56: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007d5a: 2b00 cmp r3, #0 8007d5c: d003 beq.n 8007d66 { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); 8007d5e: 68b9 ldr r1, [r7, #8] 8007d60: 68f8 ldr r0, [r7, #12] 8007d62: f000 fa0d bl 8008180 { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007d66: 68fb ldr r3, [r7, #12] 8007d68: 2200 movs r2, #0 8007d6a: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8007d6e: 2300 movs r3, #0 } 8007d70: 4618 mov r0, r3 8007d72: 3718 adds r7, #24 8007d74: 46bd mov sp, r7 8007d76: bd80 pop {r7, pc} 8007d78: 80002000 .word 0x80002000 8007d7c: 80002400 .word 0x80002400 08007d80 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8007d80: b580 push {r7, lr} 8007d82: b088 sub sp, #32 8007d84: af00 add r7, sp, #0 8007d86: 60f8 str r0, [r7, #12] 8007d88: 60b9 str r1, [r7, #8] 8007d8a: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 8007d8c: 68fb ldr r3, [r7, #12] 8007d8e: 6adb ldr r3, [r3, #44] @ 0x2c 8007d90: 61bb str r3, [r7, #24] uint32_t treatdmanack = 0U; 8007d92: 2300 movs r3, #0 8007d94: 61fb str r3, [r7, #28] HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); 8007d96: 68fb ldr r3, [r7, #12] 8007d98: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8007d9c: 2b01 cmp r3, #1 8007d9e: d101 bne.n 8007da4 8007da0: 2302 movs r3, #2 8007da2: e0ca b.n 8007f3a 8007da4: 68fb ldr r3, [r7, #12] 8007da6: 2201 movs r2, #1 8007da8: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007dac: 68bb ldr r3, [r7, #8] 8007dae: 095b lsrs r3, r3, #5 8007db0: f003 0301 and.w r3, r3, #1 8007db4: 2b00 cmp r3, #0 8007db6: d00a beq.n 8007dce (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8007db8: 687b ldr r3, [r7, #4] 8007dba: 095b lsrs r3, r3, #5 8007dbc: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007dc0: 2b00 cmp r3, #0 8007dc2: d004 beq.n 8007dce { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); 8007dc4: 68b9 ldr r1, [r7, #8] 8007dc6: 68f8 ldr r0, [r7, #12] 8007dc8: f000 faa4 bl 8008314 8007dcc: e0b0 b.n 8007f30 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8007dce: 68bb ldr r3, [r7, #8] 8007dd0: 091b lsrs r3, r3, #4 8007dd2: f003 0301 and.w r3, r3, #1 8007dd6: 2b00 cmp r3, #0 8007dd8: f000 809a beq.w 8007f10 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8007ddc: 687b ldr r3, [r7, #4] 8007dde: 091b lsrs r3, r3, #4 8007de0: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8007de4: 2b00 cmp r3, #0 8007de6: f000 8093 beq.w 8007f10 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8007dea: 687b ldr r3, [r7, #4] 8007dec: 0b9b lsrs r3, r3, #14 8007dee: f003 0301 and.w r3, r3, #1 8007df2: 2b00 cmp r3, #0 8007df4: d105 bne.n 8007e02 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) 8007df6: 687b ldr r3, [r7, #4] 8007df8: 0bdb lsrs r3, r3, #15 8007dfa: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8007dfe: 2b00 cmp r3, #0 8007e00: d07f beq.n 8007f02 { /* Split check of hdmarx, for MISRA compliance */ if (hi2c->hdmarx != NULL) 8007e02: 68fb ldr r3, [r7, #12] 8007e04: 6bdb ldr r3, [r3, #60] @ 0x3c 8007e06: 2b00 cmp r3, #0 8007e08: d00d beq.n 8007e26 { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) 8007e0a: 687b ldr r3, [r7, #4] 8007e0c: 0bdb lsrs r3, r3, #15 8007e0e: f003 0301 and.w r3, r3, #1 8007e12: 2b00 cmp r3, #0 8007e14: d007 beq.n 8007e26 { if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) 8007e16: 68fb ldr r3, [r7, #12] 8007e18: 6bdb ldr r3, [r3, #60] @ 0x3c 8007e1a: 681b ldr r3, [r3, #0] 8007e1c: 685b ldr r3, [r3, #4] 8007e1e: 2b00 cmp r3, #0 8007e20: d101 bne.n 8007e26 { treatdmanack = 1U; 8007e22: 2301 movs r3, #1 8007e24: 61fb str r3, [r7, #28] } } } /* Split check of hdmatx, for MISRA compliance */ if (hi2c->hdmatx != NULL) 8007e26: 68fb ldr r3, [r7, #12] 8007e28: 6b9b ldr r3, [r3, #56] @ 0x38 8007e2a: 2b00 cmp r3, #0 8007e2c: d00d beq.n 8007e4a { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) 8007e2e: 687b ldr r3, [r7, #4] 8007e30: 0b9b lsrs r3, r3, #14 8007e32: f003 0301 and.w r3, r3, #1 8007e36: 2b00 cmp r3, #0 8007e38: d007 beq.n 8007e4a { if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) 8007e3a: 68fb ldr r3, [r7, #12] 8007e3c: 6b9b ldr r3, [r3, #56] @ 0x38 8007e3e: 681b ldr r3, [r3, #0] 8007e40: 685b ldr r3, [r3, #4] 8007e42: 2b00 cmp r3, #0 8007e44: d101 bne.n 8007e4a { treatdmanack = 1U; 8007e46: 2301 movs r3, #1 8007e48: 61fb str r3, [r7, #28] } } } if (treatdmanack == 1U) 8007e4a: 69fb ldr r3, [r7, #28] 8007e4c: 2b01 cmp r3, #1 8007e4e: d128 bne.n 8007ea2 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8007e50: 68fb ldr r3, [r7, #12] 8007e52: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007e56: b2db uxtb r3, r3 8007e58: 2b28 cmp r3, #40 @ 0x28 8007e5a: d108 bne.n 8007e6e 8007e5c: 69bb ldr r3, [r7, #24] 8007e5e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8007e62: d104 bne.n 8007e6e /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); 8007e64: 68b9 ldr r1, [r7, #8] 8007e66: 68f8 ldr r0, [r7, #12] 8007e68: f000 fbbe bl 80085e8 8007e6c: e048 b.n 8007f00 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 8007e6e: 68fb ldr r3, [r7, #12] 8007e70: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007e74: b2db uxtb r3, r3 8007e76: 2b29 cmp r3, #41 @ 0x29 8007e78: d10e bne.n 8007e98 8007e7a: 69bb ldr r3, [r7, #24] 8007e7c: f513 3f80 cmn.w r3, #65536 @ 0x10000 8007e80: d00a beq.n 8007e98 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007e82: 68fb ldr r3, [r7, #12] 8007e84: 681b ldr r3, [r3, #0] 8007e86: 2210 movs r2, #16 8007e88: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8007e8a: 68f8 ldr r0, [r7, #12] 8007e8c: f000 fd19 bl 80088c2 /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8007e90: 68f8 ldr r0, [r7, #12] 8007e92: f000 f917 bl 80080c4 8007e96: e033 b.n 8007f00 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007e98: 68fb ldr r3, [r7, #12] 8007e9a: 681b ldr r3, [r3, #0] 8007e9c: 2210 movs r2, #16 8007e9e: 61da str r2, [r3, #28] if (treatdmanack == 1U) 8007ea0: e034 b.n 8007f0c } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007ea2: 68fb ldr r3, [r7, #12] 8007ea4: 681b ldr r3, [r3, #0] 8007ea6: 2210 movs r2, #16 8007ea8: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8007eaa: 68fb ldr r3, [r7, #12] 8007eac: 6c5b ldr r3, [r3, #68] @ 0x44 8007eae: f043 0204 orr.w r2, r3, #4 8007eb2: 68fb ldr r3, [r7, #12] 8007eb4: 645a str r2, [r3, #68] @ 0x44 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ tmpstate = hi2c->State; 8007eb6: 68fb ldr r3, [r7, #12] 8007eb8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007ebc: 75fb strb r3, [r7, #23] if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8007ebe: 69bb ldr r3, [r7, #24] 8007ec0: 2b00 cmp r3, #0 8007ec2: d003 beq.n 8007ecc 8007ec4: 69bb ldr r3, [r7, #24] 8007ec6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8007eca: d11f bne.n 8007f0c { if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 8007ecc: 7dfb ldrb r3, [r7, #23] 8007ece: 2b21 cmp r3, #33 @ 0x21 8007ed0: d002 beq.n 8007ed8 8007ed2: 7dfb ldrb r3, [r7, #23] 8007ed4: 2b29 cmp r3, #41 @ 0x29 8007ed6: d103 bne.n 8007ee0 { hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 8007ed8: 68fb ldr r3, [r7, #12] 8007eda: 2221 movs r2, #33 @ 0x21 8007edc: 631a str r2, [r3, #48] @ 0x30 8007ede: e008 b.n 8007ef2 } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 8007ee0: 7dfb ldrb r3, [r7, #23] 8007ee2: 2b22 cmp r3, #34 @ 0x22 8007ee4: d002 beq.n 8007eec 8007ee6: 7dfb ldrb r3, [r7, #23] 8007ee8: 2b2a cmp r3, #42 @ 0x2a 8007eea: d102 bne.n 8007ef2 { hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 8007eec: 68fb ldr r3, [r7, #12] 8007eee: 2222 movs r2, #34 @ 0x22 8007ef0: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8007ef2: 68fb ldr r3, [r7, #12] 8007ef4: 6c5b ldr r3, [r3, #68] @ 0x44 8007ef6: 4619 mov r1, r3 8007ef8: 68f8 ldr r0, [r7, #12] 8007efa: f000 fbcb bl 8008694 if (treatdmanack == 1U) 8007efe: e005 b.n 8007f0c 8007f00: e004 b.n 8007f0c } } else { /* Only Clear NACK Flag, no DMA treatment is pending */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007f02: 68fb ldr r3, [r7, #12] 8007f04: 681b ldr r3, [r3, #0] 8007f06: 2210 movs r2, #16 8007f08: 61da str r2, [r3, #28] if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8007f0a: e011 b.n 8007f30 if (treatdmanack == 1U) 8007f0c: bf00 nop if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8007f0e: e00f b.n 8007f30 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ 8007f10: 68bb ldr r3, [r7, #8] 8007f12: 08db lsrs r3, r3, #3 8007f14: f003 0301 and.w r3, r3, #1 8007f18: 2b00 cmp r3, #0 8007f1a: d009 beq.n 8007f30 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 8007f1c: 687b ldr r3, [r7, #4] 8007f1e: 08db lsrs r3, r3, #3 8007f20: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ 8007f24: 2b00 cmp r3, #0 8007f26: d003 beq.n 8007f30 { I2C_ITAddrCplt(hi2c, ITFlags); 8007f28: 68b9 ldr r1, [r7, #8] 8007f2a: 68f8 ldr r0, [r7, #12] 8007f2c: f000 f809 bl 8007f42 { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007f30: 68fb ldr r3, [r7, #12] 8007f32: 2200 movs r2, #0 8007f34: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8007f38: 2300 movs r3, #0 } 8007f3a: 4618 mov r0, r3 8007f3c: 3720 adds r7, #32 8007f3e: 46bd mov sp, r7 8007f40: bd80 pop {r7, pc} 08007f42 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8007f42: b580 push {r7, lr} 8007f44: b084 sub sp, #16 8007f46: af00 add r7, sp, #0 8007f48: 6078 str r0, [r7, #4] 8007f4a: 6039 str r1, [r7, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 8007f4c: 687b ldr r3, [r7, #4] 8007f4e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007f52: b2db uxtb r3, r3 8007f54: f003 0328 and.w r3, r3, #40 @ 0x28 8007f58: 2b28 cmp r3, #40 @ 0x28 8007f5a: d16a bne.n 8008032 { transferdirection = I2C_GET_DIR(hi2c); 8007f5c: 687b ldr r3, [r7, #4] 8007f5e: 681b ldr r3, [r3, #0] 8007f60: 699b ldr r3, [r3, #24] 8007f62: 0c1b lsrs r3, r3, #16 8007f64: b2db uxtb r3, r3 8007f66: f003 0301 and.w r3, r3, #1 8007f6a: 73fb strb r3, [r7, #15] slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); 8007f6c: 687b ldr r3, [r7, #4] 8007f6e: 681b ldr r3, [r3, #0] 8007f70: 699b ldr r3, [r3, #24] 8007f72: 0c1b lsrs r3, r3, #16 8007f74: b29b uxth r3, r3 8007f76: f003 03fe and.w r3, r3, #254 @ 0xfe 8007f7a: 81bb strh r3, [r7, #12] ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); 8007f7c: 687b ldr r3, [r7, #4] 8007f7e: 681b ldr r3, [r3, #0] 8007f80: 689b ldr r3, [r3, #8] 8007f82: b29b uxth r3, r3 8007f84: f3c3 0309 ubfx r3, r3, #0, #10 8007f88: 817b strh r3, [r7, #10] ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); 8007f8a: 687b ldr r3, [r7, #4] 8007f8c: 681b ldr r3, [r3, #0] 8007f8e: 68db ldr r3, [r3, #12] 8007f90: b29b uxth r3, r3 8007f92: f003 03fe and.w r3, r3, #254 @ 0xfe 8007f96: 813b strh r3, [r7, #8] /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8007f98: 687b ldr r3, [r7, #4] 8007f9a: 68db ldr r3, [r3, #12] 8007f9c: 2b02 cmp r3, #2 8007f9e: d138 bne.n 8008012 { if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) 8007fa0: 897b ldrh r3, [r7, #10] 8007fa2: 09db lsrs r3, r3, #7 8007fa4: b29a uxth r2, r3 8007fa6: 89bb ldrh r3, [r7, #12] 8007fa8: 4053 eors r3, r2 8007faa: b29b uxth r3, r3 8007fac: f003 0306 and.w r3, r3, #6 8007fb0: 2b00 cmp r3, #0 8007fb2: d11c bne.n 8007fee { slaveaddrcode = ownadd1code; 8007fb4: 897b ldrh r3, [r7, #10] 8007fb6: 81bb strh r3, [r7, #12] hi2c->AddrEventCount++; 8007fb8: 687b ldr r3, [r7, #4] 8007fba: 6c9b ldr r3, [r3, #72] @ 0x48 8007fbc: 1c5a adds r2, r3, #1 8007fbe: 687b ldr r3, [r7, #4] 8007fc0: 649a str r2, [r3, #72] @ 0x48 if (hi2c->AddrEventCount == 2U) 8007fc2: 687b ldr r3, [r7, #4] 8007fc4: 6c9b ldr r3, [r3, #72] @ 0x48 8007fc6: 2b02 cmp r3, #2 8007fc8: d13b bne.n 8008042 { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; 8007fca: 687b ldr r3, [r7, #4] 8007fcc: 2200 movs r2, #0 8007fce: 649a str r2, [r3, #72] @ 0x48 /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 8007fd0: 687b ldr r3, [r7, #4] 8007fd2: 681b ldr r3, [r3, #0] 8007fd4: 2208 movs r2, #8 8007fd6: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007fd8: 687b ldr r3, [r7, #4] 8007fda: 2200 movs r2, #0 8007fdc: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call Slave Addr callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); #else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 8007fe0: 89ba ldrh r2, [r7, #12] 8007fe2: 7bfb ldrb r3, [r7, #15] 8007fe4: 4619 mov r1, r3 8007fe6: 6878 ldr r0, [r7, #4] 8007fe8: f7ff fb75 bl 80076d6 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); } } 8007fec: e029 b.n 8008042 slaveaddrcode = ownadd2code; 8007fee: 893b ldrh r3, [r7, #8] 8007ff0: 81bb strh r3, [r7, #12] I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 8007ff2: f44f 4100 mov.w r1, #32768 @ 0x8000 8007ff6: 6878 ldr r0, [r7, #4] 8007ff8: f000 fe08 bl 8008c0c __HAL_UNLOCK(hi2c); 8007ffc: 687b ldr r3, [r7, #4] 8007ffe: 2200 movs r2, #0 8008000: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 8008004: 89ba ldrh r2, [r7, #12] 8008006: 7bfb ldrb r3, [r7, #15] 8008008: 4619 mov r1, r3 800800a: 6878 ldr r0, [r7, #4] 800800c: f7ff fb63 bl 80076d6 } 8008010: e017 b.n 8008042 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 8008012: f44f 4100 mov.w r1, #32768 @ 0x8000 8008016: 6878 ldr r0, [r7, #4] 8008018: f000 fdf8 bl 8008c0c __HAL_UNLOCK(hi2c); 800801c: 687b ldr r3, [r7, #4] 800801e: 2200 movs r2, #0 8008020: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 8008024: 89ba ldrh r2, [r7, #12] 8008026: 7bfb ldrb r3, [r7, #15] 8008028: 4619 mov r1, r3 800802a: 6878 ldr r0, [r7, #4] 800802c: f7ff fb53 bl 80076d6 } 8008030: e007 b.n 8008042 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 8008032: 687b ldr r3, [r7, #4] 8008034: 681b ldr r3, [r3, #0] 8008036: 2208 movs r2, #8 8008038: 61da str r2, [r3, #28] __HAL_UNLOCK(hi2c); 800803a: 687b ldr r3, [r7, #4] 800803c: 2200 movs r2, #0 800803e: f883 2040 strb.w r2, [r3, #64] @ 0x40 } 8008042: bf00 nop 8008044: 3710 adds r7, #16 8008046: 46bd mov sp, r7 8008048: bd80 pop {r7, pc} 0800804a : * @brief I2C Master sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) { 800804a: b580 push {r7, lr} 800804c: b082 sub sp, #8 800804e: af00 add r7, sp, #0 8008050: 6078 str r0, [r7, #4] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 8008052: 687b ldr r3, [r7, #4] 8008054: 2200 movs r2, #0 8008056: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 800805a: 687b ldr r3, [r7, #4] 800805c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008060: b2db uxtb r3, r3 8008062: 2b21 cmp r3, #33 @ 0x21 8008064: d115 bne.n 8008092 { hi2c->State = HAL_I2C_STATE_READY; 8008066: 687b ldr r3, [r7, #4] 8008068: 2220 movs r2, #32 800806a: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 800806e: 687b ldr r3, [r7, #4] 8008070: 2211 movs r2, #17 8008072: 631a str r2, [r3, #48] @ 0x30 hi2c->XferISR = NULL; 8008074: 687b ldr r3, [r7, #4] 8008076: 2200 movs r2, #0 8008078: 635a str r2, [r3, #52] @ 0x34 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 800807a: 2101 movs r1, #1 800807c: 6878 ldr r0, [r7, #4] 800807e: f000 fdc5 bl 8008c0c /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008082: 687b ldr r3, [r7, #4] 8008084: 2200 movs r2, #0 8008086: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterTxCpltCallback(hi2c); #else HAL_I2C_MasterTxCpltCallback(hi2c); 800808a: 6878 ldr r0, [r7, #4] 800808c: f7ff fafb bl 8007686 hi2c->MasterRxCpltCallback(hi2c); #else HAL_I2C_MasterRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 8008090: e014 b.n 80080bc hi2c->State = HAL_I2C_STATE_READY; 8008092: 687b ldr r3, [r7, #4] 8008094: 2220 movs r2, #32 8008096: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 800809a: 687b ldr r3, [r7, #4] 800809c: 2212 movs r2, #18 800809e: 631a str r2, [r3, #48] @ 0x30 hi2c->XferISR = NULL; 80080a0: 687b ldr r3, [r7, #4] 80080a2: 2200 movs r2, #0 80080a4: 635a str r2, [r3, #52] @ 0x34 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 80080a6: 2102 movs r1, #2 80080a8: 6878 ldr r0, [r7, #4] 80080aa: f000 fdaf bl 8008c0c __HAL_UNLOCK(hi2c); 80080ae: 687b ldr r3, [r7, #4] 80080b0: 2200 movs r2, #0 80080b2: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MasterRxCpltCallback(hi2c); 80080b6: 6878 ldr r0, [r7, #4] 80080b8: f7ff faef bl 800769a } 80080bc: bf00 nop 80080be: 3708 adds r7, #8 80080c0: 46bd mov sp, r7 80080c2: bd80 pop {r7, pc} 080080c4 : * @brief I2C Slave sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { 80080c4: b580 push {r7, lr} 80080c6: b084 sub sp, #16 80080c8: af00 add r7, sp, #0 80080ca: 6078 str r0, [r7, #4] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 80080cc: 687b ldr r3, [r7, #4] 80080ce: 681b ldr r3, [r3, #0] 80080d0: 681b ldr r3, [r3, #0] 80080d2: 60fb str r3, [r7, #12] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 80080d4: 687b ldr r3, [r7, #4] 80080d6: 2200 movs r2, #0 80080d8: f883 2042 strb.w r2, [r3, #66] @ 0x42 #if defined(HAL_DMA_MODULE_ENABLED) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 80080dc: 68fb ldr r3, [r7, #12] 80080de: 0b9b lsrs r3, r3, #14 80080e0: f003 0301 and.w r3, r3, #1 80080e4: 2b00 cmp r3, #0 80080e6: d008 beq.n 80080fa { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 80080e8: 687b ldr r3, [r7, #4] 80080ea: 681b ldr r3, [r3, #0] 80080ec: 681a ldr r2, [r3, #0] 80080ee: 687b ldr r3, [r7, #4] 80080f0: 681b ldr r3, [r3, #0] 80080f2: f422 4280 bic.w r2, r2, #16384 @ 0x4000 80080f6: 601a str r2, [r3, #0] 80080f8: e00d b.n 8008116 } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 80080fa: 68fb ldr r3, [r7, #12] 80080fc: 0bdb lsrs r3, r3, #15 80080fe: f003 0301 and.w r3, r3, #1 8008102: 2b00 cmp r3, #0 8008104: d007 beq.n 8008116 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8008106: 687b ldr r3, [r7, #4] 8008108: 681b ldr r3, [r3, #0] 800810a: 681a ldr r2, [r3, #0] 800810c: 687b ldr r3, [r7, #4] 800810e: 681b ldr r3, [r3, #0] 8008110: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8008114: 601a str r2, [r3, #0] { /* Do nothing */ } #endif /* HAL_DMA_MODULE_ENABLED */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 8008116: 687b ldr r3, [r7, #4] 8008118: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800811c: b2db uxtb r3, r3 800811e: 2b29 cmp r3, #41 @ 0x29 8008120: d112 bne.n 8008148 { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; 8008122: 687b ldr r3, [r7, #4] 8008124: 2228 movs r2, #40 @ 0x28 8008126: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 800812a: 687b ldr r3, [r7, #4] 800812c: 2221 movs r2, #33 @ 0x21 800812e: 631a str r2, [r3, #48] @ 0x30 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8008130: 2101 movs r1, #1 8008132: 6878 ldr r0, [r7, #4] 8008134: f000 fd6a bl 8008c0c /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008138: 687b ldr r3, [r7, #4] 800813a: 2200 movs r2, #0 800813c: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); 8008140: 6878 ldr r0, [r7, #4] 8008142: f7ff fab4 bl 80076ae } else { /* Nothing to do */ } } 8008146: e017 b.n 8008178 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 8008148: 687b ldr r3, [r7, #4] 800814a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800814e: b2db uxtb r3, r3 8008150: 2b2a cmp r3, #42 @ 0x2a 8008152: d111 bne.n 8008178 hi2c->State = HAL_I2C_STATE_LISTEN; 8008154: 687b ldr r3, [r7, #4] 8008156: 2228 movs r2, #40 @ 0x28 8008158: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 800815c: 687b ldr r3, [r7, #4] 800815e: 2222 movs r2, #34 @ 0x22 8008160: 631a str r2, [r3, #48] @ 0x30 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 8008162: 2102 movs r1, #2 8008164: 6878 ldr r0, [r7, #4] 8008166: f000 fd51 bl 8008c0c __HAL_UNLOCK(hi2c); 800816a: 687b ldr r3, [r7, #4] 800816c: 2200 movs r2, #0 800816e: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_SlaveRxCpltCallback(hi2c); 8008172: 6878 ldr r0, [r7, #4] 8008174: f7ff faa5 bl 80076c2 } 8008178: bf00 nop 800817a: 3710 adds r7, #16 800817c: 46bd mov sp, r7 800817e: bd80 pop {r7, pc} 08008180 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8008180: b580 push {r7, lr} 8008182: b086 sub sp, #24 8008184: af00 add r7, sp, #0 8008186: 6078 str r0, [r7, #4] 8008188: 6039 str r1, [r7, #0] uint32_t tmperror; uint32_t tmpITFlags = ITFlags; 800818a: 683b ldr r3, [r7, #0] 800818c: 617b str r3, [r7, #20] __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 800818e: 687b ldr r3, [r7, #4] 8008190: 681b ldr r3, [r3, #0] 8008192: 2220 movs r2, #32 8008194: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8008196: 687b ldr r3, [r7, #4] 8008198: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800819c: b2db uxtb r3, r3 800819e: 2b21 cmp r3, #33 @ 0x21 80081a0: d107 bne.n 80081b2 { I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 80081a2: 2101 movs r1, #1 80081a4: 6878 ldr r0, [r7, #4] 80081a6: f000 fd31 bl 8008c0c hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 80081aa: 687b ldr r3, [r7, #4] 80081ac: 2211 movs r2, #17 80081ae: 631a str r2, [r3, #48] @ 0x30 80081b0: e00c b.n 80081cc } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 80081b2: 687b ldr r3, [r7, #4] 80081b4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80081b8: b2db uxtb r3, r3 80081ba: 2b22 cmp r3, #34 @ 0x22 80081bc: d106 bne.n 80081cc { I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 80081be: 2102 movs r1, #2 80081c0: 6878 ldr r0, [r7, #4] 80081c2: f000 fd23 bl 8008c0c hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 80081c6: 687b ldr r3, [r7, #4] 80081c8: 2212 movs r2, #18 80081ca: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80081cc: 687b ldr r3, [r7, #4] 80081ce: 681b ldr r3, [r3, #0] 80081d0: 6859 ldr r1, [r3, #4] 80081d2: 687b ldr r3, [r7, #4] 80081d4: 681a ldr r2, [r3, #0] 80081d6: 4b4d ldr r3, [pc, #308] @ (800830c ) 80081d8: 400b ands r3, r1 80081da: 6053 str r3, [r2, #4] /* Reset handle parameters */ hi2c->XferISR = NULL; 80081dc: 687b ldr r3, [r7, #4] 80081de: 2200 movs r2, #0 80081e0: 635a str r2, [r3, #52] @ 0x34 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80081e2: 687b ldr r3, [r7, #4] 80081e4: 4a4a ldr r2, [pc, #296] @ (8008310 ) 80081e6: 62da str r2, [r3, #44] @ 0x2c if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) 80081e8: 697b ldr r3, [r7, #20] 80081ea: 091b lsrs r3, r3, #4 80081ec: f003 0301 and.w r3, r3, #1 80081f0: 2b00 cmp r3, #0 80081f2: d009 beq.n 8008208 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80081f4: 687b ldr r3, [r7, #4] 80081f6: 681b ldr r3, [r3, #0] 80081f8: 2210 movs r2, #16 80081fa: 61da str r2, [r3, #28] /* Set acknowledge error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80081fc: 687b ldr r3, [r7, #4] 80081fe: 6c5b ldr r3, [r3, #68] @ 0x44 8008200: f043 0204 orr.w r2, r3, #4 8008204: 687b ldr r3, [r7, #4] 8008206: 645a str r2, [r3, #68] @ 0x44 } /* Fetch Last receive data if any */ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) 8008208: 687b ldr r3, [r7, #4] 800820a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800820e: b2db uxtb r3, r3 8008210: 2b60 cmp r3, #96 @ 0x60 8008212: d10b bne.n 800822c 8008214: 697b ldr r3, [r7, #20] 8008216: 089b lsrs r3, r3, #2 8008218: f003 0301 and.w r3, r3, #1 800821c: 2b00 cmp r3, #0 800821e: d005 beq.n 800822c { /* Read data from RXDR */ tmpreg = (uint8_t)hi2c->Instance->RXDR; 8008220: 687b ldr r3, [r7, #4] 8008222: 681b ldr r3, [r3, #0] 8008224: 6a5b ldr r3, [r3, #36] @ 0x24 8008226: b2db uxtb r3, r3 8008228: 60fb str r3, [r7, #12] UNUSED(tmpreg); 800822a: 68fb ldr r3, [r7, #12] } /* Flush TX register */ I2C_Flush_TXDR(hi2c); 800822c: 6878 ldr r0, [r7, #4] 800822e: f000 fb48 bl 80088c2 /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 8008232: 687b ldr r3, [r7, #4] 8008234: 6c5b ldr r3, [r3, #68] @ 0x44 8008236: 613b str r3, [r7, #16] /* Call the corresponding callback to inform upper layer of End of Transfer */ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) 8008238: 687b ldr r3, [r7, #4] 800823a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800823e: b2db uxtb r3, r3 8008240: 2b60 cmp r3, #96 @ 0x60 8008242: d002 beq.n 800824a 8008244: 693b ldr r3, [r7, #16] 8008246: 2b00 cmp r3, #0 8008248: d006 beq.n 8008258 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 800824a: 687b ldr r3, [r7, #4] 800824c: 6c5b ldr r3, [r3, #68] @ 0x44 800824e: 4619 mov r1, r3 8008250: 6878 ldr r0, [r7, #4] 8008252: f000 fa1f bl 8008694 } else { /* Nothing to do */ } } 8008256: e054 b.n 8008302 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8008258: 687b ldr r3, [r7, #4] 800825a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800825e: b2db uxtb r3, r3 8008260: 2b21 cmp r3, #33 @ 0x21 8008262: d124 bne.n 80082ae hi2c->State = HAL_I2C_STATE_READY; 8008264: 687b ldr r3, [r7, #4] 8008266: 2220 movs r2, #32 8008268: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 800826c: 687b ldr r3, [r7, #4] 800826e: 2200 movs r2, #0 8008270: 631a str r2, [r3, #48] @ 0x30 if (hi2c->Mode == HAL_I2C_MODE_MEM) 8008272: 687b ldr r3, [r7, #4] 8008274: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8008278: b2db uxtb r3, r3 800827a: 2b40 cmp r3, #64 @ 0x40 800827c: d10b bne.n 8008296 hi2c->Mode = HAL_I2C_MODE_NONE; 800827e: 687b ldr r3, [r7, #4] 8008280: 2200 movs r2, #0 8008282: f883 2042 strb.w r2, [r3, #66] @ 0x42 __HAL_UNLOCK(hi2c); 8008286: 687b ldr r3, [r7, #4] 8008288: 2200 movs r2, #0 800828a: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MemTxCpltCallback(hi2c); 800828e: 6878 ldr r0, [r7, #4] 8008290: f7fd f822 bl 80052d8 } 8008294: e035 b.n 8008302 hi2c->Mode = HAL_I2C_MODE_NONE; 8008296: 687b ldr r3, [r7, #4] 8008298: 2200 movs r2, #0 800829a: f883 2042 strb.w r2, [r3, #66] @ 0x42 __HAL_UNLOCK(hi2c); 800829e: 687b ldr r3, [r7, #4] 80082a0: 2200 movs r2, #0 80082a2: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MasterTxCpltCallback(hi2c); 80082a6: 6878 ldr r0, [r7, #4] 80082a8: f7ff f9ed bl 8007686 } 80082ac: e029 b.n 8008302 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 80082ae: 687b ldr r3, [r7, #4] 80082b0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80082b4: b2db uxtb r3, r3 80082b6: 2b22 cmp r3, #34 @ 0x22 80082b8: d123 bne.n 8008302 hi2c->State = HAL_I2C_STATE_READY; 80082ba: 687b ldr r3, [r7, #4] 80082bc: 2220 movs r2, #32 80082be: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 80082c2: 687b ldr r3, [r7, #4] 80082c4: 2200 movs r2, #0 80082c6: 631a str r2, [r3, #48] @ 0x30 if (hi2c->Mode == HAL_I2C_MODE_MEM) 80082c8: 687b ldr r3, [r7, #4] 80082ca: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 80082ce: b2db uxtb r3, r3 80082d0: 2b40 cmp r3, #64 @ 0x40 80082d2: d10b bne.n 80082ec hi2c->Mode = HAL_I2C_MODE_NONE; 80082d4: 687b ldr r3, [r7, #4] 80082d6: 2200 movs r2, #0 80082d8: f883 2042 strb.w r2, [r3, #66] @ 0x42 __HAL_UNLOCK(hi2c); 80082dc: 687b ldr r3, [r7, #4] 80082de: 2200 movs r2, #0 80082e0: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MemRxCpltCallback(hi2c); 80082e4: 6878 ldr r0, [r7, #4] 80082e6: f7fc ffcf bl 8005288 } 80082ea: e00a b.n 8008302 hi2c->Mode = HAL_I2C_MODE_NONE; 80082ec: 687b ldr r3, [r7, #4] 80082ee: 2200 movs r2, #0 80082f0: f883 2042 strb.w r2, [r3, #66] @ 0x42 __HAL_UNLOCK(hi2c); 80082f4: 687b ldr r3, [r7, #4] 80082f6: 2200 movs r2, #0 80082f8: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MasterRxCpltCallback(hi2c); 80082fc: 6878 ldr r0, [r7, #4] 80082fe: f7ff f9cc bl 800769a } 8008302: bf00 nop 8008304: 3718 adds r7, #24 8008306: 46bd mov sp, r7 8008308: bd80 pop {r7, pc} 800830a: bf00 nop 800830c: fe00e800 .word 0xfe00e800 8008310: ffff0000 .word 0xffff0000 08008314 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8008314: b580 push {r7, lr} 8008316: b086 sub sp, #24 8008318: af00 add r7, sp, #0 800831a: 6078 str r0, [r7, #4] 800831c: 6039 str r1, [r7, #0] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 800831e: 687b ldr r3, [r7, #4] 8008320: 681b ldr r3, [r3, #0] 8008322: 681b ldr r3, [r3, #0] 8008324: 613b str r3, [r7, #16] uint32_t tmpITFlags = ITFlags; 8008326: 683b ldr r3, [r7, #0] 8008328: 617b str r3, [r7, #20] uint32_t tmpoptions = hi2c->XferOptions; 800832a: 687b ldr r3, [r7, #4] 800832c: 6adb ldr r3, [r3, #44] @ 0x2c 800832e: 60fb str r3, [r7, #12] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 8008330: 687b ldr r3, [r7, #4] 8008332: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008336: 72fb strb r3, [r7, #11] /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8008338: 687b ldr r3, [r7, #4] 800833a: 681b ldr r3, [r3, #0] 800833c: 2220 movs r2, #32 800833e: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 8008340: 7afb ldrb r3, [r7, #11] 8008342: 2b21 cmp r3, #33 @ 0x21 8008344: d002 beq.n 800834c 8008346: 7afb ldrb r3, [r7, #11] 8008348: 2b29 cmp r3, #41 @ 0x29 800834a: d108 bne.n 800835e { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); 800834c: f248 0101 movw r1, #32769 @ 0x8001 8008350: 6878 ldr r0, [r7, #4] 8008352: f000 fc5b bl 8008c0c hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 8008356: 687b ldr r3, [r7, #4] 8008358: 2221 movs r2, #33 @ 0x21 800835a: 631a str r2, [r3, #48] @ 0x30 800835c: e019 b.n 8008392 } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 800835e: 7afb ldrb r3, [r7, #11] 8008360: 2b22 cmp r3, #34 @ 0x22 8008362: d002 beq.n 800836a 8008364: 7afb ldrb r3, [r7, #11] 8008366: 2b2a cmp r3, #42 @ 0x2a 8008368: d108 bne.n 800837c { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); 800836a: f248 0102 movw r1, #32770 @ 0x8002 800836e: 6878 ldr r0, [r7, #4] 8008370: f000 fc4c bl 8008c0c hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 8008374: 687b ldr r3, [r7, #4] 8008376: 2222 movs r2, #34 @ 0x22 8008378: 631a str r2, [r3, #48] @ 0x30 800837a: e00a b.n 8008392 } else if (tmpstate == HAL_I2C_STATE_LISTEN) 800837c: 7afb ldrb r3, [r7, #11] 800837e: 2b28 cmp r3, #40 @ 0x28 8008380: d107 bne.n 8008392 { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); 8008382: f248 0103 movw r1, #32771 @ 0x8003 8008386: 6878 ldr r0, [r7, #4] 8008388: f000 fc40 bl 8008c0c hi2c->PreviousState = I2C_STATE_NONE; 800838c: 687b ldr r3, [r7, #4] 800838e: 2200 movs r2, #0 8008390: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; 8008392: 687b ldr r3, [r7, #4] 8008394: 681b ldr r3, [r3, #0] 8008396: 685a ldr r2, [r3, #4] 8008398: 687b ldr r3, [r7, #4] 800839a: 681b ldr r3, [r3, #0] 800839c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80083a0: 605a str r2, [r3, #4] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80083a2: 687b ldr r3, [r7, #4] 80083a4: 681b ldr r3, [r3, #0] 80083a6: 6859 ldr r1, [r3, #4] 80083a8: 687b ldr r3, [r7, #4] 80083aa: 681a ldr r2, [r3, #0] 80083ac: 4b8c ldr r3, [pc, #560] @ (80085e0 ) 80083ae: 400b ands r3, r1 80083b0: 6053 str r3, [r2, #4] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80083b2: 6878 ldr r0, [r7, #4] 80083b4: f000 fa85 bl 80088c2 #if defined(HAL_DMA_MODULE_ENABLED) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 80083b8: 693b ldr r3, [r7, #16] 80083ba: 0b9b lsrs r3, r3, #14 80083bc: f003 0301 and.w r3, r3, #1 80083c0: 2b00 cmp r3, #0 80083c2: d013 beq.n 80083ec { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 80083c4: 687b ldr r3, [r7, #4] 80083c6: 681b ldr r3, [r3, #0] 80083c8: 681a ldr r2, [r3, #0] 80083ca: 687b ldr r3, [r7, #4] 80083cc: 681b ldr r3, [r3, #0] 80083ce: f422 4280 bic.w r2, r2, #16384 @ 0x4000 80083d2: 601a str r2, [r3, #0] if (hi2c->hdmatx != NULL) 80083d4: 687b ldr r3, [r7, #4] 80083d6: 6b9b ldr r3, [r3, #56] @ 0x38 80083d8: 2b00 cmp r3, #0 80083da: d020 beq.n 800841e { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); 80083dc: 687b ldr r3, [r7, #4] 80083de: 6b9b ldr r3, [r3, #56] @ 0x38 80083e0: 681b ldr r3, [r3, #0] 80083e2: 685b ldr r3, [r3, #4] 80083e4: b29a uxth r2, r3 80083e6: 687b ldr r3, [r7, #4] 80083e8: 855a strh r2, [r3, #42] @ 0x2a 80083ea: e018 b.n 800841e } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 80083ec: 693b ldr r3, [r7, #16] 80083ee: 0bdb lsrs r3, r3, #15 80083f0: f003 0301 and.w r3, r3, #1 80083f4: 2b00 cmp r3, #0 80083f6: d012 beq.n 800841e { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 80083f8: 687b ldr r3, [r7, #4] 80083fa: 681b ldr r3, [r3, #0] 80083fc: 681a ldr r2, [r3, #0] 80083fe: 687b ldr r3, [r7, #4] 8008400: 681b ldr r3, [r3, #0] 8008402: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8008406: 601a str r2, [r3, #0] if (hi2c->hdmarx != NULL) 8008408: 687b ldr r3, [r7, #4] 800840a: 6bdb ldr r3, [r3, #60] @ 0x3c 800840c: 2b00 cmp r3, #0 800840e: d006 beq.n 800841e { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); 8008410: 687b ldr r3, [r7, #4] 8008412: 6bdb ldr r3, [r3, #60] @ 0x3c 8008414: 681b ldr r3, [r3, #0] 8008416: 685b ldr r3, [r3, #4] 8008418: b29a uxth r2, r3 800841a: 687b ldr r3, [r7, #4] 800841c: 855a strh r2, [r3, #42] @ 0x2a /* Do nothing */ } #endif /* HAL_DMA_MODULE_ENABLED */ /* Store Last receive data if any */ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) 800841e: 697b ldr r3, [r7, #20] 8008420: 089b lsrs r3, r3, #2 8008422: f003 0301 and.w r3, r3, #1 8008426: 2b00 cmp r3, #0 8008428: d020 beq.n 800846c { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; 800842a: 697b ldr r3, [r7, #20] 800842c: f023 0304 bic.w r3, r3, #4 8008430: 617b str r3, [r7, #20] /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8008432: 687b ldr r3, [r7, #4] 8008434: 681b ldr r3, [r3, #0] 8008436: 6a5a ldr r2, [r3, #36] @ 0x24 8008438: 687b ldr r3, [r7, #4] 800843a: 6a5b ldr r3, [r3, #36] @ 0x24 800843c: b2d2 uxtb r2, r2 800843e: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8008440: 687b ldr r3, [r7, #4] 8008442: 6a5b ldr r3, [r3, #36] @ 0x24 8008444: 1c5a adds r2, r3, #1 8008446: 687b ldr r3, [r7, #4] 8008448: 625a str r2, [r3, #36] @ 0x24 if (hi2c->XferSize > 0U) 800844a: 687b ldr r3, [r7, #4] 800844c: 8d1b ldrh r3, [r3, #40] @ 0x28 800844e: 2b00 cmp r3, #0 8008450: d00c beq.n 800846c { hi2c->XferSize--; 8008452: 687b ldr r3, [r7, #4] 8008454: 8d1b ldrh r3, [r3, #40] @ 0x28 8008456: 3b01 subs r3, #1 8008458: b29a uxth r2, r3 800845a: 687b ldr r3, [r7, #4] 800845c: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 800845e: 687b ldr r3, [r7, #4] 8008460: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008462: b29b uxth r3, r3 8008464: 3b01 subs r3, #1 8008466: b29a uxth r2, r3 8008468: 687b ldr r3, [r7, #4] 800846a: 855a strh r2, [r3, #42] @ 0x2a } } /* All data are not transferred, so set error code accordingly */ if (hi2c->XferCount != 0U) 800846c: 687b ldr r3, [r7, #4] 800846e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008470: b29b uxth r3, r3 8008472: 2b00 cmp r3, #0 8008474: d005 beq.n 8008482 { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008476: 687b ldr r3, [r7, #4] 8008478: 6c5b ldr r3, [r3, #68] @ 0x44 800847a: f043 0204 orr.w r2, r3, #4 800847e: 687b ldr r3, [r7, #4] 8008480: 645a str r2, [r3, #68] @ 0x44 } if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8008482: 697b ldr r3, [r7, #20] 8008484: 091b lsrs r3, r3, #4 8008486: f003 0301 and.w r3, r3, #1 800848a: 2b00 cmp r3, #0 800848c: d04a beq.n 8008524 (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) 800848e: 693b ldr r3, [r7, #16] 8008490: 091b lsrs r3, r3, #4 8008492: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8008496: 2b00 cmp r3, #0 8008498: d044 beq.n 8008524 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 800849a: 687b ldr r3, [r7, #4] 800849c: 8d5b ldrh r3, [r3, #42] @ 0x2a 800849e: b29b uxth r3, r3 80084a0: 2b00 cmp r3, #0 80084a2: d128 bne.n 80084f6 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 80084a4: 687b ldr r3, [r7, #4] 80084a6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80084aa: b2db uxtb r3, r3 80084ac: 2b28 cmp r3, #40 @ 0x28 80084ae: d108 bne.n 80084c2 80084b0: 68fb ldr r3, [r7, #12] 80084b2: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80084b6: d104 bne.n 80084c2 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 80084b8: 6979 ldr r1, [r7, #20] 80084ba: 6878 ldr r0, [r7, #4] 80084bc: f000 f894 bl 80085e8 80084c0: e030 b.n 8008524 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 80084c2: 687b ldr r3, [r7, #4] 80084c4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80084c8: b2db uxtb r3, r3 80084ca: 2b29 cmp r3, #41 @ 0x29 80084cc: d10e bne.n 80084ec 80084ce: 68fb ldr r3, [r7, #12] 80084d0: f513 3f80 cmn.w r3, #65536 @ 0x10000 80084d4: d00a beq.n 80084ec { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80084d6: 687b ldr r3, [r7, #4] 80084d8: 681b ldr r3, [r3, #0] 80084da: 2210 movs r2, #16 80084dc: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80084de: 6878 ldr r0, [r7, #4] 80084e0: f000 f9ef bl 80088c2 /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 80084e4: 6878 ldr r0, [r7, #4] 80084e6: f7ff fded bl 80080c4 80084ea: e01b b.n 8008524 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80084ec: 687b ldr r3, [r7, #4] 80084ee: 681b ldr r3, [r3, #0] 80084f0: 2210 movs r2, #16 80084f2: 61da str r2, [r3, #28] 80084f4: e016 b.n 8008524 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80084f6: 687b ldr r3, [r7, #4] 80084f8: 681b ldr r3, [r3, #0] 80084fa: 2210 movs r2, #16 80084fc: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80084fe: 687b ldr r3, [r7, #4] 8008500: 6c5b ldr r3, [r3, #68] @ 0x44 8008502: f043 0204 orr.w r2, r3, #4 8008506: 687b ldr r3, [r7, #4] 8008508: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 800850a: 68fb ldr r3, [r7, #12] 800850c: 2b00 cmp r3, #0 800850e: d003 beq.n 8008518 8008510: 68fb ldr r3, [r7, #12] 8008512: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8008516: d105 bne.n 8008524 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8008518: 687b ldr r3, [r7, #4] 800851a: 6c5b ldr r3, [r3, #68] @ 0x44 800851c: 4619 mov r1, r3 800851e: 6878 ldr r0, [r7, #4] 8008520: f000 f8b8 bl 8008694 } } } hi2c->Mode = HAL_I2C_MODE_NONE; 8008524: 687b ldr r3, [r7, #4] 8008526: 2200 movs r2, #0 8008528: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->XferISR = NULL; 800852c: 687b ldr r3, [r7, #4] 800852e: 2200 movs r2, #0 8008530: 635a str r2, [r3, #52] @ 0x34 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 8008532: 687b ldr r3, [r7, #4] 8008534: 6c5b ldr r3, [r3, #68] @ 0x44 8008536: 2b00 cmp r3, #0 8008538: d010 beq.n 800855c { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 800853a: 687b ldr r3, [r7, #4] 800853c: 6c5b ldr r3, [r3, #68] @ 0x44 800853e: 4619 mov r1, r3 8008540: 6878 ldr r0, [r7, #4] 8008542: f000 f8a7 bl 8008694 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ if (hi2c->State == HAL_I2C_STATE_LISTEN) 8008546: 687b ldr r3, [r7, #4] 8008548: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800854c: b2db uxtb r3, r3 800854e: 2b28 cmp r3, #40 @ 0x28 8008550: d141 bne.n 80085d6 { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8008552: 6979 ldr r1, [r7, #20] 8008554: 6878 ldr r0, [r7, #4] 8008556: f000 f847 bl 80085e8 hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 800855a: e03c b.n 80085d6 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 800855c: 687b ldr r3, [r7, #4] 800855e: 6adb ldr r3, [r3, #44] @ 0x2c 8008560: f513 3f80 cmn.w r3, #65536 @ 0x10000 8008564: d014 beq.n 8008590 I2C_ITSlaveSeqCplt(hi2c); 8008566: 6878 ldr r0, [r7, #4] 8008568: f7ff fdac bl 80080c4 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 800856c: 687b ldr r3, [r7, #4] 800856e: 4a1d ldr r2, [pc, #116] @ (80085e4 ) 8008570: 62da str r2, [r3, #44] @ 0x2c hi2c->State = HAL_I2C_STATE_READY; 8008572: 687b ldr r3, [r7, #4] 8008574: 2220 movs r2, #32 8008576: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 800857a: 687b ldr r3, [r7, #4] 800857c: 2200 movs r2, #0 800857e: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8008580: 687b ldr r3, [r7, #4] 8008582: 2200 movs r2, #0 8008584: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_ListenCpltCallback(hi2c); 8008588: 6878 ldr r0, [r7, #4] 800858a: f7ff f8b2 bl 80076f2 } 800858e: e022 b.n 80085d6 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8008590: 687b ldr r3, [r7, #4] 8008592: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008596: b2db uxtb r3, r3 8008598: 2b22 cmp r3, #34 @ 0x22 800859a: d10e bne.n 80085ba hi2c->State = HAL_I2C_STATE_READY; 800859c: 687b ldr r3, [r7, #4] 800859e: 2220 movs r2, #32 80085a0: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 80085a4: 687b ldr r3, [r7, #4] 80085a6: 2200 movs r2, #0 80085a8: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 80085aa: 687b ldr r3, [r7, #4] 80085ac: 2200 movs r2, #0 80085ae: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_SlaveRxCpltCallback(hi2c); 80085b2: 6878 ldr r0, [r7, #4] 80085b4: f7ff f885 bl 80076c2 } 80085b8: e00d b.n 80085d6 hi2c->State = HAL_I2C_STATE_READY; 80085ba: 687b ldr r3, [r7, #4] 80085bc: 2220 movs r2, #32 80085be: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 80085c2: 687b ldr r3, [r7, #4] 80085c4: 2200 movs r2, #0 80085c6: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 80085c8: 687b ldr r3, [r7, #4] 80085ca: 2200 movs r2, #0 80085cc: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_SlaveTxCpltCallback(hi2c); 80085d0: 6878 ldr r0, [r7, #4] 80085d2: f7ff f86c bl 80076ae } 80085d6: bf00 nop 80085d8: 3718 adds r7, #24 80085da: 46bd mov sp, r7 80085dc: bd80 pop {r7, pc} 80085de: bf00 nop 80085e0: fe00e800 .word 0xfe00e800 80085e4: ffff0000 .word 0xffff0000 080085e8 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 80085e8: b580 push {r7, lr} 80085ea: b082 sub sp, #8 80085ec: af00 add r7, sp, #0 80085ee: 6078 str r0, [r7, #4] 80085f0: 6039 str r1, [r7, #0] /* Reset handle parameters */ hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80085f2: 687b ldr r3, [r7, #4] 80085f4: 4a26 ldr r2, [pc, #152] @ (8008690 ) 80085f6: 62da str r2, [r3, #44] @ 0x2c hi2c->PreviousState = I2C_STATE_NONE; 80085f8: 687b ldr r3, [r7, #4] 80085fa: 2200 movs r2, #0 80085fc: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 80085fe: 687b ldr r3, [r7, #4] 8008600: 2220 movs r2, #32 8008602: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8008606: 687b ldr r3, [r7, #4] 8008608: 2200 movs r2, #0 800860a: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->XferISR = NULL; 800860e: 687b ldr r3, [r7, #4] 8008610: 2200 movs r2, #0 8008612: 635a str r2, [r3, #52] @ 0x34 /* Store Last receive data if any */ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) 8008614: 683b ldr r3, [r7, #0] 8008616: 089b lsrs r3, r3, #2 8008618: f003 0301 and.w r3, r3, #1 800861c: 2b00 cmp r3, #0 800861e: d022 beq.n 8008666 { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8008620: 687b ldr r3, [r7, #4] 8008622: 681b ldr r3, [r3, #0] 8008624: 6a5a ldr r2, [r3, #36] @ 0x24 8008626: 687b ldr r3, [r7, #4] 8008628: 6a5b ldr r3, [r3, #36] @ 0x24 800862a: b2d2 uxtb r2, r2 800862c: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800862e: 687b ldr r3, [r7, #4] 8008630: 6a5b ldr r3, [r3, #36] @ 0x24 8008632: 1c5a adds r2, r3, #1 8008634: 687b ldr r3, [r7, #4] 8008636: 625a str r2, [r3, #36] @ 0x24 if (hi2c->XferSize > 0U) 8008638: 687b ldr r3, [r7, #4] 800863a: 8d1b ldrh r3, [r3, #40] @ 0x28 800863c: 2b00 cmp r3, #0 800863e: d012 beq.n 8008666 { hi2c->XferSize--; 8008640: 687b ldr r3, [r7, #4] 8008642: 8d1b ldrh r3, [r3, #40] @ 0x28 8008644: 3b01 subs r3, #1 8008646: b29a uxth r2, r3 8008648: 687b ldr r3, [r7, #4] 800864a: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 800864c: 687b ldr r3, [r7, #4] 800864e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008650: b29b uxth r3, r3 8008652: 3b01 subs r3, #1 8008654: b29a uxth r2, r3 8008656: 687b ldr r3, [r7, #4] 8008658: 855a strh r2, [r3, #42] @ 0x2a /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 800865a: 687b ldr r3, [r7, #4] 800865c: 6c5b ldr r3, [r3, #68] @ 0x44 800865e: f043 0204 orr.w r2, r3, #4 8008662: 687b ldr r3, [r7, #4] 8008664: 645a str r2, [r3, #68] @ 0x44 } } /* Disable all Interrupts*/ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8008666: f248 0103 movw r1, #32771 @ 0x8003 800866a: 6878 ldr r0, [r7, #4] 800866c: f000 face bl 8008c0c /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008670: 687b ldr r3, [r7, #4] 8008672: 681b ldr r3, [r3, #0] 8008674: 2210 movs r2, #16 8008676: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008678: 687b ldr r3, [r7, #4] 800867a: 2200 movs r2, #0 800867c: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ListenCpltCallback(hi2c); #else HAL_I2C_ListenCpltCallback(hi2c); 8008680: 6878 ldr r0, [r7, #4] 8008682: f7ff f836 bl 80076f2 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } 8008686: bf00 nop 8008688: 3708 adds r7, #8 800868a: 46bd mov sp, r7 800868c: bd80 pop {r7, pc} 800868e: bf00 nop 8008690: ffff0000 .word 0xffff0000 08008694 : * @param hi2c I2C handle. * @param ErrorCode Error code to handle. * @retval None */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { 8008694: b580 push {r7, lr} 8008696: b084 sub sp, #16 8008698: af00 add r7, sp, #0 800869a: 6078 str r0, [r7, #4] 800869c: 6039 str r1, [r7, #0] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 800869e: 687b ldr r3, [r7, #4] 80086a0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80086a4: 73fb strb r3, [r7, #15] #if defined(HAL_DMA_MODULE_ENABLED) uint32_t tmppreviousstate; #endif /* HAL_DMA_MODULE_ENABLED */ /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; 80086a6: 687b ldr r3, [r7, #4] 80086a8: 2200 movs r2, #0 80086aa: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80086ae: 687b ldr r3, [r7, #4] 80086b0: 4a6d ldr r2, [pc, #436] @ (8008868 ) 80086b2: 62da str r2, [r3, #44] @ 0x2c hi2c->XferCount = 0U; 80086b4: 687b ldr r3, [r7, #4] 80086b6: 2200 movs r2, #0 80086b8: 855a strh r2, [r3, #42] @ 0x2a /* Set new error code */ hi2c->ErrorCode |= ErrorCode; 80086ba: 687b ldr r3, [r7, #4] 80086bc: 6c5a ldr r2, [r3, #68] @ 0x44 80086be: 683b ldr r3, [r7, #0] 80086c0: 431a orrs r2, r3 80086c2: 687b ldr r3, [r7, #4] 80086c4: 645a str r2, [r3, #68] @ 0x44 /* Disable Interrupts */ if ((tmpstate == HAL_I2C_STATE_LISTEN) || 80086c6: 7bfb ldrb r3, [r7, #15] 80086c8: 2b28 cmp r3, #40 @ 0x28 80086ca: d005 beq.n 80086d8 80086cc: 7bfb ldrb r3, [r7, #15] 80086ce: 2b29 cmp r3, #41 @ 0x29 80086d0: d002 beq.n 80086d8 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || 80086d2: 7bfb ldrb r3, [r7, #15] 80086d4: 2b2a cmp r3, #42 @ 0x2a 80086d6: d10b bne.n 80086f0 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); 80086d8: 2103 movs r1, #3 80086da: 6878 ldr r0, [r7, #4] 80086dc: f000 fa96 bl 8008c0c /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; 80086e0: 687b ldr r3, [r7, #4] 80086e2: 2228 movs r2, #40 @ 0x28 80086e4: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->XferISR = I2C_Slave_ISR_IT; 80086e8: 687b ldr r3, [r7, #4] 80086ea: 4a60 ldr r2, [pc, #384] @ (800886c ) 80086ec: 635a str r2, [r3, #52] @ 0x34 80086ee: e030 b.n 8008752 } else { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 80086f0: f248 0103 movw r1, #32771 @ 0x8003 80086f4: 6878 ldr r0, [r7, #4] 80086f6: f000 fa89 bl 8008c0c /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80086fa: 6878 ldr r0, [r7, #4] 80086fc: f000 f8e1 bl 80088c2 /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) 8008700: 687b ldr r3, [r7, #4] 8008702: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008706: b2db uxtb r3, r3 8008708: 2b60 cmp r3, #96 @ 0x60 800870a: d01f beq.n 800874c { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; 800870c: 687b ldr r3, [r7, #4] 800870e: 2220 movs r2, #32 8008710: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 8008714: 687b ldr r3, [r7, #4] 8008716: 681b ldr r3, [r3, #0] 8008718: 699b ldr r3, [r3, #24] 800871a: f003 0320 and.w r3, r3, #32 800871e: 2b20 cmp r3, #32 8008720: d114 bne.n 800874c { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 8008722: 687b ldr r3, [r7, #4] 8008724: 681b ldr r3, [r3, #0] 8008726: 699b ldr r3, [r3, #24] 8008728: f003 0310 and.w r3, r3, #16 800872c: 2b10 cmp r3, #16 800872e: d109 bne.n 8008744 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008730: 687b ldr r3, [r7, #4] 8008732: 681b ldr r3, [r3, #0] 8008734: 2210 movs r2, #16 8008736: 61da str r2, [r3, #28] hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008738: 687b ldr r3, [r7, #4] 800873a: 6c5b ldr r3, [r3, #68] @ 0x44 800873c: f043 0204 orr.w r2, r3, #4 8008740: 687b ldr r3, [r7, #4] 8008742: 645a str r2, [r3, #68] @ 0x44 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8008744: 687b ldr r3, [r7, #4] 8008746: 681b ldr r3, [r3, #0] 8008748: 2220 movs r2, #32 800874a: 61da str r2, [r3, #28] } } hi2c->XferISR = NULL; 800874c: 687b ldr r3, [r7, #4] 800874e: 2200 movs r2, #0 8008750: 635a str r2, [r3, #52] @ 0x34 } #if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; 8008752: 687b ldr r3, [r7, #4] 8008754: 6b1b ldr r3, [r3, #48] @ 0x30 8008756: 60bb str r3, [r7, #8] if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ 8008758: 687b ldr r3, [r7, #4] 800875a: 6b9b ldr r3, [r3, #56] @ 0x38 800875c: 2b00 cmp r3, #0 800875e: d039 beq.n 80087d4 8008760: 68bb ldr r3, [r7, #8] 8008762: 2b11 cmp r3, #17 8008764: d002 beq.n 800876c 8008766: 68bb ldr r3, [r7, #8] 8008768: 2b21 cmp r3, #33 @ 0x21 800876a: d133 bne.n 80087d4 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) 800876c: 687b ldr r3, [r7, #4] 800876e: 681b ldr r3, [r3, #0] 8008770: 681b ldr r3, [r3, #0] 8008772: f403 4380 and.w r3, r3, #16384 @ 0x4000 8008776: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800877a: d107 bne.n 800878c { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 800877c: 687b ldr r3, [r7, #4] 800877e: 681b ldr r3, [r3, #0] 8008780: 681a ldr r2, [r3, #0] 8008782: 687b ldr r3, [r7, #4] 8008784: 681b ldr r3, [r3, #0] 8008786: f422 4280 bic.w r2, r2, #16384 @ 0x4000 800878a: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 800878c: 687b ldr r3, [r7, #4] 800878e: 6b9b ldr r3, [r3, #56] @ 0x38 8008790: 4618 mov r0, r3 8008792: f7fe fa20 bl 8006bd6 8008796: 4603 mov r3, r0 8008798: 2b01 cmp r3, #1 800879a: d017 beq.n 80087cc { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 800879c: 687b ldr r3, [r7, #4] 800879e: 6b9b ldr r3, [r3, #56] @ 0x38 80087a0: 4a33 ldr r2, [pc, #204] @ (8008870 ) 80087a2: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80087a4: 687b ldr r3, [r7, #4] 80087a6: 2200 movs r2, #0 80087a8: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 80087ac: 687b ldr r3, [r7, #4] 80087ae: 6b9b ldr r3, [r3, #56] @ 0x38 80087b0: 4618 mov r0, r3 80087b2: f7fe f902 bl 80069ba 80087b6: 4603 mov r3, r0 80087b8: 2b00 cmp r3, #0 80087ba: d04d beq.n 8008858 { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 80087bc: 687b ldr r3, [r7, #4] 80087be: 6b9b ldr r3, [r3, #56] @ 0x38 80087c0: 6b9b ldr r3, [r3, #56] @ 0x38 80087c2: 687a ldr r2, [r7, #4] 80087c4: 6b92 ldr r2, [r2, #56] @ 0x38 80087c6: 4610 mov r0, r2 80087c8: 4798 blx r3 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 80087ca: e045 b.n 8008858 } } else { I2C_TreatErrorCallback(hi2c); 80087cc: 6878 ldr r0, [r7, #4] 80087ce: f000 f851 bl 8008874 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 80087d2: e041 b.n 8008858 } } /* Abort DMA RX transfer if any */ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ 80087d4: 687b ldr r3, [r7, #4] 80087d6: 6bdb ldr r3, [r3, #60] @ 0x3c 80087d8: 2b00 cmp r3, #0 80087da: d039 beq.n 8008850 80087dc: 68bb ldr r3, [r7, #8] 80087de: 2b12 cmp r3, #18 80087e0: d002 beq.n 80087e8 80087e2: 68bb ldr r3, [r7, #8] 80087e4: 2b22 cmp r3, #34 @ 0x22 80087e6: d133 bne.n 8008850 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) 80087e8: 687b ldr r3, [r7, #4] 80087ea: 681b ldr r3, [r3, #0] 80087ec: 681b ldr r3, [r3, #0] 80087ee: f403 4300 and.w r3, r3, #32768 @ 0x8000 80087f2: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80087f6: d107 bne.n 8008808 { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 80087f8: 687b ldr r3, [r7, #4] 80087fa: 681b ldr r3, [r3, #0] 80087fc: 681a ldr r2, [r3, #0] 80087fe: 687b ldr r3, [r7, #4] 8008800: 681b ldr r3, [r3, #0] 8008802: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8008806: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8008808: 687b ldr r3, [r7, #4] 800880a: 6bdb ldr r3, [r3, #60] @ 0x3c 800880c: 4618 mov r0, r3 800880e: f7fe f9e2 bl 8006bd6 8008812: 4603 mov r3, r0 8008814: 2b01 cmp r3, #1 8008816: d017 beq.n 8008848 { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 8008818: 687b ldr r3, [r7, #4] 800881a: 6bdb ldr r3, [r3, #60] @ 0x3c 800881c: 4a14 ldr r2, [pc, #80] @ (8008870 ) 800881e: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008820: 687b ldr r3, [r7, #4] 8008822: 2200 movs r2, #0 8008824: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 8008828: 687b ldr r3, [r7, #4] 800882a: 6bdb ldr r3, [r3, #60] @ 0x3c 800882c: 4618 mov r0, r3 800882e: f7fe f8c4 bl 80069ba 8008832: 4603 mov r3, r0 8008834: 2b00 cmp r3, #0 8008836: d011 beq.n 800885c { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 8008838: 687b ldr r3, [r7, #4] 800883a: 6bdb ldr r3, [r3, #60] @ 0x3c 800883c: 6b9b ldr r3, [r3, #56] @ 0x38 800883e: 687a ldr r2, [r7, #4] 8008840: 6bd2 ldr r2, [r2, #60] @ 0x3c 8008842: 4610 mov r0, r2 8008844: 4798 blx r3 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8008846: e009 b.n 800885c } } else { I2C_TreatErrorCallback(hi2c); 8008848: 6878 ldr r0, [r7, #4] 800884a: f000 f813 bl 8008874 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 800884e: e005 b.n 800885c } } else #endif /* HAL_DMA_MODULE_ENABLED */ { I2C_TreatErrorCallback(hi2c); 8008850: 6878 ldr r0, [r7, #4] 8008852: f000 f80f bl 8008874 } } 8008856: e002 b.n 800885e if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8008858: bf00 nop 800885a: e000 b.n 800885e if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 800885c: bf00 nop } 800885e: bf00 nop 8008860: 3710 adds r7, #16 8008862: 46bd mov sp, r7 8008864: bd80 pop {r7, pc} 8008866: bf00 nop 8008868: ffff0000 .word 0xffff0000 800886c: 08007733 .word 0x08007733 8008870: 08008a65 .word 0x08008a65 08008874 : * @brief I2C Error callback treatment. * @param hi2c I2C handle. * @retval None */ static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) { 8008874: b580 push {r7, lr} 8008876: b082 sub sp, #8 8008878: af00 add r7, sp, #0 800887a: 6078 str r0, [r7, #4] if (hi2c->State == HAL_I2C_STATE_ABORT) 800887c: 687b ldr r3, [r7, #4] 800887e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008882: b2db uxtb r3, r3 8008884: 2b60 cmp r3, #96 @ 0x60 8008886: d10e bne.n 80088a6 { hi2c->State = HAL_I2C_STATE_READY; 8008888: 687b ldr r3, [r7, #4] 800888a: 2220 movs r2, #32 800888c: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 8008890: 687b ldr r3, [r7, #4] 8008892: 2200 movs r2, #0 8008894: 631a str r2, [r3, #48] @ 0x30 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008896: 687b ldr r3, [r7, #4] 8008898: 2200 movs r2, #0 800889a: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AbortCpltCallback(hi2c); #else HAL_I2C_AbortCpltCallback(hi2c); 800889e: 6878 ldr r0, [r7, #4] 80088a0: f7fe ff31 bl 8007706 hi2c->ErrorCallback(hi2c); #else HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 80088a4: e009 b.n 80088ba hi2c->PreviousState = I2C_STATE_NONE; 80088a6: 687b ldr r3, [r7, #4] 80088a8: 2200 movs r2, #0 80088aa: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 80088ac: 687b ldr r3, [r7, #4] 80088ae: 2200 movs r2, #0 80088b0: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_ErrorCallback(hi2c); 80088b4: 6878 ldr r0, [r7, #4] 80088b6: f7fc fd37 bl 8005328 } 80088ba: bf00 nop 80088bc: 3708 adds r7, #8 80088be: 46bd mov sp, r7 80088c0: bd80 pop {r7, pc} 080088c2 : * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { 80088c2: b480 push {r7} 80088c4: b083 sub sp, #12 80088c6: af00 add r7, sp, #0 80088c8: 6078 str r0, [r7, #4] /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) 80088ca: 687b ldr r3, [r7, #4] 80088cc: 681b ldr r3, [r3, #0] 80088ce: 699b ldr r3, [r3, #24] 80088d0: f003 0302 and.w r3, r3, #2 80088d4: 2b02 cmp r3, #2 80088d6: d103 bne.n 80088e0 { hi2c->Instance->TXDR = 0x00U; 80088d8: 687b ldr r3, [r7, #4] 80088da: 681b ldr r3, [r3, #0] 80088dc: 2200 movs r2, #0 80088de: 629a str r2, [r3, #40] @ 0x28 } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 80088e0: 687b ldr r3, [r7, #4] 80088e2: 681b ldr r3, [r3, #0] 80088e4: 699b ldr r3, [r3, #24] 80088e6: f003 0301 and.w r3, r3, #1 80088ea: 2b01 cmp r3, #1 80088ec: d007 beq.n 80088fe { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); 80088ee: 687b ldr r3, [r7, #4] 80088f0: 681b ldr r3, [r3, #0] 80088f2: 699a ldr r2, [r3, #24] 80088f4: 687b ldr r3, [r7, #4] 80088f6: 681b ldr r3, [r3, #0] 80088f8: f042 0201 orr.w r2, r2, #1 80088fc: 619a str r2, [r3, #24] } } 80088fe: bf00 nop 8008900: 370c adds r7, #12 8008902: 46bd mov sp, r7 8008904: f85d 7b04 ldr.w r7, [sp], #4 8008908: 4770 bx lr 0800890a : * @brief DMA I2C master transmit process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { 800890a: b580 push {r7, lr} 800890c: b084 sub sp, #16 800890e: af00 add r7, sp, #0 8008910: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8008912: 687b ldr r3, [r7, #4] 8008914: 6a9b ldr r3, [r3, #40] @ 0x28 8008916: 60fb str r3, [r7, #12] /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8008918: 68fb ldr r3, [r7, #12] 800891a: 681b ldr r3, [r3, #0] 800891c: 681a ldr r2, [r3, #0] 800891e: 68fb ldr r3, [r7, #12] 8008920: 681b ldr r3, [r3, #0] 8008922: f422 4280 bic.w r2, r2, #16384 @ 0x4000 8008926: 601a str r2, [r3, #0] /* If last transfer, enable STOP interrupt */ if (hi2c->XferCount == 0U) 8008928: 68fb ldr r3, [r7, #12] 800892a: 8d5b ldrh r3, [r3, #42] @ 0x2a 800892c: b29b uxth r3, r3 800892e: 2b00 cmp r3, #0 8008930: d104 bne.n 800893c { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8008932: 2120 movs r1, #32 8008934: 68f8 ldr r0, [r7, #12] 8008936: f000 f8e5 bl 8008b04 { /* Enable TC interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } } 800893a: e02d b.n 8008998 hi2c->pBuffPtr += hi2c->XferSize; 800893c: 68fb ldr r3, [r7, #12] 800893e: 6a5b ldr r3, [r3, #36] @ 0x24 8008940: 68fa ldr r2, [r7, #12] 8008942: 8d12 ldrh r2, [r2, #40] @ 0x28 8008944: 441a add r2, r3 8008946: 68fb ldr r3, [r7, #12] 8008948: 625a str r2, [r3, #36] @ 0x24 if (hi2c->XferCount > MAX_NBYTE_SIZE) 800894a: 68fb ldr r3, [r7, #12] 800894c: 8d5b ldrh r3, [r3, #42] @ 0x2a 800894e: b29b uxth r3, r3 8008950: 2bff cmp r3, #255 @ 0xff 8008952: d903 bls.n 800895c hi2c->XferSize = MAX_NBYTE_SIZE; 8008954: 68fb ldr r3, [r7, #12] 8008956: 22ff movs r2, #255 @ 0xff 8008958: 851a strh r2, [r3, #40] @ 0x28 800895a: e004 b.n 8008966 hi2c->XferSize = hi2c->XferCount; 800895c: 68fb ldr r3, [r7, #12] 800895e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008960: b29a uxth r2, r3 8008962: 68fb ldr r3, [r7, #12] 8008964: 851a strh r2, [r3, #40] @ 0x28 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, 8008966: 68fb ldr r3, [r7, #12] 8008968: 6b98 ldr r0, [r3, #56] @ 0x38 800896a: 68fb ldr r3, [r7, #12] 800896c: 6a5b ldr r3, [r3, #36] @ 0x24 800896e: 4619 mov r1, r3 8008970: 68fb ldr r3, [r7, #12] 8008972: 681b ldr r3, [r3, #0] 8008974: 3328 adds r3, #40 @ 0x28 8008976: 461a mov r2, r3 hi2c->XferSize) != HAL_OK) 8008978: 68fb ldr r3, [r7, #12] 800897a: 8d1b ldrh r3, [r3, #40] @ 0x28 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, 800897c: f7fd ffa2 bl 80068c4 8008980: 4603 mov r3, r0 8008982: 2b00 cmp r3, #0 8008984: d004 beq.n 8008990 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); 8008986: 2110 movs r1, #16 8008988: 68f8 ldr r0, [r7, #12] 800898a: f7ff fe83 bl 8008694 } 800898e: e003 b.n 8008998 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); 8008990: 2140 movs r1, #64 @ 0x40 8008992: 68f8 ldr r0, [r7, #12] 8008994: f000 f8b6 bl 8008b04 } 8008998: bf00 nop 800899a: 3710 adds r7, #16 800899c: 46bd mov sp, r7 800899e: bd80 pop {r7, pc} 080089a0 : * @brief DMA I2C master receive process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { 80089a0: b580 push {r7, lr} 80089a2: b084 sub sp, #16 80089a4: af00 add r7, sp, #0 80089a6: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 80089a8: 687b ldr r3, [r7, #4] 80089aa: 6a9b ldr r3, [r3, #40] @ 0x28 80089ac: 60fb str r3, [r7, #12] /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 80089ae: 68fb ldr r3, [r7, #12] 80089b0: 681b ldr r3, [r3, #0] 80089b2: 681a ldr r2, [r3, #0] 80089b4: 68fb ldr r3, [r7, #12] 80089b6: 681b ldr r3, [r3, #0] 80089b8: f422 4200 bic.w r2, r2, #32768 @ 0x8000 80089bc: 601a str r2, [r3, #0] /* If last transfer, enable STOP interrupt */ if (hi2c->XferCount == 0U) 80089be: 68fb ldr r3, [r7, #12] 80089c0: 8d5b ldrh r3, [r3, #42] @ 0x2a 80089c2: b29b uxth r3, r3 80089c4: 2b00 cmp r3, #0 80089c6: d104 bne.n 80089d2 { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 80089c8: 2120 movs r1, #32 80089ca: 68f8 ldr r0, [r7, #12] 80089cc: f000 f89a bl 8008b04 { /* Enable TC interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } } 80089d0: e02d b.n 8008a2e hi2c->pBuffPtr += hi2c->XferSize; 80089d2: 68fb ldr r3, [r7, #12] 80089d4: 6a5b ldr r3, [r3, #36] @ 0x24 80089d6: 68fa ldr r2, [r7, #12] 80089d8: 8d12 ldrh r2, [r2, #40] @ 0x28 80089da: 441a add r2, r3 80089dc: 68fb ldr r3, [r7, #12] 80089de: 625a str r2, [r3, #36] @ 0x24 if (hi2c->XferCount > MAX_NBYTE_SIZE) 80089e0: 68fb ldr r3, [r7, #12] 80089e2: 8d5b ldrh r3, [r3, #42] @ 0x2a 80089e4: b29b uxth r3, r3 80089e6: 2bff cmp r3, #255 @ 0xff 80089e8: d903 bls.n 80089f2 hi2c->XferSize = MAX_NBYTE_SIZE; 80089ea: 68fb ldr r3, [r7, #12] 80089ec: 22ff movs r2, #255 @ 0xff 80089ee: 851a strh r2, [r3, #40] @ 0x28 80089f0: e004 b.n 80089fc hi2c->XferSize = hi2c->XferCount; 80089f2: 68fb ldr r3, [r7, #12] 80089f4: 8d5b ldrh r3, [r3, #42] @ 0x2a 80089f6: b29a uxth r2, r3 80089f8: 68fb ldr r3, [r7, #12] 80089fa: 851a strh r2, [r3, #40] @ 0x28 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, 80089fc: 68fb ldr r3, [r7, #12] 80089fe: 6bd8 ldr r0, [r3, #60] @ 0x3c 8008a00: 68fb ldr r3, [r7, #12] 8008a02: 681b ldr r3, [r3, #0] 8008a04: 3324 adds r3, #36 @ 0x24 8008a06: 4619 mov r1, r3 8008a08: 68fb ldr r3, [r7, #12] 8008a0a: 6a5b ldr r3, [r3, #36] @ 0x24 8008a0c: 461a mov r2, r3 hi2c->XferSize) != HAL_OK) 8008a0e: 68fb ldr r3, [r7, #12] 8008a10: 8d1b ldrh r3, [r3, #40] @ 0x28 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, 8008a12: f7fd ff57 bl 80068c4 8008a16: 4603 mov r3, r0 8008a18: 2b00 cmp r3, #0 8008a1a: d004 beq.n 8008a26 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); 8008a1c: 2110 movs r1, #16 8008a1e: 68f8 ldr r0, [r7, #12] 8008a20: f7ff fe38 bl 8008694 } 8008a24: e003 b.n 8008a2e I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); 8008a26: 2140 movs r1, #64 @ 0x40 8008a28: 68f8 ldr r0, [r7, #12] 8008a2a: f000 f86b bl 8008b04 } 8008a2e: bf00 nop 8008a30: 3710 adds r7, #16 8008a32: 46bd mov sp, r7 8008a34: bd80 pop {r7, pc} 08008a36 : * @brief DMA I2C communication error callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { 8008a36: b580 push {r7, lr} 8008a38: b084 sub sp, #16 8008a3a: af00 add r7, sp, #0 8008a3c: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8008a3e: 687b ldr r3, [r7, #4] 8008a40: 6a9b ldr r3, [r3, #40] @ 0x28 8008a42: 60fb str r3, [r7, #12] /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; 8008a44: 68fb ldr r3, [r7, #12] 8008a46: 681b ldr r3, [r3, #0] 8008a48: 685a ldr r2, [r3, #4] 8008a4a: 68fb ldr r3, [r7, #12] 8008a4c: 681b ldr r3, [r3, #0] 8008a4e: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8008a52: 605a str r2, [r3, #4] /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); 8008a54: 2110 movs r1, #16 8008a56: 68f8 ldr r0, [r7, #12] 8008a58: f7ff fe1c bl 8008694 } 8008a5c: bf00 nop 8008a5e: 3710 adds r7, #16 8008a60: 46bd mov sp, r7 8008a62: bd80 pop {r7, pc} 08008a64 : * (To be called at end of DMA Abort procedure). * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { 8008a64: b580 push {r7, lr} 8008a66: b084 sub sp, #16 8008a68: af00 add r7, sp, #0 8008a6a: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8008a6c: 687b ldr r3, [r7, #4] 8008a6e: 6a9b ldr r3, [r3, #40] @ 0x28 8008a70: 60fb str r3, [r7, #12] /* Reset AbortCpltCallback */ if (hi2c->hdmatx != NULL) 8008a72: 68fb ldr r3, [r7, #12] 8008a74: 6b9b ldr r3, [r3, #56] @ 0x38 8008a76: 2b00 cmp r3, #0 8008a78: d003 beq.n 8008a82 { hi2c->hdmatx->XferAbortCallback = NULL; 8008a7a: 68fb ldr r3, [r7, #12] 8008a7c: 6b9b ldr r3, [r3, #56] @ 0x38 8008a7e: 2200 movs r2, #0 8008a80: 639a str r2, [r3, #56] @ 0x38 } if (hi2c->hdmarx != NULL) 8008a82: 68fb ldr r3, [r7, #12] 8008a84: 6bdb ldr r3, [r3, #60] @ 0x3c 8008a86: 2b00 cmp r3, #0 8008a88: d003 beq.n 8008a92 { hi2c->hdmarx->XferAbortCallback = NULL; 8008a8a: 68fb ldr r3, [r7, #12] 8008a8c: 6bdb ldr r3, [r3, #60] @ 0x3c 8008a8e: 2200 movs r2, #0 8008a90: 639a str r2, [r3, #56] @ 0x38 } I2C_TreatErrorCallback(hi2c); 8008a92: 68f8 ldr r0, [r7, #12] 8008a94: f7ff feee bl 8008874 } 8008a98: bf00 nop 8008a9a: 3710 adds r7, #16 8008a9c: 46bd mov sp, r7 8008a9e: bd80 pop {r7, pc} 08008aa0 : * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { 8008aa0: b480 push {r7} 8008aa2: b087 sub sp, #28 8008aa4: af00 add r7, sp, #0 8008aa6: 60f8 str r0, [r7, #12] 8008aa8: 607b str r3, [r7, #4] 8008aaa: 460b mov r3, r1 8008aac: 817b strh r3, [r7, #10] 8008aae: 4613 mov r3, r2 8008ab0: 727b strb r3, [r7, #9] assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 8008ab2: 897b ldrh r3, [r7, #10] 8008ab4: f3c3 0209 ubfx r2, r3, #0, #10 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 8008ab8: 7a7b ldrb r3, [r7, #9] 8008aba: 041b lsls r3, r3, #16 8008abc: f403 037f and.w r3, r3, #16711680 @ 0xff0000 tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 8008ac0: 431a orrs r2, r3 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 8008ac2: 687b ldr r3, [r7, #4] 8008ac4: 431a orrs r2, r3 tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 8008ac6: 6a3b ldr r3, [r7, #32] 8008ac8: 4313 orrs r3, r2 8008aca: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8008ace: 617b str r3, [r7, #20] (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ 8008ad0: 68fb ldr r3, [r7, #12] 8008ad2: 681b ldr r3, [r3, #0] 8008ad4: 685a ldr r2, [r3, #4] 8008ad6: 6a3b ldr r3, [r7, #32] 8008ad8: 0d5b lsrs r3, r3, #21 8008ada: f403 6180 and.w r1, r3, #1024 @ 0x400 8008ade: 4b08 ldr r3, [pc, #32] @ (8008b00 ) 8008ae0: 430b orrs r3, r1 8008ae2: 43db mvns r3, r3 8008ae4: ea02 0103 and.w r1, r2, r3 8008ae8: 68fb ldr r3, [r7, #12] 8008aea: 681b ldr r3, [r3, #0] 8008aec: 697a ldr r2, [r7, #20] 8008aee: 430a orrs r2, r1 8008af0: 605a str r2, [r3, #4] ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ I2C_CR2_START | I2C_CR2_STOP)), tmp); } 8008af2: bf00 nop 8008af4: 371c adds r7, #28 8008af6: 46bd mov sp, r7 8008af8: f85d 7b04 ldr.w r7, [sp], #4 8008afc: 4770 bx lr 8008afe: bf00 nop 8008b00: 03ff63ff .word 0x03ff63ff 08008b04 : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 8008b04: b480 push {r7} 8008b06: b085 sub sp, #20 8008b08: af00 add r7, sp, #0 8008b0a: 6078 str r0, [r7, #4] 8008b0c: 460b mov r3, r1 8008b0e: 807b strh r3, [r7, #2] uint32_t tmpisr = 0U; 8008b10: 2300 movs r3, #0 8008b12: 60fb str r3, [r7, #12] #if defined(HAL_DMA_MODULE_ENABLED) if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ 8008b14: 687b ldr r3, [r7, #4] 8008b16: 6b5b ldr r3, [r3, #52] @ 0x34 8008b18: 4a39 ldr r2, [pc, #228] @ (8008c00 ) 8008b1a: 4293 cmp r3, r2 8008b1c: d032 beq.n 8008b84 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ 8008b1e: 687b ldr r3, [r7, #4] 8008b20: 6b5b ldr r3, [r3, #52] @ 0x34 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ 8008b22: 4a38 ldr r2, [pc, #224] @ (8008c04 ) 8008b24: 4293 cmp r3, r2 8008b26: d02d beq.n 8008b84 (hi2c->XferISR != I2C_Mem_ISR_DMA)) 8008b28: 687b ldr r3, [r7, #4] 8008b2a: 6b5b ldr r3, [r3, #52] @ 0x34 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ 8008b2c: 4a36 ldr r2, [pc, #216] @ (8008c08 ) 8008b2e: 4293 cmp r3, r2 8008b30: d028 beq.n 8008b84 #endif /* HAL_DMA_MODULE_ENABLED */ { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8008b32: f9b7 3002 ldrsh.w r3, [r7, #2] 8008b36: 2b00 cmp r3, #0 8008b38: da03 bge.n 8008b42 { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8008b3a: 68fb ldr r3, [r7, #12] 8008b3c: f043 03b8 orr.w r3, r3, #184 @ 0xb8 8008b40: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 8008b42: 887b ldrh r3, [r7, #2] 8008b44: f003 0301 and.w r3, r3, #1 8008b48: 2b00 cmp r3, #0 8008b4a: d003 beq.n 8008b54 { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; 8008b4c: 68fb ldr r3, [r7, #12] 8008b4e: f043 03f2 orr.w r3, r3, #242 @ 0xf2 8008b52: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8008b54: 887b ldrh r3, [r7, #2] 8008b56: f003 0302 and.w r3, r3, #2 8008b5a: 2b00 cmp r3, #0 8008b5c: d003 beq.n 8008b66 { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; 8008b5e: 68fb ldr r3, [r7, #12] 8008b60: f043 03f4 orr.w r3, r3, #244 @ 0xf4 8008b64: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 8008b66: 887b ldrh r3, [r7, #2] 8008b68: 2b10 cmp r3, #16 8008b6a: d103 bne.n 8008b74 { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8008b6c: 68fb ldr r3, [r7, #12] 8008b6e: f043 0390 orr.w r3, r3, #144 @ 0x90 8008b72: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 8008b74: 887b ldrh r3, [r7, #2] 8008b76: 2b20 cmp r3, #32 8008b78: d133 bne.n 8008be2 { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 8008b7a: 68fb ldr r3, [r7, #12] 8008b7c: f043 0320 orr.w r3, r3, #32 8008b80: 60fb str r3, [r7, #12] if (InterruptRequest == I2C_XFER_CPLT_IT) 8008b82: e02e b.n 8008be2 } #if defined(HAL_DMA_MODULE_ENABLED) else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8008b84: f9b7 3002 ldrsh.w r3, [r7, #2] 8008b88: 2b00 cmp r3, #0 8008b8a: da03 bge.n 8008b94 { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8008b8c: 68fb ldr r3, [r7, #12] 8008b8e: f043 03b8 orr.w r3, r3, #184 @ 0xb8 8008b92: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 8008b94: 887b ldrh r3, [r7, #2] 8008b96: f003 0301 and.w r3, r3, #1 8008b9a: 2b00 cmp r3, #0 8008b9c: d003 beq.n 8008ba6 { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; 8008b9e: 68fb ldr r3, [r7, #12] 8008ba0: f043 03f2 orr.w r3, r3, #242 @ 0xf2 8008ba4: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8008ba6: 887b ldrh r3, [r7, #2] 8008ba8: f003 0302 and.w r3, r3, #2 8008bac: 2b00 cmp r3, #0 8008bae: d003 beq.n 8008bb8 { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; 8008bb0: 68fb ldr r3, [r7, #12] 8008bb2: f043 03f4 orr.w r3, r3, #244 @ 0xf4 8008bb6: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 8008bb8: 887b ldrh r3, [r7, #2] 8008bba: 2b10 cmp r3, #16 8008bbc: d103 bne.n 8008bc6 { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8008bbe: 68fb ldr r3, [r7, #12] 8008bc0: f043 0390 orr.w r3, r3, #144 @ 0x90 8008bc4: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 8008bc6: 887b ldrh r3, [r7, #2] 8008bc8: 2b20 cmp r3, #32 8008bca: d103 bne.n 8008bd4 { /* Enable STOP interrupts */ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); 8008bcc: 68fb ldr r3, [r7, #12] 8008bce: f043 0360 orr.w r3, r3, #96 @ 0x60 8008bd2: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 8008bd4: 887b ldrh r3, [r7, #2] 8008bd6: 2b40 cmp r3, #64 @ 0x40 8008bd8: d103 bne.n 8008be2 { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 8008bda: 68fb ldr r3, [r7, #12] 8008bdc: f043 0340 orr.w r3, r3, #64 @ 0x40 8008be0: 60fb str r3, [r7, #12] #endif /* HAL_DMA_MODULE_ENABLED */ /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ __HAL_I2C_ENABLE_IT(hi2c, tmpisr); 8008be2: 687b ldr r3, [r7, #4] 8008be4: 681b ldr r3, [r3, #0] 8008be6: 6819 ldr r1, [r3, #0] 8008be8: 687b ldr r3, [r7, #4] 8008bea: 681b ldr r3, [r3, #0] 8008bec: 68fa ldr r2, [r7, #12] 8008bee: 430a orrs r2, r1 8008bf0: 601a str r2, [r3, #0] } 8008bf2: bf00 nop 8008bf4: 3714 adds r7, #20 8008bf6: 46bd mov sp, r7 8008bf8: f85d 7b04 ldr.w r7, [sp], #4 8008bfc: 4770 bx lr 8008bfe: bf00 nop 8008c00: 0800793b .word 0x0800793b 8008c04: 08007d81 .word 0x08007d81 8008c08: 08007b21 .word 0x08007b21 08008c0c : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 8008c0c: b480 push {r7} 8008c0e: b085 sub sp, #20 8008c10: af00 add r7, sp, #0 8008c12: 6078 str r0, [r7, #4] 8008c14: 460b mov r3, r1 8008c16: 807b strh r3, [r7, #2] uint32_t tmpisr = 0U; 8008c18: 2300 movs r3, #0 8008c1a: 60fb str r3, [r7, #12] if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 8008c1c: 887b ldrh r3, [r7, #2] 8008c1e: f003 0301 and.w r3, r3, #1 8008c22: 2b00 cmp r3, #0 8008c24: d00f beq.n 8008c46 { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; 8008c26: 68fb ldr r3, [r7, #12] 8008c28: f043 0342 orr.w r3, r3, #66 @ 0x42 8008c2c: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 8008c2e: 687b ldr r3, [r7, #4] 8008c30: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008c34: b2db uxtb r3, r3 8008c36: f003 0328 and.w r3, r3, #40 @ 0x28 8008c3a: 2b28 cmp r3, #40 @ 0x28 8008c3c: d003 beq.n 8008c46 { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8008c3e: 68fb ldr r3, [r7, #12] 8008c40: f043 03b0 orr.w r3, r3, #176 @ 0xb0 8008c44: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8008c46: 887b ldrh r3, [r7, #2] 8008c48: f003 0302 and.w r3, r3, #2 8008c4c: 2b00 cmp r3, #0 8008c4e: d00f beq.n 8008c70 { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; 8008c50: 68fb ldr r3, [r7, #12] 8008c52: f043 0344 orr.w r3, r3, #68 @ 0x44 8008c56: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 8008c58: 687b ldr r3, [r7, #4] 8008c5a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008c5e: b2db uxtb r3, r3 8008c60: f003 0328 and.w r3, r3, #40 @ 0x28 8008c64: 2b28 cmp r3, #40 @ 0x28 8008c66: d003 beq.n 8008c70 { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8008c68: 68fb ldr r3, [r7, #12] 8008c6a: f043 03b0 orr.w r3, r3, #176 @ 0xb0 8008c6e: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8008c70: f9b7 3002 ldrsh.w r3, [r7, #2] 8008c74: 2b00 cmp r3, #0 8008c76: da03 bge.n 8008c80 { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8008c78: 68fb ldr r3, [r7, #12] 8008c7a: f043 03b8 orr.w r3, r3, #184 @ 0xb8 8008c7e: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 8008c80: 887b ldrh r3, [r7, #2] 8008c82: 2b10 cmp r3, #16 8008c84: d103 bne.n 8008c8e { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8008c86: 68fb ldr r3, [r7, #12] 8008c88: f043 0390 orr.w r3, r3, #144 @ 0x90 8008c8c: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 8008c8e: 887b ldrh r3, [r7, #2] 8008c90: 2b20 cmp r3, #32 8008c92: d103 bne.n 8008c9c { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 8008c94: 68fb ldr r3, [r7, #12] 8008c96: f043 0320 orr.w r3, r3, #32 8008c9a: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 8008c9c: 887b ldrh r3, [r7, #2] 8008c9e: 2b40 cmp r3, #64 @ 0x40 8008ca0: d103 bne.n 8008caa { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 8008ca2: 68fb ldr r3, [r7, #12] 8008ca4: f043 0340 orr.w r3, r3, #64 @ 0x40 8008ca8: 60fb str r3, [r7, #12] } /* Disable interrupts only at the end */ /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); 8008caa: 687b ldr r3, [r7, #4] 8008cac: 681b ldr r3, [r3, #0] 8008cae: 6819 ldr r1, [r3, #0] 8008cb0: 68fb ldr r3, [r7, #12] 8008cb2: 43da mvns r2, r3 8008cb4: 687b ldr r3, [r7, #4] 8008cb6: 681b ldr r3, [r3, #0] 8008cb8: 400a ands r2, r1 8008cba: 601a str r2, [r3, #0] } 8008cbc: bf00 nop 8008cbe: 3714 adds r7, #20 8008cc0: 46bd mov sp, r7 8008cc2: f85d 7b04 ldr.w r7, [sp], #4 8008cc6: 4770 bx lr 08008cc8 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8008cc8: b480 push {r7} 8008cca: b083 sub sp, #12 8008ccc: af00 add r7, sp, #0 8008cce: 6078 str r0, [r7, #4] 8008cd0: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8008cd2: 687b ldr r3, [r7, #4] 8008cd4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008cd8: b2db uxtb r3, r3 8008cda: 2b20 cmp r3, #32 8008cdc: d138 bne.n 8008d50 { /* Process Locked */ __HAL_LOCK(hi2c); 8008cde: 687b ldr r3, [r7, #4] 8008ce0: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008ce4: 2b01 cmp r3, #1 8008ce6: d101 bne.n 8008cec 8008ce8: 2302 movs r3, #2 8008cea: e032 b.n 8008d52 8008cec: 687b ldr r3, [r7, #4] 8008cee: 2201 movs r2, #1 8008cf0: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 8008cf4: 687b ldr r3, [r7, #4] 8008cf6: 2224 movs r2, #36 @ 0x24 8008cf8: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8008cfc: 687b ldr r3, [r7, #4] 8008cfe: 681b ldr r3, [r3, #0] 8008d00: 681a ldr r2, [r3, #0] 8008d02: 687b ldr r3, [r7, #4] 8008d04: 681b ldr r3, [r3, #0] 8008d06: f022 0201 bic.w r2, r2, #1 8008d0a: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 8008d0c: 687b ldr r3, [r7, #4] 8008d0e: 681b ldr r3, [r3, #0] 8008d10: 681a ldr r2, [r3, #0] 8008d12: 687b ldr r3, [r7, #4] 8008d14: 681b ldr r3, [r3, #0] 8008d16: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8008d1a: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 8008d1c: 687b ldr r3, [r7, #4] 8008d1e: 681b ldr r3, [r3, #0] 8008d20: 6819 ldr r1, [r3, #0] 8008d22: 687b ldr r3, [r7, #4] 8008d24: 681b ldr r3, [r3, #0] 8008d26: 683a ldr r2, [r7, #0] 8008d28: 430a orrs r2, r1 8008d2a: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8008d2c: 687b ldr r3, [r7, #4] 8008d2e: 681b ldr r3, [r3, #0] 8008d30: 681a ldr r2, [r3, #0] 8008d32: 687b ldr r3, [r7, #4] 8008d34: 681b ldr r3, [r3, #0] 8008d36: f042 0201 orr.w r2, r2, #1 8008d3a: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8008d3c: 687b ldr r3, [r7, #4] 8008d3e: 2220 movs r2, #32 8008d40: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008d44: 687b ldr r3, [r7, #4] 8008d46: 2200 movs r2, #0 8008d48: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8008d4c: 2300 movs r3, #0 8008d4e: e000 b.n 8008d52 } else { return HAL_BUSY; 8008d50: 2302 movs r3, #2 } } 8008d52: 4618 mov r0, r3 8008d54: 370c adds r7, #12 8008d56: 46bd mov sp, r7 8008d58: f85d 7b04 ldr.w r7, [sp], #4 8008d5c: 4770 bx lr 08008d5e : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8008d5e: b480 push {r7} 8008d60: b085 sub sp, #20 8008d62: af00 add r7, sp, #0 8008d64: 6078 str r0, [r7, #4] 8008d66: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8008d68: 687b ldr r3, [r7, #4] 8008d6a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008d6e: b2db uxtb r3, r3 8008d70: 2b20 cmp r3, #32 8008d72: d139 bne.n 8008de8 { /* Process Locked */ __HAL_LOCK(hi2c); 8008d74: 687b ldr r3, [r7, #4] 8008d76: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008d7a: 2b01 cmp r3, #1 8008d7c: d101 bne.n 8008d82 8008d7e: 2302 movs r3, #2 8008d80: e033 b.n 8008dea 8008d82: 687b ldr r3, [r7, #4] 8008d84: 2201 movs r2, #1 8008d86: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 8008d8a: 687b ldr r3, [r7, #4] 8008d8c: 2224 movs r2, #36 @ 0x24 8008d8e: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8008d92: 687b ldr r3, [r7, #4] 8008d94: 681b ldr r3, [r3, #0] 8008d96: 681a ldr r2, [r3, #0] 8008d98: 687b ldr r3, [r7, #4] 8008d9a: 681b ldr r3, [r3, #0] 8008d9c: f022 0201 bic.w r2, r2, #1 8008da0: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 8008da2: 687b ldr r3, [r7, #4] 8008da4: 681b ldr r3, [r3, #0] 8008da6: 681b ldr r3, [r3, #0] 8008da8: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 8008daa: 68fb ldr r3, [r7, #12] 8008dac: f423 6370 bic.w r3, r3, #3840 @ 0xf00 8008db0: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 8008db2: 683b ldr r3, [r7, #0] 8008db4: 021b lsls r3, r3, #8 8008db6: 68fa ldr r2, [r7, #12] 8008db8: 4313 orrs r3, r2 8008dba: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 8008dbc: 687b ldr r3, [r7, #4] 8008dbe: 681b ldr r3, [r3, #0] 8008dc0: 68fa ldr r2, [r7, #12] 8008dc2: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8008dc4: 687b ldr r3, [r7, #4] 8008dc6: 681b ldr r3, [r3, #0] 8008dc8: 681a ldr r2, [r3, #0] 8008dca: 687b ldr r3, [r7, #4] 8008dcc: 681b ldr r3, [r3, #0] 8008dce: f042 0201 orr.w r2, r2, #1 8008dd2: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8008dd4: 687b ldr r3, [r7, #4] 8008dd6: 2220 movs r2, #32 8008dd8: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008ddc: 687b ldr r3, [r7, #4] 8008dde: 2200 movs r2, #0 8008de0: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8008de4: 2300 movs r3, #0 8008de6: e000 b.n 8008dea } else { return HAL_BUSY; 8008de8: 2302 movs r3, #2 } } 8008dea: 4618 mov r0, r3 8008dec: 3714 adds r7, #20 8008dee: 46bd mov sp, r7 8008df0: f85d 7b04 ldr.w r7, [sp], #4 8008df4: 4770 bx lr ... 08008df8 : * @brief Initialize the IPCC peripheral. * @param hipcc IPCC handle * @retval HAL status */ HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc) { 8008df8: b580 push {r7, lr} 8008dfa: b084 sub sp, #16 8008dfc: af00 add r7, sp, #0 8008dfe: 6078 str r0, [r7, #4] HAL_StatusTypeDef err = HAL_OK; 8008e00: 2300 movs r3, #0 8008e02: 73fb strb r3, [r7, #15] /* Check the IPCC handle allocation */ if (hipcc != NULL) 8008e04: 687b ldr r3, [r7, #4] 8008e06: 2b00 cmp r3, #0 8008e08: d01e beq.n 8008e48 { /* Check the parameters */ assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance)); IPCC_CommonTypeDef *currentInstance = IPCC_C1; 8008e0a: 4b13 ldr r3, [pc, #76] @ (8008e58 ) 8008e0c: 60bb str r3, [r7, #8] if (hipcc->State == HAL_IPCC_STATE_RESET) 8008e0e: 687b ldr r3, [r7, #4] 8008e10: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8008e14: b2db uxtb r3, r3 8008e16: 2b00 cmp r3, #0 8008e18: d102 bne.n 8008e20 { /* Init the low level hardware : CLOCK, NVIC */ HAL_IPCC_MspInit(hipcc); 8008e1a: 6878 ldr r0, [r7, #4] 8008e1c: f7fc ff42 bl 8005ca4 } /* Reset all registers of the current cpu to default state */ IPCC_Reset_Register(currentInstance); 8008e20: 68b8 ldr r0, [r7, #8] 8008e22: f000 f85b bl 8008edc /* Activate the interrupts */ currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE); 8008e26: 68bb ldr r3, [r7, #8] 8008e28: 681b ldr r3, [r3, #0] 8008e2a: f043 1201 orr.w r2, r3, #65537 @ 0x10001 8008e2e: 68bb ldr r3, [r7, #8] 8008e30: 601a str r2, [r3, #0] /* Clear callback pointers */ IPCC_SetDefaultCallbacks(hipcc); 8008e32: 6878 ldr r0, [r7, #4] 8008e34: f000 f82c bl 8008e90 /* Reset all callback notification request */ hipcc->callbackRequest = 0; 8008e38: 687b ldr r3, [r7, #4] 8008e3a: 2200 movs r2, #0 8008e3c: 635a str r2, [r3, #52] @ 0x34 hipcc->State = HAL_IPCC_STATE_READY; 8008e3e: 687b ldr r3, [r7, #4] 8008e40: 2201 movs r2, #1 8008e42: f883 2038 strb.w r2, [r3, #56] @ 0x38 8008e46: e001 b.n 8008e4c } else { err = HAL_ERROR; 8008e48: 2301 movs r3, #1 8008e4a: 73fb strb r3, [r7, #15] } return err; 8008e4c: 7bfb ldrb r3, [r7, #15] } 8008e4e: 4618 mov r0, r3 8008e50: 3710 adds r7, #16 8008e52: 46bd mov sp, r7 8008e54: bd80 pop {r7, pc} 8008e56: bf00 nop 8008e58: 58000c00 .word 0x58000c00 08008e5c : * @arg IPCC_CHANNEL_5: IPCC Channel 5 * @arg IPCC_CHANNEL_6: IPCC Channel 6 * @param ChannelDir Channel direction */ __weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) { 8008e5c: b480 push {r7} 8008e5e: b085 sub sp, #20 8008e60: af00 add r7, sp, #0 8008e62: 60f8 str r0, [r7, #12] 8008e64: 60b9 str r1, [r7, #8] 8008e66: 4613 mov r3, r2 8008e68: 71fb strb r3, [r7, #7] UNUSED(ChannelDir); /* NOTE : This function should not be modified, when the callback is needed, the HAL_IPCC_RxCallback can be implemented in the user file */ } 8008e6a: bf00 nop 8008e6c: 3714 adds r7, #20 8008e6e: 46bd mov sp, r7 8008e70: f85d 7b04 ldr.w r7, [sp], #4 8008e74: 4770 bx lr 08008e76 : * @arg IPCC_CHANNEL_5: IPCC Channel 5 * @arg IPCC_CHANNEL_6: IPCC Channel 6 * @param ChannelDir Channel direction */ __weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) { 8008e76: b480 push {r7} 8008e78: b085 sub sp, #20 8008e7a: af00 add r7, sp, #0 8008e7c: 60f8 str r0, [r7, #12] 8008e7e: 60b9 str r1, [r7, #8] 8008e80: 4613 mov r3, r2 8008e82: 71fb strb r3, [r7, #7] UNUSED(ChannelDir); /* NOTE : This function should not be modified, when the callback is needed, the HAL_IPCC_TxCallback can be implemented in the user file */ } 8008e84: bf00 nop 8008e86: 3714 adds r7, #20 8008e88: 46bd mov sp, r7 8008e8a: f85d 7b04 ldr.w r7, [sp], #4 8008e8e: 4770 bx lr 08008e90 : /** * @brief Reset all callbacks of the handle to NULL. * @param hipcc IPCC handle */ void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc) { 8008e90: b480 push {r7} 8008e92: b085 sub sp, #20 8008e94: af00 add r7, sp, #0 8008e96: 6078 str r0, [r7, #4] uint32_t i; /* Set all callbacks to default */ for (i = 0; i < IPCC_CHANNEL_NUMBER; i++) 8008e98: 2300 movs r3, #0 8008e9a: 60fb str r3, [r7, #12] 8008e9c: e00f b.n 8008ebe { hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback; 8008e9e: 687a ldr r2, [r7, #4] 8008ea0: 68fb ldr r3, [r7, #12] 8008ea2: 009b lsls r3, r3, #2 8008ea4: 4413 add r3, r2 8008ea6: 4a0b ldr r2, [pc, #44] @ (8008ed4 ) 8008ea8: 605a str r2, [r3, #4] hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback; 8008eaa: 687a ldr r2, [r7, #4] 8008eac: 68fb ldr r3, [r7, #12] 8008eae: 3306 adds r3, #6 8008eb0: 009b lsls r3, r3, #2 8008eb2: 4413 add r3, r2 8008eb4: 4a08 ldr r2, [pc, #32] @ (8008ed8 ) 8008eb6: 605a str r2, [r3, #4] for (i = 0; i < IPCC_CHANNEL_NUMBER; i++) 8008eb8: 68fb ldr r3, [r7, #12] 8008eba: 3301 adds r3, #1 8008ebc: 60fb str r3, [r7, #12] 8008ebe: 68fb ldr r3, [r7, #12] 8008ec0: 2b05 cmp r3, #5 8008ec2: d9ec bls.n 8008e9e } } 8008ec4: bf00 nop 8008ec6: bf00 nop 8008ec8: 3714 adds r7, #20 8008eca: 46bd mov sp, r7 8008ecc: f85d 7b04 ldr.w r7, [sp], #4 8008ed0: 4770 bx lr 8008ed2: bf00 nop 8008ed4: 08008e5d .word 0x08008e5d 8008ed8: 08008e77 .word 0x08008e77 08008edc : /** * @brief Reset IPCC register to default value for the concerned instance. * @param Instance pointer to register */ void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance) { 8008edc: b480 push {r7} 8008ede: b083 sub sp, #12 8008ee0: af00 add r7, sp, #0 8008ee2: 6078 str r0, [r7, #4] /* Disable RX and TX interrupts */ Instance->CR = 0x00000000U; 8008ee4: 687b ldr r3, [r7, #4] 8008ee6: 2200 movs r2, #0 8008ee8: 601a str r2, [r3, #0] /* Mask RX and TX interrupts */ Instance->MR = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF); 8008eea: 687b ldr r3, [r7, #4] 8008eec: f04f 123f mov.w r2, #4128831 @ 0x3f003f 8008ef0: 605a str r2, [r3, #4] /* Clear RX status */ Instance->SCR = IPCC_ALL_RX_BUF; 8008ef2: 687b ldr r3, [r7, #4] 8008ef4: 223f movs r2, #63 @ 0x3f 8008ef6: 609a str r2, [r3, #8] } 8008ef8: bf00 nop 8008efa: 370c adds r7, #12 8008efc: 46bd mov sp, r7 8008efe: f85d 7b04 ldr.w r7, [sp], #4 8008f02: 4770 bx lr 08008f04 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8008f04: b580 push {r7, lr} 8008f06: b084 sub sp, #16 8008f08: af00 add r7, sp, #0 8008f0a: 6078 str r0, [r7, #4] uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8008f0c: 687b ldr r3, [r7, #4] 8008f0e: 2b00 cmp r3, #0 8008f10: d101 bne.n 8008f16 { return HAL_ERROR; 8008f12: 2301 movs r3, #1 8008f14: e0c0 b.n 8009098 } /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); if (hpcd->State == HAL_PCD_STATE_RESET) 8008f16: 687b ldr r3, [r7, #4] 8008f18: f893 3291 ldrb.w r3, [r3, #657] @ 0x291 8008f1c: b2db uxtb r3, r3 8008f1e: 2b00 cmp r3, #0 8008f20: d106 bne.n 8008f30 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8008f22: 687b ldr r3, [r7, #4] 8008f24: 2200 movs r2, #0 8008f26: f883 2290 strb.w r2, [r3, #656] @ 0x290 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8008f2a: 6878 ldr r0, [r7, #4] 8008f2c: f00f f9f4 bl 8018318 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8008f30: 687b ldr r3, [r7, #4] 8008f32: 2203 movs r2, #3 8008f34: f883 2291 strb.w r2, [r3, #657] @ 0x291 /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8008f38: 687b ldr r3, [r7, #4] 8008f3a: 681b ldr r3, [r3, #0] 8008f3c: 4618 mov r0, r3 8008f3e: f005 fc5c bl 800e7fa /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8008f42: 2300 movs r3, #0 8008f44: 73fb strb r3, [r7, #15] 8008f46: e03e b.n 8008fc6 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8008f48: 7bfa ldrb r2, [r7, #15] 8008f4a: 6879 ldr r1, [r7, #4] 8008f4c: 4613 mov r3, r2 8008f4e: 009b lsls r3, r3, #2 8008f50: 4413 add r3, r2 8008f52: 00db lsls r3, r3, #3 8008f54: 440b add r3, r1 8008f56: 3311 adds r3, #17 8008f58: 2201 movs r2, #1 8008f5a: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8008f5c: 7bfa ldrb r2, [r7, #15] 8008f5e: 6879 ldr r1, [r7, #4] 8008f60: 4613 mov r3, r2 8008f62: 009b lsls r3, r3, #2 8008f64: 4413 add r3, r2 8008f66: 00db lsls r3, r3, #3 8008f68: 440b add r3, r1 8008f6a: 3310 adds r3, #16 8008f6c: 7bfa ldrb r2, [r7, #15] 8008f6e: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8008f70: 7bfa ldrb r2, [r7, #15] 8008f72: 6879 ldr r1, [r7, #4] 8008f74: 4613 mov r3, r2 8008f76: 009b lsls r3, r3, #2 8008f78: 4413 add r3, r2 8008f7a: 00db lsls r3, r3, #3 8008f7c: 440b add r3, r1 8008f7e: 3313 adds r3, #19 8008f80: 2200 movs r2, #0 8008f82: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8008f84: 7bfa ldrb r2, [r7, #15] 8008f86: 6879 ldr r1, [r7, #4] 8008f88: 4613 mov r3, r2 8008f8a: 009b lsls r3, r3, #2 8008f8c: 4413 add r3, r2 8008f8e: 00db lsls r3, r3, #3 8008f90: 440b add r3, r1 8008f92: 3320 adds r3, #32 8008f94: 2200 movs r2, #0 8008f96: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8008f98: 7bfa ldrb r2, [r7, #15] 8008f9a: 6879 ldr r1, [r7, #4] 8008f9c: 4613 mov r3, r2 8008f9e: 009b lsls r3, r3, #2 8008fa0: 4413 add r3, r2 8008fa2: 00db lsls r3, r3, #3 8008fa4: 440b add r3, r1 8008fa6: 3324 adds r3, #36 @ 0x24 8008fa8: 2200 movs r2, #0 8008faa: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8008fac: 7bfb ldrb r3, [r7, #15] 8008fae: 6879 ldr r1, [r7, #4] 8008fb0: 1c5a adds r2, r3, #1 8008fb2: 4613 mov r3, r2 8008fb4: 009b lsls r3, r3, #2 8008fb6: 4413 add r3, r2 8008fb8: 00db lsls r3, r3, #3 8008fba: 440b add r3, r1 8008fbc: 2200 movs r2, #0 8008fbe: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8008fc0: 7bfb ldrb r3, [r7, #15] 8008fc2: 3301 adds r3, #1 8008fc4: 73fb strb r3, [r7, #15] 8008fc6: 687b ldr r3, [r7, #4] 8008fc8: 791b ldrb r3, [r3, #4] 8008fca: 7bfa ldrb r2, [r7, #15] 8008fcc: 429a cmp r2, r3 8008fce: d3bb bcc.n 8008f48 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8008fd0: 2300 movs r3, #0 8008fd2: 73fb strb r3, [r7, #15] 8008fd4: e044 b.n 8009060 { hpcd->OUT_ep[i].is_in = 0U; 8008fd6: 7bfa ldrb r2, [r7, #15] 8008fd8: 6879 ldr r1, [r7, #4] 8008fda: 4613 mov r3, r2 8008fdc: 009b lsls r3, r3, #2 8008fde: 4413 add r3, r2 8008fe0: 00db lsls r3, r3, #3 8008fe2: 440b add r3, r1 8008fe4: f203 1351 addw r3, r3, #337 @ 0x151 8008fe8: 2200 movs r2, #0 8008fea: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8008fec: 7bfa ldrb r2, [r7, #15] 8008fee: 6879 ldr r1, [r7, #4] 8008ff0: 4613 mov r3, r2 8008ff2: 009b lsls r3, r3, #2 8008ff4: 4413 add r3, r2 8008ff6: 00db lsls r3, r3, #3 8008ff8: 440b add r3, r1 8008ffa: f503 73a8 add.w r3, r3, #336 @ 0x150 8008ffe: 7bfa ldrb r2, [r7, #15] 8009000: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8009002: 7bfa ldrb r2, [r7, #15] 8009004: 6879 ldr r1, [r7, #4] 8009006: 4613 mov r3, r2 8009008: 009b lsls r3, r3, #2 800900a: 4413 add r3, r2 800900c: 00db lsls r3, r3, #3 800900e: 440b add r3, r1 8009010: f203 1353 addw r3, r3, #339 @ 0x153 8009014: 2200 movs r2, #0 8009016: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8009018: 7bfa ldrb r2, [r7, #15] 800901a: 6879 ldr r1, [r7, #4] 800901c: 4613 mov r3, r2 800901e: 009b lsls r3, r3, #2 8009020: 4413 add r3, r2 8009022: 00db lsls r3, r3, #3 8009024: 440b add r3, r1 8009026: f503 73b0 add.w r3, r3, #352 @ 0x160 800902a: 2200 movs r2, #0 800902c: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 800902e: 7bfa ldrb r2, [r7, #15] 8009030: 6879 ldr r1, [r7, #4] 8009032: 4613 mov r3, r2 8009034: 009b lsls r3, r3, #2 8009036: 4413 add r3, r2 8009038: 00db lsls r3, r3, #3 800903a: 440b add r3, r1 800903c: f503 73b2 add.w r3, r3, #356 @ 0x164 8009040: 2200 movs r2, #0 8009042: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8009044: 7bfa ldrb r2, [r7, #15] 8009046: 6879 ldr r1, [r7, #4] 8009048: 4613 mov r3, r2 800904a: 009b lsls r3, r3, #2 800904c: 4413 add r3, r2 800904e: 00db lsls r3, r3, #3 8009050: 440b add r3, r1 8009052: f503 73b4 add.w r3, r3, #360 @ 0x168 8009056: 2200 movs r2, #0 8009058: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800905a: 7bfb ldrb r3, [r7, #15] 800905c: 3301 adds r3, #1 800905e: 73fb strb r3, [r7, #15] 8009060: 687b ldr r3, [r7, #4] 8009062: 791b ldrb r3, [r3, #4] 8009064: 7bfa ldrb r2, [r7, #15] 8009066: 429a cmp r2, r3 8009068: d3b5 bcc.n 8008fd6 } /* Init Device */ (void)USB_DevInit(hpcd->Instance, hpcd->Init); 800906a: 687b ldr r3, [r7, #4] 800906c: 6818 ldr r0, [r3, #0] 800906e: 687b ldr r3, [r7, #4] 8009070: 3304 adds r3, #4 8009072: e893 0006 ldmia.w r3, {r1, r2} 8009076: f005 fbdb bl 800e830 hpcd->USB_Address = 0U; 800907a: 687b ldr r3, [r7, #4] 800907c: 2200 movs r2, #0 800907e: 731a strb r2, [r3, #12] hpcd->State = HAL_PCD_STATE_READY; 8009080: 687b ldr r3, [r7, #4] 8009082: 2201 movs r2, #1 8009084: f883 2291 strb.w r2, [r3, #657] @ 0x291 /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8009088: 687b ldr r3, [r7, #4] 800908a: 7a9b ldrb r3, [r3, #10] 800908c: 2b01 cmp r3, #1 800908e: d102 bne.n 8009096 { (void)HAL_PCDEx_ActivateLPM(hpcd); 8009090: 6878 ldr r0, [r7, #4] 8009092: f001 fc4f bl 800a934 } return HAL_OK; 8009096: 2300 movs r3, #0 } 8009098: 4618 mov r0, r3 800909a: 3710 adds r7, #16 800909c: 46bd mov sp, r7 800909e: bd80 pop {r7, pc} 080090a0 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 80090a0: b580 push {r7, lr} 80090a2: b082 sub sp, #8 80090a4: af00 add r7, sp, #0 80090a6: 6078 str r0, [r7, #4] __HAL_LOCK(hpcd); 80090a8: 687b ldr r3, [r7, #4] 80090aa: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 80090ae: 2b01 cmp r3, #1 80090b0: d101 bne.n 80090b6 80090b2: 2302 movs r3, #2 80090b4: e012 b.n 80090dc 80090b6: 687b ldr r3, [r7, #4] 80090b8: 2201 movs r2, #1 80090ba: f883 2290 strb.w r2, [r3, #656] @ 0x290 __HAL_PCD_ENABLE(hpcd); 80090be: 687b ldr r3, [r7, #4] 80090c0: 681b ldr r3, [r3, #0] 80090c2: 4618 mov r0, r3 80090c4: f005 fb82 bl 800e7cc (void)USB_DevConnect(hpcd->Instance); 80090c8: 687b ldr r3, [r7, #4] 80090ca: 681b ldr r3, [r3, #0] 80090cc: 4618 mov r0, r3 80090ce: f007 f95f bl 8010390 __HAL_UNLOCK(hpcd); 80090d2: 687b ldr r3, [r7, #4] 80090d4: 2200 movs r2, #0 80090d6: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 80090da: 2300 movs r3, #0 } 80090dc: 4618 mov r0, r3 80090de: 3708 adds r7, #8 80090e0: 46bd mov sp, r7 80090e2: bd80 pop {r7, pc} 080090e4 : * @brief This function handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 80090e4: b580 push {r7, lr} 80090e6: b084 sub sp, #16 80090e8: af00 add r7, sp, #0 80090ea: 6078 str r0, [r7, #4] uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); 80090ec: 687b ldr r3, [r7, #4] 80090ee: 681b ldr r3, [r3, #0] 80090f0: 4618 mov r0, r3 80090f2: f007 f964 bl 80103be 80090f6: 60f8 str r0, [r7, #12] if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) 80090f8: 68fb ldr r3, [r7, #12] 80090fa: f403 4300 and.w r3, r3, #32768 @ 0x8000 80090fe: 2b00 cmp r3, #0 8009100: d003 beq.n 800910a { /* servicing of the endpoint correct transfer interrupt */ /* clear of the CTR flag into the sub */ (void)PCD_EP_ISR_Handler(hpcd); 8009102: 6878 ldr r0, [r7, #4] 8009104: f000 fb06 bl 8009714 return; 8009108: e110 b.n 800932c } if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) 800910a: 68fb ldr r3, [r7, #12] 800910c: f403 6380 and.w r3, r3, #1024 @ 0x400 8009110: 2b00 cmp r3, #0 8009112: d013 beq.n 800913c { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); 8009114: 687b ldr r3, [r7, #4] 8009116: 681b ldr r3, [r3, #0] 8009118: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 800911c: b29a uxth r2, r3 800911e: 687b ldr r3, [r7, #4] 8009120: 681b ldr r3, [r3, #0] 8009122: f422 6280 bic.w r2, r2, #1024 @ 0x400 8009126: b292 uxth r2, r2 8009128: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 800912c: 6878 ldr r0, [r7, #4] 800912e: f00f f9a6 bl 801847e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ (void)HAL_PCD_SetAddress(hpcd, 0U); 8009132: 2100 movs r1, #0 8009134: 6878 ldr r0, [r7, #4] 8009136: f000 f8fc bl 8009332 return; 800913a: e0f7 b.n 800932c } if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) 800913c: 68fb ldr r3, [r7, #12] 800913e: f403 4380 and.w r3, r3, #16384 @ 0x4000 8009142: 2b00 cmp r3, #0 8009144: d00c beq.n 8009160 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); 8009146: 687b ldr r3, [r7, #4] 8009148: 681b ldr r3, [r3, #0] 800914a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 800914e: b29a uxth r2, r3 8009150: 687b ldr r3, [r7, #4] 8009152: 681b ldr r3, [r3, #0] 8009154: f422 4280 bic.w r2, r2, #16384 @ 0x4000 8009158: b292 uxth r2, r2 800915a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 800915e: e0e5 b.n 800932c } if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) 8009160: 68fb ldr r3, [r7, #12] 8009162: f403 5300 and.w r3, r3, #8192 @ 0x2000 8009166: 2b00 cmp r3, #0 8009168: d00c beq.n 8009184 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); 800916a: 687b ldr r3, [r7, #4] 800916c: 681b ldr r3, [r3, #0] 800916e: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8009172: b29a uxth r2, r3 8009174: 687b ldr r3, [r7, #4] 8009176: 681b ldr r3, [r3, #0] 8009178: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800917c: b292 uxth r2, r2 800917e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 8009182: e0d3 b.n 800932c } if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) 8009184: 68fb ldr r3, [r7, #12] 8009186: f403 5380 and.w r3, r3, #4096 @ 0x1000 800918a: 2b00 cmp r3, #0 800918c: d034 beq.n 80091f8 { hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE); 800918e: 687b ldr r3, [r7, #4] 8009190: 681b ldr r3, [r3, #0] 8009192: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8009196: b29a uxth r2, r3 8009198: 687b ldr r3, [r7, #4] 800919a: 681b ldr r3, [r3, #0] 800919c: f022 0204 bic.w r2, r2, #4 80091a0: b292 uxth r2, r2 80091a2: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); 80091a6: 687b ldr r3, [r7, #4] 80091a8: 681b ldr r3, [r3, #0] 80091aa: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 80091ae: b29a uxth r2, r3 80091b0: 687b ldr r3, [r7, #4] 80091b2: 681b ldr r3, [r3, #0] 80091b4: f022 0208 bic.w r2, r2, #8 80091b8: b292 uxth r2, r2 80091ba: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 if (hpcd->LPM_State == LPM_L1) 80091be: 687b ldr r3, [r7, #4] 80091c0: f893 32c8 ldrb.w r3, [r3, #712] @ 0x2c8 80091c4: 2b01 cmp r3, #1 80091c6: d107 bne.n 80091d8 { hpcd->LPM_State = LPM_L0; 80091c8: 687b ldr r3, [r7, #4] 80091ca: 2200 movs r2, #0 80091cc: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 80091d0: 2100 movs r1, #0 80091d2: 6878 ldr r0, [r7, #4] 80091d4: f00f fb48 bl 8018868 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 80091d8: 6878 ldr r0, [r7, #4] 80091da: f00f f989 bl 80184f0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); 80091de: 687b ldr r3, [r7, #4] 80091e0: 681b ldr r3, [r3, #0] 80091e2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80091e6: b29a uxth r2, r3 80091e8: 687b ldr r3, [r7, #4] 80091ea: 681b ldr r3, [r3, #0] 80091ec: f422 5280 bic.w r2, r2, #4096 @ 0x1000 80091f0: b292 uxth r2, r2 80091f2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 80091f6: e099 b.n 800932c } if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) 80091f8: 68fb ldr r3, [r7, #12] 80091fa: f403 6300 and.w r3, r3, #2048 @ 0x800 80091fe: 2b00 cmp r3, #0 8009200: d027 beq.n 8009252 { /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; 8009202: 687b ldr r3, [r7, #4] 8009204: 681b ldr r3, [r3, #0] 8009206: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 800920a: b29a uxth r2, r3 800920c: 687b ldr r3, [r7, #4] 800920e: 681b ldr r3, [r3, #0] 8009210: f042 0208 orr.w r2, r2, #8 8009214: b292 uxth r2, r2 8009216: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); 800921a: 687b ldr r3, [r7, #4] 800921c: 681b ldr r3, [r3, #0] 800921e: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8009222: b29a uxth r2, r3 8009224: 687b ldr r3, [r7, #4] 8009226: 681b ldr r3, [r3, #0] 8009228: f422 6200 bic.w r2, r2, #2048 @ 0x800 800922c: b292 uxth r2, r2 800922e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; 8009232: 687b ldr r3, [r7, #4] 8009234: 681b ldr r3, [r3, #0] 8009236: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 800923a: b29a uxth r2, r3 800923c: 687b ldr r3, [r7, #4] 800923e: 681b ldr r3, [r3, #0] 8009240: f042 0204 orr.w r2, r2, #4 8009244: b292 uxth r2, r2 8009246: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 800924a: 6878 ldr r0, [r7, #4] 800924c: f00f f936 bl 80184bc #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ return; 8009250: e06c b.n 800932c } /* Handle LPM Interrupt */ if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) 8009252: 68fb ldr r3, [r7, #12] 8009254: f003 0380 and.w r3, r3, #128 @ 0x80 8009258: 2b00 cmp r3, #0 800925a: d040 beq.n 80092de { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); 800925c: 687b ldr r3, [r7, #4] 800925e: 681b ldr r3, [r3, #0] 8009260: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8009264: b29a uxth r2, r3 8009266: 687b ldr r3, [r7, #4] 8009268: 681b ldr r3, [r3, #0] 800926a: f022 0280 bic.w r2, r2, #128 @ 0x80 800926e: b292 uxth r2, r2 8009270: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 if (hpcd->LPM_State == LPM_L0) 8009274: 687b ldr r3, [r7, #4] 8009276: f893 32c8 ldrb.w r3, [r3, #712] @ 0x2c8 800927a: 2b00 cmp r3, #0 800927c: d12b bne.n 80092d6 { /* Force suspend and low-power mode before going to L1 state*/ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; 800927e: 687b ldr r3, [r7, #4] 8009280: 681b ldr r3, [r3, #0] 8009282: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8009286: b29a uxth r2, r3 8009288: 687b ldr r3, [r7, #4] 800928a: 681b ldr r3, [r3, #0] 800928c: f042 0204 orr.w r2, r2, #4 8009290: b292 uxth r2, r2 8009292: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; 8009296: 687b ldr r3, [r7, #4] 8009298: 681b ldr r3, [r3, #0] 800929a: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 800929e: b29a uxth r2, r3 80092a0: 687b ldr r3, [r7, #4] 80092a2: 681b ldr r3, [r3, #0] 80092a4: f042 0208 orr.w r2, r2, #8 80092a8: b292 uxth r2, r2 80092aa: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 hpcd->LPM_State = LPM_L1; 80092ae: 687b ldr r3, [r7, #4] 80092b0: 2201 movs r2, #1 80092b2: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8 hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; 80092b6: 687b ldr r3, [r7, #4] 80092b8: 681b ldr r3, [r3, #0] 80092ba: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 80092be: b29b uxth r3, r3 80092c0: 089b lsrs r3, r3, #2 80092c2: f003 023c and.w r2, r3, #60 @ 0x3c 80092c6: 687b ldr r3, [r7, #4] 80092c8: f8c3 22cc str.w r2, [r3, #716] @ 0x2cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 80092cc: 2101 movs r1, #1 80092ce: 6878 ldr r0, [r7, #4] 80092d0: f00f faca bl 8018868 #else HAL_PCD_SuspendCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } return; 80092d4: e02a b.n 800932c HAL_PCD_SuspendCallback(hpcd); 80092d6: 6878 ldr r0, [r7, #4] 80092d8: f00f f8f0 bl 80184bc return; 80092dc: e026 b.n 800932c } if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) 80092de: 68fb ldr r3, [r7, #12] 80092e0: f403 7300 and.w r3, r3, #512 @ 0x200 80092e4: 2b00 cmp r3, #0 80092e6: d00f beq.n 8009308 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); 80092e8: 687b ldr r3, [r7, #4] 80092ea: 681b ldr r3, [r3, #0] 80092ec: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80092f0: b29a uxth r2, r3 80092f2: 687b ldr r3, [r7, #4] 80092f4: 681b ldr r3, [r3, #0] 80092f6: f422 7200 bic.w r2, r2, #512 @ 0x200 80092fa: b292 uxth r2, r2 80092fc: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 8009300: 6878 ldr r0, [r7, #4] 8009302: f00f f8ae bl 8018462 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ return; 8009306: e011 b.n 800932c } if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) 8009308: 68fb ldr r3, [r7, #12] 800930a: f403 7380 and.w r3, r3, #256 @ 0x100 800930e: 2b00 cmp r3, #0 8009310: d00c beq.n 800932c { /* clear ESOF flag in ISTR */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); 8009312: 687b ldr r3, [r7, #4] 8009314: 681b ldr r3, [r3, #0] 8009316: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 800931a: b29a uxth r2, r3 800931c: 687b ldr r3, [r7, #4] 800931e: 681b ldr r3, [r3, #0] 8009320: f422 7280 bic.w r2, r2, #256 @ 0x100 8009324: b292 uxth r2, r2 8009326: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 800932a: bf00 nop } } 800932c: 3710 adds r7, #16 800932e: 46bd mov sp, r7 8009330: bd80 pop {r7, pc} 08009332 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 8009332: b580 push {r7, lr} 8009334: b082 sub sp, #8 8009336: af00 add r7, sp, #0 8009338: 6078 str r0, [r7, #4] 800933a: 460b mov r3, r1 800933c: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 800933e: 687b ldr r3, [r7, #4] 8009340: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8009344: 2b01 cmp r3, #1 8009346: d101 bne.n 800934c 8009348: 2302 movs r3, #2 800934a: e012 b.n 8009372 800934c: 687b ldr r3, [r7, #4] 800934e: 2201 movs r2, #1 8009350: f883 2290 strb.w r2, [r3, #656] @ 0x290 hpcd->USB_Address = address; 8009354: 687b ldr r3, [r7, #4] 8009356: 78fa ldrb r2, [r7, #3] 8009358: 731a strb r2, [r3, #12] (void)USB_SetDevAddress(hpcd->Instance, address); 800935a: 687b ldr r3, [r7, #4] 800935c: 681b ldr r3, [r3, #0] 800935e: 78fa ldrb r2, [r7, #3] 8009360: 4611 mov r1, r2 8009362: 4618 mov r0, r3 8009364: f007 f800 bl 8010368 __HAL_UNLOCK(hpcd); 8009368: 687b ldr r3, [r7, #4] 800936a: 2200 movs r2, #0 800936c: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8009370: 2300 movs r3, #0 } 8009372: 4618 mov r0, r3 8009374: 3708 adds r7, #8 8009376: 46bd mov sp, r7 8009378: bd80 pop {r7, pc} 0800937a : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 800937a: b580 push {r7, lr} 800937c: b084 sub sp, #16 800937e: af00 add r7, sp, #0 8009380: 6078 str r0, [r7, #4] 8009382: 4608 mov r0, r1 8009384: 4611 mov r1, r2 8009386: 461a mov r2, r3 8009388: 4603 mov r3, r0 800938a: 70fb strb r3, [r7, #3] 800938c: 460b mov r3, r1 800938e: 803b strh r3, [r7, #0] 8009390: 4613 mov r3, r2 8009392: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8009394: 2300 movs r3, #0 8009396: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8009398: f997 3003 ldrsb.w r3, [r7, #3] 800939c: 2b00 cmp r3, #0 800939e: da0e bge.n 80093be { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80093a0: 78fb ldrb r3, [r7, #3] 80093a2: f003 0207 and.w r2, r3, #7 80093a6: 4613 mov r3, r2 80093a8: 009b lsls r3, r3, #2 80093aa: 4413 add r3, r2 80093ac: 00db lsls r3, r3, #3 80093ae: 3310 adds r3, #16 80093b0: 687a ldr r2, [r7, #4] 80093b2: 4413 add r3, r2 80093b4: 60fb str r3, [r7, #12] ep->is_in = 1U; 80093b6: 68fb ldr r3, [r7, #12] 80093b8: 2201 movs r2, #1 80093ba: 705a strb r2, [r3, #1] 80093bc: e00e b.n 80093dc } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80093be: 78fb ldrb r3, [r7, #3] 80093c0: f003 0207 and.w r2, r3, #7 80093c4: 4613 mov r3, r2 80093c6: 009b lsls r3, r3, #2 80093c8: 4413 add r3, r2 80093ca: 00db lsls r3, r3, #3 80093cc: f503 73a8 add.w r3, r3, #336 @ 0x150 80093d0: 687a ldr r2, [r7, #4] 80093d2: 4413 add r3, r2 80093d4: 60fb str r3, [r7, #12] ep->is_in = 0U; 80093d6: 68fb ldr r3, [r7, #12] 80093d8: 2200 movs r2, #0 80093da: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 80093dc: 78fb ldrb r3, [r7, #3] 80093de: f003 0307 and.w r3, r3, #7 80093e2: b2da uxtb r2, r3 80093e4: 68fb ldr r3, [r7, #12] 80093e6: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 80093e8: 883b ldrh r3, [r7, #0] 80093ea: f3c3 020a ubfx r2, r3, #0, #11 80093ee: 68fb ldr r3, [r7, #12] 80093f0: 611a str r2, [r3, #16] ep->type = ep_type; 80093f2: 68fb ldr r3, [r7, #12] 80093f4: 78ba ldrb r2, [r7, #2] 80093f6: 70da strb r2, [r3, #3] /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 80093f8: 78bb ldrb r3, [r7, #2] 80093fa: 2b02 cmp r3, #2 80093fc: d102 bne.n 8009404 { ep->data_pid_start = 0U; 80093fe: 68fb ldr r3, [r7, #12] 8009400: 2200 movs r2, #0 8009402: 711a strb r2, [r3, #4] } __HAL_LOCK(hpcd); 8009404: 687b ldr r3, [r7, #4] 8009406: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 800940a: 2b01 cmp r3, #1 800940c: d101 bne.n 8009412 800940e: 2302 movs r3, #2 8009410: e00e b.n 8009430 8009412: 687b ldr r3, [r7, #4] 8009414: 2201 movs r2, #1 8009416: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 800941a: 687b ldr r3, [r7, #4] 800941c: 681b ldr r3, [r3, #0] 800941e: 68f9 ldr r1, [r7, #12] 8009420: 4618 mov r0, r3 8009422: f005 fa23 bl 800e86c __HAL_UNLOCK(hpcd); 8009426: 687b ldr r3, [r7, #4] 8009428: 2200 movs r2, #0 800942a: f883 2290 strb.w r2, [r3, #656] @ 0x290 return ret; 800942e: 7afb ldrb r3, [r7, #11] } 8009430: 4618 mov r0, r3 8009432: 3710 adds r7, #16 8009434: 46bd mov sp, r7 8009436: bd80 pop {r7, pc} 08009438 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8009438: b580 push {r7, lr} 800943a: b084 sub sp, #16 800943c: af00 add r7, sp, #0 800943e: 6078 str r0, [r7, #4] 8009440: 460b mov r3, r1 8009442: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8009444: f997 3003 ldrsb.w r3, [r7, #3] 8009448: 2b00 cmp r3, #0 800944a: da0e bge.n 800946a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800944c: 78fb ldrb r3, [r7, #3] 800944e: f003 0207 and.w r2, r3, #7 8009452: 4613 mov r3, r2 8009454: 009b lsls r3, r3, #2 8009456: 4413 add r3, r2 8009458: 00db lsls r3, r3, #3 800945a: 3310 adds r3, #16 800945c: 687a ldr r2, [r7, #4] 800945e: 4413 add r3, r2 8009460: 60fb str r3, [r7, #12] ep->is_in = 1U; 8009462: 68fb ldr r3, [r7, #12] 8009464: 2201 movs r2, #1 8009466: 705a strb r2, [r3, #1] 8009468: e00e b.n 8009488 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 800946a: 78fb ldrb r3, [r7, #3] 800946c: f003 0207 and.w r2, r3, #7 8009470: 4613 mov r3, r2 8009472: 009b lsls r3, r3, #2 8009474: 4413 add r3, r2 8009476: 00db lsls r3, r3, #3 8009478: f503 73a8 add.w r3, r3, #336 @ 0x150 800947c: 687a ldr r2, [r7, #4] 800947e: 4413 add r3, r2 8009480: 60fb str r3, [r7, #12] ep->is_in = 0U; 8009482: 68fb ldr r3, [r7, #12] 8009484: 2200 movs r2, #0 8009486: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8009488: 78fb ldrb r3, [r7, #3] 800948a: f003 0307 and.w r3, r3, #7 800948e: b2da uxtb r2, r3 8009490: 68fb ldr r3, [r7, #12] 8009492: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8009494: 687b ldr r3, [r7, #4] 8009496: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 800949a: 2b01 cmp r3, #1 800949c: d101 bne.n 80094a2 800949e: 2302 movs r3, #2 80094a0: e00e b.n 80094c0 80094a2: 687b ldr r3, [r7, #4] 80094a4: 2201 movs r2, #1 80094a6: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 80094aa: 687b ldr r3, [r7, #4] 80094ac: 681b ldr r3, [r3, #0] 80094ae: 68f9 ldr r1, [r7, #12] 80094b0: 4618 mov r0, r3 80094b2: f005 fec3 bl 800f23c __HAL_UNLOCK(hpcd); 80094b6: 687b ldr r3, [r7, #4] 80094b8: 2200 movs r2, #0 80094ba: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 80094be: 2300 movs r3, #0 } 80094c0: 4618 mov r0, r3 80094c2: 3710 adds r7, #16 80094c4: 46bd mov sp, r7 80094c6: bd80 pop {r7, pc} 080094c8 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 80094c8: b580 push {r7, lr} 80094ca: b086 sub sp, #24 80094cc: af00 add r7, sp, #0 80094ce: 60f8 str r0, [r7, #12] 80094d0: 607a str r2, [r7, #4] 80094d2: 603b str r3, [r7, #0] 80094d4: 460b mov r3, r1 80094d6: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80094d8: 7afb ldrb r3, [r7, #11] 80094da: f003 0207 and.w r2, r3, #7 80094de: 4613 mov r3, r2 80094e0: 009b lsls r3, r3, #2 80094e2: 4413 add r3, r2 80094e4: 00db lsls r3, r3, #3 80094e6: f503 73a8 add.w r3, r3, #336 @ 0x150 80094ea: 68fa ldr r2, [r7, #12] 80094ec: 4413 add r3, r2 80094ee: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 80094f0: 697b ldr r3, [r7, #20] 80094f2: 687a ldr r2, [r7, #4] 80094f4: 615a str r2, [r3, #20] ep->xfer_len = len; 80094f6: 697b ldr r3, [r7, #20] 80094f8: 683a ldr r2, [r7, #0] 80094fa: 619a str r2, [r3, #24] ep->xfer_count = 0U; 80094fc: 697b ldr r3, [r7, #20] 80094fe: 2200 movs r2, #0 8009500: 61da str r2, [r3, #28] ep->is_in = 0U; 8009502: 697b ldr r3, [r7, #20] 8009504: 2200 movs r2, #0 8009506: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8009508: 7afb ldrb r3, [r7, #11] 800950a: f003 0307 and.w r3, r3, #7 800950e: b2da uxtb r2, r3 8009510: 697b ldr r3, [r7, #20] 8009512: 701a strb r2, [r3, #0] (void)USB_EPStartXfer(hpcd->Instance, ep); 8009514: 68fb ldr r3, [r7, #12] 8009516: 681b ldr r3, [r3, #0] 8009518: 6979 ldr r1, [r7, #20] 800951a: 4618 mov r0, r3 800951c: f006 f87b bl 800f616 return HAL_OK; 8009520: 2300 movs r3, #0 } 8009522: 4618 mov r0, r3 8009524: 3718 adds r7, #24 8009526: 46bd mov sp, r7 8009528: bd80 pop {r7, pc} 0800952a : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval Data Size */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { 800952a: b480 push {r7} 800952c: b083 sub sp, #12 800952e: af00 add r7, sp, #0 8009530: 6078 str r0, [r7, #4] 8009532: 460b mov r3, r1 8009534: 70fb strb r3, [r7, #3] return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; 8009536: 78fb ldrb r3, [r7, #3] 8009538: f003 0207 and.w r2, r3, #7 800953c: 6879 ldr r1, [r7, #4] 800953e: 4613 mov r3, r2 8009540: 009b lsls r3, r3, #2 8009542: 4413 add r3, r2 8009544: 00db lsls r3, r3, #3 8009546: 440b add r3, r1 8009548: f503 73b6 add.w r3, r3, #364 @ 0x16c 800954c: 681b ldr r3, [r3, #0] } 800954e: 4618 mov r0, r3 8009550: 370c adds r7, #12 8009552: 46bd mov sp, r7 8009554: f85d 7b04 ldr.w r7, [sp], #4 8009558: 4770 bx lr 0800955a : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 800955a: b580 push {r7, lr} 800955c: b086 sub sp, #24 800955e: af00 add r7, sp, #0 8009560: 60f8 str r0, [r7, #12] 8009562: 607a str r2, [r7, #4] 8009564: 603b str r3, [r7, #0] 8009566: 460b mov r3, r1 8009568: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800956a: 7afb ldrb r3, [r7, #11] 800956c: f003 0207 and.w r2, r3, #7 8009570: 4613 mov r3, r2 8009572: 009b lsls r3, r3, #2 8009574: 4413 add r3, r2 8009576: 00db lsls r3, r3, #3 8009578: 3310 adds r3, #16 800957a: 68fa ldr r2, [r7, #12] 800957c: 4413 add r3, r2 800957e: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8009580: 697b ldr r3, [r7, #20] 8009582: 687a ldr r2, [r7, #4] 8009584: 615a str r2, [r3, #20] ep->xfer_len = len; 8009586: 697b ldr r3, [r7, #20] 8009588: 683a ldr r2, [r7, #0] 800958a: 619a str r2, [r3, #24] ep->xfer_fill_db = 1U; 800958c: 697b ldr r3, [r7, #20] 800958e: 2201 movs r2, #1 8009590: f883 2024 strb.w r2, [r3, #36] @ 0x24 ep->xfer_len_db = len; 8009594: 697b ldr r3, [r7, #20] 8009596: 683a ldr r2, [r7, #0] 8009598: 621a str r2, [r3, #32] ep->xfer_count = 0U; 800959a: 697b ldr r3, [r7, #20] 800959c: 2200 movs r2, #0 800959e: 61da str r2, [r3, #28] ep->is_in = 1U; 80095a0: 697b ldr r3, [r7, #20] 80095a2: 2201 movs r2, #1 80095a4: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 80095a6: 7afb ldrb r3, [r7, #11] 80095a8: f003 0307 and.w r3, r3, #7 80095ac: b2da uxtb r2, r3 80095ae: 697b ldr r3, [r7, #20] 80095b0: 701a strb r2, [r3, #0] (void)USB_EPStartXfer(hpcd->Instance, ep); 80095b2: 68fb ldr r3, [r7, #12] 80095b4: 681b ldr r3, [r3, #0] 80095b6: 6979 ldr r1, [r7, #20] 80095b8: 4618 mov r0, r3 80095ba: f006 f82c bl 800f616 return HAL_OK; 80095be: 2300 movs r3, #0 } 80095c0: 4618 mov r0, r3 80095c2: 3718 adds r7, #24 80095c4: 46bd mov sp, r7 80095c6: bd80 pop {r7, pc} 080095c8 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80095c8: b580 push {r7, lr} 80095ca: b084 sub sp, #16 80095cc: af00 add r7, sp, #0 80095ce: 6078 str r0, [r7, #4] 80095d0: 460b mov r3, r1 80095d2: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 80095d4: 78fb ldrb r3, [r7, #3] 80095d6: f003 0307 and.w r3, r3, #7 80095da: 687a ldr r2, [r7, #4] 80095dc: 7912 ldrb r2, [r2, #4] 80095de: 4293 cmp r3, r2 80095e0: d901 bls.n 80095e6 { return HAL_ERROR; 80095e2: 2301 movs r3, #1 80095e4: e03e b.n 8009664 } if ((0x80U & ep_addr) == 0x80U) 80095e6: f997 3003 ldrsb.w r3, [r7, #3] 80095ea: 2b00 cmp r3, #0 80095ec: da0e bge.n 800960c { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80095ee: 78fb ldrb r3, [r7, #3] 80095f0: f003 0207 and.w r2, r3, #7 80095f4: 4613 mov r3, r2 80095f6: 009b lsls r3, r3, #2 80095f8: 4413 add r3, r2 80095fa: 00db lsls r3, r3, #3 80095fc: 3310 adds r3, #16 80095fe: 687a ldr r2, [r7, #4] 8009600: 4413 add r3, r2 8009602: 60fb str r3, [r7, #12] ep->is_in = 1U; 8009604: 68fb ldr r3, [r7, #12] 8009606: 2201 movs r2, #1 8009608: 705a strb r2, [r3, #1] 800960a: e00c b.n 8009626 } else { ep = &hpcd->OUT_ep[ep_addr]; 800960c: 78fa ldrb r2, [r7, #3] 800960e: 4613 mov r3, r2 8009610: 009b lsls r3, r3, #2 8009612: 4413 add r3, r2 8009614: 00db lsls r3, r3, #3 8009616: f503 73a8 add.w r3, r3, #336 @ 0x150 800961a: 687a ldr r2, [r7, #4] 800961c: 4413 add r3, r2 800961e: 60fb str r3, [r7, #12] ep->is_in = 0U; 8009620: 68fb ldr r3, [r7, #12] 8009622: 2200 movs r2, #0 8009624: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8009626: 68fb ldr r3, [r7, #12] 8009628: 2201 movs r2, #1 800962a: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 800962c: 78fb ldrb r3, [r7, #3] 800962e: f003 0307 and.w r3, r3, #7 8009632: b2da uxtb r2, r3 8009634: 68fb ldr r3, [r7, #12] 8009636: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8009638: 687b ldr r3, [r7, #4] 800963a: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 800963e: 2b01 cmp r3, #1 8009640: d101 bne.n 8009646 8009642: 2302 movs r3, #2 8009644: e00e b.n 8009664 8009646: 687b ldr r3, [r7, #4] 8009648: 2201 movs r2, #1 800964a: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_EPSetStall(hpcd->Instance, ep); 800964e: 687b ldr r3, [r7, #4] 8009650: 681b ldr r3, [r3, #0] 8009652: 68f9 ldr r1, [r7, #12] 8009654: 4618 mov r0, r3 8009656: f006 fd8d bl 8010174 __HAL_UNLOCK(hpcd); 800965a: 687b ldr r3, [r7, #4] 800965c: 2200 movs r2, #0 800965e: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8009662: 2300 movs r3, #0 } 8009664: 4618 mov r0, r3 8009666: 3710 adds r7, #16 8009668: 46bd mov sp, r7 800966a: bd80 pop {r7, pc} 0800966c : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 800966c: b580 push {r7, lr} 800966e: b084 sub sp, #16 8009670: af00 add r7, sp, #0 8009672: 6078 str r0, [r7, #4] 8009674: 460b mov r3, r1 8009676: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8009678: 78fb ldrb r3, [r7, #3] 800967a: f003 030f and.w r3, r3, #15 800967e: 687a ldr r2, [r7, #4] 8009680: 7912 ldrb r2, [r2, #4] 8009682: 4293 cmp r3, r2 8009684: d901 bls.n 800968a { return HAL_ERROR; 8009686: 2301 movs r3, #1 8009688: e040 b.n 800970c } if ((0x80U & ep_addr) == 0x80U) 800968a: f997 3003 ldrsb.w r3, [r7, #3] 800968e: 2b00 cmp r3, #0 8009690: da0e bge.n 80096b0 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8009692: 78fb ldrb r3, [r7, #3] 8009694: f003 0207 and.w r2, r3, #7 8009698: 4613 mov r3, r2 800969a: 009b lsls r3, r3, #2 800969c: 4413 add r3, r2 800969e: 00db lsls r3, r3, #3 80096a0: 3310 adds r3, #16 80096a2: 687a ldr r2, [r7, #4] 80096a4: 4413 add r3, r2 80096a6: 60fb str r3, [r7, #12] ep->is_in = 1U; 80096a8: 68fb ldr r3, [r7, #12] 80096aa: 2201 movs r2, #1 80096ac: 705a strb r2, [r3, #1] 80096ae: e00e b.n 80096ce } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80096b0: 78fb ldrb r3, [r7, #3] 80096b2: f003 0207 and.w r2, r3, #7 80096b6: 4613 mov r3, r2 80096b8: 009b lsls r3, r3, #2 80096ba: 4413 add r3, r2 80096bc: 00db lsls r3, r3, #3 80096be: f503 73a8 add.w r3, r3, #336 @ 0x150 80096c2: 687a ldr r2, [r7, #4] 80096c4: 4413 add r3, r2 80096c6: 60fb str r3, [r7, #12] ep->is_in = 0U; 80096c8: 68fb ldr r3, [r7, #12] 80096ca: 2200 movs r2, #0 80096cc: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 80096ce: 68fb ldr r3, [r7, #12] 80096d0: 2200 movs r2, #0 80096d2: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 80096d4: 78fb ldrb r3, [r7, #3] 80096d6: f003 0307 and.w r3, r3, #7 80096da: b2da uxtb r2, r3 80096dc: 68fb ldr r3, [r7, #12] 80096de: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 80096e0: 687b ldr r3, [r7, #4] 80096e2: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 80096e6: 2b01 cmp r3, #1 80096e8: d101 bne.n 80096ee 80096ea: 2302 movs r3, #2 80096ec: e00e b.n 800970c 80096ee: 687b ldr r3, [r7, #4] 80096f0: 2201 movs r2, #1 80096f2: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_EPClearStall(hpcd->Instance, ep); 80096f6: 687b ldr r3, [r7, #4] 80096f8: 681b ldr r3, [r3, #0] 80096fa: 68f9 ldr r1, [r7, #12] 80096fc: 4618 mov r0, r3 80096fe: f006 fd8a bl 8010216 __HAL_UNLOCK(hpcd); 8009702: 687b ldr r3, [r7, #4] 8009704: 2200 movs r2, #0 8009706: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 800970a: 2300 movs r3, #0 } 800970c: 4618 mov r0, r3 800970e: 3710 adds r7, #16 8009710: 46bd mov sp, r7 8009712: bd80 pop {r7, pc} 08009714 : * @brief This function handles PCD Endpoint interrupt request. * @param hpcd PCD handle * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { 8009714: b580 push {r7, lr} 8009716: b094 sub sp, #80 @ 0x50 8009718: af00 add r7, sp, #0 800971a: 6078 str r0, [r7, #4] #if (USE_USB_DOUBLE_BUFFER != 1U) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) 800971c: e374 b.n 8009e08 { wIstr = hpcd->Instance->ISTR; 800971e: 687b ldr r3, [r7, #4] 8009720: 681b ldr r3, [r3, #0] 8009722: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8009726: f8a7 3042 strh.w r3, [r7, #66] @ 0x42 /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); 800972a: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42 800972e: b2db uxtb r3, r3 8009730: f003 030f and.w r3, r3, #15 8009734: f887 3041 strb.w r3, [r7, #65] @ 0x41 if (epindex == 0U) 8009738: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 800973c: 2b00 cmp r3, #0 800973e: f040 8143 bne.w 80099c8 { /* Decode and service control endpoint interrupt */ /* DIR bit = origin of the interrupt */ if ((wIstr & USB_ISTR_DIR) == 0U) 8009742: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42 8009746: f003 0310 and.w r3, r3, #16 800974a: 2b00 cmp r3, #0 800974c: d14c bne.n 80097e8 { /* DIR = 0 */ /* DIR = 0 => IN int */ /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); 800974e: 687b ldr r3, [r7, #4] 8009750: 681b ldr r3, [r3, #0] 8009752: 881b ldrh r3, [r3, #0] 8009754: b29b uxth r3, r3 8009756: f423 43e1 bic.w r3, r3, #28800 @ 0x7080 800975a: f023 0370 bic.w r3, r3, #112 @ 0x70 800975e: 817b strh r3, [r7, #10] 8009760: 687b ldr r3, [r7, #4] 8009762: 681a ldr r2, [r3, #0] 8009764: 897b ldrh r3, [r7, #10] 8009766: ea6f 4343 mvn.w r3, r3, lsl #17 800976a: ea6f 4353 mvn.w r3, r3, lsr #17 800976e: b29b uxth r3, r3 8009770: 8013 strh r3, [r2, #0] ep = &hpcd->IN_ep[0]; 8009772: 687b ldr r3, [r7, #4] 8009774: 3310 adds r3, #16 8009776: 64bb str r3, [r7, #72] @ 0x48 ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); 8009778: 687b ldr r3, [r7, #4] 800977a: 681b ldr r3, [r3, #0] 800977c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009780: b29b uxth r3, r3 8009782: 461a mov r2, r3 8009784: 6cbb ldr r3, [r7, #72] @ 0x48 8009786: 781b ldrb r3, [r3, #0] 8009788: 00db lsls r3, r3, #3 800978a: 4413 add r3, r2 800978c: 687a ldr r2, [r7, #4] 800978e: 6812 ldr r2, [r2, #0] 8009790: 4413 add r3, r2 8009792: f203 4302 addw r3, r3, #1026 @ 0x402 8009796: 881b ldrh r3, [r3, #0] 8009798: f3c3 0209 ubfx r2, r3, #0, #10 800979c: 6cbb ldr r3, [r7, #72] @ 0x48 800979e: 61da str r2, [r3, #28] ep->xfer_buff += ep->xfer_count; 80097a0: 6cbb ldr r3, [r7, #72] @ 0x48 80097a2: 695a ldr r2, [r3, #20] 80097a4: 6cbb ldr r3, [r7, #72] @ 0x48 80097a6: 69db ldr r3, [r3, #28] 80097a8: 441a add r2, r3 80097aa: 6cbb ldr r3, [r7, #72] @ 0x48 80097ac: 615a str r2, [r3, #20] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, 0U); #else HAL_PCD_DataInStageCallback(hpcd, 0U); 80097ae: 2100 movs r1, #0 80097b0: 6878 ldr r0, [r7, #4] 80097b2: f00e fe3c bl 801842e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) 80097b6: 687b ldr r3, [r7, #4] 80097b8: 7b1b ldrb r3, [r3, #12] 80097ba: b2db uxtb r3, r3 80097bc: 2b00 cmp r3, #0 80097be: f000 8323 beq.w 8009e08 80097c2: 6cbb ldr r3, [r7, #72] @ 0x48 80097c4: 699b ldr r3, [r3, #24] 80097c6: 2b00 cmp r3, #0 80097c8: f040 831e bne.w 8009e08 { hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); 80097cc: 687b ldr r3, [r7, #4] 80097ce: 7b1b ldrb r3, [r3, #12] 80097d0: b2db uxtb r3, r3 80097d2: f063 037f orn r3, r3, #127 @ 0x7f 80097d6: b2da uxtb r2, r3 80097d8: 687b ldr r3, [r7, #4] 80097da: 681b ldr r3, [r3, #0] 80097dc: f8a3 204c strh.w r2, [r3, #76] @ 0x4c hpcd->USB_Address = 0U; 80097e0: 687b ldr r3, [r7, #4] 80097e2: 2200 movs r2, #0 80097e4: 731a strb r2, [r3, #12] 80097e6: e30f b.n 8009e08 { /* DIR = 1 */ /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; 80097e8: 687b ldr r3, [r7, #4] 80097ea: f503 73a8 add.w r3, r3, #336 @ 0x150 80097ee: 64bb str r3, [r7, #72] @ 0x48 wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); 80097f0: 687b ldr r3, [r7, #4] 80097f2: 681b ldr r3, [r3, #0] 80097f4: 881b ldrh r3, [r3, #0] 80097f6: 87fb strh r3, [r7, #62] @ 0x3e if ((wEPVal & USB_EP_SETUP) != 0U) 80097f8: 8ffb ldrh r3, [r7, #62] @ 0x3e 80097fa: f403 6300 and.w r3, r3, #2048 @ 0x800 80097fe: 2b00 cmp r3, #0 8009800: d07b beq.n 80098fa { /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8009802: 687b ldr r3, [r7, #4] 8009804: 681b ldr r3, [r3, #0] 8009806: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800980a: b29b uxth r3, r3 800980c: 461a mov r2, r3 800980e: 6cbb ldr r3, [r7, #72] @ 0x48 8009810: 781b ldrb r3, [r3, #0] 8009812: 00db lsls r3, r3, #3 8009814: 4413 add r3, r2 8009816: 687a ldr r2, [r7, #4] 8009818: 6812 ldr r2, [r2, #0] 800981a: 4413 add r3, r2 800981c: f203 4306 addw r3, r3, #1030 @ 0x406 8009820: 881b ldrh r3, [r3, #0] 8009822: f3c3 0209 ubfx r2, r3, #0, #10 8009826: 6cbb ldr r3, [r7, #72] @ 0x48 8009828: 61da str r2, [r3, #28] if (ep->xfer_count != 8U) 800982a: 6cbb ldr r3, [r7, #72] @ 0x48 800982c: 69db ldr r3, [r3, #28] 800982e: 2b08 cmp r3, #8 8009830: d044 beq.n 80098bc { /* Set Stall condition for EP0 IN/OUT */ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); 8009832: 687b ldr r3, [r7, #4] 8009834: 681b ldr r3, [r3, #0] 8009836: 881b ldrh r3, [r3, #0] 8009838: b29b uxth r3, r3 800983a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800983e: f023 0370 bic.w r3, r3, #112 @ 0x70 8009842: 823b strh r3, [r7, #16] 8009844: 8a3b ldrh r3, [r7, #16] 8009846: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800984a: 823b strh r3, [r7, #16] 800984c: 687b ldr r3, [r7, #4] 800984e: 681a ldr r2, [r3, #0] 8009850: 8a3b ldrh r3, [r7, #16] 8009852: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009856: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800985a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800985e: f043 0380 orr.w r3, r3, #128 @ 0x80 8009862: b29b uxth r3, r3 8009864: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); 8009866: 687b ldr r3, [r7, #4] 8009868: 681b ldr r3, [r3, #0] 800986a: 881b ldrh r3, [r3, #0] 800986c: b29b uxth r3, r3 800986e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009872: f023 0340 bic.w r3, r3, #64 @ 0x40 8009876: 81fb strh r3, [r7, #14] 8009878: 89fb ldrh r3, [r7, #14] 800987a: f083 0310 eor.w r3, r3, #16 800987e: 81fb strh r3, [r7, #14] 8009880: 687b ldr r3, [r7, #4] 8009882: 681a ldr r2, [r3, #0] 8009884: 89fb ldrh r3, [r7, #14] 8009886: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800988a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800988e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009892: f043 0380 orr.w r3, r3, #128 @ 0x80 8009896: b29b uxth r3, r3 8009898: 8013 strh r3, [r2, #0] /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 800989a: 687b ldr r3, [r7, #4] 800989c: 681b ldr r3, [r3, #0] 800989e: 881b ldrh r3, [r3, #0] 80098a0: b29a uxth r2, r3 80098a2: f640 738f movw r3, #3983 @ 0xf8f 80098a6: 4013 ands r3, r2 80098a8: 81bb strh r3, [r7, #12] 80098aa: 687b ldr r3, [r7, #4] 80098ac: 681b ldr r3, [r3, #0] 80098ae: 89ba ldrh r2, [r7, #12] 80098b0: f042 0280 orr.w r2, r2, #128 @ 0x80 80098b4: b292 uxth r2, r2 80098b6: 801a strh r2, [r3, #0] return HAL_OK; 80098b8: 2300 movs r3, #0 80098ba: e2af b.n 8009e1c } USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, 80098bc: 687b ldr r3, [r7, #4] 80098be: 6818 ldr r0, [r3, #0] 80098c0: 687b ldr r3, [r7, #4] 80098c2: f503 7126 add.w r1, r3, #664 @ 0x298 80098c6: 6cbb ldr r3, [r7, #72] @ 0x48 80098c8: 88da ldrh r2, [r3, #6] ep->pmaadress, (uint16_t)ep->xfer_count); 80098ca: 6cbb ldr r3, [r7, #72] @ 0x48 80098cc: 69db ldr r3, [r3, #28] USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, 80098ce: b29b uxth r3, r3 80098d0: f006 fdc8 bl 8010464 /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 80098d4: 687b ldr r3, [r7, #4] 80098d6: 681b ldr r3, [r3, #0] 80098d8: 881b ldrh r3, [r3, #0] 80098da: b29a uxth r2, r3 80098dc: f640 738f movw r3, #3983 @ 0xf8f 80098e0: 4013 ands r3, r2 80098e2: 827b strh r3, [r7, #18] 80098e4: 687b ldr r3, [r7, #4] 80098e6: 681b ldr r3, [r3, #0] 80098e8: 8a7a ldrh r2, [r7, #18] 80098ea: f042 0280 orr.w r2, r2, #128 @ 0x80 80098ee: b292 uxth r2, r2 80098f0: 801a strh r2, [r3, #0] /* Process SETUP Packet*/ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 80098f2: 6878 ldr r0, [r7, #4] 80098f4: f00e fd6e bl 80183d4 80098f8: e286 b.n 8009e08 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else if ((wEPVal & USB_EP_CTR_RX) != 0U) 80098fa: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e 80098fe: 2b00 cmp r3, #0 8009900: f280 8282 bge.w 8009e08 { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 8009904: 687b ldr r3, [r7, #4] 8009906: 681b ldr r3, [r3, #0] 8009908: 881b ldrh r3, [r3, #0] 800990a: b29a uxth r2, r3 800990c: f640 738f movw r3, #3983 @ 0xf8f 8009910: 4013 ands r3, r2 8009912: 82fb strh r3, [r7, #22] 8009914: 687b ldr r3, [r7, #4] 8009916: 681b ldr r3, [r3, #0] 8009918: 8afa ldrh r2, [r7, #22] 800991a: f042 0280 orr.w r2, r2, #128 @ 0x80 800991e: b292 uxth r2, r2 8009920: 801a strh r2, [r3, #0] /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8009922: 687b ldr r3, [r7, #4] 8009924: 681b ldr r3, [r3, #0] 8009926: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800992a: b29b uxth r3, r3 800992c: 461a mov r2, r3 800992e: 6cbb ldr r3, [r7, #72] @ 0x48 8009930: 781b ldrb r3, [r3, #0] 8009932: 00db lsls r3, r3, #3 8009934: 4413 add r3, r2 8009936: 687a ldr r2, [r7, #4] 8009938: 6812 ldr r2, [r2, #0] 800993a: 4413 add r3, r2 800993c: f203 4306 addw r3, r3, #1030 @ 0x406 8009940: 881b ldrh r3, [r3, #0] 8009942: f3c3 0209 ubfx r2, r3, #0, #10 8009946: 6cbb ldr r3, [r7, #72] @ 0x48 8009948: 61da str r2, [r3, #28] if (ep->xfer_count == 0U) 800994a: 6cbb ldr r3, [r7, #72] @ 0x48 800994c: 69db ldr r3, [r3, #28] 800994e: 2b00 cmp r3, #0 8009950: d11e bne.n 8009990 { /* Status phase re-arm for next setup */ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); 8009952: 687b ldr r3, [r7, #4] 8009954: 681b ldr r3, [r3, #0] 8009956: 881b ldrh r3, [r3, #0] 8009958: b29b uxth r3, r3 800995a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800995e: f023 0370 bic.w r3, r3, #112 @ 0x70 8009962: 82bb strh r3, [r7, #20] 8009964: 8abb ldrh r3, [r7, #20] 8009966: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800996a: 82bb strh r3, [r7, #20] 800996c: 8abb ldrh r3, [r7, #20] 800996e: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8009972: 82bb strh r3, [r7, #20] 8009974: 687b ldr r3, [r7, #4] 8009976: 681a ldr r2, [r3, #0] 8009978: 8abb ldrh r3, [r7, #20] 800997a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800997e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009982: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009986: f043 0380 orr.w r3, r3, #128 @ 0x80 800998a: b29b uxth r3, r3 800998c: 8013 strh r3, [r2, #0] 800998e: e23b b.n 8009e08 } else { if (ep->xfer_buff != 0U) 8009990: 6cbb ldr r3, [r7, #72] @ 0x48 8009992: 695b ldr r3, [r3, #20] 8009994: 2b00 cmp r3, #0 8009996: f000 8237 beq.w 8009e08 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, 800999a: 687b ldr r3, [r7, #4] 800999c: 6818 ldr r0, [r3, #0] 800999e: 6cbb ldr r3, [r7, #72] @ 0x48 80099a0: 6959 ldr r1, [r3, #20] 80099a2: 6cbb ldr r3, [r7, #72] @ 0x48 80099a4: 88da ldrh r2, [r3, #6] ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ 80099a6: 6cbb ldr r3, [r7, #72] @ 0x48 80099a8: 69db ldr r3, [r3, #28] USB_ReadPMA(hpcd->Instance, ep->xfer_buff, 80099aa: b29b uxth r3, r3 80099ac: f006 fd5a bl 8010464 ep->xfer_buff += ep->xfer_count; 80099b0: 6cbb ldr r3, [r7, #72] @ 0x48 80099b2: 695a ldr r2, [r3, #20] 80099b4: 6cbb ldr r3, [r7, #72] @ 0x48 80099b6: 69db ldr r3, [r3, #28] 80099b8: 441a add r2, r3 80099ba: 6cbb ldr r3, [r7, #72] @ 0x48 80099bc: 615a str r2, [r3, #20] /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, 0U); #else HAL_PCD_DataOutStageCallback(hpcd, 0U); 80099be: 2100 movs r1, #0 80099c0: 6878 ldr r0, [r7, #4] 80099c2: f00e fd19 bl 80183f8 80099c6: e21f b.n 8009e08 } else { /* Decode and service non control endpoints interrupt */ /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); 80099c8: 687b ldr r3, [r7, #4] 80099ca: 681b ldr r3, [r3, #0] 80099cc: 461a mov r2, r3 80099ce: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 80099d2: 009b lsls r3, r3, #2 80099d4: 4413 add r3, r2 80099d6: 881b ldrh r3, [r3, #0] 80099d8: 87fb strh r3, [r7, #62] @ 0x3e if ((wEPVal & USB_EP_CTR_RX) != 0U) 80099da: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e 80099de: 2b00 cmp r3, #0 80099e0: f280 80f5 bge.w 8009bce { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); 80099e4: 687b ldr r3, [r7, #4] 80099e6: 681b ldr r3, [r3, #0] 80099e8: 461a mov r2, r3 80099ea: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 80099ee: 009b lsls r3, r3, #2 80099f0: 4413 add r3, r2 80099f2: 881b ldrh r3, [r3, #0] 80099f4: b29a uxth r2, r3 80099f6: f640 738f movw r3, #3983 @ 0xf8f 80099fa: 4013 ands r3, r2 80099fc: f8a7 3046 strh.w r3, [r7, #70] @ 0x46 8009a00: 687b ldr r3, [r7, #4] 8009a02: 681b ldr r3, [r3, #0] 8009a04: 461a mov r2, r3 8009a06: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 8009a0a: 009b lsls r3, r3, #2 8009a0c: 4413 add r3, r2 8009a0e: f8b7 2046 ldrh.w r2, [r7, #70] @ 0x46 8009a12: f042 0280 orr.w r2, r2, #128 @ 0x80 8009a16: b292 uxth r2, r2 8009a18: 801a strh r2, [r3, #0] ep = &hpcd->OUT_ep[epindex]; 8009a1a: f897 2041 ldrb.w r2, [r7, #65] @ 0x41 8009a1e: 4613 mov r3, r2 8009a20: 009b lsls r3, r3, #2 8009a22: 4413 add r3, r2 8009a24: 00db lsls r3, r3, #3 8009a26: f503 73a8 add.w r3, r3, #336 @ 0x150 8009a2a: 687a ldr r2, [r7, #4] 8009a2c: 4413 add r3, r2 8009a2e: 64bb str r3, [r7, #72] @ 0x48 /* OUT Single Buffering */ if (ep->doublebuffer == 0U) 8009a30: 6cbb ldr r3, [r7, #72] @ 0x48 8009a32: 7b1b ldrb r3, [r3, #12] 8009a34: 2b00 cmp r3, #0 8009a36: d123 bne.n 8009a80 { count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8009a38: 687b ldr r3, [r7, #4] 8009a3a: 681b ldr r3, [r3, #0] 8009a3c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009a40: b29b uxth r3, r3 8009a42: 461a mov r2, r3 8009a44: 6cbb ldr r3, [r7, #72] @ 0x48 8009a46: 781b ldrb r3, [r3, #0] 8009a48: 00db lsls r3, r3, #3 8009a4a: 4413 add r3, r2 8009a4c: 687a ldr r2, [r7, #4] 8009a4e: 6812 ldr r2, [r2, #0] 8009a50: 4413 add r3, r2 8009a52: f203 4306 addw r3, r3, #1030 @ 0x406 8009a56: 881b ldrh r3, [r3, #0] 8009a58: f3c3 0309 ubfx r3, r3, #0, #10 8009a5c: f8a7 304e strh.w r3, [r7, #78] @ 0x4e if (count != 0U) 8009a60: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8009a64: 2b00 cmp r3, #0 8009a66: f000 808d beq.w 8009b84 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); 8009a6a: 687b ldr r3, [r7, #4] 8009a6c: 6818 ldr r0, [r3, #0] 8009a6e: 6cbb ldr r3, [r7, #72] @ 0x48 8009a70: 6959 ldr r1, [r3, #20] 8009a72: 6cbb ldr r3, [r7, #72] @ 0x48 8009a74: 88da ldrh r2, [r3, #6] 8009a76: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8009a7a: f006 fcf3 bl 8010464 8009a7e: e081 b.n 8009b84 } #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* manage double buffer bulk out */ if (ep->type == EP_TYPE_BULK) 8009a80: 6cbb ldr r3, [r7, #72] @ 0x48 8009a82: 78db ldrb r3, [r3, #3] 8009a84: 2b02 cmp r3, #2 8009a86: d109 bne.n 8009a9c { count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); 8009a88: 8ffb ldrh r3, [r7, #62] @ 0x3e 8009a8a: 461a mov r2, r3 8009a8c: 6cb9 ldr r1, [r7, #72] @ 0x48 8009a8e: 6878 ldr r0, [r7, #4] 8009a90: f000 f9c8 bl 8009e24 8009a94: 4603 mov r3, r0 8009a96: f8a7 304e strh.w r3, [r7, #78] @ 0x4e 8009a9a: e073 b.n 8009b84 } else /* manage double buffer iso out */ { /* free EP OUT Buffer */ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 8009a9c: 687b ldr r3, [r7, #4] 8009a9e: 681b ldr r3, [r3, #0] 8009aa0: 461a mov r2, r3 8009aa2: 6cbb ldr r3, [r7, #72] @ 0x48 8009aa4: 781b ldrb r3, [r3, #0] 8009aa6: 009b lsls r3, r3, #2 8009aa8: 4413 add r3, r2 8009aaa: 881b ldrh r3, [r3, #0] 8009aac: b29b uxth r3, r3 8009aae: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009ab2: f023 0370 bic.w r3, r3, #112 @ 0x70 8009ab6: f8a7 3044 strh.w r3, [r7, #68] @ 0x44 8009aba: 687b ldr r3, [r7, #4] 8009abc: 681b ldr r3, [r3, #0] 8009abe: 461a mov r2, r3 8009ac0: 6cbb ldr r3, [r7, #72] @ 0x48 8009ac2: 781b ldrb r3, [r3, #0] 8009ac4: 009b lsls r3, r3, #2 8009ac6: 441a add r2, r3 8009ac8: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44 8009acc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009ad0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009ad4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009ad8: f043 03c0 orr.w r3, r3, #192 @ 0xc0 8009adc: b29b uxth r3, r3 8009ade: 8013 strh r3, [r2, #0] if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) 8009ae0: 687b ldr r3, [r7, #4] 8009ae2: 681b ldr r3, [r3, #0] 8009ae4: 461a mov r2, r3 8009ae6: 6cbb ldr r3, [r7, #72] @ 0x48 8009ae8: 781b ldrb r3, [r3, #0] 8009aea: 009b lsls r3, r3, #2 8009aec: 4413 add r3, r2 8009aee: 881b ldrh r3, [r3, #0] 8009af0: b29b uxth r3, r3 8009af2: f403 4380 and.w r3, r3, #16384 @ 0x4000 8009af6: 2b00 cmp r3, #0 8009af8: d022 beq.n 8009b40 { /* read from endpoint BUF0Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 8009afa: 687b ldr r3, [r7, #4] 8009afc: 681b ldr r3, [r3, #0] 8009afe: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009b02: b29b uxth r3, r3 8009b04: 461a mov r2, r3 8009b06: 6cbb ldr r3, [r7, #72] @ 0x48 8009b08: 781b ldrb r3, [r3, #0] 8009b0a: 00db lsls r3, r3, #3 8009b0c: 4413 add r3, r2 8009b0e: 687a ldr r2, [r7, #4] 8009b10: 6812 ldr r2, [r2, #0] 8009b12: 4413 add r3, r2 8009b14: f203 4302 addw r3, r3, #1026 @ 0x402 8009b18: 881b ldrh r3, [r3, #0] 8009b1a: f3c3 0309 ubfx r3, r3, #0, #10 8009b1e: f8a7 304e strh.w r3, [r7, #78] @ 0x4e if (count != 0U) 8009b22: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8009b26: 2b00 cmp r3, #0 8009b28: d02c beq.n 8009b84 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); 8009b2a: 687b ldr r3, [r7, #4] 8009b2c: 6818 ldr r0, [r3, #0] 8009b2e: 6cbb ldr r3, [r7, #72] @ 0x48 8009b30: 6959 ldr r1, [r3, #20] 8009b32: 6cbb ldr r3, [r7, #72] @ 0x48 8009b34: 891a ldrh r2, [r3, #8] 8009b36: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8009b3a: f006 fc93 bl 8010464 8009b3e: e021 b.n 8009b84 } } else { /* read from endpoint BUF1Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 8009b40: 687b ldr r3, [r7, #4] 8009b42: 681b ldr r3, [r3, #0] 8009b44: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009b48: b29b uxth r3, r3 8009b4a: 461a mov r2, r3 8009b4c: 6cbb ldr r3, [r7, #72] @ 0x48 8009b4e: 781b ldrb r3, [r3, #0] 8009b50: 00db lsls r3, r3, #3 8009b52: 4413 add r3, r2 8009b54: 687a ldr r2, [r7, #4] 8009b56: 6812 ldr r2, [r2, #0] 8009b58: 4413 add r3, r2 8009b5a: f203 4306 addw r3, r3, #1030 @ 0x406 8009b5e: 881b ldrh r3, [r3, #0] 8009b60: f3c3 0309 ubfx r3, r3, #0, #10 8009b64: f8a7 304e strh.w r3, [r7, #78] @ 0x4e if (count != 0U) 8009b68: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8009b6c: 2b00 cmp r3, #0 8009b6e: d009 beq.n 8009b84 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); 8009b70: 687b ldr r3, [r7, #4] 8009b72: 6818 ldr r0, [r3, #0] 8009b74: 6cbb ldr r3, [r7, #72] @ 0x48 8009b76: 6959 ldr r1, [r3, #20] 8009b78: 6cbb ldr r3, [r7, #72] @ 0x48 8009b7a: 895a ldrh r2, [r3, #10] 8009b7c: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8009b80: f006 fc70 bl 8010464 } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; 8009b84: 6cbb ldr r3, [r7, #72] @ 0x48 8009b86: 69da ldr r2, [r3, #28] 8009b88: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8009b8c: 441a add r2, r3 8009b8e: 6cbb ldr r3, [r7, #72] @ 0x48 8009b90: 61da str r2, [r3, #28] if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) 8009b92: 6cbb ldr r3, [r7, #72] @ 0x48 8009b94: 699b ldr r3, [r3, #24] 8009b96: 2b00 cmp r3, #0 8009b98: d005 beq.n 8009ba6 8009b9a: f8b7 204e ldrh.w r2, [r7, #78] @ 0x4e 8009b9e: 6cbb ldr r3, [r7, #72] @ 0x48 8009ba0: 691b ldr r3, [r3, #16] 8009ba2: 429a cmp r2, r3 8009ba4: d206 bcs.n 8009bb4 { /* RX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, ep->num); #else HAL_PCD_DataOutStageCallback(hpcd, ep->num); 8009ba6: 6cbb ldr r3, [r7, #72] @ 0x48 8009ba8: 781b ldrb r3, [r3, #0] 8009baa: 4619 mov r1, r3 8009bac: 6878 ldr r0, [r7, #4] 8009bae: f00e fc23 bl 80183f8 8009bb2: e00c b.n 8009bce #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { ep->xfer_buff += count; 8009bb4: 6cbb ldr r3, [r7, #72] @ 0x48 8009bb6: 695a ldr r2, [r3, #20] 8009bb8: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 8009bbc: 441a add r2, r3 8009bbe: 6cbb ldr r3, [r7, #72] @ 0x48 8009bc0: 615a str r2, [r3, #20] (void)USB_EPStartXfer(hpcd->Instance, ep); 8009bc2: 687b ldr r3, [r7, #4] 8009bc4: 681b ldr r3, [r3, #0] 8009bc6: 6cb9 ldr r1, [r7, #72] @ 0x48 8009bc8: 4618 mov r0, r3 8009bca: f005 fd24 bl 800f616 } } if ((wEPVal & USB_EP_CTR_TX) != 0U) 8009bce: 8ffb ldrh r3, [r7, #62] @ 0x3e 8009bd0: f003 0380 and.w r3, r3, #128 @ 0x80 8009bd4: 2b00 cmp r3, #0 8009bd6: f000 8117 beq.w 8009e08 { ep = &hpcd->IN_ep[epindex]; 8009bda: f897 2041 ldrb.w r2, [r7, #65] @ 0x41 8009bde: 4613 mov r3, r2 8009be0: 009b lsls r3, r3, #2 8009be2: 4413 add r3, r2 8009be4: 00db lsls r3, r3, #3 8009be6: 3310 adds r3, #16 8009be8: 687a ldr r2, [r7, #4] 8009bea: 4413 add r3, r2 8009bec: 64bb str r3, [r7, #72] @ 0x48 /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); 8009bee: 687b ldr r3, [r7, #4] 8009bf0: 681b ldr r3, [r3, #0] 8009bf2: 461a mov r2, r3 8009bf4: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 8009bf8: 009b lsls r3, r3, #2 8009bfa: 4413 add r3, r2 8009bfc: 881b ldrh r3, [r3, #0] 8009bfe: b29b uxth r3, r3 8009c00: f423 43e1 bic.w r3, r3, #28800 @ 0x7080 8009c04: f023 0370 bic.w r3, r3, #112 @ 0x70 8009c08: 87bb strh r3, [r7, #60] @ 0x3c 8009c0a: 687b ldr r3, [r7, #4] 8009c0c: 681b ldr r3, [r3, #0] 8009c0e: 461a mov r2, r3 8009c10: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 8009c14: 009b lsls r3, r3, #2 8009c16: 441a add r2, r3 8009c18: 8fbb ldrh r3, [r7, #60] @ 0x3c 8009c1a: ea6f 4343 mvn.w r3, r3, lsl #17 8009c1e: ea6f 4353 mvn.w r3, r3, lsr #17 8009c22: b29b uxth r3, r3 8009c24: 8013 strh r3, [r2, #0] if (ep->type == EP_TYPE_ISOC) 8009c26: 6cbb ldr r3, [r7, #72] @ 0x48 8009c28: 78db ldrb r3, [r3, #3] 8009c2a: 2b01 cmp r3, #1 8009c2c: f040 80a1 bne.w 8009d72 { ep->xfer_len = 0U; 8009c30: 6cbb ldr r3, [r7, #72] @ 0x48 8009c32: 2200 movs r2, #0 8009c34: 619a str r2, [r3, #24] #if (USE_USB_DOUBLE_BUFFER == 1U) if (ep->doublebuffer != 0U) 8009c36: 6cbb ldr r3, [r7, #72] @ 0x48 8009c38: 7b1b ldrb r3, [r3, #12] 8009c3a: 2b00 cmp r3, #0 8009c3c: f000 8092 beq.w 8009d64 { if ((wEPVal & USB_EP_DTOG_TX) != 0U) 8009c40: 8ffb ldrh r3, [r7, #62] @ 0x3e 8009c42: f003 0340 and.w r3, r3, #64 @ 0x40 8009c46: 2b00 cmp r3, #0 8009c48: d046 beq.n 8009cd8 { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 8009c4a: 6cbb ldr r3, [r7, #72] @ 0x48 8009c4c: 785b ldrb r3, [r3, #1] 8009c4e: 2b00 cmp r3, #0 8009c50: d126 bne.n 8009ca0 8009c52: 687b ldr r3, [r7, #4] 8009c54: 681b ldr r3, [r3, #0] 8009c56: 61fb str r3, [r7, #28] 8009c58: 687b ldr r3, [r7, #4] 8009c5a: 681b ldr r3, [r3, #0] 8009c5c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009c60: b29b uxth r3, r3 8009c62: 461a mov r2, r3 8009c64: 69fb ldr r3, [r7, #28] 8009c66: 4413 add r3, r2 8009c68: 61fb str r3, [r7, #28] 8009c6a: 6cbb ldr r3, [r7, #72] @ 0x48 8009c6c: 781b ldrb r3, [r3, #0] 8009c6e: 00da lsls r2, r3, #3 8009c70: 69fb ldr r3, [r7, #28] 8009c72: 4413 add r3, r2 8009c74: f203 4302 addw r3, r3, #1026 @ 0x402 8009c78: 61bb str r3, [r7, #24] 8009c7a: 69bb ldr r3, [r7, #24] 8009c7c: 881b ldrh r3, [r3, #0] 8009c7e: b29b uxth r3, r3 8009c80: f3c3 0309 ubfx r3, r3, #0, #10 8009c84: b29a uxth r2, r3 8009c86: 69bb ldr r3, [r7, #24] 8009c88: 801a strh r2, [r3, #0] 8009c8a: 69bb ldr r3, [r7, #24] 8009c8c: 881b ldrh r3, [r3, #0] 8009c8e: b29b uxth r3, r3 8009c90: ea6f 4343 mvn.w r3, r3, lsl #17 8009c94: ea6f 4353 mvn.w r3, r3, lsr #17 8009c98: b29a uxth r2, r3 8009c9a: 69bb ldr r3, [r7, #24] 8009c9c: 801a strh r2, [r3, #0] 8009c9e: e061 b.n 8009d64 8009ca0: 6cbb ldr r3, [r7, #72] @ 0x48 8009ca2: 785b ldrb r3, [r3, #1] 8009ca4: 2b01 cmp r3, #1 8009ca6: d15d bne.n 8009d64 8009ca8: 687b ldr r3, [r7, #4] 8009caa: 681b ldr r3, [r3, #0] 8009cac: 627b str r3, [r7, #36] @ 0x24 8009cae: 687b ldr r3, [r7, #4] 8009cb0: 681b ldr r3, [r3, #0] 8009cb2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009cb6: b29b uxth r3, r3 8009cb8: 461a mov r2, r3 8009cba: 6a7b ldr r3, [r7, #36] @ 0x24 8009cbc: 4413 add r3, r2 8009cbe: 627b str r3, [r7, #36] @ 0x24 8009cc0: 6cbb ldr r3, [r7, #72] @ 0x48 8009cc2: 781b ldrb r3, [r3, #0] 8009cc4: 00da lsls r2, r3, #3 8009cc6: 6a7b ldr r3, [r7, #36] @ 0x24 8009cc8: 4413 add r3, r2 8009cca: f203 4302 addw r3, r3, #1026 @ 0x402 8009cce: 623b str r3, [r7, #32] 8009cd0: 6a3b ldr r3, [r7, #32] 8009cd2: 2200 movs r2, #0 8009cd4: 801a strh r2, [r3, #0] 8009cd6: e045 b.n 8009d64 } else { PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 8009cd8: 687b ldr r3, [r7, #4] 8009cda: 681b ldr r3, [r3, #0] 8009cdc: 637b str r3, [r7, #52] @ 0x34 8009cde: 6cbb ldr r3, [r7, #72] @ 0x48 8009ce0: 785b ldrb r3, [r3, #1] 8009ce2: 2b00 cmp r3, #0 8009ce4: d126 bne.n 8009d34 8009ce6: 687b ldr r3, [r7, #4] 8009ce8: 681b ldr r3, [r3, #0] 8009cea: 62fb str r3, [r7, #44] @ 0x2c 8009cec: 687b ldr r3, [r7, #4] 8009cee: 681b ldr r3, [r3, #0] 8009cf0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009cf4: b29b uxth r3, r3 8009cf6: 461a mov r2, r3 8009cf8: 6afb ldr r3, [r7, #44] @ 0x2c 8009cfa: 4413 add r3, r2 8009cfc: 62fb str r3, [r7, #44] @ 0x2c 8009cfe: 6cbb ldr r3, [r7, #72] @ 0x48 8009d00: 781b ldrb r3, [r3, #0] 8009d02: 00da lsls r2, r3, #3 8009d04: 6afb ldr r3, [r7, #44] @ 0x2c 8009d06: 4413 add r3, r2 8009d08: f203 4306 addw r3, r3, #1030 @ 0x406 8009d0c: 62bb str r3, [r7, #40] @ 0x28 8009d0e: 6abb ldr r3, [r7, #40] @ 0x28 8009d10: 881b ldrh r3, [r3, #0] 8009d12: b29b uxth r3, r3 8009d14: f3c3 0309 ubfx r3, r3, #0, #10 8009d18: b29a uxth r2, r3 8009d1a: 6abb ldr r3, [r7, #40] @ 0x28 8009d1c: 801a strh r2, [r3, #0] 8009d1e: 6abb ldr r3, [r7, #40] @ 0x28 8009d20: 881b ldrh r3, [r3, #0] 8009d22: b29b uxth r3, r3 8009d24: ea6f 4343 mvn.w r3, r3, lsl #17 8009d28: ea6f 4353 mvn.w r3, r3, lsr #17 8009d2c: b29a uxth r2, r3 8009d2e: 6abb ldr r3, [r7, #40] @ 0x28 8009d30: 801a strh r2, [r3, #0] 8009d32: e017 b.n 8009d64 8009d34: 6cbb ldr r3, [r7, #72] @ 0x48 8009d36: 785b ldrb r3, [r3, #1] 8009d38: 2b01 cmp r3, #1 8009d3a: d113 bne.n 8009d64 8009d3c: 687b ldr r3, [r7, #4] 8009d3e: 681b ldr r3, [r3, #0] 8009d40: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009d44: b29b uxth r3, r3 8009d46: 461a mov r2, r3 8009d48: 6b7b ldr r3, [r7, #52] @ 0x34 8009d4a: 4413 add r3, r2 8009d4c: 637b str r3, [r7, #52] @ 0x34 8009d4e: 6cbb ldr r3, [r7, #72] @ 0x48 8009d50: 781b ldrb r3, [r3, #0] 8009d52: 00da lsls r2, r3, #3 8009d54: 6b7b ldr r3, [r7, #52] @ 0x34 8009d56: 4413 add r3, r2 8009d58: f203 4306 addw r3, r3, #1030 @ 0x406 8009d5c: 633b str r3, [r7, #48] @ 0x30 8009d5e: 6b3b ldr r3, [r7, #48] @ 0x30 8009d60: 2200 movs r2, #0 8009d62: 801a strh r2, [r3, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 8009d64: 6cbb ldr r3, [r7, #72] @ 0x48 8009d66: 781b ldrb r3, [r3, #0] 8009d68: 4619 mov r1, r3 8009d6a: 6878 ldr r0, [r7, #4] 8009d6c: f00e fb5f bl 801842e 8009d70: e04a b.n 8009e08 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) 8009d72: 8ffb ldrh r3, [r7, #62] @ 0x3e 8009d74: f403 7380 and.w r3, r3, #256 @ 0x100 8009d78: 2b00 cmp r3, #0 8009d7a: d13f bne.n 8009dfc { /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); 8009d7c: 687b ldr r3, [r7, #4] 8009d7e: 681b ldr r3, [r3, #0] 8009d80: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009d84: b29b uxth r3, r3 8009d86: 461a mov r2, r3 8009d88: 6cbb ldr r3, [r7, #72] @ 0x48 8009d8a: 781b ldrb r3, [r3, #0] 8009d8c: 00db lsls r3, r3, #3 8009d8e: 4413 add r3, r2 8009d90: 687a ldr r2, [r7, #4] 8009d92: 6812 ldr r2, [r2, #0] 8009d94: 4413 add r3, r2 8009d96: f203 4302 addw r3, r3, #1026 @ 0x402 8009d9a: 881b ldrh r3, [r3, #0] 8009d9c: f3c3 0309 ubfx r3, r3, #0, #10 8009da0: 877b strh r3, [r7, #58] @ 0x3a if (ep->xfer_len > TxPctSize) 8009da2: 6cbb ldr r3, [r7, #72] @ 0x48 8009da4: 699a ldr r2, [r3, #24] 8009da6: 8f7b ldrh r3, [r7, #58] @ 0x3a 8009da8: 429a cmp r2, r3 8009daa: d906 bls.n 8009dba { ep->xfer_len -= TxPctSize; 8009dac: 6cbb ldr r3, [r7, #72] @ 0x48 8009dae: 699a ldr r2, [r3, #24] 8009db0: 8f7b ldrh r3, [r7, #58] @ 0x3a 8009db2: 1ad2 subs r2, r2, r3 8009db4: 6cbb ldr r3, [r7, #72] @ 0x48 8009db6: 619a str r2, [r3, #24] 8009db8: e002 b.n 8009dc0 } else { ep->xfer_len = 0U; 8009dba: 6cbb ldr r3, [r7, #72] @ 0x48 8009dbc: 2200 movs r2, #0 8009dbe: 619a str r2, [r3, #24] } /* Zero Length Packet? */ if (ep->xfer_len == 0U) 8009dc0: 6cbb ldr r3, [r7, #72] @ 0x48 8009dc2: 699b ldr r3, [r3, #24] 8009dc4: 2b00 cmp r3, #0 8009dc6: d106 bne.n 8009dd6 { /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 8009dc8: 6cbb ldr r3, [r7, #72] @ 0x48 8009dca: 781b ldrb r3, [r3, #0] 8009dcc: 4619 mov r1, r3 8009dce: 6878 ldr r0, [r7, #4] 8009dd0: f00e fb2d bl 801842e 8009dd4: e018 b.n 8009e08 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Transfer is not yet Done */ ep->xfer_buff += TxPctSize; 8009dd6: 6cbb ldr r3, [r7, #72] @ 0x48 8009dd8: 695a ldr r2, [r3, #20] 8009dda: 8f7b ldrh r3, [r7, #58] @ 0x3a 8009ddc: 441a add r2, r3 8009dde: 6cbb ldr r3, [r7, #72] @ 0x48 8009de0: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 8009de2: 6cbb ldr r3, [r7, #72] @ 0x48 8009de4: 69da ldr r2, [r3, #28] 8009de6: 8f7b ldrh r3, [r7, #58] @ 0x3a 8009de8: 441a add r2, r3 8009dea: 6cbb ldr r3, [r7, #72] @ 0x48 8009dec: 61da str r2, [r3, #28] (void)USB_EPStartXfer(hpcd->Instance, ep); 8009dee: 687b ldr r3, [r7, #4] 8009df0: 681b ldr r3, [r3, #0] 8009df2: 6cb9 ldr r1, [r7, #72] @ 0x48 8009df4: 4618 mov r0, r3 8009df6: f005 fc0e bl 800f616 8009dfa: e005 b.n 8009e08 } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ else { (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); 8009dfc: 8ffb ldrh r3, [r7, #62] @ 0x3e 8009dfe: 461a mov r2, r3 8009e00: 6cb9 ldr r1, [r7, #72] @ 0x48 8009e02: 6878 ldr r0, [r7, #4] 8009e04: f000 f917 bl 800a036 while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) 8009e08: 687b ldr r3, [r7, #4] 8009e0a: 681b ldr r3, [r3, #0] 8009e0c: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8009e10: b29b uxth r3, r3 8009e12: b21b sxth r3, r3 8009e14: 2b00 cmp r3, #0 8009e16: f6ff ac82 blt.w 800971e } } } } return HAL_OK; 8009e1a: 2300 movs r3, #0 } 8009e1c: 4618 mov r0, r3 8009e1e: 3750 adds r7, #80 @ 0x50 8009e20: 46bd mov sp, r7 8009e22: bd80 pop {r7, pc} 08009e24 : * @param wEPVal Last snapshot of EPRx register value taken in ISR * @retval HAL status */ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal) { 8009e24: b580 push {r7, lr} 8009e26: b088 sub sp, #32 8009e28: af00 add r7, sp, #0 8009e2a: 60f8 str r0, [r7, #12] 8009e2c: 60b9 str r1, [r7, #8] 8009e2e: 4613 mov r3, r2 8009e30: 80fb strh r3, [r7, #6] uint16_t count; /* Manage Buffer0 OUT */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 8009e32: 88fb ldrh r3, [r7, #6] 8009e34: f403 4380 and.w r3, r3, #16384 @ 0x4000 8009e38: 2b00 cmp r3, #0 8009e3a: d07c beq.n 8009f36 { /* Get count of received Data on buffer0 */ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 8009e3c: 68fb ldr r3, [r7, #12] 8009e3e: 681b ldr r3, [r3, #0] 8009e40: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009e44: b29b uxth r3, r3 8009e46: 461a mov r2, r3 8009e48: 68bb ldr r3, [r7, #8] 8009e4a: 781b ldrb r3, [r3, #0] 8009e4c: 00db lsls r3, r3, #3 8009e4e: 4413 add r3, r2 8009e50: 68fa ldr r2, [r7, #12] 8009e52: 6812 ldr r2, [r2, #0] 8009e54: 4413 add r3, r2 8009e56: f203 4302 addw r3, r3, #1026 @ 0x402 8009e5a: 881b ldrh r3, [r3, #0] 8009e5c: f3c3 0309 ubfx r3, r3, #0, #10 8009e60: 837b strh r3, [r7, #26] if (ep->xfer_len >= count) 8009e62: 68bb ldr r3, [r7, #8] 8009e64: 699a ldr r2, [r3, #24] 8009e66: 8b7b ldrh r3, [r7, #26] 8009e68: 429a cmp r2, r3 8009e6a: d306 bcc.n 8009e7a { ep->xfer_len -= count; 8009e6c: 68bb ldr r3, [r7, #8] 8009e6e: 699a ldr r2, [r3, #24] 8009e70: 8b7b ldrh r3, [r7, #26] 8009e72: 1ad2 subs r2, r2, r3 8009e74: 68bb ldr r3, [r7, #8] 8009e76: 619a str r2, [r3, #24] 8009e78: e002 b.n 8009e80 } else { ep->xfer_len = 0U; 8009e7a: 68bb ldr r3, [r7, #8] 8009e7c: 2200 movs r2, #0 8009e7e: 619a str r2, [r3, #24] } if (ep->xfer_len == 0U) 8009e80: 68bb ldr r3, [r7, #8] 8009e82: 699b ldr r3, [r3, #24] 8009e84: 2b00 cmp r3, #0 8009e86: d123 bne.n 8009ed0 { /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); 8009e88: 68fb ldr r3, [r7, #12] 8009e8a: 681b ldr r3, [r3, #0] 8009e8c: 461a mov r2, r3 8009e8e: 68bb ldr r3, [r7, #8] 8009e90: 781b ldrb r3, [r3, #0] 8009e92: 009b lsls r3, r3, #2 8009e94: 4413 add r3, r2 8009e96: 881b ldrh r3, [r3, #0] 8009e98: b29b uxth r3, r3 8009e9a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8009e9e: f023 0370 bic.w r3, r3, #112 @ 0x70 8009ea2: 833b strh r3, [r7, #24] 8009ea4: 8b3b ldrh r3, [r7, #24] 8009ea6: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8009eaa: 833b strh r3, [r7, #24] 8009eac: 68fb ldr r3, [r7, #12] 8009eae: 681b ldr r3, [r3, #0] 8009eb0: 461a mov r2, r3 8009eb2: 68bb ldr r3, [r7, #8] 8009eb4: 781b ldrb r3, [r3, #0] 8009eb6: 009b lsls r3, r3, #2 8009eb8: 441a add r2, r3 8009eba: 8b3b ldrh r3, [r7, #24] 8009ebc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009ec0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009ec4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009ec8: f043 0380 orr.w r3, r3, #128 @ 0x80 8009ecc: b29b uxth r3, r3 8009ece: 8013 strh r3, [r2, #0] } /* Check if Buffer1 is in blocked state which requires to toggle */ if ((wEPVal & USB_EP_DTOG_TX) != 0U) 8009ed0: 88fb ldrh r3, [r7, #6] 8009ed2: f003 0340 and.w r3, r3, #64 @ 0x40 8009ed6: 2b00 cmp r3, #0 8009ed8: d01f beq.n 8009f1a { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 8009eda: 68fb ldr r3, [r7, #12] 8009edc: 681b ldr r3, [r3, #0] 8009ede: 461a mov r2, r3 8009ee0: 68bb ldr r3, [r7, #8] 8009ee2: 781b ldrb r3, [r3, #0] 8009ee4: 009b lsls r3, r3, #2 8009ee6: 4413 add r3, r2 8009ee8: 881b ldrh r3, [r3, #0] 8009eea: b29b uxth r3, r3 8009eec: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009ef0: f023 0370 bic.w r3, r3, #112 @ 0x70 8009ef4: 82fb strh r3, [r7, #22] 8009ef6: 68fb ldr r3, [r7, #12] 8009ef8: 681b ldr r3, [r3, #0] 8009efa: 461a mov r2, r3 8009efc: 68bb ldr r3, [r7, #8] 8009efe: 781b ldrb r3, [r3, #0] 8009f00: 009b lsls r3, r3, #2 8009f02: 441a add r2, r3 8009f04: 8afb ldrh r3, [r7, #22] 8009f06: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009f0a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009f0e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009f12: f043 03c0 orr.w r3, r3, #192 @ 0xc0 8009f16: b29b uxth r3, r3 8009f18: 8013 strh r3, [r2, #0] } if (count != 0U) 8009f1a: 8b7b ldrh r3, [r7, #26] 8009f1c: 2b00 cmp r3, #0 8009f1e: f000 8085 beq.w 800a02c { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); 8009f22: 68fb ldr r3, [r7, #12] 8009f24: 6818 ldr r0, [r3, #0] 8009f26: 68bb ldr r3, [r7, #8] 8009f28: 6959 ldr r1, [r3, #20] 8009f2a: 68bb ldr r3, [r7, #8] 8009f2c: 891a ldrh r2, [r3, #8] 8009f2e: 8b7b ldrh r3, [r7, #26] 8009f30: f006 fa98 bl 8010464 8009f34: e07a b.n 800a02c } /* Manage Buffer 1 DTOG_RX=0 */ else { /* Get count of received data */ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 8009f36: 68fb ldr r3, [r7, #12] 8009f38: 681b ldr r3, [r3, #0] 8009f3a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009f3e: b29b uxth r3, r3 8009f40: 461a mov r2, r3 8009f42: 68bb ldr r3, [r7, #8] 8009f44: 781b ldrb r3, [r3, #0] 8009f46: 00db lsls r3, r3, #3 8009f48: 4413 add r3, r2 8009f4a: 68fa ldr r2, [r7, #12] 8009f4c: 6812 ldr r2, [r2, #0] 8009f4e: 4413 add r3, r2 8009f50: f203 4306 addw r3, r3, #1030 @ 0x406 8009f54: 881b ldrh r3, [r3, #0] 8009f56: f3c3 0309 ubfx r3, r3, #0, #10 8009f5a: 837b strh r3, [r7, #26] if (ep->xfer_len >= count) 8009f5c: 68bb ldr r3, [r7, #8] 8009f5e: 699a ldr r2, [r3, #24] 8009f60: 8b7b ldrh r3, [r7, #26] 8009f62: 429a cmp r2, r3 8009f64: d306 bcc.n 8009f74 { ep->xfer_len -= count; 8009f66: 68bb ldr r3, [r7, #8] 8009f68: 699a ldr r2, [r3, #24] 8009f6a: 8b7b ldrh r3, [r7, #26] 8009f6c: 1ad2 subs r2, r2, r3 8009f6e: 68bb ldr r3, [r7, #8] 8009f70: 619a str r2, [r3, #24] 8009f72: e002 b.n 8009f7a } else { ep->xfer_len = 0U; 8009f74: 68bb ldr r3, [r7, #8] 8009f76: 2200 movs r2, #0 8009f78: 619a str r2, [r3, #24] } if (ep->xfer_len == 0U) 8009f7a: 68bb ldr r3, [r7, #8] 8009f7c: 699b ldr r3, [r3, #24] 8009f7e: 2b00 cmp r3, #0 8009f80: d123 bne.n 8009fca { /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); 8009f82: 68fb ldr r3, [r7, #12] 8009f84: 681b ldr r3, [r3, #0] 8009f86: 461a mov r2, r3 8009f88: 68bb ldr r3, [r7, #8] 8009f8a: 781b ldrb r3, [r3, #0] 8009f8c: 009b lsls r3, r3, #2 8009f8e: 4413 add r3, r2 8009f90: 881b ldrh r3, [r3, #0] 8009f92: b29b uxth r3, r3 8009f94: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8009f98: f023 0370 bic.w r3, r3, #112 @ 0x70 8009f9c: 83fb strh r3, [r7, #30] 8009f9e: 8bfb ldrh r3, [r7, #30] 8009fa0: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8009fa4: 83fb strh r3, [r7, #30] 8009fa6: 68fb ldr r3, [r7, #12] 8009fa8: 681b ldr r3, [r3, #0] 8009faa: 461a mov r2, r3 8009fac: 68bb ldr r3, [r7, #8] 8009fae: 781b ldrb r3, [r3, #0] 8009fb0: 009b lsls r3, r3, #2 8009fb2: 441a add r2, r3 8009fb4: 8bfb ldrh r3, [r7, #30] 8009fb6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009fba: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009fbe: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009fc2: f043 0380 orr.w r3, r3, #128 @ 0x80 8009fc6: b29b uxth r3, r3 8009fc8: 8013 strh r3, [r2, #0] } /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) 8009fca: 88fb ldrh r3, [r7, #6] 8009fcc: f003 0340 and.w r3, r3, #64 @ 0x40 8009fd0: 2b00 cmp r3, #0 8009fd2: d11f bne.n 800a014 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 8009fd4: 68fb ldr r3, [r7, #12] 8009fd6: 681b ldr r3, [r3, #0] 8009fd8: 461a mov r2, r3 8009fda: 68bb ldr r3, [r7, #8] 8009fdc: 781b ldrb r3, [r3, #0] 8009fde: 009b lsls r3, r3, #2 8009fe0: 4413 add r3, r2 8009fe2: 881b ldrh r3, [r3, #0] 8009fe4: b29b uxth r3, r3 8009fe6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009fea: f023 0370 bic.w r3, r3, #112 @ 0x70 8009fee: 83bb strh r3, [r7, #28] 8009ff0: 68fb ldr r3, [r7, #12] 8009ff2: 681b ldr r3, [r3, #0] 8009ff4: 461a mov r2, r3 8009ff6: 68bb ldr r3, [r7, #8] 8009ff8: 781b ldrb r3, [r3, #0] 8009ffa: 009b lsls r3, r3, #2 8009ffc: 441a add r2, r3 8009ffe: 8bbb ldrh r3, [r7, #28] 800a000: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a004: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a008: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a00c: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a010: b29b uxth r3, r3 800a012: 8013 strh r3, [r2, #0] } if (count != 0U) 800a014: 8b7b ldrh r3, [r7, #26] 800a016: 2b00 cmp r3, #0 800a018: d008 beq.n 800a02c { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); 800a01a: 68fb ldr r3, [r7, #12] 800a01c: 6818 ldr r0, [r3, #0] 800a01e: 68bb ldr r3, [r7, #8] 800a020: 6959 ldr r1, [r3, #20] 800a022: 68bb ldr r3, [r7, #8] 800a024: 895a ldrh r2, [r3, #10] 800a026: 8b7b ldrh r3, [r7, #26] 800a028: f006 fa1c bl 8010464 } } return count; 800a02c: 8b7b ldrh r3, [r7, #26] } 800a02e: 4618 mov r0, r3 800a030: 3720 adds r7, #32 800a032: 46bd mov sp, r7 800a034: bd80 pop {r7, pc} 0800a036 : * @param wEPVal Last snapshot of EPRx register value taken in ISR * @retval HAL status */ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal) { 800a036: b580 push {r7, lr} 800a038: b0a6 sub sp, #152 @ 0x98 800a03a: af00 add r7, sp, #0 800a03c: 60f8 str r0, [r7, #12] 800a03e: 60b9 str r1, [r7, #8] 800a040: 4613 mov r3, r2 800a042: 80fb strh r3, [r7, #6] uint32_t len; uint16_t TxPctSize; /* Data Buffer0 ACK received */ if ((wEPVal & USB_EP_DTOG_TX) != 0U) 800a044: 88fb ldrh r3, [r7, #6] 800a046: f003 0340 and.w r3, r3, #64 @ 0x40 800a04a: 2b00 cmp r3, #0 800a04c: f000 81f7 beq.w 800a43e { /* multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 800a050: 68fb ldr r3, [r7, #12] 800a052: 681b ldr r3, [r3, #0] 800a054: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a058: b29b uxth r3, r3 800a05a: 461a mov r2, r3 800a05c: 68bb ldr r3, [r7, #8] 800a05e: 781b ldrb r3, [r3, #0] 800a060: 00db lsls r3, r3, #3 800a062: 4413 add r3, r2 800a064: 68fa ldr r2, [r7, #12] 800a066: 6812 ldr r2, [r2, #0] 800a068: 4413 add r3, r2 800a06a: f203 4302 addw r3, r3, #1026 @ 0x402 800a06e: 881b ldrh r3, [r3, #0] 800a070: f3c3 0309 ubfx r3, r3, #0, #10 800a074: f8a7 3096 strh.w r3, [r7, #150] @ 0x96 if (ep->xfer_len > TxPctSize) 800a078: 68bb ldr r3, [r7, #8] 800a07a: 699a ldr r2, [r3, #24] 800a07c: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a080: 429a cmp r2, r3 800a082: d907 bls.n 800a094 { ep->xfer_len -= TxPctSize; 800a084: 68bb ldr r3, [r7, #8] 800a086: 699a ldr r2, [r3, #24] 800a088: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a08c: 1ad2 subs r2, r2, r3 800a08e: 68bb ldr r3, [r7, #8] 800a090: 619a str r2, [r3, #24] 800a092: e002 b.n 800a09a } else { ep->xfer_len = 0U; 800a094: 68bb ldr r3, [r7, #8] 800a096: 2200 movs r2, #0 800a098: 619a str r2, [r3, #24] } /* Transfer is completed */ if (ep->xfer_len == 0U) 800a09a: 68bb ldr r3, [r7, #8] 800a09c: 699b ldr r3, [r3, #24] 800a09e: 2b00 cmp r3, #0 800a0a0: f040 80e1 bne.w 800a266 { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800a0a4: 68bb ldr r3, [r7, #8] 800a0a6: 785b ldrb r3, [r3, #1] 800a0a8: 2b00 cmp r3, #0 800a0aa: d126 bne.n 800a0fa 800a0ac: 68fb ldr r3, [r7, #12] 800a0ae: 681b ldr r3, [r3, #0] 800a0b0: 633b str r3, [r7, #48] @ 0x30 800a0b2: 68fb ldr r3, [r7, #12] 800a0b4: 681b ldr r3, [r3, #0] 800a0b6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a0ba: b29b uxth r3, r3 800a0bc: 461a mov r2, r3 800a0be: 6b3b ldr r3, [r7, #48] @ 0x30 800a0c0: 4413 add r3, r2 800a0c2: 633b str r3, [r7, #48] @ 0x30 800a0c4: 68bb ldr r3, [r7, #8] 800a0c6: 781b ldrb r3, [r3, #0] 800a0c8: 00da lsls r2, r3, #3 800a0ca: 6b3b ldr r3, [r7, #48] @ 0x30 800a0cc: 4413 add r3, r2 800a0ce: f203 4302 addw r3, r3, #1026 @ 0x402 800a0d2: 62fb str r3, [r7, #44] @ 0x2c 800a0d4: 6afb ldr r3, [r7, #44] @ 0x2c 800a0d6: 881b ldrh r3, [r3, #0] 800a0d8: b29b uxth r3, r3 800a0da: f3c3 0309 ubfx r3, r3, #0, #10 800a0de: b29a uxth r2, r3 800a0e0: 6afb ldr r3, [r7, #44] @ 0x2c 800a0e2: 801a strh r2, [r3, #0] 800a0e4: 6afb ldr r3, [r7, #44] @ 0x2c 800a0e6: 881b ldrh r3, [r3, #0] 800a0e8: b29b uxth r3, r3 800a0ea: ea6f 4343 mvn.w r3, r3, lsl #17 800a0ee: ea6f 4353 mvn.w r3, r3, lsr #17 800a0f2: b29a uxth r2, r3 800a0f4: 6afb ldr r3, [r7, #44] @ 0x2c 800a0f6: 801a strh r2, [r3, #0] 800a0f8: e01a b.n 800a130 800a0fa: 68bb ldr r3, [r7, #8] 800a0fc: 785b ldrb r3, [r3, #1] 800a0fe: 2b01 cmp r3, #1 800a100: d116 bne.n 800a130 800a102: 68fb ldr r3, [r7, #12] 800a104: 681b ldr r3, [r3, #0] 800a106: 63bb str r3, [r7, #56] @ 0x38 800a108: 68fb ldr r3, [r7, #12] 800a10a: 681b ldr r3, [r3, #0] 800a10c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a110: b29b uxth r3, r3 800a112: 461a mov r2, r3 800a114: 6bbb ldr r3, [r7, #56] @ 0x38 800a116: 4413 add r3, r2 800a118: 63bb str r3, [r7, #56] @ 0x38 800a11a: 68bb ldr r3, [r7, #8] 800a11c: 781b ldrb r3, [r3, #0] 800a11e: 00da lsls r2, r3, #3 800a120: 6bbb ldr r3, [r7, #56] @ 0x38 800a122: 4413 add r3, r2 800a124: f203 4302 addw r3, r3, #1026 @ 0x402 800a128: 637b str r3, [r7, #52] @ 0x34 800a12a: 6b7b ldr r3, [r7, #52] @ 0x34 800a12c: 2200 movs r2, #0 800a12e: 801a strh r2, [r3, #0] PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800a130: 68fb ldr r3, [r7, #12] 800a132: 681b ldr r3, [r3, #0] 800a134: 62bb str r3, [r7, #40] @ 0x28 800a136: 68bb ldr r3, [r7, #8] 800a138: 785b ldrb r3, [r3, #1] 800a13a: 2b00 cmp r3, #0 800a13c: d126 bne.n 800a18c 800a13e: 68fb ldr r3, [r7, #12] 800a140: 681b ldr r3, [r3, #0] 800a142: 623b str r3, [r7, #32] 800a144: 68fb ldr r3, [r7, #12] 800a146: 681b ldr r3, [r3, #0] 800a148: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a14c: b29b uxth r3, r3 800a14e: 461a mov r2, r3 800a150: 6a3b ldr r3, [r7, #32] 800a152: 4413 add r3, r2 800a154: 623b str r3, [r7, #32] 800a156: 68bb ldr r3, [r7, #8] 800a158: 781b ldrb r3, [r3, #0] 800a15a: 00da lsls r2, r3, #3 800a15c: 6a3b ldr r3, [r7, #32] 800a15e: 4413 add r3, r2 800a160: f203 4306 addw r3, r3, #1030 @ 0x406 800a164: 61fb str r3, [r7, #28] 800a166: 69fb ldr r3, [r7, #28] 800a168: 881b ldrh r3, [r3, #0] 800a16a: b29b uxth r3, r3 800a16c: f3c3 0309 ubfx r3, r3, #0, #10 800a170: b29a uxth r2, r3 800a172: 69fb ldr r3, [r7, #28] 800a174: 801a strh r2, [r3, #0] 800a176: 69fb ldr r3, [r7, #28] 800a178: 881b ldrh r3, [r3, #0] 800a17a: b29b uxth r3, r3 800a17c: ea6f 4343 mvn.w r3, r3, lsl #17 800a180: ea6f 4353 mvn.w r3, r3, lsr #17 800a184: b29a uxth r2, r3 800a186: 69fb ldr r3, [r7, #28] 800a188: 801a strh r2, [r3, #0] 800a18a: e017 b.n 800a1bc 800a18c: 68bb ldr r3, [r7, #8] 800a18e: 785b ldrb r3, [r3, #1] 800a190: 2b01 cmp r3, #1 800a192: d113 bne.n 800a1bc 800a194: 68fb ldr r3, [r7, #12] 800a196: 681b ldr r3, [r3, #0] 800a198: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a19c: b29b uxth r3, r3 800a19e: 461a mov r2, r3 800a1a0: 6abb ldr r3, [r7, #40] @ 0x28 800a1a2: 4413 add r3, r2 800a1a4: 62bb str r3, [r7, #40] @ 0x28 800a1a6: 68bb ldr r3, [r7, #8] 800a1a8: 781b ldrb r3, [r3, #0] 800a1aa: 00da lsls r2, r3, #3 800a1ac: 6abb ldr r3, [r7, #40] @ 0x28 800a1ae: 4413 add r3, r2 800a1b0: f203 4306 addw r3, r3, #1030 @ 0x406 800a1b4: 627b str r3, [r7, #36] @ 0x24 800a1b6: 6a7b ldr r3, [r7, #36] @ 0x24 800a1b8: 2200 movs r2, #0 800a1ba: 801a strh r2, [r3, #0] if (ep->type == EP_TYPE_BULK) 800a1bc: 68bb ldr r3, [r7, #8] 800a1be: 78db ldrb r3, [r3, #3] 800a1c0: 2b02 cmp r3, #2 800a1c2: d123 bne.n 800a20c { /* Set Bulk endpoint in NAK state */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); 800a1c4: 68fb ldr r3, [r7, #12] 800a1c6: 681b ldr r3, [r3, #0] 800a1c8: 461a mov r2, r3 800a1ca: 68bb ldr r3, [r7, #8] 800a1cc: 781b ldrb r3, [r3, #0] 800a1ce: 009b lsls r3, r3, #2 800a1d0: 4413 add r3, r2 800a1d2: 881b ldrh r3, [r3, #0] 800a1d4: b29b uxth r3, r3 800a1d6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a1da: f023 0340 bic.w r3, r3, #64 @ 0x40 800a1de: 837b strh r3, [r7, #26] 800a1e0: 8b7b ldrh r3, [r7, #26] 800a1e2: f083 0320 eor.w r3, r3, #32 800a1e6: 837b strh r3, [r7, #26] 800a1e8: 68fb ldr r3, [r7, #12] 800a1ea: 681b ldr r3, [r3, #0] 800a1ec: 461a mov r2, r3 800a1ee: 68bb ldr r3, [r7, #8] 800a1f0: 781b ldrb r3, [r3, #0] 800a1f2: 009b lsls r3, r3, #2 800a1f4: 441a add r2, r3 800a1f6: 8b7b ldrh r3, [r7, #26] 800a1f8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a1fc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a200: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a204: f043 0380 orr.w r3, r3, #128 @ 0x80 800a208: b29b uxth r3, r3 800a20a: 8013 strh r3, [r2, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 800a20c: 68bb ldr r3, [r7, #8] 800a20e: 781b ldrb r3, [r3, #0] 800a210: 4619 mov r1, r3 800a212: 68f8 ldr r0, [r7, #12] 800a214: f00e f90b bl 801842e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 800a218: 88fb ldrh r3, [r7, #6] 800a21a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a21e: 2b00 cmp r3, #0 800a220: d01f beq.n 800a262 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 800a222: 68fb ldr r3, [r7, #12] 800a224: 681b ldr r3, [r3, #0] 800a226: 461a mov r2, r3 800a228: 68bb ldr r3, [r7, #8] 800a22a: 781b ldrb r3, [r3, #0] 800a22c: 009b lsls r3, r3, #2 800a22e: 4413 add r3, r2 800a230: 881b ldrh r3, [r3, #0] 800a232: b29b uxth r3, r3 800a234: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a238: f023 0370 bic.w r3, r3, #112 @ 0x70 800a23c: 833b strh r3, [r7, #24] 800a23e: 68fb ldr r3, [r7, #12] 800a240: 681b ldr r3, [r3, #0] 800a242: 461a mov r2, r3 800a244: 68bb ldr r3, [r7, #8] 800a246: 781b ldrb r3, [r3, #0] 800a248: 009b lsls r3, r3, #2 800a24a: 441a add r2, r3 800a24c: 8b3b ldrh r3, [r7, #24] 800a24e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a252: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a256: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a25a: f043 0380 orr.w r3, r3, #128 @ 0x80 800a25e: b29b uxth r3, r3 800a260: 8013 strh r3, [r2, #0] } return HAL_OK; 800a262: 2300 movs r3, #0 800a264: e31f b.n 800a8a6 } else /* Transfer is not yet Done */ { /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 800a266: 88fb ldrh r3, [r7, #6] 800a268: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a26c: 2b00 cmp r3, #0 800a26e: d021 beq.n 800a2b4 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 800a270: 68fb ldr r3, [r7, #12] 800a272: 681b ldr r3, [r3, #0] 800a274: 461a mov r2, r3 800a276: 68bb ldr r3, [r7, #8] 800a278: 781b ldrb r3, [r3, #0] 800a27a: 009b lsls r3, r3, #2 800a27c: 4413 add r3, r2 800a27e: 881b ldrh r3, [r3, #0] 800a280: b29b uxth r3, r3 800a282: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a286: f023 0370 bic.w r3, r3, #112 @ 0x70 800a28a: f8a7 304e strh.w r3, [r7, #78] @ 0x4e 800a28e: 68fb ldr r3, [r7, #12] 800a290: 681b ldr r3, [r3, #0] 800a292: 461a mov r2, r3 800a294: 68bb ldr r3, [r7, #8] 800a296: 781b ldrb r3, [r3, #0] 800a298: 009b lsls r3, r3, #2 800a29a: 441a add r2, r3 800a29c: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a2a0: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a2a4: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a2a8: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a2ac: f043 0380 orr.w r3, r3, #128 @ 0x80 800a2b0: b29b uxth r3, r3 800a2b2: 8013 strh r3, [r2, #0] } /* Still there is data to Fill in the next Buffer */ if (ep->xfer_fill_db == 1U) 800a2b4: 68bb ldr r3, [r7, #8] 800a2b6: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800a2ba: 2b01 cmp r3, #1 800a2bc: f040 82ca bne.w 800a854 { ep->xfer_buff += TxPctSize; 800a2c0: 68bb ldr r3, [r7, #8] 800a2c2: 695a ldr r2, [r3, #20] 800a2c4: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a2c8: 441a add r2, r3 800a2ca: 68bb ldr r3, [r7, #8] 800a2cc: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 800a2ce: 68bb ldr r3, [r7, #8] 800a2d0: 69da ldr r2, [r3, #28] 800a2d2: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a2d6: 441a add r2, r3 800a2d8: 68bb ldr r3, [r7, #8] 800a2da: 61da str r2, [r3, #28] /* Calculate the len of the new buffer to fill */ if (ep->xfer_len_db >= ep->maxpacket) 800a2dc: 68bb ldr r3, [r7, #8] 800a2de: 6a1a ldr r2, [r3, #32] 800a2e0: 68bb ldr r3, [r7, #8] 800a2e2: 691b ldr r3, [r3, #16] 800a2e4: 429a cmp r2, r3 800a2e6: d309 bcc.n 800a2fc { len = ep->maxpacket; 800a2e8: 68bb ldr r3, [r7, #8] 800a2ea: 691b ldr r3, [r3, #16] 800a2ec: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_len_db -= len; 800a2ee: 68bb ldr r3, [r7, #8] 800a2f0: 6a1a ldr r2, [r3, #32] 800a2f2: 6dbb ldr r3, [r7, #88] @ 0x58 800a2f4: 1ad2 subs r2, r2, r3 800a2f6: 68bb ldr r3, [r7, #8] 800a2f8: 621a str r2, [r3, #32] 800a2fa: e015 b.n 800a328 } else if (ep->xfer_len_db == 0U) 800a2fc: 68bb ldr r3, [r7, #8] 800a2fe: 6a1b ldr r3, [r3, #32] 800a300: 2b00 cmp r3, #0 800a302: d107 bne.n 800a314 { len = TxPctSize; 800a304: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a308: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_fill_db = 0U; 800a30a: 68bb ldr r3, [r7, #8] 800a30c: 2200 movs r2, #0 800a30e: f883 2024 strb.w r2, [r3, #36] @ 0x24 800a312: e009 b.n 800a328 } else { ep->xfer_fill_db = 0U; 800a314: 68bb ldr r3, [r7, #8] 800a316: 2200 movs r2, #0 800a318: f883 2024 strb.w r2, [r3, #36] @ 0x24 len = ep->xfer_len_db; 800a31c: 68bb ldr r3, [r7, #8] 800a31e: 6a1b ldr r3, [r3, #32] 800a320: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_len_db = 0U; 800a322: 68bb ldr r3, [r7, #8] 800a324: 2200 movs r2, #0 800a326: 621a str r2, [r3, #32] } /* Write remaining Data to Buffer */ /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); 800a328: 68bb ldr r3, [r7, #8] 800a32a: 785b ldrb r3, [r3, #1] 800a32c: 2b00 cmp r3, #0 800a32e: d15f bne.n 800a3f0 800a330: 68fb ldr r3, [r7, #12] 800a332: 681b ldr r3, [r3, #0] 800a334: 643b str r3, [r7, #64] @ 0x40 800a336: 68fb ldr r3, [r7, #12] 800a338: 681b ldr r3, [r3, #0] 800a33a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a33e: b29b uxth r3, r3 800a340: 461a mov r2, r3 800a342: 6c3b ldr r3, [r7, #64] @ 0x40 800a344: 4413 add r3, r2 800a346: 643b str r3, [r7, #64] @ 0x40 800a348: 68bb ldr r3, [r7, #8] 800a34a: 781b ldrb r3, [r3, #0] 800a34c: 00da lsls r2, r3, #3 800a34e: 6c3b ldr r3, [r7, #64] @ 0x40 800a350: 4413 add r3, r2 800a352: f203 4302 addw r3, r3, #1026 @ 0x402 800a356: 63fb str r3, [r7, #60] @ 0x3c 800a358: 6bfb ldr r3, [r7, #60] @ 0x3c 800a35a: 881b ldrh r3, [r3, #0] 800a35c: b29b uxth r3, r3 800a35e: f3c3 0309 ubfx r3, r3, #0, #10 800a362: b29a uxth r2, r3 800a364: 6bfb ldr r3, [r7, #60] @ 0x3c 800a366: 801a strh r2, [r3, #0] 800a368: 6dbb ldr r3, [r7, #88] @ 0x58 800a36a: 2b00 cmp r3, #0 800a36c: d10a bne.n 800a384 800a36e: 6bfb ldr r3, [r7, #60] @ 0x3c 800a370: 881b ldrh r3, [r3, #0] 800a372: b29b uxth r3, r3 800a374: ea6f 4343 mvn.w r3, r3, lsl #17 800a378: ea6f 4353 mvn.w r3, r3, lsr #17 800a37c: b29a uxth r2, r3 800a37e: 6bfb ldr r3, [r7, #60] @ 0x3c 800a380: 801a strh r2, [r3, #0] 800a382: e051 b.n 800a428 800a384: 6dbb ldr r3, [r7, #88] @ 0x58 800a386: 2b3e cmp r3, #62 @ 0x3e 800a388: d816 bhi.n 800a3b8 800a38a: 6dbb ldr r3, [r7, #88] @ 0x58 800a38c: 085b lsrs r3, r3, #1 800a38e: 653b str r3, [r7, #80] @ 0x50 800a390: 6dbb ldr r3, [r7, #88] @ 0x58 800a392: f003 0301 and.w r3, r3, #1 800a396: 2b00 cmp r3, #0 800a398: d002 beq.n 800a3a0 800a39a: 6d3b ldr r3, [r7, #80] @ 0x50 800a39c: 3301 adds r3, #1 800a39e: 653b str r3, [r7, #80] @ 0x50 800a3a0: 6bfb ldr r3, [r7, #60] @ 0x3c 800a3a2: 881b ldrh r3, [r3, #0] 800a3a4: b29a uxth r2, r3 800a3a6: 6d3b ldr r3, [r7, #80] @ 0x50 800a3a8: b29b uxth r3, r3 800a3aa: 029b lsls r3, r3, #10 800a3ac: b29b uxth r3, r3 800a3ae: 4313 orrs r3, r2 800a3b0: b29a uxth r2, r3 800a3b2: 6bfb ldr r3, [r7, #60] @ 0x3c 800a3b4: 801a strh r2, [r3, #0] 800a3b6: e037 b.n 800a428 800a3b8: 6dbb ldr r3, [r7, #88] @ 0x58 800a3ba: 095b lsrs r3, r3, #5 800a3bc: 653b str r3, [r7, #80] @ 0x50 800a3be: 6dbb ldr r3, [r7, #88] @ 0x58 800a3c0: f003 031f and.w r3, r3, #31 800a3c4: 2b00 cmp r3, #0 800a3c6: d102 bne.n 800a3ce 800a3c8: 6d3b ldr r3, [r7, #80] @ 0x50 800a3ca: 3b01 subs r3, #1 800a3cc: 653b str r3, [r7, #80] @ 0x50 800a3ce: 6bfb ldr r3, [r7, #60] @ 0x3c 800a3d0: 881b ldrh r3, [r3, #0] 800a3d2: b29a uxth r2, r3 800a3d4: 6d3b ldr r3, [r7, #80] @ 0x50 800a3d6: b29b uxth r3, r3 800a3d8: 029b lsls r3, r3, #10 800a3da: b29b uxth r3, r3 800a3dc: 4313 orrs r3, r2 800a3de: b29b uxth r3, r3 800a3e0: ea6f 4343 mvn.w r3, r3, lsl #17 800a3e4: ea6f 4353 mvn.w r3, r3, lsr #17 800a3e8: b29a uxth r2, r3 800a3ea: 6bfb ldr r3, [r7, #60] @ 0x3c 800a3ec: 801a strh r2, [r3, #0] 800a3ee: e01b b.n 800a428 800a3f0: 68bb ldr r3, [r7, #8] 800a3f2: 785b ldrb r3, [r3, #1] 800a3f4: 2b01 cmp r3, #1 800a3f6: d117 bne.n 800a428 800a3f8: 68fb ldr r3, [r7, #12] 800a3fa: 681b ldr r3, [r3, #0] 800a3fc: 64bb str r3, [r7, #72] @ 0x48 800a3fe: 68fb ldr r3, [r7, #12] 800a400: 681b ldr r3, [r3, #0] 800a402: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a406: b29b uxth r3, r3 800a408: 461a mov r2, r3 800a40a: 6cbb ldr r3, [r7, #72] @ 0x48 800a40c: 4413 add r3, r2 800a40e: 64bb str r3, [r7, #72] @ 0x48 800a410: 68bb ldr r3, [r7, #8] 800a412: 781b ldrb r3, [r3, #0] 800a414: 00da lsls r2, r3, #3 800a416: 6cbb ldr r3, [r7, #72] @ 0x48 800a418: 4413 add r3, r2 800a41a: f203 4302 addw r3, r3, #1026 @ 0x402 800a41e: 647b str r3, [r7, #68] @ 0x44 800a420: 6dbb ldr r3, [r7, #88] @ 0x58 800a422: b29a uxth r2, r3 800a424: 6c7b ldr r3, [r7, #68] @ 0x44 800a426: 801a strh r2, [r3, #0] /* Copy user buffer to USB PMA */ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); 800a428: 68fb ldr r3, [r7, #12] 800a42a: 6818 ldr r0, [r3, #0] 800a42c: 68bb ldr r3, [r7, #8] 800a42e: 6959 ldr r1, [r3, #20] 800a430: 68bb ldr r3, [r7, #8] 800a432: 891a ldrh r2, [r3, #8] 800a434: 6dbb ldr r3, [r7, #88] @ 0x58 800a436: b29b uxth r3, r3 800a438: f005 ffd1 bl 80103de 800a43c: e20a b.n 800a854 } } else /* Data Buffer1 ACK received */ { /* multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 800a43e: 68fb ldr r3, [r7, #12] 800a440: 681b ldr r3, [r3, #0] 800a442: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a446: b29b uxth r3, r3 800a448: 461a mov r2, r3 800a44a: 68bb ldr r3, [r7, #8] 800a44c: 781b ldrb r3, [r3, #0] 800a44e: 00db lsls r3, r3, #3 800a450: 4413 add r3, r2 800a452: 68fa ldr r2, [r7, #12] 800a454: 6812 ldr r2, [r2, #0] 800a456: 4413 add r3, r2 800a458: f203 4306 addw r3, r3, #1030 @ 0x406 800a45c: 881b ldrh r3, [r3, #0] 800a45e: f3c3 0309 ubfx r3, r3, #0, #10 800a462: f8a7 3096 strh.w r3, [r7, #150] @ 0x96 if (ep->xfer_len >= TxPctSize) 800a466: 68bb ldr r3, [r7, #8] 800a468: 699a ldr r2, [r3, #24] 800a46a: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a46e: 429a cmp r2, r3 800a470: d307 bcc.n 800a482 { ep->xfer_len -= TxPctSize; 800a472: 68bb ldr r3, [r7, #8] 800a474: 699a ldr r2, [r3, #24] 800a476: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a47a: 1ad2 subs r2, r2, r3 800a47c: 68bb ldr r3, [r7, #8] 800a47e: 619a str r2, [r3, #24] 800a480: e002 b.n 800a488 } else { ep->xfer_len = 0U; 800a482: 68bb ldr r3, [r7, #8] 800a484: 2200 movs r2, #0 800a486: 619a str r2, [r3, #24] } /* Transfer is completed */ if (ep->xfer_len == 0U) 800a488: 68bb ldr r3, [r7, #8] 800a48a: 699b ldr r3, [r3, #24] 800a48c: 2b00 cmp r3, #0 800a48e: f040 80f6 bne.w 800a67e { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800a492: 68bb ldr r3, [r7, #8] 800a494: 785b ldrb r3, [r3, #1] 800a496: 2b00 cmp r3, #0 800a498: d126 bne.n 800a4e8 800a49a: 68fb ldr r3, [r7, #12] 800a49c: 681b ldr r3, [r3, #0] 800a49e: 677b str r3, [r7, #116] @ 0x74 800a4a0: 68fb ldr r3, [r7, #12] 800a4a2: 681b ldr r3, [r3, #0] 800a4a4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a4a8: b29b uxth r3, r3 800a4aa: 461a mov r2, r3 800a4ac: 6f7b ldr r3, [r7, #116] @ 0x74 800a4ae: 4413 add r3, r2 800a4b0: 677b str r3, [r7, #116] @ 0x74 800a4b2: 68bb ldr r3, [r7, #8] 800a4b4: 781b ldrb r3, [r3, #0] 800a4b6: 00da lsls r2, r3, #3 800a4b8: 6f7b ldr r3, [r7, #116] @ 0x74 800a4ba: 4413 add r3, r2 800a4bc: f203 4302 addw r3, r3, #1026 @ 0x402 800a4c0: 673b str r3, [r7, #112] @ 0x70 800a4c2: 6f3b ldr r3, [r7, #112] @ 0x70 800a4c4: 881b ldrh r3, [r3, #0] 800a4c6: b29b uxth r3, r3 800a4c8: f3c3 0309 ubfx r3, r3, #0, #10 800a4cc: b29a uxth r2, r3 800a4ce: 6f3b ldr r3, [r7, #112] @ 0x70 800a4d0: 801a strh r2, [r3, #0] 800a4d2: 6f3b ldr r3, [r7, #112] @ 0x70 800a4d4: 881b ldrh r3, [r3, #0] 800a4d6: b29b uxth r3, r3 800a4d8: ea6f 4343 mvn.w r3, r3, lsl #17 800a4dc: ea6f 4353 mvn.w r3, r3, lsr #17 800a4e0: b29a uxth r2, r3 800a4e2: 6f3b ldr r3, [r7, #112] @ 0x70 800a4e4: 801a strh r2, [r3, #0] 800a4e6: e01a b.n 800a51e 800a4e8: 68bb ldr r3, [r7, #8] 800a4ea: 785b ldrb r3, [r3, #1] 800a4ec: 2b01 cmp r3, #1 800a4ee: d116 bne.n 800a51e 800a4f0: 68fb ldr r3, [r7, #12] 800a4f2: 681b ldr r3, [r3, #0] 800a4f4: 67fb str r3, [r7, #124] @ 0x7c 800a4f6: 68fb ldr r3, [r7, #12] 800a4f8: 681b ldr r3, [r3, #0] 800a4fa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a4fe: b29b uxth r3, r3 800a500: 461a mov r2, r3 800a502: 6ffb ldr r3, [r7, #124] @ 0x7c 800a504: 4413 add r3, r2 800a506: 67fb str r3, [r7, #124] @ 0x7c 800a508: 68bb ldr r3, [r7, #8] 800a50a: 781b ldrb r3, [r3, #0] 800a50c: 00da lsls r2, r3, #3 800a50e: 6ffb ldr r3, [r7, #124] @ 0x7c 800a510: 4413 add r3, r2 800a512: f203 4302 addw r3, r3, #1026 @ 0x402 800a516: 67bb str r3, [r7, #120] @ 0x78 800a518: 6fbb ldr r3, [r7, #120] @ 0x78 800a51a: 2200 movs r2, #0 800a51c: 801a strh r2, [r3, #0] PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800a51e: 68fb ldr r3, [r7, #12] 800a520: 681b ldr r3, [r3, #0] 800a522: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800a526: 68bb ldr r3, [r7, #8] 800a528: 785b ldrb r3, [r3, #1] 800a52a: 2b00 cmp r3, #0 800a52c: d12f bne.n 800a58e 800a52e: 68fb ldr r3, [r7, #12] 800a530: 681b ldr r3, [r3, #0] 800a532: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800a536: 68fb ldr r3, [r7, #12] 800a538: 681b ldr r3, [r3, #0] 800a53a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a53e: b29b uxth r3, r3 800a540: 461a mov r2, r3 800a542: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800a546: 4413 add r3, r2 800a548: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800a54c: 68bb ldr r3, [r7, #8] 800a54e: 781b ldrb r3, [r3, #0] 800a550: 00da lsls r2, r3, #3 800a552: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800a556: 4413 add r3, r2 800a558: f203 4306 addw r3, r3, #1030 @ 0x406 800a55c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800a560: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800a564: 881b ldrh r3, [r3, #0] 800a566: b29b uxth r3, r3 800a568: f3c3 0309 ubfx r3, r3, #0, #10 800a56c: b29a uxth r2, r3 800a56e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800a572: 801a strh r2, [r3, #0] 800a574: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800a578: 881b ldrh r3, [r3, #0] 800a57a: b29b uxth r3, r3 800a57c: ea6f 4343 mvn.w r3, r3, lsl #17 800a580: ea6f 4353 mvn.w r3, r3, lsr #17 800a584: b29a uxth r2, r3 800a586: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800a58a: 801a strh r2, [r3, #0] 800a58c: e01c b.n 800a5c8 800a58e: 68bb ldr r3, [r7, #8] 800a590: 785b ldrb r3, [r3, #1] 800a592: 2b01 cmp r3, #1 800a594: d118 bne.n 800a5c8 800a596: 68fb ldr r3, [r7, #12] 800a598: 681b ldr r3, [r3, #0] 800a59a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a59e: b29b uxth r3, r3 800a5a0: 461a mov r2, r3 800a5a2: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800a5a6: 4413 add r3, r2 800a5a8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800a5ac: 68bb ldr r3, [r7, #8] 800a5ae: 781b ldrb r3, [r3, #0] 800a5b0: 00da lsls r2, r3, #3 800a5b2: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800a5b6: 4413 add r3, r2 800a5b8: f203 4306 addw r3, r3, #1030 @ 0x406 800a5bc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800a5c0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800a5c4: 2200 movs r2, #0 800a5c6: 801a strh r2, [r3, #0] if (ep->type == EP_TYPE_BULK) 800a5c8: 68bb ldr r3, [r7, #8] 800a5ca: 78db ldrb r3, [r3, #3] 800a5cc: 2b02 cmp r3, #2 800a5ce: d127 bne.n 800a620 { /* Set Bulk endpoint in NAK state */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); 800a5d0: 68fb ldr r3, [r7, #12] 800a5d2: 681b ldr r3, [r3, #0] 800a5d4: 461a mov r2, r3 800a5d6: 68bb ldr r3, [r7, #8] 800a5d8: 781b ldrb r3, [r3, #0] 800a5da: 009b lsls r3, r3, #2 800a5dc: 4413 add r3, r2 800a5de: 881b ldrh r3, [r3, #0] 800a5e0: b29b uxth r3, r3 800a5e2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a5e6: f023 0340 bic.w r3, r3, #64 @ 0x40 800a5ea: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 800a5ee: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800a5f2: f083 0320 eor.w r3, r3, #32 800a5f6: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 800a5fa: 68fb ldr r3, [r7, #12] 800a5fc: 681b ldr r3, [r3, #0] 800a5fe: 461a mov r2, r3 800a600: 68bb ldr r3, [r7, #8] 800a602: 781b ldrb r3, [r3, #0] 800a604: 009b lsls r3, r3, #2 800a606: 441a add r2, r3 800a608: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800a60c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a610: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a614: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a618: f043 0380 orr.w r3, r3, #128 @ 0x80 800a61c: b29b uxth r3, r3 800a61e: 8013 strh r3, [r2, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 800a620: 68bb ldr r3, [r7, #8] 800a622: 781b ldrb r3, [r3, #0] 800a624: 4619 mov r1, r3 800a626: 68f8 ldr r0, [r7, #12] 800a628: f00d ff01 bl 801842e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* need to Free USB Buff */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) 800a62c: 88fb ldrh r3, [r7, #6] 800a62e: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a632: 2b00 cmp r3, #0 800a634: d121 bne.n 800a67a { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 800a636: 68fb ldr r3, [r7, #12] 800a638: 681b ldr r3, [r3, #0] 800a63a: 461a mov r2, r3 800a63c: 68bb ldr r3, [r7, #8] 800a63e: 781b ldrb r3, [r3, #0] 800a640: 009b lsls r3, r3, #2 800a642: 4413 add r3, r2 800a644: 881b ldrh r3, [r3, #0] 800a646: b29b uxth r3, r3 800a648: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a64c: f023 0370 bic.w r3, r3, #112 @ 0x70 800a650: f8a7 3092 strh.w r3, [r7, #146] @ 0x92 800a654: 68fb ldr r3, [r7, #12] 800a656: 681b ldr r3, [r3, #0] 800a658: 461a mov r2, r3 800a65a: 68bb ldr r3, [r7, #8] 800a65c: 781b ldrb r3, [r3, #0] 800a65e: 009b lsls r3, r3, #2 800a660: 441a add r2, r3 800a662: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 800a666: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a66a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a66e: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a672: f043 0380 orr.w r3, r3, #128 @ 0x80 800a676: b29b uxth r3, r3 800a678: 8013 strh r3, [r2, #0] } return HAL_OK; 800a67a: 2300 movs r3, #0 800a67c: e113 b.n 800a8a6 } else /* Transfer is not yet Done */ { /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) 800a67e: 88fb ldrh r3, [r7, #6] 800a680: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a684: 2b00 cmp r3, #0 800a686: d121 bne.n 800a6cc { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 800a688: 68fb ldr r3, [r7, #12] 800a68a: 681b ldr r3, [r3, #0] 800a68c: 461a mov r2, r3 800a68e: 68bb ldr r3, [r7, #8] 800a690: 781b ldrb r3, [r3, #0] 800a692: 009b lsls r3, r3, #2 800a694: 4413 add r3, r2 800a696: 881b ldrh r3, [r3, #0] 800a698: b29b uxth r3, r3 800a69a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a69e: f023 0370 bic.w r3, r3, #112 @ 0x70 800a6a2: f8a7 3056 strh.w r3, [r7, #86] @ 0x56 800a6a6: 68fb ldr r3, [r7, #12] 800a6a8: 681b ldr r3, [r3, #0] 800a6aa: 461a mov r2, r3 800a6ac: 68bb ldr r3, [r7, #8] 800a6ae: 781b ldrb r3, [r3, #0] 800a6b0: 009b lsls r3, r3, #2 800a6b2: 441a add r2, r3 800a6b4: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56 800a6b8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a6bc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a6c0: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a6c4: f043 0380 orr.w r3, r3, #128 @ 0x80 800a6c8: b29b uxth r3, r3 800a6ca: 8013 strh r3, [r2, #0] } /* Still there is data to Fill in the next Buffer */ if (ep->xfer_fill_db == 1U) 800a6cc: 68bb ldr r3, [r7, #8] 800a6ce: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800a6d2: 2b01 cmp r3, #1 800a6d4: f040 80be bne.w 800a854 { ep->xfer_buff += TxPctSize; 800a6d8: 68bb ldr r3, [r7, #8] 800a6da: 695a ldr r2, [r3, #20] 800a6dc: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a6e0: 441a add r2, r3 800a6e2: 68bb ldr r3, [r7, #8] 800a6e4: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 800a6e6: 68bb ldr r3, [r7, #8] 800a6e8: 69da ldr r2, [r3, #28] 800a6ea: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a6ee: 441a add r2, r3 800a6f0: 68bb ldr r3, [r7, #8] 800a6f2: 61da str r2, [r3, #28] /* Calculate the len of the new buffer to fill */ if (ep->xfer_len_db >= ep->maxpacket) 800a6f4: 68bb ldr r3, [r7, #8] 800a6f6: 6a1a ldr r2, [r3, #32] 800a6f8: 68bb ldr r3, [r7, #8] 800a6fa: 691b ldr r3, [r3, #16] 800a6fc: 429a cmp r2, r3 800a6fe: d309 bcc.n 800a714 { len = ep->maxpacket; 800a700: 68bb ldr r3, [r7, #8] 800a702: 691b ldr r3, [r3, #16] 800a704: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_len_db -= len; 800a706: 68bb ldr r3, [r7, #8] 800a708: 6a1a ldr r2, [r3, #32] 800a70a: 6dbb ldr r3, [r7, #88] @ 0x58 800a70c: 1ad2 subs r2, r2, r3 800a70e: 68bb ldr r3, [r7, #8] 800a710: 621a str r2, [r3, #32] 800a712: e015 b.n 800a740 } else if (ep->xfer_len_db == 0U) 800a714: 68bb ldr r3, [r7, #8] 800a716: 6a1b ldr r3, [r3, #32] 800a718: 2b00 cmp r3, #0 800a71a: d107 bne.n 800a72c { len = TxPctSize; 800a71c: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a720: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_fill_db = 0U; 800a722: 68bb ldr r3, [r7, #8] 800a724: 2200 movs r2, #0 800a726: f883 2024 strb.w r2, [r3, #36] @ 0x24 800a72a: e009 b.n 800a740 } else { len = ep->xfer_len_db; 800a72c: 68bb ldr r3, [r7, #8] 800a72e: 6a1b ldr r3, [r3, #32] 800a730: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_len_db = 0U; 800a732: 68bb ldr r3, [r7, #8] 800a734: 2200 movs r2, #0 800a736: 621a str r2, [r3, #32] ep->xfer_fill_db = 0; 800a738: 68bb ldr r3, [r7, #8] 800a73a: 2200 movs r2, #0 800a73c: f883 2024 strb.w r2, [r3, #36] @ 0x24 } /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); 800a740: 68fb ldr r3, [r7, #12] 800a742: 681b ldr r3, [r3, #0] 800a744: 65fb str r3, [r7, #92] @ 0x5c 800a746: 68bb ldr r3, [r7, #8] 800a748: 785b ldrb r3, [r3, #1] 800a74a: 2b00 cmp r3, #0 800a74c: d15f bne.n 800a80e 800a74e: 68fb ldr r3, [r7, #12] 800a750: 681b ldr r3, [r3, #0] 800a752: 66bb str r3, [r7, #104] @ 0x68 800a754: 68fb ldr r3, [r7, #12] 800a756: 681b ldr r3, [r3, #0] 800a758: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a75c: b29b uxth r3, r3 800a75e: 461a mov r2, r3 800a760: 6ebb ldr r3, [r7, #104] @ 0x68 800a762: 4413 add r3, r2 800a764: 66bb str r3, [r7, #104] @ 0x68 800a766: 68bb ldr r3, [r7, #8] 800a768: 781b ldrb r3, [r3, #0] 800a76a: 00da lsls r2, r3, #3 800a76c: 6ebb ldr r3, [r7, #104] @ 0x68 800a76e: 4413 add r3, r2 800a770: f203 4306 addw r3, r3, #1030 @ 0x406 800a774: 667b str r3, [r7, #100] @ 0x64 800a776: 6e7b ldr r3, [r7, #100] @ 0x64 800a778: 881b ldrh r3, [r3, #0] 800a77a: b29b uxth r3, r3 800a77c: f3c3 0309 ubfx r3, r3, #0, #10 800a780: b29a uxth r2, r3 800a782: 6e7b ldr r3, [r7, #100] @ 0x64 800a784: 801a strh r2, [r3, #0] 800a786: 6dbb ldr r3, [r7, #88] @ 0x58 800a788: 2b00 cmp r3, #0 800a78a: d10a bne.n 800a7a2 800a78c: 6e7b ldr r3, [r7, #100] @ 0x64 800a78e: 881b ldrh r3, [r3, #0] 800a790: b29b uxth r3, r3 800a792: ea6f 4343 mvn.w r3, r3, lsl #17 800a796: ea6f 4353 mvn.w r3, r3, lsr #17 800a79a: b29a uxth r2, r3 800a79c: 6e7b ldr r3, [r7, #100] @ 0x64 800a79e: 801a strh r2, [r3, #0] 800a7a0: e04e b.n 800a840 800a7a2: 6dbb ldr r3, [r7, #88] @ 0x58 800a7a4: 2b3e cmp r3, #62 @ 0x3e 800a7a6: d816 bhi.n 800a7d6 800a7a8: 6dbb ldr r3, [r7, #88] @ 0x58 800a7aa: 085b lsrs r3, r3, #1 800a7ac: 663b str r3, [r7, #96] @ 0x60 800a7ae: 6dbb ldr r3, [r7, #88] @ 0x58 800a7b0: f003 0301 and.w r3, r3, #1 800a7b4: 2b00 cmp r3, #0 800a7b6: d002 beq.n 800a7be 800a7b8: 6e3b ldr r3, [r7, #96] @ 0x60 800a7ba: 3301 adds r3, #1 800a7bc: 663b str r3, [r7, #96] @ 0x60 800a7be: 6e7b ldr r3, [r7, #100] @ 0x64 800a7c0: 881b ldrh r3, [r3, #0] 800a7c2: b29a uxth r2, r3 800a7c4: 6e3b ldr r3, [r7, #96] @ 0x60 800a7c6: b29b uxth r3, r3 800a7c8: 029b lsls r3, r3, #10 800a7ca: b29b uxth r3, r3 800a7cc: 4313 orrs r3, r2 800a7ce: b29a uxth r2, r3 800a7d0: 6e7b ldr r3, [r7, #100] @ 0x64 800a7d2: 801a strh r2, [r3, #0] 800a7d4: e034 b.n 800a840 800a7d6: 6dbb ldr r3, [r7, #88] @ 0x58 800a7d8: 095b lsrs r3, r3, #5 800a7da: 663b str r3, [r7, #96] @ 0x60 800a7dc: 6dbb ldr r3, [r7, #88] @ 0x58 800a7de: f003 031f and.w r3, r3, #31 800a7e2: 2b00 cmp r3, #0 800a7e4: d102 bne.n 800a7ec 800a7e6: 6e3b ldr r3, [r7, #96] @ 0x60 800a7e8: 3b01 subs r3, #1 800a7ea: 663b str r3, [r7, #96] @ 0x60 800a7ec: 6e7b ldr r3, [r7, #100] @ 0x64 800a7ee: 881b ldrh r3, [r3, #0] 800a7f0: b29a uxth r2, r3 800a7f2: 6e3b ldr r3, [r7, #96] @ 0x60 800a7f4: b29b uxth r3, r3 800a7f6: 029b lsls r3, r3, #10 800a7f8: b29b uxth r3, r3 800a7fa: 4313 orrs r3, r2 800a7fc: b29b uxth r3, r3 800a7fe: ea6f 4343 mvn.w r3, r3, lsl #17 800a802: ea6f 4353 mvn.w r3, r3, lsr #17 800a806: b29a uxth r2, r3 800a808: 6e7b ldr r3, [r7, #100] @ 0x64 800a80a: 801a strh r2, [r3, #0] 800a80c: e018 b.n 800a840 800a80e: 68bb ldr r3, [r7, #8] 800a810: 785b ldrb r3, [r3, #1] 800a812: 2b01 cmp r3, #1 800a814: d114 bne.n 800a840 800a816: 68fb ldr r3, [r7, #12] 800a818: 681b ldr r3, [r3, #0] 800a81a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a81e: b29b uxth r3, r3 800a820: 461a mov r2, r3 800a822: 6dfb ldr r3, [r7, #92] @ 0x5c 800a824: 4413 add r3, r2 800a826: 65fb str r3, [r7, #92] @ 0x5c 800a828: 68bb ldr r3, [r7, #8] 800a82a: 781b ldrb r3, [r3, #0] 800a82c: 00da lsls r2, r3, #3 800a82e: 6dfb ldr r3, [r7, #92] @ 0x5c 800a830: 4413 add r3, r2 800a832: f203 4306 addw r3, r3, #1030 @ 0x406 800a836: 66fb str r3, [r7, #108] @ 0x6c 800a838: 6dbb ldr r3, [r7, #88] @ 0x58 800a83a: b29a uxth r2, r3 800a83c: 6efb ldr r3, [r7, #108] @ 0x6c 800a83e: 801a strh r2, [r3, #0] /* Copy the user buffer to USB PMA */ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); 800a840: 68fb ldr r3, [r7, #12] 800a842: 6818 ldr r0, [r3, #0] 800a844: 68bb ldr r3, [r7, #8] 800a846: 6959 ldr r1, [r3, #20] 800a848: 68bb ldr r3, [r7, #8] 800a84a: 895a ldrh r2, [r3, #10] 800a84c: 6dbb ldr r3, [r7, #88] @ 0x58 800a84e: b29b uxth r3, r3 800a850: f005 fdc5 bl 80103de } } } /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); 800a854: 68fb ldr r3, [r7, #12] 800a856: 681b ldr r3, [r3, #0] 800a858: 461a mov r2, r3 800a85a: 68bb ldr r3, [r7, #8] 800a85c: 781b ldrb r3, [r3, #0] 800a85e: 009b lsls r3, r3, #2 800a860: 4413 add r3, r2 800a862: 881b ldrh r3, [r3, #0] 800a864: b29b uxth r3, r3 800a866: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a86a: f023 0340 bic.w r3, r3, #64 @ 0x40 800a86e: 82fb strh r3, [r7, #22] 800a870: 8afb ldrh r3, [r7, #22] 800a872: f083 0310 eor.w r3, r3, #16 800a876: 82fb strh r3, [r7, #22] 800a878: 8afb ldrh r3, [r7, #22] 800a87a: f083 0320 eor.w r3, r3, #32 800a87e: 82fb strh r3, [r7, #22] 800a880: 68fb ldr r3, [r7, #12] 800a882: 681b ldr r3, [r3, #0] 800a884: 461a mov r2, r3 800a886: 68bb ldr r3, [r7, #8] 800a888: 781b ldrb r3, [r3, #0] 800a88a: 009b lsls r3, r3, #2 800a88c: 441a add r2, r3 800a88e: 8afb ldrh r3, [r7, #22] 800a890: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a894: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a898: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a89c: f043 0380 orr.w r3, r3, #128 @ 0x80 800a8a0: b29b uxth r3, r3 800a8a2: 8013 strh r3, [r2, #0] return HAL_OK; 800a8a4: 2300 movs r3, #0 } 800a8a6: 4618 mov r0, r3 800a8a8: 3798 adds r7, #152 @ 0x98 800a8aa: 46bd mov sp, r7 800a8ac: bd80 pop {r7, pc} 0800a8ae : * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress) { 800a8ae: b480 push {r7} 800a8b0: b087 sub sp, #28 800a8b2: af00 add r7, sp, #0 800a8b4: 60f8 str r0, [r7, #12] 800a8b6: 607b str r3, [r7, #4] 800a8b8: 460b mov r3, r1 800a8ba: 817b strh r3, [r7, #10] 800a8bc: 4613 mov r3, r2 800a8be: 813b strh r3, [r7, #8] PCD_EPTypeDef *ep; /* Initialize ep structure */ if ((0x80U & ep_addr) == 0x80U) 800a8c0: 897b ldrh r3, [r7, #10] 800a8c2: f003 0380 and.w r3, r3, #128 @ 0x80 800a8c6: b29b uxth r3, r3 800a8c8: 2b00 cmp r3, #0 800a8ca: d00b beq.n 800a8e4 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800a8cc: 897b ldrh r3, [r7, #10] 800a8ce: f003 0207 and.w r2, r3, #7 800a8d2: 4613 mov r3, r2 800a8d4: 009b lsls r3, r3, #2 800a8d6: 4413 add r3, r2 800a8d8: 00db lsls r3, r3, #3 800a8da: 3310 adds r3, #16 800a8dc: 68fa ldr r2, [r7, #12] 800a8de: 4413 add r3, r2 800a8e0: 617b str r3, [r7, #20] 800a8e2: e009 b.n 800a8f8 } else { ep = &hpcd->OUT_ep[ep_addr]; 800a8e4: 897a ldrh r2, [r7, #10] 800a8e6: 4613 mov r3, r2 800a8e8: 009b lsls r3, r3, #2 800a8ea: 4413 add r3, r2 800a8ec: 00db lsls r3, r3, #3 800a8ee: f503 73a8 add.w r3, r3, #336 @ 0x150 800a8f2: 68fa ldr r2, [r7, #12] 800a8f4: 4413 add r3, r2 800a8f6: 617b str r3, [r7, #20] } /* Here we check if the endpoint is single or double Buffer*/ if (ep_kind == PCD_SNG_BUF) 800a8f8: 893b ldrh r3, [r7, #8] 800a8fa: 2b00 cmp r3, #0 800a8fc: d107 bne.n 800a90e { /* Single Buffer */ ep->doublebuffer = 0U; 800a8fe: 697b ldr r3, [r7, #20] 800a900: 2200 movs r2, #0 800a902: 731a strb r2, [r3, #12] /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; 800a904: 687b ldr r3, [r7, #4] 800a906: b29a uxth r2, r3 800a908: 697b ldr r3, [r7, #20] 800a90a: 80da strh r2, [r3, #6] 800a90c: e00b b.n 800a926 } #if (USE_USB_DOUBLE_BUFFER == 1U) else /* USB_DBL_BUF */ { /* Double Buffer Endpoint */ ep->doublebuffer = 1U; 800a90e: 697b ldr r3, [r7, #20] 800a910: 2201 movs r2, #1 800a912: 731a strb r2, [r3, #12] /* Configure the PMA */ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); 800a914: 687b ldr r3, [r7, #4] 800a916: b29a uxth r2, r3 800a918: 697b ldr r3, [r7, #20] 800a91a: 811a strh r2, [r3, #8] ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); 800a91c: 687b ldr r3, [r7, #4] 800a91e: 0c1b lsrs r3, r3, #16 800a920: b29a uxth r2, r3 800a922: 697b ldr r3, [r7, #20] 800a924: 815a strh r2, [r3, #10] } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; 800a926: 2300 movs r3, #0 } 800a928: 4618 mov r0, r3 800a92a: 371c adds r7, #28 800a92c: 46bd mov sp, r7 800a92e: f85d 7b04 ldr.w r7, [sp], #4 800a932: 4770 bx lr 0800a934 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 800a934: b480 push {r7} 800a936: b085 sub sp, #20 800a938: af00 add r7, sp, #0 800a93a: 6078 str r0, [r7, #4] USB_TypeDef *USBx = hpcd->Instance; 800a93c: 687b ldr r3, [r7, #4] 800a93e: 681b ldr r3, [r3, #0] 800a940: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 800a942: 687b ldr r3, [r7, #4] 800a944: 2201 movs r2, #1 800a946: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 hpcd->LPM_State = LPM_L0; 800a94a: 687b ldr r3, [r7, #4] 800a94c: 2200 movs r2, #0 800a94e: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8 USBx->LPMCSR |= USB_LPMCSR_LMPEN; 800a952: 68fb ldr r3, [r7, #12] 800a954: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 800a958: b29b uxth r3, r3 800a95a: f043 0301 orr.w r3, r3, #1 800a95e: b29a uxth r2, r3 800a960: 68fb ldr r3, [r7, #12] 800a962: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 USBx->LPMCSR |= USB_LPMCSR_LPMACK; 800a966: 68fb ldr r3, [r7, #12] 800a968: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 800a96c: b29b uxth r3, r3 800a96e: f043 0302 orr.w r3, r3, #2 800a972: b29a uxth r2, r3 800a974: 68fb ldr r3, [r7, #12] 800a976: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 return HAL_OK; 800a97a: 2300 movs r3, #0 } 800a97c: 4618 mov r0, r3 800a97e: 3714 adds r7, #20 800a980: 46bd mov sp, r7 800a982: f85d 7b04 ldr.w r7, [sp], #4 800a986: 4770 bx lr 0800a988 : * @note LSEON bit that switches on and off the LSE crystal belongs as well to the * back-up domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 800a988: b480 push {r7} 800a98a: af00 add r7, sp, #0 SET_BIT(PWR->CR1, PWR_CR1_DBP); 800a98c: 4b05 ldr r3, [pc, #20] @ (800a9a4 ) 800a98e: 681b ldr r3, [r3, #0] 800a990: 4a04 ldr r2, [pc, #16] @ (800a9a4 ) 800a992: f443 7380 orr.w r3, r3, #256 @ 0x100 800a996: 6013 str r3, [r2, #0] } 800a998: bf00 nop 800a99a: 46bd mov sp, r7 800a99c: f85d 7b04 ldr.w r7, [sp], #4 800a9a0: 4770 bx lr 800a9a2: bf00 nop 800a9a4: 58000400 .word 0x58000400 0800a9a8 : /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) */ uint32_t HAL_PWREx_GetVoltageRange(void) { 800a9a8: b480 push {r7} 800a9aa: af00 add r7, sp, #0 return (PWR->CR1 & PWR_CR1_VOS); 800a9ac: 4b04 ldr r3, [pc, #16] @ (800a9c0 ) 800a9ae: 681b ldr r3, [r3, #0] 800a9b0: f403 63c0 and.w r3, r3, #1536 @ 0x600 } 800a9b4: 4618 mov r0, r3 800a9b6: 46bd mov sp, r7 800a9b8: f85d 7b04 ldr.w r7, [sp], #4 800a9bc: 4770 bx lr 800a9be: bf00 nop 800a9c0: 58000400 .word 0x58000400 0800a9c4 : * @brief Enable VDDUSB supply. * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. * @retval None */ void HAL_PWREx_EnableVddUSB(void) { 800a9c4: b480 push {r7} 800a9c6: af00 add r7, sp, #0 SET_BIT(PWR->CR2, PWR_CR2_USV); 800a9c8: 4b05 ldr r3, [pc, #20] @ (800a9e0 ) 800a9ca: 685b ldr r3, [r3, #4] 800a9cc: 4a04 ldr r2, [pc, #16] @ (800a9e0 ) 800a9ce: f443 6380 orr.w r3, r3, #1024 @ 0x400 800a9d2: 6053 str r3, [r2, #4] } 800a9d4: bf00 nop 800a9d6: 46bd mov sp, r7 800a9d8: f85d 7b04 ldr.w r7, [sp], #4 800a9dc: 4770 bx lr 800a9de: bf00 nop 800a9e0: 58000400 .word 0x58000400 0800a9e4 : { 800a9e4: b480 push {r7} 800a9e6: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); 800a9e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800a9ec: 681b ldr r3, [r3, #0] 800a9ee: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800a9f2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800a9f6: d101 bne.n 800a9fc 800a9f8: 2301 movs r3, #1 800a9fa: e000 b.n 800a9fe 800a9fc: 2300 movs r3, #0 } 800a9fe: 4618 mov r0, r3 800aa00: 46bd mov sp, r7 800aa02: f85d 7b04 ldr.w r7, [sp], #4 800aa06: 4770 bx lr 0800aa08 : { 800aa08: b480 push {r7} 800aa0a: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSEON); 800aa0c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aa10: 681b ldr r3, [r3, #0] 800aa12: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800aa16: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800aa1a: 6013 str r3, [r2, #0] } 800aa1c: bf00 nop 800aa1e: 46bd mov sp, r7 800aa20: f85d 7b04 ldr.w r7, [sp], #4 800aa24: 4770 bx lr 0800aa26 : { 800aa26: b480 push {r7} 800aa28: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 800aa2a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aa2e: 681b ldr r3, [r3, #0] 800aa30: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800aa34: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800aa38: 6013 str r3, [r2, #0] } 800aa3a: bf00 nop 800aa3c: 46bd mov sp, r7 800aa3e: f85d 7b04 ldr.w r7, [sp], #4 800aa42: 4770 bx lr 0800aa44 : { 800aa44: b480 push {r7} 800aa46: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); 800aa48: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aa4c: 681b ldr r3, [r3, #0] 800aa4e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800aa52: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800aa56: d101 bne.n 800aa5c 800aa58: 2301 movs r3, #1 800aa5a: e000 b.n 800aa5e 800aa5c: 2300 movs r3, #0 } 800aa5e: 4618 mov r0, r3 800aa60: 46bd mov sp, r7 800aa62: f85d 7b04 ldr.w r7, [sp], #4 800aa66: 4770 bx lr 0800aa68 : { 800aa68: b480 push {r7} 800aa6a: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSION); 800aa6c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aa70: 681b ldr r3, [r3, #0] 800aa72: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800aa76: f443 7380 orr.w r3, r3, #256 @ 0x100 800aa7a: 6013 str r3, [r2, #0] } 800aa7c: bf00 nop 800aa7e: 46bd mov sp, r7 800aa80: f85d 7b04 ldr.w r7, [sp], #4 800aa84: 4770 bx lr 0800aa86 : { 800aa86: b480 push {r7} 800aa88: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 800aa8a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aa8e: 681b ldr r3, [r3, #0] 800aa90: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800aa94: f423 7380 bic.w r3, r3, #256 @ 0x100 800aa98: 6013 str r3, [r2, #0] } 800aa9a: bf00 nop 800aa9c: 46bd mov sp, r7 800aa9e: f85d 7b04 ldr.w r7, [sp], #4 800aaa2: 4770 bx lr 0800aaa4 : { 800aaa4: b480 push {r7} 800aaa6: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); 800aaa8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aaac: 681b ldr r3, [r3, #0] 800aaae: f403 6380 and.w r3, r3, #1024 @ 0x400 800aab2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800aab6: d101 bne.n 800aabc 800aab8: 2301 movs r3, #1 800aaba: e000 b.n 800aabe 800aabc: 2300 movs r3, #0 } 800aabe: 4618 mov r0, r3 800aac0: 46bd mov sp, r7 800aac2: f85d 7b04 ldr.w r7, [sp], #4 800aac6: 4770 bx lr 0800aac8 : { 800aac8: b480 push {r7} 800aaca: b083 sub sp, #12 800aacc: af00 add r7, sp, #0 800aace: 6078 str r0, [r7, #4] MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); 800aad0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aad4: 685b ldr r3, [r3, #4] 800aad6: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800aada: 687b ldr r3, [r7, #4] 800aadc: 061b lsls r3, r3, #24 800aade: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800aae2: 4313 orrs r3, r2 800aae4: 604b str r3, [r1, #4] } 800aae6: bf00 nop 800aae8: 370c adds r7, #12 800aaea: 46bd mov sp, r7 800aaec: f85d 7b04 ldr.w r7, [sp], #4 800aaf0: 4770 bx lr 0800aaf2 : { 800aaf2: b480 push {r7} 800aaf4: af00 add r7, sp, #0 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 800aaf6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aafa: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800aafe: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ab02: f043 0301 orr.w r3, r3, #1 800ab06: f8c2 3098 str.w r3, [r2, #152] @ 0x98 } 800ab0a: bf00 nop 800ab0c: 46bd mov sp, r7 800ab0e: f85d 7b04 ldr.w r7, [sp], #4 800ab12: 4770 bx lr 0800ab14 : { 800ab14: b480 push {r7} 800ab16: af00 add r7, sp, #0 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 800ab18: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ab1c: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800ab20: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ab24: f023 0301 bic.w r3, r3, #1 800ab28: f8c2 3098 str.w r3, [r2, #152] @ 0x98 } 800ab2c: bf00 nop 800ab2e: 46bd mov sp, r7 800ab30: f85d 7b04 ldr.w r7, [sp], #4 800ab34: 4770 bx lr 0800ab36 : { 800ab36: b480 push {r7} 800ab38: af00 add r7, sp, #0 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL); 800ab3a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ab3e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800ab42: f003 0302 and.w r3, r3, #2 800ab46: 2b02 cmp r3, #2 800ab48: d101 bne.n 800ab4e 800ab4a: 2301 movs r3, #1 800ab4c: e000 b.n 800ab50 800ab4e: 2300 movs r3, #0 } 800ab50: 4618 mov r0, r3 800ab52: 46bd mov sp, r7 800ab54: f85d 7b04 ldr.w r7, [sp], #4 800ab58: 4770 bx lr 0800ab5a : { 800ab5a: b480 push {r7} 800ab5c: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 800ab5e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ab62: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ab66: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ab6a: f043 0301 orr.w r3, r3, #1 800ab6e: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800ab72: bf00 nop 800ab74: 46bd mov sp, r7 800ab76: f85d 7b04 ldr.w r7, [sp], #4 800ab7a: 4770 bx lr 0800ab7c : { 800ab7c: b480 push {r7} 800ab7e: af00 add r7, sp, #0 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 800ab80: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ab84: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ab88: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ab8c: f023 0301 bic.w r3, r3, #1 800ab90: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800ab94: bf00 nop 800ab96: 46bd mov sp, r7 800ab98: f85d 7b04 ldr.w r7, [sp], #4 800ab9c: 4770 bx lr 0800ab9e : { 800ab9e: b480 push {r7} 800aba0: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 800aba2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aba6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800abaa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800abae: f043 0304 orr.w r3, r3, #4 800abb2: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800abb6: bf00 nop 800abb8: 46bd mov sp, r7 800abba: f85d 7b04 ldr.w r7, [sp], #4 800abbe: 4770 bx lr 0800abc0 : { 800abc0: b480 push {r7} 800abc2: af00 add r7, sp, #0 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 800abc4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800abc8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800abcc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800abd0: f023 0304 bic.w r3, r3, #4 800abd4: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800abd8: bf00 nop 800abda: 46bd mov sp, r7 800abdc: f85d 7b04 ldr.w r7, [sp], #4 800abe0: 4770 bx lr 0800abe2 : { 800abe2: b480 push {r7} 800abe4: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); 800abe6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800abea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800abee: f003 0302 and.w r3, r3, #2 800abf2: 2b02 cmp r3, #2 800abf4: d101 bne.n 800abfa 800abf6: 2301 movs r3, #1 800abf8: e000 b.n 800abfc 800abfa: 2300 movs r3, #0 } 800abfc: 4618 mov r0, r3 800abfe: 46bd mov sp, r7 800ac00: f85d 7b04 ldr.w r7, [sp], #4 800ac04: 4770 bx lr 0800ac06 : { 800ac06: b480 push {r7} 800ac08: af00 add r7, sp, #0 SET_BIT(RCC->CSR, RCC_CSR_LSI1ON); 800ac0a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac0e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800ac12: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac16: f043 0301 orr.w r3, r3, #1 800ac1a: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 800ac1e: bf00 nop 800ac20: 46bd mov sp, r7 800ac22: f85d 7b04 ldr.w r7, [sp], #4 800ac26: 4770 bx lr 0800ac28 : { 800ac28: b480 push {r7} 800ac2a: af00 add r7, sp, #0 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON); 800ac2c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac30: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800ac34: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac38: f023 0301 bic.w r3, r3, #1 800ac3c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 800ac40: bf00 nop 800ac42: 46bd mov sp, r7 800ac44: f85d 7b04 ldr.w r7, [sp], #4 800ac48: 4770 bx lr 0800ac4a : { 800ac4a: b480 push {r7} 800ac4c: af00 add r7, sp, #0 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL); 800ac4e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac52: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800ac56: f003 0302 and.w r3, r3, #2 800ac5a: 2b02 cmp r3, #2 800ac5c: d101 bne.n 800ac62 800ac5e: 2301 movs r3, #1 800ac60: e000 b.n 800ac64 800ac62: 2300 movs r3, #0 } 800ac64: 4618 mov r0, r3 800ac66: 46bd mov sp, r7 800ac68: f85d 7b04 ldr.w r7, [sp], #4 800ac6c: 4770 bx lr 0800ac6e : { 800ac6e: b480 push {r7} 800ac70: af00 add r7, sp, #0 SET_BIT(RCC->CSR, RCC_CSR_LSI2ON); 800ac72: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac76: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800ac7a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac7e: f043 0304 orr.w r3, r3, #4 800ac82: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 800ac86: bf00 nop 800ac88: 46bd mov sp, r7 800ac8a: f85d 7b04 ldr.w r7, [sp], #4 800ac8e: 4770 bx lr 0800ac90 : { 800ac90: b480 push {r7} 800ac92: af00 add r7, sp, #0 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON); 800ac94: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac98: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800ac9c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800aca0: f023 0304 bic.w r3, r3, #4 800aca4: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 800aca8: bf00 nop 800acaa: 46bd mov sp, r7 800acac: f85d 7b04 ldr.w r7, [sp], #4 800acb0: 4770 bx lr 0800acb2 : { 800acb2: b480 push {r7} 800acb4: af00 add r7, sp, #0 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL); 800acb6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800acba: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800acbe: f003 0308 and.w r3, r3, #8 800acc2: 2b08 cmp r3, #8 800acc4: d101 bne.n 800acca 800acc6: 2301 movs r3, #1 800acc8: e000 b.n 800accc 800acca: 2300 movs r3, #0 } 800accc: 4618 mov r0, r3 800acce: 46bd mov sp, r7 800acd0: f85d 7b04 ldr.w r7, [sp], #4 800acd4: 4770 bx lr 0800acd6 : { 800acd6: b480 push {r7} 800acd8: b083 sub sp, #12 800acda: af00 add r7, sp, #0 800acdc: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos); 800acde: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ace2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800ace6: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800acea: 687b ldr r3, [r7, #4] 800acec: 021b lsls r3, r3, #8 800acee: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800acf2: 4313 orrs r3, r2 800acf4: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } 800acf8: bf00 nop 800acfa: 370c adds r7, #12 800acfc: 46bd mov sp, r7 800acfe: f85d 7b04 ldr.w r7, [sp], #4 800ad02: 4770 bx lr 0800ad04 : { 800ad04: b480 push {r7} 800ad06: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSION); 800ad08: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad0c: 681b ldr r3, [r3, #0] 800ad0e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ad12: f043 0301 orr.w r3, r3, #1 800ad16: 6013 str r3, [r2, #0] } 800ad18: bf00 nop 800ad1a: 46bd mov sp, r7 800ad1c: f85d 7b04 ldr.w r7, [sp], #4 800ad20: 4770 bx lr 0800ad22 : { 800ad22: b480 push {r7} 800ad24: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_MSION); 800ad26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad2a: 681b ldr r3, [r3, #0] 800ad2c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ad30: f023 0301 bic.w r3, r3, #1 800ad34: 6013 str r3, [r2, #0] } 800ad36: bf00 nop 800ad38: 46bd mov sp, r7 800ad3a: f85d 7b04 ldr.w r7, [sp], #4 800ad3e: 4770 bx lr 0800ad40 : { 800ad40: b480 push {r7} 800ad42: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); 800ad44: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad48: 681b ldr r3, [r3, #0] 800ad4a: f003 0302 and.w r3, r3, #2 800ad4e: 2b02 cmp r3, #2 800ad50: d101 bne.n 800ad56 800ad52: 2301 movs r3, #1 800ad54: e000 b.n 800ad58 800ad56: 2300 movs r3, #0 } 800ad58: 4618 mov r0, r3 800ad5a: 46bd mov sp, r7 800ad5c: f85d 7b04 ldr.w r7, [sp], #4 800ad60: 4770 bx lr 0800ad62 : { 800ad62: b480 push {r7} 800ad64: b083 sub sp, #12 800ad66: af00 add r7, sp, #0 800ad68: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); 800ad6a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad6e: 681b ldr r3, [r3, #0] 800ad70: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800ad74: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800ad78: 687b ldr r3, [r7, #4] 800ad7a: 4313 orrs r3, r2 800ad7c: 600b str r3, [r1, #0] } 800ad7e: bf00 nop 800ad80: 370c adds r7, #12 800ad82: 46bd mov sp, r7 800ad84: f85d 7b04 ldr.w r7, [sp], #4 800ad88: 4770 bx lr 0800ad8a : { 800ad8a: b480 push {r7} 800ad8c: b083 sub sp, #12 800ad8e: af00 add r7, sp, #0 uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); 800ad90: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad94: 681b ldr r3, [r3, #0] 800ad96: f003 03f0 and.w r3, r3, #240 @ 0xf0 800ad9a: 607b str r3, [r7, #4] if (msiRange > LL_RCC_MSIRANGE_11) 800ad9c: 687b ldr r3, [r7, #4] 800ad9e: 2bb0 cmp r3, #176 @ 0xb0 800ada0: d901 bls.n 800ada6 msiRange = LL_RCC_MSIRANGE_11; 800ada2: 23b0 movs r3, #176 @ 0xb0 800ada4: 607b str r3, [r7, #4] return msiRange; 800ada6: 687b ldr r3, [r7, #4] } 800ada8: 4618 mov r0, r3 800adaa: 370c adds r7, #12 800adac: 46bd mov sp, r7 800adae: f85d 7b04 ldr.w r7, [sp], #4 800adb2: 4770 bx lr 0800adb4 : { 800adb4: b480 push {r7} 800adb6: b083 sub sp, #12 800adb8: af00 add r7, sp, #0 800adba: 6078 str r0, [r7, #4] MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); 800adbc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800adc0: 685b ldr r3, [r3, #4] 800adc2: f423 427f bic.w r2, r3, #65280 @ 0xff00 800adc6: 687b ldr r3, [r7, #4] 800adc8: 021b lsls r3, r3, #8 800adca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800adce: 4313 orrs r3, r2 800add0: 604b str r3, [r1, #4] } 800add2: bf00 nop 800add4: 370c adds r7, #12 800add6: 46bd mov sp, r7 800add8: f85d 7b04 ldr.w r7, [sp], #4 800addc: 4770 bx lr 0800adde : { 800adde: b480 push {r7} 800ade0: b083 sub sp, #12 800ade2: af00 add r7, sp, #0 800ade4: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 800ade6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800adea: 689b ldr r3, [r3, #8] 800adec: f023 0203 bic.w r2, r3, #3 800adf0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800adf4: 687b ldr r3, [r7, #4] 800adf6: 4313 orrs r3, r2 800adf8: 608b str r3, [r1, #8] } 800adfa: bf00 nop 800adfc: 370c adds r7, #12 800adfe: 46bd mov sp, r7 800ae00: f85d 7b04 ldr.w r7, [sp], #4 800ae04: 4770 bx lr 0800ae06 : { 800ae06: b480 push {r7} 800ae08: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 800ae0a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ae0e: 689b ldr r3, [r3, #8] 800ae10: f003 030c and.w r3, r3, #12 } 800ae14: 4618 mov r0, r3 800ae16: 46bd mov sp, r7 800ae18: f85d 7b04 ldr.w r7, [sp], #4 800ae1c: 4770 bx lr 0800ae1e : { 800ae1e: b480 push {r7} 800ae20: b083 sub sp, #12 800ae22: af00 add r7, sp, #0 800ae24: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 800ae26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ae2a: 689b ldr r3, [r3, #8] 800ae2c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800ae30: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800ae34: 687b ldr r3, [r7, #4] 800ae36: 4313 orrs r3, r2 800ae38: 608b str r3, [r1, #8] } 800ae3a: bf00 nop 800ae3c: 370c adds r7, #12 800ae3e: 46bd mov sp, r7 800ae40: f85d 7b04 ldr.w r7, [sp], #4 800ae44: 4770 bx lr 0800ae46 : { 800ae46: b480 push {r7} 800ae48: b083 sub sp, #12 800ae4a: af00 add r7, sp, #0 800ae4c: 6078 str r0, [r7, #4] MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler); 800ae4e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ae52: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800ae56: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800ae5a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800ae5e: 687b ldr r3, [r7, #4] 800ae60: 4313 orrs r3, r2 800ae62: f8c1 3108 str.w r3, [r1, #264] @ 0x108 } 800ae66: bf00 nop 800ae68: 370c adds r7, #12 800ae6a: 46bd mov sp, r7 800ae6c: f85d 7b04 ldr.w r7, [sp], #4 800ae70: 4770 bx lr 0800ae72 : { 800ae72: b480 push {r7} 800ae74: b083 sub sp, #12 800ae76: af00 add r7, sp, #0 800ae78: 6078 str r0, [r7, #4] MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); 800ae7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ae7e: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800ae82: f023 020f bic.w r2, r3, #15 800ae86: 687b ldr r3, [r7, #4] 800ae88: 091b lsrs r3, r3, #4 800ae8a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800ae8e: 4313 orrs r3, r2 800ae90: f8c1 3108 str.w r3, [r1, #264] @ 0x108 } 800ae94: bf00 nop 800ae96: 370c adds r7, #12 800ae98: 46bd mov sp, r7 800ae9a: f85d 7b04 ldr.w r7, [sp], #4 800ae9e: 4770 bx lr 0800aea0 : { 800aea0: b480 push {r7} 800aea2: b083 sub sp, #12 800aea4: af00 add r7, sp, #0 800aea6: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 800aea8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aeac: 689b ldr r3, [r3, #8] 800aeae: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800aeb2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800aeb6: 687b ldr r3, [r7, #4] 800aeb8: 4313 orrs r3, r2 800aeba: 608b str r3, [r1, #8] } 800aebc: bf00 nop 800aebe: 370c adds r7, #12 800aec0: 46bd mov sp, r7 800aec2: f85d 7b04 ldr.w r7, [sp], #4 800aec6: 4770 bx lr 0800aec8 : { 800aec8: b480 push {r7} 800aeca: b083 sub sp, #12 800aecc: af00 add r7, sp, #0 800aece: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 800aed0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aed4: 689b ldr r3, [r3, #8] 800aed6: f423 5260 bic.w r2, r3, #14336 @ 0x3800 800aeda: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800aede: 687b ldr r3, [r7, #4] 800aee0: 4313 orrs r3, r2 800aee2: 608b str r3, [r1, #8] } 800aee4: bf00 nop 800aee6: 370c adds r7, #12 800aee8: 46bd mov sp, r7 800aeea: f85d 7b04 ldr.w r7, [sp], #4 800aeee: 4770 bx lr 0800aef0 : { 800aef0: b480 push {r7} 800aef2: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 800aef4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aef8: 689b ldr r3, [r3, #8] 800aefa: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 800aefe: 4618 mov r0, r3 800af00: 46bd mov sp, r7 800af02: f85d 7b04 ldr.w r7, [sp], #4 800af06: 4770 bx lr 0800af08 : { 800af08: b480 push {r7} 800af0a: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE)); 800af0c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800af10: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800af14: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 800af18: 4618 mov r0, r3 800af1a: 46bd mov sp, r7 800af1c: f85d 7b04 ldr.w r7, [sp], #4 800af20: 4770 bx lr 0800af22 : { 800af22: b480 push {r7} 800af24: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); 800af26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800af2a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800af2e: 011b lsls r3, r3, #4 800af30: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 800af34: 4618 mov r0, r3 800af36: 46bd mov sp, r7 800af38: f85d 7b04 ldr.w r7, [sp], #4 800af3c: 4770 bx lr 0800af3e : { 800af3e: b480 push {r7} 800af40: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 800af42: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800af46: 689b ldr r3, [r3, #8] 800af48: f403 63e0 and.w r3, r3, #1792 @ 0x700 } 800af4c: 4618 mov r0, r3 800af4e: 46bd mov sp, r7 800af50: f85d 7b04 ldr.w r7, [sp], #4 800af54: 4770 bx lr 0800af56 : { 800af56: b480 push {r7} 800af58: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 800af5a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800af5e: 689b ldr r3, [r3, #8] 800af60: f403 5360 and.w r3, r3, #14336 @ 0x3800 } 800af64: 4618 mov r0, r3 800af66: 46bd mov sp, r7 800af68: f85d 7b04 ldr.w r7, [sp], #4 800af6c: 4770 bx lr 0800af6e : * @brief Enable PLL * @rmtoll CR PLLON LL_RCC_PLL_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Enable(void) { 800af6e: b480 push {r7} 800af70: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_PLLON); 800af72: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800af76: 681b ldr r3, [r3, #0] 800af78: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800af7c: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800af80: 6013 str r3, [r2, #0] } 800af82: bf00 nop 800af84: 46bd mov sp, r7 800af86: f85d 7b04 ldr.w r7, [sp], #4 800af8a: 4770 bx lr 0800af8c : * @note Cannot be disabled if the PLL clock is used as the system clock * @rmtoll CR PLLON LL_RCC_PLL_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Disable(void) { 800af8c: b480 push {r7} 800af8e: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 800af90: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800af94: 681b ldr r3, [r3, #0] 800af96: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800af9a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800af9e: 6013 str r3, [r2, #0] } 800afa0: bf00 nop 800afa2: 46bd mov sp, r7 800afa4: f85d 7b04 ldr.w r7, [sp], #4 800afa8: 4770 bx lr 0800afaa : * @brief Check if PLL Ready * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { 800afaa: b480 push {r7} 800afac: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); 800afae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800afb2: 681b ldr r3, [r3, #0] 800afb4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800afb8: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800afbc: d101 bne.n 800afc2 800afbe: 2301 movs r3, #1 800afc0: e000 b.n 800afc4 800afc2: 2300 movs r3, #0 } 800afc4: 4618 mov r0, r3 800afc6: 46bd mov sp, r7 800afc8: f85d 7b04 ldr.w r7, [sp], #4 800afcc: 4770 bx lr 0800afce : * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN * @retval Between 6 and 127 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) { 800afce: b480 push {r7} 800afd0: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 800afd2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800afd6: 68db ldr r3, [r3, #12] 800afd8: 0a1b lsrs r3, r3, #8 800afda: f003 037f and.w r3, r3, #127 @ 0x7f } 800afde: 4618 mov r0, r3 800afe0: 46bd mov sp, r7 800afe2: f85d 7b04 ldr.w r7, [sp], #4 800afe6: 4770 bx lr 0800afe8 : * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @arg @ref LL_RCC_PLLR_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) { 800afe8: b480 push {r7} 800afea: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); 800afec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aff0: 68db ldr r3, [r3, #12] 800aff2: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000 } 800aff6: 4618 mov r0, r3 800aff8: 46bd mov sp, r7 800affa: f85d 7b04 ldr.w r7, [sp], #4 800affe: 4770 bx lr 0800b000 : * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) { 800b000: b480 push {r7} 800b002: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 800b004: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b008: 68db ldr r3, [r3, #12] 800b00a: f003 0370 and.w r3, r3, #112 @ 0x70 } 800b00e: 4618 mov r0, r3 800b010: 46bd mov sp, r7 800b012: f85d 7b04 ldr.w r7, [sp], #4 800b016: 4770 bx lr 0800b018 : * @arg @ref LL_RCC_PLLSOURCE_MSI * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) { 800b018: b480 push {r7} 800b01a: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 800b01c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b020: 68db ldr r3, [r3, #12] 800b022: f003 0303 and.w r3, r3, #3 } 800b026: 4618 mov r0, r3 800b028: 46bd mov sp, r7 800b02a: f85d 7b04 ldr.w r7, [sp], #4 800b02e: 4770 bx lr 0800b030 : * @brief Check if HCLK1 prescaler flag value has been applied or not * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) { 800b030: b480 push {r7} 800b032: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); 800b034: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b038: 689b ldr r3, [r3, #8] 800b03a: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b03e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b042: d101 bne.n 800b048 800b044: 2301 movs r3, #1 800b046: e000 b.n 800b04a 800b048: 2300 movs r3, #0 } 800b04a: 4618 mov r0, r3 800b04c: 46bd mov sp, r7 800b04e: f85d 7b04 ldr.w r7, [sp], #4 800b052: 4770 bx lr 0800b054 : * @brief Check if HCLK2 prescaler flag value has been applied or not * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void) { 800b054: b480 push {r7} 800b056: af00 add r7, sp, #0 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL); 800b058: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b05c: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800b060: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b064: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800b068: d101 bne.n 800b06e 800b06a: 2301 movs r3, #1 800b06c: e000 b.n 800b070 800b06e: 2300 movs r3, #0 } 800b070: 4618 mov r0, r3 800b072: 46bd mov sp, r7 800b074: f85d 7b04 ldr.w r7, [sp], #4 800b078: 4770 bx lr 0800b07a : * @brief Check if HCLK4 prescaler flag value has been applied or not * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) { 800b07a: b480 push {r7} 800b07c: af00 add r7, sp, #0 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); 800b07e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b082: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800b086: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b08a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b08e: d101 bne.n 800b094 800b090: 2301 movs r3, #1 800b092: e000 b.n 800b096 800b094: 2300 movs r3, #0 } 800b096: 4618 mov r0, r3 800b098: 46bd mov sp, r7 800b09a: f85d 7b04 ldr.w r7, [sp], #4 800b09e: 4770 bx lr 0800b0a0 : * @brief Check if PLCK1 prescaler flag value has been applied or not * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) { 800b0a0: b480 push {r7} 800b0a2: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); 800b0a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b0a8: 689b ldr r3, [r3, #8] 800b0aa: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b0ae: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800b0b2: d101 bne.n 800b0b8 800b0b4: 2301 movs r3, #1 800b0b6: e000 b.n 800b0ba 800b0b8: 2300 movs r3, #0 } 800b0ba: 4618 mov r0, r3 800b0bc: 46bd mov sp, r7 800b0be: f85d 7b04 ldr.w r7, [sp], #4 800b0c2: 4770 bx lr 0800b0c4 : * @brief Check if PLCK2 prescaler flag value has been applied or not * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) { 800b0c4: b480 push {r7} 800b0c6: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); 800b0c8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b0cc: 689b ldr r3, [r3, #8] 800b0ce: f403 2380 and.w r3, r3, #262144 @ 0x40000 800b0d2: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800b0d6: d101 bne.n 800b0dc 800b0d8: 2301 movs r3, #1 800b0da: e000 b.n 800b0de 800b0dc: 2300 movs r3, #0 } 800b0de: 4618 mov r0, r3 800b0e0: 46bd mov sp, r7 800b0e2: f85d 7b04 ldr.w r7, [sp], #4 800b0e6: 4770 bx lr 0800b0e8 : * @note The PLL is not disabled when used as system clock. * @note The PLL source is not updated when used as PLLSAI1 clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800b0e8: b590 push {r4, r7, lr} 800b0ea: b08d sub sp, #52 @ 0x34 800b0ec: af00 add r7, sp, #0 800b0ee: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800b0f0: 687b ldr r3, [r7, #4] 800b0f2: 2b00 cmp r3, #0 800b0f4: d101 bne.n 800b0fa { return HAL_ERROR; 800b0f6: 2301 movs r3, #1 800b0f8: e363 b.n 800b7c2 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*----------------------------- MSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) 800b0fa: 687b ldr r3, [r7, #4] 800b0fc: 681b ldr r3, [r3, #0] 800b0fe: f003 0320 and.w r3, r3, #32 800b102: 2b00 cmp r3, #0 800b104: f000 808d beq.w 800b222 assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* When the MSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b108: f7ff fe7d bl 800ae06 800b10c: 62f8 str r0, [r7, #44] @ 0x2c const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); 800b10e: f7ff ff83 bl 800b018 800b112: 62b8 str r0, [r7, #40] @ 0x28 if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) || 800b114: 6afb ldr r3, [r7, #44] @ 0x2c 800b116: 2b00 cmp r3, #0 800b118: d005 beq.n 800b126 800b11a: 6afb ldr r3, [r7, #44] @ 0x2c 800b11c: 2b0c cmp r3, #12 800b11e: d147 bne.n 800b1b0 ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_MSI))) 800b120: 6abb ldr r3, [r7, #40] @ 0x28 800b122: 2b01 cmp r3, #1 800b124: d144 bne.n 800b1b0 { if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) 800b126: 687b ldr r3, [r7, #4] 800b128: 69db ldr r3, [r3, #28] 800b12a: 2b00 cmp r3, #0 800b12c: d101 bne.n 800b132 { return HAL_ERROR; 800b12e: 2301 movs r3, #1 800b130: e347 b.n 800b7c2 else { /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the AHB4 clock and the supply voltage of the device. */ if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) 800b132: 687b ldr r3, [r7, #4] 800b134: 6a5c ldr r4, [r3, #36] @ 0x24 800b136: f7ff fe28 bl 800ad8a 800b13a: 4603 mov r3, r0 800b13c: 429c cmp r4, r3 800b13e: d914 bls.n 800b16a { /* First increase number of wait states update if necessary */ if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 800b140: 687b ldr r3, [r7, #4] 800b142: 6a5b ldr r3, [r3, #36] @ 0x24 800b144: 4618 mov r0, r3 800b146: f000 fd4b bl 800bbe0 800b14a: 4603 mov r3, r0 800b14c: 2b00 cmp r3, #0 800b14e: d001 beq.n 800b154 { return HAL_ERROR; 800b150: 2301 movs r3, #1 800b152: e336 b.n 800b7c2 } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800b154: 687b ldr r3, [r7, #4] 800b156: 6a5b ldr r3, [r3, #36] @ 0x24 800b158: 4618 mov r0, r3 800b15a: f7ff fe02 bl 800ad62 /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 800b15e: 687b ldr r3, [r7, #4] 800b160: 6a1b ldr r3, [r3, #32] 800b162: 4618 mov r0, r3 800b164: f7ff fe26 bl 800adb4 800b168: e013 b.n 800b192 } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800b16a: 687b ldr r3, [r7, #4] 800b16c: 6a5b ldr r3, [r3, #36] @ 0x24 800b16e: 4618 mov r0, r3 800b170: f7ff fdf7 bl 800ad62 /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 800b174: 687b ldr r3, [r7, #4] 800b176: 6a1b ldr r3, [r3, #32] 800b178: 4618 mov r0, r3 800b17a: f7ff fe1b bl 800adb4 /* Decrease number of wait states update if necessary */ if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 800b17e: 687b ldr r3, [r7, #4] 800b180: 6a5b ldr r3, [r3, #36] @ 0x24 800b182: 4618 mov r0, r3 800b184: f000 fd2c bl 800bbe0 800b188: 4603 mov r3, r0 800b18a: 2b00 cmp r3, #0 800b18c: d001 beq.n 800b192 { return HAL_ERROR; 800b18e: 2301 movs r3, #1 800b190: e317 b.n 800b7c2 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); 800b192: f000 fcc9 bl 800bb28 800b196: 4603 mov r3, r0 800b198: 4aa4 ldr r2, [pc, #656] @ (800b42c ) 800b19a: 6013 str r3, [r2, #0] if (HAL_InitTick(uwTickPrio) != HAL_OK) 800b19c: 4ba4 ldr r3, [pc, #656] @ (800b430 ) 800b19e: 681b ldr r3, [r3, #0] 800b1a0: 4618 mov r0, r3 800b1a2: f7fa fefd bl 8005fa0 800b1a6: 4603 mov r3, r0 800b1a8: 2b00 cmp r3, #0 800b1aa: d039 beq.n 800b220 { return HAL_ERROR; 800b1ac: 2301 movs r3, #1 800b1ae: e308 b.n 800b7c2 } } else { /* Check the MSI State */ if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) 800b1b0: 687b ldr r3, [r7, #4] 800b1b2: 69db ldr r3, [r3, #28] 800b1b4: 2b00 cmp r3, #0 800b1b6: d01e beq.n 800b1f6 { /* Enable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); 800b1b8: f7ff fda4 bl 800ad04 /* Get timeout */ tickstart = HAL_GetTick(); 800b1bc: f7fb f958 bl 8006470 800b1c0: 6278 str r0, [r7, #36] @ 0x24 /* Wait till MSI is ready */ while (LL_RCC_MSI_IsReady() == 0U) 800b1c2: e008 b.n 800b1d6 { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 800b1c4: f7fb f954 bl 8006470 800b1c8: 4602 mov r2, r0 800b1ca: 6a7b ldr r3, [r7, #36] @ 0x24 800b1cc: 1ad3 subs r3, r2, r3 800b1ce: 2b02 cmp r3, #2 800b1d0: d901 bls.n 800b1d6 { return HAL_TIMEOUT; 800b1d2: 2303 movs r3, #3 800b1d4: e2f5 b.n 800b7c2 while (LL_RCC_MSI_IsReady() == 0U) 800b1d6: f7ff fdb3 bl 800ad40 800b1da: 4603 mov r3, r0 800b1dc: 2b00 cmp r3, #0 800b1de: d0f1 beq.n 800b1c4 } } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800b1e0: 687b ldr r3, [r7, #4] 800b1e2: 6a5b ldr r3, [r3, #36] @ 0x24 800b1e4: 4618 mov r0, r3 800b1e6: f7ff fdbc bl 800ad62 /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 800b1ea: 687b ldr r3, [r7, #4] 800b1ec: 6a1b ldr r3, [r3, #32] 800b1ee: 4618 mov r0, r3 800b1f0: f7ff fde0 bl 800adb4 800b1f4: e015 b.n 800b222 } else { /* Disable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); 800b1f6: f7ff fd94 bl 800ad22 /* Get timeout */ tickstart = HAL_GetTick(); 800b1fa: f7fb f939 bl 8006470 800b1fe: 6278 str r0, [r7, #36] @ 0x24 /* Wait till MSI is disabled */ while (LL_RCC_MSI_IsReady() != 0U) 800b200: e008 b.n 800b214 { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 800b202: f7fb f935 bl 8006470 800b206: 4602 mov r2, r0 800b208: 6a7b ldr r3, [r7, #36] @ 0x24 800b20a: 1ad3 subs r3, r2, r3 800b20c: 2b02 cmp r3, #2 800b20e: d901 bls.n 800b214 { return HAL_TIMEOUT; 800b210: 2303 movs r3, #3 800b212: e2d6 b.n 800b7c2 while (LL_RCC_MSI_IsReady() != 0U) 800b214: f7ff fd94 bl 800ad40 800b218: 4603 mov r3, r0 800b21a: 2b00 cmp r3, #0 800b21c: d1f1 bne.n 800b202 800b21e: e000 b.n 800b222 if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) 800b220: bf00 nop } } } /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800b222: 687b ldr r3, [r7, #4] 800b224: 681b ldr r3, [r3, #0] 800b226: f003 0301 and.w r3, r3, #1 800b22a: 2b00 cmp r3, #0 800b22c: d047 beq.n 800b2be { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b22e: f7ff fdea bl 800ae06 800b232: 6238 str r0, [r7, #32] const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); 800b234: f7ff fef0 bl 800b018 800b238: 61f8 str r0, [r7, #28] if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || 800b23a: 6a3b ldr r3, [r7, #32] 800b23c: 2b08 cmp r3, #8 800b23e: d005 beq.n 800b24c 800b240: 6a3b ldr r3, [r7, #32] 800b242: 2b0c cmp r3, #12 800b244: d108 bne.n 800b258 ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSE))) 800b246: 69fb ldr r3, [r7, #28] 800b248: 2b03 cmp r3, #3 800b24a: d105 bne.n 800b258 { if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) 800b24c: 687b ldr r3, [r7, #4] 800b24e: 685b ldr r3, [r3, #4] 800b250: 2b00 cmp r3, #0 800b252: d134 bne.n 800b2be { return HAL_ERROR; 800b254: 2301 movs r3, #1 800b256: e2b4 b.n 800b7c2 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800b258: 687b ldr r3, [r7, #4] 800b25a: 685b ldr r3, [r3, #4] 800b25c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b260: d102 bne.n 800b268 800b262: f7ff fbd1 bl 800aa08 800b266: e001 b.n 800b26c 800b268: f7ff fbdd bl 800aa26 /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800b26c: 687b ldr r3, [r7, #4] 800b26e: 685b ldr r3, [r3, #4] 800b270: 2b00 cmp r3, #0 800b272: d012 beq.n 800b29a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b274: f7fb f8fc bl 8006470 800b278: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (LL_RCC_HSE_IsReady() == 0U) 800b27a: e008 b.n 800b28e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800b27c: f7fb f8f8 bl 8006470 800b280: 4602 mov r2, r0 800b282: 6a7b ldr r3, [r7, #36] @ 0x24 800b284: 1ad3 subs r3, r2, r3 800b286: 2b64 cmp r3, #100 @ 0x64 800b288: d901 bls.n 800b28e { return HAL_TIMEOUT; 800b28a: 2303 movs r3, #3 800b28c: e299 b.n 800b7c2 while (LL_RCC_HSE_IsReady() == 0U) 800b28e: f7ff fbd9 bl 800aa44 800b292: 4603 mov r3, r0 800b294: 2b00 cmp r3, #0 800b296: d0f1 beq.n 800b27c 800b298: e011 b.n 800b2be } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b29a: f7fb f8e9 bl 8006470 800b29e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (LL_RCC_HSE_IsReady() != 0U) 800b2a0: e008 b.n 800b2b4 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800b2a2: f7fb f8e5 bl 8006470 800b2a6: 4602 mov r2, r0 800b2a8: 6a7b ldr r3, [r7, #36] @ 0x24 800b2aa: 1ad3 subs r3, r2, r3 800b2ac: 2b64 cmp r3, #100 @ 0x64 800b2ae: d901 bls.n 800b2b4 { return HAL_TIMEOUT; 800b2b0: 2303 movs r3, #3 800b2b2: e286 b.n 800b7c2 while (LL_RCC_HSE_IsReady() != 0U) 800b2b4: f7ff fbc6 bl 800aa44 800b2b8: 4603 mov r3, r0 800b2ba: 2b00 cmp r3, #0 800b2bc: d1f1 bne.n 800b2a2 } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800b2be: 687b ldr r3, [r7, #4] 800b2c0: 681b ldr r3, [r3, #0] 800b2c2: f003 0302 and.w r3, r3, #2 800b2c6: 2b00 cmp r3, #0 800b2c8: d04c beq.n 800b364 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b2ca: f7ff fd9c bl 800ae06 800b2ce: 61b8 str r0, [r7, #24] const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); 800b2d0: f7ff fea2 bl 800b018 800b2d4: 6178 str r0, [r7, #20] if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || 800b2d6: 69bb ldr r3, [r7, #24] 800b2d8: 2b04 cmp r3, #4 800b2da: d005 beq.n 800b2e8 800b2dc: 69bb ldr r3, [r7, #24] 800b2de: 2b0c cmp r3, #12 800b2e0: d10e bne.n 800b300 ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSI))) 800b2e2: 697b ldr r3, [r7, #20] 800b2e4: 2b02 cmp r3, #2 800b2e6: d10b bne.n 800b300 { /* When HSI is used as system clock it will not be disabled */ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) 800b2e8: 687b ldr r3, [r7, #4] 800b2ea: 68db ldr r3, [r3, #12] 800b2ec: 2b00 cmp r3, #0 800b2ee: d101 bne.n 800b2f4 { return HAL_ERROR; 800b2f0: 2301 movs r3, #1 800b2f2: e266 b.n 800b7c2 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b2f4: 687b ldr r3, [r7, #4] 800b2f6: 691b ldr r3, [r3, #16] 800b2f8: 4618 mov r0, r3 800b2fa: f7ff fbe5 bl 800aac8 if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) 800b2fe: e031 b.n 800b364 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800b300: 687b ldr r3, [r7, #4] 800b302: 68db ldr r3, [r3, #12] 800b304: 2b00 cmp r3, #0 800b306: d019 beq.n 800b33c { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800b308: f7ff fbae bl 800aa68 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b30c: f7fb f8b0 bl 8006470 800b310: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (LL_RCC_HSI_IsReady() == 0U) 800b312: e008 b.n 800b326 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b314: f7fb f8ac bl 8006470 800b318: 4602 mov r2, r0 800b31a: 6a7b ldr r3, [r7, #36] @ 0x24 800b31c: 1ad3 subs r3, r2, r3 800b31e: 2b02 cmp r3, #2 800b320: d901 bls.n 800b326 { return HAL_TIMEOUT; 800b322: 2303 movs r3, #3 800b324: e24d b.n 800b7c2 while (LL_RCC_HSI_IsReady() == 0U) 800b326: f7ff fbbd bl 800aaa4 800b32a: 4603 mov r3, r0 800b32c: 2b00 cmp r3, #0 800b32e: d0f1 beq.n 800b314 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b330: 687b ldr r3, [r7, #4] 800b332: 691b ldr r3, [r3, #16] 800b334: 4618 mov r0, r3 800b336: f7ff fbc7 bl 800aac8 800b33a: e013 b.n 800b364 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800b33c: f7ff fba3 bl 800aa86 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b340: f7fb f896 bl 8006470 800b344: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (LL_RCC_HSI_IsReady() != 0U) 800b346: e008 b.n 800b35a { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b348: f7fb f892 bl 8006470 800b34c: 4602 mov r2, r0 800b34e: 6a7b ldr r3, [r7, #36] @ 0x24 800b350: 1ad3 subs r3, r2, r3 800b352: 2b02 cmp r3, #2 800b354: d901 bls.n 800b35a { return HAL_TIMEOUT; 800b356: 2303 movs r3, #3 800b358: e233 b.n 800b7c2 while (LL_RCC_HSI_IsReady() != 0U) 800b35a: f7ff fba3 bl 800aaa4 800b35e: 4603 mov r3, r0 800b360: 2b00 cmp r3, #0 800b362: d1f1 bne.n 800b348 } } } /*------------------------------ LSI Configuration (LSI1 or LSI2) -------------------------*/ if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ 800b364: 687b ldr r3, [r7, #4] 800b366: 681b ldr r3, [r3, #0] 800b368: f003 0308 and.w r3, r3, #8 800b36c: 2b00 cmp r3, #0 800b36e: d106 bne.n 800b37e (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2)) 800b370: 687b ldr r3, [r7, #4] 800b372: 681b ldr r3, [r3, #0] 800b374: f003 0310 and.w r3, r3, #16 if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ 800b378: 2b00 cmp r3, #0 800b37a: f000 80a3 beq.w 800b4c4 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800b37e: 687b ldr r3, [r7, #4] 800b380: 695b ldr r3, [r3, #20] 800b382: 2b00 cmp r3, #0 800b384: d076 beq.n 800b474 { /*------------------------------ LSI2 selected by default (when Switch ON) -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) 800b386: 687b ldr r3, [r7, #4] 800b388: 681b ldr r3, [r3, #0] 800b38a: f003 0310 and.w r3, r3, #16 800b38e: 2b00 cmp r3, #0 800b390: d046 beq.n 800b420 { assert_param(IS_RCC_LSI2_CALIBRATION_VALUE(RCC_OscInitStruct->LSI2CalibrationValue)); /* 1. Check LSI1 state and enable if required */ if (LL_RCC_LSI1_IsReady() == 0U) 800b392: f7ff fc5a bl 800ac4a 800b396: 4603 mov r3, r0 800b398: 2b00 cmp r3, #0 800b39a: d113 bne.n 800b3c4 { /* This is required to enable LSI1 before enabling LSI2 */ __HAL_RCC_LSI1_ENABLE(); 800b39c: f7ff fc33 bl 800ac06 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b3a0: f7fb f866 bl 8006470 800b3a4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI1 is ready */ while (LL_RCC_LSI1_IsReady() == 0U) 800b3a6: e008 b.n 800b3ba { if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) 800b3a8: f7fb f862 bl 8006470 800b3ac: 4602 mov r2, r0 800b3ae: 6a7b ldr r3, [r7, #36] @ 0x24 800b3b0: 1ad3 subs r3, r2, r3 800b3b2: 2b02 cmp r3, #2 800b3b4: d901 bls.n 800b3ba { return HAL_TIMEOUT; 800b3b6: 2303 movs r3, #3 800b3b8: e203 b.n 800b7c2 while (LL_RCC_LSI1_IsReady() == 0U) 800b3ba: f7ff fc46 bl 800ac4a 800b3be: 4603 mov r3, r0 800b3c0: 2b00 cmp r3, #0 800b3c2: d0f1 beq.n 800b3a8 } } } /* 2. Enable the Internal Low Speed oscillator (LSI2) and set trimming value */ __HAL_RCC_LSI2_ENABLE(); 800b3c4: f7ff fc53 bl 800ac6e /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b3c8: f7fb f852 bl 8006470 800b3cc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI2 is ready */ while (LL_RCC_LSI2_IsReady() == 0U) 800b3ce: e008 b.n 800b3e2 { if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) 800b3d0: f7fb f84e bl 8006470 800b3d4: 4602 mov r2, r0 800b3d6: 6a7b ldr r3, [r7, #36] @ 0x24 800b3d8: 1ad3 subs r3, r2, r3 800b3da: 2b03 cmp r3, #3 800b3dc: d901 bls.n 800b3e2 { return HAL_TIMEOUT; 800b3de: 2303 movs r3, #3 800b3e0: e1ef b.n 800b7c2 while (LL_RCC_LSI2_IsReady() == 0U) 800b3e2: f7ff fc66 bl 800acb2 800b3e6: 4603 mov r3, r0 800b3e8: 2b00 cmp r3, #0 800b3ea: d0f1 beq.n 800b3d0 } } /* Adjusts the Internal Low Spee oscillator (LSI2) calibration value */ __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->LSI2CalibrationValue); 800b3ec: 687b ldr r3, [r7, #4] 800b3ee: 699b ldr r3, [r3, #24] 800b3f0: 4618 mov r0, r3 800b3f2: f7ff fc70 bl 800acd6 /* 3. Disable LSI1 */ /* LSI1 was initially not enable, require to disable it */ __HAL_RCC_LSI1_DISABLE(); 800b3f6: f7ff fc17 bl 800ac28 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b3fa: f7fb f839 bl 8006470 800b3fe: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI1 is disabled */ while (LL_RCC_LSI1_IsReady() != 0U) 800b400: e008 b.n 800b414 { if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) 800b402: f7fb f835 bl 8006470 800b406: 4602 mov r2, r0 800b408: 6a7b ldr r3, [r7, #36] @ 0x24 800b40a: 1ad3 subs r3, r2, r3 800b40c: 2b02 cmp r3, #2 800b40e: d901 bls.n 800b414 { return HAL_TIMEOUT; 800b410: 2303 movs r3, #3 800b412: e1d6 b.n 800b7c2 while (LL_RCC_LSI1_IsReady() != 0U) 800b414: f7ff fc19 bl 800ac4a 800b418: 4603 mov r3, r0 800b41a: 2b00 cmp r3, #0 800b41c: d1f1 bne.n 800b402 800b41e: e051 b.n 800b4c4 else { /*------------------------------ LSI1 selected (only if LSI2 OFF)-------------------------*/ /* 1. Enable the Internal Low Speed oscillator (LSI1). */ __HAL_RCC_LSI1_ENABLE(); 800b420: f7ff fbf1 bl 800ac06 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b424: f7fb f824 bl 8006470 800b428: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI1 is ready */ while (LL_RCC_LSI1_IsReady() == 0U) 800b42a: e00c b.n 800b446 800b42c: 2000000c .word 0x2000000c 800b430: 20000010 .word 0x20000010 { if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) 800b434: f7fb f81c bl 8006470 800b438: 4602 mov r2, r0 800b43a: 6a7b ldr r3, [r7, #36] @ 0x24 800b43c: 1ad3 subs r3, r2, r3 800b43e: 2b02 cmp r3, #2 800b440: d901 bls.n 800b446 { return HAL_TIMEOUT; 800b442: 2303 movs r3, #3 800b444: e1bd b.n 800b7c2 while (LL_RCC_LSI1_IsReady() == 0U) 800b446: f7ff fc00 bl 800ac4a 800b44a: 4603 mov r3, r0 800b44c: 2b00 cmp r3, #0 800b44e: d0f1 beq.n 800b434 } } /*2. Switch OFF LSI2*/ /* Disable the Internal Low Speed oscillator (LSI2). */ __HAL_RCC_LSI2_DISABLE(); 800b450: f7ff fc1e bl 800ac90 /* Wait till LSI2 is disabled */ while (LL_RCC_LSI2_IsReady() != 0U) 800b454: e008 b.n 800b468 { if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) 800b456: f7fb f80b bl 8006470 800b45a: 4602 mov r2, r0 800b45c: 6a7b ldr r3, [r7, #36] @ 0x24 800b45e: 1ad3 subs r3, r2, r3 800b460: 2b03 cmp r3, #3 800b462: d901 bls.n 800b468 { return HAL_TIMEOUT; 800b464: 2303 movs r3, #3 800b466: e1ac b.n 800b7c2 while (LL_RCC_LSI2_IsReady() != 0U) 800b468: f7ff fc23 bl 800acb2 800b46c: 4603 mov r3, r0 800b46e: 2b00 cmp r3, #0 800b470: d1f1 bne.n 800b456 800b472: e027 b.n 800b4c4 } else { /* Disable the Internal Low Speed oscillator (LSI2). */ __HAL_RCC_LSI2_DISABLE(); 800b474: f7ff fc0c bl 800ac90 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b478: f7fa fffa bl 8006470 800b47c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI2 is disabled */ while (LL_RCC_LSI2_IsReady() != 0U) 800b47e: e008 b.n 800b492 { if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) 800b480: f7fa fff6 bl 8006470 800b484: 4602 mov r2, r0 800b486: 6a7b ldr r3, [r7, #36] @ 0x24 800b488: 1ad3 subs r3, r2, r3 800b48a: 2b03 cmp r3, #3 800b48c: d901 bls.n 800b492 { return HAL_TIMEOUT; 800b48e: 2303 movs r3, #3 800b490: e197 b.n 800b7c2 while (LL_RCC_LSI2_IsReady() != 0U) 800b492: f7ff fc0e bl 800acb2 800b496: 4603 mov r3, r0 800b498: 2b00 cmp r3, #0 800b49a: d1f1 bne.n 800b480 } } /* Disable the Internal Low Speed oscillator (LSI1). */ __HAL_RCC_LSI1_DISABLE(); 800b49c: f7ff fbc4 bl 800ac28 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b4a0: f7fa ffe6 bl 8006470 800b4a4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI1 is disabled */ while (LL_RCC_LSI1_IsReady() != 0U) 800b4a6: e008 b.n 800b4ba { if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) 800b4a8: f7fa ffe2 bl 8006470 800b4ac: 4602 mov r2, r0 800b4ae: 6a7b ldr r3, [r7, #36] @ 0x24 800b4b0: 1ad3 subs r3, r2, r3 800b4b2: 2b02 cmp r3, #2 800b4b4: d901 bls.n 800b4ba { return HAL_TIMEOUT; 800b4b6: 2303 movs r3, #3 800b4b8: e183 b.n 800b7c2 while (LL_RCC_LSI1_IsReady() != 0U) 800b4ba: f7ff fbc6 bl 800ac4a 800b4be: 4603 mov r3, r0 800b4c0: 2b00 cmp r3, #0 800b4c2: d1f1 bne.n 800b4a8 } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800b4c4: 687b ldr r3, [r7, #4] 800b4c6: 681b ldr r3, [r3, #0] 800b4c8: f003 0304 and.w r3, r3, #4 800b4cc: 2b00 cmp r3, #0 800b4ce: d05b beq.n 800b588 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800b4d0: 4ba7 ldr r3, [pc, #668] @ (800b770 ) 800b4d2: 681b ldr r3, [r3, #0] 800b4d4: f403 7380 and.w r3, r3, #256 @ 0x100 800b4d8: 2b00 cmp r3, #0 800b4da: d114 bne.n 800b506 { /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); 800b4dc: f7ff fa54 bl 800a988 /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800b4e0: f7fa ffc6 bl 8006470 800b4e4: 6278 str r0, [r7, #36] @ 0x24 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800b4e6: e008 b.n 800b4fa { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800b4e8: f7fa ffc2 bl 8006470 800b4ec: 4602 mov r2, r0 800b4ee: 6a7b ldr r3, [r7, #36] @ 0x24 800b4f0: 1ad3 subs r3, r2, r3 800b4f2: 2b02 cmp r3, #2 800b4f4: d901 bls.n 800b4fa { return HAL_TIMEOUT; 800b4f6: 2303 movs r3, #3 800b4f8: e163 b.n 800b7c2 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800b4fa: 4b9d ldr r3, [pc, #628] @ (800b770 ) 800b4fc: 681b ldr r3, [r3, #0] 800b4fe: f403 7380 and.w r3, r3, #256 @ 0x100 800b502: 2b00 cmp r3, #0 800b504: d0f0 beq.n 800b4e8 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800b506: 687b ldr r3, [r7, #4] 800b508: 689b ldr r3, [r3, #8] 800b50a: 2b01 cmp r3, #1 800b50c: d102 bne.n 800b514 800b50e: f7ff fb24 bl 800ab5a 800b512: e00c b.n 800b52e 800b514: 687b ldr r3, [r7, #4] 800b516: 689b ldr r3, [r3, #8] 800b518: 2b05 cmp r3, #5 800b51a: d104 bne.n 800b526 800b51c: f7ff fb3f bl 800ab9e 800b520: f7ff fb1b bl 800ab5a 800b524: e003 b.n 800b52e 800b526: f7ff fb29 bl 800ab7c 800b52a: f7ff fb49 bl 800abc0 /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800b52e: 687b ldr r3, [r7, #4] 800b530: 689b ldr r3, [r3, #8] 800b532: 2b00 cmp r3, #0 800b534: d014 beq.n 800b560 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b536: f7fa ff9b bl 8006470 800b53a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() == 0U) 800b53c: e00a b.n 800b554 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800b53e: f7fa ff97 bl 8006470 800b542: 4602 mov r2, r0 800b544: 6a7b ldr r3, [r7, #36] @ 0x24 800b546: 1ad3 subs r3, r2, r3 800b548: f241 3288 movw r2, #5000 @ 0x1388 800b54c: 4293 cmp r3, r2 800b54e: d901 bls.n 800b554 { return HAL_TIMEOUT; 800b550: 2303 movs r3, #3 800b552: e136 b.n 800b7c2 while (LL_RCC_LSE_IsReady() == 0U) 800b554: f7ff fb45 bl 800abe2 800b558: 4603 mov r3, r0 800b55a: 2b00 cmp r3, #0 800b55c: d0ef beq.n 800b53e 800b55e: e013 b.n 800b588 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b560: f7fa ff86 bl 8006470 800b564: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (LL_RCC_LSE_IsReady() != 0U) 800b566: e00a b.n 800b57e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800b568: f7fa ff82 bl 8006470 800b56c: 4602 mov r2, r0 800b56e: 6a7b ldr r3, [r7, #36] @ 0x24 800b570: 1ad3 subs r3, r2, r3 800b572: f241 3288 movw r2, #5000 @ 0x1388 800b576: 4293 cmp r3, r2 800b578: d901 bls.n 800b57e { return HAL_TIMEOUT; 800b57a: 2303 movs r3, #3 800b57c: e121 b.n 800b7c2 while (LL_RCC_LSE_IsReady() != 0U) 800b57e: f7ff fb30 bl 800abe2 800b582: 4603 mov r3, r0 800b584: 2b00 cmp r3, #0 800b586: d1ef bne.n 800b568 } } #if defined(RCC_HSI48_SUPPORT) /*------------------------------ HSI48 Configuration -----------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800b588: 687b ldr r3, [r7, #4] 800b58a: 681b ldr r3, [r3, #0] 800b58c: f003 0340 and.w r3, r3, #64 @ 0x40 800b590: 2b00 cmp r3, #0 800b592: d02c beq.n 800b5ee { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI State */ if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 800b594: 687b ldr r3, [r7, #4] 800b596: 6a9b ldr r3, [r3, #40] @ 0x28 800b598: 2b00 cmp r3, #0 800b59a: d014 beq.n 800b5c6 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800b59c: f7ff faa9 bl 800aaf2 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b5a0: f7fa ff66 bl 8006470 800b5a4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (LL_RCC_HSI48_IsReady() == 0U) 800b5a6: e008 b.n 800b5ba { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800b5a8: f7fa ff62 bl 8006470 800b5ac: 4602 mov r2, r0 800b5ae: 6a7b ldr r3, [r7, #36] @ 0x24 800b5b0: 1ad3 subs r3, r2, r3 800b5b2: 2b02 cmp r3, #2 800b5b4: d901 bls.n 800b5ba { return HAL_TIMEOUT; 800b5b6: 2303 movs r3, #3 800b5b8: e103 b.n 800b7c2 while (LL_RCC_HSI48_IsReady() == 0U) 800b5ba: f7ff fabc bl 800ab36 800b5be: 4603 mov r3, r0 800b5c0: 2b00 cmp r3, #0 800b5c2: d0f1 beq.n 800b5a8 800b5c4: e013 b.n 800b5ee } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800b5c6: f7ff faa5 bl 800ab14 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b5ca: f7fa ff51 bl 8006470 800b5ce: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is disabled */ while (LL_RCC_HSI48_IsReady() != 0U) 800b5d0: e008 b.n 800b5e4 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800b5d2: f7fa ff4d bl 8006470 800b5d6: 4602 mov r2, r0 800b5d8: 6a7b ldr r3, [r7, #36] @ 0x24 800b5da: 1ad3 subs r3, r2, r3 800b5dc: 2b02 cmp r3, #2 800b5de: d901 bls.n 800b5e4 { return HAL_TIMEOUT; 800b5e0: 2303 movs r3, #3 800b5e2: e0ee b.n 800b7c2 while (LL_RCC_HSI48_IsReady() != 0U) 800b5e4: f7ff faa7 bl 800ab36 800b5e8: 4603 mov r3, r0 800b5ea: 2b00 cmp r3, #0 800b5ec: d1f1 bne.n 800b5d2 #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 800b5ee: 687b ldr r3, [r7, #4] 800b5f0: 6adb ldr r3, [r3, #44] @ 0x2c 800b5f2: 2b00 cmp r3, #0 800b5f4: f000 80e4 beq.w 800b7c0 { const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b5f8: f7ff fc05 bl 800ae06 800b5fc: 6138 str r0, [r7, #16] const uint32_t temp_pllconfig = RCC->PLLCFGR; 800b5fe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b602: 68db ldr r3, [r3, #12] 800b604: 60fb str r3, [r7, #12] /* PLL On ? */ if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 800b606: 687b ldr r3, [r7, #4] 800b608: 6adb ldr r3, [r3, #44] @ 0x2c 800b60a: 2b02 cmp r3, #2 800b60c: f040 80b4 bne.w 800b778 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Do nothing if PLL configuration is unchanged */ if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800b610: 68fb ldr r3, [r7, #12] 800b612: f003 0203 and.w r2, r3, #3 800b616: 687b ldr r3, [r7, #4] 800b618: 6b1b ldr r3, [r3, #48] @ 0x30 800b61a: 429a cmp r2, r3 800b61c: d123 bne.n 800b666 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 800b61e: 68fb ldr r3, [r7, #12] 800b620: f003 0270 and.w r2, r3, #112 @ 0x70 800b624: 687b ldr r3, [r7, #4] 800b626: 6b5b ldr r3, [r3, #52] @ 0x34 if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800b628: 429a cmp r2, r3 800b62a: d11c bne.n 800b666 ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || 800b62c: 68fb ldr r3, [r7, #12] 800b62e: 0a1b lsrs r3, r3, #8 800b630: f003 027f and.w r2, r3, #127 @ 0x7f 800b634: 687b ldr r3, [r7, #4] 800b636: 6b9b ldr r3, [r3, #56] @ 0x38 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 800b638: 429a cmp r2, r3 800b63a: d114 bne.n 800b666 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 800b63c: 68fb ldr r3, [r7, #12] 800b63e: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 800b642: 687b ldr r3, [r7, #4] 800b644: 6bdb ldr r3, [r3, #60] @ 0x3c ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || 800b646: 429a cmp r2, r3 800b648: d10d bne.n 800b666 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || 800b64a: 68fb ldr r3, [r7, #12] 800b64c: f003 6260 and.w r2, r3, #234881024 @ 0xe000000 800b650: 687b ldr r3, [r7, #4] 800b652: 6c1b ldr r3, [r3, #64] @ 0x40 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 800b654: 429a cmp r2, r3 800b656: d106 bne.n 800b666 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) 800b658: 68fb ldr r3, [r7, #12] 800b65a: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000 800b65e: 687b ldr r3, [r7, #4] 800b660: 6c5b ldr r3, [r3, #68] @ 0x44 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || 800b662: 429a cmp r2, r3 800b664: d05d beq.n 800b722 { /* Check if the PLL is used as system clock or not */ if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800b666: 693b ldr r3, [r7, #16] 800b668: 2b0c cmp r3, #12 800b66a: d058 beq.n 800b71e { #if defined(SAI1) /* Check if main PLL can be updated */ /* Not possible if the source is shared by other enabled PLLSAIx */ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) 800b66c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b670: 681b ldr r3, [r3, #0] 800b672: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800b676: 2b00 cmp r3, #0 800b678: d001 beq.n 800b67e { return HAL_ERROR; 800b67a: 2301 movs r3, #1 800b67c: e0a1 b.n 800b7c2 } else #endif /* SAI1 */ { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800b67e: f7ff fc85 bl 800af8c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b682: f7fa fef5 bl 8006470 800b686: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800b688: e008 b.n 800b69c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800b68a: f7fa fef1 bl 8006470 800b68e: 4602 mov r2, r0 800b690: 6a7b ldr r3, [r7, #36] @ 0x24 800b692: 1ad3 subs r3, r2, r3 800b694: 2b02 cmp r3, #2 800b696: d901 bls.n 800b69c { return HAL_TIMEOUT; 800b698: 2303 movs r3, #3 800b69a: e092 b.n 800b7c2 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800b69c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6a0: 681b ldr r3, [r3, #0] 800b6a2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b6a6: 2b00 cmp r3, #0 800b6a8: d1ef bne.n 800b68a } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800b6aa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6ae: 68da ldr r2, [r3, #12] 800b6b0: 4b30 ldr r3, [pc, #192] @ (800b774 ) 800b6b2: 4013 ands r3, r2 800b6b4: 687a ldr r2, [r7, #4] 800b6b6: 6b11 ldr r1, [r2, #48] @ 0x30 800b6b8: 687a ldr r2, [r7, #4] 800b6ba: 6b52 ldr r2, [r2, #52] @ 0x34 800b6bc: 4311 orrs r1, r2 800b6be: 687a ldr r2, [r7, #4] 800b6c0: 6b92 ldr r2, [r2, #56] @ 0x38 800b6c2: 0212 lsls r2, r2, #8 800b6c4: 4311 orrs r1, r2 800b6c6: 687a ldr r2, [r7, #4] 800b6c8: 6bd2 ldr r2, [r2, #60] @ 0x3c 800b6ca: 4311 orrs r1, r2 800b6cc: 687a ldr r2, [r7, #4] 800b6ce: 6c12 ldr r2, [r2, #64] @ 0x40 800b6d0: 4311 orrs r1, r2 800b6d2: 687a ldr r2, [r7, #4] 800b6d4: 6c52 ldr r2, [r2, #68] @ 0x44 800b6d6: 430a orrs r2, r1 800b6d8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b6dc: 4313 orrs r3, r2 800b6de: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800b6e0: f7ff fc45 bl 800af6e /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 800b6e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6e8: 68db ldr r3, [r3, #12] 800b6ea: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6ee: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800b6f2: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b6f4: f7fa febc bl 8006470 800b6f8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800b6fa: e008 b.n 800b70e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800b6fc: f7fa feb8 bl 8006470 800b700: 4602 mov r2, r0 800b702: 6a7b ldr r3, [r7, #36] @ 0x24 800b704: 1ad3 subs r3, r2, r3 800b706: 2b02 cmp r3, #2 800b708: d901 bls.n 800b70e { return HAL_TIMEOUT; 800b70a: 2303 movs r3, #3 800b70c: e059 b.n 800b7c2 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800b70e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b712: 681b ldr r3, [r3, #0] 800b714: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b718: 2b00 cmp r3, #0 800b71a: d0ef beq.n 800b6fc if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800b71c: e050 b.n 800b7c0 } } else { /* PLL is already used as System core clock */ return HAL_ERROR; 800b71e: 2301 movs r3, #1 800b720: e04f b.n 800b7c2 } else { /* PLL configuration is unchanged */ /* Re-enable PLL if it was disabled (ie. low power mode) */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800b722: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b726: 681b ldr r3, [r3, #0] 800b728: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b72c: 2b00 cmp r3, #0 800b72e: d147 bne.n 800b7c0 { /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800b730: f7ff fc1d bl 800af6e /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 800b734: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b738: 68db ldr r3, [r3, #12] 800b73a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b73e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800b742: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b744: f7fa fe94 bl 8006470 800b748: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800b74a: e008 b.n 800b75e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800b74c: f7fa fe90 bl 8006470 800b750: 4602 mov r2, r0 800b752: 6a7b ldr r3, [r7, #36] @ 0x24 800b754: 1ad3 subs r3, r2, r3 800b756: 2b02 cmp r3, #2 800b758: d901 bls.n 800b75e { return HAL_TIMEOUT; 800b75a: 2303 movs r3, #3 800b75c: e031 b.n 800b7c2 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800b75e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b762: 681b ldr r3, [r3, #0] 800b764: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b768: 2b00 cmp r3, #0 800b76a: d0ef beq.n 800b74c 800b76c: e028 b.n 800b7c0 800b76e: bf00 nop 800b770: 58000400 .word 0x58000400 800b774: 11c1808c .word 0x11c1808c } } else { /* Check that PLL is not used as system clock or not */ if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800b778: 693b ldr r3, [r7, #16] 800b77a: 2b0c cmp r3, #12 800b77c: d01e beq.n 800b7bc { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800b77e: f7ff fc05 bl 800af8c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b782: f7fa fe75 bl 8006470 800b786: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800b788: e008 b.n 800b79c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800b78a: f7fa fe71 bl 8006470 800b78e: 4602 mov r2, r0 800b790: 6a7b ldr r3, [r7, #36] @ 0x24 800b792: 1ad3 subs r3, r2, r3 800b794: 2b02 cmp r3, #2 800b796: d901 bls.n 800b79c { return HAL_TIMEOUT; 800b798: 2303 movs r3, #3 800b79a: e012 b.n 800b7c2 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800b79c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b7a0: 681b ldr r3, [r3, #0] 800b7a2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b7a6: 2b00 cmp r3, #0 800b7a8: d1ef bne.n 800b78a } } /* Disable the PLL source and outputs to save power when PLL is off */ #if defined(SAI1) && defined(USB) CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); 800b7aa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b7ae: 68da ldr r2, [r3, #12] 800b7b0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b7b4: 4b05 ldr r3, [pc, #20] @ (800b7cc ) 800b7b6: 4013 ands r3, r2 800b7b8: 60cb str r3, [r1, #12] 800b7ba: e001 b.n 800b7c0 #endif /* SAI1 && USB */ } else { /* PLL is already used as System core clock */ return HAL_ERROR; 800b7bc: 2301 movs r3, #1 800b7be: e000 b.n 800b7c2 } } } return HAL_OK; 800b7c0: 2300 movs r3, #0 } 800b7c2: 4618 mov r0, r3 800b7c4: 3734 adds r7, #52 @ 0x34 800b7c6: 46bd mov sp, r7 800b7c8: bd90 pop {r4, r7, pc} 800b7ca: bf00 nop 800b7cc: eefefffc .word 0xeefefffc 0800b7d0 : * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800b7d0: b580 push {r7, lr} 800b7d2: b084 sub sp, #16 800b7d4: af00 add r7, sp, #0 800b7d6: 6078 str r0, [r7, #4] 800b7d8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800b7da: 687b ldr r3, [r7, #4] 800b7dc: 2b00 cmp r3, #0 800b7de: d101 bne.n 800b7e4 { return HAL_ERROR; 800b7e0: 2301 movs r3, #1 800b7e2: e12d b.n 800ba40 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK4) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800b7e4: 4b98 ldr r3, [pc, #608] @ (800ba48 ) 800b7e6: 681b ldr r3, [r3, #0] 800b7e8: f003 0307 and.w r3, r3, #7 800b7ec: 683a ldr r2, [r7, #0] 800b7ee: 429a cmp r2, r3 800b7f0: d91b bls.n 800b82a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800b7f2: 4b95 ldr r3, [pc, #596] @ (800ba48 ) 800b7f4: 681b ldr r3, [r3, #0] 800b7f6: f023 0207 bic.w r2, r3, #7 800b7fa: 4993 ldr r1, [pc, #588] @ (800ba48 ) 800b7fc: 683b ldr r3, [r7, #0] 800b7fe: 4313 orrs r3, r2 800b800: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b802: f7fa fe35 bl 8006470 800b806: 60f8 str r0, [r7, #12] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != FLatency) 800b808: e008 b.n 800b81c { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 800b80a: f7fa fe31 bl 8006470 800b80e: 4602 mov r2, r0 800b810: 68fb ldr r3, [r7, #12] 800b812: 1ad3 subs r3, r2, r3 800b814: 2b02 cmp r3, #2 800b816: d901 bls.n 800b81c { return HAL_TIMEOUT; 800b818: 2303 movs r3, #3 800b81a: e111 b.n 800ba40 while (__HAL_FLASH_GET_LATENCY() != FLatency) 800b81c: 4b8a ldr r3, [pc, #552] @ (800ba48 ) 800b81e: 681b ldr r3, [r3, #0] 800b820: f003 0307 and.w r3, r3, #7 800b824: 683a ldr r2, [r7, #0] 800b826: 429a cmp r2, r3 800b828: d1ef bne.n 800b80a } } } /*-------------------------- HCLK1 Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800b82a: 687b ldr r3, [r7, #4] 800b82c: 681b ldr r3, [r3, #0] 800b82e: f003 0302 and.w r3, r3, #2 800b832: 2b00 cmp r3, #0 800b834: d016 beq.n 800b864 { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); 800b836: 687b ldr r3, [r7, #4] 800b838: 689b ldr r3, [r3, #8] 800b83a: 4618 mov r0, r3 800b83c: f7ff faef bl 800ae1e /* HCLK1 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800b840: f7fa fe16 bl 8006470 800b844: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_HPRE() == 0U) 800b846: e008 b.n 800b85a { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800b848: f7fa fe12 bl 8006470 800b84c: 4602 mov r2, r0 800b84e: 68fb ldr r3, [r7, #12] 800b850: 1ad3 subs r3, r2, r3 800b852: 2b02 cmp r3, #2 800b854: d901 bls.n 800b85a { return HAL_TIMEOUT; 800b856: 2303 movs r3, #3 800b858: e0f2 b.n 800ba40 while (LL_RCC_IsActiveFlag_HPRE() == 0U) 800b85a: f7ff fbe9 bl 800b030 800b85e: 4603 mov r3, r0 800b860: 2b00 cmp r3, #0 800b862: d0f1 beq.n 800b848 } } } /*-------------------------- HCLK2 Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2) 800b864: 687b ldr r3, [r7, #4] 800b866: 681b ldr r3, [r3, #0] 800b868: f003 0320 and.w r3, r3, #32 800b86c: 2b00 cmp r3, #0 800b86e: d016 beq.n 800b89e { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider)); LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider); 800b870: 687b ldr r3, [r7, #4] 800b872: 695b ldr r3, [r3, #20] 800b874: 4618 mov r0, r3 800b876: f7ff fae6 bl 800ae46 /* HCLK2 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800b87a: f7fa fdf9 bl 8006470 800b87e: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) 800b880: e008 b.n 800b894 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800b882: f7fa fdf5 bl 8006470 800b886: 4602 mov r2, r0 800b888: 68fb ldr r3, [r7, #12] 800b88a: 1ad3 subs r3, r2, r3 800b88c: 2b02 cmp r3, #2 800b88e: d901 bls.n 800b894 { return HAL_TIMEOUT; 800b890: 2303 movs r3, #3 800b892: e0d5 b.n 800ba40 while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) 800b894: f7ff fbde bl 800b054 800b898: 4603 mov r3, r0 800b89a: 2b00 cmp r3, #0 800b89c: d0f1 beq.n 800b882 } } } /*-------------------------- HCLK4 Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK4) == RCC_CLOCKTYPE_HCLK4) 800b89e: 687b ldr r3, [r7, #4] 800b8a0: 681b ldr r3, [r3, #0] 800b8a2: f003 0340 and.w r3, r3, #64 @ 0x40 800b8a6: 2b00 cmp r3, #0 800b8a8: d016 beq.n 800b8d8 { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK4Divider)); LL_RCC_SetAHB4Prescaler(RCC_ClkInitStruct->AHBCLK4Divider); 800b8aa: 687b ldr r3, [r7, #4] 800b8ac: 699b ldr r3, [r3, #24] 800b8ae: 4618 mov r0, r3 800b8b0: f7ff fadf bl 800ae72 /* AHB shared prescaler flag when value applied */ tickstart = HAL_GetTick(); 800b8b4: f7fa fddc bl 8006470 800b8b8: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) 800b8ba: e008 b.n 800b8ce { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800b8bc: f7fa fdd8 bl 8006470 800b8c0: 4602 mov r2, r0 800b8c2: 68fb ldr r3, [r7, #12] 800b8c4: 1ad3 subs r3, r2, r3 800b8c6: 2b02 cmp r3, #2 800b8c8: d901 bls.n 800b8ce { return HAL_TIMEOUT; 800b8ca: 2303 movs r3, #3 800b8cc: e0b8 b.n 800ba40 while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) 800b8ce: f7ff fbd4 bl 800b07a 800b8d2: 4603 mov r3, r0 800b8d4: 2b00 cmp r3, #0 800b8d6: d0f1 beq.n 800b8bc } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800b8d8: 687b ldr r3, [r7, #4] 800b8da: 681b ldr r3, [r3, #0] 800b8dc: f003 0304 and.w r3, r3, #4 800b8e0: 2b00 cmp r3, #0 800b8e2: d016 beq.n 800b912 { assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); 800b8e4: 687b ldr r3, [r7, #4] 800b8e6: 68db ldr r3, [r3, #12] 800b8e8: 4618 mov r0, r3 800b8ea: f7ff fad9 bl 800aea0 /* APB1 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800b8ee: f7fa fdbf bl 8006470 800b8f2: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_PPRE1() == 0U) 800b8f4: e008 b.n 800b908 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800b8f6: f7fa fdbb bl 8006470 800b8fa: 4602 mov r2, r0 800b8fc: 68fb ldr r3, [r7, #12] 800b8fe: 1ad3 subs r3, r2, r3 800b900: 2b02 cmp r3, #2 800b902: d901 bls.n 800b908 { return HAL_TIMEOUT; 800b904: 2303 movs r3, #3 800b906: e09b b.n 800ba40 while (LL_RCC_IsActiveFlag_PPRE1() == 0U) 800b908: f7ff fbca bl 800b0a0 800b90c: 4603 mov r3, r0 800b90e: 2b00 cmp r3, #0 800b910: d0f1 beq.n 800b8f6 } } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800b912: 687b ldr r3, [r7, #4] 800b914: 681b ldr r3, [r3, #0] 800b916: f003 0308 and.w r3, r3, #8 800b91a: 2b00 cmp r3, #0 800b91c: d017 beq.n 800b94e { assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); 800b91e: 687b ldr r3, [r7, #4] 800b920: 691b ldr r3, [r3, #16] 800b922: 00db lsls r3, r3, #3 800b924: 4618 mov r0, r3 800b926: f7ff facf bl 800aec8 /* APB2 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800b92a: f7fa fda1 bl 8006470 800b92e: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_PPRE2() == 0U) 800b930: e008 b.n 800b944 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800b932: f7fa fd9d bl 8006470 800b936: 4602 mov r2, r0 800b938: 68fb ldr r3, [r7, #12] 800b93a: 1ad3 subs r3, r2, r3 800b93c: 2b02 cmp r3, #2 800b93e: d901 bls.n 800b944 { return HAL_TIMEOUT; 800b940: 2303 movs r3, #3 800b942: e07d b.n 800ba40 while (LL_RCC_IsActiveFlag_PPRE2() == 0U) 800b944: f7ff fbbe bl 800b0c4 800b948: 4603 mov r3, r0 800b94a: 2b00 cmp r3, #0 800b94c: d0f1 beq.n 800b932 } } } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800b94e: 687b ldr r3, [r7, #4] 800b950: 681b ldr r3, [r3, #0] 800b952: f003 0301 and.w r3, r3, #1 800b956: 2b00 cmp r3, #0 800b958: d043 beq.n 800b9e2 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800b95a: 687b ldr r3, [r7, #4] 800b95c: 685b ldr r3, [r3, #4] 800b95e: 2b02 cmp r3, #2 800b960: d106 bne.n 800b970 { /* Check the HSE ready flag */ if (LL_RCC_HSE_IsReady() == 0U) 800b962: f7ff f86f bl 800aa44 800b966: 4603 mov r3, r0 800b968: 2b00 cmp r3, #0 800b96a: d11e bne.n 800b9aa { return HAL_ERROR; 800b96c: 2301 movs r3, #1 800b96e: e067 b.n 800ba40 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800b970: 687b ldr r3, [r7, #4] 800b972: 685b ldr r3, [r3, #4] 800b974: 2b03 cmp r3, #3 800b976: d106 bne.n 800b986 { /* Check the PLL ready flag */ if (LL_RCC_PLL_IsReady() == 0U) 800b978: f7ff fb17 bl 800afaa 800b97c: 4603 mov r3, r0 800b97e: 2b00 cmp r3, #0 800b980: d113 bne.n 800b9aa { return HAL_ERROR; 800b982: 2301 movs r3, #1 800b984: e05c b.n 800ba40 } } /* MSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) 800b986: 687b ldr r3, [r7, #4] 800b988: 685b ldr r3, [r3, #4] 800b98a: 2b00 cmp r3, #0 800b98c: d106 bne.n 800b99c { /* Check the MSI ready flag */ if (LL_RCC_MSI_IsReady() == 0U) 800b98e: f7ff f9d7 bl 800ad40 800b992: 4603 mov r3, r0 800b994: 2b00 cmp r3, #0 800b996: d108 bne.n 800b9aa { return HAL_ERROR; 800b998: 2301 movs r3, #1 800b99a: e051 b.n 800ba40 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (LL_RCC_HSI_IsReady() == 0U) 800b99c: f7ff f882 bl 800aaa4 800b9a0: 4603 mov r3, r0 800b9a2: 2b00 cmp r3, #0 800b9a4: d101 bne.n 800b9aa { return HAL_ERROR; 800b9a6: 2301 movs r3, #1 800b9a8: e04a b.n 800ba40 } } /* apply system clock switch */ LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); 800b9aa: 687b ldr r3, [r7, #4] 800b9ac: 685b ldr r3, [r3, #4] 800b9ae: 4618 mov r0, r3 800b9b0: f7ff fa15 bl 800adde /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b9b4: f7fa fd5c bl 8006470 800b9b8: 60f8 str r0, [r7, #12] /* check system clock source switch status */ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800b9ba: e00a b.n 800b9d2 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800b9bc: f7fa fd58 bl 8006470 800b9c0: 4602 mov r2, r0 800b9c2: 68fb ldr r3, [r7, #12] 800b9c4: 1ad3 subs r3, r2, r3 800b9c6: f241 3288 movw r2, #5000 @ 0x1388 800b9ca: 4293 cmp r3, r2 800b9cc: d901 bls.n 800b9d2 { return HAL_TIMEOUT; 800b9ce: 2303 movs r3, #3 800b9d0: e036 b.n 800ba40 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800b9d2: f7ff fa18 bl 800ae06 800b9d6: 4602 mov r2, r0 800b9d8: 687b ldr r3, [r7, #4] 800b9da: 685b ldr r3, [r3, #4] 800b9dc: 009b lsls r3, r3, #2 800b9de: 429a cmp r2, r3 800b9e0: d1ec bne.n 800b9bc } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800b9e2: 4b19 ldr r3, [pc, #100] @ (800ba48 ) 800b9e4: 681b ldr r3, [r3, #0] 800b9e6: f003 0307 and.w r3, r3, #7 800b9ea: 683a ldr r2, [r7, #0] 800b9ec: 429a cmp r2, r3 800b9ee: d21b bcs.n 800ba28 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800b9f0: 4b15 ldr r3, [pc, #84] @ (800ba48 ) 800b9f2: 681b ldr r3, [r3, #0] 800b9f4: f023 0207 bic.w r2, r3, #7 800b9f8: 4913 ldr r1, [pc, #76] @ (800ba48 ) 800b9fa: 683b ldr r3, [r7, #0] 800b9fc: 4313 orrs r3, r2 800b9fe: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba00: f7fa fd36 bl 8006470 800ba04: 60f8 str r0, [r7, #12] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != FLatency) 800ba06: e008 b.n 800ba1a { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 800ba08: f7fa fd32 bl 8006470 800ba0c: 4602 mov r2, r0 800ba0e: 68fb ldr r3, [r7, #12] 800ba10: 1ad3 subs r3, r2, r3 800ba12: 2b02 cmp r3, #2 800ba14: d901 bls.n 800ba1a { return HAL_TIMEOUT; 800ba16: 2303 movs r3, #3 800ba18: e012 b.n 800ba40 while (__HAL_FLASH_GET_LATENCY() != FLatency) 800ba1a: 4b0b ldr r3, [pc, #44] @ (800ba48 ) 800ba1c: 681b ldr r3, [r3, #0] 800ba1e: f003 0307 and.w r3, r3, #7 800ba22: 683a ldr r2, [r7, #0] 800ba24: 429a cmp r2, r3 800ba26: d1ef bne.n 800ba08 } /*---------------------------------------------------------------------------*/ /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); 800ba28: f000 f87e bl 800bb28 800ba2c: 4603 mov r3, r0 800ba2e: 4a07 ldr r2, [pc, #28] @ (800ba4c ) 800ba30: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(HAL_GetTickPrio()); 800ba32: f7fa fd29 bl 8006488 800ba36: 4603 mov r3, r0 800ba38: 4618 mov r0, r3 800ba3a: f7fa fab1 bl 8005fa0 800ba3e: 4603 mov r3, r0 } 800ba40: 4618 mov r0, r3 800ba42: 3710 adds r7, #16 800ba44: 46bd mov sp, r7 800ba46: bd80 pop {r7, pc} 800ba48: 58004000 .word 0x58004000 800ba4c: 2000000c .word 0x2000000c 0800ba50 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800ba50: b590 push {r4, r7, lr} 800ba52: b085 sub sp, #20 800ba54: af00 add r7, sp, #0 uint32_t pllsource; uint32_t sysclockfreq; uint32_t pllinputfreq; const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800ba56: f7ff f9d6 bl 800ae06 800ba5a: 6078 str r0, [r7, #4] if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) 800ba5c: 687b ldr r3, [r7, #4] 800ba5e: 2b00 cmp r3, #0 800ba60: d10a bne.n 800ba78 { /* Retrieve MSI frequency range in HZ*/ /* MSI used as system clock source */ sysclockfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); 800ba62: f7ff f992 bl 800ad8a 800ba66: 4603 mov r3, r0 800ba68: 091b lsrs r3, r3, #4 800ba6a: f003 030f and.w r3, r3, #15 800ba6e: 4a2b ldr r2, [pc, #172] @ (800bb1c ) 800ba70: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800ba74: 60fb str r3, [r7, #12] 800ba76: e04b b.n 800bb10 } else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) 800ba78: 687b ldr r3, [r7, #4] 800ba7a: 2b04 cmp r3, #4 800ba7c: d102 bne.n 800ba84 { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; 800ba7e: 4b28 ldr r3, [pc, #160] @ (800bb20 ) 800ba80: 60fb str r3, [r7, #12] 800ba82: e045 b.n 800bb10 } else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) 800ba84: 687b ldr r3, [r7, #4] 800ba86: 2b08 cmp r3, #8 800ba88: d10a bne.n 800baa0 { /* HSE used as system clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) 800ba8a: f7fe ffab bl 800a9e4 800ba8e: 4603 mov r3, r0 800ba90: 2b01 cmp r3, #1 800ba92: d102 bne.n 800ba9a { sysclockfreq = HSE_VALUE / 2U; 800ba94: 4b22 ldr r3, [pc, #136] @ (800bb20 ) 800ba96: 60fb str r3, [r7, #12] 800ba98: e03a b.n 800bb10 } else { sysclockfreq = HSE_VALUE; 800ba9a: 4b22 ldr r3, [pc, #136] @ (800bb24 ) 800ba9c: 60fb str r3, [r7, #12] 800ba9e: e037 b.n 800bb10 } } else { /* PLL used as system clock source */ pllsource = LL_RCC_PLL_GetMainSource(); 800baa0: f7ff faba bl 800b018 800baa4: 6038 str r0, [r7, #0] switch (pllsource) 800baa6: 683b ldr r3, [r7, #0] 800baa8: 2b02 cmp r3, #2 800baaa: d003 beq.n 800bab4 800baac: 683b ldr r3, [r7, #0] 800baae: 2b03 cmp r3, #3 800bab0: d003 beq.n 800baba 800bab2: e00d b.n 800bad0 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; 800bab4: 4b1a ldr r3, [pc, #104] @ (800bb20 ) 800bab6: 60bb str r3, [r7, #8] break; 800bab8: e015 b.n 800bae6 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) 800baba: f7fe ff93 bl 800a9e4 800babe: 4603 mov r3, r0 800bac0: 2b01 cmp r3, #1 800bac2: d102 bne.n 800baca { pllinputfreq = HSE_VALUE / 2U; 800bac4: 4b16 ldr r3, [pc, #88] @ (800bb20 ) 800bac6: 60bb str r3, [r7, #8] } else { pllinputfreq = HSE_VALUE; } break; 800bac8: e00d b.n 800bae6 pllinputfreq = HSE_VALUE; 800baca: 4b16 ldr r3, [pc, #88] @ (800bb24 ) 800bacc: 60bb str r3, [r7, #8] break; 800bace: e00a b.n 800bae6 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); 800bad0: f7ff f95b bl 800ad8a 800bad4: 4603 mov r3, r0 800bad6: 091b lsrs r3, r3, #4 800bad8: f003 030f and.w r3, r3, #15 800badc: 4a0f ldr r2, [pc, #60] @ (800bb1c ) 800bade: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800bae2: 60bb str r3, [r7, #8] break; 800bae4: bf00 nop } sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), 800bae6: f7ff fa72 bl 800afce 800baea: 4602 mov r2, r0 800baec: 68bb ldr r3, [r7, #8] 800baee: fb03 f402 mul.w r4, r3, r2 800baf2: f7ff fa85 bl 800b000 800baf6: 4603 mov r3, r0 800baf8: 091b lsrs r3, r3, #4 800bafa: 3301 adds r3, #1 800bafc: fbb4 f4f3 udiv r4, r4, r3 800bb00: f7ff fa72 bl 800afe8 800bb04: 4603 mov r3, r0 800bb06: 0f5b lsrs r3, r3, #29 800bb08: 3301 adds r3, #1 800bb0a: fbb4 f3f3 udiv r3, r4, r3 800bb0e: 60fb str r3, [r7, #12] LL_RCC_PLL_GetR()); } return sysclockfreq; 800bb10: 68fb ldr r3, [r7, #12] } 800bb12: 4618 mov r0, r3 800bb14: 3714 adds r7, #20 800bb16: 46bd mov sp, r7 800bb18: bd90 pop {r4, r7, pc} 800bb1a: bf00 nop 800bb1c: 0801dc6c .word 0x0801dc6c 800bb20: 00f42400 .word 0x00f42400 800bb24: 01e84800 .word 0x01e84800 0800bb28 : /** * @brief Return the HCLK frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800bb28: b598 push {r3, r4, r7, lr} 800bb2a: af00 add r7, sp, #0 /* Get SysClock and Compute HCLK1 frequency ---------------------------*/ return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); 800bb2c: f7ff ff90 bl 800ba50 800bb30: 4604 mov r4, r0 800bb32: f7ff f9dd bl 800aef0 800bb36: 4603 mov r3, r0 800bb38: 091b lsrs r3, r3, #4 800bb3a: f003 030f and.w r3, r3, #15 800bb3e: 4a03 ldr r2, [pc, #12] @ (800bb4c ) 800bb40: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800bb44: fbb4 f3f3 udiv r3, r4, r3 } 800bb48: 4618 mov r0, r3 800bb4a: bd98 pop {r3, r4, r7, pc} 800bb4c: 0801dc0c .word 0x0801dc0c 0800bb50 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800bb50: b598 push {r3, r4, r7, lr} 800bb52: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler()))); 800bb54: f7ff ffe8 bl 800bb28 800bb58: 4604 mov r4, r0 800bb5a: f7ff f9fc bl 800af56 800bb5e: 4603 mov r3, r0 800bb60: 0adb lsrs r3, r3, #11 800bb62: f003 0307 and.w r3, r3, #7 800bb66: 4a04 ldr r2, [pc, #16] @ (800bb78 ) 800bb68: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800bb6c: f003 031f and.w r3, r3, #31 800bb70: fa24 f303 lsr.w r3, r4, r3 } 800bb74: 4618 mov r0, r3 800bb76: bd98 pop {r3, r4, r7, pc} 800bb78: 0801dc4c .word 0x0801dc4c 0800bb7c : * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800bb7c: b580 push {r7, lr} 800bb7e: b082 sub sp, #8 800bb80: af00 add r7, sp, #0 800bb82: 6078 str r0, [r7, #4] 800bb84: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(RCC_ClkInitStruct != (void *)NULL); assert_param(pFLatency != (void *)NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | 800bb86: 687b ldr r3, [r7, #4] 800bb88: 226f movs r2, #111 @ 0x6f 800bb8a: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4); /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = LL_RCC_GetSysClkSource(); 800bb8c: f7ff f93b bl 800ae06 800bb90: 4602 mov r2, r0 800bb92: 687b ldr r3, [r7, #4] 800bb94: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = LL_RCC_GetAHBPrescaler(); 800bb96: f7ff f9ab bl 800aef0 800bb9a: 4602 mov r2, r0 800bb9c: 687b ldr r3, [r7, #4] 800bb9e: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = LL_RCC_GetAPB1Prescaler(); 800bba0: f7ff f9cd bl 800af3e 800bba4: 4602 mov r2, r0 800bba6: 687b ldr r3, [r7, #4] 800bba8: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = LL_RCC_GetAPB2Prescaler(); 800bbaa: f7ff f9d4 bl 800af56 800bbae: 4602 mov r2, r0 800bbb0: 687b ldr r3, [r7, #4] 800bbb2: 611a str r2, [r3, #16] /* Get the AHBCLK2Divider configuration ------------------------------------*/ RCC_ClkInitStruct->AHBCLK2Divider = LL_C2_RCC_GetAHBPrescaler(); 800bbb4: f7ff f9a8 bl 800af08 800bbb8: 4602 mov r2, r0 800bbba: 687b ldr r3, [r7, #4] 800bbbc: 615a str r2, [r3, #20] /* Get the AHBCLK4Divider configuration ------------------------------------*/ RCC_ClkInitStruct->AHBCLK4Divider = LL_RCC_GetAHB4Prescaler(); 800bbbe: f7ff f9b0 bl 800af22 800bbc2: 4602 mov r2, r0 800bbc4: 687b ldr r3, [r7, #4] 800bbc6: 619a str r2, [r3, #24] /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = __HAL_FLASH_GET_LATENCY(); 800bbc8: 4b04 ldr r3, [pc, #16] @ (800bbdc ) 800bbca: 681b ldr r3, [r3, #0] 800bbcc: f003 0207 and.w r2, r3, #7 800bbd0: 683b ldr r3, [r7, #0] 800bbd2: 601a str r2, [r3, #0] } 800bbd4: bf00 nop 800bbd6: 3708 adds r7, #8 800bbd8: 46bd mov sp, r7 800bbda: bd80 pop {r7, pc} 800bbdc: 58004000 .word 0x58004000 0800bbe0 : voltage range. * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) { 800bbe0: b590 push {r4, r7, lr} 800bbe2: b085 sub sp, #20 800bbe4: af00 add r7, sp, #0 800bbe6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range)); /* MSI frequency range in Hz */ if (MSI_Range > RCC_MSIRANGE_11) 800bbe8: 687b ldr r3, [r7, #4] 800bbea: 2bb0 cmp r3, #176 @ 0xb0 800bbec: d903 bls.n 800bbf6 { msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11); 800bbee: 4b15 ldr r3, [pc, #84] @ (800bc44 ) 800bbf0: 6adb ldr r3, [r3, #44] @ 0x2c 800bbf2: 60fb str r3, [r7, #12] 800bbf4: e007 b.n 800bc06 } else { msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range); 800bbf6: 687b ldr r3, [r7, #4] 800bbf8: 091b lsrs r3, r3, #4 800bbfa: f003 030f and.w r3, r3, #15 800bbfe: 4a11 ldr r2, [pc, #68] @ (800bc44 ) 800bc00: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800bc04: 60fb str r3, [r7, #12] } flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler()); 800bc06: f7ff f98c bl 800af22 800bc0a: 4603 mov r3, r0 800bc0c: 091b lsrs r3, r3, #4 800bc0e: f003 030f and.w r3, r3, #15 800bc12: 4a0d ldr r2, [pc, #52] @ (800bc48 ) 800bc14: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800bc18: 68fa ldr r2, [r7, #12] 800bc1a: fbb2 f3f3 udiv r3, r2, r3 800bc1e: 60bb str r3, [r7, #8] #if defined(PWR_CR1_VOS) return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); 800bc20: 68bb ldr r3, [r7, #8] 800bc22: 4a0a ldr r2, [pc, #40] @ (800bc4c ) 800bc24: fba2 2303 umull r2, r3, r2, r3 800bc28: 0c9c lsrs r4, r3, #18 800bc2a: f7fe febd bl 800a9a8 800bc2e: 4603 mov r3, r0 800bc30: 4619 mov r1, r3 800bc32: 4620 mov r0, r4 800bc34: f000 f80c bl 800bc50 800bc38: 4603 mov r3, r0 #else return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1); #endif /* PWR_CR1_VOS */ } 800bc3a: 4618 mov r0, r3 800bc3c: 3714 adds r7, #20 800bc3e: 46bd mov sp, r7 800bc40: bd90 pop {r4, r7, pc} 800bc42: bf00 nop 800bc44: 0801dc6c .word 0x0801dc6c 800bc48: 0801dc0c .word 0x0801dc0c 800bc4c: 431bde83 .word 0x431bde83 0800bc50 : * @param Flash_ClkSrcFreq Flash Clock Source (in MHz) * @param VCORE_Voltage Current Vcore voltage (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2) * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) { 800bc50: b590 push {r4, r7, lr} 800bc52: b093 sub sp, #76 @ 0x4c 800bc54: af00 add r7, sp, #0 800bc56: 6078 str r0, [r7, #4] 800bc58: 6039 str r1, [r7, #0] /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL}; 800bc5a: 4b37 ldr r3, [pc, #220] @ (800bd38 ) 800bc5c: f107 0428 add.w r4, r7, #40 @ 0x28 800bc60: cb0f ldmia r3, {r0, r1, r2, r3} 800bc62: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(PWR_CR1_VOS) /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL}; 800bc66: 4a35 ldr r2, [pc, #212] @ (800bd3c ) 800bc68: f107 031c add.w r3, r7, #28 800bc6c: ca07 ldmia r2, {r0, r1, r2} 800bc6e: e883 0007 stmia.w r3, {r0, r1, r2} #endif /* PWR_CR1_VOS */ /* Flash Latency range */ const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3}; 800bc72: 4b33 ldr r3, [pc, #204] @ (800bd40 ) 800bc74: f107 040c add.w r4, r7, #12 800bc78: cb0f ldmia r3, {r0, r1, r2, r3} 800bc7a: e884 000f stmia.w r4, {r0, r1, r2, r3} uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ 800bc7e: 2300 movs r3, #0 800bc80: 647b str r3, [r7, #68] @ 0x44 uint32_t tickstart; #if defined(PWR_CR1_VOS) if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) 800bc82: 683b ldr r3, [r7, #0] 800bc84: f5b3 7f00 cmp.w r3, #512 @ 0x200 800bc88: d11a bne.n 800bcc0 { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) 800bc8a: 2300 movs r3, #0 800bc8c: 643b str r3, [r7, #64] @ 0x40 800bc8e: e013 b.n 800bcb8 { if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) 800bc90: 6c3b ldr r3, [r7, #64] @ 0x40 800bc92: 009b lsls r3, r3, #2 800bc94: 3348 adds r3, #72 @ 0x48 800bc96: 443b add r3, r7 800bc98: f853 3c20 ldr.w r3, [r3, #-32] 800bc9c: 687a ldr r2, [r7, #4] 800bc9e: 429a cmp r2, r3 800bca0: d807 bhi.n 800bcb2 { latency = FLASH_LATENCY_RANGE[index]; 800bca2: 6c3b ldr r3, [r7, #64] @ 0x40 800bca4: 009b lsls r3, r3, #2 800bca6: 3348 adds r3, #72 @ 0x48 800bca8: 443b add r3, r7 800bcaa: f853 3c3c ldr.w r3, [r3, #-60] 800bcae: 647b str r3, [r7, #68] @ 0x44 break; 800bcb0: e020 b.n 800bcf4 for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) 800bcb2: 6c3b ldr r3, [r7, #64] @ 0x40 800bcb4: 3301 adds r3, #1 800bcb6: 643b str r3, [r7, #64] @ 0x40 800bcb8: 6c3b ldr r3, [r7, #64] @ 0x40 800bcba: 2b03 cmp r3, #3 800bcbc: d9e8 bls.n 800bc90 800bcbe: e019 b.n 800bcf4 } } } else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) 800bcc0: 2300 movs r3, #0 800bcc2: 63fb str r3, [r7, #60] @ 0x3c 800bcc4: e013 b.n 800bcee { if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) 800bcc6: 6bfb ldr r3, [r7, #60] @ 0x3c 800bcc8: 009b lsls r3, r3, #2 800bcca: 3348 adds r3, #72 @ 0x48 800bccc: 443b add r3, r7 800bcce: f853 3c2c ldr.w r3, [r3, #-44] 800bcd2: 687a ldr r2, [r7, #4] 800bcd4: 429a cmp r2, r3 800bcd6: d807 bhi.n 800bce8 { latency = FLASH_LATENCY_RANGE[index]; 800bcd8: 6bfb ldr r3, [r7, #60] @ 0x3c 800bcda: 009b lsls r3, r3, #2 800bcdc: 3348 adds r3, #72 @ 0x48 800bcde: 443b add r3, r7 800bce0: f853 3c3c ldr.w r3, [r3, #-60] 800bce4: 647b str r3, [r7, #68] @ 0x44 break; 800bce6: e005 b.n 800bcf4 for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) 800bce8: 6bfb ldr r3, [r7, #60] @ 0x3c 800bcea: 3301 adds r3, #1 800bcec: 63fb str r3, [r7, #60] @ 0x3c 800bcee: 6bfb ldr r3, [r7, #60] @ 0x3c 800bcf0: 2b02 cmp r3, #2 800bcf2: d9e8 bls.n 800bcc6 break; } } #endif /* PWR_CR1_VOS */ __HAL_FLASH_SET_LATENCY(latency); 800bcf4: 4b13 ldr r3, [pc, #76] @ (800bd44 ) 800bcf6: 681b ldr r3, [r3, #0] 800bcf8: f023 0207 bic.w r2, r3, #7 800bcfc: 4911 ldr r1, [pc, #68] @ (800bd44 ) 800bcfe: 6c7b ldr r3, [r7, #68] @ 0x44 800bd00: 4313 orrs r3, r2 800bd02: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd04: f7fa fbb4 bl 8006470 800bd08: 63b8 str r0, [r7, #56] @ 0x38 /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != latency) 800bd0a: e008 b.n 800bd1e { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 800bd0c: f7fa fbb0 bl 8006470 800bd10: 4602 mov r2, r0 800bd12: 6bbb ldr r3, [r7, #56] @ 0x38 800bd14: 1ad3 subs r3, r2, r3 800bd16: 2b02 cmp r3, #2 800bd18: d901 bls.n 800bd1e { return HAL_TIMEOUT; 800bd1a: 2303 movs r3, #3 800bd1c: e007 b.n 800bd2e while (__HAL_FLASH_GET_LATENCY() != latency) 800bd1e: 4b09 ldr r3, [pc, #36] @ (800bd44 ) 800bd20: 681b ldr r3, [r3, #0] 800bd22: f003 0307 and.w r3, r3, #7 800bd26: 6c7a ldr r2, [r7, #68] @ 0x44 800bd28: 429a cmp r2, r3 800bd2a: d1ef bne.n 800bd0c } } return HAL_OK; 800bd2c: 2300 movs r3, #0 } 800bd2e: 4618 mov r0, r3 800bd30: 374c adds r7, #76 @ 0x4c 800bd32: 46bd mov sp, r7 800bd34: bd90 pop {r4, r7, pc} 800bd36: bf00 nop 800bd38: 0801d990 .word 0x0801d990 800bd3c: 0801d9a0 .word 0x0801d9a0 800bd40: 0801d9ac .word 0x0801d9ac 800bd44: 58004000 .word 0x58004000 0800bd48 : { 800bd48: b480 push {r7} 800bd4a: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL); 800bd4c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bd50: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800bd54: f003 0301 and.w r3, r3, #1 800bd58: 2b01 cmp r3, #1 800bd5a: d101 bne.n 800bd60 800bd5c: 2301 movs r3, #1 800bd5e: e000 b.n 800bd62 800bd60: 2300 movs r3, #0 } 800bd62: 4618 mov r0, r3 800bd64: 46bd mov sp, r7 800bd66: f85d 7b04 ldr.w r7, [sp], #4 800bd6a: 4770 bx lr 0800bd6c : { 800bd6c: b480 push {r7} 800bd6e: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); 800bd70: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bd74: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800bd78: f003 0302 and.w r3, r3, #2 800bd7c: 2b02 cmp r3, #2 800bd7e: d101 bne.n 800bd84 800bd80: 2301 movs r3, #1 800bd82: e000 b.n 800bd86 800bd84: 2300 movs r3, #0 } 800bd86: 4618 mov r0, r3 800bd88: 46bd mov sp, r7 800bd8a: f85d 7b04 ldr.w r7, [sp], #4 800bd8e: 4770 bx lr 0800bd90 : { 800bd90: b480 push {r7} 800bd92: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); 800bd94: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bd98: 681b ldr r3, [r3, #0] 800bd9a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800bd9e: f043 0304 orr.w r3, r3, #4 800bda2: 6013 str r3, [r2, #0] } 800bda4: bf00 nop 800bda6: 46bd mov sp, r7 800bda8: f85d 7b04 ldr.w r7, [sp], #4 800bdac: 4770 bx lr 0800bdae : { 800bdae: b480 push {r7} 800bdb0: b083 sub sp, #12 800bdb2: af00 add r7, sp, #0 800bdb4: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source); 800bdb6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bdba: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800bdbe: f423 4240 bic.w r2, r3, #49152 @ 0xc000 800bdc2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bdc6: 687b ldr r3, [r7, #4] 800bdc8: 4313 orrs r3, r2 800bdca: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } 800bdce: bf00 nop 800bdd0: 370c adds r7, #12 800bdd2: 46bd mov sp, r7 800bdd4: f85d 7b04 ldr.w r7, [sp], #4 800bdd8: 4770 bx lr 0800bdda : { 800bdda: b480 push {r7} 800bddc: b083 sub sp, #12 800bdde: af00 add r7, sp, #0 800bde0: 6078 str r0, [r7, #4] MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource); 800bde2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bde6: 6a5b ldr r3, [r3, #36] @ 0x24 800bde8: f023 0203 bic.w r2, r3, #3 800bdec: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bdf0: 687b ldr r3, [r7, #4] 800bdf2: 4313 orrs r3, r2 800bdf4: 624b str r3, [r1, #36] @ 0x24 } 800bdf6: bf00 nop 800bdf8: 370c adds r7, #12 800bdfa: 46bd mov sp, r7 800bdfc: f85d 7b04 ldr.w r7, [sp], #4 800be00: 4770 bx lr 0800be02 : { 800be02: b480 push {r7} 800be04: b083 sub sp, #12 800be06: af00 add r7, sp, #0 800be08: 6078 str r0, [r7, #4] MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler); 800be0a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800be0e: 6a5b ldr r3, [r3, #36] @ 0x24 800be10: f023 0230 bic.w r2, r3, #48 @ 0x30 800be14: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800be18: 687b ldr r3, [r7, #4] 800be1a: 4313 orrs r3, r2 800be1c: 624b str r3, [r1, #36] @ 0x24 } 800be1e: bf00 nop 800be20: 370c adds r7, #12 800be22: 46bd mov sp, r7 800be24: f85d 7b04 ldr.w r7, [sp], #4 800be28: 4770 bx lr 0800be2a : { 800be2a: b480 push {r7} 800be2c: b083 sub sp, #12 800be2e: af00 add r7, sp, #0 800be30: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource); 800be32: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800be36: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800be3a: f023 0203 bic.w r2, r3, #3 800be3e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800be42: 687b ldr r3, [r7, #4] 800be44: 4313 orrs r3, r2 800be46: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800be4a: bf00 nop 800be4c: 370c adds r7, #12 800be4e: 46bd mov sp, r7 800be50: f85d 7b04 ldr.w r7, [sp], #4 800be54: 4770 bx lr 0800be56 : { 800be56: b480 push {r7} 800be58: b083 sub sp, #12 800be5a: af00 add r7, sp, #0 800be5c: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); 800be5e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800be62: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800be66: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800be6a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800be6e: 687b ldr r3, [r7, #4] 800be70: 4313 orrs r3, r2 800be72: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800be76: bf00 nop 800be78: 370c adds r7, #12 800be7a: 46bd mov sp, r7 800be7c: f85d 7b04 ldr.w r7, [sp], #4 800be80: 4770 bx lr 0800be82 : { 800be82: b480 push {r7} 800be84: b083 sub sp, #12 800be86: af00 add r7, sp, #0 800be88: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); 800be8a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800be8e: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800be92: 687b ldr r3, [r7, #4] 800be94: 091b lsrs r3, r3, #4 800be96: f403 237f and.w r3, r3, #1044480 @ 0xff000 800be9a: 43db mvns r3, r3 800be9c: 401a ands r2, r3 800be9e: 687b ldr r3, [r7, #4] 800bea0: 011b lsls r3, r3, #4 800bea2: f403 237f and.w r3, r3, #1044480 @ 0xff000 800bea6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800beaa: 4313 orrs r3, r2 800beac: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800beb0: bf00 nop 800beb2: 370c adds r7, #12 800beb4: 46bd mov sp, r7 800beb6: f85d 7b04 ldr.w r7, [sp], #4 800beba: 4770 bx lr 0800bebc : { 800bebc: b480 push {r7} 800bebe: b083 sub sp, #12 800bec0: af00 add r7, sp, #0 800bec2: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); 800bec4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bec8: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800becc: 687b ldr r3, [r7, #4] 800bece: 0c1b lsrs r3, r3, #16 800bed0: 041b lsls r3, r3, #16 800bed2: 43db mvns r3, r3 800bed4: 401a ands r2, r3 800bed6: 687b ldr r3, [r7, #4] 800bed8: 041b lsls r3, r3, #16 800beda: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bede: 4313 orrs r3, r2 800bee0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800bee4: bf00 nop 800bee6: 370c adds r7, #12 800bee8: 46bd mov sp, r7 800beea: f85d 7b04 ldr.w r7, [sp], #4 800beee: 4770 bx lr 0800bef0 : { 800bef0: b480 push {r7} 800bef2: b083 sub sp, #12 800bef4: af00 add r7, sp, #0 800bef6: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource); 800bef8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800befc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800bf00: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 800bf04: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bf08: 687b ldr r3, [r7, #4] 800bf0a: 4313 orrs r3, r2 800bf0c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800bf10: bf00 nop 800bf12: 370c adds r7, #12 800bf14: 46bd mov sp, r7 800bf16: f85d 7b04 ldr.w r7, [sp], #4 800bf1a: 4770 bx lr 0800bf1c : { 800bf1c: b480 push {r7} 800bf1e: b083 sub sp, #12 800bf20: af00 add r7, sp, #0 800bf22: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); 800bf24: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bf28: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800bf2c: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000 800bf30: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bf34: 687b ldr r3, [r7, #4] 800bf36: 4313 orrs r3, r2 800bf38: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800bf3c: bf00 nop 800bf3e: 370c adds r7, #12 800bf40: 46bd mov sp, r7 800bf42: f85d 7b04 ldr.w r7, [sp], #4 800bf46: 4770 bx lr 0800bf48 : { 800bf48: b480 push {r7} 800bf4a: b083 sub sp, #12 800bf4c: af00 add r7, sp, #0 800bf4e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource); 800bf50: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bf54: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800bf58: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 800bf5c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bf60: 687b ldr r3, [r7, #4] 800bf62: 4313 orrs r3, r2 800bf64: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800bf68: bf00 nop 800bf6a: 370c adds r7, #12 800bf6c: 46bd mov sp, r7 800bf6e: f85d 7b04 ldr.w r7, [sp], #4 800bf72: 4770 bx lr 0800bf74 : { 800bf74: b580 push {r7, lr} 800bf76: b082 sub sp, #8 800bf78: af00 add r7, sp, #0 800bf7a: 6078 str r0, [r7, #4] LL_RCC_SetCLK48ClockSource(USBxSource); 800bf7c: 6878 ldr r0, [r7, #4] 800bf7e: f7ff ffe3 bl 800bf48 } 800bf82: bf00 nop 800bf84: 3708 adds r7, #8 800bf86: 46bd mov sp, r7 800bf88: bd80 pop {r7, pc} 0800bf8a : { 800bf8a: b480 push {r7} 800bf8c: b083 sub sp, #12 800bf8e: af00 add r7, sp, #0 800bf90: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); 800bf92: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bf96: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800bf9a: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 800bf9e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bfa2: 687b ldr r3, [r7, #4] 800bfa4: 4313 orrs r3, r2 800bfa6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800bfaa: bf00 nop 800bfac: 370c adds r7, #12 800bfae: 46bd mov sp, r7 800bfb0: f85d 7b04 ldr.w r7, [sp], #4 800bfb4: 4770 bx lr 0800bfb6 : { 800bfb6: b480 push {r7} 800bfb8: b083 sub sp, #12 800bfba: af00 add r7, sp, #0 800bfbc: 6078 str r0, [r7, #4] MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 800bfbe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bfc2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800bfc6: f423 7240 bic.w r2, r3, #768 @ 0x300 800bfca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bfce: 687b ldr r3, [r7, #4] 800bfd0: 4313 orrs r3, r2 800bfd2: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 800bfd6: bf00 nop 800bfd8: 370c adds r7, #12 800bfda: 46bd mov sp, r7 800bfdc: f85d 7b04 ldr.w r7, [sp], #4 800bfe0: 4770 bx lr 0800bfe2 : { 800bfe2: b480 push {r7} 800bfe4: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 800bfe6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bfea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800bfee: f403 7340 and.w r3, r3, #768 @ 0x300 } 800bff2: 4618 mov r0, r3 800bff4: 46bd mov sp, r7 800bff6: f85d 7b04 ldr.w r7, [sp], #4 800bffa: 4770 bx lr 0800bffc : { 800bffc: b480 push {r7} 800bffe: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 800c000: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c004: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c008: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c00c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c010: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800c014: bf00 nop 800c016: 46bd mov sp, r7 800c018: f85d 7b04 ldr.w r7, [sp], #4 800c01c: 4770 bx lr 0800c01e : { 800c01e: b480 push {r7} 800c020: af00 add r7, sp, #0 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 800c022: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c026: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c02a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c02e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800c032: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800c036: bf00 nop 800c038: 46bd mov sp, r7 800c03a: f85d 7b04 ldr.w r7, [sp], #4 800c03e: 4770 bx lr 0800c040 : { 800c040: b480 push {r7} 800c042: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 800c044: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c048: 681b ldr r3, [r3, #0] 800c04a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c04e: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800c052: 6013 str r3, [r2, #0] } 800c054: bf00 nop 800c056: 46bd mov sp, r7 800c058: f85d 7b04 ldr.w r7, [sp], #4 800c05c: 4770 bx lr 0800c05e : { 800c05e: b480 push {r7} 800c060: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 800c062: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c066: 681b ldr r3, [r3, #0] 800c068: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c06c: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800c070: 6013 str r3, [r2, #0] } 800c072: bf00 nop 800c074: 46bd mov sp, r7 800c076: f85d 7b04 ldr.w r7, [sp], #4 800c07a: 4770 bx lr 0800c07c : { 800c07c: b480 push {r7} 800c07e: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL); 800c080: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c084: 681b ldr r3, [r3, #0] 800c086: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800c08a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800c08e: d101 bne.n 800c094 800c090: 2301 movs r3, #1 800c092: e000 b.n 800c096 800c094: 2300 movs r3, #0 } 800c096: 4618 mov r0, r3 800c098: 46bd mov sp, r7 800c09a: f85d 7b04 ldr.w r7, [sp], #4 800c09e: 4770 bx lr 0800c0a0 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800c0a0: b580 push {r7, lr} 800c0a2: b088 sub sp, #32 800c0a4: af00 add r7, sp, #0 800c0a6: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800c0a8: 2300 movs r3, #0 800c0aa: 77fb strb r3, [r7, #31] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800c0ac: 2300 movs r3, #0 800c0ae: 77bb strb r3, [r7, #30] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); #if defined(SAI1) /*-------------------------- SAI1 clock source configuration ---------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) 800c0b0: 687b ldr r3, [r7, #4] 800c0b2: 681b ldr r3, [r3, #0] 800c0b4: f003 0340 and.w r3, r3, #64 @ 0x40 800c0b8: 2b00 cmp r3, #0 800c0ba: d034 beq.n 800c126 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); switch (PeriphClkInit->Sai1ClockSelection) 800c0bc: 687b ldr r3, [r7, #4] 800c0be: 6b1b ldr r3, [r3, #48] @ 0x30 800c0c0: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 800c0c4: d021 beq.n 800c10a 800c0c6: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 800c0ca: d81b bhi.n 800c104 800c0cc: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c0d0: d01d beq.n 800c10e 800c0d2: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c0d6: d815 bhi.n 800c104 800c0d8: 2b00 cmp r3, #0 800c0da: d00b beq.n 800c0f4 800c0dc: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c0e0: d110 bne.n 800c104 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1 */ /* Enable SAI1 Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI1CLK); 800c0e2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c0e6: 68db ldr r3, [r3, #12] 800c0e8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c0ec: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c0f0: 60d3 str r3, [r2, #12] /* SAI1 clock source config set later after clock selection check */ break; 800c0f2: e00d b.n 800c110 case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */ /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1)); 800c0f4: 687b ldr r3, [r7, #4] 800c0f6: 3304 adds r3, #4 800c0f8: 4618 mov r0, r3 800c0fa: f000 f94d bl 800c398 800c0fe: 4603 mov r3, r0 800c100: 77fb strb r3, [r7, #31] /* SAI1 clock source config set later after clock selection check */ break; 800c102: e005 b.n 800c110 case RCC_SAI1CLKSOURCE_HSI: break; default: ret = HAL_ERROR; 800c104: 2301 movs r3, #1 800c106: 77fb strb r3, [r7, #31] break; 800c108: e002 b.n 800c110 break; 800c10a: bf00 nop 800c10c: e000 b.n 800c110 break; 800c10e: bf00 nop } if (ret == HAL_OK) 800c110: 7ffb ldrb r3, [r7, #31] 800c112: 2b00 cmp r3, #0 800c114: d105 bne.n 800c122 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800c116: 687b ldr r3, [r7, #4] 800c118: 6b1b ldr r3, [r3, #48] @ 0x30 800c11a: 4618 mov r0, r3 800c11c: f7ff fee8 bl 800bef0 800c120: e001 b.n 800c126 } else { /* set overall return value */ status = ret; 800c122: 7ffb ldrb r3, [r7, #31] 800c124: 77bb strb r3, [r7, #30] } } #endif /* SAI1 */ /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800c126: 687b ldr r3, [r7, #4] 800c128: 681b ldr r3, [r3, #0] 800c12a: f403 6300 and.w r3, r3, #2048 @ 0x800 800c12e: 2b00 cmp r3, #0 800c130: d046 beq.n 800c1c0 { uint32_t rtcclocksource = LL_RCC_GetRTCClockSource(); 800c132: f7ff ff56 bl 800bfe2 800c136: 61b8 str r0, [r7, #24] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Configure the clock source only if a different source is expected */ if (rtcclocksource != PeriphClkInit->RTCClockSelection) 800c138: 687b ldr r3, [r7, #4] 800c13a: 6c1b ldr r3, [r3, #64] @ 0x40 800c13c: 69ba ldr r2, [r7, #24] 800c13e: 429a cmp r2, r3 800c140: d03c beq.n 800c1bc { /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); 800c142: f7fe fc21 bl 800a988 /* If a clock source is not yet selected */ if (rtcclocksource == RCC_RTCCLKSOURCE_NONE) 800c146: 69bb ldr r3, [r7, #24] 800c148: 2b00 cmp r3, #0 800c14a: d105 bne.n 800c158 { /* Directly set the configuration of the clock source selection */ LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection); 800c14c: 687b ldr r3, [r7, #4] 800c14e: 6c1b ldr r3, [r3, #64] @ 0x40 800c150: 4618 mov r0, r3 800c152: f7ff ff30 bl 800bfb6 800c156: e02e b.n 800c1b6 } else /* A clock source is already selected */ { /* Store the content of BDCR register before the reset of Backup Domain */ uint32_t bdcr = LL_RCC_ReadReg(BDCR); 800c158: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c15c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c160: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ LL_RCC_ForceBackupDomainReset(); 800c162: f7ff ff4b bl 800bffc LL_RCC_ReleaseBackupDomainReset(); 800c166: f7ff ff5a bl 800c01e /* Set the value of the clock source selection */ MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection); 800c16a: 697b ldr r3, [r7, #20] 800c16c: f423 7240 bic.w r2, r3, #768 @ 0x300 800c170: 687b ldr r3, [r7, #4] 800c172: 6c1b ldr r3, [r3, #64] @ 0x40 800c174: 4313 orrs r3, r2 800c176: 617b str r3, [r7, #20] /* Restore the content of BDCR register */ LL_RCC_WriteReg(BDCR, bdcr); 800c178: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c17c: 697b ldr r3, [r7, #20] 800c17e: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (LL_RCC_LSE_IsEnabled() == 1U) 800c182: f7ff fde1 bl 800bd48 800c186: 4603 mov r3, r0 800c188: 2b01 cmp r3, #1 800c18a: d114 bne.n 800c1b6 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c18c: f7fa f970 bl 8006470 800c190: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() != 1U) 800c192: e00b b.n 800c1ac { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800c194: f7fa f96c bl 8006470 800c198: 4602 mov r2, r0 800c19a: 693b ldr r3, [r7, #16] 800c19c: 1ad3 subs r3, r2, r3 800c19e: f241 3288 movw r2, #5000 @ 0x1388 800c1a2: 4293 cmp r3, r2 800c1a4: d902 bls.n 800c1ac { ret = HAL_TIMEOUT; 800c1a6: 2303 movs r3, #3 800c1a8: 77fb strb r3, [r7, #31] break; 800c1aa: e004 b.n 800c1b6 while (LL_RCC_LSE_IsReady() != 1U) 800c1ac: f7ff fdde bl 800bd6c 800c1b0: 4603 mov r3, r0 800c1b2: 2b01 cmp r3, #1 800c1b4: d1ee bne.n 800c194 } } } /* set overall return value */ status = ret; 800c1b6: 7ffb ldrb r3, [r7, #31] 800c1b8: 77bb strb r3, [r7, #30] 800c1ba: e001 b.n 800c1c0 } else { /* set overall return value */ status = ret; 800c1bc: 7ffb ldrb r3, [r7, #31] 800c1be: 77bb strb r3, [r7, #30] } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 800c1c0: 687b ldr r3, [r7, #4] 800c1c2: 681b ldr r3, [r3, #0] 800c1c4: f003 0301 and.w r3, r3, #1 800c1c8: 2b00 cmp r3, #0 800c1ca: d004 beq.n 800c1d6 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 800c1cc: 687b ldr r3, [r7, #4] 800c1ce: 699b ldr r3, [r3, #24] 800c1d0: 4618 mov r0, r3 800c1d2: f7ff fe2a bl 800be2a } #if defined(LPUART1) /*-------------------------- LPUART1 clock source configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800c1d6: 687b ldr r3, [r7, #4] 800c1d8: 681b ldr r3, [r3, #0] 800c1da: f003 0302 and.w r3, r3, #2 800c1de: 2b00 cmp r3, #0 800c1e0: d004 beq.n 800c1ec { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800c1e2: 687b ldr r3, [r7, #4] 800c1e4: 69db ldr r3, [r3, #28] 800c1e6: 4618 mov r0, r3 800c1e8: f7ff fe35 bl 800be56 } #endif /* LPUART1 */ /*-------------------------- LPTIM1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) 800c1ec: 687b ldr r3, [r7, #4] 800c1ee: 681b ldr r3, [r3, #0] 800c1f0: f003 0310 and.w r3, r3, #16 800c1f4: 2b00 cmp r3, #0 800c1f6: d004 beq.n 800c202 { assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800c1f8: 687b ldr r3, [r7, #4] 800c1fa: 6a9b ldr r3, [r3, #40] @ 0x28 800c1fc: 4618 mov r0, r3 800c1fe: f7ff fe5d bl 800bebc } /*-------------------------- LPTIM2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) 800c202: 687b ldr r3, [r7, #4] 800c204: 681b ldr r3, [r3, #0] 800c206: f003 0320 and.w r3, r3, #32 800c20a: 2b00 cmp r3, #0 800c20c: d004 beq.n 800c218 { assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800c20e: 687b ldr r3, [r7, #4] 800c210: 6adb ldr r3, [r3, #44] @ 0x2c 800c212: 4618 mov r0, r3 800c214: f7ff fe52 bl 800bebc } /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 800c218: 687b ldr r3, [r7, #4] 800c21a: 681b ldr r3, [r3, #0] 800c21c: f003 0304 and.w r3, r3, #4 800c220: 2b00 cmp r3, #0 800c222: d004 beq.n 800c22e { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 800c224: 687b ldr r3, [r7, #4] 800c226: 6a1b ldr r3, [r3, #32] 800c228: 4618 mov r0, r3 800c22a: f7ff fe2a bl 800be82 } #if defined(I2C3) /*-------------------------- I2C3 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 800c22e: 687b ldr r3, [r7, #4] 800c230: 681b ldr r3, [r3, #0] 800c232: f003 0308 and.w r3, r3, #8 800c236: 2b00 cmp r3, #0 800c238: d004 beq.n 800c244 { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 800c23a: 687b ldr r3, [r7, #4] 800c23c: 6a5b ldr r3, [r3, #36] @ 0x24 800c23e: 4618 mov r0, r3 800c240: f7ff fe1f bl 800be82 } #endif /* I2C3 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 800c244: 687b ldr r3, [r7, #4] 800c246: 681b ldr r3, [r3, #0] 800c248: f403 7380 and.w r3, r3, #256 @ 0x100 800c24c: 2b00 cmp r3, #0 800c24e: d022 beq.n 800c296 { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800c250: 687b ldr r3, [r7, #4] 800c252: 6b5b ldr r3, [r3, #52] @ 0x34 800c254: 4618 mov r0, r3 800c256: f7ff fe8d bl 800bf74 if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 800c25a: 687b ldr r3, [r7, #4] 800c25c: 6b5b ldr r3, [r3, #52] @ 0x34 800c25e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800c262: d107 bne.n 800c274 { /* Enable PLLQ output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK); 800c264: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c268: 68db ldr r3, [r3, #12] 800c26a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c26e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800c272: 60d3 str r3, [r2, #12] } #if defined(SAI1) if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) 800c274: 687b ldr r3, [r7, #4] 800c276: 6b5b ldr r3, [r3, #52] @ 0x34 800c278: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c27c: d10b bne.n 800c296 { /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1)); 800c27e: 687b ldr r3, [r7, #4] 800c280: 3304 adds r3, #4 800c282: 4618 mov r0, r3 800c284: f000 f8e3 bl 800c44e 800c288: 4603 mov r3, r0 800c28a: 77fb strb r3, [r7, #31] if (ret != HAL_OK) 800c28c: 7ffb ldrb r3, [r7, #31] 800c28e: 2b00 cmp r3, #0 800c290: d001 beq.n 800c296 { /* set overall return value */ status = ret; 800c292: 7ffb ldrb r3, [r7, #31] 800c294: 77bb strb r3, [r7, #30] #endif /* SAI1 */ } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 800c296: 687b ldr r3, [r7, #4] 800c298: 681b ldr r3, [r3, #0] 800c29a: f403 7300 and.w r3, r3, #512 @ 0x200 800c29e: 2b00 cmp r3, #0 800c2a0: d02b beq.n 800c2fa { /* Check the parameters */ assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); /* Configure the RNG clock source */ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800c2a2: 687b ldr r3, [r7, #4] 800c2a4: 6b9b ldr r3, [r3, #56] @ 0x38 800c2a6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800c2aa: d008 beq.n 800c2be 800c2ac: 687b ldr r3, [r7, #4] 800c2ae: 6b9b ldr r3, [r3, #56] @ 0x38 800c2b0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800c2b4: d003 beq.n 800c2be 800c2b6: 687b ldr r3, [r7, #4] 800c2b8: 6b9b ldr r3, [r3, #56] @ 0x38 800c2ba: 2b00 cmp r3, #0 800c2bc: d105 bne.n 800c2ca 800c2be: 687b ldr r3, [r7, #4] 800c2c0: 6b9b ldr r3, [r3, #56] @ 0x38 800c2c2: 4618 mov r0, r3 800c2c4: f7ff fe2a bl 800bf1c 800c2c8: e00a b.n 800c2e0 800c2ca: 687b ldr r3, [r7, #4] 800c2cc: 6b9b ldr r3, [r3, #56] @ 0x38 800c2ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800c2d2: 60fb str r3, [r7, #12] 800c2d4: 2000 movs r0, #0 800c2d6: f7ff fe21 bl 800bf1c 800c2da: 68f8 ldr r0, [r7, #12] 800c2dc: f7ff fe34 bl 800bf48 if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 800c2e0: 687b ldr r3, [r7, #4] 800c2e2: 6b9b ldr r3, [r3, #56] @ 0x38 800c2e4: f1b3 5fc0 cmp.w r3, #402653184 @ 0x18000000 800c2e8: d107 bne.n 800c2fa { /* Enable PLLQ output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); 800c2ea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c2ee: 68db ldr r3, [r3, #12] 800c2f0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c2f4: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800c2f8: 60d3 str r3, [r2, #12] } } /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800c2fa: 687b ldr r3, [r7, #4] 800c2fc: 681b ldr r3, [r3, #0] 800c2fe: f403 6380 and.w r3, r3, #1024 @ 0x400 800c302: 2b00 cmp r3, #0 800c304: d022 beq.n 800c34c { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800c306: 687b ldr r3, [r7, #4] 800c308: 6bdb ldr r3, [r3, #60] @ 0x3c 800c30a: 4618 mov r0, r3 800c30c: f7ff fe3d bl 800bf8a if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) 800c310: 687b ldr r3, [r7, #4] 800c312: 6bdb ldr r3, [r3, #60] @ 0x3c 800c314: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c318: d107 bne.n 800c32a { /* Enable RCC_PLL_RNGCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 800c31a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c31e: 68db ldr r3, [r3, #12] 800c320: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c324: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c328: 60d3 str r3, [r2, #12] } #if defined(SAI1) if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) 800c32a: 687b ldr r3, [r7, #4] 800c32c: 6bdb ldr r3, [r3, #60] @ 0x3c 800c32e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800c332: d10b bne.n 800c34c { /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1)); 800c334: 687b ldr r3, [r7, #4] 800c336: 3304 adds r3, #4 800c338: 4618 mov r0, r3 800c33a: f000 f8e3 bl 800c504 800c33e: 4603 mov r3, r0 800c340: 77fb strb r3, [r7, #31] if (ret != HAL_OK) 800c342: 7ffb ldrb r3, [r7, #31] 800c344: 2b00 cmp r3, #0 800c346: d001 beq.n 800c34c { /* set overall return value */ status = ret; 800c348: 7ffb ldrb r3, [r7, #31] 800c34a: 77bb strb r3, [r7, #30] } #endif /* SAI1 */ } /*-------------------------- RFWKP clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP) 800c34c: 687b ldr r3, [r7, #4] 800c34e: 681b ldr r3, [r3, #0] 800c350: f403 5380 and.w r3, r3, #4096 @ 0x1000 800c354: 2b00 cmp r3, #0 800c356: d004 beq.n 800c362 { /* Check the parameters */ assert_param(IS_RCC_RFWKPCLKSOURCE(PeriphClkInit->RFWakeUpClockSelection)); /* Configure the RFWKP interface clock source */ __HAL_RCC_RFWAKEUP_CONFIG(PeriphClkInit->RFWakeUpClockSelection); 800c358: 687b ldr r3, [r7, #4] 800c35a: 6c5b ldr r3, [r3, #68] @ 0x44 800c35c: 4618 mov r0, r3 800c35e: f7ff fd26 bl 800bdae } #if defined(RCC_SMPS_SUPPORT) /*-------------------------- SMPS clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) 800c362: 687b ldr r3, [r7, #4] 800c364: 681b ldr r3, [r3, #0] 800c366: f403 5300 and.w r3, r3, #8192 @ 0x2000 800c36a: 2b00 cmp r3, #0 800c36c: d009 beq.n 800c382 /* Check the parameters */ assert_param(IS_RCC_SMPSCLKDIV(PeriphClkInit->SmpsDivSelection)); assert_param(IS_RCC_SMPSCLKSOURCE(PeriphClkInit->SmpsClockSelection)); /* Configure the SMPS interface clock division factor */ __HAL_RCC_SMPS_DIV_CONFIG(PeriphClkInit->SmpsDivSelection); 800c36e: 687b ldr r3, [r7, #4] 800c370: 6cdb ldr r3, [r3, #76] @ 0x4c 800c372: 4618 mov r0, r3 800c374: f7ff fd45 bl 800be02 /* Configure the SMPS interface clock source */ __HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection); 800c378: 687b ldr r3, [r7, #4] 800c37a: 6c9b ldr r3, [r3, #72] @ 0x48 800c37c: 4618 mov r0, r3 800c37e: f7ff fd2c bl 800bdda } #endif /* RCC_SMPS_SUPPORT */ return status; 800c382: 7fbb ldrb r3, [r7, #30] } 800c384: 4618 mov r0, r3 800c386: 3720 adds r7, #32 800c388: 46bd mov sp, r7 800c38a: bd80 pop {r7, pc} 0800c38c : * @note Prior to enable the PLL-mode of the MSI for automatic hardware * calibration LSE oscillator is to be enabled with @ref HAL_RCC_OscConfig(). * @retval None */ void HAL_RCCEx_EnableMSIPLLMode(void) { 800c38c: b580 push {r7, lr} 800c38e: af00 add r7, sp, #0 LL_RCC_MSI_EnablePLLMode() ; 800c390: f7ff fcfe bl 800bd90 } 800c394: bf00 nop 800c396: bd80 pop {r7, pc} 0800c398 : * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1) { 800c398: b580 push {r7, lr} 800c39a: b084 sub sp, #16 800c39c: af00 add r7, sp, #0 800c39e: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800c3a0: 2300 movs r3, #0 800c3a2: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); assert_param(IS_RCC_PLLP_VALUE(PLLSAI1->PLLP)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); /* Disable the PLLSAI1 */ __HAL_RCC_PLLSAI1_DISABLE(); 800c3a4: f7ff fe5b bl 800c05e /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c3a8: f7fa f862 bl 8006470 800c3ac: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready to be updated */ while (LL_RCC_PLLSAI1_IsReady() != 0U) 800c3ae: e009 b.n 800c3c4 { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800c3b0: f7fa f85e bl 8006470 800c3b4: 4602 mov r2, r0 800c3b6: 68bb ldr r3, [r7, #8] 800c3b8: 1ad3 subs r3, r2, r3 800c3ba: 2b02 cmp r3, #2 800c3bc: d902 bls.n 800c3c4 { status = HAL_TIMEOUT; 800c3be: 2303 movs r3, #3 800c3c0: 73fb strb r3, [r7, #15] break; 800c3c2: e004 b.n 800c3ce while (LL_RCC_PLLSAI1_IsReady() != 0U) 800c3c4: f7ff fe5a bl 800c07c 800c3c8: 4603 mov r3, r0 800c3ca: 2b00 cmp r3, #0 800c3cc: d1f0 bne.n 800c3b0 } } if (status == HAL_OK) 800c3ce: 7bfb ldrb r3, [r7, #15] 800c3d0: 2b00 cmp r3, #0 800c3d2: d137 bne.n 800c444 { /* Configure the PLLSAI1 Multiplication factor N */ __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); 800c3d4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c3d8: 691b ldr r3, [r3, #16] 800c3da: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 800c3de: 687b ldr r3, [r7, #4] 800c3e0: 681b ldr r3, [r3, #0] 800c3e2: 021b lsls r3, r3, #8 800c3e4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c3e8: 4313 orrs r3, r2 800c3ea: 610b str r3, [r1, #16] /* Configure the PLLSAI1 Division factor P */ __HAL_RCC_PLLSAI1_DIVP_CONFIG(PLLSAI1->PLLP); 800c3ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c3f0: 691b ldr r3, [r3, #16] 800c3f2: f423 1278 bic.w r2, r3, #4063232 @ 0x3e0000 800c3f6: 687b ldr r3, [r7, #4] 800c3f8: 685b ldr r3, [r3, #4] 800c3fa: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c3fe: 4313 orrs r3, r2 800c400: 610b str r3, [r1, #16] /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ __HAL_RCC_PLLSAI1_ENABLE(); 800c402: f7ff fe1d bl 800c040 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c406: f7fa f833 bl 8006470 800c40a: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready */ while (LL_RCC_PLLSAI1_IsReady() != 1U) 800c40c: e009 b.n 800c422 { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800c40e: f7fa f82f bl 8006470 800c412: 4602 mov r2, r0 800c414: 68bb ldr r3, [r7, #8] 800c416: 1ad3 subs r3, r2, r3 800c418: 2b02 cmp r3, #2 800c41a: d902 bls.n 800c422 { status = HAL_TIMEOUT; 800c41c: 2303 movs r3, #3 800c41e: 73fb strb r3, [r7, #15] break; 800c420: e004 b.n 800c42c while (LL_RCC_PLLSAI1_IsReady() != 1U) 800c422: f7ff fe2b bl 800c07c 800c426: 4603 mov r3, r0 800c428: 2b01 cmp r3, #1 800c42a: d1f0 bne.n 800c40e } } if (status == HAL_OK) 800c42c: 7bfb ldrb r3, [r7, #15] 800c42e: 2b00 cmp r3, #0 800c430: d108 bne.n 800c444 { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); 800c432: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c436: 691a ldr r2, [r3, #16] 800c438: 687b ldr r3, [r7, #4] 800c43a: 691b ldr r3, [r3, #16] 800c43c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c440: 4313 orrs r3, r2 800c442: 610b str r3, [r1, #16] } } return status; 800c444: 7bfb ldrb r3, [r7, #15] } 800c446: 4618 mov r0, r3 800c448: 3710 adds r7, #16 800c44a: 46bd mov sp, r7 800c44c: bd80 pop {r7, pc} 0800c44e : * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1) { 800c44e: b580 push {r7, lr} 800c450: b084 sub sp, #16 800c452: af00 add r7, sp, #0 800c454: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800c456: 2300 movs r3, #0 800c458: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); assert_param(IS_RCC_PLLQ_VALUE(PLLSAI1->PLLQ)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); /* Disable the PLLSAI1 */ __HAL_RCC_PLLSAI1_DISABLE(); 800c45a: f7ff fe00 bl 800c05e /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c45e: f7fa f807 bl 8006470 800c462: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready to be updated */ while (LL_RCC_PLLSAI1_IsReady() != 0U) 800c464: e009 b.n 800c47a { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800c466: f7fa f803 bl 8006470 800c46a: 4602 mov r2, r0 800c46c: 68bb ldr r3, [r7, #8] 800c46e: 1ad3 subs r3, r2, r3 800c470: 2b02 cmp r3, #2 800c472: d902 bls.n 800c47a { status = HAL_TIMEOUT; 800c474: 2303 movs r3, #3 800c476: 73fb strb r3, [r7, #15] break; 800c478: e004 b.n 800c484 while (LL_RCC_PLLSAI1_IsReady() != 0U) 800c47a: f7ff fdff bl 800c07c 800c47e: 4603 mov r3, r0 800c480: 2b00 cmp r3, #0 800c482: d1f0 bne.n 800c466 } } if (status == HAL_OK) 800c484: 7bfb ldrb r3, [r7, #15] 800c486: 2b00 cmp r3, #0 800c488: d137 bne.n 800c4fa { /* Configure the PLLSAI1 Multiplication factor N */ __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); 800c48a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c48e: 691b ldr r3, [r3, #16] 800c490: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 800c494: 687b ldr r3, [r7, #4] 800c496: 681b ldr r3, [r3, #0] 800c498: 021b lsls r3, r3, #8 800c49a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c49e: 4313 orrs r3, r2 800c4a0: 610b str r3, [r1, #16] /* Configure the PLLSAI1 Division factor Q */ __HAL_RCC_PLLSAI1_DIVQ_CONFIG(PLLSAI1->PLLQ); 800c4a2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c4a6: 691b ldr r3, [r3, #16] 800c4a8: f023 6260 bic.w r2, r3, #234881024 @ 0xe000000 800c4ac: 687b ldr r3, [r7, #4] 800c4ae: 689b ldr r3, [r3, #8] 800c4b0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c4b4: 4313 orrs r3, r2 800c4b6: 610b str r3, [r1, #16] /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ __HAL_RCC_PLLSAI1_ENABLE(); 800c4b8: f7ff fdc2 bl 800c040 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c4bc: f7f9 ffd8 bl 8006470 800c4c0: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready */ while (LL_RCC_PLLSAI1_IsReady() != 1U) 800c4c2: e009 b.n 800c4d8 { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800c4c4: f7f9 ffd4 bl 8006470 800c4c8: 4602 mov r2, r0 800c4ca: 68bb ldr r3, [r7, #8] 800c4cc: 1ad3 subs r3, r2, r3 800c4ce: 2b02 cmp r3, #2 800c4d0: d902 bls.n 800c4d8 { status = HAL_TIMEOUT; 800c4d2: 2303 movs r3, #3 800c4d4: 73fb strb r3, [r7, #15] break; 800c4d6: e004 b.n 800c4e2 while (LL_RCC_PLLSAI1_IsReady() != 1U) 800c4d8: f7ff fdd0 bl 800c07c 800c4dc: 4603 mov r3, r0 800c4de: 2b01 cmp r3, #1 800c4e0: d1f0 bne.n 800c4c4 } } if (status == HAL_OK) 800c4e2: 7bfb ldrb r3, [r7, #15] 800c4e4: 2b00 cmp r3, #0 800c4e6: d108 bne.n 800c4fa { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); 800c4e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c4ec: 691a ldr r2, [r3, #16] 800c4ee: 687b ldr r3, [r7, #4] 800c4f0: 691b ldr r3, [r3, #16] 800c4f2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c4f6: 4313 orrs r3, r2 800c4f8: 610b str r3, [r1, #16] } } return status; 800c4fa: 7bfb ldrb r3, [r7, #15] } 800c4fc: 4618 mov r0, r3 800c4fe: 3710 adds r7, #16 800c500: 46bd mov sp, r7 800c502: bd80 pop {r7, pc} 0800c504 : * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1) { 800c504: b580 push {r7, lr} 800c506: b084 sub sp, #16 800c508: af00 add r7, sp, #0 800c50a: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800c50c: 2300 movs r3, #0 800c50e: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); assert_param(IS_RCC_PLLR_VALUE(PLLSAI1->PLLR)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); /* Disable the PLLSAI1 */ __HAL_RCC_PLLSAI1_DISABLE(); 800c510: f7ff fda5 bl 800c05e /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c514: f7f9 ffac bl 8006470 800c518: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready to be updated */ while (LL_RCC_PLLSAI1_IsReady() != 0U) 800c51a: e009 b.n 800c530 { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800c51c: f7f9 ffa8 bl 8006470 800c520: 4602 mov r2, r0 800c522: 68bb ldr r3, [r7, #8] 800c524: 1ad3 subs r3, r2, r3 800c526: 2b02 cmp r3, #2 800c528: d902 bls.n 800c530 { status = HAL_TIMEOUT; 800c52a: 2303 movs r3, #3 800c52c: 73fb strb r3, [r7, #15] break; 800c52e: e004 b.n 800c53a while (LL_RCC_PLLSAI1_IsReady() != 0U) 800c530: f7ff fda4 bl 800c07c 800c534: 4603 mov r3, r0 800c536: 2b00 cmp r3, #0 800c538: d1f0 bne.n 800c51c } } if (status == HAL_OK) 800c53a: 7bfb ldrb r3, [r7, #15] 800c53c: 2b00 cmp r3, #0 800c53e: d137 bne.n 800c5b0 { /* Configure the PLLSAI1 Multiplication factor N */ __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); 800c540: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c544: 691b ldr r3, [r3, #16] 800c546: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 800c54a: 687b ldr r3, [r7, #4] 800c54c: 681b ldr r3, [r3, #0] 800c54e: 021b lsls r3, r3, #8 800c550: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c554: 4313 orrs r3, r2 800c556: 610b str r3, [r1, #16] /* Configure the PLLSAI1 Division factor R */ __HAL_RCC_PLLSAI1_DIVR_CONFIG(PLLSAI1->PLLR); 800c558: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c55c: 691b ldr r3, [r3, #16] 800c55e: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 800c562: 687b ldr r3, [r7, #4] 800c564: 68db ldr r3, [r3, #12] 800c566: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c56a: 4313 orrs r3, r2 800c56c: 610b str r3, [r1, #16] /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ __HAL_RCC_PLLSAI1_ENABLE(); 800c56e: f7ff fd67 bl 800c040 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c572: f7f9 ff7d bl 8006470 800c576: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready */ while (LL_RCC_PLLSAI1_IsReady() != 1U) 800c578: e009 b.n 800c58e { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800c57a: f7f9 ff79 bl 8006470 800c57e: 4602 mov r2, r0 800c580: 68bb ldr r3, [r7, #8] 800c582: 1ad3 subs r3, r2, r3 800c584: 2b02 cmp r3, #2 800c586: d902 bls.n 800c58e { status = HAL_TIMEOUT; 800c588: 2303 movs r3, #3 800c58a: 73fb strb r3, [r7, #15] break; 800c58c: e004 b.n 800c598 while (LL_RCC_PLLSAI1_IsReady() != 1U) 800c58e: f7ff fd75 bl 800c07c 800c592: 4603 mov r3, r0 800c594: 2b01 cmp r3, #1 800c596: d1f0 bne.n 800c57a } } if (status == HAL_OK) 800c598: 7bfb ldrb r3, [r7, #15] 800c59a: 2b00 cmp r3, #0 800c59c: d108 bne.n 800c5b0 { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); 800c59e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c5a2: 691a ldr r2, [r3, #16] 800c5a4: 687b ldr r3, [r7, #4] 800c5a6: 691b ldr r3, [r3, #16] 800c5a8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c5ac: 4313 orrs r3, r2 800c5ae: 610b str r3, [r1, #16] } } return status; 800c5b0: 7bfb ldrb r3, [r7, #15] } 800c5b2: 4618 mov r0, r3 800c5b4: 3710 adds r7, #16 800c5b6: 46bd mov sp, r7 800c5b8: bd80 pop {r7, pc} 0800c5ba : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 800c5ba: b580 push {r7, lr} 800c5bc: b084 sub sp, #16 800c5be: af00 add r7, sp, #0 800c5c0: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; /* Check RTC handler validity */ if (hrtc == NULL) 800c5c2: 687b ldr r3, [r7, #4] 800c5c4: 2b00 cmp r3, #0 800c5c6: d101 bne.n 800c5cc { return HAL_ERROR; 800c5c8: 2301 movs r3, #1 800c5ca: e07a b.n 800c6c2 { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else /* USE_HAL_RTC_REGISTER_CALLBACKS */ if (hrtc->State == HAL_RTC_STATE_RESET) 800c5cc: 687b ldr r3, [r7, #4] 800c5ce: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800c5d2: b2db uxtb r3, r3 800c5d4: 2b00 cmp r3, #0 800c5d6: d106 bne.n 800c5e6 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 800c5d8: 687b ldr r3, [r7, #4] 800c5da: 2200 movs r2, #0 800c5dc: f883 2020 strb.w r2, [r3, #32] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 800c5e0: 6878 ldr r0, [r7, #4] 800c5e2: f7f9 fb83 bl 8005cec } #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 800c5e6: 687b ldr r3, [r7, #4] 800c5e8: 2202 movs r2, #2 800c5ea: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Check whether the calendar needs to be initialized */ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) 800c5ee: 687b ldr r3, [r7, #4] 800c5f0: 681b ldr r3, [r3, #0] 800c5f2: 68db ldr r3, [r3, #12] 800c5f4: f003 0310 and.w r3, r3, #16 800c5f8: 2b10 cmp r3, #16 800c5fa: d058 beq.n 800c6ae { /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 800c5fc: 687b ldr r3, [r7, #4] 800c5fe: 681b ldr r3, [r3, #0] 800c600: 22ca movs r2, #202 @ 0xca 800c602: 625a str r2, [r3, #36] @ 0x24 800c604: 687b ldr r3, [r7, #4] 800c606: 681b ldr r3, [r3, #0] 800c608: 2253 movs r2, #83 @ 0x53 800c60a: 625a str r2, [r3, #36] @ 0x24 /* Enter Initialization mode */ status = RTC_EnterInitMode(hrtc); 800c60c: 6878 ldr r0, [r7, #4] 800c60e: f000 f883 bl 800c718 800c612: 4603 mov r3, r0 800c614: 73fb strb r3, [r7, #15] if (status == HAL_OK) 800c616: 7bfb ldrb r3, [r7, #15] 800c618: 2b00 cmp r3, #0 800c61a: d12c bne.n 800c676 { /* Clear RTC_CR FMT, OSEL and POL Bits */ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); 800c61c: 687b ldr r3, [r7, #4] 800c61e: 681b ldr r3, [r3, #0] 800c620: 689b ldr r3, [r3, #8] 800c622: 687a ldr r2, [r7, #4] 800c624: 6812 ldr r2, [r2, #0] 800c626: f423 03e0 bic.w r3, r3, #7340032 @ 0x700000 800c62a: f023 0340 bic.w r3, r3, #64 @ 0x40 800c62e: 6093 str r3, [r2, #8] /* Set RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); 800c630: 687b ldr r3, [r7, #4] 800c632: 681b ldr r3, [r3, #0] 800c634: 6899 ldr r1, [r3, #8] 800c636: 687b ldr r3, [r7, #4] 800c638: 685a ldr r2, [r3, #4] 800c63a: 687b ldr r3, [r7, #4] 800c63c: 691b ldr r3, [r3, #16] 800c63e: 431a orrs r2, r3 800c640: 687b ldr r3, [r7, #4] 800c642: 699b ldr r3, [r3, #24] 800c644: 431a orrs r2, r3 800c646: 687b ldr r3, [r7, #4] 800c648: 681b ldr r3, [r3, #0] 800c64a: 430a orrs r2, r1 800c64c: 609a str r2, [r3, #8] /* Configure the RTC PRER */ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); 800c64e: 687b ldr r3, [r7, #4] 800c650: 681b ldr r3, [r3, #0] 800c652: 687a ldr r2, [r7, #4] 800c654: 68d2 ldr r2, [r2, #12] 800c656: 611a str r2, [r3, #16] hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); 800c658: 687b ldr r3, [r7, #4] 800c65a: 681b ldr r3, [r3, #0] 800c65c: 6919 ldr r1, [r3, #16] 800c65e: 687b ldr r3, [r7, #4] 800c660: 689b ldr r3, [r3, #8] 800c662: 041a lsls r2, r3, #16 800c664: 687b ldr r3, [r7, #4] 800c666: 681b ldr r3, [r3, #0] 800c668: 430a orrs r2, r1 800c66a: 611a str r2, [r3, #16] /* Exit Initialization mode */ status = RTC_ExitInitMode(hrtc); 800c66c: 6878 ldr r0, [r7, #4] 800c66e: f000 f88b bl 800c788 800c672: 4603 mov r3, r0 800c674: 73fb strb r3, [r7, #15] } if (status == HAL_OK) 800c676: 7bfb ldrb r3, [r7, #15] 800c678: 2b00 cmp r3, #0 800c67a: d113 bne.n 800c6a4 { #if defined(RTC_OR_ALARMOUTTYPE) hrtc->Instance->OR &= (uint32_t)~(RTC_OUTPUT_TYPE_PUSHPULL | RTC_OUTPUT_REMAP_POS1); 800c67c: 687b ldr r3, [r7, #4] 800c67e: 681b ldr r3, [r3, #0] 800c680: 6cda ldr r2, [r3, #76] @ 0x4c 800c682: 687b ldr r3, [r7, #4] 800c684: 681b ldr r3, [r3, #0] 800c686: f022 0203 bic.w r2, r2, #3 800c68a: 64da str r2, [r3, #76] @ 0x4c hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); 800c68c: 687b ldr r3, [r7, #4] 800c68e: 681b ldr r3, [r3, #0] 800c690: 6cd9 ldr r1, [r3, #76] @ 0x4c 800c692: 687b ldr r3, [r7, #4] 800c694: 69da ldr r2, [r3, #28] 800c696: 687b ldr r3, [r7, #4] 800c698: 695b ldr r3, [r3, #20] 800c69a: 431a orrs r2, r3 800c69c: 687b ldr r3, [r7, #4] 800c69e: 681b ldr r3, [r3, #0] 800c6a0: 430a orrs r2, r1 800c6a2: 64da str r2, [r3, #76] @ 0x4c hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutRemap); #endif /* RTC_OR_ALARMOUTTYPE */ } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800c6a4: 687b ldr r3, [r7, #4] 800c6a6: 681b ldr r3, [r3, #0] 800c6a8: 22ff movs r2, #255 @ 0xff 800c6aa: 625a str r2, [r3, #36] @ 0x24 800c6ac: e001 b.n 800c6b2 } else { /* The calendar is already initialized */ status = HAL_OK; 800c6ae: 2300 movs r3, #0 800c6b0: 73fb strb r3, [r7, #15] } if (status == HAL_OK) 800c6b2: 7bfb ldrb r3, [r7, #15] 800c6b4: 2b00 cmp r3, #0 800c6b6: d103 bne.n 800c6c0 { hrtc->State = HAL_RTC_STATE_READY; 800c6b8: 687b ldr r3, [r7, #4] 800c6ba: 2201 movs r2, #1 800c6bc: f883 2021 strb.w r2, [r3, #33] @ 0x21 } return status; 800c6c0: 7bfb ldrb r3, [r7, #15] } 800c6c2: 4618 mov r0, r3 800c6c4: 3710 adds r7, #16 800c6c6: 46bd mov sp, r7 800c6c8: bd80 pop {r7, pc} ... 0800c6cc : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 800c6cc: b580 push {r7, lr} 800c6ce: b084 sub sp, #16 800c6d0: af00 add r7, sp, #0 800c6d2: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800c6d4: 2300 movs r3, #0 800c6d6: 60fb str r3, [r7, #12] /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK)); 800c6d8: 687b ldr r3, [r7, #4] 800c6da: 681b ldr r3, [r3, #0] 800c6dc: 4a0d ldr r2, [pc, #52] @ (800c714 ) 800c6de: 60da str r2, [r3, #12] /* Get tick */ tickstart = HAL_GetTick(); 800c6e0: f7f9 fec6 bl 8006470 800c6e4: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) 800c6e6: e009 b.n 800c6fc { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800c6e8: f7f9 fec2 bl 8006470 800c6ec: 4602 mov r2, r0 800c6ee: 68fb ldr r3, [r7, #12] 800c6f0: 1ad3 subs r3, r2, r3 800c6f2: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c6f6: d901 bls.n 800c6fc { return HAL_TIMEOUT; 800c6f8: 2303 movs r3, #3 800c6fa: e007 b.n 800c70c while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) 800c6fc: 687b ldr r3, [r7, #4] 800c6fe: 681b ldr r3, [r3, #0] 800c700: 68db ldr r3, [r3, #12] 800c702: f003 0320 and.w r3, r3, #32 800c706: 2b00 cmp r3, #0 800c708: d0ee beq.n 800c6e8 } } return HAL_OK; 800c70a: 2300 movs r3, #0 } 800c70c: 4618 mov r0, r3 800c70e: 3710 adds r7, #16 800c710: 46bd mov sp, r7 800c712: bd80 pop {r7, pc} 800c714: 0001ff5f .word 0x0001ff5f 0800c718 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 800c718: b580 push {r7, lr} 800c71a: b084 sub sp, #16 800c71c: af00 add r7, sp, #0 800c71e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800c720: 2300 movs r3, #0 800c722: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 800c724: 2300 movs r3, #0 800c726: 73fb strb r3, [r7, #15] /* Check that Initialization mode is not already set */ if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) 800c728: 687b ldr r3, [r7, #4] 800c72a: 681b ldr r3, [r3, #0] 800c72c: 68db ldr r3, [r3, #12] 800c72e: f003 0340 and.w r3, r3, #64 @ 0x40 800c732: 2b00 cmp r3, #0 800c734: d123 bne.n 800c77e { /* Set INIT bit to enter Initialization mode */ SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); 800c736: 687b ldr r3, [r7, #4] 800c738: 681b ldr r3, [r3, #0] 800c73a: 68da ldr r2, [r3, #12] 800c73c: 687b ldr r3, [r7, #4] 800c73e: 681b ldr r3, [r3, #0] 800c740: f042 0280 orr.w r2, r2, #128 @ 0x80 800c744: 60da str r2, [r3, #12] /* Get tick */ tickstart = HAL_GetTick(); 800c746: f7f9 fe93 bl 8006470 800c74a: 60b8 str r0, [r7, #8] /* Wait till RTC is in INIT state and if timeout is reached exit */ while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) 800c74c: e00d b.n 800c76a { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800c74e: f7f9 fe8f bl 8006470 800c752: 4602 mov r2, r0 800c754: 68bb ldr r3, [r7, #8] 800c756: 1ad3 subs r3, r2, r3 800c758: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800c75c: d905 bls.n 800c76a { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 800c75e: 687b ldr r3, [r7, #4] 800c760: 2204 movs r2, #4 800c762: f883 2021 strb.w r2, [r3, #33] @ 0x21 status = HAL_ERROR; 800c766: 2301 movs r3, #1 800c768: 73fb strb r3, [r7, #15] while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) 800c76a: 687b ldr r3, [r7, #4] 800c76c: 681b ldr r3, [r3, #0] 800c76e: 68db ldr r3, [r3, #12] 800c770: f003 0340 and.w r3, r3, #64 @ 0x40 800c774: 2b00 cmp r3, #0 800c776: d102 bne.n 800c77e 800c778: 7bfb ldrb r3, [r7, #15] 800c77a: 2b01 cmp r3, #1 800c77c: d1e7 bne.n 800c74e } } } return status; 800c77e: 7bfb ldrb r3, [r7, #15] } 800c780: 4618 mov r0, r3 800c782: 3710 adds r7, #16 800c784: 46bd mov sp, r7 800c786: bd80 pop {r7, pc} 0800c788 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 800c788: b580 push {r7, lr} 800c78a: b084 sub sp, #16 800c78c: af00 add r7, sp, #0 800c78e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800c790: 2300 movs r3, #0 800c792: 73fb strb r3, [r7, #15] /* Clear INIT bit to exit Initialization mode */ CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); 800c794: 687b ldr r3, [r7, #4] 800c796: 681b ldr r3, [r3, #0] 800c798: 68da ldr r2, [r3, #12] 800c79a: 687b ldr r3, [r7, #4] 800c79c: 681b ldr r3, [r3, #0] 800c79e: f022 0280 bic.w r2, r2, #128 @ 0x80 800c7a2: 60da str r2, [r3, #12] /* If CR_BYPSHAD bit = 0, wait for synchro */ if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U) 800c7a4: 687b ldr r3, [r7, #4] 800c7a6: 681b ldr r3, [r3, #0] 800c7a8: 689b ldr r3, [r3, #8] 800c7aa: f003 0320 and.w r3, r3, #32 800c7ae: 2b00 cmp r3, #0 800c7b0: d10b bne.n 800c7ca { if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 800c7b2: 6878 ldr r0, [r7, #4] 800c7b4: f7ff ff8a bl 800c6cc 800c7b8: 4603 mov r3, r0 800c7ba: 2b00 cmp r3, #0 800c7bc: d005 beq.n 800c7ca { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 800c7be: 687b ldr r3, [r7, #4] 800c7c0: 2204 movs r2, #4 800c7c2: f883 2021 strb.w r2, [r3, #33] @ 0x21 status = HAL_ERROR; 800c7c6: 2301 movs r3, #1 800c7c8: 73fb strb r3, [r7, #15] } } return status; 800c7ca: 7bfb ldrb r3, [r7, #15] } 800c7cc: 4618 mov r0, r3 800c7ce: 3710 adds r7, #16 800c7d0: 46bd mov sp, r7 800c7d2: bd80 pop {r7, pc} 0800c7d4 : * @param WakeUpCounter Wakeup counter * @param WakeUpClock Wakeup clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { 800c7d4: b480 push {r7} 800c7d6: b087 sub sp, #28 800c7d8: af00 add r7, sp, #0 800c7da: 60f8 str r0, [r7, #12] 800c7dc: 60b9 str r1, [r7, #8] 800c7de: 607a str r2, [r7, #4] __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); 800c7e0: 4b5f ldr r3, [pc, #380] @ (800c960 ) 800c7e2: 681b ldr r3, [r3, #0] 800c7e4: 4a5f ldr r2, [pc, #380] @ (800c964 ) 800c7e6: fba2 2303 umull r2, r3, r2, r3 800c7ea: 0adb lsrs r3, r3, #11 800c7ec: f44f 727a mov.w r2, #1000 @ 0x3e8 800c7f0: fb02 f303 mul.w r3, r2, r3 800c7f4: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); 800c7f6: 68fb ldr r3, [r7, #12] 800c7f8: f893 3020 ldrb.w r3, [r3, #32] 800c7fc: 2b01 cmp r3, #1 800c7fe: d101 bne.n 800c804 800c800: 2302 movs r3, #2 800c802: e0a7 b.n 800c954 800c804: 68fb ldr r3, [r7, #12] 800c806: 2201 movs r2, #1 800c808: f883 2020 strb.w r2, [r3, #32] hrtc->State = HAL_RTC_STATE_BUSY; 800c80c: 68fb ldr r3, [r7, #12] 800c80e: 2202 movs r2, #2 800c810: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 800c814: 68fb ldr r3, [r7, #12] 800c816: 681b ldr r3, [r3, #0] 800c818: 22ca movs r2, #202 @ 0xca 800c81a: 625a str r2, [r3, #36] @ 0x24 800c81c: 68fb ldr r3, [r7, #12] 800c81e: 681b ldr r3, [r3, #0] 800c820: 2253 movs r2, #83 @ 0x53 800c822: 625a str r2, [r3, #36] @ 0x24 /* Check RTC WUTWF flag is reset only when wakeup timer enabled */ if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) 800c824: 68fb ldr r3, [r7, #12] 800c826: 681b ldr r3, [r3, #0] 800c828: 689b ldr r3, [r3, #8] 800c82a: f403 6380 and.w r3, r3, #1024 @ 0x400 800c82e: 2b00 cmp r3, #0 800c830: d01a beq.n 800c868 { /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ do { count = count - 1U; 800c832: 697b ldr r3, [r7, #20] 800c834: 3b01 subs r3, #1 800c836: 617b str r3, [r7, #20] if (count == 0U) 800c838: 697b ldr r3, [r7, #20] 800c83a: 2b00 cmp r3, #0 800c83c: d10d bne.n 800c85a { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800c83e: 68fb ldr r3, [r7, #12] 800c840: 681b ldr r3, [r3, #0] 800c842: 22ff movs r2, #255 @ 0xff 800c844: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_TIMEOUT; 800c846: 68fb ldr r3, [r7, #12] 800c848: 2203 movs r2, #3 800c84a: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hrtc); 800c84e: 68fb ldr r3, [r7, #12] 800c850: 2200 movs r2, #0 800c852: f883 2020 strb.w r2, [r3, #32] return HAL_TIMEOUT; 800c856: 2303 movs r3, #3 800c858: e07c b.n 800c954 } } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U); 800c85a: 68fb ldr r3, [r7, #12] 800c85c: 681b ldr r3, [r3, #0] 800c85e: 68db ldr r3, [r3, #12] 800c860: f003 0304 and.w r3, r3, #4 800c864: 2b00 cmp r3, #0 800c866: d1e4 bne.n 800c832 } /* Disable the Wakeup timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); 800c868: 68fb ldr r3, [r7, #12] 800c86a: 681b ldr r3, [r3, #0] 800c86c: 689a ldr r2, [r3, #8] 800c86e: 68fb ldr r3, [r7, #12] 800c870: 681b ldr r3, [r3, #0] 800c872: f422 6280 bic.w r2, r2, #1024 @ 0x400 800c876: 609a str r2, [r3, #8] /* Clear the Wakeup flag */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); 800c878: 68fb ldr r3, [r7, #12] 800c87a: 681b ldr r3, [r3, #0] 800c87c: 68db ldr r3, [r3, #12] 800c87e: b2da uxtb r2, r3 800c880: 68fb ldr r3, [r7, #12] 800c882: 681b ldr r3, [r3, #0] 800c884: f462 6290 orn r2, r2, #1152 @ 0x480 800c888: 60da str r2, [r3, #12] /* Reload the counter */ count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); 800c88a: 4b35 ldr r3, [pc, #212] @ (800c960 ) 800c88c: 681b ldr r3, [r3, #0] 800c88e: 4a35 ldr r2, [pc, #212] @ (800c964 ) 800c890: fba2 2303 umull r2, r3, r2, r3 800c894: 0adb lsrs r3, r3, #11 800c896: f44f 727a mov.w r2, #1000 @ 0x3e8 800c89a: fb02 f303 mul.w r3, r2, r3 800c89e: 617b str r3, [r7, #20] /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ do { count = count - 1U; 800c8a0: 697b ldr r3, [r7, #20] 800c8a2: 3b01 subs r3, #1 800c8a4: 617b str r3, [r7, #20] if (count == 0U) 800c8a6: 697b ldr r3, [r7, #20] 800c8a8: 2b00 cmp r3, #0 800c8aa: d10d bne.n 800c8c8 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800c8ac: 68fb ldr r3, [r7, #12] 800c8ae: 681b ldr r3, [r3, #0] 800c8b0: 22ff movs r2, #255 @ 0xff 800c8b2: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_TIMEOUT; 800c8b4: 68fb ldr r3, [r7, #12] 800c8b6: 2203 movs r2, #3 800c8b8: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hrtc); 800c8bc: 68fb ldr r3, [r7, #12] 800c8be: 2200 movs r2, #0 800c8c0: f883 2020 strb.w r2, [r3, #32] return HAL_TIMEOUT; 800c8c4: 2303 movs r3, #3 800c8c6: e045 b.n 800c954 } } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U); 800c8c8: 68fb ldr r3, [r7, #12] 800c8ca: 681b ldr r3, [r3, #0] 800c8cc: 68db ldr r3, [r3, #12] 800c8ce: f003 0304 and.w r3, r3, #4 800c8d2: 2b00 cmp r3, #0 800c8d4: d0e4 beq.n 800c8a0 /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; 800c8d6: 68fb ldr r3, [r7, #12] 800c8d8: 681b ldr r3, [r3, #0] 800c8da: 689a ldr r2, [r3, #8] 800c8dc: 68fb ldr r3, [r7, #12] 800c8de: 681b ldr r3, [r3, #0] 800c8e0: f022 0207 bic.w r2, r2, #7 800c8e4: 609a str r2, [r3, #8] /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; 800c8e6: 68fb ldr r3, [r7, #12] 800c8e8: 681b ldr r3, [r3, #0] 800c8ea: 6899 ldr r1, [r3, #8] 800c8ec: 68fb ldr r3, [r7, #12] 800c8ee: 681b ldr r3, [r3, #0] 800c8f0: 687a ldr r2, [r7, #4] 800c8f2: 430a orrs r2, r1 800c8f4: 609a str r2, [r3, #8] /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; 800c8f6: 68fb ldr r3, [r7, #12] 800c8f8: 681b ldr r3, [r3, #0] 800c8fa: 68ba ldr r2, [r7, #8] 800c8fc: 615a str r2, [r3, #20] /* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); 800c8fe: 4b1a ldr r3, [pc, #104] @ (800c968 ) 800c900: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800c904: 4a18 ldr r2, [pc, #96] @ (800c968 ) 800c906: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800c90a: f8c2 3080 str.w r3, [r2, #128] @ 0x80 __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); 800c90e: 4b16 ldr r3, [pc, #88] @ (800c968 ) 800c910: 681b ldr r3, [r3, #0] 800c912: 4a15 ldr r2, [pc, #84] @ (800c968 ) 800c914: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800c918: 6013 str r3, [r2, #0] /* Configure the interrupt in the RTC_CR register */ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT); 800c91a: 68fb ldr r3, [r7, #12] 800c91c: 681b ldr r3, [r3, #0] 800c91e: 689a ldr r2, [r3, #8] 800c920: 68fb ldr r3, [r7, #12] 800c922: 681b ldr r3, [r3, #0] 800c924: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800c928: 609a str r2, [r3, #8] /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); 800c92a: 68fb ldr r3, [r7, #12] 800c92c: 681b ldr r3, [r3, #0] 800c92e: 689a ldr r2, [r3, #8] 800c930: 68fb ldr r3, [r7, #12] 800c932: 681b ldr r3, [r3, #0] 800c934: f442 6280 orr.w r2, r2, #1024 @ 0x400 800c938: 609a str r2, [r3, #8] /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800c93a: 68fb ldr r3, [r7, #12] 800c93c: 681b ldr r3, [r3, #0] 800c93e: 22ff movs r2, #255 @ 0xff 800c940: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_READY; 800c942: 68fb ldr r3, [r7, #12] 800c944: 2201 movs r2, #1 800c946: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hrtc); 800c94a: 68fb ldr r3, [r7, #12] 800c94c: 2200 movs r2, #0 800c94e: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 800c952: 2300 movs r3, #0 } 800c954: 4618 mov r0, r3 800c956: 371c adds r7, #28 800c958: 46bd mov sp, r7 800c95a: f85d 7b04 ldr.w r7, [sp], #4 800c95e: 4770 bx lr 800c960: 2000000c .word 0x2000000c 800c964: 10624dd3 .word 0x10624dd3 800c968: 58000800 .word 0x58000800 0800c96c : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 800c96c: b580 push {r7, lr} 800c96e: b084 sub sp, #16 800c970: af00 add r7, sp, #0 800c972: 6078 str r0, [r7, #4] uint32_t frxth; /* Check the SPI handle allocation */ if (hspi == NULL) 800c974: 687b ldr r3, [r7, #4] 800c976: 2b00 cmp r3, #0 800c978: d101 bne.n 800c97e { return HAL_ERROR; 800c97a: 2301 movs r3, #1 800c97c: e095 b.n 800caaa assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 800c97e: 687b ldr r3, [r7, #4] 800c980: 6a5b ldr r3, [r3, #36] @ 0x24 800c982: 2b00 cmp r3, #0 800c984: d108 bne.n 800c998 { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 800c986: 687b ldr r3, [r7, #4] 800c988: 685b ldr r3, [r3, #4] 800c98a: f5b3 7f82 cmp.w r3, #260 @ 0x104 800c98e: d009 beq.n 800c9a4 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 800c990: 687b ldr r3, [r7, #4] 800c992: 2200 movs r2, #0 800c994: 61da str r2, [r3, #28] 800c996: e005 b.n 800c9a4 else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 800c998: 687b ldr r3, [r7, #4] 800c99a: 2200 movs r2, #0 800c99c: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 800c99e: 687b ldr r3, [r7, #4] 800c9a0: 2200 movs r2, #0 800c9a2: 615a str r2, [r3, #20] { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 800c9a4: 687b ldr r3, [r7, #4] 800c9a6: 2200 movs r2, #0 800c9a8: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 800c9aa: 687b ldr r3, [r7, #4] 800c9ac: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800c9b0: b2db uxtb r3, r3 800c9b2: 2b00 cmp r3, #0 800c9b4: d106 bne.n 800c9c4 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 800c9b6: 687b ldr r3, [r7, #4] 800c9b8: 2200 movs r2, #0 800c9ba: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 800c9be: 6878 ldr r0, [r7, #4] 800c9c0: f7f9 f9ca bl 8005d58 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 800c9c4: 687b ldr r3, [r7, #4] 800c9c6: 2202 movs r2, #2 800c9c8: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800c9cc: 687b ldr r3, [r7, #4] 800c9ce: 681b ldr r3, [r3, #0] 800c9d0: 681a ldr r2, [r3, #0] 800c9d2: 687b ldr r3, [r7, #4] 800c9d4: 681b ldr r3, [r3, #0] 800c9d6: f022 0240 bic.w r2, r2, #64 @ 0x40 800c9da: 601a str r2, [r3, #0] /* Align by default the rs fifo threshold on the data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 800c9dc: 687b ldr r3, [r7, #4] 800c9de: 68db ldr r3, [r3, #12] 800c9e0: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800c9e4: d902 bls.n 800c9ec { frxth = SPI_RXFIFO_THRESHOLD_HF; 800c9e6: 2300 movs r3, #0 800c9e8: 60fb str r3, [r7, #12] 800c9ea: e002 b.n 800c9f2 } else { frxth = SPI_RXFIFO_THRESHOLD_QF; 800c9ec: f44f 5380 mov.w r3, #4096 @ 0x1000 800c9f0: 60fb str r3, [r7, #12] } /* CRC calculation is valid only for 16Bit and 8 Bit */ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) 800c9f2: 687b ldr r3, [r7, #4] 800c9f4: 68db ldr r3, [r3, #12] 800c9f6: f5b3 6f70 cmp.w r3, #3840 @ 0xf00 800c9fa: d007 beq.n 800ca0c 800c9fc: 687b ldr r3, [r7, #4] 800c9fe: 68db ldr r3, [r3, #12] 800ca00: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800ca04: d002 beq.n 800ca0c { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 800ca06: 687b ldr r3, [r7, #4] 800ca08: 2200 movs r2, #0 800ca0a: 629a str r2, [r3, #40] @ 0x28 } /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 800ca0c: 687b ldr r3, [r7, #4] 800ca0e: 685b ldr r3, [r3, #4] 800ca10: f403 7282 and.w r2, r3, #260 @ 0x104 800ca14: 687b ldr r3, [r7, #4] 800ca16: 689b ldr r3, [r3, #8] 800ca18: f403 4304 and.w r3, r3, #33792 @ 0x8400 800ca1c: 431a orrs r2, r3 800ca1e: 687b ldr r3, [r7, #4] 800ca20: 691b ldr r3, [r3, #16] 800ca22: f003 0302 and.w r3, r3, #2 800ca26: 431a orrs r2, r3 800ca28: 687b ldr r3, [r7, #4] 800ca2a: 695b ldr r3, [r3, #20] 800ca2c: f003 0301 and.w r3, r3, #1 800ca30: 431a orrs r2, r3 800ca32: 687b ldr r3, [r7, #4] 800ca34: 699b ldr r3, [r3, #24] 800ca36: f403 7300 and.w r3, r3, #512 @ 0x200 800ca3a: 431a orrs r2, r3 800ca3c: 687b ldr r3, [r7, #4] 800ca3e: 69db ldr r3, [r3, #28] 800ca40: f003 0338 and.w r3, r3, #56 @ 0x38 800ca44: 431a orrs r2, r3 800ca46: 687b ldr r3, [r7, #4] 800ca48: 6a1b ldr r3, [r3, #32] 800ca4a: f003 0380 and.w r3, r3, #128 @ 0x80 800ca4e: ea42 0103 orr.w r1, r2, r3 800ca52: 687b ldr r3, [r7, #4] 800ca54: 6a9b ldr r3, [r3, #40] @ 0x28 800ca56: f403 5200 and.w r2, r3, #8192 @ 0x2000 800ca5a: 687b ldr r3, [r7, #4] 800ca5c: 681b ldr r3, [r3, #0] 800ca5e: 430a orrs r2, r1 800ca60: 601a str r2, [r3, #0] } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | 800ca62: 687b ldr r3, [r7, #4] 800ca64: 699b ldr r3, [r3, #24] 800ca66: 0c1b lsrs r3, r3, #16 800ca68: f003 0204 and.w r2, r3, #4 800ca6c: 687b ldr r3, [r7, #4] 800ca6e: 6a5b ldr r3, [r3, #36] @ 0x24 800ca70: f003 0310 and.w r3, r3, #16 800ca74: 431a orrs r2, r3 800ca76: 687b ldr r3, [r7, #4] 800ca78: 6b5b ldr r3, [r3, #52] @ 0x34 800ca7a: f003 0308 and.w r3, r3, #8 800ca7e: 431a orrs r2, r3 800ca80: 687b ldr r3, [r7, #4] 800ca82: 68db ldr r3, [r3, #12] 800ca84: f403 6370 and.w r3, r3, #3840 @ 0xf00 800ca88: ea42 0103 orr.w r1, r2, r3 800ca8c: 68fb ldr r3, [r7, #12] 800ca8e: f403 5280 and.w r2, r3, #4096 @ 0x1000 800ca92: 687b ldr r3, [r7, #4] 800ca94: 681b ldr r3, [r3, #0] 800ca96: 430a orrs r2, r1 800ca98: 605a str r2, [r3, #4] #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800ca9a: 687b ldr r3, [r7, #4] 800ca9c: 2200 movs r2, #0 800ca9e: 661a str r2, [r3, #96] @ 0x60 hspi->State = HAL_SPI_STATE_READY; 800caa0: 687b ldr r3, [r7, #4] 800caa2: 2201 movs r2, #1 800caa4: f883 205d strb.w r2, [r3, #93] @ 0x5d return HAL_OK; 800caa8: 2300 movs r3, #0 } 800caaa: 4618 mov r0, r3 800caac: 3710 adds r7, #16 800caae: 46bd mov sp, r7 800cab0: bd80 pop {r7, pc} 0800cab2 : * @param Size amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration in ms * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 800cab2: b580 push {r7, lr} 800cab4: b088 sub sp, #32 800cab6: af00 add r7, sp, #0 800cab8: 60f8 str r0, [r7, #12] 800caba: 60b9 str r1, [r7, #8] 800cabc: 603b str r3, [r7, #0] 800cabe: 4613 mov r3, r2 800cac0: 80fb strh r3, [r7, #6] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800cac2: f7f9 fcd5 bl 8006470 800cac6: 61f8 str r0, [r7, #28] initial_TxXferCount = Size; 800cac8: 88fb ldrh r3, [r7, #6] 800caca: 837b strh r3, [r7, #26] if (hspi->State != HAL_SPI_STATE_READY) 800cacc: 68fb ldr r3, [r7, #12] 800cace: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800cad2: b2db uxtb r3, r3 800cad4: 2b01 cmp r3, #1 800cad6: d001 beq.n 800cadc { return HAL_BUSY; 800cad8: 2302 movs r3, #2 800cada: e15c b.n 800cd96 } if ((pData == NULL) || (Size == 0U)) 800cadc: 68bb ldr r3, [r7, #8] 800cade: 2b00 cmp r3, #0 800cae0: d002 beq.n 800cae8 800cae2: 88fb ldrh r3, [r7, #6] 800cae4: 2b00 cmp r3, #0 800cae6: d101 bne.n 800caec { return HAL_ERROR; 800cae8: 2301 movs r3, #1 800caea: e154 b.n 800cd96 } /* Process Locked */ __HAL_LOCK(hspi); 800caec: 68fb ldr r3, [r7, #12] 800caee: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 800caf2: 2b01 cmp r3, #1 800caf4: d101 bne.n 800cafa 800caf6: 2302 movs r3, #2 800caf8: e14d b.n 800cd96 800cafa: 68fb ldr r3, [r7, #12] 800cafc: 2201 movs r2, #1 800cafe: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; 800cb02: 68fb ldr r3, [r7, #12] 800cb04: 2203 movs r2, #3 800cb06: f883 205d strb.w r2, [r3, #93] @ 0x5d hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800cb0a: 68fb ldr r3, [r7, #12] 800cb0c: 2200 movs r2, #0 800cb0e: 661a str r2, [r3, #96] @ 0x60 hspi->pTxBuffPtr = (const uint8_t *)pData; 800cb10: 68fb ldr r3, [r7, #12] 800cb12: 68ba ldr r2, [r7, #8] 800cb14: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferSize = Size; 800cb16: 68fb ldr r3, [r7, #12] 800cb18: 88fa ldrh r2, [r7, #6] 800cb1a: 879a strh r2, [r3, #60] @ 0x3c hspi->TxXferCount = Size; 800cb1c: 68fb ldr r3, [r7, #12] 800cb1e: 88fa ldrh r2, [r7, #6] 800cb20: 87da strh r2, [r3, #62] @ 0x3e /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; 800cb22: 68fb ldr r3, [r7, #12] 800cb24: 2200 movs r2, #0 800cb26: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferSize = 0U; 800cb28: 68fb ldr r3, [r7, #12] 800cb2a: 2200 movs r2, #0 800cb2c: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hspi->RxXferCount = 0U; 800cb30: 68fb ldr r3, [r7, #12] 800cb32: 2200 movs r2, #0 800cb34: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->TxISR = NULL; 800cb38: 68fb ldr r3, [r7, #12] 800cb3a: 2200 movs r2, #0 800cb3c: 651a str r2, [r3, #80] @ 0x50 hspi->RxISR = NULL; 800cb3e: 68fb ldr r3, [r7, #12] 800cb40: 2200 movs r2, #0 800cb42: 64da str r2, [r3, #76] @ 0x4c /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 800cb44: 68fb ldr r3, [r7, #12] 800cb46: 689b ldr r3, [r3, #8] 800cb48: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800cb4c: d10f bne.n 800cb6e { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 800cb4e: 68fb ldr r3, [r7, #12] 800cb50: 681b ldr r3, [r3, #0] 800cb52: 681a ldr r2, [r3, #0] 800cb54: 68fb ldr r3, [r7, #12] 800cb56: 681b ldr r3, [r3, #0] 800cb58: f022 0240 bic.w r2, r2, #64 @ 0x40 800cb5c: 601a str r2, [r3, #0] SPI_1LINE_TX(hspi); 800cb5e: 68fb ldr r3, [r7, #12] 800cb60: 681b ldr r3, [r3, #0] 800cb62: 681a ldr r2, [r3, #0] 800cb64: 68fb ldr r3, [r7, #12] 800cb66: 681b ldr r3, [r3, #0] 800cb68: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800cb6c: 601a str r2, [r3, #0] SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 800cb6e: 68fb ldr r3, [r7, #12] 800cb70: 681b ldr r3, [r3, #0] 800cb72: 681b ldr r3, [r3, #0] 800cb74: f003 0340 and.w r3, r3, #64 @ 0x40 800cb78: 2b40 cmp r3, #64 @ 0x40 800cb7a: d007 beq.n 800cb8c { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 800cb7c: 68fb ldr r3, [r7, #12] 800cb7e: 681b ldr r3, [r3, #0] 800cb80: 681a ldr r2, [r3, #0] 800cb82: 68fb ldr r3, [r7, #12] 800cb84: 681b ldr r3, [r3, #0] 800cb86: f042 0240 orr.w r2, r2, #64 @ 0x40 800cb8a: 601a str r2, [r3, #0] } /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 800cb8c: 68fb ldr r3, [r7, #12] 800cb8e: 68db ldr r3, [r3, #12] 800cb90: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800cb94: d952 bls.n 800cc3c { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800cb96: 68fb ldr r3, [r7, #12] 800cb98: 685b ldr r3, [r3, #4] 800cb9a: 2b00 cmp r3, #0 800cb9c: d002 beq.n 800cba4 800cb9e: 8b7b ldrh r3, [r7, #26] 800cba0: 2b01 cmp r3, #1 800cba2: d145 bne.n 800cc30 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800cba4: 68fb ldr r3, [r7, #12] 800cba6: 6b9b ldr r3, [r3, #56] @ 0x38 800cba8: 881a ldrh r2, [r3, #0] 800cbaa: 68fb ldr r3, [r7, #12] 800cbac: 681b ldr r3, [r3, #0] 800cbae: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800cbb0: 68fb ldr r3, [r7, #12] 800cbb2: 6b9b ldr r3, [r3, #56] @ 0x38 800cbb4: 1c9a adds r2, r3, #2 800cbb6: 68fb ldr r3, [r7, #12] 800cbb8: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800cbba: 68fb ldr r3, [r7, #12] 800cbbc: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cbbe: b29b uxth r3, r3 800cbc0: 3b01 subs r3, #1 800cbc2: b29a uxth r2, r3 800cbc4: 68fb ldr r3, [r7, #12] 800cbc6: 87da strh r2, [r3, #62] @ 0x3e } /* Transmit data in 16 Bit mode */ while (hspi->TxXferCount > 0U) 800cbc8: e032 b.n 800cc30 { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 800cbca: 68fb ldr r3, [r7, #12] 800cbcc: 681b ldr r3, [r3, #0] 800cbce: 689b ldr r3, [r3, #8] 800cbd0: f003 0302 and.w r3, r3, #2 800cbd4: 2b02 cmp r3, #2 800cbd6: d112 bne.n 800cbfe { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800cbd8: 68fb ldr r3, [r7, #12] 800cbda: 6b9b ldr r3, [r3, #56] @ 0x38 800cbdc: 881a ldrh r2, [r3, #0] 800cbde: 68fb ldr r3, [r7, #12] 800cbe0: 681b ldr r3, [r3, #0] 800cbe2: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800cbe4: 68fb ldr r3, [r7, #12] 800cbe6: 6b9b ldr r3, [r3, #56] @ 0x38 800cbe8: 1c9a adds r2, r3, #2 800cbea: 68fb ldr r3, [r7, #12] 800cbec: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800cbee: 68fb ldr r3, [r7, #12] 800cbf0: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cbf2: b29b uxth r3, r3 800cbf4: 3b01 subs r3, #1 800cbf6: b29a uxth r2, r3 800cbf8: 68fb ldr r3, [r7, #12] 800cbfa: 87da strh r2, [r3, #62] @ 0x3e 800cbfc: e018 b.n 800cc30 } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 800cbfe: f7f9 fc37 bl 8006470 800cc02: 4602 mov r2, r0 800cc04: 69fb ldr r3, [r7, #28] 800cc06: 1ad3 subs r3, r2, r3 800cc08: 683a ldr r2, [r7, #0] 800cc0a: 429a cmp r2, r3 800cc0c: d803 bhi.n 800cc16 800cc0e: 683b ldr r3, [r7, #0] 800cc10: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800cc14: d102 bne.n 800cc1c 800cc16: 683b ldr r3, [r7, #0] 800cc18: 2b00 cmp r3, #0 800cc1a: d109 bne.n 800cc30 { hspi->State = HAL_SPI_STATE_READY; 800cc1c: 68fb ldr r3, [r7, #12] 800cc1e: 2201 movs r2, #1 800cc20: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 800cc24: 68fb ldr r3, [r7, #12] 800cc26: 2200 movs r2, #0 800cc28: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800cc2c: 2303 movs r3, #3 800cc2e: e0b2 b.n 800cd96 while (hspi->TxXferCount > 0U) 800cc30: 68fb ldr r3, [r7, #12] 800cc32: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cc34: b29b uxth r3, r3 800cc36: 2b00 cmp r3, #0 800cc38: d1c7 bne.n 800cbca 800cc3a: e083 b.n 800cd44 } } /* Transmit data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800cc3c: 68fb ldr r3, [r7, #12] 800cc3e: 685b ldr r3, [r3, #4] 800cc40: 2b00 cmp r3, #0 800cc42: d002 beq.n 800cc4a 800cc44: 8b7b ldrh r3, [r7, #26] 800cc46: 2b01 cmp r3, #1 800cc48: d177 bne.n 800cd3a { if (hspi->TxXferCount > 1U) 800cc4a: 68fb ldr r3, [r7, #12] 800cc4c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cc4e: b29b uxth r3, r3 800cc50: 2b01 cmp r3, #1 800cc52: d912 bls.n 800cc7a { /* write on the data register in packing mode */ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800cc54: 68fb ldr r3, [r7, #12] 800cc56: 6b9b ldr r3, [r3, #56] @ 0x38 800cc58: 881a ldrh r2, [r3, #0] 800cc5a: 68fb ldr r3, [r7, #12] 800cc5c: 681b ldr r3, [r3, #0] 800cc5e: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800cc60: 68fb ldr r3, [r7, #12] 800cc62: 6b9b ldr r3, [r3, #56] @ 0x38 800cc64: 1c9a adds r2, r3, #2 800cc66: 68fb ldr r3, [r7, #12] 800cc68: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 800cc6a: 68fb ldr r3, [r7, #12] 800cc6c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cc6e: b29b uxth r3, r3 800cc70: 3b02 subs r3, #2 800cc72: b29a uxth r2, r3 800cc74: 68fb ldr r3, [r7, #12] 800cc76: 87da strh r2, [r3, #62] @ 0x3e 800cc78: e05f b.n 800cd3a } else { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 800cc7a: 68fb ldr r3, [r7, #12] 800cc7c: 6b9a ldr r2, [r3, #56] @ 0x38 800cc7e: 68fb ldr r3, [r7, #12] 800cc80: 681b ldr r3, [r3, #0] 800cc82: 330c adds r3, #12 800cc84: 7812 ldrb r2, [r2, #0] 800cc86: 701a strb r2, [r3, #0] hspi->pTxBuffPtr ++; 800cc88: 68fb ldr r3, [r7, #12] 800cc8a: 6b9b ldr r3, [r3, #56] @ 0x38 800cc8c: 1c5a adds r2, r3, #1 800cc8e: 68fb ldr r3, [r7, #12] 800cc90: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800cc92: 68fb ldr r3, [r7, #12] 800cc94: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cc96: b29b uxth r3, r3 800cc98: 3b01 subs r3, #1 800cc9a: b29a uxth r2, r3 800cc9c: 68fb ldr r3, [r7, #12] 800cc9e: 87da strh r2, [r3, #62] @ 0x3e } } while (hspi->TxXferCount > 0U) 800cca0: e04b b.n 800cd3a { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 800cca2: 68fb ldr r3, [r7, #12] 800cca4: 681b ldr r3, [r3, #0] 800cca6: 689b ldr r3, [r3, #8] 800cca8: f003 0302 and.w r3, r3, #2 800ccac: 2b02 cmp r3, #2 800ccae: d12b bne.n 800cd08 { if (hspi->TxXferCount > 1U) 800ccb0: 68fb ldr r3, [r7, #12] 800ccb2: 8fdb ldrh r3, [r3, #62] @ 0x3e 800ccb4: b29b uxth r3, r3 800ccb6: 2b01 cmp r3, #1 800ccb8: d912 bls.n 800cce0 { /* write on the data register in packing mode */ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800ccba: 68fb ldr r3, [r7, #12] 800ccbc: 6b9b ldr r3, [r3, #56] @ 0x38 800ccbe: 881a ldrh r2, [r3, #0] 800ccc0: 68fb ldr r3, [r7, #12] 800ccc2: 681b ldr r3, [r3, #0] 800ccc4: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800ccc6: 68fb ldr r3, [r7, #12] 800ccc8: 6b9b ldr r3, [r3, #56] @ 0x38 800ccca: 1c9a adds r2, r3, #2 800cccc: 68fb ldr r3, [r7, #12] 800ccce: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 800ccd0: 68fb ldr r3, [r7, #12] 800ccd2: 8fdb ldrh r3, [r3, #62] @ 0x3e 800ccd4: b29b uxth r3, r3 800ccd6: 3b02 subs r3, #2 800ccd8: b29a uxth r2, r3 800ccda: 68fb ldr r3, [r7, #12] 800ccdc: 87da strh r2, [r3, #62] @ 0x3e 800ccde: e02c b.n 800cd3a } else { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 800cce0: 68fb ldr r3, [r7, #12] 800cce2: 6b9a ldr r2, [r3, #56] @ 0x38 800cce4: 68fb ldr r3, [r7, #12] 800cce6: 681b ldr r3, [r3, #0] 800cce8: 330c adds r3, #12 800ccea: 7812 ldrb r2, [r2, #0] 800ccec: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 800ccee: 68fb ldr r3, [r7, #12] 800ccf0: 6b9b ldr r3, [r3, #56] @ 0x38 800ccf2: 1c5a adds r2, r3, #1 800ccf4: 68fb ldr r3, [r7, #12] 800ccf6: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800ccf8: 68fb ldr r3, [r7, #12] 800ccfa: 8fdb ldrh r3, [r3, #62] @ 0x3e 800ccfc: b29b uxth r3, r3 800ccfe: 3b01 subs r3, #1 800cd00: b29a uxth r2, r3 800cd02: 68fb ldr r3, [r7, #12] 800cd04: 87da strh r2, [r3, #62] @ 0x3e 800cd06: e018 b.n 800cd3a } } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 800cd08: f7f9 fbb2 bl 8006470 800cd0c: 4602 mov r2, r0 800cd0e: 69fb ldr r3, [r7, #28] 800cd10: 1ad3 subs r3, r2, r3 800cd12: 683a ldr r2, [r7, #0] 800cd14: 429a cmp r2, r3 800cd16: d803 bhi.n 800cd20 800cd18: 683b ldr r3, [r7, #0] 800cd1a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800cd1e: d102 bne.n 800cd26 800cd20: 683b ldr r3, [r7, #0] 800cd22: 2b00 cmp r3, #0 800cd24: d109 bne.n 800cd3a { hspi->State = HAL_SPI_STATE_READY; 800cd26: 68fb ldr r3, [r7, #12] 800cd28: 2201 movs r2, #1 800cd2a: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 800cd2e: 68fb ldr r3, [r7, #12] 800cd30: 2200 movs r2, #0 800cd32: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800cd36: 2303 movs r3, #3 800cd38: e02d b.n 800cd96 while (hspi->TxXferCount > 0U) 800cd3a: 68fb ldr r3, [r7, #12] 800cd3c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cd3e: b29b uxth r3, r3 800cd40: 2b00 cmp r3, #0 800cd42: d1ae bne.n 800cca2 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 800cd44: 69fa ldr r2, [r7, #28] 800cd46: 6839 ldr r1, [r7, #0] 800cd48: 68f8 ldr r0, [r7, #12] 800cd4a: f000 fe43 bl 800d9d4 800cd4e: 4603 mov r3, r0 800cd50: 2b00 cmp r3, #0 800cd52: d002 beq.n 800cd5a { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 800cd54: 68fb ldr r3, [r7, #12] 800cd56: 2220 movs r2, #32 800cd58: 661a str r2, [r3, #96] @ 0x60 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 800cd5a: 68fb ldr r3, [r7, #12] 800cd5c: 689b ldr r3, [r3, #8] 800cd5e: 2b00 cmp r3, #0 800cd60: d10a bne.n 800cd78 { __HAL_SPI_CLEAR_OVRFLAG(hspi); 800cd62: 2300 movs r3, #0 800cd64: 617b str r3, [r7, #20] 800cd66: 68fb ldr r3, [r7, #12] 800cd68: 681b ldr r3, [r3, #0] 800cd6a: 68db ldr r3, [r3, #12] 800cd6c: 617b str r3, [r7, #20] 800cd6e: 68fb ldr r3, [r7, #12] 800cd70: 681b ldr r3, [r3, #0] 800cd72: 689b ldr r3, [r3, #8] 800cd74: 617b str r3, [r7, #20] 800cd76: 697b ldr r3, [r7, #20] } hspi->State = HAL_SPI_STATE_READY; 800cd78: 68fb ldr r3, [r7, #12] 800cd7a: 2201 movs r2, #1 800cd7c: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 800cd80: 68fb ldr r3, [r7, #12] 800cd82: 2200 movs r2, #0 800cd84: f883 205c strb.w r2, [r3, #92] @ 0x5c if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800cd88: 68fb ldr r3, [r7, #12] 800cd8a: 6e1b ldr r3, [r3, #96] @ 0x60 800cd8c: 2b00 cmp r3, #0 800cd8e: d001 beq.n 800cd94 { return HAL_ERROR; 800cd90: 2301 movs r3, #1 800cd92: e000 b.n 800cd96 } else { return HAL_OK; 800cd94: 2300 movs r3, #0 } } 800cd96: 4618 mov r0, r3 800cd98: 3720 adds r7, #32 800cd9a: 46bd mov sp, r7 800cd9c: bd80 pop {r7, pc} 0800cd9e : * @param Timeout Timeout duration in ms * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { 800cd9e: b580 push {r7, lr} 800cda0: b08a sub sp, #40 @ 0x28 800cda2: af00 add r7, sp, #0 800cda4: 60f8 str r0, [r7, #12] 800cda6: 60b9 str r1, [r7, #8] 800cda8: 607a str r2, [r7, #4] 800cdaa: 807b strh r3, [r7, #2] __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; 800cdac: 2301 movs r3, #1 800cdae: 627b str r3, [r7, #36] @ 0x24 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800cdb0: f7f9 fb5e bl 8006470 800cdb4: 6238 str r0, [r7, #32] /* Init temporary variables */ tmp_state = hspi->State; 800cdb6: 68fb ldr r3, [r7, #12] 800cdb8: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800cdbc: 77fb strb r3, [r7, #31] tmp_mode = hspi->Init.Mode; 800cdbe: 68fb ldr r3, [r7, #12] 800cdc0: 685b ldr r3, [r3, #4] 800cdc2: 61bb str r3, [r7, #24] initial_TxXferCount = Size; 800cdc4: 887b ldrh r3, [r7, #2] 800cdc6: 82fb strh r3, [r7, #22] initial_RxXferCount = Size; 800cdc8: 887b ldrh r3, [r7, #2] 800cdca: 82bb strh r3, [r7, #20] #if (USE_SPI_CRC != 0U) spi_cr1 = READ_REG(hspi->Instance->CR1); spi_cr2 = READ_REG(hspi->Instance->CR2); #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ 800cdcc: 7ffb ldrb r3, [r7, #31] 800cdce: 2b01 cmp r3, #1 800cdd0: d00c beq.n 800cdec 800cdd2: 69bb ldr r3, [r7, #24] 800cdd4: f5b3 7f82 cmp.w r3, #260 @ 0x104 800cdd8: d106 bne.n 800cde8 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && 800cdda: 68fb ldr r3, [r7, #12] 800cddc: 689b ldr r3, [r3, #8] 800cdde: 2b00 cmp r3, #0 800cde0: d102 bne.n 800cde8 800cde2: 7ffb ldrb r3, [r7, #31] 800cde4: 2b04 cmp r3, #4 800cde6: d001 beq.n 800cdec (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; 800cde8: 2302 movs r3, #2 800cdea: e1f3 b.n 800d1d4 } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 800cdec: 68bb ldr r3, [r7, #8] 800cdee: 2b00 cmp r3, #0 800cdf0: d005 beq.n 800cdfe 800cdf2: 687b ldr r3, [r7, #4] 800cdf4: 2b00 cmp r3, #0 800cdf6: d002 beq.n 800cdfe 800cdf8: 887b ldrh r3, [r7, #2] 800cdfa: 2b00 cmp r3, #0 800cdfc: d101 bne.n 800ce02 { return HAL_ERROR; 800cdfe: 2301 movs r3, #1 800ce00: e1e8 b.n 800d1d4 } /* Process Locked */ __HAL_LOCK(hspi); 800ce02: 68fb ldr r3, [r7, #12] 800ce04: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 800ce08: 2b01 cmp r3, #1 800ce0a: d101 bne.n 800ce10 800ce0c: 2302 movs r3, #2 800ce0e: e1e1 b.n 800d1d4 800ce10: 68fb ldr r3, [r7, #12] 800ce12: 2201 movs r2, #1 800ce14: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 800ce18: 68fb ldr r3, [r7, #12] 800ce1a: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800ce1e: b2db uxtb r3, r3 800ce20: 2b04 cmp r3, #4 800ce22: d003 beq.n 800ce2c { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 800ce24: 68fb ldr r3, [r7, #12] 800ce26: 2205 movs r2, #5 800ce28: f883 205d strb.w r2, [r3, #93] @ 0x5d } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800ce2c: 68fb ldr r3, [r7, #12] 800ce2e: 2200 movs r2, #0 800ce30: 661a str r2, [r3, #96] @ 0x60 hspi->pRxBuffPtr = (uint8_t *)pRxData; 800ce32: 68fb ldr r3, [r7, #12] 800ce34: 687a ldr r2, [r7, #4] 800ce36: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount = Size; 800ce38: 68fb ldr r3, [r7, #12] 800ce3a: 887a ldrh r2, [r7, #2] 800ce3c: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->RxXferSize = Size; 800ce40: 68fb ldr r3, [r7, #12] 800ce42: 887a ldrh r2, [r7, #2] 800ce44: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hspi->pTxBuffPtr = (const uint8_t *)pTxData; 800ce48: 68fb ldr r3, [r7, #12] 800ce4a: 68ba ldr r2, [r7, #8] 800ce4c: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount = Size; 800ce4e: 68fb ldr r3, [r7, #12] 800ce50: 887a ldrh r2, [r7, #2] 800ce52: 87da strh r2, [r3, #62] @ 0x3e hspi->TxXferSize = Size; 800ce54: 68fb ldr r3, [r7, #12] 800ce56: 887a ldrh r2, [r7, #2] 800ce58: 879a strh r2, [r3, #60] @ 0x3c /*Init field not used in handle to zero */ hspi->RxISR = NULL; 800ce5a: 68fb ldr r3, [r7, #12] 800ce5c: 2200 movs r2, #0 800ce5e: 64da str r2, [r3, #76] @ 0x4c hspi->TxISR = NULL; 800ce60: 68fb ldr r3, [r7, #12] 800ce62: 2200 movs r2, #0 800ce64: 651a str r2, [r3, #80] @ 0x50 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) 800ce66: 68fb ldr r3, [r7, #12] 800ce68: 68db ldr r3, [r3, #12] 800ce6a: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800ce6e: d802 bhi.n 800ce76 800ce70: 8abb ldrh r3, [r7, #20] 800ce72: 2b01 cmp r3, #1 800ce74: d908 bls.n 800ce88 { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800ce76: 68fb ldr r3, [r7, #12] 800ce78: 681b ldr r3, [r3, #0] 800ce7a: 685a ldr r2, [r3, #4] 800ce7c: 68fb ldr r3, [r7, #12] 800ce7e: 681b ldr r3, [r3, #0] 800ce80: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800ce84: 605a str r2, [r3, #4] 800ce86: e007 b.n 800ce98 } else { /* Set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800ce88: 68fb ldr r3, [r7, #12] 800ce8a: 681b ldr r3, [r3, #0] 800ce8c: 685a ldr r2, [r3, #4] 800ce8e: 68fb ldr r3, [r7, #12] 800ce90: 681b ldr r3, [r3, #0] 800ce92: f442 5280 orr.w r2, r2, #4096 @ 0x1000 800ce96: 605a str r2, [r3, #4] } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 800ce98: 68fb ldr r3, [r7, #12] 800ce9a: 681b ldr r3, [r3, #0] 800ce9c: 681b ldr r3, [r3, #0] 800ce9e: f003 0340 and.w r3, r3, #64 @ 0x40 800cea2: 2b40 cmp r3, #64 @ 0x40 800cea4: d007 beq.n 800ceb6 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 800cea6: 68fb ldr r3, [r7, #12] 800cea8: 681b ldr r3, [r3, #0] 800ceaa: 681a ldr r2, [r3, #0] 800ceac: 68fb ldr r3, [r7, #12] 800ceae: 681b ldr r3, [r3, #0] 800ceb0: f042 0240 orr.w r2, r2, #64 @ 0x40 800ceb4: 601a str r2, [r3, #0] } /* Transmit and Receive data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 800ceb6: 68fb ldr r3, [r7, #12] 800ceb8: 68db ldr r3, [r3, #12] 800ceba: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800cebe: f240 8083 bls.w 800cfc8 { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800cec2: 68fb ldr r3, [r7, #12] 800cec4: 685b ldr r3, [r3, #4] 800cec6: 2b00 cmp r3, #0 800cec8: d002 beq.n 800ced0 800ceca: 8afb ldrh r3, [r7, #22] 800cecc: 2b01 cmp r3, #1 800cece: d16f bne.n 800cfb0 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800ced0: 68fb ldr r3, [r7, #12] 800ced2: 6b9b ldr r3, [r3, #56] @ 0x38 800ced4: 881a ldrh r2, [r3, #0] 800ced6: 68fb ldr r3, [r7, #12] 800ced8: 681b ldr r3, [r3, #0] 800ceda: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800cedc: 68fb ldr r3, [r7, #12] 800cede: 6b9b ldr r3, [r3, #56] @ 0x38 800cee0: 1c9a adds r2, r3, #2 800cee2: 68fb ldr r3, [r7, #12] 800cee4: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800cee6: 68fb ldr r3, [r7, #12] 800cee8: 8fdb ldrh r3, [r3, #62] @ 0x3e 800ceea: b29b uxth r3, r3 800ceec: 3b01 subs r3, #1 800ceee: b29a uxth r2, r3 800cef0: 68fb ldr r3, [r7, #12] 800cef2: 87da strh r2, [r3, #62] @ 0x3e SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 800cef4: e05c b.n 800cfb0 { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 800cef6: 68fb ldr r3, [r7, #12] 800cef8: 681b ldr r3, [r3, #0] 800cefa: 689b ldr r3, [r3, #8] 800cefc: f003 0302 and.w r3, r3, #2 800cf00: 2b02 cmp r3, #2 800cf02: d11b bne.n 800cf3c 800cf04: 68fb ldr r3, [r7, #12] 800cf06: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cf08: b29b uxth r3, r3 800cf0a: 2b00 cmp r3, #0 800cf0c: d016 beq.n 800cf3c 800cf0e: 6a7b ldr r3, [r7, #36] @ 0x24 800cf10: 2b01 cmp r3, #1 800cf12: d113 bne.n 800cf3c { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800cf14: 68fb ldr r3, [r7, #12] 800cf16: 6b9b ldr r3, [r3, #56] @ 0x38 800cf18: 881a ldrh r2, [r3, #0] 800cf1a: 68fb ldr r3, [r7, #12] 800cf1c: 681b ldr r3, [r3, #0] 800cf1e: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800cf20: 68fb ldr r3, [r7, #12] 800cf22: 6b9b ldr r3, [r3, #56] @ 0x38 800cf24: 1c9a adds r2, r3, #2 800cf26: 68fb ldr r3, [r7, #12] 800cf28: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800cf2a: 68fb ldr r3, [r7, #12] 800cf2c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cf2e: b29b uxth r3, r3 800cf30: 3b01 subs r3, #1 800cf32: b29a uxth r2, r3 800cf34: 68fb ldr r3, [r7, #12] 800cf36: 87da strh r2, [r3, #62] @ 0x3e /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 800cf38: 2300 movs r3, #0 800cf3a: 627b str r3, [r7, #36] @ 0x24 } #endif /* USE_SPI_CRC */ } /* Check RXNE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 800cf3c: 68fb ldr r3, [r7, #12] 800cf3e: 681b ldr r3, [r3, #0] 800cf40: 689b ldr r3, [r3, #8] 800cf42: f003 0301 and.w r3, r3, #1 800cf46: 2b01 cmp r3, #1 800cf48: d11c bne.n 800cf84 800cf4a: 68fb ldr r3, [r7, #12] 800cf4c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800cf50: b29b uxth r3, r3 800cf52: 2b00 cmp r3, #0 800cf54: d016 beq.n 800cf84 { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 800cf56: 68fb ldr r3, [r7, #12] 800cf58: 681b ldr r3, [r3, #0] 800cf5a: 68da ldr r2, [r3, #12] 800cf5c: 68fb ldr r3, [r7, #12] 800cf5e: 6c1b ldr r3, [r3, #64] @ 0x40 800cf60: b292 uxth r2, r2 800cf62: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 800cf64: 68fb ldr r3, [r7, #12] 800cf66: 6c1b ldr r3, [r3, #64] @ 0x40 800cf68: 1c9a adds r2, r3, #2 800cf6a: 68fb ldr r3, [r7, #12] 800cf6c: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount--; 800cf6e: 68fb ldr r3, [r7, #12] 800cf70: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800cf74: b29b uxth r3, r3 800cf76: 3b01 subs r3, #1 800cf78: b29a uxth r2, r3 800cf7a: 68fb ldr r3, [r7, #12] 800cf7c: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 800cf80: 2301 movs r3, #1 800cf82: 627b str r3, [r7, #36] @ 0x24 } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) 800cf84: f7f9 fa74 bl 8006470 800cf88: 4602 mov r2, r0 800cf8a: 6a3b ldr r3, [r7, #32] 800cf8c: 1ad3 subs r3, r2, r3 800cf8e: 6b3a ldr r2, [r7, #48] @ 0x30 800cf90: 429a cmp r2, r3 800cf92: d80d bhi.n 800cfb0 800cf94: 6b3b ldr r3, [r7, #48] @ 0x30 800cf96: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800cf9a: d009 beq.n 800cfb0 { hspi->State = HAL_SPI_STATE_READY; 800cf9c: 68fb ldr r3, [r7, #12] 800cf9e: 2201 movs r2, #1 800cfa0: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 800cfa4: 68fb ldr r3, [r7, #12] 800cfa6: 2200 movs r2, #0 800cfa8: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800cfac: 2303 movs r3, #3 800cfae: e111 b.n 800d1d4 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 800cfb0: 68fb ldr r3, [r7, #12] 800cfb2: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cfb4: b29b uxth r3, r3 800cfb6: 2b00 cmp r3, #0 800cfb8: d19d bne.n 800cef6 800cfba: 68fb ldr r3, [r7, #12] 800cfbc: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800cfc0: b29b uxth r3, r3 800cfc2: 2b00 cmp r3, #0 800cfc4: d197 bne.n 800cef6 800cfc6: e0e5 b.n 800d194 } } /* Transmit and Receive data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800cfc8: 68fb ldr r3, [r7, #12] 800cfca: 685b ldr r3, [r3, #4] 800cfcc: 2b00 cmp r3, #0 800cfce: d003 beq.n 800cfd8 800cfd0: 8afb ldrh r3, [r7, #22] 800cfd2: 2b01 cmp r3, #1 800cfd4: f040 80d1 bne.w 800d17a { if (hspi->TxXferCount > 1U) 800cfd8: 68fb ldr r3, [r7, #12] 800cfda: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cfdc: b29b uxth r3, r3 800cfde: 2b01 cmp r3, #1 800cfe0: d912 bls.n 800d008 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800cfe2: 68fb ldr r3, [r7, #12] 800cfe4: 6b9b ldr r3, [r3, #56] @ 0x38 800cfe6: 881a ldrh r2, [r3, #0] 800cfe8: 68fb ldr r3, [r7, #12] 800cfea: 681b ldr r3, [r3, #0] 800cfec: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800cfee: 68fb ldr r3, [r7, #12] 800cff0: 6b9b ldr r3, [r3, #56] @ 0x38 800cff2: 1c9a adds r2, r3, #2 800cff4: 68fb ldr r3, [r7, #12] 800cff6: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 800cff8: 68fb ldr r3, [r7, #12] 800cffa: 8fdb ldrh r3, [r3, #62] @ 0x3e 800cffc: b29b uxth r3, r3 800cffe: 3b02 subs r3, #2 800d000: b29a uxth r2, r3 800d002: 68fb ldr r3, [r7, #12] 800d004: 87da strh r2, [r3, #62] @ 0x3e 800d006: e0b8 b.n 800d17a } else { *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); 800d008: 68fb ldr r3, [r7, #12] 800d00a: 6b9a ldr r2, [r3, #56] @ 0x38 800d00c: 68fb ldr r3, [r7, #12] 800d00e: 681b ldr r3, [r3, #0] 800d010: 330c adds r3, #12 800d012: 7812 ldrb r2, [r2, #0] 800d014: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 800d016: 68fb ldr r3, [r7, #12] 800d018: 6b9b ldr r3, [r3, #56] @ 0x38 800d01a: 1c5a adds r2, r3, #1 800d01c: 68fb ldr r3, [r7, #12] 800d01e: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d020: 68fb ldr r3, [r7, #12] 800d022: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d024: b29b uxth r3, r3 800d026: 3b01 subs r3, #1 800d028: b29a uxth r2, r3 800d02a: 68fb ldr r3, [r7, #12] 800d02c: 87da strh r2, [r3, #62] @ 0x3e SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ } } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 800d02e: e0a4 b.n 800d17a { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 800d030: 68fb ldr r3, [r7, #12] 800d032: 681b ldr r3, [r3, #0] 800d034: 689b ldr r3, [r3, #8] 800d036: f003 0302 and.w r3, r3, #2 800d03a: 2b02 cmp r3, #2 800d03c: d134 bne.n 800d0a8 800d03e: 68fb ldr r3, [r7, #12] 800d040: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d042: b29b uxth r3, r3 800d044: 2b00 cmp r3, #0 800d046: d02f beq.n 800d0a8 800d048: 6a7b ldr r3, [r7, #36] @ 0x24 800d04a: 2b01 cmp r3, #1 800d04c: d12c bne.n 800d0a8 { if (hspi->TxXferCount > 1U) 800d04e: 68fb ldr r3, [r7, #12] 800d050: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d052: b29b uxth r3, r3 800d054: 2b01 cmp r3, #1 800d056: d912 bls.n 800d07e { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d058: 68fb ldr r3, [r7, #12] 800d05a: 6b9b ldr r3, [r3, #56] @ 0x38 800d05c: 881a ldrh r2, [r3, #0] 800d05e: 68fb ldr r3, [r7, #12] 800d060: 681b ldr r3, [r3, #0] 800d062: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d064: 68fb ldr r3, [r7, #12] 800d066: 6b9b ldr r3, [r3, #56] @ 0x38 800d068: 1c9a adds r2, r3, #2 800d06a: 68fb ldr r3, [r7, #12] 800d06c: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 800d06e: 68fb ldr r3, [r7, #12] 800d070: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d072: b29b uxth r3, r3 800d074: 3b02 subs r3, #2 800d076: b29a uxth r2, r3 800d078: 68fb ldr r3, [r7, #12] 800d07a: 87da strh r2, [r3, #62] @ 0x3e 800d07c: e012 b.n 800d0a4 } else { *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); 800d07e: 68fb ldr r3, [r7, #12] 800d080: 6b9a ldr r2, [r3, #56] @ 0x38 800d082: 68fb ldr r3, [r7, #12] 800d084: 681b ldr r3, [r3, #0] 800d086: 330c adds r3, #12 800d088: 7812 ldrb r2, [r2, #0] 800d08a: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 800d08c: 68fb ldr r3, [r7, #12] 800d08e: 6b9b ldr r3, [r3, #56] @ 0x38 800d090: 1c5a adds r2, r3, #1 800d092: 68fb ldr r3, [r7, #12] 800d094: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d096: 68fb ldr r3, [r7, #12] 800d098: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d09a: b29b uxth r3, r3 800d09c: 3b01 subs r3, #1 800d09e: b29a uxth r2, r3 800d0a0: 68fb ldr r3, [r7, #12] 800d0a2: 87da strh r2, [r3, #62] @ 0x3e } /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 800d0a4: 2300 movs r3, #0 800d0a6: 627b str r3, [r7, #36] @ 0x24 } #endif /* USE_SPI_CRC */ } /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 800d0a8: 68fb ldr r3, [r7, #12] 800d0aa: 681b ldr r3, [r3, #0] 800d0ac: 689b ldr r3, [r3, #8] 800d0ae: f003 0301 and.w r3, r3, #1 800d0b2: 2b01 cmp r3, #1 800d0b4: d148 bne.n 800d148 800d0b6: 68fb ldr r3, [r7, #12] 800d0b8: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d0bc: b29b uxth r3, r3 800d0be: 2b00 cmp r3, #0 800d0c0: d042 beq.n 800d148 { if (hspi->RxXferCount > 1U) 800d0c2: 68fb ldr r3, [r7, #12] 800d0c4: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d0c8: b29b uxth r3, r3 800d0ca: 2b01 cmp r3, #1 800d0cc: d923 bls.n 800d116 { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 800d0ce: 68fb ldr r3, [r7, #12] 800d0d0: 681b ldr r3, [r3, #0] 800d0d2: 68da ldr r2, [r3, #12] 800d0d4: 68fb ldr r3, [r7, #12] 800d0d6: 6c1b ldr r3, [r3, #64] @ 0x40 800d0d8: b292 uxth r2, r2 800d0da: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 800d0dc: 68fb ldr r3, [r7, #12] 800d0de: 6c1b ldr r3, [r3, #64] @ 0x40 800d0e0: 1c9a adds r2, r3, #2 800d0e2: 68fb ldr r3, [r7, #12] 800d0e4: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount -= 2U; 800d0e6: 68fb ldr r3, [r7, #12] 800d0e8: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d0ec: b29b uxth r3, r3 800d0ee: 3b02 subs r3, #2 800d0f0: b29a uxth r2, r3 800d0f2: 68fb ldr r3, [r7, #12] 800d0f4: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 if (hspi->RxXferCount <= 1U) 800d0f8: 68fb ldr r3, [r7, #12] 800d0fa: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d0fe: b29b uxth r3, r3 800d100: 2b01 cmp r3, #1 800d102: d81f bhi.n 800d144 { /* Set RX Fifo threshold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d104: 68fb ldr r3, [r7, #12] 800d106: 681b ldr r3, [r3, #0] 800d108: 685a ldr r2, [r3, #4] 800d10a: 68fb ldr r3, [r7, #12] 800d10c: 681b ldr r3, [r3, #0] 800d10e: f442 5280 orr.w r2, r2, #4096 @ 0x1000 800d112: 605a str r2, [r3, #4] 800d114: e016 b.n 800d144 } } else { (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; 800d116: 68fb ldr r3, [r7, #12] 800d118: 681b ldr r3, [r3, #0] 800d11a: f103 020c add.w r2, r3, #12 800d11e: 68fb ldr r3, [r7, #12] 800d120: 6c1b ldr r3, [r3, #64] @ 0x40 800d122: 7812 ldrb r2, [r2, #0] 800d124: b2d2 uxtb r2, r2 800d126: 701a strb r2, [r3, #0] hspi->pRxBuffPtr++; 800d128: 68fb ldr r3, [r7, #12] 800d12a: 6c1b ldr r3, [r3, #64] @ 0x40 800d12c: 1c5a adds r2, r3, #1 800d12e: 68fb ldr r3, [r7, #12] 800d130: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount--; 800d132: 68fb ldr r3, [r7, #12] 800d134: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d138: b29b uxth r3, r3 800d13a: 3b01 subs r3, #1 800d13c: b29a uxth r2, r3 800d13e: 68fb ldr r3, [r7, #12] 800d140: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 } /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 800d144: 2301 movs r3, #1 800d146: 627b str r3, [r7, #36] @ 0x24 } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) 800d148: f7f9 f992 bl 8006470 800d14c: 4602 mov r2, r0 800d14e: 6a3b ldr r3, [r7, #32] 800d150: 1ad3 subs r3, r2, r3 800d152: 6b3a ldr r2, [r7, #48] @ 0x30 800d154: 429a cmp r2, r3 800d156: d803 bhi.n 800d160 800d158: 6b3b ldr r3, [r7, #48] @ 0x30 800d15a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d15e: d102 bne.n 800d166 800d160: 6b3b ldr r3, [r7, #48] @ 0x30 800d162: 2b00 cmp r3, #0 800d164: d109 bne.n 800d17a { hspi->State = HAL_SPI_STATE_READY; 800d166: 68fb ldr r3, [r7, #12] 800d168: 2201 movs r2, #1 800d16a: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 800d16e: 68fb ldr r3, [r7, #12] 800d170: 2200 movs r2, #0 800d172: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800d176: 2303 movs r3, #3 800d178: e02c b.n 800d1d4 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 800d17a: 68fb ldr r3, [r7, #12] 800d17c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d17e: b29b uxth r3, r3 800d180: 2b00 cmp r3, #0 800d182: f47f af55 bne.w 800d030 800d186: 68fb ldr r3, [r7, #12] 800d188: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d18c: b29b uxth r3, r3 800d18e: 2b00 cmp r3, #0 800d190: f47f af4e bne.w 800d030 return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 800d194: 6a3a ldr r2, [r7, #32] 800d196: 6b39 ldr r1, [r7, #48] @ 0x30 800d198: 68f8 ldr r0, [r7, #12] 800d19a: f000 fc1b bl 800d9d4 800d19e: 4603 mov r3, r0 800d1a0: 2b00 cmp r3, #0 800d1a2: d008 beq.n 800d1b6 { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 800d1a4: 68fb ldr r3, [r7, #12] 800d1a6: 2220 movs r2, #32 800d1a8: 661a str r2, [r3, #96] @ 0x60 __HAL_UNLOCK(hspi); 800d1aa: 68fb ldr r3, [r7, #12] 800d1ac: 2200 movs r2, #0 800d1ae: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_ERROR; 800d1b2: 2301 movs r3, #1 800d1b4: e00e b.n 800d1d4 } hspi->State = HAL_SPI_STATE_READY; 800d1b6: 68fb ldr r3, [r7, #12] 800d1b8: 2201 movs r2, #1 800d1ba: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Unlock the process */ __HAL_UNLOCK(hspi); 800d1be: 68fb ldr r3, [r7, #12] 800d1c0: 2200 movs r2, #0 800d1c2: f883 205c strb.w r2, [r3, #92] @ 0x5c if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800d1c6: 68fb ldr r3, [r7, #12] 800d1c8: 6e1b ldr r3, [r3, #96] @ 0x60 800d1ca: 2b00 cmp r3, #0 800d1cc: d001 beq.n 800d1d2 { return HAL_ERROR; 800d1ce: 2301 movs r3, #1 800d1d0: e000 b.n 800d1d4 } else { return HAL_OK; 800d1d2: 2300 movs r3, #0 } } 800d1d4: 4618 mov r0, r3 800d1d6: 3728 adds r7, #40 @ 0x28 800d1d8: 46bd mov sp, r7 800d1da: bd80 pop {r7, pc} 0800d1dc : * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { 800d1dc: b580 push {r7, lr} 800d1de: b086 sub sp, #24 800d1e0: af00 add r7, sp, #0 800d1e2: 60f8 str r0, [r7, #12] 800d1e4: 60b9 str r1, [r7, #8] 800d1e6: 607a str r2, [r7, #4] 800d1e8: 807b strh r3, [r7, #2] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Init temporary variables */ tmp_state = hspi->State; 800d1ea: 68fb ldr r3, [r7, #12] 800d1ec: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d1f0: 75fb strb r3, [r7, #23] tmp_mode = hspi->Init.Mode; 800d1f2: 68fb ldr r3, [r7, #12] 800d1f4: 685b ldr r3, [r3, #4] 800d1f6: 613b str r3, [r7, #16] if (!((tmp_state == HAL_SPI_STATE_READY) || 800d1f8: 7dfb ldrb r3, [r7, #23] 800d1fa: 2b01 cmp r3, #1 800d1fc: d00c beq.n 800d218 800d1fe: 693b ldr r3, [r7, #16] 800d200: f5b3 7f82 cmp.w r3, #260 @ 0x104 800d204: d106 bne.n 800d214 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && 800d206: 68fb ldr r3, [r7, #12] 800d208: 689b ldr r3, [r3, #8] 800d20a: 2b00 cmp r3, #0 800d20c: d102 bne.n 800d214 800d20e: 7dfb ldrb r3, [r7, #23] 800d210: 2b04 cmp r3, #4 800d212: d001 beq.n 800d218 (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; 800d214: 2302 movs r3, #2 800d216: e158 b.n 800d4ca } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 800d218: 68bb ldr r3, [r7, #8] 800d21a: 2b00 cmp r3, #0 800d21c: d005 beq.n 800d22a 800d21e: 687b ldr r3, [r7, #4] 800d220: 2b00 cmp r3, #0 800d222: d002 beq.n 800d22a 800d224: 887b ldrh r3, [r7, #2] 800d226: 2b00 cmp r3, #0 800d228: d101 bne.n 800d22e { return HAL_ERROR; 800d22a: 2301 movs r3, #1 800d22c: e14d b.n 800d4ca } /* Process locked */ __HAL_LOCK(hspi); 800d22e: 68fb ldr r3, [r7, #12] 800d230: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 800d234: 2b01 cmp r3, #1 800d236: d101 bne.n 800d23c 800d238: 2302 movs r3, #2 800d23a: e146 b.n 800d4ca 800d23c: 68fb ldr r3, [r7, #12] 800d23e: 2201 movs r2, #1 800d240: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 800d244: 68fb ldr r3, [r7, #12] 800d246: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d24a: b2db uxtb r3, r3 800d24c: 2b04 cmp r3, #4 800d24e: d003 beq.n 800d258 { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 800d250: 68fb ldr r3, [r7, #12] 800d252: 2205 movs r2, #5 800d254: f883 205d strb.w r2, [r3, #93] @ 0x5d } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800d258: 68fb ldr r3, [r7, #12] 800d25a: 2200 movs r2, #0 800d25c: 661a str r2, [r3, #96] @ 0x60 hspi->pTxBuffPtr = (const uint8_t *)pTxData; 800d25e: 68fb ldr r3, [r7, #12] 800d260: 68ba ldr r2, [r7, #8] 800d262: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferSize = Size; 800d264: 68fb ldr r3, [r7, #12] 800d266: 887a ldrh r2, [r7, #2] 800d268: 879a strh r2, [r3, #60] @ 0x3c hspi->TxXferCount = Size; 800d26a: 68fb ldr r3, [r7, #12] 800d26c: 887a ldrh r2, [r7, #2] 800d26e: 87da strh r2, [r3, #62] @ 0x3e hspi->pRxBuffPtr = (uint8_t *)pRxData; 800d270: 68fb ldr r3, [r7, #12] 800d272: 687a ldr r2, [r7, #4] 800d274: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferSize = Size; 800d276: 68fb ldr r3, [r7, #12] 800d278: 887a ldrh r2, [r7, #2] 800d27a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hspi->RxXferCount = Size; 800d27e: 68fb ldr r3, [r7, #12] 800d280: 887a ldrh r2, [r7, #2] 800d282: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 /* Init field not used in handle to zero */ hspi->RxISR = NULL; 800d286: 68fb ldr r3, [r7, #12] 800d288: 2200 movs r2, #0 800d28a: 64da str r2, [r3, #76] @ 0x4c hspi->TxISR = NULL; 800d28c: 68fb ldr r3, [r7, #12] 800d28e: 2200 movs r2, #0 800d290: 651a str r2, [r3, #80] @ 0x50 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); 800d292: 68fb ldr r3, [r7, #12] 800d294: 681b ldr r3, [r3, #0] 800d296: 685a ldr r2, [r3, #4] 800d298: 68fb ldr r3, [r7, #12] 800d29a: 681b ldr r3, [r3, #0] 800d29c: f422 42c0 bic.w r2, r2, #24576 @ 0x6000 800d2a0: 605a str r2, [r3, #4] /* The packing mode management is enabled by the DMA settings according the spi data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 800d2a2: 68fb ldr r3, [r7, #12] 800d2a4: 68db ldr r3, [r3, #12] 800d2a6: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800d2aa: d908 bls.n 800d2be { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d2ac: 68fb ldr r3, [r7, #12] 800d2ae: 681b ldr r3, [r3, #0] 800d2b0: 685a ldr r2, [r3, #4] 800d2b2: 68fb ldr r3, [r7, #12] 800d2b4: 681b ldr r3, [r3, #0] 800d2b6: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800d2ba: 605a str r2, [r3, #4] 800d2bc: e06f b.n 800d39e } else { /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d2be: 68fb ldr r3, [r7, #12] 800d2c0: 681b ldr r3, [r3, #0] 800d2c2: 685a ldr r2, [r3, #4] 800d2c4: 68fb ldr r3, [r7, #12] 800d2c6: 681b ldr r3, [r3, #0] 800d2c8: f442 5280 orr.w r2, r2, #4096 @ 0x1000 800d2cc: 605a str r2, [r3, #4] if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800d2ce: 68fb ldr r3, [r7, #12] 800d2d0: 6d5b ldr r3, [r3, #84] @ 0x54 800d2d2: 699b ldr r3, [r3, #24] 800d2d4: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d2d8: d126 bne.n 800d328 { if ((hspi->TxXferSize & 0x1U) == 0x0U) 800d2da: 68fb ldr r3, [r7, #12] 800d2dc: 8f9b ldrh r3, [r3, #60] @ 0x3c 800d2de: f003 0301 and.w r3, r3, #1 800d2e2: 2b00 cmp r3, #0 800d2e4: d10f bne.n 800d306 { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); 800d2e6: 68fb ldr r3, [r7, #12] 800d2e8: 681b ldr r3, [r3, #0] 800d2ea: 685a ldr r2, [r3, #4] 800d2ec: 68fb ldr r3, [r7, #12] 800d2ee: 681b ldr r3, [r3, #0] 800d2f0: f422 4280 bic.w r2, r2, #16384 @ 0x4000 800d2f4: 605a str r2, [r3, #4] hspi->TxXferCount = hspi->TxXferCount >> 1U; 800d2f6: 68fb ldr r3, [r7, #12] 800d2f8: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d2fa: b29b uxth r3, r3 800d2fc: 085b lsrs r3, r3, #1 800d2fe: b29a uxth r2, r3 800d300: 68fb ldr r3, [r7, #12] 800d302: 87da strh r2, [r3, #62] @ 0x3e 800d304: e010 b.n 800d328 } else { SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); 800d306: 68fb ldr r3, [r7, #12] 800d308: 681b ldr r3, [r3, #0] 800d30a: 685a ldr r2, [r3, #4] 800d30c: 68fb ldr r3, [r7, #12] 800d30e: 681b ldr r3, [r3, #0] 800d310: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800d314: 605a str r2, [r3, #4] hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; 800d316: 68fb ldr r3, [r7, #12] 800d318: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d31a: b29b uxth r3, r3 800d31c: 085b lsrs r3, r3, #1 800d31e: b29b uxth r3, r3 800d320: 3301 adds r3, #1 800d322: b29a uxth r2, r3 800d324: 68fb ldr r3, [r7, #12] 800d326: 87da strh r2, [r3, #62] @ 0x3e } } if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800d328: 68fb ldr r3, [r7, #12] 800d32a: 6d9b ldr r3, [r3, #88] @ 0x58 800d32c: 699b ldr r3, [r3, #24] 800d32e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d332: d134 bne.n 800d39e { /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d334: 68fb ldr r3, [r7, #12] 800d336: 681b ldr r3, [r3, #0] 800d338: 685a ldr r2, [r3, #4] 800d33a: 68fb ldr r3, [r7, #12] 800d33c: 681b ldr r3, [r3, #0] 800d33e: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800d342: 605a str r2, [r3, #4] if ((hspi->RxXferCount & 0x1U) == 0x0U) 800d344: 68fb ldr r3, [r7, #12] 800d346: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d34a: b29b uxth r3, r3 800d34c: f003 0301 and.w r3, r3, #1 800d350: 2b00 cmp r3, #0 800d352: d111 bne.n 800d378 { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); 800d354: 68fb ldr r3, [r7, #12] 800d356: 681b ldr r3, [r3, #0] 800d358: 685a ldr r2, [r3, #4] 800d35a: 68fb ldr r3, [r7, #12] 800d35c: 681b ldr r3, [r3, #0] 800d35e: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800d362: 605a str r2, [r3, #4] hspi->RxXferCount = hspi->RxXferCount >> 1U; 800d364: 68fb ldr r3, [r7, #12] 800d366: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d36a: b29b uxth r3, r3 800d36c: 085b lsrs r3, r3, #1 800d36e: b29a uxth r2, r3 800d370: 68fb ldr r3, [r7, #12] 800d372: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 800d376: e012 b.n 800d39e } else { SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); 800d378: 68fb ldr r3, [r7, #12] 800d37a: 681b ldr r3, [r3, #0] 800d37c: 685a ldr r2, [r3, #4] 800d37e: 68fb ldr r3, [r7, #12] 800d380: 681b ldr r3, [r3, #0] 800d382: f442 5200 orr.w r2, r2, #8192 @ 0x2000 800d386: 605a str r2, [r3, #4] hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; 800d388: 68fb ldr r3, [r7, #12] 800d38a: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d38e: b29b uxth r3, r3 800d390: 085b lsrs r3, r3, #1 800d392: b29b uxth r3, r3 800d394: 3301 adds r3, #1 800d396: b29a uxth r2, r3 800d398: 68fb ldr r3, [r7, #12] 800d39a: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 } } } /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ if (hspi->State == HAL_SPI_STATE_BUSY_RX) 800d39e: 68fb ldr r3, [r7, #12] 800d3a0: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d3a4: b2db uxtb r3, r3 800d3a6: 2b04 cmp r3, #4 800d3a8: d108 bne.n 800d3bc { /* Set the SPI Rx DMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; 800d3aa: 68fb ldr r3, [r7, #12] 800d3ac: 6d9b ldr r3, [r3, #88] @ 0x58 800d3ae: 4a49 ldr r2, [pc, #292] @ (800d4d4 ) 800d3b0: 631a str r2, [r3, #48] @ 0x30 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; 800d3b2: 68fb ldr r3, [r7, #12] 800d3b4: 6d9b ldr r3, [r3, #88] @ 0x58 800d3b6: 4a48 ldr r2, [pc, #288] @ (800d4d8 ) 800d3b8: 62da str r2, [r3, #44] @ 0x2c 800d3ba: e007 b.n 800d3cc } else { /* Set the SPI Tx/Rx DMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; 800d3bc: 68fb ldr r3, [r7, #12] 800d3be: 6d9b ldr r3, [r3, #88] @ 0x58 800d3c0: 4a46 ldr r2, [pc, #280] @ (800d4dc ) 800d3c2: 631a str r2, [r3, #48] @ 0x30 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; 800d3c4: 68fb ldr r3, [r7, #12] 800d3c6: 6d9b ldr r3, [r3, #88] @ 0x58 800d3c8: 4a45 ldr r2, [pc, #276] @ (800d4e0 ) 800d3ca: 62da str r2, [r3, #44] @ 0x2c } /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; 800d3cc: 68fb ldr r3, [r7, #12] 800d3ce: 6d9b ldr r3, [r3, #88] @ 0x58 800d3d0: 4a44 ldr r2, [pc, #272] @ (800d4e4 ) 800d3d2: 635a str r2, [r3, #52] @ 0x34 /* Set the DMA AbortCpltCallback */ hspi->hdmarx->XferAbortCallback = NULL; 800d3d4: 68fb ldr r3, [r7, #12] 800d3d6: 6d9b ldr r3, [r3, #88] @ 0x58 800d3d8: 2200 movs r2, #0 800d3da: 639a str r2, [r3, #56] @ 0x38 /* Enable the Rx DMA Stream/Channel */ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, 800d3dc: 68fb ldr r3, [r7, #12] 800d3de: 6d98 ldr r0, [r3, #88] @ 0x58 800d3e0: 68fb ldr r3, [r7, #12] 800d3e2: 681b ldr r3, [r3, #0] 800d3e4: 330c adds r3, #12 800d3e6: 4619 mov r1, r3 800d3e8: 68fb ldr r3, [r7, #12] 800d3ea: 6c1b ldr r3, [r3, #64] @ 0x40 800d3ec: 461a mov r2, r3 hspi->RxXferCount)) 800d3ee: 68fb ldr r3, [r7, #12] 800d3f0: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d3f4: b29b uxth r3, r3 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, 800d3f6: f7f9 fa65 bl 80068c4 800d3fa: 4603 mov r3, r0 800d3fc: 2b00 cmp r3, #0 800d3fe: d00b beq.n 800d418 { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); 800d400: 68fb ldr r3, [r7, #12] 800d402: 6e1b ldr r3, [r3, #96] @ 0x60 800d404: f043 0210 orr.w r2, r3, #16 800d408: 68fb ldr r3, [r7, #12] 800d40a: 661a str r2, [r3, #96] @ 0x60 /* Process Unlocked */ __HAL_UNLOCK(hspi); 800d40c: 68fb ldr r3, [r7, #12] 800d40e: 2200 movs r2, #0 800d410: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_ERROR; 800d414: 2301 movs r3, #1 800d416: e058 b.n 800d4ca } /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); 800d418: 68fb ldr r3, [r7, #12] 800d41a: 681b ldr r3, [r3, #0] 800d41c: 685a ldr r2, [r3, #4] 800d41e: 68fb ldr r3, [r7, #12] 800d420: 681b ldr r3, [r3, #0] 800d422: f042 0201 orr.w r2, r2, #1 800d426: 605a str r2, [r3, #4] /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing is performed in DMA reception complete callback */ hspi->hdmatx->XferHalfCpltCallback = NULL; 800d428: 68fb ldr r3, [r7, #12] 800d42a: 6d5b ldr r3, [r3, #84] @ 0x54 800d42c: 2200 movs r2, #0 800d42e: 631a str r2, [r3, #48] @ 0x30 hspi->hdmatx->XferCpltCallback = NULL; 800d430: 68fb ldr r3, [r7, #12] 800d432: 6d5b ldr r3, [r3, #84] @ 0x54 800d434: 2200 movs r2, #0 800d436: 62da str r2, [r3, #44] @ 0x2c hspi->hdmatx->XferErrorCallback = NULL; 800d438: 68fb ldr r3, [r7, #12] 800d43a: 6d5b ldr r3, [r3, #84] @ 0x54 800d43c: 2200 movs r2, #0 800d43e: 635a str r2, [r3, #52] @ 0x34 hspi->hdmatx->XferAbortCallback = NULL; 800d440: 68fb ldr r3, [r7, #12] 800d442: 6d5b ldr r3, [r3, #84] @ 0x54 800d444: 2200 movs r2, #0 800d446: 639a str r2, [r3, #56] @ 0x38 /* Enable the Tx DMA Stream/Channel */ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, 800d448: 68fb ldr r3, [r7, #12] 800d44a: 6d58 ldr r0, [r3, #84] @ 0x54 800d44c: 68fb ldr r3, [r7, #12] 800d44e: 6b9b ldr r3, [r3, #56] @ 0x38 800d450: 4619 mov r1, r3 800d452: 68fb ldr r3, [r7, #12] 800d454: 681b ldr r3, [r3, #0] 800d456: 330c adds r3, #12 800d458: 461a mov r2, r3 hspi->TxXferCount)) 800d45a: 68fb ldr r3, [r7, #12] 800d45c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d45e: b29b uxth r3, r3 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, 800d460: f7f9 fa30 bl 80068c4 800d464: 4603 mov r3, r0 800d466: 2b00 cmp r3, #0 800d468: d00b beq.n 800d482 { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); 800d46a: 68fb ldr r3, [r7, #12] 800d46c: 6e1b ldr r3, [r3, #96] @ 0x60 800d46e: f043 0210 orr.w r2, r3, #16 800d472: 68fb ldr r3, [r7, #12] 800d474: 661a str r2, [r3, #96] @ 0x60 /* Process Unlocked */ __HAL_UNLOCK(hspi); 800d476: 68fb ldr r3, [r7, #12] 800d478: 2200 movs r2, #0 800d47a: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_ERROR; 800d47e: 2301 movs r3, #1 800d480: e023 b.n 800d4ca } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 800d482: 68fb ldr r3, [r7, #12] 800d484: 681b ldr r3, [r3, #0] 800d486: 681b ldr r3, [r3, #0] 800d488: f003 0340 and.w r3, r3, #64 @ 0x40 800d48c: 2b40 cmp r3, #64 @ 0x40 800d48e: d007 beq.n 800d4a0 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 800d490: 68fb ldr r3, [r7, #12] 800d492: 681b ldr r3, [r3, #0] 800d494: 681a ldr r2, [r3, #0] 800d496: 68fb ldr r3, [r7, #12] 800d498: 681b ldr r3, [r3, #0] 800d49a: f042 0240 orr.w r2, r2, #64 @ 0x40 800d49e: 601a str r2, [r3, #0] } /* Process Unlocked */ __HAL_UNLOCK(hspi); 800d4a0: 68fb ldr r3, [r7, #12] 800d4a2: 2200 movs r2, #0 800d4a4: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); 800d4a8: 68fb ldr r3, [r7, #12] 800d4aa: 681b ldr r3, [r3, #0] 800d4ac: 685a ldr r2, [r3, #4] 800d4ae: 68fb ldr r3, [r7, #12] 800d4b0: 681b ldr r3, [r3, #0] 800d4b2: f042 0220 orr.w r2, r2, #32 800d4b6: 605a str r2, [r3, #4] /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); 800d4b8: 68fb ldr r3, [r7, #12] 800d4ba: 681b ldr r3, [r3, #0] 800d4bc: 685a ldr r2, [r3, #4] 800d4be: 68fb ldr r3, [r7, #12] 800d4c0: 681b ldr r3, [r3, #0] 800d4c2: f042 0202 orr.w r2, r2, #2 800d4c6: 605a str r2, [r3, #4] return HAL_OK; 800d4c8: 2300 movs r3, #0 } 800d4ca: 4618 mov r0, r3 800d4cc: 3718 adds r7, #24 800d4ce: 46bd mov sp, r7 800d4d0: bd80 pop {r7, pc} 800d4d2: bf00 nop 800d4d4: 0800d671 .word 0x0800d671 800d4d8: 0800d539 .word 0x0800d539 800d4dc: 0800d68d .word 0x0800d68d 800d4e0: 0800d5e1 .word 0x0800d5e1 800d4e4: 0800d6a9 .word 0x0800d6a9 0800d4e8 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { 800d4e8: b480 push {r7} 800d4ea: b083 sub sp, #12 800d4ec: af00 add r7, sp, #0 800d4ee: 6078 str r0, [r7, #4] UNUSED(hspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_RxCpltCallback should be implemented in the user file */ } 800d4f0: bf00 nop 800d4f2: 370c adds r7, #12 800d4f4: 46bd mov sp, r7 800d4f6: f85d 7b04 ldr.w r7, [sp], #4 800d4fa: 4770 bx lr 0800d4fc : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) { 800d4fc: b480 push {r7} 800d4fe: b083 sub sp, #12 800d500: af00 add r7, sp, #0 800d502: 6078 str r0, [r7, #4] UNUSED(hspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file */ } 800d504: bf00 nop 800d506: 370c adds r7, #12 800d508: 46bd mov sp, r7 800d50a: f85d 7b04 ldr.w r7, [sp], #4 800d50e: 4770 bx lr 0800d510 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) { 800d510: b480 push {r7} 800d512: b083 sub sp, #12 800d514: af00 add r7, sp, #0 800d516: 6078 str r0, [r7, #4] UNUSED(hspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file */ } 800d518: bf00 nop 800d51a: 370c adds r7, #12 800d51c: 46bd mov sp, r7 800d51e: f85d 7b04 ldr.w r7, [sp], #4 800d522: 4770 bx lr 0800d524 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { 800d524: b480 push {r7} 800d526: b083 sub sp, #12 800d528: af00 add r7, sp, #0 800d52a: 6078 str r0, [r7, #4] the HAL_SPI_ErrorCallback should be implemented in the user file */ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes and user can use HAL_SPI_GetError() API to check the latest error occurred */ } 800d52c: bf00 nop 800d52e: 370c adds r7, #12 800d530: 46bd mov sp, r7 800d532: f85d 7b04 ldr.w r7, [sp], #4 800d536: 4770 bx lr 0800d538 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 800d538: b580 push {r7, lr} 800d53a: b084 sub sp, #16 800d53c: af00 add r7, sp, #0 800d53e: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800d540: 687b ldr r3, [r7, #4] 800d542: 6a9b ldr r3, [r3, #40] @ 0x28 800d544: 60fb str r3, [r7, #12] __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800d546: f7f8 ff93 bl 8006470 800d54a: 60b8 str r0, [r7, #8] /* DMA Normal Mode */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) 800d54c: 687b ldr r3, [r7, #4] 800d54e: 681b ldr r3, [r3, #0] 800d550: 681b ldr r3, [r3, #0] 800d552: f003 0320 and.w r3, r3, #32 800d556: 2b20 cmp r3, #32 800d558: d03c beq.n 800d5d4 { /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); 800d55a: 68fb ldr r3, [r7, #12] 800d55c: 681b ldr r3, [r3, #0] 800d55e: 685a ldr r2, [r3, #4] 800d560: 68fb ldr r3, [r7, #12] 800d562: 681b ldr r3, [r3, #0] 800d564: f022 0220 bic.w r2, r2, #32 800d568: 605a str r2, [r3, #4] } } #endif /* USE_SPI_CRC */ /* Check if we are in Master RX 2 line mode */ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) 800d56a: 68fb ldr r3, [r7, #12] 800d56c: 689b ldr r3, [r3, #8] 800d56e: 2b00 cmp r3, #0 800d570: d10d bne.n 800d58e 800d572: 68fb ldr r3, [r7, #12] 800d574: 685b ldr r3, [r3, #4] 800d576: f5b3 7f82 cmp.w r3, #260 @ 0x104 800d57a: d108 bne.n 800d58e { /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); 800d57c: 68fb ldr r3, [r7, #12] 800d57e: 681b ldr r3, [r3, #0] 800d580: 685a ldr r2, [r3, #4] 800d582: 68fb ldr r3, [r7, #12] 800d584: 681b ldr r3, [r3, #0] 800d586: f022 0203 bic.w r2, r2, #3 800d58a: 605a str r2, [r3, #4] 800d58c: e007 b.n 800d59e } else { /* Normal case */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); 800d58e: 68fb ldr r3, [r7, #12] 800d590: 681b ldr r3, [r3, #0] 800d592: 685a ldr r2, [r3, #4] 800d594: 68fb ldr r3, [r7, #12] 800d596: 681b ldr r3, [r3, #0] 800d598: f022 0201 bic.w r2, r2, #1 800d59c: 605a str r2, [r3, #4] } /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) 800d59e: 68ba ldr r2, [r7, #8] 800d5a0: 2164 movs r1, #100 @ 0x64 800d5a2: 68f8 ldr r0, [r7, #12] 800d5a4: f000 f9be bl 800d924 800d5a8: 4603 mov r3, r0 800d5aa: 2b00 cmp r3, #0 800d5ac: d002 beq.n 800d5b4 { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 800d5ae: 68fb ldr r3, [r7, #12] 800d5b0: 2220 movs r2, #32 800d5b2: 661a str r2, [r3, #96] @ 0x60 } hspi->RxXferCount = 0U; 800d5b4: 68fb ldr r3, [r7, #12] 800d5b6: 2200 movs r2, #0 800d5b8: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->State = HAL_SPI_STATE_READY; 800d5bc: 68fb ldr r3, [r7, #12] 800d5be: 2201 movs r2, #1 800d5c0: f883 205d strb.w r2, [r3, #93] @ 0x5d SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } #endif /* USE_SPI_CRC */ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800d5c4: 68fb ldr r3, [r7, #12] 800d5c6: 6e1b ldr r3, [r3, #96] @ 0x60 800d5c8: 2b00 cmp r3, #0 800d5ca: d003 beq.n 800d5d4 { /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 800d5cc: 68f8 ldr r0, [r7, #12] 800d5ce: f7ff ffa9 bl 800d524 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; 800d5d2: e002 b.n 800d5da } /* Call user Rx complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->RxCpltCallback(hspi); #else HAL_SPI_RxCpltCallback(hspi); 800d5d4: 68f8 ldr r0, [r7, #12] 800d5d6: f7ff ff87 bl 800d4e8 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800d5da: 3710 adds r7, #16 800d5dc: 46bd mov sp, r7 800d5de: bd80 pop {r7, pc} 0800d5e0 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { 800d5e0: b580 push {r7, lr} 800d5e2: b084 sub sp, #16 800d5e4: af00 add r7, sp, #0 800d5e6: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800d5e8: 687b ldr r3, [r7, #4] 800d5ea: 6a9b ldr r3, [r3, #40] @ 0x28 800d5ec: 60fb str r3, [r7, #12] __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800d5ee: f7f8 ff3f bl 8006470 800d5f2: 60b8 str r0, [r7, #8] /* DMA Normal Mode */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) 800d5f4: 687b ldr r3, [r7, #4] 800d5f6: 681b ldr r3, [r3, #0] 800d5f8: 681b ldr r3, [r3, #0] 800d5fa: f003 0320 and.w r3, r3, #32 800d5fe: 2b20 cmp r3, #32 800d600: d030 beq.n 800d664 { /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); 800d602: 68fb ldr r3, [r7, #12] 800d604: 681b ldr r3, [r3, #0] 800d606: 685a ldr r2, [r3, #4] 800d608: 68fb ldr r3, [r7, #12] 800d60a: 681b ldr r3, [r3, #0] 800d60c: f022 0220 bic.w r2, r2, #32 800d610: 605a str r2, [r3, #4] } } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) 800d612: 68ba ldr r2, [r7, #8] 800d614: 2164 movs r1, #100 @ 0x64 800d616: 68f8 ldr r0, [r7, #12] 800d618: f000 f9dc bl 800d9d4 800d61c: 4603 mov r3, r0 800d61e: 2b00 cmp r3, #0 800d620: d005 beq.n 800d62e { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800d622: 68fb ldr r3, [r7, #12] 800d624: 6e1b ldr r3, [r3, #96] @ 0x60 800d626: f043 0220 orr.w r2, r3, #32 800d62a: 68fb ldr r3, [r7, #12] 800d62c: 661a str r2, [r3, #96] @ 0x60 } /* Disable Rx/Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); 800d62e: 68fb ldr r3, [r7, #12] 800d630: 681b ldr r3, [r3, #0] 800d632: 685a ldr r2, [r3, #4] 800d634: 68fb ldr r3, [r7, #12] 800d636: 681b ldr r3, [r3, #0] 800d638: f022 0203 bic.w r2, r2, #3 800d63c: 605a str r2, [r3, #4] hspi->TxXferCount = 0U; 800d63e: 68fb ldr r3, [r7, #12] 800d640: 2200 movs r2, #0 800d642: 87da strh r2, [r3, #62] @ 0x3e hspi->RxXferCount = 0U; 800d644: 68fb ldr r3, [r7, #12] 800d646: 2200 movs r2, #0 800d648: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->State = HAL_SPI_STATE_READY; 800d64c: 68fb ldr r3, [r7, #12] 800d64e: 2201 movs r2, #1 800d650: f883 205d strb.w r2, [r3, #93] @ 0x5d SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } #endif /* USE_SPI_CRC */ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800d654: 68fb ldr r3, [r7, #12] 800d656: 6e1b ldr r3, [r3, #96] @ 0x60 800d658: 2b00 cmp r3, #0 800d65a: d003 beq.n 800d664 { /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 800d65c: 68f8 ldr r0, [r7, #12] 800d65e: f7ff ff61 bl 800d524 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; 800d662: e002 b.n 800d66a } /* Call user TxRx complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->TxRxCpltCallback(hspi); #else HAL_SPI_TxRxCpltCallback(hspi); 800d664: 68f8 ldr r0, [r7, #12] 800d666: f7f7 fde1 bl 800522c #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800d66a: 3710 adds r7, #16 800d66c: 46bd mov sp, r7 800d66e: bd80 pop {r7, pc} 0800d670 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { 800d670: b580 push {r7, lr} 800d672: b084 sub sp, #16 800d674: af00 add r7, sp, #0 800d676: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800d678: 687b ldr r3, [r7, #4] 800d67a: 6a9b ldr r3, [r3, #40] @ 0x28 800d67c: 60fb str r3, [r7, #12] /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->RxHalfCpltCallback(hspi); #else HAL_SPI_RxHalfCpltCallback(hspi); 800d67e: 68f8 ldr r0, [r7, #12] 800d680: f7ff ff3c bl 800d4fc #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800d684: bf00 nop 800d686: 3710 adds r7, #16 800d688: 46bd mov sp, r7 800d68a: bd80 pop {r7, pc} 0800d68c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { 800d68c: b580 push {r7, lr} 800d68e: b084 sub sp, #16 800d690: af00 add r7, sp, #0 800d692: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800d694: 687b ldr r3, [r7, #4] 800d696: 6a9b ldr r3, [r3, #40] @ 0x28 800d698: 60fb str r3, [r7, #12] /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->TxRxHalfCpltCallback(hspi); #else HAL_SPI_TxRxHalfCpltCallback(hspi); 800d69a: 68f8 ldr r0, [r7, #12] 800d69c: f7ff ff38 bl 800d510 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800d6a0: bf00 nop 800d6a2: 3710 adds r7, #16 800d6a4: 46bd mov sp, r7 800d6a6: bd80 pop {r7, pc} 0800d6a8 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { 800d6a8: b580 push {r7, lr} 800d6aa: b084 sub sp, #16 800d6ac: af00 add r7, sp, #0 800d6ae: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800d6b0: 687b ldr r3, [r7, #4] 800d6b2: 6a9b ldr r3, [r3, #40] @ 0x28 800d6b4: 60fb str r3, [r7, #12] /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); 800d6b6: 68fb ldr r3, [r7, #12] 800d6b8: 681b ldr r3, [r3, #0] 800d6ba: 685a ldr r2, [r3, #4] 800d6bc: 68fb ldr r3, [r7, #12] 800d6be: 681b ldr r3, [r3, #0] 800d6c0: f022 0203 bic.w r2, r2, #3 800d6c4: 605a str r2, [r3, #4] SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); 800d6c6: 68fb ldr r3, [r7, #12] 800d6c8: 6e1b ldr r3, [r3, #96] @ 0x60 800d6ca: f043 0210 orr.w r2, r3, #16 800d6ce: 68fb ldr r3, [r7, #12] 800d6d0: 661a str r2, [r3, #96] @ 0x60 hspi->State = HAL_SPI_STATE_READY; 800d6d2: 68fb ldr r3, [r7, #12] 800d6d4: 2201 movs r2, #1 800d6d6: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 800d6da: 68f8 ldr r0, [r7, #12] 800d6dc: f7ff ff22 bl 800d524 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800d6e0: bf00 nop 800d6e2: 3710 adds r7, #16 800d6e4: 46bd mov sp, r7 800d6e6: bd80 pop {r7, pc} 0800d6e8 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { 800d6e8: b580 push {r7, lr} 800d6ea: b088 sub sp, #32 800d6ec: af00 add r7, sp, #0 800d6ee: 60f8 str r0, [r7, #12] 800d6f0: 60b9 str r1, [r7, #8] 800d6f2: 603b str r3, [r7, #0] 800d6f4: 4613 mov r3, r2 800d6f6: 71fb strb r3, [r7, #7] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 800d6f8: f7f8 feba bl 8006470 800d6fc: 4602 mov r2, r0 800d6fe: 6abb ldr r3, [r7, #40] @ 0x28 800d700: 1a9b subs r3, r3, r2 800d702: 683a ldr r2, [r7, #0] 800d704: 4413 add r3, r2 800d706: 61fb str r3, [r7, #28] tmp_tickstart = HAL_GetTick(); 800d708: f7f8 feb2 bl 8006470 800d70c: 61b8 str r0, [r7, #24] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); 800d70e: 4b39 ldr r3, [pc, #228] @ (800d7f4 ) 800d710: 681b ldr r3, [r3, #0] 800d712: 015b lsls r3, r3, #5 800d714: 0d1b lsrs r3, r3, #20 800d716: 69fa ldr r2, [r7, #28] 800d718: fb02 f303 mul.w r3, r2, r3 800d71c: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 800d71e: e055 b.n 800d7cc { if (Timeout != HAL_MAX_DELAY) 800d720: 683b ldr r3, [r7, #0] 800d722: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d726: d051 beq.n 800d7cc { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 800d728: f7f8 fea2 bl 8006470 800d72c: 4602 mov r2, r0 800d72e: 69bb ldr r3, [r7, #24] 800d730: 1ad3 subs r3, r2, r3 800d732: 69fa ldr r2, [r7, #28] 800d734: 429a cmp r2, r3 800d736: d902 bls.n 800d73e 800d738: 69fb ldr r3, [r7, #28] 800d73a: 2b00 cmp r3, #0 800d73c: d13d bne.n 800d7ba /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 800d73e: 68fb ldr r3, [r7, #12] 800d740: 681b ldr r3, [r3, #0] 800d742: 685a ldr r2, [r3, #4] 800d744: 68fb ldr r3, [r7, #12] 800d746: 681b ldr r3, [r3, #0] 800d748: f022 02e0 bic.w r2, r2, #224 @ 0xe0 800d74c: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800d74e: 68fb ldr r3, [r7, #12] 800d750: 685b ldr r3, [r3, #4] 800d752: f5b3 7f82 cmp.w r3, #260 @ 0x104 800d756: d111 bne.n 800d77c 800d758: 68fb ldr r3, [r7, #12] 800d75a: 689b ldr r3, [r3, #8] 800d75c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d760: d004 beq.n 800d76c || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800d762: 68fb ldr r3, [r7, #12] 800d764: 689b ldr r3, [r3, #8] 800d766: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d76a: d107 bne.n 800d77c { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800d76c: 68fb ldr r3, [r7, #12] 800d76e: 681b ldr r3, [r3, #0] 800d770: 681a ldr r2, [r3, #0] 800d772: 68fb ldr r3, [r7, #12] 800d774: 681b ldr r3, [r3, #0] 800d776: f022 0240 bic.w r2, r2, #64 @ 0x40 800d77a: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 800d77c: 68fb ldr r3, [r7, #12] 800d77e: 6a9b ldr r3, [r3, #40] @ 0x28 800d780: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d784: d10f bne.n 800d7a6 { SPI_RESET_CRC(hspi); 800d786: 68fb ldr r3, [r7, #12] 800d788: 681b ldr r3, [r3, #0] 800d78a: 681a ldr r2, [r3, #0] 800d78c: 68fb ldr r3, [r7, #12] 800d78e: 681b ldr r3, [r3, #0] 800d790: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800d794: 601a str r2, [r3, #0] 800d796: 68fb ldr r3, [r7, #12] 800d798: 681b ldr r3, [r3, #0] 800d79a: 681a ldr r2, [r3, #0] 800d79c: 68fb ldr r3, [r7, #12] 800d79e: 681b ldr r3, [r3, #0] 800d7a0: f442 5200 orr.w r2, r2, #8192 @ 0x2000 800d7a4: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 800d7a6: 68fb ldr r3, [r7, #12] 800d7a8: 2201 movs r2, #1 800d7aa: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 800d7ae: 68fb ldr r3, [r7, #12] 800d7b0: 2200 movs r2, #0 800d7b2: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800d7b6: 2303 movs r3, #3 800d7b8: e018 b.n 800d7ec } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 800d7ba: 697b ldr r3, [r7, #20] 800d7bc: 2b00 cmp r3, #0 800d7be: d102 bne.n 800d7c6 { tmp_timeout = 0U; 800d7c0: 2300 movs r3, #0 800d7c2: 61fb str r3, [r7, #28] 800d7c4: e002 b.n 800d7cc } else { count--; 800d7c6: 697b ldr r3, [r7, #20] 800d7c8: 3b01 subs r3, #1 800d7ca: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 800d7cc: 68fb ldr r3, [r7, #12] 800d7ce: 681b ldr r3, [r3, #0] 800d7d0: 689a ldr r2, [r3, #8] 800d7d2: 68bb ldr r3, [r7, #8] 800d7d4: 4013 ands r3, r2 800d7d6: 68ba ldr r2, [r7, #8] 800d7d8: 429a cmp r2, r3 800d7da: bf0c ite eq 800d7dc: 2301 moveq r3, #1 800d7de: 2300 movne r3, #0 800d7e0: b2db uxtb r3, r3 800d7e2: 461a mov r2, r3 800d7e4: 79fb ldrb r3, [r7, #7] 800d7e6: 429a cmp r2, r3 800d7e8: d19a bne.n 800d720 } } } return HAL_OK; 800d7ea: 2300 movs r3, #0 } 800d7ec: 4618 mov r0, r3 800d7ee: 3720 adds r7, #32 800d7f0: 46bd mov sp, r7 800d7f2: bd80 pop {r7, pc} 800d7f4: 2000000c .word 0x2000000c 0800d7f8 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { 800d7f8: b580 push {r7, lr} 800d7fa: b08a sub sp, #40 @ 0x28 800d7fc: af00 add r7, sp, #0 800d7fe: 60f8 str r0, [r7, #12] 800d800: 60b9 str r1, [r7, #8] 800d802: 607a str r2, [r7, #4] 800d804: 603b str r3, [r7, #0] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; 800d806: 2300 movs r3, #0 800d808: 75fb strb r3, [r7, #23] /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 800d80a: f7f8 fe31 bl 8006470 800d80e: 4602 mov r2, r0 800d810: 6b3b ldr r3, [r7, #48] @ 0x30 800d812: 1a9b subs r3, r3, r2 800d814: 683a ldr r2, [r7, #0] 800d816: 4413 add r3, r2 800d818: 627b str r3, [r7, #36] @ 0x24 tmp_tickstart = HAL_GetTick(); 800d81a: f7f8 fe29 bl 8006470 800d81e: 6238 str r0, [r7, #32] /* Initialize the 8bit temporary pointer */ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; 800d820: 68fb ldr r3, [r7, #12] 800d822: 681b ldr r3, [r3, #0] 800d824: 330c adds r3, #12 800d826: 61fb str r3, [r7, #28] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); 800d828: 4b3d ldr r3, [pc, #244] @ (800d920 ) 800d82a: 681a ldr r2, [r3, #0] 800d82c: 4613 mov r3, r2 800d82e: 009b lsls r3, r3, #2 800d830: 4413 add r3, r2 800d832: 00da lsls r2, r3, #3 800d834: 1ad3 subs r3, r2, r3 800d836: 0d1b lsrs r3, r3, #20 800d838: 6a7a ldr r2, [r7, #36] @ 0x24 800d83a: fb02 f303 mul.w r3, r2, r3 800d83e: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 800d840: e061 b.n 800d906 { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) 800d842: 68bb ldr r3, [r7, #8] 800d844: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 800d848: d107 bne.n 800d85a 800d84a: 687b ldr r3, [r7, #4] 800d84c: 2b00 cmp r3, #0 800d84e: d104 bne.n 800d85a { /* Flush Data Register by a blank read */ tmpreg8 = *ptmpreg8; 800d850: 69fb ldr r3, [r7, #28] 800d852: 781b ldrb r3, [r3, #0] 800d854: b2db uxtb r3, r3 800d856: 75fb strb r3, [r7, #23] /* To avoid GCC warning */ UNUSED(tmpreg8); 800d858: 7dfb ldrb r3, [r7, #23] } if (Timeout != HAL_MAX_DELAY) 800d85a: 683b ldr r3, [r7, #0] 800d85c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d860: d051 beq.n 800d906 { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 800d862: f7f8 fe05 bl 8006470 800d866: 4602 mov r2, r0 800d868: 6a3b ldr r3, [r7, #32] 800d86a: 1ad3 subs r3, r2, r3 800d86c: 6a7a ldr r2, [r7, #36] @ 0x24 800d86e: 429a cmp r2, r3 800d870: d902 bls.n 800d878 800d872: 6a7b ldr r3, [r7, #36] @ 0x24 800d874: 2b00 cmp r3, #0 800d876: d13d bne.n 800d8f4 /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 800d878: 68fb ldr r3, [r7, #12] 800d87a: 681b ldr r3, [r3, #0] 800d87c: 685a ldr r2, [r3, #4] 800d87e: 68fb ldr r3, [r7, #12] 800d880: 681b ldr r3, [r3, #0] 800d882: f022 02e0 bic.w r2, r2, #224 @ 0xe0 800d886: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800d888: 68fb ldr r3, [r7, #12] 800d88a: 685b ldr r3, [r3, #4] 800d88c: f5b3 7f82 cmp.w r3, #260 @ 0x104 800d890: d111 bne.n 800d8b6 800d892: 68fb ldr r3, [r7, #12] 800d894: 689b ldr r3, [r3, #8] 800d896: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d89a: d004 beq.n 800d8a6 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800d89c: 68fb ldr r3, [r7, #12] 800d89e: 689b ldr r3, [r3, #8] 800d8a0: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d8a4: d107 bne.n 800d8b6 { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800d8a6: 68fb ldr r3, [r7, #12] 800d8a8: 681b ldr r3, [r3, #0] 800d8aa: 681a ldr r2, [r3, #0] 800d8ac: 68fb ldr r3, [r7, #12] 800d8ae: 681b ldr r3, [r3, #0] 800d8b0: f022 0240 bic.w r2, r2, #64 @ 0x40 800d8b4: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 800d8b6: 68fb ldr r3, [r7, #12] 800d8b8: 6a9b ldr r3, [r3, #40] @ 0x28 800d8ba: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d8be: d10f bne.n 800d8e0 { SPI_RESET_CRC(hspi); 800d8c0: 68fb ldr r3, [r7, #12] 800d8c2: 681b ldr r3, [r3, #0] 800d8c4: 681a ldr r2, [r3, #0] 800d8c6: 68fb ldr r3, [r7, #12] 800d8c8: 681b ldr r3, [r3, #0] 800d8ca: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800d8ce: 601a str r2, [r3, #0] 800d8d0: 68fb ldr r3, [r7, #12] 800d8d2: 681b ldr r3, [r3, #0] 800d8d4: 681a ldr r2, [r3, #0] 800d8d6: 68fb ldr r3, [r7, #12] 800d8d8: 681b ldr r3, [r3, #0] 800d8da: f442 5200 orr.w r2, r2, #8192 @ 0x2000 800d8de: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 800d8e0: 68fb ldr r3, [r7, #12] 800d8e2: 2201 movs r2, #1 800d8e4: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 800d8e8: 68fb ldr r3, [r7, #12] 800d8ea: 2200 movs r2, #0 800d8ec: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800d8f0: 2303 movs r3, #3 800d8f2: e011 b.n 800d918 } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 800d8f4: 69bb ldr r3, [r7, #24] 800d8f6: 2b00 cmp r3, #0 800d8f8: d102 bne.n 800d900 { tmp_timeout = 0U; 800d8fa: 2300 movs r3, #0 800d8fc: 627b str r3, [r7, #36] @ 0x24 800d8fe: e002 b.n 800d906 } else { count--; 800d900: 69bb ldr r3, [r7, #24] 800d902: 3b01 subs r3, #1 800d904: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 800d906: 68fb ldr r3, [r7, #12] 800d908: 681b ldr r3, [r3, #0] 800d90a: 689a ldr r2, [r3, #8] 800d90c: 68bb ldr r3, [r7, #8] 800d90e: 4013 ands r3, r2 800d910: 687a ldr r2, [r7, #4] 800d912: 429a cmp r2, r3 800d914: d195 bne.n 800d842 } } } return HAL_OK; 800d916: 2300 movs r3, #0 } 800d918: 4618 mov r0, r3 800d91a: 3728 adds r7, #40 @ 0x28 800d91c: 46bd mov sp, r7 800d91e: bd80 pop {r7, pc} 800d920: 2000000c .word 0x2000000c 0800d924 : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 800d924: b580 push {r7, lr} 800d926: b086 sub sp, #24 800d928: af02 add r7, sp, #8 800d92a: 60f8 str r0, [r7, #12] 800d92c: 60b9 str r1, [r7, #8] 800d92e: 607a str r2, [r7, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800d930: 68fb ldr r3, [r7, #12] 800d932: 685b ldr r3, [r3, #4] 800d934: f5b3 7f82 cmp.w r3, #260 @ 0x104 800d938: d111 bne.n 800d95e 800d93a: 68fb ldr r3, [r7, #12] 800d93c: 689b ldr r3, [r3, #8] 800d93e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d942: d004 beq.n 800d94e || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800d944: 68fb ldr r3, [r7, #12] 800d946: 689b ldr r3, [r3, #8] 800d948: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d94c: d107 bne.n 800d95e { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800d94e: 68fb ldr r3, [r7, #12] 800d950: 681b ldr r3, [r3, #0] 800d952: 681a ldr r2, [r3, #0] 800d954: 68fb ldr r3, [r7, #12] 800d956: 681b ldr r3, [r3, #0] 800d958: f022 0240 bic.w r2, r2, #64 @ 0x40 800d95c: 601a str r2, [r3, #0] } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 800d95e: 687b ldr r3, [r7, #4] 800d960: 9300 str r3, [sp, #0] 800d962: 68bb ldr r3, [r7, #8] 800d964: 2200 movs r2, #0 800d966: 2180 movs r1, #128 @ 0x80 800d968: 68f8 ldr r0, [r7, #12] 800d96a: f7ff febd bl 800d6e8 800d96e: 4603 mov r3, r0 800d970: 2b00 cmp r3, #0 800d972: d007 beq.n 800d984 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800d974: 68fb ldr r3, [r7, #12] 800d976: 6e1b ldr r3, [r3, #96] @ 0x60 800d978: f043 0220 orr.w r2, r3, #32 800d97c: 68fb ldr r3, [r7, #12] 800d97e: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800d980: 2303 movs r3, #3 800d982: e023 b.n 800d9cc } if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800d984: 68fb ldr r3, [r7, #12] 800d986: 685b ldr r3, [r3, #4] 800d988: f5b3 7f82 cmp.w r3, #260 @ 0x104 800d98c: d11d bne.n 800d9ca 800d98e: 68fb ldr r3, [r7, #12] 800d990: 689b ldr r3, [r3, #8] 800d992: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d996: d004 beq.n 800d9a2 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800d998: 68fb ldr r3, [r7, #12] 800d99a: 689b ldr r3, [r3, #8] 800d99c: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d9a0: d113 bne.n 800d9ca { /* Empty the FRLVL fifo */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 800d9a2: 687b ldr r3, [r7, #4] 800d9a4: 9300 str r3, [sp, #0] 800d9a6: 68bb ldr r3, [r7, #8] 800d9a8: 2200 movs r2, #0 800d9aa: f44f 61c0 mov.w r1, #1536 @ 0x600 800d9ae: 68f8 ldr r0, [r7, #12] 800d9b0: f7ff ff22 bl 800d7f8 800d9b4: 4603 mov r3, r0 800d9b6: 2b00 cmp r3, #0 800d9b8: d007 beq.n 800d9ca { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800d9ba: 68fb ldr r3, [r7, #12] 800d9bc: 6e1b ldr r3, [r3, #96] @ 0x60 800d9be: f043 0220 orr.w r2, r3, #32 800d9c2: 68fb ldr r3, [r7, #12] 800d9c4: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800d9c6: 2303 movs r3, #3 800d9c8: e000 b.n 800d9cc } } return HAL_OK; 800d9ca: 2300 movs r3, #0 } 800d9cc: 4618 mov r0, r3 800d9ce: 3710 adds r7, #16 800d9d0: 46bd mov sp, r7 800d9d2: bd80 pop {r7, pc} 0800d9d4 : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 800d9d4: b580 push {r7, lr} 800d9d6: b086 sub sp, #24 800d9d8: af02 add r7, sp, #8 800d9da: 60f8 str r0, [r7, #12] 800d9dc: 60b9 str r1, [r7, #8] 800d9de: 607a str r2, [r7, #4] /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 800d9e0: 687b ldr r3, [r7, #4] 800d9e2: 9300 str r3, [sp, #0] 800d9e4: 68bb ldr r3, [r7, #8] 800d9e6: 2200 movs r2, #0 800d9e8: f44f 51c0 mov.w r1, #6144 @ 0x1800 800d9ec: 68f8 ldr r0, [r7, #12] 800d9ee: f7ff ff03 bl 800d7f8 800d9f2: 4603 mov r3, r0 800d9f4: 2b00 cmp r3, #0 800d9f6: d007 beq.n 800da08 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800d9f8: 68fb ldr r3, [r7, #12] 800d9fa: 6e1b ldr r3, [r3, #96] @ 0x60 800d9fc: f043 0220 orr.w r2, r3, #32 800da00: 68fb ldr r3, [r7, #12] 800da02: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800da04: 2303 movs r3, #3 800da06: e027 b.n 800da58 } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 800da08: 687b ldr r3, [r7, #4] 800da0a: 9300 str r3, [sp, #0] 800da0c: 68bb ldr r3, [r7, #8] 800da0e: 2200 movs r2, #0 800da10: 2180 movs r1, #128 @ 0x80 800da12: 68f8 ldr r0, [r7, #12] 800da14: f7ff fe68 bl 800d6e8 800da18: 4603 mov r3, r0 800da1a: 2b00 cmp r3, #0 800da1c: d007 beq.n 800da2e { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800da1e: 68fb ldr r3, [r7, #12] 800da20: 6e1b ldr r3, [r3, #96] @ 0x60 800da22: f043 0220 orr.w r2, r3, #32 800da26: 68fb ldr r3, [r7, #12] 800da28: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800da2a: 2303 movs r3, #3 800da2c: e014 b.n 800da58 } /* Control if the RX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 800da2e: 687b ldr r3, [r7, #4] 800da30: 9300 str r3, [sp, #0] 800da32: 68bb ldr r3, [r7, #8] 800da34: 2200 movs r2, #0 800da36: f44f 61c0 mov.w r1, #1536 @ 0x600 800da3a: 68f8 ldr r0, [r7, #12] 800da3c: f7ff fedc bl 800d7f8 800da40: 4603 mov r3, r0 800da42: 2b00 cmp r3, #0 800da44: d007 beq.n 800da56 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800da46: 68fb ldr r3, [r7, #12] 800da48: 6e1b ldr r3, [r3, #96] @ 0x60 800da4a: f043 0220 orr.w r2, r3, #32 800da4e: 68fb ldr r3, [r7, #12] 800da50: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800da52: 2303 movs r3, #3 800da54: e000 b.n 800da58 } return HAL_OK; 800da56: 2300 movs r3, #0 } 800da58: 4618 mov r0, r3 800da5a: 3710 adds r7, #16 800da5c: 46bd mov sp, r7 800da5e: bd80 pop {r7, pc} 0800da60 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800da60: b580 push {r7, lr} 800da62: b082 sub sp, #8 800da64: af00 add r7, sp, #0 800da66: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800da68: 687b ldr r3, [r7, #4] 800da6a: 2b00 cmp r3, #0 800da6c: d101 bne.n 800da72 { return HAL_ERROR; 800da6e: 2301 movs r3, #1 800da70: e049 b.n 800db06 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800da72: 687b ldr r3, [r7, #4] 800da74: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800da78: b2db uxtb r3, r3 800da7a: 2b00 cmp r3, #0 800da7c: d106 bne.n 800da8c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800da7e: 687b ldr r3, [r7, #4] 800da80: 2200 movs r2, #0 800da82: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800da86: 6878 ldr r0, [r7, #4] 800da88: f000 f841 bl 800db0e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800da8c: 687b ldr r3, [r7, #4] 800da8e: 2202 movs r2, #2 800da90: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800da94: 687b ldr r3, [r7, #4] 800da96: 681a ldr r2, [r3, #0] 800da98: 687b ldr r3, [r7, #4] 800da9a: 3304 adds r3, #4 800da9c: 4619 mov r1, r3 800da9e: 4610 mov r0, r2 800daa0: f000 fb28 bl 800e0f4 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800daa4: 687b ldr r3, [r7, #4] 800daa6: 2201 movs r2, #1 800daa8: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800daac: 687b ldr r3, [r7, #4] 800daae: 2201 movs r2, #1 800dab0: f883 203e strb.w r2, [r3, #62] @ 0x3e 800dab4: 687b ldr r3, [r7, #4] 800dab6: 2201 movs r2, #1 800dab8: f883 203f strb.w r2, [r3, #63] @ 0x3f 800dabc: 687b ldr r3, [r7, #4] 800dabe: 2201 movs r2, #1 800dac0: f883 2040 strb.w r2, [r3, #64] @ 0x40 800dac4: 687b ldr r3, [r7, #4] 800dac6: 2201 movs r2, #1 800dac8: f883 2041 strb.w r2, [r3, #65] @ 0x41 800dacc: 687b ldr r3, [r7, #4] 800dace: 2201 movs r2, #1 800dad0: f883 2042 strb.w r2, [r3, #66] @ 0x42 800dad4: 687b ldr r3, [r7, #4] 800dad6: 2201 movs r2, #1 800dad8: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800dadc: 687b ldr r3, [r7, #4] 800dade: 2201 movs r2, #1 800dae0: f883 2044 strb.w r2, [r3, #68] @ 0x44 800dae4: 687b ldr r3, [r7, #4] 800dae6: 2201 movs r2, #1 800dae8: f883 2045 strb.w r2, [r3, #69] @ 0x45 800daec: 687b ldr r3, [r7, #4] 800daee: 2201 movs r2, #1 800daf0: f883 2046 strb.w r2, [r3, #70] @ 0x46 800daf4: 687b ldr r3, [r7, #4] 800daf6: 2201 movs r2, #1 800daf8: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800dafc: 687b ldr r3, [r7, #4] 800dafe: 2201 movs r2, #1 800db00: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800db04: 2300 movs r3, #0 } 800db06: 4618 mov r0, r3 800db08: 3708 adds r7, #8 800db0a: 46bd mov sp, r7 800db0c: bd80 pop {r7, pc} 0800db0e : * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { 800db0e: b480 push {r7} 800db10: b083 sub sp, #12 800db12: af00 add r7, sp, #0 800db14: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } 800db16: bf00 nop 800db18: 370c adds r7, #12 800db1a: 46bd mov sp, r7 800db1c: f85d 7b04 ldr.w r7, [sp], #4 800db20: 4770 bx lr ... 0800db24 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800db24: b480 push {r7} 800db26: b085 sub sp, #20 800db28: af00 add r7, sp, #0 800db2a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800db2c: 687b ldr r3, [r7, #4] 800db2e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800db32: b2db uxtb r3, r3 800db34: 2b01 cmp r3, #1 800db36: d001 beq.n 800db3c { return HAL_ERROR; 800db38: 2301 movs r3, #1 800db3a: e036 b.n 800dbaa } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800db3c: 687b ldr r3, [r7, #4] 800db3e: 2202 movs r2, #2 800db40: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800db44: 687b ldr r3, [r7, #4] 800db46: 681b ldr r3, [r3, #0] 800db48: 68da ldr r2, [r3, #12] 800db4a: 687b ldr r3, [r7, #4] 800db4c: 681b ldr r3, [r3, #0] 800db4e: f042 0201 orr.w r2, r2, #1 800db52: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800db54: 687b ldr r3, [r7, #4] 800db56: 681b ldr r3, [r3, #0] 800db58: 4a17 ldr r2, [pc, #92] @ (800dbb8 ) 800db5a: 4293 cmp r3, r2 800db5c: d004 beq.n 800db68 800db5e: 687b ldr r3, [r7, #4] 800db60: 681b ldr r3, [r3, #0] 800db62: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800db66: d115 bne.n 800db94 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800db68: 687b ldr r3, [r7, #4] 800db6a: 681b ldr r3, [r3, #0] 800db6c: 689a ldr r2, [r3, #8] 800db6e: 4b13 ldr r3, [pc, #76] @ (800dbbc ) 800db70: 4013 ands r3, r2 800db72: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800db74: 68fb ldr r3, [r7, #12] 800db76: 2b06 cmp r3, #6 800db78: d015 beq.n 800dba6 800db7a: 68fb ldr r3, [r7, #12] 800db7c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800db80: d011 beq.n 800dba6 { __HAL_TIM_ENABLE(htim); 800db82: 687b ldr r3, [r7, #4] 800db84: 681b ldr r3, [r3, #0] 800db86: 681a ldr r2, [r3, #0] 800db88: 687b ldr r3, [r7, #4] 800db8a: 681b ldr r3, [r3, #0] 800db8c: f042 0201 orr.w r2, r2, #1 800db90: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800db92: e008 b.n 800dba6 } } else { __HAL_TIM_ENABLE(htim); 800db94: 687b ldr r3, [r7, #4] 800db96: 681b ldr r3, [r3, #0] 800db98: 681a ldr r2, [r3, #0] 800db9a: 687b ldr r3, [r7, #4] 800db9c: 681b ldr r3, [r3, #0] 800db9e: f042 0201 orr.w r2, r2, #1 800dba2: 601a str r2, [r3, #0] 800dba4: e000 b.n 800dba8 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800dba6: bf00 nop } /* Return function status */ return HAL_OK; 800dba8: 2300 movs r3, #0 } 800dbaa: 4618 mov r0, r3 800dbac: 3714 adds r7, #20 800dbae: 46bd mov sp, r7 800dbb0: f85d 7b04 ldr.w r7, [sp], #4 800dbb4: 4770 bx lr 800dbb6: bf00 nop 800dbb8: 40012c00 .word 0x40012c00 800dbbc: 00010007 .word 0x00010007 0800dbc0 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800dbc0: b580 push {r7, lr} 800dbc2: b082 sub sp, #8 800dbc4: af00 add r7, sp, #0 800dbc6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800dbc8: 687b ldr r3, [r7, #4] 800dbca: 2b00 cmp r3, #0 800dbcc: d101 bne.n 800dbd2 { return HAL_ERROR; 800dbce: 2301 movs r3, #1 800dbd0: e049 b.n 800dc66 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800dbd2: 687b ldr r3, [r7, #4] 800dbd4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800dbd8: b2db uxtb r3, r3 800dbda: 2b00 cmp r3, #0 800dbdc: d106 bne.n 800dbec { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800dbde: 687b ldr r3, [r7, #4] 800dbe0: 2200 movs r2, #0 800dbe2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800dbe6: 6878 ldr r0, [r7, #4] 800dbe8: f7f8 f988 bl 8005efc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800dbec: 687b ldr r3, [r7, #4] 800dbee: 2202 movs r2, #2 800dbf0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800dbf4: 687b ldr r3, [r7, #4] 800dbf6: 681a ldr r2, [r3, #0] 800dbf8: 687b ldr r3, [r7, #4] 800dbfa: 3304 adds r3, #4 800dbfc: 4619 mov r1, r3 800dbfe: 4610 mov r0, r2 800dc00: f000 fa78 bl 800e0f4 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800dc04: 687b ldr r3, [r7, #4] 800dc06: 2201 movs r2, #1 800dc08: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800dc0c: 687b ldr r3, [r7, #4] 800dc0e: 2201 movs r2, #1 800dc10: f883 203e strb.w r2, [r3, #62] @ 0x3e 800dc14: 687b ldr r3, [r7, #4] 800dc16: 2201 movs r2, #1 800dc18: f883 203f strb.w r2, [r3, #63] @ 0x3f 800dc1c: 687b ldr r3, [r7, #4] 800dc1e: 2201 movs r2, #1 800dc20: f883 2040 strb.w r2, [r3, #64] @ 0x40 800dc24: 687b ldr r3, [r7, #4] 800dc26: 2201 movs r2, #1 800dc28: f883 2041 strb.w r2, [r3, #65] @ 0x41 800dc2c: 687b ldr r3, [r7, #4] 800dc2e: 2201 movs r2, #1 800dc30: f883 2042 strb.w r2, [r3, #66] @ 0x42 800dc34: 687b ldr r3, [r7, #4] 800dc36: 2201 movs r2, #1 800dc38: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800dc3c: 687b ldr r3, [r7, #4] 800dc3e: 2201 movs r2, #1 800dc40: f883 2044 strb.w r2, [r3, #68] @ 0x44 800dc44: 687b ldr r3, [r7, #4] 800dc46: 2201 movs r2, #1 800dc48: f883 2045 strb.w r2, [r3, #69] @ 0x45 800dc4c: 687b ldr r3, [r7, #4] 800dc4e: 2201 movs r2, #1 800dc50: f883 2046 strb.w r2, [r3, #70] @ 0x46 800dc54: 687b ldr r3, [r7, #4] 800dc56: 2201 movs r2, #1 800dc58: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800dc5c: 687b ldr r3, [r7, #4] 800dc5e: 2201 movs r2, #1 800dc60: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800dc64: 2300 movs r3, #0 } 800dc66: 4618 mov r0, r3 800dc68: 3708 adds r7, #8 800dc6a: 46bd mov sp, r7 800dc6c: bd80 pop {r7, pc} 0800dc6e : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800dc6e: b580 push {r7, lr} 800dc70: b084 sub sp, #16 800dc72: af00 add r7, sp, #0 800dc74: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800dc76: 687b ldr r3, [r7, #4] 800dc78: 681b ldr r3, [r3, #0] 800dc7a: 68db ldr r3, [r3, #12] 800dc7c: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800dc7e: 687b ldr r3, [r7, #4] 800dc80: 681b ldr r3, [r3, #0] 800dc82: 691b ldr r3, [r3, #16] 800dc84: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800dc86: 68bb ldr r3, [r7, #8] 800dc88: f003 0302 and.w r3, r3, #2 800dc8c: 2b00 cmp r3, #0 800dc8e: d020 beq.n 800dcd2 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800dc90: 68fb ldr r3, [r7, #12] 800dc92: f003 0302 and.w r3, r3, #2 800dc96: 2b00 cmp r3, #0 800dc98: d01b beq.n 800dcd2 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800dc9a: 687b ldr r3, [r7, #4] 800dc9c: 681b ldr r3, [r3, #0] 800dc9e: f06f 0202 mvn.w r2, #2 800dca2: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800dca4: 687b ldr r3, [r7, #4] 800dca6: 2201 movs r2, #1 800dca8: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800dcaa: 687b ldr r3, [r7, #4] 800dcac: 681b ldr r3, [r3, #0] 800dcae: 699b ldr r3, [r3, #24] 800dcb0: f003 0303 and.w r3, r3, #3 800dcb4: 2b00 cmp r3, #0 800dcb6: d003 beq.n 800dcc0 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800dcb8: 6878 ldr r0, [r7, #4] 800dcba: f000 f9fd bl 800e0b8 800dcbe: e005 b.n 800dccc { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800dcc0: 6878 ldr r0, [r7, #4] 800dcc2: f000 f9ef bl 800e0a4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800dcc6: 6878 ldr r0, [r7, #4] 800dcc8: f000 fa00 bl 800e0cc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800dccc: 687b ldr r3, [r7, #4] 800dcce: 2200 movs r2, #0 800dcd0: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800dcd2: 68bb ldr r3, [r7, #8] 800dcd4: f003 0304 and.w r3, r3, #4 800dcd8: 2b00 cmp r3, #0 800dcda: d020 beq.n 800dd1e { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800dcdc: 68fb ldr r3, [r7, #12] 800dcde: f003 0304 and.w r3, r3, #4 800dce2: 2b00 cmp r3, #0 800dce4: d01b beq.n 800dd1e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800dce6: 687b ldr r3, [r7, #4] 800dce8: 681b ldr r3, [r3, #0] 800dcea: f06f 0204 mvn.w r2, #4 800dcee: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800dcf0: 687b ldr r3, [r7, #4] 800dcf2: 2202 movs r2, #2 800dcf4: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800dcf6: 687b ldr r3, [r7, #4] 800dcf8: 681b ldr r3, [r3, #0] 800dcfa: 699b ldr r3, [r3, #24] 800dcfc: f403 7340 and.w r3, r3, #768 @ 0x300 800dd00: 2b00 cmp r3, #0 800dd02: d003 beq.n 800dd0c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800dd04: 6878 ldr r0, [r7, #4] 800dd06: f000 f9d7 bl 800e0b8 800dd0a: e005 b.n 800dd18 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800dd0c: 6878 ldr r0, [r7, #4] 800dd0e: f000 f9c9 bl 800e0a4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800dd12: 6878 ldr r0, [r7, #4] 800dd14: f000 f9da bl 800e0cc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800dd18: 687b ldr r3, [r7, #4] 800dd1a: 2200 movs r2, #0 800dd1c: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800dd1e: 68bb ldr r3, [r7, #8] 800dd20: f003 0308 and.w r3, r3, #8 800dd24: 2b00 cmp r3, #0 800dd26: d020 beq.n 800dd6a { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800dd28: 68fb ldr r3, [r7, #12] 800dd2a: f003 0308 and.w r3, r3, #8 800dd2e: 2b00 cmp r3, #0 800dd30: d01b beq.n 800dd6a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800dd32: 687b ldr r3, [r7, #4] 800dd34: 681b ldr r3, [r3, #0] 800dd36: f06f 0208 mvn.w r2, #8 800dd3a: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800dd3c: 687b ldr r3, [r7, #4] 800dd3e: 2204 movs r2, #4 800dd40: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800dd42: 687b ldr r3, [r7, #4] 800dd44: 681b ldr r3, [r3, #0] 800dd46: 69db ldr r3, [r3, #28] 800dd48: f003 0303 and.w r3, r3, #3 800dd4c: 2b00 cmp r3, #0 800dd4e: d003 beq.n 800dd58 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800dd50: 6878 ldr r0, [r7, #4] 800dd52: f000 f9b1 bl 800e0b8 800dd56: e005 b.n 800dd64 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800dd58: 6878 ldr r0, [r7, #4] 800dd5a: f000 f9a3 bl 800e0a4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800dd5e: 6878 ldr r0, [r7, #4] 800dd60: f000 f9b4 bl 800e0cc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800dd64: 687b ldr r3, [r7, #4] 800dd66: 2200 movs r2, #0 800dd68: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800dd6a: 68bb ldr r3, [r7, #8] 800dd6c: f003 0310 and.w r3, r3, #16 800dd70: 2b00 cmp r3, #0 800dd72: d020 beq.n 800ddb6 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800dd74: 68fb ldr r3, [r7, #12] 800dd76: f003 0310 and.w r3, r3, #16 800dd7a: 2b00 cmp r3, #0 800dd7c: d01b beq.n 800ddb6 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800dd7e: 687b ldr r3, [r7, #4] 800dd80: 681b ldr r3, [r3, #0] 800dd82: f06f 0210 mvn.w r2, #16 800dd86: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800dd88: 687b ldr r3, [r7, #4] 800dd8a: 2208 movs r2, #8 800dd8c: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800dd8e: 687b ldr r3, [r7, #4] 800dd90: 681b ldr r3, [r3, #0] 800dd92: 69db ldr r3, [r3, #28] 800dd94: f403 7340 and.w r3, r3, #768 @ 0x300 800dd98: 2b00 cmp r3, #0 800dd9a: d003 beq.n 800dda4 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800dd9c: 6878 ldr r0, [r7, #4] 800dd9e: f000 f98b bl 800e0b8 800dda2: e005 b.n 800ddb0 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800dda4: 6878 ldr r0, [r7, #4] 800dda6: f000 f97d bl 800e0a4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800ddaa: 6878 ldr r0, [r7, #4] 800ddac: f000 f98e bl 800e0cc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800ddb0: 687b ldr r3, [r7, #4] 800ddb2: 2200 movs r2, #0 800ddb4: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800ddb6: 68bb ldr r3, [r7, #8] 800ddb8: f003 0301 and.w r3, r3, #1 800ddbc: 2b00 cmp r3, #0 800ddbe: d00c beq.n 800ddda { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800ddc0: 68fb ldr r3, [r7, #12] 800ddc2: f003 0301 and.w r3, r3, #1 800ddc6: 2b00 cmp r3, #0 800ddc8: d007 beq.n 800ddda { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800ddca: 687b ldr r3, [r7, #4] 800ddcc: 681b ldr r3, [r3, #0] 800ddce: f06f 0201 mvn.w r2, #1 800ddd2: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800ddd4: 6878 ldr r0, [r7, #4] 800ddd6: f7f7 fa11 bl 80051fc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800ddda: 68bb ldr r3, [r7, #8] 800dddc: f003 0380 and.w r3, r3, #128 @ 0x80 800dde0: 2b00 cmp r3, #0 800dde2: d104 bne.n 800ddee ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800dde4: 68bb ldr r3, [r7, #8] 800dde6: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800ddea: 2b00 cmp r3, #0 800ddec: d00c beq.n 800de08 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800ddee: 68fb ldr r3, [r7, #12] 800ddf0: f003 0380 and.w r3, r3, #128 @ 0x80 800ddf4: 2b00 cmp r3, #0 800ddf6: d007 beq.n 800de08 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800ddf8: 687b ldr r3, [r7, #4] 800ddfa: 681b ldr r3, [r3, #0] 800ddfc: f46f 5202 mvn.w r2, #8320 @ 0x2080 800de00: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800de02: 6878 ldr r0, [r7, #4] 800de04: f000 fcce bl 800e7a4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800de08: 68bb ldr r3, [r7, #8] 800de0a: f403 7380 and.w r3, r3, #256 @ 0x100 800de0e: 2b00 cmp r3, #0 800de10: d00c beq.n 800de2c { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800de12: 68fb ldr r3, [r7, #12] 800de14: f003 0380 and.w r3, r3, #128 @ 0x80 800de18: 2b00 cmp r3, #0 800de1a: d007 beq.n 800de2c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800de1c: 687b ldr r3, [r7, #4] 800de1e: 681b ldr r3, [r3, #0] 800de20: f46f 7280 mvn.w r2, #256 @ 0x100 800de24: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800de26: 6878 ldr r0, [r7, #4] 800de28: f000 fcc6 bl 800e7b8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800de2c: 68bb ldr r3, [r7, #8] 800de2e: f003 0340 and.w r3, r3, #64 @ 0x40 800de32: 2b00 cmp r3, #0 800de34: d00c beq.n 800de50 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800de36: 68fb ldr r3, [r7, #12] 800de38: f003 0340 and.w r3, r3, #64 @ 0x40 800de3c: 2b00 cmp r3, #0 800de3e: d007 beq.n 800de50 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800de40: 687b ldr r3, [r7, #4] 800de42: 681b ldr r3, [r3, #0] 800de44: f06f 0240 mvn.w r2, #64 @ 0x40 800de48: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800de4a: 6878 ldr r0, [r7, #4] 800de4c: f000 f948 bl 800e0e0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800de50: 68bb ldr r3, [r7, #8] 800de52: f003 0320 and.w r3, r3, #32 800de56: 2b00 cmp r3, #0 800de58: d00c beq.n 800de74 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800de5a: 68fb ldr r3, [r7, #12] 800de5c: f003 0320 and.w r3, r3, #32 800de60: 2b00 cmp r3, #0 800de62: d007 beq.n 800de74 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800de64: 687b ldr r3, [r7, #4] 800de66: 681b ldr r3, [r3, #0] 800de68: f06f 0220 mvn.w r2, #32 800de6c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800de6e: 6878 ldr r0, [r7, #4] 800de70: f000 fc8e bl 800e790 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800de74: bf00 nop 800de76: 3710 adds r7, #16 800de78: 46bd mov sp, r7 800de7a: bd80 pop {r7, pc} 0800de7c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 800de7c: b580 push {r7, lr} 800de7e: b086 sub sp, #24 800de80: af00 add r7, sp, #0 800de82: 60f8 str r0, [r7, #12] 800de84: 60b9 str r1, [r7, #8] 800de86: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800de88: 2300 movs r3, #0 800de8a: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 800de8c: 68fb ldr r3, [r7, #12] 800de8e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800de92: 2b01 cmp r3, #1 800de94: d101 bne.n 800de9a 800de96: 2302 movs r3, #2 800de98: e0ff b.n 800e09a 800de9a: 68fb ldr r3, [r7, #12] 800de9c: 2201 movs r2, #1 800de9e: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 800dea2: 687b ldr r3, [r7, #4] 800dea4: 2b14 cmp r3, #20 800dea6: f200 80f0 bhi.w 800e08a 800deaa: a201 add r2, pc, #4 @ (adr r2, 800deb0 ) 800deac: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800deb0: 0800df05 .word 0x0800df05 800deb4: 0800e08b .word 0x0800e08b 800deb8: 0800e08b .word 0x0800e08b 800debc: 0800e08b .word 0x0800e08b 800dec0: 0800df45 .word 0x0800df45 800dec4: 0800e08b .word 0x0800e08b 800dec8: 0800e08b .word 0x0800e08b 800decc: 0800e08b .word 0x0800e08b 800ded0: 0800df87 .word 0x0800df87 800ded4: 0800e08b .word 0x0800e08b 800ded8: 0800e08b .word 0x0800e08b 800dedc: 0800e08b .word 0x0800e08b 800dee0: 0800dfc7 .word 0x0800dfc7 800dee4: 0800e08b .word 0x0800e08b 800dee8: 0800e08b .word 0x0800e08b 800deec: 0800e08b .word 0x0800e08b 800def0: 0800e009 .word 0x0800e009 800def4: 0800e08b .word 0x0800e08b 800def8: 0800e08b .word 0x0800e08b 800defc: 0800e08b .word 0x0800e08b 800df00: 0800e049 .word 0x0800e049 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 800df04: 68fb ldr r3, [r7, #12] 800df06: 681b ldr r3, [r3, #0] 800df08: 68b9 ldr r1, [r7, #8] 800df0a: 4618 mov r0, r3 800df0c: f000 f95c bl 800e1c8 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800df10: 68fb ldr r3, [r7, #12] 800df12: 681b ldr r3, [r3, #0] 800df14: 699a ldr r2, [r3, #24] 800df16: 68fb ldr r3, [r7, #12] 800df18: 681b ldr r3, [r3, #0] 800df1a: f042 0208 orr.w r2, r2, #8 800df1e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800df20: 68fb ldr r3, [r7, #12] 800df22: 681b ldr r3, [r3, #0] 800df24: 699a ldr r2, [r3, #24] 800df26: 68fb ldr r3, [r7, #12] 800df28: 681b ldr r3, [r3, #0] 800df2a: f022 0204 bic.w r2, r2, #4 800df2e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800df30: 68fb ldr r3, [r7, #12] 800df32: 681b ldr r3, [r3, #0] 800df34: 6999 ldr r1, [r3, #24] 800df36: 68bb ldr r3, [r7, #8] 800df38: 691a ldr r2, [r3, #16] 800df3a: 68fb ldr r3, [r7, #12] 800df3c: 681b ldr r3, [r3, #0] 800df3e: 430a orrs r2, r1 800df40: 619a str r2, [r3, #24] break; 800df42: e0a5 b.n 800e090 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800df44: 68fb ldr r3, [r7, #12] 800df46: 681b ldr r3, [r3, #0] 800df48: 68b9 ldr r1, [r7, #8] 800df4a: 4618 mov r0, r3 800df4c: f000 f9ba bl 800e2c4 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800df50: 68fb ldr r3, [r7, #12] 800df52: 681b ldr r3, [r3, #0] 800df54: 699a ldr r2, [r3, #24] 800df56: 68fb ldr r3, [r7, #12] 800df58: 681b ldr r3, [r3, #0] 800df5a: f442 6200 orr.w r2, r2, #2048 @ 0x800 800df5e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800df60: 68fb ldr r3, [r7, #12] 800df62: 681b ldr r3, [r3, #0] 800df64: 699a ldr r2, [r3, #24] 800df66: 68fb ldr r3, [r7, #12] 800df68: 681b ldr r3, [r3, #0] 800df6a: f422 6280 bic.w r2, r2, #1024 @ 0x400 800df6e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800df70: 68fb ldr r3, [r7, #12] 800df72: 681b ldr r3, [r3, #0] 800df74: 6999 ldr r1, [r3, #24] 800df76: 68bb ldr r3, [r7, #8] 800df78: 691b ldr r3, [r3, #16] 800df7a: 021a lsls r2, r3, #8 800df7c: 68fb ldr r3, [r7, #12] 800df7e: 681b ldr r3, [r3, #0] 800df80: 430a orrs r2, r1 800df82: 619a str r2, [r3, #24] break; 800df84: e084 b.n 800e090 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800df86: 68fb ldr r3, [r7, #12] 800df88: 681b ldr r3, [r3, #0] 800df8a: 68b9 ldr r1, [r7, #8] 800df8c: 4618 mov r0, r3 800df8e: f000 fa15 bl 800e3bc /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800df92: 68fb ldr r3, [r7, #12] 800df94: 681b ldr r3, [r3, #0] 800df96: 69da ldr r2, [r3, #28] 800df98: 68fb ldr r3, [r7, #12] 800df9a: 681b ldr r3, [r3, #0] 800df9c: f042 0208 orr.w r2, r2, #8 800dfa0: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800dfa2: 68fb ldr r3, [r7, #12] 800dfa4: 681b ldr r3, [r3, #0] 800dfa6: 69da ldr r2, [r3, #28] 800dfa8: 68fb ldr r3, [r7, #12] 800dfaa: 681b ldr r3, [r3, #0] 800dfac: f022 0204 bic.w r2, r2, #4 800dfb0: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 800dfb2: 68fb ldr r3, [r7, #12] 800dfb4: 681b ldr r3, [r3, #0] 800dfb6: 69d9 ldr r1, [r3, #28] 800dfb8: 68bb ldr r3, [r7, #8] 800dfba: 691a ldr r2, [r3, #16] 800dfbc: 68fb ldr r3, [r7, #12] 800dfbe: 681b ldr r3, [r3, #0] 800dfc0: 430a orrs r2, r1 800dfc2: 61da str r2, [r3, #28] break; 800dfc4: e064 b.n 800e090 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800dfc6: 68fb ldr r3, [r7, #12] 800dfc8: 681b ldr r3, [r3, #0] 800dfca: 68b9 ldr r1, [r7, #8] 800dfcc: 4618 mov r0, r3 800dfce: f000 fa6f bl 800e4b0 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800dfd2: 68fb ldr r3, [r7, #12] 800dfd4: 681b ldr r3, [r3, #0] 800dfd6: 69da ldr r2, [r3, #28] 800dfd8: 68fb ldr r3, [r7, #12] 800dfda: 681b ldr r3, [r3, #0] 800dfdc: f442 6200 orr.w r2, r2, #2048 @ 0x800 800dfe0: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800dfe2: 68fb ldr r3, [r7, #12] 800dfe4: 681b ldr r3, [r3, #0] 800dfe6: 69da ldr r2, [r3, #28] 800dfe8: 68fb ldr r3, [r7, #12] 800dfea: 681b ldr r3, [r3, #0] 800dfec: f422 6280 bic.w r2, r2, #1024 @ 0x400 800dff0: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800dff2: 68fb ldr r3, [r7, #12] 800dff4: 681b ldr r3, [r3, #0] 800dff6: 69d9 ldr r1, [r3, #28] 800dff8: 68bb ldr r3, [r7, #8] 800dffa: 691b ldr r3, [r3, #16] 800dffc: 021a lsls r2, r3, #8 800dffe: 68fb ldr r3, [r7, #12] 800e000: 681b ldr r3, [r3, #0] 800e002: 430a orrs r2, r1 800e004: 61da str r2, [r3, #28] break; 800e006: e043 b.n 800e090 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 800e008: 68fb ldr r3, [r7, #12] 800e00a: 681b ldr r3, [r3, #0] 800e00c: 68b9 ldr r1, [r7, #8] 800e00e: 4618 mov r0, r3 800e010: f000 faac bl 800e56c /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 800e014: 68fb ldr r3, [r7, #12] 800e016: 681b ldr r3, [r3, #0] 800e018: 6d5a ldr r2, [r3, #84] @ 0x54 800e01a: 68fb ldr r3, [r7, #12] 800e01c: 681b ldr r3, [r3, #0] 800e01e: f042 0208 orr.w r2, r2, #8 800e022: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 800e024: 68fb ldr r3, [r7, #12] 800e026: 681b ldr r3, [r3, #0] 800e028: 6d5a ldr r2, [r3, #84] @ 0x54 800e02a: 68fb ldr r3, [r7, #12] 800e02c: 681b ldr r3, [r3, #0] 800e02e: f022 0204 bic.w r2, r2, #4 800e032: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800e034: 68fb ldr r3, [r7, #12] 800e036: 681b ldr r3, [r3, #0] 800e038: 6d59 ldr r1, [r3, #84] @ 0x54 800e03a: 68bb ldr r3, [r7, #8] 800e03c: 691a ldr r2, [r3, #16] 800e03e: 68fb ldr r3, [r7, #12] 800e040: 681b ldr r3, [r3, #0] 800e042: 430a orrs r2, r1 800e044: 655a str r2, [r3, #84] @ 0x54 break; 800e046: e023 b.n 800e090 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 800e048: 68fb ldr r3, [r7, #12] 800e04a: 681b ldr r3, [r3, #0] 800e04c: 68b9 ldr r1, [r7, #8] 800e04e: 4618 mov r0, r3 800e050: f000 fae4 bl 800e61c /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800e054: 68fb ldr r3, [r7, #12] 800e056: 681b ldr r3, [r3, #0] 800e058: 6d5a ldr r2, [r3, #84] @ 0x54 800e05a: 68fb ldr r3, [r7, #12] 800e05c: 681b ldr r3, [r3, #0] 800e05e: f442 6200 orr.w r2, r2, #2048 @ 0x800 800e062: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 800e064: 68fb ldr r3, [r7, #12] 800e066: 681b ldr r3, [r3, #0] 800e068: 6d5a ldr r2, [r3, #84] @ 0x54 800e06a: 68fb ldr r3, [r7, #12] 800e06c: 681b ldr r3, [r3, #0] 800e06e: f422 6280 bic.w r2, r2, #1024 @ 0x400 800e072: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800e074: 68fb ldr r3, [r7, #12] 800e076: 681b ldr r3, [r3, #0] 800e078: 6d59 ldr r1, [r3, #84] @ 0x54 800e07a: 68bb ldr r3, [r7, #8] 800e07c: 691b ldr r3, [r3, #16] 800e07e: 021a lsls r2, r3, #8 800e080: 68fb ldr r3, [r7, #12] 800e082: 681b ldr r3, [r3, #0] 800e084: 430a orrs r2, r1 800e086: 655a str r2, [r3, #84] @ 0x54 break; 800e088: e002 b.n 800e090 } default: status = HAL_ERROR; 800e08a: 2301 movs r3, #1 800e08c: 75fb strb r3, [r7, #23] break; 800e08e: bf00 nop } __HAL_UNLOCK(htim); 800e090: 68fb ldr r3, [r7, #12] 800e092: 2200 movs r2, #0 800e094: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800e098: 7dfb ldrb r3, [r7, #23] } 800e09a: 4618 mov r0, r3 800e09c: 3718 adds r7, #24 800e09e: 46bd mov sp, r7 800e0a0: bd80 pop {r7, pc} 800e0a2: bf00 nop 0800e0a4 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800e0a4: b480 push {r7} 800e0a6: b083 sub sp, #12 800e0a8: af00 add r7, sp, #0 800e0aa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800e0ac: bf00 nop 800e0ae: 370c adds r7, #12 800e0b0: 46bd mov sp, r7 800e0b2: f85d 7b04 ldr.w r7, [sp], #4 800e0b6: 4770 bx lr 0800e0b8 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800e0b8: b480 push {r7} 800e0ba: b083 sub sp, #12 800e0bc: af00 add r7, sp, #0 800e0be: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800e0c0: bf00 nop 800e0c2: 370c adds r7, #12 800e0c4: 46bd mov sp, r7 800e0c6: f85d 7b04 ldr.w r7, [sp], #4 800e0ca: 4770 bx lr 0800e0cc : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800e0cc: b480 push {r7} 800e0ce: b083 sub sp, #12 800e0d0: af00 add r7, sp, #0 800e0d2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 800e0d4: bf00 nop 800e0d6: 370c adds r7, #12 800e0d8: 46bd mov sp, r7 800e0da: f85d 7b04 ldr.w r7, [sp], #4 800e0de: 4770 bx lr 0800e0e0 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800e0e0: b480 push {r7} 800e0e2: b083 sub sp, #12 800e0e4: af00 add r7, sp, #0 800e0e6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800e0e8: bf00 nop 800e0ea: 370c adds r7, #12 800e0ec: 46bd mov sp, r7 800e0ee: f85d 7b04 ldr.w r7, [sp], #4 800e0f2: 4770 bx lr 0800e0f4 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 800e0f4: b480 push {r7} 800e0f6: b085 sub sp, #20 800e0f8: af00 add r7, sp, #0 800e0fa: 6078 str r0, [r7, #4] 800e0fc: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800e0fe: 687b ldr r3, [r7, #4] 800e100: 681b ldr r3, [r3, #0] 800e102: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800e104: 687b ldr r3, [r7, #4] 800e106: 4a2d ldr r2, [pc, #180] @ (800e1bc ) 800e108: 4293 cmp r3, r2 800e10a: d003 beq.n 800e114 800e10c: 687b ldr r3, [r7, #4] 800e10e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e112: d108 bne.n 800e126 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800e114: 68fb ldr r3, [r7, #12] 800e116: f023 0370 bic.w r3, r3, #112 @ 0x70 800e11a: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 800e11c: 683b ldr r3, [r7, #0] 800e11e: 685b ldr r3, [r3, #4] 800e120: 68fa ldr r2, [r7, #12] 800e122: 4313 orrs r3, r2 800e124: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800e126: 687b ldr r3, [r7, #4] 800e128: 4a24 ldr r2, [pc, #144] @ (800e1bc ) 800e12a: 4293 cmp r3, r2 800e12c: d00b beq.n 800e146 800e12e: 687b ldr r3, [r7, #4] 800e130: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e134: d007 beq.n 800e146 800e136: 687b ldr r3, [r7, #4] 800e138: 4a21 ldr r2, [pc, #132] @ (800e1c0 ) 800e13a: 4293 cmp r3, r2 800e13c: d003 beq.n 800e146 800e13e: 687b ldr r3, [r7, #4] 800e140: 4a20 ldr r2, [pc, #128] @ (800e1c4 ) 800e142: 4293 cmp r3, r2 800e144: d108 bne.n 800e158 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800e146: 68fb ldr r3, [r7, #12] 800e148: f423 7340 bic.w r3, r3, #768 @ 0x300 800e14c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800e14e: 683b ldr r3, [r7, #0] 800e150: 68db ldr r3, [r3, #12] 800e152: 68fa ldr r2, [r7, #12] 800e154: 4313 orrs r3, r2 800e156: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800e158: 68fb ldr r3, [r7, #12] 800e15a: f023 0280 bic.w r2, r3, #128 @ 0x80 800e15e: 683b ldr r3, [r7, #0] 800e160: 695b ldr r3, [r3, #20] 800e162: 4313 orrs r3, r2 800e164: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800e166: 683b ldr r3, [r7, #0] 800e168: 689a ldr r2, [r3, #8] 800e16a: 687b ldr r3, [r7, #4] 800e16c: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800e16e: 683b ldr r3, [r7, #0] 800e170: 681a ldr r2, [r3, #0] 800e172: 687b ldr r3, [r7, #4] 800e174: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800e176: 687b ldr r3, [r7, #4] 800e178: 4a10 ldr r2, [pc, #64] @ (800e1bc ) 800e17a: 4293 cmp r3, r2 800e17c: d007 beq.n 800e18e 800e17e: 687b ldr r3, [r7, #4] 800e180: 4a0f ldr r2, [pc, #60] @ (800e1c0 ) 800e182: 4293 cmp r3, r2 800e184: d003 beq.n 800e18e 800e186: 687b ldr r3, [r7, #4] 800e188: 4a0e ldr r2, [pc, #56] @ (800e1c4 ) 800e18a: 4293 cmp r3, r2 800e18c: d103 bne.n 800e196 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800e18e: 683b ldr r3, [r7, #0] 800e190: 691a ldr r2, [r3, #16] 800e192: 687b ldr r3, [r7, #4] 800e194: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 800e196: 687b ldr r3, [r7, #4] 800e198: 681b ldr r3, [r3, #0] 800e19a: f043 0204 orr.w r2, r3, #4 800e19e: 687b ldr r3, [r7, #4] 800e1a0: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800e1a2: 687b ldr r3, [r7, #4] 800e1a4: 2201 movs r2, #1 800e1a6: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 800e1a8: 687b ldr r3, [r7, #4] 800e1aa: 68fa ldr r2, [r7, #12] 800e1ac: 601a str r2, [r3, #0] } 800e1ae: bf00 nop 800e1b0: 3714 adds r7, #20 800e1b2: 46bd mov sp, r7 800e1b4: f85d 7b04 ldr.w r7, [sp], #4 800e1b8: 4770 bx lr 800e1ba: bf00 nop 800e1bc: 40012c00 .word 0x40012c00 800e1c0: 40014400 .word 0x40014400 800e1c4: 40014800 .word 0x40014800 0800e1c8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800e1c8: b480 push {r7} 800e1ca: b087 sub sp, #28 800e1cc: af00 add r7, sp, #0 800e1ce: 6078 str r0, [r7, #4] 800e1d0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800e1d2: 687b ldr r3, [r7, #4] 800e1d4: 6a1b ldr r3, [r3, #32] 800e1d6: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 800e1d8: 687b ldr r3, [r7, #4] 800e1da: 6a1b ldr r3, [r3, #32] 800e1dc: f023 0201 bic.w r2, r3, #1 800e1e0: 687b ldr r3, [r7, #4] 800e1e2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800e1e4: 687b ldr r3, [r7, #4] 800e1e6: 685b ldr r3, [r3, #4] 800e1e8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800e1ea: 687b ldr r3, [r7, #4] 800e1ec: 699b ldr r3, [r3, #24] 800e1ee: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800e1f0: 68fb ldr r3, [r7, #12] 800e1f2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800e1f6: f023 0370 bic.w r3, r3, #112 @ 0x70 800e1fa: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 800e1fc: 68fb ldr r3, [r7, #12] 800e1fe: f023 0303 bic.w r3, r3, #3 800e202: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800e204: 683b ldr r3, [r7, #0] 800e206: 681b ldr r3, [r3, #0] 800e208: 68fa ldr r2, [r7, #12] 800e20a: 4313 orrs r3, r2 800e20c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800e20e: 697b ldr r3, [r7, #20] 800e210: f023 0302 bic.w r3, r3, #2 800e214: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800e216: 683b ldr r3, [r7, #0] 800e218: 689b ldr r3, [r3, #8] 800e21a: 697a ldr r2, [r7, #20] 800e21c: 4313 orrs r3, r2 800e21e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 800e220: 687b ldr r3, [r7, #4] 800e222: 4a25 ldr r2, [pc, #148] @ (800e2b8 ) 800e224: 4293 cmp r3, r2 800e226: d007 beq.n 800e238 800e228: 687b ldr r3, [r7, #4] 800e22a: 4a24 ldr r2, [pc, #144] @ (800e2bc ) 800e22c: 4293 cmp r3, r2 800e22e: d003 beq.n 800e238 800e230: 687b ldr r3, [r7, #4] 800e232: 4a23 ldr r2, [pc, #140] @ (800e2c0 ) 800e234: 4293 cmp r3, r2 800e236: d10e bne.n 800e256 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 1N: Reset the CC1NE Bit */ TIMx->CCER &= ~TIM_CCER_CC1NE; 800e238: 687b ldr r3, [r7, #4] 800e23a: 6a1b ldr r3, [r3, #32] 800e23c: f023 0204 bic.w r2, r3, #4 800e240: 687b ldr r3, [r7, #4] 800e242: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 800e244: 697b ldr r3, [r7, #20] 800e246: f023 0308 bic.w r3, r3, #8 800e24a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 800e24c: 683b ldr r3, [r7, #0] 800e24e: 68db ldr r3, [r3, #12] 800e250: 697a ldr r2, [r7, #20] 800e252: 4313 orrs r3, r2 800e254: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800e256: 687b ldr r3, [r7, #4] 800e258: 4a17 ldr r2, [pc, #92] @ (800e2b8 ) 800e25a: 4293 cmp r3, r2 800e25c: d007 beq.n 800e26e 800e25e: 687b ldr r3, [r7, #4] 800e260: 4a17 ldr r2, [pc, #92] @ (800e2c0 ) 800e262: 4293 cmp r3, r2 800e264: d003 beq.n 800e26e 800e266: 687b ldr r3, [r7, #4] 800e268: 4a14 ldr r2, [pc, #80] @ (800e2bc ) 800e26a: 4293 cmp r3, r2 800e26c: d111 bne.n 800e292 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800e26e: 693b ldr r3, [r7, #16] 800e270: f423 7380 bic.w r3, r3, #256 @ 0x100 800e274: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800e276: 693b ldr r3, [r7, #16] 800e278: f423 7300 bic.w r3, r3, #512 @ 0x200 800e27c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800e27e: 683b ldr r3, [r7, #0] 800e280: 695b ldr r3, [r3, #20] 800e282: 693a ldr r2, [r7, #16] 800e284: 4313 orrs r3, r2 800e286: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800e288: 683b ldr r3, [r7, #0] 800e28a: 699b ldr r3, [r3, #24] 800e28c: 693a ldr r2, [r7, #16] 800e28e: 4313 orrs r3, r2 800e290: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800e292: 687b ldr r3, [r7, #4] 800e294: 693a ldr r2, [r7, #16] 800e296: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800e298: 687b ldr r3, [r7, #4] 800e29a: 68fa ldr r2, [r7, #12] 800e29c: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800e29e: 683b ldr r3, [r7, #0] 800e2a0: 685a ldr r2, [r3, #4] 800e2a2: 687b ldr r3, [r7, #4] 800e2a4: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800e2a6: 687b ldr r3, [r7, #4] 800e2a8: 697a ldr r2, [r7, #20] 800e2aa: 621a str r2, [r3, #32] } 800e2ac: bf00 nop 800e2ae: 371c adds r7, #28 800e2b0: 46bd mov sp, r7 800e2b2: f85d 7b04 ldr.w r7, [sp], #4 800e2b6: 4770 bx lr 800e2b8: 40012c00 .word 0x40012c00 800e2bc: 40014800 .word 0x40014800 800e2c0: 40014400 .word 0x40014400 0800e2c4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800e2c4: b480 push {r7} 800e2c6: b087 sub sp, #28 800e2c8: af00 add r7, sp, #0 800e2ca: 6078 str r0, [r7, #4] 800e2cc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800e2ce: 687b ldr r3, [r7, #4] 800e2d0: 6a1b ldr r3, [r3, #32] 800e2d2: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 800e2d4: 687b ldr r3, [r7, #4] 800e2d6: 6a1b ldr r3, [r3, #32] 800e2d8: f023 0210 bic.w r2, r3, #16 800e2dc: 687b ldr r3, [r7, #4] 800e2de: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800e2e0: 687b ldr r3, [r7, #4] 800e2e2: 685b ldr r3, [r3, #4] 800e2e4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800e2e6: 687b ldr r3, [r7, #4] 800e2e8: 699b ldr r3, [r3, #24] 800e2ea: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 800e2ec: 68fb ldr r3, [r7, #12] 800e2ee: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800e2f2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800e2f6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 800e2f8: 68fb ldr r3, [r7, #12] 800e2fa: f423 7340 bic.w r3, r3, #768 @ 0x300 800e2fe: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800e300: 683b ldr r3, [r7, #0] 800e302: 681b ldr r3, [r3, #0] 800e304: 021b lsls r3, r3, #8 800e306: 68fa ldr r2, [r7, #12] 800e308: 4313 orrs r3, r2 800e30a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 800e30c: 697b ldr r3, [r7, #20] 800e30e: f023 0320 bic.w r3, r3, #32 800e312: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 800e314: 683b ldr r3, [r7, #0] 800e316: 689b ldr r3, [r3, #8] 800e318: 011b lsls r3, r3, #4 800e31a: 697a ldr r2, [r7, #20] 800e31c: 4313 orrs r3, r2 800e31e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800e320: 687b ldr r3, [r7, #4] 800e322: 4a23 ldr r2, [pc, #140] @ (800e3b0 ) 800e324: 4293 cmp r3, r2 800e326: d10f bne.n 800e348 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 2N: Reset the CC2NE Bit */ TIMx->CCER &= ~TIM_CCER_CC2NE; 800e328: 687b ldr r3, [r7, #4] 800e32a: 6a1b ldr r3, [r3, #32] 800e32c: f023 0240 bic.w r2, r3, #64 @ 0x40 800e330: 687b ldr r3, [r7, #4] 800e332: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800e334: 697b ldr r3, [r7, #20] 800e336: f023 0380 bic.w r3, r3, #128 @ 0x80 800e33a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 800e33c: 683b ldr r3, [r7, #0] 800e33e: 68db ldr r3, [r3, #12] 800e340: 011b lsls r3, r3, #4 800e342: 697a ldr r2, [r7, #20] 800e344: 4313 orrs r3, r2 800e346: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800e348: 687b ldr r3, [r7, #4] 800e34a: 4a19 ldr r2, [pc, #100] @ (800e3b0 ) 800e34c: 4293 cmp r3, r2 800e34e: d007 beq.n 800e360 800e350: 687b ldr r3, [r7, #4] 800e352: 4a18 ldr r2, [pc, #96] @ (800e3b4 ) 800e354: 4293 cmp r3, r2 800e356: d003 beq.n 800e360 800e358: 687b ldr r3, [r7, #4] 800e35a: 4a17 ldr r2, [pc, #92] @ (800e3b8 ) 800e35c: 4293 cmp r3, r2 800e35e: d113 bne.n 800e388 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 800e360: 693b ldr r3, [r7, #16] 800e362: f423 6380 bic.w r3, r3, #1024 @ 0x400 800e366: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 800e368: 693b ldr r3, [r7, #16] 800e36a: f423 6300 bic.w r3, r3, #2048 @ 0x800 800e36e: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 800e370: 683b ldr r3, [r7, #0] 800e372: 695b ldr r3, [r3, #20] 800e374: 009b lsls r3, r3, #2 800e376: 693a ldr r2, [r7, #16] 800e378: 4313 orrs r3, r2 800e37a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 800e37c: 683b ldr r3, [r7, #0] 800e37e: 699b ldr r3, [r3, #24] 800e380: 009b lsls r3, r3, #2 800e382: 693a ldr r2, [r7, #16] 800e384: 4313 orrs r3, r2 800e386: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800e388: 687b ldr r3, [r7, #4] 800e38a: 693a ldr r2, [r7, #16] 800e38c: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800e38e: 687b ldr r3, [r7, #4] 800e390: 68fa ldr r2, [r7, #12] 800e392: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800e394: 683b ldr r3, [r7, #0] 800e396: 685a ldr r2, [r3, #4] 800e398: 687b ldr r3, [r7, #4] 800e39a: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800e39c: 687b ldr r3, [r7, #4] 800e39e: 697a ldr r2, [r7, #20] 800e3a0: 621a str r2, [r3, #32] } 800e3a2: bf00 nop 800e3a4: 371c adds r7, #28 800e3a6: 46bd mov sp, r7 800e3a8: f85d 7b04 ldr.w r7, [sp], #4 800e3ac: 4770 bx lr 800e3ae: bf00 nop 800e3b0: 40012c00 .word 0x40012c00 800e3b4: 40014400 .word 0x40014400 800e3b8: 40014800 .word 0x40014800 0800e3bc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800e3bc: b480 push {r7} 800e3be: b087 sub sp, #28 800e3c0: af00 add r7, sp, #0 800e3c2: 6078 str r0, [r7, #4] 800e3c4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800e3c6: 687b ldr r3, [r7, #4] 800e3c8: 6a1b ldr r3, [r3, #32] 800e3ca: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 800e3cc: 687b ldr r3, [r7, #4] 800e3ce: 6a1b ldr r3, [r3, #32] 800e3d0: f423 7280 bic.w r2, r3, #256 @ 0x100 800e3d4: 687b ldr r3, [r7, #4] 800e3d6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800e3d8: 687b ldr r3, [r7, #4] 800e3da: 685b ldr r3, [r3, #4] 800e3dc: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800e3de: 687b ldr r3, [r7, #4] 800e3e0: 69db ldr r3, [r3, #28] 800e3e2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 800e3e4: 68fb ldr r3, [r7, #12] 800e3e6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800e3ea: f023 0370 bic.w r3, r3, #112 @ 0x70 800e3ee: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 800e3f0: 68fb ldr r3, [r7, #12] 800e3f2: f023 0303 bic.w r3, r3, #3 800e3f6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800e3f8: 683b ldr r3, [r7, #0] 800e3fa: 681b ldr r3, [r3, #0] 800e3fc: 68fa ldr r2, [r7, #12] 800e3fe: 4313 orrs r3, r2 800e400: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 800e402: 697b ldr r3, [r7, #20] 800e404: f423 7300 bic.w r3, r3, #512 @ 0x200 800e408: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800e40a: 683b ldr r3, [r7, #0] 800e40c: 689b ldr r3, [r3, #8] 800e40e: 021b lsls r3, r3, #8 800e410: 697a ldr r2, [r7, #20] 800e412: 4313 orrs r3, r2 800e414: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 800e416: 687b ldr r3, [r7, #4] 800e418: 4a22 ldr r2, [pc, #136] @ (800e4a4 ) 800e41a: 4293 cmp r3, r2 800e41c: d10f bne.n 800e43e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 3N: Reset the CC3NE Bit */ TIMx->CCER &= ~TIM_CCER_CC3NE; 800e41e: 687b ldr r3, [r7, #4] 800e420: 6a1b ldr r3, [r3, #32] 800e422: f423 6280 bic.w r2, r3, #1024 @ 0x400 800e426: 687b ldr r3, [r7, #4] 800e428: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 800e42a: 697b ldr r3, [r7, #20] 800e42c: f423 6300 bic.w r3, r3, #2048 @ 0x800 800e430: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800e432: 683b ldr r3, [r7, #0] 800e434: 68db ldr r3, [r3, #12] 800e436: 021b lsls r3, r3, #8 800e438: 697a ldr r2, [r7, #20] 800e43a: 4313 orrs r3, r2 800e43c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800e43e: 687b ldr r3, [r7, #4] 800e440: 4a18 ldr r2, [pc, #96] @ (800e4a4 ) 800e442: 4293 cmp r3, r2 800e444: d007 beq.n 800e456 800e446: 687b ldr r3, [r7, #4] 800e448: 4a17 ldr r2, [pc, #92] @ (800e4a8 ) 800e44a: 4293 cmp r3, r2 800e44c: d003 beq.n 800e456 800e44e: 687b ldr r3, [r7, #4] 800e450: 4a16 ldr r2, [pc, #88] @ (800e4ac ) 800e452: 4293 cmp r3, r2 800e454: d113 bne.n 800e47e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 800e456: 693b ldr r3, [r7, #16] 800e458: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800e45c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800e45e: 693b ldr r3, [r7, #16] 800e460: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800e464: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 800e466: 683b ldr r3, [r7, #0] 800e468: 695b ldr r3, [r3, #20] 800e46a: 011b lsls r3, r3, #4 800e46c: 693a ldr r2, [r7, #16] 800e46e: 4313 orrs r3, r2 800e470: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800e472: 683b ldr r3, [r7, #0] 800e474: 699b ldr r3, [r3, #24] 800e476: 011b lsls r3, r3, #4 800e478: 693a ldr r2, [r7, #16] 800e47a: 4313 orrs r3, r2 800e47c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800e47e: 687b ldr r3, [r7, #4] 800e480: 693a ldr r2, [r7, #16] 800e482: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800e484: 687b ldr r3, [r7, #4] 800e486: 68fa ldr r2, [r7, #12] 800e488: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 800e48a: 683b ldr r3, [r7, #0] 800e48c: 685a ldr r2, [r3, #4] 800e48e: 687b ldr r3, [r7, #4] 800e490: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800e492: 687b ldr r3, [r7, #4] 800e494: 697a ldr r2, [r7, #20] 800e496: 621a str r2, [r3, #32] } 800e498: bf00 nop 800e49a: 371c adds r7, #28 800e49c: 46bd mov sp, r7 800e49e: f85d 7b04 ldr.w r7, [sp], #4 800e4a2: 4770 bx lr 800e4a4: 40012c00 .word 0x40012c00 800e4a8: 40014400 .word 0x40014400 800e4ac: 40014800 .word 0x40014800 0800e4b0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800e4b0: b480 push {r7} 800e4b2: b087 sub sp, #28 800e4b4: af00 add r7, sp, #0 800e4b6: 6078 str r0, [r7, #4] 800e4b8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800e4ba: 687b ldr r3, [r7, #4] 800e4bc: 6a1b ldr r3, [r3, #32] 800e4be: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 800e4c0: 687b ldr r3, [r7, #4] 800e4c2: 6a1b ldr r3, [r3, #32] 800e4c4: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800e4c8: 687b ldr r3, [r7, #4] 800e4ca: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800e4cc: 687b ldr r3, [r7, #4] 800e4ce: 685b ldr r3, [r3, #4] 800e4d0: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800e4d2: 687b ldr r3, [r7, #4] 800e4d4: 69db ldr r3, [r3, #28] 800e4d6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 800e4d8: 68fb ldr r3, [r7, #12] 800e4da: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800e4de: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800e4e2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 800e4e4: 68fb ldr r3, [r7, #12] 800e4e6: f423 7340 bic.w r3, r3, #768 @ 0x300 800e4ea: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800e4ec: 683b ldr r3, [r7, #0] 800e4ee: 681b ldr r3, [r3, #0] 800e4f0: 021b lsls r3, r3, #8 800e4f2: 68fa ldr r2, [r7, #12] 800e4f4: 4313 orrs r3, r2 800e4f6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 800e4f8: 693b ldr r3, [r7, #16] 800e4fa: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800e4fe: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 800e500: 683b ldr r3, [r7, #0] 800e502: 689b ldr r3, [r3, #8] 800e504: 031b lsls r3, r3, #12 800e506: 693a ldr r2, [r7, #16] 800e508: 4313 orrs r3, r2 800e50a: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800e50c: 687b ldr r3, [r7, #4] 800e50e: 4a14 ldr r2, [pc, #80] @ (800e560 ) 800e510: 4293 cmp r3, r2 800e512: d007 beq.n 800e524 800e514: 687b ldr r3, [r7, #4] 800e516: 4a13 ldr r2, [pc, #76] @ (800e564 ) 800e518: 4293 cmp r3, r2 800e51a: d003 beq.n 800e524 800e51c: 687b ldr r3, [r7, #4] 800e51e: 4a12 ldr r2, [pc, #72] @ (800e568 ) 800e520: 4293 cmp r3, r2 800e522: d109 bne.n 800e538 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 800e524: 697b ldr r3, [r7, #20] 800e526: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800e52a: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 800e52c: 683b ldr r3, [r7, #0] 800e52e: 695b ldr r3, [r3, #20] 800e530: 019b lsls r3, r3, #6 800e532: 697a ldr r2, [r7, #20] 800e534: 4313 orrs r3, r2 800e536: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800e538: 687b ldr r3, [r7, #4] 800e53a: 697a ldr r2, [r7, #20] 800e53c: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800e53e: 687b ldr r3, [r7, #4] 800e540: 68fa ldr r2, [r7, #12] 800e542: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 800e544: 683b ldr r3, [r7, #0] 800e546: 685a ldr r2, [r3, #4] 800e548: 687b ldr r3, [r7, #4] 800e54a: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800e54c: 687b ldr r3, [r7, #4] 800e54e: 693a ldr r2, [r7, #16] 800e550: 621a str r2, [r3, #32] } 800e552: bf00 nop 800e554: 371c adds r7, #28 800e556: 46bd mov sp, r7 800e558: f85d 7b04 ldr.w r7, [sp], #4 800e55c: 4770 bx lr 800e55e: bf00 nop 800e560: 40012c00 .word 0x40012c00 800e564: 40014400 .word 0x40014400 800e568: 40014800 .word 0x40014800 0800e56c : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800e56c: b480 push {r7} 800e56e: b087 sub sp, #28 800e570: af00 add r7, sp, #0 800e572: 6078 str r0, [r7, #4] 800e574: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800e576: 687b ldr r3, [r7, #4] 800e578: 6a1b ldr r3, [r3, #32] 800e57a: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 800e57c: 687b ldr r3, [r7, #4] 800e57e: 6a1b ldr r3, [r3, #32] 800e580: f423 3280 bic.w r2, r3, #65536 @ 0x10000 800e584: 687b ldr r3, [r7, #4] 800e586: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800e588: 687b ldr r3, [r7, #4] 800e58a: 685b ldr r3, [r3, #4] 800e58c: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 800e58e: 687b ldr r3, [r7, #4] 800e590: 6d5b ldr r3, [r3, #84] @ 0x54 800e592: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 800e594: 68fb ldr r3, [r7, #12] 800e596: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800e59a: f023 0370 bic.w r3, r3, #112 @ 0x70 800e59e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800e5a0: 683b ldr r3, [r7, #0] 800e5a2: 681b ldr r3, [r3, #0] 800e5a4: 68fa ldr r2, [r7, #12] 800e5a6: 4313 orrs r3, r2 800e5a8: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 800e5aa: 693b ldr r3, [r7, #16] 800e5ac: f423 3300 bic.w r3, r3, #131072 @ 0x20000 800e5b0: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 800e5b2: 683b ldr r3, [r7, #0] 800e5b4: 689b ldr r3, [r3, #8] 800e5b6: 041b lsls r3, r3, #16 800e5b8: 693a ldr r2, [r7, #16] 800e5ba: 4313 orrs r3, r2 800e5bc: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800e5be: 687b ldr r3, [r7, #4] 800e5c0: 4a13 ldr r2, [pc, #76] @ (800e610 ) 800e5c2: 4293 cmp r3, r2 800e5c4: d007 beq.n 800e5d6 800e5c6: 687b ldr r3, [r7, #4] 800e5c8: 4a12 ldr r2, [pc, #72] @ (800e614 ) 800e5ca: 4293 cmp r3, r2 800e5cc: d003 beq.n 800e5d6 800e5ce: 687b ldr r3, [r7, #4] 800e5d0: 4a11 ldr r2, [pc, #68] @ (800e618 ) 800e5d2: 4293 cmp r3, r2 800e5d4: d109 bne.n 800e5ea { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 800e5d6: 697b ldr r3, [r7, #20] 800e5d8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800e5dc: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 800e5de: 683b ldr r3, [r7, #0] 800e5e0: 695b ldr r3, [r3, #20] 800e5e2: 021b lsls r3, r3, #8 800e5e4: 697a ldr r2, [r7, #20] 800e5e6: 4313 orrs r3, r2 800e5e8: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800e5ea: 687b ldr r3, [r7, #4] 800e5ec: 697a ldr r2, [r7, #20] 800e5ee: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 800e5f0: 687b ldr r3, [r7, #4] 800e5f2: 68fa ldr r2, [r7, #12] 800e5f4: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 800e5f6: 683b ldr r3, [r7, #0] 800e5f8: 685a ldr r2, [r3, #4] 800e5fa: 687b ldr r3, [r7, #4] 800e5fc: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800e5fe: 687b ldr r3, [r7, #4] 800e600: 693a ldr r2, [r7, #16] 800e602: 621a str r2, [r3, #32] } 800e604: bf00 nop 800e606: 371c adds r7, #28 800e608: 46bd mov sp, r7 800e60a: f85d 7b04 ldr.w r7, [sp], #4 800e60e: 4770 bx lr 800e610: 40012c00 .word 0x40012c00 800e614: 40014400 .word 0x40014400 800e618: 40014800 .word 0x40014800 0800e61c : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800e61c: b480 push {r7} 800e61e: b087 sub sp, #28 800e620: af00 add r7, sp, #0 800e622: 6078 str r0, [r7, #4] 800e624: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800e626: 687b ldr r3, [r7, #4] 800e628: 6a1b ldr r3, [r3, #32] 800e62a: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 800e62c: 687b ldr r3, [r7, #4] 800e62e: 6a1b ldr r3, [r3, #32] 800e630: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800e634: 687b ldr r3, [r7, #4] 800e636: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800e638: 687b ldr r3, [r7, #4] 800e63a: 685b ldr r3, [r3, #4] 800e63c: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 800e63e: 687b ldr r3, [r7, #4] 800e640: 6d5b ldr r3, [r3, #84] @ 0x54 800e642: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 800e644: 68fb ldr r3, [r7, #12] 800e646: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800e64a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800e64e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800e650: 683b ldr r3, [r7, #0] 800e652: 681b ldr r3, [r3, #0] 800e654: 021b lsls r3, r3, #8 800e656: 68fa ldr r2, [r7, #12] 800e658: 4313 orrs r3, r2 800e65a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 800e65c: 693b ldr r3, [r7, #16] 800e65e: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800e662: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 800e664: 683b ldr r3, [r7, #0] 800e666: 689b ldr r3, [r3, #8] 800e668: 051b lsls r3, r3, #20 800e66a: 693a ldr r2, [r7, #16] 800e66c: 4313 orrs r3, r2 800e66e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800e670: 687b ldr r3, [r7, #4] 800e672: 4a14 ldr r2, [pc, #80] @ (800e6c4 ) 800e674: 4293 cmp r3, r2 800e676: d007 beq.n 800e688 800e678: 687b ldr r3, [r7, #4] 800e67a: 4a13 ldr r2, [pc, #76] @ (800e6c8 ) 800e67c: 4293 cmp r3, r2 800e67e: d003 beq.n 800e688 800e680: 687b ldr r3, [r7, #4] 800e682: 4a12 ldr r2, [pc, #72] @ (800e6cc ) 800e684: 4293 cmp r3, r2 800e686: d109 bne.n 800e69c { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 800e688: 697b ldr r3, [r7, #20] 800e68a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800e68e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 800e690: 683b ldr r3, [r7, #0] 800e692: 695b ldr r3, [r3, #20] 800e694: 029b lsls r3, r3, #10 800e696: 697a ldr r2, [r7, #20] 800e698: 4313 orrs r3, r2 800e69a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800e69c: 687b ldr r3, [r7, #4] 800e69e: 697a ldr r2, [r7, #20] 800e6a0: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 800e6a2: 687b ldr r3, [r7, #4] 800e6a4: 68fa ldr r2, [r7, #12] 800e6a6: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 800e6a8: 683b ldr r3, [r7, #0] 800e6aa: 685a ldr r2, [r3, #4] 800e6ac: 687b ldr r3, [r7, #4] 800e6ae: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800e6b0: 687b ldr r3, [r7, #4] 800e6b2: 693a ldr r2, [r7, #16] 800e6b4: 621a str r2, [r3, #32] } 800e6b6: bf00 nop 800e6b8: 371c adds r7, #28 800e6ba: 46bd mov sp, r7 800e6bc: f85d 7b04 ldr.w r7, [sp], #4 800e6c0: 4770 bx lr 800e6c2: bf00 nop 800e6c4: 40012c00 .word 0x40012c00 800e6c8: 40014400 .word 0x40014400 800e6cc: 40014800 .word 0x40014800 0800e6d0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 800e6d0: b480 push {r7} 800e6d2: b085 sub sp, #20 800e6d4: af00 add r7, sp, #0 800e6d6: 6078 str r0, [r7, #4] 800e6d8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800e6da: 687b ldr r3, [r7, #4] 800e6dc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800e6e0: 2b01 cmp r3, #1 800e6e2: d101 bne.n 800e6e8 800e6e4: 2302 movs r3, #2 800e6e6: e04a b.n 800e77e 800e6e8: 687b ldr r3, [r7, #4] 800e6ea: 2201 movs r2, #1 800e6ec: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 800e6f0: 687b ldr r3, [r7, #4] 800e6f2: 2202 movs r2, #2 800e6f4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800e6f8: 687b ldr r3, [r7, #4] 800e6fa: 681b ldr r3, [r3, #0] 800e6fc: 685b ldr r3, [r3, #4] 800e6fe: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 800e700: 687b ldr r3, [r7, #4] 800e702: 681b ldr r3, [r3, #0] 800e704: 689b ldr r3, [r3, #8] 800e706: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800e708: 687b ldr r3, [r7, #4] 800e70a: 681b ldr r3, [r3, #0] 800e70c: 4a1f ldr r2, [pc, #124] @ (800e78c ) 800e70e: 4293 cmp r3, r2 800e710: d108 bne.n 800e724 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 800e712: 68fb ldr r3, [r7, #12] 800e714: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 800e718: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 800e71a: 683b ldr r3, [r7, #0] 800e71c: 685b ldr r3, [r3, #4] 800e71e: 68fa ldr r2, [r7, #12] 800e720: 4313 orrs r3, r2 800e722: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800e724: 68fb ldr r3, [r7, #12] 800e726: f023 0370 bic.w r3, r3, #112 @ 0x70 800e72a: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800e72c: 683b ldr r3, [r7, #0] 800e72e: 681b ldr r3, [r3, #0] 800e730: 68fa ldr r2, [r7, #12] 800e732: 4313 orrs r3, r2 800e734: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800e736: 687b ldr r3, [r7, #4] 800e738: 681b ldr r3, [r3, #0] 800e73a: 68fa ldr r2, [r7, #12] 800e73c: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800e73e: 687b ldr r3, [r7, #4] 800e740: 681b ldr r3, [r3, #0] 800e742: 4a12 ldr r2, [pc, #72] @ (800e78c ) 800e744: 4293 cmp r3, r2 800e746: d004 beq.n 800e752 800e748: 687b ldr r3, [r7, #4] 800e74a: 681b ldr r3, [r3, #0] 800e74c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e750: d10c bne.n 800e76c { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 800e752: 68bb ldr r3, [r7, #8] 800e754: f023 0380 bic.w r3, r3, #128 @ 0x80 800e758: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800e75a: 683b ldr r3, [r7, #0] 800e75c: 689b ldr r3, [r3, #8] 800e75e: 68ba ldr r2, [r7, #8] 800e760: 4313 orrs r3, r2 800e762: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800e764: 687b ldr r3, [r7, #4] 800e766: 681b ldr r3, [r3, #0] 800e768: 68ba ldr r2, [r7, #8] 800e76a: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 800e76c: 687b ldr r3, [r7, #4] 800e76e: 2201 movs r2, #1 800e770: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800e774: 687b ldr r3, [r7, #4] 800e776: 2200 movs r2, #0 800e778: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 800e77c: 2300 movs r3, #0 } 800e77e: 4618 mov r0, r3 800e780: 3714 adds r7, #20 800e782: 46bd mov sp, r7 800e784: f85d 7b04 ldr.w r7, [sp], #4 800e788: 4770 bx lr 800e78a: bf00 nop 800e78c: 40012c00 .word 0x40012c00 0800e790 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 800e790: b480 push {r7} 800e792: b083 sub sp, #12 800e794: af00 add r7, sp, #0 800e796: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 800e798: bf00 nop 800e79a: 370c adds r7, #12 800e79c: 46bd mov sp, r7 800e79e: f85d 7b04 ldr.w r7, [sp], #4 800e7a2: 4770 bx lr 0800e7a4 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 800e7a4: b480 push {r7} 800e7a6: b083 sub sp, #12 800e7a8: af00 add r7, sp, #0 800e7aa: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 800e7ac: bf00 nop 800e7ae: 370c adds r7, #12 800e7b0: 46bd mov sp, r7 800e7b2: f85d 7b04 ldr.w r7, [sp], #4 800e7b6: 4770 bx lr 0800e7b8 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 800e7b8: b480 push {r7} 800e7ba: b083 sub sp, #12 800e7bc: af00 add r7, sp, #0 800e7be: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 800e7c0: bf00 nop 800e7c2: 370c adds r7, #12 800e7c4: 46bd mov sp, r7 800e7c6: f85d 7b04 ldr.w r7, [sp], #4 800e7ca: 4770 bx lr 0800e7cc : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { 800e7cc: b480 push {r7} 800e7ce: b085 sub sp, #20 800e7d0: af00 add r7, sp, #0 800e7d2: 6078 str r0, [r7, #4] uint32_t winterruptmask; /* Clear pending interrupts */ USBx->ISTR = 0U; 800e7d4: 687b ldr r3, [r7, #4] 800e7d6: 2200 movs r2, #0 800e7d8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | 800e7dc: f64b 7380 movw r3, #49024 @ 0xbf80 800e7e0: 60fb str r3, [r7, #12] USB_CNTR_SUSPM | USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Set interrupt mask */ USBx->CNTR = (uint16_t)winterruptmask; 800e7e2: 68fb ldr r3, [r7, #12] 800e7e4: b29a uxth r2, r3 800e7e6: 687b ldr r3, [r7, #4] 800e7e8: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 return HAL_OK; 800e7ec: 2300 movs r3, #0 } 800e7ee: 4618 mov r0, r3 800e7f0: 3714 adds r7, #20 800e7f2: 46bd mov sp, r7 800e7f4: f85d 7b04 ldr.w r7, [sp], #4 800e7f8: 4770 bx lr 0800e7fa : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { 800e7fa: b480 push {r7} 800e7fc: b085 sub sp, #20 800e7fe: af00 add r7, sp, #0 800e800: 6078 str r0, [r7, #4] uint32_t winterruptmask; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | 800e802: f64b 7380 movw r3, #49024 @ 0xbf80 800e806: 60fb str r3, [r7, #12] USB_CNTR_SUSPM | USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Clear interrupt mask */ USBx->CNTR &= (uint16_t)(~winterruptmask); 800e808: 687b ldr r3, [r7, #4] 800e80a: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 800e80e: b29a uxth r2, r3 800e810: 68fb ldr r3, [r7, #12] 800e812: b29b uxth r3, r3 800e814: 43db mvns r3, r3 800e816: b29b uxth r3, r3 800e818: 4013 ands r3, r2 800e81a: b29a uxth r2, r3 800e81c: 687b ldr r3, [r7, #4] 800e81e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 return HAL_OK; 800e822: 2300 movs r3, #0 } 800e824: 4618 mov r0, r3 800e826: 3714 adds r7, #20 800e828: 46bd mov sp, r7 800e82a: f85d 7b04 ldr.w r7, [sp], #4 800e82e: 4770 bx lr 0800e830 : * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { 800e830: b480 push {r7} 800e832: b085 sub sp, #20 800e834: af00 add r7, sp, #0 800e836: 60f8 str r0, [r7, #12] 800e838: 1d3b adds r3, r7, #4 800e83a: e883 0006 stmia.w r3, {r1, r2} /* Prevent unused argument(s) compilation warning */ UNUSED(cfg); /* Init Device */ /* CNTR_FRES = 1 */ USBx->CNTR = (uint16_t)USB_CNTR_FRES; 800e83e: 68fb ldr r3, [r7, #12] 800e840: 2201 movs r2, #1 800e842: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* CNTR_FRES = 0 */ USBx->CNTR = 0U; 800e846: 68fb ldr r3, [r7, #12] 800e848: 2200 movs r2, #0 800e84a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* Clear pending interrupts */ USBx->ISTR = 0U; 800e84e: 68fb ldr r3, [r7, #12] 800e850: 2200 movs r2, #0 800e852: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; 800e856: 68fb ldr r3, [r7, #12] 800e858: 2200 movs r2, #0 800e85a: f8a3 2050 strh.w r2, [r3, #80] @ 0x50 return HAL_OK; 800e85e: 2300 movs r3, #0 } 800e860: 4618 mov r0, r3 800e862: 3714 adds r7, #20 800e864: 46bd mov sp, r7 800e866: f85d 7b04 ldr.w r7, [sp], #4 800e86a: 4770 bx lr 0800e86c : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800e86c: b480 push {r7} 800e86e: b0a7 sub sp, #156 @ 0x9c 800e870: af00 add r7, sp, #0 800e872: 6078 str r0, [r7, #4] 800e874: 6039 str r1, [r7, #0] HAL_StatusTypeDef ret = HAL_OK; 800e876: 2300 movs r3, #0 800e878: f887 3097 strb.w r3, [r7, #151] @ 0x97 uint16_t wEpRegVal; wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; 800e87c: 687a ldr r2, [r7, #4] 800e87e: 683b ldr r3, [r7, #0] 800e880: 781b ldrb r3, [r3, #0] 800e882: 009b lsls r3, r3, #2 800e884: 4413 add r3, r2 800e886: 881b ldrh r3, [r3, #0] 800e888: b29b uxth r3, r3 800e88a: f423 43ec bic.w r3, r3, #30208 @ 0x7600 800e88e: f023 0370 bic.w r3, r3, #112 @ 0x70 800e892: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 /* initialize Endpoint */ switch (ep->type) 800e896: 683b ldr r3, [r7, #0] 800e898: 78db ldrb r3, [r3, #3] 800e89a: 2b03 cmp r3, #3 800e89c: d81f bhi.n 800e8de 800e89e: a201 add r2, pc, #4 @ (adr r2, 800e8a4 ) 800e8a0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800e8a4: 0800e8b5 .word 0x0800e8b5 800e8a8: 0800e8d1 .word 0x0800e8d1 800e8ac: 0800e8e7 .word 0x0800e8e7 800e8b0: 0800e8c3 .word 0x0800e8c3 { case EP_TYPE_CTRL: wEpRegVal |= USB_EP_CONTROL; 800e8b4: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800e8b8: f443 7300 orr.w r3, r3, #512 @ 0x200 800e8bc: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 break; 800e8c0: e012 b.n 800e8e8 case EP_TYPE_BULK: wEpRegVal |= USB_EP_BULK; break; case EP_TYPE_INTR: wEpRegVal |= USB_EP_INTERRUPT; 800e8c2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800e8c6: f443 63c0 orr.w r3, r3, #1536 @ 0x600 800e8ca: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 break; 800e8ce: e00b b.n 800e8e8 case EP_TYPE_ISOC: wEpRegVal |= USB_EP_ISOCHRONOUS; 800e8d0: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800e8d4: f443 6380 orr.w r3, r3, #1024 @ 0x400 800e8d8: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 break; 800e8dc: e004 b.n 800e8e8 default: ret = HAL_ERROR; 800e8de: 2301 movs r3, #1 800e8e0: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800e8e4: e000 b.n 800e8e8 break; 800e8e6: bf00 nop } PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); 800e8e8: 687a ldr r2, [r7, #4] 800e8ea: 683b ldr r3, [r7, #0] 800e8ec: 781b ldrb r3, [r3, #0] 800e8ee: 009b lsls r3, r3, #2 800e8f0: 441a add r2, r3 800e8f2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800e8f6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800e8fa: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800e8fe: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800e902: f043 0380 orr.w r3, r3, #128 @ 0x80 800e906: b29b uxth r3, r3 800e908: 8013 strh r3, [r2, #0] PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); 800e90a: 687a ldr r2, [r7, #4] 800e90c: 683b ldr r3, [r7, #0] 800e90e: 781b ldrb r3, [r3, #0] 800e910: 009b lsls r3, r3, #2 800e912: 4413 add r3, r2 800e914: 881b ldrh r3, [r3, #0] 800e916: b29b uxth r3, r3 800e918: b21b sxth r3, r3 800e91a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800e91e: f023 0370 bic.w r3, r3, #112 @ 0x70 800e922: b21a sxth r2, r3 800e924: 683b ldr r3, [r7, #0] 800e926: 781b ldrb r3, [r3, #0] 800e928: b21b sxth r3, r3 800e92a: 4313 orrs r3, r2 800e92c: b21b sxth r3, r3 800e92e: f8a7 3086 strh.w r3, [r7, #134] @ 0x86 800e932: 687a ldr r2, [r7, #4] 800e934: 683b ldr r3, [r7, #0] 800e936: 781b ldrb r3, [r3, #0] 800e938: 009b lsls r3, r3, #2 800e93a: 441a add r2, r3 800e93c: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 800e940: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800e944: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800e948: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800e94c: f043 0380 orr.w r3, r3, #128 @ 0x80 800e950: b29b uxth r3, r3 800e952: 8013 strh r3, [r2, #0] if (ep->doublebuffer == 0U) 800e954: 683b ldr r3, [r7, #0] 800e956: 7b1b ldrb r3, [r3, #12] 800e958: 2b00 cmp r3, #0 800e95a: f040 8180 bne.w 800ec5e { if (ep->is_in != 0U) 800e95e: 683b ldr r3, [r7, #0] 800e960: 785b ldrb r3, [r3, #1] 800e962: 2b00 cmp r3, #0 800e964: f000 8084 beq.w 800ea70 { /*Set the endpoint Transmit buffer address */ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); 800e968: 687b ldr r3, [r7, #4] 800e96a: 61bb str r3, [r7, #24] 800e96c: 687b ldr r3, [r7, #4] 800e96e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800e972: b29b uxth r3, r3 800e974: 461a mov r2, r3 800e976: 69bb ldr r3, [r7, #24] 800e978: 4413 add r3, r2 800e97a: 61bb str r3, [r7, #24] 800e97c: 683b ldr r3, [r7, #0] 800e97e: 781b ldrb r3, [r3, #0] 800e980: 00da lsls r2, r3, #3 800e982: 69bb ldr r3, [r7, #24] 800e984: 4413 add r3, r2 800e986: f503 6380 add.w r3, r3, #1024 @ 0x400 800e98a: 617b str r3, [r7, #20] 800e98c: 683b ldr r3, [r7, #0] 800e98e: 88db ldrh r3, [r3, #6] 800e990: 085b lsrs r3, r3, #1 800e992: b29b uxth r3, r3 800e994: 005b lsls r3, r3, #1 800e996: b29a uxth r2, r3 800e998: 697b ldr r3, [r7, #20] 800e99a: 801a strh r2, [r3, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800e99c: 687a ldr r2, [r7, #4] 800e99e: 683b ldr r3, [r7, #0] 800e9a0: 781b ldrb r3, [r3, #0] 800e9a2: 009b lsls r3, r3, #2 800e9a4: 4413 add r3, r2 800e9a6: 881b ldrh r3, [r3, #0] 800e9a8: 827b strh r3, [r7, #18] 800e9aa: 8a7b ldrh r3, [r7, #18] 800e9ac: f003 0340 and.w r3, r3, #64 @ 0x40 800e9b0: 2b00 cmp r3, #0 800e9b2: d01b beq.n 800e9ec 800e9b4: 687a ldr r2, [r7, #4] 800e9b6: 683b ldr r3, [r7, #0] 800e9b8: 781b ldrb r3, [r3, #0] 800e9ba: 009b lsls r3, r3, #2 800e9bc: 4413 add r3, r2 800e9be: 881b ldrh r3, [r3, #0] 800e9c0: b29b uxth r3, r3 800e9c2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800e9c6: f023 0370 bic.w r3, r3, #112 @ 0x70 800e9ca: 823b strh r3, [r7, #16] 800e9cc: 687a ldr r2, [r7, #4] 800e9ce: 683b ldr r3, [r7, #0] 800e9d0: 781b ldrb r3, [r3, #0] 800e9d2: 009b lsls r3, r3, #2 800e9d4: 441a add r2, r3 800e9d6: 8a3b ldrh r3, [r7, #16] 800e9d8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800e9dc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800e9e0: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800e9e4: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800e9e8: b29b uxth r3, r3 800e9ea: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800e9ec: 683b ldr r3, [r7, #0] 800e9ee: 78db ldrb r3, [r3, #3] 800e9f0: 2b01 cmp r3, #1 800e9f2: d020 beq.n 800ea36 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 800e9f4: 687a ldr r2, [r7, #4] 800e9f6: 683b ldr r3, [r7, #0] 800e9f8: 781b ldrb r3, [r3, #0] 800e9fa: 009b lsls r3, r3, #2 800e9fc: 4413 add r3, r2 800e9fe: 881b ldrh r3, [r3, #0] 800ea00: b29b uxth r3, r3 800ea02: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ea06: f023 0340 bic.w r3, r3, #64 @ 0x40 800ea0a: 81bb strh r3, [r7, #12] 800ea0c: 89bb ldrh r3, [r7, #12] 800ea0e: f083 0320 eor.w r3, r3, #32 800ea12: 81bb strh r3, [r7, #12] 800ea14: 687a ldr r2, [r7, #4] 800ea16: 683b ldr r3, [r7, #0] 800ea18: 781b ldrb r3, [r3, #0] 800ea1a: 009b lsls r3, r3, #2 800ea1c: 441a add r2, r3 800ea1e: 89bb ldrh r3, [r7, #12] 800ea20: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ea24: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ea28: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ea2c: f043 0380 orr.w r3, r3, #128 @ 0x80 800ea30: b29b uxth r3, r3 800ea32: 8013 strh r3, [r2, #0] 800ea34: e3f9 b.n 800f22a } else { /* Configure TX Endpoint to disabled state */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800ea36: 687a ldr r2, [r7, #4] 800ea38: 683b ldr r3, [r7, #0] 800ea3a: 781b ldrb r3, [r3, #0] 800ea3c: 009b lsls r3, r3, #2 800ea3e: 4413 add r3, r2 800ea40: 881b ldrh r3, [r3, #0] 800ea42: b29b uxth r3, r3 800ea44: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ea48: f023 0340 bic.w r3, r3, #64 @ 0x40 800ea4c: 81fb strh r3, [r7, #14] 800ea4e: 687a ldr r2, [r7, #4] 800ea50: 683b ldr r3, [r7, #0] 800ea52: 781b ldrb r3, [r3, #0] 800ea54: 009b lsls r3, r3, #2 800ea56: 441a add r2, r3 800ea58: 89fb ldrh r3, [r7, #14] 800ea5a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ea5e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ea62: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ea66: f043 0380 orr.w r3, r3, #128 @ 0x80 800ea6a: b29b uxth r3, r3 800ea6c: 8013 strh r3, [r2, #0] 800ea6e: e3dc b.n 800f22a } } else { /* Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); 800ea70: 687b ldr r3, [r7, #4] 800ea72: 633b str r3, [r7, #48] @ 0x30 800ea74: 687b ldr r3, [r7, #4] 800ea76: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ea7a: b29b uxth r3, r3 800ea7c: 461a mov r2, r3 800ea7e: 6b3b ldr r3, [r7, #48] @ 0x30 800ea80: 4413 add r3, r2 800ea82: 633b str r3, [r7, #48] @ 0x30 800ea84: 683b ldr r3, [r7, #0] 800ea86: 781b ldrb r3, [r3, #0] 800ea88: 00da lsls r2, r3, #3 800ea8a: 6b3b ldr r3, [r7, #48] @ 0x30 800ea8c: 4413 add r3, r2 800ea8e: f203 4304 addw r3, r3, #1028 @ 0x404 800ea92: 62fb str r3, [r7, #44] @ 0x2c 800ea94: 683b ldr r3, [r7, #0] 800ea96: 88db ldrh r3, [r3, #6] 800ea98: 085b lsrs r3, r3, #1 800ea9a: b29b uxth r3, r3 800ea9c: 005b lsls r3, r3, #1 800ea9e: b29a uxth r2, r3 800eaa0: 6afb ldr r3, [r7, #44] @ 0x2c 800eaa2: 801a strh r2, [r3, #0] /* Set the endpoint Receive buffer counter */ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); 800eaa4: 687b ldr r3, [r7, #4] 800eaa6: 62bb str r3, [r7, #40] @ 0x28 800eaa8: 687b ldr r3, [r7, #4] 800eaaa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800eaae: b29b uxth r3, r3 800eab0: 461a mov r2, r3 800eab2: 6abb ldr r3, [r7, #40] @ 0x28 800eab4: 4413 add r3, r2 800eab6: 62bb str r3, [r7, #40] @ 0x28 800eab8: 683b ldr r3, [r7, #0] 800eaba: 781b ldrb r3, [r3, #0] 800eabc: 00da lsls r2, r3, #3 800eabe: 6abb ldr r3, [r7, #40] @ 0x28 800eac0: 4413 add r3, r2 800eac2: f203 4306 addw r3, r3, #1030 @ 0x406 800eac6: 627b str r3, [r7, #36] @ 0x24 800eac8: 6a7b ldr r3, [r7, #36] @ 0x24 800eaca: 881b ldrh r3, [r3, #0] 800eacc: b29b uxth r3, r3 800eace: f3c3 0309 ubfx r3, r3, #0, #10 800ead2: b29a uxth r2, r3 800ead4: 6a7b ldr r3, [r7, #36] @ 0x24 800ead6: 801a strh r2, [r3, #0] 800ead8: 683b ldr r3, [r7, #0] 800eada: 691b ldr r3, [r3, #16] 800eadc: 2b00 cmp r3, #0 800eade: d10a bne.n 800eaf6 800eae0: 6a7b ldr r3, [r7, #36] @ 0x24 800eae2: 881b ldrh r3, [r3, #0] 800eae4: b29b uxth r3, r3 800eae6: ea6f 4343 mvn.w r3, r3, lsl #17 800eaea: ea6f 4353 mvn.w r3, r3, lsr #17 800eaee: b29a uxth r2, r3 800eaf0: 6a7b ldr r3, [r7, #36] @ 0x24 800eaf2: 801a strh r2, [r3, #0] 800eaf4: e041 b.n 800eb7a 800eaf6: 683b ldr r3, [r7, #0] 800eaf8: 691b ldr r3, [r3, #16] 800eafa: 2b3e cmp r3, #62 @ 0x3e 800eafc: d81c bhi.n 800eb38 800eafe: 683b ldr r3, [r7, #0] 800eb00: 691b ldr r3, [r3, #16] 800eb02: 085b lsrs r3, r3, #1 800eb04: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800eb08: 683b ldr r3, [r7, #0] 800eb0a: 691b ldr r3, [r3, #16] 800eb0c: f003 0301 and.w r3, r3, #1 800eb10: 2b00 cmp r3, #0 800eb12: d004 beq.n 800eb1e 800eb14: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800eb18: 3301 adds r3, #1 800eb1a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800eb1e: 6a7b ldr r3, [r7, #36] @ 0x24 800eb20: 881b ldrh r3, [r3, #0] 800eb22: b29a uxth r2, r3 800eb24: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800eb28: b29b uxth r3, r3 800eb2a: 029b lsls r3, r3, #10 800eb2c: b29b uxth r3, r3 800eb2e: 4313 orrs r3, r2 800eb30: b29a uxth r2, r3 800eb32: 6a7b ldr r3, [r7, #36] @ 0x24 800eb34: 801a strh r2, [r3, #0] 800eb36: e020 b.n 800eb7a 800eb38: 683b ldr r3, [r7, #0] 800eb3a: 691b ldr r3, [r3, #16] 800eb3c: 095b lsrs r3, r3, #5 800eb3e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800eb42: 683b ldr r3, [r7, #0] 800eb44: 691b ldr r3, [r3, #16] 800eb46: f003 031f and.w r3, r3, #31 800eb4a: 2b00 cmp r3, #0 800eb4c: d104 bne.n 800eb58 800eb4e: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800eb52: 3b01 subs r3, #1 800eb54: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800eb58: 6a7b ldr r3, [r7, #36] @ 0x24 800eb5a: 881b ldrh r3, [r3, #0] 800eb5c: b29a uxth r2, r3 800eb5e: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800eb62: b29b uxth r3, r3 800eb64: 029b lsls r3, r3, #10 800eb66: b29b uxth r3, r3 800eb68: 4313 orrs r3, r2 800eb6a: b29b uxth r3, r3 800eb6c: ea6f 4343 mvn.w r3, r3, lsl #17 800eb70: ea6f 4353 mvn.w r3, r3, lsr #17 800eb74: b29a uxth r2, r3 800eb76: 6a7b ldr r3, [r7, #36] @ 0x24 800eb78: 801a strh r2, [r3, #0] PCD_CLEAR_RX_DTOG(USBx, ep->num); 800eb7a: 687a ldr r2, [r7, #4] 800eb7c: 683b ldr r3, [r7, #0] 800eb7e: 781b ldrb r3, [r3, #0] 800eb80: 009b lsls r3, r3, #2 800eb82: 4413 add r3, r2 800eb84: 881b ldrh r3, [r3, #0] 800eb86: 847b strh r3, [r7, #34] @ 0x22 800eb88: 8c7b ldrh r3, [r7, #34] @ 0x22 800eb8a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800eb8e: 2b00 cmp r3, #0 800eb90: d01b beq.n 800ebca 800eb92: 687a ldr r2, [r7, #4] 800eb94: 683b ldr r3, [r7, #0] 800eb96: 781b ldrb r3, [r3, #0] 800eb98: 009b lsls r3, r3, #2 800eb9a: 4413 add r3, r2 800eb9c: 881b ldrh r3, [r3, #0] 800eb9e: b29b uxth r3, r3 800eba0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800eba4: f023 0370 bic.w r3, r3, #112 @ 0x70 800eba8: 843b strh r3, [r7, #32] 800ebaa: 687a ldr r2, [r7, #4] 800ebac: 683b ldr r3, [r7, #0] 800ebae: 781b ldrb r3, [r3, #0] 800ebb0: 009b lsls r3, r3, #2 800ebb2: 441a add r2, r3 800ebb4: 8c3b ldrh r3, [r7, #32] 800ebb6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ebba: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ebbe: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800ebc2: f043 0380 orr.w r3, r3, #128 @ 0x80 800ebc6: b29b uxth r3, r3 800ebc8: 8013 strh r3, [r2, #0] if (ep->num == 0U) 800ebca: 683b ldr r3, [r7, #0] 800ebcc: 781b ldrb r3, [r3, #0] 800ebce: 2b00 cmp r3, #0 800ebd0: d124 bne.n 800ec1c { /* Configure VALID status for EP0 */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 800ebd2: 687a ldr r2, [r7, #4] 800ebd4: 683b ldr r3, [r7, #0] 800ebd6: 781b ldrb r3, [r3, #0] 800ebd8: 009b lsls r3, r3, #2 800ebda: 4413 add r3, r2 800ebdc: 881b ldrh r3, [r3, #0] 800ebde: b29b uxth r3, r3 800ebe0: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800ebe4: f023 0370 bic.w r3, r3, #112 @ 0x70 800ebe8: 83bb strh r3, [r7, #28] 800ebea: 8bbb ldrh r3, [r7, #28] 800ebec: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800ebf0: 83bb strh r3, [r7, #28] 800ebf2: 8bbb ldrh r3, [r7, #28] 800ebf4: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800ebf8: 83bb strh r3, [r7, #28] 800ebfa: 687a ldr r2, [r7, #4] 800ebfc: 683b ldr r3, [r7, #0] 800ebfe: 781b ldrb r3, [r3, #0] 800ec00: 009b lsls r3, r3, #2 800ec02: 441a add r2, r3 800ec04: 8bbb ldrh r3, [r7, #28] 800ec06: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ec0a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ec0e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ec12: f043 0380 orr.w r3, r3, #128 @ 0x80 800ec16: b29b uxth r3, r3 800ec18: 8013 strh r3, [r2, #0] 800ec1a: e306 b.n 800f22a } else { /* Configure NAK status for OUT Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); 800ec1c: 687a ldr r2, [r7, #4] 800ec1e: 683b ldr r3, [r7, #0] 800ec20: 781b ldrb r3, [r3, #0] 800ec22: 009b lsls r3, r3, #2 800ec24: 4413 add r3, r2 800ec26: 881b ldrh r3, [r3, #0] 800ec28: b29b uxth r3, r3 800ec2a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800ec2e: f023 0370 bic.w r3, r3, #112 @ 0x70 800ec32: 83fb strh r3, [r7, #30] 800ec34: 8bfb ldrh r3, [r7, #30] 800ec36: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800ec3a: 83fb strh r3, [r7, #30] 800ec3c: 687a ldr r2, [r7, #4] 800ec3e: 683b ldr r3, [r7, #0] 800ec40: 781b ldrb r3, [r3, #0] 800ec42: 009b lsls r3, r3, #2 800ec44: 441a add r2, r3 800ec46: 8bfb ldrh r3, [r7, #30] 800ec48: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ec4c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ec50: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ec54: f043 0380 orr.w r3, r3, #128 @ 0x80 800ec58: b29b uxth r3, r3 800ec5a: 8013 strh r3, [r2, #0] 800ec5c: e2e5 b.n 800f22a } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer */ else { if (ep->type == EP_TYPE_BULK) 800ec5e: 683b ldr r3, [r7, #0] 800ec60: 78db ldrb r3, [r3, #3] 800ec62: 2b02 cmp r3, #2 800ec64: d11e bne.n 800eca4 { /* Set bulk endpoint as double buffered */ PCD_SET_BULK_EP_DBUF(USBx, ep->num); 800ec66: 687a ldr r2, [r7, #4] 800ec68: 683b ldr r3, [r7, #0] 800ec6a: 781b ldrb r3, [r3, #0] 800ec6c: 009b lsls r3, r3, #2 800ec6e: 4413 add r3, r2 800ec70: 881b ldrh r3, [r3, #0] 800ec72: b29b uxth r3, r3 800ec74: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ec78: f023 0370 bic.w r3, r3, #112 @ 0x70 800ec7c: f8a7 3082 strh.w r3, [r7, #130] @ 0x82 800ec80: 687a ldr r2, [r7, #4] 800ec82: 683b ldr r3, [r7, #0] 800ec84: 781b ldrb r3, [r3, #0] 800ec86: 009b lsls r3, r3, #2 800ec88: 441a add r2, r3 800ec8a: f8b7 3082 ldrh.w r3, [r7, #130] @ 0x82 800ec8e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ec92: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ec96: f443 4301 orr.w r3, r3, #33024 @ 0x8100 800ec9a: f043 0380 orr.w r3, r3, #128 @ 0x80 800ec9e: b29b uxth r3, r3 800eca0: 8013 strh r3, [r2, #0] 800eca2: e01d b.n 800ece0 } else { /* Set the ISOC endpoint in double buffer mode */ PCD_CLEAR_EP_KIND(USBx, ep->num); 800eca4: 687a ldr r2, [r7, #4] 800eca6: 683b ldr r3, [r7, #0] 800eca8: 781b ldrb r3, [r3, #0] 800ecaa: 009b lsls r3, r3, #2 800ecac: 4413 add r3, r2 800ecae: 881b ldrh r3, [r3, #0] 800ecb0: b29b uxth r3, r3 800ecb2: f423 43e2 bic.w r3, r3, #28928 @ 0x7100 800ecb6: f023 0370 bic.w r3, r3, #112 @ 0x70 800ecba: f8a7 3084 strh.w r3, [r7, #132] @ 0x84 800ecbe: 687a ldr r2, [r7, #4] 800ecc0: 683b ldr r3, [r7, #0] 800ecc2: 781b ldrb r3, [r3, #0] 800ecc4: 009b lsls r3, r3, #2 800ecc6: 441a add r2, r3 800ecc8: f8b7 3084 ldrh.w r3, [r7, #132] @ 0x84 800eccc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ecd0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ecd4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ecd8: f043 0380 orr.w r3, r3, #128 @ 0x80 800ecdc: b29b uxth r3, r3 800ecde: 8013 strh r3, [r2, #0] } /* Set buffer address for double buffered mode */ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); 800ece0: 687b ldr r3, [r7, #4] 800ece2: 67fb str r3, [r7, #124] @ 0x7c 800ece4: 687b ldr r3, [r7, #4] 800ece6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ecea: b29b uxth r3, r3 800ecec: 461a mov r2, r3 800ecee: 6ffb ldr r3, [r7, #124] @ 0x7c 800ecf0: 4413 add r3, r2 800ecf2: 67fb str r3, [r7, #124] @ 0x7c 800ecf4: 683b ldr r3, [r7, #0] 800ecf6: 781b ldrb r3, [r3, #0] 800ecf8: 00da lsls r2, r3, #3 800ecfa: 6ffb ldr r3, [r7, #124] @ 0x7c 800ecfc: 4413 add r3, r2 800ecfe: f503 6380 add.w r3, r3, #1024 @ 0x400 800ed02: 67bb str r3, [r7, #120] @ 0x78 800ed04: 683b ldr r3, [r7, #0] 800ed06: 891b ldrh r3, [r3, #8] 800ed08: 085b lsrs r3, r3, #1 800ed0a: b29b uxth r3, r3 800ed0c: 005b lsls r3, r3, #1 800ed0e: b29a uxth r2, r3 800ed10: 6fbb ldr r3, [r7, #120] @ 0x78 800ed12: 801a strh r2, [r3, #0] 800ed14: 687b ldr r3, [r7, #4] 800ed16: 677b str r3, [r7, #116] @ 0x74 800ed18: 687b ldr r3, [r7, #4] 800ed1a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ed1e: b29b uxth r3, r3 800ed20: 461a mov r2, r3 800ed22: 6f7b ldr r3, [r7, #116] @ 0x74 800ed24: 4413 add r3, r2 800ed26: 677b str r3, [r7, #116] @ 0x74 800ed28: 683b ldr r3, [r7, #0] 800ed2a: 781b ldrb r3, [r3, #0] 800ed2c: 00da lsls r2, r3, #3 800ed2e: 6f7b ldr r3, [r7, #116] @ 0x74 800ed30: 4413 add r3, r2 800ed32: f203 4304 addw r3, r3, #1028 @ 0x404 800ed36: 673b str r3, [r7, #112] @ 0x70 800ed38: 683b ldr r3, [r7, #0] 800ed3a: 895b ldrh r3, [r3, #10] 800ed3c: 085b lsrs r3, r3, #1 800ed3e: b29b uxth r3, r3 800ed40: 005b lsls r3, r3, #1 800ed42: b29a uxth r2, r3 800ed44: 6f3b ldr r3, [r7, #112] @ 0x70 800ed46: 801a strh r2, [r3, #0] if (ep->is_in == 0U) 800ed48: 683b ldr r3, [r7, #0] 800ed4a: 785b ldrb r3, [r3, #1] 800ed4c: 2b00 cmp r3, #0 800ed4e: f040 81af bne.w 800f0b0 { /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800ed52: 687a ldr r2, [r7, #4] 800ed54: 683b ldr r3, [r7, #0] 800ed56: 781b ldrb r3, [r3, #0] 800ed58: 009b lsls r3, r3, #2 800ed5a: 4413 add r3, r2 800ed5c: 881b ldrh r3, [r3, #0] 800ed5e: f8a7 3060 strh.w r3, [r7, #96] @ 0x60 800ed62: f8b7 3060 ldrh.w r3, [r7, #96] @ 0x60 800ed66: f403 4380 and.w r3, r3, #16384 @ 0x4000 800ed6a: 2b00 cmp r3, #0 800ed6c: d01d beq.n 800edaa 800ed6e: 687a ldr r2, [r7, #4] 800ed70: 683b ldr r3, [r7, #0] 800ed72: 781b ldrb r3, [r3, #0] 800ed74: 009b lsls r3, r3, #2 800ed76: 4413 add r3, r2 800ed78: 881b ldrh r3, [r3, #0] 800ed7a: b29b uxth r3, r3 800ed7c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ed80: f023 0370 bic.w r3, r3, #112 @ 0x70 800ed84: f8a7 305e strh.w r3, [r7, #94] @ 0x5e 800ed88: 687a ldr r2, [r7, #4] 800ed8a: 683b ldr r3, [r7, #0] 800ed8c: 781b ldrb r3, [r3, #0] 800ed8e: 009b lsls r3, r3, #2 800ed90: 441a add r2, r3 800ed92: f8b7 305e ldrh.w r3, [r7, #94] @ 0x5e 800ed96: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ed9a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ed9e: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800eda2: f043 0380 orr.w r3, r3, #128 @ 0x80 800eda6: b29b uxth r3, r3 800eda8: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800edaa: 687a ldr r2, [r7, #4] 800edac: 683b ldr r3, [r7, #0] 800edae: 781b ldrb r3, [r3, #0] 800edb0: 009b lsls r3, r3, #2 800edb2: 4413 add r3, r2 800edb4: 881b ldrh r3, [r3, #0] 800edb6: f8a7 305c strh.w r3, [r7, #92] @ 0x5c 800edba: f8b7 305c ldrh.w r3, [r7, #92] @ 0x5c 800edbe: f003 0340 and.w r3, r3, #64 @ 0x40 800edc2: 2b00 cmp r3, #0 800edc4: d01d beq.n 800ee02 800edc6: 687a ldr r2, [r7, #4] 800edc8: 683b ldr r3, [r7, #0] 800edca: 781b ldrb r3, [r3, #0] 800edcc: 009b lsls r3, r3, #2 800edce: 4413 add r3, r2 800edd0: 881b ldrh r3, [r3, #0] 800edd2: b29b uxth r3, r3 800edd4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800edd8: f023 0370 bic.w r3, r3, #112 @ 0x70 800eddc: f8a7 305a strh.w r3, [r7, #90] @ 0x5a 800ede0: 687a ldr r2, [r7, #4] 800ede2: 683b ldr r3, [r7, #0] 800ede4: 781b ldrb r3, [r3, #0] 800ede6: 009b lsls r3, r3, #2 800ede8: 441a add r2, r3 800edea: f8b7 305a ldrh.w r3, [r7, #90] @ 0x5a 800edee: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800edf2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800edf6: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800edfa: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800edfe: b29b uxth r3, r3 800ee00: 8013 strh r3, [r2, #0] /* Set endpoint RX count */ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); 800ee02: 683b ldr r3, [r7, #0] 800ee04: 785b ldrb r3, [r3, #1] 800ee06: 2b00 cmp r3, #0 800ee08: d16b bne.n 800eee2 800ee0a: 687b ldr r3, [r7, #4] 800ee0c: 64fb str r3, [r7, #76] @ 0x4c 800ee0e: 687b ldr r3, [r7, #4] 800ee10: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ee14: b29b uxth r3, r3 800ee16: 461a mov r2, r3 800ee18: 6cfb ldr r3, [r7, #76] @ 0x4c 800ee1a: 4413 add r3, r2 800ee1c: 64fb str r3, [r7, #76] @ 0x4c 800ee1e: 683b ldr r3, [r7, #0] 800ee20: 781b ldrb r3, [r3, #0] 800ee22: 00da lsls r2, r3, #3 800ee24: 6cfb ldr r3, [r7, #76] @ 0x4c 800ee26: 4413 add r3, r2 800ee28: f203 4302 addw r3, r3, #1026 @ 0x402 800ee2c: 64bb str r3, [r7, #72] @ 0x48 800ee2e: 6cbb ldr r3, [r7, #72] @ 0x48 800ee30: 881b ldrh r3, [r3, #0] 800ee32: b29b uxth r3, r3 800ee34: f3c3 0309 ubfx r3, r3, #0, #10 800ee38: b29a uxth r2, r3 800ee3a: 6cbb ldr r3, [r7, #72] @ 0x48 800ee3c: 801a strh r2, [r3, #0] 800ee3e: 683b ldr r3, [r7, #0] 800ee40: 691b ldr r3, [r3, #16] 800ee42: 2b00 cmp r3, #0 800ee44: d10a bne.n 800ee5c 800ee46: 6cbb ldr r3, [r7, #72] @ 0x48 800ee48: 881b ldrh r3, [r3, #0] 800ee4a: b29b uxth r3, r3 800ee4c: ea6f 4343 mvn.w r3, r3, lsl #17 800ee50: ea6f 4353 mvn.w r3, r3, lsr #17 800ee54: b29a uxth r2, r3 800ee56: 6cbb ldr r3, [r7, #72] @ 0x48 800ee58: 801a strh r2, [r3, #0] 800ee5a: e05d b.n 800ef18 800ee5c: 683b ldr r3, [r7, #0] 800ee5e: 691b ldr r3, [r3, #16] 800ee60: 2b3e cmp r3, #62 @ 0x3e 800ee62: d81c bhi.n 800ee9e 800ee64: 683b ldr r3, [r7, #0] 800ee66: 691b ldr r3, [r3, #16] 800ee68: 085b lsrs r3, r3, #1 800ee6a: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800ee6e: 683b ldr r3, [r7, #0] 800ee70: 691b ldr r3, [r3, #16] 800ee72: f003 0301 and.w r3, r3, #1 800ee76: 2b00 cmp r3, #0 800ee78: d004 beq.n 800ee84 800ee7a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800ee7e: 3301 adds r3, #1 800ee80: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800ee84: 6cbb ldr r3, [r7, #72] @ 0x48 800ee86: 881b ldrh r3, [r3, #0] 800ee88: b29a uxth r2, r3 800ee8a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800ee8e: b29b uxth r3, r3 800ee90: 029b lsls r3, r3, #10 800ee92: b29b uxth r3, r3 800ee94: 4313 orrs r3, r2 800ee96: b29a uxth r2, r3 800ee98: 6cbb ldr r3, [r7, #72] @ 0x48 800ee9a: 801a strh r2, [r3, #0] 800ee9c: e03c b.n 800ef18 800ee9e: 683b ldr r3, [r7, #0] 800eea0: 691b ldr r3, [r3, #16] 800eea2: 095b lsrs r3, r3, #5 800eea4: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800eea8: 683b ldr r3, [r7, #0] 800eeaa: 691b ldr r3, [r3, #16] 800eeac: f003 031f and.w r3, r3, #31 800eeb0: 2b00 cmp r3, #0 800eeb2: d104 bne.n 800eebe 800eeb4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800eeb8: 3b01 subs r3, #1 800eeba: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800eebe: 6cbb ldr r3, [r7, #72] @ 0x48 800eec0: 881b ldrh r3, [r3, #0] 800eec2: b29a uxth r2, r3 800eec4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800eec8: b29b uxth r3, r3 800eeca: 029b lsls r3, r3, #10 800eecc: b29b uxth r3, r3 800eece: 4313 orrs r3, r2 800eed0: b29b uxth r3, r3 800eed2: ea6f 4343 mvn.w r3, r3, lsl #17 800eed6: ea6f 4353 mvn.w r3, r3, lsr #17 800eeda: b29a uxth r2, r3 800eedc: 6cbb ldr r3, [r7, #72] @ 0x48 800eede: 801a strh r2, [r3, #0] 800eee0: e01a b.n 800ef18 800eee2: 683b ldr r3, [r7, #0] 800eee4: 785b ldrb r3, [r3, #1] 800eee6: 2b01 cmp r3, #1 800eee8: d116 bne.n 800ef18 800eeea: 687b ldr r3, [r7, #4] 800eeec: 657b str r3, [r7, #84] @ 0x54 800eeee: 687b ldr r3, [r7, #4] 800eef0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800eef4: b29b uxth r3, r3 800eef6: 461a mov r2, r3 800eef8: 6d7b ldr r3, [r7, #84] @ 0x54 800eefa: 4413 add r3, r2 800eefc: 657b str r3, [r7, #84] @ 0x54 800eefe: 683b ldr r3, [r7, #0] 800ef00: 781b ldrb r3, [r3, #0] 800ef02: 00da lsls r2, r3, #3 800ef04: 6d7b ldr r3, [r7, #84] @ 0x54 800ef06: 4413 add r3, r2 800ef08: f203 4302 addw r3, r3, #1026 @ 0x402 800ef0c: 653b str r3, [r7, #80] @ 0x50 800ef0e: 683b ldr r3, [r7, #0] 800ef10: 691b ldr r3, [r3, #16] 800ef12: b29a uxth r2, r3 800ef14: 6d3b ldr r3, [r7, #80] @ 0x50 800ef16: 801a strh r2, [r3, #0] 800ef18: 687b ldr r3, [r7, #4] 800ef1a: 647b str r3, [r7, #68] @ 0x44 800ef1c: 683b ldr r3, [r7, #0] 800ef1e: 785b ldrb r3, [r3, #1] 800ef20: 2b00 cmp r3, #0 800ef22: d16b bne.n 800effc 800ef24: 687b ldr r3, [r7, #4] 800ef26: 63fb str r3, [r7, #60] @ 0x3c 800ef28: 687b ldr r3, [r7, #4] 800ef2a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ef2e: b29b uxth r3, r3 800ef30: 461a mov r2, r3 800ef32: 6bfb ldr r3, [r7, #60] @ 0x3c 800ef34: 4413 add r3, r2 800ef36: 63fb str r3, [r7, #60] @ 0x3c 800ef38: 683b ldr r3, [r7, #0] 800ef3a: 781b ldrb r3, [r3, #0] 800ef3c: 00da lsls r2, r3, #3 800ef3e: 6bfb ldr r3, [r7, #60] @ 0x3c 800ef40: 4413 add r3, r2 800ef42: f203 4306 addw r3, r3, #1030 @ 0x406 800ef46: 63bb str r3, [r7, #56] @ 0x38 800ef48: 6bbb ldr r3, [r7, #56] @ 0x38 800ef4a: 881b ldrh r3, [r3, #0] 800ef4c: b29b uxth r3, r3 800ef4e: f3c3 0309 ubfx r3, r3, #0, #10 800ef52: b29a uxth r2, r3 800ef54: 6bbb ldr r3, [r7, #56] @ 0x38 800ef56: 801a strh r2, [r3, #0] 800ef58: 683b ldr r3, [r7, #0] 800ef5a: 691b ldr r3, [r3, #16] 800ef5c: 2b00 cmp r3, #0 800ef5e: d10a bne.n 800ef76 800ef60: 6bbb ldr r3, [r7, #56] @ 0x38 800ef62: 881b ldrh r3, [r3, #0] 800ef64: b29b uxth r3, r3 800ef66: ea6f 4343 mvn.w r3, r3, lsl #17 800ef6a: ea6f 4353 mvn.w r3, r3, lsr #17 800ef6e: b29a uxth r2, r3 800ef70: 6bbb ldr r3, [r7, #56] @ 0x38 800ef72: 801a strh r2, [r3, #0] 800ef74: e05b b.n 800f02e 800ef76: 683b ldr r3, [r7, #0] 800ef78: 691b ldr r3, [r3, #16] 800ef7a: 2b3e cmp r3, #62 @ 0x3e 800ef7c: d81c bhi.n 800efb8 800ef7e: 683b ldr r3, [r7, #0] 800ef80: 691b ldr r3, [r3, #16] 800ef82: 085b lsrs r3, r3, #1 800ef84: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800ef88: 683b ldr r3, [r7, #0] 800ef8a: 691b ldr r3, [r3, #16] 800ef8c: f003 0301 and.w r3, r3, #1 800ef90: 2b00 cmp r3, #0 800ef92: d004 beq.n 800ef9e 800ef94: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800ef98: 3301 adds r3, #1 800ef9a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800ef9e: 6bbb ldr r3, [r7, #56] @ 0x38 800efa0: 881b ldrh r3, [r3, #0] 800efa2: b29a uxth r2, r3 800efa4: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800efa8: b29b uxth r3, r3 800efaa: 029b lsls r3, r3, #10 800efac: b29b uxth r3, r3 800efae: 4313 orrs r3, r2 800efb0: b29a uxth r2, r3 800efb2: 6bbb ldr r3, [r7, #56] @ 0x38 800efb4: 801a strh r2, [r3, #0] 800efb6: e03a b.n 800f02e 800efb8: 683b ldr r3, [r7, #0] 800efba: 691b ldr r3, [r3, #16] 800efbc: 095b lsrs r3, r3, #5 800efbe: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800efc2: 683b ldr r3, [r7, #0] 800efc4: 691b ldr r3, [r3, #16] 800efc6: f003 031f and.w r3, r3, #31 800efca: 2b00 cmp r3, #0 800efcc: d104 bne.n 800efd8 800efce: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800efd2: 3b01 subs r3, #1 800efd4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800efd8: 6bbb ldr r3, [r7, #56] @ 0x38 800efda: 881b ldrh r3, [r3, #0] 800efdc: b29a uxth r2, r3 800efde: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800efe2: b29b uxth r3, r3 800efe4: 029b lsls r3, r3, #10 800efe6: b29b uxth r3, r3 800efe8: 4313 orrs r3, r2 800efea: b29b uxth r3, r3 800efec: ea6f 4343 mvn.w r3, r3, lsl #17 800eff0: ea6f 4353 mvn.w r3, r3, lsr #17 800eff4: b29a uxth r2, r3 800eff6: 6bbb ldr r3, [r7, #56] @ 0x38 800eff8: 801a strh r2, [r3, #0] 800effa: e018 b.n 800f02e 800effc: 683b ldr r3, [r7, #0] 800effe: 785b ldrb r3, [r3, #1] 800f000: 2b01 cmp r3, #1 800f002: d114 bne.n 800f02e 800f004: 687b ldr r3, [r7, #4] 800f006: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f00a: b29b uxth r3, r3 800f00c: 461a mov r2, r3 800f00e: 6c7b ldr r3, [r7, #68] @ 0x44 800f010: 4413 add r3, r2 800f012: 647b str r3, [r7, #68] @ 0x44 800f014: 683b ldr r3, [r7, #0] 800f016: 781b ldrb r3, [r3, #0] 800f018: 00da lsls r2, r3, #3 800f01a: 6c7b ldr r3, [r7, #68] @ 0x44 800f01c: 4413 add r3, r2 800f01e: f203 4306 addw r3, r3, #1030 @ 0x406 800f022: 643b str r3, [r7, #64] @ 0x40 800f024: 683b ldr r3, [r7, #0] 800f026: 691b ldr r3, [r3, #16] 800f028: b29a uxth r2, r3 800f02a: 6c3b ldr r3, [r7, #64] @ 0x40 800f02c: 801a strh r2, [r3, #0] /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 800f02e: 687a ldr r2, [r7, #4] 800f030: 683b ldr r3, [r7, #0] 800f032: 781b ldrb r3, [r3, #0] 800f034: 009b lsls r3, r3, #2 800f036: 4413 add r3, r2 800f038: 881b ldrh r3, [r3, #0] 800f03a: b29b uxth r3, r3 800f03c: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800f040: f023 0370 bic.w r3, r3, #112 @ 0x70 800f044: 86fb strh r3, [r7, #54] @ 0x36 800f046: 8efb ldrh r3, [r7, #54] @ 0x36 800f048: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800f04c: 86fb strh r3, [r7, #54] @ 0x36 800f04e: 8efb ldrh r3, [r7, #54] @ 0x36 800f050: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800f054: 86fb strh r3, [r7, #54] @ 0x36 800f056: 687a ldr r2, [r7, #4] 800f058: 683b ldr r3, [r7, #0] 800f05a: 781b ldrb r3, [r3, #0] 800f05c: 009b lsls r3, r3, #2 800f05e: 441a add r2, r3 800f060: 8efb ldrh r3, [r7, #54] @ 0x36 800f062: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f066: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f06a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f06e: f043 0380 orr.w r3, r3, #128 @ 0x80 800f072: b29b uxth r3, r3 800f074: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800f076: 687a ldr r2, [r7, #4] 800f078: 683b ldr r3, [r7, #0] 800f07a: 781b ldrb r3, [r3, #0] 800f07c: 009b lsls r3, r3, #2 800f07e: 4413 add r3, r2 800f080: 881b ldrh r3, [r3, #0] 800f082: b29b uxth r3, r3 800f084: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f088: f023 0340 bic.w r3, r3, #64 @ 0x40 800f08c: 86bb strh r3, [r7, #52] @ 0x34 800f08e: 687a ldr r2, [r7, #4] 800f090: 683b ldr r3, [r7, #0] 800f092: 781b ldrb r3, [r3, #0] 800f094: 009b lsls r3, r3, #2 800f096: 441a add r2, r3 800f098: 8ebb ldrh r3, [r7, #52] @ 0x34 800f09a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f09e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f0a2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f0a6: f043 0380 orr.w r3, r3, #128 @ 0x80 800f0aa: b29b uxth r3, r3 800f0ac: 8013 strh r3, [r2, #0] 800f0ae: e0bc b.n 800f22a } else { /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800f0b0: 687a ldr r2, [r7, #4] 800f0b2: 683b ldr r3, [r7, #0] 800f0b4: 781b ldrb r3, [r3, #0] 800f0b6: 009b lsls r3, r3, #2 800f0b8: 4413 add r3, r2 800f0ba: 881b ldrh r3, [r3, #0] 800f0bc: f8a7 306e strh.w r3, [r7, #110] @ 0x6e 800f0c0: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 800f0c4: f403 4380 and.w r3, r3, #16384 @ 0x4000 800f0c8: 2b00 cmp r3, #0 800f0ca: d01d beq.n 800f108 800f0cc: 687a ldr r2, [r7, #4] 800f0ce: 683b ldr r3, [r7, #0] 800f0d0: 781b ldrb r3, [r3, #0] 800f0d2: 009b lsls r3, r3, #2 800f0d4: 4413 add r3, r2 800f0d6: 881b ldrh r3, [r3, #0] 800f0d8: b29b uxth r3, r3 800f0da: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f0de: f023 0370 bic.w r3, r3, #112 @ 0x70 800f0e2: f8a7 306c strh.w r3, [r7, #108] @ 0x6c 800f0e6: 687a ldr r2, [r7, #4] 800f0e8: 683b ldr r3, [r7, #0] 800f0ea: 781b ldrb r3, [r3, #0] 800f0ec: 009b lsls r3, r3, #2 800f0ee: 441a add r2, r3 800f0f0: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 800f0f4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f0f8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f0fc: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800f100: f043 0380 orr.w r3, r3, #128 @ 0x80 800f104: b29b uxth r3, r3 800f106: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800f108: 687a ldr r2, [r7, #4] 800f10a: 683b ldr r3, [r7, #0] 800f10c: 781b ldrb r3, [r3, #0] 800f10e: 009b lsls r3, r3, #2 800f110: 4413 add r3, r2 800f112: 881b ldrh r3, [r3, #0] 800f114: f8a7 306a strh.w r3, [r7, #106] @ 0x6a 800f118: f8b7 306a ldrh.w r3, [r7, #106] @ 0x6a 800f11c: f003 0340 and.w r3, r3, #64 @ 0x40 800f120: 2b00 cmp r3, #0 800f122: d01d beq.n 800f160 800f124: 687a ldr r2, [r7, #4] 800f126: 683b ldr r3, [r7, #0] 800f128: 781b ldrb r3, [r3, #0] 800f12a: 009b lsls r3, r3, #2 800f12c: 4413 add r3, r2 800f12e: 881b ldrh r3, [r3, #0] 800f130: b29b uxth r3, r3 800f132: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f136: f023 0370 bic.w r3, r3, #112 @ 0x70 800f13a: f8a7 3068 strh.w r3, [r7, #104] @ 0x68 800f13e: 687a ldr r2, [r7, #4] 800f140: 683b ldr r3, [r7, #0] 800f142: 781b ldrb r3, [r3, #0] 800f144: 009b lsls r3, r3, #2 800f146: 441a add r2, r3 800f148: f8b7 3068 ldrh.w r3, [r7, #104] @ 0x68 800f14c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f150: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f154: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f158: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800f15c: b29b uxth r3, r3 800f15e: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800f160: 683b ldr r3, [r7, #0] 800f162: 78db ldrb r3, [r3, #3] 800f164: 2b01 cmp r3, #1 800f166: d024 beq.n 800f1b2 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 800f168: 687a ldr r2, [r7, #4] 800f16a: 683b ldr r3, [r7, #0] 800f16c: 781b ldrb r3, [r3, #0] 800f16e: 009b lsls r3, r3, #2 800f170: 4413 add r3, r2 800f172: 881b ldrh r3, [r3, #0] 800f174: b29b uxth r3, r3 800f176: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f17a: f023 0340 bic.w r3, r3, #64 @ 0x40 800f17e: f8a7 3064 strh.w r3, [r7, #100] @ 0x64 800f182: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64 800f186: f083 0320 eor.w r3, r3, #32 800f18a: f8a7 3064 strh.w r3, [r7, #100] @ 0x64 800f18e: 687a ldr r2, [r7, #4] 800f190: 683b ldr r3, [r7, #0] 800f192: 781b ldrb r3, [r3, #0] 800f194: 009b lsls r3, r3, #2 800f196: 441a add r2, r3 800f198: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64 800f19c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f1a0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f1a4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f1a8: f043 0380 orr.w r3, r3, #128 @ 0x80 800f1ac: b29b uxth r3, r3 800f1ae: 8013 strh r3, [r2, #0] 800f1b0: e01d b.n 800f1ee } else { /* Configure TX Endpoint to disabled state */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800f1b2: 687a ldr r2, [r7, #4] 800f1b4: 683b ldr r3, [r7, #0] 800f1b6: 781b ldrb r3, [r3, #0] 800f1b8: 009b lsls r3, r3, #2 800f1ba: 4413 add r3, r2 800f1bc: 881b ldrh r3, [r3, #0] 800f1be: b29b uxth r3, r3 800f1c0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f1c4: f023 0340 bic.w r3, r3, #64 @ 0x40 800f1c8: f8a7 3066 strh.w r3, [r7, #102] @ 0x66 800f1cc: 687a ldr r2, [r7, #4] 800f1ce: 683b ldr r3, [r7, #0] 800f1d0: 781b ldrb r3, [r3, #0] 800f1d2: 009b lsls r3, r3, #2 800f1d4: 441a add r2, r3 800f1d6: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66 800f1da: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f1de: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f1e2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f1e6: f043 0380 orr.w r3, r3, #128 @ 0x80 800f1ea: b29b uxth r3, r3 800f1ec: 8013 strh r3, [r2, #0] } PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800f1ee: 687a ldr r2, [r7, #4] 800f1f0: 683b ldr r3, [r7, #0] 800f1f2: 781b ldrb r3, [r3, #0] 800f1f4: 009b lsls r3, r3, #2 800f1f6: 4413 add r3, r2 800f1f8: 881b ldrh r3, [r3, #0] 800f1fa: b29b uxth r3, r3 800f1fc: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800f200: f023 0370 bic.w r3, r3, #112 @ 0x70 800f204: f8a7 3062 strh.w r3, [r7, #98] @ 0x62 800f208: 687a ldr r2, [r7, #4] 800f20a: 683b ldr r3, [r7, #0] 800f20c: 781b ldrb r3, [r3, #0] 800f20e: 009b lsls r3, r3, #2 800f210: 441a add r2, r3 800f212: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62 800f216: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f21a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f21e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f222: f043 0380 orr.w r3, r3, #128 @ 0x80 800f226: b29b uxth r3, r3 800f228: 8013 strh r3, [r2, #0] } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return ret; 800f22a: f897 3097 ldrb.w r3, [r7, #151] @ 0x97 } 800f22e: 4618 mov r0, r3 800f230: 379c adds r7, #156 @ 0x9c 800f232: 46bd mov sp, r7 800f234: f85d 7b04 ldr.w r7, [sp], #4 800f238: 4770 bx lr 800f23a: bf00 nop 0800f23c : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800f23c: b480 push {r7} 800f23e: b08d sub sp, #52 @ 0x34 800f240: af00 add r7, sp, #0 800f242: 6078 str r0, [r7, #4] 800f244: 6039 str r1, [r7, #0] if (ep->doublebuffer == 0U) 800f246: 683b ldr r3, [r7, #0] 800f248: 7b1b ldrb r3, [r3, #12] 800f24a: 2b00 cmp r3, #0 800f24c: f040 808e bne.w 800f36c { if (ep->is_in != 0U) 800f250: 683b ldr r3, [r7, #0] 800f252: 785b ldrb r3, [r3, #1] 800f254: 2b00 cmp r3, #0 800f256: d044 beq.n 800f2e2 { PCD_CLEAR_TX_DTOG(USBx, ep->num); 800f258: 687a ldr r2, [r7, #4] 800f25a: 683b ldr r3, [r7, #0] 800f25c: 781b ldrb r3, [r3, #0] 800f25e: 009b lsls r3, r3, #2 800f260: 4413 add r3, r2 800f262: 881b ldrh r3, [r3, #0] 800f264: 81bb strh r3, [r7, #12] 800f266: 89bb ldrh r3, [r7, #12] 800f268: f003 0340 and.w r3, r3, #64 @ 0x40 800f26c: 2b00 cmp r3, #0 800f26e: d01b beq.n 800f2a8 800f270: 687a ldr r2, [r7, #4] 800f272: 683b ldr r3, [r7, #0] 800f274: 781b ldrb r3, [r3, #0] 800f276: 009b lsls r3, r3, #2 800f278: 4413 add r3, r2 800f27a: 881b ldrh r3, [r3, #0] 800f27c: b29b uxth r3, r3 800f27e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f282: f023 0370 bic.w r3, r3, #112 @ 0x70 800f286: 817b strh r3, [r7, #10] 800f288: 687a ldr r2, [r7, #4] 800f28a: 683b ldr r3, [r7, #0] 800f28c: 781b ldrb r3, [r3, #0] 800f28e: 009b lsls r3, r3, #2 800f290: 441a add r2, r3 800f292: 897b ldrh r3, [r7, #10] 800f294: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f298: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f29c: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f2a0: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800f2a4: b29b uxth r3, r3 800f2a6: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800f2a8: 687a ldr r2, [r7, #4] 800f2aa: 683b ldr r3, [r7, #0] 800f2ac: 781b ldrb r3, [r3, #0] 800f2ae: 009b lsls r3, r3, #2 800f2b0: 4413 add r3, r2 800f2b2: 881b ldrh r3, [r3, #0] 800f2b4: b29b uxth r3, r3 800f2b6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f2ba: f023 0340 bic.w r3, r3, #64 @ 0x40 800f2be: 813b strh r3, [r7, #8] 800f2c0: 687a ldr r2, [r7, #4] 800f2c2: 683b ldr r3, [r7, #0] 800f2c4: 781b ldrb r3, [r3, #0] 800f2c6: 009b lsls r3, r3, #2 800f2c8: 441a add r2, r3 800f2ca: 893b ldrh r3, [r7, #8] 800f2cc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f2d0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f2d4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f2d8: f043 0380 orr.w r3, r3, #128 @ 0x80 800f2dc: b29b uxth r3, r3 800f2de: 8013 strh r3, [r2, #0] 800f2e0: e192 b.n 800f608 } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); 800f2e2: 687a ldr r2, [r7, #4] 800f2e4: 683b ldr r3, [r7, #0] 800f2e6: 781b ldrb r3, [r3, #0] 800f2e8: 009b lsls r3, r3, #2 800f2ea: 4413 add r3, r2 800f2ec: 881b ldrh r3, [r3, #0] 800f2ee: 827b strh r3, [r7, #18] 800f2f0: 8a7b ldrh r3, [r7, #18] 800f2f2: f403 4380 and.w r3, r3, #16384 @ 0x4000 800f2f6: 2b00 cmp r3, #0 800f2f8: d01b beq.n 800f332 800f2fa: 687a ldr r2, [r7, #4] 800f2fc: 683b ldr r3, [r7, #0] 800f2fe: 781b ldrb r3, [r3, #0] 800f300: 009b lsls r3, r3, #2 800f302: 4413 add r3, r2 800f304: 881b ldrh r3, [r3, #0] 800f306: b29b uxth r3, r3 800f308: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f30c: f023 0370 bic.w r3, r3, #112 @ 0x70 800f310: 823b strh r3, [r7, #16] 800f312: 687a ldr r2, [r7, #4] 800f314: 683b ldr r3, [r7, #0] 800f316: 781b ldrb r3, [r3, #0] 800f318: 009b lsls r3, r3, #2 800f31a: 441a add r2, r3 800f31c: 8a3b ldrh r3, [r7, #16] 800f31e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f322: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f326: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800f32a: f043 0380 orr.w r3, r3, #128 @ 0x80 800f32e: b29b uxth r3, r3 800f330: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800f332: 687a ldr r2, [r7, #4] 800f334: 683b ldr r3, [r7, #0] 800f336: 781b ldrb r3, [r3, #0] 800f338: 009b lsls r3, r3, #2 800f33a: 4413 add r3, r2 800f33c: 881b ldrh r3, [r3, #0] 800f33e: b29b uxth r3, r3 800f340: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800f344: f023 0370 bic.w r3, r3, #112 @ 0x70 800f348: 81fb strh r3, [r7, #14] 800f34a: 687a ldr r2, [r7, #4] 800f34c: 683b ldr r3, [r7, #0] 800f34e: 781b ldrb r3, [r3, #0] 800f350: 009b lsls r3, r3, #2 800f352: 441a add r2, r3 800f354: 89fb ldrh r3, [r7, #14] 800f356: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f35a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f35e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f362: f043 0380 orr.w r3, r3, #128 @ 0x80 800f366: b29b uxth r3, r3 800f368: 8013 strh r3, [r2, #0] 800f36a: e14d b.n 800f608 } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer */ else { if (ep->is_in == 0U) 800f36c: 683b ldr r3, [r7, #0] 800f36e: 785b ldrb r3, [r3, #1] 800f370: 2b00 cmp r3, #0 800f372: f040 80a5 bne.w 800f4c0 { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800f376: 687a ldr r2, [r7, #4] 800f378: 683b ldr r3, [r7, #0] 800f37a: 781b ldrb r3, [r3, #0] 800f37c: 009b lsls r3, r3, #2 800f37e: 4413 add r3, r2 800f380: 881b ldrh r3, [r3, #0] 800f382: 843b strh r3, [r7, #32] 800f384: 8c3b ldrh r3, [r7, #32] 800f386: f403 4380 and.w r3, r3, #16384 @ 0x4000 800f38a: 2b00 cmp r3, #0 800f38c: d01b beq.n 800f3c6 800f38e: 687a ldr r2, [r7, #4] 800f390: 683b ldr r3, [r7, #0] 800f392: 781b ldrb r3, [r3, #0] 800f394: 009b lsls r3, r3, #2 800f396: 4413 add r3, r2 800f398: 881b ldrh r3, [r3, #0] 800f39a: b29b uxth r3, r3 800f39c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f3a0: f023 0370 bic.w r3, r3, #112 @ 0x70 800f3a4: 83fb strh r3, [r7, #30] 800f3a6: 687a ldr r2, [r7, #4] 800f3a8: 683b ldr r3, [r7, #0] 800f3aa: 781b ldrb r3, [r3, #0] 800f3ac: 009b lsls r3, r3, #2 800f3ae: 441a add r2, r3 800f3b0: 8bfb ldrh r3, [r7, #30] 800f3b2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f3b6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f3ba: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800f3be: f043 0380 orr.w r3, r3, #128 @ 0x80 800f3c2: b29b uxth r3, r3 800f3c4: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800f3c6: 687a ldr r2, [r7, #4] 800f3c8: 683b ldr r3, [r7, #0] 800f3ca: 781b ldrb r3, [r3, #0] 800f3cc: 009b lsls r3, r3, #2 800f3ce: 4413 add r3, r2 800f3d0: 881b ldrh r3, [r3, #0] 800f3d2: 83bb strh r3, [r7, #28] 800f3d4: 8bbb ldrh r3, [r7, #28] 800f3d6: f003 0340 and.w r3, r3, #64 @ 0x40 800f3da: 2b00 cmp r3, #0 800f3dc: d01b beq.n 800f416 800f3de: 687a ldr r2, [r7, #4] 800f3e0: 683b ldr r3, [r7, #0] 800f3e2: 781b ldrb r3, [r3, #0] 800f3e4: 009b lsls r3, r3, #2 800f3e6: 4413 add r3, r2 800f3e8: 881b ldrh r3, [r3, #0] 800f3ea: b29b uxth r3, r3 800f3ec: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f3f0: f023 0370 bic.w r3, r3, #112 @ 0x70 800f3f4: 837b strh r3, [r7, #26] 800f3f6: 687a ldr r2, [r7, #4] 800f3f8: 683b ldr r3, [r7, #0] 800f3fa: 781b ldrb r3, [r3, #0] 800f3fc: 009b lsls r3, r3, #2 800f3fe: 441a add r2, r3 800f400: 8b7b ldrh r3, [r7, #26] 800f402: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f406: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f40a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f40e: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800f412: b29b uxth r3, r3 800f414: 8013 strh r3, [r2, #0] /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); 800f416: 687a ldr r2, [r7, #4] 800f418: 683b ldr r3, [r7, #0] 800f41a: 781b ldrb r3, [r3, #0] 800f41c: 009b lsls r3, r3, #2 800f41e: 4413 add r3, r2 800f420: 881b ldrh r3, [r3, #0] 800f422: b29b uxth r3, r3 800f424: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f428: f023 0370 bic.w r3, r3, #112 @ 0x70 800f42c: 833b strh r3, [r7, #24] 800f42e: 687a ldr r2, [r7, #4] 800f430: 683b ldr r3, [r7, #0] 800f432: 781b ldrb r3, [r3, #0] 800f434: 009b lsls r3, r3, #2 800f436: 441a add r2, r3 800f438: 8b3b ldrh r3, [r7, #24] 800f43a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f43e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f442: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f446: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800f44a: b29b uxth r3, r3 800f44c: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800f44e: 687a ldr r2, [r7, #4] 800f450: 683b ldr r3, [r7, #0] 800f452: 781b ldrb r3, [r3, #0] 800f454: 009b lsls r3, r3, #2 800f456: 4413 add r3, r2 800f458: 881b ldrh r3, [r3, #0] 800f45a: b29b uxth r3, r3 800f45c: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800f460: f023 0370 bic.w r3, r3, #112 @ 0x70 800f464: 82fb strh r3, [r7, #22] 800f466: 687a ldr r2, [r7, #4] 800f468: 683b ldr r3, [r7, #0] 800f46a: 781b ldrb r3, [r3, #0] 800f46c: 009b lsls r3, r3, #2 800f46e: 441a add r2, r3 800f470: 8afb ldrh r3, [r7, #22] 800f472: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f476: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f47a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f47e: f043 0380 orr.w r3, r3, #128 @ 0x80 800f482: b29b uxth r3, r3 800f484: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800f486: 687a ldr r2, [r7, #4] 800f488: 683b ldr r3, [r7, #0] 800f48a: 781b ldrb r3, [r3, #0] 800f48c: 009b lsls r3, r3, #2 800f48e: 4413 add r3, r2 800f490: 881b ldrh r3, [r3, #0] 800f492: b29b uxth r3, r3 800f494: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f498: f023 0340 bic.w r3, r3, #64 @ 0x40 800f49c: 82bb strh r3, [r7, #20] 800f49e: 687a ldr r2, [r7, #4] 800f4a0: 683b ldr r3, [r7, #0] 800f4a2: 781b ldrb r3, [r3, #0] 800f4a4: 009b lsls r3, r3, #2 800f4a6: 441a add r2, r3 800f4a8: 8abb ldrh r3, [r7, #20] 800f4aa: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f4ae: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f4b2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f4b6: f043 0380 orr.w r3, r3, #128 @ 0x80 800f4ba: b29b uxth r3, r3 800f4bc: 8013 strh r3, [r2, #0] 800f4be: e0a3 b.n 800f608 } else { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800f4c0: 687a ldr r2, [r7, #4] 800f4c2: 683b ldr r3, [r7, #0] 800f4c4: 781b ldrb r3, [r3, #0] 800f4c6: 009b lsls r3, r3, #2 800f4c8: 4413 add r3, r2 800f4ca: 881b ldrh r3, [r3, #0] 800f4cc: 85fb strh r3, [r7, #46] @ 0x2e 800f4ce: 8dfb ldrh r3, [r7, #46] @ 0x2e 800f4d0: f403 4380 and.w r3, r3, #16384 @ 0x4000 800f4d4: 2b00 cmp r3, #0 800f4d6: d01b beq.n 800f510 800f4d8: 687a ldr r2, [r7, #4] 800f4da: 683b ldr r3, [r7, #0] 800f4dc: 781b ldrb r3, [r3, #0] 800f4de: 009b lsls r3, r3, #2 800f4e0: 4413 add r3, r2 800f4e2: 881b ldrh r3, [r3, #0] 800f4e4: b29b uxth r3, r3 800f4e6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f4ea: f023 0370 bic.w r3, r3, #112 @ 0x70 800f4ee: 85bb strh r3, [r7, #44] @ 0x2c 800f4f0: 687a ldr r2, [r7, #4] 800f4f2: 683b ldr r3, [r7, #0] 800f4f4: 781b ldrb r3, [r3, #0] 800f4f6: 009b lsls r3, r3, #2 800f4f8: 441a add r2, r3 800f4fa: 8dbb ldrh r3, [r7, #44] @ 0x2c 800f4fc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f500: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f504: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800f508: f043 0380 orr.w r3, r3, #128 @ 0x80 800f50c: b29b uxth r3, r3 800f50e: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800f510: 687a ldr r2, [r7, #4] 800f512: 683b ldr r3, [r7, #0] 800f514: 781b ldrb r3, [r3, #0] 800f516: 009b lsls r3, r3, #2 800f518: 4413 add r3, r2 800f51a: 881b ldrh r3, [r3, #0] 800f51c: 857b strh r3, [r7, #42] @ 0x2a 800f51e: 8d7b ldrh r3, [r7, #42] @ 0x2a 800f520: f003 0340 and.w r3, r3, #64 @ 0x40 800f524: 2b00 cmp r3, #0 800f526: d01b beq.n 800f560 800f528: 687a ldr r2, [r7, #4] 800f52a: 683b ldr r3, [r7, #0] 800f52c: 781b ldrb r3, [r3, #0] 800f52e: 009b lsls r3, r3, #2 800f530: 4413 add r3, r2 800f532: 881b ldrh r3, [r3, #0] 800f534: b29b uxth r3, r3 800f536: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f53a: f023 0370 bic.w r3, r3, #112 @ 0x70 800f53e: 853b strh r3, [r7, #40] @ 0x28 800f540: 687a ldr r2, [r7, #4] 800f542: 683b ldr r3, [r7, #0] 800f544: 781b ldrb r3, [r3, #0] 800f546: 009b lsls r3, r3, #2 800f548: 441a add r2, r3 800f54a: 8d3b ldrh r3, [r7, #40] @ 0x28 800f54c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f550: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f554: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f558: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800f55c: b29b uxth r3, r3 800f55e: 8013 strh r3, [r2, #0] PCD_RX_DTOG(USBx, ep->num); 800f560: 687a ldr r2, [r7, #4] 800f562: 683b ldr r3, [r7, #0] 800f564: 781b ldrb r3, [r3, #0] 800f566: 009b lsls r3, r3, #2 800f568: 4413 add r3, r2 800f56a: 881b ldrh r3, [r3, #0] 800f56c: b29b uxth r3, r3 800f56e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f572: f023 0370 bic.w r3, r3, #112 @ 0x70 800f576: 84fb strh r3, [r7, #38] @ 0x26 800f578: 687a ldr r2, [r7, #4] 800f57a: 683b ldr r3, [r7, #0] 800f57c: 781b ldrb r3, [r3, #0] 800f57e: 009b lsls r3, r3, #2 800f580: 441a add r2, r3 800f582: 8cfb ldrh r3, [r7, #38] @ 0x26 800f584: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f588: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f58c: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800f590: f043 0380 orr.w r3, r3, #128 @ 0x80 800f594: b29b uxth r3, r3 800f596: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800f598: 687a ldr r2, [r7, #4] 800f59a: 683b ldr r3, [r7, #0] 800f59c: 781b ldrb r3, [r3, #0] 800f59e: 009b lsls r3, r3, #2 800f5a0: 4413 add r3, r2 800f5a2: 881b ldrh r3, [r3, #0] 800f5a4: b29b uxth r3, r3 800f5a6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f5aa: f023 0340 bic.w r3, r3, #64 @ 0x40 800f5ae: 84bb strh r3, [r7, #36] @ 0x24 800f5b0: 687a ldr r2, [r7, #4] 800f5b2: 683b ldr r3, [r7, #0] 800f5b4: 781b ldrb r3, [r3, #0] 800f5b6: 009b lsls r3, r3, #2 800f5b8: 441a add r2, r3 800f5ba: 8cbb ldrh r3, [r7, #36] @ 0x24 800f5bc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f5c0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f5c4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f5c8: f043 0380 orr.w r3, r3, #128 @ 0x80 800f5cc: b29b uxth r3, r3 800f5ce: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800f5d0: 687a ldr r2, [r7, #4] 800f5d2: 683b ldr r3, [r7, #0] 800f5d4: 781b ldrb r3, [r3, #0] 800f5d6: 009b lsls r3, r3, #2 800f5d8: 4413 add r3, r2 800f5da: 881b ldrh r3, [r3, #0] 800f5dc: b29b uxth r3, r3 800f5de: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800f5e2: f023 0370 bic.w r3, r3, #112 @ 0x70 800f5e6: 847b strh r3, [r7, #34] @ 0x22 800f5e8: 687a ldr r2, [r7, #4] 800f5ea: 683b ldr r3, [r7, #0] 800f5ec: 781b ldrb r3, [r3, #0] 800f5ee: 009b lsls r3, r3, #2 800f5f0: 441a add r2, r3 800f5f2: 8c7b ldrh r3, [r7, #34] @ 0x22 800f5f4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f5f8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f5fc: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f600: f043 0380 orr.w r3, r3, #128 @ 0x80 800f604: b29b uxth r3, r3 800f606: 8013 strh r3, [r2, #0] } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; 800f608: 2300 movs r3, #0 } 800f60a: 4618 mov r0, r3 800f60c: 3734 adds r7, #52 @ 0x34 800f60e: 46bd mov sp, r7 800f610: f85d 7b04 ldr.w r7, [sp], #4 800f614: 4770 bx lr 0800f616 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800f616: b580 push {r7, lr} 800f618: b0ac sub sp, #176 @ 0xb0 800f61a: af00 add r7, sp, #0 800f61c: 6078 str r0, [r7, #4] 800f61e: 6039 str r1, [r7, #0] uint16_t pmabuffer; uint16_t wEPVal; #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* IN endpoint */ if (ep->is_in == 1U) 800f620: 683b ldr r3, [r7, #0] 800f622: 785b ldrb r3, [r3, #1] 800f624: 2b01 cmp r3, #1 800f626: f040 84ca bne.w 800ffbe { /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) 800f62a: 683b ldr r3, [r7, #0] 800f62c: 699a ldr r2, [r3, #24] 800f62e: 683b ldr r3, [r7, #0] 800f630: 691b ldr r3, [r3, #16] 800f632: 429a cmp r2, r3 800f634: d904 bls.n 800f640 { len = ep->maxpacket; 800f636: 683b ldr r3, [r7, #0] 800f638: 691b ldr r3, [r3, #16] 800f63a: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800f63e: e003 b.n 800f648 } else { len = ep->xfer_len; 800f640: 683b ldr r3, [r7, #0] 800f642: 699b ldr r3, [r3, #24] 800f644: f8c7 30ac str.w r3, [r7, #172] @ 0xac } /* configure and validate Tx endpoint */ if (ep->doublebuffer == 0U) 800f648: 683b ldr r3, [r7, #0] 800f64a: 7b1b ldrb r3, [r3, #12] 800f64c: 2b00 cmp r3, #0 800f64e: d122 bne.n 800f696 { USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); 800f650: 683b ldr r3, [r7, #0] 800f652: 6959 ldr r1, [r3, #20] 800f654: 683b ldr r3, [r7, #0] 800f656: 88da ldrh r2, [r3, #6] 800f658: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f65c: b29b uxth r3, r3 800f65e: 6878 ldr r0, [r7, #4] 800f660: f000 febd bl 80103de PCD_SET_EP_TX_CNT(USBx, ep->num, len); 800f664: 687b ldr r3, [r7, #4] 800f666: 613b str r3, [r7, #16] 800f668: 687b ldr r3, [r7, #4] 800f66a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f66e: b29b uxth r3, r3 800f670: 461a mov r2, r3 800f672: 693b ldr r3, [r7, #16] 800f674: 4413 add r3, r2 800f676: 613b str r3, [r7, #16] 800f678: 683b ldr r3, [r7, #0] 800f67a: 781b ldrb r3, [r3, #0] 800f67c: 00da lsls r2, r3, #3 800f67e: 693b ldr r3, [r7, #16] 800f680: 4413 add r3, r2 800f682: f203 4302 addw r3, r3, #1026 @ 0x402 800f686: 60fb str r3, [r7, #12] 800f688: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f68c: b29a uxth r2, r3 800f68e: 68fb ldr r3, [r7, #12] 800f690: 801a strh r2, [r3, #0] 800f692: f000 bc6f b.w 800ff74 } #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* double buffer bulk management */ if (ep->type == EP_TYPE_BULK) 800f696: 683b ldr r3, [r7, #0] 800f698: 78db ldrb r3, [r3, #3] 800f69a: 2b02 cmp r3, #2 800f69c: f040 831e bne.w 800fcdc { if (ep->xfer_len_db > ep->maxpacket) 800f6a0: 683b ldr r3, [r7, #0] 800f6a2: 6a1a ldr r2, [r3, #32] 800f6a4: 683b ldr r3, [r7, #0] 800f6a6: 691b ldr r3, [r3, #16] 800f6a8: 429a cmp r2, r3 800f6aa: f240 82cf bls.w 800fc4c { /* enable double buffer */ PCD_SET_BULK_EP_DBUF(USBx, ep->num); 800f6ae: 687a ldr r2, [r7, #4] 800f6b0: 683b ldr r3, [r7, #0] 800f6b2: 781b ldrb r3, [r3, #0] 800f6b4: 009b lsls r3, r3, #2 800f6b6: 4413 add r3, r2 800f6b8: 881b ldrh r3, [r3, #0] 800f6ba: b29b uxth r3, r3 800f6bc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f6c0: f023 0370 bic.w r3, r3, #112 @ 0x70 800f6c4: f8a7 3056 strh.w r3, [r7, #86] @ 0x56 800f6c8: 687a ldr r2, [r7, #4] 800f6ca: 683b ldr r3, [r7, #0] 800f6cc: 781b ldrb r3, [r3, #0] 800f6ce: 009b lsls r3, r3, #2 800f6d0: 441a add r2, r3 800f6d2: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56 800f6d6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f6da: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f6de: f443 4301 orr.w r3, r3, #33024 @ 0x8100 800f6e2: f043 0380 orr.w r3, r3, #128 @ 0x80 800f6e6: b29b uxth r3, r3 800f6e8: 8013 strh r3, [r2, #0] /* each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; 800f6ea: 683b ldr r3, [r7, #0] 800f6ec: 6a1a ldr r2, [r3, #32] 800f6ee: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f6f2: 1ad2 subs r2, r2, r3 800f6f4: 683b ldr r3, [r7, #0] 800f6f6: 621a str r2, [r3, #32] /* Fill the two first buffer in the Buffer0 & Buffer1 */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) 800f6f8: 687a ldr r2, [r7, #4] 800f6fa: 683b ldr r3, [r7, #0] 800f6fc: 781b ldrb r3, [r3, #0] 800f6fe: 009b lsls r3, r3, #2 800f700: 4413 add r3, r2 800f702: 881b ldrh r3, [r3, #0] 800f704: b29b uxth r3, r3 800f706: f003 0340 and.w r3, r3, #64 @ 0x40 800f70a: 2b00 cmp r3, #0 800f70c: f000 814f beq.w 800f9ae { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 800f710: 687b ldr r3, [r7, #4] 800f712: 633b str r3, [r7, #48] @ 0x30 800f714: 683b ldr r3, [r7, #0] 800f716: 785b ldrb r3, [r3, #1] 800f718: 2b00 cmp r3, #0 800f71a: d16b bne.n 800f7f4 800f71c: 687b ldr r3, [r7, #4] 800f71e: 62bb str r3, [r7, #40] @ 0x28 800f720: 687b ldr r3, [r7, #4] 800f722: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f726: b29b uxth r3, r3 800f728: 461a mov r2, r3 800f72a: 6abb ldr r3, [r7, #40] @ 0x28 800f72c: 4413 add r3, r2 800f72e: 62bb str r3, [r7, #40] @ 0x28 800f730: 683b ldr r3, [r7, #0] 800f732: 781b ldrb r3, [r3, #0] 800f734: 00da lsls r2, r3, #3 800f736: 6abb ldr r3, [r7, #40] @ 0x28 800f738: 4413 add r3, r2 800f73a: f203 4306 addw r3, r3, #1030 @ 0x406 800f73e: 627b str r3, [r7, #36] @ 0x24 800f740: 6a7b ldr r3, [r7, #36] @ 0x24 800f742: 881b ldrh r3, [r3, #0] 800f744: b29b uxth r3, r3 800f746: f3c3 0309 ubfx r3, r3, #0, #10 800f74a: b29a uxth r2, r3 800f74c: 6a7b ldr r3, [r7, #36] @ 0x24 800f74e: 801a strh r2, [r3, #0] 800f750: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f754: 2b00 cmp r3, #0 800f756: d10a bne.n 800f76e 800f758: 6a7b ldr r3, [r7, #36] @ 0x24 800f75a: 881b ldrh r3, [r3, #0] 800f75c: b29b uxth r3, r3 800f75e: ea6f 4343 mvn.w r3, r3, lsl #17 800f762: ea6f 4353 mvn.w r3, r3, lsr #17 800f766: b29a uxth r2, r3 800f768: 6a7b ldr r3, [r7, #36] @ 0x24 800f76a: 801a strh r2, [r3, #0] 800f76c: e05b b.n 800f826 800f76e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f772: 2b3e cmp r3, #62 @ 0x3e 800f774: d81c bhi.n 800f7b0 800f776: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f77a: 085b lsrs r3, r3, #1 800f77c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800f780: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f784: f003 0301 and.w r3, r3, #1 800f788: 2b00 cmp r3, #0 800f78a: d004 beq.n 800f796 800f78c: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800f790: 3301 adds r3, #1 800f792: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800f796: 6a7b ldr r3, [r7, #36] @ 0x24 800f798: 881b ldrh r3, [r3, #0] 800f79a: b29a uxth r2, r3 800f79c: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800f7a0: b29b uxth r3, r3 800f7a2: 029b lsls r3, r3, #10 800f7a4: b29b uxth r3, r3 800f7a6: 4313 orrs r3, r2 800f7a8: b29a uxth r2, r3 800f7aa: 6a7b ldr r3, [r7, #36] @ 0x24 800f7ac: 801a strh r2, [r3, #0] 800f7ae: e03a b.n 800f826 800f7b0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f7b4: 095b lsrs r3, r3, #5 800f7b6: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800f7ba: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f7be: f003 031f and.w r3, r3, #31 800f7c2: 2b00 cmp r3, #0 800f7c4: d104 bne.n 800f7d0 800f7c6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800f7ca: 3b01 subs r3, #1 800f7cc: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800f7d0: 6a7b ldr r3, [r7, #36] @ 0x24 800f7d2: 881b ldrh r3, [r3, #0] 800f7d4: b29a uxth r2, r3 800f7d6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800f7da: b29b uxth r3, r3 800f7dc: 029b lsls r3, r3, #10 800f7de: b29b uxth r3, r3 800f7e0: 4313 orrs r3, r2 800f7e2: b29b uxth r3, r3 800f7e4: ea6f 4343 mvn.w r3, r3, lsl #17 800f7e8: ea6f 4353 mvn.w r3, r3, lsr #17 800f7ec: b29a uxth r2, r3 800f7ee: 6a7b ldr r3, [r7, #36] @ 0x24 800f7f0: 801a strh r2, [r3, #0] 800f7f2: e018 b.n 800f826 800f7f4: 683b ldr r3, [r7, #0] 800f7f6: 785b ldrb r3, [r3, #1] 800f7f8: 2b01 cmp r3, #1 800f7fa: d114 bne.n 800f826 800f7fc: 687b ldr r3, [r7, #4] 800f7fe: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f802: b29b uxth r3, r3 800f804: 461a mov r2, r3 800f806: 6b3b ldr r3, [r7, #48] @ 0x30 800f808: 4413 add r3, r2 800f80a: 633b str r3, [r7, #48] @ 0x30 800f80c: 683b ldr r3, [r7, #0] 800f80e: 781b ldrb r3, [r3, #0] 800f810: 00da lsls r2, r3, #3 800f812: 6b3b ldr r3, [r7, #48] @ 0x30 800f814: 4413 add r3, r2 800f816: f203 4306 addw r3, r3, #1030 @ 0x406 800f81a: 62fb str r3, [r7, #44] @ 0x2c 800f81c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f820: b29a uxth r2, r3 800f822: 6afb ldr r3, [r7, #44] @ 0x2c 800f824: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 800f826: 683b ldr r3, [r7, #0] 800f828: 895b ldrh r3, [r3, #10] 800f82a: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800f82e: 683b ldr r3, [r7, #0] 800f830: 6959 ldr r1, [r3, #20] 800f832: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f836: b29b uxth r3, r3 800f838: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800f83c: 6878 ldr r0, [r7, #4] 800f83e: f000 fdce bl 80103de ep->xfer_buff += len; 800f842: 683b ldr r3, [r7, #0] 800f844: 695a ldr r2, [r3, #20] 800f846: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f84a: 441a add r2, r3 800f84c: 683b ldr r3, [r7, #0] 800f84e: 615a str r2, [r3, #20] if (ep->xfer_len_db > ep->maxpacket) 800f850: 683b ldr r3, [r7, #0] 800f852: 6a1a ldr r2, [r3, #32] 800f854: 683b ldr r3, [r7, #0] 800f856: 691b ldr r3, [r3, #16] 800f858: 429a cmp r2, r3 800f85a: d907 bls.n 800f86c { ep->xfer_len_db -= len; 800f85c: 683b ldr r3, [r7, #0] 800f85e: 6a1a ldr r2, [r3, #32] 800f860: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f864: 1ad2 subs r2, r2, r3 800f866: 683b ldr r3, [r7, #0] 800f868: 621a str r2, [r3, #32] 800f86a: e006 b.n 800f87a } else { len = ep->xfer_len_db; 800f86c: 683b ldr r3, [r7, #0] 800f86e: 6a1b ldr r3, [r3, #32] 800f870: f8c7 30ac str.w r3, [r7, #172] @ 0xac ep->xfer_len_db = 0U; 800f874: 683b ldr r3, [r7, #0] 800f876: 2200 movs r2, #0 800f878: 621a str r2, [r3, #32] } /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 800f87a: 683b ldr r3, [r7, #0] 800f87c: 785b ldrb r3, [r3, #1] 800f87e: 2b00 cmp r3, #0 800f880: d16b bne.n 800f95a 800f882: 687b ldr r3, [r7, #4] 800f884: 61bb str r3, [r7, #24] 800f886: 687b ldr r3, [r7, #4] 800f888: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f88c: b29b uxth r3, r3 800f88e: 461a mov r2, r3 800f890: 69bb ldr r3, [r7, #24] 800f892: 4413 add r3, r2 800f894: 61bb str r3, [r7, #24] 800f896: 683b ldr r3, [r7, #0] 800f898: 781b ldrb r3, [r3, #0] 800f89a: 00da lsls r2, r3, #3 800f89c: 69bb ldr r3, [r7, #24] 800f89e: 4413 add r3, r2 800f8a0: f203 4302 addw r3, r3, #1026 @ 0x402 800f8a4: 617b str r3, [r7, #20] 800f8a6: 697b ldr r3, [r7, #20] 800f8a8: 881b ldrh r3, [r3, #0] 800f8aa: b29b uxth r3, r3 800f8ac: f3c3 0309 ubfx r3, r3, #0, #10 800f8b0: b29a uxth r2, r3 800f8b2: 697b ldr r3, [r7, #20] 800f8b4: 801a strh r2, [r3, #0] 800f8b6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f8ba: 2b00 cmp r3, #0 800f8bc: d10a bne.n 800f8d4 800f8be: 697b ldr r3, [r7, #20] 800f8c0: 881b ldrh r3, [r3, #0] 800f8c2: b29b uxth r3, r3 800f8c4: ea6f 4343 mvn.w r3, r3, lsl #17 800f8c8: ea6f 4353 mvn.w r3, r3, lsr #17 800f8cc: b29a uxth r2, r3 800f8ce: 697b ldr r3, [r7, #20] 800f8d0: 801a strh r2, [r3, #0] 800f8d2: e05d b.n 800f990 800f8d4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f8d8: 2b3e cmp r3, #62 @ 0x3e 800f8da: d81c bhi.n 800f916 800f8dc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f8e0: 085b lsrs r3, r3, #1 800f8e2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800f8e6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f8ea: f003 0301 and.w r3, r3, #1 800f8ee: 2b00 cmp r3, #0 800f8f0: d004 beq.n 800f8fc 800f8f2: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800f8f6: 3301 adds r3, #1 800f8f8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800f8fc: 697b ldr r3, [r7, #20] 800f8fe: 881b ldrh r3, [r3, #0] 800f900: b29a uxth r2, r3 800f902: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800f906: b29b uxth r3, r3 800f908: 029b lsls r3, r3, #10 800f90a: b29b uxth r3, r3 800f90c: 4313 orrs r3, r2 800f90e: b29a uxth r2, r3 800f910: 697b ldr r3, [r7, #20] 800f912: 801a strh r2, [r3, #0] 800f914: e03c b.n 800f990 800f916: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f91a: 095b lsrs r3, r3, #5 800f91c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800f920: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f924: f003 031f and.w r3, r3, #31 800f928: 2b00 cmp r3, #0 800f92a: d104 bne.n 800f936 800f92c: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800f930: 3b01 subs r3, #1 800f932: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800f936: 697b ldr r3, [r7, #20] 800f938: 881b ldrh r3, [r3, #0] 800f93a: b29a uxth r2, r3 800f93c: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800f940: b29b uxth r3, r3 800f942: 029b lsls r3, r3, #10 800f944: b29b uxth r3, r3 800f946: 4313 orrs r3, r2 800f948: b29b uxth r3, r3 800f94a: ea6f 4343 mvn.w r3, r3, lsl #17 800f94e: ea6f 4353 mvn.w r3, r3, lsr #17 800f952: b29a uxth r2, r3 800f954: 697b ldr r3, [r7, #20] 800f956: 801a strh r2, [r3, #0] 800f958: e01a b.n 800f990 800f95a: 683b ldr r3, [r7, #0] 800f95c: 785b ldrb r3, [r3, #1] 800f95e: 2b01 cmp r3, #1 800f960: d116 bne.n 800f990 800f962: 687b ldr r3, [r7, #4] 800f964: 623b str r3, [r7, #32] 800f966: 687b ldr r3, [r7, #4] 800f968: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f96c: b29b uxth r3, r3 800f96e: 461a mov r2, r3 800f970: 6a3b ldr r3, [r7, #32] 800f972: 4413 add r3, r2 800f974: 623b str r3, [r7, #32] 800f976: 683b ldr r3, [r7, #0] 800f978: 781b ldrb r3, [r3, #0] 800f97a: 00da lsls r2, r3, #3 800f97c: 6a3b ldr r3, [r7, #32] 800f97e: 4413 add r3, r2 800f980: f203 4302 addw r3, r3, #1026 @ 0x402 800f984: 61fb str r3, [r7, #28] 800f986: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f98a: b29a uxth r2, r3 800f98c: 69fb ldr r3, [r7, #28] 800f98e: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 800f990: 683b ldr r3, [r7, #0] 800f992: 891b ldrh r3, [r3, #8] 800f994: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800f998: 683b ldr r3, [r7, #0] 800f99a: 6959 ldr r1, [r3, #20] 800f99c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f9a0: b29b uxth r3, r3 800f9a2: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800f9a6: 6878 ldr r0, [r7, #4] 800f9a8: f000 fd19 bl 80103de 800f9ac: e2e2 b.n 800ff74 } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 800f9ae: 683b ldr r3, [r7, #0] 800f9b0: 785b ldrb r3, [r3, #1] 800f9b2: 2b00 cmp r3, #0 800f9b4: d16b bne.n 800fa8e 800f9b6: 687b ldr r3, [r7, #4] 800f9b8: 64bb str r3, [r7, #72] @ 0x48 800f9ba: 687b ldr r3, [r7, #4] 800f9bc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f9c0: b29b uxth r3, r3 800f9c2: 461a mov r2, r3 800f9c4: 6cbb ldr r3, [r7, #72] @ 0x48 800f9c6: 4413 add r3, r2 800f9c8: 64bb str r3, [r7, #72] @ 0x48 800f9ca: 683b ldr r3, [r7, #0] 800f9cc: 781b ldrb r3, [r3, #0] 800f9ce: 00da lsls r2, r3, #3 800f9d0: 6cbb ldr r3, [r7, #72] @ 0x48 800f9d2: 4413 add r3, r2 800f9d4: f203 4302 addw r3, r3, #1026 @ 0x402 800f9d8: 647b str r3, [r7, #68] @ 0x44 800f9da: 6c7b ldr r3, [r7, #68] @ 0x44 800f9dc: 881b ldrh r3, [r3, #0] 800f9de: b29b uxth r3, r3 800f9e0: f3c3 0309 ubfx r3, r3, #0, #10 800f9e4: b29a uxth r2, r3 800f9e6: 6c7b ldr r3, [r7, #68] @ 0x44 800f9e8: 801a strh r2, [r3, #0] 800f9ea: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800f9ee: 2b00 cmp r3, #0 800f9f0: d10a bne.n 800fa08 800f9f2: 6c7b ldr r3, [r7, #68] @ 0x44 800f9f4: 881b ldrh r3, [r3, #0] 800f9f6: b29b uxth r3, r3 800f9f8: ea6f 4343 mvn.w r3, r3, lsl #17 800f9fc: ea6f 4353 mvn.w r3, r3, lsr #17 800fa00: b29a uxth r2, r3 800fa02: 6c7b ldr r3, [r7, #68] @ 0x44 800fa04: 801a strh r2, [r3, #0] 800fa06: e05d b.n 800fac4 800fa08: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fa0c: 2b3e cmp r3, #62 @ 0x3e 800fa0e: d81c bhi.n 800fa4a 800fa10: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fa14: 085b lsrs r3, r3, #1 800fa16: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800fa1a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fa1e: f003 0301 and.w r3, r3, #1 800fa22: 2b00 cmp r3, #0 800fa24: d004 beq.n 800fa30 800fa26: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800fa2a: 3301 adds r3, #1 800fa2c: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800fa30: 6c7b ldr r3, [r7, #68] @ 0x44 800fa32: 881b ldrh r3, [r3, #0] 800fa34: b29a uxth r2, r3 800fa36: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800fa3a: b29b uxth r3, r3 800fa3c: 029b lsls r3, r3, #10 800fa3e: b29b uxth r3, r3 800fa40: 4313 orrs r3, r2 800fa42: b29a uxth r2, r3 800fa44: 6c7b ldr r3, [r7, #68] @ 0x44 800fa46: 801a strh r2, [r3, #0] 800fa48: e03c b.n 800fac4 800fa4a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fa4e: 095b lsrs r3, r3, #5 800fa50: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800fa54: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fa58: f003 031f and.w r3, r3, #31 800fa5c: 2b00 cmp r3, #0 800fa5e: d104 bne.n 800fa6a 800fa60: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800fa64: 3b01 subs r3, #1 800fa66: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800fa6a: 6c7b ldr r3, [r7, #68] @ 0x44 800fa6c: 881b ldrh r3, [r3, #0] 800fa6e: b29a uxth r2, r3 800fa70: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800fa74: b29b uxth r3, r3 800fa76: 029b lsls r3, r3, #10 800fa78: b29b uxth r3, r3 800fa7a: 4313 orrs r3, r2 800fa7c: b29b uxth r3, r3 800fa7e: ea6f 4343 mvn.w r3, r3, lsl #17 800fa82: ea6f 4353 mvn.w r3, r3, lsr #17 800fa86: b29a uxth r2, r3 800fa88: 6c7b ldr r3, [r7, #68] @ 0x44 800fa8a: 801a strh r2, [r3, #0] 800fa8c: e01a b.n 800fac4 800fa8e: 683b ldr r3, [r7, #0] 800fa90: 785b ldrb r3, [r3, #1] 800fa92: 2b01 cmp r3, #1 800fa94: d116 bne.n 800fac4 800fa96: 687b ldr r3, [r7, #4] 800fa98: 653b str r3, [r7, #80] @ 0x50 800fa9a: 687b ldr r3, [r7, #4] 800fa9c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800faa0: b29b uxth r3, r3 800faa2: 461a mov r2, r3 800faa4: 6d3b ldr r3, [r7, #80] @ 0x50 800faa6: 4413 add r3, r2 800faa8: 653b str r3, [r7, #80] @ 0x50 800faaa: 683b ldr r3, [r7, #0] 800faac: 781b ldrb r3, [r3, #0] 800faae: 00da lsls r2, r3, #3 800fab0: 6d3b ldr r3, [r7, #80] @ 0x50 800fab2: 4413 add r3, r2 800fab4: f203 4302 addw r3, r3, #1026 @ 0x402 800fab8: 64fb str r3, [r7, #76] @ 0x4c 800faba: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fabe: b29a uxth r2, r3 800fac0: 6cfb ldr r3, [r7, #76] @ 0x4c 800fac2: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 800fac4: 683b ldr r3, [r7, #0] 800fac6: 891b ldrh r3, [r3, #8] 800fac8: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800facc: 683b ldr r3, [r7, #0] 800face: 6959 ldr r1, [r3, #20] 800fad0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fad4: b29b uxth r3, r3 800fad6: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800fada: 6878 ldr r0, [r7, #4] 800fadc: f000 fc7f bl 80103de ep->xfer_buff += len; 800fae0: 683b ldr r3, [r7, #0] 800fae2: 695a ldr r2, [r3, #20] 800fae4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fae8: 441a add r2, r3 800faea: 683b ldr r3, [r7, #0] 800faec: 615a str r2, [r3, #20] if (ep->xfer_len_db > ep->maxpacket) 800faee: 683b ldr r3, [r7, #0] 800faf0: 6a1a ldr r2, [r3, #32] 800faf2: 683b ldr r3, [r7, #0] 800faf4: 691b ldr r3, [r3, #16] 800faf6: 429a cmp r2, r3 800faf8: d907 bls.n 800fb0a { ep->xfer_len_db -= len; 800fafa: 683b ldr r3, [r7, #0] 800fafc: 6a1a ldr r2, [r3, #32] 800fafe: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fb02: 1ad2 subs r2, r2, r3 800fb04: 683b ldr r3, [r7, #0] 800fb06: 621a str r2, [r3, #32] 800fb08: e006 b.n 800fb18 } else { len = ep->xfer_len_db; 800fb0a: 683b ldr r3, [r7, #0] 800fb0c: 6a1b ldr r3, [r3, #32] 800fb0e: f8c7 30ac str.w r3, [r7, #172] @ 0xac ep->xfer_len_db = 0U; 800fb12: 683b ldr r3, [r7, #0] 800fb14: 2200 movs r2, #0 800fb16: 621a str r2, [r3, #32] } /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 800fb18: 687b ldr r3, [r7, #4] 800fb1a: 643b str r3, [r7, #64] @ 0x40 800fb1c: 683b ldr r3, [r7, #0] 800fb1e: 785b ldrb r3, [r3, #1] 800fb20: 2b00 cmp r3, #0 800fb22: d16b bne.n 800fbfc 800fb24: 687b ldr r3, [r7, #4] 800fb26: 63bb str r3, [r7, #56] @ 0x38 800fb28: 687b ldr r3, [r7, #4] 800fb2a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800fb2e: b29b uxth r3, r3 800fb30: 461a mov r2, r3 800fb32: 6bbb ldr r3, [r7, #56] @ 0x38 800fb34: 4413 add r3, r2 800fb36: 63bb str r3, [r7, #56] @ 0x38 800fb38: 683b ldr r3, [r7, #0] 800fb3a: 781b ldrb r3, [r3, #0] 800fb3c: 00da lsls r2, r3, #3 800fb3e: 6bbb ldr r3, [r7, #56] @ 0x38 800fb40: 4413 add r3, r2 800fb42: f203 4306 addw r3, r3, #1030 @ 0x406 800fb46: 637b str r3, [r7, #52] @ 0x34 800fb48: 6b7b ldr r3, [r7, #52] @ 0x34 800fb4a: 881b ldrh r3, [r3, #0] 800fb4c: b29b uxth r3, r3 800fb4e: f3c3 0309 ubfx r3, r3, #0, #10 800fb52: b29a uxth r2, r3 800fb54: 6b7b ldr r3, [r7, #52] @ 0x34 800fb56: 801a strh r2, [r3, #0] 800fb58: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fb5c: 2b00 cmp r3, #0 800fb5e: d10a bne.n 800fb76 800fb60: 6b7b ldr r3, [r7, #52] @ 0x34 800fb62: 881b ldrh r3, [r3, #0] 800fb64: b29b uxth r3, r3 800fb66: ea6f 4343 mvn.w r3, r3, lsl #17 800fb6a: ea6f 4353 mvn.w r3, r3, lsr #17 800fb6e: b29a uxth r2, r3 800fb70: 6b7b ldr r3, [r7, #52] @ 0x34 800fb72: 801a strh r2, [r3, #0] 800fb74: e05b b.n 800fc2e 800fb76: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fb7a: 2b3e cmp r3, #62 @ 0x3e 800fb7c: d81c bhi.n 800fbb8 800fb7e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fb82: 085b lsrs r3, r3, #1 800fb84: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800fb88: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fb8c: f003 0301 and.w r3, r3, #1 800fb90: 2b00 cmp r3, #0 800fb92: d004 beq.n 800fb9e 800fb94: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800fb98: 3301 adds r3, #1 800fb9a: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800fb9e: 6b7b ldr r3, [r7, #52] @ 0x34 800fba0: 881b ldrh r3, [r3, #0] 800fba2: b29a uxth r2, r3 800fba4: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800fba8: b29b uxth r3, r3 800fbaa: 029b lsls r3, r3, #10 800fbac: b29b uxth r3, r3 800fbae: 4313 orrs r3, r2 800fbb0: b29a uxth r2, r3 800fbb2: 6b7b ldr r3, [r7, #52] @ 0x34 800fbb4: 801a strh r2, [r3, #0] 800fbb6: e03a b.n 800fc2e 800fbb8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fbbc: 095b lsrs r3, r3, #5 800fbbe: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800fbc2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fbc6: f003 031f and.w r3, r3, #31 800fbca: 2b00 cmp r3, #0 800fbcc: d104 bne.n 800fbd8 800fbce: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800fbd2: 3b01 subs r3, #1 800fbd4: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800fbd8: 6b7b ldr r3, [r7, #52] @ 0x34 800fbda: 881b ldrh r3, [r3, #0] 800fbdc: b29a uxth r2, r3 800fbde: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800fbe2: b29b uxth r3, r3 800fbe4: 029b lsls r3, r3, #10 800fbe6: b29b uxth r3, r3 800fbe8: 4313 orrs r3, r2 800fbea: b29b uxth r3, r3 800fbec: ea6f 4343 mvn.w r3, r3, lsl #17 800fbf0: ea6f 4353 mvn.w r3, r3, lsr #17 800fbf4: b29a uxth r2, r3 800fbf6: 6b7b ldr r3, [r7, #52] @ 0x34 800fbf8: 801a strh r2, [r3, #0] 800fbfa: e018 b.n 800fc2e 800fbfc: 683b ldr r3, [r7, #0] 800fbfe: 785b ldrb r3, [r3, #1] 800fc00: 2b01 cmp r3, #1 800fc02: d114 bne.n 800fc2e 800fc04: 687b ldr r3, [r7, #4] 800fc06: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800fc0a: b29b uxth r3, r3 800fc0c: 461a mov r2, r3 800fc0e: 6c3b ldr r3, [r7, #64] @ 0x40 800fc10: 4413 add r3, r2 800fc12: 643b str r3, [r7, #64] @ 0x40 800fc14: 683b ldr r3, [r7, #0] 800fc16: 781b ldrb r3, [r3, #0] 800fc18: 00da lsls r2, r3, #3 800fc1a: 6c3b ldr r3, [r7, #64] @ 0x40 800fc1c: 4413 add r3, r2 800fc1e: f203 4306 addw r3, r3, #1030 @ 0x406 800fc22: 63fb str r3, [r7, #60] @ 0x3c 800fc24: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fc28: b29a uxth r2, r3 800fc2a: 6bfb ldr r3, [r7, #60] @ 0x3c 800fc2c: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 800fc2e: 683b ldr r3, [r7, #0] 800fc30: 895b ldrh r3, [r3, #10] 800fc32: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800fc36: 683b ldr r3, [r7, #0] 800fc38: 6959 ldr r1, [r3, #20] 800fc3a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fc3e: b29b uxth r3, r3 800fc40: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800fc44: 6878 ldr r0, [r7, #4] 800fc46: f000 fbca bl 80103de 800fc4a: e193 b.n 800ff74 } } /* auto Switch to single buffer mode when transfer xfer_len_db; 800fc4c: 683b ldr r3, [r7, #0] 800fc4e: 6a1b ldr r3, [r3, #32] 800fc50: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* disable double buffer mode for Bulk endpoint */ PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); 800fc54: 687a ldr r2, [r7, #4] 800fc56: 683b ldr r3, [r7, #0] 800fc58: 781b ldrb r3, [r3, #0] 800fc5a: 009b lsls r3, r3, #2 800fc5c: 4413 add r3, r2 800fc5e: 881b ldrh r3, [r3, #0] 800fc60: b29b uxth r3, r3 800fc62: f423 43e2 bic.w r3, r3, #28928 @ 0x7100 800fc66: f023 0370 bic.w r3, r3, #112 @ 0x70 800fc6a: f8a7 3062 strh.w r3, [r7, #98] @ 0x62 800fc6e: 687a ldr r2, [r7, #4] 800fc70: 683b ldr r3, [r7, #0] 800fc72: 781b ldrb r3, [r3, #0] 800fc74: 009b lsls r3, r3, #2 800fc76: 441a add r2, r3 800fc78: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62 800fc7c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fc80: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fc84: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fc88: f043 0380 orr.w r3, r3, #128 @ 0x80 800fc8c: b29b uxth r3, r3 800fc8e: 8013 strh r3, [r2, #0] /* Set Tx count with nbre of byte to be transmitted */ PCD_SET_EP_TX_CNT(USBx, ep->num, len); 800fc90: 687b ldr r3, [r7, #4] 800fc92: 65fb str r3, [r7, #92] @ 0x5c 800fc94: 687b ldr r3, [r7, #4] 800fc96: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800fc9a: b29b uxth r3, r3 800fc9c: 461a mov r2, r3 800fc9e: 6dfb ldr r3, [r7, #92] @ 0x5c 800fca0: 4413 add r3, r2 800fca2: 65fb str r3, [r7, #92] @ 0x5c 800fca4: 683b ldr r3, [r7, #0] 800fca6: 781b ldrb r3, [r3, #0] 800fca8: 00da lsls r2, r3, #3 800fcaa: 6dfb ldr r3, [r7, #92] @ 0x5c 800fcac: 4413 add r3, r2 800fcae: f203 4302 addw r3, r3, #1026 @ 0x402 800fcb2: 65bb str r3, [r7, #88] @ 0x58 800fcb4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fcb8: b29a uxth r2, r3 800fcba: 6dbb ldr r3, [r7, #88] @ 0x58 800fcbc: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 800fcbe: 683b ldr r3, [r7, #0] 800fcc0: 891b ldrh r3, [r3, #8] 800fcc2: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800fcc6: 683b ldr r3, [r7, #0] 800fcc8: 6959 ldr r1, [r3, #20] 800fcca: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fcce: b29b uxth r3, r3 800fcd0: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800fcd4: 6878 ldr r0, [r7, #4] 800fcd6: f000 fb82 bl 80103de 800fcda: e14b b.n 800ff74 } } else /* Manage isochronous double buffer IN mode */ { /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; 800fcdc: 683b ldr r3, [r7, #0] 800fcde: 6a1a ldr r2, [r3, #32] 800fce0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fce4: 1ad2 subs r2, r2, r3 800fce6: 683b ldr r3, [r7, #0] 800fce8: 621a str r2, [r3, #32] /* Fill the data buffer */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) 800fcea: 687a ldr r2, [r7, #4] 800fcec: 683b ldr r3, [r7, #0] 800fcee: 781b ldrb r3, [r3, #0] 800fcf0: 009b lsls r3, r3, #2 800fcf2: 4413 add r3, r2 800fcf4: 881b ldrh r3, [r3, #0] 800fcf6: b29b uxth r3, r3 800fcf8: f003 0340 and.w r3, r3, #64 @ 0x40 800fcfc: 2b00 cmp r3, #0 800fcfe: f000 809a beq.w 800fe36 { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 800fd02: 687b ldr r3, [r7, #4] 800fd04: 673b str r3, [r7, #112] @ 0x70 800fd06: 683b ldr r3, [r7, #0] 800fd08: 785b ldrb r3, [r3, #1] 800fd0a: 2b00 cmp r3, #0 800fd0c: d16b bne.n 800fde6 800fd0e: 687b ldr r3, [r7, #4] 800fd10: 66bb str r3, [r7, #104] @ 0x68 800fd12: 687b ldr r3, [r7, #4] 800fd14: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800fd18: b29b uxth r3, r3 800fd1a: 461a mov r2, r3 800fd1c: 6ebb ldr r3, [r7, #104] @ 0x68 800fd1e: 4413 add r3, r2 800fd20: 66bb str r3, [r7, #104] @ 0x68 800fd22: 683b ldr r3, [r7, #0] 800fd24: 781b ldrb r3, [r3, #0] 800fd26: 00da lsls r2, r3, #3 800fd28: 6ebb ldr r3, [r7, #104] @ 0x68 800fd2a: 4413 add r3, r2 800fd2c: f203 4306 addw r3, r3, #1030 @ 0x406 800fd30: 667b str r3, [r7, #100] @ 0x64 800fd32: 6e7b ldr r3, [r7, #100] @ 0x64 800fd34: 881b ldrh r3, [r3, #0] 800fd36: b29b uxth r3, r3 800fd38: f3c3 0309 ubfx r3, r3, #0, #10 800fd3c: b29a uxth r2, r3 800fd3e: 6e7b ldr r3, [r7, #100] @ 0x64 800fd40: 801a strh r2, [r3, #0] 800fd42: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fd46: 2b00 cmp r3, #0 800fd48: d10a bne.n 800fd60 800fd4a: 6e7b ldr r3, [r7, #100] @ 0x64 800fd4c: 881b ldrh r3, [r3, #0] 800fd4e: b29b uxth r3, r3 800fd50: ea6f 4343 mvn.w r3, r3, lsl #17 800fd54: ea6f 4353 mvn.w r3, r3, lsr #17 800fd58: b29a uxth r2, r3 800fd5a: 6e7b ldr r3, [r7, #100] @ 0x64 800fd5c: 801a strh r2, [r3, #0] 800fd5e: e05b b.n 800fe18 800fd60: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fd64: 2b3e cmp r3, #62 @ 0x3e 800fd66: d81c bhi.n 800fda2 800fd68: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fd6c: 085b lsrs r3, r3, #1 800fd6e: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800fd72: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fd76: f003 0301 and.w r3, r3, #1 800fd7a: 2b00 cmp r3, #0 800fd7c: d004 beq.n 800fd88 800fd7e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800fd82: 3301 adds r3, #1 800fd84: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800fd88: 6e7b ldr r3, [r7, #100] @ 0x64 800fd8a: 881b ldrh r3, [r3, #0] 800fd8c: b29a uxth r2, r3 800fd8e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800fd92: b29b uxth r3, r3 800fd94: 029b lsls r3, r3, #10 800fd96: b29b uxth r3, r3 800fd98: 4313 orrs r3, r2 800fd9a: b29a uxth r2, r3 800fd9c: 6e7b ldr r3, [r7, #100] @ 0x64 800fd9e: 801a strh r2, [r3, #0] 800fda0: e03a b.n 800fe18 800fda2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fda6: 095b lsrs r3, r3, #5 800fda8: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800fdac: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fdb0: f003 031f and.w r3, r3, #31 800fdb4: 2b00 cmp r3, #0 800fdb6: d104 bne.n 800fdc2 800fdb8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800fdbc: 3b01 subs r3, #1 800fdbe: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800fdc2: 6e7b ldr r3, [r7, #100] @ 0x64 800fdc4: 881b ldrh r3, [r3, #0] 800fdc6: b29a uxth r2, r3 800fdc8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800fdcc: b29b uxth r3, r3 800fdce: 029b lsls r3, r3, #10 800fdd0: b29b uxth r3, r3 800fdd2: 4313 orrs r3, r2 800fdd4: b29b uxth r3, r3 800fdd6: ea6f 4343 mvn.w r3, r3, lsl #17 800fdda: ea6f 4353 mvn.w r3, r3, lsr #17 800fdde: b29a uxth r2, r3 800fde0: 6e7b ldr r3, [r7, #100] @ 0x64 800fde2: 801a strh r2, [r3, #0] 800fde4: e018 b.n 800fe18 800fde6: 683b ldr r3, [r7, #0] 800fde8: 785b ldrb r3, [r3, #1] 800fdea: 2b01 cmp r3, #1 800fdec: d114 bne.n 800fe18 800fdee: 687b ldr r3, [r7, #4] 800fdf0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800fdf4: b29b uxth r3, r3 800fdf6: 461a mov r2, r3 800fdf8: 6f3b ldr r3, [r7, #112] @ 0x70 800fdfa: 4413 add r3, r2 800fdfc: 673b str r3, [r7, #112] @ 0x70 800fdfe: 683b ldr r3, [r7, #0] 800fe00: 781b ldrb r3, [r3, #0] 800fe02: 00da lsls r2, r3, #3 800fe04: 6f3b ldr r3, [r7, #112] @ 0x70 800fe06: 4413 add r3, r2 800fe08: f203 4306 addw r3, r3, #1030 @ 0x406 800fe0c: 66fb str r3, [r7, #108] @ 0x6c 800fe0e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fe12: b29a uxth r2, r3 800fe14: 6efb ldr r3, [r7, #108] @ 0x6c 800fe16: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 800fe18: 683b ldr r3, [r7, #0] 800fe1a: 895b ldrh r3, [r3, #10] 800fe1c: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800fe20: 683b ldr r3, [r7, #0] 800fe22: 6959 ldr r1, [r3, #20] 800fe24: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fe28: b29b uxth r3, r3 800fe2a: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800fe2e: 6878 ldr r0, [r7, #4] 800fe30: f000 fad5 bl 80103de 800fe34: e09e b.n 800ff74 } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 800fe36: 683b ldr r3, [r7, #0] 800fe38: 785b ldrb r3, [r3, #1] 800fe3a: 2b00 cmp r3, #0 800fe3c: d16b bne.n 800ff16 800fe3e: 687b ldr r3, [r7, #4] 800fe40: 67fb str r3, [r7, #124] @ 0x7c 800fe42: 687b ldr r3, [r7, #4] 800fe44: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800fe48: b29b uxth r3, r3 800fe4a: 461a mov r2, r3 800fe4c: 6ffb ldr r3, [r7, #124] @ 0x7c 800fe4e: 4413 add r3, r2 800fe50: 67fb str r3, [r7, #124] @ 0x7c 800fe52: 683b ldr r3, [r7, #0] 800fe54: 781b ldrb r3, [r3, #0] 800fe56: 00da lsls r2, r3, #3 800fe58: 6ffb ldr r3, [r7, #124] @ 0x7c 800fe5a: 4413 add r3, r2 800fe5c: f203 4302 addw r3, r3, #1026 @ 0x402 800fe60: 67bb str r3, [r7, #120] @ 0x78 800fe62: 6fbb ldr r3, [r7, #120] @ 0x78 800fe64: 881b ldrh r3, [r3, #0] 800fe66: b29b uxth r3, r3 800fe68: f3c3 0309 ubfx r3, r3, #0, #10 800fe6c: b29a uxth r2, r3 800fe6e: 6fbb ldr r3, [r7, #120] @ 0x78 800fe70: 801a strh r2, [r3, #0] 800fe72: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fe76: 2b00 cmp r3, #0 800fe78: d10a bne.n 800fe90 800fe7a: 6fbb ldr r3, [r7, #120] @ 0x78 800fe7c: 881b ldrh r3, [r3, #0] 800fe7e: b29b uxth r3, r3 800fe80: ea6f 4343 mvn.w r3, r3, lsl #17 800fe84: ea6f 4353 mvn.w r3, r3, lsr #17 800fe88: b29a uxth r2, r3 800fe8a: 6fbb ldr r3, [r7, #120] @ 0x78 800fe8c: 801a strh r2, [r3, #0] 800fe8e: e063 b.n 800ff58 800fe90: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fe94: 2b3e cmp r3, #62 @ 0x3e 800fe96: d81c bhi.n 800fed2 800fe98: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fe9c: 085b lsrs r3, r3, #1 800fe9e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800fea2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fea6: f003 0301 and.w r3, r3, #1 800feaa: 2b00 cmp r3, #0 800feac: d004 beq.n 800feb8 800feae: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 800feb2: 3301 adds r3, #1 800feb4: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800feb8: 6fbb ldr r3, [r7, #120] @ 0x78 800feba: 881b ldrh r3, [r3, #0] 800febc: b29a uxth r2, r3 800febe: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 800fec2: b29b uxth r3, r3 800fec4: 029b lsls r3, r3, #10 800fec6: b29b uxth r3, r3 800fec8: 4313 orrs r3, r2 800feca: b29a uxth r2, r3 800fecc: 6fbb ldr r3, [r7, #120] @ 0x78 800fece: 801a strh r2, [r3, #0] 800fed0: e042 b.n 800ff58 800fed2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fed6: 095b lsrs r3, r3, #5 800fed8: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800fedc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800fee0: f003 031f and.w r3, r3, #31 800fee4: 2b00 cmp r3, #0 800fee6: d104 bne.n 800fef2 800fee8: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 800feec: 3b01 subs r3, #1 800feee: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800fef2: 6fbb ldr r3, [r7, #120] @ 0x78 800fef4: 881b ldrh r3, [r3, #0] 800fef6: b29a uxth r2, r3 800fef8: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 800fefc: b29b uxth r3, r3 800fefe: 029b lsls r3, r3, #10 800ff00: b29b uxth r3, r3 800ff02: 4313 orrs r3, r2 800ff04: b29b uxth r3, r3 800ff06: ea6f 4343 mvn.w r3, r3, lsl #17 800ff0a: ea6f 4353 mvn.w r3, r3, lsr #17 800ff0e: b29a uxth r2, r3 800ff10: 6fbb ldr r3, [r7, #120] @ 0x78 800ff12: 801a strh r2, [r3, #0] 800ff14: e020 b.n 800ff58 800ff16: 683b ldr r3, [r7, #0] 800ff18: 785b ldrb r3, [r3, #1] 800ff1a: 2b01 cmp r3, #1 800ff1c: d11c bne.n 800ff58 800ff1e: 687b ldr r3, [r7, #4] 800ff20: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800ff24: 687b ldr r3, [r7, #4] 800ff26: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ff2a: b29b uxth r3, r3 800ff2c: 461a mov r2, r3 800ff2e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800ff32: 4413 add r3, r2 800ff34: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800ff38: 683b ldr r3, [r7, #0] 800ff3a: 781b ldrb r3, [r3, #0] 800ff3c: 00da lsls r2, r3, #3 800ff3e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800ff42: 4413 add r3, r2 800ff44: f203 4302 addw r3, r3, #1026 @ 0x402 800ff48: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800ff4c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800ff50: b29a uxth r2, r3 800ff52: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800ff56: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 800ff58: 683b ldr r3, [r7, #0] 800ff5a: 891b ldrh r3, [r3, #8] 800ff5c: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 800ff60: 683b ldr r3, [r7, #0] 800ff62: 6959 ldr r1, [r3, #20] 800ff64: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800ff68: b29b uxth r3, r3 800ff6a: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 800ff6e: 6878 ldr r0, [r7, #4] 800ff70: f000 fa35 bl 80103de } } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); 800ff74: 687a ldr r2, [r7, #4] 800ff76: 683b ldr r3, [r7, #0] 800ff78: 781b ldrb r3, [r3, #0] 800ff7a: 009b lsls r3, r3, #2 800ff7c: 4413 add r3, r2 800ff7e: 881b ldrh r3, [r3, #0] 800ff80: b29b uxth r3, r3 800ff82: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ff86: f023 0340 bic.w r3, r3, #64 @ 0x40 800ff8a: 817b strh r3, [r7, #10] 800ff8c: 897b ldrh r3, [r7, #10] 800ff8e: f083 0310 eor.w r3, r3, #16 800ff92: 817b strh r3, [r7, #10] 800ff94: 897b ldrh r3, [r7, #10] 800ff96: f083 0320 eor.w r3, r3, #32 800ff9a: 817b strh r3, [r7, #10] 800ff9c: 687a ldr r2, [r7, #4] 800ff9e: 683b ldr r3, [r7, #0] 800ffa0: 781b ldrb r3, [r3, #0] 800ffa2: 009b lsls r3, r3, #2 800ffa4: 441a add r2, r3 800ffa6: 897b ldrh r3, [r7, #10] 800ffa8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ffac: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ffb0: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ffb4: f043 0380 orr.w r3, r3, #128 @ 0x80 800ffb8: b29b uxth r3, r3 800ffba: 8013 strh r3, [r2, #0] 800ffbc: e0d5 b.n 801016a } else /* OUT endpoint */ { if (ep->doublebuffer == 0U) 800ffbe: 683b ldr r3, [r7, #0] 800ffc0: 7b1b ldrb r3, [r3, #12] 800ffc2: 2b00 cmp r3, #0 800ffc4: d156 bne.n 8010074 { if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) 800ffc6: 683b ldr r3, [r7, #0] 800ffc8: 699b ldr r3, [r3, #24] 800ffca: 2b00 cmp r3, #0 800ffcc: d122 bne.n 8010014 800ffce: 683b ldr r3, [r7, #0] 800ffd0: 78db ldrb r3, [r3, #3] 800ffd2: 2b00 cmp r3, #0 800ffd4: d11e bne.n 8010014 { /* This is a status out stage set the OUT_STATUS */ PCD_SET_OUT_STATUS(USBx, ep->num); 800ffd6: 687a ldr r2, [r7, #4] 800ffd8: 683b ldr r3, [r7, #0] 800ffda: 781b ldrb r3, [r3, #0] 800ffdc: 009b lsls r3, r3, #2 800ffde: 4413 add r3, r2 800ffe0: 881b ldrh r3, [r3, #0] 800ffe2: b29b uxth r3, r3 800ffe4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ffe8: f023 0370 bic.w r3, r3, #112 @ 0x70 800ffec: f8a7 308e strh.w r3, [r7, #142] @ 0x8e 800fff0: 687a ldr r2, [r7, #4] 800fff2: 683b ldr r3, [r7, #0] 800fff4: 781b ldrb r3, [r3, #0] 800fff6: 009b lsls r3, r3, #2 800fff8: 441a add r2, r3 800fffa: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 800fffe: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010002: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010006: f443 4301 orr.w r3, r3, #33024 @ 0x8100 801000a: f043 0380 orr.w r3, r3, #128 @ 0x80 801000e: b29b uxth r3, r3 8010010: 8013 strh r3, [r2, #0] 8010012: e01d b.n 8010050 } else { PCD_CLEAR_OUT_STATUS(USBx, ep->num); 8010014: 687a ldr r2, [r7, #4] 8010016: 683b ldr r3, [r7, #0] 8010018: 781b ldrb r3, [r3, #0] 801001a: 009b lsls r3, r3, #2 801001c: 4413 add r3, r2 801001e: 881b ldrh r3, [r3, #0] 8010020: b29b uxth r3, r3 8010022: f423 43e2 bic.w r3, r3, #28928 @ 0x7100 8010026: f023 0370 bic.w r3, r3, #112 @ 0x70 801002a: f8a7 308c strh.w r3, [r7, #140] @ 0x8c 801002e: 687a ldr r2, [r7, #4] 8010030: 683b ldr r3, [r7, #0] 8010032: 781b ldrb r3, [r3, #0] 8010034: 009b lsls r3, r3, #2 8010036: 441a add r2, r3 8010038: f8b7 308c ldrh.w r3, [r7, #140] @ 0x8c 801003c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010040: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010044: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010048: f043 0380 orr.w r3, r3, #128 @ 0x80 801004c: b29b uxth r3, r3 801004e: 8013 strh r3, [r2, #0] } /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) 8010050: 683b ldr r3, [r7, #0] 8010052: 699a ldr r2, [r3, #24] 8010054: 683b ldr r3, [r7, #0] 8010056: 691b ldr r3, [r3, #16] 8010058: 429a cmp r2, r3 801005a: d907 bls.n 801006c { ep->xfer_len -= ep->maxpacket; 801005c: 683b ldr r3, [r7, #0] 801005e: 699a ldr r2, [r3, #24] 8010060: 683b ldr r3, [r7, #0] 8010062: 691b ldr r3, [r3, #16] 8010064: 1ad2 subs r2, r2, r3 8010066: 683b ldr r3, [r7, #0] 8010068: 619a str r2, [r3, #24] 801006a: e054 b.n 8010116 } else { ep->xfer_len = 0U; 801006c: 683b ldr r3, [r7, #0] 801006e: 2200 movs r2, #0 8010070: 619a str r2, [r3, #24] 8010072: e050 b.n 8010116 #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) 8010074: 683b ldr r3, [r7, #0] 8010076: 78db ldrb r3, [r3, #3] 8010078: 2b02 cmp r3, #2 801007a: d142 bne.n 8010102 { /* Coming from ISR */ if (ep->xfer_count != 0U) 801007c: 683b ldr r3, [r7, #0] 801007e: 69db ldr r3, [r3, #28] 8010080: 2b00 cmp r3, #0 8010082: d048 beq.n 8010116 { /* Update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); 8010084: 687a ldr r2, [r7, #4] 8010086: 683b ldr r3, [r7, #0] 8010088: 781b ldrb r3, [r3, #0] 801008a: 009b lsls r3, r3, #2 801008c: 4413 add r3, r2 801008e: 881b ldrh r3, [r3, #0] 8010090: f8a7 3092 strh.w r3, [r7, #146] @ 0x92 /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || 8010094: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 8010098: f403 4380 and.w r3, r3, #16384 @ 0x4000 801009c: 2b00 cmp r3, #0 801009e: d005 beq.n 80100ac 80100a0: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 80100a4: f003 0340 and.w r3, r3, #64 @ 0x40 80100a8: 2b00 cmp r3, #0 80100aa: d10b bne.n 80100c4 (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) 80100ac: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 80100b0: f403 4380 and.w r3, r3, #16384 @ 0x4000 if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || 80100b4: 2b00 cmp r3, #0 80100b6: d12e bne.n 8010116 (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) 80100b8: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 80100bc: f003 0340 and.w r3, r3, #64 @ 0x40 80100c0: 2b00 cmp r3, #0 80100c2: d128 bne.n 8010116 { PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); 80100c4: 687a ldr r2, [r7, #4] 80100c6: 683b ldr r3, [r7, #0] 80100c8: 781b ldrb r3, [r3, #0] 80100ca: 009b lsls r3, r3, #2 80100cc: 4413 add r3, r2 80100ce: 881b ldrh r3, [r3, #0] 80100d0: b29b uxth r3, r3 80100d2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80100d6: f023 0370 bic.w r3, r3, #112 @ 0x70 80100da: f8a7 3090 strh.w r3, [r7, #144] @ 0x90 80100de: 687a ldr r2, [r7, #4] 80100e0: 683b ldr r3, [r7, #0] 80100e2: 781b ldrb r3, [r3, #0] 80100e4: 009b lsls r3, r3, #2 80100e6: 441a add r2, r3 80100e8: f8b7 3090 ldrh.w r3, [r7, #144] @ 0x90 80100ec: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80100f0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80100f4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80100f8: f043 03c0 orr.w r3, r3, #192 @ 0xc0 80100fc: b29b uxth r3, r3 80100fe: 8013 strh r3, [r2, #0] 8010100: e009 b.n 8010116 } } } /* iso out double */ else if (ep->type == EP_TYPE_ISOC) 8010102: 683b ldr r3, [r7, #0] 8010104: 78db ldrb r3, [r3, #3] 8010106: 2b01 cmp r3, #1 8010108: d103 bne.n 8010112 { /* Only single packet transfer supported in FS */ ep->xfer_len = 0U; 801010a: 683b ldr r3, [r7, #0] 801010c: 2200 movs r2, #0 801010e: 619a str r2, [r3, #24] 8010110: e001 b.n 8010116 } else { return HAL_ERROR; 8010112: 2301 movs r3, #1 8010114: e02a b.n 801016c } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 8010116: 687a ldr r2, [r7, #4] 8010118: 683b ldr r3, [r7, #0] 801011a: 781b ldrb r3, [r3, #0] 801011c: 009b lsls r3, r3, #2 801011e: 4413 add r3, r2 8010120: 881b ldrh r3, [r3, #0] 8010122: b29b uxth r3, r3 8010124: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010128: f023 0370 bic.w r3, r3, #112 @ 0x70 801012c: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 8010130: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8010134: f483 5380 eor.w r3, r3, #4096 @ 0x1000 8010138: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 801013c: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8010140: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8010144: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 8010148: 687a ldr r2, [r7, #4] 801014a: 683b ldr r3, [r7, #0] 801014c: 781b ldrb r3, [r3, #0] 801014e: 009b lsls r3, r3, #2 8010150: 441a add r2, r3 8010152: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8010156: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 801015a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 801015e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010162: f043 0380 orr.w r3, r3, #128 @ 0x80 8010166: b29b uxth r3, r3 8010168: 8013 strh r3, [r2, #0] } return HAL_OK; 801016a: 2300 movs r3, #0 } 801016c: 4618 mov r0, r3 801016e: 37b0 adds r7, #176 @ 0xb0 8010170: 46bd mov sp, r7 8010172: bd80 pop {r7, pc} 08010174 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 8010174: b480 push {r7} 8010176: b085 sub sp, #20 8010178: af00 add r7, sp, #0 801017a: 6078 str r0, [r7, #4] 801017c: 6039 str r1, [r7, #0] if (ep->is_in != 0U) 801017e: 683b ldr r3, [r7, #0] 8010180: 785b ldrb r3, [r3, #1] 8010182: 2b00 cmp r3, #0 8010184: d020 beq.n 80101c8 { PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); 8010186: 687a ldr r2, [r7, #4] 8010188: 683b ldr r3, [r7, #0] 801018a: 781b ldrb r3, [r3, #0] 801018c: 009b lsls r3, r3, #2 801018e: 4413 add r3, r2 8010190: 881b ldrh r3, [r3, #0] 8010192: b29b uxth r3, r3 8010194: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010198: f023 0340 bic.w r3, r3, #64 @ 0x40 801019c: 81bb strh r3, [r7, #12] 801019e: 89bb ldrh r3, [r7, #12] 80101a0: f083 0310 eor.w r3, r3, #16 80101a4: 81bb strh r3, [r7, #12] 80101a6: 687a ldr r2, [r7, #4] 80101a8: 683b ldr r3, [r7, #0] 80101aa: 781b ldrb r3, [r3, #0] 80101ac: 009b lsls r3, r3, #2 80101ae: 441a add r2, r3 80101b0: 89bb ldrh r3, [r7, #12] 80101b2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80101b6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80101ba: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80101be: f043 0380 orr.w r3, r3, #128 @ 0x80 80101c2: b29b uxth r3, r3 80101c4: 8013 strh r3, [r2, #0] 80101c6: e01f b.n 8010208 } else { PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); 80101c8: 687a ldr r2, [r7, #4] 80101ca: 683b ldr r3, [r7, #0] 80101cc: 781b ldrb r3, [r3, #0] 80101ce: 009b lsls r3, r3, #2 80101d0: 4413 add r3, r2 80101d2: 881b ldrh r3, [r3, #0] 80101d4: b29b uxth r3, r3 80101d6: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80101da: f023 0370 bic.w r3, r3, #112 @ 0x70 80101de: 81fb strh r3, [r7, #14] 80101e0: 89fb ldrh r3, [r7, #14] 80101e2: f483 5380 eor.w r3, r3, #4096 @ 0x1000 80101e6: 81fb strh r3, [r7, #14] 80101e8: 687a ldr r2, [r7, #4] 80101ea: 683b ldr r3, [r7, #0] 80101ec: 781b ldrb r3, [r3, #0] 80101ee: 009b lsls r3, r3, #2 80101f0: 441a add r2, r3 80101f2: 89fb ldrh r3, [r7, #14] 80101f4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80101f8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80101fc: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010200: f043 0380 orr.w r3, r3, #128 @ 0x80 8010204: b29b uxth r3, r3 8010206: 8013 strh r3, [r2, #0] } return HAL_OK; 8010208: 2300 movs r3, #0 } 801020a: 4618 mov r0, r3 801020c: 3714 adds r7, #20 801020e: 46bd mov sp, r7 8010210: f85d 7b04 ldr.w r7, [sp], #4 8010214: 4770 bx lr 08010216 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 8010216: b480 push {r7} 8010218: b087 sub sp, #28 801021a: af00 add r7, sp, #0 801021c: 6078 str r0, [r7, #4] 801021e: 6039 str r1, [r7, #0] if (ep->is_in != 0U) 8010220: 683b ldr r3, [r7, #0] 8010222: 785b ldrb r3, [r3, #1] 8010224: 2b00 cmp r3, #0 8010226: d04c beq.n 80102c2 { PCD_CLEAR_TX_DTOG(USBx, ep->num); 8010228: 687a ldr r2, [r7, #4] 801022a: 683b ldr r3, [r7, #0] 801022c: 781b ldrb r3, [r3, #0] 801022e: 009b lsls r3, r3, #2 8010230: 4413 add r3, r2 8010232: 881b ldrh r3, [r3, #0] 8010234: 823b strh r3, [r7, #16] 8010236: 8a3b ldrh r3, [r7, #16] 8010238: f003 0340 and.w r3, r3, #64 @ 0x40 801023c: 2b00 cmp r3, #0 801023e: d01b beq.n 8010278 8010240: 687a ldr r2, [r7, #4] 8010242: 683b ldr r3, [r7, #0] 8010244: 781b ldrb r3, [r3, #0] 8010246: 009b lsls r3, r3, #2 8010248: 4413 add r3, r2 801024a: 881b ldrh r3, [r3, #0] 801024c: b29b uxth r3, r3 801024e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010252: f023 0370 bic.w r3, r3, #112 @ 0x70 8010256: 81fb strh r3, [r7, #14] 8010258: 687a ldr r2, [r7, #4] 801025a: 683b ldr r3, [r7, #0] 801025c: 781b ldrb r3, [r3, #0] 801025e: 009b lsls r3, r3, #2 8010260: 441a add r2, r3 8010262: 89fb ldrh r3, [r7, #14] 8010264: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010268: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 801026c: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010270: f043 03c0 orr.w r3, r3, #192 @ 0xc0 8010274: b29b uxth r3, r3 8010276: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8010278: 683b ldr r3, [r7, #0] 801027a: 78db ldrb r3, [r3, #3] 801027c: 2b01 cmp r3, #1 801027e: d06c beq.n 801035a { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 8010280: 687a ldr r2, [r7, #4] 8010282: 683b ldr r3, [r7, #0] 8010284: 781b ldrb r3, [r3, #0] 8010286: 009b lsls r3, r3, #2 8010288: 4413 add r3, r2 801028a: 881b ldrh r3, [r3, #0] 801028c: b29b uxth r3, r3 801028e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010292: f023 0340 bic.w r3, r3, #64 @ 0x40 8010296: 81bb strh r3, [r7, #12] 8010298: 89bb ldrh r3, [r7, #12] 801029a: f083 0320 eor.w r3, r3, #32 801029e: 81bb strh r3, [r7, #12] 80102a0: 687a ldr r2, [r7, #4] 80102a2: 683b ldr r3, [r7, #0] 80102a4: 781b ldrb r3, [r3, #0] 80102a6: 009b lsls r3, r3, #2 80102a8: 441a add r2, r3 80102aa: 89bb ldrh r3, [r7, #12] 80102ac: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80102b0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80102b4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80102b8: f043 0380 orr.w r3, r3, #128 @ 0x80 80102bc: b29b uxth r3, r3 80102be: 8013 strh r3, [r2, #0] 80102c0: e04b b.n 801035a } } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); 80102c2: 687a ldr r2, [r7, #4] 80102c4: 683b ldr r3, [r7, #0] 80102c6: 781b ldrb r3, [r3, #0] 80102c8: 009b lsls r3, r3, #2 80102ca: 4413 add r3, r2 80102cc: 881b ldrh r3, [r3, #0] 80102ce: 82fb strh r3, [r7, #22] 80102d0: 8afb ldrh r3, [r7, #22] 80102d2: f403 4380 and.w r3, r3, #16384 @ 0x4000 80102d6: 2b00 cmp r3, #0 80102d8: d01b beq.n 8010312 80102da: 687a ldr r2, [r7, #4] 80102dc: 683b ldr r3, [r7, #0] 80102de: 781b ldrb r3, [r3, #0] 80102e0: 009b lsls r3, r3, #2 80102e2: 4413 add r3, r2 80102e4: 881b ldrh r3, [r3, #0] 80102e6: b29b uxth r3, r3 80102e8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80102ec: f023 0370 bic.w r3, r3, #112 @ 0x70 80102f0: 82bb strh r3, [r7, #20] 80102f2: 687a ldr r2, [r7, #4] 80102f4: 683b ldr r3, [r7, #0] 80102f6: 781b ldrb r3, [r3, #0] 80102f8: 009b lsls r3, r3, #2 80102fa: 441a add r2, r3 80102fc: 8abb ldrh r3, [r7, #20] 80102fe: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010302: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010306: f443 4340 orr.w r3, r3, #49152 @ 0xc000 801030a: f043 0380 orr.w r3, r3, #128 @ 0x80 801030e: b29b uxth r3, r3 8010310: 8013 strh r3, [r2, #0] /* Configure VALID status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 8010312: 687a ldr r2, [r7, #4] 8010314: 683b ldr r3, [r7, #0] 8010316: 781b ldrb r3, [r3, #0] 8010318: 009b lsls r3, r3, #2 801031a: 4413 add r3, r2 801031c: 881b ldrh r3, [r3, #0] 801031e: b29b uxth r3, r3 8010320: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010324: f023 0370 bic.w r3, r3, #112 @ 0x70 8010328: 827b strh r3, [r7, #18] 801032a: 8a7b ldrh r3, [r7, #18] 801032c: f483 5380 eor.w r3, r3, #4096 @ 0x1000 8010330: 827b strh r3, [r7, #18] 8010332: 8a7b ldrh r3, [r7, #18] 8010334: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8010338: 827b strh r3, [r7, #18] 801033a: 687a ldr r2, [r7, #4] 801033c: 683b ldr r3, [r7, #0] 801033e: 781b ldrb r3, [r3, #0] 8010340: 009b lsls r3, r3, #2 8010342: 441a add r2, r3 8010344: 8a7b ldrh r3, [r7, #18] 8010346: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 801034a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 801034e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010352: f043 0380 orr.w r3, r3, #128 @ 0x80 8010356: b29b uxth r3, r3 8010358: 8013 strh r3, [r2, #0] } return HAL_OK; 801035a: 2300 movs r3, #0 } 801035c: 4618 mov r0, r3 801035e: 371c adds r7, #28 8010360: 46bd mov sp, r7 8010362: f85d 7b04 ldr.w r7, [sp], #4 8010366: 4770 bx lr 08010368 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) { 8010368: b480 push {r7} 801036a: b083 sub sp, #12 801036c: af00 add r7, sp, #0 801036e: 6078 str r0, [r7, #4] 8010370: 460b mov r3, r1 8010372: 70fb strb r3, [r7, #3] if (address == 0U) 8010374: 78fb ldrb r3, [r7, #3] 8010376: 2b00 cmp r3, #0 8010378: d103 bne.n 8010382 { /* set device address and enable function */ USBx->DADDR = (uint16_t)USB_DADDR_EF; 801037a: 687b ldr r3, [r7, #4] 801037c: 2280 movs r2, #128 @ 0x80 801037e: f8a3 204c strh.w r2, [r3, #76] @ 0x4c } return HAL_OK; 8010382: 2300 movs r3, #0 } 8010384: 4618 mov r0, r3 8010386: 370c adds r7, #12 8010388: 46bd mov sp, r7 801038a: f85d 7b04 ldr.w r7, [sp], #4 801038e: 4770 bx lr 08010390 : * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { 8010390: b480 push {r7} 8010392: b083 sub sp, #12 8010394: af00 add r7, sp, #0 8010396: 6078 str r0, [r7, #4] /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ USBx->BCDR |= (uint16_t)USB_BCDR_DPPU; 8010398: 687b ldr r3, [r7, #4] 801039a: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58 801039e: b29b uxth r3, r3 80103a0: ea6f 4343 mvn.w r3, r3, lsl #17 80103a4: ea6f 4353 mvn.w r3, r3, lsr #17 80103a8: b29a uxth r2, r3 80103aa: 687b ldr r3, [r7, #4] 80103ac: f8a3 2058 strh.w r2, [r3, #88] @ 0x58 return HAL_OK; 80103b0: 2300 movs r3, #0 } 80103b2: 4618 mov r0, r3 80103b4: 370c adds r7, #12 80103b6: 46bd mov sp, r7 80103b8: f85d 7b04 ldr.w r7, [sp], #4 80103bc: 4770 bx lr 080103be : * @brief USB_ReadInterrupts return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) { 80103be: b480 push {r7} 80103c0: b085 sub sp, #20 80103c2: af00 add r7, sp, #0 80103c4: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->ISTR; 80103c6: 687b ldr r3, [r7, #4] 80103c8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80103cc: b29b uxth r3, r3 80103ce: 60fb str r3, [r7, #12] return tmpreg; 80103d0: 68fb ldr r3, [r7, #12] } 80103d2: 4618 mov r0, r3 80103d4: 3714 adds r7, #20 80103d6: 46bd mov sp, r7 80103d8: f85d 7b04 ldr.w r7, [sp], #4 80103dc: 4770 bx lr 080103de : * @param wPMABufAddr address into PMA. * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { 80103de: b480 push {r7} 80103e0: b08b sub sp, #44 @ 0x2c 80103e2: af00 add r7, sp, #0 80103e4: 60f8 str r0, [r7, #12] 80103e6: 60b9 str r1, [r7, #8] 80103e8: 4611 mov r1, r2 80103ea: 461a mov r2, r3 80103ec: 460b mov r3, r1 80103ee: 80fb strh r3, [r7, #6] 80103f0: 4613 mov r3, r2 80103f2: 80bb strh r3, [r7, #4] uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; 80103f4: 88bb ldrh r3, [r7, #4] 80103f6: 3301 adds r3, #1 80103f8: 085b lsrs r3, r3, #1 80103fa: 61bb str r3, [r7, #24] uint32_t BaseAddr = (uint32_t)USBx; 80103fc: 68fb ldr r3, [r7, #12] 80103fe: 617b str r3, [r7, #20] uint32_t count; uint16_t WrVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; 8010400: 68bb ldr r3, [r7, #8] 8010402: 61fb str r3, [r7, #28] pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); 8010404: 88fa ldrh r2, [r7, #6] 8010406: 697b ldr r3, [r7, #20] 8010408: 4413 add r3, r2 801040a: f503 6380 add.w r3, r3, #1024 @ 0x400 801040e: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) 8010410: 69bb ldr r3, [r7, #24] 8010412: 627b str r3, [r7, #36] @ 0x24 8010414: e01c b.n 8010450 { WrVal = pBuf[0]; 8010416: 69fb ldr r3, [r7, #28] 8010418: 781b ldrb r3, [r3, #0] 801041a: 827b strh r3, [r7, #18] WrVal |= (uint16_t)pBuf[1] << 8; 801041c: 69fb ldr r3, [r7, #28] 801041e: 3301 adds r3, #1 8010420: 781b ldrb r3, [r3, #0] 8010422: b21b sxth r3, r3 8010424: 021b lsls r3, r3, #8 8010426: b21a sxth r2, r3 8010428: f9b7 3012 ldrsh.w r3, [r7, #18] 801042c: 4313 orrs r3, r2 801042e: b21b sxth r3, r3 8010430: 827b strh r3, [r7, #18] *pdwVal = (WrVal & 0xFFFFU); 8010432: 6a3b ldr r3, [r7, #32] 8010434: 8a7a ldrh r2, [r7, #18] 8010436: 801a strh r2, [r3, #0] pdwVal++; 8010438: 6a3b ldr r3, [r7, #32] 801043a: 3302 adds r3, #2 801043c: 623b str r3, [r7, #32] #if PMA_ACCESS > 1U pdwVal++; #endif /* PMA_ACCESS */ pBuf++; 801043e: 69fb ldr r3, [r7, #28] 8010440: 3301 adds r3, #1 8010442: 61fb str r3, [r7, #28] pBuf++; 8010444: 69fb ldr r3, [r7, #28] 8010446: 3301 adds r3, #1 8010448: 61fb str r3, [r7, #28] for (count = n; count != 0U; count--) 801044a: 6a7b ldr r3, [r7, #36] @ 0x24 801044c: 3b01 subs r3, #1 801044e: 627b str r3, [r7, #36] @ 0x24 8010450: 6a7b ldr r3, [r7, #36] @ 0x24 8010452: 2b00 cmp r3, #0 8010454: d1df bne.n 8010416 } } 8010456: bf00 nop 8010458: bf00 nop 801045a: 372c adds r7, #44 @ 0x2c 801045c: 46bd mov sp, r7 801045e: f85d 7b04 ldr.w r7, [sp], #4 8010462: 4770 bx lr 08010464 : * @param wPMABufAddr address into PMA. * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { 8010464: b480 push {r7} 8010466: b08b sub sp, #44 @ 0x2c 8010468: af00 add r7, sp, #0 801046a: 60f8 str r0, [r7, #12] 801046c: 60b9 str r1, [r7, #8] 801046e: 4611 mov r1, r2 8010470: 461a mov r2, r3 8010472: 460b mov r3, r1 8010474: 80fb strh r3, [r7, #6] 8010476: 4613 mov r3, r2 8010478: 80bb strh r3, [r7, #4] uint32_t n = (uint32_t)wNBytes >> 1; 801047a: 88bb ldrh r3, [r7, #4] 801047c: 085b lsrs r3, r3, #1 801047e: b29b uxth r3, r3 8010480: 61bb str r3, [r7, #24] uint32_t BaseAddr = (uint32_t)USBx; 8010482: 68fb ldr r3, [r7, #12] 8010484: 617b str r3, [r7, #20] uint32_t count; uint32_t RdVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; 8010486: 68bb ldr r3, [r7, #8] 8010488: 61fb str r3, [r7, #28] pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); 801048a: 88fa ldrh r2, [r7, #6] 801048c: 697b ldr r3, [r7, #20] 801048e: 4413 add r3, r2 8010490: f503 6380 add.w r3, r3, #1024 @ 0x400 8010494: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) 8010496: 69bb ldr r3, [r7, #24] 8010498: 627b str r3, [r7, #36] @ 0x24 801049a: e018 b.n 80104ce { RdVal = *(__IO uint16_t *)pdwVal; 801049c: 6a3b ldr r3, [r7, #32] 801049e: 881b ldrh r3, [r3, #0] 80104a0: b29b uxth r3, r3 80104a2: 613b str r3, [r7, #16] pdwVal++; 80104a4: 6a3b ldr r3, [r7, #32] 80104a6: 3302 adds r3, #2 80104a8: 623b str r3, [r7, #32] *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); 80104aa: 693b ldr r3, [r7, #16] 80104ac: b2da uxtb r2, r3 80104ae: 69fb ldr r3, [r7, #28] 80104b0: 701a strb r2, [r3, #0] pBuf++; 80104b2: 69fb ldr r3, [r7, #28] 80104b4: 3301 adds r3, #1 80104b6: 61fb str r3, [r7, #28] *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU); 80104b8: 693b ldr r3, [r7, #16] 80104ba: 0a1b lsrs r3, r3, #8 80104bc: b2da uxtb r2, r3 80104be: 69fb ldr r3, [r7, #28] 80104c0: 701a strb r2, [r3, #0] pBuf++; 80104c2: 69fb ldr r3, [r7, #28] 80104c4: 3301 adds r3, #1 80104c6: 61fb str r3, [r7, #28] for (count = n; count != 0U; count--) 80104c8: 6a7b ldr r3, [r7, #36] @ 0x24 80104ca: 3b01 subs r3, #1 80104cc: 627b str r3, [r7, #36] @ 0x24 80104ce: 6a7b ldr r3, [r7, #36] @ 0x24 80104d0: 2b00 cmp r3, #0 80104d2: d1e3 bne.n 801049c #if PMA_ACCESS > 1U pdwVal++; #endif /* PMA_ACCESS */ } if ((wNBytes % 2U) != 0U) 80104d4: 88bb ldrh r3, [r7, #4] 80104d6: f003 0301 and.w r3, r3, #1 80104da: b29b uxth r3, r3 80104dc: 2b00 cmp r3, #0 80104de: d007 beq.n 80104f0 { RdVal = *pdwVal; 80104e0: 6a3b ldr r3, [r7, #32] 80104e2: 881b ldrh r3, [r3, #0] 80104e4: b29b uxth r3, r3 80104e6: 613b str r3, [r7, #16] *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); 80104e8: 693b ldr r3, [r7, #16] 80104ea: b2da uxtb r2, r3 80104ec: 69fb ldr r3, [r7, #28] 80104ee: 701a strb r2, [r3, #0] } } 80104f0: bf00 nop 80104f2: 372c adds r7, #44 @ 0x2c 80104f4: 46bd mov sp, r7 80104f6: f85d 7b04 ldr.w r7, [sp], #4 80104fa: 4770 bx lr 080104fc : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80104fc: b580 push {r7, lr} 80104fe: b084 sub sp, #16 8010500: af00 add r7, sp, #0 8010502: 6078 str r0, [r7, #4] 8010504: 460b mov r3, r1 8010506: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_CDC_HandleTypeDef *hcdc; hcdc = (USBD_CDC_HandleTypeDef *)USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); 8010508: f44f 7007 mov.w r0, #540 @ 0x21c 801050c: f008 f9e2 bl 80188d4 8010510: 60f8 str r0, [r7, #12] if (hcdc == NULL) 8010512: 68fb ldr r3, [r7, #12] 8010514: 2b00 cmp r3, #0 8010516: d109 bne.n 801052c { pdev->pClassDataCmsit[pdev->classId] = NULL; 8010518: 687b ldr r3, [r7, #4] 801051a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 801051e: 687b ldr r3, [r7, #4] 8010520: 32b0 adds r2, #176 @ 0xb0 8010522: 2100 movs r1, #0 8010524: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 8010528: 2302 movs r3, #2 801052a: e0d4 b.n 80106d6 } (void)USBD_memset(hcdc, 0, sizeof(USBD_CDC_HandleTypeDef)); 801052c: f44f 7207 mov.w r2, #540 @ 0x21c 8010530: 2100 movs r1, #0 8010532: 68f8 ldr r0, [r7, #12] 8010534: f009 faee bl 8019b14 pdev->pClassDataCmsit[pdev->classId] = (void *)hcdc; 8010538: 687b ldr r3, [r7, #4] 801053a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 801053e: 687b ldr r3, [r7, #4] 8010540: 32b0 adds r2, #176 @ 0xb0 8010542: 68f9 ldr r1, [r7, #12] 8010544: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 8010548: 687b ldr r3, [r7, #4] 801054a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 801054e: 687b ldr r3, [r7, #4] 8010550: 32b0 adds r2, #176 @ 0xb0 8010552: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8010556: 687b ldr r3, [r7, #4] 8010558: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 801055c: 687b ldr r3, [r7, #4] 801055e: 7c1b ldrb r3, [r3, #16] 8010560: 2b00 cmp r3, #0 8010562: d138 bne.n 80105d6 { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK, 8010564: 4b5e ldr r3, [pc, #376] @ (80106e0 ) 8010566: 7819 ldrb r1, [r3, #0] 8010568: f44f 7300 mov.w r3, #512 @ 0x200 801056c: 2202 movs r2, #2 801056e: 6878 ldr r0, [r7, #4] 8010570: f008 f857 bl 8018622 CDC_DATA_HS_IN_PACKET_SIZE); pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U; 8010574: 4b5a ldr r3, [pc, #360] @ (80106e0 ) 8010576: 781b ldrb r3, [r3, #0] 8010578: f003 020f and.w r2, r3, #15 801057c: 6879 ldr r1, [r7, #4] 801057e: 4613 mov r3, r2 8010580: 009b lsls r3, r3, #2 8010582: 4413 add r3, r2 8010584: 009b lsls r3, r3, #2 8010586: 440b add r3, r1 8010588: 3323 adds r3, #35 @ 0x23 801058a: 2201 movs r2, #1 801058c: 701a strb r2, [r3, #0] /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK, 801058e: 4b55 ldr r3, [pc, #340] @ (80106e4 ) 8010590: 7819 ldrb r1, [r3, #0] 8010592: f44f 7300 mov.w r3, #512 @ 0x200 8010596: 2202 movs r2, #2 8010598: 6878 ldr r0, [r7, #4] 801059a: f008 f842 bl 8018622 CDC_DATA_HS_OUT_PACKET_SIZE); pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U; 801059e: 4b51 ldr r3, [pc, #324] @ (80106e4 ) 80105a0: 781b ldrb r3, [r3, #0] 80105a2: f003 020f and.w r2, r3, #15 80105a6: 6879 ldr r1, [r7, #4] 80105a8: 4613 mov r3, r2 80105aa: 009b lsls r3, r3, #2 80105ac: 4413 add r3, r2 80105ae: 009b lsls r3, r3, #2 80105b0: 440b add r3, r1 80105b2: f203 1363 addw r3, r3, #355 @ 0x163 80105b6: 2201 movs r2, #1 80105b8: 701a strb r2, [r3, #0] /* Set bInterval for CDC CMD Endpoint */ pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_HS_BINTERVAL; 80105ba: 4b4b ldr r3, [pc, #300] @ (80106e8 ) 80105bc: 781b ldrb r3, [r3, #0] 80105be: f003 020f and.w r2, r3, #15 80105c2: 6879 ldr r1, [r7, #4] 80105c4: 4613 mov r3, r2 80105c6: 009b lsls r3, r3, #2 80105c8: 4413 add r3, r2 80105ca: 009b lsls r3, r3, #2 80105cc: 440b add r3, r1 80105ce: 331c adds r3, #28 80105d0: 2210 movs r2, #16 80105d2: 601a str r2, [r3, #0] 80105d4: e035 b.n 8010642 } else { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK, 80105d6: 4b42 ldr r3, [pc, #264] @ (80106e0 ) 80105d8: 7819 ldrb r1, [r3, #0] 80105da: 2340 movs r3, #64 @ 0x40 80105dc: 2202 movs r2, #2 80105de: 6878 ldr r0, [r7, #4] 80105e0: f008 f81f bl 8018622 CDC_DATA_FS_IN_PACKET_SIZE); pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U; 80105e4: 4b3e ldr r3, [pc, #248] @ (80106e0 ) 80105e6: 781b ldrb r3, [r3, #0] 80105e8: f003 020f and.w r2, r3, #15 80105ec: 6879 ldr r1, [r7, #4] 80105ee: 4613 mov r3, r2 80105f0: 009b lsls r3, r3, #2 80105f2: 4413 add r3, r2 80105f4: 009b lsls r3, r3, #2 80105f6: 440b add r3, r1 80105f8: 3323 adds r3, #35 @ 0x23 80105fa: 2201 movs r2, #1 80105fc: 701a strb r2, [r3, #0] /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK, 80105fe: 4b39 ldr r3, [pc, #228] @ (80106e4 ) 8010600: 7819 ldrb r1, [r3, #0] 8010602: 2340 movs r3, #64 @ 0x40 8010604: 2202 movs r2, #2 8010606: 6878 ldr r0, [r7, #4] 8010608: f008 f80b bl 8018622 CDC_DATA_FS_OUT_PACKET_SIZE); pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U; 801060c: 4b35 ldr r3, [pc, #212] @ (80106e4 ) 801060e: 781b ldrb r3, [r3, #0] 8010610: f003 020f and.w r2, r3, #15 8010614: 6879 ldr r1, [r7, #4] 8010616: 4613 mov r3, r2 8010618: 009b lsls r3, r3, #2 801061a: 4413 add r3, r2 801061c: 009b lsls r3, r3, #2 801061e: 440b add r3, r1 8010620: f203 1363 addw r3, r3, #355 @ 0x163 8010624: 2201 movs r2, #1 8010626: 701a strb r2, [r3, #0] /* Set bInterval for CMD Endpoint */ pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_FS_BINTERVAL; 8010628: 4b2f ldr r3, [pc, #188] @ (80106e8 ) 801062a: 781b ldrb r3, [r3, #0] 801062c: f003 020f and.w r2, r3, #15 8010630: 6879 ldr r1, [r7, #4] 8010632: 4613 mov r3, r2 8010634: 009b lsls r3, r3, #2 8010636: 4413 add r3, r2 8010638: 009b lsls r3, r3, #2 801063a: 440b add r3, r1 801063c: 331c adds r3, #28 801063e: 2210 movs r2, #16 8010640: 601a str r2, [r3, #0] } /* Open Command IN EP */ (void)USBD_LL_OpenEP(pdev, CDCCmdEpAdd, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); 8010642: 4b29 ldr r3, [pc, #164] @ (80106e8 ) 8010644: 7819 ldrb r1, [r3, #0] 8010646: 2308 movs r3, #8 8010648: 2203 movs r2, #3 801064a: 6878 ldr r0, [r7, #4] 801064c: f007 ffe9 bl 8018622 pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 1U; 8010650: 4b25 ldr r3, [pc, #148] @ (80106e8 ) 8010652: 781b ldrb r3, [r3, #0] 8010654: f003 020f and.w r2, r3, #15 8010658: 6879 ldr r1, [r7, #4] 801065a: 4613 mov r3, r2 801065c: 009b lsls r3, r3, #2 801065e: 4413 add r3, r2 8010660: 009b lsls r3, r3, #2 8010662: 440b add r3, r1 8010664: 3323 adds r3, #35 @ 0x23 8010666: 2201 movs r2, #1 8010668: 701a strb r2, [r3, #0] hcdc->RxBuffer = NULL; 801066a: 68fb ldr r3, [r7, #12] 801066c: 2200 movs r2, #0 801066e: f8c3 2204 str.w r2, [r3, #516] @ 0x204 /* Init physical Interface components */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Init(); 8010672: 687b ldr r3, [r7, #4] 8010674: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8010678: 687a ldr r2, [r7, #4] 801067a: 33b0 adds r3, #176 @ 0xb0 801067c: 009b lsls r3, r3, #2 801067e: 4413 add r3, r2 8010680: 685b ldr r3, [r3, #4] 8010682: 681b ldr r3, [r3, #0] 8010684: 4798 blx r3 /* Init Xfer states */ hcdc->TxState = 0U; 8010686: 68fb ldr r3, [r7, #12] 8010688: 2200 movs r2, #0 801068a: f8c3 2214 str.w r2, [r3, #532] @ 0x214 hcdc->RxState = 0U; 801068e: 68fb ldr r3, [r7, #12] 8010690: 2200 movs r2, #0 8010692: f8c3 2218 str.w r2, [r3, #536] @ 0x218 if (hcdc->RxBuffer == NULL) 8010696: 68fb ldr r3, [r7, #12] 8010698: f8d3 3204 ldr.w r3, [r3, #516] @ 0x204 801069c: 2b00 cmp r3, #0 801069e: d101 bne.n 80106a4 { return (uint8_t)USBD_EMEM; 80106a0: 2302 movs r3, #2 80106a2: e018 b.n 80106d6 } if (pdev->dev_speed == USBD_SPEED_HIGH) 80106a4: 687b ldr r3, [r7, #4] 80106a6: 7c1b ldrb r3, [r3, #16] 80106a8: 2b00 cmp r3, #0 80106aa: d10a bne.n 80106c2 { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, 80106ac: 4b0d ldr r3, [pc, #52] @ (80106e4 ) 80106ae: 7819 ldrb r1, [r3, #0] 80106b0: 68fb ldr r3, [r7, #12] 80106b2: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 80106b6: f44f 7300 mov.w r3, #512 @ 0x200 80106ba: 6878 ldr r0, [r7, #4] 80106bc: f008 f8a0 bl 8018800 80106c0: e008 b.n 80106d4 CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, 80106c2: 4b08 ldr r3, [pc, #32] @ (80106e4 ) 80106c4: 7819 ldrb r1, [r3, #0] 80106c6: 68fb ldr r3, [r7, #12] 80106c8: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 80106cc: 2340 movs r3, #64 @ 0x40 80106ce: 6878 ldr r0, [r7, #4] 80106d0: f008 f896 bl 8018800 CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 80106d4: 2300 movs r3, #0 } 80106d6: 4618 mov r0, r3 80106d8: 3710 adds r7, #16 80106da: 46bd mov sp, r7 80106dc: bd80 pop {r7, pc} 80106de: bf00 nop 80106e0: 2000009f .word 0x2000009f 80106e4: 200000a0 .word 0x200000a0 80106e8: 200000a1 .word 0x200000a1 080106ec : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80106ec: b580 push {r7, lr} 80106ee: b082 sub sp, #8 80106f0: af00 add r7, sp, #0 80106f2: 6078 str r0, [r7, #4] 80106f4: 460b mov r3, r1 80106f6: 70fb strb r3, [r7, #3] CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close EP IN */ (void)USBD_LL_CloseEP(pdev, CDCInEpAdd); 80106f8: 4b3a ldr r3, [pc, #232] @ (80107e4 ) 80106fa: 781b ldrb r3, [r3, #0] 80106fc: 4619 mov r1, r3 80106fe: 6878 ldr r0, [r7, #4] 8010700: f007 ffb5 bl 801866e pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 0U; 8010704: 4b37 ldr r3, [pc, #220] @ (80107e4 ) 8010706: 781b ldrb r3, [r3, #0] 8010708: f003 020f and.w r2, r3, #15 801070c: 6879 ldr r1, [r7, #4] 801070e: 4613 mov r3, r2 8010710: 009b lsls r3, r3, #2 8010712: 4413 add r3, r2 8010714: 009b lsls r3, r3, #2 8010716: 440b add r3, r1 8010718: 3323 adds r3, #35 @ 0x23 801071a: 2200 movs r2, #0 801071c: 701a strb r2, [r3, #0] /* Close EP OUT */ (void)USBD_LL_CloseEP(pdev, CDCOutEpAdd); 801071e: 4b32 ldr r3, [pc, #200] @ (80107e8 ) 8010720: 781b ldrb r3, [r3, #0] 8010722: 4619 mov r1, r3 8010724: 6878 ldr r0, [r7, #4] 8010726: f007 ffa2 bl 801866e pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 0U; 801072a: 4b2f ldr r3, [pc, #188] @ (80107e8 ) 801072c: 781b ldrb r3, [r3, #0] 801072e: f003 020f and.w r2, r3, #15 8010732: 6879 ldr r1, [r7, #4] 8010734: 4613 mov r3, r2 8010736: 009b lsls r3, r3, #2 8010738: 4413 add r3, r2 801073a: 009b lsls r3, r3, #2 801073c: 440b add r3, r1 801073e: f203 1363 addw r3, r3, #355 @ 0x163 8010742: 2200 movs r2, #0 8010744: 701a strb r2, [r3, #0] /* Close Command IN EP */ (void)USBD_LL_CloseEP(pdev, CDCCmdEpAdd); 8010746: 4b29 ldr r3, [pc, #164] @ (80107ec ) 8010748: 781b ldrb r3, [r3, #0] 801074a: 4619 mov r1, r3 801074c: 6878 ldr r0, [r7, #4] 801074e: f007 ff8e bl 801866e pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 0U; 8010752: 4b26 ldr r3, [pc, #152] @ (80107ec ) 8010754: 781b ldrb r3, [r3, #0] 8010756: f003 020f and.w r2, r3, #15 801075a: 6879 ldr r1, [r7, #4] 801075c: 4613 mov r3, r2 801075e: 009b lsls r3, r3, #2 8010760: 4413 add r3, r2 8010762: 009b lsls r3, r3, #2 8010764: 440b add r3, r1 8010766: 3323 adds r3, #35 @ 0x23 8010768: 2200 movs r2, #0 801076a: 701a strb r2, [r3, #0] pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = 0U; 801076c: 4b1f ldr r3, [pc, #124] @ (80107ec ) 801076e: 781b ldrb r3, [r3, #0] 8010770: f003 020f and.w r2, r3, #15 8010774: 6879 ldr r1, [r7, #4] 8010776: 4613 mov r3, r2 8010778: 009b lsls r3, r3, #2 801077a: 4413 add r3, r2 801077c: 009b lsls r3, r3, #2 801077e: 440b add r3, r1 8010780: 331c adds r3, #28 8010782: 2200 movs r2, #0 8010784: 601a str r2, [r3, #0] /* DeInit physical Interface components */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 8010786: 687b ldr r3, [r7, #4] 8010788: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 801078c: 687b ldr r3, [r7, #4] 801078e: 32b0 adds r2, #176 @ 0xb0 8010790: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010794: 2b00 cmp r3, #0 8010796: d01f beq.n 80107d8 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->DeInit(); 8010798: 687b ldr r3, [r7, #4] 801079a: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 801079e: 687a ldr r2, [r7, #4] 80107a0: 33b0 adds r3, #176 @ 0xb0 80107a2: 009b lsls r3, r3, #2 80107a4: 4413 add r3, r2 80107a6: 685b ldr r3, [r3, #4] 80107a8: 685b ldr r3, [r3, #4] 80107aa: 4798 blx r3 (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 80107ac: 687b ldr r3, [r7, #4] 80107ae: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80107b2: 687b ldr r3, [r7, #4] 80107b4: 32b0 adds r2, #176 @ 0xb0 80107b6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80107ba: 4618 mov r0, r3 80107bc: f008 f898 bl 80188f0 pdev->pClassDataCmsit[pdev->classId] = NULL; 80107c0: 687b ldr r3, [r7, #4] 80107c2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80107c6: 687b ldr r3, [r7, #4] 80107c8: 32b0 adds r2, #176 @ 0xb0 80107ca: 2100 movs r1, #0 80107cc: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = NULL; 80107d0: 687b ldr r3, [r7, #4] 80107d2: 2200 movs r2, #0 80107d4: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc } return (uint8_t)USBD_OK; 80107d8: 2300 movs r3, #0 } 80107da: 4618 mov r0, r3 80107dc: 3708 adds r7, #8 80107de: 46bd mov sp, r7 80107e0: bd80 pop {r7, pc} 80107e2: bf00 nop 80107e4: 2000009f .word 0x2000009f 80107e8: 200000a0 .word 0x200000a0 80107ec: 200000a1 .word 0x200000a1 080107f0 : * @param req: usb requests * @retval status */ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80107f0: b580 push {r7, lr} 80107f2: b086 sub sp, #24 80107f4: af00 add r7, sp, #0 80107f6: 6078 str r0, [r7, #4] 80107f8: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80107fa: 687b ldr r3, [r7, #4] 80107fc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010800: 687b ldr r3, [r7, #4] 8010802: 32b0 adds r2, #176 @ 0xb0 8010804: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010808: 613b str r3, [r7, #16] uint16_t len; uint8_t ifalt = 0U; 801080a: 2300 movs r3, #0 801080c: 737b strb r3, [r7, #13] uint16_t status_info = 0U; 801080e: 2300 movs r3, #0 8010810: 817b strh r3, [r7, #10] USBD_StatusTypeDef ret = USBD_OK; 8010812: 2300 movs r3, #0 8010814: 75fb strb r3, [r7, #23] if (hcdc == NULL) 8010816: 693b ldr r3, [r7, #16] 8010818: 2b00 cmp r3, #0 801081a: d101 bne.n 8010820 { return (uint8_t)USBD_FAIL; 801081c: 2303 movs r3, #3 801081e: e0bf b.n 80109a0 } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8010820: 683b ldr r3, [r7, #0] 8010822: 781b ldrb r3, [r3, #0] 8010824: f003 0360 and.w r3, r3, #96 @ 0x60 8010828: 2b00 cmp r3, #0 801082a: d050 beq.n 80108ce 801082c: 2b20 cmp r3, #32 801082e: f040 80af bne.w 8010990 { case USB_REQ_TYPE_CLASS: if (req->wLength != 0U) 8010832: 683b ldr r3, [r7, #0] 8010834: 88db ldrh r3, [r3, #6] 8010836: 2b00 cmp r3, #0 8010838: d03a beq.n 80108b0 { if ((req->bmRequest & 0x80U) != 0U) 801083a: 683b ldr r3, [r7, #0] 801083c: 781b ldrb r3, [r3, #0] 801083e: b25b sxtb r3, r3 8010840: 2b00 cmp r3, #0 8010842: da1b bge.n 801087c { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, 8010844: 687b ldr r3, [r7, #4] 8010846: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 801084a: 687a ldr r2, [r7, #4] 801084c: 33b0 adds r3, #176 @ 0xb0 801084e: 009b lsls r3, r3, #2 8010850: 4413 add r3, r2 8010852: 685b ldr r3, [r3, #4] 8010854: 689b ldr r3, [r3, #8] 8010856: 683a ldr r2, [r7, #0] 8010858: 7850 ldrb r0, [r2, #1] (uint8_t *)hcdc->data, 801085a: 6939 ldr r1, [r7, #16] ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, 801085c: 683a ldr r2, [r7, #0] 801085e: 88d2 ldrh r2, [r2, #6] 8010860: 4798 blx r3 req->wLength); len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength); 8010862: 683b ldr r3, [r7, #0] 8010864: 88db ldrh r3, [r3, #6] 8010866: 2b07 cmp r3, #7 8010868: bf28 it cs 801086a: 2307 movcs r3, #7 801086c: 81fb strh r3, [r7, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len); 801086e: 693b ldr r3, [r7, #16] 8010870: 89fa ldrh r2, [r7, #14] 8010872: 4619 mov r1, r3 8010874: 6878 ldr r0, [r7, #4] 8010876: f001 fd41 bl 80122fc else { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, (uint8_t *)req, 0U); } break; 801087a: e090 b.n 801099e hcdc->CmdOpCode = req->bRequest; 801087c: 683b ldr r3, [r7, #0] 801087e: 785a ldrb r2, [r3, #1] 8010880: 693b ldr r3, [r7, #16] 8010882: f883 2200 strb.w r2, [r3, #512] @ 0x200 hcdc->CmdLength = (uint8_t)MIN(req->wLength, USB_MAX_EP0_SIZE); 8010886: 683b ldr r3, [r7, #0] 8010888: 88db ldrh r3, [r3, #6] 801088a: 2b3f cmp r3, #63 @ 0x3f 801088c: d803 bhi.n 8010896 801088e: 683b ldr r3, [r7, #0] 8010890: 88db ldrh r3, [r3, #6] 8010892: b2da uxtb r2, r3 8010894: e000 b.n 8010898 8010896: 2240 movs r2, #64 @ 0x40 8010898: 693b ldr r3, [r7, #16] 801089a: f883 2201 strb.w r2, [r3, #513] @ 0x201 (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, hcdc->CmdLength); 801089e: 6939 ldr r1, [r7, #16] 80108a0: 693b ldr r3, [r7, #16] 80108a2: f893 3201 ldrb.w r3, [r3, #513] @ 0x201 80108a6: 461a mov r2, r3 80108a8: 6878 ldr r0, [r7, #4] 80108aa: f001 fd56 bl 801235a break; 80108ae: e076 b.n 801099e ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, 80108b0: 687b ldr r3, [r7, #4] 80108b2: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 80108b6: 687a ldr r2, [r7, #4] 80108b8: 33b0 adds r3, #176 @ 0xb0 80108ba: 009b lsls r3, r3, #2 80108bc: 4413 add r3, r2 80108be: 685b ldr r3, [r3, #4] 80108c0: 689b ldr r3, [r3, #8] 80108c2: 683a ldr r2, [r7, #0] 80108c4: 7850 ldrb r0, [r2, #1] 80108c6: 2200 movs r2, #0 80108c8: 6839 ldr r1, [r7, #0] 80108ca: 4798 blx r3 break; 80108cc: e067 b.n 801099e case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80108ce: 683b ldr r3, [r7, #0] 80108d0: 785b ldrb r3, [r3, #1] 80108d2: 2b0b cmp r3, #11 80108d4: d851 bhi.n 801097a 80108d6: a201 add r2, pc, #4 @ (adr r2, 80108dc ) 80108d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80108dc: 0801090d .word 0x0801090d 80108e0: 08010989 .word 0x08010989 80108e4: 0801097b .word 0x0801097b 80108e8: 0801097b .word 0x0801097b 80108ec: 0801097b .word 0x0801097b 80108f0: 0801097b .word 0x0801097b 80108f4: 0801097b .word 0x0801097b 80108f8: 0801097b .word 0x0801097b 80108fc: 0801097b .word 0x0801097b 8010900: 0801097b .word 0x0801097b 8010904: 08010937 .word 0x08010937 8010908: 08010961 .word 0x08010961 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 801090c: 687b ldr r3, [r7, #4] 801090e: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8010912: b2db uxtb r3, r3 8010914: 2b03 cmp r3, #3 8010916: d107 bne.n 8010928 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8010918: f107 030a add.w r3, r7, #10 801091c: 2202 movs r2, #2 801091e: 4619 mov r1, r3 8010920: 6878 ldr r0, [r7, #4] 8010922: f001 fceb bl 80122fc else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8010926: e032 b.n 801098e USBD_CtlError(pdev, req); 8010928: 6839 ldr r1, [r7, #0] 801092a: 6878 ldr r0, [r7, #4] 801092c: f001 fc69 bl 8012202 ret = USBD_FAIL; 8010930: 2303 movs r3, #3 8010932: 75fb strb r3, [r7, #23] break; 8010934: e02b b.n 801098e case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8010936: 687b ldr r3, [r7, #4] 8010938: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 801093c: b2db uxtb r3, r3 801093e: 2b03 cmp r3, #3 8010940: d107 bne.n 8010952 { (void)USBD_CtlSendData(pdev, &ifalt, 1U); 8010942: f107 030d add.w r3, r7, #13 8010946: 2201 movs r2, #1 8010948: 4619 mov r1, r3 801094a: 6878 ldr r0, [r7, #4] 801094c: f001 fcd6 bl 80122fc else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8010950: e01d b.n 801098e USBD_CtlError(pdev, req); 8010952: 6839 ldr r1, [r7, #0] 8010954: 6878 ldr r0, [r7, #4] 8010956: f001 fc54 bl 8012202 ret = USBD_FAIL; 801095a: 2303 movs r3, #3 801095c: 75fb strb r3, [r7, #23] break; 801095e: e016 b.n 801098e case USB_REQ_SET_INTERFACE: if (pdev->dev_state != USBD_STATE_CONFIGURED) 8010960: 687b ldr r3, [r7, #4] 8010962: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8010966: b2db uxtb r3, r3 8010968: 2b03 cmp r3, #3 801096a: d00f beq.n 801098c { USBD_CtlError(pdev, req); 801096c: 6839 ldr r1, [r7, #0] 801096e: 6878 ldr r0, [r7, #4] 8010970: f001 fc47 bl 8012202 ret = USBD_FAIL; 8010974: 2303 movs r3, #3 8010976: 75fb strb r3, [r7, #23] } break; 8010978: e008 b.n 801098c case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 801097a: 6839 ldr r1, [r7, #0] 801097c: 6878 ldr r0, [r7, #4] 801097e: f001 fc40 bl 8012202 ret = USBD_FAIL; 8010982: 2303 movs r3, #3 8010984: 75fb strb r3, [r7, #23] break; 8010986: e002 b.n 801098e break; 8010988: bf00 nop 801098a: e008 b.n 801099e break; 801098c: bf00 nop } break; 801098e: e006 b.n 801099e default: USBD_CtlError(pdev, req); 8010990: 6839 ldr r1, [r7, #0] 8010992: 6878 ldr r0, [r7, #4] 8010994: f001 fc35 bl 8012202 ret = USBD_FAIL; 8010998: 2303 movs r3, #3 801099a: 75fb strb r3, [r7, #23] break; 801099c: bf00 nop } return (uint8_t)ret; 801099e: 7dfb ldrb r3, [r7, #23] } 80109a0: 4618 mov r0, r3 80109a2: 3718 adds r7, #24 80109a4: 46bd mov sp, r7 80109a6: bd80 pop {r7, pc} 080109a8 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 80109a8: b580 push {r7, lr} 80109aa: b084 sub sp, #16 80109ac: af00 add r7, sp, #0 80109ae: 6078 str r0, [r7, #4] 80109b0: 460b mov r3, r1 80109b2: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc; PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef *)pdev->pData; 80109b4: 687b ldr r3, [r7, #4] 80109b6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 80109ba: 60fb str r3, [r7, #12] if (pdev->pClassDataCmsit[pdev->classId] == NULL) 80109bc: 687b ldr r3, [r7, #4] 80109be: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80109c2: 687b ldr r3, [r7, #4] 80109c4: 32b0 adds r2, #176 @ 0xb0 80109c6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80109ca: 2b00 cmp r3, #0 80109cc: d101 bne.n 80109d2 { return (uint8_t)USBD_FAIL; 80109ce: 2303 movs r3, #3 80109d0: e065 b.n 8010a9e } hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80109d2: 687b ldr r3, [r7, #4] 80109d4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80109d8: 687b ldr r3, [r7, #4] 80109da: 32b0 adds r2, #176 @ 0xb0 80109dc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80109e0: 60bb str r3, [r7, #8] if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) && 80109e2: 78fb ldrb r3, [r7, #3] 80109e4: f003 020f and.w r2, r3, #15 80109e8: 6879 ldr r1, [r7, #4] 80109ea: 4613 mov r3, r2 80109ec: 009b lsls r3, r3, #2 80109ee: 4413 add r3, r2 80109f0: 009b lsls r3, r3, #2 80109f2: 440b add r3, r1 80109f4: 3314 adds r3, #20 80109f6: 681b ldr r3, [r3, #0] 80109f8: 2b00 cmp r3, #0 80109fa: d02f beq.n 8010a5c ((pdev->ep_in[epnum & 0xFU].total_length % hpcd->IN_ep[epnum & 0xFU].maxpacket) == 0U)) 80109fc: 78fb ldrb r3, [r7, #3] 80109fe: f003 020f and.w r2, r3, #15 8010a02: 6879 ldr r1, [r7, #4] 8010a04: 4613 mov r3, r2 8010a06: 009b lsls r3, r3, #2 8010a08: 4413 add r3, r2 8010a0a: 009b lsls r3, r3, #2 8010a0c: 440b add r3, r1 8010a0e: 3314 adds r3, #20 8010a10: 681a ldr r2, [r3, #0] 8010a12: 78fb ldrb r3, [r7, #3] 8010a14: f003 010f and.w r1, r3, #15 8010a18: 68f8 ldr r0, [r7, #12] 8010a1a: 460b mov r3, r1 8010a1c: 009b lsls r3, r3, #2 8010a1e: 440b add r3, r1 8010a20: 00db lsls r3, r3, #3 8010a22: 4403 add r3, r0 8010a24: 3320 adds r3, #32 8010a26: 681b ldr r3, [r3, #0] 8010a28: fbb2 f1f3 udiv r1, r2, r3 8010a2c: fb01 f303 mul.w r3, r1, r3 8010a30: 1ad3 subs r3, r2, r3 if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) && 8010a32: 2b00 cmp r3, #0 8010a34: d112 bne.n 8010a5c { /* Update the packet total length */ pdev->ep_in[epnum & 0xFU].total_length = 0U; 8010a36: 78fb ldrb r3, [r7, #3] 8010a38: f003 020f and.w r2, r3, #15 8010a3c: 6879 ldr r1, [r7, #4] 8010a3e: 4613 mov r3, r2 8010a40: 009b lsls r3, r3, #2 8010a42: 4413 add r3, r2 8010a44: 009b lsls r3, r3, #2 8010a46: 440b add r3, r1 8010a48: 3314 adds r3, #20 8010a4a: 2200 movs r2, #0 8010a4c: 601a str r2, [r3, #0] /* Send ZLP */ (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); 8010a4e: 78f9 ldrb r1, [r7, #3] 8010a50: 2300 movs r3, #0 8010a52: 2200 movs r2, #0 8010a54: 6878 ldr r0, [r7, #4] 8010a56: f007 feb2 bl 80187be 8010a5a: e01f b.n 8010a9c } else { hcdc->TxState = 0U; 8010a5c: 68bb ldr r3, [r7, #8] 8010a5e: 2200 movs r2, #0 8010a60: f8c3 2214 str.w r2, [r3, #532] @ 0x214 if (((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt != NULL) 8010a64: 687b ldr r3, [r7, #4] 8010a66: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8010a6a: 687a ldr r2, [r7, #4] 8010a6c: 33b0 adds r3, #176 @ 0xb0 8010a6e: 009b lsls r3, r3, #2 8010a70: 4413 add r3, r2 8010a72: 685b ldr r3, [r3, #4] 8010a74: 691b ldr r3, [r3, #16] 8010a76: 2b00 cmp r3, #0 8010a78: d010 beq.n 8010a9c { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); 8010a7a: 687b ldr r3, [r7, #4] 8010a7c: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8010a80: 687a ldr r2, [r7, #4] 8010a82: 33b0 adds r3, #176 @ 0xb0 8010a84: 009b lsls r3, r3, #2 8010a86: 4413 add r3, r2 8010a88: 685b ldr r3, [r3, #4] 8010a8a: 691b ldr r3, [r3, #16] 8010a8c: 68ba ldr r2, [r7, #8] 8010a8e: f8d2 0208 ldr.w r0, [r2, #520] @ 0x208 8010a92: 68ba ldr r2, [r7, #8] 8010a94: f502 7104 add.w r1, r2, #528 @ 0x210 8010a98: 78fa ldrb r2, [r7, #3] 8010a9a: 4798 blx r3 } } return (uint8_t)USBD_OK; 8010a9c: 2300 movs r3, #0 } 8010a9e: 4618 mov r0, r3 8010aa0: 3710 adds r7, #16 8010aa2: 46bd mov sp, r7 8010aa4: bd80 pop {r7, pc} 08010aa6 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8010aa6: b580 push {r7, lr} 8010aa8: b084 sub sp, #16 8010aaa: af00 add r7, sp, #0 8010aac: 6078 str r0, [r7, #4] 8010aae: 460b mov r3, r1 8010ab0: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8010ab2: 687b ldr r3, [r7, #4] 8010ab4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010ab8: 687b ldr r3, [r7, #4] 8010aba: 32b0 adds r2, #176 @ 0xb0 8010abc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010ac0: 60fb str r3, [r7, #12] if (pdev->pClassDataCmsit[pdev->classId] == NULL) 8010ac2: 687b ldr r3, [r7, #4] 8010ac4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010ac8: 687b ldr r3, [r7, #4] 8010aca: 32b0 adds r2, #176 @ 0xb0 8010acc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010ad0: 2b00 cmp r3, #0 8010ad2: d101 bne.n 8010ad8 { return (uint8_t)USBD_FAIL; 8010ad4: 2303 movs r3, #3 8010ad6: e01a b.n 8010b0e } /* Get the received data length */ hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); 8010ad8: 78fb ldrb r3, [r7, #3] 8010ada: 4619 mov r1, r3 8010adc: 6878 ldr r0, [r7, #4] 8010ade: f007 feb0 bl 8018842 8010ae2: 4602 mov r2, r0 8010ae4: 68fb ldr r3, [r7, #12] 8010ae6: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Receive(hcdc->RxBuffer, &hcdc->RxLength); 8010aea: 687b ldr r3, [r7, #4] 8010aec: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8010af0: 687a ldr r2, [r7, #4] 8010af2: 33b0 adds r3, #176 @ 0xb0 8010af4: 009b lsls r3, r3, #2 8010af6: 4413 add r3, r2 8010af8: 685b ldr r3, [r3, #4] 8010afa: 68db ldr r3, [r3, #12] 8010afc: 68fa ldr r2, [r7, #12] 8010afe: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204 8010b02: 68fa ldr r2, [r7, #12] 8010b04: f502 7203 add.w r2, r2, #524 @ 0x20c 8010b08: 4611 mov r1, r2 8010b0a: 4798 blx r3 return (uint8_t)USBD_OK; 8010b0c: 2300 movs r3, #0 } 8010b0e: 4618 mov r0, r3 8010b10: 3710 adds r7, #16 8010b12: 46bd mov sp, r7 8010b14: bd80 pop {r7, pc} 08010b16 : * Handle EP0 Rx Ready event * @param pdev: device instance * @retval status */ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) { 8010b16: b580 push {r7, lr} 8010b18: b084 sub sp, #16 8010b1a: af00 add r7, sp, #0 8010b1c: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8010b1e: 687b ldr r3, [r7, #4] 8010b20: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010b24: 687b ldr r3, [r7, #4] 8010b26: 32b0 adds r2, #176 @ 0xb0 8010b28: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010b2c: 60fb str r3, [r7, #12] if (hcdc == NULL) 8010b2e: 68fb ldr r3, [r7, #12] 8010b30: 2b00 cmp r3, #0 8010b32: d101 bne.n 8010b38 { return (uint8_t)USBD_FAIL; 8010b34: 2303 movs r3, #3 8010b36: e024 b.n 8010b82 } if ((pdev->pUserData[pdev->classId] != NULL) && (hcdc->CmdOpCode != 0xFFU)) 8010b38: 687b ldr r3, [r7, #4] 8010b3a: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8010b3e: 687a ldr r2, [r7, #4] 8010b40: 33b0 adds r3, #176 @ 0xb0 8010b42: 009b lsls r3, r3, #2 8010b44: 4413 add r3, r2 8010b46: 685b ldr r3, [r3, #4] 8010b48: 2b00 cmp r3, #0 8010b4a: d019 beq.n 8010b80 8010b4c: 68fb ldr r3, [r7, #12] 8010b4e: f893 3200 ldrb.w r3, [r3, #512] @ 0x200 8010b52: 2bff cmp r3, #255 @ 0xff 8010b54: d014 beq.n 8010b80 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode, 8010b56: 687b ldr r3, [r7, #4] 8010b58: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8010b5c: 687a ldr r2, [r7, #4] 8010b5e: 33b0 adds r3, #176 @ 0xb0 8010b60: 009b lsls r3, r3, #2 8010b62: 4413 add r3, r2 8010b64: 685b ldr r3, [r3, #4] 8010b66: 689b ldr r3, [r3, #8] 8010b68: 68fa ldr r2, [r7, #12] 8010b6a: f892 0200 ldrb.w r0, [r2, #512] @ 0x200 (uint8_t *)hcdc->data, 8010b6e: 68f9 ldr r1, [r7, #12] (uint16_t)hcdc->CmdLength); 8010b70: 68fa ldr r2, [r7, #12] 8010b72: f892 2201 ldrb.w r2, [r2, #513] @ 0x201 ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode, 8010b76: 4798 blx r3 hcdc->CmdOpCode = 0xFFU; 8010b78: 68fb ldr r3, [r7, #12] 8010b7a: 22ff movs r2, #255 @ 0xff 8010b7c: f883 2200 strb.w r2, [r3, #512] @ 0x200 } return (uint8_t)USBD_OK; 8010b80: 2300 movs r3, #0 } 8010b82: 4618 mov r0, r3 8010b84: 3710 adds r7, #16 8010b86: 46bd mov sp, r7 8010b88: bd80 pop {r7, pc} ... 08010b8c : * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) { 8010b8c: b580 push {r7, lr} 8010b8e: b086 sub sp, #24 8010b90: af00 add r7, sp, #0 8010b92: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); 8010b94: 2182 movs r1, #130 @ 0x82 8010b96: 4818 ldr r0, [pc, #96] @ (8010bf8 ) 8010b98: f000 fcd0 bl 801153c 8010b9c: 6178 str r0, [r7, #20] USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); 8010b9e: 2101 movs r1, #1 8010ba0: 4815 ldr r0, [pc, #84] @ (8010bf8 ) 8010ba2: f000 fccb bl 801153c 8010ba6: 6138 str r0, [r7, #16] USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); 8010ba8: 2181 movs r1, #129 @ 0x81 8010baa: 4813 ldr r0, [pc, #76] @ (8010bf8 ) 8010bac: f000 fcc6 bl 801153c 8010bb0: 60f8 str r0, [r7, #12] if (pEpCmdDesc != NULL) 8010bb2: 697b ldr r3, [r7, #20] 8010bb4: 2b00 cmp r3, #0 8010bb6: d002 beq.n 8010bbe { pEpCmdDesc->bInterval = CDC_FS_BINTERVAL; 8010bb8: 697b ldr r3, [r7, #20] 8010bba: 2210 movs r2, #16 8010bbc: 719a strb r2, [r3, #6] } if (pEpOutDesc != NULL) 8010bbe: 693b ldr r3, [r7, #16] 8010bc0: 2b00 cmp r3, #0 8010bc2: d006 beq.n 8010bd2 { pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; 8010bc4: 693b ldr r3, [r7, #16] 8010bc6: 2200 movs r2, #0 8010bc8: f042 0240 orr.w r2, r2, #64 @ 0x40 8010bcc: 711a strb r2, [r3, #4] 8010bce: 2200 movs r2, #0 8010bd0: 715a strb r2, [r3, #5] } if (pEpInDesc != NULL) 8010bd2: 68fb ldr r3, [r7, #12] 8010bd4: 2b00 cmp r3, #0 8010bd6: d006 beq.n 8010be6 { pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; 8010bd8: 68fb ldr r3, [r7, #12] 8010bda: 2200 movs r2, #0 8010bdc: f042 0240 orr.w r2, r2, #64 @ 0x40 8010be0: 711a strb r2, [r3, #4] 8010be2: 2200 movs r2, #0 8010be4: 715a strb r2, [r3, #5] } *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); 8010be6: 687b ldr r3, [r7, #4] 8010be8: 2243 movs r2, #67 @ 0x43 8010bea: 801a strh r2, [r3, #0] return USBD_CDC_CfgDesc; 8010bec: 4b02 ldr r3, [pc, #8] @ (8010bf8 ) } 8010bee: 4618 mov r0, r3 8010bf0: 3718 adds r7, #24 8010bf2: 46bd mov sp, r7 8010bf4: bd80 pop {r7, pc} 8010bf6: bf00 nop 8010bf8: 2000005c .word 0x2000005c 08010bfc : * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) { 8010bfc: b580 push {r7, lr} 8010bfe: b086 sub sp, #24 8010c00: af00 add r7, sp, #0 8010c02: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); 8010c04: 2182 movs r1, #130 @ 0x82 8010c06: 4818 ldr r0, [pc, #96] @ (8010c68 ) 8010c08: f000 fc98 bl 801153c 8010c0c: 6178 str r0, [r7, #20] USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); 8010c0e: 2101 movs r1, #1 8010c10: 4815 ldr r0, [pc, #84] @ (8010c68 ) 8010c12: f000 fc93 bl 801153c 8010c16: 6138 str r0, [r7, #16] USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); 8010c18: 2181 movs r1, #129 @ 0x81 8010c1a: 4813 ldr r0, [pc, #76] @ (8010c68 ) 8010c1c: f000 fc8e bl 801153c 8010c20: 60f8 str r0, [r7, #12] if (pEpCmdDesc != NULL) 8010c22: 697b ldr r3, [r7, #20] 8010c24: 2b00 cmp r3, #0 8010c26: d002 beq.n 8010c2e { pEpCmdDesc->bInterval = CDC_HS_BINTERVAL; 8010c28: 697b ldr r3, [r7, #20] 8010c2a: 2210 movs r2, #16 8010c2c: 719a strb r2, [r3, #6] } if (pEpOutDesc != NULL) 8010c2e: 693b ldr r3, [r7, #16] 8010c30: 2b00 cmp r3, #0 8010c32: d006 beq.n 8010c42 { pEpOutDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE; 8010c34: 693b ldr r3, [r7, #16] 8010c36: 2200 movs r2, #0 8010c38: 711a strb r2, [r3, #4] 8010c3a: 2200 movs r2, #0 8010c3c: f042 0202 orr.w r2, r2, #2 8010c40: 715a strb r2, [r3, #5] } if (pEpInDesc != NULL) 8010c42: 68fb ldr r3, [r7, #12] 8010c44: 2b00 cmp r3, #0 8010c46: d006 beq.n 8010c56 { pEpInDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE; 8010c48: 68fb ldr r3, [r7, #12] 8010c4a: 2200 movs r2, #0 8010c4c: 711a strb r2, [r3, #4] 8010c4e: 2200 movs r2, #0 8010c50: f042 0202 orr.w r2, r2, #2 8010c54: 715a strb r2, [r3, #5] } *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); 8010c56: 687b ldr r3, [r7, #4] 8010c58: 2243 movs r2, #67 @ 0x43 8010c5a: 801a strh r2, [r3, #0] return USBD_CDC_CfgDesc; 8010c5c: 4b02 ldr r3, [pc, #8] @ (8010c68 ) } 8010c5e: 4618 mov r0, r3 8010c60: 3718 adds r7, #24 8010c62: 46bd mov sp, r7 8010c64: bd80 pop {r7, pc} 8010c66: bf00 nop 8010c68: 2000005c .word 0x2000005c 08010c6c : * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) { 8010c6c: b580 push {r7, lr} 8010c6e: b086 sub sp, #24 8010c70: af00 add r7, sp, #0 8010c72: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); 8010c74: 2182 movs r1, #130 @ 0x82 8010c76: 4818 ldr r0, [pc, #96] @ (8010cd8 ) 8010c78: f000 fc60 bl 801153c 8010c7c: 6178 str r0, [r7, #20] USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); 8010c7e: 2101 movs r1, #1 8010c80: 4815 ldr r0, [pc, #84] @ (8010cd8 ) 8010c82: f000 fc5b bl 801153c 8010c86: 6138 str r0, [r7, #16] USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); 8010c88: 2181 movs r1, #129 @ 0x81 8010c8a: 4813 ldr r0, [pc, #76] @ (8010cd8 ) 8010c8c: f000 fc56 bl 801153c 8010c90: 60f8 str r0, [r7, #12] if (pEpCmdDesc != NULL) 8010c92: 697b ldr r3, [r7, #20] 8010c94: 2b00 cmp r3, #0 8010c96: d002 beq.n 8010c9e { pEpCmdDesc->bInterval = CDC_FS_BINTERVAL; 8010c98: 697b ldr r3, [r7, #20] 8010c9a: 2210 movs r2, #16 8010c9c: 719a strb r2, [r3, #6] } if (pEpOutDesc != NULL) 8010c9e: 693b ldr r3, [r7, #16] 8010ca0: 2b00 cmp r3, #0 8010ca2: d006 beq.n 8010cb2 { pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; 8010ca4: 693b ldr r3, [r7, #16] 8010ca6: 2200 movs r2, #0 8010ca8: f042 0240 orr.w r2, r2, #64 @ 0x40 8010cac: 711a strb r2, [r3, #4] 8010cae: 2200 movs r2, #0 8010cb0: 715a strb r2, [r3, #5] } if (pEpInDesc != NULL) 8010cb2: 68fb ldr r3, [r7, #12] 8010cb4: 2b00 cmp r3, #0 8010cb6: d006 beq.n 8010cc6 { pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; 8010cb8: 68fb ldr r3, [r7, #12] 8010cba: 2200 movs r2, #0 8010cbc: f042 0240 orr.w r2, r2, #64 @ 0x40 8010cc0: 711a strb r2, [r3, #4] 8010cc2: 2200 movs r2, #0 8010cc4: 715a strb r2, [r3, #5] } *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); 8010cc6: 687b ldr r3, [r7, #4] 8010cc8: 2243 movs r2, #67 @ 0x43 8010cca: 801a strh r2, [r3, #0] return USBD_CDC_CfgDesc; 8010ccc: 4b02 ldr r3, [pc, #8] @ (8010cd8 ) } 8010cce: 4618 mov r0, r3 8010cd0: 3718 adds r7, #24 8010cd2: 46bd mov sp, r7 8010cd4: bd80 pop {r7, pc} 8010cd6: bf00 nop 8010cd8: 2000005c .word 0x2000005c 08010cdc : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) { 8010cdc: b480 push {r7} 8010cde: b083 sub sp, #12 8010ce0: af00 add r7, sp, #0 8010ce2: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); 8010ce4: 687b ldr r3, [r7, #4] 8010ce6: 220a movs r2, #10 8010ce8: 801a strh r2, [r3, #0] return USBD_CDC_DeviceQualifierDesc; 8010cea: 4b03 ldr r3, [pc, #12] @ (8010cf8 ) } 8010cec: 4618 mov r0, r3 8010cee: 370c adds r7, #12 8010cf0: 46bd mov sp, r7 8010cf2: f85d 7b04 ldr.w r7, [sp], #4 8010cf6: 4770 bx lr 8010cf8: 20000018 .word 0x20000018 08010cfc : * @param fops: CD Interface callback * @retval status */ uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops) { 8010cfc: b480 push {r7} 8010cfe: b083 sub sp, #12 8010d00: af00 add r7, sp, #0 8010d02: 6078 str r0, [r7, #4] 8010d04: 6039 str r1, [r7, #0] if (fops == NULL) 8010d06: 683b ldr r3, [r7, #0] 8010d08: 2b00 cmp r3, #0 8010d0a: d101 bne.n 8010d10 { return (uint8_t)USBD_FAIL; 8010d0c: 2303 movs r3, #3 8010d0e: e009 b.n 8010d24 } pdev->pUserData[pdev->classId] = fops; 8010d10: 687b ldr r3, [r7, #4] 8010d12: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8010d16: 687a ldr r2, [r7, #4] 8010d18: 33b0 adds r3, #176 @ 0xb0 8010d1a: 009b lsls r3, r3, #2 8010d1c: 4413 add r3, r2 8010d1e: 683a ldr r2, [r7, #0] 8010d20: 605a str r2, [r3, #4] return (uint8_t)USBD_OK; 8010d22: 2300 movs r3, #0 } 8010d24: 4618 mov r0, r3 8010d26: 370c adds r7, #12 8010d28: 46bd mov sp, r7 8010d2a: f85d 7b04 ldr.w r7, [sp], #4 8010d2e: 4770 bx lr 08010d30 : { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint32_t length) { 8010d30: b480 push {r7} 8010d32: b087 sub sp, #28 8010d34: af00 add r7, sp, #0 8010d36: 60f8 str r0, [r7, #12] 8010d38: 60b9 str r1, [r7, #8] 8010d3a: 607a str r2, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8010d3c: 68fb ldr r3, [r7, #12] 8010d3e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010d42: 68fb ldr r3, [r7, #12] 8010d44: 32b0 adds r2, #176 @ 0xb0 8010d46: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010d4a: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hcdc == NULL) 8010d4c: 697b ldr r3, [r7, #20] 8010d4e: 2b00 cmp r3, #0 8010d50: d101 bne.n 8010d56 { return (uint8_t)USBD_FAIL; 8010d52: 2303 movs r3, #3 8010d54: e008 b.n 8010d68 } hcdc->TxBuffer = pbuff; 8010d56: 697b ldr r3, [r7, #20] 8010d58: 68ba ldr r2, [r7, #8] 8010d5a: f8c3 2208 str.w r2, [r3, #520] @ 0x208 hcdc->TxLength = length; 8010d5e: 697b ldr r3, [r7, #20] 8010d60: 687a ldr r2, [r7, #4] 8010d62: f8c3 2210 str.w r2, [r3, #528] @ 0x210 return (uint8_t)USBD_OK; 8010d66: 2300 movs r3, #0 } 8010d68: 4618 mov r0, r3 8010d6a: 371c adds r7, #28 8010d6c: 46bd mov sp, r7 8010d6e: f85d 7b04 ldr.w r7, [sp], #4 8010d72: 4770 bx lr 08010d74 : * @param pdev: device instance * @param pbuff: Rx Buffer * @retval status */ uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) { 8010d74: b480 push {r7} 8010d76: b085 sub sp, #20 8010d78: af00 add r7, sp, #0 8010d7a: 6078 str r0, [r7, #4] 8010d7c: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8010d7e: 687b ldr r3, [r7, #4] 8010d80: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010d84: 687b ldr r3, [r7, #4] 8010d86: 32b0 adds r2, #176 @ 0xb0 8010d88: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010d8c: 60fb str r3, [r7, #12] if (hcdc == NULL) 8010d8e: 68fb ldr r3, [r7, #12] 8010d90: 2b00 cmp r3, #0 8010d92: d101 bne.n 8010d98 { return (uint8_t)USBD_FAIL; 8010d94: 2303 movs r3, #3 8010d96: e004 b.n 8010da2 } hcdc->RxBuffer = pbuff; 8010d98: 68fb ldr r3, [r7, #12] 8010d9a: 683a ldr r2, [r7, #0] 8010d9c: f8c3 2204 str.w r2, [r3, #516] @ 0x204 return (uint8_t)USBD_OK; 8010da0: 2300 movs r3, #0 } 8010da2: 4618 mov r0, r3 8010da4: 3714 adds r7, #20 8010da6: 46bd mov sp, r7 8010da8: f85d 7b04 ldr.w r7, [sp], #4 8010dac: 4770 bx lr ... 08010db0 : uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t ClassId) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) { 8010db0: b580 push {r7, lr} 8010db2: b084 sub sp, #16 8010db4: af00 add r7, sp, #0 8010db6: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8010db8: 687b ldr r3, [r7, #4] 8010dba: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010dbe: 687b ldr r3, [r7, #4] 8010dc0: 32b0 adds r2, #176 @ 0xb0 8010dc2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010dc6: 60bb str r3, [r7, #8] #endif /* USE_USBD_COMPOSITE */ USBD_StatusTypeDef ret = USBD_BUSY; 8010dc8: 2301 movs r3, #1 8010dca: 73fb strb r3, [r7, #15] #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, ClassId); #endif /* USE_USBD_COMPOSITE */ if (hcdc == NULL) 8010dcc: 68bb ldr r3, [r7, #8] 8010dce: 2b00 cmp r3, #0 8010dd0: d101 bne.n 8010dd6 { return (uint8_t)USBD_FAIL; 8010dd2: 2303 movs r3, #3 8010dd4: e025 b.n 8010e22 } if (hcdc->TxState == 0U) 8010dd6: 68bb ldr r3, [r7, #8] 8010dd8: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214 8010ddc: 2b00 cmp r3, #0 8010dde: d11f bne.n 8010e20 { /* Tx Transfer in progress */ hcdc->TxState = 1U; 8010de0: 68bb ldr r3, [r7, #8] 8010de2: 2201 movs r2, #1 8010de4: f8c3 2214 str.w r2, [r3, #532] @ 0x214 /* Update the packet total length */ pdev->ep_in[CDCInEpAdd & 0xFU].total_length = hcdc->TxLength; 8010de8: 4b10 ldr r3, [pc, #64] @ (8010e2c ) 8010dea: 781b ldrb r3, [r3, #0] 8010dec: f003 020f and.w r2, r3, #15 8010df0: 68bb ldr r3, [r7, #8] 8010df2: f8d3 1210 ldr.w r1, [r3, #528] @ 0x210 8010df6: 6878 ldr r0, [r7, #4] 8010df8: 4613 mov r3, r2 8010dfa: 009b lsls r3, r3, #2 8010dfc: 4413 add r3, r2 8010dfe: 009b lsls r3, r3, #2 8010e00: 4403 add r3, r0 8010e02: 3314 adds r3, #20 8010e04: 6019 str r1, [r3, #0] /* Transmit next packet */ (void)USBD_LL_Transmit(pdev, CDCInEpAdd, hcdc->TxBuffer, hcdc->TxLength); 8010e06: 4b09 ldr r3, [pc, #36] @ (8010e2c ) 8010e08: 7819 ldrb r1, [r3, #0] 8010e0a: 68bb ldr r3, [r7, #8] 8010e0c: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208 8010e10: 68bb ldr r3, [r7, #8] 8010e12: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210 8010e16: 6878 ldr r0, [r7, #4] 8010e18: f007 fcd1 bl 80187be ret = USBD_OK; 8010e1c: 2300 movs r3, #0 8010e1e: 73fb strb r3, [r7, #15] } return (uint8_t)ret; 8010e20: 7bfb ldrb r3, [r7, #15] } 8010e22: 4618 mov r0, r3 8010e24: 3710 adds r7, #16 8010e26: 46bd mov sp, r7 8010e28: bd80 pop {r7, pc} 8010e2a: bf00 nop 8010e2c: 2000009f .word 0x2000009f 08010e30 : * prepare OUT Endpoint for reception * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { 8010e30: b580 push {r7, lr} 8010e32: b084 sub sp, #16 8010e34: af00 add r7, sp, #0 8010e36: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8010e38: 687b ldr r3, [r7, #4] 8010e3a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010e3e: 687b ldr r3, [r7, #4] 8010e40: 32b0 adds r2, #176 @ 0xb0 8010e42: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010e46: 60fb str r3, [r7, #12] #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->pClassDataCmsit[pdev->classId] == NULL) 8010e48: 687b ldr r3, [r7, #4] 8010e4a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010e4e: 687b ldr r3, [r7, #4] 8010e50: 32b0 adds r2, #176 @ 0xb0 8010e52: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010e56: 2b00 cmp r3, #0 8010e58: d101 bne.n 8010e5e { return (uint8_t)USBD_FAIL; 8010e5a: 2303 movs r3, #3 8010e5c: e018 b.n 8010e90 } if (pdev->dev_speed == USBD_SPEED_HIGH) 8010e5e: 687b ldr r3, [r7, #4] 8010e60: 7c1b ldrb r3, [r3, #16] 8010e62: 2b00 cmp r3, #0 8010e64: d10a bne.n 8010e7c { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, 8010e66: 4b0c ldr r3, [pc, #48] @ (8010e98 ) 8010e68: 7819 ldrb r1, [r3, #0] 8010e6a: 68fb ldr r3, [r7, #12] 8010e6c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8010e70: f44f 7300 mov.w r3, #512 @ 0x200 8010e74: 6878 ldr r0, [r7, #4] 8010e76: f007 fcc3 bl 8018800 8010e7a: e008 b.n 8010e8e CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, 8010e7c: 4b06 ldr r3, [pc, #24] @ (8010e98 ) 8010e7e: 7819 ldrb r1, [r3, #0] 8010e80: 68fb ldr r3, [r7, #12] 8010e82: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8010e86: 2340 movs r3, #64 @ 0x40 8010e88: 6878 ldr r0, [r7, #4] 8010e8a: f007 fcb9 bl 8018800 CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 8010e8e: 2300 movs r3, #0 } 8010e90: 4618 mov r0, r3 8010e92: 3710 adds r7, #16 8010e94: 46bd mov sp, r7 8010e96: bd80 pop {r7, pc} 8010e98: 200000a0 .word 0x200000a0 08010e9c : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 8010e9c: b580 push {r7, lr} 8010e9e: b086 sub sp, #24 8010ea0: af00 add r7, sp, #0 8010ea2: 60f8 str r0, [r7, #12] 8010ea4: 60b9 str r1, [r7, #8] 8010ea6: 4613 mov r3, r2 8010ea8: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 8010eaa: 68fb ldr r3, [r7, #12] 8010eac: 2b00 cmp r3, #0 8010eae: d101 bne.n 8010eb4 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8010eb0: 2303 movs r3, #3 8010eb2: e01f b.n 8010ef4 pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 8010eb4: 68fb ldr r3, [r7, #12] 8010eb6: 2200 movs r2, #0 8010eb8: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 8010ebc: 68fb ldr r3, [r7, #12] 8010ebe: 2200 movs r2, #0 8010ec0: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 8010ec4: 68fb ldr r3, [r7, #12] 8010ec6: 2200 movs r2, #0 8010ec8: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 8010ecc: 68bb ldr r3, [r7, #8] 8010ece: 2b00 cmp r3, #0 8010ed0: d003 beq.n 8010eda { pdev->pDesc = pdesc; 8010ed2: 68fb ldr r3, [r7, #12] 8010ed4: 68ba ldr r2, [r7, #8] 8010ed6: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 8010eda: 68fb ldr r3, [r7, #12] 8010edc: 2201 movs r2, #1 8010ede: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 8010ee2: 68fb ldr r3, [r7, #12] 8010ee4: 79fa ldrb r2, [r7, #7] 8010ee6: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8010ee8: 68f8 ldr r0, [r7, #12] 8010eea: f007 fb1d bl 8018528 8010eee: 4603 mov r3, r0 8010ef0: 75fb strb r3, [r7, #23] return ret; 8010ef2: 7dfb ldrb r3, [r7, #23] } 8010ef4: 4618 mov r0, r3 8010ef6: 3718 adds r7, #24 8010ef8: 46bd mov sp, r7 8010efa: bd80 pop {r7, pc} 08010efc : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 8010efc: b580 push {r7, lr} 8010efe: b084 sub sp, #16 8010f00: af00 add r7, sp, #0 8010f02: 6078 str r0, [r7, #4] 8010f04: 6039 str r1, [r7, #0] uint16_t len = 0U; 8010f06: 2300 movs r3, #0 8010f08: 81fb strh r3, [r7, #14] if (pclass == NULL) 8010f0a: 683b ldr r3, [r7, #0] 8010f0c: 2b00 cmp r3, #0 8010f0e: d101 bne.n 8010f14 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8010f10: 2303 movs r3, #3 8010f12: e025 b.n 8010f60 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 8010f14: 687b ldr r3, [r7, #4] 8010f16: 683a ldr r2, [r7, #0] 8010f18: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 8010f1c: 687b ldr r3, [r7, #4] 8010f1e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010f22: 687b ldr r3, [r7, #4] 8010f24: 32ae adds r2, #174 @ 0xae 8010f26: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010f2a: 6adb ldr r3, [r3, #44] @ 0x2c 8010f2c: 2b00 cmp r3, #0 8010f2e: d00f beq.n 8010f50 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 8010f30: 687b ldr r3, [r7, #4] 8010f32: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010f36: 687b ldr r3, [r7, #4] 8010f38: 32ae adds r2, #174 @ 0xae 8010f3a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8010f3e: 6adb ldr r3, [r3, #44] @ 0x2c 8010f40: f107 020e add.w r2, r7, #14 8010f44: 4610 mov r0, r2 8010f46: 4798 blx r3 8010f48: 4602 mov r2, r0 8010f4a: 687b ldr r3, [r7, #4] 8010f4c: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8010f50: 687b ldr r3, [r7, #4] 8010f52: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8010f56: 1c5a adds r2, r3, #1 8010f58: 687b ldr r3, [r7, #4] 8010f5a: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 8010f5e: 2300 movs r3, #0 } 8010f60: 4618 mov r0, r3 8010f62: 3710 adds r7, #16 8010f64: 46bd mov sp, r7 8010f66: bd80 pop {r7, pc} 08010f68 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8010f68: b580 push {r7, lr} 8010f6a: b082 sub sp, #8 8010f6c: af00 add r7, sp, #0 8010f6e: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8010f70: 6878 ldr r0, [r7, #4] 8010f72: f007 fb3b bl 80185ec 8010f76: 4603 mov r3, r0 } 8010f78: 4618 mov r0, r3 8010f7a: 3708 adds r7, #8 8010f7c: 46bd mov sp, r7 8010f7e: bd80 pop {r7, pc} 08010f80 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8010f80: b480 push {r7} 8010f82: b083 sub sp, #12 8010f84: af00 add r7, sp, #0 8010f86: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8010f88: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 8010f8a: 4618 mov r0, r3 8010f8c: 370c adds r7, #12 8010f8e: 46bd mov sp, r7 8010f90: f85d 7b04 ldr.w r7, [sp], #4 8010f94: 4770 bx lr 08010f96 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8010f96: b580 push {r7, lr} 8010f98: b084 sub sp, #16 8010f9a: af00 add r7, sp, #0 8010f9c: 6078 str r0, [r7, #4] 8010f9e: 460b mov r3, r1 8010fa0: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8010fa2: 2300 movs r3, #0 8010fa4: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8010fa6: 687b ldr r3, [r7, #4] 8010fa8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8010fac: 2b00 cmp r3, #0 8010fae: d009 beq.n 8010fc4 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8010fb0: 687b ldr r3, [r7, #4] 8010fb2: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8010fb6: 681b ldr r3, [r3, #0] 8010fb8: 78fa ldrb r2, [r7, #3] 8010fba: 4611 mov r1, r2 8010fbc: 6878 ldr r0, [r7, #4] 8010fbe: 4798 blx r3 8010fc0: 4603 mov r3, r0 8010fc2: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8010fc4: 7bfb ldrb r3, [r7, #15] } 8010fc6: 4618 mov r0, r3 8010fc8: 3710 adds r7, #16 8010fca: 46bd mov sp, r7 8010fcc: bd80 pop {r7, pc} 08010fce : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8010fce: b580 push {r7, lr} 8010fd0: b084 sub sp, #16 8010fd2: af00 add r7, sp, #0 8010fd4: 6078 str r0, [r7, #4] 8010fd6: 460b mov r3, r1 8010fd8: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8010fda: 2300 movs r3, #0 8010fdc: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 8010fde: 687b ldr r3, [r7, #4] 8010fe0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8010fe4: 685b ldr r3, [r3, #4] 8010fe6: 78fa ldrb r2, [r7, #3] 8010fe8: 4611 mov r1, r2 8010fea: 6878 ldr r0, [r7, #4] 8010fec: 4798 blx r3 8010fee: 4603 mov r3, r0 8010ff0: 2b00 cmp r3, #0 8010ff2: d001 beq.n 8010ff8 { ret = USBD_FAIL; 8010ff4: 2303 movs r3, #3 8010ff6: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 8010ff8: 7bfb ldrb r3, [r7, #15] } 8010ffa: 4618 mov r0, r3 8010ffc: 3710 adds r7, #16 8010ffe: 46bd mov sp, r7 8011000: bd80 pop {r7, pc} 08011002 : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8011002: b580 push {r7, lr} 8011004: b084 sub sp, #16 8011006: af00 add r7, sp, #0 8011008: 6078 str r0, [r7, #4] 801100a: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 801100c: 687b ldr r3, [r7, #4] 801100e: f203 23aa addw r3, r3, #682 @ 0x2aa 8011012: 6839 ldr r1, [r7, #0] 8011014: 4618 mov r0, r3 8011016: f001 f8ba bl 801218e pdev->ep0_state = USBD_EP0_SETUP; 801101a: 687b ldr r3, [r7, #4] 801101c: 2201 movs r2, #1 801101e: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 8011022: 687b ldr r3, [r7, #4] 8011024: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8011028: 461a mov r2, r3 801102a: 687b ldr r3, [r7, #4] 801102c: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 8011030: 687b ldr r3, [r7, #4] 8011032: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8011036: f003 031f and.w r3, r3, #31 801103a: 2b02 cmp r3, #2 801103c: d01a beq.n 8011074 801103e: 2b02 cmp r3, #2 8011040: d822 bhi.n 8011088 8011042: 2b00 cmp r3, #0 8011044: d002 beq.n 801104c 8011046: 2b01 cmp r3, #1 8011048: d00a beq.n 8011060 801104a: e01d b.n 8011088 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 801104c: 687b ldr r3, [r7, #4] 801104e: f203 23aa addw r3, r3, #682 @ 0x2aa 8011052: 4619 mov r1, r3 8011054: 6878 ldr r0, [r7, #4] 8011056: f000 fae5 bl 8011624 801105a: 4603 mov r3, r0 801105c: 73fb strb r3, [r7, #15] break; 801105e: e020 b.n 80110a2 case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8011060: 687b ldr r3, [r7, #4] 8011062: f203 23aa addw r3, r3, #682 @ 0x2aa 8011066: 4619 mov r1, r3 8011068: 6878 ldr r0, [r7, #4] 801106a: f000 fb4d bl 8011708 801106e: 4603 mov r3, r0 8011070: 73fb strb r3, [r7, #15] break; 8011072: e016 b.n 80110a2 case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8011074: 687b ldr r3, [r7, #4] 8011076: f203 23aa addw r3, r3, #682 @ 0x2aa 801107a: 4619 mov r1, r3 801107c: 6878 ldr r0, [r7, #4] 801107e: f000 fbaf bl 80117e0 8011082: 4603 mov r3, r0 8011084: 73fb strb r3, [r7, #15] break; 8011086: e00c b.n 80110a2 default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8011088: 687b ldr r3, [r7, #4] 801108a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 801108e: f023 037f bic.w r3, r3, #127 @ 0x7f 8011092: b2db uxtb r3, r3 8011094: 4619 mov r1, r3 8011096: 6878 ldr r0, [r7, #4] 8011098: f007 fb08 bl 80186ac 801109c: 4603 mov r3, r0 801109e: 73fb strb r3, [r7, #15] break; 80110a0: bf00 nop } return ret; 80110a2: 7bfb ldrb r3, [r7, #15] } 80110a4: 4618 mov r0, r3 80110a6: 3710 adds r7, #16 80110a8: 46bd mov sp, r7 80110aa: bd80 pop {r7, pc} 080110ac : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 80110ac: b580 push {r7, lr} 80110ae: b086 sub sp, #24 80110b0: af00 add r7, sp, #0 80110b2: 60f8 str r0, [r7, #12] 80110b4: 460b mov r3, r1 80110b6: 607a str r2, [r7, #4] 80110b8: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 80110ba: 2300 movs r3, #0 80110bc: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 80110be: 7afb ldrb r3, [r7, #11] 80110c0: 2b00 cmp r3, #0 80110c2: d177 bne.n 80111b4 { pep = &pdev->ep_out[0]; 80110c4: 68fb ldr r3, [r7, #12] 80110c6: f503 73aa add.w r3, r3, #340 @ 0x154 80110ca: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 80110cc: 68fb ldr r3, [r7, #12] 80110ce: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 80110d2: 2b03 cmp r3, #3 80110d4: f040 80a1 bne.w 801121a { if (pep->rem_length > pep->maxpacket) 80110d8: 693b ldr r3, [r7, #16] 80110da: 685b ldr r3, [r3, #4] 80110dc: 693a ldr r2, [r7, #16] 80110de: 8992 ldrh r2, [r2, #12] 80110e0: 4293 cmp r3, r2 80110e2: d91c bls.n 801111e { pep->rem_length -= pep->maxpacket; 80110e4: 693b ldr r3, [r7, #16] 80110e6: 685b ldr r3, [r3, #4] 80110e8: 693a ldr r2, [r7, #16] 80110ea: 8992 ldrh r2, [r2, #12] 80110ec: 1a9a subs r2, r3, r2 80110ee: 693b ldr r3, [r7, #16] 80110f0: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 80110f2: 693b ldr r3, [r7, #16] 80110f4: 691b ldr r3, [r3, #16] 80110f6: 693a ldr r2, [r7, #16] 80110f8: 8992 ldrh r2, [r2, #12] 80110fa: 441a add r2, r3 80110fc: 693b ldr r3, [r7, #16] 80110fe: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8011100: 693b ldr r3, [r7, #16] 8011102: 6919 ldr r1, [r3, #16] 8011104: 693b ldr r3, [r7, #16] 8011106: 899b ldrh r3, [r3, #12] 8011108: 461a mov r2, r3 801110a: 693b ldr r3, [r7, #16] 801110c: 685b ldr r3, [r3, #4] 801110e: 4293 cmp r3, r2 8011110: bf38 it cc 8011112: 4613 movcc r3, r2 8011114: 461a mov r2, r3 8011116: 68f8 ldr r0, [r7, #12] 8011118: f001 f940 bl 801239c 801111c: e07d b.n 801121a } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 801111e: 68fb ldr r3, [r7, #12] 8011120: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8011124: f003 031f and.w r3, r3, #31 8011128: 2b02 cmp r3, #2 801112a: d014 beq.n 8011156 801112c: 2b02 cmp r3, #2 801112e: d81d bhi.n 801116c 8011130: 2b00 cmp r3, #0 8011132: d002 beq.n 801113a 8011134: 2b01 cmp r3, #1 8011136: d003 beq.n 8011140 8011138: e018 b.n 801116c { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 801113a: 2300 movs r3, #0 801113c: 75bb strb r3, [r7, #22] break; 801113e: e018 b.n 8011172 case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8011140: 68fb ldr r3, [r7, #12] 8011142: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8011146: b2db uxtb r3, r3 8011148: 4619 mov r1, r3 801114a: 68f8 ldr r0, [r7, #12] 801114c: f000 f9dc bl 8011508 8011150: 4603 mov r3, r0 8011152: 75bb strb r3, [r7, #22] break; 8011154: e00d b.n 8011172 case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8011156: 68fb ldr r3, [r7, #12] 8011158: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 801115c: b2db uxtb r3, r3 801115e: 4619 mov r1, r3 8011160: 68f8 ldr r0, [r7, #12] 8011162: f000 f9de bl 8011522 8011166: 4603 mov r3, r0 8011168: 75bb strb r3, [r7, #22] break; 801116a: e002 b.n 8011172 default: /* Back to the first class in case of doubt */ idx = 0U; 801116c: 2300 movs r3, #0 801116e: 75bb strb r3, [r7, #22] break; 8011170: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8011172: 7dbb ldrb r3, [r7, #22] 8011174: 2b00 cmp r3, #0 8011176: d119 bne.n 80111ac { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011178: 68fb ldr r3, [r7, #12] 801117a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 801117e: b2db uxtb r3, r3 8011180: 2b03 cmp r3, #3 8011182: d113 bne.n 80111ac { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8011184: 7dba ldrb r2, [r7, #22] 8011186: 68fb ldr r3, [r7, #12] 8011188: 32ae adds r2, #174 @ 0xae 801118a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801118e: 691b ldr r3, [r3, #16] 8011190: 2b00 cmp r3, #0 8011192: d00b beq.n 80111ac { pdev->classId = idx; 8011194: 7dba ldrb r2, [r7, #22] 8011196: 68fb ldr r3, [r7, #12] 8011198: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 801119c: 7dba ldrb r2, [r7, #22] 801119e: 68fb ldr r3, [r7, #12] 80111a0: 32ae adds r2, #174 @ 0xae 80111a2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80111a6: 691b ldr r3, [r3, #16] 80111a8: 68f8 ldr r0, [r7, #12] 80111aa: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 80111ac: 68f8 ldr r0, [r7, #12] 80111ae: f001 f906 bl 80123be 80111b2: e032 b.n 801121a } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 80111b4: 7afb ldrb r3, [r7, #11] 80111b6: f003 037f and.w r3, r3, #127 @ 0x7f 80111ba: b2db uxtb r3, r3 80111bc: 4619 mov r1, r3 80111be: 68f8 ldr r0, [r7, #12] 80111c0: f000 f9af bl 8011522 80111c4: 4603 mov r3, r0 80111c6: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 80111c8: 7dbb ldrb r3, [r7, #22] 80111ca: 2bff cmp r3, #255 @ 0xff 80111cc: d025 beq.n 801121a 80111ce: 7dbb ldrb r3, [r7, #22] 80111d0: 2b00 cmp r3, #0 80111d2: d122 bne.n 801121a { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80111d4: 68fb ldr r3, [r7, #12] 80111d6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80111da: b2db uxtb r3, r3 80111dc: 2b03 cmp r3, #3 80111de: d117 bne.n 8011210 { if (pdev->pClass[idx]->DataOut != NULL) 80111e0: 7dba ldrb r2, [r7, #22] 80111e2: 68fb ldr r3, [r7, #12] 80111e4: 32ae adds r2, #174 @ 0xae 80111e6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80111ea: 699b ldr r3, [r3, #24] 80111ec: 2b00 cmp r3, #0 80111ee: d00f beq.n 8011210 { pdev->classId = idx; 80111f0: 7dba ldrb r2, [r7, #22] 80111f2: 68fb ldr r3, [r7, #12] 80111f4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 80111f8: 7dba ldrb r2, [r7, #22] 80111fa: 68fb ldr r3, [r7, #12] 80111fc: 32ae adds r2, #174 @ 0xae 80111fe: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011202: 699b ldr r3, [r3, #24] 8011204: 7afa ldrb r2, [r7, #11] 8011206: 4611 mov r1, r2 8011208: 68f8 ldr r0, [r7, #12] 801120a: 4798 blx r3 801120c: 4603 mov r3, r0 801120e: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8011210: 7dfb ldrb r3, [r7, #23] 8011212: 2b00 cmp r3, #0 8011214: d001 beq.n 801121a { return ret; 8011216: 7dfb ldrb r3, [r7, #23] 8011218: e000 b.n 801121c } } } return USBD_OK; 801121a: 2300 movs r3, #0 } 801121c: 4618 mov r0, r3 801121e: 3718 adds r7, #24 8011220: 46bd mov sp, r7 8011222: bd80 pop {r7, pc} 08011224 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8011224: b580 push {r7, lr} 8011226: b086 sub sp, #24 8011228: af00 add r7, sp, #0 801122a: 60f8 str r0, [r7, #12] 801122c: 460b mov r3, r1 801122e: 607a str r2, [r7, #4] 8011230: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8011232: 7afb ldrb r3, [r7, #11] 8011234: 2b00 cmp r3, #0 8011236: d178 bne.n 801132a { pep = &pdev->ep_in[0]; 8011238: 68fb ldr r3, [r7, #12] 801123a: 3314 adds r3, #20 801123c: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 801123e: 68fb ldr r3, [r7, #12] 8011240: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8011244: 2b02 cmp r3, #2 8011246: d163 bne.n 8011310 { if (pep->rem_length > pep->maxpacket) 8011248: 693b ldr r3, [r7, #16] 801124a: 685b ldr r3, [r3, #4] 801124c: 693a ldr r2, [r7, #16] 801124e: 8992 ldrh r2, [r2, #12] 8011250: 4293 cmp r3, r2 8011252: d91c bls.n 801128e { pep->rem_length -= pep->maxpacket; 8011254: 693b ldr r3, [r7, #16] 8011256: 685b ldr r3, [r3, #4] 8011258: 693a ldr r2, [r7, #16] 801125a: 8992 ldrh r2, [r2, #12] 801125c: 1a9a subs r2, r3, r2 801125e: 693b ldr r3, [r7, #16] 8011260: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8011262: 693b ldr r3, [r7, #16] 8011264: 691b ldr r3, [r3, #16] 8011266: 693a ldr r2, [r7, #16] 8011268: 8992 ldrh r2, [r2, #12] 801126a: 441a add r2, r3 801126c: 693b ldr r3, [r7, #16] 801126e: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8011270: 693b ldr r3, [r7, #16] 8011272: 6919 ldr r1, [r3, #16] 8011274: 693b ldr r3, [r7, #16] 8011276: 685b ldr r3, [r3, #4] 8011278: 461a mov r2, r3 801127a: 68f8 ldr r0, [r7, #12] 801127c: f001 f85c bl 8012338 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8011280: 2300 movs r3, #0 8011282: 2200 movs r2, #0 8011284: 2100 movs r1, #0 8011286: 68f8 ldr r0, [r7, #12] 8011288: f007 faba bl 8018800 801128c: e040 b.n 8011310 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 801128e: 693b ldr r3, [r7, #16] 8011290: 899b ldrh r3, [r3, #12] 8011292: 461a mov r2, r3 8011294: 693b ldr r3, [r7, #16] 8011296: 685b ldr r3, [r3, #4] 8011298: 429a cmp r2, r3 801129a: d11c bne.n 80112d6 (pep->total_length >= pep->maxpacket) && 801129c: 693b ldr r3, [r7, #16] 801129e: 681b ldr r3, [r3, #0] 80112a0: 693a ldr r2, [r7, #16] 80112a2: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 80112a4: 4293 cmp r3, r2 80112a6: d316 bcc.n 80112d6 (pep->total_length < pdev->ep0_data_len)) 80112a8: 693b ldr r3, [r7, #16] 80112aa: 681a ldr r2, [r3, #0] 80112ac: 68fb ldr r3, [r7, #12] 80112ae: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 80112b2: 429a cmp r2, r3 80112b4: d20f bcs.n 80112d6 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 80112b6: 2200 movs r2, #0 80112b8: 2100 movs r1, #0 80112ba: 68f8 ldr r0, [r7, #12] 80112bc: f001 f83c bl 8012338 pdev->ep0_data_len = 0U; 80112c0: 68fb ldr r3, [r7, #12] 80112c2: 2200 movs r2, #0 80112c4: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 80112c8: 2300 movs r3, #0 80112ca: 2200 movs r2, #0 80112cc: 2100 movs r1, #0 80112ce: 68f8 ldr r0, [r7, #12] 80112d0: f007 fa96 bl 8018800 80112d4: e01c b.n 8011310 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 80112d6: 68fb ldr r3, [r7, #12] 80112d8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80112dc: b2db uxtb r3, r3 80112de: 2b03 cmp r3, #3 80112e0: d10f bne.n 8011302 { if (pdev->pClass[0]->EP0_TxSent != NULL) 80112e2: 68fb ldr r3, [r7, #12] 80112e4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80112e8: 68db ldr r3, [r3, #12] 80112ea: 2b00 cmp r3, #0 80112ec: d009 beq.n 8011302 { pdev->classId = 0U; 80112ee: 68fb ldr r3, [r7, #12] 80112f0: 2200 movs r2, #0 80112f2: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 80112f6: 68fb ldr r3, [r7, #12] 80112f8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80112fc: 68db ldr r3, [r3, #12] 80112fe: 68f8 ldr r0, [r7, #12] 8011300: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8011302: 2180 movs r1, #128 @ 0x80 8011304: 68f8 ldr r0, [r7, #12] 8011306: f007 f9d1 bl 80186ac (void)USBD_CtlReceiveStatus(pdev); 801130a: 68f8 ldr r0, [r7, #12] 801130c: f001 f86a bl 80123e4 } } } if (pdev->dev_test_mode != 0U) 8011310: 68fb ldr r3, [r7, #12] 8011312: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8011316: 2b00 cmp r3, #0 8011318: d03a beq.n 8011390 { (void)USBD_RunTestMode(pdev); 801131a: 68f8 ldr r0, [r7, #12] 801131c: f7ff fe30 bl 8010f80 pdev->dev_test_mode = 0U; 8011320: 68fb ldr r3, [r7, #12] 8011322: 2200 movs r2, #0 8011324: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8011328: e032 b.n 8011390 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 801132a: 7afb ldrb r3, [r7, #11] 801132c: f063 037f orn r3, r3, #127 @ 0x7f 8011330: b2db uxtb r3, r3 8011332: 4619 mov r1, r3 8011334: 68f8 ldr r0, [r7, #12] 8011336: f000 f8f4 bl 8011522 801133a: 4603 mov r3, r0 801133c: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 801133e: 7dfb ldrb r3, [r7, #23] 8011340: 2bff cmp r3, #255 @ 0xff 8011342: d025 beq.n 8011390 8011344: 7dfb ldrb r3, [r7, #23] 8011346: 2b00 cmp r3, #0 8011348: d122 bne.n 8011390 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 801134a: 68fb ldr r3, [r7, #12] 801134c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011350: b2db uxtb r3, r3 8011352: 2b03 cmp r3, #3 8011354: d11c bne.n 8011390 { if (pdev->pClass[idx]->DataIn != NULL) 8011356: 7dfa ldrb r2, [r7, #23] 8011358: 68fb ldr r3, [r7, #12] 801135a: 32ae adds r2, #174 @ 0xae 801135c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011360: 695b ldr r3, [r3, #20] 8011362: 2b00 cmp r3, #0 8011364: d014 beq.n 8011390 { pdev->classId = idx; 8011366: 7dfa ldrb r2, [r7, #23] 8011368: 68fb ldr r3, [r7, #12] 801136a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 801136e: 7dfa ldrb r2, [r7, #23] 8011370: 68fb ldr r3, [r7, #12] 8011372: 32ae adds r2, #174 @ 0xae 8011374: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011378: 695b ldr r3, [r3, #20] 801137a: 7afa ldrb r2, [r7, #11] 801137c: 4611 mov r1, r2 801137e: 68f8 ldr r0, [r7, #12] 8011380: 4798 blx r3 8011382: 4603 mov r3, r0 8011384: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8011386: 7dbb ldrb r3, [r7, #22] 8011388: 2b00 cmp r3, #0 801138a: d001 beq.n 8011390 { return ret; 801138c: 7dbb ldrb r3, [r7, #22] 801138e: e000 b.n 8011392 } } } } return USBD_OK; 8011390: 2300 movs r3, #0 } 8011392: 4618 mov r0, r3 8011394: 3718 adds r7, #24 8011396: 46bd mov sp, r7 8011398: bd80 pop {r7, pc} 0801139a : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 801139a: b580 push {r7, lr} 801139c: b084 sub sp, #16 801139e: af00 add r7, sp, #0 80113a0: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 80113a2: 2300 movs r3, #0 80113a4: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 80113a6: 687b ldr r3, [r7, #4] 80113a8: 2201 movs r2, #1 80113aa: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 80113ae: 687b ldr r3, [r7, #4] 80113b0: 2200 movs r2, #0 80113b2: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 80113b6: 687b ldr r3, [r7, #4] 80113b8: 2200 movs r2, #0 80113ba: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 80113bc: 687b ldr r3, [r7, #4] 80113be: 2200 movs r2, #0 80113c0: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 80113c4: 687b ldr r3, [r7, #4] 80113c6: 2200 movs r2, #0 80113c8: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 80113cc: 687b ldr r3, [r7, #4] 80113ce: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80113d2: 2b00 cmp r3, #0 80113d4: d014 beq.n 8011400 { if (pdev->pClass[0]->DeInit != NULL) 80113d6: 687b ldr r3, [r7, #4] 80113d8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80113dc: 685b ldr r3, [r3, #4] 80113de: 2b00 cmp r3, #0 80113e0: d00e beq.n 8011400 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 80113e2: 687b ldr r3, [r7, #4] 80113e4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80113e8: 685b ldr r3, [r3, #4] 80113ea: 687a ldr r2, [r7, #4] 80113ec: 6852 ldr r2, [r2, #4] 80113ee: b2d2 uxtb r2, r2 80113f0: 4611 mov r1, r2 80113f2: 6878 ldr r0, [r7, #4] 80113f4: 4798 blx r3 80113f6: 4603 mov r3, r0 80113f8: 2b00 cmp r3, #0 80113fa: d001 beq.n 8011400 { ret = USBD_FAIL; 80113fc: 2303 movs r3, #3 80113fe: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8011400: 2340 movs r3, #64 @ 0x40 8011402: 2200 movs r2, #0 8011404: 2100 movs r1, #0 8011406: 6878 ldr r0, [r7, #4] 8011408: f007 f90b bl 8018622 pdev->ep_out[0x00U & 0xFU].is_used = 1U; 801140c: 687b ldr r3, [r7, #4] 801140e: 2201 movs r2, #1 8011410: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8011414: 687b ldr r3, [r7, #4] 8011416: 2240 movs r2, #64 @ 0x40 8011418: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 801141c: 2340 movs r3, #64 @ 0x40 801141e: 2200 movs r2, #0 8011420: 2180 movs r1, #128 @ 0x80 8011422: 6878 ldr r0, [r7, #4] 8011424: f007 f8fd bl 8018622 pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8011428: 687b ldr r3, [r7, #4] 801142a: 2201 movs r2, #1 801142c: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8011430: 687b ldr r3, [r7, #4] 8011432: 2240 movs r2, #64 @ 0x40 8011434: 841a strh r2, [r3, #32] return ret; 8011436: 7bfb ldrb r3, [r7, #15] } 8011438: 4618 mov r0, r3 801143a: 3710 adds r7, #16 801143c: 46bd mov sp, r7 801143e: bd80 pop {r7, pc} 08011440 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8011440: b480 push {r7} 8011442: b083 sub sp, #12 8011444: af00 add r7, sp, #0 8011446: 6078 str r0, [r7, #4] 8011448: 460b mov r3, r1 801144a: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 801144c: 687b ldr r3, [r7, #4] 801144e: 78fa ldrb r2, [r7, #3] 8011450: 741a strb r2, [r3, #16] return USBD_OK; 8011452: 2300 movs r3, #0 } 8011454: 4618 mov r0, r3 8011456: 370c adds r7, #12 8011458: 46bd mov sp, r7 801145a: f85d 7b04 ldr.w r7, [sp], #4 801145e: 4770 bx lr 08011460 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8011460: b480 push {r7} 8011462: b083 sub sp, #12 8011464: af00 add r7, sp, #0 8011466: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8011468: 687b ldr r3, [r7, #4] 801146a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 801146e: b2db uxtb r3, r3 8011470: 2b04 cmp r3, #4 8011472: d006 beq.n 8011482 { pdev->dev_old_state = pdev->dev_state; 8011474: 687b ldr r3, [r7, #4] 8011476: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 801147a: b2da uxtb r2, r3 801147c: 687b ldr r3, [r7, #4] 801147e: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 8011482: 687b ldr r3, [r7, #4] 8011484: 2204 movs r2, #4 8011486: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 801148a: 2300 movs r3, #0 } 801148c: 4618 mov r0, r3 801148e: 370c adds r7, #12 8011490: 46bd mov sp, r7 8011492: f85d 7b04 ldr.w r7, [sp], #4 8011496: 4770 bx lr 08011498 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8011498: b480 push {r7} 801149a: b083 sub sp, #12 801149c: af00 add r7, sp, #0 801149e: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 80114a0: 687b ldr r3, [r7, #4] 80114a2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80114a6: b2db uxtb r3, r3 80114a8: 2b04 cmp r3, #4 80114aa: d106 bne.n 80114ba { pdev->dev_state = pdev->dev_old_state; 80114ac: 687b ldr r3, [r7, #4] 80114ae: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 80114b2: b2da uxtb r2, r3 80114b4: 687b ldr r3, [r7, #4] 80114b6: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 80114ba: 2300 movs r3, #0 } 80114bc: 4618 mov r0, r3 80114be: 370c adds r7, #12 80114c0: 46bd mov sp, r7 80114c2: f85d 7b04 ldr.w r7, [sp], #4 80114c6: 4770 bx lr 080114c8 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 80114c8: b580 push {r7, lr} 80114ca: b082 sub sp, #8 80114cc: af00 add r7, sp, #0 80114ce: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 80114d0: 687b ldr r3, [r7, #4] 80114d2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80114d6: b2db uxtb r3, r3 80114d8: 2b03 cmp r3, #3 80114da: d110 bne.n 80114fe } } } } #else if (pdev->pClass[0] != NULL) 80114dc: 687b ldr r3, [r7, #4] 80114de: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80114e2: 2b00 cmp r3, #0 80114e4: d00b beq.n 80114fe { if (pdev->pClass[0]->SOF != NULL) 80114e6: 687b ldr r3, [r7, #4] 80114e8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80114ec: 69db ldr r3, [r3, #28] 80114ee: 2b00 cmp r3, #0 80114f0: d005 beq.n 80114fe { (void)pdev->pClass[0]->SOF(pdev); 80114f2: 687b ldr r3, [r7, #4] 80114f4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80114f8: 69db ldr r3, [r3, #28] 80114fa: 6878 ldr r0, [r7, #4] 80114fc: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 80114fe: 2300 movs r3, #0 } 8011500: 4618 mov r0, r3 8011502: 3708 adds r7, #8 8011504: 46bd mov sp, r7 8011506: bd80 pop {r7, pc} 08011508 : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 8011508: b480 push {r7} 801150a: b083 sub sp, #12 801150c: af00 add r7, sp, #0 801150e: 6078 str r0, [r7, #4] 8011510: 460b mov r3, r1 8011512: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8011514: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8011516: 4618 mov r0, r3 8011518: 370c adds r7, #12 801151a: 46bd mov sp, r7 801151c: f85d 7b04 ldr.w r7, [sp], #4 8011520: 4770 bx lr 08011522 : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8011522: b480 push {r7} 8011524: b083 sub sp, #12 8011526: af00 add r7, sp, #0 8011528: 6078 str r0, [r7, #4] 801152a: 460b mov r3, r1 801152c: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 801152e: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8011530: 4618 mov r0, r3 8011532: 370c adds r7, #12 8011534: 46bd mov sp, r7 8011536: f85d 7b04 ldr.w r7, [sp], #4 801153a: 4770 bx lr 0801153c : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 801153c: b580 push {r7, lr} 801153e: b086 sub sp, #24 8011540: af00 add r7, sp, #0 8011542: 6078 str r0, [r7, #4] 8011544: 460b mov r3, r1 8011546: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 8011548: 687b ldr r3, [r7, #4] 801154a: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 801154c: 687b ldr r3, [r7, #4] 801154e: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8011550: 2300 movs r3, #0 8011552: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8011554: 68fb ldr r3, [r7, #12] 8011556: 885b ldrh r3, [r3, #2] 8011558: b29b uxth r3, r3 801155a: 68fa ldr r2, [r7, #12] 801155c: 7812 ldrb r2, [r2, #0] 801155e: 4293 cmp r3, r2 8011560: d91f bls.n 80115a2 { ptr = desc->bLength; 8011562: 68fb ldr r3, [r7, #12] 8011564: 781b ldrb r3, [r3, #0] 8011566: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 8011568: e013 b.n 8011592 { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 801156a: f107 030a add.w r3, r7, #10 801156e: 4619 mov r1, r3 8011570: 6978 ldr r0, [r7, #20] 8011572: f000 f81b bl 80115ac 8011576: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 8011578: 697b ldr r3, [r7, #20] 801157a: 785b ldrb r3, [r3, #1] 801157c: 2b05 cmp r3, #5 801157e: d108 bne.n 8011592 { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 8011580: 697b ldr r3, [r7, #20] 8011582: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 8011584: 693b ldr r3, [r7, #16] 8011586: 789b ldrb r3, [r3, #2] 8011588: 78fa ldrb r2, [r7, #3] 801158a: 429a cmp r2, r3 801158c: d008 beq.n 80115a0 { break; } else { pEpDesc = NULL; 801158e: 2300 movs r3, #0 8011590: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 8011592: 68fb ldr r3, [r7, #12] 8011594: 885b ldrh r3, [r3, #2] 8011596: b29a uxth r2, r3 8011598: 897b ldrh r3, [r7, #10] 801159a: 429a cmp r2, r3 801159c: d8e5 bhi.n 801156a 801159e: e000 b.n 80115a2 break; 80115a0: bf00 nop } } } } return (void *)pEpDesc; 80115a2: 693b ldr r3, [r7, #16] } 80115a4: 4618 mov r0, r3 80115a6: 3718 adds r7, #24 80115a8: 46bd mov sp, r7 80115aa: bd80 pop {r7, pc} 080115ac : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 80115ac: b480 push {r7} 80115ae: b085 sub sp, #20 80115b0: af00 add r7, sp, #0 80115b2: 6078 str r0, [r7, #4] 80115b4: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 80115b6: 687b ldr r3, [r7, #4] 80115b8: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 80115ba: 683b ldr r3, [r7, #0] 80115bc: 881b ldrh r3, [r3, #0] 80115be: 68fa ldr r2, [r7, #12] 80115c0: 7812 ldrb r2, [r2, #0] 80115c2: 4413 add r3, r2 80115c4: b29a uxth r2, r3 80115c6: 683b ldr r3, [r7, #0] 80115c8: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 80115ca: 68fb ldr r3, [r7, #12] 80115cc: 781b ldrb r3, [r3, #0] 80115ce: 461a mov r2, r3 80115d0: 687b ldr r3, [r7, #4] 80115d2: 4413 add r3, r2 80115d4: 60fb str r3, [r7, #12] return (pnext); 80115d6: 68fb ldr r3, [r7, #12] } 80115d8: 4618 mov r0, r3 80115da: 3714 adds r7, #20 80115dc: 46bd mov sp, r7 80115de: f85d 7b04 ldr.w r7, [sp], #4 80115e2: 4770 bx lr 080115e4 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 80115e4: b480 push {r7} 80115e6: b087 sub sp, #28 80115e8: af00 add r7, sp, #0 80115ea: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 80115ec: 687b ldr r3, [r7, #4] 80115ee: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 80115f0: 697b ldr r3, [r7, #20] 80115f2: 781b ldrb r3, [r3, #0] 80115f4: 827b strh r3, [r7, #18] _pbuff++; 80115f6: 697b ldr r3, [r7, #20] 80115f8: 3301 adds r3, #1 80115fa: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 80115fc: 697b ldr r3, [r7, #20] 80115fe: 781b ldrb r3, [r3, #0] 8011600: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8011602: f9b7 3010 ldrsh.w r3, [r7, #16] 8011606: 021b lsls r3, r3, #8 8011608: b21a sxth r2, r3 801160a: f9b7 3012 ldrsh.w r3, [r7, #18] 801160e: 4313 orrs r3, r2 8011610: b21b sxth r3, r3 8011612: 81fb strh r3, [r7, #14] return _SwapVal; 8011614: 89fb ldrh r3, [r7, #14] } 8011616: 4618 mov r0, r3 8011618: 371c adds r7, #28 801161a: 46bd mov sp, r7 801161c: f85d 7b04 ldr.w r7, [sp], #4 8011620: 4770 bx lr ... 08011624 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8011624: b580 push {r7, lr} 8011626: b084 sub sp, #16 8011628: af00 add r7, sp, #0 801162a: 6078 str r0, [r7, #4] 801162c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 801162e: 2300 movs r3, #0 8011630: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8011632: 683b ldr r3, [r7, #0] 8011634: 781b ldrb r3, [r3, #0] 8011636: f003 0360 and.w r3, r3, #96 @ 0x60 801163a: 2b40 cmp r3, #64 @ 0x40 801163c: d005 beq.n 801164a 801163e: 2b40 cmp r3, #64 @ 0x40 8011640: d857 bhi.n 80116f2 8011642: 2b00 cmp r3, #0 8011644: d00f beq.n 8011666 8011646: 2b20 cmp r3, #32 8011648: d153 bne.n 80116f2 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 801164a: 687b ldr r3, [r7, #4] 801164c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8011650: 687b ldr r3, [r7, #4] 8011652: 32ae adds r2, #174 @ 0xae 8011654: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011658: 689b ldr r3, [r3, #8] 801165a: 6839 ldr r1, [r7, #0] 801165c: 6878 ldr r0, [r7, #4] 801165e: 4798 blx r3 8011660: 4603 mov r3, r0 8011662: 73fb strb r3, [r7, #15] break; 8011664: e04a b.n 80116fc case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8011666: 683b ldr r3, [r7, #0] 8011668: 785b ldrb r3, [r3, #1] 801166a: 2b09 cmp r3, #9 801166c: d83b bhi.n 80116e6 801166e: a201 add r2, pc, #4 @ (adr r2, 8011674 ) 8011670: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011674: 080116c9 .word 0x080116c9 8011678: 080116dd .word 0x080116dd 801167c: 080116e7 .word 0x080116e7 8011680: 080116d3 .word 0x080116d3 8011684: 080116e7 .word 0x080116e7 8011688: 080116a7 .word 0x080116a7 801168c: 0801169d .word 0x0801169d 8011690: 080116e7 .word 0x080116e7 8011694: 080116bf .word 0x080116bf 8011698: 080116b1 .word 0x080116b1 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 801169c: 6839 ldr r1, [r7, #0] 801169e: 6878 ldr r0, [r7, #4] 80116a0: f000 fa3e bl 8011b20 break; 80116a4: e024 b.n 80116f0 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 80116a6: 6839 ldr r1, [r7, #0] 80116a8: 6878 ldr r0, [r7, #4] 80116aa: f000 fbcd bl 8011e48 break; 80116ae: e01f b.n 80116f0 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 80116b0: 6839 ldr r1, [r7, #0] 80116b2: 6878 ldr r0, [r7, #4] 80116b4: f000 fc0c bl 8011ed0 80116b8: 4603 mov r3, r0 80116ba: 73fb strb r3, [r7, #15] break; 80116bc: e018 b.n 80116f0 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 80116be: 6839 ldr r1, [r7, #0] 80116c0: 6878 ldr r0, [r7, #4] 80116c2: f000 fcaf bl 8012024 break; 80116c6: e013 b.n 80116f0 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 80116c8: 6839 ldr r1, [r7, #0] 80116ca: 6878 ldr r0, [r7, #4] 80116cc: f000 fce0 bl 8012090 break; 80116d0: e00e b.n 80116f0 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 80116d2: 6839 ldr r1, [r7, #0] 80116d4: 6878 ldr r0, [r7, #4] 80116d6: f000 fd0f bl 80120f8 break; 80116da: e009 b.n 80116f0 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 80116dc: 6839 ldr r1, [r7, #0] 80116de: 6878 ldr r0, [r7, #4] 80116e0: f000 fd33 bl 801214a break; 80116e4: e004 b.n 80116f0 default: USBD_CtlError(pdev, req); 80116e6: 6839 ldr r1, [r7, #0] 80116e8: 6878 ldr r0, [r7, #4] 80116ea: f000 fd8a bl 8012202 break; 80116ee: bf00 nop } break; 80116f0: e004 b.n 80116fc default: USBD_CtlError(pdev, req); 80116f2: 6839 ldr r1, [r7, #0] 80116f4: 6878 ldr r0, [r7, #4] 80116f6: f000 fd84 bl 8012202 break; 80116fa: bf00 nop } return ret; 80116fc: 7bfb ldrb r3, [r7, #15] } 80116fe: 4618 mov r0, r3 8011700: 3710 adds r7, #16 8011702: 46bd mov sp, r7 8011704: bd80 pop {r7, pc} 8011706: bf00 nop 08011708 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8011708: b580 push {r7, lr} 801170a: b084 sub sp, #16 801170c: af00 add r7, sp, #0 801170e: 6078 str r0, [r7, #4] 8011710: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8011712: 2300 movs r3, #0 8011714: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 8011716: 683b ldr r3, [r7, #0] 8011718: 781b ldrb r3, [r3, #0] 801171a: f003 0360 and.w r3, r3, #96 @ 0x60 801171e: 2b40 cmp r3, #64 @ 0x40 8011720: d005 beq.n 801172e 8011722: 2b40 cmp r3, #64 @ 0x40 8011724: d852 bhi.n 80117cc 8011726: 2b00 cmp r3, #0 8011728: d001 beq.n 801172e 801172a: 2b20 cmp r3, #32 801172c: d14e bne.n 80117cc { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 801172e: 687b ldr r3, [r7, #4] 8011730: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011734: b2db uxtb r3, r3 8011736: 3b01 subs r3, #1 8011738: 2b02 cmp r3, #2 801173a: d840 bhi.n 80117be { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 801173c: 683b ldr r3, [r7, #0] 801173e: 889b ldrh r3, [r3, #4] 8011740: b2db uxtb r3, r3 8011742: 2b01 cmp r3, #1 8011744: d836 bhi.n 80117b4 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 8011746: 683b ldr r3, [r7, #0] 8011748: 889b ldrh r3, [r3, #4] 801174a: b2db uxtb r3, r3 801174c: 4619 mov r1, r3 801174e: 6878 ldr r0, [r7, #4] 8011750: f7ff feda bl 8011508 8011754: 4603 mov r3, r0 8011756: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8011758: 7bbb ldrb r3, [r7, #14] 801175a: 2bff cmp r3, #255 @ 0xff 801175c: d01d beq.n 801179a 801175e: 7bbb ldrb r3, [r7, #14] 8011760: 2b00 cmp r3, #0 8011762: d11a bne.n 801179a { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8011764: 7bba ldrb r2, [r7, #14] 8011766: 687b ldr r3, [r7, #4] 8011768: 32ae adds r2, #174 @ 0xae 801176a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801176e: 689b ldr r3, [r3, #8] 8011770: 2b00 cmp r3, #0 8011772: d00f beq.n 8011794 { pdev->classId = idx; 8011774: 7bba ldrb r2, [r7, #14] 8011776: 687b ldr r3, [r7, #4] 8011778: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 801177c: 7bba ldrb r2, [r7, #14] 801177e: 687b ldr r3, [r7, #4] 8011780: 32ae adds r2, #174 @ 0xae 8011782: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011786: 689b ldr r3, [r3, #8] 8011788: 6839 ldr r1, [r7, #0] 801178a: 6878 ldr r0, [r7, #4] 801178c: 4798 blx r3 801178e: 4603 mov r3, r0 8011790: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8011792: e004 b.n 801179e } else { /* should never reach this condition */ ret = USBD_FAIL; 8011794: 2303 movs r3, #3 8011796: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8011798: e001 b.n 801179e } } else { /* No relative interface found */ ret = USBD_FAIL; 801179a: 2303 movs r3, #3 801179c: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 801179e: 683b ldr r3, [r7, #0] 80117a0: 88db ldrh r3, [r3, #6] 80117a2: 2b00 cmp r3, #0 80117a4: d110 bne.n 80117c8 80117a6: 7bfb ldrb r3, [r7, #15] 80117a8: 2b00 cmp r3, #0 80117aa: d10d bne.n 80117c8 { (void)USBD_CtlSendStatus(pdev); 80117ac: 6878 ldr r0, [r7, #4] 80117ae: f000 fe06 bl 80123be } else { USBD_CtlError(pdev, req); } break; 80117b2: e009 b.n 80117c8 USBD_CtlError(pdev, req); 80117b4: 6839 ldr r1, [r7, #0] 80117b6: 6878 ldr r0, [r7, #4] 80117b8: f000 fd23 bl 8012202 break; 80117bc: e004 b.n 80117c8 default: USBD_CtlError(pdev, req); 80117be: 6839 ldr r1, [r7, #0] 80117c0: 6878 ldr r0, [r7, #4] 80117c2: f000 fd1e bl 8012202 break; 80117c6: e000 b.n 80117ca break; 80117c8: bf00 nop } break; 80117ca: e004 b.n 80117d6 default: USBD_CtlError(pdev, req); 80117cc: 6839 ldr r1, [r7, #0] 80117ce: 6878 ldr r0, [r7, #4] 80117d0: f000 fd17 bl 8012202 break; 80117d4: bf00 nop } return ret; 80117d6: 7bfb ldrb r3, [r7, #15] } 80117d8: 4618 mov r0, r3 80117da: 3710 adds r7, #16 80117dc: 46bd mov sp, r7 80117de: bd80 pop {r7, pc} 080117e0 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80117e0: b580 push {r7, lr} 80117e2: b084 sub sp, #16 80117e4: af00 add r7, sp, #0 80117e6: 6078 str r0, [r7, #4] 80117e8: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 80117ea: 2300 movs r3, #0 80117ec: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 80117ee: 683b ldr r3, [r7, #0] 80117f0: 889b ldrh r3, [r3, #4] 80117f2: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 80117f4: 683b ldr r3, [r7, #0] 80117f6: 781b ldrb r3, [r3, #0] 80117f8: f003 0360 and.w r3, r3, #96 @ 0x60 80117fc: 2b40 cmp r3, #64 @ 0x40 80117fe: d007 beq.n 8011810 8011800: 2b40 cmp r3, #64 @ 0x40 8011802: f200 8181 bhi.w 8011b08 8011806: 2b00 cmp r3, #0 8011808: d02a beq.n 8011860 801180a: 2b20 cmp r3, #32 801180c: f040 817c bne.w 8011b08 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 8011810: 7bbb ldrb r3, [r7, #14] 8011812: 4619 mov r1, r3 8011814: 6878 ldr r0, [r7, #4] 8011816: f7ff fe84 bl 8011522 801181a: 4603 mov r3, r0 801181c: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 801181e: 7b7b ldrb r3, [r7, #13] 8011820: 2bff cmp r3, #255 @ 0xff 8011822: f000 8176 beq.w 8011b12 8011826: 7b7b ldrb r3, [r7, #13] 8011828: 2b00 cmp r3, #0 801182a: f040 8172 bne.w 8011b12 { pdev->classId = idx; 801182e: 7b7a ldrb r2, [r7, #13] 8011830: 687b ldr r3, [r7, #4] 8011832: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8011836: 7b7a ldrb r2, [r7, #13] 8011838: 687b ldr r3, [r7, #4] 801183a: 32ae adds r2, #174 @ 0xae 801183c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011840: 689b ldr r3, [r3, #8] 8011842: 2b00 cmp r3, #0 8011844: f000 8165 beq.w 8011b12 { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 8011848: 7b7a ldrb r2, [r7, #13] 801184a: 687b ldr r3, [r7, #4] 801184c: 32ae adds r2, #174 @ 0xae 801184e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011852: 689b ldr r3, [r3, #8] 8011854: 6839 ldr r1, [r7, #0] 8011856: 6878 ldr r0, [r7, #4] 8011858: 4798 blx r3 801185a: 4603 mov r3, r0 801185c: 73fb strb r3, [r7, #15] } } break; 801185e: e158 b.n 8011b12 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8011860: 683b ldr r3, [r7, #0] 8011862: 785b ldrb r3, [r3, #1] 8011864: 2b03 cmp r3, #3 8011866: d008 beq.n 801187a 8011868: 2b03 cmp r3, #3 801186a: f300 8147 bgt.w 8011afc 801186e: 2b00 cmp r3, #0 8011870: f000 809b beq.w 80119aa 8011874: 2b01 cmp r3, #1 8011876: d03c beq.n 80118f2 8011878: e140 b.n 8011afc { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 801187a: 687b ldr r3, [r7, #4] 801187c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011880: b2db uxtb r3, r3 8011882: 2b02 cmp r3, #2 8011884: d002 beq.n 801188c 8011886: 2b03 cmp r3, #3 8011888: d016 beq.n 80118b8 801188a: e02c b.n 80118e6 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 801188c: 7bbb ldrb r3, [r7, #14] 801188e: 2b00 cmp r3, #0 8011890: d00d beq.n 80118ae 8011892: 7bbb ldrb r3, [r7, #14] 8011894: 2b80 cmp r3, #128 @ 0x80 8011896: d00a beq.n 80118ae { (void)USBD_LL_StallEP(pdev, ep_addr); 8011898: 7bbb ldrb r3, [r7, #14] 801189a: 4619 mov r1, r3 801189c: 6878 ldr r0, [r7, #4] 801189e: f006 ff05 bl 80186ac (void)USBD_LL_StallEP(pdev, 0x80U); 80118a2: 2180 movs r1, #128 @ 0x80 80118a4: 6878 ldr r0, [r7, #4] 80118a6: f006 ff01 bl 80186ac 80118aa: bf00 nop } else { USBD_CtlError(pdev, req); } break; 80118ac: e020 b.n 80118f0 USBD_CtlError(pdev, req); 80118ae: 6839 ldr r1, [r7, #0] 80118b0: 6878 ldr r0, [r7, #4] 80118b2: f000 fca6 bl 8012202 break; 80118b6: e01b b.n 80118f0 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80118b8: 683b ldr r3, [r7, #0] 80118ba: 885b ldrh r3, [r3, #2] 80118bc: 2b00 cmp r3, #0 80118be: d10e bne.n 80118de { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 80118c0: 7bbb ldrb r3, [r7, #14] 80118c2: 2b00 cmp r3, #0 80118c4: d00b beq.n 80118de 80118c6: 7bbb ldrb r3, [r7, #14] 80118c8: 2b80 cmp r3, #128 @ 0x80 80118ca: d008 beq.n 80118de 80118cc: 683b ldr r3, [r7, #0] 80118ce: 88db ldrh r3, [r3, #6] 80118d0: 2b00 cmp r3, #0 80118d2: d104 bne.n 80118de { (void)USBD_LL_StallEP(pdev, ep_addr); 80118d4: 7bbb ldrb r3, [r7, #14] 80118d6: 4619 mov r1, r3 80118d8: 6878 ldr r0, [r7, #4] 80118da: f006 fee7 bl 80186ac } } (void)USBD_CtlSendStatus(pdev); 80118de: 6878 ldr r0, [r7, #4] 80118e0: f000 fd6d bl 80123be break; 80118e4: e004 b.n 80118f0 default: USBD_CtlError(pdev, req); 80118e6: 6839 ldr r1, [r7, #0] 80118e8: 6878 ldr r0, [r7, #4] 80118ea: f000 fc8a bl 8012202 break; 80118ee: bf00 nop } break; 80118f0: e109 b.n 8011b06 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 80118f2: 687b ldr r3, [r7, #4] 80118f4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80118f8: b2db uxtb r3, r3 80118fa: 2b02 cmp r3, #2 80118fc: d002 beq.n 8011904 80118fe: 2b03 cmp r3, #3 8011900: d016 beq.n 8011930 8011902: e04b b.n 801199c { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8011904: 7bbb ldrb r3, [r7, #14] 8011906: 2b00 cmp r3, #0 8011908: d00d beq.n 8011926 801190a: 7bbb ldrb r3, [r7, #14] 801190c: 2b80 cmp r3, #128 @ 0x80 801190e: d00a beq.n 8011926 { (void)USBD_LL_StallEP(pdev, ep_addr); 8011910: 7bbb ldrb r3, [r7, #14] 8011912: 4619 mov r1, r3 8011914: 6878 ldr r0, [r7, #4] 8011916: f006 fec9 bl 80186ac (void)USBD_LL_StallEP(pdev, 0x80U); 801191a: 2180 movs r1, #128 @ 0x80 801191c: 6878 ldr r0, [r7, #4] 801191e: f006 fec5 bl 80186ac 8011922: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8011924: e040 b.n 80119a8 USBD_CtlError(pdev, req); 8011926: 6839 ldr r1, [r7, #0] 8011928: 6878 ldr r0, [r7, #4] 801192a: f000 fc6a bl 8012202 break; 801192e: e03b b.n 80119a8 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8011930: 683b ldr r3, [r7, #0] 8011932: 885b ldrh r3, [r3, #2] 8011934: 2b00 cmp r3, #0 8011936: d136 bne.n 80119a6 { if ((ep_addr & 0x7FU) != 0x00U) 8011938: 7bbb ldrb r3, [r7, #14] 801193a: f003 037f and.w r3, r3, #127 @ 0x7f 801193e: 2b00 cmp r3, #0 8011940: d004 beq.n 801194c { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 8011942: 7bbb ldrb r3, [r7, #14] 8011944: 4619 mov r1, r3 8011946: 6878 ldr r0, [r7, #4] 8011948: f006 fecf bl 80186ea } (void)USBD_CtlSendStatus(pdev); 801194c: 6878 ldr r0, [r7, #4] 801194e: f000 fd36 bl 80123be /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 8011952: 7bbb ldrb r3, [r7, #14] 8011954: 4619 mov r1, r3 8011956: 6878 ldr r0, [r7, #4] 8011958: f7ff fde3 bl 8011522 801195c: 4603 mov r3, r0 801195e: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8011960: 7b7b ldrb r3, [r7, #13] 8011962: 2bff cmp r3, #255 @ 0xff 8011964: d01f beq.n 80119a6 8011966: 7b7b ldrb r3, [r7, #13] 8011968: 2b00 cmp r3, #0 801196a: d11c bne.n 80119a6 { pdev->classId = idx; 801196c: 7b7a ldrb r2, [r7, #13] 801196e: 687b ldr r3, [r7, #4] 8011970: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8011974: 7b7a ldrb r2, [r7, #13] 8011976: 687b ldr r3, [r7, #4] 8011978: 32ae adds r2, #174 @ 0xae 801197a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801197e: 689b ldr r3, [r3, #8] 8011980: 2b00 cmp r3, #0 8011982: d010 beq.n 80119a6 { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8011984: 7b7a ldrb r2, [r7, #13] 8011986: 687b ldr r3, [r7, #4] 8011988: 32ae adds r2, #174 @ 0xae 801198a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801198e: 689b ldr r3, [r3, #8] 8011990: 6839 ldr r1, [r7, #0] 8011992: 6878 ldr r0, [r7, #4] 8011994: 4798 blx r3 8011996: 4603 mov r3, r0 8011998: 73fb strb r3, [r7, #15] } } } break; 801199a: e004 b.n 80119a6 default: USBD_CtlError(pdev, req); 801199c: 6839 ldr r1, [r7, #0] 801199e: 6878 ldr r0, [r7, #4] 80119a0: f000 fc2f bl 8012202 break; 80119a4: e000 b.n 80119a8 break; 80119a6: bf00 nop } break; 80119a8: e0ad b.n 8011b06 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 80119aa: 687b ldr r3, [r7, #4] 80119ac: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80119b0: b2db uxtb r3, r3 80119b2: 2b02 cmp r3, #2 80119b4: d002 beq.n 80119bc 80119b6: 2b03 cmp r3, #3 80119b8: d033 beq.n 8011a22 80119ba: e099 b.n 8011af0 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80119bc: 7bbb ldrb r3, [r7, #14] 80119be: 2b00 cmp r3, #0 80119c0: d007 beq.n 80119d2 80119c2: 7bbb ldrb r3, [r7, #14] 80119c4: 2b80 cmp r3, #128 @ 0x80 80119c6: d004 beq.n 80119d2 { USBD_CtlError(pdev, req); 80119c8: 6839 ldr r1, [r7, #0] 80119ca: 6878 ldr r0, [r7, #4] 80119cc: f000 fc19 bl 8012202 break; 80119d0: e093 b.n 8011afa } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80119d2: f997 300e ldrsb.w r3, [r7, #14] 80119d6: 2b00 cmp r3, #0 80119d8: da0b bge.n 80119f2 80119da: 7bbb ldrb r3, [r7, #14] 80119dc: f003 027f and.w r2, r3, #127 @ 0x7f 80119e0: 4613 mov r3, r2 80119e2: 009b lsls r3, r3, #2 80119e4: 4413 add r3, r2 80119e6: 009b lsls r3, r3, #2 80119e8: 3310 adds r3, #16 80119ea: 687a ldr r2, [r7, #4] 80119ec: 4413 add r3, r2 80119ee: 3304 adds r3, #4 80119f0: e00b b.n 8011a0a &pdev->ep_out[ep_addr & 0x7FU]; 80119f2: 7bbb ldrb r3, [r7, #14] 80119f4: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80119f8: 4613 mov r3, r2 80119fa: 009b lsls r3, r3, #2 80119fc: 4413 add r3, r2 80119fe: 009b lsls r3, r3, #2 8011a00: f503 73a8 add.w r3, r3, #336 @ 0x150 8011a04: 687a ldr r2, [r7, #4] 8011a06: 4413 add r3, r2 8011a08: 3304 adds r3, #4 8011a0a: 60bb str r3, [r7, #8] pep->status = 0x0000U; 8011a0c: 68bb ldr r3, [r7, #8] 8011a0e: 2200 movs r2, #0 8011a10: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8011a12: 68bb ldr r3, [r7, #8] 8011a14: 330e adds r3, #14 8011a16: 2202 movs r2, #2 8011a18: 4619 mov r1, r3 8011a1a: 6878 ldr r0, [r7, #4] 8011a1c: f000 fc6e bl 80122fc break; 8011a20: e06b b.n 8011afa case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 8011a22: f997 300e ldrsb.w r3, [r7, #14] 8011a26: 2b00 cmp r3, #0 8011a28: da11 bge.n 8011a4e { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 8011a2a: 7bbb ldrb r3, [r7, #14] 8011a2c: f003 020f and.w r2, r3, #15 8011a30: 6879 ldr r1, [r7, #4] 8011a32: 4613 mov r3, r2 8011a34: 009b lsls r3, r3, #2 8011a36: 4413 add r3, r2 8011a38: 009b lsls r3, r3, #2 8011a3a: 440b add r3, r1 8011a3c: 3323 adds r3, #35 @ 0x23 8011a3e: 781b ldrb r3, [r3, #0] 8011a40: 2b00 cmp r3, #0 8011a42: d117 bne.n 8011a74 { USBD_CtlError(pdev, req); 8011a44: 6839 ldr r1, [r7, #0] 8011a46: 6878 ldr r0, [r7, #4] 8011a48: f000 fbdb bl 8012202 break; 8011a4c: e055 b.n 8011afa } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 8011a4e: 7bbb ldrb r3, [r7, #14] 8011a50: f003 020f and.w r2, r3, #15 8011a54: 6879 ldr r1, [r7, #4] 8011a56: 4613 mov r3, r2 8011a58: 009b lsls r3, r3, #2 8011a5a: 4413 add r3, r2 8011a5c: 009b lsls r3, r3, #2 8011a5e: 440b add r3, r1 8011a60: f203 1363 addw r3, r3, #355 @ 0x163 8011a64: 781b ldrb r3, [r3, #0] 8011a66: 2b00 cmp r3, #0 8011a68: d104 bne.n 8011a74 { USBD_CtlError(pdev, req); 8011a6a: 6839 ldr r1, [r7, #0] 8011a6c: 6878 ldr r0, [r7, #4] 8011a6e: f000 fbc8 bl 8012202 break; 8011a72: e042 b.n 8011afa } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8011a74: f997 300e ldrsb.w r3, [r7, #14] 8011a78: 2b00 cmp r3, #0 8011a7a: da0b bge.n 8011a94 8011a7c: 7bbb ldrb r3, [r7, #14] 8011a7e: f003 027f and.w r2, r3, #127 @ 0x7f 8011a82: 4613 mov r3, r2 8011a84: 009b lsls r3, r3, #2 8011a86: 4413 add r3, r2 8011a88: 009b lsls r3, r3, #2 8011a8a: 3310 adds r3, #16 8011a8c: 687a ldr r2, [r7, #4] 8011a8e: 4413 add r3, r2 8011a90: 3304 adds r3, #4 8011a92: e00b b.n 8011aac &pdev->ep_out[ep_addr & 0x7FU]; 8011a94: 7bbb ldrb r3, [r7, #14] 8011a96: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8011a9a: 4613 mov r3, r2 8011a9c: 009b lsls r3, r3, #2 8011a9e: 4413 add r3, r2 8011aa0: 009b lsls r3, r3, #2 8011aa2: f503 73a8 add.w r3, r3, #336 @ 0x150 8011aa6: 687a ldr r2, [r7, #4] 8011aa8: 4413 add r3, r2 8011aaa: 3304 adds r3, #4 8011aac: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 8011aae: 7bbb ldrb r3, [r7, #14] 8011ab0: 2b00 cmp r3, #0 8011ab2: d002 beq.n 8011aba 8011ab4: 7bbb ldrb r3, [r7, #14] 8011ab6: 2b80 cmp r3, #128 @ 0x80 8011ab8: d103 bne.n 8011ac2 { pep->status = 0x0000U; 8011aba: 68bb ldr r3, [r7, #8] 8011abc: 2200 movs r2, #0 8011abe: 739a strb r2, [r3, #14] 8011ac0: e00e b.n 8011ae0 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 8011ac2: 7bbb ldrb r3, [r7, #14] 8011ac4: 4619 mov r1, r3 8011ac6: 6878 ldr r0, [r7, #4] 8011ac8: f006 fe2e bl 8018728 8011acc: 4603 mov r3, r0 8011ace: 2b00 cmp r3, #0 8011ad0: d003 beq.n 8011ada { pep->status = 0x0001U; 8011ad2: 68bb ldr r3, [r7, #8] 8011ad4: 2201 movs r2, #1 8011ad6: 739a strb r2, [r3, #14] 8011ad8: e002 b.n 8011ae0 } else { pep->status = 0x0000U; 8011ada: 68bb ldr r3, [r7, #8] 8011adc: 2200 movs r2, #0 8011ade: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8011ae0: 68bb ldr r3, [r7, #8] 8011ae2: 330e adds r3, #14 8011ae4: 2202 movs r2, #2 8011ae6: 4619 mov r1, r3 8011ae8: 6878 ldr r0, [r7, #4] 8011aea: f000 fc07 bl 80122fc break; 8011aee: e004 b.n 8011afa default: USBD_CtlError(pdev, req); 8011af0: 6839 ldr r1, [r7, #0] 8011af2: 6878 ldr r0, [r7, #4] 8011af4: f000 fb85 bl 8012202 break; 8011af8: bf00 nop } break; 8011afa: e004 b.n 8011b06 default: USBD_CtlError(pdev, req); 8011afc: 6839 ldr r1, [r7, #0] 8011afe: 6878 ldr r0, [r7, #4] 8011b00: f000 fb7f bl 8012202 break; 8011b04: bf00 nop } break; 8011b06: e005 b.n 8011b14 default: USBD_CtlError(pdev, req); 8011b08: 6839 ldr r1, [r7, #0] 8011b0a: 6878 ldr r0, [r7, #4] 8011b0c: f000 fb79 bl 8012202 break; 8011b10: e000 b.n 8011b14 break; 8011b12: bf00 nop } return ret; 8011b14: 7bfb ldrb r3, [r7, #15] } 8011b16: 4618 mov r0, r3 8011b18: 3710 adds r7, #16 8011b1a: 46bd mov sp, r7 8011b1c: bd80 pop {r7, pc} ... 08011b20 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8011b20: b580 push {r7, lr} 8011b22: b084 sub sp, #16 8011b24: af00 add r7, sp, #0 8011b26: 6078 str r0, [r7, #4] 8011b28: 6039 str r1, [r7, #0] uint16_t len = 0U; 8011b2a: 2300 movs r3, #0 8011b2c: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 8011b2e: 2300 movs r3, #0 8011b30: 60fb str r3, [r7, #12] uint8_t err = 0U; 8011b32: 2300 movs r3, #0 8011b34: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 8011b36: 683b ldr r3, [r7, #0] 8011b38: 885b ldrh r3, [r3, #2] 8011b3a: 0a1b lsrs r3, r3, #8 8011b3c: b29b uxth r3, r3 8011b3e: 3b01 subs r3, #1 8011b40: 2b0e cmp r3, #14 8011b42: f200 8152 bhi.w 8011dea 8011b46: a201 add r2, pc, #4 @ (adr r2, 8011b4c ) 8011b48: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011b4c: 08011bbd .word 0x08011bbd 8011b50: 08011bd5 .word 0x08011bd5 8011b54: 08011c15 .word 0x08011c15 8011b58: 08011deb .word 0x08011deb 8011b5c: 08011deb .word 0x08011deb 8011b60: 08011d8b .word 0x08011d8b 8011b64: 08011db7 .word 0x08011db7 8011b68: 08011deb .word 0x08011deb 8011b6c: 08011deb .word 0x08011deb 8011b70: 08011deb .word 0x08011deb 8011b74: 08011deb .word 0x08011deb 8011b78: 08011deb .word 0x08011deb 8011b7c: 08011deb .word 0x08011deb 8011b80: 08011deb .word 0x08011deb 8011b84: 08011b89 .word 0x08011b89 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 8011b88: 687b ldr r3, [r7, #4] 8011b8a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011b8e: 69db ldr r3, [r3, #28] 8011b90: 2b00 cmp r3, #0 8011b92: d00b beq.n 8011bac { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 8011b94: 687b ldr r3, [r7, #4] 8011b96: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011b9a: 69db ldr r3, [r3, #28] 8011b9c: 687a ldr r2, [r7, #4] 8011b9e: 7c12 ldrb r2, [r2, #16] 8011ba0: f107 0108 add.w r1, r7, #8 8011ba4: 4610 mov r0, r2 8011ba6: 4798 blx r3 8011ba8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8011baa: e126 b.n 8011dfa USBD_CtlError(pdev, req); 8011bac: 6839 ldr r1, [r7, #0] 8011bae: 6878 ldr r0, [r7, #4] 8011bb0: f000 fb27 bl 8012202 err++; 8011bb4: 7afb ldrb r3, [r7, #11] 8011bb6: 3301 adds r3, #1 8011bb8: 72fb strb r3, [r7, #11] break; 8011bba: e11e b.n 8011dfa #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 8011bbc: 687b ldr r3, [r7, #4] 8011bbe: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011bc2: 681b ldr r3, [r3, #0] 8011bc4: 687a ldr r2, [r7, #4] 8011bc6: 7c12 ldrb r2, [r2, #16] 8011bc8: f107 0108 add.w r1, r7, #8 8011bcc: 4610 mov r0, r2 8011bce: 4798 blx r3 8011bd0: 60f8 str r0, [r7, #12] break; 8011bd2: e112 b.n 8011dfa case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8011bd4: 687b ldr r3, [r7, #4] 8011bd6: 7c1b ldrb r3, [r3, #16] 8011bd8: 2b00 cmp r3, #0 8011bda: d10d bne.n 8011bf8 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 8011bdc: 687b ldr r3, [r7, #4] 8011bde: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011be2: 6a9b ldr r3, [r3, #40] @ 0x28 8011be4: f107 0208 add.w r2, r7, #8 8011be8: 4610 mov r0, r2 8011bea: 4798 blx r3 8011bec: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8011bee: 68fb ldr r3, [r7, #12] 8011bf0: 3301 adds r3, #1 8011bf2: 2202 movs r2, #2 8011bf4: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 8011bf6: e100 b.n 8011dfa pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 8011bf8: 687b ldr r3, [r7, #4] 8011bfa: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011bfe: 6adb ldr r3, [r3, #44] @ 0x2c 8011c00: f107 0208 add.w r2, r7, #8 8011c04: 4610 mov r0, r2 8011c06: 4798 blx r3 8011c08: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8011c0a: 68fb ldr r3, [r7, #12] 8011c0c: 3301 adds r3, #1 8011c0e: 2202 movs r2, #2 8011c10: 701a strb r2, [r3, #0] break; 8011c12: e0f2 b.n 8011dfa case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 8011c14: 683b ldr r3, [r7, #0] 8011c16: 885b ldrh r3, [r3, #2] 8011c18: b2db uxtb r3, r3 8011c1a: 2b05 cmp r3, #5 8011c1c: f200 80ac bhi.w 8011d78 8011c20: a201 add r2, pc, #4 @ (adr r2, 8011c28 ) 8011c22: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011c26: bf00 nop 8011c28: 08011c41 .word 0x08011c41 8011c2c: 08011c75 .word 0x08011c75 8011c30: 08011ca9 .word 0x08011ca9 8011c34: 08011cdd .word 0x08011cdd 8011c38: 08011d11 .word 0x08011d11 8011c3c: 08011d45 .word 0x08011d45 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 8011c40: 687b ldr r3, [r7, #4] 8011c42: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011c46: 685b ldr r3, [r3, #4] 8011c48: 2b00 cmp r3, #0 8011c4a: d00b beq.n 8011c64 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 8011c4c: 687b ldr r3, [r7, #4] 8011c4e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011c52: 685b ldr r3, [r3, #4] 8011c54: 687a ldr r2, [r7, #4] 8011c56: 7c12 ldrb r2, [r2, #16] 8011c58: f107 0108 add.w r1, r7, #8 8011c5c: 4610 mov r0, r2 8011c5e: 4798 blx r3 8011c60: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8011c62: e091 b.n 8011d88 USBD_CtlError(pdev, req); 8011c64: 6839 ldr r1, [r7, #0] 8011c66: 6878 ldr r0, [r7, #4] 8011c68: f000 facb bl 8012202 err++; 8011c6c: 7afb ldrb r3, [r7, #11] 8011c6e: 3301 adds r3, #1 8011c70: 72fb strb r3, [r7, #11] break; 8011c72: e089 b.n 8011d88 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 8011c74: 687b ldr r3, [r7, #4] 8011c76: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011c7a: 689b ldr r3, [r3, #8] 8011c7c: 2b00 cmp r3, #0 8011c7e: d00b beq.n 8011c98 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 8011c80: 687b ldr r3, [r7, #4] 8011c82: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011c86: 689b ldr r3, [r3, #8] 8011c88: 687a ldr r2, [r7, #4] 8011c8a: 7c12 ldrb r2, [r2, #16] 8011c8c: f107 0108 add.w r1, r7, #8 8011c90: 4610 mov r0, r2 8011c92: 4798 blx r3 8011c94: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8011c96: e077 b.n 8011d88 USBD_CtlError(pdev, req); 8011c98: 6839 ldr r1, [r7, #0] 8011c9a: 6878 ldr r0, [r7, #4] 8011c9c: f000 fab1 bl 8012202 err++; 8011ca0: 7afb ldrb r3, [r7, #11] 8011ca2: 3301 adds r3, #1 8011ca4: 72fb strb r3, [r7, #11] break; 8011ca6: e06f b.n 8011d88 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 8011ca8: 687b ldr r3, [r7, #4] 8011caa: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011cae: 68db ldr r3, [r3, #12] 8011cb0: 2b00 cmp r3, #0 8011cb2: d00b beq.n 8011ccc { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 8011cb4: 687b ldr r3, [r7, #4] 8011cb6: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011cba: 68db ldr r3, [r3, #12] 8011cbc: 687a ldr r2, [r7, #4] 8011cbe: 7c12 ldrb r2, [r2, #16] 8011cc0: f107 0108 add.w r1, r7, #8 8011cc4: 4610 mov r0, r2 8011cc6: 4798 blx r3 8011cc8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8011cca: e05d b.n 8011d88 USBD_CtlError(pdev, req); 8011ccc: 6839 ldr r1, [r7, #0] 8011cce: 6878 ldr r0, [r7, #4] 8011cd0: f000 fa97 bl 8012202 err++; 8011cd4: 7afb ldrb r3, [r7, #11] 8011cd6: 3301 adds r3, #1 8011cd8: 72fb strb r3, [r7, #11] break; 8011cda: e055 b.n 8011d88 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 8011cdc: 687b ldr r3, [r7, #4] 8011cde: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011ce2: 691b ldr r3, [r3, #16] 8011ce4: 2b00 cmp r3, #0 8011ce6: d00b beq.n 8011d00 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 8011ce8: 687b ldr r3, [r7, #4] 8011cea: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011cee: 691b ldr r3, [r3, #16] 8011cf0: 687a ldr r2, [r7, #4] 8011cf2: 7c12 ldrb r2, [r2, #16] 8011cf4: f107 0108 add.w r1, r7, #8 8011cf8: 4610 mov r0, r2 8011cfa: 4798 blx r3 8011cfc: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8011cfe: e043 b.n 8011d88 USBD_CtlError(pdev, req); 8011d00: 6839 ldr r1, [r7, #0] 8011d02: 6878 ldr r0, [r7, #4] 8011d04: f000 fa7d bl 8012202 err++; 8011d08: 7afb ldrb r3, [r7, #11] 8011d0a: 3301 adds r3, #1 8011d0c: 72fb strb r3, [r7, #11] break; 8011d0e: e03b b.n 8011d88 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 8011d10: 687b ldr r3, [r7, #4] 8011d12: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011d16: 695b ldr r3, [r3, #20] 8011d18: 2b00 cmp r3, #0 8011d1a: d00b beq.n 8011d34 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 8011d1c: 687b ldr r3, [r7, #4] 8011d1e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011d22: 695b ldr r3, [r3, #20] 8011d24: 687a ldr r2, [r7, #4] 8011d26: 7c12 ldrb r2, [r2, #16] 8011d28: f107 0108 add.w r1, r7, #8 8011d2c: 4610 mov r0, r2 8011d2e: 4798 blx r3 8011d30: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8011d32: e029 b.n 8011d88 USBD_CtlError(pdev, req); 8011d34: 6839 ldr r1, [r7, #0] 8011d36: 6878 ldr r0, [r7, #4] 8011d38: f000 fa63 bl 8012202 err++; 8011d3c: 7afb ldrb r3, [r7, #11] 8011d3e: 3301 adds r3, #1 8011d40: 72fb strb r3, [r7, #11] break; 8011d42: e021 b.n 8011d88 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8011d44: 687b ldr r3, [r7, #4] 8011d46: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011d4a: 699b ldr r3, [r3, #24] 8011d4c: 2b00 cmp r3, #0 8011d4e: d00b beq.n 8011d68 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8011d50: 687b ldr r3, [r7, #4] 8011d52: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8011d56: 699b ldr r3, [r3, #24] 8011d58: 687a ldr r2, [r7, #4] 8011d5a: 7c12 ldrb r2, [r2, #16] 8011d5c: f107 0108 add.w r1, r7, #8 8011d60: 4610 mov r0, r2 8011d62: 4798 blx r3 8011d64: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8011d66: e00f b.n 8011d88 USBD_CtlError(pdev, req); 8011d68: 6839 ldr r1, [r7, #0] 8011d6a: 6878 ldr r0, [r7, #4] 8011d6c: f000 fa49 bl 8012202 err++; 8011d70: 7afb ldrb r3, [r7, #11] 8011d72: 3301 adds r3, #1 8011d74: 72fb strb r3, [r7, #11] break; 8011d76: e007 b.n 8011d88 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8011d78: 6839 ldr r1, [r7, #0] 8011d7a: 6878 ldr r0, [r7, #4] 8011d7c: f000 fa41 bl 8012202 err++; 8011d80: 7afb ldrb r3, [r7, #11] 8011d82: 3301 adds r3, #1 8011d84: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 8011d86: bf00 nop } break; 8011d88: e037 b.n 8011dfa case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 8011d8a: 687b ldr r3, [r7, #4] 8011d8c: 7c1b ldrb r3, [r3, #16] 8011d8e: 2b00 cmp r3, #0 8011d90: d109 bne.n 8011da6 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 8011d92: 687b ldr r3, [r7, #4] 8011d94: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011d98: 6b5b ldr r3, [r3, #52] @ 0x34 8011d9a: f107 0208 add.w r2, r7, #8 8011d9e: 4610 mov r0, r2 8011da0: 4798 blx r3 8011da2: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8011da4: e029 b.n 8011dfa USBD_CtlError(pdev, req); 8011da6: 6839 ldr r1, [r7, #0] 8011da8: 6878 ldr r0, [r7, #4] 8011daa: f000 fa2a bl 8012202 err++; 8011dae: 7afb ldrb r3, [r7, #11] 8011db0: 3301 adds r3, #1 8011db2: 72fb strb r3, [r7, #11] break; 8011db4: e021 b.n 8011dfa case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8011db6: 687b ldr r3, [r7, #4] 8011db8: 7c1b ldrb r3, [r3, #16] 8011dba: 2b00 cmp r3, #0 8011dbc: d10d bne.n 8011dda pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 8011dbe: 687b ldr r3, [r7, #4] 8011dc0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011dc4: 6b1b ldr r3, [r3, #48] @ 0x30 8011dc6: f107 0208 add.w r2, r7, #8 8011dca: 4610 mov r0, r2 8011dcc: 4798 blx r3 8011dce: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 8011dd0: 68fb ldr r3, [r7, #12] 8011dd2: 3301 adds r3, #1 8011dd4: 2207 movs r2, #7 8011dd6: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 8011dd8: e00f b.n 8011dfa USBD_CtlError(pdev, req); 8011dda: 6839 ldr r1, [r7, #0] 8011ddc: 6878 ldr r0, [r7, #4] 8011dde: f000 fa10 bl 8012202 err++; 8011de2: 7afb ldrb r3, [r7, #11] 8011de4: 3301 adds r3, #1 8011de6: 72fb strb r3, [r7, #11] break; 8011de8: e007 b.n 8011dfa default: USBD_CtlError(pdev, req); 8011dea: 6839 ldr r1, [r7, #0] 8011dec: 6878 ldr r0, [r7, #4] 8011dee: f000 fa08 bl 8012202 err++; 8011df2: 7afb ldrb r3, [r7, #11] 8011df4: 3301 adds r3, #1 8011df6: 72fb strb r3, [r7, #11] break; 8011df8: bf00 nop } if (err != 0U) 8011dfa: 7afb ldrb r3, [r7, #11] 8011dfc: 2b00 cmp r3, #0 8011dfe: d11e bne.n 8011e3e { return; } if (req->wLength != 0U) 8011e00: 683b ldr r3, [r7, #0] 8011e02: 88db ldrh r3, [r3, #6] 8011e04: 2b00 cmp r3, #0 8011e06: d016 beq.n 8011e36 { if (len != 0U) 8011e08: 893b ldrh r3, [r7, #8] 8011e0a: 2b00 cmp r3, #0 8011e0c: d00e beq.n 8011e2c { len = MIN(len, req->wLength); 8011e0e: 683b ldr r3, [r7, #0] 8011e10: 88da ldrh r2, [r3, #6] 8011e12: 893b ldrh r3, [r7, #8] 8011e14: 4293 cmp r3, r2 8011e16: bf28 it cs 8011e18: 4613 movcs r3, r2 8011e1a: b29b uxth r3, r3 8011e1c: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 8011e1e: 893b ldrh r3, [r7, #8] 8011e20: 461a mov r2, r3 8011e22: 68f9 ldr r1, [r7, #12] 8011e24: 6878 ldr r0, [r7, #4] 8011e26: f000 fa69 bl 80122fc 8011e2a: e009 b.n 8011e40 } else { USBD_CtlError(pdev, req); 8011e2c: 6839 ldr r1, [r7, #0] 8011e2e: 6878 ldr r0, [r7, #4] 8011e30: f000 f9e7 bl 8012202 8011e34: e004 b.n 8011e40 } } else { (void)USBD_CtlSendStatus(pdev); 8011e36: 6878 ldr r0, [r7, #4] 8011e38: f000 fac1 bl 80123be 8011e3c: e000 b.n 8011e40 return; 8011e3e: bf00 nop } } 8011e40: 3710 adds r7, #16 8011e42: 46bd mov sp, r7 8011e44: bd80 pop {r7, pc} 8011e46: bf00 nop 08011e48 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8011e48: b580 push {r7, lr} 8011e4a: b084 sub sp, #16 8011e4c: af00 add r7, sp, #0 8011e4e: 6078 str r0, [r7, #4] 8011e50: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8011e52: 683b ldr r3, [r7, #0] 8011e54: 889b ldrh r3, [r3, #4] 8011e56: 2b00 cmp r3, #0 8011e58: d131 bne.n 8011ebe 8011e5a: 683b ldr r3, [r7, #0] 8011e5c: 88db ldrh r3, [r3, #6] 8011e5e: 2b00 cmp r3, #0 8011e60: d12d bne.n 8011ebe 8011e62: 683b ldr r3, [r7, #0] 8011e64: 885b ldrh r3, [r3, #2] 8011e66: 2b7f cmp r3, #127 @ 0x7f 8011e68: d829 bhi.n 8011ebe { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 8011e6a: 683b ldr r3, [r7, #0] 8011e6c: 885b ldrh r3, [r3, #2] 8011e6e: b2db uxtb r3, r3 8011e70: f003 037f and.w r3, r3, #127 @ 0x7f 8011e74: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011e76: 687b ldr r3, [r7, #4] 8011e78: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011e7c: b2db uxtb r3, r3 8011e7e: 2b03 cmp r3, #3 8011e80: d104 bne.n 8011e8c { USBD_CtlError(pdev, req); 8011e82: 6839 ldr r1, [r7, #0] 8011e84: 6878 ldr r0, [r7, #4] 8011e86: f000 f9bc bl 8012202 if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011e8a: e01d b.n 8011ec8 } else { pdev->dev_address = dev_addr; 8011e8c: 687b ldr r3, [r7, #4] 8011e8e: 7bfa ldrb r2, [r7, #15] 8011e90: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8011e94: 7bfb ldrb r3, [r7, #15] 8011e96: 4619 mov r1, r3 8011e98: 6878 ldr r0, [r7, #4] 8011e9a: f006 fc71 bl 8018780 (void)USBD_CtlSendStatus(pdev); 8011e9e: 6878 ldr r0, [r7, #4] 8011ea0: f000 fa8d bl 80123be if (dev_addr != 0U) 8011ea4: 7bfb ldrb r3, [r7, #15] 8011ea6: 2b00 cmp r3, #0 8011ea8: d004 beq.n 8011eb4 { pdev->dev_state = USBD_STATE_ADDRESSED; 8011eaa: 687b ldr r3, [r7, #4] 8011eac: 2202 movs r2, #2 8011eae: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011eb2: e009 b.n 8011ec8 } else { pdev->dev_state = USBD_STATE_DEFAULT; 8011eb4: 687b ldr r3, [r7, #4] 8011eb6: 2201 movs r2, #1 8011eb8: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011ebc: e004 b.n 8011ec8 } } } else { USBD_CtlError(pdev, req); 8011ebe: 6839 ldr r1, [r7, #0] 8011ec0: 6878 ldr r0, [r7, #4] 8011ec2: f000 f99e bl 8012202 } } 8011ec6: bf00 nop 8011ec8: bf00 nop 8011eca: 3710 adds r7, #16 8011ecc: 46bd mov sp, r7 8011ece: bd80 pop {r7, pc} 08011ed0 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8011ed0: b580 push {r7, lr} 8011ed2: b084 sub sp, #16 8011ed4: af00 add r7, sp, #0 8011ed6: 6078 str r0, [r7, #4] 8011ed8: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8011eda: 2300 movs r3, #0 8011edc: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 8011ede: 683b ldr r3, [r7, #0] 8011ee0: 885b ldrh r3, [r3, #2] 8011ee2: b2da uxtb r2, r3 8011ee4: 4b4e ldr r3, [pc, #312] @ (8012020 ) 8011ee6: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 8011ee8: 4b4d ldr r3, [pc, #308] @ (8012020 ) 8011eea: 781b ldrb r3, [r3, #0] 8011eec: 2b01 cmp r3, #1 8011eee: d905 bls.n 8011efc { USBD_CtlError(pdev, req); 8011ef0: 6839 ldr r1, [r7, #0] 8011ef2: 6878 ldr r0, [r7, #4] 8011ef4: f000 f985 bl 8012202 return USBD_FAIL; 8011ef8: 2303 movs r3, #3 8011efa: e08c b.n 8012016 } switch (pdev->dev_state) 8011efc: 687b ldr r3, [r7, #4] 8011efe: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011f02: b2db uxtb r3, r3 8011f04: 2b02 cmp r3, #2 8011f06: d002 beq.n 8011f0e 8011f08: 2b03 cmp r3, #3 8011f0a: d029 beq.n 8011f60 8011f0c: e075 b.n 8011ffa { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 8011f0e: 4b44 ldr r3, [pc, #272] @ (8012020 ) 8011f10: 781b ldrb r3, [r3, #0] 8011f12: 2b00 cmp r3, #0 8011f14: d020 beq.n 8011f58 { pdev->dev_config = cfgidx; 8011f16: 4b42 ldr r3, [pc, #264] @ (8012020 ) 8011f18: 781b ldrb r3, [r3, #0] 8011f1a: 461a mov r2, r3 8011f1c: 687b ldr r3, [r7, #4] 8011f1e: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8011f20: 4b3f ldr r3, [pc, #252] @ (8012020 ) 8011f22: 781b ldrb r3, [r3, #0] 8011f24: 4619 mov r1, r3 8011f26: 6878 ldr r0, [r7, #4] 8011f28: f7ff f835 bl 8010f96 8011f2c: 4603 mov r3, r0 8011f2e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8011f30: 7bfb ldrb r3, [r7, #15] 8011f32: 2b00 cmp r3, #0 8011f34: d008 beq.n 8011f48 { USBD_CtlError(pdev, req); 8011f36: 6839 ldr r1, [r7, #0] 8011f38: 6878 ldr r0, [r7, #4] 8011f3a: f000 f962 bl 8012202 pdev->dev_state = USBD_STATE_ADDRESSED; 8011f3e: 687b ldr r3, [r7, #4] 8011f40: 2202 movs r2, #2 8011f42: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 8011f46: e065 b.n 8012014 (void)USBD_CtlSendStatus(pdev); 8011f48: 6878 ldr r0, [r7, #4] 8011f4a: f000 fa38 bl 80123be pdev->dev_state = USBD_STATE_CONFIGURED; 8011f4e: 687b ldr r3, [r7, #4] 8011f50: 2203 movs r2, #3 8011f52: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8011f56: e05d b.n 8012014 (void)USBD_CtlSendStatus(pdev); 8011f58: 6878 ldr r0, [r7, #4] 8011f5a: f000 fa30 bl 80123be break; 8011f5e: e059 b.n 8012014 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8011f60: 4b2f ldr r3, [pc, #188] @ (8012020 ) 8011f62: 781b ldrb r3, [r3, #0] 8011f64: 2b00 cmp r3, #0 8011f66: d112 bne.n 8011f8e { pdev->dev_state = USBD_STATE_ADDRESSED; 8011f68: 687b ldr r3, [r7, #4] 8011f6a: 2202 movs r2, #2 8011f6c: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 8011f70: 4b2b ldr r3, [pc, #172] @ (8012020 ) 8011f72: 781b ldrb r3, [r3, #0] 8011f74: 461a mov r2, r3 8011f76: 687b ldr r3, [r7, #4] 8011f78: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 8011f7a: 4b29 ldr r3, [pc, #164] @ (8012020 ) 8011f7c: 781b ldrb r3, [r3, #0] 8011f7e: 4619 mov r1, r3 8011f80: 6878 ldr r0, [r7, #4] 8011f82: f7ff f824 bl 8010fce (void)USBD_CtlSendStatus(pdev); 8011f86: 6878 ldr r0, [r7, #4] 8011f88: f000 fa19 bl 80123be } else { (void)USBD_CtlSendStatus(pdev); } break; 8011f8c: e042 b.n 8012014 else if (cfgidx != pdev->dev_config) 8011f8e: 4b24 ldr r3, [pc, #144] @ (8012020 ) 8011f90: 781b ldrb r3, [r3, #0] 8011f92: 461a mov r2, r3 8011f94: 687b ldr r3, [r7, #4] 8011f96: 685b ldr r3, [r3, #4] 8011f98: 429a cmp r2, r3 8011f9a: d02a beq.n 8011ff2 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8011f9c: 687b ldr r3, [r7, #4] 8011f9e: 685b ldr r3, [r3, #4] 8011fa0: b2db uxtb r3, r3 8011fa2: 4619 mov r1, r3 8011fa4: 6878 ldr r0, [r7, #4] 8011fa6: f7ff f812 bl 8010fce pdev->dev_config = cfgidx; 8011faa: 4b1d ldr r3, [pc, #116] @ (8012020 ) 8011fac: 781b ldrb r3, [r3, #0] 8011fae: 461a mov r2, r3 8011fb0: 687b ldr r3, [r7, #4] 8011fb2: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8011fb4: 4b1a ldr r3, [pc, #104] @ (8012020 ) 8011fb6: 781b ldrb r3, [r3, #0] 8011fb8: 4619 mov r1, r3 8011fba: 6878 ldr r0, [r7, #4] 8011fbc: f7fe ffeb bl 8010f96 8011fc0: 4603 mov r3, r0 8011fc2: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8011fc4: 7bfb ldrb r3, [r7, #15] 8011fc6: 2b00 cmp r3, #0 8011fc8: d00f beq.n 8011fea USBD_CtlError(pdev, req); 8011fca: 6839 ldr r1, [r7, #0] 8011fcc: 6878 ldr r0, [r7, #4] 8011fce: f000 f918 bl 8012202 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8011fd2: 687b ldr r3, [r7, #4] 8011fd4: 685b ldr r3, [r3, #4] 8011fd6: b2db uxtb r3, r3 8011fd8: 4619 mov r1, r3 8011fda: 6878 ldr r0, [r7, #4] 8011fdc: f7fe fff7 bl 8010fce pdev->dev_state = USBD_STATE_ADDRESSED; 8011fe0: 687b ldr r3, [r7, #4] 8011fe2: 2202 movs r2, #2 8011fe4: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8011fe8: e014 b.n 8012014 (void)USBD_CtlSendStatus(pdev); 8011fea: 6878 ldr r0, [r7, #4] 8011fec: f000 f9e7 bl 80123be break; 8011ff0: e010 b.n 8012014 (void)USBD_CtlSendStatus(pdev); 8011ff2: 6878 ldr r0, [r7, #4] 8011ff4: f000 f9e3 bl 80123be break; 8011ff8: e00c b.n 8012014 default: USBD_CtlError(pdev, req); 8011ffa: 6839 ldr r1, [r7, #0] 8011ffc: 6878 ldr r0, [r7, #4] 8011ffe: f000 f900 bl 8012202 (void)USBD_ClrClassConfig(pdev, cfgidx); 8012002: 4b07 ldr r3, [pc, #28] @ (8012020 ) 8012004: 781b ldrb r3, [r3, #0] 8012006: 4619 mov r1, r3 8012008: 6878 ldr r0, [r7, #4] 801200a: f7fe ffe0 bl 8010fce ret = USBD_FAIL; 801200e: 2303 movs r3, #3 8012010: 73fb strb r3, [r7, #15] break; 8012012: bf00 nop } return ret; 8012014: 7bfb ldrb r3, [r7, #15] } 8012016: 4618 mov r0, r3 8012018: 3710 adds r7, #16 801201a: 46bd mov sp, r7 801201c: bd80 pop {r7, pc} 801201e: bf00 nop 8012020: 20000784 .word 0x20000784 08012024 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012024: b580 push {r7, lr} 8012026: b082 sub sp, #8 8012028: af00 add r7, sp, #0 801202a: 6078 str r0, [r7, #4] 801202c: 6039 str r1, [r7, #0] if (req->wLength != 1U) 801202e: 683b ldr r3, [r7, #0] 8012030: 88db ldrh r3, [r3, #6] 8012032: 2b01 cmp r3, #1 8012034: d004 beq.n 8012040 { USBD_CtlError(pdev, req); 8012036: 6839 ldr r1, [r7, #0] 8012038: 6878 ldr r0, [r7, #4] 801203a: f000 f8e2 bl 8012202 default: USBD_CtlError(pdev, req); break; } } } 801203e: e023 b.n 8012088 switch (pdev->dev_state) 8012040: 687b ldr r3, [r7, #4] 8012042: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8012046: b2db uxtb r3, r3 8012048: 2b02 cmp r3, #2 801204a: dc02 bgt.n 8012052 801204c: 2b00 cmp r3, #0 801204e: dc03 bgt.n 8012058 8012050: e015 b.n 801207e 8012052: 2b03 cmp r3, #3 8012054: d00b beq.n 801206e 8012056: e012 b.n 801207e pdev->dev_default_config = 0U; 8012058: 687b ldr r3, [r7, #4] 801205a: 2200 movs r2, #0 801205c: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 801205e: 687b ldr r3, [r7, #4] 8012060: 3308 adds r3, #8 8012062: 2201 movs r2, #1 8012064: 4619 mov r1, r3 8012066: 6878 ldr r0, [r7, #4] 8012068: f000 f948 bl 80122fc break; 801206c: e00c b.n 8012088 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 801206e: 687b ldr r3, [r7, #4] 8012070: 3304 adds r3, #4 8012072: 2201 movs r2, #1 8012074: 4619 mov r1, r3 8012076: 6878 ldr r0, [r7, #4] 8012078: f000 f940 bl 80122fc break; 801207c: e004 b.n 8012088 USBD_CtlError(pdev, req); 801207e: 6839 ldr r1, [r7, #0] 8012080: 6878 ldr r0, [r7, #4] 8012082: f000 f8be bl 8012202 break; 8012086: bf00 nop } 8012088: bf00 nop 801208a: 3708 adds r7, #8 801208c: 46bd mov sp, r7 801208e: bd80 pop {r7, pc} 08012090 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012090: b580 push {r7, lr} 8012092: b082 sub sp, #8 8012094: af00 add r7, sp, #0 8012096: 6078 str r0, [r7, #4] 8012098: 6039 str r1, [r7, #0] switch (pdev->dev_state) 801209a: 687b ldr r3, [r7, #4] 801209c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80120a0: b2db uxtb r3, r3 80120a2: 3b01 subs r3, #1 80120a4: 2b02 cmp r3, #2 80120a6: d81e bhi.n 80120e6 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 80120a8: 683b ldr r3, [r7, #0] 80120aa: 88db ldrh r3, [r3, #6] 80120ac: 2b02 cmp r3, #2 80120ae: d004 beq.n 80120ba { USBD_CtlError(pdev, req); 80120b0: 6839 ldr r1, [r7, #0] 80120b2: 6878 ldr r0, [r7, #4] 80120b4: f000 f8a5 bl 8012202 break; 80120b8: e01a b.n 80120f0 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 80120ba: 687b ldr r3, [r7, #4] 80120bc: 2201 movs r2, #1 80120be: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 80120c0: 687b ldr r3, [r7, #4] 80120c2: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 80120c6: 2b00 cmp r3, #0 80120c8: d005 beq.n 80120d6 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 80120ca: 687b ldr r3, [r7, #4] 80120cc: 68db ldr r3, [r3, #12] 80120ce: f043 0202 orr.w r2, r3, #2 80120d2: 687b ldr r3, [r7, #4] 80120d4: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 80120d6: 687b ldr r3, [r7, #4] 80120d8: 330c adds r3, #12 80120da: 2202 movs r2, #2 80120dc: 4619 mov r1, r3 80120de: 6878 ldr r0, [r7, #4] 80120e0: f000 f90c bl 80122fc break; 80120e4: e004 b.n 80120f0 default: USBD_CtlError(pdev, req); 80120e6: 6839 ldr r1, [r7, #0] 80120e8: 6878 ldr r0, [r7, #4] 80120ea: f000 f88a bl 8012202 break; 80120ee: bf00 nop } } 80120f0: bf00 nop 80120f2: 3708 adds r7, #8 80120f4: 46bd mov sp, r7 80120f6: bd80 pop {r7, pc} 080120f8 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80120f8: b580 push {r7, lr} 80120fa: b082 sub sp, #8 80120fc: af00 add r7, sp, #0 80120fe: 6078 str r0, [r7, #4] 8012100: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8012102: 683b ldr r3, [r7, #0] 8012104: 885b ldrh r3, [r3, #2] 8012106: 2b01 cmp r3, #1 8012108: d107 bne.n 801211a { pdev->dev_remote_wakeup = 1U; 801210a: 687b ldr r3, [r7, #4] 801210c: 2201 movs r2, #1 801210e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8012112: 6878 ldr r0, [r7, #4] 8012114: f000 f953 bl 80123be } else { USBD_CtlError(pdev, req); } } 8012118: e013 b.n 8012142 else if (req->wValue == USB_FEATURE_TEST_MODE) 801211a: 683b ldr r3, [r7, #0] 801211c: 885b ldrh r3, [r3, #2] 801211e: 2b02 cmp r3, #2 8012120: d10b bne.n 801213a pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 8012122: 683b ldr r3, [r7, #0] 8012124: 889b ldrh r3, [r3, #4] 8012126: 0a1b lsrs r3, r3, #8 8012128: b29b uxth r3, r3 801212a: b2da uxtb r2, r3 801212c: 687b ldr r3, [r7, #4] 801212e: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 8012132: 6878 ldr r0, [r7, #4] 8012134: f000 f943 bl 80123be } 8012138: e003 b.n 8012142 USBD_CtlError(pdev, req); 801213a: 6839 ldr r1, [r7, #0] 801213c: 6878 ldr r0, [r7, #4] 801213e: f000 f860 bl 8012202 } 8012142: bf00 nop 8012144: 3708 adds r7, #8 8012146: 46bd mov sp, r7 8012148: bd80 pop {r7, pc} 0801214a : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 801214a: b580 push {r7, lr} 801214c: b082 sub sp, #8 801214e: af00 add r7, sp, #0 8012150: 6078 str r0, [r7, #4] 8012152: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8012154: 687b ldr r3, [r7, #4] 8012156: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 801215a: b2db uxtb r3, r3 801215c: 3b01 subs r3, #1 801215e: 2b02 cmp r3, #2 8012160: d80b bhi.n 801217a { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8012162: 683b ldr r3, [r7, #0] 8012164: 885b ldrh r3, [r3, #2] 8012166: 2b01 cmp r3, #1 8012168: d10c bne.n 8012184 { pdev->dev_remote_wakeup = 0U; 801216a: 687b ldr r3, [r7, #4] 801216c: 2200 movs r2, #0 801216e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8012172: 6878 ldr r0, [r7, #4] 8012174: f000 f923 bl 80123be } break; 8012178: e004 b.n 8012184 default: USBD_CtlError(pdev, req); 801217a: 6839 ldr r1, [r7, #0] 801217c: 6878 ldr r0, [r7, #4] 801217e: f000 f840 bl 8012202 break; 8012182: e000 b.n 8012186 break; 8012184: bf00 nop } } 8012186: bf00 nop 8012188: 3708 adds r7, #8 801218a: 46bd mov sp, r7 801218c: bd80 pop {r7, pc} 0801218e : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 801218e: b580 push {r7, lr} 8012190: b084 sub sp, #16 8012192: af00 add r7, sp, #0 8012194: 6078 str r0, [r7, #4] 8012196: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8012198: 683b ldr r3, [r7, #0] 801219a: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 801219c: 68fb ldr r3, [r7, #12] 801219e: 781a ldrb r2, [r3, #0] 80121a0: 687b ldr r3, [r7, #4] 80121a2: 701a strb r2, [r3, #0] pbuff++; 80121a4: 68fb ldr r3, [r7, #12] 80121a6: 3301 adds r3, #1 80121a8: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 80121aa: 68fb ldr r3, [r7, #12] 80121ac: 781a ldrb r2, [r3, #0] 80121ae: 687b ldr r3, [r7, #4] 80121b0: 705a strb r2, [r3, #1] pbuff++; 80121b2: 68fb ldr r3, [r7, #12] 80121b4: 3301 adds r3, #1 80121b6: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 80121b8: 68f8 ldr r0, [r7, #12] 80121ba: f7ff fa13 bl 80115e4 80121be: 4603 mov r3, r0 80121c0: 461a mov r2, r3 80121c2: 687b ldr r3, [r7, #4] 80121c4: 805a strh r2, [r3, #2] pbuff++; 80121c6: 68fb ldr r3, [r7, #12] 80121c8: 3301 adds r3, #1 80121ca: 60fb str r3, [r7, #12] pbuff++; 80121cc: 68fb ldr r3, [r7, #12] 80121ce: 3301 adds r3, #1 80121d0: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 80121d2: 68f8 ldr r0, [r7, #12] 80121d4: f7ff fa06 bl 80115e4 80121d8: 4603 mov r3, r0 80121da: 461a mov r2, r3 80121dc: 687b ldr r3, [r7, #4] 80121de: 809a strh r2, [r3, #4] pbuff++; 80121e0: 68fb ldr r3, [r7, #12] 80121e2: 3301 adds r3, #1 80121e4: 60fb str r3, [r7, #12] pbuff++; 80121e6: 68fb ldr r3, [r7, #12] 80121e8: 3301 adds r3, #1 80121ea: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 80121ec: 68f8 ldr r0, [r7, #12] 80121ee: f7ff f9f9 bl 80115e4 80121f2: 4603 mov r3, r0 80121f4: 461a mov r2, r3 80121f6: 687b ldr r3, [r7, #4] 80121f8: 80da strh r2, [r3, #6] } 80121fa: bf00 nop 80121fc: 3710 adds r7, #16 80121fe: 46bd mov sp, r7 8012200: bd80 pop {r7, pc} 08012202 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012202: b580 push {r7, lr} 8012204: b082 sub sp, #8 8012206: af00 add r7, sp, #0 8012208: 6078 str r0, [r7, #4] 801220a: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 801220c: 2180 movs r1, #128 @ 0x80 801220e: 6878 ldr r0, [r7, #4] 8012210: f006 fa4c bl 80186ac (void)USBD_LL_StallEP(pdev, 0U); 8012214: 2100 movs r1, #0 8012216: 6878 ldr r0, [r7, #4] 8012218: f006 fa48 bl 80186ac } 801221c: bf00 nop 801221e: 3708 adds r7, #8 8012220: 46bd mov sp, r7 8012222: bd80 pop {r7, pc} 08012224 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8012224: b580 push {r7, lr} 8012226: b086 sub sp, #24 8012228: af00 add r7, sp, #0 801222a: 60f8 str r0, [r7, #12] 801222c: 60b9 str r1, [r7, #8] 801222e: 607a str r2, [r7, #4] uint8_t idx = 0U; 8012230: 2300 movs r3, #0 8012232: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8012234: 68fb ldr r3, [r7, #12] 8012236: 2b00 cmp r3, #0 8012238: d042 beq.n 80122c0 { return; } pdesc = desc; 801223a: 68fb ldr r3, [r7, #12] 801223c: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 801223e: 6938 ldr r0, [r7, #16] 8012240: f000 f842 bl 80122c8 8012244: 4603 mov r3, r0 8012246: 3301 adds r3, #1 8012248: 005b lsls r3, r3, #1 801224a: f5b3 7f00 cmp.w r3, #512 @ 0x200 801224e: d808 bhi.n 8012262 8012250: 6938 ldr r0, [r7, #16] 8012252: f000 f839 bl 80122c8 8012256: 4603 mov r3, r0 8012258: 3301 adds r3, #1 801225a: b29b uxth r3, r3 801225c: 005b lsls r3, r3, #1 801225e: b29a uxth r2, r3 8012260: e001 b.n 8012266 8012262: f44f 7200 mov.w r2, #512 @ 0x200 8012266: 687b ldr r3, [r7, #4] 8012268: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 801226a: 7dfb ldrb r3, [r7, #23] 801226c: 68ba ldr r2, [r7, #8] 801226e: 4413 add r3, r2 8012270: 687a ldr r2, [r7, #4] 8012272: 7812 ldrb r2, [r2, #0] 8012274: 701a strb r2, [r3, #0] idx++; 8012276: 7dfb ldrb r3, [r7, #23] 8012278: 3301 adds r3, #1 801227a: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 801227c: 7dfb ldrb r3, [r7, #23] 801227e: 68ba ldr r2, [r7, #8] 8012280: 4413 add r3, r2 8012282: 2203 movs r2, #3 8012284: 701a strb r2, [r3, #0] idx++; 8012286: 7dfb ldrb r3, [r7, #23] 8012288: 3301 adds r3, #1 801228a: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 801228c: e013 b.n 80122b6 { unicode[idx] = *pdesc; 801228e: 7dfb ldrb r3, [r7, #23] 8012290: 68ba ldr r2, [r7, #8] 8012292: 4413 add r3, r2 8012294: 693a ldr r2, [r7, #16] 8012296: 7812 ldrb r2, [r2, #0] 8012298: 701a strb r2, [r3, #0] pdesc++; 801229a: 693b ldr r3, [r7, #16] 801229c: 3301 adds r3, #1 801229e: 613b str r3, [r7, #16] idx++; 80122a0: 7dfb ldrb r3, [r7, #23] 80122a2: 3301 adds r3, #1 80122a4: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 80122a6: 7dfb ldrb r3, [r7, #23] 80122a8: 68ba ldr r2, [r7, #8] 80122aa: 4413 add r3, r2 80122ac: 2200 movs r2, #0 80122ae: 701a strb r2, [r3, #0] idx++; 80122b0: 7dfb ldrb r3, [r7, #23] 80122b2: 3301 adds r3, #1 80122b4: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 80122b6: 693b ldr r3, [r7, #16] 80122b8: 781b ldrb r3, [r3, #0] 80122ba: 2b00 cmp r3, #0 80122bc: d1e7 bne.n 801228e 80122be: e000 b.n 80122c2 return; 80122c0: bf00 nop } } 80122c2: 3718 adds r7, #24 80122c4: 46bd mov sp, r7 80122c6: bd80 pop {r7, pc} 080122c8 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 80122c8: b480 push {r7} 80122ca: b085 sub sp, #20 80122cc: af00 add r7, sp, #0 80122ce: 6078 str r0, [r7, #4] uint8_t len = 0U; 80122d0: 2300 movs r3, #0 80122d2: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 80122d4: 687b ldr r3, [r7, #4] 80122d6: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 80122d8: e005 b.n 80122e6 { len++; 80122da: 7bfb ldrb r3, [r7, #15] 80122dc: 3301 adds r3, #1 80122de: 73fb strb r3, [r7, #15] pbuff++; 80122e0: 68bb ldr r3, [r7, #8] 80122e2: 3301 adds r3, #1 80122e4: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 80122e6: 68bb ldr r3, [r7, #8] 80122e8: 781b ldrb r3, [r3, #0] 80122ea: 2b00 cmp r3, #0 80122ec: d1f5 bne.n 80122da } return len; 80122ee: 7bfb ldrb r3, [r7, #15] } 80122f0: 4618 mov r0, r3 80122f2: 3714 adds r7, #20 80122f4: 46bd mov sp, r7 80122f6: f85d 7b04 ldr.w r7, [sp], #4 80122fa: 4770 bx lr 080122fc : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 80122fc: b580 push {r7, lr} 80122fe: b084 sub sp, #16 8012300: af00 add r7, sp, #0 8012302: 60f8 str r0, [r7, #12] 8012304: 60b9 str r1, [r7, #8] 8012306: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 8012308: 68fb ldr r3, [r7, #12] 801230a: 2202 movs r2, #2 801230c: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 8012310: 68fb ldr r3, [r7, #12] 8012312: 687a ldr r2, [r7, #4] 8012314: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 8012316: 68fb ldr r3, [r7, #12] 8012318: 68ba ldr r2, [r7, #8] 801231a: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 801231c: 68fb ldr r3, [r7, #12] 801231e: 687a ldr r2, [r7, #4] 8012320: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8012322: 687b ldr r3, [r7, #4] 8012324: 68ba ldr r2, [r7, #8] 8012326: 2100 movs r1, #0 8012328: 68f8 ldr r0, [r7, #12] 801232a: f006 fa48 bl 80187be return USBD_OK; 801232e: 2300 movs r3, #0 } 8012330: 4618 mov r0, r3 8012332: 3710 adds r7, #16 8012334: 46bd mov sp, r7 8012336: bd80 pop {r7, pc} 08012338 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8012338: b580 push {r7, lr} 801233a: b084 sub sp, #16 801233c: af00 add r7, sp, #0 801233e: 60f8 str r0, [r7, #12] 8012340: 60b9 str r1, [r7, #8] 8012342: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8012344: 687b ldr r3, [r7, #4] 8012346: 68ba ldr r2, [r7, #8] 8012348: 2100 movs r1, #0 801234a: 68f8 ldr r0, [r7, #12] 801234c: f006 fa37 bl 80187be return USBD_OK; 8012350: 2300 movs r3, #0 } 8012352: 4618 mov r0, r3 8012354: 3710 adds r7, #16 8012356: 46bd mov sp, r7 8012358: bd80 pop {r7, pc} 0801235a : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 801235a: b580 push {r7, lr} 801235c: b084 sub sp, #16 801235e: af00 add r7, sp, #0 8012360: 60f8 str r0, [r7, #12] 8012362: 60b9 str r1, [r7, #8] 8012364: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_OUT; 8012366: 68fb ldr r3, [r7, #12] 8012368: 2203 movs r2, #3 801236a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_out[0].total_length = len; 801236e: 68fb ldr r3, [r7, #12] 8012370: 687a ldr r2, [r7, #4] 8012372: f8c3 2154 str.w r2, [r3, #340] @ 0x154 pdev->ep_out[0].pbuffer = pbuf; 8012376: 68fb ldr r3, [r7, #12] 8012378: 68ba ldr r2, [r7, #8] 801237a: f8c3 2164 str.w r2, [r3, #356] @ 0x164 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_out[0].rem_length = 0U; #else pdev->ep_out[0].rem_length = len; 801237e: 68fb ldr r3, [r7, #12] 8012380: 687a ldr r2, [r7, #4] 8012382: f8c3 2158 str.w r2, [r3, #344] @ 0x158 #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8012386: 687b ldr r3, [r7, #4] 8012388: 68ba ldr r2, [r7, #8] 801238a: 2100 movs r1, #0 801238c: 68f8 ldr r0, [r7, #12] 801238e: f006 fa37 bl 8018800 return USBD_OK; 8012392: 2300 movs r3, #0 } 8012394: 4618 mov r0, r3 8012396: 3710 adds r7, #16 8012398: 46bd mov sp, r7 801239a: bd80 pop {r7, pc} 0801239c : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 801239c: b580 push {r7, lr} 801239e: b084 sub sp, #16 80123a0: af00 add r7, sp, #0 80123a2: 60f8 str r0, [r7, #12] 80123a4: 60b9 str r1, [r7, #8] 80123a6: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 80123a8: 687b ldr r3, [r7, #4] 80123aa: 68ba ldr r2, [r7, #8] 80123ac: 2100 movs r1, #0 80123ae: 68f8 ldr r0, [r7, #12] 80123b0: f006 fa26 bl 8018800 return USBD_OK; 80123b4: 2300 movs r3, #0 } 80123b6: 4618 mov r0, r3 80123b8: 3710 adds r7, #16 80123ba: 46bd mov sp, r7 80123bc: bd80 pop {r7, pc} 080123be : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 80123be: b580 push {r7, lr} 80123c0: b082 sub sp, #8 80123c2: af00 add r7, sp, #0 80123c4: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 80123c6: 687b ldr r3, [r7, #4] 80123c8: 2204 movs r2, #4 80123ca: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 80123ce: 2300 movs r3, #0 80123d0: 2200 movs r2, #0 80123d2: 2100 movs r1, #0 80123d4: 6878 ldr r0, [r7, #4] 80123d6: f006 f9f2 bl 80187be return USBD_OK; 80123da: 2300 movs r3, #0 } 80123dc: 4618 mov r0, r3 80123de: 3708 adds r7, #8 80123e0: 46bd mov sp, r7 80123e2: bd80 pop {r7, pc} 080123e4 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 80123e4: b580 push {r7, lr} 80123e6: b082 sub sp, #8 80123e8: af00 add r7, sp, #0 80123ea: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 80123ec: 687b ldr r3, [r7, #4] 80123ee: 2205 movs r2, #5 80123f0: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 80123f4: 2300 movs r3, #0 80123f6: 2200 movs r2, #0 80123f8: 2100 movs r1, #0 80123fa: 6878 ldr r0, [r7, #4] 80123fc: f006 fa00 bl 8018800 return USBD_OK; 8012400: 2300 movs r3, #0 } 8012402: 4618 mov r0, r3 8012404: 3708 adds r7, #8 8012406: 46bd mov sp, r7 8012408: bd80 pop {r7, pc} 0801240a : return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); } SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket ) { 801240a: b580 push {r7, lr} 801240c: b088 sub sp, #32 801240e: af00 add r7, sp, #0 8012410: 6078 str r0, [r7, #4] * Buffer is large enough to hold command complete without payload */ uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE]; TL_EvtPacket_t * p_rsp; p_rsp = (TL_EvtPacket_t *)local_buffer; 8012412: f107 030c add.w r3, r7, #12 8012416: 61fb str r3, [r7, #28] shci_send( SHCI_OPCODE_C2_DEBUG_INIT, sizeof( SHCI_C2_DEBUG_init_Cmd_Param_t ), (uint8_t*)&pCmdPacket->Param, 8012418: 687b ldr r3, [r7, #4] 801241a: f103 020c add.w r2, r3, #12 shci_send( SHCI_OPCODE_C2_DEBUG_INIT, 801241e: 69fb ldr r3, [r7, #28] 8012420: 210f movs r1, #15 8012422: f64f 4068 movw r0, #64616 @ 0xfc68 8012426: f000 f935 bl 8012694 p_rsp ); return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); 801242a: 69fb ldr r3, [r7, #28] 801242c: 330b adds r3, #11 801242e: 78db ldrb r3, [r3, #3] } 8012430: 4618 mov r0, r3 8012432: 3720 adds r7, #32 8012434: 46bd mov sp, r7 8012436: bd80 pop {r7, pc} 08012438 : return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); } SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket) { 8012438: b580 push {r7, lr} 801243a: b088 sub sp, #32 801243c: af00 add r7, sp, #0 801243e: 6078 str r0, [r7, #4] * Buffer is large enough to hold command complete without payload */ uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE]; TL_EvtPacket_t * p_rsp; p_rsp = (TL_EvtPacket_t *)local_buffer; 8012440: f107 030c add.w r3, r7, #12 8012444: 61fb str r3, [r7, #28] shci_send( SHCI_OPCODE_C2_CONFIG, 8012446: 69fb ldr r3, [r7, #28] 8012448: 687a ldr r2, [r7, #4] 801244a: 2110 movs r1, #16 801244c: f64f 4075 movw r0, #64629 @ 0xfc75 8012450: f000 f920 bl 8012694 sizeof(SHCI_C2_CONFIG_Cmd_Param_t), (uint8_t*)pCmdPacket, p_rsp ); return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); 8012454: 69fb ldr r3, [r7, #28] 8012456: 330b adds r3, #11 8012458: 78db ldrb r3, [r3, #3] } 801245a: 4618 mov r0, r3 801245c: 3720 adds r7, #32 801245e: 46bd mov sp, r7 8012460: bd80 pop {r7, pc} ... 08012464 : * Local System COMMAND * These commands are NOT sent to the CPU2 */ SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo ) { 8012464: b480 push {r7} 8012466: b08b sub sp, #44 @ 0x2c 8012468: af00 add r7, sp, #0 801246a: 6078 str r0, [r7, #4] uint32_t ipccdba = 0; 801246c: 2300 movs r3, #0 801246e: 613b str r3, [r7, #16] MB_RefTable_t * p_RefTable = NULL; 8012470: 2300 movs r3, #0 8012472: 60fb str r3, [r7, #12] uint32_t wireless_firmware_version = 0; 8012474: 2300 movs r3, #0 8012476: 627b str r3, [r7, #36] @ 0x24 uint32_t wireless_firmware_memorySize = 0; 8012478: 2300 movs r3, #0 801247a: 623b str r3, [r7, #32] uint32_t wireless_firmware_infoStack = 0; 801247c: 2300 movs r3, #0 801247e: 61fb str r3, [r7, #28] MB_FUS_DeviceInfoTable_t * p_fus_device_info_table = NULL; 8012480: 2300 movs r3, #0 8012482: 60bb str r3, [r7, #8] uint32_t fus_version = 0; 8012484: 2300 movs r3, #0 8012486: 61bb str r3, [r7, #24] uint32_t fus_memorySize = 0; 8012488: 2300 movs r3, #0 801248a: 617b str r3, [r7, #20] ipccdba = READ_BIT( FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA ); 801248c: 4b4a ldr r3, [pc, #296] @ (80125b8 ) 801248e: 6bdb ldr r3, [r3, #60] @ 0x3c 8012490: f3c3 030d ubfx r3, r3, #0, #14 8012494: 613b str r3, [r7, #16] /** * The Device Info Table mapping depends on which firmware is running on CPU2. * If the FUS is running on CPU2, FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD shall be written in the table. * Otherwise, it means the Wireless Firmware is running on the CPU2 */ p_fus_device_info_table = (MB_FUS_DeviceInfoTable_t*)(*(uint32_t*)((ipccdba<<2) + SRAM2A_BASE)); 8012496: 693b ldr r3, [r7, #16] 8012498: 009b lsls r3, r3, #2 801249a: f103 5300 add.w r3, r3, #536870912 @ 0x20000000 801249e: f503 3340 add.w r3, r3, #196608 @ 0x30000 80124a2: 681b ldr r3, [r3, #0] 80124a4: 60bb str r3, [r7, #8] if(p_fus_device_info_table->DeviceInfoTableState == FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD) 80124a6: 68bb ldr r3, [r7, #8] 80124a8: 681b ldr r3, [r3, #0] 80124aa: 4a44 ldr r2, [pc, #272] @ (80125bc ) 80124ac: 4293 cmp r3, r2 80124ae: d10f bne.n 80124d0 /* The FUS is running on CPU2 */ /** * Retrieve the WirelessFwInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ wireless_firmware_version = p_fus_device_info_table->WirelessStackVersion; 80124b0: 68bb ldr r3, [r7, #8] 80124b2: 695b ldr r3, [r3, #20] 80124b4: 627b str r3, [r7, #36] @ 0x24 wireless_firmware_memorySize = p_fus_device_info_table->WirelessStackMemorySize; 80124b6: 68bb ldr r3, [r7, #8] 80124b8: 699b ldr r3, [r3, #24] 80124ba: 623b str r3, [r7, #32] wireless_firmware_infoStack = p_fus_device_info_table->WirelessFirmwareBleInfo; 80124bc: 68bb ldr r3, [r7, #8] 80124be: 69db ldr r3, [r3, #28] 80124c0: 61fb str r3, [r7, #28] /** * Retrieve the FusInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ fus_version = p_fus_device_info_table->FusVersion; 80124c2: 68bb ldr r3, [r7, #8] 80124c4: 68db ldr r3, [r3, #12] 80124c6: 61bb str r3, [r7, #24] fus_memorySize = p_fus_device_info_table->FusMemorySize; 80124c8: 68bb ldr r3, [r7, #8] 80124ca: 691b ldr r3, [r3, #16] 80124cc: 617b str r3, [r7, #20] 80124ce: e01a b.n 8012506 } else { /* The Wireless Firmware is running on CPU2 */ p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE); 80124d0: 693b ldr r3, [r7, #16] 80124d2: 009b lsls r3, r3, #2 80124d4: f103 5300 add.w r3, r3, #536870912 @ 0x20000000 80124d8: f503 3340 add.w r3, r3, #196608 @ 0x30000 80124dc: 60fb str r3, [r7, #12] /** * Retrieve the WirelessFwInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ wireless_firmware_version = p_RefTable->p_device_info_table->WirelessFwInfoTable.Version; 80124de: 68fb ldr r3, [r7, #12] 80124e0: 681b ldr r3, [r3, #0] 80124e2: 691b ldr r3, [r3, #16] 80124e4: 627b str r3, [r7, #36] @ 0x24 wireless_firmware_memorySize = p_RefTable->p_device_info_table->WirelessFwInfoTable.MemorySize; 80124e6: 68fb ldr r3, [r7, #12] 80124e8: 681b ldr r3, [r3, #0] 80124ea: 695b ldr r3, [r3, #20] 80124ec: 623b str r3, [r7, #32] wireless_firmware_infoStack = p_RefTable->p_device_info_table->WirelessFwInfoTable.InfoStack; 80124ee: 68fb ldr r3, [r7, #12] 80124f0: 681b ldr r3, [r3, #0] 80124f2: 699b ldr r3, [r3, #24] 80124f4: 61fb str r3, [r7, #28] /** * Retrieve the FusInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ fus_version = p_RefTable->p_device_info_table->FusInfoTable.Version; 80124f6: 68fb ldr r3, [r7, #12] 80124f8: 681b ldr r3, [r3, #0] 80124fa: 685b ldr r3, [r3, #4] 80124fc: 61bb str r3, [r7, #24] fus_memorySize = p_RefTable->p_device_info_table->FusInfoTable.MemorySize; 80124fe: 68fb ldr r3, [r7, #12] 8012500: 681b ldr r3, [r3, #0] 8012502: 689b ldr r3, [r3, #8] 8012504: 617b str r3, [r7, #20] /** * Retrieve the WirelessFwInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ pWirelessInfo->VersionMajor = ((wireless_firmware_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET); 8012506: 6a7b ldr r3, [r7, #36] @ 0x24 8012508: 0e1b lsrs r3, r3, #24 801250a: b2da uxtb r2, r3 801250c: 687b ldr r3, [r7, #4] 801250e: 701a strb r2, [r3, #0] pWirelessInfo->VersionMinor = ((wireless_firmware_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET); 8012510: 6a7b ldr r3, [r7, #36] @ 0x24 8012512: 0c1b lsrs r3, r3, #16 8012514: b2da uxtb r2, r3 8012516: 687b ldr r3, [r7, #4] 8012518: 705a strb r2, [r3, #1] pWirelessInfo->VersionSub = ((wireless_firmware_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET); 801251a: 6a7b ldr r3, [r7, #36] @ 0x24 801251c: 0a1b lsrs r3, r3, #8 801251e: b2da uxtb r2, r3 8012520: 687b ldr r3, [r7, #4] 8012522: 709a strb r2, [r3, #2] pWirelessInfo->VersionBranch = ((wireless_firmware_version & INFO_VERSION_BRANCH_MASK) >> INFO_VERSION_BRANCH_OFFSET); 8012524: 6a7b ldr r3, [r7, #36] @ 0x24 8012526: 091b lsrs r3, r3, #4 8012528: b2db uxtb r3, r3 801252a: f003 030f and.w r3, r3, #15 801252e: b2da uxtb r2, r3 8012530: 687b ldr r3, [r7, #4] 8012532: 70da strb r2, [r3, #3] pWirelessInfo->VersionReleaseType = ((wireless_firmware_version & INFO_VERSION_TYPE_MASK) >> INFO_VERSION_TYPE_OFFSET); 8012534: 6a7b ldr r3, [r7, #36] @ 0x24 8012536: b2db uxtb r3, r3 8012538: f003 030f and.w r3, r3, #15 801253c: b2da uxtb r2, r3 801253e: 687b ldr r3, [r7, #4] 8012540: 711a strb r2, [r3, #4] pWirelessInfo->MemorySizeSram2B = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET); 8012542: 6a3b ldr r3, [r7, #32] 8012544: 0e1b lsrs r3, r3, #24 8012546: b2da uxtb r2, r3 8012548: 687b ldr r3, [r7, #4] 801254a: 715a strb r2, [r3, #5] pWirelessInfo->MemorySizeSram2A = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET); 801254c: 6a3b ldr r3, [r7, #32] 801254e: 0c1b lsrs r3, r3, #16 8012550: b2da uxtb r2, r3 8012552: 687b ldr r3, [r7, #4] 8012554: 719a strb r2, [r3, #6] pWirelessInfo->MemorySizeSram1 = ((wireless_firmware_memorySize & INFO_SIZE_SRAM1_MASK) >> INFO_SIZE_SRAM1_OFFSET); 8012556: 6a3b ldr r3, [r7, #32] 8012558: 0a1b lsrs r3, r3, #8 801255a: b2da uxtb r2, r3 801255c: 687b ldr r3, [r7, #4] 801255e: 71da strb r2, [r3, #7] pWirelessInfo->MemorySizeFlash = ((wireless_firmware_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET); 8012560: 6a3b ldr r3, [r7, #32] 8012562: b2da uxtb r2, r3 8012564: 687b ldr r3, [r7, #4] 8012566: 721a strb r2, [r3, #8] pWirelessInfo->StackType = ((wireless_firmware_infoStack & INFO_STACK_TYPE_MASK) >> INFO_STACK_TYPE_OFFSET); 8012568: 69fb ldr r3, [r7, #28] 801256a: b2da uxtb r2, r3 801256c: 687b ldr r3, [r7, #4] 801256e: 725a strb r2, [r3, #9] /** * Retrieve the FusInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ pWirelessInfo->FusVersionMajor = ((fus_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET); 8012570: 69bb ldr r3, [r7, #24] 8012572: 0e1b lsrs r3, r3, #24 8012574: b2da uxtb r2, r3 8012576: 687b ldr r3, [r7, #4] 8012578: 729a strb r2, [r3, #10] pWirelessInfo->FusVersionMinor = ((fus_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET); 801257a: 69bb ldr r3, [r7, #24] 801257c: 0c1b lsrs r3, r3, #16 801257e: b2da uxtb r2, r3 8012580: 687b ldr r3, [r7, #4] 8012582: 72da strb r2, [r3, #11] pWirelessInfo->FusVersionSub = ((fus_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET); 8012584: 69bb ldr r3, [r7, #24] 8012586: 0a1b lsrs r3, r3, #8 8012588: b2da uxtb r2, r3 801258a: 687b ldr r3, [r7, #4] 801258c: 731a strb r2, [r3, #12] pWirelessInfo->FusMemorySizeSram2B = ((fus_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET); 801258e: 697b ldr r3, [r7, #20] 8012590: 0e1b lsrs r3, r3, #24 8012592: b2da uxtb r2, r3 8012594: 687b ldr r3, [r7, #4] 8012596: 735a strb r2, [r3, #13] pWirelessInfo->FusMemorySizeSram2A = ((fus_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET); 8012598: 697b ldr r3, [r7, #20] 801259a: 0c1b lsrs r3, r3, #16 801259c: b2da uxtb r2, r3 801259e: 687b ldr r3, [r7, #4] 80125a0: 739a strb r2, [r3, #14] pWirelessInfo->FusMemorySizeFlash = ((fus_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET); 80125a2: 697b ldr r3, [r7, #20] 80125a4: b2da uxtb r2, r3 80125a6: 687b ldr r3, [r7, #4] 80125a8: 73da strb r2, [r3, #15] return (SHCI_Success); 80125aa: 2300 movs r3, #0 } 80125ac: 4618 mov r0, r3 80125ae: 372c adds r7, #44 @ 0x2c 80125b0: 46bd mov sp, r7 80125b2: f85d 7b04 ldr.w r7, [sp], #4 80125b6: 4770 bx lr 80125b8: 58004000 .word 0x58004000 80125bc: a94656b9 .word 0xa94656b9 080125c0 : static void TlUserEvtReceived(TL_EvtPacket_t *shcievt); static void TlInit( TL_CmdPacket_t * p_cmdbuffer ); /* Interface ------- ---------------------------------------------------------*/ void shci_init(void(* UserEvtRx)(void* pData), void* pConf) { 80125c0: b580 push {r7, lr} 80125c2: b082 sub sp, #8 80125c4: af00 add r7, sp, #0 80125c6: 6078 str r0, [r7, #4] 80125c8: 6039 str r1, [r7, #0] StatusNotCallBackFunction = ((SHCI_TL_HciInitConf_t *)pConf)->StatusNotCallBack; 80125ca: 683b ldr r3, [r7, #0] 80125cc: 685b ldr r3, [r3, #4] 80125ce: 4a08 ldr r2, [pc, #32] @ (80125f0 ) 80125d0: 6013 str r3, [r2, #0] shciContext.UserEvtRx = UserEvtRx; 80125d2: 4a08 ldr r2, [pc, #32] @ (80125f4 ) 80125d4: 687b ldr r3, [r7, #4] 80125d6: 61d3 str r3, [r2, #28] shci_register_io_bus (&shciContext.io); 80125d8: 4806 ldr r0, [pc, #24] @ (80125f4 ) 80125da: f000 f915 bl 8012808 TlInit((TL_CmdPacket_t *)(((SHCI_TL_HciInitConf_t *)pConf)->p_cmdbuffer)); 80125de: 683b ldr r3, [r7, #0] 80125e0: 681b ldr r3, [r3, #0] 80125e2: 4618 mov r0, r3 80125e4: f000 f898 bl 8012718 return; 80125e8: bf00 nop } 80125ea: 3708 adds r7, #8 80125ec: 46bd mov sp, r7 80125ee: bd80 pop {r7, pc} 80125f0: 200007a8 .word 0x200007a8 80125f4: 20000788 .word 0x20000788 080125f8 : void shci_user_evt_proc(void) { 80125f8: b580 push {r7, lr} 80125fa: b084 sub sp, #16 80125fc: af00 add r7, sp, #0 /** * It is more secure to use LST_remove_head()/LST_insert_head() compare to LST_get_next_node()/LST_remove_node() * in case the user overwrite the header where the next/prev pointers are located */ if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable)) 80125fe: 4822 ldr r0, [pc, #136] @ (8012688 ) 8012600: f000 fb52 bl 8012ca8 8012604: 4603 mov r3, r0 8012606: 2b00 cmp r3, #0 8012608: d12b bne.n 8012662 801260a: 4b20 ldr r3, [pc, #128] @ (801268c ) 801260c: 781b ldrb r3, [r3, #0] 801260e: 2b00 cmp r3, #0 8012610: d027 beq.n 8012662 { LST_remove_head ( &SHciAsynchEventQueue, (tListNode **)&phcievtbuffer ); 8012612: f107 030c add.w r3, r7, #12 8012616: 4619 mov r1, r3 8012618: 481b ldr r0, [pc, #108] @ (8012688 ) 801261a: f000 fbd4 bl 8012dc6 if (shciContext.UserEvtRx != NULL) 801261e: 4b1c ldr r3, [pc, #112] @ (8012690 ) 8012620: 69db ldr r3, [r3, #28] 8012622: 2b00 cmp r3, #0 8012624: d00c beq.n 8012640 { UserEvtRxParam.pckt = phcievtbuffer; 8012626: 68fb ldr r3, [r7, #12] 8012628: 60bb str r3, [r7, #8] UserEvtRxParam.status = SHCI_TL_UserEventFlow_Enable; 801262a: 2301 movs r3, #1 801262c: 713b strb r3, [r7, #4] shciContext.UserEvtRx((void *)&UserEvtRxParam); 801262e: 4b18 ldr r3, [pc, #96] @ (8012690 ) 8012630: 69db ldr r3, [r3, #28] 8012632: 1d3a adds r2, r7, #4 8012634: 4610 mov r0, r2 8012636: 4798 blx r3 SHCI_TL_UserEventFlow = UserEvtRxParam.status; 8012638: 793a ldrb r2, [r7, #4] 801263a: 4b14 ldr r3, [pc, #80] @ (801268c ) 801263c: 701a strb r2, [r3, #0] 801263e: e002 b.n 8012646 } else { SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable; 8012640: 4b12 ldr r3, [pc, #72] @ (801268c ) 8012642: 2201 movs r2, #1 8012644: 701a strb r2, [r3, #0] } if(SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable) 8012646: 4b11 ldr r3, [pc, #68] @ (801268c ) 8012648: 781b ldrb r3, [r3, #0] 801264a: 2b00 cmp r3, #0 801264c: d004 beq.n 8012658 { TL_MM_EvtDone( phcievtbuffer ); 801264e: 68fb ldr r3, [r7, #12] 8012650: 4618 mov r0, r3 8012652: f000 fa25 bl 8012aa0 8012656: e004 b.n 8012662 else { /** * put back the event in the queue */ LST_insert_head ( &SHciAsynchEventQueue, (tListNode *)phcievtbuffer ); 8012658: 68fb ldr r3, [r7, #12] 801265a: 4619 mov r1, r3 801265c: 480a ldr r0, [pc, #40] @ (8012688 ) 801265e: f000 fb45 bl 8012cec } } if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable)) 8012662: 4809 ldr r0, [pc, #36] @ (8012688 ) 8012664: f000 fb20 bl 8012ca8 8012668: 4603 mov r3, r0 801266a: 2b00 cmp r3, #0 801266c: d107 bne.n 801267e 801266e: 4b07 ldr r3, [pc, #28] @ (801268c ) 8012670: 781b ldrb r3, [r3, #0] 8012672: 2b00 cmp r3, #0 8012674: d003 beq.n 801267e { shci_notify_asynch_evt((void*) &SHciAsynchEventQueue); 8012676: 4804 ldr r0, [pc, #16] @ (8012688 ) 8012678: f7ef ff6e bl 8002558 } return; 801267c: bf00 nop 801267e: bf00 nop } 8012680: 3710 adds r7, #16 8012682: 46bd mov sp, r7 8012684: bd80 pop {r7, pc} 8012686: bf00 nop 8012688: 200002d8 .word 0x200002d8 801268c: 200002e8 .word 0x200002e8 8012690: 20000788 .word 0x20000788 08012694 : return; } void shci_send( uint16_t cmd_code, uint8_t len_cmd_payload, uint8_t * p_cmd_payload, TL_EvtPacket_t * p_rsp ) { 8012694: b580 push {r7, lr} 8012696: b084 sub sp, #16 8012698: af00 add r7, sp, #0 801269a: 60ba str r2, [r7, #8] 801269c: 607b str r3, [r7, #4] 801269e: 4603 mov r3, r0 80126a0: 81fb strh r3, [r7, #14] 80126a2: 460b mov r3, r1 80126a4: 737b strb r3, [r7, #13] Cmd_SetStatus(SHCI_TL_CmdBusy); 80126a6: 2000 movs r0, #0 80126a8: f000 f868 bl 801277c pCmdBuffer->cmdserial.cmd.cmdcode = cmd_code; 80126ac: 4b17 ldr r3, [pc, #92] @ (801270c ) 80126ae: 681b ldr r3, [r3, #0] 80126b0: 89fa ldrh r2, [r7, #14] 80126b2: f8a3 2009 strh.w r2, [r3, #9] pCmdBuffer->cmdserial.cmd.plen = len_cmd_payload; 80126b6: 4b15 ldr r3, [pc, #84] @ (801270c ) 80126b8: 681b ldr r3, [r3, #0] 80126ba: 7b7a ldrb r2, [r7, #13] 80126bc: 72da strb r2, [r3, #11] memcpy(pCmdBuffer->cmdserial.cmd.payload, p_cmd_payload, len_cmd_payload ); 80126be: 4b13 ldr r3, [pc, #76] @ (801270c ) 80126c0: 681b ldr r3, [r3, #0] 80126c2: 330c adds r3, #12 80126c4: 7b7a ldrb r2, [r7, #13] 80126c6: 68b9 ldr r1, [r7, #8] 80126c8: 4618 mov r0, r3 80126ca: f007 faa2 bl 8019c12 CmdRspStatusFlag = SHCI_TL_CMD_RESP_WAIT; 80126ce: 4b10 ldr r3, [pc, #64] @ (8012710 ) 80126d0: 2201 movs r2, #1 80126d2: 701a strb r2, [r3, #0] shciContext.io.Send(0,0); 80126d4: 4b0f ldr r3, [pc, #60] @ (8012714 ) 80126d6: 691b ldr r3, [r3, #16] 80126d8: 2100 movs r1, #0 80126da: 2000 movs r0, #0 80126dc: 4798 blx r3 shci_cmd_resp_wait(SHCI_TL_DEFAULT_TIMEOUT); 80126de: f248 00e8 movw r0, #33000 @ 0x80e8 80126e2: f7ef ff59 bl 8002598 /** * The command complete of a system command does not have the header * It starts immediately with the evtserial field */ memcpy( &(p_rsp->evtserial), pCmdBuffer, ((TL_EvtSerial_t*)pCmdBuffer)->evt.plen + TL_EVT_HDR_SIZE ); 80126e6: 687b ldr r3, [r7, #4] 80126e8: f103 0008 add.w r0, r3, #8 80126ec: 4b07 ldr r3, [pc, #28] @ (801270c ) 80126ee: 6819 ldr r1, [r3, #0] 80126f0: 4b06 ldr r3, [pc, #24] @ (801270c ) 80126f2: 681b ldr r3, [r3, #0] 80126f4: 789b ldrb r3, [r3, #2] 80126f6: 3303 adds r3, #3 80126f8: 461a mov r2, r3 80126fa: f007 fa8a bl 8019c12 Cmd_SetStatus(SHCI_TL_CmdAvailable); 80126fe: 2001 movs r0, #1 8012700: f000 f83c bl 801277c return; 8012704: bf00 nop } 8012706: 3710 adds r7, #16 8012708: 46bd mov sp, r7 801270a: bd80 pop {r7, pc} 801270c: 200002e4 .word 0x200002e4 8012710: 200007ac .word 0x200007ac 8012714: 20000788 .word 0x20000788 08012718 : /* Private functions ---------------------------------------------------------*/ static void TlInit( TL_CmdPacket_t * p_cmdbuffer ) { 8012718: b580 push {r7, lr} 801271a: b086 sub sp, #24 801271c: af00 add r7, sp, #0 801271e: 6078 str r0, [r7, #4] TL_SYS_InitConf_t Conf; pCmdBuffer = p_cmdbuffer; 8012720: 4a10 ldr r2, [pc, #64] @ (8012764 ) 8012722: 687b ldr r3, [r7, #4] 8012724: 6013 str r3, [r2, #0] LST_init_head (&SHciAsynchEventQueue); 8012726: 4810 ldr r0, [pc, #64] @ (8012768 ) 8012728: f000 faae bl 8012c88 Cmd_SetStatus(SHCI_TL_CmdAvailable); 801272c: 2001 movs r0, #1 801272e: f000 f825 bl 801277c SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable; 8012732: 4b0e ldr r3, [pc, #56] @ (801276c ) 8012734: 2201 movs r2, #1 8012736: 701a strb r2, [r3, #0] /* Initialize low level driver */ if (shciContext.io.Init) 8012738: 4b0d ldr r3, [pc, #52] @ (8012770 ) 801273a: 681b ldr r3, [r3, #0] 801273c: 2b00 cmp r3, #0 801273e: d00c beq.n 801275a { Conf.p_cmdbuffer = (uint8_t *)p_cmdbuffer; 8012740: 687b ldr r3, [r7, #4] 8012742: 617b str r3, [r7, #20] Conf.IoBusCallBackCmdEvt = TlCmdEvtReceived; 8012744: 4b0b ldr r3, [pc, #44] @ (8012774 ) 8012746: 60fb str r3, [r7, #12] Conf.IoBusCallBackUserEvt = TlUserEvtReceived; 8012748: 4b0b ldr r3, [pc, #44] @ (8012778 ) 801274a: 613b str r3, [r7, #16] shciContext.io.Init(&Conf); 801274c: 4b08 ldr r3, [pc, #32] @ (8012770 ) 801274e: 681b ldr r3, [r3, #0] 8012750: f107 020c add.w r2, r7, #12 8012754: 4610 mov r0, r2 8012756: 4798 blx r3 } return; 8012758: bf00 nop 801275a: bf00 nop } 801275c: 3718 adds r7, #24 801275e: 46bd mov sp, r7 8012760: bd80 pop {r7, pc} 8012762: bf00 nop 8012764: 200002e4 .word 0x200002e4 8012768: 200002d8 .word 0x200002d8 801276c: 200002e8 .word 0x200002e8 8012770: 20000788 .word 0x20000788 8012774: 080127cd .word 0x080127cd 8012778: 080127e5 .word 0x080127e5 0801277c : static void Cmd_SetStatus(SHCI_TL_CmdStatus_t shcicmdstatus) { 801277c: b580 push {r7, lr} 801277e: b082 sub sp, #8 8012780: af00 add r7, sp, #0 8012782: 4603 mov r3, r0 8012784: 71fb strb r3, [r7, #7] if(shcicmdstatus == SHCI_TL_CmdBusy) 8012786: 79fb ldrb r3, [r7, #7] 8012788: 2b00 cmp r3, #0 801278a: d10b bne.n 80127a4 { if(StatusNotCallBackFunction != 0) 801278c: 4b0d ldr r3, [pc, #52] @ (80127c4 ) 801278e: 681b ldr r3, [r3, #0] 8012790: 2b00 cmp r3, #0 8012792: d003 beq.n 801279c { StatusNotCallBackFunction( SHCI_TL_CmdBusy ); 8012794: 4b0b ldr r3, [pc, #44] @ (80127c4 ) 8012796: 681b ldr r3, [r3, #0] 8012798: 2000 movs r0, #0 801279a: 4798 blx r3 } SHCICmdStatus = SHCI_TL_CmdBusy; 801279c: 4b0a ldr r3, [pc, #40] @ (80127c8 ) 801279e: 2200 movs r2, #0 80127a0: 701a strb r2, [r3, #0] { StatusNotCallBackFunction( SHCI_TL_CmdAvailable ); } } return; 80127a2: e00b b.n 80127bc SHCICmdStatus = SHCI_TL_CmdAvailable; 80127a4: 4b08 ldr r3, [pc, #32] @ (80127c8 ) 80127a6: 2201 movs r2, #1 80127a8: 701a strb r2, [r3, #0] if(StatusNotCallBackFunction != 0) 80127aa: 4b06 ldr r3, [pc, #24] @ (80127c4 ) 80127ac: 681b ldr r3, [r3, #0] 80127ae: 2b00 cmp r3, #0 80127b0: d004 beq.n 80127bc StatusNotCallBackFunction( SHCI_TL_CmdAvailable ); 80127b2: 4b04 ldr r3, [pc, #16] @ (80127c4 ) 80127b4: 681b ldr r3, [r3, #0] 80127b6: 2001 movs r0, #1 80127b8: 4798 blx r3 return; 80127ba: bf00 nop 80127bc: bf00 nop } 80127be: 3708 adds r7, #8 80127c0: 46bd mov sp, r7 80127c2: bd80 pop {r7, pc} 80127c4: 200007a8 .word 0x200007a8 80127c8: 200002e0 .word 0x200002e0 080127cc : static void TlCmdEvtReceived(TL_EvtPacket_t *shcievt) { 80127cc: b580 push {r7, lr} 80127ce: b082 sub sp, #8 80127d0: af00 add r7, sp, #0 80127d2: 6078 str r0, [r7, #4] (void)(shcievt); shci_cmd_resp_release(0); /**< Notify the application the Cmd response has been received */ 80127d4: 2000 movs r0, #0 80127d6: f7ef fecf bl 8002578 return; 80127da: bf00 nop } 80127dc: 3708 adds r7, #8 80127de: 46bd mov sp, r7 80127e0: bd80 pop {r7, pc} ... 080127e4 : static void TlUserEvtReceived(TL_EvtPacket_t *shcievt) { 80127e4: b580 push {r7, lr} 80127e6: b082 sub sp, #8 80127e8: af00 add r7, sp, #0 80127ea: 6078 str r0, [r7, #4] LST_insert_tail(&SHciAsynchEventQueue, (tListNode *)shcievt); 80127ec: 6879 ldr r1, [r7, #4] 80127ee: 4805 ldr r0, [pc, #20] @ (8012804 ) 80127f0: f000 faa2 bl 8012d38 shci_notify_asynch_evt((void*) &SHciAsynchEventQueue); /**< Notify the application a full HCI event has been received */ 80127f4: 4803 ldr r0, [pc, #12] @ (8012804 ) 80127f6: f7ef feaf bl 8002558 return; 80127fa: bf00 nop } 80127fc: 3708 adds r7, #8 80127fe: 46bd mov sp, r7 8012800: bd80 pop {r7, pc} 8012802: bf00 nop 8012804: 200002d8 .word 0x200002d8 08012808 : #include "shci_tl.h" #include "tl.h" void shci_register_io_bus(tSHciIO* fops) { 8012808: b480 push {r7} 801280a: b083 sub sp, #12 801280c: af00 add r7, sp, #0 801280e: 6078 str r0, [r7, #4] /* Register IO bus services */ fops->Init = TL_SYS_Init; 8012810: 687b ldr r3, [r7, #4] 8012812: 4a05 ldr r2, [pc, #20] @ (8012828 ) 8012814: 601a str r2, [r3, #0] fops->Send = TL_SYS_SendCmd; 8012816: 687b ldr r3, [r7, #4] 8012818: 4a04 ldr r2, [pc, #16] @ (801282c ) 801281a: 611a str r2, [r3, #16] return; 801281c: bf00 nop } 801281e: 370c adds r7, #12 8012820: 46bd mov sp, r7 8012822: f85d 7b04 ldr.w r7, [sp], #4 8012826: 4770 bx lr 8012828: 0801292d .word 0x0801292d 801282c: 08012981 .word 0x08012981 08012830 : /****************************************************************************** * GENERAL - refer to AN5289 for functions description. ******************************************************************************/ void TL_Enable( void ) { 8012830: b580 push {r7, lr} 8012832: af00 add r7, sp, #0 HW_IPCC_Enable(); 8012834: f005 fa0e bl 8017c54 return; 8012838: bf00 nop } 801283a: bd80 pop {r7, pc} 0801283c : void TL_Init( void ) { 801283c: b580 push {r7, lr} 801283e: af00 add r7, sp, #0 TL_RefTable.p_device_info_table = &TL_DeviceInfoTable; 8012840: 4b10 ldr r3, [pc, #64] @ (8012884 ) 8012842: 4a11 ldr r2, [pc, #68] @ (8012888 ) 8012844: 601a str r2, [r3, #0] TL_RefTable.p_ble_table = &TL_BleTable; 8012846: 4b0f ldr r3, [pc, #60] @ (8012884 ) 8012848: 4a10 ldr r2, [pc, #64] @ (801288c ) 801284a: 605a str r2, [r3, #4] TL_RefTable.p_thread_table = &TL_ThreadTable; 801284c: 4b0d ldr r3, [pc, #52] @ (8012884 ) 801284e: 4a10 ldr r2, [pc, #64] @ (8012890 ) 8012850: 609a str r2, [r3, #8] TL_RefTable.p_lld_tests_table = &TL_LldTestsTable; 8012852: 4b0c ldr r3, [pc, #48] @ (8012884 ) 8012854: 4a0f ldr r2, [pc, #60] @ (8012894 ) 8012856: 621a str r2, [r3, #32] TL_RefTable.p_ble_lld_table = &TL_BleLldTable; 8012858: 4b0a ldr r3, [pc, #40] @ (8012884 ) 801285a: 4a0f ldr r2, [pc, #60] @ (8012898 ) 801285c: 625a str r2, [r3, #36] @ 0x24 TL_RefTable.p_sys_table = &TL_SysTable; 801285e: 4b09 ldr r3, [pc, #36] @ (8012884 ) 8012860: 4a0e ldr r2, [pc, #56] @ (801289c ) 8012862: 60da str r2, [r3, #12] TL_RefTable.p_mem_manager_table = &TL_MemManagerTable; 8012864: 4b07 ldr r3, [pc, #28] @ (8012884 ) 8012866: 4a0e ldr r2, [pc, #56] @ (80128a0 ) 8012868: 611a str r2, [r3, #16] TL_RefTable.p_traces_table = &TL_TracesTable; 801286a: 4b06 ldr r3, [pc, #24] @ (8012884 ) 801286c: 4a0d ldr r2, [pc, #52] @ (80128a4 ) 801286e: 615a str r2, [r3, #20] TL_RefTable.p_mac_802_15_4_table = &TL_Mac_802_15_4_Table; 8012870: 4b04 ldr r3, [pc, #16] @ (8012884 ) 8012872: 4a0d ldr r2, [pc, #52] @ (80128a8 ) 8012874: 619a str r2, [r3, #24] TL_RefTable.p_zigbee_table = &TL_Zigbee_Table; 8012876: 4b03 ldr r3, [pc, #12] @ (8012884 ) 8012878: 4a0c ldr r2, [pc, #48] @ (80128ac ) 801287a: 61da str r2, [r3, #28] HW_IPCC_Init(); 801287c: f005 f9fe bl 8017c7c return; 8012880: bf00 nop } 8012882: bd80 pop {r7, pc} 8012884: 20030000 .word 0x20030000 8012888: 20030028 .word 0x20030028 801288c: 20030048 .word 0x20030048 8012890: 20030058 .word 0x20030058 8012894: 20030068 .word 0x20030068 8012898: 20030070 .word 0x20030070 801289c: 20030078 .word 0x20030078 80128a0: 20030080 .word 0x20030080 80128a4: 2003009c .word 0x2003009c 80128a8: 200300a0 .word 0x200300a0 80128ac: 200300ac .word 0x200300ac 080128b0 : return 0; } void HW_IPCC_BLE_RxEvtNot(void) { 80128b0: b580 push {r7, lr} 80128b2: b082 sub sp, #8 80128b4: af00 add r7, sp, #0 TL_EvtPacket_t *phcievt; while(LST_is_empty(&EvtQueue) == FALSE) 80128b6: e01c b.n 80128f2 { LST_remove_head (&EvtQueue, (tListNode **)&phcievt); 80128b8: 1d3b adds r3, r7, #4 80128ba: 4619 mov r1, r3 80128bc: 4812 ldr r0, [pc, #72] @ (8012908 ) 80128be: f000 fa82 bl 8012dc6 if ( ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CS_OPCODE) || ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CC_OPCODE ) ) 80128c2: 687b ldr r3, [r7, #4] 80128c4: 7a5b ldrb r3, [r3, #9] 80128c6: 2b0f cmp r3, #15 80128c8: d003 beq.n 80128d2 80128ca: 687b ldr r3, [r7, #4] 80128cc: 7a5b ldrb r3, [r3, #9] 80128ce: 2b0e cmp r3, #14 80128d0: d105 bne.n 80128de { OutputDbgTrace(TL_MB_BLE_CMD_RSP, (uint8_t*)phcievt); 80128d2: 687b ldr r3, [r7, #4] 80128d4: 4619 mov r1, r3 80128d6: 2002 movs r0, #2 80128d8: f000 f950 bl 8012b7c 80128dc: e004 b.n 80128e8 } else { OutputDbgTrace(TL_MB_BLE_ASYNCH_EVT, (uint8_t*)phcievt); 80128de: 687b ldr r3, [r7, #4] 80128e0: 4619 mov r1, r3 80128e2: 2005 movs r0, #5 80128e4: f000 f94a bl 8012b7c } BLE_IoBusEvtCallBackFunction(phcievt); 80128e8: 4b08 ldr r3, [pc, #32] @ (801290c ) 80128ea: 681b ldr r3, [r3, #0] 80128ec: 687a ldr r2, [r7, #4] 80128ee: 4610 mov r0, r2 80128f0: 4798 blx r3 while(LST_is_empty(&EvtQueue) == FALSE) 80128f2: 4805 ldr r0, [pc, #20] @ (8012908 ) 80128f4: f000 f9d8 bl 8012ca8 80128f8: 4603 mov r3, r0 80128fa: 2b00 cmp r3, #0 80128fc: d0dc beq.n 80128b8 } return; 80128fe: bf00 nop } 8012900: 3708 adds r7, #8 8012902: 46bd mov sp, r7 8012904: bd80 pop {r7, pc} 8012906: bf00 nop 8012908: 200300c8 .word 0x200300c8 801290c: 200007b8 .word 0x200007b8 08012910 : return 0; } void HW_IPCC_BLE_AclDataAckNot(void) { 8012910: b580 push {r7, lr} 8012912: af00 add r7, sp, #0 OutputDbgTrace(TL_MB_ACL_DATA_RSP, (uint8_t*)NULL); 8012914: 2100 movs r1, #0 8012916: 2004 movs r0, #4 8012918: f000 f930 bl 8012b7c BLE_IoBusAclDataTxAck( ); 801291c: 4b02 ldr r3, [pc, #8] @ (8012928 ) 801291e: 681b ldr r3, [r3, #0] 8012920: 4798 blx r3 return; 8012922: bf00 nop } 8012924: bd80 pop {r7, pc} 8012926: bf00 nop 8012928: 200007bc .word 0x200007bc 0801292c : /****************************************************************************** * SYSTEM ******************************************************************************/ int32_t TL_SYS_Init( void* pConf ) { 801292c: b580 push {r7, lr} 801292e: b084 sub sp, #16 8012930: af00 add r7, sp, #0 8012932: 6078 str r0, [r7, #4] MB_SysTable_t * p_systable; TL_SYS_InitConf_t *pInitHciConf = (TL_SYS_InitConf_t *) pConf; 8012934: 687b ldr r3, [r7, #4] 8012936: 60fb str r3, [r7, #12] LST_init_head (&SystemEvtQueue); 8012938: 480d ldr r0, [pc, #52] @ (8012970 ) 801293a: f000 f9a5 bl 8012c88 p_systable = TL_RefTable.p_sys_table; 801293e: 4b0d ldr r3, [pc, #52] @ (8012974 ) 8012940: 68db ldr r3, [r3, #12] 8012942: 60bb str r3, [r7, #8] p_systable->pcmd_buffer = pInitHciConf->p_cmdbuffer; 8012944: 68fb ldr r3, [r7, #12] 8012946: 689a ldr r2, [r3, #8] 8012948: 68bb ldr r3, [r7, #8] 801294a: 601a str r2, [r3, #0] p_systable->sys_queue = (uint8_t*)&SystemEvtQueue; 801294c: 68bb ldr r3, [r7, #8] 801294e: 4a08 ldr r2, [pc, #32] @ (8012970 ) 8012950: 605a str r2, [r3, #4] HW_IPCC_SYS_Init(); 8012952: f005 f9d1 bl 8017cf8 SYS_CMD_IoBusCallBackFunction = pInitHciConf->IoBusCallBackCmdEvt; 8012956: 68fb ldr r3, [r7, #12] 8012958: 681b ldr r3, [r3, #0] 801295a: 4a07 ldr r2, [pc, #28] @ (8012978 ) 801295c: 6013 str r3, [r2, #0] SYS_EVT_IoBusCallBackFunction = pInitHciConf->IoBusCallBackUserEvt; 801295e: 68fb ldr r3, [r7, #12] 8012960: 685b ldr r3, [r3, #4] 8012962: 4a06 ldr r2, [pc, #24] @ (801297c ) 8012964: 6013 str r3, [r2, #0] return 0; 8012966: 2300 movs r3, #0 } 8012968: 4618 mov r0, r3 801296a: 3710 adds r7, #16 801296c: 46bd mov sp, r7 801296e: bd80 pop {r7, pc} 8012970: 200300d0 .word 0x200300d0 8012974: 20030000 .word 0x20030000 8012978: 200007c0 .word 0x200007c0 801297c: 200007c4 .word 0x200007c4 08012980 : int32_t TL_SYS_SendCmd( uint8_t* buffer, uint16_t size ) { 8012980: b580 push {r7, lr} 8012982: b082 sub sp, #8 8012984: af00 add r7, sp, #0 8012986: 6078 str r0, [r7, #4] 8012988: 460b mov r3, r1 801298a: 807b strh r3, [r7, #2] (void)(buffer); (void)(size); ((TL_CmdPacket_t *)(TL_RefTable.p_sys_table->pcmd_buffer))->cmdserial.type = TL_SYSCMD_PKT_TYPE; 801298c: 4b09 ldr r3, [pc, #36] @ (80129b4 ) 801298e: 68db ldr r3, [r3, #12] 8012990: 681b ldr r3, [r3, #0] 8012992: 2210 movs r2, #16 8012994: 721a strb r2, [r3, #8] OutputDbgTrace(TL_MB_SYS_CMD, TL_RefTable.p_sys_table->pcmd_buffer); 8012996: 4b07 ldr r3, [pc, #28] @ (80129b4 ) 8012998: 68db ldr r3, [r3, #12] 801299a: 681b ldr r3, [r3, #0] 801299c: 4619 mov r1, r3 801299e: 2006 movs r0, #6 80129a0: f000 f8ec bl 8012b7c HW_IPCC_SYS_SendCmd(); 80129a4: f005 f9c2 bl 8017d2c return 0; 80129a8: 2300 movs r3, #0 } 80129aa: 4618 mov r0, r3 80129ac: 3708 adds r7, #8 80129ae: 46bd mov sp, r7 80129b0: bd80 pop {r7, pc} 80129b2: bf00 nop 80129b4: 20030000 .word 0x20030000 080129b8 : void HW_IPCC_SYS_CmdEvtNot(void) { 80129b8: b580 push {r7, lr} 80129ba: af00 add r7, sp, #0 OutputDbgTrace(TL_MB_SYS_CMD_RSP, (uint8_t*)(TL_RefTable.p_sys_table->pcmd_buffer) ); 80129bc: 4b07 ldr r3, [pc, #28] @ (80129dc ) 80129be: 68db ldr r3, [r3, #12] 80129c0: 681b ldr r3, [r3, #0] 80129c2: 4619 mov r1, r3 80129c4: 2007 movs r0, #7 80129c6: f000 f8d9 bl 8012b7c SYS_CMD_IoBusCallBackFunction( (TL_EvtPacket_t*)(TL_RefTable.p_sys_table->pcmd_buffer) ); 80129ca: 4b05 ldr r3, [pc, #20] @ (80129e0 ) 80129cc: 681b ldr r3, [r3, #0] 80129ce: 4a03 ldr r2, [pc, #12] @ (80129dc ) 80129d0: 68d2 ldr r2, [r2, #12] 80129d2: 6812 ldr r2, [r2, #0] 80129d4: 4610 mov r0, r2 80129d6: 4798 blx r3 return; 80129d8: bf00 nop } 80129da: bd80 pop {r7, pc} 80129dc: 20030000 .word 0x20030000 80129e0: 200007c0 .word 0x200007c0 080129e4 : void HW_IPCC_SYS_EvtNot( void ) { 80129e4: b580 push {r7, lr} 80129e6: b082 sub sp, #8 80129e8: af00 add r7, sp, #0 TL_EvtPacket_t *p_evt; while(LST_is_empty(&SystemEvtQueue) == FALSE) 80129ea: e00e b.n 8012a0a { LST_remove_head (&SystemEvtQueue, (tListNode **)&p_evt); 80129ec: 1d3b adds r3, r7, #4 80129ee: 4619 mov r1, r3 80129f0: 480b ldr r0, [pc, #44] @ (8012a20 ) 80129f2: f000 f9e8 bl 8012dc6 OutputDbgTrace(TL_MB_SYS_ASYNCH_EVT, (uint8_t*)p_evt ); 80129f6: 687b ldr r3, [r7, #4] 80129f8: 4619 mov r1, r3 80129fa: 2008 movs r0, #8 80129fc: f000 f8be bl 8012b7c SYS_EVT_IoBusCallBackFunction( p_evt ); 8012a00: 4b08 ldr r3, [pc, #32] @ (8012a24 ) 8012a02: 681b ldr r3, [r3, #0] 8012a04: 687a ldr r2, [r7, #4] 8012a06: 4610 mov r0, r2 8012a08: 4798 blx r3 while(LST_is_empty(&SystemEvtQueue) == FALSE) 8012a0a: 4805 ldr r0, [pc, #20] @ (8012a20 ) 8012a0c: f000 f94c bl 8012ca8 8012a10: 4603 mov r3, r0 8012a12: 2b00 cmp r3, #0 8012a14: d0ea beq.n 80129ec } return; 8012a16: bf00 nop } 8012a18: 3708 adds r7, #8 8012a1a: 46bd mov sp, r7 8012a1c: bd80 pop {r7, pc} 8012a1e: bf00 nop 8012a20: 200300d0 .word 0x200300d0 8012a24: 200007c4 .word 0x200007c4 08012a28 : /****************************************************************************** * MEMORY MANAGER ******************************************************************************/ void TL_MM_Init( TL_MM_Config_t *p_Config ) { 8012a28: b580 push {r7, lr} 8012a2a: b082 sub sp, #8 8012a2c: af00 add r7, sp, #0 8012a2e: 6078 str r0, [r7, #4] static MB_MemManagerTable_t * p_mem_manager_table; LST_init_head (&FreeBufQueue); 8012a30: 4817 ldr r0, [pc, #92] @ (8012a90 ) 8012a32: f000 f929 bl 8012c88 LST_init_head (&LocalFreeBufQueue); 8012a36: 4817 ldr r0, [pc, #92] @ (8012a94 ) 8012a38: f000 f926 bl 8012c88 p_mem_manager_table = TL_RefTable.p_mem_manager_table; 8012a3c: 4b16 ldr r3, [pc, #88] @ (8012a98 ) 8012a3e: 691b ldr r3, [r3, #16] 8012a40: 4a16 ldr r2, [pc, #88] @ (8012a9c ) 8012a42: 6013 str r3, [r2, #0] p_mem_manager_table->blepool = p_Config->p_AsynchEvtPool; 8012a44: 4b15 ldr r3, [pc, #84] @ (8012a9c ) 8012a46: 681b ldr r3, [r3, #0] 8012a48: 687a ldr r2, [r7, #4] 8012a4a: 6892 ldr r2, [r2, #8] 8012a4c: 609a str r2, [r3, #8] p_mem_manager_table->blepoolsize = p_Config->AsynchEvtPoolSize; 8012a4e: 4b13 ldr r3, [pc, #76] @ (8012a9c ) 8012a50: 681b ldr r3, [r3, #0] 8012a52: 687a ldr r2, [r7, #4] 8012a54: 68d2 ldr r2, [r2, #12] 8012a56: 60da str r2, [r3, #12] p_mem_manager_table->pevt_free_buffer_queue = (uint8_t*)&FreeBufQueue; 8012a58: 4b10 ldr r3, [pc, #64] @ (8012a9c ) 8012a5a: 681b ldr r3, [r3, #0] 8012a5c: 4a0c ldr r2, [pc, #48] @ (8012a90 ) 8012a5e: 611a str r2, [r3, #16] p_mem_manager_table->spare_ble_buffer = p_Config->p_BleSpareEvtBuffer; 8012a60: 4b0e ldr r3, [pc, #56] @ (8012a9c ) 8012a62: 681b ldr r3, [r3, #0] 8012a64: 687a ldr r2, [r7, #4] 8012a66: 6812 ldr r2, [r2, #0] 8012a68: 601a str r2, [r3, #0] p_mem_manager_table->spare_sys_buffer = p_Config->p_SystemSpareEvtBuffer; 8012a6a: 4b0c ldr r3, [pc, #48] @ (8012a9c ) 8012a6c: 681b ldr r3, [r3, #0] 8012a6e: 687a ldr r2, [r7, #4] 8012a70: 6852 ldr r2, [r2, #4] 8012a72: 605a str r2, [r3, #4] p_mem_manager_table->traces_evt_pool = p_Config->p_TracesEvtPool; 8012a74: 4b09 ldr r3, [pc, #36] @ (8012a9c ) 8012a76: 681b ldr r3, [r3, #0] 8012a78: 687a ldr r2, [r7, #4] 8012a7a: 6912 ldr r2, [r2, #16] 8012a7c: 615a str r2, [r3, #20] p_mem_manager_table->tracespoolsize = p_Config->TracesEvtPoolSize; 8012a7e: 4b07 ldr r3, [pc, #28] @ (8012a9c ) 8012a80: 681b ldr r3, [r3, #0] 8012a82: 687a ldr r2, [r7, #4] 8012a84: 6952 ldr r2, [r2, #20] 8012a86: 619a str r2, [r3, #24] return; 8012a88: bf00 nop } 8012a8a: 3708 adds r7, #8 8012a8c: 46bd mov sp, r7 8012a8e: bd80 pop {r7, pc} 8012a90: 200300b8 .word 0x200300b8 8012a94: 200007b0 .word 0x200007b0 8012a98: 20030000 .word 0x20030000 8012a9c: 200007c8 .word 0x200007c8 08012aa0 : void TL_MM_EvtDone(TL_EvtPacket_t * phcievt) { 8012aa0: b580 push {r7, lr} 8012aa2: b082 sub sp, #8 8012aa4: af00 add r7, sp, #0 8012aa6: 6078 str r0, [r7, #4] LST_insert_tail(&LocalFreeBufQueue, (tListNode *)phcievt); 8012aa8: 6879 ldr r1, [r7, #4] 8012aaa: 4807 ldr r0, [pc, #28] @ (8012ac8 ) 8012aac: f000 f944 bl 8012d38 OutputDbgTrace(TL_MB_MM_RELEASE_BUFFER, (uint8_t*)phcievt); 8012ab0: 6879 ldr r1, [r7, #4] 8012ab2: 2000 movs r0, #0 8012ab4: f000 f862 bl 8012b7c HW_IPCC_MM_SendFreeBuf( SendFreeBuf ); 8012ab8: 4804 ldr r0, [pc, #16] @ (8012acc ) 8012aba: f005 f97d bl 8017db8 return; 8012abe: bf00 nop } 8012ac0: 3708 adds r7, #8 8012ac2: 46bd mov sp, r7 8012ac4: bd80 pop {r7, pc} 8012ac6: bf00 nop 8012ac8: 200007b0 .word 0x200007b0 8012acc: 08012ad1 .word 0x08012ad1 08012ad0 : static void SendFreeBuf( void ) { 8012ad0: b580 push {r7, lr} 8012ad2: b082 sub sp, #8 8012ad4: af00 add r7, sp, #0 tListNode *p_node; while ( FALSE == LST_is_empty (&LocalFreeBufQueue) ) 8012ad6: e00c b.n 8012af2 { LST_remove_head( &LocalFreeBufQueue, (tListNode **)&p_node ); 8012ad8: 1d3b adds r3, r7, #4 8012ada: 4619 mov r1, r3 8012adc: 480a ldr r0, [pc, #40] @ (8012b08 ) 8012ade: f000 f972 bl 8012dc6 LST_insert_tail( (tListNode*)(TL_RefTable.p_mem_manager_table->pevt_free_buffer_queue), p_node ); 8012ae2: 4b0a ldr r3, [pc, #40] @ (8012b0c ) 8012ae4: 691b ldr r3, [r3, #16] 8012ae6: 691b ldr r3, [r3, #16] 8012ae8: 687a ldr r2, [r7, #4] 8012aea: 4611 mov r1, r2 8012aec: 4618 mov r0, r3 8012aee: f000 f923 bl 8012d38 while ( FALSE == LST_is_empty (&LocalFreeBufQueue) ) 8012af2: 4805 ldr r0, [pc, #20] @ (8012b08 ) 8012af4: f000 f8d8 bl 8012ca8 8012af8: 4603 mov r3, r0 8012afa: 2b00 cmp r3, #0 8012afc: d0ec beq.n 8012ad8 } return; 8012afe: bf00 nop } 8012b00: 3708 adds r7, #8 8012b02: 46bd mov sp, r7 8012b04: bd80 pop {r7, pc} 8012b06: bf00 nop 8012b08: 200007b0 .word 0x200007b0 8012b0c: 20030000 .word 0x20030000 08012b10 : /****************************************************************************** * TRACES ******************************************************************************/ void TL_TRACES_Init( void ) { 8012b10: b580 push {r7, lr} 8012b12: af00 add r7, sp, #0 LST_init_head (&TracesEvtQueue); 8012b14: 4805 ldr r0, [pc, #20] @ (8012b2c ) 8012b16: f000 f8b7 bl 8012c88 TL_RefTable.p_traces_table->traces_queue = (uint8_t*)&TracesEvtQueue; 8012b1a: 4b05 ldr r3, [pc, #20] @ (8012b30 ) 8012b1c: 695b ldr r3, [r3, #20] 8012b1e: 4a03 ldr r2, [pc, #12] @ (8012b2c ) 8012b20: 601a str r2, [r3, #0] HW_IPCC_TRACES_Init(); 8012b22: f005 f99b bl 8017e5c return; 8012b26: bf00 nop } 8012b28: bd80 pop {r7, pc} 8012b2a: bf00 nop 8012b2c: 200300c0 .word 0x200300c0 8012b30: 20030000 .word 0x20030000 08012b34 : void HW_IPCC_TRACES_EvtNot(void) { 8012b34: b580 push {r7, lr} 8012b36: b082 sub sp, #8 8012b38: af00 add r7, sp, #0 TL_EvtPacket_t *phcievt; while(LST_is_empty(&TracesEvtQueue) == FALSE) 8012b3a: e008 b.n 8012b4e { LST_remove_head (&TracesEvtQueue, (tListNode **)&phcievt); 8012b3c: 1d3b adds r3, r7, #4 8012b3e: 4619 mov r1, r3 8012b40: 4808 ldr r0, [pc, #32] @ (8012b64 ) 8012b42: f000 f940 bl 8012dc6 TL_TRACES_EvtReceived( phcievt ); 8012b46: 687b ldr r3, [r7, #4] 8012b48: 4618 mov r0, r3 8012b4a: f000 f80d bl 8012b68 while(LST_is_empty(&TracesEvtQueue) == FALSE) 8012b4e: 4805 ldr r0, [pc, #20] @ (8012b64 ) 8012b50: f000 f8aa bl 8012ca8 8012b54: 4603 mov r3, r0 8012b56: 2b00 cmp r3, #0 8012b58: d0f0 beq.n 8012b3c } return; 8012b5a: bf00 nop } 8012b5c: 3708 adds r7, #8 8012b5e: 46bd mov sp, r7 8012b60: bd80 pop {r7, pc} 8012b62: bf00 nop 8012b64: 200300c0 .word 0x200300c0 08012b68 : __WEAK void TL_TRACES_EvtReceived( TL_EvtPacket_t * hcievt ) { 8012b68: b480 push {r7} 8012b6a: b083 sub sp, #12 8012b6c: af00 add r7, sp, #0 8012b6e: 6078 str r0, [r7, #4] (void)(hcievt); } 8012b70: bf00 nop 8012b72: 370c adds r7, #12 8012b74: 46bd mov sp, r7 8012b76: f85d 7b04 ldr.w r7, [sp], #4 8012b7a: 4770 bx lr 08012b7c : /****************************************************************************** * DEBUG INFORMATION ******************************************************************************/ static void OutputDbgTrace(TL_MB_PacketType_t packet_type, uint8_t* buffer) { 8012b7c: b480 push {r7} 8012b7e: b087 sub sp, #28 8012b80: af00 add r7, sp, #0 8012b82: 4603 mov r3, r0 8012b84: 6039 str r1, [r7, #0] 8012b86: 71fb strb r3, [r7, #7] TL_EvtPacket_t *p_evt_packet; TL_CmdPacket_t *p_cmd_packet; TL_AclDataPacket_t *p_acldata_packet; TL_EvtSerial_t *p_cmd_rsp_packet; switch(packet_type) 8012b88: 79fb ldrb r3, [r7, #7] 8012b8a: 2b08 cmp r3, #8 8012b8c: d84c bhi.n 8012c28 8012b8e: a201 add r2, pc, #4 @ (adr r2, 8012b94 ) 8012b90: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012b94: 08012bb9 .word 0x08012bb9 8012b98: 08012bdd .word 0x08012bdd 8012b9c: 08012be9 .word 0x08012be9 8012ba0: 08012be3 .word 0x08012be3 8012ba4: 08012c29 .word 0x08012c29 8012ba8: 08012bfd .word 0x08012bfd 8012bac: 08012c09 .word 0x08012c09 8012bb0: 08012c0f .word 0x08012c0f 8012bb4: 08012c1d .word 0x08012c1d { case TL_MB_MM_RELEASE_BUFFER: p_evt_packet = (TL_EvtPacket_t*)buffer; 8012bb8: 683b ldr r3, [r7, #0] 8012bba: 617b str r3, [r7, #20] switch(p_evt_packet->evtserial.evt.evtcode) 8012bbc: 697b ldr r3, [r7, #20] 8012bbe: 7a5b ldrb r3, [r3, #9] 8012bc0: 2bff cmp r3, #255 @ 0xff 8012bc2: d005 beq.n 8012bd0 8012bc4: 2bff cmp r3, #255 @ 0xff 8012bc6: dc05 bgt.n 8012bd4 8012bc8: 2b0e cmp r3, #14 8012bca: d005 beq.n 8012bd8 8012bcc: 2b0f cmp r3, #15 break; default: TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode); TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet); break; 8012bce: e001 b.n 8012bd4 break; 8012bd0: bf00 nop 8012bd2: e02a b.n 8012c2a break; 8012bd4: bf00 nop 8012bd6: e028 b.n 8012c2a break; 8012bd8: bf00 nop } TL_MM_DBG_MSG("\r\n"); break; 8012bda: e026 b.n 8012c2a case TL_MB_BLE_CMD: p_cmd_packet = (TL_CmdPacket_t*)buffer; 8012bdc: 683b ldr r3, [r7, #0] 8012bde: 60fb str r3, [r7, #12] TL_HCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, ""); } TL_HCI_CMD_DBG_MSG("\r\n"); TL_HCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE); break; 8012be0: e023 b.n 8012c2a case TL_MB_ACL_DATA: (void)p_acldata_packet; p_acldata_packet = (TL_AclDataPacket_t*)buffer; 8012be2: 683b ldr r3, [r7, #0] 8012be4: 60bb str r3, [r7, #8] TL_HCI_CMD_DBG_MSG(" payload:"); TL_HCI_CMD_DBG_BUF(p_acldata_packet->AclDataSerial.acl_data, p_acldata_packet->AclDataSerial.length, ""); }*/ TL_HCI_CMD_DBG_MSG("\r\n"); /*TL_HCI_CMD_DBG_RAW(&p_acldata_packet->AclDataSerial, p_acldata_packet->AclDataSerial.length+TL_CMD_HDR_SIZE);*/ break; 8012be6: e020 b.n 8012c2a TL_HCI_CMD_DBG_MSG(" ACL Data Tx Ack received"); TL_HCI_CMD_DBG_MSG("\r\n"); break; case TL_MB_BLE_CMD_RSP: p_evt_packet = (TL_EvtPacket_t*)buffer; 8012be8: 683b ldr r3, [r7, #0] 8012bea: 617b str r3, [r7, #20] switch(p_evt_packet->evtserial.evt.evtcode) 8012bec: 697b ldr r3, [r7, #20] 8012bee: 7a5b ldrb r3, [r3, #9] 8012bf0: 2b0e cmp r3, #14 8012bf2: d001 beq.n 8012bf8 8012bf4: 2b0f cmp r3, #15 } break; default: TL_HCI_CMD_DBG_MSG("unknown ble rsp received: %02X", p_evt_packet->evtserial.evt.evtcode); break; 8012bf6: e000 b.n 8012bfa break; 8012bf8: bf00 nop } TL_HCI_CMD_DBG_MSG("\r\n"); TL_HCI_CMD_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); break; 8012bfa: e016 b.n 8012c2a case TL_MB_BLE_ASYNCH_EVT: p_evt_packet = (TL_EvtPacket_t*)buffer; 8012bfc: 683b ldr r3, [r7, #0] 8012bfe: 617b str r3, [r7, #20] if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE) 8012c00: 697b ldr r3, [r7, #20] 8012c02: 7a5b ldrb r3, [r3, #9] 8012c04: 2bff cmp r3, #255 @ 0xff } TL_HCI_EVT_DBG_MSG("\r\n"); TL_HCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); break; 8012c06: e010 b.n 8012c2a case TL_MB_SYS_CMD: p_cmd_packet = (TL_CmdPacket_t*)buffer; 8012c08: 683b ldr r3, [r7, #0] 8012c0a: 60fb str r3, [r7, #12] TL_SHCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, ""); } TL_SHCI_CMD_DBG_MSG("\r\n"); TL_SHCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE); break; 8012c0c: e00d b.n 8012c2a case TL_MB_SYS_CMD_RSP: p_cmd_rsp_packet = (TL_EvtSerial_t*)buffer; 8012c0e: 683b ldr r3, [r7, #0] 8012c10: 613b str r3, [r7, #16] switch(p_cmd_rsp_packet->evt.evtcode) 8012c12: 693b ldr r3, [r7, #16] 8012c14: 785b ldrb r3, [r3, #1] 8012c16: 2b0e cmp r3, #14 } break; default: TL_SHCI_CMD_DBG_MSG("unknown sys rsp received: %02X", p_cmd_rsp_packet->evt.evtcode); break; 8012c18: bf00 nop } TL_SHCI_CMD_DBG_MSG("\r\n"); TL_SHCI_CMD_DBG_RAW(&p_cmd_rsp_packet->evt, p_cmd_rsp_packet->evt.plen+TL_EVT_HDR_SIZE); break; 8012c1a: e006 b.n 8012c2a case TL_MB_SYS_ASYNCH_EVT: p_evt_packet = (TL_EvtPacket_t*)buffer; 8012c1c: 683b ldr r3, [r7, #0] 8012c1e: 617b str r3, [r7, #20] if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE) 8012c20: 697b ldr r3, [r7, #20] 8012c22: 7a5b ldrb r3, [r3, #9] 8012c24: 2bff cmp r3, #255 @ 0xff } TL_SHCI_EVT_DBG_MSG("\r\n"); TL_SHCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); break; 8012c26: e000 b.n 8012c2a default: break; 8012c28: bf00 nop } return; 8012c2a: bf00 nop } 8012c2c: 371c adds r7, #28 8012c2e: 46bd mov sp, r7 8012c30: f85d 7b04 ldr.w r7, [sp], #4 8012c34: 4770 bx lr 8012c36: bf00 nop 08012c38 : /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Functions Definition ------------------------------------------------------*/ uint8_t * OTP_Read( uint8_t id ) { 8012c38: b480 push {r7} 8012c3a: b085 sub sp, #20 8012c3c: af00 add r7, sp, #0 8012c3e: 4603 mov r3, r0 8012c40: 71fb strb r3, [r7, #7] uint8_t *p_id; p_id = (uint8_t*)(CFG_OTP_END_ADRESS - 7) ; 8012c42: 4b0f ldr r3, [pc, #60] @ (8012c80 ) 8012c44: 60fb str r3, [r7, #12] while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) ) 8012c46: e002 b.n 8012c4e { p_id -= 8 ; 8012c48: 68fb ldr r3, [r7, #12] 8012c4a: 3b08 subs r3, #8 8012c4c: 60fb str r3, [r7, #12] while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) ) 8012c4e: 68fb ldr r3, [r7, #12] 8012c50: 3307 adds r3, #7 8012c52: 781b ldrb r3, [r3, #0] 8012c54: 79fa ldrb r2, [r7, #7] 8012c56: 429a cmp r2, r3 8012c58: d003 beq.n 8012c62 8012c5a: 68fb ldr r3, [r7, #12] 8012c5c: 4a09 ldr r2, [pc, #36] @ (8012c84 ) 8012c5e: 4293 cmp r3, r2 8012c60: d1f2 bne.n 8012c48 } if((*( p_id + 7 )) != id) 8012c62: 68fb ldr r3, [r7, #12] 8012c64: 3307 adds r3, #7 8012c66: 781b ldrb r3, [r3, #0] 8012c68: 79fa ldrb r2, [r7, #7] 8012c6a: 429a cmp r2, r3 8012c6c: d001 beq.n 8012c72 { p_id = 0 ; 8012c6e: 2300 movs r3, #0 8012c70: 60fb str r3, [r7, #12] } return p_id ; 8012c72: 68fb ldr r3, [r7, #12] } 8012c74: 4618 mov r0, r3 8012c76: 3714 adds r7, #20 8012c78: 46bd mov sp, r7 8012c7a: f85d 7b04 ldr.w r7, [sp], #4 8012c7e: 4770 bx lr 8012c80: 1fff73f8 .word 0x1fff73f8 8012c84: 1fff7000 .word 0x1fff7000 08012c88 : /****************************************************************************** * Function Definitions ******************************************************************************/ void LST_init_head (tListNode * listHead) { 8012c88: b480 push {r7} 8012c8a: b083 sub sp, #12 8012c8c: af00 add r7, sp, #0 8012c8e: 6078 str r0, [r7, #4] listHead->next = listHead; 8012c90: 687b ldr r3, [r7, #4] 8012c92: 687a ldr r2, [r7, #4] 8012c94: 601a str r2, [r3, #0] listHead->prev = listHead; 8012c96: 687b ldr r3, [r7, #4] 8012c98: 687a ldr r2, [r7, #4] 8012c9a: 605a str r2, [r3, #4] } 8012c9c: bf00 nop 8012c9e: 370c adds r7, #12 8012ca0: 46bd mov sp, r7 8012ca2: f85d 7b04 ldr.w r7, [sp], #4 8012ca6: 4770 bx lr 08012ca8 : uint8_t LST_is_empty (tListNode * listHead) { 8012ca8: b480 push {r7} 8012caa: b087 sub sp, #28 8012cac: af00 add r7, sp, #0 8012cae: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8012cb0: f3ef 8310 mrs r3, PRIMASK 8012cb4: 60fb str r3, [r7, #12] return(result); 8012cb6: 68fb ldr r3, [r7, #12] uint32_t primask_bit; uint8_t return_value; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 8012cb8: 613b str r3, [r7, #16] __ASM volatile ("cpsid i" : : : "memory"); 8012cba: b672 cpsid i } 8012cbc: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ if(listHead->next == listHead) 8012cbe: 687b ldr r3, [r7, #4] 8012cc0: 681b ldr r3, [r3, #0] 8012cc2: 687a ldr r2, [r7, #4] 8012cc4: 429a cmp r2, r3 8012cc6: d102 bne.n 8012cce { return_value = TRUE; 8012cc8: 2301 movs r3, #1 8012cca: 75fb strb r3, [r7, #23] 8012ccc: e001 b.n 8012cd2 } else { return_value = FALSE; 8012cce: 2300 movs r3, #0 8012cd0: 75fb strb r3, [r7, #23] 8012cd2: 693b ldr r3, [r7, #16] 8012cd4: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8012cd6: 68bb ldr r3, [r7, #8] 8012cd8: f383 8810 msr PRIMASK, r3 } 8012cdc: bf00 nop } __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ return return_value; 8012cde: 7dfb ldrb r3, [r7, #23] } 8012ce0: 4618 mov r0, r3 8012ce2: 371c adds r7, #28 8012ce4: 46bd mov sp, r7 8012ce6: f85d 7b04 ldr.w r7, [sp], #4 8012cea: 4770 bx lr 08012cec : void LST_insert_head (tListNode * listHead, tListNode * node) { 8012cec: b480 push {r7} 8012cee: b087 sub sp, #28 8012cf0: af00 add r7, sp, #0 8012cf2: 6078 str r0, [r7, #4] 8012cf4: 6039 str r1, [r7, #0] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8012cf6: f3ef 8310 mrs r3, PRIMASK 8012cfa: 60fb str r3, [r7, #12] return(result); 8012cfc: 68fb ldr r3, [r7, #12] uint32_t primask_bit; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 8012cfe: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 8012d00: b672 cpsid i } 8012d02: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ node->next = listHead->next; 8012d04: 687b ldr r3, [r7, #4] 8012d06: 681a ldr r2, [r3, #0] 8012d08: 683b ldr r3, [r7, #0] 8012d0a: 601a str r2, [r3, #0] node->prev = listHead; 8012d0c: 683b ldr r3, [r7, #0] 8012d0e: 687a ldr r2, [r7, #4] 8012d10: 605a str r2, [r3, #4] listHead->next = node; 8012d12: 687b ldr r3, [r7, #4] 8012d14: 683a ldr r2, [r7, #0] 8012d16: 601a str r2, [r3, #0] (node->next)->prev = node; 8012d18: 683b ldr r3, [r7, #0] 8012d1a: 681b ldr r3, [r3, #0] 8012d1c: 683a ldr r2, [r7, #0] 8012d1e: 605a str r2, [r3, #4] 8012d20: 697b ldr r3, [r7, #20] 8012d22: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8012d24: 693b ldr r3, [r7, #16] 8012d26: f383 8810 msr PRIMASK, r3 } 8012d2a: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ } 8012d2c: bf00 nop 8012d2e: 371c adds r7, #28 8012d30: 46bd mov sp, r7 8012d32: f85d 7b04 ldr.w r7, [sp], #4 8012d36: 4770 bx lr 08012d38 : void LST_insert_tail (tListNode * listHead, tListNode * node) { 8012d38: b480 push {r7} 8012d3a: b087 sub sp, #28 8012d3c: af00 add r7, sp, #0 8012d3e: 6078 str r0, [r7, #4] 8012d40: 6039 str r1, [r7, #0] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8012d42: f3ef 8310 mrs r3, PRIMASK 8012d46: 60fb str r3, [r7, #12] return(result); 8012d48: 68fb ldr r3, [r7, #12] uint32_t primask_bit; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 8012d4a: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 8012d4c: b672 cpsid i } 8012d4e: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ node->next = listHead; 8012d50: 683b ldr r3, [r7, #0] 8012d52: 687a ldr r2, [r7, #4] 8012d54: 601a str r2, [r3, #0] node->prev = listHead->prev; 8012d56: 687b ldr r3, [r7, #4] 8012d58: 685a ldr r2, [r3, #4] 8012d5a: 683b ldr r3, [r7, #0] 8012d5c: 605a str r2, [r3, #4] listHead->prev = node; 8012d5e: 687b ldr r3, [r7, #4] 8012d60: 683a ldr r2, [r7, #0] 8012d62: 605a str r2, [r3, #4] (node->prev)->next = node; 8012d64: 683b ldr r3, [r7, #0] 8012d66: 685b ldr r3, [r3, #4] 8012d68: 683a ldr r2, [r7, #0] 8012d6a: 601a str r2, [r3, #0] 8012d6c: 697b ldr r3, [r7, #20] 8012d6e: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8012d70: 693b ldr r3, [r7, #16] 8012d72: f383 8810 msr PRIMASK, r3 } 8012d76: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ } 8012d78: bf00 nop 8012d7a: 371c adds r7, #28 8012d7c: 46bd mov sp, r7 8012d7e: f85d 7b04 ldr.w r7, [sp], #4 8012d82: 4770 bx lr 08012d84 : void LST_remove_node (tListNode * node) { 8012d84: b480 push {r7} 8012d86: b087 sub sp, #28 8012d88: af00 add r7, sp, #0 8012d8a: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8012d8c: f3ef 8310 mrs r3, PRIMASK 8012d90: 60fb str r3, [r7, #12] return(result); 8012d92: 68fb ldr r3, [r7, #12] uint32_t primask_bit; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 8012d94: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 8012d96: b672 cpsid i } 8012d98: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ (node->prev)->next = node->next; 8012d9a: 687b ldr r3, [r7, #4] 8012d9c: 685b ldr r3, [r3, #4] 8012d9e: 687a ldr r2, [r7, #4] 8012da0: 6812 ldr r2, [r2, #0] 8012da2: 601a str r2, [r3, #0] (node->next)->prev = node->prev; 8012da4: 687b ldr r3, [r7, #4] 8012da6: 681b ldr r3, [r3, #0] 8012da8: 687a ldr r2, [r7, #4] 8012daa: 6852 ldr r2, [r2, #4] 8012dac: 605a str r2, [r3, #4] 8012dae: 697b ldr r3, [r7, #20] 8012db0: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8012db2: 693b ldr r3, [r7, #16] 8012db4: f383 8810 msr PRIMASK, r3 } 8012db8: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ } 8012dba: bf00 nop 8012dbc: 371c adds r7, #28 8012dbe: 46bd mov sp, r7 8012dc0: f85d 7b04 ldr.w r7, [sp], #4 8012dc4: 4770 bx lr 08012dc6 : void LST_remove_head (tListNode * listHead, tListNode ** node ) { 8012dc6: b580 push {r7, lr} 8012dc8: b086 sub sp, #24 8012dca: af00 add r7, sp, #0 8012dcc: 6078 str r0, [r7, #4] 8012dce: 6039 str r1, [r7, #0] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8012dd0: f3ef 8310 mrs r3, PRIMASK 8012dd4: 60fb str r3, [r7, #12] return(result); 8012dd6: 68fb ldr r3, [r7, #12] uint32_t primask_bit; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 8012dd8: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 8012dda: b672 cpsid i } 8012ddc: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ *node = listHead->next; 8012dde: 687b ldr r3, [r7, #4] 8012de0: 681a ldr r2, [r3, #0] 8012de2: 683b ldr r3, [r7, #0] 8012de4: 601a str r2, [r3, #0] LST_remove_node (listHead->next); 8012de6: 687b ldr r3, [r7, #4] 8012de8: 681b ldr r3, [r3, #0] 8012dea: 4618 mov r0, r3 8012dec: f7ff ffca bl 8012d84 8012df0: 697b ldr r3, [r7, #20] 8012df2: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8012df4: 693b ldr r3, [r7, #16] 8012df6: f383 8810 msr PRIMASK, r3 } 8012dfa: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ } 8012dfc: bf00 nop 8012dfe: 3718 adds r7, #24 8012e00: 46bd mov sp, r7 8012e02: bd80 pop {r7, pc} 08012e04 <__NVIC_SetPriority>: { 8012e04: b480 push {r7} 8012e06: b083 sub sp, #12 8012e08: af00 add r7, sp, #0 8012e0a: 4603 mov r3, r0 8012e0c: 6039 str r1, [r7, #0] 8012e0e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8012e10: f997 3007 ldrsb.w r3, [r7, #7] 8012e14: 2b00 cmp r3, #0 8012e16: db0a blt.n 8012e2e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8012e18: 683b ldr r3, [r7, #0] 8012e1a: b2da uxtb r2, r3 8012e1c: 490c ldr r1, [pc, #48] @ (8012e50 <__NVIC_SetPriority+0x4c>) 8012e1e: f997 3007 ldrsb.w r3, [r7, #7] 8012e22: 0112 lsls r2, r2, #4 8012e24: b2d2 uxtb r2, r2 8012e26: 440b add r3, r1 8012e28: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8012e2c: e00a b.n 8012e44 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8012e2e: 683b ldr r3, [r7, #0] 8012e30: b2da uxtb r2, r3 8012e32: 4908 ldr r1, [pc, #32] @ (8012e54 <__NVIC_SetPriority+0x50>) 8012e34: 79fb ldrb r3, [r7, #7] 8012e36: f003 030f and.w r3, r3, #15 8012e3a: 3b04 subs r3, #4 8012e3c: 0112 lsls r2, r2, #4 8012e3e: b2d2 uxtb r2, r2 8012e40: 440b add r3, r1 8012e42: 761a strb r2, [r3, #24] } 8012e44: bf00 nop 8012e46: 370c adds r7, #12 8012e48: 46bd mov sp, r7 8012e4a: f85d 7b04 ldr.w r7, [sp], #4 8012e4e: 4770 bx lr 8012e50: e000e100 .word 0xe000e100 8012e54: e000ed00 .word 0xe000ed00 08012e58 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 8012e58: b580 push {r7, lr} 8012e5a: af00 add r7, sp, #0 #if (configUSE_TICKLESS_IDLE == 0) /* Clear overflow flag */ SysTick->CTRL; 8012e5c: 4b05 ldr r3, [pc, #20] @ (8012e74 ) 8012e5e: 681b ldr r3, [r3, #0] #endif if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 8012e60: f002 ff62 bl 8015d28 8012e64: 4603 mov r3, r0 8012e66: 2b01 cmp r3, #1 8012e68: d001 beq.n 8012e6e /* Call tick handler */ xPortSysTickHandler(); 8012e6a: f004 fb0d bl 8017488 } } 8012e6e: bf00 nop 8012e70: bd80 pop {r7, pc} 8012e72: bf00 nop 8012e74: e000e010 .word 0xe000e010 08012e78 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 8012e78: b580 push {r7, lr} 8012e7a: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc instruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQn, 0U); 8012e7c: 2100 movs r1, #0 8012e7e: f06f 0004 mvn.w r0, #4 8012e82: f7ff ffbf bl 8012e04 <__NVIC_SetPriority> #endif } 8012e86: bf00 nop 8012e88: bd80 pop {r7, pc} 08012e8a : #endif /* Determine if CPU executes from interrupt context or if interrupts are masked. */ __STATIC_INLINE uint32_t IRQ_Context (void) { 8012e8a: b580 push {r7, lr} 8012e8c: b086 sub sp, #24 8012e8e: af00 add r7, sp, #0 uint32_t irq; BaseType_t state; irq = 0U; 8012e90: 2300 movs r3, #0 8012e92: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8012e94: f3ef 8305 mrs r3, IPSR 8012e98: 60fb str r3, [r7, #12] return(result); 8012e9a: 68fb ldr r3, [r7, #12] if (IS_IRQ_MODE()) { 8012e9c: 2b00 cmp r3, #0 8012e9e: d002 beq.n 8012ea6 /* Called from interrupt context */ irq = 1U; 8012ea0: 2301 movs r3, #1 8012ea2: 617b str r3, [r7, #20] 8012ea4: e013 b.n 8012ece } else { /* Get FreeRTOS scheduler state */ state = xTaskGetSchedulerState(); 8012ea6: f002 ff3f bl 8015d28 8012eaa: 6138 str r0, [r7, #16] if (state != taskSCHEDULER_NOT_STARTED) { 8012eac: 693b ldr r3, [r7, #16] 8012eae: 2b01 cmp r3, #1 8012eb0: d00d beq.n 8012ece __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8012eb2: f3ef 8310 mrs r3, PRIMASK 8012eb6: 60bb str r3, [r7, #8] return(result); 8012eb8: 68bb ldr r3, [r7, #8] /* Scheduler was started */ if (IS_IRQ_MASKED()) { 8012eba: 2b00 cmp r3, #0 8012ebc: d105 bne.n 8012eca __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 8012ebe: f3ef 8311 mrs r3, BASEPRI 8012ec2: 607b str r3, [r7, #4] return(result); 8012ec4: 687b ldr r3, [r7, #4] 8012ec6: 2b00 cmp r3, #0 8012ec8: d001 beq.n 8012ece /* Interrupts are masked */ irq = 1U; 8012eca: 2301 movs r3, #1 8012ecc: 617b str r3, [r7, #20] } } } /* Return context, 0: thread context, 1: IRQ context */ return (irq); 8012ece: 697b ldr r3, [r7, #20] } 8012ed0: 4618 mov r0, r3 8012ed2: 3718 adds r7, #24 8012ed4: 46bd mov sp, r7 8012ed6: bd80 pop {r7, pc} 08012ed8 : /* ==== Kernel Management Functions ==== */ /* Initialize the RTOS Kernel. */ osStatus_t osKernelInitialize (void) { 8012ed8: b580 push {r7, lr} 8012eda: b082 sub sp, #8 8012edc: af00 add r7, sp, #0 osStatus_t stat; BaseType_t state; if (IRQ_Context() != 0U) { 8012ede: f7ff ffd4 bl 8012e8a 8012ee2: 4603 mov r3, r0 8012ee4: 2b00 cmp r3, #0 8012ee6: d003 beq.n 8012ef0 stat = osErrorISR; 8012ee8: f06f 0305 mvn.w r3, #5 8012eec: 607b str r3, [r7, #4] 8012eee: e012 b.n 8012f16 } else { state = xTaskGetSchedulerState(); 8012ef0: f002 ff1a bl 8015d28 8012ef4: 6038 str r0, [r7, #0] /* Initialize if scheduler not started and not initialized before */ if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelInactive)) { 8012ef6: 683b ldr r3, [r7, #0] 8012ef8: 2b01 cmp r3, #1 8012efa: d109 bne.n 8012f10 8012efc: 4b08 ldr r3, [pc, #32] @ (8012f20 ) 8012efe: 681b ldr r3, [r3, #0] 8012f00: 2b00 cmp r3, #0 8012f02: d105 bne.n 8012f10 #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) /* Initialize the memory regions when using heap_5 variant */ vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 8012f04: 4b06 ldr r3, [pc, #24] @ (8012f20 ) 8012f06: 2201 movs r2, #1 8012f08: 601a str r2, [r3, #0] stat = osOK; 8012f0a: 2300 movs r3, #0 8012f0c: 607b str r3, [r7, #4] 8012f0e: e002 b.n 8012f16 } else { stat = osError; 8012f10: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8012f14: 607b str r3, [r7, #4] } } /* Return execution status */ return (stat); 8012f16: 687b ldr r3, [r7, #4] } 8012f18: 4618 mov r0, r3 8012f1a: 3708 adds r7, #8 8012f1c: 46bd mov sp, r7 8012f1e: bd80 pop {r7, pc} 8012f20: 200007cc .word 0x200007cc 08012f24 : } /* Start the RTOS Kernel scheduler. */ osStatus_t osKernelStart (void) { 8012f24: b580 push {r7, lr} 8012f26: b082 sub sp, #8 8012f28: af00 add r7, sp, #0 osStatus_t stat; BaseType_t state; if (IRQ_Context() != 0U) { 8012f2a: f7ff ffae bl 8012e8a 8012f2e: 4603 mov r3, r0 8012f30: 2b00 cmp r3, #0 8012f32: d003 beq.n 8012f3c stat = osErrorISR; 8012f34: f06f 0305 mvn.w r3, #5 8012f38: 607b str r3, [r7, #4] 8012f3a: e016 b.n 8012f6a } else { state = xTaskGetSchedulerState(); 8012f3c: f002 fef4 bl 8015d28 8012f40: 6038 str r0, [r7, #0] /* Start scheduler if initialized and not started before */ if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelReady)) { 8012f42: 683b ldr r3, [r7, #0] 8012f44: 2b01 cmp r3, #1 8012f46: d10d bne.n 8012f64 8012f48: 4b0a ldr r3, [pc, #40] @ (8012f74 ) 8012f4a: 681b ldr r3, [r3, #0] 8012f4c: 2b01 cmp r3, #1 8012f4e: d109 bne.n 8012f64 /* Ensure SVC priority is at the reset value */ SVC_Setup(); 8012f50: f7ff ff92 bl 8012e78 /* Change state to ensure correct API flow */ KernelState = osKernelRunning; 8012f54: 4b07 ldr r3, [pc, #28] @ (8012f74 ) 8012f56: 2202 movs r2, #2 8012f58: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 8012f5a: f002 f92b bl 80151b4 stat = osOK; 8012f5e: 2300 movs r3, #0 8012f60: 607b str r3, [r7, #4] 8012f62: e002 b.n 8012f6a } else { stat = osError; 8012f64: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8012f68: 607b str r3, [r7, #4] } } /* Return execution status */ return (stat); 8012f6a: 687b ldr r3, [r7, #4] } 8012f6c: 4618 mov r0, r3 8012f6e: 3708 adds r7, #8 8012f70: 46bd mov sp, r7 8012f72: bd80 pop {r7, pc} 8012f74: 200007cc .word 0x200007cc 08012f78 : Limitations: - The memory for control block and stack must be provided in the osThreadAttr_t structure in order to allocate object statically. - Attribute osThreadJoinable is not supported, NULL is returned if used. */ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 8012f78: b580 push {r7, lr} 8012f7a: b08e sub sp, #56 @ 0x38 8012f7c: af04 add r7, sp, #16 8012f7e: 60f8 str r0, [r7, #12] 8012f80: 60b9 str r1, [r7, #8] 8012f82: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 8012f84: 2300 movs r3, #0 8012f86: 617b str r3, [r7, #20] if ((IRQ_Context() == 0U) && (func != NULL)) { 8012f88: f7ff ff7f bl 8012e8a 8012f8c: 4603 mov r3, r0 8012f8e: 2b00 cmp r3, #0 8012f90: d17f bne.n 8013092 8012f92: 68fb ldr r3, [r7, #12] 8012f94: 2b00 cmp r3, #0 8012f96: d07c beq.n 8013092 stack = configMINIMAL_STACK_SIZE; 8012f98: f44f 7300 mov.w r3, #512 @ 0x200 8012f9c: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 8012f9e: 2318 movs r3, #24 8012fa0: 61fb str r3, [r7, #28] name = NULL; 8012fa2: 2300 movs r3, #0 8012fa4: 627b str r3, [r7, #36] @ 0x24 mem = -1; 8012fa6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8012faa: 61bb str r3, [r7, #24] if (attr != NULL) { 8012fac: 687b ldr r3, [r7, #4] 8012fae: 2b00 cmp r3, #0 8012fb0: d045 beq.n 801303e if (attr->name != NULL) { 8012fb2: 687b ldr r3, [r7, #4] 8012fb4: 681b ldr r3, [r3, #0] 8012fb6: 2b00 cmp r3, #0 8012fb8: d002 beq.n 8012fc0 name = attr->name; 8012fba: 687b ldr r3, [r7, #4] 8012fbc: 681b ldr r3, [r3, #0] 8012fbe: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 8012fc0: 687b ldr r3, [r7, #4] 8012fc2: 699b ldr r3, [r3, #24] 8012fc4: 2b00 cmp r3, #0 8012fc6: d002 beq.n 8012fce prio = (UBaseType_t)attr->priority; 8012fc8: 687b ldr r3, [r7, #4] 8012fca: 699b ldr r3, [r3, #24] 8012fcc: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 8012fce: 69fb ldr r3, [r7, #28] 8012fd0: 2b00 cmp r3, #0 8012fd2: d008 beq.n 8012fe6 8012fd4: 69fb ldr r3, [r7, #28] 8012fd6: 2b38 cmp r3, #56 @ 0x38 8012fd8: d805 bhi.n 8012fe6 8012fda: 687b ldr r3, [r7, #4] 8012fdc: 685b ldr r3, [r3, #4] 8012fde: f003 0301 and.w r3, r3, #1 8012fe2: 2b00 cmp r3, #0 8012fe4: d001 beq.n 8012fea /* Invalid priority or unsupported osThreadJoinable attribute used */ return (NULL); 8012fe6: 2300 movs r3, #0 8012fe8: e054 b.n 8013094 } if (attr->stack_size > 0U) { 8012fea: 687b ldr r3, [r7, #4] 8012fec: 695b ldr r3, [r3, #20] 8012fee: 2b00 cmp r3, #0 8012ff0: d003 beq.n 8012ffa /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 8012ff2: 687b ldr r3, [r7, #4] 8012ff4: 695b ldr r3, [r3, #20] 8012ff6: 089b lsrs r3, r3, #2 8012ff8: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 8012ffa: 687b ldr r3, [r7, #4] 8012ffc: 689b ldr r3, [r3, #8] 8012ffe: 2b00 cmp r3, #0 8013000: d00e beq.n 8013020 8013002: 687b ldr r3, [r7, #4] 8013004: 68db ldr r3, [r3, #12] 8013006: 2b5b cmp r3, #91 @ 0x5b 8013008: d90a bls.n 8013020 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 801300a: 687b ldr r3, [r7, #4] 801300c: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 801300e: 2b00 cmp r3, #0 8013010: d006 beq.n 8013020 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 8013012: 687b ldr r3, [r7, #4] 8013014: 695b ldr r3, [r3, #20] 8013016: 2b00 cmp r3, #0 8013018: d002 beq.n 8013020 /* The memory for control block and stack is provided, use static object */ mem = 1; 801301a: 2301 movs r3, #1 801301c: 61bb str r3, [r7, #24] 801301e: e010 b.n 8013042 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 8013020: 687b ldr r3, [r7, #4] 8013022: 689b ldr r3, [r3, #8] 8013024: 2b00 cmp r3, #0 8013026: d10c bne.n 8013042 8013028: 687b ldr r3, [r7, #4] 801302a: 68db ldr r3, [r3, #12] 801302c: 2b00 cmp r3, #0 801302e: d108 bne.n 8013042 8013030: 687b ldr r3, [r7, #4] 8013032: 691b ldr r3, [r3, #16] 8013034: 2b00 cmp r3, #0 8013036: d104 bne.n 8013042 /* Control block and stack memory will be allocated from the dynamic pool */ mem = 0; 8013038: 2300 movs r3, #0 801303a: 61bb str r3, [r7, #24] 801303c: e001 b.n 8013042 } } } else { mem = 0; 801303e: 2300 movs r3, #0 8013040: 61bb str r3, [r7, #24] } if (mem == 1) { 8013042: 69bb ldr r3, [r7, #24] 8013044: 2b01 cmp r3, #1 8013046: d110 bne.n 801306a #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8013048: 687b ldr r3, [r7, #4] 801304a: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 801304c: 687a ldr r2, [r7, #4] 801304e: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8013050: 9202 str r2, [sp, #8] 8013052: 9301 str r3, [sp, #4] 8013054: 69fb ldr r3, [r7, #28] 8013056: 9300 str r3, [sp, #0] 8013058: 68bb ldr r3, [r7, #8] 801305a: 6a3a ldr r2, [r7, #32] 801305c: 6a79 ldr r1, [r7, #36] @ 0x24 801305e: 68f8 ldr r0, [r7, #12] 8013060: f001 fe9a bl 8014d98 8013064: 4603 mov r3, r0 8013066: 617b str r3, [r7, #20] 8013068: e013 b.n 8013092 #endif } else { if (mem == 0) { 801306a: 69bb ldr r3, [r7, #24] 801306c: 2b00 cmp r3, #0 801306e: d110 bne.n 8013092 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (configSTACK_DEPTH_TYPE)stack, argument, prio, &hTask) != pdPASS) { 8013070: 6a3b ldr r3, [r7, #32] 8013072: b29a uxth r2, r3 8013074: f107 0314 add.w r3, r7, #20 8013078: 9301 str r3, [sp, #4] 801307a: 69fb ldr r3, [r7, #28] 801307c: 9300 str r3, [sp, #0] 801307e: 68bb ldr r3, [r7, #8] 8013080: 6a79 ldr r1, [r7, #36] @ 0x24 8013082: 68f8 ldr r0, [r7, #12] 8013084: f001 feed bl 8014e62 8013088: 4603 mov r3, r0 801308a: 2b01 cmp r3, #1 801308c: d001 beq.n 8013092 hTask = NULL; 801308e: 2300 movs r3, #0 8013090: 617b str r3, [r7, #20] } } } /* Return thread ID */ return ((osThreadId_t)hTask); 8013092: 697b ldr r3, [r7, #20] } 8013094: 4618 mov r0, r3 8013096: 3728 adds r7, #40 @ 0x28 8013098: 46bd mov sp, r7 801309a: bd80 pop {r7, pc} 0801309c : } /* Return the thread ID of the current running thread. */ osThreadId_t osThreadGetId (void) { 801309c: b580 push {r7, lr} 801309e: b082 sub sp, #8 80130a0: af00 add r7, sp, #0 osThreadId_t id; id = (osThreadId_t)xTaskGetCurrentTaskHandle(); 80130a2: f002 fe31 bl 8015d08 80130a6: 6078 str r0, [r7, #4] /* Return thread ID */ return (id); 80130a8: 687b ldr r3, [r7, #4] } 80130aa: 4618 mov r0, r3 80130ac: 3708 adds r7, #8 80130ae: 46bd mov sp, r7 80130b0: bd80 pop {r7, pc} ... 080130b4 : #if (configUSE_OS2_THREAD_FLAGS == 1) /* Set the specified Thread Flags of a thread. */ uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { 80130b4: b580 push {r7, lr} 80130b6: b088 sub sp, #32 80130b8: af02 add r7, sp, #8 80130ba: 6078 str r0, [r7, #4] 80130bc: 6039 str r1, [r7, #0] TaskHandle_t hTask = (TaskHandle_t)thread_id; 80130be: 687b ldr r3, [r7, #4] 80130c0: 617b str r3, [r7, #20] uint32_t rflags; BaseType_t yield; if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) { 80130c2: 697b ldr r3, [r7, #20] 80130c4: 2b00 cmp r3, #0 80130c6: d002 beq.n 80130ce 80130c8: 683b ldr r3, [r7, #0] 80130ca: 2b00 cmp r3, #0 80130cc: da03 bge.n 80130d6 rflags = (uint32_t)osErrorParameter; 80130ce: f06f 0303 mvn.w r3, #3 80130d2: 613b str r3, [r7, #16] 80130d4: e03c b.n 8013150 } else { rflags = (uint32_t)osError; 80130d6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80130da: 613b str r3, [r7, #16] if (IRQ_Context() != 0U) { 80130dc: f7ff fed5 bl 8012e8a 80130e0: 4603 mov r3, r0 80130e2: 2b00 cmp r3, #0 80130e4: d023 beq.n 801312e yield = pdFALSE; 80130e6: 2300 movs r3, #0 80130e8: 60fb str r3, [r7, #12] (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield); 80130ea: f107 030c add.w r3, r7, #12 80130ee: 9301 str r3, [sp, #4] 80130f0: 2300 movs r3, #0 80130f2: 9300 str r3, [sp, #0] 80130f4: 2301 movs r3, #1 80130f6: 683a ldr r2, [r7, #0] 80130f8: 2100 movs r1, #0 80130fa: 6978 ldr r0, [r7, #20] 80130fc: f003 fa3a bl 8016574 (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL); 8013100: 2300 movs r3, #0 8013102: 9301 str r3, [sp, #4] 8013104: f107 0310 add.w r3, r7, #16 8013108: 9300 str r3, [sp, #0] 801310a: 2300 movs r3, #0 801310c: 2200 movs r2, #0 801310e: 2100 movs r1, #0 8013110: 6978 ldr r0, [r7, #20] 8013112: f003 fa2f bl 8016574 portYIELD_FROM_ISR (yield); 8013116: 68fb ldr r3, [r7, #12] 8013118: 2b00 cmp r3, #0 801311a: d019 beq.n 8013150 801311c: 4b0f ldr r3, [pc, #60] @ (801315c ) 801311e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013122: 601a str r2, [r3, #0] 8013124: f3bf 8f4f dsb sy 8013128: f3bf 8f6f isb sy 801312c: e010 b.n 8013150 } else { (void)xTaskNotify (hTask, flags, eSetBits); 801312e: 2300 movs r3, #0 8013130: 9300 str r3, [sp, #0] 8013132: 2301 movs r3, #1 8013134: 683a ldr r2, [r7, #0] 8013136: 2100 movs r1, #0 8013138: 6978 ldr r0, [r7, #20] 801313a: f003 f8ed bl 8016318 (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags); 801313e: f107 0310 add.w r3, r7, #16 8013142: 9300 str r3, [sp, #0] 8013144: 2300 movs r3, #0 8013146: 2200 movs r2, #0 8013148: 2100 movs r1, #0 801314a: 6978 ldr r0, [r7, #20] 801314c: f003 f8e4 bl 8016318 } } /* Return flags after setting */ return (rflags); 8013150: 693b ldr r3, [r7, #16] } 8013152: 4618 mov r0, r3 8013154: 3718 adds r7, #24 8013156: 46bd mov sp, r7 8013158: bd80 pop {r7, pc} 801315a: bf00 nop 801315c: e000ed04 .word 0xe000ed04 08013160 : } /* Wait for one or more Thread Flags of the current running thread to become signaled. */ uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { 8013160: b580 push {r7, lr} 8013162: b08e sub sp, #56 @ 0x38 8013164: af02 add r7, sp, #8 8013166: 60f8 str r0, [r7, #12] 8013168: 60b9 str r1, [r7, #8] 801316a: 607a str r2, [r7, #4] uint32_t rflags, nval; uint32_t clear; TickType_t t0, td, tout; BaseType_t rval; if (IRQ_Context() != 0U) { 801316c: f7ff fe8d bl 8012e8a 8013170: 4603 mov r3, r0 8013172: 2b00 cmp r3, #0 8013174: d003 beq.n 801317e rflags = (uint32_t)osErrorISR; 8013176: f06f 0305 mvn.w r3, #5 801317a: 62fb str r3, [r7, #44] @ 0x2c 801317c: e06e b.n 801325c } else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { 801317e: 68fb ldr r3, [r7, #12] 8013180: 2b00 cmp r3, #0 8013182: da03 bge.n 801318c rflags = (uint32_t)osErrorParameter; 8013184: f06f 0303 mvn.w r3, #3 8013188: 62fb str r3, [r7, #44] @ 0x2c 801318a: e067 b.n 801325c } else { if ((options & osFlagsNoClear) == osFlagsNoClear) { 801318c: 68bb ldr r3, [r7, #8] 801318e: f003 0302 and.w r3, r3, #2 8013192: 2b00 cmp r3, #0 8013194: d002 beq.n 801319c clear = 0U; 8013196: 2300 movs r3, #0 8013198: 62bb str r3, [r7, #40] @ 0x28 801319a: e001 b.n 80131a0 } else { clear = flags; 801319c: 68fb ldr r3, [r7, #12] 801319e: 62bb str r3, [r7, #40] @ 0x28 } rflags = 0U; 80131a0: 2300 movs r3, #0 80131a2: 62fb str r3, [r7, #44] @ 0x2c tout = timeout; 80131a4: 687b ldr r3, [r7, #4] 80131a6: 627b str r3, [r7, #36] @ 0x24 t0 = xTaskGetTickCount(); 80131a8: f002 f97c bl 80154a4 80131ac: 6238 str r0, [r7, #32] do { rval = xTaskNotifyWait (0, clear, &nval, tout); 80131ae: f107 0214 add.w r2, r7, #20 80131b2: 6a7b ldr r3, [r7, #36] @ 0x24 80131b4: 9300 str r3, [sp, #0] 80131b6: 4613 mov r3, r2 80131b8: 6aba ldr r2, [r7, #40] @ 0x28 80131ba: 2100 movs r1, #0 80131bc: 2000 movs r0, #0 80131be: f003 f825 bl 801620c 80131c2: 61f8 str r0, [r7, #28] if (rval == pdPASS) { 80131c4: 69fb ldr r3, [r7, #28] 80131c6: 2b01 cmp r3, #1 80131c8: d137 bne.n 801323a rflags &= flags; 80131ca: 6afa ldr r2, [r7, #44] @ 0x2c 80131cc: 68fb ldr r3, [r7, #12] 80131ce: 4013 ands r3, r2 80131d0: 62fb str r3, [r7, #44] @ 0x2c rflags |= nval; 80131d2: 697b ldr r3, [r7, #20] 80131d4: 6afa ldr r2, [r7, #44] @ 0x2c 80131d6: 4313 orrs r3, r2 80131d8: 62fb str r3, [r7, #44] @ 0x2c if ((options & osFlagsWaitAll) == osFlagsWaitAll) { 80131da: 68bb ldr r3, [r7, #8] 80131dc: f003 0301 and.w r3, r3, #1 80131e0: 2b00 cmp r3, #0 80131e2: d00c beq.n 80131fe if ((flags & rflags) == flags) { 80131e4: 68fa ldr r2, [r7, #12] 80131e6: 6afb ldr r3, [r7, #44] @ 0x2c 80131e8: 4013 ands r3, r2 80131ea: 68fa ldr r2, [r7, #12] 80131ec: 429a cmp r2, r3 80131ee: d032 beq.n 8013256 break; } else { if (timeout == 0U) { 80131f0: 687b ldr r3, [r7, #4] 80131f2: 2b00 cmp r3, #0 80131f4: d10f bne.n 8013216 rflags = (uint32_t)osErrorResource; 80131f6: f06f 0302 mvn.w r3, #2 80131fa: 62fb str r3, [r7, #44] @ 0x2c break; 80131fc: e02e b.n 801325c } } } else { if ((flags & rflags) != 0) { 80131fe: 68fa ldr r2, [r7, #12] 8013200: 6afb ldr r3, [r7, #44] @ 0x2c 8013202: 4013 ands r3, r2 8013204: 2b00 cmp r3, #0 8013206: d128 bne.n 801325a break; } else { if (timeout == 0U) { 8013208: 687b ldr r3, [r7, #4] 801320a: 2b00 cmp r3, #0 801320c: d103 bne.n 8013216 rflags = (uint32_t)osErrorResource; 801320e: f06f 0302 mvn.w r3, #2 8013212: 62fb str r3, [r7, #44] @ 0x2c break; 8013214: e022 b.n 801325c } } } /* Update timeout */ td = xTaskGetTickCount() - t0; 8013216: f002 f945 bl 80154a4 801321a: 4602 mov r2, r0 801321c: 6a3b ldr r3, [r7, #32] 801321e: 1ad3 subs r3, r2, r3 8013220: 61bb str r3, [r7, #24] if (td > timeout) { 8013222: 69ba ldr r2, [r7, #24] 8013224: 687b ldr r3, [r7, #4] 8013226: 429a cmp r2, r3 8013228: d902 bls.n 8013230 tout = 0; 801322a: 2300 movs r3, #0 801322c: 627b str r3, [r7, #36] @ 0x24 801322e: e00e b.n 801324e } else { tout = timeout - td; 8013230: 687a ldr r2, [r7, #4] 8013232: 69bb ldr r3, [r7, #24] 8013234: 1ad3 subs r3, r2, r3 8013236: 627b str r3, [r7, #36] @ 0x24 8013238: e009 b.n 801324e } } else { if (timeout == 0) { 801323a: 687b ldr r3, [r7, #4] 801323c: 2b00 cmp r3, #0 801323e: d103 bne.n 8013248 rflags = (uint32_t)osErrorResource; 8013240: f06f 0302 mvn.w r3, #2 8013244: 62fb str r3, [r7, #44] @ 0x2c 8013246: e002 b.n 801324e } else { rflags = (uint32_t)osErrorTimeout; 8013248: f06f 0301 mvn.w r3, #1 801324c: 62fb str r3, [r7, #44] @ 0x2c } } } while (rval != pdFAIL); 801324e: 69fb ldr r3, [r7, #28] 8013250: 2b00 cmp r3, #0 8013252: d1ac bne.n 80131ae 8013254: e002 b.n 801325c break; 8013256: bf00 nop 8013258: e000 b.n 801325c break; 801325a: bf00 nop } /* Return flags before clearing */ return (rflags); 801325c: 6afb ldr r3, [r7, #44] @ 0x2c } 801325e: 4618 mov r0, r3 8013260: 3730 adds r7, #48 @ 0x30 8013262: 46bd mov sp, r7 8013264: bd80 pop {r7, pc} 08013266 : /* ==== Generic Wait Functions ==== */ /* Wait for Timeout (Time Delay). */ osStatus_t osDelay (uint32_t ticks) { 8013266: b580 push {r7, lr} 8013268: b084 sub sp, #16 801326a: af00 add r7, sp, #0 801326c: 6078 str r0, [r7, #4] osStatus_t stat; if (IRQ_Context() != 0U) { 801326e: f7ff fe0c bl 8012e8a 8013272: 4603 mov r3, r0 8013274: 2b00 cmp r3, #0 8013276: d003 beq.n 8013280 stat = osErrorISR; 8013278: f06f 0305 mvn.w r3, #5 801327c: 60fb str r3, [r7, #12] 801327e: e007 b.n 8013290 } else { stat = osOK; 8013280: 2300 movs r3, #0 8013282: 60fb str r3, [r7, #12] if (ticks != 0U) { 8013284: 687b ldr r3, [r7, #4] 8013286: 2b00 cmp r3, #0 8013288: d002 beq.n 8013290 vTaskDelay(ticks); 801328a: 6878 ldr r0, [r7, #4] 801328c: f001 ff5c bl 8015148 } } /* Return execution status */ return (stat); 8013290: 68fb ldr r3, [r7, #12] } 8013292: 4618 mov r0, r3 8013294: 3710 adds r7, #16 8013296: 46bd mov sp, r7 8013298: bd80 pop {r7, pc} 0801329a : Limitations: - Priority inherit protocol is used by default, osMutexPrioInherit attribute is ignored. - Robust mutex is not supported, NULL is returned if used. */ osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 801329a: b580 push {r7, lr} 801329c: b086 sub sp, #24 801329e: af00 add r7, sp, #0 80132a0: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; uint32_t type; uint32_t rmtx; int32_t mem; hMutex = NULL; 80132a2: 2300 movs r3, #0 80132a4: 617b str r3, [r7, #20] if (IRQ_Context() == 0U) { 80132a6: f7ff fdf0 bl 8012e8a 80132aa: 4603 mov r3, r0 80132ac: 2b00 cmp r3, #0 80132ae: d174 bne.n 801339a if (attr != NULL) { 80132b0: 687b ldr r3, [r7, #4] 80132b2: 2b00 cmp r3, #0 80132b4: d003 beq.n 80132be type = attr->attr_bits; 80132b6: 687b ldr r3, [r7, #4] 80132b8: 685b ldr r3, [r3, #4] 80132ba: 613b str r3, [r7, #16] 80132bc: e001 b.n 80132c2 } else { type = 0U; 80132be: 2300 movs r3, #0 80132c0: 613b str r3, [r7, #16] } if ((type & osMutexRecursive) == osMutexRecursive) { 80132c2: 693b ldr r3, [r7, #16] 80132c4: f003 0301 and.w r3, r3, #1 80132c8: 2b00 cmp r3, #0 80132ca: d002 beq.n 80132d2 rmtx = 1U; 80132cc: 2301 movs r3, #1 80132ce: 60fb str r3, [r7, #12] 80132d0: e001 b.n 80132d6 } else { rmtx = 0U; 80132d2: 2300 movs r3, #0 80132d4: 60fb str r3, [r7, #12] } if ((type & osMutexRobust) != osMutexRobust) { 80132d6: 693b ldr r3, [r7, #16] 80132d8: f003 0308 and.w r3, r3, #8 80132dc: 2b00 cmp r3, #0 80132de: d15c bne.n 801339a mem = -1; 80132e0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80132e4: 60bb str r3, [r7, #8] if (attr != NULL) { 80132e6: 687b ldr r3, [r7, #4] 80132e8: 2b00 cmp r3, #0 80132ea: d015 beq.n 8013318 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 80132ec: 687b ldr r3, [r7, #4] 80132ee: 689b ldr r3, [r3, #8] 80132f0: 2b00 cmp r3, #0 80132f2: d006 beq.n 8013302 80132f4: 687b ldr r3, [r7, #4] 80132f6: 68db ldr r3, [r3, #12] 80132f8: 2b4f cmp r3, #79 @ 0x4f 80132fa: d902 bls.n 8013302 /* The memory for control block is provided, use static object */ mem = 1; 80132fc: 2301 movs r3, #1 80132fe: 60bb str r3, [r7, #8] 8013300: e00c b.n 801331c } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8013302: 687b ldr r3, [r7, #4] 8013304: 689b ldr r3, [r3, #8] 8013306: 2b00 cmp r3, #0 8013308: d108 bne.n 801331c 801330a: 687b ldr r3, [r7, #4] 801330c: 68db ldr r3, [r3, #12] 801330e: 2b00 cmp r3, #0 8013310: d104 bne.n 801331c /* Control block will be allocated from the dynamic pool */ mem = 0; 8013312: 2300 movs r3, #0 8013314: 60bb str r3, [r7, #8] 8013316: e001 b.n 801331c } } } else { mem = 0; 8013318: 2300 movs r3, #0 801331a: 60bb str r3, [r7, #8] } if (mem == 1) { 801331c: 68bb ldr r3, [r7, #8] 801331e: 2b01 cmp r3, #1 8013320: d112 bne.n 8013348 #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 8013322: 68fb ldr r3, [r7, #12] 8013324: 2b00 cmp r3, #0 8013326: d007 beq.n 8013338 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 8013328: 687b ldr r3, [r7, #4] 801332a: 689b ldr r3, [r3, #8] 801332c: 4619 mov r1, r3 801332e: 2004 movs r0, #4 8013330: f000 fd63 bl 8013dfa 8013334: 6178 str r0, [r7, #20] 8013336: e016 b.n 8013366 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 8013338: 687b ldr r3, [r7, #4] 801333a: 689b ldr r3, [r3, #8] 801333c: 4619 mov r1, r3 801333e: 2001 movs r0, #1 8013340: f000 fd5b bl 8013dfa 8013344: 6178 str r0, [r7, #20] 8013346: e00e b.n 8013366 } #endif } else { if (mem == 0) { 8013348: 68bb ldr r3, [r7, #8] 801334a: 2b00 cmp r3, #0 801334c: d10b bne.n 8013366 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 801334e: 68fb ldr r3, [r7, #12] 8013350: 2b00 cmp r3, #0 8013352: d004 beq.n 801335e #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 8013354: 2004 movs r0, #4 8013356: f000 fd38 bl 8013dca 801335a: 6178 str r0, [r7, #20] 801335c: e003 b.n 8013366 #endif } else { hMutex = xSemaphoreCreateMutex (); 801335e: 2001 movs r0, #1 8013360: f000 fd33 bl 8013dca 8013364: 6178 str r0, [r7, #20] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8013366: 697b ldr r3, [r7, #20] 8013368: 2b00 cmp r3, #0 801336a: d00c beq.n 8013386 if ((attr != NULL) && (attr->name != NULL)) { 801336c: 687b ldr r3, [r7, #4] 801336e: 2b00 cmp r3, #0 8013370: d009 beq.n 8013386 8013372: 687b ldr r3, [r7, #4] 8013374: 681b ldr r3, [r3, #0] 8013376: 2b00 cmp r3, #0 8013378: d005 beq.n 8013386 /* Only non-NULL name objects are added to the Queue Registry */ vQueueAddToRegistry (hMutex, attr->name); 801337a: 687b ldr r3, [r7, #4] 801337c: 681b ldr r3, [r3, #0] 801337e: 4619 mov r1, r3 8013380: 6978 ldr r0, [r7, #20] 8013382: f001 fc4b bl 8014c1c } } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 8013386: 697b ldr r3, [r7, #20] 8013388: 2b00 cmp r3, #0 801338a: d006 beq.n 801339a 801338c: 68fb ldr r3, [r7, #12] 801338e: 2b00 cmp r3, #0 8013390: d003 beq.n 801339a /* Set LSB as 'recursive mutex flag' */ hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 8013392: 697b ldr r3, [r7, #20] 8013394: f043 0301 orr.w r3, r3, #1 8013398: 617b str r3, [r7, #20] } } } /* Return mutex ID */ return ((osMutexId_t)hMutex); 801339a: 697b ldr r3, [r7, #20] } 801339c: 4618 mov r0, r3 801339e: 3718 adds r7, #24 80133a0: 46bd mov sp, r7 80133a2: bd80 pop {r7, pc} 080133a4 : /* Acquire a Mutex or timeout if it is locked. */ osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 80133a4: b580 push {r7, lr} 80133a6: b086 sub sp, #24 80133a8: af00 add r7, sp, #0 80133aa: 6078 str r0, [r7, #4] 80133ac: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 80133ae: 687b ldr r3, [r7, #4] 80133b0: f023 0301 bic.w r3, r3, #1 80133b4: 613b str r3, [r7, #16] /* Extract recursive mutex flag */ rmtx = (uint32_t)mutex_id & 1U; 80133b6: 687b ldr r3, [r7, #4] 80133b8: f003 0301 and.w r3, r3, #1 80133bc: 60fb str r3, [r7, #12] stat = osOK; 80133be: 2300 movs r3, #0 80133c0: 617b str r3, [r7, #20] if (IRQ_Context() != 0U) { 80133c2: f7ff fd62 bl 8012e8a 80133c6: 4603 mov r3, r0 80133c8: 2b00 cmp r3, #0 80133ca: d003 beq.n 80133d4 stat = osErrorISR; 80133cc: f06f 0305 mvn.w r3, #5 80133d0: 617b str r3, [r7, #20] 80133d2: e02c b.n 801342e } else if (hMutex == NULL) { 80133d4: 693b ldr r3, [r7, #16] 80133d6: 2b00 cmp r3, #0 80133d8: d103 bne.n 80133e2 stat = osErrorParameter; 80133da: f06f 0303 mvn.w r3, #3 80133de: 617b str r3, [r7, #20] 80133e0: e025 b.n 801342e } else { if (rmtx != 0U) { 80133e2: 68fb ldr r3, [r7, #12] 80133e4: 2b00 cmp r3, #0 80133e6: d011 beq.n 801340c #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 80133e8: 6839 ldr r1, [r7, #0] 80133ea: 6938 ldr r0, [r7, #16] 80133ec: f000 fd55 bl 8013e9a 80133f0: 4603 mov r3, r0 80133f2: 2b01 cmp r3, #1 80133f4: d01b beq.n 801342e if (timeout != 0U) { 80133f6: 683b ldr r3, [r7, #0] 80133f8: 2b00 cmp r3, #0 80133fa: d003 beq.n 8013404 stat = osErrorTimeout; 80133fc: f06f 0301 mvn.w r3, #1 8013400: 617b str r3, [r7, #20] 8013402: e014 b.n 801342e } else { stat = osErrorResource; 8013404: f06f 0302 mvn.w r3, #2 8013408: 617b str r3, [r7, #20] 801340a: e010 b.n 801342e } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 801340c: 6839 ldr r1, [r7, #0] 801340e: 6938 ldr r0, [r7, #16] 8013410: f001 f91e bl 8014650 8013414: 4603 mov r3, r0 8013416: 2b01 cmp r3, #1 8013418: d009 beq.n 801342e if (timeout != 0U) { 801341a: 683b ldr r3, [r7, #0] 801341c: 2b00 cmp r3, #0 801341e: d003 beq.n 8013428 stat = osErrorTimeout; 8013420: f06f 0301 mvn.w r3, #1 8013424: 617b str r3, [r7, #20] 8013426: e002 b.n 801342e } else { stat = osErrorResource; 8013428: f06f 0302 mvn.w r3, #2 801342c: 617b str r3, [r7, #20] } } } /* Return execution status */ return (stat); 801342e: 697b ldr r3, [r7, #20] } 8013430: 4618 mov r0, r3 8013432: 3718 adds r7, #24 8013434: 46bd mov sp, r7 8013436: bd80 pop {r7, pc} 08013438 : /* Release a Mutex that was acquired by osMutexAcquire. */ osStatus_t osMutexRelease (osMutexId_t mutex_id) { 8013438: b580 push {r7, lr} 801343a: b086 sub sp, #24 801343c: af00 add r7, sp, #0 801343e: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8013440: 687b ldr r3, [r7, #4] 8013442: f023 0301 bic.w r3, r3, #1 8013446: 613b str r3, [r7, #16] /* Extract recursive mutex flag */ rmtx = (uint32_t)mutex_id & 1U; 8013448: 687b ldr r3, [r7, #4] 801344a: f003 0301 and.w r3, r3, #1 801344e: 60fb str r3, [r7, #12] stat = osOK; 8013450: 2300 movs r3, #0 8013452: 617b str r3, [r7, #20] if (IRQ_Context() != 0U) { 8013454: f7ff fd19 bl 8012e8a 8013458: 4603 mov r3, r0 801345a: 2b00 cmp r3, #0 801345c: d003 beq.n 8013466 stat = osErrorISR; 801345e: f06f 0305 mvn.w r3, #5 8013462: 617b str r3, [r7, #20] 8013464: e01f b.n 80134a6 } else if (hMutex == NULL) { 8013466: 693b ldr r3, [r7, #16] 8013468: 2b00 cmp r3, #0 801346a: d103 bne.n 8013474 stat = osErrorParameter; 801346c: f06f 0303 mvn.w r3, #3 8013470: 617b str r3, [r7, #20] 8013472: e018 b.n 80134a6 } else { if (rmtx != 0U) { 8013474: 68fb ldr r3, [r7, #12] 8013476: 2b00 cmp r3, #0 8013478: d009 beq.n 801348e #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 801347a: 6938 ldr r0, [r7, #16] 801347c: f000 fcd8 bl 8013e30 8013480: 4603 mov r3, r0 8013482: 2b01 cmp r3, #1 8013484: d00f beq.n 80134a6 stat = osErrorResource; 8013486: f06f 0302 mvn.w r3, #2 801348a: 617b str r3, [r7, #20] 801348c: e00b b.n 80134a6 } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 801348e: 2300 movs r3, #0 8013490: 2200 movs r2, #0 8013492: 2100 movs r1, #0 8013494: 6938 ldr r0, [r7, #16] 8013496: f000 fd99 bl 8013fcc 801349a: 4603 mov r3, r0 801349c: 2b01 cmp r3, #1 801349e: d002 beq.n 80134a6 stat = osErrorResource; 80134a0: f06f 0302 mvn.w r3, #2 80134a4: 617b str r3, [r7, #20] } } } /* Return execution status */ return (stat); 80134a6: 697b ldr r3, [r7, #20] } 80134a8: 4618 mov r0, r3 80134aa: 3718 adds r7, #24 80134ac: 46bd mov sp, r7 80134ae: bd80 pop {r7, pc} 080134b0 : /* ==== Semaphore Management Functions ==== */ /* Create and Initialize a Semaphore object. */ osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { 80134b0: b580 push {r7, lr} 80134b2: b088 sub sp, #32 80134b4: af02 add r7, sp, #8 80134b6: 60f8 str r0, [r7, #12] 80134b8: 60b9 str r1, [r7, #8] 80134ba: 607a str r2, [r7, #4] SemaphoreHandle_t hSemaphore; int32_t mem; hSemaphore = NULL; 80134bc: 2300 movs r3, #0 80134be: 617b str r3, [r7, #20] if ((IRQ_Context() == 0U) && (max_count > 0U) && (initial_count <= max_count)) { 80134c0: f7ff fce3 bl 8012e8a 80134c4: 4603 mov r3, r0 80134c6: 2b00 cmp r3, #0 80134c8: d175 bne.n 80135b6 80134ca: 68fb ldr r3, [r7, #12] 80134cc: 2b00 cmp r3, #0 80134ce: d072 beq.n 80135b6 80134d0: 68ba ldr r2, [r7, #8] 80134d2: 68fb ldr r3, [r7, #12] 80134d4: 429a cmp r2, r3 80134d6: d86e bhi.n 80135b6 mem = -1; 80134d8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80134dc: 613b str r3, [r7, #16] if (attr != NULL) { 80134de: 687b ldr r3, [r7, #4] 80134e0: 2b00 cmp r3, #0 80134e2: d015 beq.n 8013510 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 80134e4: 687b ldr r3, [r7, #4] 80134e6: 689b ldr r3, [r3, #8] 80134e8: 2b00 cmp r3, #0 80134ea: d006 beq.n 80134fa 80134ec: 687b ldr r3, [r7, #4] 80134ee: 68db ldr r3, [r3, #12] 80134f0: 2b4f cmp r3, #79 @ 0x4f 80134f2: d902 bls.n 80134fa /* The memory for control block is provided, use static object */ mem = 1; 80134f4: 2301 movs r3, #1 80134f6: 613b str r3, [r7, #16] 80134f8: e00c b.n 8013514 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 80134fa: 687b ldr r3, [r7, #4] 80134fc: 689b ldr r3, [r3, #8] 80134fe: 2b00 cmp r3, #0 8013500: d108 bne.n 8013514 8013502: 687b ldr r3, [r7, #4] 8013504: 68db ldr r3, [r3, #12] 8013506: 2b00 cmp r3, #0 8013508: d104 bne.n 8013514 /* Control block will be allocated from the dynamic pool */ mem = 0; 801350a: 2300 movs r3, #0 801350c: 613b str r3, [r7, #16] 801350e: e001 b.n 8013514 } } } else { mem = 0; 8013510: 2300 movs r3, #0 8013512: 613b str r3, [r7, #16] } if (mem != -1) { 8013514: 693b ldr r3, [r7, #16] 8013516: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801351a: d04c beq.n 80135b6 if (max_count == 1U) { 801351c: 68fb ldr r3, [r7, #12] 801351e: 2b01 cmp r3, #1 8013520: d128 bne.n 8013574 if (mem == 1) { 8013522: 693b ldr r3, [r7, #16] 8013524: 2b01 cmp r3, #1 8013526: d10a bne.n 801353e #if (configSUPPORT_STATIC_ALLOCATION == 1) hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem); 8013528: 687b ldr r3, [r7, #4] 801352a: 689b ldr r3, [r3, #8] 801352c: 2203 movs r2, #3 801352e: 9200 str r2, [sp, #0] 8013530: 2200 movs r2, #0 8013532: 2100 movs r1, #0 8013534: 2001 movs r0, #1 8013536: f000 fb57 bl 8013be8 801353a: 6178 str r0, [r7, #20] 801353c: e005 b.n 801354a #endif } else { #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hSemaphore = xSemaphoreCreateBinary(); 801353e: 2203 movs r2, #3 8013540: 2100 movs r1, #0 8013542: 2001 movs r0, #1 8013544: f000 fbb1 bl 8013caa 8013548: 6178 str r0, [r7, #20] #endif } if ((hSemaphore != NULL) && (initial_count != 0U)) { 801354a: 697b ldr r3, [r7, #20] 801354c: 2b00 cmp r3, #0 801354e: d022 beq.n 8013596 8013550: 68bb ldr r3, [r7, #8] 8013552: 2b00 cmp r3, #0 8013554: d01f beq.n 8013596 if (xSemaphoreGive (hSemaphore) != pdPASS) { 8013556: 2300 movs r3, #0 8013558: 2200 movs r2, #0 801355a: 2100 movs r1, #0 801355c: 6978 ldr r0, [r7, #20] 801355e: f000 fd35 bl 8013fcc 8013562: 4603 mov r3, r0 8013564: 2b01 cmp r3, #1 8013566: d016 beq.n 8013596 vSemaphoreDelete (hSemaphore); 8013568: 6978 ldr r0, [r7, #20] 801356a: f001 fa0b bl 8014984 hSemaphore = NULL; 801356e: 2300 movs r3, #0 8013570: 617b str r3, [r7, #20] 8013572: e010 b.n 8013596 } } } else { if (mem == 1) { 8013574: 693b ldr r3, [r7, #16] 8013576: 2b01 cmp r3, #1 8013578: d108 bne.n 801358c #if (configSUPPORT_STATIC_ALLOCATION == 1) hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem); 801357a: 687b ldr r3, [r7, #4] 801357c: 689b ldr r3, [r3, #8] 801357e: 461a mov r2, r3 8013580: 68b9 ldr r1, [r7, #8] 8013582: 68f8 ldr r0, [r7, #12] 8013584: f000 fcc0 bl 8013f08 8013588: 6178 str r0, [r7, #20] 801358a: e004 b.n 8013596 #endif } else { #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hSemaphore = xSemaphoreCreateCounting (max_count, initial_count); 801358c: 68b9 ldr r1, [r7, #8] 801358e: 68f8 ldr r0, [r7, #12] 8013590: f000 fced bl 8013f6e 8013594: 6178 str r0, [r7, #20] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hSemaphore != NULL) { 8013596: 697b ldr r3, [r7, #20] 8013598: 2b00 cmp r3, #0 801359a: d00c beq.n 80135b6 if ((attr != NULL) && (attr->name != NULL)) { 801359c: 687b ldr r3, [r7, #4] 801359e: 2b00 cmp r3, #0 80135a0: d009 beq.n 80135b6 80135a2: 687b ldr r3, [r7, #4] 80135a4: 681b ldr r3, [r3, #0] 80135a6: 2b00 cmp r3, #0 80135a8: d005 beq.n 80135b6 /* Only non-NULL name objects are added to the Queue Registry */ vQueueAddToRegistry (hSemaphore, attr->name); 80135aa: 687b ldr r3, [r7, #4] 80135ac: 681b ldr r3, [r3, #0] 80135ae: 4619 mov r1, r3 80135b0: 6978 ldr r0, [r7, #20] 80135b2: f001 fb33 bl 8014c1c #endif } } /* Return semaphore ID */ return ((osSemaphoreId_t)hSemaphore); 80135b6: 697b ldr r3, [r7, #20] } 80135b8: 4618 mov r0, r3 80135ba: 3718 adds r7, #24 80135bc: 46bd mov sp, r7 80135be: bd80 pop {r7, pc} 080135c0 : /* Acquire a Semaphore token or timeout if no tokens are available. */ osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { 80135c0: b580 push {r7, lr} 80135c2: b086 sub sp, #24 80135c4: af00 add r7, sp, #0 80135c6: 6078 str r0, [r7, #4] 80135c8: 6039 str r1, [r7, #0] SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; 80135ca: 687b ldr r3, [r7, #4] 80135cc: 613b str r3, [r7, #16] osStatus_t stat; BaseType_t yield; stat = osOK; 80135ce: 2300 movs r3, #0 80135d0: 617b str r3, [r7, #20] if (hSemaphore == NULL) { 80135d2: 693b ldr r3, [r7, #16] 80135d4: 2b00 cmp r3, #0 80135d6: d103 bne.n 80135e0 stat = osErrorParameter; 80135d8: f06f 0303 mvn.w r3, #3 80135dc: 617b str r3, [r7, #20] 80135de: e038 b.n 8013652 } else if (IRQ_Context() != 0U) { 80135e0: f7ff fc53 bl 8012e8a 80135e4: 4603 mov r3, r0 80135e6: 2b00 cmp r3, #0 80135e8: d022 beq.n 8013630 if (timeout != 0U) { 80135ea: 683b ldr r3, [r7, #0] 80135ec: 2b00 cmp r3, #0 80135ee: d003 beq.n 80135f8 stat = osErrorParameter; 80135f0: f06f 0303 mvn.w r3, #3 80135f4: 617b str r3, [r7, #20] 80135f6: e02c b.n 8013652 } else { yield = pdFALSE; 80135f8: 2300 movs r3, #0 80135fa: 60fb str r3, [r7, #12] if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) { 80135fc: f107 030c add.w r3, r7, #12 8013600: 461a mov r2, r3 8013602: 2100 movs r1, #0 8013604: 6938 ldr r0, [r7, #16] 8013606: f001 f923 bl 8014850 801360a: 4603 mov r3, r0 801360c: 2b01 cmp r3, #1 801360e: d003 beq.n 8013618 stat = osErrorResource; 8013610: f06f 0302 mvn.w r3, #2 8013614: 617b str r3, [r7, #20] 8013616: e01c b.n 8013652 } else { portYIELD_FROM_ISR (yield); 8013618: 68fb ldr r3, [r7, #12] 801361a: 2b00 cmp r3, #0 801361c: d019 beq.n 8013652 801361e: 4b0f ldr r3, [pc, #60] @ (801365c ) 8013620: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013624: 601a str r2, [r3, #0] 8013626: f3bf 8f4f dsb sy 801362a: f3bf 8f6f isb sy 801362e: e010 b.n 8013652 } } } else { if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) { 8013630: 6839 ldr r1, [r7, #0] 8013632: 6938 ldr r0, [r7, #16] 8013634: f001 f80c bl 8014650 8013638: 4603 mov r3, r0 801363a: 2b01 cmp r3, #1 801363c: d009 beq.n 8013652 if (timeout != 0U) { 801363e: 683b ldr r3, [r7, #0] 8013640: 2b00 cmp r3, #0 8013642: d003 beq.n 801364c stat = osErrorTimeout; 8013644: f06f 0301 mvn.w r3, #1 8013648: 617b str r3, [r7, #20] 801364a: e002 b.n 8013652 } else { stat = osErrorResource; 801364c: f06f 0302 mvn.w r3, #2 8013650: 617b str r3, [r7, #20] } } } /* Return execution status */ return (stat); 8013652: 697b ldr r3, [r7, #20] } 8013654: 4618 mov r0, r3 8013656: 3718 adds r7, #24 8013658: 46bd mov sp, r7 801365a: bd80 pop {r7, pc} 801365c: e000ed04 .word 0xe000ed04 08013660 : /* Release a Semaphore token up to the initial maximum count. */ osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { 8013660: b580 push {r7, lr} 8013662: b086 sub sp, #24 8013664: af00 add r7, sp, #0 8013666: 6078 str r0, [r7, #4] SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; 8013668: 687b ldr r3, [r7, #4] 801366a: 613b str r3, [r7, #16] osStatus_t stat; BaseType_t yield; stat = osOK; 801366c: 2300 movs r3, #0 801366e: 617b str r3, [r7, #20] if (hSemaphore == NULL) { 8013670: 693b ldr r3, [r7, #16] 8013672: 2b00 cmp r3, #0 8013674: d103 bne.n 801367e stat = osErrorParameter; 8013676: f06f 0303 mvn.w r3, #3 801367a: 617b str r3, [r7, #20] 801367c: e02b b.n 80136d6 } else if (IRQ_Context() != 0U) { 801367e: f7ff fc04 bl 8012e8a 8013682: 4603 mov r3, r0 8013684: 2b00 cmp r3, #0 8013686: d01a beq.n 80136be yield = pdFALSE; 8013688: 2300 movs r3, #0 801368a: 60fb str r3, [r7, #12] if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) { 801368c: f107 030c add.w r3, r7, #12 8013690: 4619 mov r1, r3 8013692: 6938 ldr r0, [r7, #16] 8013694: f000 fe52 bl 801433c 8013698: 4603 mov r3, r0 801369a: 2b01 cmp r3, #1 801369c: d003 beq.n 80136a6 stat = osErrorResource; 801369e: f06f 0302 mvn.w r3, #2 80136a2: 617b str r3, [r7, #20] 80136a4: e017 b.n 80136d6 } else { portYIELD_FROM_ISR (yield); 80136a6: 68fb ldr r3, [r7, #12] 80136a8: 2b00 cmp r3, #0 80136aa: d014 beq.n 80136d6 80136ac: 4b0c ldr r3, [pc, #48] @ (80136e0 ) 80136ae: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80136b2: 601a str r2, [r3, #0] 80136b4: f3bf 8f4f dsb sy 80136b8: f3bf 8f6f isb sy 80136bc: e00b b.n 80136d6 } } else { if (xSemaphoreGive (hSemaphore) != pdPASS) { 80136be: 2300 movs r3, #0 80136c0: 2200 movs r2, #0 80136c2: 2100 movs r1, #0 80136c4: 6938 ldr r0, [r7, #16] 80136c6: f000 fc81 bl 8013fcc 80136ca: 4603 mov r3, r0 80136cc: 2b01 cmp r3, #1 80136ce: d002 beq.n 80136d6 stat = osErrorResource; 80136d0: f06f 0302 mvn.w r3, #2 80136d4: 617b str r3, [r7, #20] } } /* Return execution status */ return (stat); 80136d6: 697b ldr r3, [r7, #20] } 80136d8: 4618 mov r0, r3 80136da: 3718 adds r7, #24 80136dc: 46bd mov sp, r7 80136de: bd80 pop {r7, pc} 80136e0: e000ed04 .word 0xe000ed04 080136e4 : Limitations: - The memory for control block and and message data must be provided in the osThreadAttr_t structure in order to allocate object statically. */ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 80136e4: b580 push {r7, lr} 80136e6: b088 sub sp, #32 80136e8: af02 add r7, sp, #8 80136ea: 60f8 str r0, [r7, #12] 80136ec: 60b9 str r1, [r7, #8] 80136ee: 607a str r2, [r7, #4] QueueHandle_t hQueue; int32_t mem; hQueue = NULL; 80136f0: 2300 movs r3, #0 80136f2: 617b str r3, [r7, #20] if ((IRQ_Context() == 0U) && (msg_count > 0U) && (msg_size > 0U)) { 80136f4: f7ff fbc9 bl 8012e8a 80136f8: 4603 mov r3, r0 80136fa: 2b00 cmp r3, #0 80136fc: d15f bne.n 80137be 80136fe: 68fb ldr r3, [r7, #12] 8013700: 2b00 cmp r3, #0 8013702: d05c beq.n 80137be 8013704: 68bb ldr r3, [r7, #8] 8013706: 2b00 cmp r3, #0 8013708: d059 beq.n 80137be mem = -1; 801370a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801370e: 613b str r3, [r7, #16] if (attr != NULL) { 8013710: 687b ldr r3, [r7, #4] 8013712: 2b00 cmp r3, #0 8013714: d029 beq.n 801376a if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8013716: 687b ldr r3, [r7, #4] 8013718: 689b ldr r3, [r3, #8] 801371a: 2b00 cmp r3, #0 801371c: d012 beq.n 8013744 801371e: 687b ldr r3, [r7, #4] 8013720: 68db ldr r3, [r3, #12] 8013722: 2b4f cmp r3, #79 @ 0x4f 8013724: d90e bls.n 8013744 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8013726: 687b ldr r3, [r7, #4] 8013728: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 801372a: 2b00 cmp r3, #0 801372c: d00a beq.n 8013744 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 801372e: 687b ldr r3, [r7, #4] 8013730: 695a ldr r2, [r3, #20] 8013732: 68fb ldr r3, [r7, #12] 8013734: 68b9 ldr r1, [r7, #8] 8013736: fb01 f303 mul.w r3, r1, r3 801373a: 429a cmp r2, r3 801373c: d302 bcc.n 8013744 /* The memory for control block and message data is provided, use static object */ mem = 1; 801373e: 2301 movs r3, #1 8013740: 613b str r3, [r7, #16] 8013742: e014 b.n 801376e } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8013744: 687b ldr r3, [r7, #4] 8013746: 689b ldr r3, [r3, #8] 8013748: 2b00 cmp r3, #0 801374a: d110 bne.n 801376e 801374c: 687b ldr r3, [r7, #4] 801374e: 68db ldr r3, [r3, #12] 8013750: 2b00 cmp r3, #0 8013752: d10c bne.n 801376e (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8013754: 687b ldr r3, [r7, #4] 8013756: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8013758: 2b00 cmp r3, #0 801375a: d108 bne.n 801376e (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 801375c: 687b ldr r3, [r7, #4] 801375e: 695b ldr r3, [r3, #20] 8013760: 2b00 cmp r3, #0 8013762: d104 bne.n 801376e /* Control block will be allocated from the dynamic pool */ mem = 0; 8013764: 2300 movs r3, #0 8013766: 613b str r3, [r7, #16] 8013768: e001 b.n 801376e } } } else { mem = 0; 801376a: 2300 movs r3, #0 801376c: 613b str r3, [r7, #16] } if (mem == 1) { 801376e: 693b ldr r3, [r7, #16] 8013770: 2b01 cmp r3, #1 8013772: d10b bne.n 801378c #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8013774: 687b ldr r3, [r7, #4] 8013776: 691a ldr r2, [r3, #16] 8013778: 687b ldr r3, [r7, #4] 801377a: 689b ldr r3, [r3, #8] 801377c: 2100 movs r1, #0 801377e: 9100 str r1, [sp, #0] 8013780: 68b9 ldr r1, [r7, #8] 8013782: 68f8 ldr r0, [r7, #12] 8013784: f000 fa30 bl 8013be8 8013788: 6178 str r0, [r7, #20] 801378a: e008 b.n 801379e #endif } else { if (mem == 0) { 801378c: 693b ldr r3, [r7, #16] 801378e: 2b00 cmp r3, #0 8013790: d105 bne.n 801379e #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 8013792: 2200 movs r2, #0 8013794: 68b9 ldr r1, [r7, #8] 8013796: 68f8 ldr r0, [r7, #12] 8013798: f000 fa87 bl 8013caa 801379c: 6178 str r0, [r7, #20] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 801379e: 697b ldr r3, [r7, #20] 80137a0: 2b00 cmp r3, #0 80137a2: d00c beq.n 80137be if ((attr != NULL) && (attr->name != NULL)) { 80137a4: 687b ldr r3, [r7, #4] 80137a6: 2b00 cmp r3, #0 80137a8: d009 beq.n 80137be 80137aa: 687b ldr r3, [r7, #4] 80137ac: 681b ldr r3, [r3, #0] 80137ae: 2b00 cmp r3, #0 80137b0: d005 beq.n 80137be /* Only non-NULL name objects are added to the Queue Registry */ vQueueAddToRegistry (hQueue, attr->name); 80137b2: 687b ldr r3, [r7, #4] 80137b4: 681b ldr r3, [r3, #0] 80137b6: 4619 mov r1, r3 80137b8: 6978 ldr r0, [r7, #20] 80137ba: f001 fa2f bl 8014c1c #endif } /* Return message queue ID */ return ((osMessageQueueId_t)hQueue); 80137be: 697b ldr r3, [r7, #20] } 80137c0: 4618 mov r0, r3 80137c2: 3718 adds r7, #24 80137c4: 46bd mov sp, r7 80137c6: bd80 pop {r7, pc} 080137c8 : Put a Message into a Queue or timeout if Queue is full. Limitations: - Message priority is ignored */ osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 80137c8: b580 push {r7, lr} 80137ca: b088 sub sp, #32 80137cc: af00 add r7, sp, #0 80137ce: 60f8 str r0, [r7, #12] 80137d0: 60b9 str r1, [r7, #8] 80137d2: 603b str r3, [r7, #0] 80137d4: 4613 mov r3, r2 80137d6: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 80137d8: 68fb ldr r3, [r7, #12] 80137da: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 80137dc: 2300 movs r3, #0 80137de: 61fb str r3, [r7, #28] if (IRQ_Context() != 0U) { 80137e0: f7ff fb53 bl 8012e8a 80137e4: 4603 mov r3, r0 80137e6: 2b00 cmp r3, #0 80137e8: d028 beq.n 801383c if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 80137ea: 69bb ldr r3, [r7, #24] 80137ec: 2b00 cmp r3, #0 80137ee: d005 beq.n 80137fc 80137f0: 68bb ldr r3, [r7, #8] 80137f2: 2b00 cmp r3, #0 80137f4: d002 beq.n 80137fc 80137f6: 683b ldr r3, [r7, #0] 80137f8: 2b00 cmp r3, #0 80137fa: d003 beq.n 8013804 stat = osErrorParameter; 80137fc: f06f 0303 mvn.w r3, #3 8013800: 61fb str r3, [r7, #28] 8013802: e038 b.n 8013876 } else { yield = pdFALSE; 8013804: 2300 movs r3, #0 8013806: 617b str r3, [r7, #20] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 8013808: f107 0214 add.w r2, r7, #20 801380c: 2300 movs r3, #0 801380e: 68b9 ldr r1, [r7, #8] 8013810: 69b8 ldr r0, [r7, #24] 8013812: f000 fcdd bl 80141d0 8013816: 4603 mov r3, r0 8013818: 2b01 cmp r3, #1 801381a: d003 beq.n 8013824 stat = osErrorResource; 801381c: f06f 0302 mvn.w r3, #2 8013820: 61fb str r3, [r7, #28] 8013822: e028 b.n 8013876 } else { portYIELD_FROM_ISR (yield); 8013824: 697b ldr r3, [r7, #20] 8013826: 2b00 cmp r3, #0 8013828: d025 beq.n 8013876 801382a: 4b15 ldr r3, [pc, #84] @ (8013880 ) 801382c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013830: 601a str r2, [r3, #0] 8013832: f3bf 8f4f dsb sy 8013836: f3bf 8f6f isb sy 801383a: e01c b.n 8013876 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 801383c: 69bb ldr r3, [r7, #24] 801383e: 2b00 cmp r3, #0 8013840: d002 beq.n 8013848 8013842: 68bb ldr r3, [r7, #8] 8013844: 2b00 cmp r3, #0 8013846: d103 bne.n 8013850 stat = osErrorParameter; 8013848: f06f 0303 mvn.w r3, #3 801384c: 61fb str r3, [r7, #28] 801384e: e012 b.n 8013876 } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8013850: 2300 movs r3, #0 8013852: 683a ldr r2, [r7, #0] 8013854: 68b9 ldr r1, [r7, #8] 8013856: 69b8 ldr r0, [r7, #24] 8013858: f000 fbb8 bl 8013fcc 801385c: 4603 mov r3, r0 801385e: 2b01 cmp r3, #1 8013860: d009 beq.n 8013876 if (timeout != 0U) { 8013862: 683b ldr r3, [r7, #0] 8013864: 2b00 cmp r3, #0 8013866: d003 beq.n 8013870 stat = osErrorTimeout; 8013868: f06f 0301 mvn.w r3, #1 801386c: 61fb str r3, [r7, #28] 801386e: e002 b.n 8013876 } else { stat = osErrorResource; 8013870: f06f 0302 mvn.w r3, #2 8013874: 61fb str r3, [r7, #28] } } } /* Return execution status */ return (stat); 8013876: 69fb ldr r3, [r7, #28] } 8013878: 4618 mov r0, r3 801387a: 3720 adds r7, #32 801387c: 46bd mov sp, r7 801387e: bd80 pop {r7, pc} 8013880: e000ed04 .word 0xe000ed04 08013884 : Get a Message from a Queue or timeout if Queue is empty. Limitations: - Message priority is ignored */ osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 8013884: b580 push {r7, lr} 8013886: b088 sub sp, #32 8013888: af00 add r7, sp, #0 801388a: 60f8 str r0, [r7, #12] 801388c: 60b9 str r1, [r7, #8] 801388e: 607a str r2, [r7, #4] 8013890: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8013892: 68fb ldr r3, [r7, #12] 8013894: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8013896: 2300 movs r3, #0 8013898: 61fb str r3, [r7, #28] if (IRQ_Context() != 0U) { 801389a: f7ff faf6 bl 8012e8a 801389e: 4603 mov r3, r0 80138a0: 2b00 cmp r3, #0 80138a2: d028 beq.n 80138f6 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 80138a4: 69bb ldr r3, [r7, #24] 80138a6: 2b00 cmp r3, #0 80138a8: d005 beq.n 80138b6 80138aa: 68bb ldr r3, [r7, #8] 80138ac: 2b00 cmp r3, #0 80138ae: d002 beq.n 80138b6 80138b0: 683b ldr r3, [r7, #0] 80138b2: 2b00 cmp r3, #0 80138b4: d003 beq.n 80138be stat = osErrorParameter; 80138b6: f06f 0303 mvn.w r3, #3 80138ba: 61fb str r3, [r7, #28] 80138bc: e037 b.n 801392e } else { yield = pdFALSE; 80138be: 2300 movs r3, #0 80138c0: 617b str r3, [r7, #20] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 80138c2: f107 0314 add.w r3, r7, #20 80138c6: 461a mov r2, r3 80138c8: 68b9 ldr r1, [r7, #8] 80138ca: 69b8 ldr r0, [r7, #24] 80138cc: f000 ffc0 bl 8014850 80138d0: 4603 mov r3, r0 80138d2: 2b01 cmp r3, #1 80138d4: d003 beq.n 80138de stat = osErrorResource; 80138d6: f06f 0302 mvn.w r3, #2 80138da: 61fb str r3, [r7, #28] 80138dc: e027 b.n 801392e } else { portYIELD_FROM_ISR (yield); 80138de: 697b ldr r3, [r7, #20] 80138e0: 2b00 cmp r3, #0 80138e2: d024 beq.n 801392e 80138e4: 4b14 ldr r3, [pc, #80] @ (8013938 ) 80138e6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80138ea: 601a str r2, [r3, #0] 80138ec: f3bf 8f4f dsb sy 80138f0: f3bf 8f6f isb sy 80138f4: e01b b.n 801392e } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 80138f6: 69bb ldr r3, [r7, #24] 80138f8: 2b00 cmp r3, #0 80138fa: d002 beq.n 8013902 80138fc: 68bb ldr r3, [r7, #8] 80138fe: 2b00 cmp r3, #0 8013900: d103 bne.n 801390a stat = osErrorParameter; 8013902: f06f 0303 mvn.w r3, #3 8013906: 61fb str r3, [r7, #28] 8013908: e011 b.n 801392e } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 801390a: 683a ldr r2, [r7, #0] 801390c: 68b9 ldr r1, [r7, #8] 801390e: 69b8 ldr r0, [r7, #24] 8013910: f000 fdbc bl 801448c 8013914: 4603 mov r3, r0 8013916: 2b01 cmp r3, #1 8013918: d009 beq.n 801392e if (timeout != 0U) { 801391a: 683b ldr r3, [r7, #0] 801391c: 2b00 cmp r3, #0 801391e: d003 beq.n 8013928 stat = osErrorTimeout; 8013920: f06f 0301 mvn.w r3, #1 8013924: 61fb str r3, [r7, #28] 8013926: e002 b.n 801392e } else { stat = osErrorResource; 8013928: f06f 0302 mvn.w r3, #2 801392c: 61fb str r3, [r7, #28] } } } /* Return execution status */ return (stat); 801392e: 69fb ldr r3, [r7, #28] } 8013930: 4618 mov r0, r3 8013932: 3720 adds r7, #32 8013934: 46bd mov sp, r7 8013936: bd80 pop {r7, pc} 8013938: e000ed04 .word 0xe000ed04 0801393c : #if (configSUPPORT_STATIC_ALLOCATION == 1) /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 801393c: b480 push {r7} 801393e: b085 sub sp, #20 8013940: af00 add r7, sp, #0 8013942: 60f8 str r0, [r7, #12] 8013944: 60b9 str r1, [r7, #8] 8013946: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 8013948: 68fb ldr r3, [r7, #12] 801394a: 4a07 ldr r2, [pc, #28] @ (8013968 ) 801394c: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 801394e: 68bb ldr r3, [r7, #8] 8013950: 4a06 ldr r2, [pc, #24] @ (801396c ) 8013952: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8013954: 687b ldr r3, [r7, #4] 8013956: f44f 7200 mov.w r2, #512 @ 0x200 801395a: 601a str r2, [r3, #0] } 801395c: bf00 nop 801395e: 3714 adds r7, #20 8013960: 46bd mov sp, r7 8013962: f85d 7b04 ldr.w r7, [sp], #4 8013966: 4770 bx lr 8013968: 200007d0 .word 0x200007d0 801396c: 2000082c .word 0x2000082c 08013970 : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 8013970: b480 push {r7} 8013972: b085 sub sp, #20 8013974: af00 add r7, sp, #0 8013976: 60f8 str r0, [r7, #12] 8013978: 60b9 str r1, [r7, #8] 801397a: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 801397c: 68fb ldr r3, [r7, #12] 801397e: 4a07 ldr r2, [pc, #28] @ (801399c ) 8013980: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 8013982: 68bb ldr r3, [r7, #8] 8013984: 4a06 ldr r2, [pc, #24] @ (80139a0 ) 8013986: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8013988: 687b ldr r3, [r7, #4] 801398a: f44f 6280 mov.w r2, #1024 @ 0x400 801398e: 601a str r2, [r3, #0] } 8013990: bf00 nop 8013992: 3714 adds r7, #20 8013994: 46bd mov sp, r7 8013996: f85d 7b04 ldr.w r7, [sp], #4 801399a: 4770 bx lr 801399c: 2000102c .word 0x2000102c 80139a0: 20001088 .word 0x20001088 080139a4 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 80139a4: b480 push {r7} 80139a6: b083 sub sp, #12 80139a8: af00 add r7, sp, #0 80139aa: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the * end of the list. To initialise the list the list end is inserted * as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80139ac: 687b ldr r3, [r7, #4] 80139ae: f103 0208 add.w r2, r3, #8 80139b2: 687b ldr r3, [r7, #4] 80139b4: 605a str r2, [r3, #4] listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); /* The list end value is the highest possible value in the list to * ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 80139b6: 687b ldr r3, [r7, #4] 80139b8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80139bc: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know * when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80139be: 687b ldr r3, [r7, #4] 80139c0: f103 0208 add.w r2, r3, #8 80139c4: 687b ldr r3, [r7, #4] 80139c6: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80139c8: 687b ldr r3, [r7, #4] 80139ca: f103 0208 add.w r2, r3, #8 80139ce: 687b ldr r3, [r7, #4] 80139d0: 611a str r2, [r3, #16] pxList->xListEnd.pxContainer = NULL; listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); } #endif pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 80139d2: 687b ldr r3, [r7, #4] 80139d4: 2200 movs r2, #0 80139d6: 601a str r2, [r3, #0] /* Write known values into the list if * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 80139d8: bf00 nop 80139da: 370c adds r7, #12 80139dc: 46bd mov sp, r7 80139de: f85d 7b04 ldr.w r7, [sp], #4 80139e2: 4770 bx lr 080139e4 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 80139e4: b480 push {r7} 80139e6: b083 sub sp, #12 80139e8: af00 add r7, sp, #0 80139ea: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 80139ec: 687b ldr r3, [r7, #4] 80139ee: 2200 movs r2, #0 80139f0: 611a str r2, [r3, #16] /* Write known values into the list item if * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 80139f2: bf00 nop 80139f4: 370c adds r7, #12 80139f6: 46bd mov sp, r7 80139f8: f85d 7b04 ldr.w r7, [sp], #4 80139fc: 4770 bx lr 080139fe : } /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 80139fe: b480 push {r7} 8013a00: b085 sub sp, #20 8013a02: af00 add r7, sp, #0 8013a04: 6078 str r0, [r7, #4] 8013a06: 6039 str r1, [r7, #0] ListItem_t * pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8013a08: 683b ldr r3, [r7, #0] 8013a0a: 681b ldr r3, [r3, #0] 8013a0c: 60bb str r3, [r7, #8] * new list item should be placed after it. This ensures that TCBs which are * stored in ready lists (all of which have the same xItemValue value) get a * share of the CPU. However, if the xItemValue is the same as the back marker * the iteration loop below will not end. Therefore the value is checked * first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8013a0e: 68bb ldr r3, [r7, #8] 8013a10: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013a14: d103 bne.n 8013a1e { pxIterator = pxList->xListEnd.pxPrevious; 8013a16: 687b ldr r3, [r7, #4] 8013a18: 691b ldr r3, [r3, #16] 8013a1a: 60fb str r3, [r7, #12] 8013a1c: e00c b.n 8013a38 * 5) If the FreeRTOS port supports interrupt nesting then ensure that * the priority of the tick interrupt is at or below * configMAX_SYSCALL_INTERRUPT_PRIORITY. **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8013a1e: 687b ldr r3, [r7, #4] 8013a20: 3308 adds r3, #8 8013a22: 60fb str r3, [r7, #12] 8013a24: e002 b.n 8013a2c 8013a26: 68fb ldr r3, [r7, #12] 8013a28: 685b ldr r3, [r3, #4] 8013a2a: 60fb str r3, [r7, #12] 8013a2c: 68fb ldr r3, [r7, #12] 8013a2e: 685b ldr r3, [r3, #4] 8013a30: 681b ldr r3, [r3, #0] 8013a32: 68ba ldr r2, [r7, #8] 8013a34: 429a cmp r2, r3 8013a36: d2f6 bcs.n 8013a26 /* There is nothing to do here, just iterating to the wanted * insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8013a38: 68fb ldr r3, [r7, #12] 8013a3a: 685a ldr r2, [r3, #4] 8013a3c: 683b ldr r3, [r7, #0] 8013a3e: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8013a40: 683b ldr r3, [r7, #0] 8013a42: 685b ldr r3, [r3, #4] 8013a44: 683a ldr r2, [r7, #0] 8013a46: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8013a48: 683b ldr r3, [r7, #0] 8013a4a: 68fa ldr r2, [r7, #12] 8013a4c: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8013a4e: 68fb ldr r3, [r7, #12] 8013a50: 683a ldr r2, [r7, #0] 8013a52: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the * item later. */ pxNewListItem->pxContainer = pxList; 8013a54: 683b ldr r3, [r7, #0] 8013a56: 687a ldr r2, [r7, #4] 8013a58: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8013a5a: 687b ldr r3, [r7, #4] 8013a5c: 681b ldr r3, [r3, #0] 8013a5e: 1c5a adds r2, r3, #1 8013a60: 687b ldr r3, [r7, #4] 8013a62: 601a str r2, [r3, #0] } 8013a64: bf00 nop 8013a66: 3714 adds r7, #20 8013a68: 46bd mov sp, r7 8013a6a: f85d 7b04 ldr.w r7, [sp], #4 8013a6e: 4770 bx lr 08013a70 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8013a70: b480 push {r7} 8013a72: b085 sub sp, #20 8013a74: af00 add r7, sp, #0 8013a76: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list * item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8013a78: 687b ldr r3, [r7, #4] 8013a7a: 691b ldr r3, [r3, #16] 8013a7c: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8013a7e: 687b ldr r3, [r7, #4] 8013a80: 685b ldr r3, [r3, #4] 8013a82: 687a ldr r2, [r7, #4] 8013a84: 6892 ldr r2, [r2, #8] 8013a86: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8013a88: 687b ldr r3, [r7, #4] 8013a8a: 689b ldr r3, [r3, #8] 8013a8c: 687a ldr r2, [r7, #4] 8013a8e: 6852 ldr r2, [r2, #4] 8013a90: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 8013a92: 68fb ldr r3, [r7, #12] 8013a94: 685b ldr r3, [r3, #4] 8013a96: 687a ldr r2, [r7, #4] 8013a98: 429a cmp r2, r3 8013a9a: d103 bne.n 8013aa4 { pxList->pxIndex = pxItemToRemove->pxPrevious; 8013a9c: 687b ldr r3, [r7, #4] 8013a9e: 689a ldr r2, [r3, #8] 8013aa0: 68fb ldr r3, [r7, #12] 8013aa2: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8013aa4: 687b ldr r3, [r7, #4] 8013aa6: 2200 movs r2, #0 8013aa8: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8013aaa: 68fb ldr r3, [r7, #12] 8013aac: 681b ldr r3, [r3, #0] 8013aae: 1e5a subs r2, r3, #1 8013ab0: 68fb ldr r3, [r7, #12] 8013ab2: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8013ab4: 68fb ldr r3, [r7, #12] 8013ab6: 681b ldr r3, [r3, #0] } 8013ab8: 4618 mov r0, r3 8013aba: 3714 adds r7, #20 8013abc: 46bd mov sp, r7 8013abe: f85d 7b04 ldr.w r7, [sp], #4 8013ac2: 4770 bx lr 08013ac4 : } while( 0 ) /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 8013ac4: b580 push {r7, lr} 8013ac6: b086 sub sp, #24 8013ac8: af00 add r7, sp, #0 8013aca: 6078 str r0, [r7, #4] 8013acc: 6039 str r1, [r7, #0] BaseType_t xReturn = pdPASS; 8013ace: 2301 movs r3, #1 8013ad0: 617b str r3, [r7, #20] Queue_t * const pxQueue = xQueue; 8013ad2: 687b ldr r3, [r7, #4] 8013ad4: 613b str r3, [r7, #16] configASSERT( pxQueue ); 8013ad6: 693b ldr r3, [r7, #16] 8013ad8: 2b00 cmp r3, #0 8013ada: d10b bne.n 8013af4 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8013adc: f04f 0350 mov.w r3, #80 @ 0x50 8013ae0: f383 8811 msr BASEPRI, r3 8013ae4: f3bf 8f6f isb sy 8013ae8: f3bf 8f4f dsb sy 8013aec: 60fb str r3, [r7, #12] " msr basepri, %0 \n"\ " isb \n"\ " dsb \n"\ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8013aee: bf00 nop 8013af0: bf00 nop 8013af2: e7fd b.n 8013af0 if( ( pxQueue != NULL ) && 8013af4: 693b ldr r3, [r7, #16] 8013af6: 2b00 cmp r3, #0 8013af8: d05d beq.n 8013bb6 ( pxQueue->uxLength >= 1U ) && 8013afa: 693b ldr r3, [r7, #16] 8013afc: 6bdb ldr r3, [r3, #60] @ 0x3c if( ( pxQueue != NULL ) && 8013afe: 2b00 cmp r3, #0 8013b00: d059 beq.n 8013bb6 /* Check for multiplication overflow. */ ( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) ) 8013b02: 693b ldr r3, [r7, #16] 8013b04: 6c1a ldr r2, [r3, #64] @ 0x40 8013b06: 693b ldr r3, [r7, #16] 8013b08: 6bdb ldr r3, [r3, #60] @ 0x3c 8013b0a: 2100 movs r1, #0 8013b0c: fba3 2302 umull r2, r3, r3, r2 8013b10: 2b00 cmp r3, #0 8013b12: d000 beq.n 8013b16 8013b14: 2101 movs r1, #1 8013b16: 460b mov r3, r1 ( pxQueue->uxLength >= 1U ) && 8013b18: 2b00 cmp r3, #0 8013b1a: d14c bne.n 8013bb6 { taskENTER_CRITICAL(); 8013b1c: f003 fc20 bl 8017360 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8013b20: 693b ldr r3, [r7, #16] 8013b22: 681a ldr r2, [r3, #0] 8013b24: 693b ldr r3, [r7, #16] 8013b26: 6bdb ldr r3, [r3, #60] @ 0x3c 8013b28: 6939 ldr r1, [r7, #16] 8013b2a: 6c09 ldr r1, [r1, #64] @ 0x40 8013b2c: fb01 f303 mul.w r3, r1, r3 8013b30: 441a add r2, r3 8013b32: 693b ldr r3, [r7, #16] 8013b34: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8013b36: 693b ldr r3, [r7, #16] 8013b38: 2200 movs r2, #0 8013b3a: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8013b3c: 693b ldr r3, [r7, #16] 8013b3e: 681a ldr r2, [r3, #0] 8013b40: 693b ldr r3, [r7, #16] 8013b42: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8013b44: 693b ldr r3, [r7, #16] 8013b46: 681a ldr r2, [r3, #0] 8013b48: 693b ldr r3, [r7, #16] 8013b4a: 6bdb ldr r3, [r3, #60] @ 0x3c 8013b4c: 3b01 subs r3, #1 8013b4e: 6939 ldr r1, [r7, #16] 8013b50: 6c09 ldr r1, [r1, #64] @ 0x40 8013b52: fb01 f303 mul.w r3, r1, r3 8013b56: 441a add r2, r3 8013b58: 693b ldr r3, [r7, #16] 8013b5a: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8013b5c: 693b ldr r3, [r7, #16] 8013b5e: 22ff movs r2, #255 @ 0xff 8013b60: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8013b64: 693b ldr r3, [r7, #16] 8013b66: 22ff movs r2, #255 @ 0xff 8013b68: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8013b6c: 683b ldr r3, [r7, #0] 8013b6e: 2b00 cmp r3, #0 8013b70: d114 bne.n 8013b9c /* If there are tasks blocked waiting to read from the queue, then * the tasks will remain blocked as after this function exits the queue * will still be empty. If there are tasks blocked waiting to write to * the queue, then one should be unblocked as after this function exits * it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8013b72: 693b ldr r3, [r7, #16] 8013b74: 691b ldr r3, [r3, #16] 8013b76: 2b00 cmp r3, #0 8013b78: d01a beq.n 8013bb0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8013b7a: 693b ldr r3, [r7, #16] 8013b7c: 3310 adds r3, #16 8013b7e: 4618 mov r0, r3 8013b80: f001 fe8e bl 80158a0 8013b84: 4603 mov r3, r0 8013b86: 2b00 cmp r3, #0 8013b88: d012 beq.n 8013bb0 { queueYIELD_IF_USING_PREEMPTION(); 8013b8a: 4b16 ldr r3, [pc, #88] @ (8013be4 ) 8013b8c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013b90: 601a str r2, [r3, #0] 8013b92: f3bf 8f4f dsb sy 8013b96: f3bf 8f6f isb sy 8013b9a: e009 b.n 8013bb0 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8013b9c: 693b ldr r3, [r7, #16] 8013b9e: 3310 adds r3, #16 8013ba0: 4618 mov r0, r3 8013ba2: f7ff feff bl 80139a4 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8013ba6: 693b ldr r3, [r7, #16] 8013ba8: 3324 adds r3, #36 @ 0x24 8013baa: 4618 mov r0, r3 8013bac: f7ff fefa bl 80139a4 } } taskEXIT_CRITICAL(); 8013bb0: f003 fc08 bl 80173c4 8013bb4: e001 b.n 8013bba } else { xReturn = pdFAIL; 8013bb6: 2300 movs r3, #0 8013bb8: 617b str r3, [r7, #20] } configASSERT( xReturn != pdFAIL ); 8013bba: 697b ldr r3, [r7, #20] 8013bbc: 2b00 cmp r3, #0 8013bbe: d10b bne.n 8013bd8 __asm volatile 8013bc0: f04f 0350 mov.w r3, #80 @ 0x50 8013bc4: f383 8811 msr BASEPRI, r3 8013bc8: f3bf 8f6f isb sy 8013bcc: f3bf 8f4f dsb sy 8013bd0: 60bb str r3, [r7, #8] } 8013bd2: bf00 nop 8013bd4: bf00 nop 8013bd6: e7fd b.n 8013bd4 /* A value is returned for calling semantic consistency with previous * versions. */ return xReturn; 8013bd8: 697b ldr r3, [r7, #20] } 8013bda: 4618 mov r0, r3 8013bdc: 3718 adds r7, #24 8013bde: 46bd mov sp, r7 8013be0: bd80 pop {r7, pc} 8013be2: bf00 nop 8013be4: e000ed04 .word 0xe000ed04 08013be8 : QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t * pucQueueStorage, StaticQueue_t * pxStaticQueue, const uint8_t ucQueueType ) { 8013be8: b580 push {r7, lr} 8013bea: b08c sub sp, #48 @ 0x30 8013bec: af02 add r7, sp, #8 8013bee: 60f8 str r0, [r7, #12] 8013bf0: 60b9 str r1, [r7, #8] 8013bf2: 607a str r2, [r7, #4] 8013bf4: 603b str r3, [r7, #0] Queue_t * pxNewQueue = NULL; 8013bf6: 2300 movs r3, #0 8013bf8: 627b str r3, [r7, #36] @ 0x24 /* The StaticQueue_t structure and the queue storage area must be * supplied. */ configASSERT( pxStaticQueue ); 8013bfa: 683b ldr r3, [r7, #0] 8013bfc: 2b00 cmp r3, #0 8013bfe: d10b bne.n 8013c18 __asm volatile 8013c00: f04f 0350 mov.w r3, #80 @ 0x50 8013c04: f383 8811 msr BASEPRI, r3 8013c08: f3bf 8f6f isb sy 8013c0c: f3bf 8f4f dsb sy 8013c10: 623b str r3, [r7, #32] } 8013c12: bf00 nop 8013c14: bf00 nop 8013c16: e7fd b.n 8013c14 if( ( uxQueueLength > ( UBaseType_t ) 0 ) && 8013c18: 68fb ldr r3, [r7, #12] 8013c1a: 2b00 cmp r3, #0 8013c1c: d031 beq.n 8013c82 8013c1e: 683b ldr r3, [r7, #0] 8013c20: 2b00 cmp r3, #0 8013c22: d02e beq.n 8013c82 ( pxStaticQueue != NULL ) && 8013c24: 687b ldr r3, [r7, #4] 8013c26: 2b00 cmp r3, #0 8013c28: d002 beq.n 8013c30 /* A queue storage area should be provided if the item size is not 0, and * should not be provided if the item size is 0. */ ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) && 8013c2a: 68bb ldr r3, [r7, #8] 8013c2c: 2b00 cmp r3, #0 8013c2e: d028 beq.n 8013c82 8013c30: 687b ldr r3, [r7, #4] 8013c32: 2b00 cmp r3, #0 8013c34: d102 bne.n 8013c3c ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) ) 8013c36: 68bb ldr r3, [r7, #8] 8013c38: 2b00 cmp r3, #0 8013c3a: d122 bne.n 8013c82 #if ( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a * variable of type StaticQueue_t or StaticSemaphore_t equals the size of * the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8013c3c: 2350 movs r3, #80 @ 0x50 8013c3e: 617b str r3, [r7, #20] /* This assertion cannot be branch covered in unit tests */ configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */ 8013c40: 697b ldr r3, [r7, #20] 8013c42: 2b50 cmp r3, #80 @ 0x50 8013c44: d00b beq.n 8013c5e __asm volatile 8013c46: f04f 0350 mov.w r3, #80 @ 0x50 8013c4a: f383 8811 msr BASEPRI, r3 8013c4e: f3bf 8f6f isb sy 8013c52: f3bf 8f4f dsb sy 8013c56: 61fb str r3, [r7, #28] } 8013c58: bf00 nop 8013c5a: bf00 nop 8013c5c: e7fd b.n 8013c5a ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8013c5e: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. * The address of a statically allocated storage area was also passed in * but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8013c60: 683b ldr r3, [r7, #0] 8013c62: 627b str r3, [r7, #36] @ 0x24 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so * note this queue was allocated statically in case the queue is * later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8013c64: 6a7b ldr r3, [r7, #36] @ 0x24 8013c66: 2201 movs r2, #1 8013c68: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8013c6c: f897 2030 ldrb.w r2, [r7, #48] @ 0x30 8013c70: 6a7b ldr r3, [r7, #36] @ 0x24 8013c72: 9300 str r3, [sp, #0] 8013c74: 4613 mov r3, r2 8013c76: 687a ldr r2, [r7, #4] 8013c78: 68b9 ldr r1, [r7, #8] 8013c7a: 68f8 ldr r0, [r7, #12] 8013c7c: f000 f868 bl 8013d50 8013c80: e00e b.n 8013ca0 } else { configASSERT( pxNewQueue ); 8013c82: 6a7b ldr r3, [r7, #36] @ 0x24 8013c84: 2b00 cmp r3, #0 8013c86: d10b bne.n 8013ca0 __asm volatile 8013c88: f04f 0350 mov.w r3, #80 @ 0x50 8013c8c: f383 8811 msr BASEPRI, r3 8013c90: f3bf 8f6f isb sy 8013c94: f3bf 8f4f dsb sy 8013c98: 61bb str r3, [r7, #24] } 8013c9a: bf00 nop 8013c9c: bf00 nop 8013c9e: e7fd b.n 8013c9c mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8013ca0: 6a7b ldr r3, [r7, #36] @ 0x24 } 8013ca2: 4618 mov r0, r3 8013ca4: 3728 adds r7, #40 @ 0x28 8013ca6: 46bd mov sp, r7 8013ca8: bd80 pop {r7, pc} 08013caa : #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 8013caa: b580 push {r7, lr} 8013cac: b08a sub sp, #40 @ 0x28 8013cae: af02 add r7, sp, #8 8013cb0: 60f8 str r0, [r7, #12] 8013cb2: 60b9 str r1, [r7, #8] 8013cb4: 4613 mov r3, r2 8013cb6: 71fb strb r3, [r7, #7] Queue_t * pxNewQueue = NULL; 8013cb8: 2300 movs r3, #0 8013cba: 61fb str r3, [r7, #28] size_t xQueueSizeInBytes; uint8_t * pucQueueStorage; if( ( uxQueueLength > ( UBaseType_t ) 0 ) && 8013cbc: 68fb ldr r3, [r7, #12] 8013cbe: 2b00 cmp r3, #0 8013cc0: d032 beq.n 8013d28 /* Check for multiplication overflow. */ ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) && 8013cc2: 2100 movs r1, #0 8013cc4: 68ba ldr r2, [r7, #8] 8013cc6: 68fb ldr r3, [r7, #12] 8013cc8: fba3 2302 umull r2, r3, r3, r2 8013ccc: 2b00 cmp r3, #0 8013cce: d000 beq.n 8013cd2 8013cd0: 2101 movs r1, #1 8013cd2: 460b mov r3, r1 if( ( uxQueueLength > ( UBaseType_t ) 0 ) && 8013cd4: 2b00 cmp r3, #0 8013cd6: d127 bne.n 8013d28 /* Check for addition overflow. */ ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) ) 8013cd8: 68fb ldr r3, [r7, #12] 8013cda: 68ba ldr r2, [r7, #8] 8013cdc: fb02 f303 mul.w r3, r2, r3 ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) && 8013ce0: f113 0f51 cmn.w r3, #81 @ 0x51 8013ce4: d820 bhi.n 8013d28 { /* Allocate enough space to hold the maximum number of items that * can be in the queue at any time. It is valid for uxItemSize to be * zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8013ce6: 68fb ldr r3, [r7, #12] 8013ce8: 68ba ldr r2, [r7, #8] 8013cea: fb02 f303 mul.w r3, r2, r3 8013cee: 61bb str r3, [r7, #24] * alignment requirements of the Queue_t structure - which in this case * is an int8_t *. Therefore, whenever the stack alignment requirements * are greater than or equal to the pointer to char requirements the cast * is safe. In other cases alignment requirements are not strict (one or * two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 8013cf0: 69bb ldr r3, [r7, #24] 8013cf2: 3350 adds r3, #80 @ 0x50 8013cf4: 4618 mov r0, r3 8013cf6: f003 fc5b bl 80175b0 8013cfa: 61f8 str r0, [r7, #28] if( pxNewQueue != NULL ) 8013cfc: 69fb ldr r3, [r7, #28] 8013cfe: 2b00 cmp r3, #0 8013d00: d021 beq.n 8013d46 { /* Jump past the queue structure to find the location of the queue * storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 8013d02: 69fb ldr r3, [r7, #28] 8013d04: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8013d06: 697b ldr r3, [r7, #20] 8013d08: 3350 adds r3, #80 @ 0x50 8013d0a: 617b str r3, [r7, #20] #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so * note this task was created dynamically in case it is later * deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8013d0c: 69fb ldr r3, [r7, #28] 8013d0e: 2200 movs r2, #0 8013d10: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8013d14: 79fa ldrb r2, [r7, #7] 8013d16: 69fb ldr r3, [r7, #28] 8013d18: 9300 str r3, [sp, #0] 8013d1a: 4613 mov r3, r2 8013d1c: 697a ldr r2, [r7, #20] 8013d1e: 68b9 ldr r1, [r7, #8] 8013d20: 68f8 ldr r0, [r7, #12] 8013d22: f000 f815 bl 8013d50 if( pxNewQueue != NULL ) 8013d26: e00e b.n 8013d46 mtCOVERAGE_TEST_MARKER(); } } else { configASSERT( pxNewQueue ); 8013d28: 69fb ldr r3, [r7, #28] 8013d2a: 2b00 cmp r3, #0 8013d2c: d10b bne.n 8013d46 __asm volatile 8013d2e: f04f 0350 mov.w r3, #80 @ 0x50 8013d32: f383 8811 msr BASEPRI, r3 8013d36: f3bf 8f6f isb sy 8013d3a: f3bf 8f4f dsb sy 8013d3e: 613b str r3, [r7, #16] } 8013d40: bf00 nop 8013d42: bf00 nop 8013d44: e7fd b.n 8013d42 mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8013d46: 69fb ldr r3, [r7, #28] } 8013d48: 4618 mov r0, r3 8013d4a: 3720 adds r7, #32 8013d4c: 46bd mov sp, r7 8013d4e: bd80 pop {r7, pc} 08013d50 : static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t * pucQueueStorage, const uint8_t ucQueueType, Queue_t * pxNewQueue ) { 8013d50: b580 push {r7, lr} 8013d52: b084 sub sp, #16 8013d54: af00 add r7, sp, #0 8013d56: 60f8 str r0, [r7, #12] 8013d58: 60b9 str r1, [r7, #8] 8013d5a: 607a str r2, [r7, #4] 8013d5c: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should * configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 8013d5e: 68bb ldr r3, [r7, #8] 8013d60: 2b00 cmp r3, #0 8013d62: d103 bne.n 8013d6c { /* No RAM was allocated for the queue storage area, but PC head cannot * be set to NULL because NULL is used as a key to say the queue is used as * a mutex. Therefore just set pcHead to point to the queue as a benign * value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8013d64: 69bb ldr r3, [r7, #24] 8013d66: 69ba ldr r2, [r7, #24] 8013d68: 601a str r2, [r3, #0] 8013d6a: e002 b.n 8013d72 } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8013d6c: 69bb ldr r3, [r7, #24] 8013d6e: 687a ldr r2, [r7, #4] 8013d70: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is * defined. */ pxNewQueue->uxLength = uxQueueLength; 8013d72: 69bb ldr r3, [r7, #24] 8013d74: 68fa ldr r2, [r7, #12] 8013d76: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8013d78: 69bb ldr r3, [r7, #24] 8013d7a: 68ba ldr r2, [r7, #8] 8013d7c: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 8013d7e: 2101 movs r1, #1 8013d80: 69b8 ldr r0, [r7, #24] 8013d82: f7ff fe9f bl 8013ac4 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8013d86: 69bb ldr r3, [r7, #24] 8013d88: 78fa ldrb r2, [r7, #3] 8013d8a: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 8013d8e: bf00 nop 8013d90: 3710 adds r7, #16 8013d92: 46bd mov sp, r7 8013d94: bd80 pop {r7, pc} 08013d96 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t * pxNewQueue ) { 8013d96: b580 push {r7, lr} 8013d98: b082 sub sp, #8 8013d9a: af00 add r7, sp, #0 8013d9c: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 8013d9e: 687b ldr r3, [r7, #4] 8013da0: 2b00 cmp r3, #0 8013da2: d00e beq.n 8013dc2 { /* The queue create function will set all the queue structure members * correctly for a generic queue, but this function is creating a * mutex. Overwrite those members that need to be set differently - * in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8013da4: 687b ldr r3, [r7, #4] 8013da6: 2200 movs r2, #0 8013da8: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8013daa: 687b ldr r3, [r7, #4] 8013dac: 2200 movs r2, #0 8013dae: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 8013db0: 687b ldr r3, [r7, #4] 8013db2: 2200 movs r2, #0 8013db4: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8013db6: 2300 movs r3, #0 8013db8: 2200 movs r2, #0 8013dba: 2100 movs r1, #0 8013dbc: 6878 ldr r0, [r7, #4] 8013dbe: f000 f905 bl 8013fcc } else { traceCREATE_MUTEX_FAILED(); } } 8013dc2: bf00 nop 8013dc4: 3708 adds r7, #8 8013dc6: 46bd mov sp, r7 8013dc8: bd80 pop {r7, pc} 08013dca : /*-----------------------------------------------------------*/ #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 8013dca: b580 push {r7, lr} 8013dcc: b086 sub sp, #24 8013dce: af00 add r7, sp, #0 8013dd0: 4603 mov r3, r0 8013dd2: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8013dd4: 2301 movs r3, #1 8013dd6: 617b str r3, [r7, #20] 8013dd8: 2300 movs r3, #0 8013dda: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 8013ddc: 79fb ldrb r3, [r7, #7] 8013dde: 461a mov r2, r3 8013de0: 6939 ldr r1, [r7, #16] 8013de2: 6978 ldr r0, [r7, #20] 8013de4: f7ff ff61 bl 8013caa 8013de8: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8013dea: 68f8 ldr r0, [r7, #12] 8013dec: f7ff ffd3 bl 8013d96 return xNewQueue; 8013df0: 68fb ldr r3, [r7, #12] } 8013df2: 4618 mov r0, r3 8013df4: 3718 adds r7, #24 8013df6: 46bd mov sp, r7 8013df8: bd80 pop {r7, pc} 08013dfa : #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t * pxStaticQueue ) { 8013dfa: b580 push {r7, lr} 8013dfc: b088 sub sp, #32 8013dfe: af02 add r7, sp, #8 8013e00: 4603 mov r3, r0 8013e02: 6039 str r1, [r7, #0] 8013e04: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8013e06: 2301 movs r3, #1 8013e08: 617b str r3, [r7, #20] 8013e0a: 2300 movs r3, #0 8013e0c: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if * configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 8013e0e: 79fb ldrb r3, [r7, #7] 8013e10: 9300 str r3, [sp, #0] 8013e12: 683b ldr r3, [r7, #0] 8013e14: 2200 movs r2, #0 8013e16: 6939 ldr r1, [r7, #16] 8013e18: 6978 ldr r0, [r7, #20] 8013e1a: f7ff fee5 bl 8013be8 8013e1e: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8013e20: 68f8 ldr r0, [r7, #12] 8013e22: f7ff ffb8 bl 8013d96 return xNewQueue; 8013e26: 68fb ldr r3, [r7, #12] } 8013e28: 4618 mov r0, r3 8013e2a: 3718 adds r7, #24 8013e2c: 46bd mov sp, r7 8013e2e: bd80 pop {r7, pc} 08013e30 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 8013e30: b590 push {r4, r7, lr} 8013e32: b087 sub sp, #28 8013e34: af00 add r7, sp, #0 8013e36: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8013e38: 687b ldr r3, [r7, #4] 8013e3a: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8013e3c: 693b ldr r3, [r7, #16] 8013e3e: 2b00 cmp r3, #0 8013e40: d10b bne.n 8013e5a __asm volatile 8013e42: f04f 0350 mov.w r3, #80 @ 0x50 8013e46: f383 8811 msr BASEPRI, r3 8013e4a: f3bf 8f6f isb sy 8013e4e: f3bf 8f4f dsb sy 8013e52: 60fb str r3, [r7, #12] } 8013e54: bf00 nop 8013e56: bf00 nop 8013e58: e7fd b.n 8013e56 * change outside of this task. If this task does not hold the mutex then * pxMutexHolder can never coincidentally equal the tasks handle, and as * this is the only condition we are interested in it does not matter if * pxMutexHolder is accessed simultaneously by another task. Therefore no * mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8013e5a: 693b ldr r3, [r7, #16] 8013e5c: 689c ldr r4, [r3, #8] 8013e5e: f001 ff53 bl 8015d08 8013e62: 4603 mov r3, r0 8013e64: 429c cmp r4, r3 8013e66: d111 bne.n 8013e8c /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to * the task handle, therefore no underflow check is required. Also, * uxRecursiveCallCount is only modified by the mutex holder, and as * there can only be one, no mutual exclusion is required to modify the * uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8013e68: 693b ldr r3, [r7, #16] 8013e6a: 68db ldr r3, [r3, #12] 8013e6c: 1e5a subs r2, r3, #1 8013e6e: 693b ldr r3, [r7, #16] 8013e70: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 8013e72: 693b ldr r3, [r7, #16] 8013e74: 68db ldr r3, [r3, #12] 8013e76: 2b00 cmp r3, #0 8013e78: d105 bne.n 8013e86 { /* Return the mutex. This will automatically unblock any other * task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8013e7a: 2300 movs r3, #0 8013e7c: 2200 movs r2, #0 8013e7e: 2100 movs r1, #0 8013e80: 6938 ldr r0, [r7, #16] 8013e82: f000 f8a3 bl 8013fcc else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8013e86: 2301 movs r3, #1 8013e88: 617b str r3, [r7, #20] 8013e8a: e001 b.n 8013e90 } else { /* The mutex cannot be given because the calling task is not the * holder. */ xReturn = pdFAIL; 8013e8c: 2300 movs r3, #0 8013e8e: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 8013e90: 697b ldr r3, [r7, #20] } 8013e92: 4618 mov r0, r3 8013e94: 371c adds r7, #28 8013e96: 46bd mov sp, r7 8013e98: bd90 pop {r4, r7, pc} 08013e9a : #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 8013e9a: b590 push {r4, r7, lr} 8013e9c: b087 sub sp, #28 8013e9e: af00 add r7, sp, #0 8013ea0: 6078 str r0, [r7, #4] 8013ea2: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8013ea4: 687b ldr r3, [r7, #4] 8013ea6: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8013ea8: 693b ldr r3, [r7, #16] 8013eaa: 2b00 cmp r3, #0 8013eac: d10b bne.n 8013ec6 __asm volatile 8013eae: f04f 0350 mov.w r3, #80 @ 0x50 8013eb2: f383 8811 msr BASEPRI, r3 8013eb6: f3bf 8f6f isb sy 8013eba: f3bf 8f4f dsb sy 8013ebe: 60fb str r3, [r7, #12] } 8013ec0: bf00 nop 8013ec2: bf00 nop 8013ec4: e7fd b.n 8013ec2 /* Comments regarding mutual exclusion as per those within * xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8013ec6: 693b ldr r3, [r7, #16] 8013ec8: 689c ldr r4, [r3, #8] 8013eca: f001 ff1d bl 8015d08 8013ece: 4603 mov r3, r0 8013ed0: 429c cmp r4, r3 8013ed2: d107 bne.n 8013ee4 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8013ed4: 693b ldr r3, [r7, #16] 8013ed6: 68db ldr r3, [r3, #12] 8013ed8: 1c5a adds r2, r3, #1 8013eda: 693b ldr r3, [r7, #16] 8013edc: 60da str r2, [r3, #12] xReturn = pdPASS; 8013ede: 2301 movs r3, #1 8013ee0: 617b str r3, [r7, #20] 8013ee2: e00c b.n 8013efe } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 8013ee4: 6839 ldr r1, [r7, #0] 8013ee6: 6938 ldr r0, [r7, #16] 8013ee8: f000 fbb2 bl 8014650 8013eec: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully * obtained. The calling task may have entered the Blocked state * before reaching here. */ if( xReturn != pdFAIL ) 8013eee: 697b ldr r3, [r7, #20] 8013ef0: 2b00 cmp r3, #0 8013ef2: d004 beq.n 8013efe { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8013ef4: 693b ldr r3, [r7, #16] 8013ef6: 68db ldr r3, [r3, #12] 8013ef8: 1c5a adds r2, r3, #1 8013efa: 693b ldr r3, [r7, #16] 8013efc: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 8013efe: 697b ldr r3, [r7, #20] } 8013f00: 4618 mov r0, r3 8013f02: 371c adds r7, #28 8013f04: 46bd mov sp, r7 8013f06: bd90 pop {r4, r7, pc} 08013f08 : #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t * pxStaticQueue ) { 8013f08: b580 push {r7, lr} 8013f0a: b088 sub sp, #32 8013f0c: af02 add r7, sp, #8 8013f0e: 60f8 str r0, [r7, #12] 8013f10: 60b9 str r1, [r7, #8] 8013f12: 607a str r2, [r7, #4] QueueHandle_t xHandle = NULL; 8013f14: 2300 movs r3, #0 8013f16: 617b str r3, [r7, #20] if( ( uxMaxCount != 0 ) && 8013f18: 68fb ldr r3, [r7, #12] 8013f1a: 2b00 cmp r3, #0 8013f1c: d013 beq.n 8013f46 8013f1e: 68ba ldr r2, [r7, #8] 8013f20: 68fb ldr r3, [r7, #12] 8013f22: 429a cmp r2, r3 8013f24: d80f bhi.n 8013f46 ( uxInitialCount <= uxMaxCount ) ) { xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); 8013f26: 2302 movs r3, #2 8013f28: 9300 str r3, [sp, #0] 8013f2a: 687b ldr r3, [r7, #4] 8013f2c: 2200 movs r2, #0 8013f2e: 2100 movs r1, #0 8013f30: 68f8 ldr r0, [r7, #12] 8013f32: f7ff fe59 bl 8013be8 8013f36: 6178 str r0, [r7, #20] if( xHandle != NULL ) 8013f38: 697b ldr r3, [r7, #20] 8013f3a: 2b00 cmp r3, #0 8013f3c: d012 beq.n 8013f64 { ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; 8013f3e: 697b ldr r3, [r7, #20] 8013f40: 68ba ldr r2, [r7, #8] 8013f42: 639a str r2, [r3, #56] @ 0x38 if( xHandle != NULL ) 8013f44: e00e b.n 8013f64 traceCREATE_COUNTING_SEMAPHORE_FAILED(); } } else { configASSERT( xHandle ); 8013f46: 697b ldr r3, [r7, #20] 8013f48: 2b00 cmp r3, #0 8013f4a: d10b bne.n 8013f64 __asm volatile 8013f4c: f04f 0350 mov.w r3, #80 @ 0x50 8013f50: f383 8811 msr BASEPRI, r3 8013f54: f3bf 8f6f isb sy 8013f58: f3bf 8f4f dsb sy 8013f5c: 613b str r3, [r7, #16] } 8013f5e: bf00 nop 8013f60: bf00 nop 8013f62: e7fd b.n 8013f60 mtCOVERAGE_TEST_MARKER(); } return xHandle; 8013f64: 697b ldr r3, [r7, #20] } 8013f66: 4618 mov r0, r3 8013f68: 3718 adds r7, #24 8013f6a: 46bd mov sp, r7 8013f6c: bd80 pop {r7, pc} 08013f6e : #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) { 8013f6e: b580 push {r7, lr} 8013f70: b084 sub sp, #16 8013f72: af00 add r7, sp, #0 8013f74: 6078 str r0, [r7, #4] 8013f76: 6039 str r1, [r7, #0] QueueHandle_t xHandle = NULL; 8013f78: 2300 movs r3, #0 8013f7a: 60fb str r3, [r7, #12] if( ( uxMaxCount != 0 ) && 8013f7c: 687b ldr r3, [r7, #4] 8013f7e: 2b00 cmp r3, #0 8013f80: d010 beq.n 8013fa4 8013f82: 683a ldr r2, [r7, #0] 8013f84: 687b ldr r3, [r7, #4] 8013f86: 429a cmp r2, r3 8013f88: d80c bhi.n 8013fa4 ( uxInitialCount <= uxMaxCount ) ) { xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); 8013f8a: 2202 movs r2, #2 8013f8c: 2100 movs r1, #0 8013f8e: 6878 ldr r0, [r7, #4] 8013f90: f7ff fe8b bl 8013caa 8013f94: 60f8 str r0, [r7, #12] if( xHandle != NULL ) 8013f96: 68fb ldr r3, [r7, #12] 8013f98: 2b00 cmp r3, #0 8013f9a: d012 beq.n 8013fc2 { ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; 8013f9c: 68fb ldr r3, [r7, #12] 8013f9e: 683a ldr r2, [r7, #0] 8013fa0: 639a str r2, [r3, #56] @ 0x38 if( xHandle != NULL ) 8013fa2: e00e b.n 8013fc2 traceCREATE_COUNTING_SEMAPHORE_FAILED(); } } else { configASSERT( xHandle ); 8013fa4: 68fb ldr r3, [r7, #12] 8013fa6: 2b00 cmp r3, #0 8013fa8: d10b bne.n 8013fc2 __asm volatile 8013faa: f04f 0350 mov.w r3, #80 @ 0x50 8013fae: f383 8811 msr BASEPRI, r3 8013fb2: f3bf 8f6f isb sy 8013fb6: f3bf 8f4f dsb sy 8013fba: 60bb str r3, [r7, #8] } 8013fbc: bf00 nop 8013fbe: bf00 nop 8013fc0: e7fd b.n 8013fbe mtCOVERAGE_TEST_MARKER(); } return xHandle; 8013fc2: 68fb ldr r3, [r7, #12] } 8013fc4: 4618 mov r0, r3 8013fc6: 3710 adds r7, #16 8013fc8: 46bd mov sp, r7 8013fca: bd80 pop {r7, pc} 08013fcc : BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8013fcc: b580 push {r7, lr} 8013fce: b08e sub sp, #56 @ 0x38 8013fd0: af00 add r7, sp, #0 8013fd2: 60f8 str r0, [r7, #12] 8013fd4: 60b9 str r1, [r7, #8] 8013fd6: 607a str r2, [r7, #4] 8013fd8: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8013fda: 2300 movs r3, #0 8013fdc: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8013fde: 68fb ldr r3, [r7, #12] 8013fe0: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8013fe2: 6b3b ldr r3, [r7, #48] @ 0x30 8013fe4: 2b00 cmp r3, #0 8013fe6: d10b bne.n 8014000 __asm volatile 8013fe8: f04f 0350 mov.w r3, #80 @ 0x50 8013fec: f383 8811 msr BASEPRI, r3 8013ff0: f3bf 8f6f isb sy 8013ff4: f3bf 8f4f dsb sy 8013ff8: 62bb str r3, [r7, #40] @ 0x28 } 8013ffa: bf00 nop 8013ffc: bf00 nop 8013ffe: e7fd b.n 8013ffc configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014000: 68bb ldr r3, [r7, #8] 8014002: 2b00 cmp r3, #0 8014004: d103 bne.n 801400e 8014006: 6b3b ldr r3, [r7, #48] @ 0x30 8014008: 6c1b ldr r3, [r3, #64] @ 0x40 801400a: 2b00 cmp r3, #0 801400c: d101 bne.n 8014012 801400e: 2301 movs r3, #1 8014010: e000 b.n 8014014 8014012: 2300 movs r3, #0 8014014: 2b00 cmp r3, #0 8014016: d10b bne.n 8014030 __asm volatile 8014018: f04f 0350 mov.w r3, #80 @ 0x50 801401c: f383 8811 msr BASEPRI, r3 8014020: f3bf 8f6f isb sy 8014024: f3bf 8f4f dsb sy 8014028: 627b str r3, [r7, #36] @ 0x24 } 801402a: bf00 nop 801402c: bf00 nop 801402e: e7fd b.n 801402c configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014030: 683b ldr r3, [r7, #0] 8014032: 2b02 cmp r3, #2 8014034: d103 bne.n 801403e 8014036: 6b3b ldr r3, [r7, #48] @ 0x30 8014038: 6bdb ldr r3, [r3, #60] @ 0x3c 801403a: 2b01 cmp r3, #1 801403c: d101 bne.n 8014042 801403e: 2301 movs r3, #1 8014040: e000 b.n 8014044 8014042: 2300 movs r3, #0 8014044: 2b00 cmp r3, #0 8014046: d10b bne.n 8014060 __asm volatile 8014048: f04f 0350 mov.w r3, #80 @ 0x50 801404c: f383 8811 msr BASEPRI, r3 8014050: f3bf 8f6f isb sy 8014054: f3bf 8f4f dsb sy 8014058: 623b str r3, [r7, #32] } 801405a: bf00 nop 801405c: bf00 nop 801405e: e7fd b.n 801405c #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014060: f001 fe62 bl 8015d28 8014064: 4603 mov r3, r0 8014066: 2b00 cmp r3, #0 8014068: d102 bne.n 8014070 801406a: 687b ldr r3, [r7, #4] 801406c: 2b00 cmp r3, #0 801406e: d101 bne.n 8014074 8014070: 2301 movs r3, #1 8014072: e000 b.n 8014076 8014074: 2300 movs r3, #0 8014076: 2b00 cmp r3, #0 8014078: d10b bne.n 8014092 __asm volatile 801407a: f04f 0350 mov.w r3, #80 @ 0x50 801407e: f383 8811 msr BASEPRI, r3 8014082: f3bf 8f6f isb sy 8014086: f3bf 8f4f dsb sy 801408a: 61fb str r3, [r7, #28] } 801408c: bf00 nop 801408e: bf00 nop 8014090: e7fd b.n 801408e /*lint -save -e904 This function relaxes the coding standard somewhat to * allow return statements within the function itself. This is done in the * interest of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); 8014092: f003 f965 bl 8017360 { /* Is there room on the queue now? The running task must be the * highest priority task wanting to access the queue. If the head item * in the queue is to be overwritten then it does not matter if the * queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014096: 6b3b ldr r3, [r7, #48] @ 0x30 8014098: 6b9a ldr r2, [r3, #56] @ 0x38 801409a: 6b3b ldr r3, [r7, #48] @ 0x30 801409c: 6bdb ldr r3, [r3, #60] @ 0x3c 801409e: 429a cmp r2, r3 80140a0: d302 bcc.n 80140a8 80140a2: 683b ldr r3, [r7, #0] 80140a4: 2b02 cmp r3, #2 80140a6: d129 bne.n 80140fc } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80140a8: 683a ldr r2, [r7, #0] 80140aa: 68b9 ldr r1, [r7, #8] 80140ac: 6b38 ldr r0, [r7, #48] @ 0x30 80140ae: f000 fca5 bl 80149fc 80140b2: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the * queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80140b4: 6b3b ldr r3, [r7, #48] @ 0x30 80140b6: 6a5b ldr r3, [r3, #36] @ 0x24 80140b8: 2b00 cmp r3, #0 80140ba: d010 beq.n 80140de { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80140bc: 6b3b ldr r3, [r7, #48] @ 0x30 80140be: 3324 adds r3, #36 @ 0x24 80140c0: 4618 mov r0, r3 80140c2: f001 fbed bl 80158a0 80140c6: 4603 mov r3, r0 80140c8: 2b00 cmp r3, #0 80140ca: d013 beq.n 80140f4 { /* The unblocked task has a priority higher than * our own so yield immediately. Yes it is ok to do * this from within the critical section - the kernel * takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 80140cc: 4b3f ldr r3, [pc, #252] @ (80141cc ) 80140ce: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80140d2: 601a str r2, [r3, #0] 80140d4: f3bf 8f4f dsb sy 80140d8: f3bf 8f6f isb sy 80140dc: e00a b.n 80140f4 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 80140de: 6afb ldr r3, [r7, #44] @ 0x2c 80140e0: 2b00 cmp r3, #0 80140e2: d007 beq.n 80140f4 { /* This path is a special case that will only get * executed if the task was holding multiple mutexes and * the mutexes were given back in an order that is * different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 80140e4: 4b39 ldr r3, [pc, #228] @ (80141cc ) 80140e6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80140ea: 601a str r2, [r3, #0] 80140ec: f3bf 8f4f dsb sy 80140f0: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 80140f4: f003 f966 bl 80173c4 return pdPASS; 80140f8: 2301 movs r3, #1 80140fa: e063 b.n 80141c4 } else { if( xTicksToWait == ( TickType_t ) 0 ) 80140fc: 687b ldr r3, [r7, #4] 80140fe: 2b00 cmp r3, #0 8014100: d103 bne.n 801410a { /* The queue was full and no block time is specified (or * the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014102: f003 f95f bl 80173c4 /* Return to the original privilege level before exiting * the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014106: 2300 movs r3, #0 8014108: e05c b.n 80141c4 } else if( xEntryTimeSet == pdFALSE ) 801410a: 6b7b ldr r3, [r7, #52] @ 0x34 801410c: 2b00 cmp r3, #0 801410e: d106 bne.n 801411e { /* The queue was full and a block time was specified so * configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014110: f107 0314 add.w r3, r7, #20 8014114: 4618 mov r0, r3 8014116: f001 fc9b bl 8015a50 xEntryTimeSet = pdTRUE; 801411a: 2301 movs r3, #1 801411c: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 801411e: f003 f951 bl 80173c4 /* Interrupts and other tasks can send to and receive from the queue * now the critical section has been exited. */ vTaskSuspendAll(); 8014122: f001 f8b3 bl 801528c prvLockQueue( pxQueue ); 8014126: f003 f91b bl 8017360 801412a: 6b3b ldr r3, [r7, #48] @ 0x30 801412c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014130: b25b sxtb r3, r3 8014132: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014136: d103 bne.n 8014140 8014138: 6b3b ldr r3, [r7, #48] @ 0x30 801413a: 2200 movs r2, #0 801413c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014140: 6b3b ldr r3, [r7, #48] @ 0x30 8014142: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014146: b25b sxtb r3, r3 8014148: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801414c: d103 bne.n 8014156 801414e: 6b3b ldr r3, [r7, #48] @ 0x30 8014150: 2200 movs r2, #0 8014152: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014156: f003 f935 bl 80173c4 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 801415a: 1d3a adds r2, r7, #4 801415c: f107 0314 add.w r3, r7, #20 8014160: 4611 mov r1, r2 8014162: 4618 mov r0, r3 8014164: f001 fc8a bl 8015a7c 8014168: 4603 mov r3, r0 801416a: 2b00 cmp r3, #0 801416c: d124 bne.n 80141b8 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 801416e: 6b38 ldr r0, [r7, #48] @ 0x30 8014170: f000 fd3c bl 8014bec 8014174: 4603 mov r3, r0 8014176: 2b00 cmp r3, #0 8014178: d018 beq.n 80141ac { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 801417a: 6b3b ldr r3, [r7, #48] @ 0x30 801417c: 3310 adds r3, #16 801417e: 687a ldr r2, [r7, #4] 8014180: 4611 mov r1, r2 8014182: 4618 mov r0, r3 8014184: f001 fb20 bl 80157c8 /* Unlocking the queue means queue events can effect the * event list. It is possible that interrupts occurring now * remove this task from the event list again - but as the * scheduler is suspended the task will go onto the pending * ready list instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8014188: 6b38 ldr r0, [r7, #48] @ 0x30 801418a: f000 fcc7 bl 8014b1c /* Resuming the scheduler will move tasks from the pending * ready list into the ready list - so it is feasible that this * task is already in the ready list before it yields - in which * case the yield will not cause a context switch unless there * is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 801418e: f001 f88b bl 80152a8 8014192: 4603 mov r3, r0 8014194: 2b00 cmp r3, #0 8014196: f47f af7c bne.w 8014092 { portYIELD_WITHIN_API(); 801419a: 4b0c ldr r3, [pc, #48] @ (80141cc ) 801419c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80141a0: 601a str r2, [r3, #0] 80141a2: f3bf 8f4f dsb sy 80141a6: f3bf 8f6f isb sy 80141aa: e772 b.n 8014092 } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 80141ac: 6b38 ldr r0, [r7, #48] @ 0x30 80141ae: f000 fcb5 bl 8014b1c ( void ) xTaskResumeAll(); 80141b2: f001 f879 bl 80152a8 80141b6: e76c b.n 8014092 } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 80141b8: 6b38 ldr r0, [r7, #48] @ 0x30 80141ba: f000 fcaf bl 8014b1c ( void ) xTaskResumeAll(); 80141be: f001 f873 bl 80152a8 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 80141c2: 2300 movs r3, #0 } } /*lint -restore */ } 80141c4: 4618 mov r0, r3 80141c6: 3738 adds r7, #56 @ 0x38 80141c8: 46bd mov sp, r7 80141ca: bd80 pop {r7, pc} 80141cc: e000ed04 .word 0xe000ed04 080141d0 : BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 80141d0: b580 push {r7, lr} 80141d2: b092 sub sp, #72 @ 0x48 80141d4: af00 add r7, sp, #0 80141d6: 60f8 str r0, [r7, #12] 80141d8: 60b9 str r1, [r7, #8] 80141da: 607a str r2, [r7, #4] 80141dc: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 80141de: 68fb ldr r3, [r7, #12] 80141e0: 643b str r3, [r7, #64] @ 0x40 configASSERT( pxQueue ); 80141e2: 6c3b ldr r3, [r7, #64] @ 0x40 80141e4: 2b00 cmp r3, #0 80141e6: d10b bne.n 8014200 __asm volatile 80141e8: f04f 0350 mov.w r3, #80 @ 0x50 80141ec: f383 8811 msr BASEPRI, r3 80141f0: f3bf 8f6f isb sy 80141f4: f3bf 8f4f dsb sy 80141f8: 62fb str r3, [r7, #44] @ 0x2c } 80141fa: bf00 nop 80141fc: bf00 nop 80141fe: e7fd b.n 80141fc configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014200: 68bb ldr r3, [r7, #8] 8014202: 2b00 cmp r3, #0 8014204: d103 bne.n 801420e 8014206: 6c3b ldr r3, [r7, #64] @ 0x40 8014208: 6c1b ldr r3, [r3, #64] @ 0x40 801420a: 2b00 cmp r3, #0 801420c: d101 bne.n 8014212 801420e: 2301 movs r3, #1 8014210: e000 b.n 8014214 8014212: 2300 movs r3, #0 8014214: 2b00 cmp r3, #0 8014216: d10b bne.n 8014230 __asm volatile 8014218: f04f 0350 mov.w r3, #80 @ 0x50 801421c: f383 8811 msr BASEPRI, r3 8014220: f3bf 8f6f isb sy 8014224: f3bf 8f4f dsb sy 8014228: 62bb str r3, [r7, #40] @ 0x28 } 801422a: bf00 nop 801422c: bf00 nop 801422e: e7fd b.n 801422c configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014230: 683b ldr r3, [r7, #0] 8014232: 2b02 cmp r3, #2 8014234: d103 bne.n 801423e 8014236: 6c3b ldr r3, [r7, #64] @ 0x40 8014238: 6bdb ldr r3, [r3, #60] @ 0x3c 801423a: 2b01 cmp r3, #1 801423c: d101 bne.n 8014242 801423e: 2301 movs r3, #1 8014240: e000 b.n 8014244 8014242: 2300 movs r3, #0 8014244: 2b00 cmp r3, #0 8014246: d10b bne.n 8014260 __asm volatile 8014248: f04f 0350 mov.w r3, #80 @ 0x50 801424c: f383 8811 msr BASEPRI, r3 8014250: f3bf 8f6f isb sy 8014254: f3bf 8f4f dsb sy 8014258: 627b str r3, [r7, #36] @ 0x24 } 801425a: bf00 nop 801425c: bf00 nop 801425e: e7fd b.n 801425c * that have been assigned a priority at or (logically) below the maximum * system call interrupt priority. FreeRTOS maintains a separate interrupt * safe API to ensure interrupt entry is as fast and as simple as possible. * More information (albeit Cortex-M specific) is provided on the following * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8014260: f003 f964 bl 801752c portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 8014264: f3ef 8211 mrs r2, BASEPRI 8014268: f04f 0350 mov.w r3, #80 @ 0x50 801426c: f383 8811 msr BASEPRI, r3 8014270: f3bf 8f6f isb sy 8014274: f3bf 8f4f dsb sy 8014278: 623a str r2, [r7, #32] 801427a: 61fb str r3, [r7, #28] : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler * warnings. */ return ulOriginalBASEPRI; 801427c: 6a3b ldr r3, [r7, #32] /* Similar to xQueueGenericSend, except without blocking if there is no room * in the queue. Also don't directly wake a task that was blocked on a queue * read, instead return a flag to say whether a context switch is required or * not (i.e. has a task with a higher priority than us been woken by this * post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 801427e: 63fb str r3, [r7, #60] @ 0x3c { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014280: 6c3b ldr r3, [r7, #64] @ 0x40 8014282: 6b9a ldr r2, [r3, #56] @ 0x38 8014284: 6c3b ldr r3, [r7, #64] @ 0x40 8014286: 6bdb ldr r3, [r3, #60] @ 0x3c 8014288: 429a cmp r2, r3 801428a: d302 bcc.n 8014292 801428c: 683b ldr r3, [r7, #0] 801428e: 2b02 cmp r3, #2 8014290: d147 bne.n 8014322 { const int8_t cTxLock = pxQueue->cTxLock; 8014292: 6c3b ldr r3, [r7, #64] @ 0x40 8014294: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014298: f887 303b strb.w r3, [r7, #59] @ 0x3b const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 801429c: 6c3b ldr r3, [r7, #64] @ 0x40 801429e: 6b9b ldr r3, [r3, #56] @ 0x38 80142a0: 637b str r3, [r7, #52] @ 0x34 /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a * semaphore or mutex. That means prvCopyDataToQueue() cannot result * in a task disinheriting a priority and prvCopyDataToQueue() can be * called here even though the disinherit function does not check if * the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80142a2: 683a ldr r2, [r7, #0] 80142a4: 68b9 ldr r1, [r7, #8] 80142a6: 6c38 ldr r0, [r7, #64] @ 0x40 80142a8: f000 fba8 bl 80149fc /* The event list is not altered if the queue is locked. This will * be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80142ac: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b 80142b0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80142b4: d112 bne.n 80142dc } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80142b6: 6c3b ldr r3, [r7, #64] @ 0x40 80142b8: 6a5b ldr r3, [r3, #36] @ 0x24 80142ba: 2b00 cmp r3, #0 80142bc: d02e beq.n 801431c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80142be: 6c3b ldr r3, [r7, #64] @ 0x40 80142c0: 3324 adds r3, #36 @ 0x24 80142c2: 4618 mov r0, r3 80142c4: f001 faec bl 80158a0 80142c8: 4603 mov r3, r0 80142ca: 2b00 cmp r3, #0 80142cc: d026 beq.n 801431c { /* The task waiting has a higher priority so record that a * context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80142ce: 687b ldr r3, [r7, #4] 80142d0: 2b00 cmp r3, #0 80142d2: d023 beq.n 801431c { *pxHigherPriorityTaskWoken = pdTRUE; 80142d4: 687b ldr r3, [r7, #4] 80142d6: 2201 movs r2, #1 80142d8: 601a str r2, [r3, #0] 80142da: e01f b.n 801431c } else { /* Increment the lock count so the task that unlocks the queue * knows that data was posted while it was locked. */ prvIncrementQueueTxLock( pxQueue, cTxLock ); 80142dc: f001 f8f2 bl 80154c4 80142e0: 6338 str r0, [r7, #48] @ 0x30 80142e2: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b 80142e6: 6b3a ldr r2, [r7, #48] @ 0x30 80142e8: 429a cmp r2, r3 80142ea: d917 bls.n 801431c 80142ec: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b 80142f0: 2b7f cmp r3, #127 @ 0x7f 80142f2: d10b bne.n 801430c __asm volatile 80142f4: f04f 0350 mov.w r3, #80 @ 0x50 80142f8: f383 8811 msr BASEPRI, r3 80142fc: f3bf 8f6f isb sy 8014300: f3bf 8f4f dsb sy 8014304: 61bb str r3, [r7, #24] } 8014306: bf00 nop 8014308: bf00 nop 801430a: e7fd b.n 8014308 801430c: f897 303b ldrb.w r3, [r7, #59] @ 0x3b 8014310: 3301 adds r3, #1 8014312: b2db uxtb r3, r3 8014314: b25a sxtb r2, r3 8014316: 6c3b ldr r3, [r7, #64] @ 0x40 8014318: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 801431c: 2301 movs r3, #1 801431e: 647b str r3, [r7, #68] @ 0x44 { 8014320: e001 b.n 8014326 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 8014322: 2300 movs r3, #0 8014324: 647b str r3, [r7, #68] @ 0x44 8014326: 6bfb ldr r3, [r7, #60] @ 0x3c 8014328: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 801432a: 697b ldr r3, [r7, #20] 801432c: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" ); } 8014330: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8014332: 6c7b ldr r3, [r7, #68] @ 0x44 } 8014334: 4618 mov r0, r3 8014336: 3748 adds r7, #72 @ 0x48 8014338: 46bd mov sp, r7 801433a: bd80 pop {r7, pc} 0801433c : /*-----------------------------------------------------------*/ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) { 801433c: b580 push {r7, lr} 801433e: b090 sub sp, #64 @ 0x40 8014340: af00 add r7, sp, #0 8014342: 6078 str r0, [r7, #4] 8014344: 6039 str r1, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014346: 687b ldr r3, [r7, #4] 8014348: 63bb str r3, [r7, #56] @ 0x38 * item size is 0. Don't directly wake a task that was blocked on a queue * read, instead return a flag to say whether a context switch is required or * not (i.e. has a task with a higher priority than us been woken by this * post). */ configASSERT( pxQueue ); 801434a: 6bbb ldr r3, [r7, #56] @ 0x38 801434c: 2b00 cmp r3, #0 801434e: d10b bne.n 8014368 __asm volatile 8014350: f04f 0350 mov.w r3, #80 @ 0x50 8014354: f383 8811 msr BASEPRI, r3 8014358: f3bf 8f6f isb sy 801435c: f3bf 8f4f dsb sy 8014360: 627b str r3, [r7, #36] @ 0x24 } 8014362: bf00 nop 8014364: bf00 nop 8014366: e7fd b.n 8014364 /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() * if the item size is not 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 8014368: 6bbb ldr r3, [r7, #56] @ 0x38 801436a: 6c1b ldr r3, [r3, #64] @ 0x40 801436c: 2b00 cmp r3, #0 801436e: d00b beq.n 8014388 __asm volatile 8014370: f04f 0350 mov.w r3, #80 @ 0x50 8014374: f383 8811 msr BASEPRI, r3 8014378: f3bf 8f6f isb sy 801437c: f3bf 8f4f dsb sy 8014380: 623b str r3, [r7, #32] } 8014382: bf00 nop 8014384: bf00 nop 8014386: e7fd b.n 8014384 /* Normally a mutex would not be given from an interrupt, especially if * there is a mutex holder, as priority inheritance makes no sense for an * interrupts, only tasks. */ configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); 8014388: 6bbb ldr r3, [r7, #56] @ 0x38 801438a: 681b ldr r3, [r3, #0] 801438c: 2b00 cmp r3, #0 801438e: d103 bne.n 8014398 8014390: 6bbb ldr r3, [r7, #56] @ 0x38 8014392: 689b ldr r3, [r3, #8] 8014394: 2b00 cmp r3, #0 8014396: d101 bne.n 801439c 8014398: 2301 movs r3, #1 801439a: e000 b.n 801439e 801439c: 2300 movs r3, #0 801439e: 2b00 cmp r3, #0 80143a0: d10b bne.n 80143ba __asm volatile 80143a2: f04f 0350 mov.w r3, #80 @ 0x50 80143a6: f383 8811 msr BASEPRI, r3 80143aa: f3bf 8f6f isb sy 80143ae: f3bf 8f4f dsb sy 80143b2: 61fb str r3, [r7, #28] } 80143b4: bf00 nop 80143b6: bf00 nop 80143b8: e7fd b.n 80143b6 * that have been assigned a priority at or (logically) below the maximum * system call interrupt priority. FreeRTOS maintains a separate interrupt * safe API to ensure interrupt entry is as fast and as simple as possible. * More information (albeit Cortex-M specific) is provided on the following * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 80143ba: f003 f8b7 bl 801752c __asm volatile 80143be: f3ef 8211 mrs r2, BASEPRI 80143c2: f04f 0350 mov.w r3, #80 @ 0x50 80143c6: f383 8811 msr BASEPRI, r3 80143ca: f3bf 8f6f isb sy 80143ce: f3bf 8f4f dsb sy 80143d2: 61ba str r2, [r7, #24] 80143d4: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 80143d6: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80143d8: 637b str r3, [r7, #52] @ 0x34 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80143da: 6bbb ldr r3, [r7, #56] @ 0x38 80143dc: 6b9b ldr r3, [r3, #56] @ 0x38 80143de: 633b str r3, [r7, #48] @ 0x30 /* When the queue is used to implement a semaphore no data is ever * moved through the queue but it is still valid to see if the queue 'has * space'. */ if( uxMessagesWaiting < pxQueue->uxLength ) 80143e0: 6bbb ldr r3, [r7, #56] @ 0x38 80143e2: 6bdb ldr r3, [r3, #60] @ 0x3c 80143e4: 6b3a ldr r2, [r7, #48] @ 0x30 80143e6: 429a cmp r2, r3 80143e8: d243 bcs.n 8014472 { const int8_t cTxLock = pxQueue->cTxLock; 80143ea: 6bbb ldr r3, [r7, #56] @ 0x38 80143ec: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80143f0: f887 302f strb.w r3, [r7, #47] @ 0x2f * holder - and if there is a mutex holder then the mutex cannot be * given from an ISR. As this is the ISR version of the function it * can be assumed there is no mutex holder and no need to determine if * priority disinheritance is needed. Simply increase the count of * messages (semaphores) available. */ pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 80143f4: 6b3b ldr r3, [r7, #48] @ 0x30 80143f6: 1c5a adds r2, r3, #1 80143f8: 6bbb ldr r3, [r7, #56] @ 0x38 80143fa: 639a str r2, [r3, #56] @ 0x38 /* The event list is not altered if the queue is locked. This will * be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80143fc: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 8014400: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014404: d112 bne.n 801442c } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014406: 6bbb ldr r3, [r7, #56] @ 0x38 8014408: 6a5b ldr r3, [r3, #36] @ 0x24 801440a: 2b00 cmp r3, #0 801440c: d02e beq.n 801446c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 801440e: 6bbb ldr r3, [r7, #56] @ 0x38 8014410: 3324 adds r3, #36 @ 0x24 8014412: 4618 mov r0, r3 8014414: f001 fa44 bl 80158a0 8014418: 4603 mov r3, r0 801441a: 2b00 cmp r3, #0 801441c: d026 beq.n 801446c { /* The task waiting has a higher priority so record that a * context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 801441e: 683b ldr r3, [r7, #0] 8014420: 2b00 cmp r3, #0 8014422: d023 beq.n 801446c { *pxHigherPriorityTaskWoken = pdTRUE; 8014424: 683b ldr r3, [r7, #0] 8014426: 2201 movs r2, #1 8014428: 601a str r2, [r3, #0] 801442a: e01f b.n 801446c } else { /* Increment the lock count so the task that unlocks the queue * knows that data was posted while it was locked. */ prvIncrementQueueTxLock( pxQueue, cTxLock ); 801442c: f001 f84a bl 80154c4 8014430: 62b8 str r0, [r7, #40] @ 0x28 8014432: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 8014436: 6aba ldr r2, [r7, #40] @ 0x28 8014438: 429a cmp r2, r3 801443a: d917 bls.n 801446c 801443c: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 8014440: 2b7f cmp r3, #127 @ 0x7f 8014442: d10b bne.n 801445c __asm volatile 8014444: f04f 0350 mov.w r3, #80 @ 0x50 8014448: f383 8811 msr BASEPRI, r3 801444c: f3bf 8f6f isb sy 8014450: f3bf 8f4f dsb sy 8014454: 613b str r3, [r7, #16] } 8014456: bf00 nop 8014458: bf00 nop 801445a: e7fd b.n 8014458 801445c: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8014460: 3301 adds r3, #1 8014462: b2db uxtb r3, r3 8014464: b25a sxtb r2, r3 8014466: 6bbb ldr r3, [r7, #56] @ 0x38 8014468: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 801446c: 2301 movs r3, #1 801446e: 63fb str r3, [r7, #60] @ 0x3c 8014470: e001 b.n 8014476 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 8014472: 2300 movs r3, #0 8014474: 63fb str r3, [r7, #60] @ 0x3c 8014476: 6b7b ldr r3, [r7, #52] @ 0x34 8014478: 60fb str r3, [r7, #12] __asm volatile 801447a: 68fb ldr r3, [r7, #12] 801447c: f383 8811 msr BASEPRI, r3 } 8014480: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8014482: 6bfb ldr r3, [r7, #60] @ 0x3c } 8014484: 4618 mov r0, r3 8014486: 3740 adds r7, #64 @ 0x40 8014488: 46bd mov sp, r7 801448a: bd80 pop {r7, pc} 0801448c : /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 801448c: b580 push {r7, lr} 801448e: b08c sub sp, #48 @ 0x30 8014490: af00 add r7, sp, #0 8014492: 60f8 str r0, [r7, #12] 8014494: 60b9 str r1, [r7, #8] 8014496: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 8014498: 2300 movs r3, #0 801449a: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801449c: 68fb ldr r3, [r7, #12] 801449e: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 80144a0: 6abb ldr r3, [r7, #40] @ 0x28 80144a2: 2b00 cmp r3, #0 80144a4: d10b bne.n 80144be __asm volatile 80144a6: f04f 0350 mov.w r3, #80 @ 0x50 80144aa: f383 8811 msr BASEPRI, r3 80144ae: f3bf 8f6f isb sy 80144b2: f3bf 8f4f dsb sy 80144b6: 623b str r3, [r7, #32] } 80144b8: bf00 nop 80144ba: bf00 nop 80144bc: e7fd b.n 80144ba /* The buffer into which data is received can only be NULL if the data size * is zero (so no data is copied into the buffer). */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 80144be: 68bb ldr r3, [r7, #8] 80144c0: 2b00 cmp r3, #0 80144c2: d103 bne.n 80144cc 80144c4: 6abb ldr r3, [r7, #40] @ 0x28 80144c6: 6c1b ldr r3, [r3, #64] @ 0x40 80144c8: 2b00 cmp r3, #0 80144ca: d101 bne.n 80144d0 80144cc: 2301 movs r3, #1 80144ce: e000 b.n 80144d2 80144d0: 2300 movs r3, #0 80144d2: 2b00 cmp r3, #0 80144d4: d10b bne.n 80144ee __asm volatile 80144d6: f04f 0350 mov.w r3, #80 @ 0x50 80144da: f383 8811 msr BASEPRI, r3 80144de: f3bf 8f6f isb sy 80144e2: f3bf 8f4f dsb sy 80144e6: 61fb str r3, [r7, #28] } 80144e8: bf00 nop 80144ea: bf00 nop 80144ec: e7fd b.n 80144ea /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80144ee: f001 fc1b bl 8015d28 80144f2: 4603 mov r3, r0 80144f4: 2b00 cmp r3, #0 80144f6: d102 bne.n 80144fe 80144f8: 687b ldr r3, [r7, #4] 80144fa: 2b00 cmp r3, #0 80144fc: d101 bne.n 8014502 80144fe: 2301 movs r3, #1 8014500: e000 b.n 8014504 8014502: 2300 movs r3, #0 8014504: 2b00 cmp r3, #0 8014506: d10b bne.n 8014520 __asm volatile 8014508: f04f 0350 mov.w r3, #80 @ 0x50 801450c: f383 8811 msr BASEPRI, r3 8014510: f3bf 8f6f isb sy 8014514: f3bf 8f4f dsb sy 8014518: 61bb str r3, [r7, #24] } 801451a: bf00 nop 801451c: bf00 nop 801451e: e7fd b.n 801451c /*lint -save -e904 This function relaxes the coding standard somewhat to * allow return statements within the function itself. This is done in the * interest of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); 8014520: f002 ff1e bl 8017360 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014524: 6abb ldr r3, [r7, #40] @ 0x28 8014526: 6b9b ldr r3, [r3, #56] @ 0x38 8014528: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task * must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 801452a: 6a7b ldr r3, [r7, #36] @ 0x24 801452c: 2b00 cmp r3, #0 801452e: d01f beq.n 8014570 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 8014530: 68b9 ldr r1, [r7, #8] 8014532: 6ab8 ldr r0, [r7, #40] @ 0x28 8014534: f000 facc bl 8014ad0 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8014538: 6a7b ldr r3, [r7, #36] @ 0x24 801453a: 1e5a subs r2, r3, #1 801453c: 6abb ldr r3, [r7, #40] @ 0x28 801453e: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to * post to the queue? If so, unblock the highest priority waiting * task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014540: 6abb ldr r3, [r7, #40] @ 0x28 8014542: 691b ldr r3, [r3, #16] 8014544: 2b00 cmp r3, #0 8014546: d00f beq.n 8014568 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014548: 6abb ldr r3, [r7, #40] @ 0x28 801454a: 3310 adds r3, #16 801454c: 4618 mov r0, r3 801454e: f001 f9a7 bl 80158a0 8014552: 4603 mov r3, r0 8014554: 2b00 cmp r3, #0 8014556: d007 beq.n 8014568 { queueYIELD_IF_USING_PREEMPTION(); 8014558: 4b3c ldr r3, [pc, #240] @ (801464c ) 801455a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801455e: 601a str r2, [r3, #0] 8014560: f3bf 8f4f dsb sy 8014564: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8014568: f002 ff2c bl 80173c4 return pdPASS; 801456c: 2301 movs r3, #1 801456e: e069 b.n 8014644 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014570: 687b ldr r3, [r7, #4] 8014572: 2b00 cmp r3, #0 8014574: d103 bne.n 801457e { /* The queue was empty and no block time is specified (or * the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014576: f002 ff25 bl 80173c4 traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 801457a: 2300 movs r3, #0 801457c: e062 b.n 8014644 } else if( xEntryTimeSet == pdFALSE ) 801457e: 6afb ldr r3, [r7, #44] @ 0x2c 8014580: 2b00 cmp r3, #0 8014582: d106 bne.n 8014592 { /* The queue was empty and a block time was specified so * configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014584: f107 0310 add.w r3, r7, #16 8014588: 4618 mov r0, r3 801458a: f001 fa61 bl 8015a50 xEntryTimeSet = pdTRUE; 801458e: 2301 movs r3, #1 8014590: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014592: f002 ff17 bl 80173c4 /* Interrupts and other tasks can send to and receive from the queue * now the critical section has been exited. */ vTaskSuspendAll(); 8014596: f000 fe79 bl 801528c prvLockQueue( pxQueue ); 801459a: f002 fee1 bl 8017360 801459e: 6abb ldr r3, [r7, #40] @ 0x28 80145a0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80145a4: b25b sxtb r3, r3 80145a6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80145aa: d103 bne.n 80145b4 80145ac: 6abb ldr r3, [r7, #40] @ 0x28 80145ae: 2200 movs r2, #0 80145b0: f883 2044 strb.w r2, [r3, #68] @ 0x44 80145b4: 6abb ldr r3, [r7, #40] @ 0x28 80145b6: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80145ba: b25b sxtb r3, r3 80145bc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80145c0: d103 bne.n 80145ca 80145c2: 6abb ldr r3, [r7, #40] @ 0x28 80145c4: 2200 movs r2, #0 80145c6: f883 2045 strb.w r2, [r3, #69] @ 0x45 80145ca: f002 fefb bl 80173c4 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 80145ce: 1d3a adds r2, r7, #4 80145d0: f107 0310 add.w r3, r7, #16 80145d4: 4611 mov r1, r2 80145d6: 4618 mov r0, r3 80145d8: f001 fa50 bl 8015a7c 80145dc: 4603 mov r3, r0 80145de: 2b00 cmp r3, #0 80145e0: d123 bne.n 801462a { /* The timeout has not expired. If the queue is still empty place * the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80145e2: 6ab8 ldr r0, [r7, #40] @ 0x28 80145e4: f000 faec bl 8014bc0 80145e8: 4603 mov r3, r0 80145ea: 2b00 cmp r3, #0 80145ec: d017 beq.n 801461e { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 80145ee: 6abb ldr r3, [r7, #40] @ 0x28 80145f0: 3324 adds r3, #36 @ 0x24 80145f2: 687a ldr r2, [r7, #4] 80145f4: 4611 mov r1, r2 80145f6: 4618 mov r0, r3 80145f8: f001 f8e6 bl 80157c8 prvUnlockQueue( pxQueue ); 80145fc: 6ab8 ldr r0, [r7, #40] @ 0x28 80145fe: f000 fa8d bl 8014b1c if( xTaskResumeAll() == pdFALSE ) 8014602: f000 fe51 bl 80152a8 8014606: 4603 mov r3, r0 8014608: 2b00 cmp r3, #0 801460a: d189 bne.n 8014520 { portYIELD_WITHIN_API(); 801460c: 4b0f ldr r3, [pc, #60] @ (801464c ) 801460e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014612: 601a str r2, [r3, #0] 8014614: f3bf 8f4f dsb sy 8014618: f3bf 8f6f isb sy 801461c: e780 b.n 8014520 } else { /* The queue contains data again. Loop back to try and read the * data. */ prvUnlockQueue( pxQueue ); 801461e: 6ab8 ldr r0, [r7, #40] @ 0x28 8014620: f000 fa7c bl 8014b1c ( void ) xTaskResumeAll(); 8014624: f000 fe40 bl 80152a8 8014628: e77a b.n 8014520 } else { /* Timed out. If there is no data in the queue exit, otherwise loop * back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 801462a: 6ab8 ldr r0, [r7, #40] @ 0x28 801462c: f000 fa76 bl 8014b1c ( void ) xTaskResumeAll(); 8014630: f000 fe3a bl 80152a8 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014634: 6ab8 ldr r0, [r7, #40] @ 0x28 8014636: f000 fac3 bl 8014bc0 801463a: 4603 mov r3, r0 801463c: 2b00 cmp r3, #0 801463e: f43f af6f beq.w 8014520 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014642: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8014644: 4618 mov r0, r3 8014646: 3730 adds r7, #48 @ 0x30 8014648: 46bd mov sp, r7 801464a: bd80 pop {r7, pc} 801464c: e000ed04 .word 0xe000ed04 08014650 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 8014650: b580 push {r7, lr} 8014652: b08c sub sp, #48 @ 0x30 8014654: af00 add r7, sp, #0 8014656: 6078 str r0, [r7, #4] 8014658: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 801465a: 2300 movs r3, #0 801465c: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801465e: 687b ldr r3, [r7, #4] 8014660: 627b str r3, [r7, #36] @ 0x24 #if ( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 8014662: 2300 movs r3, #0 8014664: 62bb str r3, [r7, #40] @ 0x28 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8014666: 6a7b ldr r3, [r7, #36] @ 0x24 8014668: 2b00 cmp r3, #0 801466a: d10b bne.n 8014684 __asm volatile 801466c: f04f 0350 mov.w r3, #80 @ 0x50 8014670: f383 8811 msr BASEPRI, r3 8014674: f3bf 8f6f isb sy 8014678: f3bf 8f4f dsb sy 801467c: 61bb str r3, [r7, #24] } 801467e: bf00 nop 8014680: bf00 nop 8014682: e7fd b.n 8014680 /* Check this really is a semaphore, in which case the item size will be * 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 8014684: 6a7b ldr r3, [r7, #36] @ 0x24 8014686: 6c1b ldr r3, [r3, #64] @ 0x40 8014688: 2b00 cmp r3, #0 801468a: d00b beq.n 80146a4 __asm volatile 801468c: f04f 0350 mov.w r3, #80 @ 0x50 8014690: f383 8811 msr BASEPRI, r3 8014694: f3bf 8f6f isb sy 8014698: f3bf 8f4f dsb sy 801469c: 617b str r3, [r7, #20] } 801469e: bf00 nop 80146a0: bf00 nop 80146a2: e7fd b.n 80146a0 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80146a4: f001 fb40 bl 8015d28 80146a8: 4603 mov r3, r0 80146aa: 2b00 cmp r3, #0 80146ac: d102 bne.n 80146b4 80146ae: 683b ldr r3, [r7, #0] 80146b0: 2b00 cmp r3, #0 80146b2: d101 bne.n 80146b8 80146b4: 2301 movs r3, #1 80146b6: e000 b.n 80146ba 80146b8: 2300 movs r3, #0 80146ba: 2b00 cmp r3, #0 80146bc: d10b bne.n 80146d6 __asm volatile 80146be: f04f 0350 mov.w r3, #80 @ 0x50 80146c2: f383 8811 msr BASEPRI, r3 80146c6: f3bf 8f6f isb sy 80146ca: f3bf 8f4f dsb sy 80146ce: 613b str r3, [r7, #16] } 80146d0: bf00 nop 80146d2: bf00 nop 80146d4: e7fd b.n 80146d2 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return * statements within the function itself. This is done in the interest * of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); 80146d6: f002 fe43 bl 8017360 { /* Semaphores are queues with an item size of 0, and where the * number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 80146da: 6a7b ldr r3, [r7, #36] @ 0x24 80146dc: 6b9b ldr r3, [r3, #56] @ 0x38 80146de: 623b str r3, [r7, #32] /* Is there data in the queue now? To be running the calling task * must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 80146e0: 6a3b ldr r3, [r7, #32] 80146e2: 2b00 cmp r3, #0 80146e4: d024 beq.n 8014730 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the * messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 80146e6: 6a3b ldr r3, [r7, #32] 80146e8: 1e5a subs r2, r3, #1 80146ea: 6a7b ldr r3, [r7, #36] @ 0x24 80146ec: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80146ee: 6a7b ldr r3, [r7, #36] @ 0x24 80146f0: 681b ldr r3, [r3, #0] 80146f2: 2b00 cmp r3, #0 80146f4: d104 bne.n 8014700 { /* Record the information required to implement * priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 80146f6: f001 fd09 bl 801610c 80146fa: 4602 mov r2, r0 80146fc: 6a7b ldr r3, [r7, #36] @ 0x24 80146fe: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the * semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014700: 6a7b ldr r3, [r7, #36] @ 0x24 8014702: 691b ldr r3, [r3, #16] 8014704: 2b00 cmp r3, #0 8014706: d00f beq.n 8014728 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014708: 6a7b ldr r3, [r7, #36] @ 0x24 801470a: 3310 adds r3, #16 801470c: 4618 mov r0, r3 801470e: f001 f8c7 bl 80158a0 8014712: 4603 mov r3, r0 8014714: 2b00 cmp r3, #0 8014716: d007 beq.n 8014728 { queueYIELD_IF_USING_PREEMPTION(); 8014718: 4b4c ldr r3, [pc, #304] @ (801484c ) 801471a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801471e: 601a str r2, [r3, #0] 8014720: f3bf 8f4f dsb sy 8014724: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8014728: f002 fe4c bl 80173c4 return pdPASS; 801472c: 2301 movs r3, #1 801472e: e089 b.n 8014844 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014730: 683b ldr r3, [r7, #0] 8014732: 2b00 cmp r3, #0 8014734: d103 bne.n 801473e { /* The semaphore count was 0 and no block time is specified * (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 8014736: f002 fe45 bl 80173c4 traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 801473a: 2300 movs r3, #0 801473c: e082 b.n 8014844 } else if( xEntryTimeSet == pdFALSE ) 801473e: 6afb ldr r3, [r7, #44] @ 0x2c 8014740: 2b00 cmp r3, #0 8014742: d106 bne.n 8014752 { /* The semaphore count was 0 and a block time was specified * so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014744: f107 0308 add.w r3, r7, #8 8014748: 4618 mov r0, r3 801474a: f001 f981 bl 8015a50 xEntryTimeSet = pdTRUE; 801474e: 2301 movs r3, #1 8014750: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014752: f002 fe37 bl 80173c4 /* Interrupts and other tasks can give to and take from the semaphore * now the critical section has been exited. */ vTaskSuspendAll(); 8014756: f000 fd99 bl 801528c prvLockQueue( pxQueue ); 801475a: f002 fe01 bl 8017360 801475e: 6a7b ldr r3, [r7, #36] @ 0x24 8014760: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014764: b25b sxtb r3, r3 8014766: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801476a: d103 bne.n 8014774 801476c: 6a7b ldr r3, [r7, #36] @ 0x24 801476e: 2200 movs r2, #0 8014770: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014774: 6a7b ldr r3, [r7, #36] @ 0x24 8014776: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801477a: b25b sxtb r3, r3 801477c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014780: d103 bne.n 801478a 8014782: 6a7b ldr r3, [r7, #36] @ 0x24 8014784: 2200 movs r2, #0 8014786: f883 2045 strb.w r2, [r3, #69] @ 0x45 801478a: f002 fe1b bl 80173c4 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 801478e: 463a mov r2, r7 8014790: f107 0308 add.w r3, r7, #8 8014794: 4611 mov r1, r2 8014796: 4618 mov r0, r3 8014798: f001 f970 bl 8015a7c 801479c: 4603 mov r3, r0 801479e: 2b00 cmp r3, #0 80147a0: d132 bne.n 8014808 { /* A block time is specified and not expired. If the semaphore * count is 0 then enter the Blocked state to wait for a semaphore to * become available. As semaphores are implemented with queues the * queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80147a2: 6a78 ldr r0, [r7, #36] @ 0x24 80147a4: f000 fa0c bl 8014bc0 80147a8: 4603 mov r3, r0 80147aa: 2b00 cmp r3, #0 80147ac: d026 beq.n 80147fc { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80147ae: 6a7b ldr r3, [r7, #36] @ 0x24 80147b0: 681b ldr r3, [r3, #0] 80147b2: 2b00 cmp r3, #0 80147b4: d109 bne.n 80147ca { taskENTER_CRITICAL(); 80147b6: f002 fdd3 bl 8017360 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 80147ba: 6a7b ldr r3, [r7, #36] @ 0x24 80147bc: 689b ldr r3, [r3, #8] 80147be: 4618 mov r0, r3 80147c0: f001 fad0 bl 8015d64 80147c4: 62b8 str r0, [r7, #40] @ 0x28 } taskEXIT_CRITICAL(); 80147c6: f002 fdfd bl 80173c4 mtCOVERAGE_TEST_MARKER(); } } #endif /* if ( configUSE_MUTEXES == 1 ) */ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 80147ca: 6a7b ldr r3, [r7, #36] @ 0x24 80147cc: 3324 adds r3, #36 @ 0x24 80147ce: 683a ldr r2, [r7, #0] 80147d0: 4611 mov r1, r2 80147d2: 4618 mov r0, r3 80147d4: f000 fff8 bl 80157c8 prvUnlockQueue( pxQueue ); 80147d8: 6a78 ldr r0, [r7, #36] @ 0x24 80147da: f000 f99f bl 8014b1c if( xTaskResumeAll() == pdFALSE ) 80147de: f000 fd63 bl 80152a8 80147e2: 4603 mov r3, r0 80147e4: 2b00 cmp r3, #0 80147e6: f47f af76 bne.w 80146d6 { portYIELD_WITHIN_API(); 80147ea: 4b18 ldr r3, [pc, #96] @ (801484c ) 80147ec: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80147f0: 601a str r2, [r3, #0] 80147f2: f3bf 8f4f dsb sy 80147f6: f3bf 8f6f isb sy 80147fa: e76c b.n 80146d6 } else { /* There was no timeout and the semaphore count was not 0, so * attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 80147fc: 6a78 ldr r0, [r7, #36] @ 0x24 80147fe: f000 f98d bl 8014b1c ( void ) xTaskResumeAll(); 8014802: f000 fd51 bl 80152a8 8014806: e766 b.n 80146d6 } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 8014808: 6a78 ldr r0, [r7, #36] @ 0x24 801480a: f000 f987 bl 8014b1c ( void ) xTaskResumeAll(); 801480e: f000 fd4b bl 80152a8 /* If the semaphore count is 0 exit now as the timeout has * expired. Otherwise return to attempt to take the semaphore that is * known to be available. As semaphores are implemented by queues the * queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014812: 6a78 ldr r0, [r7, #36] @ 0x24 8014814: f000 f9d4 bl 8014bc0 8014818: 4603 mov r3, r0 801481a: 2b00 cmp r3, #0 801481c: f43f af5b beq.w 80146d6 #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to * test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 8014820: 6abb ldr r3, [r7, #40] @ 0x28 8014822: 2b00 cmp r3, #0 8014824: d00d beq.n 8014842 { taskENTER_CRITICAL(); 8014826: f002 fd9b bl 8017360 /* This task blocking on the mutex caused another * task to inherit this task's priority. Now this task * has timed out the priority should be disinherited * again, but only as low as the next highest priority * task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 801482a: 6a78 ldr r0, [r7, #36] @ 0x24 801482c: f000 f8ce bl 80149cc 8014830: 61f8 str r0, [r7, #28] vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 8014832: 6a7b ldr r3, [r7, #36] @ 0x24 8014834: 689b ldr r3, [r3, #8] 8014836: 69f9 ldr r1, [r7, #28] 8014838: 4618 mov r0, r3 801483a: f001 fbbb bl 8015fb4 } taskEXIT_CRITICAL(); 801483e: f002 fdc1 bl 80173c4 } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014842: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8014844: 4618 mov r0, r3 8014846: 3730 adds r7, #48 @ 0x30 8014848: 46bd mov sp, r7 801484a: bd80 pop {r7, pc} 801484c: e000ed04 .word 0xe000ed04 08014850 : /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 8014850: b580 push {r7, lr} 8014852: b090 sub sp, #64 @ 0x40 8014854: af00 add r7, sp, #0 8014856: 60f8 str r0, [r7, #12] 8014858: 60b9 str r1, [r7, #8] 801485a: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 801485c: 68fb ldr r3, [r7, #12] 801485e: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 8014860: 6bbb ldr r3, [r7, #56] @ 0x38 8014862: 2b00 cmp r3, #0 8014864: d10b bne.n 801487e __asm volatile 8014866: f04f 0350 mov.w r3, #80 @ 0x50 801486a: f383 8811 msr BASEPRI, r3 801486e: f3bf 8f6f isb sy 8014872: f3bf 8f4f dsb sy 8014876: 627b str r3, [r7, #36] @ 0x24 } 8014878: bf00 nop 801487a: bf00 nop 801487c: e7fd b.n 801487a configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 801487e: 68bb ldr r3, [r7, #8] 8014880: 2b00 cmp r3, #0 8014882: d103 bne.n 801488c 8014884: 6bbb ldr r3, [r7, #56] @ 0x38 8014886: 6c1b ldr r3, [r3, #64] @ 0x40 8014888: 2b00 cmp r3, #0 801488a: d101 bne.n 8014890 801488c: 2301 movs r3, #1 801488e: e000 b.n 8014892 8014890: 2300 movs r3, #0 8014892: 2b00 cmp r3, #0 8014894: d10b bne.n 80148ae __asm volatile 8014896: f04f 0350 mov.w r3, #80 @ 0x50 801489a: f383 8811 msr BASEPRI, r3 801489e: f3bf 8f6f isb sy 80148a2: f3bf 8f4f dsb sy 80148a6: 623b str r3, [r7, #32] } 80148a8: bf00 nop 80148aa: bf00 nop 80148ac: e7fd b.n 80148aa * that have been assigned a priority at or (logically) below the maximum * system call interrupt priority. FreeRTOS maintains a separate interrupt * safe API to ensure interrupt entry is as fast and as simple as possible. * More information (albeit Cortex-M specific) is provided on the following * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 80148ae: f002 fe3d bl 801752c __asm volatile 80148b2: f3ef 8211 mrs r2, BASEPRI 80148b6: f04f 0350 mov.w r3, #80 @ 0x50 80148ba: f383 8811 msr BASEPRI, r3 80148be: f3bf 8f6f isb sy 80148c2: f3bf 8f4f dsb sy 80148c6: 61fa str r2, [r7, #28] 80148c8: 61bb str r3, [r7, #24] return ulOriginalBASEPRI; 80148ca: 69fb ldr r3, [r7, #28] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80148cc: 637b str r3, [r7, #52] @ 0x34 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80148ce: 6bbb ldr r3, [r7, #56] @ 0x38 80148d0: 6b9b ldr r3, [r3, #56] @ 0x38 80148d2: 633b str r3, [r7, #48] @ 0x30 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80148d4: 6b3b ldr r3, [r7, #48] @ 0x30 80148d6: 2b00 cmp r3, #0 80148d8: d047 beq.n 801496a { const int8_t cRxLock = pxQueue->cRxLock; 80148da: 6bbb ldr r3, [r7, #56] @ 0x38 80148dc: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80148e0: f887 302f strb.w r3, [r7, #47] @ 0x2f traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 80148e4: 68b9 ldr r1, [r7, #8] 80148e6: 6bb8 ldr r0, [r7, #56] @ 0x38 80148e8: f000 f8f2 bl 8014ad0 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80148ec: 6b3b ldr r3, [r7, #48] @ 0x30 80148ee: 1e5a subs r2, r3, #1 80148f0: 6bbb ldr r3, [r7, #56] @ 0x38 80148f2: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. * Instead update the lock count so the task that unlocks the queue * will know that an ISR has removed data while the queue was * locked. */ if( cRxLock == queueUNLOCKED ) 80148f4: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 80148f8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80148fc: d112 bne.n 8014924 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80148fe: 6bbb ldr r3, [r7, #56] @ 0x38 8014900: 691b ldr r3, [r3, #16] 8014902: 2b00 cmp r3, #0 8014904: d02e beq.n 8014964 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014906: 6bbb ldr r3, [r7, #56] @ 0x38 8014908: 3310 adds r3, #16 801490a: 4618 mov r0, r3 801490c: f000 ffc8 bl 80158a0 8014910: 4603 mov r3, r0 8014912: 2b00 cmp r3, #0 8014914: d026 beq.n 8014964 { /* The task waiting has a higher priority than us so * force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 8014916: 687b ldr r3, [r7, #4] 8014918: 2b00 cmp r3, #0 801491a: d023 beq.n 8014964 { *pxHigherPriorityTaskWoken = pdTRUE; 801491c: 687b ldr r3, [r7, #4] 801491e: 2201 movs r2, #1 8014920: 601a str r2, [r3, #0] 8014922: e01f b.n 8014964 } else { /* Increment the lock count so the task that unlocks the queue * knows that data was removed while it was locked. */ prvIncrementQueueRxLock( pxQueue, cRxLock ); 8014924: f000 fdce bl 80154c4 8014928: 62b8 str r0, [r7, #40] @ 0x28 801492a: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 801492e: 6aba ldr r2, [r7, #40] @ 0x28 8014930: 429a cmp r2, r3 8014932: d917 bls.n 8014964 8014934: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 8014938: 2b7f cmp r3, #127 @ 0x7f 801493a: d10b bne.n 8014954 __asm volatile 801493c: f04f 0350 mov.w r3, #80 @ 0x50 8014940: f383 8811 msr BASEPRI, r3 8014944: f3bf 8f6f isb sy 8014948: f3bf 8f4f dsb sy 801494c: 617b str r3, [r7, #20] } 801494e: bf00 nop 8014950: bf00 nop 8014952: e7fd b.n 8014950 8014954: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8014958: 3301 adds r3, #1 801495a: b2db uxtb r3, r3 801495c: b25a sxtb r2, r3 801495e: 6bbb ldr r3, [r7, #56] @ 0x38 8014960: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 8014964: 2301 movs r3, #1 8014966: 63fb str r3, [r7, #60] @ 0x3c 8014968: e001 b.n 801496e } else { xReturn = pdFAIL; 801496a: 2300 movs r3, #0 801496c: 63fb str r3, [r7, #60] @ 0x3c 801496e: 6b7b ldr r3, [r7, #52] @ 0x34 8014970: 613b str r3, [r7, #16] __asm volatile 8014972: 693b ldr r3, [r7, #16] 8014974: f383 8811 msr BASEPRI, r3 } 8014978: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801497a: 6bfb ldr r3, [r7, #60] @ 0x3c } 801497c: 4618 mov r0, r3 801497e: 3740 adds r7, #64 @ 0x40 8014980: 46bd mov sp, r7 8014982: bd80 pop {r7, pc} 08014984 : return uxReturn; } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ /*-----------------------------------------------------------*/ void vQueueDelete( QueueHandle_t xQueue ) { 8014984: b580 push {r7, lr} 8014986: b084 sub sp, #16 8014988: af00 add r7, sp, #0 801498a: 6078 str r0, [r7, #4] Queue_t * const pxQueue = xQueue; 801498c: 687b ldr r3, [r7, #4] 801498e: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 8014990: 68fb ldr r3, [r7, #12] 8014992: 2b00 cmp r3, #0 8014994: d10b bne.n 80149ae __asm volatile 8014996: f04f 0350 mov.w r3, #80 @ 0x50 801499a: f383 8811 msr BASEPRI, r3 801499e: f3bf 8f6f isb sy 80149a2: f3bf 8f4f dsb sy 80149a6: 60bb str r3, [r7, #8] } 80149a8: bf00 nop 80149aa: bf00 nop 80149ac: e7fd b.n 80149aa traceQUEUE_DELETE( pxQueue ); #if ( configQUEUE_REGISTRY_SIZE > 0 ) { vQueueUnregisterQueue( pxQueue ); 80149ae: 68f8 ldr r0, [r7, #12] 80149b0: f000 f984 bl 8014cbc } #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) { /* The queue could have been allocated statically or dynamically, so * check before attempting to free the memory. */ if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) 80149b4: 68fb ldr r3, [r7, #12] 80149b6: f893 3046 ldrb.w r3, [r3, #70] @ 0x46 80149ba: 2b00 cmp r3, #0 80149bc: d102 bne.n 80149c4 { vPortFree( pxQueue ); 80149be: 68f8 ldr r0, [r7, #12] 80149c0: f002 fec2 bl 8017748 /* The queue must have been statically allocated, so is not going to be * deleted. Avoid compiler warnings about the unused parameter. */ ( void ) pxQueue; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 80149c4: bf00 nop 80149c6: 3710 adds r7, #16 80149c8: 46bd mov sp, r7 80149ca: bd80 pop {r7, pc} 080149cc : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 80149cc: b480 push {r7} 80149ce: b085 sub sp, #20 80149d0: af00 add r7, sp, #0 80149d2: 6078 str r0, [r7, #4] * priority, but the waiting task times out, then the holder should * disinherit the priority - but only down to the highest priority of any * other tasks that are waiting for the same mutex. For this purpose, * return the priority of the highest priority task that is waiting for the * mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 80149d4: 687b ldr r3, [r7, #4] 80149d6: 6a5b ldr r3, [r3, #36] @ 0x24 80149d8: 2b00 cmp r3, #0 80149da: d006 beq.n 80149ea { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 80149dc: 687b ldr r3, [r7, #4] 80149de: 6b1b ldr r3, [r3, #48] @ 0x30 80149e0: 681b ldr r3, [r3, #0] 80149e2: f1c3 0338 rsb r3, r3, #56 @ 0x38 80149e6: 60fb str r3, [r7, #12] 80149e8: e001 b.n 80149ee } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 80149ea: 2300 movs r3, #0 80149ec: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 80149ee: 68fb ldr r3, [r7, #12] } 80149f0: 4618 mov r0, r3 80149f2: 3714 adds r7, #20 80149f4: 46bd mov sp, r7 80149f6: f85d 7b04 ldr.w r7, [sp], #4 80149fa: 4770 bx lr 080149fc : /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void * pvItemToQueue, const BaseType_t xPosition ) { 80149fc: b580 push {r7, lr} 80149fe: b086 sub sp, #24 8014a00: af00 add r7, sp, #0 8014a02: 60f8 str r0, [r7, #12] 8014a04: 60b9 str r1, [r7, #8] 8014a06: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8014a08: 2300 movs r3, #0 8014a0a: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014a0c: 68fb ldr r3, [r7, #12] 8014a0e: 6b9b ldr r3, [r3, #56] @ 0x38 8014a10: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 8014a12: 68fb ldr r3, [r7, #12] 8014a14: 6c1b ldr r3, [r3, #64] @ 0x40 8014a16: 2b00 cmp r3, #0 8014a18: d10d bne.n 8014a36 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8014a1a: 68fb ldr r3, [r7, #12] 8014a1c: 681b ldr r3, [r3, #0] 8014a1e: 2b00 cmp r3, #0 8014a20: d14d bne.n 8014abe { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 8014a22: 68fb ldr r3, [r7, #12] 8014a24: 689b ldr r3, [r3, #8] 8014a26: 4618 mov r0, r3 8014a28: f001 fa2c bl 8015e84 8014a2c: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 8014a2e: 68fb ldr r3, [r7, #12] 8014a30: 2200 movs r2, #0 8014a32: 609a str r2, [r3, #8] 8014a34: e043 b.n 8014abe mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8014a36: 687b ldr r3, [r7, #4] 8014a38: 2b00 cmp r3, #0 8014a3a: d119 bne.n 8014a70 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8014a3c: 68fb ldr r3, [r7, #12] 8014a3e: 6858 ldr r0, [r3, #4] 8014a40: 68fb ldr r3, [r7, #12] 8014a42: 6c1b ldr r3, [r3, #64] @ 0x40 8014a44: 461a mov r2, r3 8014a46: 68b9 ldr r1, [r7, #8] 8014a48: f005 f8e3 bl 8019c12 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8014a4c: 68fb ldr r3, [r7, #12] 8014a4e: 685a ldr r2, [r3, #4] 8014a50: 68fb ldr r3, [r7, #12] 8014a52: 6c1b ldr r3, [r3, #64] @ 0x40 8014a54: 441a add r2, r3 8014a56: 68fb ldr r3, [r7, #12] 8014a58: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8014a5a: 68fb ldr r3, [r7, #12] 8014a5c: 685a ldr r2, [r3, #4] 8014a5e: 68fb ldr r3, [r7, #12] 8014a60: 689b ldr r3, [r3, #8] 8014a62: 429a cmp r2, r3 8014a64: d32b bcc.n 8014abe { pxQueue->pcWriteTo = pxQueue->pcHead; 8014a66: 68fb ldr r3, [r7, #12] 8014a68: 681a ldr r2, [r3, #0] 8014a6a: 68fb ldr r3, [r7, #12] 8014a6c: 605a str r2, [r3, #4] 8014a6e: e026 b.n 8014abe mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 8014a70: 68fb ldr r3, [r7, #12] 8014a72: 68d8 ldr r0, [r3, #12] 8014a74: 68fb ldr r3, [r7, #12] 8014a76: 6c1b ldr r3, [r3, #64] @ 0x40 8014a78: 461a mov r2, r3 8014a7a: 68b9 ldr r1, [r7, #8] 8014a7c: f005 f8c9 bl 8019c12 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 8014a80: 68fb ldr r3, [r7, #12] 8014a82: 68da ldr r2, [r3, #12] 8014a84: 68fb ldr r3, [r7, #12] 8014a86: 6c1b ldr r3, [r3, #64] @ 0x40 8014a88: 425b negs r3, r3 8014a8a: 441a add r2, r3 8014a8c: 68fb ldr r3, [r7, #12] 8014a8e: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8014a90: 68fb ldr r3, [r7, #12] 8014a92: 68da ldr r2, [r3, #12] 8014a94: 68fb ldr r3, [r7, #12] 8014a96: 681b ldr r3, [r3, #0] 8014a98: 429a cmp r2, r3 8014a9a: d207 bcs.n 8014aac { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 8014a9c: 68fb ldr r3, [r7, #12] 8014a9e: 689a ldr r2, [r3, #8] 8014aa0: 68fb ldr r3, [r7, #12] 8014aa2: 6c1b ldr r3, [r3, #64] @ 0x40 8014aa4: 425b negs r3, r3 8014aa6: 441a add r2, r3 8014aa8: 68fb ldr r3, [r7, #12] 8014aaa: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8014aac: 687b ldr r3, [r7, #4] 8014aae: 2b02 cmp r3, #2 8014ab0: d105 bne.n 8014abe { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014ab2: 693b ldr r3, [r7, #16] 8014ab4: 2b00 cmp r3, #0 8014ab6: d002 beq.n 8014abe { /* An item is not being added but overwritten, so subtract * one from the recorded number of items in the queue so when * one is added again below the number of recorded items remains * correct. */ --uxMessagesWaiting; 8014ab8: 693b ldr r3, [r7, #16] 8014aba: 3b01 subs r3, #1 8014abc: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8014abe: 693b ldr r3, [r7, #16] 8014ac0: 1c5a adds r2, r3, #1 8014ac2: 68fb ldr r3, [r7, #12] 8014ac4: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8014ac6: 697b ldr r3, [r7, #20] } 8014ac8: 4618 mov r0, r3 8014aca: 3718 adds r7, #24 8014acc: 46bd mov sp, r7 8014ace: bd80 pop {r7, pc} 08014ad0 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8014ad0: b580 push {r7, lr} 8014ad2: b082 sub sp, #8 8014ad4: af00 add r7, sp, #0 8014ad6: 6078 str r0, [r7, #4] 8014ad8: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 8014ada: 687b ldr r3, [r7, #4] 8014adc: 6c1b ldr r3, [r3, #64] @ 0x40 8014ade: 2b00 cmp r3, #0 8014ae0: d018 beq.n 8014b14 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8014ae2: 687b ldr r3, [r7, #4] 8014ae4: 68da ldr r2, [r3, #12] 8014ae6: 687b ldr r3, [r7, #4] 8014ae8: 6c1b ldr r3, [r3, #64] @ 0x40 8014aea: 441a add r2, r3 8014aec: 687b ldr r3, [r7, #4] 8014aee: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8014af0: 687b ldr r3, [r7, #4] 8014af2: 68da ldr r2, [r3, #12] 8014af4: 687b ldr r3, [r7, #4] 8014af6: 689b ldr r3, [r3, #8] 8014af8: 429a cmp r2, r3 8014afa: d303 bcc.n 8014b04 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 8014afc: 687b ldr r3, [r7, #4] 8014afe: 681a ldr r2, [r3, #0] 8014b00: 687b ldr r3, [r7, #4] 8014b02: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8014b04: 687b ldr r3, [r7, #4] 8014b06: 68d9 ldr r1, [r3, #12] 8014b08: 687b ldr r3, [r7, #4] 8014b0a: 6c1b ldr r3, [r3, #64] @ 0x40 8014b0c: 461a mov r2, r3 8014b0e: 6838 ldr r0, [r7, #0] 8014b10: f005 f87f bl 8019c12 } } 8014b14: bf00 nop 8014b16: 3708 adds r7, #8 8014b18: 46bd mov sp, r7 8014b1a: bd80 pop {r7, pc} 08014b1c : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 8014b1c: b580 push {r7, lr} 8014b1e: b084 sub sp, #16 8014b20: af00 add r7, sp, #0 8014b22: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or * removed from the queue while the queue was locked. When a queue is * locked items can be added or removed, but the event lists cannot be * updated. */ taskENTER_CRITICAL(); 8014b24: f002 fc1c bl 8017360 { int8_t cTxLock = pxQueue->cTxLock; 8014b28: 687b ldr r3, [r7, #4] 8014b2a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014b2e: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8014b30: e011 b.n 8014b56 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to * the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014b32: 687b ldr r3, [r7, #4] 8014b34: 6a5b ldr r3, [r3, #36] @ 0x24 8014b36: 2b00 cmp r3, #0 8014b38: d012 beq.n 8014b60 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014b3a: 687b ldr r3, [r7, #4] 8014b3c: 3324 adds r3, #36 @ 0x24 8014b3e: 4618 mov r0, r3 8014b40: f000 feae bl 80158a0 8014b44: 4603 mov r3, r0 8014b46: 2b00 cmp r3, #0 8014b48: d001 beq.n 8014b4e { /* The task waiting has a higher priority so record that * a context switch is required. */ vTaskMissedYield(); 8014b4a: f000 ffff bl 8015b4c break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 8014b4e: 7bfb ldrb r3, [r7, #15] 8014b50: 3b01 subs r3, #1 8014b52: b2db uxtb r3, r3 8014b54: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8014b56: f997 300f ldrsb.w r3, [r7, #15] 8014b5a: 2b00 cmp r3, #0 8014b5c: dce9 bgt.n 8014b32 8014b5e: e000 b.n 8014b62 break; 8014b60: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 8014b62: 687b ldr r3, [r7, #4] 8014b64: 22ff movs r2, #255 @ 0xff 8014b66: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 8014b6a: f002 fc2b bl 80173c4 /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 8014b6e: f002 fbf7 bl 8017360 { int8_t cRxLock = pxQueue->cRxLock; 8014b72: 687b ldr r3, [r7, #4] 8014b74: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014b78: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8014b7a: e011 b.n 8014ba0 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014b7c: 687b ldr r3, [r7, #4] 8014b7e: 691b ldr r3, [r3, #16] 8014b80: 2b00 cmp r3, #0 8014b82: d012 beq.n 8014baa { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014b84: 687b ldr r3, [r7, #4] 8014b86: 3310 adds r3, #16 8014b88: 4618 mov r0, r3 8014b8a: f000 fe89 bl 80158a0 8014b8e: 4603 mov r3, r0 8014b90: 2b00 cmp r3, #0 8014b92: d001 beq.n 8014b98 { vTaskMissedYield(); 8014b94: f000 ffda bl 8015b4c else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 8014b98: 7bbb ldrb r3, [r7, #14] 8014b9a: 3b01 subs r3, #1 8014b9c: b2db uxtb r3, r3 8014b9e: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8014ba0: f997 300e ldrsb.w r3, [r7, #14] 8014ba4: 2b00 cmp r3, #0 8014ba6: dce9 bgt.n 8014b7c 8014ba8: e000 b.n 8014bac } else { break; 8014baa: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8014bac: 687b ldr r3, [r7, #4] 8014bae: 22ff movs r2, #255 @ 0xff 8014bb0: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 8014bb4: f002 fc06 bl 80173c4 } 8014bb8: bf00 nop 8014bba: 3710 adds r7, #16 8014bbc: 46bd mov sp, r7 8014bbe: bd80 pop {r7, pc} 08014bc0 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) { 8014bc0: b580 push {r7, lr} 8014bc2: b084 sub sp, #16 8014bc4: af00 add r7, sp, #0 8014bc6: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8014bc8: f002 fbca bl 8017360 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 8014bcc: 687b ldr r3, [r7, #4] 8014bce: 6b9b ldr r3, [r3, #56] @ 0x38 8014bd0: 2b00 cmp r3, #0 8014bd2: d102 bne.n 8014bda { xReturn = pdTRUE; 8014bd4: 2301 movs r3, #1 8014bd6: 60fb str r3, [r7, #12] 8014bd8: e001 b.n 8014bde } else { xReturn = pdFALSE; 8014bda: 2300 movs r3, #0 8014bdc: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8014bde: f002 fbf1 bl 80173c4 return xReturn; 8014be2: 68fb ldr r3, [r7, #12] } 8014be4: 4618 mov r0, r3 8014be6: 3710 adds r7, #16 8014be8: 46bd mov sp, r7 8014bea: bd80 pop {r7, pc} 08014bec : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) { 8014bec: b580 push {r7, lr} 8014bee: b084 sub sp, #16 8014bf0: af00 add r7, sp, #0 8014bf2: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8014bf4: f002 fbb4 bl 8017360 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8014bf8: 687b ldr r3, [r7, #4] 8014bfa: 6b9a ldr r2, [r3, #56] @ 0x38 8014bfc: 687b ldr r3, [r7, #4] 8014bfe: 6bdb ldr r3, [r3, #60] @ 0x3c 8014c00: 429a cmp r2, r3 8014c02: d102 bne.n 8014c0a { xReturn = pdTRUE; 8014c04: 2301 movs r3, #1 8014c06: 60fb str r3, [r7, #12] 8014c08: e001 b.n 8014c0e } else { xReturn = pdFALSE; 8014c0a: 2300 movs r3, #0 8014c0c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8014c0e: f002 fbd9 bl 80173c4 return xReturn; 8014c12: 68fb ldr r3, [r7, #12] } 8014c14: 4618 mov r0, r3 8014c16: 3710 adds r7, #16 8014c18: 46bd mov sp, r7 8014c1a: bd80 pop {r7, pc} 08014c1c : #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 8014c1c: b480 push {r7} 8014c1e: b087 sub sp, #28 8014c20: af00 add r7, sp, #0 8014c22: 6078 str r0, [r7, #4] 8014c24: 6039 str r1, [r7, #0] UBaseType_t ux; QueueRegistryItem_t * pxEntryToWrite = NULL; 8014c26: 2300 movs r3, #0 8014c28: 613b str r3, [r7, #16] configASSERT( xQueue ); 8014c2a: 687b ldr r3, [r7, #4] 8014c2c: 2b00 cmp r3, #0 8014c2e: d10b bne.n 8014c48 __asm volatile 8014c30: f04f 0350 mov.w r3, #80 @ 0x50 8014c34: f383 8811 msr BASEPRI, r3 8014c38: f3bf 8f6f isb sy 8014c3c: f3bf 8f4f dsb sy 8014c40: 60fb str r3, [r7, #12] } 8014c42: bf00 nop 8014c44: bf00 nop 8014c46: e7fd b.n 8014c44 if( pcQueueName != NULL ) 8014c48: 683b ldr r3, [r7, #0] 8014c4a: 2b00 cmp r3, #0 8014c4c: d024 beq.n 8014c98 { /* See if there is an empty space in the registry. A NULL name denotes * a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014c4e: 2300 movs r3, #0 8014c50: 617b str r3, [r7, #20] 8014c52: e01e b.n 8014c92 { /* Replace an existing entry if the queue is already in the registry. */ if( xQueue == xQueueRegistry[ ux ].xHandle ) 8014c54: 4a18 ldr r2, [pc, #96] @ (8014cb8 ) 8014c56: 697b ldr r3, [r7, #20] 8014c58: 00db lsls r3, r3, #3 8014c5a: 4413 add r3, r2 8014c5c: 685b ldr r3, [r3, #4] 8014c5e: 687a ldr r2, [r7, #4] 8014c60: 429a cmp r2, r3 8014c62: d105 bne.n 8014c70 { pxEntryToWrite = &( xQueueRegistry[ ux ] ); 8014c64: 697b ldr r3, [r7, #20] 8014c66: 00db lsls r3, r3, #3 8014c68: 4a13 ldr r2, [pc, #76] @ (8014cb8 ) 8014c6a: 4413 add r3, r2 8014c6c: 613b str r3, [r7, #16] break; 8014c6e: e013 b.n 8014c98 } /* Otherwise, store in the next empty location */ else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) ) 8014c70: 693b ldr r3, [r7, #16] 8014c72: 2b00 cmp r3, #0 8014c74: d10a bne.n 8014c8c 8014c76: 4a10 ldr r2, [pc, #64] @ (8014cb8 ) 8014c78: 697b ldr r3, [r7, #20] 8014c7a: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8014c7e: 2b00 cmp r3, #0 8014c80: d104 bne.n 8014c8c { pxEntryToWrite = &( xQueueRegistry[ ux ] ); 8014c82: 697b ldr r3, [r7, #20] 8014c84: 00db lsls r3, r3, #3 8014c86: 4a0c ldr r2, [pc, #48] @ (8014cb8 ) 8014c88: 4413 add r3, r2 8014c8a: 613b str r3, [r7, #16] for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014c8c: 697b ldr r3, [r7, #20] 8014c8e: 3301 adds r3, #1 8014c90: 617b str r3, [r7, #20] 8014c92: 697b ldr r3, [r7, #20] 8014c94: 2b07 cmp r3, #7 8014c96: d9dd bls.n 8014c54 mtCOVERAGE_TEST_MARKER(); } } } if( pxEntryToWrite != NULL ) 8014c98: 693b ldr r3, [r7, #16] 8014c9a: 2b00 cmp r3, #0 8014c9c: d005 beq.n 8014caa { /* Store the information on this queue. */ pxEntryToWrite->pcQueueName = pcQueueName; 8014c9e: 693b ldr r3, [r7, #16] 8014ca0: 683a ldr r2, [r7, #0] 8014ca2: 601a str r2, [r3, #0] pxEntryToWrite->xHandle = xQueue; 8014ca4: 693b ldr r3, [r7, #16] 8014ca6: 687a ldr r2, [r7, #4] 8014ca8: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); } } 8014caa: bf00 nop 8014cac: 371c adds r7, #28 8014cae: 46bd mov sp, r7 8014cb0: f85d 7b04 ldr.w r7, [sp], #4 8014cb4: 4770 bx lr 8014cb6: bf00 nop 8014cb8: 20002088 .word 0x20002088 08014cbc : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueUnregisterQueue( QueueHandle_t xQueue ) { 8014cbc: b480 push {r7} 8014cbe: b085 sub sp, #20 8014cc0: af00 add r7, sp, #0 8014cc2: 6078 str r0, [r7, #4] UBaseType_t ux; configASSERT( xQueue ); 8014cc4: 687b ldr r3, [r7, #4] 8014cc6: 2b00 cmp r3, #0 8014cc8: d10b bne.n 8014ce2 __asm volatile 8014cca: f04f 0350 mov.w r3, #80 @ 0x50 8014cce: f383 8811 msr BASEPRI, r3 8014cd2: f3bf 8f6f isb sy 8014cd6: f3bf 8f4f dsb sy 8014cda: 60bb str r3, [r7, #8] } 8014cdc: bf00 nop 8014cde: bf00 nop 8014ce0: e7fd b.n 8014cde /* See if the handle of the queue being unregistered in actually in the * registry. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014ce2: 2300 movs r3, #0 8014ce4: 60fb str r3, [r7, #12] 8014ce6: e016 b.n 8014d16 { if( xQueueRegistry[ ux ].xHandle == xQueue ) 8014ce8: 4a10 ldr r2, [pc, #64] @ (8014d2c ) 8014cea: 68fb ldr r3, [r7, #12] 8014cec: 00db lsls r3, r3, #3 8014cee: 4413 add r3, r2 8014cf0: 685b ldr r3, [r3, #4] 8014cf2: 687a ldr r2, [r7, #4] 8014cf4: 429a cmp r2, r3 8014cf6: d10b bne.n 8014d10 { /* Set the name to NULL to show that this slot if free again. */ xQueueRegistry[ ux ].pcQueueName = NULL; 8014cf8: 4a0c ldr r2, [pc, #48] @ (8014d2c ) 8014cfa: 68fb ldr r3, [r7, #12] 8014cfc: 2100 movs r1, #0 8014cfe: f842 1033 str.w r1, [r2, r3, lsl #3] /* Set the handle to NULL to ensure the same queue handle cannot * appear in the registry twice if it is added, removed, then * added again. */ xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; 8014d02: 4a0a ldr r2, [pc, #40] @ (8014d2c ) 8014d04: 68fb ldr r3, [r7, #12] 8014d06: 00db lsls r3, r3, #3 8014d08: 4413 add r3, r2 8014d0a: 2200 movs r2, #0 8014d0c: 605a str r2, [r3, #4] break; 8014d0e: e006 b.n 8014d1e for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014d10: 68fb ldr r3, [r7, #12] 8014d12: 3301 adds r3, #1 8014d14: 60fb str r3, [r7, #12] 8014d16: 68fb ldr r3, [r7, #12] 8014d18: 2b07 cmp r3, #7 8014d1a: d9e5 bls.n 8014ce8 else { mtCOVERAGE_TEST_MARKER(); } } } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ 8014d1c: bf00 nop 8014d1e: bf00 nop 8014d20: 3714 adds r7, #20 8014d22: 46bd mov sp, r7 8014d24: f85d 7b04 ldr.w r7, [sp], #4 8014d28: 4770 bx lr 8014d2a: bf00 nop 8014d2c: 20002088 .word 0x20002088 08014d30 : #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8014d30: b580 push {r7, lr} 8014d32: b086 sub sp, #24 8014d34: af00 add r7, sp, #0 8014d36: 60f8 str r0, [r7, #12] 8014d38: 60b9 str r1, [r7, #8] 8014d3a: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 8014d3c: 68fb ldr r3, [r7, #12] 8014d3e: 617b str r3, [r7, #20] * will not actually cause the task to block, just place it on a blocked * list. It will not block until the scheduler is unlocked - at which * time a yield will be performed. If an item is added to the queue while * the queue is locked, and the calling task blocks on the queue, then the * calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 8014d40: f002 fb0e bl 8017360 8014d44: 697b ldr r3, [r7, #20] 8014d46: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014d4a: b25b sxtb r3, r3 8014d4c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014d50: d103 bne.n 8014d5a 8014d52: 697b ldr r3, [r7, #20] 8014d54: 2200 movs r2, #0 8014d56: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014d5a: 697b ldr r3, [r7, #20] 8014d5c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014d60: b25b sxtb r3, r3 8014d62: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014d66: d103 bne.n 8014d70 8014d68: 697b ldr r3, [r7, #20] 8014d6a: 2200 movs r2, #0 8014d6c: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014d70: f002 fb28 bl 80173c4 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8014d74: 697b ldr r3, [r7, #20] 8014d76: 6b9b ldr r3, [r3, #56] @ 0x38 8014d78: 2b00 cmp r3, #0 8014d7a: d106 bne.n 8014d8a { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8014d7c: 697b ldr r3, [r7, #20] 8014d7e: 3324 adds r3, #36 @ 0x24 8014d80: 687a ldr r2, [r7, #4] 8014d82: 68b9 ldr r1, [r7, #8] 8014d84: 4618 mov r0, r3 8014d86: f000 fd45 bl 8015814 else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8014d8a: 6978 ldr r0, [r7, #20] 8014d8c: f7ff fec6 bl 8014b1c } 8014d90: bf00 nop 8014d92: 3718 adds r7, #24 8014d94: 46bd mov sp, r7 8014d96: bd80 pop {r7, pc} 08014d98 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8014d98: b580 push {r7, lr} 8014d9a: b08e sub sp, #56 @ 0x38 8014d9c: af04 add r7, sp, #16 8014d9e: 60f8 str r0, [r7, #12] 8014da0: 60b9 str r1, [r7, #8] 8014da2: 607a str r2, [r7, #4] 8014da4: 603b str r3, [r7, #0] TCB_t * pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8014da6: 6b7b ldr r3, [r7, #52] @ 0x34 8014da8: 2b00 cmp r3, #0 8014daa: d10b bne.n 8014dc4 __asm volatile 8014dac: f04f 0350 mov.w r3, #80 @ 0x50 8014db0: f383 8811 msr BASEPRI, r3 8014db4: f3bf 8f6f isb sy 8014db8: f3bf 8f4f dsb sy 8014dbc: 623b str r3, [r7, #32] } 8014dbe: bf00 nop 8014dc0: bf00 nop 8014dc2: e7fd b.n 8014dc0 configASSERT( pxTaskBuffer != NULL ); 8014dc4: 6bbb ldr r3, [r7, #56] @ 0x38 8014dc6: 2b00 cmp r3, #0 8014dc8: d10b bne.n 8014de2 __asm volatile 8014dca: f04f 0350 mov.w r3, #80 @ 0x50 8014dce: f383 8811 msr BASEPRI, r3 8014dd2: f3bf 8f6f isb sy 8014dd6: f3bf 8f4f dsb sy 8014dda: 61fb str r3, [r7, #28] } 8014ddc: bf00 nop 8014dde: bf00 nop 8014de0: e7fd b.n 8014dde #if ( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a * variable of type StaticTask_t equals the size of the real task * structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8014de2: 235c movs r3, #92 @ 0x5c 8014de4: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8014de6: 693b ldr r3, [r7, #16] 8014de8: 2b5c cmp r3, #92 @ 0x5c 8014dea: d00b beq.n 8014e04 __asm volatile 8014dec: f04f 0350 mov.w r3, #80 @ 0x50 8014df0: f383 8811 msr BASEPRI, r3 8014df4: f3bf 8f6f isb sy 8014df8: f3bf 8f4f dsb sy 8014dfc: 61bb str r3, [r7, #24] } 8014dfe: bf00 nop 8014e00: bf00 nop 8014e02: e7fd b.n 8014e00 ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8014e04: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8014e06: 6bbb ldr r3, [r7, #56] @ 0x38 8014e08: 2b00 cmp r3, #0 8014e0a: d023 beq.n 8014e54 8014e0c: 6b7b ldr r3, [r7, #52] @ 0x34 8014e0e: 2b00 cmp r3, #0 8014e10: d020 beq.n 8014e54 { /* The memory used for the task's TCB and stack are passed into this * function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8014e12: 6bbb ldr r3, [r7, #56] @ 0x38 8014e14: 627b str r3, [r7, #36] @ 0x24 memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); 8014e16: 225c movs r2, #92 @ 0x5c 8014e18: 2100 movs r1, #0 8014e1a: 6a78 ldr r0, [r7, #36] @ 0x24 8014e1c: f004 fe7a bl 8019b14 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8014e20: 6a7b ldr r3, [r7, #36] @ 0x24 8014e22: 6b7a ldr r2, [r7, #52] @ 0x34 8014e24: 631a str r2, [r3, #48] @ 0x30 #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this * task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 8014e26: 6a7b ldr r3, [r7, #36] @ 0x24 8014e28: 2202 movs r2, #2 8014e2a: f883 2059 strb.w r2, [r3, #89] @ 0x59 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8014e2e: 2300 movs r3, #0 8014e30: 9303 str r3, [sp, #12] 8014e32: 6a7b ldr r3, [r7, #36] @ 0x24 8014e34: 9302 str r3, [sp, #8] 8014e36: f107 0314 add.w r3, r7, #20 8014e3a: 9301 str r3, [sp, #4] 8014e3c: 6b3b ldr r3, [r7, #48] @ 0x30 8014e3e: 9300 str r3, [sp, #0] 8014e40: 683b ldr r3, [r7, #0] 8014e42: 687a ldr r2, [r7, #4] 8014e44: 68b9 ldr r1, [r7, #8] 8014e46: 68f8 ldr r0, [r7, #12] 8014e48: f000 f855 bl 8014ef6 prvAddNewTaskToReadyList( pxNewTCB ); 8014e4c: 6a78 ldr r0, [r7, #36] @ 0x24 8014e4e: f000 f8e3 bl 8015018 8014e52: e001 b.n 8014e58 } else { xReturn = NULL; 8014e54: 2300 movs r3, #0 8014e56: 617b str r3, [r7, #20] } return xReturn; 8014e58: 697b ldr r3, [r7, #20] } 8014e5a: 4618 mov r0, r3 8014e5c: 3728 adds r7, #40 @ 0x28 8014e5e: 46bd mov sp, r7 8014e60: bd80 pop {r7, pc} 08014e62 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8014e62: b580 push {r7, lr} 8014e64: b08c sub sp, #48 @ 0x30 8014e66: af04 add r7, sp, #16 8014e68: 60f8 str r0, [r7, #12] 8014e6a: 60b9 str r1, [r7, #8] 8014e6c: 603b str r3, [r7, #0] 8014e6e: 4613 mov r3, r2 8014e70: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t * pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8014e72: 88fb ldrh r3, [r7, #6] 8014e74: 009b lsls r3, r3, #2 8014e76: 4618 mov r0, r3 8014e78: f002 fb9a bl 80175b0 8014e7c: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8014e7e: 697b ldr r3, [r7, #20] 8014e80: 2b00 cmp r3, #0 8014e82: d013 beq.n 8014eac { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8014e84: 205c movs r0, #92 @ 0x5c 8014e86: f002 fb93 bl 80175b0 8014e8a: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8014e8c: 69fb ldr r3, [r7, #28] 8014e8e: 2b00 cmp r3, #0 8014e90: d008 beq.n 8014ea4 { memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); 8014e92: 225c movs r2, #92 @ 0x5c 8014e94: 2100 movs r1, #0 8014e96: 69f8 ldr r0, [r7, #28] 8014e98: f004 fe3c bl 8019b14 /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8014e9c: 69fb ldr r3, [r7, #28] 8014e9e: 697a ldr r2, [r7, #20] 8014ea0: 631a str r2, [r3, #48] @ 0x30 8014ea2: e005 b.n 8014eb0 } else { /* The stack cannot be used as the TCB was not created. Free * it again. */ vPortFreeStack( pxStack ); 8014ea4: 6978 ldr r0, [r7, #20] 8014ea6: f002 fc4f bl 8017748 8014eaa: e001 b.n 8014eb0 } } else { pxNewTCB = NULL; 8014eac: 2300 movs r3, #0 8014eae: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 8014eb0: 69fb ldr r3, [r7, #28] 8014eb2: 2b00 cmp r3, #0 8014eb4: d017 beq.n 8014ee6 { #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this * task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8014eb6: 69fb ldr r3, [r7, #28] 8014eb8: 2200 movs r2, #0 8014eba: f883 2059 strb.w r2, [r3, #89] @ 0x59 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 8014ebe: 88fa ldrh r2, [r7, #6] 8014ec0: 2300 movs r3, #0 8014ec2: 9303 str r3, [sp, #12] 8014ec4: 69fb ldr r3, [r7, #28] 8014ec6: 9302 str r3, [sp, #8] 8014ec8: 6afb ldr r3, [r7, #44] @ 0x2c 8014eca: 9301 str r3, [sp, #4] 8014ecc: 6abb ldr r3, [r7, #40] @ 0x28 8014ece: 9300 str r3, [sp, #0] 8014ed0: 683b ldr r3, [r7, #0] 8014ed2: 68b9 ldr r1, [r7, #8] 8014ed4: 68f8 ldr r0, [r7, #12] 8014ed6: f000 f80e bl 8014ef6 prvAddNewTaskToReadyList( pxNewTCB ); 8014eda: 69f8 ldr r0, [r7, #28] 8014edc: f000 f89c bl 8015018 xReturn = pdPASS; 8014ee0: 2301 movs r3, #1 8014ee2: 61bb str r3, [r7, #24] 8014ee4: e002 b.n 8014eec } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8014ee6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014eea: 61bb str r3, [r7, #24] } return xReturn; 8014eec: 69bb ldr r3, [r7, #24] } 8014eee: 4618 mov r0, r3 8014ef0: 3720 adds r7, #32 8014ef2: 46bd mov sp, r7 8014ef4: bd80 pop {r7, pc} 08014ef6 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t * pxNewTCB, const MemoryRegion_t * const xRegions ) { 8014ef6: b580 push {r7, lr} 8014ef8: b088 sub sp, #32 8014efa: af00 add r7, sp, #0 8014efc: 60f8 str r0, [r7, #12] 8014efe: 60b9 str r1, [r7, #8] 8014f00: 607a str r2, [r7, #4] 8014f02: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 8014f04: 6b3b ldr r3, [r7, #48] @ 0x30 8014f06: 6b18 ldr r0, [r3, #48] @ 0x30 8014f08: 687b ldr r3, [r7, #4] 8014f0a: 009b lsls r3, r3, #2 8014f0c: 461a mov r2, r3 8014f0e: 21a5 movs r1, #165 @ 0xa5 8014f10: f004 fe00 bl 8019b14 * grows from high memory to low (as per the 80x86) or vice versa. * portSTACK_GROWTH is used to make the result positive or negative as required * by the port. */ #if ( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 8014f14: 6b3b ldr r3, [r7, #48] @ 0x30 8014f16: 6b1a ldr r2, [r3, #48] @ 0x30 8014f18: 687b ldr r3, [r7, #4] 8014f1a: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 8014f1e: 3b01 subs r3, #1 8014f20: 009b lsls r3, r3, #2 8014f22: 4413 add r3, r2 8014f24: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8014f26: 69bb ldr r3, [r7, #24] 8014f28: f023 0307 bic.w r3, r3, #7 8014f2c: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8014f2e: 69bb ldr r3, [r7, #24] 8014f30: f003 0307 and.w r3, r3, #7 8014f34: 2b00 cmp r3, #0 8014f36: d00b beq.n 8014f50 __asm volatile 8014f38: f04f 0350 mov.w r3, #80 @ 0x50 8014f3c: f383 8811 msr BASEPRI, r3 8014f40: f3bf 8f6f isb sy 8014f44: f3bf 8f4f dsb sy 8014f48: 617b str r3, [r7, #20] } 8014f4a: bf00 nop 8014f4c: bf00 nop 8014f4e: e7fd b.n 8014f4c pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 8014f50: 68bb ldr r3, [r7, #8] 8014f52: 2b00 cmp r3, #0 8014f54: d01e beq.n 8014f94 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8014f56: 2300 movs r3, #0 8014f58: 61fb str r3, [r7, #28] 8014f5a: e012 b.n 8014f82 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8014f5c: 68ba ldr r2, [r7, #8] 8014f5e: 69fb ldr r3, [r7, #28] 8014f60: 4413 add r3, r2 8014f62: 7819 ldrb r1, [r3, #0] 8014f64: 6b3a ldr r2, [r7, #48] @ 0x30 8014f66: 69fb ldr r3, [r7, #28] 8014f68: 4413 add r3, r2 8014f6a: 3334 adds r3, #52 @ 0x34 8014f6c: 460a mov r2, r1 8014f6e: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than * configMAX_TASK_NAME_LEN characters just in case the memory after the * string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 8014f70: 68ba ldr r2, [r7, #8] 8014f72: 69fb ldr r3, [r7, #28] 8014f74: 4413 add r3, r2 8014f76: 781b ldrb r3, [r3, #0] 8014f78: 2b00 cmp r3, #0 8014f7a: d006 beq.n 8014f8a for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8014f7c: 69fb ldr r3, [r7, #28] 8014f7e: 3301 adds r3, #1 8014f80: 61fb str r3, [r7, #28] 8014f82: 69fb ldr r3, [r7, #28] 8014f84: 2b0f cmp r3, #15 8014f86: d9e9 bls.n 8014f5c 8014f88: e000 b.n 8014f8c { break; 8014f8a: bf00 nop } } /* Ensure the name string is terminated in the case that the string length * was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 8014f8c: 6b3b ldr r3, [r7, #48] @ 0x30 8014f8e: 2200 movs r2, #0 8014f90: f883 2043 strb.w r2, [r3, #67] @ 0x43 { mtCOVERAGE_TEST_MARKER(); } /* This is used as an array index so must ensure it's not too large. */ configASSERT( uxPriority < configMAX_PRIORITIES ); 8014f94: 6abb ldr r3, [r7, #40] @ 0x28 8014f96: 2b37 cmp r3, #55 @ 0x37 8014f98: d90b bls.n 8014fb2 __asm volatile 8014f9a: f04f 0350 mov.w r3, #80 @ 0x50 8014f9e: f383 8811 msr BASEPRI, r3 8014fa2: f3bf 8f6f isb sy 8014fa6: f3bf 8f4f dsb sy 8014faa: 613b str r3, [r7, #16] } 8014fac: bf00 nop 8014fae: bf00 nop 8014fb0: e7fd b.n 8014fae if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8014fb2: 6abb ldr r3, [r7, #40] @ 0x28 8014fb4: 2b37 cmp r3, #55 @ 0x37 8014fb6: d901 bls.n 8014fbc { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8014fb8: 2337 movs r3, #55 @ 0x37 8014fba: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 8014fbc: 6b3b ldr r3, [r7, #48] @ 0x30 8014fbe: 6aba ldr r2, [r7, #40] @ 0x28 8014fc0: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 8014fc2: 6b3b ldr r3, [r7, #48] @ 0x30 8014fc4: 6aba ldr r2, [r7, #40] @ 0x28 8014fc6: 64da str r2, [r3, #76] @ 0x4c } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8014fc8: 6b3b ldr r3, [r7, #48] @ 0x30 8014fca: 3304 adds r3, #4 8014fcc: 4618 mov r0, r3 8014fce: f7fe fd09 bl 80139e4 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8014fd2: 6b3b ldr r3, [r7, #48] @ 0x30 8014fd4: 3318 adds r3, #24 8014fd6: 4618 mov r0, r3 8014fd8: f7fe fd04 bl 80139e4 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get * back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 8014fdc: 6b3b ldr r3, [r7, #48] @ 0x30 8014fde: 6b3a ldr r2, [r7, #48] @ 0x30 8014fe0: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014fe2: 6abb ldr r3, [r7, #40] @ 0x28 8014fe4: f1c3 0238 rsb r2, r3, #56 @ 0x38 8014fe8: 6b3b ldr r3, [r7, #48] @ 0x30 8014fea: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 8014fec: 6b3b ldr r3, [r7, #48] @ 0x30 8014fee: 6b3a ldr r2, [r7, #48] @ 0x30 8014ff0: 625a str r2, [r3, #36] @ 0x24 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 8014ff2: 683a ldr r2, [r7, #0] 8014ff4: 68f9 ldr r1, [r7, #12] 8014ff6: 69b8 ldr r0, [r7, #24] 8014ff8: f002 f866 bl 80170c8 8014ffc: 4602 mov r2, r0 8014ffe: 6b3b ldr r3, [r7, #48] @ 0x30 8015000: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 8015002: 6afb ldr r3, [r7, #44] @ 0x2c 8015004: 2b00 cmp r3, #0 8015006: d002 beq.n 801500e { /* Pass the handle out in an anonymous way. The handle can be used to * change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8015008: 6afb ldr r3, [r7, #44] @ 0x2c 801500a: 6b3a ldr r2, [r7, #48] @ 0x30 801500c: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 801500e: bf00 nop 8015010: 3720 adds r7, #32 8015012: 46bd mov sp, r7 8015014: bd80 pop {r7, pc} ... 08015018 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { 8015018: b580 push {r7, lr} 801501a: b084 sub sp, #16 801501c: af00 add r7, sp, #0 801501e: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being * updated. */ taskENTER_CRITICAL(); 8015020: f002 f99e bl 8017360 { uxCurrentNumberOfTasks++; 8015024: 4b41 ldr r3, [pc, #260] @ (801512c ) 8015026: 681b ldr r3, [r3, #0] 8015028: 3301 adds r3, #1 801502a: 4a40 ldr r2, [pc, #256] @ (801512c ) 801502c: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 801502e: 4b40 ldr r3, [pc, #256] @ (8015130 ) 8015030: 681b ldr r3, [r3, #0] 8015032: 2b00 cmp r3, #0 8015034: d109 bne.n 801504a { /* There are no other tasks, or all the other tasks are in * the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 8015036: 4a3e ldr r2, [pc, #248] @ (8015130 ) 8015038: 687b ldr r3, [r7, #4] 801503a: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 801503c: 4b3b ldr r3, [pc, #236] @ (801512c ) 801503e: 681b ldr r3, [r3, #0] 8015040: 2b01 cmp r3, #1 8015042: d110 bne.n 8015066 { /* This is the first task to be created so do the preliminary * initialisation required. We will not recover if this call * fails, but we will report the failure. */ prvInitialiseTaskLists(); 8015044: f000 fda6 bl 8015b94 8015048: e00d b.n 8015066 else { /* If the scheduler is not already running, make this task the * current task if it is the highest priority task to be created * so far. */ if( xSchedulerRunning == pdFALSE ) 801504a: 4b3a ldr r3, [pc, #232] @ (8015134 ) 801504c: 681b ldr r3, [r3, #0] 801504e: 2b00 cmp r3, #0 8015050: d109 bne.n 8015066 { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 8015052: 4b37 ldr r3, [pc, #220] @ (8015130 ) 8015054: 681b ldr r3, [r3, #0] 8015056: 6ada ldr r2, [r3, #44] @ 0x2c 8015058: 687b ldr r3, [r7, #4] 801505a: 6adb ldr r3, [r3, #44] @ 0x2c 801505c: 429a cmp r2, r3 801505e: d802 bhi.n 8015066 { pxCurrentTCB = pxNewTCB; 8015060: 4a33 ldr r2, [pc, #204] @ (8015130 ) 8015062: 687b ldr r3, [r7, #4] 8015064: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 8015066: 4b34 ldr r3, [pc, #208] @ (8015138 ) 8015068: 681b ldr r3, [r3, #0] 801506a: 3301 adds r3, #1 801506c: 4a32 ldr r2, [pc, #200] @ (8015138 ) 801506e: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 8015070: 4b31 ldr r3, [pc, #196] @ (8015138 ) 8015072: 681a ldr r2, [r3, #0] 8015074: 687b ldr r3, [r7, #4] 8015076: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 8015078: 687b ldr r3, [r7, #4] 801507a: 6ada ldr r2, [r3, #44] @ 0x2c 801507c: 4b2f ldr r3, [pc, #188] @ (801513c ) 801507e: 681b ldr r3, [r3, #0] 8015080: 429a cmp r2, r3 8015082: d903 bls.n 801508c 8015084: 687b ldr r3, [r7, #4] 8015086: 6adb ldr r3, [r3, #44] @ 0x2c 8015088: 4a2c ldr r2, [pc, #176] @ (801513c ) 801508a: 6013 str r3, [r2, #0] 801508c: 687b ldr r3, [r7, #4] 801508e: 6ada ldr r2, [r3, #44] @ 0x2c 8015090: 492b ldr r1, [pc, #172] @ (8015140 ) 8015092: 4613 mov r3, r2 8015094: 009b lsls r3, r3, #2 8015096: 4413 add r3, r2 8015098: 009b lsls r3, r3, #2 801509a: 440b add r3, r1 801509c: 3304 adds r3, #4 801509e: 681b ldr r3, [r3, #0] 80150a0: 60fb str r3, [r7, #12] 80150a2: 687b ldr r3, [r7, #4] 80150a4: 68fa ldr r2, [r7, #12] 80150a6: 609a str r2, [r3, #8] 80150a8: 68fb ldr r3, [r7, #12] 80150aa: 689a ldr r2, [r3, #8] 80150ac: 687b ldr r3, [r7, #4] 80150ae: 60da str r2, [r3, #12] 80150b0: 68fb ldr r3, [r7, #12] 80150b2: 689b ldr r3, [r3, #8] 80150b4: 687a ldr r2, [r7, #4] 80150b6: 3204 adds r2, #4 80150b8: 605a str r2, [r3, #4] 80150ba: 687b ldr r3, [r7, #4] 80150bc: 1d1a adds r2, r3, #4 80150be: 68fb ldr r3, [r7, #12] 80150c0: 609a str r2, [r3, #8] 80150c2: 687b ldr r3, [r7, #4] 80150c4: 6ada ldr r2, [r3, #44] @ 0x2c 80150c6: 4613 mov r3, r2 80150c8: 009b lsls r3, r3, #2 80150ca: 4413 add r3, r2 80150cc: 009b lsls r3, r3, #2 80150ce: 4a1c ldr r2, [pc, #112] @ (8015140 ) 80150d0: 441a add r2, r3 80150d2: 687b ldr r3, [r7, #4] 80150d4: 615a str r2, [r3, #20] 80150d6: 687b ldr r3, [r7, #4] 80150d8: 6ada ldr r2, [r3, #44] @ 0x2c 80150da: 4919 ldr r1, [pc, #100] @ (8015140 ) 80150dc: 4613 mov r3, r2 80150de: 009b lsls r3, r3, #2 80150e0: 4413 add r3, r2 80150e2: 009b lsls r3, r3, #2 80150e4: 440b add r3, r1 80150e6: 681b ldr r3, [r3, #0] 80150e8: 1c59 adds r1, r3, #1 80150ea: 4815 ldr r0, [pc, #84] @ (8015140 ) 80150ec: 4613 mov r3, r2 80150ee: 009b lsls r3, r3, #2 80150f0: 4413 add r3, r2 80150f2: 009b lsls r3, r3, #2 80150f4: 4403 add r3, r0 80150f6: 6019 str r1, [r3, #0] portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 80150f8: f002 f964 bl 80173c4 if( xSchedulerRunning != pdFALSE ) 80150fc: 4b0d ldr r3, [pc, #52] @ (8015134 ) 80150fe: 681b ldr r3, [r3, #0] 8015100: 2b00 cmp r3, #0 8015102: d00e beq.n 8015122 { /* If the created task is of a higher priority than the current task * then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8015104: 4b0a ldr r3, [pc, #40] @ (8015130 ) 8015106: 681b ldr r3, [r3, #0] 8015108: 6ada ldr r2, [r3, #44] @ 0x2c 801510a: 687b ldr r3, [r7, #4] 801510c: 6adb ldr r3, [r3, #44] @ 0x2c 801510e: 429a cmp r2, r3 8015110: d207 bcs.n 8015122 { taskYIELD_IF_USING_PREEMPTION(); 8015112: 4b0c ldr r3, [pc, #48] @ (8015144 ) 8015114: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015118: 601a str r2, [r3, #0] 801511a: f3bf 8f4f dsb sy 801511e: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8015122: bf00 nop 8015124: 3710 adds r7, #16 8015126: 46bd mov sp, r7 8015128: bd80 pop {r7, pc} 801512a: bf00 nop 801512c: 2000259c .word 0x2000259c 8015130: 200020c8 .word 0x200020c8 8015134: 200025a8 .word 0x200025a8 8015138: 200025b8 .word 0x200025b8 801513c: 200025a4 .word 0x200025a4 8015140: 200020cc .word 0x200020cc 8015144: e000ed04 .word 0xe000ed04 08015148 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8015148: b580 push {r7, lr} 801514a: b084 sub sp, #16 801514c: af00 add r7, sp, #0 801514e: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 8015150: 2300 movs r3, #0 8015152: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 8015154: 687b ldr r3, [r7, #4] 8015156: 2b00 cmp r3, #0 8015158: d018 beq.n 801518c { configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U ); 801515a: 4b14 ldr r3, [pc, #80] @ (80151ac ) 801515c: 681b ldr r3, [r3, #0] 801515e: 2b00 cmp r3, #0 8015160: d00b beq.n 801517a __asm volatile 8015162: f04f 0350 mov.w r3, #80 @ 0x50 8015166: f383 8811 msr BASEPRI, r3 801516a: f3bf 8f6f isb sy 801516e: f3bf 8f4f dsb sy 8015172: 60bb str r3, [r7, #8] } 8015174: bf00 nop 8015176: bf00 nop 8015178: e7fd b.n 8015176 vTaskSuspendAll(); 801517a: f000 f887 bl 801528c * list or removed from the blocked list until the scheduler * is resumed. * * This task cannot be in an event list as it is the currently * executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 801517e: 2100 movs r1, #0 8015180: 6878 ldr r0, [r7, #4] 8015182: f001 fc6b bl 8016a5c } xAlreadyYielded = xTaskResumeAll(); 8015186: f000 f88f bl 80152a8 801518a: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may * have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 801518c: 68fb ldr r3, [r7, #12] 801518e: 2b00 cmp r3, #0 8015190: d107 bne.n 80151a2 { portYIELD_WITHIN_API(); 8015192: 4b07 ldr r3, [pc, #28] @ (80151b0 ) 8015194: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015198: 601a str r2, [r3, #0] 801519a: f3bf 8f4f dsb sy 801519e: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 80151a2: bf00 nop 80151a4: 3710 adds r7, #16 80151a6: 46bd mov sp, r7 80151a8: bd80 pop {r7, pc} 80151aa: bf00 nop 80151ac: 200025c4 .word 0x200025c4 80151b0: e000ed04 .word 0xe000ed04 080151b4 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 80151b4: b580 push {r7, lr} 80151b6: b08a sub sp, #40 @ 0x28 80151b8: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t * pxIdleTaskTCBBuffer = NULL; 80151ba: 2300 movs r3, #0 80151bc: 60bb str r3, [r7, #8] StackType_t * pxIdleTaskStackBuffer = NULL; 80151be: 2300 movs r3, #0 80151c0: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the * address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 80151c2: 463a mov r2, r7 80151c4: 1d39 adds r1, r7, #4 80151c6: f107 0308 add.w r3, r7, #8 80151ca: 4618 mov r0, r3 80151cc: f7fe fbb6 bl 801393c xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 80151d0: 6839 ldr r1, [r7, #0] 80151d2: 687b ldr r3, [r7, #4] 80151d4: 68ba ldr r2, [r7, #8] 80151d6: 9202 str r2, [sp, #8] 80151d8: 9301 str r3, [sp, #4] 80151da: 2300 movs r3, #0 80151dc: 9300 str r3, [sp, #0] 80151de: 2300 movs r3, #0 80151e0: 460a mov r2, r1 80151e2: 4923 ldr r1, [pc, #140] @ (8015270 ) 80151e4: 4823 ldr r0, [pc, #140] @ (8015274 ) 80151e6: f7ff fdd7 bl 8014d98 80151ea: 4603 mov r3, r0 80151ec: 4a22 ldr r2, [pc, #136] @ (8015278 ) 80151ee: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 80151f0: 4b21 ldr r3, [pc, #132] @ (8015278 ) 80151f2: 681b ldr r3, [r3, #0] 80151f4: 2b00 cmp r3, #0 80151f6: d002 beq.n 80151fe { xReturn = pdPASS; 80151f8: 2301 movs r3, #1 80151fa: 617b str r3, [r7, #20] 80151fc: e001 b.n 8015202 } else { xReturn = pdFAIL; 80151fe: 2300 movs r3, #0 8015200: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 8015202: 697b ldr r3, [r7, #20] 8015204: 2b01 cmp r3, #1 8015206: d102 bne.n 801520e { xReturn = xTimerCreateTimerTask(); 8015208: f001 fc96 bl 8016b38 801520c: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 801520e: 697b ldr r3, [r7, #20] 8015210: 2b01 cmp r3, #1 8015212: d116 bne.n 8015242 __asm volatile 8015214: f04f 0350 mov.w r3, #80 @ 0x50 8015218: f383 8811 msr BASEPRI, r3 801521c: f3bf 8f6f isb sy 8015220: f3bf 8f4f dsb sy 8015224: 613b str r3, [r7, #16] } 8015226: bf00 nop * block specific to the task that will run first. */ configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); } #endif xNextTaskUnblockTime = portMAX_DELAY; 8015228: 4b14 ldr r3, [pc, #80] @ (801527c ) 801522a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801522e: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8015230: 4b13 ldr r3, [pc, #76] @ (8015280 ) 8015232: 2201 movs r2, #1 8015234: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 8015236: 4b13 ldr r3, [pc, #76] @ (8015284 ) 8015238: 2200 movs r2, #0 801523a: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the * portable interface. */ xPortStartScheduler(); 801523c: f001 ffd2 bl 80171e4 8015240: e00f b.n 8015262 else { /* This line will only be reached if the kernel could not be started, * because there was not enough FreeRTOS heap to create the idle task * or the timer task. */ configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8015242: 697b ldr r3, [r7, #20] 8015244: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015248: d10b bne.n 8015262 __asm volatile 801524a: f04f 0350 mov.w r3, #80 @ 0x50 801524e: f383 8811 msr BASEPRI, r3 8015252: f3bf 8f6f isb sy 8015256: f3bf 8f4f dsb sy 801525a: 60fb str r3, [r7, #12] } 801525c: bf00 nop 801525e: bf00 nop 8015260: e7fd b.n 801525e * meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority * from getting optimized out as it is no longer used by the kernel. */ ( void ) uxTopUsedPriority; 8015262: 4b09 ldr r3, [pc, #36] @ (8015288 ) 8015264: 681b ldr r3, [r3, #0] } 8015266: bf00 nop 8015268: 3718 adds r7, #24 801526a: 46bd mov sp, r7 801526c: bd80 pop {r7, pc} 801526e: bf00 nop 8015270: 0801d9bc .word 0x0801d9bc 8015274: 08015b65 .word 0x08015b65 8015278: 200025c0 .word 0x200025c0 801527c: 200025bc .word 0x200025bc 8015280: 200025a8 .word 0x200025a8 8015284: 200025a0 .word 0x200025a0 8015288: 0801dcac .word 0x0801dcac 0801528c : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 801528c: b480 push {r7} 801528e: af00 add r7, sp, #0 * do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment * is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8015290: 4b04 ldr r3, [pc, #16] @ (80152a4 ) 8015292: 681b ldr r3, [r3, #0] 8015294: 3301 adds r3, #1 8015296: 4a03 ldr r2, [pc, #12] @ (80152a4 ) 8015298: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place * the above increment elsewhere. */ portMEMORY_BARRIER(); } 801529a: bf00 nop 801529c: 46bd mov sp, r7 801529e: f85d 7b04 ldr.w r7, [sp], #4 80152a2: 4770 bx lr 80152a4: 200025c4 .word 0x200025c4 080152a8 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 80152a8: b580 push {r7, lr} 80152aa: b088 sub sp, #32 80152ac: af00 add r7, sp, #0 TCB_t * pxTCB = NULL; 80152ae: 2300 movs r3, #0 80152b0: 61fb str r3, [r7, #28] BaseType_t xAlreadyYielded = pdFALSE; 80152b2: 2300 movs r3, #0 80152b4: 61bb str r3, [r7, #24] /* If uxSchedulerSuspended is zero then this function does not match a * previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U ); 80152b6: 4b72 ldr r3, [pc, #456] @ (8015480 ) 80152b8: 681b ldr r3, [r3, #0] 80152ba: 2b00 cmp r3, #0 80152bc: d10b bne.n 80152d6 __asm volatile 80152be: f04f 0350 mov.w r3, #80 @ 0x50 80152c2: f383 8811 msr BASEPRI, r3 80152c6: f3bf 8f6f isb sy 80152ca: f3bf 8f4f dsb sy 80152ce: 607b str r3, [r7, #4] } 80152d0: bf00 nop 80152d2: bf00 nop 80152d4: e7fd b.n 80152d2 /* It is possible that an ISR caused a task to be removed from an event * list while the scheduler was suspended. If this was the case then the * removed task will have been added to the xPendingReadyList. Once the * scheduler has been resumed it is safe to move all the pending ready * tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 80152d6: f002 f843 bl 8017360 { --uxSchedulerSuspended; 80152da: 4b69 ldr r3, [pc, #420] @ (8015480 ) 80152dc: 681b ldr r3, [r3, #0] 80152de: 3b01 subs r3, #1 80152e0: 4a67 ldr r2, [pc, #412] @ (8015480 ) 80152e2: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 80152e4: 4b66 ldr r3, [pc, #408] @ (8015480 ) 80152e6: 681b ldr r3, [r3, #0] 80152e8: 2b00 cmp r3, #0 80152ea: f040 80c1 bne.w 8015470 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80152ee: 4b65 ldr r3, [pc, #404] @ (8015484 ) 80152f0: 681b ldr r3, [r3, #0] 80152f2: 2b00 cmp r3, #0 80152f4: f000 80bc beq.w 8015470 { /* Move any readied tasks from the pending list into the * appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80152f8: e08b b.n 8015412 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80152fa: 4b63 ldr r3, [pc, #396] @ (8015488 ) 80152fc: 68db ldr r3, [r3, #12] 80152fe: 68db ldr r3, [r3, #12] 8015300: 61fb str r3, [r7, #28] listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); 8015302: 69fb ldr r3, [r7, #28] 8015304: 6a9b ldr r3, [r3, #40] @ 0x28 8015306: 613b str r3, [r7, #16] 8015308: 69fb ldr r3, [r7, #28] 801530a: 69db ldr r3, [r3, #28] 801530c: 69fa ldr r2, [r7, #28] 801530e: 6a12 ldr r2, [r2, #32] 8015310: 609a str r2, [r3, #8] 8015312: 69fb ldr r3, [r7, #28] 8015314: 6a1b ldr r3, [r3, #32] 8015316: 69fa ldr r2, [r7, #28] 8015318: 69d2 ldr r2, [r2, #28] 801531a: 605a str r2, [r3, #4] 801531c: 693b ldr r3, [r7, #16] 801531e: 685a ldr r2, [r3, #4] 8015320: 69fb ldr r3, [r7, #28] 8015322: 3318 adds r3, #24 8015324: 429a cmp r2, r3 8015326: d103 bne.n 8015330 8015328: 69fb ldr r3, [r7, #28] 801532a: 6a1a ldr r2, [r3, #32] 801532c: 693b ldr r3, [r7, #16] 801532e: 605a str r2, [r3, #4] 8015330: 69fb ldr r3, [r7, #28] 8015332: 2200 movs r2, #0 8015334: 629a str r2, [r3, #40] @ 0x28 8015336: 693b ldr r3, [r7, #16] 8015338: 681b ldr r3, [r3, #0] 801533a: 1e5a subs r2, r3, #1 801533c: 693b ldr r3, [r7, #16] 801533e: 601a str r2, [r3, #0] portMEMORY_BARRIER(); listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 8015340: 69fb ldr r3, [r7, #28] 8015342: 695b ldr r3, [r3, #20] 8015344: 60fb str r3, [r7, #12] 8015346: 69fb ldr r3, [r7, #28] 8015348: 689b ldr r3, [r3, #8] 801534a: 69fa ldr r2, [r7, #28] 801534c: 68d2 ldr r2, [r2, #12] 801534e: 609a str r2, [r3, #8] 8015350: 69fb ldr r3, [r7, #28] 8015352: 68db ldr r3, [r3, #12] 8015354: 69fa ldr r2, [r7, #28] 8015356: 6892 ldr r2, [r2, #8] 8015358: 605a str r2, [r3, #4] 801535a: 68fb ldr r3, [r7, #12] 801535c: 685a ldr r2, [r3, #4] 801535e: 69fb ldr r3, [r7, #28] 8015360: 3304 adds r3, #4 8015362: 429a cmp r2, r3 8015364: d103 bne.n 801536e 8015366: 69fb ldr r3, [r7, #28] 8015368: 68da ldr r2, [r3, #12] 801536a: 68fb ldr r3, [r7, #12] 801536c: 605a str r2, [r3, #4] 801536e: 69fb ldr r3, [r7, #28] 8015370: 2200 movs r2, #0 8015372: 615a str r2, [r3, #20] 8015374: 68fb ldr r3, [r7, #12] 8015376: 681b ldr r3, [r3, #0] 8015378: 1e5a subs r2, r3, #1 801537a: 68fb ldr r3, [r7, #12] 801537c: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxTCB ); 801537e: 69fb ldr r3, [r7, #28] 8015380: 6ada ldr r2, [r3, #44] @ 0x2c 8015382: 4b42 ldr r3, [pc, #264] @ (801548c ) 8015384: 681b ldr r3, [r3, #0] 8015386: 429a cmp r2, r3 8015388: d903 bls.n 8015392 801538a: 69fb ldr r3, [r7, #28] 801538c: 6adb ldr r3, [r3, #44] @ 0x2c 801538e: 4a3f ldr r2, [pc, #252] @ (801548c ) 8015390: 6013 str r3, [r2, #0] 8015392: 69fb ldr r3, [r7, #28] 8015394: 6ada ldr r2, [r3, #44] @ 0x2c 8015396: 493e ldr r1, [pc, #248] @ (8015490 ) 8015398: 4613 mov r3, r2 801539a: 009b lsls r3, r3, #2 801539c: 4413 add r3, r2 801539e: 009b lsls r3, r3, #2 80153a0: 440b add r3, r1 80153a2: 3304 adds r3, #4 80153a4: 681b ldr r3, [r3, #0] 80153a6: 60bb str r3, [r7, #8] 80153a8: 69fb ldr r3, [r7, #28] 80153aa: 68ba ldr r2, [r7, #8] 80153ac: 609a str r2, [r3, #8] 80153ae: 68bb ldr r3, [r7, #8] 80153b0: 689a ldr r2, [r3, #8] 80153b2: 69fb ldr r3, [r7, #28] 80153b4: 60da str r2, [r3, #12] 80153b6: 68bb ldr r3, [r7, #8] 80153b8: 689b ldr r3, [r3, #8] 80153ba: 69fa ldr r2, [r7, #28] 80153bc: 3204 adds r2, #4 80153be: 605a str r2, [r3, #4] 80153c0: 69fb ldr r3, [r7, #28] 80153c2: 1d1a adds r2, r3, #4 80153c4: 68bb ldr r3, [r7, #8] 80153c6: 609a str r2, [r3, #8] 80153c8: 69fb ldr r3, [r7, #28] 80153ca: 6ada ldr r2, [r3, #44] @ 0x2c 80153cc: 4613 mov r3, r2 80153ce: 009b lsls r3, r3, #2 80153d0: 4413 add r3, r2 80153d2: 009b lsls r3, r3, #2 80153d4: 4a2e ldr r2, [pc, #184] @ (8015490 ) 80153d6: 441a add r2, r3 80153d8: 69fb ldr r3, [r7, #28] 80153da: 615a str r2, [r3, #20] 80153dc: 69fb ldr r3, [r7, #28] 80153de: 6ada ldr r2, [r3, #44] @ 0x2c 80153e0: 492b ldr r1, [pc, #172] @ (8015490 ) 80153e2: 4613 mov r3, r2 80153e4: 009b lsls r3, r3, #2 80153e6: 4413 add r3, r2 80153e8: 009b lsls r3, r3, #2 80153ea: 440b add r3, r1 80153ec: 681b ldr r3, [r3, #0] 80153ee: 1c59 adds r1, r3, #1 80153f0: 4827 ldr r0, [pc, #156] @ (8015490 ) 80153f2: 4613 mov r3, r2 80153f4: 009b lsls r3, r3, #2 80153f6: 4413 add r3, r2 80153f8: 009b lsls r3, r3, #2 80153fa: 4403 add r3, r0 80153fc: 6019 str r1, [r3, #0] /* If the moved task has a priority higher than the current * task then a yield must be performed. */ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80153fe: 69fb ldr r3, [r7, #28] 8015400: 6ada ldr r2, [r3, #44] @ 0x2c 8015402: 4b24 ldr r3, [pc, #144] @ (8015494 ) 8015404: 681b ldr r3, [r3, #0] 8015406: 6adb ldr r3, [r3, #44] @ 0x2c 8015408: 429a cmp r2, r3 801540a: d902 bls.n 8015412 { xYieldPending = pdTRUE; 801540c: 4b22 ldr r3, [pc, #136] @ (8015498 ) 801540e: 2201 movs r2, #1 8015410: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8015412: 4b1d ldr r3, [pc, #116] @ (8015488 ) 8015414: 681b ldr r3, [r3, #0] 8015416: 2b00 cmp r3, #0 8015418: f47f af6f bne.w 80152fa { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 801541c: 69fb ldr r3, [r7, #28] 801541e: 2b00 cmp r3, #0 8015420: d001 beq.n 8015426 * which may have prevented the next unblock time from being * re-calculated, in which case re-calculate it now. Mainly * important for low power tickless implementations, where * this can prevent an unnecessary exit from low power * state. */ prvResetNextTaskUnblockTime(); 8015422: f000 fc55 bl 8015cd0 /* If any ticks occurred while the scheduler was suspended then * they should be processed now. This ensures the tick count does * not slip, and that any delayed tasks are resumed at the correct * time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8015426: 4b1d ldr r3, [pc, #116] @ (801549c ) 8015428: 681b ldr r3, [r3, #0] 801542a: 617b str r3, [r7, #20] if( xPendedCounts > ( TickType_t ) 0U ) 801542c: 697b ldr r3, [r7, #20] 801542e: 2b00 cmp r3, #0 8015430: d010 beq.n 8015454 { do { if( xTaskIncrementTick() != pdFALSE ) 8015432: f000 f853 bl 80154dc 8015436: 4603 mov r3, r0 8015438: 2b00 cmp r3, #0 801543a: d002 beq.n 8015442 { xYieldPending = pdTRUE; 801543c: 4b16 ldr r3, [pc, #88] @ (8015498 ) 801543e: 2201 movs r2, #1 8015440: 601a str r2, [r3, #0] else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8015442: 697b ldr r3, [r7, #20] 8015444: 3b01 subs r3, #1 8015446: 617b str r3, [r7, #20] } while( xPendedCounts > ( TickType_t ) 0U ); 8015448: 697b ldr r3, [r7, #20] 801544a: 2b00 cmp r3, #0 801544c: d1f1 bne.n 8015432 xPendedTicks = 0; 801544e: 4b13 ldr r3, [pc, #76] @ (801549c ) 8015450: 2200 movs r2, #0 8015452: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8015454: 4b10 ldr r3, [pc, #64] @ (8015498 ) 8015456: 681b ldr r3, [r3, #0] 8015458: 2b00 cmp r3, #0 801545a: d009 beq.n 8015470 { #if ( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 801545c: 2301 movs r3, #1 801545e: 61bb str r3, [r7, #24] } #endif taskYIELD_IF_USING_PREEMPTION(); 8015460: 4b0f ldr r3, [pc, #60] @ (80154a0 ) 8015462: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015466: 601a str r2, [r3, #0] 8015468: f3bf 8f4f dsb sy 801546c: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8015470: f001 ffa8 bl 80173c4 return xAlreadyYielded; 8015474: 69bb ldr r3, [r7, #24] } 8015476: 4618 mov r0, r3 8015478: 3720 adds r7, #32 801547a: 46bd mov sp, r7 801547c: bd80 pop {r7, pc} 801547e: bf00 nop 8015480: 200025c4 .word 0x200025c4 8015484: 2000259c .word 0x2000259c 8015488: 2000255c .word 0x2000255c 801548c: 200025a4 .word 0x200025a4 8015490: 200020cc .word 0x200020cc 8015494: 200020c8 .word 0x200020c8 8015498: 200025b0 .word 0x200025b0 801549c: 200025ac .word 0x200025ac 80154a0: e000ed04 .word 0xe000ed04 080154a4 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 80154a4: b480 push {r7} 80154a6: b083 sub sp, #12 80154a8: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 80154aa: 4b05 ldr r3, [pc, #20] @ (80154c0 ) 80154ac: 681b ldr r3, [r3, #0] 80154ae: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 80154b0: 687b ldr r3, [r7, #4] } 80154b2: 4618 mov r0, r3 80154b4: 370c adds r7, #12 80154b6: 46bd mov sp, r7 80154b8: f85d 7b04 ldr.w r7, [sp], #4 80154bc: 4770 bx lr 80154be: bf00 nop 80154c0: 200025a0 .word 0x200025a0 080154c4 : return xReturn; } /*-----------------------------------------------------------*/ UBaseType_t uxTaskGetNumberOfTasks( void ) { 80154c4: b480 push {r7} 80154c6: af00 add r7, sp, #0 /* A critical section is not required because the variables are of type * BaseType_t. */ return uxCurrentNumberOfTasks; 80154c8: 4b03 ldr r3, [pc, #12] @ (80154d8 ) 80154ca: 681b ldr r3, [r3, #0] } 80154cc: 4618 mov r0, r3 80154ce: 46bd mov sp, r7 80154d0: f85d 7b04 ldr.w r7, [sp], #4 80154d4: 4770 bx lr 80154d6: bf00 nop 80154d8: 2000259c .word 0x2000259c 080154dc : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 80154dc: b580 push {r7, lr} 80154de: b08a sub sp, #40 @ 0x28 80154e0: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 80154e2: 2300 movs r3, #0 80154e4: 627b str r3, [r7, #36] @ 0x24 /* Called by the portable layer each time a tick interrupt occurs. * Increments the tick then checks to see if the new tick value will cause any * tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 80154e6: 4b7e ldr r3, [pc, #504] @ (80156e0 ) 80154e8: 681b ldr r3, [r3, #0] 80154ea: 2b00 cmp r3, #0 80154ec: f040 80ee bne.w 80156cc { /* Minor optimisation. The tick count cannot change in this * block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 80154f0: 4b7c ldr r3, [pc, #496] @ (80156e4 ) 80154f2: 681b ldr r3, [r3, #0] 80154f4: 3301 adds r3, #1 80154f6: 623b str r3, [r7, #32] /* Increment the RTOS tick, switching the delayed and overflowed * delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 80154f8: 4a7a ldr r2, [pc, #488] @ (80156e4 ) 80154fa: 6a3b ldr r3, [r7, #32] 80154fc: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 80154fe: 6a3b ldr r3, [r7, #32] 8015500: 2b00 cmp r3, #0 8015502: d121 bne.n 8015548 { taskSWITCH_DELAYED_LISTS(); 8015504: 4b78 ldr r3, [pc, #480] @ (80156e8 ) 8015506: 681b ldr r3, [r3, #0] 8015508: 681b ldr r3, [r3, #0] 801550a: 2b00 cmp r3, #0 801550c: d00b beq.n 8015526 __asm volatile 801550e: f04f 0350 mov.w r3, #80 @ 0x50 8015512: f383 8811 msr BASEPRI, r3 8015516: f3bf 8f6f isb sy 801551a: f3bf 8f4f dsb sy 801551e: 607b str r3, [r7, #4] } 8015520: bf00 nop 8015522: bf00 nop 8015524: e7fd b.n 8015522 8015526: 4b70 ldr r3, [pc, #448] @ (80156e8 ) 8015528: 681b ldr r3, [r3, #0] 801552a: 61fb str r3, [r7, #28] 801552c: 4b6f ldr r3, [pc, #444] @ (80156ec ) 801552e: 681b ldr r3, [r3, #0] 8015530: 4a6d ldr r2, [pc, #436] @ (80156e8 ) 8015532: 6013 str r3, [r2, #0] 8015534: 4a6d ldr r2, [pc, #436] @ (80156ec ) 8015536: 69fb ldr r3, [r7, #28] 8015538: 6013 str r3, [r2, #0] 801553a: 4b6d ldr r3, [pc, #436] @ (80156f0 ) 801553c: 681b ldr r3, [r3, #0] 801553e: 3301 adds r3, #1 8015540: 4a6b ldr r2, [pc, #428] @ (80156f0 ) 8015542: 6013 str r3, [r2, #0] 8015544: f000 fbc4 bl 8015cd0 /* See if this tick has made a timeout expire. Tasks are stored in * the queue in the order of their wake time - meaning once one task * has been found whose block time has not expired there is no need to * look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8015548: 4b6a ldr r3, [pc, #424] @ (80156f4 ) 801554a: 681b ldr r3, [r3, #0] 801554c: 6a3a ldr r2, [r7, #32] 801554e: 429a cmp r2, r3 8015550: f0c0 80a7 bcc.w 80156a2 { for( ; ; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8015554: 4b64 ldr r3, [pc, #400] @ (80156e8 ) 8015556: 681b ldr r3, [r3, #0] 8015558: 681b ldr r3, [r3, #0] 801555a: 2b00 cmp r3, #0 801555c: d104 bne.n 8015568 /* The delayed list is empty. Set xNextTaskUnblockTime * to the maximum possible value so it is extremely * unlikely that the * if( xTickCount >= xNextTaskUnblockTime ) test will pass * next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 801555e: 4b65 ldr r3, [pc, #404] @ (80156f4 ) 8015560: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015564: 601a str r2, [r3, #0] break; 8015566: e09c b.n 80156a2 { /* The delayed list is not empty, get the value of the * item at the head of the delayed list. This is the time * at which the task at the head of the delayed list must * be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015568: 4b5f ldr r3, [pc, #380] @ (80156e8 ) 801556a: 681b ldr r3, [r3, #0] 801556c: 68db ldr r3, [r3, #12] 801556e: 68db ldr r3, [r3, #12] 8015570: 61bb str r3, [r7, #24] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8015572: 69bb ldr r3, [r7, #24] 8015574: 685b ldr r3, [r3, #4] 8015576: 617b str r3, [r7, #20] if( xConstTickCount < xItemValue ) 8015578: 6a3a ldr r2, [r7, #32] 801557a: 697b ldr r3, [r7, #20] 801557c: 429a cmp r2, r3 801557e: d203 bcs.n 8015588 /* It is not time to unblock this item yet, but the * item value is the time at which the task at the head * of the blocked list must be removed from the Blocked * state - so record the item value in * xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 8015580: 4a5c ldr r2, [pc, #368] @ (80156f4 ) 8015582: 697b ldr r3, [r7, #20] 8015584: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */ 8015586: e08c b.n 80156a2 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 8015588: 69bb ldr r3, [r7, #24] 801558a: 695b ldr r3, [r3, #20] 801558c: 613b str r3, [r7, #16] 801558e: 69bb ldr r3, [r7, #24] 8015590: 689b ldr r3, [r3, #8] 8015592: 69ba ldr r2, [r7, #24] 8015594: 68d2 ldr r2, [r2, #12] 8015596: 609a str r2, [r3, #8] 8015598: 69bb ldr r3, [r7, #24] 801559a: 68db ldr r3, [r3, #12] 801559c: 69ba ldr r2, [r7, #24] 801559e: 6892 ldr r2, [r2, #8] 80155a0: 605a str r2, [r3, #4] 80155a2: 693b ldr r3, [r7, #16] 80155a4: 685a ldr r2, [r3, #4] 80155a6: 69bb ldr r3, [r7, #24] 80155a8: 3304 adds r3, #4 80155aa: 429a cmp r2, r3 80155ac: d103 bne.n 80155b6 80155ae: 69bb ldr r3, [r7, #24] 80155b0: 68da ldr r2, [r3, #12] 80155b2: 693b ldr r3, [r7, #16] 80155b4: 605a str r2, [r3, #4] 80155b6: 69bb ldr r3, [r7, #24] 80155b8: 2200 movs r2, #0 80155ba: 615a str r2, [r3, #20] 80155bc: 693b ldr r3, [r7, #16] 80155be: 681b ldr r3, [r3, #0] 80155c0: 1e5a subs r2, r3, #1 80155c2: 693b ldr r3, [r7, #16] 80155c4: 601a str r2, [r3, #0] /* Is the task waiting on an event also? If so remove * it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 80155c6: 69bb ldr r3, [r7, #24] 80155c8: 6a9b ldr r3, [r3, #40] @ 0x28 80155ca: 2b00 cmp r3, #0 80155cc: d01e beq.n 801560c { listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); 80155ce: 69bb ldr r3, [r7, #24] 80155d0: 6a9b ldr r3, [r3, #40] @ 0x28 80155d2: 60fb str r3, [r7, #12] 80155d4: 69bb ldr r3, [r7, #24] 80155d6: 69db ldr r3, [r3, #28] 80155d8: 69ba ldr r2, [r7, #24] 80155da: 6a12 ldr r2, [r2, #32] 80155dc: 609a str r2, [r3, #8] 80155de: 69bb ldr r3, [r7, #24] 80155e0: 6a1b ldr r3, [r3, #32] 80155e2: 69ba ldr r2, [r7, #24] 80155e4: 69d2 ldr r2, [r2, #28] 80155e6: 605a str r2, [r3, #4] 80155e8: 68fb ldr r3, [r7, #12] 80155ea: 685a ldr r2, [r3, #4] 80155ec: 69bb ldr r3, [r7, #24] 80155ee: 3318 adds r3, #24 80155f0: 429a cmp r2, r3 80155f2: d103 bne.n 80155fc 80155f4: 69bb ldr r3, [r7, #24] 80155f6: 6a1a ldr r2, [r3, #32] 80155f8: 68fb ldr r3, [r7, #12] 80155fa: 605a str r2, [r3, #4] 80155fc: 69bb ldr r3, [r7, #24] 80155fe: 2200 movs r2, #0 8015600: 629a str r2, [r3, #40] @ 0x28 8015602: 68fb ldr r3, [r7, #12] 8015604: 681b ldr r3, [r3, #0] 8015606: 1e5a subs r2, r3, #1 8015608: 68fb ldr r3, [r7, #12] 801560a: 601a str r2, [r3, #0] mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready * list. */ prvAddTaskToReadyList( pxTCB ); 801560c: 69bb ldr r3, [r7, #24] 801560e: 6ada ldr r2, [r3, #44] @ 0x2c 8015610: 4b39 ldr r3, [pc, #228] @ (80156f8 ) 8015612: 681b ldr r3, [r3, #0] 8015614: 429a cmp r2, r3 8015616: d903 bls.n 8015620 8015618: 69bb ldr r3, [r7, #24] 801561a: 6adb ldr r3, [r3, #44] @ 0x2c 801561c: 4a36 ldr r2, [pc, #216] @ (80156f8 ) 801561e: 6013 str r3, [r2, #0] 8015620: 69bb ldr r3, [r7, #24] 8015622: 6ada ldr r2, [r3, #44] @ 0x2c 8015624: 4935 ldr r1, [pc, #212] @ (80156fc ) 8015626: 4613 mov r3, r2 8015628: 009b lsls r3, r3, #2 801562a: 4413 add r3, r2 801562c: 009b lsls r3, r3, #2 801562e: 440b add r3, r1 8015630: 3304 adds r3, #4 8015632: 681b ldr r3, [r3, #0] 8015634: 60bb str r3, [r7, #8] 8015636: 69bb ldr r3, [r7, #24] 8015638: 68ba ldr r2, [r7, #8] 801563a: 609a str r2, [r3, #8] 801563c: 68bb ldr r3, [r7, #8] 801563e: 689a ldr r2, [r3, #8] 8015640: 69bb ldr r3, [r7, #24] 8015642: 60da str r2, [r3, #12] 8015644: 68bb ldr r3, [r7, #8] 8015646: 689b ldr r3, [r3, #8] 8015648: 69ba ldr r2, [r7, #24] 801564a: 3204 adds r2, #4 801564c: 605a str r2, [r3, #4] 801564e: 69bb ldr r3, [r7, #24] 8015650: 1d1a adds r2, r3, #4 8015652: 68bb ldr r3, [r7, #8] 8015654: 609a str r2, [r3, #8] 8015656: 69bb ldr r3, [r7, #24] 8015658: 6ada ldr r2, [r3, #44] @ 0x2c 801565a: 4613 mov r3, r2 801565c: 009b lsls r3, r3, #2 801565e: 4413 add r3, r2 8015660: 009b lsls r3, r3, #2 8015662: 4a26 ldr r2, [pc, #152] @ (80156fc ) 8015664: 441a add r2, r3 8015666: 69bb ldr r3, [r7, #24] 8015668: 615a str r2, [r3, #20] 801566a: 69bb ldr r3, [r7, #24] 801566c: 6ada ldr r2, [r3, #44] @ 0x2c 801566e: 4923 ldr r1, [pc, #140] @ (80156fc ) 8015670: 4613 mov r3, r2 8015672: 009b lsls r3, r3, #2 8015674: 4413 add r3, r2 8015676: 009b lsls r3, r3, #2 8015678: 440b add r3, r1 801567a: 681b ldr r3, [r3, #0] 801567c: 1c59 adds r1, r3, #1 801567e: 481f ldr r0, [pc, #124] @ (80156fc ) 8015680: 4613 mov r3, r2 8015682: 009b lsls r3, r3, #2 8015684: 4413 add r3, r2 8015686: 009b lsls r3, r3, #2 8015688: 4403 add r3, r0 801568a: 6019 str r1, [r3, #0] * task. * The case of equal priority tasks sharing * processing time (which happens when both * preemption and time slicing are on) is * handled below.*/ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 801568c: 69bb ldr r3, [r7, #24] 801568e: 6ada ldr r2, [r3, #44] @ 0x2c 8015690: 4b1b ldr r3, [pc, #108] @ (8015700 ) 8015692: 681b ldr r3, [r3, #0] 8015694: 6adb ldr r3, [r3, #44] @ 0x2c 8015696: 429a cmp r2, r3 8015698: f67f af5c bls.w 8015554 { xSwitchRequired = pdTRUE; 801569c: 2301 movs r3, #1 801569e: 627b str r3, [r7, #36] @ 0x24 if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80156a0: e758 b.n 8015554 /* Tasks of equal priority to the currently running task will share * processing time (time slice) if preemption is on, and the application * writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 80156a2: 4b17 ldr r3, [pc, #92] @ (8015700 ) 80156a4: 681b ldr r3, [r3, #0] 80156a6: 6ada ldr r2, [r3, #44] @ 0x2c 80156a8: 4914 ldr r1, [pc, #80] @ (80156fc ) 80156aa: 4613 mov r3, r2 80156ac: 009b lsls r3, r3, #2 80156ae: 4413 add r3, r2 80156b0: 009b lsls r3, r3, #2 80156b2: 440b add r3, r1 80156b4: 681b ldr r3, [r3, #0] 80156b6: 2b01 cmp r3, #1 80156b8: d901 bls.n 80156be { xSwitchRequired = pdTRUE; 80156ba: 2301 movs r3, #1 80156bc: 627b str r3, [r7, #36] @ 0x24 } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 80156be: 4b11 ldr r3, [pc, #68] @ (8015704 ) 80156c0: 681b ldr r3, [r3, #0] 80156c2: 2b00 cmp r3, #0 80156c4: d007 beq.n 80156d6 { xSwitchRequired = pdTRUE; 80156c6: 2301 movs r3, #1 80156c8: 627b str r3, [r7, #36] @ 0x24 80156ca: e004 b.n 80156d6 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 80156cc: 4b0e ldr r3, [pc, #56] @ (8015708 ) 80156ce: 681b ldr r3, [r3, #0] 80156d0: 3301 adds r3, #1 80156d2: 4a0d ldr r2, [pc, #52] @ (8015708 ) 80156d4: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 80156d6: 6a7b ldr r3, [r7, #36] @ 0x24 } 80156d8: 4618 mov r0, r3 80156da: 3728 adds r7, #40 @ 0x28 80156dc: 46bd mov sp, r7 80156de: bd80 pop {r7, pc} 80156e0: 200025c4 .word 0x200025c4 80156e4: 200025a0 .word 0x200025a0 80156e8: 20002554 .word 0x20002554 80156ec: 20002558 .word 0x20002558 80156f0: 200025b4 .word 0x200025b4 80156f4: 200025bc .word 0x200025bc 80156f8: 200025a4 .word 0x200025a4 80156fc: 200020cc .word 0x200020cc 8015700: 200020c8 .word 0x200020c8 8015704: 200025b0 .word 0x200025b0 8015708: 200025ac .word 0x200025ac 0801570c : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 801570c: b480 push {r7} 801570e: b085 sub sp, #20 8015710: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) 0U ) 8015712: 4b28 ldr r3, [pc, #160] @ (80157b4 ) 8015714: 681b ldr r3, [r3, #0] 8015716: 2b00 cmp r3, #0 8015718: d003 beq.n 8015722 { /* The scheduler is currently suspended - do not allow a context * switch. */ xYieldPending = pdTRUE; 801571a: 4b27 ldr r3, [pc, #156] @ (80157b8 ) 801571c: 2201 movs r2, #1 801571e: 601a str r2, [r3, #0] * Block specific to this task. */ configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); } #endif } } 8015720: e041 b.n 80157a6 xYieldPending = pdFALSE; 8015722: 4b25 ldr r3, [pc, #148] @ (80157b8 ) 8015724: 2200 movs r2, #0 8015726: 601a str r2, [r3, #0] taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015728: 4b24 ldr r3, [pc, #144] @ (80157bc ) 801572a: 681b ldr r3, [r3, #0] 801572c: 60fb str r3, [r7, #12] 801572e: e011 b.n 8015754 8015730: 68fb ldr r3, [r7, #12] 8015732: 2b00 cmp r3, #0 8015734: d10b bne.n 801574e __asm volatile 8015736: f04f 0350 mov.w r3, #80 @ 0x50 801573a: f383 8811 msr BASEPRI, r3 801573e: f3bf 8f6f isb sy 8015742: f3bf 8f4f dsb sy 8015746: 607b str r3, [r7, #4] } 8015748: bf00 nop 801574a: bf00 nop 801574c: e7fd b.n 801574a 801574e: 68fb ldr r3, [r7, #12] 8015750: 3b01 subs r3, #1 8015752: 60fb str r3, [r7, #12] 8015754: 491a ldr r1, [pc, #104] @ (80157c0 ) 8015756: 68fa ldr r2, [r7, #12] 8015758: 4613 mov r3, r2 801575a: 009b lsls r3, r3, #2 801575c: 4413 add r3, r2 801575e: 009b lsls r3, r3, #2 8015760: 440b add r3, r1 8015762: 681b ldr r3, [r3, #0] 8015764: 2b00 cmp r3, #0 8015766: d0e3 beq.n 8015730 8015768: 68fa ldr r2, [r7, #12] 801576a: 4613 mov r3, r2 801576c: 009b lsls r3, r3, #2 801576e: 4413 add r3, r2 8015770: 009b lsls r3, r3, #2 8015772: 4a13 ldr r2, [pc, #76] @ (80157c0 ) 8015774: 4413 add r3, r2 8015776: 60bb str r3, [r7, #8] 8015778: 68bb ldr r3, [r7, #8] 801577a: 685b ldr r3, [r3, #4] 801577c: 685a ldr r2, [r3, #4] 801577e: 68bb ldr r3, [r7, #8] 8015780: 605a str r2, [r3, #4] 8015782: 68bb ldr r3, [r7, #8] 8015784: 685a ldr r2, [r3, #4] 8015786: 68bb ldr r3, [r7, #8] 8015788: 3308 adds r3, #8 801578a: 429a cmp r2, r3 801578c: d103 bne.n 8015796 801578e: 68bb ldr r3, [r7, #8] 8015790: 68da ldr r2, [r3, #12] 8015792: 68bb ldr r3, [r7, #8] 8015794: 605a str r2, [r3, #4] 8015796: 68bb ldr r3, [r7, #8] 8015798: 685b ldr r3, [r3, #4] 801579a: 68db ldr r3, [r3, #12] 801579c: 4a09 ldr r2, [pc, #36] @ (80157c4 ) 801579e: 6013 str r3, [r2, #0] 80157a0: 4a06 ldr r2, [pc, #24] @ (80157bc ) 80157a2: 68fb ldr r3, [r7, #12] 80157a4: 6013 str r3, [r2, #0] } 80157a6: bf00 nop 80157a8: 3714 adds r7, #20 80157aa: 46bd mov sp, r7 80157ac: f85d 7b04 ldr.w r7, [sp], #4 80157b0: 4770 bx lr 80157b2: bf00 nop 80157b4: 200025c4 .word 0x200025c4 80157b8: 200025b0 .word 0x200025b0 80157bc: 200025a4 .word 0x200025a4 80157c0: 200020cc .word 0x200020cc 80157c4: 200020c8 .word 0x200020c8 080157c8 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 80157c8: b580 push {r7, lr} 80157ca: b084 sub sp, #16 80157cc: af00 add r7, sp, #0 80157ce: 6078 str r0, [r7, #4] 80157d0: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 80157d2: 687b ldr r3, [r7, #4] 80157d4: 2b00 cmp r3, #0 80157d6: d10b bne.n 80157f0 __asm volatile 80157d8: f04f 0350 mov.w r3, #80 @ 0x50 80157dc: f383 8811 msr BASEPRI, r3 80157e0: f3bf 8f6f isb sy 80157e4: f3bf 8f4f dsb sy 80157e8: 60fb str r3, [r7, #12] } 80157ea: bf00 nop 80157ec: bf00 nop 80157ee: e7fd b.n 80157ec * xItemValue = ( configMAX_PRIORITIES - uxPriority ) * Therefore, the event list is sorted in descending priority order. * * The queue that contains the event list is locked, preventing * simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80157f0: 4b07 ldr r3, [pc, #28] @ (8015810 ) 80157f2: 681b ldr r3, [r3, #0] 80157f4: 3318 adds r3, #24 80157f6: 4619 mov r1, r3 80157f8: 6878 ldr r0, [r7, #4] 80157fa: f7fe f900 bl 80139fe prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 80157fe: 2101 movs r1, #1 8015800: 6838 ldr r0, [r7, #0] 8015802: f001 f92b bl 8016a5c } 8015806: bf00 nop 8015808: 3710 adds r7, #16 801580a: 46bd mov sp, r7 801580c: bd80 pop {r7, pc} 801580e: bf00 nop 8015810: 200020c8 .word 0x200020c8 08015814 : #if ( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8015814: b580 push {r7, lr} 8015816: b086 sub sp, #24 8015818: af00 add r7, sp, #0 801581a: 60f8 str r0, [r7, #12] 801581c: 60b9 str r1, [r7, #8] 801581e: 607a str r2, [r7, #4] configASSERT( pxEventList ); 8015820: 68fb ldr r3, [r7, #12] 8015822: 2b00 cmp r3, #0 8015824: d10b bne.n 801583e __asm volatile 8015826: f04f 0350 mov.w r3, #80 @ 0x50 801582a: f383 8811 msr BASEPRI, r3 801582e: f3bf 8f6f isb sy 8015832: f3bf 8f4f dsb sy 8015836: 613b str r3, [r7, #16] } 8015838: bf00 nop 801583a: bf00 nop 801583c: e7fd b.n 801583a /* Place the event list item of the TCB in the appropriate event list. * In this case it is assume that this is the only task that is going to * be waiting on this event list, so the faster vListInsertEnd() function * can be used in place of vListInsert. */ listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 801583e: 68fb ldr r3, [r7, #12] 8015840: 685b ldr r3, [r3, #4] 8015842: 617b str r3, [r7, #20] 8015844: 4b15 ldr r3, [pc, #84] @ (801589c ) 8015846: 681b ldr r3, [r3, #0] 8015848: 697a ldr r2, [r7, #20] 801584a: 61da str r2, [r3, #28] 801584c: 4b13 ldr r3, [pc, #76] @ (801589c ) 801584e: 681b ldr r3, [r3, #0] 8015850: 697a ldr r2, [r7, #20] 8015852: 6892 ldr r2, [r2, #8] 8015854: 621a str r2, [r3, #32] 8015856: 4b11 ldr r3, [pc, #68] @ (801589c ) 8015858: 681a ldr r2, [r3, #0] 801585a: 697b ldr r3, [r7, #20] 801585c: 689b ldr r3, [r3, #8] 801585e: 3218 adds r2, #24 8015860: 605a str r2, [r3, #4] 8015862: 4b0e ldr r3, [pc, #56] @ (801589c ) 8015864: 681b ldr r3, [r3, #0] 8015866: f103 0218 add.w r2, r3, #24 801586a: 697b ldr r3, [r7, #20] 801586c: 609a str r2, [r3, #8] 801586e: 4b0b ldr r3, [pc, #44] @ (801589c ) 8015870: 681b ldr r3, [r3, #0] 8015872: 68fa ldr r2, [r7, #12] 8015874: 629a str r2, [r3, #40] @ 0x28 8015876: 68fb ldr r3, [r7, #12] 8015878: 681b ldr r3, [r3, #0] 801587a: 1c5a adds r2, r3, #1 801587c: 68fb ldr r3, [r7, #12] 801587e: 601a str r2, [r3, #0] /* If the task should block indefinitely then set the block time to a * value that will be recognised as an indefinite delay inside the * prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 8015880: 687b ldr r3, [r7, #4] 8015882: 2b00 cmp r3, #0 8015884: d002 beq.n 801588c { xTicksToWait = portMAX_DELAY; 8015886: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801588a: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 801588c: 6879 ldr r1, [r7, #4] 801588e: 68b8 ldr r0, [r7, #8] 8015890: f001 f8e4 bl 8016a5c } 8015894: bf00 nop 8015896: 3718 adds r7, #24 8015898: 46bd mov sp, r7 801589a: bd80 pop {r7, pc} 801589c: 200020c8 .word 0x200020c8 080158a0 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 80158a0: b480 push {r7} 80158a2: b08b sub sp, #44 @ 0x2c 80158a4: af00 add r7, sp, #0 80158a6: 6078 str r0, [r7, #4] * get called - the lock count on the queue will get modified instead. This * means exclusive access to the event list is guaranteed here. * * This function assumes that a check has already been made to ensure that * pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80158a8: 687b ldr r3, [r7, #4] 80158aa: 68db ldr r3, [r3, #12] 80158ac: 68db ldr r3, [r3, #12] 80158ae: 623b str r3, [r7, #32] configASSERT( pxUnblockedTCB ); 80158b0: 6a3b ldr r3, [r7, #32] 80158b2: 2b00 cmp r3, #0 80158b4: d10b bne.n 80158ce __asm volatile 80158b6: f04f 0350 mov.w r3, #80 @ 0x50 80158ba: f383 8811 msr BASEPRI, r3 80158be: f3bf 8f6f isb sy 80158c2: f3bf 8f4f dsb sy 80158c6: 60fb str r3, [r7, #12] } 80158c8: bf00 nop 80158ca: bf00 nop 80158cc: e7fd b.n 80158ca listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) ); 80158ce: 6a3b ldr r3, [r7, #32] 80158d0: 6a9b ldr r3, [r3, #40] @ 0x28 80158d2: 61fb str r3, [r7, #28] 80158d4: 6a3b ldr r3, [r7, #32] 80158d6: 69db ldr r3, [r3, #28] 80158d8: 6a3a ldr r2, [r7, #32] 80158da: 6a12 ldr r2, [r2, #32] 80158dc: 609a str r2, [r3, #8] 80158de: 6a3b ldr r3, [r7, #32] 80158e0: 6a1b ldr r3, [r3, #32] 80158e2: 6a3a ldr r2, [r7, #32] 80158e4: 69d2 ldr r2, [r2, #28] 80158e6: 605a str r2, [r3, #4] 80158e8: 69fb ldr r3, [r7, #28] 80158ea: 685a ldr r2, [r3, #4] 80158ec: 6a3b ldr r3, [r7, #32] 80158ee: 3318 adds r3, #24 80158f0: 429a cmp r2, r3 80158f2: d103 bne.n 80158fc 80158f4: 6a3b ldr r3, [r7, #32] 80158f6: 6a1a ldr r2, [r3, #32] 80158f8: 69fb ldr r3, [r7, #28] 80158fa: 605a str r2, [r3, #4] 80158fc: 6a3b ldr r3, [r7, #32] 80158fe: 2200 movs r2, #0 8015900: 629a str r2, [r3, #40] @ 0x28 8015902: 69fb ldr r3, [r7, #28] 8015904: 681b ldr r3, [r3, #0] 8015906: 1e5a subs r2, r3, #1 8015908: 69fb ldr r3, [r7, #28] 801590a: 601a str r2, [r3, #0] if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 801590c: 4b4a ldr r3, [pc, #296] @ (8015a38 ) 801590e: 681b ldr r3, [r3, #0] 8015910: 2b00 cmp r3, #0 8015912: d15f bne.n 80159d4 { listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); 8015914: 6a3b ldr r3, [r7, #32] 8015916: 695b ldr r3, [r3, #20] 8015918: 617b str r3, [r7, #20] 801591a: 6a3b ldr r3, [r7, #32] 801591c: 689b ldr r3, [r3, #8] 801591e: 6a3a ldr r2, [r7, #32] 8015920: 68d2 ldr r2, [r2, #12] 8015922: 609a str r2, [r3, #8] 8015924: 6a3b ldr r3, [r7, #32] 8015926: 68db ldr r3, [r3, #12] 8015928: 6a3a ldr r2, [r7, #32] 801592a: 6892 ldr r2, [r2, #8] 801592c: 605a str r2, [r3, #4] 801592e: 697b ldr r3, [r7, #20] 8015930: 685a ldr r2, [r3, #4] 8015932: 6a3b ldr r3, [r7, #32] 8015934: 3304 adds r3, #4 8015936: 429a cmp r2, r3 8015938: d103 bne.n 8015942 801593a: 6a3b ldr r3, [r7, #32] 801593c: 68da ldr r2, [r3, #12] 801593e: 697b ldr r3, [r7, #20] 8015940: 605a str r2, [r3, #4] 8015942: 6a3b ldr r3, [r7, #32] 8015944: 2200 movs r2, #0 8015946: 615a str r2, [r3, #20] 8015948: 697b ldr r3, [r7, #20] 801594a: 681b ldr r3, [r3, #0] 801594c: 1e5a subs r2, r3, #1 801594e: 697b ldr r3, [r7, #20] 8015950: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxUnblockedTCB ); 8015952: 6a3b ldr r3, [r7, #32] 8015954: 6ada ldr r2, [r3, #44] @ 0x2c 8015956: 4b39 ldr r3, [pc, #228] @ (8015a3c ) 8015958: 681b ldr r3, [r3, #0] 801595a: 429a cmp r2, r3 801595c: d903 bls.n 8015966 801595e: 6a3b ldr r3, [r7, #32] 8015960: 6adb ldr r3, [r3, #44] @ 0x2c 8015962: 4a36 ldr r2, [pc, #216] @ (8015a3c ) 8015964: 6013 str r3, [r2, #0] 8015966: 6a3b ldr r3, [r7, #32] 8015968: 6ada ldr r2, [r3, #44] @ 0x2c 801596a: 4935 ldr r1, [pc, #212] @ (8015a40 ) 801596c: 4613 mov r3, r2 801596e: 009b lsls r3, r3, #2 8015970: 4413 add r3, r2 8015972: 009b lsls r3, r3, #2 8015974: 440b add r3, r1 8015976: 3304 adds r3, #4 8015978: 681b ldr r3, [r3, #0] 801597a: 613b str r3, [r7, #16] 801597c: 6a3b ldr r3, [r7, #32] 801597e: 693a ldr r2, [r7, #16] 8015980: 609a str r2, [r3, #8] 8015982: 693b ldr r3, [r7, #16] 8015984: 689a ldr r2, [r3, #8] 8015986: 6a3b ldr r3, [r7, #32] 8015988: 60da str r2, [r3, #12] 801598a: 693b ldr r3, [r7, #16] 801598c: 689b ldr r3, [r3, #8] 801598e: 6a3a ldr r2, [r7, #32] 8015990: 3204 adds r2, #4 8015992: 605a str r2, [r3, #4] 8015994: 6a3b ldr r3, [r7, #32] 8015996: 1d1a adds r2, r3, #4 8015998: 693b ldr r3, [r7, #16] 801599a: 609a str r2, [r3, #8] 801599c: 6a3b ldr r3, [r7, #32] 801599e: 6ada ldr r2, [r3, #44] @ 0x2c 80159a0: 4613 mov r3, r2 80159a2: 009b lsls r3, r3, #2 80159a4: 4413 add r3, r2 80159a6: 009b lsls r3, r3, #2 80159a8: 4a25 ldr r2, [pc, #148] @ (8015a40 ) 80159aa: 441a add r2, r3 80159ac: 6a3b ldr r3, [r7, #32] 80159ae: 615a str r2, [r3, #20] 80159b0: 6a3b ldr r3, [r7, #32] 80159b2: 6ada ldr r2, [r3, #44] @ 0x2c 80159b4: 4922 ldr r1, [pc, #136] @ (8015a40 ) 80159b6: 4613 mov r3, r2 80159b8: 009b lsls r3, r3, #2 80159ba: 4413 add r3, r2 80159bc: 009b lsls r3, r3, #2 80159be: 440b add r3, r1 80159c0: 681b ldr r3, [r3, #0] 80159c2: 1c59 adds r1, r3, #1 80159c4: 481e ldr r0, [pc, #120] @ (8015a40 ) 80159c6: 4613 mov r3, r2 80159c8: 009b lsls r3, r3, #2 80159ca: 4413 add r3, r2 80159cc: 009b lsls r3, r3, #2 80159ce: 4403 add r3, r0 80159d0: 6019 str r1, [r3, #0] 80159d2: e01b b.n 8015a0c } else { /* The delayed and ready lists cannot be accessed, so hold this task * pending until the scheduler is resumed. */ listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 80159d4: 4b1b ldr r3, [pc, #108] @ (8015a44 ) 80159d6: 685b ldr r3, [r3, #4] 80159d8: 61bb str r3, [r7, #24] 80159da: 6a3b ldr r3, [r7, #32] 80159dc: 69ba ldr r2, [r7, #24] 80159de: 61da str r2, [r3, #28] 80159e0: 69bb ldr r3, [r7, #24] 80159e2: 689a ldr r2, [r3, #8] 80159e4: 6a3b ldr r3, [r7, #32] 80159e6: 621a str r2, [r3, #32] 80159e8: 69bb ldr r3, [r7, #24] 80159ea: 689b ldr r3, [r3, #8] 80159ec: 6a3a ldr r2, [r7, #32] 80159ee: 3218 adds r2, #24 80159f0: 605a str r2, [r3, #4] 80159f2: 6a3b ldr r3, [r7, #32] 80159f4: f103 0218 add.w r2, r3, #24 80159f8: 69bb ldr r3, [r7, #24] 80159fa: 609a str r2, [r3, #8] 80159fc: 6a3b ldr r3, [r7, #32] 80159fe: 4a11 ldr r2, [pc, #68] @ (8015a44 ) 8015a00: 629a str r2, [r3, #40] @ 0x28 8015a02: 4b10 ldr r3, [pc, #64] @ (8015a44 ) 8015a04: 681b ldr r3, [r3, #0] 8015a06: 3301 adds r3, #1 8015a08: 4a0e ldr r2, [pc, #56] @ (8015a44 ) 8015a0a: 6013 str r3, [r2, #0] } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 8015a0c: 6a3b ldr r3, [r7, #32] 8015a0e: 6ada ldr r2, [r3, #44] @ 0x2c 8015a10: 4b0d ldr r3, [pc, #52] @ (8015a48 ) 8015a12: 681b ldr r3, [r3, #0] 8015a14: 6adb ldr r3, [r3, #44] @ 0x2c 8015a16: 429a cmp r2, r3 8015a18: d905 bls.n 8015a26 { /* Return true if the task removed from the event list has a higher * priority than the calling task. This allows the calling task to know if * it should force a context switch now. */ xReturn = pdTRUE; 8015a1a: 2301 movs r3, #1 8015a1c: 627b str r3, [r7, #36] @ 0x24 /* Mark that a yield is pending in case the user is not using the * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 8015a1e: 4b0b ldr r3, [pc, #44] @ (8015a4c ) 8015a20: 2201 movs r2, #1 8015a22: 601a str r2, [r3, #0] 8015a24: e001 b.n 8015a2a } else { xReturn = pdFALSE; 8015a26: 2300 movs r3, #0 8015a28: 627b str r3, [r7, #36] @ 0x24 } return xReturn; 8015a2a: 6a7b ldr r3, [r7, #36] @ 0x24 } 8015a2c: 4618 mov r0, r3 8015a2e: 372c adds r7, #44 @ 0x2c 8015a30: 46bd mov sp, r7 8015a32: f85d 7b04 ldr.w r7, [sp], #4 8015a36: 4770 bx lr 8015a38: 200025c4 .word 0x200025c4 8015a3c: 200025a4 .word 0x200025a4 8015a40: 200020cc .word 0x200020cc 8015a44: 2000255c .word 0x2000255c 8015a48: 200020c8 .word 0x200020c8 8015a4c: 200025b0 .word 0x200025b0 08015a50 : taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8015a50: b480 push {r7} 8015a52: b083 sub sp, #12 8015a54: af00 add r7, sp, #0 8015a56: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 8015a58: 4b06 ldr r3, [pc, #24] @ (8015a74 ) 8015a5a: 681a ldr r2, [r3, #0] 8015a5c: 687b ldr r3, [r7, #4] 8015a5e: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8015a60: 4b05 ldr r3, [pc, #20] @ (8015a78 ) 8015a62: 681a ldr r2, [r3, #0] 8015a64: 687b ldr r3, [r7, #4] 8015a66: 605a str r2, [r3, #4] } 8015a68: bf00 nop 8015a6a: 370c adds r7, #12 8015a6c: 46bd mov sp, r7 8015a6e: f85d 7b04 ldr.w r7, [sp], #4 8015a72: 4770 bx lr 8015a74: 200025b4 .word 0x200025b4 8015a78: 200025a0 .word 0x200025a0 08015a7c : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8015a7c: b580 push {r7, lr} 8015a7e: b088 sub sp, #32 8015a80: af00 add r7, sp, #0 8015a82: 6078 str r0, [r7, #4] 8015a84: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 8015a86: 687b ldr r3, [r7, #4] 8015a88: 2b00 cmp r3, #0 8015a8a: d10b bne.n 8015aa4 __asm volatile 8015a8c: f04f 0350 mov.w r3, #80 @ 0x50 8015a90: f383 8811 msr BASEPRI, r3 8015a94: f3bf 8f6f isb sy 8015a98: f3bf 8f4f dsb sy 8015a9c: 613b str r3, [r7, #16] } 8015a9e: bf00 nop 8015aa0: bf00 nop 8015aa2: e7fd b.n 8015aa0 configASSERT( pxTicksToWait ); 8015aa4: 683b ldr r3, [r7, #0] 8015aa6: 2b00 cmp r3, #0 8015aa8: d10b bne.n 8015ac2 __asm volatile 8015aaa: f04f 0350 mov.w r3, #80 @ 0x50 8015aae: f383 8811 msr BASEPRI, r3 8015ab2: f3bf 8f6f isb sy 8015ab6: f3bf 8f4f dsb sy 8015aba: 60fb str r3, [r7, #12] } 8015abc: bf00 nop 8015abe: bf00 nop 8015ac0: e7fd b.n 8015abe taskENTER_CRITICAL(); 8015ac2: f001 fc4d bl 8017360 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 8015ac6: 4b1f ldr r3, [pc, #124] @ (8015b44 ) 8015ac8: 681b ldr r3, [r3, #0] 8015aca: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8015acc: 687b ldr r3, [r7, #4] 8015ace: 685b ldr r3, [r3, #4] 8015ad0: 69ba ldr r2, [r7, #24] 8015ad2: 1ad3 subs r3, r2, r3 8015ad4: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 8015ad6: 683b ldr r3, [r7, #0] 8015ad8: 681b ldr r3, [r3, #0] 8015ada: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015ade: d102 bne.n 8015ae6 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time * specified is the maximum block time then the task should block * indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8015ae0: 2300 movs r3, #0 8015ae2: 61fb str r3, [r7, #28] 8015ae4: e026 b.n 8015b34 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 8015ae6: 687b ldr r3, [r7, #4] 8015ae8: 681a ldr r2, [r3, #0] 8015aea: 4b17 ldr r3, [pc, #92] @ (8015b48 ) 8015aec: 681b ldr r3, [r3, #0] 8015aee: 429a cmp r2, r3 8015af0: d00a beq.n 8015b08 8015af2: 687b ldr r3, [r7, #4] 8015af4: 685b ldr r3, [r3, #4] 8015af6: 69ba ldr r2, [r7, #24] 8015af8: 429a cmp r2, r3 8015afa: d305 bcc.n 8015b08 /* The tick count is greater than the time at which * vTaskSetTimeout() was called, but has also overflowed since * vTaskSetTimeOut() was called. It must have wrapped all the way * around and gone past again. This passed since vTaskSetTimeout() * was called. */ xReturn = pdTRUE; 8015afc: 2301 movs r3, #1 8015afe: 61fb str r3, [r7, #28] *pxTicksToWait = ( TickType_t ) 0; 8015b00: 683b ldr r3, [r7, #0] 8015b02: 2200 movs r2, #0 8015b04: 601a str r2, [r3, #0] 8015b06: e015 b.n 8015b34 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 8015b08: 683b ldr r3, [r7, #0] 8015b0a: 681b ldr r3, [r3, #0] 8015b0c: 697a ldr r2, [r7, #20] 8015b0e: 429a cmp r2, r3 8015b10: d20b bcs.n 8015b2a { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 8015b12: 683b ldr r3, [r7, #0] 8015b14: 681a ldr r2, [r3, #0] 8015b16: 697b ldr r3, [r7, #20] 8015b18: 1ad2 subs r2, r2, r3 8015b1a: 683b ldr r3, [r7, #0] 8015b1c: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 8015b1e: 6878 ldr r0, [r7, #4] 8015b20: f7ff ff96 bl 8015a50 xReturn = pdFALSE; 8015b24: 2300 movs r3, #0 8015b26: 61fb str r3, [r7, #28] 8015b28: e004 b.n 8015b34 } else { *pxTicksToWait = ( TickType_t ) 0; 8015b2a: 683b ldr r3, [r7, #0] 8015b2c: 2200 movs r2, #0 8015b2e: 601a str r2, [r3, #0] xReturn = pdTRUE; 8015b30: 2301 movs r3, #1 8015b32: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 8015b34: f001 fc46 bl 80173c4 return xReturn; 8015b38: 69fb ldr r3, [r7, #28] } 8015b3a: 4618 mov r0, r3 8015b3c: 3720 adds r7, #32 8015b3e: 46bd mov sp, r7 8015b40: bd80 pop {r7, pc} 8015b42: bf00 nop 8015b44: 200025a0 .word 0x200025a0 8015b48: 200025b4 .word 0x200025b4 08015b4c : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 8015b4c: b480 push {r7} 8015b4e: af00 add r7, sp, #0 xYieldPending = pdTRUE; 8015b50: 4b03 ldr r3, [pc, #12] @ (8015b60 ) 8015b52: 2201 movs r2, #1 8015b54: 601a str r2, [r3, #0] } 8015b56: bf00 nop 8015b58: 46bd mov sp, r7 8015b5a: f85d 7b04 ldr.w r7, [sp], #4 8015b5e: 4770 bx lr 8015b60: 200025b0 .word 0x200025b0 08015b64 : * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8015b64: b580 push {r7, lr} 8015b66: b082 sub sp, #8 8015b68: af00 add r7, sp, #0 8015b6a: 6078 str r0, [r7, #4] for( ; ; ) { /* See if any tasks have deleted themselves - if so then the idle task * is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8015b6c: f000 f852 bl 8015c14 * * A critical region is not required here as we are just reading from * the list, and an occasional incorrect value will not matter. If * the ready list at the idle priority contains more than one task * then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 8015b70: 4b06 ldr r3, [pc, #24] @ (8015b8c ) 8015b72: 681b ldr r3, [r3, #0] 8015b74: 2b01 cmp r3, #1 8015b76: d9f9 bls.n 8015b6c { taskYIELD(); 8015b78: 4b05 ldr r3, [pc, #20] @ (8015b90 ) 8015b7a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015b7e: 601a str r2, [r3, #0] 8015b80: f3bf 8f4f dsb sy 8015b84: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 8015b88: e7f0 b.n 8015b6c 8015b8a: bf00 nop 8015b8c: 200020cc .word 0x200020cc 8015b90: e000ed04 .word 0xe000ed04 08015b94 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8015b94: b580 push {r7, lr} 8015b96: b082 sub sp, #8 8015b98: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8015b9a: 2300 movs r3, #0 8015b9c: 607b str r3, [r7, #4] 8015b9e: e00c b.n 8015bba { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8015ba0: 687a ldr r2, [r7, #4] 8015ba2: 4613 mov r3, r2 8015ba4: 009b lsls r3, r3, #2 8015ba6: 4413 add r3, r2 8015ba8: 009b lsls r3, r3, #2 8015baa: 4a12 ldr r2, [pc, #72] @ (8015bf4 ) 8015bac: 4413 add r3, r2 8015bae: 4618 mov r0, r3 8015bb0: f7fd fef8 bl 80139a4 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8015bb4: 687b ldr r3, [r7, #4] 8015bb6: 3301 adds r3, #1 8015bb8: 607b str r3, [r7, #4] 8015bba: 687b ldr r3, [r7, #4] 8015bbc: 2b37 cmp r3, #55 @ 0x37 8015bbe: d9ef bls.n 8015ba0 } vListInitialise( &xDelayedTaskList1 ); 8015bc0: 480d ldr r0, [pc, #52] @ (8015bf8 ) 8015bc2: f7fd feef bl 80139a4 vListInitialise( &xDelayedTaskList2 ); 8015bc6: 480d ldr r0, [pc, #52] @ (8015bfc ) 8015bc8: f7fd feec bl 80139a4 vListInitialise( &xPendingReadyList ); 8015bcc: 480c ldr r0, [pc, #48] @ (8015c00 ) 8015bce: f7fd fee9 bl 80139a4 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 8015bd2: 480c ldr r0, [pc, #48] @ (8015c04 ) 8015bd4: f7fd fee6 bl 80139a4 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8015bd8: 480b ldr r0, [pc, #44] @ (8015c08 ) 8015bda: f7fd fee3 bl 80139a4 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList * using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8015bde: 4b0b ldr r3, [pc, #44] @ (8015c0c ) 8015be0: 4a05 ldr r2, [pc, #20] @ (8015bf8 ) 8015be2: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8015be4: 4b0a ldr r3, [pc, #40] @ (8015c10 ) 8015be6: 4a05 ldr r2, [pc, #20] @ (8015bfc ) 8015be8: 601a str r2, [r3, #0] } 8015bea: bf00 nop 8015bec: 3708 adds r7, #8 8015bee: 46bd mov sp, r7 8015bf0: bd80 pop {r7, pc} 8015bf2: bf00 nop 8015bf4: 200020cc .word 0x200020cc 8015bf8: 2000252c .word 0x2000252c 8015bfc: 20002540 .word 0x20002540 8015c00: 2000255c .word 0x2000255c 8015c04: 20002570 .word 0x20002570 8015c08: 20002588 .word 0x20002588 8015c0c: 20002554 .word 0x20002554 8015c10: 20002558 .word 0x20002558 08015c14 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 8015c14: b580 push {r7, lr} 8015c16: b082 sub sp, #8 8015c18: af00 add r7, sp, #0 { TCB_t * pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() * being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8015c1a: e019 b.n 8015c50 { taskENTER_CRITICAL(); 8015c1c: f001 fba0 bl 8017360 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015c20: 4b10 ldr r3, [pc, #64] @ (8015c64 ) 8015c22: 68db ldr r3, [r3, #12] 8015c24: 68db ldr r3, [r3, #12] 8015c26: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8015c28: 687b ldr r3, [r7, #4] 8015c2a: 3304 adds r3, #4 8015c2c: 4618 mov r0, r3 8015c2e: f7fd ff1f bl 8013a70 --uxCurrentNumberOfTasks; 8015c32: 4b0d ldr r3, [pc, #52] @ (8015c68 ) 8015c34: 681b ldr r3, [r3, #0] 8015c36: 3b01 subs r3, #1 8015c38: 4a0b ldr r2, [pc, #44] @ (8015c68 ) 8015c3a: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 8015c3c: 4b0b ldr r3, [pc, #44] @ (8015c6c ) 8015c3e: 681b ldr r3, [r3, #0] 8015c40: 3b01 subs r3, #1 8015c42: 4a0a ldr r2, [pc, #40] @ (8015c6c ) 8015c44: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 8015c46: f001 fbbd bl 80173c4 prvDeleteTCB( pxTCB ); 8015c4a: 6878 ldr r0, [r7, #4] 8015c4c: f000 f810 bl 8015c70 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8015c50: 4b06 ldr r3, [pc, #24] @ (8015c6c ) 8015c52: 681b ldr r3, [r3, #0] 8015c54: 2b00 cmp r3, #0 8015c56: d1e1 bne.n 8015c1c } } #endif /* INCLUDE_vTaskDelete */ } 8015c58: bf00 nop 8015c5a: bf00 nop 8015c5c: 3708 adds r7, #8 8015c5e: 46bd mov sp, r7 8015c60: bd80 pop {r7, pc} 8015c62: bf00 nop 8015c64: 20002570 .word 0x20002570 8015c68: 2000259c .word 0x2000259c 8015c6c: 20002584 .word 0x20002584 08015c70 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t * pxTCB ) { 8015c70: b580 push {r7, lr} 8015c72: b084 sub sp, #16 8015c74: af00 add r7, sp, #0 8015c76: 6078 str r0, [r7, #4] #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so * check what was statically allocated before trying to free the * memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8015c78: 687b ldr r3, [r7, #4] 8015c7a: f893 3059 ldrb.w r3, [r3, #89] @ 0x59 8015c7e: 2b00 cmp r3, #0 8015c80: d108 bne.n 8015c94 { /* Both the stack and TCB were allocated dynamically, so both * must be freed. */ vPortFreeStack( pxTCB->pxStack ); 8015c82: 687b ldr r3, [r7, #4] 8015c84: 6b1b ldr r3, [r3, #48] @ 0x30 8015c86: 4618 mov r0, r3 8015c88: f001 fd5e bl 8017748 vPortFree( pxTCB ); 8015c8c: 6878 ldr r0, [r7, #4] 8015c8e: f001 fd5b bl 8017748 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8015c92: e019 b.n 8015cc8 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8015c94: 687b ldr r3, [r7, #4] 8015c96: f893 3059 ldrb.w r3, [r3, #89] @ 0x59 8015c9a: 2b01 cmp r3, #1 8015c9c: d103 bne.n 8015ca6 vPortFree( pxTCB ); 8015c9e: 6878 ldr r0, [r7, #4] 8015ca0: f001 fd52 bl 8017748 } 8015ca4: e010 b.n 8015cc8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8015ca6: 687b ldr r3, [r7, #4] 8015ca8: f893 3059 ldrb.w r3, [r3, #89] @ 0x59 8015cac: 2b02 cmp r3, #2 8015cae: d00b beq.n 8015cc8 __asm volatile 8015cb0: f04f 0350 mov.w r3, #80 @ 0x50 8015cb4: f383 8811 msr BASEPRI, r3 8015cb8: f3bf 8f6f isb sy 8015cbc: f3bf 8f4f dsb sy 8015cc0: 60fb str r3, [r7, #12] } 8015cc2: bf00 nop 8015cc4: bf00 nop 8015cc6: e7fd b.n 8015cc4 } 8015cc8: bf00 nop 8015cca: 3710 adds r7, #16 8015ccc: 46bd mov sp, r7 8015cce: bd80 pop {r7, pc} 08015cd0 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8015cd0: b480 push {r7} 8015cd2: af00 add r7, sp, #0 if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8015cd4: 4b0a ldr r3, [pc, #40] @ (8015d00 ) 8015cd6: 681b ldr r3, [r3, #0] 8015cd8: 681b ldr r3, [r3, #0] 8015cda: 2b00 cmp r3, #0 8015cdc: d104 bne.n 8015ce8 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to * the maximum possible value so it is extremely unlikely that the * if( xTickCount >= xNextTaskUnblockTime ) test will pass until * there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8015cde: 4b09 ldr r3, [pc, #36] @ (8015d04 ) 8015ce0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015ce4: 601a str r2, [r3, #0] * the item at the head of the delayed list. This is the time at * which the task at the head of the delayed list should be removed * from the Blocked state. */ xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList ); } } 8015ce6: e005 b.n 8015cf4 xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList ); 8015ce8: 4b05 ldr r3, [pc, #20] @ (8015d00 ) 8015cea: 681b ldr r3, [r3, #0] 8015cec: 68db ldr r3, [r3, #12] 8015cee: 681b ldr r3, [r3, #0] 8015cf0: 4a04 ldr r2, [pc, #16] @ (8015d04 ) 8015cf2: 6013 str r3, [r2, #0] } 8015cf4: bf00 nop 8015cf6: 46bd mov sp, r7 8015cf8: f85d 7b04 ldr.w r7, [sp], #4 8015cfc: 4770 bx lr 8015cfe: bf00 nop 8015d00: 20002554 .word 0x20002554 8015d04: 200025bc .word 0x200025bc 08015d08 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 8015d08: b480 push {r7} 8015d0a: b083 sub sp, #12 8015d0c: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from * an interrupt and the current TCB will always be the same for any * individual execution thread. */ xReturn = pxCurrentTCB; 8015d0e: 4b05 ldr r3, [pc, #20] @ (8015d24 ) 8015d10: 681b ldr r3, [r3, #0] 8015d12: 607b str r3, [r7, #4] return xReturn; 8015d14: 687b ldr r3, [r7, #4] } 8015d16: 4618 mov r0, r3 8015d18: 370c adds r7, #12 8015d1a: 46bd mov sp, r7 8015d1c: f85d 7b04 ldr.w r7, [sp], #4 8015d20: 4770 bx lr 8015d22: bf00 nop 8015d24: 200020c8 .word 0x200020c8 08015d28 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8015d28: b480 push {r7} 8015d2a: b083 sub sp, #12 8015d2c: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8015d2e: 4b0b ldr r3, [pc, #44] @ (8015d5c ) 8015d30: 681b ldr r3, [r3, #0] 8015d32: 2b00 cmp r3, #0 8015d34: d102 bne.n 8015d3c { xReturn = taskSCHEDULER_NOT_STARTED; 8015d36: 2301 movs r3, #1 8015d38: 607b str r3, [r7, #4] 8015d3a: e008 b.n 8015d4e } else { if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 8015d3c: 4b08 ldr r3, [pc, #32] @ (8015d60 ) 8015d3e: 681b ldr r3, [r3, #0] 8015d40: 2b00 cmp r3, #0 8015d42: d102 bne.n 8015d4a { xReturn = taskSCHEDULER_RUNNING; 8015d44: 2302 movs r3, #2 8015d46: 607b str r3, [r7, #4] 8015d48: e001 b.n 8015d4e } else { xReturn = taskSCHEDULER_SUSPENDED; 8015d4a: 2300 movs r3, #0 8015d4c: 607b str r3, [r7, #4] } } return xReturn; 8015d4e: 687b ldr r3, [r7, #4] } 8015d50: 4618 mov r0, r3 8015d52: 370c adds r7, #12 8015d54: 46bd mov sp, r7 8015d56: f85d 7b04 ldr.w r7, [sp], #4 8015d5a: 4770 bx lr 8015d5c: 200025a8 .word 0x200025a8 8015d60: 200025c4 .word 0x200025c4 08015d64 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8015d64: b580 push {r7, lr} 8015d66: b086 sub sp, #24 8015d68: af00 add r7, sp, #0 8015d6a: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8015d6c: 687b ldr r3, [r7, #4] 8015d6e: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8015d70: 2300 movs r3, #0 8015d72: 617b str r3, [r7, #20] /* If the mutex was given back by an interrupt while the queue was * locked then the mutex holder might now be NULL. _RB_ Is this still * needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8015d74: 687b ldr r3, [r7, #4] 8015d76: 2b00 cmp r3, #0 8015d78: d079 beq.n 8015e6e { /* If the holder of the mutex has a priority below the priority of * the task attempting to obtain the mutex then it will temporarily * inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8015d7a: 693b ldr r3, [r7, #16] 8015d7c: 6ada ldr r2, [r3, #44] @ 0x2c 8015d7e: 4b3e ldr r3, [pc, #248] @ (8015e78 ) 8015d80: 681b ldr r3, [r3, #0] 8015d82: 6adb ldr r3, [r3, #44] @ 0x2c 8015d84: 429a cmp r2, r3 8015d86: d269 bcs.n 8015e5c { /* Adjust the mutex holder state to account for its new * priority. Only reset the event list item value if the value is * not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8015d88: 693b ldr r3, [r7, #16] 8015d8a: 699b ldr r3, [r3, #24] 8015d8c: 2b00 cmp r3, #0 8015d8e: db06 blt.n 8015d9e { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015d90: 4b39 ldr r3, [pc, #228] @ (8015e78 ) 8015d92: 681b ldr r3, [r3, #0] 8015d94: 6adb ldr r3, [r3, #44] @ 0x2c 8015d96: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015d9a: 693b ldr r3, [r7, #16] 8015d9c: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need * to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8015d9e: 693b ldr r3, [r7, #16] 8015da0: 6959 ldr r1, [r3, #20] 8015da2: 693b ldr r3, [r7, #16] 8015da4: 6ada ldr r2, [r3, #44] @ 0x2c 8015da6: 4613 mov r3, r2 8015da8: 009b lsls r3, r3, #2 8015daa: 4413 add r3, r2 8015dac: 009b lsls r3, r3, #2 8015dae: 4a33 ldr r2, [pc, #204] @ (8015e7c ) 8015db0: 4413 add r3, r2 8015db2: 4299 cmp r1, r3 8015db4: d14a bne.n 8015e4c { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8015db6: 693b ldr r3, [r7, #16] 8015db8: 3304 adds r3, #4 8015dba: 4618 mov r0, r3 8015dbc: f7fd fe58 bl 8013a70 { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8015dc0: 4b2d ldr r3, [pc, #180] @ (8015e78 ) 8015dc2: 681b ldr r3, [r3, #0] 8015dc4: 6ada ldr r2, [r3, #44] @ 0x2c 8015dc6: 693b ldr r3, [r7, #16] 8015dc8: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 8015dca: 693b ldr r3, [r7, #16] 8015dcc: 6ada ldr r2, [r3, #44] @ 0x2c 8015dce: 4b2c ldr r3, [pc, #176] @ (8015e80 ) 8015dd0: 681b ldr r3, [r3, #0] 8015dd2: 429a cmp r2, r3 8015dd4: d903 bls.n 8015dde 8015dd6: 693b ldr r3, [r7, #16] 8015dd8: 6adb ldr r3, [r3, #44] @ 0x2c 8015dda: 4a29 ldr r2, [pc, #164] @ (8015e80 ) 8015ddc: 6013 str r3, [r2, #0] 8015dde: 693b ldr r3, [r7, #16] 8015de0: 6ada ldr r2, [r3, #44] @ 0x2c 8015de2: 4926 ldr r1, [pc, #152] @ (8015e7c ) 8015de4: 4613 mov r3, r2 8015de6: 009b lsls r3, r3, #2 8015de8: 4413 add r3, r2 8015dea: 009b lsls r3, r3, #2 8015dec: 440b add r3, r1 8015dee: 3304 adds r3, #4 8015df0: 681b ldr r3, [r3, #0] 8015df2: 60fb str r3, [r7, #12] 8015df4: 693b ldr r3, [r7, #16] 8015df6: 68fa ldr r2, [r7, #12] 8015df8: 609a str r2, [r3, #8] 8015dfa: 68fb ldr r3, [r7, #12] 8015dfc: 689a ldr r2, [r3, #8] 8015dfe: 693b ldr r3, [r7, #16] 8015e00: 60da str r2, [r3, #12] 8015e02: 68fb ldr r3, [r7, #12] 8015e04: 689b ldr r3, [r3, #8] 8015e06: 693a ldr r2, [r7, #16] 8015e08: 3204 adds r2, #4 8015e0a: 605a str r2, [r3, #4] 8015e0c: 693b ldr r3, [r7, #16] 8015e0e: 1d1a adds r2, r3, #4 8015e10: 68fb ldr r3, [r7, #12] 8015e12: 609a str r2, [r3, #8] 8015e14: 693b ldr r3, [r7, #16] 8015e16: 6ada ldr r2, [r3, #44] @ 0x2c 8015e18: 4613 mov r3, r2 8015e1a: 009b lsls r3, r3, #2 8015e1c: 4413 add r3, r2 8015e1e: 009b lsls r3, r3, #2 8015e20: 4a16 ldr r2, [pc, #88] @ (8015e7c ) 8015e22: 441a add r2, r3 8015e24: 693b ldr r3, [r7, #16] 8015e26: 615a str r2, [r3, #20] 8015e28: 693b ldr r3, [r7, #16] 8015e2a: 6ada ldr r2, [r3, #44] @ 0x2c 8015e2c: 4913 ldr r1, [pc, #76] @ (8015e7c ) 8015e2e: 4613 mov r3, r2 8015e30: 009b lsls r3, r3, #2 8015e32: 4413 add r3, r2 8015e34: 009b lsls r3, r3, #2 8015e36: 440b add r3, r1 8015e38: 681b ldr r3, [r3, #0] 8015e3a: 1c59 adds r1, r3, #1 8015e3c: 480f ldr r0, [pc, #60] @ (8015e7c ) 8015e3e: 4613 mov r3, r2 8015e40: 009b lsls r3, r3, #2 8015e42: 4413 add r3, r2 8015e44: 009b lsls r3, r3, #2 8015e46: 4403 add r3, r0 8015e48: 6019 str r1, [r3, #0] 8015e4a: e004 b.n 8015e56 } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8015e4c: 4b0a ldr r3, [pc, #40] @ (8015e78 ) 8015e4e: 681b ldr r3, [r3, #0] 8015e50: 6ada ldr r2, [r3, #44] @ 0x2c 8015e52: 693b ldr r3, [r7, #16] 8015e54: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8015e56: 2301 movs r3, #1 8015e58: 617b str r3, [r7, #20] 8015e5a: e008 b.n 8015e6e } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8015e5c: 693b ldr r3, [r7, #16] 8015e5e: 6cda ldr r2, [r3, #76] @ 0x4c 8015e60: 4b05 ldr r3, [pc, #20] @ (8015e78 ) 8015e62: 681b ldr r3, [r3, #0] 8015e64: 6adb ldr r3, [r3, #44] @ 0x2c 8015e66: 429a cmp r2, r3 8015e68: d201 bcs.n 8015e6e * current priority of the mutex holder is not lower than the * priority of the task attempting to take the mutex. * Therefore the mutex holder must have already inherited a * priority, but inheritance would have occurred if that had * not been the case. */ xReturn = pdTRUE; 8015e6a: 2301 movs r3, #1 8015e6c: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8015e6e: 697b ldr r3, [r7, #20] } 8015e70: 4618 mov r0, r3 8015e72: 3718 adds r7, #24 8015e74: 46bd mov sp, r7 8015e76: bd80 pop {r7, pc} 8015e78: 200020c8 .word 0x200020c8 8015e7c: 200020cc .word 0x200020cc 8015e80: 200025a4 .word 0x200025a4 08015e84 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8015e84: b580 push {r7, lr} 8015e86: b088 sub sp, #32 8015e88: af00 add r7, sp, #0 8015e8a: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8015e8c: 687b ldr r3, [r7, #4] 8015e8e: 61bb str r3, [r7, #24] BaseType_t xReturn = pdFALSE; 8015e90: 2300 movs r3, #0 8015e92: 61fb str r3, [r7, #28] if( pxMutexHolder != NULL ) 8015e94: 687b ldr r3, [r7, #4] 8015e96: 2b00 cmp r3, #0 8015e98: f000 8081 beq.w 8015f9e { /* A task can only have an inherited priority if it holds the mutex. * If the mutex is held by a task then it cannot be given from an * interrupt, and if a mutex is given by the holding task then it must * be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8015e9c: 4b42 ldr r3, [pc, #264] @ (8015fa8 ) 8015e9e: 681b ldr r3, [r3, #0] 8015ea0: 69ba ldr r2, [r7, #24] 8015ea2: 429a cmp r2, r3 8015ea4: d00b beq.n 8015ebe __asm volatile 8015ea6: f04f 0350 mov.w r3, #80 @ 0x50 8015eaa: f383 8811 msr BASEPRI, r3 8015eae: f3bf 8f6f isb sy 8015eb2: f3bf 8f4f dsb sy 8015eb6: 613b str r3, [r7, #16] } 8015eb8: bf00 nop 8015eba: bf00 nop 8015ebc: e7fd b.n 8015eba configASSERT( pxTCB->uxMutexesHeld ); 8015ebe: 69bb ldr r3, [r7, #24] 8015ec0: 6d1b ldr r3, [r3, #80] @ 0x50 8015ec2: 2b00 cmp r3, #0 8015ec4: d10b bne.n 8015ede __asm volatile 8015ec6: f04f 0350 mov.w r3, #80 @ 0x50 8015eca: f383 8811 msr BASEPRI, r3 8015ece: f3bf 8f6f isb sy 8015ed2: f3bf 8f4f dsb sy 8015ed6: 60fb str r3, [r7, #12] } 8015ed8: bf00 nop 8015eda: bf00 nop 8015edc: e7fd b.n 8015eda ( pxTCB->uxMutexesHeld )--; 8015ede: 69bb ldr r3, [r7, #24] 8015ee0: 6d1b ldr r3, [r3, #80] @ 0x50 8015ee2: 1e5a subs r2, r3, #1 8015ee4: 69bb ldr r3, [r7, #24] 8015ee6: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another * task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 8015ee8: 69bb ldr r3, [r7, #24] 8015eea: 6ada ldr r2, [r3, #44] @ 0x2c 8015eec: 69bb ldr r3, [r7, #24] 8015eee: 6cdb ldr r3, [r3, #76] @ 0x4c 8015ef0: 429a cmp r2, r3 8015ef2: d054 beq.n 8015f9e { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 8015ef4: 69bb ldr r3, [r7, #24] 8015ef6: 6d1b ldr r3, [r3, #80] @ 0x50 8015ef8: 2b00 cmp r3, #0 8015efa: d150 bne.n 8015f9e /* A task can only have an inherited priority if it holds * the mutex. If the mutex is held by a task then it cannot be * given from an interrupt, and if a mutex is given by the * holding task then it must be the running state task. Remove * the holding task from the ready list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8015efc: 69bb ldr r3, [r7, #24] 8015efe: 3304 adds r3, #4 8015f00: 4618 mov r0, r3 8015f02: f7fd fdb5 bl 8013a70 } /* Disinherit the priority before adding the task into the * new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8015f06: 69bb ldr r3, [r7, #24] 8015f08: 6cda ldr r2, [r3, #76] @ 0x4c 8015f0a: 69bb ldr r3, [r7, #24] 8015f0c: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for * any other purpose if this task is running, and it must be * running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015f0e: 69bb ldr r3, [r7, #24] 8015f10: 6adb ldr r3, [r3, #44] @ 0x2c 8015f12: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015f16: 69bb ldr r3, [r7, #24] 8015f18: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8015f1a: 69bb ldr r3, [r7, #24] 8015f1c: 6ada ldr r2, [r3, #44] @ 0x2c 8015f1e: 4b23 ldr r3, [pc, #140] @ (8015fac ) 8015f20: 681b ldr r3, [r3, #0] 8015f22: 429a cmp r2, r3 8015f24: d903 bls.n 8015f2e 8015f26: 69bb ldr r3, [r7, #24] 8015f28: 6adb ldr r3, [r3, #44] @ 0x2c 8015f2a: 4a20 ldr r2, [pc, #128] @ (8015fac ) 8015f2c: 6013 str r3, [r2, #0] 8015f2e: 69bb ldr r3, [r7, #24] 8015f30: 6ada ldr r2, [r3, #44] @ 0x2c 8015f32: 491f ldr r1, [pc, #124] @ (8015fb0 ) 8015f34: 4613 mov r3, r2 8015f36: 009b lsls r3, r3, #2 8015f38: 4413 add r3, r2 8015f3a: 009b lsls r3, r3, #2 8015f3c: 440b add r3, r1 8015f3e: 3304 adds r3, #4 8015f40: 681b ldr r3, [r3, #0] 8015f42: 617b str r3, [r7, #20] 8015f44: 69bb ldr r3, [r7, #24] 8015f46: 697a ldr r2, [r7, #20] 8015f48: 609a str r2, [r3, #8] 8015f4a: 697b ldr r3, [r7, #20] 8015f4c: 689a ldr r2, [r3, #8] 8015f4e: 69bb ldr r3, [r7, #24] 8015f50: 60da str r2, [r3, #12] 8015f52: 697b ldr r3, [r7, #20] 8015f54: 689b ldr r3, [r3, #8] 8015f56: 69ba ldr r2, [r7, #24] 8015f58: 3204 adds r2, #4 8015f5a: 605a str r2, [r3, #4] 8015f5c: 69bb ldr r3, [r7, #24] 8015f5e: 1d1a adds r2, r3, #4 8015f60: 697b ldr r3, [r7, #20] 8015f62: 609a str r2, [r3, #8] 8015f64: 69bb ldr r3, [r7, #24] 8015f66: 6ada ldr r2, [r3, #44] @ 0x2c 8015f68: 4613 mov r3, r2 8015f6a: 009b lsls r3, r3, #2 8015f6c: 4413 add r3, r2 8015f6e: 009b lsls r3, r3, #2 8015f70: 4a0f ldr r2, [pc, #60] @ (8015fb0 ) 8015f72: 441a add r2, r3 8015f74: 69bb ldr r3, [r7, #24] 8015f76: 615a str r2, [r3, #20] 8015f78: 69bb ldr r3, [r7, #24] 8015f7a: 6ada ldr r2, [r3, #44] @ 0x2c 8015f7c: 490c ldr r1, [pc, #48] @ (8015fb0 ) 8015f7e: 4613 mov r3, r2 8015f80: 009b lsls r3, r3, #2 8015f82: 4413 add r3, r2 8015f84: 009b lsls r3, r3, #2 8015f86: 440b add r3, r1 8015f88: 681b ldr r3, [r3, #0] 8015f8a: 1c59 adds r1, r3, #1 8015f8c: 4808 ldr r0, [pc, #32] @ (8015fb0 ) 8015f8e: 4613 mov r3, r2 8015f90: 009b lsls r3, r3, #2 8015f92: 4413 add r3, r2 8015f94: 009b lsls r3, r3, #2 8015f96: 4403 add r3, r0 8015f98: 6019 str r1, [r3, #0] * in an order different to that in which they were taken. * If a context switch did not occur when the first mutex was * returned, even if a task was waiting on it, then a context * switch should occur when the last mutex is returned whether * a task is waiting on it or not. */ xReturn = pdTRUE; 8015f9a: 2301 movs r3, #1 8015f9c: 61fb str r3, [r7, #28] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8015f9e: 69fb ldr r3, [r7, #28] } 8015fa0: 4618 mov r0, r3 8015fa2: 3720 adds r7, #32 8015fa4: 46bd mov sp, r7 8015fa6: bd80 pop {r7, pc} 8015fa8: 200020c8 .word 0x200020c8 8015fac: 200025a4 .word 0x200025a4 8015fb0: 200020cc .word 0x200020cc 08015fb4 : #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 8015fb4: b580 push {r7, lr} 8015fb6: b08a sub sp, #40 @ 0x28 8015fb8: af00 add r7, sp, #0 8015fba: 6078 str r0, [r7, #4] 8015fbc: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 8015fbe: 687b ldr r3, [r7, #4] 8015fc0: 623b str r3, [r7, #32] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 8015fc2: 2301 movs r3, #1 8015fc4: 61fb str r3, [r7, #28] if( pxMutexHolder != NULL ) 8015fc6: 687b ldr r3, [r7, #4] 8015fc8: 2b00 cmp r3, #0 8015fca: f000 8095 beq.w 80160f8 { /* If pxMutexHolder is not NULL then the holder must hold at least * one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8015fce: 6a3b ldr r3, [r7, #32] 8015fd0: 6d1b ldr r3, [r3, #80] @ 0x50 8015fd2: 2b00 cmp r3, #0 8015fd4: d10b bne.n 8015fee __asm volatile 8015fd6: f04f 0350 mov.w r3, #80 @ 0x50 8015fda: f383 8811 msr BASEPRI, r3 8015fde: f3bf 8f6f isb sy 8015fe2: f3bf 8f4f dsb sy 8015fe6: 613b str r3, [r7, #16] } 8015fe8: bf00 nop 8015fea: bf00 nop 8015fec: e7fd b.n 8015fea /* Determine the priority to which the priority of the task that * holds the mutex should be set. This will be the greater of the * holding task's base priority and the priority of the highest * priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8015fee: 6a3b ldr r3, [r7, #32] 8015ff0: 6cdb ldr r3, [r3, #76] @ 0x4c 8015ff2: 683a ldr r2, [r7, #0] 8015ff4: 429a cmp r2, r3 8015ff6: d902 bls.n 8015ffe { uxPriorityToUse = uxHighestPriorityWaitingTask; 8015ff8: 683b ldr r3, [r7, #0] 8015ffa: 627b str r3, [r7, #36] @ 0x24 8015ffc: e002 b.n 8016004 } else { uxPriorityToUse = pxTCB->uxBasePriority; 8015ffe: 6a3b ldr r3, [r7, #32] 8016000: 6cdb ldr r3, [r3, #76] @ 0x4c 8016002: 627b str r3, [r7, #36] @ 0x24 } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 8016004: 6a3b ldr r3, [r7, #32] 8016006: 6adb ldr r3, [r3, #44] @ 0x2c 8016008: 6a7a ldr r2, [r7, #36] @ 0x24 801600a: 429a cmp r2, r3 801600c: d074 beq.n 80160f8 { /* Only disinherit if no other mutexes are held. This is a * simplification in the priority inheritance implementation. If * the task that holds the mutex is also holding other mutexes then * the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 801600e: 6a3b ldr r3, [r7, #32] 8016010: 6d1b ldr r3, [r3, #80] @ 0x50 8016012: 69fa ldr r2, [r7, #28] 8016014: 429a cmp r2, r3 8016016: d16f bne.n 80160f8 { /* If a task has timed out because it already holds the * mutex it was trying to obtain then it cannot of inherited * its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 8016018: 4b39 ldr r3, [pc, #228] @ (8016100 ) 801601a: 681b ldr r3, [r3, #0] 801601c: 6a3a ldr r2, [r7, #32] 801601e: 429a cmp r2, r3 8016020: d10b bne.n 801603a __asm volatile 8016022: f04f 0350 mov.w r3, #80 @ 0x50 8016026: f383 8811 msr BASEPRI, r3 801602a: f3bf 8f6f isb sy 801602e: f3bf 8f4f dsb sy 8016032: 60fb str r3, [r7, #12] } 8016034: bf00 nop 8016036: bf00 nop 8016038: e7fd b.n 8016036 /* Disinherit the priority, remembering the previous * priority to facilitate determining the subject task's * state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 801603a: 6a3b ldr r3, [r7, #32] 801603c: 6adb ldr r3, [r3, #44] @ 0x2c 801603e: 61bb str r3, [r7, #24] pxTCB->uxPriority = uxPriorityToUse; 8016040: 6a3b ldr r3, [r7, #32] 8016042: 6a7a ldr r2, [r7, #36] @ 0x24 8016044: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not * being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016046: 6a3b ldr r3, [r7, #32] 8016048: 699b ldr r3, [r3, #24] 801604a: 2b00 cmp r3, #0 801604c: db04 blt.n 8016058 { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 801604e: 6a7b ldr r3, [r7, #36] @ 0x24 8016050: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016054: 6a3b ldr r3, [r7, #32] 8016056: 619a str r2, [r3, #24] * then the task that holds the mutex could be in either the * Ready, Blocked or Suspended states. Only remove the task * from its current state list if it is in the Ready state as * the task's priority is going to change and there is one * Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 8016058: 6a3b ldr r3, [r7, #32] 801605a: 6959 ldr r1, [r3, #20] 801605c: 69ba ldr r2, [r7, #24] 801605e: 4613 mov r3, r2 8016060: 009b lsls r3, r3, #2 8016062: 4413 add r3, r2 8016064: 009b lsls r3, r3, #2 8016066: 4a27 ldr r2, [pc, #156] @ (8016104 ) 8016068: 4413 add r3, r2 801606a: 4299 cmp r1, r3 801606c: d144 bne.n 80160f8 { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 801606e: 6a3b ldr r3, [r7, #32] 8016070: 3304 adds r3, #4 8016072: 4618 mov r0, r3 8016074: f7fd fcfc bl 8013a70 else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8016078: 6a3b ldr r3, [r7, #32] 801607a: 6ada ldr r2, [r3, #44] @ 0x2c 801607c: 4b22 ldr r3, [pc, #136] @ (8016108 ) 801607e: 681b ldr r3, [r3, #0] 8016080: 429a cmp r2, r3 8016082: d903 bls.n 801608c 8016084: 6a3b ldr r3, [r7, #32] 8016086: 6adb ldr r3, [r3, #44] @ 0x2c 8016088: 4a1f ldr r2, [pc, #124] @ (8016108 ) 801608a: 6013 str r3, [r2, #0] 801608c: 6a3b ldr r3, [r7, #32] 801608e: 6ada ldr r2, [r3, #44] @ 0x2c 8016090: 491c ldr r1, [pc, #112] @ (8016104 ) 8016092: 4613 mov r3, r2 8016094: 009b lsls r3, r3, #2 8016096: 4413 add r3, r2 8016098: 009b lsls r3, r3, #2 801609a: 440b add r3, r1 801609c: 3304 adds r3, #4 801609e: 681b ldr r3, [r3, #0] 80160a0: 617b str r3, [r7, #20] 80160a2: 6a3b ldr r3, [r7, #32] 80160a4: 697a ldr r2, [r7, #20] 80160a6: 609a str r2, [r3, #8] 80160a8: 697b ldr r3, [r7, #20] 80160aa: 689a ldr r2, [r3, #8] 80160ac: 6a3b ldr r3, [r7, #32] 80160ae: 60da str r2, [r3, #12] 80160b0: 697b ldr r3, [r7, #20] 80160b2: 689b ldr r3, [r3, #8] 80160b4: 6a3a ldr r2, [r7, #32] 80160b6: 3204 adds r2, #4 80160b8: 605a str r2, [r3, #4] 80160ba: 6a3b ldr r3, [r7, #32] 80160bc: 1d1a adds r2, r3, #4 80160be: 697b ldr r3, [r7, #20] 80160c0: 609a str r2, [r3, #8] 80160c2: 6a3b ldr r3, [r7, #32] 80160c4: 6ada ldr r2, [r3, #44] @ 0x2c 80160c6: 4613 mov r3, r2 80160c8: 009b lsls r3, r3, #2 80160ca: 4413 add r3, r2 80160cc: 009b lsls r3, r3, #2 80160ce: 4a0d ldr r2, [pc, #52] @ (8016104 ) 80160d0: 441a add r2, r3 80160d2: 6a3b ldr r3, [r7, #32] 80160d4: 615a str r2, [r3, #20] 80160d6: 6a3b ldr r3, [r7, #32] 80160d8: 6ada ldr r2, [r3, #44] @ 0x2c 80160da: 490a ldr r1, [pc, #40] @ (8016104 ) 80160dc: 4613 mov r3, r2 80160de: 009b lsls r3, r3, #2 80160e0: 4413 add r3, r2 80160e2: 009b lsls r3, r3, #2 80160e4: 440b add r3, r1 80160e6: 681b ldr r3, [r3, #0] 80160e8: 1c59 adds r1, r3, #1 80160ea: 4806 ldr r0, [pc, #24] @ (8016104 ) 80160ec: 4613 mov r3, r2 80160ee: 009b lsls r3, r3, #2 80160f0: 4413 add r3, r2 80160f2: 009b lsls r3, r3, #2 80160f4: 4403 add r3, r0 80160f6: 6019 str r1, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 80160f8: bf00 nop 80160fa: 3728 adds r7, #40 @ 0x28 80160fc: 46bd mov sp, r7 80160fe: bd80 pop {r7, pc} 8016100: 200020c8 .word 0x200020c8 8016104: 200020cc .word 0x200020cc 8016108: 200025a4 .word 0x200025a4 0801610c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 801610c: b480 push {r7} 801610e: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created * then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 8016110: 4b07 ldr r3, [pc, #28] @ (8016130 ) 8016112: 681b ldr r3, [r3, #0] 8016114: 2b00 cmp r3, #0 8016116: d004 beq.n 8016122 { ( pxCurrentTCB->uxMutexesHeld )++; 8016118: 4b05 ldr r3, [pc, #20] @ (8016130 ) 801611a: 681b ldr r3, [r3, #0] 801611c: 6d1a ldr r2, [r3, #80] @ 0x50 801611e: 3201 adds r2, #1 8016120: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 8016122: 4b03 ldr r3, [pc, #12] @ (8016130 ) 8016124: 681b ldr r3, [r3, #0] } 8016126: 4618 mov r0, r3 8016128: 46bd mov sp, r7 801612a: f85d 7b04 ldr.w r7, [sp], #4 801612e: 4770 bx lr 8016130: 200020c8 .word 0x200020c8 08016134 : #if ( configUSE_TASK_NOTIFICATIONS == 1 ) uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait, BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) { 8016134: b580 push {r7, lr} 8016136: b086 sub sp, #24 8016138: af00 add r7, sp, #0 801613a: 60f8 str r0, [r7, #12] 801613c: 60b9 str r1, [r7, #8] 801613e: 607a str r2, [r7, #4] uint32_t ulReturn; configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 8016140: 68fb ldr r3, [r7, #12] 8016142: 2b00 cmp r3, #0 8016144: d00b beq.n 801615e __asm volatile 8016146: f04f 0350 mov.w r3, #80 @ 0x50 801614a: f383 8811 msr BASEPRI, r3 801614e: f3bf 8f6f isb sy 8016152: f3bf 8f4f dsb sy 8016156: 613b str r3, [r7, #16] } 8016158: bf00 nop 801615a: bf00 nop 801615c: e7fd b.n 801615a taskENTER_CRITICAL(); 801615e: f001 f8ff bl 8017360 { /* Only block if the notification count is not already non-zero. */ if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL ) 8016162: 4b28 ldr r3, [pc, #160] @ (8016204 ) 8016164: 681a ldr r2, [r3, #0] 8016166: 68fb ldr r3, [r7, #12] 8016168: 3314 adds r3, #20 801616a: 009b lsls r3, r3, #2 801616c: 4413 add r3, r2 801616e: 685b ldr r3, [r3, #4] 8016170: 2b00 cmp r3, #0 8016172: d115 bne.n 80161a0 { /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; 8016174: 4b23 ldr r3, [pc, #140] @ (8016204 ) 8016176: 681a ldr r2, [r3, #0] 8016178: 68fb ldr r3, [r7, #12] 801617a: 4413 add r3, r2 801617c: 3358 adds r3, #88 @ 0x58 801617e: 2201 movs r2, #1 8016180: 701a strb r2, [r3, #0] if( xTicksToWait > ( TickType_t ) 0 ) 8016182: 687b ldr r3, [r7, #4] 8016184: 2b00 cmp r3, #0 8016186: d00b beq.n 80161a0 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016188: 2101 movs r1, #1 801618a: 6878 ldr r0, [r7, #4] 801618c: f000 fc66 bl 8016a5c /* All ports are written to allow a yield in a critical * section (some will yield immediately, others wait until the * critical section exits) - but it is not something that * application code should ever do. */ portYIELD_WITHIN_API(); 8016190: 4b1d ldr r3, [pc, #116] @ (8016208 ) 8016192: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016196: 601a str r2, [r3, #0] 8016198: f3bf 8f4f dsb sy 801619c: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80161a0: f001 f910 bl 80173c4 taskENTER_CRITICAL(); 80161a4: f001 f8dc bl 8017360 { traceTASK_NOTIFY_TAKE( uxIndexToWait ); ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; 80161a8: 4b16 ldr r3, [pc, #88] @ (8016204 ) 80161aa: 681a ldr r2, [r3, #0] 80161ac: 68fb ldr r3, [r7, #12] 80161ae: 3314 adds r3, #20 80161b0: 009b lsls r3, r3, #2 80161b2: 4413 add r3, r2 80161b4: 685b ldr r3, [r3, #4] 80161b6: 617b str r3, [r7, #20] if( ulReturn != 0UL ) 80161b8: 697b ldr r3, [r7, #20] 80161ba: 2b00 cmp r3, #0 80161bc: d014 beq.n 80161e8 { if( xClearCountOnExit != pdFALSE ) 80161be: 68bb ldr r3, [r7, #8] 80161c0: 2b00 cmp r3, #0 80161c2: d008 beq.n 80161d6 { pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL; 80161c4: 4b0f ldr r3, [pc, #60] @ (8016204 ) 80161c6: 681a ldr r2, [r3, #0] 80161c8: 68fb ldr r3, [r7, #12] 80161ca: 3314 adds r3, #20 80161cc: 009b lsls r3, r3, #2 80161ce: 4413 add r3, r2 80161d0: 2200 movs r2, #0 80161d2: 605a str r2, [r3, #4] 80161d4: e008 b.n 80161e8 } else { pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1; 80161d6: 4b0b ldr r3, [pc, #44] @ (8016204 ) 80161d8: 6819 ldr r1, [r3, #0] 80161da: 697b ldr r3, [r7, #20] 80161dc: 1e5a subs r2, r3, #1 80161de: 68fb ldr r3, [r7, #12] 80161e0: 3314 adds r3, #20 80161e2: 009b lsls r3, r3, #2 80161e4: 440b add r3, r1 80161e6: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; 80161e8: 4b06 ldr r3, [pc, #24] @ (8016204 ) 80161ea: 681a ldr r2, [r3, #0] 80161ec: 68fb ldr r3, [r7, #12] 80161ee: 4413 add r3, r2 80161f0: 3358 adds r3, #88 @ 0x58 80161f2: 2200 movs r2, #0 80161f4: 701a strb r2, [r3, #0] } taskEXIT_CRITICAL(); 80161f6: f001 f8e5 bl 80173c4 return ulReturn; 80161fa: 697b ldr r3, [r7, #20] } 80161fc: 4618 mov r0, r3 80161fe: 3718 adds r7, #24 8016200: 46bd mov sp, r7 8016202: bd80 pop {r7, pc} 8016204: 200020c8 .word 0x200020c8 8016208: e000ed04 .word 0xe000ed04 0801620c : BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t * pulNotificationValue, TickType_t xTicksToWait ) { 801620c: b580 push {r7, lr} 801620e: b086 sub sp, #24 8016210: af00 add r7, sp, #0 8016212: 60f8 str r0, [r7, #12] 8016214: 60b9 str r1, [r7, #8] 8016216: 607a str r2, [r7, #4] 8016218: 603b str r3, [r7, #0] BaseType_t xReturn; configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 801621a: 68fb ldr r3, [r7, #12] 801621c: 2b00 cmp r3, #0 801621e: d00b beq.n 8016238 __asm volatile 8016220: f04f 0350 mov.w r3, #80 @ 0x50 8016224: f383 8811 msr BASEPRI, r3 8016228: f3bf 8f6f isb sy 801622c: f3bf 8f4f dsb sy 8016230: 613b str r3, [r7, #16] } 8016232: bf00 nop 8016234: bf00 nop 8016236: e7fd b.n 8016234 taskENTER_CRITICAL(); 8016238: f001 f892 bl 8017360 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) 801623c: 4b34 ldr r3, [pc, #208] @ (8016310 ) 801623e: 681a ldr r2, [r3, #0] 8016240: 68fb ldr r3, [r7, #12] 8016242: 4413 add r3, r2 8016244: 3358 adds r3, #88 @ 0x58 8016246: 781b ldrb r3, [r3, #0] 8016248: b2db uxtb r3, r3 801624a: 2b02 cmp r3, #2 801624c: d024 beq.n 8016298 { /* Clear bits in the task's notification value as bits may get * set by the notifying task or interrupt. This can be used to * clear the value to zero. */ pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry; 801624e: 4b30 ldr r3, [pc, #192] @ (8016310 ) 8016250: 681a ldr r2, [r3, #0] 8016252: 68fb ldr r3, [r7, #12] 8016254: 3314 adds r3, #20 8016256: 009b lsls r3, r3, #2 8016258: 4413 add r3, r2 801625a: 6859 ldr r1, [r3, #4] 801625c: 68bb ldr r3, [r7, #8] 801625e: 43db mvns r3, r3 8016260: 4019 ands r1, r3 8016262: 68fb ldr r3, [r7, #12] 8016264: 3314 adds r3, #20 8016266: 009b lsls r3, r3, #2 8016268: 4413 add r3, r2 801626a: 6059 str r1, [r3, #4] /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; 801626c: 4b28 ldr r3, [pc, #160] @ (8016310 ) 801626e: 681a ldr r2, [r3, #0] 8016270: 68fb ldr r3, [r7, #12] 8016272: 4413 add r3, r2 8016274: 3358 adds r3, #88 @ 0x58 8016276: 2201 movs r2, #1 8016278: 701a strb r2, [r3, #0] if( xTicksToWait > ( TickType_t ) 0 ) 801627a: 6a3b ldr r3, [r7, #32] 801627c: 2b00 cmp r3, #0 801627e: d00b beq.n 8016298 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016280: 2101 movs r1, #1 8016282: 6a38 ldr r0, [r7, #32] 8016284: f000 fbea bl 8016a5c /* All ports are written to allow a yield in a critical * section (some will yield immediately, others wait until the * critical section exits) - but it is not something that * application code should ever do. */ portYIELD_WITHIN_API(); 8016288: 4b22 ldr r3, [pc, #136] @ (8016314 ) 801628a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801628e: 601a str r2, [r3, #0] 8016290: f3bf 8f4f dsb sy 8016294: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016298: f001 f894 bl 80173c4 taskENTER_CRITICAL(); 801629c: f001 f860 bl 8017360 { traceTASK_NOTIFY_WAIT( uxIndexToWait ); if( pulNotificationValue != NULL ) 80162a0: 683b ldr r3, [r7, #0] 80162a2: 2b00 cmp r3, #0 80162a4: d008 beq.n 80162b8 { /* Output the current notification value, which may or may not * have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; 80162a6: 4b1a ldr r3, [pc, #104] @ (8016310 ) 80162a8: 681a ldr r2, [r3, #0] 80162aa: 68fb ldr r3, [r7, #12] 80162ac: 3314 adds r3, #20 80162ae: 009b lsls r3, r3, #2 80162b0: 4413 add r3, r2 80162b2: 685a ldr r2, [r3, #4] 80162b4: 683b ldr r3, [r7, #0] 80162b6: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the * blocked state (because a notification was already pending) or the * task unblocked because of a notification. Otherwise the task * unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) 80162b8: 4b15 ldr r3, [pc, #84] @ (8016310 ) 80162ba: 681a ldr r2, [r3, #0] 80162bc: 68fb ldr r3, [r7, #12] 80162be: 4413 add r3, r2 80162c0: 3358 adds r3, #88 @ 0x58 80162c2: 781b ldrb r3, [r3, #0] 80162c4: b2db uxtb r3, r3 80162c6: 2b02 cmp r3, #2 80162c8: d002 beq.n 80162d0 { /* A notification was not received. */ xReturn = pdFALSE; 80162ca: 2300 movs r3, #0 80162cc: 617b str r3, [r7, #20] 80162ce: e010 b.n 80162f2 } else { /* A notification was already pending or a notification was * received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit; 80162d0: 4b0f ldr r3, [pc, #60] @ (8016310 ) 80162d2: 681a ldr r2, [r3, #0] 80162d4: 68fb ldr r3, [r7, #12] 80162d6: 3314 adds r3, #20 80162d8: 009b lsls r3, r3, #2 80162da: 4413 add r3, r2 80162dc: 6859 ldr r1, [r3, #4] 80162de: 687b ldr r3, [r7, #4] 80162e0: 43db mvns r3, r3 80162e2: 4019 ands r1, r3 80162e4: 68fb ldr r3, [r7, #12] 80162e6: 3314 adds r3, #20 80162e8: 009b lsls r3, r3, #2 80162ea: 4413 add r3, r2 80162ec: 6059 str r1, [r3, #4] xReturn = pdTRUE; 80162ee: 2301 movs r3, #1 80162f0: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; 80162f2: 4b07 ldr r3, [pc, #28] @ (8016310 ) 80162f4: 681a ldr r2, [r3, #0] 80162f6: 68fb ldr r3, [r7, #12] 80162f8: 4413 add r3, r2 80162fa: 3358 adds r3, #88 @ 0x58 80162fc: 2200 movs r2, #0 80162fe: 701a strb r2, [r3, #0] } taskEXIT_CRITICAL(); 8016300: f001 f860 bl 80173c4 return xReturn; 8016304: 697b ldr r3, [r7, #20] } 8016306: 4618 mov r0, r3 8016308: 3718 adds r7, #24 801630a: 46bd mov sp, r7 801630c: bd80 pop {r7, pc} 801630e: bf00 nop 8016310: 200020c8 .word 0x200020c8 8016314: e000ed04 .word 0xe000ed04 08016318 : BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t * pulPreviousNotificationValue ) { 8016318: b580 push {r7, lr} 801631a: b08e sub sp, #56 @ 0x38 801631c: af00 add r7, sp, #0 801631e: 60f8 str r0, [r7, #12] 8016320: 60b9 str r1, [r7, #8] 8016322: 607a str r2, [r7, #4] 8016324: 70fb strb r3, [r7, #3] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 8016326: 2301 movs r3, #1 8016328: 637b str r3, [r7, #52] @ 0x34 uint8_t ucOriginalNotifyState; configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 801632a: 68bb ldr r3, [r7, #8] 801632c: 2b00 cmp r3, #0 801632e: d00b beq.n 8016348 __asm volatile 8016330: f04f 0350 mov.w r3, #80 @ 0x50 8016334: f383 8811 msr BASEPRI, r3 8016338: f3bf 8f6f isb sy 801633c: f3bf 8f4f dsb sy 8016340: 623b str r3, [r7, #32] } 8016342: bf00 nop 8016344: bf00 nop 8016346: e7fd b.n 8016344 configASSERT( xTaskToNotify ); 8016348: 68fb ldr r3, [r7, #12] 801634a: 2b00 cmp r3, #0 801634c: d10b bne.n 8016366 __asm volatile 801634e: f04f 0350 mov.w r3, #80 @ 0x50 8016352: f383 8811 msr BASEPRI, r3 8016356: f3bf 8f6f isb sy 801635a: f3bf 8f4f dsb sy 801635e: 61fb str r3, [r7, #28] } 8016360: bf00 nop 8016362: bf00 nop 8016364: e7fd b.n 8016362 pxTCB = xTaskToNotify; 8016366: 68fb ldr r3, [r7, #12] 8016368: 633b str r3, [r7, #48] @ 0x30 taskENTER_CRITICAL(); 801636a: f000 fff9 bl 8017360 { if( pulPreviousNotificationValue != NULL ) 801636e: 6c3b ldr r3, [r7, #64] @ 0x40 8016370: 2b00 cmp r3, #0 8016372: d007 beq.n 8016384 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; 8016374: 6b3a ldr r2, [r7, #48] @ 0x30 8016376: 68bb ldr r3, [r7, #8] 8016378: 3314 adds r3, #20 801637a: 009b lsls r3, r3, #2 801637c: 4413 add r3, r2 801637e: 685a ldr r2, [r3, #4] 8016380: 6c3b ldr r3, [r7, #64] @ 0x40 8016382: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; 8016384: 6b3a ldr r2, [r7, #48] @ 0x30 8016386: 68bb ldr r3, [r7, #8] 8016388: 4413 add r3, r2 801638a: 3358 adds r3, #88 @ 0x58 801638c: 781b ldrb r3, [r3, #0] 801638e: f887 302f strb.w r3, [r7, #47] @ 0x2f pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; 8016392: 6b3a ldr r2, [r7, #48] @ 0x30 8016394: 68bb ldr r3, [r7, #8] 8016396: 4413 add r3, r2 8016398: 3358 adds r3, #88 @ 0x58 801639a: 2202 movs r2, #2 801639c: 701a strb r2, [r3, #0] switch( eAction ) 801639e: 78fb ldrb r3, [r7, #3] 80163a0: 2b04 cmp r3, #4 80163a2: d841 bhi.n 8016428 80163a4: a201 add r2, pc, #4 @ (adr r2, 80163ac ) 80163a6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80163aa: bf00 nop 80163ac: 08016449 .word 0x08016449 80163b0: 080163c1 .word 0x080163c1 80163b4: 080163df .word 0x080163df 80163b8: 080163fb .word 0x080163fb 80163bc: 0801640b .word 0x0801640b { case eSetBits: pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; 80163c0: 6b3a ldr r2, [r7, #48] @ 0x30 80163c2: 68bb ldr r3, [r7, #8] 80163c4: 3314 adds r3, #20 80163c6: 009b lsls r3, r3, #2 80163c8: 4413 add r3, r2 80163ca: 685a ldr r2, [r3, #4] 80163cc: 687b ldr r3, [r7, #4] 80163ce: 431a orrs r2, r3 80163d0: 6b39 ldr r1, [r7, #48] @ 0x30 80163d2: 68bb ldr r3, [r7, #8] 80163d4: 3314 adds r3, #20 80163d6: 009b lsls r3, r3, #2 80163d8: 440b add r3, r1 80163da: 605a str r2, [r3, #4] break; 80163dc: e037 b.n 801644e case eIncrement: ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; 80163de: 6b3a ldr r2, [r7, #48] @ 0x30 80163e0: 68bb ldr r3, [r7, #8] 80163e2: 3314 adds r3, #20 80163e4: 009b lsls r3, r3, #2 80163e6: 4413 add r3, r2 80163e8: 685b ldr r3, [r3, #4] 80163ea: 1c5a adds r2, r3, #1 80163ec: 6b39 ldr r1, [r7, #48] @ 0x30 80163ee: 68bb ldr r3, [r7, #8] 80163f0: 3314 adds r3, #20 80163f2: 009b lsls r3, r3, #2 80163f4: 440b add r3, r1 80163f6: 605a str r2, [r3, #4] break; 80163f8: e029 b.n 801644e case eSetValueWithOverwrite: pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; 80163fa: 6b3a ldr r2, [r7, #48] @ 0x30 80163fc: 68bb ldr r3, [r7, #8] 80163fe: 3314 adds r3, #20 8016400: 009b lsls r3, r3, #2 8016402: 4413 add r3, r2 8016404: 687a ldr r2, [r7, #4] 8016406: 605a str r2, [r3, #4] break; 8016408: e021 b.n 801644e case eSetValueWithoutOverwrite: if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 801640a: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 801640e: 2b02 cmp r3, #2 8016410: d007 beq.n 8016422 { pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; 8016412: 6b3a ldr r2, [r7, #48] @ 0x30 8016414: 68bb ldr r3, [r7, #8] 8016416: 3314 adds r3, #20 8016418: 009b lsls r3, r3, #2 801641a: 4413 add r3, r2 801641c: 687a ldr r2, [r7, #4] 801641e: 605a str r2, [r3, #4] { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016420: e015 b.n 801644e xReturn = pdFAIL; 8016422: 2300 movs r3, #0 8016424: 637b str r3, [r7, #52] @ 0x34 break; 8016426: e012 b.n 801644e default: /* Should not get here if all enums are handled. * Artificially force an assert by testing a value the * compiler can't assume is const. */ configASSERT( xTickCount == ( TickType_t ) 0 ); 8016428: 4b4d ldr r3, [pc, #308] @ (8016560 ) 801642a: 681b ldr r3, [r3, #0] 801642c: 2b00 cmp r3, #0 801642e: d00d beq.n 801644c __asm volatile 8016430: f04f 0350 mov.w r3, #80 @ 0x50 8016434: f383 8811 msr BASEPRI, r3 8016438: f3bf 8f6f isb sy 801643c: f3bf 8f4f dsb sy 8016440: 61bb str r3, [r7, #24] } 8016442: bf00 nop 8016444: bf00 nop 8016446: e7fd b.n 8016444 break; 8016448: bf00 nop 801644a: e000 b.n 801644e break; 801644c: bf00 nop traceTASK_NOTIFY( uxIndexToNotify ); /* If the task is in the blocked state specifically to wait for a * notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 801644e: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8016452: 2b01 cmp r3, #1 8016454: d17d bne.n 8016552 { listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 8016456: 6b3b ldr r3, [r7, #48] @ 0x30 8016458: 695b ldr r3, [r3, #20] 801645a: 62bb str r3, [r7, #40] @ 0x28 801645c: 6b3b ldr r3, [r7, #48] @ 0x30 801645e: 689b ldr r3, [r3, #8] 8016460: 6b3a ldr r2, [r7, #48] @ 0x30 8016462: 68d2 ldr r2, [r2, #12] 8016464: 609a str r2, [r3, #8] 8016466: 6b3b ldr r3, [r7, #48] @ 0x30 8016468: 68db ldr r3, [r3, #12] 801646a: 6b3a ldr r2, [r7, #48] @ 0x30 801646c: 6892 ldr r2, [r2, #8] 801646e: 605a str r2, [r3, #4] 8016470: 6abb ldr r3, [r7, #40] @ 0x28 8016472: 685a ldr r2, [r3, #4] 8016474: 6b3b ldr r3, [r7, #48] @ 0x30 8016476: 3304 adds r3, #4 8016478: 429a cmp r2, r3 801647a: d103 bne.n 8016484 801647c: 6b3b ldr r3, [r7, #48] @ 0x30 801647e: 68da ldr r2, [r3, #12] 8016480: 6abb ldr r3, [r7, #40] @ 0x28 8016482: 605a str r2, [r3, #4] 8016484: 6b3b ldr r3, [r7, #48] @ 0x30 8016486: 2200 movs r2, #0 8016488: 615a str r2, [r3, #20] 801648a: 6abb ldr r3, [r7, #40] @ 0x28 801648c: 681b ldr r3, [r3, #0] 801648e: 1e5a subs r2, r3, #1 8016490: 6abb ldr r3, [r7, #40] @ 0x28 8016492: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxTCB ); 8016494: 6b3b ldr r3, [r7, #48] @ 0x30 8016496: 6ada ldr r2, [r3, #44] @ 0x2c 8016498: 4b32 ldr r3, [pc, #200] @ (8016564 ) 801649a: 681b ldr r3, [r3, #0] 801649c: 429a cmp r2, r3 801649e: d903 bls.n 80164a8 80164a0: 6b3b ldr r3, [r7, #48] @ 0x30 80164a2: 6adb ldr r3, [r3, #44] @ 0x2c 80164a4: 4a2f ldr r2, [pc, #188] @ (8016564 ) 80164a6: 6013 str r3, [r2, #0] 80164a8: 6b3b ldr r3, [r7, #48] @ 0x30 80164aa: 6ada ldr r2, [r3, #44] @ 0x2c 80164ac: 492e ldr r1, [pc, #184] @ (8016568 ) 80164ae: 4613 mov r3, r2 80164b0: 009b lsls r3, r3, #2 80164b2: 4413 add r3, r2 80164b4: 009b lsls r3, r3, #2 80164b6: 440b add r3, r1 80164b8: 3304 adds r3, #4 80164ba: 681b ldr r3, [r3, #0] 80164bc: 627b str r3, [r7, #36] @ 0x24 80164be: 6b3b ldr r3, [r7, #48] @ 0x30 80164c0: 6a7a ldr r2, [r7, #36] @ 0x24 80164c2: 609a str r2, [r3, #8] 80164c4: 6a7b ldr r3, [r7, #36] @ 0x24 80164c6: 689a ldr r2, [r3, #8] 80164c8: 6b3b ldr r3, [r7, #48] @ 0x30 80164ca: 60da str r2, [r3, #12] 80164cc: 6a7b ldr r3, [r7, #36] @ 0x24 80164ce: 689b ldr r3, [r3, #8] 80164d0: 6b3a ldr r2, [r7, #48] @ 0x30 80164d2: 3204 adds r2, #4 80164d4: 605a str r2, [r3, #4] 80164d6: 6b3b ldr r3, [r7, #48] @ 0x30 80164d8: 1d1a adds r2, r3, #4 80164da: 6a7b ldr r3, [r7, #36] @ 0x24 80164dc: 609a str r2, [r3, #8] 80164de: 6b3b ldr r3, [r7, #48] @ 0x30 80164e0: 6ada ldr r2, [r3, #44] @ 0x2c 80164e2: 4613 mov r3, r2 80164e4: 009b lsls r3, r3, #2 80164e6: 4413 add r3, r2 80164e8: 009b lsls r3, r3, #2 80164ea: 4a1f ldr r2, [pc, #124] @ (8016568 ) 80164ec: 441a add r2, r3 80164ee: 6b3b ldr r3, [r7, #48] @ 0x30 80164f0: 615a str r2, [r3, #20] 80164f2: 6b3b ldr r3, [r7, #48] @ 0x30 80164f4: 6ada ldr r2, [r3, #44] @ 0x2c 80164f6: 491c ldr r1, [pc, #112] @ (8016568 ) 80164f8: 4613 mov r3, r2 80164fa: 009b lsls r3, r3, #2 80164fc: 4413 add r3, r2 80164fe: 009b lsls r3, r3, #2 8016500: 440b add r3, r1 8016502: 681b ldr r3, [r3, #0] 8016504: 1c59 adds r1, r3, #1 8016506: 4818 ldr r0, [pc, #96] @ (8016568 ) 8016508: 4613 mov r3, r2 801650a: 009b lsls r3, r3, #2 801650c: 4413 add r3, r2 801650e: 009b lsls r3, r3, #2 8016510: 4403 add r3, r0 8016512: 6019 str r1, [r3, #0] /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8016514: 6b3b ldr r3, [r7, #48] @ 0x30 8016516: 6a9b ldr r3, [r3, #40] @ 0x28 8016518: 2b00 cmp r3, #0 801651a: d00b beq.n 8016534 __asm volatile 801651c: f04f 0350 mov.w r3, #80 @ 0x50 8016520: f383 8811 msr BASEPRI, r3 8016524: f3bf 8f6f isb sy 8016528: f3bf 8f4f dsb sy 801652c: 617b str r3, [r7, #20] } 801652e: bf00 nop 8016530: bf00 nop 8016532: e7fd b.n 8016530 * earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016534: 6b3b ldr r3, [r7, #48] @ 0x30 8016536: 6ada ldr r2, [r3, #44] @ 0x2c 8016538: 4b0c ldr r3, [pc, #48] @ (801656c ) 801653a: 681b ldr r3, [r3, #0] 801653c: 6adb ldr r3, [r3, #44] @ 0x2c 801653e: 429a cmp r2, r3 8016540: d907 bls.n 8016552 { /* The notified task has a priority above the currently * executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016542: 4b0b ldr r3, [pc, #44] @ (8016570 ) 8016544: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016548: 601a str r2, [r3, #0] 801654a: f3bf 8f4f dsb sy 801654e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016552: f000 ff37 bl 80173c4 return xReturn; 8016556: 6b7b ldr r3, [r7, #52] @ 0x34 } 8016558: 4618 mov r0, r3 801655a: 3738 adds r7, #56 @ 0x38 801655c: 46bd mov sp, r7 801655e: bd80 pop {r7, pc} 8016560: 200025a0 .word 0x200025a0 8016564: 200025a4 .word 0x200025a4 8016568: 200020cc .word 0x200020cc 801656c: 200020c8 .word 0x200020c8 8016570: e000ed04 .word 0xe000ed04 08016574 : UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t * pulPreviousNotificationValue, BaseType_t * pxHigherPriorityTaskWoken ) { 8016574: b580 push {r7, lr} 8016576: b092 sub sp, #72 @ 0x48 8016578: af00 add r7, sp, #0 801657a: 60f8 str r0, [r7, #12] 801657c: 60b9 str r1, [r7, #8] 801657e: 607a str r2, [r7, #4] 8016580: 70fb strb r3, [r7, #3] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8016582: 2301 movs r3, #1 8016584: 647b str r3, [r7, #68] @ 0x44 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016586: 68fb ldr r3, [r7, #12] 8016588: 2b00 cmp r3, #0 801658a: d10b bne.n 80165a4 __asm volatile 801658c: f04f 0350 mov.w r3, #80 @ 0x50 8016590: f383 8811 msr BASEPRI, r3 8016594: f3bf 8f6f isb sy 8016598: f3bf 8f4f dsb sy 801659c: 62bb str r3, [r7, #40] @ 0x28 } 801659e: bf00 nop 80165a0: bf00 nop 80165a2: e7fd b.n 80165a0 configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 80165a4: 68bb ldr r3, [r7, #8] 80165a6: 2b00 cmp r3, #0 80165a8: d00b beq.n 80165c2 __asm volatile 80165aa: f04f 0350 mov.w r3, #80 @ 0x50 80165ae: f383 8811 msr BASEPRI, r3 80165b2: f3bf 8f6f isb sy 80165b6: f3bf 8f4f dsb sy 80165ba: 627b str r3, [r7, #36] @ 0x24 } 80165bc: bf00 nop 80165be: bf00 nop 80165c0: e7fd b.n 80165be * below the maximum system call interrupt priority. FreeRTOS maintains a * separate interrupt safe API to ensure interrupt entry is as fast and as * simple as possible. More information (albeit Cortex-M specific) is * provided on the following link: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 80165c2: f000 ffb3 bl 801752c pxTCB = xTaskToNotify; 80165c6: 68fb ldr r3, [r7, #12] 80165c8: 643b str r3, [r7, #64] @ 0x40 __asm volatile 80165ca: f3ef 8211 mrs r2, BASEPRI 80165ce: f04f 0350 mov.w r3, #80 @ 0x50 80165d2: f383 8811 msr BASEPRI, r3 80165d6: f3bf 8f6f isb sy 80165da: f3bf 8f4f dsb sy 80165de: 623a str r2, [r7, #32] 80165e0: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 80165e2: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80165e4: 63fb str r3, [r7, #60] @ 0x3c { if( pulPreviousNotificationValue != NULL ) 80165e6: 6d3b ldr r3, [r7, #80] @ 0x50 80165e8: 2b00 cmp r3, #0 80165ea: d007 beq.n 80165fc { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; 80165ec: 6c3a ldr r2, [r7, #64] @ 0x40 80165ee: 68bb ldr r3, [r7, #8] 80165f0: 3314 adds r3, #20 80165f2: 009b lsls r3, r3, #2 80165f4: 4413 add r3, r2 80165f6: 685a ldr r2, [r3, #4] 80165f8: 6d3b ldr r3, [r7, #80] @ 0x50 80165fa: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; 80165fc: 6c3a ldr r2, [r7, #64] @ 0x40 80165fe: 68bb ldr r3, [r7, #8] 8016600: 4413 add r3, r2 8016602: 3358 adds r3, #88 @ 0x58 8016604: 781b ldrb r3, [r3, #0] 8016606: f887 303b strb.w r3, [r7, #59] @ 0x3b pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; 801660a: 6c3a ldr r2, [r7, #64] @ 0x40 801660c: 68bb ldr r3, [r7, #8] 801660e: 4413 add r3, r2 8016610: 3358 adds r3, #88 @ 0x58 8016612: 2202 movs r2, #2 8016614: 701a strb r2, [r3, #0] switch( eAction ) 8016616: 78fb ldrb r3, [r7, #3] 8016618: 2b04 cmp r3, #4 801661a: d841 bhi.n 80166a0 801661c: a201 add r2, pc, #4 @ (adr r2, 8016624 ) 801661e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016622: bf00 nop 8016624: 080166c1 .word 0x080166c1 8016628: 08016639 .word 0x08016639 801662c: 08016657 .word 0x08016657 8016630: 08016673 .word 0x08016673 8016634: 08016683 .word 0x08016683 { case eSetBits: pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; 8016638: 6c3a ldr r2, [r7, #64] @ 0x40 801663a: 68bb ldr r3, [r7, #8] 801663c: 3314 adds r3, #20 801663e: 009b lsls r3, r3, #2 8016640: 4413 add r3, r2 8016642: 685a ldr r2, [r3, #4] 8016644: 687b ldr r3, [r7, #4] 8016646: 431a orrs r2, r3 8016648: 6c39 ldr r1, [r7, #64] @ 0x40 801664a: 68bb ldr r3, [r7, #8] 801664c: 3314 adds r3, #20 801664e: 009b lsls r3, r3, #2 8016650: 440b add r3, r1 8016652: 605a str r2, [r3, #4] break; 8016654: e037 b.n 80166c6 case eIncrement: ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; 8016656: 6c3a ldr r2, [r7, #64] @ 0x40 8016658: 68bb ldr r3, [r7, #8] 801665a: 3314 adds r3, #20 801665c: 009b lsls r3, r3, #2 801665e: 4413 add r3, r2 8016660: 685b ldr r3, [r3, #4] 8016662: 1c5a adds r2, r3, #1 8016664: 6c39 ldr r1, [r7, #64] @ 0x40 8016666: 68bb ldr r3, [r7, #8] 8016668: 3314 adds r3, #20 801666a: 009b lsls r3, r3, #2 801666c: 440b add r3, r1 801666e: 605a str r2, [r3, #4] break; 8016670: e029 b.n 80166c6 case eSetValueWithOverwrite: pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; 8016672: 6c3a ldr r2, [r7, #64] @ 0x40 8016674: 68bb ldr r3, [r7, #8] 8016676: 3314 adds r3, #20 8016678: 009b lsls r3, r3, #2 801667a: 4413 add r3, r2 801667c: 687a ldr r2, [r7, #4] 801667e: 605a str r2, [r3, #4] break; 8016680: e021 b.n 80166c6 case eSetValueWithoutOverwrite: if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016682: f897 303b ldrb.w r3, [r7, #59] @ 0x3b 8016686: 2b02 cmp r3, #2 8016688: d007 beq.n 801669a { pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; 801668a: 6c3a ldr r2, [r7, #64] @ 0x40 801668c: 68bb ldr r3, [r7, #8] 801668e: 3314 adds r3, #20 8016690: 009b lsls r3, r3, #2 8016692: 4413 add r3, r2 8016694: 687a ldr r2, [r7, #4] 8016696: 605a str r2, [r3, #4] { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016698: e015 b.n 80166c6 xReturn = pdFAIL; 801669a: 2300 movs r3, #0 801669c: 647b str r3, [r7, #68] @ 0x44 break; 801669e: e012 b.n 80166c6 default: /* Should not get here if all enums are handled. * Artificially force an assert by testing a value the * compiler can't assume is const. */ configASSERT( xTickCount == ( TickType_t ) 0 ); 80166a0: 4b61 ldr r3, [pc, #388] @ (8016828 ) 80166a2: 681b ldr r3, [r3, #0] 80166a4: 2b00 cmp r3, #0 80166a6: d00d beq.n 80166c4 __asm volatile 80166a8: f04f 0350 mov.w r3, #80 @ 0x50 80166ac: f383 8811 msr BASEPRI, r3 80166b0: f3bf 8f6f isb sy 80166b4: f3bf 8f4f dsb sy 80166b8: 61bb str r3, [r7, #24] } 80166ba: bf00 nop 80166bc: bf00 nop 80166be: e7fd b.n 80166bc break; 80166c0: bf00 nop 80166c2: e000 b.n 80166c6 break; 80166c4: bf00 nop traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ); /* If the task is in the blocked state specifically to wait for a * notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 80166c6: f897 303b ldrb.w r3, [r7, #59] @ 0x3b 80166ca: 2b01 cmp r3, #1 80166cc: f040 80a0 bne.w 8016810 { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 80166d0: 6c3b ldr r3, [r7, #64] @ 0x40 80166d2: 6a9b ldr r3, [r3, #40] @ 0x28 80166d4: 2b00 cmp r3, #0 80166d6: d00b beq.n 80166f0 __asm volatile 80166d8: f04f 0350 mov.w r3, #80 @ 0x50 80166dc: f383 8811 msr BASEPRI, r3 80166e0: f3bf 8f6f isb sy 80166e4: f3bf 8f4f dsb sy 80166e8: 617b str r3, [r7, #20] } 80166ea: bf00 nop 80166ec: bf00 nop 80166ee: e7fd b.n 80166ec if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 80166f0: 4b4e ldr r3, [pc, #312] @ (801682c ) 80166f2: 681b ldr r3, [r3, #0] 80166f4: 2b00 cmp r3, #0 80166f6: d15f bne.n 80167b8 { listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 80166f8: 6c3b ldr r3, [r7, #64] @ 0x40 80166fa: 695b ldr r3, [r3, #20] 80166fc: 633b str r3, [r7, #48] @ 0x30 80166fe: 6c3b ldr r3, [r7, #64] @ 0x40 8016700: 689b ldr r3, [r3, #8] 8016702: 6c3a ldr r2, [r7, #64] @ 0x40 8016704: 68d2 ldr r2, [r2, #12] 8016706: 609a str r2, [r3, #8] 8016708: 6c3b ldr r3, [r7, #64] @ 0x40 801670a: 68db ldr r3, [r3, #12] 801670c: 6c3a ldr r2, [r7, #64] @ 0x40 801670e: 6892 ldr r2, [r2, #8] 8016710: 605a str r2, [r3, #4] 8016712: 6b3b ldr r3, [r7, #48] @ 0x30 8016714: 685a ldr r2, [r3, #4] 8016716: 6c3b ldr r3, [r7, #64] @ 0x40 8016718: 3304 adds r3, #4 801671a: 429a cmp r2, r3 801671c: d103 bne.n 8016726 801671e: 6c3b ldr r3, [r7, #64] @ 0x40 8016720: 68da ldr r2, [r3, #12] 8016722: 6b3b ldr r3, [r7, #48] @ 0x30 8016724: 605a str r2, [r3, #4] 8016726: 6c3b ldr r3, [r7, #64] @ 0x40 8016728: 2200 movs r2, #0 801672a: 615a str r2, [r3, #20] 801672c: 6b3b ldr r3, [r7, #48] @ 0x30 801672e: 681b ldr r3, [r3, #0] 8016730: 1e5a subs r2, r3, #1 8016732: 6b3b ldr r3, [r7, #48] @ 0x30 8016734: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxTCB ); 8016736: 6c3b ldr r3, [r7, #64] @ 0x40 8016738: 6ada ldr r2, [r3, #44] @ 0x2c 801673a: 4b3d ldr r3, [pc, #244] @ (8016830 ) 801673c: 681b ldr r3, [r3, #0] 801673e: 429a cmp r2, r3 8016740: d903 bls.n 801674a 8016742: 6c3b ldr r3, [r7, #64] @ 0x40 8016744: 6adb ldr r3, [r3, #44] @ 0x2c 8016746: 4a3a ldr r2, [pc, #232] @ (8016830 ) 8016748: 6013 str r3, [r2, #0] 801674a: 6c3b ldr r3, [r7, #64] @ 0x40 801674c: 6ada ldr r2, [r3, #44] @ 0x2c 801674e: 4939 ldr r1, [pc, #228] @ (8016834 ) 8016750: 4613 mov r3, r2 8016752: 009b lsls r3, r3, #2 8016754: 4413 add r3, r2 8016756: 009b lsls r3, r3, #2 8016758: 440b add r3, r1 801675a: 3304 adds r3, #4 801675c: 681b ldr r3, [r3, #0] 801675e: 62fb str r3, [r7, #44] @ 0x2c 8016760: 6c3b ldr r3, [r7, #64] @ 0x40 8016762: 6afa ldr r2, [r7, #44] @ 0x2c 8016764: 609a str r2, [r3, #8] 8016766: 6afb ldr r3, [r7, #44] @ 0x2c 8016768: 689a ldr r2, [r3, #8] 801676a: 6c3b ldr r3, [r7, #64] @ 0x40 801676c: 60da str r2, [r3, #12] 801676e: 6afb ldr r3, [r7, #44] @ 0x2c 8016770: 689b ldr r3, [r3, #8] 8016772: 6c3a ldr r2, [r7, #64] @ 0x40 8016774: 3204 adds r2, #4 8016776: 605a str r2, [r3, #4] 8016778: 6c3b ldr r3, [r7, #64] @ 0x40 801677a: 1d1a adds r2, r3, #4 801677c: 6afb ldr r3, [r7, #44] @ 0x2c 801677e: 609a str r2, [r3, #8] 8016780: 6c3b ldr r3, [r7, #64] @ 0x40 8016782: 6ada ldr r2, [r3, #44] @ 0x2c 8016784: 4613 mov r3, r2 8016786: 009b lsls r3, r3, #2 8016788: 4413 add r3, r2 801678a: 009b lsls r3, r3, #2 801678c: 4a29 ldr r2, [pc, #164] @ (8016834 ) 801678e: 441a add r2, r3 8016790: 6c3b ldr r3, [r7, #64] @ 0x40 8016792: 615a str r2, [r3, #20] 8016794: 6c3b ldr r3, [r7, #64] @ 0x40 8016796: 6ada ldr r2, [r3, #44] @ 0x2c 8016798: 4926 ldr r1, [pc, #152] @ (8016834 ) 801679a: 4613 mov r3, r2 801679c: 009b lsls r3, r3, #2 801679e: 4413 add r3, r2 80167a0: 009b lsls r3, r3, #2 80167a2: 440b add r3, r1 80167a4: 681b ldr r3, [r3, #0] 80167a6: 1c59 adds r1, r3, #1 80167a8: 4822 ldr r0, [pc, #136] @ (8016834 ) 80167aa: 4613 mov r3, r2 80167ac: 009b lsls r3, r3, #2 80167ae: 4413 add r3, r2 80167b0: 009b lsls r3, r3, #2 80167b2: 4403 add r3, r0 80167b4: 6019 str r1, [r3, #0] 80167b6: e01b b.n 80167f0 } else { /* The delayed and ready lists cannot be accessed, so hold * this task pending until the scheduler is resumed. */ listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 80167b8: 4b1f ldr r3, [pc, #124] @ (8016838 ) 80167ba: 685b ldr r3, [r3, #4] 80167bc: 637b str r3, [r7, #52] @ 0x34 80167be: 6c3b ldr r3, [r7, #64] @ 0x40 80167c0: 6b7a ldr r2, [r7, #52] @ 0x34 80167c2: 61da str r2, [r3, #28] 80167c4: 6b7b ldr r3, [r7, #52] @ 0x34 80167c6: 689a ldr r2, [r3, #8] 80167c8: 6c3b ldr r3, [r7, #64] @ 0x40 80167ca: 621a str r2, [r3, #32] 80167cc: 6b7b ldr r3, [r7, #52] @ 0x34 80167ce: 689b ldr r3, [r3, #8] 80167d0: 6c3a ldr r2, [r7, #64] @ 0x40 80167d2: 3218 adds r2, #24 80167d4: 605a str r2, [r3, #4] 80167d6: 6c3b ldr r3, [r7, #64] @ 0x40 80167d8: f103 0218 add.w r2, r3, #24 80167dc: 6b7b ldr r3, [r7, #52] @ 0x34 80167de: 609a str r2, [r3, #8] 80167e0: 6c3b ldr r3, [r7, #64] @ 0x40 80167e2: 4a15 ldr r2, [pc, #84] @ (8016838 ) 80167e4: 629a str r2, [r3, #40] @ 0x28 80167e6: 4b14 ldr r3, [pc, #80] @ (8016838 ) 80167e8: 681b ldr r3, [r3, #0] 80167ea: 3301 adds r3, #1 80167ec: 4a12 ldr r2, [pc, #72] @ (8016838 ) 80167ee: 6013 str r3, [r2, #0] } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80167f0: 6c3b ldr r3, [r7, #64] @ 0x40 80167f2: 6ada ldr r2, [r3, #44] @ 0x2c 80167f4: 4b11 ldr r3, [pc, #68] @ (801683c ) 80167f6: 681b ldr r3, [r3, #0] 80167f8: 6adb ldr r3, [r3, #44] @ 0x2c 80167fa: 429a cmp r2, r3 80167fc: d908 bls.n 8016810 { /* The notified task has a priority above the currently * executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80167fe: 6d7b ldr r3, [r7, #84] @ 0x54 8016800: 2b00 cmp r3, #0 8016802: d002 beq.n 801680a { *pxHigherPriorityTaskWoken = pdTRUE; 8016804: 6d7b ldr r3, [r7, #84] @ 0x54 8016806: 2201 movs r2, #1 8016808: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not * using the "xHigherPriorityTaskWoken" parameter to an ISR * safe FreeRTOS function. */ xYieldPending = pdTRUE; 801680a: 4b0d ldr r3, [pc, #52] @ (8016840 ) 801680c: 2201 movs r2, #1 801680e: 601a str r2, [r3, #0] 8016810: 6bfb ldr r3, [r7, #60] @ 0x3c 8016812: 613b str r3, [r7, #16] __asm volatile 8016814: 693b ldr r3, [r7, #16] 8016816: f383 8811 msr BASEPRI, r3 } 801681a: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801681c: 6c7b ldr r3, [r7, #68] @ 0x44 } 801681e: 4618 mov r0, r3 8016820: 3748 adds r7, #72 @ 0x48 8016822: 46bd mov sp, r7 8016824: bd80 pop {r7, pc} 8016826: bf00 nop 8016828: 200025a0 .word 0x200025a0 801682c: 200025c4 .word 0x200025c4 8016830: 200025a4 .word 0x200025a4 8016834: 200020cc .word 0x200020cc 8016838: 2000255c .word 0x2000255c 801683c: 200020c8 .word 0x200020c8 8016840: 200025b0 .word 0x200025b0 08016844 : #if ( configUSE_TASK_NOTIFICATIONS == 1 ) void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, BaseType_t * pxHigherPriorityTaskWoken ) { 8016844: b580 push {r7, lr} 8016846: b090 sub sp, #64 @ 0x40 8016848: af00 add r7, sp, #0 801684a: 60f8 str r0, [r7, #12] 801684c: 60b9 str r1, [r7, #8] 801684e: 607a str r2, [r7, #4] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016850: 68fb ldr r3, [r7, #12] 8016852: 2b00 cmp r3, #0 8016854: d10b bne.n 801686e __asm volatile 8016856: f04f 0350 mov.w r3, #80 @ 0x50 801685a: f383 8811 msr BASEPRI, r3 801685e: f3bf 8f6f isb sy 8016862: f3bf 8f4f dsb sy 8016866: 627b str r3, [r7, #36] @ 0x24 } 8016868: bf00 nop 801686a: bf00 nop 801686c: e7fd b.n 801686a configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 801686e: 68bb ldr r3, [r7, #8] 8016870: 2b00 cmp r3, #0 8016872: d00b beq.n 801688c __asm volatile 8016874: f04f 0350 mov.w r3, #80 @ 0x50 8016878: f383 8811 msr BASEPRI, r3 801687c: f3bf 8f6f isb sy 8016880: f3bf 8f4f dsb sy 8016884: 623b str r3, [r7, #32] } 8016886: bf00 nop 8016888: bf00 nop 801688a: e7fd b.n 8016888 * below the maximum system call interrupt priority. FreeRTOS maintains a * separate interrupt safe API to ensure interrupt entry is as fast and as * simple as possible. More information (albeit Cortex-M specific) is * provided on the following link: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 801688c: f000 fe4e bl 801752c pxTCB = xTaskToNotify; 8016890: 68fb ldr r3, [r7, #12] 8016892: 63fb str r3, [r7, #60] @ 0x3c __asm volatile 8016894: f3ef 8211 mrs r2, BASEPRI 8016898: f04f 0350 mov.w r3, #80 @ 0x50 801689c: f383 8811 msr BASEPRI, r3 80168a0: f3bf 8f6f isb sy 80168a4: f3bf 8f4f dsb sy 80168a8: 61fa str r2, [r7, #28] 80168aa: 61bb str r3, [r7, #24] return ulOriginalBASEPRI; 80168ac: 69fb ldr r3, [r7, #28] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80168ae: 63bb str r3, [r7, #56] @ 0x38 { ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; 80168b0: 6bfa ldr r2, [r7, #60] @ 0x3c 80168b2: 68bb ldr r3, [r7, #8] 80168b4: 4413 add r3, r2 80168b6: 3358 adds r3, #88 @ 0x58 80168b8: 781b ldrb r3, [r3, #0] 80168ba: f887 3037 strb.w r3, [r7, #55] @ 0x37 pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; 80168be: 6bfa ldr r2, [r7, #60] @ 0x3c 80168c0: 68bb ldr r3, [r7, #8] 80168c2: 4413 add r3, r2 80168c4: 3358 adds r3, #88 @ 0x58 80168c6: 2202 movs r2, #2 80168c8: 701a strb r2, [r3, #0] /* 'Giving' is equivalent to incrementing a count in a counting * semaphore. */ ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; 80168ca: 6bfa ldr r2, [r7, #60] @ 0x3c 80168cc: 68bb ldr r3, [r7, #8] 80168ce: 3314 adds r3, #20 80168d0: 009b lsls r3, r3, #2 80168d2: 4413 add r3, r2 80168d4: 685b ldr r3, [r3, #4] 80168d6: 1c5a adds r2, r3, #1 80168d8: 6bf9 ldr r1, [r7, #60] @ 0x3c 80168da: 68bb ldr r3, [r7, #8] 80168dc: 3314 adds r3, #20 80168de: 009b lsls r3, r3, #2 80168e0: 440b add r3, r1 80168e2: 605a str r2, [r3, #4] traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ); /* If the task is in the blocked state specifically to wait for a * notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 80168e4: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80168e8: 2b01 cmp r3, #1 80168ea: f040 80a0 bne.w 8016a2e { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 80168ee: 6bfb ldr r3, [r7, #60] @ 0x3c 80168f0: 6a9b ldr r3, [r3, #40] @ 0x28 80168f2: 2b00 cmp r3, #0 80168f4: d00b beq.n 801690e __asm volatile 80168f6: f04f 0350 mov.w r3, #80 @ 0x50 80168fa: f383 8811 msr BASEPRI, r3 80168fe: f3bf 8f6f isb sy 8016902: f3bf 8f4f dsb sy 8016906: 617b str r3, [r7, #20] } 8016908: bf00 nop 801690a: bf00 nop 801690c: e7fd b.n 801690a if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 801690e: 4b4d ldr r3, [pc, #308] @ (8016a44 ) 8016910: 681b ldr r3, [r3, #0] 8016912: 2b00 cmp r3, #0 8016914: d15f bne.n 80169d6 { listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 8016916: 6bfb ldr r3, [r7, #60] @ 0x3c 8016918: 695b ldr r3, [r3, #20] 801691a: 62fb str r3, [r7, #44] @ 0x2c 801691c: 6bfb ldr r3, [r7, #60] @ 0x3c 801691e: 689b ldr r3, [r3, #8] 8016920: 6bfa ldr r2, [r7, #60] @ 0x3c 8016922: 68d2 ldr r2, [r2, #12] 8016924: 609a str r2, [r3, #8] 8016926: 6bfb ldr r3, [r7, #60] @ 0x3c 8016928: 68db ldr r3, [r3, #12] 801692a: 6bfa ldr r2, [r7, #60] @ 0x3c 801692c: 6892 ldr r2, [r2, #8] 801692e: 605a str r2, [r3, #4] 8016930: 6afb ldr r3, [r7, #44] @ 0x2c 8016932: 685a ldr r2, [r3, #4] 8016934: 6bfb ldr r3, [r7, #60] @ 0x3c 8016936: 3304 adds r3, #4 8016938: 429a cmp r2, r3 801693a: d103 bne.n 8016944 801693c: 6bfb ldr r3, [r7, #60] @ 0x3c 801693e: 68da ldr r2, [r3, #12] 8016940: 6afb ldr r3, [r7, #44] @ 0x2c 8016942: 605a str r2, [r3, #4] 8016944: 6bfb ldr r3, [r7, #60] @ 0x3c 8016946: 2200 movs r2, #0 8016948: 615a str r2, [r3, #20] 801694a: 6afb ldr r3, [r7, #44] @ 0x2c 801694c: 681b ldr r3, [r3, #0] 801694e: 1e5a subs r2, r3, #1 8016950: 6afb ldr r3, [r7, #44] @ 0x2c 8016952: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxTCB ); 8016954: 6bfb ldr r3, [r7, #60] @ 0x3c 8016956: 6ada ldr r2, [r3, #44] @ 0x2c 8016958: 4b3b ldr r3, [pc, #236] @ (8016a48 ) 801695a: 681b ldr r3, [r3, #0] 801695c: 429a cmp r2, r3 801695e: d903 bls.n 8016968 8016960: 6bfb ldr r3, [r7, #60] @ 0x3c 8016962: 6adb ldr r3, [r3, #44] @ 0x2c 8016964: 4a38 ldr r2, [pc, #224] @ (8016a48 ) 8016966: 6013 str r3, [r2, #0] 8016968: 6bfb ldr r3, [r7, #60] @ 0x3c 801696a: 6ada ldr r2, [r3, #44] @ 0x2c 801696c: 4937 ldr r1, [pc, #220] @ (8016a4c ) 801696e: 4613 mov r3, r2 8016970: 009b lsls r3, r3, #2 8016972: 4413 add r3, r2 8016974: 009b lsls r3, r3, #2 8016976: 440b add r3, r1 8016978: 3304 adds r3, #4 801697a: 681b ldr r3, [r3, #0] 801697c: 62bb str r3, [r7, #40] @ 0x28 801697e: 6bfb ldr r3, [r7, #60] @ 0x3c 8016980: 6aba ldr r2, [r7, #40] @ 0x28 8016982: 609a str r2, [r3, #8] 8016984: 6abb ldr r3, [r7, #40] @ 0x28 8016986: 689a ldr r2, [r3, #8] 8016988: 6bfb ldr r3, [r7, #60] @ 0x3c 801698a: 60da str r2, [r3, #12] 801698c: 6abb ldr r3, [r7, #40] @ 0x28 801698e: 689b ldr r3, [r3, #8] 8016990: 6bfa ldr r2, [r7, #60] @ 0x3c 8016992: 3204 adds r2, #4 8016994: 605a str r2, [r3, #4] 8016996: 6bfb ldr r3, [r7, #60] @ 0x3c 8016998: 1d1a adds r2, r3, #4 801699a: 6abb ldr r3, [r7, #40] @ 0x28 801699c: 609a str r2, [r3, #8] 801699e: 6bfb ldr r3, [r7, #60] @ 0x3c 80169a0: 6ada ldr r2, [r3, #44] @ 0x2c 80169a2: 4613 mov r3, r2 80169a4: 009b lsls r3, r3, #2 80169a6: 4413 add r3, r2 80169a8: 009b lsls r3, r3, #2 80169aa: 4a28 ldr r2, [pc, #160] @ (8016a4c ) 80169ac: 441a add r2, r3 80169ae: 6bfb ldr r3, [r7, #60] @ 0x3c 80169b0: 615a str r2, [r3, #20] 80169b2: 6bfb ldr r3, [r7, #60] @ 0x3c 80169b4: 6ada ldr r2, [r3, #44] @ 0x2c 80169b6: 4925 ldr r1, [pc, #148] @ (8016a4c ) 80169b8: 4613 mov r3, r2 80169ba: 009b lsls r3, r3, #2 80169bc: 4413 add r3, r2 80169be: 009b lsls r3, r3, #2 80169c0: 440b add r3, r1 80169c2: 681b ldr r3, [r3, #0] 80169c4: 1c59 adds r1, r3, #1 80169c6: 4821 ldr r0, [pc, #132] @ (8016a4c ) 80169c8: 4613 mov r3, r2 80169ca: 009b lsls r3, r3, #2 80169cc: 4413 add r3, r2 80169ce: 009b lsls r3, r3, #2 80169d0: 4403 add r3, r0 80169d2: 6019 str r1, [r3, #0] 80169d4: e01b b.n 8016a0e } else { /* The delayed and ready lists cannot be accessed, so hold * this task pending until the scheduler is resumed. */ listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 80169d6: 4b1e ldr r3, [pc, #120] @ (8016a50 ) 80169d8: 685b ldr r3, [r3, #4] 80169da: 633b str r3, [r7, #48] @ 0x30 80169dc: 6bfb ldr r3, [r7, #60] @ 0x3c 80169de: 6b3a ldr r2, [r7, #48] @ 0x30 80169e0: 61da str r2, [r3, #28] 80169e2: 6b3b ldr r3, [r7, #48] @ 0x30 80169e4: 689a ldr r2, [r3, #8] 80169e6: 6bfb ldr r3, [r7, #60] @ 0x3c 80169e8: 621a str r2, [r3, #32] 80169ea: 6b3b ldr r3, [r7, #48] @ 0x30 80169ec: 689b ldr r3, [r3, #8] 80169ee: 6bfa ldr r2, [r7, #60] @ 0x3c 80169f0: 3218 adds r2, #24 80169f2: 605a str r2, [r3, #4] 80169f4: 6bfb ldr r3, [r7, #60] @ 0x3c 80169f6: f103 0218 add.w r2, r3, #24 80169fa: 6b3b ldr r3, [r7, #48] @ 0x30 80169fc: 609a str r2, [r3, #8] 80169fe: 6bfb ldr r3, [r7, #60] @ 0x3c 8016a00: 4a13 ldr r2, [pc, #76] @ (8016a50 ) 8016a02: 629a str r2, [r3, #40] @ 0x28 8016a04: 4b12 ldr r3, [pc, #72] @ (8016a50 ) 8016a06: 681b ldr r3, [r3, #0] 8016a08: 3301 adds r3, #1 8016a0a: 4a11 ldr r2, [pc, #68] @ (8016a50 ) 8016a0c: 6013 str r3, [r2, #0] } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016a0e: 6bfb ldr r3, [r7, #60] @ 0x3c 8016a10: 6ada ldr r2, [r3, #44] @ 0x2c 8016a12: 4b10 ldr r3, [pc, #64] @ (8016a54 ) 8016a14: 681b ldr r3, [r3, #0] 8016a16: 6adb ldr r3, [r3, #44] @ 0x2c 8016a18: 429a cmp r2, r3 8016a1a: d908 bls.n 8016a2e { /* The notified task has a priority above the currently * executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8016a1c: 687b ldr r3, [r7, #4] 8016a1e: 2b00 cmp r3, #0 8016a20: d002 beq.n 8016a28 { *pxHigherPriorityTaskWoken = pdTRUE; 8016a22: 687b ldr r3, [r7, #4] 8016a24: 2201 movs r2, #1 8016a26: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not * using the "xHigherPriorityTaskWoken" parameter in an ISR * safe FreeRTOS function. */ xYieldPending = pdTRUE; 8016a28: 4b0b ldr r3, [pc, #44] @ (8016a58 ) 8016a2a: 2201 movs r2, #1 8016a2c: 601a str r2, [r3, #0] 8016a2e: 6bbb ldr r3, [r7, #56] @ 0x38 8016a30: 613b str r3, [r7, #16] __asm volatile 8016a32: 693b ldr r3, [r7, #16] 8016a34: f383 8811 msr BASEPRI, r3 } 8016a38: bf00 nop mtCOVERAGE_TEST_MARKER(); } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); } 8016a3a: bf00 nop 8016a3c: 3740 adds r7, #64 @ 0x40 8016a3e: 46bd mov sp, r7 8016a40: bd80 pop {r7, pc} 8016a42: bf00 nop 8016a44: 200025c4 .word 0x200025c4 8016a48: 200025a4 .word 0x200025a4 8016a4c: 200020cc .word 0x200020cc 8016a50: 2000255c .word 0x2000255c 8016a54: 200020c8 .word 0x200020c8 8016a58: 200025b0 .word 0x200025b0 08016a5c : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8016a5c: b580 push {r7, lr} 8016a5e: b086 sub sp, #24 8016a60: af00 add r7, sp, #0 8016a62: 6078 str r0, [r7, #4] 8016a64: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8016a66: 4b2e ldr r3, [pc, #184] @ (8016b20 ) 8016a68: 681b ldr r3, [r3, #0] 8016a6a: 617b str r3, [r7, #20] } #endif /* Remove the task from the ready list before adding it to the blocked list * as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016a6c: 4b2d ldr r3, [pc, #180] @ (8016b24 ) 8016a6e: 681b ldr r3, [r3, #0] 8016a70: 3304 adds r3, #4 8016a72: 4618 mov r0, r3 8016a74: f7fc fffc bl 8013a70 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8016a78: 687b ldr r3, [r7, #4] 8016a7a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016a7e: d124 bne.n 8016aca 8016a80: 683b ldr r3, [r7, #0] 8016a82: 2b00 cmp r3, #0 8016a84: d021 beq.n 8016aca { /* Add the task to the suspended task list instead of a delayed task * list to ensure it is not woken by a timing event. It will block * indefinitely. */ listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8016a86: 4b28 ldr r3, [pc, #160] @ (8016b28 ) 8016a88: 685b ldr r3, [r3, #4] 8016a8a: 613b str r3, [r7, #16] 8016a8c: 4b25 ldr r3, [pc, #148] @ (8016b24 ) 8016a8e: 681b ldr r3, [r3, #0] 8016a90: 693a ldr r2, [r7, #16] 8016a92: 609a str r2, [r3, #8] 8016a94: 4b23 ldr r3, [pc, #140] @ (8016b24 ) 8016a96: 681b ldr r3, [r3, #0] 8016a98: 693a ldr r2, [r7, #16] 8016a9a: 6892 ldr r2, [r2, #8] 8016a9c: 60da str r2, [r3, #12] 8016a9e: 4b21 ldr r3, [pc, #132] @ (8016b24 ) 8016aa0: 681a ldr r2, [r3, #0] 8016aa2: 693b ldr r3, [r7, #16] 8016aa4: 689b ldr r3, [r3, #8] 8016aa6: 3204 adds r2, #4 8016aa8: 605a str r2, [r3, #4] 8016aaa: 4b1e ldr r3, [pc, #120] @ (8016b24 ) 8016aac: 681b ldr r3, [r3, #0] 8016aae: 1d1a adds r2, r3, #4 8016ab0: 693b ldr r3, [r7, #16] 8016ab2: 609a str r2, [r3, #8] 8016ab4: 4b1b ldr r3, [pc, #108] @ (8016b24 ) 8016ab6: 681b ldr r3, [r3, #0] 8016ab8: 4a1b ldr r2, [pc, #108] @ (8016b28 ) 8016aba: 615a str r2, [r3, #20] 8016abc: 4b1a ldr r3, [pc, #104] @ (8016b28 ) 8016abe: 681b ldr r3, [r3, #0] 8016ac0: 3301 adds r3, #1 8016ac2: 4a19 ldr r2, [pc, #100] @ (8016b28 ) 8016ac4: 6013 str r3, [r2, #0] 8016ac6: bf00 nop /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8016ac8: e026 b.n 8016b18 xTimeToWake = xConstTickCount + xTicksToWait; 8016aca: 697a ldr r2, [r7, #20] 8016acc: 687b ldr r3, [r7, #4] 8016ace: 4413 add r3, r2 8016ad0: 60fb str r3, [r7, #12] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 8016ad2: 4b14 ldr r3, [pc, #80] @ (8016b24 ) 8016ad4: 681b ldr r3, [r3, #0] 8016ad6: 68fa ldr r2, [r7, #12] 8016ad8: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 8016ada: 68fa ldr r2, [r7, #12] 8016adc: 697b ldr r3, [r7, #20] 8016ade: 429a cmp r2, r3 8016ae0: d209 bcs.n 8016af6 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8016ae2: 4b12 ldr r3, [pc, #72] @ (8016b2c ) 8016ae4: 681a ldr r2, [r3, #0] 8016ae6: 4b0f ldr r3, [pc, #60] @ (8016b24 ) 8016ae8: 681b ldr r3, [r3, #0] 8016aea: 3304 adds r3, #4 8016aec: 4619 mov r1, r3 8016aee: 4610 mov r0, r2 8016af0: f7fc ff85 bl 80139fe } 8016af4: e010 b.n 8016b18 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8016af6: 4b0e ldr r3, [pc, #56] @ (8016b30 ) 8016af8: 681a ldr r2, [r3, #0] 8016afa: 4b0a ldr r3, [pc, #40] @ (8016b24 ) 8016afc: 681b ldr r3, [r3, #0] 8016afe: 3304 adds r3, #4 8016b00: 4619 mov r1, r3 8016b02: 4610 mov r0, r2 8016b04: f7fc ff7b bl 80139fe if( xTimeToWake < xNextTaskUnblockTime ) 8016b08: 4b0a ldr r3, [pc, #40] @ (8016b34 ) 8016b0a: 681b ldr r3, [r3, #0] 8016b0c: 68fa ldr r2, [r7, #12] 8016b0e: 429a cmp r2, r3 8016b10: d202 bcs.n 8016b18 xNextTaskUnblockTime = xTimeToWake; 8016b12: 4a08 ldr r2, [pc, #32] @ (8016b34 ) 8016b14: 68fb ldr r3, [r7, #12] 8016b16: 6013 str r3, [r2, #0] } 8016b18: bf00 nop 8016b1a: 3718 adds r7, #24 8016b1c: 46bd mov sp, r7 8016b1e: bd80 pop {r7, pc} 8016b20: 200025a0 .word 0x200025a0 8016b24: 200020c8 .word 0x200020c8 8016b28: 20002588 .word 0x20002588 8016b2c: 20002558 .word 0x20002558 8016b30: 20002554 .word 0x20002554 8016b34: 200025bc .word 0x200025bc 08016b38 : TimerCallbackFunction_t pxCallbackFunction, Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8016b38: b580 push {r7, lr} 8016b3a: b08a sub sp, #40 @ 0x28 8016b3c: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 8016b3e: 2300 movs r3, #0 8016b40: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if * configUSE_TIMERS is set to 1. Check that the infrastructure used by the * timer service task has been created/initialised. If timers have already * been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 8016b42: f000 fa81 bl 8017048 if( xTimerQueue != NULL ) 8016b46: 4b1d ldr r3, [pc, #116] @ (8016bbc ) 8016b48: 681b ldr r3, [r3, #0] 8016b4a: 2b00 cmp r3, #0 8016b4c: d021 beq.n 8016b92 { #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t * pxTimerTaskTCBBuffer = NULL; 8016b4e: 2300 movs r3, #0 8016b50: 60fb str r3, [r7, #12] StackType_t * pxTimerTaskStackBuffer = NULL; 8016b52: 2300 movs r3, #0 8016b54: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 8016b56: 1d3a adds r2, r7, #4 8016b58: f107 0108 add.w r1, r7, #8 8016b5c: f107 030c add.w r3, r7, #12 8016b60: 4618 mov r0, r3 8016b62: f7fc ff05 bl 8013970 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 8016b66: 6879 ldr r1, [r7, #4] 8016b68: 68bb ldr r3, [r7, #8] 8016b6a: 68fa ldr r2, [r7, #12] 8016b6c: 9202 str r2, [sp, #8] 8016b6e: 9301 str r3, [sp, #4] 8016b70: 2302 movs r3, #2 8016b72: 9300 str r3, [sp, #0] 8016b74: 2300 movs r3, #0 8016b76: 460a mov r2, r1 8016b78: 4911 ldr r1, [pc, #68] @ (8016bc0 ) 8016b7a: 4812 ldr r0, [pc, #72] @ (8016bc4 ) 8016b7c: f7fe f90c bl 8014d98 8016b80: 4603 mov r3, r0 8016b82: 4a11 ldr r2, [pc, #68] @ (8016bc8 ) 8016b84: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 8016b86: 4b10 ldr r3, [pc, #64] @ (8016bc8 ) 8016b88: 681b ldr r3, [r3, #0] 8016b8a: 2b00 cmp r3, #0 8016b8c: d001 beq.n 8016b92 { xReturn = pdPASS; 8016b8e: 2301 movs r3, #1 8016b90: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 8016b92: 697b ldr r3, [r7, #20] 8016b94: 2b00 cmp r3, #0 8016b96: d10b bne.n 8016bb0 __asm volatile 8016b98: f04f 0350 mov.w r3, #80 @ 0x50 8016b9c: f383 8811 msr BASEPRI, r3 8016ba0: f3bf 8f6f isb sy 8016ba4: f3bf 8f4f dsb sy 8016ba8: 613b str r3, [r7, #16] } 8016baa: bf00 nop 8016bac: bf00 nop 8016bae: e7fd b.n 8016bac return xReturn; 8016bb0: 697b ldr r3, [r7, #20] } 8016bb2: 4618 mov r0, r3 8016bb4: 3718 adds r7, #24 8016bb6: 46bd mov sp, r7 8016bb8: bd80 pop {r7, pc} 8016bba: bf00 nop 8016bbc: 200025f8 .word 0x200025f8 8016bc0: 0801d9c4 .word 0x0801d9c4 8016bc4: 08016c71 .word 0x08016c71 8016bc8: 200025fc .word 0x200025fc 08016bcc : /*-----------------------------------------------------------*/ static void prvReloadTimer( Timer_t * const pxTimer, TickType_t xExpiredTime, const TickType_t xTimeNow ) { 8016bcc: b580 push {r7, lr} 8016bce: b084 sub sp, #16 8016bd0: af00 add r7, sp, #0 8016bd2: 60f8 str r0, [r7, #12] 8016bd4: 60b9 str r1, [r7, #8] 8016bd6: 607a str r2, [r7, #4] /* Insert the timer into the appropriate list for the next expiry time. * If the next expiry time has already passed, advance the expiry time, * call the callback function, and try again. */ while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE ) 8016bd8: e008 b.n 8016bec { /* Advance the expiry time. */ xExpiredTime += pxTimer->xTimerPeriodInTicks; 8016bda: 68fb ldr r3, [r7, #12] 8016bdc: 699b ldr r3, [r3, #24] 8016bde: 68ba ldr r2, [r7, #8] 8016be0: 4413 add r3, r2 8016be2: 60bb str r3, [r7, #8] /* Call the timer callback. */ traceTIMER_EXPIRED( pxTimer ); pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016be4: 68fb ldr r3, [r7, #12] 8016be6: 6a1b ldr r3, [r3, #32] 8016be8: 68f8 ldr r0, [r7, #12] 8016bea: 4798 blx r3 while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE ) 8016bec: 68fb ldr r3, [r7, #12] 8016bee: 699a ldr r2, [r3, #24] 8016bf0: 68bb ldr r3, [r7, #8] 8016bf2: 18d1 adds r1, r2, r3 8016bf4: 68bb ldr r3, [r7, #8] 8016bf6: 687a ldr r2, [r7, #4] 8016bf8: 68f8 ldr r0, [r7, #12] 8016bfa: f000 f8df bl 8016dbc 8016bfe: 4603 mov r3, r0 8016c00: 2b00 cmp r3, #0 8016c02: d1ea bne.n 8016bda } } 8016c04: bf00 nop 8016c06: bf00 nop 8016c08: 3710 adds r7, #16 8016c0a: 46bd mov sp, r7 8016c0c: bd80 pop {r7, pc} ... 08016c10 : /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 8016c10: b580 push {r7, lr} 8016c12: b084 sub sp, #16 8016c14: af00 add r7, sp, #0 8016c16: 6078 str r0, [r7, #4] 8016c18: 6039 str r1, [r7, #0] Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016c1a: 4b14 ldr r3, [pc, #80] @ (8016c6c ) 8016c1c: 681b ldr r3, [r3, #0] 8016c1e: 68db ldr r3, [r3, #12] 8016c20: 68db ldr r3, [r3, #12] 8016c22: 60fb str r3, [r7, #12] /* Remove the timer from the list of active timers. A check has already * been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016c24: 68fb ldr r3, [r7, #12] 8016c26: 3304 adds r3, #4 8016c28: 4618 mov r0, r3 8016c2a: f7fc ff21 bl 8013a70 /* If the timer is an auto-reload timer then calculate the next * expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016c2e: 68fb ldr r3, [r7, #12] 8016c30: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016c34: f003 0304 and.w r3, r3, #4 8016c38: 2b00 cmp r3, #0 8016c3a: d005 beq.n 8016c48 { prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow ); 8016c3c: 683a ldr r2, [r7, #0] 8016c3e: 6879 ldr r1, [r7, #4] 8016c40: 68f8 ldr r0, [r7, #12] 8016c42: f7ff ffc3 bl 8016bcc 8016c46: e008 b.n 8016c5a } else { pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); 8016c48: 68fb ldr r3, [r7, #12] 8016c4a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016c4e: f023 0301 bic.w r3, r3, #1 8016c52: b2da uxtb r2, r3 8016c54: 68fb ldr r3, [r7, #12] 8016c56: f883 2028 strb.w r2, [r3, #40] @ 0x28 } /* Call the timer callback. */ traceTIMER_EXPIRED( pxTimer ); pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016c5a: 68fb ldr r3, [r7, #12] 8016c5c: 6a1b ldr r3, [r3, #32] 8016c5e: 68f8 ldr r0, [r7, #12] 8016c60: 4798 blx r3 } 8016c62: bf00 nop 8016c64: 3710 adds r7, #16 8016c66: 46bd mov sp, r7 8016c68: bd80 pop {r7, pc} 8016c6a: bf00 nop 8016c6c: 200025f0 .word 0x200025f0 08016c70 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8016c70: b580 push {r7, lr} 8016c72: b084 sub sp, #16 8016c74: af00 add r7, sp, #0 8016c76: 6078 str r0, [r7, #4] for( ; ; ) { /* Query the timers list to see if it contains any timers, and if so, * obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8016c78: f107 0308 add.w r3, r7, #8 8016c7c: 4618 mov r0, r3 8016c7e: f000 f859 bl 8016d34 8016c82: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task * until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 8016c84: 68bb ldr r3, [r7, #8] 8016c86: 4619 mov r1, r3 8016c88: 68f8 ldr r0, [r7, #12] 8016c8a: f000 f805 bl 8016c98 /* Empty the command queue. */ prvProcessReceivedCommands(); 8016c8e: f000 f8d7 bl 8016e40 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8016c92: bf00 nop 8016c94: e7f0 b.n 8016c78 ... 08016c98 : } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8016c98: b580 push {r7, lr} 8016c9a: b084 sub sp, #16 8016c9c: af00 add r7, sp, #0 8016c9e: 6078 str r0, [r7, #4] 8016ca0: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 8016ca2: f7fe faf3 bl 801528c /* Obtain the time now to make an assessment as to whether the timer * has expired or not. If obtaining the time causes the lists to switch * then don't process this timer as any timers that remained in the list * when the lists were switched will have been processed within the * prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8016ca6: f107 0308 add.w r3, r7, #8 8016caa: 4618 mov r0, r3 8016cac: f000 f866 bl 8016d7c 8016cb0: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 8016cb2: 68bb ldr r3, [r7, #8] 8016cb4: 2b00 cmp r3, #0 8016cb6: d130 bne.n 8016d1a { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8016cb8: 683b ldr r3, [r7, #0] 8016cba: 2b00 cmp r3, #0 8016cbc: d10a bne.n 8016cd4 8016cbe: 687a ldr r2, [r7, #4] 8016cc0: 68fb ldr r3, [r7, #12] 8016cc2: 429a cmp r2, r3 8016cc4: d806 bhi.n 8016cd4 { ( void ) xTaskResumeAll(); 8016cc6: f7fe faef bl 80152a8 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8016cca: 68f9 ldr r1, [r7, #12] 8016ccc: 6878 ldr r0, [r7, #4] 8016cce: f7ff ff9f bl 8016c10 else { ( void ) xTaskResumeAll(); } } } 8016cd2: e024 b.n 8016d1e if( xListWasEmpty != pdFALSE ) 8016cd4: 683b ldr r3, [r7, #0] 8016cd6: 2b00 cmp r3, #0 8016cd8: d008 beq.n 8016cec xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8016cda: 4b13 ldr r3, [pc, #76] @ (8016d28 ) 8016cdc: 681b ldr r3, [r3, #0] 8016cde: 681b ldr r3, [r3, #0] 8016ce0: 2b00 cmp r3, #0 8016ce2: d101 bne.n 8016ce8 8016ce4: 2301 movs r3, #1 8016ce6: e000 b.n 8016cea 8016ce8: 2300 movs r3, #0 8016cea: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 8016cec: 4b0f ldr r3, [pc, #60] @ (8016d2c ) 8016cee: 6818 ldr r0, [r3, #0] 8016cf0: 687a ldr r2, [r7, #4] 8016cf2: 68fb ldr r3, [r7, #12] 8016cf4: 1ad3 subs r3, r2, r3 8016cf6: 683a ldr r2, [r7, #0] 8016cf8: 4619 mov r1, r3 8016cfa: f7fe f819 bl 8014d30 if( xTaskResumeAll() == pdFALSE ) 8016cfe: f7fe fad3 bl 80152a8 8016d02: 4603 mov r3, r0 8016d04: 2b00 cmp r3, #0 8016d06: d10a bne.n 8016d1e portYIELD_WITHIN_API(); 8016d08: 4b09 ldr r3, [pc, #36] @ (8016d30 ) 8016d0a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016d0e: 601a str r2, [r3, #0] 8016d10: f3bf 8f4f dsb sy 8016d14: f3bf 8f6f isb sy } 8016d18: e001 b.n 8016d1e ( void ) xTaskResumeAll(); 8016d1a: f7fe fac5 bl 80152a8 } 8016d1e: bf00 nop 8016d20: 3710 adds r7, #16 8016d22: 46bd mov sp, r7 8016d24: bd80 pop {r7, pc} 8016d26: bf00 nop 8016d28: 200025f4 .word 0x200025f4 8016d2c: 200025f8 .word 0x200025f8 8016d30: e000ed04 .word 0xe000ed04 08016d34 : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 8016d34: b480 push {r7} 8016d36: b085 sub sp, #20 8016d38: af00 add r7, sp, #0 8016d3a: 6078 str r0, [r7, #4] * the timer with the nearest expiry time will expire. If there are no * active timers then just set the next expire time to 0. That will cause * this task to unblock when the tick count overflows, at which point the * timer lists will be switched and the next expiry time can be * re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 8016d3c: 4b0e ldr r3, [pc, #56] @ (8016d78 ) 8016d3e: 681b ldr r3, [r3, #0] 8016d40: 681b ldr r3, [r3, #0] 8016d42: 2b00 cmp r3, #0 8016d44: d101 bne.n 8016d4a 8016d46: 2201 movs r2, #1 8016d48: e000 b.n 8016d4c 8016d4a: 2200 movs r2, #0 8016d4c: 687b ldr r3, [r7, #4] 8016d4e: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8016d50: 687b ldr r3, [r7, #4] 8016d52: 681b ldr r3, [r3, #0] 8016d54: 2b00 cmp r3, #0 8016d56: d105 bne.n 8016d64 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8016d58: 4b07 ldr r3, [pc, #28] @ (8016d78 ) 8016d5a: 681b ldr r3, [r3, #0] 8016d5c: 68db ldr r3, [r3, #12] 8016d5e: 681b ldr r3, [r3, #0] 8016d60: 60fb str r3, [r7, #12] 8016d62: e001 b.n 8016d68 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8016d64: 2300 movs r3, #0 8016d66: 60fb str r3, [r7, #12] } return xNextExpireTime; 8016d68: 68fb ldr r3, [r7, #12] } 8016d6a: 4618 mov r0, r3 8016d6c: 3714 adds r7, #20 8016d6e: 46bd mov sp, r7 8016d70: f85d 7b04 ldr.w r7, [sp], #4 8016d74: 4770 bx lr 8016d76: bf00 nop 8016d78: 200025f0 .word 0x200025f0 08016d7c : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 8016d7c: b580 push {r7, lr} 8016d7e: b084 sub sp, #16 8016d80: af00 add r7, sp, #0 8016d82: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 8016d84: f7fe fb8e bl 80154a4 8016d88: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8016d8a: 4b0b ldr r3, [pc, #44] @ (8016db8 ) 8016d8c: 681b ldr r3, [r3, #0] 8016d8e: 68fa ldr r2, [r7, #12] 8016d90: 429a cmp r2, r3 8016d92: d205 bcs.n 8016da0 { prvSwitchTimerLists(); 8016d94: f000 f932 bl 8016ffc *pxTimerListsWereSwitched = pdTRUE; 8016d98: 687b ldr r3, [r7, #4] 8016d9a: 2201 movs r2, #1 8016d9c: 601a str r2, [r3, #0] 8016d9e: e002 b.n 8016da6 } else { *pxTimerListsWereSwitched = pdFALSE; 8016da0: 687b ldr r3, [r7, #4] 8016da2: 2200 movs r2, #0 8016da4: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 8016da6: 4a04 ldr r2, [pc, #16] @ (8016db8 ) 8016da8: 68fb ldr r3, [r7, #12] 8016daa: 6013 str r3, [r2, #0] return xTimeNow; 8016dac: 68fb ldr r3, [r7, #12] } 8016dae: 4618 mov r0, r3 8016db0: 3710 adds r7, #16 8016db2: 46bd mov sp, r7 8016db4: bd80 pop {r7, pc} 8016db6: bf00 nop 8016db8: 20002600 .word 0x20002600 08016dbc : static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8016dbc: b580 push {r7, lr} 8016dbe: b086 sub sp, #24 8016dc0: af00 add r7, sp, #0 8016dc2: 60f8 str r0, [r7, #12] 8016dc4: 60b9 str r1, [r7, #8] 8016dc6: 607a str r2, [r7, #4] 8016dc8: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8016dca: 2300 movs r3, #0 8016dcc: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8016dce: 68fb ldr r3, [r7, #12] 8016dd0: 68ba ldr r2, [r7, #8] 8016dd2: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8016dd4: 68fb ldr r3, [r7, #12] 8016dd6: 68fa ldr r2, [r7, #12] 8016dd8: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8016dda: 68ba ldr r2, [r7, #8] 8016ddc: 687b ldr r3, [r7, #4] 8016dde: 429a cmp r2, r3 8016de0: d812 bhi.n 8016e08 { /* Has the expiry time elapsed between the command to start/reset a * timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016de2: 687a ldr r2, [r7, #4] 8016de4: 683b ldr r3, [r7, #0] 8016de6: 1ad2 subs r2, r2, r3 8016de8: 68fb ldr r3, [r7, #12] 8016dea: 699b ldr r3, [r3, #24] 8016dec: 429a cmp r2, r3 8016dee: d302 bcc.n 8016df6 { /* The time between a command being issued and the command being * processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8016df0: 2301 movs r3, #1 8016df2: 617b str r3, [r7, #20] 8016df4: e01b b.n 8016e2e } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 8016df6: 4b10 ldr r3, [pc, #64] @ (8016e38 ) 8016df8: 681a ldr r2, [r3, #0] 8016dfa: 68fb ldr r3, [r7, #12] 8016dfc: 3304 adds r3, #4 8016dfe: 4619 mov r1, r3 8016e00: 4610 mov r0, r2 8016e02: f7fc fdfc bl 80139fe 8016e06: e012 b.n 8016e2e } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 8016e08: 687a ldr r2, [r7, #4] 8016e0a: 683b ldr r3, [r7, #0] 8016e0c: 429a cmp r2, r3 8016e0e: d206 bcs.n 8016e1e 8016e10: 68ba ldr r2, [r7, #8] 8016e12: 683b ldr r3, [r7, #0] 8016e14: 429a cmp r2, r3 8016e16: d302 bcc.n 8016e1e { /* If, since the command was issued, the tick count has overflowed * but the expiry time has not, then the timer must have already passed * its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 8016e18: 2301 movs r3, #1 8016e1a: 617b str r3, [r7, #20] 8016e1c: e007 b.n 8016e2e } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8016e1e: 4b07 ldr r3, [pc, #28] @ (8016e3c ) 8016e20: 681a ldr r2, [r3, #0] 8016e22: 68fb ldr r3, [r7, #12] 8016e24: 3304 adds r3, #4 8016e26: 4619 mov r1, r3 8016e28: 4610 mov r0, r2 8016e2a: f7fc fde8 bl 80139fe } } return xProcessTimerNow; 8016e2e: 697b ldr r3, [r7, #20] } 8016e30: 4618 mov r0, r3 8016e32: 3718 adds r7, #24 8016e34: 46bd mov sp, r7 8016e36: bd80 pop {r7, pc} 8016e38: 200025f4 .word 0x200025f4 8016e3c: 200025f0 .word 0x200025f0 08016e40 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 8016e40: b580 push {r7, lr} 8016e42: b08a sub sp, #40 @ 0x28 8016e44: af00 add r7, sp, #0 DaemonTaskMessage_t xMessage; Timer_t * pxTimer; BaseType_t xTimerListsWereSwitched; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8016e46: e0c7 b.n 8016fd8 { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer * commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 8016e48: 687b ldr r3, [r7, #4] 8016e4a: 2b00 cmp r3, #0 8016e4c: da19 bge.n 8016e82 { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 8016e4e: 1d3b adds r3, r7, #4 8016e50: 3304 adds r3, #4 8016e52: 627b str r3, [r7, #36] @ 0x24 /* The timer uses the xCallbackParameters member to request a * callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 8016e54: 6a7b ldr r3, [r7, #36] @ 0x24 8016e56: 2b00 cmp r3, #0 8016e58: d10b bne.n 8016e72 __asm volatile 8016e5a: f04f 0350 mov.w r3, #80 @ 0x50 8016e5e: f383 8811 msr BASEPRI, r3 8016e62: f3bf 8f6f isb sy 8016e66: f3bf 8f4f dsb sy 8016e6a: 61bb str r3, [r7, #24] } 8016e6c: bf00 nop 8016e6e: bf00 nop 8016e70: e7fd b.n 8016e6e /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 8016e72: 6a7b ldr r3, [r7, #36] @ 0x24 8016e74: 681b ldr r3, [r3, #0] 8016e76: 6a7a ldr r2, [r7, #36] @ 0x24 8016e78: 6850 ldr r0, [r2, #4] 8016e7a: 6a7a ldr r2, [r7, #36] @ 0x24 8016e7c: 6892 ldr r2, [r2, #8] 8016e7e: 4611 mov r1, r2 8016e80: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended * function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 8016e82: 687b ldr r3, [r7, #4] 8016e84: 2b00 cmp r3, #0 8016e86: f2c0 80a7 blt.w 8016fd8 { /* The messages uses the xTimerParameters member to work on a * software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8016e8a: 68fb ldr r3, [r7, #12] 8016e8c: 623b str r3, [r7, #32] if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8016e8e: 6a3b ldr r3, [r7, #32] 8016e90: 695b ldr r3, [r3, #20] 8016e92: 2b00 cmp r3, #0 8016e94: d004 beq.n 8016ea0 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016e96: 6a3b ldr r3, [r7, #32] 8016e98: 3304 adds r3, #4 8016e9a: 4618 mov r0, r3 8016e9c: f7fc fde8 bl 8013a70 * it must be present in the function call. prvSampleTimeNow() must be * called after the message is received from xTimerQueue so there is no * possibility of a higher priority task adding a message to the message * queue with a time that is ahead of the timer daemon task (because it * pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8016ea0: 463b mov r3, r7 8016ea2: 4618 mov r0, r3 8016ea4: f7ff ff6a bl 8016d7c 8016ea8: 61f8 str r0, [r7, #28] switch( xMessage.xMessageID ) 8016eaa: 687b ldr r3, [r7, #4] 8016eac: 3b01 subs r3, #1 8016eae: 2b08 cmp r3, #8 8016eb0: f200 808f bhi.w 8016fd2 8016eb4: a201 add r2, pc, #4 @ (adr r2, 8016ebc ) 8016eb6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016eba: bf00 nop 8016ebc: 08016ee1 .word 0x08016ee1 8016ec0: 08016ee1 .word 0x08016ee1 8016ec4: 08016f49 .word 0x08016f49 8016ec8: 08016f5d .word 0x08016f5d 8016ecc: 08016fa9 .word 0x08016fa9 8016ed0: 08016ee1 .word 0x08016ee1 8016ed4: 08016ee1 .word 0x08016ee1 8016ed8: 08016f49 .word 0x08016f49 8016edc: 08016f5d .word 0x08016f5d case tmrCOMMAND_START: case tmrCOMMAND_START_FROM_ISR: case tmrCOMMAND_RESET: case tmrCOMMAND_RESET_FROM_ISR: /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8016ee0: 6a3b ldr r3, [r7, #32] 8016ee2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016ee6: f043 0301 orr.w r3, r3, #1 8016eea: b2da uxtb r2, r3 8016eec: 6a3b ldr r3, [r7, #32] 8016eee: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 8016ef2: 68ba ldr r2, [r7, #8] 8016ef4: 6a3b ldr r3, [r7, #32] 8016ef6: 699b ldr r3, [r3, #24] 8016ef8: 18d1 adds r1, r2, r3 8016efa: 68bb ldr r3, [r7, #8] 8016efc: 69fa ldr r2, [r7, #28] 8016efe: 6a38 ldr r0, [r7, #32] 8016f00: f7ff ff5c bl 8016dbc 8016f04: 4603 mov r3, r0 8016f06: 2b00 cmp r3, #0 8016f08: d065 beq.n 8016fd6 { /* The timer expired before it was added to the active * timer list. Process it now. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016f0a: 6a3b ldr r3, [r7, #32] 8016f0c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016f10: f003 0304 and.w r3, r3, #4 8016f14: 2b00 cmp r3, #0 8016f16: d009 beq.n 8016f2c { prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow ); 8016f18: 68ba ldr r2, [r7, #8] 8016f1a: 6a3b ldr r3, [r7, #32] 8016f1c: 699b ldr r3, [r3, #24] 8016f1e: 4413 add r3, r2 8016f20: 69fa ldr r2, [r7, #28] 8016f22: 4619 mov r1, r3 8016f24: 6a38 ldr r0, [r7, #32] 8016f26: f7ff fe51 bl 8016bcc 8016f2a: e008 b.n 8016f3e } else { pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); 8016f2c: 6a3b ldr r3, [r7, #32] 8016f2e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016f32: f023 0301 bic.w r3, r3, #1 8016f36: b2da uxtb r2, r3 8016f38: 6a3b ldr r3, [r7, #32] 8016f3a: f883 2028 strb.w r2, [r3, #40] @ 0x28 } /* Call the timer callback. */ traceTIMER_EXPIRED( pxTimer ); pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016f3e: 6a3b ldr r3, [r7, #32] 8016f40: 6a1b ldr r3, [r3, #32] 8016f42: 6a38 ldr r0, [r7, #32] 8016f44: 4798 blx r3 else { mtCOVERAGE_TEST_MARKER(); } break; 8016f46: e046 b.n 8016fd6 case tmrCOMMAND_STOP: case tmrCOMMAND_STOP_FROM_ISR: /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); 8016f48: 6a3b ldr r3, [r7, #32] 8016f4a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016f4e: f023 0301 bic.w r3, r3, #1 8016f52: b2da uxtb r2, r3 8016f54: 6a3b ldr r3, [r7, #32] 8016f56: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8016f5a: e03d b.n 8016fd8 case tmrCOMMAND_CHANGE_PERIOD: case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8016f5c: 6a3b ldr r3, [r7, #32] 8016f5e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016f62: f043 0301 orr.w r3, r3, #1 8016f66: b2da uxtb r2, r3 8016f68: 6a3b ldr r3, [r7, #32] 8016f6a: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 8016f6e: 68ba ldr r2, [r7, #8] 8016f70: 6a3b ldr r3, [r7, #32] 8016f72: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 8016f74: 6a3b ldr r3, [r7, #32] 8016f76: 699b ldr r3, [r3, #24] 8016f78: 2b00 cmp r3, #0 8016f7a: d10b bne.n 8016f94 __asm volatile 8016f7c: f04f 0350 mov.w r3, #80 @ 0x50 8016f80: f383 8811 msr BASEPRI, r3 8016f84: f3bf 8f6f isb sy 8016f88: f3bf 8f4f dsb sy 8016f8c: 617b str r3, [r7, #20] } 8016f8e: bf00 nop 8016f90: bf00 nop 8016f92: e7fd b.n 8016f90 * be longer or shorter than the old one. The command time is * therefore set to the current time, and as the period cannot * be zero the next expiry time can only be in the future, * meaning (unlike for the xTimerStart() case above) there is * no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 8016f94: 6a3b ldr r3, [r7, #32] 8016f96: 699a ldr r2, [r3, #24] 8016f98: 69fb ldr r3, [r7, #28] 8016f9a: 18d1 adds r1, r2, r3 8016f9c: 69fb ldr r3, [r7, #28] 8016f9e: 69fa ldr r2, [r7, #28] 8016fa0: 6a38 ldr r0, [r7, #32] 8016fa2: f7ff ff0b bl 8016dbc break; 8016fa6: e017 b.n 8016fd8 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, * just free up the memory if the memory was dynamically * allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 8016fa8: 6a3b ldr r3, [r7, #32] 8016faa: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016fae: f003 0302 and.w r3, r3, #2 8016fb2: 2b00 cmp r3, #0 8016fb4: d103 bne.n 8016fbe { vPortFree( pxTimer ); 8016fb6: 6a38 ldr r0, [r7, #32] 8016fb8: f000 fbc6 bl 8017748 * no need to free the memory - just mark the timer as * "not active". */ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 8016fbc: e00c b.n 8016fd8 pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); 8016fbe: 6a3b ldr r3, [r7, #32] 8016fc0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016fc4: f023 0301 bic.w r3, r3, #1 8016fc8: b2da uxtb r2, r3 8016fca: 6a3b ldr r3, [r7, #32] 8016fcc: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8016fd0: e002 b.n 8016fd8 default: /* Don't expect to get here. */ break; 8016fd2: bf00 nop 8016fd4: e000 b.n 8016fd8 break; 8016fd6: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8016fd8: 4b07 ldr r3, [pc, #28] @ (8016ff8 ) 8016fda: 681b ldr r3, [r3, #0] 8016fdc: 1d39 adds r1, r7, #4 8016fde: 2200 movs r2, #0 8016fe0: 4618 mov r0, r3 8016fe2: f7fd fa53 bl 801448c 8016fe6: 4603 mov r3, r0 8016fe8: 2b00 cmp r3, #0 8016fea: f47f af2d bne.w 8016e48 } } } } 8016fee: bf00 nop 8016ff0: bf00 nop 8016ff2: 3728 adds r7, #40 @ 0x28 8016ff4: 46bd mov sp, r7 8016ff6: bd80 pop {r7, pc} 8016ff8: 200025f8 .word 0x200025f8 08016ffc : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 8016ffc: b580 push {r7, lr} 8016ffe: b082 sub sp, #8 8017000: af00 add r7, sp, #0 /* The tick count has overflowed. The timer lists must be switched. * If there are any timers still referenced from the current timer list * then they must have expired and should be processed before the lists * are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8017002: e009 b.n 8017018 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8017004: 4b0e ldr r3, [pc, #56] @ (8017040 ) 8017006: 681b ldr r3, [r3, #0] 8017008: 68db ldr r3, [r3, #12] 801700a: 681b ldr r3, [r3, #0] 801700c: 603b str r3, [r7, #0] /* Process the expired timer. For auto-reload timers, be careful to * process only expirations that occur on the current list. Further * expirations must wait until after the lists are switched. */ prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW ); 801700e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8017012: 6838 ldr r0, [r7, #0] 8017014: f7ff fdfc bl 8016c10 while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8017018: 4b09 ldr r3, [pc, #36] @ (8017040 ) 801701a: 681b ldr r3, [r3, #0] 801701c: 681b ldr r3, [r3, #0] 801701e: 2b00 cmp r3, #0 8017020: d1f0 bne.n 8017004 } pxTemp = pxCurrentTimerList; 8017022: 4b07 ldr r3, [pc, #28] @ (8017040 ) 8017024: 681b ldr r3, [r3, #0] 8017026: 607b str r3, [r7, #4] pxCurrentTimerList = pxOverflowTimerList; 8017028: 4b06 ldr r3, [pc, #24] @ (8017044 ) 801702a: 681b ldr r3, [r3, #0] 801702c: 4a04 ldr r2, [pc, #16] @ (8017040 ) 801702e: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8017030: 4a04 ldr r2, [pc, #16] @ (8017044 ) 8017032: 687b ldr r3, [r7, #4] 8017034: 6013 str r3, [r2, #0] } 8017036: bf00 nop 8017038: 3708 adds r7, #8 801703a: 46bd mov sp, r7 801703c: bd80 pop {r7, pc} 801703e: bf00 nop 8017040: 200025f0 .word 0x200025f0 8017044: 200025f4 .word 0x200025f4 08017048 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8017048: b580 push {r7, lr} 801704a: b082 sub sp, #8 801704c: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the * queue used to communicate with the timer service, have been * initialised. */ taskENTER_CRITICAL(); 801704e: f000 f987 bl 8017360 { if( xTimerQueue == NULL ) 8017052: 4b15 ldr r3, [pc, #84] @ (80170a8 ) 8017054: 681b ldr r3, [r3, #0] 8017056: 2b00 cmp r3, #0 8017058: d120 bne.n 801709c { vListInitialise( &xActiveTimerList1 ); 801705a: 4814 ldr r0, [pc, #80] @ (80170ac ) 801705c: f7fc fca2 bl 80139a4 vListInitialise( &xActiveTimerList2 ); 8017060: 4813 ldr r0, [pc, #76] @ (80170b0 ) 8017062: f7fc fc9f bl 80139a4 pxCurrentTimerList = &xActiveTimerList1; 8017066: 4b13 ldr r3, [pc, #76] @ (80170b4 ) 8017068: 4a10 ldr r2, [pc, #64] @ (80170ac ) 801706a: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 801706c: 4b12 ldr r3, [pc, #72] @ (80170b8 ) 801706e: 4a10 ldr r2, [pc, #64] @ (80170b0 ) 8017070: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case * configSUPPORT_DYNAMIC_ALLOCATION is 0. */ PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 8017072: 2300 movs r3, #0 8017074: 9300 str r3, [sp, #0] 8017076: 4b11 ldr r3, [pc, #68] @ (80170bc ) 8017078: 4a11 ldr r2, [pc, #68] @ (80170c0 ) 801707a: 2110 movs r1, #16 801707c: 200a movs r0, #10 801707e: f7fc fdb3 bl 8013be8 8017082: 4603 mov r3, r0 8017084: 4a08 ldr r2, [pc, #32] @ (80170a8 ) 8017086: 6013 str r3, [r2, #0] } #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8017088: 4b07 ldr r3, [pc, #28] @ (80170a8 ) 801708a: 681b ldr r3, [r3, #0] 801708c: 2b00 cmp r3, #0 801708e: d005 beq.n 801709c { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8017090: 4b05 ldr r3, [pc, #20] @ (80170a8 ) 8017092: 681b ldr r3, [r3, #0] 8017094: 490b ldr r1, [pc, #44] @ (80170c4 ) 8017096: 4618 mov r0, r3 8017098: f7fd fdc0 bl 8014c1c else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 801709c: f000 f992 bl 80173c4 } 80170a0: bf00 nop 80170a2: 46bd mov sp, r7 80170a4: bd80 pop {r7, pc} 80170a6: bf00 nop 80170a8: 200025f8 .word 0x200025f8 80170ac: 200025c8 .word 0x200025c8 80170b0: 200025dc .word 0x200025dc 80170b4: 200025f0 .word 0x200025f0 80170b8: 200025f4 .word 0x200025f4 80170bc: 200026a4 .word 0x200026a4 80170c0: 20002604 .word 0x20002604 80170c4: 0801d9cc .word 0x0801d9cc 080170c8 : * See header file for description. */ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void * pvParameters ) { 80170c8: b480 push {r7} 80170ca: b085 sub sp, #20 80170cc: af00 add r7, sp, #0 80170ce: 60f8 str r0, [r7, #12] 80170d0: 60b9 str r1, [r7, #8] 80170d2: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch * interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit * of interrupts, and to ensure alignment. */ pxTopOfStack--; 80170d4: 68fb ldr r3, [r7, #12] 80170d6: 3b04 subs r3, #4 80170d8: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 80170da: 68fb ldr r3, [r7, #12] 80170dc: f04f 7280 mov.w r2, #16777216 @ 0x1000000 80170e0: 601a str r2, [r3, #0] pxTopOfStack--; 80170e2: 68fb ldr r3, [r7, #12] 80170e4: 3b04 subs r3, #4 80170e6: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 80170e8: 68bb ldr r3, [r7, #8] 80170ea: f023 0201 bic.w r2, r3, #1 80170ee: 68fb ldr r3, [r7, #12] 80170f0: 601a str r2, [r3, #0] pxTopOfStack--; 80170f2: 68fb ldr r3, [r7, #12] 80170f4: 3b04 subs r3, #4 80170f6: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 80170f8: 4a0c ldr r2, [pc, #48] @ (801712c ) 80170fa: 68fb ldr r3, [r7, #12] 80170fc: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 80170fe: 68fb ldr r3, [r7, #12] 8017100: 3b14 subs r3, #20 8017102: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8017104: 687a ldr r2, [r7, #4] 8017106: 68fb ldr r3, [r7, #12] 8017108: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its * own exec return value. */ pxTopOfStack--; 801710a: 68fb ldr r3, [r7, #12] 801710c: 3b04 subs r3, #4 801710e: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8017110: 68fb ldr r3, [r7, #12] 8017112: f06f 0202 mvn.w r2, #2 8017116: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8017118: 68fb ldr r3, [r7, #12] 801711a: 3b20 subs r3, #32 801711c: 60fb str r3, [r7, #12] return pxTopOfStack; 801711e: 68fb ldr r3, [r7, #12] } 8017120: 4618 mov r0, r3 8017122: 3714 adds r7, #20 8017124: 46bd mov sp, r7 8017126: f85d 7b04 ldr.w r7, [sp], #4 801712a: 4770 bx lr 801712c: 08017131 .word 0x08017131 08017130 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8017130: b480 push {r7} 8017132: b085 sub sp, #20 8017134: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8017136: 2300 movs r3, #0 8017138: 607b str r3, [r7, #4] * its caller as there is nothing to return to. If a task wants to exit it * should instead call vTaskDelete( NULL ). * * Artificially force an assert() to be triggered if configASSERT() is * defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 801713a: 4b13 ldr r3, [pc, #76] @ (8017188 ) 801713c: 681b ldr r3, [r3, #0] 801713e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017142: d00b beq.n 801715c __asm volatile 8017144: f04f 0350 mov.w r3, #80 @ 0x50 8017148: f383 8811 msr BASEPRI, r3 801714c: f3bf 8f6f isb sy 8017150: f3bf 8f4f dsb sy 8017154: 60fb str r3, [r7, #12] } 8017156: bf00 nop 8017158: bf00 nop 801715a: e7fd b.n 8017158 __asm volatile 801715c: f04f 0350 mov.w r3, #80 @ 0x50 8017160: f383 8811 msr BASEPRI, r3 8017164: f3bf 8f6f isb sy 8017168: f3bf 8f4f dsb sy 801716c: 60bb str r3, [r7, #8] } 801716e: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8017170: bf00 nop 8017172: 687b ldr r3, [r7, #4] 8017174: 2b00 cmp r3, #0 8017176: d0fc beq.n 8017172 * about code appearing after this function is called - making ulDummy * volatile makes the compiler think the function could return and * therefore not output an 'unreachable code' warning for code that appears * after it. */ } } 8017178: bf00 nop 801717a: bf00 nop 801717c: 3714 adds r7, #20 801717e: 46bd mov sp, r7 8017180: f85d 7b04 ldr.w r7, [sp], #4 8017184: 4770 bx lr 8017186: bf00 nop 8017188: 200000a4 .word 0x200000a4 801718c: 00000000 .word 0x00000000 08017190 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8017190: 4b07 ldr r3, [pc, #28] @ (80171b0 ) 8017192: 6819 ldr r1, [r3, #0] 8017194: 6808 ldr r0, [r1, #0] 8017196: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801719a: f380 8809 msr PSP, r0 801719e: f3bf 8f6f isb sy 80171a2: f04f 0000 mov.w r0, #0 80171a6: f380 8811 msr BASEPRI, r0 80171aa: 4770 bx lr 80171ac: f3af 8000 nop.w 080171b0 : 80171b0: 200020c8 .word 0x200020c8 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 80171b4: bf00 nop 80171b6: bf00 nop 080171b8 : { /* Start the first task. This also clears the bit that indicates the FPU is * in use in case the FPU was used before the scheduler was started - which * would otherwise result in the unnecessary leaving of space in the SVC stack * for lazy saving of FPU registers. */ __asm volatile ( 80171b8: 4808 ldr r0, [pc, #32] @ (80171dc ) 80171ba: 6800 ldr r0, [r0, #0] 80171bc: 6800 ldr r0, [r0, #0] 80171be: f380 8808 msr MSP, r0 80171c2: f04f 0000 mov.w r0, #0 80171c6: f380 8814 msr CONTROL, r0 80171ca: b662 cpsie i 80171cc: b661 cpsie f 80171ce: f3bf 8f4f dsb sy 80171d2: f3bf 8f6f isb sy 80171d6: df00 svc 0 80171d8: bf00 nop 80171da: 0000 .short 0x0000 80171dc: e000ed08 .word 0xe000ed08 " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" " .ltorg \n" ); } 80171e0: bf00 nop 80171e2: bf00 nop 080171e4 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 80171e4: b580 push {r7, lr} 80171e6: b088 sub sp, #32 80171e8: af00 add r7, sp, #0 /* This port can be used on all revisions of the Cortex-M7 core other than * the r0p1 parts. r0p1 parts should use the port from the * /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 80171ea: 4b54 ldr r3, [pc, #336] @ (801733c ) 80171ec: 681b ldr r3, [r3, #0] 80171ee: 4a54 ldr r2, [pc, #336] @ (8017340 ) 80171f0: 4293 cmp r3, r2 80171f2: d10b bne.n 801720c __asm volatile 80171f4: f04f 0350 mov.w r3, #80 @ 0x50 80171f8: f383 8811 msr BASEPRI, r3 80171fc: f3bf 8f6f isb sy 8017200: f3bf 8f4f dsb sy 8017204: 617b str r3, [r7, #20] } 8017206: bf00 nop 8017208: bf00 nop 801720a: e7fd b.n 8017208 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 801720c: 4b4b ldr r3, [pc, #300] @ (801733c ) 801720e: 681b ldr r3, [r3, #0] 8017210: 4a4c ldr r2, [pc, #304] @ (8017344 ) 8017212: 4293 cmp r3, r2 8017214: d10b bne.n 801722e __asm volatile 8017216: f04f 0350 mov.w r3, #80 @ 0x50 801721a: f383 8811 msr BASEPRI, r3 801721e: f3bf 8f6f isb sy 8017222: f3bf 8f4f dsb sy 8017226: 61bb str r3, [r7, #24] } 8017228: bf00 nop 801722a: bf00 nop 801722c: e7fd b.n 801722a #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; 801722e: 2300 movs r3, #0 8017230: 607b str r3, [r7, #4] volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 8017232: 4b45 ldr r3, [pc, #276] @ (8017348 ) 8017234: 61fb str r3, [r7, #28] * functions can be called. ISR safe functions are those that end in * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * * Save the interrupt priority value that is about to be clobbered. */ ucOriginalPriority = *pucFirstUserPriorityRegister; 8017236: 69fb ldr r3, [r7, #28] 8017238: 781b ldrb r3, [r3, #0] 801723a: b2db uxtb r3, r3 801723c: 72fb strb r3, [r7, #11] /* Determine the number of priority bits available. First write to all * possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 801723e: 69fb ldr r3, [r7, #28] 8017240: 22ff movs r2, #255 @ 0xff 8017242: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 8017244: 69fb ldr r3, [r7, #28] 8017246: 781b ldrb r3, [r3, #0] 8017248: b2db uxtb r3, r3 801724a: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 801724c: 78fb ldrb r3, [r7, #3] 801724e: b2db uxtb r3, r3 8017250: f003 0350 and.w r3, r3, #80 @ 0x50 8017254: b2da uxtb r2, r3 8017256: 4b3d ldr r3, [pc, #244] @ (801734c ) 8017258: 701a strb r2, [r3, #0] * accounting for the number of priority bits supported by the * hardware. A priority of 0 is invalid because setting the BASEPRI * register to 0 unmasks all interrupts, and interrupts with priority 0 * cannot be masked using BASEPRI. * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); 801725a: 4b3c ldr r3, [pc, #240] @ (801734c ) 801725c: 781b ldrb r3, [r3, #0] 801725e: 2b00 cmp r3, #0 8017260: d10b bne.n 801727a __asm volatile 8017262: f04f 0350 mov.w r3, #80 @ 0x50 8017266: f383 8811 msr BASEPRI, r3 801726a: f3bf 8f6f isb sy 801726e: f3bf 8f4f dsb sy 8017272: 613b str r3, [r7, #16] } 8017274: bf00 nop 8017276: bf00 nop 8017278: e7fd b.n 8017276 /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); 801727a: 78fb ldrb r3, [r7, #3] 801727c: b2db uxtb r3, r3 801727e: 43db mvns r3, r3 8017280: f003 0350 and.w r3, r3, #80 @ 0x50 8017284: 2b00 cmp r3, #0 8017286: d013 beq.n 80172b0 __asm volatile 8017288: f04f 0350 mov.w r3, #80 @ 0x50 801728c: f383 8811 msr BASEPRI, r3 8017290: f3bf 8f6f isb sy 8017294: f3bf 8f4f dsb sy 8017298: 60fb str r3, [r7, #12] } 801729a: bf00 nop 801729c: bf00 nop 801729e: e7fd b.n 801729c /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; 80172a0: 687b ldr r3, [r7, #4] 80172a2: 3301 adds r3, #1 80172a4: 607b str r3, [r7, #4] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 80172a6: 78fb ldrb r3, [r7, #3] 80172a8: b2db uxtb r3, r3 80172aa: 005b lsls r3, r3, #1 80172ac: b2db uxtb r3, r3 80172ae: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 80172b0: 78fb ldrb r3, [r7, #3] 80172b2: b2db uxtb r3, r3 80172b4: f003 0380 and.w r3, r3, #128 @ 0x80 80172b8: 2b80 cmp r3, #128 @ 0x80 80172ba: d0f1 beq.n 80172a0 } if( ulImplementedPrioBits == 8 ) 80172bc: 687b ldr r3, [r7, #4] 80172be: 2b08 cmp r3, #8 80172c0: d103 bne.n 80172ca * * The following assert ensures that the sub-priority bit in the * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; 80172c2: 4b23 ldr r3, [pc, #140] @ (8017350 ) 80172c4: 2200 movs r2, #0 80172c6: 601a str r2, [r3, #0] 80172c8: e004 b.n 80172d4 } else { ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; 80172ca: 687b ldr r3, [r7, #4] 80172cc: f1c3 0307 rsb r3, r3, #7 80172d0: 4a1f ldr r2, [pc, #124] @ (8017350 ) 80172d2: 6013 str r3, [r2, #0] } /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 80172d4: 4b1e ldr r3, [pc, #120] @ (8017350 ) 80172d6: 681b ldr r3, [r3, #0] 80172d8: 021b lsls r3, r3, #8 80172da: 4a1d ldr r2, [pc, #116] @ (8017350 ) 80172dc: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 80172de: 4b1c ldr r3, [pc, #112] @ (8017350 ) 80172e0: 681b ldr r3, [r3, #0] 80172e2: f403 63e0 and.w r3, r3, #1792 @ 0x700 80172e6: 4a1a ldr r2, [pc, #104] @ (8017350 ) 80172e8: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original * value. */ *pucFirstUserPriorityRegister = ucOriginalPriority; 80172ea: 7afb ldrb r3, [r7, #11] 80172ec: b2da uxtb r2, r3 80172ee: 69fb ldr r3, [r7, #28] 80172f0: 701a strb r2, [r3, #0] } #endif /* configASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; 80172f2: 4b18 ldr r3, [pc, #96] @ (8017354 ) 80172f4: 681b ldr r3, [r3, #0] 80172f6: 4a17 ldr r2, [pc, #92] @ (8017354 ) 80172f8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80172fc: 6013 str r3, [r2, #0] portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; 80172fe: 4b15 ldr r3, [pc, #84] @ (8017354 ) 8017300: 681b ldr r3, [r3, #0] 8017302: 4a14 ldr r2, [pc, #80] @ (8017354 ) 8017304: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8017308: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ vPortSetupTimerInterrupt(); 801730a: f000 f8df bl 80174cc /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 801730e: 4b12 ldr r3, [pc, #72] @ (8017358 ) 8017310: 2200 movs r2, #0 8017312: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 8017314: f000 f8fe bl 8017514 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8017318: 4b10 ldr r3, [pc, #64] @ (801735c ) 801731a: 681b ldr r3, [r3, #0] 801731c: 4a0f ldr r2, [pc, #60] @ (801735c ) 801731e: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 8017322: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 8017324: f7ff ff48 bl 80171b8 * exit error function to prevent compiler warnings about a static function * not being called in the case that the application writer overrides this * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimisation does not remove the * symbol. */ vTaskSwitchContext(); 8017328: f7fe f9f0 bl 801570c prvTaskExitError(); 801732c: f7ff ff00 bl 8017130 /* Should not get here! */ return 0; 8017330: 2300 movs r3, #0 } 8017332: 4618 mov r0, r3 8017334: 3720 adds r7, #32 8017336: 46bd mov sp, r7 8017338: bd80 pop {r7, pc} 801733a: bf00 nop 801733c: e000ed00 .word 0xe000ed00 8017340: 410fc271 .word 0x410fc271 8017344: 410fc270 .word 0x410fc270 8017348: e000e400 .word 0xe000e400 801734c: 200026f4 .word 0x200026f4 8017350: 200026f8 .word 0x200026f8 8017354: e000ed20 .word 0xe000ed20 8017358: 200000a4 .word 0x200000a4 801735c: e000ef34 .word 0xe000ef34 08017360 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8017360: b480 push {r7} 8017362: b083 sub sp, #12 8017364: af00 add r7, sp, #0 __asm volatile 8017366: f04f 0350 mov.w r3, #80 @ 0x50 801736a: f383 8811 msr BASEPRI, r3 801736e: f3bf 8f6f isb sy 8017372: f3bf 8f4f dsb sy 8017376: 607b str r3, [r7, #4] } 8017378: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 801737a: 4b10 ldr r3, [pc, #64] @ (80173bc ) 801737c: 681b ldr r3, [r3, #0] 801737e: 3301 adds r3, #1 8017380: 4a0e ldr r2, [pc, #56] @ (80173bc ) 8017382: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so * assert() if it is being called from an interrupt context. Only API * functions that end in "FromISR" can be used in an interrupt. Only assert if * the critical nesting count is 1 to protect against recursive calls if the * assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8017384: 4b0d ldr r3, [pc, #52] @ (80173bc ) 8017386: 681b ldr r3, [r3, #0] 8017388: 2b01 cmp r3, #1 801738a: d110 bne.n 80173ae { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 801738c: 4b0c ldr r3, [pc, #48] @ (80173c0 ) 801738e: 681b ldr r3, [r3, #0] 8017390: b2db uxtb r3, r3 8017392: 2b00 cmp r3, #0 8017394: d00b beq.n 80173ae __asm volatile 8017396: f04f 0350 mov.w r3, #80 @ 0x50 801739a: f383 8811 msr BASEPRI, r3 801739e: f3bf 8f6f isb sy 80173a2: f3bf 8f4f dsb sy 80173a6: 603b str r3, [r7, #0] } 80173a8: bf00 nop 80173aa: bf00 nop 80173ac: e7fd b.n 80173aa } } 80173ae: bf00 nop 80173b0: 370c adds r7, #12 80173b2: 46bd mov sp, r7 80173b4: f85d 7b04 ldr.w r7, [sp], #4 80173b8: 4770 bx lr 80173ba: bf00 nop 80173bc: 200000a4 .word 0x200000a4 80173c0: e000ed04 .word 0xe000ed04 080173c4 : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 80173c4: b480 push {r7} 80173c6: b083 sub sp, #12 80173c8: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 80173ca: 4b12 ldr r3, [pc, #72] @ (8017414 ) 80173cc: 681b ldr r3, [r3, #0] 80173ce: 2b00 cmp r3, #0 80173d0: d10b bne.n 80173ea __asm volatile 80173d2: f04f 0350 mov.w r3, #80 @ 0x50 80173d6: f383 8811 msr BASEPRI, r3 80173da: f3bf 8f6f isb sy 80173de: f3bf 8f4f dsb sy 80173e2: 607b str r3, [r7, #4] } 80173e4: bf00 nop 80173e6: bf00 nop 80173e8: e7fd b.n 80173e6 uxCriticalNesting--; 80173ea: 4b0a ldr r3, [pc, #40] @ (8017414 ) 80173ec: 681b ldr r3, [r3, #0] 80173ee: 3b01 subs r3, #1 80173f0: 4a08 ldr r2, [pc, #32] @ (8017414 ) 80173f2: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 80173f4: 4b07 ldr r3, [pc, #28] @ (8017414 ) 80173f6: 681b ldr r3, [r3, #0] 80173f8: 2b00 cmp r3, #0 80173fa: d105 bne.n 8017408 80173fc: 2300 movs r3, #0 80173fe: 603b str r3, [r7, #0] __asm volatile 8017400: 683b ldr r3, [r7, #0] 8017402: f383 8811 msr BASEPRI, r3 } 8017406: bf00 nop { portENABLE_INTERRUPTS(); } } 8017408: bf00 nop 801740a: 370c adds r7, #12 801740c: 46bd mov sp, r7 801740e: f85d 7b04 ldr.w r7, [sp], #4 8017412: 4770 bx lr 8017414: 200000a4 .word 0x200000a4 ... 08017420 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8017420: f3ef 8009 mrs r0, PSP 8017424: f3bf 8f6f isb sy 8017428: 4b15 ldr r3, [pc, #84] @ (8017480 ) 801742a: 681a ldr r2, [r3, #0] 801742c: f01e 0f10 tst.w lr, #16 8017430: bf08 it eq 8017432: ed20 8a10 vstmdbeq r0!, {s16-s31} 8017436: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801743a: 6010 str r0, [r2, #0] 801743c: b409 push {r0, r3} 801743e: f04f 0050 mov.w r0, #80 @ 0x50 8017442: f380 8811 msr BASEPRI, r0 8017446: f3bf 8f4f dsb sy 801744a: f3bf 8f6f isb sy 801744e: f7fe f95d bl 801570c 8017452: f04f 0000 mov.w r0, #0 8017456: f380 8811 msr BASEPRI, r0 801745a: bc09 pop {r0, r3} 801745c: 6819 ldr r1, [r3, #0] 801745e: 6808 ldr r0, [r1, #0] 8017460: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017464: f01e 0f10 tst.w lr, #16 8017468: bf08 it eq 801746a: ecb0 8a10 vldmiaeq r0!, {s16-s31} 801746e: f380 8809 msr PSP, r0 8017472: f3bf 8f6f isb sy 8017476: 4770 bx lr 8017478: f3af 8000 nop.w 801747c: f3af 8000 nop.w 08017480 : 8017480: 200020c8 .word 0x200020c8 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); } 8017484: bf00 nop 8017486: bf00 nop 08017488 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017488: b580 push {r7, lr} 801748a: b082 sub sp, #8 801748c: af00 add r7, sp, #0 __asm volatile 801748e: f04f 0350 mov.w r3, #80 @ 0x50 8017492: f383 8811 msr BASEPRI, r3 8017496: f3bf 8f6f isb sy 801749a: f3bf 8f4f dsb sy 801749e: 607b str r3, [r7, #4] } 80174a0: bf00 nop * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 80174a2: f7fe f81b bl 80154dc 80174a6: 4603 mov r3, r0 80174a8: 2b00 cmp r3, #0 80174aa: d003 beq.n 80174b4 { /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 80174ac: 4b06 ldr r3, [pc, #24] @ (80174c8 ) 80174ae: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80174b2: 601a str r2, [r3, #0] 80174b4: 2300 movs r3, #0 80174b6: 603b str r3, [r7, #0] __asm volatile 80174b8: 683b ldr r3, [r7, #0] 80174ba: f383 8811 msr BASEPRI, r3 } 80174be: bf00 nop } } portENABLE_INTERRUPTS(); } 80174c0: bf00 nop 80174c2: 3708 adds r7, #8 80174c4: 46bd mov sp, r7 80174c6: bd80 pop {r7, pc} 80174c8: e000ed04 .word 0xe000ed04 080174cc : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) { 80174cc: b480 push {r7} 80174ce: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 80174d0: 4b0b ldr r3, [pc, #44] @ (8017500 ) 80174d2: 2200 movs r2, #0 80174d4: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 80174d6: 4b0b ldr r3, [pc, #44] @ (8017504 ) 80174d8: 2200 movs r2, #0 80174da: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 80174dc: 4b0a ldr r3, [pc, #40] @ (8017508 ) 80174de: 681b ldr r3, [r3, #0] 80174e0: 4a0a ldr r2, [pc, #40] @ (801750c ) 80174e2: fba2 2303 umull r2, r3, r2, r3 80174e6: 099b lsrs r3, r3, #6 80174e8: 4a09 ldr r2, [pc, #36] @ (8017510 ) 80174ea: 3b01 subs r3, #1 80174ec: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 80174ee: 4b04 ldr r3, [pc, #16] @ (8017500 ) 80174f0: 2207 movs r2, #7 80174f2: 601a str r2, [r3, #0] } 80174f4: bf00 nop 80174f6: 46bd mov sp, r7 80174f8: f85d 7b04 ldr.w r7, [sp], #4 80174fc: 4770 bx lr 80174fe: bf00 nop 8017500: e000e010 .word 0xe000e010 8017504: e000e018 .word 0xe000e018 8017508: 2000000c .word 0x2000000c 801750c: 10624dd3 .word 0x10624dd3 8017510: e000e014 .word 0xe000e014 08017514 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8017514: f8df 000c ldr.w r0, [pc, #12] @ 8017524 8017518: 6801 ldr r1, [r0, #0] 801751a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 801751e: 6001 str r1, [r0, #0] 8017520: 4770 bx lr 8017522: 0000 .short 0x0000 8017524: e000ed88 .word 0xe000ed88 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 \n" " .ltorg \n" ); } 8017528: bf00 nop 801752a: bf00 nop 0801752c : /*-----------------------------------------------------------*/ #if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 801752c: b480 push {r7} 801752e: b085 sub sp, #20 8017530: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); 8017532: f3ef 8305 mrs r3, IPSR 8017536: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8017538: 68fb ldr r3, [r7, #12] 801753a: 2b0f cmp r3, #15 801753c: d915 bls.n 801756a { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 801753e: 4a18 ldr r2, [pc, #96] @ (80175a0 ) 8017540: 68fb ldr r3, [r7, #12] 8017542: 4413 add r3, r2 8017544: 781b ldrb r3, [r3, #0] 8017546: 72fb strb r3, [r7, #11] * interrupt entry is as fast and simple as possible. * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html * https://www.FreeRTOS.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8017548: 4b16 ldr r3, [pc, #88] @ (80175a4 ) 801754a: 781b ldrb r3, [r3, #0] 801754c: 7afa ldrb r2, [r7, #11] 801754e: 429a cmp r2, r3 8017550: d20b bcs.n 801756a __asm volatile 8017552: f04f 0350 mov.w r3, #80 @ 0x50 8017556: f383 8811 msr BASEPRI, r3 801755a: f3bf 8f6f isb sy 801755e: f3bf 8f4f dsb sy 8017562: 607b str r3, [r7, #4] } 8017564: bf00 nop 8017566: bf00 nop 8017568: e7fd b.n 8017566 * configuration then the correct setting can be achieved on all Cortex-M * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the * scheduler. Note however that some vendor specific peripheral libraries * assume a non-zero priority group setting, in which cases using a value * of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 801756a: 4b0f ldr r3, [pc, #60] @ (80175a8 ) 801756c: 681b ldr r3, [r3, #0] 801756e: f403 62e0 and.w r2, r3, #1792 @ 0x700 8017572: 4b0e ldr r3, [pc, #56] @ (80175ac ) 8017574: 681b ldr r3, [r3, #0] 8017576: 429a cmp r2, r3 8017578: d90b bls.n 8017592 __asm volatile 801757a: f04f 0350 mov.w r3, #80 @ 0x50 801757e: f383 8811 msr BASEPRI, r3 8017582: f3bf 8f6f isb sy 8017586: f3bf 8f4f dsb sy 801758a: 603b str r3, [r7, #0] } 801758c: bf00 nop 801758e: bf00 nop 8017590: e7fd b.n 801758e } 8017592: bf00 nop 8017594: 3714 adds r7, #20 8017596: 46bd mov sp, r7 8017598: f85d 7b04 ldr.w r7, [sp], #4 801759c: 4770 bx lr 801759e: bf00 nop 80175a0: e000e3f0 .word 0xe000e3f0 80175a4: 200026f4 .word 0x200026f4 80175a8: e000ed0c .word 0xe000ed0c 80175ac: 200026f8 .word 0x200026f8 080175b0 : PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0; /*-----------------------------------------------------------*/ void * pvPortMalloc( size_t xWantedSize ) { 80175b0: b580 push {r7, lr} 80175b2: b08a sub sp, #40 @ 0x28 80175b4: af00 add r7, sp, #0 80175b6: 6078 str r0, [r7, #4] BlockLink_t * pxBlock; BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; 80175b8: 2300 movs r3, #0 80175ba: 61fb str r3, [r7, #28] size_t xAdditionalRequiredSize; vTaskSuspendAll(); 80175bc: f7fd fe66 bl 801528c { /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 80175c0: 4b5c ldr r3, [pc, #368] @ (8017734 ) 80175c2: 681b ldr r3, [r3, #0] 80175c4: 2b00 cmp r3, #0 80175c6: d101 bne.n 80175cc { prvHeapInit(); 80175c8: f000 f918 bl 80177fc else { mtCOVERAGE_TEST_MARKER(); } if( xWantedSize > 0 ) 80175cc: 687b ldr r3, [r7, #4] 80175ce: 2b00 cmp r3, #0 80175d0: d022 beq.n 8017618 { /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) 80175d2: 2308 movs r3, #8 80175d4: 43db mvns r3, r3 80175d6: 687a ldr r2, [r7, #4] 80175d8: 429a cmp r2, r3 80175da: d81b bhi.n 8017614 { xWantedSize += xHeapStructSize; 80175dc: 2208 movs r2, #8 80175de: 687b ldr r3, [r7, #4] 80175e0: 4413 add r3, r2 80175e2: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number * of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 80175e4: 687b ldr r3, [r7, #4] 80175e6: f003 0307 and.w r3, r3, #7 80175ea: 2b00 cmp r3, #0 80175ec: d014 beq.n 8017618 { /* Byte alignment required. */ xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); 80175ee: 687b ldr r3, [r7, #4] 80175f0: f003 0307 and.w r3, r3, #7 80175f4: f1c3 0308 rsb r3, r3, #8 80175f8: 61bb str r3, [r7, #24] if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) 80175fa: 69bb ldr r3, [r7, #24] 80175fc: 43db mvns r3, r3 80175fe: 687a ldr r2, [r7, #4] 8017600: 429a cmp r2, r3 8017602: d804 bhi.n 801760e { xWantedSize += xAdditionalRequiredSize; 8017604: 687a ldr r2, [r7, #4] 8017606: 69bb ldr r3, [r7, #24] 8017608: 4413 add r3, r2 801760a: 607b str r3, [r7, #4] 801760c: e004 b.n 8017618 } else { xWantedSize = 0; 801760e: 2300 movs r3, #0 8017610: 607b str r3, [r7, #4] 8017612: e001 b.n 8017618 mtCOVERAGE_TEST_MARKER(); } } else { xWantedSize = 0; 8017614: 2300 movs r3, #0 8017616: 607b str r3, [r7, #4] /* Check the block size we are trying to allocate is not so large that the * top bit is set. The top bit of the block size member of the BlockLink_t * structure is used to determine who owns the block - the application or * the kernel, so it must be free. */ if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) 8017618: 687b ldr r3, [r7, #4] 801761a: 2b00 cmp r3, #0 801761c: db71 blt.n 8017702 { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 801761e: 687b ldr r3, [r7, #4] 8017620: 2b00 cmp r3, #0 8017622: d06e beq.n 8017702 8017624: 4b44 ldr r3, [pc, #272] @ (8017738 ) 8017626: 681b ldr r3, [r3, #0] 8017628: 687a ldr r2, [r7, #4] 801762a: 429a cmp r2, r3 801762c: d869 bhi.n 8017702 { /* Traverse the list from the start (lowest address) block until * one of adequate size is found. */ pxPreviousBlock = &xStart; 801762e: 4b43 ldr r3, [pc, #268] @ (801773c ) 8017630: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 8017632: 4b42 ldr r3, [pc, #264] @ (801773c ) 8017634: 681b ldr r3, [r3, #0] 8017636: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017638: e004 b.n 8017644 { pxPreviousBlock = pxBlock; 801763a: 6a7b ldr r3, [r7, #36] @ 0x24 801763c: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 801763e: 6a7b ldr r3, [r7, #36] @ 0x24 8017640: 681b ldr r3, [r3, #0] 8017642: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017644: 6a7b ldr r3, [r7, #36] @ 0x24 8017646: 685b ldr r3, [r3, #4] 8017648: 687a ldr r2, [r7, #4] 801764a: 429a cmp r2, r3 801764c: d903 bls.n 8017656 801764e: 6a7b ldr r3, [r7, #36] @ 0x24 8017650: 681b ldr r3, [r3, #0] 8017652: 2b00 cmp r3, #0 8017654: d1f1 bne.n 801763a } /* If the end marker was reached then a block of adequate size * was not found. */ if( pxBlock != pxEnd ) 8017656: 4b37 ldr r3, [pc, #220] @ (8017734 ) 8017658: 681b ldr r3, [r3, #0] 801765a: 6a7a ldr r2, [r7, #36] @ 0x24 801765c: 429a cmp r2, r3 801765e: d050 beq.n 8017702 { /* Return the memory space pointed to - jumping over the * BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 8017660: 6a3b ldr r3, [r7, #32] 8017662: 681b ldr r3, [r3, #0] 8017664: 2208 movs r2, #8 8017666: 4413 add r3, r2 8017668: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out * of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 801766a: 6a7b ldr r3, [r7, #36] @ 0x24 801766c: 681a ldr r2, [r3, #0] 801766e: 6a3b ldr r3, [r7, #32] 8017670: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into * two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 8017672: 6a7b ldr r3, [r7, #36] @ 0x24 8017674: 685a ldr r2, [r3, #4] 8017676: 687b ldr r3, [r7, #4] 8017678: 1ad2 subs r2, r2, r3 801767a: 2308 movs r3, #8 801767c: 005b lsls r3, r3, #1 801767e: 429a cmp r2, r3 8017680: d920 bls.n 80176c4 { /* This block is to be split into two. Create a new * block following the number of bytes requested. The void * cast is used to prevent byte alignment warnings from the * compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 8017682: 6a7a ldr r2, [r7, #36] @ 0x24 8017684: 687b ldr r3, [r7, #4] 8017686: 4413 add r3, r2 8017688: 617b str r3, [r7, #20] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 801768a: 697b ldr r3, [r7, #20] 801768c: f003 0307 and.w r3, r3, #7 8017690: 2b00 cmp r3, #0 8017692: d00b beq.n 80176ac __asm volatile 8017694: f04f 0350 mov.w r3, #80 @ 0x50 8017698: f383 8811 msr BASEPRI, r3 801769c: f3bf 8f6f isb sy 80176a0: f3bf 8f4f dsb sy 80176a4: 613b str r3, [r7, #16] } 80176a6: bf00 nop 80176a8: bf00 nop 80176aa: e7fd b.n 80176a8 /* Calculate the sizes of two blocks split from the * single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 80176ac: 6a7b ldr r3, [r7, #36] @ 0x24 80176ae: 685a ldr r2, [r3, #4] 80176b0: 687b ldr r3, [r7, #4] 80176b2: 1ad2 subs r2, r2, r3 80176b4: 697b ldr r3, [r7, #20] 80176b6: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 80176b8: 6a7b ldr r3, [r7, #36] @ 0x24 80176ba: 687a ldr r2, [r7, #4] 80176bc: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 80176be: 6978 ldr r0, [r7, #20] 80176c0: f000 f8f8 bl 80178b4 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 80176c4: 4b1c ldr r3, [pc, #112] @ (8017738 ) 80176c6: 681a ldr r2, [r3, #0] 80176c8: 6a7b ldr r3, [r7, #36] @ 0x24 80176ca: 685b ldr r3, [r3, #4] 80176cc: 1ad3 subs r3, r2, r3 80176ce: 4a1a ldr r2, [pc, #104] @ (8017738 ) 80176d0: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 80176d2: 4b19 ldr r3, [pc, #100] @ (8017738 ) 80176d4: 681a ldr r2, [r3, #0] 80176d6: 4b1a ldr r3, [pc, #104] @ (8017740 ) 80176d8: 681b ldr r3, [r3, #0] 80176da: 429a cmp r2, r3 80176dc: d203 bcs.n 80176e6 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 80176de: 4b16 ldr r3, [pc, #88] @ (8017738 ) 80176e0: 681b ldr r3, [r3, #0] 80176e2: 4a17 ldr r2, [pc, #92] @ (8017740 ) 80176e4: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned * by the application and has no "next" block. */ heapALLOCATE_BLOCK( pxBlock ); 80176e6: 6a7b ldr r3, [r7, #36] @ 0x24 80176e8: 685b ldr r3, [r3, #4] 80176ea: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 80176ee: 6a7b ldr r3, [r7, #36] @ 0x24 80176f0: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 80176f2: 6a7b ldr r3, [r7, #36] @ 0x24 80176f4: 2200 movs r2, #0 80176f6: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 80176f8: 4b12 ldr r3, [pc, #72] @ (8017744 ) 80176fa: 681b ldr r3, [r3, #0] 80176fc: 3301 adds r3, #1 80176fe: 4a11 ldr r2, [pc, #68] @ (8017744 ) 8017700: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 8017702: f7fd fdd1 bl 80152a8 mtCOVERAGE_TEST_MARKER(); } } #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 8017706: 69fb ldr r3, [r7, #28] 8017708: f003 0307 and.w r3, r3, #7 801770c: 2b00 cmp r3, #0 801770e: d00b beq.n 8017728 __asm volatile 8017710: f04f 0350 mov.w r3, #80 @ 0x50 8017714: f383 8811 msr BASEPRI, r3 8017718: f3bf 8f6f isb sy 801771c: f3bf 8f4f dsb sy 8017720: 60fb str r3, [r7, #12] } 8017722: bf00 nop 8017724: bf00 nop 8017726: e7fd b.n 8017724 return pvReturn; 8017728: 69fb ldr r3, [r7, #28] } 801772a: 4618 mov r0, r3 801772c: 3728 adds r7, #40 @ 0x28 801772e: 46bd mov sp, r7 8017730: bd80 pop {r7, pc} 8017732: bf00 nop 8017734: 20012104 .word 0x20012104 8017738: 20012108 .word 0x20012108 801773c: 200120fc .word 0x200120fc 8017740: 2001210c .word 0x2001210c 8017744: 20012110 .word 0x20012110 08017748 : /*-----------------------------------------------------------*/ void vPortFree( void * pv ) { 8017748: b580 push {r7, lr} 801774a: b086 sub sp, #24 801774c: af00 add r7, sp, #0 801774e: 6078 str r0, [r7, #4] uint8_t * puc = ( uint8_t * ) pv; 8017750: 687b ldr r3, [r7, #4] 8017752: 617b str r3, [r7, #20] BlockLink_t * pxLink; if( pv != NULL ) 8017754: 687b ldr r3, [r7, #4] 8017756: 2b00 cmp r3, #0 8017758: d047 beq.n 80177ea { /* The memory being freed will have an BlockLink_t structure immediately * before it. */ puc -= xHeapStructSize; 801775a: 2308 movs r3, #8 801775c: 425b negs r3, r3 801775e: 697a ldr r2, [r7, #20] 8017760: 4413 add r3, r2 8017762: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 8017764: 697b ldr r3, [r7, #20] 8017766: 613b str r3, [r7, #16] configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); 8017768: 693b ldr r3, [r7, #16] 801776a: 685b ldr r3, [r3, #4] 801776c: 2b00 cmp r3, #0 801776e: db0b blt.n 8017788 __asm volatile 8017770: f04f 0350 mov.w r3, #80 @ 0x50 8017774: f383 8811 msr BASEPRI, r3 8017778: f3bf 8f6f isb sy 801777c: f3bf 8f4f dsb sy 8017780: 60fb str r3, [r7, #12] } 8017782: bf00 nop 8017784: bf00 nop 8017786: e7fd b.n 8017784 configASSERT( pxLink->pxNextFreeBlock == NULL ); 8017788: 693b ldr r3, [r7, #16] 801778a: 681b ldr r3, [r3, #0] 801778c: 2b00 cmp r3, #0 801778e: d00b beq.n 80177a8 __asm volatile 8017790: f04f 0350 mov.w r3, #80 @ 0x50 8017794: f383 8811 msr BASEPRI, r3 8017798: f3bf 8f6f isb sy 801779c: f3bf 8f4f dsb sy 80177a0: 60bb str r3, [r7, #8] } 80177a2: bf00 nop 80177a4: bf00 nop 80177a6: e7fd b.n 80177a4 if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) 80177a8: 693b ldr r3, [r7, #16] 80177aa: 685b ldr r3, [r3, #4] 80177ac: 2b00 cmp r3, #0 80177ae: da1c bge.n 80177ea { if( pxLink->pxNextFreeBlock == NULL ) 80177b0: 693b ldr r3, [r7, #16] 80177b2: 681b ldr r3, [r3, #0] 80177b4: 2b00 cmp r3, #0 80177b6: d118 bne.n 80177ea { /* The block is being returned to the heap - it is no longer * allocated. */ heapFREE_BLOCK( pxLink ); 80177b8: 693b ldr r3, [r7, #16] 80177ba: 685b ldr r3, [r3, #4] 80177bc: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 80177c0: 693b ldr r3, [r7, #16] 80177c2: 605a str r2, [r3, #4] { ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); } #endif vTaskSuspendAll(); 80177c4: f7fd fd62 bl 801528c { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 80177c8: 693b ldr r3, [r7, #16] 80177ca: 685a ldr r2, [r3, #4] 80177cc: 4b09 ldr r3, [pc, #36] @ (80177f4 ) 80177ce: 681b ldr r3, [r3, #0] 80177d0: 4413 add r3, r2 80177d2: 4a08 ldr r2, [pc, #32] @ (80177f4 ) 80177d4: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 80177d6: 6938 ldr r0, [r7, #16] 80177d8: f000 f86c bl 80178b4 xNumberOfSuccessfulFrees++; 80177dc: 4b06 ldr r3, [pc, #24] @ (80177f8 ) 80177de: 681b ldr r3, [r3, #0] 80177e0: 3301 adds r3, #1 80177e2: 4a05 ldr r2, [pc, #20] @ (80177f8 ) 80177e4: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 80177e6: f7fd fd5f bl 80152a8 else { mtCOVERAGE_TEST_MARKER(); } } } 80177ea: bf00 nop 80177ec: 3718 adds r7, #24 80177ee: 46bd mov sp, r7 80177f0: bd80 pop {r7, pc} 80177f2: bf00 nop 80177f4: 20012108 .word 0x20012108 80177f8: 20012114 .word 0x20012114 080177fc : return pv; } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ { 80177fc: b480 push {r7} 80177fe: b085 sub sp, #20 8017800: af00 add r7, sp, #0 BlockLink_t * pxFirstFreeBlock; uint8_t * pucAlignedHeap; portPOINTER_SIZE_TYPE uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 8017802: f44f 437a mov.w r3, #64000 @ 0xfa00 8017806: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap; 8017808: 4b25 ldr r3, [pc, #148] @ (80178a0 ) 801780a: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 801780c: 68fb ldr r3, [r7, #12] 801780e: f003 0307 and.w r3, r3, #7 8017812: 2b00 cmp r3, #0 8017814: d00c beq.n 8017830 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 8017816: 68fb ldr r3, [r7, #12] 8017818: 3307 adds r3, #7 801781a: 60fb str r3, [r7, #12] uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); 801781c: 68fb ldr r3, [r7, #12] 801781e: f023 0307 bic.w r3, r3, #7 8017822: 60fb str r3, [r7, #12] xTotalHeapSize -= ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap ); 8017824: 68ba ldr r2, [r7, #8] 8017826: 68fb ldr r3, [r7, #12] 8017828: 1ad3 subs r3, r2, r3 801782a: 4a1d ldr r2, [pc, #116] @ (80178a0 ) 801782c: 4413 add r3, r2 801782e: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 8017830: 68fb ldr r3, [r7, #12] 8017832: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free * blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 8017834: 4a1b ldr r2, [pc, #108] @ (80178a4 ) 8017836: 687b ldr r3, [r7, #4] 8017838: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 801783a: 4b1a ldr r3, [pc, #104] @ (80178a4 ) 801783c: 2200 movs r2, #0 801783e: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted * at the end of the heap space. */ uxAddress = ( portPOINTER_SIZE_TYPE ) ( pucAlignedHeap + xTotalHeapSize ); 8017840: 687a ldr r2, [r7, #4] 8017842: 68bb ldr r3, [r7, #8] 8017844: 4413 add r3, r2 8017846: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 8017848: 2208 movs r2, #8 801784a: 68fb ldr r3, [r7, #12] 801784c: 1a9b subs r3, r3, r2 801784e: 60fb str r3, [r7, #12] uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); 8017850: 68fb ldr r3, [r7, #12] 8017852: f023 0307 bic.w r3, r3, #7 8017856: 60fb str r3, [r7, #12] pxEnd = ( BlockLink_t * ) uxAddress; 8017858: 68fb ldr r3, [r7, #12] 801785a: 4a13 ldr r2, [pc, #76] @ (80178a8 ) 801785c: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 801785e: 4b12 ldr r3, [pc, #72] @ (80178a8 ) 8017860: 681b ldr r3, [r3, #0] 8017862: 2200 movs r2, #0 8017864: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 8017866: 4b10 ldr r3, [pc, #64] @ (80178a8 ) 8017868: 681b ldr r3, [r3, #0] 801786a: 2200 movs r2, #0 801786c: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the * entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap; 801786e: 687b ldr r3, [r7, #4] 8017870: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock ); 8017872: 683b ldr r3, [r7, #0] 8017874: 68fa ldr r2, [r7, #12] 8017876: 1ad2 subs r2, r2, r3 8017878: 683b ldr r3, [r7, #0] 801787a: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 801787c: 4b0a ldr r3, [pc, #40] @ (80178a8 ) 801787e: 681a ldr r2, [r3, #0] 8017880: 683b ldr r3, [r7, #0] 8017882: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8017884: 683b ldr r3, [r7, #0] 8017886: 685b ldr r3, [r3, #4] 8017888: 4a08 ldr r2, [pc, #32] @ (80178ac ) 801788a: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 801788c: 683b ldr r3, [r7, #0] 801788e: 685b ldr r3, [r3, #4] 8017890: 4a07 ldr r2, [pc, #28] @ (80178b0 ) 8017892: 6013 str r3, [r2, #0] } 8017894: bf00 nop 8017896: 3714 adds r7, #20 8017898: 46bd mov sp, r7 801789a: f85d 7b04 ldr.w r7, [sp], #4 801789e: 4770 bx lr 80178a0: 200026fc .word 0x200026fc 80178a4: 200120fc .word 0x200120fc 80178a8: 20012104 .word 0x20012104 80178ac: 2001210c .word 0x2001210c 80178b0: 20012108 .word 0x20012108 080178b4 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ { 80178b4: b480 push {r7} 80178b6: b085 sub sp, #20 80178b8: af00 add r7, sp, #0 80178ba: 6078 str r0, [r7, #4] BlockLink_t * pxIterator; uint8_t * puc; /* Iterate through the list until a block is found that has a higher address * than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 80178bc: 4b28 ldr r3, [pc, #160] @ (8017960 ) 80178be: 60fb str r3, [r7, #12] 80178c0: e002 b.n 80178c8 80178c2: 68fb ldr r3, [r7, #12] 80178c4: 681b ldr r3, [r3, #0] 80178c6: 60fb str r3, [r7, #12] 80178c8: 68fb ldr r3, [r7, #12] 80178ca: 681b ldr r3, [r3, #0] 80178cc: 687a ldr r2, [r7, #4] 80178ce: 429a cmp r2, r3 80178d0: d8f7 bhi.n 80178c2 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after * make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 80178d2: 68fb ldr r3, [r7, #12] 80178d4: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 80178d6: 68fb ldr r3, [r7, #12] 80178d8: 685b ldr r3, [r3, #4] 80178da: 68ba ldr r2, [r7, #8] 80178dc: 4413 add r3, r2 80178de: 687a ldr r2, [r7, #4] 80178e0: 429a cmp r2, r3 80178e2: d108 bne.n 80178f6 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 80178e4: 68fb ldr r3, [r7, #12] 80178e6: 685a ldr r2, [r3, #4] 80178e8: 687b ldr r3, [r7, #4] 80178ea: 685b ldr r3, [r3, #4] 80178ec: 441a add r2, r3 80178ee: 68fb ldr r3, [r7, #12] 80178f0: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 80178f2: 68fb ldr r3, [r7, #12] 80178f4: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before * make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 80178f6: 687b ldr r3, [r7, #4] 80178f8: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 80178fa: 687b ldr r3, [r7, #4] 80178fc: 685b ldr r3, [r3, #4] 80178fe: 68ba ldr r2, [r7, #8] 8017900: 441a add r2, r3 8017902: 68fb ldr r3, [r7, #12] 8017904: 681b ldr r3, [r3, #0] 8017906: 429a cmp r2, r3 8017908: d118 bne.n 801793c { if( pxIterator->pxNextFreeBlock != pxEnd ) 801790a: 68fb ldr r3, [r7, #12] 801790c: 681a ldr r2, [r3, #0] 801790e: 4b15 ldr r3, [pc, #84] @ (8017964 ) 8017910: 681b ldr r3, [r3, #0] 8017912: 429a cmp r2, r3 8017914: d00d beq.n 8017932 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 8017916: 687b ldr r3, [r7, #4] 8017918: 685a ldr r2, [r3, #4] 801791a: 68fb ldr r3, [r7, #12] 801791c: 681b ldr r3, [r3, #0] 801791e: 685b ldr r3, [r3, #4] 8017920: 441a add r2, r3 8017922: 687b ldr r3, [r7, #4] 8017924: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 8017926: 68fb ldr r3, [r7, #12] 8017928: 681b ldr r3, [r3, #0] 801792a: 681a ldr r2, [r3, #0] 801792c: 687b ldr r3, [r7, #4] 801792e: 601a str r2, [r3, #0] 8017930: e008 b.n 8017944 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 8017932: 4b0c ldr r3, [pc, #48] @ (8017964 ) 8017934: 681a ldr r2, [r3, #0] 8017936: 687b ldr r3, [r7, #4] 8017938: 601a str r2, [r3, #0] 801793a: e003 b.n 8017944 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 801793c: 68fb ldr r3, [r7, #12] 801793e: 681a ldr r2, [r3, #0] 8017940: 687b ldr r3, [r7, #4] 8017942: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block * before and the block after, then it's pxNextFreeBlock pointer will have * already been set, and should not be set here as that would make it point * to itself. */ if( pxIterator != pxBlockToInsert ) 8017944: 68fa ldr r2, [r7, #12] 8017946: 687b ldr r3, [r7, #4] 8017948: 429a cmp r2, r3 801794a: d002 beq.n 8017952 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 801794c: 68fb ldr r3, [r7, #12] 801794e: 687a ldr r2, [r7, #4] 8017950: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8017952: bf00 nop 8017954: 3714 adds r7, #20 8017956: 46bd mov sp, r7 8017958: f85d 7b04 ldr.w r7, [sp], #4 801795c: 4770 bx lr 801795e: bf00 nop 8017960: 200120fc .word 0x200120fc 8017964: 20012104 .word 0x20012104 08017968 : { 8017968: b480 push {r7} 801796a: af00 add r7, sp, #0 SET_BIT(PWR->CR4, PWR_CR4_C2BOOT); 801796c: 4b05 ldr r3, [pc, #20] @ (8017984 ) 801796e: 68db ldr r3, [r3, #12] 8017970: 4a04 ldr r2, [pc, #16] @ (8017984 ) 8017972: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8017976: 60d3 str r3, [r2, #12] } 8017978: bf00 nop 801797a: 46bd mov sp, r7 801797c: f85d 7b04 ldr.w r7, [sp], #4 8017980: 4770 bx lr 8017982: bf00 nop 8017984: 58000400 .word 0x58000400 08017988 : { 8017988: b480 push {r7} 801798a: b083 sub sp, #12 801798c: af00 add r7, sp, #0 801798e: 6078 str r0, [r7, #4] SET_BIT(EXTI->C2EMR2, ExtiLine); 8017990: 4b06 ldr r3, [pc, #24] @ (80179ac ) 8017992: f8d3 20d4 ldr.w r2, [r3, #212] @ 0xd4 8017996: 4905 ldr r1, [pc, #20] @ (80179ac ) 8017998: 687b ldr r3, [r7, #4] 801799a: 4313 orrs r3, r2 801799c: f8c1 30d4 str.w r3, [r1, #212] @ 0xd4 } 80179a0: bf00 nop 80179a2: 370c adds r7, #12 80179a4: 46bd mov sp, r7 80179a6: f85d 7b04 ldr.w r7, [sp], #4 80179aa: 4770 bx lr 80179ac: 58000800 .word 0x58000800 080179b0 : * @arg @ref LL_EXTI_LINE_41 * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) { 80179b0: b480 push {r7} 80179b2: b083 sub sp, #12 80179b4: af00 add r7, sp, #0 80179b6: 6078 str r0, [r7, #4] SET_BIT(EXTI->RTSR2, ExtiLine); 80179b8: 4b05 ldr r3, [pc, #20] @ (80179d0 ) 80179ba: 6a1a ldr r2, [r3, #32] 80179bc: 4904 ldr r1, [pc, #16] @ (80179d0 ) 80179be: 687b ldr r3, [r7, #4] 80179c0: 4313 orrs r3, r2 80179c2: 620b str r3, [r1, #32] } 80179c4: bf00 nop 80179c6: 370c adds r7, #12 80179c8: 46bd mov sp, r7 80179ca: f85d 7b04 ldr.w r7, [sp], #4 80179ce: 4770 bx lr 80179d0: 58000800 .word 0x58000800 080179d4 : { 80179d4: b480 push {r7} 80179d6: b085 sub sp, #20 80179d8: af00 add r7, sp, #0 80179da: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB3ENR, Periphs); 80179dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80179e0: 6d1a ldr r2, [r3, #80] @ 0x50 80179e2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80179e6: 687b ldr r3, [r7, #4] 80179e8: 4313 orrs r3, r2 80179ea: 650b str r3, [r1, #80] @ 0x50 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 80179ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80179f0: 6d1a ldr r2, [r3, #80] @ 0x50 80179f2: 687b ldr r3, [r7, #4] 80179f4: 4013 ands r3, r2 80179f6: 60fb str r3, [r7, #12] (void)tmpreg; 80179f8: 68fb ldr r3, [r7, #12] } 80179fa: bf00 nop 80179fc: 3714 adds r7, #20 80179fe: 46bd mov sp, r7 8017a00: f85d 7b04 ldr.w r7, [sp], #4 8017a04: 4770 bx lr 08017a06 : * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH * @retval None */ __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) { 8017a06: b480 push {r7} 8017a08: b085 sub sp, #20 8017a0a: af00 add r7, sp, #0 8017a0c: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->C2AHB3ENR, Periphs); 8017a0e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8017a12: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 8017a16: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8017a1a: 687b ldr r3, [r7, #4] 8017a1c: 4313 orrs r3, r2 8017a1e: f8c1 3150 str.w r3, [r1, #336] @ 0x150 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs); 8017a22: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8017a26: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 8017a2a: 687b ldr r3, [r7, #4] 8017a2c: 4013 ands r3, r2 8017a2e: 60fb str r3, [r7, #12] (void)tmpreg; 8017a30: 68fb ldr r3, [r7, #12] } 8017a32: bf00 nop 8017a34: 3714 adds r7, #20 8017a36: 46bd mov sp, r7 8017a38: f85d 7b04 ldr.w r7, [sp], #4 8017a3c: 4770 bx lr 08017a3e : * @rmtoll C1CR TXFIE LL_C1_IPCC_EnableIT_TXF * @param IPCCx IPCC Instance. * @retval None */ __STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx) { 8017a3e: b480 push {r7} 8017a40: b083 sub sp, #12 8017a42: af00 add r7, sp, #0 8017a44: 6078 str r0, [r7, #4] SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE); 8017a46: 687b ldr r3, [r7, #4] 8017a48: 681b ldr r3, [r3, #0] 8017a4a: f443 3280 orr.w r2, r3, #65536 @ 0x10000 8017a4e: 687b ldr r3, [r7, #4] 8017a50: 601a str r2, [r3, #0] } 8017a52: bf00 nop 8017a54: 370c adds r7, #12 8017a56: 46bd mov sp, r7 8017a58: f85d 7b04 ldr.w r7, [sp], #4 8017a5c: 4770 bx lr 08017a5e : * @rmtoll C1CR RXOIE LL_C1_IPCC_EnableIT_RXO * @param IPCCx IPCC Instance. * @retval None */ __STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx) { 8017a5e: b480 push {r7} 8017a60: b083 sub sp, #12 8017a62: af00 add r7, sp, #0 8017a64: 6078 str r0, [r7, #4] SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE); 8017a66: 687b ldr r3, [r7, #4] 8017a68: 681b ldr r3, [r3, #0] 8017a6a: f043 0201 orr.w r2, r3, #1 8017a6e: 687b ldr r3, [r7, #4] 8017a70: 601a str r2, [r3, #0] } 8017a72: bf00 nop 8017a74: 370c adds r7, #12 8017a76: 46bd mov sp, r7 8017a78: f85d 7b04 ldr.w r7, [sp], #4 8017a7c: 4770 bx lr 08017a7e : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) { 8017a7e: b480 push {r7} 8017a80: b083 sub sp, #12 8017a82: af00 add r7, sp, #0 8017a84: 6078 str r0, [r7, #4] 8017a86: 6039 str r1, [r7, #0] CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); 8017a88: 687b ldr r3, [r7, #4] 8017a8a: 685a ldr r2, [r3, #4] 8017a8c: 683b ldr r3, [r7, #0] 8017a8e: 041b lsls r3, r3, #16 8017a90: 43db mvns r3, r3 8017a92: 401a ands r2, r3 8017a94: 687b ldr r3, [r7, #4] 8017a96: 605a str r2, [r3, #4] } 8017a98: bf00 nop 8017a9a: 370c adds r7, #12 8017a9c: 46bd mov sp, r7 8017a9e: f85d 7b04 ldr.w r7, [sp], #4 8017aa2: 4770 bx lr 08017aa4 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) { 8017aa4: b480 push {r7} 8017aa6: b083 sub sp, #12 8017aa8: af00 add r7, sp, #0 8017aaa: 6078 str r0, [r7, #4] 8017aac: 6039 str r1, [r7, #0] SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); 8017aae: 687b ldr r3, [r7, #4] 8017ab0: 685a ldr r2, [r3, #4] 8017ab2: 683b ldr r3, [r7, #0] 8017ab4: 041b lsls r3, r3, #16 8017ab6: 431a orrs r2, r3 8017ab8: 687b ldr r3, [r7, #4] 8017aba: 605a str r2, [r3, #4] } 8017abc: bf00 nop 8017abe: 370c adds r7, #12 8017ac0: 46bd mov sp, r7 8017ac2: f85d 7b04 ldr.w r7, [sp], #4 8017ac6: 4770 bx lr 08017ac8 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) { 8017ac8: b480 push {r7} 8017aca: b083 sub sp, #12 8017acc: af00 add r7, sp, #0 8017ace: 6078 str r0, [r7, #4] 8017ad0: 6039 str r1, [r7, #0] CLEAR_BIT(IPCCx->C1MR, Channel); 8017ad2: 687b ldr r3, [r7, #4] 8017ad4: 685a ldr r2, [r3, #4] 8017ad6: 683b ldr r3, [r7, #0] 8017ad8: 43db mvns r3, r3 8017ada: 401a ands r2, r3 8017adc: 687b ldr r3, [r7, #4] 8017ade: 605a str r2, [r3, #4] } 8017ae0: bf00 nop 8017ae2: 370c adds r7, #12 8017ae4: 46bd mov sp, r7 8017ae6: f85d 7b04 ldr.w r7, [sp], #4 8017aea: 4770 bx lr 08017aec : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel) { 8017aec: b480 push {r7} 8017aee: b083 sub sp, #12 8017af0: af00 add r7, sp, #0 8017af2: 6078 str r0, [r7, #4] 8017af4: 6039 str r1, [r7, #0] WRITE_REG(IPCCx->C1SCR, Channel); 8017af6: 687b ldr r3, [r7, #4] 8017af8: 683a ldr r2, [r7, #0] 8017afa: 609a str r2, [r3, #8] } 8017afc: bf00 nop 8017afe: 370c adds r7, #12 8017b00: 46bd mov sp, r7 8017b02: f85d 7b04 ldr.w r7, [sp], #4 8017b06: 4770 bx lr 08017b08 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel) { 8017b08: b480 push {r7} 8017b0a: b083 sub sp, #12 8017b0c: af00 add r7, sp, #0 8017b0e: 6078 str r0, [r7, #4] 8017b10: 6039 str r1, [r7, #0] WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos); 8017b12: 683b ldr r3, [r7, #0] 8017b14: 041a lsls r2, r3, #16 8017b16: 687b ldr r3, [r7, #4] 8017b18: 609a str r2, [r3, #8] } 8017b1a: bf00 nop 8017b1c: 370c adds r7, #12 8017b1e: 46bd mov sp, r7 8017b20: f85d 7b04 ldr.w r7, [sp], #4 8017b24: 4770 bx lr 08017b26 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel) { 8017b26: b480 push {r7} 8017b28: b083 sub sp, #12 8017b2a: af00 add r7, sp, #0 8017b2c: 6078 str r0, [r7, #4] 8017b2e: 6039 str r1, [r7, #0] return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL); 8017b30: 687b ldr r3, [r7, #4] 8017b32: 68da ldr r2, [r3, #12] 8017b34: 683b ldr r3, [r7, #0] 8017b36: 4013 ands r3, r2 8017b38: 683a ldr r2, [r7, #0] 8017b3a: 429a cmp r2, r3 8017b3c: d101 bne.n 8017b42 8017b3e: 2301 movs r3, #1 8017b40: e000 b.n 8017b44 8017b42: 2300 movs r3, #0 } 8017b44: 4618 mov r0, r3 8017b46: 370c adds r7, #12 8017b48: 46bd mov sp, r7 8017b4a: f85d 7b04 ldr.w r7, [sp], #4 8017b4e: 4770 bx lr 08017b50 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel) { 8017b50: b480 push {r7} 8017b52: b083 sub sp, #12 8017b54: af00 add r7, sp, #0 8017b56: 6078 str r0, [r7, #4] 8017b58: 6039 str r1, [r7, #0] return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL); 8017b5a: 687b ldr r3, [r7, #4] 8017b5c: 69da ldr r2, [r3, #28] 8017b5e: 683b ldr r3, [r7, #0] 8017b60: 4013 ands r3, r2 8017b62: 683a ldr r2, [r7, #0] 8017b64: 429a cmp r2, r3 8017b66: d101 bne.n 8017b6c 8017b68: 2301 movs r3, #1 8017b6a: e000 b.n 8017b6e 8017b6c: 2300 movs r3, #0 } 8017b6e: 4618 mov r0, r3 8017b70: 370c adds r7, #12 8017b72: 46bd mov sp, r7 8017b74: f85d 7b04 ldr.w r7, [sp], #4 8017b78: 4770 bx lr ... 08017b7c : /****************************************************************************** * INTERRUPT HANDLER ******************************************************************************/ void HW_IPCC_Rx_Handler( void ) { 8017b7c: b580 push {r7, lr} 8017b7e: af00 add r7, sp, #0 if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL )) 8017b80: 2102 movs r1, #2 8017b82: 4818 ldr r0, [pc, #96] @ (8017be4 ) 8017b84: f7ff ffe4 bl 8017b50 8017b88: 4603 mov r3, r0 8017b8a: 2b00 cmp r3, #0 8017b8c: d008 beq.n 8017ba0 8017b8e: 4b15 ldr r3, [pc, #84] @ (8017be4 ) 8017b90: 685b ldr r3, [r3, #4] 8017b92: f003 0302 and.w r3, r3, #2 8017b96: 2b00 cmp r3, #0 8017b98: d102 bne.n 8017ba0 { HW_IPCC_SYS_EvtHandler(); 8017b9a: f000 f901 bl 8017da0 8017b9e: e01e b.n 8017bde else if (HW_IPCC_RX_PENDING( HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL )) { HW_IPCC_ZIGBEE_StackM0RequestHandler(); } #endif /* ZIGBEE_WB */ else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL )) 8017ba0: 2101 movs r1, #1 8017ba2: 4810 ldr r0, [pc, #64] @ (8017be4 ) 8017ba4: f7ff ffd4 bl 8017b50 8017ba8: 4603 mov r3, r0 8017baa: 2b00 cmp r3, #0 8017bac: d008 beq.n 8017bc0 8017bae: 4b0d ldr r3, [pc, #52] @ (8017be4 ) 8017bb0: 685b ldr r3, [r3, #4] 8017bb2: f003 0301 and.w r3, r3, #1 8017bb6: 2b00 cmp r3, #0 8017bb8: d102 bne.n 8017bc0 { HW_IPCC_BLE_EvtHandler(); 8017bba: f000 f875 bl 8017ca8 8017bbe: e00e b.n 8017bde } else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL )) 8017bc0: 2108 movs r1, #8 8017bc2: 4808 ldr r0, [pc, #32] @ (8017be4 ) 8017bc4: f7ff ffc4 bl 8017b50 8017bc8: 4603 mov r3, r0 8017bca: 2b00 cmp r3, #0 8017bcc: d008 beq.n 8017be0 8017bce: 4b05 ldr r3, [pc, #20] @ (8017be4 ) 8017bd0: 685b ldr r3, [r3, #4] 8017bd2: f003 0308 and.w r3, r3, #8 8017bd6: 2b00 cmp r3, #0 8017bd8: d102 bne.n 8017be0 { HW_IPCC_TRACES_EvtHandler(); 8017bda: f000 f959 bl 8017e90 } return; 8017bde: bf00 nop 8017be0: bf00 nop } 8017be2: bd80 pop {r7, pc} 8017be4: 58000c00 .word 0x58000c00 08017be8 : void HW_IPCC_Tx_Handler( void ) { 8017be8: b580 push {r7, lr} 8017bea: af00 add r7, sp, #0 if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL )) 8017bec: 2102 movs r1, #2 8017bee: 4818 ldr r0, [pc, #96] @ (8017c50 ) 8017bf0: f7ff ff99 bl 8017b26 8017bf4: 4603 mov r3, r0 8017bf6: 2b00 cmp r3, #0 8017bf8: d108 bne.n 8017c0c 8017bfa: 4b15 ldr r3, [pc, #84] @ (8017c50 ) 8017bfc: 685b ldr r3, [r3, #4] 8017bfe: f403 3300 and.w r3, r3, #131072 @ 0x20000 8017c02: 2b00 cmp r3, #0 8017c04: d102 bne.n 8017c0c { HW_IPCC_SYS_CmdEvtHandler(); 8017c06: f000 f8af bl 8017d68 8017c0a: e01e b.n 8017c4a if (HW_IPCC_TX_PENDING( HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL )) { HW_IPCC_ZIGBEE_CmdEvtHandler(); } #endif /* ZIGBEE_WB */ else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL )) 8017c0c: 2108 movs r1, #8 8017c0e: 4810 ldr r0, [pc, #64] @ (8017c50 ) 8017c10: f7ff ff89 bl 8017b26 8017c14: 4603 mov r3, r0 8017c16: 2b00 cmp r3, #0 8017c18: d108 bne.n 8017c2c 8017c1a: 4b0d ldr r3, [pc, #52] @ (8017c50 ) 8017c1c: 685b ldr r3, [r3, #4] 8017c1e: f403 2300 and.w r3, r3, #524288 @ 0x80000 8017c22: 2b00 cmp r3, #0 8017c24: d102 bne.n 8017c2c { HW_IPCC_MM_FreeBufHandler(); 8017c26: f000 f8f5 bl 8017e14 8017c2a: e00e b.n 8017c4a } else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL )) 8017c2c: 2120 movs r1, #32 8017c2e: 4808 ldr r0, [pc, #32] @ (8017c50 ) 8017c30: f7ff ff79 bl 8017b26 8017c34: 4603 mov r3, r0 8017c36: 2b00 cmp r3, #0 8017c38: d108 bne.n 8017c4c 8017c3a: 4b05 ldr r3, [pc, #20] @ (8017c50 ) 8017c3c: 685b ldr r3, [r3, #4] 8017c3e: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8017c42: 2b00 cmp r3, #0 8017c44: d102 bne.n 8017c4c { HW_IPCC_BLE_AclDataEvtHandler(); 8017c46: f000 f83b bl 8017cc0 } return; 8017c4a: bf00 nop 8017c4c: bf00 nop } 8017c4e: bd80 pop {r7, pc} 8017c50: 58000c00 .word 0x58000c00 08017c54 : /****************************************************************************** * GENERAL ******************************************************************************/ void HW_IPCC_Enable( void ) { 8017c54: b580 push {r7, lr} 8017c56: af00 add r7, sp, #0 /** * Such as IPCC IP available to the CPU2, it is required to keep the IPCC clock running * when FUS is running on CPU2 and CPU1 enters deep sleep mode */ LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC); 8017c58: f44f 1080 mov.w r0, #1048576 @ 0x100000 8017c5c: f7ff fed3 bl 8017a06 /** * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2 */ LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 ); 8017c60: f44f 7000 mov.w r0, #512 @ 0x200 8017c64: f7ff fea4 bl 80179b0 /* It is required to have at least a system clock cycle before a SEV after LL_EXTI_EnableRisingTrig_32_63() */ LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 ); 8017c68: f44f 7000 mov.w r0, #512 @ 0x200 8017c6c: f7ff fe8c bl 8017988 * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware. * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect. * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect * So, by default, the application shall both set the event flag and set the C2BOOT bit. */ __SEV( ); /* Set the internal event flag and send an event to the CPU2 */ 8017c70: bf40 sev __WFE( ); /* Clear the internal event flag */ 8017c72: bf20 wfe LL_PWR_EnableBootC2( ); 8017c74: f7ff fe78 bl 8017968 return; 8017c78: bf00 nop } 8017c7a: bd80 pop {r7, pc} 08017c7c : void HW_IPCC_Init( void ) { 8017c7c: b580 push {r7, lr} 8017c7e: af00 add r7, sp, #0 LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC ); 8017c80: f44f 1080 mov.w r0, #1048576 @ 0x100000 8017c84: f7ff fea6 bl 80179d4 LL_C1_IPCC_EnableIT_RXO( IPCC ); 8017c88: 4806 ldr r0, [pc, #24] @ (8017ca4 ) 8017c8a: f7ff fee8 bl 8017a5e LL_C1_IPCC_EnableIT_TXF( IPCC ); 8017c8e: 4805 ldr r0, [pc, #20] @ (8017ca4 ) 8017c90: f7ff fed5 bl 8017a3e HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn); 8017c94: 202c movs r0, #44 @ 0x2c 8017c96: f7ee fd35 bl 8006704 HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn); 8017c9a: 202d movs r0, #45 @ 0x2d 8017c9c: f7ee fd32 bl 8006704 return; 8017ca0: bf00 nop } 8017ca2: bd80 pop {r7, pc} 8017ca4: 58000c00 .word 0x58000c00 08017ca8 : return; } static void HW_IPCC_BLE_EvtHandler( void ) { 8017ca8: b580 push {r7, lr} 8017caa: af00 add r7, sp, #0 HW_IPCC_BLE_RxEvtNot(); 8017cac: f7fa fe00 bl 80128b0 LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL ); 8017cb0: 2101 movs r1, #1 8017cb2: 4802 ldr r0, [pc, #8] @ (8017cbc ) 8017cb4: f7ff ff1a bl 8017aec return; 8017cb8: bf00 nop } 8017cba: bd80 pop {r7, pc} 8017cbc: 58000c00 .word 0x58000c00 08017cc0 : return; } static void HW_IPCC_BLE_AclDataEvtHandler( void ) { 8017cc0: b580 push {r7, lr} 8017cc2: b084 sub sp, #16 8017cc4: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8017cc6: f3ef 8310 mrs r3, PRIMASK 8017cca: 607b str r3, [r7, #4] return(result); 8017ccc: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 8017cce: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 8017cd0: b672 cpsid i } 8017cd2: bf00 nop LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL ); 8017cd4: 2120 movs r1, #32 8017cd6: 4807 ldr r0, [pc, #28] @ (8017cf4 ) 8017cd8: f7ff fee4 bl 8017aa4 8017cdc: 68fb ldr r3, [r7, #12] 8017cde: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8017ce0: 68bb ldr r3, [r7, #8] 8017ce2: f383 8810 msr PRIMASK, r3 } 8017ce6: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); HW_IPCC_BLE_AclDataAckNot(); 8017ce8: f7fa fe12 bl 8012910 return; 8017cec: bf00 nop } 8017cee: 3710 adds r7, #16 8017cf0: 46bd mov sp, r7 8017cf2: bd80 pop {r7, pc} 8017cf4: 58000c00 .word 0x58000c00 08017cf8 : /****************************************************************************** * SYSTEM ******************************************************************************/ void HW_IPCC_SYS_Init( void ) { 8017cf8: b580 push {r7, lr} 8017cfa: b084 sub sp, #16 8017cfc: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8017cfe: f3ef 8310 mrs r3, PRIMASK 8017d02: 607b str r3, [r7, #4] return(result); 8017d04: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 8017d06: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 8017d08: b672 cpsid i } 8017d0a: bf00 nop LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL ); 8017d0c: 2102 movs r1, #2 8017d0e: 4806 ldr r0, [pc, #24] @ (8017d28 ) 8017d10: f7ff feda bl 8017ac8 8017d14: 68fb ldr r3, [r7, #12] 8017d16: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8017d18: 68bb ldr r3, [r7, #8] 8017d1a: f383 8810 msr PRIMASK, r3 } 8017d1e: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); return; 8017d20: bf00 nop } 8017d22: 3710 adds r7, #16 8017d24: 46bd mov sp, r7 8017d26: bd80 pop {r7, pc} 8017d28: 58000c00 .word 0x58000c00 08017d2c : void HW_IPCC_SYS_SendCmd( void ) { 8017d2c: b580 push {r7, lr} 8017d2e: b084 sub sp, #16 8017d30: af00 add r7, sp, #0 LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); 8017d32: 2102 movs r1, #2 8017d34: 480b ldr r0, [pc, #44] @ (8017d64 ) 8017d36: f7ff fee7 bl 8017b08 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8017d3a: f3ef 8310 mrs r3, PRIMASK 8017d3e: 607b str r3, [r7, #4] return(result); 8017d40: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 8017d42: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 8017d44: b672 cpsid i } 8017d46: bf00 nop LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); 8017d48: 2102 movs r1, #2 8017d4a: 4806 ldr r0, [pc, #24] @ (8017d64 ) 8017d4c: f7ff fe97 bl 8017a7e 8017d50: 68fb ldr r3, [r7, #12] 8017d52: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8017d54: 68bb ldr r3, [r7, #8] 8017d56: f383 8810 msr PRIMASK, r3 } 8017d5a: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); return; 8017d5c: bf00 nop } 8017d5e: 3710 adds r7, #16 8017d60: 46bd mov sp, r7 8017d62: bd80 pop {r7, pc} 8017d64: 58000c00 .word 0x58000c00 08017d68 : static void HW_IPCC_SYS_CmdEvtHandler( void ) { 8017d68: b580 push {r7, lr} 8017d6a: b084 sub sp, #16 8017d6c: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8017d6e: f3ef 8310 mrs r3, PRIMASK 8017d72: 607b str r3, [r7, #4] return(result); 8017d74: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 8017d76: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 8017d78: b672 cpsid i } 8017d7a: bf00 nop LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); 8017d7c: 2102 movs r1, #2 8017d7e: 4807 ldr r0, [pc, #28] @ (8017d9c ) 8017d80: f7ff fe90 bl 8017aa4 8017d84: 68fb ldr r3, [r7, #12] 8017d86: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8017d88: 68bb ldr r3, [r7, #8] 8017d8a: f383 8810 msr PRIMASK, r3 } 8017d8e: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); HW_IPCC_SYS_CmdEvtNot(); 8017d90: f7fa fe12 bl 80129b8 return; 8017d94: bf00 nop } 8017d96: 3710 adds r7, #16 8017d98: 46bd mov sp, r7 8017d9a: bd80 pop {r7, pc} 8017d9c: 58000c00 .word 0x58000c00 08017da0 : static void HW_IPCC_SYS_EvtHandler( void ) { 8017da0: b580 push {r7, lr} 8017da2: af00 add r7, sp, #0 HW_IPCC_SYS_EvtNot(); 8017da4: f7fa fe1e bl 80129e4 LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL ); 8017da8: 2102 movs r1, #2 8017daa: 4802 ldr r0, [pc, #8] @ (8017db4 ) 8017dac: f7ff fe9e bl 8017aec return; 8017db0: bf00 nop } 8017db2: bd80 pop {r7, pc} 8017db4: 58000c00 .word 0x58000c00 08017db8 : /****************************************************************************** * MEMORY MANAGER ******************************************************************************/ void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) ) { 8017db8: b580 push {r7, lr} 8017dba: b086 sub sp, #24 8017dbc: af00 add r7, sp, #0 8017dbe: 6078 str r0, [r7, #4] if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) ) 8017dc0: 2108 movs r1, #8 8017dc2: 4812 ldr r0, [pc, #72] @ (8017e0c ) 8017dc4: f7ff feaf bl 8017b26 8017dc8: 4603 mov r3, r0 8017dca: 2b00 cmp r3, #0 8017dcc: d013 beq.n 8017df6 { FreeBufCb = cb; 8017dce: 4a10 ldr r2, [pc, #64] @ (8017e10 ) 8017dd0: 687b ldr r3, [r7, #4] 8017dd2: 6013 str r3, [r2, #0] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8017dd4: f3ef 8310 mrs r3, PRIMASK 8017dd8: 60fb str r3, [r7, #12] return(result); 8017dda: 68fb ldr r3, [r7, #12] UTILS_ENTER_CRITICAL_SECTION(); 8017ddc: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 8017dde: b672 cpsid i } 8017de0: bf00 nop LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); 8017de2: 2108 movs r1, #8 8017de4: 4809 ldr r0, [pc, #36] @ (8017e0c ) 8017de6: f7ff fe4a bl 8017a7e 8017dea: 697b ldr r3, [r7, #20] 8017dec: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8017dee: 693b ldr r3, [r7, #16] 8017df0: f383 8810 msr PRIMASK, r3 } 8017df4: e005 b.n 8017e02 UTILS_EXIT_CRITICAL_SECTION(); } else { cb(); 8017df6: 687b ldr r3, [r7, #4] 8017df8: 4798 blx r3 LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); 8017dfa: 2108 movs r1, #8 8017dfc: 4803 ldr r0, [pc, #12] @ (8017e0c ) 8017dfe: f7ff fe83 bl 8017b08 } return; 8017e02: bf00 nop } 8017e04: 3718 adds r7, #24 8017e06: 46bd mov sp, r7 8017e08: bd80 pop {r7, pc} 8017e0a: bf00 nop 8017e0c: 58000c00 .word 0x58000c00 8017e10: 20012118 .word 0x20012118 08017e14 : static void HW_IPCC_MM_FreeBufHandler( void ) { 8017e14: b580 push {r7, lr} 8017e16: b084 sub sp, #16 8017e18: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8017e1a: f3ef 8310 mrs r3, PRIMASK 8017e1e: 607b str r3, [r7, #4] return(result); 8017e20: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 8017e22: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 8017e24: b672 cpsid i } 8017e26: bf00 nop LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); 8017e28: 2108 movs r1, #8 8017e2a: 480a ldr r0, [pc, #40] @ (8017e54 ) 8017e2c: f7ff fe3a bl 8017aa4 8017e30: 68fb ldr r3, [r7, #12] 8017e32: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8017e34: 68bb ldr r3, [r7, #8] 8017e36: f383 8810 msr PRIMASK, r3 } 8017e3a: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); FreeBufCb(); 8017e3c: 4b06 ldr r3, [pc, #24] @ (8017e58 ) 8017e3e: 681b ldr r3, [r3, #0] 8017e40: 4798 blx r3 LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); 8017e42: 2108 movs r1, #8 8017e44: 4803 ldr r0, [pc, #12] @ (8017e54 ) 8017e46: f7ff fe5f bl 8017b08 return; 8017e4a: bf00 nop } 8017e4c: 3710 adds r7, #16 8017e4e: 46bd mov sp, r7 8017e50: bd80 pop {r7, pc} 8017e52: bf00 nop 8017e54: 58000c00 .word 0x58000c00 8017e58: 20012118 .word 0x20012118 08017e5c : /****************************************************************************** * TRACES ******************************************************************************/ void HW_IPCC_TRACES_Init( void ) { 8017e5c: b580 push {r7, lr} 8017e5e: b084 sub sp, #16 8017e60: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8017e62: f3ef 8310 mrs r3, PRIMASK 8017e66: 607b str r3, [r7, #4] return(result); 8017e68: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 8017e6a: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 8017e6c: b672 cpsid i } 8017e6e: bf00 nop LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL ); 8017e70: 2108 movs r1, #8 8017e72: 4806 ldr r0, [pc, #24] @ (8017e8c ) 8017e74: f7ff fe28 bl 8017ac8 8017e78: 68fb ldr r3, [r7, #12] 8017e7a: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8017e7c: 68bb ldr r3, [r7, #8] 8017e7e: f383 8810 msr PRIMASK, r3 } 8017e82: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); return; 8017e84: bf00 nop } 8017e86: 3710 adds r7, #16 8017e88: 46bd mov sp, r7 8017e8a: bd80 pop {r7, pc} 8017e8c: 58000c00 .word 0x58000c00 08017e90 : static void HW_IPCC_TRACES_EvtHandler( void ) { 8017e90: b580 push {r7, lr} 8017e92: af00 add r7, sp, #0 HW_IPCC_TRACES_EvtNot(); 8017e94: f7fa fe4e bl 8012b34 LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL ); 8017e98: 2108 movs r1, #8 8017e9a: 4802 ldr r0, [pc, #8] @ (8017ea4 ) 8017e9c: f7ff fe26 bl 8017aec return; 8017ea0: bf00 nop } 8017ea2: bd80 pop {r7, pc} 8017ea4: 58000c00 .word 0x58000c00 08017ea8 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_Device_Init(void) { 8017ea8: b580 push {r7, lr} 8017eaa: af00 add r7, sp, #0 /* USER CODE BEGIN USB_Device_Init_PreTreatment */ /* USER CODE END USB_Device_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &CDC_Desc, DEVICE_FS) != USBD_OK) { 8017eac: 2200 movs r2, #0 8017eae: 4912 ldr r1, [pc, #72] @ (8017ef8 ) 8017eb0: 4812 ldr r0, [pc, #72] @ (8017efc ) 8017eb2: f7f8 fff3 bl 8010e9c 8017eb6: 4603 mov r3, r0 8017eb8: 2b00 cmp r3, #0 8017eba: d001 beq.n 8017ec0 Error_Handler(); 8017ebc: f7ed f9b0 bl 8005220 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) { 8017ec0: 490f ldr r1, [pc, #60] @ (8017f00 ) 8017ec2: 480e ldr r0, [pc, #56] @ (8017efc ) 8017ec4: f7f9 f81a bl 8010efc 8017ec8: 4603 mov r3, r0 8017eca: 2b00 cmp r3, #0 8017ecc: d001 beq.n 8017ed2 Error_Handler(); 8017ece: f7ed f9a7 bl 8005220 } if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) { 8017ed2: 490c ldr r1, [pc, #48] @ (8017f04 ) 8017ed4: 4809 ldr r0, [pc, #36] @ (8017efc ) 8017ed6: f7f8 ff11 bl 8010cfc 8017eda: 4603 mov r3, r0 8017edc: 2b00 cmp r3, #0 8017ede: d001 beq.n 8017ee4 Error_Handler(); 8017ee0: f7ed f99e bl 8005220 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) { 8017ee4: 4805 ldr r0, [pc, #20] @ (8017efc ) 8017ee6: f7f9 f83f bl 8010f68 8017eea: 4603 mov r3, r0 8017eec: 2b00 cmp r3, #0 8017eee: d001 beq.n 8017ef4 Error_Handler(); 8017ef0: f7ed f996 bl 8005220 } /* USER CODE BEGIN USB_Device_Init_PostTreatment */ /* USER CODE END USB_Device_Init_PostTreatment */ } 8017ef4: bf00 nop 8017ef6: bd80 pop {r7, pc} 8017ef8: 200000bc .word 0x200000bc 8017efc: 2001211c .word 0x2001211c 8017f00: 20000024 .word 0x20000024 8017f04: 200000a8 .word 0x200000a8 08017f08 : /** * @brief Initializes the CDC media low layer over the FS USB IP * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Init_FS(void) { 8017f08: b580 push {r7, lr} 8017f0a: af00 add r7, sp, #0 /* USER CODE BEGIN 3 */ /* Set Application Buffers */ USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); 8017f0c: 2200 movs r2, #0 8017f0e: 4905 ldr r1, [pc, #20] @ (8017f24 ) 8017f10: 4805 ldr r0, [pc, #20] @ (8017f28 ) 8017f12: f7f8 ff0d bl 8010d30 USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); 8017f16: 4905 ldr r1, [pc, #20] @ (8017f2c ) 8017f18: 4803 ldr r0, [pc, #12] @ (8017f28 ) 8017f1a: f7f8 ff2b bl 8010d74 return (USBD_OK); 8017f1e: 2300 movs r3, #0 /* USER CODE END 3 */ } 8017f20: 4618 mov r0, r3 8017f22: bd80 pop {r7, pc} 8017f24: 20012bf8 .word 0x20012bf8 8017f28: 2001211c .word 0x2001211c 8017f2c: 200123f8 .word 0x200123f8 08017f30 : /** * @brief DeInitializes the CDC media low layer * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_DeInit_FS(void) { 8017f30: b480 push {r7} 8017f32: af00 add r7, sp, #0 /* USER CODE BEGIN 4 */ return (USBD_OK); 8017f34: 2300 movs r3, #0 /* USER CODE END 4 */ } 8017f36: 4618 mov r0, r3 8017f38: 46bd mov sp, r7 8017f3a: f85d 7b04 ldr.w r7, [sp], #4 8017f3e: 4770 bx lr 08017f40 : * @param pbuf: Buffer containing command data (request parameters) * @param length: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { 8017f40: b480 push {r7} 8017f42: b083 sub sp, #12 8017f44: af00 add r7, sp, #0 8017f46: 4603 mov r3, r0 8017f48: 6039 str r1, [r7, #0] 8017f4a: 71fb strb r3, [r7, #7] 8017f4c: 4613 mov r3, r2 8017f4e: 80bb strh r3, [r7, #4] /* USER CODE BEGIN 5 */ switch(cmd) 8017f50: 79fb ldrb r3, [r7, #7] 8017f52: 2b23 cmp r3, #35 @ 0x23 8017f54: d84a bhi.n 8017fec 8017f56: a201 add r2, pc, #4 @ (adr r2, 8017f5c ) 8017f58: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8017f5c: 08017fed .word 0x08017fed 8017f60: 08017fed .word 0x08017fed 8017f64: 08017fed .word 0x08017fed 8017f68: 08017fed .word 0x08017fed 8017f6c: 08017fed .word 0x08017fed 8017f70: 08017fed .word 0x08017fed 8017f74: 08017fed .word 0x08017fed 8017f78: 08017fed .word 0x08017fed 8017f7c: 08017fed .word 0x08017fed 8017f80: 08017fed .word 0x08017fed 8017f84: 08017fed .word 0x08017fed 8017f88: 08017fed .word 0x08017fed 8017f8c: 08017fed .word 0x08017fed 8017f90: 08017fed .word 0x08017fed 8017f94: 08017fed .word 0x08017fed 8017f98: 08017fed .word 0x08017fed 8017f9c: 08017fed .word 0x08017fed 8017fa0: 08017fed .word 0x08017fed 8017fa4: 08017fed .word 0x08017fed 8017fa8: 08017fed .word 0x08017fed 8017fac: 08017fed .word 0x08017fed 8017fb0: 08017fed .word 0x08017fed 8017fb4: 08017fed .word 0x08017fed 8017fb8: 08017fed .word 0x08017fed 8017fbc: 08017fed .word 0x08017fed 8017fc0: 08017fed .word 0x08017fed 8017fc4: 08017fed .word 0x08017fed 8017fc8: 08017fed .word 0x08017fed 8017fcc: 08017fed .word 0x08017fed 8017fd0: 08017fed .word 0x08017fed 8017fd4: 08017fed .word 0x08017fed 8017fd8: 08017fed .word 0x08017fed 8017fdc: 08017fed .word 0x08017fed 8017fe0: 08017fed .word 0x08017fed 8017fe4: 08017fed .word 0x08017fed 8017fe8: 08017fed .word 0x08017fed case CDC_SEND_BREAK: break; default: break; 8017fec: bf00 nop } return (USBD_OK); 8017fee: 2300 movs r3, #0 /* USER CODE END 5 */ } 8017ff0: 4618 mov r0, r3 8017ff2: 370c adds r7, #12 8017ff4: 46bd mov sp, r7 8017ff6: f85d 7b04 ldr.w r7, [sp], #4 8017ffa: 4770 bx lr 08017ffc : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { 8017ffc: b580 push {r7, lr} 8017ffe: b082 sub sp, #8 8018000: af00 add r7, sp, #0 8018002: 6078 str r0, [r7, #4] 8018004: 6039 str r1, [r7, #0] /* USER CODE BEGIN 6 */ USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); 8018006: 6879 ldr r1, [r7, #4] 8018008: 4805 ldr r0, [pc, #20] @ (8018020 ) 801800a: f7f8 feb3 bl 8010d74 USBD_CDC_ReceivePacket(&hUsbDeviceFS); 801800e: 4804 ldr r0, [pc, #16] @ (8018020 ) 8018010: f7f8 ff0e bl 8010e30 return (USBD_OK); 8018014: 2300 movs r3, #0 /* USER CODE END 6 */ } 8018016: 4618 mov r0, r3 8018018: 3708 adds r7, #8 801801a: 46bd mov sp, r7 801801c: bd80 pop {r7, pc} 801801e: bf00 nop 8018020: 2001211c .word 0x2001211c 08018024 : * @param Buf: Buffer of data to be sent * @param Len: Number of data to be sent (in bytes) * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) { 8018024: b580 push {r7, lr} 8018026: b084 sub sp, #16 8018028: af00 add r7, sp, #0 801802a: 6078 str r0, [r7, #4] 801802c: 460b mov r3, r1 801802e: 807b strh r3, [r7, #2] uint8_t result = USBD_OK; 8018030: 2300 movs r3, #0 8018032: 73fb strb r3, [r7, #15] /* USER CODE BEGIN 7 */ USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; 8018034: 4b0d ldr r3, [pc, #52] @ (801806c ) 8018036: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 801803a: 60bb str r3, [r7, #8] if (hcdc->TxState != 0){ 801803c: 68bb ldr r3, [r7, #8] 801803e: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214 8018042: 2b00 cmp r3, #0 8018044: d001 beq.n 801804a return USBD_BUSY; 8018046: 2301 movs r3, #1 8018048: e00b b.n 8018062 } USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); 801804a: 887b ldrh r3, [r7, #2] 801804c: 461a mov r2, r3 801804e: 6879 ldr r1, [r7, #4] 8018050: 4806 ldr r0, [pc, #24] @ (801806c ) 8018052: f7f8 fe6d bl 8010d30 result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); 8018056: 4805 ldr r0, [pc, #20] @ (801806c ) 8018058: f7f8 feaa bl 8010db0 801805c: 4603 mov r3, r0 801805e: 73fb strb r3, [r7, #15] /* USER CODE END 7 */ return result; 8018060: 7bfb ldrb r3, [r7, #15] } 8018062: 4618 mov r0, r3 8018064: 3710 adds r7, #16 8018066: 46bd mov sp, r7 8018068: bd80 pop {r7, pc} 801806a: bf00 nop 801806c: 2001211c .word 0x2001211c 08018070 : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum) { 8018070: b480 push {r7} 8018072: b087 sub sp, #28 8018074: af00 add r7, sp, #0 8018076: 60f8 str r0, [r7, #12] 8018078: 60b9 str r1, [r7, #8] 801807a: 4613 mov r3, r2 801807c: 71fb strb r3, [r7, #7] uint8_t result = USBD_OK; 801807e: 2300 movs r3, #0 8018080: 75fb strb r3, [r7, #23] /* USER CODE BEGIN 13 */ UNUSED(Buf); UNUSED(Len); UNUSED(epnum); /* USER CODE END 13 */ return result; 8018082: f997 3017 ldrsb.w r3, [r7, #23] } 8018086: 4618 mov r0, r3 8018088: 371c adds r7, #28 801808a: 46bd mov sp, r7 801808c: f85d 7b04 ldr.w r7, [sp], #4 8018090: 4770 bx lr ... 08018094 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018094: b480 push {r7} 8018096: b083 sub sp, #12 8018098: af00 add r7, sp, #0 801809a: 4603 mov r3, r0 801809c: 6039 str r1, [r7, #0] 801809e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_CDC_DeviceDesc); 80180a0: 683b ldr r3, [r7, #0] 80180a2: 2212 movs r2, #18 80180a4: 801a strh r2, [r3, #0] return USBD_CDC_DeviceDesc; 80180a6: 4b03 ldr r3, [pc, #12] @ (80180b4 ) } 80180a8: 4618 mov r0, r3 80180aa: 370c adds r7, #12 80180ac: 46bd mov sp, r7 80180ae: f85d 7b04 ldr.w r7, [sp], #4 80180b2: 4770 bx lr 80180b4: 200000dc .word 0x200000dc 080180b8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80180b8: b480 push {r7} 80180ba: b083 sub sp, #12 80180bc: af00 add r7, sp, #0 80180be: 4603 mov r3, r0 80180c0: 6039 str r1, [r7, #0] 80180c2: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 80180c4: 683b ldr r3, [r7, #0] 80180c6: 2204 movs r2, #4 80180c8: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 80180ca: 4b03 ldr r3, [pc, #12] @ (80180d8 ) } 80180cc: 4618 mov r0, r3 80180ce: 370c adds r7, #12 80180d0: 46bd mov sp, r7 80180d2: f85d 7b04 ldr.w r7, [sp], #4 80180d6: 4770 bx lr 80180d8: 200000f0 .word 0x200000f0 080180dc : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80180dc: b580 push {r7, lr} 80180de: b082 sub sp, #8 80180e0: af00 add r7, sp, #0 80180e2: 4603 mov r3, r0 80180e4: 6039 str r1, [r7, #0] 80180e6: 71fb strb r3, [r7, #7] if(speed == 0) 80180e8: 79fb ldrb r3, [r7, #7] 80180ea: 2b00 cmp r3, #0 80180ec: d105 bne.n 80180fa { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length); 80180ee: 683a ldr r2, [r7, #0] 80180f0: 4907 ldr r1, [pc, #28] @ (8018110 ) 80180f2: 4808 ldr r0, [pc, #32] @ (8018114 ) 80180f4: f7fa f896 bl 8012224 80180f8: e004 b.n 8018104 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length); 80180fa: 683a ldr r2, [r7, #0] 80180fc: 4904 ldr r1, [pc, #16] @ (8018110 ) 80180fe: 4805 ldr r0, [pc, #20] @ (8018114 ) 8018100: f7fa f890 bl 8012224 } return USBD_StrDesc; 8018104: 4b02 ldr r3, [pc, #8] @ (8018110 ) } 8018106: 4618 mov r0, r3 8018108: 3708 adds r7, #8 801810a: 46bd mov sp, r7 801810c: bd80 pop {r7, pc} 801810e: bf00 nop 8018110: 200133f8 .word 0x200133f8 8018114: 0801d9d4 .word 0x0801d9d4 08018118 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018118: b580 push {r7, lr} 801811a: b082 sub sp, #8 801811c: af00 add r7, sp, #0 801811e: 4603 mov r3, r0 8018120: 6039 str r1, [r7, #0] 8018122: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 8018124: 683a ldr r2, [r7, #0] 8018126: 4904 ldr r1, [pc, #16] @ (8018138 ) 8018128: 4804 ldr r0, [pc, #16] @ (801813c ) 801812a: f7fa f87b bl 8012224 return USBD_StrDesc; 801812e: 4b02 ldr r3, [pc, #8] @ (8018138 ) } 8018130: 4618 mov r0, r3 8018132: 3708 adds r7, #8 8018134: 46bd mov sp, r7 8018136: bd80 pop {r7, pc} 8018138: 200133f8 .word 0x200133f8 801813c: 0801d9ec .word 0x0801d9ec 08018140 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018140: b580 push {r7, lr} 8018142: b082 sub sp, #8 8018144: af00 add r7, sp, #0 8018146: 4603 mov r3, r0 8018148: 6039 str r1, [r7, #0] 801814a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 801814c: 683b ldr r3, [r7, #0] 801814e: 221a movs r2, #26 8018150: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 8018152: f000 f843 bl 80181dc /* USER CODE BEGIN USBD_CDC_SerialStrDescriptor */ /* USER CODE END USBD_CDC_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 8018156: 4b02 ldr r3, [pc, #8] @ (8018160 ) } 8018158: 4618 mov r0, r3 801815a: 3708 adds r7, #8 801815c: 46bd mov sp, r7 801815e: bd80 pop {r7, pc} 8018160: 200000f4 .word 0x200000f4 08018164 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018164: b580 push {r7, lr} 8018166: b082 sub sp, #8 8018168: af00 add r7, sp, #0 801816a: 4603 mov r3, r0 801816c: 6039 str r1, [r7, #0] 801816e: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 8018170: 79fb ldrb r3, [r7, #7] 8018172: 2b00 cmp r3, #0 8018174: d105 bne.n 8018182 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length); 8018176: 683a ldr r2, [r7, #0] 8018178: 4907 ldr r1, [pc, #28] @ (8018198 ) 801817a: 4808 ldr r0, [pc, #32] @ (801819c ) 801817c: f7fa f852 bl 8012224 8018180: e004 b.n 801818c } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length); 8018182: 683a ldr r2, [r7, #0] 8018184: 4904 ldr r1, [pc, #16] @ (8018198 ) 8018186: 4805 ldr r0, [pc, #20] @ (801819c ) 8018188: f7fa f84c bl 8012224 } return USBD_StrDesc; 801818c: 4b02 ldr r3, [pc, #8] @ (8018198 ) } 801818e: 4618 mov r0, r3 8018190: 3708 adds r7, #8 8018192: 46bd mov sp, r7 8018194: bd80 pop {r7, pc} 8018196: bf00 nop 8018198: 200133f8 .word 0x200133f8 801819c: 0801da00 .word 0x0801da00 080181a0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80181a0: b580 push {r7, lr} 80181a2: b082 sub sp, #8 80181a4: af00 add r7, sp, #0 80181a6: 4603 mov r3, r0 80181a8: 6039 str r1, [r7, #0] 80181aa: 71fb strb r3, [r7, #7] if(speed == 0) 80181ac: 79fb ldrb r3, [r7, #7] 80181ae: 2b00 cmp r3, #0 80181b0: d105 bne.n 80181be { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length); 80181b2: 683a ldr r2, [r7, #0] 80181b4: 4907 ldr r1, [pc, #28] @ (80181d4 ) 80181b6: 4808 ldr r0, [pc, #32] @ (80181d8 ) 80181b8: f7fa f834 bl 8012224 80181bc: e004 b.n 80181c8 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length); 80181be: 683a ldr r2, [r7, #0] 80181c0: 4904 ldr r1, [pc, #16] @ (80181d4 ) 80181c2: 4805 ldr r0, [pc, #20] @ (80181d8 ) 80181c4: f7fa f82e bl 8012224 } return USBD_StrDesc; 80181c8: 4b02 ldr r3, [pc, #8] @ (80181d4 ) } 80181ca: 4618 mov r0, r3 80181cc: 3708 adds r7, #8 80181ce: 46bd mov sp, r7 80181d0: bd80 pop {r7, pc} 80181d2: bf00 nop 80181d4: 200133f8 .word 0x200133f8 80181d8: 0801da0c .word 0x0801da0c 080181dc : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 80181dc: b580 push {r7, lr} 80181de: b084 sub sp, #16 80181e0: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 80181e2: 4b0f ldr r3, [pc, #60] @ (8018220 ) 80181e4: 681b ldr r3, [r3, #0] 80181e6: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 80181e8: 4b0e ldr r3, [pc, #56] @ (8018224 ) 80181ea: 681b ldr r3, [r3, #0] 80181ec: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 80181ee: 4b0e ldr r3, [pc, #56] @ (8018228 ) 80181f0: 681b ldr r3, [r3, #0] 80181f2: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 80181f4: 68fa ldr r2, [r7, #12] 80181f6: 687b ldr r3, [r7, #4] 80181f8: 4413 add r3, r2 80181fa: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 80181fc: 68fb ldr r3, [r7, #12] 80181fe: 2b00 cmp r3, #0 8018200: d009 beq.n 8018216 { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 8018202: 2208 movs r2, #8 8018204: 4909 ldr r1, [pc, #36] @ (801822c ) 8018206: 68f8 ldr r0, [r7, #12] 8018208: f000 f814 bl 8018234 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 801820c: 2204 movs r2, #4 801820e: 4908 ldr r1, [pc, #32] @ (8018230 ) 8018210: 68b8 ldr r0, [r7, #8] 8018212: f000 f80f bl 8018234 } } 8018216: bf00 nop 8018218: 3710 adds r7, #16 801821a: 46bd mov sp, r7 801821c: bd80 pop {r7, pc} 801821e: bf00 nop 8018220: 1fff7590 .word 0x1fff7590 8018224: 1fff7594 .word 0x1fff7594 8018228: 1fff7598 .word 0x1fff7598 801822c: 200000f6 .word 0x200000f6 8018230: 20000106 .word 0x20000106 08018234 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 8018234: b480 push {r7} 8018236: b087 sub sp, #28 8018238: af00 add r7, sp, #0 801823a: 60f8 str r0, [r7, #12] 801823c: 60b9 str r1, [r7, #8] 801823e: 4613 mov r3, r2 8018240: 71fb strb r3, [r7, #7] uint8_t idx = 0; 8018242: 2300 movs r3, #0 8018244: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 8018246: 2300 movs r3, #0 8018248: 75fb strb r3, [r7, #23] 801824a: e027 b.n 801829c { if (((value >> 28)) < 0xA) 801824c: 68fb ldr r3, [r7, #12] 801824e: 0f1b lsrs r3, r3, #28 8018250: 2b09 cmp r3, #9 8018252: d80b bhi.n 801826c { pbuf[2 * idx] = (value >> 28) + '0'; 8018254: 68fb ldr r3, [r7, #12] 8018256: 0f1b lsrs r3, r3, #28 8018258: b2da uxtb r2, r3 801825a: 7dfb ldrb r3, [r7, #23] 801825c: 005b lsls r3, r3, #1 801825e: 4619 mov r1, r3 8018260: 68bb ldr r3, [r7, #8] 8018262: 440b add r3, r1 8018264: 3230 adds r2, #48 @ 0x30 8018266: b2d2 uxtb r2, r2 8018268: 701a strb r2, [r3, #0] 801826a: e00a b.n 8018282 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 801826c: 68fb ldr r3, [r7, #12] 801826e: 0f1b lsrs r3, r3, #28 8018270: b2da uxtb r2, r3 8018272: 7dfb ldrb r3, [r7, #23] 8018274: 005b lsls r3, r3, #1 8018276: 4619 mov r1, r3 8018278: 68bb ldr r3, [r7, #8] 801827a: 440b add r3, r1 801827c: 3237 adds r2, #55 @ 0x37 801827e: b2d2 uxtb r2, r2 8018280: 701a strb r2, [r3, #0] } value = value << 4; 8018282: 68fb ldr r3, [r7, #12] 8018284: 011b lsls r3, r3, #4 8018286: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 8018288: 7dfb ldrb r3, [r7, #23] 801828a: 005b lsls r3, r3, #1 801828c: 3301 adds r3, #1 801828e: 68ba ldr r2, [r7, #8] 8018290: 4413 add r3, r2 8018292: 2200 movs r2, #0 8018294: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 8018296: 7dfb ldrb r3, [r7, #23] 8018298: 3301 adds r3, #1 801829a: 75fb strb r3, [r7, #23] 801829c: 7dfa ldrb r2, [r7, #23] 801829e: 79fb ldrb r3, [r7, #7] 80182a0: 429a cmp r2, r3 80182a2: d3d3 bcc.n 801824c } } 80182a4: bf00 nop 80182a6: bf00 nop 80182a8: 371c adds r7, #28 80182aa: 46bd mov sp, r7 80182ac: f85d 7b04 ldr.w r7, [sp], #4 80182b0: 4770 bx lr 080182b2 : { 80182b2: b480 push {r7} 80182b4: b085 sub sp, #20 80182b6: af00 add r7, sp, #0 80182b8: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB2ENR, Periphs); 80182ba: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80182be: 6cda ldr r2, [r3, #76] @ 0x4c 80182c0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80182c4: 687b ldr r3, [r7, #4] 80182c6: 4313 orrs r3, r2 80182c8: 64cb str r3, [r1, #76] @ 0x4c tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 80182ca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80182ce: 6cda ldr r2, [r3, #76] @ 0x4c 80182d0: 687b ldr r3, [r7, #4] 80182d2: 4013 ands r3, r2 80182d4: 60fb str r3, [r7, #12] (void)tmpreg; 80182d6: 68fb ldr r3, [r7, #12] } 80182d8: bf00 nop 80182da: 3714 adds r7, #20 80182dc: 46bd mov sp, r7 80182de: f85d 7b04 ldr.w r7, [sp], #4 80182e2: 4770 bx lr 080182e4 : { 80182e4: b480 push {r7} 80182e6: b085 sub sp, #20 80182e8: af00 add r7, sp, #0 80182ea: 6078 str r0, [r7, #4] SET_BIT(RCC->APB1ENR1, Periphs); 80182ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80182f0: 6d9a ldr r2, [r3, #88] @ 0x58 80182f2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80182f6: 687b ldr r3, [r7, #4] 80182f8: 4313 orrs r3, r2 80182fa: 658b str r3, [r1, #88] @ 0x58 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 80182fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8018300: 6d9a ldr r2, [r3, #88] @ 0x58 8018302: 687b ldr r3, [r7, #4] 8018304: 4013 ands r3, r2 8018306: 60fb str r3, [r7, #12] (void)tmpreg; 8018308: 68fb ldr r3, [r7, #12] } 801830a: bf00 nop 801830c: 3714 adds r7, #20 801830e: 46bd mov sp, r7 8018310: f85d 7b04 ldr.w r7, [sp], #4 8018314: 4770 bx lr ... 08018318 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) #else void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018318: b580 push {r7, lr} 801831a: b09c sub sp, #112 @ 0x70 801831c: af00 add r7, sp, #0 801831e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8018320: f107 035c add.w r3, r7, #92 @ 0x5c 8018324: 2200 movs r2, #0 8018326: 601a str r2, [r3, #0] 8018328: 605a str r2, [r3, #4] 801832a: 609a str r2, [r3, #8] 801832c: 60da str r2, [r3, #12] 801832e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8018330: f107 030c add.w r3, r7, #12 8018334: 2250 movs r2, #80 @ 0x50 8018336: 2100 movs r1, #0 8018338: 4618 mov r0, r3 801833a: f001 fbeb bl 8019b14 if(pcdHandle->Instance==USB) 801833e: 687b ldr r3, [r7, #4] 8018340: 681b ldr r3, [r3, #0] 8018342: 4a23 ldr r2, [pc, #140] @ (80183d0 ) 8018344: 4293 cmp r3, r2 8018346: d13e bne.n 80183c6 /* USER CODE END USB_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; 8018348: f44f 7380 mov.w r3, #256 @ 0x100 801834c: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLLSAI1.PLLN = 24; 801834e: 2318 movs r3, #24 8018350: 613b str r3, [r7, #16] PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2; 8018352: f44f 3300 mov.w r3, #131072 @ 0x20000 8018356: 617b str r3, [r7, #20] PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2; 8018358: f04f 7300 mov.w r3, #33554432 @ 0x2000000 801835c: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2; 801835e: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8018362: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK; 8018364: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8018368: 623b str r3, [r7, #32] PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; 801836a: f04f 6380 mov.w r3, #67108864 @ 0x4000000 801836e: 643b str r3, [r7, #64] @ 0x40 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8018370: f107 030c add.w r3, r7, #12 8018374: 4618 mov r0, r3 8018376: f7f3 fe93 bl 800c0a0 801837a: 4603 mov r3, r0 801837c: 2b00 cmp r3, #0 801837e: d001 beq.n 8018384 { Error_Handler(); 8018380: f7ec ff4e bl 8005220 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8018384: 2001 movs r0, #1 8018386: f7ff ff94 bl 80182b2 /**USB GPIO Configuration PA11 ------> USB_DM PA12 ------> USB_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 801838a: f44f 53c0 mov.w r3, #6144 @ 0x1800 801838e: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8018390: 2302 movs r3, #2 8018392: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Pull = GPIO_NOPULL; 8018394: 2300 movs r3, #0 8018396: 667b str r3, [r7, #100] @ 0x64 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8018398: 2300 movs r3, #0 801839a: 66bb str r3, [r7, #104] @ 0x68 GPIO_InitStruct.Alternate = GPIO_AF10_USB; 801839c: 230a movs r3, #10 801839e: 66fb str r3, [r7, #108] @ 0x6c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80183a0: f107 035c add.w r3, r7, #92 @ 0x5c 80183a4: 4619 mov r1, r3 80183a6: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80183aa: f7ee fcc5 bl 8006d38 /* Peripheral clock enable */ __HAL_RCC_USB_CLK_ENABLE(); 80183ae: f04f 6080 mov.w r0, #67108864 @ 0x4000000 80183b2: f7ff ff97 bl 80182e4 /* Peripheral interrupt init */ HAL_NVIC_SetPriority(USB_LP_IRQn, 5, 0); 80183b6: 2200 movs r2, #0 80183b8: 2105 movs r1, #5 80183ba: 2014 movs r0, #20 80183bc: f7ee f988 bl 80066d0 HAL_NVIC_EnableIRQ(USB_LP_IRQn); 80183c0: 2014 movs r0, #20 80183c2: f7ee f99f bl 8006704 /* USER CODE BEGIN USB_MspInit 1 */ /* USER CODE END USB_MspInit 1 */ } } 80183c6: bf00 nop 80183c8: 3770 adds r7, #112 @ 0x70 80183ca: 46bd mov sp, r7 80183cc: bd80 pop {r7, pc} 80183ce: bf00 nop 80183d0: 40006800 .word 0x40006800 080183d4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80183d4: b580 push {r7, lr} 80183d6: b082 sub sp, #8 80183d8: af00 add r7, sp, #0 80183da: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */ /* USER CODE END HAL_PCD_SetupStageCallback_PreTreatment */ USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 80183dc: 687b ldr r3, [r7, #4] 80183de: f8d3 22d8 ldr.w r2, [r3, #728] @ 0x2d8 80183e2: 687b ldr r3, [r7, #4] 80183e4: f503 7326 add.w r3, r3, #664 @ 0x298 80183e8: 4619 mov r1, r3 80183ea: 4610 mov r0, r2 80183ec: f7f8 fe09 bl 8011002 /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */ /* USER CODE END HAL_PCD_SetupStageCallback_PostTreatment */ } 80183f0: bf00 nop 80183f2: 3708 adds r7, #8 80183f4: 46bd mov sp, r7 80183f6: bd80 pop {r7, pc} 080183f8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80183f8: b580 push {r7, lr} 80183fa: b082 sub sp, #8 80183fc: af00 add r7, sp, #0 80183fe: 6078 str r0, [r7, #4] 8018400: 460b mov r3, r1 8018402: 70fb strb r3, [r7, #3] /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */ /* USER CODE END HAL_PCD_DataOutStageCallback_PreTreatment */ USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 8018404: 687b ldr r3, [r7, #4] 8018406: f8d3 02d8 ldr.w r0, [r3, #728] @ 0x2d8 801840a: 78fa ldrb r2, [r7, #3] 801840c: 6879 ldr r1, [r7, #4] 801840e: 4613 mov r3, r2 8018410: 009b lsls r3, r3, #2 8018412: 4413 add r3, r2 8018414: 00db lsls r3, r3, #3 8018416: 440b add r3, r1 8018418: f503 73b2 add.w r3, r3, #356 @ 0x164 801841c: 681a ldr r2, [r3, #0] 801841e: 78fb ldrb r3, [r7, #3] 8018420: 4619 mov r1, r3 8018422: f7f8 fe43 bl 80110ac /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */ /* USER CODE END HAL_PCD_DataOutStageCallback_PostTreatment */ } 8018426: bf00 nop 8018428: 3708 adds r7, #8 801842a: 46bd mov sp, r7 801842c: bd80 pop {r7, pc} 0801842e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 801842e: b580 push {r7, lr} 8018430: b082 sub sp, #8 8018432: af00 add r7, sp, #0 8018434: 6078 str r0, [r7, #4] 8018436: 460b mov r3, r1 8018438: 70fb strb r3, [r7, #3] /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */ /* USER CODE END HAL_PCD_DataInStageCallback_PreTreatment */ USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 801843a: 687b ldr r3, [r7, #4] 801843c: f8d3 02d8 ldr.w r0, [r3, #728] @ 0x2d8 8018440: 78fa ldrb r2, [r7, #3] 8018442: 6879 ldr r1, [r7, #4] 8018444: 4613 mov r3, r2 8018446: 009b lsls r3, r3, #2 8018448: 4413 add r3, r2 801844a: 00db lsls r3, r3, #3 801844c: 440b add r3, r1 801844e: 3324 adds r3, #36 @ 0x24 8018450: 681a ldr r2, [r3, #0] 8018452: 78fb ldrb r3, [r7, #3] 8018454: 4619 mov r1, r3 8018456: f7f8 fee5 bl 8011224 /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment */ /* USER CODE END HAL_PCD_DataInStageCallback_PostTreatment */ } 801845a: bf00 nop 801845c: 3708 adds r7, #8 801845e: 46bd mov sp, r7 8018460: bd80 pop {r7, pc} 08018462 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018462: b580 push {r7, lr} 8018464: b082 sub sp, #8 8018466: af00 add r7, sp, #0 8018468: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */ /* USER CODE END HAL_PCD_SOFCallback_PreTreatment */ USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 801846a: 687b ldr r3, [r7, #4] 801846c: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8018470: 4618 mov r0, r3 8018472: f7f9 f829 bl 80114c8 /* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */ /* USER CODE END HAL_PCD_SOFCallback_PostTreatment */ } 8018476: bf00 nop 8018478: 3708 adds r7, #8 801847a: 46bd mov sp, r7 801847c: bd80 pop {r7, pc} 0801847e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 801847e: b580 push {r7, lr} 8018480: b084 sub sp, #16 8018482: af00 add r7, sp, #0 8018484: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */ /* USER CODE END HAL_PCD_ResetCallback_PreTreatment */ USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 8018486: 2301 movs r3, #1 8018488: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed != PCD_SPEED_FULL) 801848a: 687b ldr r3, [r7, #4] 801848c: 795b ldrb r3, [r3, #5] 801848e: 2b02 cmp r3, #2 8018490: d001 beq.n 8018496 { Error_Handler(); 8018492: f7ec fec5 bl 8005220 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 8018496: 687b ldr r3, [r7, #4] 8018498: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 801849c: 7bfa ldrb r2, [r7, #15] 801849e: 4611 mov r1, r2 80184a0: 4618 mov r0, r3 80184a2: f7f8 ffcd bl 8011440 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 80184a6: 687b ldr r3, [r7, #4] 80184a8: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 80184ac: 4618 mov r0, r3 80184ae: f7f8 ff74 bl 801139a /* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */ /* USER CODE END HAL_PCD_ResetCallback_PostTreatment */ } 80184b2: bf00 nop 80184b4: 3710 adds r7, #16 80184b6: 46bd mov sp, r7 80184b8: bd80 pop {r7, pc} ... 080184bc : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80184bc: b580 push {r7, lr} 80184be: b082 sub sp, #8 80184c0: af00 add r7, sp, #0 80184c2: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */ /* USER CODE END HAL_PCD_SuspendCallback_PreTreatment */ /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 80184c4: 687b ldr r3, [r7, #4] 80184c6: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 80184ca: 4618 mov r0, r3 80184cc: f7f8 ffc8 bl 8011460 /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 80184d0: 687b ldr r3, [r7, #4] 80184d2: 7a5b ldrb r3, [r3, #9] 80184d4: 2b00 cmp r3, #0 80184d6: d005 beq.n 80184e4 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 80184d8: 4b04 ldr r3, [pc, #16] @ (80184ec ) 80184da: 691b ldr r3, [r3, #16] 80184dc: 4a03 ldr r2, [pc, #12] @ (80184ec ) 80184de: f043 0306 orr.w r3, r3, #6 80184e2: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ /* USER CODE BEGIN HAL_PCD_SuspendCallback_PostTreatment */ /* USER CODE END HAL_PCD_SuspendCallback_PostTreatment */ } 80184e4: bf00 nop 80184e6: 3708 adds r7, #8 80184e8: 46bd mov sp, r7 80184ea: bd80 pop {r7, pc} 80184ec: e000ed00 .word 0xe000ed00 080184f0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80184f0: b580 push {r7, lr} 80184f2: b082 sub sp, #8 80184f4: af00 add r7, sp, #0 80184f6: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */ /* USER CODE END HAL_PCD_ResumeCallback_PreTreatment */ /* USER CODE BEGIN 3 */ if (hpcd->Init.low_power_enable) 80184f8: 687b ldr r3, [r7, #4] 80184fa: 7a5b ldrb r3, [r3, #9] 80184fc: 2b00 cmp r3, #0 80184fe: d007 beq.n 8018510 { /* Reset SLEEPDEEP bit of Cortex System Control Register. */ SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 8018500: 4b08 ldr r3, [pc, #32] @ (8018524 ) 8018502: 691b ldr r3, [r3, #16] 8018504: 4a07 ldr r2, [pc, #28] @ (8018524 ) 8018506: f023 0306 bic.w r3, r3, #6 801850a: 6113 str r3, [r2, #16] SystemClockConfig_Resume(); 801850c: f000 f9fa bl 8018904 } /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 8018510: 687b ldr r3, [r7, #4] 8018512: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8018516: 4618 mov r0, r3 8018518: f7f8 ffbe bl 8011498 /* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */ /* USER CODE END HAL_PCD_ResumeCallback_PostTreatment */ } 801851c: bf00 nop 801851e: 3708 adds r7, #8 8018520: 46bd mov sp, r7 8018522: bd80 pop {r7, pc} 8018524: e000ed00 .word 0xe000ed00 08018528 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 8018528: b580 push {r7, lr} 801852a: b082 sub sp, #8 801852c: af00 add r7, sp, #0 801852e: 6078 str r0, [r7, #4] /* Init USB Ip. */ hpcd_USB_FS.pData = pdev; 8018530: 4a2c ldr r2, [pc, #176] @ (80185e4 ) 8018532: 687b ldr r3, [r7, #4] 8018534: f8c2 32d8 str.w r3, [r2, #728] @ 0x2d8 /* Link the driver to the stack. */ pdev->pData = &hpcd_USB_FS; 8018538: 687b ldr r3, [r7, #4] 801853a: 4a2a ldr r2, [pc, #168] @ (80185e4 ) 801853c: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 /* Enable USB power on Pwrctrl CR2 register. */ HAL_PWREx_EnableVddUSB(); 8018540: f7f2 fa40 bl 800a9c4 hpcd_USB_FS.Instance = USB; 8018544: 4b27 ldr r3, [pc, #156] @ (80185e4 ) 8018546: 4a28 ldr r2, [pc, #160] @ (80185e8 ) 8018548: 601a str r2, [r3, #0] hpcd_USB_FS.Init.dev_endpoints = 8; 801854a: 4b26 ldr r3, [pc, #152] @ (80185e4 ) 801854c: 2208 movs r2, #8 801854e: 711a strb r2, [r3, #4] hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; 8018550: 4b24 ldr r3, [pc, #144] @ (80185e4 ) 8018552: 2202 movs r2, #2 8018554: 715a strb r2, [r3, #5] hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 8018556: 4b23 ldr r3, [pc, #140] @ (80185e4 ) 8018558: 2202 movs r2, #2 801855a: 71da strb r2, [r3, #7] hpcd_USB_FS.Init.Sof_enable = DISABLE; 801855c: 4b21 ldr r3, [pc, #132] @ (80185e4 ) 801855e: 2200 movs r2, #0 8018560: 721a strb r2, [r3, #8] hpcd_USB_FS.Init.low_power_enable = DISABLE; 8018562: 4b20 ldr r3, [pc, #128] @ (80185e4 ) 8018564: 2200 movs r2, #0 8018566: 725a strb r2, [r3, #9] hpcd_USB_FS.Init.lpm_enable = DISABLE; 8018568: 4b1e ldr r3, [pc, #120] @ (80185e4 ) 801856a: 2200 movs r2, #0 801856c: 729a strb r2, [r3, #10] hpcd_USB_FS.Init.battery_charging_enable = DISABLE; 801856e: 4b1d ldr r3, [pc, #116] @ (80185e4 ) 8018570: 2200 movs r2, #0 8018572: 72da strb r2, [r3, #11] /* register Msp Callbacks (before the Init) */ HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPINIT_CB_ID, PCD_MspInit); HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPDEINIT_CB_ID, PCD_MspDeInit); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) 8018574: 481b ldr r0, [pc, #108] @ (80185e4 ) 8018576: f7f0 fcc5 bl 8008f04 801857a: 4603 mov r3, r0 801857c: 2b00 cmp r3, #0 801857e: d001 beq.n 8018584 { Error_Handler( ); 8018580: f7ec fe4e bl 8005220 /* USER CODE BEGIN RegisterCallBackSecondPart */ /* USER CODE END RegisterCallBackSecondPart */ #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* USER CODE BEGIN EndPoint_Configuration */ HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); 8018584: 687b ldr r3, [r7, #4] 8018586: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 801858a: 2318 movs r3, #24 801858c: 2200 movs r2, #0 801858e: 2100 movs r1, #0 8018590: f7f2 f98d bl 800a8ae HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); 8018594: 687b ldr r3, [r7, #4] 8018596: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 801859a: 2358 movs r3, #88 @ 0x58 801859c: 2200 movs r2, #0 801859e: 2180 movs r1, #128 @ 0x80 80185a0: f7f2 f985 bl 800a8ae /* USER CODE END EndPoint_Configuration */ /* USER CODE BEGIN EndPoint_Configuration_CDC */ HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); 80185a4: 687b ldr r3, [r7, #4] 80185a6: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 80185aa: 23c0 movs r3, #192 @ 0xc0 80185ac: 2200 movs r2, #0 80185ae: 2181 movs r1, #129 @ 0x81 80185b0: f7f2 f97d bl 800a8ae HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); 80185b4: 687b ldr r3, [r7, #4] 80185b6: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 80185ba: f44f 7388 mov.w r3, #272 @ 0x110 80185be: 2200 movs r2, #0 80185c0: 2101 movs r1, #1 80185c2: f7f2 f974 bl 800a8ae HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); 80185c6: 687b ldr r3, [r7, #4] 80185c8: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 80185cc: f44f 7380 mov.w r3, #256 @ 0x100 80185d0: 2200 movs r2, #0 80185d2: 2182 movs r1, #130 @ 0x82 80185d4: f7f2 f96b bl 800a8ae /* USER CODE END EndPoint_Configuration_CDC */ return USBD_OK; 80185d8: 2300 movs r3, #0 } 80185da: 4618 mov r0, r3 80185dc: 3708 adds r7, #8 80185de: 46bd mov sp, r7 80185e0: bd80 pop {r7, pc} 80185e2: bf00 nop 80185e4: 200135f8 .word 0x200135f8 80185e8: 40006800 .word 0x40006800 080185ec : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 80185ec: b580 push {r7, lr} 80185ee: b084 sub sp, #16 80185f0: af00 add r7, sp, #0 80185f2: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 80185f4: 2300 movs r3, #0 80185f6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80185f8: 2300 movs r3, #0 80185fa: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 80185fc: 687b ldr r3, [r7, #4] 80185fe: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 8018602: 4618 mov r0, r3 8018604: f7f0 fd4c bl 80090a0 8018608: 4603 mov r3, r0 801860a: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 801860c: 7bfb ldrb r3, [r7, #15] 801860e: 4618 mov r0, r3 8018610: f000 f97e bl 8018910 8018614: 4603 mov r3, r0 8018616: 73bb strb r3, [r7, #14] return usb_status; 8018618: 7bbb ldrb r3, [r7, #14] } 801861a: 4618 mov r0, r3 801861c: 3710 adds r7, #16 801861e: 46bd mov sp, r7 8018620: bd80 pop {r7, pc} 08018622 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 8018622: b580 push {r7, lr} 8018624: b084 sub sp, #16 8018626: af00 add r7, sp, #0 8018628: 6078 str r0, [r7, #4] 801862a: 4608 mov r0, r1 801862c: 4611 mov r1, r2 801862e: 461a mov r2, r3 8018630: 4603 mov r3, r0 8018632: 70fb strb r3, [r7, #3] 8018634: 460b mov r3, r1 8018636: 70bb strb r3, [r7, #2] 8018638: 4613 mov r3, r2 801863a: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 801863c: 2300 movs r3, #0 801863e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8018640: 2300 movs r3, #0 8018642: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 8018644: 687b ldr r3, [r7, #4] 8018646: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 801864a: 78bb ldrb r3, [r7, #2] 801864c: 883a ldrh r2, [r7, #0] 801864e: 78f9 ldrb r1, [r7, #3] 8018650: f7f0 fe93 bl 800937a 8018654: 4603 mov r3, r0 8018656: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8018658: 7bfb ldrb r3, [r7, #15] 801865a: 4618 mov r0, r3 801865c: f000 f958 bl 8018910 8018660: 4603 mov r3, r0 8018662: 73bb strb r3, [r7, #14] return usb_status; 8018664: 7bbb ldrb r3, [r7, #14] } 8018666: 4618 mov r0, r3 8018668: 3710 adds r7, #16 801866a: 46bd mov sp, r7 801866c: bd80 pop {r7, pc} 0801866e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 801866e: b580 push {r7, lr} 8018670: b084 sub sp, #16 8018672: af00 add r7, sp, #0 8018674: 6078 str r0, [r7, #4] 8018676: 460b mov r3, r1 8018678: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 801867a: 2300 movs r3, #0 801867c: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 801867e: 2300 movs r3, #0 8018680: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 8018682: 687b ldr r3, [r7, #4] 8018684: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 8018688: 78fa ldrb r2, [r7, #3] 801868a: 4611 mov r1, r2 801868c: 4618 mov r0, r3 801868e: f7f0 fed3 bl 8009438 8018692: 4603 mov r3, r0 8018694: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8018696: 7bfb ldrb r3, [r7, #15] 8018698: 4618 mov r0, r3 801869a: f000 f939 bl 8018910 801869e: 4603 mov r3, r0 80186a0: 73bb strb r3, [r7, #14] return usb_status; 80186a2: 7bbb ldrb r3, [r7, #14] } 80186a4: 4618 mov r0, r3 80186a6: 3710 adds r7, #16 80186a8: 46bd mov sp, r7 80186aa: bd80 pop {r7, pc} 080186ac : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 80186ac: b580 push {r7, lr} 80186ae: b084 sub sp, #16 80186b0: af00 add r7, sp, #0 80186b2: 6078 str r0, [r7, #4] 80186b4: 460b mov r3, r1 80186b6: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 80186b8: 2300 movs r3, #0 80186ba: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80186bc: 2300 movs r3, #0 80186be: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 80186c0: 687b ldr r3, [r7, #4] 80186c2: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 80186c6: 78fa ldrb r2, [r7, #3] 80186c8: 4611 mov r1, r2 80186ca: 4618 mov r0, r3 80186cc: f7f0 ff7c bl 80095c8 80186d0: 4603 mov r3, r0 80186d2: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 80186d4: 7bfb ldrb r3, [r7, #15] 80186d6: 4618 mov r0, r3 80186d8: f000 f91a bl 8018910 80186dc: 4603 mov r3, r0 80186de: 73bb strb r3, [r7, #14] return usb_status; 80186e0: 7bbb ldrb r3, [r7, #14] } 80186e2: 4618 mov r0, r3 80186e4: 3710 adds r7, #16 80186e6: 46bd mov sp, r7 80186e8: bd80 pop {r7, pc} 080186ea : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 80186ea: b580 push {r7, lr} 80186ec: b084 sub sp, #16 80186ee: af00 add r7, sp, #0 80186f0: 6078 str r0, [r7, #4] 80186f2: 460b mov r3, r1 80186f4: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 80186f6: 2300 movs r3, #0 80186f8: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80186fa: 2300 movs r3, #0 80186fc: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 80186fe: 687b ldr r3, [r7, #4] 8018700: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 8018704: 78fa ldrb r2, [r7, #3] 8018706: 4611 mov r1, r2 8018708: 4618 mov r0, r3 801870a: f7f0 ffaf bl 800966c 801870e: 4603 mov r3, r0 8018710: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8018712: 7bfb ldrb r3, [r7, #15] 8018714: 4618 mov r0, r3 8018716: f000 f8fb bl 8018910 801871a: 4603 mov r3, r0 801871c: 73bb strb r3, [r7, #14] return usb_status; 801871e: 7bbb ldrb r3, [r7, #14] } 8018720: 4618 mov r0, r3 8018722: 3710 adds r7, #16 8018724: 46bd mov sp, r7 8018726: bd80 pop {r7, pc} 08018728 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8018728: b480 push {r7} 801872a: b085 sub sp, #20 801872c: af00 add r7, sp, #0 801872e: 6078 str r0, [r7, #4] 8018730: 460b mov r3, r1 8018732: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 8018734: 687b ldr r3, [r7, #4] 8018736: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 801873a: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 801873c: f997 3003 ldrsb.w r3, [r7, #3] 8018740: 2b00 cmp r3, #0 8018742: da0b bge.n 801875c { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 8018744: 78fb ldrb r3, [r7, #3] 8018746: f003 027f and.w r2, r3, #127 @ 0x7f 801874a: 68f9 ldr r1, [r7, #12] 801874c: 4613 mov r3, r2 801874e: 009b lsls r3, r3, #2 8018750: 4413 add r3, r2 8018752: 00db lsls r3, r3, #3 8018754: 440b add r3, r1 8018756: 3312 adds r3, #18 8018758: 781b ldrb r3, [r3, #0] 801875a: e00b b.n 8018774 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 801875c: 78fb ldrb r3, [r7, #3] 801875e: f003 027f and.w r2, r3, #127 @ 0x7f 8018762: 68f9 ldr r1, [r7, #12] 8018764: 4613 mov r3, r2 8018766: 009b lsls r3, r3, #2 8018768: 4413 add r3, r2 801876a: 00db lsls r3, r3, #3 801876c: 440b add r3, r1 801876e: f503 73a9 add.w r3, r3, #338 @ 0x152 8018772: 781b ldrb r3, [r3, #0] } } 8018774: 4618 mov r0, r3 8018776: 3714 adds r7, #20 8018778: 46bd mov sp, r7 801877a: f85d 7b04 ldr.w r7, [sp], #4 801877e: 4770 bx lr 08018780 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 8018780: b580 push {r7, lr} 8018782: b084 sub sp, #16 8018784: af00 add r7, sp, #0 8018786: 6078 str r0, [r7, #4] 8018788: 460b mov r3, r1 801878a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 801878c: 2300 movs r3, #0 801878e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8018790: 2300 movs r3, #0 8018792: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 8018794: 687b ldr r3, [r7, #4] 8018796: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 801879a: 78fa ldrb r2, [r7, #3] 801879c: 4611 mov r1, r2 801879e: 4618 mov r0, r3 80187a0: f7f0 fdc7 bl 8009332 80187a4: 4603 mov r3, r0 80187a6: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 80187a8: 7bfb ldrb r3, [r7, #15] 80187aa: 4618 mov r0, r3 80187ac: f000 f8b0 bl 8018910 80187b0: 4603 mov r3, r0 80187b2: 73bb strb r3, [r7, #14] return usb_status; 80187b4: 7bbb ldrb r3, [r7, #14] } 80187b6: 4618 mov r0, r3 80187b8: 3710 adds r7, #16 80187ba: 46bd mov sp, r7 80187bc: bd80 pop {r7, pc} 080187be : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 80187be: b580 push {r7, lr} 80187c0: b086 sub sp, #24 80187c2: af00 add r7, sp, #0 80187c4: 60f8 str r0, [r7, #12] 80187c6: 607a str r2, [r7, #4] 80187c8: 603b str r3, [r7, #0] 80187ca: 460b mov r3, r1 80187cc: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 80187ce: 2300 movs r3, #0 80187d0: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 80187d2: 2300 movs r3, #0 80187d4: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 80187d6: 68fb ldr r3, [r7, #12] 80187d8: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 80187dc: 7af9 ldrb r1, [r7, #11] 80187de: 683b ldr r3, [r7, #0] 80187e0: 687a ldr r2, [r7, #4] 80187e2: f7f0 feba bl 800955a 80187e6: 4603 mov r3, r0 80187e8: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 80187ea: 7dfb ldrb r3, [r7, #23] 80187ec: 4618 mov r0, r3 80187ee: f000 f88f bl 8018910 80187f2: 4603 mov r3, r0 80187f4: 75bb strb r3, [r7, #22] return usb_status; 80187f6: 7dbb ldrb r3, [r7, #22] } 80187f8: 4618 mov r0, r3 80187fa: 3718 adds r7, #24 80187fc: 46bd mov sp, r7 80187fe: bd80 pop {r7, pc} 08018800 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 8018800: b580 push {r7, lr} 8018802: b086 sub sp, #24 8018804: af00 add r7, sp, #0 8018806: 60f8 str r0, [r7, #12] 8018808: 607a str r2, [r7, #4] 801880a: 603b str r3, [r7, #0] 801880c: 460b mov r3, r1 801880e: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 8018810: 2300 movs r3, #0 8018812: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 8018814: 2300 movs r3, #0 8018816: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 8018818: 68fb ldr r3, [r7, #12] 801881a: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 801881e: 7af9 ldrb r1, [r7, #11] 8018820: 683b ldr r3, [r7, #0] 8018822: 687a ldr r2, [r7, #4] 8018824: f7f0 fe50 bl 80094c8 8018828: 4603 mov r3, r0 801882a: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 801882c: 7dfb ldrb r3, [r7, #23] 801882e: 4618 mov r0, r3 8018830: f000 f86e bl 8018910 8018834: 4603 mov r3, r0 8018836: 75bb strb r3, [r7, #22] return usb_status; 8018838: 7dbb ldrb r3, [r7, #22] } 801883a: 4618 mov r0, r3 801883c: 3718 adds r7, #24 801883e: 46bd mov sp, r7 8018840: bd80 pop {r7, pc} 08018842 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Received Data Size */ uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8018842: b580 push {r7, lr} 8018844: b082 sub sp, #8 8018846: af00 add r7, sp, #0 8018848: 6078 str r0, [r7, #4] 801884a: 460b mov r3, r1 801884c: 70fb strb r3, [r7, #3] return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); 801884e: 687b ldr r3, [r7, #4] 8018850: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 8018854: 78fa ldrb r2, [r7, #3] 8018856: 4611 mov r1, r2 8018858: 4618 mov r0, r3 801885a: f7f0 fe66 bl 800952a 801885e: 4603 mov r3, r0 } 8018860: 4618 mov r0, r3 8018862: 3708 adds r7, #8 8018864: 46bd mov sp, r7 8018866: bd80 pop {r7, pc} 08018868 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) #else void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018868: b580 push {r7, lr} 801886a: b082 sub sp, #8 801886c: af00 add r7, sp, #0 801886e: 6078 str r0, [r7, #4] 8018870: 460b mov r3, r1 8018872: 70fb strb r3, [r7, #3] /* USER CODE BEGIN LPM_Callback */ switch (msg) 8018874: 78fb ldrb r3, [r7, #3] 8018876: 2b00 cmp r3, #0 8018878: d002 beq.n 8018880 801887a: 2b01 cmp r3, #1 801887c: d013 beq.n 80188a6 SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } /* USER CODE END LPM_Callback */ } 801887e: e023 b.n 80188c8 if (hpcd->Init.low_power_enable) 8018880: 687b ldr r3, [r7, #4] 8018882: 7a5b ldrb r3, [r3, #9] 8018884: 2b00 cmp r3, #0 8018886: d007 beq.n 8018898 SystemClockConfig_Resume(); 8018888: f000 f83c bl 8018904 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 801888c: 4b10 ldr r3, [pc, #64] @ (80188d0 ) 801888e: 691b ldr r3, [r3, #16] 8018890: 4a0f ldr r2, [pc, #60] @ (80188d0 ) 8018892: f023 0306 bic.w r3, r3, #6 8018896: 6113 str r3, [r2, #16] USBD_LL_Resume(hpcd->pData); 8018898: 687b ldr r3, [r7, #4] 801889a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 801889e: 4618 mov r0, r3 80188a0: f7f8 fdfa bl 8011498 break; 80188a4: e010 b.n 80188c8 USBD_LL_Suspend(hpcd->pData); 80188a6: 687b ldr r3, [r7, #4] 80188a8: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 80188ac: 4618 mov r0, r3 80188ae: f7f8 fdd7 bl 8011460 if (hpcd->Init.low_power_enable) 80188b2: 687b ldr r3, [r7, #4] 80188b4: 7a5b ldrb r3, [r3, #9] 80188b6: 2b00 cmp r3, #0 80188b8: d005 beq.n 80188c6 SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 80188ba: 4b05 ldr r3, [pc, #20] @ (80188d0 ) 80188bc: 691b ldr r3, [r3, #16] 80188be: 4a04 ldr r2, [pc, #16] @ (80188d0 ) 80188c0: f043 0306 orr.w r3, r3, #6 80188c4: 6113 str r3, [r2, #16] break; 80188c6: bf00 nop } 80188c8: bf00 nop 80188ca: 3708 adds r7, #8 80188cc: 46bd mov sp, r7 80188ce: bd80 pop {r7, pc} 80188d0: e000ed00 .word 0xe000ed00 080188d4 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 80188d4: b480 push {r7} 80188d6: b083 sub sp, #12 80188d8: af00 add r7, sp, #0 80188da: 6078 str r0, [r7, #4] UNUSED(size); static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 80188dc: 4b03 ldr r3, [pc, #12] @ (80188ec ) } 80188de: 4618 mov r0, r3 80188e0: 370c adds r7, #12 80188e2: 46bd mov sp, r7 80188e4: f85d 7b04 ldr.w r7, [sp], #4 80188e8: 4770 bx lr 80188ea: bf00 nop 80188ec: 200138d4 .word 0x200138d4 080188f0 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 80188f0: b480 push {r7} 80188f2: b083 sub sp, #12 80188f4: af00 add r7, sp, #0 80188f6: 6078 str r0, [r7, #4] UNUSED(p); } 80188f8: bf00 nop 80188fa: 370c adds r7, #12 80188fc: 46bd mov sp, r7 80188fe: f85d 7b04 ldr.w r7, [sp], #4 8018902: 4770 bx lr 08018904 : * @brief Configures system clock after wake-up from USB resume callBack: * enable HSI, PLL and select PLL as system clock source. * @retval None */ static void SystemClockConfig_Resume(void) { 8018904: b580 push {r7, lr} 8018906: af00 add r7, sp, #0 SystemClock_Config(); 8018908: f7eb ff96 bl 8004838 } 801890c: bf00 nop 801890e: bd80 pop {r7, pc} 08018910 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 8018910: b480 push {r7} 8018912: b085 sub sp, #20 8018914: af00 add r7, sp, #0 8018916: 4603 mov r3, r0 8018918: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 801891a: 2300 movs r3, #0 801891c: 73fb strb r3, [r7, #15] switch (hal_status) 801891e: 79fb ldrb r3, [r7, #7] 8018920: 2b03 cmp r3, #3 8018922: d817 bhi.n 8018954 8018924: a201 add r2, pc, #4 @ (adr r2, 801892c ) 8018926: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801892a: bf00 nop 801892c: 0801893d .word 0x0801893d 8018930: 08018943 .word 0x08018943 8018934: 08018949 .word 0x08018949 8018938: 0801894f .word 0x0801894f { case HAL_OK : usb_status = USBD_OK; 801893c: 2300 movs r3, #0 801893e: 73fb strb r3, [r7, #15] break; 8018940: e00b b.n 801895a case HAL_ERROR : usb_status = USBD_FAIL; 8018942: 2303 movs r3, #3 8018944: 73fb strb r3, [r7, #15] break; 8018946: e008 b.n 801895a case HAL_BUSY : usb_status = USBD_BUSY; 8018948: 2301 movs r3, #1 801894a: 73fb strb r3, [r7, #15] break; 801894c: e005 b.n 801895a case HAL_TIMEOUT : usb_status = USBD_FAIL; 801894e: 2303 movs r3, #3 8018950: 73fb strb r3, [r7, #15] break; 8018952: e002 b.n 801895a default : usb_status = USBD_FAIL; 8018954: 2303 movs r3, #3 8018956: 73fb strb r3, [r7, #15] break; 8018958: bf00 nop } return usb_status; 801895a: 7bfb ldrb r3, [r7, #15] } 801895c: 4618 mov r0, r3 801895e: 3714 adds r7, #20 8018960: 46bd mov sp, r7 8018962: f85d 7b04 ldr.w r7, [sp], #4 8018966: 4770 bx lr 08018968 : /** @addtogroup TINY_LPM_Exported_function * @{ */ void UTIL_LPM_Init( void ) { 8018968: b480 push {r7} 801896a: af00 add r7, sp, #0 StopModeDisable = UTIL_LPM_NO_BIT_SET; 801896c: 4b05 ldr r3, [pc, #20] @ (8018984 ) 801896e: 2200 movs r2, #0 8018970: 601a str r2, [r3, #0] OffModeDisable = UTIL_LPM_NO_BIT_SET; 8018972: 4b05 ldr r3, [pc, #20] @ (8018988 ) 8018974: 2200 movs r2, #0 8018976: 601a str r2, [r3, #0] UTIL_LPM_INIT_CRITICAL_SECTION( ); } 8018978: bf00 nop 801897a: 46bd mov sp, r7 801897c: f85d 7b04 ldr.w r7, [sp], #4 8018980: 4770 bx lr 8018982: bf00 nop 8018984: 20013af4 .word 0x20013af4 8018988: 20013af8 .word 0x20013af8 0801898c : UTIL_LPM_EXIT_CRITICAL_SECTION( ); } void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) { 801898c: b480 push {r7} 801898e: b087 sub sp, #28 8018990: af00 add r7, sp, #0 8018992: 6078 str r0, [r7, #4] 8018994: 460b mov r3, r1 8018996: 70fb strb r3, [r7, #3] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8018998: f3ef 8310 mrs r3, PRIMASK 801899c: 613b str r3, [r7, #16] return(result); 801899e: 693b ldr r3, [r7, #16] UTIL_LPM_ENTER_CRITICAL_SECTION( ); 80189a0: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 80189a2: b672 cpsid i } 80189a4: bf00 nop switch(state) 80189a6: 78fb ldrb r3, [r7, #3] 80189a8: 2b00 cmp r3, #0 80189aa: d008 beq.n 80189be 80189ac: 2b01 cmp r3, #1 80189ae: d10e bne.n 80189ce { case UTIL_LPM_DISABLE: { OffModeDisable |= lpm_id_bm; 80189b0: 4b0d ldr r3, [pc, #52] @ (80189e8 ) 80189b2: 681a ldr r2, [r3, #0] 80189b4: 687b ldr r3, [r7, #4] 80189b6: 4313 orrs r3, r2 80189b8: 4a0b ldr r2, [pc, #44] @ (80189e8 ) 80189ba: 6013 str r3, [r2, #0] break; 80189bc: e008 b.n 80189d0 } case UTIL_LPM_ENABLE: { OffModeDisable &= ( ~lpm_id_bm ); 80189be: 687b ldr r3, [r7, #4] 80189c0: 43da mvns r2, r3 80189c2: 4b09 ldr r3, [pc, #36] @ (80189e8 ) 80189c4: 681b ldr r3, [r3, #0] 80189c6: 4013 ands r3, r2 80189c8: 4a07 ldr r2, [pc, #28] @ (80189e8 ) 80189ca: 6013 str r3, [r2, #0] break; 80189cc: e000 b.n 80189d0 } default : { break; 80189ce: bf00 nop 80189d0: 697b ldr r3, [r7, #20] 80189d2: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80189d4: 68fb ldr r3, [r7, #12] 80189d6: f383 8810 msr PRIMASK, r3 } 80189da: bf00 nop } } UTIL_LPM_EXIT_CRITICAL_SECTION( ); } 80189dc: bf00 nop 80189de: 371c adds r7, #28 80189e0: 46bd mov sp, r7 80189e2: f85d 7b04 ldr.w r7, [sp], #4 80189e6: 4770 bx lr 80189e8: 20013af8 .word 0x20013af8 080189ec <__cvt>: 80189ec: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 80189f0: ec57 6b10 vmov r6, r7, d0 80189f4: 2f00 cmp r7, #0 80189f6: 460c mov r4, r1 80189f8: 4619 mov r1, r3 80189fa: 463b mov r3, r7 80189fc: bfbb ittet lt 80189fe: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000 8018a02: 461f movlt r7, r3 8018a04: 2300 movge r3, #0 8018a06: 232d movlt r3, #45 @ 0x2d 8018a08: 700b strb r3, [r1, #0] 8018a0a: 9b0d ldr r3, [sp, #52] @ 0x34 8018a0c: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 8018a10: 4691 mov r9, r2 8018a12: f023 0820 bic.w r8, r3, #32 8018a16: bfbc itt lt 8018a18: 4632 movlt r2, r6 8018a1a: 4616 movlt r6, r2 8018a1c: f1b8 0f46 cmp.w r8, #70 @ 0x46 8018a20: d005 beq.n 8018a2e <__cvt+0x42> 8018a22: f1b8 0f45 cmp.w r8, #69 @ 0x45 8018a26: d100 bne.n 8018a2a <__cvt+0x3e> 8018a28: 3401 adds r4, #1 8018a2a: 2102 movs r1, #2 8018a2c: e000 b.n 8018a30 <__cvt+0x44> 8018a2e: 2103 movs r1, #3 8018a30: ab03 add r3, sp, #12 8018a32: 9301 str r3, [sp, #4] 8018a34: ab02 add r3, sp, #8 8018a36: 9300 str r3, [sp, #0] 8018a38: ec47 6b10 vmov d0, r6, r7 8018a3c: 4653 mov r3, sl 8018a3e: 4622 mov r2, r4 8018a40: f001 f986 bl 8019d50 <_dtoa_r> 8018a44: f1b8 0f47 cmp.w r8, #71 @ 0x47 8018a48: 4605 mov r5, r0 8018a4a: d119 bne.n 8018a80 <__cvt+0x94> 8018a4c: f019 0f01 tst.w r9, #1 8018a50: d00e beq.n 8018a70 <__cvt+0x84> 8018a52: eb00 0904 add.w r9, r0, r4 8018a56: 2200 movs r2, #0 8018a58: 2300 movs r3, #0 8018a5a: 4630 mov r0, r6 8018a5c: 4639 mov r1, r7 8018a5e: f7e8 f80b bl 8000a78 <__aeabi_dcmpeq> 8018a62: b108 cbz r0, 8018a68 <__cvt+0x7c> 8018a64: f8cd 900c str.w r9, [sp, #12] 8018a68: 2230 movs r2, #48 @ 0x30 8018a6a: 9b03 ldr r3, [sp, #12] 8018a6c: 454b cmp r3, r9 8018a6e: d31e bcc.n 8018aae <__cvt+0xc2> 8018a70: 9b03 ldr r3, [sp, #12] 8018a72: 9a0e ldr r2, [sp, #56] @ 0x38 8018a74: 1b5b subs r3, r3, r5 8018a76: 4628 mov r0, r5 8018a78: 6013 str r3, [r2, #0] 8018a7a: b004 add sp, #16 8018a7c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8018a80: f1b8 0f46 cmp.w r8, #70 @ 0x46 8018a84: eb00 0904 add.w r9, r0, r4 8018a88: d1e5 bne.n 8018a56 <__cvt+0x6a> 8018a8a: 7803 ldrb r3, [r0, #0] 8018a8c: 2b30 cmp r3, #48 @ 0x30 8018a8e: d10a bne.n 8018aa6 <__cvt+0xba> 8018a90: 2200 movs r2, #0 8018a92: 2300 movs r3, #0 8018a94: 4630 mov r0, r6 8018a96: 4639 mov r1, r7 8018a98: f7e7 ffee bl 8000a78 <__aeabi_dcmpeq> 8018a9c: b918 cbnz r0, 8018aa6 <__cvt+0xba> 8018a9e: f1c4 0401 rsb r4, r4, #1 8018aa2: f8ca 4000 str.w r4, [sl] 8018aa6: f8da 3000 ldr.w r3, [sl] 8018aaa: 4499 add r9, r3 8018aac: e7d3 b.n 8018a56 <__cvt+0x6a> 8018aae: 1c59 adds r1, r3, #1 8018ab0: 9103 str r1, [sp, #12] 8018ab2: 701a strb r2, [r3, #0] 8018ab4: e7d9 b.n 8018a6a <__cvt+0x7e> 08018ab6 <__exponent>: 8018ab6: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8018ab8: 2900 cmp r1, #0 8018aba: bfba itte lt 8018abc: 4249 neglt r1, r1 8018abe: 232d movlt r3, #45 @ 0x2d 8018ac0: 232b movge r3, #43 @ 0x2b 8018ac2: 2909 cmp r1, #9 8018ac4: 7002 strb r2, [r0, #0] 8018ac6: 7043 strb r3, [r0, #1] 8018ac8: dd29 ble.n 8018b1e <__exponent+0x68> 8018aca: f10d 0407 add.w r4, sp, #7 8018ace: 4625 mov r5, r4 8018ad0: 270a movs r7, #10 8018ad2: 4622 mov r2, r4 8018ad4: fbb1 f6f7 udiv r6, r1, r7 8018ad8: fb07 1316 mls r3, r7, r6, r1 8018adc: 3330 adds r3, #48 @ 0x30 8018ade: f802 3c01 strb.w r3, [r2, #-1] 8018ae2: 460b mov r3, r1 8018ae4: 2b63 cmp r3, #99 @ 0x63 8018ae6: f104 34ff add.w r4, r4, #4294967295 @ 0xffffffff 8018aea: 4631 mov r1, r6 8018aec: dcf1 bgt.n 8018ad2 <__exponent+0x1c> 8018aee: 3130 adds r1, #48 @ 0x30 8018af0: 1e93 subs r3, r2, #2 8018af2: f804 1c01 strb.w r1, [r4, #-1] 8018af6: 1c41 adds r1, r0, #1 8018af8: 461c mov r4, r3 8018afa: 42ab cmp r3, r5 8018afc: d30a bcc.n 8018b14 <__exponent+0x5e> 8018afe: f10d 0309 add.w r3, sp, #9 8018b02: 1a9b subs r3, r3, r2 8018b04: 42a5 cmp r5, r4 8018b06: bf38 it cc 8018b08: 2300 movcc r3, #0 8018b0a: 1c82 adds r2, r0, #2 8018b0c: 4413 add r3, r2 8018b0e: 1a18 subs r0, r3, r0 8018b10: b003 add sp, #12 8018b12: bdf0 pop {r4, r5, r6, r7, pc} 8018b14: f813 6b01 ldrb.w r6, [r3], #1 8018b18: f801 6f01 strb.w r6, [r1, #1]! 8018b1c: e7ed b.n 8018afa <__exponent+0x44> 8018b1e: 2330 movs r3, #48 @ 0x30 8018b20: 3130 adds r1, #48 @ 0x30 8018b22: 7083 strb r3, [r0, #2] 8018b24: 70c1 strb r1, [r0, #3] 8018b26: 1d03 adds r3, r0, #4 8018b28: e7f1 b.n 8018b0e <__exponent+0x58> ... 08018b2c <_printf_float>: 8018b2c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8018b30: b08d sub sp, #52 @ 0x34 8018b32: 460c mov r4, r1 8018b34: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58 8018b38: 4616 mov r6, r2 8018b3a: 461f mov r7, r3 8018b3c: 4605 mov r5, r0 8018b3e: f000 fff1 bl 8019b24 <_localeconv_r> 8018b42: 6803 ldr r3, [r0, #0] 8018b44: 9306 str r3, [sp, #24] 8018b46: 4618 mov r0, r3 8018b48: f7e7 fb6a bl 8000220 8018b4c: 2300 movs r3, #0 8018b4e: 930a str r3, [sp, #40] @ 0x28 8018b50: f8d8 3000 ldr.w r3, [r8] 8018b54: f894 a018 ldrb.w sl, [r4, #24] 8018b58: f8d4 b000 ldr.w fp, [r4] 8018b5c: 9007 str r0, [sp, #28] 8018b5e: 3307 adds r3, #7 8018b60: f023 0307 bic.w r3, r3, #7 8018b64: ecb3 7b02 vldmia r3!, {d7} 8018b68: ed8d 7b04 vstr d7, [sp, #16] 8018b6c: f8c8 3000 str.w r3, [r8] 8018b70: e9dd 8304 ldrd r8, r3, [sp, #16] 8018b74: f023 4900 bic.w r9, r3, #2147483648 @ 0x80000000 8018b78: ed84 7b12 vstr d7, [r4, #72] @ 0x48 8018b7c: 4b9c ldr r3, [pc, #624] @ (8018df0 <_printf_float+0x2c4>) 8018b7e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8018b82: 4640 mov r0, r8 8018b84: 4649 mov r1, r9 8018b86: f7e7 ffa9 bl 8000adc <__aeabi_dcmpun> 8018b8a: bb70 cbnz r0, 8018bea <_printf_float+0xbe> 8018b8c: 4b98 ldr r3, [pc, #608] @ (8018df0 <_printf_float+0x2c4>) 8018b8e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8018b92: 4640 mov r0, r8 8018b94: 4649 mov r1, r9 8018b96: f7e7 ff83 bl 8000aa0 <__aeabi_dcmple> 8018b9a: bb30 cbnz r0, 8018bea <_printf_float+0xbe> 8018b9c: e9dd 0104 ldrd r0, r1, [sp, #16] 8018ba0: 2200 movs r2, #0 8018ba2: 2300 movs r3, #0 8018ba4: f7e7 ff72 bl 8000a8c <__aeabi_dcmplt> 8018ba8: b110 cbz r0, 8018bb0 <_printf_float+0x84> 8018baa: 232d movs r3, #45 @ 0x2d 8018bac: f884 3043 strb.w r3, [r4, #67] @ 0x43 8018bb0: 4a90 ldr r2, [pc, #576] @ (8018df4 <_printf_float+0x2c8>) 8018bb2: 4b91 ldr r3, [pc, #580] @ (8018df8 <_printf_float+0x2cc>) 8018bb4: f1ba 0f47 cmp.w sl, #71 @ 0x47 8018bb8: bf8c ite hi 8018bba: 4690 movhi r8, r2 8018bbc: 4698 movls r8, r3 8018bbe: 2303 movs r3, #3 8018bc0: 6123 str r3, [r4, #16] 8018bc2: f02b 0304 bic.w r3, fp, #4 8018bc6: 6023 str r3, [r4, #0] 8018bc8: f04f 0900 mov.w r9, #0 8018bcc: 9700 str r7, [sp, #0] 8018bce: 4633 mov r3, r6 8018bd0: aa0b add r2, sp, #44 @ 0x2c 8018bd2: 4621 mov r1, r4 8018bd4: 4628 mov r0, r5 8018bd6: f000 f9d1 bl 8018f7c <_printf_common> 8018bda: 3001 adds r0, #1 8018bdc: f040 808c bne.w 8018cf8 <_printf_float+0x1cc> 8018be0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8018be4: b00d add sp, #52 @ 0x34 8018be6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8018bea: e9dd 2304 ldrd r2, r3, [sp, #16] 8018bee: 4610 mov r0, r2 8018bf0: 4619 mov r1, r3 8018bf2: f7e7 ff73 bl 8000adc <__aeabi_dcmpun> 8018bf6: b140 cbz r0, 8018c0a <_printf_float+0xde> 8018bf8: 9b05 ldr r3, [sp, #20] 8018bfa: 4a80 ldr r2, [pc, #512] @ (8018dfc <_printf_float+0x2d0>) 8018bfc: 2b00 cmp r3, #0 8018bfe: bfbc itt lt 8018c00: 232d movlt r3, #45 @ 0x2d 8018c02: f884 3043 strblt.w r3, [r4, #67] @ 0x43 8018c06: 4b7e ldr r3, [pc, #504] @ (8018e00 <_printf_float+0x2d4>) 8018c08: e7d4 b.n 8018bb4 <_printf_float+0x88> 8018c0a: 6863 ldr r3, [r4, #4] 8018c0c: 1c5a adds r2, r3, #1 8018c0e: f00a 09df and.w r9, sl, #223 @ 0xdf 8018c12: d13b bne.n 8018c8c <_printf_float+0x160> 8018c14: 2306 movs r3, #6 8018c16: 6063 str r3, [r4, #4] 8018c18: f44b 6280 orr.w r2, fp, #1024 @ 0x400 8018c1c: 2300 movs r3, #0 8018c1e: 6022 str r2, [r4, #0] 8018c20: 9303 str r3, [sp, #12] 8018c22: ab0a add r3, sp, #40 @ 0x28 8018c24: e9cd a301 strd sl, r3, [sp, #4] 8018c28: ab09 add r3, sp, #36 @ 0x24 8018c2a: 9300 str r3, [sp, #0] 8018c2c: 6861 ldr r1, [r4, #4] 8018c2e: ed9d 0b04 vldr d0, [sp, #16] 8018c32: f10d 0323 add.w r3, sp, #35 @ 0x23 8018c36: 4628 mov r0, r5 8018c38: f7ff fed8 bl 80189ec <__cvt> 8018c3c: f1b9 0f47 cmp.w r9, #71 @ 0x47 8018c40: 9909 ldr r1, [sp, #36] @ 0x24 8018c42: 4680 mov r8, r0 8018c44: d129 bne.n 8018c9a <_printf_float+0x16e> 8018c46: 1cc8 adds r0, r1, #3 8018c48: db02 blt.n 8018c50 <_printf_float+0x124> 8018c4a: 6863 ldr r3, [r4, #4] 8018c4c: 428b cmp r3, r1 8018c4e: da41 bge.n 8018cd4 <_printf_float+0x1a8> 8018c50: f1aa 0a02 sub.w sl, sl, #2 8018c54: fa5f fa8a uxtb.w sl, sl 8018c58: 3901 subs r1, #1 8018c5a: 4652 mov r2, sl 8018c5c: f104 0050 add.w r0, r4, #80 @ 0x50 8018c60: 9109 str r1, [sp, #36] @ 0x24 8018c62: f7ff ff28 bl 8018ab6 <__exponent> 8018c66: 9a0a ldr r2, [sp, #40] @ 0x28 8018c68: 1813 adds r3, r2, r0 8018c6a: 2a01 cmp r2, #1 8018c6c: 4681 mov r9, r0 8018c6e: 6123 str r3, [r4, #16] 8018c70: dc02 bgt.n 8018c78 <_printf_float+0x14c> 8018c72: 6822 ldr r2, [r4, #0] 8018c74: 07d2 lsls r2, r2, #31 8018c76: d501 bpl.n 8018c7c <_printf_float+0x150> 8018c78: 3301 adds r3, #1 8018c7a: 6123 str r3, [r4, #16] 8018c7c: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23 8018c80: 2b00 cmp r3, #0 8018c82: d0a3 beq.n 8018bcc <_printf_float+0xa0> 8018c84: 232d movs r3, #45 @ 0x2d 8018c86: f884 3043 strb.w r3, [r4, #67] @ 0x43 8018c8a: e79f b.n 8018bcc <_printf_float+0xa0> 8018c8c: f1b9 0f47 cmp.w r9, #71 @ 0x47 8018c90: d1c2 bne.n 8018c18 <_printf_float+0xec> 8018c92: 2b00 cmp r3, #0 8018c94: d1c0 bne.n 8018c18 <_printf_float+0xec> 8018c96: 2301 movs r3, #1 8018c98: e7bd b.n 8018c16 <_printf_float+0xea> 8018c9a: f1ba 0f65 cmp.w sl, #101 @ 0x65 8018c9e: d9db bls.n 8018c58 <_printf_float+0x12c> 8018ca0: f1ba 0f66 cmp.w sl, #102 @ 0x66 8018ca4: d118 bne.n 8018cd8 <_printf_float+0x1ac> 8018ca6: 2900 cmp r1, #0 8018ca8: 6863 ldr r3, [r4, #4] 8018caa: dd0b ble.n 8018cc4 <_printf_float+0x198> 8018cac: 6121 str r1, [r4, #16] 8018cae: b913 cbnz r3, 8018cb6 <_printf_float+0x18a> 8018cb0: 6822 ldr r2, [r4, #0] 8018cb2: 07d0 lsls r0, r2, #31 8018cb4: d502 bpl.n 8018cbc <_printf_float+0x190> 8018cb6: 3301 adds r3, #1 8018cb8: 440b add r3, r1 8018cba: 6123 str r3, [r4, #16] 8018cbc: 65a1 str r1, [r4, #88] @ 0x58 8018cbe: f04f 0900 mov.w r9, #0 8018cc2: e7db b.n 8018c7c <_printf_float+0x150> 8018cc4: b913 cbnz r3, 8018ccc <_printf_float+0x1a0> 8018cc6: 6822 ldr r2, [r4, #0] 8018cc8: 07d2 lsls r2, r2, #31 8018cca: d501 bpl.n 8018cd0 <_printf_float+0x1a4> 8018ccc: 3302 adds r3, #2 8018cce: e7f4 b.n 8018cba <_printf_float+0x18e> 8018cd0: 2301 movs r3, #1 8018cd2: e7f2 b.n 8018cba <_printf_float+0x18e> 8018cd4: f04f 0a67 mov.w sl, #103 @ 0x67 8018cd8: 9b0a ldr r3, [sp, #40] @ 0x28 8018cda: 428b cmp r3, r1 8018cdc: dc05 bgt.n 8018cea <_printf_float+0x1be> 8018cde: 6823 ldr r3, [r4, #0] 8018ce0: 6121 str r1, [r4, #16] 8018ce2: 07d8 lsls r0, r3, #31 8018ce4: d5ea bpl.n 8018cbc <_printf_float+0x190> 8018ce6: 1c4b adds r3, r1, #1 8018ce8: e7e7 b.n 8018cba <_printf_float+0x18e> 8018cea: 2900 cmp r1, #0 8018cec: bfd4 ite le 8018cee: f1c1 0202 rsble r2, r1, #2 8018cf2: 2201 movgt r2, #1 8018cf4: 4413 add r3, r2 8018cf6: e7e0 b.n 8018cba <_printf_float+0x18e> 8018cf8: 6823 ldr r3, [r4, #0] 8018cfa: 055a lsls r2, r3, #21 8018cfc: d407 bmi.n 8018d0e <_printf_float+0x1e2> 8018cfe: 6923 ldr r3, [r4, #16] 8018d00: 4642 mov r2, r8 8018d02: 4631 mov r1, r6 8018d04: 4628 mov r0, r5 8018d06: 47b8 blx r7 8018d08: 3001 adds r0, #1 8018d0a: d12b bne.n 8018d64 <_printf_float+0x238> 8018d0c: e768 b.n 8018be0 <_printf_float+0xb4> 8018d0e: f1ba 0f65 cmp.w sl, #101 @ 0x65 8018d12: f240 80dd bls.w 8018ed0 <_printf_float+0x3a4> 8018d16: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8018d1a: 2200 movs r2, #0 8018d1c: 2300 movs r3, #0 8018d1e: f7e7 feab bl 8000a78 <__aeabi_dcmpeq> 8018d22: 2800 cmp r0, #0 8018d24: d033 beq.n 8018d8e <_printf_float+0x262> 8018d26: 4a37 ldr r2, [pc, #220] @ (8018e04 <_printf_float+0x2d8>) 8018d28: 2301 movs r3, #1 8018d2a: 4631 mov r1, r6 8018d2c: 4628 mov r0, r5 8018d2e: 47b8 blx r7 8018d30: 3001 adds r0, #1 8018d32: f43f af55 beq.w 8018be0 <_printf_float+0xb4> 8018d36: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24 8018d3a: 4543 cmp r3, r8 8018d3c: db02 blt.n 8018d44 <_printf_float+0x218> 8018d3e: 6823 ldr r3, [r4, #0] 8018d40: 07d8 lsls r0, r3, #31 8018d42: d50f bpl.n 8018d64 <_printf_float+0x238> 8018d44: e9dd 2306 ldrd r2, r3, [sp, #24] 8018d48: 4631 mov r1, r6 8018d4a: 4628 mov r0, r5 8018d4c: 47b8 blx r7 8018d4e: 3001 adds r0, #1 8018d50: f43f af46 beq.w 8018be0 <_printf_float+0xb4> 8018d54: f04f 0900 mov.w r9, #0 8018d58: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8018d5c: f104 0a1a add.w sl, r4, #26 8018d60: 45c8 cmp r8, r9 8018d62: dc09 bgt.n 8018d78 <_printf_float+0x24c> 8018d64: 6823 ldr r3, [r4, #0] 8018d66: 079b lsls r3, r3, #30 8018d68: f100 8103 bmi.w 8018f72 <_printf_float+0x446> 8018d6c: 68e0 ldr r0, [r4, #12] 8018d6e: 9b0b ldr r3, [sp, #44] @ 0x2c 8018d70: 4298 cmp r0, r3 8018d72: bfb8 it lt 8018d74: 4618 movlt r0, r3 8018d76: e735 b.n 8018be4 <_printf_float+0xb8> 8018d78: 2301 movs r3, #1 8018d7a: 4652 mov r2, sl 8018d7c: 4631 mov r1, r6 8018d7e: 4628 mov r0, r5 8018d80: 47b8 blx r7 8018d82: 3001 adds r0, #1 8018d84: f43f af2c beq.w 8018be0 <_printf_float+0xb4> 8018d88: f109 0901 add.w r9, r9, #1 8018d8c: e7e8 b.n 8018d60 <_printf_float+0x234> 8018d8e: 9b09 ldr r3, [sp, #36] @ 0x24 8018d90: 2b00 cmp r3, #0 8018d92: dc39 bgt.n 8018e08 <_printf_float+0x2dc> 8018d94: 4a1b ldr r2, [pc, #108] @ (8018e04 <_printf_float+0x2d8>) 8018d96: 2301 movs r3, #1 8018d98: 4631 mov r1, r6 8018d9a: 4628 mov r0, r5 8018d9c: 47b8 blx r7 8018d9e: 3001 adds r0, #1 8018da0: f43f af1e beq.w 8018be0 <_printf_float+0xb4> 8018da4: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24 8018da8: ea59 0303 orrs.w r3, r9, r3 8018dac: d102 bne.n 8018db4 <_printf_float+0x288> 8018dae: 6823 ldr r3, [r4, #0] 8018db0: 07d9 lsls r1, r3, #31 8018db2: d5d7 bpl.n 8018d64 <_printf_float+0x238> 8018db4: e9dd 2306 ldrd r2, r3, [sp, #24] 8018db8: 4631 mov r1, r6 8018dba: 4628 mov r0, r5 8018dbc: 47b8 blx r7 8018dbe: 3001 adds r0, #1 8018dc0: f43f af0e beq.w 8018be0 <_printf_float+0xb4> 8018dc4: f04f 0a00 mov.w sl, #0 8018dc8: f104 0b1a add.w fp, r4, #26 8018dcc: 9b09 ldr r3, [sp, #36] @ 0x24 8018dce: 425b negs r3, r3 8018dd0: 4553 cmp r3, sl 8018dd2: dc01 bgt.n 8018dd8 <_printf_float+0x2ac> 8018dd4: 464b mov r3, r9 8018dd6: e793 b.n 8018d00 <_printf_float+0x1d4> 8018dd8: 2301 movs r3, #1 8018dda: 465a mov r2, fp 8018ddc: 4631 mov r1, r6 8018dde: 4628 mov r0, r5 8018de0: 47b8 blx r7 8018de2: 3001 adds r0, #1 8018de4: f43f aefc beq.w 8018be0 <_printf_float+0xb4> 8018de8: f10a 0a01 add.w sl, sl, #1 8018dec: e7ee b.n 8018dcc <_printf_float+0x2a0> 8018dee: bf00 nop 8018df0: 7fefffff .word 0x7fefffff 8018df4: 0801dcb4 .word 0x0801dcb4 8018df8: 0801dcb0 .word 0x0801dcb0 8018dfc: 0801dcbc .word 0x0801dcbc 8018e00: 0801dcb8 .word 0x0801dcb8 8018e04: 0801dcc0 .word 0x0801dcc0 8018e08: 6da3 ldr r3, [r4, #88] @ 0x58 8018e0a: f8dd a028 ldr.w sl, [sp, #40] @ 0x28 8018e0e: 4553 cmp r3, sl 8018e10: bfa8 it ge 8018e12: 4653 movge r3, sl 8018e14: 2b00 cmp r3, #0 8018e16: 4699 mov r9, r3 8018e18: dc36 bgt.n 8018e88 <_printf_float+0x35c> 8018e1a: f04f 0b00 mov.w fp, #0 8018e1e: ea29 79e9 bic.w r9, r9, r9, asr #31 8018e22: f104 021a add.w r2, r4, #26 8018e26: 6da3 ldr r3, [r4, #88] @ 0x58 8018e28: 9304 str r3, [sp, #16] 8018e2a: eba3 0309 sub.w r3, r3, r9 8018e2e: 455b cmp r3, fp 8018e30: dc31 bgt.n 8018e96 <_printf_float+0x36a> 8018e32: 9b09 ldr r3, [sp, #36] @ 0x24 8018e34: 459a cmp sl, r3 8018e36: dc3a bgt.n 8018eae <_printf_float+0x382> 8018e38: 6823 ldr r3, [r4, #0] 8018e3a: 07da lsls r2, r3, #31 8018e3c: d437 bmi.n 8018eae <_printf_float+0x382> 8018e3e: 9b09 ldr r3, [sp, #36] @ 0x24 8018e40: ebaa 0903 sub.w r9, sl, r3 8018e44: 9b04 ldr r3, [sp, #16] 8018e46: ebaa 0303 sub.w r3, sl, r3 8018e4a: 4599 cmp r9, r3 8018e4c: bfa8 it ge 8018e4e: 4699 movge r9, r3 8018e50: f1b9 0f00 cmp.w r9, #0 8018e54: dc33 bgt.n 8018ebe <_printf_float+0x392> 8018e56: f04f 0800 mov.w r8, #0 8018e5a: ea29 79e9 bic.w r9, r9, r9, asr #31 8018e5e: f104 0b1a add.w fp, r4, #26 8018e62: 9b09 ldr r3, [sp, #36] @ 0x24 8018e64: ebaa 0303 sub.w r3, sl, r3 8018e68: eba3 0309 sub.w r3, r3, r9 8018e6c: 4543 cmp r3, r8 8018e6e: f77f af79 ble.w 8018d64 <_printf_float+0x238> 8018e72: 2301 movs r3, #1 8018e74: 465a mov r2, fp 8018e76: 4631 mov r1, r6 8018e78: 4628 mov r0, r5 8018e7a: 47b8 blx r7 8018e7c: 3001 adds r0, #1 8018e7e: f43f aeaf beq.w 8018be0 <_printf_float+0xb4> 8018e82: f108 0801 add.w r8, r8, #1 8018e86: e7ec b.n 8018e62 <_printf_float+0x336> 8018e88: 4642 mov r2, r8 8018e8a: 4631 mov r1, r6 8018e8c: 4628 mov r0, r5 8018e8e: 47b8 blx r7 8018e90: 3001 adds r0, #1 8018e92: d1c2 bne.n 8018e1a <_printf_float+0x2ee> 8018e94: e6a4 b.n 8018be0 <_printf_float+0xb4> 8018e96: 2301 movs r3, #1 8018e98: 4631 mov r1, r6 8018e9a: 4628 mov r0, r5 8018e9c: 9204 str r2, [sp, #16] 8018e9e: 47b8 blx r7 8018ea0: 3001 adds r0, #1 8018ea2: f43f ae9d beq.w 8018be0 <_printf_float+0xb4> 8018ea6: 9a04 ldr r2, [sp, #16] 8018ea8: f10b 0b01 add.w fp, fp, #1 8018eac: e7bb b.n 8018e26 <_printf_float+0x2fa> 8018eae: e9dd 2306 ldrd r2, r3, [sp, #24] 8018eb2: 4631 mov r1, r6 8018eb4: 4628 mov r0, r5 8018eb6: 47b8 blx r7 8018eb8: 3001 adds r0, #1 8018eba: d1c0 bne.n 8018e3e <_printf_float+0x312> 8018ebc: e690 b.n 8018be0 <_printf_float+0xb4> 8018ebe: 9a04 ldr r2, [sp, #16] 8018ec0: 464b mov r3, r9 8018ec2: 4442 add r2, r8 8018ec4: 4631 mov r1, r6 8018ec6: 4628 mov r0, r5 8018ec8: 47b8 blx r7 8018eca: 3001 adds r0, #1 8018ecc: d1c3 bne.n 8018e56 <_printf_float+0x32a> 8018ece: e687 b.n 8018be0 <_printf_float+0xb4> 8018ed0: f8dd a028 ldr.w sl, [sp, #40] @ 0x28 8018ed4: f1ba 0f01 cmp.w sl, #1 8018ed8: dc01 bgt.n 8018ede <_printf_float+0x3b2> 8018eda: 07db lsls r3, r3, #31 8018edc: d536 bpl.n 8018f4c <_printf_float+0x420> 8018ede: 2301 movs r3, #1 8018ee0: 4642 mov r2, r8 8018ee2: 4631 mov r1, r6 8018ee4: 4628 mov r0, r5 8018ee6: 47b8 blx r7 8018ee8: 3001 adds r0, #1 8018eea: f43f ae79 beq.w 8018be0 <_printf_float+0xb4> 8018eee: e9dd 2306 ldrd r2, r3, [sp, #24] 8018ef2: 4631 mov r1, r6 8018ef4: 4628 mov r0, r5 8018ef6: 47b8 blx r7 8018ef8: 3001 adds r0, #1 8018efa: f43f ae71 beq.w 8018be0 <_printf_float+0xb4> 8018efe: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 8018f02: 2200 movs r2, #0 8018f04: 2300 movs r3, #0 8018f06: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 8018f0a: f7e7 fdb5 bl 8000a78 <__aeabi_dcmpeq> 8018f0e: b9c0 cbnz r0, 8018f42 <_printf_float+0x416> 8018f10: 4653 mov r3, sl 8018f12: f108 0201 add.w r2, r8, #1 8018f16: 4631 mov r1, r6 8018f18: 4628 mov r0, r5 8018f1a: 47b8 blx r7 8018f1c: 3001 adds r0, #1 8018f1e: d10c bne.n 8018f3a <_printf_float+0x40e> 8018f20: e65e b.n 8018be0 <_printf_float+0xb4> 8018f22: 2301 movs r3, #1 8018f24: 465a mov r2, fp 8018f26: 4631 mov r1, r6 8018f28: 4628 mov r0, r5 8018f2a: 47b8 blx r7 8018f2c: 3001 adds r0, #1 8018f2e: f43f ae57 beq.w 8018be0 <_printf_float+0xb4> 8018f32: f108 0801 add.w r8, r8, #1 8018f36: 45d0 cmp r8, sl 8018f38: dbf3 blt.n 8018f22 <_printf_float+0x3f6> 8018f3a: 464b mov r3, r9 8018f3c: f104 0250 add.w r2, r4, #80 @ 0x50 8018f40: e6df b.n 8018d02 <_printf_float+0x1d6> 8018f42: f04f 0800 mov.w r8, #0 8018f46: f104 0b1a add.w fp, r4, #26 8018f4a: e7f4 b.n 8018f36 <_printf_float+0x40a> 8018f4c: 2301 movs r3, #1 8018f4e: 4642 mov r2, r8 8018f50: e7e1 b.n 8018f16 <_printf_float+0x3ea> 8018f52: 2301 movs r3, #1 8018f54: 464a mov r2, r9 8018f56: 4631 mov r1, r6 8018f58: 4628 mov r0, r5 8018f5a: 47b8 blx r7 8018f5c: 3001 adds r0, #1 8018f5e: f43f ae3f beq.w 8018be0 <_printf_float+0xb4> 8018f62: f108 0801 add.w r8, r8, #1 8018f66: 68e3 ldr r3, [r4, #12] 8018f68: 990b ldr r1, [sp, #44] @ 0x2c 8018f6a: 1a5b subs r3, r3, r1 8018f6c: 4543 cmp r3, r8 8018f6e: dcf0 bgt.n 8018f52 <_printf_float+0x426> 8018f70: e6fc b.n 8018d6c <_printf_float+0x240> 8018f72: f04f 0800 mov.w r8, #0 8018f76: f104 0919 add.w r9, r4, #25 8018f7a: e7f4 b.n 8018f66 <_printf_float+0x43a> 08018f7c <_printf_common>: 8018f7c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8018f80: 4616 mov r6, r2 8018f82: 4698 mov r8, r3 8018f84: 688a ldr r2, [r1, #8] 8018f86: 690b ldr r3, [r1, #16] 8018f88: f8dd 9020 ldr.w r9, [sp, #32] 8018f8c: 4293 cmp r3, r2 8018f8e: bfb8 it lt 8018f90: 4613 movlt r3, r2 8018f92: 6033 str r3, [r6, #0] 8018f94: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8018f98: 4607 mov r7, r0 8018f9a: 460c mov r4, r1 8018f9c: b10a cbz r2, 8018fa2 <_printf_common+0x26> 8018f9e: 3301 adds r3, #1 8018fa0: 6033 str r3, [r6, #0] 8018fa2: 6823 ldr r3, [r4, #0] 8018fa4: 0699 lsls r1, r3, #26 8018fa6: bf42 ittt mi 8018fa8: 6833 ldrmi r3, [r6, #0] 8018faa: 3302 addmi r3, #2 8018fac: 6033 strmi r3, [r6, #0] 8018fae: 6825 ldr r5, [r4, #0] 8018fb0: f015 0506 ands.w r5, r5, #6 8018fb4: d106 bne.n 8018fc4 <_printf_common+0x48> 8018fb6: f104 0a19 add.w sl, r4, #25 8018fba: 68e3 ldr r3, [r4, #12] 8018fbc: 6832 ldr r2, [r6, #0] 8018fbe: 1a9b subs r3, r3, r2 8018fc0: 42ab cmp r3, r5 8018fc2: dc26 bgt.n 8019012 <_printf_common+0x96> 8018fc4: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8018fc8: 6822 ldr r2, [r4, #0] 8018fca: 3b00 subs r3, #0 8018fcc: bf18 it ne 8018fce: 2301 movne r3, #1 8018fd0: 0692 lsls r2, r2, #26 8018fd2: d42b bmi.n 801902c <_printf_common+0xb0> 8018fd4: f104 0243 add.w r2, r4, #67 @ 0x43 8018fd8: 4641 mov r1, r8 8018fda: 4638 mov r0, r7 8018fdc: 47c8 blx r9 8018fde: 3001 adds r0, #1 8018fe0: d01e beq.n 8019020 <_printf_common+0xa4> 8018fe2: 6823 ldr r3, [r4, #0] 8018fe4: 6922 ldr r2, [r4, #16] 8018fe6: f003 0306 and.w r3, r3, #6 8018fea: 2b04 cmp r3, #4 8018fec: bf02 ittt eq 8018fee: 68e5 ldreq r5, [r4, #12] 8018ff0: 6833 ldreq r3, [r6, #0] 8018ff2: 1aed subeq r5, r5, r3 8018ff4: 68a3 ldr r3, [r4, #8] 8018ff6: bf0c ite eq 8018ff8: ea25 75e5 biceq.w r5, r5, r5, asr #31 8018ffc: 2500 movne r5, #0 8018ffe: 4293 cmp r3, r2 8019000: bfc4 itt gt 8019002: 1a9b subgt r3, r3, r2 8019004: 18ed addgt r5, r5, r3 8019006: 2600 movs r6, #0 8019008: 341a adds r4, #26 801900a: 42b5 cmp r5, r6 801900c: d11a bne.n 8019044 <_printf_common+0xc8> 801900e: 2000 movs r0, #0 8019010: e008 b.n 8019024 <_printf_common+0xa8> 8019012: 2301 movs r3, #1 8019014: 4652 mov r2, sl 8019016: 4641 mov r1, r8 8019018: 4638 mov r0, r7 801901a: 47c8 blx r9 801901c: 3001 adds r0, #1 801901e: d103 bne.n 8019028 <_printf_common+0xac> 8019020: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8019024: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8019028: 3501 adds r5, #1 801902a: e7c6 b.n 8018fba <_printf_common+0x3e> 801902c: 18e1 adds r1, r4, r3 801902e: 1c5a adds r2, r3, #1 8019030: 2030 movs r0, #48 @ 0x30 8019032: f881 0043 strb.w r0, [r1, #67] @ 0x43 8019036: 4422 add r2, r4 8019038: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 801903c: f882 1043 strb.w r1, [r2, #67] @ 0x43 8019040: 3302 adds r3, #2 8019042: e7c7 b.n 8018fd4 <_printf_common+0x58> 8019044: 2301 movs r3, #1 8019046: 4622 mov r2, r4 8019048: 4641 mov r1, r8 801904a: 4638 mov r0, r7 801904c: 47c8 blx r9 801904e: 3001 adds r0, #1 8019050: d0e6 beq.n 8019020 <_printf_common+0xa4> 8019052: 3601 adds r6, #1 8019054: e7d9 b.n 801900a <_printf_common+0x8e> ... 08019058 <_printf_i>: 8019058: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 801905c: 7e0d ldrb r5, [r1, #24] 801905e: b085 sub sp, #20 8019060: 2d78 cmp r5, #120 @ 0x78 8019062: 4690 mov r8, r2 8019064: 9e0c ldr r6, [sp, #48] @ 0x30 8019066: 4607 mov r7, r0 8019068: 460c mov r4, r1 801906a: 4699 mov r9, r3 801906c: f101 0243 add.w r2, r1, #67 @ 0x43 8019070: d807 bhi.n 8019082 <_printf_i+0x2a> 8019072: 2d62 cmp r5, #98 @ 0x62 8019074: d80a bhi.n 801908c <_printf_i+0x34> 8019076: 2d00 cmp r5, #0 8019078: f000 80d7 beq.w 801922a <_printf_i+0x1d2> 801907c: 2d58 cmp r5, #88 @ 0x58 801907e: f000 80bc beq.w 80191fa <_printf_i+0x1a2> 8019082: f104 0642 add.w r6, r4, #66 @ 0x42 8019086: f884 5042 strb.w r5, [r4, #66] @ 0x42 801908a: e03b b.n 8019104 <_printf_i+0xac> 801908c: f1a5 0363 sub.w r3, r5, #99 @ 0x63 8019090: 2b15 cmp r3, #21 8019092: d8f6 bhi.n 8019082 <_printf_i+0x2a> 8019094: a101 add r1, pc, #4 @ (adr r1, 801909c <_printf_i+0x44>) 8019096: f851 f023 ldr.w pc, [r1, r3, lsl #2] 801909a: bf00 nop 801909c: 080190f5 .word 0x080190f5 80190a0: 08019109 .word 0x08019109 80190a4: 08019083 .word 0x08019083 80190a8: 08019083 .word 0x08019083 80190ac: 08019083 .word 0x08019083 80190b0: 08019083 .word 0x08019083 80190b4: 08019109 .word 0x08019109 80190b8: 08019083 .word 0x08019083 80190bc: 08019083 .word 0x08019083 80190c0: 08019083 .word 0x08019083 80190c4: 08019083 .word 0x08019083 80190c8: 08019211 .word 0x08019211 80190cc: 08019133 .word 0x08019133 80190d0: 080191c3 .word 0x080191c3 80190d4: 08019083 .word 0x08019083 80190d8: 08019083 .word 0x08019083 80190dc: 08019233 .word 0x08019233 80190e0: 08019083 .word 0x08019083 80190e4: 08019133 .word 0x08019133 80190e8: 08019083 .word 0x08019083 80190ec: 08019083 .word 0x08019083 80190f0: 080191cb .word 0x080191cb 80190f4: 6833 ldr r3, [r6, #0] 80190f6: 1d1a adds r2, r3, #4 80190f8: 681b ldr r3, [r3, #0] 80190fa: 6032 str r2, [r6, #0] 80190fc: f104 0642 add.w r6, r4, #66 @ 0x42 8019100: f884 3042 strb.w r3, [r4, #66] @ 0x42 8019104: 2301 movs r3, #1 8019106: e0a1 b.n 801924c <_printf_i+0x1f4> 8019108: 6833 ldr r3, [r6, #0] 801910a: 6820 ldr r0, [r4, #0] 801910c: 1d19 adds r1, r3, #4 801910e: 6031 str r1, [r6, #0] 8019110: 0606 lsls r6, r0, #24 8019112: d501 bpl.n 8019118 <_printf_i+0xc0> 8019114: 681d ldr r5, [r3, #0] 8019116: e003 b.n 8019120 <_printf_i+0xc8> 8019118: 0645 lsls r5, r0, #25 801911a: d5fb bpl.n 8019114 <_printf_i+0xbc> 801911c: f9b3 5000 ldrsh.w r5, [r3] 8019120: 2d00 cmp r5, #0 8019122: da03 bge.n 801912c <_printf_i+0xd4> 8019124: 232d movs r3, #45 @ 0x2d 8019126: 426d negs r5, r5 8019128: f884 3043 strb.w r3, [r4, #67] @ 0x43 801912c: 485b ldr r0, [pc, #364] @ (801929c <_printf_i+0x244>) 801912e: 230a movs r3, #10 8019130: e011 b.n 8019156 <_printf_i+0xfe> 8019132: 6821 ldr r1, [r4, #0] 8019134: 6833 ldr r3, [r6, #0] 8019136: 0608 lsls r0, r1, #24 8019138: f853 5b04 ldr.w r5, [r3], #4 801913c: d402 bmi.n 8019144 <_printf_i+0xec> 801913e: 0649 lsls r1, r1, #25 8019140: bf48 it mi 8019142: b2ad uxthmi r5, r5 8019144: 6033 str r3, [r6, #0] 8019146: 7e23 ldrb r3, [r4, #24] 8019148: 4854 ldr r0, [pc, #336] @ (801929c <_printf_i+0x244>) 801914a: 2b6f cmp r3, #111 @ 0x6f 801914c: d15c bne.n 8019208 <_printf_i+0x1b0> 801914e: 2308 movs r3, #8 8019150: 2100 movs r1, #0 8019152: f884 1043 strb.w r1, [r4, #67] @ 0x43 8019156: 6866 ldr r6, [r4, #4] 8019158: 60a6 str r6, [r4, #8] 801915a: 2e00 cmp r6, #0 801915c: db05 blt.n 801916a <_printf_i+0x112> 801915e: 6821 ldr r1, [r4, #0] 8019160: 432e orrs r6, r5 8019162: f021 0104 bic.w r1, r1, #4 8019166: 6021 str r1, [r4, #0] 8019168: d050 beq.n 801920c <_printf_i+0x1b4> 801916a: 4616 mov r6, r2 801916c: fbb5 f1f3 udiv r1, r5, r3 8019170: fb03 5c11 mls ip, r3, r1, r5 8019174: f810 c00c ldrb.w ip, [r0, ip] 8019178: f806 cd01 strb.w ip, [r6, #-1]! 801917c: 46ac mov ip, r5 801917e: 4563 cmp r3, ip 8019180: 460d mov r5, r1 8019182: d9f3 bls.n 801916c <_printf_i+0x114> 8019184: 2b08 cmp r3, #8 8019186: d10b bne.n 80191a0 <_printf_i+0x148> 8019188: 6823 ldr r3, [r4, #0] 801918a: 07db lsls r3, r3, #31 801918c: d508 bpl.n 80191a0 <_printf_i+0x148> 801918e: 6923 ldr r3, [r4, #16] 8019190: 6861 ldr r1, [r4, #4] 8019192: 4299 cmp r1, r3 8019194: bfde ittt le 8019196: 2330 movle r3, #48 @ 0x30 8019198: f806 3c01 strble.w r3, [r6, #-1] 801919c: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 80191a0: 1b92 subs r2, r2, r6 80191a2: 6122 str r2, [r4, #16] 80191a4: f8cd 9000 str.w r9, [sp] 80191a8: 4643 mov r3, r8 80191aa: aa03 add r2, sp, #12 80191ac: 4621 mov r1, r4 80191ae: 4638 mov r0, r7 80191b0: f7ff fee4 bl 8018f7c <_printf_common> 80191b4: 3001 adds r0, #1 80191b6: d14e bne.n 8019256 <_printf_i+0x1fe> 80191b8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80191bc: b005 add sp, #20 80191be: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 80191c2: 6823 ldr r3, [r4, #0] 80191c4: f043 0320 orr.w r3, r3, #32 80191c8: 6023 str r3, [r4, #0] 80191ca: 4835 ldr r0, [pc, #212] @ (80192a0 <_printf_i+0x248>) 80191cc: 2578 movs r5, #120 @ 0x78 80191ce: f884 5045 strb.w r5, [r4, #69] @ 0x45 80191d2: 6823 ldr r3, [r4, #0] 80191d4: 6831 ldr r1, [r6, #0] 80191d6: f013 0f80 tst.w r3, #128 @ 0x80 80191da: f851 5b04 ldr.w r5, [r1], #4 80191de: d103 bne.n 80191e8 <_printf_i+0x190> 80191e0: f013 0f40 tst.w r3, #64 @ 0x40 80191e4: bf18 it ne 80191e6: b2ad uxthne r5, r5 80191e8: 6031 str r1, [r6, #0] 80191ea: 07d9 lsls r1, r3, #31 80191ec: bf44 itt mi 80191ee: f043 0320 orrmi.w r3, r3, #32 80191f2: 6023 strmi r3, [r4, #0] 80191f4: b11d cbz r5, 80191fe <_printf_i+0x1a6> 80191f6: 2310 movs r3, #16 80191f8: e7aa b.n 8019150 <_printf_i+0xf8> 80191fa: 4828 ldr r0, [pc, #160] @ (801929c <_printf_i+0x244>) 80191fc: e7e7 b.n 80191ce <_printf_i+0x176> 80191fe: 6823 ldr r3, [r4, #0] 8019200: f023 0320 bic.w r3, r3, #32 8019204: 6023 str r3, [r4, #0] 8019206: e7f6 b.n 80191f6 <_printf_i+0x19e> 8019208: 230a movs r3, #10 801920a: e7a1 b.n 8019150 <_printf_i+0xf8> 801920c: 4616 mov r6, r2 801920e: e7b9 b.n 8019184 <_printf_i+0x12c> 8019210: 6833 ldr r3, [r6, #0] 8019212: 6825 ldr r5, [r4, #0] 8019214: 6961 ldr r1, [r4, #20] 8019216: 1d18 adds r0, r3, #4 8019218: 6030 str r0, [r6, #0] 801921a: 062e lsls r6, r5, #24 801921c: 681b ldr r3, [r3, #0] 801921e: d501 bpl.n 8019224 <_printf_i+0x1cc> 8019220: 6019 str r1, [r3, #0] 8019222: e002 b.n 801922a <_printf_i+0x1d2> 8019224: 0668 lsls r0, r5, #25 8019226: d5fb bpl.n 8019220 <_printf_i+0x1c8> 8019228: 8019 strh r1, [r3, #0] 801922a: 2300 movs r3, #0 801922c: 6123 str r3, [r4, #16] 801922e: 4616 mov r6, r2 8019230: e7b8 b.n 80191a4 <_printf_i+0x14c> 8019232: 6833 ldr r3, [r6, #0] 8019234: 1d1a adds r2, r3, #4 8019236: 6032 str r2, [r6, #0] 8019238: 681e ldr r6, [r3, #0] 801923a: 6862 ldr r2, [r4, #4] 801923c: 2100 movs r1, #0 801923e: 4630 mov r0, r6 8019240: f7e6 ff9e bl 8000180 8019244: b108 cbz r0, 801924a <_printf_i+0x1f2> 8019246: 1b80 subs r0, r0, r6 8019248: 6060 str r0, [r4, #4] 801924a: 6863 ldr r3, [r4, #4] 801924c: 6123 str r3, [r4, #16] 801924e: 2300 movs r3, #0 8019250: f884 3043 strb.w r3, [r4, #67] @ 0x43 8019254: e7a6 b.n 80191a4 <_printf_i+0x14c> 8019256: 6923 ldr r3, [r4, #16] 8019258: 4632 mov r2, r6 801925a: 4641 mov r1, r8 801925c: 4638 mov r0, r7 801925e: 47c8 blx r9 8019260: 3001 adds r0, #1 8019262: d0a9 beq.n 80191b8 <_printf_i+0x160> 8019264: 6823 ldr r3, [r4, #0] 8019266: 079b lsls r3, r3, #30 8019268: d413 bmi.n 8019292 <_printf_i+0x23a> 801926a: 68e0 ldr r0, [r4, #12] 801926c: 9b03 ldr r3, [sp, #12] 801926e: 4298 cmp r0, r3 8019270: bfb8 it lt 8019272: 4618 movlt r0, r3 8019274: e7a2 b.n 80191bc <_printf_i+0x164> 8019276: 2301 movs r3, #1 8019278: 4632 mov r2, r6 801927a: 4641 mov r1, r8 801927c: 4638 mov r0, r7 801927e: 47c8 blx r9 8019280: 3001 adds r0, #1 8019282: d099 beq.n 80191b8 <_printf_i+0x160> 8019284: 3501 adds r5, #1 8019286: 68e3 ldr r3, [r4, #12] 8019288: 9903 ldr r1, [sp, #12] 801928a: 1a5b subs r3, r3, r1 801928c: 42ab cmp r3, r5 801928e: dcf2 bgt.n 8019276 <_printf_i+0x21e> 8019290: e7eb b.n 801926a <_printf_i+0x212> 8019292: 2500 movs r5, #0 8019294: f104 0619 add.w r6, r4, #25 8019298: e7f5 b.n 8019286 <_printf_i+0x22e> 801929a: bf00 nop 801929c: 0801dcc2 .word 0x0801dcc2 80192a0: 0801dcd3 .word 0x0801dcd3 080192a4 <_scanf_float>: 80192a4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80192a8: b087 sub sp, #28 80192aa: 4691 mov r9, r2 80192ac: 9303 str r3, [sp, #12] 80192ae: 688b ldr r3, [r1, #8] 80192b0: 1e5a subs r2, r3, #1 80192b2: f5b2 7fae cmp.w r2, #348 @ 0x15c 80192b6: bf81 itttt hi 80192b8: f46f 75ae mvnhi.w r5, #348 @ 0x15c 80192bc: eb03 0b05 addhi.w fp, r3, r5 80192c0: f240 135d movwhi r3, #349 @ 0x15d 80192c4: 608b strhi r3, [r1, #8] 80192c6: 680b ldr r3, [r1, #0] 80192c8: 460a mov r2, r1 80192ca: f04f 0500 mov.w r5, #0 80192ce: f443 63f0 orr.w r3, r3, #1920 @ 0x780 80192d2: f842 3b1c str.w r3, [r2], #28 80192d6: e9cd 5504 strd r5, r5, [sp, #16] 80192da: 4680 mov r8, r0 80192dc: 460c mov r4, r1 80192de: bf98 it ls 80192e0: f04f 0b00 movls.w fp, #0 80192e4: 9201 str r2, [sp, #4] 80192e6: 4616 mov r6, r2 80192e8: 46aa mov sl, r5 80192ea: 462f mov r7, r5 80192ec: 9502 str r5, [sp, #8] 80192ee: 68a2 ldr r2, [r4, #8] 80192f0: b15a cbz r2, 801930a <_scanf_float+0x66> 80192f2: f8d9 3000 ldr.w r3, [r9] 80192f6: 781b ldrb r3, [r3, #0] 80192f8: 2b4e cmp r3, #78 @ 0x4e 80192fa: d863 bhi.n 80193c4 <_scanf_float+0x120> 80192fc: 2b40 cmp r3, #64 @ 0x40 80192fe: d83b bhi.n 8019378 <_scanf_float+0xd4> 8019300: f1a3 012b sub.w r1, r3, #43 @ 0x2b 8019304: b2c8 uxtb r0, r1 8019306: 280e cmp r0, #14 8019308: d939 bls.n 801937e <_scanf_float+0xda> 801930a: b11f cbz r7, 8019314 <_scanf_float+0x70> 801930c: 6823 ldr r3, [r4, #0] 801930e: f423 7380 bic.w r3, r3, #256 @ 0x100 8019312: 6023 str r3, [r4, #0] 8019314: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 8019318: f1ba 0f01 cmp.w sl, #1 801931c: f200 8114 bhi.w 8019548 <_scanf_float+0x2a4> 8019320: 9b01 ldr r3, [sp, #4] 8019322: 429e cmp r6, r3 8019324: f200 8105 bhi.w 8019532 <_scanf_float+0x28e> 8019328: 2001 movs r0, #1 801932a: b007 add sp, #28 801932c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8019330: f1a3 0261 sub.w r2, r3, #97 @ 0x61 8019334: 2a0d cmp r2, #13 8019336: d8e8 bhi.n 801930a <_scanf_float+0x66> 8019338: a101 add r1, pc, #4 @ (adr r1, 8019340 <_scanf_float+0x9c>) 801933a: f851 f022 ldr.w pc, [r1, r2, lsl #2] 801933e: bf00 nop 8019340: 08019489 .word 0x08019489 8019344: 0801930b .word 0x0801930b 8019348: 0801930b .word 0x0801930b 801934c: 0801930b .word 0x0801930b 8019350: 080194e5 .word 0x080194e5 8019354: 080194bf .word 0x080194bf 8019358: 0801930b .word 0x0801930b 801935c: 0801930b .word 0x0801930b 8019360: 08019497 .word 0x08019497 8019364: 0801930b .word 0x0801930b 8019368: 0801930b .word 0x0801930b 801936c: 0801930b .word 0x0801930b 8019370: 0801930b .word 0x0801930b 8019374: 08019453 .word 0x08019453 8019378: f1a3 0241 sub.w r2, r3, #65 @ 0x41 801937c: e7da b.n 8019334 <_scanf_float+0x90> 801937e: 290e cmp r1, #14 8019380: d8c3 bhi.n 801930a <_scanf_float+0x66> 8019382: a001 add r0, pc, #4 @ (adr r0, 8019388 <_scanf_float+0xe4>) 8019384: f850 f021 ldr.w pc, [r0, r1, lsl #2] 8019388: 08019443 .word 0x08019443 801938c: 0801930b .word 0x0801930b 8019390: 08019443 .word 0x08019443 8019394: 080194d3 .word 0x080194d3 8019398: 0801930b .word 0x0801930b 801939c: 080193e5 .word 0x080193e5 80193a0: 08019429 .word 0x08019429 80193a4: 08019429 .word 0x08019429 80193a8: 08019429 .word 0x08019429 80193ac: 08019429 .word 0x08019429 80193b0: 08019429 .word 0x08019429 80193b4: 08019429 .word 0x08019429 80193b8: 08019429 .word 0x08019429 80193bc: 08019429 .word 0x08019429 80193c0: 08019429 .word 0x08019429 80193c4: 2b6e cmp r3, #110 @ 0x6e 80193c6: d809 bhi.n 80193dc <_scanf_float+0x138> 80193c8: 2b60 cmp r3, #96 @ 0x60 80193ca: d8b1 bhi.n 8019330 <_scanf_float+0x8c> 80193cc: 2b54 cmp r3, #84 @ 0x54 80193ce: d07b beq.n 80194c8 <_scanf_float+0x224> 80193d0: 2b59 cmp r3, #89 @ 0x59 80193d2: d19a bne.n 801930a <_scanf_float+0x66> 80193d4: 2d07 cmp r5, #7 80193d6: d198 bne.n 801930a <_scanf_float+0x66> 80193d8: 2508 movs r5, #8 80193da: e02f b.n 801943c <_scanf_float+0x198> 80193dc: 2b74 cmp r3, #116 @ 0x74 80193de: d073 beq.n 80194c8 <_scanf_float+0x224> 80193e0: 2b79 cmp r3, #121 @ 0x79 80193e2: e7f6 b.n 80193d2 <_scanf_float+0x12e> 80193e4: 6821 ldr r1, [r4, #0] 80193e6: 05c8 lsls r0, r1, #23 80193e8: d51e bpl.n 8019428 <_scanf_float+0x184> 80193ea: f021 0180 bic.w r1, r1, #128 @ 0x80 80193ee: 6021 str r1, [r4, #0] 80193f0: 3701 adds r7, #1 80193f2: f1bb 0f00 cmp.w fp, #0 80193f6: d003 beq.n 8019400 <_scanf_float+0x15c> 80193f8: 3201 adds r2, #1 80193fa: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff 80193fe: 60a2 str r2, [r4, #8] 8019400: 68a3 ldr r3, [r4, #8] 8019402: 3b01 subs r3, #1 8019404: 60a3 str r3, [r4, #8] 8019406: 6923 ldr r3, [r4, #16] 8019408: 3301 adds r3, #1 801940a: 6123 str r3, [r4, #16] 801940c: f8d9 3004 ldr.w r3, [r9, #4] 8019410: 3b01 subs r3, #1 8019412: 2b00 cmp r3, #0 8019414: f8c9 3004 str.w r3, [r9, #4] 8019418: f340 8082 ble.w 8019520 <_scanf_float+0x27c> 801941c: f8d9 3000 ldr.w r3, [r9] 8019420: 3301 adds r3, #1 8019422: f8c9 3000 str.w r3, [r9] 8019426: e762 b.n 80192ee <_scanf_float+0x4a> 8019428: eb1a 0105 adds.w r1, sl, r5 801942c: f47f af6d bne.w 801930a <_scanf_float+0x66> 8019430: 6822 ldr r2, [r4, #0] 8019432: f422 72c0 bic.w r2, r2, #384 @ 0x180 8019436: 6022 str r2, [r4, #0] 8019438: 460d mov r5, r1 801943a: 468a mov sl, r1 801943c: f806 3b01 strb.w r3, [r6], #1 8019440: e7de b.n 8019400 <_scanf_float+0x15c> 8019442: 6822 ldr r2, [r4, #0] 8019444: 0610 lsls r0, r2, #24 8019446: f57f af60 bpl.w 801930a <_scanf_float+0x66> 801944a: f022 0280 bic.w r2, r2, #128 @ 0x80 801944e: 6022 str r2, [r4, #0] 8019450: e7f4 b.n 801943c <_scanf_float+0x198> 8019452: f1ba 0f00 cmp.w sl, #0 8019456: d10c bne.n 8019472 <_scanf_float+0x1ce> 8019458: b977 cbnz r7, 8019478 <_scanf_float+0x1d4> 801945a: 6822 ldr r2, [r4, #0] 801945c: f402 61e0 and.w r1, r2, #1792 @ 0x700 8019460: f5b1 6fe0 cmp.w r1, #1792 @ 0x700 8019464: d108 bne.n 8019478 <_scanf_float+0x1d4> 8019466: f422 62f0 bic.w r2, r2, #1920 @ 0x780 801946a: 6022 str r2, [r4, #0] 801946c: f04f 0a01 mov.w sl, #1 8019470: e7e4 b.n 801943c <_scanf_float+0x198> 8019472: f1ba 0f02 cmp.w sl, #2 8019476: d050 beq.n 801951a <_scanf_float+0x276> 8019478: 2d01 cmp r5, #1 801947a: d002 beq.n 8019482 <_scanf_float+0x1de> 801947c: 2d04 cmp r5, #4 801947e: f47f af44 bne.w 801930a <_scanf_float+0x66> 8019482: 3501 adds r5, #1 8019484: b2ed uxtb r5, r5 8019486: e7d9 b.n 801943c <_scanf_float+0x198> 8019488: f1ba 0f01 cmp.w sl, #1 801948c: f47f af3d bne.w 801930a <_scanf_float+0x66> 8019490: f04f 0a02 mov.w sl, #2 8019494: e7d2 b.n 801943c <_scanf_float+0x198> 8019496: b975 cbnz r5, 80194b6 <_scanf_float+0x212> 8019498: 2f00 cmp r7, #0 801949a: f47f af37 bne.w 801930c <_scanf_float+0x68> 801949e: 6822 ldr r2, [r4, #0] 80194a0: f402 61e0 and.w r1, r2, #1792 @ 0x700 80194a4: f5b1 6fe0 cmp.w r1, #1792 @ 0x700 80194a8: f040 8102 bne.w 80196b0 <_scanf_float+0x40c> 80194ac: f422 62f0 bic.w r2, r2, #1920 @ 0x780 80194b0: 6022 str r2, [r4, #0] 80194b2: 2501 movs r5, #1 80194b4: e7c2 b.n 801943c <_scanf_float+0x198> 80194b6: 2d03 cmp r5, #3 80194b8: d0e3 beq.n 8019482 <_scanf_float+0x1de> 80194ba: 2d05 cmp r5, #5 80194bc: e7df b.n 801947e <_scanf_float+0x1da> 80194be: 2d02 cmp r5, #2 80194c0: f47f af23 bne.w 801930a <_scanf_float+0x66> 80194c4: 2503 movs r5, #3 80194c6: e7b9 b.n 801943c <_scanf_float+0x198> 80194c8: 2d06 cmp r5, #6 80194ca: f47f af1e bne.w 801930a <_scanf_float+0x66> 80194ce: 2507 movs r5, #7 80194d0: e7b4 b.n 801943c <_scanf_float+0x198> 80194d2: 6822 ldr r2, [r4, #0] 80194d4: 0591 lsls r1, r2, #22 80194d6: f57f af18 bpl.w 801930a <_scanf_float+0x66> 80194da: f422 7220 bic.w r2, r2, #640 @ 0x280 80194de: 6022 str r2, [r4, #0] 80194e0: 9702 str r7, [sp, #8] 80194e2: e7ab b.n 801943c <_scanf_float+0x198> 80194e4: 6822 ldr r2, [r4, #0] 80194e6: f402 61a0 and.w r1, r2, #1280 @ 0x500 80194ea: f5b1 6f80 cmp.w r1, #1024 @ 0x400 80194ee: d005 beq.n 80194fc <_scanf_float+0x258> 80194f0: 0550 lsls r0, r2, #21 80194f2: f57f af0a bpl.w 801930a <_scanf_float+0x66> 80194f6: 2f00 cmp r7, #0 80194f8: f000 80da beq.w 80196b0 <_scanf_float+0x40c> 80194fc: 0591 lsls r1, r2, #22 80194fe: bf58 it pl 8019500: 9902 ldrpl r1, [sp, #8] 8019502: f422 62f0 bic.w r2, r2, #1920 @ 0x780 8019506: bf58 it pl 8019508: 1a79 subpl r1, r7, r1 801950a: f442 72c0 orr.w r2, r2, #384 @ 0x180 801950e: bf58 it pl 8019510: e9cd 1604 strdpl r1, r6, [sp, #16] 8019514: 6022 str r2, [r4, #0] 8019516: 2700 movs r7, #0 8019518: e790 b.n 801943c <_scanf_float+0x198> 801951a: f04f 0a03 mov.w sl, #3 801951e: e78d b.n 801943c <_scanf_float+0x198> 8019520: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180 8019524: 4649 mov r1, r9 8019526: 4640 mov r0, r8 8019528: 4798 blx r3 801952a: 2800 cmp r0, #0 801952c: f43f aedf beq.w 80192ee <_scanf_float+0x4a> 8019530: e6eb b.n 801930a <_scanf_float+0x66> 8019532: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 8019536: f816 1d01 ldrb.w r1, [r6, #-1]! 801953a: 464a mov r2, r9 801953c: 4640 mov r0, r8 801953e: 4798 blx r3 8019540: 6923 ldr r3, [r4, #16] 8019542: 3b01 subs r3, #1 8019544: 6123 str r3, [r4, #16] 8019546: e6eb b.n 8019320 <_scanf_float+0x7c> 8019548: 1e6b subs r3, r5, #1 801954a: 2b06 cmp r3, #6 801954c: d824 bhi.n 8019598 <_scanf_float+0x2f4> 801954e: 2d02 cmp r5, #2 8019550: d836 bhi.n 80195c0 <_scanf_float+0x31c> 8019552: 9b01 ldr r3, [sp, #4] 8019554: 429e cmp r6, r3 8019556: f67f aee7 bls.w 8019328 <_scanf_float+0x84> 801955a: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 801955e: f816 1d01 ldrb.w r1, [r6, #-1]! 8019562: 464a mov r2, r9 8019564: 4640 mov r0, r8 8019566: 4798 blx r3 8019568: 6923 ldr r3, [r4, #16] 801956a: 3b01 subs r3, #1 801956c: 6123 str r3, [r4, #16] 801956e: e7f0 b.n 8019552 <_scanf_float+0x2ae> 8019570: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 8019574: f81b 1d01 ldrb.w r1, [fp, #-1]! 8019578: 464a mov r2, r9 801957a: 4640 mov r0, r8 801957c: 4798 blx r3 801957e: 6923 ldr r3, [r4, #16] 8019580: 3b01 subs r3, #1 8019582: 6123 str r3, [r4, #16] 8019584: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 8019588: fa5f fa8a uxtb.w sl, sl 801958c: f1ba 0f02 cmp.w sl, #2 8019590: d1ee bne.n 8019570 <_scanf_float+0x2cc> 8019592: 3d03 subs r5, #3 8019594: b2ed uxtb r5, r5 8019596: 1b76 subs r6, r6, r5 8019598: 6823 ldr r3, [r4, #0] 801959a: 05da lsls r2, r3, #23 801959c: d530 bpl.n 8019600 <_scanf_float+0x35c> 801959e: 055d lsls r5, r3, #21 80195a0: d511 bpl.n 80195c6 <_scanf_float+0x322> 80195a2: 9b01 ldr r3, [sp, #4] 80195a4: 429e cmp r6, r3 80195a6: f67f aebf bls.w 8019328 <_scanf_float+0x84> 80195aa: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 80195ae: f816 1d01 ldrb.w r1, [r6, #-1]! 80195b2: 464a mov r2, r9 80195b4: 4640 mov r0, r8 80195b6: 4798 blx r3 80195b8: 6923 ldr r3, [r4, #16] 80195ba: 3b01 subs r3, #1 80195bc: 6123 str r3, [r4, #16] 80195be: e7f0 b.n 80195a2 <_scanf_float+0x2fe> 80195c0: 46aa mov sl, r5 80195c2: 46b3 mov fp, r6 80195c4: e7de b.n 8019584 <_scanf_float+0x2e0> 80195c6: f816 1c01 ldrb.w r1, [r6, #-1] 80195ca: 6923 ldr r3, [r4, #16] 80195cc: 2965 cmp r1, #101 @ 0x65 80195ce: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 80195d2: f106 35ff add.w r5, r6, #4294967295 @ 0xffffffff 80195d6: 6123 str r3, [r4, #16] 80195d8: d00c beq.n 80195f4 <_scanf_float+0x350> 80195da: 2945 cmp r1, #69 @ 0x45 80195dc: d00a beq.n 80195f4 <_scanf_float+0x350> 80195de: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 80195e2: 464a mov r2, r9 80195e4: 4640 mov r0, r8 80195e6: 4798 blx r3 80195e8: 6923 ldr r3, [r4, #16] 80195ea: f816 1c02 ldrb.w r1, [r6, #-2] 80195ee: 3b01 subs r3, #1 80195f0: 1eb5 subs r5, r6, #2 80195f2: 6123 str r3, [r4, #16] 80195f4: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 80195f8: 464a mov r2, r9 80195fa: 4640 mov r0, r8 80195fc: 4798 blx r3 80195fe: 462e mov r6, r5 8019600: 6822 ldr r2, [r4, #0] 8019602: f012 0210 ands.w r2, r2, #16 8019606: d001 beq.n 801960c <_scanf_float+0x368> 8019608: 2000 movs r0, #0 801960a: e68e b.n 801932a <_scanf_float+0x86> 801960c: 7032 strb r2, [r6, #0] 801960e: 6823 ldr r3, [r4, #0] 8019610: f403 63c0 and.w r3, r3, #1536 @ 0x600 8019614: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8019618: d124 bne.n 8019664 <_scanf_float+0x3c0> 801961a: 9b02 ldr r3, [sp, #8] 801961c: 429f cmp r7, r3 801961e: d00a beq.n 8019636 <_scanf_float+0x392> 8019620: 1bda subs r2, r3, r7 8019622: f204 136f addw r3, r4, #367 @ 0x16f 8019626: 429e cmp r6, r3 8019628: bf28 it cs 801962a: f504 76b7 addcs.w r6, r4, #366 @ 0x16e 801962e: 4921 ldr r1, [pc, #132] @ (80196b4 <_scanf_float+0x410>) 8019630: 4630 mov r0, r6 8019632: f000 f977 bl 8019924 8019636: 9901 ldr r1, [sp, #4] 8019638: 2200 movs r2, #0 801963a: 4640 mov r0, r8 801963c: f002 fd18 bl 801c070 <_strtod_r> 8019640: 9b03 ldr r3, [sp, #12] 8019642: 6821 ldr r1, [r4, #0] 8019644: 681b ldr r3, [r3, #0] 8019646: 0788 lsls r0, r1, #30 8019648: ec57 6b10 vmov r6, r7, d0 801964c: f103 0204 add.w r2, r3, #4 8019650: d515 bpl.n 801967e <_scanf_float+0x3da> 8019652: 9903 ldr r1, [sp, #12] 8019654: 600a str r2, [r1, #0] 8019656: 681b ldr r3, [r3, #0] 8019658: e9c3 6700 strd r6, r7, [r3] 801965c: 68e3 ldr r3, [r4, #12] 801965e: 3301 adds r3, #1 8019660: 60e3 str r3, [r4, #12] 8019662: e7d1 b.n 8019608 <_scanf_float+0x364> 8019664: 9b04 ldr r3, [sp, #16] 8019666: 2b00 cmp r3, #0 8019668: d0e5 beq.n 8019636 <_scanf_float+0x392> 801966a: 9905 ldr r1, [sp, #20] 801966c: 230a movs r3, #10 801966e: 3101 adds r1, #1 8019670: 4640 mov r0, r8 8019672: f002 fd7d bl 801c170 <_strtol_r> 8019676: 9b04 ldr r3, [sp, #16] 8019678: 9e05 ldr r6, [sp, #20] 801967a: 1ac2 subs r2, r0, r3 801967c: e7d1 b.n 8019622 <_scanf_float+0x37e> 801967e: f011 0f04 tst.w r1, #4 8019682: 9903 ldr r1, [sp, #12] 8019684: 600a str r2, [r1, #0] 8019686: d1e6 bne.n 8019656 <_scanf_float+0x3b2> 8019688: 681d ldr r5, [r3, #0] 801968a: 4632 mov r2, r6 801968c: 463b mov r3, r7 801968e: 4630 mov r0, r6 8019690: 4639 mov r1, r7 8019692: f7e7 fa23 bl 8000adc <__aeabi_dcmpun> 8019696: b128 cbz r0, 80196a4 <_scanf_float+0x400> 8019698: 4807 ldr r0, [pc, #28] @ (80196b8 <_scanf_float+0x414>) 801969a: f000 fac9 bl 8019c30 801969e: ed85 0a00 vstr s0, [r5] 80196a2: e7db b.n 801965c <_scanf_float+0x3b8> 80196a4: 4630 mov r0, r6 80196a6: 4639 mov r1, r7 80196a8: f7e7 fa76 bl 8000b98 <__aeabi_d2f> 80196ac: 6028 str r0, [r5, #0] 80196ae: e7d5 b.n 801965c <_scanf_float+0x3b8> 80196b0: 2700 movs r7, #0 80196b2: e62f b.n 8019314 <_scanf_float+0x70> 80196b4: 0801dce4 .word 0x0801dce4 80196b8: 0801de25 .word 0x0801de25 080196bc : 80196bc: 2300 movs r3, #0 80196be: b510 push {r4, lr} 80196c0: 4604 mov r4, r0 80196c2: e9c0 3300 strd r3, r3, [r0] 80196c6: e9c0 3304 strd r3, r3, [r0, #16] 80196ca: 6083 str r3, [r0, #8] 80196cc: 8181 strh r1, [r0, #12] 80196ce: 6643 str r3, [r0, #100] @ 0x64 80196d0: 81c2 strh r2, [r0, #14] 80196d2: 6183 str r3, [r0, #24] 80196d4: 4619 mov r1, r3 80196d6: 2208 movs r2, #8 80196d8: 305c adds r0, #92 @ 0x5c 80196da: f000 fa1b bl 8019b14 80196de: 4b0d ldr r3, [pc, #52] @ (8019714 ) 80196e0: 6263 str r3, [r4, #36] @ 0x24 80196e2: 4b0d ldr r3, [pc, #52] @ (8019718 ) 80196e4: 62a3 str r3, [r4, #40] @ 0x28 80196e6: 4b0d ldr r3, [pc, #52] @ (801971c ) 80196e8: 62e3 str r3, [r4, #44] @ 0x2c 80196ea: 4b0d ldr r3, [pc, #52] @ (8019720 ) 80196ec: 6323 str r3, [r4, #48] @ 0x30 80196ee: 4b0d ldr r3, [pc, #52] @ (8019724 ) 80196f0: 6224 str r4, [r4, #32] 80196f2: 429c cmp r4, r3 80196f4: d006 beq.n 8019704 80196f6: f103 0268 add.w r2, r3, #104 @ 0x68 80196fa: 4294 cmp r4, r2 80196fc: d002 beq.n 8019704 80196fe: 33d0 adds r3, #208 @ 0xd0 8019700: 429c cmp r4, r3 8019702: d105 bne.n 8019710 8019704: f104 0058 add.w r0, r4, #88 @ 0x58 8019708: e8bd 4010 ldmia.w sp!, {r4, lr} 801970c: f000 ba7e b.w 8019c0c <__retarget_lock_init_recursive> 8019710: bd10 pop {r4, pc} 8019712: bf00 nop 8019714: 08019969 .word 0x08019969 8019718: 0801998b .word 0x0801998b 801971c: 080199c3 .word 0x080199c3 8019720: 080199e9 .word 0x080199e9 8019724: 20013afc .word 0x20013afc 08019728 : 8019728: 4a02 ldr r2, [pc, #8] @ (8019734 ) 801972a: 4903 ldr r1, [pc, #12] @ (8019738 ) 801972c: 4803 ldr r0, [pc, #12] @ (801973c ) 801972e: f000 b86b b.w 8019808 <_fwalk_sglue> 8019732: bf00 nop 8019734: 20000110 .word 0x20000110 8019738: 0801c7a5 .word 0x0801c7a5 801973c: 20000120 .word 0x20000120 08019740 : 8019740: 6841 ldr r1, [r0, #4] 8019742: 4b0c ldr r3, [pc, #48] @ (8019774 ) 8019744: 4299 cmp r1, r3 8019746: b510 push {r4, lr} 8019748: 4604 mov r4, r0 801974a: d001 beq.n 8019750 801974c: f003 f82a bl 801c7a4 <_fflush_r> 8019750: 68a1 ldr r1, [r4, #8] 8019752: 4b09 ldr r3, [pc, #36] @ (8019778 ) 8019754: 4299 cmp r1, r3 8019756: d002 beq.n 801975e 8019758: 4620 mov r0, r4 801975a: f003 f823 bl 801c7a4 <_fflush_r> 801975e: 68e1 ldr r1, [r4, #12] 8019760: 4b06 ldr r3, [pc, #24] @ (801977c ) 8019762: 4299 cmp r1, r3 8019764: d004 beq.n 8019770 8019766: 4620 mov r0, r4 8019768: e8bd 4010 ldmia.w sp!, {r4, lr} 801976c: f003 b81a b.w 801c7a4 <_fflush_r> 8019770: bd10 pop {r4, pc} 8019772: bf00 nop 8019774: 20013afc .word 0x20013afc 8019778: 20013b64 .word 0x20013b64 801977c: 20013bcc .word 0x20013bcc 08019780 : 8019780: 4b0c ldr r3, [pc, #48] @ (80197b4 ) 8019782: 4a0d ldr r2, [pc, #52] @ (80197b8 ) 8019784: 480d ldr r0, [pc, #52] @ (80197bc ) 8019786: b510 push {r4, lr} 8019788: 2104 movs r1, #4 801978a: 601a str r2, [r3, #0] 801978c: 2200 movs r2, #0 801978e: f7ff ff95 bl 80196bc 8019792: 4b0a ldr r3, [pc, #40] @ (80197bc ) 8019794: 2201 movs r2, #1 8019796: 461c mov r4, r3 8019798: 2109 movs r1, #9 801979a: f103 0068 add.w r0, r3, #104 @ 0x68 801979e: f7ff ff8d bl 80196bc 80197a2: f104 00d0 add.w r0, r4, #208 @ 0xd0 80197a6: 2202 movs r2, #2 80197a8: e8bd 4010 ldmia.w sp!, {r4, lr} 80197ac: 2112 movs r1, #18 80197ae: f7ff bf85 b.w 80196bc 80197b2: bf00 nop 80197b4: 20013c34 .word 0x20013c34 80197b8: 08019729 .word 0x08019729 80197bc: 20013afc .word 0x20013afc 080197c0 <__sfp_lock_acquire>: 80197c0: 4801 ldr r0, [pc, #4] @ (80197c8 <__sfp_lock_acquire+0x8>) 80197c2: f000 ba24 b.w 8019c0e <__retarget_lock_acquire_recursive> 80197c6: bf00 nop 80197c8: 20013c3d .word 0x20013c3d 080197cc <__sfp_lock_release>: 80197cc: 4801 ldr r0, [pc, #4] @ (80197d4 <__sfp_lock_release+0x8>) 80197ce: f000 ba1f b.w 8019c10 <__retarget_lock_release_recursive> 80197d2: bf00 nop 80197d4: 20013c3d .word 0x20013c3d 080197d8 <__sinit>: 80197d8: b510 push {r4, lr} 80197da: 4604 mov r4, r0 80197dc: f7ff fff0 bl 80197c0 <__sfp_lock_acquire> 80197e0: 6a23 ldr r3, [r4, #32] 80197e2: b11b cbz r3, 80197ec <__sinit+0x14> 80197e4: e8bd 4010 ldmia.w sp!, {r4, lr} 80197e8: f7ff bff0 b.w 80197cc <__sfp_lock_release> 80197ec: 4b04 ldr r3, [pc, #16] @ (8019800 <__sinit+0x28>) 80197ee: 6223 str r3, [r4, #32] 80197f0: 4b04 ldr r3, [pc, #16] @ (8019804 <__sinit+0x2c>) 80197f2: 681b ldr r3, [r3, #0] 80197f4: 2b00 cmp r3, #0 80197f6: d1f5 bne.n 80197e4 <__sinit+0xc> 80197f8: f7ff ffc2 bl 8019780 80197fc: e7f2 b.n 80197e4 <__sinit+0xc> 80197fe: bf00 nop 8019800: 08019741 .word 0x08019741 8019804: 20013c34 .word 0x20013c34 08019808 <_fwalk_sglue>: 8019808: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801980c: 4607 mov r7, r0 801980e: 4688 mov r8, r1 8019810: 4614 mov r4, r2 8019812: 2600 movs r6, #0 8019814: e9d4 9501 ldrd r9, r5, [r4, #4] 8019818: f1b9 0901 subs.w r9, r9, #1 801981c: d505 bpl.n 801982a <_fwalk_sglue+0x22> 801981e: 6824 ldr r4, [r4, #0] 8019820: 2c00 cmp r4, #0 8019822: d1f7 bne.n 8019814 <_fwalk_sglue+0xc> 8019824: 4630 mov r0, r6 8019826: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801982a: 89ab ldrh r3, [r5, #12] 801982c: 2b01 cmp r3, #1 801982e: d907 bls.n 8019840 <_fwalk_sglue+0x38> 8019830: f9b5 300e ldrsh.w r3, [r5, #14] 8019834: 3301 adds r3, #1 8019836: d003 beq.n 8019840 <_fwalk_sglue+0x38> 8019838: 4629 mov r1, r5 801983a: 4638 mov r0, r7 801983c: 47c0 blx r8 801983e: 4306 orrs r6, r0 8019840: 3568 adds r5, #104 @ 0x68 8019842: e7e9 b.n 8019818 <_fwalk_sglue+0x10> 08019844 : 8019844: b40f push {r0, r1, r2, r3} 8019846: b507 push {r0, r1, r2, lr} 8019848: 4906 ldr r1, [pc, #24] @ (8019864 ) 801984a: ab04 add r3, sp, #16 801984c: 6808 ldr r0, [r1, #0] 801984e: f853 2b04 ldr.w r2, [r3], #4 8019852: 6881 ldr r1, [r0, #8] 8019854: 9301 str r3, [sp, #4] 8019856: f002 fe0f bl 801c478 <_vfiprintf_r> 801985a: b003 add sp, #12 801985c: f85d eb04 ldr.w lr, [sp], #4 8019860: b004 add sp, #16 8019862: 4770 bx lr 8019864: 2000011c .word 0x2000011c 08019868 <_puts_r>: 8019868: 6a03 ldr r3, [r0, #32] 801986a: b570 push {r4, r5, r6, lr} 801986c: 6884 ldr r4, [r0, #8] 801986e: 4605 mov r5, r0 8019870: 460e mov r6, r1 8019872: b90b cbnz r3, 8019878 <_puts_r+0x10> 8019874: f7ff ffb0 bl 80197d8 <__sinit> 8019878: 6e63 ldr r3, [r4, #100] @ 0x64 801987a: 07db lsls r3, r3, #31 801987c: d405 bmi.n 801988a <_puts_r+0x22> 801987e: 89a3 ldrh r3, [r4, #12] 8019880: 0598 lsls r0, r3, #22 8019882: d402 bmi.n 801988a <_puts_r+0x22> 8019884: 6da0 ldr r0, [r4, #88] @ 0x58 8019886: f000 f9c2 bl 8019c0e <__retarget_lock_acquire_recursive> 801988a: 89a3 ldrh r3, [r4, #12] 801988c: 0719 lsls r1, r3, #28 801988e: d502 bpl.n 8019896 <_puts_r+0x2e> 8019890: 6923 ldr r3, [r4, #16] 8019892: 2b00 cmp r3, #0 8019894: d135 bne.n 8019902 <_puts_r+0x9a> 8019896: 4621 mov r1, r4 8019898: 4628 mov r0, r5 801989a: f000 f8e7 bl 8019a6c <__swsetup_r> 801989e: b380 cbz r0, 8019902 <_puts_r+0x9a> 80198a0: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff 80198a4: 6e63 ldr r3, [r4, #100] @ 0x64 80198a6: 07da lsls r2, r3, #31 80198a8: d405 bmi.n 80198b6 <_puts_r+0x4e> 80198aa: 89a3 ldrh r3, [r4, #12] 80198ac: 059b lsls r3, r3, #22 80198ae: d402 bmi.n 80198b6 <_puts_r+0x4e> 80198b0: 6da0 ldr r0, [r4, #88] @ 0x58 80198b2: f000 f9ad bl 8019c10 <__retarget_lock_release_recursive> 80198b6: 4628 mov r0, r5 80198b8: bd70 pop {r4, r5, r6, pc} 80198ba: 2b00 cmp r3, #0 80198bc: da04 bge.n 80198c8 <_puts_r+0x60> 80198be: 69a2 ldr r2, [r4, #24] 80198c0: 4293 cmp r3, r2 80198c2: db17 blt.n 80198f4 <_puts_r+0x8c> 80198c4: 290a cmp r1, #10 80198c6: d015 beq.n 80198f4 <_puts_r+0x8c> 80198c8: 6823 ldr r3, [r4, #0] 80198ca: 1c5a adds r2, r3, #1 80198cc: 6022 str r2, [r4, #0] 80198ce: 7019 strb r1, [r3, #0] 80198d0: 68a3 ldr r3, [r4, #8] 80198d2: f816 1f01 ldrb.w r1, [r6, #1]! 80198d6: 3b01 subs r3, #1 80198d8: 60a3 str r3, [r4, #8] 80198da: 2900 cmp r1, #0 80198dc: d1ed bne.n 80198ba <_puts_r+0x52> 80198de: 2b00 cmp r3, #0 80198e0: da11 bge.n 8019906 <_puts_r+0x9e> 80198e2: 4622 mov r2, r4 80198e4: 210a movs r1, #10 80198e6: 4628 mov r0, r5 80198e8: f000 f882 bl 80199f0 <__swbuf_r> 80198ec: 3001 adds r0, #1 80198ee: d0d7 beq.n 80198a0 <_puts_r+0x38> 80198f0: 250a movs r5, #10 80198f2: e7d7 b.n 80198a4 <_puts_r+0x3c> 80198f4: 4622 mov r2, r4 80198f6: 4628 mov r0, r5 80198f8: f000 f87a bl 80199f0 <__swbuf_r> 80198fc: 3001 adds r0, #1 80198fe: d1e7 bne.n 80198d0 <_puts_r+0x68> 8019900: e7ce b.n 80198a0 <_puts_r+0x38> 8019902: 3e01 subs r6, #1 8019904: e7e4 b.n 80198d0 <_puts_r+0x68> 8019906: 6823 ldr r3, [r4, #0] 8019908: 1c5a adds r2, r3, #1 801990a: 6022 str r2, [r4, #0] 801990c: 220a movs r2, #10 801990e: 701a strb r2, [r3, #0] 8019910: e7ee b.n 80198f0 <_puts_r+0x88> ... 08019914 : 8019914: 4b02 ldr r3, [pc, #8] @ (8019920 ) 8019916: 4601 mov r1, r0 8019918: 6818 ldr r0, [r3, #0] 801991a: f7ff bfa5 b.w 8019868 <_puts_r> 801991e: bf00 nop 8019920: 2000011c .word 0x2000011c 08019924 : 8019924: b40e push {r1, r2, r3} 8019926: b510 push {r4, lr} 8019928: b09d sub sp, #116 @ 0x74 801992a: ab1f add r3, sp, #124 @ 0x7c 801992c: 9002 str r0, [sp, #8] 801992e: 9006 str r0, [sp, #24] 8019930: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000 8019934: 480a ldr r0, [pc, #40] @ (8019960 ) 8019936: 9107 str r1, [sp, #28] 8019938: 9104 str r1, [sp, #16] 801993a: 490a ldr r1, [pc, #40] @ (8019964 ) 801993c: f853 2b04 ldr.w r2, [r3], #4 8019940: 9105 str r1, [sp, #20] 8019942: 2400 movs r4, #0 8019944: a902 add r1, sp, #8 8019946: 6800 ldr r0, [r0, #0] 8019948: 9301 str r3, [sp, #4] 801994a: 941b str r4, [sp, #108] @ 0x6c 801994c: f002 fc72 bl 801c234 <_svfiprintf_r> 8019950: 9b02 ldr r3, [sp, #8] 8019952: 701c strb r4, [r3, #0] 8019954: b01d add sp, #116 @ 0x74 8019956: e8bd 4010 ldmia.w sp!, {r4, lr} 801995a: b003 add sp, #12 801995c: 4770 bx lr 801995e: bf00 nop 8019960: 2000011c .word 0x2000011c 8019964: ffff0208 .word 0xffff0208 08019968 <__sread>: 8019968: b510 push {r4, lr} 801996a: 460c mov r4, r1 801996c: f9b1 100e ldrsh.w r1, [r1, #14] 8019970: f000 f8fe bl 8019b70 <_read_r> 8019974: 2800 cmp r0, #0 8019976: bfab itete ge 8019978: 6d63 ldrge r3, [r4, #84] @ 0x54 801997a: 89a3 ldrhlt r3, [r4, #12] 801997c: 181b addge r3, r3, r0 801997e: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 8019982: bfac ite ge 8019984: 6563 strge r3, [r4, #84] @ 0x54 8019986: 81a3 strhlt r3, [r4, #12] 8019988: bd10 pop {r4, pc} 0801998a <__swrite>: 801998a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801998e: 461f mov r7, r3 8019990: 898b ldrh r3, [r1, #12] 8019992: 05db lsls r3, r3, #23 8019994: 4605 mov r5, r0 8019996: 460c mov r4, r1 8019998: 4616 mov r6, r2 801999a: d505 bpl.n 80199a8 <__swrite+0x1e> 801999c: f9b1 100e ldrsh.w r1, [r1, #14] 80199a0: 2302 movs r3, #2 80199a2: 2200 movs r2, #0 80199a4: f000 f8d2 bl 8019b4c <_lseek_r> 80199a8: 89a3 ldrh r3, [r4, #12] 80199aa: f9b4 100e ldrsh.w r1, [r4, #14] 80199ae: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80199b2: 81a3 strh r3, [r4, #12] 80199b4: 4632 mov r2, r6 80199b6: 463b mov r3, r7 80199b8: 4628 mov r0, r5 80199ba: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 80199be: f000 b8e9 b.w 8019b94 <_write_r> 080199c2 <__sseek>: 80199c2: b510 push {r4, lr} 80199c4: 460c mov r4, r1 80199c6: f9b1 100e ldrsh.w r1, [r1, #14] 80199ca: f000 f8bf bl 8019b4c <_lseek_r> 80199ce: f9b4 300c ldrsh.w r3, [r4, #12] 80199d2: 1c42 adds r2, r0, #1 80199d4: bf0b itete eq 80199d6: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 80199da: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 80199de: 81a3 strheq r3, [r4, #12] 80199e0: 81a3 strhne r3, [r4, #12] 80199e2: bf18 it ne 80199e4: 6560 strne r0, [r4, #84] @ 0x54 80199e6: bd10 pop {r4, pc} 080199e8 <__sclose>: 80199e8: f9b1 100e ldrsh.w r1, [r1, #14] 80199ec: f000 b89e b.w 8019b2c <_close_r> 080199f0 <__swbuf_r>: 80199f0: b5f8 push {r3, r4, r5, r6, r7, lr} 80199f2: 460e mov r6, r1 80199f4: 4614 mov r4, r2 80199f6: 4605 mov r5, r0 80199f8: b118 cbz r0, 8019a02 <__swbuf_r+0x12> 80199fa: 6a03 ldr r3, [r0, #32] 80199fc: b90b cbnz r3, 8019a02 <__swbuf_r+0x12> 80199fe: f7ff feeb bl 80197d8 <__sinit> 8019a02: 69a3 ldr r3, [r4, #24] 8019a04: 60a3 str r3, [r4, #8] 8019a06: 89a3 ldrh r3, [r4, #12] 8019a08: 071a lsls r2, r3, #28 8019a0a: d501 bpl.n 8019a10 <__swbuf_r+0x20> 8019a0c: 6923 ldr r3, [r4, #16] 8019a0e: b943 cbnz r3, 8019a22 <__swbuf_r+0x32> 8019a10: 4621 mov r1, r4 8019a12: 4628 mov r0, r5 8019a14: f000 f82a bl 8019a6c <__swsetup_r> 8019a18: b118 cbz r0, 8019a22 <__swbuf_r+0x32> 8019a1a: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 8019a1e: 4638 mov r0, r7 8019a20: bdf8 pop {r3, r4, r5, r6, r7, pc} 8019a22: 6823 ldr r3, [r4, #0] 8019a24: 6922 ldr r2, [r4, #16] 8019a26: 1a98 subs r0, r3, r2 8019a28: 6963 ldr r3, [r4, #20] 8019a2a: b2f6 uxtb r6, r6 8019a2c: 4283 cmp r3, r0 8019a2e: 4637 mov r7, r6 8019a30: dc05 bgt.n 8019a3e <__swbuf_r+0x4e> 8019a32: 4621 mov r1, r4 8019a34: 4628 mov r0, r5 8019a36: f002 feb5 bl 801c7a4 <_fflush_r> 8019a3a: 2800 cmp r0, #0 8019a3c: d1ed bne.n 8019a1a <__swbuf_r+0x2a> 8019a3e: 68a3 ldr r3, [r4, #8] 8019a40: 3b01 subs r3, #1 8019a42: 60a3 str r3, [r4, #8] 8019a44: 6823 ldr r3, [r4, #0] 8019a46: 1c5a adds r2, r3, #1 8019a48: 6022 str r2, [r4, #0] 8019a4a: 701e strb r6, [r3, #0] 8019a4c: 6962 ldr r2, [r4, #20] 8019a4e: 1c43 adds r3, r0, #1 8019a50: 429a cmp r2, r3 8019a52: d004 beq.n 8019a5e <__swbuf_r+0x6e> 8019a54: 89a3 ldrh r3, [r4, #12] 8019a56: 07db lsls r3, r3, #31 8019a58: d5e1 bpl.n 8019a1e <__swbuf_r+0x2e> 8019a5a: 2e0a cmp r6, #10 8019a5c: d1df bne.n 8019a1e <__swbuf_r+0x2e> 8019a5e: 4621 mov r1, r4 8019a60: 4628 mov r0, r5 8019a62: f002 fe9f bl 801c7a4 <_fflush_r> 8019a66: 2800 cmp r0, #0 8019a68: d0d9 beq.n 8019a1e <__swbuf_r+0x2e> 8019a6a: e7d6 b.n 8019a1a <__swbuf_r+0x2a> 08019a6c <__swsetup_r>: 8019a6c: b538 push {r3, r4, r5, lr} 8019a6e: 4b28 ldr r3, [pc, #160] @ (8019b10 <__swsetup_r+0xa4>) 8019a70: 4605 mov r5, r0 8019a72: 6818 ldr r0, [r3, #0] 8019a74: 460c mov r4, r1 8019a76: b118 cbz r0, 8019a80 <__swsetup_r+0x14> 8019a78: 6a03 ldr r3, [r0, #32] 8019a7a: b90b cbnz r3, 8019a80 <__swsetup_r+0x14> 8019a7c: f7ff feac bl 80197d8 <__sinit> 8019a80: f9b4 300c ldrsh.w r3, [r4, #12] 8019a84: 071a lsls r2, r3, #28 8019a86: d421 bmi.n 8019acc <__swsetup_r+0x60> 8019a88: 06d8 lsls r0, r3, #27 8019a8a: d407 bmi.n 8019a9c <__swsetup_r+0x30> 8019a8c: 2209 movs r2, #9 8019a8e: 602a str r2, [r5, #0] 8019a90: f043 0340 orr.w r3, r3, #64 @ 0x40 8019a94: 81a3 strh r3, [r4, #12] 8019a96: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8019a9a: e030 b.n 8019afe <__swsetup_r+0x92> 8019a9c: 0759 lsls r1, r3, #29 8019a9e: d512 bpl.n 8019ac6 <__swsetup_r+0x5a> 8019aa0: 6b61 ldr r1, [r4, #52] @ 0x34 8019aa2: b141 cbz r1, 8019ab6 <__swsetup_r+0x4a> 8019aa4: f104 0344 add.w r3, r4, #68 @ 0x44 8019aa8: 4299 cmp r1, r3 8019aaa: d002 beq.n 8019ab2 <__swsetup_r+0x46> 8019aac: 4628 mov r0, r5 8019aae: f000 ff2b bl 801a908 <_free_r> 8019ab2: 2300 movs r3, #0 8019ab4: 6363 str r3, [r4, #52] @ 0x34 8019ab6: 2200 movs r2, #0 8019ab8: f9b4 300c ldrsh.w r3, [r4, #12] 8019abc: 6062 str r2, [r4, #4] 8019abe: 6922 ldr r2, [r4, #16] 8019ac0: 6022 str r2, [r4, #0] 8019ac2: f023 0324 bic.w r3, r3, #36 @ 0x24 8019ac6: f043 0308 orr.w r3, r3, #8 8019aca: 81a3 strh r3, [r4, #12] 8019acc: 6922 ldr r2, [r4, #16] 8019ace: b93a cbnz r2, 8019ae0 <__swsetup_r+0x74> 8019ad0: 059a lsls r2, r3, #22 8019ad2: d501 bpl.n 8019ad8 <__swsetup_r+0x6c> 8019ad4: 0618 lsls r0, r3, #24 8019ad6: d503 bpl.n 8019ae0 <__swsetup_r+0x74> 8019ad8: 4621 mov r1, r4 8019ada: 4628 mov r0, r5 8019adc: f002 feae bl 801c83c <__smakebuf_r> 8019ae0: f9b4 300c ldrsh.w r3, [r4, #12] 8019ae4: f013 0201 ands.w r2, r3, #1 8019ae8: d00a beq.n 8019b00 <__swsetup_r+0x94> 8019aea: 2200 movs r2, #0 8019aec: 60a2 str r2, [r4, #8] 8019aee: 6962 ldr r2, [r4, #20] 8019af0: 4252 negs r2, r2 8019af2: 61a2 str r2, [r4, #24] 8019af4: 6922 ldr r2, [r4, #16] 8019af6: b942 cbnz r2, 8019b0a <__swsetup_r+0x9e> 8019af8: f013 0080 ands.w r0, r3, #128 @ 0x80 8019afc: d1c8 bne.n 8019a90 <__swsetup_r+0x24> 8019afe: bd38 pop {r3, r4, r5, pc} 8019b00: 0799 lsls r1, r3, #30 8019b02: bf58 it pl 8019b04: 6962 ldrpl r2, [r4, #20] 8019b06: 60a2 str r2, [r4, #8] 8019b08: e7f4 b.n 8019af4 <__swsetup_r+0x88> 8019b0a: 2000 movs r0, #0 8019b0c: e7f7 b.n 8019afe <__swsetup_r+0x92> 8019b0e: bf00 nop 8019b10: 2000011c .word 0x2000011c 08019b14 : 8019b14: 4402 add r2, r0 8019b16: 4603 mov r3, r0 8019b18: 4293 cmp r3, r2 8019b1a: d100 bne.n 8019b1e 8019b1c: 4770 bx lr 8019b1e: f803 1b01 strb.w r1, [r3], #1 8019b22: e7f9 b.n 8019b18 08019b24 <_localeconv_r>: 8019b24: 4800 ldr r0, [pc, #0] @ (8019b28 <_localeconv_r+0x4>) 8019b26: 4770 bx lr 8019b28: 2000025c .word 0x2000025c 08019b2c <_close_r>: 8019b2c: b538 push {r3, r4, r5, lr} 8019b2e: 4d06 ldr r5, [pc, #24] @ (8019b48 <_close_r+0x1c>) 8019b30: 2300 movs r3, #0 8019b32: 4604 mov r4, r0 8019b34: 4608 mov r0, r1 8019b36: 602b str r3, [r5, #0] 8019b38: f7ec fb70 bl 800621c <_close> 8019b3c: 1c43 adds r3, r0, #1 8019b3e: d102 bne.n 8019b46 <_close_r+0x1a> 8019b40: 682b ldr r3, [r5, #0] 8019b42: b103 cbz r3, 8019b46 <_close_r+0x1a> 8019b44: 6023 str r3, [r4, #0] 8019b46: bd38 pop {r3, r4, r5, pc} 8019b48: 20013c38 .word 0x20013c38 08019b4c <_lseek_r>: 8019b4c: b538 push {r3, r4, r5, lr} 8019b4e: 4d07 ldr r5, [pc, #28] @ (8019b6c <_lseek_r+0x20>) 8019b50: 4604 mov r4, r0 8019b52: 4608 mov r0, r1 8019b54: 4611 mov r1, r2 8019b56: 2200 movs r2, #0 8019b58: 602a str r2, [r5, #0] 8019b5a: 461a mov r2, r3 8019b5c: f7ec fb85 bl 800626a <_lseek> 8019b60: 1c43 adds r3, r0, #1 8019b62: d102 bne.n 8019b6a <_lseek_r+0x1e> 8019b64: 682b ldr r3, [r5, #0] 8019b66: b103 cbz r3, 8019b6a <_lseek_r+0x1e> 8019b68: 6023 str r3, [r4, #0] 8019b6a: bd38 pop {r3, r4, r5, pc} 8019b6c: 20013c38 .word 0x20013c38 08019b70 <_read_r>: 8019b70: b538 push {r3, r4, r5, lr} 8019b72: 4d07 ldr r5, [pc, #28] @ (8019b90 <_read_r+0x20>) 8019b74: 4604 mov r4, r0 8019b76: 4608 mov r0, r1 8019b78: 4611 mov r1, r2 8019b7a: 2200 movs r2, #0 8019b7c: 602a str r2, [r5, #0] 8019b7e: 461a mov r2, r3 8019b80: f7ec fb2f bl 80061e2 <_read> 8019b84: 1c43 adds r3, r0, #1 8019b86: d102 bne.n 8019b8e <_read_r+0x1e> 8019b88: 682b ldr r3, [r5, #0] 8019b8a: b103 cbz r3, 8019b8e <_read_r+0x1e> 8019b8c: 6023 str r3, [r4, #0] 8019b8e: bd38 pop {r3, r4, r5, pc} 8019b90: 20013c38 .word 0x20013c38 08019b94 <_write_r>: 8019b94: b538 push {r3, r4, r5, lr} 8019b96: 4d07 ldr r5, [pc, #28] @ (8019bb4 <_write_r+0x20>) 8019b98: 4604 mov r4, r0 8019b9a: 4608 mov r0, r1 8019b9c: 4611 mov r1, r2 8019b9e: 2200 movs r2, #0 8019ba0: 602a str r2, [r5, #0] 8019ba2: 461a mov r2, r3 8019ba4: f7ea fdba bl 800471c <_write> 8019ba8: 1c43 adds r3, r0, #1 8019baa: d102 bne.n 8019bb2 <_write_r+0x1e> 8019bac: 682b ldr r3, [r5, #0] 8019bae: b103 cbz r3, 8019bb2 <_write_r+0x1e> 8019bb0: 6023 str r3, [r4, #0] 8019bb2: bd38 pop {r3, r4, r5, pc} 8019bb4: 20013c38 .word 0x20013c38 08019bb8 <__errno>: 8019bb8: 4b01 ldr r3, [pc, #4] @ (8019bc0 <__errno+0x8>) 8019bba: 6818 ldr r0, [r3, #0] 8019bbc: 4770 bx lr 8019bbe: bf00 nop 8019bc0: 2000011c .word 0x2000011c 08019bc4 <__libc_init_array>: 8019bc4: b570 push {r4, r5, r6, lr} 8019bc6: 4b0d ldr r3, [pc, #52] @ (8019bfc <__libc_init_array+0x38>) 8019bc8: 4d0d ldr r5, [pc, #52] @ (8019c00 <__libc_init_array+0x3c>) 8019bca: 1b5b subs r3, r3, r5 8019bcc: 109c asrs r4, r3, #2 8019bce: 2600 movs r6, #0 8019bd0: 42a6 cmp r6, r4 8019bd2: d109 bne.n 8019be8 <__libc_init_array+0x24> 8019bd4: f003 fc1c bl 801d410 <_init> 8019bd8: 4d0a ldr r5, [pc, #40] @ (8019c04 <__libc_init_array+0x40>) 8019bda: 4b0b ldr r3, [pc, #44] @ (8019c08 <__libc_init_array+0x44>) 8019bdc: 1b5b subs r3, r3, r5 8019bde: 109c asrs r4, r3, #2 8019be0: 2600 movs r6, #0 8019be2: 42a6 cmp r6, r4 8019be4: d105 bne.n 8019bf2 <__libc_init_array+0x2e> 8019be6: bd70 pop {r4, r5, r6, pc} 8019be8: f855 3b04 ldr.w r3, [r5], #4 8019bec: 4798 blx r3 8019bee: 3601 adds r6, #1 8019bf0: e7ee b.n 8019bd0 <__libc_init_array+0xc> 8019bf2: f855 3b04 ldr.w r3, [r5], #4 8019bf6: 4798 blx r3 8019bf8: 3601 adds r6, #1 8019bfa: e7f2 b.n 8019be2 <__libc_init_array+0x1e> 8019bfc: 0801e0f8 .word 0x0801e0f8 8019c00: 0801e0f8 .word 0x0801e0f8 8019c04: 0801e0f8 .word 0x0801e0f8 8019c08: 0801e0fc .word 0x0801e0fc 08019c0c <__retarget_lock_init_recursive>: 8019c0c: 4770 bx lr 08019c0e <__retarget_lock_acquire_recursive>: 8019c0e: 4770 bx lr 08019c10 <__retarget_lock_release_recursive>: 8019c10: 4770 bx lr 08019c12 : 8019c12: 440a add r2, r1 8019c14: 4291 cmp r1, r2 8019c16: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8019c1a: d100 bne.n 8019c1e 8019c1c: 4770 bx lr 8019c1e: b510 push {r4, lr} 8019c20: f811 4b01 ldrb.w r4, [r1], #1 8019c24: f803 4f01 strb.w r4, [r3, #1]! 8019c28: 4291 cmp r1, r2 8019c2a: d1f9 bne.n 8019c20 8019c2c: bd10 pop {r4, pc} ... 08019c30 : 8019c30: ed9f 0a01 vldr s0, [pc, #4] @ 8019c38 8019c34: 4770 bx lr 8019c36: bf00 nop 8019c38: 7fc00000 .word 0x7fc00000 08019c3c : 8019c3c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8019c40: 6903 ldr r3, [r0, #16] 8019c42: 690c ldr r4, [r1, #16] 8019c44: 42a3 cmp r3, r4 8019c46: 4607 mov r7, r0 8019c48: db7e blt.n 8019d48 8019c4a: 3c01 subs r4, #1 8019c4c: f101 0814 add.w r8, r1, #20 8019c50: 00a3 lsls r3, r4, #2 8019c52: f100 0514 add.w r5, r0, #20 8019c56: 9300 str r3, [sp, #0] 8019c58: eb05 0384 add.w r3, r5, r4, lsl #2 8019c5c: 9301 str r3, [sp, #4] 8019c5e: f858 3024 ldr.w r3, [r8, r4, lsl #2] 8019c62: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8019c66: 3301 adds r3, #1 8019c68: 429a cmp r2, r3 8019c6a: eb08 0984 add.w r9, r8, r4, lsl #2 8019c6e: fbb2 f6f3 udiv r6, r2, r3 8019c72: d32e bcc.n 8019cd2 8019c74: f04f 0a00 mov.w sl, #0 8019c78: 46c4 mov ip, r8 8019c7a: 46ae mov lr, r5 8019c7c: 46d3 mov fp, sl 8019c7e: f85c 3b04 ldr.w r3, [ip], #4 8019c82: b298 uxth r0, r3 8019c84: fb06 a000 mla r0, r6, r0, sl 8019c88: 0c02 lsrs r2, r0, #16 8019c8a: 0c1b lsrs r3, r3, #16 8019c8c: fb06 2303 mla r3, r6, r3, r2 8019c90: f8de 2000 ldr.w r2, [lr] 8019c94: b280 uxth r0, r0 8019c96: b292 uxth r2, r2 8019c98: 1a12 subs r2, r2, r0 8019c9a: 445a add r2, fp 8019c9c: f8de 0000 ldr.w r0, [lr] 8019ca0: ea4f 4a13 mov.w sl, r3, lsr #16 8019ca4: b29b uxth r3, r3 8019ca6: ebc3 4322 rsb r3, r3, r2, asr #16 8019caa: eb03 4310 add.w r3, r3, r0, lsr #16 8019cae: b292 uxth r2, r2 8019cb0: ea42 4203 orr.w r2, r2, r3, lsl #16 8019cb4: 45e1 cmp r9, ip 8019cb6: f84e 2b04 str.w r2, [lr], #4 8019cba: ea4f 4b23 mov.w fp, r3, asr #16 8019cbe: d2de bcs.n 8019c7e 8019cc0: 9b00 ldr r3, [sp, #0] 8019cc2: 58eb ldr r3, [r5, r3] 8019cc4: b92b cbnz r3, 8019cd2 8019cc6: 9b01 ldr r3, [sp, #4] 8019cc8: 3b04 subs r3, #4 8019cca: 429d cmp r5, r3 8019ccc: 461a mov r2, r3 8019cce: d32f bcc.n 8019d30 8019cd0: 613c str r4, [r7, #16] 8019cd2: 4638 mov r0, r7 8019cd4: f001 f9de bl 801b094 <__mcmp> 8019cd8: 2800 cmp r0, #0 8019cda: db25 blt.n 8019d28 8019cdc: 4629 mov r1, r5 8019cde: 2000 movs r0, #0 8019ce0: f858 2b04 ldr.w r2, [r8], #4 8019ce4: f8d1 c000 ldr.w ip, [r1] 8019ce8: fa1f fe82 uxth.w lr, r2 8019cec: fa1f f38c uxth.w r3, ip 8019cf0: eba3 030e sub.w r3, r3, lr 8019cf4: 4403 add r3, r0 8019cf6: 0c12 lsrs r2, r2, #16 8019cf8: ebc2 4223 rsb r2, r2, r3, asr #16 8019cfc: eb02 421c add.w r2, r2, ip, lsr #16 8019d00: b29b uxth r3, r3 8019d02: ea43 4302 orr.w r3, r3, r2, lsl #16 8019d06: 45c1 cmp r9, r8 8019d08: f841 3b04 str.w r3, [r1], #4 8019d0c: ea4f 4022 mov.w r0, r2, asr #16 8019d10: d2e6 bcs.n 8019ce0 8019d12: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8019d16: eb05 0384 add.w r3, r5, r4, lsl #2 8019d1a: b922 cbnz r2, 8019d26 8019d1c: 3b04 subs r3, #4 8019d1e: 429d cmp r5, r3 8019d20: 461a mov r2, r3 8019d22: d30b bcc.n 8019d3c 8019d24: 613c str r4, [r7, #16] 8019d26: 3601 adds r6, #1 8019d28: 4630 mov r0, r6 8019d2a: b003 add sp, #12 8019d2c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8019d30: 6812 ldr r2, [r2, #0] 8019d32: 3b04 subs r3, #4 8019d34: 2a00 cmp r2, #0 8019d36: d1cb bne.n 8019cd0 8019d38: 3c01 subs r4, #1 8019d3a: e7c6 b.n 8019cca 8019d3c: 6812 ldr r2, [r2, #0] 8019d3e: 3b04 subs r3, #4 8019d40: 2a00 cmp r2, #0 8019d42: d1ef bne.n 8019d24 8019d44: 3c01 subs r4, #1 8019d46: e7ea b.n 8019d1e 8019d48: 2000 movs r0, #0 8019d4a: e7ee b.n 8019d2a 8019d4c: 0000 movs r0, r0 ... 08019d50 <_dtoa_r>: 8019d50: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8019d54: b099 sub sp, #100 @ 0x64 8019d56: ed8d 0b0e vstr d0, [sp, #56] @ 0x38 8019d5a: 920c str r2, [sp, #48] @ 0x30 8019d5c: 69c2 ldr r2, [r0, #28] 8019d5e: 9c22 ldr r4, [sp, #136] @ 0x88 8019d60: 910a str r1, [sp, #40] @ 0x28 8019d62: ec57 6b10 vmov r6, r7, d0 8019d66: 4681 mov r9, r0 8019d68: 9313 str r3, [sp, #76] @ 0x4c 8019d6a: b982 cbnz r2, 8019d8e <_dtoa_r+0x3e> 8019d6c: 2010 movs r0, #16 8019d6e: f000 fe15 bl 801a99c 8019d72: 4602 mov r2, r0 8019d74: f8c9 001c str.w r0, [r9, #28] 8019d78: b920 cbnz r0, 8019d84 <_dtoa_r+0x34> 8019d7a: 4bab ldr r3, [pc, #684] @ (801a028 <_dtoa_r+0x2d8>) 8019d7c: 21ef movs r1, #239 @ 0xef 8019d7e: 48ab ldr r0, [pc, #684] @ (801a02c <_dtoa_r+0x2dc>) 8019d80: f002 fdfa bl 801c978 <__assert_func> 8019d84: 2300 movs r3, #0 8019d86: e9c0 3301 strd r3, r3, [r0, #4] 8019d8a: 6003 str r3, [r0, #0] 8019d8c: 60c3 str r3, [r0, #12] 8019d8e: 6811 ldr r1, [r2, #0] 8019d90: b159 cbz r1, 8019daa <_dtoa_r+0x5a> 8019d92: 6852 ldr r2, [r2, #4] 8019d94: 604a str r2, [r1, #4] 8019d96: 2301 movs r3, #1 8019d98: 4093 lsls r3, r2 8019d9a: 608b str r3, [r1, #8] 8019d9c: 4648 mov r0, r9 8019d9e: f000 fef1 bl 801ab84 <_Bfree> 8019da2: f8d9 301c ldr.w r3, [r9, #28] 8019da6: 2200 movs r2, #0 8019da8: 601a str r2, [r3, #0] 8019daa: f1b7 0800 subs.w r8, r7, #0 8019dae: bfb5 itete lt 8019db0: 2301 movlt r3, #1 8019db2: 2300 movge r3, #0 8019db4: 6023 strlt r3, [r4, #0] 8019db6: 6023 strge r3, [r4, #0] 8019db8: 4b9d ldr r3, [pc, #628] @ (801a030 <_dtoa_r+0x2e0>) 8019dba: bfbc itt lt 8019dbc: f028 4800 biclt.w r8, r8, #2147483648 @ 0x80000000 8019dc0: f8cd 803c strlt.w r8, [sp, #60] @ 0x3c 8019dc4: ea33 0308 bics.w r3, r3, r8 8019dc8: d11a bne.n 8019e00 <_dtoa_r+0xb0> 8019dca: 9a13 ldr r2, [sp, #76] @ 0x4c 8019dcc: f3c8 0813 ubfx r8, r8, #0, #20 8019dd0: f242 730f movw r3, #9999 @ 0x270f 8019dd4: ea58 0806 orrs.w r8, r8, r6 8019dd8: 6013 str r3, [r2, #0] 8019dda: f000 8568 beq.w 801a8ae <_dtoa_r+0xb5e> 8019dde: 9b23 ldr r3, [sp, #140] @ 0x8c 8019de0: b953 cbnz r3, 8019df8 <_dtoa_r+0xa8> 8019de2: 4b94 ldr r3, [pc, #592] @ (801a034 <_dtoa_r+0x2e4>) 8019de4: e021 b.n 8019e2a <_dtoa_r+0xda> 8019de6: 4b94 ldr r3, [pc, #592] @ (801a038 <_dtoa_r+0x2e8>) 8019de8: 9300 str r3, [sp, #0] 8019dea: 3308 adds r3, #8 8019dec: 9a23 ldr r2, [sp, #140] @ 0x8c 8019dee: 6013 str r3, [r2, #0] 8019df0: 9800 ldr r0, [sp, #0] 8019df2: b019 add sp, #100 @ 0x64 8019df4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8019df8: 4b8e ldr r3, [pc, #568] @ (801a034 <_dtoa_r+0x2e4>) 8019dfa: 9300 str r3, [sp, #0] 8019dfc: 3303 adds r3, #3 8019dfe: e7f5 b.n 8019dec <_dtoa_r+0x9c> 8019e00: ed9d 7b0e vldr d7, [sp, #56] @ 0x38 8019e04: 2200 movs r2, #0 8019e06: ec51 0b17 vmov r0, r1, d7 8019e0a: 2300 movs r3, #0 8019e0c: ed8d 7b06 vstr d7, [sp, #24] 8019e10: f7e6 fe32 bl 8000a78 <__aeabi_dcmpeq> 8019e14: 4682 mov sl, r0 8019e16: b150 cbz r0, 8019e2e <_dtoa_r+0xde> 8019e18: 9a13 ldr r2, [sp, #76] @ 0x4c 8019e1a: 2301 movs r3, #1 8019e1c: 6013 str r3, [r2, #0] 8019e1e: 9b23 ldr r3, [sp, #140] @ 0x8c 8019e20: b113 cbz r3, 8019e28 <_dtoa_r+0xd8> 8019e22: 9a23 ldr r2, [sp, #140] @ 0x8c 8019e24: 4b85 ldr r3, [pc, #532] @ (801a03c <_dtoa_r+0x2ec>) 8019e26: 6013 str r3, [r2, #0] 8019e28: 4b85 ldr r3, [pc, #532] @ (801a040 <_dtoa_r+0x2f0>) 8019e2a: 9300 str r3, [sp, #0] 8019e2c: e7e0 b.n 8019df0 <_dtoa_r+0xa0> 8019e2e: ed9d 0b06 vldr d0, [sp, #24] 8019e32: aa16 add r2, sp, #88 @ 0x58 8019e34: a917 add r1, sp, #92 @ 0x5c 8019e36: 4648 mov r0, r9 8019e38: f001 fa50 bl 801b2dc <__d2b> 8019e3c: ea5f 5418 movs.w r4, r8, lsr #20 8019e40: 9d16 ldr r5, [sp, #88] @ 0x58 8019e42: 9001 str r0, [sp, #4] 8019e44: d079 beq.n 8019f3a <_dtoa_r+0x1ea> 8019e46: 9b07 ldr r3, [sp, #28] 8019e48: f8cd a050 str.w sl, [sp, #80] @ 0x50 8019e4c: f3c3 0313 ubfx r3, r3, #0, #20 8019e50: e9dd 0106 ldrd r0, r1, [sp, #24] 8019e54: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 8019e58: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 8019e5c: f2a4 34ff subw r4, r4, #1023 @ 0x3ff 8019e60: 4619 mov r1, r3 8019e62: 2200 movs r2, #0 8019e64: 4b77 ldr r3, [pc, #476] @ (801a044 <_dtoa_r+0x2f4>) 8019e66: f7e6 f9e7 bl 8000238 <__aeabi_dsub> 8019e6a: a369 add r3, pc, #420 @ (adr r3, 801a010 <_dtoa_r+0x2c0>) 8019e6c: e9d3 2300 ldrd r2, r3, [r3] 8019e70: f7e6 fb9a bl 80005a8 <__aeabi_dmul> 8019e74: a368 add r3, pc, #416 @ (adr r3, 801a018 <_dtoa_r+0x2c8>) 8019e76: e9d3 2300 ldrd r2, r3, [r3] 8019e7a: f7e6 f9df bl 800023c <__adddf3> 8019e7e: 4606 mov r6, r0 8019e80: 4620 mov r0, r4 8019e82: 460f mov r7, r1 8019e84: f7e6 fb26 bl 80004d4 <__aeabi_i2d> 8019e88: a365 add r3, pc, #404 @ (adr r3, 801a020 <_dtoa_r+0x2d0>) 8019e8a: e9d3 2300 ldrd r2, r3, [r3] 8019e8e: f7e6 fb8b bl 80005a8 <__aeabi_dmul> 8019e92: 4602 mov r2, r0 8019e94: 460b mov r3, r1 8019e96: 4630 mov r0, r6 8019e98: 4639 mov r1, r7 8019e9a: f7e6 f9cf bl 800023c <__adddf3> 8019e9e: 4606 mov r6, r0 8019ea0: 460f mov r7, r1 8019ea2: f7e6 fe31 bl 8000b08 <__aeabi_d2iz> 8019ea6: 2200 movs r2, #0 8019ea8: 4680 mov r8, r0 8019eaa: 2300 movs r3, #0 8019eac: 4630 mov r0, r6 8019eae: 4639 mov r1, r7 8019eb0: f7e6 fdec bl 8000a8c <__aeabi_dcmplt> 8019eb4: b148 cbz r0, 8019eca <_dtoa_r+0x17a> 8019eb6: 4640 mov r0, r8 8019eb8: f7e6 fb0c bl 80004d4 <__aeabi_i2d> 8019ebc: 4632 mov r2, r6 8019ebe: 463b mov r3, r7 8019ec0: f7e6 fdda bl 8000a78 <__aeabi_dcmpeq> 8019ec4: b908 cbnz r0, 8019eca <_dtoa_r+0x17a> 8019ec6: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8019eca: f1b8 0f16 cmp.w r8, #22 8019ece: d851 bhi.n 8019f74 <_dtoa_r+0x224> 8019ed0: 4b5d ldr r3, [pc, #372] @ (801a048 <_dtoa_r+0x2f8>) 8019ed2: eb03 03c8 add.w r3, r3, r8, lsl #3 8019ed6: e9d3 2300 ldrd r2, r3, [r3] 8019eda: e9dd 0106 ldrd r0, r1, [sp, #24] 8019ede: f7e6 fdd5 bl 8000a8c <__aeabi_dcmplt> 8019ee2: 2800 cmp r0, #0 8019ee4: d048 beq.n 8019f78 <_dtoa_r+0x228> 8019ee6: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 8019eea: 2300 movs r3, #0 8019eec: 9312 str r3, [sp, #72] @ 0x48 8019eee: 1b2d subs r5, r5, r4 8019ef0: 1e6b subs r3, r5, #1 8019ef2: 9308 str r3, [sp, #32] 8019ef4: bf43 ittte mi 8019ef6: 2300 movmi r3, #0 8019ef8: f1c5 0701 rsbmi r7, r5, #1 8019efc: 9308 strmi r3, [sp, #32] 8019efe: 2700 movpl r7, #0 8019f00: f1b8 0f00 cmp.w r8, #0 8019f04: db3a blt.n 8019f7c <_dtoa_r+0x22c> 8019f06: 9b08 ldr r3, [sp, #32] 8019f08: f8cd 8034 str.w r8, [sp, #52] @ 0x34 8019f0c: 4443 add r3, r8 8019f0e: 9308 str r3, [sp, #32] 8019f10: 2300 movs r3, #0 8019f12: 9309 str r3, [sp, #36] @ 0x24 8019f14: 9b0a ldr r3, [sp, #40] @ 0x28 8019f16: 2b09 cmp r3, #9 8019f18: d862 bhi.n 8019fe0 <_dtoa_r+0x290> 8019f1a: 2b05 cmp r3, #5 8019f1c: bfc4 itt gt 8019f1e: 3b04 subgt r3, #4 8019f20: 930a strgt r3, [sp, #40] @ 0x28 8019f22: 9b0a ldr r3, [sp, #40] @ 0x28 8019f24: f1a3 0302 sub.w r3, r3, #2 8019f28: bfcc ite gt 8019f2a: 2400 movgt r4, #0 8019f2c: 2401 movle r4, #1 8019f2e: 2b03 cmp r3, #3 8019f30: d862 bhi.n 8019ff8 <_dtoa_r+0x2a8> 8019f32: e8df f003 tbb [pc, r3] 8019f36: 5351 .short 0x5351 8019f38: 2b36 .short 0x2b36 8019f3a: 9c17 ldr r4, [sp, #92] @ 0x5c 8019f3c: 442c add r4, r5 8019f3e: f204 4332 addw r3, r4, #1074 @ 0x432 8019f42: 2b20 cmp r3, #32 8019f44: bfc1 itttt gt 8019f46: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 8019f4a: fa08 f803 lslgt.w r8, r8, r3 8019f4e: f204 4312 addwgt r3, r4, #1042 @ 0x412 8019f52: fa26 f303 lsrgt.w r3, r6, r3 8019f56: bfd6 itet le 8019f58: f1c3 0320 rsble r3, r3, #32 8019f5c: ea48 0003 orrgt.w r0, r8, r3 8019f60: fa06 f003 lslle.w r0, r6, r3 8019f64: f7e6 faa6 bl 80004b4 <__aeabi_ui2d> 8019f68: 2201 movs r2, #1 8019f6a: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 8019f6e: 3c01 subs r4, #1 8019f70: 9214 str r2, [sp, #80] @ 0x50 8019f72: e775 b.n 8019e60 <_dtoa_r+0x110> 8019f74: 2301 movs r3, #1 8019f76: e7b9 b.n 8019eec <_dtoa_r+0x19c> 8019f78: 9012 str r0, [sp, #72] @ 0x48 8019f7a: e7b8 b.n 8019eee <_dtoa_r+0x19e> 8019f7c: f1c8 0300 rsb r3, r8, #0 8019f80: 9309 str r3, [sp, #36] @ 0x24 8019f82: 2300 movs r3, #0 8019f84: eba7 0708 sub.w r7, r7, r8 8019f88: 930d str r3, [sp, #52] @ 0x34 8019f8a: e7c3 b.n 8019f14 <_dtoa_r+0x1c4> 8019f8c: 2301 movs r3, #1 8019f8e: 930b str r3, [sp, #44] @ 0x2c 8019f90: 9b0c ldr r3, [sp, #48] @ 0x30 8019f92: 4443 add r3, r8 8019f94: 9305 str r3, [sp, #20] 8019f96: 3301 adds r3, #1 8019f98: 2b01 cmp r3, #1 8019f9a: 9304 str r3, [sp, #16] 8019f9c: bfb8 it lt 8019f9e: 2301 movlt r3, #1 8019fa0: e006 b.n 8019fb0 <_dtoa_r+0x260> 8019fa2: 2301 movs r3, #1 8019fa4: 930b str r3, [sp, #44] @ 0x2c 8019fa6: 9b0c ldr r3, [sp, #48] @ 0x30 8019fa8: 2b00 cmp r3, #0 8019faa: dd28 ble.n 8019ffe <_dtoa_r+0x2ae> 8019fac: e9cd 3304 strd r3, r3, [sp, #16] 8019fb0: f8d9 001c ldr.w r0, [r9, #28] 8019fb4: 2100 movs r1, #0 8019fb6: 2204 movs r2, #4 8019fb8: f102 0514 add.w r5, r2, #20 8019fbc: 429d cmp r5, r3 8019fbe: d923 bls.n 801a008 <_dtoa_r+0x2b8> 8019fc0: 6041 str r1, [r0, #4] 8019fc2: 4648 mov r0, r9 8019fc4: f000 fda0 bl 801ab08 <_Balloc> 8019fc8: 9000 str r0, [sp, #0] 8019fca: 2800 cmp r0, #0 8019fcc: d140 bne.n 801a050 <_dtoa_r+0x300> 8019fce: 4b1f ldr r3, [pc, #124] @ (801a04c <_dtoa_r+0x2fc>) 8019fd0: 4602 mov r2, r0 8019fd2: f240 11af movw r1, #431 @ 0x1af 8019fd6: e6d2 b.n 8019d7e <_dtoa_r+0x2e> 8019fd8: 2300 movs r3, #0 8019fda: e7e3 b.n 8019fa4 <_dtoa_r+0x254> 8019fdc: 2300 movs r3, #0 8019fde: e7d6 b.n 8019f8e <_dtoa_r+0x23e> 8019fe0: 2401 movs r4, #1 8019fe2: 2300 movs r3, #0 8019fe4: e9cd 340a strd r3, r4, [sp, #40] @ 0x28 8019fe8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8019fec: e9cd 3304 strd r3, r3, [sp, #16] 8019ff0: 2200 movs r2, #0 8019ff2: 2312 movs r3, #18 8019ff4: 920c str r2, [sp, #48] @ 0x30 8019ff6: e7db b.n 8019fb0 <_dtoa_r+0x260> 8019ff8: 2301 movs r3, #1 8019ffa: 930b str r3, [sp, #44] @ 0x2c 8019ffc: e7f4 b.n 8019fe8 <_dtoa_r+0x298> 8019ffe: 2301 movs r3, #1 801a000: e9cd 3304 strd r3, r3, [sp, #16] 801a004: 461a mov r2, r3 801a006: e7f5 b.n 8019ff4 <_dtoa_r+0x2a4> 801a008: 3101 adds r1, #1 801a00a: 0052 lsls r2, r2, #1 801a00c: e7d4 b.n 8019fb8 <_dtoa_r+0x268> 801a00e: bf00 nop 801a010: 636f4361 .word 0x636f4361 801a014: 3fd287a7 .word 0x3fd287a7 801a018: 8b60c8b3 .word 0x8b60c8b3 801a01c: 3fc68a28 .word 0x3fc68a28 801a020: 509f79fb .word 0x509f79fb 801a024: 3fd34413 .word 0x3fd34413 801a028: 0801dcf6 .word 0x0801dcf6 801a02c: 0801dd0d .word 0x0801dd0d 801a030: 7ff00000 .word 0x7ff00000 801a034: 0801dcf2 .word 0x0801dcf2 801a038: 0801dce9 .word 0x0801dce9 801a03c: 0801dcc1 .word 0x0801dcc1 801a040: 0801dcc0 .word 0x0801dcc0 801a044: 3ff80000 .word 0x3ff80000 801a048: 0801dec0 .word 0x0801dec0 801a04c: 0801dd65 .word 0x0801dd65 801a050: f8d9 301c ldr.w r3, [r9, #28] 801a054: 9a00 ldr r2, [sp, #0] 801a056: 601a str r2, [r3, #0] 801a058: 9b04 ldr r3, [sp, #16] 801a05a: 2b0e cmp r3, #14 801a05c: f200 80a1 bhi.w 801a1a2 <_dtoa_r+0x452> 801a060: 2c00 cmp r4, #0 801a062: f000 809e beq.w 801a1a2 <_dtoa_r+0x452> 801a066: f1b8 0f00 cmp.w r8, #0 801a06a: dd36 ble.n 801a0da <_dtoa_r+0x38a> 801a06c: 4b9e ldr r3, [pc, #632] @ (801a2e8 <_dtoa_r+0x598>) 801a06e: f008 020f and.w r2, r8, #15 801a072: eb03 03c2 add.w r3, r3, r2, lsl #3 801a076: f418 7f80 tst.w r8, #256 @ 0x100 801a07a: e9d3 ab00 ldrd sl, fp, [r3] 801a07e: ea4f 1528 mov.w r5, r8, asr #4 801a082: d016 beq.n 801a0b2 <_dtoa_r+0x362> 801a084: 4b99 ldr r3, [pc, #612] @ (801a2ec <_dtoa_r+0x59c>) 801a086: e9dd 0106 ldrd r0, r1, [sp, #24] 801a08a: e9d3 2308 ldrd r2, r3, [r3, #32] 801a08e: f7e6 fbb5 bl 80007fc <__aeabi_ddiv> 801a092: e9cd 0102 strd r0, r1, [sp, #8] 801a096: f005 050f and.w r5, r5, #15 801a09a: 2403 movs r4, #3 801a09c: 4e93 ldr r6, [pc, #588] @ (801a2ec <_dtoa_r+0x59c>) 801a09e: b975 cbnz r5, 801a0be <_dtoa_r+0x36e> 801a0a0: e9dd 0102 ldrd r0, r1, [sp, #8] 801a0a4: 4652 mov r2, sl 801a0a6: 465b mov r3, fp 801a0a8: f7e6 fba8 bl 80007fc <__aeabi_ddiv> 801a0ac: 4682 mov sl, r0 801a0ae: 468b mov fp, r1 801a0b0: e02d b.n 801a10e <_dtoa_r+0x3be> 801a0b2: ed9d 7b06 vldr d7, [sp, #24] 801a0b6: 2402 movs r4, #2 801a0b8: ed8d 7b02 vstr d7, [sp, #8] 801a0bc: e7ee b.n 801a09c <_dtoa_r+0x34c> 801a0be: 07e9 lsls r1, r5, #31 801a0c0: d508 bpl.n 801a0d4 <_dtoa_r+0x384> 801a0c2: 4650 mov r0, sl 801a0c4: 4659 mov r1, fp 801a0c6: e9d6 2300 ldrd r2, r3, [r6] 801a0ca: f7e6 fa6d bl 80005a8 <__aeabi_dmul> 801a0ce: 3401 adds r4, #1 801a0d0: 4682 mov sl, r0 801a0d2: 468b mov fp, r1 801a0d4: 106d asrs r5, r5, #1 801a0d6: 3608 adds r6, #8 801a0d8: e7e1 b.n 801a09e <_dtoa_r+0x34e> 801a0da: f000 80ad beq.w 801a238 <_dtoa_r+0x4e8> 801a0de: f1c8 0500 rsb r5, r8, #0 801a0e2: 4b81 ldr r3, [pc, #516] @ (801a2e8 <_dtoa_r+0x598>) 801a0e4: 4e81 ldr r6, [pc, #516] @ (801a2ec <_dtoa_r+0x59c>) 801a0e6: f005 020f and.w r2, r5, #15 801a0ea: eb03 03c2 add.w r3, r3, r2, lsl #3 801a0ee: e9d3 2300 ldrd r2, r3, [r3] 801a0f2: e9dd 0106 ldrd r0, r1, [sp, #24] 801a0f6: f7e6 fa57 bl 80005a8 <__aeabi_dmul> 801a0fa: 112d asrs r5, r5, #4 801a0fc: 4682 mov sl, r0 801a0fe: 468b mov fp, r1 801a100: 2300 movs r3, #0 801a102: 2402 movs r4, #2 801a104: 2d00 cmp r5, #0 801a106: f040 808c bne.w 801a222 <_dtoa_r+0x4d2> 801a10a: 2b00 cmp r3, #0 801a10c: d1ce bne.n 801a0ac <_dtoa_r+0x35c> 801a10e: 9b12 ldr r3, [sp, #72] @ 0x48 801a110: 2b00 cmp r3, #0 801a112: f000 8095 beq.w 801a240 <_dtoa_r+0x4f0> 801a116: 4b76 ldr r3, [pc, #472] @ (801a2f0 <_dtoa_r+0x5a0>) 801a118: 2200 movs r2, #0 801a11a: 4650 mov r0, sl 801a11c: 4659 mov r1, fp 801a11e: f7e6 fcb5 bl 8000a8c <__aeabi_dcmplt> 801a122: 2800 cmp r0, #0 801a124: f000 808c beq.w 801a240 <_dtoa_r+0x4f0> 801a128: 9b04 ldr r3, [sp, #16] 801a12a: 2b00 cmp r3, #0 801a12c: f000 8088 beq.w 801a240 <_dtoa_r+0x4f0> 801a130: 9b05 ldr r3, [sp, #20] 801a132: 2b00 cmp r3, #0 801a134: dd35 ble.n 801a1a2 <_dtoa_r+0x452> 801a136: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff 801a13a: 9302 str r3, [sp, #8] 801a13c: 4650 mov r0, sl 801a13e: 4659 mov r1, fp 801a140: 4b6c ldr r3, [pc, #432] @ (801a2f4 <_dtoa_r+0x5a4>) 801a142: 2200 movs r2, #0 801a144: f7e6 fa30 bl 80005a8 <__aeabi_dmul> 801a148: 9e05 ldr r6, [sp, #20] 801a14a: 4682 mov sl, r0 801a14c: 468b mov fp, r1 801a14e: 3401 adds r4, #1 801a150: 4620 mov r0, r4 801a152: f7e6 f9bf bl 80004d4 <__aeabi_i2d> 801a156: 4652 mov r2, sl 801a158: 465b mov r3, fp 801a15a: f7e6 fa25 bl 80005a8 <__aeabi_dmul> 801a15e: 4b66 ldr r3, [pc, #408] @ (801a2f8 <_dtoa_r+0x5a8>) 801a160: 2200 movs r2, #0 801a162: f7e6 f86b bl 800023c <__adddf3> 801a166: 4604 mov r4, r0 801a168: f1a1 7550 sub.w r5, r1, #54525952 @ 0x3400000 801a16c: e9cd 4510 strd r4, r5, [sp, #64] @ 0x40 801a170: 2e00 cmp r6, #0 801a172: d169 bne.n 801a248 <_dtoa_r+0x4f8> 801a174: 4b61 ldr r3, [pc, #388] @ (801a2fc <_dtoa_r+0x5ac>) 801a176: 2200 movs r2, #0 801a178: 4650 mov r0, sl 801a17a: 4659 mov r1, fp 801a17c: f7e6 f85c bl 8000238 <__aeabi_dsub> 801a180: 4622 mov r2, r4 801a182: 462b mov r3, r5 801a184: 4682 mov sl, r0 801a186: 468b mov fp, r1 801a188: f7e6 fc9e bl 8000ac8 <__aeabi_dcmpgt> 801a18c: 2800 cmp r0, #0 801a18e: f040 8294 bne.w 801a6ba <_dtoa_r+0x96a> 801a192: 4622 mov r2, r4 801a194: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 801a198: 4650 mov r0, sl 801a19a: 4659 mov r1, fp 801a19c: f7e6 fc76 bl 8000a8c <__aeabi_dcmplt> 801a1a0: bb20 cbnz r0, 801a1ec <_dtoa_r+0x49c> 801a1a2: 9b17 ldr r3, [sp, #92] @ 0x5c 801a1a4: 2b00 cmp r3, #0 801a1a6: f2c0 8160 blt.w 801a46a <_dtoa_r+0x71a> 801a1aa: f1b8 0f0e cmp.w r8, #14 801a1ae: f300 815c bgt.w 801a46a <_dtoa_r+0x71a> 801a1b2: 4b4d ldr r3, [pc, #308] @ (801a2e8 <_dtoa_r+0x598>) 801a1b4: eb03 03c8 add.w r3, r3, r8, lsl #3 801a1b8: e9d3 ab00 ldrd sl, fp, [r3] 801a1bc: 9b0c ldr r3, [sp, #48] @ 0x30 801a1be: 2b00 cmp r3, #0 801a1c0: f280 80ee bge.w 801a3a0 <_dtoa_r+0x650> 801a1c4: 9b04 ldr r3, [sp, #16] 801a1c6: 2b00 cmp r3, #0 801a1c8: f300 80ea bgt.w 801a3a0 <_dtoa_r+0x650> 801a1cc: d10e bne.n 801a1ec <_dtoa_r+0x49c> 801a1ce: 4b4b ldr r3, [pc, #300] @ (801a2fc <_dtoa_r+0x5ac>) 801a1d0: 2200 movs r2, #0 801a1d2: 4650 mov r0, sl 801a1d4: 4659 mov r1, fp 801a1d6: f7e6 f9e7 bl 80005a8 <__aeabi_dmul> 801a1da: 4602 mov r2, r0 801a1dc: 460b mov r3, r1 801a1de: e9dd 0106 ldrd r0, r1, [sp, #24] 801a1e2: f7e6 fc5d bl 8000aa0 <__aeabi_dcmple> 801a1e6: 2800 cmp r0, #0 801a1e8: f000 826a beq.w 801a6c0 <_dtoa_r+0x970> 801a1ec: 2500 movs r5, #0 801a1ee: 462c mov r4, r5 801a1f0: 9b0c ldr r3, [sp, #48] @ 0x30 801a1f2: 9e00 ldr r6, [sp, #0] 801a1f4: 43db mvns r3, r3 801a1f6: 9302 str r3, [sp, #8] 801a1f8: 4627 mov r7, r4 801a1fa: 2400 movs r4, #0 801a1fc: 4629 mov r1, r5 801a1fe: 4648 mov r0, r9 801a200: f000 fcc0 bl 801ab84 <_Bfree> 801a204: 2f00 cmp r7, #0 801a206: f000 80c1 beq.w 801a38c <_dtoa_r+0x63c> 801a20a: b12c cbz r4, 801a218 <_dtoa_r+0x4c8> 801a20c: 42bc cmp r4, r7 801a20e: d003 beq.n 801a218 <_dtoa_r+0x4c8> 801a210: 4621 mov r1, r4 801a212: 4648 mov r0, r9 801a214: f000 fcb6 bl 801ab84 <_Bfree> 801a218: 4639 mov r1, r7 801a21a: 4648 mov r0, r9 801a21c: f000 fcb2 bl 801ab84 <_Bfree> 801a220: e0b4 b.n 801a38c <_dtoa_r+0x63c> 801a222: 07ea lsls r2, r5, #31 801a224: d505 bpl.n 801a232 <_dtoa_r+0x4e2> 801a226: e9d6 2300 ldrd r2, r3, [r6] 801a22a: f7e6 f9bd bl 80005a8 <__aeabi_dmul> 801a22e: 3401 adds r4, #1 801a230: 2301 movs r3, #1 801a232: 106d asrs r5, r5, #1 801a234: 3608 adds r6, #8 801a236: e765 b.n 801a104 <_dtoa_r+0x3b4> 801a238: e9dd ab06 ldrd sl, fp, [sp, #24] 801a23c: 2402 movs r4, #2 801a23e: e766 b.n 801a10e <_dtoa_r+0x3be> 801a240: 9e04 ldr r6, [sp, #16] 801a242: f8cd 8008 str.w r8, [sp, #8] 801a246: e783 b.n 801a150 <_dtoa_r+0x400> 801a248: 4b27 ldr r3, [pc, #156] @ (801a2e8 <_dtoa_r+0x598>) 801a24a: eb03 03c6 add.w r3, r3, r6, lsl #3 801a24e: e953 0102 ldrd r0, r1, [r3, #-8] 801a252: 9b0b ldr r3, [sp, #44] @ 0x2c 801a254: 2b00 cmp r3, #0 801a256: d055 beq.n 801a304 <_dtoa_r+0x5b4> 801a258: 4602 mov r2, r0 801a25a: 460b mov r3, r1 801a25c: 2000 movs r0, #0 801a25e: 4928 ldr r1, [pc, #160] @ (801a300 <_dtoa_r+0x5b0>) 801a260: f7e6 facc bl 80007fc <__aeabi_ddiv> 801a264: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801a268: f7e5 ffe6 bl 8000238 <__aeabi_dsub> 801a26c: 9b00 ldr r3, [sp, #0] 801a26e: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801a272: 199d adds r5, r3, r6 801a274: 461e mov r6, r3 801a276: 4659 mov r1, fp 801a278: 4650 mov r0, sl 801a27a: f7e6 fc45 bl 8000b08 <__aeabi_d2iz> 801a27e: 4604 mov r4, r0 801a280: f7e6 f928 bl 80004d4 <__aeabi_i2d> 801a284: 4602 mov r2, r0 801a286: 460b mov r3, r1 801a288: 4650 mov r0, sl 801a28a: 4659 mov r1, fp 801a28c: f7e5 ffd4 bl 8000238 <__aeabi_dsub> 801a290: 3430 adds r4, #48 @ 0x30 801a292: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801a296: f806 4b01 strb.w r4, [r6], #1 801a29a: 4682 mov sl, r0 801a29c: 468b mov fp, r1 801a29e: f7e6 fbf5 bl 8000a8c <__aeabi_dcmplt> 801a2a2: 2800 cmp r0, #0 801a2a4: d172 bne.n 801a38c <_dtoa_r+0x63c> 801a2a6: 4652 mov r2, sl 801a2a8: 465b mov r3, fp 801a2aa: 4911 ldr r1, [pc, #68] @ (801a2f0 <_dtoa_r+0x5a0>) 801a2ac: 2000 movs r0, #0 801a2ae: f7e5 ffc3 bl 8000238 <__aeabi_dsub> 801a2b2: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801a2b6: f7e6 fbe9 bl 8000a8c <__aeabi_dcmplt> 801a2ba: 2800 cmp r0, #0 801a2bc: f040 80b6 bne.w 801a42c <_dtoa_r+0x6dc> 801a2c0: 42ae cmp r6, r5 801a2c2: f43f af6e beq.w 801a1a2 <_dtoa_r+0x452> 801a2c6: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 801a2ca: 4b0a ldr r3, [pc, #40] @ (801a2f4 <_dtoa_r+0x5a4>) 801a2cc: 2200 movs r2, #0 801a2ce: f7e6 f96b bl 80005a8 <__aeabi_dmul> 801a2d2: 4b08 ldr r3, [pc, #32] @ (801a2f4 <_dtoa_r+0x5a4>) 801a2d4: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801a2d8: 2200 movs r2, #0 801a2da: 4650 mov r0, sl 801a2dc: 4659 mov r1, fp 801a2de: f7e6 f963 bl 80005a8 <__aeabi_dmul> 801a2e2: 4682 mov sl, r0 801a2e4: 468b mov fp, r1 801a2e6: e7c6 b.n 801a276 <_dtoa_r+0x526> 801a2e8: 0801dec0 .word 0x0801dec0 801a2ec: 0801de98 .word 0x0801de98 801a2f0: 3ff00000 .word 0x3ff00000 801a2f4: 40240000 .word 0x40240000 801a2f8: 401c0000 .word 0x401c0000 801a2fc: 40140000 .word 0x40140000 801a300: 3fe00000 .word 0x3fe00000 801a304: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801a308: f7e6 f94e bl 80005a8 <__aeabi_dmul> 801a30c: 9b00 ldr r3, [sp, #0] 801a30e: 9d00 ldr r5, [sp, #0] 801a310: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801a314: 4433 add r3, r6 801a316: 9315 str r3, [sp, #84] @ 0x54 801a318: 4659 mov r1, fp 801a31a: 4650 mov r0, sl 801a31c: f7e6 fbf4 bl 8000b08 <__aeabi_d2iz> 801a320: 4604 mov r4, r0 801a322: f7e6 f8d7 bl 80004d4 <__aeabi_i2d> 801a326: 3430 adds r4, #48 @ 0x30 801a328: 460b mov r3, r1 801a32a: 4602 mov r2, r0 801a32c: 4659 mov r1, fp 801a32e: 4650 mov r0, sl 801a330: f7e5 ff82 bl 8000238 <__aeabi_dsub> 801a334: f805 4b01 strb.w r4, [r5], #1 801a338: 9b15 ldr r3, [sp, #84] @ 0x54 801a33a: 429d cmp r5, r3 801a33c: 4682 mov sl, r0 801a33e: 468b mov fp, r1 801a340: d127 bne.n 801a392 <_dtoa_r+0x642> 801a342: 9b00 ldr r3, [sp, #0] 801a344: 2200 movs r2, #0 801a346: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 801a34a: 441e add r6, r3 801a34c: 4bb3 ldr r3, [pc, #716] @ (801a61c <_dtoa_r+0x8cc>) 801a34e: f7e5 ff75 bl 800023c <__adddf3> 801a352: 4602 mov r2, r0 801a354: 460b mov r3, r1 801a356: 4650 mov r0, sl 801a358: 4659 mov r1, fp 801a35a: f7e6 fbb5 bl 8000ac8 <__aeabi_dcmpgt> 801a35e: 2800 cmp r0, #0 801a360: d164 bne.n 801a42c <_dtoa_r+0x6dc> 801a362: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801a366: 49ad ldr r1, [pc, #692] @ (801a61c <_dtoa_r+0x8cc>) 801a368: 2000 movs r0, #0 801a36a: f7e5 ff65 bl 8000238 <__aeabi_dsub> 801a36e: 4602 mov r2, r0 801a370: 460b mov r3, r1 801a372: 4650 mov r0, sl 801a374: 4659 mov r1, fp 801a376: f7e6 fb89 bl 8000a8c <__aeabi_dcmplt> 801a37a: 2800 cmp r0, #0 801a37c: f43f af11 beq.w 801a1a2 <_dtoa_r+0x452> 801a380: 4633 mov r3, r6 801a382: f816 2d01 ldrb.w r2, [r6, #-1]! 801a386: 2a30 cmp r2, #48 @ 0x30 801a388: d0fa beq.n 801a380 <_dtoa_r+0x630> 801a38a: 461e mov r6, r3 801a38c: f8dd 8008 ldr.w r8, [sp, #8] 801a390: e03a b.n 801a408 <_dtoa_r+0x6b8> 801a392: 4ba3 ldr r3, [pc, #652] @ (801a620 <_dtoa_r+0x8d0>) 801a394: 2200 movs r2, #0 801a396: f7e6 f907 bl 80005a8 <__aeabi_dmul> 801a39a: 4682 mov sl, r0 801a39c: 468b mov fp, r1 801a39e: e7bb b.n 801a318 <_dtoa_r+0x5c8> 801a3a0: 9e00 ldr r6, [sp, #0] 801a3a2: 4652 mov r2, sl 801a3a4: 465b mov r3, fp 801a3a6: e9dd 0106 ldrd r0, r1, [sp, #24] 801a3aa: f7e6 fa27 bl 80007fc <__aeabi_ddiv> 801a3ae: f7e6 fbab bl 8000b08 <__aeabi_d2iz> 801a3b2: 4607 mov r7, r0 801a3b4: f7e6 f88e bl 80004d4 <__aeabi_i2d> 801a3b8: 4652 mov r2, sl 801a3ba: 465b mov r3, fp 801a3bc: f7e6 f8f4 bl 80005a8 <__aeabi_dmul> 801a3c0: 4602 mov r2, r0 801a3c2: 460b mov r3, r1 801a3c4: e9dd 0106 ldrd r0, r1, [sp, #24] 801a3c8: f7e5 ff36 bl 8000238 <__aeabi_dsub> 801a3cc: f107 0c30 add.w ip, r7, #48 @ 0x30 801a3d0: 9c00 ldr r4, [sp, #0] 801a3d2: f806 cb01 strb.w ip, [r6], #1 801a3d6: eba6 0c04 sub.w ip, r6, r4 801a3da: 9c04 ldr r4, [sp, #16] 801a3dc: 4564 cmp r4, ip 801a3de: 4602 mov r2, r0 801a3e0: 460b mov r3, r1 801a3e2: d133 bne.n 801a44c <_dtoa_r+0x6fc> 801a3e4: f7e5 ff2a bl 800023c <__adddf3> 801a3e8: 4652 mov r2, sl 801a3ea: 465b mov r3, fp 801a3ec: 4604 mov r4, r0 801a3ee: 460d mov r5, r1 801a3f0: f7e6 fb6a bl 8000ac8 <__aeabi_dcmpgt> 801a3f4: b9c0 cbnz r0, 801a428 <_dtoa_r+0x6d8> 801a3f6: 4652 mov r2, sl 801a3f8: 465b mov r3, fp 801a3fa: 4620 mov r0, r4 801a3fc: 4629 mov r1, r5 801a3fe: f7e6 fb3b bl 8000a78 <__aeabi_dcmpeq> 801a402: b108 cbz r0, 801a408 <_dtoa_r+0x6b8> 801a404: 07fb lsls r3, r7, #31 801a406: d40f bmi.n 801a428 <_dtoa_r+0x6d8> 801a408: 9901 ldr r1, [sp, #4] 801a40a: 4648 mov r0, r9 801a40c: f000 fbba bl 801ab84 <_Bfree> 801a410: 2300 movs r3, #0 801a412: 9a13 ldr r2, [sp, #76] @ 0x4c 801a414: 7033 strb r3, [r6, #0] 801a416: f108 0301 add.w r3, r8, #1 801a41a: 6013 str r3, [r2, #0] 801a41c: 9b23 ldr r3, [sp, #140] @ 0x8c 801a41e: 2b00 cmp r3, #0 801a420: f43f ace6 beq.w 8019df0 <_dtoa_r+0xa0> 801a424: 601e str r6, [r3, #0] 801a426: e4e3 b.n 8019df0 <_dtoa_r+0xa0> 801a428: f8cd 8008 str.w r8, [sp, #8] 801a42c: 4633 mov r3, r6 801a42e: 461e mov r6, r3 801a430: f813 2d01 ldrb.w r2, [r3, #-1]! 801a434: 2a39 cmp r2, #57 @ 0x39 801a436: d106 bne.n 801a446 <_dtoa_r+0x6f6> 801a438: 9a00 ldr r2, [sp, #0] 801a43a: 429a cmp r2, r3 801a43c: d1f7 bne.n 801a42e <_dtoa_r+0x6de> 801a43e: 9a02 ldr r2, [sp, #8] 801a440: 3201 adds r2, #1 801a442: 9202 str r2, [sp, #8] 801a444: 2230 movs r2, #48 @ 0x30 801a446: 3201 adds r2, #1 801a448: 701a strb r2, [r3, #0] 801a44a: e79f b.n 801a38c <_dtoa_r+0x63c> 801a44c: 4b74 ldr r3, [pc, #464] @ (801a620 <_dtoa_r+0x8d0>) 801a44e: 2200 movs r2, #0 801a450: f7e6 f8aa bl 80005a8 <__aeabi_dmul> 801a454: 4602 mov r2, r0 801a456: 460b mov r3, r1 801a458: e9cd 2306 strd r2, r3, [sp, #24] 801a45c: 2200 movs r2, #0 801a45e: 2300 movs r3, #0 801a460: f7e6 fb0a bl 8000a78 <__aeabi_dcmpeq> 801a464: 2800 cmp r0, #0 801a466: d09c beq.n 801a3a2 <_dtoa_r+0x652> 801a468: e7ce b.n 801a408 <_dtoa_r+0x6b8> 801a46a: 9a0b ldr r2, [sp, #44] @ 0x2c 801a46c: 2a00 cmp r2, #0 801a46e: f000 80e3 beq.w 801a638 <_dtoa_r+0x8e8> 801a472: 9a0a ldr r2, [sp, #40] @ 0x28 801a474: 2a01 cmp r2, #1 801a476: f300 80c2 bgt.w 801a5fe <_dtoa_r+0x8ae> 801a47a: 9a14 ldr r2, [sp, #80] @ 0x50 801a47c: 2a00 cmp r2, #0 801a47e: f000 80ba beq.w 801a5f6 <_dtoa_r+0x8a6> 801a482: f203 4333 addw r3, r3, #1075 @ 0x433 801a486: 9d09 ldr r5, [sp, #36] @ 0x24 801a488: 463e mov r6, r7 801a48a: 9a08 ldr r2, [sp, #32] 801a48c: 2101 movs r1, #1 801a48e: 441a add r2, r3 801a490: 4648 mov r0, r9 801a492: 441f add r7, r3 801a494: 9208 str r2, [sp, #32] 801a496: f000 fc73 bl 801ad80 <__i2b> 801a49a: 4604 mov r4, r0 801a49c: b156 cbz r6, 801a4b4 <_dtoa_r+0x764> 801a49e: 9b08 ldr r3, [sp, #32] 801a4a0: 2b00 cmp r3, #0 801a4a2: dd07 ble.n 801a4b4 <_dtoa_r+0x764> 801a4a4: 42b3 cmp r3, r6 801a4a6: 9a08 ldr r2, [sp, #32] 801a4a8: bfa8 it ge 801a4aa: 4633 movge r3, r6 801a4ac: 1aff subs r7, r7, r3 801a4ae: 1af6 subs r6, r6, r3 801a4b0: 1ad3 subs r3, r2, r3 801a4b2: 9308 str r3, [sp, #32] 801a4b4: 9b09 ldr r3, [sp, #36] @ 0x24 801a4b6: b30b cbz r3, 801a4fc <_dtoa_r+0x7ac> 801a4b8: 9b0b ldr r3, [sp, #44] @ 0x2c 801a4ba: 2b00 cmp r3, #0 801a4bc: f000 80c3 beq.w 801a646 <_dtoa_r+0x8f6> 801a4c0: 2d00 cmp r5, #0 801a4c2: f000 80bd beq.w 801a640 <_dtoa_r+0x8f0> 801a4c6: 4621 mov r1, r4 801a4c8: 462a mov r2, r5 801a4ca: 4648 mov r0, r9 801a4cc: f000 fd18 bl 801af00 <__pow5mult> 801a4d0: 9a01 ldr r2, [sp, #4] 801a4d2: 4601 mov r1, r0 801a4d4: 4604 mov r4, r0 801a4d6: 4648 mov r0, r9 801a4d8: f000 fc68 bl 801adac <__multiply> 801a4dc: 9901 ldr r1, [sp, #4] 801a4de: 4682 mov sl, r0 801a4e0: 4648 mov r0, r9 801a4e2: f000 fb4f bl 801ab84 <_Bfree> 801a4e6: 9b09 ldr r3, [sp, #36] @ 0x24 801a4e8: 1b5b subs r3, r3, r5 801a4ea: 9309 str r3, [sp, #36] @ 0x24 801a4ec: f000 80ae beq.w 801a64c <_dtoa_r+0x8fc> 801a4f0: 9a09 ldr r2, [sp, #36] @ 0x24 801a4f2: 4651 mov r1, sl 801a4f4: 4648 mov r0, r9 801a4f6: f000 fd03 bl 801af00 <__pow5mult> 801a4fa: 9001 str r0, [sp, #4] 801a4fc: 2101 movs r1, #1 801a4fe: 4648 mov r0, r9 801a500: f000 fc3e bl 801ad80 <__i2b> 801a504: 9b0d ldr r3, [sp, #52] @ 0x34 801a506: 4605 mov r5, r0 801a508: 2b00 cmp r3, #0 801a50a: f000 81d7 beq.w 801a8bc <_dtoa_r+0xb6c> 801a50e: 461a mov r2, r3 801a510: 4601 mov r1, r0 801a512: 4648 mov r0, r9 801a514: f000 fcf4 bl 801af00 <__pow5mult> 801a518: 9b0a ldr r3, [sp, #40] @ 0x28 801a51a: 2b01 cmp r3, #1 801a51c: 4605 mov r5, r0 801a51e: f300 809d bgt.w 801a65c <_dtoa_r+0x90c> 801a522: 9b0e ldr r3, [sp, #56] @ 0x38 801a524: 2b00 cmp r3, #0 801a526: f040 8094 bne.w 801a652 <_dtoa_r+0x902> 801a52a: 9b0f ldr r3, [sp, #60] @ 0x3c 801a52c: f3c3 0313 ubfx r3, r3, #0, #20 801a530: 2b00 cmp r3, #0 801a532: f040 808e bne.w 801a652 <_dtoa_r+0x902> 801a536: 9b0f ldr r3, [sp, #60] @ 0x3c 801a538: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 801a53c: 0d1b lsrs r3, r3, #20 801a53e: 051b lsls r3, r3, #20 801a540: 2b00 cmp r3, #0 801a542: f000 8089 beq.w 801a658 <_dtoa_r+0x908> 801a546: 9b08 ldr r3, [sp, #32] 801a548: 3301 adds r3, #1 801a54a: 3701 adds r7, #1 801a54c: 9308 str r3, [sp, #32] 801a54e: f04f 0a01 mov.w sl, #1 801a552: 9b0d ldr r3, [sp, #52] @ 0x34 801a554: 2b00 cmp r3, #0 801a556: f000 81b7 beq.w 801a8c8 <_dtoa_r+0xb78> 801a55a: 692b ldr r3, [r5, #16] 801a55c: eb05 0383 add.w r3, r5, r3, lsl #2 801a560: 6918 ldr r0, [r3, #16] 801a562: f000 fbc1 bl 801ace8 <__hi0bits> 801a566: f1c0 0020 rsb r0, r0, #32 801a56a: 9b08 ldr r3, [sp, #32] 801a56c: 4418 add r0, r3 801a56e: f010 001f ands.w r0, r0, #31 801a572: d07e beq.n 801a672 <_dtoa_r+0x922> 801a574: f1c0 0320 rsb r3, r0, #32 801a578: 2b04 cmp r3, #4 801a57a: dd72 ble.n 801a662 <_dtoa_r+0x912> 801a57c: 9b08 ldr r3, [sp, #32] 801a57e: f1c0 001c rsb r0, r0, #28 801a582: 4403 add r3, r0 801a584: 4407 add r7, r0 801a586: 4406 add r6, r0 801a588: 9308 str r3, [sp, #32] 801a58a: 2f00 cmp r7, #0 801a58c: dd05 ble.n 801a59a <_dtoa_r+0x84a> 801a58e: 9901 ldr r1, [sp, #4] 801a590: 463a mov r2, r7 801a592: 4648 mov r0, r9 801a594: f000 fd10 bl 801afb8 <__lshift> 801a598: 9001 str r0, [sp, #4] 801a59a: 9b08 ldr r3, [sp, #32] 801a59c: 2b00 cmp r3, #0 801a59e: dd05 ble.n 801a5ac <_dtoa_r+0x85c> 801a5a0: 4629 mov r1, r5 801a5a2: 461a mov r2, r3 801a5a4: 4648 mov r0, r9 801a5a6: f000 fd07 bl 801afb8 <__lshift> 801a5aa: 4605 mov r5, r0 801a5ac: 9b12 ldr r3, [sp, #72] @ 0x48 801a5ae: 2b00 cmp r3, #0 801a5b0: d061 beq.n 801a676 <_dtoa_r+0x926> 801a5b2: 9801 ldr r0, [sp, #4] 801a5b4: 4629 mov r1, r5 801a5b6: f000 fd6d bl 801b094 <__mcmp> 801a5ba: 2800 cmp r0, #0 801a5bc: da5b bge.n 801a676 <_dtoa_r+0x926> 801a5be: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff 801a5c2: 9302 str r3, [sp, #8] 801a5c4: 9901 ldr r1, [sp, #4] 801a5c6: 2300 movs r3, #0 801a5c8: 220a movs r2, #10 801a5ca: 4648 mov r0, r9 801a5cc: f000 fafc bl 801abc8 <__multadd> 801a5d0: 9b0b ldr r3, [sp, #44] @ 0x2c 801a5d2: 9001 str r0, [sp, #4] 801a5d4: 2b00 cmp r3, #0 801a5d6: f000 8179 beq.w 801a8cc <_dtoa_r+0xb7c> 801a5da: 2300 movs r3, #0 801a5dc: 4621 mov r1, r4 801a5de: 220a movs r2, #10 801a5e0: 4648 mov r0, r9 801a5e2: f000 faf1 bl 801abc8 <__multadd> 801a5e6: 9b05 ldr r3, [sp, #20] 801a5e8: 2b00 cmp r3, #0 801a5ea: 4604 mov r4, r0 801a5ec: dc72 bgt.n 801a6d4 <_dtoa_r+0x984> 801a5ee: 9b0a ldr r3, [sp, #40] @ 0x28 801a5f0: 2b02 cmp r3, #2 801a5f2: dc49 bgt.n 801a688 <_dtoa_r+0x938> 801a5f4: e06e b.n 801a6d4 <_dtoa_r+0x984> 801a5f6: 9b16 ldr r3, [sp, #88] @ 0x58 801a5f8: f1c3 0336 rsb r3, r3, #54 @ 0x36 801a5fc: e743 b.n 801a486 <_dtoa_r+0x736> 801a5fe: 9b04 ldr r3, [sp, #16] 801a600: 1e5d subs r5, r3, #1 801a602: 9b09 ldr r3, [sp, #36] @ 0x24 801a604: 42ab cmp r3, r5 801a606: db0d blt.n 801a624 <_dtoa_r+0x8d4> 801a608: 1b5d subs r5, r3, r5 801a60a: 9b04 ldr r3, [sp, #16] 801a60c: 2b00 cmp r3, #0 801a60e: f6bf af3b bge.w 801a488 <_dtoa_r+0x738> 801a612: 9b04 ldr r3, [sp, #16] 801a614: 1afe subs r6, r7, r3 801a616: 2300 movs r3, #0 801a618: e737 b.n 801a48a <_dtoa_r+0x73a> 801a61a: bf00 nop 801a61c: 3fe00000 .word 0x3fe00000 801a620: 40240000 .word 0x40240000 801a624: 9b09 ldr r3, [sp, #36] @ 0x24 801a626: 9a0d ldr r2, [sp, #52] @ 0x34 801a628: 9509 str r5, [sp, #36] @ 0x24 801a62a: 1aeb subs r3, r5, r3 801a62c: 441a add r2, r3 801a62e: 920d str r2, [sp, #52] @ 0x34 801a630: 9b04 ldr r3, [sp, #16] 801a632: 463e mov r6, r7 801a634: 2500 movs r5, #0 801a636: e728 b.n 801a48a <_dtoa_r+0x73a> 801a638: 9d09 ldr r5, [sp, #36] @ 0x24 801a63a: 9c0b ldr r4, [sp, #44] @ 0x2c 801a63c: 463e mov r6, r7 801a63e: e72d b.n 801a49c <_dtoa_r+0x74c> 801a640: f8dd a004 ldr.w sl, [sp, #4] 801a644: e754 b.n 801a4f0 <_dtoa_r+0x7a0> 801a646: 9a09 ldr r2, [sp, #36] @ 0x24 801a648: 9901 ldr r1, [sp, #4] 801a64a: e753 b.n 801a4f4 <_dtoa_r+0x7a4> 801a64c: f8cd a004 str.w sl, [sp, #4] 801a650: e754 b.n 801a4fc <_dtoa_r+0x7ac> 801a652: f04f 0a00 mov.w sl, #0 801a656: e77c b.n 801a552 <_dtoa_r+0x802> 801a658: 469a mov sl, r3 801a65a: e77a b.n 801a552 <_dtoa_r+0x802> 801a65c: f04f 0a00 mov.w sl, #0 801a660: e77b b.n 801a55a <_dtoa_r+0x80a> 801a662: d092 beq.n 801a58a <_dtoa_r+0x83a> 801a664: 9a08 ldr r2, [sp, #32] 801a666: 331c adds r3, #28 801a668: 441a add r2, r3 801a66a: 441f add r7, r3 801a66c: 441e add r6, r3 801a66e: 9208 str r2, [sp, #32] 801a670: e78b b.n 801a58a <_dtoa_r+0x83a> 801a672: 4603 mov r3, r0 801a674: e7f6 b.n 801a664 <_dtoa_r+0x914> 801a676: 9b04 ldr r3, [sp, #16] 801a678: f8cd 8008 str.w r8, [sp, #8] 801a67c: 2b00 cmp r3, #0 801a67e: dc23 bgt.n 801a6c8 <_dtoa_r+0x978> 801a680: 9305 str r3, [sp, #20] 801a682: 9b0a ldr r3, [sp, #40] @ 0x28 801a684: 2b02 cmp r3, #2 801a686: dd21 ble.n 801a6cc <_dtoa_r+0x97c> 801a688: 9b05 ldr r3, [sp, #20] 801a68a: 2b00 cmp r3, #0 801a68c: f47f adb0 bne.w 801a1f0 <_dtoa_r+0x4a0> 801a690: 4629 mov r1, r5 801a692: 2205 movs r2, #5 801a694: 4648 mov r0, r9 801a696: f000 fa97 bl 801abc8 <__multadd> 801a69a: 4601 mov r1, r0 801a69c: 4605 mov r5, r0 801a69e: 9801 ldr r0, [sp, #4] 801a6a0: f000 fcf8 bl 801b094 <__mcmp> 801a6a4: 2800 cmp r0, #0 801a6a6: f77f ada3 ble.w 801a1f0 <_dtoa_r+0x4a0> 801a6aa: 9e00 ldr r6, [sp, #0] 801a6ac: 2331 movs r3, #49 @ 0x31 801a6ae: f806 3b01 strb.w r3, [r6], #1 801a6b2: 9b02 ldr r3, [sp, #8] 801a6b4: 3301 adds r3, #1 801a6b6: 9302 str r3, [sp, #8] 801a6b8: e59e b.n 801a1f8 <_dtoa_r+0x4a8> 801a6ba: 4635 mov r5, r6 801a6bc: 462c mov r4, r5 801a6be: e7f4 b.n 801a6aa <_dtoa_r+0x95a> 801a6c0: 9d04 ldr r5, [sp, #16] 801a6c2: f8cd 8008 str.w r8, [sp, #8] 801a6c6: e7f9 b.n 801a6bc <_dtoa_r+0x96c> 801a6c8: 9b04 ldr r3, [sp, #16] 801a6ca: 9305 str r3, [sp, #20] 801a6cc: 9b0b ldr r3, [sp, #44] @ 0x2c 801a6ce: 2b00 cmp r3, #0 801a6d0: f000 8100 beq.w 801a8d4 <_dtoa_r+0xb84> 801a6d4: 2e00 cmp r6, #0 801a6d6: dd05 ble.n 801a6e4 <_dtoa_r+0x994> 801a6d8: 4621 mov r1, r4 801a6da: 4632 mov r2, r6 801a6dc: 4648 mov r0, r9 801a6de: f000 fc6b bl 801afb8 <__lshift> 801a6e2: 4604 mov r4, r0 801a6e4: f1ba 0f00 cmp.w sl, #0 801a6e8: d05a beq.n 801a7a0 <_dtoa_r+0xa50> 801a6ea: 6861 ldr r1, [r4, #4] 801a6ec: 4648 mov r0, r9 801a6ee: f000 fa0b bl 801ab08 <_Balloc> 801a6f2: 4606 mov r6, r0 801a6f4: b928 cbnz r0, 801a702 <_dtoa_r+0x9b2> 801a6f6: 4b82 ldr r3, [pc, #520] @ (801a900 <_dtoa_r+0xbb0>) 801a6f8: 4602 mov r2, r0 801a6fa: f240 21ef movw r1, #751 @ 0x2ef 801a6fe: f7ff bb3e b.w 8019d7e <_dtoa_r+0x2e> 801a702: 6922 ldr r2, [r4, #16] 801a704: 3202 adds r2, #2 801a706: 0092 lsls r2, r2, #2 801a708: f104 010c add.w r1, r4, #12 801a70c: 300c adds r0, #12 801a70e: f7ff fa80 bl 8019c12 801a712: 2201 movs r2, #1 801a714: 4631 mov r1, r6 801a716: 4648 mov r0, r9 801a718: f000 fc4e bl 801afb8 <__lshift> 801a71c: 4607 mov r7, r0 801a71e: 9b00 ldr r3, [sp, #0] 801a720: 9a00 ldr r2, [sp, #0] 801a722: f103 0b01 add.w fp, r3, #1 801a726: 9b05 ldr r3, [sp, #20] 801a728: 4413 add r3, r2 801a72a: 9306 str r3, [sp, #24] 801a72c: 9b0e ldr r3, [sp, #56] @ 0x38 801a72e: f003 0301 and.w r3, r3, #1 801a732: 9308 str r3, [sp, #32] 801a734: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff 801a738: 4629 mov r1, r5 801a73a: 9801 ldr r0, [sp, #4] 801a73c: 9304 str r3, [sp, #16] 801a73e: f7ff fa7d bl 8019c3c 801a742: 4621 mov r1, r4 801a744: 9005 str r0, [sp, #20] 801a746: f100 0a30 add.w sl, r0, #48 @ 0x30 801a74a: 9801 ldr r0, [sp, #4] 801a74c: f000 fca2 bl 801b094 <__mcmp> 801a750: 463a mov r2, r7 801a752: 4680 mov r8, r0 801a754: 4629 mov r1, r5 801a756: 4648 mov r0, r9 801a758: f000 fcb8 bl 801b0cc <__mdiff> 801a75c: 68c2 ldr r2, [r0, #12] 801a75e: 4606 mov r6, r0 801a760: bb02 cbnz r2, 801a7a4 <_dtoa_r+0xa54> 801a762: 4601 mov r1, r0 801a764: 9801 ldr r0, [sp, #4] 801a766: f000 fc95 bl 801b094 <__mcmp> 801a76a: 4602 mov r2, r0 801a76c: 4631 mov r1, r6 801a76e: 4648 mov r0, r9 801a770: 9209 str r2, [sp, #36] @ 0x24 801a772: f000 fa07 bl 801ab84 <_Bfree> 801a776: e9dd 2309 ldrd r2, r3, [sp, #36] @ 0x24 801a77a: ea42 0103 orr.w r1, r2, r3 801a77e: 9b08 ldr r3, [sp, #32] 801a780: 4319 orrs r1, r3 801a782: 465e mov r6, fp 801a784: d110 bne.n 801a7a8 <_dtoa_r+0xa58> 801a786: f1ba 0f39 cmp.w sl, #57 @ 0x39 801a78a: d02b beq.n 801a7e4 <_dtoa_r+0xa94> 801a78c: f1b8 0f00 cmp.w r8, #0 801a790: dd02 ble.n 801a798 <_dtoa_r+0xa48> 801a792: 9b05 ldr r3, [sp, #20] 801a794: f103 0a31 add.w sl, r3, #49 @ 0x31 801a798: 9b04 ldr r3, [sp, #16] 801a79a: f883 a000 strb.w sl, [r3] 801a79e: e52d b.n 801a1fc <_dtoa_r+0x4ac> 801a7a0: 4627 mov r7, r4 801a7a2: e7bc b.n 801a71e <_dtoa_r+0x9ce> 801a7a4: 2201 movs r2, #1 801a7a6: e7e1 b.n 801a76c <_dtoa_r+0xa1c> 801a7a8: f1b8 0f00 cmp.w r8, #0 801a7ac: db06 blt.n 801a7bc <_dtoa_r+0xa6c> 801a7ae: 9b0a ldr r3, [sp, #40] @ 0x28 801a7b0: ea48 0803 orr.w r8, r8, r3 801a7b4: 9b08 ldr r3, [sp, #32] 801a7b6: ea58 0803 orrs.w r8, r8, r3 801a7ba: d120 bne.n 801a7fe <_dtoa_r+0xaae> 801a7bc: 2a00 cmp r2, #0 801a7be: ddeb ble.n 801a798 <_dtoa_r+0xa48> 801a7c0: 9901 ldr r1, [sp, #4] 801a7c2: 2201 movs r2, #1 801a7c4: 4648 mov r0, r9 801a7c6: f000 fbf7 bl 801afb8 <__lshift> 801a7ca: 4629 mov r1, r5 801a7cc: 9001 str r0, [sp, #4] 801a7ce: f000 fc61 bl 801b094 <__mcmp> 801a7d2: 2800 cmp r0, #0 801a7d4: dc03 bgt.n 801a7de <_dtoa_r+0xa8e> 801a7d6: d1df bne.n 801a798 <_dtoa_r+0xa48> 801a7d8: f01a 0f01 tst.w sl, #1 801a7dc: d0dc beq.n 801a798 <_dtoa_r+0xa48> 801a7de: f1ba 0f39 cmp.w sl, #57 @ 0x39 801a7e2: d1d6 bne.n 801a792 <_dtoa_r+0xa42> 801a7e4: 9a04 ldr r2, [sp, #16] 801a7e6: 2339 movs r3, #57 @ 0x39 801a7e8: 7013 strb r3, [r2, #0] 801a7ea: 4633 mov r3, r6 801a7ec: 461e mov r6, r3 801a7ee: 3b01 subs r3, #1 801a7f0: f816 2c01 ldrb.w r2, [r6, #-1] 801a7f4: 2a39 cmp r2, #57 @ 0x39 801a7f6: d052 beq.n 801a89e <_dtoa_r+0xb4e> 801a7f8: 3201 adds r2, #1 801a7fa: 701a strb r2, [r3, #0] 801a7fc: e4fe b.n 801a1fc <_dtoa_r+0x4ac> 801a7fe: 2a00 cmp r2, #0 801a800: dd07 ble.n 801a812 <_dtoa_r+0xac2> 801a802: f1ba 0f39 cmp.w sl, #57 @ 0x39 801a806: d0ed beq.n 801a7e4 <_dtoa_r+0xa94> 801a808: 9a04 ldr r2, [sp, #16] 801a80a: f10a 0301 add.w r3, sl, #1 801a80e: 7013 strb r3, [r2, #0] 801a810: e4f4 b.n 801a1fc <_dtoa_r+0x4ac> 801a812: 9b06 ldr r3, [sp, #24] 801a814: f80b ac01 strb.w sl, [fp, #-1] 801a818: 455b cmp r3, fp 801a81a: d02a beq.n 801a872 <_dtoa_r+0xb22> 801a81c: 9901 ldr r1, [sp, #4] 801a81e: 2300 movs r3, #0 801a820: 220a movs r2, #10 801a822: 4648 mov r0, r9 801a824: f000 f9d0 bl 801abc8 <__multadd> 801a828: 42bc cmp r4, r7 801a82a: 9001 str r0, [sp, #4] 801a82c: f04f 0300 mov.w r3, #0 801a830: f04f 020a mov.w r2, #10 801a834: 4621 mov r1, r4 801a836: 4648 mov r0, r9 801a838: d106 bne.n 801a848 <_dtoa_r+0xaf8> 801a83a: f000 f9c5 bl 801abc8 <__multadd> 801a83e: 4604 mov r4, r0 801a840: 4607 mov r7, r0 801a842: f10b 0b01 add.w fp, fp, #1 801a846: e775 b.n 801a734 <_dtoa_r+0x9e4> 801a848: f000 f9be bl 801abc8 <__multadd> 801a84c: 4639 mov r1, r7 801a84e: 4604 mov r4, r0 801a850: 2300 movs r3, #0 801a852: 220a movs r2, #10 801a854: 4648 mov r0, r9 801a856: f000 f9b7 bl 801abc8 <__multadd> 801a85a: 4607 mov r7, r0 801a85c: e7f1 b.n 801a842 <_dtoa_r+0xaf2> 801a85e: 9b05 ldr r3, [sp, #20] 801a860: 1e5e subs r6, r3, #1 801a862: 2b00 cmp r3, #0 801a864: 9b00 ldr r3, [sp, #0] 801a866: bfd8 it le 801a868: 2600 movle r6, #0 801a86a: 1c5a adds r2, r3, #1 801a86c: 4627 mov r7, r4 801a86e: 4416 add r6, r2 801a870: 2400 movs r4, #0 801a872: 9901 ldr r1, [sp, #4] 801a874: 2201 movs r2, #1 801a876: 4648 mov r0, r9 801a878: f000 fb9e bl 801afb8 <__lshift> 801a87c: 4629 mov r1, r5 801a87e: 9001 str r0, [sp, #4] 801a880: f000 fc08 bl 801b094 <__mcmp> 801a884: 2800 cmp r0, #0 801a886: dcb0 bgt.n 801a7ea <_dtoa_r+0xa9a> 801a888: d102 bne.n 801a890 <_dtoa_r+0xb40> 801a88a: f01a 0f01 tst.w sl, #1 801a88e: d1ac bne.n 801a7ea <_dtoa_r+0xa9a> 801a890: 4633 mov r3, r6 801a892: 461e mov r6, r3 801a894: f813 2d01 ldrb.w r2, [r3, #-1]! 801a898: 2a30 cmp r2, #48 @ 0x30 801a89a: d0fa beq.n 801a892 <_dtoa_r+0xb42> 801a89c: e4ae b.n 801a1fc <_dtoa_r+0x4ac> 801a89e: 9a00 ldr r2, [sp, #0] 801a8a0: 429a cmp r2, r3 801a8a2: d1a3 bne.n 801a7ec <_dtoa_r+0xa9c> 801a8a4: 9b02 ldr r3, [sp, #8] 801a8a6: 3301 adds r3, #1 801a8a8: 9302 str r3, [sp, #8] 801a8aa: 2331 movs r3, #49 @ 0x31 801a8ac: e7af b.n 801a80e <_dtoa_r+0xabe> 801a8ae: 9b23 ldr r3, [sp, #140] @ 0x8c 801a8b0: 2b00 cmp r3, #0 801a8b2: f47f aa98 bne.w 8019de6 <_dtoa_r+0x96> 801a8b6: 4b13 ldr r3, [pc, #76] @ (801a904 <_dtoa_r+0xbb4>) 801a8b8: f7ff bab7 b.w 8019e2a <_dtoa_r+0xda> 801a8bc: 9b0a ldr r3, [sp, #40] @ 0x28 801a8be: 2b01 cmp r3, #1 801a8c0: f77f ae2f ble.w 801a522 <_dtoa_r+0x7d2> 801a8c4: f8dd a034 ldr.w sl, [sp, #52] @ 0x34 801a8c8: 2001 movs r0, #1 801a8ca: e64e b.n 801a56a <_dtoa_r+0x81a> 801a8cc: 9b05 ldr r3, [sp, #20] 801a8ce: 2b00 cmp r3, #0 801a8d0: f77f aed7 ble.w 801a682 <_dtoa_r+0x932> 801a8d4: 9e00 ldr r6, [sp, #0] 801a8d6: 9801 ldr r0, [sp, #4] 801a8d8: 4629 mov r1, r5 801a8da: f7ff f9af bl 8019c3c 801a8de: f100 0a30 add.w sl, r0, #48 @ 0x30 801a8e2: 9b00 ldr r3, [sp, #0] 801a8e4: f806 ab01 strb.w sl, [r6], #1 801a8e8: 1af2 subs r2, r6, r3 801a8ea: 9b05 ldr r3, [sp, #20] 801a8ec: 4293 cmp r3, r2 801a8ee: ddb6 ble.n 801a85e <_dtoa_r+0xb0e> 801a8f0: 9901 ldr r1, [sp, #4] 801a8f2: 2300 movs r3, #0 801a8f4: 220a movs r2, #10 801a8f6: 4648 mov r0, r9 801a8f8: f000 f966 bl 801abc8 <__multadd> 801a8fc: 9001 str r0, [sp, #4] 801a8fe: e7ea b.n 801a8d6 <_dtoa_r+0xb86> 801a900: 0801dd65 .word 0x0801dd65 801a904: 0801dce9 .word 0x0801dce9 0801a908 <_free_r>: 801a908: b538 push {r3, r4, r5, lr} 801a90a: 4605 mov r5, r0 801a90c: 2900 cmp r1, #0 801a90e: d041 beq.n 801a994 <_free_r+0x8c> 801a910: f851 3c04 ldr.w r3, [r1, #-4] 801a914: 1f0c subs r4, r1, #4 801a916: 2b00 cmp r3, #0 801a918: bfb8 it lt 801a91a: 18e4 addlt r4, r4, r3 801a91c: f000 f8e8 bl 801aaf0 <__malloc_lock> 801a920: 4a1d ldr r2, [pc, #116] @ (801a998 <_free_r+0x90>) 801a922: 6813 ldr r3, [r2, #0] 801a924: b933 cbnz r3, 801a934 <_free_r+0x2c> 801a926: 6063 str r3, [r4, #4] 801a928: 6014 str r4, [r2, #0] 801a92a: 4628 mov r0, r5 801a92c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 801a930: f000 b8e4 b.w 801aafc <__malloc_unlock> 801a934: 42a3 cmp r3, r4 801a936: d908 bls.n 801a94a <_free_r+0x42> 801a938: 6820 ldr r0, [r4, #0] 801a93a: 1821 adds r1, r4, r0 801a93c: 428b cmp r3, r1 801a93e: bf01 itttt eq 801a940: 6819 ldreq r1, [r3, #0] 801a942: 685b ldreq r3, [r3, #4] 801a944: 1809 addeq r1, r1, r0 801a946: 6021 streq r1, [r4, #0] 801a948: e7ed b.n 801a926 <_free_r+0x1e> 801a94a: 461a mov r2, r3 801a94c: 685b ldr r3, [r3, #4] 801a94e: b10b cbz r3, 801a954 <_free_r+0x4c> 801a950: 42a3 cmp r3, r4 801a952: d9fa bls.n 801a94a <_free_r+0x42> 801a954: 6811 ldr r1, [r2, #0] 801a956: 1850 adds r0, r2, r1 801a958: 42a0 cmp r0, r4 801a95a: d10b bne.n 801a974 <_free_r+0x6c> 801a95c: 6820 ldr r0, [r4, #0] 801a95e: 4401 add r1, r0 801a960: 1850 adds r0, r2, r1 801a962: 4283 cmp r3, r0 801a964: 6011 str r1, [r2, #0] 801a966: d1e0 bne.n 801a92a <_free_r+0x22> 801a968: 6818 ldr r0, [r3, #0] 801a96a: 685b ldr r3, [r3, #4] 801a96c: 6053 str r3, [r2, #4] 801a96e: 4408 add r0, r1 801a970: 6010 str r0, [r2, #0] 801a972: e7da b.n 801a92a <_free_r+0x22> 801a974: d902 bls.n 801a97c <_free_r+0x74> 801a976: 230c movs r3, #12 801a978: 602b str r3, [r5, #0] 801a97a: e7d6 b.n 801a92a <_free_r+0x22> 801a97c: 6820 ldr r0, [r4, #0] 801a97e: 1821 adds r1, r4, r0 801a980: 428b cmp r3, r1 801a982: bf04 itt eq 801a984: 6819 ldreq r1, [r3, #0] 801a986: 685b ldreq r3, [r3, #4] 801a988: 6063 str r3, [r4, #4] 801a98a: bf04 itt eq 801a98c: 1809 addeq r1, r1, r0 801a98e: 6021 streq r1, [r4, #0] 801a990: 6054 str r4, [r2, #4] 801a992: e7ca b.n 801a92a <_free_r+0x22> 801a994: bd38 pop {r3, r4, r5, pc} 801a996: bf00 nop 801a998: 20013c44 .word 0x20013c44 0801a99c : 801a99c: 4b02 ldr r3, [pc, #8] @ (801a9a8 ) 801a99e: 4601 mov r1, r0 801a9a0: 6818 ldr r0, [r3, #0] 801a9a2: f000 b825 b.w 801a9f0 <_malloc_r> 801a9a6: bf00 nop 801a9a8: 2000011c .word 0x2000011c 0801a9ac : 801a9ac: b570 push {r4, r5, r6, lr} 801a9ae: 4e0f ldr r6, [pc, #60] @ (801a9ec ) 801a9b0: 460c mov r4, r1 801a9b2: 6831 ldr r1, [r6, #0] 801a9b4: 4605 mov r5, r0 801a9b6: b911 cbnz r1, 801a9be 801a9b8: f001 ffc6 bl 801c948 <_sbrk_r> 801a9bc: 6030 str r0, [r6, #0] 801a9be: 4621 mov r1, r4 801a9c0: 4628 mov r0, r5 801a9c2: f001 ffc1 bl 801c948 <_sbrk_r> 801a9c6: 1c43 adds r3, r0, #1 801a9c8: d103 bne.n 801a9d2 801a9ca: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 801a9ce: 4620 mov r0, r4 801a9d0: bd70 pop {r4, r5, r6, pc} 801a9d2: 1cc4 adds r4, r0, #3 801a9d4: f024 0403 bic.w r4, r4, #3 801a9d8: 42a0 cmp r0, r4 801a9da: d0f8 beq.n 801a9ce 801a9dc: 1a21 subs r1, r4, r0 801a9de: 4628 mov r0, r5 801a9e0: f001 ffb2 bl 801c948 <_sbrk_r> 801a9e4: 3001 adds r0, #1 801a9e6: d1f2 bne.n 801a9ce 801a9e8: e7ef b.n 801a9ca 801a9ea: bf00 nop 801a9ec: 20013c40 .word 0x20013c40 0801a9f0 <_malloc_r>: 801a9f0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801a9f4: 1ccd adds r5, r1, #3 801a9f6: f025 0503 bic.w r5, r5, #3 801a9fa: 3508 adds r5, #8 801a9fc: 2d0c cmp r5, #12 801a9fe: bf38 it cc 801aa00: 250c movcc r5, #12 801aa02: 2d00 cmp r5, #0 801aa04: 4606 mov r6, r0 801aa06: db01 blt.n 801aa0c <_malloc_r+0x1c> 801aa08: 42a9 cmp r1, r5 801aa0a: d904 bls.n 801aa16 <_malloc_r+0x26> 801aa0c: 230c movs r3, #12 801aa0e: 6033 str r3, [r6, #0] 801aa10: 2000 movs r0, #0 801aa12: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801aa16: f8df 80d4 ldr.w r8, [pc, #212] @ 801aaec <_malloc_r+0xfc> 801aa1a: f000 f869 bl 801aaf0 <__malloc_lock> 801aa1e: f8d8 3000 ldr.w r3, [r8] 801aa22: 461c mov r4, r3 801aa24: bb44 cbnz r4, 801aa78 <_malloc_r+0x88> 801aa26: 4629 mov r1, r5 801aa28: 4630 mov r0, r6 801aa2a: f7ff ffbf bl 801a9ac 801aa2e: 1c43 adds r3, r0, #1 801aa30: 4604 mov r4, r0 801aa32: d158 bne.n 801aae6 <_malloc_r+0xf6> 801aa34: f8d8 4000 ldr.w r4, [r8] 801aa38: 4627 mov r7, r4 801aa3a: 2f00 cmp r7, #0 801aa3c: d143 bne.n 801aac6 <_malloc_r+0xd6> 801aa3e: 2c00 cmp r4, #0 801aa40: d04b beq.n 801aada <_malloc_r+0xea> 801aa42: 6823 ldr r3, [r4, #0] 801aa44: 4639 mov r1, r7 801aa46: 4630 mov r0, r6 801aa48: eb04 0903 add.w r9, r4, r3 801aa4c: f001 ff7c bl 801c948 <_sbrk_r> 801aa50: 4581 cmp r9, r0 801aa52: d142 bne.n 801aada <_malloc_r+0xea> 801aa54: 6821 ldr r1, [r4, #0] 801aa56: 1a6d subs r5, r5, r1 801aa58: 4629 mov r1, r5 801aa5a: 4630 mov r0, r6 801aa5c: f7ff ffa6 bl 801a9ac 801aa60: 3001 adds r0, #1 801aa62: d03a beq.n 801aada <_malloc_r+0xea> 801aa64: 6823 ldr r3, [r4, #0] 801aa66: 442b add r3, r5 801aa68: 6023 str r3, [r4, #0] 801aa6a: f8d8 3000 ldr.w r3, [r8] 801aa6e: 685a ldr r2, [r3, #4] 801aa70: bb62 cbnz r2, 801aacc <_malloc_r+0xdc> 801aa72: f8c8 7000 str.w r7, [r8] 801aa76: e00f b.n 801aa98 <_malloc_r+0xa8> 801aa78: 6822 ldr r2, [r4, #0] 801aa7a: 1b52 subs r2, r2, r5 801aa7c: d420 bmi.n 801aac0 <_malloc_r+0xd0> 801aa7e: 2a0b cmp r2, #11 801aa80: d917 bls.n 801aab2 <_malloc_r+0xc2> 801aa82: 1961 adds r1, r4, r5 801aa84: 42a3 cmp r3, r4 801aa86: 6025 str r5, [r4, #0] 801aa88: bf18 it ne 801aa8a: 6059 strne r1, [r3, #4] 801aa8c: 6863 ldr r3, [r4, #4] 801aa8e: bf08 it eq 801aa90: f8c8 1000 streq.w r1, [r8] 801aa94: 5162 str r2, [r4, r5] 801aa96: 604b str r3, [r1, #4] 801aa98: 4630 mov r0, r6 801aa9a: f000 f82f bl 801aafc <__malloc_unlock> 801aa9e: f104 000b add.w r0, r4, #11 801aaa2: 1d23 adds r3, r4, #4 801aaa4: f020 0007 bic.w r0, r0, #7 801aaa8: 1ac2 subs r2, r0, r3 801aaaa: bf1c itt ne 801aaac: 1a1b subne r3, r3, r0 801aaae: 50a3 strne r3, [r4, r2] 801aab0: e7af b.n 801aa12 <_malloc_r+0x22> 801aab2: 6862 ldr r2, [r4, #4] 801aab4: 42a3 cmp r3, r4 801aab6: bf0c ite eq 801aab8: f8c8 2000 streq.w r2, [r8] 801aabc: 605a strne r2, [r3, #4] 801aabe: e7eb b.n 801aa98 <_malloc_r+0xa8> 801aac0: 4623 mov r3, r4 801aac2: 6864 ldr r4, [r4, #4] 801aac4: e7ae b.n 801aa24 <_malloc_r+0x34> 801aac6: 463c mov r4, r7 801aac8: 687f ldr r7, [r7, #4] 801aaca: e7b6 b.n 801aa3a <_malloc_r+0x4a> 801aacc: 461a mov r2, r3 801aace: 685b ldr r3, [r3, #4] 801aad0: 42a3 cmp r3, r4 801aad2: d1fb bne.n 801aacc <_malloc_r+0xdc> 801aad4: 2300 movs r3, #0 801aad6: 6053 str r3, [r2, #4] 801aad8: e7de b.n 801aa98 <_malloc_r+0xa8> 801aada: 230c movs r3, #12 801aadc: 6033 str r3, [r6, #0] 801aade: 4630 mov r0, r6 801aae0: f000 f80c bl 801aafc <__malloc_unlock> 801aae4: e794 b.n 801aa10 <_malloc_r+0x20> 801aae6: 6005 str r5, [r0, #0] 801aae8: e7d6 b.n 801aa98 <_malloc_r+0xa8> 801aaea: bf00 nop 801aaec: 20013c44 .word 0x20013c44 0801aaf0 <__malloc_lock>: 801aaf0: 4801 ldr r0, [pc, #4] @ (801aaf8 <__malloc_lock+0x8>) 801aaf2: f7ff b88c b.w 8019c0e <__retarget_lock_acquire_recursive> 801aaf6: bf00 nop 801aaf8: 20013c3c .word 0x20013c3c 0801aafc <__malloc_unlock>: 801aafc: 4801 ldr r0, [pc, #4] @ (801ab04 <__malloc_unlock+0x8>) 801aafe: f7ff b887 b.w 8019c10 <__retarget_lock_release_recursive> 801ab02: bf00 nop 801ab04: 20013c3c .word 0x20013c3c 0801ab08 <_Balloc>: 801ab08: b570 push {r4, r5, r6, lr} 801ab0a: 69c4 ldr r4, [r0, #28] 801ab0c: 4605 mov r5, r0 801ab0e: 460e mov r6, r1 801ab10: b984 cbnz r4, 801ab34 <_Balloc+0x2c> 801ab12: 2010 movs r0, #16 801ab14: f7ff ff42 bl 801a99c 801ab18: 4604 mov r4, r0 801ab1a: 61e8 str r0, [r5, #28] 801ab1c: b928 cbnz r0, 801ab2a <_Balloc+0x22> 801ab1e: 4602 mov r2, r0 801ab20: 4b16 ldr r3, [pc, #88] @ (801ab7c <_Balloc+0x74>) 801ab22: 4817 ldr r0, [pc, #92] @ (801ab80 <_Balloc+0x78>) 801ab24: 216b movs r1, #107 @ 0x6b 801ab26: f001 ff27 bl 801c978 <__assert_func> 801ab2a: 2300 movs r3, #0 801ab2c: e9c0 3301 strd r3, r3, [r0, #4] 801ab30: 6003 str r3, [r0, #0] 801ab32: 60c3 str r3, [r0, #12] 801ab34: 68e3 ldr r3, [r4, #12] 801ab36: b953 cbnz r3, 801ab4e <_Balloc+0x46> 801ab38: 2221 movs r2, #33 @ 0x21 801ab3a: 2104 movs r1, #4 801ab3c: 4628 mov r0, r5 801ab3e: f001 ff39 bl 801c9b4 <_calloc_r> 801ab42: 69eb ldr r3, [r5, #28] 801ab44: 60e0 str r0, [r4, #12] 801ab46: 68db ldr r3, [r3, #12] 801ab48: b90b cbnz r3, 801ab4e <_Balloc+0x46> 801ab4a: 2000 movs r0, #0 801ab4c: bd70 pop {r4, r5, r6, pc} 801ab4e: f853 0026 ldr.w r0, [r3, r6, lsl #2] 801ab52: b130 cbz r0, 801ab62 <_Balloc+0x5a> 801ab54: 6802 ldr r2, [r0, #0] 801ab56: f843 2026 str.w r2, [r3, r6, lsl #2] 801ab5a: 2300 movs r3, #0 801ab5c: e9c0 3303 strd r3, r3, [r0, #12] 801ab60: e7f4 b.n 801ab4c <_Balloc+0x44> 801ab62: 2101 movs r1, #1 801ab64: fa01 f406 lsl.w r4, r1, r6 801ab68: 1d62 adds r2, r4, #5 801ab6a: 0092 lsls r2, r2, #2 801ab6c: 4628 mov r0, r5 801ab6e: f001 ff21 bl 801c9b4 <_calloc_r> 801ab72: 2800 cmp r0, #0 801ab74: d0e9 beq.n 801ab4a <_Balloc+0x42> 801ab76: e9c0 6401 strd r6, r4, [r0, #4] 801ab7a: e7ee b.n 801ab5a <_Balloc+0x52> 801ab7c: 0801dcf6 .word 0x0801dcf6 801ab80: 0801dd76 .word 0x0801dd76 0801ab84 <_Bfree>: 801ab84: b570 push {r4, r5, r6, lr} 801ab86: 69c6 ldr r6, [r0, #28] 801ab88: 4605 mov r5, r0 801ab8a: 460c mov r4, r1 801ab8c: b976 cbnz r6, 801abac <_Bfree+0x28> 801ab8e: 2010 movs r0, #16 801ab90: f7ff ff04 bl 801a99c 801ab94: 4602 mov r2, r0 801ab96: 61e8 str r0, [r5, #28] 801ab98: b920 cbnz r0, 801aba4 <_Bfree+0x20> 801ab9a: 4b09 ldr r3, [pc, #36] @ (801abc0 <_Bfree+0x3c>) 801ab9c: 4809 ldr r0, [pc, #36] @ (801abc4 <_Bfree+0x40>) 801ab9e: 218f movs r1, #143 @ 0x8f 801aba0: f001 feea bl 801c978 <__assert_func> 801aba4: e9c0 6601 strd r6, r6, [r0, #4] 801aba8: 6006 str r6, [r0, #0] 801abaa: 60c6 str r6, [r0, #12] 801abac: b13c cbz r4, 801abbe <_Bfree+0x3a> 801abae: 69eb ldr r3, [r5, #28] 801abb0: 6862 ldr r2, [r4, #4] 801abb2: 68db ldr r3, [r3, #12] 801abb4: f853 1022 ldr.w r1, [r3, r2, lsl #2] 801abb8: 6021 str r1, [r4, #0] 801abba: f843 4022 str.w r4, [r3, r2, lsl #2] 801abbe: bd70 pop {r4, r5, r6, pc} 801abc0: 0801dcf6 .word 0x0801dcf6 801abc4: 0801dd76 .word 0x0801dd76 0801abc8 <__multadd>: 801abc8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801abcc: 690d ldr r5, [r1, #16] 801abce: 4607 mov r7, r0 801abd0: 460c mov r4, r1 801abd2: 461e mov r6, r3 801abd4: f101 0c14 add.w ip, r1, #20 801abd8: 2000 movs r0, #0 801abda: f8dc 3000 ldr.w r3, [ip] 801abde: b299 uxth r1, r3 801abe0: fb02 6101 mla r1, r2, r1, r6 801abe4: 0c1e lsrs r6, r3, #16 801abe6: 0c0b lsrs r3, r1, #16 801abe8: fb02 3306 mla r3, r2, r6, r3 801abec: b289 uxth r1, r1 801abee: 3001 adds r0, #1 801abf0: eb01 4103 add.w r1, r1, r3, lsl #16 801abf4: 4285 cmp r5, r0 801abf6: f84c 1b04 str.w r1, [ip], #4 801abfa: ea4f 4613 mov.w r6, r3, lsr #16 801abfe: dcec bgt.n 801abda <__multadd+0x12> 801ac00: b30e cbz r6, 801ac46 <__multadd+0x7e> 801ac02: 68a3 ldr r3, [r4, #8] 801ac04: 42ab cmp r3, r5 801ac06: dc19 bgt.n 801ac3c <__multadd+0x74> 801ac08: 6861 ldr r1, [r4, #4] 801ac0a: 4638 mov r0, r7 801ac0c: 3101 adds r1, #1 801ac0e: f7ff ff7b bl 801ab08 <_Balloc> 801ac12: 4680 mov r8, r0 801ac14: b928 cbnz r0, 801ac22 <__multadd+0x5a> 801ac16: 4602 mov r2, r0 801ac18: 4b0c ldr r3, [pc, #48] @ (801ac4c <__multadd+0x84>) 801ac1a: 480d ldr r0, [pc, #52] @ (801ac50 <__multadd+0x88>) 801ac1c: 21ba movs r1, #186 @ 0xba 801ac1e: f001 feab bl 801c978 <__assert_func> 801ac22: 6922 ldr r2, [r4, #16] 801ac24: 3202 adds r2, #2 801ac26: f104 010c add.w r1, r4, #12 801ac2a: 0092 lsls r2, r2, #2 801ac2c: 300c adds r0, #12 801ac2e: f7fe fff0 bl 8019c12 801ac32: 4621 mov r1, r4 801ac34: 4638 mov r0, r7 801ac36: f7ff ffa5 bl 801ab84 <_Bfree> 801ac3a: 4644 mov r4, r8 801ac3c: eb04 0385 add.w r3, r4, r5, lsl #2 801ac40: 3501 adds r5, #1 801ac42: 615e str r6, [r3, #20] 801ac44: 6125 str r5, [r4, #16] 801ac46: 4620 mov r0, r4 801ac48: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801ac4c: 0801dd65 .word 0x0801dd65 801ac50: 0801dd76 .word 0x0801dd76 0801ac54 <__s2b>: 801ac54: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801ac58: 460c mov r4, r1 801ac5a: 4615 mov r5, r2 801ac5c: 461f mov r7, r3 801ac5e: 2209 movs r2, #9 801ac60: 3308 adds r3, #8 801ac62: 4606 mov r6, r0 801ac64: fb93 f3f2 sdiv r3, r3, r2 801ac68: 2100 movs r1, #0 801ac6a: 2201 movs r2, #1 801ac6c: 429a cmp r2, r3 801ac6e: db09 blt.n 801ac84 <__s2b+0x30> 801ac70: 4630 mov r0, r6 801ac72: f7ff ff49 bl 801ab08 <_Balloc> 801ac76: b940 cbnz r0, 801ac8a <__s2b+0x36> 801ac78: 4602 mov r2, r0 801ac7a: 4b19 ldr r3, [pc, #100] @ (801ace0 <__s2b+0x8c>) 801ac7c: 4819 ldr r0, [pc, #100] @ (801ace4 <__s2b+0x90>) 801ac7e: 21d3 movs r1, #211 @ 0xd3 801ac80: f001 fe7a bl 801c978 <__assert_func> 801ac84: 0052 lsls r2, r2, #1 801ac86: 3101 adds r1, #1 801ac88: e7f0 b.n 801ac6c <__s2b+0x18> 801ac8a: 9b08 ldr r3, [sp, #32] 801ac8c: 6143 str r3, [r0, #20] 801ac8e: 2d09 cmp r5, #9 801ac90: f04f 0301 mov.w r3, #1 801ac94: 6103 str r3, [r0, #16] 801ac96: dd16 ble.n 801acc6 <__s2b+0x72> 801ac98: f104 0809 add.w r8, r4, #9 801ac9c: 46c1 mov r9, r8 801ac9e: 442c add r4, r5 801aca0: f819 3b01 ldrb.w r3, [r9], #1 801aca4: 4601 mov r1, r0 801aca6: 3b30 subs r3, #48 @ 0x30 801aca8: 220a movs r2, #10 801acaa: 4630 mov r0, r6 801acac: f7ff ff8c bl 801abc8 <__multadd> 801acb0: 45a1 cmp r9, r4 801acb2: d1f5 bne.n 801aca0 <__s2b+0x4c> 801acb4: 44a8 add r8, r5 801acb6: f1a8 0408 sub.w r4, r8, #8 801acba: 1b2d subs r5, r5, r4 801acbc: 1963 adds r3, r4, r5 801acbe: 429f cmp r7, r3 801acc0: dc04 bgt.n 801accc <__s2b+0x78> 801acc2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801acc6: 340a adds r4, #10 801acc8: 2509 movs r5, #9 801acca: e7f6 b.n 801acba <__s2b+0x66> 801accc: f814 3b01 ldrb.w r3, [r4], #1 801acd0: 4601 mov r1, r0 801acd2: 3b30 subs r3, #48 @ 0x30 801acd4: 220a movs r2, #10 801acd6: 4630 mov r0, r6 801acd8: f7ff ff76 bl 801abc8 <__multadd> 801acdc: e7ee b.n 801acbc <__s2b+0x68> 801acde: bf00 nop 801ace0: 0801dd65 .word 0x0801dd65 801ace4: 0801dd76 .word 0x0801dd76 0801ace8 <__hi0bits>: 801ace8: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 801acec: 4603 mov r3, r0 801acee: bf36 itet cc 801acf0: 0403 lslcc r3, r0, #16 801acf2: 2000 movcs r0, #0 801acf4: 2010 movcc r0, #16 801acf6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 801acfa: bf3c itt cc 801acfc: 021b lslcc r3, r3, #8 801acfe: 3008 addcc r0, #8 801ad00: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 801ad04: bf3c itt cc 801ad06: 011b lslcc r3, r3, #4 801ad08: 3004 addcc r0, #4 801ad0a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801ad0e: bf3c itt cc 801ad10: 009b lslcc r3, r3, #2 801ad12: 3002 addcc r0, #2 801ad14: 2b00 cmp r3, #0 801ad16: db05 blt.n 801ad24 <__hi0bits+0x3c> 801ad18: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 801ad1c: f100 0001 add.w r0, r0, #1 801ad20: bf08 it eq 801ad22: 2020 moveq r0, #32 801ad24: 4770 bx lr 0801ad26 <__lo0bits>: 801ad26: 6803 ldr r3, [r0, #0] 801ad28: 4602 mov r2, r0 801ad2a: f013 0007 ands.w r0, r3, #7 801ad2e: d00b beq.n 801ad48 <__lo0bits+0x22> 801ad30: 07d9 lsls r1, r3, #31 801ad32: d421 bmi.n 801ad78 <__lo0bits+0x52> 801ad34: 0798 lsls r0, r3, #30 801ad36: bf49 itett mi 801ad38: 085b lsrmi r3, r3, #1 801ad3a: 089b lsrpl r3, r3, #2 801ad3c: 2001 movmi r0, #1 801ad3e: 6013 strmi r3, [r2, #0] 801ad40: bf5c itt pl 801ad42: 6013 strpl r3, [r2, #0] 801ad44: 2002 movpl r0, #2 801ad46: 4770 bx lr 801ad48: b299 uxth r1, r3 801ad4a: b909 cbnz r1, 801ad50 <__lo0bits+0x2a> 801ad4c: 0c1b lsrs r3, r3, #16 801ad4e: 2010 movs r0, #16 801ad50: b2d9 uxtb r1, r3 801ad52: b909 cbnz r1, 801ad58 <__lo0bits+0x32> 801ad54: 3008 adds r0, #8 801ad56: 0a1b lsrs r3, r3, #8 801ad58: 0719 lsls r1, r3, #28 801ad5a: bf04 itt eq 801ad5c: 091b lsreq r3, r3, #4 801ad5e: 3004 addeq r0, #4 801ad60: 0799 lsls r1, r3, #30 801ad62: bf04 itt eq 801ad64: 089b lsreq r3, r3, #2 801ad66: 3002 addeq r0, #2 801ad68: 07d9 lsls r1, r3, #31 801ad6a: d403 bmi.n 801ad74 <__lo0bits+0x4e> 801ad6c: 085b lsrs r3, r3, #1 801ad6e: f100 0001 add.w r0, r0, #1 801ad72: d003 beq.n 801ad7c <__lo0bits+0x56> 801ad74: 6013 str r3, [r2, #0] 801ad76: 4770 bx lr 801ad78: 2000 movs r0, #0 801ad7a: 4770 bx lr 801ad7c: 2020 movs r0, #32 801ad7e: 4770 bx lr 0801ad80 <__i2b>: 801ad80: b510 push {r4, lr} 801ad82: 460c mov r4, r1 801ad84: 2101 movs r1, #1 801ad86: f7ff febf bl 801ab08 <_Balloc> 801ad8a: 4602 mov r2, r0 801ad8c: b928 cbnz r0, 801ad9a <__i2b+0x1a> 801ad8e: 4b05 ldr r3, [pc, #20] @ (801ada4 <__i2b+0x24>) 801ad90: 4805 ldr r0, [pc, #20] @ (801ada8 <__i2b+0x28>) 801ad92: f240 1145 movw r1, #325 @ 0x145 801ad96: f001 fdef bl 801c978 <__assert_func> 801ad9a: 2301 movs r3, #1 801ad9c: 6144 str r4, [r0, #20] 801ad9e: 6103 str r3, [r0, #16] 801ada0: bd10 pop {r4, pc} 801ada2: bf00 nop 801ada4: 0801dd65 .word 0x0801dd65 801ada8: 0801dd76 .word 0x0801dd76 0801adac <__multiply>: 801adac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801adb0: f8d1 9010 ldr.w r9, [r1, #16] 801adb4: f8d2 a010 ldr.w sl, [r2, #16] 801adb8: 45d1 cmp r9, sl 801adba: b085 sub sp, #20 801adbc: 4688 mov r8, r1 801adbe: 4614 mov r4, r2 801adc0: db04 blt.n 801adcc <__multiply+0x20> 801adc2: 4653 mov r3, sl 801adc4: 460c mov r4, r1 801adc6: 46ca mov sl, r9 801adc8: 4690 mov r8, r2 801adca: 4699 mov r9, r3 801adcc: 68a3 ldr r3, [r4, #8] 801adce: 6861 ldr r1, [r4, #4] 801add0: eb0a 0609 add.w r6, sl, r9 801add4: 42b3 cmp r3, r6 801add6: bfb8 it lt 801add8: 3101 addlt r1, #1 801adda: f7ff fe95 bl 801ab08 <_Balloc> 801adde: b930 cbnz r0, 801adee <__multiply+0x42> 801ade0: 4602 mov r2, r0 801ade2: 4b45 ldr r3, [pc, #276] @ (801aef8 <__multiply+0x14c>) 801ade4: 4845 ldr r0, [pc, #276] @ (801aefc <__multiply+0x150>) 801ade6: f44f 71b1 mov.w r1, #354 @ 0x162 801adea: f001 fdc5 bl 801c978 <__assert_func> 801adee: f100 0514 add.w r5, r0, #20 801adf2: eb05 0786 add.w r7, r5, r6, lsl #2 801adf6: 462b mov r3, r5 801adf8: 2200 movs r2, #0 801adfa: 42bb cmp r3, r7 801adfc: d31f bcc.n 801ae3e <__multiply+0x92> 801adfe: f104 0c14 add.w ip, r4, #20 801ae02: f108 0114 add.w r1, r8, #20 801ae06: eb0c 038a add.w r3, ip, sl, lsl #2 801ae0a: eb01 0289 add.w r2, r1, r9, lsl #2 801ae0e: 9202 str r2, [sp, #8] 801ae10: 1b1a subs r2, r3, r4 801ae12: 3a15 subs r2, #21 801ae14: f022 0203 bic.w r2, r2, #3 801ae18: 3415 adds r4, #21 801ae1a: 429c cmp r4, r3 801ae1c: bf88 it hi 801ae1e: 2200 movhi r2, #0 801ae20: 9201 str r2, [sp, #4] 801ae22: 9a02 ldr r2, [sp, #8] 801ae24: 9103 str r1, [sp, #12] 801ae26: 428a cmp r2, r1 801ae28: d80c bhi.n 801ae44 <__multiply+0x98> 801ae2a: 2e00 cmp r6, #0 801ae2c: dd03 ble.n 801ae36 <__multiply+0x8a> 801ae2e: f857 3d04 ldr.w r3, [r7, #-4]! 801ae32: 2b00 cmp r3, #0 801ae34: d05d beq.n 801aef2 <__multiply+0x146> 801ae36: 6106 str r6, [r0, #16] 801ae38: b005 add sp, #20 801ae3a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801ae3e: f843 2b04 str.w r2, [r3], #4 801ae42: e7da b.n 801adfa <__multiply+0x4e> 801ae44: f8b1 a000 ldrh.w sl, [r1] 801ae48: f1ba 0f00 cmp.w sl, #0 801ae4c: d024 beq.n 801ae98 <__multiply+0xec> 801ae4e: 46e0 mov r8, ip 801ae50: 46a9 mov r9, r5 801ae52: f04f 0e00 mov.w lr, #0 801ae56: f858 2b04 ldr.w r2, [r8], #4 801ae5a: f8d9 4000 ldr.w r4, [r9] 801ae5e: fa1f fb82 uxth.w fp, r2 801ae62: b2a4 uxth r4, r4 801ae64: fb0a 440b mla r4, sl, fp, r4 801ae68: ea4f 4b12 mov.w fp, r2, lsr #16 801ae6c: f8d9 2000 ldr.w r2, [r9] 801ae70: 4474 add r4, lr 801ae72: ea4f 4e12 mov.w lr, r2, lsr #16 801ae76: fb0a e20b mla r2, sl, fp, lr 801ae7a: eb02 4214 add.w r2, r2, r4, lsr #16 801ae7e: b2a4 uxth r4, r4 801ae80: ea44 4402 orr.w r4, r4, r2, lsl #16 801ae84: 4543 cmp r3, r8 801ae86: f849 4b04 str.w r4, [r9], #4 801ae8a: ea4f 4e12 mov.w lr, r2, lsr #16 801ae8e: d8e2 bhi.n 801ae56 <__multiply+0xaa> 801ae90: 9a01 ldr r2, [sp, #4] 801ae92: 18aa adds r2, r5, r2 801ae94: f8c2 e004 str.w lr, [r2, #4] 801ae98: 9a03 ldr r2, [sp, #12] 801ae9a: f8b2 8002 ldrh.w r8, [r2, #2] 801ae9e: 3104 adds r1, #4 801aea0: f1b8 0f00 cmp.w r8, #0 801aea4: d023 beq.n 801aeee <__multiply+0x142> 801aea6: 682a ldr r2, [r5, #0] 801aea8: 46e6 mov lr, ip 801aeaa: 4691 mov r9, r2 801aeac: 46aa mov sl, r5 801aeae: f04f 0b00 mov.w fp, #0 801aeb2: f8be 4000 ldrh.w r4, [lr] 801aeb6: fb08 b404 mla r4, r8, r4, fp 801aeba: eb04 4419 add.w r4, r4, r9, lsr #16 801aebe: b292 uxth r2, r2 801aec0: ea42 4204 orr.w r2, r2, r4, lsl #16 801aec4: f84a 2b04 str.w r2, [sl], #4 801aec8: f85e 2b04 ldr.w r2, [lr], #4 801aecc: f8da 9000 ldr.w r9, [sl] 801aed0: ea4f 4b12 mov.w fp, r2, lsr #16 801aed4: fa1f f289 uxth.w r2, r9 801aed8: fb08 220b mla r2, r8, fp, r2 801aedc: eb02 4214 add.w r2, r2, r4, lsr #16 801aee0: 4573 cmp r3, lr 801aee2: ea4f 4b12 mov.w fp, r2, lsr #16 801aee6: d8e4 bhi.n 801aeb2 <__multiply+0x106> 801aee8: 9c01 ldr r4, [sp, #4] 801aeea: 192c adds r4, r5, r4 801aeec: 6062 str r2, [r4, #4] 801aeee: 3504 adds r5, #4 801aef0: e797 b.n 801ae22 <__multiply+0x76> 801aef2: 3e01 subs r6, #1 801aef4: e799 b.n 801ae2a <__multiply+0x7e> 801aef6: bf00 nop 801aef8: 0801dd65 .word 0x0801dd65 801aefc: 0801dd76 .word 0x0801dd76 0801af00 <__pow5mult>: 801af00: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801af04: 4617 mov r7, r2 801af06: f012 0203 ands.w r2, r2, #3 801af0a: 4680 mov r8, r0 801af0c: 460d mov r5, r1 801af0e: d007 beq.n 801af20 <__pow5mult+0x20> 801af10: 4c26 ldr r4, [pc, #152] @ (801afac <__pow5mult+0xac>) 801af12: 3a01 subs r2, #1 801af14: 2300 movs r3, #0 801af16: f854 2022 ldr.w r2, [r4, r2, lsl #2] 801af1a: f7ff fe55 bl 801abc8 <__multadd> 801af1e: 4605 mov r5, r0 801af20: 10bf asrs r7, r7, #2 801af22: d03f beq.n 801afa4 <__pow5mult+0xa4> 801af24: f8d8 401c ldr.w r4, [r8, #28] 801af28: b994 cbnz r4, 801af50 <__pow5mult+0x50> 801af2a: 2010 movs r0, #16 801af2c: f7ff fd36 bl 801a99c 801af30: 4604 mov r4, r0 801af32: f8c8 001c str.w r0, [r8, #28] 801af36: b930 cbnz r0, 801af46 <__pow5mult+0x46> 801af38: 4602 mov r2, r0 801af3a: 4b1d ldr r3, [pc, #116] @ (801afb0 <__pow5mult+0xb0>) 801af3c: 481d ldr r0, [pc, #116] @ (801afb4 <__pow5mult+0xb4>) 801af3e: f240 11b3 movw r1, #435 @ 0x1b3 801af42: f001 fd19 bl 801c978 <__assert_func> 801af46: 2300 movs r3, #0 801af48: e9c0 3301 strd r3, r3, [r0, #4] 801af4c: 6003 str r3, [r0, #0] 801af4e: 60c3 str r3, [r0, #12] 801af50: 68a6 ldr r6, [r4, #8] 801af52: b946 cbnz r6, 801af66 <__pow5mult+0x66> 801af54: f240 2171 movw r1, #625 @ 0x271 801af58: 4640 mov r0, r8 801af5a: f7ff ff11 bl 801ad80 <__i2b> 801af5e: 2300 movs r3, #0 801af60: 60a0 str r0, [r4, #8] 801af62: 4606 mov r6, r0 801af64: 6003 str r3, [r0, #0] 801af66: 462c mov r4, r5 801af68: f04f 0900 mov.w r9, #0 801af6c: f007 0301 and.w r3, r7, #1 801af70: 107f asrs r7, r7, #1 801af72: b153 cbz r3, 801af8a <__pow5mult+0x8a> 801af74: 4629 mov r1, r5 801af76: 4632 mov r2, r6 801af78: 4640 mov r0, r8 801af7a: f7ff ff17 bl 801adac <__multiply> 801af7e: 4621 mov r1, r4 801af80: 4605 mov r5, r0 801af82: 4640 mov r0, r8 801af84: f7ff fdfe bl 801ab84 <_Bfree> 801af88: b167 cbz r7, 801afa4 <__pow5mult+0xa4> 801af8a: 6830 ldr r0, [r6, #0] 801af8c: b938 cbnz r0, 801af9e <__pow5mult+0x9e> 801af8e: 4632 mov r2, r6 801af90: 4631 mov r1, r6 801af92: 4640 mov r0, r8 801af94: f7ff ff0a bl 801adac <__multiply> 801af98: 6030 str r0, [r6, #0] 801af9a: f8c0 9000 str.w r9, [r0] 801af9e: 4606 mov r6, r0 801afa0: 462c mov r4, r5 801afa2: e7e3 b.n 801af6c <__pow5mult+0x6c> 801afa4: 4628 mov r0, r5 801afa6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801afaa: bf00 nop 801afac: 0801de88 .word 0x0801de88 801afb0: 0801dcf6 .word 0x0801dcf6 801afb4: 0801dd76 .word 0x0801dd76 0801afb8 <__lshift>: 801afb8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801afbc: 460c mov r4, r1 801afbe: 6849 ldr r1, [r1, #4] 801afc0: 6923 ldr r3, [r4, #16] 801afc2: eb03 1862 add.w r8, r3, r2, asr #5 801afc6: 68a3 ldr r3, [r4, #8] 801afc8: 4607 mov r7, r0 801afca: 4615 mov r5, r2 801afcc: ea4f 1a62 mov.w sl, r2, asr #5 801afd0: f108 0901 add.w r9, r8, #1 801afd4: 454b cmp r3, r9 801afd6: db0b blt.n 801aff0 <__lshift+0x38> 801afd8: 4638 mov r0, r7 801afda: f7ff fd95 bl 801ab08 <_Balloc> 801afde: 4606 mov r6, r0 801afe0: b948 cbnz r0, 801aff6 <__lshift+0x3e> 801afe2: 4602 mov r2, r0 801afe4: 4b29 ldr r3, [pc, #164] @ (801b08c <__lshift+0xd4>) 801afe6: 482a ldr r0, [pc, #168] @ (801b090 <__lshift+0xd8>) 801afe8: f44f 71ef mov.w r1, #478 @ 0x1de 801afec: f001 fcc4 bl 801c978 <__assert_func> 801aff0: 3101 adds r1, #1 801aff2: 005b lsls r3, r3, #1 801aff4: e7ee b.n 801afd4 <__lshift+0x1c> 801aff6: 2300 movs r3, #0 801aff8: f100 0c14 add.w ip, r0, #20 801affc: f100 0210 add.w r2, r0, #16 801b000: 4619 mov r1, r3 801b002: 4553 cmp r3, sl 801b004: db35 blt.n 801b072 <__lshift+0xba> 801b006: 6922 ldr r2, [r4, #16] 801b008: ea2a 7aea bic.w sl, sl, sl, asr #31 801b00c: eb0c 0c8a add.w ip, ip, sl, lsl #2 801b010: f104 0314 add.w r3, r4, #20 801b014: f015 0e1f ands.w lr, r5, #31 801b018: 4661 mov r1, ip 801b01a: eb03 0282 add.w r2, r3, r2, lsl #2 801b01e: d02c beq.n 801b07a <__lshift+0xc2> 801b020: f1ce 0a20 rsb sl, lr, #32 801b024: 2500 movs r5, #0 801b026: 6818 ldr r0, [r3, #0] 801b028: 468b mov fp, r1 801b02a: fa00 f00e lsl.w r0, r0, lr 801b02e: 4328 orrs r0, r5 801b030: f8cb 0000 str.w r0, [fp] 801b034: f853 5b04 ldr.w r5, [r3], #4 801b038: 429a cmp r2, r3 801b03a: f101 0104 add.w r1, r1, #4 801b03e: fa25 f50a lsr.w r5, r5, sl 801b042: d8f0 bhi.n 801b026 <__lshift+0x6e> 801b044: 1b13 subs r3, r2, r4 801b046: 3b15 subs r3, #21 801b048: f023 0303 bic.w r3, r3, #3 801b04c: f104 0115 add.w r1, r4, #21 801b050: 428a cmp r2, r1 801b052: bf38 it cc 801b054: 2300 movcc r3, #0 801b056: 449c add ip, r3 801b058: f8cc 5004 str.w r5, [ip, #4] 801b05c: b905 cbnz r5, 801b060 <__lshift+0xa8> 801b05e: 46c1 mov r9, r8 801b060: 4638 mov r0, r7 801b062: f8c6 9010 str.w r9, [r6, #16] 801b066: 4621 mov r1, r4 801b068: f7ff fd8c bl 801ab84 <_Bfree> 801b06c: 4630 mov r0, r6 801b06e: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 801b072: f842 1f04 str.w r1, [r2, #4]! 801b076: 3301 adds r3, #1 801b078: e7c3 b.n 801b002 <__lshift+0x4a> 801b07a: f853 5b04 ldr.w r5, [r3], #4 801b07e: 600d str r5, [r1, #0] 801b080: 429a cmp r2, r3 801b082: f101 0104 add.w r1, r1, #4 801b086: d8f8 bhi.n 801b07a <__lshift+0xc2> 801b088: e7e9 b.n 801b05e <__lshift+0xa6> 801b08a: bf00 nop 801b08c: 0801dd65 .word 0x0801dd65 801b090: 0801dd76 .word 0x0801dd76 0801b094 <__mcmp>: 801b094: 690a ldr r2, [r1, #16] 801b096: 4603 mov r3, r0 801b098: 6900 ldr r0, [r0, #16] 801b09a: 1a80 subs r0, r0, r2 801b09c: b530 push {r4, r5, lr} 801b09e: d10e bne.n 801b0be <__mcmp+0x2a> 801b0a0: 3314 adds r3, #20 801b0a2: 3114 adds r1, #20 801b0a4: eb03 0482 add.w r4, r3, r2, lsl #2 801b0a8: eb01 0182 add.w r1, r1, r2, lsl #2 801b0ac: f854 5d04 ldr.w r5, [r4, #-4]! 801b0b0: f851 2d04 ldr.w r2, [r1, #-4]! 801b0b4: 4295 cmp r5, r2 801b0b6: d003 beq.n 801b0c0 <__mcmp+0x2c> 801b0b8: d205 bcs.n 801b0c6 <__mcmp+0x32> 801b0ba: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801b0be: bd30 pop {r4, r5, pc} 801b0c0: 42a3 cmp r3, r4 801b0c2: d3f3 bcc.n 801b0ac <__mcmp+0x18> 801b0c4: e7fb b.n 801b0be <__mcmp+0x2a> 801b0c6: 2001 movs r0, #1 801b0c8: e7f9 b.n 801b0be <__mcmp+0x2a> ... 0801b0cc <__mdiff>: 801b0cc: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801b0d0: 468a mov sl, r1 801b0d2: 4606 mov r6, r0 801b0d4: 4611 mov r1, r2 801b0d6: 4650 mov r0, sl 801b0d8: 4614 mov r4, r2 801b0da: f7ff ffdb bl 801b094 <__mcmp> 801b0de: 1e05 subs r5, r0, #0 801b0e0: d112 bne.n 801b108 <__mdiff+0x3c> 801b0e2: 4629 mov r1, r5 801b0e4: 4630 mov r0, r6 801b0e6: f7ff fd0f bl 801ab08 <_Balloc> 801b0ea: 4602 mov r2, r0 801b0ec: b928 cbnz r0, 801b0fa <__mdiff+0x2e> 801b0ee: 4b41 ldr r3, [pc, #260] @ (801b1f4 <__mdiff+0x128>) 801b0f0: f240 2137 movw r1, #567 @ 0x237 801b0f4: 4840 ldr r0, [pc, #256] @ (801b1f8 <__mdiff+0x12c>) 801b0f6: f001 fc3f bl 801c978 <__assert_func> 801b0fa: 2301 movs r3, #1 801b0fc: e9c0 3504 strd r3, r5, [r0, #16] 801b100: 4610 mov r0, r2 801b102: b003 add sp, #12 801b104: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801b108: bfbc itt lt 801b10a: 4653 movlt r3, sl 801b10c: 46a2 movlt sl, r4 801b10e: 4630 mov r0, r6 801b110: f8da 1004 ldr.w r1, [sl, #4] 801b114: bfba itte lt 801b116: 461c movlt r4, r3 801b118: 2501 movlt r5, #1 801b11a: 2500 movge r5, #0 801b11c: f7ff fcf4 bl 801ab08 <_Balloc> 801b120: 4602 mov r2, r0 801b122: b918 cbnz r0, 801b12c <__mdiff+0x60> 801b124: 4b33 ldr r3, [pc, #204] @ (801b1f4 <__mdiff+0x128>) 801b126: f240 2145 movw r1, #581 @ 0x245 801b12a: e7e3 b.n 801b0f4 <__mdiff+0x28> 801b12c: f8da 7010 ldr.w r7, [sl, #16] 801b130: 6926 ldr r6, [r4, #16] 801b132: 60c5 str r5, [r0, #12] 801b134: f10a 0914 add.w r9, sl, #20 801b138: f104 0e14 add.w lr, r4, #20 801b13c: f100 0514 add.w r5, r0, #20 801b140: f10a 0310 add.w r3, sl, #16 801b144: eb09 0887 add.w r8, r9, r7, lsl #2 801b148: eb0e 0686 add.w r6, lr, r6, lsl #2 801b14c: 9301 str r3, [sp, #4] 801b14e: 46ab mov fp, r5 801b150: f04f 0c00 mov.w ip, #0 801b154: 9b01 ldr r3, [sp, #4] 801b156: f85e 0b04 ldr.w r0, [lr], #4 801b15a: f853 af04 ldr.w sl, [r3, #4]! 801b15e: 9301 str r3, [sp, #4] 801b160: fa1f f38a uxth.w r3, sl 801b164: 4619 mov r1, r3 801b166: b283 uxth r3, r0 801b168: 1acb subs r3, r1, r3 801b16a: 0c00 lsrs r0, r0, #16 801b16c: 4463 add r3, ip 801b16e: ebc0 401a rsb r0, r0, sl, lsr #16 801b172: eb00 4023 add.w r0, r0, r3, asr #16 801b176: b29b uxth r3, r3 801b178: ea43 4300 orr.w r3, r3, r0, lsl #16 801b17c: 4576 cmp r6, lr 801b17e: f84b 3b04 str.w r3, [fp], #4 801b182: ea4f 4c20 mov.w ip, r0, asr #16 801b186: d8e5 bhi.n 801b154 <__mdiff+0x88> 801b188: 1b33 subs r3, r6, r4 801b18a: 3b15 subs r3, #21 801b18c: 3415 adds r4, #21 801b18e: f023 0303 bic.w r3, r3, #3 801b192: 42a6 cmp r6, r4 801b194: bf38 it cc 801b196: 2300 movcc r3, #0 801b198: 18e8 adds r0, r5, r3 801b19a: 444b add r3, r9 801b19c: 1d1c adds r4, r3, #4 801b19e: 3004 adds r0, #4 801b1a0: 4626 mov r6, r4 801b1a2: eba5 0509 sub.w r5, r5, r9 801b1a6: 4546 cmp r6, r8 801b1a8: eb06 0e05 add.w lr, r6, r5 801b1ac: d30e bcc.n 801b1cc <__mdiff+0x100> 801b1ae: f108 0103 add.w r1, r8, #3 801b1b2: 1b09 subs r1, r1, r4 801b1b4: f021 0103 bic.w r1, r1, #3 801b1b8: 3301 adds r3, #1 801b1ba: 4598 cmp r8, r3 801b1bc: bf38 it cc 801b1be: 2100 movcc r1, #0 801b1c0: 4401 add r1, r0 801b1c2: f851 3d04 ldr.w r3, [r1, #-4]! 801b1c6: b19b cbz r3, 801b1f0 <__mdiff+0x124> 801b1c8: 6117 str r7, [r2, #16] 801b1ca: e799 b.n 801b100 <__mdiff+0x34> 801b1cc: f856 1b04 ldr.w r1, [r6], #4 801b1d0: 46e2 mov sl, ip 801b1d2: ea4f 4911 mov.w r9, r1, lsr #16 801b1d6: fa1c fc81 uxtah ip, ip, r1 801b1da: 4451 add r1, sl 801b1dc: eb09 492c add.w r9, r9, ip, asr #16 801b1e0: b289 uxth r1, r1 801b1e2: ea41 4109 orr.w r1, r1, r9, lsl #16 801b1e6: ea4f 4c29 mov.w ip, r9, asr #16 801b1ea: f8ce 1000 str.w r1, [lr] 801b1ee: e7da b.n 801b1a6 <__mdiff+0xda> 801b1f0: 3f01 subs r7, #1 801b1f2: e7e6 b.n 801b1c2 <__mdiff+0xf6> 801b1f4: 0801dd65 .word 0x0801dd65 801b1f8: 0801dd76 .word 0x0801dd76 0801b1fc <__ulp>: 801b1fc: b082 sub sp, #8 801b1fe: ed8d 0b00 vstr d0, [sp] 801b202: 9a01 ldr r2, [sp, #4] 801b204: 4b0f ldr r3, [pc, #60] @ (801b244 <__ulp+0x48>) 801b206: 4013 ands r3, r2 801b208: f1a3 7350 sub.w r3, r3, #54525952 @ 0x3400000 801b20c: 2b00 cmp r3, #0 801b20e: dc08 bgt.n 801b222 <__ulp+0x26> 801b210: 425b negs r3, r3 801b212: f1b3 7fa0 cmp.w r3, #20971520 @ 0x1400000 801b216: ea4f 5223 mov.w r2, r3, asr #20 801b21a: da04 bge.n 801b226 <__ulp+0x2a> 801b21c: f44f 2300 mov.w r3, #524288 @ 0x80000 801b220: 4113 asrs r3, r2 801b222: 2200 movs r2, #0 801b224: e008 b.n 801b238 <__ulp+0x3c> 801b226: f1a2 0314 sub.w r3, r2, #20 801b22a: 2b1e cmp r3, #30 801b22c: bfda itte le 801b22e: f04f 4200 movle.w r2, #2147483648 @ 0x80000000 801b232: 40da lsrle r2, r3 801b234: 2201 movgt r2, #1 801b236: 2300 movs r3, #0 801b238: 4619 mov r1, r3 801b23a: 4610 mov r0, r2 801b23c: ec41 0b10 vmov d0, r0, r1 801b240: b002 add sp, #8 801b242: 4770 bx lr 801b244: 7ff00000 .word 0x7ff00000 0801b248 <__b2d>: 801b248: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801b24c: 6906 ldr r6, [r0, #16] 801b24e: f100 0814 add.w r8, r0, #20 801b252: eb08 0686 add.w r6, r8, r6, lsl #2 801b256: 1f37 subs r7, r6, #4 801b258: f856 2c04 ldr.w r2, [r6, #-4] 801b25c: 4610 mov r0, r2 801b25e: f7ff fd43 bl 801ace8 <__hi0bits> 801b262: f1c0 0320 rsb r3, r0, #32 801b266: 280a cmp r0, #10 801b268: 600b str r3, [r1, #0] 801b26a: 491b ldr r1, [pc, #108] @ (801b2d8 <__b2d+0x90>) 801b26c: dc15 bgt.n 801b29a <__b2d+0x52> 801b26e: f1c0 0c0b rsb ip, r0, #11 801b272: fa22 f30c lsr.w r3, r2, ip 801b276: 45b8 cmp r8, r7 801b278: ea43 0501 orr.w r5, r3, r1 801b27c: bf34 ite cc 801b27e: f856 3c08 ldrcc.w r3, [r6, #-8] 801b282: 2300 movcs r3, #0 801b284: 3015 adds r0, #21 801b286: fa02 f000 lsl.w r0, r2, r0 801b28a: fa23 f30c lsr.w r3, r3, ip 801b28e: 4303 orrs r3, r0 801b290: 461c mov r4, r3 801b292: ec45 4b10 vmov d0, r4, r5 801b296: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801b29a: 45b8 cmp r8, r7 801b29c: bf3a itte cc 801b29e: f856 3c08 ldrcc.w r3, [r6, #-8] 801b2a2: f1a6 0708 subcc.w r7, r6, #8 801b2a6: 2300 movcs r3, #0 801b2a8: 380b subs r0, #11 801b2aa: d012 beq.n 801b2d2 <__b2d+0x8a> 801b2ac: f1c0 0120 rsb r1, r0, #32 801b2b0: fa23 f401 lsr.w r4, r3, r1 801b2b4: 4082 lsls r2, r0 801b2b6: 4322 orrs r2, r4 801b2b8: 4547 cmp r7, r8 801b2ba: f042 557f orr.w r5, r2, #1069547520 @ 0x3fc00000 801b2be: bf8c ite hi 801b2c0: f857 2c04 ldrhi.w r2, [r7, #-4] 801b2c4: 2200 movls r2, #0 801b2c6: 4083 lsls r3, r0 801b2c8: 40ca lsrs r2, r1 801b2ca: f445 1540 orr.w r5, r5, #3145728 @ 0x300000 801b2ce: 4313 orrs r3, r2 801b2d0: e7de b.n 801b290 <__b2d+0x48> 801b2d2: ea42 0501 orr.w r5, r2, r1 801b2d6: e7db b.n 801b290 <__b2d+0x48> 801b2d8: 3ff00000 .word 0x3ff00000 0801b2dc <__d2b>: 801b2dc: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 801b2e0: 460f mov r7, r1 801b2e2: 2101 movs r1, #1 801b2e4: ec59 8b10 vmov r8, r9, d0 801b2e8: 4616 mov r6, r2 801b2ea: f7ff fc0d bl 801ab08 <_Balloc> 801b2ee: 4604 mov r4, r0 801b2f0: b930 cbnz r0, 801b300 <__d2b+0x24> 801b2f2: 4602 mov r2, r0 801b2f4: 4b23 ldr r3, [pc, #140] @ (801b384 <__d2b+0xa8>) 801b2f6: 4824 ldr r0, [pc, #144] @ (801b388 <__d2b+0xac>) 801b2f8: f240 310f movw r1, #783 @ 0x30f 801b2fc: f001 fb3c bl 801c978 <__assert_func> 801b300: f3c9 550a ubfx r5, r9, #20, #11 801b304: f3c9 0313 ubfx r3, r9, #0, #20 801b308: b10d cbz r5, 801b30e <__d2b+0x32> 801b30a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 801b30e: 9301 str r3, [sp, #4] 801b310: f1b8 0300 subs.w r3, r8, #0 801b314: d023 beq.n 801b35e <__d2b+0x82> 801b316: 4668 mov r0, sp 801b318: 9300 str r3, [sp, #0] 801b31a: f7ff fd04 bl 801ad26 <__lo0bits> 801b31e: 9900 ldr r1, [sp, #0] 801b320: b1d8 cbz r0, 801b35a <__d2b+0x7e> 801b322: 9a01 ldr r2, [sp, #4] 801b324: f1c0 0320 rsb r3, r0, #32 801b328: fa02 f303 lsl.w r3, r2, r3 801b32c: 430b orrs r3, r1 801b32e: 40c2 lsrs r2, r0 801b330: 6163 str r3, [r4, #20] 801b332: 9201 str r2, [sp, #4] 801b334: 9b01 ldr r3, [sp, #4] 801b336: 61a3 str r3, [r4, #24] 801b338: 2b00 cmp r3, #0 801b33a: bf0c ite eq 801b33c: 2201 moveq r2, #1 801b33e: 2202 movne r2, #2 801b340: 6122 str r2, [r4, #16] 801b342: b1a5 cbz r5, 801b36e <__d2b+0x92> 801b344: f2a5 4533 subw r5, r5, #1075 @ 0x433 801b348: 4405 add r5, r0 801b34a: 603d str r5, [r7, #0] 801b34c: f1c0 0035 rsb r0, r0, #53 @ 0x35 801b350: 6030 str r0, [r6, #0] 801b352: 4620 mov r0, r4 801b354: b003 add sp, #12 801b356: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 801b35a: 6161 str r1, [r4, #20] 801b35c: e7ea b.n 801b334 <__d2b+0x58> 801b35e: a801 add r0, sp, #4 801b360: f7ff fce1 bl 801ad26 <__lo0bits> 801b364: 9b01 ldr r3, [sp, #4] 801b366: 6163 str r3, [r4, #20] 801b368: 3020 adds r0, #32 801b36a: 2201 movs r2, #1 801b36c: e7e8 b.n 801b340 <__d2b+0x64> 801b36e: eb04 0382 add.w r3, r4, r2, lsl #2 801b372: f2a0 4032 subw r0, r0, #1074 @ 0x432 801b376: 6038 str r0, [r7, #0] 801b378: 6918 ldr r0, [r3, #16] 801b37a: f7ff fcb5 bl 801ace8 <__hi0bits> 801b37e: ebc0 1042 rsb r0, r0, r2, lsl #5 801b382: e7e5 b.n 801b350 <__d2b+0x74> 801b384: 0801dd65 .word 0x0801dd65 801b388: 0801dd76 .word 0x0801dd76 0801b38c <__ratio>: 801b38c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801b390: b085 sub sp, #20 801b392: e9cd 1000 strd r1, r0, [sp] 801b396: a902 add r1, sp, #8 801b398: f7ff ff56 bl 801b248 <__b2d> 801b39c: 9800 ldr r0, [sp, #0] 801b39e: a903 add r1, sp, #12 801b3a0: ec55 4b10 vmov r4, r5, d0 801b3a4: f7ff ff50 bl 801b248 <__b2d> 801b3a8: 9b01 ldr r3, [sp, #4] 801b3aa: 6919 ldr r1, [r3, #16] 801b3ac: 9b00 ldr r3, [sp, #0] 801b3ae: 691b ldr r3, [r3, #16] 801b3b0: 1ac9 subs r1, r1, r3 801b3b2: e9dd 3202 ldrd r3, r2, [sp, #8] 801b3b6: 1a9b subs r3, r3, r2 801b3b8: ec5b ab10 vmov sl, fp, d0 801b3bc: eb03 1341 add.w r3, r3, r1, lsl #5 801b3c0: 2b00 cmp r3, #0 801b3c2: bfce itee gt 801b3c4: 462a movgt r2, r5 801b3c6: ebc3 3303 rsble r3, r3, r3, lsl #12 801b3ca: 465a movle r2, fp 801b3cc: 462f mov r7, r5 801b3ce: 46d9 mov r9, fp 801b3d0: bfcc ite gt 801b3d2: eb02 5703 addgt.w r7, r2, r3, lsl #20 801b3d6: eb02 5903 addle.w r9, r2, r3, lsl #20 801b3da: 464b mov r3, r9 801b3dc: 4652 mov r2, sl 801b3de: 4620 mov r0, r4 801b3e0: 4639 mov r1, r7 801b3e2: f7e5 fa0b bl 80007fc <__aeabi_ddiv> 801b3e6: ec41 0b10 vmov d0, r0, r1 801b3ea: b005 add sp, #20 801b3ec: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 0801b3f0 <__copybits>: 801b3f0: 3901 subs r1, #1 801b3f2: b570 push {r4, r5, r6, lr} 801b3f4: 1149 asrs r1, r1, #5 801b3f6: 6914 ldr r4, [r2, #16] 801b3f8: 3101 adds r1, #1 801b3fa: f102 0314 add.w r3, r2, #20 801b3fe: eb00 0181 add.w r1, r0, r1, lsl #2 801b402: eb03 0484 add.w r4, r3, r4, lsl #2 801b406: 1f05 subs r5, r0, #4 801b408: 42a3 cmp r3, r4 801b40a: d30c bcc.n 801b426 <__copybits+0x36> 801b40c: 1aa3 subs r3, r4, r2 801b40e: 3b11 subs r3, #17 801b410: f023 0303 bic.w r3, r3, #3 801b414: 3211 adds r2, #17 801b416: 4294 cmp r4, r2 801b418: bf38 it cc 801b41a: 2300 movcc r3, #0 801b41c: 4418 add r0, r3 801b41e: 2300 movs r3, #0 801b420: 4288 cmp r0, r1 801b422: d305 bcc.n 801b430 <__copybits+0x40> 801b424: bd70 pop {r4, r5, r6, pc} 801b426: f853 6b04 ldr.w r6, [r3], #4 801b42a: f845 6f04 str.w r6, [r5, #4]! 801b42e: e7eb b.n 801b408 <__copybits+0x18> 801b430: f840 3b04 str.w r3, [r0], #4 801b434: e7f4 b.n 801b420 <__copybits+0x30> 0801b436 <__any_on>: 801b436: f100 0214 add.w r2, r0, #20 801b43a: 6900 ldr r0, [r0, #16] 801b43c: 114b asrs r3, r1, #5 801b43e: 4298 cmp r0, r3 801b440: b510 push {r4, lr} 801b442: db11 blt.n 801b468 <__any_on+0x32> 801b444: dd0a ble.n 801b45c <__any_on+0x26> 801b446: f011 011f ands.w r1, r1, #31 801b44a: d007 beq.n 801b45c <__any_on+0x26> 801b44c: f852 4023 ldr.w r4, [r2, r3, lsl #2] 801b450: fa24 f001 lsr.w r0, r4, r1 801b454: fa00 f101 lsl.w r1, r0, r1 801b458: 428c cmp r4, r1 801b45a: d10b bne.n 801b474 <__any_on+0x3e> 801b45c: eb02 0383 add.w r3, r2, r3, lsl #2 801b460: 4293 cmp r3, r2 801b462: d803 bhi.n 801b46c <__any_on+0x36> 801b464: 2000 movs r0, #0 801b466: bd10 pop {r4, pc} 801b468: 4603 mov r3, r0 801b46a: e7f7 b.n 801b45c <__any_on+0x26> 801b46c: f853 1d04 ldr.w r1, [r3, #-4]! 801b470: 2900 cmp r1, #0 801b472: d0f5 beq.n 801b460 <__any_on+0x2a> 801b474: 2001 movs r0, #1 801b476: e7f6 b.n 801b466 <__any_on+0x30> 0801b478 : 801b478: b570 push {r4, r5, r6, lr} 801b47a: 4604 mov r4, r0 801b47c: 460d mov r5, r1 801b47e: ec45 4b10 vmov d0, r4, r5 801b482: 4616 mov r6, r2 801b484: f7ff feba bl 801b1fc <__ulp> 801b488: ec51 0b10 vmov r0, r1, d0 801b48c: b17e cbz r6, 801b4ae 801b48e: f3c5 530a ubfx r3, r5, #20, #11 801b492: f1c3 036b rsb r3, r3, #107 @ 0x6b 801b496: 2b00 cmp r3, #0 801b498: dd09 ble.n 801b4ae 801b49a: 051b lsls r3, r3, #20 801b49c: f103 557f add.w r5, r3, #1069547520 @ 0x3fc00000 801b4a0: 2400 movs r4, #0 801b4a2: f505 1540 add.w r5, r5, #3145728 @ 0x300000 801b4a6: 4622 mov r2, r4 801b4a8: 462b mov r3, r5 801b4aa: f7e5 f87d bl 80005a8 <__aeabi_dmul> 801b4ae: ec41 0b10 vmov d0, r0, r1 801b4b2: bd70 pop {r4, r5, r6, pc} 801b4b4: 0000 movs r0, r0 ... 0801b4b8 <_strtod_l>: 801b4b8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801b4bc: b09d sub sp, #116 @ 0x74 801b4be: 460e mov r6, r1 801b4c0: 9215 str r2, [sp, #84] @ 0x54 801b4c2: 2200 movs r2, #0 801b4c4: 9004 str r0, [sp, #16] 801b4c6: 9218 str r2, [sp, #96] @ 0x60 801b4c8: f04f 0800 mov.w r8, #0 801b4cc: f04f 0900 mov.w r9, #0 801b4d0: 9117 str r1, [sp, #92] @ 0x5c 801b4d2: 780a ldrb r2, [r1, #0] 801b4d4: 2a2b cmp r2, #43 @ 0x2b 801b4d6: 460d mov r5, r1 801b4d8: f101 0101 add.w r1, r1, #1 801b4dc: d01d beq.n 801b51a <_strtod_l+0x62> 801b4de: d80b bhi.n 801b4f8 <_strtod_l+0x40> 801b4e0: 2a0d cmp r2, #13 801b4e2: d806 bhi.n 801b4f2 <_strtod_l+0x3a> 801b4e4: 2a08 cmp r2, #8 801b4e6: d8f3 bhi.n 801b4d0 <_strtod_l+0x18> 801b4e8: b17a cbz r2, 801b50a <_strtod_l+0x52> 801b4ea: 2300 movs r3, #0 801b4ec: 930b str r3, [sp, #44] @ 0x2c 801b4ee: 469a mov sl, r3 801b4f0: e083 b.n 801b5fa <_strtod_l+0x142> 801b4f2: 2a20 cmp r2, #32 801b4f4: d0ec beq.n 801b4d0 <_strtod_l+0x18> 801b4f6: e7f8 b.n 801b4ea <_strtod_l+0x32> 801b4f8: 2a2d cmp r2, #45 @ 0x2d 801b4fa: d110 bne.n 801b51e <_strtod_l+0x66> 801b4fc: 2201 movs r2, #1 801b4fe: 1c69 adds r1, r5, #1 801b500: 9117 str r1, [sp, #92] @ 0x5c 801b502: 920b str r2, [sp, #44] @ 0x2c 801b504: 786a ldrb r2, [r5, #1] 801b506: 2a00 cmp r2, #0 801b508: d137 bne.n 801b57a <_strtod_l+0xc2> 801b50a: 9b15 ldr r3, [sp, #84] @ 0x54 801b50c: 9617 str r6, [sp, #92] @ 0x5c 801b50e: 2b00 cmp r3, #0 801b510: f040 8595 bne.w 801c03e <_strtod_l+0xb86> 801b514: 4642 mov r2, r8 801b516: 464b mov r3, r9 801b518: e02a b.n 801b570 <_strtod_l+0xb8> 801b51a: 2200 movs r2, #0 801b51c: e7ef b.n 801b4fe <_strtod_l+0x46> 801b51e: 2100 movs r1, #0 801b520: 910b str r1, [sp, #44] @ 0x2c 801b522: 2a30 cmp r2, #48 @ 0x30 801b524: f040 809b bne.w 801b65e <_strtod_l+0x1a6> 801b528: 786a ldrb r2, [r5, #1] 801b52a: f002 02df and.w r2, r2, #223 @ 0xdf 801b52e: 2a58 cmp r2, #88 @ 0x58 801b530: d15a bne.n 801b5e8 <_strtod_l+0x130> 801b532: 9302 str r3, [sp, #8] 801b534: 9b0b ldr r3, [sp, #44] @ 0x2c 801b536: 9301 str r3, [sp, #4] 801b538: ab18 add r3, sp, #96 @ 0x60 801b53a: 9300 str r3, [sp, #0] 801b53c: 4a81 ldr r2, [pc, #516] @ (801b744 <_strtod_l+0x28c>) 801b53e: 9804 ldr r0, [sp, #16] 801b540: ab19 add r3, sp, #100 @ 0x64 801b542: a917 add r1, sp, #92 @ 0x5c 801b544: f001 fab2 bl 801caac <__gethex> 801b548: f010 060f ands.w r6, r0, #15 801b54c: 4604 mov r4, r0 801b54e: d005 beq.n 801b55c <_strtod_l+0xa4> 801b550: 2e06 cmp r6, #6 801b552: d114 bne.n 801b57e <_strtod_l+0xc6> 801b554: 3501 adds r5, #1 801b556: 2300 movs r3, #0 801b558: 9517 str r5, [sp, #92] @ 0x5c 801b55a: 930b str r3, [sp, #44] @ 0x2c 801b55c: 9b15 ldr r3, [sp, #84] @ 0x54 801b55e: 2b00 cmp r3, #0 801b560: f040 856f bne.w 801c042 <_strtod_l+0xb8a> 801b564: 9b0b ldr r3, [sp, #44] @ 0x2c 801b566: 2b00 cmp r3, #0 801b568: d0d4 beq.n 801b514 <_strtod_l+0x5c> 801b56a: 4642 mov r2, r8 801b56c: f109 4300 add.w r3, r9, #2147483648 @ 0x80000000 801b570: ec43 2b10 vmov d0, r2, r3 801b574: b01d add sp, #116 @ 0x74 801b576: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801b57a: 460d mov r5, r1 801b57c: e7d1 b.n 801b522 <_strtod_l+0x6a> 801b57e: 9a18 ldr r2, [sp, #96] @ 0x60 801b580: b13a cbz r2, 801b592 <_strtod_l+0xda> 801b582: 2135 movs r1, #53 @ 0x35 801b584: a81a add r0, sp, #104 @ 0x68 801b586: f7ff ff33 bl 801b3f0 <__copybits> 801b58a: 9918 ldr r1, [sp, #96] @ 0x60 801b58c: 9804 ldr r0, [sp, #16] 801b58e: f7ff faf9 bl 801ab84 <_Bfree> 801b592: 3e01 subs r6, #1 801b594: 2e04 cmp r6, #4 801b596: d806 bhi.n 801b5a6 <_strtod_l+0xee> 801b598: e8df f006 tbb [pc, r6] 801b59c: 211e0314 .word 0x211e0314 801b5a0: 14 .byte 0x14 801b5a1: 00 .byte 0x00 801b5a2: e9dd 891a ldrd r8, r9, [sp, #104] @ 0x68 801b5a6: 05e0 lsls r0, r4, #23 801b5a8: bf48 it mi 801b5aa: f049 4900 orrmi.w r9, r9, #2147483648 @ 0x80000000 801b5ae: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 801b5b2: 0d1b lsrs r3, r3, #20 801b5b4: 051b lsls r3, r3, #20 801b5b6: 2b00 cmp r3, #0 801b5b8: d1d0 bne.n 801b55c <_strtod_l+0xa4> 801b5ba: f7fe fafd bl 8019bb8 <__errno> 801b5be: 2322 movs r3, #34 @ 0x22 801b5c0: 6003 str r3, [r0, #0] 801b5c2: e7cb b.n 801b55c <_strtod_l+0xa4> 801b5c4: e9dd 831a ldrd r8, r3, [sp, #104] @ 0x68 801b5c8: 9a19 ldr r2, [sp, #100] @ 0x64 801b5ca: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 801b5ce: f202 4233 addw r2, r2, #1075 @ 0x433 801b5d2: ea43 5902 orr.w r9, r3, r2, lsl #20 801b5d6: e7e6 b.n 801b5a6 <_strtod_l+0xee> 801b5d8: f8df 9170 ldr.w r9, [pc, #368] @ 801b74c <_strtod_l+0x294> 801b5dc: e7e3 b.n 801b5a6 <_strtod_l+0xee> 801b5de: f06f 4900 mvn.w r9, #2147483648 @ 0x80000000 801b5e2: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff 801b5e6: e7de b.n 801b5a6 <_strtod_l+0xee> 801b5e8: 3501 adds r5, #1 801b5ea: 9517 str r5, [sp, #92] @ 0x5c 801b5ec: 782b ldrb r3, [r5, #0] 801b5ee: 2b30 cmp r3, #48 @ 0x30 801b5f0: d0fa beq.n 801b5e8 <_strtod_l+0x130> 801b5f2: 2b00 cmp r3, #0 801b5f4: d0b2 beq.n 801b55c <_strtod_l+0xa4> 801b5f6: f04f 0a01 mov.w sl, #1 801b5fa: 2700 movs r7, #0 801b5fc: 462b mov r3, r5 801b5fe: 970e str r7, [sp, #56] @ 0x38 801b600: 46bb mov fp, r7 801b602: 210a movs r1, #10 801b604: 4618 mov r0, r3 801b606: f813 4b01 ldrb.w r4, [r3], #1 801b60a: f1a4 0230 sub.w r2, r4, #48 @ 0x30 801b60e: 2a09 cmp r2, #9 801b610: d928 bls.n 801b664 <_strtod_l+0x1ac> 801b612: 494d ldr r1, [pc, #308] @ (801b748 <_strtod_l+0x290>) 801b614: 2201 movs r2, #1 801b616: f001 f963 bl 801c8e0 801b61a: 2800 cmp r0, #0 801b61c: d034 beq.n 801b688 <_strtod_l+0x1d0> 801b61e: 2000 movs r0, #0 801b620: e9cd 0006 strd r0, r0, [sp, #24] 801b624: 4622 mov r2, r4 801b626: 465c mov r4, fp 801b628: 2a65 cmp r2, #101 @ 0x65 801b62a: d001 beq.n 801b630 <_strtod_l+0x178> 801b62c: 2a45 cmp r2, #69 @ 0x45 801b62e: d114 bne.n 801b65a <_strtod_l+0x1a2> 801b630: b924 cbnz r4, 801b63c <_strtod_l+0x184> 801b632: ea5a 0300 orrs.w r3, sl, r0 801b636: f43f af68 beq.w 801b50a <_strtod_l+0x52> 801b63a: 2400 movs r4, #0 801b63c: 9e17 ldr r6, [sp, #92] @ 0x5c 801b63e: 1c73 adds r3, r6, #1 801b640: 9317 str r3, [sp, #92] @ 0x5c 801b642: 7872 ldrb r2, [r6, #1] 801b644: 2a2b cmp r2, #43 @ 0x2b 801b646: d073 beq.n 801b730 <_strtod_l+0x278> 801b648: 2a2d cmp r2, #45 @ 0x2d 801b64a: d077 beq.n 801b73c <_strtod_l+0x284> 801b64c: f04f 0c00 mov.w ip, #0 801b650: f1a2 0330 sub.w r3, r2, #48 @ 0x30 801b654: 2b09 cmp r3, #9 801b656: d97f bls.n 801b758 <_strtod_l+0x2a0> 801b658: 9617 str r6, [sp, #92] @ 0x5c 801b65a: 2300 movs r3, #0 801b65c: e09e b.n 801b79c <_strtod_l+0x2e4> 801b65e: f04f 0a00 mov.w sl, #0 801b662: e7ca b.n 801b5fa <_strtod_l+0x142> 801b664: f1bb 0f08 cmp.w fp, #8 801b668: bfd8 it le 801b66a: 9a0e ldrle r2, [sp, #56] @ 0x38 801b66c: 9317 str r3, [sp, #92] @ 0x5c 801b66e: bfdb ittet le 801b670: fb01 4202 mlale r2, r1, r2, r4 801b674: 3a30 suble r2, #48 @ 0x30 801b676: fb01 4207 mlagt r2, r1, r7, r4 801b67a: 920e strle r2, [sp, #56] @ 0x38 801b67c: bfc8 it gt 801b67e: f1a2 0730 subgt.w r7, r2, #48 @ 0x30 801b682: f10b 0b01 add.w fp, fp, #1 801b686: e7bd b.n 801b604 <_strtod_l+0x14c> 801b688: 9b17 ldr r3, [sp, #92] @ 0x5c 801b68a: 1c5a adds r2, r3, #1 801b68c: 9217 str r2, [sp, #92] @ 0x5c 801b68e: 785a ldrb r2, [r3, #1] 801b690: f1bb 0f00 cmp.w fp, #0 801b694: d033 beq.n 801b6fe <_strtod_l+0x246> 801b696: 9006 str r0, [sp, #24] 801b698: 465c mov r4, fp 801b69a: f1a2 0330 sub.w r3, r2, #48 @ 0x30 801b69e: 2b09 cmp r3, #9 801b6a0: d912 bls.n 801b6c8 <_strtod_l+0x210> 801b6a2: 2301 movs r3, #1 801b6a4: 9307 str r3, [sp, #28] 801b6a6: e7bf b.n 801b628 <_strtod_l+0x170> 801b6a8: 9b17 ldr r3, [sp, #92] @ 0x5c 801b6aa: 1c5a adds r2, r3, #1 801b6ac: 9217 str r2, [sp, #92] @ 0x5c 801b6ae: 785a ldrb r2, [r3, #1] 801b6b0: 3001 adds r0, #1 801b6b2: 2a30 cmp r2, #48 @ 0x30 801b6b4: d0f8 beq.n 801b6a8 <_strtod_l+0x1f0> 801b6b6: f1a2 0331 sub.w r3, r2, #49 @ 0x31 801b6ba: 2b08 cmp r3, #8 801b6bc: f200 84c6 bhi.w 801c04c <_strtod_l+0xb94> 801b6c0: 9006 str r0, [sp, #24] 801b6c2: 9d17 ldr r5, [sp, #92] @ 0x5c 801b6c4: 2000 movs r0, #0 801b6c6: 4604 mov r4, r0 801b6c8: 3a30 subs r2, #48 @ 0x30 801b6ca: f100 0301 add.w r3, r0, #1 801b6ce: d010 beq.n 801b6f2 <_strtod_l+0x23a> 801b6d0: 9906 ldr r1, [sp, #24] 801b6d2: 4419 add r1, r3 801b6d4: 9106 str r1, [sp, #24] 801b6d6: 4420 add r0, r4 801b6d8: 230a movs r3, #10 801b6da: 42a0 cmp r0, r4 801b6dc: d111 bne.n 801b702 <_strtod_l+0x24a> 801b6de: 2808 cmp r0, #8 801b6e0: f100 0401 add.w r4, r0, #1 801b6e4: dc19 bgt.n 801b71a <_strtod_l+0x262> 801b6e6: 990e ldr r1, [sp, #56] @ 0x38 801b6e8: 230a movs r3, #10 801b6ea: fb03 2301 mla r3, r3, r1, r2 801b6ee: 930e str r3, [sp, #56] @ 0x38 801b6f0: 2300 movs r3, #0 801b6f2: 9a17 ldr r2, [sp, #92] @ 0x5c 801b6f4: 1c51 adds r1, r2, #1 801b6f6: 9117 str r1, [sp, #92] @ 0x5c 801b6f8: 7852 ldrb r2, [r2, #1] 801b6fa: 4618 mov r0, r3 801b6fc: e7cd b.n 801b69a <_strtod_l+0x1e2> 801b6fe: 4658 mov r0, fp 801b700: e7d7 b.n 801b6b2 <_strtod_l+0x1fa> 801b702: 2c08 cmp r4, #8 801b704: f104 0401 add.w r4, r4, #1 801b708: dc03 bgt.n 801b712 <_strtod_l+0x25a> 801b70a: 990e ldr r1, [sp, #56] @ 0x38 801b70c: 4359 muls r1, r3 801b70e: 910e str r1, [sp, #56] @ 0x38 801b710: e7e3 b.n 801b6da <_strtod_l+0x222> 801b712: 2c10 cmp r4, #16 801b714: bfd8 it le 801b716: 435f mulle r7, r3 801b718: e7df b.n 801b6da <_strtod_l+0x222> 801b71a: 280f cmp r0, #15 801b71c: bfdc itt le 801b71e: 230a movle r3, #10 801b720: fb03 2707 mlale r7, r3, r7, r2 801b724: e7e4 b.n 801b6f0 <_strtod_l+0x238> 801b726: 2100 movs r1, #0 801b728: 2301 movs r3, #1 801b72a: e9cd 1306 strd r1, r3, [sp, #24] 801b72e: e780 b.n 801b632 <_strtod_l+0x17a> 801b730: f04f 0c00 mov.w ip, #0 801b734: 1cb3 adds r3, r6, #2 801b736: 9317 str r3, [sp, #92] @ 0x5c 801b738: 78b2 ldrb r2, [r6, #2] 801b73a: e789 b.n 801b650 <_strtod_l+0x198> 801b73c: f04f 0c01 mov.w ip, #1 801b740: e7f8 b.n 801b734 <_strtod_l+0x27c> 801b742: bf00 nop 801b744: 0801df9c .word 0x0801df9c 801b748: 0801ddcf .word 0x0801ddcf 801b74c: 7ff00000 .word 0x7ff00000 801b750: 9b17 ldr r3, [sp, #92] @ 0x5c 801b752: 1c5a adds r2, r3, #1 801b754: 9217 str r2, [sp, #92] @ 0x5c 801b756: 785a ldrb r2, [r3, #1] 801b758: 2a30 cmp r2, #48 @ 0x30 801b75a: d0f9 beq.n 801b750 <_strtod_l+0x298> 801b75c: f1a2 0331 sub.w r3, r2, #49 @ 0x31 801b760: 2b08 cmp r3, #8 801b762: f63f af7a bhi.w 801b65a <_strtod_l+0x1a2> 801b766: 9b17 ldr r3, [sp, #92] @ 0x5c 801b768: 9305 str r3, [sp, #20] 801b76a: f1a2 0e30 sub.w lr, r2, #48 @ 0x30 801b76e: 3301 adds r3, #1 801b770: 9317 str r3, [sp, #92] @ 0x5c 801b772: 781a ldrb r2, [r3, #0] 801b774: f1a2 0130 sub.w r1, r2, #48 @ 0x30 801b778: 2909 cmp r1, #9 801b77a: d93c bls.n 801b7f6 <_strtod_l+0x33e> 801b77c: 9905 ldr r1, [sp, #20] 801b77e: 1a5b subs r3, r3, r1 801b780: 2b08 cmp r3, #8 801b782: f644 631f movw r3, #19999 @ 0x4e1f 801b786: dc3c bgt.n 801b802 <_strtod_l+0x34a> 801b788: 459e cmp lr, r3 801b78a: 4671 mov r1, lr 801b78c: bfa8 it ge 801b78e: 4619 movge r1, r3 801b790: 9105 str r1, [sp, #20] 801b792: f1bc 0f00 cmp.w ip, #0 801b796: d002 beq.n 801b79e <_strtod_l+0x2e6> 801b798: 9b05 ldr r3, [sp, #20] 801b79a: 425b negs r3, r3 801b79c: 9305 str r3, [sp, #20] 801b79e: 2c00 cmp r4, #0 801b7a0: d150 bne.n 801b844 <_strtod_l+0x38c> 801b7a2: ea5a 0000 orrs.w r0, sl, r0 801b7a6: f47f aed9 bne.w 801b55c <_strtod_l+0xa4> 801b7aa: 9b07 ldr r3, [sp, #28] 801b7ac: 2b00 cmp r3, #0 801b7ae: f47f aeac bne.w 801b50a <_strtod_l+0x52> 801b7b2: 2a69 cmp r2, #105 @ 0x69 801b7b4: d029 beq.n 801b80a <_strtod_l+0x352> 801b7b6: dc26 bgt.n 801b806 <_strtod_l+0x34e> 801b7b8: 2a49 cmp r2, #73 @ 0x49 801b7ba: d026 beq.n 801b80a <_strtod_l+0x352> 801b7bc: 2a4e cmp r2, #78 @ 0x4e 801b7be: f47f aea4 bne.w 801b50a <_strtod_l+0x52> 801b7c2: 49a1 ldr r1, [pc, #644] @ (801ba48 <_strtod_l+0x590>) 801b7c4: a817 add r0, sp, #92 @ 0x5c 801b7c6: f001 fb93 bl 801cef0 <__match> 801b7ca: 2800 cmp r0, #0 801b7cc: f43f ae9d beq.w 801b50a <_strtod_l+0x52> 801b7d0: 9b17 ldr r3, [sp, #92] @ 0x5c 801b7d2: 781b ldrb r3, [r3, #0] 801b7d4: 2b28 cmp r3, #40 @ 0x28 801b7d6: d12f bne.n 801b838 <_strtod_l+0x380> 801b7d8: 499c ldr r1, [pc, #624] @ (801ba4c <_strtod_l+0x594>) 801b7da: aa1a add r2, sp, #104 @ 0x68 801b7dc: a817 add r0, sp, #92 @ 0x5c 801b7de: f001 fb9b bl 801cf18 <__hexnan> 801b7e2: 2805 cmp r0, #5 801b7e4: d128 bne.n 801b838 <_strtod_l+0x380> 801b7e6: 9b1b ldr r3, [sp, #108] @ 0x6c 801b7e8: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 801b7ec: f043 49ff orr.w r9, r3, #2139095040 @ 0x7f800000 801b7f0: f449 09e0 orr.w r9, r9, #7340032 @ 0x700000 801b7f4: e6b2 b.n 801b55c <_strtod_l+0xa4> 801b7f6: 210a movs r1, #10 801b7f8: fb01 220e mla r2, r1, lr, r2 801b7fc: f1a2 0e30 sub.w lr, r2, #48 @ 0x30 801b800: e7b5 b.n 801b76e <_strtod_l+0x2b6> 801b802: 9305 str r3, [sp, #20] 801b804: e7c5 b.n 801b792 <_strtod_l+0x2da> 801b806: 2a6e cmp r2, #110 @ 0x6e 801b808: e7d9 b.n 801b7be <_strtod_l+0x306> 801b80a: 4991 ldr r1, [pc, #580] @ (801ba50 <_strtod_l+0x598>) 801b80c: a817 add r0, sp, #92 @ 0x5c 801b80e: f001 fb6f bl 801cef0 <__match> 801b812: 2800 cmp r0, #0 801b814: f43f ae79 beq.w 801b50a <_strtod_l+0x52> 801b818: 9b17 ldr r3, [sp, #92] @ 0x5c 801b81a: 498e ldr r1, [pc, #568] @ (801ba54 <_strtod_l+0x59c>) 801b81c: 3b01 subs r3, #1 801b81e: a817 add r0, sp, #92 @ 0x5c 801b820: 9317 str r3, [sp, #92] @ 0x5c 801b822: f001 fb65 bl 801cef0 <__match> 801b826: b910 cbnz r0, 801b82e <_strtod_l+0x376> 801b828: 9b17 ldr r3, [sp, #92] @ 0x5c 801b82a: 3301 adds r3, #1 801b82c: 9317 str r3, [sp, #92] @ 0x5c 801b82e: f8df 9234 ldr.w r9, [pc, #564] @ 801ba64 <_strtod_l+0x5ac> 801b832: f04f 0800 mov.w r8, #0 801b836: e691 b.n 801b55c <_strtod_l+0xa4> 801b838: 4887 ldr r0, [pc, #540] @ (801ba58 <_strtod_l+0x5a0>) 801b83a: f001 f895 bl 801c968 801b83e: ec59 8b10 vmov r8, r9, d0 801b842: e68b b.n 801b55c <_strtod_l+0xa4> 801b844: e9dd 3205 ldrd r3, r2, [sp, #20] 801b848: 980e ldr r0, [sp, #56] @ 0x38 801b84a: 1a9b subs r3, r3, r2 801b84c: f1bb 0f00 cmp.w fp, #0 801b850: bf08 it eq 801b852: 46a3 moveq fp, r4 801b854: 2c10 cmp r4, #16 801b856: 930a str r3, [sp, #40] @ 0x28 801b858: 46a2 mov sl, r4 801b85a: bfa8 it ge 801b85c: f04f 0a10 movge.w sl, #16 801b860: f7e4 fe28 bl 80004b4 <__aeabi_ui2d> 801b864: 2c09 cmp r4, #9 801b866: 4680 mov r8, r0 801b868: 4689 mov r9, r1 801b86a: dc13 bgt.n 801b894 <_strtod_l+0x3dc> 801b86c: 9b0a ldr r3, [sp, #40] @ 0x28 801b86e: 2b00 cmp r3, #0 801b870: f43f ae74 beq.w 801b55c <_strtod_l+0xa4> 801b874: 9b0a ldr r3, [sp, #40] @ 0x28 801b876: dd73 ble.n 801b960 <_strtod_l+0x4a8> 801b878: 2b16 cmp r3, #22 801b87a: dc5a bgt.n 801b932 <_strtod_l+0x47a> 801b87c: 4977 ldr r1, [pc, #476] @ (801ba5c <_strtod_l+0x5a4>) 801b87e: eb01 01c3 add.w r1, r1, r3, lsl #3 801b882: e9d1 0100 ldrd r0, r1, [r1] 801b886: 4642 mov r2, r8 801b888: 464b mov r3, r9 801b88a: f7e4 fe8d bl 80005a8 <__aeabi_dmul> 801b88e: 4680 mov r8, r0 801b890: 4689 mov r9, r1 801b892: e663 b.n 801b55c <_strtod_l+0xa4> 801b894: 4b71 ldr r3, [pc, #452] @ (801ba5c <_strtod_l+0x5a4>) 801b896: eb03 03ca add.w r3, r3, sl, lsl #3 801b89a: e953 2312 ldrd r2, r3, [r3, #-72] @ 0x48 801b89e: f7e4 fe83 bl 80005a8 <__aeabi_dmul> 801b8a2: 4680 mov r8, r0 801b8a4: 4638 mov r0, r7 801b8a6: 4689 mov r9, r1 801b8a8: f7e4 fe04 bl 80004b4 <__aeabi_ui2d> 801b8ac: 4602 mov r2, r0 801b8ae: 460b mov r3, r1 801b8b0: 4640 mov r0, r8 801b8b2: 4649 mov r1, r9 801b8b4: f7e4 fcc2 bl 800023c <__adddf3> 801b8b8: 2c0f cmp r4, #15 801b8ba: 4680 mov r8, r0 801b8bc: 4689 mov r9, r1 801b8be: ddd5 ble.n 801b86c <_strtod_l+0x3b4> 801b8c0: 9b0a ldr r3, [sp, #40] @ 0x28 801b8c2: eba4 0a0a sub.w sl, r4, sl 801b8c6: 449a add sl, r3 801b8c8: f1ba 0f00 cmp.w sl, #0 801b8cc: f340 8097 ble.w 801b9fe <_strtod_l+0x546> 801b8d0: f02a 060f bic.w r6, sl, #15 801b8d4: f01a 0a0f ands.w sl, sl, #15 801b8d8: d151 bne.n 801b97e <_strtod_l+0x4c6> 801b8da: f5b6 7f9a cmp.w r6, #308 @ 0x134 801b8de: dc5e bgt.n 801b99e <_strtod_l+0x4e6> 801b8e0: 2300 movs r3, #0 801b8e2: f8df a17c ldr.w sl, [pc, #380] @ 801ba60 <_strtod_l+0x5a8> 801b8e6: 1136 asrs r6, r6, #4 801b8e8: 4640 mov r0, r8 801b8ea: 4649 mov r1, r9 801b8ec: 461f mov r7, r3 801b8ee: 2e01 cmp r6, #1 801b8f0: d179 bne.n 801b9e6 <_strtod_l+0x52e> 801b8f2: b10b cbz r3, 801b8f8 <_strtod_l+0x440> 801b8f4: 4680 mov r8, r0 801b8f6: 4689 mov r9, r1 801b8f8: 4959 ldr r1, [pc, #356] @ (801ba60 <_strtod_l+0x5a8>) 801b8fa: f1a9 7954 sub.w r9, r9, #55574528 @ 0x3500000 801b8fe: eb01 01c7 add.w r1, r1, r7, lsl #3 801b902: 4642 mov r2, r8 801b904: 464b mov r3, r9 801b906: e9d1 0100 ldrd r0, r1, [r1] 801b90a: f7e4 fe4d bl 80005a8 <__aeabi_dmul> 801b90e: 4b55 ldr r3, [pc, #340] @ (801ba64 <_strtod_l+0x5ac>) 801b910: 460a mov r2, r1 801b912: 400b ands r3, r1 801b914: 4954 ldr r1, [pc, #336] @ (801ba68 <_strtod_l+0x5b0>) 801b916: 428b cmp r3, r1 801b918: 4680 mov r8, r0 801b91a: d840 bhi.n 801b99e <_strtod_l+0x4e6> 801b91c: f5a1 1180 sub.w r1, r1, #1048576 @ 0x100000 801b920: 428b cmp r3, r1 801b922: bf86 itte hi 801b924: f8df 9144 ldrhi.w r9, [pc, #324] @ 801ba6c <_strtod_l+0x5b4> 801b928: f04f 38ff movhi.w r8, #4294967295 @ 0xffffffff 801b92c: f102 7954 addls.w r9, r2, #55574528 @ 0x3500000 801b930: e032 b.n 801b998 <_strtod_l+0x4e0> 801b932: 9a0a ldr r2, [sp, #40] @ 0x28 801b934: f1c4 0325 rsb r3, r4, #37 @ 0x25 801b938: 4293 cmp r3, r2 801b93a: dbc1 blt.n 801b8c0 <_strtod_l+0x408> 801b93c: 4d47 ldr r5, [pc, #284] @ (801ba5c <_strtod_l+0x5a4>) 801b93e: f1c4 040f rsb r4, r4, #15 801b942: eb05 01c4 add.w r1, r5, r4, lsl #3 801b946: 4642 mov r2, r8 801b948: 464b mov r3, r9 801b94a: e9d1 0100 ldrd r0, r1, [r1] 801b94e: f7e4 fe2b bl 80005a8 <__aeabi_dmul> 801b952: 9b0a ldr r3, [sp, #40] @ 0x28 801b954: 1b1c subs r4, r3, r4 801b956: eb05 05c4 add.w r5, r5, r4, lsl #3 801b95a: e9d5 2300 ldrd r2, r3, [r5] 801b95e: e794 b.n 801b88a <_strtod_l+0x3d2> 801b960: 3316 adds r3, #22 801b962: dbad blt.n 801b8c0 <_strtod_l+0x408> 801b964: e9dd 2305 ldrd r2, r3, [sp, #20] 801b968: 1a9a subs r2, r3, r2 801b96a: 4b3c ldr r3, [pc, #240] @ (801ba5c <_strtod_l+0x5a4>) 801b96c: eb03 03c2 add.w r3, r3, r2, lsl #3 801b970: e9d3 2300 ldrd r2, r3, [r3] 801b974: 4640 mov r0, r8 801b976: 4649 mov r1, r9 801b978: f7e4 ff40 bl 80007fc <__aeabi_ddiv> 801b97c: e787 b.n 801b88e <_strtod_l+0x3d6> 801b97e: 4937 ldr r1, [pc, #220] @ (801ba5c <_strtod_l+0x5a4>) 801b980: eb01 01ca add.w r1, r1, sl, lsl #3 801b984: 4642 mov r2, r8 801b986: 464b mov r3, r9 801b988: e9d1 0100 ldrd r0, r1, [r1] 801b98c: f7e4 fe0c bl 80005a8 <__aeabi_dmul> 801b990: 4680 mov r8, r0 801b992: 4689 mov r9, r1 801b994: 2e00 cmp r6, #0 801b996: d1a0 bne.n 801b8da <_strtod_l+0x422> 801b998: 2300 movs r3, #0 801b99a: 9307 str r3, [sp, #28] 801b99c: e0a0 b.n 801bae0 <_strtod_l+0x628> 801b99e: 2400 movs r4, #0 801b9a0: 9405 str r4, [sp, #20] 801b9a2: 940e str r4, [sp, #56] @ 0x38 801b9a4: 9406 str r4, [sp, #24] 801b9a6: 9a04 ldr r2, [sp, #16] 801b9a8: f8df 90b8 ldr.w r9, [pc, #184] @ 801ba64 <_strtod_l+0x5ac> 801b9ac: 2322 movs r3, #34 @ 0x22 801b9ae: 6013 str r3, [r2, #0] 801b9b0: f04f 0800 mov.w r8, #0 801b9b4: 9b0e ldr r3, [sp, #56] @ 0x38 801b9b6: 2b00 cmp r3, #0 801b9b8: f43f add0 beq.w 801b55c <_strtod_l+0xa4> 801b9bc: 9918 ldr r1, [sp, #96] @ 0x60 801b9be: 9804 ldr r0, [sp, #16] 801b9c0: f7ff f8e0 bl 801ab84 <_Bfree> 801b9c4: 9906 ldr r1, [sp, #24] 801b9c6: 9804 ldr r0, [sp, #16] 801b9c8: f7ff f8dc bl 801ab84 <_Bfree> 801b9cc: e9dd 0104 ldrd r0, r1, [sp, #16] 801b9d0: f7ff f8d8 bl 801ab84 <_Bfree> 801b9d4: 990e ldr r1, [sp, #56] @ 0x38 801b9d6: 9804 ldr r0, [sp, #16] 801b9d8: f7ff f8d4 bl 801ab84 <_Bfree> 801b9dc: 9804 ldr r0, [sp, #16] 801b9de: 4621 mov r1, r4 801b9e0: f7ff f8d0 bl 801ab84 <_Bfree> 801b9e4: e5ba b.n 801b55c <_strtod_l+0xa4> 801b9e6: 07f2 lsls r2, r6, #31 801b9e8: d504 bpl.n 801b9f4 <_strtod_l+0x53c> 801b9ea: e9da 2300 ldrd r2, r3, [sl] 801b9ee: f7e4 fddb bl 80005a8 <__aeabi_dmul> 801b9f2: 2301 movs r3, #1 801b9f4: 3701 adds r7, #1 801b9f6: 1076 asrs r6, r6, #1 801b9f8: f10a 0a08 add.w sl, sl, #8 801b9fc: e777 b.n 801b8ee <_strtod_l+0x436> 801b9fe: d0cb beq.n 801b998 <_strtod_l+0x4e0> 801ba00: f1ca 0a00 rsb sl, sl, #0 801ba04: ea4f 162a mov.w r6, sl, asr #4 801ba08: f01a 0a0f ands.w sl, sl, #15 801ba0c: d10d bne.n 801ba2a <_strtod_l+0x572> 801ba0e: 2e1f cmp r6, #31 801ba10: dd2e ble.n 801ba70 <_strtod_l+0x5b8> 801ba12: 2400 movs r4, #0 801ba14: 9405 str r4, [sp, #20] 801ba16: 940e str r4, [sp, #56] @ 0x38 801ba18: 9406 str r4, [sp, #24] 801ba1a: 9a04 ldr r2, [sp, #16] 801ba1c: 2322 movs r3, #34 @ 0x22 801ba1e: f04f 0800 mov.w r8, #0 801ba22: f04f 0900 mov.w r9, #0 801ba26: 6013 str r3, [r2, #0] 801ba28: e7c4 b.n 801b9b4 <_strtod_l+0x4fc> 801ba2a: 4b0c ldr r3, [pc, #48] @ (801ba5c <_strtod_l+0x5a4>) 801ba2c: eb03 03ca add.w r3, r3, sl, lsl #3 801ba30: 4640 mov r0, r8 801ba32: 4649 mov r1, r9 801ba34: e9d3 2300 ldrd r2, r3, [r3] 801ba38: f7e4 fee0 bl 80007fc <__aeabi_ddiv> 801ba3c: 4680 mov r8, r0 801ba3e: 4689 mov r9, r1 801ba40: 2e00 cmp r6, #0 801ba42: d0a9 beq.n 801b998 <_strtod_l+0x4e0> 801ba44: e7e3 b.n 801ba0e <_strtod_l+0x556> 801ba46: bf00 nop 801ba48: 0801dcbd .word 0x0801dcbd 801ba4c: 0801df88 .word 0x0801df88 801ba50: 0801dcb5 .word 0x0801dcb5 801ba54: 0801dcec .word 0x0801dcec 801ba58: 0801de25 .word 0x0801de25 801ba5c: 0801dec0 .word 0x0801dec0 801ba60: 0801de98 .word 0x0801de98 801ba64: 7ff00000 .word 0x7ff00000 801ba68: 7ca00000 .word 0x7ca00000 801ba6c: 7fefffff .word 0x7fefffff 801ba70: f016 0310 ands.w r3, r6, #16 801ba74: bf18 it ne 801ba76: 236a movne r3, #106 @ 0x6a 801ba78: 4f76 ldr r7, [pc, #472] @ (801bc54 <_strtod_l+0x79c>) 801ba7a: 9307 str r3, [sp, #28] 801ba7c: 4640 mov r0, r8 801ba7e: 4649 mov r1, r9 801ba80: 2300 movs r3, #0 801ba82: 07f2 lsls r2, r6, #31 801ba84: d504 bpl.n 801ba90 <_strtod_l+0x5d8> 801ba86: e9d7 2300 ldrd r2, r3, [r7] 801ba8a: f7e4 fd8d bl 80005a8 <__aeabi_dmul> 801ba8e: 2301 movs r3, #1 801ba90: 1076 asrs r6, r6, #1 801ba92: f107 0708 add.w r7, r7, #8 801ba96: d1f4 bne.n 801ba82 <_strtod_l+0x5ca> 801ba98: b10b cbz r3, 801ba9e <_strtod_l+0x5e6> 801ba9a: 4680 mov r8, r0 801ba9c: 4689 mov r9, r1 801ba9e: 9b07 ldr r3, [sp, #28] 801baa0: b1b3 cbz r3, 801bad0 <_strtod_l+0x618> 801baa2: f3c9 520a ubfx r2, r9, #20, #11 801baa6: f1c2 036b rsb r3, r2, #107 @ 0x6b 801baaa: 2b00 cmp r3, #0 801baac: 4649 mov r1, r9 801baae: dd0f ble.n 801bad0 <_strtod_l+0x618> 801bab0: 2b1f cmp r3, #31 801bab2: dd57 ble.n 801bb64 <_strtod_l+0x6ac> 801bab4: 2b34 cmp r3, #52 @ 0x34 801bab6: bfde ittt le 801bab8: f04f 33ff movle.w r3, #4294967295 @ 0xffffffff 801babc: f1c2 024b rsble r2, r2, #75 @ 0x4b 801bac0: 4093 lslle r3, r2 801bac2: f04f 0800 mov.w r8, #0 801bac6: bfcc ite gt 801bac8: f04f 795c movgt.w r9, #57671680 @ 0x3700000 801bacc: ea03 0901 andle.w r9, r3, r1 801bad0: 2200 movs r2, #0 801bad2: 2300 movs r3, #0 801bad4: 4640 mov r0, r8 801bad6: 4649 mov r1, r9 801bad8: f7e4 ffce bl 8000a78 <__aeabi_dcmpeq> 801badc: 2800 cmp r0, #0 801bade: d198 bne.n 801ba12 <_strtod_l+0x55a> 801bae0: 9b0e ldr r3, [sp, #56] @ 0x38 801bae2: 9300 str r3, [sp, #0] 801bae4: 9804 ldr r0, [sp, #16] 801bae6: 4623 mov r3, r4 801bae8: 465a mov r2, fp 801baea: 4629 mov r1, r5 801baec: f7ff f8b2 bl 801ac54 <__s2b> 801baf0: 900e str r0, [sp, #56] @ 0x38 801baf2: 2800 cmp r0, #0 801baf4: f43f af53 beq.w 801b99e <_strtod_l+0x4e6> 801baf8: e9dd 2305 ldrd r2, r3, [sp, #20] 801bafc: 1a9b subs r3, r3, r2 801bafe: 9a0a ldr r2, [sp, #40] @ 0x28 801bb00: 2a00 cmp r2, #0 801bb02: bfa8 it ge 801bb04: 2300 movge r3, #0 801bb06: 9312 str r3, [sp, #72] @ 0x48 801bb08: 2400 movs r4, #0 801bb0a: ea22 73e2 bic.w r3, r2, r2, asr #31 801bb0e: 9314 str r3, [sp, #80] @ 0x50 801bb10: 9405 str r4, [sp, #20] 801bb12: 9b0e ldr r3, [sp, #56] @ 0x38 801bb14: 9804 ldr r0, [sp, #16] 801bb16: 6859 ldr r1, [r3, #4] 801bb18: f7fe fff6 bl 801ab08 <_Balloc> 801bb1c: 9006 str r0, [sp, #24] 801bb1e: 2800 cmp r0, #0 801bb20: f43f af41 beq.w 801b9a6 <_strtod_l+0x4ee> 801bb24: 9b0e ldr r3, [sp, #56] @ 0x38 801bb26: 691a ldr r2, [r3, #16] 801bb28: 3202 adds r2, #2 801bb2a: f103 010c add.w r1, r3, #12 801bb2e: 0092 lsls r2, r2, #2 801bb30: 300c adds r0, #12 801bb32: f7fe f86e bl 8019c12 801bb36: ec49 8b10 vmov d0, r8, r9 801bb3a: 9804 ldr r0, [sp, #16] 801bb3c: aa1a add r2, sp, #104 @ 0x68 801bb3e: a919 add r1, sp, #100 @ 0x64 801bb40: e9cd 890c strd r8, r9, [sp, #48] @ 0x30 801bb44: f7ff fbca bl 801b2dc <__d2b> 801bb48: 9018 str r0, [sp, #96] @ 0x60 801bb4a: 2800 cmp r0, #0 801bb4c: f43f af2b beq.w 801b9a6 <_strtod_l+0x4ee> 801bb50: 9804 ldr r0, [sp, #16] 801bb52: 2101 movs r1, #1 801bb54: f7ff f914 bl 801ad80 <__i2b> 801bb58: 9005 str r0, [sp, #20] 801bb5a: 4603 mov r3, r0 801bb5c: b948 cbnz r0, 801bb72 <_strtod_l+0x6ba> 801bb5e: 2300 movs r3, #0 801bb60: 9305 str r3, [sp, #20] 801bb62: e720 b.n 801b9a6 <_strtod_l+0x4ee> 801bb64: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801bb68: fa02 f303 lsl.w r3, r2, r3 801bb6c: ea03 0808 and.w r8, r3, r8 801bb70: e7ae b.n 801bad0 <_strtod_l+0x618> 801bb72: 9d19 ldr r5, [sp, #100] @ 0x64 801bb74: 9a1a ldr r2, [sp, #104] @ 0x68 801bb76: 2d00 cmp r5, #0 801bb78: bfab itete ge 801bb7a: 9b12 ldrge r3, [sp, #72] @ 0x48 801bb7c: 9b14 ldrlt r3, [sp, #80] @ 0x50 801bb7e: 9e14 ldrge r6, [sp, #80] @ 0x50 801bb80: 9f12 ldrlt r7, [sp, #72] @ 0x48 801bb82: bfac ite ge 801bb84: 18ef addge r7, r5, r3 801bb86: 1b5e sublt r6, r3, r5 801bb88: 9b07 ldr r3, [sp, #28] 801bb8a: 1aed subs r5, r5, r3 801bb8c: 4415 add r5, r2 801bb8e: 4b32 ldr r3, [pc, #200] @ (801bc58 <_strtod_l+0x7a0>) 801bb90: 3d01 subs r5, #1 801bb92: 429d cmp r5, r3 801bb94: f1c2 0236 rsb r2, r2, #54 @ 0x36 801bb98: da4f bge.n 801bc3a <_strtod_l+0x782> 801bb9a: 1b5b subs r3, r3, r5 801bb9c: 2b1f cmp r3, #31 801bb9e: eba2 0203 sub.w r2, r2, r3 801bba2: f04f 0101 mov.w r1, #1 801bba6: dc3c bgt.n 801bc22 <_strtod_l+0x76a> 801bba8: fa01 fa03 lsl.w sl, r1, r3 801bbac: f04f 0b00 mov.w fp, #0 801bbb0: 18bd adds r5, r7, r2 801bbb2: 9b07 ldr r3, [sp, #28] 801bbb4: 42af cmp r7, r5 801bbb6: 4416 add r6, r2 801bbb8: 441e add r6, r3 801bbba: 463b mov r3, r7 801bbbc: bfa8 it ge 801bbbe: 462b movge r3, r5 801bbc0: 42b3 cmp r3, r6 801bbc2: bfa8 it ge 801bbc4: 4633 movge r3, r6 801bbc6: 2b00 cmp r3, #0 801bbc8: bfc2 ittt gt 801bbca: 1aed subgt r5, r5, r3 801bbcc: 1af6 subgt r6, r6, r3 801bbce: 1aff subgt r7, r7, r3 801bbd0: 9b12 ldr r3, [sp, #72] @ 0x48 801bbd2: 2b00 cmp r3, #0 801bbd4: dd16 ble.n 801bc04 <_strtod_l+0x74c> 801bbd6: e9dd 0104 ldrd r0, r1, [sp, #16] 801bbda: 461a mov r2, r3 801bbdc: f7ff f990 bl 801af00 <__pow5mult> 801bbe0: 9005 str r0, [sp, #20] 801bbe2: 2800 cmp r0, #0 801bbe4: d0bb beq.n 801bb5e <_strtod_l+0x6a6> 801bbe6: 4601 mov r1, r0 801bbe8: 9a18 ldr r2, [sp, #96] @ 0x60 801bbea: 9804 ldr r0, [sp, #16] 801bbec: f7ff f8de bl 801adac <__multiply> 801bbf0: 900f str r0, [sp, #60] @ 0x3c 801bbf2: 2800 cmp r0, #0 801bbf4: f43f aed7 beq.w 801b9a6 <_strtod_l+0x4ee> 801bbf8: 9918 ldr r1, [sp, #96] @ 0x60 801bbfa: 9804 ldr r0, [sp, #16] 801bbfc: f7fe ffc2 bl 801ab84 <_Bfree> 801bc00: 9b0f ldr r3, [sp, #60] @ 0x3c 801bc02: 9318 str r3, [sp, #96] @ 0x60 801bc04: 2d00 cmp r5, #0 801bc06: dc1b bgt.n 801bc40 <_strtod_l+0x788> 801bc08: 9b0a ldr r3, [sp, #40] @ 0x28 801bc0a: 2b00 cmp r3, #0 801bc0c: dd26 ble.n 801bc5c <_strtod_l+0x7a4> 801bc0e: 9a14 ldr r2, [sp, #80] @ 0x50 801bc10: 9906 ldr r1, [sp, #24] 801bc12: 9804 ldr r0, [sp, #16] 801bc14: f7ff f974 bl 801af00 <__pow5mult> 801bc18: 9006 str r0, [sp, #24] 801bc1a: b9f8 cbnz r0, 801bc5c <_strtod_l+0x7a4> 801bc1c: 2300 movs r3, #0 801bc1e: 9306 str r3, [sp, #24] 801bc20: e6c1 b.n 801b9a6 <_strtod_l+0x4ee> 801bc22: f1c5 457f rsb r5, r5, #4278190080 @ 0xff000000 801bc26: f505 057f add.w r5, r5, #16711680 @ 0xff0000 801bc2a: f505 457b add.w r5, r5, #64256 @ 0xfb00 801bc2e: 35e2 adds r5, #226 @ 0xe2 801bc30: fa01 fb05 lsl.w fp, r1, r5 801bc34: f04f 0a01 mov.w sl, #1 801bc38: e7ba b.n 801bbb0 <_strtod_l+0x6f8> 801bc3a: f04f 0b00 mov.w fp, #0 801bc3e: e7f9 b.n 801bc34 <_strtod_l+0x77c> 801bc40: 9918 ldr r1, [sp, #96] @ 0x60 801bc42: 9804 ldr r0, [sp, #16] 801bc44: 462a mov r2, r5 801bc46: f7ff f9b7 bl 801afb8 <__lshift> 801bc4a: 9018 str r0, [sp, #96] @ 0x60 801bc4c: 2800 cmp r0, #0 801bc4e: d1db bne.n 801bc08 <_strtod_l+0x750> 801bc50: e6a9 b.n 801b9a6 <_strtod_l+0x4ee> 801bc52: bf00 nop 801bc54: 0801dfb0 .word 0x0801dfb0 801bc58: fffffc02 .word 0xfffffc02 801bc5c: 2e00 cmp r6, #0 801bc5e: dd07 ble.n 801bc70 <_strtod_l+0x7b8> 801bc60: 9906 ldr r1, [sp, #24] 801bc62: 9804 ldr r0, [sp, #16] 801bc64: 4632 mov r2, r6 801bc66: f7ff f9a7 bl 801afb8 <__lshift> 801bc6a: 9006 str r0, [sp, #24] 801bc6c: 2800 cmp r0, #0 801bc6e: d0d5 beq.n 801bc1c <_strtod_l+0x764> 801bc70: 2f00 cmp r7, #0 801bc72: dd08 ble.n 801bc86 <_strtod_l+0x7ce> 801bc74: e9dd 0104 ldrd r0, r1, [sp, #16] 801bc78: 463a mov r2, r7 801bc7a: f7ff f99d bl 801afb8 <__lshift> 801bc7e: 9005 str r0, [sp, #20] 801bc80: 2800 cmp r0, #0 801bc82: f43f ae90 beq.w 801b9a6 <_strtod_l+0x4ee> 801bc86: 9a06 ldr r2, [sp, #24] 801bc88: 9918 ldr r1, [sp, #96] @ 0x60 801bc8a: 9804 ldr r0, [sp, #16] 801bc8c: f7ff fa1e bl 801b0cc <__mdiff> 801bc90: 4604 mov r4, r0 801bc92: 2800 cmp r0, #0 801bc94: f43f ae87 beq.w 801b9a6 <_strtod_l+0x4ee> 801bc98: 68c3 ldr r3, [r0, #12] 801bc9a: 930f str r3, [sp, #60] @ 0x3c 801bc9c: 2300 movs r3, #0 801bc9e: 9905 ldr r1, [sp, #20] 801bca0: 60c3 str r3, [r0, #12] 801bca2: f7ff f9f7 bl 801b094 <__mcmp> 801bca6: 2800 cmp r0, #0 801bca8: da3c bge.n 801bd24 <_strtod_l+0x86c> 801bcaa: 9b0f ldr r3, [sp, #60] @ 0x3c 801bcac: ea53 0308 orrs.w r3, r3, r8 801bcb0: d15e bne.n 801bd70 <_strtod_l+0x8b8> 801bcb2: f3c9 0313 ubfx r3, r9, #0, #20 801bcb6: 464d mov r5, r9 801bcb8: 2b00 cmp r3, #0 801bcba: d159 bne.n 801bd70 <_strtod_l+0x8b8> 801bcbc: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 801bcc0: 0d1b lsrs r3, r3, #20 801bcc2: 051b lsls r3, r3, #20 801bcc4: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000 801bcc8: d952 bls.n 801bd70 <_strtod_l+0x8b8> 801bcca: 6963 ldr r3, [r4, #20] 801bccc: b913 cbnz r3, 801bcd4 <_strtod_l+0x81c> 801bcce: 6923 ldr r3, [r4, #16] 801bcd0: 2b01 cmp r3, #1 801bcd2: dd4d ble.n 801bd70 <_strtod_l+0x8b8> 801bcd4: 4621 mov r1, r4 801bcd6: 2201 movs r2, #1 801bcd8: 9804 ldr r0, [sp, #16] 801bcda: f7ff f96d bl 801afb8 <__lshift> 801bcde: 9905 ldr r1, [sp, #20] 801bce0: 4604 mov r4, r0 801bce2: f7ff f9d7 bl 801b094 <__mcmp> 801bce6: 2800 cmp r0, #0 801bce8: dd42 ble.n 801bd70 <_strtod_l+0x8b8> 801bcea: 4bad ldr r3, [pc, #692] @ (801bfa0 <_strtod_l+0xae8>) 801bcec: 9a07 ldr r2, [sp, #28] 801bcee: 402b ands r3, r5 801bcf0: 2a00 cmp r2, #0 801bcf2: d05f beq.n 801bdb4 <_strtod_l+0x8fc> 801bcf4: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000 801bcf8: d85c bhi.n 801bdb4 <_strtod_l+0x8fc> 801bcfa: f1b3 7f5c cmp.w r3, #57671680 @ 0x3700000 801bcfe: f67f ae8c bls.w 801ba1a <_strtod_l+0x562> 801bd02: 4ba8 ldr r3, [pc, #672] @ (801bfa4 <_strtod_l+0xaec>) 801bd04: 4640 mov r0, r8 801bd06: 4649 mov r1, r9 801bd08: 2200 movs r2, #0 801bd0a: f7e4 fc4d bl 80005a8 <__aeabi_dmul> 801bd0e: 4ba4 ldr r3, [pc, #656] @ (801bfa0 <_strtod_l+0xae8>) 801bd10: 400b ands r3, r1 801bd12: 4680 mov r8, r0 801bd14: 4689 mov r9, r1 801bd16: 2b00 cmp r3, #0 801bd18: f47f ae50 bne.w 801b9bc <_strtod_l+0x504> 801bd1c: 9a04 ldr r2, [sp, #16] 801bd1e: 2322 movs r3, #34 @ 0x22 801bd20: 6013 str r3, [r2, #0] 801bd22: e64b b.n 801b9bc <_strtod_l+0x504> 801bd24: 464d mov r5, r9 801bd26: d162 bne.n 801bdee <_strtod_l+0x936> 801bd28: 9a0f ldr r2, [sp, #60] @ 0x3c 801bd2a: f3c9 0313 ubfx r3, r9, #0, #20 801bd2e: b342 cbz r2, 801bd82 <_strtod_l+0x8ca> 801bd30: 4a9d ldr r2, [pc, #628] @ (801bfa8 <_strtod_l+0xaf0>) 801bd32: 4293 cmp r3, r2 801bd34: d128 bne.n 801bd88 <_strtod_l+0x8d0> 801bd36: 9b07 ldr r3, [sp, #28] 801bd38: 4641 mov r1, r8 801bd3a: b1eb cbz r3, 801bd78 <_strtod_l+0x8c0> 801bd3c: 4b98 ldr r3, [pc, #608] @ (801bfa0 <_strtod_l+0xae8>) 801bd3e: 402b ands r3, r5 801bd40: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000 801bd44: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801bd48: d819 bhi.n 801bd7e <_strtod_l+0x8c6> 801bd4a: 0d1b lsrs r3, r3, #20 801bd4c: f1c3 036b rsb r3, r3, #107 @ 0x6b 801bd50: fa02 f303 lsl.w r3, r2, r3 801bd54: 4299 cmp r1, r3 801bd56: d117 bne.n 801bd88 <_strtod_l+0x8d0> 801bd58: 4b94 ldr r3, [pc, #592] @ (801bfac <_strtod_l+0xaf4>) 801bd5a: 429d cmp r5, r3 801bd5c: d102 bne.n 801bd64 <_strtod_l+0x8ac> 801bd5e: 3101 adds r1, #1 801bd60: f43f ae21 beq.w 801b9a6 <_strtod_l+0x4ee> 801bd64: 4b8e ldr r3, [pc, #568] @ (801bfa0 <_strtod_l+0xae8>) 801bd66: 402b ands r3, r5 801bd68: f503 1980 add.w r9, r3, #1048576 @ 0x100000 801bd6c: f04f 0800 mov.w r8, #0 801bd70: 9b07 ldr r3, [sp, #28] 801bd72: 2b00 cmp r3, #0 801bd74: d1c5 bne.n 801bd02 <_strtod_l+0x84a> 801bd76: e621 b.n 801b9bc <_strtod_l+0x504> 801bd78: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801bd7c: e7ea b.n 801bd54 <_strtod_l+0x89c> 801bd7e: 4613 mov r3, r2 801bd80: e7e8 b.n 801bd54 <_strtod_l+0x89c> 801bd82: ea53 0308 orrs.w r3, r3, r8 801bd86: d0b0 beq.n 801bcea <_strtod_l+0x832> 801bd88: f1bb 0f00 cmp.w fp, #0 801bd8c: d01b beq.n 801bdc6 <_strtod_l+0x90e> 801bd8e: ea1b 0f05 tst.w fp, r5 801bd92: d0ed beq.n 801bd70 <_strtod_l+0x8b8> 801bd94: 9b0f ldr r3, [sp, #60] @ 0x3c 801bd96: 9a07 ldr r2, [sp, #28] 801bd98: 4640 mov r0, r8 801bd9a: 4649 mov r1, r9 801bd9c: b1b3 cbz r3, 801bdcc <_strtod_l+0x914> 801bd9e: f7ff fb6b bl 801b478 801bda2: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801bda6: ec53 2b10 vmov r2, r3, d0 801bdaa: f7e4 fa47 bl 800023c <__adddf3> 801bdae: 4680 mov r8, r0 801bdb0: 4689 mov r9, r1 801bdb2: e7dd b.n 801bd70 <_strtod_l+0x8b8> 801bdb4: f5a3 1380 sub.w r3, r3, #1048576 @ 0x100000 801bdb8: ea6f 5913 mvn.w r9, r3, lsr #20 801bdbc: ea6f 5909 mvn.w r9, r9, lsl #20 801bdc0: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff 801bdc4: e7d4 b.n 801bd70 <_strtod_l+0x8b8> 801bdc6: ea1a 0f08 tst.w sl, r8 801bdca: e7e2 b.n 801bd92 <_strtod_l+0x8da> 801bdcc: f7ff fb54 bl 801b478 801bdd0: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801bdd4: ec53 2b10 vmov r2, r3, d0 801bdd8: f7e4 fa2e bl 8000238 <__aeabi_dsub> 801bddc: 2200 movs r2, #0 801bdde: 2300 movs r3, #0 801bde0: 4680 mov r8, r0 801bde2: 4689 mov r9, r1 801bde4: f7e4 fe48 bl 8000a78 <__aeabi_dcmpeq> 801bde8: 2800 cmp r0, #0 801bdea: d0c1 beq.n 801bd70 <_strtod_l+0x8b8> 801bdec: e615 b.n 801ba1a <_strtod_l+0x562> 801bdee: 9905 ldr r1, [sp, #20] 801bdf0: 4620 mov r0, r4 801bdf2: f7ff facb bl 801b38c <__ratio> 801bdf6: ec57 6b10 vmov r6, r7, d0 801bdfa: 2200 movs r2, #0 801bdfc: f04f 4380 mov.w r3, #1073741824 @ 0x40000000 801be00: 4630 mov r0, r6 801be02: 4639 mov r1, r7 801be04: f7e4 fe4c bl 8000aa0 <__aeabi_dcmple> 801be08: 2800 cmp r0, #0 801be0a: d070 beq.n 801beee <_strtod_l+0xa36> 801be0c: 9b0f ldr r3, [sp, #60] @ 0x3c 801be0e: 2b00 cmp r3, #0 801be10: d17b bne.n 801bf0a <_strtod_l+0xa52> 801be12: f1b8 0f00 cmp.w r8, #0 801be16: d156 bne.n 801bec6 <_strtod_l+0xa0e> 801be18: f3c9 0313 ubfx r3, r9, #0, #20 801be1c: 2b00 cmp r3, #0 801be1e: d158 bne.n 801bed2 <_strtod_l+0xa1a> 801be20: 4b63 ldr r3, [pc, #396] @ (801bfb0 <_strtod_l+0xaf8>) 801be22: 2200 movs r2, #0 801be24: 4630 mov r0, r6 801be26: 4639 mov r1, r7 801be28: f7e4 fe30 bl 8000a8c <__aeabi_dcmplt> 801be2c: 2800 cmp r0, #0 801be2e: d159 bne.n 801bee4 <_strtod_l+0xa2c> 801be30: 4b60 ldr r3, [pc, #384] @ (801bfb4 <_strtod_l+0xafc>) 801be32: 2200 movs r2, #0 801be34: 4630 mov r0, r6 801be36: 4639 mov r1, r7 801be38: f7e4 fbb6 bl 80005a8 <__aeabi_dmul> 801be3c: 4682 mov sl, r0 801be3e: 468b mov fp, r1 801be40: f10b 4300 add.w r3, fp, #2147483648 @ 0x80000000 801be44: f8cd a020 str.w sl, [sp, #32] 801be48: 9309 str r3, [sp, #36] @ 0x24 801be4a: 4b55 ldr r3, [pc, #340] @ (801bfa0 <_strtod_l+0xae8>) 801be4c: 4a54 ldr r2, [pc, #336] @ (801bfa0 <_strtod_l+0xae8>) 801be4e: 402b ands r3, r5 801be50: 9313 str r3, [sp, #76] @ 0x4c 801be52: 4b59 ldr r3, [pc, #356] @ (801bfb8 <_strtod_l+0xb00>) 801be54: 402a ands r2, r5 801be56: 429a cmp r2, r3 801be58: e9dd 6708 ldrd r6, r7, [sp, #32] 801be5c: f040 80b0 bne.w 801bfc0 <_strtod_l+0xb08> 801be60: f1a5 7954 sub.w r9, r5, #55574528 @ 0x3500000 801be64: ec49 8b10 vmov d0, r8, r9 801be68: f7ff f9c8 bl 801b1fc <__ulp> 801be6c: e9dd 2308 ldrd r2, r3, [sp, #32] 801be70: ec51 0b10 vmov r0, r1, d0 801be74: f7e4 fb98 bl 80005a8 <__aeabi_dmul> 801be78: 4642 mov r2, r8 801be7a: 464b mov r3, r9 801be7c: f7e4 f9de bl 800023c <__adddf3> 801be80: 4d47 ldr r5, [pc, #284] @ (801bfa0 <_strtod_l+0xae8>) 801be82: 4a4e ldr r2, [pc, #312] @ (801bfbc <_strtod_l+0xb04>) 801be84: 400d ands r5, r1 801be86: 4295 cmp r5, r2 801be88: 4680 mov r8, r0 801be8a: d945 bls.n 801bf18 <_strtod_l+0xa60> 801be8c: 9a0d ldr r2, [sp, #52] @ 0x34 801be8e: 4b47 ldr r3, [pc, #284] @ (801bfac <_strtod_l+0xaf4>) 801be90: 429a cmp r2, r3 801be92: d103 bne.n 801be9c <_strtod_l+0x9e4> 801be94: 9b0c ldr r3, [sp, #48] @ 0x30 801be96: 3301 adds r3, #1 801be98: f43f ad85 beq.w 801b9a6 <_strtod_l+0x4ee> 801be9c: f8df 910c ldr.w r9, [pc, #268] @ 801bfac <_strtod_l+0xaf4> 801bea0: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff 801bea4: 9918 ldr r1, [sp, #96] @ 0x60 801bea6: 9804 ldr r0, [sp, #16] 801bea8: f7fe fe6c bl 801ab84 <_Bfree> 801beac: 9906 ldr r1, [sp, #24] 801beae: 9804 ldr r0, [sp, #16] 801beb0: f7fe fe68 bl 801ab84 <_Bfree> 801beb4: e9dd 0104 ldrd r0, r1, [sp, #16] 801beb8: f7fe fe64 bl 801ab84 <_Bfree> 801bebc: 9804 ldr r0, [sp, #16] 801bebe: 4621 mov r1, r4 801bec0: f7fe fe60 bl 801ab84 <_Bfree> 801bec4: e625 b.n 801bb12 <_strtod_l+0x65a> 801bec6: f1b8 0f01 cmp.w r8, #1 801beca: d102 bne.n 801bed2 <_strtod_l+0xa1a> 801becc: 2d00 cmp r5, #0 801bece: f43f ada4 beq.w 801ba1a <_strtod_l+0x562> 801bed2: ed9f 7b2b vldr d7, [pc, #172] @ 801bf80 <_strtod_l+0xac8> 801bed6: f8df b0d8 ldr.w fp, [pc, #216] @ 801bfb0 <_strtod_l+0xaf8> 801beda: ed8d 7b08 vstr d7, [sp, #32] 801bede: f04f 0a00 mov.w sl, #0 801bee2: e7b2 b.n 801be4a <_strtod_l+0x992> 801bee4: f8df b0cc ldr.w fp, [pc, #204] @ 801bfb4 <_strtod_l+0xafc> 801bee8: f04f 0a00 mov.w sl, #0 801beec: e7a8 b.n 801be40 <_strtod_l+0x988> 801beee: 4b31 ldr r3, [pc, #196] @ (801bfb4 <_strtod_l+0xafc>) 801bef0: 2200 movs r2, #0 801bef2: 4630 mov r0, r6 801bef4: 4639 mov r1, r7 801bef6: f7e4 fb57 bl 80005a8 <__aeabi_dmul> 801befa: 9b0f ldr r3, [sp, #60] @ 0x3c 801befc: 4682 mov sl, r0 801befe: 468b mov fp, r1 801bf00: 2b00 cmp r3, #0 801bf02: d09d beq.n 801be40 <_strtod_l+0x988> 801bf04: e9cd ab08 strd sl, fp, [sp, #32] 801bf08: e79f b.n 801be4a <_strtod_l+0x992> 801bf0a: ed9f 7b1f vldr d7, [pc, #124] @ 801bf88 <_strtod_l+0xad0> 801bf0e: ed8d 7b08 vstr d7, [sp, #32] 801bf12: ec5b ab17 vmov sl, fp, d7 801bf16: e798 b.n 801be4a <_strtod_l+0x992> 801bf18: f101 7954 add.w r9, r1, #55574528 @ 0x3500000 801bf1c: 9b07 ldr r3, [sp, #28] 801bf1e: 2b00 cmp r3, #0 801bf20: d1c0 bne.n 801bea4 <_strtod_l+0x9ec> 801bf22: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 801bf26: 9a13 ldr r2, [sp, #76] @ 0x4c 801bf28: 0d1b lsrs r3, r3, #20 801bf2a: 051b lsls r3, r3, #20 801bf2c: 429a cmp r2, r3 801bf2e: d1b9 bne.n 801bea4 <_strtod_l+0x9ec> 801bf30: 4650 mov r0, sl 801bf32: 4659 mov r1, fp 801bf34: f7e4 fe80 bl 8000c38 <__aeabi_d2lz> 801bf38: f7e4 fb08 bl 800054c <__aeabi_l2d> 801bf3c: 4602 mov r2, r0 801bf3e: 460b mov r3, r1 801bf40: 4650 mov r0, sl 801bf42: 4659 mov r1, fp 801bf44: f7e4 f978 bl 8000238 <__aeabi_dsub> 801bf48: 9a0f ldr r2, [sp, #60] @ 0x3c 801bf4a: f3c9 0313 ubfx r3, r9, #0, #20 801bf4e: ea43 0308 orr.w r3, r3, r8 801bf52: 4313 orrs r3, r2 801bf54: 4606 mov r6, r0 801bf56: 460f mov r7, r1 801bf58: d06b beq.n 801c032 <_strtod_l+0xb7a> 801bf5a: a30d add r3, pc, #52 @ (adr r3, 801bf90 <_strtod_l+0xad8>) 801bf5c: e9d3 2300 ldrd r2, r3, [r3] 801bf60: f7e4 fd94 bl 8000a8c <__aeabi_dcmplt> 801bf64: 2800 cmp r0, #0 801bf66: f47f ad29 bne.w 801b9bc <_strtod_l+0x504> 801bf6a: a30b add r3, pc, #44 @ (adr r3, 801bf98 <_strtod_l+0xae0>) 801bf6c: e9d3 2300 ldrd r2, r3, [r3] 801bf70: 4630 mov r0, r6 801bf72: 4639 mov r1, r7 801bf74: f7e4 fda8 bl 8000ac8 <__aeabi_dcmpgt> 801bf78: 2800 cmp r0, #0 801bf7a: d093 beq.n 801bea4 <_strtod_l+0x9ec> 801bf7c: e51e b.n 801b9bc <_strtod_l+0x504> 801bf7e: bf00 nop 801bf80: 00000000 .word 0x00000000 801bf84: bff00000 .word 0xbff00000 801bf88: 00000000 .word 0x00000000 801bf8c: 3ff00000 .word 0x3ff00000 801bf90: 94a03595 .word 0x94a03595 801bf94: 3fdfffff .word 0x3fdfffff 801bf98: 35afe535 .word 0x35afe535 801bf9c: 3fe00000 .word 0x3fe00000 801bfa0: 7ff00000 .word 0x7ff00000 801bfa4: 39500000 .word 0x39500000 801bfa8: 000fffff .word 0x000fffff 801bfac: 7fefffff .word 0x7fefffff 801bfb0: 3ff00000 .word 0x3ff00000 801bfb4: 3fe00000 .word 0x3fe00000 801bfb8: 7fe00000 .word 0x7fe00000 801bfbc: 7c9fffff .word 0x7c9fffff 801bfc0: 9b07 ldr r3, [sp, #28] 801bfc2: b313 cbz r3, 801c00a <_strtod_l+0xb52> 801bfc4: 9b13 ldr r3, [sp, #76] @ 0x4c 801bfc6: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000 801bfca: d81e bhi.n 801c00a <_strtod_l+0xb52> 801bfcc: a324 add r3, pc, #144 @ (adr r3, 801c060 <_strtod_l+0xba8>) 801bfce: e9d3 2300 ldrd r2, r3, [r3] 801bfd2: 4650 mov r0, sl 801bfd4: 4659 mov r1, fp 801bfd6: f7e4 fd63 bl 8000aa0 <__aeabi_dcmple> 801bfda: b190 cbz r0, 801c002 <_strtod_l+0xb4a> 801bfdc: 4659 mov r1, fp 801bfde: 4650 mov r0, sl 801bfe0: f7e4 fdba bl 8000b58 <__aeabi_d2uiz> 801bfe4: 2801 cmp r0, #1 801bfe6: bf38 it cc 801bfe8: 2001 movcc r0, #1 801bfea: f7e4 fa63 bl 80004b4 <__aeabi_ui2d> 801bfee: 9b0f ldr r3, [sp, #60] @ 0x3c 801bff0: 4682 mov sl, r0 801bff2: 468b mov fp, r1 801bff4: b9d3 cbnz r3, 801c02c <_strtod_l+0xb74> 801bff6: f101 4300 add.w r3, r1, #2147483648 @ 0x80000000 801bffa: 9010 str r0, [sp, #64] @ 0x40 801bffc: 9311 str r3, [sp, #68] @ 0x44 801bffe: e9dd 6710 ldrd r6, r7, [sp, #64] @ 0x40 801c002: 9a13 ldr r2, [sp, #76] @ 0x4c 801c004: f107 63d6 add.w r3, r7, #112197632 @ 0x6b00000 801c008: 1a9f subs r7, r3, r2 801c00a: ed9d 0b0c vldr d0, [sp, #48] @ 0x30 801c00e: f7ff f8f5 bl 801b1fc <__ulp> 801c012: 4630 mov r0, r6 801c014: ec53 2b10 vmov r2, r3, d0 801c018: 4639 mov r1, r7 801c01a: f7e4 fac5 bl 80005a8 <__aeabi_dmul> 801c01e: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 801c022: f7e4 f90b bl 800023c <__adddf3> 801c026: 4680 mov r8, r0 801c028: 4689 mov r9, r1 801c02a: e777 b.n 801bf1c <_strtod_l+0xa64> 801c02c: e9cd ab10 strd sl, fp, [sp, #64] @ 0x40 801c030: e7e5 b.n 801bffe <_strtod_l+0xb46> 801c032: a30d add r3, pc, #52 @ (adr r3, 801c068 <_strtod_l+0xbb0>) 801c034: e9d3 2300 ldrd r2, r3, [r3] 801c038: f7e4 fd28 bl 8000a8c <__aeabi_dcmplt> 801c03c: e79c b.n 801bf78 <_strtod_l+0xac0> 801c03e: 2300 movs r3, #0 801c040: 930b str r3, [sp, #44] @ 0x2c 801c042: 9a15 ldr r2, [sp, #84] @ 0x54 801c044: 9b17 ldr r3, [sp, #92] @ 0x5c 801c046: 6013 str r3, [r2, #0] 801c048: f7ff ba8c b.w 801b564 <_strtod_l+0xac> 801c04c: 2a65 cmp r2, #101 @ 0x65 801c04e: f43f ab6a beq.w 801b726 <_strtod_l+0x26e> 801c052: 2a45 cmp r2, #69 @ 0x45 801c054: f43f ab67 beq.w 801b726 <_strtod_l+0x26e> 801c058: 2301 movs r3, #1 801c05a: 9307 str r3, [sp, #28] 801c05c: f7ff bba1 b.w 801b7a2 <_strtod_l+0x2ea> 801c060: ffc00000 .word 0xffc00000 801c064: 41dfffff .word 0x41dfffff 801c068: 94a03595 .word 0x94a03595 801c06c: 3fcfffff .word 0x3fcfffff 0801c070 <_strtod_r>: 801c070: 4b01 ldr r3, [pc, #4] @ (801c078 <_strtod_r+0x8>) 801c072: f7ff ba21 b.w 801b4b8 <_strtod_l> 801c076: bf00 nop 801c078: 2000016c .word 0x2000016c 0801c07c <_strtol_l.isra.0>: 801c07c: 2b24 cmp r3, #36 @ 0x24 801c07e: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801c082: 4686 mov lr, r0 801c084: 4690 mov r8, r2 801c086: d801 bhi.n 801c08c <_strtol_l.isra.0+0x10> 801c088: 2b01 cmp r3, #1 801c08a: d106 bne.n 801c09a <_strtol_l.isra.0+0x1e> 801c08c: f7fd fd94 bl 8019bb8 <__errno> 801c090: 2316 movs r3, #22 801c092: 6003 str r3, [r0, #0] 801c094: 2000 movs r0, #0 801c096: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801c09a: 4834 ldr r0, [pc, #208] @ (801c16c <_strtol_l.isra.0+0xf0>) 801c09c: 460d mov r5, r1 801c09e: 462a mov r2, r5 801c0a0: f815 4b01 ldrb.w r4, [r5], #1 801c0a4: 5d06 ldrb r6, [r0, r4] 801c0a6: f016 0608 ands.w r6, r6, #8 801c0aa: d1f8 bne.n 801c09e <_strtol_l.isra.0+0x22> 801c0ac: 2c2d cmp r4, #45 @ 0x2d 801c0ae: d110 bne.n 801c0d2 <_strtol_l.isra.0+0x56> 801c0b0: 782c ldrb r4, [r5, #0] 801c0b2: 2601 movs r6, #1 801c0b4: 1c95 adds r5, r2, #2 801c0b6: f033 0210 bics.w r2, r3, #16 801c0ba: d115 bne.n 801c0e8 <_strtol_l.isra.0+0x6c> 801c0bc: 2c30 cmp r4, #48 @ 0x30 801c0be: d10d bne.n 801c0dc <_strtol_l.isra.0+0x60> 801c0c0: 782a ldrb r2, [r5, #0] 801c0c2: f002 02df and.w r2, r2, #223 @ 0xdf 801c0c6: 2a58 cmp r2, #88 @ 0x58 801c0c8: d108 bne.n 801c0dc <_strtol_l.isra.0+0x60> 801c0ca: 786c ldrb r4, [r5, #1] 801c0cc: 3502 adds r5, #2 801c0ce: 2310 movs r3, #16 801c0d0: e00a b.n 801c0e8 <_strtol_l.isra.0+0x6c> 801c0d2: 2c2b cmp r4, #43 @ 0x2b 801c0d4: bf04 itt eq 801c0d6: 782c ldrbeq r4, [r5, #0] 801c0d8: 1c95 addeq r5, r2, #2 801c0da: e7ec b.n 801c0b6 <_strtol_l.isra.0+0x3a> 801c0dc: 2b00 cmp r3, #0 801c0de: d1f6 bne.n 801c0ce <_strtol_l.isra.0+0x52> 801c0e0: 2c30 cmp r4, #48 @ 0x30 801c0e2: bf14 ite ne 801c0e4: 230a movne r3, #10 801c0e6: 2308 moveq r3, #8 801c0e8: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000 801c0ec: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff 801c0f0: 2200 movs r2, #0 801c0f2: fbbc f9f3 udiv r9, ip, r3 801c0f6: 4610 mov r0, r2 801c0f8: fb03 ca19 mls sl, r3, r9, ip 801c0fc: f1a4 0730 sub.w r7, r4, #48 @ 0x30 801c100: 2f09 cmp r7, #9 801c102: d80f bhi.n 801c124 <_strtol_l.isra.0+0xa8> 801c104: 463c mov r4, r7 801c106: 42a3 cmp r3, r4 801c108: dd1b ble.n 801c142 <_strtol_l.isra.0+0xc6> 801c10a: 1c57 adds r7, r2, #1 801c10c: d007 beq.n 801c11e <_strtol_l.isra.0+0xa2> 801c10e: 4581 cmp r9, r0 801c110: d314 bcc.n 801c13c <_strtol_l.isra.0+0xc0> 801c112: d101 bne.n 801c118 <_strtol_l.isra.0+0x9c> 801c114: 45a2 cmp sl, r4 801c116: db11 blt.n 801c13c <_strtol_l.isra.0+0xc0> 801c118: fb00 4003 mla r0, r0, r3, r4 801c11c: 2201 movs r2, #1 801c11e: f815 4b01 ldrb.w r4, [r5], #1 801c122: e7eb b.n 801c0fc <_strtol_l.isra.0+0x80> 801c124: f1a4 0741 sub.w r7, r4, #65 @ 0x41 801c128: 2f19 cmp r7, #25 801c12a: d801 bhi.n 801c130 <_strtol_l.isra.0+0xb4> 801c12c: 3c37 subs r4, #55 @ 0x37 801c12e: e7ea b.n 801c106 <_strtol_l.isra.0+0x8a> 801c130: f1a4 0761 sub.w r7, r4, #97 @ 0x61 801c134: 2f19 cmp r7, #25 801c136: d804 bhi.n 801c142 <_strtol_l.isra.0+0xc6> 801c138: 3c57 subs r4, #87 @ 0x57 801c13a: e7e4 b.n 801c106 <_strtol_l.isra.0+0x8a> 801c13c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801c140: e7ed b.n 801c11e <_strtol_l.isra.0+0xa2> 801c142: 1c53 adds r3, r2, #1 801c144: d108 bne.n 801c158 <_strtol_l.isra.0+0xdc> 801c146: 2322 movs r3, #34 @ 0x22 801c148: f8ce 3000 str.w r3, [lr] 801c14c: 4660 mov r0, ip 801c14e: f1b8 0f00 cmp.w r8, #0 801c152: d0a0 beq.n 801c096 <_strtol_l.isra.0+0x1a> 801c154: 1e69 subs r1, r5, #1 801c156: e006 b.n 801c166 <_strtol_l.isra.0+0xea> 801c158: b106 cbz r6, 801c15c <_strtol_l.isra.0+0xe0> 801c15a: 4240 negs r0, r0 801c15c: f1b8 0f00 cmp.w r8, #0 801c160: d099 beq.n 801c096 <_strtol_l.isra.0+0x1a> 801c162: 2a00 cmp r2, #0 801c164: d1f6 bne.n 801c154 <_strtol_l.isra.0+0xd8> 801c166: f8c8 1000 str.w r1, [r8] 801c16a: e794 b.n 801c096 <_strtol_l.isra.0+0x1a> 801c16c: 0801dfd9 .word 0x0801dfd9 0801c170 <_strtol_r>: 801c170: f7ff bf84 b.w 801c07c <_strtol_l.isra.0> 0801c174 <__ssputs_r>: 801c174: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801c178: 688e ldr r6, [r1, #8] 801c17a: 461f mov r7, r3 801c17c: 42be cmp r6, r7 801c17e: 4682 mov sl, r0 801c180: 460c mov r4, r1 801c182: 4690 mov r8, r2 801c184: 4633 mov r3, r6 801c186: d853 bhi.n 801c230 <__ssputs_r+0xbc> 801c188: f9b1 000c ldrsh.w r0, [r1, #12] 801c18c: f410 6f90 tst.w r0, #1152 @ 0x480 801c190: d02b beq.n 801c1ea <__ssputs_r+0x76> 801c192: 6965 ldr r5, [r4, #20] 801c194: 6823 ldr r3, [r4, #0] 801c196: 6909 ldr r1, [r1, #16] 801c198: eb05 0545 add.w r5, r5, r5, lsl #1 801c19c: eba3 0901 sub.w r9, r3, r1 801c1a0: eb05 75d5 add.w r5, r5, r5, lsr #31 801c1a4: 1c7b adds r3, r7, #1 801c1a6: 106d asrs r5, r5, #1 801c1a8: 444b add r3, r9 801c1aa: 42ab cmp r3, r5 801c1ac: 462a mov r2, r5 801c1ae: bf84 itt hi 801c1b0: 461d movhi r5, r3 801c1b2: 462a movhi r2, r5 801c1b4: 0543 lsls r3, r0, #21 801c1b6: d527 bpl.n 801c208 <__ssputs_r+0x94> 801c1b8: 4611 mov r1, r2 801c1ba: 4650 mov r0, sl 801c1bc: f7fe fc18 bl 801a9f0 <_malloc_r> 801c1c0: 4606 mov r6, r0 801c1c2: b358 cbz r0, 801c21c <__ssputs_r+0xa8> 801c1c4: 6921 ldr r1, [r4, #16] 801c1c6: 464a mov r2, r9 801c1c8: f7fd fd23 bl 8019c12 801c1cc: 89a3 ldrh r3, [r4, #12] 801c1ce: f423 6390 bic.w r3, r3, #1152 @ 0x480 801c1d2: f043 0380 orr.w r3, r3, #128 @ 0x80 801c1d6: 81a3 strh r3, [r4, #12] 801c1d8: 6126 str r6, [r4, #16] 801c1da: 6165 str r5, [r4, #20] 801c1dc: 444e add r6, r9 801c1de: eba5 0509 sub.w r5, r5, r9 801c1e2: 6026 str r6, [r4, #0] 801c1e4: 60a5 str r5, [r4, #8] 801c1e6: 463e mov r6, r7 801c1e8: 463b mov r3, r7 801c1ea: 461f mov r7, r3 801c1ec: 6820 ldr r0, [r4, #0] 801c1ee: 463a mov r2, r7 801c1f0: 4641 mov r1, r8 801c1f2: f000 fb5c bl 801c8ae 801c1f6: 68a3 ldr r3, [r4, #8] 801c1f8: 1b9b subs r3, r3, r6 801c1fa: 60a3 str r3, [r4, #8] 801c1fc: 6823 ldr r3, [r4, #0] 801c1fe: 443b add r3, r7 801c200: 6023 str r3, [r4, #0] 801c202: 2000 movs r0, #0 801c204: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801c208: 4650 mov r0, sl 801c20a: f000 ff34 bl 801d076 <_realloc_r> 801c20e: 4606 mov r6, r0 801c210: 2800 cmp r0, #0 801c212: d1e1 bne.n 801c1d8 <__ssputs_r+0x64> 801c214: 6921 ldr r1, [r4, #16] 801c216: 4650 mov r0, sl 801c218: f7fe fb76 bl 801a908 <_free_r> 801c21c: 230c movs r3, #12 801c21e: f8ca 3000 str.w r3, [sl] 801c222: 89a3 ldrh r3, [r4, #12] 801c224: f043 0340 orr.w r3, r3, #64 @ 0x40 801c228: 81a3 strh r3, [r4, #12] 801c22a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801c22e: e7e9 b.n 801c204 <__ssputs_r+0x90> 801c230: 463e mov r6, r7 801c232: e7db b.n 801c1ec <__ssputs_r+0x78> 0801c234 <_svfiprintf_r>: 801c234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801c238: 461f mov r7, r3 801c23a: 898b ldrh r3, [r1, #12] 801c23c: 061b lsls r3, r3, #24 801c23e: b09c sub sp, #112 @ 0x70 801c240: 4606 mov r6, r0 801c242: 460d mov r5, r1 801c244: 4614 mov r4, r2 801c246: d510 bpl.n 801c26a <_svfiprintf_r+0x36> 801c248: 690b ldr r3, [r1, #16] 801c24a: b973 cbnz r3, 801c26a <_svfiprintf_r+0x36> 801c24c: 2140 movs r1, #64 @ 0x40 801c24e: f7fe fbcf bl 801a9f0 <_malloc_r> 801c252: 6028 str r0, [r5, #0] 801c254: 6128 str r0, [r5, #16] 801c256: b930 cbnz r0, 801c266 <_svfiprintf_r+0x32> 801c258: 230c movs r3, #12 801c25a: 6033 str r3, [r6, #0] 801c25c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801c260: b01c add sp, #112 @ 0x70 801c262: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801c266: 2340 movs r3, #64 @ 0x40 801c268: 616b str r3, [r5, #20] 801c26a: 2300 movs r3, #0 801c26c: 9309 str r3, [sp, #36] @ 0x24 801c26e: 2320 movs r3, #32 801c270: f88d 3029 strb.w r3, [sp, #41] @ 0x29 801c274: 9703 str r7, [sp, #12] 801c276: 2330 movs r3, #48 @ 0x30 801c278: 4f65 ldr r7, [pc, #404] @ (801c410 <_svfiprintf_r+0x1dc>) 801c27a: f88d 302a strb.w r3, [sp, #42] @ 0x2a 801c27e: f04f 0801 mov.w r8, #1 801c282: 4623 mov r3, r4 801c284: 4699 mov r9, r3 801c286: f813 2b01 ldrb.w r2, [r3], #1 801c28a: b10a cbz r2, 801c290 <_svfiprintf_r+0x5c> 801c28c: 2a25 cmp r2, #37 @ 0x25 801c28e: d1f9 bne.n 801c284 <_svfiprintf_r+0x50> 801c290: ebb9 0a04 subs.w sl, r9, r4 801c294: d00b beq.n 801c2ae <_svfiprintf_r+0x7a> 801c296: 4653 mov r3, sl 801c298: 4622 mov r2, r4 801c29a: 4629 mov r1, r5 801c29c: 4630 mov r0, r6 801c29e: f7ff ff69 bl 801c174 <__ssputs_r> 801c2a2: 3001 adds r0, #1 801c2a4: f000 80a4 beq.w 801c3f0 <_svfiprintf_r+0x1bc> 801c2a8: 9a09 ldr r2, [sp, #36] @ 0x24 801c2aa: 4452 add r2, sl 801c2ac: 9209 str r2, [sp, #36] @ 0x24 801c2ae: f899 3000 ldrb.w r3, [r9] 801c2b2: 2b00 cmp r3, #0 801c2b4: f000 809c beq.w 801c3f0 <_svfiprintf_r+0x1bc> 801c2b8: 2300 movs r3, #0 801c2ba: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801c2be: e9cd 2305 strd r2, r3, [sp, #20] 801c2c2: f109 0901 add.w r9, r9, #1 801c2c6: 9304 str r3, [sp, #16] 801c2c8: 9307 str r3, [sp, #28] 801c2ca: f88d 3053 strb.w r3, [sp, #83] @ 0x53 801c2ce: 931a str r3, [sp, #104] @ 0x68 801c2d0: 464c mov r4, r9 801c2d2: 484f ldr r0, [pc, #316] @ (801c410 <_svfiprintf_r+0x1dc>) 801c2d4: f814 1b01 ldrb.w r1, [r4], #1 801c2d8: 2205 movs r2, #5 801c2da: f7e3 ff51 bl 8000180 801c2de: 9b04 ldr r3, [sp, #16] 801c2e0: b9d0 cbnz r0, 801c318 <_svfiprintf_r+0xe4> 801c2e2: 06d8 lsls r0, r3, #27 801c2e4: bf44 itt mi 801c2e6: 2220 movmi r2, #32 801c2e8: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53 801c2ec: 0719 lsls r1, r3, #28 801c2ee: bf44 itt mi 801c2f0: 222b movmi r2, #43 @ 0x2b 801c2f2: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53 801c2f6: f899 2000 ldrb.w r2, [r9] 801c2fa: 2a2a cmp r2, #42 @ 0x2a 801c2fc: d013 beq.n 801c326 <_svfiprintf_r+0xf2> 801c2fe: 9a07 ldr r2, [sp, #28] 801c300: 464c mov r4, r9 801c302: 2000 movs r0, #0 801c304: f04f 0c0a mov.w ip, #10 801c308: 4621 mov r1, r4 801c30a: f811 3b01 ldrb.w r3, [r1], #1 801c30e: 3b30 subs r3, #48 @ 0x30 801c310: 2b09 cmp r3, #9 801c312: d949 bls.n 801c3a8 <_svfiprintf_r+0x174> 801c314: b968 cbnz r0, 801c332 <_svfiprintf_r+0xfe> 801c316: e013 b.n 801c340 <_svfiprintf_r+0x10c> 801c318: 1bc0 subs r0, r0, r7 801c31a: fa08 f000 lsl.w r0, r8, r0 801c31e: 4318 orrs r0, r3 801c320: 9004 str r0, [sp, #16] 801c322: 46a1 mov r9, r4 801c324: e7d4 b.n 801c2d0 <_svfiprintf_r+0x9c> 801c326: 9a03 ldr r2, [sp, #12] 801c328: 1d11 adds r1, r2, #4 801c32a: 6812 ldr r2, [r2, #0] 801c32c: 9103 str r1, [sp, #12] 801c32e: 2a00 cmp r2, #0 801c330: db01 blt.n 801c336 <_svfiprintf_r+0x102> 801c332: 9207 str r2, [sp, #28] 801c334: e004 b.n 801c340 <_svfiprintf_r+0x10c> 801c336: 4252 negs r2, r2 801c338: f043 0302 orr.w r3, r3, #2 801c33c: 9207 str r2, [sp, #28] 801c33e: 9304 str r3, [sp, #16] 801c340: 7823 ldrb r3, [r4, #0] 801c342: 2b2e cmp r3, #46 @ 0x2e 801c344: d10a bne.n 801c35c <_svfiprintf_r+0x128> 801c346: 7863 ldrb r3, [r4, #1] 801c348: 2b2a cmp r3, #42 @ 0x2a 801c34a: d132 bne.n 801c3b2 <_svfiprintf_r+0x17e> 801c34c: 9b03 ldr r3, [sp, #12] 801c34e: 1d1a adds r2, r3, #4 801c350: 681b ldr r3, [r3, #0] 801c352: 9203 str r2, [sp, #12] 801c354: ea43 73e3 orr.w r3, r3, r3, asr #31 801c358: 3402 adds r4, #2 801c35a: 9305 str r3, [sp, #20] 801c35c: f8df 90c0 ldr.w r9, [pc, #192] @ 801c420 <_svfiprintf_r+0x1ec> 801c360: 7821 ldrb r1, [r4, #0] 801c362: 2203 movs r2, #3 801c364: 4648 mov r0, r9 801c366: f7e3 ff0b bl 8000180 801c36a: b138 cbz r0, 801c37c <_svfiprintf_r+0x148> 801c36c: 9b04 ldr r3, [sp, #16] 801c36e: eba0 0009 sub.w r0, r0, r9 801c372: 2240 movs r2, #64 @ 0x40 801c374: 4082 lsls r2, r0 801c376: 4313 orrs r3, r2 801c378: 3401 adds r4, #1 801c37a: 9304 str r3, [sp, #16] 801c37c: f814 1b01 ldrb.w r1, [r4], #1 801c380: 4824 ldr r0, [pc, #144] @ (801c414 <_svfiprintf_r+0x1e0>) 801c382: f88d 1028 strb.w r1, [sp, #40] @ 0x28 801c386: 2206 movs r2, #6 801c388: f7e3 fefa bl 8000180 801c38c: 2800 cmp r0, #0 801c38e: d035 beq.n 801c3fc <_svfiprintf_r+0x1c8> 801c390: 4821 ldr r0, [pc, #132] @ (801c418 <_svfiprintf_r+0x1e4>) 801c392: bb18 cbnz r0, 801c3dc <_svfiprintf_r+0x1a8> 801c394: 9b03 ldr r3, [sp, #12] 801c396: 3307 adds r3, #7 801c398: f023 0307 bic.w r3, r3, #7 801c39c: 3308 adds r3, #8 801c39e: 9303 str r3, [sp, #12] 801c3a0: 9b09 ldr r3, [sp, #36] @ 0x24 801c3a2: 4403 add r3, r0 801c3a4: 9309 str r3, [sp, #36] @ 0x24 801c3a6: e76c b.n 801c282 <_svfiprintf_r+0x4e> 801c3a8: fb0c 3202 mla r2, ip, r2, r3 801c3ac: 460c mov r4, r1 801c3ae: 2001 movs r0, #1 801c3b0: e7aa b.n 801c308 <_svfiprintf_r+0xd4> 801c3b2: 2300 movs r3, #0 801c3b4: 3401 adds r4, #1 801c3b6: 9305 str r3, [sp, #20] 801c3b8: 4619 mov r1, r3 801c3ba: f04f 0c0a mov.w ip, #10 801c3be: 4620 mov r0, r4 801c3c0: f810 2b01 ldrb.w r2, [r0], #1 801c3c4: 3a30 subs r2, #48 @ 0x30 801c3c6: 2a09 cmp r2, #9 801c3c8: d903 bls.n 801c3d2 <_svfiprintf_r+0x19e> 801c3ca: 2b00 cmp r3, #0 801c3cc: d0c6 beq.n 801c35c <_svfiprintf_r+0x128> 801c3ce: 9105 str r1, [sp, #20] 801c3d0: e7c4 b.n 801c35c <_svfiprintf_r+0x128> 801c3d2: fb0c 2101 mla r1, ip, r1, r2 801c3d6: 4604 mov r4, r0 801c3d8: 2301 movs r3, #1 801c3da: e7f0 b.n 801c3be <_svfiprintf_r+0x18a> 801c3dc: ab03 add r3, sp, #12 801c3de: 9300 str r3, [sp, #0] 801c3e0: 462a mov r2, r5 801c3e2: 4b0e ldr r3, [pc, #56] @ (801c41c <_svfiprintf_r+0x1e8>) 801c3e4: a904 add r1, sp, #16 801c3e6: 4630 mov r0, r6 801c3e8: f7fc fba0 bl 8018b2c <_printf_float> 801c3ec: 1c42 adds r2, r0, #1 801c3ee: d1d7 bne.n 801c3a0 <_svfiprintf_r+0x16c> 801c3f0: 89ab ldrh r3, [r5, #12] 801c3f2: 065b lsls r3, r3, #25 801c3f4: f53f af32 bmi.w 801c25c <_svfiprintf_r+0x28> 801c3f8: 9809 ldr r0, [sp, #36] @ 0x24 801c3fa: e731 b.n 801c260 <_svfiprintf_r+0x2c> 801c3fc: ab03 add r3, sp, #12 801c3fe: 9300 str r3, [sp, #0] 801c400: 462a mov r2, r5 801c402: 4b06 ldr r3, [pc, #24] @ (801c41c <_svfiprintf_r+0x1e8>) 801c404: a904 add r1, sp, #16 801c406: 4630 mov r0, r6 801c408: f7fc fe26 bl 8019058 <_printf_i> 801c40c: e7ee b.n 801c3ec <_svfiprintf_r+0x1b8> 801c40e: bf00 nop 801c410: 0801ddd1 .word 0x0801ddd1 801c414: 0801dddb .word 0x0801dddb 801c418: 08018b2d .word 0x08018b2d 801c41c: 0801c175 .word 0x0801c175 801c420: 0801ddd7 .word 0x0801ddd7 0801c424 <__sfputc_r>: 801c424: 6893 ldr r3, [r2, #8] 801c426: 3b01 subs r3, #1 801c428: 2b00 cmp r3, #0 801c42a: b410 push {r4} 801c42c: 6093 str r3, [r2, #8] 801c42e: da08 bge.n 801c442 <__sfputc_r+0x1e> 801c430: 6994 ldr r4, [r2, #24] 801c432: 42a3 cmp r3, r4 801c434: db01 blt.n 801c43a <__sfputc_r+0x16> 801c436: 290a cmp r1, #10 801c438: d103 bne.n 801c442 <__sfputc_r+0x1e> 801c43a: f85d 4b04 ldr.w r4, [sp], #4 801c43e: f7fd bad7 b.w 80199f0 <__swbuf_r> 801c442: 6813 ldr r3, [r2, #0] 801c444: 1c58 adds r0, r3, #1 801c446: 6010 str r0, [r2, #0] 801c448: 7019 strb r1, [r3, #0] 801c44a: 4608 mov r0, r1 801c44c: f85d 4b04 ldr.w r4, [sp], #4 801c450: 4770 bx lr 0801c452 <__sfputs_r>: 801c452: b5f8 push {r3, r4, r5, r6, r7, lr} 801c454: 4606 mov r6, r0 801c456: 460f mov r7, r1 801c458: 4614 mov r4, r2 801c45a: 18d5 adds r5, r2, r3 801c45c: 42ac cmp r4, r5 801c45e: d101 bne.n 801c464 <__sfputs_r+0x12> 801c460: 2000 movs r0, #0 801c462: e007 b.n 801c474 <__sfputs_r+0x22> 801c464: f814 1b01 ldrb.w r1, [r4], #1 801c468: 463a mov r2, r7 801c46a: 4630 mov r0, r6 801c46c: f7ff ffda bl 801c424 <__sfputc_r> 801c470: 1c43 adds r3, r0, #1 801c472: d1f3 bne.n 801c45c <__sfputs_r+0xa> 801c474: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 0801c478 <_vfiprintf_r>: 801c478: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801c47c: 460d mov r5, r1 801c47e: b09c sub sp, #112 @ 0x70 801c480: 4614 mov r4, r2 801c482: 461f mov r7, r3 801c484: 4606 mov r6, r0 801c486: b118 cbz r0, 801c490 <_vfiprintf_r+0x18> 801c488: 6a03 ldr r3, [r0, #32] 801c48a: b90b cbnz r3, 801c490 <_vfiprintf_r+0x18> 801c48c: f7fd f9a4 bl 80197d8 <__sinit> 801c490: 6e6b ldr r3, [r5, #100] @ 0x64 801c492: 07d9 lsls r1, r3, #31 801c494: d405 bmi.n 801c4a2 <_vfiprintf_r+0x2a> 801c496: 89ab ldrh r3, [r5, #12] 801c498: 059a lsls r2, r3, #22 801c49a: d402 bmi.n 801c4a2 <_vfiprintf_r+0x2a> 801c49c: 6da8 ldr r0, [r5, #88] @ 0x58 801c49e: f7fd fbb6 bl 8019c0e <__retarget_lock_acquire_recursive> 801c4a2: 89ab ldrh r3, [r5, #12] 801c4a4: 071b lsls r3, r3, #28 801c4a6: d501 bpl.n 801c4ac <_vfiprintf_r+0x34> 801c4a8: 692b ldr r3, [r5, #16] 801c4aa: b99b cbnz r3, 801c4d4 <_vfiprintf_r+0x5c> 801c4ac: 4629 mov r1, r5 801c4ae: 4630 mov r0, r6 801c4b0: f7fd fadc bl 8019a6c <__swsetup_r> 801c4b4: b170 cbz r0, 801c4d4 <_vfiprintf_r+0x5c> 801c4b6: 6e6b ldr r3, [r5, #100] @ 0x64 801c4b8: 07dc lsls r4, r3, #31 801c4ba: d504 bpl.n 801c4c6 <_vfiprintf_r+0x4e> 801c4bc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801c4c0: b01c add sp, #112 @ 0x70 801c4c2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801c4c6: 89ab ldrh r3, [r5, #12] 801c4c8: 0598 lsls r0, r3, #22 801c4ca: d4f7 bmi.n 801c4bc <_vfiprintf_r+0x44> 801c4cc: 6da8 ldr r0, [r5, #88] @ 0x58 801c4ce: f7fd fb9f bl 8019c10 <__retarget_lock_release_recursive> 801c4d2: e7f3 b.n 801c4bc <_vfiprintf_r+0x44> 801c4d4: 2300 movs r3, #0 801c4d6: 9309 str r3, [sp, #36] @ 0x24 801c4d8: 2320 movs r3, #32 801c4da: f88d 3029 strb.w r3, [sp, #41] @ 0x29 801c4de: 9703 str r7, [sp, #12] 801c4e0: 2330 movs r3, #48 @ 0x30 801c4e2: 4f6a ldr r7, [pc, #424] @ (801c68c <_vfiprintf_r+0x214>) 801c4e4: f88d 302a strb.w r3, [sp, #42] @ 0x2a 801c4e8: f04f 0801 mov.w r8, #1 801c4ec: 4623 mov r3, r4 801c4ee: 4699 mov r9, r3 801c4f0: f813 2b01 ldrb.w r2, [r3], #1 801c4f4: b10a cbz r2, 801c4fa <_vfiprintf_r+0x82> 801c4f6: 2a25 cmp r2, #37 @ 0x25 801c4f8: d1f9 bne.n 801c4ee <_vfiprintf_r+0x76> 801c4fa: ebb9 0a04 subs.w sl, r9, r4 801c4fe: d00b beq.n 801c518 <_vfiprintf_r+0xa0> 801c500: 4653 mov r3, sl 801c502: 4622 mov r2, r4 801c504: 4629 mov r1, r5 801c506: 4630 mov r0, r6 801c508: f7ff ffa3 bl 801c452 <__sfputs_r> 801c50c: 3001 adds r0, #1 801c50e: f000 80a4 beq.w 801c65a <_vfiprintf_r+0x1e2> 801c512: 9a09 ldr r2, [sp, #36] @ 0x24 801c514: 4452 add r2, sl 801c516: 9209 str r2, [sp, #36] @ 0x24 801c518: f899 3000 ldrb.w r3, [r9] 801c51c: 2b00 cmp r3, #0 801c51e: f000 809c beq.w 801c65a <_vfiprintf_r+0x1e2> 801c522: 2300 movs r3, #0 801c524: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801c528: e9cd 2305 strd r2, r3, [sp, #20] 801c52c: f109 0901 add.w r9, r9, #1 801c530: 9304 str r3, [sp, #16] 801c532: 9307 str r3, [sp, #28] 801c534: f88d 3053 strb.w r3, [sp, #83] @ 0x53 801c538: 931a str r3, [sp, #104] @ 0x68 801c53a: 464c mov r4, r9 801c53c: 4853 ldr r0, [pc, #332] @ (801c68c <_vfiprintf_r+0x214>) 801c53e: f814 1b01 ldrb.w r1, [r4], #1 801c542: 2205 movs r2, #5 801c544: f7e3 fe1c bl 8000180 801c548: 9b04 ldr r3, [sp, #16] 801c54a: b9d0 cbnz r0, 801c582 <_vfiprintf_r+0x10a> 801c54c: 06d9 lsls r1, r3, #27 801c54e: bf44 itt mi 801c550: 2220 movmi r2, #32 801c552: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53 801c556: 071a lsls r2, r3, #28 801c558: bf44 itt mi 801c55a: 222b movmi r2, #43 @ 0x2b 801c55c: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53 801c560: f899 2000 ldrb.w r2, [r9] 801c564: 2a2a cmp r2, #42 @ 0x2a 801c566: d013 beq.n 801c590 <_vfiprintf_r+0x118> 801c568: 9a07 ldr r2, [sp, #28] 801c56a: 464c mov r4, r9 801c56c: 2000 movs r0, #0 801c56e: f04f 0c0a mov.w ip, #10 801c572: 4621 mov r1, r4 801c574: f811 3b01 ldrb.w r3, [r1], #1 801c578: 3b30 subs r3, #48 @ 0x30 801c57a: 2b09 cmp r3, #9 801c57c: d949 bls.n 801c612 <_vfiprintf_r+0x19a> 801c57e: b968 cbnz r0, 801c59c <_vfiprintf_r+0x124> 801c580: e013 b.n 801c5aa <_vfiprintf_r+0x132> 801c582: 1bc0 subs r0, r0, r7 801c584: fa08 f000 lsl.w r0, r8, r0 801c588: 4318 orrs r0, r3 801c58a: 9004 str r0, [sp, #16] 801c58c: 46a1 mov r9, r4 801c58e: e7d4 b.n 801c53a <_vfiprintf_r+0xc2> 801c590: 9a03 ldr r2, [sp, #12] 801c592: 1d11 adds r1, r2, #4 801c594: 6812 ldr r2, [r2, #0] 801c596: 9103 str r1, [sp, #12] 801c598: 2a00 cmp r2, #0 801c59a: db01 blt.n 801c5a0 <_vfiprintf_r+0x128> 801c59c: 9207 str r2, [sp, #28] 801c59e: e004 b.n 801c5aa <_vfiprintf_r+0x132> 801c5a0: 4252 negs r2, r2 801c5a2: f043 0302 orr.w r3, r3, #2 801c5a6: 9207 str r2, [sp, #28] 801c5a8: 9304 str r3, [sp, #16] 801c5aa: 7823 ldrb r3, [r4, #0] 801c5ac: 2b2e cmp r3, #46 @ 0x2e 801c5ae: d10a bne.n 801c5c6 <_vfiprintf_r+0x14e> 801c5b0: 7863 ldrb r3, [r4, #1] 801c5b2: 2b2a cmp r3, #42 @ 0x2a 801c5b4: d132 bne.n 801c61c <_vfiprintf_r+0x1a4> 801c5b6: 9b03 ldr r3, [sp, #12] 801c5b8: 1d1a adds r2, r3, #4 801c5ba: 681b ldr r3, [r3, #0] 801c5bc: 9203 str r2, [sp, #12] 801c5be: ea43 73e3 orr.w r3, r3, r3, asr #31 801c5c2: 3402 adds r4, #2 801c5c4: 9305 str r3, [sp, #20] 801c5c6: f8df 90d4 ldr.w r9, [pc, #212] @ 801c69c <_vfiprintf_r+0x224> 801c5ca: 7821 ldrb r1, [r4, #0] 801c5cc: 2203 movs r2, #3 801c5ce: 4648 mov r0, r9 801c5d0: f7e3 fdd6 bl 8000180 801c5d4: b138 cbz r0, 801c5e6 <_vfiprintf_r+0x16e> 801c5d6: 9b04 ldr r3, [sp, #16] 801c5d8: eba0 0009 sub.w r0, r0, r9 801c5dc: 2240 movs r2, #64 @ 0x40 801c5de: 4082 lsls r2, r0 801c5e0: 4313 orrs r3, r2 801c5e2: 3401 adds r4, #1 801c5e4: 9304 str r3, [sp, #16] 801c5e6: f814 1b01 ldrb.w r1, [r4], #1 801c5ea: 4829 ldr r0, [pc, #164] @ (801c690 <_vfiprintf_r+0x218>) 801c5ec: f88d 1028 strb.w r1, [sp, #40] @ 0x28 801c5f0: 2206 movs r2, #6 801c5f2: f7e3 fdc5 bl 8000180 801c5f6: 2800 cmp r0, #0 801c5f8: d03e beq.n 801c678 <_vfiprintf_r+0x200> 801c5fa: 4826 ldr r0, [pc, #152] @ (801c694 <_vfiprintf_r+0x21c>) 801c5fc: bb18 cbnz r0, 801c646 <_vfiprintf_r+0x1ce> 801c5fe: 9b03 ldr r3, [sp, #12] 801c600: 3307 adds r3, #7 801c602: f023 0307 bic.w r3, r3, #7 801c606: 3308 adds r3, #8 801c608: 9303 str r3, [sp, #12] 801c60a: 9b09 ldr r3, [sp, #36] @ 0x24 801c60c: 4403 add r3, r0 801c60e: 9309 str r3, [sp, #36] @ 0x24 801c610: e76c b.n 801c4ec <_vfiprintf_r+0x74> 801c612: fb0c 3202 mla r2, ip, r2, r3 801c616: 460c mov r4, r1 801c618: 2001 movs r0, #1 801c61a: e7aa b.n 801c572 <_vfiprintf_r+0xfa> 801c61c: 2300 movs r3, #0 801c61e: 3401 adds r4, #1 801c620: 9305 str r3, [sp, #20] 801c622: 4619 mov r1, r3 801c624: f04f 0c0a mov.w ip, #10 801c628: 4620 mov r0, r4 801c62a: f810 2b01 ldrb.w r2, [r0], #1 801c62e: 3a30 subs r2, #48 @ 0x30 801c630: 2a09 cmp r2, #9 801c632: d903 bls.n 801c63c <_vfiprintf_r+0x1c4> 801c634: 2b00 cmp r3, #0 801c636: d0c6 beq.n 801c5c6 <_vfiprintf_r+0x14e> 801c638: 9105 str r1, [sp, #20] 801c63a: e7c4 b.n 801c5c6 <_vfiprintf_r+0x14e> 801c63c: fb0c 2101 mla r1, ip, r1, r2 801c640: 4604 mov r4, r0 801c642: 2301 movs r3, #1 801c644: e7f0 b.n 801c628 <_vfiprintf_r+0x1b0> 801c646: ab03 add r3, sp, #12 801c648: 9300 str r3, [sp, #0] 801c64a: 462a mov r2, r5 801c64c: 4b12 ldr r3, [pc, #72] @ (801c698 <_vfiprintf_r+0x220>) 801c64e: a904 add r1, sp, #16 801c650: 4630 mov r0, r6 801c652: f7fc fa6b bl 8018b2c <_printf_float> 801c656: 1c43 adds r3, r0, #1 801c658: d1d7 bne.n 801c60a <_vfiprintf_r+0x192> 801c65a: 6e6b ldr r3, [r5, #100] @ 0x64 801c65c: 07d9 lsls r1, r3, #31 801c65e: d405 bmi.n 801c66c <_vfiprintf_r+0x1f4> 801c660: 89ab ldrh r3, [r5, #12] 801c662: 059a lsls r2, r3, #22 801c664: d402 bmi.n 801c66c <_vfiprintf_r+0x1f4> 801c666: 6da8 ldr r0, [r5, #88] @ 0x58 801c668: f7fd fad2 bl 8019c10 <__retarget_lock_release_recursive> 801c66c: 89ab ldrh r3, [r5, #12] 801c66e: 065b lsls r3, r3, #25 801c670: f53f af24 bmi.w 801c4bc <_vfiprintf_r+0x44> 801c674: 9809 ldr r0, [sp, #36] @ 0x24 801c676: e723 b.n 801c4c0 <_vfiprintf_r+0x48> 801c678: ab03 add r3, sp, #12 801c67a: 9300 str r3, [sp, #0] 801c67c: 462a mov r2, r5 801c67e: 4b06 ldr r3, [pc, #24] @ (801c698 <_vfiprintf_r+0x220>) 801c680: a904 add r1, sp, #16 801c682: 4630 mov r0, r6 801c684: f7fc fce8 bl 8019058 <_printf_i> 801c688: e7e5 b.n 801c656 <_vfiprintf_r+0x1de> 801c68a: bf00 nop 801c68c: 0801ddd1 .word 0x0801ddd1 801c690: 0801dddb .word 0x0801dddb 801c694: 08018b2d .word 0x08018b2d 801c698: 0801c453 .word 0x0801c453 801c69c: 0801ddd7 .word 0x0801ddd7 0801c6a0 <__sflush_r>: 801c6a0: f9b1 200c ldrsh.w r2, [r1, #12] 801c6a4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801c6a8: 0716 lsls r6, r2, #28 801c6aa: 4605 mov r5, r0 801c6ac: 460c mov r4, r1 801c6ae: d451 bmi.n 801c754 <__sflush_r+0xb4> 801c6b0: 684b ldr r3, [r1, #4] 801c6b2: 2b00 cmp r3, #0 801c6b4: dc02 bgt.n 801c6bc <__sflush_r+0x1c> 801c6b6: 6c0b ldr r3, [r1, #64] @ 0x40 801c6b8: 2b00 cmp r3, #0 801c6ba: dd49 ble.n 801c750 <__sflush_r+0xb0> 801c6bc: 6ae6 ldr r6, [r4, #44] @ 0x2c 801c6be: 2e00 cmp r6, #0 801c6c0: d046 beq.n 801c750 <__sflush_r+0xb0> 801c6c2: 2300 movs r3, #0 801c6c4: f412 5280 ands.w r2, r2, #4096 @ 0x1000 801c6c8: 682f ldr r7, [r5, #0] 801c6ca: 602b str r3, [r5, #0] 801c6cc: d031 beq.n 801c732 <__sflush_r+0x92> 801c6ce: 6d62 ldr r2, [r4, #84] @ 0x54 801c6d0: 89a3 ldrh r3, [r4, #12] 801c6d2: 0759 lsls r1, r3, #29 801c6d4: d505 bpl.n 801c6e2 <__sflush_r+0x42> 801c6d6: 6863 ldr r3, [r4, #4] 801c6d8: 1ad2 subs r2, r2, r3 801c6da: 6b63 ldr r3, [r4, #52] @ 0x34 801c6dc: b10b cbz r3, 801c6e2 <__sflush_r+0x42> 801c6de: 6c23 ldr r3, [r4, #64] @ 0x40 801c6e0: 1ad2 subs r2, r2, r3 801c6e2: 2300 movs r3, #0 801c6e4: 6ae6 ldr r6, [r4, #44] @ 0x2c 801c6e6: 6a21 ldr r1, [r4, #32] 801c6e8: 4628 mov r0, r5 801c6ea: 47b0 blx r6 801c6ec: 1c42 adds r2, r0, #1 801c6ee: f9b4 300c ldrsh.w r3, [r4, #12] 801c6f2: d106 bne.n 801c702 <__sflush_r+0x62> 801c6f4: 6829 ldr r1, [r5, #0] 801c6f6: 291d cmp r1, #29 801c6f8: d846 bhi.n 801c788 <__sflush_r+0xe8> 801c6fa: 4a29 ldr r2, [pc, #164] @ (801c7a0 <__sflush_r+0x100>) 801c6fc: 40ca lsrs r2, r1 801c6fe: 07d6 lsls r6, r2, #31 801c700: d542 bpl.n 801c788 <__sflush_r+0xe8> 801c702: 2200 movs r2, #0 801c704: 6062 str r2, [r4, #4] 801c706: 04d9 lsls r1, r3, #19 801c708: 6922 ldr r2, [r4, #16] 801c70a: 6022 str r2, [r4, #0] 801c70c: d504 bpl.n 801c718 <__sflush_r+0x78> 801c70e: 1c42 adds r2, r0, #1 801c710: d101 bne.n 801c716 <__sflush_r+0x76> 801c712: 682b ldr r3, [r5, #0] 801c714: b903 cbnz r3, 801c718 <__sflush_r+0x78> 801c716: 6560 str r0, [r4, #84] @ 0x54 801c718: 6b61 ldr r1, [r4, #52] @ 0x34 801c71a: 602f str r7, [r5, #0] 801c71c: b1c1 cbz r1, 801c750 <__sflush_r+0xb0> 801c71e: f104 0344 add.w r3, r4, #68 @ 0x44 801c722: 4299 cmp r1, r3 801c724: d002 beq.n 801c72c <__sflush_r+0x8c> 801c726: 4628 mov r0, r5 801c728: f7fe f8ee bl 801a908 <_free_r> 801c72c: 2300 movs r3, #0 801c72e: 6363 str r3, [r4, #52] @ 0x34 801c730: e00e b.n 801c750 <__sflush_r+0xb0> 801c732: 6a21 ldr r1, [r4, #32] 801c734: 2301 movs r3, #1 801c736: 4628 mov r0, r5 801c738: 47b0 blx r6 801c73a: 4602 mov r2, r0 801c73c: 1c50 adds r0, r2, #1 801c73e: d1c7 bne.n 801c6d0 <__sflush_r+0x30> 801c740: 682b ldr r3, [r5, #0] 801c742: 2b00 cmp r3, #0 801c744: d0c4 beq.n 801c6d0 <__sflush_r+0x30> 801c746: 2b1d cmp r3, #29 801c748: d001 beq.n 801c74e <__sflush_r+0xae> 801c74a: 2b16 cmp r3, #22 801c74c: d11a bne.n 801c784 <__sflush_r+0xe4> 801c74e: 602f str r7, [r5, #0] 801c750: 2000 movs r0, #0 801c752: e01e b.n 801c792 <__sflush_r+0xf2> 801c754: 690f ldr r7, [r1, #16] 801c756: 2f00 cmp r7, #0 801c758: d0fa beq.n 801c750 <__sflush_r+0xb0> 801c75a: 0793 lsls r3, r2, #30 801c75c: 680e ldr r6, [r1, #0] 801c75e: bf08 it eq 801c760: 694b ldreq r3, [r1, #20] 801c762: 600f str r7, [r1, #0] 801c764: bf18 it ne 801c766: 2300 movne r3, #0 801c768: eba6 0807 sub.w r8, r6, r7 801c76c: 608b str r3, [r1, #8] 801c76e: f1b8 0f00 cmp.w r8, #0 801c772: dded ble.n 801c750 <__sflush_r+0xb0> 801c774: 6a21 ldr r1, [r4, #32] 801c776: 6aa6 ldr r6, [r4, #40] @ 0x28 801c778: 4643 mov r3, r8 801c77a: 463a mov r2, r7 801c77c: 4628 mov r0, r5 801c77e: 47b0 blx r6 801c780: 2800 cmp r0, #0 801c782: dc08 bgt.n 801c796 <__sflush_r+0xf6> 801c784: f9b4 300c ldrsh.w r3, [r4, #12] 801c788: f043 0340 orr.w r3, r3, #64 @ 0x40 801c78c: 81a3 strh r3, [r4, #12] 801c78e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801c792: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801c796: 4407 add r7, r0 801c798: eba8 0800 sub.w r8, r8, r0 801c79c: e7e7 b.n 801c76e <__sflush_r+0xce> 801c79e: bf00 nop 801c7a0: 20400001 .word 0x20400001 0801c7a4 <_fflush_r>: 801c7a4: b538 push {r3, r4, r5, lr} 801c7a6: 690b ldr r3, [r1, #16] 801c7a8: 4605 mov r5, r0 801c7aa: 460c mov r4, r1 801c7ac: b913 cbnz r3, 801c7b4 <_fflush_r+0x10> 801c7ae: 2500 movs r5, #0 801c7b0: 4628 mov r0, r5 801c7b2: bd38 pop {r3, r4, r5, pc} 801c7b4: b118 cbz r0, 801c7be <_fflush_r+0x1a> 801c7b6: 6a03 ldr r3, [r0, #32] 801c7b8: b90b cbnz r3, 801c7be <_fflush_r+0x1a> 801c7ba: f7fd f80d bl 80197d8 <__sinit> 801c7be: f9b4 300c ldrsh.w r3, [r4, #12] 801c7c2: 2b00 cmp r3, #0 801c7c4: d0f3 beq.n 801c7ae <_fflush_r+0xa> 801c7c6: 6e62 ldr r2, [r4, #100] @ 0x64 801c7c8: 07d0 lsls r0, r2, #31 801c7ca: d404 bmi.n 801c7d6 <_fflush_r+0x32> 801c7cc: 0599 lsls r1, r3, #22 801c7ce: d402 bmi.n 801c7d6 <_fflush_r+0x32> 801c7d0: 6da0 ldr r0, [r4, #88] @ 0x58 801c7d2: f7fd fa1c bl 8019c0e <__retarget_lock_acquire_recursive> 801c7d6: 4628 mov r0, r5 801c7d8: 4621 mov r1, r4 801c7da: f7ff ff61 bl 801c6a0 <__sflush_r> 801c7de: 6e63 ldr r3, [r4, #100] @ 0x64 801c7e0: 07da lsls r2, r3, #31 801c7e2: 4605 mov r5, r0 801c7e4: d4e4 bmi.n 801c7b0 <_fflush_r+0xc> 801c7e6: 89a3 ldrh r3, [r4, #12] 801c7e8: 059b lsls r3, r3, #22 801c7ea: d4e1 bmi.n 801c7b0 <_fflush_r+0xc> 801c7ec: 6da0 ldr r0, [r4, #88] @ 0x58 801c7ee: f7fd fa0f bl 8019c10 <__retarget_lock_release_recursive> 801c7f2: e7dd b.n 801c7b0 <_fflush_r+0xc> 0801c7f4 <__swhatbuf_r>: 801c7f4: b570 push {r4, r5, r6, lr} 801c7f6: 460c mov r4, r1 801c7f8: f9b1 100e ldrsh.w r1, [r1, #14] 801c7fc: 2900 cmp r1, #0 801c7fe: b096 sub sp, #88 @ 0x58 801c800: 4615 mov r5, r2 801c802: 461e mov r6, r3 801c804: da0a bge.n 801c81c <__swhatbuf_r+0x28> 801c806: 89a1 ldrh r1, [r4, #12] 801c808: f011 0180 ands.w r1, r1, #128 @ 0x80 801c80c: d113 bne.n 801c836 <__swhatbuf_r+0x42> 801c80e: f44f 6280 mov.w r2, #1024 @ 0x400 801c812: 2000 movs r0, #0 801c814: 6031 str r1, [r6, #0] 801c816: 602a str r2, [r5, #0] 801c818: b016 add sp, #88 @ 0x58 801c81a: bd70 pop {r4, r5, r6, pc} 801c81c: 466a mov r2, sp 801c81e: f000 f871 bl 801c904 <_fstat_r> 801c822: 2800 cmp r0, #0 801c824: dbef blt.n 801c806 <__swhatbuf_r+0x12> 801c826: 9901 ldr r1, [sp, #4] 801c828: f401 4170 and.w r1, r1, #61440 @ 0xf000 801c82c: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 801c830: 4259 negs r1, r3 801c832: 4159 adcs r1, r3 801c834: e7eb b.n 801c80e <__swhatbuf_r+0x1a> 801c836: 2100 movs r1, #0 801c838: 2240 movs r2, #64 @ 0x40 801c83a: e7ea b.n 801c812 <__swhatbuf_r+0x1e> 0801c83c <__smakebuf_r>: 801c83c: 898b ldrh r3, [r1, #12] 801c83e: b573 push {r0, r1, r4, r5, r6, lr} 801c840: 079e lsls r6, r3, #30 801c842: 4605 mov r5, r0 801c844: 460c mov r4, r1 801c846: d507 bpl.n 801c858 <__smakebuf_r+0x1c> 801c848: f104 0347 add.w r3, r4, #71 @ 0x47 801c84c: 6023 str r3, [r4, #0] 801c84e: 6123 str r3, [r4, #16] 801c850: 2301 movs r3, #1 801c852: 6163 str r3, [r4, #20] 801c854: b002 add sp, #8 801c856: bd70 pop {r4, r5, r6, pc} 801c858: ab01 add r3, sp, #4 801c85a: 466a mov r2, sp 801c85c: f7ff ffca bl 801c7f4 <__swhatbuf_r> 801c860: 9e00 ldr r6, [sp, #0] 801c862: 4628 mov r0, r5 801c864: 4631 mov r1, r6 801c866: f7fe f8c3 bl 801a9f0 <_malloc_r> 801c86a: f9b4 300c ldrsh.w r3, [r4, #12] 801c86e: b938 cbnz r0, 801c880 <__smakebuf_r+0x44> 801c870: 059a lsls r2, r3, #22 801c872: d4ef bmi.n 801c854 <__smakebuf_r+0x18> 801c874: f023 0303 bic.w r3, r3, #3 801c878: f043 0302 orr.w r3, r3, #2 801c87c: 81a3 strh r3, [r4, #12] 801c87e: e7e3 b.n 801c848 <__smakebuf_r+0xc> 801c880: f043 0380 orr.w r3, r3, #128 @ 0x80 801c884: 81a3 strh r3, [r4, #12] 801c886: 9b01 ldr r3, [sp, #4] 801c888: 6020 str r0, [r4, #0] 801c88a: e9c4 0604 strd r0, r6, [r4, #16] 801c88e: 2b00 cmp r3, #0 801c890: d0e0 beq.n 801c854 <__smakebuf_r+0x18> 801c892: f9b4 100e ldrsh.w r1, [r4, #14] 801c896: 4628 mov r0, r5 801c898: f000 f846 bl 801c928 <_isatty_r> 801c89c: 2800 cmp r0, #0 801c89e: d0d9 beq.n 801c854 <__smakebuf_r+0x18> 801c8a0: 89a3 ldrh r3, [r4, #12] 801c8a2: f023 0303 bic.w r3, r3, #3 801c8a6: f043 0301 orr.w r3, r3, #1 801c8aa: 81a3 strh r3, [r4, #12] 801c8ac: e7d2 b.n 801c854 <__smakebuf_r+0x18> 0801c8ae : 801c8ae: 4288 cmp r0, r1 801c8b0: b510 push {r4, lr} 801c8b2: eb01 0402 add.w r4, r1, r2 801c8b6: d902 bls.n 801c8be 801c8b8: 4284 cmp r4, r0 801c8ba: 4623 mov r3, r4 801c8bc: d807 bhi.n 801c8ce 801c8be: 1e43 subs r3, r0, #1 801c8c0: 42a1 cmp r1, r4 801c8c2: d007 beq.n 801c8d4 801c8c4: f811 2b01 ldrb.w r2, [r1], #1 801c8c8: f803 2f01 strb.w r2, [r3, #1]! 801c8cc: e7f8 b.n 801c8c0 801c8ce: 4402 add r2, r0 801c8d0: 4282 cmp r2, r0 801c8d2: d100 bne.n 801c8d6 801c8d4: bd10 pop {r4, pc} 801c8d6: f813 1d01 ldrb.w r1, [r3, #-1]! 801c8da: f802 1d01 strb.w r1, [r2, #-1]! 801c8de: e7f7 b.n 801c8d0 0801c8e0 : 801c8e0: b510 push {r4, lr} 801c8e2: b16a cbz r2, 801c900 801c8e4: 3901 subs r1, #1 801c8e6: 1884 adds r4, r0, r2 801c8e8: f810 2b01 ldrb.w r2, [r0], #1 801c8ec: f811 3f01 ldrb.w r3, [r1, #1]! 801c8f0: 429a cmp r2, r3 801c8f2: d103 bne.n 801c8fc 801c8f4: 42a0 cmp r0, r4 801c8f6: d001 beq.n 801c8fc 801c8f8: 2a00 cmp r2, #0 801c8fa: d1f5 bne.n 801c8e8 801c8fc: 1ad0 subs r0, r2, r3 801c8fe: bd10 pop {r4, pc} 801c900: 4610 mov r0, r2 801c902: e7fc b.n 801c8fe 0801c904 <_fstat_r>: 801c904: b538 push {r3, r4, r5, lr} 801c906: 4d07 ldr r5, [pc, #28] @ (801c924 <_fstat_r+0x20>) 801c908: 2300 movs r3, #0 801c90a: 4604 mov r4, r0 801c90c: 4608 mov r0, r1 801c90e: 4611 mov r1, r2 801c910: 602b str r3, [r5, #0] 801c912: f7e9 fc8f bl 8006234 <_fstat> 801c916: 1c43 adds r3, r0, #1 801c918: d102 bne.n 801c920 <_fstat_r+0x1c> 801c91a: 682b ldr r3, [r5, #0] 801c91c: b103 cbz r3, 801c920 <_fstat_r+0x1c> 801c91e: 6023 str r3, [r4, #0] 801c920: bd38 pop {r3, r4, r5, pc} 801c922: bf00 nop 801c924: 20013c38 .word 0x20013c38 0801c928 <_isatty_r>: 801c928: b538 push {r3, r4, r5, lr} 801c92a: 4d06 ldr r5, [pc, #24] @ (801c944 <_isatty_r+0x1c>) 801c92c: 2300 movs r3, #0 801c92e: 4604 mov r4, r0 801c930: 4608 mov r0, r1 801c932: 602b str r3, [r5, #0] 801c934: f7e9 fc8e bl 8006254 <_isatty> 801c938: 1c43 adds r3, r0, #1 801c93a: d102 bne.n 801c942 <_isatty_r+0x1a> 801c93c: 682b ldr r3, [r5, #0] 801c93e: b103 cbz r3, 801c942 <_isatty_r+0x1a> 801c940: 6023 str r3, [r4, #0] 801c942: bd38 pop {r3, r4, r5, pc} 801c944: 20013c38 .word 0x20013c38 0801c948 <_sbrk_r>: 801c948: b538 push {r3, r4, r5, lr} 801c94a: 4d06 ldr r5, [pc, #24] @ (801c964 <_sbrk_r+0x1c>) 801c94c: 2300 movs r3, #0 801c94e: 4604 mov r4, r0 801c950: 4608 mov r0, r1 801c952: 602b str r3, [r5, #0] 801c954: f7e9 fc96 bl 8006284 <_sbrk> 801c958: 1c43 adds r3, r0, #1 801c95a: d102 bne.n 801c962 <_sbrk_r+0x1a> 801c95c: 682b ldr r3, [r5, #0] 801c95e: b103 cbz r3, 801c962 <_sbrk_r+0x1a> 801c960: 6023 str r3, [r4, #0] 801c962: bd38 pop {r3, r4, r5, pc} 801c964: 20013c38 .word 0x20013c38 0801c968 : 801c968: ed9f 0b01 vldr d0, [pc, #4] @ 801c970 801c96c: 4770 bx lr 801c96e: bf00 nop 801c970: 00000000 .word 0x00000000 801c974: 7ff80000 .word 0x7ff80000 0801c978 <__assert_func>: 801c978: b51f push {r0, r1, r2, r3, r4, lr} 801c97a: 4614 mov r4, r2 801c97c: 461a mov r2, r3 801c97e: 4b09 ldr r3, [pc, #36] @ (801c9a4 <__assert_func+0x2c>) 801c980: 681b ldr r3, [r3, #0] 801c982: 4605 mov r5, r0 801c984: 68d8 ldr r0, [r3, #12] 801c986: b14c cbz r4, 801c99c <__assert_func+0x24> 801c988: 4b07 ldr r3, [pc, #28] @ (801c9a8 <__assert_func+0x30>) 801c98a: 9100 str r1, [sp, #0] 801c98c: e9cd 3401 strd r3, r4, [sp, #4] 801c990: 4906 ldr r1, [pc, #24] @ (801c9ac <__assert_func+0x34>) 801c992: 462b mov r3, r5 801c994: f000 fbaa bl 801d0ec 801c998: f000 fbba bl 801d110 801c99c: 4b04 ldr r3, [pc, #16] @ (801c9b0 <__assert_func+0x38>) 801c99e: 461c mov r4, r3 801c9a0: e7f3 b.n 801c98a <__assert_func+0x12> 801c9a2: bf00 nop 801c9a4: 2000011c .word 0x2000011c 801c9a8: 0801ddea .word 0x0801ddea 801c9ac: 0801ddf7 .word 0x0801ddf7 801c9b0: 0801de25 .word 0x0801de25 0801c9b4 <_calloc_r>: 801c9b4: b570 push {r4, r5, r6, lr} 801c9b6: fba1 5402 umull r5, r4, r1, r2 801c9ba: b934 cbnz r4, 801c9ca <_calloc_r+0x16> 801c9bc: 4629 mov r1, r5 801c9be: f7fe f817 bl 801a9f0 <_malloc_r> 801c9c2: 4606 mov r6, r0 801c9c4: b928 cbnz r0, 801c9d2 <_calloc_r+0x1e> 801c9c6: 4630 mov r0, r6 801c9c8: bd70 pop {r4, r5, r6, pc} 801c9ca: 220c movs r2, #12 801c9cc: 6002 str r2, [r0, #0] 801c9ce: 2600 movs r6, #0 801c9d0: e7f9 b.n 801c9c6 <_calloc_r+0x12> 801c9d2: 462a mov r2, r5 801c9d4: 4621 mov r1, r4 801c9d6: f7fd f89d bl 8019b14 801c9da: e7f4 b.n 801c9c6 <_calloc_r+0x12> 0801c9dc : 801c9dc: 6903 ldr r3, [r0, #16] 801c9de: ebb3 1f61 cmp.w r3, r1, asr #5 801c9e2: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 801c9e6: ea4f 1261 mov.w r2, r1, asr #5 801c9ea: f100 0414 add.w r4, r0, #20 801c9ee: dd45 ble.n 801ca7c 801c9f0: f011 011f ands.w r1, r1, #31 801c9f4: eb04 0683 add.w r6, r4, r3, lsl #2 801c9f8: eb04 0582 add.w r5, r4, r2, lsl #2 801c9fc: d10c bne.n 801ca18 801c9fe: f100 0710 add.w r7, r0, #16 801ca02: 4629 mov r1, r5 801ca04: 42b1 cmp r1, r6 801ca06: d334 bcc.n 801ca72 801ca08: 1a9b subs r3, r3, r2 801ca0a: 009b lsls r3, r3, #2 801ca0c: 1eea subs r2, r5, #3 801ca0e: 4296 cmp r6, r2 801ca10: bf38 it cc 801ca12: 2300 movcc r3, #0 801ca14: 4423 add r3, r4 801ca16: e015 b.n 801ca44 801ca18: f854 7022 ldr.w r7, [r4, r2, lsl #2] 801ca1c: f1c1 0820 rsb r8, r1, #32 801ca20: 40cf lsrs r7, r1 801ca22: f105 0e04 add.w lr, r5, #4 801ca26: 46a1 mov r9, r4 801ca28: 4576 cmp r6, lr 801ca2a: 46f4 mov ip, lr 801ca2c: d815 bhi.n 801ca5a 801ca2e: 1a9a subs r2, r3, r2 801ca30: 0092 lsls r2, r2, #2 801ca32: 3a04 subs r2, #4 801ca34: 3501 adds r5, #1 801ca36: 42ae cmp r6, r5 801ca38: bf38 it cc 801ca3a: 2200 movcc r2, #0 801ca3c: 18a3 adds r3, r4, r2 801ca3e: 50a7 str r7, [r4, r2] 801ca40: b107 cbz r7, 801ca44 801ca42: 3304 adds r3, #4 801ca44: 1b1a subs r2, r3, r4 801ca46: 42a3 cmp r3, r4 801ca48: ea4f 02a2 mov.w r2, r2, asr #2 801ca4c: bf08 it eq 801ca4e: 2300 moveq r3, #0 801ca50: 6102 str r2, [r0, #16] 801ca52: bf08 it eq 801ca54: 6143 streq r3, [r0, #20] 801ca56: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 801ca5a: f8dc c000 ldr.w ip, [ip] 801ca5e: fa0c fc08 lsl.w ip, ip, r8 801ca62: ea4c 0707 orr.w r7, ip, r7 801ca66: f849 7b04 str.w r7, [r9], #4 801ca6a: f85e 7b04 ldr.w r7, [lr], #4 801ca6e: 40cf lsrs r7, r1 801ca70: e7da b.n 801ca28 801ca72: f851 cb04 ldr.w ip, [r1], #4 801ca76: f847 cf04 str.w ip, [r7, #4]! 801ca7a: e7c3 b.n 801ca04 801ca7c: 4623 mov r3, r4 801ca7e: e7e1 b.n 801ca44 0801ca80 <__hexdig_fun>: 801ca80: f1a0 0330 sub.w r3, r0, #48 @ 0x30 801ca84: 2b09 cmp r3, #9 801ca86: d802 bhi.n 801ca8e <__hexdig_fun+0xe> 801ca88: 3820 subs r0, #32 801ca8a: b2c0 uxtb r0, r0 801ca8c: 4770 bx lr 801ca8e: f1a0 0361 sub.w r3, r0, #97 @ 0x61 801ca92: 2b05 cmp r3, #5 801ca94: d801 bhi.n 801ca9a <__hexdig_fun+0x1a> 801ca96: 3847 subs r0, #71 @ 0x47 801ca98: e7f7 b.n 801ca8a <__hexdig_fun+0xa> 801ca9a: f1a0 0341 sub.w r3, r0, #65 @ 0x41 801ca9e: 2b05 cmp r3, #5 801caa0: d801 bhi.n 801caa6 <__hexdig_fun+0x26> 801caa2: 3827 subs r0, #39 @ 0x27 801caa4: e7f1 b.n 801ca8a <__hexdig_fun+0xa> 801caa6: 2000 movs r0, #0 801caa8: 4770 bx lr ... 0801caac <__gethex>: 801caac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801cab0: b085 sub sp, #20 801cab2: 468a mov sl, r1 801cab4: 9302 str r3, [sp, #8] 801cab6: 680b ldr r3, [r1, #0] 801cab8: 9001 str r0, [sp, #4] 801caba: 4690 mov r8, r2 801cabc: 1c9c adds r4, r3, #2 801cabe: 46a1 mov r9, r4 801cac0: f814 0b01 ldrb.w r0, [r4], #1 801cac4: 2830 cmp r0, #48 @ 0x30 801cac6: d0fa beq.n 801cabe <__gethex+0x12> 801cac8: eba9 0303 sub.w r3, r9, r3 801cacc: f1a3 0b02 sub.w fp, r3, #2 801cad0: f7ff ffd6 bl 801ca80 <__hexdig_fun> 801cad4: 4605 mov r5, r0 801cad6: 2800 cmp r0, #0 801cad8: d168 bne.n 801cbac <__gethex+0x100> 801cada: 49a0 ldr r1, [pc, #640] @ (801cd5c <__gethex+0x2b0>) 801cadc: 2201 movs r2, #1 801cade: 4648 mov r0, r9 801cae0: f7ff fefe bl 801c8e0 801cae4: 4607 mov r7, r0 801cae6: 2800 cmp r0, #0 801cae8: d167 bne.n 801cbba <__gethex+0x10e> 801caea: f899 0001 ldrb.w r0, [r9, #1] 801caee: 4626 mov r6, r4 801caf0: f7ff ffc6 bl 801ca80 <__hexdig_fun> 801caf4: 2800 cmp r0, #0 801caf6: d062 beq.n 801cbbe <__gethex+0x112> 801caf8: 4623 mov r3, r4 801cafa: 7818 ldrb r0, [r3, #0] 801cafc: 2830 cmp r0, #48 @ 0x30 801cafe: 4699 mov r9, r3 801cb00: f103 0301 add.w r3, r3, #1 801cb04: d0f9 beq.n 801cafa <__gethex+0x4e> 801cb06: f7ff ffbb bl 801ca80 <__hexdig_fun> 801cb0a: fab0 f580 clz r5, r0 801cb0e: 096d lsrs r5, r5, #5 801cb10: f04f 0b01 mov.w fp, #1 801cb14: 464a mov r2, r9 801cb16: 4616 mov r6, r2 801cb18: 3201 adds r2, #1 801cb1a: 7830 ldrb r0, [r6, #0] 801cb1c: f7ff ffb0 bl 801ca80 <__hexdig_fun> 801cb20: 2800 cmp r0, #0 801cb22: d1f8 bne.n 801cb16 <__gethex+0x6a> 801cb24: 498d ldr r1, [pc, #564] @ (801cd5c <__gethex+0x2b0>) 801cb26: 2201 movs r2, #1 801cb28: 4630 mov r0, r6 801cb2a: f7ff fed9 bl 801c8e0 801cb2e: 2800 cmp r0, #0 801cb30: d13f bne.n 801cbb2 <__gethex+0x106> 801cb32: b944 cbnz r4, 801cb46 <__gethex+0x9a> 801cb34: 1c74 adds r4, r6, #1 801cb36: 4622 mov r2, r4 801cb38: 4616 mov r6, r2 801cb3a: 3201 adds r2, #1 801cb3c: 7830 ldrb r0, [r6, #0] 801cb3e: f7ff ff9f bl 801ca80 <__hexdig_fun> 801cb42: 2800 cmp r0, #0 801cb44: d1f8 bne.n 801cb38 <__gethex+0x8c> 801cb46: 1ba4 subs r4, r4, r6 801cb48: 00a7 lsls r7, r4, #2 801cb4a: 7833 ldrb r3, [r6, #0] 801cb4c: f003 03df and.w r3, r3, #223 @ 0xdf 801cb50: 2b50 cmp r3, #80 @ 0x50 801cb52: d13e bne.n 801cbd2 <__gethex+0x126> 801cb54: 7873 ldrb r3, [r6, #1] 801cb56: 2b2b cmp r3, #43 @ 0x2b 801cb58: d033 beq.n 801cbc2 <__gethex+0x116> 801cb5a: 2b2d cmp r3, #45 @ 0x2d 801cb5c: d034 beq.n 801cbc8 <__gethex+0x11c> 801cb5e: 1c71 adds r1, r6, #1 801cb60: 2400 movs r4, #0 801cb62: 7808 ldrb r0, [r1, #0] 801cb64: f7ff ff8c bl 801ca80 <__hexdig_fun> 801cb68: 1e43 subs r3, r0, #1 801cb6a: b2db uxtb r3, r3 801cb6c: 2b18 cmp r3, #24 801cb6e: d830 bhi.n 801cbd2 <__gethex+0x126> 801cb70: f1a0 0210 sub.w r2, r0, #16 801cb74: f811 0f01 ldrb.w r0, [r1, #1]! 801cb78: f7ff ff82 bl 801ca80 <__hexdig_fun> 801cb7c: f100 3cff add.w ip, r0, #4294967295 @ 0xffffffff 801cb80: fa5f fc8c uxtb.w ip, ip 801cb84: f1bc 0f18 cmp.w ip, #24 801cb88: f04f 030a mov.w r3, #10 801cb8c: d91e bls.n 801cbcc <__gethex+0x120> 801cb8e: b104 cbz r4, 801cb92 <__gethex+0xe6> 801cb90: 4252 negs r2, r2 801cb92: 4417 add r7, r2 801cb94: f8ca 1000 str.w r1, [sl] 801cb98: b1ed cbz r5, 801cbd6 <__gethex+0x12a> 801cb9a: f1bb 0f00 cmp.w fp, #0 801cb9e: bf0c ite eq 801cba0: 2506 moveq r5, #6 801cba2: 2500 movne r5, #0 801cba4: 4628 mov r0, r5 801cba6: b005 add sp, #20 801cba8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801cbac: 2500 movs r5, #0 801cbae: 462c mov r4, r5 801cbb0: e7b0 b.n 801cb14 <__gethex+0x68> 801cbb2: 2c00 cmp r4, #0 801cbb4: d1c7 bne.n 801cb46 <__gethex+0x9a> 801cbb6: 4627 mov r7, r4 801cbb8: e7c7 b.n 801cb4a <__gethex+0x9e> 801cbba: 464e mov r6, r9 801cbbc: 462f mov r7, r5 801cbbe: 2501 movs r5, #1 801cbc0: e7c3 b.n 801cb4a <__gethex+0x9e> 801cbc2: 2400 movs r4, #0 801cbc4: 1cb1 adds r1, r6, #2 801cbc6: e7cc b.n 801cb62 <__gethex+0xb6> 801cbc8: 2401 movs r4, #1 801cbca: e7fb b.n 801cbc4 <__gethex+0x118> 801cbcc: fb03 0002 mla r0, r3, r2, r0 801cbd0: e7ce b.n 801cb70 <__gethex+0xc4> 801cbd2: 4631 mov r1, r6 801cbd4: e7de b.n 801cb94 <__gethex+0xe8> 801cbd6: eba6 0309 sub.w r3, r6, r9 801cbda: 3b01 subs r3, #1 801cbdc: 4629 mov r1, r5 801cbde: 2b07 cmp r3, #7 801cbe0: dc0a bgt.n 801cbf8 <__gethex+0x14c> 801cbe2: 9801 ldr r0, [sp, #4] 801cbe4: f7fd ff90 bl 801ab08 <_Balloc> 801cbe8: 4604 mov r4, r0 801cbea: b940 cbnz r0, 801cbfe <__gethex+0x152> 801cbec: 4b5c ldr r3, [pc, #368] @ (801cd60 <__gethex+0x2b4>) 801cbee: 4602 mov r2, r0 801cbf0: 21e4 movs r1, #228 @ 0xe4 801cbf2: 485c ldr r0, [pc, #368] @ (801cd64 <__gethex+0x2b8>) 801cbf4: f7ff fec0 bl 801c978 <__assert_func> 801cbf8: 3101 adds r1, #1 801cbfa: 105b asrs r3, r3, #1 801cbfc: e7ef b.n 801cbde <__gethex+0x132> 801cbfe: f100 0a14 add.w sl, r0, #20 801cc02: 2300 movs r3, #0 801cc04: 4655 mov r5, sl 801cc06: 469b mov fp, r3 801cc08: 45b1 cmp r9, r6 801cc0a: d337 bcc.n 801cc7c <__gethex+0x1d0> 801cc0c: f845 bb04 str.w fp, [r5], #4 801cc10: eba5 050a sub.w r5, r5, sl 801cc14: 10ad asrs r5, r5, #2 801cc16: 6125 str r5, [r4, #16] 801cc18: 4658 mov r0, fp 801cc1a: f7fe f865 bl 801ace8 <__hi0bits> 801cc1e: 016d lsls r5, r5, #5 801cc20: f8d8 6000 ldr.w r6, [r8] 801cc24: 1a2d subs r5, r5, r0 801cc26: 42b5 cmp r5, r6 801cc28: dd54 ble.n 801ccd4 <__gethex+0x228> 801cc2a: 1bad subs r5, r5, r6 801cc2c: 4629 mov r1, r5 801cc2e: 4620 mov r0, r4 801cc30: f7fe fc01 bl 801b436 <__any_on> 801cc34: 4681 mov r9, r0 801cc36: b178 cbz r0, 801cc58 <__gethex+0x1ac> 801cc38: 1e6b subs r3, r5, #1 801cc3a: 1159 asrs r1, r3, #5 801cc3c: f003 021f and.w r2, r3, #31 801cc40: f85a 1021 ldr.w r1, [sl, r1, lsl #2] 801cc44: f04f 0901 mov.w r9, #1 801cc48: fa09 f202 lsl.w r2, r9, r2 801cc4c: 420a tst r2, r1 801cc4e: d003 beq.n 801cc58 <__gethex+0x1ac> 801cc50: 454b cmp r3, r9 801cc52: dc36 bgt.n 801ccc2 <__gethex+0x216> 801cc54: f04f 0902 mov.w r9, #2 801cc58: 4629 mov r1, r5 801cc5a: 4620 mov r0, r4 801cc5c: f7ff febe bl 801c9dc 801cc60: 442f add r7, r5 801cc62: f8d8 3008 ldr.w r3, [r8, #8] 801cc66: 42bb cmp r3, r7 801cc68: da42 bge.n 801ccf0 <__gethex+0x244> 801cc6a: 9801 ldr r0, [sp, #4] 801cc6c: 4621 mov r1, r4 801cc6e: f7fd ff89 bl 801ab84 <_Bfree> 801cc72: 9a0e ldr r2, [sp, #56] @ 0x38 801cc74: 2300 movs r3, #0 801cc76: 6013 str r3, [r2, #0] 801cc78: 25a3 movs r5, #163 @ 0xa3 801cc7a: e793 b.n 801cba4 <__gethex+0xf8> 801cc7c: f816 2d01 ldrb.w r2, [r6, #-1]! 801cc80: 2a2e cmp r2, #46 @ 0x2e 801cc82: d012 beq.n 801ccaa <__gethex+0x1fe> 801cc84: 2b20 cmp r3, #32 801cc86: d104 bne.n 801cc92 <__gethex+0x1e6> 801cc88: f845 bb04 str.w fp, [r5], #4 801cc8c: f04f 0b00 mov.w fp, #0 801cc90: 465b mov r3, fp 801cc92: 7830 ldrb r0, [r6, #0] 801cc94: 9303 str r3, [sp, #12] 801cc96: f7ff fef3 bl 801ca80 <__hexdig_fun> 801cc9a: 9b03 ldr r3, [sp, #12] 801cc9c: f000 000f and.w r0, r0, #15 801cca0: 4098 lsls r0, r3 801cca2: ea4b 0b00 orr.w fp, fp, r0 801cca6: 3304 adds r3, #4 801cca8: e7ae b.n 801cc08 <__gethex+0x15c> 801ccaa: 45b1 cmp r9, r6 801ccac: d8ea bhi.n 801cc84 <__gethex+0x1d8> 801ccae: 492b ldr r1, [pc, #172] @ (801cd5c <__gethex+0x2b0>) 801ccb0: 9303 str r3, [sp, #12] 801ccb2: 2201 movs r2, #1 801ccb4: 4630 mov r0, r6 801ccb6: f7ff fe13 bl 801c8e0 801ccba: 9b03 ldr r3, [sp, #12] 801ccbc: 2800 cmp r0, #0 801ccbe: d1e1 bne.n 801cc84 <__gethex+0x1d8> 801ccc0: e7a2 b.n 801cc08 <__gethex+0x15c> 801ccc2: 1ea9 subs r1, r5, #2 801ccc4: 4620 mov r0, r4 801ccc6: f7fe fbb6 bl 801b436 <__any_on> 801ccca: 2800 cmp r0, #0 801cccc: d0c2 beq.n 801cc54 <__gethex+0x1a8> 801ccce: f04f 0903 mov.w r9, #3 801ccd2: e7c1 b.n 801cc58 <__gethex+0x1ac> 801ccd4: da09 bge.n 801ccea <__gethex+0x23e> 801ccd6: 1b75 subs r5, r6, r5 801ccd8: 4621 mov r1, r4 801ccda: 9801 ldr r0, [sp, #4] 801ccdc: 462a mov r2, r5 801ccde: f7fe f96b bl 801afb8 <__lshift> 801cce2: 1b7f subs r7, r7, r5 801cce4: 4604 mov r4, r0 801cce6: f100 0a14 add.w sl, r0, #20 801ccea: f04f 0900 mov.w r9, #0 801ccee: e7b8 b.n 801cc62 <__gethex+0x1b6> 801ccf0: f8d8 5004 ldr.w r5, [r8, #4] 801ccf4: 42bd cmp r5, r7 801ccf6: dd6f ble.n 801cdd8 <__gethex+0x32c> 801ccf8: 1bed subs r5, r5, r7 801ccfa: 42ae cmp r6, r5 801ccfc: dc34 bgt.n 801cd68 <__gethex+0x2bc> 801ccfe: f8d8 300c ldr.w r3, [r8, #12] 801cd02: 2b02 cmp r3, #2 801cd04: d022 beq.n 801cd4c <__gethex+0x2a0> 801cd06: 2b03 cmp r3, #3 801cd08: d024 beq.n 801cd54 <__gethex+0x2a8> 801cd0a: 2b01 cmp r3, #1 801cd0c: d115 bne.n 801cd3a <__gethex+0x28e> 801cd0e: 42ae cmp r6, r5 801cd10: d113 bne.n 801cd3a <__gethex+0x28e> 801cd12: 2e01 cmp r6, #1 801cd14: d10b bne.n 801cd2e <__gethex+0x282> 801cd16: 9a02 ldr r2, [sp, #8] 801cd18: f8d8 3004 ldr.w r3, [r8, #4] 801cd1c: 6013 str r3, [r2, #0] 801cd1e: 2301 movs r3, #1 801cd20: 6123 str r3, [r4, #16] 801cd22: f8ca 3000 str.w r3, [sl] 801cd26: 9b0e ldr r3, [sp, #56] @ 0x38 801cd28: 2562 movs r5, #98 @ 0x62 801cd2a: 601c str r4, [r3, #0] 801cd2c: e73a b.n 801cba4 <__gethex+0xf8> 801cd2e: 1e71 subs r1, r6, #1 801cd30: 4620 mov r0, r4 801cd32: f7fe fb80 bl 801b436 <__any_on> 801cd36: 2800 cmp r0, #0 801cd38: d1ed bne.n 801cd16 <__gethex+0x26a> 801cd3a: 9801 ldr r0, [sp, #4] 801cd3c: 4621 mov r1, r4 801cd3e: f7fd ff21 bl 801ab84 <_Bfree> 801cd42: 9a0e ldr r2, [sp, #56] @ 0x38 801cd44: 2300 movs r3, #0 801cd46: 6013 str r3, [r2, #0] 801cd48: 2550 movs r5, #80 @ 0x50 801cd4a: e72b b.n 801cba4 <__gethex+0xf8> 801cd4c: 9b0f ldr r3, [sp, #60] @ 0x3c 801cd4e: 2b00 cmp r3, #0 801cd50: d1f3 bne.n 801cd3a <__gethex+0x28e> 801cd52: e7e0 b.n 801cd16 <__gethex+0x26a> 801cd54: 9b0f ldr r3, [sp, #60] @ 0x3c 801cd56: 2b00 cmp r3, #0 801cd58: d1dd bne.n 801cd16 <__gethex+0x26a> 801cd5a: e7ee b.n 801cd3a <__gethex+0x28e> 801cd5c: 0801ddcf .word 0x0801ddcf 801cd60: 0801dd65 .word 0x0801dd65 801cd64: 0801de26 .word 0x0801de26 801cd68: 1e6f subs r7, r5, #1 801cd6a: f1b9 0f00 cmp.w r9, #0 801cd6e: d130 bne.n 801cdd2 <__gethex+0x326> 801cd70: b127 cbz r7, 801cd7c <__gethex+0x2d0> 801cd72: 4639 mov r1, r7 801cd74: 4620 mov r0, r4 801cd76: f7fe fb5e bl 801b436 <__any_on> 801cd7a: 4681 mov r9, r0 801cd7c: 117a asrs r2, r7, #5 801cd7e: 2301 movs r3, #1 801cd80: f85a 2022 ldr.w r2, [sl, r2, lsl #2] 801cd84: f007 071f and.w r7, r7, #31 801cd88: 40bb lsls r3, r7 801cd8a: 4213 tst r3, r2 801cd8c: 4629 mov r1, r5 801cd8e: 4620 mov r0, r4 801cd90: bf18 it ne 801cd92: f049 0902 orrne.w r9, r9, #2 801cd96: f7ff fe21 bl 801c9dc 801cd9a: f8d8 7004 ldr.w r7, [r8, #4] 801cd9e: 1b76 subs r6, r6, r5 801cda0: 2502 movs r5, #2 801cda2: f1b9 0f00 cmp.w r9, #0 801cda6: d047 beq.n 801ce38 <__gethex+0x38c> 801cda8: f8d8 300c ldr.w r3, [r8, #12] 801cdac: 2b02 cmp r3, #2 801cdae: d015 beq.n 801cddc <__gethex+0x330> 801cdb0: 2b03 cmp r3, #3 801cdb2: d017 beq.n 801cde4 <__gethex+0x338> 801cdb4: 2b01 cmp r3, #1 801cdb6: d109 bne.n 801cdcc <__gethex+0x320> 801cdb8: f019 0f02 tst.w r9, #2 801cdbc: d006 beq.n 801cdcc <__gethex+0x320> 801cdbe: f8da 3000 ldr.w r3, [sl] 801cdc2: ea49 0903 orr.w r9, r9, r3 801cdc6: f019 0f01 tst.w r9, #1 801cdca: d10e bne.n 801cdea <__gethex+0x33e> 801cdcc: f045 0510 orr.w r5, r5, #16 801cdd0: e032 b.n 801ce38 <__gethex+0x38c> 801cdd2: f04f 0901 mov.w r9, #1 801cdd6: e7d1 b.n 801cd7c <__gethex+0x2d0> 801cdd8: 2501 movs r5, #1 801cdda: e7e2 b.n 801cda2 <__gethex+0x2f6> 801cddc: 9b0f ldr r3, [sp, #60] @ 0x3c 801cdde: f1c3 0301 rsb r3, r3, #1 801cde2: 930f str r3, [sp, #60] @ 0x3c 801cde4: 9b0f ldr r3, [sp, #60] @ 0x3c 801cde6: 2b00 cmp r3, #0 801cde8: d0f0 beq.n 801cdcc <__gethex+0x320> 801cdea: f8d4 b010 ldr.w fp, [r4, #16] 801cdee: f104 0314 add.w r3, r4, #20 801cdf2: ea4f 0a8b mov.w sl, fp, lsl #2 801cdf6: eb03 018b add.w r1, r3, fp, lsl #2 801cdfa: f04f 0c00 mov.w ip, #0 801cdfe: 4618 mov r0, r3 801ce00: f853 2b04 ldr.w r2, [r3], #4 801ce04: f1b2 3fff cmp.w r2, #4294967295 @ 0xffffffff 801ce08: d01b beq.n 801ce42 <__gethex+0x396> 801ce0a: 3201 adds r2, #1 801ce0c: 6002 str r2, [r0, #0] 801ce0e: 2d02 cmp r5, #2 801ce10: f104 0314 add.w r3, r4, #20 801ce14: d13c bne.n 801ce90 <__gethex+0x3e4> 801ce16: f8d8 2000 ldr.w r2, [r8] 801ce1a: 3a01 subs r2, #1 801ce1c: 42b2 cmp r2, r6 801ce1e: d109 bne.n 801ce34 <__gethex+0x388> 801ce20: 1171 asrs r1, r6, #5 801ce22: 2201 movs r2, #1 801ce24: f853 3021 ldr.w r3, [r3, r1, lsl #2] 801ce28: f006 061f and.w r6, r6, #31 801ce2c: fa02 f606 lsl.w r6, r2, r6 801ce30: 421e tst r6, r3 801ce32: d13a bne.n 801ceaa <__gethex+0x3fe> 801ce34: f045 0520 orr.w r5, r5, #32 801ce38: 9b0e ldr r3, [sp, #56] @ 0x38 801ce3a: 601c str r4, [r3, #0] 801ce3c: 9b02 ldr r3, [sp, #8] 801ce3e: 601f str r7, [r3, #0] 801ce40: e6b0 b.n 801cba4 <__gethex+0xf8> 801ce42: 4299 cmp r1, r3 801ce44: f843 cc04 str.w ip, [r3, #-4] 801ce48: d8d9 bhi.n 801cdfe <__gethex+0x352> 801ce4a: 68a3 ldr r3, [r4, #8] 801ce4c: 459b cmp fp, r3 801ce4e: db17 blt.n 801ce80 <__gethex+0x3d4> 801ce50: 6861 ldr r1, [r4, #4] 801ce52: 9801 ldr r0, [sp, #4] 801ce54: 3101 adds r1, #1 801ce56: f7fd fe57 bl 801ab08 <_Balloc> 801ce5a: 4681 mov r9, r0 801ce5c: b918 cbnz r0, 801ce66 <__gethex+0x3ba> 801ce5e: 4b1a ldr r3, [pc, #104] @ (801cec8 <__gethex+0x41c>) 801ce60: 4602 mov r2, r0 801ce62: 2184 movs r1, #132 @ 0x84 801ce64: e6c5 b.n 801cbf2 <__gethex+0x146> 801ce66: 6922 ldr r2, [r4, #16] 801ce68: 3202 adds r2, #2 801ce6a: f104 010c add.w r1, r4, #12 801ce6e: 0092 lsls r2, r2, #2 801ce70: 300c adds r0, #12 801ce72: f7fc fece bl 8019c12 801ce76: 4621 mov r1, r4 801ce78: 9801 ldr r0, [sp, #4] 801ce7a: f7fd fe83 bl 801ab84 <_Bfree> 801ce7e: 464c mov r4, r9 801ce80: 6923 ldr r3, [r4, #16] 801ce82: 1c5a adds r2, r3, #1 801ce84: eb04 0383 add.w r3, r4, r3, lsl #2 801ce88: 6122 str r2, [r4, #16] 801ce8a: 2201 movs r2, #1 801ce8c: 615a str r2, [r3, #20] 801ce8e: e7be b.n 801ce0e <__gethex+0x362> 801ce90: 6922 ldr r2, [r4, #16] 801ce92: 455a cmp r2, fp 801ce94: dd0b ble.n 801ceae <__gethex+0x402> 801ce96: 2101 movs r1, #1 801ce98: 4620 mov r0, r4 801ce9a: f7ff fd9f bl 801c9dc 801ce9e: f8d8 3008 ldr.w r3, [r8, #8] 801cea2: 3701 adds r7, #1 801cea4: 42bb cmp r3, r7 801cea6: f6ff aee0 blt.w 801cc6a <__gethex+0x1be> 801ceaa: 2501 movs r5, #1 801ceac: e7c2 b.n 801ce34 <__gethex+0x388> 801ceae: f016 061f ands.w r6, r6, #31 801ceb2: d0fa beq.n 801ceaa <__gethex+0x3fe> 801ceb4: 4453 add r3, sl 801ceb6: f1c6 0620 rsb r6, r6, #32 801ceba: f853 0c04 ldr.w r0, [r3, #-4] 801cebe: f7fd ff13 bl 801ace8 <__hi0bits> 801cec2: 42b0 cmp r0, r6 801cec4: dbe7 blt.n 801ce96 <__gethex+0x3ea> 801cec6: e7f0 b.n 801ceaa <__gethex+0x3fe> 801cec8: 0801dd65 .word 0x0801dd65 0801cecc : 801cecc: f1c2 0208 rsb r2, r2, #8 801ced0: 0092 lsls r2, r2, #2 801ced2: b570 push {r4, r5, r6, lr} 801ced4: f1c2 0620 rsb r6, r2, #32 801ced8: 6843 ldr r3, [r0, #4] 801ceda: 6804 ldr r4, [r0, #0] 801cedc: fa03 f506 lsl.w r5, r3, r6 801cee0: 432c orrs r4, r5 801cee2: 40d3 lsrs r3, r2 801cee4: 6004 str r4, [r0, #0] 801cee6: f840 3f04 str.w r3, [r0, #4]! 801ceea: 4288 cmp r0, r1 801ceec: d3f4 bcc.n 801ced8 801ceee: bd70 pop {r4, r5, r6, pc} 0801cef0 <__match>: 801cef0: b530 push {r4, r5, lr} 801cef2: 6803 ldr r3, [r0, #0] 801cef4: 3301 adds r3, #1 801cef6: f811 4b01 ldrb.w r4, [r1], #1 801cefa: b914 cbnz r4, 801cf02 <__match+0x12> 801cefc: 6003 str r3, [r0, #0] 801cefe: 2001 movs r0, #1 801cf00: bd30 pop {r4, r5, pc} 801cf02: f813 2b01 ldrb.w r2, [r3], #1 801cf06: f1a2 0541 sub.w r5, r2, #65 @ 0x41 801cf0a: 2d19 cmp r5, #25 801cf0c: bf98 it ls 801cf0e: 3220 addls r2, #32 801cf10: 42a2 cmp r2, r4 801cf12: d0f0 beq.n 801cef6 <__match+0x6> 801cf14: 2000 movs r0, #0 801cf16: e7f3 b.n 801cf00 <__match+0x10> 0801cf18 <__hexnan>: 801cf18: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801cf1c: 680b ldr r3, [r1, #0] 801cf1e: 6801 ldr r1, [r0, #0] 801cf20: 115e asrs r6, r3, #5 801cf22: eb02 0686 add.w r6, r2, r6, lsl #2 801cf26: f013 031f ands.w r3, r3, #31 801cf2a: b087 sub sp, #28 801cf2c: bf18 it ne 801cf2e: 3604 addne r6, #4 801cf30: 2500 movs r5, #0 801cf32: 1f37 subs r7, r6, #4 801cf34: 4682 mov sl, r0 801cf36: 4690 mov r8, r2 801cf38: 9301 str r3, [sp, #4] 801cf3a: f846 5c04 str.w r5, [r6, #-4] 801cf3e: 46b9 mov r9, r7 801cf40: 463c mov r4, r7 801cf42: 9502 str r5, [sp, #8] 801cf44: 46ab mov fp, r5 801cf46: 784a ldrb r2, [r1, #1] 801cf48: 1c4b adds r3, r1, #1 801cf4a: 9303 str r3, [sp, #12] 801cf4c: b342 cbz r2, 801cfa0 <__hexnan+0x88> 801cf4e: 4610 mov r0, r2 801cf50: 9105 str r1, [sp, #20] 801cf52: 9204 str r2, [sp, #16] 801cf54: f7ff fd94 bl 801ca80 <__hexdig_fun> 801cf58: 2800 cmp r0, #0 801cf5a: d153 bne.n 801d004 <__hexnan+0xec> 801cf5c: 9a04 ldr r2, [sp, #16] 801cf5e: 9905 ldr r1, [sp, #20] 801cf60: 2a20 cmp r2, #32 801cf62: d818 bhi.n 801cf96 <__hexnan+0x7e> 801cf64: 9b02 ldr r3, [sp, #8] 801cf66: 459b cmp fp, r3 801cf68: dd13 ble.n 801cf92 <__hexnan+0x7a> 801cf6a: 454c cmp r4, r9 801cf6c: d206 bcs.n 801cf7c <__hexnan+0x64> 801cf6e: 2d07 cmp r5, #7 801cf70: dc04 bgt.n 801cf7c <__hexnan+0x64> 801cf72: 462a mov r2, r5 801cf74: 4649 mov r1, r9 801cf76: 4620 mov r0, r4 801cf78: f7ff ffa8 bl 801cecc 801cf7c: 4544 cmp r4, r8 801cf7e: d954 bls.n 801d02a <__hexnan+0x112> 801cf80: 2300 movs r3, #0 801cf82: f1a4 0904 sub.w r9, r4, #4 801cf86: f844 3c04 str.w r3, [r4, #-4] 801cf8a: f8cd b008 str.w fp, [sp, #8] 801cf8e: 464c mov r4, r9 801cf90: 461d mov r5, r3 801cf92: 9903 ldr r1, [sp, #12] 801cf94: e7d7 b.n 801cf46 <__hexnan+0x2e> 801cf96: 2a29 cmp r2, #41 @ 0x29 801cf98: d159 bne.n 801d04e <__hexnan+0x136> 801cf9a: 3102 adds r1, #2 801cf9c: f8ca 1000 str.w r1, [sl] 801cfa0: f1bb 0f00 cmp.w fp, #0 801cfa4: d053 beq.n 801d04e <__hexnan+0x136> 801cfa6: 454c cmp r4, r9 801cfa8: d206 bcs.n 801cfb8 <__hexnan+0xa0> 801cfaa: 2d07 cmp r5, #7 801cfac: dc04 bgt.n 801cfb8 <__hexnan+0xa0> 801cfae: 462a mov r2, r5 801cfb0: 4649 mov r1, r9 801cfb2: 4620 mov r0, r4 801cfb4: f7ff ff8a bl 801cecc 801cfb8: 4544 cmp r4, r8 801cfba: d938 bls.n 801d02e <__hexnan+0x116> 801cfbc: f1a8 0204 sub.w r2, r8, #4 801cfc0: 4623 mov r3, r4 801cfc2: f853 1b04 ldr.w r1, [r3], #4 801cfc6: f842 1f04 str.w r1, [r2, #4]! 801cfca: 429f cmp r7, r3 801cfcc: d2f9 bcs.n 801cfc2 <__hexnan+0xaa> 801cfce: 1b3b subs r3, r7, r4 801cfd0: f023 0303 bic.w r3, r3, #3 801cfd4: 3401 adds r4, #1 801cfd6: 3e03 subs r6, #3 801cfd8: 42b4 cmp r4, r6 801cfda: bf88 it hi 801cfdc: 2300 movhi r3, #0 801cfde: f108 0204 add.w r2, r8, #4 801cfe2: 4413 add r3, r2 801cfe4: 2100 movs r1, #0 801cfe6: 461a mov r2, r3 801cfe8: 3304 adds r3, #4 801cfea: 429f cmp r7, r3 801cfec: 6011 str r1, [r2, #0] 801cfee: d2fa bcs.n 801cfe6 <__hexnan+0xce> 801cff0: 683b ldr r3, [r7, #0] 801cff2: b91b cbnz r3, 801cffc <__hexnan+0xe4> 801cff4: 4547 cmp r7, r8 801cff6: d128 bne.n 801d04a <__hexnan+0x132> 801cff8: 2301 movs r3, #1 801cffa: 603b str r3, [r7, #0] 801cffc: 2005 movs r0, #5 801cffe: b007 add sp, #28 801d000: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801d004: 3501 adds r5, #1 801d006: 2d08 cmp r5, #8 801d008: f10b 0b01 add.w fp, fp, #1 801d00c: dd06 ble.n 801d01c <__hexnan+0x104> 801d00e: 4544 cmp r4, r8 801d010: d9bf bls.n 801cf92 <__hexnan+0x7a> 801d012: 2300 movs r3, #0 801d014: f844 3c04 str.w r3, [r4, #-4] 801d018: 2501 movs r5, #1 801d01a: 3c04 subs r4, #4 801d01c: 6822 ldr r2, [r4, #0] 801d01e: f000 000f and.w r0, r0, #15 801d022: ea40 1002 orr.w r0, r0, r2, lsl #4 801d026: 6020 str r0, [r4, #0] 801d028: e7b3 b.n 801cf92 <__hexnan+0x7a> 801d02a: 2508 movs r5, #8 801d02c: e7b1 b.n 801cf92 <__hexnan+0x7a> 801d02e: 9b01 ldr r3, [sp, #4] 801d030: 2b00 cmp r3, #0 801d032: d0dd beq.n 801cff0 <__hexnan+0xd8> 801d034: f1c3 0320 rsb r3, r3, #32 801d038: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801d03c: 40da lsrs r2, r3 801d03e: f856 3c04 ldr.w r3, [r6, #-4] 801d042: 4013 ands r3, r2 801d044: f846 3c04 str.w r3, [r6, #-4] 801d048: e7d2 b.n 801cff0 <__hexnan+0xd8> 801d04a: 3f04 subs r7, #4 801d04c: e7d0 b.n 801cff0 <__hexnan+0xd8> 801d04e: 2004 movs r0, #4 801d050: e7d5 b.n 801cffe <__hexnan+0xe6> 0801d052 <__ascii_mbtowc>: 801d052: b082 sub sp, #8 801d054: b901 cbnz r1, 801d058 <__ascii_mbtowc+0x6> 801d056: a901 add r1, sp, #4 801d058: b142 cbz r2, 801d06c <__ascii_mbtowc+0x1a> 801d05a: b14b cbz r3, 801d070 <__ascii_mbtowc+0x1e> 801d05c: 7813 ldrb r3, [r2, #0] 801d05e: 600b str r3, [r1, #0] 801d060: 7812 ldrb r2, [r2, #0] 801d062: 1e10 subs r0, r2, #0 801d064: bf18 it ne 801d066: 2001 movne r0, #1 801d068: b002 add sp, #8 801d06a: 4770 bx lr 801d06c: 4610 mov r0, r2 801d06e: e7fb b.n 801d068 <__ascii_mbtowc+0x16> 801d070: f06f 0001 mvn.w r0, #1 801d074: e7f8 b.n 801d068 <__ascii_mbtowc+0x16> 0801d076 <_realloc_r>: 801d076: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801d07a: 4607 mov r7, r0 801d07c: 4614 mov r4, r2 801d07e: 460d mov r5, r1 801d080: b921 cbnz r1, 801d08c <_realloc_r+0x16> 801d082: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801d086: 4611 mov r1, r2 801d088: f7fd bcb2 b.w 801a9f0 <_malloc_r> 801d08c: b92a cbnz r2, 801d09a <_realloc_r+0x24> 801d08e: f7fd fc3b bl 801a908 <_free_r> 801d092: 4625 mov r5, r4 801d094: 4628 mov r0, r5 801d096: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801d09a: f000 f840 bl 801d11e <_malloc_usable_size_r> 801d09e: 4284 cmp r4, r0 801d0a0: 4606 mov r6, r0 801d0a2: d802 bhi.n 801d0aa <_realloc_r+0x34> 801d0a4: ebb4 0f50 cmp.w r4, r0, lsr #1 801d0a8: d8f4 bhi.n 801d094 <_realloc_r+0x1e> 801d0aa: 4621 mov r1, r4 801d0ac: 4638 mov r0, r7 801d0ae: f7fd fc9f bl 801a9f0 <_malloc_r> 801d0b2: 4680 mov r8, r0 801d0b4: b908 cbnz r0, 801d0ba <_realloc_r+0x44> 801d0b6: 4645 mov r5, r8 801d0b8: e7ec b.n 801d094 <_realloc_r+0x1e> 801d0ba: 42b4 cmp r4, r6 801d0bc: 4622 mov r2, r4 801d0be: 4629 mov r1, r5 801d0c0: bf28 it cs 801d0c2: 4632 movcs r2, r6 801d0c4: f7fc fda5 bl 8019c12 801d0c8: 4629 mov r1, r5 801d0ca: 4638 mov r0, r7 801d0cc: f7fd fc1c bl 801a908 <_free_r> 801d0d0: e7f1 b.n 801d0b6 <_realloc_r+0x40> 0801d0d2 <__ascii_wctomb>: 801d0d2: 4603 mov r3, r0 801d0d4: 4608 mov r0, r1 801d0d6: b141 cbz r1, 801d0ea <__ascii_wctomb+0x18> 801d0d8: 2aff cmp r2, #255 @ 0xff 801d0da: d904 bls.n 801d0e6 <__ascii_wctomb+0x14> 801d0dc: 228a movs r2, #138 @ 0x8a 801d0de: 601a str r2, [r3, #0] 801d0e0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801d0e4: 4770 bx lr 801d0e6: 700a strb r2, [r1, #0] 801d0e8: 2001 movs r0, #1 801d0ea: 4770 bx lr 0801d0ec : 801d0ec: b40e push {r1, r2, r3} 801d0ee: b503 push {r0, r1, lr} 801d0f0: 4601 mov r1, r0 801d0f2: ab03 add r3, sp, #12 801d0f4: 4805 ldr r0, [pc, #20] @ (801d10c ) 801d0f6: f853 2b04 ldr.w r2, [r3], #4 801d0fa: 6800 ldr r0, [r0, #0] 801d0fc: 9301 str r3, [sp, #4] 801d0fe: f7ff f9bb bl 801c478 <_vfiprintf_r> 801d102: b002 add sp, #8 801d104: f85d eb04 ldr.w lr, [sp], #4 801d108: b003 add sp, #12 801d10a: 4770 bx lr 801d10c: 2000011c .word 0x2000011c 0801d110 : 801d110: b508 push {r3, lr} 801d112: 2006 movs r0, #6 801d114: f000 f834 bl 801d180 801d118: 2001 movs r0, #1 801d11a: f7e9 f857 bl 80061cc <_exit> 0801d11e <_malloc_usable_size_r>: 801d11e: f851 3c04 ldr.w r3, [r1, #-4] 801d122: 1f18 subs r0, r3, #4 801d124: 2b00 cmp r3, #0 801d126: bfbc itt lt 801d128: 580b ldrlt r3, [r1, r0] 801d12a: 18c0 addlt r0, r0, r3 801d12c: 4770 bx lr 0801d12e <_raise_r>: 801d12e: 291f cmp r1, #31 801d130: b538 push {r3, r4, r5, lr} 801d132: 4605 mov r5, r0 801d134: 460c mov r4, r1 801d136: d904 bls.n 801d142 <_raise_r+0x14> 801d138: 2316 movs r3, #22 801d13a: 6003 str r3, [r0, #0] 801d13c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801d140: bd38 pop {r3, r4, r5, pc} 801d142: 6bc2 ldr r2, [r0, #60] @ 0x3c 801d144: b112 cbz r2, 801d14c <_raise_r+0x1e> 801d146: f852 3021 ldr.w r3, [r2, r1, lsl #2] 801d14a: b94b cbnz r3, 801d160 <_raise_r+0x32> 801d14c: 4628 mov r0, r5 801d14e: f000 f831 bl 801d1b4 <_getpid_r> 801d152: 4622 mov r2, r4 801d154: 4601 mov r1, r0 801d156: 4628 mov r0, r5 801d158: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 801d15c: f000 b818 b.w 801d190 <_kill_r> 801d160: 2b01 cmp r3, #1 801d162: d00a beq.n 801d17a <_raise_r+0x4c> 801d164: 1c59 adds r1, r3, #1 801d166: d103 bne.n 801d170 <_raise_r+0x42> 801d168: 2316 movs r3, #22 801d16a: 6003 str r3, [r0, #0] 801d16c: 2001 movs r0, #1 801d16e: e7e7 b.n 801d140 <_raise_r+0x12> 801d170: 2100 movs r1, #0 801d172: f842 1024 str.w r1, [r2, r4, lsl #2] 801d176: 4620 mov r0, r4 801d178: 4798 blx r3 801d17a: 2000 movs r0, #0 801d17c: e7e0 b.n 801d140 <_raise_r+0x12> ... 0801d180 : 801d180: 4b02 ldr r3, [pc, #8] @ (801d18c ) 801d182: 4601 mov r1, r0 801d184: 6818 ldr r0, [r3, #0] 801d186: f7ff bfd2 b.w 801d12e <_raise_r> 801d18a: bf00 nop 801d18c: 2000011c .word 0x2000011c 0801d190 <_kill_r>: 801d190: b538 push {r3, r4, r5, lr} 801d192: 4d07 ldr r5, [pc, #28] @ (801d1b0 <_kill_r+0x20>) 801d194: 2300 movs r3, #0 801d196: 4604 mov r4, r0 801d198: 4608 mov r0, r1 801d19a: 4611 mov r1, r2 801d19c: 602b str r3, [r5, #0] 801d19e: f7e9 f805 bl 80061ac <_kill> 801d1a2: 1c43 adds r3, r0, #1 801d1a4: d102 bne.n 801d1ac <_kill_r+0x1c> 801d1a6: 682b ldr r3, [r5, #0] 801d1a8: b103 cbz r3, 801d1ac <_kill_r+0x1c> 801d1aa: 6023 str r3, [r4, #0] 801d1ac: bd38 pop {r3, r4, r5, pc} 801d1ae: bf00 nop 801d1b0: 20013c38 .word 0x20013c38 0801d1b4 <_getpid_r>: 801d1b4: f7e8 bff2 b.w 800619c <_getpid> 0801d1b8 : 801d1b8: b538 push {r3, r4, r5, lr} 801d1ba: ed2d 8b02 vpush {d8} 801d1be: ec55 4b10 vmov r4, r5, d0 801d1c2: f000 f82d bl 801d220 <__ieee754_sqrt> 801d1c6: 4622 mov r2, r4 801d1c8: 462b mov r3, r5 801d1ca: 4620 mov r0, r4 801d1cc: 4629 mov r1, r5 801d1ce: eeb0 8a40 vmov.f32 s16, s0 801d1d2: eef0 8a60 vmov.f32 s17, s1 801d1d6: f7e3 fc81 bl 8000adc <__aeabi_dcmpun> 801d1da: b930 cbnz r0, 801d1ea 801d1dc: 2200 movs r2, #0 801d1de: 2300 movs r3, #0 801d1e0: 4620 mov r0, r4 801d1e2: 4629 mov r1, r5 801d1e4: f7e3 fc52 bl 8000a8c <__aeabi_dcmplt> 801d1e8: b930 cbnz r0, 801d1f8 801d1ea: eeb0 0a48 vmov.f32 s0, s16 801d1ee: eef0 0a68 vmov.f32 s1, s17 801d1f2: ecbd 8b02 vpop {d8} 801d1f6: bd38 pop {r3, r4, r5, pc} 801d1f8: f7fc fcde bl 8019bb8 <__errno> 801d1fc: 2200 movs r2, #0 801d1fe: 2300 movs r3, #0 801d200: 2121 movs r1, #33 @ 0x21 801d202: 6001 str r1, [r0, #0] 801d204: 4610 mov r0, r2 801d206: 4619 mov r1, r3 801d208: f7e3 faf8 bl 80007fc <__aeabi_ddiv> 801d20c: ec41 0b18 vmov d8, r0, r1 801d210: eeb0 0a48 vmov.f32 s0, s16 801d214: eef0 0a68 vmov.f32 s1, s17 801d218: ecbd 8b02 vpop {d8} 801d21c: bd38 pop {r3, r4, r5, pc} 801d21e: bf00 nop 0801d220 <__ieee754_sqrt>: 801d220: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801d224: 4977 ldr r1, [pc, #476] @ (801d404 <__ieee754_sqrt+0x1e4>) 801d226: ec55 4b10 vmov r4, r5, d0 801d22a: 43a9 bics r1, r5 801d22c: f000 80ae beq.w 801d38c <__ieee754_sqrt+0x16c> 801d230: 2d00 cmp r5, #0 801d232: 462a mov r2, r5 801d234: 4623 mov r3, r4 801d236: dd55 ble.n 801d2e4 <__ieee754_sqrt+0xc4> 801d238: 152c asrs r4, r5, #20 801d23a: d062 beq.n 801d302 <__ieee754_sqrt+0xe2> 801d23c: f3c2 0213 ubfx r2, r2, #0, #20 801d240: 07e1 lsls r1, r4, #31 801d242: f2a4 37ff subw r7, r4, #1023 @ 0x3ff 801d246: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 801d24a: d403 bmi.n 801d254 <__ieee754_sqrt+0x34> 801d24c: 0052 lsls r2, r2, #1 801d24e: eb02 72d3 add.w r2, r2, r3, lsr #31 801d252: 005b lsls r3, r3, #1 801d254: 0052 lsls r2, r2, #1 801d256: 2600 movs r6, #0 801d258: eb02 72d3 add.w r2, r2, r3, lsr #31 801d25c: 107f asrs r7, r7, #1 801d25e: 005b lsls r3, r3, #1 801d260: 2416 movs r4, #22 801d262: 46b4 mov ip, r6 801d264: f44f 1100 mov.w r1, #2097152 @ 0x200000 801d268: eb0c 0001 add.w r0, ip, r1 801d26c: 4290 cmp r0, r2 801d26e: ea4f 75d3 mov.w r5, r3, lsr #31 801d272: ea4f 0343 mov.w r3, r3, lsl #1 801d276: dc03 bgt.n 801d280 <__ieee754_sqrt+0x60> 801d278: eb00 0c01 add.w ip, r0, r1 801d27c: 1a12 subs r2, r2, r0 801d27e: 440e add r6, r1 801d280: 3c01 subs r4, #1 801d282: eb05 0242 add.w r2, r5, r2, lsl #1 801d286: ea4f 0151 mov.w r1, r1, lsr #1 801d28a: d1ed bne.n 801d268 <__ieee754_sqrt+0x48> 801d28c: 46a0 mov r8, r4 801d28e: 2520 movs r5, #32 801d290: f04f 4000 mov.w r0, #2147483648 @ 0x80000000 801d294: e00a b.n 801d2ac <__ieee754_sqrt+0x8c> 801d296: d043 beq.n 801d320 <__ieee754_sqrt+0x100> 801d298: 0051 lsls r1, r2, #1 801d29a: eb01 71d3 add.w r1, r1, r3, lsr #31 801d29e: 3d01 subs r5, #1 801d2a0: 460a mov r2, r1 801d2a2: ea4f 0343 mov.w r3, r3, lsl #1 801d2a6: ea4f 0050 mov.w r0, r0, lsr #1 801d2aa: d045 beq.n 801d338 <__ieee754_sqrt+0x118> 801d2ac: 4562 cmp r2, ip 801d2ae: eb00 0e08 add.w lr, r0, r8 801d2b2: ddf0 ble.n 801d296 <__ieee754_sqrt+0x76> 801d2b4: f1be 0f00 cmp.w lr, #0 801d2b8: eb0e 0800 add.w r8, lr, r0 801d2bc: db0c blt.n 801d2d8 <__ieee754_sqrt+0xb8> 801d2be: 46e1 mov r9, ip 801d2c0: eba2 010c sub.w r1, r2, ip 801d2c4: 459e cmp lr, r3 801d2c6: bf88 it hi 801d2c8: f101 31ff addhi.w r1, r1, #4294967295 @ 0xffffffff 801d2cc: 0049 lsls r1, r1, #1 801d2ce: 46cc mov ip, r9 801d2d0: eba3 030e sub.w r3, r3, lr 801d2d4: 4404 add r4, r0 801d2d6: e7e0 b.n 801d29a <__ieee754_sqrt+0x7a> 801d2d8: f1b8 0f00 cmp.w r8, #0 801d2dc: dbef blt.n 801d2be <__ieee754_sqrt+0x9e> 801d2de: f10c 0901 add.w r9, ip, #1 801d2e2: e7ed b.n 801d2c0 <__ieee754_sqrt+0xa0> 801d2e4: f025 4100 bic.w r1, r5, #2147483648 @ 0x80000000 801d2e8: 4321 orrs r1, r4 801d2ea: d046 beq.n 801d37a <__ieee754_sqrt+0x15a> 801d2ec: 2d00 cmp r5, #0 801d2ee: d174 bne.n 801d3da <__ieee754_sqrt+0x1ba> 801d2f0: 0ad9 lsrs r1, r3, #11 801d2f2: 3a15 subs r2, #21 801d2f4: 055b lsls r3, r3, #21 801d2f6: 2900 cmp r1, #0 801d2f8: d0fa beq.n 801d2f0 <__ieee754_sqrt+0xd0> 801d2fa: 02ce lsls r6, r1, #11 801d2fc: 4614 mov r4, r2 801d2fe: d47d bmi.n 801d3fc <__ieee754_sqrt+0x1dc> 801d300: 460a mov r2, r1 801d302: 2100 movs r1, #0 801d304: 0052 lsls r2, r2, #1 801d306: 02d5 lsls r5, r2, #11 801d308: 4608 mov r0, r1 801d30a: f101 0101 add.w r1, r1, #1 801d30e: d5f9 bpl.n 801d304 <__ieee754_sqrt+0xe4> 801d310: f1c1 0520 rsb r5, r1, #32 801d314: fa23 f505 lsr.w r5, r3, r5 801d318: 432a orrs r2, r5 801d31a: 408b lsls r3, r1 801d31c: 1a24 subs r4, r4, r0 801d31e: e78d b.n 801d23c <__ieee754_sqrt+0x1c> 801d320: 459e cmp lr, r3 801d322: d902 bls.n 801d32a <__ieee754_sqrt+0x10a> 801d324: ea4f 014c mov.w r1, ip, lsl #1 801d328: e7b7 b.n 801d29a <__ieee754_sqrt+0x7a> 801d32a: f1be 0f00 cmp.w lr, #0 801d32e: eb0e 0800 add.w r8, lr, r0 801d332: db24 blt.n 801d37e <__ieee754_sqrt+0x15e> 801d334: 2100 movs r1, #0 801d336: e7cb b.n 801d2d0 <__ieee754_sqrt+0xb0> 801d338: 4319 orrs r1, r3 801d33a: d012 beq.n 801d362 <__ieee754_sqrt+0x142> 801d33c: f8df a0c8 ldr.w sl, [pc, #200] @ 801d408 <__ieee754_sqrt+0x1e8> 801d340: f8df b0c8 ldr.w fp, [pc, #200] @ 801d40c <__ieee754_sqrt+0x1ec> 801d344: e9da 0100 ldrd r0, r1, [sl] 801d348: e9db 2300 ldrd r2, r3, [fp] 801d34c: f7e2 ff74 bl 8000238 <__aeabi_dsub> 801d350: e9da 8900 ldrd r8, r9, [sl] 801d354: 4602 mov r2, r0 801d356: 460b mov r3, r1 801d358: 4640 mov r0, r8 801d35a: 4649 mov r1, r9 801d35c: f7e3 fba0 bl 8000aa0 <__aeabi_dcmple> 801d360: bb10 cbnz r0, 801d3a8 <__ieee754_sqrt+0x188> 801d362: 0865 lsrs r5, r4, #1 801d364: 1071 asrs r1, r6, #1 801d366: f101 517f add.w r1, r1, #1069547520 @ 0x3fc00000 801d36a: f501 1100 add.w r1, r1, #2097152 @ 0x200000 801d36e: eb01 5307 add.w r3, r1, r7, lsl #20 801d372: ea45 72c6 orr.w r2, r5, r6, lsl #31 801d376: ec43 2b10 vmov d0, r2, r3 801d37a: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 801d37e: f1b8 0f00 cmp.w r8, #0 801d382: dbd7 blt.n 801d334 <__ieee754_sqrt+0x114> 801d384: f10c 0c01 add.w ip, ip, #1 801d388: 2100 movs r1, #0 801d38a: e7a1 b.n 801d2d0 <__ieee754_sqrt+0xb0> 801d38c: 4622 mov r2, r4 801d38e: 462b mov r3, r5 801d390: 4620 mov r0, r4 801d392: 4629 mov r1, r5 801d394: f7e3 f908 bl 80005a8 <__aeabi_dmul> 801d398: 4622 mov r2, r4 801d39a: 462b mov r3, r5 801d39c: f7e2 ff4e bl 800023c <__adddf3> 801d3a0: ec41 0b10 vmov d0, r0, r1 801d3a4: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 801d3a8: f1b4 3fff cmp.w r4, #4294967295 @ 0xffffffff 801d3ac: e9da 0100 ldrd r0, r1, [sl] 801d3b0: e9db 2300 ldrd r2, r3, [fp] 801d3b4: d01e beq.n 801d3f4 <__ieee754_sqrt+0x1d4> 801d3b6: f7e2 ff41 bl 800023c <__adddf3> 801d3ba: e9da 8900 ldrd r8, r9, [sl] 801d3be: 4602 mov r2, r0 801d3c0: 460b mov r3, r1 801d3c2: 4640 mov r0, r8 801d3c4: 4649 mov r1, r9 801d3c6: f7e3 fb61 bl 8000a8c <__aeabi_dcmplt> 801d3ca: b1a8 cbz r0, 801d3f8 <__ieee754_sqrt+0x1d8> 801d3cc: 1ca3 adds r3, r4, #2 801d3ce: f104 0502 add.w r5, r4, #2 801d3d2: bf08 it eq 801d3d4: 3601 addeq r6, #1 801d3d6: 086d lsrs r5, r5, #1 801d3d8: e7c4 b.n 801d364 <__ieee754_sqrt+0x144> 801d3da: 4622 mov r2, r4 801d3dc: 462b mov r3, r5 801d3de: 4620 mov r0, r4 801d3e0: 4629 mov r1, r5 801d3e2: f7e2 ff29 bl 8000238 <__aeabi_dsub> 801d3e6: 4602 mov r2, r0 801d3e8: 460b mov r3, r1 801d3ea: f7e3 fa07 bl 80007fc <__aeabi_ddiv> 801d3ee: ec41 0b10 vmov d0, r0, r1 801d3f2: e7c2 b.n 801d37a <__ieee754_sqrt+0x15a> 801d3f4: 3601 adds r6, #1 801d3f6: e7b5 b.n 801d364 <__ieee754_sqrt+0x144> 801d3f8: 3401 adds r4, #1 801d3fa: e7b2 b.n 801d362 <__ieee754_sqrt+0x142> 801d3fc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801d400: 460a mov r2, r1 801d402: e78b b.n 801d31c <__ieee754_sqrt+0xfc> 801d404: 7ff00000 .word 0x7ff00000 801d408: 0801e0e8 .word 0x0801e0e8 801d40c: 0801e0e0 .word 0x0801e0e0 0801d410 <_init>: 801d410: b5f8 push {r3, r4, r5, r6, r7, lr} 801d412: bf00 nop 801d414: bcf8 pop {r3, r4, r5, r6, r7} 801d416: bc08 pop {r3} 801d418: 469e mov lr, r3 801d41a: 4770 bx lr 0801d41c <_fini>: 801d41c: b5f8 push {r3, r4, r5, r6, r7, lr} 801d41e: bf00 nop 801d420: bcf8 pop {r3, r4, r5, r6, r7} 801d422: bc08 pop {r3} 801d424: 469e mov lr, r3 801d426: 4770 bx lr