Trinity_Devboard_V2.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0001dc98 08000140 08000140 00001140 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000c58 0801ddd8 0801ddd8 0001edd8 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 0801ea30 0801ea30 0001fa30 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0801ea38 0801ea38 0001fa38 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 0801ea3c 0801ea3c 0001fa3c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 000002d0 20000008 0801ea40 00020008 2**2 CONTENTS, ALLOC, LOAD, DATA 7 SYSTEM_DRIVER_CONTEXT 00000011 200002d8 0801ed10 000202d8 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .bss 000139fc 200002ec 0801ed21 000202ec 2**2 ALLOC 9 ._user_heap_stack 00000600 20013ce8 0801ed21 00020ce8 2**0 ALLOC 10 .ARM.attributes 00000030 00000000 00000000 0002194a 2**0 CONTENTS, READONLY 11 MAPPING_TABLE 00000028 20030000 20030000 00022000 2**2 ALLOC 12 MB_MEM1 000000b0 20030028 20030028 00022000 2**2 ALLOC 13 .MB_MEM2 00000872 200300d8 0801ed21 000210d8 2**2 CONTENTS, ALLOC, LOAD, DATA 14 .debug_info 0003ba7b 00000000 00000000 0002197a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_abbrev 00008772 00000000 00000000 0005d3f5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_aranges 00003678 00000000 00000000 00065b68 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_rnglists 0000297a 00000000 00000000 000691e0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_macro 00032a14 00000000 00000000 0006bb5a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line 0003c3ba 00000000 00000000 0009e56e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .debug_str 00112f4a 00000000 00000000 000da928 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .comment 00000043 00000000 00000000 001ed872 2**0 CONTENTS, READONLY 22 .debug_frame 0000ee28 00000000 00000000 001ed8b8 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 23 .debug_line_str 00000061 00000000 00000000 001fc6e0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000140 <__do_global_dtors_aux>: 8000140: b510 push {r4, lr} 8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>) 8000144: 7823 ldrb r3, [r4, #0] 8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16> 8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>) 800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12> 800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>) 800014e: f3af 8000 nop.w 8000152: 2301 movs r3, #1 8000154: 7023 strb r3, [r4, #0] 8000156: bd10 pop {r4, pc} 8000158: 200002ec .word 0x200002ec 800015c: 00000000 .word 0x00000000 8000160: 0801ddc0 .word 0x0801ddc0 08000164 : 8000164: b508 push {r3, lr} 8000166: 4b03 ldr r3, [pc, #12] @ (8000174 ) 8000168: b11b cbz r3, 8000172 800016a: 4903 ldr r1, [pc, #12] @ (8000178 ) 800016c: 4803 ldr r0, [pc, #12] @ (800017c ) 800016e: f3af 8000 nop.w 8000172: bd08 pop {r3, pc} 8000174: 00000000 .word 0x00000000 8000178: 200002f0 .word 0x200002f0 800017c: 0801ddc0 .word 0x0801ddc0 08000180 : 8000180: f001 01ff and.w r1, r1, #255 @ 0xff 8000184: 2a10 cmp r2, #16 8000186: db2b blt.n 80001e0 8000188: f010 0f07 tst.w r0, #7 800018c: d008 beq.n 80001a0 800018e: f810 3b01 ldrb.w r3, [r0], #1 8000192: 3a01 subs r2, #1 8000194: 428b cmp r3, r1 8000196: d02d beq.n 80001f4 8000198: f010 0f07 tst.w r0, #7 800019c: b342 cbz r2, 80001f0 800019e: d1f6 bne.n 800018e 80001a0: b4f0 push {r4, r5, r6, r7} 80001a2: ea41 2101 orr.w r1, r1, r1, lsl #8 80001a6: ea41 4101 orr.w r1, r1, r1, lsl #16 80001aa: f022 0407 bic.w r4, r2, #7 80001ae: f07f 0700 mvns.w r7, #0 80001b2: 2300 movs r3, #0 80001b4: e8f0 5602 ldrd r5, r6, [r0], #8 80001b8: 3c08 subs r4, #8 80001ba: ea85 0501 eor.w r5, r5, r1 80001be: ea86 0601 eor.w r6, r6, r1 80001c2: fa85 f547 uadd8 r5, r5, r7 80001c6: faa3 f587 sel r5, r3, r7 80001ca: fa86 f647 uadd8 r6, r6, r7 80001ce: faa5 f687 sel r6, r5, r7 80001d2: b98e cbnz r6, 80001f8 80001d4: d1ee bne.n 80001b4 80001d6: bcf0 pop {r4, r5, r6, r7} 80001d8: f001 01ff and.w r1, r1, #255 @ 0xff 80001dc: f002 0207 and.w r2, r2, #7 80001e0: b132 cbz r2, 80001f0 80001e2: f810 3b01 ldrb.w r3, [r0], #1 80001e6: 3a01 subs r2, #1 80001e8: ea83 0301 eor.w r3, r3, r1 80001ec: b113 cbz r3, 80001f4 80001ee: d1f8 bne.n 80001e2 80001f0: 2000 movs r0, #0 80001f2: 4770 bx lr 80001f4: 3801 subs r0, #1 80001f6: 4770 bx lr 80001f8: 2d00 cmp r5, #0 80001fa: bf06 itte eq 80001fc: 4635 moveq r5, r6 80001fe: 3803 subeq r0, #3 8000200: 3807 subne r0, #7 8000202: f015 0f01 tst.w r5, #1 8000206: d107 bne.n 8000218 8000208: 3001 adds r0, #1 800020a: f415 7f80 tst.w r5, #256 @ 0x100 800020e: bf02 ittt eq 8000210: 3001 addeq r0, #1 8000212: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000216: 3001 addeq r0, #1 8000218: bcf0 pop {r4, r5, r6, r7} 800021a: 3801 subs r0, #1 800021c: 4770 bx lr 800021e: bf00 nop 08000220 : 8000220: 4603 mov r3, r0 8000222: f813 2b01 ldrb.w r2, [r3], #1 8000226: 2a00 cmp r2, #0 8000228: d1fb bne.n 8000222 800022a: 1a18 subs r0, r3, r0 800022c: 3801 subs r0, #1 800022e: 4770 bx lr 08000230 <__aeabi_drsub>: 8000230: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 8000234: e002 b.n 800023c <__adddf3> 8000236: bf00 nop 08000238 <__aeabi_dsub>: 8000238: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 0800023c <__adddf3>: 800023c: b530 push {r4, r5, lr} 800023e: ea4f 0441 mov.w r4, r1, lsl #1 8000242: ea4f 0543 mov.w r5, r3, lsl #1 8000246: ea94 0f05 teq r4, r5 800024a: bf08 it eq 800024c: ea90 0f02 teqeq r0, r2 8000250: bf1f itttt ne 8000252: ea54 0c00 orrsne.w ip, r4, r0 8000256: ea55 0c02 orrsne.w ip, r5, r2 800025a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800025e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000262: f000 80e2 beq.w 800042a <__adddf3+0x1ee> 8000266: ea4f 5454 mov.w r4, r4, lsr #21 800026a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800026e: bfb8 it lt 8000270: 426d neglt r5, r5 8000272: dd0c ble.n 800028e <__adddf3+0x52> 8000274: 442c add r4, r5 8000276: ea80 0202 eor.w r2, r0, r2 800027a: ea81 0303 eor.w r3, r1, r3 800027e: ea82 0000 eor.w r0, r2, r0 8000282: ea83 0101 eor.w r1, r3, r1 8000286: ea80 0202 eor.w r2, r0, r2 800028a: ea81 0303 eor.w r3, r1, r3 800028e: 2d36 cmp r5, #54 @ 0x36 8000290: bf88 it hi 8000292: bd30 pophi {r4, r5, pc} 8000294: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8000298: ea4f 3101 mov.w r1, r1, lsl #12 800029c: f44f 1c80 mov.w ip, #1048576 @ 0x100000 80002a0: ea4c 3111 orr.w r1, ip, r1, lsr #12 80002a4: d002 beq.n 80002ac <__adddf3+0x70> 80002a6: 4240 negs r0, r0 80002a8: eb61 0141 sbc.w r1, r1, r1, lsl #1 80002ac: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 80002b0: ea4f 3303 mov.w r3, r3, lsl #12 80002b4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002b8: d002 beq.n 80002c0 <__adddf3+0x84> 80002ba: 4252 negs r2, r2 80002bc: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002c0: ea94 0f05 teq r4, r5 80002c4: f000 80a7 beq.w 8000416 <__adddf3+0x1da> 80002c8: f1a4 0401 sub.w r4, r4, #1 80002cc: f1d5 0e20 rsbs lr, r5, #32 80002d0: db0d blt.n 80002ee <__adddf3+0xb2> 80002d2: fa02 fc0e lsl.w ip, r2, lr 80002d6: fa22 f205 lsr.w r2, r2, r5 80002da: 1880 adds r0, r0, r2 80002dc: f141 0100 adc.w r1, r1, #0 80002e0: fa03 f20e lsl.w r2, r3, lr 80002e4: 1880 adds r0, r0, r2 80002e6: fa43 f305 asr.w r3, r3, r5 80002ea: 4159 adcs r1, r3 80002ec: e00e b.n 800030c <__adddf3+0xd0> 80002ee: f1a5 0520 sub.w r5, r5, #32 80002f2: f10e 0e20 add.w lr, lr, #32 80002f6: 2a01 cmp r2, #1 80002f8: fa03 fc0e lsl.w ip, r3, lr 80002fc: bf28 it cs 80002fe: f04c 0c02 orrcs.w ip, ip, #2 8000302: fa43 f305 asr.w r3, r3, r5 8000306: 18c0 adds r0, r0, r3 8000308: eb51 71e3 adcs.w r1, r1, r3, asr #31 800030c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000310: d507 bpl.n 8000322 <__adddf3+0xe6> 8000312: f04f 0e00 mov.w lr, #0 8000316: f1dc 0c00 rsbs ip, ip, #0 800031a: eb7e 0000 sbcs.w r0, lr, r0 800031e: eb6e 0101 sbc.w r1, lr, r1 8000322: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 8000326: d31b bcc.n 8000360 <__adddf3+0x124> 8000328: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 800032c: d30c bcc.n 8000348 <__adddf3+0x10c> 800032e: 0849 lsrs r1, r1, #1 8000330: ea5f 0030 movs.w r0, r0, rrx 8000334: ea4f 0c3c mov.w ip, ip, rrx 8000338: f104 0401 add.w r4, r4, #1 800033c: ea4f 5244 mov.w r2, r4, lsl #21 8000340: f512 0f80 cmn.w r2, #4194304 @ 0x400000 8000344: f080 809a bcs.w 800047c <__adddf3+0x240> 8000348: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 800034c: bf08 it eq 800034e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000352: f150 0000 adcs.w r0, r0, #0 8000356: eb41 5104 adc.w r1, r1, r4, lsl #20 800035a: ea41 0105 orr.w r1, r1, r5 800035e: bd30 pop {r4, r5, pc} 8000360: ea5f 0c4c movs.w ip, ip, lsl #1 8000364: 4140 adcs r0, r0 8000366: eb41 0101 adc.w r1, r1, r1 800036a: 3c01 subs r4, #1 800036c: bf28 it cs 800036e: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 8000372: d2e9 bcs.n 8000348 <__adddf3+0x10c> 8000374: f091 0f00 teq r1, #0 8000378: bf04 itt eq 800037a: 4601 moveq r1, r0 800037c: 2000 moveq r0, #0 800037e: fab1 f381 clz r3, r1 8000382: bf08 it eq 8000384: 3320 addeq r3, #32 8000386: f1a3 030b sub.w r3, r3, #11 800038a: f1b3 0220 subs.w r2, r3, #32 800038e: da0c bge.n 80003aa <__adddf3+0x16e> 8000390: 320c adds r2, #12 8000392: dd08 ble.n 80003a6 <__adddf3+0x16a> 8000394: f102 0c14 add.w ip, r2, #20 8000398: f1c2 020c rsb r2, r2, #12 800039c: fa01 f00c lsl.w r0, r1, ip 80003a0: fa21 f102 lsr.w r1, r1, r2 80003a4: e00c b.n 80003c0 <__adddf3+0x184> 80003a6: f102 0214 add.w r2, r2, #20 80003aa: bfd8 it le 80003ac: f1c2 0c20 rsble ip, r2, #32 80003b0: fa01 f102 lsl.w r1, r1, r2 80003b4: fa20 fc0c lsr.w ip, r0, ip 80003b8: bfdc itt le 80003ba: ea41 010c orrle.w r1, r1, ip 80003be: 4090 lslle r0, r2 80003c0: 1ae4 subs r4, r4, r3 80003c2: bfa2 ittt ge 80003c4: eb01 5104 addge.w r1, r1, r4, lsl #20 80003c8: 4329 orrge r1, r5 80003ca: bd30 popge {r4, r5, pc} 80003cc: ea6f 0404 mvn.w r4, r4 80003d0: 3c1f subs r4, #31 80003d2: da1c bge.n 800040e <__adddf3+0x1d2> 80003d4: 340c adds r4, #12 80003d6: dc0e bgt.n 80003f6 <__adddf3+0x1ba> 80003d8: f104 0414 add.w r4, r4, #20 80003dc: f1c4 0220 rsb r2, r4, #32 80003e0: fa20 f004 lsr.w r0, r0, r4 80003e4: fa01 f302 lsl.w r3, r1, r2 80003e8: ea40 0003 orr.w r0, r0, r3 80003ec: fa21 f304 lsr.w r3, r1, r4 80003f0: ea45 0103 orr.w r1, r5, r3 80003f4: bd30 pop {r4, r5, pc} 80003f6: f1c4 040c rsb r4, r4, #12 80003fa: f1c4 0220 rsb r2, r4, #32 80003fe: fa20 f002 lsr.w r0, r0, r2 8000402: fa01 f304 lsl.w r3, r1, r4 8000406: ea40 0003 orr.w r0, r0, r3 800040a: 4629 mov r1, r5 800040c: bd30 pop {r4, r5, pc} 800040e: fa21 f004 lsr.w r0, r1, r4 8000412: 4629 mov r1, r5 8000414: bd30 pop {r4, r5, pc} 8000416: f094 0f00 teq r4, #0 800041a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 800041e: bf06 itte eq 8000420: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 8000424: 3401 addeq r4, #1 8000426: 3d01 subne r5, #1 8000428: e74e b.n 80002c8 <__adddf3+0x8c> 800042a: ea7f 5c64 mvns.w ip, r4, asr #21 800042e: bf18 it ne 8000430: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000434: d029 beq.n 800048a <__adddf3+0x24e> 8000436: ea94 0f05 teq r4, r5 800043a: bf08 it eq 800043c: ea90 0f02 teqeq r0, r2 8000440: d005 beq.n 800044e <__adddf3+0x212> 8000442: ea54 0c00 orrs.w ip, r4, r0 8000446: bf04 itt eq 8000448: 4619 moveq r1, r3 800044a: 4610 moveq r0, r2 800044c: bd30 pop {r4, r5, pc} 800044e: ea91 0f03 teq r1, r3 8000452: bf1e ittt ne 8000454: 2100 movne r1, #0 8000456: 2000 movne r0, #0 8000458: bd30 popne {r4, r5, pc} 800045a: ea5f 5c54 movs.w ip, r4, lsr #21 800045e: d105 bne.n 800046c <__adddf3+0x230> 8000460: 0040 lsls r0, r0, #1 8000462: 4149 adcs r1, r1 8000464: bf28 it cs 8000466: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 800046a: bd30 pop {r4, r5, pc} 800046c: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 8000470: bf3c itt cc 8000472: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 8000476: bd30 popcc {r4, r5, pc} 8000478: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 800047c: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 8000480: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8000484: f04f 0000 mov.w r0, #0 8000488: bd30 pop {r4, r5, pc} 800048a: ea7f 5c64 mvns.w ip, r4, asr #21 800048e: bf1a itte ne 8000490: 4619 movne r1, r3 8000492: 4610 movne r0, r2 8000494: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000498: bf1c itt ne 800049a: 460b movne r3, r1 800049c: 4602 movne r2, r0 800049e: ea50 3401 orrs.w r4, r0, r1, lsl #12 80004a2: bf06 itte eq 80004a4: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80004a8: ea91 0f03 teqeq r1, r3 80004ac: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 80004b0: bd30 pop {r4, r5, pc} 80004b2: bf00 nop 080004b4 <__aeabi_ui2d>: 80004b4: f090 0f00 teq r0, #0 80004b8: bf04 itt eq 80004ba: 2100 moveq r1, #0 80004bc: 4770 bxeq lr 80004be: b530 push {r4, r5, lr} 80004c0: f44f 6480 mov.w r4, #1024 @ 0x400 80004c4: f104 0432 add.w r4, r4, #50 @ 0x32 80004c8: f04f 0500 mov.w r5, #0 80004cc: f04f 0100 mov.w r1, #0 80004d0: e750 b.n 8000374 <__adddf3+0x138> 80004d2: bf00 nop 080004d4 <__aeabi_i2d>: 80004d4: f090 0f00 teq r0, #0 80004d8: bf04 itt eq 80004da: 2100 moveq r1, #0 80004dc: 4770 bxeq lr 80004de: b530 push {r4, r5, lr} 80004e0: f44f 6480 mov.w r4, #1024 @ 0x400 80004e4: f104 0432 add.w r4, r4, #50 @ 0x32 80004e8: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 80004ec: bf48 it mi 80004ee: 4240 negmi r0, r0 80004f0: f04f 0100 mov.w r1, #0 80004f4: e73e b.n 8000374 <__adddf3+0x138> 80004f6: bf00 nop 080004f8 <__aeabi_f2d>: 80004f8: 0042 lsls r2, r0, #1 80004fa: ea4f 01e2 mov.w r1, r2, asr #3 80004fe: ea4f 0131 mov.w r1, r1, rrx 8000502: ea4f 7002 mov.w r0, r2, lsl #28 8000506: bf1f itttt ne 8000508: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 800050c: f093 4f7f teqne r3, #4278190080 @ 0xff000000 8000510: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 8000514: 4770 bxne lr 8000516: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 800051a: bf08 it eq 800051c: 4770 bxeq lr 800051e: f093 4f7f teq r3, #4278190080 @ 0xff000000 8000522: bf04 itt eq 8000524: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 8000528: 4770 bxeq lr 800052a: b530 push {r4, r5, lr} 800052c: f44f 7460 mov.w r4, #896 @ 0x380 8000530: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 8000534: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8000538: e71c b.n 8000374 <__adddf3+0x138> 800053a: bf00 nop 0800053c <__aeabi_ul2d>: 800053c: ea50 0201 orrs.w r2, r0, r1 8000540: bf08 it eq 8000542: 4770 bxeq lr 8000544: b530 push {r4, r5, lr} 8000546: f04f 0500 mov.w r5, #0 800054a: e00a b.n 8000562 <__aeabi_l2d+0x16> 0800054c <__aeabi_l2d>: 800054c: ea50 0201 orrs.w r2, r0, r1 8000550: bf08 it eq 8000552: 4770 bxeq lr 8000554: b530 push {r4, r5, lr} 8000556: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 800055a: d502 bpl.n 8000562 <__aeabi_l2d+0x16> 800055c: 4240 negs r0, r0 800055e: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000562: f44f 6480 mov.w r4, #1024 @ 0x400 8000566: f104 0432 add.w r4, r4, #50 @ 0x32 800056a: ea5f 5c91 movs.w ip, r1, lsr #22 800056e: f43f aed8 beq.w 8000322 <__adddf3+0xe6> 8000572: f04f 0203 mov.w r2, #3 8000576: ea5f 0cdc movs.w ip, ip, lsr #3 800057a: bf18 it ne 800057c: 3203 addne r2, #3 800057e: ea5f 0cdc movs.w ip, ip, lsr #3 8000582: bf18 it ne 8000584: 3203 addne r2, #3 8000586: eb02 02dc add.w r2, r2, ip, lsr #3 800058a: f1c2 0320 rsb r3, r2, #32 800058e: fa00 fc03 lsl.w ip, r0, r3 8000592: fa20 f002 lsr.w r0, r0, r2 8000596: fa01 fe03 lsl.w lr, r1, r3 800059a: ea40 000e orr.w r0, r0, lr 800059e: fa21 f102 lsr.w r1, r1, r2 80005a2: 4414 add r4, r2 80005a4: e6bd b.n 8000322 <__adddf3+0xe6> 80005a6: bf00 nop 080005a8 <__aeabi_dmul>: 80005a8: b570 push {r4, r5, r6, lr} 80005aa: f04f 0cff mov.w ip, #255 @ 0xff 80005ae: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 80005b2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80005b6: bf1d ittte ne 80005b8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005bc: ea94 0f0c teqne r4, ip 80005c0: ea95 0f0c teqne r5, ip 80005c4: f000 f8de bleq 8000784 <__aeabi_dmul+0x1dc> 80005c8: 442c add r4, r5 80005ca: ea81 0603 eor.w r6, r1, r3 80005ce: ea21 514c bic.w r1, r1, ip, lsl #21 80005d2: ea23 534c bic.w r3, r3, ip, lsl #21 80005d6: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005da: bf18 it ne 80005dc: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005e0: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 80005e4: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80005e8: d038 beq.n 800065c <__aeabi_dmul+0xb4> 80005ea: fba0 ce02 umull ip, lr, r0, r2 80005ee: f04f 0500 mov.w r5, #0 80005f2: fbe1 e502 umlal lr, r5, r1, r2 80005f6: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 80005fa: fbe0 e503 umlal lr, r5, r0, r3 80005fe: f04f 0600 mov.w r6, #0 8000602: fbe1 5603 umlal r5, r6, r1, r3 8000606: f09c 0f00 teq ip, #0 800060a: bf18 it ne 800060c: f04e 0e01 orrne.w lr, lr, #1 8000610: f1a4 04ff sub.w r4, r4, #255 @ 0xff 8000614: f5b6 7f00 cmp.w r6, #512 @ 0x200 8000618: f564 7440 sbc.w r4, r4, #768 @ 0x300 800061c: d204 bcs.n 8000628 <__aeabi_dmul+0x80> 800061e: ea5f 0e4e movs.w lr, lr, lsl #1 8000622: 416d adcs r5, r5 8000624: eb46 0606 adc.w r6, r6, r6 8000628: ea42 21c6 orr.w r1, r2, r6, lsl #11 800062c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000630: ea4f 20c5 mov.w r0, r5, lsl #11 8000634: ea40 505e orr.w r0, r0, lr, lsr #21 8000638: ea4f 2ece mov.w lr, lr, lsl #11 800063c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 8000640: bf88 it hi 8000642: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 8000646: d81e bhi.n 8000686 <__aeabi_dmul+0xde> 8000648: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 800064c: bf08 it eq 800064e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000652: f150 0000 adcs.w r0, r0, #0 8000656: eb41 5104 adc.w r1, r1, r4, lsl #20 800065a: bd70 pop {r4, r5, r6, pc} 800065c: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 8000660: ea46 0101 orr.w r1, r6, r1 8000664: ea40 0002 orr.w r0, r0, r2 8000668: ea81 0103 eor.w r1, r1, r3 800066c: ebb4 045c subs.w r4, r4, ip, lsr #1 8000670: bfc2 ittt gt 8000672: ebd4 050c rsbsgt r5, r4, ip 8000676: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800067a: bd70 popgt {r4, r5, r6, pc} 800067c: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000680: f04f 0e00 mov.w lr, #0 8000684: 3c01 subs r4, #1 8000686: f300 80ab bgt.w 80007e0 <__aeabi_dmul+0x238> 800068a: f114 0f36 cmn.w r4, #54 @ 0x36 800068e: bfde ittt le 8000690: 2000 movle r0, #0 8000692: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 8000696: bd70 pople {r4, r5, r6, pc} 8000698: f1c4 0400 rsb r4, r4, #0 800069c: 3c20 subs r4, #32 800069e: da35 bge.n 800070c <__aeabi_dmul+0x164> 80006a0: 340c adds r4, #12 80006a2: dc1b bgt.n 80006dc <__aeabi_dmul+0x134> 80006a4: f104 0414 add.w r4, r4, #20 80006a8: f1c4 0520 rsb r5, r4, #32 80006ac: fa00 f305 lsl.w r3, r0, r5 80006b0: fa20 f004 lsr.w r0, r0, r4 80006b4: fa01 f205 lsl.w r2, r1, r5 80006b8: ea40 0002 orr.w r0, r0, r2 80006bc: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 80006c0: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 80006c4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006c8: fa21 f604 lsr.w r6, r1, r4 80006cc: eb42 0106 adc.w r1, r2, r6 80006d0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006d4: bf08 it eq 80006d6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006da: bd70 pop {r4, r5, r6, pc} 80006dc: f1c4 040c rsb r4, r4, #12 80006e0: f1c4 0520 rsb r5, r4, #32 80006e4: fa00 f304 lsl.w r3, r0, r4 80006e8: fa20 f005 lsr.w r0, r0, r5 80006ec: fa01 f204 lsl.w r2, r1, r4 80006f0: ea40 0002 orr.w r0, r0, r2 80006f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80006f8: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006fc: f141 0100 adc.w r1, r1, #0 8000700: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000704: bf08 it eq 8000706: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800070a: bd70 pop {r4, r5, r6, pc} 800070c: f1c4 0520 rsb r5, r4, #32 8000710: fa00 f205 lsl.w r2, r0, r5 8000714: ea4e 0e02 orr.w lr, lr, r2 8000718: fa20 f304 lsr.w r3, r0, r4 800071c: fa01 f205 lsl.w r2, r1, r5 8000720: ea43 0302 orr.w r3, r3, r2 8000724: fa21 f004 lsr.w r0, r1, r4 8000728: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 800072c: fa21 f204 lsr.w r2, r1, r4 8000730: ea20 0002 bic.w r0, r0, r2 8000734: eb00 70d3 add.w r0, r0, r3, lsr #31 8000738: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800073c: bf08 it eq 800073e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000742: bd70 pop {r4, r5, r6, pc} 8000744: f094 0f00 teq r4, #0 8000748: d10f bne.n 800076a <__aeabi_dmul+0x1c2> 800074a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 800074e: 0040 lsls r0, r0, #1 8000750: eb41 0101 adc.w r1, r1, r1 8000754: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000758: bf08 it eq 800075a: 3c01 subeq r4, #1 800075c: d0f7 beq.n 800074e <__aeabi_dmul+0x1a6> 800075e: ea41 0106 orr.w r1, r1, r6 8000762: f095 0f00 teq r5, #0 8000766: bf18 it ne 8000768: 4770 bxne lr 800076a: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 800076e: 0052 lsls r2, r2, #1 8000770: eb43 0303 adc.w r3, r3, r3 8000774: f413 1f80 tst.w r3, #1048576 @ 0x100000 8000778: bf08 it eq 800077a: 3d01 subeq r5, #1 800077c: d0f7 beq.n 800076e <__aeabi_dmul+0x1c6> 800077e: ea43 0306 orr.w r3, r3, r6 8000782: 4770 bx lr 8000784: ea94 0f0c teq r4, ip 8000788: ea0c 5513 and.w r5, ip, r3, lsr #20 800078c: bf18 it ne 800078e: ea95 0f0c teqne r5, ip 8000792: d00c beq.n 80007ae <__aeabi_dmul+0x206> 8000794: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000798: bf18 it ne 800079a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 800079e: d1d1 bne.n 8000744 <__aeabi_dmul+0x19c> 80007a0: ea81 0103 eor.w r1, r1, r3 80007a4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80007a8: f04f 0000 mov.w r0, #0 80007ac: bd70 pop {r4, r5, r6, pc} 80007ae: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007b2: bf06 itte eq 80007b4: 4610 moveq r0, r2 80007b6: 4619 moveq r1, r3 80007b8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007bc: d019 beq.n 80007f2 <__aeabi_dmul+0x24a> 80007be: ea94 0f0c teq r4, ip 80007c2: d102 bne.n 80007ca <__aeabi_dmul+0x222> 80007c4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007c8: d113 bne.n 80007f2 <__aeabi_dmul+0x24a> 80007ca: ea95 0f0c teq r5, ip 80007ce: d105 bne.n 80007dc <__aeabi_dmul+0x234> 80007d0: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007d4: bf1c itt ne 80007d6: 4610 movne r0, r2 80007d8: 4619 movne r1, r3 80007da: d10a bne.n 80007f2 <__aeabi_dmul+0x24a> 80007dc: ea81 0103 eor.w r1, r1, r3 80007e0: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 80007e4: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80007e8: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80007ec: f04f 0000 mov.w r0, #0 80007f0: bd70 pop {r4, r5, r6, pc} 80007f2: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 80007f6: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 80007fa: bd70 pop {r4, r5, r6, pc} 080007fc <__aeabi_ddiv>: 80007fc: b570 push {r4, r5, r6, lr} 80007fe: f04f 0cff mov.w ip, #255 @ 0xff 8000802: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 8000806: ea1c 5411 ands.w r4, ip, r1, lsr #20 800080a: bf1d ittte ne 800080c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000810: ea94 0f0c teqne r4, ip 8000814: ea95 0f0c teqne r5, ip 8000818: f000 f8a7 bleq 800096a <__aeabi_ddiv+0x16e> 800081c: eba4 0405 sub.w r4, r4, r5 8000820: ea81 0e03 eor.w lr, r1, r3 8000824: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000828: ea4f 3101 mov.w r1, r1, lsl #12 800082c: f000 8088 beq.w 8000940 <__aeabi_ddiv+0x144> 8000830: ea4f 3303 mov.w r3, r3, lsl #12 8000834: f04f 5580 mov.w r5, #268435456 @ 0x10000000 8000838: ea45 1313 orr.w r3, r5, r3, lsr #4 800083c: ea43 6312 orr.w r3, r3, r2, lsr #24 8000840: ea4f 2202 mov.w r2, r2, lsl #8 8000844: ea45 1511 orr.w r5, r5, r1, lsr #4 8000848: ea45 6510 orr.w r5, r5, r0, lsr #24 800084c: ea4f 2600 mov.w r6, r0, lsl #8 8000850: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000 8000854: 429d cmp r5, r3 8000856: bf08 it eq 8000858: 4296 cmpeq r6, r2 800085a: f144 04fd adc.w r4, r4, #253 @ 0xfd 800085e: f504 7440 add.w r4, r4, #768 @ 0x300 8000862: d202 bcs.n 800086a <__aeabi_ddiv+0x6e> 8000864: 085b lsrs r3, r3, #1 8000866: ea4f 0232 mov.w r2, r2, rrx 800086a: 1ab6 subs r6, r6, r2 800086c: eb65 0503 sbc.w r5, r5, r3 8000870: 085b lsrs r3, r3, #1 8000872: ea4f 0232 mov.w r2, r2, rrx 8000876: f44f 1080 mov.w r0, #1048576 @ 0x100000 800087a: f44f 2c00 mov.w ip, #524288 @ 0x80000 800087e: ebb6 0e02 subs.w lr, r6, r2 8000882: eb75 0e03 sbcs.w lr, r5, r3 8000886: bf22 ittt cs 8000888: 1ab6 subcs r6, r6, r2 800088a: 4675 movcs r5, lr 800088c: ea40 000c orrcs.w r0, r0, ip 8000890: 085b lsrs r3, r3, #1 8000892: ea4f 0232 mov.w r2, r2, rrx 8000896: ebb6 0e02 subs.w lr, r6, r2 800089a: eb75 0e03 sbcs.w lr, r5, r3 800089e: bf22 ittt cs 80008a0: 1ab6 subcs r6, r6, r2 80008a2: 4675 movcs r5, lr 80008a4: ea40 005c orrcs.w r0, r0, ip, lsr #1 80008a8: 085b lsrs r3, r3, #1 80008aa: ea4f 0232 mov.w r2, r2, rrx 80008ae: ebb6 0e02 subs.w lr, r6, r2 80008b2: eb75 0e03 sbcs.w lr, r5, r3 80008b6: bf22 ittt cs 80008b8: 1ab6 subcs r6, r6, r2 80008ba: 4675 movcs r5, lr 80008bc: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008c0: 085b lsrs r3, r3, #1 80008c2: ea4f 0232 mov.w r2, r2, rrx 80008c6: ebb6 0e02 subs.w lr, r6, r2 80008ca: eb75 0e03 sbcs.w lr, r5, r3 80008ce: bf22 ittt cs 80008d0: 1ab6 subcs r6, r6, r2 80008d2: 4675 movcs r5, lr 80008d4: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008d8: ea55 0e06 orrs.w lr, r5, r6 80008dc: d018 beq.n 8000910 <__aeabi_ddiv+0x114> 80008de: ea4f 1505 mov.w r5, r5, lsl #4 80008e2: ea45 7516 orr.w r5, r5, r6, lsr #28 80008e6: ea4f 1606 mov.w r6, r6, lsl #4 80008ea: ea4f 03c3 mov.w r3, r3, lsl #3 80008ee: ea43 7352 orr.w r3, r3, r2, lsr #29 80008f2: ea4f 02c2 mov.w r2, r2, lsl #3 80008f6: ea5f 1c1c movs.w ip, ip, lsr #4 80008fa: d1c0 bne.n 800087e <__aeabi_ddiv+0x82> 80008fc: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000900: d10b bne.n 800091a <__aeabi_ddiv+0x11e> 8000902: ea41 0100 orr.w r1, r1, r0 8000906: f04f 0000 mov.w r0, #0 800090a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000 800090e: e7b6 b.n 800087e <__aeabi_ddiv+0x82> 8000910: f411 1f80 tst.w r1, #1048576 @ 0x100000 8000914: bf04 itt eq 8000916: 4301 orreq r1, r0 8000918: 2000 moveq r0, #0 800091a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd 800091e: bf88 it hi 8000920: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 8000924: f63f aeaf bhi.w 8000686 <__aeabi_dmul+0xde> 8000928: ebb5 0c03 subs.w ip, r5, r3 800092c: bf04 itt eq 800092e: ebb6 0c02 subseq.w ip, r6, r2 8000932: ea5f 0c50 movseq.w ip, r0, lsr #1 8000936: f150 0000 adcs.w r0, r0, #0 800093a: eb41 5104 adc.w r1, r1, r4, lsl #20 800093e: bd70 pop {r4, r5, r6, pc} 8000940: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000 8000944: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000948: eb14 045c adds.w r4, r4, ip, lsr #1 800094c: bfc2 ittt gt 800094e: ebd4 050c rsbsgt r5, r4, ip 8000952: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000956: bd70 popgt {r4, r5, r6, pc} 8000958: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 800095c: f04f 0e00 mov.w lr, #0 8000960: 3c01 subs r4, #1 8000962: e690 b.n 8000686 <__aeabi_dmul+0xde> 8000964: ea45 0e06 orr.w lr, r5, r6 8000968: e68d b.n 8000686 <__aeabi_dmul+0xde> 800096a: ea0c 5513 and.w r5, ip, r3, lsr #20 800096e: ea94 0f0c teq r4, ip 8000972: bf08 it eq 8000974: ea95 0f0c teqeq r5, ip 8000978: f43f af3b beq.w 80007f2 <__aeabi_dmul+0x24a> 800097c: ea94 0f0c teq r4, ip 8000980: d10a bne.n 8000998 <__aeabi_ddiv+0x19c> 8000982: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000986: f47f af34 bne.w 80007f2 <__aeabi_dmul+0x24a> 800098a: ea95 0f0c teq r5, ip 800098e: f47f af25 bne.w 80007dc <__aeabi_dmul+0x234> 8000992: 4610 mov r0, r2 8000994: 4619 mov r1, r3 8000996: e72c b.n 80007f2 <__aeabi_dmul+0x24a> 8000998: ea95 0f0c teq r5, ip 800099c: d106 bne.n 80009ac <__aeabi_ddiv+0x1b0> 800099e: ea52 3503 orrs.w r5, r2, r3, lsl #12 80009a2: f43f aefd beq.w 80007a0 <__aeabi_dmul+0x1f8> 80009a6: 4610 mov r0, r2 80009a8: 4619 mov r1, r3 80009aa: e722 b.n 80007f2 <__aeabi_dmul+0x24a> 80009ac: ea50 0641 orrs.w r6, r0, r1, lsl #1 80009b0: bf18 it ne 80009b2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80009b6: f47f aec5 bne.w 8000744 <__aeabi_dmul+0x19c> 80009ba: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009be: f47f af0d bne.w 80007dc <__aeabi_dmul+0x234> 80009c2: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009c6: f47f aeeb bne.w 80007a0 <__aeabi_dmul+0x1f8> 80009ca: e712 b.n 80007f2 <__aeabi_dmul+0x24a> 080009cc <__gedf2>: 80009cc: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff 80009d0: e006 b.n 80009e0 <__cmpdf2+0x4> 80009d2: bf00 nop 080009d4 <__ledf2>: 80009d4: f04f 0c01 mov.w ip, #1 80009d8: e002 b.n 80009e0 <__cmpdf2+0x4> 80009da: bf00 nop 080009dc <__cmpdf2>: 80009dc: f04f 0c01 mov.w ip, #1 80009e0: f84d cd04 str.w ip, [sp, #-4]! 80009e4: ea4f 0c41 mov.w ip, r1, lsl #1 80009e8: ea7f 5c6c mvns.w ip, ip, asr #21 80009ec: ea4f 0c43 mov.w ip, r3, lsl #1 80009f0: bf18 it ne 80009f2: ea7f 5c6c mvnsne.w ip, ip, asr #21 80009f6: d01b beq.n 8000a30 <__cmpdf2+0x54> 80009f8: b001 add sp, #4 80009fa: ea50 0c41 orrs.w ip, r0, r1, lsl #1 80009fe: bf0c ite eq 8000a00: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8000a04: ea91 0f03 teqne r1, r3 8000a08: bf02 ittt eq 8000a0a: ea90 0f02 teqeq r0, r2 8000a0e: 2000 moveq r0, #0 8000a10: 4770 bxeq lr 8000a12: f110 0f00 cmn.w r0, #0 8000a16: ea91 0f03 teq r1, r3 8000a1a: bf58 it pl 8000a1c: 4299 cmppl r1, r3 8000a1e: bf08 it eq 8000a20: 4290 cmpeq r0, r2 8000a22: bf2c ite cs 8000a24: 17d8 asrcs r0, r3, #31 8000a26: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a2a: f040 0001 orr.w r0, r0, #1 8000a2e: 4770 bx lr 8000a30: ea4f 0c41 mov.w ip, r1, lsl #1 8000a34: ea7f 5c6c mvns.w ip, ip, asr #21 8000a38: d102 bne.n 8000a40 <__cmpdf2+0x64> 8000a3a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a3e: d107 bne.n 8000a50 <__cmpdf2+0x74> 8000a40: ea4f 0c43 mov.w ip, r3, lsl #1 8000a44: ea7f 5c6c mvns.w ip, ip, asr #21 8000a48: d1d6 bne.n 80009f8 <__cmpdf2+0x1c> 8000a4a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a4e: d0d3 beq.n 80009f8 <__cmpdf2+0x1c> 8000a50: f85d 0b04 ldr.w r0, [sp], #4 8000a54: 4770 bx lr 8000a56: bf00 nop 08000a58 <__aeabi_cdrcmple>: 8000a58: 4684 mov ip, r0 8000a5a: 4610 mov r0, r2 8000a5c: 4662 mov r2, ip 8000a5e: 468c mov ip, r1 8000a60: 4619 mov r1, r3 8000a62: 4663 mov r3, ip 8000a64: e000 b.n 8000a68 <__aeabi_cdcmpeq> 8000a66: bf00 nop 08000a68 <__aeabi_cdcmpeq>: 8000a68: b501 push {r0, lr} 8000a6a: f7ff ffb7 bl 80009dc <__cmpdf2> 8000a6e: 2800 cmp r0, #0 8000a70: bf48 it mi 8000a72: f110 0f00 cmnmi.w r0, #0 8000a76: bd01 pop {r0, pc} 08000a78 <__aeabi_dcmpeq>: 8000a78: f84d ed08 str.w lr, [sp, #-8]! 8000a7c: f7ff fff4 bl 8000a68 <__aeabi_cdcmpeq> 8000a80: bf0c ite eq 8000a82: 2001 moveq r0, #1 8000a84: 2000 movne r0, #0 8000a86: f85d fb08 ldr.w pc, [sp], #8 8000a8a: bf00 nop 08000a8c <__aeabi_dcmplt>: 8000a8c: f84d ed08 str.w lr, [sp, #-8]! 8000a90: f7ff ffea bl 8000a68 <__aeabi_cdcmpeq> 8000a94: bf34 ite cc 8000a96: 2001 movcc r0, #1 8000a98: 2000 movcs r0, #0 8000a9a: f85d fb08 ldr.w pc, [sp], #8 8000a9e: bf00 nop 08000aa0 <__aeabi_dcmple>: 8000aa0: f84d ed08 str.w lr, [sp, #-8]! 8000aa4: f7ff ffe0 bl 8000a68 <__aeabi_cdcmpeq> 8000aa8: bf94 ite ls 8000aaa: 2001 movls r0, #1 8000aac: 2000 movhi r0, #0 8000aae: f85d fb08 ldr.w pc, [sp], #8 8000ab2: bf00 nop 08000ab4 <__aeabi_dcmpge>: 8000ab4: f84d ed08 str.w lr, [sp, #-8]! 8000ab8: f7ff ffce bl 8000a58 <__aeabi_cdrcmple> 8000abc: bf94 ite ls 8000abe: 2001 movls r0, #1 8000ac0: 2000 movhi r0, #0 8000ac2: f85d fb08 ldr.w pc, [sp], #8 8000ac6: bf00 nop 08000ac8 <__aeabi_dcmpgt>: 8000ac8: f84d ed08 str.w lr, [sp, #-8]! 8000acc: f7ff ffc4 bl 8000a58 <__aeabi_cdrcmple> 8000ad0: bf34 ite cc 8000ad2: 2001 movcc r0, #1 8000ad4: 2000 movcs r0, #0 8000ad6: f85d fb08 ldr.w pc, [sp], #8 8000ada: bf00 nop 08000adc <__aeabi_dcmpun>: 8000adc: ea4f 0c41 mov.w ip, r1, lsl #1 8000ae0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ae4: d102 bne.n 8000aec <__aeabi_dcmpun+0x10> 8000ae6: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000aea: d10a bne.n 8000b02 <__aeabi_dcmpun+0x26> 8000aec: ea4f 0c43 mov.w ip, r3, lsl #1 8000af0: ea7f 5c6c mvns.w ip, ip, asr #21 8000af4: d102 bne.n 8000afc <__aeabi_dcmpun+0x20> 8000af6: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000afa: d102 bne.n 8000b02 <__aeabi_dcmpun+0x26> 8000afc: f04f 0000 mov.w r0, #0 8000b00: 4770 bx lr 8000b02: f04f 0001 mov.w r0, #1 8000b06: 4770 bx lr 08000b08 <__aeabi_d2iz>: 8000b08: ea4f 0241 mov.w r2, r1, lsl #1 8000b0c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8000b10: d215 bcs.n 8000b3e <__aeabi_d2iz+0x36> 8000b12: d511 bpl.n 8000b38 <__aeabi_d2iz+0x30> 8000b14: f46f 7378 mvn.w r3, #992 @ 0x3e0 8000b18: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b1c: d912 bls.n 8000b44 <__aeabi_d2iz+0x3c> 8000b1e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b22: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8000b26: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b2a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 8000b2e: fa23 f002 lsr.w r0, r3, r2 8000b32: bf18 it ne 8000b34: 4240 negne r0, r0 8000b36: 4770 bx lr 8000b38: f04f 0000 mov.w r0, #0 8000b3c: 4770 bx lr 8000b3e: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b42: d105 bne.n 8000b50 <__aeabi_d2iz+0x48> 8000b44: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000 8000b48: bf08 it eq 8000b4a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000 8000b4e: 4770 bx lr 8000b50: f04f 0000 mov.w r0, #0 8000b54: 4770 bx lr 8000b56: bf00 nop 08000b58 <__aeabi_d2uiz>: 8000b58: 004a lsls r2, r1, #1 8000b5a: d211 bcs.n 8000b80 <__aeabi_d2uiz+0x28> 8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 8000b60: d211 bcs.n 8000b86 <__aeabi_d2uiz+0x2e> 8000b62: d50d bpl.n 8000b80 <__aeabi_d2uiz+0x28> 8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0 8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b6c: d40e bmi.n 8000b8c <__aeabi_d2uiz+0x34> 8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b7a: fa23 f002 lsr.w r0, r3, r2 8000b7e: 4770 bx lr 8000b80: f04f 0000 mov.w r0, #0 8000b84: 4770 bx lr 8000b86: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b8a: d102 bne.n 8000b92 <__aeabi_d2uiz+0x3a> 8000b8c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8000b90: 4770 bx lr 8000b92: f04f 0000 mov.w r0, #0 8000b96: 4770 bx lr 08000b98 <__aeabi_d2f>: 8000b98: ea4f 0241 mov.w r2, r1, lsl #1 8000b9c: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000 8000ba0: bf24 itt cs 8000ba2: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000 8000ba6: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000 8000baa: d90d bls.n 8000bc8 <__aeabi_d2f+0x30> 8000bac: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000 8000bb0: ea4f 02c0 mov.w r2, r0, lsl #3 8000bb4: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000bb8: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000 8000bbc: eb40 0083 adc.w r0, r0, r3, lsl #2 8000bc0: bf08 it eq 8000bc2: f020 0001 biceq.w r0, r0, #1 8000bc6: 4770 bx lr 8000bc8: f011 4f80 tst.w r1, #1073741824 @ 0x40000000 8000bcc: d121 bne.n 8000c12 <__aeabi_d2f+0x7a> 8000bce: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000 8000bd2: bfbc itt lt 8000bd4: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000 8000bd8: 4770 bxlt lr 8000bda: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 8000bde: ea4f 5252 mov.w r2, r2, lsr #21 8000be2: f1c2 0218 rsb r2, r2, #24 8000be6: f1c2 0c20 rsb ip, r2, #32 8000bea: fa10 f30c lsls.w r3, r0, ip 8000bee: fa20 f002 lsr.w r0, r0, r2 8000bf2: bf18 it ne 8000bf4: f040 0001 orrne.w r0, r0, #1 8000bf8: ea4f 23c1 mov.w r3, r1, lsl #11 8000bfc: ea4f 23d3 mov.w r3, r3, lsr #11 8000c00: fa03 fc0c lsl.w ip, r3, ip 8000c04: ea40 000c orr.w r0, r0, ip 8000c08: fa23 f302 lsr.w r3, r3, r2 8000c0c: ea4f 0343 mov.w r3, r3, lsl #1 8000c10: e7cc b.n 8000bac <__aeabi_d2f+0x14> 8000c12: ea7f 5362 mvns.w r3, r2, asr #21 8000c16: d107 bne.n 8000c28 <__aeabi_d2f+0x90> 8000c18: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000c1c: bf1e ittt ne 8000c1e: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000 8000c22: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000 8000c26: 4770 bxne lr 8000c28: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000 8000c2c: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000 8000c30: f440 0000 orr.w r0, r0, #8388608 @ 0x800000 8000c34: 4770 bx lr 8000c36: bf00 nop 08000c38 <__aeabi_d2lz>: 8000c38: b538 push {r3, r4, r5, lr} 8000c3a: 2200 movs r2, #0 8000c3c: 2300 movs r3, #0 8000c3e: 4604 mov r4, r0 8000c40: 460d mov r5, r1 8000c42: f7ff ff23 bl 8000a8c <__aeabi_dcmplt> 8000c46: b928 cbnz r0, 8000c54 <__aeabi_d2lz+0x1c> 8000c48: 4620 mov r0, r4 8000c4a: 4629 mov r1, r5 8000c4c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8000c50: f000 b80a b.w 8000c68 <__aeabi_d2ulz> 8000c54: 4620 mov r0, r4 8000c56: f105 4100 add.w r1, r5, #2147483648 @ 0x80000000 8000c5a: f000 f805 bl 8000c68 <__aeabi_d2ulz> 8000c5e: 4240 negs r0, r0 8000c60: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000c64: bd38 pop {r3, r4, r5, pc} 8000c66: bf00 nop 08000c68 <__aeabi_d2ulz>: 8000c68: b5d0 push {r4, r6, r7, lr} 8000c6a: 4b0c ldr r3, [pc, #48] @ (8000c9c <__aeabi_d2ulz+0x34>) 8000c6c: 2200 movs r2, #0 8000c6e: 4606 mov r6, r0 8000c70: 460f mov r7, r1 8000c72: f7ff fc99 bl 80005a8 <__aeabi_dmul> 8000c76: f7ff ff6f bl 8000b58 <__aeabi_d2uiz> 8000c7a: 4604 mov r4, r0 8000c7c: f7ff fc1a bl 80004b4 <__aeabi_ui2d> 8000c80: 4b07 ldr r3, [pc, #28] @ (8000ca0 <__aeabi_d2ulz+0x38>) 8000c82: 2200 movs r2, #0 8000c84: f7ff fc90 bl 80005a8 <__aeabi_dmul> 8000c88: 4602 mov r2, r0 8000c8a: 460b mov r3, r1 8000c8c: 4630 mov r0, r6 8000c8e: 4639 mov r1, r7 8000c90: f7ff fad2 bl 8000238 <__aeabi_dsub> 8000c94: f7ff ff60 bl 8000b58 <__aeabi_d2uiz> 8000c98: 4621 mov r1, r4 8000c9a: bdd0 pop {r4, r6, r7, pc} 8000c9c: 3df00000 .word 0x3df00000 8000ca0: 41f00000 .word 0x41f00000 08000ca4 : float invSqrt(float x); //==================================================================================================== // Functions void MadgwickAHRS_init (MadgwickAHRS_Filter* filter, float beta, float sample_freq) { 8000ca4: b480 push {r7} 8000ca6: b085 sub sp, #20 8000ca8: af00 add r7, sp, #0 8000caa: 60f8 str r0, [r7, #12] 8000cac: ed87 0a02 vstr s0, [r7, #8] 8000cb0: edc7 0a01 vstr s1, [r7, #4] filter->q[0] = 1.0f; // qw 8000cb4: 68fb ldr r3, [r7, #12] 8000cb6: f04f 527e mov.w r2, #1065353216 @ 0x3f800000 8000cba: 601a str r2, [r3, #0] filter->q[1] = 0.0f; // qx 8000cbc: 68fb ldr r3, [r7, #12] 8000cbe: f04f 0200 mov.w r2, #0 8000cc2: 605a str r2, [r3, #4] filter->q[2] = 0.0f; // qy 8000cc4: 68fb ldr r3, [r7, #12] 8000cc6: f04f 0200 mov.w r2, #0 8000cca: 609a str r2, [r3, #8] filter->q[3] = 0.0f; // qz 8000ccc: 68fb ldr r3, [r7, #12] 8000cce: f04f 0200 mov.w r2, #0 8000cd2: 60da str r2, [r3, #12] filter->beta = beta; 8000cd4: 68fb ldr r3, [r7, #12] 8000cd6: 68ba ldr r2, [r7, #8] 8000cd8: 611a str r2, [r3, #16] filter->sample_freq = sample_freq; 8000cda: 68fb ldr r3, [r7, #12] 8000cdc: 687a ldr r2, [r7, #4] 8000cde: 615a str r2, [r3, #20] } 8000ce0: bf00 nop 8000ce2: 3714 adds r7, #20 8000ce4: 46bd mov sp, r7 8000ce6: f85d 7b04 ldr.w r7, [sp], #4 8000cea: 4770 bx lr 08000cec : //--------------------------------------------------------------------------------------------------- // AHRS algorithm update void MadgwickAHRS_update(MadgwickAHRS_Filter* filter, float gx, float gy, float gz, float ax, float ay, float az, float mx, float my, float mz) { 8000cec: b580 push {r7, lr} 8000cee: b0b2 sub sp, #200 @ 0xc8 8000cf0: af00 add r7, sp, #0 8000cf2: 6278 str r0, [r7, #36] @ 0x24 8000cf4: ed87 0a08 vstr s0, [r7, #32] 8000cf8: edc7 0a07 vstr s1, [r7, #28] 8000cfc: ed87 1a06 vstr s2, [r7, #24] 8000d00: edc7 1a05 vstr s3, [r7, #20] 8000d04: ed87 2a04 vstr s4, [r7, #16] 8000d08: edc7 2a03 vstr s5, [r7, #12] 8000d0c: ed87 3a02 vstr s6, [r7, #8] 8000d10: edc7 3a01 vstr s7, [r7, #4] 8000d14: ed87 4a00 vstr s8, [r7] float q[4] = {filter->q[0], filter->q[1], filter->q[2], filter->q[3]}; 8000d18: 6a7b ldr r3, [r7, #36] @ 0x24 8000d1a: 681b ldr r3, [r3, #0] 8000d1c: 63bb str r3, [r7, #56] @ 0x38 8000d1e: 6a7b ldr r3, [r7, #36] @ 0x24 8000d20: 685b ldr r3, [r3, #4] 8000d22: 63fb str r3, [r7, #60] @ 0x3c 8000d24: 6a7b ldr r3, [r7, #36] @ 0x24 8000d26: 689b ldr r3, [r3, #8] 8000d28: 643b str r3, [r7, #64] @ 0x40 8000d2a: 6a7b ldr r3, [r7, #36] @ 0x24 8000d2c: 68db ldr r3, [r3, #12] 8000d2e: 647b str r3, [r7, #68] @ 0x44 float qDot[4]; float hx, hy; float _2q0mx, _2q0my, _2q0mz, _2q1mx, _2bx, _2bz, _4bx, _4bz, _2q0, _2q1, _2q2, _2q3, _2q0q2, _2q2q3, q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; // Use IMU algorithm if magnetometer measurement invalid (avoids NaN in magnetometer normalisation) if((mx == 0.0f) && (my == 0.0f) && (mz == 0.0f)) { 8000d30: edd7 7a02 vldr s15, [r7, #8] 8000d34: eef5 7a40 vcmp.f32 s15, #0.0 8000d38: eef1 fa10 vmrs APSR_nzcv, fpscr 8000d3c: d11e bne.n 8000d7c 8000d3e: edd7 7a01 vldr s15, [r7, #4] 8000d42: eef5 7a40 vcmp.f32 s15, #0.0 8000d46: eef1 fa10 vmrs APSR_nzcv, fpscr 8000d4a: d117 bne.n 8000d7c 8000d4c: edd7 7a00 vldr s15, [r7] 8000d50: eef5 7a40 vcmp.f32 s15, #0.0 8000d54: eef1 fa10 vmrs APSR_nzcv, fpscr 8000d58: d110 bne.n 8000d7c MadgwickAHRS_update_IMU(filter, gx, gy, gz, ax, ay, az); 8000d5a: edd7 2a03 vldr s5, [r7, #12] 8000d5e: ed97 2a04 vldr s4, [r7, #16] 8000d62: edd7 1a05 vldr s3, [r7, #20] 8000d66: ed97 1a06 vldr s2, [r7, #24] 8000d6a: edd7 0a07 vldr s1, [r7, #28] 8000d6e: ed97 0a08 vldr s0, [r7, #32] 8000d72: 6a78 ldr r0, [r7, #36] @ 0x24 8000d74: f000 feb2 bl 8001adc 8000d78: f000 bead b.w 8001ad6 return; } // Rate of change of quaternion from gyroscope qDot[0] = 0.5f * (-q[1] * gx - q[2] * gy - q[3] * gz); 8000d7c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000d80: eeb1 7a67 vneg.f32 s14, s15 8000d84: edd7 7a08 vldr s15, [r7, #32] 8000d88: ee27 7a27 vmul.f32 s14, s14, s15 8000d8c: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8000d90: edd7 7a07 vldr s15, [r7, #28] 8000d94: ee66 7aa7 vmul.f32 s15, s13, s15 8000d98: ee37 7a67 vsub.f32 s14, s14, s15 8000d9c: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8000da0: edd7 7a06 vldr s15, [r7, #24] 8000da4: ee66 7aa7 vmul.f32 s15, s13, s15 8000da8: ee77 7a67 vsub.f32 s15, s14, s15 8000dac: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8000db0: ee67 7a87 vmul.f32 s15, s15, s14 8000db4: edc7 7a0a vstr s15, [r7, #40] @ 0x28 qDot[1] = 0.5f * (q[0] * gx + q[2] * gz - q[3] * gy); 8000db8: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8000dbc: edd7 7a08 vldr s15, [r7, #32] 8000dc0: ee27 7a27 vmul.f32 s14, s14, s15 8000dc4: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8000dc8: edd7 7a06 vldr s15, [r7, #24] 8000dcc: ee66 7aa7 vmul.f32 s15, s13, s15 8000dd0: ee37 7a27 vadd.f32 s14, s14, s15 8000dd4: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8000dd8: edd7 7a07 vldr s15, [r7, #28] 8000ddc: ee66 7aa7 vmul.f32 s15, s13, s15 8000de0: ee77 7a67 vsub.f32 s15, s14, s15 8000de4: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8000de8: ee67 7a87 vmul.f32 s15, s15, s14 8000dec: edc7 7a0b vstr s15, [r7, #44] @ 0x2c qDot[2] = 0.5f * (q[0] * gy - q[1] * gz + q[3] * gx); 8000df0: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8000df4: edd7 7a07 vldr s15, [r7, #28] 8000df8: ee27 7a27 vmul.f32 s14, s14, s15 8000dfc: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8000e00: edd7 7a06 vldr s15, [r7, #24] 8000e04: ee66 7aa7 vmul.f32 s15, s13, s15 8000e08: ee37 7a67 vsub.f32 s14, s14, s15 8000e0c: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8000e10: edd7 7a08 vldr s15, [r7, #32] 8000e14: ee66 7aa7 vmul.f32 s15, s13, s15 8000e18: ee77 7a27 vadd.f32 s15, s14, s15 8000e1c: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8000e20: ee67 7a87 vmul.f32 s15, s15, s14 8000e24: edc7 7a0c vstr s15, [r7, #48] @ 0x30 qDot[3] = 0.5f * (q[0] * gz + q[1] * gy - q[2] * gx); 8000e28: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8000e2c: edd7 7a06 vldr s15, [r7, #24] 8000e30: ee27 7a27 vmul.f32 s14, s14, s15 8000e34: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8000e38: edd7 7a07 vldr s15, [r7, #28] 8000e3c: ee66 7aa7 vmul.f32 s15, s13, s15 8000e40: ee37 7a27 vadd.f32 s14, s14, s15 8000e44: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8000e48: edd7 7a08 vldr s15, [r7, #32] 8000e4c: ee66 7aa7 vmul.f32 s15, s13, s15 8000e50: ee77 7a67 vsub.f32 s15, s14, s15 8000e54: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8000e58: ee67 7a87 vmul.f32 s15, s15, s14 8000e5c: edc7 7a0d vstr s15, [r7, #52] @ 0x34 // Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation) if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) { 8000e60: edd7 7a05 vldr s15, [r7, #20] 8000e64: eef5 7a40 vcmp.f32 s15, #0.0 8000e68: eef1 fa10 vmrs APSR_nzcv, fpscr 8000e6c: d10e bne.n 8000e8c 8000e6e: edd7 7a04 vldr s15, [r7, #16] 8000e72: eef5 7a40 vcmp.f32 s15, #0.0 8000e76: eef1 fa10 vmrs APSR_nzcv, fpscr 8000e7a: d107 bne.n 8000e8c 8000e7c: edd7 7a03 vldr s15, [r7, #12] 8000e80: eef5 7a40 vcmp.f32 s15, #0.0 8000e84: eef1 fa10 vmrs APSR_nzcv, fpscr 8000e88: f000 854e beq.w 8001928 // Normalise accelerometer measurement recipNorm = invSqrt(ax * ax + ay * ay + az * az); 8000e8c: edd7 7a05 vldr s15, [r7, #20] 8000e90: ee27 7aa7 vmul.f32 s14, s15, s15 8000e94: edd7 7a04 vldr s15, [r7, #16] 8000e98: ee67 7aa7 vmul.f32 s15, s15, s15 8000e9c: ee37 7a27 vadd.f32 s14, s14, s15 8000ea0: edd7 7a03 vldr s15, [r7, #12] 8000ea4: ee67 7aa7 vmul.f32 s15, s15, s15 8000ea8: ee77 7a27 vadd.f32 s15, s14, s15 8000eac: eeb0 0a67 vmov.f32 s0, s15 8000eb0: f001 f95a bl 8002168 8000eb4: ed87 0a31 vstr s0, [r7, #196] @ 0xc4 ax *= recipNorm; 8000eb8: ed97 7a05 vldr s14, [r7, #20] 8000ebc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000ec0: ee67 7a27 vmul.f32 s15, s14, s15 8000ec4: edc7 7a05 vstr s15, [r7, #20] ay *= recipNorm; 8000ec8: ed97 7a04 vldr s14, [r7, #16] 8000ecc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000ed0: ee67 7a27 vmul.f32 s15, s14, s15 8000ed4: edc7 7a04 vstr s15, [r7, #16] az *= recipNorm; 8000ed8: ed97 7a03 vldr s14, [r7, #12] 8000edc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000ee0: ee67 7a27 vmul.f32 s15, s14, s15 8000ee4: edc7 7a03 vstr s15, [r7, #12] // Normalise magnetometer measurement recipNorm = invSqrt(mx * mx + my * my + mz * mz); 8000ee8: edd7 7a02 vldr s15, [r7, #8] 8000eec: ee27 7aa7 vmul.f32 s14, s15, s15 8000ef0: edd7 7a01 vldr s15, [r7, #4] 8000ef4: ee67 7aa7 vmul.f32 s15, s15, s15 8000ef8: ee37 7a27 vadd.f32 s14, s14, s15 8000efc: edd7 7a00 vldr s15, [r7] 8000f00: ee67 7aa7 vmul.f32 s15, s15, s15 8000f04: ee77 7a27 vadd.f32 s15, s14, s15 8000f08: eeb0 0a67 vmov.f32 s0, s15 8000f0c: f001 f92c bl 8002168 8000f10: ed87 0a31 vstr s0, [r7, #196] @ 0xc4 mx *= recipNorm; 8000f14: ed97 7a02 vldr s14, [r7, #8] 8000f18: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000f1c: ee67 7a27 vmul.f32 s15, s14, s15 8000f20: edc7 7a02 vstr s15, [r7, #8] my *= recipNorm; 8000f24: ed97 7a01 vldr s14, [r7, #4] 8000f28: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000f2c: ee67 7a27 vmul.f32 s15, s14, s15 8000f30: edc7 7a01 vstr s15, [r7, #4] mz *= recipNorm; 8000f34: ed97 7a00 vldr s14, [r7] 8000f38: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8000f3c: ee67 7a27 vmul.f32 s15, s14, s15 8000f40: edc7 7a00 vstr s15, [r7] // Auxiliary variables to avoid repeated arithmetic _2q0mx = 2.0f * q[0] * mx; 8000f44: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8000f48: ee77 7aa7 vadd.f32 s15, s15, s15 8000f4c: ed97 7a02 vldr s14, [r7, #8] 8000f50: ee67 7a27 vmul.f32 s15, s14, s15 8000f54: edc7 7a30 vstr s15, [r7, #192] @ 0xc0 _2q0my = 2.0f * q[0] * my; 8000f58: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8000f5c: ee77 7aa7 vadd.f32 s15, s15, s15 8000f60: ed97 7a01 vldr s14, [r7, #4] 8000f64: ee67 7a27 vmul.f32 s15, s14, s15 8000f68: edc7 7a2f vstr s15, [r7, #188] @ 0xbc _2q0mz = 2.0f * q[0] * mz; 8000f6c: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8000f70: ee77 7aa7 vadd.f32 s15, s15, s15 8000f74: ed97 7a00 vldr s14, [r7] 8000f78: ee67 7a27 vmul.f32 s15, s14, s15 8000f7c: edc7 7a2e vstr s15, [r7, #184] @ 0xb8 _2q1mx = 2.0f * q[1] * mx; 8000f80: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000f84: ee77 7aa7 vadd.f32 s15, s15, s15 8000f88: ed97 7a02 vldr s14, [r7, #8] 8000f8c: ee67 7a27 vmul.f32 s15, s14, s15 8000f90: edc7 7a2d vstr s15, [r7, #180] @ 0xb4 _2q0 = 2.0f * q[0]; 8000f94: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8000f98: ee77 7aa7 vadd.f32 s15, s15, s15 8000f9c: edc7 7a2c vstr s15, [r7, #176] @ 0xb0 _2q1 = 2.0f * q[1]; 8000fa0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8000fa4: ee77 7aa7 vadd.f32 s15, s15, s15 8000fa8: edc7 7a2b vstr s15, [r7, #172] @ 0xac _2q2 = 2.0f * q[2]; 8000fac: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8000fb0: ee77 7aa7 vadd.f32 s15, s15, s15 8000fb4: edc7 7a2a vstr s15, [r7, #168] @ 0xa8 _2q3 = 2.0f * q[3]; 8000fb8: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8000fbc: ee77 7aa7 vadd.f32 s15, s15, s15 8000fc0: edc7 7a29 vstr s15, [r7, #164] @ 0xa4 _2q0q2 = 2.0f * q[0] * q[2]; 8000fc4: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8000fc8: ee37 7aa7 vadd.f32 s14, s15, s15 8000fcc: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8000fd0: ee67 7a27 vmul.f32 s15, s14, s15 8000fd4: edc7 7a28 vstr s15, [r7, #160] @ 0xa0 _2q2q3 = 2.0f * q[2] * q[3]; 8000fd8: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8000fdc: ee37 7aa7 vadd.f32 s14, s15, s15 8000fe0: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8000fe4: ee67 7a27 vmul.f32 s15, s14, s15 8000fe8: edc7 7a27 vstr s15, [r7, #156] @ 0x9c q0q0 = q[0] * q[0]; 8000fec: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8000ff0: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8000ff4: ee67 7a27 vmul.f32 s15, s14, s15 8000ff8: edc7 7a26 vstr s15, [r7, #152] @ 0x98 q0q1 = q[0] * q[1]; 8000ffc: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8001000: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001004: ee67 7a27 vmul.f32 s15, s14, s15 8001008: edc7 7a25 vstr s15, [r7, #148] @ 0x94 q0q2 = q[0] * q[2]; 800100c: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8001010: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001014: ee67 7a27 vmul.f32 s15, s14, s15 8001018: edc7 7a24 vstr s15, [r7, #144] @ 0x90 q0q3 = q[0] * q[3]; 800101c: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8001020: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001024: ee67 7a27 vmul.f32 s15, s14, s15 8001028: edc7 7a23 vstr s15, [r7, #140] @ 0x8c q1q1 = q[1] * q[1]; 800102c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001030: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001034: ee67 7a27 vmul.f32 s15, s14, s15 8001038: edc7 7a22 vstr s15, [r7, #136] @ 0x88 q1q2 = q[1] * q[2]; 800103c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001040: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001044: ee67 7a27 vmul.f32 s15, s14, s15 8001048: edc7 7a21 vstr s15, [r7, #132] @ 0x84 q1q3 = q[1] * q[3]; 800104c: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001050: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001054: ee67 7a27 vmul.f32 s15, s14, s15 8001058: edc7 7a20 vstr s15, [r7, #128] @ 0x80 q2q2 = q[2] * q[2]; 800105c: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001060: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001064: ee67 7a27 vmul.f32 s15, s14, s15 8001068: edc7 7a1f vstr s15, [r7, #124] @ 0x7c q2q3 = q[2] * q[3]; 800106c: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001070: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001074: ee67 7a27 vmul.f32 s15, s14, s15 8001078: edc7 7a1e vstr s15, [r7, #120] @ 0x78 q3q3 = q[3] * q[3]; 800107c: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001080: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001084: ee67 7a27 vmul.f32 s15, s14, s15 8001088: edc7 7a1d vstr s15, [r7, #116] @ 0x74 // Reference direction of Earth's magnetic field hx = mx * q0q0 - _2q0my * q[3] + _2q0mz * q[2] + mx * q1q1 + _2q1 * my * q[2] + _2q1 * mz * q[3] - mx * q2q2 - mx * q3q3; 800108c: ed97 7a02 vldr s14, [r7, #8] 8001090: edd7 7a26 vldr s15, [r7, #152] @ 0x98 8001094: ee27 7a27 vmul.f32 s14, s14, s15 8001098: edd7 6a11 vldr s13, [r7, #68] @ 0x44 800109c: edd7 7a2f vldr s15, [r7, #188] @ 0xbc 80010a0: ee66 7aa7 vmul.f32 s15, s13, s15 80010a4: ee37 7a67 vsub.f32 s14, s14, s15 80010a8: edd7 6a10 vldr s13, [r7, #64] @ 0x40 80010ac: edd7 7a2e vldr s15, [r7, #184] @ 0xb8 80010b0: ee66 7aa7 vmul.f32 s15, s13, s15 80010b4: ee37 7a27 vadd.f32 s14, s14, s15 80010b8: edd7 6a02 vldr s13, [r7, #8] 80010bc: edd7 7a22 vldr s15, [r7, #136] @ 0x88 80010c0: ee66 7aa7 vmul.f32 s15, s13, s15 80010c4: ee37 7a27 vadd.f32 s14, s14, s15 80010c8: edd7 6a2b vldr s13, [r7, #172] @ 0xac 80010cc: edd7 7a01 vldr s15, [r7, #4] 80010d0: ee66 6aa7 vmul.f32 s13, s13, s15 80010d4: edd7 7a10 vldr s15, [r7, #64] @ 0x40 80010d8: ee66 7aa7 vmul.f32 s15, s13, s15 80010dc: ee37 7a27 vadd.f32 s14, s14, s15 80010e0: edd7 6a2b vldr s13, [r7, #172] @ 0xac 80010e4: edd7 7a00 vldr s15, [r7] 80010e8: ee66 6aa7 vmul.f32 s13, s13, s15 80010ec: edd7 7a11 vldr s15, [r7, #68] @ 0x44 80010f0: ee66 7aa7 vmul.f32 s15, s13, s15 80010f4: ee37 7a27 vadd.f32 s14, s14, s15 80010f8: edd7 6a02 vldr s13, [r7, #8] 80010fc: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 8001100: ee66 7aa7 vmul.f32 s15, s13, s15 8001104: ee37 7a67 vsub.f32 s14, s14, s15 8001108: edd7 6a02 vldr s13, [r7, #8] 800110c: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001110: ee66 7aa7 vmul.f32 s15, s13, s15 8001114: ee77 7a67 vsub.f32 s15, s14, s15 8001118: edc7 7a1c vstr s15, [r7, #112] @ 0x70 hy = _2q0mx * q[3] + my * q0q0 - _2q0mz * q[1] + _2q1mx * q[2] - my * q1q1 + my * q2q2 + _2q2 * mz * q[3] - my * q3q3; 800111c: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001120: edd7 7a30 vldr s15, [r7, #192] @ 0xc0 8001124: ee27 7a27 vmul.f32 s14, s14, s15 8001128: edd7 6a01 vldr s13, [r7, #4] 800112c: edd7 7a26 vldr s15, [r7, #152] @ 0x98 8001130: ee66 7aa7 vmul.f32 s15, s13, s15 8001134: ee37 7a27 vadd.f32 s14, s14, s15 8001138: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 800113c: edd7 7a2e vldr s15, [r7, #184] @ 0xb8 8001140: ee66 7aa7 vmul.f32 s15, s13, s15 8001144: ee37 7a67 vsub.f32 s14, s14, s15 8001148: edd7 6a10 vldr s13, [r7, #64] @ 0x40 800114c: edd7 7a2d vldr s15, [r7, #180] @ 0xb4 8001150: ee66 7aa7 vmul.f32 s15, s13, s15 8001154: ee37 7a27 vadd.f32 s14, s14, s15 8001158: edd7 6a01 vldr s13, [r7, #4] 800115c: edd7 7a22 vldr s15, [r7, #136] @ 0x88 8001160: ee66 7aa7 vmul.f32 s15, s13, s15 8001164: ee37 7a67 vsub.f32 s14, s14, s15 8001168: edd7 6a01 vldr s13, [r7, #4] 800116c: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 8001170: ee66 7aa7 vmul.f32 s15, s13, s15 8001174: ee37 7a27 vadd.f32 s14, s14, s15 8001178: edd7 6a2a vldr s13, [r7, #168] @ 0xa8 800117c: edd7 7a00 vldr s15, [r7] 8001180: ee66 6aa7 vmul.f32 s13, s13, s15 8001184: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001188: ee66 7aa7 vmul.f32 s15, s13, s15 800118c: ee37 7a27 vadd.f32 s14, s14, s15 8001190: edd7 6a01 vldr s13, [r7, #4] 8001194: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001198: ee66 7aa7 vmul.f32 s15, s13, s15 800119c: ee77 7a67 vsub.f32 s15, s14, s15 80011a0: edc7 7a1b vstr s15, [r7, #108] @ 0x6c _2bx = sqrt(hx * hx + hy * hy); 80011a4: edd7 7a1c vldr s15, [r7, #112] @ 0x70 80011a8: ee27 7aa7 vmul.f32 s14, s15, s15 80011ac: edd7 7a1b vldr s15, [r7, #108] @ 0x6c 80011b0: ee67 7aa7 vmul.f32 s15, s15, s15 80011b4: ee77 7a27 vadd.f32 s15, s14, s15 80011b8: ee17 0a90 vmov r0, s15 80011bc: f7ff f99c bl 80004f8 <__aeabi_f2d> 80011c0: 4602 mov r2, r0 80011c2: 460b mov r3, r1 80011c4: ec43 2b10 vmov d0, r2, r3 80011c8: f01c fcce bl 801db68 80011cc: ec53 2b10 vmov r2, r3, d0 80011d0: 4610 mov r0, r2 80011d2: 4619 mov r1, r3 80011d4: f7ff fce0 bl 8000b98 <__aeabi_d2f> 80011d8: 4603 mov r3, r0 80011da: 66bb str r3, [r7, #104] @ 0x68 _2bz = -_2q0mx * q[2] + _2q0my * q[1] + mz * q0q0 + _2q1mx * q[3] - mz * q1q1 + _2q2 * my * q[3] - mz * q2q2 + mz * q3q3; 80011dc: edd7 7a30 vldr s15, [r7, #192] @ 0xc0 80011e0: eeb1 7a67 vneg.f32 s14, s15 80011e4: edd7 7a10 vldr s15, [r7, #64] @ 0x40 80011e8: ee27 7a27 vmul.f32 s14, s14, s15 80011ec: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 80011f0: edd7 7a2f vldr s15, [r7, #188] @ 0xbc 80011f4: ee66 7aa7 vmul.f32 s15, s13, s15 80011f8: ee37 7a27 vadd.f32 s14, s14, s15 80011fc: edd7 6a00 vldr s13, [r7] 8001200: edd7 7a26 vldr s15, [r7, #152] @ 0x98 8001204: ee66 7aa7 vmul.f32 s15, s13, s15 8001208: ee37 7a27 vadd.f32 s14, s14, s15 800120c: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8001210: edd7 7a2d vldr s15, [r7, #180] @ 0xb4 8001214: ee66 7aa7 vmul.f32 s15, s13, s15 8001218: ee37 7a27 vadd.f32 s14, s14, s15 800121c: edd7 6a00 vldr s13, [r7] 8001220: edd7 7a22 vldr s15, [r7, #136] @ 0x88 8001224: ee66 7aa7 vmul.f32 s15, s13, s15 8001228: ee37 7a67 vsub.f32 s14, s14, s15 800122c: edd7 6a2a vldr s13, [r7, #168] @ 0xa8 8001230: edd7 7a01 vldr s15, [r7, #4] 8001234: ee66 6aa7 vmul.f32 s13, s13, s15 8001238: edd7 7a11 vldr s15, [r7, #68] @ 0x44 800123c: ee66 7aa7 vmul.f32 s15, s13, s15 8001240: ee37 7a27 vadd.f32 s14, s14, s15 8001244: edd7 6a00 vldr s13, [r7] 8001248: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 800124c: ee66 7aa7 vmul.f32 s15, s13, s15 8001250: ee37 7a67 vsub.f32 s14, s14, s15 8001254: edd7 6a00 vldr s13, [r7] 8001258: edd7 7a1d vldr s15, [r7, #116] @ 0x74 800125c: ee66 7aa7 vmul.f32 s15, s13, s15 8001260: ee77 7a27 vadd.f32 s15, s14, s15 8001264: edc7 7a19 vstr s15, [r7, #100] @ 0x64 _4bx = 2.0f * _2bx; 8001268: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800126c: ee77 7aa7 vadd.f32 s15, s15, s15 8001270: edc7 7a18 vstr s15, [r7, #96] @ 0x60 _4bz = 2.0f * _2bz; 8001274: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001278: ee77 7aa7 vadd.f32 s15, s15, s15 800127c: edc7 7a17 vstr s15, [r7, #92] @ 0x5c // Gradient decent algorithm corrective step s0 = -_2q2 * (2.0f * q1q3 - _2q0q2 - ax) + _2q1 * (2.0f * q0q1 + _2q2q3 - ay) - _2bz * q[2] * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (-_2bx * q[3] + _2bz * q[1]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + _2bx * q[2] * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz); 8001280: edd7 7a2a vldr s15, [r7, #168] @ 0xa8 8001284: eeb1 7a67 vneg.f32 s14, s15 8001288: edd7 7a20 vldr s15, [r7, #128] @ 0x80 800128c: ee77 6aa7 vadd.f32 s13, s15, s15 8001290: edd7 7a28 vldr s15, [r7, #160] @ 0xa0 8001294: ee76 6ae7 vsub.f32 s13, s13, s15 8001298: edd7 7a05 vldr s15, [r7, #20] 800129c: ee76 7ae7 vsub.f32 s15, s13, s15 80012a0: ee27 7a27 vmul.f32 s14, s14, s15 80012a4: edd7 7a25 vldr s15, [r7, #148] @ 0x94 80012a8: ee77 6aa7 vadd.f32 s13, s15, s15 80012ac: edd7 7a27 vldr s15, [r7, #156] @ 0x9c 80012b0: ee76 6aa7 vadd.f32 s13, s13, s15 80012b4: edd7 7a04 vldr s15, [r7, #16] 80012b8: ee76 6ae7 vsub.f32 s13, s13, s15 80012bc: edd7 7a2b vldr s15, [r7, #172] @ 0xac 80012c0: ee66 7aa7 vmul.f32 s15, s13, s15 80012c4: ee37 7a27 vadd.f32 s14, s14, s15 80012c8: edd7 6a10 vldr s13, [r7, #64] @ 0x40 80012cc: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80012d0: ee66 6aa7 vmul.f32 s13, s13, s15 80012d4: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 80012d8: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80012dc: ee36 6a67 vsub.f32 s12, s12, s15 80012e0: edd7 7a1d vldr s15, [r7, #116] @ 0x74 80012e4: ee36 6a67 vsub.f32 s12, s12, s15 80012e8: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80012ec: ee26 6a27 vmul.f32 s12, s12, s15 80012f0: edd7 5a20 vldr s11, [r7, #128] @ 0x80 80012f4: edd7 7a24 vldr s15, [r7, #144] @ 0x90 80012f8: ee75 5ae7 vsub.f32 s11, s11, s15 80012fc: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001300: ee65 7aa7 vmul.f32 s15, s11, s15 8001304: ee36 6a27 vadd.f32 s12, s12, s15 8001308: edd7 7a02 vldr s15, [r7, #8] 800130c: ee76 7a67 vsub.f32 s15, s12, s15 8001310: ee66 7aa7 vmul.f32 s15, s13, s15 8001314: ee37 7a67 vsub.f32 s14, s14, s15 8001318: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800131c: eef1 6a67 vneg.f32 s13, s15 8001320: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001324: ee66 6aa7 vmul.f32 s13, s13, s15 8001328: ed97 6a0f vldr s12, [r7, #60] @ 0x3c 800132c: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001330: ee66 7a27 vmul.f32 s15, s12, s15 8001334: ee76 6aa7 vadd.f32 s13, s13, s15 8001338: ed97 6a21 vldr s12, [r7, #132] @ 0x84 800133c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001340: ee36 6a67 vsub.f32 s12, s12, s15 8001344: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001348: ee26 6a27 vmul.f32 s12, s12, s15 800134c: edd7 5a25 vldr s11, [r7, #148] @ 0x94 8001350: edd7 7a1e vldr s15, [r7, #120] @ 0x78 8001354: ee75 5aa7 vadd.f32 s11, s11, s15 8001358: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800135c: ee65 7aa7 vmul.f32 s15, s11, s15 8001360: ee36 6a27 vadd.f32 s12, s12, s15 8001364: edd7 7a01 vldr s15, [r7, #4] 8001368: ee76 7a67 vsub.f32 s15, s12, s15 800136c: ee66 7aa7 vmul.f32 s15, s13, s15 8001370: ee37 7a27 vadd.f32 s14, s14, s15 8001374: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8001378: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800137c: ee66 6aa7 vmul.f32 s13, s13, s15 8001380: ed97 6a24 vldr s12, [r7, #144] @ 0x90 8001384: edd7 7a20 vldr s15, [r7, #128] @ 0x80 8001388: ee36 6a27 vadd.f32 s12, s12, s15 800138c: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001390: ee26 6a27 vmul.f32 s12, s12, s15 8001394: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5 8001398: edd7 7a22 vldr s15, [r7, #136] @ 0x88 800139c: ee75 5ae7 vsub.f32 s11, s11, s15 80013a0: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80013a4: ee75 5ae7 vsub.f32 s11, s11, s15 80013a8: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80013ac: ee65 7aa7 vmul.f32 s15, s11, s15 80013b0: ee36 6a27 vadd.f32 s12, s12, s15 80013b4: edd7 7a00 vldr s15, [r7] 80013b8: ee76 7a67 vsub.f32 s15, s12, s15 80013bc: ee66 7aa7 vmul.f32 s15, s13, s15 80013c0: ee77 7a27 vadd.f32 s15, s14, s15 80013c4: edc7 7a16 vstr s15, [r7, #88] @ 0x58 s1 = _2q3 * (2.0f * q1q3 - _2q0q2 - ax) + _2q0 * (2.0f * q0q1 + _2q2q3 - ay) - 4.0f * q[1] * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) + _2bz * q[3] * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (_2bx * q[2] + _2bz * q[0]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + (_2bx * q[3] - _4bz * q[1]) * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz); 80013c8: edd7 7a20 vldr s15, [r7, #128] @ 0x80 80013cc: ee37 7aa7 vadd.f32 s14, s15, s15 80013d0: edd7 7a28 vldr s15, [r7, #160] @ 0xa0 80013d4: ee37 7a67 vsub.f32 s14, s14, s15 80013d8: edd7 7a05 vldr s15, [r7, #20] 80013dc: ee37 7a67 vsub.f32 s14, s14, s15 80013e0: edd7 7a29 vldr s15, [r7, #164] @ 0xa4 80013e4: ee27 7a27 vmul.f32 s14, s14, s15 80013e8: edd7 7a25 vldr s15, [r7, #148] @ 0x94 80013ec: ee77 6aa7 vadd.f32 s13, s15, s15 80013f0: edd7 7a27 vldr s15, [r7, #156] @ 0x9c 80013f4: ee76 6aa7 vadd.f32 s13, s13, s15 80013f8: edd7 7a04 vldr s15, [r7, #16] 80013fc: ee76 6ae7 vsub.f32 s13, s13, s15 8001400: edd7 7a2c vldr s15, [r7, #176] @ 0xb0 8001404: ee66 7aa7 vmul.f32 s15, s13, s15 8001408: ee37 7a27 vadd.f32 s14, s14, s15 800140c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001410: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0 8001414: ee67 6aa6 vmul.f32 s13, s15, s13 8001418: edd7 7a22 vldr s15, [r7, #136] @ 0x88 800141c: ee77 7aa7 vadd.f32 s15, s15, s15 8001420: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0 8001424: ee36 6a67 vsub.f32 s12, s12, s15 8001428: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 800142c: ee77 7aa7 vadd.f32 s15, s15, s15 8001430: ee36 6a67 vsub.f32 s12, s12, s15 8001434: edd7 7a03 vldr s15, [r7, #12] 8001438: ee76 7a67 vsub.f32 s15, s12, s15 800143c: ee66 7aa7 vmul.f32 s15, s13, s15 8001440: ee37 7a67 vsub.f32 s14, s14, s15 8001444: edd7 6a11 vldr s13, [r7, #68] @ 0x44 8001448: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800144c: ee66 6aa7 vmul.f32 s13, s13, s15 8001450: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 8001454: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 8001458: ee36 6a67 vsub.f32 s12, s12, s15 800145c: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001460: ee36 6a67 vsub.f32 s12, s12, s15 8001464: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001468: ee26 6a27 vmul.f32 s12, s12, s15 800146c: edd7 5a20 vldr s11, [r7, #128] @ 0x80 8001470: edd7 7a24 vldr s15, [r7, #144] @ 0x90 8001474: ee75 5ae7 vsub.f32 s11, s11, s15 8001478: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800147c: ee65 7aa7 vmul.f32 s15, s11, s15 8001480: ee36 6a27 vadd.f32 s12, s12, s15 8001484: edd7 7a02 vldr s15, [r7, #8] 8001488: ee76 7a67 vsub.f32 s15, s12, s15 800148c: ee66 7aa7 vmul.f32 s15, s13, s15 8001490: ee37 7a27 vadd.f32 s14, s14, s15 8001494: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8001498: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800149c: ee66 6aa7 vmul.f32 s13, s13, s15 80014a0: ed97 6a0e vldr s12, [r7, #56] @ 0x38 80014a4: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80014a8: ee66 7a27 vmul.f32 s15, s12, s15 80014ac: ee76 6aa7 vadd.f32 s13, s13, s15 80014b0: ed97 6a21 vldr s12, [r7, #132] @ 0x84 80014b4: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 80014b8: ee36 6a67 vsub.f32 s12, s12, s15 80014bc: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80014c0: ee26 6a27 vmul.f32 s12, s12, s15 80014c4: edd7 5a25 vldr s11, [r7, #148] @ 0x94 80014c8: edd7 7a1e vldr s15, [r7, #120] @ 0x78 80014cc: ee75 5aa7 vadd.f32 s11, s11, s15 80014d0: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80014d4: ee65 7aa7 vmul.f32 s15, s11, s15 80014d8: ee36 6a27 vadd.f32 s12, s12, s15 80014dc: edd7 7a01 vldr s15, [r7, #4] 80014e0: ee76 7a67 vsub.f32 s15, s12, s15 80014e4: ee66 7aa7 vmul.f32 s15, s13, s15 80014e8: ee37 7a27 vadd.f32 s14, s14, s15 80014ec: edd7 6a11 vldr s13, [r7, #68] @ 0x44 80014f0: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80014f4: ee66 6aa7 vmul.f32 s13, s13, s15 80014f8: ed97 6a0f vldr s12, [r7, #60] @ 0x3c 80014fc: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8001500: ee66 7a27 vmul.f32 s15, s12, s15 8001504: ee76 6ae7 vsub.f32 s13, s13, s15 8001508: ed97 6a24 vldr s12, [r7, #144] @ 0x90 800150c: edd7 7a20 vldr s15, [r7, #128] @ 0x80 8001510: ee36 6a27 vadd.f32 s12, s12, s15 8001514: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001518: ee26 6a27 vmul.f32 s12, s12, s15 800151c: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5 8001520: edd7 7a22 vldr s15, [r7, #136] @ 0x88 8001524: ee75 5ae7 vsub.f32 s11, s11, s15 8001528: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 800152c: ee75 5ae7 vsub.f32 s11, s11, s15 8001530: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001534: ee65 7aa7 vmul.f32 s15, s11, s15 8001538: ee36 6a27 vadd.f32 s12, s12, s15 800153c: edd7 7a00 vldr s15, [r7] 8001540: ee76 7a67 vsub.f32 s15, s12, s15 8001544: ee66 7aa7 vmul.f32 s15, s13, s15 8001548: ee77 7a27 vadd.f32 s15, s14, s15 800154c: edc7 7a15 vstr s15, [r7, #84] @ 0x54 s2 = -_2q0 * (2.0f * q1q3 - _2q0q2 - ax) + _2q3 * (2.0f * q0q1 + _2q2q3 - ay) - 4.0f * q[2] * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) + (-_4bx * q[2] - _2bz * q[0]) * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (_2bx * q[1] + _2bz * q[3]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + (_2bx * q[0] - _4bz * q[2]) * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz); 8001550: edd7 7a2c vldr s15, [r7, #176] @ 0xb0 8001554: eeb1 7a67 vneg.f32 s14, s15 8001558: edd7 7a20 vldr s15, [r7, #128] @ 0x80 800155c: ee77 6aa7 vadd.f32 s13, s15, s15 8001560: edd7 7a28 vldr s15, [r7, #160] @ 0xa0 8001564: ee76 6ae7 vsub.f32 s13, s13, s15 8001568: edd7 7a05 vldr s15, [r7, #20] 800156c: ee76 7ae7 vsub.f32 s15, s13, s15 8001570: ee27 7a27 vmul.f32 s14, s14, s15 8001574: edd7 7a25 vldr s15, [r7, #148] @ 0x94 8001578: ee77 6aa7 vadd.f32 s13, s15, s15 800157c: edd7 7a27 vldr s15, [r7, #156] @ 0x9c 8001580: ee76 6aa7 vadd.f32 s13, s13, s15 8001584: edd7 7a04 vldr s15, [r7, #16] 8001588: ee76 6ae7 vsub.f32 s13, s13, s15 800158c: edd7 7a29 vldr s15, [r7, #164] @ 0xa4 8001590: ee66 7aa7 vmul.f32 s15, s13, s15 8001594: ee37 7a27 vadd.f32 s14, s14, s15 8001598: edd7 7a10 vldr s15, [r7, #64] @ 0x40 800159c: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0 80015a0: ee67 6aa6 vmul.f32 s13, s15, s13 80015a4: edd7 7a22 vldr s15, [r7, #136] @ 0x88 80015a8: ee77 7aa7 vadd.f32 s15, s15, s15 80015ac: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0 80015b0: ee36 6a67 vsub.f32 s12, s12, s15 80015b4: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80015b8: ee77 7aa7 vadd.f32 s15, s15, s15 80015bc: ee36 6a67 vsub.f32 s12, s12, s15 80015c0: edd7 7a03 vldr s15, [r7, #12] 80015c4: ee76 7a67 vsub.f32 s15, s12, s15 80015c8: ee66 7aa7 vmul.f32 s15, s13, s15 80015cc: ee37 7a67 vsub.f32 s14, s14, s15 80015d0: edd7 7a18 vldr s15, [r7, #96] @ 0x60 80015d4: eef1 6a67 vneg.f32 s13, s15 80015d8: edd7 7a10 vldr s15, [r7, #64] @ 0x40 80015dc: ee66 6aa7 vmul.f32 s13, s13, s15 80015e0: ed97 6a0e vldr s12, [r7, #56] @ 0x38 80015e4: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80015e8: ee66 7a27 vmul.f32 s15, s12, s15 80015ec: ee76 6ae7 vsub.f32 s13, s13, s15 80015f0: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 80015f4: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80015f8: ee36 6a67 vsub.f32 s12, s12, s15 80015fc: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001600: ee36 6a67 vsub.f32 s12, s12, s15 8001604: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001608: ee26 6a27 vmul.f32 s12, s12, s15 800160c: edd7 5a20 vldr s11, [r7, #128] @ 0x80 8001610: edd7 7a24 vldr s15, [r7, #144] @ 0x90 8001614: ee75 5ae7 vsub.f32 s11, s11, s15 8001618: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800161c: ee65 7aa7 vmul.f32 s15, s11, s15 8001620: ee36 6a27 vadd.f32 s12, s12, s15 8001624: edd7 7a02 vldr s15, [r7, #8] 8001628: ee76 7a67 vsub.f32 s15, s12, s15 800162c: ee66 7aa7 vmul.f32 s15, s13, s15 8001630: ee37 7a27 vadd.f32 s14, s14, s15 8001634: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001638: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800163c: ee66 6aa7 vmul.f32 s13, s13, s15 8001640: ed97 6a11 vldr s12, [r7, #68] @ 0x44 8001644: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001648: ee66 7a27 vmul.f32 s15, s12, s15 800164c: ee76 6aa7 vadd.f32 s13, s13, s15 8001650: ed97 6a21 vldr s12, [r7, #132] @ 0x84 8001654: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001658: ee36 6a67 vsub.f32 s12, s12, s15 800165c: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001660: ee26 6a27 vmul.f32 s12, s12, s15 8001664: edd7 5a25 vldr s11, [r7, #148] @ 0x94 8001668: edd7 7a1e vldr s15, [r7, #120] @ 0x78 800166c: ee75 5aa7 vadd.f32 s11, s11, s15 8001670: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001674: ee65 7aa7 vmul.f32 s15, s11, s15 8001678: ee36 6a27 vadd.f32 s12, s12, s15 800167c: edd7 7a01 vldr s15, [r7, #4] 8001680: ee76 7a67 vsub.f32 s15, s12, s15 8001684: ee66 7aa7 vmul.f32 s15, s13, s15 8001688: ee37 7a27 vadd.f32 s14, s14, s15 800168c: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8001690: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001694: ee66 6aa7 vmul.f32 s13, s13, s15 8001698: ed97 6a10 vldr s12, [r7, #64] @ 0x40 800169c: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 80016a0: ee66 7a27 vmul.f32 s15, s12, s15 80016a4: ee76 6ae7 vsub.f32 s13, s13, s15 80016a8: ed97 6a24 vldr s12, [r7, #144] @ 0x90 80016ac: edd7 7a20 vldr s15, [r7, #128] @ 0x80 80016b0: ee36 6a27 vadd.f32 s12, s12, s15 80016b4: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80016b8: ee26 6a27 vmul.f32 s12, s12, s15 80016bc: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5 80016c0: edd7 7a22 vldr s15, [r7, #136] @ 0x88 80016c4: ee75 5ae7 vsub.f32 s11, s11, s15 80016c8: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 80016cc: ee75 5ae7 vsub.f32 s11, s11, s15 80016d0: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80016d4: ee65 7aa7 vmul.f32 s15, s11, s15 80016d8: ee36 6a27 vadd.f32 s12, s12, s15 80016dc: edd7 7a00 vldr s15, [r7] 80016e0: ee76 7a67 vsub.f32 s15, s12, s15 80016e4: ee66 7aa7 vmul.f32 s15, s13, s15 80016e8: ee77 7a27 vadd.f32 s15, s14, s15 80016ec: edc7 7a14 vstr s15, [r7, #80] @ 0x50 s3 = _2q1 * (2.0f * q1q3 - _2q0q2 - ax) + _2q2 * (2.0f * q0q1 + _2q2q3 - ay) + (-_4bx * q[3] + _2bz * q[1]) * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (-_2bx * q[0] + _2bz * q[2]) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + _2bx * q[1] * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz); 80016f0: edd7 7a20 vldr s15, [r7, #128] @ 0x80 80016f4: ee37 7aa7 vadd.f32 s14, s15, s15 80016f8: edd7 7a28 vldr s15, [r7, #160] @ 0xa0 80016fc: ee37 7a67 vsub.f32 s14, s14, s15 8001700: edd7 7a05 vldr s15, [r7, #20] 8001704: ee37 7a67 vsub.f32 s14, s14, s15 8001708: edd7 7a2b vldr s15, [r7, #172] @ 0xac 800170c: ee27 7a27 vmul.f32 s14, s14, s15 8001710: edd7 7a25 vldr s15, [r7, #148] @ 0x94 8001714: ee77 6aa7 vadd.f32 s13, s15, s15 8001718: edd7 7a27 vldr s15, [r7, #156] @ 0x9c 800171c: ee76 6aa7 vadd.f32 s13, s13, s15 8001720: edd7 7a04 vldr s15, [r7, #16] 8001724: ee76 6ae7 vsub.f32 s13, s13, s15 8001728: edd7 7a2a vldr s15, [r7, #168] @ 0xa8 800172c: ee66 7aa7 vmul.f32 s15, s13, s15 8001730: ee37 7a27 vadd.f32 s14, s14, s15 8001734: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8001738: eef1 6a67 vneg.f32 s13, s15 800173c: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001740: ee66 6aa7 vmul.f32 s13, s13, s15 8001744: ed97 6a0f vldr s12, [r7, #60] @ 0x3c 8001748: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800174c: ee66 7a27 vmul.f32 s15, s12, s15 8001750: ee76 6aa7 vadd.f32 s13, s13, s15 8001754: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 8001758: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 800175c: ee36 6a67 vsub.f32 s12, s12, s15 8001760: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001764: ee36 6a67 vsub.f32 s12, s12, s15 8001768: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800176c: ee26 6a27 vmul.f32 s12, s12, s15 8001770: edd7 5a20 vldr s11, [r7, #128] @ 0x80 8001774: edd7 7a24 vldr s15, [r7, #144] @ 0x90 8001778: ee75 5ae7 vsub.f32 s11, s11, s15 800177c: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001780: ee65 7aa7 vmul.f32 s15, s11, s15 8001784: ee36 6a27 vadd.f32 s12, s12, s15 8001788: edd7 7a02 vldr s15, [r7, #8] 800178c: ee76 7a67 vsub.f32 s15, s12, s15 8001790: ee66 7aa7 vmul.f32 s15, s13, s15 8001794: ee37 7a27 vadd.f32 s14, s14, s15 8001798: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800179c: eef1 6a67 vneg.f32 s13, s15 80017a0: edd7 7a0e vldr s15, [r7, #56] @ 0x38 80017a4: ee66 6aa7 vmul.f32 s13, s13, s15 80017a8: ed97 6a10 vldr s12, [r7, #64] @ 0x40 80017ac: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80017b0: ee66 7a27 vmul.f32 s15, s12, s15 80017b4: ee76 6aa7 vadd.f32 s13, s13, s15 80017b8: ed97 6a21 vldr s12, [r7, #132] @ 0x84 80017bc: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 80017c0: ee36 6a67 vsub.f32 s12, s12, s15 80017c4: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80017c8: ee26 6a27 vmul.f32 s12, s12, s15 80017cc: edd7 5a25 vldr s11, [r7, #148] @ 0x94 80017d0: edd7 7a1e vldr s15, [r7, #120] @ 0x78 80017d4: ee75 5aa7 vadd.f32 s11, s11, s15 80017d8: edd7 7a19 vldr s15, [r7, #100] @ 0x64 80017dc: ee65 7aa7 vmul.f32 s15, s11, s15 80017e0: ee36 6a27 vadd.f32 s12, s12, s15 80017e4: edd7 7a01 vldr s15, [r7, #4] 80017e8: ee76 7a67 vsub.f32 s15, s12, s15 80017ec: ee66 7aa7 vmul.f32 s15, s13, s15 80017f0: ee37 7a27 vadd.f32 s14, s14, s15 80017f4: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 80017f8: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80017fc: ee66 6aa7 vmul.f32 s13, s13, s15 8001800: ed97 6a24 vldr s12, [r7, #144] @ 0x90 8001804: edd7 7a20 vldr s15, [r7, #128] @ 0x80 8001808: ee36 6a27 vadd.f32 s12, s12, s15 800180c: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8001810: ee26 6a27 vmul.f32 s12, s12, s15 8001814: eef6 5a00 vmov.f32 s11, #96 @ 0x3f000000 0.5 8001818: edd7 7a22 vldr s15, [r7, #136] @ 0x88 800181c: ee75 5ae7 vsub.f32 s11, s11, s15 8001820: edd7 7a1f vldr s15, [r7, #124] @ 0x7c 8001824: ee75 5ae7 vsub.f32 s11, s11, s15 8001828: edd7 7a19 vldr s15, [r7, #100] @ 0x64 800182c: ee65 7aa7 vmul.f32 s15, s11, s15 8001830: ee36 6a27 vadd.f32 s12, s12, s15 8001834: edd7 7a00 vldr s15, [r7] 8001838: ee76 7a67 vsub.f32 s15, s12, s15 800183c: ee66 7aa7 vmul.f32 s15, s13, s15 8001840: ee77 7a27 vadd.f32 s15, s14, s15 8001844: edc7 7a13 vstr s15, [r7, #76] @ 0x4c recipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude 8001848: edd7 7a16 vldr s15, [r7, #88] @ 0x58 800184c: ee27 7aa7 vmul.f32 s14, s15, s15 8001850: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001854: ee67 7aa7 vmul.f32 s15, s15, s15 8001858: ee37 7a27 vadd.f32 s14, s14, s15 800185c: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001860: ee67 7aa7 vmul.f32 s15, s15, s15 8001864: ee37 7a27 vadd.f32 s14, s14, s15 8001868: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 800186c: ee67 7aa7 vmul.f32 s15, s15, s15 8001870: ee77 7a27 vadd.f32 s15, s14, s15 8001874: eeb0 0a67 vmov.f32 s0, s15 8001878: f000 fc76 bl 8002168 800187c: ed87 0a31 vstr s0, [r7, #196] @ 0xc4 s0 *= recipNorm; 8001880: ed97 7a16 vldr s14, [r7, #88] @ 0x58 8001884: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001888: ee67 7a27 vmul.f32 s15, s14, s15 800188c: edc7 7a16 vstr s15, [r7, #88] @ 0x58 s1 *= recipNorm; 8001890: ed97 7a15 vldr s14, [r7, #84] @ 0x54 8001894: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001898: ee67 7a27 vmul.f32 s15, s14, s15 800189c: edc7 7a15 vstr s15, [r7, #84] @ 0x54 s2 *= recipNorm; 80018a0: ed97 7a14 vldr s14, [r7, #80] @ 0x50 80018a4: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 80018a8: ee67 7a27 vmul.f32 s15, s14, s15 80018ac: edc7 7a14 vstr s15, [r7, #80] @ 0x50 s3 *= recipNorm; 80018b0: ed97 7a13 vldr s14, [r7, #76] @ 0x4c 80018b4: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 80018b8: ee67 7a27 vmul.f32 s15, s14, s15 80018bc: edc7 7a13 vstr s15, [r7, #76] @ 0x4c // Apply feedback step qDot[0] -= filter->beta * s0; 80018c0: ed97 7a0a vldr s14, [r7, #40] @ 0x28 80018c4: 6a7b ldr r3, [r7, #36] @ 0x24 80018c6: edd3 6a04 vldr s13, [r3, #16] 80018ca: edd7 7a16 vldr s15, [r7, #88] @ 0x58 80018ce: ee66 7aa7 vmul.f32 s15, s13, s15 80018d2: ee77 7a67 vsub.f32 s15, s14, s15 80018d6: edc7 7a0a vstr s15, [r7, #40] @ 0x28 qDot[1] -= filter->beta * s1; 80018da: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 80018de: 6a7b ldr r3, [r7, #36] @ 0x24 80018e0: edd3 6a04 vldr s13, [r3, #16] 80018e4: edd7 7a15 vldr s15, [r7, #84] @ 0x54 80018e8: ee66 7aa7 vmul.f32 s15, s13, s15 80018ec: ee77 7a67 vsub.f32 s15, s14, s15 80018f0: edc7 7a0b vstr s15, [r7, #44] @ 0x2c qDot[2] -= filter->beta * s2; 80018f4: ed97 7a0c vldr s14, [r7, #48] @ 0x30 80018f8: 6a7b ldr r3, [r7, #36] @ 0x24 80018fa: edd3 6a04 vldr s13, [r3, #16] 80018fe: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001902: ee66 7aa7 vmul.f32 s15, s13, s15 8001906: ee77 7a67 vsub.f32 s15, s14, s15 800190a: edc7 7a0c vstr s15, [r7, #48] @ 0x30 qDot[3] -= filter->beta * s3; 800190e: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8001912: 6a7b ldr r3, [r7, #36] @ 0x24 8001914: edd3 6a04 vldr s13, [r3, #16] 8001918: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 800191c: ee66 7aa7 vmul.f32 s15, s13, s15 8001920: ee77 7a67 vsub.f32 s15, s14, s15 8001924: edc7 7a0d vstr s15, [r7, #52] @ 0x34 } // Integrate rate of change of quaternion to yield quaternion q[0] += qDot[0] * (1.0f / filter->sample_freq); 8001928: ed97 7a0e vldr s14, [r7, #56] @ 0x38 800192c: edd7 6a0a vldr s13, [r7, #40] @ 0x28 8001930: 6a7b ldr r3, [r7, #36] @ 0x24 8001932: ed93 6a05 vldr s12, [r3, #20] 8001936: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 800193a: eec5 7a86 vdiv.f32 s15, s11, s12 800193e: ee66 7aa7 vmul.f32 s15, s13, s15 8001942: ee77 7a27 vadd.f32 s15, s14, s15 8001946: edc7 7a0e vstr s15, [r7, #56] @ 0x38 q[1] += qDot[1] * (1.0f / filter->sample_freq); 800194a: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 800194e: edd7 6a0b vldr s13, [r7, #44] @ 0x2c 8001952: 6a7b ldr r3, [r7, #36] @ 0x24 8001954: ed93 6a05 vldr s12, [r3, #20] 8001958: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 800195c: eec5 7a86 vdiv.f32 s15, s11, s12 8001960: ee66 7aa7 vmul.f32 s15, s13, s15 8001964: ee77 7a27 vadd.f32 s15, s14, s15 8001968: edc7 7a0f vstr s15, [r7, #60] @ 0x3c q[2] += qDot[2] * (1.0f / filter->sample_freq); 800196c: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001970: edd7 6a0c vldr s13, [r7, #48] @ 0x30 8001974: 6a7b ldr r3, [r7, #36] @ 0x24 8001976: ed93 6a05 vldr s12, [r3, #20] 800197a: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 800197e: eec5 7a86 vdiv.f32 s15, s11, s12 8001982: ee66 7aa7 vmul.f32 s15, s13, s15 8001986: ee77 7a27 vadd.f32 s15, s14, s15 800198a: edc7 7a10 vstr s15, [r7, #64] @ 0x40 q[3] += qDot[3] * (1.0f / filter->sample_freq); 800198e: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001992: edd7 6a0d vldr s13, [r7, #52] @ 0x34 8001996: 6a7b ldr r3, [r7, #36] @ 0x24 8001998: ed93 6a05 vldr s12, [r3, #20] 800199c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 80019a0: eec5 7a86 vdiv.f32 s15, s11, s12 80019a4: ee66 7aa7 vmul.f32 s15, s13, s15 80019a8: ee77 7a27 vadd.f32 s15, s14, s15 80019ac: edc7 7a11 vstr s15, [r7, #68] @ 0x44 // Normalise quaternion recipNorm = invSqrt(q[0] * q[0] + q[1] * q[1] + q[2] * q[2] + q[3] * q[3]); 80019b0: ed97 7a0e vldr s14, [r7, #56] @ 0x38 80019b4: edd7 7a0e vldr s15, [r7, #56] @ 0x38 80019b8: ee27 7a27 vmul.f32 s14, s14, s15 80019bc: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 80019c0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 80019c4: ee66 7aa7 vmul.f32 s15, s13, s15 80019c8: ee37 7a27 vadd.f32 s14, s14, s15 80019cc: edd7 6a10 vldr s13, [r7, #64] @ 0x40 80019d0: edd7 7a10 vldr s15, [r7, #64] @ 0x40 80019d4: ee66 7aa7 vmul.f32 s15, s13, s15 80019d8: ee37 7a27 vadd.f32 s14, s14, s15 80019dc: edd7 6a11 vldr s13, [r7, #68] @ 0x44 80019e0: edd7 7a11 vldr s15, [r7, #68] @ 0x44 80019e4: ee66 7aa7 vmul.f32 s15, s13, s15 80019e8: ee77 7a27 vadd.f32 s15, s14, s15 80019ec: eeb0 0a67 vmov.f32 s0, s15 80019f0: f000 fbba bl 8002168 80019f4: ed87 0a31 vstr s0, [r7, #196] @ 0xc4 q[0] *= recipNorm; 80019f8: ed97 7a0e vldr s14, [r7, #56] @ 0x38 80019fc: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001a00: ee67 7a27 vmul.f32 s15, s14, s15 8001a04: edc7 7a0e vstr s15, [r7, #56] @ 0x38 q[1] *= recipNorm; 8001a08: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001a0c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001a10: ee67 7a27 vmul.f32 s15, s14, s15 8001a14: edc7 7a0f vstr s15, [r7, #60] @ 0x3c q[2] *= recipNorm; 8001a18: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001a1c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001a20: ee67 7a27 vmul.f32 s15, s14, s15 8001a24: edc7 7a10 vstr s15, [r7, #64] @ 0x40 q[3] *= recipNorm; 8001a28: ed97 7a11 vldr s14, [r7, #68] @ 0x44 8001a2c: edd7 7a31 vldr s15, [r7, #196] @ 0xc4 8001a30: ee67 7a27 vmul.f32 s15, s14, s15 8001a34: edc7 7a11 vstr s15, [r7, #68] @ 0x44 // enforce hemisphere continuity (because of the positive and negative doubling of output) float dot = filter->q[0] * q[0] + filter->q[1] * q[1] + filter->q[2] * q[2] + filter->q[3] * q[3]; 8001a38: 6a7b ldr r3, [r7, #36] @ 0x24 8001a3a: ed93 7a00 vldr s14, [r3] 8001a3e: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001a42: ee27 7a27 vmul.f32 s14, s14, s15 8001a46: 6a7b ldr r3, [r7, #36] @ 0x24 8001a48: edd3 6a01 vldr s13, [r3, #4] 8001a4c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001a50: ee66 7aa7 vmul.f32 s15, s13, s15 8001a54: ee37 7a27 vadd.f32 s14, s14, s15 8001a58: 6a7b ldr r3, [r7, #36] @ 0x24 8001a5a: edd3 6a02 vldr s13, [r3, #8] 8001a5e: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001a62: ee66 7aa7 vmul.f32 s15, s13, s15 8001a66: ee37 7a27 vadd.f32 s14, s14, s15 8001a6a: 6a7b ldr r3, [r7, #36] @ 0x24 8001a6c: edd3 6a03 vldr s13, [r3, #12] 8001a70: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001a74: ee66 7aa7 vmul.f32 s15, s13, s15 8001a78: ee77 7a27 vadd.f32 s15, s14, s15 8001a7c: edc7 7a12 vstr s15, [r7, #72] @ 0x48 if (dot < 0.0f){ 8001a80: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001a84: eef5 7ac0 vcmpe.f32 s15, #0.0 8001a88: eef1 fa10 vmrs APSR_nzcv, fpscr 8001a8c: d517 bpl.n 8001abe q[0] = -q[0]; 8001a8e: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001a92: eef1 7a67 vneg.f32 s15, s15 8001a96: edc7 7a0e vstr s15, [r7, #56] @ 0x38 q[1] = -q[1]; 8001a9a: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001a9e: eef1 7a67 vneg.f32 s15, s15 8001aa2: edc7 7a0f vstr s15, [r7, #60] @ 0x3c q[2] = -q[2]; 8001aa6: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001aaa: eef1 7a67 vneg.f32 s15, s15 8001aae: edc7 7a10 vstr s15, [r7, #64] @ 0x40 q[3] = -q[3]; 8001ab2: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8001ab6: eef1 7a67 vneg.f32 s15, s15 8001aba: edc7 7a11 vstr s15, [r7, #68] @ 0x44 } // Update filter state filter->q[0] = q[0]; 8001abe: 6bba ldr r2, [r7, #56] @ 0x38 8001ac0: 6a7b ldr r3, [r7, #36] @ 0x24 8001ac2: 601a str r2, [r3, #0] filter->q[1] = q[1]; 8001ac4: 6bfa ldr r2, [r7, #60] @ 0x3c 8001ac6: 6a7b ldr r3, [r7, #36] @ 0x24 8001ac8: 605a str r2, [r3, #4] filter->q[2] = q[2]; 8001aca: 6c3a ldr r2, [r7, #64] @ 0x40 8001acc: 6a7b ldr r3, [r7, #36] @ 0x24 8001ace: 609a str r2, [r3, #8] filter->q[3] = q[3]; 8001ad0: 6c7a ldr r2, [r7, #68] @ 0x44 8001ad2: 6a7b ldr r3, [r7, #36] @ 0x24 8001ad4: 60da str r2, [r3, #12] } 8001ad6: 37c8 adds r7, #200 @ 0xc8 8001ad8: 46bd mov sp, r7 8001ada: bd80 pop {r7, pc} 08001adc : //--------------------------------------------------------------------------------------------------- // IMU algorithm update void MadgwickAHRS_update_IMU(MadgwickAHRS_Filter* filter, float gx, float gy, float gz, float ax, float ay, float az) { 8001adc: b580 push {r7, lr} 8001ade: b0a4 sub sp, #144 @ 0x90 8001ae0: af00 add r7, sp, #0 8001ae2: 61f8 str r0, [r7, #28] 8001ae4: ed87 0a06 vstr s0, [r7, #24] 8001ae8: edc7 0a05 vstr s1, [r7, #20] 8001aec: ed87 1a04 vstr s2, [r7, #16] 8001af0: edc7 1a03 vstr s3, [r7, #12] 8001af4: ed87 2a02 vstr s4, [r7, #8] 8001af8: edc7 2a01 vstr s5, [r7, #4] float q[4] = {filter->q[0], filter->q[1], filter->q[2], filter->q[3]}; 8001afc: 69fb ldr r3, [r7, #28] 8001afe: 681b ldr r3, [r3, #0] 8001b00: 637b str r3, [r7, #52] @ 0x34 8001b02: 69fb ldr r3, [r7, #28] 8001b04: 685b ldr r3, [r3, #4] 8001b06: 63bb str r3, [r7, #56] @ 0x38 8001b08: 69fb ldr r3, [r7, #28] 8001b0a: 689b ldr r3, [r3, #8] 8001b0c: 63fb str r3, [r7, #60] @ 0x3c 8001b0e: 69fb ldr r3, [r7, #28] 8001b10: 68db ldr r3, [r3, #12] 8001b12: 643b str r3, [r7, #64] @ 0x40 float s0, s1, s2, s3; float qDot[4]; float _2q0, _2q1, _2q2, _2q3, _4q0, _4q1, _4q2 ,_8q1, _8q2, q0q0, q1q1, q2q2, q3q3; // Rate of change of quaternion from gyroscope qDot[0] = 0.5f * (-q[1] * gx - q[2] * gy - q[3] * gz); 8001b14: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001b18: eeb1 7a67 vneg.f32 s14, s15 8001b1c: edd7 7a06 vldr s15, [r7, #24] 8001b20: ee27 7a27 vmul.f32 s14, s14, s15 8001b24: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001b28: edd7 7a05 vldr s15, [r7, #20] 8001b2c: ee66 7aa7 vmul.f32 s15, s13, s15 8001b30: ee37 7a67 vsub.f32 s14, s14, s15 8001b34: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8001b38: edd7 7a04 vldr s15, [r7, #16] 8001b3c: ee66 7aa7 vmul.f32 s15, s13, s15 8001b40: ee77 7a67 vsub.f32 s15, s14, s15 8001b44: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8001b48: ee67 7a87 vmul.f32 s15, s15, s14 8001b4c: edc7 7a09 vstr s15, [r7, #36] @ 0x24 qDot[1] = 0.5f * (q[0] * gx + q[2] * gz - q[3] * gy); 8001b50: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8001b54: edd7 7a06 vldr s15, [r7, #24] 8001b58: ee27 7a27 vmul.f32 s14, s14, s15 8001b5c: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001b60: edd7 7a04 vldr s15, [r7, #16] 8001b64: ee66 7aa7 vmul.f32 s15, s13, s15 8001b68: ee37 7a27 vadd.f32 s14, s14, s15 8001b6c: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8001b70: edd7 7a05 vldr s15, [r7, #20] 8001b74: ee66 7aa7 vmul.f32 s15, s13, s15 8001b78: ee77 7a67 vsub.f32 s15, s14, s15 8001b7c: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8001b80: ee67 7a87 vmul.f32 s15, s15, s14 8001b84: edc7 7a0a vstr s15, [r7, #40] @ 0x28 qDot[2] = 0.5f * (q[0] * gy - q[1] * gz + q[3] * gx); 8001b88: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8001b8c: edd7 7a05 vldr s15, [r7, #20] 8001b90: ee27 7a27 vmul.f32 s14, s14, s15 8001b94: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8001b98: edd7 7a04 vldr s15, [r7, #16] 8001b9c: ee66 7aa7 vmul.f32 s15, s13, s15 8001ba0: ee37 7a67 vsub.f32 s14, s14, s15 8001ba4: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8001ba8: edd7 7a06 vldr s15, [r7, #24] 8001bac: ee66 7aa7 vmul.f32 s15, s13, s15 8001bb0: ee77 7a27 vadd.f32 s15, s14, s15 8001bb4: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8001bb8: ee67 7a87 vmul.f32 s15, s15, s14 8001bbc: edc7 7a0b vstr s15, [r7, #44] @ 0x2c qDot[3] = 0.5f * (q[0] * gz + q[1] * gy - q[2] * gx); 8001bc0: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8001bc4: edd7 7a04 vldr s15, [r7, #16] 8001bc8: ee27 7a27 vmul.f32 s14, s14, s15 8001bcc: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8001bd0: edd7 7a05 vldr s15, [r7, #20] 8001bd4: ee66 7aa7 vmul.f32 s15, s13, s15 8001bd8: ee37 7a27 vadd.f32 s14, s14, s15 8001bdc: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8001be0: edd7 7a06 vldr s15, [r7, #24] 8001be4: ee66 7aa7 vmul.f32 s15, s13, s15 8001be8: ee77 7a67 vsub.f32 s15, s14, s15 8001bec: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 8001bf0: ee67 7a87 vmul.f32 s15, s15, s14 8001bf4: edc7 7a0c vstr s15, [r7, #48] @ 0x30 // Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation) if(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) { 8001bf8: edd7 7a03 vldr s15, [r7, #12] 8001bfc: eef5 7a40 vcmp.f32 s15, #0.0 8001c00: eef1 fa10 vmrs APSR_nzcv, fpscr 8001c04: d10e bne.n 8001c24 8001c06: edd7 7a02 vldr s15, [r7, #8] 8001c0a: eef5 7a40 vcmp.f32 s15, #0.0 8001c0e: eef1 fa10 vmrs APSR_nzcv, fpscr 8001c12: d107 bne.n 8001c24 8001c14: edd7 7a01 vldr s15, [r7, #4] 8001c18: eef5 7a40 vcmp.f32 s15, #0.0 8001c1c: eef1 fa10 vmrs APSR_nzcv, fpscr 8001c20: f000 81c6 beq.w 8001fb0 // Normalise accelerometer measurement recipNorm = invSqrt(ax * ax + ay * ay + az * az); 8001c24: edd7 7a03 vldr s15, [r7, #12] 8001c28: ee27 7aa7 vmul.f32 s14, s15, s15 8001c2c: edd7 7a02 vldr s15, [r7, #8] 8001c30: ee67 7aa7 vmul.f32 s15, s15, s15 8001c34: ee37 7a27 vadd.f32 s14, s14, s15 8001c38: edd7 7a01 vldr s15, [r7, #4] 8001c3c: ee67 7aa7 vmul.f32 s15, s15, s15 8001c40: ee77 7a27 vadd.f32 s15, s14, s15 8001c44: eeb0 0a67 vmov.f32 s0, s15 8001c48: f000 fa8e bl 8002168 8001c4c: ed87 0a23 vstr s0, [r7, #140] @ 0x8c ax *= recipNorm; 8001c50: ed97 7a03 vldr s14, [r7, #12] 8001c54: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001c58: ee67 7a27 vmul.f32 s15, s14, s15 8001c5c: edc7 7a03 vstr s15, [r7, #12] ay *= recipNorm; 8001c60: ed97 7a02 vldr s14, [r7, #8] 8001c64: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001c68: ee67 7a27 vmul.f32 s15, s14, s15 8001c6c: edc7 7a02 vstr s15, [r7, #8] az *= recipNorm; 8001c70: ed97 7a01 vldr s14, [r7, #4] 8001c74: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001c78: ee67 7a27 vmul.f32 s15, s14, s15 8001c7c: edc7 7a01 vstr s15, [r7, #4] // Auxiliary variables to avoid repeated arithmetic _2q0 = 2.0f * q[0]; 8001c80: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001c84: ee77 7aa7 vadd.f32 s15, s15, s15 8001c88: edc7 7a22 vstr s15, [r7, #136] @ 0x88 _2q1 = 2.0f * q[1]; 8001c8c: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001c90: ee77 7aa7 vadd.f32 s15, s15, s15 8001c94: edc7 7a21 vstr s15, [r7, #132] @ 0x84 _2q2 = 2.0f * q[2]; 8001c98: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001c9c: ee77 7aa7 vadd.f32 s15, s15, s15 8001ca0: edc7 7a20 vstr s15, [r7, #128] @ 0x80 _2q3 = 2.0f * q[3]; 8001ca4: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001ca8: ee77 7aa7 vadd.f32 s15, s15, s15 8001cac: edc7 7a1f vstr s15, [r7, #124] @ 0x7c _4q0 = 4.0f * q[0]; 8001cb0: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001cb4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001cb8: ee67 7a87 vmul.f32 s15, s15, s14 8001cbc: edc7 7a1e vstr s15, [r7, #120] @ 0x78 _4q1 = 4.0f * q[1]; 8001cc0: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001cc4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001cc8: ee67 7a87 vmul.f32 s15, s15, s14 8001ccc: edc7 7a1d vstr s15, [r7, #116] @ 0x74 _4q2 = 4.0f * q[2]; 8001cd0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001cd4: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001cd8: ee67 7a87 vmul.f32 s15, s15, s14 8001cdc: edc7 7a1c vstr s15, [r7, #112] @ 0x70 _8q1 = 8.0f * q[1]; 8001ce0: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001ce4: eeb2 7a00 vmov.f32 s14, #32 @ 0x41000000 8.0 8001ce8: ee67 7a87 vmul.f32 s15, s15, s14 8001cec: edc7 7a1b vstr s15, [r7, #108] @ 0x6c _8q2 = 8.0f * q[2]; 8001cf0: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001cf4: eeb2 7a00 vmov.f32 s14, #32 @ 0x41000000 8.0 8001cf8: ee67 7a87 vmul.f32 s15, s15, s14 8001cfc: edc7 7a1a vstr s15, [r7, #104] @ 0x68 q0q0 = q[0] * q[0]; 8001d00: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8001d04: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8001d08: ee67 7a27 vmul.f32 s15, s14, s15 8001d0c: edc7 7a19 vstr s15, [r7, #100] @ 0x64 q1q1 = q[1] * q[1]; 8001d10: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8001d14: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001d18: ee67 7a27 vmul.f32 s15, s14, s15 8001d1c: edc7 7a18 vstr s15, [r7, #96] @ 0x60 q2q2 = q[2] * q[2]; 8001d20: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001d24: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001d28: ee67 7a27 vmul.f32 s15, s14, s15 8001d2c: edc7 7a17 vstr s15, [r7, #92] @ 0x5c q3q3 = q[3] * q[3]; 8001d30: ed97 7a10 vldr s14, [r7, #64] @ 0x40 8001d34: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001d38: ee67 7a27 vmul.f32 s15, s14, s15 8001d3c: edc7 7a16 vstr s15, [r7, #88] @ 0x58 // Gradient decent algorithm corrective step s0 = _4q0 * q2q2 + _2q2 * ax + _4q0 * q1q1 - _2q1 * ay; 8001d40: ed97 7a1e vldr s14, [r7, #120] @ 0x78 8001d44: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8001d48: ee27 7a27 vmul.f32 s14, s14, s15 8001d4c: edd7 6a20 vldr s13, [r7, #128] @ 0x80 8001d50: edd7 7a03 vldr s15, [r7, #12] 8001d54: ee66 7aa7 vmul.f32 s15, s13, s15 8001d58: ee37 7a27 vadd.f32 s14, s14, s15 8001d5c: edd7 6a1e vldr s13, [r7, #120] @ 0x78 8001d60: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8001d64: ee66 7aa7 vmul.f32 s15, s13, s15 8001d68: ee37 7a27 vadd.f32 s14, s14, s15 8001d6c: edd7 6a21 vldr s13, [r7, #132] @ 0x84 8001d70: edd7 7a02 vldr s15, [r7, #8] 8001d74: ee66 7aa7 vmul.f32 s15, s13, s15 8001d78: ee77 7a67 vsub.f32 s15, s14, s15 8001d7c: edc7 7a15 vstr s15, [r7, #84] @ 0x54 s1 = _4q1 * q3q3 - _2q3 * ax + 4.0f * q0q0 * q[1] - _2q0 * ay - _4q1 + _8q1 * q1q1 + _8q1 * q2q2 + _4q1 * az; 8001d80: ed97 7a1d vldr s14, [r7, #116] @ 0x74 8001d84: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8001d88: ee27 7a27 vmul.f32 s14, s14, s15 8001d8c: edd7 6a1f vldr s13, [r7, #124] @ 0x7c 8001d90: edd7 7a03 vldr s15, [r7, #12] 8001d94: ee66 7aa7 vmul.f32 s15, s13, s15 8001d98: ee37 7a67 vsub.f32 s14, s14, s15 8001d9c: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001da0: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0 8001da4: ee67 6aa6 vmul.f32 s13, s15, s13 8001da8: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8001dac: ee66 7aa7 vmul.f32 s15, s13, s15 8001db0: ee37 7a27 vadd.f32 s14, s14, s15 8001db4: edd7 6a22 vldr s13, [r7, #136] @ 0x88 8001db8: edd7 7a02 vldr s15, [r7, #8] 8001dbc: ee66 7aa7 vmul.f32 s15, s13, s15 8001dc0: ee37 7a67 vsub.f32 s14, s14, s15 8001dc4: edd7 7a1d vldr s15, [r7, #116] @ 0x74 8001dc8: ee37 7a67 vsub.f32 s14, s14, s15 8001dcc: edd7 6a1b vldr s13, [r7, #108] @ 0x6c 8001dd0: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8001dd4: ee66 7aa7 vmul.f32 s15, s13, s15 8001dd8: ee37 7a27 vadd.f32 s14, s14, s15 8001ddc: edd7 6a1b vldr s13, [r7, #108] @ 0x6c 8001de0: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8001de4: ee66 7aa7 vmul.f32 s15, s13, s15 8001de8: ee37 7a27 vadd.f32 s14, s14, s15 8001dec: edd7 6a1d vldr s13, [r7, #116] @ 0x74 8001df0: edd7 7a01 vldr s15, [r7, #4] 8001df4: ee66 7aa7 vmul.f32 s15, s13, s15 8001df8: ee77 7a27 vadd.f32 s15, s14, s15 8001dfc: edc7 7a14 vstr s15, [r7, #80] @ 0x50 s2 = 4.0f * q0q0 * q[2] + _2q0 * ax + _4q2 * q3q3 - _2q3 * ay - _4q2 + _8q2 * q1q1 + _8q2 * q2q2 + _4q2 * az; 8001e00: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8001e04: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001e08: ee27 7a87 vmul.f32 s14, s15, s14 8001e0c: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8001e10: ee27 7a27 vmul.f32 s14, s14, s15 8001e14: edd7 6a22 vldr s13, [r7, #136] @ 0x88 8001e18: edd7 7a03 vldr s15, [r7, #12] 8001e1c: ee66 7aa7 vmul.f32 s15, s13, s15 8001e20: ee37 7a27 vadd.f32 s14, s14, s15 8001e24: edd7 6a1c vldr s13, [r7, #112] @ 0x70 8001e28: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8001e2c: ee66 7aa7 vmul.f32 s15, s13, s15 8001e30: ee37 7a27 vadd.f32 s14, s14, s15 8001e34: edd7 6a1f vldr s13, [r7, #124] @ 0x7c 8001e38: edd7 7a02 vldr s15, [r7, #8] 8001e3c: ee66 7aa7 vmul.f32 s15, s13, s15 8001e40: ee37 7a67 vsub.f32 s14, s14, s15 8001e44: edd7 7a1c vldr s15, [r7, #112] @ 0x70 8001e48: ee37 7a67 vsub.f32 s14, s14, s15 8001e4c: edd7 6a1a vldr s13, [r7, #104] @ 0x68 8001e50: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8001e54: ee66 7aa7 vmul.f32 s15, s13, s15 8001e58: ee37 7a27 vadd.f32 s14, s14, s15 8001e5c: edd7 6a1a vldr s13, [r7, #104] @ 0x68 8001e60: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8001e64: ee66 7aa7 vmul.f32 s15, s13, s15 8001e68: ee37 7a27 vadd.f32 s14, s14, s15 8001e6c: edd7 6a1c vldr s13, [r7, #112] @ 0x70 8001e70: edd7 7a01 vldr s15, [r7, #4] 8001e74: ee66 7aa7 vmul.f32 s15, s13, s15 8001e78: ee77 7a27 vadd.f32 s15, s14, s15 8001e7c: edc7 7a13 vstr s15, [r7, #76] @ 0x4c s3 = 4.0f * q1q1 * q[3] - _2q1 * ax + 4.0f * q2q2 * q[3] - _2q2 * ay; 8001e80: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8001e84: eeb1 7a00 vmov.f32 s14, #16 @ 0x40800000 4.0 8001e88: ee27 7a87 vmul.f32 s14, s15, s14 8001e8c: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001e90: ee27 7a27 vmul.f32 s14, s14, s15 8001e94: edd7 6a21 vldr s13, [r7, #132] @ 0x84 8001e98: edd7 7a03 vldr s15, [r7, #12] 8001e9c: ee66 7aa7 vmul.f32 s15, s13, s15 8001ea0: ee37 7a67 vsub.f32 s14, s14, s15 8001ea4: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8001ea8: eef1 6a00 vmov.f32 s13, #16 @ 0x40800000 4.0 8001eac: ee67 6aa6 vmul.f32 s13, s15, s13 8001eb0: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8001eb4: ee66 7aa7 vmul.f32 s15, s13, s15 8001eb8: ee37 7a27 vadd.f32 s14, s14, s15 8001ebc: edd7 6a20 vldr s13, [r7, #128] @ 0x80 8001ec0: edd7 7a02 vldr s15, [r7, #8] 8001ec4: ee66 7aa7 vmul.f32 s15, s13, s15 8001ec8: ee77 7a67 vsub.f32 s15, s14, s15 8001ecc: edc7 7a12 vstr s15, [r7, #72] @ 0x48 recipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude 8001ed0: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001ed4: ee27 7aa7 vmul.f32 s14, s15, s15 8001ed8: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001edc: ee67 7aa7 vmul.f32 s15, s15, s15 8001ee0: ee37 7a27 vadd.f32 s14, s14, s15 8001ee4: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 8001ee8: ee67 7aa7 vmul.f32 s15, s15, s15 8001eec: ee37 7a27 vadd.f32 s14, s14, s15 8001ef0: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001ef4: ee67 7aa7 vmul.f32 s15, s15, s15 8001ef8: ee77 7a27 vadd.f32 s15, s14, s15 8001efc: eeb0 0a67 vmov.f32 s0, s15 8001f00: f000 f932 bl 8002168 8001f04: ed87 0a23 vstr s0, [r7, #140] @ 0x8c s0 *= recipNorm; 8001f08: ed97 7a15 vldr s14, [r7, #84] @ 0x54 8001f0c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001f10: ee67 7a27 vmul.f32 s15, s14, s15 8001f14: edc7 7a15 vstr s15, [r7, #84] @ 0x54 s1 *= recipNorm; 8001f18: ed97 7a14 vldr s14, [r7, #80] @ 0x50 8001f1c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001f20: ee67 7a27 vmul.f32 s15, s14, s15 8001f24: edc7 7a14 vstr s15, [r7, #80] @ 0x50 s2 *= recipNorm; 8001f28: ed97 7a13 vldr s14, [r7, #76] @ 0x4c 8001f2c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001f30: ee67 7a27 vmul.f32 s15, s14, s15 8001f34: edc7 7a13 vstr s15, [r7, #76] @ 0x4c s3 *= recipNorm; 8001f38: ed97 7a12 vldr s14, [r7, #72] @ 0x48 8001f3c: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8001f40: ee67 7a27 vmul.f32 s15, s14, s15 8001f44: edc7 7a12 vstr s15, [r7, #72] @ 0x48 // Apply feedback step qDot[0] -= filter->beta * s0; 8001f48: ed97 7a09 vldr s14, [r7, #36] @ 0x24 8001f4c: 69fb ldr r3, [r7, #28] 8001f4e: edd3 6a04 vldr s13, [r3, #16] 8001f52: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8001f56: ee66 7aa7 vmul.f32 s15, s13, s15 8001f5a: ee77 7a67 vsub.f32 s15, s14, s15 8001f5e: edc7 7a09 vstr s15, [r7, #36] @ 0x24 qDot[1] -= filter->beta * s1; 8001f62: ed97 7a0a vldr s14, [r7, #40] @ 0x28 8001f66: 69fb ldr r3, [r7, #28] 8001f68: edd3 6a04 vldr s13, [r3, #16] 8001f6c: edd7 7a14 vldr s15, [r7, #80] @ 0x50 8001f70: ee66 7aa7 vmul.f32 s15, s13, s15 8001f74: ee77 7a67 vsub.f32 s15, s14, s15 8001f78: edc7 7a0a vstr s15, [r7, #40] @ 0x28 qDot[2] -= filter->beta * s2; 8001f7c: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 8001f80: 69fb ldr r3, [r7, #28] 8001f82: edd3 6a04 vldr s13, [r3, #16] 8001f86: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 8001f8a: ee66 7aa7 vmul.f32 s15, s13, s15 8001f8e: ee77 7a67 vsub.f32 s15, s14, s15 8001f92: edc7 7a0b vstr s15, [r7, #44] @ 0x2c qDot[3] -= filter->beta * s3; 8001f96: ed97 7a0c vldr s14, [r7, #48] @ 0x30 8001f9a: 69fb ldr r3, [r7, #28] 8001f9c: edd3 6a04 vldr s13, [r3, #16] 8001fa0: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8001fa4: ee66 7aa7 vmul.f32 s15, s13, s15 8001fa8: ee77 7a67 vsub.f32 s15, s14, s15 8001fac: edc7 7a0c vstr s15, [r7, #48] @ 0x30 } // Integrate rate of change of quaternion to yield quaternion q[0] += qDot[0] * (1.0f / filter->sample_freq); 8001fb0: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8001fb4: edd7 6a09 vldr s13, [r7, #36] @ 0x24 8001fb8: 69fb ldr r3, [r7, #28] 8001fba: ed93 6a05 vldr s12, [r3, #20] 8001fbe: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8001fc2: eec5 7a86 vdiv.f32 s15, s11, s12 8001fc6: ee66 7aa7 vmul.f32 s15, s13, s15 8001fca: ee77 7a27 vadd.f32 s15, s14, s15 8001fce: edc7 7a0d vstr s15, [r7, #52] @ 0x34 q[1] += qDot[1] * (1.0f / filter->sample_freq); 8001fd2: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8001fd6: edd7 6a0a vldr s13, [r7, #40] @ 0x28 8001fda: 69fb ldr r3, [r7, #28] 8001fdc: ed93 6a05 vldr s12, [r3, #20] 8001fe0: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8001fe4: eec5 7a86 vdiv.f32 s15, s11, s12 8001fe8: ee66 7aa7 vmul.f32 s15, s13, s15 8001fec: ee77 7a27 vadd.f32 s15, s14, s15 8001ff0: edc7 7a0e vstr s15, [r7, #56] @ 0x38 q[2] += qDot[2] * (1.0f / filter->sample_freq); 8001ff4: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 8001ff8: edd7 6a0b vldr s13, [r7, #44] @ 0x2c 8001ffc: 69fb ldr r3, [r7, #28] 8001ffe: ed93 6a05 vldr s12, [r3, #20] 8002002: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8002006: eec5 7a86 vdiv.f32 s15, s11, s12 800200a: ee66 7aa7 vmul.f32 s15, s13, s15 800200e: ee77 7a27 vadd.f32 s15, s14, s15 8002012: edc7 7a0f vstr s15, [r7, #60] @ 0x3c q[3] += qDot[3] * (1.0f / filter->sample_freq); 8002016: ed97 7a10 vldr s14, [r7, #64] @ 0x40 800201a: edd7 6a0c vldr s13, [r7, #48] @ 0x30 800201e: 69fb ldr r3, [r7, #28] 8002020: ed93 6a05 vldr s12, [r3, #20] 8002024: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8002028: eec5 7a86 vdiv.f32 s15, s11, s12 800202c: ee66 7aa7 vmul.f32 s15, s13, s15 8002030: ee77 7a27 vadd.f32 s15, s14, s15 8002034: edc7 7a10 vstr s15, [r7, #64] @ 0x40 // Normalise quaternion recipNorm = invSqrt(q[0] * q[0] + q[1] * q[1] + q[2] * q[2] + q[3] * q[3]); 8002038: ed97 7a0d vldr s14, [r7, #52] @ 0x34 800203c: edd7 7a0d vldr s15, [r7, #52] @ 0x34 8002040: ee27 7a27 vmul.f32 s14, s14, s15 8002044: edd7 6a0e vldr s13, [r7, #56] @ 0x38 8002048: edd7 7a0e vldr s15, [r7, #56] @ 0x38 800204c: ee66 7aa7 vmul.f32 s15, s13, s15 8002050: ee37 7a27 vadd.f32 s14, s14, s15 8002054: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8002058: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 800205c: ee66 7aa7 vmul.f32 s15, s13, s15 8002060: ee37 7a27 vadd.f32 s14, s14, s15 8002064: edd7 6a10 vldr s13, [r7, #64] @ 0x40 8002068: edd7 7a10 vldr s15, [r7, #64] @ 0x40 800206c: ee66 7aa7 vmul.f32 s15, s13, s15 8002070: ee77 7a27 vadd.f32 s15, s14, s15 8002074: eeb0 0a67 vmov.f32 s0, s15 8002078: f000 f876 bl 8002168 800207c: ed87 0a23 vstr s0, [r7, #140] @ 0x8c q[0] *= recipNorm; 8002080: ed97 7a0d vldr s14, [r7, #52] @ 0x34 8002084: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8002088: ee67 7a27 vmul.f32 s15, s14, s15 800208c: edc7 7a0d vstr s15, [r7, #52] @ 0x34 q[1] *= recipNorm; 8002090: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8002094: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 8002098: ee67 7a27 vmul.f32 s15, s14, s15 800209c: edc7 7a0e vstr s15, [r7, #56] @ 0x38 q[2] *= recipNorm; 80020a0: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 80020a4: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 80020a8: ee67 7a27 vmul.f32 s15, s14, s15 80020ac: edc7 7a0f vstr s15, [r7, #60] @ 0x3c q[3] *= recipNorm; 80020b0: ed97 7a10 vldr s14, [r7, #64] @ 0x40 80020b4: edd7 7a23 vldr s15, [r7, #140] @ 0x8c 80020b8: ee67 7a27 vmul.f32 s15, s14, s15 80020bc: edc7 7a10 vstr s15, [r7, #64] @ 0x40 // enforce hemisphere continuity (because of the positive and negative doubling of output) float dot = filter->q[0] * q[0] + filter->q[1] * q[1] + filter->q[2] * q[2] + filter->q[3] * q[3]; 80020c0: 69fb ldr r3, [r7, #28] 80020c2: ed93 7a00 vldr s14, [r3] 80020c6: edd7 7a0d vldr s15, [r7, #52] @ 0x34 80020ca: ee27 7a27 vmul.f32 s14, s14, s15 80020ce: 69fb ldr r3, [r7, #28] 80020d0: edd3 6a01 vldr s13, [r3, #4] 80020d4: edd7 7a0e vldr s15, [r7, #56] @ 0x38 80020d8: ee66 7aa7 vmul.f32 s15, s13, s15 80020dc: ee37 7a27 vadd.f32 s14, s14, s15 80020e0: 69fb ldr r3, [r7, #28] 80020e2: edd3 6a02 vldr s13, [r3, #8] 80020e6: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 80020ea: ee66 7aa7 vmul.f32 s15, s13, s15 80020ee: ee37 7a27 vadd.f32 s14, s14, s15 80020f2: 69fb ldr r3, [r7, #28] 80020f4: edd3 6a03 vldr s13, [r3, #12] 80020f8: edd7 7a10 vldr s15, [r7, #64] @ 0x40 80020fc: ee66 7aa7 vmul.f32 s15, s13, s15 8002100: ee77 7a27 vadd.f32 s15, s14, s15 8002104: edc7 7a11 vstr s15, [r7, #68] @ 0x44 if (dot < 0.0f){ 8002108: edd7 7a11 vldr s15, [r7, #68] @ 0x44 800210c: eef5 7ac0 vcmpe.f32 s15, #0.0 8002110: eef1 fa10 vmrs APSR_nzcv, fpscr 8002114: d517 bpl.n 8002146 q[0] = -q[0]; 8002116: edd7 7a0d vldr s15, [r7, #52] @ 0x34 800211a: eef1 7a67 vneg.f32 s15, s15 800211e: edc7 7a0d vstr s15, [r7, #52] @ 0x34 q[1] = -q[1]; 8002122: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8002126: eef1 7a67 vneg.f32 s15, s15 800212a: edc7 7a0e vstr s15, [r7, #56] @ 0x38 q[2] = -q[2]; 800212e: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8002132: eef1 7a67 vneg.f32 s15, s15 8002136: edc7 7a0f vstr s15, [r7, #60] @ 0x3c q[3] = -q[3]; 800213a: edd7 7a10 vldr s15, [r7, #64] @ 0x40 800213e: eef1 7a67 vneg.f32 s15, s15 8002142: edc7 7a10 vstr s15, [r7, #64] @ 0x40 } // Update filter state filter->q[0] = q[0]; 8002146: 6b7a ldr r2, [r7, #52] @ 0x34 8002148: 69fb ldr r3, [r7, #28] 800214a: 601a str r2, [r3, #0] filter->q[1] = q[1]; 800214c: 6bba ldr r2, [r7, #56] @ 0x38 800214e: 69fb ldr r3, [r7, #28] 8002150: 605a str r2, [r3, #4] filter->q[2] = q[2]; 8002152: 6bfa ldr r2, [r7, #60] @ 0x3c 8002154: 69fb ldr r3, [r7, #28] 8002156: 609a str r2, [r3, #8] filter->q[3] = q[3]; 8002158: 6c3a ldr r2, [r7, #64] @ 0x40 800215a: 69fb ldr r3, [r7, #28] 800215c: 60da str r2, [r3, #12] } 800215e: bf00 nop 8002160: 3790 adds r7, #144 @ 0x90 8002162: 46bd mov sp, r7 8002164: bd80 pop {r7, pc} ... 08002168 : //--------------------------------------------------------------------------------------------------- // Fast inverse square-root // See: http://en.wikipedia.org/wiki/Fast_inverse_square_root float invSqrt(float x) { 8002168: b480 push {r7} 800216a: b087 sub sp, #28 800216c: af00 add r7, sp, #0 800216e: ed87 0a01 vstr s0, [r7, #4] float halfx = 0.5f * x; 8002172: edd7 7a01 vldr s15, [r7, #4] 8002176: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 800217a: ee67 7a87 vmul.f32 s15, s15, s14 800217e: edc7 7a05 vstr s15, [r7, #20] float y = x; 8002182: 687b ldr r3, [r7, #4] 8002184: 613b str r3, [r7, #16] long i = *(long*)&y; 8002186: f107 0310 add.w r3, r7, #16 800218a: 681b ldr r3, [r3, #0] 800218c: 60fb str r3, [r7, #12] i = 0x5f3759df - (i>>1); 800218e: 68fb ldr r3, [r7, #12] 8002190: 105a asrs r2, r3, #1 8002192: 4b12 ldr r3, [pc, #72] @ (80021dc ) 8002194: 1a9b subs r3, r3, r2 8002196: 60fb str r3, [r7, #12] y = *(float*)&i; 8002198: f107 030c add.w r3, r7, #12 800219c: 681b ldr r3, [r3, #0] 800219e: 613b str r3, [r7, #16] y = y * (1.5f - (halfx * y * y)); 80021a0: ed97 7a04 vldr s14, [r7, #16] 80021a4: edd7 7a05 vldr s15, [r7, #20] 80021a8: ee27 7a27 vmul.f32 s14, s14, s15 80021ac: edd7 7a04 vldr s15, [r7, #16] 80021b0: ee67 7a27 vmul.f32 s15, s14, s15 80021b4: eeb7 7a08 vmov.f32 s14, #120 @ 0x3fc00000 1.5 80021b8: ee37 7a67 vsub.f32 s14, s14, s15 80021bc: edd7 7a04 vldr s15, [r7, #16] 80021c0: ee67 7a27 vmul.f32 s15, s14, s15 80021c4: edc7 7a04 vstr s15, [r7, #16] return y; 80021c8: 693b ldr r3, [r7, #16] 80021ca: ee07 3a90 vmov s15, r3 } 80021ce: eeb0 0a67 vmov.f32 s0, s15 80021d2: 371c adds r7, #28 80021d4: 46bd mov sp, r7 80021d6: f85d 7b04 ldr.w r7, [sp], #4 80021da: 4770 bx lr 80021dc: 5f3759df .word 0x5f3759df 080021e0 : /* USER CODE END APPD_Init */ return; } void APPD_EnableCPU2( void ) { 80021e0: b5b0 push {r4, r5, r7, lr} 80021e2: b088 sub sp, #32 80021e4: af00 add r7, sp, #0 /* USER CODE BEGIN APPD_EnableCPU2 */ SHCI_C2_DEBUG_Init_Cmd_Packet_t DebugCmdPacket = 80021e6: 4b0b ldr r3, [pc, #44] @ (8002214 ) 80021e8: 1d3c adds r4, r7, #4 80021ea: 461d mov r5, r3 80021ec: cd0f ldmia r5!, {r0, r1, r2, r3} 80021ee: c40f stmia r4!, {r0, r1, r2, r3} 80021f0: e895 0007 ldmia.w r5, {r0, r1, r2} 80021f4: c403 stmia r4!, {r0, r1} 80021f6: 8022 strh r2, [r4, #0] 80021f8: 3402 adds r4, #2 80021fa: 0c13 lsrs r3, r2, #16 80021fc: 7023 strb r3, [r4, #0] NBR_OF_TRACES_CONFIG_PARAMETERS, NBR_OF_GENERAL_CONFIG_PARAMETERS} }; /**< Traces channel initialization */ TL_TRACES_Init( ); 80021fe: f011 f977 bl 80134f0 /** GPIO DEBUG Initialization */ SHCI_C2_DEBUG_Init( &DebugCmdPacket ); 8002202: 1d3b adds r3, r7, #4 8002204: 4618 mov r0, r3 8002206: f010 fdf0 bl 8012dea /* USER CODE END APPD_EnableCPU2 */ return; 800220a: bf00 nop } 800220c: 3720 adds r7, #32 800220e: 46bd mov sp, r7 8002210: bdb0 pop {r4, r5, r7, pc} 8002212: bf00 nop 8002214: 0801ddd8 .word 0x0801ddd8 08002218 : * * (*) Not available on devices STM32WB15xx, STM32WB10xx, STM32WB1Mxx * @retval None */ __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode) { 8002218: b480 push {r7} 800221a: b083 sub sp, #12 800221c: af00 add r7, sp, #0 800221e: 6078 str r0, [r7, #4] MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode); 8002220: 4b07 ldr r3, [pc, #28] @ (8002240 ) 8002222: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8002226: f023 0207 bic.w r2, r3, #7 800222a: 4905 ldr r1, [pc, #20] @ (8002240 ) 800222c: 687b ldr r3, [r7, #4] 800222e: 4313 orrs r3, r2 8002230: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } 8002234: bf00 nop 8002236: 370c adds r7, #12 8002238: 46bd mov sp, r7 800223a: f85d 7b04 ldr.w r7, [sp], #4 800223e: 4770 bx lr 8002240: 58000400 .word 0x58000400 08002244 : * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) { 8002244: b480 push {r7} 8002246: b083 sub sp, #12 8002248: af00 add r7, sp, #0 800224a: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR2, ExtiLine); 800224c: 4b06 ldr r3, [pc, #24] @ (8002268 ) 800224e: f8d3 2090 ldr.w r2, [r3, #144] @ 0x90 8002252: 4905 ldr r1, [pc, #20] @ (8002268 ) 8002254: 687b ldr r3, [r7, #4] 8002256: 4313 orrs r3, r2 8002258: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 800225c: bf00 nop 800225e: 370c adds r7, #12 8002260: 46bd mov sp, r7 8002262: f85d 7b04 ldr.w r7, [sp], #4 8002266: 4770 bx lr 8002268: 58000800 .word 0x58000800 0800226c : * @rmtoll HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning * @param Value Between Min_Data = 0 and Max_Data = 63 * @retval None */ __STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value) { 800226c: b480 push {r7} 800226e: b083 sub sp, #12 8002270: af00 add r7, sp, #0 8002272: 6078 str r0, [r7, #4] WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY); 8002274: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002278: 4a0a ldr r2, [pc, #40] @ (80022a4 ) 800227a: f8c3 209c str.w r2, [r3, #156] @ 0x9c MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos); 800227e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8002282: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 8002286: f423 527c bic.w r2, r3, #16128 @ 0x3f00 800228a: 687b ldr r3, [r7, #4] 800228c: 021b lsls r3, r3, #8 800228e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8002292: 4313 orrs r3, r2 8002294: f8c1 309c str.w r3, [r1, #156] @ 0x9c } 8002298: bf00 nop 800229a: 370c adds r7, #12 800229c: 46bd mov sp, r7 800229e: f85d 7b04 ldr.w r7, [sp], #4 80022a2: 4770 bx lr 80022a4: cafecafe .word 0xcafecafe 080022a8 : * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI * @retval None */ __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) { 80022a8: b480 push {r7} 80022aa: b083 sub sp, #12 80022ac: af00 add r7, sp, #0 80022ae: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); 80022b0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80022b4: 689b ldr r3, [r3, #8] 80022b6: f423 4200 bic.w r2, r3, #32768 @ 0x8000 80022ba: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80022be: 687b ldr r3, [r7, #4] 80022c0: 4313 orrs r3, r2 80022c2: 608b str r3, [r1, #8] } 80022c4: bf00 nop 80022c6: 370c adds r7, #12 80022c8: 46bd mov sp, r7 80022ca: f85d 7b04 ldr.w r7, [sp], #4 80022ce: 4770 bx lr 080022d0 : * @note For STM32WBxxxx devices, the device ID is 0x495 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID * @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495) */ __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) { 80022d0: b480 push {r7} 80022d2: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); 80022d4: 4b04 ldr r3, [pc, #16] @ (80022e8 ) 80022d6: 681b ldr r3, [r3, #0] 80022d8: f3c3 030b ubfx r3, r3, #0, #12 } 80022dc: 4618 mov r0, r3 80022de: 46bd mov sp, r7 80022e0: f85d 7b04 ldr.w r7, [sp], #4 80022e4: 4770 bx lr 80022e6: bf00 nop 80022e8: e0042000 .word 0xe0042000 080022ec : * @note This field indicates the revision of the device. * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF */ __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) { 80022ec: b480 push {r7} 80022ee: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); 80022f0: 4b04 ldr r3, [pc, #16] @ (8002304 ) 80022f2: 681b ldr r3, [r3, #0] 80022f4: 0c1b lsrs r3, r3, #16 80022f6: b29b uxth r3, r3 } 80022f8: 4618 mov r0, r3 80022fa: 46bd mov sp, r7 80022fc: f85d 7b04 ldr.w r7, [sp], #4 8002300: 4770 bx lr 8002302: bf00 nop 8002304: e0042000 .word 0xe0042000 08002308 : * @rmtoll WPR KEY LL_RTC_EnableWriteProtection * @param RTCx RTC Instance * @retval None */ __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) { 8002308: b480 push {r7} 800230a: b083 sub sp, #12 800230c: af00 add r7, sp, #0 800230e: 6078 str r0, [r7, #4] WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); 8002310: 687b ldr r3, [r7, #4] 8002312: 22ff movs r2, #255 @ 0xff 8002314: 625a str r2, [r3, #36] @ 0x24 } 8002316: bf00 nop 8002318: 370c adds r7, #12 800231a: 46bd mov sp, r7 800231c: f85d 7b04 ldr.w r7, [sp], #4 8002320: 4770 bx lr 08002322 : * @rmtoll WPR KEY LL_RTC_DisableWriteProtection * @param RTCx RTC Instance * @retval None */ __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) { 8002322: b480 push {r7} 8002324: b083 sub sp, #12 8002326: af00 add r7, sp, #0 8002328: 6078 str r0, [r7, #4] WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); 800232a: 687b ldr r3, [r7, #4] 800232c: 22ca movs r2, #202 @ 0xca 800232e: 625a str r2, [r3, #36] @ 0x24 WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); 8002330: 687b ldr r3, [r7, #4] 8002332: 2253 movs r2, #83 @ 0x53 8002334: 625a str r2, [r3, #36] @ 0x24 } 8002336: bf00 nop 8002338: 370c adds r7, #12 800233a: 46bd mov sp, r7 800233c: f85d 7b04 ldr.w r7, [sp], #4 8002340: 4770 bx lr 08002342 : * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT * @retval None */ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) { 8002342: b480 push {r7} 8002344: b083 sub sp, #12 8002346: af00 add r7, sp, #0 8002348: 6078 str r0, [r7, #4] 800234a: 6039 str r1, [r7, #0] MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); 800234c: 687b ldr r3, [r7, #4] 800234e: 689b ldr r3, [r3, #8] 8002350: f023 0207 bic.w r2, r3, #7 8002354: 683b ldr r3, [r7, #0] 8002356: 431a orrs r2, r3 8002358: 687b ldr r3, [r7, #4] 800235a: 609a str r2, [r3, #8] } 800235c: bf00 nop 800235e: 370c adds r7, #12 8002360: 46bd mov sp, r7 8002362: f85d 7b04 ldr.w r7, [sp], #4 8002366: 4770 bx lr 08002368 : /* USER CODE END PFP */ /* Functions Definition ------------------------------------------------------*/ void MX_APPE_Config(void) { 8002368: b580 push {r7, lr} 800236a: af00 add r7, sp, #0 /** * The OPTVERR flag is wrongly set at power on * It shall be cleared before using any HAL_FLASH_xxx() api */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); 800236c: 4b04 ldr r3, [pc, #16] @ (8002380 ) 800236e: f44f 4200 mov.w r2, #32768 @ 0x8000 8002372: 611a str r2, [r3, #16] /** * Reset some configurations so that the system behave in the same way * when either out of nReset or Power On */ Reset_Device(); 8002374: f000 f824 bl 80023c0 /* Configure HSE Tuning */ Config_HSE(); 8002378: f000 f829 bl 80023ce return; 800237c: bf00 nop } 800237e: bd80 pop {r7, pc} 8002380: 58004000 .word 0x58004000 08002384 : void MX_APPE_Init(void) { 8002384: b580 push {r7, lr} 8002386: af00 add r7, sp, #0 System_Init(); /**< System initialization */ 8002388: f000 f835 bl 80023f6 SystemPower_Config(); /**< Configure the system Power Mode */ 800238c: f000 f84e bl 800242c HW_TS_Init(hw_ts_InitMode_Full, &hrtc); /**< Initialize the TimerServer */ 8002390: 4903 ldr r1, [pc, #12] @ (80023a0 ) 8002392: 2000 movs r0, #0 8002394: f001 ffd6 bl 8004344 /* USER CODE BEGIN APPE_Init_1 */ /* USER CODE END APPE_Init_1 */ appe_Tl_Init(); /* Initialize all transport layers */ 8002398: f000 f856 bl 8002448 */ /* USER CODE BEGIN APPE_Init_2 */ /* USER CODE END APPE_Init_2 */ return; 800239c: bf00 nop } 800239e: bd80 pop {r7, pc} 80023a0: 20000504 .word 0x20000504 080023a4 : void Init_Smps(void) { 80023a4: b480 push {r7} 80023a6: af00 add r7, sp, #0 LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA); LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40); LL_PWR_SMPS_Enable(); #endif /* CFG_USE_SMPS != 0 */ return; 80023a8: bf00 nop } 80023aa: 46bd mov sp, r7 80023ac: f85d 7b04 ldr.w r7, [sp], #4 80023b0: 4770 bx lr 080023b2 : void Init_Exti(void) { 80023b2: b580 push {r7, lr} 80023b4: af00 add r7, sp, #0 /* Enable IPCC(36), HSEM(38) wakeup interrupts on CPU1 */ LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_36 | LL_EXTI_LINE_38); 80023b6: 2050 movs r0, #80 @ 0x50 80023b8: f7ff ff44 bl 8002244 return; 80023bc: bf00 nop } 80023be: bd80 pop {r7, pc} 080023c0 : * * LOCAL FUNCTIONS * *************************************************************/ static void Reset_Device(void) { 80023c0: b480 push {r7} 80023c2: af00 add r7, sp, #0 Reset_BackupDomain(); Reset_IPCC(); #endif /* CFG_HW_RESET_BY_FW == 1 */ return; 80023c4: bf00 nop } 80023c6: 46bd mov sp, r7 80023c8: f85d 7b04 ldr.w r7, [sp], #4 80023cc: 4770 bx lr 080023ce : return; } #endif /* CFG_HW_RESET_BY_FW == 1 */ static void Config_HSE(void) { 80023ce: b580 push {r7, lr} 80023d0: b082 sub sp, #8 80023d2: af00 add r7, sp, #0 OTP_ID0_t * p_otp; /** * Read HSE_Tuning from OTP */ p_otp = (OTP_ID0_t *) OTP_Read(0); 80023d4: 2000 movs r0, #0 80023d6: f011 f91f bl 8013618 80023da: 6078 str r0, [r7, #4] if (p_otp) 80023dc: 687b ldr r3, [r7, #4] 80023de: 2b00 cmp r3, #0 80023e0: d005 beq.n 80023ee { LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning); 80023e2: 687b ldr r3, [r7, #4] 80023e4: 799b ldrb r3, [r3, #6] 80023e6: 4618 mov r0, r3 80023e8: f7ff ff40 bl 800226c } return; 80023ec: bf00 nop 80023ee: bf00 nop } 80023f0: 3708 adds r7, #8 80023f2: 46bd mov sp, r7 80023f4: bd80 pop {r7, pc} 080023f6 : static void System_Init(void) { 80023f6: b580 push {r7, lr} 80023f8: af00 add r7, sp, #0 Init_Smps(); 80023fa: f7ff ffd3 bl 80023a4 Init_Exti(); 80023fe: f7ff ffd8 bl 80023b2 Init_Rtc(); 8002402: f000 f803 bl 800240c return; 8002406: bf00 nop } 8002408: bd80 pop {r7, pc} ... 0800240c : static void Init_Rtc(void) { 800240c: b580 push {r7, lr} 800240e: af00 add r7, sp, #0 /* Disable RTC registers write protection */ LL_RTC_DisableWriteProtection(RTC); 8002410: 4805 ldr r0, [pc, #20] @ (8002428 ) 8002412: f7ff ff86 bl 8002322 LL_RTC_WAKEUP_SetClock(RTC, CFG_RTC_WUCKSEL_DIVIDER); 8002416: 2100 movs r1, #0 8002418: 4803 ldr r0, [pc, #12] @ (8002428 ) 800241a: f7ff ff92 bl 8002342 /* Enable RTC registers write protection */ LL_RTC_EnableWriteProtection(RTC); 800241e: 4802 ldr r0, [pc, #8] @ (8002428 ) 8002420: f7ff ff72 bl 8002308 return; 8002424: bf00 nop } 8002426: bd80 pop {r7, pc} 8002428: 40002800 .word 0x40002800 0800242c : * * @param None * @retval None */ static void SystemPower_Config(void) { 800242c: b580 push {r7, lr} 800242e: af00 add r7, sp, #0 /** * Select HSI as system clock source after Wake Up from Stop mode */ LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI); 8002430: f44f 4000 mov.w r0, #32768 @ 0x8000 8002434: f7ff ff38 bl 80022a8 /* Initialize low power manager */ UTIL_LPM_Init(); 8002438: f016 ff6e bl 8019318 /* Initialize the CPU2 reset value before starting CPU2 with C2BOOT */ LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN); 800243c: 2004 movs r0, #4 800243e: f7ff feeb bl 8002218 * Enable USB power */ HAL_PWREx_EnableVddUSB(); #endif /* CFG_USB_INTERFACE_ENABLE != 0 */ return; 8002442: bf00 nop } 8002444: bd80 pop {r7, pc} ... 08002448 : static void appe_Tl_Init(void) { 8002448: b580 push {r7, lr} 800244a: b088 sub sp, #32 800244c: af00 add r7, sp, #0 TL_MM_Config_t tl_mm_config; SHCI_TL_HciInitConf_t SHci_Tl_Init_Conf; /**< Reference table initialization */ TL_Init(); 800244e: f010 fee5 bl 801321c MtxShciId = osMutexNew(NULL); 8002452: 2000 movs r0, #0 8002454: f011 fbf7 bl 8013c46 8002458: 4603 mov r3, r0 800245a: 4a17 ldr r2, [pc, #92] @ (80024b8 ) 800245c: 6013 str r3, [r2, #0] SemShciId = osSemaphoreNew(1, 0, NULL); /*< Create the semaphore and make it busy at initialization */ 800245e: 2200 movs r2, #0 8002460: 2100 movs r1, #0 8002462: 2001 movs r0, #1 8002464: f011 fcfa bl 8013e5c 8002468: 4603 mov r3, r0 800246a: 4a14 ldr r2, [pc, #80] @ (80024bc ) 800246c: 6013 str r3, [r2, #0] /** FreeRTOS system task creation */ ShciUserEvtProcessId = osThreadNew(ShciUserEvtProcess, NULL, &ShciUserEvtProcess_attr); 800246e: 4a14 ldr r2, [pc, #80] @ (80024c0 ) 8002470: 2100 movs r1, #0 8002472: 4814 ldr r0, [pc, #80] @ (80024c4 ) 8002474: f011 fa70 bl 8013958 8002478: 4603 mov r3, r0 800247a: 4a13 ldr r2, [pc, #76] @ (80024c8 ) 800247c: 6013 str r3, [r2, #0] /**< System channel initialization */ SHci_Tl_Init_Conf.p_cmdbuffer = (uint8_t*)&SystemCmdBuffer; 800247e: 4b13 ldr r3, [pc, #76] @ (80024cc ) 8002480: 603b str r3, [r7, #0] SHci_Tl_Init_Conf.StatusNotCallBack = APPE_SysStatusNot; 8002482: 4b13 ldr r3, [pc, #76] @ (80024d0 ) 8002484: 607b str r3, [r7, #4] shci_init(APPE_SysUserEvtRx, (void*) &SHci_Tl_Init_Conf); 8002486: 463b mov r3, r7 8002488: 4619 mov r1, r3 800248a: 4812 ldr r0, [pc, #72] @ (80024d4 ) 800248c: f010 fd88 bl 8012fa0 /**< Memory Manager channel initialization */ tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer; 8002490: 4b11 ldr r3, [pc, #68] @ (80024d8 ) 8002492: 60bb str r3, [r7, #8] tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer; 8002494: 4b11 ldr r3, [pc, #68] @ (80024dc ) 8002496: 60fb str r3, [r7, #12] tl_mm_config.p_AsynchEvtPool = EvtPool; 8002498: 4b11 ldr r3, [pc, #68] @ (80024e0 ) 800249a: 613b str r3, [r7, #16] tl_mm_config.AsynchEvtPoolSize = POOL_SIZE; 800249c: f240 533c movw r3, #1340 @ 0x53c 80024a0: 617b str r3, [r7, #20] TL_MM_Init(&tl_mm_config); 80024a2: f107 0308 add.w r3, r7, #8 80024a6: 4618 mov r0, r3 80024a8: f010 ffae bl 8013408 TL_Enable(); 80024ac: f010 feb0 bl 8013210 return; 80024b0: bf00 nop } 80024b2: 3720 adds r7, #32 80024b4: 46bd mov sp, r7 80024b6: bd80 pop {r7, pc} 80024b8: 20000308 .word 0x20000308 80024bc: 2000030c .word 0x2000030c 80024c0: 0801e48c .word 0x0801e48c 80024c4: 08002647 .word 0x08002647 80024c8: 20000310 .word 0x20000310 80024cc: 20030628 .word 0x20030628 80024d0: 080024f5 .word 0x080024f5 80024d4: 08002535 .word 0x08002535 80024d8: 20030840 .word 0x20030840 80024dc: 20030734 .word 0x20030734 80024e0: 200300ec .word 0x200300ec 080024e4 : __WEAK void APP_BLE_Init(void) { 80024e4: b480 push {r7} 80024e6: af00 add r7, sp, #0 } 80024e8: bf00 nop 80024ea: 46bd mov sp, r7 80024ec: f85d 7b04 ldr.w r7, [sp], #4 80024f0: 4770 bx lr ... 080024f4 : static void APPE_SysStatusNot(SHCI_TL_CmdStatus_t status) { 80024f4: b580 push {r7, lr} 80024f6: b082 sub sp, #8 80024f8: af00 add r7, sp, #0 80024fa: 4603 mov r3, r0 80024fc: 71fb strb r3, [r7, #7] switch (status) 80024fe: 79fb ldrb r3, [r7, #7] 8002500: 2b00 cmp r3, #0 8002502: d002 beq.n 800250a 8002504: 2b01 cmp r3, #1 8002506: d008 beq.n 800251a case SHCI_TL_CmdAvailable: osMutexRelease(MtxShciId); break; default: break; 8002508: e00d b.n 8002526 osMutexAcquire(MtxShciId, osWaitForever); 800250a: 4b09 ldr r3, [pc, #36] @ (8002530 ) 800250c: 681b ldr r3, [r3, #0] 800250e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002512: 4618 mov r0, r3 8002514: f011 fc1c bl 8013d50 break; 8002518: e005 b.n 8002526 osMutexRelease(MtxShciId); 800251a: 4b05 ldr r3, [pc, #20] @ (8002530 ) 800251c: 681b ldr r3, [r3, #0] 800251e: 4618 mov r0, r3 8002520: f011 fc60 bl 8013de4 break; 8002524: bf00 nop } return; 8002526: bf00 nop } 8002528: 3708 adds r7, #8 800252a: 46bd mov sp, r7 800252c: bd80 pop {r7, pc} 800252e: bf00 nop 8002530: 20000308 .word 0x20000308 08002534 : * The buffer shall not be released * (eg ((tSHCI_UserEvtRxParam*)pPayload)->status shall be set to SHCI_TL_UserEventFlow_Disable) * When the status is not filled, the buffer is released by default */ static void APPE_SysUserEvtRx(void * pPayload) { 8002534: b580 push {r7, lr} 8002536: b088 sub sp, #32 8002538: af00 add r7, sp, #0 800253a: 6078 str r0, [r7, #4] TL_AsynchEvt_t *p_sys_event; WirelessFwInfo_t WirelessInfo; p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); 800253c: 687b ldr r3, [r7, #4] 800253e: 685b ldr r3, [r3, #4] 8002540: 330b adds r3, #11 8002542: 61fb str r3, [r7, #28] switch(p_sys_event->subevtcode) 8002544: 69fb ldr r3, [r7, #28] 8002546: 881b ldrh r3, [r3, #0] 8002548: b29b uxth r3, r3 800254a: f5a3 4312 sub.w r3, r3, #37376 @ 0x9200 800254e: 2b07 cmp r3, #7 8002550: d81f bhi.n 8002592 8002552: a201 add r2, pc, #4 @ (adr r2, 8002558 ) 8002554: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002558: 08002579 .word 0x08002579 800255c: 0800258b .word 0x0800258b 8002560: 08002593 .word 0x08002593 8002564: 08002593 .word 0x08002593 8002568: 08002593 .word 0x08002593 800256c: 08002593 .word 0x08002593 8002570: 08002593 .word 0x08002593 8002574: 08002593 .word 0x08002593 { case SHCI_SUB_EVT_CODE_READY: /* Read the firmware version of both the wireless firmware and the FUS */ SHCI_GetWirelessFwInfo(&WirelessInfo); 8002578: f107 030c add.w r3, r7, #12 800257c: 4618 mov r0, r3 800257e: f010 fc61 bl 8012e44 APP_DBG_MSG("Wireless Firmware version %d.%d.%d\n", WirelessInfo.VersionMajor, WirelessInfo.VersionMinor, WirelessInfo.VersionSub); APP_DBG_MSG("Wireless Firmware build %d\n", WirelessInfo.VersionReleaseType); APP_DBG_MSG("FUS version %d.%d.%d\n", WirelessInfo.FusVersionMajor, WirelessInfo.FusVersionMinor, WirelessInfo.FusVersionSub); APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY\n\r"); APPE_SysEvtReadyProcessing(pPayload); 8002582: 6878 ldr r0, [r7, #4] 8002584: f000 f81b bl 80025be break; 8002588: e004 b.n 8002594 case SHCI_SUB_EVT_ERROR_NOTIF: APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF \n\r"); APPE_SysEvtError(pPayload); 800258a: 6878 ldr r0, [r7, #4] 800258c: f000 f806 bl 800259c break; 8002590: e000 b.n 8002594 case SHCI_SUB_EVT_NVM_END_ERASE: APP_DBG_MSG(">>== SHCI_SUB_EVT_NVM_END_ERASE\n\r"); break; default: break; 8002592: bf00 nop } return; 8002594: bf00 nop } 8002596: 3720 adds r7, #32 8002598: 46bd mov sp, r7 800259a: bd80 pop {r7, pc} 0800259c : * @param ErrorCode : errorCode detected by the M0 firmware * * @retval None */ static void APPE_SysEvtError(void * pPayload) { 800259c: b480 push {r7} 800259e: b085 sub sp, #20 80025a0: af00 add r7, sp, #0 80025a2: 6078 str r0, [r7, #4] TL_AsynchEvt_t *p_sys_event; SCHI_SystemErrCode_t *p_sys_error_code; p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); 80025a4: 687b ldr r3, [r7, #4] 80025a6: 685b ldr r3, [r3, #4] 80025a8: 330b adds r3, #11 80025aa: 60fb str r3, [r7, #12] p_sys_error_code = (SCHI_SystemErrCode_t*) p_sys_event->payload; 80025ac: 68fb ldr r3, [r7, #12] 80025ae: 3302 adds r3, #2 80025b0: 60bb str r3, [r7, #8] } else { APP_DBG_MSG(">>== SHCI_SUB_EVT_ERROR_NOTIF WITH REASON - BLE ERROR \n"); } return; 80025b2: bf00 nop } 80025b4: 3714 adds r7, #20 80025b6: 46bd mov sp, r7 80025b8: f85d 7b04 ldr.w r7, [sp], #4 80025bc: 4770 bx lr 080025be : static void APPE_SysEvtReadyProcessing(void * pPayload) { 80025be: b580 push {r7, lr} 80025c0: b08a sub sp, #40 @ 0x28 80025c2: af00 add r7, sp, #0 80025c4: 6078 str r0, [r7, #4] TL_AsynchEvt_t *p_sys_event; SHCI_C2_Ready_Evt_t *p_sys_ready_event; SHCI_C2_CONFIG_Cmd_Param_t config_param = {0}; 80025c6: f107 0308 add.w r3, r7, #8 80025ca: 2200 movs r2, #0 80025cc: 601a str r2, [r3, #0] 80025ce: 605a str r2, [r3, #4] 80025d0: 609a str r2, [r3, #8] 80025d2: 60da str r2, [r3, #12] uint32_t RevisionID=0; 80025d4: 2300 movs r3, #0 80025d6: 627b str r3, [r7, #36] @ 0x24 uint32_t DeviceID=0; 80025d8: 2300 movs r3, #0 80025da: 623b str r3, [r7, #32] p_sys_event = (TL_AsynchEvt_t*)(((tSHCI_UserEvtRxParam*)pPayload)->pckt->evtserial.evt.payload); 80025dc: 687b ldr r3, [r7, #4] 80025de: 685b ldr r3, [r3, #4] 80025e0: 330b adds r3, #11 80025e2: 61fb str r3, [r7, #28] p_sys_ready_event = (SHCI_C2_Ready_Evt_t*) p_sys_event->payload; 80025e4: 69fb ldr r3, [r7, #28] 80025e6: 3302 adds r3, #2 80025e8: 61bb str r3, [r7, #24] if (p_sys_ready_event->sysevt_ready_rsp == WIRELESS_FW_RUNNING) 80025ea: 69bb ldr r3, [r7, #24] 80025ec: 781b ldrb r3, [r3, #0] 80025ee: 2b00 cmp r3, #0 80025f0: d11d bne.n 800262e * The wireless firmware is running on the CPU2 */ APP_DBG_MSG(">>== WIRELESS_FW_RUNNING \n"); /* Traces channel initialization */ APPD_EnableCPU2(); 80025f2: f7ff fdf5 bl 80021e0 /* Enable all events Notification */ config_param.PayloadCmdSize = SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE; 80025f6: 230f movs r3, #15 80025f8: 723b strb r3, [r7, #8] config_param.EvtMask1 = SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE 80025fa: 237f movs r3, #127 @ 0x7f 80025fc: 72bb strb r3, [r7, #10] * @brief Return the device revision identifier * @note This field indicates the revision of the device. * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF */ RevisionID = LL_DBGMCU_GetRevisionID(); 80025fe: f7ff fe75 bl 80022ec 8002602: 6278 str r0, [r7, #36] @ 0x24 APP_DBG_MSG(">>== DBGMCU_GetRevisionID= %lx \n\r", RevisionID); config_param.RevisionID = (uint16_t)RevisionID; 8002604: 6a7b ldr r3, [r7, #36] @ 0x24 8002606: b29b uxth r3, r3 8002608: 82bb strh r3, [r7, #20] DeviceID = LL_DBGMCU_GetDeviceID(); 800260a: f7ff fe61 bl 80022d0 800260e: 6238 str r0, [r7, #32] APP_DBG_MSG(">>== DBGMCU_GetDeviceID= %lx \n\r", DeviceID); config_param.DeviceID = (uint16_t)DeviceID; 8002610: 6a3b ldr r3, [r7, #32] 8002612: b29b uxth r3, r3 8002614: 82fb strh r3, [r7, #22] (void)SHCI_C2_Config(&config_param); 8002616: f107 0308 add.w r3, r7, #8 800261a: 4618 mov r0, r3 800261c: f010 fbfc bl 8012e18 APP_BLE_Init(); 8002620: f7ff ff60 bl 80024e4 UTIL_LPM_SetOffMode(1U << CFG_LPM_APP, UTIL_LPM_ENABLE); 8002624: 2100 movs r1, #0 8002626: 2001 movs r0, #1 8002628: f016 fe88 bl 801933c else { APP_DBG_MSG(">>== SHCI_SUB_EVT_CODE_READY - UNEXPECTED CASE \n\r"); } return; 800262c: e007 b.n 800263e else if (p_sys_ready_event->sysevt_ready_rsp == FUS_FW_RUNNING) 800262e: 69bb ldr r3, [r7, #24] 8002630: 781b ldrb r3, [r3, #0] 8002632: 2b01 cmp r3, #1 8002634: d103 bne.n 800263e ((tSHCI_UserEvtRxParam*)pPayload)->status = SHCI_TL_UserEventFlow_Disable; 8002636: 687b ldr r3, [r7, #4] 8002638: 2200 movs r2, #0 800263a: 701a strb r2, [r3, #0] return; 800263c: bf00 nop 800263e: bf00 nop } 8002640: 3728 adds r7, #40 @ 0x28 8002642: 46bd mov sp, r7 8002644: bd80 pop {r7, pc} 08002646 : * * FREERTOS WRAPPER FUNCTIONS * *************************************************************/ static void ShciUserEvtProcess(void *argument) { 8002646: b580 push {r7, lr} 8002648: b082 sub sp, #8 800264a: af00 add r7, sp, #0 800264c: 6078 str r0, [r7, #4] for(;;) { /* USER CODE BEGIN SHCI_USER_EVT_PROCESS_1 */ /* USER CODE END SHCI_USER_EVT_PROCESS_1 */ osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever); 800264e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8002652: 2100 movs r1, #0 8002654: 2001 movs r0, #1 8002656: f011 fa73 bl 8013b40 shci_user_evt_proc(); 800265a: f010 fcbd bl 8012fd8 osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever); 800265e: bf00 nop 8002660: e7f5 b.n 800264e ... 08002664 : __WFI(); } } void shci_notify_asynch_evt(void* pdata) { 8002664: b580 push {r7, lr} 8002666: b082 sub sp, #8 8002668: af00 add r7, sp, #0 800266a: 6078 str r0, [r7, #4] UNUSED(pdata); osThreadFlagsSet(ShciUserEvtProcessId, 1); 800266c: 4b04 ldr r3, [pc, #16] @ (8002680 ) 800266e: 681b ldr r3, [r3, #0] 8002670: 2101 movs r1, #1 8002672: 4618 mov r0, r3 8002674: f011 fa0e bl 8013a94 return; 8002678: bf00 nop } 800267a: 3708 adds r7, #8 800267c: 46bd mov sp, r7 800267e: bd80 pop {r7, pc} 8002680: 20000310 .word 0x20000310 08002684 : void shci_cmd_resp_release(uint32_t flag) { 8002684: b580 push {r7, lr} 8002686: b082 sub sp, #8 8002688: af00 add r7, sp, #0 800268a: 6078 str r0, [r7, #4] UNUSED(flag); osSemaphoreRelease(SemShciId); 800268c: 4b04 ldr r3, [pc, #16] @ (80026a0 ) 800268e: 681b ldr r3, [r3, #0] 8002690: 4618 mov r0, r3 8002692: f011 fcbb bl 801400c return; 8002696: bf00 nop } 8002698: 3708 adds r7, #8 800269a: 46bd mov sp, r7 800269c: bd80 pop {r7, pc} 800269e: bf00 nop 80026a0: 2000030c .word 0x2000030c 080026a4 : void shci_cmd_resp_wait(uint32_t timeout) { 80026a4: b580 push {r7, lr} 80026a6: b082 sub sp, #8 80026a8: af00 add r7, sp, #0 80026aa: 6078 str r0, [r7, #4] UNUSED(timeout); osSemaphoreAcquire(SemShciId, osWaitForever); 80026ac: 4b05 ldr r3, [pc, #20] @ (80026c4 ) 80026ae: 681b ldr r3, [r3, #0] 80026b0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80026b4: 4618 mov r0, r3 80026b6: f011 fc59 bl 8013f6c return; 80026ba: bf00 nop } 80026bc: 3708 adds r7, #8 80026be: 46bd mov sp, r7 80026c0: bd80 pop {r7, pc} 80026c2: bf00 nop 80026c4: 2000030c .word 0x2000030c 080026c8 : /* Hook prototypes */ void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) { 80026c8: b480 push {r7} 80026ca: b083 sub sp, #12 80026cc: af00 add r7, sp, #0 80026ce: 6078 str r0, [r7, #4] 80026d0: 6039 str r1, [r7, #0] \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80026d2: b672 cpsid i } 80026d4: bf00 nop /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ __disable_irq(); for (;;) { } // breakpoint here 80026d6: bf00 nop 80026d8: e7fd b.n 80026d6 080026da : /*! * @brief This API is the entry point. Call this API before using other APIs. */ int8_t bmm350_init(struct bmm350_dev *dev) { 80026da: b580 push {r7, lr} 80026dc: b084 sub sp, #16 80026de: af00 add r7, sp, #0 80026e0: 6078 str r0, [r7, #4] /* Variable to store the function result */ int8_t rslt; /* Variable to get chip id */ uint8_t chip_id = BMM350_DISABLE; 80026e2: 2300 movs r3, #0 80026e4: 73bb strb r3, [r7, #14] /* Variable to store the command to power-off the OTP */ uint8_t otp_cmd = BMM350_OTP_CMD_PWR_OFF_OTP; 80026e6: 2380 movs r3, #128 @ 0x80 80026e8: 737b strb r3, [r7, #13] /* Variable to store soft-reset command */ uint8_t soft_reset; /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 80026ea: 6878 ldr r0, [r7, #4] 80026ec: f000 fd8a bl 8003204 80026f0: 4603 mov r3, r0 80026f2: 73fb strb r3, [r7, #15] /* Proceed if null check is fine */ if (rslt == BMM350_OK) 80026f4: f997 300f ldrsb.w r3, [r7, #15] 80026f8: 2b00 cmp r3, #0 80026fa: d173 bne.n 80027e4 { dev->chip_id = 0; 80026fc: 687b ldr r3, [r7, #4] 80026fe: 2200 movs r2, #0 8002700: 711a strb r2, [r3, #4] /* Assign axis_en with all axis enabled (BMM350_EN_XYZ_MSK) */ dev->axis_en = BMM350_EN_XYZ_MSK; 8002702: 687b ldr r3, [r7, #4] 8002704: 2207 movs r2, #7 8002706: 755a strb r2, [r3, #21] rslt = bmm350_delay_us(BMM350_START_UP_TIME_FROM_POR, dev); 8002708: 6879 ldr r1, [r7, #4] 800270a: f640 30b8 movw r0, #3000 @ 0xbb8 800270e: f000 f8f8 bl 8002902 8002712: 4603 mov r3, r0 8002714: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002716: f997 300f ldrsb.w r3, [r7, #15] 800271a: 2b00 cmp r3, #0 800271c: d115 bne.n 800274a { /* Soft-reset */ soft_reset = BMM350_CMD_SOFTRESET; 800271e: 23b6 movs r3, #182 @ 0xb6 8002720: 733b strb r3, [r7, #12] /* Set the command in the command register */ rslt = bmm350_set_regs(BMM350_REG_CMD, &soft_reset, 1, dev); 8002722: f107 010c add.w r1, r7, #12 8002726: 687b ldr r3, [r7, #4] 8002728: 2201 movs r2, #1 800272a: 207e movs r0, #126 @ 0x7e 800272c: f000 f860 bl 80027f0 8002730: 4603 mov r3, r0 8002732: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002734: f997 300f ldrsb.w r3, [r7, #15] 8002738: 2b00 cmp r3, #0 800273a: d106 bne.n 800274a { rslt = bmm350_delay_us(BMM350_SOFT_RESET_DELAY, dev); 800273c: 6879 ldr r1, [r7, #4] 800273e: f645 50c0 movw r0, #24000 @ 0x5dc0 8002742: f000 f8de bl 8002902 8002746: 4603 mov r3, r0 8002748: 73fb strb r3, [r7, #15] } } if (rslt == BMM350_OK) 800274a: f997 300f ldrsb.w r3, [r7, #15] 800274e: 2b00 cmp r3, #0 8002750: d10f bne.n 8002772 { /* Chip ID of the sensor is read */ rslt = bmm350_get_regs(BMM350_REG_CHIP_ID, &chip_id, 1, dev); 8002752: f107 010e add.w r1, r7, #14 8002756: 687b ldr r3, [r7, #4] 8002758: 2201 movs r2, #1 800275a: 2000 movs r0, #0 800275c: f000 f87c bl 8002858 8002760: 4603 mov r3, r0 8002762: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002764: f997 300f ldrsb.w r3, [r7, #15] 8002768: 2b00 cmp r3, #0 800276a: d102 bne.n 8002772 { /* Assign chip_id to dev->chip_id */ dev->chip_id = chip_id; 800276c: 7bba ldrb r2, [r7, #14] 800276e: 687b ldr r3, [r7, #4] 8002770: 711a strb r2, [r3, #4] } } /* Check for chip id validity */ if ((rslt == BMM350_OK) && (dev->chip_id == BMM350_CHIP_ID)) 8002772: f997 300f ldrsb.w r3, [r7, #15] 8002776: 2b00 cmp r3, #0 8002778: d130 bne.n 80027dc 800277a: 687b ldr r3, [r7, #4] 800277c: 791b ldrb r3, [r3, #4] 800277e: 2b33 cmp r3, #51 @ 0x33 8002780: d12c bne.n 80027dc { /* Download OTP memory */ rslt = otp_dump_after_boot(dev); 8002782: 6878 ldr r0, [r7, #4] 8002784: f001 f910 bl 80039a8 8002788: 4603 mov r3, r0 800278a: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 800278c: f997 300f ldrsb.w r3, [r7, #15] 8002790: 2b00 cmp r3, #0 8002792: d126 bne.n 80027e2 { /* Power off OTP */ rslt = bmm350_set_regs(BMM350_REG_OTP_CMD_REG, &otp_cmd, 1, dev); 8002794: f107 010d add.w r1, r7, #13 8002798: 687b ldr r3, [r7, #4] 800279a: 2201 movs r2, #1 800279c: 2050 movs r0, #80 @ 0x50 800279e: f000 f827 bl 80027f0 80027a2: 4603 mov r3, r0 80027a4: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80027a6: f997 300f ldrsb.w r3, [r7, #15] 80027aa: 2b00 cmp r3, #0 80027ac: d119 bne.n 80027e2 { if (dev->boot_done_status != BMM350_BOOT_NOT_DONE) 80027ae: 687b ldr r3, [r7, #4] 80027b0: f893 30ac ldrb.w r3, [r3, #172] @ 0xac 80027b4: 2b00 cmp r3, #0 80027b6: d003 beq.n 80027c0 { dev->boot_done_status = BMM350_BOOT_NOT_DONE; 80027b8: 687b ldr r3, [r7, #4] 80027ba: 2200 movs r2, #0 80027bc: f883 20ac strb.w r2, [r3, #172] @ 0xac } rslt = bmm350_magnetic_reset_and_wait(dev); 80027c0: 6878 ldr r0, [r7, #4] 80027c2: f000 fa98 bl 8002cf6 80027c6: 4603 mov r3, r0 80027c8: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80027ca: f997 300f ldrsb.w r3, [r7, #15] 80027ce: 2b00 cmp r3, #0 80027d0: d107 bne.n 80027e2 { dev->boot_done_status = BMM350_BOOT_DONE; 80027d2: 687b ldr r3, [r7, #4] 80027d4: 2201 movs r2, #1 80027d6: f883 20ac strb.w r2, [r3, #172] @ 0xac if (rslt == BMM350_OK) 80027da: e002 b.n 80027e2 } } } else { rslt = BMM350_E_DEV_NOT_FOUND; 80027dc: 23fd movs r3, #253 @ 0xfd 80027de: 73fb strb r3, [r7, #15] 80027e0: e000 b.n 80027e4 if (rslt == BMM350_OK) 80027e2: bf00 nop } } return rslt; 80027e4: f997 300f ldrsb.w r3, [r7, #15] } 80027e8: 4618 mov r0, r3 80027ea: 3710 adds r7, #16 80027ec: 46bd mov sp, r7 80027ee: bd80 pop {r7, pc} 080027f0 : /*! * @brief This API writes the given data to the register address * of the sensor. */ int8_t bmm350_set_regs(uint8_t reg_addr, const uint8_t *reg_data, uint16_t len, struct bmm350_dev *dev) { 80027f0: b590 push {r4, r7, lr} 80027f2: b087 sub sp, #28 80027f4: af00 add r7, sp, #0 80027f6: 60b9 str r1, [r7, #8] 80027f8: 607b str r3, [r7, #4] 80027fa: 4603 mov r3, r0 80027fc: 73fb strb r3, [r7, #15] 80027fe: 4613 mov r3, r2 8002800: 81bb strh r3, [r7, #12] /* Variable to store the function result */ int8_t rslt; /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 8002802: 6878 ldr r0, [r7, #4] 8002804: f000 fcfe bl 8003204 8002808: 4603 mov r3, r0 800280a: 75fb strb r3, [r7, #23] /* Proceed if null check is fine */ if ((rslt == BMM350_OK) && (reg_data != NULL) && (len != 0)) 800280c: f997 3017 ldrsb.w r3, [r7, #23] 8002810: 2b00 cmp r3, #0 8002812: d119 bne.n 8002848 8002814: 68bb ldr r3, [r7, #8] 8002816: 2b00 cmp r3, #0 8002818: d016 beq.n 8002848 800281a: 89bb ldrh r3, [r7, #12] 800281c: 2b00 cmp r3, #0 800281e: d013 beq.n 8002848 { /* Write the data to the reg_addr */ dev->intf_rslt = dev->write(reg_addr, reg_data, len, dev->intf_ptr); 8002820: 687b ldr r3, [r7, #4] 8002822: 68dc ldr r4, [r3, #12] 8002824: 89ba ldrh r2, [r7, #12] 8002826: 687b ldr r3, [r7, #4] 8002828: 681b ldr r3, [r3, #0] 800282a: 7bf8 ldrb r0, [r7, #15] 800282c: 68b9 ldr r1, [r7, #8] 800282e: 47a0 blx r4 8002830: 4603 mov r3, r0 8002832: 461a mov r2, r3 8002834: 687b ldr r3, [r7, #4] 8002836: 751a strb r2, [r3, #20] if (dev->intf_rslt != BMM350_INTF_RET_SUCCESS) 8002838: 687b ldr r3, [r7, #4] 800283a: f993 3014 ldrsb.w r3, [r3, #20] 800283e: 2b00 cmp r3, #0 8002840: d004 beq.n 800284c { rslt = BMM350_E_COM_FAIL; 8002842: 23fe movs r3, #254 @ 0xfe 8002844: 75fb strb r3, [r7, #23] if (dev->intf_rslt != BMM350_INTF_RET_SUCCESS) 8002846: e001 b.n 800284c } } else { rslt = BMM350_E_NULL_PTR; 8002848: 23ff movs r3, #255 @ 0xff 800284a: 75fb strb r3, [r7, #23] } return rslt; 800284c: f997 3017 ldrsb.w r3, [r7, #23] } 8002850: 4618 mov r0, r3 8002852: 371c adds r7, #28 8002854: 46bd mov sp, r7 8002856: bd90 pop {r4, r7, pc} 08002858 : /*! * @brief This API reads the data from the given register address of sensor. */ int8_t bmm350_get_regs(uint8_t reg_addr, uint8_t *reg_data, uint16_t len, struct bmm350_dev *dev) { 8002858: b590 push {r4, r7, lr} 800285a: b0a7 sub sp, #156 @ 0x9c 800285c: af00 add r7, sp, #0 800285e: 60b9 str r1, [r7, #8] 8002860: 607b str r3, [r7, #4] 8002862: 4603 mov r3, r0 8002864: 73fb strb r3, [r7, #15] 8002866: 4613 mov r3, r2 8002868: 81bb strh r3, [r7, #12] /* Variable to store the function result */ int8_t rslt; /* Variable to define temporary length */ uint16_t temp_len = len + BMM350_DUMMY_BYTES; 800286a: 89bb ldrh r3, [r7, #12] 800286c: 3302 adds r3, #2 800286e: f8a7 3092 strh.w r3, [r7, #146] @ 0x92 /* Variable to define temporary buffer */ uint8_t temp_buf[BMM350_READ_BUFFER_LENGTH]; /* Variable to define loop */ uint16_t index = 0; 8002872: 2300 movs r3, #0 8002874: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 8002878: 6878 ldr r0, [r7, #4] 800287a: f000 fcc3 bl 8003204 800287e: 4603 mov r3, r0 8002880: f887 3097 strb.w r3, [r7, #151] @ 0x97 /* Proceed if null check is fine */ if ((rslt == BMM350_OK) && (reg_data != NULL)) 8002884: f997 3097 ldrsb.w r3, [r7, #151] @ 0x97 8002888: 2b00 cmp r3, #0 800288a: d131 bne.n 80028f0 800288c: 68bb ldr r3, [r7, #8] 800288e: 2b00 cmp r3, #0 8002890: d02e beq.n 80028f0 { /* Read the data from the reg_addr */ dev->intf_rslt = dev->read(reg_addr, temp_buf, temp_len, dev->intf_ptr); 8002892: 687b ldr r3, [r7, #4] 8002894: 689c ldr r4, [r3, #8] 8002896: f8b7 2092 ldrh.w r2, [r7, #146] @ 0x92 800289a: 687b ldr r3, [r7, #4] 800289c: 681b ldr r3, [r3, #0] 800289e: f107 0110 add.w r1, r7, #16 80028a2: 7bf8 ldrb r0, [r7, #15] 80028a4: 47a0 blx r4 80028a6: 4603 mov r3, r0 80028a8: 461a mov r2, r3 80028aa: 687b ldr r3, [r7, #4] 80028ac: 751a strb r2, [r3, #20] if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS) 80028ae: 687b ldr r3, [r7, #4] 80028b0: f993 3014 ldrsb.w r3, [r3, #20] 80028b4: 2b00 cmp r3, #0 80028b6: d117 bne.n 80028e8 { /* Copy data after dummy byte indices */ while (index < len) 80028b8: e010 b.n 80028dc { reg_data[index] = temp_buf[index + BMM350_DUMMY_BYTES]; 80028ba: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 80028be: 1c9a adds r2, r3, #2 80028c0: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 80028c4: 68b9 ldr r1, [r7, #8] 80028c6: 440b add r3, r1 80028c8: 3298 adds r2, #152 @ 0x98 80028ca: 443a add r2, r7 80028cc: f812 2c88 ldrb.w r2, [r2, #-136] 80028d0: 701a strb r2, [r3, #0] index++; 80028d2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 80028d6: 3301 adds r3, #1 80028d8: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 while (index < len) 80028dc: f8b7 2094 ldrh.w r2, [r7, #148] @ 0x94 80028e0: 89bb ldrh r3, [r7, #12] 80028e2: 429a cmp r2, r3 80028e4: d3e9 bcc.n 80028ba if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS) 80028e6: e006 b.n 80028f6 } } else { rslt = BMM350_E_COM_FAIL; 80028e8: 23fe movs r3, #254 @ 0xfe 80028ea: f887 3097 strb.w r3, [r7, #151] @ 0x97 if (dev->intf_rslt == BMM350_INTF_RET_SUCCESS) 80028ee: e002 b.n 80028f6 } } else { rslt = BMM350_E_NULL_PTR; 80028f0: 23ff movs r3, #255 @ 0xff 80028f2: f887 3097 strb.w r3, [r7, #151] @ 0x97 } return rslt; 80028f6: f997 3097 ldrsb.w r3, [r7, #151] @ 0x97 } 80028fa: 4618 mov r0, r3 80028fc: 379c adds r7, #156 @ 0x9c 80028fe: 46bd mov sp, r7 8002900: bd90 pop {r4, r7, pc} 08002902 : /*! * @brief This function provides the delay for required time (Microsecond) as per the input provided in some of the * APIs. */ int8_t bmm350_delay_us(uint32_t period_us, const struct bmm350_dev *dev) { 8002902: b580 push {r7, lr} 8002904: b084 sub sp, #16 8002906: af00 add r7, sp, #0 8002908: 6078 str r0, [r7, #4] 800290a: 6039 str r1, [r7, #0] /* Variable to store the function result */ int8_t rslt; /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 800290c: 6838 ldr r0, [r7, #0] 800290e: f000 fc79 bl 8003204 8002912: 4603 mov r3, r0 8002914: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002916: f997 300f ldrsb.w r3, [r7, #15] 800291a: 2b00 cmp r3, #0 800291c: d106 bne.n 800292c { dev->delay_us(period_us, dev->intf_ptr); 800291e: 683b ldr r3, [r7, #0] 8002920: 691b ldr r3, [r3, #16] 8002922: 683a ldr r2, [r7, #0] 8002924: 6812 ldr r2, [r2, #0] 8002926: 4611 mov r1, r2 8002928: 6878 ldr r0, [r7, #4] 800292a: 4798 blx r3 } return rslt; 800292c: f997 300f ldrsb.w r3, [r7, #15] } 8002930: 4618 mov r0, r3 8002932: 3710 adds r7, #16 8002934: 46bd mov sp, r7 8002936: bd80 pop {r7, pc} 08002938 : /*! * @brief This API is used to set the power mode of the sensor */ int8_t bmm350_set_powermode(enum bmm350_power_modes powermode, struct bmm350_dev *dev) { 8002938: b580 push {r7, lr} 800293a: b084 sub sp, #16 800293c: af00 add r7, sp, #0 800293e: 4603 mov r3, r0 8002940: 6039 str r1, [r7, #0] 8002942: 71fb strb r3, [r7, #7] uint8_t last_pwr_mode; uint8_t reg_data; /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 8002944: 6838 ldr r0, [r7, #0] 8002946: f000 fc5d bl 8003204 800294a: 4603 mov r3, r0 800294c: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 800294e: f997 300f ldrsb.w r3, [r7, #15] 8002952: 2b00 cmp r3, #0 8002954: d13c bne.n 80029d0 { rslt = bmm350_get_regs(BMM350_REG_PMU_CMD, &last_pwr_mode, 1, dev); 8002956: f107 010e add.w r1, r7, #14 800295a: 683b ldr r3, [r7, #0] 800295c: 2201 movs r2, #1 800295e: 2006 movs r0, #6 8002960: f7ff ff7a bl 8002858 8002964: 4603 mov r3, r0 8002966: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002968: f997 300f ldrsb.w r3, [r7, #15] 800296c: 2b00 cmp r3, #0 800296e: d12f bne.n 80029d0 { if (last_pwr_mode > BMM350_PMU_CMD_BR_FAST) 8002970: 7bbb ldrb r3, [r7, #14] 8002972: 2b08 cmp r3, #8 8002974: d901 bls.n 800297a { rslt = BMM350_E_INVALID_CONFIG; 8002976: 23fc movs r3, #252 @ 0xfc 8002978: 73fb strb r3, [r7, #15] } if ((rslt == BMM350_OK) && 800297a: f997 300f ldrsb.w r3, [r7, #15] 800297e: 2b00 cmp r3, #0 8002980: d11b bne.n 80029ba ((last_pwr_mode == BMM350_PMU_CMD_NM) || (last_pwr_mode == BMM350_PMU_CMD_UPD_OAE))) 8002982: 7bbb ldrb r3, [r7, #14] if ((rslt == BMM350_OK) && 8002984: 2b01 cmp r3, #1 8002986: d002 beq.n 800298e ((last_pwr_mode == BMM350_PMU_CMD_NM) || (last_pwr_mode == BMM350_PMU_CMD_UPD_OAE))) 8002988: 7bbb ldrb r3, [r7, #14] 800298a: 2b02 cmp r3, #2 800298c: d115 bne.n 80029ba { reg_data = BMM350_PMU_CMD_SUS; 800298e: 2300 movs r3, #0 8002990: 737b strb r3, [r7, #13] /* Set PMU command configuration */ rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev); 8002992: f107 010d add.w r1, r7, #13 8002996: 683b ldr r3, [r7, #0] 8002998: 2201 movs r2, #1 800299a: 2006 movs r0, #6 800299c: f7ff ff28 bl 80027f0 80029a0: 4603 mov r3, r0 80029a2: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80029a4: f997 300f ldrsb.w r3, [r7, #15] 80029a8: 2b00 cmp r3, #0 80029aa: d106 bne.n 80029ba { rslt = bmm350_delay_us(BMM350_GOTO_SUSPEND_DELAY, dev); 80029ac: 6839 ldr r1, [r7, #0] 80029ae: f241 7070 movw r0, #6000 @ 0x1770 80029b2: f7ff ffa6 bl 8002902 80029b6: 4603 mov r3, r0 80029b8: 73fb strb r3, [r7, #15] } } if (rslt == BMM350_OK) 80029ba: f997 300f ldrsb.w r3, [r7, #15] 80029be: 2b00 cmp r3, #0 80029c0: d106 bne.n 80029d0 { rslt = set_powermode(powermode, dev); 80029c2: 79fb ldrb r3, [r7, #7] 80029c4: 6839 ldr r1, [r7, #0] 80029c6: 4618 mov r0, r3 80029c8: f001 f82e bl 8003a28 80029cc: 4603 mov r3, r0 80029ce: 73fb strb r3, [r7, #15] } } } return rslt; 80029d0: f997 300f ldrsb.w r3, [r7, #15] } 80029d4: 4618 mov r0, r3 80029d6: 3710 adds r7, #16 80029d8: 46bd mov sp, r7 80029da: bd80 pop {r7, pc} 080029dc : * @brief This API sets the ODR and averaging factor. */ int8_t bmm350_set_odr_performance(enum bmm350_data_rates odr, enum bmm350_performance_parameters performance, struct bmm350_dev *dev) { 80029dc: b580 push {r7, lr} 80029de: b084 sub sp, #16 80029e0: af00 add r7, sp, #0 80029e2: 4603 mov r3, r0 80029e4: 603a str r2, [r7, #0] 80029e6: 71fb strb r3, [r7, #7] 80029e8: 460b mov r3, r1 80029ea: 71bb strb r3, [r7, #6] /* Variable to store the function result */ int8_t rslt; /* Variable to get PMU command */ uint8_t reg_data = 0; 80029ec: 2300 movs r3, #0 80029ee: 737b strb r3, [r7, #13] enum bmm350_performance_parameters performance_fix = performance; 80029f0: 79bb ldrb r3, [r7, #6] 80029f2: 73bb strb r3, [r7, #14] /* Check for null pointer in the device structure */ rslt = null_ptr_check(dev); 80029f4: 6838 ldr r0, [r7, #0] 80029f6: f000 fc05 bl 8003204 80029fa: 4603 mov r3, r0 80029fc: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 80029fe: f997 300f ldrsb.w r3, [r7, #15] 8002a02: 2b00 cmp r3, #0 8002a04: d151 bne.n 8002aaa { /* Reduce the performance setting when too high for the chosen ODR */ if ((odr == BMM350_DATA_RATE_400HZ) && (performance >= BMM350_AVERAGING_2)) 8002a06: 79fb ldrb r3, [r7, #7] 8002a08: 2b02 cmp r3, #2 8002a0a: d105 bne.n 8002a18 8002a0c: 79bb ldrb r3, [r7, #6] 8002a0e: 2b00 cmp r3, #0 8002a10: d002 beq.n 8002a18 { performance_fix = BMM350_NO_AVERAGING; 8002a12: 2300 movs r3, #0 8002a14: 73bb strb r3, [r7, #14] 8002a16: e010 b.n 8002a3a } else if ((odr == BMM350_DATA_RATE_200HZ) && (performance >= BMM350_AVERAGING_4)) 8002a18: 79fb ldrb r3, [r7, #7] 8002a1a: 2b03 cmp r3, #3 8002a1c: d105 bne.n 8002a2a 8002a1e: 79bb ldrb r3, [r7, #6] 8002a20: 2b01 cmp r3, #1 8002a22: d902 bls.n 8002a2a { performance_fix = BMM350_AVERAGING_2; 8002a24: 2301 movs r3, #1 8002a26: 73bb strb r3, [r7, #14] 8002a28: e007 b.n 8002a3a } else if ((odr == BMM350_DATA_RATE_100HZ) && (performance >= BMM350_AVERAGING_8)) 8002a2a: 79fb ldrb r3, [r7, #7] 8002a2c: 2b04 cmp r3, #4 8002a2e: d104 bne.n 8002a3a 8002a30: 79bb ldrb r3, [r7, #6] 8002a32: 2b02 cmp r3, #2 8002a34: d901 bls.n 8002a3a { performance_fix = BMM350_AVERAGING_4; 8002a36: 2302 movs r3, #2 8002a38: 73bb strb r3, [r7, #14] } /* ODR is an enum taking the generated constants from the register map */ reg_data = ((uint8_t)odr & BMM350_ODR_MSK); 8002a3a: 79fb ldrb r3, [r7, #7] 8002a3c: f003 030f and.w r3, r3, #15 8002a40: b2db uxtb r3, r3 8002a42: 737b strb r3, [r7, #13] /* AVG / performance is an enum taking the generated constants from the register map */ reg_data = BMM350_SET_BITS(reg_data, BMM350_AVG, (uint8_t)performance_fix); 8002a44: 7b7b ldrb r3, [r7, #13] 8002a46: b25b sxtb r3, r3 8002a48: f023 0330 bic.w r3, r3, #48 @ 0x30 8002a4c: b25a sxtb r2, r3 8002a4e: f997 300e ldrsb.w r3, [r7, #14] 8002a52: 011b lsls r3, r3, #4 8002a54: b25b sxtb r3, r3 8002a56: f003 0330 and.w r3, r3, #48 @ 0x30 8002a5a: b25b sxtb r3, r3 8002a5c: 4313 orrs r3, r2 8002a5e: b25b sxtb r3, r3 8002a60: b2db uxtb r3, r3 8002a62: 737b strb r3, [r7, #13] /* Set PMU command configurations for ODR and performance */ rslt = bmm350_set_regs(BMM350_REG_PMU_CMD_AGGR_SET, ®_data, 1, dev); 8002a64: f107 010d add.w r1, r7, #13 8002a68: 683b ldr r3, [r7, #0] 8002a6a: 2201 movs r2, #1 8002a6c: 2004 movs r0, #4 8002a6e: f7ff febf bl 80027f0 8002a72: 4603 mov r3, r0 8002a74: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002a76: f997 300f ldrsb.w r3, [r7, #15] 8002a7a: 2b00 cmp r3, #0 8002a7c: d115 bne.n 8002aaa { /* Set PMU command configurations to update odr and average */ reg_data = BMM350_PMU_CMD_UPD_OAE; 8002a7e: 2302 movs r3, #2 8002a80: 737b strb r3, [r7, #13] /* Set PMU command configuration */ rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev); 8002a82: f107 010d add.w r1, r7, #13 8002a86: 683b ldr r3, [r7, #0] 8002a88: 2201 movs r2, #1 8002a8a: 2006 movs r0, #6 8002a8c: f7ff feb0 bl 80027f0 8002a90: 4603 mov r3, r0 8002a92: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002a94: f997 300f ldrsb.w r3, [r7, #15] 8002a98: 2b00 cmp r3, #0 8002a9a: d106 bne.n 8002aaa { rslt = bmm350_delay_us(BMM350_UPD_OAE_DELAY, dev); 8002a9c: 6839 ldr r1, [r7, #0] 8002a9e: f44f 707a mov.w r0, #1000 @ 0x3e8 8002aa2: f7ff ff2e bl 8002902 8002aa6: 4603 mov r3, r0 8002aa8: 73fb strb r3, [r7, #15] } } } return rslt; 8002aaa: f997 300f ldrsb.w r3, [r7, #15] } 8002aae: 4618 mov r0, r3 8002ab0: 3710 adds r7, #16 8002ab2: 46bd mov sp, r7 8002ab4: bd80 pop {r7, pc} 08002ab6 : /*! * @brief This API is used to enable or disable the data ready interrupt */ int8_t bmm350_enable_interrupt(enum bmm350_interrupt_enable_disable enable_disable, struct bmm350_dev *dev) { 8002ab6: b580 push {r7, lr} 8002ab8: b084 sub sp, #16 8002aba: af00 add r7, sp, #0 8002abc: 4603 mov r3, r0 8002abe: 6039 str r1, [r7, #0] 8002ac0: 71fb strb r3, [r7, #7] /* Variable to get interrupt control configuration */ uint8_t reg_data = 0; 8002ac2: 2300 movs r3, #0 8002ac4: 73bb strb r3, [r7, #14] /* Variable to store the function result */ int8_t rslt; /* Get interrupt control configuration */ rslt = bmm350_get_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev); 8002ac6: f107 010e add.w r1, r7, #14 8002aca: 683b ldr r3, [r7, #0] 8002acc: 2201 movs r2, #1 8002ace: 202e movs r0, #46 @ 0x2e 8002ad0: f7ff fec2 bl 8002858 8002ad4: 4603 mov r3, r0 8002ad6: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002ad8: f997 300f ldrsb.w r3, [r7, #15] 8002adc: 2b00 cmp r3, #0 8002ade: d115 bne.n 8002b0c { reg_data = BMM350_SET_BITS(reg_data, BMM350_DRDY_DATA_REG_EN, (uint8_t)enable_disable); 8002ae0: 7bbb ldrb r3, [r7, #14] 8002ae2: b25b sxtb r3, r3 8002ae4: f003 037f and.w r3, r3, #127 @ 0x7f 8002ae8: b25a sxtb r2, r3 8002aea: f997 3007 ldrsb.w r3, [r7, #7] 8002aee: 01db lsls r3, r3, #7 8002af0: b25b sxtb r3, r3 8002af2: 4313 orrs r3, r2 8002af4: b25b sxtb r3, r3 8002af6: b2db uxtb r3, r3 8002af8: 73bb strb r3, [r7, #14] /* Finally transfer the interrupt configurations */ rslt = bmm350_set_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev); 8002afa: f107 010e add.w r1, r7, #14 8002afe: 683b ldr r3, [r7, #0] 8002b00: 2201 movs r2, #1 8002b02: 202e movs r0, #46 @ 0x2e 8002b04: f7ff fe74 bl 80027f0 8002b08: 4603 mov r3, r0 8002b0a: 73fb strb r3, [r7, #15] } return rslt; 8002b0c: f997 300f ldrsb.w r3, [r7, #15] } 8002b10: 4618 mov r0, r3 8002b12: 3710 adds r7, #16 8002b14: 46bd mov sp, r7 8002b16: bd80 pop {r7, pc} 08002b18 : int8_t bmm350_configure_interrupt(enum bmm350_intr_latch latching, enum bmm350_intr_polarity polarity, enum bmm350_intr_drive drivertype, enum bmm350_intr_map map_nomap, struct bmm350_dev *dev) { 8002b18: b590 push {r4, r7, lr} 8002b1a: b085 sub sp, #20 8002b1c: af00 add r7, sp, #0 8002b1e: 4604 mov r4, r0 8002b20: 4608 mov r0, r1 8002b22: 4611 mov r1, r2 8002b24: 461a mov r2, r3 8002b26: 4623 mov r3, r4 8002b28: 71fb strb r3, [r7, #7] 8002b2a: 4603 mov r3, r0 8002b2c: 71bb strb r3, [r7, #6] 8002b2e: 460b mov r3, r1 8002b30: 717b strb r3, [r7, #5] 8002b32: 4613 mov r3, r2 8002b34: 713b strb r3, [r7, #4] /* Variable to get interrupt control configuration */ uint8_t reg_data = 0; 8002b36: 2300 movs r3, #0 8002b38: 73bb strb r3, [r7, #14] /* Variable to store the function result */ int8_t rslt; /* Get interrupt control configuration */ rslt = bmm350_get_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev); 8002b3a: f107 010e add.w r1, r7, #14 8002b3e: 6a3b ldr r3, [r7, #32] 8002b40: 2201 movs r2, #1 8002b42: 202e movs r0, #46 @ 0x2e 8002b44: f7ff fe88 bl 8002858 8002b48: 4603 mov r3, r0 8002b4a: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8002b4c: f997 300f ldrsb.w r3, [r7, #15] 8002b50: 2b00 cmp r3, #0 8002b52: d146 bne.n 8002be2 { reg_data = BMM350_SET_BITS_POS_0(reg_data, BMM350_INT_MODE, latching); 8002b54: 7bbb ldrb r3, [r7, #14] 8002b56: b25b sxtb r3, r3 8002b58: f023 0301 bic.w r3, r3, #1 8002b5c: b25a sxtb r2, r3 8002b5e: f997 3007 ldrsb.w r3, [r7, #7] 8002b62: f003 0301 and.w r3, r3, #1 8002b66: b25b sxtb r3, r3 8002b68: 4313 orrs r3, r2 8002b6a: b25b sxtb r3, r3 8002b6c: b2db uxtb r3, r3 8002b6e: 73bb strb r3, [r7, #14] reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_POL, polarity); 8002b70: 7bbb ldrb r3, [r7, #14] 8002b72: b25b sxtb r3, r3 8002b74: f023 0302 bic.w r3, r3, #2 8002b78: b25a sxtb r2, r3 8002b7a: f997 3006 ldrsb.w r3, [r7, #6] 8002b7e: 005b lsls r3, r3, #1 8002b80: b25b sxtb r3, r3 8002b82: f003 0302 and.w r3, r3, #2 8002b86: b25b sxtb r3, r3 8002b88: 4313 orrs r3, r2 8002b8a: b25b sxtb r3, r3 8002b8c: b2db uxtb r3, r3 8002b8e: 73bb strb r3, [r7, #14] reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_OD, drivertype); 8002b90: 7bbb ldrb r3, [r7, #14] 8002b92: b25b sxtb r3, r3 8002b94: f023 0304 bic.w r3, r3, #4 8002b98: b25a sxtb r2, r3 8002b9a: f997 3005 ldrsb.w r3, [r7, #5] 8002b9e: 009b lsls r3, r3, #2 8002ba0: b25b sxtb r3, r3 8002ba2: f003 0304 and.w r3, r3, #4 8002ba6: b25b sxtb r3, r3 8002ba8: 4313 orrs r3, r2 8002baa: b25b sxtb r3, r3 8002bac: b2db uxtb r3, r3 8002bae: 73bb strb r3, [r7, #14] reg_data = BMM350_SET_BITS(reg_data, BMM350_INT_OUTPUT_EN, map_nomap); 8002bb0: 7bbb ldrb r3, [r7, #14] 8002bb2: b25b sxtb r3, r3 8002bb4: f023 0308 bic.w r3, r3, #8 8002bb8: b25a sxtb r2, r3 8002bba: f997 3004 ldrsb.w r3, [r7, #4] 8002bbe: 00db lsls r3, r3, #3 8002bc0: b25b sxtb r3, r3 8002bc2: f003 0308 and.w r3, r3, #8 8002bc6: b25b sxtb r3, r3 8002bc8: 4313 orrs r3, r2 8002bca: b25b sxtb r3, r3 8002bcc: b2db uxtb r3, r3 8002bce: 73bb strb r3, [r7, #14] /* Finally transfer the interrupt configurations */ rslt = bmm350_set_regs(BMM350_REG_INT_CTRL, ®_data, 1, dev); 8002bd0: f107 010e add.w r1, r7, #14 8002bd4: 6a3b ldr r3, [r7, #32] 8002bd6: 2201 movs r2, #1 8002bd8: 202e movs r0, #46 @ 0x2e 8002bda: f7ff fe09 bl 80027f0 8002bde: 4603 mov r3, r0 8002be0: 73fb strb r3, [r7, #15] } return rslt; 8002be2: f997 300f ldrsb.w r3, [r7, #15] } 8002be6: 4618 mov r0, r3 8002be8: 3714 adds r7, #20 8002bea: 46bd mov sp, r7 8002bec: bd90 pop {r4, r7, pc} 08002bee : /*! * @brief This API is used to read uncompensated mag and temperature data. */ int8_t bmm350_read_uncomp_mag_temp_data(struct bmm350_raw_mag_data *raw_data, struct bmm350_dev *dev) { 8002bee: b580 push {r7, lr} 8002bf0: b08a sub sp, #40 @ 0x28 8002bf2: af00 add r7, sp, #0 8002bf4: 6078 str r0, [r7, #4] 8002bf6: 6039 str r1, [r7, #0] /* Variable to store the function result */ int8_t rslt; uint8_t mag_data[12] = { 0 }; 8002bf8: f107 0308 add.w r3, r7, #8 8002bfc: 2200 movs r2, #0 8002bfe: 601a str r2, [r3, #0] 8002c00: 605a str r2, [r3, #4] 8002c02: 609a str r2, [r3, #8] uint32_t raw_mag_x, raw_mag_y, raw_mag_z, raw_temp; if (raw_data != NULL) 8002c04: 687b ldr r3, [r7, #4] 8002c06: 2b00 cmp r3, #0 8002c08: d06c beq.n 8002ce4 { /* Get uncompensated mag data */ rslt = bmm350_get_regs(BMM350_REG_MAG_X_XLSB, mag_data, BMM350_MAG_TEMP_DATA_LEN, dev); 8002c0a: f107 0108 add.w r1, r7, #8 8002c0e: 683b ldr r3, [r7, #0] 8002c10: 220c movs r2, #12 8002c12: 2031 movs r0, #49 @ 0x31 8002c14: f7ff fe20 bl 8002858 8002c18: 4603 mov r3, r0 8002c1a: f887 3027 strb.w r3, [r7, #39] @ 0x27 if (rslt == BMM350_OK) 8002c1e: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 8002c22: 2b00 cmp r3, #0 8002c24: d161 bne.n 8002cea { raw_mag_x = (uint32_t)mag_data[0] + ((uint32_t)mag_data[1] << 8) + ((uint32_t)mag_data[2] << 16); 8002c26: 7a3b ldrb r3, [r7, #8] 8002c28: 461a mov r2, r3 8002c2a: 7a7b ldrb r3, [r7, #9] 8002c2c: 021b lsls r3, r3, #8 8002c2e: 441a add r2, r3 8002c30: 7abb ldrb r3, [r7, #10] 8002c32: 041b lsls r3, r3, #16 8002c34: 4413 add r3, r2 8002c36: 623b str r3, [r7, #32] raw_mag_y = (uint32_t)mag_data[3] + ((uint32_t)mag_data[4] << 8) + ((uint32_t)mag_data[5] << 16); 8002c38: 7afb ldrb r3, [r7, #11] 8002c3a: 461a mov r2, r3 8002c3c: 7b3b ldrb r3, [r7, #12] 8002c3e: 021b lsls r3, r3, #8 8002c40: 441a add r2, r3 8002c42: 7b7b ldrb r3, [r7, #13] 8002c44: 041b lsls r3, r3, #16 8002c46: 4413 add r3, r2 8002c48: 61fb str r3, [r7, #28] raw_mag_z = (uint32_t)mag_data[6] + ((uint32_t)mag_data[7] << 8) + ((uint32_t)mag_data[8] << 16); 8002c4a: 7bbb ldrb r3, [r7, #14] 8002c4c: 461a mov r2, r3 8002c4e: 7bfb ldrb r3, [r7, #15] 8002c50: 021b lsls r3, r3, #8 8002c52: 441a add r2, r3 8002c54: 7c3b ldrb r3, [r7, #16] 8002c56: 041b lsls r3, r3, #16 8002c58: 4413 add r3, r2 8002c5a: 61bb str r3, [r7, #24] raw_temp = (uint32_t)mag_data[9] + ((uint32_t)mag_data[10] << 8) + ((uint32_t)mag_data[11] << 16); 8002c5c: 7c7b ldrb r3, [r7, #17] 8002c5e: 461a mov r2, r3 8002c60: 7cbb ldrb r3, [r7, #18] 8002c62: 021b lsls r3, r3, #8 8002c64: 441a add r2, r3 8002c66: 7cfb ldrb r3, [r7, #19] 8002c68: 041b lsls r3, r3, #16 8002c6a: 4413 add r3, r2 8002c6c: 617b str r3, [r7, #20] if ((dev->axis_en & BMM350_EN_X_MSK) == BMM350_DISABLE) 8002c6e: 683b ldr r3, [r7, #0] 8002c70: 7d5b ldrb r3, [r3, #21] 8002c72: f003 0301 and.w r3, r3, #1 8002c76: 2b00 cmp r3, #0 8002c78: d103 bne.n 8002c82 { raw_data->raw_xdata = BMM350_DISABLE; 8002c7a: 687b ldr r3, [r7, #4] 8002c7c: 2200 movs r2, #0 8002c7e: 601a str r2, [r3, #0] 8002c80: e006 b.n 8002c90 } else { raw_data->raw_xdata = fix_sign(raw_mag_x, BMM350_SIGNED_24_BIT); 8002c82: 2118 movs r1, #24 8002c84: 6a38 ldr r0, [r7, #32] 8002c86: f000 fadd bl 8003244 8002c8a: 4602 mov r2, r0 8002c8c: 687b ldr r3, [r7, #4] 8002c8e: 601a str r2, [r3, #0] } if ((dev->axis_en & BMM350_EN_Y_MSK) == BMM350_DISABLE) 8002c90: 683b ldr r3, [r7, #0] 8002c92: 7d5b ldrb r3, [r3, #21] 8002c94: f003 0302 and.w r3, r3, #2 8002c98: 2b00 cmp r3, #0 8002c9a: d103 bne.n 8002ca4 { raw_data->raw_ydata = BMM350_DISABLE; 8002c9c: 687b ldr r3, [r7, #4] 8002c9e: 2200 movs r2, #0 8002ca0: 605a str r2, [r3, #4] 8002ca2: e006 b.n 8002cb2 } else { raw_data->raw_ydata = fix_sign(raw_mag_y, BMM350_SIGNED_24_BIT); 8002ca4: 2118 movs r1, #24 8002ca6: 69f8 ldr r0, [r7, #28] 8002ca8: f000 facc bl 8003244 8002cac: 4602 mov r2, r0 8002cae: 687b ldr r3, [r7, #4] 8002cb0: 605a str r2, [r3, #4] } if ((dev->axis_en & BMM350_EN_Z_MSK) == BMM350_DISABLE) 8002cb2: 683b ldr r3, [r7, #0] 8002cb4: 7d5b ldrb r3, [r3, #21] 8002cb6: f003 0304 and.w r3, r3, #4 8002cba: 2b00 cmp r3, #0 8002cbc: d103 bne.n 8002cc6 { raw_data->raw_zdata = BMM350_DISABLE; 8002cbe: 687b ldr r3, [r7, #4] 8002cc0: 2200 movs r2, #0 8002cc2: 609a str r2, [r3, #8] 8002cc4: e006 b.n 8002cd4 } else { raw_data->raw_zdata = fix_sign(raw_mag_z, BMM350_SIGNED_24_BIT); 8002cc6: 2118 movs r1, #24 8002cc8: 69b8 ldr r0, [r7, #24] 8002cca: f000 fabb bl 8003244 8002cce: 4602 mov r2, r0 8002cd0: 687b ldr r3, [r7, #4] 8002cd2: 609a str r2, [r3, #8] } raw_data->raw_data_t = fix_sign(raw_temp, BMM350_SIGNED_24_BIT); 8002cd4: 2118 movs r1, #24 8002cd6: 6978 ldr r0, [r7, #20] 8002cd8: f000 fab4 bl 8003244 8002cdc: 4602 mov r2, r0 8002cde: 687b ldr r3, [r7, #4] 8002ce0: 60da str r2, [r3, #12] 8002ce2: e002 b.n 8002cea } } else { rslt = BMM350_E_NULL_PTR; 8002ce4: 23ff movs r3, #255 @ 0xff 8002ce6: f887 3027 strb.w r3, [r7, #39] @ 0x27 } return rslt; 8002cea: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 } 8002cee: 4618 mov r0, r3 8002cf0: 3728 adds r7, #40 @ 0x28 8002cf2: 46bd mov sp, r7 8002cf4: bd80 pop {r7, pc} 08002cf6 : * @brief This API is used to perform the magnetic reset of the sensor * which is necessary after a field shock (400mT field applied to sensor). * It sends flux guide or bit reset to the device in suspend mode. */ int8_t bmm350_magnetic_reset_and_wait(struct bmm350_dev *dev) { 8002cf6: b580 push {r7, lr} 8002cf8: b086 sub sp, #24 8002cfa: af00 add r7, sp, #0 8002cfc: 6078 str r0, [r7, #4] /* Variable to store the function result */ int8_t rslt; uint8_t pmu_cmd = 0; 8002cfe: 2300 movs r3, #0 8002d00: 757b strb r3, [r7, #21] struct bmm350_pmu_cmd_status_0 pmu_cmd_stat_0 = { 0 }; 8002d02: f107 030c add.w r3, r7, #12 8002d06: 2200 movs r2, #0 8002d08: 601a str r2, [r3, #0] 8002d0a: 809a strh r2, [r3, #4] uint8_t restore_normal = BMM350_DISABLE; 8002d0c: 2300 movs r3, #0 8002d0e: 75bb strb r3, [r7, #22] rslt = null_ptr_check(dev); 8002d10: 6878 ldr r0, [r7, #4] 8002d12: f000 fa77 bl 8003204 8002d16: 4603 mov r3, r0 8002d18: 75fb strb r3, [r7, #23] if ((rslt == BMM350_OK) && (dev->mraw_override)) 8002d1a: f997 3017 ldrsb.w r3, [r7, #23] 8002d1e: 2b00 cmp r3, #0 8002d20: d10c bne.n 8002d3c 8002d22: 687b ldr r3, [r7, #4] 8002d24: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 8002d28: 2b00 cmp r3, #0 8002d2a: d007 beq.n 8002d3c { rslt = dev->mraw_override(dev); 8002d2c: 687b ldr r3, [r7, #4] 8002d2e: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 8002d32: 6878 ldr r0, [r7, #4] 8002d34: 4798 blx r3 8002d36: 4603 mov r3, r0 8002d38: 75fb strb r3, [r7, #23] 8002d3a: e081 b.n 8002e40 } else { /* Read PMU CMD status */ rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev); 8002d3c: f107 030c add.w r3, r7, #12 8002d40: 6879 ldr r1, [r7, #4] 8002d42: 4618 mov r0, r3 8002d44: f000 fa15 bl 8003172 8002d48: 4603 mov r3, r0 8002d4a: 75fb strb r3, [r7, #23] /* Check the powermode is normal before performing magnetic reset */ if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pwr_mode_is_normal == BMM350_ENABLE)) 8002d4c: f997 3017 ldrsb.w r3, [r7, #23] 8002d50: 2b00 cmp r3, #0 8002d52: d10a bne.n 8002d6a 8002d54: 7bfb ldrb r3, [r7, #15] 8002d56: 2b01 cmp r3, #1 8002d58: d107 bne.n 8002d6a { restore_normal = BMM350_ENABLE; 8002d5a: 2301 movs r3, #1 8002d5c: 75bb strb r3, [r7, #22] /* Reset can only be triggered in suspend */ rslt = bmm350_set_powermode(BMM350_SUSPEND_MODE, dev); 8002d5e: 6879 ldr r1, [r7, #4] 8002d60: 2000 movs r0, #0 8002d62: f7ff fde9 bl 8002938 8002d66: 4603 mov r3, r0 8002d68: 75fb strb r3, [r7, #23] } if (rslt == BMM350_OK) 8002d6a: f997 3017 ldrsb.w r3, [r7, #23] 8002d6e: 2b00 cmp r3, #0 8002d70: d115 bne.n 8002d9e { /* Set BR to PMU_CMD register */ pmu_cmd = BMM350_PMU_CMD_BR; 8002d72: 2307 movs r3, #7 8002d74: 757b strb r3, [r7, #21] rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &pmu_cmd, 1, dev); 8002d76: f107 0115 add.w r1, r7, #21 8002d7a: 687b ldr r3, [r7, #4] 8002d7c: 2201 movs r2, #1 8002d7e: 2006 movs r0, #6 8002d80: f7ff fd36 bl 80027f0 8002d84: 4603 mov r3, r0 8002d86: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 8002d88: f997 3017 ldrsb.w r3, [r7, #23] 8002d8c: 2b00 cmp r3, #0 8002d8e: d106 bne.n 8002d9e { rslt = bmm350_delay_us(BMM350_BR_DELAY, dev); 8002d90: 6879 ldr r1, [r7, #4] 8002d92: f243 60b0 movw r0, #14000 @ 0x36b0 8002d96: f7ff fdb4 bl 8002902 8002d9a: 4603 mov r3, r0 8002d9c: 75fb strb r3, [r7, #23] } } if (rslt == BMM350_OK) 8002d9e: f997 3017 ldrsb.w r3, [r7, #23] 8002da2: 2b00 cmp r3, #0 8002da4: d110 bne.n 8002dc8 { /* Verify if PMU_CMD_STATUS_0 register has BR set */ rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev); 8002da6: f107 030c add.w r3, r7, #12 8002daa: 6879 ldr r1, [r7, #4] 8002dac: 4618 mov r0, r3 8002dae: f000 f9e0 bl 8003172 8002db2: 4603 mov r3, r0 8002db4: 75fb strb r3, [r7, #23] if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pmu_cmd_value != BMM350_PMU_CMD_STATUS_0_BR)) 8002db6: f997 3017 ldrsb.w r3, [r7, #23] 8002dba: 2b00 cmp r3, #0 8002dbc: d104 bne.n 8002dc8 8002dbe: 7c7b ldrb r3, [r7, #17] 8002dc0: 2b07 cmp r3, #7 8002dc2: d001 beq.n 8002dc8 { rslt = BMM350_E_PMU_CMD_VALUE; 8002dc4: 23f0 movs r3, #240 @ 0xf0 8002dc6: 75fb strb r3, [r7, #23] } } if (rslt == BMM350_OK) 8002dc8: f997 3017 ldrsb.w r3, [r7, #23] 8002dcc: 2b00 cmp r3, #0 8002dce: d115 bne.n 8002dfc { /* Set FGR to PMU_CMD register */ pmu_cmd = BMM350_PMU_CMD_FGR; 8002dd0: 2305 movs r3, #5 8002dd2: 757b strb r3, [r7, #21] rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, &pmu_cmd, 1, dev); 8002dd4: f107 0115 add.w r1, r7, #21 8002dd8: 687b ldr r3, [r7, #4] 8002dda: 2201 movs r2, #1 8002ddc: 2006 movs r0, #6 8002dde: f7ff fd07 bl 80027f0 8002de2: 4603 mov r3, r0 8002de4: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 8002de6: f997 3017 ldrsb.w r3, [r7, #23] 8002dea: 2b00 cmp r3, #0 8002dec: d106 bne.n 8002dfc { rslt = bmm350_delay_us(BMM350_FGR_DELAY, dev); 8002dee: 6879 ldr r1, [r7, #4] 8002df0: f244 6050 movw r0, #18000 @ 0x4650 8002df4: f7ff fd85 bl 8002902 8002df8: 4603 mov r3, r0 8002dfa: 75fb strb r3, [r7, #23] } } if (rslt == BMM350_OK) 8002dfc: f997 3017 ldrsb.w r3, [r7, #23] 8002e00: 2b00 cmp r3, #0 8002e02: d110 bne.n 8002e26 { /* Verify if PMU_CMD_STATUS_0 register has FGR set */ rslt = bmm350_get_pmu_cmd_status_0(&pmu_cmd_stat_0, dev); 8002e04: f107 030c add.w r3, r7, #12 8002e08: 6879 ldr r1, [r7, #4] 8002e0a: 4618 mov r0, r3 8002e0c: f000 f9b1 bl 8003172 8002e10: 4603 mov r3, r0 8002e12: 75fb strb r3, [r7, #23] if ((rslt == BMM350_OK) && (pmu_cmd_stat_0.pmu_cmd_value != BMM350_PMU_CMD_STATUS_0_FGR)) 8002e14: f997 3017 ldrsb.w r3, [r7, #23] 8002e18: 2b00 cmp r3, #0 8002e1a: d104 bne.n 8002e26 8002e1c: 7c7b ldrb r3, [r7, #17] 8002e1e: 2b05 cmp r3, #5 8002e20: d001 beq.n 8002e26 { rslt = BMM350_E_PMU_CMD_VALUE; 8002e22: 23f0 movs r3, #240 @ 0xf0 8002e24: 75fb strb r3, [r7, #23] } } if ((rslt == BMM350_OK) && (restore_normal == BMM350_ENABLE)) 8002e26: f997 3017 ldrsb.w r3, [r7, #23] 8002e2a: 2b00 cmp r3, #0 8002e2c: d108 bne.n 8002e40 8002e2e: 7dbb ldrb r3, [r7, #22] 8002e30: 2b01 cmp r3, #1 8002e32: d105 bne.n 8002e40 { rslt = bmm350_set_powermode(BMM350_NORMAL_MODE, dev); 8002e34: 6879 ldr r1, [r7, #4] 8002e36: 2001 movs r0, #1 8002e38: f7ff fd7e bl 8002938 8002e3c: 4603 mov r3, r0 8002e3e: 75fb strb r3, [r7, #23] } } return rslt; 8002e40: f997 3017 ldrsb.w r3, [r7, #23] } 8002e44: 4618 mov r0, r3 8002e46: 3718 adds r7, #24 8002e48: 46bd mov sp, r7 8002e4a: bd80 pop {r7, pc} 08002e4c : /*! * @brief This API is used to perform compensation for raw magnetometer and temperature data. */ int8_t bmm350_get_compensated_mag_xyz_temp_data(struct bmm350_mag_temp_data *mag_temp_data, struct bmm350_dev *dev) { 8002e4c: b580 push {r7, lr} 8002e4e: b096 sub sp, #88 @ 0x58 8002e50: af00 add r7, sp, #0 8002e52: 6078 str r0, [r7, #4] 8002e54: 6039 str r1, [r7, #0] /* Variable to store the function result */ int8_t rslt; uint8_t indx; float out_data[4] = { 0.0f }; 8002e56: f107 0338 add.w r3, r7, #56 @ 0x38 8002e5a: 2200 movs r2, #0 8002e5c: 601a str r2, [r3, #0] 8002e5e: 605a str r2, [r3, #4] 8002e60: 609a str r2, [r3, #8] 8002e62: 60da str r2, [r3, #12] float dut_offset_coef[3], dut_sensit_coef[3], dut_tco[3], dut_tcs[3]; float cr_ax_comp_x, cr_ax_comp_y, cr_ax_comp_z; if (mag_temp_data != NULL) 8002e64: 687b ldr r3, [r7, #4] 8002e66: 2b00 cmp r3, #0 8002e68: f000 817a beq.w 8003160 { /* Reads raw magnetic x,y and z axis along with temperature */ rslt = read_out_raw_data(out_data, dev); 8002e6c: f107 0338 add.w r3, r7, #56 @ 0x38 8002e70: 6839 ldr r1, [r7, #0] 8002e72: 4618 mov r0, r3 8002e74: f000 fc9c bl 80037b0 8002e78: 4603 mov r3, r0 8002e7a: f887 3057 strb.w r3, [r7, #87] @ 0x57 if (rslt == BMM350_OK) 8002e7e: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57 8002e82: 2b00 cmp r3, #0 8002e84: f040 813a bne.w 80030fc { /* Apply compensation to temperature reading */ out_data[3] = (1 + dev->mag_comp.dut_sensit_coef.t_sens) * out_data[3] + 8002e88: 683b ldr r3, [r7, #0] 8002e8a: edd3 7a0a vldr s15, [r3, #40] @ 0x28 8002e8e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8002e92: ee37 7a87 vadd.f32 s14, s15, s14 8002e96: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8002e9a: ee27 7a27 vmul.f32 s14, s14, s15 dev->mag_comp.dut_offset_coef.t_offs; 8002e9e: 683b ldr r3, [r7, #0] 8002ea0: edd3 7a06 vldr s15, [r3, #24] out_data[3] = (1 + dev->mag_comp.dut_sensit_coef.t_sens) * out_data[3] + 8002ea4: ee77 7a27 vadd.f32 s15, s14, s15 8002ea8: edc7 7a11 vstr s15, [r7, #68] @ 0x44 /* Store magnetic compensation structure to an array */ dut_offset_coef[0] = dev->mag_comp.dut_offset_coef.offset_x; 8002eac: 683b ldr r3, [r7, #0] 8002eae: 69db ldr r3, [r3, #28] 8002eb0: 62fb str r3, [r7, #44] @ 0x2c dut_offset_coef[1] = dev->mag_comp.dut_offset_coef.offset_y; 8002eb2: 683b ldr r3, [r7, #0] 8002eb4: 6a1b ldr r3, [r3, #32] 8002eb6: 633b str r3, [r7, #48] @ 0x30 dut_offset_coef[2] = dev->mag_comp.dut_offset_coef.offset_z; 8002eb8: 683b ldr r3, [r7, #0] 8002eba: 6a5b ldr r3, [r3, #36] @ 0x24 8002ebc: 637b str r3, [r7, #52] @ 0x34 dut_sensit_coef[0] = dev->mag_comp.dut_sensit_coef.sens_x; 8002ebe: 683b ldr r3, [r7, #0] 8002ec0: 6adb ldr r3, [r3, #44] @ 0x2c 8002ec2: 623b str r3, [r7, #32] dut_sensit_coef[1] = dev->mag_comp.dut_sensit_coef.sens_y; 8002ec4: 683b ldr r3, [r7, #0] 8002ec6: 6b1b ldr r3, [r3, #48] @ 0x30 8002ec8: 627b str r3, [r7, #36] @ 0x24 dut_sensit_coef[2] = dev->mag_comp.dut_sensit_coef.sens_z; 8002eca: 683b ldr r3, [r7, #0] 8002ecc: 6b5b ldr r3, [r3, #52] @ 0x34 8002ece: 62bb str r3, [r7, #40] @ 0x28 dut_tco[0] = dev->mag_comp.dut_tco.tco_x; 8002ed0: 683b ldr r3, [r7, #0] 8002ed2: 6b9b ldr r3, [r3, #56] @ 0x38 8002ed4: 617b str r3, [r7, #20] dut_tco[1] = dev->mag_comp.dut_tco.tco_y; 8002ed6: 683b ldr r3, [r7, #0] 8002ed8: 6bdb ldr r3, [r3, #60] @ 0x3c 8002eda: 61bb str r3, [r7, #24] dut_tco[2] = dev->mag_comp.dut_tco.tco_z; 8002edc: 683b ldr r3, [r7, #0] 8002ede: 6c1b ldr r3, [r3, #64] @ 0x40 8002ee0: 61fb str r3, [r7, #28] dut_tcs[0] = dev->mag_comp.dut_tcs.tcs_x; 8002ee2: 683b ldr r3, [r7, #0] 8002ee4: 6c5b ldr r3, [r3, #68] @ 0x44 8002ee6: 60bb str r3, [r7, #8] dut_tcs[1] = dev->mag_comp.dut_tcs.tcs_y; 8002ee8: 683b ldr r3, [r7, #0] 8002eea: 6c9b ldr r3, [r3, #72] @ 0x48 8002eec: 60fb str r3, [r7, #12] dut_tcs[2] = dev->mag_comp.dut_tcs.tcs_z; 8002eee: 683b ldr r3, [r7, #0] 8002ef0: 6cdb ldr r3, [r3, #76] @ 0x4c 8002ef2: 613b str r3, [r7, #16] /* Compensate raw magnetic data */ for (indx = 0; indx < 3; indx++) 8002ef4: 2300 movs r3, #0 8002ef6: f887 3056 strb.w r3, [r7, #86] @ 0x56 8002efa: e086 b.n 800300a { out_data[indx] *= 1 + dut_sensit_coef[indx]; 8002efc: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002f00: 009b lsls r3, r3, #2 8002f02: 3358 adds r3, #88 @ 0x58 8002f04: 443b add r3, r7 8002f06: 3b20 subs r3, #32 8002f08: ed93 7a00 vldr s14, [r3] 8002f0c: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002f10: 009b lsls r3, r3, #2 8002f12: 3358 adds r3, #88 @ 0x58 8002f14: 443b add r3, r7 8002f16: 3b38 subs r3, #56 @ 0x38 8002f18: edd3 7a00 vldr s15, [r3] 8002f1c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8002f20: ee77 7aa6 vadd.f32 s15, s15, s13 8002f24: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002f28: ee67 7a27 vmul.f32 s15, s14, s15 8002f2c: 009b lsls r3, r3, #2 8002f2e: 3358 adds r3, #88 @ 0x58 8002f30: 443b add r3, r7 8002f32: 3b20 subs r3, #32 8002f34: edc3 7a00 vstr s15, [r3] out_data[indx] += dut_offset_coef[indx]; 8002f38: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002f3c: 009b lsls r3, r3, #2 8002f3e: 3358 adds r3, #88 @ 0x58 8002f40: 443b add r3, r7 8002f42: 3b20 subs r3, #32 8002f44: ed93 7a00 vldr s14, [r3] 8002f48: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002f4c: 009b lsls r3, r3, #2 8002f4e: 3358 adds r3, #88 @ 0x58 8002f50: 443b add r3, r7 8002f52: 3b2c subs r3, #44 @ 0x2c 8002f54: edd3 7a00 vldr s15, [r3] 8002f58: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002f5c: ee77 7a27 vadd.f32 s15, s14, s15 8002f60: 009b lsls r3, r3, #2 8002f62: 3358 adds r3, #88 @ 0x58 8002f64: 443b add r3, r7 8002f66: 3b20 subs r3, #32 8002f68: edc3 7a00 vstr s15, [r3] out_data[indx] += dut_tco[indx] * (out_data[3] - dev->mag_comp.dut_t0); 8002f6c: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002f70: 009b lsls r3, r3, #2 8002f72: 3358 adds r3, #88 @ 0x58 8002f74: 443b add r3, r7 8002f76: 3b20 subs r3, #32 8002f78: ed93 7a00 vldr s14, [r3] 8002f7c: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002f80: 009b lsls r3, r3, #2 8002f82: 3358 adds r3, #88 @ 0x58 8002f84: 443b add r3, r7 8002f86: 3b44 subs r3, #68 @ 0x44 8002f88: edd3 6a00 vldr s13, [r3] 8002f8c: ed97 6a11 vldr s12, [r7, #68] @ 0x44 8002f90: 683b ldr r3, [r7, #0] 8002f92: edd3 7a14 vldr s15, [r3, #80] @ 0x50 8002f96: ee76 7a67 vsub.f32 s15, s12, s15 8002f9a: ee66 7aa7 vmul.f32 s15, s13, s15 8002f9e: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002fa2: ee77 7a27 vadd.f32 s15, s14, s15 8002fa6: 009b lsls r3, r3, #2 8002fa8: 3358 adds r3, #88 @ 0x58 8002faa: 443b add r3, r7 8002fac: 3b20 subs r3, #32 8002fae: edc3 7a00 vstr s15, [r3] out_data[indx] /= 1 + dut_tcs[indx] * (out_data[3] - dev->mag_comp.dut_t0); 8002fb2: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002fb6: 009b lsls r3, r3, #2 8002fb8: 3358 adds r3, #88 @ 0x58 8002fba: 443b add r3, r7 8002fbc: 3b20 subs r3, #32 8002fbe: edd3 6a00 vldr s13, [r3] 8002fc2: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002fc6: 009b lsls r3, r3, #2 8002fc8: 3358 adds r3, #88 @ 0x58 8002fca: 443b add r3, r7 8002fcc: 3b50 subs r3, #80 @ 0x50 8002fce: ed93 7a00 vldr s14, [r3] 8002fd2: ed97 6a11 vldr s12, [r7, #68] @ 0x44 8002fd6: 683b ldr r3, [r7, #0] 8002fd8: edd3 7a14 vldr s15, [r3, #80] @ 0x50 8002fdc: ee76 7a67 vsub.f32 s15, s12, s15 8002fe0: ee67 7a27 vmul.f32 s15, s14, s15 8002fe4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8002fe8: ee37 7a87 vadd.f32 s14, s15, s14 8002fec: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8002ff0: eec6 7a87 vdiv.f32 s15, s13, s14 8002ff4: 009b lsls r3, r3, #2 8002ff6: 3358 adds r3, #88 @ 0x58 8002ff8: 443b add r3, r7 8002ffa: 3b20 subs r3, #32 8002ffc: edc3 7a00 vstr s15, [r3] for (indx = 0; indx < 3; indx++) 8003000: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 8003004: 3301 adds r3, #1 8003006: f887 3056 strb.w r3, [r7, #86] @ 0x56 800300a: f897 3056 ldrb.w r3, [r7, #86] @ 0x56 800300e: 2b02 cmp r3, #2 8003010: f67f af74 bls.w 8002efc } cr_ax_comp_x = (out_data[0] - dev->mag_comp.cross_axis.cross_x_y * out_data[1]) / 8003014: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8003018: 683b ldr r3, [r7, #0] 800301a: edd3 6a15 vldr s13, [r3, #84] @ 0x54 800301e: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 8003022: ee66 7aa7 vmul.f32 s15, s13, s15 8003026: ee77 6a67 vsub.f32 s13, s14, s15 (1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y); 800302a: 683b ldr r3, [r7, #0] 800302c: ed93 7a16 vldr s14, [r3, #88] @ 0x58 8003030: 683b ldr r3, [r7, #0] 8003032: edd3 7a15 vldr s15, [r3, #84] @ 0x54 8003036: ee67 7a27 vmul.f32 s15, s14, s15 800303a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800303e: ee37 7a67 vsub.f32 s14, s14, s15 cr_ax_comp_x = (out_data[0] - dev->mag_comp.cross_axis.cross_x_y * out_data[1]) / 8003042: eec6 7a87 vdiv.f32 s15, s13, s14 8003046: edc7 7a14 vstr s15, [r7, #80] @ 0x50 cr_ax_comp_y = (out_data[1] - dev->mag_comp.cross_axis.cross_y_x * out_data[0]) / 800304a: ed97 7a0f vldr s14, [r7, #60] @ 0x3c 800304e: 683b ldr r3, [r7, #0] 8003050: edd3 6a16 vldr s13, [r3, #88] @ 0x58 8003054: edd7 7a0e vldr s15, [r7, #56] @ 0x38 8003058: ee66 7aa7 vmul.f32 s15, s13, s15 800305c: ee77 6a67 vsub.f32 s13, s14, s15 (1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y); 8003060: 683b ldr r3, [r7, #0] 8003062: ed93 7a16 vldr s14, [r3, #88] @ 0x58 8003066: 683b ldr r3, [r7, #0] 8003068: edd3 7a15 vldr s15, [r3, #84] @ 0x54 800306c: ee67 7a27 vmul.f32 s15, s14, s15 8003070: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8003074: ee37 7a67 vsub.f32 s14, s14, s15 cr_ax_comp_y = (out_data[1] - dev->mag_comp.cross_axis.cross_y_x * out_data[0]) / 8003078: eec6 7a87 vdiv.f32 s15, s13, s14 800307c: edc7 7a13 vstr s15, [r7, #76] @ 0x4c cr_ax_comp_z = (out_data[2] + 8003080: ed97 7a10 vldr s14, [r7, #64] @ 0x40 (out_data[0] * 8003084: edd7 6a0e vldr s13, [r7, #56] @ 0x38 (dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_z_y - 8003088: 683b ldr r3, [r7, #0] 800308a: ed93 6a16 vldr s12, [r3, #88] @ 0x58 800308e: 683b ldr r3, [r7, #0] 8003090: edd3 7a18 vldr s15, [r3, #96] @ 0x60 8003094: ee26 6a27 vmul.f32 s12, s12, s15 dev->mag_comp.cross_axis.cross_z_x) - out_data[1] * 8003098: 683b ldr r3, [r7, #0] 800309a: edd3 7a17 vldr s15, [r3, #92] @ 0x5c (dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_z_y - 800309e: ee76 7a67 vsub.f32 s15, s12, s15 (out_data[0] * 80030a2: ee66 6aa7 vmul.f32 s13, s13, s15 dev->mag_comp.cross_axis.cross_z_x) - out_data[1] * 80030a6: ed97 6a0f vldr s12, [r7, #60] @ 0x3c (dev->mag_comp.cross_axis.cross_z_y - dev->mag_comp.cross_axis.cross_x_y * 80030aa: 683b ldr r3, [r7, #0] 80030ac: edd3 5a18 vldr s11, [r3, #96] @ 0x60 80030b0: 683b ldr r3, [r7, #0] 80030b2: ed93 5a15 vldr s10, [r3, #84] @ 0x54 dev->mag_comp.cross_axis.cross_z_x)) / 80030b6: 683b ldr r3, [r7, #0] 80030b8: edd3 7a17 vldr s15, [r3, #92] @ 0x5c (dev->mag_comp.cross_axis.cross_z_y - dev->mag_comp.cross_axis.cross_x_y * 80030bc: ee65 7a27 vmul.f32 s15, s10, s15 80030c0: ee75 7ae7 vsub.f32 s15, s11, s15 dev->mag_comp.cross_axis.cross_z_x) - out_data[1] * 80030c4: ee66 7a27 vmul.f32 s15, s12, s15 80030c8: ee36 6ae7 vsub.f32 s12, s13, s15 (1 - dev->mag_comp.cross_axis.cross_y_x * dev->mag_comp.cross_axis.cross_x_y)); 80030cc: 683b ldr r3, [r7, #0] 80030ce: edd3 6a16 vldr s13, [r3, #88] @ 0x58 80030d2: 683b ldr r3, [r7, #0] 80030d4: edd3 7a15 vldr s15, [r3, #84] @ 0x54 80030d8: ee66 7aa7 vmul.f32 s15, s13, s15 80030dc: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80030e0: ee76 6ae7 vsub.f32 s13, s13, s15 dev->mag_comp.cross_axis.cross_z_x)) / 80030e4: eec6 7a26 vdiv.f32 s15, s12, s13 cr_ax_comp_z = 80030e8: ee77 7a27 vadd.f32 s15, s14, s15 80030ec: edc7 7a12 vstr s15, [r7, #72] @ 0x48 out_data[0] = cr_ax_comp_x; 80030f0: 6d3b ldr r3, [r7, #80] @ 0x50 80030f2: 63bb str r3, [r7, #56] @ 0x38 out_data[1] = cr_ax_comp_y; 80030f4: 6cfb ldr r3, [r7, #76] @ 0x4c 80030f6: 63fb str r3, [r7, #60] @ 0x3c out_data[2] = cr_ax_comp_z; 80030f8: 6cbb ldr r3, [r7, #72] @ 0x48 80030fa: 643b str r3, [r7, #64] @ 0x40 } if (rslt == BMM350_OK) 80030fc: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57 8003100: 2b00 cmp r3, #0 8003102: d130 bne.n 8003166 { if ((dev->axis_en & BMM350_EN_X_MSK) == BMM350_DISABLE) 8003104: 683b ldr r3, [r7, #0] 8003106: 7d5b ldrb r3, [r3, #21] 8003108: f003 0301 and.w r3, r3, #1 800310c: 2b00 cmp r3, #0 800310e: d104 bne.n 800311a { mag_temp_data->x = BMM350_DISABLE; 8003110: 687b ldr r3, [r7, #4] 8003112: f04f 0200 mov.w r2, #0 8003116: 601a str r2, [r3, #0] 8003118: e002 b.n 8003120 } else { mag_temp_data->x = out_data[0]; 800311a: 6bba ldr r2, [r7, #56] @ 0x38 800311c: 687b ldr r3, [r7, #4] 800311e: 601a str r2, [r3, #0] } if ((dev->axis_en & BMM350_EN_Y_MSK) == BMM350_DISABLE) 8003120: 683b ldr r3, [r7, #0] 8003122: 7d5b ldrb r3, [r3, #21] 8003124: f003 0302 and.w r3, r3, #2 8003128: 2b00 cmp r3, #0 800312a: d104 bne.n 8003136 { mag_temp_data->y = BMM350_DISABLE; 800312c: 687b ldr r3, [r7, #4] 800312e: f04f 0200 mov.w r2, #0 8003132: 605a str r2, [r3, #4] 8003134: e002 b.n 800313c } else { mag_temp_data->y = out_data[1]; 8003136: 6bfa ldr r2, [r7, #60] @ 0x3c 8003138: 687b ldr r3, [r7, #4] 800313a: 605a str r2, [r3, #4] } if ((dev->axis_en & BMM350_EN_Z_MSK) == BMM350_DISABLE) 800313c: 683b ldr r3, [r7, #0] 800313e: 7d5b ldrb r3, [r3, #21] 8003140: f003 0304 and.w r3, r3, #4 8003144: 2b00 cmp r3, #0 8003146: d104 bne.n 8003152 { mag_temp_data->z = BMM350_DISABLE; 8003148: 687b ldr r3, [r7, #4] 800314a: f04f 0200 mov.w r2, #0 800314e: 609a str r2, [r3, #8] 8003150: e002 b.n 8003158 } else { mag_temp_data->z = out_data[2]; 8003152: 6c3a ldr r2, [r7, #64] @ 0x40 8003154: 687b ldr r3, [r7, #4] 8003156: 609a str r2, [r3, #8] } mag_temp_data->temperature = out_data[3]; 8003158: 6c7a ldr r2, [r7, #68] @ 0x44 800315a: 687b ldr r3, [r7, #4] 800315c: 60da str r2, [r3, #12] 800315e: e002 b.n 8003166 } } else { rslt = BMM350_E_NULL_PTR; 8003160: 23ff movs r3, #255 @ 0xff 8003162: f887 3057 strb.w r3, [r7, #87] @ 0x57 } return rslt; 8003166: f997 3057 ldrsb.w r3, [r7, #87] @ 0x57 } 800316a: 4618 mov r0, r3 800316c: 3758 adds r7, #88 @ 0x58 800316e: 46bd mov sp, r7 8003170: bd80 pop {r7, pc} 08003172 : /*! * @brief This API gets the PMU command status 0 value */ int8_t bmm350_get_pmu_cmd_status_0(struct bmm350_pmu_cmd_status_0 *pmu_cmd_stat_0, struct bmm350_dev *dev) { 8003172: b580 push {r7, lr} 8003174: b084 sub sp, #16 8003176: af00 add r7, sp, #0 8003178: 6078 str r0, [r7, #4] 800317a: 6039 str r1, [r7, #0] /* Variable to store the function result */ int8_t rslt; uint8_t reg_data; if (pmu_cmd_stat_0 != NULL) 800317c: 687b ldr r3, [r7, #4] 800317e: 2b00 cmp r3, #0 8003180: d038 beq.n 80031f4 { /* Get PMU command status 0 data */ rslt = bmm350_get_regs(BMM350_REG_PMU_CMD_STATUS_0, ®_data, 1, dev); 8003182: f107 010e add.w r1, r7, #14 8003186: 683b ldr r3, [r7, #0] 8003188: 2201 movs r2, #1 800318a: 2007 movs r0, #7 800318c: f7ff fb64 bl 8002858 8003190: 4603 mov r3, r0 8003192: 73fb strb r3, [r7, #15] if (rslt == BMM350_OK) 8003194: f997 300f ldrsb.w r3, [r7, #15] 8003198: 2b00 cmp r3, #0 800319a: d12d bne.n 80031f8 { pmu_cmd_stat_0->pmu_cmd_busy = BMM350_GET_BITS_POS_0(reg_data, BMM350_PMU_CMD_BUSY); 800319c: 7bbb ldrb r3, [r7, #14] 800319e: f003 0301 and.w r3, r3, #1 80031a2: b2da uxtb r2, r3 80031a4: 687b ldr r3, [r7, #4] 80031a6: 701a strb r2, [r3, #0] pmu_cmd_stat_0->odr_ovwr = BMM350_GET_BITS(reg_data, BMM350_ODR_OVWR); 80031a8: 7bbb ldrb r3, [r7, #14] 80031aa: 105b asrs r3, r3, #1 80031ac: b2db uxtb r3, r3 80031ae: f003 0301 and.w r3, r3, #1 80031b2: b2da uxtb r2, r3 80031b4: 687b ldr r3, [r7, #4] 80031b6: 705a strb r2, [r3, #1] pmu_cmd_stat_0->avr_ovwr = BMM350_GET_BITS(reg_data, BMM350_AVG_OVWR); 80031b8: 7bbb ldrb r3, [r7, #14] 80031ba: 109b asrs r3, r3, #2 80031bc: b2db uxtb r3, r3 80031be: f003 0301 and.w r3, r3, #1 80031c2: b2da uxtb r2, r3 80031c4: 687b ldr r3, [r7, #4] 80031c6: 709a strb r2, [r3, #2] pmu_cmd_stat_0->pwr_mode_is_normal = BMM350_GET_BITS(reg_data, BMM350_PWR_MODE_IS_NORMAL); 80031c8: 7bbb ldrb r3, [r7, #14] 80031ca: 10db asrs r3, r3, #3 80031cc: b2db uxtb r3, r3 80031ce: f003 0301 and.w r3, r3, #1 80031d2: b2da uxtb r2, r3 80031d4: 687b ldr r3, [r7, #4] 80031d6: 70da strb r2, [r3, #3] pmu_cmd_stat_0->cmd_is_illegal = BMM350_GET_BITS(reg_data, BMM350_CMD_IS_ILLEGAL); 80031d8: 7bbb ldrb r3, [r7, #14] 80031da: 111b asrs r3, r3, #4 80031dc: b2db uxtb r3, r3 80031de: f003 0301 and.w r3, r3, #1 80031e2: b2da uxtb r2, r3 80031e4: 687b ldr r3, [r7, #4] 80031e6: 711a strb r2, [r3, #4] pmu_cmd_stat_0->pmu_cmd_value = BMM350_GET_BITS(reg_data, BMM350_PMU_CMD_VALUE); 80031e8: 7bbb ldrb r3, [r7, #14] 80031ea: 095b lsrs r3, r3, #5 80031ec: b2da uxtb r2, r3 80031ee: 687b ldr r3, [r7, #4] 80031f0: 715a strb r2, [r3, #5] 80031f2: e001 b.n 80031f8 } } else { rslt = BMM350_E_NULL_PTR; 80031f4: 23ff movs r3, #255 @ 0xff 80031f6: 73fb strb r3, [r7, #15] } return rslt; 80031f8: f997 300f ldrsb.w r3, [r7, #15] } 80031fc: 4618 mov r0, r3 80031fe: 3710 adds r7, #16 8003200: 46bd mov sp, r7 8003202: bd80 pop {r7, pc} 08003204 : /*! * @brief This internal API is used to validate the device structure pointer for * null conditions. */ static int8_t null_ptr_check(const struct bmm350_dev *dev) { 8003204: b480 push {r7} 8003206: b085 sub sp, #20 8003208: af00 add r7, sp, #0 800320a: 6078 str r0, [r7, #4] /* Variable to store the function result */ int8_t rslt; if ((dev == NULL) || (dev->read == NULL) || (dev->write == NULL) || (dev->delay_us == NULL)) 800320c: 687b ldr r3, [r7, #4] 800320e: 2b00 cmp r3, #0 8003210: d00b beq.n 800322a 8003212: 687b ldr r3, [r7, #4] 8003214: 689b ldr r3, [r3, #8] 8003216: 2b00 cmp r3, #0 8003218: d007 beq.n 800322a 800321a: 687b ldr r3, [r7, #4] 800321c: 68db ldr r3, [r3, #12] 800321e: 2b00 cmp r3, #0 8003220: d003 beq.n 800322a 8003222: 687b ldr r3, [r7, #4] 8003224: 691b ldr r3, [r3, #16] 8003226: 2b00 cmp r3, #0 8003228: d102 bne.n 8003230 { /* Device structure pointer is not valid */ rslt = BMM350_E_NULL_PTR; 800322a: 23ff movs r3, #255 @ 0xff 800322c: 73fb strb r3, [r7, #15] 800322e: e001 b.n 8003234 } else { /* Device structure is fine */ rslt = BMM350_OK; 8003230: 2300 movs r3, #0 8003232: 73fb strb r3, [r7, #15] } return rslt; 8003234: f997 300f ldrsb.w r3, [r7, #15] } 8003238: 4618 mov r0, r3 800323a: 3714 adds r7, #20 800323c: 46bd mov sp, r7 800323e: f85d 7b04 ldr.w r7, [sp], #4 8003242: 4770 bx lr 08003244 : /*! * @brief This internal API converts the raw data from the IC data registers to signed integer */ static int32_t fix_sign(uint32_t inval, int8_t number_of_bits) { 8003244: b480 push {r7} 8003246: b085 sub sp, #20 8003248: af00 add r7, sp, #0 800324a: 6078 str r0, [r7, #4] 800324c: 460b mov r3, r1 800324e: 70fb strb r3, [r7, #3] int32_t power = 0; 8003250: 2300 movs r3, #0 8003252: 60fb str r3, [r7, #12] int32_t retval; switch (number_of_bits) 8003254: f997 3003 ldrsb.w r3, [r7, #3] 8003258: 3b08 subs r3, #8 800325a: 2b10 cmp r3, #16 800325c: d837 bhi.n 80032ce 800325e: a201 add r2, pc, #4 @ (adr r2, 8003264 ) 8003260: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003264: 080032a9 .word 0x080032a9 8003268: 080032cf .word 0x080032cf 800326c: 080032cf .word 0x080032cf 8003270: 080032cf .word 0x080032cf 8003274: 080032af .word 0x080032af 8003278: 080032cf .word 0x080032cf 800327c: 080032cf .word 0x080032cf 8003280: 080032cf .word 0x080032cf 8003284: 080032b7 .word 0x080032b7 8003288: 080032cf .word 0x080032cf 800328c: 080032cf .word 0x080032cf 8003290: 080032cf .word 0x080032cf 8003294: 080032cf .word 0x080032cf 8003298: 080032bf .word 0x080032bf 800329c: 080032cf .word 0x080032cf 80032a0: 080032cf .word 0x080032cf 80032a4: 080032c7 .word 0x080032c7 { case BMM350_SIGNED_8_BIT: power = 128; /* 2^7 */ 80032a8: 2380 movs r3, #128 @ 0x80 80032aa: 60fb str r3, [r7, #12] break; 80032ac: e012 b.n 80032d4 case BMM350_SIGNED_12_BIT: power = 2048; /* 2^11 */ 80032ae: f44f 6300 mov.w r3, #2048 @ 0x800 80032b2: 60fb str r3, [r7, #12] break; 80032b4: e00e b.n 80032d4 case BMM350_SIGNED_16_BIT: power = 32768; /* 2^15 */ 80032b6: f44f 4300 mov.w r3, #32768 @ 0x8000 80032ba: 60fb str r3, [r7, #12] break; 80032bc: e00a b.n 80032d4 case BMM350_SIGNED_21_BIT: power = 1048576; /* 2^20 */ 80032be: f44f 1380 mov.w r3, #1048576 @ 0x100000 80032c2: 60fb str r3, [r7, #12] break; 80032c4: e006 b.n 80032d4 case BMM350_SIGNED_24_BIT: power = 8388608; /* 2^23 */ 80032c6: f44f 0300 mov.w r3, #8388608 @ 0x800000 80032ca: 60fb str r3, [r7, #12] break; 80032cc: e002 b.n 80032d4 default: power = 0; 80032ce: 2300 movs r3, #0 80032d0: 60fb str r3, [r7, #12] break; 80032d2: bf00 nop } retval = (int32_t)inval; 80032d4: 687b ldr r3, [r7, #4] 80032d6: 60bb str r3, [r7, #8] if (retval >= power) 80032d8: 68ba ldr r2, [r7, #8] 80032da: 68fb ldr r3, [r7, #12] 80032dc: 429a cmp r2, r3 80032de: db04 blt.n 80032ea { retval = retval - (power * 2); 80032e0: 68fb ldr r3, [r7, #12] 80032e2: 005b lsls r3, r3, #1 80032e4: 68ba ldr r2, [r7, #8] 80032e6: 1ad3 subs r3, r2, r3 80032e8: 60bb str r3, [r7, #8] } return retval; 80032ea: 68bb ldr r3, [r7, #8] } 80032ec: 4618 mov r0, r3 80032ee: 3714 adds r7, #20 80032f0: 46bd mov sp, r7 80032f2: f85d 7b04 ldr.w r7, [sp], #4 80032f6: 4770 bx lr 080032f8 : /*! * @brief This internal API is used to read OTP word */ static int8_t read_otp_word(uint8_t addr, uint16_t *lsb_msb, struct bmm350_dev *dev) { 80032f8: b580 push {r7, lr} 80032fa: b086 sub sp, #24 80032fc: af00 add r7, sp, #0 80032fe: 4603 mov r3, r0 8003300: 60b9 str r1, [r7, #8] 8003302: 607a str r2, [r7, #4] 8003304: 73fb strb r3, [r7, #15] /* Variable to store the function result */ int8_t rslt; uint8_t otp_cmd, otp_status = 0, otp_err = BMM350_OTP_STATUS_NO_ERROR, lsb = 0, msb = 0; 8003306: 2300 movs r3, #0 8003308: 753b strb r3, [r7, #20] 800330a: 2300 movs r3, #0 800330c: 75bb strb r3, [r7, #22] 800330e: 2300 movs r3, #0 8003310: 74fb strb r3, [r7, #19] 8003312: 2300 movs r3, #0 8003314: 74bb strb r3, [r7, #18] if (lsb_msb != NULL) 8003316: 68bb ldr r3, [r7, #8] 8003318: 2b00 cmp r3, #0 800331a: f000 8087 beq.w 800342c { /* Set OTP command at specified address */ otp_cmd = BMM350_OTP_CMD_DIR_READ | (addr & BMM350_OTP_WORD_ADDR_MSK); 800331e: f997 300f ldrsb.w r3, [r7, #15] 8003322: f003 031f and.w r3, r3, #31 8003326: b25b sxtb r3, r3 8003328: f043 0320 orr.w r3, r3, #32 800332c: b25b sxtb r3, r3 800332e: b2db uxtb r3, r3 8003330: 757b strb r3, [r7, #21] rslt = bmm350_set_regs(BMM350_REG_OTP_CMD_REG, &otp_cmd, 1, dev); 8003332: f107 0115 add.w r1, r7, #21 8003336: 687b ldr r3, [r7, #4] 8003338: 2201 movs r2, #1 800333a: 2050 movs r0, #80 @ 0x50 800333c: f7ff fa58 bl 80027f0 8003340: 4603 mov r3, r0 8003342: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 8003344: f997 3017 ldrsb.w r3, [r7, #23] 8003348: 2b00 cmp r3, #0 800334a: d14c bne.n 80033e6 { do { rslt = bmm350_delay_us(300, dev); 800334c: 6879 ldr r1, [r7, #4] 800334e: f44f 7096 mov.w r0, #300 @ 0x12c 8003352: f7ff fad6 bl 8002902 8003356: 4603 mov r3, r0 8003358: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 800335a: f997 3017 ldrsb.w r3, [r7, #23] 800335e: 2b00 cmp r3, #0 8003360: d10f bne.n 8003382 { /* Get OTP status */ rslt = bmm350_get_regs(BMM350_REG_OTP_STATUS_REG, &otp_status, 1, dev); 8003362: f107 0114 add.w r1, r7, #20 8003366: 687b ldr r3, [r7, #4] 8003368: 2201 movs r2, #1 800336a: 2055 movs r0, #85 @ 0x55 800336c: f7ff fa74 bl 8002858 8003370: 4603 mov r3, r0 8003372: 75fb strb r3, [r7, #23] otp_err = BMM350_OTP_STATUS_ERROR(otp_status); 8003374: 7d3b ldrb r3, [r7, #20] 8003376: f023 031f bic.w r3, r3, #31 800337a: 75bb strb r3, [r7, #22] if (otp_err != BMM350_OTP_STATUS_NO_ERROR) 800337c: 7dbb ldrb r3, [r7, #22] 800337e: 2b00 cmp r3, #0 8003380: d109 bne.n 8003396 { break; } } } while ((!(otp_status & BMM350_OTP_STATUS_CMD_DONE)) && (rslt == BMM350_OK)); 8003382: 7d3b ldrb r3, [r7, #20] 8003384: f003 0301 and.w r3, r3, #1 8003388: 2b00 cmp r3, #0 800338a: d105 bne.n 8003398 800338c: f997 3017 ldrsb.w r3, [r7, #23] 8003390: 2b00 cmp r3, #0 8003392: d0db beq.n 800334c 8003394: e000 b.n 8003398 break; 8003396: bf00 nop if (otp_err != BMM350_OTP_STATUS_NO_ERROR) 8003398: 7dbb ldrb r3, [r7, #22] 800339a: 2b00 cmp r3, #0 800339c: d023 beq.n 80033e6 { switch (otp_err) 800339e: 7dbb ldrb r3, [r7, #22] 80033a0: 2ba0 cmp r3, #160 @ 0xa0 80033a2: d01a beq.n 80033da 80033a4: 2ba0 cmp r3, #160 @ 0xa0 80033a6: dc1b bgt.n 80033e0 80033a8: 2b80 cmp r3, #128 @ 0x80 80033aa: d013 beq.n 80033d4 80033ac: 2b80 cmp r3, #128 @ 0x80 80033ae: dc17 bgt.n 80033e0 80033b0: 2b60 cmp r3, #96 @ 0x60 80033b2: d00c beq.n 80033ce 80033b4: 2b60 cmp r3, #96 @ 0x60 80033b6: dc13 bgt.n 80033e0 80033b8: 2b20 cmp r3, #32 80033ba: d002 beq.n 80033c2 80033bc: 2b40 cmp r3, #64 @ 0x40 80033be: d003 beq.n 80033c8 80033c0: e00e b.n 80033e0 { case BMM350_OTP_STATUS_BOOT_ERR: rslt = BMM350_E_OTP_BOOT; 80033c2: 23f7 movs r3, #247 @ 0xf7 80033c4: 75fb strb r3, [r7, #23] break; 80033c6: e00e b.n 80033e6 case BMM350_OTP_STATUS_PAGE_RD_ERR: rslt = BMM350_E_OTP_PAGE_RD; 80033c8: 23f6 movs r3, #246 @ 0xf6 80033ca: 75fb strb r3, [r7, #23] break; 80033cc: e00b b.n 80033e6 case BMM350_OTP_STATUS_PAGE_PRG_ERR: rslt = BMM350_E_OTP_PAGE_PRG; 80033ce: 23f5 movs r3, #245 @ 0xf5 80033d0: 75fb strb r3, [r7, #23] break; 80033d2: e008 b.n 80033e6 case BMM350_OTP_STATUS_SIGN_ERR: rslt = BMM350_E_OTP_SIGN; 80033d4: 23f4 movs r3, #244 @ 0xf4 80033d6: 75fb strb r3, [r7, #23] break; 80033d8: e005 b.n 80033e6 case BMM350_OTP_STATUS_INV_CMD_ERR: rslt = BMM350_E_OTP_INV_CMD; 80033da: 23f3 movs r3, #243 @ 0xf3 80033dc: 75fb strb r3, [r7, #23] break; 80033de: e002 b.n 80033e6 default: rslt = BMM350_E_OTP_UNDEFINED; 80033e0: 23f2 movs r3, #242 @ 0xf2 80033e2: 75fb strb r3, [r7, #23] break; 80033e4: bf00 nop } } } if (rslt == BMM350_OK) 80033e6: f997 3017 ldrsb.w r3, [r7, #23] 80033ea: 2b00 cmp r3, #0 80033ec: d120 bne.n 8003430 { /* Get OTP MSB data */ rslt = bmm350_get_regs(BMM350_REG_OTP_DATA_MSB_REG, &msb, 1, dev); 80033ee: f107 0112 add.w r1, r7, #18 80033f2: 687b ldr r3, [r7, #4] 80033f4: 2201 movs r2, #1 80033f6: 2052 movs r0, #82 @ 0x52 80033f8: f7ff fa2e bl 8002858 80033fc: 4603 mov r3, r0 80033fe: 75fb strb r3, [r7, #23] if (rslt == BMM350_OK) 8003400: f997 3017 ldrsb.w r3, [r7, #23] 8003404: 2b00 cmp r3, #0 8003406: d113 bne.n 8003430 { /* Get OTP LSB data */ rslt = bmm350_get_regs(BMM350_REG_OTP_DATA_LSB_REG, &lsb, 1, dev); 8003408: f107 0113 add.w r1, r7, #19 800340c: 687b ldr r3, [r7, #4] 800340e: 2201 movs r2, #1 8003410: 2053 movs r0, #83 @ 0x53 8003412: f7ff fa21 bl 8002858 8003416: 4603 mov r3, r0 8003418: 75fb strb r3, [r7, #23] *lsb_msb = ((uint16_t)(msb << 8) | lsb) & 0xFFFF; 800341a: 7cbb ldrb r3, [r7, #18] 800341c: 021b lsls r3, r3, #8 800341e: b29b uxth r3, r3 8003420: 7cfa ldrb r2, [r7, #19] 8003422: 4313 orrs r3, r2 8003424: b29a uxth r2, r3 8003426: 68bb ldr r3, [r7, #8] 8003428: 801a strh r2, [r3, #0] 800342a: e001 b.n 8003430 } } } else { rslt = BMM350_E_NULL_PTR; 800342c: 23ff movs r3, #255 @ 0xff 800342e: 75fb strb r3, [r7, #23] } return rslt; 8003430: f997 3017 ldrsb.w r3, [r7, #23] } 8003434: 4618 mov r0, r3 8003436: 3718 adds r7, #24 8003438: 46bd mov sp, r7 800343a: bd80 pop {r7, pc} 0800343c : /*! * @brief This internal API is used to update magnetometer offset and sensitivity data. */ static void update_mag_off_sens(struct bmm350_dev *dev) { 800343c: b580 push {r7, lr} 800343e: b088 sub sp, #32 8003440: af00 add r7, sp, #0 8003442: 6078 str r0, [r7, #4] uint16_t off_x_lsb_msb, off_y_lsb_msb, off_z_lsb_msb, t_off = 0; 8003444: 2300 movs r3, #0 8003446: 83fb strh r3, [r7, #30] uint8_t sens_x, sens_y, sens_z, t_sens = 0; 8003448: 2300 movs r3, #0 800344a: 777b strb r3, [r7, #29] uint8_t tco_x, tco_y, tco_z = 0; 800344c: 2300 movs r3, #0 800344e: 773b strb r3, [r7, #28] uint8_t tcs_x, tcs_y, tcs_z = 0; 8003450: 2300 movs r3, #0 8003452: 76fb strb r3, [r7, #27] uint8_t cross_x_y, cross_y_x, cross_z_x, cross_z_y = 0; 8003454: 2300 movs r3, #0 8003456: 76bb strb r3, [r7, #26] off_x_lsb_msb = dev->otp_data[BMM350_MAG_OFFSET_X] & 0x0FFF; 8003458: 687b ldr r3, [r7, #4] 800345a: f8b3 3080 ldrh.w r3, [r3, #128] @ 0x80 800345e: f3c3 030b ubfx r3, r3, #0, #12 8003462: 833b strh r3, [r7, #24] off_y_lsb_msb = ((dev->otp_data[BMM350_MAG_OFFSET_X] & 0xF000) >> 4) + 8003464: 687b ldr r3, [r7, #4] 8003466: f8b3 3080 ldrh.w r3, [r3, #128] @ 0x80 800346a: 111b asrs r3, r3, #4 800346c: b21b sxth r3, r3 800346e: f403 6370 and.w r3, r3, #3840 @ 0xf00 8003472: b21a sxth r2, r3 (dev->otp_data[BMM350_MAG_OFFSET_Y] & BMM350_LSB_MASK); 8003474: 687b ldr r3, [r7, #4] 8003476: f8b3 3082 ldrh.w r3, [r3, #130] @ 0x82 800347a: b21b sxth r3, r3 800347c: b2db uxtb r3, r3 800347e: b21b sxth r3, r3 off_y_lsb_msb = ((dev->otp_data[BMM350_MAG_OFFSET_X] & 0xF000) >> 4) + 8003480: 4313 orrs r3, r2 8003482: b21b sxth r3, r3 8003484: 82fb strh r3, [r7, #22] off_z_lsb_msb = (dev->otp_data[BMM350_MAG_OFFSET_Y] & 0x0F00) + 8003486: 687b ldr r3, [r7, #4] 8003488: f8b3 3082 ldrh.w r3, [r3, #130] @ 0x82 800348c: b21b sxth r3, r3 800348e: f403 6370 and.w r3, r3, #3840 @ 0xf00 8003492: b21a sxth r2, r3 (dev->otp_data[BMM350_MAG_OFFSET_Z] & BMM350_LSB_MASK); 8003494: 687b ldr r3, [r7, #4] 8003496: f8b3 3084 ldrh.w r3, [r3, #132] @ 0x84 800349a: b21b sxth r3, r3 800349c: b2db uxtb r3, r3 800349e: b21b sxth r3, r3 off_z_lsb_msb = (dev->otp_data[BMM350_MAG_OFFSET_Y] & 0x0F00) + 80034a0: 4313 orrs r3, r2 80034a2: b21b sxth r3, r3 80034a4: 82bb strh r3, [r7, #20] t_off = dev->otp_data[BMM350_TEMP_OFF_SENS] & BMM350_LSB_MASK; 80034a6: 687b ldr r3, [r7, #4] 80034a8: f8b3 307e ldrh.w r3, [r3, #126] @ 0x7e 80034ac: b2db uxtb r3, r3 80034ae: 83fb strh r3, [r7, #30] dev->mag_comp.dut_offset_coef.offset_z = f16_from_int(fix_sign(off_z_lsb_msb, BMM350_SIGNED_12_BIT)); dev->mag_comp.dut_offset_coef.t_offs = fixed_mul_A48_16(f16_from_int(fix_sign(t_off, BMM350_SIGNED_8_BIT)), A48_16_0_2); #else dev->mag_comp.dut_offset_coef.offset_x = fix_sign(off_x_lsb_msb, BMM350_SIGNED_12_BIT); 80034b0: 8b3b ldrh r3, [r7, #24] 80034b2: 210c movs r1, #12 80034b4: 4618 mov r0, r3 80034b6: f7ff fec5 bl 8003244 80034ba: ee07 0a90 vmov s15, r0 80034be: eef8 7ae7 vcvt.f32.s32 s15, s15 80034c2: 687b ldr r3, [r7, #4] 80034c4: edc3 7a07 vstr s15, [r3, #28] dev->mag_comp.dut_offset_coef.offset_y = fix_sign(off_y_lsb_msb, BMM350_SIGNED_12_BIT); 80034c8: 8afb ldrh r3, [r7, #22] 80034ca: 210c movs r1, #12 80034cc: 4618 mov r0, r3 80034ce: f7ff feb9 bl 8003244 80034d2: ee07 0a90 vmov s15, r0 80034d6: eef8 7ae7 vcvt.f32.s32 s15, s15 80034da: 687b ldr r3, [r7, #4] 80034dc: edc3 7a08 vstr s15, [r3, #32] dev->mag_comp.dut_offset_coef.offset_z = fix_sign(off_z_lsb_msb, BMM350_SIGNED_12_BIT); 80034e0: 8abb ldrh r3, [r7, #20] 80034e2: 210c movs r1, #12 80034e4: 4618 mov r0, r3 80034e6: f7ff fead bl 8003244 80034ea: ee07 0a90 vmov s15, r0 80034ee: eef8 7ae7 vcvt.f32.s32 s15, s15 80034f2: 687b ldr r3, [r7, #4] 80034f4: edc3 7a09 vstr s15, [r3, #36] @ 0x24 dev->mag_comp.dut_offset_coef.t_offs = fix_sign(t_off, BMM350_SIGNED_8_BIT) / 5.0f; 80034f8: 8bfb ldrh r3, [r7, #30] 80034fa: 2108 movs r1, #8 80034fc: 4618 mov r0, r3 80034fe: f7ff fea1 bl 8003244 8003502: ee07 0a90 vmov s15, r0 8003506: eeb8 7ae7 vcvt.f32.s32 s14, s15 800350a: eef1 6a04 vmov.f32 s13, #20 @ 0x40a00000 5.0 800350e: eec7 7a26 vdiv.f32 s15, s14, s13 8003512: 687b ldr r3, [r7, #4] 8003514: edc3 7a06 vstr s15, [r3, #24] #endif sens_x = (dev->otp_data[BMM350_MAG_SENS_X] & BMM350_MSB_MASK) >> 8; 8003518: 687b ldr r3, [r7, #4] 800351a: f8b3 3084 ldrh.w r3, [r3, #132] @ 0x84 800351e: 0a1b lsrs r3, r3, #8 8003520: b29b uxth r3, r3 8003522: 74fb strb r3, [r7, #19] sens_y = (dev->otp_data[BMM350_MAG_SENS_Y] & BMM350_LSB_MASK); 8003524: 687b ldr r3, [r7, #4] 8003526: f8b3 3086 ldrh.w r3, [r3, #134] @ 0x86 800352a: 74bb strb r3, [r7, #18] sens_z = (dev->otp_data[BMM350_MAG_SENS_Z] & BMM350_MSB_MASK) >> 8; 800352c: 687b ldr r3, [r7, #4] 800352e: f8b3 3086 ldrh.w r3, [r3, #134] @ 0x86 8003532: 0a1b lsrs r3, r3, #8 8003534: b29b uxth r3, r3 8003536: 747b strb r3, [r7, #17] t_sens = (dev->otp_data[BMM350_TEMP_OFF_SENS] & BMM350_MSB_MASK) >> 8; 8003538: 687b ldr r3, [r7, #4] 800353a: f8b3 307e ldrh.w r3, [r3, #126] @ 0x7e 800353e: 0a1b lsrs r3, r3, #8 8003540: b29b uxth r3, r3 8003542: 777b strb r3, [r7, #29] A48_16_0_00390625); dev->mag_comp.dut_sensit_coef.t_sens = fixed_mul_A48_16(f16_from_int(fix_sign(t_sens, BMM350_SIGNED_8_BIT)), A48_16_0_001953125); #else dev->mag_comp.dut_sensit_coef.sens_x = fix_sign(sens_x, BMM350_SIGNED_8_BIT) / 256.0f; 8003544: 7cfb ldrb r3, [r7, #19] 8003546: 2108 movs r1, #8 8003548: 4618 mov r0, r3 800354a: f7ff fe7b bl 8003244 800354e: ee07 0a90 vmov s15, r0 8003552: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003556: eddf 6a91 vldr s13, [pc, #580] @ 800379c 800355a: eec7 7a26 vdiv.f32 s15, s14, s13 800355e: 687b ldr r3, [r7, #4] 8003560: edc3 7a0b vstr s15, [r3, #44] @ 0x2c dev->mag_comp.dut_sensit_coef.sens_y = fix_sign(sens_y, BMM350_SIGNED_8_BIT) / 256.0f; 8003564: 7cbb ldrb r3, [r7, #18] 8003566: 2108 movs r1, #8 8003568: 4618 mov r0, r3 800356a: f7ff fe6b bl 8003244 800356e: ee07 0a90 vmov s15, r0 8003572: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003576: eddf 6a89 vldr s13, [pc, #548] @ 800379c 800357a: eec7 7a26 vdiv.f32 s15, s14, s13 800357e: 687b ldr r3, [r7, #4] 8003580: edc3 7a0c vstr s15, [r3, #48] @ 0x30 dev->mag_comp.dut_sensit_coef.sens_z = fix_sign(sens_z, BMM350_SIGNED_8_BIT) / 256.0f; 8003584: 7c7b ldrb r3, [r7, #17] 8003586: 2108 movs r1, #8 8003588: 4618 mov r0, r3 800358a: f7ff fe5b bl 8003244 800358e: ee07 0a90 vmov s15, r0 8003592: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003596: eddf 6a81 vldr s13, [pc, #516] @ 800379c 800359a: eec7 7a26 vdiv.f32 s15, s14, s13 800359e: 687b ldr r3, [r7, #4] 80035a0: edc3 7a0d vstr s15, [r3, #52] @ 0x34 dev->mag_comp.dut_sensit_coef.t_sens = fix_sign(t_sens, BMM350_SIGNED_8_BIT) / 512.0f; 80035a4: 7f7b ldrb r3, [r7, #29] 80035a6: 2108 movs r1, #8 80035a8: 4618 mov r0, r3 80035aa: f7ff fe4b bl 8003244 80035ae: ee07 0a90 vmov s15, r0 80035b2: eeb8 7ae7 vcvt.f32.s32 s14, s15 80035b6: eddf 6a7a vldr s13, [pc, #488] @ 80037a0 80035ba: eec7 7a26 vdiv.f32 s15, s14, s13 80035be: 687b ldr r3, [r7, #4] 80035c0: edc3 7a0a vstr s15, [r3, #40] @ 0x28 #endif tco_x = (dev->otp_data[BMM350_MAG_TCO_X] & BMM350_LSB_MASK); 80035c4: 687b ldr r3, [r7, #4] 80035c6: f8b3 3088 ldrh.w r3, [r3, #136] @ 0x88 80035ca: 743b strb r3, [r7, #16] tco_y = (dev->otp_data[BMM350_MAG_TCO_Y] & BMM350_LSB_MASK); 80035cc: 687b ldr r3, [r7, #4] 80035ce: f8b3 308a ldrh.w r3, [r3, #138] @ 0x8a 80035d2: 73fb strb r3, [r7, #15] tco_z = (dev->otp_data[BMM350_MAG_TCO_Z] & BMM350_LSB_MASK); 80035d4: 687b ldr r3, [r7, #4] 80035d6: f8b3 308c ldrh.w r3, [r3, #140] @ 0x8c 80035da: 773b strb r3, [r7, #28] dev->mag_comp.dut_tco.tco_x = fixed_mul_A48_16(f16_from_int(fix_sign(tco_x, BMM350_SIGNED_8_BIT)), A48_16_0_03125); dev->mag_comp.dut_tco.tco_y = fixed_mul_A48_16(f16_from_int(fix_sign(tco_y, BMM350_SIGNED_8_BIT)), A48_16_0_03125); dev->mag_comp.dut_tco.tco_z = fixed_mul_A48_16(f16_from_int(fix_sign(tco_z, BMM350_SIGNED_8_BIT)), A48_16_0_03125); #else dev->mag_comp.dut_tco.tco_x = fix_sign(tco_x, BMM350_SIGNED_8_BIT) / 32.0f; 80035dc: 7c3b ldrb r3, [r7, #16] 80035de: 2108 movs r1, #8 80035e0: 4618 mov r0, r3 80035e2: f7ff fe2f bl 8003244 80035e6: ee07 0a90 vmov s15, r0 80035ea: eeb8 7ae7 vcvt.f32.s32 s14, s15 80035ee: eddf 6a6d vldr s13, [pc, #436] @ 80037a4 80035f2: eec7 7a26 vdiv.f32 s15, s14, s13 80035f6: 687b ldr r3, [r7, #4] 80035f8: edc3 7a0e vstr s15, [r3, #56] @ 0x38 dev->mag_comp.dut_tco.tco_y = fix_sign(tco_y, BMM350_SIGNED_8_BIT) / 32.0f; 80035fc: 7bfb ldrb r3, [r7, #15] 80035fe: 2108 movs r1, #8 8003600: 4618 mov r0, r3 8003602: f7ff fe1f bl 8003244 8003606: ee07 0a90 vmov s15, r0 800360a: eeb8 7ae7 vcvt.f32.s32 s14, s15 800360e: eddf 6a65 vldr s13, [pc, #404] @ 80037a4 8003612: eec7 7a26 vdiv.f32 s15, s14, s13 8003616: 687b ldr r3, [r7, #4] 8003618: edc3 7a0f vstr s15, [r3, #60] @ 0x3c dev->mag_comp.dut_tco.tco_z = fix_sign(tco_z, BMM350_SIGNED_8_BIT) / 32.0f; 800361c: 7f3b ldrb r3, [r7, #28] 800361e: 2108 movs r1, #8 8003620: 4618 mov r0, r3 8003622: f7ff fe0f bl 8003244 8003626: ee07 0a90 vmov s15, r0 800362a: eeb8 7ae7 vcvt.f32.s32 s14, s15 800362e: eddf 6a5d vldr s13, [pc, #372] @ 80037a4 8003632: eec7 7a26 vdiv.f32 s15, s14, s13 8003636: 687b ldr r3, [r7, #4] 8003638: edc3 7a10 vstr s15, [r3, #64] @ 0x40 #endif tcs_x = (dev->otp_data[BMM350_MAG_TCS_X] & BMM350_MSB_MASK) >> 8; 800363c: 687b ldr r3, [r7, #4] 800363e: f8b3 3088 ldrh.w r3, [r3, #136] @ 0x88 8003642: 0a1b lsrs r3, r3, #8 8003644: b29b uxth r3, r3 8003646: 73bb strb r3, [r7, #14] tcs_y = (dev->otp_data[BMM350_MAG_TCS_Y] & BMM350_MSB_MASK) >> 8; 8003648: 687b ldr r3, [r7, #4] 800364a: f8b3 308a ldrh.w r3, [r3, #138] @ 0x8a 800364e: 0a1b lsrs r3, r3, #8 8003650: b29b uxth r3, r3 8003652: 737b strb r3, [r7, #13] tcs_z = (dev->otp_data[BMM350_MAG_TCS_Z] & BMM350_MSB_MASK) >> 8; 8003654: 687b ldr r3, [r7, #4] 8003656: f8b3 308c ldrh.w r3, [r3, #140] @ 0x8c 800365a: 0a1b lsrs r3, r3, #8 800365c: b29b uxth r3, r3 800365e: 76fb strb r3, [r7, #27] A48_16_0_00006103515625); dev->mag_comp.dut_tcs.tcs_z = fixed_mul_A48_16(f16_from_int(fix_sign(tcs_z, BMM350_SIGNED_8_BIT)), A48_16_0_00006103515625); #else dev->mag_comp.dut_tcs.tcs_x = fix_sign(tcs_x, BMM350_SIGNED_8_BIT) / 16384.0f; 8003660: 7bbb ldrb r3, [r7, #14] 8003662: 2108 movs r1, #8 8003664: 4618 mov r0, r3 8003666: f7ff fded bl 8003244 800366a: ee07 0a90 vmov s15, r0 800366e: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003672: eddf 6a4d vldr s13, [pc, #308] @ 80037a8 8003676: eec7 7a26 vdiv.f32 s15, s14, s13 800367a: 687b ldr r3, [r7, #4] 800367c: edc3 7a11 vstr s15, [r3, #68] @ 0x44 dev->mag_comp.dut_tcs.tcs_y = fix_sign(tcs_y, BMM350_SIGNED_8_BIT) / 16384.0f; 8003680: 7b7b ldrb r3, [r7, #13] 8003682: 2108 movs r1, #8 8003684: 4618 mov r0, r3 8003686: f7ff fddd bl 8003244 800368a: ee07 0a90 vmov s15, r0 800368e: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003692: eddf 6a45 vldr s13, [pc, #276] @ 80037a8 8003696: eec7 7a26 vdiv.f32 s15, s14, s13 800369a: 687b ldr r3, [r7, #4] 800369c: edc3 7a12 vstr s15, [r3, #72] @ 0x48 dev->mag_comp.dut_tcs.tcs_z = fix_sign(tcs_z, BMM350_SIGNED_8_BIT) / 16384.0f; 80036a0: 7efb ldrb r3, [r7, #27] 80036a2: 2108 movs r1, #8 80036a4: 4618 mov r0, r3 80036a6: f7ff fdcd bl 8003244 80036aa: ee07 0a90 vmov s15, r0 80036ae: eeb8 7ae7 vcvt.f32.s32 s14, s15 80036b2: eddf 6a3d vldr s13, [pc, #244] @ 80037a8 80036b6: eec7 7a26 vdiv.f32 s15, s14, s13 80036ba: 687b ldr r3, [r7, #4] 80036bc: edc3 7a13 vstr s15, [r3, #76] @ 0x4c dev->mag_comp.dut_t0 = fixed_add(fixed_mul_A48_16(f16_from_int(fix_sign(dev->otp_data[BMM350_MAG_DUT_T_0], BMM350_SIGNED_16_BIT)), A48_16_0_001953125), f16_from_int(23)); #else dev->mag_comp.dut_t0 = (fix_sign(dev->otp_data[BMM350_MAG_DUT_T_0], BMM350_SIGNED_16_BIT) / 512.0f) + 23.0f; 80036c0: 687b ldr r3, [r7, #4] 80036c2: f8b3 3094 ldrh.w r3, [r3, #148] @ 0x94 80036c6: 2110 movs r1, #16 80036c8: 4618 mov r0, r3 80036ca: f7ff fdbb bl 8003244 80036ce: ee07 0a90 vmov s15, r0 80036d2: eeb8 7ae7 vcvt.f32.s32 s14, s15 80036d6: eddf 6a32 vldr s13, [pc, #200] @ 80037a0 80036da: eec7 7a26 vdiv.f32 s15, s14, s13 80036de: eeb3 7a07 vmov.f32 s14, #55 @ 0x41b80000 23.0 80036e2: ee77 7a87 vadd.f32 s15, s15, s14 80036e6: 687b ldr r3, [r7, #4] 80036e8: edc3 7a14 vstr s15, [r3, #80] @ 0x50 #endif cross_x_y = (dev->otp_data[BMM350_CROSS_X_Y] & BMM350_LSB_MASK); 80036ec: 687b ldr r3, [r7, #4] 80036ee: f8b3 308e ldrh.w r3, [r3, #142] @ 0x8e 80036f2: 733b strb r3, [r7, #12] cross_y_x = (dev->otp_data[BMM350_CROSS_Y_X] & BMM350_MSB_MASK) >> 8; 80036f4: 687b ldr r3, [r7, #4] 80036f6: f8b3 308e ldrh.w r3, [r3, #142] @ 0x8e 80036fa: 0a1b lsrs r3, r3, #8 80036fc: b29b uxth r3, r3 80036fe: 72fb strb r3, [r7, #11] cross_z_x = (dev->otp_data[BMM350_CROSS_Z_X] & BMM350_LSB_MASK); 8003700: 687b ldr r3, [r7, #4] 8003702: f8b3 3090 ldrh.w r3, [r3, #144] @ 0x90 8003706: 72bb strb r3, [r7, #10] cross_z_y = (dev->otp_data[BMM350_CROSS_Z_Y] & BMM350_MSB_MASK) >> 8; 8003708: 687b ldr r3, [r7, #4] 800370a: f8b3 3090 ldrh.w r3, [r3, #144] @ 0x90 800370e: 0a1b lsrs r3, r3, #8 8003710: b29b uxth r3, r3 8003712: 76bb strb r3, [r7, #26] A48_16_0_00125); dev->mag_comp.cross_axis.cross_z_y = fixed_mul_A48_16(f16_from_int(fix_sign(cross_z_y, BMM350_SIGNED_8_BIT)), A48_16_0_00125); #else dev->mag_comp.cross_axis.cross_x_y = fix_sign(cross_x_y, BMM350_SIGNED_8_BIT) / 800.0f; 8003714: 7b3b ldrb r3, [r7, #12] 8003716: 2108 movs r1, #8 8003718: 4618 mov r0, r3 800371a: f7ff fd93 bl 8003244 800371e: ee07 0a90 vmov s15, r0 8003722: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003726: eddf 6a21 vldr s13, [pc, #132] @ 80037ac 800372a: eec7 7a26 vdiv.f32 s15, s14, s13 800372e: 687b ldr r3, [r7, #4] 8003730: edc3 7a15 vstr s15, [r3, #84] @ 0x54 dev->mag_comp.cross_axis.cross_y_x = fix_sign(cross_y_x, BMM350_SIGNED_8_BIT) / 800.0f; 8003734: 7afb ldrb r3, [r7, #11] 8003736: 2108 movs r1, #8 8003738: 4618 mov r0, r3 800373a: f7ff fd83 bl 8003244 800373e: ee07 0a90 vmov s15, r0 8003742: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003746: eddf 6a19 vldr s13, [pc, #100] @ 80037ac 800374a: eec7 7a26 vdiv.f32 s15, s14, s13 800374e: 687b ldr r3, [r7, #4] 8003750: edc3 7a16 vstr s15, [r3, #88] @ 0x58 dev->mag_comp.cross_axis.cross_z_x = fix_sign(cross_z_x, BMM350_SIGNED_8_BIT) / 800.0f; 8003754: 7abb ldrb r3, [r7, #10] 8003756: 2108 movs r1, #8 8003758: 4618 mov r0, r3 800375a: f7ff fd73 bl 8003244 800375e: ee07 0a90 vmov s15, r0 8003762: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003766: eddf 6a11 vldr s13, [pc, #68] @ 80037ac 800376a: eec7 7a26 vdiv.f32 s15, s14, s13 800376e: 687b ldr r3, [r7, #4] 8003770: edc3 7a17 vstr s15, [r3, #92] @ 0x5c dev->mag_comp.cross_axis.cross_z_y = fix_sign(cross_z_y, BMM350_SIGNED_8_BIT) / 800.0f; 8003774: 7ebb ldrb r3, [r7, #26] 8003776: 2108 movs r1, #8 8003778: 4618 mov r0, r3 800377a: f7ff fd63 bl 8003244 800377e: ee07 0a90 vmov s15, r0 8003782: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003786: eddf 6a09 vldr s13, [pc, #36] @ 80037ac 800378a: eec7 7a26 vdiv.f32 s15, s14, s13 800378e: 687b ldr r3, [r7, #4] 8003790: edc3 7a18 vstr s15, [r3, #96] @ 0x60 #endif } 8003794: bf00 nop 8003796: 3720 adds r7, #32 8003798: 46bd mov sp, r7 800379a: bd80 pop {r7, pc} 800379c: 43800000 .word 0x43800000 80037a0: 44000000 .word 0x44000000 80037a4: 42000000 .word 0x42000000 80037a8: 46800000 .word 0x46800000 80037ac: 44480000 .word 0x44480000 080037b0 : return rslt; } #else static int8_t read_out_raw_data(float *out_data, struct bmm350_dev *dev) { 80037b0: b590 push {r4, r7, lr} 80037b2: b08d sub sp, #52 @ 0x34 80037b4: af00 add r7, sp, #0 80037b6: 6078 str r0, [r7, #4] 80037b8: 6039 str r1, [r7, #0] int8_t rslt; /* Float variable to convert mag lsb to uT and temp lsb to degC */ float lsb_to_ut_degc[4]; struct bmm350_raw_mag_data raw_data = { 0 }; 80037ba: f107 030c add.w r3, r7, #12 80037be: 2200 movs r2, #0 80037c0: 601a str r2, [r3, #0] 80037c2: 605a str r2, [r3, #4] 80037c4: 609a str r2, [r3, #8] 80037c6: 60da str r2, [r3, #12] if (out_data != NULL) 80037c8: 687b ldr r3, [r7, #4] 80037ca: 2b00 cmp r3, #0 80037cc: d05b beq.n 8003886 { rslt = bmm350_read_uncomp_mag_temp_data(&raw_data, dev); 80037ce: f107 030c add.w r3, r7, #12 80037d2: 6839 ldr r1, [r7, #0] 80037d4: 4618 mov r0, r3 80037d6: f7ff fa0a bl 8002bee 80037da: 4603 mov r3, r0 80037dc: f887 302f strb.w r3, [r7, #47] @ 0x2f if (rslt == BMM350_OK) 80037e0: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 80037e4: 2b00 cmp r3, #0 80037e6: d151 bne.n 800388c { /* Convert mag lsb to uT and temp lsb to degC */ update_default_coefiecents(lsb_to_ut_degc); 80037e8: f107 031c add.w r3, r7, #28 80037ec: 4618 mov r0, r3 80037ee: f000 f857 bl 80038a0 out_data[0] = (float)raw_data.raw_xdata * lsb_to_ut_degc[0]; 80037f2: 68fb ldr r3, [r7, #12] 80037f4: ee07 3a90 vmov s15, r3 80037f8: eeb8 7ae7 vcvt.f32.s32 s14, s15 80037fc: edd7 7a07 vldr s15, [r7, #28] 8003800: ee67 7a27 vmul.f32 s15, s14, s15 8003804: 687b ldr r3, [r7, #4] 8003806: edc3 7a00 vstr s15, [r3] out_data[1] = (float)raw_data.raw_ydata * lsb_to_ut_degc[1]; 800380a: 693b ldr r3, [r7, #16] 800380c: ee07 3a90 vmov s15, r3 8003810: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003814: edd7 7a08 vldr s15, [r7, #32] 8003818: 687b ldr r3, [r7, #4] 800381a: 3304 adds r3, #4 800381c: ee67 7a27 vmul.f32 s15, s14, s15 8003820: edc3 7a00 vstr s15, [r3] out_data[2] = (float)raw_data.raw_zdata * lsb_to_ut_degc[2]; 8003824: 697b ldr r3, [r7, #20] 8003826: ee07 3a90 vmov s15, r3 800382a: eeb8 7ae7 vcvt.f32.s32 s14, s15 800382e: edd7 7a09 vldr s15, [r7, #36] @ 0x24 8003832: 687b ldr r3, [r7, #4] 8003834: 3308 adds r3, #8 8003836: ee67 7a27 vmul.f32 s15, s14, s15 800383a: edc3 7a00 vstr s15, [r3] out_data[3] = (float)raw_data.raw_data_t * lsb_to_ut_degc[3]; 800383e: 69bb ldr r3, [r7, #24] 8003840: ee07 3a90 vmov s15, r3 8003844: eeb8 7ae7 vcvt.f32.s32 s14, s15 8003848: edd7 7a0a vldr s15, [r7, #40] @ 0x28 800384c: 687b ldr r3, [r7, #4] 800384e: 330c adds r3, #12 8003850: ee67 7a27 vmul.f32 s15, s14, s15 8003854: edc3 7a00 vstr s15, [r3] out_data[3] = (float)(out_data[3] - (1 * 25.49)); 8003858: 687b ldr r3, [r7, #4] 800385a: 330c adds r3, #12 800385c: 681b ldr r3, [r3, #0] 800385e: 4618 mov r0, r3 8003860: f7fc fe4a bl 80004f8 <__aeabi_f2d> 8003864: a30c add r3, pc, #48 @ (adr r3, 8003898 ) 8003866: e9d3 2300 ldrd r2, r3, [r3] 800386a: f7fc fce5 bl 8000238 <__aeabi_dsub> 800386e: 4602 mov r2, r0 8003870: 460b mov r3, r1 8003872: 4610 mov r0, r2 8003874: 4619 mov r1, r3 8003876: 687b ldr r3, [r7, #4] 8003878: f103 040c add.w r4, r3, #12 800387c: f7fd f98c bl 8000b98 <__aeabi_d2f> 8003880: 4603 mov r3, r0 8003882: 6023 str r3, [r4, #0] 8003884: e002 b.n 800388c } } else { rslt = BMM350_E_NULL_PTR; 8003886: 23ff movs r3, #255 @ 0xff 8003888: f887 302f strb.w r3, [r7, #47] @ 0x2f } return rslt; 800388c: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f } 8003890: 4618 mov r0, r3 8003892: 3734 adds r7, #52 @ 0x34 8003894: 46bd mov sp, r7 8003896: bd90 pop {r4, r7, pc} 8003898: a3d70a3d .word 0xa3d70a3d 800389c: 40397d70 .word 0x40397d70 080038a0 : /*! * @brief This internal API is used to convert lsb to uT and degC. */ static void update_default_coefiecents(float *lsb_to_ut_degc) { 80038a0: b480 push {r7} 80038a2: b08b sub sp, #44 @ 0x2c 80038a4: af00 add r7, sp, #0 80038a6: 6078 str r0, [r7, #4] float bxy_sens, bz_sens, temp_sens, ina_xy_gain_trgt, ina_z_gain_trgt, adc_gain, lut_gain; float power; bxy_sens = 14.55f; 80038a8: 4b36 ldr r3, [pc, #216] @ (8003984 ) 80038aa: 627b str r3, [r7, #36] @ 0x24 bz_sens = 9.0f; 80038ac: 4b36 ldr r3, [pc, #216] @ (8003988 ) 80038ae: 623b str r3, [r7, #32] temp_sens = 0.00204f; 80038b0: 4b36 ldr r3, [pc, #216] @ (800398c ) 80038b2: 61fb str r3, [r7, #28] ina_xy_gain_trgt = 19.46f; 80038b4: 4b36 ldr r3, [pc, #216] @ (8003990 ) 80038b6: 61bb str r3, [r7, #24] ina_z_gain_trgt = 31.0; 80038b8: 4b36 ldr r3, [pc, #216] @ (8003994 ) 80038ba: 617b str r3, [r7, #20] adc_gain = 1 / 1.5f; 80038bc: 4b36 ldr r3, [pc, #216] @ (8003998 ) 80038be: 613b str r3, [r7, #16] lut_gain = 0.714607238769531f; 80038c0: 4b36 ldr r3, [pc, #216] @ (800399c ) 80038c2: 60fb str r3, [r7, #12] power = (float)(1000000.0 / 1048576.0); 80038c4: 4b36 ldr r3, [pc, #216] @ (80039a0 ) 80038c6: 60bb str r3, [r7, #8] lsb_to_ut_degc[0] = (power / (bxy_sens * ina_xy_gain_trgt * adc_gain * lut_gain)); 80038c8: ed97 7a09 vldr s14, [r7, #36] @ 0x24 80038cc: edd7 7a06 vldr s15, [r7, #24] 80038d0: ee27 7a27 vmul.f32 s14, s14, s15 80038d4: edd7 7a04 vldr s15, [r7, #16] 80038d8: ee27 7a27 vmul.f32 s14, s14, s15 80038dc: edd7 7a03 vldr s15, [r7, #12] 80038e0: ee27 7a27 vmul.f32 s14, s14, s15 80038e4: edd7 6a02 vldr s13, [r7, #8] 80038e8: eec6 7a87 vdiv.f32 s15, s13, s14 80038ec: 687b ldr r3, [r7, #4] 80038ee: edc3 7a00 vstr s15, [r3] lsb_to_ut_degc[1] = (power / (bxy_sens * ina_xy_gain_trgt * adc_gain * lut_gain)); 80038f2: ed97 7a09 vldr s14, [r7, #36] @ 0x24 80038f6: edd7 7a06 vldr s15, [r7, #24] 80038fa: ee27 7a27 vmul.f32 s14, s14, s15 80038fe: edd7 7a04 vldr s15, [r7, #16] 8003902: ee27 7a27 vmul.f32 s14, s14, s15 8003906: edd7 7a03 vldr s15, [r7, #12] 800390a: ee27 7a27 vmul.f32 s14, s14, s15 800390e: 687b ldr r3, [r7, #4] 8003910: 3304 adds r3, #4 8003912: edd7 6a02 vldr s13, [r7, #8] 8003916: eec6 7a87 vdiv.f32 s15, s13, s14 800391a: edc3 7a00 vstr s15, [r3] lsb_to_ut_degc[2] = (power / (bz_sens * ina_z_gain_trgt * adc_gain * lut_gain)); 800391e: ed97 7a08 vldr s14, [r7, #32] 8003922: edd7 7a05 vldr s15, [r7, #20] 8003926: ee27 7a27 vmul.f32 s14, s14, s15 800392a: edd7 7a04 vldr s15, [r7, #16] 800392e: ee27 7a27 vmul.f32 s14, s14, s15 8003932: edd7 7a03 vldr s15, [r7, #12] 8003936: ee27 7a27 vmul.f32 s14, s14, s15 800393a: 687b ldr r3, [r7, #4] 800393c: 3308 adds r3, #8 800393e: edd7 6a02 vldr s13, [r7, #8] 8003942: eec6 7a87 vdiv.f32 s15, s13, s14 8003946: edc3 7a00 vstr s15, [r3] lsb_to_ut_degc[3] = 1 / (temp_sens * adc_gain * lut_gain * 1048576); 800394a: ed97 7a07 vldr s14, [r7, #28] 800394e: edd7 7a04 vldr s15, [r7, #16] 8003952: ee27 7a27 vmul.f32 s14, s14, s15 8003956: edd7 7a03 vldr s15, [r7, #12] 800395a: ee67 7a27 vmul.f32 s15, s14, s15 800395e: ed9f 7a11 vldr s14, [pc, #68] @ 80039a4 8003962: ee27 7a87 vmul.f32 s14, s15, s14 8003966: 687b ldr r3, [r7, #4] 8003968: 330c adds r3, #12 800396a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800396e: eec6 7a87 vdiv.f32 s15, s13, s14 8003972: edc3 7a00 vstr s15, [r3] } 8003976: bf00 nop 8003978: 372c adds r7, #44 @ 0x2c 800397a: 46bd mov sp, r7 800397c: f85d 7b04 ldr.w r7, [sp], #4 8003980: 4770 bx lr 8003982: bf00 nop 8003984: 4168cccd .word 0x4168cccd 8003988: 41100000 .word 0x41100000 800398c: 3b05b185 .word 0x3b05b185 8003990: 419bae14 .word 0x419bae14 8003994: 41f80000 .word 0x41f80000 8003998: 3f2aaaab .word 0x3f2aaaab 800399c: 3f36f080 .word 0x3f36f080 80039a0: 3f742400 .word 0x3f742400 80039a4: 49800000 .word 0x49800000 080039a8 : /*! * @brief This internal API is used to read OTP data after boot in user mode. */ static int8_t otp_dump_after_boot(struct bmm350_dev *dev) { 80039a8: b580 push {r7, lr} 80039aa: b084 sub sp, #16 80039ac: af00 add r7, sp, #0 80039ae: 6078 str r0, [r7, #4] /* Variable to store the function result */ int8_t rslt; uint16_t otp_word = 0; 80039b0: 2300 movs r3, #0 80039b2: 81bb strh r3, [r7, #12] uint8_t indx; for (indx = 0; indx < BMM350_OTP_DATA_LENGTH; indx++) 80039b4: 2300 movs r3, #0 80039b6: 73bb strb r3, [r7, #14] 80039b8: e013 b.n 80039e2 { rslt = read_otp_word(indx, &otp_word, dev); 80039ba: f107 010c add.w r1, r7, #12 80039be: 7bbb ldrb r3, [r7, #14] 80039c0: 687a ldr r2, [r7, #4] 80039c2: 4618 mov r0, r3 80039c4: f7ff fc98 bl 80032f8 80039c8: 4603 mov r3, r0 80039ca: 73fb strb r3, [r7, #15] dev->otp_data[indx] = otp_word; 80039cc: 7bbb ldrb r3, [r7, #14] 80039ce: 89b9 ldrh r1, [r7, #12] 80039d0: 687a ldr r2, [r7, #4] 80039d2: 3330 adds r3, #48 @ 0x30 80039d4: 005b lsls r3, r3, #1 80039d6: 4413 add r3, r2 80039d8: 460a mov r2, r1 80039da: 809a strh r2, [r3, #4] for (indx = 0; indx < BMM350_OTP_DATA_LENGTH; indx++) 80039dc: 7bbb ldrb r3, [r7, #14] 80039de: 3301 adds r3, #1 80039e0: 73bb strb r3, [r7, #14] 80039e2: 7bbb ldrb r3, [r7, #14] 80039e4: 2b1f cmp r3, #31 80039e6: d9e8 bls.n 80039ba } dev->var_id = (dev->otp_data[30] & 0x7f00) >> 9; 80039e8: 687b ldr r3, [r7, #4] 80039ea: f8b3 30a0 ldrh.w r3, [r3, #160] @ 0xa0 80039ee: 125b asrs r3, r3, #9 80039f0: b2db uxtb r3, r3 80039f2: f003 033f and.w r3, r3, #63 @ 0x3f 80039f6: b2da uxtb r2, r3 80039f8: 687b ldr r3, [r7, #4] 80039fa: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 /* Set the default auto bit reset configuration */ dev->enable_auto_br = ((dev->var_id > BMM350_CURRENT_SHUTTLE_VARIANT_ID) ? BMM350_DISABLE : BMM350_ENABLE); 80039fe: 687b ldr r3, [r7, #4] 8003a00: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8003a04: 2b11 cmp r3, #17 8003a06: bf94 ite ls 8003a08: 2301 movls r3, #1 8003a0a: 2300 movhi r3, #0 8003a0c: b2db uxtb r3, r3 8003a0e: 461a mov r2, r3 8003a10: 687b ldr r3, [r7, #4] 8003a12: f883 20ad strb.w r2, [r3, #173] @ 0xad /* Update magnetometer offset and sensitivity data. */ update_mag_off_sens(dev); 8003a16: 6878 ldr r0, [r7, #4] 8003a18: f7ff fd10 bl 800343c return rslt; 8003a1c: f997 300f ldrsb.w r3, [r7, #15] } 8003a20: 4618 mov r0, r3 8003a22: 3710 adds r7, #16 8003a24: 46bd mov sp, r7 8003a26: bd80 pop {r7, pc} 08003a28 : /*! * @brief This internal API is used to switch from suspend mode to normal mode or forced mode. */ static int8_t set_powermode(enum bmm350_power_modes powermode, struct bmm350_dev *dev) { 8003a28: b590 push {r4, r7, lr} 8003a2a: b08f sub sp, #60 @ 0x3c 8003a2c: af00 add r7, sp, #0 8003a2e: 4603 mov r3, r0 8003a30: 6039 str r1, [r7, #0] 8003a32: 71fb strb r3, [r7, #7] /* Variable to store the function result */ int8_t rslt; uint8_t reg_data = powermode; 8003a34: 79fb ldrb r3, [r7, #7] 8003a36: f887 302f strb.w r3, [r7, #47] @ 0x2f uint8_t get_avg; /* Array to store suspend to forced mode delay */ uint32_t sus_to_forced_mode[4] = 8003a3a: 4b36 ldr r3, [pc, #216] @ (8003b14 ) 8003a3c: f107 041c add.w r4, r7, #28 8003a40: cb0f ldmia r3, {r0, r1, r2, r3} 8003a42: e884 000f stmia.w r4, {r0, r1, r2, r3} { BMM350_SUS_TO_FORCEDMODE_NO_AVG_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_2_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_4_DELAY, BMM350_SUS_TO_FORCEDMODE_AVG_8_DELAY }; /* Array to store suspend to forced mode fast delay */ uint32_t sus_to_forced_mode_fast[4] = 8003a46: 4b34 ldr r3, [pc, #208] @ (8003b18 ) 8003a48: f107 040c add.w r4, r7, #12 8003a4c: cb0f ldmia r3, {r0, r1, r2, r3} 8003a4e: e884 000f stmia.w r4, {r0, r1, r2, r3} { BMM350_SUS_TO_FORCEDMODE_FAST_NO_AVG_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_2_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_4_DELAY, BMM350_SUS_TO_FORCEDMODE_FAST_AVG_8_DELAY }; uint8_t avg = 0; 8003a52: 2300 movs r3, #0 8003a54: f887 3036 strb.w r3, [r7, #54] @ 0x36 uint32_t delay_us = 0; 8003a58: 2300 movs r3, #0 8003a5a: 633b str r3, [r7, #48] @ 0x30 rslt = null_ptr_check(dev); 8003a5c: 6838 ldr r0, [r7, #0] 8003a5e: f7ff fbd1 bl 8003204 8003a62: 4603 mov r3, r0 8003a64: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (rslt == BMM350_OK) 8003a68: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 8003a6c: 2b00 cmp r3, #0 8003a6e: d123 bne.n 8003ab8 { /* Set PMU command configuration to desired power mode */ rslt = bmm350_set_regs(BMM350_REG_PMU_CMD, ®_data, 1, dev); 8003a70: f107 012f add.w r1, r7, #47 @ 0x2f 8003a74: 683b ldr r3, [r7, #0] 8003a76: 2201 movs r2, #1 8003a78: 2006 movs r0, #6 8003a7a: f7fe feb9 bl 80027f0 8003a7e: 4603 mov r3, r0 8003a80: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (rslt == BMM350_OK) 8003a84: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 8003a88: 2b00 cmp r3, #0 8003a8a: d115 bne.n 8003ab8 { /* Get average configuration */ rslt = bmm350_get_regs(BMM350_REG_PMU_CMD_AGGR_SET, &get_avg, 1, dev); 8003a8c: f107 012e add.w r1, r7, #46 @ 0x2e 8003a90: 683b ldr r3, [r7, #0] 8003a92: 2201 movs r2, #1 8003a94: 2004 movs r0, #4 8003a96: f7fe fedf bl 8002858 8003a9a: 4603 mov r3, r0 8003a9c: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (rslt == BMM350_OK) 8003aa0: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 8003aa4: 2b00 cmp r3, #0 8003aa6: d107 bne.n 8003ab8 { /* Mask the average value */ avg = ((get_avg & BMM350_AVG_MSK) >> BMM350_AVG_POS); 8003aa8: f897 302e ldrb.w r3, [r7, #46] @ 0x2e 8003aac: 111b asrs r3, r3, #4 8003aae: b2db uxtb r3, r3 8003ab0: f003 0303 and.w r3, r3, #3 8003ab4: f887 3036 strb.w r3, [r7, #54] @ 0x36 } } } if (rslt == BMM350_OK) 8003ab8: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 8003abc: 2b00 cmp r3, #0 8003abe: d122 bne.n 8003b06 { /* Check if desired power mode is normal mode */ if (powermode == BMM350_NORMAL_MODE) 8003ac0: 79fb ldrb r3, [r7, #7] 8003ac2: 2b01 cmp r3, #1 8003ac4: d102 bne.n 8003acc { delay_us = BMM350_SUSPEND_TO_NORMAL_DELAY; 8003ac6: f249 4370 movw r3, #38000 @ 0x9470 8003aca: 633b str r3, [r7, #48] @ 0x30 } /* Check if desired power mode is forced mode */ if (powermode == BMM350_FORCED_MODE) 8003acc: 79fb ldrb r3, [r7, #7] 8003ace: 2b03 cmp r3, #3 8003ad0: d107 bne.n 8003ae2 { /* Store delay based on averaging mode */ delay_us = sus_to_forced_mode[avg]; 8003ad2: f897 3036 ldrb.w r3, [r7, #54] @ 0x36 8003ad6: 009b lsls r3, r3, #2 8003ad8: 3338 adds r3, #56 @ 0x38 8003ada: 443b add r3, r7 8003adc: f853 3c1c ldr.w r3, [r3, #-28] 8003ae0: 633b str r3, [r7, #48] @ 0x30 } /* Check if desired power mode is forced mode fast */ if (powermode == BMM350_FORCED_MODE_FAST) 8003ae2: 79fb ldrb r3, [r7, #7] 8003ae4: 2b04 cmp r3, #4 8003ae6: d107 bne.n 8003af8 { /* Store delay based on averaging mode */ delay_us = sus_to_forced_mode_fast[avg]; 8003ae8: f897 3036 ldrb.w r3, [r7, #54] @ 0x36 8003aec: 009b lsls r3, r3, #2 8003aee: 3338 adds r3, #56 @ 0x38 8003af0: 443b add r3, r7 8003af2: f853 3c2c ldr.w r3, [r3, #-44] 8003af6: 633b str r3, [r7, #48] @ 0x30 } /* Perform delay based on power mode */ rslt = bmm350_delay_us(delay_us, dev); 8003af8: 6839 ldr r1, [r7, #0] 8003afa: 6b38 ldr r0, [r7, #48] @ 0x30 8003afc: f7fe ff01 bl 8002902 8003b00: 4603 mov r3, r0 8003b02: f887 3037 strb.w r3, [r7, #55] @ 0x37 } return rslt; 8003b06: f997 3037 ldrsb.w r3, [r7, #55] @ 0x37 } 8003b0a: 4618 mov r0, r3 8003b0c: 373c adds r7, #60 @ 0x3c 8003b0e: 46bd mov sp, r7 8003b10: bd90 pop {r4, r7, pc} 8003b12: bf00 nop 8003b14: 0801de0c .word 0x0801de0c 8003b18: 0801de1c .word 0x0801de1c 08003b1c : { 8003b1c: b480 push {r7} 8003b1e: b083 sub sp, #12 8003b20: af00 add r7, sp, #0 8003b22: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR1, ExtiLine); 8003b24: 4b06 ldr r3, [pc, #24] @ (8003b40 ) 8003b26: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8003b2a: 4905 ldr r1, [pc, #20] @ (8003b40 ) 8003b2c: 687b ldr r3, [r7, #4] 8003b2e: 4313 orrs r3, r2 8003b30: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } 8003b34: bf00 nop 8003b36: 370c adds r7, #12 8003b38: 46bd mov sp, r7 8003b3a: f85d 7b04 ldr.w r7, [sp], #4 8003b3e: 4770 bx lr 8003b40: 58000800 .word 0x58000800 08003b44 : * @arg @ref LL_EXTI_LINE_31 (*) * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) { 8003b44: b480 push {r7} 8003b46: b083 sub sp, #12 8003b48: af00 add r7, sp, #0 8003b4a: 6078 str r0, [r7, #4] SET_BIT(EXTI->RTSR1, ExtiLine); 8003b4c: 4b05 ldr r3, [pc, #20] @ (8003b64 ) 8003b4e: 681a ldr r2, [r3, #0] 8003b50: 4904 ldr r1, [pc, #16] @ (8003b64 ) 8003b52: 687b ldr r3, [r7, #4] 8003b54: 4313 orrs r3, r2 8003b56: 600b str r3, [r1, #0] } 8003b58: bf00 nop 8003b5a: 370c adds r7, #12 8003b5c: 46bd mov sp, r7 8003b5e: f85d 7b04 ldr.w r7, [sp], #4 8003b62: 4770 bx lr 8003b64: 58000800 .word 0x58000800 08003b68 : * reliability of the value * @param None * @retval SSR value read */ static uint32_t ReadRtcSsrValue(void) { 8003b68: b480 push {r7} 8003b6a: b083 sub sp, #12 8003b6c: af00 add r7, sp, #0 uint32_t first_read; uint32_t second_read; first_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); 8003b6e: 4b0d ldr r3, [pc, #52] @ (8003ba4 ) 8003b70: 6a9b ldr r3, [r3, #40] @ 0x28 8003b72: b29b uxth r3, r3 8003b74: 607b str r3, [r7, #4] second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); 8003b76: 4b0b ldr r3, [pc, #44] @ (8003ba4 ) 8003b78: 6a9b ldr r3, [r3, #40] @ 0x28 8003b7a: b29b uxth r3, r3 8003b7c: 603b str r3, [r7, #0] while(first_read != second_read) 8003b7e: e005 b.n 8003b8c { first_read = second_read; 8003b80: 683b ldr r3, [r7, #0] 8003b82: 607b str r3, [r7, #4] second_read = (uint32_t)(READ_BIT(RTC->SSR, RTC_SSR_SS)); 8003b84: 4b07 ldr r3, [pc, #28] @ (8003ba4 ) 8003b86: 6a9b ldr r3, [r3, #40] @ 0x28 8003b88: b29b uxth r3, r3 8003b8a: 603b str r3, [r7, #0] while(first_read != second_read) 8003b8c: 687a ldr r2, [r7, #4] 8003b8e: 683b ldr r3, [r7, #0] 8003b90: 429a cmp r2, r3 8003b92: d1f5 bne.n 8003b80 } return second_read; 8003b94: 683b ldr r3, [r7, #0] } 8003b96: 4618 mov r0, r3 8003b98: 370c adds r7, #12 8003b9a: 46bd mov sp, r7 8003b9c: f85d 7b04 ldr.w r7, [sp], #4 8003ba0: 4770 bx lr 8003ba2: bf00 nop 8003ba4: 40002800 .word 0x40002800 08003ba8 : * @param TimerID: The ID of the Timer * @param RefTimerID: The ID of the Timer to be linked after * @retval None */ static void LinkTimerAfter(uint8_t TimerID, uint8_t RefTimerID) { 8003ba8: b480 push {r7} 8003baa: b085 sub sp, #20 8003bac: af00 add r7, sp, #0 8003bae: 4603 mov r3, r0 8003bb0: 460a mov r2, r1 8003bb2: 71fb strb r3, [r7, #7] 8003bb4: 4613 mov r3, r2 8003bb6: 71bb strb r3, [r7, #6] uint8_t next_id; next_id = aTimerContext[RefTimerID].NextID; 8003bb8: 79ba ldrb r2, [r7, #6] 8003bba: 491d ldr r1, [pc, #116] @ (8003c30 ) 8003bbc: 4613 mov r3, r2 8003bbe: 005b lsls r3, r3, #1 8003bc0: 4413 add r3, r2 8003bc2: 00db lsls r3, r3, #3 8003bc4: 440b add r3, r1 8003bc6: 3315 adds r3, #21 8003bc8: 781b ldrb r3, [r3, #0] 8003bca: 73fb strb r3, [r7, #15] if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8003bcc: 7bfb ldrb r3, [r7, #15] 8003bce: 2b06 cmp r3, #6 8003bd0: d009 beq.n 8003be6 { aTimerContext[next_id].PreviousID = TimerID; 8003bd2: 7bfa ldrb r2, [r7, #15] 8003bd4: 4916 ldr r1, [pc, #88] @ (8003c30 ) 8003bd6: 4613 mov r3, r2 8003bd8: 005b lsls r3, r3, #1 8003bda: 4413 add r3, r2 8003bdc: 00db lsls r3, r3, #3 8003bde: 440b add r3, r1 8003be0: 3314 adds r3, #20 8003be2: 79fa ldrb r2, [r7, #7] 8003be4: 701a strb r2, [r3, #0] } aTimerContext[TimerID].NextID = next_id; 8003be6: 79fa ldrb r2, [r7, #7] 8003be8: 4911 ldr r1, [pc, #68] @ (8003c30 ) 8003bea: 4613 mov r3, r2 8003bec: 005b lsls r3, r3, #1 8003bee: 4413 add r3, r2 8003bf0: 00db lsls r3, r3, #3 8003bf2: 440b add r3, r1 8003bf4: 3315 adds r3, #21 8003bf6: 7bfa ldrb r2, [r7, #15] 8003bf8: 701a strb r2, [r3, #0] aTimerContext[TimerID].PreviousID = RefTimerID ; 8003bfa: 79fa ldrb r2, [r7, #7] 8003bfc: 490c ldr r1, [pc, #48] @ (8003c30 ) 8003bfe: 4613 mov r3, r2 8003c00: 005b lsls r3, r3, #1 8003c02: 4413 add r3, r2 8003c04: 00db lsls r3, r3, #3 8003c06: 440b add r3, r1 8003c08: 3314 adds r3, #20 8003c0a: 79ba ldrb r2, [r7, #6] 8003c0c: 701a strb r2, [r3, #0] aTimerContext[RefTimerID].NextID = TimerID; 8003c0e: 79ba ldrb r2, [r7, #6] 8003c10: 4907 ldr r1, [pc, #28] @ (8003c30 ) 8003c12: 4613 mov r3, r2 8003c14: 005b lsls r3, r3, #1 8003c16: 4413 add r3, r2 8003c18: 00db lsls r3, r3, #3 8003c1a: 440b add r3, r1 8003c1c: 3315 adds r3, #21 8003c1e: 79fa ldrb r2, [r7, #7] 8003c20: 701a strb r2, [r3, #0] return; 8003c22: bf00 nop } 8003c24: 3714 adds r7, #20 8003c26: 46bd mov sp, r7 8003c28: f85d 7b04 ldr.w r7, [sp], #4 8003c2c: 4770 bx lr 8003c2e: bf00 nop 8003c30: 20000314 .word 0x20000314 08003c34 : * @param TimerID: The ID of the Timer * @param RefTimerID: The ID of the Timer to be linked before * @retval None */ static void LinkTimerBefore(uint8_t TimerID, uint8_t RefTimerID) { 8003c34: b480 push {r7} 8003c36: b085 sub sp, #20 8003c38: af00 add r7, sp, #0 8003c3a: 4603 mov r3, r0 8003c3c: 460a mov r2, r1 8003c3e: 71fb strb r3, [r7, #7] 8003c40: 4613 mov r3, r2 8003c42: 71bb strb r3, [r7, #6] uint8_t previous_id; if(RefTimerID != CurrentRunningTimerID) 8003c44: 4b29 ldr r3, [pc, #164] @ (8003cec ) 8003c46: 781b ldrb r3, [r3, #0] 8003c48: b2db uxtb r3, r3 8003c4a: 79ba ldrb r2, [r7, #6] 8003c4c: 429a cmp r2, r3 8003c4e: d032 beq.n 8003cb6 { previous_id = aTimerContext[RefTimerID].PreviousID; 8003c50: 79ba ldrb r2, [r7, #6] 8003c52: 4927 ldr r1, [pc, #156] @ (8003cf0 ) 8003c54: 4613 mov r3, r2 8003c56: 005b lsls r3, r3, #1 8003c58: 4413 add r3, r2 8003c5a: 00db lsls r3, r3, #3 8003c5c: 440b add r3, r1 8003c5e: 3314 adds r3, #20 8003c60: 781b ldrb r3, [r3, #0] 8003c62: 73fb strb r3, [r7, #15] aTimerContext[previous_id].NextID = TimerID; 8003c64: 7bfa ldrb r2, [r7, #15] 8003c66: 4922 ldr r1, [pc, #136] @ (8003cf0 ) 8003c68: 4613 mov r3, r2 8003c6a: 005b lsls r3, r3, #1 8003c6c: 4413 add r3, r2 8003c6e: 00db lsls r3, r3, #3 8003c70: 440b add r3, r1 8003c72: 3315 adds r3, #21 8003c74: 79fa ldrb r2, [r7, #7] 8003c76: 701a strb r2, [r3, #0] aTimerContext[TimerID].NextID = RefTimerID; 8003c78: 79fa ldrb r2, [r7, #7] 8003c7a: 491d ldr r1, [pc, #116] @ (8003cf0 ) 8003c7c: 4613 mov r3, r2 8003c7e: 005b lsls r3, r3, #1 8003c80: 4413 add r3, r2 8003c82: 00db lsls r3, r3, #3 8003c84: 440b add r3, r1 8003c86: 3315 adds r3, #21 8003c88: 79ba ldrb r2, [r7, #6] 8003c8a: 701a strb r2, [r3, #0] aTimerContext[TimerID].PreviousID = previous_id ; 8003c8c: 79fa ldrb r2, [r7, #7] 8003c8e: 4918 ldr r1, [pc, #96] @ (8003cf0 ) 8003c90: 4613 mov r3, r2 8003c92: 005b lsls r3, r3, #1 8003c94: 4413 add r3, r2 8003c96: 00db lsls r3, r3, #3 8003c98: 440b add r3, r1 8003c9a: 3314 adds r3, #20 8003c9c: 7bfa ldrb r2, [r7, #15] 8003c9e: 701a strb r2, [r3, #0] aTimerContext[RefTimerID].PreviousID = TimerID; 8003ca0: 79ba ldrb r2, [r7, #6] 8003ca2: 4913 ldr r1, [pc, #76] @ (8003cf0 ) 8003ca4: 4613 mov r3, r2 8003ca6: 005b lsls r3, r3, #1 8003ca8: 4413 add r3, r2 8003caa: 00db lsls r3, r3, #3 8003cac: 440b add r3, r1 8003cae: 3314 adds r3, #20 8003cb0: 79fa ldrb r2, [r7, #7] 8003cb2: 701a strb r2, [r3, #0] { aTimerContext[TimerID].NextID = RefTimerID; aTimerContext[RefTimerID].PreviousID = TimerID; } return; 8003cb4: e014 b.n 8003ce0 aTimerContext[TimerID].NextID = RefTimerID; 8003cb6: 79fa ldrb r2, [r7, #7] 8003cb8: 490d ldr r1, [pc, #52] @ (8003cf0 ) 8003cba: 4613 mov r3, r2 8003cbc: 005b lsls r3, r3, #1 8003cbe: 4413 add r3, r2 8003cc0: 00db lsls r3, r3, #3 8003cc2: 440b add r3, r1 8003cc4: 3315 adds r3, #21 8003cc6: 79ba ldrb r2, [r7, #6] 8003cc8: 701a strb r2, [r3, #0] aTimerContext[RefTimerID].PreviousID = TimerID; 8003cca: 79ba ldrb r2, [r7, #6] 8003ccc: 4908 ldr r1, [pc, #32] @ (8003cf0 ) 8003cce: 4613 mov r3, r2 8003cd0: 005b lsls r3, r3, #1 8003cd2: 4413 add r3, r2 8003cd4: 00db lsls r3, r3, #3 8003cd6: 440b add r3, r1 8003cd8: 3314 adds r3, #20 8003cda: 79fa ldrb r2, [r7, #7] 8003cdc: 701a strb r2, [r3, #0] return; 8003cde: bf00 nop } 8003ce0: 3714 adds r7, #20 8003ce2: 46bd mov sp, r7 8003ce4: f85d 7b04 ldr.w r7, [sp], #4 8003ce8: 4770 bx lr 8003cea: bf00 nop 8003cec: 200003a4 .word 0x200003a4 8003cf0: 20000314 .word 0x20000314 08003cf4 : * @brief Insert a Timer in the list * @param TimerID: The ID of the Timer * @retval None */ static uint16_t linkTimer(uint8_t TimerID) { 8003cf4: b580 push {r7, lr} 8003cf6: b084 sub sp, #16 8003cf8: af00 add r7, sp, #0 8003cfa: 4603 mov r3, r0 8003cfc: 71fb strb r3, [r7, #7] uint32_t time_left; uint16_t time_elapsed; uint8_t timer_id_lookup; uint8_t next_id; if(CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8003cfe: 4b4e ldr r3, [pc, #312] @ (8003e38 ) 8003d00: 781b ldrb r3, [r3, #0] 8003d02: b2db uxtb r3, r3 8003d04: 2b06 cmp r3, #6 8003d06: d118 bne.n 8003d3a { /** * No timer in the list */ PreviousRunningTimerID = CurrentRunningTimerID; 8003d08: 4b4b ldr r3, [pc, #300] @ (8003e38 ) 8003d0a: 781b ldrb r3, [r3, #0] 8003d0c: b2da uxtb r2, r3 8003d0e: 4b4b ldr r3, [pc, #300] @ (8003e3c ) 8003d10: 701a strb r2, [r3, #0] CurrentRunningTimerID = TimerID; 8003d12: 4a49 ldr r2, [pc, #292] @ (8003e38 ) 8003d14: 79fb ldrb r3, [r7, #7] 8003d16: 7013 strb r3, [r2, #0] aTimerContext[TimerID].NextID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; 8003d18: 79fa ldrb r2, [r7, #7] 8003d1a: 4949 ldr r1, [pc, #292] @ (8003e40 ) 8003d1c: 4613 mov r3, r2 8003d1e: 005b lsls r3, r3, #1 8003d20: 4413 add r3, r2 8003d22: 00db lsls r3, r3, #3 8003d24: 440b add r3, r1 8003d26: 3315 adds r3, #21 8003d28: 2206 movs r2, #6 8003d2a: 701a strb r2, [r3, #0] SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; 8003d2c: 4b45 ldr r3, [pc, #276] @ (8003e44 ) 8003d2e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8003d32: 601a str r2, [r3, #0] time_elapsed = 0; 8003d34: 2300 movs r3, #0 8003d36: 81fb strh r3, [r7, #14] 8003d38: e078 b.n 8003e2c } else { time_elapsed = ReturnTimeElapsed(); 8003d3a: f000 f909 bl 8003f50 8003d3e: 4603 mov r3, r0 8003d40: 81fb strh r3, [r7, #14] /** * update count of the timer to be linked */ aTimerContext[TimerID].CountLeft += time_elapsed; 8003d42: 79fa ldrb r2, [r7, #7] 8003d44: 493e ldr r1, [pc, #248] @ (8003e40 ) 8003d46: 4613 mov r3, r2 8003d48: 005b lsls r3, r3, #1 8003d4a: 4413 add r3, r2 8003d4c: 00db lsls r3, r3, #3 8003d4e: 440b add r3, r1 8003d50: 3308 adds r3, #8 8003d52: 6819 ldr r1, [r3, #0] 8003d54: 89fb ldrh r3, [r7, #14] 8003d56: 79fa ldrb r2, [r7, #7] 8003d58: 4419 add r1, r3 8003d5a: 4839 ldr r0, [pc, #228] @ (8003e40 ) 8003d5c: 4613 mov r3, r2 8003d5e: 005b lsls r3, r3, #1 8003d60: 4413 add r3, r2 8003d62: 00db lsls r3, r3, #3 8003d64: 4403 add r3, r0 8003d66: 3308 adds r3, #8 8003d68: 6019 str r1, [r3, #0] time_left = aTimerContext[TimerID].CountLeft; 8003d6a: 79fa ldrb r2, [r7, #7] 8003d6c: 4934 ldr r1, [pc, #208] @ (8003e40 ) 8003d6e: 4613 mov r3, r2 8003d70: 005b lsls r3, r3, #1 8003d72: 4413 add r3, r2 8003d74: 00db lsls r3, r3, #3 8003d76: 440b add r3, r1 8003d78: 3308 adds r3, #8 8003d7a: 681b ldr r3, [r3, #0] 8003d7c: 60bb str r3, [r7, #8] /** * Search for index where the new timer shall be linked */ if(aTimerContext[CurrentRunningTimerID].CountLeft <= time_left) 8003d7e: 4b2e ldr r3, [pc, #184] @ (8003e38 ) 8003d80: 781b ldrb r3, [r3, #0] 8003d82: b2db uxtb r3, r3 8003d84: 4619 mov r1, r3 8003d86: 4a2e ldr r2, [pc, #184] @ (8003e40 ) 8003d88: 460b mov r3, r1 8003d8a: 005b lsls r3, r3, #1 8003d8c: 440b add r3, r1 8003d8e: 00db lsls r3, r3, #3 8003d90: 4413 add r3, r2 8003d92: 3308 adds r3, #8 8003d94: 681b ldr r3, [r3, #0] 8003d96: 68ba ldr r2, [r7, #8] 8003d98: 429a cmp r2, r3 8003d9a: d337 bcc.n 8003e0c { /** * Search for the ID after the first one */ timer_id_lookup = CurrentRunningTimerID; 8003d9c: 4b26 ldr r3, [pc, #152] @ (8003e38 ) 8003d9e: 781b ldrb r3, [r3, #0] 8003da0: 737b strb r3, [r7, #13] next_id = aTimerContext[timer_id_lookup].NextID; 8003da2: 7b7a ldrb r2, [r7, #13] 8003da4: 4926 ldr r1, [pc, #152] @ (8003e40 ) 8003da6: 4613 mov r3, r2 8003da8: 005b lsls r3, r3, #1 8003daa: 4413 add r3, r2 8003dac: 00db lsls r3, r3, #3 8003dae: 440b add r3, r1 8003db0: 3315 adds r3, #21 8003db2: 781b ldrb r3, [r3, #0] 8003db4: 733b strb r3, [r7, #12] while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left)) 8003db6: e013 b.n 8003de0 { timer_id_lookup = aTimerContext[timer_id_lookup].NextID; 8003db8: 7b7a ldrb r2, [r7, #13] 8003dba: 4921 ldr r1, [pc, #132] @ (8003e40 ) 8003dbc: 4613 mov r3, r2 8003dbe: 005b lsls r3, r3, #1 8003dc0: 4413 add r3, r2 8003dc2: 00db lsls r3, r3, #3 8003dc4: 440b add r3, r1 8003dc6: 3315 adds r3, #21 8003dc8: 781b ldrb r3, [r3, #0] 8003dca: 737b strb r3, [r7, #13] next_id = aTimerContext[timer_id_lookup].NextID; 8003dcc: 7b7a ldrb r2, [r7, #13] 8003dce: 491c ldr r1, [pc, #112] @ (8003e40 ) 8003dd0: 4613 mov r3, r2 8003dd2: 005b lsls r3, r3, #1 8003dd4: 4413 add r3, r2 8003dd6: 00db lsls r3, r3, #3 8003dd8: 440b add r3, r1 8003dda: 3315 adds r3, #21 8003ddc: 781b ldrb r3, [r3, #0] 8003dde: 733b strb r3, [r7, #12] while((next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (aTimerContext[next_id].CountLeft <= time_left)) 8003de0: 7b3b ldrb r3, [r7, #12] 8003de2: 2b06 cmp r3, #6 8003de4: d00b beq.n 8003dfe 8003de6: 7b3a ldrb r2, [r7, #12] 8003de8: 4915 ldr r1, [pc, #84] @ (8003e40 ) 8003dea: 4613 mov r3, r2 8003dec: 005b lsls r3, r3, #1 8003dee: 4413 add r3, r2 8003df0: 00db lsls r3, r3, #3 8003df2: 440b add r3, r1 8003df4: 3308 adds r3, #8 8003df6: 681b ldr r3, [r3, #0] 8003df8: 68ba ldr r2, [r7, #8] 8003dfa: 429a cmp r2, r3 8003dfc: d2dc bcs.n 8003db8 } /** * Link after the ID */ LinkTimerAfter(TimerID, timer_id_lookup); 8003dfe: 7b7a ldrb r2, [r7, #13] 8003e00: 79fb ldrb r3, [r7, #7] 8003e02: 4611 mov r1, r2 8003e04: 4618 mov r0, r3 8003e06: f7ff fecf bl 8003ba8 8003e0a: e00f b.n 8003e2c else { /** * Link before the first ID */ LinkTimerBefore(TimerID, CurrentRunningTimerID); 8003e0c: 4b0a ldr r3, [pc, #40] @ (8003e38 ) 8003e0e: 781b ldrb r3, [r3, #0] 8003e10: b2da uxtb r2, r3 8003e12: 79fb ldrb r3, [r7, #7] 8003e14: 4611 mov r1, r2 8003e16: 4618 mov r0, r3 8003e18: f7ff ff0c bl 8003c34 PreviousRunningTimerID = CurrentRunningTimerID; 8003e1c: 4b06 ldr r3, [pc, #24] @ (8003e38 ) 8003e1e: 781b ldrb r3, [r3, #0] 8003e20: b2da uxtb r2, r3 8003e22: 4b06 ldr r3, [pc, #24] @ (8003e3c ) 8003e24: 701a strb r2, [r3, #0] CurrentRunningTimerID = TimerID; 8003e26: 4a04 ldr r2, [pc, #16] @ (8003e38 ) 8003e28: 79fb ldrb r3, [r7, #7] 8003e2a: 7013 strb r3, [r2, #0] } } return time_elapsed; 8003e2c: 89fb ldrh r3, [r7, #14] } 8003e2e: 4618 mov r0, r3 8003e30: 3710 adds r7, #16 8003e32: 46bd mov sp, r7 8003e34: bd80 pop {r7, pc} 8003e36: bf00 nop 8003e38: 200003a4 .word 0x200003a4 8003e3c: 200003a5 .word 0x200003a5 8003e40: 20000314 .word 0x20000314 8003e44: 200003a8 .word 0x200003a8 08003e48 : * @param TimerID: The ID of the Timer * @param RequestReadSSR: Request to read the SSR register or not * @retval None */ static void UnlinkTimer(uint8_t TimerID, RequestReadSSR_t RequestReadSSR) { 8003e48: b480 push {r7} 8003e4a: b085 sub sp, #20 8003e4c: af00 add r7, sp, #0 8003e4e: 4603 mov r3, r0 8003e50: 460a mov r2, r1 8003e52: 71fb strb r3, [r7, #7] 8003e54: 4613 mov r3, r2 8003e56: 71bb strb r3, [r7, #6] uint8_t previous_id; uint8_t next_id; if(TimerID == CurrentRunningTimerID) 8003e58: 4b39 ldr r3, [pc, #228] @ (8003f40 ) 8003e5a: 781b ldrb r3, [r3, #0] 8003e5c: b2db uxtb r3, r3 8003e5e: 79fa ldrb r2, [r7, #7] 8003e60: 429a cmp r2, r3 8003e62: d111 bne.n 8003e88 { PreviousRunningTimerID = CurrentRunningTimerID; 8003e64: 4b36 ldr r3, [pc, #216] @ (8003f40 ) 8003e66: 781b ldrb r3, [r3, #0] 8003e68: b2da uxtb r2, r3 8003e6a: 4b36 ldr r3, [pc, #216] @ (8003f44 ) 8003e6c: 701a strb r2, [r3, #0] CurrentRunningTimerID = aTimerContext[TimerID].NextID; 8003e6e: 79fa ldrb r2, [r7, #7] 8003e70: 4935 ldr r1, [pc, #212] @ (8003f48 ) 8003e72: 4613 mov r3, r2 8003e74: 005b lsls r3, r3, #1 8003e76: 4413 add r3, r2 8003e78: 00db lsls r3, r3, #3 8003e7a: 440b add r3, r1 8003e7c: 3315 adds r3, #21 8003e7e: 781b ldrb r3, [r3, #0] 8003e80: b2da uxtb r2, r3 8003e82: 4b2f ldr r3, [pc, #188] @ (8003f40 ) 8003e84: 701a strb r2, [r3, #0] 8003e86: e03e b.n 8003f06 } else { previous_id = aTimerContext[TimerID].PreviousID; 8003e88: 79fa ldrb r2, [r7, #7] 8003e8a: 492f ldr r1, [pc, #188] @ (8003f48 ) 8003e8c: 4613 mov r3, r2 8003e8e: 005b lsls r3, r3, #1 8003e90: 4413 add r3, r2 8003e92: 00db lsls r3, r3, #3 8003e94: 440b add r3, r1 8003e96: 3314 adds r3, #20 8003e98: 781b ldrb r3, [r3, #0] 8003e9a: 73fb strb r3, [r7, #15] next_id = aTimerContext[TimerID].NextID; 8003e9c: 79fa ldrb r2, [r7, #7] 8003e9e: 492a ldr r1, [pc, #168] @ (8003f48 ) 8003ea0: 4613 mov r3, r2 8003ea2: 005b lsls r3, r3, #1 8003ea4: 4413 add r3, r2 8003ea6: 00db lsls r3, r3, #3 8003ea8: 440b add r3, r1 8003eaa: 3315 adds r3, #21 8003eac: 781b ldrb r3, [r3, #0] 8003eae: 73bb strb r3, [r7, #14] aTimerContext[previous_id].NextID = aTimerContext[TimerID].NextID; 8003eb0: 79f9 ldrb r1, [r7, #7] 8003eb2: 7bfa ldrb r2, [r7, #15] 8003eb4: 4824 ldr r0, [pc, #144] @ (8003f48 ) 8003eb6: 460b mov r3, r1 8003eb8: 005b lsls r3, r3, #1 8003eba: 440b add r3, r1 8003ebc: 00db lsls r3, r3, #3 8003ebe: 4403 add r3, r0 8003ec0: 3315 adds r3, #21 8003ec2: 781b ldrb r3, [r3, #0] 8003ec4: b2d8 uxtb r0, r3 8003ec6: 4920 ldr r1, [pc, #128] @ (8003f48 ) 8003ec8: 4613 mov r3, r2 8003eca: 005b lsls r3, r3, #1 8003ecc: 4413 add r3, r2 8003ece: 00db lsls r3, r3, #3 8003ed0: 440b add r3, r1 8003ed2: 3315 adds r3, #21 8003ed4: 4602 mov r2, r0 8003ed6: 701a strb r2, [r3, #0] if(next_id != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8003ed8: 7bbb ldrb r3, [r7, #14] 8003eda: 2b06 cmp r3, #6 8003edc: d013 beq.n 8003f06 { aTimerContext[next_id].PreviousID = aTimerContext[TimerID].PreviousID; 8003ede: 79f9 ldrb r1, [r7, #7] 8003ee0: 7bba ldrb r2, [r7, #14] 8003ee2: 4819 ldr r0, [pc, #100] @ (8003f48 ) 8003ee4: 460b mov r3, r1 8003ee6: 005b lsls r3, r3, #1 8003ee8: 440b add r3, r1 8003eea: 00db lsls r3, r3, #3 8003eec: 4403 add r3, r0 8003eee: 3314 adds r3, #20 8003ef0: 781b ldrb r3, [r3, #0] 8003ef2: b2d8 uxtb r0, r3 8003ef4: 4914 ldr r1, [pc, #80] @ (8003f48 ) 8003ef6: 4613 mov r3, r2 8003ef8: 005b lsls r3, r3, #1 8003efa: 4413 add r3, r2 8003efc: 00db lsls r3, r3, #3 8003efe: 440b add r3, r1 8003f00: 3314 adds r3, #20 8003f02: 4602 mov r2, r0 8003f04: 701a strb r2, [r3, #0] } /** * Timer is out of the list */ aTimerContext[TimerID].TimerIDStatus = TimerID_Created; 8003f06: 79fa ldrb r2, [r7, #7] 8003f08: 490f ldr r1, [pc, #60] @ (8003f48 ) 8003f0a: 4613 mov r3, r2 8003f0c: 005b lsls r3, r3, #1 8003f0e: 4413 add r3, r2 8003f10: 00db lsls r3, r3, #3 8003f12: 440b add r3, r1 8003f14: 330c adds r3, #12 8003f16: 2201 movs r2, #1 8003f18: 701a strb r2, [r3, #0] if((CurrentRunningTimerID == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) && (RequestReadSSR == SSR_Read_Requested)) 8003f1a: 4b09 ldr r3, [pc, #36] @ (8003f40 ) 8003f1c: 781b ldrb r3, [r3, #0] 8003f1e: b2db uxtb r3, r3 8003f20: 2b06 cmp r3, #6 8003f22: d107 bne.n 8003f34 8003f24: 79bb ldrb r3, [r7, #6] 8003f26: 2b00 cmp r3, #0 8003f28: d104 bne.n 8003f34 { SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; 8003f2a: 4b08 ldr r3, [pc, #32] @ (8003f4c ) 8003f2c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8003f30: 601a str r2, [r3, #0] } return; 8003f32: bf00 nop 8003f34: bf00 nop } 8003f36: 3714 adds r7, #20 8003f38: 46bd mov sp, r7 8003f3a: f85d 7b04 ldr.w r7, [sp], #4 8003f3e: 4770 bx lr 8003f40: 200003a4 .word 0x200003a4 8003f44: 200003a5 .word 0x200003a5 8003f48: 20000314 .word 0x20000314 8003f4c: 200003a8 .word 0x200003a8 08003f50 : * since the time the timer has been started * @param None * @retval Time expired in Ticks */ static uint16_t ReturnTimeElapsed(void) { 8003f50: b580 push {r7, lr} 8003f52: b082 sub sp, #8 8003f54: af00 add r7, sp, #0 uint32_t return_value; uint32_t wrap_counter; if(SSRValueOnLastSetup != SSR_FORBIDDEN_VALUE) 8003f56: 4b1a ldr r3, [pc, #104] @ (8003fc0 ) 8003f58: 681b ldr r3, [r3, #0] 8003f5a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8003f5e: d026 beq.n 8003fae { return_value = ReadRtcSsrValue(); /**< Read SSR register first */ 8003f60: f7ff fe02 bl 8003b68 8003f64: 6078 str r0, [r7, #4] if (SSRValueOnLastSetup >= return_value) 8003f66: 4b16 ldr r3, [pc, #88] @ (8003fc0 ) 8003f68: 681b ldr r3, [r3, #0] 8003f6a: 687a ldr r2, [r7, #4] 8003f6c: 429a cmp r2, r3 8003f6e: d805 bhi.n 8003f7c { return_value = SSRValueOnLastSetup - return_value; 8003f70: 4b13 ldr r3, [pc, #76] @ (8003fc0 ) 8003f72: 681a ldr r2, [r3, #0] 8003f74: 687b ldr r3, [r7, #4] 8003f76: 1ad3 subs r3, r2, r3 8003f78: 607b str r3, [r7, #4] 8003f7a: e00a b.n 8003f92 } else { wrap_counter = SynchPrescalerUserConfig - return_value; 8003f7c: 4b11 ldr r3, [pc, #68] @ (8003fc4 ) 8003f7e: 881b ldrh r3, [r3, #0] 8003f80: 461a mov r2, r3 8003f82: 687b ldr r3, [r7, #4] 8003f84: 1ad3 subs r3, r2, r3 8003f86: 603b str r3, [r7, #0] return_value = SSRValueOnLastSetup + wrap_counter; 8003f88: 4b0d ldr r3, [pc, #52] @ (8003fc0 ) 8003f8a: 681b ldr r3, [r3, #0] 8003f8c: 683a ldr r2, [r7, #0] 8003f8e: 4413 add r3, r2 8003f90: 607b str r3, [r7, #4] /** * At this stage, ReturnValue holds the number of ticks counted by SSR * Need to translate in number of ticks counted by the Wakeuptimer */ return_value = return_value*AsynchPrescalerUserConfig; 8003f92: 4b0d ldr r3, [pc, #52] @ (8003fc8 ) 8003f94: 781b ldrb r3, [r3, #0] 8003f96: 461a mov r2, r3 8003f98: 687b ldr r3, [r7, #4] 8003f9a: fb02 f303 mul.w r3, r2, r3 8003f9e: 607b str r3, [r7, #4] return_value = return_value >> WakeupTimerDivider; 8003fa0: 4b0a ldr r3, [pc, #40] @ (8003fcc ) 8003fa2: 781b ldrb r3, [r3, #0] 8003fa4: 461a mov r2, r3 8003fa6: 687b ldr r3, [r7, #4] 8003fa8: 40d3 lsrs r3, r2 8003faa: 607b str r3, [r7, #4] 8003fac: e001 b.n 8003fb2 } else { return_value = 0; 8003fae: 2300 movs r3, #0 8003fb0: 607b str r3, [r7, #4] } return (uint16_t)return_value; 8003fb2: 687b ldr r3, [r7, #4] 8003fb4: b29b uxth r3, r3 } 8003fb6: 4618 mov r0, r3 8003fb8: 3708 adds r7, #8 8003fba: 46bd mov sp, r7 8003fbc: bd80 pop {r7, pc} 8003fbe: bf00 nop 8003fc0: 200003a8 .word 0x200003a8 8003fc4: 200003b0 .word 0x200003b0 8003fc8: 200003ae .word 0x200003ae 8003fcc: 200003ad .word 0x200003ad 08003fd0 : * It assumes all condition are met to be allowed to write the wakeup counter * @param Value: Value to be written in the counter * @retval None */ static void RestartWakeupCounter(uint16_t Value) { 8003fd0: b580 push {r7, lr} 8003fd2: b082 sub sp, #8 8003fd4: af00 add r7, sp, #0 8003fd6: 4603 mov r3, r0 8003fd8: 80fb strh r3, [r7, #6] * The wakeuptimer has been disabled in the calling function to reduce the time to poll the WUTWF * FLAG when the new value will have to be written * __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); */ if(Value == 0) 8003fda: 88fb ldrh r3, [r7, #6] 8003fdc: 2b00 cmp r3, #0 8003fde: d108 bne.n 8003ff2 { SSRValueOnLastSetup = ReadRtcSsrValue(); 8003fe0: f7ff fdc2 bl 8003b68 8003fe4: 4603 mov r3, r0 8003fe6: 4a21 ldr r2, [pc, #132] @ (800406c ) 8003fe8: 6013 str r3, [r2, #0] /** * Simulate that the Timer expired */ HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); 8003fea: 2003 movs r0, #3 8003fec: f002 fe16 bl 8006c1c __HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */ HW_TS_RTC_CountUpdated_AppNot(); } return ; 8003ff0: e039 b.n 8004066 if((Value > 1) ||(WakeupTimerDivider != 1)) 8003ff2: 88fb ldrh r3, [r7, #6] 8003ff4: 2b01 cmp r3, #1 8003ff6: d803 bhi.n 8004000 8003ff8: 4b1d ldr r3, [pc, #116] @ (8004070 ) 8003ffa: 781b ldrb r3, [r3, #0] 8003ffc: 2b01 cmp r3, #1 8003ffe: d002 beq.n 8004006 Value -= 1; 8004000: 88fb ldrh r3, [r7, #6] 8004002: 3b01 subs r3, #1 8004004: 80fb strh r3, [r7, #6] while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET); 8004006: bf00 nop 8004008: 4b1a ldr r3, [pc, #104] @ (8004074 ) 800400a: 681b ldr r3, [r3, #0] 800400c: 68db ldr r3, [r3, #12] 800400e: f003 0304 and.w r3, r3, #4 8004012: 2b00 cmp r3, #0 8004014: d0f8 beq.n 8004008 __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ 8004016: 4b17 ldr r3, [pc, #92] @ (8004074 ) 8004018: 681b ldr r3, [r3, #0] 800401a: 68db ldr r3, [r3, #12] 800401c: b2da uxtb r2, r3 800401e: 4b15 ldr r3, [pc, #84] @ (8004074 ) 8004020: 681b ldr r3, [r3, #0] 8004022: f462 6290 orn r2, r2, #1152 @ 0x480 8004026: 60da str r2, [r3, #12] __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ 8004028: 4b13 ldr r3, [pc, #76] @ (8004078 ) 800402a: f44f 2200 mov.w r2, #524288 @ 0x80000 800402e: 60da str r2, [r3, #12] HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ 8004030: 2003 movs r0, #3 8004032: f002 fe01 bl 8006c38 MODIFY_REG(RTC->WUTR, RTC_WUTR_WUT, Value); 8004036: 4b11 ldr r3, [pc, #68] @ (800407c ) 8004038: 695b ldr r3, [r3, #20] 800403a: 0c1b lsrs r3, r3, #16 800403c: 041b lsls r3, r3, #16 800403e: 88fa ldrh r2, [r7, #6] 8004040: 490e ldr r1, [pc, #56] @ (800407c ) 8004042: 4313 orrs r3, r2 8004044: 614b str r3, [r1, #20] SSRValueOnLastSetup = ReadRtcSsrValue(); 8004046: f7ff fd8f bl 8003b68 800404a: 4603 mov r3, r0 800404c: 4a07 ldr r2, [pc, #28] @ (800406c ) 800404e: 6013 str r3, [r2, #0] __HAL_RTC_WAKEUPTIMER_ENABLE(&hrtc); /**< Enable the Wakeup Timer */ 8004050: 4b08 ldr r3, [pc, #32] @ (8004074 ) 8004052: 681b ldr r3, [r3, #0] 8004054: 689a ldr r2, [r3, #8] 8004056: 4b07 ldr r3, [pc, #28] @ (8004074 ) 8004058: 681b ldr r3, [r3, #0] 800405a: f442 6280 orr.w r2, r2, #1024 @ 0x400 800405e: 609a str r2, [r3, #8] HW_TS_RTC_CountUpdated_AppNot(); 8004060: f3af 8000 nop.w return ; 8004064: bf00 nop } 8004066: 3708 adds r7, #8 8004068: 46bd mov sp, r7 800406a: bd80 pop {r7, pc} 800406c: 200003a8 .word 0x200003a8 8004070: 200003ad .word 0x200003ad 8004074: 20000504 .word 0x20000504 8004078: 58000800 .word 0x58000800 800407c: 40002800 .word 0x40002800 08004080 : * 2) Setup the wakeuptimer * @param None * @retval None */ static void RescheduleTimerList(void) { 8004080: b580 push {r7, lr} 8004082: b084 sub sp, #16 8004084: af00 add r7, sp, #0 /** * The wakeuptimer is disabled now to reduce the time to poll the WUTWF * FLAG when the new value will have to be written */ if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET) 8004086: 4b45 ldr r3, [pc, #276] @ (800419c ) 8004088: 689b ldr r3, [r3, #8] 800408a: f403 6380 and.w r3, r3, #1024 @ 0x400 800408e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004092: d107 bne.n 80040a4 { /** * Wait for the flag to be back to 0 when the wakeup timer is enabled */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET); 8004094: bf00 nop 8004096: 4b42 ldr r3, [pc, #264] @ (80041a0 ) 8004098: 681b ldr r3, [r3, #0] 800409a: 68db ldr r3, [r3, #12] 800409c: f003 0304 and.w r3, r3, #4 80040a0: 2b00 cmp r3, #0 80040a2: d1f8 bne.n 8004096 } __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ 80040a4: 4b3e ldr r3, [pc, #248] @ (80041a0 ) 80040a6: 681b ldr r3, [r3, #0] 80040a8: 689a ldr r2, [r3, #8] 80040aa: 4b3d ldr r3, [pc, #244] @ (80041a0 ) 80040ac: 681b ldr r3, [r3, #0] 80040ae: f422 6280 bic.w r2, r2, #1024 @ 0x400 80040b2: 609a str r2, [r3, #8] localTimerID = CurrentRunningTimerID; 80040b4: 4b3b ldr r3, [pc, #236] @ (80041a4 ) 80040b6: 781b ldrb r3, [r3, #0] 80040b8: 73fb strb r3, [r7, #15] /** * Calculate what will be the value to write in the wakeuptimer */ timecountleft = aTimerContext[localTimerID].CountLeft; 80040ba: 7bfa ldrb r2, [r7, #15] 80040bc: 493a ldr r1, [pc, #232] @ (80041a8 ) 80040be: 4613 mov r3, r2 80040c0: 005b lsls r3, r3, #1 80040c2: 4413 add r3, r2 80040c4: 00db lsls r3, r3, #3 80040c6: 440b add r3, r1 80040c8: 3308 adds r3, #8 80040ca: 681b ldr r3, [r3, #0] 80040cc: 60bb str r3, [r7, #8] /** * Read how much has been counted */ time_elapsed = ReturnTimeElapsed(); 80040ce: f7ff ff3f bl 8003f50 80040d2: 4603 mov r3, r0 80040d4: 80fb strh r3, [r7, #6] if(timecountleft < time_elapsed ) 80040d6: 88fb ldrh r3, [r7, #6] 80040d8: 68ba ldr r2, [r7, #8] 80040da: 429a cmp r2, r3 80040dc: d205 bcs.n 80040ea { /** * There is no tick left to count */ wakeup_timer_value = 0; 80040de: 2300 movs r3, #0 80040e0: 81bb strh r3, [r7, #12] WakeupTimerLimitation = WakeupTimerValue_LargeEnough; 80040e2: 4b32 ldr r3, [pc, #200] @ (80041ac ) 80040e4: 2201 movs r2, #1 80040e6: 701a strb r2, [r3, #0] 80040e8: e04d b.n 8004186 } else { if(timecountleft > (time_elapsed + MaxWakeupTimerSetup)) 80040ea: 88fb ldrh r3, [r7, #6] 80040ec: 4a30 ldr r2, [pc, #192] @ (80041b0 ) 80040ee: 8812 ldrh r2, [r2, #0] 80040f0: b292 uxth r2, r2 80040f2: 4413 add r3, r2 80040f4: 461a mov r2, r3 80040f6: 68bb ldr r3, [r7, #8] 80040f8: 4293 cmp r3, r2 80040fa: d906 bls.n 800410a { /** * The number of tick left is greater than the Wakeuptimer maximum value */ wakeup_timer_value = MaxWakeupTimerSetup; 80040fc: 4b2c ldr r3, [pc, #176] @ (80041b0 ) 80040fe: 881b ldrh r3, [r3, #0] 8004100: 81bb strh r3, [r7, #12] WakeupTimerLimitation = WakeupTimerValue_Overpassed; 8004102: 4b2a ldr r3, [pc, #168] @ (80041ac ) 8004104: 2200 movs r2, #0 8004106: 701a strb r2, [r3, #0] 8004108: e03d b.n 8004186 } else { wakeup_timer_value = timecountleft - time_elapsed; 800410a: 68bb ldr r3, [r7, #8] 800410c: b29a uxth r2, r3 800410e: 88fb ldrh r3, [r7, #6] 8004110: 1ad3 subs r3, r2, r3 8004112: 81bb strh r3, [r7, #12] WakeupTimerLimitation = WakeupTimerValue_LargeEnough; 8004114: 4b25 ldr r3, [pc, #148] @ (80041ac ) 8004116: 2201 movs r2, #1 8004118: 701a strb r2, [r3, #0] } /** * update ticks left to be counted for each timer */ while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 800411a: e034 b.n 8004186 { if (aTimerContext[localTimerID].CountLeft < time_elapsed) 800411c: 7bfa ldrb r2, [r7, #15] 800411e: 4922 ldr r1, [pc, #136] @ (80041a8 ) 8004120: 4613 mov r3, r2 8004122: 005b lsls r3, r3, #1 8004124: 4413 add r3, r2 8004126: 00db lsls r3, r3, #3 8004128: 440b add r3, r1 800412a: 3308 adds r3, #8 800412c: 681a ldr r2, [r3, #0] 800412e: 88fb ldrh r3, [r7, #6] 8004130: 429a cmp r2, r3 8004132: d20a bcs.n 800414a { aTimerContext[localTimerID].CountLeft = 0; 8004134: 7bfa ldrb r2, [r7, #15] 8004136: 491c ldr r1, [pc, #112] @ (80041a8 ) 8004138: 4613 mov r3, r2 800413a: 005b lsls r3, r3, #1 800413c: 4413 add r3, r2 800413e: 00db lsls r3, r3, #3 8004140: 440b add r3, r1 8004142: 3308 adds r3, #8 8004144: 2200 movs r2, #0 8004146: 601a str r2, [r3, #0] 8004148: e013 b.n 8004172 } else { aTimerContext[localTimerID].CountLeft -= time_elapsed; 800414a: 7bfa ldrb r2, [r7, #15] 800414c: 4916 ldr r1, [pc, #88] @ (80041a8 ) 800414e: 4613 mov r3, r2 8004150: 005b lsls r3, r3, #1 8004152: 4413 add r3, r2 8004154: 00db lsls r3, r3, #3 8004156: 440b add r3, r1 8004158: 3308 adds r3, #8 800415a: 6819 ldr r1, [r3, #0] 800415c: 88fb ldrh r3, [r7, #6] 800415e: 7bfa ldrb r2, [r7, #15] 8004160: 1ac9 subs r1, r1, r3 8004162: 4811 ldr r0, [pc, #68] @ (80041a8 ) 8004164: 4613 mov r3, r2 8004166: 005b lsls r3, r3, #1 8004168: 4413 add r3, r2 800416a: 00db lsls r3, r3, #3 800416c: 4403 add r3, r0 800416e: 3308 adds r3, #8 8004170: 6019 str r1, [r3, #0] } localTimerID = aTimerContext[localTimerID].NextID; 8004172: 7bfa ldrb r2, [r7, #15] 8004174: 490c ldr r1, [pc, #48] @ (80041a8 ) 8004176: 4613 mov r3, r2 8004178: 005b lsls r3, r3, #1 800417a: 4413 add r3, r2 800417c: 00db lsls r3, r3, #3 800417e: 440b add r3, r1 8004180: 3315 adds r3, #21 8004182: 781b ldrb r3, [r3, #0] 8004184: 73fb strb r3, [r7, #15] while(localTimerID != CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 8004186: 7bfb ldrb r3, [r7, #15] 8004188: 2b06 cmp r3, #6 800418a: d1c7 bne.n 800411c } /** * Write next count */ RestartWakeupCounter(wakeup_timer_value); 800418c: 89bb ldrh r3, [r7, #12] 800418e: 4618 mov r0, r3 8004190: f7ff ff1e bl 8003fd0 return ; 8004194: bf00 nop } 8004196: 3710 adds r7, #16 8004198: 46bd mov sp, r7 800419a: bd80 pop {r7, pc} 800419c: 40002800 .word 0x40002800 80041a0: 20000504 .word 0x20000504 80041a4: 200003a4 .word 0x200003a4 80041a8: 20000314 .word 0x20000314 80041ac: 200003ac .word 0x200003ac 80041b0: 200003b2 .word 0x200003b2 080041b4 : * In order to ease maintainability, the unlock is done at the top and the lock at then end * in case some new implementation is coming in the future */ void HW_TS_RTC_Wakeup_Handler(void) { 80041b4: b580 push {r7, lr} 80041b6: b08a sub sp, #40 @ 0x28 80041b8: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80041ba: f3ef 8310 mrs r3, PRIMASK 80041be: 617b str r3, [r7, #20] return(result); 80041c0: 697b ldr r3, [r7, #20] #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) uint32_t primask_bit; #endif #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 80041c2: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("cpsid i" : : : "memory"); 80041c4: b672 cpsid i } 80041c6: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ #endif /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 80041c8: 4b59 ldr r3, [pc, #356] @ (8004330 ) 80041ca: 681b ldr r3, [r3, #0] 80041cc: 22ca movs r2, #202 @ 0xca 80041ce: 625a str r2, [r3, #36] @ 0x24 80041d0: 4b57 ldr r3, [pc, #348] @ (8004330 ) 80041d2: 681b ldr r3, [r3, #0] 80041d4: 2253 movs r2, #83 @ 0x53 80041d6: 625a str r2, [r3, #36] @ 0x24 /** * Disable the Wakeup Timer * This may speed up a bit the processing to wait the timer to be disabled * The timer is still counting 2 RTCCLK */ __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); 80041d8: 4b55 ldr r3, [pc, #340] @ (8004330 ) 80041da: 681b ldr r3, [r3, #0] 80041dc: 689a ldr r2, [r3, #8] 80041de: 4b54 ldr r3, [pc, #336] @ (8004330 ) 80041e0: 681b ldr r3, [r3, #0] 80041e2: f422 6280 bic.w r2, r2, #1024 @ 0x400 80041e6: 609a str r2, [r3, #8] local_current_running_timer_id = CurrentRunningTimerID; 80041e8: 4b52 ldr r3, [pc, #328] @ (8004334 ) 80041ea: 781b ldrb r3, [r3, #0] 80041ec: f887 3023 strb.w r3, [r7, #35] @ 0x23 if(aTimerContext[local_current_running_timer_id].TimerIDStatus == TimerID_Running) 80041f0: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 80041f4: 4950 ldr r1, [pc, #320] @ (8004338 ) 80041f6: 4613 mov r3, r2 80041f8: 005b lsls r3, r3, #1 80041fa: 4413 add r3, r2 80041fc: 00db lsls r3, r3, #3 80041fe: 440b add r3, r1 8004200: 330c adds r3, #12 8004202: 781b ldrb r3, [r3, #0] 8004204: b2db uxtb r3, r3 8004206: 2b02 cmp r3, #2 8004208: d16e bne.n 80042e8 { ptimer_callback = aTimerContext[local_current_running_timer_id].pTimerCallBack; 800420a: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 800420e: 494a ldr r1, [pc, #296] @ (8004338 ) 8004210: 4613 mov r3, r2 8004212: 005b lsls r3, r3, #1 8004214: 4413 add r3, r2 8004216: 00db lsls r3, r3, #3 8004218: 440b add r3, r1 800421a: 681b ldr r3, [r3, #0] 800421c: 61fb str r3, [r7, #28] timer_process_id = aTimerContext[local_current_running_timer_id].TimerProcessID; 800421e: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 8004222: 4945 ldr r1, [pc, #276] @ (8004338 ) 8004224: 4613 mov r3, r2 8004226: 005b lsls r3, r3, #1 8004228: 4413 add r3, r2 800422a: 00db lsls r3, r3, #3 800422c: 440b add r3, r1 800422e: 3310 adds r3, #16 8004230: 681b ldr r3, [r3, #0] 8004232: 61bb str r3, [r7, #24] * However, due to the inaccuracy of the reading of the time elapsed, it may return there is 1 tick * to be left whereas the count is over * A more secure implementation has been done with a flag to state whereas the full count has been written * in the wakeuptimer or not */ if(WakeupTimerLimitation != WakeupTimerValue_Overpassed) 8004234: 4b41 ldr r3, [pc, #260] @ (800433c ) 8004236: 781b ldrb r3, [r3, #0] 8004238: b2db uxtb r3, r3 800423a: 2b00 cmp r3, #0 800423c: d04c beq.n 80042d8 { if(aTimerContext[local_current_running_timer_id].TimerMode == hw_ts_Repeated) 800423e: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 8004242: 493d ldr r1, [pc, #244] @ (8004338 ) 8004244: 4613 mov r3, r2 8004246: 005b lsls r3, r3, #1 8004248: 4413 add r3, r2 800424a: 00db lsls r3, r3, #3 800424c: 440b add r3, r1 800424e: 330d adds r3, #13 8004250: 781b ldrb r3, [r3, #0] 8004252: b2db uxtb r3, r3 8004254: 2b01 cmp r3, #1 8004256: d124 bne.n 80042a2 { UnlinkTimer(local_current_running_timer_id, SSR_Read_Not_Requested); 8004258: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 800425c: 2101 movs r1, #1 800425e: 4618 mov r0, r3 8004260: f7ff fdf2 bl 8003e48 8004264: 6a7b ldr r3, [r7, #36] @ 0x24 8004266: 613b str r3, [r7, #16] \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004268: 693b ldr r3, [r7, #16] 800426a: f383 8810 msr PRIMASK, r3 } 800426e: bf00 nop #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif HW_TS_Start(local_current_running_timer_id, aTimerContext[local_current_running_timer_id].CounterInit); 8004270: f897 2023 ldrb.w r2, [r7, #35] @ 0x23 8004274: 4930 ldr r1, [pc, #192] @ (8004338 ) 8004276: 4613 mov r3, r2 8004278: 005b lsls r3, r3, #1 800427a: 4413 add r3, r2 800427c: 00db lsls r3, r3, #3 800427e: 440b add r3, r1 8004280: 3304 adds r3, #4 8004282: 681a ldr r2, [r3, #0] 8004284: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 8004288: 4611 mov r1, r2 800428a: 4618 mov r0, r3 800428c: f000 f9b8 bl 8004600 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 8004290: 4b27 ldr r3, [pc, #156] @ (8004330 ) 8004292: 681b ldr r3, [r3, #0] 8004294: 22ca movs r2, #202 @ 0xca 8004296: 625a str r2, [r3, #36] @ 0x24 8004298: 4b25 ldr r3, [pc, #148] @ (8004330 ) 800429a: 681b ldr r3, [r3, #0] 800429c: 2253 movs r2, #83 @ 0x53 800429e: 625a str r2, [r3, #36] @ 0x24 80042a0: e012 b.n 80042c8 80042a2: 6a7b ldr r3, [r7, #36] @ 0x24 80042a4: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80042a6: 68fb ldr r3, [r7, #12] 80042a8: f383 8810 msr PRIMASK, r3 } 80042ac: bf00 nop else { #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif HW_TS_Stop(local_current_running_timer_id); 80042ae: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 80042b2: 4618 mov r0, r3 80042b4: f000 f920 bl 80044f8 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 80042b8: 4b1d ldr r3, [pc, #116] @ (8004330 ) 80042ba: 681b ldr r3, [r3, #0] 80042bc: 22ca movs r2, #202 @ 0xca 80042be: 625a str r2, [r3, #36] @ 0x24 80042c0: 4b1b ldr r3, [pc, #108] @ (8004330 ) 80042c2: 681b ldr r3, [r3, #0] 80042c4: 2253 movs r2, #83 @ 0x53 80042c6: 625a str r2, [r3, #36] @ 0x24 } HW_TS_RTC_Int_AppNot(timer_process_id, local_current_running_timer_id, ptimer_callback); 80042c8: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 80042cc: 69fa ldr r2, [r7, #28] 80042ce: 4619 mov r1, r3 80042d0: 69b8 ldr r0, [r7, #24] 80042d2: f000 fa1b bl 800470c 80042d6: e022 b.n 800431e } else { RescheduleTimerList(); 80042d8: f7ff fed2 bl 8004080 80042dc: 6a7b ldr r3, [r7, #36] @ 0x24 80042de: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80042e0: 68bb ldr r3, [r7, #8] 80042e2: f383 8810 msr PRIMASK, r3 } 80042e6: e01a b.n 800431e /** * We should never end up in this case * However, if due to any bug in the timer server this is the case, the mistake may not impact the user. * We could just clean the interrupt flag and get out from this unexpected interrupt */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET); 80042e8: bf00 nop 80042ea: 4b11 ldr r3, [pc, #68] @ (8004330 ) 80042ec: 681b ldr r3, [r3, #0] 80042ee: 68db ldr r3, [r3, #12] 80042f0: f003 0304 and.w r3, r3, #4 80042f4: 2b00 cmp r3, #0 80042f6: d0f8 beq.n 80042ea * It takes 2 RTCCLK between the time the WUTE bit is disabled and the * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between * due to the autoreload feature */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ 80042f8: 4b0d ldr r3, [pc, #52] @ (8004330 ) 80042fa: 681b ldr r3, [r3, #0] 80042fc: 68db ldr r3, [r3, #12] 80042fe: b2da uxtb r2, r3 8004300: 4b0b ldr r3, [pc, #44] @ (8004330 ) 8004302: 681b ldr r3, [r3, #0] 8004304: f462 6290 orn r2, r2, #1152 @ 0x480 8004308: 60da str r2, [r3, #12] __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ 800430a: 4b0d ldr r3, [pc, #52] @ (8004340 ) 800430c: f44f 2200 mov.w r2, #524288 @ 0x80000 8004310: 60da str r2, [r3, #12] 8004312: 6a7b ldr r3, [r7, #36] @ 0x24 8004314: 607b str r3, [r7, #4] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004316: 687b ldr r3, [r7, #4] 8004318: f383 8810 msr PRIMASK, r3 } 800431c: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); 800431e: 4b04 ldr r3, [pc, #16] @ (8004330 ) 8004320: 681b ldr r3, [r3, #0] 8004322: 22ff movs r2, #255 @ 0xff 8004324: 625a str r2, [r3, #36] @ 0x24 return; 8004326: bf00 nop } 8004328: 3728 adds r7, #40 @ 0x28 800432a: 46bd mov sp, r7 800432c: bd80 pop {r7, pc} 800432e: bf00 nop 8004330: 20000504 .word 0x20000504 8004334: 200003a4 .word 0x200003a4 8004338: 20000314 .word 0x20000314 800433c: 200003ac .word 0x200003ac 8004340: 58000800 .word 0x58000800 08004344 : void HW_TS_Init(HW_TS_InitMode_t TimerInitMode, RTC_HandleTypeDef *phrtc) { 8004344: b580 push {r7, lr} 8004346: b088 sub sp, #32 8004348: af00 add r7, sp, #0 800434a: 4603 mov r3, r0 800434c: 6039 str r1, [r7, #0] 800434e: 71fb strb r3, [r7, #7] uint8_t loop; uint32_t localmaxwakeuptimersetup; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 8004350: 4b5e ldr r3, [pc, #376] @ (80044cc ) 8004352: 681b ldr r3, [r3, #0] 8004354: 22ca movs r2, #202 @ 0xca 8004356: 625a str r2, [r3, #36] @ 0x24 8004358: 4b5c ldr r3, [pc, #368] @ (80044cc ) 800435a: 681b ldr r3, [r3, #0] 800435c: 2253 movs r2, #83 @ 0x53 800435e: 625a str r2, [r3, #36] @ 0x24 SET_BIT(RTC->CR, RTC_CR_BYPSHAD); 8004360: 4b5b ldr r3, [pc, #364] @ (80044d0 ) 8004362: 689b ldr r3, [r3, #8] 8004364: 4a5a ldr r2, [pc, #360] @ (80044d0 ) 8004366: f043 0320 orr.w r3, r3, #32 800436a: 6093 str r3, [r2, #8] /** * Readout the user config */ WakeupTimerDivider = (4 - ((uint32_t)(READ_BIT(RTC->CR, RTC_CR_WUCKSEL)))); 800436c: 4b58 ldr r3, [pc, #352] @ (80044d0 ) 800436e: 689b ldr r3, [r3, #8] 8004370: b2db uxtb r3, r3 8004372: f003 0307 and.w r3, r3, #7 8004376: b2db uxtb r3, r3 8004378: f1c3 0304 rsb r3, r3, #4 800437c: b2da uxtb r2, r3 800437e: 4b55 ldr r3, [pc, #340] @ (80044d4 ) 8004380: 701a strb r2, [r3, #0] AsynchPrescalerUserConfig = (uint8_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_A) >> (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)) + 1; 8004382: 4b53 ldr r3, [pc, #332] @ (80044d0 ) 8004384: 691b ldr r3, [r3, #16] 8004386: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800438a: f44f 02fe mov.w r2, #8323072 @ 0x7f0000 800438e: 613a str r2, [r7, #16] uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004390: 693a ldr r2, [r7, #16] 8004392: fa92 f2a2 rbit r2, r2 8004396: 60fa str r2, [r7, #12] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8004398: 68fa ldr r2, [r7, #12] 800439a: 617a str r2, [r7, #20] optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 800439c: 697a ldr r2, [r7, #20] 800439e: 2a00 cmp r2, #0 80043a0: d101 bne.n 80043a6 { return 32U; 80043a2: 2220 movs r2, #32 80043a4: e003 b.n 80043ae } return __builtin_clz(value); 80043a6: 697a ldr r2, [r7, #20] 80043a8: fab2 f282 clz r2, r2 80043ac: b2d2 uxtb r2, r2 80043ae: 40d3 lsrs r3, r2 80043b0: b2db uxtb r3, r3 80043b2: 3301 adds r3, #1 80043b4: b2da uxtb r2, r3 80043b6: 4b48 ldr r3, [pc, #288] @ (80044d8 ) 80043b8: 701a strb r2, [r3, #0] SynchPrescalerUserConfig = (uint16_t)(READ_BIT(RTC->PRER, RTC_PRER_PREDIV_S)) + 1; 80043ba: 4b45 ldr r3, [pc, #276] @ (80044d0 ) 80043bc: 691b ldr r3, [r3, #16] 80043be: b29b uxth r3, r3 80043c0: f3c3 030e ubfx r3, r3, #0, #15 80043c4: b29b uxth r3, r3 80043c6: 3301 adds r3, #1 80043c8: b29a uxth r2, r3 80043ca: 4b44 ldr r3, [pc, #272] @ (80044dc ) 80043cc: 801a strh r2, [r3, #0] /** * Margin is taken to avoid wrong calculation when the wrap around is there and some * application interrupts may have delayed the reading */ localmaxwakeuptimersetup = ((((SynchPrescalerUserConfig - 1)*AsynchPrescalerUserConfig) - CFG_HW_TS_RTC_HANDLER_MAX_DELAY) >> WakeupTimerDivider); 80043ce: 4b43 ldr r3, [pc, #268] @ (80044dc ) 80043d0: 881b ldrh r3, [r3, #0] 80043d2: 3b01 subs r3, #1 80043d4: 4a40 ldr r2, [pc, #256] @ (80044d8 ) 80043d6: 7812 ldrb r2, [r2, #0] 80043d8: fb02 f303 mul.w r3, r2, r3 80043dc: f5a3 73a0 sub.w r3, r3, #320 @ 0x140 80043e0: 4a3c ldr r2, [pc, #240] @ (80044d4 ) 80043e2: 7812 ldrb r2, [r2, #0] 80043e4: 40d3 lsrs r3, r2 80043e6: 61bb str r3, [r7, #24] if(localmaxwakeuptimersetup >= 0xFFFF) 80043e8: 69bb ldr r3, [r7, #24] 80043ea: f64f 72fe movw r2, #65534 @ 0xfffe 80043ee: 4293 cmp r3, r2 80043f0: d904 bls.n 80043fc { MaxWakeupTimerSetup = 0xFFFF; 80043f2: 4b3b ldr r3, [pc, #236] @ (80044e0 ) 80043f4: f64f 72ff movw r2, #65535 @ 0xffff 80043f8: 801a strh r2, [r3, #0] 80043fa: e003 b.n 8004404 } else { MaxWakeupTimerSetup = (uint16_t)localmaxwakeuptimersetup; 80043fc: 69bb ldr r3, [r7, #24] 80043fe: b29a uxth r2, r3 8004400: 4b37 ldr r3, [pc, #220] @ (80044e0 ) 8004402: 801a strh r2, [r3, #0] } /** * Configure EXTI module */ LL_EXTI_EnableRisingTrig_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); 8004404: f44f 2000 mov.w r0, #524288 @ 0x80000 8004408: f7ff fb9c bl 8003b44 LL_EXTI_EnableIT_0_31(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); 800440c: f44f 2000 mov.w r0, #524288 @ 0x80000 8004410: f7ff fb84 bl 8003b1c if(TimerInitMode == hw_ts_InitMode_Full) 8004414: 79fb ldrb r3, [r7, #7] 8004416: 2b00 cmp r3, #0 8004418: d13d bne.n 8004496 { WakeupTimerLimitation = WakeupTimerValue_LargeEnough; 800441a: 4b32 ldr r3, [pc, #200] @ (80044e4 ) 800441c: 2201 movs r2, #1 800441e: 701a strb r2, [r3, #0] SSRValueOnLastSetup = SSR_FORBIDDEN_VALUE; 8004420: 4b31 ldr r3, [pc, #196] @ (80044e8 ) 8004422: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8004426: 601a str r2, [r3, #0] /** * Initialize the timer server */ for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++) 8004428: 2300 movs r3, #0 800442a: 77fb strb r3, [r7, #31] 800442c: e00c b.n 8004448 { aTimerContext[loop].TimerIDStatus = TimerID_Free; 800442e: 7ffa ldrb r2, [r7, #31] 8004430: 492e ldr r1, [pc, #184] @ (80044ec ) 8004432: 4613 mov r3, r2 8004434: 005b lsls r3, r3, #1 8004436: 4413 add r3, r2 8004438: 00db lsls r3, r3, #3 800443a: 440b add r3, r1 800443c: 330c adds r3, #12 800443e: 2200 movs r2, #0 8004440: 701a strb r2, [r3, #0] for(loop = 0; loop < CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; loop++) 8004442: 7ffb ldrb r3, [r7, #31] 8004444: 3301 adds r3, #1 8004446: 77fb strb r3, [r7, #31] 8004448: 7ffb ldrb r3, [r7, #31] 800444a: 2b05 cmp r3, #5 800444c: d9ef bls.n 800442e } CurrentRunningTimerID = CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER; /**< Set ID to non valid value */ 800444e: 4b28 ldr r3, [pc, #160] @ (80044f0 ) 8004450: 2206 movs r2, #6 8004452: 701a strb r2, [r3, #0] __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ 8004454: 4b1d ldr r3, [pc, #116] @ (80044cc ) 8004456: 681b ldr r3, [r3, #0] 8004458: 689a ldr r2, [r3, #8] 800445a: 4b1c ldr r3, [pc, #112] @ (80044cc ) 800445c: 681b ldr r3, [r3, #0] 800445e: f422 6280 bic.w r2, r2, #1024 @ 0x400 8004462: 609a str r2, [r3, #8] __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ 8004464: 4b19 ldr r3, [pc, #100] @ (80044cc ) 8004466: 681b ldr r3, [r3, #0] 8004468: 68db ldr r3, [r3, #12] 800446a: b2da uxtb r2, r3 800446c: 4b17 ldr r3, [pc, #92] @ (80044cc ) 800446e: 681b ldr r3, [r3, #0] 8004470: f462 6290 orn r2, r2, #1152 @ 0x480 8004474: 60da str r2, [r3, #12] __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ 8004476: 4b1f ldr r3, [pc, #124] @ (80044f4 ) 8004478: f44f 2200 mov.w r2, #524288 @ 0x80000 800447c: 60da str r2, [r3, #12] HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ 800447e: 2003 movs r0, #3 8004480: f002 fbda bl 8006c38 __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hrtc, RTC_IT_WUT); /**< Enable interrupt in RTC module */ 8004484: 4b11 ldr r3, [pc, #68] @ (80044cc ) 8004486: 681b ldr r3, [r3, #0] 8004488: 689a ldr r2, [r3, #8] 800448a: 4b10 ldr r3, [pc, #64] @ (80044cc ) 800448c: 681b ldr r3, [r3, #0] 800448e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8004492: 609a str r2, [r3, #8] 8004494: e009 b.n 80044aa } else { if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTF) != RESET) 8004496: 4b0d ldr r3, [pc, #52] @ (80044cc ) 8004498: 681b ldr r3, [r3, #0] 800449a: 68db ldr r3, [r3, #12] 800449c: f403 6380 and.w r3, r3, #1024 @ 0x400 80044a0: 2b00 cmp r3, #0 80044a2: d002 beq.n 80044aa { /** * Simulate that the Timer expired */ HAL_NVIC_SetPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); 80044a4: 2003 movs r0, #3 80044a6: f002 fbb9 bl 8006c1c } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); 80044aa: 4b08 ldr r3, [pc, #32] @ (80044cc ) 80044ac: 681b ldr r3, [r3, #0] 80044ae: 22ff movs r2, #255 @ 0xff 80044b0: 625a str r2, [r3, #36] @ 0x24 HAL_NVIC_SetPriority(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO, CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO); /**< Set NVIC priority */ 80044b2: 2200 movs r2, #0 80044b4: 2106 movs r1, #6 80044b6: 2003 movs r0, #3 80044b8: f002 fb7a bl 8006bb0 HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ 80044bc: 2003 movs r0, #3 80044be: f002 fb91 bl 8006be4 return; 80044c2: bf00 nop } 80044c4: 3720 adds r7, #32 80044c6: 46bd mov sp, r7 80044c8: bd80 pop {r7, pc} 80044ca: bf00 nop 80044cc: 20000504 .word 0x20000504 80044d0: 40002800 .word 0x40002800 80044d4: 200003ad .word 0x200003ad 80044d8: 200003ae .word 0x200003ae 80044dc: 200003b0 .word 0x200003b0 80044e0: 200003b2 .word 0x200003b2 80044e4: 200003ac .word 0x200003ac 80044e8: 200003a8 .word 0x200003a8 80044ec: 20000314 .word 0x20000314 80044f0: 200003a4 .word 0x200003a4 80044f4: 58000800 .word 0x58000800 080044f8 : return; } void HW_TS_Stop(uint8_t timer_id) { 80044f8: b580 push {r7, lr} 80044fa: b086 sub sp, #24 80044fc: af00 add r7, sp, #0 80044fe: 4603 mov r3, r0 8004500: 71fb strb r3, [r7, #7] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004502: f3ef 8310 mrs r3, PRIMASK 8004506: 60fb str r3, [r7, #12] return(result); 8004508: 68fb ldr r3, [r7, #12] #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) uint32_t primask_bit; #endif #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 800450a: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 800450c: b672 cpsid i } 800450e: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ #endif HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */ 8004510: 2003 movs r0, #3 8004512: f002 fb75 bl 8006c00 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 8004516: 4b34 ldr r3, [pc, #208] @ (80045e8 ) 8004518: 681b ldr r3, [r3, #0] 800451a: 22ca movs r2, #202 @ 0xca 800451c: 625a str r2, [r3, #36] @ 0x24 800451e: 4b32 ldr r3, [pc, #200] @ (80045e8 ) 8004520: 681b ldr r3, [r3, #0] 8004522: 2253 movs r2, #83 @ 0x53 8004524: 625a str r2, [r3, #36] @ 0x24 if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running) 8004526: 79fa ldrb r2, [r7, #7] 8004528: 4930 ldr r1, [pc, #192] @ (80045ec ) 800452a: 4613 mov r3, r2 800452c: 005b lsls r3, r3, #1 800452e: 4413 add r3, r2 8004530: 00db lsls r3, r3, #3 8004532: 440b add r3, r1 8004534: 330c adds r3, #12 8004536: 781b ldrb r3, [r3, #0] 8004538: b2db uxtb r3, r3 800453a: 2b02 cmp r3, #2 800453c: d142 bne.n 80045c4 { UnlinkTimer(timer_id, SSR_Read_Requested); 800453e: 79fb ldrb r3, [r7, #7] 8004540: 2100 movs r1, #0 8004542: 4618 mov r0, r3 8004544: f7ff fc80 bl 8003e48 localcurrentrunningtimerid = CurrentRunningTimerID; 8004548: 4b29 ldr r3, [pc, #164] @ (80045f0 ) 800454a: 781b ldrb r3, [r3, #0] 800454c: 74fb strb r3, [r7, #19] if(localcurrentrunningtimerid == CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER) 800454e: 7cfb ldrb r3, [r7, #19] 8004550: 2b06 cmp r3, #6 8004552: d12f bne.n 80045b4 */ /** * Disable the timer */ if((READ_BIT(RTC->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) == SET) 8004554: 4b27 ldr r3, [pc, #156] @ (80045f4 ) 8004556: 689b ldr r3, [r3, #8] 8004558: f403 6380 and.w r3, r3, #1024 @ 0x400 800455c: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004560: d107 bne.n 8004572 { /** * Wait for the flag to be back to 0 when the wakeup timer is enabled */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == SET); 8004562: bf00 nop 8004564: 4b20 ldr r3, [pc, #128] @ (80045e8 ) 8004566: 681b ldr r3, [r3, #0] 8004568: 68db ldr r3, [r3, #12] 800456a: f003 0304 and.w r3, r3, #4 800456e: 2b00 cmp r3, #0 8004570: d1f8 bne.n 8004564 } __HAL_RTC_WAKEUPTIMER_DISABLE(&hrtc); /**< Disable the Wakeup Timer */ 8004572: 4b1d ldr r3, [pc, #116] @ (80045e8 ) 8004574: 681b ldr r3, [r3, #0] 8004576: 689a ldr r2, [r3, #8] 8004578: 4b1b ldr r3, [pc, #108] @ (80045e8 ) 800457a: 681b ldr r3, [r3, #0] 800457c: f422 6280 bic.w r2, r2, #1024 @ 0x400 8004580: 609a str r2, [r3, #8] while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hrtc, RTC_FLAG_WUTWF) == RESET); 8004582: bf00 nop 8004584: 4b18 ldr r3, [pc, #96] @ (80045e8 ) 8004586: 681b ldr r3, [r3, #0] 8004588: 68db ldr r3, [r3, #12] 800458a: f003 0304 and.w r3, r3, #4 800458e: 2b00 cmp r3, #0 8004590: d0f8 beq.n 8004584 * It takes 2 RTCCLK between the time the WUTE bit is disabled and the * time the timer is disabled. The WUTWF bit somehow guarantee the system is stable * Otherwise, when the timer is periodic with 1 Tick, it may generate an extra interrupt in between * due to the autoreload feature */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); /**< Clear flag in RTC module */ 8004592: 4b15 ldr r3, [pc, #84] @ (80045e8 ) 8004594: 681b ldr r3, [r3, #0] 8004596: 68db ldr r3, [r3, #12] 8004598: b2da uxtb r2, r3 800459a: 4b13 ldr r3, [pc, #76] @ (80045e8 ) 800459c: 681b ldr r3, [r3, #0] 800459e: f462 6290 orn r2, r2, #1152 @ 0x480 80045a2: 60da str r2, [r3, #12] __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /**< Clear flag in EXTI module */ 80045a4: 4b14 ldr r3, [pc, #80] @ (80045f8 ) 80045a6: f44f 2200 mov.w r2, #524288 @ 0x80000 80045aa: 60da str r2, [r3, #12] HAL_NVIC_ClearPendingIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Clear pending bit in NVIC */ 80045ac: 2003 movs r0, #3 80045ae: f002 fb43 bl 8006c38 80045b2: e007 b.n 80045c4 } else if(PreviousRunningTimerID != localcurrentrunningtimerid) 80045b4: 4b11 ldr r3, [pc, #68] @ (80045fc ) 80045b6: 781b ldrb r3, [r3, #0] 80045b8: b2db uxtb r3, r3 80045ba: 7cfa ldrb r2, [r7, #19] 80045bc: 429a cmp r2, r3 80045be: d001 beq.n 80045c4 { RescheduleTimerList(); 80045c0: f7ff fd5e bl 8004080 } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); 80045c4: 4b08 ldr r3, [pc, #32] @ (80045e8 ) 80045c6: 681b ldr r3, [r3, #0] 80045c8: 22ff movs r2, #255 @ 0xff 80045ca: 625a str r2, [r3, #36] @ 0x24 HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ 80045cc: 2003 movs r0, #3 80045ce: f002 fb09 bl 8006be4 80045d2: 697b ldr r3, [r7, #20] 80045d4: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80045d6: 68bb ldr r3, [r7, #8] 80045d8: f383 8810 msr PRIMASK, r3 } 80045dc: bf00 nop #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif return; 80045de: bf00 nop } 80045e0: 3718 adds r7, #24 80045e2: 46bd mov sp, r7 80045e4: bd80 pop {r7, pc} 80045e6: bf00 nop 80045e8: 20000504 .word 0x20000504 80045ec: 20000314 .word 0x20000314 80045f0: 200003a4 .word 0x200003a4 80045f4: 40002800 .word 0x40002800 80045f8: 58000800 .word 0x58000800 80045fc: 200003a5 .word 0x200003a5 08004600 : void HW_TS_Start(uint8_t timer_id, uint32_t timeout_ticks) { 8004600: b580 push {r7, lr} 8004602: b086 sub sp, #24 8004604: af00 add r7, sp, #0 8004606: 4603 mov r3, r0 8004608: 6039 str r1, [r7, #0] 800460a: 71fb strb r3, [r7, #7] #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) uint32_t primask_bit; #endif if(aTimerContext[timer_id].TimerIDStatus == TimerID_Running) 800460c: 79fa ldrb r2, [r7, #7] 800460e: 493b ldr r1, [pc, #236] @ (80046fc ) 8004610: 4613 mov r3, r2 8004612: 005b lsls r3, r3, #1 8004614: 4413 add r3, r2 8004616: 00db lsls r3, r3, #3 8004618: 440b add r3, r1 800461a: 330c adds r3, #12 800461c: 781b ldrb r3, [r3, #0] 800461e: b2db uxtb r3, r3 8004620: 2b02 cmp r3, #2 8004622: d103 bne.n 800462c { HW_TS_Stop( timer_id ); 8004624: 79fb ldrb r3, [r7, #7] 8004626: 4618 mov r0, r3 8004628: f7ff ff66 bl 80044f8 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800462c: f3ef 8310 mrs r3, PRIMASK 8004630: 60fb str r3, [r7, #12] return(result); 8004632: 68fb ldr r3, [r7, #12] } #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 8004634: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 8004636: b672 cpsid i } 8004638: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ #endif HAL_NVIC_DisableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Disable NVIC */ 800463a: 2003 movs r0, #3 800463c: f002 fae0 bl 8006c00 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE( &hrtc ); 8004640: 4b2f ldr r3, [pc, #188] @ (8004700 ) 8004642: 681b ldr r3, [r3, #0] 8004644: 22ca movs r2, #202 @ 0xca 8004646: 625a str r2, [r3, #36] @ 0x24 8004648: 4b2d ldr r3, [pc, #180] @ (8004700 ) 800464a: 681b ldr r3, [r3, #0] 800464c: 2253 movs r2, #83 @ 0x53 800464e: 625a str r2, [r3, #36] @ 0x24 aTimerContext[timer_id].TimerIDStatus = TimerID_Running; 8004650: 79fa ldrb r2, [r7, #7] 8004652: 492a ldr r1, [pc, #168] @ (80046fc ) 8004654: 4613 mov r3, r2 8004656: 005b lsls r3, r3, #1 8004658: 4413 add r3, r2 800465a: 00db lsls r3, r3, #3 800465c: 440b add r3, r1 800465e: 330c adds r3, #12 8004660: 2202 movs r2, #2 8004662: 701a strb r2, [r3, #0] aTimerContext[timer_id].CountLeft = timeout_ticks; 8004664: 79fa ldrb r2, [r7, #7] 8004666: 4925 ldr r1, [pc, #148] @ (80046fc ) 8004668: 4613 mov r3, r2 800466a: 005b lsls r3, r3, #1 800466c: 4413 add r3, r2 800466e: 00db lsls r3, r3, #3 8004670: 440b add r3, r1 8004672: 3308 adds r3, #8 8004674: 683a ldr r2, [r7, #0] 8004676: 601a str r2, [r3, #0] aTimerContext[timer_id].CounterInit = timeout_ticks; 8004678: 79fa ldrb r2, [r7, #7] 800467a: 4920 ldr r1, [pc, #128] @ (80046fc ) 800467c: 4613 mov r3, r2 800467e: 005b lsls r3, r3, #1 8004680: 4413 add r3, r2 8004682: 00db lsls r3, r3, #3 8004684: 440b add r3, r1 8004686: 3304 adds r3, #4 8004688: 683a ldr r2, [r7, #0] 800468a: 601a str r2, [r3, #0] time_elapsed = linkTimer(timer_id); 800468c: 79fb ldrb r3, [r7, #7] 800468e: 4618 mov r0, r3 8004690: f7ff fb30 bl 8003cf4 8004694: 4603 mov r3, r0 8004696: 827b strh r3, [r7, #18] localcurrentrunningtimerid = CurrentRunningTimerID; 8004698: 4b1a ldr r3, [pc, #104] @ (8004704 ) 800469a: 781b ldrb r3, [r3, #0] 800469c: 747b strb r3, [r7, #17] if(PreviousRunningTimerID != localcurrentrunningtimerid) 800469e: 4b1a ldr r3, [pc, #104] @ (8004708 ) 80046a0: 781b ldrb r3, [r3, #0] 80046a2: b2db uxtb r3, r3 80046a4: 7c7a ldrb r2, [r7, #17] 80046a6: 429a cmp r2, r3 80046a8: d002 beq.n 80046b0 { RescheduleTimerList(); 80046aa: f7ff fce9 bl 8004080 80046ae: e013 b.n 80046d8 } else { aTimerContext[timer_id].CountLeft -= time_elapsed; 80046b0: 79fa ldrb r2, [r7, #7] 80046b2: 4912 ldr r1, [pc, #72] @ (80046fc ) 80046b4: 4613 mov r3, r2 80046b6: 005b lsls r3, r3, #1 80046b8: 4413 add r3, r2 80046ba: 00db lsls r3, r3, #3 80046bc: 440b add r3, r1 80046be: 3308 adds r3, #8 80046c0: 6819 ldr r1, [r3, #0] 80046c2: 8a7b ldrh r3, [r7, #18] 80046c4: 79fa ldrb r2, [r7, #7] 80046c6: 1ac9 subs r1, r1, r3 80046c8: 480c ldr r0, [pc, #48] @ (80046fc ) 80046ca: 4613 mov r3, r2 80046cc: 005b lsls r3, r3, #1 80046ce: 4413 add r3, r2 80046d0: 00db lsls r3, r3, #3 80046d2: 4403 add r3, r0 80046d4: 3308 adds r3, #8 80046d6: 6019 str r1, [r3, #0] } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE( &hrtc ); 80046d8: 4b09 ldr r3, [pc, #36] @ (8004700 ) 80046da: 681b ldr r3, [r3, #0] 80046dc: 22ff movs r2, #255 @ 0xff 80046de: 625a str r2, [r3, #36] @ 0x24 HAL_NVIC_EnableIRQ(CFG_HW_TS_RTC_WAKEUP_HANDLER_ID); /**< Enable NVIC */ 80046e0: 2003 movs r0, #3 80046e2: f002 fa7f bl 8006be4 80046e6: 697b ldr r3, [r7, #20] 80046e8: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80046ea: 68bb ldr r3, [r7, #8] 80046ec: f383 8810 msr PRIMASK, r3 } 80046f0: bf00 nop #if (CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION == 1) __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ #endif return; 80046f2: bf00 nop } 80046f4: 3718 adds r7, #24 80046f6: 46bd mov sp, r7 80046f8: bd80 pop {r7, pc} 80046fa: bf00 nop 80046fc: 20000314 .word 0x20000314 8004700: 20000504 .word 0x20000504 8004704: 200003a4 .word 0x200003a4 8004708: 200003a5 .word 0x200003a5 0800470c : return (return_value); } __weak void HW_TS_RTC_Int_AppNot(uint32_t TimerProcessID, uint8_t TimerID, HW_TS_pTimerCb_t pTimerCallBack) { 800470c: b580 push {r7, lr} 800470e: b084 sub sp, #16 8004710: af00 add r7, sp, #0 8004712: 60f8 str r0, [r7, #12] 8004714: 460b mov r3, r1 8004716: 607a str r2, [r7, #4] 8004718: 72fb strb r3, [r7, #11] pTimerCallBack(); 800471a: 687b ldr r3, [r7, #4] 800471c: 4798 blx r3 return; 800471e: bf00 nop } 8004720: 3710 adds r7, #16 8004722: 46bd mov sp, r7 8004724: bd80 pop {r7, pc} 08004726 : \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { 8004726: b480 push {r7} 8004728: b083 sub sp, #12 800472a: af00 add r7, sp, #0 800472c: 6078 str r0, [r7, #4] if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 800472e: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 8004732: f8d3 3e80 ldr.w r3, [r3, #3712] @ 0xe80 8004736: f003 0301 and.w r3, r3, #1 800473a: 2b00 cmp r3, #0 800473c: d013 beq.n 8004766 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 800473e: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 8004742: f8d3 3e00 ldr.w r3, [r3, #3584] @ 0xe00 8004746: f003 0301 and.w r3, r3, #1 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 800474a: 2b00 cmp r3, #0 800474c: d00b beq.n 8004766 { while (ITM->PORT[0U].u32 == 0UL) 800474e: e000 b.n 8004752 { __NOP(); 8004750: bf00 nop while (ITM->PORT[0U].u32 == 0UL) 8004752: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 8004756: 681b ldr r3, [r3, #0] 8004758: 2b00 cmp r3, #0 800475a: d0f9 beq.n 8004750 } ITM->PORT[0U].u8 = (uint8_t)ch; 800475c: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 8004760: 687a ldr r2, [r7, #4] 8004762: b2d2 uxtb r2, r2 8004764: 701a strb r2, [r3, #0] } return (ch); 8004766: 687b ldr r3, [r7, #4] } 8004768: 4618 mov r0, r3 800476a: 370c adds r7, #12 800476c: 46bd mov sp, r7 800476e: f85d 7b04 ldr.w r7, [sp], #4 8004772: 4770 bx lr 08004774 : { 8004774: b480 push {r7} 8004776: b083 sub sp, #12 8004778: af00 add r7, sp, #0 800477a: 6078 str r0, [r7, #4] MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); 800477c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8004780: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004784: f023 0218 bic.w r2, r3, #24 8004788: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800478c: 687b ldr r3, [r7, #4] 800478e: 4313 orrs r3, r2 8004790: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 8004794: bf00 nop 8004796: 370c adds r7, #12 8004798: 46bd mov sp, r7 800479a: f85d 7b04 ldr.w r7, [sp], #4 800479e: 4770 bx lr 080047a0 : * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) { 80047a0: b480 push {r7} 80047a2: b085 sub sp, #20 80047a4: af00 add r7, sp, #0 80047a6: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB1ENR, Periphs); 80047a8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80047ac: 6c9a ldr r2, [r3, #72] @ 0x48 80047ae: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80047b2: 687b ldr r3, [r7, #4] 80047b4: 4313 orrs r3, r2 80047b6: 648b str r3, [r1, #72] @ 0x48 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 80047b8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80047bc: 6c9a ldr r2, [r3, #72] @ 0x48 80047be: 687b ldr r3, [r7, #4] 80047c0: 4013 ands r3, r2 80047c2: 60fb str r3, [r7, #12] (void)tmpreg; 80047c4: 68fb ldr r3, [r7, #12] } 80047c6: bf00 nop 80047c8: 3714 adds r7, #20 80047ca: 46bd mov sp, r7 80047cc: f85d 7b04 ldr.w r7, [sp], #4 80047d0: 4770 bx lr 080047d2 : * @arg @ref LL_AHB2_GRP1_PERIPH_AES1 (*) * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) { 80047d2: b480 push {r7} 80047d4: b085 sub sp, #20 80047d6: af00 add r7, sp, #0 80047d8: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB2ENR, Periphs); 80047da: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80047de: 6cda ldr r2, [r3, #76] @ 0x4c 80047e0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80047e4: 687b ldr r3, [r7, #4] 80047e6: 4313 orrs r3, r2 80047e8: 64cb str r3, [r1, #76] @ 0x4c /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 80047ea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80047ee: 6cda ldr r2, [r3, #76] @ 0x4c 80047f0: 687b ldr r3, [r7, #4] 80047f2: 4013 ands r3, r2 80047f4: 60fb str r3, [r7, #12] (void)tmpreg; 80047f6: 68fb ldr r3, [r7, #12] } 80047f8: bf00 nop 80047fa: 3714 adds r7, #20 80047fc: 46bd mov sp, r7 80047fe: f85d 7b04 ldr.w r7, [sp], #4 8004802: 4770 bx lr 08004804 : * @param HSEMx HSEM Instance. * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 1 lock fail, 0 lock successful or already locked by same core */ __STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { 8004804: b480 push {r7} 8004806: b083 sub sp, #12 8004808: af00 add r7, sp, #0 800480a: 6078 str r0, [r7, #4] 800480c: 6039 str r1, [r7, #0] return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); 800480e: 687b ldr r3, [r7, #4] 8004810: 683a ldr r2, [r7, #0] 8004812: 3220 adds r2, #32 8004814: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8004818: 4a05 ldr r2, [pc, #20] @ (8004830 ) 800481a: 4293 cmp r3, r2 800481c: d001 beq.n 8004822 800481e: 2301 movs r3, #1 8004820: e000 b.n 8004824 8004822: 2300 movs r3, #0 } 8004824: 4618 mov r0, r3 8004826: 370c adds r7, #12 8004828: 46bd mov sp, r7 800482a: f85d 7b04 ldr.w r7, [sp], #4 800482e: 4770 bx lr 8004830: 80000400 .word 0x80000400 08004834 <_write>: /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ // implementation of printf() functionality through ITM int _write(int file, char *prt, int len) { 8004834: b580 push {r7, lr} 8004836: b086 sub sp, #24 8004838: af00 add r7, sp, #0 800483a: 60f8 str r0, [r7, #12] 800483c: 60b9 str r1, [r7, #8] 800483e: 607a str r2, [r7, #4] for (int i = 0; i < len; i++) { 8004840: 2300 movs r3, #0 8004842: 617b str r3, [r7, #20] 8004844: e009 b.n 800485a <_write+0x26> ITM_SendChar(*prt++); 8004846: 68bb ldr r3, [r7, #8] 8004848: 1c5a adds r2, r3, #1 800484a: 60ba str r2, [r7, #8] 800484c: 781b ldrb r3, [r3, #0] 800484e: 4618 mov r0, r3 8004850: f7ff ff69 bl 8004726 for (int i = 0; i < len; i++) { 8004854: 697b ldr r3, [r7, #20] 8004856: 3301 adds r3, #1 8004858: 617b str r3, [r7, #20] 800485a: 697a ldr r2, [r7, #20] 800485c: 687b ldr r3, [r7, #4] 800485e: 429a cmp r2, r3 8004860: dbf1 blt.n 8004846 <_write+0x12> } return len; 8004862: 687b ldr r3, [r7, #4] } 8004864: 4618 mov r0, r3 8004866: 3718 adds r7, #24 8004868: 46bd mov sp, r7 800486a: bd80 pop {r7, pc} 0800486c
: /** * @brief The application entry point. * @retval int */ int main(void) { 800486c: b580 push {r7, lr} 800486e: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8004870: f002 f83a bl 80068e8 /* Config code for STM32_WPAN (HSE Tuning must be done before system clock configuration) */ MX_APPE_Config(); 8004874: f7fd fd78 bl 8002368 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8004878: f000 f86a bl 8004950 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 800487c: f000 f8de bl 8004a3c /* IPCC initialisation */ MX_IPCC_Init(); 8004880: f000 f93c bl 8004afc /* USER CODE BEGIN SysInit */ // Initialize DWT for the BMM350 delay function to work properly bmm_init_DWT(); 8004884: f001 f9fe bl 8005c84 /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8004888: f000 fa9e bl 8004dc8 MX_DMA_Init(); 800488c: f000 fa72 bl 8004d74 MX_I2C1_Init(); 8004890: f000 f8f4 bl 8004a7c MX_SPI1_Init(); 8004894: f000 f982 bl 8004b9c MX_SPI2_Init(); 8004898: f000 f9be bl 8004c18 MX_TIM2_Init(); 800489c: f000 f9fa bl 8004c94 MX_RTC_Init(); 80048a0: f000 f948 bl 8004b34 MX_RF_Init(); 80048a4: f000 f93e bl 8004b24 /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 80048a8: f00f f806 bl 80138b8 /* start timers, add new ones, ... */ /* USER CODE END RTOS_TIMERS */ /* Create the queue(s) */ /* creation of Q_ICM */ Q_ICMHandle = osMessageQueueNew (1, sizeof(ICM45686_Data), &Q_ICM_attributes); 80048ac: 4a1a ldr r2, [pc, #104] @ (8004918 ) 80048ae: 211c movs r1, #28 80048b0: 2001 movs r0, #1 80048b2: f00f fbed bl 8014090 80048b6: 4603 mov r3, r0 80048b8: 4a18 ldr r2, [pc, #96] @ (800491c ) 80048ba: 6013 str r3, [r2, #0] /* creation of Q_BMM */ Q_BMMHandle = osMessageQueueNew (1, sizeof(struct bmm350_mag_temp_data), &Q_BMM_attributes); 80048bc: 4a18 ldr r2, [pc, #96] @ (8004920 ) 80048be: 2110 movs r1, #16 80048c0: 2001 movs r0, #1 80048c2: f00f fbe5 bl 8014090 80048c6: 4603 mov r3, r0 80048c8: 4a16 ldr r2, [pc, #88] @ (8004924 ) 80048ca: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of Task_DataAnalys */ Task_DataAnalysHandle = osThreadNew(Start_DataAnalysis, NULL, &Task_DataAnalys_attributes); 80048cc: 4a16 ldr r2, [pc, #88] @ (8004928 ) 80048ce: 2100 movs r1, #0 80048d0: 4816 ldr r0, [pc, #88] @ (800492c ) 80048d2: f00f f841 bl 8013958 80048d6: 4603 mov r3, r0 80048d8: 4a15 ldr r2, [pc, #84] @ (8004930 ) 80048da: 6013 str r3, [r2, #0] /* creation of Task_ICM45686 */ Task_ICM45686Handle = osThreadNew(Start_ICM45686, NULL, &Task_ICM45686_attributes); 80048dc: 4a15 ldr r2, [pc, #84] @ (8004934 ) 80048de: 2100 movs r1, #0 80048e0: 4815 ldr r0, [pc, #84] @ (8004938 ) 80048e2: f00f f839 bl 8013958 80048e6: 4603 mov r3, r0 80048e8: 4a14 ldr r2, [pc, #80] @ (800493c ) 80048ea: 6013 str r3, [r2, #0] /* creation of Task_BMM350 */ Task_BMM350Handle = osThreadNew(Start_BMM350, NULL, &Task_BMM350_attributes); 80048ec: 4a14 ldr r2, [pc, #80] @ (8004940 ) 80048ee: 2100 movs r1, #0 80048f0: 4814 ldr r0, [pc, #80] @ (8004944 ) 80048f2: f00f f831 bl 8013958 80048f6: 4603 mov r3, r0 80048f8: 4a13 ldr r2, [pc, #76] @ (8004948 ) 80048fa: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ while(LL_HSEM_1StepLock(HSEM, CFG_HW_CLK48_CONFIG_SEMID)); 80048fc: bf00 nop 80048fe: 2105 movs r1, #5 8004900: 4812 ldr r0, [pc, #72] @ (800494c ) 8004902: f7ff ff7f bl 8004804 8004906: 4603 mov r3, r0 8004908: 2b00 cmp r3, #0 800490a: d1f8 bne.n 80048fe /* Init code for STM32_WPAN */ MX_APPE_Init(); 800490c: f7fd fd3a bl 8002384 /* Start scheduler */ osKernelStart(); 8004910: f00e fff8 bl 8013904 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8004914: bf00 nop 8004916: e7fd b.n 8004914 8004918: 0801e51c .word 0x0801e51c 800491c: 20000708 .word 0x20000708 8004920: 0801e534 .word 0x0801e534 8004924: 2000070c .word 0x2000070c 8004928: 0801e4b0 .word 0x0801e4b0 800492c: 08004e9d .word 0x08004e9d 8004930: 200006fc .word 0x200006fc 8004934: 0801e4d4 .word 0x0801e4d4 8004938: 08004f75 .word 0x08004f75 800493c: 20000700 .word 0x20000700 8004940: 0801e4f8 .word 0x0801e4f8 8004944: 08005285 .word 0x08005285 8004948: 20000704 .word 0x20000704 800494c: 58001400 .word 0x58001400 08004950 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8004950: b580 push {r7, lr} 8004952: b09a sub sp, #104 @ 0x68 8004954: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8004956: f107 0320 add.w r3, r7, #32 800495a: 2248 movs r2, #72 @ 0x48 800495c: 2100 movs r1, #0 800495e: 4618 mov r0, r3 8004960: f015 fcc0 bl 801a2e4 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8004964: 1d3b adds r3, r7, #4 8004966: 2200 movs r2, #0 8004968: 601a str r2, [r3, #0] 800496a: 605a str r2, [r3, #4] 800496c: 609a str r2, [r3, #8] 800496e: 60da str r2, [r3, #12] 8004970: 611a str r2, [r3, #16] 8004972: 615a str r2, [r3, #20] 8004974: 619a str r2, [r3, #24] /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); 8004976: f006 fad5 bl 800af24 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); 800497a: 2010 movs r0, #16 800497c: f7ff fefa bl 8004774 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8004980: 4b2d ldr r3, [pc, #180] @ (8004a38 ) 8004982: 681b ldr r3, [r3, #0] 8004984: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8004988: 4a2b ldr r2, [pc, #172] @ (8004a38 ) 800498a: f443 7300 orr.w r3, r3, #512 @ 0x200 800498e: 6013 str r3, [r2, #0] 8004990: 4b29 ldr r3, [pc, #164] @ (8004a38 ) 8004992: 681b ldr r3, [r3, #0] 8004994: f403 63c0 and.w r3, r3, #1536 @ 0x600 8004998: 603b str r3, [r7, #0] 800499a: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI1 800499c: 232f movs r3, #47 @ 0x2f 800499e: 623b str r3, [r7, #32] |RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE |RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80049a0: f44f 3380 mov.w r3, #65536 @ 0x10000 80049a4: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 80049a6: 2301 movs r3, #1 80049a8: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 80049aa: f44f 7380 mov.w r3, #256 @ 0x100 80049ae: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.MSIState = RCC_MSI_ON; 80049b0: 2301 movs r3, #1 80049b2: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 80049b4: 2340 movs r3, #64 @ 0x40 80049b6: 633b str r3, [r7, #48] @ 0x30 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; 80049b8: 2300 movs r3, #0 80049ba: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; 80049bc: 2360 movs r3, #96 @ 0x60 80049be: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 80049c0: 2305 movs r3, #5 80049c2: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80049c4: 2302 movs r3, #2 80049c6: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; 80049c8: 2301 movs r3, #1 80049ca: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; 80049cc: 2300 movs r3, #0 80049ce: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLN = 32; 80049d0: 2320 movs r3, #32 80049d2: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 80049d4: f44f 3300 mov.w r3, #131072 @ 0x20000 80049d8: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 80049da: f04f 5300 mov.w r3, #536870912 @ 0x20000000 80049de: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 80049e0: f04f 7300 mov.w r3, #33554432 @ 0x2000000 80049e4: 663b str r3, [r7, #96] @ 0x60 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80049e6: f107 0320 add.w r3, r7, #32 80049ea: 4618 mov r0, r3 80049ec: f006 fe4a bl 800b684 80049f0: 4603 mov r3, r0 80049f2: 2b00 cmp r3, #0 80049f4: d001 beq.n 80049fa { Error_Handler(); 80049f6: f000 fcbb bl 8005370 } /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2 80049fa: 236f movs r3, #111 @ 0x6f 80049fc: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80049fe: 2303 movs r3, #3 8004a00: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8004a02: 2300 movs r3, #0 8004a04: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8004a06: 2300 movs r3, #0 8004a08: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8004a0a: 2300 movs r3, #0 8004a0c: 617b str r3, [r7, #20] RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2; 8004a0e: 2380 movs r3, #128 @ 0x80 8004a10: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; 8004a12: 2300 movs r3, #0 8004a14: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) 8004a16: 1d3b adds r3, r7, #4 8004a18: 2103 movs r1, #3 8004a1a: 4618 mov r0, r3 8004a1c: f007 f9a6 bl 800bd6c 8004a20: 4603 mov r3, r0 8004a22: 2b00 cmp r3, #0 8004a24: d001 beq.n 8004a2a { Error_Handler(); 8004a26: f000 fca3 bl 8005370 } /** Enable MSI Auto calibration */ HAL_RCCEx_EnableMSIPLLMode(); 8004a2a: f007 ff7d bl 800c928 } 8004a2e: bf00 nop 8004a30: 3768 adds r7, #104 @ 0x68 8004a32: 46bd mov sp, r7 8004a34: bd80 pop {r7, pc} 8004a36: bf00 nop 8004a38: 58000400 .word 0x58000400 08004a3c : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 8004a3c: b580 push {r7, lr} 8004a3e: b094 sub sp, #80 @ 0x50 8004a40: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8004a42: 463b mov r3, r7 8004a44: 2250 movs r2, #80 @ 0x50 8004a46: 2100 movs r1, #0 8004a48: 4618 mov r0, r3 8004a4a: f015 fc4b bl 801a2e4 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP; 8004a4e: f44f 5340 mov.w r3, #12288 @ 0x3000 8004a52: 603b str r3, [r7, #0] PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_HSE_DIV1024; 8004a54: f44f 4340 mov.w r3, #49152 @ 0xc000 8004a58: 647b str r3, [r7, #68] @ 0x44 PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI; 8004a5a: 2300 movs r3, #0 8004a5c: 64bb str r3, [r7, #72] @ 0x48 PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1; 8004a5e: 2310 movs r3, #16 8004a60: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8004a62: 463b mov r3, r7 8004a64: 4618 mov r0, r3 8004a66: f007 fde9 bl 800c63c 8004a6a: 4603 mov r3, r0 8004a6c: 2b00 cmp r3, #0 8004a6e: d001 beq.n 8004a74 { Error_Handler(); 8004a70: f000 fc7e bl 8005370 } /* USER CODE BEGIN Smps */ /* USER CODE END Smps */ } 8004a74: bf00 nop 8004a76: 3750 adds r7, #80 @ 0x50 8004a78: 46bd mov sp, r7 8004a7a: bd80 pop {r7, pc} 08004a7c : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_Init(void) { 8004a7c: b580 push {r7, lr} 8004a7e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8004a80: 4b1b ldr r3, [pc, #108] @ (8004af0 ) 8004a82: 4a1c ldr r2, [pc, #112] @ (8004af4 ) 8004a84: 601a str r2, [r3, #0] hi2c1.Init.Timing = 0x00C12166; 8004a86: 4b1a ldr r3, [pc, #104] @ (8004af0 ) 8004a88: 4a1b ldr r2, [pc, #108] @ (8004af8 ) 8004a8a: 605a str r2, [r3, #4] hi2c1.Init.OwnAddress1 = 0; 8004a8c: 4b18 ldr r3, [pc, #96] @ (8004af0 ) 8004a8e: 2200 movs r2, #0 8004a90: 609a str r2, [r3, #8] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8004a92: 4b17 ldr r3, [pc, #92] @ (8004af0 ) 8004a94: 2201 movs r2, #1 8004a96: 60da str r2, [r3, #12] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8004a98: 4b15 ldr r3, [pc, #84] @ (8004af0 ) 8004a9a: 2200 movs r2, #0 8004a9c: 611a str r2, [r3, #16] hi2c1.Init.OwnAddress2 = 0; 8004a9e: 4b14 ldr r3, [pc, #80] @ (8004af0 ) 8004aa0: 2200 movs r2, #0 8004aa2: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 8004aa4: 4b12 ldr r3, [pc, #72] @ (8004af0 ) 8004aa6: 2200 movs r2, #0 8004aa8: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8004aaa: 4b11 ldr r3, [pc, #68] @ (8004af0 ) 8004aac: 2200 movs r2, #0 8004aae: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8004ab0: 4b0f ldr r3, [pc, #60] @ (8004af0 ) 8004ab2: 2200 movs r2, #0 8004ab4: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8004ab6: 480e ldr r0, [pc, #56] @ (8004af0 ) 8004ab8: f002 fdd0 bl 800765c 8004abc: 4603 mov r3, r0 8004abe: 2b00 cmp r3, #0 8004ac0: d001 beq.n 8004ac6 { Error_Handler(); 8004ac2: f000 fc55 bl 8005370 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8004ac6: 2100 movs r1, #0 8004ac8: 4809 ldr r0, [pc, #36] @ (8004af0 ) 8004aca: f004 fbcb bl 8009264 8004ace: 4603 mov r3, r0 8004ad0: 2b00 cmp r3, #0 8004ad2: d001 beq.n 8004ad8 { Error_Handler(); 8004ad4: f000 fc4c bl 8005370 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 8004ad8: 2100 movs r1, #0 8004ada: 4805 ldr r0, [pc, #20] @ (8004af0 ) 8004adc: f004 fc0d bl 80092fa 8004ae0: 4603 mov r3, r0 8004ae2: 2b00 cmp r3, #0 8004ae4: d001 beq.n 8004aea { Error_Handler(); 8004ae6: f000 fc43 bl 8005370 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8004aea: bf00 nop 8004aec: bd80 pop {r7, pc} 8004aee: bf00 nop 8004af0: 200003b4 .word 0x200003b4 8004af4: 40005400 .word 0x40005400 8004af8: 00c12166 .word 0x00c12166 08004afc : * @brief IPCC Initialization Function * @param None * @retval None */ static void MX_IPCC_Init(void) { 8004afc: b580 push {r7, lr} 8004afe: af00 add r7, sp, #0 /* USER CODE END IPCC_Init 0 */ /* USER CODE BEGIN IPCC_Init 1 */ /* USER CODE END IPCC_Init 1 */ hipcc.Instance = IPCC; 8004b00: 4b06 ldr r3, [pc, #24] @ (8004b1c ) 8004b02: 4a07 ldr r2, [pc, #28] @ (8004b20 ) 8004b04: 601a str r2, [r3, #0] if (HAL_IPCC_Init(&hipcc) != HAL_OK) 8004b06: 4805 ldr r0, [pc, #20] @ (8004b1c ) 8004b08: f004 fc44 bl 8009394 8004b0c: 4603 mov r3, r0 8004b0e: 2b00 cmp r3, #0 8004b10: d001 beq.n 8004b16 { Error_Handler(); 8004b12: f000 fc2d bl 8005370 } /* USER CODE BEGIN IPCC_Init 2 */ /* USER CODE END IPCC_Init 2 */ } 8004b16: bf00 nop 8004b18: bd80 pop {r7, pc} 8004b1a: bf00 nop 8004b1c: 200004c8 .word 0x200004c8 8004b20: 58000c00 .word 0x58000c00 08004b24 : * @brief RF Initialization Function * @param None * @retval None */ static void MX_RF_Init(void) { 8004b24: b480 push {r7} 8004b26: af00 add r7, sp, #0 /* USER CODE END RF_Init 1 */ /* USER CODE BEGIN RF_Init 2 */ /* USER CODE END RF_Init 2 */ } 8004b28: bf00 nop 8004b2a: 46bd mov sp, r7 8004b2c: f85d 7b04 ldr.w r7, [sp], #4 8004b30: 4770 bx lr ... 08004b34 : * @brief RTC Initialization Function * @param None * @retval None */ static void MX_RTC_Init(void) { 8004b34: b580 push {r7, lr} 8004b36: af00 add r7, sp, #0 /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 8004b38: 4b16 ldr r3, [pc, #88] @ (8004b94 ) 8004b3a: 4a17 ldr r2, [pc, #92] @ (8004b98 ) 8004b3c: 601a str r2, [r3, #0] hrtc.Init.HourFormat = RTC_HOURFORMAT_24; 8004b3e: 4b15 ldr r3, [pc, #84] @ (8004b94 ) 8004b40: 2200 movs r2, #0 8004b42: 605a str r2, [r3, #4] hrtc.Init.AsynchPrediv = CFG_RTC_ASYNCH_PRESCALER; 8004b44: 4b13 ldr r3, [pc, #76] @ (8004b94 ) 8004b46: 220f movs r2, #15 8004b48: 609a str r2, [r3, #8] hrtc.Init.SynchPrediv = CFG_RTC_SYNCH_PRESCALER; 8004b4a: 4b12 ldr r3, [pc, #72] @ (8004b94 ) 8004b4c: f647 72ff movw r2, #32767 @ 0x7fff 8004b50: 60da str r2, [r3, #12] hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; 8004b52: 4b10 ldr r3, [pc, #64] @ (8004b94 ) 8004b54: 2200 movs r2, #0 8004b56: 611a str r2, [r3, #16] hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; 8004b58: 4b0e ldr r3, [pc, #56] @ (8004b94 ) 8004b5a: 2200 movs r2, #0 8004b5c: 619a str r2, [r3, #24] hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; 8004b5e: 4b0d ldr r3, [pc, #52] @ (8004b94 ) 8004b60: 2200 movs r2, #0 8004b62: 61da str r2, [r3, #28] hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; 8004b64: 4b0b ldr r3, [pc, #44] @ (8004b94 ) 8004b66: 2200 movs r2, #0 8004b68: 615a str r2, [r3, #20] if (HAL_RTC_Init(&hrtc) != HAL_OK) 8004b6a: 480a ldr r0, [pc, #40] @ (8004b94 ) 8004b6c: f007 fff3 bl 800cb56 8004b70: 4603 mov r3, r0 8004b72: 2b00 cmp r3, #0 8004b74: d001 beq.n 8004b7a { Error_Handler(); 8004b76: f000 fbfb bl 8005370 } /** Enable the WakeUp */ if (HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 0, RTC_WAKEUPCLOCK_RTCCLK_DIV16) != HAL_OK) 8004b7a: 2200 movs r2, #0 8004b7c: 2100 movs r1, #0 8004b7e: 4805 ldr r0, [pc, #20] @ (8004b94 ) 8004b80: f008 f8f6 bl 800cd70 8004b84: 4603 mov r3, r0 8004b86: 2b00 cmp r3, #0 8004b88: d001 beq.n 8004b8e { Error_Handler(); 8004b8a: f000 fbf1 bl 8005370 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 8004b8e: bf00 nop 8004b90: bd80 pop {r7, pc} 8004b92: bf00 nop 8004b94: 20000504 .word 0x20000504 8004b98: 40002800 .word 0x40002800 08004b9c : * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 8004b9c: b580 push {r7, lr} 8004b9e: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; 8004ba0: 4b1b ldr r3, [pc, #108] @ (8004c10 ) 8004ba2: 4a1c ldr r2, [pc, #112] @ (8004c14 ) 8004ba4: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 8004ba6: 4b1a ldr r3, [pc, #104] @ (8004c10 ) 8004ba8: f44f 7282 mov.w r2, #260 @ 0x104 8004bac: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 8004bae: 4b18 ldr r3, [pc, #96] @ (8004c10 ) 8004bb0: 2200 movs r2, #0 8004bb2: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 8004bb4: 4b16 ldr r3, [pc, #88] @ (8004c10 ) 8004bb6: f44f 62e0 mov.w r2, #1792 @ 0x700 8004bba: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH; 8004bbc: 4b14 ldr r3, [pc, #80] @ (8004c10 ) 8004bbe: 2202 movs r2, #2 8004bc0: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_2EDGE; 8004bc2: 4b13 ldr r3, [pc, #76] @ (8004c10 ) 8004bc4: 2201 movs r2, #1 8004bc6: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_SOFT; 8004bc8: 4b11 ldr r3, [pc, #68] @ (8004c10 ) 8004bca: f44f 7200 mov.w r2, #512 @ 0x200 8004bce: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; 8004bd0: 4b0f ldr r3, [pc, #60] @ (8004c10 ) 8004bd2: 2208 movs r2, #8 8004bd4: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 8004bd6: 4b0e ldr r3, [pc, #56] @ (8004c10 ) 8004bd8: 2200 movs r2, #0 8004bda: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 8004bdc: 4b0c ldr r3, [pc, #48] @ (8004c10 ) 8004bde: 2200 movs r2, #0 8004be0: 625a str r2, [r3, #36] @ 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8004be2: 4b0b ldr r3, [pc, #44] @ (8004c10 ) 8004be4: 2200 movs r2, #0 8004be6: 629a str r2, [r3, #40] @ 0x28 hspi1.Init.CRCPolynomial = 7; 8004be8: 4b09 ldr r3, [pc, #36] @ (8004c10 ) 8004bea: 2207 movs r2, #7 8004bec: 62da str r2, [r3, #44] @ 0x2c hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 8004bee: 4b08 ldr r3, [pc, #32] @ (8004c10 ) 8004bf0: 2200 movs r2, #0 8004bf2: 631a str r2, [r3, #48] @ 0x30 hspi1.Init.NSSPMode = SPI_NSS_PULSE_DISABLE; 8004bf4: 4b06 ldr r3, [pc, #24] @ (8004c10 ) 8004bf6: 2200 movs r2, #0 8004bf8: 635a str r2, [r3, #52] @ 0x34 if (HAL_SPI_Init(&hspi1) != HAL_OK) 8004bfa: 4805 ldr r0, [pc, #20] @ (8004c10 ) 8004bfc: f008 f984 bl 800cf08 8004c00: 4603 mov r3, r0 8004c02: 2b00 cmp r3, #0 8004c04: d001 beq.n 8004c0a { Error_Handler(); 8004c06: f000 fbb3 bl 8005370 } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 8004c0a: bf00 nop 8004c0c: bd80 pop {r7, pc} 8004c0e: bf00 nop 8004c10: 20000528 .word 0x20000528 8004c14: 40013000 .word 0x40013000 08004c18 : * @brief SPI2 Initialization Function * @param None * @retval None */ static void MX_SPI2_Init(void) { 8004c18: b580 push {r7, lr} 8004c1a: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_Init 1 */ /* USER CODE END SPI2_Init 1 */ /* SPI2 parameter configuration*/ hspi2.Instance = SPI2; 8004c1c: 4b1b ldr r3, [pc, #108] @ (8004c8c ) 8004c1e: 4a1c ldr r2, [pc, #112] @ (8004c90 ) 8004c20: 601a str r2, [r3, #0] hspi2.Init.Mode = SPI_MODE_MASTER; 8004c22: 4b1a ldr r3, [pc, #104] @ (8004c8c ) 8004c24: f44f 7282 mov.w r2, #260 @ 0x104 8004c28: 605a str r2, [r3, #4] hspi2.Init.Direction = SPI_DIRECTION_2LINES; 8004c2a: 4b18 ldr r3, [pc, #96] @ (8004c8c ) 8004c2c: 2200 movs r2, #0 8004c2e: 609a str r2, [r3, #8] hspi2.Init.DataSize = SPI_DATASIZE_4BIT; 8004c30: 4b16 ldr r3, [pc, #88] @ (8004c8c ) 8004c32: f44f 7240 mov.w r2, #768 @ 0x300 8004c36: 60da str r2, [r3, #12] hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 8004c38: 4b14 ldr r3, [pc, #80] @ (8004c8c ) 8004c3a: 2200 movs r2, #0 8004c3c: 611a str r2, [r3, #16] hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 8004c3e: 4b13 ldr r3, [pc, #76] @ (8004c8c ) 8004c40: 2200 movs r2, #0 8004c42: 615a str r2, [r3, #20] hspi2.Init.NSS = SPI_NSS_SOFT; 8004c44: 4b11 ldr r3, [pc, #68] @ (8004c8c ) 8004c46: f44f 7200 mov.w r2, #512 @ 0x200 8004c4a: 619a str r2, [r3, #24] hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8004c4c: 4b0f ldr r3, [pc, #60] @ (8004c8c ) 8004c4e: 2200 movs r2, #0 8004c50: 61da str r2, [r3, #28] hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 8004c52: 4b0e ldr r3, [pc, #56] @ (8004c8c ) 8004c54: 2200 movs r2, #0 8004c56: 621a str r2, [r3, #32] hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 8004c58: 4b0c ldr r3, [pc, #48] @ (8004c8c ) 8004c5a: 2200 movs r2, #0 8004c5c: 625a str r2, [r3, #36] @ 0x24 hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8004c5e: 4b0b ldr r3, [pc, #44] @ (8004c8c ) 8004c60: 2200 movs r2, #0 8004c62: 629a str r2, [r3, #40] @ 0x28 hspi2.Init.CRCPolynomial = 7; 8004c64: 4b09 ldr r3, [pc, #36] @ (8004c8c ) 8004c66: 2207 movs r2, #7 8004c68: 62da str r2, [r3, #44] @ 0x2c hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 8004c6a: 4b08 ldr r3, [pc, #32] @ (8004c8c ) 8004c6c: 2200 movs r2, #0 8004c6e: 631a str r2, [r3, #48] @ 0x30 hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 8004c70: 4b06 ldr r3, [pc, #24] @ (8004c8c ) 8004c72: 2208 movs r2, #8 8004c74: 635a str r2, [r3, #52] @ 0x34 if (HAL_SPI_Init(&hspi2) != HAL_OK) 8004c76: 4805 ldr r0, [pc, #20] @ (8004c8c ) 8004c78: f008 f946 bl 800cf08 8004c7c: 4603 mov r3, r0 8004c7e: 2b00 cmp r3, #0 8004c80: d001 beq.n 8004c86 { Error_Handler(); 8004c82: f000 fb75 bl 8005370 } /* USER CODE BEGIN SPI2_Init 2 */ /* USER CODE END SPI2_Init 2 */ } 8004c86: bf00 nop 8004c88: bd80 pop {r7, pc} 8004c8a: bf00 nop 8004c8c: 2000058c .word 0x2000058c 8004c90: 40003800 .word 0x40003800 08004c94 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 8004c94: b580 push {r7, lr} 8004c96: b08a sub sp, #40 @ 0x28 8004c98: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8004c9a: f107 031c add.w r3, r7, #28 8004c9e: 2200 movs r2, #0 8004ca0: 601a str r2, [r3, #0] 8004ca2: 605a str r2, [r3, #4] 8004ca4: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8004ca6: 463b mov r3, r7 8004ca8: 2200 movs r2, #0 8004caa: 601a str r2, [r3, #0] 8004cac: 605a str r2, [r3, #4] 8004cae: 609a str r2, [r3, #8] 8004cb0: 60da str r2, [r3, #12] 8004cb2: 611a str r2, [r3, #16] 8004cb4: 615a str r2, [r3, #20] 8004cb6: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8004cb8: 4b2d ldr r3, [pc, #180] @ (8004d70 ) 8004cba: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8004cbe: 601a str r2, [r3, #0] htim2.Init.Prescaler = 63; 8004cc0: 4b2b ldr r3, [pc, #172] @ (8004d70 ) 8004cc2: 223f movs r2, #63 @ 0x3f 8004cc4: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8004cc6: 4b2a ldr r3, [pc, #168] @ (8004d70 ) 8004cc8: 2200 movs r2, #0 8004cca: 609a str r2, [r3, #8] htim2.Init.Period = 999; 8004ccc: 4b28 ldr r3, [pc, #160] @ (8004d70 ) 8004cce: f240 32e7 movw r2, #999 @ 0x3e7 8004cd2: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8004cd4: 4b26 ldr r3, [pc, #152] @ (8004d70 ) 8004cd6: 2200 movs r2, #0 8004cd8: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8004cda: 4b25 ldr r3, [pc, #148] @ (8004d70 ) 8004cdc: 2200 movs r2, #0 8004cde: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 8004ce0: 4823 ldr r0, [pc, #140] @ (8004d70 ) 8004ce2: f009 fc5d bl 800e5a0 8004ce6: 4603 mov r3, r0 8004ce8: 2b00 cmp r3, #0 8004cea: d001 beq.n 8004cf0 { Error_Handler(); 8004cec: f000 fb40 bl 8005370 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8004cf0: 2300 movs r3, #0 8004cf2: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8004cf4: 2300 movs r3, #0 8004cf6: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8004cf8: f107 031c add.w r3, r7, #28 8004cfc: 4619 mov r1, r3 8004cfe: 481c ldr r0, [pc, #112] @ (8004d70 ) 8004d00: f00a f9d6 bl 800f0b0 8004d04: 4603 mov r3, r0 8004d06: 2b00 cmp r3, #0 8004d08: d001 beq.n 8004d0e { Error_Handler(); 8004d0a: f000 fb31 bl 8005370 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8004d0e: 2360 movs r3, #96 @ 0x60 8004d10: 603b str r3, [r7, #0] sConfigOC.Pulse = 0; 8004d12: 2300 movs r3, #0 8004d14: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8004d16: 2300 movs r3, #0 8004d18: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8004d1a: 2300 movs r3, #0 8004d1c: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8004d1e: 463b mov r3, r7 8004d20: 2200 movs r2, #0 8004d22: 4619 mov r1, r3 8004d24: 4812 ldr r0, [pc, #72] @ (8004d70 ) 8004d26: f009 fd99 bl 800e85c 8004d2a: 4603 mov r3, r0 8004d2c: 2b00 cmp r3, #0 8004d2e: d001 beq.n 8004d34 { Error_Handler(); 8004d30: f000 fb1e bl 8005370 } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8004d34: 463b mov r3, r7 8004d36: 2204 movs r2, #4 8004d38: 4619 mov r1, r3 8004d3a: 480d ldr r0, [pc, #52] @ (8004d70 ) 8004d3c: f009 fd8e bl 800e85c 8004d40: 4603 mov r3, r0 8004d42: 2b00 cmp r3, #0 8004d44: d001 beq.n 8004d4a { Error_Handler(); 8004d46: f000 fb13 bl 8005370 } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8004d4a: 463b mov r3, r7 8004d4c: 2208 movs r2, #8 8004d4e: 4619 mov r1, r3 8004d50: 4807 ldr r0, [pc, #28] @ (8004d70 ) 8004d52: f009 fd83 bl 800e85c 8004d56: 4603 mov r3, r0 8004d58: 2b00 cmp r3, #0 8004d5a: d001 beq.n 8004d60 { Error_Handler(); 8004d5c: f000 fb08 bl 8005370 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 8004d60: 4803 ldr r0, [pc, #12] @ (8004d70 ) 8004d62: f001 fb4b bl 80063fc } 8004d66: bf00 nop 8004d68: 3728 adds r7, #40 @ 0x28 8004d6a: 46bd mov sp, r7 8004d6c: bd80 pop {r7, pc} 8004d6e: bf00 nop 8004d70: 200006b0 .word 0x200006b0 08004d74 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8004d74: b580 push {r7, lr} 8004d76: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); 8004d78: 2004 movs r0, #4 8004d7a: f7ff fd11 bl 80047a0 __HAL_RCC_DMA1_CLK_ENABLE(); 8004d7e: 2001 movs r0, #1 8004d80: f7ff fd0e bl 80047a0 /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0); 8004d84: 2200 movs r2, #0 8004d86: 2105 movs r1, #5 8004d88: 200b movs r0, #11 8004d8a: f001 ff11 bl 8006bb0 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8004d8e: 200b movs r0, #11 8004d90: f001 ff28 bl 8006be4 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 5, 0); 8004d94: 2200 movs r2, #0 8004d96: 2105 movs r1, #5 8004d98: 200c movs r0, #12 8004d9a: f001 ff09 bl 8006bb0 HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 8004d9e: 200c movs r0, #12 8004da0: f001 ff20 bl 8006be4 /* DMA1_Channel3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 5, 0); 8004da4: 2200 movs r2, #0 8004da6: 2105 movs r1, #5 8004da8: 200d movs r0, #13 8004daa: f001 ff01 bl 8006bb0 HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); 8004dae: 200d movs r0, #13 8004db0: f001 ff18 bl 8006be4 /* DMA1_Channel4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 5, 0); 8004db4: 2200 movs r2, #0 8004db6: 2105 movs r1, #5 8004db8: 200e movs r0, #14 8004dba: f001 fef9 bl 8006bb0 HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn); 8004dbe: 200e movs r0, #14 8004dc0: f001 ff10 bl 8006be4 } 8004dc4: bf00 nop 8004dc6: bd80 pop {r7, pc} 08004dc8 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8004dc8: b580 push {r7, lr} 8004dca: b086 sub sp, #24 8004dcc: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004dce: 1d3b adds r3, r7, #4 8004dd0: 2200 movs r2, #0 8004dd2: 601a str r2, [r3, #0] 8004dd4: 605a str r2, [r3, #4] 8004dd6: 609a str r2, [r3, #8] 8004dd8: 60da str r2, [r3, #12] 8004dda: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8004ddc: 2004 movs r0, #4 8004dde: f7ff fcf8 bl 80047d2 __HAL_RCC_GPIOB_CLK_ENABLE(); 8004de2: 2002 movs r0, #2 8004de4: f7ff fcf5 bl 80047d2 __HAL_RCC_GPIOA_CLK_ENABLE(); 8004de8: 2001 movs r0, #1 8004dea: f7ff fcf2 bl 80047d2 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIO_SPI1_IMU_CS_GPIO_Port, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); 8004dee: 2201 movs r2, #1 8004df0: 2108 movs r1, #8 8004df2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8004df6: f002 fbdd bl 80075b4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_SPI2_SD_CD_Pin|GPIO_SPI2_SD_CS_Pin, GPIO_PIN_SET); 8004dfa: 2201 movs r2, #1 8004dfc: 2160 movs r1, #96 @ 0x60 8004dfe: 4826 ldr r0, [pc, #152] @ (8004e98 ) 8004e00: f002 fbd8 bl 80075b4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIO_SD_LDO_EN_GPIO_Port, GPIO_SD_LDO_EN_Pin, GPIO_PIN_RESET); 8004e04: 2200 movs r2, #0 8004e06: f44f 5180 mov.w r1, #4096 @ 0x1000 8004e0a: 4823 ldr r0, [pc, #140] @ (8004e98 ) 8004e0c: f002 fbd2 bl 80075b4 /*Configure GPIO pin : GPIO_SPI1_IMU_CS_Pin */ GPIO_InitStruct.Pin = GPIO_SPI1_IMU_CS_Pin; 8004e10: 2308 movs r3, #8 8004e12: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8004e14: 2301 movs r3, #1 8004e16: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004e18: 2300 movs r3, #0 8004e1a: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8004e1c: 2303 movs r3, #3 8004e1e: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIO_SPI1_IMU_CS_GPIO_Port, &GPIO_InitStruct); 8004e20: 1d3b adds r3, r7, #4 8004e22: 4619 mov r1, r3 8004e24: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8004e28: f002 fa54 bl 80072d4 /*Configure GPIO pins : GPIO_SPI2_SD_CD_Pin GPIO_SPI2_SD_CS_Pin GPIO_SD_LDO_EN_Pin */ GPIO_InitStruct.Pin = GPIO_SPI2_SD_CD_Pin|GPIO_SPI2_SD_CS_Pin|GPIO_SD_LDO_EN_Pin; 8004e2c: f44f 5383 mov.w r3, #4192 @ 0x1060 8004e30: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8004e32: 2301 movs r3, #1 8004e34: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004e36: 2300 movs r3, #0 8004e38: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8004e3a: 2303 movs r3, #3 8004e3c: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8004e3e: 1d3b adds r3, r7, #4 8004e40: 4619 mov r1, r3 8004e42: 4815 ldr r0, [pc, #84] @ (8004e98 ) 8004e44: f002 fa46 bl 80072d4 /*Configure GPIO pin : GPIO_IMU_INT_Pin */ GPIO_InitStruct.Pin = GPIO_IMU_INT_Pin; 8004e48: f44f 6380 mov.w r3, #1024 @ 0x400 8004e4c: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8004e4e: f44f 1388 mov.w r3, #1114112 @ 0x110000 8004e52: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004e54: 2300 movs r3, #0 8004e56: 60fb str r3, [r7, #12] HAL_GPIO_Init(GPIO_IMU_INT_GPIO_Port, &GPIO_InitStruct); 8004e58: 1d3b adds r3, r7, #4 8004e5a: 4619 mov r1, r3 8004e5c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8004e60: f002 fa38 bl 80072d4 /*Configure GPIO pin : GPIO_MAGN_INT_Pin */ GPIO_InitStruct.Pin = GPIO_MAGN_INT_Pin; 8004e64: f44f 6300 mov.w r3, #2048 @ 0x800 8004e68: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8004e6a: f44f 1388 mov.w r3, #1114112 @ 0x110000 8004e6e: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004e70: 2300 movs r3, #0 8004e72: 60fb str r3, [r7, #12] HAL_GPIO_Init(GPIO_MAGN_INT_GPIO_Port, &GPIO_InitStruct); 8004e74: 1d3b adds r3, r7, #4 8004e76: 4619 mov r1, r3 8004e78: 4807 ldr r0, [pc, #28] @ (8004e98 ) 8004e7a: f002 fa2b bl 80072d4 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 8004e7e: 2200 movs r2, #0 8004e80: 2105 movs r1, #5 8004e82: 2028 movs r0, #40 @ 0x28 8004e84: f001 fe94 bl 8006bb0 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8004e88: 2028 movs r0, #40 @ 0x28 8004e8a: f001 feab bl 8006be4 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8004e8e: bf00 nop 8004e90: 3718 adds r7, #24 8004e92: 46bd mov sp, r7 8004e94: bd80 pop {r7, pc} 8004e96: bf00 nop 8004e98: 48000800 .word 0x48000800 08004e9c : * @param argument: Not used * @retval None */ /* USER CODE END Header_Start_DataAnalysis */ void Start_DataAnalysis(void *argument) { 8004e9c: b580 push {r7, lr} 8004e9e: b092 sub sp, #72 @ 0x48 8004ea0: af00 add r7, sp, #0 8004ea2: 6078 str r0, [r7, #4] /* init code for USB_Device */ MX_USB_Device_Init(); 8004ea4: f013 fcd8 bl 8018858 // char output_buffer[128]; ICM45686_Data imu_data; struct bmm350_mag_temp_data magn_data; // struct bmm350_raw_mag_data magn_data; QuaternionData Quat_Dat; Quat_Dat.StartByte = PACKET_START_BYTE; 8004ea8: 23de movs r3, #222 @ 0xde 8004eaa: 723b strb r3, [r7, #8] Quat_Dat.SensorAddress = BMM350_I2C_ADSEL_SET_LOW; 8004eac: 2314 movs r3, #20 8004eae: 727b strb r3, [r7, #9] Quat_Dat.EndByte = PACKET_END_BYTE; 8004eb0: 23ad movs r3, #173 @ 0xad 8004eb2: 76bb strb r3, [r7, #26] MadgwickAHRS_init(&IMUQuat, 0.1f, 400.0f); 8004eb4: eddf 0a2a vldr s1, [pc, #168] @ 8004f60 8004eb8: ed9f 0a2a vldr s0, [pc, #168] @ 8004f64 8004ebc: 482a ldr r0, [pc, #168] @ (8004f68 ) 8004ebe: f7fb fef1 bl 8000ca4 // Don't feed Madgwick at 6.4 kHz. A 9-DOF update at that rate is expensive // on an STM32WB, and a USB packet per sample can't keep up anyway. Average // 16 samples in the IMU task to get 400 Hz, which also acts as a free low-pass // filter. Let the IMU be the fusion clock and read the mag non-blocking. // osMessageQueueGet(Q_BMMHandle, &magn_data, NULL, osWaitForever); 8004ec2: 4b2a ldr r3, [pc, #168] @ (8004f6c ) 8004ec4: 6818 ldr r0, [r3, #0] 8004ec6: f107 011c add.w r1, r7, #28 8004eca: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8004ece: 2200 movs r2, #0 8004ed0: f00f f9ae bl 8014230 osMessageQueueGet(Q_ICMHandle, &imu_data, NULL, osWaitForever); 8004ed4: 4b26 ldr r3, [pc, #152] @ (8004f70 ) 8004ed6: 6818 ldr r0, [r3, #0] 8004ed8: f107 012c add.w r1, r7, #44 @ 0x2c 8004edc: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8004ee0: 2200 movs r2, #0 8004ee2: f00f f9a5 bl 8014230 // imu_data.processed_imu_data[0], imu_data.processed_imu_data[1], imu_data.processed_imu_data[2], // ax, ay, yz // magn_data.x, magn_data.y, magn_data.z); // mx, my, mz // This code has the magnetometer axis rotated by 180 degrees relative to the IMU // because the axis are different. IMU xy-coordinate system and magnetometer yx-coordinate system MadgwickAHRS_update(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz 8004ee6: ed97 7a0e vldr s14, [r7, #56] @ 0x38 8004eea: edd7 6a0f vldr s13, [r7, #60] @ 0x3c 8004eee: ed97 6a10 vldr s12, [r7, #64] @ 0x40 8004ef2: edd7 5a0b vldr s11, [r7, #44] @ 0x2c 8004ef6: ed97 5a0c vldr s10, [r7, #48] @ 0x30 8004efa: edd7 4a0d vldr s9, [r7, #52] @ 0x34 8004efe: ed97 3a08 vldr s6, [r7, #32] 8004f02: edd7 3a07 vldr s7, [r7, #28] imu_data.processed_imu_data[0], imu_data.processed_imu_data[1], imu_data.processed_imu_data[2], // ax, ay, yz magn_data.y, magn_data.x, -magn_data.z); // mx, my, mz 8004f06: edd7 7a09 vldr s15, [r7, #36] @ 0x24 MadgwickAHRS_update(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz 8004f0a: eef1 7a67 vneg.f32 s15, s15 8004f0e: eeb0 4a67 vmov.f32 s8, s15 8004f12: eef0 2a64 vmov.f32 s5, s9 8004f16: eeb0 2a45 vmov.f32 s4, s10 8004f1a: eef0 1a65 vmov.f32 s3, s11 8004f1e: eeb0 1a46 vmov.f32 s2, s12 8004f22: eef0 0a66 vmov.f32 s1, s13 8004f26: eeb0 0a47 vmov.f32 s0, s14 8004f2a: 480f ldr r0, [pc, #60] @ (8004f68 ) 8004f2c: f7fb fede bl 8000cec // MadgwickAHRS_update_IMU(&IMUQuat, imu_data.processed_imu_data[3], imu_data.processed_imu_data[4], imu_data.processed_imu_data[5], //gx, gy, gz // imu_data.processed_imu_data[0], imu_data.processed_imu_data[1], imu_data.processed_imu_data[2]); // ax, ay, yz) Quat_Dat.qw = IMUQuat.q[0]; 8004f30: 4b0d ldr r3, [pc, #52] @ (8004f68 ) 8004f32: 681b ldr r3, [r3, #0] 8004f34: f8c7 300a str.w r3, [r7, #10] Quat_Dat.qx = IMUQuat.q[1]; 8004f38: 4b0b ldr r3, [pc, #44] @ (8004f68 ) 8004f3a: 685b ldr r3, [r3, #4] 8004f3c: f8c7 300e str.w r3, [r7, #14] Quat_Dat.qy = IMUQuat.q[2]; 8004f40: 4b09 ldr r3, [pc, #36] @ (8004f68 ) 8004f42: 689b ldr r3, [r3, #8] 8004f44: f8c7 3012 str.w r3, [r7, #18] Quat_Dat.qz = IMUQuat.q[3]; 8004f48: 4b07 ldr r3, [pc, #28] @ (8004f68 ) 8004f4a: 68db ldr r3, [r3, #12] 8004f4c: f8c7 3016 str.w r3, [r7, #22] CDC_Transmit_FS((uint8_t*)&Quat_Dat, sizeof(Quat_Dat)); 8004f50: f107 0308 add.w r3, r7, #8 8004f54: 2113 movs r1, #19 8004f56: 4618 mov r0, r3 8004f58: f013 fd3c bl 80189d4 osMessageQueueGet(Q_BMMHandle, &magn_data, NULL, osWaitForever); 8004f5c: bf00 nop 8004f5e: e7b0 b.n 8004ec2 8004f60: 43c80000 .word 0x43c80000 8004f64: 3dcccccd .word 0x3dcccccd 8004f68: 20000710 .word 0x20000710 8004f6c: 2000070c .word 0x2000070c 8004f70: 20000708 .word 0x20000708 08004f74 : * @param argument: Not used * @retval None */ /* USER CODE END Header_Start_ICM45686 */ void Start_ICM45686(void *argument) { 8004f74: b580 push {r7, lr} 8004f76: b0a4 sub sp, #144 @ 0x90 8004f78: af00 add r7, sp, #0 8004f7a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Start_ICM45686 */ xIMU_Task = osThreadGetId(); 8004f7c: f00e fd7e bl 8013a7c 8004f80: 4603 mov r3, r0 8004f82: 4ab8 ldr r2, [pc, #736] @ (8005264 ) 8004f84: 6013 str r3, [r2, #0] uint8_t raw_imu_data[15]; int16_t imu_sensor_data[7]; ICM45686_Data processed_data; ICM45686_HandleTypeDef imu; imu.hspi = &hspi1; 8004f86: 4bb8 ldr r3, [pc, #736] @ (8005268 ) 8004f88: 61bb str r3, [r7, #24] imu.GPIO_Port = GPIO_SPI1_IMU_CS_GPIO_Port; 8004f8a: f04f 4390 mov.w r3, #1207959552 @ 0x48000000 8004f8e: 61fb str r3, [r7, #28] imu.GPIO_Pin = GPIO_SPI1_IMU_CS_Pin; 8004f90: 2308 movs r3, #8 8004f92: 843b strh r3, [r7, #32] imu.acc_fs = ICM45686_ACC_FS_16G; 8004f94: 2310 movs r3, #16 8004f96: f887 3022 strb.w r3, [r7, #34] @ 0x22 imu.acc_ssf = ICM45686_ACC_SSF[ICM45686_ACC_FS_16G >> 4]; 8004f9a: f04f 438a mov.w r3, #1157627904 @ 0x45000000 8004f9e: 62bb str r3, [r7, #40] @ 0x28 imu.gyro_fs = ICM45686_GYRO_FS_2000DPS; 8004fa0: 2310 movs r3, #16 8004fa2: f887 3023 strb.w r3, [r7, #35] @ 0x23 imu.gyro_ssf = ICM45686_GYRO_SSF[ICM45686_GYRO_FS_2000DPS >> 4]; 8004fa6: 4bb1 ldr r3, [pc, #708] @ (800526c ) 8004fa8: 62fb str r3, [r7, #44] @ 0x2c imu.odr = ICM45686_ODR_400Hz_LNLP ; 8004faa: 2307 movs r3, #7 8004fac: f887 3024 strb.w r3, [r7, #36] @ 0x24 uint8_t tx[15] = {0x00}; 8004fb0: f107 0308 add.w r3, r7, #8 8004fb4: 2200 movs r2, #0 8004fb6: 601a str r2, [r3, #0] 8004fb8: 605a str r2, [r3, #4] 8004fba: 609a str r2, [r3, #8] 8004fbc: f8c3 200b str.w r2, [r3, #11] tx[0] = 0x00 | 0x80; 8004fc0: 2380 movs r3, #128 @ 0x80 8004fc2: 723b strb r3, [r7, #8] uint16_t tx_len = sizeof(tx); 8004fc4: 230f movs r3, #15 8004fc6: f8a7 308e strh.w r3, [r7, #142] @ 0x8e init_icm(&imu); 8004fca: f107 0318 add.w r3, r7, #24 8004fce: 4618 mov r0, r3 8004fd0: f000 fb3a bl 8005648 configure_and_enable_int_icm(&imu); 8004fd4: f107 0318 add.w r3, r7, #24 8004fd8: 4618 mov r0, r3 8004fda: f000 fda9 bl 8005b30 ulTaskNotifyTakeIndexed(ICM_NOTIFY_INT_DRDY, pdTRUE, 0); 8004fde: 2200 movs r2, #0 8004fe0: 2101 movs r1, #1 8004fe2: 2000 movs r0, #0 8004fe4: f011 fd98 bl 8016b18 ulTaskNotifyTakeIndexed(ICM_NOTIFY_DMA, pdTRUE, 0); 8004fe8: 2200 movs r2, #0 8004fea: 2101 movs r1, #1 8004fec: 2001 movs r0, #1 8004fee: f011 fd93 bl 8016b18 calibrate_icm(&imu, 1000); 8004ff2: f107 0318 add.w r3, r7, #24 8004ff6: f44f 717a mov.w r1, #1000 @ 0x3e8 8004ffa: 4618 mov r0, r3 8004ffc: f000 fc12 bl 8005824 /* Infinite loop */ for(;;) { ulTaskNotifyTakeIndexed(ICM_NOTIFY_INT_DRDY, pdTRUE, portMAX_DELAY); 8005000: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8005004: 2101 movs r1, #1 8005006: 2000 movs r0, #0 8005008: f011 fd86 bl 8016b18 status = read_icm_dma(&imu, tx, raw_imu_data, tx_len); 800500c: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8005010: f107 027c add.w r2, r7, #124 @ 0x7c 8005014: f107 0108 add.w r1, r7, #8 8005018: f107 0018 add.w r0, r7, #24 800501c: f000 fad1 bl 80055c2 8005020: 4603 mov r3, r0 8005022: f887 308d strb.w r3, [r7, #141] @ 0x8d if (status != HAL_OK) { 8005026: f897 308d ldrb.w r3, [r7, #141] @ 0x8d 800502a: 2b00 cmp r3, #0 800502c: d005 beq.n 800503a printf("Reading IMU sensordata failed: %d\n", status); 800502e: f897 308d ldrb.w r3, [r7, #141] @ 0x8d 8005032: 4619 mov r1, r3 8005034: 488e ldr r0, [pc, #568] @ (8005270 ) 8005036: f015 f8dd bl 801a1f4 } if (ulTaskNotifyTakeIndexed(ICM_NOTIFY_DMA, pdTRUE, pdMS_TO_TICKS(10)) > 0) { 800503a: 220a movs r2, #10 800503c: 2101 movs r1, #1 800503e: 2001 movs r0, #1 8005040: f011 fd6a bl 8016b18 8005044: 4603 mov r3, r0 8005046: 2b00 cmp r3, #0 8005048: f000 80fd beq.w 8005246 imu_sensor_data[0] = (int16_t)(raw_imu_data[1] << 8 | raw_imu_data[2]); // a_x 800504c: f897 307d ldrb.w r3, [r7, #125] @ 0x7d 8005050: b21b sxth r3, r3 8005052: 021b lsls r3, r3, #8 8005054: b21a sxth r2, r3 8005056: f897 307e ldrb.w r3, [r7, #126] @ 0x7e 800505a: b21b sxth r3, r3 800505c: 4313 orrs r3, r2 800505e: b21b sxth r3, r3 8005060: f8a7 306c strh.w r3, [r7, #108] @ 0x6c imu_sensor_data[1] = (int16_t)(raw_imu_data[3] << 8 | raw_imu_data[4]); // a_y 8005064: f897 307f ldrb.w r3, [r7, #127] @ 0x7f 8005068: b21b sxth r3, r3 800506a: 021b lsls r3, r3, #8 800506c: b21a sxth r2, r3 800506e: f897 3080 ldrb.w r3, [r7, #128] @ 0x80 8005072: b21b sxth r3, r3 8005074: 4313 orrs r3, r2 8005076: b21b sxth r3, r3 8005078: f8a7 306e strh.w r3, [r7, #110] @ 0x6e imu_sensor_data[2] = (int16_t)(raw_imu_data[5] << 8 | raw_imu_data[6]); // a_z 800507c: f897 3081 ldrb.w r3, [r7, #129] @ 0x81 8005080: b21b sxth r3, r3 8005082: 021b lsls r3, r3, #8 8005084: b21a sxth r2, r3 8005086: f897 3082 ldrb.w r3, [r7, #130] @ 0x82 800508a: b21b sxth r3, r3 800508c: 4313 orrs r3, r2 800508e: b21b sxth r3, r3 8005090: f8a7 3070 strh.w r3, [r7, #112] @ 0x70 imu_sensor_data[3] = (int16_t)(raw_imu_data[7] << 8 | raw_imu_data[8]); // g_x 8005094: f897 3083 ldrb.w r3, [r7, #131] @ 0x83 8005098: b21b sxth r3, r3 800509a: 021b lsls r3, r3, #8 800509c: b21a sxth r2, r3 800509e: f897 3084 ldrb.w r3, [r7, #132] @ 0x84 80050a2: b21b sxth r3, r3 80050a4: 4313 orrs r3, r2 80050a6: b21b sxth r3, r3 80050a8: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 imu_sensor_data[4] = (int16_t)(raw_imu_data[9] << 8 | raw_imu_data[10]); // g_y 80050ac: f897 3085 ldrb.w r3, [r7, #133] @ 0x85 80050b0: b21b sxth r3, r3 80050b2: 021b lsls r3, r3, #8 80050b4: b21a sxth r2, r3 80050b6: f897 3086 ldrb.w r3, [r7, #134] @ 0x86 80050ba: b21b sxth r3, r3 80050bc: 4313 orrs r3, r2 80050be: b21b sxth r3, r3 80050c0: f8a7 3074 strh.w r3, [r7, #116] @ 0x74 imu_sensor_data[5] = (int16_t)(raw_imu_data[11] << 8 | raw_imu_data[12]); // g_z 80050c4: f897 3087 ldrb.w r3, [r7, #135] @ 0x87 80050c8: b21b sxth r3, r3 80050ca: 021b lsls r3, r3, #8 80050cc: b21a sxth r2, r3 80050ce: f897 3088 ldrb.w r3, [r7, #136] @ 0x88 80050d2: b21b sxth r3, r3 80050d4: 4313 orrs r3, r2 80050d6: b21b sxth r3, r3 80050d8: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 imu_sensor_data[6] = (int16_t)(raw_imu_data[13] << 8 | raw_imu_data[14]); // t 80050dc: f897 3089 ldrb.w r3, [r7, #137] @ 0x89 80050e0: b21b sxth r3, r3 80050e2: 021b lsls r3, r3, #8 80050e4: b21a sxth r2, r3 80050e6: f897 308a ldrb.w r3, [r7, #138] @ 0x8a 80050ea: b21b sxth r3, r3 80050ec: 4313 orrs r3, r2 80050ee: b21b sxth r3, r3 80050f0: f8a7 3078 strh.w r3, [r7, #120] @ 0x78 processed_data.processed_imu_data[0] = (float)imu_sensor_data[0] / imu.acc_ssf; 80050f4: f9b7 306c ldrsh.w r3, [r7, #108] @ 0x6c 80050f8: ee07 3a90 vmov s15, r3 80050fc: eef8 6ae7 vcvt.f32.s32 s13, s15 8005100: ed97 7a0a vldr s14, [r7, #40] @ 0x28 8005104: eec6 7a87 vdiv.f32 s15, s13, s14 8005108: edc7 7a14 vstr s15, [r7, #80] @ 0x50 processed_data.processed_imu_data[1] = (float)imu_sensor_data[1] / imu.acc_ssf; 800510c: f9b7 306e ldrsh.w r3, [r7, #110] @ 0x6e 8005110: ee07 3a90 vmov s15, r3 8005114: eef8 6ae7 vcvt.f32.s32 s13, s15 8005118: ed97 7a0a vldr s14, [r7, #40] @ 0x28 800511c: eec6 7a87 vdiv.f32 s15, s13, s14 8005120: edc7 7a15 vstr s15, [r7, #84] @ 0x54 processed_data.processed_imu_data[2] = (float)imu_sensor_data[2] / imu.acc_ssf; 8005124: f9b7 3070 ldrsh.w r3, [r7, #112] @ 0x70 8005128: ee07 3a90 vmov s15, r3 800512c: eef8 6ae7 vcvt.f32.s32 s13, s15 8005130: ed97 7a0a vldr s14, [r7, #40] @ 0x28 8005134: eec6 7a87 vdiv.f32 s15, s13, s14 8005138: edc7 7a16 vstr s15, [r7, #88] @ 0x58 processed_data.processed_imu_data[3] = (float)imu_sensor_data[3] / imu.gyro_ssf * DEG2RAD;; 800513c: f9b7 3072 ldrsh.w r3, [r7, #114] @ 0x72 8005140: ee07 3a90 vmov s15, r3 8005144: eef8 6ae7 vcvt.f32.s32 s13, s15 8005148: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 800514c: eec6 7a87 vdiv.f32 s15, s13, s14 8005150: ed9f 7a48 vldr s14, [pc, #288] @ 8005274 8005154: ee67 7a87 vmul.f32 s15, s15, s14 8005158: edc7 7a17 vstr s15, [r7, #92] @ 0x5c processed_data.processed_imu_data[4] = (float)imu_sensor_data[4] / imu.gyro_ssf * DEG2RAD;; 800515c: f9b7 3074 ldrsh.w r3, [r7, #116] @ 0x74 8005160: ee07 3a90 vmov s15, r3 8005164: eef8 6ae7 vcvt.f32.s32 s13, s15 8005168: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 800516c: eec6 7a87 vdiv.f32 s15, s13, s14 8005170: ed9f 7a40 vldr s14, [pc, #256] @ 8005274 8005174: ee67 7a87 vmul.f32 s15, s15, s14 8005178: edc7 7a18 vstr s15, [r7, #96] @ 0x60 processed_data.processed_imu_data[5] = (float)imu_sensor_data[5] / imu.gyro_ssf * DEG2RAD;; 800517c: f9b7 3076 ldrsh.w r3, [r7, #118] @ 0x76 8005180: ee07 3a90 vmov s15, r3 8005184: eef8 6ae7 vcvt.f32.s32 s13, s15 8005188: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 800518c: eec6 7a87 vdiv.f32 s15, s13, s14 8005190: ed9f 7a38 vldr s14, [pc, #224] @ 8005274 8005194: ee67 7a87 vmul.f32 s15, s15, s14 8005198: edc7 7a19 vstr s15, [r7, #100] @ 0x64 processed_data.processed_imu_data[6] = (float)(imu_sensor_data[6] / 128.0f + 25.0f); 800519c: f9b7 3078 ldrsh.w r3, [r7, #120] @ 0x78 80051a0: ee07 3a90 vmov s15, r3 80051a4: eeb8 7ae7 vcvt.f32.s32 s14, s15 80051a8: eddf 6a33 vldr s13, [pc, #204] @ 8005278 80051ac: eec7 7a26 vdiv.f32 s15, s14, s13 80051b0: eeb3 7a09 vmov.f32 s14, #57 @ 0x41c80000 25.0 80051b4: ee77 7a87 vadd.f32 s15, s15, s14 80051b8: edc7 7a1a vstr s15, [r7, #104] @ 0x68 if (imu.calibated) { 80051bc: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 80051c0: 2b00 cmp r3, #0 80051c2: d037 beq.n 8005234 processed_data.processed_imu_data[0] -= imu.imu_bias[0]; 80051c4: ed97 7a14 vldr s14, [r7, #80] @ 0x50 80051c8: edd7 7a0d vldr s15, [r7, #52] @ 0x34 80051cc: ee77 7a67 vsub.f32 s15, s14, s15 80051d0: edc7 7a14 vstr s15, [r7, #80] @ 0x50 processed_data.processed_imu_data[1] -= imu.imu_bias[1]; 80051d4: ed97 7a15 vldr s14, [r7, #84] @ 0x54 80051d8: edd7 7a0e vldr s15, [r7, #56] @ 0x38 80051dc: ee77 7a67 vsub.f32 s15, s14, s15 80051e0: edc7 7a15 vstr s15, [r7, #84] @ 0x54 processed_data.processed_imu_data[2] -= imu.imu_bias[2]; 80051e4: ed97 7a16 vldr s14, [r7, #88] @ 0x58 80051e8: edd7 7a0f vldr s15, [r7, #60] @ 0x3c 80051ec: ee77 7a67 vsub.f32 s15, s14, s15 80051f0: edc7 7a16 vstr s15, [r7, #88] @ 0x58 processed_data.processed_imu_data[3] -= imu.imu_bias[3]; 80051f4: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 80051f8: edd7 7a10 vldr s15, [r7, #64] @ 0x40 80051fc: ee77 7a67 vsub.f32 s15, s14, s15 8005200: edc7 7a17 vstr s15, [r7, #92] @ 0x5c processed_data.processed_imu_data[4] -= imu.imu_bias[4]; 8005204: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005208: edd7 7a11 vldr s15, [r7, #68] @ 0x44 800520c: ee77 7a67 vsub.f32 s15, s14, s15 8005210: edc7 7a18 vstr s15, [r7, #96] @ 0x60 processed_data.processed_imu_data[5] -= imu.imu_bias[5]; 8005214: ed97 7a19 vldr s14, [r7, #100] @ 0x64 8005218: edd7 7a12 vldr s15, [r7, #72] @ 0x48 800521c: ee77 7a67 vsub.f32 s15, s14, s15 8005220: edc7 7a19 vstr s15, [r7, #100] @ 0x64 processed_data.processed_imu_data[6] -= imu.imu_bias[6]; 8005224: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8005228: edd7 7a13 vldr s15, [r7, #76] @ 0x4c 800522c: ee77 7a67 vsub.f32 s15, s14, s15 8005230: edc7 7a1a vstr s15, [r7, #104] @ 0x68 } osMessageQueuePut(Q_ICMHandle, &processed_data, 0, 5); 8005234: 4b11 ldr r3, [pc, #68] @ (800527c ) 8005236: 6818 ldr r0, [r3, #0] 8005238: f107 0150 add.w r1, r7, #80 @ 0x50 800523c: 2305 movs r3, #5 800523e: 2200 movs r2, #0 8005240: f00e ff98 bl 8014174 8005244: e6dc b.n 8005000 } else { HAL_SPI_Abort(imu.hspi); 8005246: 69bb ldr r3, [r7, #24] 8005248: 4618 mov r0, r3 800524a: f008 fc1b bl 800da84 HAL_GPIO_WritePin(imu.GPIO_Port, imu.GPIO_Pin, GPIO_PIN_SET); 800524e: 69fb ldr r3, [r7, #28] 8005250: 8c39 ldrh r1, [r7, #32] 8005252: 2201 movs r2, #1 8005254: 4618 mov r0, r3 8005256: f002 f9ad bl 80075b4 printf("IMU DMA data transaction timed out"); 800525a: 4809 ldr r0, [pc, #36] @ (8005280 ) 800525c: f014 ffca bl 801a1f4 ulTaskNotifyTakeIndexed(ICM_NOTIFY_INT_DRDY, pdTRUE, portMAX_DELAY); 8005260: e6ce b.n 8005000 8005262: bf00 nop 8005264: 20000728 .word 0x20000728 8005268: 20000528 .word 0x20000528 800526c: 41833333 .word 0x41833333 8005270: 0801de68 .word 0x0801de68 8005274: 3c8efa35 .word 0x3c8efa35 8005278: 43000000 .word 0x43000000 800527c: 20000708 .word 0x20000708 8005280: 0801de8c .word 0x0801de8c 08005284 : * @param argument: Not used * @retval None */ /* USER CODE END Header_Start_BMM350 */ void Start_BMM350(void *argument) { 8005284: b580 push {r7, lr} 8005286: b0b4 sub sp, #208 @ 0xd0 8005288: af00 add r7, sp, #0 800528a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Start_BMM350 */ xMagn_Task = osThreadGetId(); 800528c: f00e fbf6 bl 8013a7c 8005290: 4603 mov r3, r0 8005292: 4a2a ldr r2, [pc, #168] @ (800533c ) 8005294: 6013 str r3, [r2, #0] struct bmm350_dev dev = {0x00}; 8005296: f107 031c add.w r3, r7, #28 800529a: 22b0 movs r2, #176 @ 0xb0 800529c: 2100 movs r1, #0 800529e: 4618 mov r0, r3 80052a0: f015 f820 bl 801a2e4 int8_t rslt; struct bmm350_mag_temp_data mag_data; // ODR: 400HZ, AVG: 0 rslt = init_bmm(&dev); 80052a4: f107 031c add.w r3, r7, #28 80052a8: 4618 mov r0, r3 80052aa: f000 fd8d bl 8005dc8 80052ae: 4603 mov r3, r0 80052b0: f887 30cf strb.w r3, [r7, #207] @ 0xcf if (rslt != BMM350_OK) { 80052b4: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 80052b8: 2b00 cmp r3, #0 80052ba: d005 beq.n 80052c8 printf("BMM350 initialization failed: %d\n", rslt); 80052bc: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 80052c0: 4619 mov r1, r3 80052c2: 481f ldr r0, [pc, #124] @ (8005340 ) 80052c4: f014 ff96 bl 801a1f4 } rslt = bmm_configure_interrupt(&dev); 80052c8: f107 031c add.w r3, r7, #28 80052cc: 4618 mov r0, r3 80052ce: f000 fdd3 bl 8005e78 80052d2: 4603 mov r3, r0 80052d4: f887 30cf strb.w r3, [r7, #207] @ 0xcf if (rslt != BMM350_OK) { 80052d8: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 80052dc: 2b00 cmp r3, #0 80052de: d005 beq.n 80052ec printf("Configuring interrupt failed: %d\n", rslt); 80052e0: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 80052e4: 4619 mov r1, r3 80052e6: 4817 ldr r0, [pc, #92] @ (8005344 ) 80052e8: f014 ff84 bl 801a1f4 } ulTaskNotifyTakeIndexed(BMM_NOTIFY_INT_DRDY, pdTRUE, 0); 80052ec: 2200 movs r2, #0 80052ee: 2101 movs r1, #1 80052f0: 2000 movs r0, #0 80052f2: f011 fc11 bl 8016b18 ulTaskNotifyTakeIndexed(BMM_NOTIFY_DMA, pdTRUE, 0); 80052f6: 2200 movs r2, #0 80052f8: 2101 movs r1, #1 80052fa: 2001 movs r0, #1 80052fc: f011 fc0c bl 8016b18 /* Infinite loop */ for(;;) { ulTaskNotifyTakeIndexed(BMM_NOTIFY_INT_DRDY, pdTRUE, osWaitForever); 8005300: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8005304: 2101 movs r1, #1 8005306: 2000 movs r0, #0 8005308: f011 fc06 bl 8016b18 rslt = bmm350_get_compensated_mag_xyz_temp_data(&mag_data, &dev); 800530c: f107 021c add.w r2, r7, #28 8005310: f107 030c add.w r3, r7, #12 8005314: 4611 mov r1, r2 8005316: 4618 mov r0, r3 8005318: f7fd fd98 bl 8002e4c 800531c: 4603 mov r3, r0 800531e: f887 30cf strb.w r3, [r7, #207] @ 0xcf if (rslt == BMM350_OK) 8005322: f997 30cf ldrsb.w r3, [r7, #207] @ 0xcf 8005326: 2b00 cmp r3, #0 8005328: d1ea bne.n 8005300 { osMessageQueuePut(Q_BMMHandle, &mag_data, 0, 5); 800532a: 4b07 ldr r3, [pc, #28] @ (8005348 ) 800532c: 6818 ldr r0, [r3, #0] 800532e: f107 010c add.w r1, r7, #12 8005332: 2305 movs r3, #5 8005334: 2200 movs r2, #0 8005336: f00e ff1d bl 8014174 ulTaskNotifyTakeIndexed(BMM_NOTIFY_INT_DRDY, pdTRUE, osWaitForever); 800533a: e7e1 b.n 8005300 800533c: 2000072c .word 0x2000072c 8005340: 0801deb0 .word 0x0801deb0 8005344: 0801ded4 .word 0x0801ded4 8005348: 2000070c .word 0x2000070c 0800534c : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 800534c: b580 push {r7, lr} 800534e: b082 sub sp, #8 8005350: af00 add r7, sp, #0 8005352: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM16) 8005354: 687b ldr r3, [r7, #4] 8005356: 681b ldr r3, [r3, #0] 8005358: 4a04 ldr r2, [pc, #16] @ (800536c ) 800535a: 4293 cmp r3, r2 800535c: d101 bne.n 8005362 { HAL_IncTick(); 800535e: f001 fae3 bl 8006928 } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } 8005362: bf00 nop 8005364: 3708 adds r7, #8 8005366: 46bd mov sp, r7 8005368: bd80 pop {r7, pc} 800536a: bf00 nop 800536c: 40014400 .word 0x40014400 08005370 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8005370: b480 push {r7} 8005372: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8005374: b672 cpsid i } 8005376: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8005378: bf00 nop 800537a: e7fd b.n 8005378 0800537c : #define HAL_I2C_TIMEOUT 100 volatile osThreadId_t xIMU_Task = NULL; volatile osThreadId_t xMagn_Task = NULL; void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { 800537c: b580 push {r7, lr} 800537e: b084 sub sp, #16 8005380: af00 add r7, sp, #0 8005382: 6078 str r0, [r7, #4] if (hspi->Instance == SPI1 && xIMU_Task != NULL) { 8005384: 687b ldr r3, [r7, #4] 8005386: 681b ldr r3, [r3, #0] 8005388: 4a12 ldr r2, [pc, #72] @ (80053d4 ) 800538a: 4293 cmp r3, r2 800538c: d11e bne.n 80053cc 800538e: 4b12 ldr r3, [pc, #72] @ (80053d8 ) 8005390: 681b ldr r3, [r3, #0] 8005392: 2b00 cmp r3, #0 8005394: d01a beq.n 80053cc HAL_GPIO_WritePin(GPIOA, GPIO_SPI1_IMU_CS_Pin, GPIO_PIN_SET); 8005396: 2201 movs r2, #1 8005398: 2108 movs r1, #8 800539a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 800539e: f002 f909 bl 80075b4 BaseType_t xHigherPriorityTaskWoken = pdFALSE; 80053a2: 2300 movs r3, #0 80053a4: 60fb str r3, [r7, #12] vTaskNotifyGiveIndexedFromISR(xIMU_Task, ICM_NOTIFY_DMA, &xHigherPriorityTaskWoken); 80053a6: 4b0c ldr r3, [pc, #48] @ (80053d8 ) 80053a8: 681b ldr r3, [r3, #0] 80053aa: f107 020c add.w r2, r7, #12 80053ae: 2101 movs r1, #1 80053b0: 4618 mov r0, r3 80053b2: f011 ff21 bl 80171f8 portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 80053b6: 68fb ldr r3, [r7, #12] 80053b8: 2b00 cmp r3, #0 80053ba: d007 beq.n 80053cc 80053bc: 4b07 ldr r3, [pc, #28] @ (80053dc ) 80053be: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80053c2: 601a str r2, [r3, #0] 80053c4: f3bf 8f4f dsb sy 80053c8: f3bf 8f6f isb sy } } 80053cc: bf00 nop 80053ce: 3710 adds r7, #16 80053d0: 46bd mov sp, r7 80053d2: bd80 pop {r7, pc} 80053d4: 40013000 .word 0x40013000 80053d8: 20000728 .word 0x20000728 80053dc: e000ed04 .word 0xe000ed04 080053e0 : void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *I2C_address) { 80053e0: b580 push {r7, lr} 80053e2: b084 sub sp, #16 80053e4: af00 add r7, sp, #0 80053e6: 6078 str r0, [r7, #4] if (I2C_address->Instance == I2C1 && xMagn_Task != NULL) { 80053e8: 687b ldr r3, [r7, #4] 80053ea: 681b ldr r3, [r3, #0] 80053ec: 4a0f ldr r2, [pc, #60] @ (800542c ) 80053ee: 4293 cmp r3, r2 80053f0: d118 bne.n 8005424 80053f2: 4b0f ldr r3, [pc, #60] @ (8005430 ) 80053f4: 681b ldr r3, [r3, #0] 80053f6: 2b00 cmp r3, #0 80053f8: d014 beq.n 8005424 BaseType_t xHigherPriorityTaskWoken = pdFALSE; 80053fa: 2300 movs r3, #0 80053fc: 60fb str r3, [r7, #12] // vTaskNotifyGiveFromISR(xMagn_Task, &xHigherPriorityTaskWoken); vTaskNotifyGiveIndexedFromISR(xMagn_Task, BMM_NOTIFY_DMA, &xHigherPriorityTaskWoken); 80053fe: 4b0c ldr r3, [pc, #48] @ (8005430 ) 8005400: 681b ldr r3, [r3, #0] 8005402: f107 020c add.w r2, r7, #12 8005406: 2101 movs r1, #1 8005408: 4618 mov r0, r3 800540a: f011 fef5 bl 80171f8 portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 800540e: 68fb ldr r3, [r7, #12] 8005410: 2b00 cmp r3, #0 8005412: d007 beq.n 8005424 8005414: 4b07 ldr r3, [pc, #28] @ (8005434 ) 8005416: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800541a: 601a str r2, [r3, #0] 800541c: f3bf 8f4f dsb sy 8005420: f3bf 8f6f isb sy } } 8005424: bf00 nop 8005426: 3710 adds r7, #16 8005428: 46bd mov sp, r7 800542a: bd80 pop {r7, pc} 800542c: 40005400 .word 0x40005400 8005430: 2000072c .word 0x2000072c 8005434: e000ed04 .word 0xe000ed04 08005438 : void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *I2C_address) { 8005438: b580 push {r7, lr} 800543a: b084 sub sp, #16 800543c: af00 add r7, sp, #0 800543e: 6078 str r0, [r7, #4] if (I2C_address->Instance == I2C1 && xMagn_Task != NULL) { 8005440: 687b ldr r3, [r7, #4] 8005442: 681b ldr r3, [r3, #0] 8005444: 4a0f ldr r2, [pc, #60] @ (8005484 ) 8005446: 4293 cmp r3, r2 8005448: d118 bne.n 800547c 800544a: 4b0f ldr r3, [pc, #60] @ (8005488 ) 800544c: 681b ldr r3, [r3, #0] 800544e: 2b00 cmp r3, #0 8005450: d014 beq.n 800547c BaseType_t xHigherPriorityTaskWoken = pdFALSE; 8005452: 2300 movs r3, #0 8005454: 60fb str r3, [r7, #12] vTaskNotifyGiveIndexedFromISR(xMagn_Task, BMM_NOTIFY_DMA, &xHigherPriorityTaskWoken); 8005456: 4b0c ldr r3, [pc, #48] @ (8005488 ) 8005458: 681b ldr r3, [r3, #0] 800545a: f107 020c add.w r2, r7, #12 800545e: 2101 movs r1, #1 8005460: 4618 mov r0, r3 8005462: f011 fec9 bl 80171f8 portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 8005466: 68fb ldr r3, [r7, #12] 8005468: 2b00 cmp r3, #0 800546a: d007 beq.n 800547c 800546c: 4b07 ldr r3, [pc, #28] @ (800548c ) 800546e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8005472: 601a str r2, [r3, #0] 8005474: f3bf 8f4f dsb sy 8005478: f3bf 8f6f isb sy } } 800547c: bf00 nop 800547e: 3710 adds r7, #16 8005480: 46bd mov sp, r7 8005482: bd80 pop {r7, pc} 8005484: 40005400 .word 0x40005400 8005488: 2000072c .word 0x2000072c 800548c: e000ed04 .word 0xe000ed04 08005490 : void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { 8005490: b580 push {r7, lr} 8005492: b084 sub sp, #16 8005494: af00 add r7, sp, #0 8005496: 6078 str r0, [r7, #4] if (hi2c->Instance == I2C1 && xMagn_Task != NULL) { 8005498: 687b ldr r3, [r7, #4] 800549a: 681b ldr r3, [r3, #0] 800549c: 4a13 ldr r2, [pc, #76] @ (80054ec ) 800549e: 4293 cmp r3, r2 80054a0: d120 bne.n 80054e4 80054a2: 4b13 ldr r3, [pc, #76] @ (80054f0 ) 80054a4: 681b ldr r3, [r3, #0] 80054a6: 2b00 cmp r3, #0 80054a8: d01c beq.n 80054e4 BaseType_t xHigherPriorityTaskWoken = pdFALSE; 80054aa: 2300 movs r3, #0 80054ac: 60fb str r3, [r7, #12] printf("ErrorCallback: %ld\n", HAL_I2C_GetError(hi2c)); 80054ae: 6878 ldr r0, [r7, #4] 80054b0: f002 fc01 bl 8007cb6 80054b4: 4603 mov r3, r0 80054b6: 4619 mov r1, r3 80054b8: 480e ldr r0, [pc, #56] @ (80054f4 ) 80054ba: f014 fe9b bl 801a1f4 vTaskNotifyGiveIndexedFromISR(xMagn_Task, BMM_NOTIFY_DMA, &xHigherPriorityTaskWoken); 80054be: 4b0c ldr r3, [pc, #48] @ (80054f0 ) 80054c0: 681b ldr r3, [r3, #0] 80054c2: f107 020c add.w r2, r7, #12 80054c6: 2101 movs r1, #1 80054c8: 4618 mov r0, r3 80054ca: f011 fe95 bl 80171f8 portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 80054ce: 68fb ldr r3, [r7, #12] 80054d0: 2b00 cmp r3, #0 80054d2: d007 beq.n 80054e4 80054d4: 4b08 ldr r3, [pc, #32] @ (80054f8 ) 80054d6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80054da: 601a str r2, [r3, #0] 80054dc: f3bf 8f4f dsb sy 80054e0: f3bf 8f6f isb sy } } 80054e4: bf00 nop 80054e6: 3710 adds r7, #16 80054e8: 46bd mov sp, r7 80054ea: bd80 pop {r7, pc} 80054ec: 40005400 .word 0x40005400 80054f0: 2000072c .word 0x2000072c 80054f4: 0801def8 .word 0x0801def8 80054f8: e000ed04 .word 0xe000ed04 080054fc : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 80054fc: b580 push {r7, lr} 80054fe: b084 sub sp, #16 8005500: af00 add r7, sp, #0 8005502: 4603 mov r3, r0 8005504: 80fb strh r3, [r7, #6] BaseType_t xHigherPriorityTaskWoken = pdFALSE; 8005506: 2300 movs r3, #0 8005508: 60fb str r3, [r7, #12] if (GPIO_Pin == GPIO_IMU_INT_Pin && xIMU_Task != NULL) { 800550a: 88fb ldrh r3, [r7, #6] 800550c: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8005510: d10b bne.n 800552a 8005512: 4b15 ldr r3, [pc, #84] @ (8005568 ) 8005514: 681b ldr r3, [r3, #0] 8005516: 2b00 cmp r3, #0 8005518: d007 beq.n 800552a vTaskNotifyGiveIndexedFromISR(xIMU_Task, ICM_NOTIFY_INT_DRDY, &xHigherPriorityTaskWoken); 800551a: 4b13 ldr r3, [pc, #76] @ (8005568 ) 800551c: 681b ldr r3, [r3, #0] 800551e: f107 020c add.w r2, r7, #12 8005522: 2100 movs r1, #0 8005524: 4618 mov r0, r3 8005526: f011 fe67 bl 80171f8 } if (GPIO_Pin == GPIO_MAGN_INT_Pin && xMagn_Task != NULL) { 800552a: 88fb ldrh r3, [r7, #6] 800552c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8005530: d10b bne.n 800554a 8005532: 4b0e ldr r3, [pc, #56] @ (800556c ) 8005534: 681b ldr r3, [r3, #0] 8005536: 2b00 cmp r3, #0 8005538: d007 beq.n 800554a vTaskNotifyGiveIndexedFromISR(xMagn_Task, BMM_NOTIFY_INT_DRDY, &xHigherPriorityTaskWoken); 800553a: 4b0c ldr r3, [pc, #48] @ (800556c ) 800553c: 681b ldr r3, [r3, #0] 800553e: f107 020c add.w r2, r7, #12 8005542: 2100 movs r1, #0 8005544: 4618 mov r0, r3 8005546: f011 fe57 bl 80171f8 } portYIELD_FROM_ISR(xHigherPriorityTaskWoken); 800554a: 68fb ldr r3, [r7, #12] 800554c: 2b00 cmp r3, #0 800554e: d007 beq.n 8005560 8005550: 4b07 ldr r3, [pc, #28] @ (8005570 ) 8005552: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8005556: 601a str r2, [r3, #0] 8005558: f3bf 8f4f dsb sy 800555c: f3bf 8f6f isb sy } 8005560: bf00 nop 8005562: 3710 adds r7, #16 8005564: 46bd mov sp, r7 8005566: bd80 pop {r7, pc} 8005568: 20000728 .word 0x20000728 800556c: 2000072c .word 0x2000072c 8005570: e000ed04 .word 0xe000ed04 08005574 : // ICM 45686 HAL_StatusTypeDef read_icm (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint8_t rx[], uint16_t len_tx) { 8005574: b580 push {r7, lr} 8005576: b088 sub sp, #32 8005578: af02 add r7, sp, #8 800557a: 60f8 str r0, [r7, #12] 800557c: 60b9 str r1, [r7, #8] 800557e: 607a str r2, [r7, #4] 8005580: 807b strh r3, [r7, #2] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET); 8005582: 68fb ldr r3, [r7, #12] 8005584: 6858 ldr r0, [r3, #4] 8005586: 68fb ldr r3, [r7, #12] 8005588: 891b ldrh r3, [r3, #8] 800558a: 2200 movs r2, #0 800558c: 4619 mov r1, r3 800558e: f002 f811 bl 80075b4 HAL_StatusTypeDef status = HAL_SPI_TransmitReceive(imu->hspi, tx, rx, len_tx, 50); 8005592: 68fb ldr r3, [r7, #12] 8005594: 6818 ldr r0, [r3, #0] 8005596: 887b ldrh r3, [r7, #2] 8005598: 2232 movs r2, #50 @ 0x32 800559a: 9200 str r2, [sp, #0] 800559c: 687a ldr r2, [r7, #4] 800559e: 68b9 ldr r1, [r7, #8] 80055a0: f007 fecb bl 800d33a 80055a4: 4603 mov r3, r0 80055a6: 75fb strb r3, [r7, #23] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_SET); 80055a8: 68fb ldr r3, [r7, #12] 80055aa: 6858 ldr r0, [r3, #4] 80055ac: 68fb ldr r3, [r7, #12] 80055ae: 891b ldrh r3, [r3, #8] 80055b0: 2201 movs r2, #1 80055b2: 4619 mov r1, r3 80055b4: f001 fffe bl 80075b4 return status; 80055b8: 7dfb ldrb r3, [r7, #23] } 80055ba: 4618 mov r0, r3 80055bc: 3718 adds r7, #24 80055be: 46bd mov sp, r7 80055c0: bd80 pop {r7, pc} 080055c2 : HAL_StatusTypeDef read_icm_dma (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint8_t rx[], uint16_t len_tx) { 80055c2: b580 push {r7, lr} 80055c4: b086 sub sp, #24 80055c6: af00 add r7, sp, #0 80055c8: 60f8 str r0, [r7, #12] 80055ca: 60b9 str r1, [r7, #8] 80055cc: 607a str r2, [r7, #4] 80055ce: 807b strh r3, [r7, #2] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET); 80055d0: 68fb ldr r3, [r7, #12] 80055d2: 6858 ldr r0, [r3, #4] 80055d4: 68fb ldr r3, [r7, #12] 80055d6: 891b ldrh r3, [r3, #8] 80055d8: 2200 movs r2, #0 80055da: 4619 mov r1, r3 80055dc: f001 ffea bl 80075b4 HAL_StatusTypeDef status = HAL_SPI_TransmitReceive_DMA(imu->hspi, tx, rx, len_tx); 80055e0: 68fb ldr r3, [r7, #12] 80055e2: 6818 ldr r0, [r3, #0] 80055e4: 887b ldrh r3, [r7, #2] 80055e6: 687a ldr r2, [r7, #4] 80055e8: 68b9 ldr r1, [r7, #8] 80055ea: f008 f8c5 bl 800d778 80055ee: 4603 mov r3, r0 80055f0: 75fb strb r3, [r7, #23] return status; 80055f2: 7dfb ldrb r3, [r7, #23] } 80055f4: 4618 mov r0, r3 80055f6: 3718 adds r7, #24 80055f8: 46bd mov sp, r7 80055fa: bd80 pop {r7, pc} 080055fc : HAL_StatusTypeDef write_icm (ICM45686_HandleTypeDef *imu, uint8_t tx[], uint16_t len_tx) { 80055fc: b580 push {r7, lr} 80055fe: b086 sub sp, #24 8005600: af00 add r7, sp, #0 8005602: 60f8 str r0, [r7, #12] 8005604: 60b9 str r1, [r7, #8] 8005606: 4613 mov r3, r2 8005608: 80fb strh r3, [r7, #6] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_RESET); 800560a: 68fb ldr r3, [r7, #12] 800560c: 6858 ldr r0, [r3, #4] 800560e: 68fb ldr r3, [r7, #12] 8005610: 891b ldrh r3, [r3, #8] 8005612: 2200 movs r2, #0 8005614: 4619 mov r1, r3 8005616: f001 ffcd bl 80075b4 HAL_StatusTypeDef status = HAL_SPI_Transmit(imu->hspi, tx, len_tx, 50); 800561a: 68fb ldr r3, [r7, #12] 800561c: 6818 ldr r0, [r3, #0] 800561e: 88fa ldrh r2, [r7, #6] 8005620: 2332 movs r3, #50 @ 0x32 8005622: 68b9 ldr r1, [r7, #8] 8005624: f007 fd13 bl 800d04e 8005628: 4603 mov r3, r0 800562a: 75fb strb r3, [r7, #23] HAL_GPIO_WritePin(imu->GPIO_Port, imu->GPIO_Pin, GPIO_PIN_SET); 800562c: 68fb ldr r3, [r7, #12] 800562e: 6858 ldr r0, [r3, #4] 8005630: 68fb ldr r3, [r7, #12] 8005632: 891b ldrh r3, [r3, #8] 8005634: 2201 movs r2, #1 8005636: 4619 mov r1, r3 8005638: f001 ffbc bl 80075b4 return status; 800563c: 7dfb ldrb r3, [r7, #23] } 800563e: 4618 mov r0, r3 8005640: 3718 adds r7, #24 8005642: 46bd mov sp, r7 8005644: bd80 pop {r7, pc} ... 08005648 : void init_icm(ICM45686_HandleTypeDef *imu) { 8005648: b580 push {r7, lr} 800564a: b084 sub sp, #16 800564c: af00 add r7, sp, #0 800564e: 6078 str r0, [r7, #4] uint8_t tx[2], rx[2]; HAL_StatusTypeDef status; // // WHO AM tx[0] = ICM45686_WHO_AM_I | 0x80; 8005650: 23f2 movs r3, #242 @ 0xf2 8005652: 733b strb r3, [r7, #12] status = read_icm(imu, tx, rx, sizeof(tx)); 8005654: f107 0208 add.w r2, r7, #8 8005658: f107 010c add.w r1, r7, #12 800565c: 2302 movs r3, #2 800565e: 6878 ldr r0, [r7, #4] 8005660: f7ff ff88 bl 8005574 8005664: 4603 mov r3, r0 8005666: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005668: 7bfb ldrb r3, [r7, #15] 800566a: 2b00 cmp r3, #0 800566c: d005 beq.n 800567a printf("Error in reading WHO AM I:%d\n", status); 800566e: 7bfb ldrb r3, [r7, #15] 8005670: 4619 mov r1, r3 8005672: 485e ldr r0, [pc, #376] @ (80057ec ) 8005674: f014 fdbe bl 801a1f4 8005678: e004 b.n 8005684 } else { printf("WHO AM I (0xE9): 0x%02X \n", rx[1]); 800567a: 7a7b ldrb r3, [r7, #9] 800567c: 4619 mov r1, r3 800567e: 485c ldr r0, [pc, #368] @ (80057f0 ) 8005680: f014 fdb8 bl 801a1f4 } // acc config tx[0] = ICM45686_ACCEL_CONFIG0; 8005684: 231b movs r3, #27 8005686: 733b strb r3, [r7, #12] tx[1] = imu->acc_fs | imu->odr; 8005688: 687b ldr r3, [r7, #4] 800568a: 7a9a ldrb r2, [r3, #10] 800568c: 687b ldr r3, [r7, #4] 800568e: 7b1b ldrb r3, [r3, #12] 8005690: 4313 orrs r3, r2 8005692: b2db uxtb r3, r3 8005694: 737b strb r3, [r7, #13] status = write_icm(imu, tx, sizeof(tx)); 8005696: f107 030c add.w r3, r7, #12 800569a: 2202 movs r2, #2 800569c: 4619 mov r1, r3 800569e: 6878 ldr r0, [r7, #4] 80056a0: f7ff ffac bl 80055fc 80056a4: 4603 mov r3, r0 80056a6: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 80056a8: 7bfb ldrb r3, [r7, #15] 80056aa: 2b00 cmp r3, #0 80056ac: d005 beq.n 80056ba printf("Error in setting ACCEL_CONFIG0:%d\n", status); 80056ae: 7bfb ldrb r3, [r7, #15] 80056b0: 4619 mov r1, r3 80056b2: 4850 ldr r0, [pc, #320] @ (80057f4 ) 80056b4: f014 fd9e bl 801a1f4 80056b8: e004 b.n 80056c4 } else { printf("ACCEL_CONFIG0 wrote: 0x%02X \n", tx[1]); 80056ba: 7b7b ldrb r3, [r7, #13] 80056bc: 4619 mov r1, r3 80056be: 484e ldr r0, [pc, #312] @ (80057f8 ) 80056c0: f014 fd98 bl 801a1f4 } tx[0] = ICM45686_ACCEL_CONFIG0 | 0x80; 80056c4: 239b movs r3, #155 @ 0x9b 80056c6: 733b strb r3, [r7, #12] tx[1] = 0x00; 80056c8: 2300 movs r3, #0 80056ca: 737b strb r3, [r7, #13] status = read_icm(imu, tx, rx, sizeof(tx)); 80056cc: f107 0208 add.w r2, r7, #8 80056d0: f107 010c add.w r1, r7, #12 80056d4: 2302 movs r3, #2 80056d6: 6878 ldr r0, [r7, #4] 80056d8: f7ff ff4c bl 8005574 80056dc: 4603 mov r3, r0 80056de: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 80056e0: 7bfb ldrb r3, [r7, #15] 80056e2: 2b00 cmp r3, #0 80056e4: d005 beq.n 80056f2 printf("Error reading ACCEL_CONFIG0:%d\n", status); 80056e6: 7bfb ldrb r3, [r7, #15] 80056e8: 4619 mov r1, r3 80056ea: 4844 ldr r0, [pc, #272] @ (80057fc ) 80056ec: f014 fd82 bl 801a1f4 80056f0: e004 b.n 80056fc } else { printf("ACCEL_CONFIG0 read: 0x%02X \n", rx[1]); 80056f2: 7a7b ldrb r3, [r7, #9] 80056f4: 4619 mov r1, r3 80056f6: 4842 ldr r0, [pc, #264] @ (8005800 ) 80056f8: f014 fd7c bl 801a1f4 } // gyro config tx[0] = ICM45686_GYRO_CONFIG0; 80056fc: 231c movs r3, #28 80056fe: 733b strb r3, [r7, #12] tx[1] = imu->gyro_fs | imu->odr; 8005700: 687b ldr r3, [r7, #4] 8005702: 7ada ldrb r2, [r3, #11] 8005704: 687b ldr r3, [r7, #4] 8005706: 7b1b ldrb r3, [r3, #12] 8005708: 4313 orrs r3, r2 800570a: b2db uxtb r3, r3 800570c: 737b strb r3, [r7, #13] status = write_icm(imu, tx, sizeof(tx)); 800570e: f107 030c add.w r3, r7, #12 8005712: 2202 movs r2, #2 8005714: 4619 mov r1, r3 8005716: 6878 ldr r0, [r7, #4] 8005718: f7ff ff70 bl 80055fc 800571c: 4603 mov r3, r0 800571e: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005720: 7bfb ldrb r3, [r7, #15] 8005722: 2b00 cmp r3, #0 8005724: d005 beq.n 8005732 printf("Error in setting GYRO_CONFIG0:%d\n", status); 8005726: 7bfb ldrb r3, [r7, #15] 8005728: 4619 mov r1, r3 800572a: 4836 ldr r0, [pc, #216] @ (8005804 ) 800572c: f014 fd62 bl 801a1f4 8005730: e004 b.n 800573c } else { printf("GYRO_CONFIG0 wrote: 0x%02X \n", tx[1]); 8005732: 7b7b ldrb r3, [r7, #13] 8005734: 4619 mov r1, r3 8005736: 4834 ldr r0, [pc, #208] @ (8005808 ) 8005738: f014 fd5c bl 801a1f4 } tx[0] = ICM45686_GYRO_CONFIG0 | 0x80; 800573c: 239c movs r3, #156 @ 0x9c 800573e: 733b strb r3, [r7, #12] tx[1] = 0x00; 8005740: 2300 movs r3, #0 8005742: 737b strb r3, [r7, #13] status = read_icm(imu, tx, rx, sizeof(tx)); 8005744: f107 0208 add.w r2, r7, #8 8005748: f107 010c add.w r1, r7, #12 800574c: 2302 movs r3, #2 800574e: 6878 ldr r0, [r7, #4] 8005750: f7ff ff10 bl 8005574 8005754: 4603 mov r3, r0 8005756: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005758: 7bfb ldrb r3, [r7, #15] 800575a: 2b00 cmp r3, #0 800575c: d005 beq.n 800576a printf("Error reading GYRO_CONFIG0:%d\n", status); 800575e: 7bfb ldrb r3, [r7, #15] 8005760: 4619 mov r1, r3 8005762: 482a ldr r0, [pc, #168] @ (800580c ) 8005764: f014 fd46 bl 801a1f4 8005768: e004 b.n 8005774 } else { printf("GYRO_CONFIG0 read: 0x%02X \n", rx[1]); 800576a: 7a7b ldrb r3, [r7, #9] 800576c: 4619 mov r1, r3 800576e: 4828 ldr r0, [pc, #160] @ (8005810 ) 8005770: f014 fd40 bl 801a1f4 } // power settings tx[0] = ICM45686_PWR_MGMT0; 8005774: 2310 movs r3, #16 8005776: 733b strb r3, [r7, #12] tx[1] = 0x0F; //0x10 | 0x03; 8005778: 230f movs r3, #15 800577a: 737b strb r3, [r7, #13] status = write_icm(imu, tx, sizeof(tx)); 800577c: f107 030c add.w r3, r7, #12 8005780: 2202 movs r2, #2 8005782: 4619 mov r1, r3 8005784: 6878 ldr r0, [r7, #4] 8005786: f7ff ff39 bl 80055fc 800578a: 4603 mov r3, r0 800578c: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 800578e: 7bfb ldrb r3, [r7, #15] 8005790: 2b00 cmp r3, #0 8005792: d005 beq.n 80057a0 printf("Error in setting PWR_MGMT0:%d\n", status); 8005794: 7bfb ldrb r3, [r7, #15] 8005796: 4619 mov r1, r3 8005798: 481e ldr r0, [pc, #120] @ (8005814 ) 800579a: f014 fd2b bl 801a1f4 800579e: e004 b.n 80057aa } else { printf("PWR_MGMT0 wrote: 0x%02X \n", tx[1]); 80057a0: 7b7b ldrb r3, [r7, #13] 80057a2: 4619 mov r1, r3 80057a4: 481c ldr r0, [pc, #112] @ (8005818 ) 80057a6: f014 fd25 bl 801a1f4 } tx[0] = ICM45686_PWR_MGMT0 | 0x80; 80057aa: 2390 movs r3, #144 @ 0x90 80057ac: 733b strb r3, [r7, #12] tx[1] = 0x00; 80057ae: 2300 movs r3, #0 80057b0: 737b strb r3, [r7, #13] status = read_icm(imu, tx, rx, sizeof(tx)); 80057b2: f107 0208 add.w r2, r7, #8 80057b6: f107 010c add.w r1, r7, #12 80057ba: 2302 movs r3, #2 80057bc: 6878 ldr r0, [r7, #4] 80057be: f7ff fed9 bl 8005574 80057c2: 4603 mov r3, r0 80057c4: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 80057c6: 7bfb ldrb r3, [r7, #15] 80057c8: 2b00 cmp r3, #0 80057ca: d005 beq.n 80057d8 printf("Error reading PWR_MGMT0:%d\n", status); 80057cc: 7bfb ldrb r3, [r7, #15] 80057ce: 4619 mov r1, r3 80057d0: 4812 ldr r0, [pc, #72] @ (800581c ) 80057d2: f014 fd0f bl 801a1f4 } else { printf("PWR_MGMT0 read: 0x%02X \n", rx[1]); } } 80057d6: e004 b.n 80057e2 printf("PWR_MGMT0 read: 0x%02X \n", rx[1]); 80057d8: 7a7b ldrb r3, [r7, #9] 80057da: 4619 mov r1, r3 80057dc: 4810 ldr r0, [pc, #64] @ (8005820 ) 80057de: f014 fd09 bl 801a1f4 } 80057e2: bf00 nop 80057e4: 3710 adds r7, #16 80057e6: 46bd mov sp, r7 80057e8: bd80 pop {r7, pc} 80057ea: bf00 nop 80057ec: 0801df0c .word 0x0801df0c 80057f0: 0801df2c .word 0x0801df2c 80057f4: 0801df48 .word 0x0801df48 80057f8: 0801df6c .word 0x0801df6c 80057fc: 0801df8c .word 0x0801df8c 8005800: 0801dfac .word 0x0801dfac 8005804: 0801dfcc .word 0x0801dfcc 8005808: 0801dff0 .word 0x0801dff0 800580c: 0801e010 .word 0x0801e010 8005810: 0801e030 .word 0x0801e030 8005814: 0801e04c .word 0x0801e04c 8005818: 0801e06c .word 0x0801e06c 800581c: 0801e088 .word 0x0801e088 8005820: 0801e0a4 .word 0x0801e0a4 08005824 : void calibrate_icm(ICM45686_HandleTypeDef *imu, int samples) { 8005824: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8005828: b0ac sub sp, #176 @ 0xb0 800582a: af0c add r7, sp, #48 @ 0x30 800582c: 61f8 str r0, [r7, #28] 800582e: 61b9 str r1, [r7, #24] HAL_StatusTypeDef status; uint8_t raw_data[15]; int32_t sensor_data[7] = {0}; 8005830: f107 0350 add.w r3, r7, #80 @ 0x50 8005834: 2200 movs r2, #0 8005836: 601a str r2, [r3, #0] 8005838: 605a str r2, [r3, #4] 800583a: 609a str r2, [r3, #8] 800583c: 60da str r2, [r3, #12] 800583e: 611a str r2, [r3, #16] 8005840: 615a str r2, [r3, #20] 8005842: 619a str r2, [r3, #24] float processed_data[7] = {0}; 8005844: f107 0334 add.w r3, r7, #52 @ 0x34 8005848: 2200 movs r2, #0 800584a: 601a str r2, [r3, #0] 800584c: 605a str r2, [r3, #4] 800584e: 609a str r2, [r3, #8] 8005850: 60da str r2, [r3, #12] 8005852: 611a str r2, [r3, #16] 8005854: 615a str r2, [r3, #20] 8005856: 619a str r2, [r3, #24] uint8_t tx[15] = {0x00}; 8005858: f107 0324 add.w r3, r7, #36 @ 0x24 800585c: 2200 movs r2, #0 800585e: 601a str r2, [r3, #0] 8005860: 605a str r2, [r3, #4] 8005862: 609a str r2, [r3, #8] 8005864: f8c3 200b str.w r2, [r3, #11] tx[0] = 0x00 | 0x80; 8005868: 2380 movs r3, #128 @ 0x80 800586a: f887 3024 strb.w r3, [r7, #36] @ 0x24 for (int i = 1; i <= samples; i++) { 800586e: 2301 movs r3, #1 8005870: 67fb str r3, [r7, #124] @ 0x7c 8005872: e080 b.n 8005976 ulTaskNotifyTakeIndexed(ICM_NOTIFY_INT_DRDY, pdTRUE, portMAX_DELAY); 8005874: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8005878: 2101 movs r1, #1 800587a: 2000 movs r0, #0 800587c: f011 f94c bl 8016b18 status = read_icm_dma(imu, tx, raw_data, sizeof(tx)); 8005880: f107 026c add.w r2, r7, #108 @ 0x6c 8005884: f107 0124 add.w r1, r7, #36 @ 0x24 8005888: 230f movs r3, #15 800588a: 69f8 ldr r0, [r7, #28] 800588c: f7ff fe99 bl 80055c2 8005890: 4603 mov r3, r0 8005892: f887 307b strb.w r3, [r7, #123] @ 0x7b if (status != HAL_OK) { 8005896: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 800589a: 2b00 cmp r3, #0 800589c: d005 beq.n 80058aa printf("Calibration read ICM failed: %d\n", status); 800589e: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 80058a2: 4619 mov r1, r3 80058a4: 489e ldr r0, [pc, #632] @ (8005b20 ) 80058a6: f014 fca5 bl 801a1f4 } if (ulTaskNotifyTakeIndexed(ICM_NOTIFY_DMA, pdTRUE, pdMS_TO_TICKS(10)) > 0) { 80058aa: 220a movs r2, #10 80058ac: 2101 movs r1, #1 80058ae: 2001 movs r0, #1 80058b0: f011 f932 bl 8016b18 80058b4: 4603 mov r3, r0 80058b6: 2b00 cmp r3, #0 80058b8: d05a beq.n 8005970 sensor_data[0] += (int16_t)(raw_data[1] << 8 | raw_data[2]); // a_x 80058ba: 6d3b ldr r3, [r7, #80] @ 0x50 80058bc: f897 206d ldrb.w r2, [r7, #109] @ 0x6d 80058c0: b212 sxth r2, r2 80058c2: 0212 lsls r2, r2, #8 80058c4: b211 sxth r1, r2 80058c6: f897 206e ldrb.w r2, [r7, #110] @ 0x6e 80058ca: b212 sxth r2, r2 80058cc: 430a orrs r2, r1 80058ce: b212 sxth r2, r2 80058d0: 4413 add r3, r2 80058d2: 653b str r3, [r7, #80] @ 0x50 sensor_data[1] += (int16_t)(raw_data[3] << 8 | raw_data[4]); // a_y 80058d4: 6d7b ldr r3, [r7, #84] @ 0x54 80058d6: f897 206f ldrb.w r2, [r7, #111] @ 0x6f 80058da: b212 sxth r2, r2 80058dc: 0212 lsls r2, r2, #8 80058de: b211 sxth r1, r2 80058e0: f897 2070 ldrb.w r2, [r7, #112] @ 0x70 80058e4: b212 sxth r2, r2 80058e6: 430a orrs r2, r1 80058e8: b212 sxth r2, r2 80058ea: 4413 add r3, r2 80058ec: 657b str r3, [r7, #84] @ 0x54 sensor_data[2] += (int16_t)(raw_data[5] << 8 | raw_data[6]); // a_z 80058ee: 6dbb ldr r3, [r7, #88] @ 0x58 80058f0: f897 2071 ldrb.w r2, [r7, #113] @ 0x71 80058f4: b212 sxth r2, r2 80058f6: 0212 lsls r2, r2, #8 80058f8: b211 sxth r1, r2 80058fa: f897 2072 ldrb.w r2, [r7, #114] @ 0x72 80058fe: b212 sxth r2, r2 8005900: 430a orrs r2, r1 8005902: b212 sxth r2, r2 8005904: 4413 add r3, r2 8005906: 65bb str r3, [r7, #88] @ 0x58 sensor_data[3] += (int16_t)(raw_data[7] << 8 | raw_data[8]); // g_x 8005908: 6dfb ldr r3, [r7, #92] @ 0x5c 800590a: f897 2073 ldrb.w r2, [r7, #115] @ 0x73 800590e: b212 sxth r2, r2 8005910: 0212 lsls r2, r2, #8 8005912: b211 sxth r1, r2 8005914: f897 2074 ldrb.w r2, [r7, #116] @ 0x74 8005918: b212 sxth r2, r2 800591a: 430a orrs r2, r1 800591c: b212 sxth r2, r2 800591e: 4413 add r3, r2 8005920: 65fb str r3, [r7, #92] @ 0x5c sensor_data[4] += (int16_t)(raw_data[9] << 8 | raw_data[10]); // g_y 8005922: 6e3b ldr r3, [r7, #96] @ 0x60 8005924: f897 2075 ldrb.w r2, [r7, #117] @ 0x75 8005928: b212 sxth r2, r2 800592a: 0212 lsls r2, r2, #8 800592c: b211 sxth r1, r2 800592e: f897 2076 ldrb.w r2, [r7, #118] @ 0x76 8005932: b212 sxth r2, r2 8005934: 430a orrs r2, r1 8005936: b212 sxth r2, r2 8005938: 4413 add r3, r2 800593a: 663b str r3, [r7, #96] @ 0x60 sensor_data[5] += (int16_t)(raw_data[11] << 8 | raw_data[12]); // g_z 800593c: 6e7b ldr r3, [r7, #100] @ 0x64 800593e: f897 2077 ldrb.w r2, [r7, #119] @ 0x77 8005942: b212 sxth r2, r2 8005944: 0212 lsls r2, r2, #8 8005946: b211 sxth r1, r2 8005948: f897 2078 ldrb.w r2, [r7, #120] @ 0x78 800594c: b212 sxth r2, r2 800594e: 430a orrs r2, r1 8005950: b212 sxth r2, r2 8005952: 4413 add r3, r2 8005954: 667b str r3, [r7, #100] @ 0x64 sensor_data[6] += (int16_t)(raw_data[13] << 8 | raw_data[14]); // t 8005956: 6ebb ldr r3, [r7, #104] @ 0x68 8005958: f897 2079 ldrb.w r2, [r7, #121] @ 0x79 800595c: b212 sxth r2, r2 800595e: 0212 lsls r2, r2, #8 8005960: b211 sxth r1, r2 8005962: f897 207a ldrb.w r2, [r7, #122] @ 0x7a 8005966: b212 sxth r2, r2 8005968: 430a orrs r2, r1 800596a: b212 sxth r2, r2 800596c: 4413 add r3, r2 800596e: 66bb str r3, [r7, #104] @ 0x68 for (int i = 1; i <= samples; i++) { 8005970: 6ffb ldr r3, [r7, #124] @ 0x7c 8005972: 3301 adds r3, #1 8005974: 67fb str r3, [r7, #124] @ 0x7c 8005976: 6ffa ldr r2, [r7, #124] @ 0x7c 8005978: 69bb ldr r3, [r7, #24] 800597a: 429a cmp r2, r3 800597c: f77f af7a ble.w 8005874 } } // The acc biases is set to 0 or 1 for gravity to avoid messy values without // proper multiposition calibration done once per board/sensor processed_data[0] = 0.0f; //(float)sensor_data[0] / ((float)samples * imu->acc_ssf); 8005980: f04f 0300 mov.w r3, #0 8005984: 637b str r3, [r7, #52] @ 0x34 processed_data[1] = 0.0f; //(float)sensor_data[1] / ((float)samples * imu->acc_ssf); 8005986: f04f 0300 mov.w r3, #0 800598a: 63bb str r3, [r7, #56] @ 0x38 processed_data[2] = 1.0f; //(float)sensor_data[2] / ((float)samples * imu->acc_ssf); 800598c: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8005990: 63fb str r3, [r7, #60] @ 0x3c processed_data[3] = (float)sensor_data[3] / ((float)samples * imu->gyro_ssf); 8005992: 6dfb ldr r3, [r7, #92] @ 0x5c 8005994: ee07 3a90 vmov s15, r3 8005998: eef8 6ae7 vcvt.f32.s32 s13, s15 800599c: 69bb ldr r3, [r7, #24] 800599e: ee07 3a90 vmov s15, r3 80059a2: eeb8 7ae7 vcvt.f32.s32 s14, s15 80059a6: 69fb ldr r3, [r7, #28] 80059a8: edd3 7a05 vldr s15, [r3, #20] 80059ac: ee27 7a27 vmul.f32 s14, s14, s15 80059b0: eec6 7a87 vdiv.f32 s15, s13, s14 80059b4: edc7 7a10 vstr s15, [r7, #64] @ 0x40 processed_data[4] = (float)sensor_data[4] / ((float)samples * imu->gyro_ssf); 80059b8: 6e3b ldr r3, [r7, #96] @ 0x60 80059ba: ee07 3a90 vmov s15, r3 80059be: eef8 6ae7 vcvt.f32.s32 s13, s15 80059c2: 69bb ldr r3, [r7, #24] 80059c4: ee07 3a90 vmov s15, r3 80059c8: eeb8 7ae7 vcvt.f32.s32 s14, s15 80059cc: 69fb ldr r3, [r7, #28] 80059ce: edd3 7a05 vldr s15, [r3, #20] 80059d2: ee27 7a27 vmul.f32 s14, s14, s15 80059d6: eec6 7a87 vdiv.f32 s15, s13, s14 80059da: edc7 7a11 vstr s15, [r7, #68] @ 0x44 processed_data[5] = (float)sensor_data[5] / ((float)samples * imu->gyro_ssf); 80059de: 6e7b ldr r3, [r7, #100] @ 0x64 80059e0: ee07 3a90 vmov s15, r3 80059e4: eef8 6ae7 vcvt.f32.s32 s13, s15 80059e8: 69bb ldr r3, [r7, #24] 80059ea: ee07 3a90 vmov s15, r3 80059ee: eeb8 7ae7 vcvt.f32.s32 s14, s15 80059f2: 69fb ldr r3, [r7, #28] 80059f4: edd3 7a05 vldr s15, [r3, #20] 80059f8: ee27 7a27 vmul.f32 s14, s14, s15 80059fc: eec6 7a87 vdiv.f32 s15, s13, s14 8005a00: edc7 7a12 vstr s15, [r7, #72] @ 0x48 processed_data[6] = (float)sensor_data[6] / (float)samples; 8005a04: 6ebb ldr r3, [r7, #104] @ 0x68 8005a06: ee07 3a90 vmov s15, r3 8005a0a: eef8 6ae7 vcvt.f32.s32 s13, s15 8005a0e: 69bb ldr r3, [r7, #24] 8005a10: ee07 3a90 vmov s15, r3 8005a14: eeb8 7ae7 vcvt.f32.s32 s14, s15 8005a18: eec6 7a87 vdiv.f32 s15, s13, s14 8005a1c: edc7 7a13 vstr s15, [r7, #76] @ 0x4c imu->imu_bias[0] = processed_data[0]; 8005a20: 6b7a ldr r2, [r7, #52] @ 0x34 8005a22: 69fb ldr r3, [r7, #28] 8005a24: 61da str r2, [r3, #28] imu->imu_bias[1] = processed_data[1]; 8005a26: 6bba ldr r2, [r7, #56] @ 0x38 8005a28: 69fb ldr r3, [r7, #28] 8005a2a: 621a str r2, [r3, #32] imu->imu_bias[2] = processed_data[2];// - 1.0f; 8005a2c: 6bfa ldr r2, [r7, #60] @ 0x3c 8005a2e: 69fb ldr r3, [r7, #28] 8005a30: 625a str r2, [r3, #36] @ 0x24 imu->imu_bias[3] = processed_data[3] * DEG2RAD; 8005a32: edd7 7a10 vldr s15, [r7, #64] @ 0x40 8005a36: ed9f 7a3b vldr s14, [pc, #236] @ 8005b24 8005a3a: ee67 7a87 vmul.f32 s15, s15, s14 8005a3e: 69fb ldr r3, [r7, #28] 8005a40: edc3 7a0a vstr s15, [r3, #40] @ 0x28 imu->imu_bias[4] = processed_data[4] * DEG2RAD; 8005a44: edd7 7a11 vldr s15, [r7, #68] @ 0x44 8005a48: ed9f 7a36 vldr s14, [pc, #216] @ 8005b24 8005a4c: ee67 7a87 vmul.f32 s15, s15, s14 8005a50: 69fb ldr r3, [r7, #28] 8005a52: edc3 7a0b vstr s15, [r3, #44] @ 0x2c imu->imu_bias[5] = processed_data[5] * DEG2RAD; 8005a56: edd7 7a12 vldr s15, [r7, #72] @ 0x48 8005a5a: ed9f 7a32 vldr s14, [pc, #200] @ 8005b24 8005a5e: ee67 7a87 vmul.f32 s15, s15, s14 8005a62: 69fb ldr r3, [r7, #28] 8005a64: edc3 7a0c vstr s15, [r3, #48] @ 0x30 imu->imu_bias[6] = processed_data[6] / 128.0f + 25.0f; 8005a68: ed97 7a13 vldr s14, [r7, #76] @ 0x4c 8005a6c: eddf 6a2e vldr s13, [pc, #184] @ 8005b28 8005a70: eec7 7a26 vdiv.f32 s15, s14, s13 8005a74: eeb3 7a09 vmov.f32 s14, #57 @ 0x41c80000 25.0 8005a78: ee77 7a87 vadd.f32 s15, s15, s14 8005a7c: 69fb ldr r3, [r7, #28] 8005a7e: edc3 7a0d vstr s15, [r3, #52] @ 0x34 imu->calibated = true; 8005a82: 69fb ldr r3, [r7, #28] 8005a84: 2201 movs r2, #1 8005a86: 761a strb r2, [r3, #24] printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n", imu->imu_bias[0], imu->imu_bias[1], imu->imu_bias[2], 8005a88: 69fb ldr r3, [r7, #28] 8005a8a: 69db ldr r3, [r3, #28] printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n", 8005a8c: 4618 mov r0, r3 8005a8e: f7fa fd33 bl 80004f8 <__aeabi_f2d> 8005a92: e9c7 0104 strd r0, r1, [r7, #16] imu->imu_bias[0], imu->imu_bias[1], imu->imu_bias[2], 8005a96: 69fb ldr r3, [r7, #28] 8005a98: 6a1b ldr r3, [r3, #32] printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n", 8005a9a: 4618 mov r0, r3 8005a9c: f7fa fd2c bl 80004f8 <__aeabi_f2d> 8005aa0: 4680 mov r8, r0 8005aa2: 4689 mov r9, r1 imu->imu_bias[0], imu->imu_bias[1], imu->imu_bias[2], 8005aa4: 69fb ldr r3, [r7, #28] 8005aa6: 6a5b ldr r3, [r3, #36] @ 0x24 printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n", 8005aa8: 4618 mov r0, r3 8005aaa: f7fa fd25 bl 80004f8 <__aeabi_f2d> 8005aae: 4682 mov sl, r0 8005ab0: 468b mov fp, r1 imu->imu_bias[3], imu->imu_bias[4], imu->imu_bias[5], 8005ab2: 69fb ldr r3, [r7, #28] 8005ab4: 6a9b ldr r3, [r3, #40] @ 0x28 printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n", 8005ab6: 4618 mov r0, r3 8005ab8: f7fa fd1e bl 80004f8 <__aeabi_f2d> 8005abc: e9c7 0102 strd r0, r1, [r7, #8] imu->imu_bias[3], imu->imu_bias[4], imu->imu_bias[5], 8005ac0: 69fb ldr r3, [r7, #28] 8005ac2: 6adb ldr r3, [r3, #44] @ 0x2c printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n", 8005ac4: 4618 mov r0, r3 8005ac6: f7fa fd17 bl 80004f8 <__aeabi_f2d> 8005aca: e9c7 0100 strd r0, r1, [r7] imu->imu_bias[3], imu->imu_bias[4], imu->imu_bias[5], 8005ace: 69fb ldr r3, [r7, #28] 8005ad0: 6b1b ldr r3, [r3, #48] @ 0x30 printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n", 8005ad2: 4618 mov r0, r3 8005ad4: f7fa fd10 bl 80004f8 <__aeabi_f2d> 8005ad8: 4604 mov r4, r0 8005ada: 460d mov r5, r1 imu->imu_bias[6]); 8005adc: 69fb ldr r3, [r7, #28] 8005ade: 6b5b ldr r3, [r3, #52] @ 0x34 printf("ICM calibration bias: a_x: %.2f a_y: %.2f a_z: %.2f g_x: %.2f g_y: %.2f g_z: %.2f t: %.2f\n", 8005ae0: 4618 mov r0, r3 8005ae2: f7fa fd09 bl 80004f8 <__aeabi_f2d> 8005ae6: 4602 mov r2, r0 8005ae8: 460b mov r3, r1 8005aea: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 8005aee: e9cd 4508 strd r4, r5, [sp, #32] 8005af2: ed97 7b00 vldr d7, [r7] 8005af6: ed8d 7b06 vstr d7, [sp, #24] 8005afa: ed97 7b02 vldr d7, [r7, #8] 8005afe: ed8d 7b04 vstr d7, [sp, #16] 8005b02: e9cd ab02 strd sl, fp, [sp, #8] 8005b06: e9cd 8900 strd r8, r9, [sp] 8005b0a: e9d7 2304 ldrd r2, r3, [r7, #16] 8005b0e: 4807 ldr r0, [pc, #28] @ (8005b2c ) 8005b10: f014 fb70 bl 801a1f4 } 8005b14: bf00 nop 8005b16: 3780 adds r7, #128 @ 0x80 8005b18: 46bd mov sp, r7 8005b1a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8005b1e: bf00 nop 8005b20: 0801e0c0 .word 0x0801e0c0 8005b24: 3c8efa35 .word 0x3c8efa35 8005b28: 43000000 .word 0x43000000 8005b2c: 0801e0e4 .word 0x0801e0e4 08005b30 : void configure_and_enable_int_icm (ICM45686_HandleTypeDef *imu) { 8005b30: b580 push {r7, lr} 8005b32: b084 sub sp, #16 8005b34: af00 add r7, sp, #0 8005b36: 6078 str r0, [r7, #4] uint8_t tx[2], rx[2] = {0x00, 0x00}; 8005b38: 2300 movs r3, #0 8005b3a: 813b strh r3, [r7, #8] // turn off int tx[0] = ICM45686_INT1_CONFIG0; 8005b3c: 2316 movs r3, #22 8005b3e: 733b strb r3, [r7, #12] tx[1] = 0x00; 8005b40: 2300 movs r3, #0 8005b42: 737b strb r3, [r7, #13] HAL_StatusTypeDef status = write_icm(imu, tx, sizeof(tx)); 8005b44: f107 030c add.w r3, r7, #12 8005b48: 2202 movs r2, #2 8005b4a: 4619 mov r1, r3 8005b4c: 6878 ldr r0, [r7, #4] 8005b4e: f7ff fd55 bl 80055fc 8005b52: 4603 mov r3, r0 8005b54: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005b56: 7bfb ldrb r3, [r7, #15] 8005b58: 2b00 cmp r3, #0 8005b5a: d004 beq.n 8005b66 printf("Enabling of IMU INT failed: %d\n", status); 8005b5c: 7bfb ldrb r3, [r7, #15] 8005b5e: 4619 mov r1, r3 8005b60: 4842 ldr r0, [pc, #264] @ (8005c6c ) 8005b62: f014 fb47 bl 801a1f4 } tx[0] = ICM45686_INT1_CONFIG0 | 0x80; 8005b66: 2396 movs r3, #150 @ 0x96 8005b68: 733b strb r3, [r7, #12] tx[1] = 0x00; 8005b6a: 2300 movs r3, #0 8005b6c: 737b strb r3, [r7, #13] status = read_icm(imu, tx, rx, sizeof(tx)); 8005b6e: f107 0208 add.w r2, r7, #8 8005b72: f107 010c add.w r1, r7, #12 8005b76: 2302 movs r3, #2 8005b78: 6878 ldr r0, [r7, #4] 8005b7a: f7ff fcfb bl 8005574 8005b7e: 4603 mov r3, r0 8005b80: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005b82: 7bfb ldrb r3, [r7, #15] 8005b84: 2b00 cmp r3, #0 8005b86: d005 beq.n 8005b94 printf("Reading IMU INT1_CONFIG0 failed: %d\n", status); 8005b88: 7bfb ldrb r3, [r7, #15] 8005b8a: 4619 mov r1, r3 8005b8c: 4838 ldr r0, [pc, #224] @ (8005c70 ) 8005b8e: f014 fb31 bl 801a1f4 8005b92: e004 b.n 8005b9e } else { printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]); 8005b94: 7a7b ldrb r3, [r7, #9] 8005b96: 4619 mov r1, r3 8005b98: 4836 ldr r0, [pc, #216] @ (8005c74 ) 8005b9a: f014 fb2b bl 801a1f4 } // configure int1 to push-pull, pulse, active high tx[0] = ICM45686_INT1_CONFIG2; 8005b9e: 2318 movs r3, #24 8005ba0: 733b strb r3, [r7, #12] tx[1] = 0x01; 8005ba2: 2301 movs r3, #1 8005ba4: 737b strb r3, [r7, #13] status = write_icm(imu, tx, sizeof(tx)); 8005ba6: f107 030c add.w r3, r7, #12 8005baa: 2202 movs r2, #2 8005bac: 4619 mov r1, r3 8005bae: 6878 ldr r0, [r7, #4] 8005bb0: f7ff fd24 bl 80055fc 8005bb4: 4603 mov r3, r0 8005bb6: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005bb8: 7bfb ldrb r3, [r7, #15] 8005bba: 2b00 cmp r3, #0 8005bbc: d004 beq.n 8005bc8 printf("Configuration of IMU INT failed: %d\n", status); 8005bbe: 7bfb ldrb r3, [r7, #15] 8005bc0: 4619 mov r1, r3 8005bc2: 482d ldr r0, [pc, #180] @ (8005c78 ) 8005bc4: f014 fb16 bl 801a1f4 } tx[0] = ICM45686_INT1_CONFIG2 | 0x80; 8005bc8: 2398 movs r3, #152 @ 0x98 8005bca: 733b strb r3, [r7, #12] tx[1] = 0x00; 8005bcc: 2300 movs r3, #0 8005bce: 737b strb r3, [r7, #13] status = read_icm(imu, tx, rx, sizeof(tx)); 8005bd0: f107 0208 add.w r2, r7, #8 8005bd4: f107 010c add.w r1, r7, #12 8005bd8: 2302 movs r3, #2 8005bda: 6878 ldr r0, [r7, #4] 8005bdc: f7ff fcca bl 8005574 8005be0: 4603 mov r3, r0 8005be2: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005be4: 7bfb ldrb r3, [r7, #15] 8005be6: 2b00 cmp r3, #0 8005be8: d005 beq.n 8005bf6 printf("Reading IMU INT1_CONFIG2 failed: %d\n", status); 8005bea: 7bfb ldrb r3, [r7, #15] 8005bec: 4619 mov r1, r3 8005bee: 4823 ldr r0, [pc, #140] @ (8005c7c ) 8005bf0: f014 fb00 bl 801a1f4 8005bf4: e004 b.n 8005c00 } else { printf("INT1_CONFIG2 read: 0x%02X\n", rx[1]); 8005bf6: 7a7b ldrb r3, [r7, #9] 8005bf8: 4619 mov r1, r3 8005bfa: 4821 ldr r0, [pc, #132] @ (8005c80 ) 8005bfc: f014 fafa bl 801a1f4 } // enable int tx[0] = ICM45686_INT1_CONFIG0; 8005c00: 2316 movs r3, #22 8005c02: 733b strb r3, [r7, #12] tx[1] = 0x04; 8005c04: 2304 movs r3, #4 8005c06: 737b strb r3, [r7, #13] status = write_icm(imu, tx, sizeof(tx)); 8005c08: f107 030c add.w r3, r7, #12 8005c0c: 2202 movs r2, #2 8005c0e: 4619 mov r1, r3 8005c10: 6878 ldr r0, [r7, #4] 8005c12: f7ff fcf3 bl 80055fc 8005c16: 4603 mov r3, r0 8005c18: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005c1a: 7bfb ldrb r3, [r7, #15] 8005c1c: 2b00 cmp r3, #0 8005c1e: d004 beq.n 8005c2a printf("Enabling of IMU INT failed: %d\n", status); 8005c20: 7bfb ldrb r3, [r7, #15] 8005c22: 4619 mov r1, r3 8005c24: 4811 ldr r0, [pc, #68] @ (8005c6c ) 8005c26: f014 fae5 bl 801a1f4 } tx[0] = ICM45686_INT1_CONFIG0 | 0x80; 8005c2a: 2396 movs r3, #150 @ 0x96 8005c2c: 733b strb r3, [r7, #12] tx[1] = 0x00; 8005c2e: 2300 movs r3, #0 8005c30: 737b strb r3, [r7, #13] status = read_icm(imu, tx, rx, sizeof(tx)); 8005c32: f107 0208 add.w r2, r7, #8 8005c36: f107 010c add.w r1, r7, #12 8005c3a: 2302 movs r3, #2 8005c3c: 6878 ldr r0, [r7, #4] 8005c3e: f7ff fc99 bl 8005574 8005c42: 4603 mov r3, r0 8005c44: 73fb strb r3, [r7, #15] if (status != HAL_OK) { 8005c46: 7bfb ldrb r3, [r7, #15] 8005c48: 2b00 cmp r3, #0 8005c4a: d005 beq.n 8005c58 printf("Reading IMU INT1_CONFIG0 failed: %d\n", status); 8005c4c: 7bfb ldrb r3, [r7, #15] 8005c4e: 4619 mov r1, r3 8005c50: 4807 ldr r0, [pc, #28] @ (8005c70 ) 8005c52: f014 facf bl 801a1f4 } else { printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]); } } 8005c56: e004 b.n 8005c62 printf("INT1_CONFIG0 read: 0x%02X\n", rx[1]); 8005c58: 7a7b ldrb r3, [r7, #9] 8005c5a: 4619 mov r1, r3 8005c5c: 4805 ldr r0, [pc, #20] @ (8005c74 ) 8005c5e: f014 fac9 bl 801a1f4 } 8005c62: bf00 nop 8005c64: 3710 adds r7, #16 8005c66: 46bd mov sp, r7 8005c68: bd80 pop {r7, pc} 8005c6a: bf00 nop 8005c6c: 0801e140 .word 0x0801e140 8005c70: 0801e160 .word 0x0801e160 8005c74: 0801e188 .word 0x0801e188 8005c78: 0801e1a4 .word 0x0801e1a4 8005c7c: 0801e1cc .word 0x0801e1cc 8005c80: 0801e1f4 .word 0x0801e1f4 08005c84 : // BMM350 void bmm_init_DWT(void){ 8005c84: b480 push {r7} 8005c86: af00 add r7, sp, #0 // Enable trace and debug block (TRCENA) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 8005c88: 4b09 ldr r3, [pc, #36] @ (8005cb0 ) 8005c8a: 68db ldr r3, [r3, #12] 8005c8c: 4a08 ldr r2, [pc, #32] @ (8005cb0 ) 8005c8e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8005c92: 60d3 str r3, [r2, #12] // Reset cycle counter DWT->CYCCNT = 0; 8005c94: 4b07 ldr r3, [pc, #28] @ (8005cb4 ) 8005c96: 2200 movs r2, #0 8005c98: 605a str r2, [r3, #4] // Enable the cycle counter DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; 8005c9a: 4b06 ldr r3, [pc, #24] @ (8005cb4 ) 8005c9c: 681b ldr r3, [r3, #0] 8005c9e: 4a05 ldr r2, [pc, #20] @ (8005cb4 ) 8005ca0: f043 0301 orr.w r3, r3, #1 8005ca4: 6013 str r3, [r2, #0] } 8005ca6: bf00 nop 8005ca8: 46bd mov sp, r7 8005caa: f85d 7b04 ldr.w r7, [sp], #4 8005cae: 4770 bx lr 8005cb0: e000edf0 .word 0xe000edf0 8005cb4: e0001000 .word 0xe0001000 08005cb8 : BMM350_INTF_RET_TYPE bmm350_i2c_read(uint8_t reg_addr, uint8_t *reg_data, uint32_t length, void *intf_ptr){ 8005cb8: b580 push {r7, lr} 8005cba: b088 sub sp, #32 8005cbc: af02 add r7, sp, #8 8005cbe: 60b9 str r1, [r7, #8] 8005cc0: 607a str r2, [r7, #4] 8005cc2: 603b str r3, [r7, #0] 8005cc4: 4603 mov r3, r0 8005cc6: 73fb strb r3, [r7, #15] // Extract I2C device address from intf_ptr uint8_t device_addr = *(uint8_t*)intf_ptr; 8005cc8: 683b ldr r3, [r7, #0] 8005cca: 781b ldrb r3, [r3, #0] 8005ccc: 75fb strb r3, [r7, #23] // STM32 HAL: Write register address, then read data // Device address is left-shifted by 1 for STM32 HAL if (HAL_I2C_Mem_Read_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, reg_data, length) == HAL_OK) { 8005cce: 7dfb ldrb r3, [r7, #23] 8005cd0: b29b uxth r3, r3 8005cd2: 005b lsls r3, r3, #1 8005cd4: b299 uxth r1, r3 8005cd6: 7bfb ldrb r3, [r7, #15] 8005cd8: b29a uxth r2, r3 8005cda: 687b ldr r3, [r7, #4] 8005cdc: b29b uxth r3, r3 8005cde: 9301 str r3, [sp, #4] 8005ce0: 68bb ldr r3, [r7, #8] 8005ce2: 9300 str r3, [sp, #0] 8005ce4: 2301 movs r3, #1 8005ce6: 480b ldr r0, [pc, #44] @ (8005d14 ) 8005ce8: f001 fe3a bl 8007960 8005cec: 4603 mov r3, r0 8005cee: 2b00 cmp r3, #0 8005cf0: d109 bne.n 8005d06 if (ulTaskNotifyTakeIndexed(BMM_NOTIFY_DMA, pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) { 8005cf2: 220a movs r2, #10 8005cf4: 2101 movs r1, #1 8005cf6: 2001 movs r0, #1 8005cf8: f010 ff0e bl 8016b18 8005cfc: 4603 mov r3, r0 8005cfe: 2b01 cmp r3, #1 8005d00: d101 bne.n 8005d06 return BMM350_INTF_RET_SUCCESS; // 0 8005d02: 2300 movs r3, #0 8005d04: e001 b.n 8005d0a } } return -1; // Communication failure 8005d06: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 8005d0a: 4618 mov r0, r3 8005d0c: 3718 adds r7, #24 8005d0e: 46bd mov sp, r7 8005d10: bd80 pop {r7, pc} 8005d12: bf00 nop 8005d14: 200003b4 .word 0x200003b4 08005d18 : BMM350_INTF_RET_TYPE bmm350_i2c_write(uint8_t reg_addr, const uint8_t *reg_data, uint32_t length, void *intf_ptr){ 8005d18: b580 push {r7, lr} 8005d1a: b088 sub sp, #32 8005d1c: af02 add r7, sp, #8 8005d1e: 60b9 str r1, [r7, #8] 8005d20: 607a str r2, [r7, #4] 8005d22: 603b str r3, [r7, #0] 8005d24: 4603 mov r3, r0 8005d26: 73fb strb r3, [r7, #15] uint8_t device_addr = *(uint8_t*)intf_ptr; 8005d28: 683b ldr r3, [r7, #0] 8005d2a: 781b ldrb r3, [r3, #0] 8005d2c: 75fb strb r3, [r7, #23] if (HAL_I2C_Mem_Write_DMA(&hi2c1, device_addr << 1, reg_addr, I2C_MEMADD_SIZE_8BIT, (uint8_t*)reg_data, length) == HAL_OK) { 8005d2e: 7dfb ldrb r3, [r7, #23] 8005d30: b29b uxth r3, r3 8005d32: 005b lsls r3, r3, #1 8005d34: b299 uxth r1, r3 8005d36: 7bfb ldrb r3, [r7, #15] 8005d38: b29a uxth r2, r3 8005d3a: 687b ldr r3, [r7, #4] 8005d3c: b29b uxth r3, r3 8005d3e: 9301 str r3, [sp, #4] 8005d40: 68bb ldr r3, [r7, #8] 8005d42: 9300 str r3, [sp, #0] 8005d44: 2301 movs r3, #1 8005d46: 480b ldr r0, [pc, #44] @ (8005d74 ) 8005d48: f001 fd24 bl 8007794 8005d4c: 4603 mov r3, r0 8005d4e: 2b00 cmp r3, #0 8005d50: d109 bne.n 8005d66 if (ulTaskNotifyTakeIndexed(BMM_NOTIFY_DMA, pdTRUE, pdMS_TO_TICKS(10)) == pdTRUE) { 8005d52: 220a movs r2, #10 8005d54: 2101 movs r1, #1 8005d56: 2001 movs r0, #1 8005d58: f010 fede bl 8016b18 8005d5c: 4603 mov r3, r0 8005d5e: 2b01 cmp r3, #1 8005d60: d101 bne.n 8005d66 return BMM350_INTF_RET_SUCCESS; // 0 8005d62: 2300 movs r3, #0 8005d64: e001 b.n 8005d6a } } return -1; 8005d66: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 8005d6a: 4618 mov r0, r3 8005d6c: 3718 adds r7, #24 8005d6e: 46bd mov sp, r7 8005d70: bd80 pop {r7, pc} 8005d72: bf00 nop 8005d74: 200003b4 .word 0x200003b4 08005d78 : void bmm350_delay(uint32_t period_us, void *intf_ptr){ 8005d78: b480 push {r7} 8005d7a: b085 sub sp, #20 8005d7c: af00 add r7, sp, #0 8005d7e: 6078 str r0, [r7, #4] 8005d80: 6039 str r1, [r7, #0] (void)intf_ptr; // Unused // For STM32, use DWT cycle counter for accurate microsecond delays uint32_t start = DWT->CYCCNT; 8005d82: 4b0e ldr r3, [pc, #56] @ (8005dbc ) 8005d84: 685b ldr r3, [r3, #4] 8005d86: 60fb str r3, [r7, #12] uint32_t cycles = period_us * (SystemCoreClock / 1000000); 8005d88: 4b0d ldr r3, [pc, #52] @ (8005dc0 ) 8005d8a: 681b ldr r3, [r3, #0] 8005d8c: 4a0d ldr r2, [pc, #52] @ (8005dc4 ) 8005d8e: fba2 2303 umull r2, r3, r2, r3 8005d92: 0c9a lsrs r2, r3, #18 8005d94: 687b ldr r3, [r7, #4] 8005d96: fb02 f303 mul.w r3, r2, r3 8005d9a: 60bb str r3, [r7, #8] while ((DWT->CYCCNT - start) < cycles); 8005d9c: bf00 nop 8005d9e: 4b07 ldr r3, [pc, #28] @ (8005dbc ) 8005da0: 685a ldr r2, [r3, #4] 8005da2: 68fb ldr r3, [r7, #12] 8005da4: 1ad3 subs r3, r2, r3 8005da6: 68ba ldr r2, [r7, #8] 8005da8: 429a cmp r2, r3 8005daa: d8f8 bhi.n 8005d9e } 8005dac: bf00 nop 8005dae: bf00 nop 8005db0: 3714 adds r7, #20 8005db2: 46bd mov sp, r7 8005db4: f85d 7b04 ldr.w r7, [sp], #4 8005db8: 4770 bx lr 8005dba: bf00 nop 8005dbc: e0001000 .word 0xe0001000 8005dc0: 2000000c .word 0x2000000c 8005dc4: 431bde83 .word 0x431bde83 08005dc8 : // Initialization function int8_t init_bmm(struct bmm350_dev *dev) { 8005dc8: b580 push {r7, lr} 8005dca: b084 sub sp, #16 8005dcc: af00 add r7, sp, #0 8005dce: 6078 str r0, [r7, #4] // Static variable to hold I2C device address // Must be static or global because dev.intf_ptr will point to it static uint8_t dev_addr = BMM350_I2C_ADSEL_SET_LOW; // Assign function pointers dev->read = bmm350_i2c_read; 8005dd0: 687b ldr r3, [r7, #4] 8005dd2: 4a21 ldr r2, [pc, #132] @ (8005e58 ) 8005dd4: 609a str r2, [r3, #8] dev->write = bmm350_i2c_write; 8005dd6: 687b ldr r3, [r7, #4] 8005dd8: 4a20 ldr r2, [pc, #128] @ (8005e5c ) 8005dda: 60da str r2, [r3, #12] dev->delay_us = bmm350_delay; 8005ddc: 687b ldr r3, [r7, #4] 8005dde: 4a20 ldr r2, [pc, #128] @ (8005e60 ) 8005de0: 611a str r2, [r3, #16] dev->intf_ptr = &dev_addr; 8005de2: 687b ldr r3, [r7, #4] 8005de4: 4a1f ldr r2, [pc, #124] @ (8005e64 ) 8005de6: 601a str r2, [r3, #0] // Initialize BMM350 driver rslt = bmm350_init(dev); 8005de8: 6878 ldr r0, [r7, #4] 8005dea: f7fc fc76 bl 80026da 8005dee: 4603 mov r3, r0 8005df0: 73fb strb r3, [r7, #15] if (rslt != BMM350_OK) 8005df2: f997 300f ldrsb.w r3, [r7, #15] 8005df6: 2b00 cmp r3, #0 8005df8: d002 beq.n 8005e00 { // Handle error: chip ID mismatch, communication failure, etc. return rslt; 8005dfa: f997 300f ldrsb.w r3, [r7, #15] 8005dfe: e027 b.n 8005e50 } printf("Initialization: %d\n", rslt); 8005e00: f997 300f ldrsb.w r3, [r7, #15] 8005e04: 4619 mov r1, r3 8005e06: 4818 ldr r0, [pc, #96] @ (8005e68 ) 8005e08: f014 f9f4 bl 801a1f4 printf("CHIP_ID (should be 0x33) - Read Register: 0x00 BMM350 Chip ID: 0x%X\n", dev->chip_id); 8005e0c: 687b ldr r3, [r7, #4] 8005e0e: 791b ldrb r3, [r3, #4] 8005e10: 4619 mov r1, r3 8005e12: 4816 ldr r0, [pc, #88] @ (8005e6c ) 8005e14: f014 f9ee bl 801a1f4 // Set powermode, odr and avg rslt = bmm350_set_powermode(BMM350_NORMAL_MODE, dev); 8005e18: 6879 ldr r1, [r7, #4] 8005e1a: 2001 movs r0, #1 8005e1c: f7fc fd8c bl 8002938 8005e20: 4603 mov r3, r0 8005e22: 73fb strb r3, [r7, #15] printf("Powermode (%d): %d\n", BMM350_NORMAL_MODE, rslt); 8005e24: f997 300f ldrsb.w r3, [r7, #15] 8005e28: 461a mov r2, r3 8005e2a: 2101 movs r1, #1 8005e2c: 4810 ldr r0, [pc, #64] @ (8005e70 ) 8005e2e: f014 f9e1 bl 801a1f4 rslt = bmm350_set_odr_performance(BMM350_DATA_RATE_400HZ, BMM350_NO_AVERAGING, dev); 8005e32: 687a ldr r2, [r7, #4] 8005e34: 2100 movs r1, #0 8005e36: 2002 movs r0, #2 8005e38: f7fc fdd0 bl 80029dc 8005e3c: 4603 mov r3, r0 8005e3e: 73fb strb r3, [r7, #15] printf("ODR(%d) and AVG(%d): %d\n", BMM350_DATA_RATE_400HZ, BMM350_NO_AVERAGING, rslt); 8005e40: f997 300f ldrsb.w r3, [r7, #15] 8005e44: 2200 movs r2, #0 8005e46: 2102 movs r1, #2 8005e48: 480a ldr r0, [pc, #40] @ (8005e74 ) 8005e4a: f014 f9d3 bl 801a1f4 return BMM350_OK; 8005e4e: 2300 movs r3, #0 } 8005e50: 4618 mov r0, r3 8005e52: 3710 adds r7, #16 8005e54: 46bd mov sp, r7 8005e56: bd80 pop {r7, pc} 8005e58: 08005cb9 .word 0x08005cb9 8005e5c: 08005d19 .word 0x08005d19 8005e60: 08005d79 .word 0x08005d79 8005e64: 20000008 .word 0x20000008 8005e68: 0801e210 .word 0x0801e210 8005e6c: 0801e224 .word 0x0801e224 8005e70: 0801e26c .word 0x0801e26c 8005e74: 0801e280 .word 0x0801e280 08005e78 : int8_t bmm_configure_interrupt (struct bmm350_dev *dev) { 8005e78: b580 push {r7, lr} 8005e7a: b086 sub sp, #24 8005e7c: af02 add r7, sp, #8 8005e7e: 6078 str r0, [r7, #4] int8_t rslt; rslt = bmm350_enable_interrupt(BMM350_ENABLE_INTERRUPT, dev); 8005e80: 6879 ldr r1, [r7, #4] 8005e82: 2001 movs r0, #1 8005e84: f7fc fe17 bl 8002ab6 8005e88: 4603 mov r3, r0 8005e8a: 73fb strb r3, [r7, #15] printf("Interrupt enable: %d \n", rslt); 8005e8c: f997 300f ldrsb.w r3, [r7, #15] 8005e90: 4619 mov r1, r3 8005e92: 480c ldr r0, [pc, #48] @ (8005ec4 ) 8005e94: f014 f9ae bl 801a1f4 rslt = bmm350_configure_interrupt(BMM350_PULSED, BMM350_ACTIVE_HIGH, BMM350_INTR_PUSH_PULL, BMM350_MAP_TO_PIN, dev); 8005e98: 687b ldr r3, [r7, #4] 8005e9a: 9300 str r3, [sp, #0] 8005e9c: 2301 movs r3, #1 8005e9e: 2201 movs r2, #1 8005ea0: 2101 movs r1, #1 8005ea2: 2000 movs r0, #0 8005ea4: f7fc fe38 bl 8002b18 8005ea8: 4603 mov r3, r0 8005eaa: 73fb strb r3, [r7, #15] printf("Configure interrupt: %d \n", rslt); 8005eac: f997 300f ldrsb.w r3, [r7, #15] 8005eb0: 4619 mov r1, r3 8005eb2: 4805 ldr r0, [pc, #20] @ (8005ec8 ) 8005eb4: f014 f99e bl 801a1f4 return BMM350_OK; 8005eb8: 2300 movs r3, #0 } 8005eba: 4618 mov r0, r3 8005ebc: 3710 adds r7, #16 8005ebe: 46bd mov sp, r7 8005ec0: bd80 pop {r7, pc} 8005ec2: bf00 nop 8005ec4: 0801e29c .word 0x0801e29c 8005ec8: 0801e2b4 .word 0x0801e2b4 08005ecc : * @brief Enable RTC * @rmtoll BDCR RTCEN LL_RCC_EnableRTC * @retval None */ __STATIC_INLINE void LL_RCC_EnableRTC(void) { 8005ecc: b480 push {r7} 8005ece: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 8005ed0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005ed4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8005ed8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8005edc: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8005ee0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 8005ee4: bf00 nop 8005ee6: 46bd mov sp, r7 8005ee8: f85d 7b04 ldr.w r7, [sp], #4 8005eec: 4770 bx lr 08005eee : { 8005eee: b480 push {r7} 8005ef0: b085 sub sp, #20 8005ef2: af00 add r7, sp, #0 8005ef4: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB2ENR, Periphs); 8005ef6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005efa: 6cda ldr r2, [r3, #76] @ 0x4c 8005efc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005f00: 687b ldr r3, [r7, #4] 8005f02: 4313 orrs r3, r2 8005f04: 64cb str r3, [r1, #76] @ 0x4c tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 8005f06: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005f0a: 6cda ldr r2, [r3, #76] @ 0x4c 8005f0c: 687b ldr r3, [r7, #4] 8005f0e: 4013 ands r3, r2 8005f10: 60fb str r3, [r7, #12] (void)tmpreg; 8005f12: 68fb ldr r3, [r7, #12] } 8005f14: bf00 nop 8005f16: 3714 adds r7, #20 8005f18: 46bd mov sp, r7 8005f1a: f85d 7b04 ldr.w r7, [sp], #4 8005f1e: 4770 bx lr 08005f20 : * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) { 8005f20: b480 push {r7} 8005f22: b085 sub sp, #20 8005f24: af00 add r7, sp, #0 8005f26: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->AHB3ENR, Periphs); 8005f28: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005f2c: 6d1a ldr r2, [r3, #80] @ 0x50 8005f2e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005f32: 687b ldr r3, [r7, #4] 8005f34: 4313 orrs r3, r2 8005f36: 650b str r3, [r1, #80] @ 0x50 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 8005f38: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005f3c: 6d1a ldr r2, [r3, #80] @ 0x50 8005f3e: 687b ldr r3, [r7, #4] 8005f40: 4013 ands r3, r2 8005f42: 60fb str r3, [r7, #12] (void)tmpreg; 8005f44: 68fb ldr r3, [r7, #12] } 8005f46: bf00 nop 8005f48: 3714 adds r7, #20 8005f4a: 46bd mov sp, r7 8005f4c: f85d 7b04 ldr.w r7, [sp], #4 8005f50: 4770 bx lr 08005f52 : * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) { 8005f52: b480 push {r7} 8005f54: b085 sub sp, #20 8005f56: af00 add r7, sp, #0 8005f58: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR1, Periphs); 8005f5a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005f5e: 6d9a ldr r2, [r3, #88] @ 0x58 8005f60: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005f64: 687b ldr r3, [r7, #4] 8005f66: 4313 orrs r3, r2 8005f68: 658b str r3, [r1, #88] @ 0x58 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 8005f6a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005f6e: 6d9a ldr r2, [r3, #88] @ 0x58 8005f70: 687b ldr r3, [r7, #4] 8005f72: 4013 ands r3, r2 8005f74: 60fb str r3, [r7, #12] (void)tmpreg; 8005f76: 68fb ldr r3, [r7, #12] } 8005f78: bf00 nop 8005f7a: 3714 adds r7, #20 8005f7c: 46bd mov sp, r7 8005f7e: f85d 7b04 ldr.w r7, [sp], #4 8005f82: 4770 bx lr 08005f84 : * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @note (*) Not supported by all the devices * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { 8005f84: b480 push {r7} 8005f86: b085 sub sp, #20 8005f88: af00 add r7, sp, #0 8005f8a: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, Periphs); 8005f8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005f90: 6e1a ldr r2, [r3, #96] @ 0x60 8005f92: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8005f96: 687b ldr r3, [r7, #4] 8005f98: 4313 orrs r3, r2 8005f9a: 660b str r3, [r1, #96] @ 0x60 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 8005f9c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005fa0: 6e1a ldr r2, [r3, #96] @ 0x60 8005fa2: 687b ldr r3, [r7, #4] 8005fa4: 4013 ands r3, r2 8005fa6: 60fb str r3, [r7, #12] (void)tmpreg; 8005fa8: 68fb ldr r3, [r7, #12] } 8005faa: bf00 nop 8005fac: 3714 adds r7, #20 8005fae: 46bd mov sp, r7 8005fb0: f85d 7b04 ldr.w r7, [sp], #4 8005fb4: 4770 bx lr ... 08005fb8 : { 8005fb8: b480 push {r7} 8005fba: b083 sub sp, #12 8005fbc: af00 add r7, sp, #0 8005fbe: 6078 str r0, [r7, #4] SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); 8005fc0: 4b05 ldr r3, [pc, #20] @ (8005fd8 ) 8005fc2: 685a ldr r2, [r3, #4] 8005fc4: 4904 ldr r1, [pc, #16] @ (8005fd8 ) 8005fc6: 687b ldr r3, [r7, #4] 8005fc8: 4313 orrs r3, r2 8005fca: 604b str r3, [r1, #4] } 8005fcc: bf00 nop 8005fce: 370c adds r7, #12 8005fd0: 46bd mov sp, r7 8005fd2: f85d 7b04 ldr.w r7, [sp], #4 8005fd6: 4770 bx lr 8005fd8: 40010000 .word 0x40010000 08005fdc : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8005fdc: b580 push {r7, lr} 8005fde: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_HSEM_CLK_ENABLE(); 8005fe0: f44f 2000 mov.w r0, #524288 @ 0x80000 8005fe4: f7ff ff9c bl 8005f20 HAL_PWREx_EnableVddUSB(); 8005fe8: f004 ffba bl 800af60 /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8005fec: 2200 movs r2, #0 8005fee: 210f movs r1, #15 8005ff0: f06f 0001 mvn.w r0, #1 8005ff4: f000 fddc bl 8006bb0 /* Peripheral interrupt init */ /* HSEM_IRQn interrupt configuration */ HAL_NVIC_SetPriority(HSEM_IRQn, 5, 0); 8005ff8: 2200 movs r2, #0 8005ffa: 2105 movs r1, #5 8005ffc: 202e movs r0, #46 @ 0x2e 8005ffe: f000 fdd7 bl 8006bb0 HAL_NVIC_EnableIRQ(HSEM_IRQn); 8006002: 202e movs r0, #46 @ 0x2e 8006004: f000 fdee bl 8006be4 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8006008: bf00 nop 800600a: bd80 pop {r7, pc} 0800600c : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 800600c: b580 push {r7, lr} 800600e: b09c sub sp, #112 @ 0x70 8006010: af00 add r7, sp, #0 8006012: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8006014: f107 035c add.w r3, r7, #92 @ 0x5c 8006018: 2200 movs r2, #0 800601a: 601a str r2, [r3, #0] 800601c: 605a str r2, [r3, #4] 800601e: 609a str r2, [r3, #8] 8006020: 60da str r2, [r3, #12] 8006022: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8006024: f107 030c add.w r3, r7, #12 8006028: 2250 movs r2, #80 @ 0x50 800602a: 2100 movs r1, #0 800602c: 4618 mov r0, r3 800602e: f014 f959 bl 801a2e4 if(hi2c->Instance==I2C1) 8006032: 687b ldr r3, [r7, #4] 8006034: 681b ldr r3, [r3, #0] 8006036: 4a4d ldr r2, [pc, #308] @ (800616c ) 8006038: 4293 cmp r3, r2 800603a: f040 8093 bne.w 8006164 /* USER CODE END I2C1_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1; 800603e: 2304 movs r3, #4 8006040: 60fb str r3, [r7, #12] PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; 8006042: f44f 3340 mov.w r3, #196608 @ 0x30000 8006046: 62fb str r3, [r7, #44] @ 0x2c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8006048: f107 030c add.w r3, r7, #12 800604c: 4618 mov r0, r3 800604e: f006 faf5 bl 800c63c 8006052: 4603 mov r3, r0 8006054: 2b00 cmp r3, #0 8006056: d001 beq.n 800605c { Error_Handler(); 8006058: f7ff f98a bl 8005370 } __HAL_RCC_GPIOB_CLK_ENABLE(); 800605c: 2002 movs r0, #2 800605e: f7ff ff46 bl 8005eee /**I2C1 GPIO Configuration PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 8006062: f44f 7340 mov.w r3, #768 @ 0x300 8006066: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8006068: 2312 movs r3, #18 800606a: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Pull = GPIO_NOPULL; 800606c: 2300 movs r3, #0 800606e: 667b str r3, [r7, #100] @ 0x64 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8006070: 2303 movs r3, #3 8006072: 66bb str r3, [r7, #104] @ 0x68 GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 8006074: 2304 movs r3, #4 8006076: 66fb str r3, [r7, #108] @ 0x6c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8006078: f107 035c add.w r3, r7, #92 @ 0x5c 800607c: 4619 mov r1, r3 800607e: 483c ldr r0, [pc, #240] @ (8006170 ) 8006080: f001 f928 bl 80072d4 __HAL_SYSCFG_FASTMODEPLUS_ENABLE(SYSCFG_FASTMODEPLUS_PB8); 8006084: f44f 2080 mov.w r0, #262144 @ 0x40000 8006088: f7ff ff96 bl 8005fb8 __HAL_SYSCFG_FASTMODEPLUS_ENABLE(SYSCFG_FASTMODEPLUS_PB9); 800608c: f44f 2000 mov.w r0, #524288 @ 0x80000 8006090: f7ff ff92 bl 8005fb8 /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8006094: f44f 1000 mov.w r0, #2097152 @ 0x200000 8006098: f7ff ff5b bl 8005f52 /* I2C1 DMA Init */ /* I2C1_TX Init */ hdma_i2c1_tx.Instance = DMA1_Channel3; 800609c: 4b35 ldr r3, [pc, #212] @ (8006174 ) 800609e: 4a36 ldr r2, [pc, #216] @ (8006178 ) 80060a0: 601a str r2, [r3, #0] hdma_i2c1_tx.Init.Request = DMA_REQUEST_I2C1_TX; 80060a2: 4b34 ldr r3, [pc, #208] @ (8006174 ) 80060a4: 220b movs r2, #11 80060a6: 605a str r2, [r3, #4] hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80060a8: 4b32 ldr r3, [pc, #200] @ (8006174 ) 80060aa: 2210 movs r2, #16 80060ac: 609a str r2, [r3, #8] hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80060ae: 4b31 ldr r3, [pc, #196] @ (8006174 ) 80060b0: 2200 movs r2, #0 80060b2: 60da str r2, [r3, #12] hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE; 80060b4: 4b2f ldr r3, [pc, #188] @ (8006174 ) 80060b6: 2280 movs r2, #128 @ 0x80 80060b8: 611a str r2, [r3, #16] hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80060ba: 4b2e ldr r3, [pc, #184] @ (8006174 ) 80060bc: 2200 movs r2, #0 80060be: 615a str r2, [r3, #20] hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80060c0: 4b2c ldr r3, [pc, #176] @ (8006174 ) 80060c2: 2200 movs r2, #0 80060c4: 619a str r2, [r3, #24] hdma_i2c1_tx.Init.Mode = DMA_NORMAL; 80060c6: 4b2b ldr r3, [pc, #172] @ (8006174 ) 80060c8: 2200 movs r2, #0 80060ca: 61da str r2, [r3, #28] hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_HIGH; 80060cc: 4b29 ldr r3, [pc, #164] @ (8006174 ) 80060ce: f44f 5200 mov.w r2, #8192 @ 0x2000 80060d2: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_i2c1_tx) != HAL_OK) 80060d4: 4827 ldr r0, [pc, #156] @ (8006174 ) 80060d6: f000 fdbd bl 8006c54 80060da: 4603 mov r3, r0 80060dc: 2b00 cmp r3, #0 80060de: d001 beq.n 80060e4 { Error_Handler(); 80060e0: f7ff f946 bl 8005370 } __HAL_LINKDMA(hi2c,hdmatx,hdma_i2c1_tx); 80060e4: 687b ldr r3, [r7, #4] 80060e6: 4a23 ldr r2, [pc, #140] @ (8006174 ) 80060e8: 639a str r2, [r3, #56] @ 0x38 80060ea: 4a22 ldr r2, [pc, #136] @ (8006174 ) 80060ec: 687b ldr r3, [r7, #4] 80060ee: 6293 str r3, [r2, #40] @ 0x28 /* I2C1_RX Init */ hdma_i2c1_rx.Instance = DMA1_Channel4; 80060f0: 4b22 ldr r3, [pc, #136] @ (800617c ) 80060f2: 4a23 ldr r2, [pc, #140] @ (8006180 ) 80060f4: 601a str r2, [r3, #0] hdma_i2c1_rx.Init.Request = DMA_REQUEST_I2C1_RX; 80060f6: 4b21 ldr r3, [pc, #132] @ (800617c ) 80060f8: 220a movs r2, #10 80060fa: 605a str r2, [r3, #4] hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80060fc: 4b1f ldr r3, [pc, #124] @ (800617c ) 80060fe: 2200 movs r2, #0 8006100: 609a str r2, [r3, #8] hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8006102: 4b1e ldr r3, [pc, #120] @ (800617c ) 8006104: 2200 movs r2, #0 8006106: 60da str r2, [r3, #12] hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE; 8006108: 4b1c ldr r3, [pc, #112] @ (800617c ) 800610a: 2280 movs r2, #128 @ 0x80 800610c: 611a str r2, [r3, #16] hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800610e: 4b1b ldr r3, [pc, #108] @ (800617c ) 8006110: 2200 movs r2, #0 8006112: 615a str r2, [r3, #20] hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8006114: 4b19 ldr r3, [pc, #100] @ (800617c ) 8006116: 2200 movs r2, #0 8006118: 619a str r2, [r3, #24] hdma_i2c1_rx.Init.Mode = DMA_NORMAL; 800611a: 4b18 ldr r3, [pc, #96] @ (800617c ) 800611c: 2200 movs r2, #0 800611e: 61da str r2, [r3, #28] hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_HIGH; 8006120: 4b16 ldr r3, [pc, #88] @ (800617c ) 8006122: f44f 5200 mov.w r2, #8192 @ 0x2000 8006126: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_i2c1_rx) != HAL_OK) 8006128: 4814 ldr r0, [pc, #80] @ (800617c ) 800612a: f000 fd93 bl 8006c54 800612e: 4603 mov r3, r0 8006130: 2b00 cmp r3, #0 8006132: d001 beq.n 8006138 { Error_Handler(); 8006134: f7ff f91c bl 8005370 } __HAL_LINKDMA(hi2c,hdmarx,hdma_i2c1_rx); 8006138: 687b ldr r3, [r7, #4] 800613a: 4a10 ldr r2, [pc, #64] @ (800617c ) 800613c: 63da str r2, [r3, #60] @ 0x3c 800613e: 4a0f ldr r2, [pc, #60] @ (800617c ) 8006140: 687b ldr r3, [r7, #4] 8006142: 6293 str r3, [r2, #40] @ 0x28 /* I2C1 interrupt Init */ HAL_NVIC_SetPriority(I2C1_EV_IRQn, 5, 0); 8006144: 2200 movs r2, #0 8006146: 2105 movs r1, #5 8006148: 201e movs r0, #30 800614a: f000 fd31 bl 8006bb0 HAL_NVIC_EnableIRQ(I2C1_EV_IRQn); 800614e: 201e movs r0, #30 8006150: f000 fd48 bl 8006be4 HAL_NVIC_SetPriority(I2C1_ER_IRQn, 5, 0); 8006154: 2200 movs r2, #0 8006156: 2105 movs r1, #5 8006158: 201f movs r0, #31 800615a: f000 fd29 bl 8006bb0 HAL_NVIC_EnableIRQ(I2C1_ER_IRQn); 800615e: 201f movs r0, #31 8006160: f000 fd40 bl 8006be4 /* USER CODE END I2C1_MspInit 1 */ } } 8006164: bf00 nop 8006166: 3770 adds r7, #112 @ 0x70 8006168: 46bd mov sp, r7 800616a: bd80 pop {r7, pc} 800616c: 40005400 .word 0x40005400 8006170: 48000400 .word 0x48000400 8006174: 20000408 .word 0x20000408 8006178: 40020030 .word 0x40020030 800617c: 20000468 .word 0x20000468 8006180: 40020044 .word 0x40020044 08006184 : * This function configures the hardware resources used in this example * @param hipcc: IPCC handle pointer * @retval None */ void HAL_IPCC_MspInit(IPCC_HandleTypeDef* hipcc) { 8006184: b580 push {r7, lr} 8006186: b082 sub sp, #8 8006188: af00 add r7, sp, #0 800618a: 6078 str r0, [r7, #4] if(hipcc->Instance==IPCC) 800618c: 687b ldr r3, [r7, #4] 800618e: 681b ldr r3, [r3, #0] 8006190: 4a0d ldr r2, [pc, #52] @ (80061c8 ) 8006192: 4293 cmp r3, r2 8006194: d113 bne.n 80061be { /* USER CODE BEGIN IPCC_MspInit 0 */ /* USER CODE END IPCC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_IPCC_CLK_ENABLE(); 8006196: f44f 1080 mov.w r0, #1048576 @ 0x100000 800619a: f7ff fec1 bl 8005f20 /* IPCC interrupt Init */ HAL_NVIC_SetPriority(IPCC_C1_RX_IRQn, 5, 0); 800619e: 2200 movs r2, #0 80061a0: 2105 movs r1, #5 80061a2: 202c movs r0, #44 @ 0x2c 80061a4: f000 fd04 bl 8006bb0 HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn); 80061a8: 202c movs r0, #44 @ 0x2c 80061aa: f000 fd1b bl 8006be4 HAL_NVIC_SetPriority(IPCC_C1_TX_IRQn, 5, 0); 80061ae: 2200 movs r2, #0 80061b0: 2105 movs r1, #5 80061b2: 202d movs r0, #45 @ 0x2d 80061b4: f000 fcfc bl 8006bb0 HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn); 80061b8: 202d movs r0, #45 @ 0x2d 80061ba: f000 fd13 bl 8006be4 /* USER CODE END IPCC_MspInit 1 */ } } 80061be: bf00 nop 80061c0: 3708 adds r7, #8 80061c2: 46bd mov sp, r7 80061c4: bd80 pop {r7, pc} 80061c6: bf00 nop 80061c8: 58000c00 .word 0x58000c00 080061cc : * This function configures the hardware resources used in this example * @param hrtc: RTC handle pointer * @retval None */ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { 80061cc: b580 push {r7, lr} 80061ce: b096 sub sp, #88 @ 0x58 80061d0: af00 add r7, sp, #0 80061d2: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80061d4: f107 0308 add.w r3, r7, #8 80061d8: 2250 movs r2, #80 @ 0x50 80061da: 2100 movs r1, #0 80061dc: 4618 mov r0, r3 80061de: f014 f881 bl 801a2e4 if(hrtc->Instance==RTC) 80061e2: 687b ldr r3, [r7, #4] 80061e4: 681b ldr r3, [r3, #0] 80061e6: 4a13 ldr r2, [pc, #76] @ (8006234 ) 80061e8: 4293 cmp r3, r2 80061ea: d11f bne.n 800622c /* USER CODE END RTC_MspInit 0 */ /** Enable access to the backup domain */ HAL_PWR_EnableBkUpAccess(); 80061ec: f004 fe9a bl 800af24 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; 80061f0: f44f 6300 mov.w r3, #2048 @ 0x800 80061f4: 60bb str r3, [r7, #8] PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; 80061f6: f44f 7300 mov.w r3, #512 @ 0x200 80061fa: 64bb str r3, [r7, #72] @ 0x48 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80061fc: f107 0308 add.w r3, r7, #8 8006200: 4618 mov r0, r3 8006202: f006 fa1b bl 800c63c 8006206: 4603 mov r3, r0 8006208: 2b00 cmp r3, #0 800620a: d001 beq.n 8006210 { Error_Handler(); 800620c: f7ff f8b0 bl 8005370 } /* Peripheral clock enable */ __HAL_RCC_RTC_ENABLE(); 8006210: f7ff fe5c bl 8005ecc __HAL_RCC_RTCAPB_CLK_ENABLE(); 8006214: f44f 6080 mov.w r0, #1024 @ 0x400 8006218: f7ff fe9b bl 8005f52 /* RTC interrupt Init */ HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 5, 0); 800621c: 2200 movs r2, #0 800621e: 2105 movs r1, #5 8006220: 2003 movs r0, #3 8006222: f000 fcc5 bl 8006bb0 HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); 8006226: 2003 movs r0, #3 8006228: f000 fcdc bl 8006be4 /* USER CODE END RTC_MspInit 1 */ } } 800622c: bf00 nop 800622e: 3758 adds r7, #88 @ 0x58 8006230: 46bd mov sp, r7 8006232: bd80 pop {r7, pc} 8006234: 40002800 .word 0x40002800 08006238 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8006238: b580 push {r7, lr} 800623a: b088 sub sp, #32 800623c: af00 add r7, sp, #0 800623e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8006240: f107 030c add.w r3, r7, #12 8006244: 2200 movs r2, #0 8006246: 601a str r2, [r3, #0] 8006248: 605a str r2, [r3, #4] 800624a: 609a str r2, [r3, #8] 800624c: 60da str r2, [r3, #12] 800624e: 611a str r2, [r3, #16] if(hspi->Instance==SPI1) 8006250: 687b ldr r3, [r7, #4] 8006252: 681b ldr r3, [r3, #0] 8006254: 4a5a ldr r2, [pc, #360] @ (80063c0 ) 8006256: 4293 cmp r3, r2 8006258: d16c bne.n 8006334 { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 800625a: f44f 5080 mov.w r0, #4096 @ 0x1000 800625e: f7ff fe91 bl 8005f84 __HAL_RCC_GPIOA_CLK_ENABLE(); 8006262: 2001 movs r0, #1 8006264: f7ff fe43 bl 8005eee /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = SPI1_IMU_SCK_Pin|SPI1_IMU_MISO_Pin|SPI1_IMU_MOSI_Pin; 8006268: 23e0 movs r3, #224 @ 0xe0 800626a: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800626c: 2302 movs r3, #2 800626e: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8006270: 2300 movs r3, #0 8006272: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8006274: 2302 movs r3, #2 8006276: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; 8006278: 2305 movs r3, #5 800627a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800627c: f107 030c add.w r3, r7, #12 8006280: 4619 mov r1, r3 8006282: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8006286: f001 f825 bl 80072d4 /* SPI1 DMA Init */ /* SPI1_TX Init */ hdma_spi1_tx.Instance = DMA1_Channel1; 800628a: 4b4e ldr r3, [pc, #312] @ (80063c4 ) 800628c: 4a4e ldr r2, [pc, #312] @ (80063c8 ) 800628e: 601a str r2, [r3, #0] hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX; 8006290: 4b4c ldr r3, [pc, #304] @ (80063c4 ) 8006292: 2207 movs r2, #7 8006294: 605a str r2, [r3, #4] hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8006296: 4b4b ldr r3, [pc, #300] @ (80063c4 ) 8006298: 2210 movs r2, #16 800629a: 609a str r2, [r3, #8] hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800629c: 4b49 ldr r3, [pc, #292] @ (80063c4 ) 800629e: 2200 movs r2, #0 80062a0: 60da str r2, [r3, #12] hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE; 80062a2: 4b48 ldr r3, [pc, #288] @ (80063c4 ) 80062a4: 2280 movs r2, #128 @ 0x80 80062a6: 611a str r2, [r3, #16] hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80062a8: 4b46 ldr r3, [pc, #280] @ (80063c4 ) 80062aa: 2200 movs r2, #0 80062ac: 615a str r2, [r3, #20] hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80062ae: 4b45 ldr r3, [pc, #276] @ (80063c4 ) 80062b0: 2200 movs r2, #0 80062b2: 619a str r2, [r3, #24] hdma_spi1_tx.Init.Mode = DMA_NORMAL; 80062b4: 4b43 ldr r3, [pc, #268] @ (80063c4 ) 80062b6: 2200 movs r2, #0 80062b8: 61da str r2, [r3, #28] hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH; 80062ba: 4b42 ldr r3, [pc, #264] @ (80063c4 ) 80062bc: f44f 5200 mov.w r2, #8192 @ 0x2000 80062c0: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) 80062c2: 4840 ldr r0, [pc, #256] @ (80063c4 ) 80062c4: f000 fcc6 bl 8006c54 80062c8: 4603 mov r3, r0 80062ca: 2b00 cmp r3, #0 80062cc: d001 beq.n 80062d2 { Error_Handler(); 80062ce: f7ff f84f bl 8005370 } __HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx); 80062d2: 687b ldr r3, [r7, #4] 80062d4: 4a3b ldr r2, [pc, #236] @ (80063c4 ) 80062d6: 655a str r2, [r3, #84] @ 0x54 80062d8: 4a3a ldr r2, [pc, #232] @ (80063c4 ) 80062da: 687b ldr r3, [r7, #4] 80062dc: 6293 str r3, [r2, #40] @ 0x28 /* SPI1_RX Init */ hdma_spi1_rx.Instance = DMA1_Channel2; 80062de: 4b3b ldr r3, [pc, #236] @ (80063cc ) 80062e0: 4a3b ldr r2, [pc, #236] @ (80063d0 ) 80062e2: 601a str r2, [r3, #0] hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX; 80062e4: 4b39 ldr r3, [pc, #228] @ (80063cc ) 80062e6: 2206 movs r2, #6 80062e8: 605a str r2, [r3, #4] hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80062ea: 4b38 ldr r3, [pc, #224] @ (80063cc ) 80062ec: 2200 movs r2, #0 80062ee: 609a str r2, [r3, #8] hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 80062f0: 4b36 ldr r3, [pc, #216] @ (80063cc ) 80062f2: 2200 movs r2, #0 80062f4: 60da str r2, [r3, #12] hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE; 80062f6: 4b35 ldr r3, [pc, #212] @ (80063cc ) 80062f8: 2280 movs r2, #128 @ 0x80 80062fa: 611a str r2, [r3, #16] hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80062fc: 4b33 ldr r3, [pc, #204] @ (80063cc ) 80062fe: 2200 movs r2, #0 8006300: 615a str r2, [r3, #20] hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8006302: 4b32 ldr r3, [pc, #200] @ (80063cc ) 8006304: 2200 movs r2, #0 8006306: 619a str r2, [r3, #24] hdma_spi1_rx.Init.Mode = DMA_NORMAL; 8006308: 4b30 ldr r3, [pc, #192] @ (80063cc ) 800630a: 2200 movs r2, #0 800630c: 61da str r2, [r3, #28] hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH; 800630e: 4b2f ldr r3, [pc, #188] @ (80063cc ) 8006310: f44f 5200 mov.w r2, #8192 @ 0x2000 8006314: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) 8006316: 482d ldr r0, [pc, #180] @ (80063cc ) 8006318: f000 fc9c bl 8006c54 800631c: 4603 mov r3, r0 800631e: 2b00 cmp r3, #0 8006320: d001 beq.n 8006326 { Error_Handler(); 8006322: f7ff f825 bl 8005370 } __HAL_LINKDMA(hspi,hdmarx,hdma_spi1_rx); 8006326: 687b ldr r3, [r7, #4] 8006328: 4a28 ldr r2, [pc, #160] @ (80063cc ) 800632a: 659a str r2, [r3, #88] @ 0x58 800632c: 4a27 ldr r2, [pc, #156] @ (80063cc ) 800632e: 687b ldr r3, [r7, #4] 8006330: 6293 str r3, [r2, #40] @ 0x28 /* USER CODE BEGIN SPI2_MspInit 1 */ /* USER CODE END SPI2_MspInit 1 */ } } 8006332: e040 b.n 80063b6 else if(hspi->Instance==SPI2) 8006334: 687b ldr r3, [r7, #4] 8006336: 681b ldr r3, [r3, #0] 8006338: 4a26 ldr r2, [pc, #152] @ (80063d4 ) 800633a: 4293 cmp r3, r2 800633c: d13b bne.n 80063b6 __HAL_RCC_SPI2_CLK_ENABLE(); 800633e: f44f 4080 mov.w r0, #16384 @ 0x4000 8006342: f7ff fe06 bl 8005f52 __HAL_RCC_GPIOC_CLK_ENABLE(); 8006346: 2004 movs r0, #4 8006348: f7ff fdd1 bl 8005eee __HAL_RCC_GPIOA_CLK_ENABLE(); 800634c: 2001 movs r0, #1 800634e: f7ff fdce bl 8005eee GPIO_InitStruct.Pin = SPI2_SD_MOSI_Pin; 8006352: 2302 movs r3, #2 8006354: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8006356: 2302 movs r3, #2 8006358: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800635a: 2300 movs r3, #0 800635c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800635e: 2303 movs r3, #3 8006360: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF3_SPI2; 8006362: 2303 movs r3, #3 8006364: 61fb str r3, [r7, #28] HAL_GPIO_Init(SPI2_SD_MOSI_GPIO_Port, &GPIO_InitStruct); 8006366: f107 030c add.w r3, r7, #12 800636a: 4619 mov r1, r3 800636c: 481a ldr r0, [pc, #104] @ (80063d8 ) 800636e: f000 ffb1 bl 80072d4 GPIO_InitStruct.Pin = SPI2_SD_MISO_Pin; 8006372: 2304 movs r3, #4 8006374: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8006376: 2302 movs r3, #2 8006378: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800637a: 2300 movs r3, #0 800637c: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800637e: 2303 movs r3, #3 8006380: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 8006382: 2305 movs r3, #5 8006384: 61fb str r3, [r7, #28] HAL_GPIO_Init(SPI2_SD_MISO_GPIO_Port, &GPIO_InitStruct); 8006386: f107 030c add.w r3, r7, #12 800638a: 4619 mov r1, r3 800638c: 4812 ldr r0, [pc, #72] @ (80063d8 ) 800638e: f000 ffa1 bl 80072d4 GPIO_InitStruct.Pin = SPI2_SD_SCK_Pin; 8006392: f44f 7300 mov.w r3, #512 @ 0x200 8006396: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8006398: 2302 movs r3, #2 800639a: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800639c: 2300 movs r3, #0 800639e: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80063a0: 2303 movs r3, #3 80063a2: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 80063a4: 2305 movs r3, #5 80063a6: 61fb str r3, [r7, #28] HAL_GPIO_Init(SPI2_SD_SCK_GPIO_Port, &GPIO_InitStruct); 80063a8: f107 030c add.w r3, r7, #12 80063ac: 4619 mov r1, r3 80063ae: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80063b2: f000 ff8f bl 80072d4 } 80063b6: bf00 nop 80063b8: 3720 adds r7, #32 80063ba: 46bd mov sp, r7 80063bc: bd80 pop {r7, pc} 80063be: bf00 nop 80063c0: 40013000 .word 0x40013000 80063c4: 200005f0 .word 0x200005f0 80063c8: 40020008 .word 0x40020008 80063cc: 20000650 .word 0x20000650 80063d0: 4002001c .word 0x4002001c 80063d4: 40003800 .word 0x40003800 80063d8: 48000800 .word 0x48000800 080063dc : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 80063dc: b580 push {r7, lr} 80063de: b082 sub sp, #8 80063e0: af00 add r7, sp, #0 80063e2: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM2) 80063e4: 687b ldr r3, [r7, #4] 80063e6: 681b ldr r3, [r3, #0] 80063e8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80063ec: d102 bne.n 80063f4 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 80063ee: 2001 movs r0, #1 80063f0: f7ff fdaf bl 8005f52 /* USER CODE END TIM2_MspInit 1 */ } } 80063f4: bf00 nop 80063f6: 3708 adds r7, #8 80063f8: 46bd mov sp, r7 80063fa: bd80 pop {r7, pc} 080063fc : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 80063fc: b580 push {r7, lr} 80063fe: b088 sub sp, #32 8006400: af00 add r7, sp, #0 8006402: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8006404: f107 030c add.w r3, r7, #12 8006408: 2200 movs r2, #0 800640a: 601a str r2, [r3, #0] 800640c: 605a str r2, [r3, #4] 800640e: 609a str r2, [r3, #8] 8006410: 60da str r2, [r3, #12] 8006412: 611a str r2, [r3, #16] if(htim->Instance==TIM2) 8006414: 687b ldr r3, [r7, #4] 8006416: 681b ldr r3, [r3, #0] 8006418: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800641c: d113 bne.n 8006446 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800641e: 2001 movs r0, #1 8006420: f7ff fd65 bl 8005eee /**TIM2 GPIO Configuration PA0 ------> TIM2_CH1 PA1 ------> TIM2_CH2 PA2 ------> TIM2_CH3 */ GPIO_InitStruct.Pin = GPIO_CONNECT_LED_Pin|GPIO_STATUS_LED_Pin|GPIO_DEBUG_LED_Pin; 8006424: 2307 movs r3, #7 8006426: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8006428: 2302 movs r3, #2 800642a: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800642c: 2300 movs r3, #0 800642e: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8006430: 2300 movs r3, #0 8006432: 61bb str r3, [r7, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8006434: 2301 movs r3, #1 8006436: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8006438: f107 030c add.w r3, r7, #12 800643c: 4619 mov r1, r3 800643e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8006442: f000 ff47 bl 80072d4 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8006446: bf00 nop 8006448: 3720 adds r7, #32 800644a: 46bd mov sp, r7 800644c: bd80 pop {r7, pc} 0800644e : { 800644e: b480 push {r7} 8006450: b085 sub sp, #20 8006452: af00 add r7, sp, #0 8006454: 6078 str r0, [r7, #4] SET_BIT(RCC->APB2ENR, Periphs); 8006456: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800645a: 6e1a ldr r2, [r3, #96] @ 0x60 800645c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006460: 687b ldr r3, [r7, #4] 8006462: 4313 orrs r3, r2 8006464: 660b str r3, [r1, #96] @ 0x60 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 8006466: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800646a: 6e1a ldr r2, [r3, #96] @ 0x60 800646c: 687b ldr r3, [r7, #4] 800646e: 4013 ands r3, r2 8006470: 60fb str r3, [r7, #12] (void)tmpreg; 8006472: 68fb ldr r3, [r7, #12] } 8006474: bf00 nop 8006476: 3714 adds r7, #20 8006478: 46bd mov sp, r7 800647a: f85d 7b04 ldr.w r7, [sp], #4 800647e: 4770 bx lr 08006480 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8006480: b580 push {r7, lr} 8006482: b08e sub sp, #56 @ 0x38 8006484: af00 add r7, sp, #0 8006486: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0; 8006488: 2300 movs r3, #0 800648a: 633b str r3, [r7, #48] @ 0x30 uint32_t uwPrescalerValue = 0; 800648c: 2300 movs r3, #0 800648e: 62fb str r3, [r7, #44] @ 0x2c uint32_t pFLatency; HAL_StatusTypeDef status = HAL_OK; 8006490: 2300 movs r3, #0 8006492: f887 3037 strb.w r3, [r7, #55] @ 0x37 /*Configure the TIM16 IRQ priority */ HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority ,0); 8006496: 2200 movs r2, #0 8006498: 6879 ldr r1, [r7, #4] 800649a: 2019 movs r0, #25 800649c: f000 fb88 bl 8006bb0 /* Enable the TIM16 global Interrupt */ HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); 80064a0: 2019 movs r0, #25 80064a2: f000 fb9f bl 8006be4 /* Enable TIM16 clock */ __HAL_RCC_TIM16_CLK_ENABLE(); 80064a6: f44f 3000 mov.w r0, #131072 @ 0x20000 80064aa: f7ff ffd0 bl 800644e /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 80064ae: f107 020c add.w r2, r7, #12 80064b2: f107 0310 add.w r3, r7, #16 80064b6: 4611 mov r1, r2 80064b8: 4618 mov r0, r3 80064ba: f005 fe2d bl 800c118 /* Compute TIM16 clock */ uwTimclock = HAL_RCC_GetPCLK2Freq(); 80064be: f005 fe15 bl 800c0ec 80064c2: 6338 str r0, [r7, #48] @ 0x30 /* Compute the prescaler value to have TIM16 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 80064c4: 6b3b ldr r3, [r7, #48] @ 0x30 80064c6: 4a21 ldr r2, [pc, #132] @ (800654c ) 80064c8: fba2 2303 umull r2, r3, r2, r3 80064cc: 0c9b lsrs r3, r3, #18 80064ce: 3b01 subs r3, #1 80064d0: 62fb str r3, [r7, #44] @ 0x2c /* Initialize TIM16 */ htim16.Instance = TIM16; 80064d2: 4b1f ldr r3, [pc, #124] @ (8006550 ) 80064d4: 4a1f ldr r2, [pc, #124] @ (8006554 ) 80064d6: 601a str r2, [r3, #0] * Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base. * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. * ClockDivision = 0 * Counter direction = Up */ htim16.Init.Period = (1000000U / 1000U) - 1U; 80064d8: 4b1d ldr r3, [pc, #116] @ (8006550 ) 80064da: f240 32e7 movw r2, #999 @ 0x3e7 80064de: 60da str r2, [r3, #12] htim16.Init.Prescaler = uwPrescalerValue; 80064e0: 4a1b ldr r2, [pc, #108] @ (8006550 ) 80064e2: 6afb ldr r3, [r7, #44] @ 0x2c 80064e4: 6053 str r3, [r2, #4] htim16.Init.ClockDivision = 0; 80064e6: 4b1a ldr r3, [pc, #104] @ (8006550 ) 80064e8: 2200 movs r2, #0 80064ea: 611a str r2, [r3, #16] htim16.Init.CounterMode = TIM_COUNTERMODE_UP; 80064ec: 4b18 ldr r3, [pc, #96] @ (8006550 ) 80064ee: 2200 movs r2, #0 80064f0: 609a str r2, [r3, #8] status = HAL_TIM_Base_Init(&htim16); 80064f2: 4817 ldr r0, [pc, #92] @ (8006550 ) 80064f4: f007 ffa4 bl 800e440 80064f8: 4603 mov r3, r0 80064fa: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (status == HAL_OK) 80064fe: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8006502: 2b00 cmp r3, #0 8006504: d11b bne.n 800653e /* Register callback */ HAL_TIM_RegisterCallback(&htim16, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&htim16); 8006506: 4812 ldr r0, [pc, #72] @ (8006550 ) 8006508: f007 fffc bl 800e504 800650c: 4603 mov r3, r0 800650e: f887 3037 strb.w r3, [r7, #55] @ 0x37 if (status == HAL_OK) 8006512: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8006516: 2b00 cmp r3, #0 8006518: d111 bne.n 800653e { /* Enable the TIM16 global Interrupt */ HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); 800651a: 2019 movs r0, #25 800651c: f000 fb62 bl 8006be4 /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8006520: 687b ldr r3, [r7, #4] 8006522: 2b0f cmp r3, #15 8006524: d808 bhi.n 8006538 { /* Configure the TIM IRQ priority */ HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, TickPriority, 0U); 8006526: 2200 movs r2, #0 8006528: 6879 ldr r1, [r7, #4] 800652a: 2019 movs r0, #25 800652c: f000 fb40 bl 8006bb0 uwTickPrio = TickPriority; 8006530: 4a09 ldr r2, [pc, #36] @ (8006558 ) 8006532: 687b ldr r3, [r7, #4] 8006534: 6013 str r3, [r2, #0] 8006536: e002 b.n 800653e } else { status = HAL_ERROR; 8006538: 2301 movs r3, #1 800653a: f887 3037 strb.w r3, [r7, #55] @ 0x37 } } } /* Return function status */ return status; 800653e: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 } 8006542: 4618 mov r0, r3 8006544: 3738 adds r7, #56 @ 0x38 8006546: 46bd mov sp, r7 8006548: bd80 pop {r7, pc} 800654a: bf00 nop 800654c: 431bde83 .word 0x431bde83 8006550: 20000730 .word 0x20000730 8006554: 40014400 .word 0x40014400 8006558: 20000010 .word 0x20000010 0800655c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800655c: b480 push {r7} 800655e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8006560: bf00 nop 8006562: e7fd b.n 8006560 08006564 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8006564: b480 push {r7} 8006566: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8006568: bf00 nop 800656a: e7fd b.n 8006568 0800656c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800656c: b480 push {r7} 800656e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8006570: bf00 nop 8006572: e7fd b.n 8006570 08006574 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8006574: b480 push {r7} 8006576: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8006578: bf00 nop 800657a: e7fd b.n 8006578 0800657c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800657c: b480 push {r7} 800657e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8006580: bf00 nop 8006582: e7fd b.n 8006580 08006584 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8006584: b480 push {r7} 8006586: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8006588: bf00 nop 800658a: 46bd mov sp, r7 800658c: f85d 7b04 ldr.w r7, [sp], #4 8006590: 4770 bx lr 08006592 : /** * @brief This function handles RTC wake-up interrupt through EXTI line 19. */ void RTC_WKUP_IRQHandler(void) { 8006592: b580 push {r7, lr} 8006594: af00 add r7, sp, #0 /* USER CODE BEGIN RTC_WKUP_IRQn 0 */ /* USER CODE END RTC_WKUP_IRQn 0 */ HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc); 8006596: f7fd fe0d bl 80041b4 /* USER CODE BEGIN RTC_WKUP_IRQn 1 */ /* USER CODE END RTC_WKUP_IRQn 1 */ } 800659a: bf00 nop 800659c: bd80 pop {r7, pc} ... 080065a0 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 80065a0: b580 push {r7, lr} 80065a2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_spi1_tx); 80065a4: 4802 ldr r0, [pc, #8] @ (80065b0 ) 80065a6: f000 fd36 bl 8007016 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 80065aa: bf00 nop 80065ac: bd80 pop {r7, pc} 80065ae: bf00 nop 80065b0: 200005f0 .word 0x200005f0 080065b4 : /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { 80065b4: b580 push {r7, lr} 80065b6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_spi1_rx); 80065b8: 4802 ldr r0, [pc, #8] @ (80065c4 ) 80065ba: f000 fd2c bl 8007016 /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } 80065be: bf00 nop 80065c0: bd80 pop {r7, pc} 80065c2: bf00 nop 80065c4: 20000650 .word 0x20000650 080065c8 : /** * @brief This function handles DMA1 channel3 global interrupt. */ void DMA1_Channel3_IRQHandler(void) { 80065c8: b580 push {r7, lr} 80065ca: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */ /* USER CODE END DMA1_Channel3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_i2c1_tx); 80065cc: 4802 ldr r0, [pc, #8] @ (80065d8 ) 80065ce: f000 fd22 bl 8007016 /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */ /* USER CODE END DMA1_Channel3_IRQn 1 */ } 80065d2: bf00 nop 80065d4: bd80 pop {r7, pc} 80065d6: bf00 nop 80065d8: 20000408 .word 0x20000408 080065dc : /** * @brief This function handles DMA1 channel4 global interrupt. */ void DMA1_Channel4_IRQHandler(void) { 80065dc: b580 push {r7, lr} 80065de: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */ /* USER CODE END DMA1_Channel4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_i2c1_rx); 80065e0: 4802 ldr r0, [pc, #8] @ (80065ec ) 80065e2: f000 fd18 bl 8007016 /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */ /* USER CODE END DMA1_Channel4_IRQn 1 */ } 80065e6: bf00 nop 80065e8: bd80 pop {r7, pc} 80065ea: bf00 nop 80065ec: 20000468 .word 0x20000468 080065f0 : /** * @brief This function handles USB low priority interrupt, USB wake-up interrupt through EXTI line 28. */ void USB_LP_IRQHandler(void) { 80065f0: b580 push {r7, lr} 80065f2: af00 add r7, sp, #0 /* USER CODE BEGIN USB_LP_IRQn 0 */ /* USER CODE END USB_LP_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_FS); 80065f4: 4802 ldr r0, [pc, #8] @ (8006600 ) 80065f6: f003 f843 bl 8009680 /* USER CODE BEGIN USB_LP_IRQn 1 */ /* USER CODE END USB_LP_IRQn 1 */ } 80065fa: bf00 nop 80065fc: bd80 pop {r7, pc} 80065fe: bf00 nop 8006600: 20013698 .word 0x20013698 08006604 : /** * @brief This function handles TIM1 update interrupt and TIM16 global interrupt. */ void TIM1_UP_TIM16_IRQHandler(void) { 8006604: b580 push {r7, lr} 8006606: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */ /* USER CODE END TIM1_UP_TIM16_IRQn 0 */ HAL_TIM_IRQHandler(&htim16); 8006608: 4802 ldr r0, [pc, #8] @ (8006614 ) 800660a: f008 f820 bl 800e64e /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */ /* USER CODE END TIM1_UP_TIM16_IRQn 1 */ } 800660e: bf00 nop 8006610: bd80 pop {r7, pc} 8006612: bf00 nop 8006614: 20000730 .word 0x20000730 08006618 : /** * @brief This function handles I2C1 event interrupt. */ void I2C1_EV_IRQHandler(void) { 8006618: b580 push {r7, lr} 800661a: af00 add r7, sp, #0 /* USER CODE BEGIN I2C1_EV_IRQn 0 */ /* USER CODE END I2C1_EV_IRQn 0 */ HAL_I2C_EV_IRQHandler(&hi2c1); 800661c: 4802 ldr r0, [pc, #8] @ (8006628 ) 800661e: f001 fa85 bl 8007b2c /* USER CODE BEGIN I2C1_EV_IRQn 1 */ /* USER CODE END I2C1_EV_IRQn 1 */ } 8006622: bf00 nop 8006624: bd80 pop {r7, pc} 8006626: bf00 nop 8006628: 200003b4 .word 0x200003b4 0800662c : /** * @brief This function handles I2C1 error interrupt. */ void I2C1_ER_IRQHandler(void) { 800662c: b580 push {r7, lr} 800662e: af00 add r7, sp, #0 /* USER CODE BEGIN I2C1_ER_IRQn 0 */ /* USER CODE END I2C1_ER_IRQn 0 */ HAL_I2C_ER_IRQHandler(&hi2c1); 8006630: 4802 ldr r0, [pc, #8] @ (800663c ) 8006632: f001 fa95 bl 8007b60 /* USER CODE BEGIN I2C1_ER_IRQn 1 */ /* USER CODE END I2C1_ER_IRQn 1 */ } 8006636: bf00 nop 8006638: bd80 pop {r7, pc} 800663a: bf00 nop 800663c: 200003b4 .word 0x200003b4 08006640 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8006640: b580 push {r7, lr} 8006642: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_IMU_INT_Pin); 8006644: f44f 6080 mov.w r0, #1024 @ 0x400 8006648: f000 ffcc bl 80075e4 HAL_GPIO_EXTI_IRQHandler(GPIO_MAGN_INT_Pin); 800664c: f44f 6000 mov.w r0, #2048 @ 0x800 8006650: f000 ffc8 bl 80075e4 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 8006654: bf00 nop 8006656: bd80 pop {r7, pc} 08006658 : /** * @brief This function handles IPCC RX occupied interrupt. */ void IPCC_C1_RX_IRQHandler(void) { 8006658: b580 push {r7, lr} 800665a: af00 add r7, sp, #0 /* USER CODE BEGIN IPCC_C1_RX_IRQn 0 */ /* USER CODE END IPCC_C1_RX_IRQn 0 */ HAL_IPCC_RX_IRQHandler(&hipcc); 800665c: f011 ff66 bl 801852c /* USER CODE BEGIN IPCC_C1_RX_IRQn 1 */ /* USER CODE END IPCC_C1_RX_IRQn 1 */ } 8006660: bf00 nop 8006662: bd80 pop {r7, pc} 08006664 : /** * @brief This function handles IPCC TX free interrupt. */ void IPCC_C1_TX_IRQHandler(void) { 8006664: b580 push {r7, lr} 8006666: af00 add r7, sp, #0 /* USER CODE BEGIN IPCC_C1_TX_IRQn 0 */ /* USER CODE END IPCC_C1_TX_IRQn 0 */ HAL_IPCC_TX_IRQHandler(&hipcc); 8006668: f011 ff96 bl 8018598 /* USER CODE BEGIN IPCC_C1_TX_IRQn 1 */ /* USER CODE END IPCC_C1_TX_IRQn 1 */ } 800666c: bf00 nop 800666e: bd80 pop {r7, pc} 08006670 : /** * @brief This function handles HSEM global interrupt. */ void HSEM_IRQHandler(void) { 8006670: b580 push {r7, lr} 8006672: af00 add r7, sp, #0 /* USER CODE BEGIN HSEM_IRQn 0 */ /* USER CODE END HSEM_IRQn 0 */ HAL_HSEM_IRQHandler(); 8006674: f000 ffce bl 8007614 /* USER CODE BEGIN HSEM_IRQn 1 */ /* USER CODE END HSEM_IRQn 1 */ } 8006678: bf00 nop 800667a: bd80 pop {r7, pc} 0800667c <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800667c: b480 push {r7} 800667e: af00 add r7, sp, #0 return 1; 8006680: 2301 movs r3, #1 } 8006682: 4618 mov r0, r3 8006684: 46bd mov sp, r7 8006686: f85d 7b04 ldr.w r7, [sp], #4 800668a: 4770 bx lr 0800668c <_kill>: int _kill(int pid, int sig) { 800668c: b580 push {r7, lr} 800668e: b082 sub sp, #8 8006690: af00 add r7, sp, #0 8006692: 6078 str r0, [r7, #4] 8006694: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 8006696: f013 fed5 bl 801a444 <__errno> 800669a: 4603 mov r3, r0 800669c: 2216 movs r2, #22 800669e: 601a str r2, [r3, #0] return -1; 80066a0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 80066a4: 4618 mov r0, r3 80066a6: 3708 adds r7, #8 80066a8: 46bd mov sp, r7 80066aa: bd80 pop {r7, pc} 080066ac <_exit>: void _exit (int status) { 80066ac: b580 push {r7, lr} 80066ae: b082 sub sp, #8 80066b0: af00 add r7, sp, #0 80066b2: 6078 str r0, [r7, #4] _kill(status, -1); 80066b4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80066b8: 6878 ldr r0, [r7, #4] 80066ba: f7ff ffe7 bl 800668c <_kill> while (1) {} /* Make sure we hang here */ 80066be: bf00 nop 80066c0: e7fd b.n 80066be <_exit+0x12> 080066c2 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 80066c2: b580 push {r7, lr} 80066c4: b086 sub sp, #24 80066c6: af00 add r7, sp, #0 80066c8: 60f8 str r0, [r7, #12] 80066ca: 60b9 str r1, [r7, #8] 80066cc: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80066ce: 2300 movs r3, #0 80066d0: 617b str r3, [r7, #20] 80066d2: e00a b.n 80066ea <_read+0x28> { *ptr++ = __io_getchar(); 80066d4: f3af 8000 nop.w 80066d8: 4601 mov r1, r0 80066da: 68bb ldr r3, [r7, #8] 80066dc: 1c5a adds r2, r3, #1 80066de: 60ba str r2, [r7, #8] 80066e0: b2ca uxtb r2, r1 80066e2: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80066e4: 697b ldr r3, [r7, #20] 80066e6: 3301 adds r3, #1 80066e8: 617b str r3, [r7, #20] 80066ea: 697a ldr r2, [r7, #20] 80066ec: 687b ldr r3, [r7, #4] 80066ee: 429a cmp r2, r3 80066f0: dbf0 blt.n 80066d4 <_read+0x12> } return len; 80066f2: 687b ldr r3, [r7, #4] } 80066f4: 4618 mov r0, r3 80066f6: 3718 adds r7, #24 80066f8: 46bd mov sp, r7 80066fa: bd80 pop {r7, pc} 080066fc <_close>: } return len; } int _close(int file) { 80066fc: b480 push {r7} 80066fe: b083 sub sp, #12 8006700: af00 add r7, sp, #0 8006702: 6078 str r0, [r7, #4] (void)file; return -1; 8006704: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 8006708: 4618 mov r0, r3 800670a: 370c adds r7, #12 800670c: 46bd mov sp, r7 800670e: f85d 7b04 ldr.w r7, [sp], #4 8006712: 4770 bx lr 08006714 <_fstat>: int _fstat(int file, struct stat *st) { 8006714: b480 push {r7} 8006716: b083 sub sp, #12 8006718: af00 add r7, sp, #0 800671a: 6078 str r0, [r7, #4] 800671c: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800671e: 683b ldr r3, [r7, #0] 8006720: f44f 5200 mov.w r2, #8192 @ 0x2000 8006724: 605a str r2, [r3, #4] return 0; 8006726: 2300 movs r3, #0 } 8006728: 4618 mov r0, r3 800672a: 370c adds r7, #12 800672c: 46bd mov sp, r7 800672e: f85d 7b04 ldr.w r7, [sp], #4 8006732: 4770 bx lr 08006734 <_isatty>: int _isatty(int file) { 8006734: b480 push {r7} 8006736: b083 sub sp, #12 8006738: af00 add r7, sp, #0 800673a: 6078 str r0, [r7, #4] (void)file; return 1; 800673c: 2301 movs r3, #1 } 800673e: 4618 mov r0, r3 8006740: 370c adds r7, #12 8006742: 46bd mov sp, r7 8006744: f85d 7b04 ldr.w r7, [sp], #4 8006748: 4770 bx lr 0800674a <_lseek>: int _lseek(int file, int ptr, int dir) { 800674a: b480 push {r7} 800674c: b085 sub sp, #20 800674e: af00 add r7, sp, #0 8006750: 60f8 str r0, [r7, #12] 8006752: 60b9 str r1, [r7, #8] 8006754: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 8006756: 2300 movs r3, #0 } 8006758: 4618 mov r0, r3 800675a: 3714 adds r7, #20 800675c: 46bd mov sp, r7 800675e: f85d 7b04 ldr.w r7, [sp], #4 8006762: 4770 bx lr 08006764 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8006764: b580 push {r7, lr} 8006766: b086 sub sp, #24 8006768: af00 add r7, sp, #0 800676a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800676c: 4a14 ldr r2, [pc, #80] @ (80067c0 <_sbrk+0x5c>) 800676e: 4b15 ldr r3, [pc, #84] @ (80067c4 <_sbrk+0x60>) 8006770: 1ad3 subs r3, r2, r3 8006772: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8006774: 697b ldr r3, [r7, #20] 8006776: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8006778: 4b13 ldr r3, [pc, #76] @ (80067c8 <_sbrk+0x64>) 800677a: 681b ldr r3, [r3, #0] 800677c: 2b00 cmp r3, #0 800677e: d102 bne.n 8006786 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8006780: 4b11 ldr r3, [pc, #68] @ (80067c8 <_sbrk+0x64>) 8006782: 4a12 ldr r2, [pc, #72] @ (80067cc <_sbrk+0x68>) 8006784: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8006786: 4b10 ldr r3, [pc, #64] @ (80067c8 <_sbrk+0x64>) 8006788: 681a ldr r2, [r3, #0] 800678a: 687b ldr r3, [r7, #4] 800678c: 4413 add r3, r2 800678e: 693a ldr r2, [r7, #16] 8006790: 429a cmp r2, r3 8006792: d207 bcs.n 80067a4 <_sbrk+0x40> { errno = ENOMEM; 8006794: f013 fe56 bl 801a444 <__errno> 8006798: 4603 mov r3, r0 800679a: 220c movs r2, #12 800679c: 601a str r2, [r3, #0] return (void *)-1; 800679e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80067a2: e009 b.n 80067b8 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80067a4: 4b08 ldr r3, [pc, #32] @ (80067c8 <_sbrk+0x64>) 80067a6: 681b ldr r3, [r3, #0] 80067a8: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80067aa: 4b07 ldr r3, [pc, #28] @ (80067c8 <_sbrk+0x64>) 80067ac: 681a ldr r2, [r3, #0] 80067ae: 687b ldr r3, [r7, #4] 80067b0: 4413 add r3, r2 80067b2: 4a05 ldr r2, [pc, #20] @ (80067c8 <_sbrk+0x64>) 80067b4: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80067b6: 68fb ldr r3, [r7, #12] } 80067b8: 4618 mov r0, r3 80067ba: 3718 adds r7, #24 80067bc: 46bd mov sp, r7 80067be: bd80 pop {r7, pc} 80067c0: 20030000 .word 0x20030000 80067c4: 00000400 .word 0x00000400 80067c8: 2000077c .word 0x2000077c 80067cc: 20013ce8 .word 0x20013ce8 080067d0 : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 80067d0: b480 push {r7} 80067d2: af00 add r7, sp, #0 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; #endif /* USER_VECT_TAB_ADDRESS */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */ 80067d4: 4b24 ldr r3, [pc, #144] @ (8006868 ) 80067d6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80067da: 4a23 ldr r2, [pc, #140] @ (8006868 ) 80067dc: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80067e0: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* FPU */ /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ RCC->CR |= RCC_CR_MSION; 80067e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80067e8: 681b ldr r3, [r3, #0] 80067ea: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80067ee: f043 0301 orr.w r3, r3, #1 80067f2: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00070000U; 80067f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80067f8: f44f 22e0 mov.w r2, #458752 @ 0x70000 80067fc: 609a str r2, [r3, #8] /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */ RCC->CR &= (uint32_t)0xFAF6FEFBU; 80067fe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006802: 681a ldr r2, [r3, #0] 8006804: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006808: 4b18 ldr r3, [pc, #96] @ (800686c ) 800680a: 4013 ands r3, r2 800680c: 600b str r3, [r1, #0] /*!< Reset LSI1 and LSI2 bits */ RCC->CSR &= (uint32_t)0xFFFFFFFAU; 800680e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006812: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8006816: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800681a: f023 0305 bic.w r3, r3, #5 800681e: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /*!< Reset HSI48ON bit */ RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; 8006822: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006826: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800682a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800682e: f023 0301 bic.w r3, r3, #1 8006832: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x22041000U; 8006836: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800683a: 4a0d ldr r2, [pc, #52] @ (8006870 ) 800683c: 60da str r2, [r3, #12] #if defined(STM32WB55xx) || defined(STM32WB5Mxx) /* Reset PLLSAI1CFGR register */ RCC->PLLSAI1CFGR = 0x22041000U; 800683e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006842: 4a0b ldr r2, [pc, #44] @ (8006870 ) 8006844: 611a str r2, [r3, #16] #endif /* STM32WB55xx || STM32WB5Mxx */ /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8006846: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800684a: 681b ldr r3, [r3, #0] 800684c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8006850: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8006854: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8006856: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800685a: 2200 movs r2, #0 800685c: 619a str r2, [r3, #24] } 800685e: bf00 nop 8006860: 46bd mov sp, r7 8006862: f85d 7b04 ldr.w r7, [sp], #4 8006866: 4770 bx lr 8006868: e000ed00 .word 0xe000ed00 800686c: faf6fefb .word 0xfaf6fefb 8006870: 22041000 .word 0x22041000 08006874 : bl LoopCopyDataInit .endm .section .text.data_initializers CopyDataInit: ldr r4, [r2, r3] 8006874: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8006876: 50c4 str r4, [r0, r3] adds r3, r3, #4 8006878: 3304 adds r3, #4 0800687a : LoopCopyDataInit: adds r4, r0, r3 800687a: 18c4 adds r4, r0, r3 cmp r4, r1 800687c: 428c cmp r4, r1 bcc CopyDataInit 800687e: d3f9 bcc.n 8006874 bx lr 8006880: 4770 bx lr 08006882 : FillZerobss: str r3, [r0] 8006882: 6003 str r3, [r0, #0] adds r0, r0, #4 8006884: 3004 adds r0, #4 08006886 : LoopFillZerobss: cmp r0, r1 8006886: 4288 cmp r0, r1 bcc FillZerobss 8006888: d3fb bcc.n 8006882 bx lr 800688a: 4770 bx lr 0800688c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 800688c: 480c ldr r0, [pc, #48] @ (80068c0 ) mov sp, r0 /* set stack pointer */ 800688e: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8006890: f7ff ff9e bl 80067d0 /* Copy the data segment initializers from flash to SRAM */ INIT_DATA _sdata, _edata, _sidata 8006894: 480b ldr r0, [pc, #44] @ (80068c4 ) 8006896: 490c ldr r1, [pc, #48] @ (80068c8 ) 8006898: 4a0c ldr r2, [pc, #48] @ (80068cc ) 800689a: 2300 movs r3, #0 800689c: f7ff ffed bl 800687a INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2 80068a0: 480b ldr r0, [pc, #44] @ (80068d0 ) 80068a2: 490c ldr r1, [pc, #48] @ (80068d4 ) 80068a4: 4a0c ldr r2, [pc, #48] @ (80068d8 ) 80068a6: 2300 movs r3, #0 80068a8: f7ff ffe7 bl 800687a /* Zero fill the bss segments. */ INIT_BSS _sbss, _ebss 80068ac: 480b ldr r0, [pc, #44] @ (80068dc ) 80068ae: 490c ldr r1, [pc, #48] @ (80068e0 ) 80068b0: 2300 movs r3, #0 80068b2: f7ff ffe8 bl 8006886 /* Call static constructors */ bl __libc_init_array 80068b6: f013 fdcb bl 801a450 <__libc_init_array> /* Call the application s entry point.*/ bl main 80068ba: f7fd ffd7 bl 800486c
080068be : LoopForever: b LoopForever 80068be: e7fe b.n 80068be ldr r0, =_estack 80068c0: 20030000 .word 0x20030000 INIT_DATA _sdata, _edata, _sidata 80068c4: 20000008 .word 0x20000008 80068c8: 200002d8 .word 0x200002d8 80068cc: 0801ea40 .word 0x0801ea40 INIT_DATA _sMB_MEM2, _eMB_MEM2, _siMB_MEM2 80068d0: 200300d8 .word 0x200300d8 80068d4: 2003094a .word 0x2003094a 80068d8: 0801ed21 .word 0x0801ed21 INIT_BSS _sbss, _ebss 80068dc: 200002ec .word 0x200002ec 80068e0: 20013ce8 .word 0x20013ce8 080068e4 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80068e4: e7fe b.n 80068e4 ... 080068e8 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80068e8: b580 push {r7, lr} 80068ea: b082 sub sp, #8 80068ec: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 80068ee: 2300 movs r3, #0 80068f0: 71fb strb r3, [r7, #7] #if (DATA_CACHE_ENABLE == 0U) __HAL_FLASH_DATA_CACHE_DISABLE(); #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80068f2: 4b0c ldr r3, [pc, #48] @ (8006924 ) 80068f4: 681b ldr r3, [r3, #0] 80068f6: 4a0b ldr r2, [pc, #44] @ (8006924 ) 80068f8: f443 7380 orr.w r3, r3, #256 @ 0x100 80068fc: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80068fe: 2003 movs r0, #3 8006900: f000 f94b bl 8006b9a /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8006904: 200f movs r0, #15 8006906: f7ff fdbb bl 8006480 800690a: 4603 mov r3, r0 800690c: 2b00 cmp r3, #0 800690e: d002 beq.n 8006916 { status = HAL_ERROR; 8006910: 2301 movs r3, #1 8006912: 71fb strb r3, [r7, #7] 8006914: e001 b.n 800691a } else { /* Init the low level hardware */ HAL_MspInit(); 8006916: f7ff fb61 bl 8005fdc } /* Return function status */ return status; 800691a: 79fb ldrb r3, [r7, #7] } 800691c: 4618 mov r0, r3 800691e: 3708 adds r7, #8 8006920: 46bd mov sp, r7 8006922: bd80 pop {r7, pc} 8006924: 58004000 .word 0x58004000 08006928 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8006928: b480 push {r7} 800692a: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 800692c: 4b06 ldr r3, [pc, #24] @ (8006948 ) 800692e: 781b ldrb r3, [r3, #0] 8006930: 461a mov r2, r3 8006932: 4b06 ldr r3, [pc, #24] @ (800694c ) 8006934: 681b ldr r3, [r3, #0] 8006936: 4413 add r3, r2 8006938: 4a04 ldr r2, [pc, #16] @ (800694c ) 800693a: 6013 str r3, [r2, #0] } 800693c: bf00 nop 800693e: 46bd mov sp, r7 8006940: f85d 7b04 ldr.w r7, [sp], #4 8006944: 4770 bx lr 8006946: bf00 nop 8006948: 20000014 .word 0x20000014 800694c: 20000780 .word 0x20000780 08006950 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8006950: b480 push {r7} 8006952: af00 add r7, sp, #0 return uwTick; 8006954: 4b03 ldr r3, [pc, #12] @ (8006964 ) 8006956: 681b ldr r3, [r3, #0] } 8006958: 4618 mov r0, r3 800695a: 46bd mov sp, r7 800695c: f85d 7b04 ldr.w r7, [sp], #4 8006960: 4770 bx lr 8006962: bf00 nop 8006964: 20000780 .word 0x20000780 08006968 : /** * @brief This function returns a tick priority. * @retval tick priority */ uint32_t HAL_GetTickPrio(void) { 8006968: b480 push {r7} 800696a: af00 add r7, sp, #0 return uwTickPrio; 800696c: 4b03 ldr r3, [pc, #12] @ (800697c ) 800696e: 681b ldr r3, [r3, #0] } 8006970: 4618 mov r0, r3 8006972: 46bd mov sp, r7 8006974: f85d 7b04 ldr.w r7, [sp], #4 8006978: 4770 bx lr 800697a: bf00 nop 800697c: 20000010 .word 0x20000010 08006980 <__NVIC_SetPriorityGrouping>: { 8006980: b480 push {r7} 8006982: b085 sub sp, #20 8006984: af00 add r7, sp, #0 8006986: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8006988: 687b ldr r3, [r7, #4] 800698a: f003 0307 and.w r3, r3, #7 800698e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8006990: 4b0c ldr r3, [pc, #48] @ (80069c4 <__NVIC_SetPriorityGrouping+0x44>) 8006992: 68db ldr r3, [r3, #12] 8006994: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8006996: 68ba ldr r2, [r7, #8] 8006998: f64f 03ff movw r3, #63743 @ 0xf8ff 800699c: 4013 ands r3, r2 800699e: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80069a0: 68fb ldr r3, [r7, #12] 80069a2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80069a4: 68bb ldr r3, [r7, #8] 80069a6: 4313 orrs r3, r2 reg_value = (reg_value | 80069a8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80069ac: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80069b0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80069b2: 4a04 ldr r2, [pc, #16] @ (80069c4 <__NVIC_SetPriorityGrouping+0x44>) 80069b4: 68bb ldr r3, [r7, #8] 80069b6: 60d3 str r3, [r2, #12] } 80069b8: bf00 nop 80069ba: 3714 adds r7, #20 80069bc: 46bd mov sp, r7 80069be: f85d 7b04 ldr.w r7, [sp], #4 80069c2: 4770 bx lr 80069c4: e000ed00 .word 0xe000ed00 080069c8 <__NVIC_GetPriorityGrouping>: { 80069c8: b480 push {r7} 80069ca: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80069cc: 4b04 ldr r3, [pc, #16] @ (80069e0 <__NVIC_GetPriorityGrouping+0x18>) 80069ce: 68db ldr r3, [r3, #12] 80069d0: 0a1b lsrs r3, r3, #8 80069d2: f003 0307 and.w r3, r3, #7 } 80069d6: 4618 mov r0, r3 80069d8: 46bd mov sp, r7 80069da: f85d 7b04 ldr.w r7, [sp], #4 80069de: 4770 bx lr 80069e0: e000ed00 .word 0xe000ed00 080069e4 <__NVIC_EnableIRQ>: { 80069e4: b480 push {r7} 80069e6: b083 sub sp, #12 80069e8: af00 add r7, sp, #0 80069ea: 4603 mov r3, r0 80069ec: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80069ee: f997 3007 ldrsb.w r3, [r7, #7] 80069f2: 2b00 cmp r3, #0 80069f4: db0b blt.n 8006a0e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80069f6: 79fb ldrb r3, [r7, #7] 80069f8: f003 021f and.w r2, r3, #31 80069fc: 4907 ldr r1, [pc, #28] @ (8006a1c <__NVIC_EnableIRQ+0x38>) 80069fe: f997 3007 ldrsb.w r3, [r7, #7] 8006a02: 095b lsrs r3, r3, #5 8006a04: 2001 movs r0, #1 8006a06: fa00 f202 lsl.w r2, r0, r2 8006a0a: f841 2023 str.w r2, [r1, r3, lsl #2] } 8006a0e: bf00 nop 8006a10: 370c adds r7, #12 8006a12: 46bd mov sp, r7 8006a14: f85d 7b04 ldr.w r7, [sp], #4 8006a18: 4770 bx lr 8006a1a: bf00 nop 8006a1c: e000e100 .word 0xe000e100 08006a20 <__NVIC_DisableIRQ>: { 8006a20: b480 push {r7} 8006a22: b083 sub sp, #12 8006a24: af00 add r7, sp, #0 8006a26: 4603 mov r3, r0 8006a28: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8006a2a: f997 3007 ldrsb.w r3, [r7, #7] 8006a2e: 2b00 cmp r3, #0 8006a30: db12 blt.n 8006a58 <__NVIC_DisableIRQ+0x38> NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8006a32: 79fb ldrb r3, [r7, #7] 8006a34: f003 021f and.w r2, r3, #31 8006a38: 490a ldr r1, [pc, #40] @ (8006a64 <__NVIC_DisableIRQ+0x44>) 8006a3a: f997 3007 ldrsb.w r3, [r7, #7] 8006a3e: 095b lsrs r3, r3, #5 8006a40: 2001 movs r0, #1 8006a42: fa00 f202 lsl.w r2, r0, r2 8006a46: 3320 adds r3, #32 8006a48: f841 2023 str.w r2, [r1, r3, lsl #2] __ASM volatile ("dsb 0xF":::"memory"); 8006a4c: f3bf 8f4f dsb sy } 8006a50: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8006a52: f3bf 8f6f isb sy } 8006a56: bf00 nop } 8006a58: bf00 nop 8006a5a: 370c adds r7, #12 8006a5c: 46bd mov sp, r7 8006a5e: f85d 7b04 ldr.w r7, [sp], #4 8006a62: 4770 bx lr 8006a64: e000e100 .word 0xe000e100 08006a68 <__NVIC_SetPendingIRQ>: { 8006a68: b480 push {r7} 8006a6a: b083 sub sp, #12 8006a6c: af00 add r7, sp, #0 8006a6e: 4603 mov r3, r0 8006a70: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8006a72: f997 3007 ldrsb.w r3, [r7, #7] 8006a76: 2b00 cmp r3, #0 8006a78: db0c blt.n 8006a94 <__NVIC_SetPendingIRQ+0x2c> NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8006a7a: 79fb ldrb r3, [r7, #7] 8006a7c: f003 021f and.w r2, r3, #31 8006a80: 4907 ldr r1, [pc, #28] @ (8006aa0 <__NVIC_SetPendingIRQ+0x38>) 8006a82: f997 3007 ldrsb.w r3, [r7, #7] 8006a86: 095b lsrs r3, r3, #5 8006a88: 2001 movs r0, #1 8006a8a: fa00 f202 lsl.w r2, r0, r2 8006a8e: 3340 adds r3, #64 @ 0x40 8006a90: f841 2023 str.w r2, [r1, r3, lsl #2] } 8006a94: bf00 nop 8006a96: 370c adds r7, #12 8006a98: 46bd mov sp, r7 8006a9a: f85d 7b04 ldr.w r7, [sp], #4 8006a9e: 4770 bx lr 8006aa0: e000e100 .word 0xe000e100 08006aa4 <__NVIC_ClearPendingIRQ>: { 8006aa4: b480 push {r7} 8006aa6: b083 sub sp, #12 8006aa8: af00 add r7, sp, #0 8006aaa: 4603 mov r3, r0 8006aac: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8006aae: f997 3007 ldrsb.w r3, [r7, #7] 8006ab2: 2b00 cmp r3, #0 8006ab4: db0c blt.n 8006ad0 <__NVIC_ClearPendingIRQ+0x2c> NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8006ab6: 79fb ldrb r3, [r7, #7] 8006ab8: f003 021f and.w r2, r3, #31 8006abc: 4907 ldr r1, [pc, #28] @ (8006adc <__NVIC_ClearPendingIRQ+0x38>) 8006abe: f997 3007 ldrsb.w r3, [r7, #7] 8006ac2: 095b lsrs r3, r3, #5 8006ac4: 2001 movs r0, #1 8006ac6: fa00 f202 lsl.w r2, r0, r2 8006aca: 3360 adds r3, #96 @ 0x60 8006acc: f841 2023 str.w r2, [r1, r3, lsl #2] } 8006ad0: bf00 nop 8006ad2: 370c adds r7, #12 8006ad4: 46bd mov sp, r7 8006ad6: f85d 7b04 ldr.w r7, [sp], #4 8006ada: 4770 bx lr 8006adc: e000e100 .word 0xe000e100 08006ae0 <__NVIC_SetPriority>: { 8006ae0: b480 push {r7} 8006ae2: b083 sub sp, #12 8006ae4: af00 add r7, sp, #0 8006ae6: 4603 mov r3, r0 8006ae8: 6039 str r1, [r7, #0] 8006aea: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8006aec: f997 3007 ldrsb.w r3, [r7, #7] 8006af0: 2b00 cmp r3, #0 8006af2: db0a blt.n 8006b0a <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8006af4: 683b ldr r3, [r7, #0] 8006af6: b2da uxtb r2, r3 8006af8: 490c ldr r1, [pc, #48] @ (8006b2c <__NVIC_SetPriority+0x4c>) 8006afa: f997 3007 ldrsb.w r3, [r7, #7] 8006afe: 0112 lsls r2, r2, #4 8006b00: b2d2 uxtb r2, r2 8006b02: 440b add r3, r1 8006b04: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8006b08: e00a b.n 8006b20 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8006b0a: 683b ldr r3, [r7, #0] 8006b0c: b2da uxtb r2, r3 8006b0e: 4908 ldr r1, [pc, #32] @ (8006b30 <__NVIC_SetPriority+0x50>) 8006b10: 79fb ldrb r3, [r7, #7] 8006b12: f003 030f and.w r3, r3, #15 8006b16: 3b04 subs r3, #4 8006b18: 0112 lsls r2, r2, #4 8006b1a: b2d2 uxtb r2, r2 8006b1c: 440b add r3, r1 8006b1e: 761a strb r2, [r3, #24] } 8006b20: bf00 nop 8006b22: 370c adds r7, #12 8006b24: 46bd mov sp, r7 8006b26: f85d 7b04 ldr.w r7, [sp], #4 8006b2a: 4770 bx lr 8006b2c: e000e100 .word 0xe000e100 8006b30: e000ed00 .word 0xe000ed00 08006b34 : { 8006b34: b480 push {r7} 8006b36: b089 sub sp, #36 @ 0x24 8006b38: af00 add r7, sp, #0 8006b3a: 60f8 str r0, [r7, #12] 8006b3c: 60b9 str r1, [r7, #8] 8006b3e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8006b40: 68fb ldr r3, [r7, #12] 8006b42: f003 0307 and.w r3, r3, #7 8006b46: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8006b48: 69fb ldr r3, [r7, #28] 8006b4a: f1c3 0307 rsb r3, r3, #7 8006b4e: 2b04 cmp r3, #4 8006b50: bf28 it cs 8006b52: 2304 movcs r3, #4 8006b54: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8006b56: 69fb ldr r3, [r7, #28] 8006b58: 3304 adds r3, #4 8006b5a: 2b06 cmp r3, #6 8006b5c: d902 bls.n 8006b64 8006b5e: 69fb ldr r3, [r7, #28] 8006b60: 3b03 subs r3, #3 8006b62: e000 b.n 8006b66 8006b64: 2300 movs r3, #0 8006b66: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8006b68: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8006b6c: 69bb ldr r3, [r7, #24] 8006b6e: fa02 f303 lsl.w r3, r2, r3 8006b72: 43da mvns r2, r3 8006b74: 68bb ldr r3, [r7, #8] 8006b76: 401a ands r2, r3 8006b78: 697b ldr r3, [r7, #20] 8006b7a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8006b7c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8006b80: 697b ldr r3, [r7, #20] 8006b82: fa01 f303 lsl.w r3, r1, r3 8006b86: 43d9 mvns r1, r3 8006b88: 687b ldr r3, [r7, #4] 8006b8a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8006b8c: 4313 orrs r3, r2 } 8006b8e: 4618 mov r0, r3 8006b90: 3724 adds r7, #36 @ 0x24 8006b92: 46bd mov sp, r7 8006b94: f85d 7b04 ldr.w r7, [sp], #4 8006b98: 4770 bx lr 08006b9a : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8006b9a: b580 push {r7, lr} 8006b9c: b082 sub sp, #8 8006b9e: af00 add r7, sp, #0 8006ba0: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8006ba2: 6878 ldr r0, [r7, #4] 8006ba4: f7ff feec bl 8006980 <__NVIC_SetPriorityGrouping> } 8006ba8: bf00 nop 8006baa: 3708 adds r7, #8 8006bac: 46bd mov sp, r7 8006bae: bd80 pop {r7, pc} 08006bb0 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8006bb0: b580 push {r7, lr} 8006bb2: b086 sub sp, #24 8006bb4: af00 add r7, sp, #0 8006bb6: 4603 mov r3, r0 8006bb8: 60b9 str r1, [r7, #8] 8006bba: 607a str r2, [r7, #4] 8006bbc: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8006bbe: f7ff ff03 bl 80069c8 <__NVIC_GetPriorityGrouping> 8006bc2: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8006bc4: 687a ldr r2, [r7, #4] 8006bc6: 68b9 ldr r1, [r7, #8] 8006bc8: 6978 ldr r0, [r7, #20] 8006bca: f7ff ffb3 bl 8006b34 8006bce: 4602 mov r2, r0 8006bd0: f997 300f ldrsb.w r3, [r7, #15] 8006bd4: 4611 mov r1, r2 8006bd6: 4618 mov r0, r3 8006bd8: f7ff ff82 bl 8006ae0 <__NVIC_SetPriority> } 8006bdc: bf00 nop 8006bde: 3718 adds r7, #24 8006be0: 46bd mov sp, r7 8006be2: bd80 pop {r7, pc} 08006be4 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8006be4: b580 push {r7, lr} 8006be6: b082 sub sp, #8 8006be8: af00 add r7, sp, #0 8006bea: 4603 mov r3, r0 8006bec: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8006bee: f997 3007 ldrsb.w r3, [r7, #7] 8006bf2: 4618 mov r0, r3 8006bf4: f7ff fef6 bl 80069e4 <__NVIC_EnableIRQ> } 8006bf8: bf00 nop 8006bfa: 3708 adds r7, #8 8006bfc: 46bd mov sp, r7 8006bfe: bd80 pop {r7, pc} 08006c00 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { 8006c00: b580 push {r7, lr} 8006c02: b082 sub sp, #8 8006c04: af00 add r7, sp, #0 8006c06: 4603 mov r3, r0 8006c08: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); 8006c0a: f997 3007 ldrsb.w r3, [r7, #7] 8006c0e: 4618 mov r0, r3 8006c10: f7ff ff06 bl 8006a20 <__NVIC_DisableIRQ> } 8006c14: bf00 nop 8006c16: 3708 adds r7, #8 8006c18: 46bd mov sp, r7 8006c1a: bd80 pop {r7, pc} 08006c1c : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { 8006c1c: b580 push {r7, lr} 8006c1e: b082 sub sp, #8 8006c20: af00 add r7, sp, #0 8006c22: 4603 mov r3, r0 8006c24: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); 8006c26: f997 3007 ldrsb.w r3, [r7, #7] 8006c2a: 4618 mov r0, r3 8006c2c: f7ff ff1c bl 8006a68 <__NVIC_SetPendingIRQ> } 8006c30: bf00 nop 8006c32: 3708 adds r7, #8 8006c34: 46bd mov sp, r7 8006c36: bd80 pop {r7, pc} 08006c38 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { 8006c38: b580 push {r7, lr} 8006c3a: b082 sub sp, #8 8006c3c: af00 add r7, sp, #0 8006c3e: 4603 mov r3, r0 8006c40: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); 8006c42: f997 3007 ldrsb.w r3, [r7, #7] 8006c46: 4618 mov r0, r3 8006c48: f7ff ff2c bl 8006aa4 <__NVIC_ClearPendingIRQ> } 8006c4c: bf00 nop 8006c4e: 3708 adds r7, #8 8006c50: 46bd mov sp, r7 8006c52: bd80 pop {r7, pc} 08006c54 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8006c54: b580 push {r7, lr} 8006c56: b084 sub sp, #16 8006c58: af00 add r7, sp, #0 8006c5a: 6078 str r0, [r7, #4] uint32_t tmp; /* Check the DMA handle allocation */ if (hdma == NULL) 8006c5c: 687b ldr r3, [r7, #4] 8006c5e: 2b00 cmp r3, #0 8006c60: d101 bne.n 8006c66 { return HAL_ERROR; 8006c62: 2301 movs r3, #1 8006c64: e08e b.n 8006d84 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); #if defined(DMA2) /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 8006c66: 687b ldr r3, [r7, #4] 8006c68: 681b ldr r3, [r3, #0] 8006c6a: 461a mov r2, r3 8006c6c: 4b47 ldr r3, [pc, #284] @ (8006d8c ) 8006c6e: 429a cmp r2, r3 8006c70: d80f bhi.n 8006c92 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8006c72: 687b ldr r3, [r7, #4] 8006c74: 681b ldr r3, [r3, #0] 8006c76: 461a mov r2, r3 8006c78: 4b45 ldr r3, [pc, #276] @ (8006d90 ) 8006c7a: 4413 add r3, r2 8006c7c: 4a45 ldr r2, [pc, #276] @ (8006d94 ) 8006c7e: fba2 2303 umull r2, r3, r2, r3 8006c82: 091b lsrs r3, r3, #4 8006c84: 009a lsls r2, r3, #2 8006c86: 687b ldr r3, [r7, #4] 8006c88: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA1; 8006c8a: 687b ldr r3, [r7, #4] 8006c8c: 4a42 ldr r2, [pc, #264] @ (8006d98 ) 8006c8e: 641a str r2, [r3, #64] @ 0x40 8006c90: e00e b.n 8006cb0 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; 8006c92: 687b ldr r3, [r7, #4] 8006c94: 681b ldr r3, [r3, #0] 8006c96: 461a mov r2, r3 8006c98: 4b40 ldr r3, [pc, #256] @ (8006d9c ) 8006c9a: 4413 add r3, r2 8006c9c: 4a3d ldr r2, [pc, #244] @ (8006d94 ) 8006c9e: fba2 2303 umull r2, r3, r2, r3 8006ca2: 091b lsrs r3, r3, #4 8006ca4: 009a lsls r2, r3, #2 8006ca6: 687b ldr r3, [r7, #4] 8006ca8: 645a str r2, [r3, #68] @ 0x44 hdma->DmaBaseAddress = DMA2; 8006caa: 687b ldr r3, [r7, #4] 8006cac: 4a3c ldr r2, [pc, #240] @ (8006da0 ) 8006cae: 641a str r2, [r3, #64] @ 0x40 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8006cb0: 687b ldr r3, [r7, #4] 8006cb2: 2202 movs r2, #2 8006cb4: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Get the CR register value */ tmp = hdma->Instance->CCR; 8006cb8: 687b ldr r3, [r7, #4] 8006cba: 681b ldr r3, [r3, #0] 8006cbc: 681b ldr r3, [r3, #0] 8006cbe: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | 8006cc0: 68fb ldr r3, [r7, #12] 8006cc2: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 8006cc6: f023 0370 bic.w r3, r3, #112 @ 0x70 8006cca: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8006ccc: 687b ldr r3, [r7, #4] 8006cce: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8006cd0: 687b ldr r3, [r7, #4] 8006cd2: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Direction | 8006cd4: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8006cd6: 687b ldr r3, [r7, #4] 8006cd8: 691b ldr r3, [r3, #16] 8006cda: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8006cdc: 687b ldr r3, [r7, #4] 8006cde: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8006ce0: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8006ce2: 687b ldr r3, [r7, #4] 8006ce4: 699b ldr r3, [r3, #24] 8006ce6: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8006ce8: 687b ldr r3, [r7, #4] 8006cea: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8006cec: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8006cee: 687b ldr r3, [r7, #4] 8006cf0: 6a1b ldr r3, [r3, #32] 8006cf2: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 8006cf4: 68fa ldr r2, [r7, #12] 8006cf6: 4313 orrs r3, r2 8006cf8: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 8006cfa: 687b ldr r3, [r7, #4] 8006cfc: 681b ldr r3, [r3, #0] 8006cfe: 68fa ldr r2, [r7, #12] 8006d00: 601a str r2, [r3, #0] /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8006d02: 6878 ldr r0, [r7, #4] 8006d04: f000 fa82 bl 800720c if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8006d08: 687b ldr r3, [r7, #4] 8006d0a: 689b ldr r3, [r3, #8] 8006d0c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8006d10: d102 bne.n 8006d18 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8006d12: 687b ldr r3, [r7, #4] 8006d14: 2200 movs r2, #0 8006d16: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8006d18: 687b ldr r3, [r7, #4] 8006d1a: 685a ldr r2, [r3, #4] 8006d1c: 687b ldr r3, [r7, #4] 8006d1e: 6c9b ldr r3, [r3, #72] @ 0x48 8006d20: f002 023f and.w r2, r2, #63 @ 0x3f 8006d24: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006d26: 687b ldr r3, [r7, #4] 8006d28: 6cdb ldr r3, [r3, #76] @ 0x4c 8006d2a: 687a ldr r2, [r7, #4] 8006d2c: 6d12 ldr r2, [r2, #80] @ 0x50 8006d2e: 605a str r2, [r3, #4] if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 8006d30: 687b ldr r3, [r7, #4] 8006d32: 685b ldr r3, [r3, #4] 8006d34: 2b00 cmp r3, #0 8006d36: d010 beq.n 8006d5a 8006d38: 687b ldr r3, [r7, #4] 8006d3a: 685b ldr r3, [r3, #4] 8006d3c: 2b04 cmp r3, #4 8006d3e: d80c bhi.n 8006d5a { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8006d40: 6878 ldr r0, [r7, #4] 8006d42: f000 faa1 bl 8007288 /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; 8006d46: 687b ldr r3, [r7, #4] 8006d48: 6d5b ldr r3, [r3, #84] @ 0x54 8006d4a: 2200 movs r2, #0 8006d4c: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8006d4e: 687b ldr r3, [r7, #4] 8006d50: 6d9b ldr r3, [r3, #88] @ 0x58 8006d52: 687a ldr r2, [r7, #4] 8006d54: 6dd2 ldr r2, [r2, #92] @ 0x5c 8006d56: 605a str r2, [r3, #4] 8006d58: e008 b.n 8006d6c } else { hdma->DMAmuxRequestGen = 0U; 8006d5a: 687b ldr r3, [r7, #4] 8006d5c: 2200 movs r2, #0 8006d5e: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = 0U; 8006d60: 687b ldr r3, [r7, #4] 8006d62: 2200 movs r2, #0 8006d64: 659a str r2, [r3, #88] @ 0x58 hdma->DMAmuxRequestGenStatusMask = 0U; 8006d66: 687b ldr r3, [r7, #4] 8006d68: 2200 movs r2, #0 8006d6a: 65da str r2, [r3, #92] @ 0x5c } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8006d6c: 687b ldr r3, [r7, #4] 8006d6e: 2200 movs r2, #0 8006d70: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8006d72: 687b ldr r3, [r7, #4] 8006d74: 2201 movs r2, #1 8006d76: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 8006d7a: 687b ldr r3, [r7, #4] 8006d7c: 2200 movs r2, #0 8006d7e: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_OK; 8006d82: 2300 movs r3, #0 } 8006d84: 4618 mov r0, r3 8006d86: 3710 adds r7, #16 8006d88: 46bd mov sp, r7 8006d8a: bd80 pop {r7, pc} 8006d8c: 40020407 .word 0x40020407 8006d90: bffdfff8 .word 0xbffdfff8 8006d94: cccccccd .word 0xcccccccd 8006d98: 40020000 .word 0x40020000 8006d9c: bffdfbf8 .word 0xbffdfbf8 8006da0: 40020400 .word 0x40020400 08006da4 : * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8006da4: b580 push {r7, lr} 8006da6: b086 sub sp, #24 8006da8: af00 add r7, sp, #0 8006daa: 60f8 str r0, [r7, #12] 8006dac: 60b9 str r1, [r7, #8] 8006dae: 607a str r2, [r7, #4] 8006db0: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8006db2: 2300 movs r3, #0 8006db4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8006db6: 68fb ldr r3, [r7, #12] 8006db8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 8006dbc: 2b01 cmp r3, #1 8006dbe: d101 bne.n 8006dc4 8006dc0: 2302 movs r3, #2 8006dc2: e066 b.n 8006e92 8006dc4: 68fb ldr r3, [r7, #12] 8006dc6: 2201 movs r2, #1 8006dc8: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (HAL_DMA_STATE_READY == hdma->State) 8006dcc: 68fb ldr r3, [r7, #12] 8006dce: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8006dd2: b2db uxtb r3, r3 8006dd4: 2b01 cmp r3, #1 8006dd6: d155 bne.n 8006e84 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8006dd8: 68fb ldr r3, [r7, #12] 8006dda: 2202 movs r2, #2 8006ddc: f883 2025 strb.w r2, [r3, #37] @ 0x25 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8006de0: 68fb ldr r3, [r7, #12] 8006de2: 2200 movs r2, #0 8006de4: 63da str r2, [r3, #60] @ 0x3c /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8006de6: 68fb ldr r3, [r7, #12] 8006de8: 681b ldr r3, [r3, #0] 8006dea: 681a ldr r2, [r3, #0] 8006dec: 68fb ldr r3, [r7, #12] 8006dee: 681b ldr r3, [r3, #0] 8006df0: f022 0201 bic.w r2, r2, #1 8006df4: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8006df6: 683b ldr r3, [r7, #0] 8006df8: 687a ldr r2, [r7, #4] 8006dfa: 68b9 ldr r1, [r7, #8] 8006dfc: 68f8 ldr r0, [r7, #12] 8006dfe: f000 f9c7 bl 8007190 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) 8006e02: 68fb ldr r3, [r7, #12] 8006e04: 6b1b ldr r3, [r3, #48] @ 0x30 8006e06: 2b00 cmp r3, #0 8006e08: d008 beq.n 8006e1c { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8006e0a: 68fb ldr r3, [r7, #12] 8006e0c: 681b ldr r3, [r3, #0] 8006e0e: 681a ldr r2, [r3, #0] 8006e10: 68fb ldr r3, [r7, #12] 8006e12: 681b ldr r3, [r3, #0] 8006e14: f042 020e orr.w r2, r2, #14 8006e18: 601a str r2, [r3, #0] 8006e1a: e00f b.n 8006e3c } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8006e1c: 68fb ldr r3, [r7, #12] 8006e1e: 681b ldr r3, [r3, #0] 8006e20: 681a ldr r2, [r3, #0] 8006e22: 68fb ldr r3, [r7, #12] 8006e24: 681b ldr r3, [r3, #0] 8006e26: f022 0204 bic.w r2, r2, #4 8006e2a: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8006e2c: 68fb ldr r3, [r7, #12] 8006e2e: 681b ldr r3, [r3, #0] 8006e30: 681a ldr r2, [r3, #0] 8006e32: 68fb ldr r3, [r7, #12] 8006e34: 681b ldr r3, [r3, #0] 8006e36: f042 020a orr.w r2, r2, #10 8006e3a: 601a str r2, [r3, #0] } /* Check if DMAMUX Synchronization is enabled*/ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8006e3c: 68fb ldr r3, [r7, #12] 8006e3e: 6c9b ldr r3, [r3, #72] @ 0x48 8006e40: 681b ldr r3, [r3, #0] 8006e42: f403 3380 and.w r3, r3, #65536 @ 0x10000 8006e46: 2b00 cmp r3, #0 8006e48: d007 beq.n 8006e5a { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8006e4a: 68fb ldr r3, [r7, #12] 8006e4c: 6c9b ldr r3, [r3, #72] @ 0x48 8006e4e: 681a ldr r2, [r3, #0] 8006e50: 68fb ldr r3, [r7, #12] 8006e52: 6c9b ldr r3, [r3, #72] @ 0x48 8006e54: f442 7280 orr.w r2, r2, #256 @ 0x100 8006e58: 601a str r2, [r3, #0] } if (hdma->DMAmuxRequestGen != 0U) 8006e5a: 68fb ldr r3, [r7, #12] 8006e5c: 6d5b ldr r3, [r3, #84] @ 0x54 8006e5e: 2b00 cmp r3, #0 8006e60: d007 beq.n 8006e72 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8006e62: 68fb ldr r3, [r7, #12] 8006e64: 6d5b ldr r3, [r3, #84] @ 0x54 8006e66: 681a ldr r2, [r3, #0] 8006e68: 68fb ldr r3, [r7, #12] 8006e6a: 6d5b ldr r3, [r3, #84] @ 0x54 8006e6c: f442 7280 orr.w r2, r2, #256 @ 0x100 8006e70: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8006e72: 68fb ldr r3, [r7, #12] 8006e74: 681b ldr r3, [r3, #0] 8006e76: 681a ldr r2, [r3, #0] 8006e78: 68fb ldr r3, [r7, #12] 8006e7a: 681b ldr r3, [r3, #0] 8006e7c: f042 0201 orr.w r2, r2, #1 8006e80: 601a str r2, [r3, #0] 8006e82: e005 b.n 8006e90 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006e84: 68fb ldr r3, [r7, #12] 8006e86: 2200 movs r2, #0 8006e88: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Remain BUSY */ status = HAL_BUSY; 8006e8c: 2302 movs r3, #2 8006e8e: 75fb strb r3, [r7, #23] } return status; 8006e90: 7dfb ldrb r3, [r7, #23] } 8006e92: 4618 mov r0, r3 8006e94: 3718 adds r7, #24 8006e96: 46bd mov sp, r7 8006e98: bd80 pop {r7, pc} 08006e9a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8006e9a: b480 push {r7} 8006e9c: b083 sub sp, #12 8006e9e: af00 add r7, sp, #0 8006ea0: 6078 str r0, [r7, #4] /* Check the DMA peripheral handle */ if (NULL == hdma) 8006ea2: 687b ldr r3, [r7, #4] 8006ea4: 2b00 cmp r3, #0 8006ea6: d101 bne.n 8006eac { return HAL_ERROR; 8006ea8: 2301 movs r3, #1 8006eaa: e04f b.n 8006f4c } /* Check the DMA peripheral state */ if (hdma->State != HAL_DMA_STATE_BUSY) 8006eac: 687b ldr r3, [r7, #4] 8006eae: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8006eb2: b2db uxtb r3, r3 8006eb4: 2b02 cmp r3, #2 8006eb6: d008 beq.n 8006eca { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8006eb8: 687b ldr r3, [r7, #4] 8006eba: 2204 movs r2, #4 8006ebc: 63da str r2, [r3, #60] @ 0x3c /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006ebe: 687b ldr r3, [r7, #4] 8006ec0: 2200 movs r2, #0 8006ec2: f883 2024 strb.w r2, [r3, #36] @ 0x24 return HAL_ERROR; 8006ec6: 2301 movs r3, #1 8006ec8: e040 b.n 8006f4c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8006eca: 687b ldr r3, [r7, #4] 8006ecc: 681b ldr r3, [r3, #0] 8006ece: 681a ldr r2, [r3, #0] 8006ed0: 687b ldr r3, [r7, #4] 8006ed2: 681b ldr r3, [r3, #0] 8006ed4: f022 020e bic.w r2, r2, #14 8006ed8: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8006eda: 687b ldr r3, [r7, #4] 8006edc: 6c9b ldr r3, [r3, #72] @ 0x48 8006ede: 681a ldr r2, [r3, #0] 8006ee0: 687b ldr r3, [r7, #4] 8006ee2: 6c9b ldr r3, [r3, #72] @ 0x48 8006ee4: f422 7280 bic.w r2, r2, #256 @ 0x100 8006ee8: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8006eea: 687b ldr r3, [r7, #4] 8006eec: 681b ldr r3, [r3, #0] 8006eee: 681a ldr r2, [r3, #0] 8006ef0: 687b ldr r3, [r7, #4] 8006ef2: 681b ldr r3, [r3, #0] 8006ef4: f022 0201 bic.w r2, r2, #1 8006ef8: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 8006efa: 687b ldr r3, [r7, #4] 8006efc: 6c5b ldr r3, [r3, #68] @ 0x44 8006efe: f003 021c and.w r2, r3, #28 8006f02: 687b ldr r3, [r7, #4] 8006f04: 6c1b ldr r3, [r3, #64] @ 0x40 8006f06: 2101 movs r1, #1 8006f08: fa01 f202 lsl.w r2, r1, r2 8006f0c: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006f0e: 687b ldr r3, [r7, #4] 8006f10: 6cdb ldr r3, [r3, #76] @ 0x4c 8006f12: 687a ldr r2, [r7, #4] 8006f14: 6d12 ldr r2, [r2, #80] @ 0x50 8006f16: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 8006f18: 687b ldr r3, [r7, #4] 8006f1a: 6d5b ldr r3, [r3, #84] @ 0x54 8006f1c: 2b00 cmp r3, #0 8006f1e: d00c beq.n 8006f3a { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8006f20: 687b ldr r3, [r7, #4] 8006f22: 6d5b ldr r3, [r3, #84] @ 0x54 8006f24: 681a ldr r2, [r3, #0] 8006f26: 687b ldr r3, [r7, #4] 8006f28: 6d5b ldr r3, [r3, #84] @ 0x54 8006f2a: f422 7280 bic.w r2, r2, #256 @ 0x100 8006f2e: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8006f30: 687b ldr r3, [r7, #4] 8006f32: 6d9b ldr r3, [r3, #88] @ 0x58 8006f34: 687a ldr r2, [r7, #4] 8006f36: 6dd2 ldr r2, [r2, #92] @ 0x5c 8006f38: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8006f3a: 687b ldr r3, [r7, #4] 8006f3c: 2201 movs r2, #1 8006f3e: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006f42: 687b ldr r3, [r7, #4] 8006f44: 2200 movs r2, #0 8006f46: f883 2024 strb.w r2, [r3, #36] @ 0x24 } return HAL_OK; 8006f4a: 2300 movs r3, #0 } 8006f4c: 4618 mov r0, r3 8006f4e: 370c adds r7, #12 8006f50: 46bd mov sp, r7 8006f52: f85d 7b04 ldr.w r7, [sp], #4 8006f56: 4770 bx lr 08006f58 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8006f58: b580 push {r7, lr} 8006f5a: b084 sub sp, #16 8006f5c: af00 add r7, sp, #0 8006f5e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8006f60: 2300 movs r3, #0 8006f62: 73fb strb r3, [r7, #15] if (HAL_DMA_STATE_BUSY != hdma->State) 8006f64: 687b ldr r3, [r7, #4] 8006f66: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8006f6a: b2db uxtb r3, r3 8006f6c: 2b02 cmp r3, #2 8006f6e: d005 beq.n 8006f7c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8006f70: 687b ldr r3, [r7, #4] 8006f72: 2204 movs r2, #4 8006f74: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 8006f76: 2301 movs r3, #1 8006f78: 73fb strb r3, [r7, #15] 8006f7a: e047 b.n 800700c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8006f7c: 687b ldr r3, [r7, #4] 8006f7e: 681b ldr r3, [r3, #0] 8006f80: 681a ldr r2, [r3, #0] 8006f82: 687b ldr r3, [r7, #4] 8006f84: 681b ldr r3, [r3, #0] 8006f86: f022 020e bic.w r2, r2, #14 8006f8a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8006f8c: 687b ldr r3, [r7, #4] 8006f8e: 681b ldr r3, [r3, #0] 8006f90: 681a ldr r2, [r3, #0] 8006f92: 687b ldr r3, [r7, #4] 8006f94: 681b ldr r3, [r3, #0] 8006f96: f022 0201 bic.w r2, r2, #1 8006f9a: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8006f9c: 687b ldr r3, [r7, #4] 8006f9e: 6c9b ldr r3, [r3, #72] @ 0x48 8006fa0: 681a ldr r2, [r3, #0] 8006fa2: 687b ldr r3, [r7, #4] 8006fa4: 6c9b ldr r3, [r3, #72] @ 0x48 8006fa6: f422 7280 bic.w r2, r2, #256 @ 0x100 8006faa: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 8006fac: 687b ldr r3, [r7, #4] 8006fae: 6c5b ldr r3, [r3, #68] @ 0x44 8006fb0: f003 021c and.w r2, r3, #28 8006fb4: 687b ldr r3, [r7, #4] 8006fb6: 6c1b ldr r3, [r3, #64] @ 0x40 8006fb8: 2101 movs r1, #1 8006fba: fa01 f202 lsl.w r2, r1, r2 8006fbe: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006fc0: 687b ldr r3, [r7, #4] 8006fc2: 6cdb ldr r3, [r3, #76] @ 0x4c 8006fc4: 687a ldr r2, [r7, #4] 8006fc6: 6d12 ldr r2, [r2, #80] @ 0x50 8006fc8: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 8006fca: 687b ldr r3, [r7, #4] 8006fcc: 6d5b ldr r3, [r3, #84] @ 0x54 8006fce: 2b00 cmp r3, #0 8006fd0: d00c beq.n 8006fec { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8006fd2: 687b ldr r3, [r7, #4] 8006fd4: 6d5b ldr r3, [r3, #84] @ 0x54 8006fd6: 681a ldr r2, [r3, #0] 8006fd8: 687b ldr r3, [r7, #4] 8006fda: 6d5b ldr r3, [r3, #84] @ 0x54 8006fdc: f422 7280 bic.w r2, r2, #256 @ 0x100 8006fe0: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8006fe2: 687b ldr r3, [r7, #4] 8006fe4: 6d9b ldr r3, [r3, #88] @ 0x58 8006fe6: 687a ldr r2, [r7, #4] 8006fe8: 6dd2 ldr r2, [r2, #92] @ 0x5c 8006fea: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8006fec: 687b ldr r3, [r7, #4] 8006fee: 2201 movs r2, #1 8006ff0: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8006ff4: 687b ldr r3, [r7, #4] 8006ff6: 2200 movs r2, #0 8006ff8: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 8006ffc: 687b ldr r3, [r7, #4] 8006ffe: 6b9b ldr r3, [r3, #56] @ 0x38 8007000: 2b00 cmp r3, #0 8007002: d003 beq.n 800700c { hdma->XferAbortCallback(hdma); 8007004: 687b ldr r3, [r7, #4] 8007006: 6b9b ldr r3, [r3, #56] @ 0x38 8007008: 6878 ldr r0, [r7, #4] 800700a: 4798 blx r3 } } return status; 800700c: 7bfb ldrb r3, [r7, #15] } 800700e: 4618 mov r0, r3 8007010: 3710 adds r7, #16 8007012: 46bd mov sp, r7 8007014: bd80 pop {r7, pc} 08007016 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8007016: b580 push {r7, lr} 8007018: b084 sub sp, #16 800701a: af00 add r7, sp, #0 800701c: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 800701e: 687b ldr r3, [r7, #4] 8007020: 6c1b ldr r3, [r3, #64] @ 0x40 8007022: 681b ldr r3, [r3, #0] 8007024: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8007026: 687b ldr r3, [r7, #4] 8007028: 681b ldr r3, [r3, #0] 800702a: 681b ldr r3, [r3, #0] 800702c: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) 800702e: 687b ldr r3, [r7, #4] 8007030: 6c5b ldr r3, [r3, #68] @ 0x44 8007032: f003 031c and.w r3, r3, #28 8007036: 2204 movs r2, #4 8007038: 409a lsls r2, r3 800703a: 68fb ldr r3, [r7, #12] 800703c: 4013 ands r3, r2 800703e: 2b00 cmp r3, #0 8007040: d026 beq.n 8007090 8007042: 68bb ldr r3, [r7, #8] 8007044: f003 0304 and.w r3, r3, #4 8007048: 2b00 cmp r3, #0 800704a: d021 beq.n 8007090 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 800704c: 687b ldr r3, [r7, #4] 800704e: 681b ldr r3, [r3, #0] 8007050: 681b ldr r3, [r3, #0] 8007052: f003 0320 and.w r3, r3, #32 8007056: 2b00 cmp r3, #0 8007058: d107 bne.n 800706a { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800705a: 687b ldr r3, [r7, #4] 800705c: 681b ldr r3, [r3, #0] 800705e: 681a ldr r2, [r3, #0] 8007060: 687b ldr r3, [r7, #4] 8007062: 681b ldr r3, [r3, #0] 8007064: f022 0204 bic.w r2, r2, #4 8007068: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU)); 800706a: 687b ldr r3, [r7, #4] 800706c: 6c5b ldr r3, [r3, #68] @ 0x44 800706e: f003 021c and.w r2, r3, #28 8007072: 687b ldr r3, [r7, #4] 8007074: 6c1b ldr r3, [r3, #64] @ 0x40 8007076: 2104 movs r1, #4 8007078: fa01 f202 lsl.w r2, r1, r2 800707c: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) 800707e: 687b ldr r3, [r7, #4] 8007080: 6b1b ldr r3, [r3, #48] @ 0x30 8007082: 2b00 cmp r3, #0 8007084: d071 beq.n 800716a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8007086: 687b ldr r3, [r7, #4] 8007088: 6b1b ldr r3, [r3, #48] @ 0x30 800708a: 6878 ldr r0, [r7, #4] 800708c: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) 800708e: e06c b.n 800716a } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) 8007090: 687b ldr r3, [r7, #4] 8007092: 6c5b ldr r3, [r3, #68] @ 0x44 8007094: f003 031c and.w r3, r3, #28 8007098: 2202 movs r2, #2 800709a: 409a lsls r2, r3 800709c: 68fb ldr r3, [r7, #12] 800709e: 4013 ands r3, r2 80070a0: 2b00 cmp r3, #0 80070a2: d02e beq.n 8007102 80070a4: 68bb ldr r3, [r7, #8] 80070a6: f003 0302 and.w r3, r3, #2 80070aa: 2b00 cmp r3, #0 80070ac: d029 beq.n 8007102 { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80070ae: 687b ldr r3, [r7, #4] 80070b0: 681b ldr r3, [r3, #0] 80070b2: 681b ldr r3, [r3, #0] 80070b4: f003 0320 and.w r3, r3, #32 80070b8: 2b00 cmp r3, #0 80070ba: d10b bne.n 80070d4 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 80070bc: 687b ldr r3, [r7, #4] 80070be: 681b ldr r3, [r3, #0] 80070c0: 681a ldr r2, [r3, #0] 80070c2: 687b ldr r3, [r7, #4] 80070c4: 681b ldr r3, [r3, #0] 80070c6: f022 020a bic.w r2, r2, #10 80070ca: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80070cc: 687b ldr r3, [r7, #4] 80070ce: 2201 movs r2, #1 80070d0: f883 2025 strb.w r2, [r3, #37] @ 0x25 } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU)); 80070d4: 687b ldr r3, [r7, #4] 80070d6: 6c5b ldr r3, [r3, #68] @ 0x44 80070d8: f003 021c and.w r2, r3, #28 80070dc: 687b ldr r3, [r7, #4] 80070de: 6c1b ldr r3, [r3, #64] @ 0x40 80070e0: 2102 movs r1, #2 80070e2: fa01 f202 lsl.w r2, r1, r2 80070e6: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 80070e8: 687b ldr r3, [r7, #4] 80070ea: 2200 movs r2, #0 80070ec: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->XferCpltCallback != NULL) 80070f0: 687b ldr r3, [r7, #4] 80070f2: 6adb ldr r3, [r3, #44] @ 0x2c 80070f4: 2b00 cmp r3, #0 80070f6: d038 beq.n 800716a { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80070f8: 687b ldr r3, [r7, #4] 80070fa: 6adb ldr r3, [r3, #44] @ 0x2c 80070fc: 6878 ldr r0, [r7, #4] 80070fe: 4798 blx r3 if (hdma->XferCpltCallback != NULL) 8007100: e033 b.n 800716a } } /* Transfer Error Interrupt management **************************************/ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) 8007102: 687b ldr r3, [r7, #4] 8007104: 6c5b ldr r3, [r3, #68] @ 0x44 8007106: f003 031c and.w r3, r3, #28 800710a: 2208 movs r2, #8 800710c: 409a lsls r2, r3 800710e: 68fb ldr r3, [r7, #12] 8007110: 4013 ands r3, r2 8007112: 2b00 cmp r3, #0 8007114: d02a beq.n 800716c 8007116: 68bb ldr r3, [r7, #8] 8007118: f003 0308 and.w r3, r3, #8 800711c: 2b00 cmp r3, #0 800711e: d025 beq.n 800716c { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8007120: 687b ldr r3, [r7, #4] 8007122: 681b ldr r3, [r3, #0] 8007124: 681a ldr r2, [r3, #0] 8007126: 687b ldr r3, [r7, #4] 8007128: 681b ldr r3, [r3, #0] 800712a: f022 020e bic.w r2, r2, #14 800712e: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 8007130: 687b ldr r3, [r7, #4] 8007132: 6c5b ldr r3, [r3, #68] @ 0x44 8007134: f003 021c and.w r2, r3, #28 8007138: 687b ldr r3, [r7, #4] 800713a: 6c1b ldr r3, [r3, #64] @ 0x40 800713c: 2101 movs r1, #1 800713e: fa01 f202 lsl.w r2, r1, r2 8007142: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8007144: 687b ldr r3, [r7, #4] 8007146: 2201 movs r2, #1 8007148: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800714a: 687b ldr r3, [r7, #4] 800714c: 2201 movs r2, #1 800714e: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8007152: 687b ldr r3, [r7, #4] 8007154: 2200 movs r2, #0 8007156: f883 2024 strb.w r2, [r3, #36] @ 0x24 if (hdma->XferErrorCallback != NULL) 800715a: 687b ldr r3, [r7, #4] 800715c: 6b5b ldr r3, [r3, #52] @ 0x34 800715e: 2b00 cmp r3, #0 8007160: d004 beq.n 800716c { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8007162: 687b ldr r3, [r7, #4] 8007164: 6b5b ldr r3, [r3, #52] @ 0x34 8007166: 6878 ldr r0, [r7, #4] 8007168: 4798 blx r3 } else { /* Nothing To Do */ } return; 800716a: bf00 nop 800716c: bf00 nop } 800716e: 3710 adds r7, #16 8007170: 46bd mov sp, r7 8007172: bd80 pop {r7, pc} 08007174 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { 8007174: b480 push {r7} 8007176: b083 sub sp, #12 8007178: af00 add r7, sp, #0 800717a: 6078 str r0, [r7, #4] /* Return DMA handle state */ return hdma->State; 800717c: 687b ldr r3, [r7, #4] 800717e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007182: b2db uxtb r3, r3 } 8007184: 4618 mov r0, r3 8007186: 370c adds r7, #12 8007188: 46bd mov sp, r7 800718a: f85d 7b04 ldr.w r7, [sp], #4 800718e: 4770 bx lr 08007190 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8007190: b480 push {r7} 8007192: b085 sub sp, #20 8007194: af00 add r7, sp, #0 8007196: 60f8 str r0, [r7, #12] 8007198: 60b9 str r1, [r7, #8] 800719a: 607a str r2, [r7, #4] 800719c: 603b str r3, [r7, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800719e: 68fb ldr r3, [r7, #12] 80071a0: 6cdb ldr r3, [r3, #76] @ 0x4c 80071a2: 68fa ldr r2, [r7, #12] 80071a4: 6d12 ldr r2, [r2, #80] @ 0x50 80071a6: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 80071a8: 68fb ldr r3, [r7, #12] 80071aa: 6d5b ldr r3, [r3, #84] @ 0x54 80071ac: 2b00 cmp r3, #0 80071ae: d004 beq.n 80071ba { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80071b0: 68fb ldr r3, [r7, #12] 80071b2: 6d9b ldr r3, [r3, #88] @ 0x58 80071b4: 68fa ldr r2, [r7, #12] 80071b6: 6dd2 ldr r2, [r2, #92] @ 0x5c 80071b8: 605a str r2, [r3, #4] } /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 80071ba: 68fb ldr r3, [r7, #12] 80071bc: 6c5b ldr r3, [r3, #68] @ 0x44 80071be: f003 021c and.w r2, r3, #28 80071c2: 68fb ldr r3, [r7, #12] 80071c4: 6c1b ldr r3, [r3, #64] @ 0x40 80071c6: 2101 movs r1, #1 80071c8: fa01 f202 lsl.w r2, r1, r2 80071cc: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 80071ce: 68fb ldr r3, [r7, #12] 80071d0: 681b ldr r3, [r3, #0] 80071d2: 683a ldr r2, [r7, #0] 80071d4: 605a str r2, [r3, #4] /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80071d6: 68fb ldr r3, [r7, #12] 80071d8: 689b ldr r3, [r3, #8] 80071da: 2b10 cmp r3, #16 80071dc: d108 bne.n 80071f0 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 80071de: 68fb ldr r3, [r7, #12] 80071e0: 681b ldr r3, [r3, #0] 80071e2: 687a ldr r2, [r7, #4] 80071e4: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 80071e6: 68fb ldr r3, [r7, #12] 80071e8: 681b ldr r3, [r3, #0] 80071ea: 68ba ldr r2, [r7, #8] 80071ec: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 80071ee: e007 b.n 8007200 hdma->Instance->CPAR = SrcAddress; 80071f0: 68fb ldr r3, [r7, #12] 80071f2: 681b ldr r3, [r3, #0] 80071f4: 68ba ldr r2, [r7, #8] 80071f6: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 80071f8: 68fb ldr r3, [r7, #12] 80071fa: 681b ldr r3, [r3, #0] 80071fc: 687a ldr r2, [r7, #4] 80071fe: 60da str r2, [r3, #12] } 8007200: bf00 nop 8007202: 3714 adds r7, #20 8007204: 46bd mov sp, r7 8007206: f85d 7b04 ldr.w r7, [sp], #4 800720a: 4770 bx lr 0800720c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800720c: b480 push {r7} 800720e: b085 sub sp, #20 8007210: af00 add r7, sp, #0 8007212: 6078 str r0, [r7, #4] uint32_t channel_number; /* check if instance is not outside the DMA channel range */ #if defined(DMA2) if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8007214: 687b ldr r3, [r7, #4] 8007216: 681b ldr r3, [r3, #0] 8007218: 461a mov r2, r3 800721a: 4b17 ldr r3, [pc, #92] @ (8007278 ) 800721c: 429a cmp r2, r3 800721e: d80a bhi.n 8007236 { /* DMA1 */ hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); 8007220: 687b ldr r3, [r7, #4] 8007222: 6c5b ldr r3, [r3, #68] @ 0x44 8007224: 089b lsrs r3, r3, #2 8007226: 009b lsls r3, r3, #2 8007228: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 800722c: f503 3302 add.w r3, r3, #133120 @ 0x20800 8007230: 687a ldr r2, [r7, #4] 8007232: 6493 str r3, [r2, #72] @ 0x48 8007234: e007 b.n 8007246 } else { /* DMA2 */ hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); 8007236: 687b ldr r3, [r7, #4] 8007238: 6c5b ldr r3, [r3, #68] @ 0x44 800723a: 089b lsrs r3, r3, #2 800723c: 009a lsls r2, r3, #2 800723e: 4b0f ldr r3, [pc, #60] @ (800727c ) 8007240: 4413 add r3, r2 8007242: 687a ldr r2, [r7, #4] 8007244: 6493 str r3, [r2, #72] @ 0x48 } #else /* DMA1 */ hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); #endif /* DMA2 */ channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 8007246: 687b ldr r3, [r7, #4] 8007248: 681b ldr r3, [r3, #0] 800724a: b2db uxtb r3, r3 800724c: 3b08 subs r3, #8 800724e: 4a0c ldr r2, [pc, #48] @ (8007280 ) 8007250: fba2 2303 umull r2, r3, r2, r3 8007254: 091b lsrs r3, r3, #4 8007256: 60fb str r3, [r7, #12] hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8007258: 687b ldr r3, [r7, #4] 800725a: 4a0a ldr r2, [pc, #40] @ (8007284 ) 800725c: 64da str r2, [r3, #76] @ 0x4c /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 800725e: 68fb ldr r3, [r7, #12] 8007260: f003 031f and.w r3, r3, #31 8007264: 2201 movs r2, #1 8007266: 409a lsls r2, r3 8007268: 687b ldr r3, [r7, #4] 800726a: 651a str r2, [r3, #80] @ 0x50 } 800726c: bf00 nop 800726e: 3714 adds r7, #20 8007270: 46bd mov sp, r7 8007272: f85d 7b04 ldr.w r7, [sp], #4 8007276: 4770 bx lr 8007278: 40020407 .word 0x40020407 800727c: 4002081c .word 0x4002081c 8007280: cccccccd .word 0xcccccccd 8007284: 40020880 .word 0x40020880 08007288 : * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 8007288: b480 push {r7} 800728a: b085 sub sp, #20 800728c: af00 add r7, sp, #0 800728e: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8007290: 687b ldr r3, [r7, #4] 8007292: 685b ldr r3, [r3, #4] 8007294: f003 033f and.w r3, r3, #63 @ 0x3f 8007298: 60fb str r3, [r7, #12] /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800729a: 68fa ldr r2, [r7, #12] 800729c: 4b0b ldr r3, [pc, #44] @ (80072cc ) 800729e: 4413 add r3, r2 80072a0: 009b lsls r3, r3, #2 80072a2: 461a mov r2, r3 80072a4: 687b ldr r3, [r7, #4] 80072a6: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 80072a8: 687b ldr r3, [r7, #4] 80072aa: 4a09 ldr r2, [pc, #36] @ (80072d0 ) 80072ac: 659a str r2, [r3, #88] @ 0x58 /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); 80072ae: 68fb ldr r3, [r7, #12] 80072b0: 3b01 subs r3, #1 80072b2: f003 0303 and.w r3, r3, #3 80072b6: 2201 movs r2, #1 80072b8: 409a lsls r2, r3 80072ba: 687b ldr r3, [r7, #4] 80072bc: 65da str r2, [r3, #92] @ 0x5c } 80072be: bf00 nop 80072c0: 3714 adds r7, #20 80072c2: 46bd mov sp, r7 80072c4: f85d 7b04 ldr.w r7, [sp], #4 80072c8: 4770 bx lr 80072ca: bf00 nop 80072cc: 1000823f .word 0x1000823f 80072d0: 40020940 .word 0x40020940 080072d4 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { 80072d4: b480 push {r7} 80072d6: b087 sub sp, #28 80072d8: af00 add r7, sp, #0 80072da: 6078 str r0, [r7, #4] 80072dc: 6039 str r1, [r7, #0] uint32_t position = 0x00UL; 80072de: 2300 movs r3, #0 80072e0: 617b str r3, [r7, #20] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80072e2: e14c b.n 800757e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 80072e4: 683b ldr r3, [r7, #0] 80072e6: 681a ldr r2, [r3, #0] 80072e8: 2101 movs r1, #1 80072ea: 697b ldr r3, [r7, #20] 80072ec: fa01 f303 lsl.w r3, r1, r3 80072f0: 4013 ands r3, r2 80072f2: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 80072f4: 68fb ldr r3, [r7, #12] 80072f6: 2b00 cmp r3, #0 80072f8: f000 813e beq.w 8007578 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 80072fc: 683b ldr r3, [r7, #0] 80072fe: 685b ldr r3, [r3, #4] 8007300: f003 0303 and.w r3, r3, #3 8007304: 2b01 cmp r3, #1 8007306: d005 beq.n 8007314 8007308: 683b ldr r3, [r7, #0] 800730a: 685b ldr r3, [r3, #4] 800730c: f003 0303 and.w r3, r3, #3 8007310: 2b02 cmp r3, #2 8007312: d130 bne.n 8007376 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8007314: 687b ldr r3, [r7, #4] 8007316: 689b ldr r3, [r3, #8] 8007318: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); 800731a: 697b ldr r3, [r7, #20] 800731c: 005b lsls r3, r3, #1 800731e: 2203 movs r2, #3 8007320: fa02 f303 lsl.w r3, r2, r3 8007324: 43db mvns r3, r3 8007326: 693a ldr r2, [r7, #16] 8007328: 4013 ands r3, r2 800732a: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 800732c: 683b ldr r3, [r7, #0] 800732e: 68da ldr r2, [r3, #12] 8007330: 697b ldr r3, [r7, #20] 8007332: 005b lsls r3, r3, #1 8007334: fa02 f303 lsl.w r3, r2, r3 8007338: 693a ldr r2, [r7, #16] 800733a: 4313 orrs r3, r2 800733c: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 800733e: 687b ldr r3, [r7, #4] 8007340: 693a ldr r2, [r7, #16] 8007342: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8007344: 687b ldr r3, [r7, #4] 8007346: 685b ldr r3, [r3, #4] 8007348: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800734a: 2201 movs r2, #1 800734c: 697b ldr r3, [r7, #20] 800734e: fa02 f303 lsl.w r3, r2, r3 8007352: 43db mvns r3, r3 8007354: 693a ldr r2, [r7, #16] 8007356: 4013 ands r3, r2 8007358: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800735a: 683b ldr r3, [r7, #0] 800735c: 685b ldr r3, [r3, #4] 800735e: 091b lsrs r3, r3, #4 8007360: f003 0201 and.w r2, r3, #1 8007364: 697b ldr r3, [r7, #20] 8007366: fa02 f303 lsl.w r3, r2, r3 800736a: 693a ldr r2, [r7, #16] 800736c: 4313 orrs r3, r2 800736e: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8007370: 687b ldr r3, [r7, #4] 8007372: 693a ldr r2, [r7, #16] 8007374: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8007376: 683b ldr r3, [r7, #0] 8007378: 685b ldr r3, [r3, #4] 800737a: f003 0303 and.w r3, r3, #3 800737e: 2b03 cmp r3, #3 8007380: d017 beq.n 80073b2 { temp = GPIOx->PUPDR; 8007382: 687b ldr r3, [r7, #4] 8007384: 68db ldr r3, [r3, #12] 8007386: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8007388: 697b ldr r3, [r7, #20] 800738a: 005b lsls r3, r3, #1 800738c: 2203 movs r2, #3 800738e: fa02 f303 lsl.w r3, r2, r3 8007392: 43db mvns r3, r3 8007394: 693a ldr r2, [r7, #16] 8007396: 4013 ands r3, r2 8007398: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800739a: 683b ldr r3, [r7, #0] 800739c: 689a ldr r2, [r3, #8] 800739e: 697b ldr r3, [r7, #20] 80073a0: 005b lsls r3, r3, #1 80073a2: fa02 f303 lsl.w r3, r2, r3 80073a6: 693a ldr r2, [r7, #16] 80073a8: 4313 orrs r3, r2 80073aa: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 80073ac: 687b ldr r3, [r7, #4] 80073ae: 693a ldr r2, [r7, #16] 80073b0: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80073b2: 683b ldr r3, [r7, #0] 80073b4: 685b ldr r3, [r3, #4] 80073b6: f003 0303 and.w r3, r3, #3 80073ba: 2b02 cmp r3, #2 80073bc: d123 bne.n 8007406 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 80073be: 697b ldr r3, [r7, #20] 80073c0: 08da lsrs r2, r3, #3 80073c2: 687b ldr r3, [r7, #4] 80073c4: 3208 adds r2, #8 80073c6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80073ca: 613b str r3, [r7, #16] temp &= ~(0xFUL << ((position & 0x07UL) * 4UL)); 80073cc: 697b ldr r3, [r7, #20] 80073ce: f003 0307 and.w r3, r3, #7 80073d2: 009b lsls r3, r3, #2 80073d4: 220f movs r2, #15 80073d6: fa02 f303 lsl.w r3, r2, r3 80073da: 43db mvns r3, r3 80073dc: 693a ldr r2, [r7, #16] 80073de: 4013 ands r3, r2 80073e0: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 80073e2: 683b ldr r3, [r7, #0] 80073e4: 691a ldr r2, [r3, #16] 80073e6: 697b ldr r3, [r7, #20] 80073e8: f003 0307 and.w r3, r3, #7 80073ec: 009b lsls r3, r3, #2 80073ee: fa02 f303 lsl.w r3, r2, r3 80073f2: 693a ldr r2, [r7, #16] 80073f4: 4313 orrs r3, r2 80073f6: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 80073f8: 697b ldr r3, [r7, #20] 80073fa: 08da lsrs r2, r3, #3 80073fc: 687b ldr r3, [r7, #4] 80073fe: 3208 adds r2, #8 8007400: 6939 ldr r1, [r7, #16] 8007402: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8007406: 687b ldr r3, [r7, #4] 8007408: 681b ldr r3, [r3, #0] 800740a: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); 800740c: 697b ldr r3, [r7, #20] 800740e: 005b lsls r3, r3, #1 8007410: 2203 movs r2, #3 8007412: fa02 f303 lsl.w r3, r2, r3 8007416: 43db mvns r3, r3 8007418: 693a ldr r2, [r7, #16] 800741a: 4013 ands r3, r2 800741c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 800741e: 683b ldr r3, [r7, #0] 8007420: 685b ldr r3, [r3, #4] 8007422: f003 0203 and.w r2, r3, #3 8007426: 697b ldr r3, [r7, #20] 8007428: 005b lsls r3, r3, #1 800742a: fa02 f303 lsl.w r3, r2, r3 800742e: 693a ldr r2, [r7, #16] 8007430: 4313 orrs r3, r2 8007432: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8007434: 687b ldr r3, [r7, #4] 8007436: 693a ldr r2, [r7, #16] 8007438: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 800743a: 683b ldr r3, [r7, #0] 800743c: 685b ldr r3, [r3, #4] 800743e: f403 3340 and.w r3, r3, #196608 @ 0x30000 8007442: 2b00 cmp r3, #0 8007444: f000 8098 beq.w 8007578 { temp = SYSCFG->EXTICR[position >> 2u]; 8007448: 4a54 ldr r2, [pc, #336] @ (800759c ) 800744a: 697b ldr r3, [r7, #20] 800744c: 089b lsrs r3, r3, #2 800744e: 3302 adds r3, #2 8007450: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8007454: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 8007456: 697b ldr r3, [r7, #20] 8007458: f003 0303 and.w r3, r3, #3 800745c: 009b lsls r3, r3, #2 800745e: 220f movs r2, #15 8007460: fa02 f303 lsl.w r3, r2, r3 8007464: 43db mvns r3, r3 8007466: 693a ldr r2, [r7, #16] 8007468: 4013 ands r3, r2 800746a: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 800746c: 687b ldr r3, [r7, #4] 800746e: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 8007472: d019 beq.n 80074a8 8007474: 687b ldr r3, [r7, #4] 8007476: 4a4a ldr r2, [pc, #296] @ (80075a0 ) 8007478: 4293 cmp r3, r2 800747a: d013 beq.n 80074a4 800747c: 687b ldr r3, [r7, #4] 800747e: 4a49 ldr r2, [pc, #292] @ (80075a4 ) 8007480: 4293 cmp r3, r2 8007482: d00d beq.n 80074a0 8007484: 687b ldr r3, [r7, #4] 8007486: 4a48 ldr r2, [pc, #288] @ (80075a8 ) 8007488: 4293 cmp r3, r2 800748a: d007 beq.n 800749c 800748c: 687b ldr r3, [r7, #4] 800748e: 4a47 ldr r2, [pc, #284] @ (80075ac ) 8007490: 4293 cmp r3, r2 8007492: d101 bne.n 8007498 8007494: 2304 movs r3, #4 8007496: e008 b.n 80074aa 8007498: 2307 movs r3, #7 800749a: e006 b.n 80074aa 800749c: 2303 movs r3, #3 800749e: e004 b.n 80074aa 80074a0: 2302 movs r3, #2 80074a2: e002 b.n 80074aa 80074a4: 2301 movs r3, #1 80074a6: e000 b.n 80074aa 80074a8: 2300 movs r3, #0 80074aa: 697a ldr r2, [r7, #20] 80074ac: f002 0203 and.w r2, r2, #3 80074b0: 0092 lsls r2, r2, #2 80074b2: 4093 lsls r3, r2 80074b4: 693a ldr r2, [r7, #16] 80074b6: 4313 orrs r3, r2 80074b8: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; 80074ba: 4938 ldr r1, [pc, #224] @ (800759c ) 80074bc: 697b ldr r3, [r7, #20] 80074be: 089b lsrs r3, r3, #2 80074c0: 3302 adds r3, #2 80074c2: 693a ldr r2, [r7, #16] 80074c4: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 80074c8: 4b39 ldr r3, [pc, #228] @ (80075b0 ) 80074ca: 681b ldr r3, [r3, #0] 80074cc: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80074ce: 68fb ldr r3, [r7, #12] 80074d0: 43db mvns r3, r3 80074d2: 693a ldr r2, [r7, #16] 80074d4: 4013 ands r3, r2 80074d6: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 80074d8: 683b ldr r3, [r7, #0] 80074da: 685b ldr r3, [r3, #4] 80074dc: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80074e0: 2b00 cmp r3, #0 80074e2: d003 beq.n 80074ec { temp |= iocurrent; 80074e4: 693a ldr r2, [r7, #16] 80074e6: 68fb ldr r3, [r7, #12] 80074e8: 4313 orrs r3, r2 80074ea: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 80074ec: 4a30 ldr r2, [pc, #192] @ (80075b0 ) 80074ee: 693b ldr r3, [r7, #16] 80074f0: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 80074f2: 4b2f ldr r3, [pc, #188] @ (80075b0 ) 80074f4: 685b ldr r3, [r3, #4] 80074f6: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80074f8: 68fb ldr r3, [r7, #12] 80074fa: 43db mvns r3, r3 80074fc: 693a ldr r2, [r7, #16] 80074fe: 4013 ands r3, r2 8007500: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8007502: 683b ldr r3, [r7, #0] 8007504: 685b ldr r3, [r3, #4] 8007506: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800750a: 2b00 cmp r3, #0 800750c: d003 beq.n 8007516 { temp |= iocurrent; 800750e: 693a ldr r2, [r7, #16] 8007510: 68fb ldr r3, [r7, #12] 8007512: 4313 orrs r3, r2 8007514: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8007516: 4a26 ldr r2, [pc, #152] @ (80075b0 ) 8007518: 693b ldr r3, [r7, #16] 800751a: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR1; 800751c: 4b24 ldr r3, [pc, #144] @ (80075b0 ) 800751e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8007522: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8007524: 68fb ldr r3, [r7, #12] 8007526: 43db mvns r3, r3 8007528: 693a ldr r2, [r7, #16] 800752a: 4013 ands r3, r2 800752c: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 800752e: 683b ldr r3, [r7, #0] 8007530: 685b ldr r3, [r3, #4] 8007532: f403 3380 and.w r3, r3, #65536 @ 0x10000 8007536: 2b00 cmp r3, #0 8007538: d003 beq.n 8007542 { temp |= iocurrent; 800753a: 693a ldr r2, [r7, #16] 800753c: 68fb ldr r3, [r7, #12] 800753e: 4313 orrs r3, r2 8007540: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 8007542: 4a1b ldr r2, [pc, #108] @ (80075b0 ) 8007544: 693b ldr r3, [r7, #16] 8007546: f8c2 3080 str.w r3, [r2, #128] @ 0x80 temp = EXTI->EMR1; 800754a: 4b19 ldr r3, [pc, #100] @ (80075b0 ) 800754c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8007550: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8007552: 68fb ldr r3, [r7, #12] 8007554: 43db mvns r3, r3 8007556: 693a ldr r2, [r7, #16] 8007558: 4013 ands r3, r2 800755a: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 800755c: 683b ldr r3, [r7, #0] 800755e: 685b ldr r3, [r3, #4] 8007560: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007564: 2b00 cmp r3, #0 8007566: d003 beq.n 8007570 { temp |= iocurrent; 8007568: 693a ldr r2, [r7, #16] 800756a: 68fb ldr r3, [r7, #12] 800756c: 4313 orrs r3, r2 800756e: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8007570: 4a0f ldr r2, [pc, #60] @ (80075b0 ) 8007572: 693b ldr r3, [r7, #16] 8007574: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } } position++; 8007578: 697b ldr r3, [r7, #20] 800757a: 3301 adds r3, #1 800757c: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 800757e: 683b ldr r3, [r7, #0] 8007580: 681a ldr r2, [r3, #0] 8007582: 697b ldr r3, [r7, #20] 8007584: fa22 f303 lsr.w r3, r2, r3 8007588: 2b00 cmp r3, #0 800758a: f47f aeab bne.w 80072e4 } } 800758e: bf00 nop 8007590: bf00 nop 8007592: 371c adds r7, #28 8007594: 46bd mov sp, r7 8007596: f85d 7b04 ldr.w r7, [sp], #4 800759a: 4770 bx lr 800759c: 40010000 .word 0x40010000 80075a0: 48000400 .word 0x48000400 80075a4: 48000800 .word 0x48000800 80075a8: 48000c00 .word 0x48000c00 80075ac: 48001000 .word 0x48001000 80075b0: 58000800 .word 0x58000800 080075b4 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80075b4: b480 push {r7} 80075b6: b083 sub sp, #12 80075b8: af00 add r7, sp, #0 80075ba: 6078 str r0, [r7, #4] 80075bc: 460b mov r3, r1 80075be: 807b strh r3, [r7, #2] 80075c0: 4613 mov r3, r2 80075c2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80075c4: 787b ldrb r3, [r7, #1] 80075c6: 2b00 cmp r3, #0 80075c8: d003 beq.n 80075d2 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 80075ca: 887a ldrh r2, [r7, #2] 80075cc: 687b ldr r3, [r7, #4] 80075ce: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 80075d0: e002 b.n 80075d8 GPIOx->BRR = (uint32_t)GPIO_Pin; 80075d2: 887a ldrh r2, [r7, #2] 80075d4: 687b ldr r3, [r7, #4] 80075d6: 629a str r2, [r3, #40] @ 0x28 } 80075d8: bf00 nop 80075da: 370c adds r7, #12 80075dc: 46bd mov sp, r7 80075de: f85d 7b04 ldr.w r7, [sp], #4 80075e2: 4770 bx lr 080075e4 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 80075e4: b580 push {r7, lr} 80075e6: b082 sub sp, #8 80075e8: af00 add r7, sp, #0 80075ea: 4603 mov r3, r0 80075ec: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) 80075ee: 4b08 ldr r3, [pc, #32] @ (8007610 ) 80075f0: 68da ldr r2, [r3, #12] 80075f2: 88fb ldrh r3, [r7, #6] 80075f4: 4013 ands r3, r2 80075f6: 2b00 cmp r3, #0 80075f8: d006 beq.n 8007608 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 80075fa: 4a05 ldr r2, [pc, #20] @ (8007610 ) 80075fc: 88fb ldrh r3, [r7, #6] 80075fe: 60d3 str r3, [r2, #12] HAL_GPIO_EXTI_Callback(GPIO_Pin); 8007600: 88fb ldrh r3, [r7, #6] 8007602: 4618 mov r0, r3 8007604: f7fd ff7a bl 80054fc } } 8007608: bf00 nop 800760a: 3708 adds r7, #8 800760c: 46bd mov sp, r7 800760e: bd80 pop {r7, pc} 8007610: 58000800 .word 0x58000800 08007614 : /** * @brief This function handles HSEM interrupt request * @retval None */ void HAL_HSEM_IRQHandler(void) { 8007614: b580 push {r7, lr} 8007616: b082 sub sp, #8 8007618: af00 add r7, sp, #0 uint32_t statusreg; /* Get the list of masked freed semaphores*/ statusreg = HSEM_COMMON->MISR; 800761a: 4b0a ldr r3, [pc, #40] @ (8007644 ) 800761c: 68db ldr r3, [r3, #12] 800761e: 607b str r3, [r7, #4] /*Disable Interrupts*/ HSEM_COMMON->IER &= ~((uint32_t)statusreg); 8007620: 4b08 ldr r3, [pc, #32] @ (8007644 ) 8007622: 681a ldr r2, [r3, #0] 8007624: 687b ldr r3, [r7, #4] 8007626: 43db mvns r3, r3 8007628: 4906 ldr r1, [pc, #24] @ (8007644 ) 800762a: 4013 ands r3, r2 800762c: 600b str r3, [r1, #0] /*Clear Flags*/ HSEM_COMMON->ICR = ((uint32_t)statusreg); 800762e: 4a05 ldr r2, [pc, #20] @ (8007644 ) 8007630: 687b ldr r3, [r7, #4] 8007632: 6053 str r3, [r2, #4] /* Call FreeCallback */ HAL_HSEM_FreeCallback(statusreg); 8007634: 6878 ldr r0, [r7, #4] 8007636: f000 f807 bl 8007648 } 800763a: bf00 nop 800763c: 3708 adds r7, #8 800763e: 46bd mov sp, r7 8007640: bd80 pop {r7, pc} 8007642: bf00 nop 8007644: 58001500 .word 0x58001500 08007648 : * @brief Semaphore Released Callback. * @param SemMask: Mask of Released semaphores * @retval None */ __weak void HAL_HSEM_FreeCallback(uint32_t SemMask) { 8007648: b480 push {r7} 800764a: b083 sub sp, #12 800764c: af00 add r7, sp, #0 800764e: 6078 str r0, [r7, #4] UNUSED(SemMask); /* NOTE : This function should not be modified, when the callback is needed, the HAL_HSEM_FreeCallback can be implemented in the user file */ } 8007650: bf00 nop 8007652: 370c adds r7, #12 8007654: 46bd mov sp, r7 8007656: f85d 7b04 ldr.w r7, [sp], #4 800765a: 4770 bx lr 0800765c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 800765c: b580 push {r7, lr} 800765e: b082 sub sp, #8 8007660: af00 add r7, sp, #0 8007662: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 8007664: 687b ldr r3, [r7, #4] 8007666: 2b00 cmp r3, #0 8007668: d101 bne.n 800766e { return HAL_ERROR; 800766a: 2301 movs r3, #1 800766c: e08d b.n 800778a assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 800766e: 687b ldr r3, [r7, #4] 8007670: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007674: b2db uxtb r3, r3 8007676: 2b00 cmp r3, #0 8007678: d106 bne.n 8007688 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 800767a: 687b ldr r3, [r7, #4] 800767c: 2200 movs r2, #0 800767e: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 8007682: 6878 ldr r0, [r7, #4] 8007684: f7fe fcc2 bl 800600c #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8007688: 687b ldr r3, [r7, #4] 800768a: 2224 movs r2, #36 @ 0x24 800768c: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8007690: 687b ldr r3, [r7, #4] 8007692: 681b ldr r3, [r3, #0] 8007694: 681a ldr r2, [r3, #0] 8007696: 687b ldr r3, [r7, #4] 8007698: 681b ldr r3, [r3, #0] 800769a: f022 0201 bic.w r2, r2, #1 800769e: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 80076a0: 687b ldr r3, [r7, #4] 80076a2: 685a ldr r2, [r3, #4] 80076a4: 687b ldr r3, [r7, #4] 80076a6: 681b ldr r3, [r3, #0] 80076a8: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000 80076ac: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 80076ae: 687b ldr r3, [r7, #4] 80076b0: 681b ldr r3, [r3, #0] 80076b2: 689a ldr r2, [r3, #8] 80076b4: 687b ldr r3, [r7, #4] 80076b6: 681b ldr r3, [r3, #0] 80076b8: f422 4200 bic.w r2, r2, #32768 @ 0x8000 80076bc: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 80076be: 687b ldr r3, [r7, #4] 80076c0: 68db ldr r3, [r3, #12] 80076c2: 2b01 cmp r3, #1 80076c4: d107 bne.n 80076d6 { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 80076c6: 687b ldr r3, [r7, #4] 80076c8: 689a ldr r2, [r3, #8] 80076ca: 687b ldr r3, [r7, #4] 80076cc: 681b ldr r3, [r3, #0] 80076ce: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80076d2: 609a str r2, [r3, #8] 80076d4: e006 b.n 80076e4 } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 80076d6: 687b ldr r3, [r7, #4] 80076d8: 689a ldr r2, [r3, #8] 80076da: 687b ldr r3, [r7, #4] 80076dc: 681b ldr r3, [r3, #0] 80076de: f442 4204 orr.w r2, r2, #33792 @ 0x8400 80076e2: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 80076e4: 687b ldr r3, [r7, #4] 80076e6: 68db ldr r3, [r3, #12] 80076e8: 2b02 cmp r3, #2 80076ea: d108 bne.n 80076fe { SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 80076ec: 687b ldr r3, [r7, #4] 80076ee: 681b ldr r3, [r3, #0] 80076f0: 685a ldr r2, [r3, #4] 80076f2: 687b ldr r3, [r7, #4] 80076f4: 681b ldr r3, [r3, #0] 80076f6: f442 6200 orr.w r2, r2, #2048 @ 0x800 80076fa: 605a str r2, [r3, #4] 80076fc: e007 b.n 800770e } else { /* Clear the I2C ADD10 bit */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 80076fe: 687b ldr r3, [r7, #4] 8007700: 681b ldr r3, [r3, #0] 8007702: 685a ldr r2, [r3, #4] 8007704: 687b ldr r3, [r7, #4] 8007706: 681b ldr r3, [r3, #0] 8007708: f422 6200 bic.w r2, r2, #2048 @ 0x800 800770c: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 800770e: 687b ldr r3, [r7, #4] 8007710: 681b ldr r3, [r3, #0] 8007712: 685b ldr r3, [r3, #4] 8007714: 687a ldr r2, [r7, #4] 8007716: 6812 ldr r2, [r2, #0] 8007718: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800771c: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8007720: 6053 str r3, [r2, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8007722: 687b ldr r3, [r7, #4] 8007724: 681b ldr r3, [r3, #0] 8007726: 68da ldr r2, [r3, #12] 8007728: 687b ldr r3, [r7, #4] 800772a: 681b ldr r3, [r3, #0] 800772c: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8007730: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8007732: 687b ldr r3, [r7, #4] 8007734: 691a ldr r2, [r3, #16] 8007736: 687b ldr r3, [r7, #4] 8007738: 695b ldr r3, [r3, #20] 800773a: ea42 0103 orr.w r1, r2, r3 (hi2c->Init.OwnAddress2Masks << 8)); 800773e: 687b ldr r3, [r7, #4] 8007740: 699b ldr r3, [r3, #24] 8007742: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8007744: 687b ldr r3, [r7, #4] 8007746: 681b ldr r3, [r3, #0] 8007748: 430a orrs r2, r1 800774a: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 800774c: 687b ldr r3, [r7, #4] 800774e: 69d9 ldr r1, [r3, #28] 8007750: 687b ldr r3, [r7, #4] 8007752: 6a1a ldr r2, [r3, #32] 8007754: 687b ldr r3, [r7, #4] 8007756: 681b ldr r3, [r3, #0] 8007758: 430a orrs r2, r1 800775a: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 800775c: 687b ldr r3, [r7, #4] 800775e: 681b ldr r3, [r3, #0] 8007760: 681a ldr r2, [r3, #0] 8007762: 687b ldr r3, [r7, #4] 8007764: 681b ldr r3, [r3, #0] 8007766: f042 0201 orr.w r2, r2, #1 800776a: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800776c: 687b ldr r3, [r7, #4] 800776e: 2200 movs r2, #0 8007770: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 8007772: 687b ldr r3, [r7, #4] 8007774: 2220 movs r2, #32 8007776: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 800777a: 687b ldr r3, [r7, #4] 800777c: 2200 movs r2, #0 800777e: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8007780: 687b ldr r3, [r7, #4] 8007782: 2200 movs r2, #0 8007784: f883 2042 strb.w r2, [r3, #66] @ 0x42 return HAL_OK; 8007788: 2300 movs r3, #0 } 800778a: 4618 mov r0, r3 800778c: 3708 adds r7, #8 800778e: 46bd mov sp, r7 8007790: bd80 pop {r7, pc} ... 08007794 : * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { 8007794: b580 push {r7, lr} 8007796: b088 sub sp, #32 8007798: af02 add r7, sp, #8 800779a: 60f8 str r0, [r7, #12] 800779c: 4608 mov r0, r1 800779e: 4611 mov r1, r2 80077a0: 461a mov r2, r3 80077a2: 4603 mov r3, r0 80077a4: 817b strh r3, [r7, #10] 80077a6: 460b mov r3, r1 80077a8: 813b strh r3, [r7, #8] 80077aa: 4613 mov r3, r2 80077ac: 80fb strh r3, [r7, #6] HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 80077ae: 68fb ldr r3, [r7, #12] 80077b0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80077b4: b2db uxtb r3, r3 80077b6: 2b20 cmp r3, #32 80077b8: f040 80c3 bne.w 8007942 { if ((pData == NULL) || (Size == 0U)) 80077bc: 6a3b ldr r3, [r7, #32] 80077be: 2b00 cmp r3, #0 80077c0: d002 beq.n 80077c8 80077c2: 8cbb ldrh r3, [r7, #36] @ 0x24 80077c4: 2b00 cmp r3, #0 80077c6: d105 bne.n 80077d4 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 80077c8: 68fb ldr r3, [r7, #12] 80077ca: f44f 7200 mov.w r2, #512 @ 0x200 80077ce: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 80077d0: 2301 movs r3, #1 80077d2: e0b7 b.n 8007944 } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) 80077d4: 68fb ldr r3, [r7, #12] 80077d6: 681b ldr r3, [r3, #0] 80077d8: 699b ldr r3, [r3, #24] 80077da: f403 4300 and.w r3, r3, #32768 @ 0x8000 80077de: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80077e2: d101 bne.n 80077e8 { return HAL_BUSY; 80077e4: 2302 movs r3, #2 80077e6: e0ad b.n 8007944 } /* Process Locked */ __HAL_LOCK(hi2c); 80077e8: 68fb ldr r3, [r7, #12] 80077ea: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80077ee: 2b01 cmp r3, #1 80077f0: d101 bne.n 80077f6 80077f2: 2302 movs r3, #2 80077f4: e0a6 b.n 8007944 80077f6: 68fb ldr r3, [r7, #12] 80077f8: 2201 movs r2, #1 80077fa: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY_TX; 80077fe: 68fb ldr r3, [r7, #12] 8007800: 2221 movs r2, #33 @ 0x21 8007802: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_MEM; 8007806: 68fb ldr r3, [r7, #12] 8007808: 2240 movs r2, #64 @ 0x40 800780a: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800780e: 68fb ldr r3, [r7, #12] 8007810: 2200 movs r2, #0 8007812: 645a str r2, [r3, #68] @ 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8007814: 68fb ldr r3, [r7, #12] 8007816: 6a3a ldr r2, [r7, #32] 8007818: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 800781a: 68fb ldr r3, [r7, #12] 800781c: 8cba ldrh r2, [r7, #36] @ 0x24 800781e: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8007820: 68fb ldr r3, [r7, #12] 8007822: 4a4a ldr r2, [pc, #296] @ (800794c ) 8007824: 62da str r2, [r3, #44] @ 0x2c hi2c->XferISR = I2C_Mem_ISR_DMA; 8007826: 68fb ldr r3, [r7, #12] 8007828: 4a49 ldr r2, [pc, #292] @ (8007950 ) 800782a: 635a str r2, [r3, #52] @ 0x34 hi2c->Devaddress = DevAddress; 800782c: 897a ldrh r2, [r7, #10] 800782e: 68fb ldr r3, [r7, #12] 8007830: 64da str r2, [r3, #76] @ 0x4c if (hi2c->XferCount > MAX_NBYTE_SIZE) 8007832: 68fb ldr r3, [r7, #12] 8007834: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007836: b29b uxth r3, r3 8007838: 2bff cmp r3, #255 @ 0xff 800783a: d903 bls.n 8007844 { hi2c->XferSize = MAX_NBYTE_SIZE; 800783c: 68fb ldr r3, [r7, #12] 800783e: 22ff movs r2, #255 @ 0xff 8007840: 851a strh r2, [r3, #40] @ 0x28 8007842: e004 b.n 800784e } else { hi2c->XferSize = hi2c->XferCount; 8007844: 68fb ldr r3, [r7, #12] 8007846: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007848: b29a uxth r2, r3 800784a: 68fb ldr r3, [r7, #12] 800784c: 851a strh r2, [r3, #40] @ 0x28 } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 800784e: 88fb ldrh r3, [r7, #6] 8007850: 2b01 cmp r3, #1 8007852: d109 bne.n 8007868 { /* Prefetch Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8007854: 893b ldrh r3, [r7, #8] 8007856: b2da uxtb r2, r3 8007858: 68fb ldr r3, [r7, #12] 800785a: 681b ldr r3, [r3, #0] 800785c: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 800785e: 68fb ldr r3, [r7, #12] 8007860: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007864: 651a str r2, [r3, #80] @ 0x50 8007866: e00b b.n 8007880 } /* If Memory address size is 16Bit */ else { /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); 8007868: 893b ldrh r3, [r7, #8] 800786a: 0a1b lsrs r3, r3, #8 800786c: b29b uxth r3, r3 800786e: b2da uxtb r2, r3 8007870: 68fb ldr r3, [r7, #12] 8007872: 681b ldr r3, [r3, #0] 8007874: 629a str r2, [r3, #40] @ 0x28 /* Prepare Memaddress buffer for LSB part */ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); 8007876: 893b ldrh r3, [r7, #8] 8007878: b2db uxtb r3, r3 800787a: 461a mov r2, r3 800787c: 68fb ldr r3, [r7, #12] 800787e: 651a str r2, [r3, #80] @ 0x50 } if (hi2c->hdmatx != NULL) 8007880: 68fb ldr r3, [r7, #12] 8007882: 6b9b ldr r3, [r3, #56] @ 0x38 8007884: 2b00 cmp r3, #0 8007886: d020 beq.n 80078ca { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; 8007888: 68fb ldr r3, [r7, #12] 800788a: 6b9b ldr r3, [r3, #56] @ 0x38 800788c: 4a31 ldr r2, [pc, #196] @ (8007954 ) 800788e: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 8007890: 68fb ldr r3, [r7, #12] 8007892: 6b9b ldr r3, [r3, #56] @ 0x38 8007894: 4a30 ldr r2, [pc, #192] @ (8007958 ) 8007896: 635a str r2, [r3, #52] @ 0x34 /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; 8007898: 68fb ldr r3, [r7, #12] 800789a: 6b9b ldr r3, [r3, #56] @ 0x38 800789c: 2200 movs r2, #0 800789e: 631a str r2, [r3, #48] @ 0x30 hi2c->hdmatx->XferAbortCallback = NULL; 80078a0: 68fb ldr r3, [r7, #12] 80078a2: 6b9b ldr r3, [r3, #56] @ 0x38 80078a4: 2200 movs r2, #0 80078a6: 639a str r2, [r3, #56] @ 0x38 /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, 80078a8: 68fb ldr r3, [r7, #12] 80078aa: 6b98 ldr r0, [r3, #56] @ 0x38 80078ac: 6a39 ldr r1, [r7, #32] 80078ae: 68fb ldr r3, [r7, #12] 80078b0: 681b ldr r3, [r3, #0] 80078b2: 3328 adds r3, #40 @ 0x28 80078b4: 461a mov r2, r3 hi2c->XferSize); 80078b6: 68fb ldr r3, [r7, #12] 80078b8: 8d1b ldrh r3, [r3, #40] @ 0x28 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, 80078ba: f7ff fa73 bl 8006da4 80078be: 4603 mov r3, r0 80078c0: 75fb strb r3, [r7, #23] __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) 80078c2: 7dfb ldrb r3, [r7, #23] 80078c4: 2b00 cmp r3, #0 80078c6: d128 bne.n 800791a 80078c8: e013 b.n 80078f2 hi2c->State = HAL_I2C_STATE_READY; 80078ca: 68fb ldr r3, [r7, #12] 80078cc: 2220 movs r2, #32 80078ce: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 80078d2: 68fb ldr r3, [r7, #12] 80078d4: 2200 movs r2, #0 80078d6: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 80078da: 68fb ldr r3, [r7, #12] 80078dc: 6c5b ldr r3, [r3, #68] @ 0x44 80078de: f043 0280 orr.w r2, r3, #128 @ 0x80 80078e2: 68fb ldr r3, [r7, #12] 80078e4: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(hi2c); 80078e6: 68fb ldr r3, [r7, #12] 80078e8: 2200 movs r2, #0 80078ea: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 80078ee: 2301 movs r3, #1 80078f0: e028 b.n 8007944 { /* Send Slave Address and Memory Address */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 80078f2: 88fb ldrh r3, [r7, #6] 80078f4: b2da uxtb r2, r3 80078f6: 8979 ldrh r1, [r7, #10] 80078f8: 4b18 ldr r3, [pc, #96] @ (800795c ) 80078fa: 9300 str r3, [sp, #0] 80078fc: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8007900: 68f8 ldr r0, [r7, #12] 8007902: f001 fb9b bl 800903c /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007906: 68fb ldr r3, [r7, #12] 8007908: 2200 movs r2, #0 800790a: f883 2040 strb.w r2, [r3, #64] @ 0x40 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); 800790e: 2101 movs r1, #1 8007910: 68f8 ldr r0, [r7, #12] 8007912: f001 fbc5 bl 80090a0 __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; 8007916: 2300 movs r3, #0 8007918: e014 b.n 8007944 hi2c->State = HAL_I2C_STATE_READY; 800791a: 68fb ldr r3, [r7, #12] 800791c: 2220 movs r2, #32 800791e: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8007922: 68fb ldr r3, [r7, #12] 8007924: 2200 movs r2, #0 8007926: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 800792a: 68fb ldr r3, [r7, #12] 800792c: 6c5b ldr r3, [r3, #68] @ 0x44 800792e: f043 0210 orr.w r2, r3, #16 8007932: 68fb ldr r3, [r7, #12] 8007934: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(hi2c); 8007936: 68fb ldr r3, [r7, #12] 8007938: 2200 movs r2, #0 800793a: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 800793e: 2301 movs r3, #1 8007940: e000 b.n 8007944 } else { return HAL_BUSY; 8007942: 2302 movs r3, #2 } } 8007944: 4618 mov r0, r3 8007946: 3718 adds r7, #24 8007948: 46bd mov sp, r7 800794a: bd80 pop {r7, pc} 800794c: ffff0000 .word 0xffff0000 8007950: 080080bd .word 0x080080bd 8007954: 08008ea7 .word 0x08008ea7 8007958: 08008fd3 .word 0x08008fd3 800795c: 80002000 .word 0x80002000 08007960 : * @param Size Amount of data to be read * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { 8007960: b580 push {r7, lr} 8007962: b088 sub sp, #32 8007964: af02 add r7, sp, #8 8007966: 60f8 str r0, [r7, #12] 8007968: 4608 mov r0, r1 800796a: 4611 mov r1, r2 800796c: 461a mov r2, r3 800796e: 4603 mov r3, r0 8007970: 817b strh r3, [r7, #10] 8007972: 460b mov r3, r1 8007974: 813b strh r3, [r7, #8] 8007976: 4613 mov r3, r2 8007978: 80fb strh r3, [r7, #6] HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 800797a: 68fb ldr r3, [r7, #12] 800797c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007980: b2db uxtb r3, r3 8007982: 2b20 cmp r3, #32 8007984: f040 80c2 bne.w 8007b0c { if ((pData == NULL) || (Size == 0U)) 8007988: 6a3b ldr r3, [r7, #32] 800798a: 2b00 cmp r3, #0 800798c: d002 beq.n 8007994 800798e: 8cbb ldrh r3, [r7, #36] @ 0x24 8007990: 2b00 cmp r3, #0 8007992: d105 bne.n 80079a0 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 8007994: 68fb ldr r3, [r7, #12] 8007996: f44f 7200 mov.w r2, #512 @ 0x200 800799a: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 800799c: 2301 movs r3, #1 800799e: e0b6 b.n 8007b0e } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) 80079a0: 68fb ldr r3, [r7, #12] 80079a2: 681b ldr r3, [r3, #0] 80079a4: 699b ldr r3, [r3, #24] 80079a6: f403 4300 and.w r3, r3, #32768 @ 0x8000 80079aa: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80079ae: d101 bne.n 80079b4 { return HAL_BUSY; 80079b0: 2302 movs r3, #2 80079b2: e0ac b.n 8007b0e } /* Process Locked */ __HAL_LOCK(hi2c); 80079b4: 68fb ldr r3, [r7, #12] 80079b6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80079ba: 2b01 cmp r3, #1 80079bc: d101 bne.n 80079c2 80079be: 2302 movs r3, #2 80079c0: e0a5 b.n 8007b0e 80079c2: 68fb ldr r3, [r7, #12] 80079c4: 2201 movs r2, #1 80079c6: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY_RX; 80079ca: 68fb ldr r3, [r7, #12] 80079cc: 2222 movs r2, #34 @ 0x22 80079ce: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_MEM; 80079d2: 68fb ldr r3, [r7, #12] 80079d4: 2240 movs r2, #64 @ 0x40 80079d6: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80079da: 68fb ldr r3, [r7, #12] 80079dc: 2200 movs r2, #0 80079de: 645a str r2, [r3, #68] @ 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 80079e0: 68fb ldr r3, [r7, #12] 80079e2: 6a3a ldr r2, [r7, #32] 80079e4: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 80079e6: 68fb ldr r3, [r7, #12] 80079e8: 8cba ldrh r2, [r7, #36] @ 0x24 80079ea: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80079ec: 68fb ldr r3, [r7, #12] 80079ee: 4a4a ldr r2, [pc, #296] @ (8007b18 ) 80079f0: 62da str r2, [r3, #44] @ 0x2c hi2c->XferISR = I2C_Mem_ISR_DMA; 80079f2: 68fb ldr r3, [r7, #12] 80079f4: 4a49 ldr r2, [pc, #292] @ (8007b1c ) 80079f6: 635a str r2, [r3, #52] @ 0x34 hi2c->Devaddress = DevAddress; 80079f8: 897a ldrh r2, [r7, #10] 80079fa: 68fb ldr r3, [r7, #12] 80079fc: 64da str r2, [r3, #76] @ 0x4c if (hi2c->XferCount > MAX_NBYTE_SIZE) 80079fe: 68fb ldr r3, [r7, #12] 8007a00: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007a02: b29b uxth r3, r3 8007a04: 2bff cmp r3, #255 @ 0xff 8007a06: d903 bls.n 8007a10 { hi2c->XferSize = MAX_NBYTE_SIZE; 8007a08: 68fb ldr r3, [r7, #12] 8007a0a: 22ff movs r2, #255 @ 0xff 8007a0c: 851a strh r2, [r3, #40] @ 0x28 8007a0e: e004 b.n 8007a1a } else { hi2c->XferSize = hi2c->XferCount; 8007a10: 68fb ldr r3, [r7, #12] 8007a12: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007a14: b29a uxth r2, r3 8007a16: 68fb ldr r3, [r7, #12] 8007a18: 851a strh r2, [r3, #40] @ 0x28 } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 8007a1a: 88fb ldrh r3, [r7, #6] 8007a1c: 2b01 cmp r3, #1 8007a1e: d109 bne.n 8007a34 { /* Prefetch Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8007a20: 893b ldrh r3, [r7, #8] 8007a22: b2da uxtb r2, r3 8007a24: 68fb ldr r3, [r7, #12] 8007a26: 681b ldr r3, [r3, #0] 8007a28: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 8007a2a: 68fb ldr r3, [r7, #12] 8007a2c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007a30: 651a str r2, [r3, #80] @ 0x50 8007a32: e00b b.n 8007a4c } /* If Memory address size is 16Bit */ else { /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); 8007a34: 893b ldrh r3, [r7, #8] 8007a36: 0a1b lsrs r3, r3, #8 8007a38: b29b uxth r3, r3 8007a3a: b2da uxtb r2, r3 8007a3c: 68fb ldr r3, [r7, #12] 8007a3e: 681b ldr r3, [r3, #0] 8007a40: 629a str r2, [r3, #40] @ 0x28 /* Prepare Memaddress buffer for LSB part */ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); 8007a42: 893b ldrh r3, [r7, #8] 8007a44: b2db uxtb r3, r3 8007a46: 461a mov r2, r3 8007a48: 68fb ldr r3, [r7, #12] 8007a4a: 651a str r2, [r3, #80] @ 0x50 } if (hi2c->hdmarx != NULL) 8007a4c: 68fb ldr r3, [r7, #12] 8007a4e: 6bdb ldr r3, [r3, #60] @ 0x3c 8007a50: 2b00 cmp r3, #0 8007a52: d020 beq.n 8007a96 { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; 8007a54: 68fb ldr r3, [r7, #12] 8007a56: 6bdb ldr r3, [r3, #60] @ 0x3c 8007a58: 4a31 ldr r2, [pc, #196] @ (8007b20 ) 8007a5a: 62da str r2, [r3, #44] @ 0x2c /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 8007a5c: 68fb ldr r3, [r7, #12] 8007a5e: 6bdb ldr r3, [r3, #60] @ 0x3c 8007a60: 4a30 ldr r2, [pc, #192] @ (8007b24 ) 8007a62: 635a str r2, [r3, #52] @ 0x34 /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; 8007a64: 68fb ldr r3, [r7, #12] 8007a66: 6bdb ldr r3, [r3, #60] @ 0x3c 8007a68: 2200 movs r2, #0 8007a6a: 631a str r2, [r3, #48] @ 0x30 hi2c->hdmarx->XferAbortCallback = NULL; 8007a6c: 68fb ldr r3, [r7, #12] 8007a6e: 6bdb ldr r3, [r3, #60] @ 0x3c 8007a70: 2200 movs r2, #0 8007a72: 639a str r2, [r3, #56] @ 0x38 /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, 8007a74: 68fb ldr r3, [r7, #12] 8007a76: 6bd8 ldr r0, [r3, #60] @ 0x3c 8007a78: 68fb ldr r3, [r7, #12] 8007a7a: 681b ldr r3, [r3, #0] 8007a7c: 3324 adds r3, #36 @ 0x24 8007a7e: 4619 mov r1, r3 8007a80: 6a3a ldr r2, [r7, #32] hi2c->XferSize); 8007a82: 68fb ldr r3, [r7, #12] 8007a84: 8d1b ldrh r3, [r3, #40] @ 0x28 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, 8007a86: f7ff f98d bl 8006da4 8007a8a: 4603 mov r3, r0 8007a8c: 75fb strb r3, [r7, #23] __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) 8007a8e: 7dfb ldrb r3, [r7, #23] 8007a90: 2b00 cmp r3, #0 8007a92: d127 bne.n 8007ae4 8007a94: e013 b.n 8007abe hi2c->State = HAL_I2C_STATE_READY; 8007a96: 68fb ldr r3, [r7, #12] 8007a98: 2220 movs r2, #32 8007a9a: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8007a9e: 68fb ldr r3, [r7, #12] 8007aa0: 2200 movs r2, #0 8007aa2: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 8007aa6: 68fb ldr r3, [r7, #12] 8007aa8: 6c5b ldr r3, [r3, #68] @ 0x44 8007aaa: f043 0280 orr.w r2, r3, #128 @ 0x80 8007aae: 68fb ldr r3, [r7, #12] 8007ab0: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(hi2c); 8007ab2: 68fb ldr r3, [r7, #12] 8007ab4: 2200 movs r2, #0 8007ab6: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 8007aba: 2301 movs r3, #1 8007abc: e027 b.n 8007b0e { /* Send Slave Address and Memory Address */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 8007abe: 88fb ldrh r3, [r7, #6] 8007ac0: b2da uxtb r2, r3 8007ac2: 8979 ldrh r1, [r7, #10] 8007ac4: 4b18 ldr r3, [pc, #96] @ (8007b28 ) 8007ac6: 9300 str r3, [sp, #0] 8007ac8: 2300 movs r3, #0 8007aca: 68f8 ldr r0, [r7, #12] 8007acc: f001 fab6 bl 800903c /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007ad0: 68fb ldr r3, [r7, #12] 8007ad2: 2200 movs r2, #0 8007ad4: f883 2040 strb.w r2, [r3, #64] @ 0x40 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); 8007ad8: 2101 movs r1, #1 8007ada: 68f8 ldr r0, [r7, #12] 8007adc: f001 fae0 bl 80090a0 __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; 8007ae0: 2300 movs r3, #0 8007ae2: e014 b.n 8007b0e hi2c->State = HAL_I2C_STATE_READY; 8007ae4: 68fb ldr r3, [r7, #12] 8007ae6: 2220 movs r2, #32 8007ae8: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8007aec: 68fb ldr r3, [r7, #12] 8007aee: 2200 movs r2, #0 8007af0: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 8007af4: 68fb ldr r3, [r7, #12] 8007af6: 6c5b ldr r3, [r3, #68] @ 0x44 8007af8: f043 0210 orr.w r2, r3, #16 8007afc: 68fb ldr r3, [r7, #12] 8007afe: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(hi2c); 8007b00: 68fb ldr r3, [r7, #12] 8007b02: 2200 movs r2, #0 8007b04: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_ERROR; 8007b08: 2301 movs r3, #1 8007b0a: e000 b.n 8007b0e } else { return HAL_BUSY; 8007b0c: 2302 movs r3, #2 } } 8007b0e: 4618 mov r0, r3 8007b10: 3718 adds r7, #24 8007b12: 46bd mov sp, r7 8007b14: bd80 pop {r7, pc} 8007b16: bf00 nop 8007b18: ffff0000 .word 0xffff0000 8007b1c: 080080bd .word 0x080080bd 8007b20: 08008f3d .word 0x08008f3d 8007b24: 08008fd3 .word 0x08008fd3 8007b28: 80002000 .word 0x80002000 08007b2c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { 8007b2c: b580 push {r7, lr} 8007b2e: b084 sub sp, #16 8007b30: af00 add r7, sp, #0 8007b32: 6078 str r0, [r7, #4] /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8007b34: 687b ldr r3, [r7, #4] 8007b36: 681b ldr r3, [r3, #0] 8007b38: 699b ldr r3, [r3, #24] 8007b3a: 60fb str r3, [r7, #12] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 8007b3c: 687b ldr r3, [r7, #4] 8007b3e: 681b ldr r3, [r3, #0] 8007b40: 681b ldr r3, [r3, #0] 8007b42: 60bb str r3, [r7, #8] /* I2C events treatment -------------------------------------*/ if (hi2c->XferISR != NULL) 8007b44: 687b ldr r3, [r7, #4] 8007b46: 6b5b ldr r3, [r3, #52] @ 0x34 8007b48: 2b00 cmp r3, #0 8007b4a: d005 beq.n 8007b58 { hi2c->XferISR(hi2c, itflags, itsources); 8007b4c: 687b ldr r3, [r7, #4] 8007b4e: 6b5b ldr r3, [r3, #52] @ 0x34 8007b50: 68ba ldr r2, [r7, #8] 8007b52: 68f9 ldr r1, [r7, #12] 8007b54: 6878 ldr r0, [r7, #4] 8007b56: 4798 blx r3 } } 8007b58: bf00 nop 8007b5a: 3710 adds r7, #16 8007b5c: 46bd mov sp, r7 8007b5e: bd80 pop {r7, pc} 08007b60 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { 8007b60: b580 push {r7, lr} 8007b62: b086 sub sp, #24 8007b64: af00 add r7, sp, #0 8007b66: 6078 str r0, [r7, #4] uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8007b68: 687b ldr r3, [r7, #4] 8007b6a: 681b ldr r3, [r3, #0] 8007b6c: 699b ldr r3, [r3, #24] 8007b6e: 617b str r3, [r7, #20] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 8007b70: 687b ldr r3, [r7, #4] 8007b72: 681b ldr r3, [r3, #0] 8007b74: 681b ldr r3, [r3, #0] 8007b76: 613b str r3, [r7, #16] uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 8007b78: 697b ldr r3, [r7, #20] 8007b7a: 0a1b lsrs r3, r3, #8 8007b7c: f003 0301 and.w r3, r3, #1 8007b80: 2b00 cmp r3, #0 8007b82: d010 beq.n 8007ba6 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8007b84: 693b ldr r3, [r7, #16] 8007b86: 09db lsrs r3, r3, #7 8007b88: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 8007b8c: 2b00 cmp r3, #0 8007b8e: d00a beq.n 8007ba6 { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; 8007b90: 687b ldr r3, [r7, #4] 8007b92: 6c5b ldr r3, [r3, #68] @ 0x44 8007b94: f043 0201 orr.w r2, r3, #1 8007b98: 687b ldr r3, [r7, #4] 8007b9a: 645a str r2, [r3, #68] @ 0x44 /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 8007b9c: 687b ldr r3, [r7, #4] 8007b9e: 681b ldr r3, [r3, #0] 8007ba0: f44f 7280 mov.w r2, #256 @ 0x100 8007ba4: 61da str r2, [r3, #28] } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 8007ba6: 697b ldr r3, [r7, #20] 8007ba8: 0a9b lsrs r3, r3, #10 8007baa: f003 0301 and.w r3, r3, #1 8007bae: 2b00 cmp r3, #0 8007bb0: d010 beq.n 8007bd4 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8007bb2: 693b ldr r3, [r7, #16] 8007bb4: 09db lsrs r3, r3, #7 8007bb6: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 8007bba: 2b00 cmp r3, #0 8007bbc: d00a beq.n 8007bd4 { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; 8007bbe: 687b ldr r3, [r7, #4] 8007bc0: 6c5b ldr r3, [r3, #68] @ 0x44 8007bc2: f043 0208 orr.w r2, r3, #8 8007bc6: 687b ldr r3, [r7, #4] 8007bc8: 645a str r2, [r3, #68] @ 0x44 /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 8007bca: 687b ldr r3, [r7, #4] 8007bcc: 681b ldr r3, [r3, #0] 8007bce: f44f 6280 mov.w r2, #1024 @ 0x400 8007bd2: 61da str r2, [r3, #28] } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 8007bd4: 697b ldr r3, [r7, #20] 8007bd6: 0a5b lsrs r3, r3, #9 8007bd8: f003 0301 and.w r3, r3, #1 8007bdc: 2b00 cmp r3, #0 8007bde: d010 beq.n 8007c02 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8007be0: 693b ldr r3, [r7, #16] 8007be2: 09db lsrs r3, r3, #7 8007be4: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 8007be8: 2b00 cmp r3, #0 8007bea: d00a beq.n 8007c02 { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; 8007bec: 687b ldr r3, [r7, #4] 8007bee: 6c5b ldr r3, [r3, #68] @ 0x44 8007bf0: f043 0202 orr.w r2, r3, #2 8007bf4: 687b ldr r3, [r7, #4] 8007bf6: 645a str r2, [r3, #68] @ 0x44 /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 8007bf8: 687b ldr r3, [r7, #4] 8007bfa: 681b ldr r3, [r3, #0] 8007bfc: f44f 7200 mov.w r2, #512 @ 0x200 8007c00: 61da str r2, [r3, #28] } /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 8007c02: 687b ldr r3, [r7, #4] 8007c04: 6c5b ldr r3, [r3, #68] @ 0x44 8007c06: 60fb str r3, [r7, #12] /* Call the Error Callback in case of Error detected */ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) 8007c08: 68fb ldr r3, [r7, #12] 8007c0a: f003 030b and.w r3, r3, #11 8007c0e: 2b00 cmp r3, #0 8007c10: d003 beq.n 8007c1a { I2C_ITError(hi2c, tmperror); 8007c12: 68f9 ldr r1, [r7, #12] 8007c14: 6878 ldr r0, [r7, #4] 8007c16: f001 f80b bl 8008c30 } } 8007c1a: bf00 nop 8007c1c: 3718 adds r7, #24 8007c1e: 46bd mov sp, r7 8007c20: bd80 pop {r7, pc} 08007c22 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { 8007c22: b480 push {r7} 8007c24: b083 sub sp, #12 8007c26: af00 add r7, sp, #0 8007c28: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterTxCpltCallback could be implemented in the user file */ } 8007c2a: bf00 nop 8007c2c: 370c adds r7, #12 8007c2e: 46bd mov sp, r7 8007c30: f85d 7b04 ldr.w r7, [sp], #4 8007c34: 4770 bx lr 08007c36 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { 8007c36: b480 push {r7} 8007c38: b083 sub sp, #12 8007c3a: af00 add r7, sp, #0 8007c3c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } 8007c3e: bf00 nop 8007c40: 370c adds r7, #12 8007c42: 46bd mov sp, r7 8007c44: f85d 7b04 ldr.w r7, [sp], #4 8007c48: 4770 bx lr 08007c4a : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { 8007c4a: b480 push {r7} 8007c4c: b083 sub sp, #12 8007c4e: af00 add r7, sp, #0 8007c50: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file */ } 8007c52: bf00 nop 8007c54: 370c adds r7, #12 8007c56: 46bd mov sp, r7 8007c58: f85d 7b04 ldr.w r7, [sp], #4 8007c5c: 4770 bx lr 08007c5e : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { 8007c5e: b480 push {r7} 8007c60: b083 sub sp, #12 8007c62: af00 add r7, sp, #0 8007c64: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file */ } 8007c66: bf00 nop 8007c68: 370c adds r7, #12 8007c6a: 46bd mov sp, r7 8007c6c: f85d 7b04 ldr.w r7, [sp], #4 8007c70: 4770 bx lr 08007c72 : * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { 8007c72: b480 push {r7} 8007c74: b083 sub sp, #12 8007c76: af00 add r7, sp, #0 8007c78: 6078 str r0, [r7, #4] 8007c7a: 460b mov r3, r1 8007c7c: 70fb strb r3, [r7, #3] 8007c7e: 4613 mov r3, r2 8007c80: 803b strh r3, [r7, #0] UNUSED(AddrMatchCode); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AddrCallback() could be implemented in the user file */ } 8007c82: bf00 nop 8007c84: 370c adds r7, #12 8007c86: 46bd mov sp, r7 8007c88: f85d 7b04 ldr.w r7, [sp], #4 8007c8c: 4770 bx lr 08007c8e : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { 8007c8e: b480 push {r7} 8007c90: b083 sub sp, #12 8007c92: af00 add r7, sp, #0 8007c94: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ListenCpltCallback() could be implemented in the user file */ } 8007c96: bf00 nop 8007c98: 370c adds r7, #12 8007c9a: 46bd mov sp, r7 8007c9c: f85d 7b04 ldr.w r7, [sp], #4 8007ca0: 4770 bx lr 08007ca2 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) { 8007ca2: b480 push {r7} 8007ca4: b083 sub sp, #12 8007ca6: af00 add r7, sp, #0 8007ca8: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AbortCpltCallback could be implemented in the user file */ } 8007caa: bf00 nop 8007cac: 370c adds r7, #12 8007cae: 46bd mov sp, r7 8007cb0: f85d 7b04 ldr.w r7, [sp], #4 8007cb4: 4770 bx lr 08007cb6 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval I2C Error Code */ uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) { 8007cb6: b480 push {r7} 8007cb8: b083 sub sp, #12 8007cba: af00 add r7, sp, #0 8007cbc: 6078 str r0, [r7, #4] return hi2c->ErrorCode; 8007cbe: 687b ldr r3, [r7, #4] 8007cc0: 6c5b ldr r3, [r3, #68] @ 0x44 } 8007cc2: 4618 mov r0, r3 8007cc4: 370c adds r7, #12 8007cc6: 46bd mov sp, r7 8007cc8: f85d 7b04 ldr.w r7, [sp], #4 8007ccc: 4770 bx lr 08007cce : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8007cce: b580 push {r7, lr} 8007cd0: b086 sub sp, #24 8007cd2: af00 add r7, sp, #0 8007cd4: 60f8 str r0, [r7, #12] 8007cd6: 60b9 str r1, [r7, #8] 8007cd8: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 8007cda: 68fb ldr r3, [r7, #12] 8007cdc: 6adb ldr r3, [r3, #44] @ 0x2c 8007cde: 617b str r3, [r7, #20] uint32_t tmpITFlags = ITFlags; 8007ce0: 68bb ldr r3, [r7, #8] 8007ce2: 613b str r3, [r7, #16] /* Process locked */ __HAL_LOCK(hi2c); 8007ce4: 68fb ldr r3, [r7, #12] 8007ce6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8007cea: 2b01 cmp r3, #1 8007cec: d101 bne.n 8007cf2 8007cee: 2302 movs r3, #2 8007cf0: e0ed b.n 8007ece 8007cf2: 68fb ldr r3, [r7, #12] 8007cf4: 2201 movs r2, #1 8007cf6: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007cfa: 693b ldr r3, [r7, #16] 8007cfc: 095b lsrs r3, r3, #5 8007cfe: f003 0301 and.w r3, r3, #1 8007d02: 2b00 cmp r3, #0 8007d04: d00a beq.n 8007d1c (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8007d06: 687b ldr r3, [r7, #4] 8007d08: 095b lsrs r3, r3, #5 8007d0a: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 8007d0e: 2b00 cmp r3, #0 8007d10: d004 beq.n 8007d1c { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); 8007d12: 6939 ldr r1, [r7, #16] 8007d14: 68f8 ldr r0, [r7, #12] 8007d16: f000 fdcb bl 80088b0 8007d1a: e0d3 b.n 8007ec4 } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8007d1c: 693b ldr r3, [r7, #16] 8007d1e: 091b lsrs r3, r3, #4 8007d20: f003 0301 and.w r3, r3, #1 8007d24: 2b00 cmp r3, #0 8007d26: d04d beq.n 8007dc4 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8007d28: 687b ldr r3, [r7, #4] 8007d2a: 091b lsrs r3, r3, #4 8007d2c: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8007d30: 2b00 cmp r3, #0 8007d32: d047 beq.n 8007dc4 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 8007d34: 68fb ldr r3, [r7, #12] 8007d36: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007d38: b29b uxth r3, r3 8007d3a: 2b00 cmp r3, #0 8007d3c: d128 bne.n 8007d90 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8007d3e: 68fb ldr r3, [r7, #12] 8007d40: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007d44: b2db uxtb r3, r3 8007d46: 2b28 cmp r3, #40 @ 0x28 8007d48: d108 bne.n 8007d5c 8007d4a: 697b ldr r3, [r7, #20] 8007d4c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8007d50: d104 bne.n 8007d5c /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8007d52: 6939 ldr r1, [r7, #16] 8007d54: 68f8 ldr r0, [r7, #12] 8007d56: f000 ff15 bl 8008b84 8007d5a: e032 b.n 8007dc2 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 8007d5c: 68fb ldr r3, [r7, #12] 8007d5e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007d62: b2db uxtb r3, r3 8007d64: 2b29 cmp r3, #41 @ 0x29 8007d66: d10e bne.n 8007d86 8007d68: 697b ldr r3, [r7, #20] 8007d6a: f513 3f80 cmn.w r3, #65536 @ 0x10000 8007d6e: d00a beq.n 8007d86 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007d70: 68fb ldr r3, [r7, #12] 8007d72: 681b ldr r3, [r3, #0] 8007d74: 2210 movs r2, #16 8007d76: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8007d78: 68f8 ldr r0, [r7, #12] 8007d7a: f001 f870 bl 8008e5e /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8007d7e: 68f8 ldr r0, [r7, #12] 8007d80: f000 fc6e bl 8008660 8007d84: e01d b.n 8007dc2 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007d86: 68fb ldr r3, [r7, #12] 8007d88: 681b ldr r3, [r3, #0] 8007d8a: 2210 movs r2, #16 8007d8c: 61da str r2, [r3, #28] if (hi2c->XferCount == 0U) 8007d8e: e096 b.n 8007ebe } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007d90: 68fb ldr r3, [r7, #12] 8007d92: 681b ldr r3, [r3, #0] 8007d94: 2210 movs r2, #16 8007d96: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8007d98: 68fb ldr r3, [r7, #12] 8007d9a: 6c5b ldr r3, [r3, #68] @ 0x44 8007d9c: f043 0204 orr.w r2, r3, #4 8007da0: 68fb ldr r3, [r7, #12] 8007da2: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8007da4: 697b ldr r3, [r7, #20] 8007da6: 2b00 cmp r3, #0 8007da8: d004 beq.n 8007db4 8007daa: 697b ldr r3, [r7, #20] 8007dac: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8007db0: f040 8085 bne.w 8007ebe { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8007db4: 68fb ldr r3, [r7, #12] 8007db6: 6c5b ldr r3, [r3, #68] @ 0x44 8007db8: 4619 mov r1, r3 8007dba: 68f8 ldr r0, [r7, #12] 8007dbc: f000 ff38 bl 8008c30 if (hi2c->XferCount == 0U) 8007dc0: e07d b.n 8007ebe 8007dc2: e07c b.n 8007ebe } } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 8007dc4: 693b ldr r3, [r7, #16] 8007dc6: 089b lsrs r3, r3, #2 8007dc8: f003 0301 and.w r3, r3, #1 8007dcc: 2b00 cmp r3, #0 8007dce: d030 beq.n 8007e32 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) 8007dd0: 687b ldr r3, [r7, #4] 8007dd2: 089b lsrs r3, r3, #2 8007dd4: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 8007dd8: 2b00 cmp r3, #0 8007dda: d02a beq.n 8007e32 { if (hi2c->XferCount > 0U) 8007ddc: 68fb ldr r3, [r7, #12] 8007dde: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007de0: b29b uxth r3, r3 8007de2: 2b00 cmp r3, #0 8007de4: d018 beq.n 8007e18 { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8007de6: 68fb ldr r3, [r7, #12] 8007de8: 681b ldr r3, [r3, #0] 8007dea: 6a5a ldr r2, [r3, #36] @ 0x24 8007dec: 68fb ldr r3, [r7, #12] 8007dee: 6a5b ldr r3, [r3, #36] @ 0x24 8007df0: b2d2 uxtb r2, r2 8007df2: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8007df4: 68fb ldr r3, [r7, #12] 8007df6: 6a5b ldr r3, [r3, #36] @ 0x24 8007df8: 1c5a adds r2, r3, #1 8007dfa: 68fb ldr r3, [r7, #12] 8007dfc: 625a str r2, [r3, #36] @ 0x24 hi2c->XferSize--; 8007dfe: 68fb ldr r3, [r7, #12] 8007e00: 8d1b ldrh r3, [r3, #40] @ 0x28 8007e02: 3b01 subs r3, #1 8007e04: b29a uxth r2, r3 8007e06: 68fb ldr r3, [r7, #12] 8007e08: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8007e0a: 68fb ldr r3, [r7, #12] 8007e0c: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007e0e: b29b uxth r3, r3 8007e10: 3b01 subs r3, #1 8007e12: b29a uxth r2, r3 8007e14: 68fb ldr r3, [r7, #12] 8007e16: 855a strh r2, [r3, #42] @ 0x2a } if ((hi2c->XferCount == 0U) && \ 8007e18: 68fb ldr r3, [r7, #12] 8007e1a: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007e1c: b29b uxth r3, r3 8007e1e: 2b00 cmp r3, #0 8007e20: d14f bne.n 8007ec2 8007e22: 697b ldr r3, [r7, #20] 8007e24: f513 3f80 cmn.w r3, #65536 @ 0x10000 8007e28: d04b beq.n 8007ec2 (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8007e2a: 68f8 ldr r0, [r7, #12] 8007e2c: f000 fc18 bl 8008660 if ((hi2c->XferCount == 0U) && \ 8007e30: e047 b.n 8007ec2 } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 8007e32: 693b ldr r3, [r7, #16] 8007e34: 08db lsrs r3, r3, #3 8007e36: f003 0301 and.w r3, r3, #1 8007e3a: 2b00 cmp r3, #0 8007e3c: d00a beq.n 8007e54 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 8007e3e: 687b ldr r3, [r7, #4] 8007e40: 08db lsrs r3, r3, #3 8007e42: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 8007e46: 2b00 cmp r3, #0 8007e48: d004 beq.n 8007e54 { I2C_ITAddrCplt(hi2c, tmpITFlags); 8007e4a: 6939 ldr r1, [r7, #16] 8007e4c: 68f8 ldr r0, [r7, #12] 8007e4e: f000 fb46 bl 80084de 8007e52: e037 b.n 8007ec4 } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 8007e54: 693b ldr r3, [r7, #16] 8007e56: 085b lsrs r3, r3, #1 8007e58: f003 0301 and.w r3, r3, #1 8007e5c: 2b00 cmp r3, #0 8007e5e: d031 beq.n 8007ec4 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 8007e60: 687b ldr r3, [r7, #4] 8007e62: 085b lsrs r3, r3, #1 8007e64: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 8007e68: 2b00 cmp r3, #0 8007e6a: d02b beq.n 8007ec4 { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) 8007e6c: 68fb ldr r3, [r7, #12] 8007e6e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007e70: b29b uxth r3, r3 8007e72: 2b00 cmp r3, #0 8007e74: d018 beq.n 8007ea8 { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 8007e76: 68fb ldr r3, [r7, #12] 8007e78: 6a5b ldr r3, [r3, #36] @ 0x24 8007e7a: 781a ldrb r2, [r3, #0] 8007e7c: 68fb ldr r3, [r7, #12] 8007e7e: 681b ldr r3, [r3, #0] 8007e80: 629a str r2, [r3, #40] @ 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8007e82: 68fb ldr r3, [r7, #12] 8007e84: 6a5b ldr r3, [r3, #36] @ 0x24 8007e86: 1c5a adds r2, r3, #1 8007e88: 68fb ldr r3, [r7, #12] 8007e8a: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount--; 8007e8c: 68fb ldr r3, [r7, #12] 8007e8e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007e90: b29b uxth r3, r3 8007e92: 3b01 subs r3, #1 8007e94: b29a uxth r2, r3 8007e96: 68fb ldr r3, [r7, #12] 8007e98: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize--; 8007e9a: 68fb ldr r3, [r7, #12] 8007e9c: 8d1b ldrh r3, [r3, #40] @ 0x28 8007e9e: 3b01 subs r3, #1 8007ea0: b29a uxth r2, r3 8007ea2: 68fb ldr r3, [r7, #12] 8007ea4: 851a strh r2, [r3, #40] @ 0x28 8007ea6: e00d b.n 8007ec4 } else { if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) 8007ea8: 697b ldr r3, [r7, #20] 8007eaa: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8007eae: d002 beq.n 8007eb6 8007eb0: 697b ldr r3, [r7, #20] 8007eb2: 2b00 cmp r3, #0 8007eb4: d106 bne.n 8007ec4 { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8007eb6: 68f8 ldr r0, [r7, #12] 8007eb8: f000 fbd2 bl 8008660 8007ebc: e002 b.n 8007ec4 if (hi2c->XferCount == 0U) 8007ebe: bf00 nop 8007ec0: e000 b.n 8007ec4 if ((hi2c->XferCount == 0U) && \ 8007ec2: bf00 nop { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8007ec4: 68fb ldr r3, [r7, #12] 8007ec6: 2200 movs r2, #0 8007ec8: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8007ecc: 2300 movs r3, #0 } 8007ece: 4618 mov r0, r3 8007ed0: 3718 adds r7, #24 8007ed2: 46bd mov sp, r7 8007ed4: bd80 pop {r7, pc} 08007ed6 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8007ed6: b580 push {r7, lr} 8007ed8: b088 sub sp, #32 8007eda: af02 add r7, sp, #8 8007edc: 60f8 str r0, [r7, #12] 8007ede: 60b9 str r1, [r7, #8] 8007ee0: 607a str r2, [r7, #4] uint16_t devaddress; uint32_t xfermode; /* Process Locked */ __HAL_LOCK(hi2c); 8007ee2: 68fb ldr r3, [r7, #12] 8007ee4: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8007ee8: 2b01 cmp r3, #1 8007eea: d101 bne.n 8007ef0 8007eec: 2302 movs r3, #2 8007eee: e0e1 b.n 80080b4 8007ef0: 68fb ldr r3, [r7, #12] 8007ef2: 2201 movs r2, #1 8007ef4: f883 2040 strb.w r2, [r3, #64] @ 0x40 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8007ef8: 68bb ldr r3, [r7, #8] 8007efa: 091b lsrs r3, r3, #4 8007efc: f003 0301 and.w r3, r3, #1 8007f00: 2b00 cmp r3, #0 8007f02: d017 beq.n 8007f34 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8007f04: 687b ldr r3, [r7, #4] 8007f06: 091b lsrs r3, r3, #4 8007f08: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8007f0c: 2b00 cmp r3, #0 8007f0e: d011 beq.n 8007f34 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8007f10: 68fb ldr r3, [r7, #12] 8007f12: 681b ldr r3, [r3, #0] 8007f14: 2210 movs r2, #16 8007f16: 61da str r2, [r3, #28] /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8007f18: 68fb ldr r3, [r7, #12] 8007f1a: 6c5b ldr r3, [r3, #68] @ 0x44 8007f1c: f043 0204 orr.w r2, r3, #4 8007f20: 68fb ldr r3, [r7, #12] 8007f22: 645a str r2, [r3, #68] @ 0x44 /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8007f24: 2120 movs r1, #32 8007f26: 68f8 ldr r0, [r7, #12] 8007f28: f001 f8ba bl 80090a0 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8007f2c: 68f8 ldr r0, [r7, #12] 8007f2e: f000 ff96 bl 8008e5e 8007f32: e0ba b.n 80080aa } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8007f34: 68bb ldr r3, [r7, #8] 8007f36: 09db lsrs r3, r3, #7 8007f38: f003 0301 and.w r3, r3, #1 8007f3c: 2b00 cmp r3, #0 8007f3e: d072 beq.n 8008026 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8007f40: 687b ldr r3, [r7, #4] 8007f42: 099b lsrs r3, r3, #6 8007f44: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8007f48: 2b00 cmp r3, #0 8007f4a: d06c beq.n 8008026 { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); 8007f4c: 68fb ldr r3, [r7, #12] 8007f4e: 681b ldr r3, [r3, #0] 8007f50: 681a ldr r2, [r3, #0] 8007f52: 68fb ldr r3, [r7, #12] 8007f54: 681b ldr r3, [r3, #0] 8007f56: f022 0240 bic.w r2, r2, #64 @ 0x40 8007f5a: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8007f5c: 68fb ldr r3, [r7, #12] 8007f5e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007f60: b29b uxth r3, r3 8007f62: 2b00 cmp r3, #0 8007f64: d04e beq.n 8008004 { /* Recover Slave address */ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); 8007f66: 68fb ldr r3, [r7, #12] 8007f68: 681b ldr r3, [r3, #0] 8007f6a: 685b ldr r3, [r3, #4] 8007f6c: b29b uxth r3, r3 8007f6e: f3c3 0309 ubfx r3, r3, #0, #10 8007f72: 827b strh r3, [r7, #18] /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8007f74: 68fb ldr r3, [r7, #12] 8007f76: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007f78: b29b uxth r3, r3 8007f7a: 2bff cmp r3, #255 @ 0xff 8007f7c: d906 bls.n 8007f8c { hi2c->XferSize = MAX_NBYTE_SIZE; 8007f7e: 68fb ldr r3, [r7, #12] 8007f80: 22ff movs r2, #255 @ 0xff 8007f82: 851a strh r2, [r3, #40] @ 0x28 xfermode = I2C_RELOAD_MODE; 8007f84: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8007f88: 617b str r3, [r7, #20] 8007f8a: e010 b.n 8007fae } else { hi2c->XferSize = hi2c->XferCount; 8007f8c: 68fb ldr r3, [r7, #12] 8007f8e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007f90: b29a uxth r2, r3 8007f92: 68fb ldr r3, [r7, #12] 8007f94: 851a strh r2, [r3, #40] @ 0x28 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 8007f96: 68fb ldr r3, [r7, #12] 8007f98: 6adb ldr r3, [r3, #44] @ 0x2c 8007f9a: f513 3f80 cmn.w r3, #65536 @ 0x10000 8007f9e: d003 beq.n 8007fa8 { xfermode = hi2c->XferOptions; 8007fa0: 68fb ldr r3, [r7, #12] 8007fa2: 6adb ldr r3, [r3, #44] @ 0x2c 8007fa4: 617b str r3, [r7, #20] 8007fa6: e002 b.n 8007fae } else { xfermode = I2C_AUTOEND_MODE; 8007fa8: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8007fac: 617b str r3, [r7, #20] } } /* Set the new XferSize in Nbytes register */ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); 8007fae: 68fb ldr r3, [r7, #12] 8007fb0: 8d1b ldrh r3, [r3, #40] @ 0x28 8007fb2: b2da uxtb r2, r3 8007fb4: 8a79 ldrh r1, [r7, #18] 8007fb6: 2300 movs r3, #0 8007fb8: 9300 str r3, [sp, #0] 8007fba: 697b ldr r3, [r7, #20] 8007fbc: 68f8 ldr r0, [r7, #12] 8007fbe: f001 f83d bl 800903c /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8007fc2: 68fb ldr r3, [r7, #12] 8007fc4: 8d5b ldrh r3, [r3, #42] @ 0x2a 8007fc6: b29a uxth r2, r3 8007fc8: 68fb ldr r3, [r7, #12] 8007fca: 8d1b ldrh r3, [r3, #40] @ 0x28 8007fcc: 1ad3 subs r3, r2, r3 8007fce: b29a uxth r2, r3 8007fd0: 68fb ldr r3, [r7, #12] 8007fd2: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8007fd4: 68fb ldr r3, [r7, #12] 8007fd6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8007fda: b2db uxtb r3, r3 8007fdc: 2b22 cmp r3, #34 @ 0x22 8007fde: d108 bne.n 8007ff2 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8007fe0: 68fb ldr r3, [r7, #12] 8007fe2: 681b ldr r3, [r3, #0] 8007fe4: 681a ldr r2, [r3, #0] 8007fe6: 68fb ldr r3, [r7, #12] 8007fe8: 681b ldr r3, [r3, #0] 8007fea: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8007fee: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8007ff0: e05b b.n 80080aa } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 8007ff2: 68fb ldr r3, [r7, #12] 8007ff4: 681b ldr r3, [r3, #0] 8007ff6: 681a ldr r2, [r3, #0] 8007ff8: 68fb ldr r3, [r7, #12] 8007ffa: 681b ldr r3, [r3, #0] 8007ffc: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8008000: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8008002: e052 b.n 80080aa } } else { /* Call TxCpltCallback() if no stop mode is set */ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 8008004: 68fb ldr r3, [r7, #12] 8008006: 681b ldr r3, [r3, #0] 8008008: 685b ldr r3, [r3, #4] 800800a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800800e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8008012: d003 beq.n 800801c { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); 8008014: 68f8 ldr r0, [r7, #12] 8008016: f000 fae6 bl 80085e6 if (hi2c->XferCount != 0U) 800801a: e046 b.n 80080aa } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 800801c: 2140 movs r1, #64 @ 0x40 800801e: 68f8 ldr r0, [r7, #12] 8008020: f000 fe06 bl 8008c30 if (hi2c->XferCount != 0U) 8008024: e041 b.n 80080aa } } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8008026: 68bb ldr r3, [r7, #8] 8008028: 099b lsrs r3, r3, #6 800802a: f003 0301 and.w r3, r3, #1 800802e: 2b00 cmp r3, #0 8008030: d029 beq.n 8008086 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8008032: 687b ldr r3, [r7, #4] 8008034: 099b lsrs r3, r3, #6 8008036: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 800803a: 2b00 cmp r3, #0 800803c: d023 beq.n 8008086 { if (hi2c->XferCount == 0U) 800803e: 68fb ldr r3, [r7, #12] 8008040: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008042: b29b uxth r3, r3 8008044: 2b00 cmp r3, #0 8008046: d119 bne.n 800807c { if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 8008048: 68fb ldr r3, [r7, #12] 800804a: 681b ldr r3, [r3, #0] 800804c: 685b ldr r3, [r3, #4] 800804e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8008052: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8008056: d027 beq.n 80080a8 { /* Generate a stop condition in case of no transfer option */ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) 8008058: 68fb ldr r3, [r7, #12] 800805a: 6adb ldr r3, [r3, #44] @ 0x2c 800805c: f513 3f80 cmn.w r3, #65536 @ 0x10000 8008060: d108 bne.n 8008074 { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; 8008062: 68fb ldr r3, [r7, #12] 8008064: 681b ldr r3, [r3, #0] 8008066: 685a ldr r2, [r3, #4] 8008068: 68fb ldr r3, [r7, #12] 800806a: 681b ldr r3, [r3, #0] 800806c: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8008070: 605a str r2, [r3, #4] if (hi2c->XferCount == 0U) 8008072: e019 b.n 80080a8 } else { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); 8008074: 68f8 ldr r0, [r7, #12] 8008076: f000 fab6 bl 80085e6 if (hi2c->XferCount == 0U) 800807a: e015 b.n 80080a8 } else { /* Wrong size Status regarding TC flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 800807c: 2140 movs r1, #64 @ 0x40 800807e: 68f8 ldr r0, [r7, #12] 8008080: f000 fdd6 bl 8008c30 if (hi2c->XferCount == 0U) 8008084: e010 b.n 80080a8 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8008086: 68bb ldr r3, [r7, #8] 8008088: 095b lsrs r3, r3, #5 800808a: f003 0301 and.w r3, r3, #1 800808e: 2b00 cmp r3, #0 8008090: d00b beq.n 80080aa (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8008092: 687b ldr r3, [r7, #4] 8008094: 095b lsrs r3, r3, #5 8008096: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 800809a: 2b00 cmp r3, #0 800809c: d005 beq.n 80080aa { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); 800809e: 68b9 ldr r1, [r7, #8] 80080a0: 68f8 ldr r0, [r7, #12] 80080a2: f000 fb3b bl 800871c 80080a6: e000 b.n 80080aa if (hi2c->XferCount == 0U) 80080a8: bf00 nop { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80080aa: 68fb ldr r3, [r7, #12] 80080ac: 2200 movs r2, #0 80080ae: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 80080b2: 2300 movs r3, #0 } 80080b4: 4618 mov r0, r3 80080b6: 3718 adds r7, #24 80080b8: 46bd mov sp, r7 80080ba: bd80 pop {r7, pc} 080080bc : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 80080bc: b580 push {r7, lr} 80080be: b088 sub sp, #32 80080c0: af02 add r7, sp, #8 80080c2: 60f8 str r0, [r7, #12] 80080c4: 60b9 str r1, [r7, #8] 80080c6: 607a str r2, [r7, #4] uint32_t direction = I2C_GENERATE_START_WRITE; 80080c8: 4b92 ldr r3, [pc, #584] @ (8008314 ) 80080ca: 617b str r3, [r7, #20] /* Process Locked */ __HAL_LOCK(hi2c); 80080cc: 68fb ldr r3, [r7, #12] 80080ce: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 80080d2: 2b01 cmp r3, #1 80080d4: d101 bne.n 80080da 80080d6: 2302 movs r3, #2 80080d8: e118 b.n 800830c 80080da: 68fb ldr r3, [r7, #12] 80080dc: 2201 movs r2, #1 80080de: f883 2040 strb.w r2, [r3, #64] @ 0x40 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 80080e2: 68bb ldr r3, [r7, #8] 80080e4: 091b lsrs r3, r3, #4 80080e6: f003 0301 and.w r3, r3, #1 80080ea: 2b00 cmp r3, #0 80080ec: d017 beq.n 800811e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 80080ee: 687b ldr r3, [r7, #4] 80080f0: 091b lsrs r3, r3, #4 80080f2: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 80080f6: 2b00 cmp r3, #0 80080f8: d011 beq.n 800811e { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80080fa: 68fb ldr r3, [r7, #12] 80080fc: 681b ldr r3, [r3, #0] 80080fe: 2210 movs r2, #16 8008100: 61da str r2, [r3, #28] /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008102: 68fb ldr r3, [r7, #12] 8008104: 6c5b ldr r3, [r3, #68] @ 0x44 8008106: f043 0204 orr.w r2, r3, #4 800810a: 68fb ldr r3, [r7, #12] 800810c: 645a str r2, [r3, #68] @ 0x44 /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 800810e: 2120 movs r1, #32 8008110: 68f8 ldr r0, [r7, #12] 8008112: f000 ffc5 bl 80090a0 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8008116: 68f8 ldr r0, [r7, #12] 8008118: f000 fea1 bl 8008e5e 800811c: e0f1 b.n 8008302 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ 800811e: 68bb ldr r3, [r7, #8] 8008120: 085b lsrs r3, r3, #1 8008122: f003 0301 and.w r3, r3, #1 8008126: 2b00 cmp r3, #0 8008128: d00f beq.n 800814a (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 800812a: 687b ldr r3, [r7, #4] 800812c: 085b lsrs r3, r3, #1 800812e: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ 8008132: 2b00 cmp r3, #0 8008134: d009 beq.n 800814a { /* Write LSB part of Memory Address */ hi2c->Instance->TXDR = hi2c->Memaddress; 8008136: 68fb ldr r3, [r7, #12] 8008138: 681b ldr r3, [r3, #0] 800813a: 68fa ldr r2, [r7, #12] 800813c: 6d12 ldr r2, [r2, #80] @ 0x50 800813e: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 8008140: 68fb ldr r3, [r7, #12] 8008142: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8008146: 651a str r2, [r3, #80] @ 0x50 8008148: e0db b.n 8008302 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 800814a: 68bb ldr r3, [r7, #8] 800814c: 09db lsrs r3, r3, #7 800814e: f003 0301 and.w r3, r3, #1 8008152: 2b00 cmp r3, #0 8008154: d060 beq.n 8008218 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8008156: 687b ldr r3, [r7, #4] 8008158: 099b lsrs r3, r3, #6 800815a: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 800815e: 2b00 cmp r3, #0 8008160: d05a beq.n 8008218 { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8008162: 2101 movs r1, #1 8008164: 68f8 ldr r0, [r7, #12] 8008166: f001 f81f bl 80091a8 /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); 800816a: 2110 movs r1, #16 800816c: 68f8 ldr r0, [r7, #12] 800816e: f000 ff97 bl 80090a0 if (hi2c->XferCount != 0U) 8008172: 68fb ldr r3, [r7, #12] 8008174: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008176: b29b uxth r3, r3 8008178: 2b00 cmp r3, #0 800817a: d048 beq.n 800820e { /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 800817c: 68fb ldr r3, [r7, #12] 800817e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008180: b29b uxth r3, r3 8008182: 2bff cmp r3, #255 @ 0xff 8008184: d910 bls.n 80081a8 { hi2c->XferSize = MAX_NBYTE_SIZE; 8008186: 68fb ldr r3, [r7, #12] 8008188: 22ff movs r2, #255 @ 0xff 800818a: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 800818c: 68fb ldr r3, [r7, #12] 800818e: 6cdb ldr r3, [r3, #76] @ 0x4c 8008190: b299 uxth r1, r3 8008192: 68fb ldr r3, [r7, #12] 8008194: 8d1b ldrh r3, [r3, #40] @ 0x28 8008196: b2da uxtb r2, r3 8008198: 2300 movs r3, #0 800819a: 9300 str r3, [sp, #0] 800819c: f04f 7380 mov.w r3, #16777216 @ 0x1000000 80081a0: 68f8 ldr r0, [r7, #12] 80081a2: f000 ff4b bl 800903c 80081a6: e011 b.n 80081cc I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 80081a8: 68fb ldr r3, [r7, #12] 80081aa: 8d5b ldrh r3, [r3, #42] @ 0x2a 80081ac: b29a uxth r2, r3 80081ae: 68fb ldr r3, [r7, #12] 80081b0: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 80081b2: 68fb ldr r3, [r7, #12] 80081b4: 6cdb ldr r3, [r3, #76] @ 0x4c 80081b6: b299 uxth r1, r3 80081b8: 68fb ldr r3, [r7, #12] 80081ba: 8d1b ldrh r3, [r3, #40] @ 0x28 80081bc: b2da uxtb r2, r3 80081be: 2300 movs r3, #0 80081c0: 9300 str r3, [sp, #0] 80081c2: f04f 7300 mov.w r3, #33554432 @ 0x2000000 80081c6: 68f8 ldr r0, [r7, #12] 80081c8: f000 ff38 bl 800903c I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 80081cc: 68fb ldr r3, [r7, #12] 80081ce: 8d5b ldrh r3, [r3, #42] @ 0x2a 80081d0: b29a uxth r2, r3 80081d2: 68fb ldr r3, [r7, #12] 80081d4: 8d1b ldrh r3, [r3, #40] @ 0x28 80081d6: 1ad3 subs r3, r2, r3 80081d8: b29a uxth r2, r3 80081da: 68fb ldr r3, [r7, #12] 80081dc: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 80081de: 68fb ldr r3, [r7, #12] 80081e0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80081e4: b2db uxtb r3, r3 80081e6: 2b22 cmp r3, #34 @ 0x22 80081e8: d108 bne.n 80081fc { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 80081ea: 68fb ldr r3, [r7, #12] 80081ec: 681b ldr r3, [r3, #0] 80081ee: 681a ldr r2, [r3, #0] 80081f0: 68fb ldr r3, [r7, #12] 80081f2: 681b ldr r3, [r3, #0] 80081f4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80081f8: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 80081fa: e082 b.n 8008302 } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 80081fc: 68fb ldr r3, [r7, #12] 80081fe: 681b ldr r3, [r3, #0] 8008200: 681a ldr r2, [r3, #0] 8008202: 68fb ldr r3, [r7, #12] 8008204: 681b ldr r3, [r3, #0] 8008206: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800820a: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 800820c: e079 b.n 8008302 } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 800820e: 2140 movs r1, #64 @ 0x40 8008210: 68f8 ldr r0, [r7, #12] 8008212: f000 fd0d bl 8008c30 if (hi2c->XferCount != 0U) 8008216: e074 b.n 8008302 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8008218: 68bb ldr r3, [r7, #8] 800821a: 099b lsrs r3, r3, #6 800821c: f003 0301 and.w r3, r3, #1 8008220: 2b00 cmp r3, #0 8008222: d05e beq.n 80082e2 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8008224: 687b ldr r3, [r7, #4] 8008226: 099b lsrs r3, r3, #6 8008228: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 800822c: 2b00 cmp r3, #0 800822e: d058 beq.n 80082e2 { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8008230: 2101 movs r1, #1 8008232: 68f8 ldr r0, [r7, #12] 8008234: f000 ffb8 bl 80091a8 /* Enable only Error and NACK interrupt for data transfer */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); 8008238: 2110 movs r1, #16 800823a: 68f8 ldr r0, [r7, #12] 800823c: f000 ff30 bl 80090a0 if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8008240: 68fb ldr r3, [r7, #12] 8008242: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008246: b2db uxtb r3, r3 8008248: 2b22 cmp r3, #34 @ 0x22 800824a: d101 bne.n 8008250 { direction = I2C_GENERATE_START_READ; 800824c: 4b32 ldr r3, [pc, #200] @ (8008318 ) 800824e: 617b str r3, [r7, #20] } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8008250: 68fb ldr r3, [r7, #12] 8008252: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008254: b29b uxth r3, r3 8008256: 2bff cmp r3, #255 @ 0xff 8008258: d910 bls.n 800827c { hi2c->XferSize = MAX_NBYTE_SIZE; 800825a: 68fb ldr r3, [r7, #12] 800825c: 22ff movs r2, #255 @ 0xff 800825e: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8008260: 68fb ldr r3, [r7, #12] 8008262: 6cdb ldr r3, [r3, #76] @ 0x4c 8008264: b299 uxth r1, r3 8008266: 68fb ldr r3, [r7, #12] 8008268: 8d1b ldrh r3, [r3, #40] @ 0x28 800826a: b2da uxtb r2, r3 800826c: 697b ldr r3, [r7, #20] 800826e: 9300 str r3, [sp, #0] 8008270: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8008274: 68f8 ldr r0, [r7, #12] 8008276: f000 fee1 bl 800903c 800827a: e011 b.n 80082a0 I2C_RELOAD_MODE, direction); } else { hi2c->XferSize = hi2c->XferCount; 800827c: 68fb ldr r3, [r7, #12] 800827e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008280: b29a uxth r2, r3 8008282: 68fb ldr r3, [r7, #12] 8008284: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8008286: 68fb ldr r3, [r7, #12] 8008288: 6cdb ldr r3, [r3, #76] @ 0x4c 800828a: b299 uxth r1, r3 800828c: 68fb ldr r3, [r7, #12] 800828e: 8d1b ldrh r3, [r3, #40] @ 0x28 8008290: b2da uxtb r2, r3 8008292: 697b ldr r3, [r7, #20] 8008294: 9300 str r3, [sp, #0] 8008296: f04f 7300 mov.w r3, #33554432 @ 0x2000000 800829a: 68f8 ldr r0, [r7, #12] 800829c: f000 fece bl 800903c I2C_AUTOEND_MODE, direction); } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 80082a0: 68fb ldr r3, [r7, #12] 80082a2: 8d5b ldrh r3, [r3, #42] @ 0x2a 80082a4: b29a uxth r2, r3 80082a6: 68fb ldr r3, [r7, #12] 80082a8: 8d1b ldrh r3, [r3, #40] @ 0x28 80082aa: 1ad3 subs r3, r2, r3 80082ac: b29a uxth r2, r3 80082ae: 68fb ldr r3, [r7, #12] 80082b0: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 80082b2: 68fb ldr r3, [r7, #12] 80082b4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80082b8: b2db uxtb r3, r3 80082ba: 2b22 cmp r3, #34 @ 0x22 80082bc: d108 bne.n 80082d0 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 80082be: 68fb ldr r3, [r7, #12] 80082c0: 681b ldr r3, [r3, #0] 80082c2: 681a ldr r2, [r3, #0] 80082c4: 68fb ldr r3, [r7, #12] 80082c6: 681b ldr r3, [r3, #0] 80082c8: f442 4200 orr.w r2, r2, #32768 @ 0x8000 80082cc: 601a str r2, [r3, #0] if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 80082ce: e018 b.n 8008302 } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 80082d0: 68fb ldr r3, [r7, #12] 80082d2: 681b ldr r3, [r3, #0] 80082d4: 681a ldr r2, [r3, #0] 80082d6: 68fb ldr r3, [r7, #12] 80082d8: 681b ldr r3, [r3, #0] 80082da: f442 4280 orr.w r2, r2, #16384 @ 0x4000 80082de: 601a str r2, [r3, #0] if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 80082e0: e00f b.n 8008302 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 80082e2: 68bb ldr r3, [r7, #8] 80082e4: 095b lsrs r3, r3, #5 80082e6: f003 0301 and.w r3, r3, #1 80082ea: 2b00 cmp r3, #0 80082ec: d009 beq.n 8008302 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 80082ee: 687b ldr r3, [r7, #4] 80082f0: 095b lsrs r3, r3, #5 80082f2: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 80082f6: 2b00 cmp r3, #0 80082f8: d003 beq.n 8008302 { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); 80082fa: 68b9 ldr r1, [r7, #8] 80082fc: 68f8 ldr r0, [r7, #12] 80082fe: f000 fa0d bl 800871c { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008302: 68fb ldr r3, [r7, #12] 8008304: 2200 movs r2, #0 8008306: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 800830a: 2300 movs r3, #0 } 800830c: 4618 mov r0, r3 800830e: 3718 adds r7, #24 8008310: 46bd mov sp, r7 8008312: bd80 pop {r7, pc} 8008314: 80002000 .word 0x80002000 8008318: 80002400 .word 0x80002400 0800831c : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 800831c: b580 push {r7, lr} 800831e: b088 sub sp, #32 8008320: af00 add r7, sp, #0 8008322: 60f8 str r0, [r7, #12] 8008324: 60b9 str r1, [r7, #8] 8008326: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 8008328: 68fb ldr r3, [r7, #12] 800832a: 6adb ldr r3, [r3, #44] @ 0x2c 800832c: 61bb str r3, [r7, #24] uint32_t treatdmanack = 0U; 800832e: 2300 movs r3, #0 8008330: 61fb str r3, [r7, #28] HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); 8008332: 68fb ldr r3, [r7, #12] 8008334: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8008338: 2b01 cmp r3, #1 800833a: d101 bne.n 8008340 800833c: 2302 movs r3, #2 800833e: e0ca b.n 80084d6 8008340: 68fb ldr r3, [r7, #12] 8008342: 2201 movs r2, #1 8008344: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8008348: 68bb ldr r3, [r7, #8] 800834a: 095b lsrs r3, r3, #5 800834c: f003 0301 and.w r3, r3, #1 8008350: 2b00 cmp r3, #0 8008352: d00a beq.n 800836a (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8008354: 687b ldr r3, [r7, #4] 8008356: 095b lsrs r3, r3, #5 8008358: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 800835c: 2b00 cmp r3, #0 800835e: d004 beq.n 800836a { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); 8008360: 68b9 ldr r1, [r7, #8] 8008362: 68f8 ldr r0, [r7, #12] 8008364: f000 faa4 bl 80088b0 8008368: e0b0 b.n 80084cc } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 800836a: 68bb ldr r3, [r7, #8] 800836c: 091b lsrs r3, r3, #4 800836e: f003 0301 and.w r3, r3, #1 8008372: 2b00 cmp r3, #0 8008374: f000 809a beq.w 80084ac (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8008378: 687b ldr r3, [r7, #4] 800837a: 091b lsrs r3, r3, #4 800837c: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8008380: 2b00 cmp r3, #0 8008382: f000 8093 beq.w 80084ac { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8008386: 687b ldr r3, [r7, #4] 8008388: 0b9b lsrs r3, r3, #14 800838a: f003 0301 and.w r3, r3, #1 800838e: 2b00 cmp r3, #0 8008390: d105 bne.n 800839e (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) 8008392: 687b ldr r3, [r7, #4] 8008394: 0bdb lsrs r3, r3, #15 8008396: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 800839a: 2b00 cmp r3, #0 800839c: d07f beq.n 800849e { /* Split check of hdmarx, for MISRA compliance */ if (hi2c->hdmarx != NULL) 800839e: 68fb ldr r3, [r7, #12] 80083a0: 6bdb ldr r3, [r3, #60] @ 0x3c 80083a2: 2b00 cmp r3, #0 80083a4: d00d beq.n 80083c2 { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) 80083a6: 687b ldr r3, [r7, #4] 80083a8: 0bdb lsrs r3, r3, #15 80083aa: f003 0301 and.w r3, r3, #1 80083ae: 2b00 cmp r3, #0 80083b0: d007 beq.n 80083c2 { if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) 80083b2: 68fb ldr r3, [r7, #12] 80083b4: 6bdb ldr r3, [r3, #60] @ 0x3c 80083b6: 681b ldr r3, [r3, #0] 80083b8: 685b ldr r3, [r3, #4] 80083ba: 2b00 cmp r3, #0 80083bc: d101 bne.n 80083c2 { treatdmanack = 1U; 80083be: 2301 movs r3, #1 80083c0: 61fb str r3, [r7, #28] } } } /* Split check of hdmatx, for MISRA compliance */ if (hi2c->hdmatx != NULL) 80083c2: 68fb ldr r3, [r7, #12] 80083c4: 6b9b ldr r3, [r3, #56] @ 0x38 80083c6: 2b00 cmp r3, #0 80083c8: d00d beq.n 80083e6 { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) 80083ca: 687b ldr r3, [r7, #4] 80083cc: 0b9b lsrs r3, r3, #14 80083ce: f003 0301 and.w r3, r3, #1 80083d2: 2b00 cmp r3, #0 80083d4: d007 beq.n 80083e6 { if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) 80083d6: 68fb ldr r3, [r7, #12] 80083d8: 6b9b ldr r3, [r3, #56] @ 0x38 80083da: 681b ldr r3, [r3, #0] 80083dc: 685b ldr r3, [r3, #4] 80083de: 2b00 cmp r3, #0 80083e0: d101 bne.n 80083e6 { treatdmanack = 1U; 80083e2: 2301 movs r3, #1 80083e4: 61fb str r3, [r7, #28] } } } if (treatdmanack == 1U) 80083e6: 69fb ldr r3, [r7, #28] 80083e8: 2b01 cmp r3, #1 80083ea: d128 bne.n 800843e { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 80083ec: 68fb ldr r3, [r7, #12] 80083ee: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80083f2: b2db uxtb r3, r3 80083f4: 2b28 cmp r3, #40 @ 0x28 80083f6: d108 bne.n 800840a 80083f8: 69bb ldr r3, [r7, #24] 80083fa: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80083fe: d104 bne.n 800840a /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); 8008400: 68b9 ldr r1, [r7, #8] 8008402: 68f8 ldr r0, [r7, #12] 8008404: f000 fbbe bl 8008b84 8008408: e048 b.n 800849c } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 800840a: 68fb ldr r3, [r7, #12] 800840c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008410: b2db uxtb r3, r3 8008412: 2b29 cmp r3, #41 @ 0x29 8008414: d10e bne.n 8008434 8008416: 69bb ldr r3, [r7, #24] 8008418: f513 3f80 cmn.w r3, #65536 @ 0x10000 800841c: d00a beq.n 8008434 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 800841e: 68fb ldr r3, [r7, #12] 8008420: 681b ldr r3, [r3, #0] 8008422: 2210 movs r2, #16 8008424: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8008426: 68f8 ldr r0, [r7, #12] 8008428: f000 fd19 bl 8008e5e /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 800842c: 68f8 ldr r0, [r7, #12] 800842e: f000 f917 bl 8008660 8008432: e033 b.n 800849c } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008434: 68fb ldr r3, [r7, #12] 8008436: 681b ldr r3, [r3, #0] 8008438: 2210 movs r2, #16 800843a: 61da str r2, [r3, #28] if (treatdmanack == 1U) 800843c: e034 b.n 80084a8 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 800843e: 68fb ldr r3, [r7, #12] 8008440: 681b ldr r3, [r3, #0] 8008442: 2210 movs r2, #16 8008444: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008446: 68fb ldr r3, [r7, #12] 8008448: 6c5b ldr r3, [r3, #68] @ 0x44 800844a: f043 0204 orr.w r2, r3, #4 800844e: 68fb ldr r3, [r7, #12] 8008450: 645a str r2, [r3, #68] @ 0x44 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ tmpstate = hi2c->State; 8008452: 68fb ldr r3, [r7, #12] 8008454: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008458: 75fb strb r3, [r7, #23] if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 800845a: 69bb ldr r3, [r7, #24] 800845c: 2b00 cmp r3, #0 800845e: d003 beq.n 8008468 8008460: 69bb ldr r3, [r7, #24] 8008462: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8008466: d11f bne.n 80084a8 { if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 8008468: 7dfb ldrb r3, [r7, #23] 800846a: 2b21 cmp r3, #33 @ 0x21 800846c: d002 beq.n 8008474 800846e: 7dfb ldrb r3, [r7, #23] 8008470: 2b29 cmp r3, #41 @ 0x29 8008472: d103 bne.n 800847c { hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 8008474: 68fb ldr r3, [r7, #12] 8008476: 2221 movs r2, #33 @ 0x21 8008478: 631a str r2, [r3, #48] @ 0x30 800847a: e008 b.n 800848e } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 800847c: 7dfb ldrb r3, [r7, #23] 800847e: 2b22 cmp r3, #34 @ 0x22 8008480: d002 beq.n 8008488 8008482: 7dfb ldrb r3, [r7, #23] 8008484: 2b2a cmp r3, #42 @ 0x2a 8008486: d102 bne.n 800848e { hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 8008488: 68fb ldr r3, [r7, #12] 800848a: 2222 movs r2, #34 @ 0x22 800848c: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 800848e: 68fb ldr r3, [r7, #12] 8008490: 6c5b ldr r3, [r3, #68] @ 0x44 8008492: 4619 mov r1, r3 8008494: 68f8 ldr r0, [r7, #12] 8008496: f000 fbcb bl 8008c30 if (treatdmanack == 1U) 800849a: e005 b.n 80084a8 800849c: e004 b.n 80084a8 } } else { /* Only Clear NACK Flag, no DMA treatment is pending */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 800849e: 68fb ldr r3, [r7, #12] 80084a0: 681b ldr r3, [r3, #0] 80084a2: 2210 movs r2, #16 80084a4: 61da str r2, [r3, #28] if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 80084a6: e011 b.n 80084cc if (treatdmanack == 1U) 80084a8: bf00 nop if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 80084aa: e00f b.n 80084cc } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ 80084ac: 68bb ldr r3, [r7, #8] 80084ae: 08db lsrs r3, r3, #3 80084b0: f003 0301 and.w r3, r3, #1 80084b4: 2b00 cmp r3, #0 80084b6: d009 beq.n 80084cc (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 80084b8: 687b ldr r3, [r7, #4] 80084ba: 08db lsrs r3, r3, #3 80084bc: f003 0301 and.w r3, r3, #1 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ 80084c0: 2b00 cmp r3, #0 80084c2: d003 beq.n 80084cc { I2C_ITAddrCplt(hi2c, ITFlags); 80084c4: 68b9 ldr r1, [r7, #8] 80084c6: 68f8 ldr r0, [r7, #12] 80084c8: f000 f809 bl 80084de { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80084cc: 68fb ldr r3, [r7, #12] 80084ce: 2200 movs r2, #0 80084d0: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 80084d4: 2300 movs r3, #0 } 80084d6: 4618 mov r0, r3 80084d8: 3720 adds r7, #32 80084da: 46bd mov sp, r7 80084dc: bd80 pop {r7, pc} 080084de : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 80084de: b580 push {r7, lr} 80084e0: b084 sub sp, #16 80084e2: af00 add r7, sp, #0 80084e4: 6078 str r0, [r7, #4] 80084e6: 6039 str r1, [r7, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 80084e8: 687b ldr r3, [r7, #4] 80084ea: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80084ee: b2db uxtb r3, r3 80084f0: f003 0328 and.w r3, r3, #40 @ 0x28 80084f4: 2b28 cmp r3, #40 @ 0x28 80084f6: d16a bne.n 80085ce { transferdirection = I2C_GET_DIR(hi2c); 80084f8: 687b ldr r3, [r7, #4] 80084fa: 681b ldr r3, [r3, #0] 80084fc: 699b ldr r3, [r3, #24] 80084fe: 0c1b lsrs r3, r3, #16 8008500: b2db uxtb r3, r3 8008502: f003 0301 and.w r3, r3, #1 8008506: 73fb strb r3, [r7, #15] slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); 8008508: 687b ldr r3, [r7, #4] 800850a: 681b ldr r3, [r3, #0] 800850c: 699b ldr r3, [r3, #24] 800850e: 0c1b lsrs r3, r3, #16 8008510: b29b uxth r3, r3 8008512: f003 03fe and.w r3, r3, #254 @ 0xfe 8008516: 81bb strh r3, [r7, #12] ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); 8008518: 687b ldr r3, [r7, #4] 800851a: 681b ldr r3, [r3, #0] 800851c: 689b ldr r3, [r3, #8] 800851e: b29b uxth r3, r3 8008520: f3c3 0309 ubfx r3, r3, #0, #10 8008524: 817b strh r3, [r7, #10] ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); 8008526: 687b ldr r3, [r7, #4] 8008528: 681b ldr r3, [r3, #0] 800852a: 68db ldr r3, [r3, #12] 800852c: b29b uxth r3, r3 800852e: f003 03fe and.w r3, r3, #254 @ 0xfe 8008532: 813b strh r3, [r7, #8] /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8008534: 687b ldr r3, [r7, #4] 8008536: 68db ldr r3, [r3, #12] 8008538: 2b02 cmp r3, #2 800853a: d138 bne.n 80085ae { if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) 800853c: 897b ldrh r3, [r7, #10] 800853e: 09db lsrs r3, r3, #7 8008540: b29a uxth r2, r3 8008542: 89bb ldrh r3, [r7, #12] 8008544: 4053 eors r3, r2 8008546: b29b uxth r3, r3 8008548: f003 0306 and.w r3, r3, #6 800854c: 2b00 cmp r3, #0 800854e: d11c bne.n 800858a { slaveaddrcode = ownadd1code; 8008550: 897b ldrh r3, [r7, #10] 8008552: 81bb strh r3, [r7, #12] hi2c->AddrEventCount++; 8008554: 687b ldr r3, [r7, #4] 8008556: 6c9b ldr r3, [r3, #72] @ 0x48 8008558: 1c5a adds r2, r3, #1 800855a: 687b ldr r3, [r7, #4] 800855c: 649a str r2, [r3, #72] @ 0x48 if (hi2c->AddrEventCount == 2U) 800855e: 687b ldr r3, [r7, #4] 8008560: 6c9b ldr r3, [r3, #72] @ 0x48 8008562: 2b02 cmp r3, #2 8008564: d13b bne.n 80085de { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; 8008566: 687b ldr r3, [r7, #4] 8008568: 2200 movs r2, #0 800856a: 649a str r2, [r3, #72] @ 0x48 /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 800856c: 687b ldr r3, [r7, #4] 800856e: 681b ldr r3, [r3, #0] 8008570: 2208 movs r2, #8 8008572: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008574: 687b ldr r3, [r7, #4] 8008576: 2200 movs r2, #0 8008578: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call Slave Addr callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); #else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 800857c: 89ba ldrh r2, [r7, #12] 800857e: 7bfb ldrb r3, [r7, #15] 8008580: 4619 mov r1, r3 8008582: 6878 ldr r0, [r7, #4] 8008584: f7ff fb75 bl 8007c72 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); } } 8008588: e029 b.n 80085de slaveaddrcode = ownadd2code; 800858a: 893b ldrh r3, [r7, #8] 800858c: 81bb strh r3, [r7, #12] I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 800858e: f44f 4100 mov.w r1, #32768 @ 0x8000 8008592: 6878 ldr r0, [r7, #4] 8008594: f000 fe08 bl 80091a8 __HAL_UNLOCK(hi2c); 8008598: 687b ldr r3, [r7, #4] 800859a: 2200 movs r2, #0 800859c: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 80085a0: 89ba ldrh r2, [r7, #12] 80085a2: 7bfb ldrb r3, [r7, #15] 80085a4: 4619 mov r1, r3 80085a6: 6878 ldr r0, [r7, #4] 80085a8: f7ff fb63 bl 8007c72 } 80085ac: e017 b.n 80085de I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 80085ae: f44f 4100 mov.w r1, #32768 @ 0x8000 80085b2: 6878 ldr r0, [r7, #4] 80085b4: f000 fdf8 bl 80091a8 __HAL_UNLOCK(hi2c); 80085b8: 687b ldr r3, [r7, #4] 80085ba: 2200 movs r2, #0 80085bc: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 80085c0: 89ba ldrh r2, [r7, #12] 80085c2: 7bfb ldrb r3, [r7, #15] 80085c4: 4619 mov r1, r3 80085c6: 6878 ldr r0, [r7, #4] 80085c8: f7ff fb53 bl 8007c72 } 80085cc: e007 b.n 80085de __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 80085ce: 687b ldr r3, [r7, #4] 80085d0: 681b ldr r3, [r3, #0] 80085d2: 2208 movs r2, #8 80085d4: 61da str r2, [r3, #28] __HAL_UNLOCK(hi2c); 80085d6: 687b ldr r3, [r7, #4] 80085d8: 2200 movs r2, #0 80085da: f883 2040 strb.w r2, [r3, #64] @ 0x40 } 80085de: bf00 nop 80085e0: 3710 adds r7, #16 80085e2: 46bd mov sp, r7 80085e4: bd80 pop {r7, pc} 080085e6 : * @brief I2C Master sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) { 80085e6: b580 push {r7, lr} 80085e8: b082 sub sp, #8 80085ea: af00 add r7, sp, #0 80085ec: 6078 str r0, [r7, #4] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 80085ee: 687b ldr r3, [r7, #4] 80085f0: 2200 movs r2, #0 80085f2: f883 2042 strb.w r2, [r3, #66] @ 0x42 /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 80085f6: 687b ldr r3, [r7, #4] 80085f8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80085fc: b2db uxtb r3, r3 80085fe: 2b21 cmp r3, #33 @ 0x21 8008600: d115 bne.n 800862e { hi2c->State = HAL_I2C_STATE_READY; 8008602: 687b ldr r3, [r7, #4] 8008604: 2220 movs r2, #32 8008606: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 800860a: 687b ldr r3, [r7, #4] 800860c: 2211 movs r2, #17 800860e: 631a str r2, [r3, #48] @ 0x30 hi2c->XferISR = NULL; 8008610: 687b ldr r3, [r7, #4] 8008612: 2200 movs r2, #0 8008614: 635a str r2, [r3, #52] @ 0x34 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8008616: 2101 movs r1, #1 8008618: 6878 ldr r0, [r7, #4] 800861a: f000 fdc5 bl 80091a8 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800861e: 687b ldr r3, [r7, #4] 8008620: 2200 movs r2, #0 8008622: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterTxCpltCallback(hi2c); #else HAL_I2C_MasterTxCpltCallback(hi2c); 8008626: 6878 ldr r0, [r7, #4] 8008628: f7ff fafb bl 8007c22 hi2c->MasterRxCpltCallback(hi2c); #else HAL_I2C_MasterRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 800862c: e014 b.n 8008658 hi2c->State = HAL_I2C_STATE_READY; 800862e: 687b ldr r3, [r7, #4] 8008630: 2220 movs r2, #32 8008632: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 8008636: 687b ldr r3, [r7, #4] 8008638: 2212 movs r2, #18 800863a: 631a str r2, [r3, #48] @ 0x30 hi2c->XferISR = NULL; 800863c: 687b ldr r3, [r7, #4] 800863e: 2200 movs r2, #0 8008640: 635a str r2, [r3, #52] @ 0x34 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 8008642: 2102 movs r1, #2 8008644: 6878 ldr r0, [r7, #4] 8008646: f000 fdaf bl 80091a8 __HAL_UNLOCK(hi2c); 800864a: 687b ldr r3, [r7, #4] 800864c: 2200 movs r2, #0 800864e: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MasterRxCpltCallback(hi2c); 8008652: 6878 ldr r0, [r7, #4] 8008654: f7ff faef bl 8007c36 } 8008658: bf00 nop 800865a: 3708 adds r7, #8 800865c: 46bd mov sp, r7 800865e: bd80 pop {r7, pc} 08008660 : * @brief I2C Slave sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { 8008660: b580 push {r7, lr} 8008662: b084 sub sp, #16 8008664: af00 add r7, sp, #0 8008666: 6078 str r0, [r7, #4] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 8008668: 687b ldr r3, [r7, #4] 800866a: 681b ldr r3, [r3, #0] 800866c: 681b ldr r3, [r3, #0] 800866e: 60fb str r3, [r7, #12] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 8008670: 687b ldr r3, [r7, #4] 8008672: 2200 movs r2, #0 8008674: f883 2042 strb.w r2, [r3, #66] @ 0x42 #if defined(HAL_DMA_MODULE_ENABLED) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 8008678: 68fb ldr r3, [r7, #12] 800867a: 0b9b lsrs r3, r3, #14 800867c: f003 0301 and.w r3, r3, #1 8008680: 2b00 cmp r3, #0 8008682: d008 beq.n 8008696 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8008684: 687b ldr r3, [r7, #4] 8008686: 681b ldr r3, [r3, #0] 8008688: 681a ldr r2, [r3, #0] 800868a: 687b ldr r3, [r7, #4] 800868c: 681b ldr r3, [r3, #0] 800868e: f422 4280 bic.w r2, r2, #16384 @ 0x4000 8008692: 601a str r2, [r3, #0] 8008694: e00d b.n 80086b2 } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 8008696: 68fb ldr r3, [r7, #12] 8008698: 0bdb lsrs r3, r3, #15 800869a: f003 0301 and.w r3, r3, #1 800869e: 2b00 cmp r3, #0 80086a0: d007 beq.n 80086b2 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 80086a2: 687b ldr r3, [r7, #4] 80086a4: 681b ldr r3, [r3, #0] 80086a6: 681a ldr r2, [r3, #0] 80086a8: 687b ldr r3, [r7, #4] 80086aa: 681b ldr r3, [r3, #0] 80086ac: f422 4200 bic.w r2, r2, #32768 @ 0x8000 80086b0: 601a str r2, [r3, #0] { /* Do nothing */ } #endif /* HAL_DMA_MODULE_ENABLED */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 80086b2: 687b ldr r3, [r7, #4] 80086b4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80086b8: b2db uxtb r3, r3 80086ba: 2b29 cmp r3, #41 @ 0x29 80086bc: d112 bne.n 80086e4 { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; 80086be: 687b ldr r3, [r7, #4] 80086c0: 2228 movs r2, #40 @ 0x28 80086c2: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 80086c6: 687b ldr r3, [r7, #4] 80086c8: 2221 movs r2, #33 @ 0x21 80086ca: 631a str r2, [r3, #48] @ 0x30 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 80086cc: 2101 movs r1, #1 80086ce: 6878 ldr r0, [r7, #4] 80086d0: f000 fd6a bl 80091a8 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80086d4: 687b ldr r3, [r7, #4] 80086d6: 2200 movs r2, #0 80086d8: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); 80086dc: 6878 ldr r0, [r7, #4] 80086de: f7ff fab4 bl 8007c4a } else { /* Nothing to do */ } } 80086e2: e017 b.n 8008714 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 80086e4: 687b ldr r3, [r7, #4] 80086e6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80086ea: b2db uxtb r3, r3 80086ec: 2b2a cmp r3, #42 @ 0x2a 80086ee: d111 bne.n 8008714 hi2c->State = HAL_I2C_STATE_LISTEN; 80086f0: 687b ldr r3, [r7, #4] 80086f2: 2228 movs r2, #40 @ 0x28 80086f4: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 80086f8: 687b ldr r3, [r7, #4] 80086fa: 2222 movs r2, #34 @ 0x22 80086fc: 631a str r2, [r3, #48] @ 0x30 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 80086fe: 2102 movs r1, #2 8008700: 6878 ldr r0, [r7, #4] 8008702: f000 fd51 bl 80091a8 __HAL_UNLOCK(hi2c); 8008706: 687b ldr r3, [r7, #4] 8008708: 2200 movs r2, #0 800870a: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_SlaveRxCpltCallback(hi2c); 800870e: 6878 ldr r0, [r7, #4] 8008710: f7ff faa5 bl 8007c5e } 8008714: bf00 nop 8008716: 3710 adds r7, #16 8008718: 46bd mov sp, r7 800871a: bd80 pop {r7, pc} 0800871c : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 800871c: b580 push {r7, lr} 800871e: b086 sub sp, #24 8008720: af00 add r7, sp, #0 8008722: 6078 str r0, [r7, #4] 8008724: 6039 str r1, [r7, #0] uint32_t tmperror; uint32_t tmpITFlags = ITFlags; 8008726: 683b ldr r3, [r7, #0] 8008728: 617b str r3, [r7, #20] __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 800872a: 687b ldr r3, [r7, #4] 800872c: 681b ldr r3, [r3, #0] 800872e: 2220 movs r2, #32 8008730: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8008732: 687b ldr r3, [r7, #4] 8008734: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008738: b2db uxtb r3, r3 800873a: 2b21 cmp r3, #33 @ 0x21 800873c: d107 bne.n 800874e { I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 800873e: 2101 movs r1, #1 8008740: 6878 ldr r0, [r7, #4] 8008742: f000 fd31 bl 80091a8 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 8008746: 687b ldr r3, [r7, #4] 8008748: 2211 movs r2, #17 800874a: 631a str r2, [r3, #48] @ 0x30 800874c: e00c b.n 8008768 } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 800874e: 687b ldr r3, [r7, #4] 8008750: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008754: b2db uxtb r3, r3 8008756: 2b22 cmp r3, #34 @ 0x22 8008758: d106 bne.n 8008768 { I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 800875a: 2102 movs r1, #2 800875c: 6878 ldr r0, [r7, #4] 800875e: f000 fd23 bl 80091a8 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 8008762: 687b ldr r3, [r7, #4] 8008764: 2212 movs r2, #18 8008766: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8008768: 687b ldr r3, [r7, #4] 800876a: 681b ldr r3, [r3, #0] 800876c: 6859 ldr r1, [r3, #4] 800876e: 687b ldr r3, [r7, #4] 8008770: 681a ldr r2, [r3, #0] 8008772: 4b4d ldr r3, [pc, #308] @ (80088a8 ) 8008774: 400b ands r3, r1 8008776: 6053 str r3, [r2, #4] /* Reset handle parameters */ hi2c->XferISR = NULL; 8008778: 687b ldr r3, [r7, #4] 800877a: 2200 movs r2, #0 800877c: 635a str r2, [r3, #52] @ 0x34 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 800877e: 687b ldr r3, [r7, #4] 8008780: 4a4a ldr r2, [pc, #296] @ (80088ac ) 8008782: 62da str r2, [r3, #44] @ 0x2c if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) 8008784: 697b ldr r3, [r7, #20] 8008786: 091b lsrs r3, r3, #4 8008788: f003 0301 and.w r3, r3, #1 800878c: 2b00 cmp r3, #0 800878e: d009 beq.n 80087a4 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008790: 687b ldr r3, [r7, #4] 8008792: 681b ldr r3, [r3, #0] 8008794: 2210 movs r2, #16 8008796: 61da str r2, [r3, #28] /* Set acknowledge error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008798: 687b ldr r3, [r7, #4] 800879a: 6c5b ldr r3, [r3, #68] @ 0x44 800879c: f043 0204 orr.w r2, r3, #4 80087a0: 687b ldr r3, [r7, #4] 80087a2: 645a str r2, [r3, #68] @ 0x44 } /* Fetch Last receive data if any */ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) 80087a4: 687b ldr r3, [r7, #4] 80087a6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80087aa: b2db uxtb r3, r3 80087ac: 2b60 cmp r3, #96 @ 0x60 80087ae: d10b bne.n 80087c8 80087b0: 697b ldr r3, [r7, #20] 80087b2: 089b lsrs r3, r3, #2 80087b4: f003 0301 and.w r3, r3, #1 80087b8: 2b00 cmp r3, #0 80087ba: d005 beq.n 80087c8 { /* Read data from RXDR */ tmpreg = (uint8_t)hi2c->Instance->RXDR; 80087bc: 687b ldr r3, [r7, #4] 80087be: 681b ldr r3, [r3, #0] 80087c0: 6a5b ldr r3, [r3, #36] @ 0x24 80087c2: b2db uxtb r3, r3 80087c4: 60fb str r3, [r7, #12] UNUSED(tmpreg); 80087c6: 68fb ldr r3, [r7, #12] } /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80087c8: 6878 ldr r0, [r7, #4] 80087ca: f000 fb48 bl 8008e5e /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 80087ce: 687b ldr r3, [r7, #4] 80087d0: 6c5b ldr r3, [r3, #68] @ 0x44 80087d2: 613b str r3, [r7, #16] /* Call the corresponding callback to inform upper layer of End of Transfer */ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) 80087d4: 687b ldr r3, [r7, #4] 80087d6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80087da: b2db uxtb r3, r3 80087dc: 2b60 cmp r3, #96 @ 0x60 80087de: d002 beq.n 80087e6 80087e0: 693b ldr r3, [r7, #16] 80087e2: 2b00 cmp r3, #0 80087e4: d006 beq.n 80087f4 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 80087e6: 687b ldr r3, [r7, #4] 80087e8: 6c5b ldr r3, [r3, #68] @ 0x44 80087ea: 4619 mov r1, r3 80087ec: 6878 ldr r0, [r7, #4] 80087ee: f000 fa1f bl 8008c30 } else { /* Nothing to do */ } } 80087f2: e054 b.n 800889e else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 80087f4: 687b ldr r3, [r7, #4] 80087f6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80087fa: b2db uxtb r3, r3 80087fc: 2b21 cmp r3, #33 @ 0x21 80087fe: d124 bne.n 800884a hi2c->State = HAL_I2C_STATE_READY; 8008800: 687b ldr r3, [r7, #4] 8008802: 2220 movs r2, #32 8008804: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 8008808: 687b ldr r3, [r7, #4] 800880a: 2200 movs r2, #0 800880c: 631a str r2, [r3, #48] @ 0x30 if (hi2c->Mode == HAL_I2C_MODE_MEM) 800880e: 687b ldr r3, [r7, #4] 8008810: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8008814: b2db uxtb r3, r3 8008816: 2b40 cmp r3, #64 @ 0x40 8008818: d10b bne.n 8008832 hi2c->Mode = HAL_I2C_MODE_NONE; 800881a: 687b ldr r3, [r7, #4] 800881c: 2200 movs r2, #0 800881e: f883 2042 strb.w r2, [r3, #66] @ 0x42 __HAL_UNLOCK(hi2c); 8008822: 687b ldr r3, [r7, #4] 8008824: 2200 movs r2, #0 8008826: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MemTxCpltCallback(hi2c); 800882a: 6878 ldr r0, [r7, #4] 800882c: f7fc fe04 bl 8005438 } 8008830: e035 b.n 800889e hi2c->Mode = HAL_I2C_MODE_NONE; 8008832: 687b ldr r3, [r7, #4] 8008834: 2200 movs r2, #0 8008836: f883 2042 strb.w r2, [r3, #66] @ 0x42 __HAL_UNLOCK(hi2c); 800883a: 687b ldr r3, [r7, #4] 800883c: 2200 movs r2, #0 800883e: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MasterTxCpltCallback(hi2c); 8008842: 6878 ldr r0, [r7, #4] 8008844: f7ff f9ed bl 8007c22 } 8008848: e029 b.n 800889e else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 800884a: 687b ldr r3, [r7, #4] 800884c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008850: b2db uxtb r3, r3 8008852: 2b22 cmp r3, #34 @ 0x22 8008854: d123 bne.n 800889e hi2c->State = HAL_I2C_STATE_READY; 8008856: 687b ldr r3, [r7, #4] 8008858: 2220 movs r2, #32 800885a: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 800885e: 687b ldr r3, [r7, #4] 8008860: 2200 movs r2, #0 8008862: 631a str r2, [r3, #48] @ 0x30 if (hi2c->Mode == HAL_I2C_MODE_MEM) 8008864: 687b ldr r3, [r7, #4] 8008866: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800886a: b2db uxtb r3, r3 800886c: 2b40 cmp r3, #64 @ 0x40 800886e: d10b bne.n 8008888 hi2c->Mode = HAL_I2C_MODE_NONE; 8008870: 687b ldr r3, [r7, #4] 8008872: 2200 movs r2, #0 8008874: f883 2042 strb.w r2, [r3, #66] @ 0x42 __HAL_UNLOCK(hi2c); 8008878: 687b ldr r3, [r7, #4] 800887a: 2200 movs r2, #0 800887c: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MemRxCpltCallback(hi2c); 8008880: 6878 ldr r0, [r7, #4] 8008882: f7fc fdad bl 80053e0 } 8008886: e00a b.n 800889e hi2c->Mode = HAL_I2C_MODE_NONE; 8008888: 687b ldr r3, [r7, #4] 800888a: 2200 movs r2, #0 800888c: f883 2042 strb.w r2, [r3, #66] @ 0x42 __HAL_UNLOCK(hi2c); 8008890: 687b ldr r3, [r7, #4] 8008892: 2200 movs r2, #0 8008894: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_MasterRxCpltCallback(hi2c); 8008898: 6878 ldr r0, [r7, #4] 800889a: f7ff f9cc bl 8007c36 } 800889e: bf00 nop 80088a0: 3718 adds r7, #24 80088a2: 46bd mov sp, r7 80088a4: bd80 pop {r7, pc} 80088a6: bf00 nop 80088a8: fe00e800 .word 0xfe00e800 80088ac: ffff0000 .word 0xffff0000 080088b0 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 80088b0: b580 push {r7, lr} 80088b2: b086 sub sp, #24 80088b4: af00 add r7, sp, #0 80088b6: 6078 str r0, [r7, #4] 80088b8: 6039 str r1, [r7, #0] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 80088ba: 687b ldr r3, [r7, #4] 80088bc: 681b ldr r3, [r3, #0] 80088be: 681b ldr r3, [r3, #0] 80088c0: 613b str r3, [r7, #16] uint32_t tmpITFlags = ITFlags; 80088c2: 683b ldr r3, [r7, #0] 80088c4: 617b str r3, [r7, #20] uint32_t tmpoptions = hi2c->XferOptions; 80088c6: 687b ldr r3, [r7, #4] 80088c8: 6adb ldr r3, [r3, #44] @ 0x2c 80088ca: 60fb str r3, [r7, #12] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 80088cc: 687b ldr r3, [r7, #4] 80088ce: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80088d2: 72fb strb r3, [r7, #11] /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 80088d4: 687b ldr r3, [r7, #4] 80088d6: 681b ldr r3, [r3, #0] 80088d8: 2220 movs r2, #32 80088da: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 80088dc: 7afb ldrb r3, [r7, #11] 80088de: 2b21 cmp r3, #33 @ 0x21 80088e0: d002 beq.n 80088e8 80088e2: 7afb ldrb r3, [r7, #11] 80088e4: 2b29 cmp r3, #41 @ 0x29 80088e6: d108 bne.n 80088fa { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); 80088e8: f248 0101 movw r1, #32769 @ 0x8001 80088ec: 6878 ldr r0, [r7, #4] 80088ee: f000 fc5b bl 80091a8 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 80088f2: 687b ldr r3, [r7, #4] 80088f4: 2221 movs r2, #33 @ 0x21 80088f6: 631a str r2, [r3, #48] @ 0x30 80088f8: e019 b.n 800892e } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 80088fa: 7afb ldrb r3, [r7, #11] 80088fc: 2b22 cmp r3, #34 @ 0x22 80088fe: d002 beq.n 8008906 8008900: 7afb ldrb r3, [r7, #11] 8008902: 2b2a cmp r3, #42 @ 0x2a 8008904: d108 bne.n 8008918 { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); 8008906: f248 0102 movw r1, #32770 @ 0x8002 800890a: 6878 ldr r0, [r7, #4] 800890c: f000 fc4c bl 80091a8 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 8008910: 687b ldr r3, [r7, #4] 8008912: 2222 movs r2, #34 @ 0x22 8008914: 631a str r2, [r3, #48] @ 0x30 8008916: e00a b.n 800892e } else if (tmpstate == HAL_I2C_STATE_LISTEN) 8008918: 7afb ldrb r3, [r7, #11] 800891a: 2b28 cmp r3, #40 @ 0x28 800891c: d107 bne.n 800892e { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); 800891e: f248 0103 movw r1, #32771 @ 0x8003 8008922: 6878 ldr r0, [r7, #4] 8008924: f000 fc40 bl 80091a8 hi2c->PreviousState = I2C_STATE_NONE; 8008928: 687b ldr r3, [r7, #4] 800892a: 2200 movs r2, #0 800892c: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; 800892e: 687b ldr r3, [r7, #4] 8008930: 681b ldr r3, [r3, #0] 8008932: 685a ldr r2, [r3, #4] 8008934: 687b ldr r3, [r7, #4] 8008936: 681b ldr r3, [r3, #0] 8008938: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800893c: 605a str r2, [r3, #4] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 800893e: 687b ldr r3, [r7, #4] 8008940: 681b ldr r3, [r3, #0] 8008942: 6859 ldr r1, [r3, #4] 8008944: 687b ldr r3, [r7, #4] 8008946: 681a ldr r2, [r3, #0] 8008948: 4b8c ldr r3, [pc, #560] @ (8008b7c ) 800894a: 400b ands r3, r1 800894c: 6053 str r3, [r2, #4] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 800894e: 6878 ldr r0, [r7, #4] 8008950: f000 fa85 bl 8008e5e #if defined(HAL_DMA_MODULE_ENABLED) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 8008954: 693b ldr r3, [r7, #16] 8008956: 0b9b lsrs r3, r3, #14 8008958: f003 0301 and.w r3, r3, #1 800895c: 2b00 cmp r3, #0 800895e: d013 beq.n 8008988 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8008960: 687b ldr r3, [r7, #4] 8008962: 681b ldr r3, [r3, #0] 8008964: 681a ldr r2, [r3, #0] 8008966: 687b ldr r3, [r7, #4] 8008968: 681b ldr r3, [r3, #0] 800896a: f422 4280 bic.w r2, r2, #16384 @ 0x4000 800896e: 601a str r2, [r3, #0] if (hi2c->hdmatx != NULL) 8008970: 687b ldr r3, [r7, #4] 8008972: 6b9b ldr r3, [r3, #56] @ 0x38 8008974: 2b00 cmp r3, #0 8008976: d020 beq.n 80089ba { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); 8008978: 687b ldr r3, [r7, #4] 800897a: 6b9b ldr r3, [r3, #56] @ 0x38 800897c: 681b ldr r3, [r3, #0] 800897e: 685b ldr r3, [r3, #4] 8008980: b29a uxth r2, r3 8008982: 687b ldr r3, [r7, #4] 8008984: 855a strh r2, [r3, #42] @ 0x2a 8008986: e018 b.n 80089ba } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 8008988: 693b ldr r3, [r7, #16] 800898a: 0bdb lsrs r3, r3, #15 800898c: f003 0301 and.w r3, r3, #1 8008990: 2b00 cmp r3, #0 8008992: d012 beq.n 80089ba { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8008994: 687b ldr r3, [r7, #4] 8008996: 681b ldr r3, [r3, #0] 8008998: 681a ldr r2, [r3, #0] 800899a: 687b ldr r3, [r7, #4] 800899c: 681b ldr r3, [r3, #0] 800899e: f422 4200 bic.w r2, r2, #32768 @ 0x8000 80089a2: 601a str r2, [r3, #0] if (hi2c->hdmarx != NULL) 80089a4: 687b ldr r3, [r7, #4] 80089a6: 6bdb ldr r3, [r3, #60] @ 0x3c 80089a8: 2b00 cmp r3, #0 80089aa: d006 beq.n 80089ba { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); 80089ac: 687b ldr r3, [r7, #4] 80089ae: 6bdb ldr r3, [r3, #60] @ 0x3c 80089b0: 681b ldr r3, [r3, #0] 80089b2: 685b ldr r3, [r3, #4] 80089b4: b29a uxth r2, r3 80089b6: 687b ldr r3, [r7, #4] 80089b8: 855a strh r2, [r3, #42] @ 0x2a /* Do nothing */ } #endif /* HAL_DMA_MODULE_ENABLED */ /* Store Last receive data if any */ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) 80089ba: 697b ldr r3, [r7, #20] 80089bc: 089b lsrs r3, r3, #2 80089be: f003 0301 and.w r3, r3, #1 80089c2: 2b00 cmp r3, #0 80089c4: d020 beq.n 8008a08 { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; 80089c6: 697b ldr r3, [r7, #20] 80089c8: f023 0304 bic.w r3, r3, #4 80089cc: 617b str r3, [r7, #20] /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 80089ce: 687b ldr r3, [r7, #4] 80089d0: 681b ldr r3, [r3, #0] 80089d2: 6a5a ldr r2, [r3, #36] @ 0x24 80089d4: 687b ldr r3, [r7, #4] 80089d6: 6a5b ldr r3, [r3, #36] @ 0x24 80089d8: b2d2 uxtb r2, r2 80089da: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80089dc: 687b ldr r3, [r7, #4] 80089de: 6a5b ldr r3, [r3, #36] @ 0x24 80089e0: 1c5a adds r2, r3, #1 80089e2: 687b ldr r3, [r7, #4] 80089e4: 625a str r2, [r3, #36] @ 0x24 if (hi2c->XferSize > 0U) 80089e6: 687b ldr r3, [r7, #4] 80089e8: 8d1b ldrh r3, [r3, #40] @ 0x28 80089ea: 2b00 cmp r3, #0 80089ec: d00c beq.n 8008a08 { hi2c->XferSize--; 80089ee: 687b ldr r3, [r7, #4] 80089f0: 8d1b ldrh r3, [r3, #40] @ 0x28 80089f2: 3b01 subs r3, #1 80089f4: b29a uxth r2, r3 80089f6: 687b ldr r3, [r7, #4] 80089f8: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 80089fa: 687b ldr r3, [r7, #4] 80089fc: 8d5b ldrh r3, [r3, #42] @ 0x2a 80089fe: b29b uxth r3, r3 8008a00: 3b01 subs r3, #1 8008a02: b29a uxth r2, r3 8008a04: 687b ldr r3, [r7, #4] 8008a06: 855a strh r2, [r3, #42] @ 0x2a } } /* All data are not transferred, so set error code accordingly */ if (hi2c->XferCount != 0U) 8008a08: 687b ldr r3, [r7, #4] 8008a0a: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008a0c: b29b uxth r3, r3 8008a0e: 2b00 cmp r3, #0 8008a10: d005 beq.n 8008a1e { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008a12: 687b ldr r3, [r7, #4] 8008a14: 6c5b ldr r3, [r3, #68] @ 0x44 8008a16: f043 0204 orr.w r2, r3, #4 8008a1a: 687b ldr r3, [r7, #4] 8008a1c: 645a str r2, [r3, #68] @ 0x44 } if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8008a1e: 697b ldr r3, [r7, #20] 8008a20: 091b lsrs r3, r3, #4 8008a22: f003 0301 and.w r3, r3, #1 8008a26: 2b00 cmp r3, #0 8008a28: d04a beq.n 8008ac0 (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) 8008a2a: 693b ldr r3, [r7, #16] 8008a2c: 091b lsrs r3, r3, #4 8008a2e: f003 0301 and.w r3, r3, #1 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8008a32: 2b00 cmp r3, #0 8008a34: d044 beq.n 8008ac0 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 8008a36: 687b ldr r3, [r7, #4] 8008a38: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008a3a: b29b uxth r3, r3 8008a3c: 2b00 cmp r3, #0 8008a3e: d128 bne.n 8008a92 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8008a40: 687b ldr r3, [r7, #4] 8008a42: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008a46: b2db uxtb r3, r3 8008a48: 2b28 cmp r3, #40 @ 0x28 8008a4a: d108 bne.n 8008a5e 8008a4c: 68fb ldr r3, [r7, #12] 8008a4e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8008a52: d104 bne.n 8008a5e /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8008a54: 6979 ldr r1, [r7, #20] 8008a56: 6878 ldr r0, [r7, #4] 8008a58: f000 f894 bl 8008b84 8008a5c: e030 b.n 8008ac0 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 8008a5e: 687b ldr r3, [r7, #4] 8008a60: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008a64: b2db uxtb r3, r3 8008a66: 2b29 cmp r3, #41 @ 0x29 8008a68: d10e bne.n 8008a88 8008a6a: 68fb ldr r3, [r7, #12] 8008a6c: f513 3f80 cmn.w r3, #65536 @ 0x10000 8008a70: d00a beq.n 8008a88 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008a72: 687b ldr r3, [r7, #4] 8008a74: 681b ldr r3, [r3, #0] 8008a76: 2210 movs r2, #16 8008a78: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8008a7a: 6878 ldr r0, [r7, #4] 8008a7c: f000 f9ef bl 8008e5e /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8008a80: 6878 ldr r0, [r7, #4] 8008a82: f7ff fded bl 8008660 8008a86: e01b b.n 8008ac0 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008a88: 687b ldr r3, [r7, #4] 8008a8a: 681b ldr r3, [r3, #0] 8008a8c: 2210 movs r2, #16 8008a8e: 61da str r2, [r3, #28] 8008a90: e016 b.n 8008ac0 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008a92: 687b ldr r3, [r7, #4] 8008a94: 681b ldr r3, [r3, #0] 8008a96: 2210 movs r2, #16 8008a98: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008a9a: 687b ldr r3, [r7, #4] 8008a9c: 6c5b ldr r3, [r3, #68] @ 0x44 8008a9e: f043 0204 orr.w r2, r3, #4 8008aa2: 687b ldr r3, [r7, #4] 8008aa4: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8008aa6: 68fb ldr r3, [r7, #12] 8008aa8: 2b00 cmp r3, #0 8008aaa: d003 beq.n 8008ab4 8008aac: 68fb ldr r3, [r7, #12] 8008aae: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8008ab2: d105 bne.n 8008ac0 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8008ab4: 687b ldr r3, [r7, #4] 8008ab6: 6c5b ldr r3, [r3, #68] @ 0x44 8008ab8: 4619 mov r1, r3 8008aba: 6878 ldr r0, [r7, #4] 8008abc: f000 f8b8 bl 8008c30 } } } hi2c->Mode = HAL_I2C_MODE_NONE; 8008ac0: 687b ldr r3, [r7, #4] 8008ac2: 2200 movs r2, #0 8008ac4: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->XferISR = NULL; 8008ac8: 687b ldr r3, [r7, #4] 8008aca: 2200 movs r2, #0 8008acc: 635a str r2, [r3, #52] @ 0x34 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 8008ace: 687b ldr r3, [r7, #4] 8008ad0: 6c5b ldr r3, [r3, #68] @ 0x44 8008ad2: 2b00 cmp r3, #0 8008ad4: d010 beq.n 8008af8 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8008ad6: 687b ldr r3, [r7, #4] 8008ad8: 6c5b ldr r3, [r3, #68] @ 0x44 8008ada: 4619 mov r1, r3 8008adc: 6878 ldr r0, [r7, #4] 8008ade: f000 f8a7 bl 8008c30 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ if (hi2c->State == HAL_I2C_STATE_LISTEN) 8008ae2: 687b ldr r3, [r7, #4] 8008ae4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008ae8: b2db uxtb r3, r3 8008aea: 2b28 cmp r3, #40 @ 0x28 8008aec: d141 bne.n 8008b72 { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8008aee: 6979 ldr r1, [r7, #20] 8008af0: 6878 ldr r0, [r7, #4] 8008af2: f000 f847 bl 8008b84 hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 8008af6: e03c b.n 8008b72 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 8008af8: 687b ldr r3, [r7, #4] 8008afa: 6adb ldr r3, [r3, #44] @ 0x2c 8008afc: f513 3f80 cmn.w r3, #65536 @ 0x10000 8008b00: d014 beq.n 8008b2c I2C_ITSlaveSeqCplt(hi2c); 8008b02: 6878 ldr r0, [r7, #4] 8008b04: f7ff fdac bl 8008660 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8008b08: 687b ldr r3, [r7, #4] 8008b0a: 4a1d ldr r2, [pc, #116] @ (8008b80 ) 8008b0c: 62da str r2, [r3, #44] @ 0x2c hi2c->State = HAL_I2C_STATE_READY; 8008b0e: 687b ldr r3, [r7, #4] 8008b10: 2220 movs r2, #32 8008b12: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 8008b16: 687b ldr r3, [r7, #4] 8008b18: 2200 movs r2, #0 8008b1a: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8008b1c: 687b ldr r3, [r7, #4] 8008b1e: 2200 movs r2, #0 8008b20: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_ListenCpltCallback(hi2c); 8008b24: 6878 ldr r0, [r7, #4] 8008b26: f7ff f8b2 bl 8007c8e } 8008b2a: e022 b.n 8008b72 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8008b2c: 687b ldr r3, [r7, #4] 8008b2e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008b32: b2db uxtb r3, r3 8008b34: 2b22 cmp r3, #34 @ 0x22 8008b36: d10e bne.n 8008b56 hi2c->State = HAL_I2C_STATE_READY; 8008b38: 687b ldr r3, [r7, #4] 8008b3a: 2220 movs r2, #32 8008b3c: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 8008b40: 687b ldr r3, [r7, #4] 8008b42: 2200 movs r2, #0 8008b44: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8008b46: 687b ldr r3, [r7, #4] 8008b48: 2200 movs r2, #0 8008b4a: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_SlaveRxCpltCallback(hi2c); 8008b4e: 6878 ldr r0, [r7, #4] 8008b50: f7ff f885 bl 8007c5e } 8008b54: e00d b.n 8008b72 hi2c->State = HAL_I2C_STATE_READY; 8008b56: 687b ldr r3, [r7, #4] 8008b58: 2220 movs r2, #32 8008b5a: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 8008b5e: 687b ldr r3, [r7, #4] 8008b60: 2200 movs r2, #0 8008b62: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8008b64: 687b ldr r3, [r7, #4] 8008b66: 2200 movs r2, #0 8008b68: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_SlaveTxCpltCallback(hi2c); 8008b6c: 6878 ldr r0, [r7, #4] 8008b6e: f7ff f86c bl 8007c4a } 8008b72: bf00 nop 8008b74: 3718 adds r7, #24 8008b76: 46bd mov sp, r7 8008b78: bd80 pop {r7, pc} 8008b7a: bf00 nop 8008b7c: fe00e800 .word 0xfe00e800 8008b80: ffff0000 .word 0xffff0000 08008b84 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8008b84: b580 push {r7, lr} 8008b86: b082 sub sp, #8 8008b88: af00 add r7, sp, #0 8008b8a: 6078 str r0, [r7, #4] 8008b8c: 6039 str r1, [r7, #0] /* Reset handle parameters */ hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8008b8e: 687b ldr r3, [r7, #4] 8008b90: 4a26 ldr r2, [pc, #152] @ (8008c2c ) 8008b92: 62da str r2, [r3, #44] @ 0x2c hi2c->PreviousState = I2C_STATE_NONE; 8008b94: 687b ldr r3, [r7, #4] 8008b96: 2200 movs r2, #0 8008b98: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 8008b9a: 687b ldr r3, [r7, #4] 8008b9c: 2220 movs r2, #32 8008b9e: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; 8008ba2: 687b ldr r3, [r7, #4] 8008ba4: 2200 movs r2, #0 8008ba6: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->XferISR = NULL; 8008baa: 687b ldr r3, [r7, #4] 8008bac: 2200 movs r2, #0 8008bae: 635a str r2, [r3, #52] @ 0x34 /* Store Last receive data if any */ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) 8008bb0: 683b ldr r3, [r7, #0] 8008bb2: 089b lsrs r3, r3, #2 8008bb4: f003 0301 and.w r3, r3, #1 8008bb8: 2b00 cmp r3, #0 8008bba: d022 beq.n 8008c02 { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8008bbc: 687b ldr r3, [r7, #4] 8008bbe: 681b ldr r3, [r3, #0] 8008bc0: 6a5a ldr r2, [r3, #36] @ 0x24 8008bc2: 687b ldr r3, [r7, #4] 8008bc4: 6a5b ldr r3, [r3, #36] @ 0x24 8008bc6: b2d2 uxtb r2, r2 8008bc8: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8008bca: 687b ldr r3, [r7, #4] 8008bcc: 6a5b ldr r3, [r3, #36] @ 0x24 8008bce: 1c5a adds r2, r3, #1 8008bd0: 687b ldr r3, [r7, #4] 8008bd2: 625a str r2, [r3, #36] @ 0x24 if (hi2c->XferSize > 0U) 8008bd4: 687b ldr r3, [r7, #4] 8008bd6: 8d1b ldrh r3, [r3, #40] @ 0x28 8008bd8: 2b00 cmp r3, #0 8008bda: d012 beq.n 8008c02 { hi2c->XferSize--; 8008bdc: 687b ldr r3, [r7, #4] 8008bde: 8d1b ldrh r3, [r3, #40] @ 0x28 8008be0: 3b01 subs r3, #1 8008be2: b29a uxth r2, r3 8008be4: 687b ldr r3, [r7, #4] 8008be6: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8008be8: 687b ldr r3, [r7, #4] 8008bea: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008bec: b29b uxth r3, r3 8008bee: 3b01 subs r3, #1 8008bf0: b29a uxth r2, r3 8008bf2: 687b ldr r3, [r7, #4] 8008bf4: 855a strh r2, [r3, #42] @ 0x2a /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008bf6: 687b ldr r3, [r7, #4] 8008bf8: 6c5b ldr r3, [r3, #68] @ 0x44 8008bfa: f043 0204 orr.w r2, r3, #4 8008bfe: 687b ldr r3, [r7, #4] 8008c00: 645a str r2, [r3, #68] @ 0x44 } } /* Disable all Interrupts*/ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8008c02: f248 0103 movw r1, #32771 @ 0x8003 8008c06: 6878 ldr r0, [r7, #4] 8008c08: f000 face bl 80091a8 /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008c0c: 687b ldr r3, [r7, #4] 8008c0e: 681b ldr r3, [r3, #0] 8008c10: 2210 movs r2, #16 8008c12: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008c14: 687b ldr r3, [r7, #4] 8008c16: 2200 movs r2, #0 8008c18: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ListenCpltCallback(hi2c); #else HAL_I2C_ListenCpltCallback(hi2c); 8008c1c: 6878 ldr r0, [r7, #4] 8008c1e: f7ff f836 bl 8007c8e #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } 8008c22: bf00 nop 8008c24: 3708 adds r7, #8 8008c26: 46bd mov sp, r7 8008c28: bd80 pop {r7, pc} 8008c2a: bf00 nop 8008c2c: ffff0000 .word 0xffff0000 08008c30 : * @param hi2c I2C handle. * @param ErrorCode Error code to handle. * @retval None */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { 8008c30: b580 push {r7, lr} 8008c32: b084 sub sp, #16 8008c34: af00 add r7, sp, #0 8008c36: 6078 str r0, [r7, #4] 8008c38: 6039 str r1, [r7, #0] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 8008c3a: 687b ldr r3, [r7, #4] 8008c3c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008c40: 73fb strb r3, [r7, #15] #if defined(HAL_DMA_MODULE_ENABLED) uint32_t tmppreviousstate; #endif /* HAL_DMA_MODULE_ENABLED */ /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; 8008c42: 687b ldr r3, [r7, #4] 8008c44: 2200 movs r2, #0 8008c46: f883 2042 strb.w r2, [r3, #66] @ 0x42 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8008c4a: 687b ldr r3, [r7, #4] 8008c4c: 4a6d ldr r2, [pc, #436] @ (8008e04 ) 8008c4e: 62da str r2, [r3, #44] @ 0x2c hi2c->XferCount = 0U; 8008c50: 687b ldr r3, [r7, #4] 8008c52: 2200 movs r2, #0 8008c54: 855a strh r2, [r3, #42] @ 0x2a /* Set new error code */ hi2c->ErrorCode |= ErrorCode; 8008c56: 687b ldr r3, [r7, #4] 8008c58: 6c5a ldr r2, [r3, #68] @ 0x44 8008c5a: 683b ldr r3, [r7, #0] 8008c5c: 431a orrs r2, r3 8008c5e: 687b ldr r3, [r7, #4] 8008c60: 645a str r2, [r3, #68] @ 0x44 /* Disable Interrupts */ if ((tmpstate == HAL_I2C_STATE_LISTEN) || 8008c62: 7bfb ldrb r3, [r7, #15] 8008c64: 2b28 cmp r3, #40 @ 0x28 8008c66: d005 beq.n 8008c74 8008c68: 7bfb ldrb r3, [r7, #15] 8008c6a: 2b29 cmp r3, #41 @ 0x29 8008c6c: d002 beq.n 8008c74 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || 8008c6e: 7bfb ldrb r3, [r7, #15] 8008c70: 2b2a cmp r3, #42 @ 0x2a 8008c72: d10b bne.n 8008c8c (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8008c74: 2103 movs r1, #3 8008c76: 6878 ldr r0, [r7, #4] 8008c78: f000 fa96 bl 80091a8 /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; 8008c7c: 687b ldr r3, [r7, #4] 8008c7e: 2228 movs r2, #40 @ 0x28 8008c80: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->XferISR = I2C_Slave_ISR_IT; 8008c84: 687b ldr r3, [r7, #4] 8008c86: 4a60 ldr r2, [pc, #384] @ (8008e08 ) 8008c88: 635a str r2, [r3, #52] @ 0x34 8008c8a: e030 b.n 8008cee } else { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8008c8c: f248 0103 movw r1, #32771 @ 0x8003 8008c90: 6878 ldr r0, [r7, #4] 8008c92: f000 fa89 bl 80091a8 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8008c96: 6878 ldr r0, [r7, #4] 8008c98: f000 f8e1 bl 8008e5e /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) 8008c9c: 687b ldr r3, [r7, #4] 8008c9e: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008ca2: b2db uxtb r3, r3 8008ca4: 2b60 cmp r3, #96 @ 0x60 8008ca6: d01f beq.n 8008ce8 { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; 8008ca8: 687b ldr r3, [r7, #4] 8008caa: 2220 movs r2, #32 8008cac: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 8008cb0: 687b ldr r3, [r7, #4] 8008cb2: 681b ldr r3, [r3, #0] 8008cb4: 699b ldr r3, [r3, #24] 8008cb6: f003 0320 and.w r3, r3, #32 8008cba: 2b20 cmp r3, #32 8008cbc: d114 bne.n 8008ce8 { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 8008cbe: 687b ldr r3, [r7, #4] 8008cc0: 681b ldr r3, [r3, #0] 8008cc2: 699b ldr r3, [r3, #24] 8008cc4: f003 0310 and.w r3, r3, #16 8008cc8: 2b10 cmp r3, #16 8008cca: d109 bne.n 8008ce0 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8008ccc: 687b ldr r3, [r7, #4] 8008cce: 681b ldr r3, [r3, #0] 8008cd0: 2210 movs r2, #16 8008cd2: 61da str r2, [r3, #28] hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8008cd4: 687b ldr r3, [r7, #4] 8008cd6: 6c5b ldr r3, [r3, #68] @ 0x44 8008cd8: f043 0204 orr.w r2, r3, #4 8008cdc: 687b ldr r3, [r7, #4] 8008cde: 645a str r2, [r3, #68] @ 0x44 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8008ce0: 687b ldr r3, [r7, #4] 8008ce2: 681b ldr r3, [r3, #0] 8008ce4: 2220 movs r2, #32 8008ce6: 61da str r2, [r3, #28] } } hi2c->XferISR = NULL; 8008ce8: 687b ldr r3, [r7, #4] 8008cea: 2200 movs r2, #0 8008cec: 635a str r2, [r3, #52] @ 0x34 } #if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; 8008cee: 687b ldr r3, [r7, #4] 8008cf0: 6b1b ldr r3, [r3, #48] @ 0x30 8008cf2: 60bb str r3, [r7, #8] if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ 8008cf4: 687b ldr r3, [r7, #4] 8008cf6: 6b9b ldr r3, [r3, #56] @ 0x38 8008cf8: 2b00 cmp r3, #0 8008cfa: d039 beq.n 8008d70 8008cfc: 68bb ldr r3, [r7, #8] 8008cfe: 2b11 cmp r3, #17 8008d00: d002 beq.n 8008d08 8008d02: 68bb ldr r3, [r7, #8] 8008d04: 2b21 cmp r3, #33 @ 0x21 8008d06: d133 bne.n 8008d70 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) 8008d08: 687b ldr r3, [r7, #4] 8008d0a: 681b ldr r3, [r3, #0] 8008d0c: 681b ldr r3, [r3, #0] 8008d0e: f403 4380 and.w r3, r3, #16384 @ 0x4000 8008d12: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8008d16: d107 bne.n 8008d28 { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8008d18: 687b ldr r3, [r7, #4] 8008d1a: 681b ldr r3, [r3, #0] 8008d1c: 681a ldr r2, [r3, #0] 8008d1e: 687b ldr r3, [r7, #4] 8008d20: 681b ldr r3, [r3, #0] 8008d22: f422 4280 bic.w r2, r2, #16384 @ 0x4000 8008d26: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8008d28: 687b ldr r3, [r7, #4] 8008d2a: 6b9b ldr r3, [r3, #56] @ 0x38 8008d2c: 4618 mov r0, r3 8008d2e: f7fe fa21 bl 8007174 8008d32: 4603 mov r3, r0 8008d34: 2b01 cmp r3, #1 8008d36: d017 beq.n 8008d68 { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 8008d38: 687b ldr r3, [r7, #4] 8008d3a: 6b9b ldr r3, [r3, #56] @ 0x38 8008d3c: 4a33 ldr r2, [pc, #204] @ (8008e0c ) 8008d3e: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008d40: 687b ldr r3, [r7, #4] 8008d42: 2200 movs r2, #0 8008d44: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 8008d48: 687b ldr r3, [r7, #4] 8008d4a: 6b9b ldr r3, [r3, #56] @ 0x38 8008d4c: 4618 mov r0, r3 8008d4e: f7fe f903 bl 8006f58 8008d52: 4603 mov r3, r0 8008d54: 2b00 cmp r3, #0 8008d56: d04d beq.n 8008df4 { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 8008d58: 687b ldr r3, [r7, #4] 8008d5a: 6b9b ldr r3, [r3, #56] @ 0x38 8008d5c: 6b9b ldr r3, [r3, #56] @ 0x38 8008d5e: 687a ldr r2, [r7, #4] 8008d60: 6b92 ldr r2, [r2, #56] @ 0x38 8008d62: 4610 mov r0, r2 8008d64: 4798 blx r3 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8008d66: e045 b.n 8008df4 } } else { I2C_TreatErrorCallback(hi2c); 8008d68: 6878 ldr r0, [r7, #4] 8008d6a: f000 f851 bl 8008e10 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8008d6e: e041 b.n 8008df4 } } /* Abort DMA RX transfer if any */ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ 8008d70: 687b ldr r3, [r7, #4] 8008d72: 6bdb ldr r3, [r3, #60] @ 0x3c 8008d74: 2b00 cmp r3, #0 8008d76: d039 beq.n 8008dec 8008d78: 68bb ldr r3, [r7, #8] 8008d7a: 2b12 cmp r3, #18 8008d7c: d002 beq.n 8008d84 8008d7e: 68bb ldr r3, [r7, #8] 8008d80: 2b22 cmp r3, #34 @ 0x22 8008d82: d133 bne.n 8008dec (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) 8008d84: 687b ldr r3, [r7, #4] 8008d86: 681b ldr r3, [r3, #0] 8008d88: 681b ldr r3, [r3, #0] 8008d8a: f403 4300 and.w r3, r3, #32768 @ 0x8000 8008d8e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8008d92: d107 bne.n 8008da4 { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8008d94: 687b ldr r3, [r7, #4] 8008d96: 681b ldr r3, [r3, #0] 8008d98: 681a ldr r2, [r3, #0] 8008d9a: 687b ldr r3, [r7, #4] 8008d9c: 681b ldr r3, [r3, #0] 8008d9e: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8008da2: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8008da4: 687b ldr r3, [r7, #4] 8008da6: 6bdb ldr r3, [r3, #60] @ 0x3c 8008da8: 4618 mov r0, r3 8008daa: f7fe f9e3 bl 8007174 8008dae: 4603 mov r3, r0 8008db0: 2b01 cmp r3, #1 8008db2: d017 beq.n 8008de4 { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 8008db4: 687b ldr r3, [r7, #4] 8008db6: 6bdb ldr r3, [r3, #60] @ 0x3c 8008db8: 4a14 ldr r2, [pc, #80] @ (8008e0c ) 8008dba: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008dbc: 687b ldr r3, [r7, #4] 8008dbe: 2200 movs r2, #0 8008dc0: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 8008dc4: 687b ldr r3, [r7, #4] 8008dc6: 6bdb ldr r3, [r3, #60] @ 0x3c 8008dc8: 4618 mov r0, r3 8008dca: f7fe f8c5 bl 8006f58 8008dce: 4603 mov r3, r0 8008dd0: 2b00 cmp r3, #0 8008dd2: d011 beq.n 8008df8 { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 8008dd4: 687b ldr r3, [r7, #4] 8008dd6: 6bdb ldr r3, [r3, #60] @ 0x3c 8008dd8: 6b9b ldr r3, [r3, #56] @ 0x38 8008dda: 687a ldr r2, [r7, #4] 8008ddc: 6bd2 ldr r2, [r2, #60] @ 0x3c 8008dde: 4610 mov r0, r2 8008de0: 4798 blx r3 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8008de2: e009 b.n 8008df8 } } else { I2C_TreatErrorCallback(hi2c); 8008de4: 6878 ldr r0, [r7, #4] 8008de6: f000 f813 bl 8008e10 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8008dea: e005 b.n 8008df8 } } else #endif /* HAL_DMA_MODULE_ENABLED */ { I2C_TreatErrorCallback(hi2c); 8008dec: 6878 ldr r0, [r7, #4] 8008dee: f000 f80f bl 8008e10 } } 8008df2: e002 b.n 8008dfa if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8008df4: bf00 nop 8008df6: e000 b.n 8008dfa if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8008df8: bf00 nop } 8008dfa: bf00 nop 8008dfc: 3710 adds r7, #16 8008dfe: 46bd mov sp, r7 8008e00: bd80 pop {r7, pc} 8008e02: bf00 nop 8008e04: ffff0000 .word 0xffff0000 8008e08: 08007ccf .word 0x08007ccf 8008e0c: 08009001 .word 0x08009001 08008e10 : * @brief I2C Error callback treatment. * @param hi2c I2C handle. * @retval None */ static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) { 8008e10: b580 push {r7, lr} 8008e12: b082 sub sp, #8 8008e14: af00 add r7, sp, #0 8008e16: 6078 str r0, [r7, #4] if (hi2c->State == HAL_I2C_STATE_ABORT) 8008e18: 687b ldr r3, [r7, #4] 8008e1a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8008e1e: b2db uxtb r3, r3 8008e20: 2b60 cmp r3, #96 @ 0x60 8008e22: d10e bne.n 8008e42 { hi2c->State = HAL_I2C_STATE_READY; 8008e24: 687b ldr r3, [r7, #4] 8008e26: 2220 movs r2, #32 8008e28: f883 2041 strb.w r2, [r3, #65] @ 0x41 hi2c->PreviousState = I2C_STATE_NONE; 8008e2c: 687b ldr r3, [r7, #4] 8008e2e: 2200 movs r2, #0 8008e30: 631a str r2, [r3, #48] @ 0x30 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8008e32: 687b ldr r3, [r7, #4] 8008e34: 2200 movs r2, #0 8008e36: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AbortCpltCallback(hi2c); #else HAL_I2C_AbortCpltCallback(hi2c); 8008e3a: 6878 ldr r0, [r7, #4] 8008e3c: f7fe ff31 bl 8007ca2 hi2c->ErrorCallback(hi2c); #else HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 8008e40: e009 b.n 8008e56 hi2c->PreviousState = I2C_STATE_NONE; 8008e42: 687b ldr r3, [r7, #4] 8008e44: 2200 movs r2, #0 8008e46: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8008e48: 687b ldr r3, [r7, #4] 8008e4a: 2200 movs r2, #0 8008e4c: f883 2040 strb.w r2, [r3, #64] @ 0x40 HAL_I2C_ErrorCallback(hi2c); 8008e50: 6878 ldr r0, [r7, #4] 8008e52: f7fc fb1d bl 8005490 } 8008e56: bf00 nop 8008e58: 3708 adds r7, #8 8008e5a: 46bd mov sp, r7 8008e5c: bd80 pop {r7, pc} 08008e5e : * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { 8008e5e: b480 push {r7} 8008e60: b083 sub sp, #12 8008e62: af00 add r7, sp, #0 8008e64: 6078 str r0, [r7, #4] /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) 8008e66: 687b ldr r3, [r7, #4] 8008e68: 681b ldr r3, [r3, #0] 8008e6a: 699b ldr r3, [r3, #24] 8008e6c: f003 0302 and.w r3, r3, #2 8008e70: 2b02 cmp r3, #2 8008e72: d103 bne.n 8008e7c { hi2c->Instance->TXDR = 0x00U; 8008e74: 687b ldr r3, [r7, #4] 8008e76: 681b ldr r3, [r3, #0] 8008e78: 2200 movs r2, #0 8008e7a: 629a str r2, [r3, #40] @ 0x28 } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 8008e7c: 687b ldr r3, [r7, #4] 8008e7e: 681b ldr r3, [r3, #0] 8008e80: 699b ldr r3, [r3, #24] 8008e82: f003 0301 and.w r3, r3, #1 8008e86: 2b01 cmp r3, #1 8008e88: d007 beq.n 8008e9a { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); 8008e8a: 687b ldr r3, [r7, #4] 8008e8c: 681b ldr r3, [r3, #0] 8008e8e: 699a ldr r2, [r3, #24] 8008e90: 687b ldr r3, [r7, #4] 8008e92: 681b ldr r3, [r3, #0] 8008e94: f042 0201 orr.w r2, r2, #1 8008e98: 619a str r2, [r3, #24] } } 8008e9a: bf00 nop 8008e9c: 370c adds r7, #12 8008e9e: 46bd mov sp, r7 8008ea0: f85d 7b04 ldr.w r7, [sp], #4 8008ea4: 4770 bx lr 08008ea6 : * @brief DMA I2C master transmit process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { 8008ea6: b580 push {r7, lr} 8008ea8: b084 sub sp, #16 8008eaa: af00 add r7, sp, #0 8008eac: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8008eae: 687b ldr r3, [r7, #4] 8008eb0: 6a9b ldr r3, [r3, #40] @ 0x28 8008eb2: 60fb str r3, [r7, #12] /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8008eb4: 68fb ldr r3, [r7, #12] 8008eb6: 681b ldr r3, [r3, #0] 8008eb8: 681a ldr r2, [r3, #0] 8008eba: 68fb ldr r3, [r7, #12] 8008ebc: 681b ldr r3, [r3, #0] 8008ebe: f422 4280 bic.w r2, r2, #16384 @ 0x4000 8008ec2: 601a str r2, [r3, #0] /* If last transfer, enable STOP interrupt */ if (hi2c->XferCount == 0U) 8008ec4: 68fb ldr r3, [r7, #12] 8008ec6: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008ec8: b29b uxth r3, r3 8008eca: 2b00 cmp r3, #0 8008ecc: d104 bne.n 8008ed8 { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8008ece: 2120 movs r1, #32 8008ed0: 68f8 ldr r0, [r7, #12] 8008ed2: f000 f8e5 bl 80090a0 { /* Enable TC interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } } 8008ed6: e02d b.n 8008f34 hi2c->pBuffPtr += hi2c->XferSize; 8008ed8: 68fb ldr r3, [r7, #12] 8008eda: 6a5b ldr r3, [r3, #36] @ 0x24 8008edc: 68fa ldr r2, [r7, #12] 8008ede: 8d12 ldrh r2, [r2, #40] @ 0x28 8008ee0: 441a add r2, r3 8008ee2: 68fb ldr r3, [r7, #12] 8008ee4: 625a str r2, [r3, #36] @ 0x24 if (hi2c->XferCount > MAX_NBYTE_SIZE) 8008ee6: 68fb ldr r3, [r7, #12] 8008ee8: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008eea: b29b uxth r3, r3 8008eec: 2bff cmp r3, #255 @ 0xff 8008eee: d903 bls.n 8008ef8 hi2c->XferSize = MAX_NBYTE_SIZE; 8008ef0: 68fb ldr r3, [r7, #12] 8008ef2: 22ff movs r2, #255 @ 0xff 8008ef4: 851a strh r2, [r3, #40] @ 0x28 8008ef6: e004 b.n 8008f02 hi2c->XferSize = hi2c->XferCount; 8008ef8: 68fb ldr r3, [r7, #12] 8008efa: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008efc: b29a uxth r2, r3 8008efe: 68fb ldr r3, [r7, #12] 8008f00: 851a strh r2, [r3, #40] @ 0x28 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, 8008f02: 68fb ldr r3, [r7, #12] 8008f04: 6b98 ldr r0, [r3, #56] @ 0x38 8008f06: 68fb ldr r3, [r7, #12] 8008f08: 6a5b ldr r3, [r3, #36] @ 0x24 8008f0a: 4619 mov r1, r3 8008f0c: 68fb ldr r3, [r7, #12] 8008f0e: 681b ldr r3, [r3, #0] 8008f10: 3328 adds r3, #40 @ 0x28 8008f12: 461a mov r2, r3 hi2c->XferSize) != HAL_OK) 8008f14: 68fb ldr r3, [r7, #12] 8008f16: 8d1b ldrh r3, [r3, #40] @ 0x28 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, 8008f18: f7fd ff44 bl 8006da4 8008f1c: 4603 mov r3, r0 8008f1e: 2b00 cmp r3, #0 8008f20: d004 beq.n 8008f2c I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); 8008f22: 2110 movs r1, #16 8008f24: 68f8 ldr r0, [r7, #12] 8008f26: f7ff fe83 bl 8008c30 } 8008f2a: e003 b.n 8008f34 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); 8008f2c: 2140 movs r1, #64 @ 0x40 8008f2e: 68f8 ldr r0, [r7, #12] 8008f30: f000 f8b6 bl 80090a0 } 8008f34: bf00 nop 8008f36: 3710 adds r7, #16 8008f38: 46bd mov sp, r7 8008f3a: bd80 pop {r7, pc} 08008f3c : * @brief DMA I2C master receive process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { 8008f3c: b580 push {r7, lr} 8008f3e: b084 sub sp, #16 8008f40: af00 add r7, sp, #0 8008f42: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8008f44: 687b ldr r3, [r7, #4] 8008f46: 6a9b ldr r3, [r3, #40] @ 0x28 8008f48: 60fb str r3, [r7, #12] /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8008f4a: 68fb ldr r3, [r7, #12] 8008f4c: 681b ldr r3, [r3, #0] 8008f4e: 681a ldr r2, [r3, #0] 8008f50: 68fb ldr r3, [r7, #12] 8008f52: 681b ldr r3, [r3, #0] 8008f54: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8008f58: 601a str r2, [r3, #0] /* If last transfer, enable STOP interrupt */ if (hi2c->XferCount == 0U) 8008f5a: 68fb ldr r3, [r7, #12] 8008f5c: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008f5e: b29b uxth r3, r3 8008f60: 2b00 cmp r3, #0 8008f62: d104 bne.n 8008f6e { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8008f64: 2120 movs r1, #32 8008f66: 68f8 ldr r0, [r7, #12] 8008f68: f000 f89a bl 80090a0 { /* Enable TC interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } } 8008f6c: e02d b.n 8008fca hi2c->pBuffPtr += hi2c->XferSize; 8008f6e: 68fb ldr r3, [r7, #12] 8008f70: 6a5b ldr r3, [r3, #36] @ 0x24 8008f72: 68fa ldr r2, [r7, #12] 8008f74: 8d12 ldrh r2, [r2, #40] @ 0x28 8008f76: 441a add r2, r3 8008f78: 68fb ldr r3, [r7, #12] 8008f7a: 625a str r2, [r3, #36] @ 0x24 if (hi2c->XferCount > MAX_NBYTE_SIZE) 8008f7c: 68fb ldr r3, [r7, #12] 8008f7e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008f80: b29b uxth r3, r3 8008f82: 2bff cmp r3, #255 @ 0xff 8008f84: d903 bls.n 8008f8e hi2c->XferSize = MAX_NBYTE_SIZE; 8008f86: 68fb ldr r3, [r7, #12] 8008f88: 22ff movs r2, #255 @ 0xff 8008f8a: 851a strh r2, [r3, #40] @ 0x28 8008f8c: e004 b.n 8008f98 hi2c->XferSize = hi2c->XferCount; 8008f8e: 68fb ldr r3, [r7, #12] 8008f90: 8d5b ldrh r3, [r3, #42] @ 0x2a 8008f92: b29a uxth r2, r3 8008f94: 68fb ldr r3, [r7, #12] 8008f96: 851a strh r2, [r3, #40] @ 0x28 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, 8008f98: 68fb ldr r3, [r7, #12] 8008f9a: 6bd8 ldr r0, [r3, #60] @ 0x3c 8008f9c: 68fb ldr r3, [r7, #12] 8008f9e: 681b ldr r3, [r3, #0] 8008fa0: 3324 adds r3, #36 @ 0x24 8008fa2: 4619 mov r1, r3 8008fa4: 68fb ldr r3, [r7, #12] 8008fa6: 6a5b ldr r3, [r3, #36] @ 0x24 8008fa8: 461a mov r2, r3 hi2c->XferSize) != HAL_OK) 8008faa: 68fb ldr r3, [r7, #12] 8008fac: 8d1b ldrh r3, [r3, #40] @ 0x28 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, 8008fae: f7fd fef9 bl 8006da4 8008fb2: 4603 mov r3, r0 8008fb4: 2b00 cmp r3, #0 8008fb6: d004 beq.n 8008fc2 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); 8008fb8: 2110 movs r1, #16 8008fba: 68f8 ldr r0, [r7, #12] 8008fbc: f7ff fe38 bl 8008c30 } 8008fc0: e003 b.n 8008fca I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); 8008fc2: 2140 movs r1, #64 @ 0x40 8008fc4: 68f8 ldr r0, [r7, #12] 8008fc6: f000 f86b bl 80090a0 } 8008fca: bf00 nop 8008fcc: 3710 adds r7, #16 8008fce: 46bd mov sp, r7 8008fd0: bd80 pop {r7, pc} 08008fd2 : * @brief DMA I2C communication error callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { 8008fd2: b580 push {r7, lr} 8008fd4: b084 sub sp, #16 8008fd6: af00 add r7, sp, #0 8008fd8: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8008fda: 687b ldr r3, [r7, #4] 8008fdc: 6a9b ldr r3, [r3, #40] @ 0x28 8008fde: 60fb str r3, [r7, #12] /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; 8008fe0: 68fb ldr r3, [r7, #12] 8008fe2: 681b ldr r3, [r3, #0] 8008fe4: 685a ldr r2, [r3, #4] 8008fe6: 68fb ldr r3, [r7, #12] 8008fe8: 681b ldr r3, [r3, #0] 8008fea: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8008fee: 605a str r2, [r3, #4] /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); 8008ff0: 2110 movs r1, #16 8008ff2: 68f8 ldr r0, [r7, #12] 8008ff4: f7ff fe1c bl 8008c30 } 8008ff8: bf00 nop 8008ffa: 3710 adds r7, #16 8008ffc: 46bd mov sp, r7 8008ffe: bd80 pop {r7, pc} 08009000 : * (To be called at end of DMA Abort procedure). * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { 8009000: b580 push {r7, lr} 8009002: b084 sub sp, #16 8009004: af00 add r7, sp, #0 8009006: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8009008: 687b ldr r3, [r7, #4] 800900a: 6a9b ldr r3, [r3, #40] @ 0x28 800900c: 60fb str r3, [r7, #12] /* Reset AbortCpltCallback */ if (hi2c->hdmatx != NULL) 800900e: 68fb ldr r3, [r7, #12] 8009010: 6b9b ldr r3, [r3, #56] @ 0x38 8009012: 2b00 cmp r3, #0 8009014: d003 beq.n 800901e { hi2c->hdmatx->XferAbortCallback = NULL; 8009016: 68fb ldr r3, [r7, #12] 8009018: 6b9b ldr r3, [r3, #56] @ 0x38 800901a: 2200 movs r2, #0 800901c: 639a str r2, [r3, #56] @ 0x38 } if (hi2c->hdmarx != NULL) 800901e: 68fb ldr r3, [r7, #12] 8009020: 6bdb ldr r3, [r3, #60] @ 0x3c 8009022: 2b00 cmp r3, #0 8009024: d003 beq.n 800902e { hi2c->hdmarx->XferAbortCallback = NULL; 8009026: 68fb ldr r3, [r7, #12] 8009028: 6bdb ldr r3, [r3, #60] @ 0x3c 800902a: 2200 movs r2, #0 800902c: 639a str r2, [r3, #56] @ 0x38 } I2C_TreatErrorCallback(hi2c); 800902e: 68f8 ldr r0, [r7, #12] 8009030: f7ff feee bl 8008e10 } 8009034: bf00 nop 8009036: 3710 adds r7, #16 8009038: 46bd mov sp, r7 800903a: bd80 pop {r7, pc} 0800903c : * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { 800903c: b480 push {r7} 800903e: b087 sub sp, #28 8009040: af00 add r7, sp, #0 8009042: 60f8 str r0, [r7, #12] 8009044: 607b str r3, [r7, #4] 8009046: 460b mov r3, r1 8009048: 817b strh r3, [r7, #10] 800904a: 4613 mov r3, r2 800904c: 727b strb r3, [r7, #9] assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 800904e: 897b ldrh r3, [r7, #10] 8009050: f3c3 0209 ubfx r2, r3, #0, #10 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 8009054: 7a7b ldrb r3, [r7, #9] 8009056: 041b lsls r3, r3, #16 8009058: f403 037f and.w r3, r3, #16711680 @ 0xff0000 tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 800905c: 431a orrs r2, r3 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 800905e: 687b ldr r3, [r7, #4] 8009060: 431a orrs r2, r3 tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 8009062: 6a3b ldr r3, [r7, #32] 8009064: 4313 orrs r3, r2 8009066: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 800906a: 617b str r3, [r7, #20] (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ 800906c: 68fb ldr r3, [r7, #12] 800906e: 681b ldr r3, [r3, #0] 8009070: 685a ldr r2, [r3, #4] 8009072: 6a3b ldr r3, [r7, #32] 8009074: 0d5b lsrs r3, r3, #21 8009076: f403 6180 and.w r1, r3, #1024 @ 0x400 800907a: 4b08 ldr r3, [pc, #32] @ (800909c ) 800907c: 430b orrs r3, r1 800907e: 43db mvns r3, r3 8009080: ea02 0103 and.w r1, r2, r3 8009084: 68fb ldr r3, [r7, #12] 8009086: 681b ldr r3, [r3, #0] 8009088: 697a ldr r2, [r7, #20] 800908a: 430a orrs r2, r1 800908c: 605a str r2, [r3, #4] ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ I2C_CR2_START | I2C_CR2_STOP)), tmp); } 800908e: bf00 nop 8009090: 371c adds r7, #28 8009092: 46bd mov sp, r7 8009094: f85d 7b04 ldr.w r7, [sp], #4 8009098: 4770 bx lr 800909a: bf00 nop 800909c: 03ff63ff .word 0x03ff63ff 080090a0 : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 80090a0: b480 push {r7} 80090a2: b085 sub sp, #20 80090a4: af00 add r7, sp, #0 80090a6: 6078 str r0, [r7, #4] 80090a8: 460b mov r3, r1 80090aa: 807b strh r3, [r7, #2] uint32_t tmpisr = 0U; 80090ac: 2300 movs r3, #0 80090ae: 60fb str r3, [r7, #12] #if defined(HAL_DMA_MODULE_ENABLED) if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ 80090b0: 687b ldr r3, [r7, #4] 80090b2: 6b5b ldr r3, [r3, #52] @ 0x34 80090b4: 4a39 ldr r2, [pc, #228] @ (800919c ) 80090b6: 4293 cmp r3, r2 80090b8: d032 beq.n 8009120 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ 80090ba: 687b ldr r3, [r7, #4] 80090bc: 6b5b ldr r3, [r3, #52] @ 0x34 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ 80090be: 4a38 ldr r2, [pc, #224] @ (80091a0 ) 80090c0: 4293 cmp r3, r2 80090c2: d02d beq.n 8009120 (hi2c->XferISR != I2C_Mem_ISR_DMA)) 80090c4: 687b ldr r3, [r7, #4] 80090c6: 6b5b ldr r3, [r3, #52] @ 0x34 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ 80090c8: 4a36 ldr r2, [pc, #216] @ (80091a4 ) 80090ca: 4293 cmp r3, r2 80090cc: d028 beq.n 8009120 #endif /* HAL_DMA_MODULE_ENABLED */ { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 80090ce: f9b7 3002 ldrsh.w r3, [r7, #2] 80090d2: 2b00 cmp r3, #0 80090d4: da03 bge.n 80090de { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 80090d6: 68fb ldr r3, [r7, #12] 80090d8: f043 03b8 orr.w r3, r3, #184 @ 0xb8 80090dc: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 80090de: 887b ldrh r3, [r7, #2] 80090e0: f003 0301 and.w r3, r3, #1 80090e4: 2b00 cmp r3, #0 80090e6: d003 beq.n 80090f0 { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; 80090e8: 68fb ldr r3, [r7, #12] 80090ea: f043 03f2 orr.w r3, r3, #242 @ 0xf2 80090ee: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 80090f0: 887b ldrh r3, [r7, #2] 80090f2: f003 0302 and.w r3, r3, #2 80090f6: 2b00 cmp r3, #0 80090f8: d003 beq.n 8009102 { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; 80090fa: 68fb ldr r3, [r7, #12] 80090fc: f043 03f4 orr.w r3, r3, #244 @ 0xf4 8009100: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 8009102: 887b ldrh r3, [r7, #2] 8009104: 2b10 cmp r3, #16 8009106: d103 bne.n 8009110 { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8009108: 68fb ldr r3, [r7, #12] 800910a: f043 0390 orr.w r3, r3, #144 @ 0x90 800910e: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 8009110: 887b ldrh r3, [r7, #2] 8009112: 2b20 cmp r3, #32 8009114: d133 bne.n 800917e { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 8009116: 68fb ldr r3, [r7, #12] 8009118: f043 0320 orr.w r3, r3, #32 800911c: 60fb str r3, [r7, #12] if (InterruptRequest == I2C_XFER_CPLT_IT) 800911e: e02e b.n 800917e } #if defined(HAL_DMA_MODULE_ENABLED) else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8009120: f9b7 3002 ldrsh.w r3, [r7, #2] 8009124: 2b00 cmp r3, #0 8009126: da03 bge.n 8009130 { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8009128: 68fb ldr r3, [r7, #12] 800912a: f043 03b8 orr.w r3, r3, #184 @ 0xb8 800912e: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 8009130: 887b ldrh r3, [r7, #2] 8009132: f003 0301 and.w r3, r3, #1 8009136: 2b00 cmp r3, #0 8009138: d003 beq.n 8009142 { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; 800913a: 68fb ldr r3, [r7, #12] 800913c: f043 03f2 orr.w r3, r3, #242 @ 0xf2 8009140: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8009142: 887b ldrh r3, [r7, #2] 8009144: f003 0302 and.w r3, r3, #2 8009148: 2b00 cmp r3, #0 800914a: d003 beq.n 8009154 { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; 800914c: 68fb ldr r3, [r7, #12] 800914e: f043 03f4 orr.w r3, r3, #244 @ 0xf4 8009152: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 8009154: 887b ldrh r3, [r7, #2] 8009156: 2b10 cmp r3, #16 8009158: d103 bne.n 8009162 { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 800915a: 68fb ldr r3, [r7, #12] 800915c: f043 0390 orr.w r3, r3, #144 @ 0x90 8009160: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 8009162: 887b ldrh r3, [r7, #2] 8009164: 2b20 cmp r3, #32 8009166: d103 bne.n 8009170 { /* Enable STOP interrupts */ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); 8009168: 68fb ldr r3, [r7, #12] 800916a: f043 0360 orr.w r3, r3, #96 @ 0x60 800916e: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 8009170: 887b ldrh r3, [r7, #2] 8009172: 2b40 cmp r3, #64 @ 0x40 8009174: d103 bne.n 800917e { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 8009176: 68fb ldr r3, [r7, #12] 8009178: f043 0340 orr.w r3, r3, #64 @ 0x40 800917c: 60fb str r3, [r7, #12] #endif /* HAL_DMA_MODULE_ENABLED */ /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ __HAL_I2C_ENABLE_IT(hi2c, tmpisr); 800917e: 687b ldr r3, [r7, #4] 8009180: 681b ldr r3, [r3, #0] 8009182: 6819 ldr r1, [r3, #0] 8009184: 687b ldr r3, [r7, #4] 8009186: 681b ldr r3, [r3, #0] 8009188: 68fa ldr r2, [r7, #12] 800918a: 430a orrs r2, r1 800918c: 601a str r2, [r3, #0] } 800918e: bf00 nop 8009190: 3714 adds r7, #20 8009192: 46bd mov sp, r7 8009194: f85d 7b04 ldr.w r7, [sp], #4 8009198: 4770 bx lr 800919a: bf00 nop 800919c: 08007ed7 .word 0x08007ed7 80091a0: 0800831d .word 0x0800831d 80091a4: 080080bd .word 0x080080bd 080091a8 : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 80091a8: b480 push {r7} 80091aa: b085 sub sp, #20 80091ac: af00 add r7, sp, #0 80091ae: 6078 str r0, [r7, #4] 80091b0: 460b mov r3, r1 80091b2: 807b strh r3, [r7, #2] uint32_t tmpisr = 0U; 80091b4: 2300 movs r3, #0 80091b6: 60fb str r3, [r7, #12] if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 80091b8: 887b ldrh r3, [r7, #2] 80091ba: f003 0301 and.w r3, r3, #1 80091be: 2b00 cmp r3, #0 80091c0: d00f beq.n 80091e2 { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; 80091c2: 68fb ldr r3, [r7, #12] 80091c4: f043 0342 orr.w r3, r3, #66 @ 0x42 80091c8: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 80091ca: 687b ldr r3, [r7, #4] 80091cc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80091d0: b2db uxtb r3, r3 80091d2: f003 0328 and.w r3, r3, #40 @ 0x28 80091d6: 2b28 cmp r3, #40 @ 0x28 80091d8: d003 beq.n 80091e2 { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 80091da: 68fb ldr r3, [r7, #12] 80091dc: f043 03b0 orr.w r3, r3, #176 @ 0xb0 80091e0: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 80091e2: 887b ldrh r3, [r7, #2] 80091e4: f003 0302 and.w r3, r3, #2 80091e8: 2b00 cmp r3, #0 80091ea: d00f beq.n 800920c { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; 80091ec: 68fb ldr r3, [r7, #12] 80091ee: f043 0344 orr.w r3, r3, #68 @ 0x44 80091f2: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 80091f4: 687b ldr r3, [r7, #4] 80091f6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 80091fa: b2db uxtb r3, r3 80091fc: f003 0328 and.w r3, r3, #40 @ 0x28 8009200: 2b28 cmp r3, #40 @ 0x28 8009202: d003 beq.n 800920c { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8009204: 68fb ldr r3, [r7, #12] 8009206: f043 03b0 orr.w r3, r3, #176 @ 0xb0 800920a: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 800920c: f9b7 3002 ldrsh.w r3, [r7, #2] 8009210: 2b00 cmp r3, #0 8009212: da03 bge.n 800921c { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8009214: 68fb ldr r3, [r7, #12] 8009216: f043 03b8 orr.w r3, r3, #184 @ 0xb8 800921a: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 800921c: 887b ldrh r3, [r7, #2] 800921e: 2b10 cmp r3, #16 8009220: d103 bne.n 800922a { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8009222: 68fb ldr r3, [r7, #12] 8009224: f043 0390 orr.w r3, r3, #144 @ 0x90 8009228: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 800922a: 887b ldrh r3, [r7, #2] 800922c: 2b20 cmp r3, #32 800922e: d103 bne.n 8009238 { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 8009230: 68fb ldr r3, [r7, #12] 8009232: f043 0320 orr.w r3, r3, #32 8009236: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 8009238: 887b ldrh r3, [r7, #2] 800923a: 2b40 cmp r3, #64 @ 0x40 800923c: d103 bne.n 8009246 { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 800923e: 68fb ldr r3, [r7, #12] 8009240: f043 0340 orr.w r3, r3, #64 @ 0x40 8009244: 60fb str r3, [r7, #12] } /* Disable interrupts only at the end */ /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); 8009246: 687b ldr r3, [r7, #4] 8009248: 681b ldr r3, [r3, #0] 800924a: 6819 ldr r1, [r3, #0] 800924c: 68fb ldr r3, [r7, #12] 800924e: 43da mvns r2, r3 8009250: 687b ldr r3, [r7, #4] 8009252: 681b ldr r3, [r3, #0] 8009254: 400a ands r2, r1 8009256: 601a str r2, [r3, #0] } 8009258: bf00 nop 800925a: 3714 adds r7, #20 800925c: 46bd mov sp, r7 800925e: f85d 7b04 ldr.w r7, [sp], #4 8009262: 4770 bx lr 08009264 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8009264: b480 push {r7} 8009266: b083 sub sp, #12 8009268: af00 add r7, sp, #0 800926a: 6078 str r0, [r7, #4] 800926c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 800926e: 687b ldr r3, [r7, #4] 8009270: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8009274: b2db uxtb r3, r3 8009276: 2b20 cmp r3, #32 8009278: d138 bne.n 80092ec { /* Process Locked */ __HAL_LOCK(hi2c); 800927a: 687b ldr r3, [r7, #4] 800927c: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8009280: 2b01 cmp r3, #1 8009282: d101 bne.n 8009288 8009284: 2302 movs r3, #2 8009286: e032 b.n 80092ee 8009288: 687b ldr r3, [r7, #4] 800928a: 2201 movs r2, #1 800928c: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 8009290: 687b ldr r3, [r7, #4] 8009292: 2224 movs r2, #36 @ 0x24 8009294: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8009298: 687b ldr r3, [r7, #4] 800929a: 681b ldr r3, [r3, #0] 800929c: 681a ldr r2, [r3, #0] 800929e: 687b ldr r3, [r7, #4] 80092a0: 681b ldr r3, [r3, #0] 80092a2: f022 0201 bic.w r2, r2, #1 80092a6: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 80092a8: 687b ldr r3, [r7, #4] 80092aa: 681b ldr r3, [r3, #0] 80092ac: 681a ldr r2, [r3, #0] 80092ae: 687b ldr r3, [r7, #4] 80092b0: 681b ldr r3, [r3, #0] 80092b2: f422 5280 bic.w r2, r2, #4096 @ 0x1000 80092b6: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 80092b8: 687b ldr r3, [r7, #4] 80092ba: 681b ldr r3, [r3, #0] 80092bc: 6819 ldr r1, [r3, #0] 80092be: 687b ldr r3, [r7, #4] 80092c0: 681b ldr r3, [r3, #0] 80092c2: 683a ldr r2, [r7, #0] 80092c4: 430a orrs r2, r1 80092c6: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 80092c8: 687b ldr r3, [r7, #4] 80092ca: 681b ldr r3, [r3, #0] 80092cc: 681a ldr r2, [r3, #0] 80092ce: 687b ldr r3, [r7, #4] 80092d0: 681b ldr r3, [r3, #0] 80092d2: f042 0201 orr.w r2, r2, #1 80092d6: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 80092d8: 687b ldr r3, [r7, #4] 80092da: 2220 movs r2, #32 80092dc: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80092e0: 687b ldr r3, [r7, #4] 80092e2: 2200 movs r2, #0 80092e4: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 80092e8: 2300 movs r3, #0 80092ea: e000 b.n 80092ee } else { return HAL_BUSY; 80092ec: 2302 movs r3, #2 } } 80092ee: 4618 mov r0, r3 80092f0: 370c adds r7, #12 80092f2: 46bd mov sp, r7 80092f4: f85d 7b04 ldr.w r7, [sp], #4 80092f8: 4770 bx lr 080092fa : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 80092fa: b480 push {r7} 80092fc: b085 sub sp, #20 80092fe: af00 add r7, sp, #0 8009300: 6078 str r0, [r7, #4] 8009302: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8009304: 687b ldr r3, [r7, #4] 8009306: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800930a: b2db uxtb r3, r3 800930c: 2b20 cmp r3, #32 800930e: d139 bne.n 8009384 { /* Process Locked */ __HAL_LOCK(hi2c); 8009310: 687b ldr r3, [r7, #4] 8009312: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8009316: 2b01 cmp r3, #1 8009318: d101 bne.n 800931e 800931a: 2302 movs r3, #2 800931c: e033 b.n 8009386 800931e: 687b ldr r3, [r7, #4] 8009320: 2201 movs r2, #1 8009322: f883 2040 strb.w r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_BUSY; 8009326: 687b ldr r3, [r7, #4] 8009328: 2224 movs r2, #36 @ 0x24 800932a: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 800932e: 687b ldr r3, [r7, #4] 8009330: 681b ldr r3, [r3, #0] 8009332: 681a ldr r2, [r3, #0] 8009334: 687b ldr r3, [r7, #4] 8009336: 681b ldr r3, [r3, #0] 8009338: f022 0201 bic.w r2, r2, #1 800933c: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 800933e: 687b ldr r3, [r7, #4] 8009340: 681b ldr r3, [r3, #0] 8009342: 681b ldr r3, [r3, #0] 8009344: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 8009346: 68fb ldr r3, [r7, #12] 8009348: f423 6370 bic.w r3, r3, #3840 @ 0xf00 800934c: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 800934e: 683b ldr r3, [r7, #0] 8009350: 021b lsls r3, r3, #8 8009352: 68fa ldr r2, [r7, #12] 8009354: 4313 orrs r3, r2 8009356: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 8009358: 687b ldr r3, [r7, #4] 800935a: 681b ldr r3, [r3, #0] 800935c: 68fa ldr r2, [r7, #12] 800935e: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8009360: 687b ldr r3, [r7, #4] 8009362: 681b ldr r3, [r3, #0] 8009364: 681a ldr r2, [r3, #0] 8009366: 687b ldr r3, [r7, #4] 8009368: 681b ldr r3, [r3, #0] 800936a: f042 0201 orr.w r2, r2, #1 800936e: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8009370: 687b ldr r3, [r7, #4] 8009372: 2220 movs r2, #32 8009374: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8009378: 687b ldr r3, [r7, #4] 800937a: 2200 movs r2, #0 800937c: f883 2040 strb.w r2, [r3, #64] @ 0x40 return HAL_OK; 8009380: 2300 movs r3, #0 8009382: e000 b.n 8009386 } else { return HAL_BUSY; 8009384: 2302 movs r3, #2 } } 8009386: 4618 mov r0, r3 8009388: 3714 adds r7, #20 800938a: 46bd mov sp, r7 800938c: f85d 7b04 ldr.w r7, [sp], #4 8009390: 4770 bx lr ... 08009394 : * @brief Initialize the IPCC peripheral. * @param hipcc IPCC handle * @retval HAL status */ HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc) { 8009394: b580 push {r7, lr} 8009396: b084 sub sp, #16 8009398: af00 add r7, sp, #0 800939a: 6078 str r0, [r7, #4] HAL_StatusTypeDef err = HAL_OK; 800939c: 2300 movs r3, #0 800939e: 73fb strb r3, [r7, #15] /* Check the IPCC handle allocation */ if (hipcc != NULL) 80093a0: 687b ldr r3, [r7, #4] 80093a2: 2b00 cmp r3, #0 80093a4: d01e beq.n 80093e4 { /* Check the parameters */ assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance)); IPCC_CommonTypeDef *currentInstance = IPCC_C1; 80093a6: 4b13 ldr r3, [pc, #76] @ (80093f4 ) 80093a8: 60bb str r3, [r7, #8] if (hipcc->State == HAL_IPCC_STATE_RESET) 80093aa: 687b ldr r3, [r7, #4] 80093ac: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 80093b0: b2db uxtb r3, r3 80093b2: 2b00 cmp r3, #0 80093b4: d102 bne.n 80093bc { /* Init the low level hardware : CLOCK, NVIC */ HAL_IPCC_MspInit(hipcc); 80093b6: 6878 ldr r0, [r7, #4] 80093b8: f7fc fee4 bl 8006184 } /* Reset all registers of the current cpu to default state */ IPCC_Reset_Register(currentInstance); 80093bc: 68b8 ldr r0, [r7, #8] 80093be: f000 f85b bl 8009478 /* Activate the interrupts */ currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE); 80093c2: 68bb ldr r3, [r7, #8] 80093c4: 681b ldr r3, [r3, #0] 80093c6: f043 1201 orr.w r2, r3, #65537 @ 0x10001 80093ca: 68bb ldr r3, [r7, #8] 80093cc: 601a str r2, [r3, #0] /* Clear callback pointers */ IPCC_SetDefaultCallbacks(hipcc); 80093ce: 6878 ldr r0, [r7, #4] 80093d0: f000 f82c bl 800942c /* Reset all callback notification request */ hipcc->callbackRequest = 0; 80093d4: 687b ldr r3, [r7, #4] 80093d6: 2200 movs r2, #0 80093d8: 635a str r2, [r3, #52] @ 0x34 hipcc->State = HAL_IPCC_STATE_READY; 80093da: 687b ldr r3, [r7, #4] 80093dc: 2201 movs r2, #1 80093de: f883 2038 strb.w r2, [r3, #56] @ 0x38 80093e2: e001 b.n 80093e8 } else { err = HAL_ERROR; 80093e4: 2301 movs r3, #1 80093e6: 73fb strb r3, [r7, #15] } return err; 80093e8: 7bfb ldrb r3, [r7, #15] } 80093ea: 4618 mov r0, r3 80093ec: 3710 adds r7, #16 80093ee: 46bd mov sp, r7 80093f0: bd80 pop {r7, pc} 80093f2: bf00 nop 80093f4: 58000c00 .word 0x58000c00 080093f8 : * @arg IPCC_CHANNEL_5: IPCC Channel 5 * @arg IPCC_CHANNEL_6: IPCC Channel 6 * @param ChannelDir Channel direction */ __weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) { 80093f8: b480 push {r7} 80093fa: b085 sub sp, #20 80093fc: af00 add r7, sp, #0 80093fe: 60f8 str r0, [r7, #12] 8009400: 60b9 str r1, [r7, #8] 8009402: 4613 mov r3, r2 8009404: 71fb strb r3, [r7, #7] UNUSED(ChannelDir); /* NOTE : This function should not be modified, when the callback is needed, the HAL_IPCC_RxCallback can be implemented in the user file */ } 8009406: bf00 nop 8009408: 3714 adds r7, #20 800940a: 46bd mov sp, r7 800940c: f85d 7b04 ldr.w r7, [sp], #4 8009410: 4770 bx lr 08009412 : * @arg IPCC_CHANNEL_5: IPCC Channel 5 * @arg IPCC_CHANNEL_6: IPCC Channel 6 * @param ChannelDir Channel direction */ __weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) { 8009412: b480 push {r7} 8009414: b085 sub sp, #20 8009416: af00 add r7, sp, #0 8009418: 60f8 str r0, [r7, #12] 800941a: 60b9 str r1, [r7, #8] 800941c: 4613 mov r3, r2 800941e: 71fb strb r3, [r7, #7] UNUSED(ChannelDir); /* NOTE : This function should not be modified, when the callback is needed, the HAL_IPCC_TxCallback can be implemented in the user file */ } 8009420: bf00 nop 8009422: 3714 adds r7, #20 8009424: 46bd mov sp, r7 8009426: f85d 7b04 ldr.w r7, [sp], #4 800942a: 4770 bx lr 0800942c : /** * @brief Reset all callbacks of the handle to NULL. * @param hipcc IPCC handle */ void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc) { 800942c: b480 push {r7} 800942e: b085 sub sp, #20 8009430: af00 add r7, sp, #0 8009432: 6078 str r0, [r7, #4] uint32_t i; /* Set all callbacks to default */ for (i = 0; i < IPCC_CHANNEL_NUMBER; i++) 8009434: 2300 movs r3, #0 8009436: 60fb str r3, [r7, #12] 8009438: e00f b.n 800945a { hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback; 800943a: 687a ldr r2, [r7, #4] 800943c: 68fb ldr r3, [r7, #12] 800943e: 009b lsls r3, r3, #2 8009440: 4413 add r3, r2 8009442: 4a0b ldr r2, [pc, #44] @ (8009470 ) 8009444: 605a str r2, [r3, #4] hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback; 8009446: 687a ldr r2, [r7, #4] 8009448: 68fb ldr r3, [r7, #12] 800944a: 3306 adds r3, #6 800944c: 009b lsls r3, r3, #2 800944e: 4413 add r3, r2 8009450: 4a08 ldr r2, [pc, #32] @ (8009474 ) 8009452: 605a str r2, [r3, #4] for (i = 0; i < IPCC_CHANNEL_NUMBER; i++) 8009454: 68fb ldr r3, [r7, #12] 8009456: 3301 adds r3, #1 8009458: 60fb str r3, [r7, #12] 800945a: 68fb ldr r3, [r7, #12] 800945c: 2b05 cmp r3, #5 800945e: d9ec bls.n 800943a } } 8009460: bf00 nop 8009462: bf00 nop 8009464: 3714 adds r7, #20 8009466: 46bd mov sp, r7 8009468: f85d 7b04 ldr.w r7, [sp], #4 800946c: 4770 bx lr 800946e: bf00 nop 8009470: 080093f9 .word 0x080093f9 8009474: 08009413 .word 0x08009413 08009478 : /** * @brief Reset IPCC register to default value for the concerned instance. * @param Instance pointer to register */ void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance) { 8009478: b480 push {r7} 800947a: b083 sub sp, #12 800947c: af00 add r7, sp, #0 800947e: 6078 str r0, [r7, #4] /* Disable RX and TX interrupts */ Instance->CR = 0x00000000U; 8009480: 687b ldr r3, [r7, #4] 8009482: 2200 movs r2, #0 8009484: 601a str r2, [r3, #0] /* Mask RX and TX interrupts */ Instance->MR = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF); 8009486: 687b ldr r3, [r7, #4] 8009488: f04f 123f mov.w r2, #4128831 @ 0x3f003f 800948c: 605a str r2, [r3, #4] /* Clear RX status */ Instance->SCR = IPCC_ALL_RX_BUF; 800948e: 687b ldr r3, [r7, #4] 8009490: 223f movs r2, #63 @ 0x3f 8009492: 609a str r2, [r3, #8] } 8009494: bf00 nop 8009496: 370c adds r7, #12 8009498: 46bd mov sp, r7 800949a: f85d 7b04 ldr.w r7, [sp], #4 800949e: 4770 bx lr 080094a0 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 80094a0: b580 push {r7, lr} 80094a2: b084 sub sp, #16 80094a4: af00 add r7, sp, #0 80094a6: 6078 str r0, [r7, #4] uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 80094a8: 687b ldr r3, [r7, #4] 80094aa: 2b00 cmp r3, #0 80094ac: d101 bne.n 80094b2 { return HAL_ERROR; 80094ae: 2301 movs r3, #1 80094b0: e0c0 b.n 8009634 } /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); if (hpcd->State == HAL_PCD_STATE_RESET) 80094b2: 687b ldr r3, [r7, #4] 80094b4: f893 3291 ldrb.w r3, [r3, #657] @ 0x291 80094b8: b2db uxtb r3, r3 80094ba: 2b00 cmp r3, #0 80094bc: d106 bne.n 80094cc { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 80094be: 687b ldr r3, [r7, #4] 80094c0: 2200 movs r2, #0 80094c2: f883 2290 strb.w r2, [r3, #656] @ 0x290 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 80094c6: 6878 ldr r0, [r7, #4] 80094c8: f00f fbfe bl 8018cc8 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 80094cc: 687b ldr r3, [r7, #4] 80094ce: 2203 movs r2, #3 80094d0: f883 2291 strb.w r2, [r3, #657] @ 0x291 /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 80094d4: 687b ldr r3, [r7, #4] 80094d6: 681b ldr r3, [r3, #0] 80094d8: 4618 mov r0, r3 80094da: f005 fe7e bl 800f1da /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80094de: 2300 movs r3, #0 80094e0: 73fb strb r3, [r7, #15] 80094e2: e03e b.n 8009562 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 80094e4: 7bfa ldrb r2, [r7, #15] 80094e6: 6879 ldr r1, [r7, #4] 80094e8: 4613 mov r3, r2 80094ea: 009b lsls r3, r3, #2 80094ec: 4413 add r3, r2 80094ee: 00db lsls r3, r3, #3 80094f0: 440b add r3, r1 80094f2: 3311 adds r3, #17 80094f4: 2201 movs r2, #1 80094f6: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 80094f8: 7bfa ldrb r2, [r7, #15] 80094fa: 6879 ldr r1, [r7, #4] 80094fc: 4613 mov r3, r2 80094fe: 009b lsls r3, r3, #2 8009500: 4413 add r3, r2 8009502: 00db lsls r3, r3, #3 8009504: 440b add r3, r1 8009506: 3310 adds r3, #16 8009508: 7bfa ldrb r2, [r7, #15] 800950a: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 800950c: 7bfa ldrb r2, [r7, #15] 800950e: 6879 ldr r1, [r7, #4] 8009510: 4613 mov r3, r2 8009512: 009b lsls r3, r3, #2 8009514: 4413 add r3, r2 8009516: 00db lsls r3, r3, #3 8009518: 440b add r3, r1 800951a: 3313 adds r3, #19 800951c: 2200 movs r2, #0 800951e: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8009520: 7bfa ldrb r2, [r7, #15] 8009522: 6879 ldr r1, [r7, #4] 8009524: 4613 mov r3, r2 8009526: 009b lsls r3, r3, #2 8009528: 4413 add r3, r2 800952a: 00db lsls r3, r3, #3 800952c: 440b add r3, r1 800952e: 3320 adds r3, #32 8009530: 2200 movs r2, #0 8009532: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8009534: 7bfa ldrb r2, [r7, #15] 8009536: 6879 ldr r1, [r7, #4] 8009538: 4613 mov r3, r2 800953a: 009b lsls r3, r3, #2 800953c: 4413 add r3, r2 800953e: 00db lsls r3, r3, #3 8009540: 440b add r3, r1 8009542: 3324 adds r3, #36 @ 0x24 8009544: 2200 movs r2, #0 8009546: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8009548: 7bfb ldrb r3, [r7, #15] 800954a: 6879 ldr r1, [r7, #4] 800954c: 1c5a adds r2, r3, #1 800954e: 4613 mov r3, r2 8009550: 009b lsls r3, r3, #2 8009552: 4413 add r3, r2 8009554: 00db lsls r3, r3, #3 8009556: 440b add r3, r1 8009558: 2200 movs r2, #0 800955a: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800955c: 7bfb ldrb r3, [r7, #15] 800955e: 3301 adds r3, #1 8009560: 73fb strb r3, [r7, #15] 8009562: 687b ldr r3, [r7, #4] 8009564: 791b ldrb r3, [r3, #4] 8009566: 7bfa ldrb r2, [r7, #15] 8009568: 429a cmp r2, r3 800956a: d3bb bcc.n 80094e4 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800956c: 2300 movs r3, #0 800956e: 73fb strb r3, [r7, #15] 8009570: e044 b.n 80095fc { hpcd->OUT_ep[i].is_in = 0U; 8009572: 7bfa ldrb r2, [r7, #15] 8009574: 6879 ldr r1, [r7, #4] 8009576: 4613 mov r3, r2 8009578: 009b lsls r3, r3, #2 800957a: 4413 add r3, r2 800957c: 00db lsls r3, r3, #3 800957e: 440b add r3, r1 8009580: f203 1351 addw r3, r3, #337 @ 0x151 8009584: 2200 movs r2, #0 8009586: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8009588: 7bfa ldrb r2, [r7, #15] 800958a: 6879 ldr r1, [r7, #4] 800958c: 4613 mov r3, r2 800958e: 009b lsls r3, r3, #2 8009590: 4413 add r3, r2 8009592: 00db lsls r3, r3, #3 8009594: 440b add r3, r1 8009596: f503 73a8 add.w r3, r3, #336 @ 0x150 800959a: 7bfa ldrb r2, [r7, #15] 800959c: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 800959e: 7bfa ldrb r2, [r7, #15] 80095a0: 6879 ldr r1, [r7, #4] 80095a2: 4613 mov r3, r2 80095a4: 009b lsls r3, r3, #2 80095a6: 4413 add r3, r2 80095a8: 00db lsls r3, r3, #3 80095aa: 440b add r3, r1 80095ac: f203 1353 addw r3, r3, #339 @ 0x153 80095b0: 2200 movs r2, #0 80095b2: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 80095b4: 7bfa ldrb r2, [r7, #15] 80095b6: 6879 ldr r1, [r7, #4] 80095b8: 4613 mov r3, r2 80095ba: 009b lsls r3, r3, #2 80095bc: 4413 add r3, r2 80095be: 00db lsls r3, r3, #3 80095c0: 440b add r3, r1 80095c2: f503 73b0 add.w r3, r3, #352 @ 0x160 80095c6: 2200 movs r2, #0 80095c8: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 80095ca: 7bfa ldrb r2, [r7, #15] 80095cc: 6879 ldr r1, [r7, #4] 80095ce: 4613 mov r3, r2 80095d0: 009b lsls r3, r3, #2 80095d2: 4413 add r3, r2 80095d4: 00db lsls r3, r3, #3 80095d6: 440b add r3, r1 80095d8: f503 73b2 add.w r3, r3, #356 @ 0x164 80095dc: 2200 movs r2, #0 80095de: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 80095e0: 7bfa ldrb r2, [r7, #15] 80095e2: 6879 ldr r1, [r7, #4] 80095e4: 4613 mov r3, r2 80095e6: 009b lsls r3, r3, #2 80095e8: 4413 add r3, r2 80095ea: 00db lsls r3, r3, #3 80095ec: 440b add r3, r1 80095ee: f503 73b4 add.w r3, r3, #360 @ 0x168 80095f2: 2200 movs r2, #0 80095f4: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80095f6: 7bfb ldrb r3, [r7, #15] 80095f8: 3301 adds r3, #1 80095fa: 73fb strb r3, [r7, #15] 80095fc: 687b ldr r3, [r7, #4] 80095fe: 791b ldrb r3, [r3, #4] 8009600: 7bfa ldrb r2, [r7, #15] 8009602: 429a cmp r2, r3 8009604: d3b5 bcc.n 8009572 } /* Init Device */ (void)USB_DevInit(hpcd->Instance, hpcd->Init); 8009606: 687b ldr r3, [r7, #4] 8009608: 6818 ldr r0, [r3, #0] 800960a: 687b ldr r3, [r7, #4] 800960c: 3304 adds r3, #4 800960e: e893 0006 ldmia.w r3, {r1, r2} 8009612: f005 fdfd bl 800f210 hpcd->USB_Address = 0U; 8009616: 687b ldr r3, [r7, #4] 8009618: 2200 movs r2, #0 800961a: 731a strb r2, [r3, #12] hpcd->State = HAL_PCD_STATE_READY; 800961c: 687b ldr r3, [r7, #4] 800961e: 2201 movs r2, #1 8009620: f883 2291 strb.w r2, [r3, #657] @ 0x291 /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8009624: 687b ldr r3, [r7, #4] 8009626: 7a9b ldrb r3, [r3, #10] 8009628: 2b01 cmp r3, #1 800962a: d102 bne.n 8009632 { (void)HAL_PCDEx_ActivateLPM(hpcd); 800962c: 6878 ldr r0, [r7, #4] 800962e: f001 fc4f bl 800aed0 } return HAL_OK; 8009632: 2300 movs r3, #0 } 8009634: 4618 mov r0, r3 8009636: 3710 adds r7, #16 8009638: 46bd mov sp, r7 800963a: bd80 pop {r7, pc} 0800963c : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 800963c: b580 push {r7, lr} 800963e: b082 sub sp, #8 8009640: af00 add r7, sp, #0 8009642: 6078 str r0, [r7, #4] __HAL_LOCK(hpcd); 8009644: 687b ldr r3, [r7, #4] 8009646: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 800964a: 2b01 cmp r3, #1 800964c: d101 bne.n 8009652 800964e: 2302 movs r3, #2 8009650: e012 b.n 8009678 8009652: 687b ldr r3, [r7, #4] 8009654: 2201 movs r2, #1 8009656: f883 2290 strb.w r2, [r3, #656] @ 0x290 __HAL_PCD_ENABLE(hpcd); 800965a: 687b ldr r3, [r7, #4] 800965c: 681b ldr r3, [r3, #0] 800965e: 4618 mov r0, r3 8009660: f005 fda4 bl 800f1ac (void)USB_DevConnect(hpcd->Instance); 8009664: 687b ldr r3, [r7, #4] 8009666: 681b ldr r3, [r3, #0] 8009668: 4618 mov r0, r3 800966a: f007 fb81 bl 8010d70 __HAL_UNLOCK(hpcd); 800966e: 687b ldr r3, [r7, #4] 8009670: 2200 movs r2, #0 8009672: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8009676: 2300 movs r3, #0 } 8009678: 4618 mov r0, r3 800967a: 3708 adds r7, #8 800967c: 46bd mov sp, r7 800967e: bd80 pop {r7, pc} 08009680 : * @brief This function handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 8009680: b580 push {r7, lr} 8009682: b084 sub sp, #16 8009684: af00 add r7, sp, #0 8009686: 6078 str r0, [r7, #4] uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); 8009688: 687b ldr r3, [r7, #4] 800968a: 681b ldr r3, [r3, #0] 800968c: 4618 mov r0, r3 800968e: f007 fb86 bl 8010d9e 8009692: 60f8 str r0, [r7, #12] if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) 8009694: 68fb ldr r3, [r7, #12] 8009696: f403 4300 and.w r3, r3, #32768 @ 0x8000 800969a: 2b00 cmp r3, #0 800969c: d003 beq.n 80096a6 { /* servicing of the endpoint correct transfer interrupt */ /* clear of the CTR flag into the sub */ (void)PCD_EP_ISR_Handler(hpcd); 800969e: 6878 ldr r0, [r7, #4] 80096a0: f000 fb06 bl 8009cb0 return; 80096a4: e110 b.n 80098c8 } if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) 80096a6: 68fb ldr r3, [r7, #12] 80096a8: f403 6380 and.w r3, r3, #1024 @ 0x400 80096ac: 2b00 cmp r3, #0 80096ae: d013 beq.n 80096d8 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); 80096b0: 687b ldr r3, [r7, #4] 80096b2: 681b ldr r3, [r3, #0] 80096b4: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80096b8: b29a uxth r2, r3 80096ba: 687b ldr r3, [r7, #4] 80096bc: 681b ldr r3, [r3, #0] 80096be: f422 6280 bic.w r2, r2, #1024 @ 0x400 80096c2: b292 uxth r2, r2 80096c4: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 80096c8: 6878 ldr r0, [r7, #4] 80096ca: f00f fbb0 bl 8018e2e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ (void)HAL_PCD_SetAddress(hpcd, 0U); 80096ce: 2100 movs r1, #0 80096d0: 6878 ldr r0, [r7, #4] 80096d2: f000 f8fc bl 80098ce return; 80096d6: e0f7 b.n 80098c8 } if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) 80096d8: 68fb ldr r3, [r7, #12] 80096da: f403 4380 and.w r3, r3, #16384 @ 0x4000 80096de: 2b00 cmp r3, #0 80096e0: d00c beq.n 80096fc { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); 80096e2: 687b ldr r3, [r7, #4] 80096e4: 681b ldr r3, [r3, #0] 80096e6: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80096ea: b29a uxth r2, r3 80096ec: 687b ldr r3, [r7, #4] 80096ee: 681b ldr r3, [r3, #0] 80096f0: f422 4280 bic.w r2, r2, #16384 @ 0x4000 80096f4: b292 uxth r2, r2 80096f6: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 80096fa: e0e5 b.n 80098c8 } if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) 80096fc: 68fb ldr r3, [r7, #12] 80096fe: f403 5300 and.w r3, r3, #8192 @ 0x2000 8009702: 2b00 cmp r3, #0 8009704: d00c beq.n 8009720 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); 8009706: 687b ldr r3, [r7, #4] 8009708: 681b ldr r3, [r3, #0] 800970a: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 800970e: b29a uxth r2, r3 8009710: 687b ldr r3, [r7, #4] 8009712: 681b ldr r3, [r3, #0] 8009714: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8009718: b292 uxth r2, r2 800971a: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 800971e: e0d3 b.n 80098c8 } if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) 8009720: 68fb ldr r3, [r7, #12] 8009722: f403 5380 and.w r3, r3, #4096 @ 0x1000 8009726: 2b00 cmp r3, #0 8009728: d034 beq.n 8009794 { hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE); 800972a: 687b ldr r3, [r7, #4] 800972c: 681b ldr r3, [r3, #0] 800972e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8009732: b29a uxth r2, r3 8009734: 687b ldr r3, [r7, #4] 8009736: 681b ldr r3, [r3, #0] 8009738: f022 0204 bic.w r2, r2, #4 800973c: b292 uxth r2, r2 800973e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); 8009742: 687b ldr r3, [r7, #4] 8009744: 681b ldr r3, [r3, #0] 8009746: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 800974a: b29a uxth r2, r3 800974c: 687b ldr r3, [r7, #4] 800974e: 681b ldr r3, [r3, #0] 8009750: f022 0208 bic.w r2, r2, #8 8009754: b292 uxth r2, r2 8009756: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 if (hpcd->LPM_State == LPM_L1) 800975a: 687b ldr r3, [r7, #4] 800975c: f893 32c8 ldrb.w r3, [r3, #712] @ 0x2c8 8009760: 2b01 cmp r3, #1 8009762: d107 bne.n 8009774 { hpcd->LPM_State = LPM_L0; 8009764: 687b ldr r3, [r7, #4] 8009766: 2200 movs r2, #0 8009768: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 800976c: 2100 movs r1, #0 800976e: 6878 ldr r0, [r7, #4] 8009770: f00f fd52 bl 8019218 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 8009774: 6878 ldr r0, [r7, #4] 8009776: f00f fb93 bl 8018ea0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); 800977a: 687b ldr r3, [r7, #4] 800977c: 681b ldr r3, [r3, #0] 800977e: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8009782: b29a uxth r2, r3 8009784: 687b ldr r3, [r7, #4] 8009786: 681b ldr r3, [r3, #0] 8009788: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800978c: b292 uxth r2, r2 800978e: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 8009792: e099 b.n 80098c8 } if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) 8009794: 68fb ldr r3, [r7, #12] 8009796: f403 6300 and.w r3, r3, #2048 @ 0x800 800979a: 2b00 cmp r3, #0 800979c: d027 beq.n 80097ee { /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; 800979e: 687b ldr r3, [r7, #4] 80097a0: 681b ldr r3, [r3, #0] 80097a2: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 80097a6: b29a uxth r2, r3 80097a8: 687b ldr r3, [r7, #4] 80097aa: 681b ldr r3, [r3, #0] 80097ac: f042 0208 orr.w r2, r2, #8 80097b0: b292 uxth r2, r2 80097b2: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); 80097b6: 687b ldr r3, [r7, #4] 80097b8: 681b ldr r3, [r3, #0] 80097ba: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80097be: b29a uxth r2, r3 80097c0: 687b ldr r3, [r7, #4] 80097c2: 681b ldr r3, [r3, #0] 80097c4: f422 6200 bic.w r2, r2, #2048 @ 0x800 80097c8: b292 uxth r2, r2 80097ca: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; 80097ce: 687b ldr r3, [r7, #4] 80097d0: 681b ldr r3, [r3, #0] 80097d2: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 80097d6: b29a uxth r2, r3 80097d8: 687b ldr r3, [r7, #4] 80097da: 681b ldr r3, [r3, #0] 80097dc: f042 0204 orr.w r2, r2, #4 80097e0: b292 uxth r2, r2 80097e2: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 80097e6: 6878 ldr r0, [r7, #4] 80097e8: f00f fb40 bl 8018e6c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ return; 80097ec: e06c b.n 80098c8 } /* Handle LPM Interrupt */ if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) 80097ee: 68fb ldr r3, [r7, #12] 80097f0: f003 0380 and.w r3, r3, #128 @ 0x80 80097f4: 2b00 cmp r3, #0 80097f6: d040 beq.n 800987a { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); 80097f8: 687b ldr r3, [r7, #4] 80097fa: 681b ldr r3, [r3, #0] 80097fc: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8009800: b29a uxth r2, r3 8009802: 687b ldr r3, [r7, #4] 8009804: 681b ldr r3, [r3, #0] 8009806: f022 0280 bic.w r2, r2, #128 @ 0x80 800980a: b292 uxth r2, r2 800980c: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 if (hpcd->LPM_State == LPM_L0) 8009810: 687b ldr r3, [r7, #4] 8009812: f893 32c8 ldrb.w r3, [r3, #712] @ 0x2c8 8009816: 2b00 cmp r3, #0 8009818: d12b bne.n 8009872 { /* Force suspend and low-power mode before going to L1 state*/ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; 800981a: 687b ldr r3, [r7, #4] 800981c: 681b ldr r3, [r3, #0] 800981e: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 8009822: b29a uxth r2, r3 8009824: 687b ldr r3, [r7, #4] 8009826: 681b ldr r3, [r3, #0] 8009828: f042 0204 orr.w r2, r2, #4 800982c: b292 uxth r2, r2 800982e: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; 8009832: 687b ldr r3, [r7, #4] 8009834: 681b ldr r3, [r3, #0] 8009836: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 800983a: b29a uxth r2, r3 800983c: 687b ldr r3, [r7, #4] 800983e: 681b ldr r3, [r3, #0] 8009840: f042 0208 orr.w r2, r2, #8 8009844: b292 uxth r2, r2 8009846: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 hpcd->LPM_State = LPM_L1; 800984a: 687b ldr r3, [r7, #4] 800984c: 2201 movs r2, #1 800984e: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8 hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; 8009852: 687b ldr r3, [r7, #4] 8009854: 681b ldr r3, [r3, #0] 8009856: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 800985a: b29b uxth r3, r3 800985c: 089b lsrs r3, r3, #2 800985e: f003 023c and.w r2, r3, #60 @ 0x3c 8009862: 687b ldr r3, [r7, #4] 8009864: f8c3 22cc str.w r2, [r3, #716] @ 0x2cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 8009868: 2101 movs r1, #1 800986a: 6878 ldr r0, [r7, #4] 800986c: f00f fcd4 bl 8019218 #else HAL_PCD_SuspendCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } return; 8009870: e02a b.n 80098c8 HAL_PCD_SuspendCallback(hpcd); 8009872: 6878 ldr r0, [r7, #4] 8009874: f00f fafa bl 8018e6c return; 8009878: e026 b.n 80098c8 } if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) 800987a: 68fb ldr r3, [r7, #12] 800987c: f403 7300 and.w r3, r3, #512 @ 0x200 8009880: 2b00 cmp r3, #0 8009882: d00f beq.n 80098a4 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); 8009884: 687b ldr r3, [r7, #4] 8009886: 681b ldr r3, [r3, #0] 8009888: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 800988c: b29a uxth r2, r3 800988e: 687b ldr r3, [r7, #4] 8009890: 681b ldr r3, [r3, #0] 8009892: f422 7200 bic.w r2, r2, #512 @ 0x200 8009896: b292 uxth r2, r2 8009898: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 800989c: 6878 ldr r0, [r7, #4] 800989e: f00f fab8 bl 8018e12 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ return; 80098a2: e011 b.n 80098c8 } if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) 80098a4: 68fb ldr r3, [r7, #12] 80098a6: f403 7380 and.w r3, r3, #256 @ 0x100 80098aa: 2b00 cmp r3, #0 80098ac: d00c beq.n 80098c8 { /* clear ESOF flag in ISTR */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); 80098ae: 687b ldr r3, [r7, #4] 80098b0: 681b ldr r3, [r3, #0] 80098b2: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 80098b6: b29a uxth r2, r3 80098b8: 687b ldr r3, [r7, #4] 80098ba: 681b ldr r3, [r3, #0] 80098bc: f422 7280 bic.w r2, r2, #256 @ 0x100 80098c0: b292 uxth r2, r2 80098c2: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 return; 80098c6: bf00 nop } } 80098c8: 3710 adds r7, #16 80098ca: 46bd mov sp, r7 80098cc: bd80 pop {r7, pc} 080098ce : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 80098ce: b580 push {r7, lr} 80098d0: b082 sub sp, #8 80098d2: af00 add r7, sp, #0 80098d4: 6078 str r0, [r7, #4] 80098d6: 460b mov r3, r1 80098d8: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 80098da: 687b ldr r3, [r7, #4] 80098dc: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 80098e0: 2b01 cmp r3, #1 80098e2: d101 bne.n 80098e8 80098e4: 2302 movs r3, #2 80098e6: e012 b.n 800990e 80098e8: 687b ldr r3, [r7, #4] 80098ea: 2201 movs r2, #1 80098ec: f883 2290 strb.w r2, [r3, #656] @ 0x290 hpcd->USB_Address = address; 80098f0: 687b ldr r3, [r7, #4] 80098f2: 78fa ldrb r2, [r7, #3] 80098f4: 731a strb r2, [r3, #12] (void)USB_SetDevAddress(hpcd->Instance, address); 80098f6: 687b ldr r3, [r7, #4] 80098f8: 681b ldr r3, [r3, #0] 80098fa: 78fa ldrb r2, [r7, #3] 80098fc: 4611 mov r1, r2 80098fe: 4618 mov r0, r3 8009900: f007 fa22 bl 8010d48 __HAL_UNLOCK(hpcd); 8009904: 687b ldr r3, [r7, #4] 8009906: 2200 movs r2, #0 8009908: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 800990c: 2300 movs r3, #0 } 800990e: 4618 mov r0, r3 8009910: 3708 adds r7, #8 8009912: 46bd mov sp, r7 8009914: bd80 pop {r7, pc} 08009916 : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 8009916: b580 push {r7, lr} 8009918: b084 sub sp, #16 800991a: af00 add r7, sp, #0 800991c: 6078 str r0, [r7, #4] 800991e: 4608 mov r0, r1 8009920: 4611 mov r1, r2 8009922: 461a mov r2, r3 8009924: 4603 mov r3, r0 8009926: 70fb strb r3, [r7, #3] 8009928: 460b mov r3, r1 800992a: 803b strh r3, [r7, #0] 800992c: 4613 mov r3, r2 800992e: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 8009930: 2300 movs r3, #0 8009932: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8009934: f997 3003 ldrsb.w r3, [r7, #3] 8009938: 2b00 cmp r3, #0 800993a: da0e bge.n 800995a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800993c: 78fb ldrb r3, [r7, #3] 800993e: f003 0207 and.w r2, r3, #7 8009942: 4613 mov r3, r2 8009944: 009b lsls r3, r3, #2 8009946: 4413 add r3, r2 8009948: 00db lsls r3, r3, #3 800994a: 3310 adds r3, #16 800994c: 687a ldr r2, [r7, #4] 800994e: 4413 add r3, r2 8009950: 60fb str r3, [r7, #12] ep->is_in = 1U; 8009952: 68fb ldr r3, [r7, #12] 8009954: 2201 movs r2, #1 8009956: 705a strb r2, [r3, #1] 8009958: e00e b.n 8009978 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 800995a: 78fb ldrb r3, [r7, #3] 800995c: f003 0207 and.w r2, r3, #7 8009960: 4613 mov r3, r2 8009962: 009b lsls r3, r3, #2 8009964: 4413 add r3, r2 8009966: 00db lsls r3, r3, #3 8009968: f503 73a8 add.w r3, r3, #336 @ 0x150 800996c: 687a ldr r2, [r7, #4] 800996e: 4413 add r3, r2 8009970: 60fb str r3, [r7, #12] ep->is_in = 0U; 8009972: 68fb ldr r3, [r7, #12] 8009974: 2200 movs r2, #0 8009976: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8009978: 78fb ldrb r3, [r7, #3] 800997a: f003 0307 and.w r3, r3, #7 800997e: b2da uxtb r2, r3 8009980: 68fb ldr r3, [r7, #12] 8009982: 701a strb r2, [r3, #0] ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; 8009984: 883b ldrh r3, [r7, #0] 8009986: f3c3 020a ubfx r2, r3, #0, #11 800998a: 68fb ldr r3, [r7, #12] 800998c: 611a str r2, [r3, #16] ep->type = ep_type; 800998e: 68fb ldr r3, [r7, #12] 8009990: 78ba ldrb r2, [r7, #2] 8009992: 70da strb r2, [r3, #3] /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8009994: 78bb ldrb r3, [r7, #2] 8009996: 2b02 cmp r3, #2 8009998: d102 bne.n 80099a0 { ep->data_pid_start = 0U; 800999a: 68fb ldr r3, [r7, #12] 800999c: 2200 movs r2, #0 800999e: 711a strb r2, [r3, #4] } __HAL_LOCK(hpcd); 80099a0: 687b ldr r3, [r7, #4] 80099a2: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 80099a6: 2b01 cmp r3, #1 80099a8: d101 bne.n 80099ae 80099aa: 2302 movs r3, #2 80099ac: e00e b.n 80099cc 80099ae: 687b ldr r3, [r7, #4] 80099b0: 2201 movs r2, #1 80099b2: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_ActivateEndpoint(hpcd->Instance, ep); 80099b6: 687b ldr r3, [r7, #4] 80099b8: 681b ldr r3, [r3, #0] 80099ba: 68f9 ldr r1, [r7, #12] 80099bc: 4618 mov r0, r3 80099be: f005 fc45 bl 800f24c __HAL_UNLOCK(hpcd); 80099c2: 687b ldr r3, [r7, #4] 80099c4: 2200 movs r2, #0 80099c6: f883 2290 strb.w r2, [r3, #656] @ 0x290 return ret; 80099ca: 7afb ldrb r3, [r7, #11] } 80099cc: 4618 mov r0, r3 80099ce: 3710 adds r7, #16 80099d0: 46bd mov sp, r7 80099d2: bd80 pop {r7, pc} 080099d4 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80099d4: b580 push {r7, lr} 80099d6: b084 sub sp, #16 80099d8: af00 add r7, sp, #0 80099da: 6078 str r0, [r7, #4] 80099dc: 460b mov r3, r1 80099de: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 80099e0: f997 3003 ldrsb.w r3, [r7, #3] 80099e4: 2b00 cmp r3, #0 80099e6: da0e bge.n 8009a06 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80099e8: 78fb ldrb r3, [r7, #3] 80099ea: f003 0207 and.w r2, r3, #7 80099ee: 4613 mov r3, r2 80099f0: 009b lsls r3, r3, #2 80099f2: 4413 add r3, r2 80099f4: 00db lsls r3, r3, #3 80099f6: 3310 adds r3, #16 80099f8: 687a ldr r2, [r7, #4] 80099fa: 4413 add r3, r2 80099fc: 60fb str r3, [r7, #12] ep->is_in = 1U; 80099fe: 68fb ldr r3, [r7, #12] 8009a00: 2201 movs r2, #1 8009a02: 705a strb r2, [r3, #1] 8009a04: e00e b.n 8009a24 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8009a06: 78fb ldrb r3, [r7, #3] 8009a08: f003 0207 and.w r2, r3, #7 8009a0c: 4613 mov r3, r2 8009a0e: 009b lsls r3, r3, #2 8009a10: 4413 add r3, r2 8009a12: 00db lsls r3, r3, #3 8009a14: f503 73a8 add.w r3, r3, #336 @ 0x150 8009a18: 687a ldr r2, [r7, #4] 8009a1a: 4413 add r3, r2 8009a1c: 60fb str r3, [r7, #12] ep->is_in = 0U; 8009a1e: 68fb ldr r3, [r7, #12] 8009a20: 2200 movs r2, #0 8009a22: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8009a24: 78fb ldrb r3, [r7, #3] 8009a26: f003 0307 and.w r3, r3, #7 8009a2a: b2da uxtb r2, r3 8009a2c: 68fb ldr r3, [r7, #12] 8009a2e: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8009a30: 687b ldr r3, [r7, #4] 8009a32: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8009a36: 2b01 cmp r3, #1 8009a38: d101 bne.n 8009a3e 8009a3a: 2302 movs r3, #2 8009a3c: e00e b.n 8009a5c 8009a3e: 687b ldr r3, [r7, #4] 8009a40: 2201 movs r2, #1 8009a42: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8009a46: 687b ldr r3, [r7, #4] 8009a48: 681b ldr r3, [r3, #0] 8009a4a: 68f9 ldr r1, [r7, #12] 8009a4c: 4618 mov r0, r3 8009a4e: f006 f8e5 bl 800fc1c __HAL_UNLOCK(hpcd); 8009a52: 687b ldr r3, [r7, #4] 8009a54: 2200 movs r2, #0 8009a56: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8009a5a: 2300 movs r3, #0 } 8009a5c: 4618 mov r0, r3 8009a5e: 3710 adds r7, #16 8009a60: 46bd mov sp, r7 8009a62: bd80 pop {r7, pc} 08009a64 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8009a64: b580 push {r7, lr} 8009a66: b086 sub sp, #24 8009a68: af00 add r7, sp, #0 8009a6a: 60f8 str r0, [r7, #12] 8009a6c: 607a str r2, [r7, #4] 8009a6e: 603b str r3, [r7, #0] 8009a70: 460b mov r3, r1 8009a72: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8009a74: 7afb ldrb r3, [r7, #11] 8009a76: f003 0207 and.w r2, r3, #7 8009a7a: 4613 mov r3, r2 8009a7c: 009b lsls r3, r3, #2 8009a7e: 4413 add r3, r2 8009a80: 00db lsls r3, r3, #3 8009a82: f503 73a8 add.w r3, r3, #336 @ 0x150 8009a86: 68fa ldr r2, [r7, #12] 8009a88: 4413 add r3, r2 8009a8a: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8009a8c: 697b ldr r3, [r7, #20] 8009a8e: 687a ldr r2, [r7, #4] 8009a90: 615a str r2, [r3, #20] ep->xfer_len = len; 8009a92: 697b ldr r3, [r7, #20] 8009a94: 683a ldr r2, [r7, #0] 8009a96: 619a str r2, [r3, #24] ep->xfer_count = 0U; 8009a98: 697b ldr r3, [r7, #20] 8009a9a: 2200 movs r2, #0 8009a9c: 61da str r2, [r3, #28] ep->is_in = 0U; 8009a9e: 697b ldr r3, [r7, #20] 8009aa0: 2200 movs r2, #0 8009aa2: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8009aa4: 7afb ldrb r3, [r7, #11] 8009aa6: f003 0307 and.w r3, r3, #7 8009aaa: b2da uxtb r2, r3 8009aac: 697b ldr r3, [r7, #20] 8009aae: 701a strb r2, [r3, #0] (void)USB_EPStartXfer(hpcd->Instance, ep); 8009ab0: 68fb ldr r3, [r7, #12] 8009ab2: 681b ldr r3, [r3, #0] 8009ab4: 6979 ldr r1, [r7, #20] 8009ab6: 4618 mov r0, r3 8009ab8: f006 fa9d bl 800fff6 return HAL_OK; 8009abc: 2300 movs r3, #0 } 8009abe: 4618 mov r0, r3 8009ac0: 3718 adds r7, #24 8009ac2: 46bd mov sp, r7 8009ac4: bd80 pop {r7, pc} 08009ac6 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval Data Size */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { 8009ac6: b480 push {r7} 8009ac8: b083 sub sp, #12 8009aca: af00 add r7, sp, #0 8009acc: 6078 str r0, [r7, #4] 8009ace: 460b mov r3, r1 8009ad0: 70fb strb r3, [r7, #3] return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; 8009ad2: 78fb ldrb r3, [r7, #3] 8009ad4: f003 0207 and.w r2, r3, #7 8009ad8: 6879 ldr r1, [r7, #4] 8009ada: 4613 mov r3, r2 8009adc: 009b lsls r3, r3, #2 8009ade: 4413 add r3, r2 8009ae0: 00db lsls r3, r3, #3 8009ae2: 440b add r3, r1 8009ae4: f503 73b6 add.w r3, r3, #364 @ 0x16c 8009ae8: 681b ldr r3, [r3, #0] } 8009aea: 4618 mov r0, r3 8009aec: 370c adds r7, #12 8009aee: 46bd mov sp, r7 8009af0: f85d 7b04 ldr.w r7, [sp], #4 8009af4: 4770 bx lr 08009af6 : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8009af6: b580 push {r7, lr} 8009af8: b086 sub sp, #24 8009afa: af00 add r7, sp, #0 8009afc: 60f8 str r0, [r7, #12] 8009afe: 607a str r2, [r7, #4] 8009b00: 603b str r3, [r7, #0] 8009b02: 460b mov r3, r1 8009b04: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8009b06: 7afb ldrb r3, [r7, #11] 8009b08: f003 0207 and.w r2, r3, #7 8009b0c: 4613 mov r3, r2 8009b0e: 009b lsls r3, r3, #2 8009b10: 4413 add r3, r2 8009b12: 00db lsls r3, r3, #3 8009b14: 3310 adds r3, #16 8009b16: 68fa ldr r2, [r7, #12] 8009b18: 4413 add r3, r2 8009b1a: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8009b1c: 697b ldr r3, [r7, #20] 8009b1e: 687a ldr r2, [r7, #4] 8009b20: 615a str r2, [r3, #20] ep->xfer_len = len; 8009b22: 697b ldr r3, [r7, #20] 8009b24: 683a ldr r2, [r7, #0] 8009b26: 619a str r2, [r3, #24] ep->xfer_fill_db = 1U; 8009b28: 697b ldr r3, [r7, #20] 8009b2a: 2201 movs r2, #1 8009b2c: f883 2024 strb.w r2, [r3, #36] @ 0x24 ep->xfer_len_db = len; 8009b30: 697b ldr r3, [r7, #20] 8009b32: 683a ldr r2, [r7, #0] 8009b34: 621a str r2, [r3, #32] ep->xfer_count = 0U; 8009b36: 697b ldr r3, [r7, #20] 8009b38: 2200 movs r2, #0 8009b3a: 61da str r2, [r3, #28] ep->is_in = 1U; 8009b3c: 697b ldr r3, [r7, #20] 8009b3e: 2201 movs r2, #1 8009b40: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8009b42: 7afb ldrb r3, [r7, #11] 8009b44: f003 0307 and.w r3, r3, #7 8009b48: b2da uxtb r2, r3 8009b4a: 697b ldr r3, [r7, #20] 8009b4c: 701a strb r2, [r3, #0] (void)USB_EPStartXfer(hpcd->Instance, ep); 8009b4e: 68fb ldr r3, [r7, #12] 8009b50: 681b ldr r3, [r3, #0] 8009b52: 6979 ldr r1, [r7, #20] 8009b54: 4618 mov r0, r3 8009b56: f006 fa4e bl 800fff6 return HAL_OK; 8009b5a: 2300 movs r3, #0 } 8009b5c: 4618 mov r0, r3 8009b5e: 3718 adds r7, #24 8009b60: 46bd mov sp, r7 8009b62: bd80 pop {r7, pc} 08009b64 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8009b64: b580 push {r7, lr} 8009b66: b084 sub sp, #16 8009b68: af00 add r7, sp, #0 8009b6a: 6078 str r0, [r7, #4] 8009b6c: 460b mov r3, r1 8009b6e: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 8009b70: 78fb ldrb r3, [r7, #3] 8009b72: f003 0307 and.w r3, r3, #7 8009b76: 687a ldr r2, [r7, #4] 8009b78: 7912 ldrb r2, [r2, #4] 8009b7a: 4293 cmp r3, r2 8009b7c: d901 bls.n 8009b82 { return HAL_ERROR; 8009b7e: 2301 movs r3, #1 8009b80: e03e b.n 8009c00 } if ((0x80U & ep_addr) == 0x80U) 8009b82: f997 3003 ldrsb.w r3, [r7, #3] 8009b86: 2b00 cmp r3, #0 8009b88: da0e bge.n 8009ba8 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8009b8a: 78fb ldrb r3, [r7, #3] 8009b8c: f003 0207 and.w r2, r3, #7 8009b90: 4613 mov r3, r2 8009b92: 009b lsls r3, r3, #2 8009b94: 4413 add r3, r2 8009b96: 00db lsls r3, r3, #3 8009b98: 3310 adds r3, #16 8009b9a: 687a ldr r2, [r7, #4] 8009b9c: 4413 add r3, r2 8009b9e: 60fb str r3, [r7, #12] ep->is_in = 1U; 8009ba0: 68fb ldr r3, [r7, #12] 8009ba2: 2201 movs r2, #1 8009ba4: 705a strb r2, [r3, #1] 8009ba6: e00c b.n 8009bc2 } else { ep = &hpcd->OUT_ep[ep_addr]; 8009ba8: 78fa ldrb r2, [r7, #3] 8009baa: 4613 mov r3, r2 8009bac: 009b lsls r3, r3, #2 8009bae: 4413 add r3, r2 8009bb0: 00db lsls r3, r3, #3 8009bb2: f503 73a8 add.w r3, r3, #336 @ 0x150 8009bb6: 687a ldr r2, [r7, #4] 8009bb8: 4413 add r3, r2 8009bba: 60fb str r3, [r7, #12] ep->is_in = 0U; 8009bbc: 68fb ldr r3, [r7, #12] 8009bbe: 2200 movs r2, #0 8009bc0: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8009bc2: 68fb ldr r3, [r7, #12] 8009bc4: 2201 movs r2, #1 8009bc6: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8009bc8: 78fb ldrb r3, [r7, #3] 8009bca: f003 0307 and.w r3, r3, #7 8009bce: b2da uxtb r2, r3 8009bd0: 68fb ldr r3, [r7, #12] 8009bd2: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8009bd4: 687b ldr r3, [r7, #4] 8009bd6: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8009bda: 2b01 cmp r3, #1 8009bdc: d101 bne.n 8009be2 8009bde: 2302 movs r3, #2 8009be0: e00e b.n 8009c00 8009be2: 687b ldr r3, [r7, #4] 8009be4: 2201 movs r2, #1 8009be6: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_EPSetStall(hpcd->Instance, ep); 8009bea: 687b ldr r3, [r7, #4] 8009bec: 681b ldr r3, [r3, #0] 8009bee: 68f9 ldr r1, [r7, #12] 8009bf0: 4618 mov r0, r3 8009bf2: f006 ffaf bl 8010b54 __HAL_UNLOCK(hpcd); 8009bf6: 687b ldr r3, [r7, #4] 8009bf8: 2200 movs r2, #0 8009bfa: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8009bfe: 2300 movs r3, #0 } 8009c00: 4618 mov r0, r3 8009c02: 3710 adds r7, #16 8009c04: 46bd mov sp, r7 8009c06: bd80 pop {r7, pc} 08009c08 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8009c08: b580 push {r7, lr} 8009c0a: b084 sub sp, #16 8009c0c: af00 add r7, sp, #0 8009c0e: 6078 str r0, [r7, #4] 8009c10: 460b mov r3, r1 8009c12: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8009c14: 78fb ldrb r3, [r7, #3] 8009c16: f003 030f and.w r3, r3, #15 8009c1a: 687a ldr r2, [r7, #4] 8009c1c: 7912 ldrb r2, [r2, #4] 8009c1e: 4293 cmp r3, r2 8009c20: d901 bls.n 8009c26 { return HAL_ERROR; 8009c22: 2301 movs r3, #1 8009c24: e040 b.n 8009ca8 } if ((0x80U & ep_addr) == 0x80U) 8009c26: f997 3003 ldrsb.w r3, [r7, #3] 8009c2a: 2b00 cmp r3, #0 8009c2c: da0e bge.n 8009c4c { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8009c2e: 78fb ldrb r3, [r7, #3] 8009c30: f003 0207 and.w r2, r3, #7 8009c34: 4613 mov r3, r2 8009c36: 009b lsls r3, r3, #2 8009c38: 4413 add r3, r2 8009c3a: 00db lsls r3, r3, #3 8009c3c: 3310 adds r3, #16 8009c3e: 687a ldr r2, [r7, #4] 8009c40: 4413 add r3, r2 8009c42: 60fb str r3, [r7, #12] ep->is_in = 1U; 8009c44: 68fb ldr r3, [r7, #12] 8009c46: 2201 movs r2, #1 8009c48: 705a strb r2, [r3, #1] 8009c4a: e00e b.n 8009c6a } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8009c4c: 78fb ldrb r3, [r7, #3] 8009c4e: f003 0207 and.w r2, r3, #7 8009c52: 4613 mov r3, r2 8009c54: 009b lsls r3, r3, #2 8009c56: 4413 add r3, r2 8009c58: 00db lsls r3, r3, #3 8009c5a: f503 73a8 add.w r3, r3, #336 @ 0x150 8009c5e: 687a ldr r2, [r7, #4] 8009c60: 4413 add r3, r2 8009c62: 60fb str r3, [r7, #12] ep->is_in = 0U; 8009c64: 68fb ldr r3, [r7, #12] 8009c66: 2200 movs r2, #0 8009c68: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8009c6a: 68fb ldr r3, [r7, #12] 8009c6c: 2200 movs r2, #0 8009c6e: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8009c70: 78fb ldrb r3, [r7, #3] 8009c72: f003 0307 and.w r3, r3, #7 8009c76: b2da uxtb r2, r3 8009c78: 68fb ldr r3, [r7, #12] 8009c7a: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8009c7c: 687b ldr r3, [r7, #4] 8009c7e: f893 3290 ldrb.w r3, [r3, #656] @ 0x290 8009c82: 2b01 cmp r3, #1 8009c84: d101 bne.n 8009c8a 8009c86: 2302 movs r3, #2 8009c88: e00e b.n 8009ca8 8009c8a: 687b ldr r3, [r7, #4] 8009c8c: 2201 movs r2, #1 8009c8e: f883 2290 strb.w r2, [r3, #656] @ 0x290 (void)USB_EPClearStall(hpcd->Instance, ep); 8009c92: 687b ldr r3, [r7, #4] 8009c94: 681b ldr r3, [r3, #0] 8009c96: 68f9 ldr r1, [r7, #12] 8009c98: 4618 mov r0, r3 8009c9a: f006 ffac bl 8010bf6 __HAL_UNLOCK(hpcd); 8009c9e: 687b ldr r3, [r7, #4] 8009ca0: 2200 movs r2, #0 8009ca2: f883 2290 strb.w r2, [r3, #656] @ 0x290 return HAL_OK; 8009ca6: 2300 movs r3, #0 } 8009ca8: 4618 mov r0, r3 8009caa: 3710 adds r7, #16 8009cac: 46bd mov sp, r7 8009cae: bd80 pop {r7, pc} 08009cb0 : * @brief This function handles PCD Endpoint interrupt request. * @param hpcd PCD handle * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { 8009cb0: b580 push {r7, lr} 8009cb2: b094 sub sp, #80 @ 0x50 8009cb4: af00 add r7, sp, #0 8009cb6: 6078 str r0, [r7, #4] #if (USE_USB_DOUBLE_BUFFER != 1U) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) 8009cb8: e374 b.n 800a3a4 { wIstr = hpcd->Instance->ISTR; 8009cba: 687b ldr r3, [r7, #4] 8009cbc: 681b ldr r3, [r3, #0] 8009cbe: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8009cc2: f8a7 3042 strh.w r3, [r7, #66] @ 0x42 /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); 8009cc6: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42 8009cca: b2db uxtb r3, r3 8009ccc: f003 030f and.w r3, r3, #15 8009cd0: f887 3041 strb.w r3, [r7, #65] @ 0x41 if (epindex == 0U) 8009cd4: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 8009cd8: 2b00 cmp r3, #0 8009cda: f040 8143 bne.w 8009f64 { /* Decode and service control endpoint interrupt */ /* DIR bit = origin of the interrupt */ if ((wIstr & USB_ISTR_DIR) == 0U) 8009cde: f8b7 3042 ldrh.w r3, [r7, #66] @ 0x42 8009ce2: f003 0310 and.w r3, r3, #16 8009ce6: 2b00 cmp r3, #0 8009ce8: d14c bne.n 8009d84 { /* DIR = 0 */ /* DIR = 0 => IN int */ /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); 8009cea: 687b ldr r3, [r7, #4] 8009cec: 681b ldr r3, [r3, #0] 8009cee: 881b ldrh r3, [r3, #0] 8009cf0: b29b uxth r3, r3 8009cf2: f423 43e1 bic.w r3, r3, #28800 @ 0x7080 8009cf6: f023 0370 bic.w r3, r3, #112 @ 0x70 8009cfa: 817b strh r3, [r7, #10] 8009cfc: 687b ldr r3, [r7, #4] 8009cfe: 681a ldr r2, [r3, #0] 8009d00: 897b ldrh r3, [r7, #10] 8009d02: ea6f 4343 mvn.w r3, r3, lsl #17 8009d06: ea6f 4353 mvn.w r3, r3, lsr #17 8009d0a: b29b uxth r3, r3 8009d0c: 8013 strh r3, [r2, #0] ep = &hpcd->IN_ep[0]; 8009d0e: 687b ldr r3, [r7, #4] 8009d10: 3310 adds r3, #16 8009d12: 64bb str r3, [r7, #72] @ 0x48 ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); 8009d14: 687b ldr r3, [r7, #4] 8009d16: 681b ldr r3, [r3, #0] 8009d18: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009d1c: b29b uxth r3, r3 8009d1e: 461a mov r2, r3 8009d20: 6cbb ldr r3, [r7, #72] @ 0x48 8009d22: 781b ldrb r3, [r3, #0] 8009d24: 00db lsls r3, r3, #3 8009d26: 4413 add r3, r2 8009d28: 687a ldr r2, [r7, #4] 8009d2a: 6812 ldr r2, [r2, #0] 8009d2c: 4413 add r3, r2 8009d2e: f203 4302 addw r3, r3, #1026 @ 0x402 8009d32: 881b ldrh r3, [r3, #0] 8009d34: f3c3 0209 ubfx r2, r3, #0, #10 8009d38: 6cbb ldr r3, [r7, #72] @ 0x48 8009d3a: 61da str r2, [r3, #28] ep->xfer_buff += ep->xfer_count; 8009d3c: 6cbb ldr r3, [r7, #72] @ 0x48 8009d3e: 695a ldr r2, [r3, #20] 8009d40: 6cbb ldr r3, [r7, #72] @ 0x48 8009d42: 69db ldr r3, [r3, #28] 8009d44: 441a add r2, r3 8009d46: 6cbb ldr r3, [r7, #72] @ 0x48 8009d48: 615a str r2, [r3, #20] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, 0U); #else HAL_PCD_DataInStageCallback(hpcd, 0U); 8009d4a: 2100 movs r1, #0 8009d4c: 6878 ldr r0, [r7, #4] 8009d4e: f00f f846 bl 8018dde #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) 8009d52: 687b ldr r3, [r7, #4] 8009d54: 7b1b ldrb r3, [r3, #12] 8009d56: b2db uxtb r3, r3 8009d58: 2b00 cmp r3, #0 8009d5a: f000 8323 beq.w 800a3a4 8009d5e: 6cbb ldr r3, [r7, #72] @ 0x48 8009d60: 699b ldr r3, [r3, #24] 8009d62: 2b00 cmp r3, #0 8009d64: f040 831e bne.w 800a3a4 { hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); 8009d68: 687b ldr r3, [r7, #4] 8009d6a: 7b1b ldrb r3, [r3, #12] 8009d6c: b2db uxtb r3, r3 8009d6e: f063 037f orn r3, r3, #127 @ 0x7f 8009d72: b2da uxtb r2, r3 8009d74: 687b ldr r3, [r7, #4] 8009d76: 681b ldr r3, [r3, #0] 8009d78: f8a3 204c strh.w r2, [r3, #76] @ 0x4c hpcd->USB_Address = 0U; 8009d7c: 687b ldr r3, [r7, #4] 8009d7e: 2200 movs r2, #0 8009d80: 731a strb r2, [r3, #12] 8009d82: e30f b.n 800a3a4 { /* DIR = 1 */ /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; 8009d84: 687b ldr r3, [r7, #4] 8009d86: f503 73a8 add.w r3, r3, #336 @ 0x150 8009d8a: 64bb str r3, [r7, #72] @ 0x48 wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); 8009d8c: 687b ldr r3, [r7, #4] 8009d8e: 681b ldr r3, [r3, #0] 8009d90: 881b ldrh r3, [r3, #0] 8009d92: 87fb strh r3, [r7, #62] @ 0x3e if ((wEPVal & USB_EP_SETUP) != 0U) 8009d94: 8ffb ldrh r3, [r7, #62] @ 0x3e 8009d96: f403 6300 and.w r3, r3, #2048 @ 0x800 8009d9a: 2b00 cmp r3, #0 8009d9c: d07b beq.n 8009e96 { /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8009d9e: 687b ldr r3, [r7, #4] 8009da0: 681b ldr r3, [r3, #0] 8009da2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009da6: b29b uxth r3, r3 8009da8: 461a mov r2, r3 8009daa: 6cbb ldr r3, [r7, #72] @ 0x48 8009dac: 781b ldrb r3, [r3, #0] 8009dae: 00db lsls r3, r3, #3 8009db0: 4413 add r3, r2 8009db2: 687a ldr r2, [r7, #4] 8009db4: 6812 ldr r2, [r2, #0] 8009db6: 4413 add r3, r2 8009db8: f203 4306 addw r3, r3, #1030 @ 0x406 8009dbc: 881b ldrh r3, [r3, #0] 8009dbe: f3c3 0209 ubfx r2, r3, #0, #10 8009dc2: 6cbb ldr r3, [r7, #72] @ 0x48 8009dc4: 61da str r2, [r3, #28] if (ep->xfer_count != 8U) 8009dc6: 6cbb ldr r3, [r7, #72] @ 0x48 8009dc8: 69db ldr r3, [r3, #28] 8009dca: 2b08 cmp r3, #8 8009dcc: d044 beq.n 8009e58 { /* Set Stall condition for EP0 IN/OUT */ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); 8009dce: 687b ldr r3, [r7, #4] 8009dd0: 681b ldr r3, [r3, #0] 8009dd2: 881b ldrh r3, [r3, #0] 8009dd4: b29b uxth r3, r3 8009dd6: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8009dda: f023 0370 bic.w r3, r3, #112 @ 0x70 8009dde: 823b strh r3, [r7, #16] 8009de0: 8a3b ldrh r3, [r7, #16] 8009de2: f483 5380 eor.w r3, r3, #4096 @ 0x1000 8009de6: 823b strh r3, [r7, #16] 8009de8: 687b ldr r3, [r7, #4] 8009dea: 681a ldr r2, [r3, #0] 8009dec: 8a3b ldrh r3, [r7, #16] 8009dee: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009df2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009df6: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009dfa: f043 0380 orr.w r3, r3, #128 @ 0x80 8009dfe: b29b uxth r3, r3 8009e00: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); 8009e02: 687b ldr r3, [r7, #4] 8009e04: 681b ldr r3, [r3, #0] 8009e06: 881b ldrh r3, [r3, #0] 8009e08: b29b uxth r3, r3 8009e0a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8009e0e: f023 0340 bic.w r3, r3, #64 @ 0x40 8009e12: 81fb strh r3, [r7, #14] 8009e14: 89fb ldrh r3, [r7, #14] 8009e16: f083 0310 eor.w r3, r3, #16 8009e1a: 81fb strh r3, [r7, #14] 8009e1c: 687b ldr r3, [r7, #4] 8009e1e: 681a ldr r2, [r3, #0] 8009e20: 89fb ldrh r3, [r7, #14] 8009e22: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009e26: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009e2a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009e2e: f043 0380 orr.w r3, r3, #128 @ 0x80 8009e32: b29b uxth r3, r3 8009e34: 8013 strh r3, [r2, #0] /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 8009e36: 687b ldr r3, [r7, #4] 8009e38: 681b ldr r3, [r3, #0] 8009e3a: 881b ldrh r3, [r3, #0] 8009e3c: b29a uxth r2, r3 8009e3e: f640 738f movw r3, #3983 @ 0xf8f 8009e42: 4013 ands r3, r2 8009e44: 81bb strh r3, [r7, #12] 8009e46: 687b ldr r3, [r7, #4] 8009e48: 681b ldr r3, [r3, #0] 8009e4a: 89ba ldrh r2, [r7, #12] 8009e4c: f042 0280 orr.w r2, r2, #128 @ 0x80 8009e50: b292 uxth r2, r2 8009e52: 801a strh r2, [r3, #0] return HAL_OK; 8009e54: 2300 movs r3, #0 8009e56: e2af b.n 800a3b8 } USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, 8009e58: 687b ldr r3, [r7, #4] 8009e5a: 6818 ldr r0, [r3, #0] 8009e5c: 687b ldr r3, [r7, #4] 8009e5e: f503 7126 add.w r1, r3, #664 @ 0x298 8009e62: 6cbb ldr r3, [r7, #72] @ 0x48 8009e64: 88da ldrh r2, [r3, #6] ep->pmaadress, (uint16_t)ep->xfer_count); 8009e66: 6cbb ldr r3, [r7, #72] @ 0x48 8009e68: 69db ldr r3, [r3, #28] USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, 8009e6a: b29b uxth r3, r3 8009e6c: f006 ffea bl 8010e44 /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 8009e70: 687b ldr r3, [r7, #4] 8009e72: 681b ldr r3, [r3, #0] 8009e74: 881b ldrh r3, [r3, #0] 8009e76: b29a uxth r2, r3 8009e78: f640 738f movw r3, #3983 @ 0xf8f 8009e7c: 4013 ands r3, r2 8009e7e: 827b strh r3, [r7, #18] 8009e80: 687b ldr r3, [r7, #4] 8009e82: 681b ldr r3, [r3, #0] 8009e84: 8a7a ldrh r2, [r7, #18] 8009e86: f042 0280 orr.w r2, r2, #128 @ 0x80 8009e8a: b292 uxth r2, r2 8009e8c: 801a strh r2, [r3, #0] /* Process SETUP Packet*/ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 8009e8e: 6878 ldr r0, [r7, #4] 8009e90: f00e ff78 bl 8018d84 8009e94: e286 b.n 800a3a4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else if ((wEPVal & USB_EP_CTR_RX) != 0U) 8009e96: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e 8009e9a: 2b00 cmp r3, #0 8009e9c: f280 8282 bge.w 800a3a4 { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 8009ea0: 687b ldr r3, [r7, #4] 8009ea2: 681b ldr r3, [r3, #0] 8009ea4: 881b ldrh r3, [r3, #0] 8009ea6: b29a uxth r2, r3 8009ea8: f640 738f movw r3, #3983 @ 0xf8f 8009eac: 4013 ands r3, r2 8009eae: 82fb strh r3, [r7, #22] 8009eb0: 687b ldr r3, [r7, #4] 8009eb2: 681b ldr r3, [r3, #0] 8009eb4: 8afa ldrh r2, [r7, #22] 8009eb6: f042 0280 orr.w r2, r2, #128 @ 0x80 8009eba: b292 uxth r2, r2 8009ebc: 801a strh r2, [r3, #0] /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8009ebe: 687b ldr r3, [r7, #4] 8009ec0: 681b ldr r3, [r3, #0] 8009ec2: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009ec6: b29b uxth r3, r3 8009ec8: 461a mov r2, r3 8009eca: 6cbb ldr r3, [r7, #72] @ 0x48 8009ecc: 781b ldrb r3, [r3, #0] 8009ece: 00db lsls r3, r3, #3 8009ed0: 4413 add r3, r2 8009ed2: 687a ldr r2, [r7, #4] 8009ed4: 6812 ldr r2, [r2, #0] 8009ed6: 4413 add r3, r2 8009ed8: f203 4306 addw r3, r3, #1030 @ 0x406 8009edc: 881b ldrh r3, [r3, #0] 8009ede: f3c3 0209 ubfx r2, r3, #0, #10 8009ee2: 6cbb ldr r3, [r7, #72] @ 0x48 8009ee4: 61da str r2, [r3, #28] if (ep->xfer_count == 0U) 8009ee6: 6cbb ldr r3, [r7, #72] @ 0x48 8009ee8: 69db ldr r3, [r3, #28] 8009eea: 2b00 cmp r3, #0 8009eec: d11e bne.n 8009f2c { /* Status phase re-arm for next setup */ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); 8009eee: 687b ldr r3, [r7, #4] 8009ef0: 681b ldr r3, [r3, #0] 8009ef2: 881b ldrh r3, [r3, #0] 8009ef4: b29b uxth r3, r3 8009ef6: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8009efa: f023 0370 bic.w r3, r3, #112 @ 0x70 8009efe: 82bb strh r3, [r7, #20] 8009f00: 8abb ldrh r3, [r7, #20] 8009f02: f483 5380 eor.w r3, r3, #4096 @ 0x1000 8009f06: 82bb strh r3, [r7, #20] 8009f08: 8abb ldrh r3, [r7, #20] 8009f0a: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8009f0e: 82bb strh r3, [r7, #20] 8009f10: 687b ldr r3, [r7, #4] 8009f12: 681a ldr r2, [r3, #0] 8009f14: 8abb ldrh r3, [r7, #20] 8009f16: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8009f1a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8009f1e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8009f22: f043 0380 orr.w r3, r3, #128 @ 0x80 8009f26: b29b uxth r3, r3 8009f28: 8013 strh r3, [r2, #0] 8009f2a: e23b b.n 800a3a4 } else { if (ep->xfer_buff != 0U) 8009f2c: 6cbb ldr r3, [r7, #72] @ 0x48 8009f2e: 695b ldr r3, [r3, #20] 8009f30: 2b00 cmp r3, #0 8009f32: f000 8237 beq.w 800a3a4 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, 8009f36: 687b ldr r3, [r7, #4] 8009f38: 6818 ldr r0, [r3, #0] 8009f3a: 6cbb ldr r3, [r7, #72] @ 0x48 8009f3c: 6959 ldr r1, [r3, #20] 8009f3e: 6cbb ldr r3, [r7, #72] @ 0x48 8009f40: 88da ldrh r2, [r3, #6] ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ 8009f42: 6cbb ldr r3, [r7, #72] @ 0x48 8009f44: 69db ldr r3, [r3, #28] USB_ReadPMA(hpcd->Instance, ep->xfer_buff, 8009f46: b29b uxth r3, r3 8009f48: f006 ff7c bl 8010e44 ep->xfer_buff += ep->xfer_count; 8009f4c: 6cbb ldr r3, [r7, #72] @ 0x48 8009f4e: 695a ldr r2, [r3, #20] 8009f50: 6cbb ldr r3, [r7, #72] @ 0x48 8009f52: 69db ldr r3, [r3, #28] 8009f54: 441a add r2, r3 8009f56: 6cbb ldr r3, [r7, #72] @ 0x48 8009f58: 615a str r2, [r3, #20] /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, 0U); #else HAL_PCD_DataOutStageCallback(hpcd, 0U); 8009f5a: 2100 movs r1, #0 8009f5c: 6878 ldr r0, [r7, #4] 8009f5e: f00e ff23 bl 8018da8 8009f62: e21f b.n 800a3a4 } else { /* Decode and service non control endpoints interrupt */ /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); 8009f64: 687b ldr r3, [r7, #4] 8009f66: 681b ldr r3, [r3, #0] 8009f68: 461a mov r2, r3 8009f6a: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 8009f6e: 009b lsls r3, r3, #2 8009f70: 4413 add r3, r2 8009f72: 881b ldrh r3, [r3, #0] 8009f74: 87fb strh r3, [r7, #62] @ 0x3e if ((wEPVal & USB_EP_CTR_RX) != 0U) 8009f76: f9b7 303e ldrsh.w r3, [r7, #62] @ 0x3e 8009f7a: 2b00 cmp r3, #0 8009f7c: f280 80f5 bge.w 800a16a { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); 8009f80: 687b ldr r3, [r7, #4] 8009f82: 681b ldr r3, [r3, #0] 8009f84: 461a mov r2, r3 8009f86: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 8009f8a: 009b lsls r3, r3, #2 8009f8c: 4413 add r3, r2 8009f8e: 881b ldrh r3, [r3, #0] 8009f90: b29a uxth r2, r3 8009f92: f640 738f movw r3, #3983 @ 0xf8f 8009f96: 4013 ands r3, r2 8009f98: f8a7 3046 strh.w r3, [r7, #70] @ 0x46 8009f9c: 687b ldr r3, [r7, #4] 8009f9e: 681b ldr r3, [r3, #0] 8009fa0: 461a mov r2, r3 8009fa2: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 8009fa6: 009b lsls r3, r3, #2 8009fa8: 4413 add r3, r2 8009faa: f8b7 2046 ldrh.w r2, [r7, #70] @ 0x46 8009fae: f042 0280 orr.w r2, r2, #128 @ 0x80 8009fb2: b292 uxth r2, r2 8009fb4: 801a strh r2, [r3, #0] ep = &hpcd->OUT_ep[epindex]; 8009fb6: f897 2041 ldrb.w r2, [r7, #65] @ 0x41 8009fba: 4613 mov r3, r2 8009fbc: 009b lsls r3, r3, #2 8009fbe: 4413 add r3, r2 8009fc0: 00db lsls r3, r3, #3 8009fc2: f503 73a8 add.w r3, r3, #336 @ 0x150 8009fc6: 687a ldr r2, [r7, #4] 8009fc8: 4413 add r3, r2 8009fca: 64bb str r3, [r7, #72] @ 0x48 /* OUT Single Buffering */ if (ep->doublebuffer == 0U) 8009fcc: 6cbb ldr r3, [r7, #72] @ 0x48 8009fce: 7b1b ldrb r3, [r3, #12] 8009fd0: 2b00 cmp r3, #0 8009fd2: d123 bne.n 800a01c { count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); 8009fd4: 687b ldr r3, [r7, #4] 8009fd6: 681b ldr r3, [r3, #0] 8009fd8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8009fdc: b29b uxth r3, r3 8009fde: 461a mov r2, r3 8009fe0: 6cbb ldr r3, [r7, #72] @ 0x48 8009fe2: 781b ldrb r3, [r3, #0] 8009fe4: 00db lsls r3, r3, #3 8009fe6: 4413 add r3, r2 8009fe8: 687a ldr r2, [r7, #4] 8009fea: 6812 ldr r2, [r2, #0] 8009fec: 4413 add r3, r2 8009fee: f203 4306 addw r3, r3, #1030 @ 0x406 8009ff2: 881b ldrh r3, [r3, #0] 8009ff4: f3c3 0309 ubfx r3, r3, #0, #10 8009ff8: f8a7 304e strh.w r3, [r7, #78] @ 0x4e if (count != 0U) 8009ffc: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a000: 2b00 cmp r3, #0 800a002: f000 808d beq.w 800a120 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); 800a006: 687b ldr r3, [r7, #4] 800a008: 6818 ldr r0, [r3, #0] 800a00a: 6cbb ldr r3, [r7, #72] @ 0x48 800a00c: 6959 ldr r1, [r3, #20] 800a00e: 6cbb ldr r3, [r7, #72] @ 0x48 800a010: 88da ldrh r2, [r3, #6] 800a012: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a016: f006 ff15 bl 8010e44 800a01a: e081 b.n 800a120 } #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* manage double buffer bulk out */ if (ep->type == EP_TYPE_BULK) 800a01c: 6cbb ldr r3, [r7, #72] @ 0x48 800a01e: 78db ldrb r3, [r3, #3] 800a020: 2b02 cmp r3, #2 800a022: d109 bne.n 800a038 { count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); 800a024: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a026: 461a mov r2, r3 800a028: 6cb9 ldr r1, [r7, #72] @ 0x48 800a02a: 6878 ldr r0, [r7, #4] 800a02c: f000 f9c8 bl 800a3c0 800a030: 4603 mov r3, r0 800a032: f8a7 304e strh.w r3, [r7, #78] @ 0x4e 800a036: e073 b.n 800a120 } else /* manage double buffer iso out */ { /* free EP OUT Buffer */ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 800a038: 687b ldr r3, [r7, #4] 800a03a: 681b ldr r3, [r3, #0] 800a03c: 461a mov r2, r3 800a03e: 6cbb ldr r3, [r7, #72] @ 0x48 800a040: 781b ldrb r3, [r3, #0] 800a042: 009b lsls r3, r3, #2 800a044: 4413 add r3, r2 800a046: 881b ldrh r3, [r3, #0] 800a048: b29b uxth r3, r3 800a04a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a04e: f023 0370 bic.w r3, r3, #112 @ 0x70 800a052: f8a7 3044 strh.w r3, [r7, #68] @ 0x44 800a056: 687b ldr r3, [r7, #4] 800a058: 681b ldr r3, [r3, #0] 800a05a: 461a mov r2, r3 800a05c: 6cbb ldr r3, [r7, #72] @ 0x48 800a05e: 781b ldrb r3, [r3, #0] 800a060: 009b lsls r3, r3, #2 800a062: 441a add r2, r3 800a064: f8b7 3044 ldrh.w r3, [r7, #68] @ 0x44 800a068: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a06c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a070: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a074: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a078: b29b uxth r3, r3 800a07a: 8013 strh r3, [r2, #0] if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) 800a07c: 687b ldr r3, [r7, #4] 800a07e: 681b ldr r3, [r3, #0] 800a080: 461a mov r2, r3 800a082: 6cbb ldr r3, [r7, #72] @ 0x48 800a084: 781b ldrb r3, [r3, #0] 800a086: 009b lsls r3, r3, #2 800a088: 4413 add r3, r2 800a08a: 881b ldrh r3, [r3, #0] 800a08c: b29b uxth r3, r3 800a08e: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a092: 2b00 cmp r3, #0 800a094: d022 beq.n 800a0dc { /* read from endpoint BUF0Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 800a096: 687b ldr r3, [r7, #4] 800a098: 681b ldr r3, [r3, #0] 800a09a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a09e: b29b uxth r3, r3 800a0a0: 461a mov r2, r3 800a0a2: 6cbb ldr r3, [r7, #72] @ 0x48 800a0a4: 781b ldrb r3, [r3, #0] 800a0a6: 00db lsls r3, r3, #3 800a0a8: 4413 add r3, r2 800a0aa: 687a ldr r2, [r7, #4] 800a0ac: 6812 ldr r2, [r2, #0] 800a0ae: 4413 add r3, r2 800a0b0: f203 4302 addw r3, r3, #1026 @ 0x402 800a0b4: 881b ldrh r3, [r3, #0] 800a0b6: f3c3 0309 ubfx r3, r3, #0, #10 800a0ba: f8a7 304e strh.w r3, [r7, #78] @ 0x4e if (count != 0U) 800a0be: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a0c2: 2b00 cmp r3, #0 800a0c4: d02c beq.n 800a120 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); 800a0c6: 687b ldr r3, [r7, #4] 800a0c8: 6818 ldr r0, [r3, #0] 800a0ca: 6cbb ldr r3, [r7, #72] @ 0x48 800a0cc: 6959 ldr r1, [r3, #20] 800a0ce: 6cbb ldr r3, [r7, #72] @ 0x48 800a0d0: 891a ldrh r2, [r3, #8] 800a0d2: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a0d6: f006 feb5 bl 8010e44 800a0da: e021 b.n 800a120 } } else { /* read from endpoint BUF1Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 800a0dc: 687b ldr r3, [r7, #4] 800a0de: 681b ldr r3, [r3, #0] 800a0e0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a0e4: b29b uxth r3, r3 800a0e6: 461a mov r2, r3 800a0e8: 6cbb ldr r3, [r7, #72] @ 0x48 800a0ea: 781b ldrb r3, [r3, #0] 800a0ec: 00db lsls r3, r3, #3 800a0ee: 4413 add r3, r2 800a0f0: 687a ldr r2, [r7, #4] 800a0f2: 6812 ldr r2, [r2, #0] 800a0f4: 4413 add r3, r2 800a0f6: f203 4306 addw r3, r3, #1030 @ 0x406 800a0fa: 881b ldrh r3, [r3, #0] 800a0fc: f3c3 0309 ubfx r3, r3, #0, #10 800a100: f8a7 304e strh.w r3, [r7, #78] @ 0x4e if (count != 0U) 800a104: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a108: 2b00 cmp r3, #0 800a10a: d009 beq.n 800a120 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); 800a10c: 687b ldr r3, [r7, #4] 800a10e: 6818 ldr r0, [r3, #0] 800a110: 6cbb ldr r3, [r7, #72] @ 0x48 800a112: 6959 ldr r1, [r3, #20] 800a114: 6cbb ldr r3, [r7, #72] @ 0x48 800a116: 895a ldrh r2, [r3, #10] 800a118: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a11c: f006 fe92 bl 8010e44 } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; 800a120: 6cbb ldr r3, [r7, #72] @ 0x48 800a122: 69da ldr r2, [r3, #28] 800a124: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a128: 441a add r2, r3 800a12a: 6cbb ldr r3, [r7, #72] @ 0x48 800a12c: 61da str r2, [r3, #28] if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) 800a12e: 6cbb ldr r3, [r7, #72] @ 0x48 800a130: 699b ldr r3, [r3, #24] 800a132: 2b00 cmp r3, #0 800a134: d005 beq.n 800a142 800a136: f8b7 204e ldrh.w r2, [r7, #78] @ 0x4e 800a13a: 6cbb ldr r3, [r7, #72] @ 0x48 800a13c: 691b ldr r3, [r3, #16] 800a13e: 429a cmp r2, r3 800a140: d206 bcs.n 800a150 { /* RX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, ep->num); #else HAL_PCD_DataOutStageCallback(hpcd, ep->num); 800a142: 6cbb ldr r3, [r7, #72] @ 0x48 800a144: 781b ldrb r3, [r3, #0] 800a146: 4619 mov r1, r3 800a148: 6878 ldr r0, [r7, #4] 800a14a: f00e fe2d bl 8018da8 800a14e: e00c b.n 800a16a #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { ep->xfer_buff += count; 800a150: 6cbb ldr r3, [r7, #72] @ 0x48 800a152: 695a ldr r2, [r3, #20] 800a154: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a158: 441a add r2, r3 800a15a: 6cbb ldr r3, [r7, #72] @ 0x48 800a15c: 615a str r2, [r3, #20] (void)USB_EPStartXfer(hpcd->Instance, ep); 800a15e: 687b ldr r3, [r7, #4] 800a160: 681b ldr r3, [r3, #0] 800a162: 6cb9 ldr r1, [r7, #72] @ 0x48 800a164: 4618 mov r0, r3 800a166: f005 ff46 bl 800fff6 } } if ((wEPVal & USB_EP_CTR_TX) != 0U) 800a16a: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a16c: f003 0380 and.w r3, r3, #128 @ 0x80 800a170: 2b00 cmp r3, #0 800a172: f000 8117 beq.w 800a3a4 { ep = &hpcd->IN_ep[epindex]; 800a176: f897 2041 ldrb.w r2, [r7, #65] @ 0x41 800a17a: 4613 mov r3, r2 800a17c: 009b lsls r3, r3, #2 800a17e: 4413 add r3, r2 800a180: 00db lsls r3, r3, #3 800a182: 3310 adds r3, #16 800a184: 687a ldr r2, [r7, #4] 800a186: 4413 add r3, r2 800a188: 64bb str r3, [r7, #72] @ 0x48 /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); 800a18a: 687b ldr r3, [r7, #4] 800a18c: 681b ldr r3, [r3, #0] 800a18e: 461a mov r2, r3 800a190: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 800a194: 009b lsls r3, r3, #2 800a196: 4413 add r3, r2 800a198: 881b ldrh r3, [r3, #0] 800a19a: b29b uxth r3, r3 800a19c: f423 43e1 bic.w r3, r3, #28800 @ 0x7080 800a1a0: f023 0370 bic.w r3, r3, #112 @ 0x70 800a1a4: 87bb strh r3, [r7, #60] @ 0x3c 800a1a6: 687b ldr r3, [r7, #4] 800a1a8: 681b ldr r3, [r3, #0] 800a1aa: 461a mov r2, r3 800a1ac: f897 3041 ldrb.w r3, [r7, #65] @ 0x41 800a1b0: 009b lsls r3, r3, #2 800a1b2: 441a add r2, r3 800a1b4: 8fbb ldrh r3, [r7, #60] @ 0x3c 800a1b6: ea6f 4343 mvn.w r3, r3, lsl #17 800a1ba: ea6f 4353 mvn.w r3, r3, lsr #17 800a1be: b29b uxth r3, r3 800a1c0: 8013 strh r3, [r2, #0] if (ep->type == EP_TYPE_ISOC) 800a1c2: 6cbb ldr r3, [r7, #72] @ 0x48 800a1c4: 78db ldrb r3, [r3, #3] 800a1c6: 2b01 cmp r3, #1 800a1c8: f040 80a1 bne.w 800a30e { ep->xfer_len = 0U; 800a1cc: 6cbb ldr r3, [r7, #72] @ 0x48 800a1ce: 2200 movs r2, #0 800a1d0: 619a str r2, [r3, #24] #if (USE_USB_DOUBLE_BUFFER == 1U) if (ep->doublebuffer != 0U) 800a1d2: 6cbb ldr r3, [r7, #72] @ 0x48 800a1d4: 7b1b ldrb r3, [r3, #12] 800a1d6: 2b00 cmp r3, #0 800a1d8: f000 8092 beq.w 800a300 { if ((wEPVal & USB_EP_DTOG_TX) != 0U) 800a1dc: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a1de: f003 0340 and.w r3, r3, #64 @ 0x40 800a1e2: 2b00 cmp r3, #0 800a1e4: d046 beq.n 800a274 { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800a1e6: 6cbb ldr r3, [r7, #72] @ 0x48 800a1e8: 785b ldrb r3, [r3, #1] 800a1ea: 2b00 cmp r3, #0 800a1ec: d126 bne.n 800a23c 800a1ee: 687b ldr r3, [r7, #4] 800a1f0: 681b ldr r3, [r3, #0] 800a1f2: 61fb str r3, [r7, #28] 800a1f4: 687b ldr r3, [r7, #4] 800a1f6: 681b ldr r3, [r3, #0] 800a1f8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a1fc: b29b uxth r3, r3 800a1fe: 461a mov r2, r3 800a200: 69fb ldr r3, [r7, #28] 800a202: 4413 add r3, r2 800a204: 61fb str r3, [r7, #28] 800a206: 6cbb ldr r3, [r7, #72] @ 0x48 800a208: 781b ldrb r3, [r3, #0] 800a20a: 00da lsls r2, r3, #3 800a20c: 69fb ldr r3, [r7, #28] 800a20e: 4413 add r3, r2 800a210: f203 4302 addw r3, r3, #1026 @ 0x402 800a214: 61bb str r3, [r7, #24] 800a216: 69bb ldr r3, [r7, #24] 800a218: 881b ldrh r3, [r3, #0] 800a21a: b29b uxth r3, r3 800a21c: f3c3 0309 ubfx r3, r3, #0, #10 800a220: b29a uxth r2, r3 800a222: 69bb ldr r3, [r7, #24] 800a224: 801a strh r2, [r3, #0] 800a226: 69bb ldr r3, [r7, #24] 800a228: 881b ldrh r3, [r3, #0] 800a22a: b29b uxth r3, r3 800a22c: ea6f 4343 mvn.w r3, r3, lsl #17 800a230: ea6f 4353 mvn.w r3, r3, lsr #17 800a234: b29a uxth r2, r3 800a236: 69bb ldr r3, [r7, #24] 800a238: 801a strh r2, [r3, #0] 800a23a: e061 b.n 800a300 800a23c: 6cbb ldr r3, [r7, #72] @ 0x48 800a23e: 785b ldrb r3, [r3, #1] 800a240: 2b01 cmp r3, #1 800a242: d15d bne.n 800a300 800a244: 687b ldr r3, [r7, #4] 800a246: 681b ldr r3, [r3, #0] 800a248: 627b str r3, [r7, #36] @ 0x24 800a24a: 687b ldr r3, [r7, #4] 800a24c: 681b ldr r3, [r3, #0] 800a24e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a252: b29b uxth r3, r3 800a254: 461a mov r2, r3 800a256: 6a7b ldr r3, [r7, #36] @ 0x24 800a258: 4413 add r3, r2 800a25a: 627b str r3, [r7, #36] @ 0x24 800a25c: 6cbb ldr r3, [r7, #72] @ 0x48 800a25e: 781b ldrb r3, [r3, #0] 800a260: 00da lsls r2, r3, #3 800a262: 6a7b ldr r3, [r7, #36] @ 0x24 800a264: 4413 add r3, r2 800a266: f203 4302 addw r3, r3, #1026 @ 0x402 800a26a: 623b str r3, [r7, #32] 800a26c: 6a3b ldr r3, [r7, #32] 800a26e: 2200 movs r2, #0 800a270: 801a strh r2, [r3, #0] 800a272: e045 b.n 800a300 } else { PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800a274: 687b ldr r3, [r7, #4] 800a276: 681b ldr r3, [r3, #0] 800a278: 637b str r3, [r7, #52] @ 0x34 800a27a: 6cbb ldr r3, [r7, #72] @ 0x48 800a27c: 785b ldrb r3, [r3, #1] 800a27e: 2b00 cmp r3, #0 800a280: d126 bne.n 800a2d0 800a282: 687b ldr r3, [r7, #4] 800a284: 681b ldr r3, [r3, #0] 800a286: 62fb str r3, [r7, #44] @ 0x2c 800a288: 687b ldr r3, [r7, #4] 800a28a: 681b ldr r3, [r3, #0] 800a28c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a290: b29b uxth r3, r3 800a292: 461a mov r2, r3 800a294: 6afb ldr r3, [r7, #44] @ 0x2c 800a296: 4413 add r3, r2 800a298: 62fb str r3, [r7, #44] @ 0x2c 800a29a: 6cbb ldr r3, [r7, #72] @ 0x48 800a29c: 781b ldrb r3, [r3, #0] 800a29e: 00da lsls r2, r3, #3 800a2a0: 6afb ldr r3, [r7, #44] @ 0x2c 800a2a2: 4413 add r3, r2 800a2a4: f203 4306 addw r3, r3, #1030 @ 0x406 800a2a8: 62bb str r3, [r7, #40] @ 0x28 800a2aa: 6abb ldr r3, [r7, #40] @ 0x28 800a2ac: 881b ldrh r3, [r3, #0] 800a2ae: b29b uxth r3, r3 800a2b0: f3c3 0309 ubfx r3, r3, #0, #10 800a2b4: b29a uxth r2, r3 800a2b6: 6abb ldr r3, [r7, #40] @ 0x28 800a2b8: 801a strh r2, [r3, #0] 800a2ba: 6abb ldr r3, [r7, #40] @ 0x28 800a2bc: 881b ldrh r3, [r3, #0] 800a2be: b29b uxth r3, r3 800a2c0: ea6f 4343 mvn.w r3, r3, lsl #17 800a2c4: ea6f 4353 mvn.w r3, r3, lsr #17 800a2c8: b29a uxth r2, r3 800a2ca: 6abb ldr r3, [r7, #40] @ 0x28 800a2cc: 801a strh r2, [r3, #0] 800a2ce: e017 b.n 800a300 800a2d0: 6cbb ldr r3, [r7, #72] @ 0x48 800a2d2: 785b ldrb r3, [r3, #1] 800a2d4: 2b01 cmp r3, #1 800a2d6: d113 bne.n 800a300 800a2d8: 687b ldr r3, [r7, #4] 800a2da: 681b ldr r3, [r3, #0] 800a2dc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a2e0: b29b uxth r3, r3 800a2e2: 461a mov r2, r3 800a2e4: 6b7b ldr r3, [r7, #52] @ 0x34 800a2e6: 4413 add r3, r2 800a2e8: 637b str r3, [r7, #52] @ 0x34 800a2ea: 6cbb ldr r3, [r7, #72] @ 0x48 800a2ec: 781b ldrb r3, [r3, #0] 800a2ee: 00da lsls r2, r3, #3 800a2f0: 6b7b ldr r3, [r7, #52] @ 0x34 800a2f2: 4413 add r3, r2 800a2f4: f203 4306 addw r3, r3, #1030 @ 0x406 800a2f8: 633b str r3, [r7, #48] @ 0x30 800a2fa: 6b3b ldr r3, [r7, #48] @ 0x30 800a2fc: 2200 movs r2, #0 800a2fe: 801a strh r2, [r3, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 800a300: 6cbb ldr r3, [r7, #72] @ 0x48 800a302: 781b ldrb r3, [r3, #0] 800a304: 4619 mov r1, r3 800a306: 6878 ldr r0, [r7, #4] 800a308: f00e fd69 bl 8018dde 800a30c: e04a b.n 800a3a4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) 800a30e: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a310: f403 7380 and.w r3, r3, #256 @ 0x100 800a314: 2b00 cmp r3, #0 800a316: d13f bne.n 800a398 { /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); 800a318: 687b ldr r3, [r7, #4] 800a31a: 681b ldr r3, [r3, #0] 800a31c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a320: b29b uxth r3, r3 800a322: 461a mov r2, r3 800a324: 6cbb ldr r3, [r7, #72] @ 0x48 800a326: 781b ldrb r3, [r3, #0] 800a328: 00db lsls r3, r3, #3 800a32a: 4413 add r3, r2 800a32c: 687a ldr r2, [r7, #4] 800a32e: 6812 ldr r2, [r2, #0] 800a330: 4413 add r3, r2 800a332: f203 4302 addw r3, r3, #1026 @ 0x402 800a336: 881b ldrh r3, [r3, #0] 800a338: f3c3 0309 ubfx r3, r3, #0, #10 800a33c: 877b strh r3, [r7, #58] @ 0x3a if (ep->xfer_len > TxPctSize) 800a33e: 6cbb ldr r3, [r7, #72] @ 0x48 800a340: 699a ldr r2, [r3, #24] 800a342: 8f7b ldrh r3, [r7, #58] @ 0x3a 800a344: 429a cmp r2, r3 800a346: d906 bls.n 800a356 { ep->xfer_len -= TxPctSize; 800a348: 6cbb ldr r3, [r7, #72] @ 0x48 800a34a: 699a ldr r2, [r3, #24] 800a34c: 8f7b ldrh r3, [r7, #58] @ 0x3a 800a34e: 1ad2 subs r2, r2, r3 800a350: 6cbb ldr r3, [r7, #72] @ 0x48 800a352: 619a str r2, [r3, #24] 800a354: e002 b.n 800a35c } else { ep->xfer_len = 0U; 800a356: 6cbb ldr r3, [r7, #72] @ 0x48 800a358: 2200 movs r2, #0 800a35a: 619a str r2, [r3, #24] } /* Zero Length Packet? */ if (ep->xfer_len == 0U) 800a35c: 6cbb ldr r3, [r7, #72] @ 0x48 800a35e: 699b ldr r3, [r3, #24] 800a360: 2b00 cmp r3, #0 800a362: d106 bne.n 800a372 { /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 800a364: 6cbb ldr r3, [r7, #72] @ 0x48 800a366: 781b ldrb r3, [r3, #0] 800a368: 4619 mov r1, r3 800a36a: 6878 ldr r0, [r7, #4] 800a36c: f00e fd37 bl 8018dde 800a370: e018 b.n 800a3a4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Transfer is not yet Done */ ep->xfer_buff += TxPctSize; 800a372: 6cbb ldr r3, [r7, #72] @ 0x48 800a374: 695a ldr r2, [r3, #20] 800a376: 8f7b ldrh r3, [r7, #58] @ 0x3a 800a378: 441a add r2, r3 800a37a: 6cbb ldr r3, [r7, #72] @ 0x48 800a37c: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 800a37e: 6cbb ldr r3, [r7, #72] @ 0x48 800a380: 69da ldr r2, [r3, #28] 800a382: 8f7b ldrh r3, [r7, #58] @ 0x3a 800a384: 441a add r2, r3 800a386: 6cbb ldr r3, [r7, #72] @ 0x48 800a388: 61da str r2, [r3, #28] (void)USB_EPStartXfer(hpcd->Instance, ep); 800a38a: 687b ldr r3, [r7, #4] 800a38c: 681b ldr r3, [r3, #0] 800a38e: 6cb9 ldr r1, [r7, #72] @ 0x48 800a390: 4618 mov r0, r3 800a392: f005 fe30 bl 800fff6 800a396: e005 b.n 800a3a4 } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ else { (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); 800a398: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a39a: 461a mov r2, r3 800a39c: 6cb9 ldr r1, [r7, #72] @ 0x48 800a39e: 6878 ldr r0, [r7, #4] 800a3a0: f000 f917 bl 800a5d2 while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) 800a3a4: 687b ldr r3, [r7, #4] 800a3a6: 681b ldr r3, [r3, #0] 800a3a8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 800a3ac: b29b uxth r3, r3 800a3ae: b21b sxth r3, r3 800a3b0: 2b00 cmp r3, #0 800a3b2: f6ff ac82 blt.w 8009cba } } } } return HAL_OK; 800a3b6: 2300 movs r3, #0 } 800a3b8: 4618 mov r0, r3 800a3ba: 3750 adds r7, #80 @ 0x50 800a3bc: 46bd mov sp, r7 800a3be: bd80 pop {r7, pc} 0800a3c0 : * @param wEPVal Last snapshot of EPRx register value taken in ISR * @retval HAL status */ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal) { 800a3c0: b580 push {r7, lr} 800a3c2: b088 sub sp, #32 800a3c4: af00 add r7, sp, #0 800a3c6: 60f8 str r0, [r7, #12] 800a3c8: 60b9 str r1, [r7, #8] 800a3ca: 4613 mov r3, r2 800a3cc: 80fb strh r3, [r7, #6] uint16_t count; /* Manage Buffer0 OUT */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 800a3ce: 88fb ldrh r3, [r7, #6] 800a3d0: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a3d4: 2b00 cmp r3, #0 800a3d6: d07c beq.n 800a4d2 { /* Get count of received Data on buffer0 */ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 800a3d8: 68fb ldr r3, [r7, #12] 800a3da: 681b ldr r3, [r3, #0] 800a3dc: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a3e0: b29b uxth r3, r3 800a3e2: 461a mov r2, r3 800a3e4: 68bb ldr r3, [r7, #8] 800a3e6: 781b ldrb r3, [r3, #0] 800a3e8: 00db lsls r3, r3, #3 800a3ea: 4413 add r3, r2 800a3ec: 68fa ldr r2, [r7, #12] 800a3ee: 6812 ldr r2, [r2, #0] 800a3f0: 4413 add r3, r2 800a3f2: f203 4302 addw r3, r3, #1026 @ 0x402 800a3f6: 881b ldrh r3, [r3, #0] 800a3f8: f3c3 0309 ubfx r3, r3, #0, #10 800a3fc: 837b strh r3, [r7, #26] if (ep->xfer_len >= count) 800a3fe: 68bb ldr r3, [r7, #8] 800a400: 699a ldr r2, [r3, #24] 800a402: 8b7b ldrh r3, [r7, #26] 800a404: 429a cmp r2, r3 800a406: d306 bcc.n 800a416 { ep->xfer_len -= count; 800a408: 68bb ldr r3, [r7, #8] 800a40a: 699a ldr r2, [r3, #24] 800a40c: 8b7b ldrh r3, [r7, #26] 800a40e: 1ad2 subs r2, r2, r3 800a410: 68bb ldr r3, [r7, #8] 800a412: 619a str r2, [r3, #24] 800a414: e002 b.n 800a41c } else { ep->xfer_len = 0U; 800a416: 68bb ldr r3, [r7, #8] 800a418: 2200 movs r2, #0 800a41a: 619a str r2, [r3, #24] } if (ep->xfer_len == 0U) 800a41c: 68bb ldr r3, [r7, #8] 800a41e: 699b ldr r3, [r3, #24] 800a420: 2b00 cmp r3, #0 800a422: d123 bne.n 800a46c { /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); 800a424: 68fb ldr r3, [r7, #12] 800a426: 681b ldr r3, [r3, #0] 800a428: 461a mov r2, r3 800a42a: 68bb ldr r3, [r7, #8] 800a42c: 781b ldrb r3, [r3, #0] 800a42e: 009b lsls r3, r3, #2 800a430: 4413 add r3, r2 800a432: 881b ldrh r3, [r3, #0] 800a434: b29b uxth r3, r3 800a436: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a43a: f023 0370 bic.w r3, r3, #112 @ 0x70 800a43e: 833b strh r3, [r7, #24] 800a440: 8b3b ldrh r3, [r7, #24] 800a442: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800a446: 833b strh r3, [r7, #24] 800a448: 68fb ldr r3, [r7, #12] 800a44a: 681b ldr r3, [r3, #0] 800a44c: 461a mov r2, r3 800a44e: 68bb ldr r3, [r7, #8] 800a450: 781b ldrb r3, [r3, #0] 800a452: 009b lsls r3, r3, #2 800a454: 441a add r2, r3 800a456: 8b3b ldrh r3, [r7, #24] 800a458: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a45c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a460: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a464: f043 0380 orr.w r3, r3, #128 @ 0x80 800a468: b29b uxth r3, r3 800a46a: 8013 strh r3, [r2, #0] } /* Check if Buffer1 is in blocked state which requires to toggle */ if ((wEPVal & USB_EP_DTOG_TX) != 0U) 800a46c: 88fb ldrh r3, [r7, #6] 800a46e: f003 0340 and.w r3, r3, #64 @ 0x40 800a472: 2b00 cmp r3, #0 800a474: d01f beq.n 800a4b6 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 800a476: 68fb ldr r3, [r7, #12] 800a478: 681b ldr r3, [r3, #0] 800a47a: 461a mov r2, r3 800a47c: 68bb ldr r3, [r7, #8] 800a47e: 781b ldrb r3, [r3, #0] 800a480: 009b lsls r3, r3, #2 800a482: 4413 add r3, r2 800a484: 881b ldrh r3, [r3, #0] 800a486: b29b uxth r3, r3 800a488: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a48c: f023 0370 bic.w r3, r3, #112 @ 0x70 800a490: 82fb strh r3, [r7, #22] 800a492: 68fb ldr r3, [r7, #12] 800a494: 681b ldr r3, [r3, #0] 800a496: 461a mov r2, r3 800a498: 68bb ldr r3, [r7, #8] 800a49a: 781b ldrb r3, [r3, #0] 800a49c: 009b lsls r3, r3, #2 800a49e: 441a add r2, r3 800a4a0: 8afb ldrh r3, [r7, #22] 800a4a2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a4a6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a4aa: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a4ae: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a4b2: b29b uxth r3, r3 800a4b4: 8013 strh r3, [r2, #0] } if (count != 0U) 800a4b6: 8b7b ldrh r3, [r7, #26] 800a4b8: 2b00 cmp r3, #0 800a4ba: f000 8085 beq.w 800a5c8 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); 800a4be: 68fb ldr r3, [r7, #12] 800a4c0: 6818 ldr r0, [r3, #0] 800a4c2: 68bb ldr r3, [r7, #8] 800a4c4: 6959 ldr r1, [r3, #20] 800a4c6: 68bb ldr r3, [r7, #8] 800a4c8: 891a ldrh r2, [r3, #8] 800a4ca: 8b7b ldrh r3, [r7, #26] 800a4cc: f006 fcba bl 8010e44 800a4d0: e07a b.n 800a5c8 } /* Manage Buffer 1 DTOG_RX=0 */ else { /* Get count of received data */ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 800a4d2: 68fb ldr r3, [r7, #12] 800a4d4: 681b ldr r3, [r3, #0] 800a4d6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a4da: b29b uxth r3, r3 800a4dc: 461a mov r2, r3 800a4de: 68bb ldr r3, [r7, #8] 800a4e0: 781b ldrb r3, [r3, #0] 800a4e2: 00db lsls r3, r3, #3 800a4e4: 4413 add r3, r2 800a4e6: 68fa ldr r2, [r7, #12] 800a4e8: 6812 ldr r2, [r2, #0] 800a4ea: 4413 add r3, r2 800a4ec: f203 4306 addw r3, r3, #1030 @ 0x406 800a4f0: 881b ldrh r3, [r3, #0] 800a4f2: f3c3 0309 ubfx r3, r3, #0, #10 800a4f6: 837b strh r3, [r7, #26] if (ep->xfer_len >= count) 800a4f8: 68bb ldr r3, [r7, #8] 800a4fa: 699a ldr r2, [r3, #24] 800a4fc: 8b7b ldrh r3, [r7, #26] 800a4fe: 429a cmp r2, r3 800a500: d306 bcc.n 800a510 { ep->xfer_len -= count; 800a502: 68bb ldr r3, [r7, #8] 800a504: 699a ldr r2, [r3, #24] 800a506: 8b7b ldrh r3, [r7, #26] 800a508: 1ad2 subs r2, r2, r3 800a50a: 68bb ldr r3, [r7, #8] 800a50c: 619a str r2, [r3, #24] 800a50e: e002 b.n 800a516 } else { ep->xfer_len = 0U; 800a510: 68bb ldr r3, [r7, #8] 800a512: 2200 movs r2, #0 800a514: 619a str r2, [r3, #24] } if (ep->xfer_len == 0U) 800a516: 68bb ldr r3, [r7, #8] 800a518: 699b ldr r3, [r3, #24] 800a51a: 2b00 cmp r3, #0 800a51c: d123 bne.n 800a566 { /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); 800a51e: 68fb ldr r3, [r7, #12] 800a520: 681b ldr r3, [r3, #0] 800a522: 461a mov r2, r3 800a524: 68bb ldr r3, [r7, #8] 800a526: 781b ldrb r3, [r3, #0] 800a528: 009b lsls r3, r3, #2 800a52a: 4413 add r3, r2 800a52c: 881b ldrh r3, [r3, #0] 800a52e: b29b uxth r3, r3 800a530: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a534: f023 0370 bic.w r3, r3, #112 @ 0x70 800a538: 83fb strh r3, [r7, #30] 800a53a: 8bfb ldrh r3, [r7, #30] 800a53c: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800a540: 83fb strh r3, [r7, #30] 800a542: 68fb ldr r3, [r7, #12] 800a544: 681b ldr r3, [r3, #0] 800a546: 461a mov r2, r3 800a548: 68bb ldr r3, [r7, #8] 800a54a: 781b ldrb r3, [r3, #0] 800a54c: 009b lsls r3, r3, #2 800a54e: 441a add r2, r3 800a550: 8bfb ldrh r3, [r7, #30] 800a552: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a556: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a55a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a55e: f043 0380 orr.w r3, r3, #128 @ 0x80 800a562: b29b uxth r3, r3 800a564: 8013 strh r3, [r2, #0] } /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) 800a566: 88fb ldrh r3, [r7, #6] 800a568: f003 0340 and.w r3, r3, #64 @ 0x40 800a56c: 2b00 cmp r3, #0 800a56e: d11f bne.n 800a5b0 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); 800a570: 68fb ldr r3, [r7, #12] 800a572: 681b ldr r3, [r3, #0] 800a574: 461a mov r2, r3 800a576: 68bb ldr r3, [r7, #8] 800a578: 781b ldrb r3, [r3, #0] 800a57a: 009b lsls r3, r3, #2 800a57c: 4413 add r3, r2 800a57e: 881b ldrh r3, [r3, #0] 800a580: b29b uxth r3, r3 800a582: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a586: f023 0370 bic.w r3, r3, #112 @ 0x70 800a58a: 83bb strh r3, [r7, #28] 800a58c: 68fb ldr r3, [r7, #12] 800a58e: 681b ldr r3, [r3, #0] 800a590: 461a mov r2, r3 800a592: 68bb ldr r3, [r7, #8] 800a594: 781b ldrb r3, [r3, #0] 800a596: 009b lsls r3, r3, #2 800a598: 441a add r2, r3 800a59a: 8bbb ldrh r3, [r7, #28] 800a59c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a5a0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a5a4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a5a8: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800a5ac: b29b uxth r3, r3 800a5ae: 8013 strh r3, [r2, #0] } if (count != 0U) 800a5b0: 8b7b ldrh r3, [r7, #26] 800a5b2: 2b00 cmp r3, #0 800a5b4: d008 beq.n 800a5c8 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); 800a5b6: 68fb ldr r3, [r7, #12] 800a5b8: 6818 ldr r0, [r3, #0] 800a5ba: 68bb ldr r3, [r7, #8] 800a5bc: 6959 ldr r1, [r3, #20] 800a5be: 68bb ldr r3, [r7, #8] 800a5c0: 895a ldrh r2, [r3, #10] 800a5c2: 8b7b ldrh r3, [r7, #26] 800a5c4: f006 fc3e bl 8010e44 } } return count; 800a5c8: 8b7b ldrh r3, [r7, #26] } 800a5ca: 4618 mov r0, r3 800a5cc: 3720 adds r7, #32 800a5ce: 46bd mov sp, r7 800a5d0: bd80 pop {r7, pc} 0800a5d2 : * @param wEPVal Last snapshot of EPRx register value taken in ISR * @retval HAL status */ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal) { 800a5d2: b580 push {r7, lr} 800a5d4: b0a6 sub sp, #152 @ 0x98 800a5d6: af00 add r7, sp, #0 800a5d8: 60f8 str r0, [r7, #12] 800a5da: 60b9 str r1, [r7, #8] 800a5dc: 4613 mov r3, r2 800a5de: 80fb strh r3, [r7, #6] uint32_t len; uint16_t TxPctSize; /* Data Buffer0 ACK received */ if ((wEPVal & USB_EP_DTOG_TX) != 0U) 800a5e0: 88fb ldrh r3, [r7, #6] 800a5e2: f003 0340 and.w r3, r3, #64 @ 0x40 800a5e6: 2b00 cmp r3, #0 800a5e8: f000 81f7 beq.w 800a9da { /* multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); 800a5ec: 68fb ldr r3, [r7, #12] 800a5ee: 681b ldr r3, [r3, #0] 800a5f0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a5f4: b29b uxth r3, r3 800a5f6: 461a mov r2, r3 800a5f8: 68bb ldr r3, [r7, #8] 800a5fa: 781b ldrb r3, [r3, #0] 800a5fc: 00db lsls r3, r3, #3 800a5fe: 4413 add r3, r2 800a600: 68fa ldr r2, [r7, #12] 800a602: 6812 ldr r2, [r2, #0] 800a604: 4413 add r3, r2 800a606: f203 4302 addw r3, r3, #1026 @ 0x402 800a60a: 881b ldrh r3, [r3, #0] 800a60c: f3c3 0309 ubfx r3, r3, #0, #10 800a610: f8a7 3096 strh.w r3, [r7, #150] @ 0x96 if (ep->xfer_len > TxPctSize) 800a614: 68bb ldr r3, [r7, #8] 800a616: 699a ldr r2, [r3, #24] 800a618: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a61c: 429a cmp r2, r3 800a61e: d907 bls.n 800a630 { ep->xfer_len -= TxPctSize; 800a620: 68bb ldr r3, [r7, #8] 800a622: 699a ldr r2, [r3, #24] 800a624: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a628: 1ad2 subs r2, r2, r3 800a62a: 68bb ldr r3, [r7, #8] 800a62c: 619a str r2, [r3, #24] 800a62e: e002 b.n 800a636 } else { ep->xfer_len = 0U; 800a630: 68bb ldr r3, [r7, #8] 800a632: 2200 movs r2, #0 800a634: 619a str r2, [r3, #24] } /* Transfer is completed */ if (ep->xfer_len == 0U) 800a636: 68bb ldr r3, [r7, #8] 800a638: 699b ldr r3, [r3, #24] 800a63a: 2b00 cmp r3, #0 800a63c: f040 80e1 bne.w 800a802 { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800a640: 68bb ldr r3, [r7, #8] 800a642: 785b ldrb r3, [r3, #1] 800a644: 2b00 cmp r3, #0 800a646: d126 bne.n 800a696 800a648: 68fb ldr r3, [r7, #12] 800a64a: 681b ldr r3, [r3, #0] 800a64c: 633b str r3, [r7, #48] @ 0x30 800a64e: 68fb ldr r3, [r7, #12] 800a650: 681b ldr r3, [r3, #0] 800a652: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a656: b29b uxth r3, r3 800a658: 461a mov r2, r3 800a65a: 6b3b ldr r3, [r7, #48] @ 0x30 800a65c: 4413 add r3, r2 800a65e: 633b str r3, [r7, #48] @ 0x30 800a660: 68bb ldr r3, [r7, #8] 800a662: 781b ldrb r3, [r3, #0] 800a664: 00da lsls r2, r3, #3 800a666: 6b3b ldr r3, [r7, #48] @ 0x30 800a668: 4413 add r3, r2 800a66a: f203 4302 addw r3, r3, #1026 @ 0x402 800a66e: 62fb str r3, [r7, #44] @ 0x2c 800a670: 6afb ldr r3, [r7, #44] @ 0x2c 800a672: 881b ldrh r3, [r3, #0] 800a674: b29b uxth r3, r3 800a676: f3c3 0309 ubfx r3, r3, #0, #10 800a67a: b29a uxth r2, r3 800a67c: 6afb ldr r3, [r7, #44] @ 0x2c 800a67e: 801a strh r2, [r3, #0] 800a680: 6afb ldr r3, [r7, #44] @ 0x2c 800a682: 881b ldrh r3, [r3, #0] 800a684: b29b uxth r3, r3 800a686: ea6f 4343 mvn.w r3, r3, lsl #17 800a68a: ea6f 4353 mvn.w r3, r3, lsr #17 800a68e: b29a uxth r2, r3 800a690: 6afb ldr r3, [r7, #44] @ 0x2c 800a692: 801a strh r2, [r3, #0] 800a694: e01a b.n 800a6cc 800a696: 68bb ldr r3, [r7, #8] 800a698: 785b ldrb r3, [r3, #1] 800a69a: 2b01 cmp r3, #1 800a69c: d116 bne.n 800a6cc 800a69e: 68fb ldr r3, [r7, #12] 800a6a0: 681b ldr r3, [r3, #0] 800a6a2: 63bb str r3, [r7, #56] @ 0x38 800a6a4: 68fb ldr r3, [r7, #12] 800a6a6: 681b ldr r3, [r3, #0] 800a6a8: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a6ac: b29b uxth r3, r3 800a6ae: 461a mov r2, r3 800a6b0: 6bbb ldr r3, [r7, #56] @ 0x38 800a6b2: 4413 add r3, r2 800a6b4: 63bb str r3, [r7, #56] @ 0x38 800a6b6: 68bb ldr r3, [r7, #8] 800a6b8: 781b ldrb r3, [r3, #0] 800a6ba: 00da lsls r2, r3, #3 800a6bc: 6bbb ldr r3, [r7, #56] @ 0x38 800a6be: 4413 add r3, r2 800a6c0: f203 4302 addw r3, r3, #1026 @ 0x402 800a6c4: 637b str r3, [r7, #52] @ 0x34 800a6c6: 6b7b ldr r3, [r7, #52] @ 0x34 800a6c8: 2200 movs r2, #0 800a6ca: 801a strh r2, [r3, #0] PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800a6cc: 68fb ldr r3, [r7, #12] 800a6ce: 681b ldr r3, [r3, #0] 800a6d0: 62bb str r3, [r7, #40] @ 0x28 800a6d2: 68bb ldr r3, [r7, #8] 800a6d4: 785b ldrb r3, [r3, #1] 800a6d6: 2b00 cmp r3, #0 800a6d8: d126 bne.n 800a728 800a6da: 68fb ldr r3, [r7, #12] 800a6dc: 681b ldr r3, [r3, #0] 800a6de: 623b str r3, [r7, #32] 800a6e0: 68fb ldr r3, [r7, #12] 800a6e2: 681b ldr r3, [r3, #0] 800a6e4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a6e8: b29b uxth r3, r3 800a6ea: 461a mov r2, r3 800a6ec: 6a3b ldr r3, [r7, #32] 800a6ee: 4413 add r3, r2 800a6f0: 623b str r3, [r7, #32] 800a6f2: 68bb ldr r3, [r7, #8] 800a6f4: 781b ldrb r3, [r3, #0] 800a6f6: 00da lsls r2, r3, #3 800a6f8: 6a3b ldr r3, [r7, #32] 800a6fa: 4413 add r3, r2 800a6fc: f203 4306 addw r3, r3, #1030 @ 0x406 800a700: 61fb str r3, [r7, #28] 800a702: 69fb ldr r3, [r7, #28] 800a704: 881b ldrh r3, [r3, #0] 800a706: b29b uxth r3, r3 800a708: f3c3 0309 ubfx r3, r3, #0, #10 800a70c: b29a uxth r2, r3 800a70e: 69fb ldr r3, [r7, #28] 800a710: 801a strh r2, [r3, #0] 800a712: 69fb ldr r3, [r7, #28] 800a714: 881b ldrh r3, [r3, #0] 800a716: b29b uxth r3, r3 800a718: ea6f 4343 mvn.w r3, r3, lsl #17 800a71c: ea6f 4353 mvn.w r3, r3, lsr #17 800a720: b29a uxth r2, r3 800a722: 69fb ldr r3, [r7, #28] 800a724: 801a strh r2, [r3, #0] 800a726: e017 b.n 800a758 800a728: 68bb ldr r3, [r7, #8] 800a72a: 785b ldrb r3, [r3, #1] 800a72c: 2b01 cmp r3, #1 800a72e: d113 bne.n 800a758 800a730: 68fb ldr r3, [r7, #12] 800a732: 681b ldr r3, [r3, #0] 800a734: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a738: b29b uxth r3, r3 800a73a: 461a mov r2, r3 800a73c: 6abb ldr r3, [r7, #40] @ 0x28 800a73e: 4413 add r3, r2 800a740: 62bb str r3, [r7, #40] @ 0x28 800a742: 68bb ldr r3, [r7, #8] 800a744: 781b ldrb r3, [r3, #0] 800a746: 00da lsls r2, r3, #3 800a748: 6abb ldr r3, [r7, #40] @ 0x28 800a74a: 4413 add r3, r2 800a74c: f203 4306 addw r3, r3, #1030 @ 0x406 800a750: 627b str r3, [r7, #36] @ 0x24 800a752: 6a7b ldr r3, [r7, #36] @ 0x24 800a754: 2200 movs r2, #0 800a756: 801a strh r2, [r3, #0] if (ep->type == EP_TYPE_BULK) 800a758: 68bb ldr r3, [r7, #8] 800a75a: 78db ldrb r3, [r3, #3] 800a75c: 2b02 cmp r3, #2 800a75e: d123 bne.n 800a7a8 { /* Set Bulk endpoint in NAK state */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); 800a760: 68fb ldr r3, [r7, #12] 800a762: 681b ldr r3, [r3, #0] 800a764: 461a mov r2, r3 800a766: 68bb ldr r3, [r7, #8] 800a768: 781b ldrb r3, [r3, #0] 800a76a: 009b lsls r3, r3, #2 800a76c: 4413 add r3, r2 800a76e: 881b ldrh r3, [r3, #0] 800a770: b29b uxth r3, r3 800a772: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a776: f023 0340 bic.w r3, r3, #64 @ 0x40 800a77a: 837b strh r3, [r7, #26] 800a77c: 8b7b ldrh r3, [r7, #26] 800a77e: f083 0320 eor.w r3, r3, #32 800a782: 837b strh r3, [r7, #26] 800a784: 68fb ldr r3, [r7, #12] 800a786: 681b ldr r3, [r3, #0] 800a788: 461a mov r2, r3 800a78a: 68bb ldr r3, [r7, #8] 800a78c: 781b ldrb r3, [r3, #0] 800a78e: 009b lsls r3, r3, #2 800a790: 441a add r2, r3 800a792: 8b7b ldrh r3, [r7, #26] 800a794: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a798: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a79c: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800a7a0: f043 0380 orr.w r3, r3, #128 @ 0x80 800a7a4: b29b uxth r3, r3 800a7a6: 8013 strh r3, [r2, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 800a7a8: 68bb ldr r3, [r7, #8] 800a7aa: 781b ldrb r3, [r3, #0] 800a7ac: 4619 mov r1, r3 800a7ae: 68f8 ldr r0, [r7, #12] 800a7b0: f00e fb15 bl 8018dde #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 800a7b4: 88fb ldrh r3, [r7, #6] 800a7b6: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a7ba: 2b00 cmp r3, #0 800a7bc: d01f beq.n 800a7fe { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 800a7be: 68fb ldr r3, [r7, #12] 800a7c0: 681b ldr r3, [r3, #0] 800a7c2: 461a mov r2, r3 800a7c4: 68bb ldr r3, [r7, #8] 800a7c6: 781b ldrb r3, [r3, #0] 800a7c8: 009b lsls r3, r3, #2 800a7ca: 4413 add r3, r2 800a7cc: 881b ldrh r3, [r3, #0] 800a7ce: b29b uxth r3, r3 800a7d0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a7d4: f023 0370 bic.w r3, r3, #112 @ 0x70 800a7d8: 833b strh r3, [r7, #24] 800a7da: 68fb ldr r3, [r7, #12] 800a7dc: 681b ldr r3, [r3, #0] 800a7de: 461a mov r2, r3 800a7e0: 68bb ldr r3, [r7, #8] 800a7e2: 781b ldrb r3, [r3, #0] 800a7e4: 009b lsls r3, r3, #2 800a7e6: 441a add r2, r3 800a7e8: 8b3b ldrh r3, [r7, #24] 800a7ea: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a7ee: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a7f2: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a7f6: f043 0380 orr.w r3, r3, #128 @ 0x80 800a7fa: b29b uxth r3, r3 800a7fc: 8013 strh r3, [r2, #0] } return HAL_OK; 800a7fe: 2300 movs r3, #0 800a800: e31f b.n 800ae42 } else /* Transfer is not yet Done */ { /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) 800a802: 88fb ldrh r3, [r7, #6] 800a804: f403 4380 and.w r3, r3, #16384 @ 0x4000 800a808: 2b00 cmp r3, #0 800a80a: d021 beq.n 800a850 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 800a80c: 68fb ldr r3, [r7, #12] 800a80e: 681b ldr r3, [r3, #0] 800a810: 461a mov r2, r3 800a812: 68bb ldr r3, [r7, #8] 800a814: 781b ldrb r3, [r3, #0] 800a816: 009b lsls r3, r3, #2 800a818: 4413 add r3, r2 800a81a: 881b ldrh r3, [r3, #0] 800a81c: b29b uxth r3, r3 800a81e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800a822: f023 0370 bic.w r3, r3, #112 @ 0x70 800a826: f8a7 304e strh.w r3, [r7, #78] @ 0x4e 800a82a: 68fb ldr r3, [r7, #12] 800a82c: 681b ldr r3, [r3, #0] 800a82e: 461a mov r2, r3 800a830: 68bb ldr r3, [r7, #8] 800a832: 781b ldrb r3, [r3, #0] 800a834: 009b lsls r3, r3, #2 800a836: 441a add r2, r3 800a838: f8b7 304e ldrh.w r3, [r7, #78] @ 0x4e 800a83c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800a840: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800a844: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800a848: f043 0380 orr.w r3, r3, #128 @ 0x80 800a84c: b29b uxth r3, r3 800a84e: 8013 strh r3, [r2, #0] } /* Still there is data to Fill in the next Buffer */ if (ep->xfer_fill_db == 1U) 800a850: 68bb ldr r3, [r7, #8] 800a852: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800a856: 2b01 cmp r3, #1 800a858: f040 82ca bne.w 800adf0 { ep->xfer_buff += TxPctSize; 800a85c: 68bb ldr r3, [r7, #8] 800a85e: 695a ldr r2, [r3, #20] 800a860: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a864: 441a add r2, r3 800a866: 68bb ldr r3, [r7, #8] 800a868: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 800a86a: 68bb ldr r3, [r7, #8] 800a86c: 69da ldr r2, [r3, #28] 800a86e: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a872: 441a add r2, r3 800a874: 68bb ldr r3, [r7, #8] 800a876: 61da str r2, [r3, #28] /* Calculate the len of the new buffer to fill */ if (ep->xfer_len_db >= ep->maxpacket) 800a878: 68bb ldr r3, [r7, #8] 800a87a: 6a1a ldr r2, [r3, #32] 800a87c: 68bb ldr r3, [r7, #8] 800a87e: 691b ldr r3, [r3, #16] 800a880: 429a cmp r2, r3 800a882: d309 bcc.n 800a898 { len = ep->maxpacket; 800a884: 68bb ldr r3, [r7, #8] 800a886: 691b ldr r3, [r3, #16] 800a888: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_len_db -= len; 800a88a: 68bb ldr r3, [r7, #8] 800a88c: 6a1a ldr r2, [r3, #32] 800a88e: 6dbb ldr r3, [r7, #88] @ 0x58 800a890: 1ad2 subs r2, r2, r3 800a892: 68bb ldr r3, [r7, #8] 800a894: 621a str r2, [r3, #32] 800a896: e015 b.n 800a8c4 } else if (ep->xfer_len_db == 0U) 800a898: 68bb ldr r3, [r7, #8] 800a89a: 6a1b ldr r3, [r3, #32] 800a89c: 2b00 cmp r3, #0 800a89e: d107 bne.n 800a8b0 { len = TxPctSize; 800a8a0: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800a8a4: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_fill_db = 0U; 800a8a6: 68bb ldr r3, [r7, #8] 800a8a8: 2200 movs r2, #0 800a8aa: f883 2024 strb.w r2, [r3, #36] @ 0x24 800a8ae: e009 b.n 800a8c4 } else { ep->xfer_fill_db = 0U; 800a8b0: 68bb ldr r3, [r7, #8] 800a8b2: 2200 movs r2, #0 800a8b4: f883 2024 strb.w r2, [r3, #36] @ 0x24 len = ep->xfer_len_db; 800a8b8: 68bb ldr r3, [r7, #8] 800a8ba: 6a1b ldr r3, [r3, #32] 800a8bc: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_len_db = 0U; 800a8be: 68bb ldr r3, [r7, #8] 800a8c0: 2200 movs r2, #0 800a8c2: 621a str r2, [r3, #32] } /* Write remaining Data to Buffer */ /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); 800a8c4: 68bb ldr r3, [r7, #8] 800a8c6: 785b ldrb r3, [r3, #1] 800a8c8: 2b00 cmp r3, #0 800a8ca: d15f bne.n 800a98c 800a8cc: 68fb ldr r3, [r7, #12] 800a8ce: 681b ldr r3, [r3, #0] 800a8d0: 643b str r3, [r7, #64] @ 0x40 800a8d2: 68fb ldr r3, [r7, #12] 800a8d4: 681b ldr r3, [r3, #0] 800a8d6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a8da: b29b uxth r3, r3 800a8dc: 461a mov r2, r3 800a8de: 6c3b ldr r3, [r7, #64] @ 0x40 800a8e0: 4413 add r3, r2 800a8e2: 643b str r3, [r7, #64] @ 0x40 800a8e4: 68bb ldr r3, [r7, #8] 800a8e6: 781b ldrb r3, [r3, #0] 800a8e8: 00da lsls r2, r3, #3 800a8ea: 6c3b ldr r3, [r7, #64] @ 0x40 800a8ec: 4413 add r3, r2 800a8ee: f203 4302 addw r3, r3, #1026 @ 0x402 800a8f2: 63fb str r3, [r7, #60] @ 0x3c 800a8f4: 6bfb ldr r3, [r7, #60] @ 0x3c 800a8f6: 881b ldrh r3, [r3, #0] 800a8f8: b29b uxth r3, r3 800a8fa: f3c3 0309 ubfx r3, r3, #0, #10 800a8fe: b29a uxth r2, r3 800a900: 6bfb ldr r3, [r7, #60] @ 0x3c 800a902: 801a strh r2, [r3, #0] 800a904: 6dbb ldr r3, [r7, #88] @ 0x58 800a906: 2b00 cmp r3, #0 800a908: d10a bne.n 800a920 800a90a: 6bfb ldr r3, [r7, #60] @ 0x3c 800a90c: 881b ldrh r3, [r3, #0] 800a90e: b29b uxth r3, r3 800a910: ea6f 4343 mvn.w r3, r3, lsl #17 800a914: ea6f 4353 mvn.w r3, r3, lsr #17 800a918: b29a uxth r2, r3 800a91a: 6bfb ldr r3, [r7, #60] @ 0x3c 800a91c: 801a strh r2, [r3, #0] 800a91e: e051 b.n 800a9c4 800a920: 6dbb ldr r3, [r7, #88] @ 0x58 800a922: 2b3e cmp r3, #62 @ 0x3e 800a924: d816 bhi.n 800a954 800a926: 6dbb ldr r3, [r7, #88] @ 0x58 800a928: 085b lsrs r3, r3, #1 800a92a: 653b str r3, [r7, #80] @ 0x50 800a92c: 6dbb ldr r3, [r7, #88] @ 0x58 800a92e: f003 0301 and.w r3, r3, #1 800a932: 2b00 cmp r3, #0 800a934: d002 beq.n 800a93c 800a936: 6d3b ldr r3, [r7, #80] @ 0x50 800a938: 3301 adds r3, #1 800a93a: 653b str r3, [r7, #80] @ 0x50 800a93c: 6bfb ldr r3, [r7, #60] @ 0x3c 800a93e: 881b ldrh r3, [r3, #0] 800a940: b29a uxth r2, r3 800a942: 6d3b ldr r3, [r7, #80] @ 0x50 800a944: b29b uxth r3, r3 800a946: 029b lsls r3, r3, #10 800a948: b29b uxth r3, r3 800a94a: 4313 orrs r3, r2 800a94c: b29a uxth r2, r3 800a94e: 6bfb ldr r3, [r7, #60] @ 0x3c 800a950: 801a strh r2, [r3, #0] 800a952: e037 b.n 800a9c4 800a954: 6dbb ldr r3, [r7, #88] @ 0x58 800a956: 095b lsrs r3, r3, #5 800a958: 653b str r3, [r7, #80] @ 0x50 800a95a: 6dbb ldr r3, [r7, #88] @ 0x58 800a95c: f003 031f and.w r3, r3, #31 800a960: 2b00 cmp r3, #0 800a962: d102 bne.n 800a96a 800a964: 6d3b ldr r3, [r7, #80] @ 0x50 800a966: 3b01 subs r3, #1 800a968: 653b str r3, [r7, #80] @ 0x50 800a96a: 6bfb ldr r3, [r7, #60] @ 0x3c 800a96c: 881b ldrh r3, [r3, #0] 800a96e: b29a uxth r2, r3 800a970: 6d3b ldr r3, [r7, #80] @ 0x50 800a972: b29b uxth r3, r3 800a974: 029b lsls r3, r3, #10 800a976: b29b uxth r3, r3 800a978: 4313 orrs r3, r2 800a97a: b29b uxth r3, r3 800a97c: ea6f 4343 mvn.w r3, r3, lsl #17 800a980: ea6f 4353 mvn.w r3, r3, lsr #17 800a984: b29a uxth r2, r3 800a986: 6bfb ldr r3, [r7, #60] @ 0x3c 800a988: 801a strh r2, [r3, #0] 800a98a: e01b b.n 800a9c4 800a98c: 68bb ldr r3, [r7, #8] 800a98e: 785b ldrb r3, [r3, #1] 800a990: 2b01 cmp r3, #1 800a992: d117 bne.n 800a9c4 800a994: 68fb ldr r3, [r7, #12] 800a996: 681b ldr r3, [r3, #0] 800a998: 64bb str r3, [r7, #72] @ 0x48 800a99a: 68fb ldr r3, [r7, #12] 800a99c: 681b ldr r3, [r3, #0] 800a99e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a9a2: b29b uxth r3, r3 800a9a4: 461a mov r2, r3 800a9a6: 6cbb ldr r3, [r7, #72] @ 0x48 800a9a8: 4413 add r3, r2 800a9aa: 64bb str r3, [r7, #72] @ 0x48 800a9ac: 68bb ldr r3, [r7, #8] 800a9ae: 781b ldrb r3, [r3, #0] 800a9b0: 00da lsls r2, r3, #3 800a9b2: 6cbb ldr r3, [r7, #72] @ 0x48 800a9b4: 4413 add r3, r2 800a9b6: f203 4302 addw r3, r3, #1026 @ 0x402 800a9ba: 647b str r3, [r7, #68] @ 0x44 800a9bc: 6dbb ldr r3, [r7, #88] @ 0x58 800a9be: b29a uxth r2, r3 800a9c0: 6c7b ldr r3, [r7, #68] @ 0x44 800a9c2: 801a strh r2, [r3, #0] /* Copy user buffer to USB PMA */ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); 800a9c4: 68fb ldr r3, [r7, #12] 800a9c6: 6818 ldr r0, [r3, #0] 800a9c8: 68bb ldr r3, [r7, #8] 800a9ca: 6959 ldr r1, [r3, #20] 800a9cc: 68bb ldr r3, [r7, #8] 800a9ce: 891a ldrh r2, [r3, #8] 800a9d0: 6dbb ldr r3, [r7, #88] @ 0x58 800a9d2: b29b uxth r3, r3 800a9d4: f006 f9f3 bl 8010dbe 800a9d8: e20a b.n 800adf0 } } else /* Data Buffer1 ACK received */ { /* multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); 800a9da: 68fb ldr r3, [r7, #12] 800a9dc: 681b ldr r3, [r3, #0] 800a9de: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800a9e2: b29b uxth r3, r3 800a9e4: 461a mov r2, r3 800a9e6: 68bb ldr r3, [r7, #8] 800a9e8: 781b ldrb r3, [r3, #0] 800a9ea: 00db lsls r3, r3, #3 800a9ec: 4413 add r3, r2 800a9ee: 68fa ldr r2, [r7, #12] 800a9f0: 6812 ldr r2, [r2, #0] 800a9f2: 4413 add r3, r2 800a9f4: f203 4306 addw r3, r3, #1030 @ 0x406 800a9f8: 881b ldrh r3, [r3, #0] 800a9fa: f3c3 0309 ubfx r3, r3, #0, #10 800a9fe: f8a7 3096 strh.w r3, [r7, #150] @ 0x96 if (ep->xfer_len >= TxPctSize) 800aa02: 68bb ldr r3, [r7, #8] 800aa04: 699a ldr r2, [r3, #24] 800aa06: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800aa0a: 429a cmp r2, r3 800aa0c: d307 bcc.n 800aa1e { ep->xfer_len -= TxPctSize; 800aa0e: 68bb ldr r3, [r7, #8] 800aa10: 699a ldr r2, [r3, #24] 800aa12: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800aa16: 1ad2 subs r2, r2, r3 800aa18: 68bb ldr r3, [r7, #8] 800aa1a: 619a str r2, [r3, #24] 800aa1c: e002 b.n 800aa24 } else { ep->xfer_len = 0U; 800aa1e: 68bb ldr r3, [r7, #8] 800aa20: 2200 movs r2, #0 800aa22: 619a str r2, [r3, #24] } /* Transfer is completed */ if (ep->xfer_len == 0U) 800aa24: 68bb ldr r3, [r7, #8] 800aa26: 699b ldr r3, [r3, #24] 800aa28: 2b00 cmp r3, #0 800aa2a: f040 80f6 bne.w 800ac1a { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800aa2e: 68bb ldr r3, [r7, #8] 800aa30: 785b ldrb r3, [r3, #1] 800aa32: 2b00 cmp r3, #0 800aa34: d126 bne.n 800aa84 800aa36: 68fb ldr r3, [r7, #12] 800aa38: 681b ldr r3, [r3, #0] 800aa3a: 677b str r3, [r7, #116] @ 0x74 800aa3c: 68fb ldr r3, [r7, #12] 800aa3e: 681b ldr r3, [r3, #0] 800aa40: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800aa44: b29b uxth r3, r3 800aa46: 461a mov r2, r3 800aa48: 6f7b ldr r3, [r7, #116] @ 0x74 800aa4a: 4413 add r3, r2 800aa4c: 677b str r3, [r7, #116] @ 0x74 800aa4e: 68bb ldr r3, [r7, #8] 800aa50: 781b ldrb r3, [r3, #0] 800aa52: 00da lsls r2, r3, #3 800aa54: 6f7b ldr r3, [r7, #116] @ 0x74 800aa56: 4413 add r3, r2 800aa58: f203 4302 addw r3, r3, #1026 @ 0x402 800aa5c: 673b str r3, [r7, #112] @ 0x70 800aa5e: 6f3b ldr r3, [r7, #112] @ 0x70 800aa60: 881b ldrh r3, [r3, #0] 800aa62: b29b uxth r3, r3 800aa64: f3c3 0309 ubfx r3, r3, #0, #10 800aa68: b29a uxth r2, r3 800aa6a: 6f3b ldr r3, [r7, #112] @ 0x70 800aa6c: 801a strh r2, [r3, #0] 800aa6e: 6f3b ldr r3, [r7, #112] @ 0x70 800aa70: 881b ldrh r3, [r3, #0] 800aa72: b29b uxth r3, r3 800aa74: ea6f 4343 mvn.w r3, r3, lsl #17 800aa78: ea6f 4353 mvn.w r3, r3, lsr #17 800aa7c: b29a uxth r2, r3 800aa7e: 6f3b ldr r3, [r7, #112] @ 0x70 800aa80: 801a strh r2, [r3, #0] 800aa82: e01a b.n 800aaba 800aa84: 68bb ldr r3, [r7, #8] 800aa86: 785b ldrb r3, [r3, #1] 800aa88: 2b01 cmp r3, #1 800aa8a: d116 bne.n 800aaba 800aa8c: 68fb ldr r3, [r7, #12] 800aa8e: 681b ldr r3, [r3, #0] 800aa90: 67fb str r3, [r7, #124] @ 0x7c 800aa92: 68fb ldr r3, [r7, #12] 800aa94: 681b ldr r3, [r3, #0] 800aa96: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800aa9a: b29b uxth r3, r3 800aa9c: 461a mov r2, r3 800aa9e: 6ffb ldr r3, [r7, #124] @ 0x7c 800aaa0: 4413 add r3, r2 800aaa2: 67fb str r3, [r7, #124] @ 0x7c 800aaa4: 68bb ldr r3, [r7, #8] 800aaa6: 781b ldrb r3, [r3, #0] 800aaa8: 00da lsls r2, r3, #3 800aaaa: 6ffb ldr r3, [r7, #124] @ 0x7c 800aaac: 4413 add r3, r2 800aaae: f203 4302 addw r3, r3, #1026 @ 0x402 800aab2: 67bb str r3, [r7, #120] @ 0x78 800aab4: 6fbb ldr r3, [r7, #120] @ 0x78 800aab6: 2200 movs r2, #0 800aab8: 801a strh r2, [r3, #0] PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); 800aaba: 68fb ldr r3, [r7, #12] 800aabc: 681b ldr r3, [r3, #0] 800aabe: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800aac2: 68bb ldr r3, [r7, #8] 800aac4: 785b ldrb r3, [r3, #1] 800aac6: 2b00 cmp r3, #0 800aac8: d12f bne.n 800ab2a 800aaca: 68fb ldr r3, [r7, #12] 800aacc: 681b ldr r3, [r3, #0] 800aace: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800aad2: 68fb ldr r3, [r7, #12] 800aad4: 681b ldr r3, [r3, #0] 800aad6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800aada: b29b uxth r3, r3 800aadc: 461a mov r2, r3 800aade: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800aae2: 4413 add r3, r2 800aae4: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800aae8: 68bb ldr r3, [r7, #8] 800aaea: 781b ldrb r3, [r3, #0] 800aaec: 00da lsls r2, r3, #3 800aaee: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800aaf2: 4413 add r3, r2 800aaf4: f203 4306 addw r3, r3, #1030 @ 0x406 800aaf8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800aafc: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800ab00: 881b ldrh r3, [r3, #0] 800ab02: b29b uxth r3, r3 800ab04: f3c3 0309 ubfx r3, r3, #0, #10 800ab08: b29a uxth r2, r3 800ab0a: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800ab0e: 801a strh r2, [r3, #0] 800ab10: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800ab14: 881b ldrh r3, [r3, #0] 800ab16: b29b uxth r3, r3 800ab18: ea6f 4343 mvn.w r3, r3, lsl #17 800ab1c: ea6f 4353 mvn.w r3, r3, lsr #17 800ab20: b29a uxth r2, r3 800ab22: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800ab26: 801a strh r2, [r3, #0] 800ab28: e01c b.n 800ab64 800ab2a: 68bb ldr r3, [r7, #8] 800ab2c: 785b ldrb r3, [r3, #1] 800ab2e: 2b01 cmp r3, #1 800ab30: d118 bne.n 800ab64 800ab32: 68fb ldr r3, [r7, #12] 800ab34: 681b ldr r3, [r3, #0] 800ab36: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800ab3a: b29b uxth r3, r3 800ab3c: 461a mov r2, r3 800ab3e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800ab42: 4413 add r3, r2 800ab44: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800ab48: 68bb ldr r3, [r7, #8] 800ab4a: 781b ldrb r3, [r3, #0] 800ab4c: 00da lsls r2, r3, #3 800ab4e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800ab52: 4413 add r3, r2 800ab54: f203 4306 addw r3, r3, #1030 @ 0x406 800ab58: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800ab5c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800ab60: 2200 movs r2, #0 800ab62: 801a strh r2, [r3, #0] if (ep->type == EP_TYPE_BULK) 800ab64: 68bb ldr r3, [r7, #8] 800ab66: 78db ldrb r3, [r3, #3] 800ab68: 2b02 cmp r3, #2 800ab6a: d127 bne.n 800abbc { /* Set Bulk endpoint in NAK state */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); 800ab6c: 68fb ldr r3, [r7, #12] 800ab6e: 681b ldr r3, [r3, #0] 800ab70: 461a mov r2, r3 800ab72: 68bb ldr r3, [r7, #8] 800ab74: 781b ldrb r3, [r3, #0] 800ab76: 009b lsls r3, r3, #2 800ab78: 4413 add r3, r2 800ab7a: 881b ldrh r3, [r3, #0] 800ab7c: b29b uxth r3, r3 800ab7e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ab82: f023 0340 bic.w r3, r3, #64 @ 0x40 800ab86: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 800ab8a: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800ab8e: f083 0320 eor.w r3, r3, #32 800ab92: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 800ab96: 68fb ldr r3, [r7, #12] 800ab98: 681b ldr r3, [r3, #0] 800ab9a: 461a mov r2, r3 800ab9c: 68bb ldr r3, [r7, #8] 800ab9e: 781b ldrb r3, [r3, #0] 800aba0: 009b lsls r3, r3, #2 800aba2: 441a add r2, r3 800aba4: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800aba8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800abac: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800abb0: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800abb4: f043 0380 orr.w r3, r3, #128 @ 0x80 800abb8: b29b uxth r3, r3 800abba: 8013 strh r3, [r2, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); 800abbc: 68bb ldr r3, [r7, #8] 800abbe: 781b ldrb r3, [r3, #0] 800abc0: 4619 mov r1, r3 800abc2: 68f8 ldr r0, [r7, #12] 800abc4: f00e f90b bl 8018dde #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* need to Free USB Buff */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) 800abc8: 88fb ldrh r3, [r7, #6] 800abca: f403 4380 and.w r3, r3, #16384 @ 0x4000 800abce: 2b00 cmp r3, #0 800abd0: d121 bne.n 800ac16 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 800abd2: 68fb ldr r3, [r7, #12] 800abd4: 681b ldr r3, [r3, #0] 800abd6: 461a mov r2, r3 800abd8: 68bb ldr r3, [r7, #8] 800abda: 781b ldrb r3, [r3, #0] 800abdc: 009b lsls r3, r3, #2 800abde: 4413 add r3, r2 800abe0: 881b ldrh r3, [r3, #0] 800abe2: b29b uxth r3, r3 800abe4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800abe8: f023 0370 bic.w r3, r3, #112 @ 0x70 800abec: f8a7 3092 strh.w r3, [r7, #146] @ 0x92 800abf0: 68fb ldr r3, [r7, #12] 800abf2: 681b ldr r3, [r3, #0] 800abf4: 461a mov r2, r3 800abf6: 68bb ldr r3, [r7, #8] 800abf8: 781b ldrb r3, [r3, #0] 800abfa: 009b lsls r3, r3, #2 800abfc: 441a add r2, r3 800abfe: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 800ac02: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ac06: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ac0a: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800ac0e: f043 0380 orr.w r3, r3, #128 @ 0x80 800ac12: b29b uxth r3, r3 800ac14: 8013 strh r3, [r2, #0] } return HAL_OK; 800ac16: 2300 movs r3, #0 800ac18: e113 b.n 800ae42 } else /* Transfer is not yet Done */ { /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) 800ac1a: 88fb ldrh r3, [r7, #6] 800ac1c: f403 4380 and.w r3, r3, #16384 @ 0x4000 800ac20: 2b00 cmp r3, #0 800ac22: d121 bne.n 800ac68 { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); 800ac24: 68fb ldr r3, [r7, #12] 800ac26: 681b ldr r3, [r3, #0] 800ac28: 461a mov r2, r3 800ac2a: 68bb ldr r3, [r7, #8] 800ac2c: 781b ldrb r3, [r3, #0] 800ac2e: 009b lsls r3, r3, #2 800ac30: 4413 add r3, r2 800ac32: 881b ldrh r3, [r3, #0] 800ac34: b29b uxth r3, r3 800ac36: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ac3a: f023 0370 bic.w r3, r3, #112 @ 0x70 800ac3e: f8a7 3056 strh.w r3, [r7, #86] @ 0x56 800ac42: 68fb ldr r3, [r7, #12] 800ac44: 681b ldr r3, [r3, #0] 800ac46: 461a mov r2, r3 800ac48: 68bb ldr r3, [r7, #8] 800ac4a: 781b ldrb r3, [r3, #0] 800ac4c: 009b lsls r3, r3, #2 800ac4e: 441a add r2, r3 800ac50: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56 800ac54: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ac58: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ac5c: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800ac60: f043 0380 orr.w r3, r3, #128 @ 0x80 800ac64: b29b uxth r3, r3 800ac66: 8013 strh r3, [r2, #0] } /* Still there is data to Fill in the next Buffer */ if (ep->xfer_fill_db == 1U) 800ac68: 68bb ldr r3, [r7, #8] 800ac6a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800ac6e: 2b01 cmp r3, #1 800ac70: f040 80be bne.w 800adf0 { ep->xfer_buff += TxPctSize; 800ac74: 68bb ldr r3, [r7, #8] 800ac76: 695a ldr r2, [r3, #20] 800ac78: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800ac7c: 441a add r2, r3 800ac7e: 68bb ldr r3, [r7, #8] 800ac80: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; 800ac82: 68bb ldr r3, [r7, #8] 800ac84: 69da ldr r2, [r3, #28] 800ac86: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800ac8a: 441a add r2, r3 800ac8c: 68bb ldr r3, [r7, #8] 800ac8e: 61da str r2, [r3, #28] /* Calculate the len of the new buffer to fill */ if (ep->xfer_len_db >= ep->maxpacket) 800ac90: 68bb ldr r3, [r7, #8] 800ac92: 6a1a ldr r2, [r3, #32] 800ac94: 68bb ldr r3, [r7, #8] 800ac96: 691b ldr r3, [r3, #16] 800ac98: 429a cmp r2, r3 800ac9a: d309 bcc.n 800acb0 { len = ep->maxpacket; 800ac9c: 68bb ldr r3, [r7, #8] 800ac9e: 691b ldr r3, [r3, #16] 800aca0: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_len_db -= len; 800aca2: 68bb ldr r3, [r7, #8] 800aca4: 6a1a ldr r2, [r3, #32] 800aca6: 6dbb ldr r3, [r7, #88] @ 0x58 800aca8: 1ad2 subs r2, r2, r3 800acaa: 68bb ldr r3, [r7, #8] 800acac: 621a str r2, [r3, #32] 800acae: e015 b.n 800acdc } else if (ep->xfer_len_db == 0U) 800acb0: 68bb ldr r3, [r7, #8] 800acb2: 6a1b ldr r3, [r3, #32] 800acb4: 2b00 cmp r3, #0 800acb6: d107 bne.n 800acc8 { len = TxPctSize; 800acb8: f8b7 3096 ldrh.w r3, [r7, #150] @ 0x96 800acbc: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_fill_db = 0U; 800acbe: 68bb ldr r3, [r7, #8] 800acc0: 2200 movs r2, #0 800acc2: f883 2024 strb.w r2, [r3, #36] @ 0x24 800acc6: e009 b.n 800acdc } else { len = ep->xfer_len_db; 800acc8: 68bb ldr r3, [r7, #8] 800acca: 6a1b ldr r3, [r3, #32] 800accc: 65bb str r3, [r7, #88] @ 0x58 ep->xfer_len_db = 0U; 800acce: 68bb ldr r3, [r7, #8] 800acd0: 2200 movs r2, #0 800acd2: 621a str r2, [r3, #32] ep->xfer_fill_db = 0; 800acd4: 68bb ldr r3, [r7, #8] 800acd6: 2200 movs r2, #0 800acd8: f883 2024 strb.w r2, [r3, #36] @ 0x24 } /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); 800acdc: 68fb ldr r3, [r7, #12] 800acde: 681b ldr r3, [r3, #0] 800ace0: 65fb str r3, [r7, #92] @ 0x5c 800ace2: 68bb ldr r3, [r7, #8] 800ace4: 785b ldrb r3, [r3, #1] 800ace6: 2b00 cmp r3, #0 800ace8: d15f bne.n 800adaa 800acea: 68fb ldr r3, [r7, #12] 800acec: 681b ldr r3, [r3, #0] 800acee: 66bb str r3, [r7, #104] @ 0x68 800acf0: 68fb ldr r3, [r7, #12] 800acf2: 681b ldr r3, [r3, #0] 800acf4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800acf8: b29b uxth r3, r3 800acfa: 461a mov r2, r3 800acfc: 6ebb ldr r3, [r7, #104] @ 0x68 800acfe: 4413 add r3, r2 800ad00: 66bb str r3, [r7, #104] @ 0x68 800ad02: 68bb ldr r3, [r7, #8] 800ad04: 781b ldrb r3, [r3, #0] 800ad06: 00da lsls r2, r3, #3 800ad08: 6ebb ldr r3, [r7, #104] @ 0x68 800ad0a: 4413 add r3, r2 800ad0c: f203 4306 addw r3, r3, #1030 @ 0x406 800ad10: 667b str r3, [r7, #100] @ 0x64 800ad12: 6e7b ldr r3, [r7, #100] @ 0x64 800ad14: 881b ldrh r3, [r3, #0] 800ad16: b29b uxth r3, r3 800ad18: f3c3 0309 ubfx r3, r3, #0, #10 800ad1c: b29a uxth r2, r3 800ad1e: 6e7b ldr r3, [r7, #100] @ 0x64 800ad20: 801a strh r2, [r3, #0] 800ad22: 6dbb ldr r3, [r7, #88] @ 0x58 800ad24: 2b00 cmp r3, #0 800ad26: d10a bne.n 800ad3e 800ad28: 6e7b ldr r3, [r7, #100] @ 0x64 800ad2a: 881b ldrh r3, [r3, #0] 800ad2c: b29b uxth r3, r3 800ad2e: ea6f 4343 mvn.w r3, r3, lsl #17 800ad32: ea6f 4353 mvn.w r3, r3, lsr #17 800ad36: b29a uxth r2, r3 800ad38: 6e7b ldr r3, [r7, #100] @ 0x64 800ad3a: 801a strh r2, [r3, #0] 800ad3c: e04e b.n 800addc 800ad3e: 6dbb ldr r3, [r7, #88] @ 0x58 800ad40: 2b3e cmp r3, #62 @ 0x3e 800ad42: d816 bhi.n 800ad72 800ad44: 6dbb ldr r3, [r7, #88] @ 0x58 800ad46: 085b lsrs r3, r3, #1 800ad48: 663b str r3, [r7, #96] @ 0x60 800ad4a: 6dbb ldr r3, [r7, #88] @ 0x58 800ad4c: f003 0301 and.w r3, r3, #1 800ad50: 2b00 cmp r3, #0 800ad52: d002 beq.n 800ad5a 800ad54: 6e3b ldr r3, [r7, #96] @ 0x60 800ad56: 3301 adds r3, #1 800ad58: 663b str r3, [r7, #96] @ 0x60 800ad5a: 6e7b ldr r3, [r7, #100] @ 0x64 800ad5c: 881b ldrh r3, [r3, #0] 800ad5e: b29a uxth r2, r3 800ad60: 6e3b ldr r3, [r7, #96] @ 0x60 800ad62: b29b uxth r3, r3 800ad64: 029b lsls r3, r3, #10 800ad66: b29b uxth r3, r3 800ad68: 4313 orrs r3, r2 800ad6a: b29a uxth r2, r3 800ad6c: 6e7b ldr r3, [r7, #100] @ 0x64 800ad6e: 801a strh r2, [r3, #0] 800ad70: e034 b.n 800addc 800ad72: 6dbb ldr r3, [r7, #88] @ 0x58 800ad74: 095b lsrs r3, r3, #5 800ad76: 663b str r3, [r7, #96] @ 0x60 800ad78: 6dbb ldr r3, [r7, #88] @ 0x58 800ad7a: f003 031f and.w r3, r3, #31 800ad7e: 2b00 cmp r3, #0 800ad80: d102 bne.n 800ad88 800ad82: 6e3b ldr r3, [r7, #96] @ 0x60 800ad84: 3b01 subs r3, #1 800ad86: 663b str r3, [r7, #96] @ 0x60 800ad88: 6e7b ldr r3, [r7, #100] @ 0x64 800ad8a: 881b ldrh r3, [r3, #0] 800ad8c: b29a uxth r2, r3 800ad8e: 6e3b ldr r3, [r7, #96] @ 0x60 800ad90: b29b uxth r3, r3 800ad92: 029b lsls r3, r3, #10 800ad94: b29b uxth r3, r3 800ad96: 4313 orrs r3, r2 800ad98: b29b uxth r3, r3 800ad9a: ea6f 4343 mvn.w r3, r3, lsl #17 800ad9e: ea6f 4353 mvn.w r3, r3, lsr #17 800ada2: b29a uxth r2, r3 800ada4: 6e7b ldr r3, [r7, #100] @ 0x64 800ada6: 801a strh r2, [r3, #0] 800ada8: e018 b.n 800addc 800adaa: 68bb ldr r3, [r7, #8] 800adac: 785b ldrb r3, [r3, #1] 800adae: 2b01 cmp r3, #1 800adb0: d114 bne.n 800addc 800adb2: 68fb ldr r3, [r7, #12] 800adb4: 681b ldr r3, [r3, #0] 800adb6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800adba: b29b uxth r3, r3 800adbc: 461a mov r2, r3 800adbe: 6dfb ldr r3, [r7, #92] @ 0x5c 800adc0: 4413 add r3, r2 800adc2: 65fb str r3, [r7, #92] @ 0x5c 800adc4: 68bb ldr r3, [r7, #8] 800adc6: 781b ldrb r3, [r3, #0] 800adc8: 00da lsls r2, r3, #3 800adca: 6dfb ldr r3, [r7, #92] @ 0x5c 800adcc: 4413 add r3, r2 800adce: f203 4306 addw r3, r3, #1030 @ 0x406 800add2: 66fb str r3, [r7, #108] @ 0x6c 800add4: 6dbb ldr r3, [r7, #88] @ 0x58 800add6: b29a uxth r2, r3 800add8: 6efb ldr r3, [r7, #108] @ 0x6c 800adda: 801a strh r2, [r3, #0] /* Copy the user buffer to USB PMA */ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); 800addc: 68fb ldr r3, [r7, #12] 800adde: 6818 ldr r0, [r3, #0] 800ade0: 68bb ldr r3, [r7, #8] 800ade2: 6959 ldr r1, [r3, #20] 800ade4: 68bb ldr r3, [r7, #8] 800ade6: 895a ldrh r2, [r3, #10] 800ade8: 6dbb ldr r3, [r7, #88] @ 0x58 800adea: b29b uxth r3, r3 800adec: f005 ffe7 bl 8010dbe } } } /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); 800adf0: 68fb ldr r3, [r7, #12] 800adf2: 681b ldr r3, [r3, #0] 800adf4: 461a mov r2, r3 800adf6: 68bb ldr r3, [r7, #8] 800adf8: 781b ldrb r3, [r3, #0] 800adfa: 009b lsls r3, r3, #2 800adfc: 4413 add r3, r2 800adfe: 881b ldrh r3, [r3, #0] 800ae00: b29b uxth r3, r3 800ae02: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ae06: f023 0340 bic.w r3, r3, #64 @ 0x40 800ae0a: 82fb strh r3, [r7, #22] 800ae0c: 8afb ldrh r3, [r7, #22] 800ae0e: f083 0310 eor.w r3, r3, #16 800ae12: 82fb strh r3, [r7, #22] 800ae14: 8afb ldrh r3, [r7, #22] 800ae16: f083 0320 eor.w r3, r3, #32 800ae1a: 82fb strh r3, [r7, #22] 800ae1c: 68fb ldr r3, [r7, #12] 800ae1e: 681b ldr r3, [r3, #0] 800ae20: 461a mov r2, r3 800ae22: 68bb ldr r3, [r7, #8] 800ae24: 781b ldrb r3, [r3, #0] 800ae26: 009b lsls r3, r3, #2 800ae28: 441a add r2, r3 800ae2a: 8afb ldrh r3, [r7, #22] 800ae2c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ae30: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ae34: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ae38: f043 0380 orr.w r3, r3, #128 @ 0x80 800ae3c: b29b uxth r3, r3 800ae3e: 8013 strh r3, [r2, #0] return HAL_OK; 800ae40: 2300 movs r3, #0 } 800ae42: 4618 mov r0, r3 800ae44: 3798 adds r7, #152 @ 0x98 800ae46: 46bd mov sp, r7 800ae48: bd80 pop {r7, pc} 0800ae4a : * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress) { 800ae4a: b480 push {r7} 800ae4c: b087 sub sp, #28 800ae4e: af00 add r7, sp, #0 800ae50: 60f8 str r0, [r7, #12] 800ae52: 607b str r3, [r7, #4] 800ae54: 460b mov r3, r1 800ae56: 817b strh r3, [r7, #10] 800ae58: 4613 mov r3, r2 800ae5a: 813b strh r3, [r7, #8] PCD_EPTypeDef *ep; /* Initialize ep structure */ if ((0x80U & ep_addr) == 0x80U) 800ae5c: 897b ldrh r3, [r7, #10] 800ae5e: f003 0380 and.w r3, r3, #128 @ 0x80 800ae62: b29b uxth r3, r3 800ae64: 2b00 cmp r3, #0 800ae66: d00b beq.n 800ae80 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800ae68: 897b ldrh r3, [r7, #10] 800ae6a: f003 0207 and.w r2, r3, #7 800ae6e: 4613 mov r3, r2 800ae70: 009b lsls r3, r3, #2 800ae72: 4413 add r3, r2 800ae74: 00db lsls r3, r3, #3 800ae76: 3310 adds r3, #16 800ae78: 68fa ldr r2, [r7, #12] 800ae7a: 4413 add r3, r2 800ae7c: 617b str r3, [r7, #20] 800ae7e: e009 b.n 800ae94 } else { ep = &hpcd->OUT_ep[ep_addr]; 800ae80: 897a ldrh r2, [r7, #10] 800ae82: 4613 mov r3, r2 800ae84: 009b lsls r3, r3, #2 800ae86: 4413 add r3, r2 800ae88: 00db lsls r3, r3, #3 800ae8a: f503 73a8 add.w r3, r3, #336 @ 0x150 800ae8e: 68fa ldr r2, [r7, #12] 800ae90: 4413 add r3, r2 800ae92: 617b str r3, [r7, #20] } /* Here we check if the endpoint is single or double Buffer*/ if (ep_kind == PCD_SNG_BUF) 800ae94: 893b ldrh r3, [r7, #8] 800ae96: 2b00 cmp r3, #0 800ae98: d107 bne.n 800aeaa { /* Single Buffer */ ep->doublebuffer = 0U; 800ae9a: 697b ldr r3, [r7, #20] 800ae9c: 2200 movs r2, #0 800ae9e: 731a strb r2, [r3, #12] /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; 800aea0: 687b ldr r3, [r7, #4] 800aea2: b29a uxth r2, r3 800aea4: 697b ldr r3, [r7, #20] 800aea6: 80da strh r2, [r3, #6] 800aea8: e00b b.n 800aec2 } #if (USE_USB_DOUBLE_BUFFER == 1U) else /* USB_DBL_BUF */ { /* Double Buffer Endpoint */ ep->doublebuffer = 1U; 800aeaa: 697b ldr r3, [r7, #20] 800aeac: 2201 movs r2, #1 800aeae: 731a strb r2, [r3, #12] /* Configure the PMA */ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); 800aeb0: 687b ldr r3, [r7, #4] 800aeb2: b29a uxth r2, r3 800aeb4: 697b ldr r3, [r7, #20] 800aeb6: 811a strh r2, [r3, #8] ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); 800aeb8: 687b ldr r3, [r7, #4] 800aeba: 0c1b lsrs r3, r3, #16 800aebc: b29a uxth r2, r3 800aebe: 697b ldr r3, [r7, #20] 800aec0: 815a strh r2, [r3, #10] } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; 800aec2: 2300 movs r3, #0 } 800aec4: 4618 mov r0, r3 800aec6: 371c adds r7, #28 800aec8: 46bd mov sp, r7 800aeca: f85d 7b04 ldr.w r7, [sp], #4 800aece: 4770 bx lr 0800aed0 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 800aed0: b480 push {r7} 800aed2: b085 sub sp, #20 800aed4: af00 add r7, sp, #0 800aed6: 6078 str r0, [r7, #4] USB_TypeDef *USBx = hpcd->Instance; 800aed8: 687b ldr r3, [r7, #4] 800aeda: 681b ldr r3, [r3, #0] 800aedc: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 800aede: 687b ldr r3, [r7, #4] 800aee0: 2201 movs r2, #1 800aee2: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 hpcd->LPM_State = LPM_L0; 800aee6: 687b ldr r3, [r7, #4] 800aee8: 2200 movs r2, #0 800aeea: f883 22c8 strb.w r2, [r3, #712] @ 0x2c8 USBx->LPMCSR |= USB_LPMCSR_LMPEN; 800aeee: 68fb ldr r3, [r7, #12] 800aef0: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 800aef4: b29b uxth r3, r3 800aef6: f043 0301 orr.w r3, r3, #1 800aefa: b29a uxth r2, r3 800aefc: 68fb ldr r3, [r7, #12] 800aefe: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 USBx->LPMCSR |= USB_LPMCSR_LPMACK; 800af02: 68fb ldr r3, [r7, #12] 800af04: f8b3 3054 ldrh.w r3, [r3, #84] @ 0x54 800af08: b29b uxth r3, r3 800af0a: f043 0302 orr.w r3, r3, #2 800af0e: b29a uxth r2, r3 800af10: 68fb ldr r3, [r7, #12] 800af12: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 return HAL_OK; 800af16: 2300 movs r3, #0 } 800af18: 4618 mov r0, r3 800af1a: 3714 adds r7, #20 800af1c: 46bd mov sp, r7 800af1e: f85d 7b04 ldr.w r7, [sp], #4 800af22: 4770 bx lr 0800af24 : * @note LSEON bit that switches on and off the LSE crystal belongs as well to the * back-up domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 800af24: b480 push {r7} 800af26: af00 add r7, sp, #0 SET_BIT(PWR->CR1, PWR_CR1_DBP); 800af28: 4b05 ldr r3, [pc, #20] @ (800af40 ) 800af2a: 681b ldr r3, [r3, #0] 800af2c: 4a04 ldr r2, [pc, #16] @ (800af40 ) 800af2e: f443 7380 orr.w r3, r3, #256 @ 0x100 800af32: 6013 str r3, [r2, #0] } 800af34: bf00 nop 800af36: 46bd mov sp, r7 800af38: f85d 7b04 ldr.w r7, [sp], #4 800af3c: 4770 bx lr 800af3e: bf00 nop 800af40: 58000400 .word 0x58000400 0800af44 : /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) */ uint32_t HAL_PWREx_GetVoltageRange(void) { 800af44: b480 push {r7} 800af46: af00 add r7, sp, #0 return (PWR->CR1 & PWR_CR1_VOS); 800af48: 4b04 ldr r3, [pc, #16] @ (800af5c ) 800af4a: 681b ldr r3, [r3, #0] 800af4c: f403 63c0 and.w r3, r3, #1536 @ 0x600 } 800af50: 4618 mov r0, r3 800af52: 46bd mov sp, r7 800af54: f85d 7b04 ldr.w r7, [sp], #4 800af58: 4770 bx lr 800af5a: bf00 nop 800af5c: 58000400 .word 0x58000400 0800af60 : * @brief Enable VDDUSB supply. * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. * @retval None */ void HAL_PWREx_EnableVddUSB(void) { 800af60: b480 push {r7} 800af62: af00 add r7, sp, #0 SET_BIT(PWR->CR2, PWR_CR2_USV); 800af64: 4b05 ldr r3, [pc, #20] @ (800af7c ) 800af66: 685b ldr r3, [r3, #4] 800af68: 4a04 ldr r2, [pc, #16] @ (800af7c ) 800af6a: f443 6380 orr.w r3, r3, #1024 @ 0x400 800af6e: 6053 str r3, [r2, #4] } 800af70: bf00 nop 800af72: 46bd mov sp, r7 800af74: f85d 7b04 ldr.w r7, [sp], #4 800af78: 4770 bx lr 800af7a: bf00 nop 800af7c: 58000400 .word 0x58000400 0800af80 : { 800af80: b480 push {r7} 800af82: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); 800af84: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800af88: 681b ldr r3, [r3, #0] 800af8a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800af8e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800af92: d101 bne.n 800af98 800af94: 2301 movs r3, #1 800af96: e000 b.n 800af9a 800af98: 2300 movs r3, #0 } 800af9a: 4618 mov r0, r3 800af9c: 46bd mov sp, r7 800af9e: f85d 7b04 ldr.w r7, [sp], #4 800afa2: 4770 bx lr 0800afa4 : { 800afa4: b480 push {r7} 800afa6: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSEON); 800afa8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800afac: 681b ldr r3, [r3, #0] 800afae: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800afb2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800afb6: 6013 str r3, [r2, #0] } 800afb8: bf00 nop 800afba: 46bd mov sp, r7 800afbc: f85d 7b04 ldr.w r7, [sp], #4 800afc0: 4770 bx lr 0800afc2 : { 800afc2: b480 push {r7} 800afc4: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 800afc6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800afca: 681b ldr r3, [r3, #0] 800afcc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800afd0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800afd4: 6013 str r3, [r2, #0] } 800afd6: bf00 nop 800afd8: 46bd mov sp, r7 800afda: f85d 7b04 ldr.w r7, [sp], #4 800afde: 4770 bx lr 0800afe0 : { 800afe0: b480 push {r7} 800afe2: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); 800afe4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800afe8: 681b ldr r3, [r3, #0] 800afea: f403 3300 and.w r3, r3, #131072 @ 0x20000 800afee: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800aff2: d101 bne.n 800aff8 800aff4: 2301 movs r3, #1 800aff6: e000 b.n 800affa 800aff8: 2300 movs r3, #0 } 800affa: 4618 mov r0, r3 800affc: 46bd mov sp, r7 800affe: f85d 7b04 ldr.w r7, [sp], #4 800b002: 4770 bx lr 0800b004 : { 800b004: b480 push {r7} 800b006: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSION); 800b008: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b00c: 681b ldr r3, [r3, #0] 800b00e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b012: f443 7380 orr.w r3, r3, #256 @ 0x100 800b016: 6013 str r3, [r2, #0] } 800b018: bf00 nop 800b01a: 46bd mov sp, r7 800b01c: f85d 7b04 ldr.w r7, [sp], #4 800b020: 4770 bx lr 0800b022 : { 800b022: b480 push {r7} 800b024: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 800b026: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b02a: 681b ldr r3, [r3, #0] 800b02c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b030: f423 7380 bic.w r3, r3, #256 @ 0x100 800b034: 6013 str r3, [r2, #0] } 800b036: bf00 nop 800b038: 46bd mov sp, r7 800b03a: f85d 7b04 ldr.w r7, [sp], #4 800b03e: 4770 bx lr 0800b040 : { 800b040: b480 push {r7} 800b042: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); 800b044: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b048: 681b ldr r3, [r3, #0] 800b04a: f403 6380 and.w r3, r3, #1024 @ 0x400 800b04e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800b052: d101 bne.n 800b058 800b054: 2301 movs r3, #1 800b056: e000 b.n 800b05a 800b058: 2300 movs r3, #0 } 800b05a: 4618 mov r0, r3 800b05c: 46bd mov sp, r7 800b05e: f85d 7b04 ldr.w r7, [sp], #4 800b062: 4770 bx lr 0800b064 : { 800b064: b480 push {r7} 800b066: b083 sub sp, #12 800b068: af00 add r7, sp, #0 800b06a: 6078 str r0, [r7, #4] MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); 800b06c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b070: 685b ldr r3, [r3, #4] 800b072: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800b076: 687b ldr r3, [r7, #4] 800b078: 061b lsls r3, r3, #24 800b07a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b07e: 4313 orrs r3, r2 800b080: 604b str r3, [r1, #4] } 800b082: bf00 nop 800b084: 370c adds r7, #12 800b086: 46bd mov sp, r7 800b088: f85d 7b04 ldr.w r7, [sp], #4 800b08c: 4770 bx lr 0800b08e : { 800b08e: b480 push {r7} 800b090: af00 add r7, sp, #0 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 800b092: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b096: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800b09a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b09e: f043 0301 orr.w r3, r3, #1 800b0a2: f8c2 3098 str.w r3, [r2, #152] @ 0x98 } 800b0a6: bf00 nop 800b0a8: 46bd mov sp, r7 800b0aa: f85d 7b04 ldr.w r7, [sp], #4 800b0ae: 4770 bx lr 0800b0b0 : { 800b0b0: b480 push {r7} 800b0b2: af00 add r7, sp, #0 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 800b0b4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b0b8: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800b0bc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b0c0: f023 0301 bic.w r3, r3, #1 800b0c4: f8c2 3098 str.w r3, [r2, #152] @ 0x98 } 800b0c8: bf00 nop 800b0ca: 46bd mov sp, r7 800b0cc: f85d 7b04 ldr.w r7, [sp], #4 800b0d0: 4770 bx lr 0800b0d2 : { 800b0d2: b480 push {r7} 800b0d4: af00 add r7, sp, #0 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL); 800b0d6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b0da: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800b0de: f003 0302 and.w r3, r3, #2 800b0e2: 2b02 cmp r3, #2 800b0e4: d101 bne.n 800b0ea 800b0e6: 2301 movs r3, #1 800b0e8: e000 b.n 800b0ec 800b0ea: 2300 movs r3, #0 } 800b0ec: 4618 mov r0, r3 800b0ee: 46bd mov sp, r7 800b0f0: f85d 7b04 ldr.w r7, [sp], #4 800b0f4: 4770 bx lr 0800b0f6 : { 800b0f6: b480 push {r7} 800b0f8: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 800b0fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b0fe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800b102: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b106: f043 0301 orr.w r3, r3, #1 800b10a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800b10e: bf00 nop 800b110: 46bd mov sp, r7 800b112: f85d 7b04 ldr.w r7, [sp], #4 800b116: 4770 bx lr 0800b118 : { 800b118: b480 push {r7} 800b11a: af00 add r7, sp, #0 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 800b11c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b120: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800b124: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b128: f023 0301 bic.w r3, r3, #1 800b12c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800b130: bf00 nop 800b132: 46bd mov sp, r7 800b134: f85d 7b04 ldr.w r7, [sp], #4 800b138: 4770 bx lr 0800b13a : { 800b13a: b480 push {r7} 800b13c: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 800b13e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b142: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800b146: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b14a: f043 0304 orr.w r3, r3, #4 800b14e: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800b152: bf00 nop 800b154: 46bd mov sp, r7 800b156: f85d 7b04 ldr.w r7, [sp], #4 800b15a: 4770 bx lr 0800b15c : { 800b15c: b480 push {r7} 800b15e: af00 add r7, sp, #0 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 800b160: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b164: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800b168: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b16c: f023 0304 bic.w r3, r3, #4 800b170: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800b174: bf00 nop 800b176: 46bd mov sp, r7 800b178: f85d 7b04 ldr.w r7, [sp], #4 800b17c: 4770 bx lr 0800b17e : { 800b17e: b480 push {r7} 800b180: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); 800b182: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b186: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800b18a: f003 0302 and.w r3, r3, #2 800b18e: 2b02 cmp r3, #2 800b190: d101 bne.n 800b196 800b192: 2301 movs r3, #1 800b194: e000 b.n 800b198 800b196: 2300 movs r3, #0 } 800b198: 4618 mov r0, r3 800b19a: 46bd mov sp, r7 800b19c: f85d 7b04 ldr.w r7, [sp], #4 800b1a0: 4770 bx lr 0800b1a2 : { 800b1a2: b480 push {r7} 800b1a4: af00 add r7, sp, #0 SET_BIT(RCC->CSR, RCC_CSR_LSI1ON); 800b1a6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b1aa: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800b1ae: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b1b2: f043 0301 orr.w r3, r3, #1 800b1b6: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 800b1ba: bf00 nop 800b1bc: 46bd mov sp, r7 800b1be: f85d 7b04 ldr.w r7, [sp], #4 800b1c2: 4770 bx lr 0800b1c4 : { 800b1c4: b480 push {r7} 800b1c6: af00 add r7, sp, #0 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON); 800b1c8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b1cc: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800b1d0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b1d4: f023 0301 bic.w r3, r3, #1 800b1d8: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 800b1dc: bf00 nop 800b1de: 46bd mov sp, r7 800b1e0: f85d 7b04 ldr.w r7, [sp], #4 800b1e4: 4770 bx lr 0800b1e6 : { 800b1e6: b480 push {r7} 800b1e8: af00 add r7, sp, #0 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL); 800b1ea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b1ee: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800b1f2: f003 0302 and.w r3, r3, #2 800b1f6: 2b02 cmp r3, #2 800b1f8: d101 bne.n 800b1fe 800b1fa: 2301 movs r3, #1 800b1fc: e000 b.n 800b200 800b1fe: 2300 movs r3, #0 } 800b200: 4618 mov r0, r3 800b202: 46bd mov sp, r7 800b204: f85d 7b04 ldr.w r7, [sp], #4 800b208: 4770 bx lr 0800b20a : { 800b20a: b480 push {r7} 800b20c: af00 add r7, sp, #0 SET_BIT(RCC->CSR, RCC_CSR_LSI2ON); 800b20e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b212: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800b216: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b21a: f043 0304 orr.w r3, r3, #4 800b21e: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 800b222: bf00 nop 800b224: 46bd mov sp, r7 800b226: f85d 7b04 ldr.w r7, [sp], #4 800b22a: 4770 bx lr 0800b22c : { 800b22c: b480 push {r7} 800b22e: af00 add r7, sp, #0 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON); 800b230: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b234: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800b238: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b23c: f023 0304 bic.w r3, r3, #4 800b240: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } 800b244: bf00 nop 800b246: 46bd mov sp, r7 800b248: f85d 7b04 ldr.w r7, [sp], #4 800b24c: 4770 bx lr 0800b24e : { 800b24e: b480 push {r7} 800b250: af00 add r7, sp, #0 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL); 800b252: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b256: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800b25a: f003 0308 and.w r3, r3, #8 800b25e: 2b08 cmp r3, #8 800b260: d101 bne.n 800b266 800b262: 2301 movs r3, #1 800b264: e000 b.n 800b268 800b266: 2300 movs r3, #0 } 800b268: 4618 mov r0, r3 800b26a: 46bd mov sp, r7 800b26c: f85d 7b04 ldr.w r7, [sp], #4 800b270: 4770 bx lr 0800b272 : { 800b272: b480 push {r7} 800b274: b083 sub sp, #12 800b276: af00 add r7, sp, #0 800b278: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos); 800b27a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b27e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800b282: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800b286: 687b ldr r3, [r7, #4] 800b288: 021b lsls r3, r3, #8 800b28a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b28e: 4313 orrs r3, r2 800b290: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } 800b294: bf00 nop 800b296: 370c adds r7, #12 800b298: 46bd mov sp, r7 800b29a: f85d 7b04 ldr.w r7, [sp], #4 800b29e: 4770 bx lr 0800b2a0 : { 800b2a0: b480 push {r7} 800b2a2: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSION); 800b2a4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b2a8: 681b ldr r3, [r3, #0] 800b2aa: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b2ae: f043 0301 orr.w r3, r3, #1 800b2b2: 6013 str r3, [r2, #0] } 800b2b4: bf00 nop 800b2b6: 46bd mov sp, r7 800b2b8: f85d 7b04 ldr.w r7, [sp], #4 800b2bc: 4770 bx lr 0800b2be : { 800b2be: b480 push {r7} 800b2c0: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_MSION); 800b2c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b2c6: 681b ldr r3, [r3, #0] 800b2c8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b2cc: f023 0301 bic.w r3, r3, #1 800b2d0: 6013 str r3, [r2, #0] } 800b2d2: bf00 nop 800b2d4: 46bd mov sp, r7 800b2d6: f85d 7b04 ldr.w r7, [sp], #4 800b2da: 4770 bx lr 0800b2dc : { 800b2dc: b480 push {r7} 800b2de: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); 800b2e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b2e4: 681b ldr r3, [r3, #0] 800b2e6: f003 0302 and.w r3, r3, #2 800b2ea: 2b02 cmp r3, #2 800b2ec: d101 bne.n 800b2f2 800b2ee: 2301 movs r3, #1 800b2f0: e000 b.n 800b2f4 800b2f2: 2300 movs r3, #0 } 800b2f4: 4618 mov r0, r3 800b2f6: 46bd mov sp, r7 800b2f8: f85d 7b04 ldr.w r7, [sp], #4 800b2fc: 4770 bx lr 0800b2fe : { 800b2fe: b480 push {r7} 800b300: b083 sub sp, #12 800b302: af00 add r7, sp, #0 800b304: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); 800b306: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b30a: 681b ldr r3, [r3, #0] 800b30c: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800b310: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b314: 687b ldr r3, [r7, #4] 800b316: 4313 orrs r3, r2 800b318: 600b str r3, [r1, #0] } 800b31a: bf00 nop 800b31c: 370c adds r7, #12 800b31e: 46bd mov sp, r7 800b320: f85d 7b04 ldr.w r7, [sp], #4 800b324: 4770 bx lr 0800b326 : { 800b326: b480 push {r7} 800b328: b083 sub sp, #12 800b32a: af00 add r7, sp, #0 uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); 800b32c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b330: 681b ldr r3, [r3, #0] 800b332: f003 03f0 and.w r3, r3, #240 @ 0xf0 800b336: 607b str r3, [r7, #4] if (msiRange > LL_RCC_MSIRANGE_11) 800b338: 687b ldr r3, [r7, #4] 800b33a: 2bb0 cmp r3, #176 @ 0xb0 800b33c: d901 bls.n 800b342 msiRange = LL_RCC_MSIRANGE_11; 800b33e: 23b0 movs r3, #176 @ 0xb0 800b340: 607b str r3, [r7, #4] return msiRange; 800b342: 687b ldr r3, [r7, #4] } 800b344: 4618 mov r0, r3 800b346: 370c adds r7, #12 800b348: 46bd mov sp, r7 800b34a: f85d 7b04 ldr.w r7, [sp], #4 800b34e: 4770 bx lr 0800b350 : { 800b350: b480 push {r7} 800b352: b083 sub sp, #12 800b354: af00 add r7, sp, #0 800b356: 6078 str r0, [r7, #4] MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); 800b358: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b35c: 685b ldr r3, [r3, #4] 800b35e: f423 427f bic.w r2, r3, #65280 @ 0xff00 800b362: 687b ldr r3, [r7, #4] 800b364: 021b lsls r3, r3, #8 800b366: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b36a: 4313 orrs r3, r2 800b36c: 604b str r3, [r1, #4] } 800b36e: bf00 nop 800b370: 370c adds r7, #12 800b372: 46bd mov sp, r7 800b374: f85d 7b04 ldr.w r7, [sp], #4 800b378: 4770 bx lr 0800b37a : { 800b37a: b480 push {r7} 800b37c: b083 sub sp, #12 800b37e: af00 add r7, sp, #0 800b380: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 800b382: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b386: 689b ldr r3, [r3, #8] 800b388: f023 0203 bic.w r2, r3, #3 800b38c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b390: 687b ldr r3, [r7, #4] 800b392: 4313 orrs r3, r2 800b394: 608b str r3, [r1, #8] } 800b396: bf00 nop 800b398: 370c adds r7, #12 800b39a: 46bd mov sp, r7 800b39c: f85d 7b04 ldr.w r7, [sp], #4 800b3a0: 4770 bx lr 0800b3a2 : { 800b3a2: b480 push {r7} 800b3a4: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 800b3a6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3aa: 689b ldr r3, [r3, #8] 800b3ac: f003 030c and.w r3, r3, #12 } 800b3b0: 4618 mov r0, r3 800b3b2: 46bd mov sp, r7 800b3b4: f85d 7b04 ldr.w r7, [sp], #4 800b3b8: 4770 bx lr 0800b3ba : { 800b3ba: b480 push {r7} 800b3bc: b083 sub sp, #12 800b3be: af00 add r7, sp, #0 800b3c0: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 800b3c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3c6: 689b ldr r3, [r3, #8] 800b3c8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800b3cc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b3d0: 687b ldr r3, [r7, #4] 800b3d2: 4313 orrs r3, r2 800b3d4: 608b str r3, [r1, #8] } 800b3d6: bf00 nop 800b3d8: 370c adds r7, #12 800b3da: 46bd mov sp, r7 800b3dc: f85d 7b04 ldr.w r7, [sp], #4 800b3e0: 4770 bx lr 0800b3e2 : { 800b3e2: b480 push {r7} 800b3e4: b083 sub sp, #12 800b3e6: af00 add r7, sp, #0 800b3e8: 6078 str r0, [r7, #4] MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler); 800b3ea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b3ee: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800b3f2: f023 02f0 bic.w r2, r3, #240 @ 0xf0 800b3f6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b3fa: 687b ldr r3, [r7, #4] 800b3fc: 4313 orrs r3, r2 800b3fe: f8c1 3108 str.w r3, [r1, #264] @ 0x108 } 800b402: bf00 nop 800b404: 370c adds r7, #12 800b406: 46bd mov sp, r7 800b408: f85d 7b04 ldr.w r7, [sp], #4 800b40c: 4770 bx lr 0800b40e : { 800b40e: b480 push {r7} 800b410: b083 sub sp, #12 800b412: af00 add r7, sp, #0 800b414: 6078 str r0, [r7, #4] MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); 800b416: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b41a: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800b41e: f023 020f bic.w r2, r3, #15 800b422: 687b ldr r3, [r7, #4] 800b424: 091b lsrs r3, r3, #4 800b426: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b42a: 4313 orrs r3, r2 800b42c: f8c1 3108 str.w r3, [r1, #264] @ 0x108 } 800b430: bf00 nop 800b432: 370c adds r7, #12 800b434: 46bd mov sp, r7 800b436: f85d 7b04 ldr.w r7, [sp], #4 800b43a: 4770 bx lr 0800b43c : { 800b43c: b480 push {r7} 800b43e: b083 sub sp, #12 800b440: af00 add r7, sp, #0 800b442: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 800b444: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b448: 689b ldr r3, [r3, #8] 800b44a: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800b44e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b452: 687b ldr r3, [r7, #4] 800b454: 4313 orrs r3, r2 800b456: 608b str r3, [r1, #8] } 800b458: bf00 nop 800b45a: 370c adds r7, #12 800b45c: 46bd mov sp, r7 800b45e: f85d 7b04 ldr.w r7, [sp], #4 800b462: 4770 bx lr 0800b464 : { 800b464: b480 push {r7} 800b466: b083 sub sp, #12 800b468: af00 add r7, sp, #0 800b46a: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 800b46c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b470: 689b ldr r3, [r3, #8] 800b472: f423 5260 bic.w r2, r3, #14336 @ 0x3800 800b476: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800b47a: 687b ldr r3, [r7, #4] 800b47c: 4313 orrs r3, r2 800b47e: 608b str r3, [r1, #8] } 800b480: bf00 nop 800b482: 370c adds r7, #12 800b484: 46bd mov sp, r7 800b486: f85d 7b04 ldr.w r7, [sp], #4 800b48a: 4770 bx lr 0800b48c : { 800b48c: b480 push {r7} 800b48e: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 800b490: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b494: 689b ldr r3, [r3, #8] 800b496: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 800b49a: 4618 mov r0, r3 800b49c: 46bd mov sp, r7 800b49e: f85d 7b04 ldr.w r7, [sp], #4 800b4a2: 4770 bx lr 0800b4a4 : { 800b4a4: b480 push {r7} 800b4a6: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE)); 800b4a8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4ac: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800b4b0: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 800b4b4: 4618 mov r0, r3 800b4b6: 46bd mov sp, r7 800b4b8: f85d 7b04 ldr.w r7, [sp], #4 800b4bc: 4770 bx lr 0800b4be : { 800b4be: b480 push {r7} 800b4c0: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); 800b4c2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4c6: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800b4ca: 011b lsls r3, r3, #4 800b4cc: f003 03f0 and.w r3, r3, #240 @ 0xf0 } 800b4d0: 4618 mov r0, r3 800b4d2: 46bd mov sp, r7 800b4d4: f85d 7b04 ldr.w r7, [sp], #4 800b4d8: 4770 bx lr 0800b4da : { 800b4da: b480 push {r7} 800b4dc: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 800b4de: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4e2: 689b ldr r3, [r3, #8] 800b4e4: f403 63e0 and.w r3, r3, #1792 @ 0x700 } 800b4e8: 4618 mov r0, r3 800b4ea: 46bd mov sp, r7 800b4ec: f85d 7b04 ldr.w r7, [sp], #4 800b4f0: 4770 bx lr 0800b4f2 : { 800b4f2: b480 push {r7} 800b4f4: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 800b4f6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b4fa: 689b ldr r3, [r3, #8] 800b4fc: f403 5360 and.w r3, r3, #14336 @ 0x3800 } 800b500: 4618 mov r0, r3 800b502: 46bd mov sp, r7 800b504: f85d 7b04 ldr.w r7, [sp], #4 800b508: 4770 bx lr 0800b50a : * @brief Enable PLL * @rmtoll CR PLLON LL_RCC_PLL_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Enable(void) { 800b50a: b480 push {r7} 800b50c: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_PLLON); 800b50e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b512: 681b ldr r3, [r3, #0] 800b514: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b518: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800b51c: 6013 str r3, [r2, #0] } 800b51e: bf00 nop 800b520: 46bd mov sp, r7 800b522: f85d 7b04 ldr.w r7, [sp], #4 800b526: 4770 bx lr 0800b528 : * @note Cannot be disabled if the PLL clock is used as the system clock * @rmtoll CR PLLON LL_RCC_PLL_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Disable(void) { 800b528: b480 push {r7} 800b52a: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 800b52c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b530: 681b ldr r3, [r3, #0] 800b532: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b536: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800b53a: 6013 str r3, [r2, #0] } 800b53c: bf00 nop 800b53e: 46bd mov sp, r7 800b540: f85d 7b04 ldr.w r7, [sp], #4 800b544: 4770 bx lr 0800b546 : * @brief Check if PLL Ready * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { 800b546: b480 push {r7} 800b548: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); 800b54a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b54e: 681b ldr r3, [r3, #0] 800b550: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b554: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800b558: d101 bne.n 800b55e 800b55a: 2301 movs r3, #1 800b55c: e000 b.n 800b560 800b55e: 2300 movs r3, #0 } 800b560: 4618 mov r0, r3 800b562: 46bd mov sp, r7 800b564: f85d 7b04 ldr.w r7, [sp], #4 800b568: 4770 bx lr 0800b56a : * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN * @retval Between 6 and 127 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) { 800b56a: b480 push {r7} 800b56c: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 800b56e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b572: 68db ldr r3, [r3, #12] 800b574: 0a1b lsrs r3, r3, #8 800b576: f003 037f and.w r3, r3, #127 @ 0x7f } 800b57a: 4618 mov r0, r3 800b57c: 46bd mov sp, r7 800b57e: f85d 7b04 ldr.w r7, [sp], #4 800b582: 4770 bx lr 0800b584 : * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @arg @ref LL_RCC_PLLR_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) { 800b584: b480 push {r7} 800b586: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); 800b588: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b58c: 68db ldr r3, [r3, #12] 800b58e: f003 4360 and.w r3, r3, #3758096384 @ 0xe0000000 } 800b592: 4618 mov r0, r3 800b594: 46bd mov sp, r7 800b596: f85d 7b04 ldr.w r7, [sp], #4 800b59a: 4770 bx lr 0800b59c : * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) { 800b59c: b480 push {r7} 800b59e: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 800b5a0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5a4: 68db ldr r3, [r3, #12] 800b5a6: f003 0370 and.w r3, r3, #112 @ 0x70 } 800b5aa: 4618 mov r0, r3 800b5ac: 46bd mov sp, r7 800b5ae: f85d 7b04 ldr.w r7, [sp], #4 800b5b2: 4770 bx lr 0800b5b4 : * @arg @ref LL_RCC_PLLSOURCE_MSI * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) { 800b5b4: b480 push {r7} 800b5b6: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 800b5b8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5bc: 68db ldr r3, [r3, #12] 800b5be: f003 0303 and.w r3, r3, #3 } 800b5c2: 4618 mov r0, r3 800b5c4: 46bd mov sp, r7 800b5c6: f85d 7b04 ldr.w r7, [sp], #4 800b5ca: 4770 bx lr 0800b5cc : * @brief Check if HCLK1 prescaler flag value has been applied or not * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) { 800b5cc: b480 push {r7} 800b5ce: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); 800b5d0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5d4: 689b ldr r3, [r3, #8] 800b5d6: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b5da: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b5de: d101 bne.n 800b5e4 800b5e0: 2301 movs r3, #1 800b5e2: e000 b.n 800b5e6 800b5e4: 2300 movs r3, #0 } 800b5e6: 4618 mov r0, r3 800b5e8: 46bd mov sp, r7 800b5ea: f85d 7b04 ldr.w r7, [sp], #4 800b5ee: 4770 bx lr 0800b5f0 : * @brief Check if HCLK2 prescaler flag value has been applied or not * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void) { 800b5f0: b480 push {r7} 800b5f2: af00 add r7, sp, #0 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL); 800b5f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5f8: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800b5fc: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b600: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800b604: d101 bne.n 800b60a 800b606: 2301 movs r3, #1 800b608: e000 b.n 800b60c 800b60a: 2300 movs r3, #0 } 800b60c: 4618 mov r0, r3 800b60e: 46bd mov sp, r7 800b610: f85d 7b04 ldr.w r7, [sp], #4 800b614: 4770 bx lr 0800b616 : * @brief Check if HCLK4 prescaler flag value has been applied or not * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) { 800b616: b480 push {r7} 800b618: af00 add r7, sp, #0 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); 800b61a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b61e: f8d3 3108 ldr.w r3, [r3, #264] @ 0x108 800b622: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b626: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b62a: d101 bne.n 800b630 800b62c: 2301 movs r3, #1 800b62e: e000 b.n 800b632 800b630: 2300 movs r3, #0 } 800b632: 4618 mov r0, r3 800b634: 46bd mov sp, r7 800b636: f85d 7b04 ldr.w r7, [sp], #4 800b63a: 4770 bx lr 0800b63c : * @brief Check if PLCK1 prescaler flag value has been applied or not * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) { 800b63c: b480 push {r7} 800b63e: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); 800b640: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b644: 689b ldr r3, [r3, #8] 800b646: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b64a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800b64e: d101 bne.n 800b654 800b650: 2301 movs r3, #1 800b652: e000 b.n 800b656 800b654: 2300 movs r3, #0 } 800b656: 4618 mov r0, r3 800b658: 46bd mov sp, r7 800b65a: f85d 7b04 ldr.w r7, [sp], #4 800b65e: 4770 bx lr 0800b660 : * @brief Check if PLCK2 prescaler flag value has been applied or not * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) { 800b660: b480 push {r7} 800b662: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); 800b664: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b668: 689b ldr r3, [r3, #8] 800b66a: f403 2380 and.w r3, r3, #262144 @ 0x40000 800b66e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800b672: d101 bne.n 800b678 800b674: 2301 movs r3, #1 800b676: e000 b.n 800b67a 800b678: 2300 movs r3, #0 } 800b67a: 4618 mov r0, r3 800b67c: 46bd mov sp, r7 800b67e: f85d 7b04 ldr.w r7, [sp], #4 800b682: 4770 bx lr 0800b684 : * @note The PLL is not disabled when used as system clock. * @note The PLL source is not updated when used as PLLSAI1 clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800b684: b590 push {r4, r7, lr} 800b686: b08d sub sp, #52 @ 0x34 800b688: af00 add r7, sp, #0 800b68a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800b68c: 687b ldr r3, [r7, #4] 800b68e: 2b00 cmp r3, #0 800b690: d101 bne.n 800b696 { return HAL_ERROR; 800b692: 2301 movs r3, #1 800b694: e363 b.n 800bd5e /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*----------------------------- MSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) 800b696: 687b ldr r3, [r7, #4] 800b698: 681b ldr r3, [r3, #0] 800b69a: f003 0320 and.w r3, r3, #32 800b69e: 2b00 cmp r3, #0 800b6a0: f000 808d beq.w 800b7be assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* When the MSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b6a4: f7ff fe7d bl 800b3a2 800b6a8: 62f8 str r0, [r7, #44] @ 0x2c const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); 800b6aa: f7ff ff83 bl 800b5b4 800b6ae: 62b8 str r0, [r7, #40] @ 0x28 if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) || 800b6b0: 6afb ldr r3, [r7, #44] @ 0x2c 800b6b2: 2b00 cmp r3, #0 800b6b4: d005 beq.n 800b6c2 800b6b6: 6afb ldr r3, [r7, #44] @ 0x2c 800b6b8: 2b0c cmp r3, #12 800b6ba: d147 bne.n 800b74c ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_MSI))) 800b6bc: 6abb ldr r3, [r7, #40] @ 0x28 800b6be: 2b01 cmp r3, #1 800b6c0: d144 bne.n 800b74c { if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) 800b6c2: 687b ldr r3, [r7, #4] 800b6c4: 69db ldr r3, [r3, #28] 800b6c6: 2b00 cmp r3, #0 800b6c8: d101 bne.n 800b6ce { return HAL_ERROR; 800b6ca: 2301 movs r3, #1 800b6cc: e347 b.n 800bd5e else { /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the AHB4 clock and the supply voltage of the device. */ if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) 800b6ce: 687b ldr r3, [r7, #4] 800b6d0: 6a5c ldr r4, [r3, #36] @ 0x24 800b6d2: f7ff fe28 bl 800b326 800b6d6: 4603 mov r3, r0 800b6d8: 429c cmp r4, r3 800b6da: d914 bls.n 800b706 { /* First increase number of wait states update if necessary */ if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 800b6dc: 687b ldr r3, [r7, #4] 800b6de: 6a5b ldr r3, [r3, #36] @ 0x24 800b6e0: 4618 mov r0, r3 800b6e2: f000 fd4b bl 800c17c 800b6e6: 4603 mov r3, r0 800b6e8: 2b00 cmp r3, #0 800b6ea: d001 beq.n 800b6f0 { return HAL_ERROR; 800b6ec: 2301 movs r3, #1 800b6ee: e336 b.n 800bd5e } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800b6f0: 687b ldr r3, [r7, #4] 800b6f2: 6a5b ldr r3, [r3, #36] @ 0x24 800b6f4: 4618 mov r0, r3 800b6f6: f7ff fe02 bl 800b2fe /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 800b6fa: 687b ldr r3, [r7, #4] 800b6fc: 6a1b ldr r3, [r3, #32] 800b6fe: 4618 mov r0, r3 800b700: f7ff fe26 bl 800b350 800b704: e013 b.n 800b72e } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800b706: 687b ldr r3, [r7, #4] 800b708: 6a5b ldr r3, [r3, #36] @ 0x24 800b70a: 4618 mov r0, r3 800b70c: f7ff fdf7 bl 800b2fe /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 800b710: 687b ldr r3, [r7, #4] 800b712: 6a1b ldr r3, [r3, #32] 800b714: 4618 mov r0, r3 800b716: f7ff fe1b bl 800b350 /* Decrease number of wait states update if necessary */ if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 800b71a: 687b ldr r3, [r7, #4] 800b71c: 6a5b ldr r3, [r3, #36] @ 0x24 800b71e: 4618 mov r0, r3 800b720: f000 fd2c bl 800c17c 800b724: 4603 mov r3, r0 800b726: 2b00 cmp r3, #0 800b728: d001 beq.n 800b72e { return HAL_ERROR; 800b72a: 2301 movs r3, #1 800b72c: e317 b.n 800bd5e } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); 800b72e: f000 fcc9 bl 800c0c4 800b732: 4603 mov r3, r0 800b734: 4aa4 ldr r2, [pc, #656] @ (800b9c8 ) 800b736: 6013 str r3, [r2, #0] if (HAL_InitTick(uwTickPrio) != HAL_OK) 800b738: 4ba4 ldr r3, [pc, #656] @ (800b9cc ) 800b73a: 681b ldr r3, [r3, #0] 800b73c: 4618 mov r0, r3 800b73e: f7fa fe9f bl 8006480 800b742: 4603 mov r3, r0 800b744: 2b00 cmp r3, #0 800b746: d039 beq.n 800b7bc { return HAL_ERROR; 800b748: 2301 movs r3, #1 800b74a: e308 b.n 800bd5e } } else { /* Check the MSI State */ if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) 800b74c: 687b ldr r3, [r7, #4] 800b74e: 69db ldr r3, [r3, #28] 800b750: 2b00 cmp r3, #0 800b752: d01e beq.n 800b792 { /* Enable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); 800b754: f7ff fda4 bl 800b2a0 /* Get timeout */ tickstart = HAL_GetTick(); 800b758: f7fb f8fa bl 8006950 800b75c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till MSI is ready */ while (LL_RCC_MSI_IsReady() == 0U) 800b75e: e008 b.n 800b772 { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 800b760: f7fb f8f6 bl 8006950 800b764: 4602 mov r2, r0 800b766: 6a7b ldr r3, [r7, #36] @ 0x24 800b768: 1ad3 subs r3, r2, r3 800b76a: 2b02 cmp r3, #2 800b76c: d901 bls.n 800b772 { return HAL_TIMEOUT; 800b76e: 2303 movs r3, #3 800b770: e2f5 b.n 800bd5e while (LL_RCC_MSI_IsReady() == 0U) 800b772: f7ff fdb3 bl 800b2dc 800b776: 4603 mov r3, r0 800b778: 2b00 cmp r3, #0 800b77a: d0f1 beq.n 800b760 } } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800b77c: 687b ldr r3, [r7, #4] 800b77e: 6a5b ldr r3, [r3, #36] @ 0x24 800b780: 4618 mov r0, r3 800b782: f7ff fdbc bl 800b2fe /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 800b786: 687b ldr r3, [r7, #4] 800b788: 6a1b ldr r3, [r3, #32] 800b78a: 4618 mov r0, r3 800b78c: f7ff fde0 bl 800b350 800b790: e015 b.n 800b7be } else { /* Disable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); 800b792: f7ff fd94 bl 800b2be /* Get timeout */ tickstart = HAL_GetTick(); 800b796: f7fb f8db bl 8006950 800b79a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till MSI is disabled */ while (LL_RCC_MSI_IsReady() != 0U) 800b79c: e008 b.n 800b7b0 { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 800b79e: f7fb f8d7 bl 8006950 800b7a2: 4602 mov r2, r0 800b7a4: 6a7b ldr r3, [r7, #36] @ 0x24 800b7a6: 1ad3 subs r3, r2, r3 800b7a8: 2b02 cmp r3, #2 800b7aa: d901 bls.n 800b7b0 { return HAL_TIMEOUT; 800b7ac: 2303 movs r3, #3 800b7ae: e2d6 b.n 800bd5e while (LL_RCC_MSI_IsReady() != 0U) 800b7b0: f7ff fd94 bl 800b2dc 800b7b4: 4603 mov r3, r0 800b7b6: 2b00 cmp r3, #0 800b7b8: d1f1 bne.n 800b79e 800b7ba: e000 b.n 800b7be if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) 800b7bc: bf00 nop } } } /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800b7be: 687b ldr r3, [r7, #4] 800b7c0: 681b ldr r3, [r3, #0] 800b7c2: f003 0301 and.w r3, r3, #1 800b7c6: 2b00 cmp r3, #0 800b7c8: d047 beq.n 800b85a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b7ca: f7ff fdea bl 800b3a2 800b7ce: 6238 str r0, [r7, #32] const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); 800b7d0: f7ff fef0 bl 800b5b4 800b7d4: 61f8 str r0, [r7, #28] if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || 800b7d6: 6a3b ldr r3, [r7, #32] 800b7d8: 2b08 cmp r3, #8 800b7da: d005 beq.n 800b7e8 800b7dc: 6a3b ldr r3, [r7, #32] 800b7de: 2b0c cmp r3, #12 800b7e0: d108 bne.n 800b7f4 ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSE))) 800b7e2: 69fb ldr r3, [r7, #28] 800b7e4: 2b03 cmp r3, #3 800b7e6: d105 bne.n 800b7f4 { if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) 800b7e8: 687b ldr r3, [r7, #4] 800b7ea: 685b ldr r3, [r3, #4] 800b7ec: 2b00 cmp r3, #0 800b7ee: d134 bne.n 800b85a { return HAL_ERROR; 800b7f0: 2301 movs r3, #1 800b7f2: e2b4 b.n 800bd5e } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800b7f4: 687b ldr r3, [r7, #4] 800b7f6: 685b ldr r3, [r3, #4] 800b7f8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b7fc: d102 bne.n 800b804 800b7fe: f7ff fbd1 bl 800afa4 800b802: e001 b.n 800b808 800b804: f7ff fbdd bl 800afc2 /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800b808: 687b ldr r3, [r7, #4] 800b80a: 685b ldr r3, [r3, #4] 800b80c: 2b00 cmp r3, #0 800b80e: d012 beq.n 800b836 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b810: f7fb f89e bl 8006950 800b814: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (LL_RCC_HSE_IsReady() == 0U) 800b816: e008 b.n 800b82a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800b818: f7fb f89a bl 8006950 800b81c: 4602 mov r2, r0 800b81e: 6a7b ldr r3, [r7, #36] @ 0x24 800b820: 1ad3 subs r3, r2, r3 800b822: 2b64 cmp r3, #100 @ 0x64 800b824: d901 bls.n 800b82a { return HAL_TIMEOUT; 800b826: 2303 movs r3, #3 800b828: e299 b.n 800bd5e while (LL_RCC_HSE_IsReady() == 0U) 800b82a: f7ff fbd9 bl 800afe0 800b82e: 4603 mov r3, r0 800b830: 2b00 cmp r3, #0 800b832: d0f1 beq.n 800b818 800b834: e011 b.n 800b85a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b836: f7fb f88b bl 8006950 800b83a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (LL_RCC_HSE_IsReady() != 0U) 800b83c: e008 b.n 800b850 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800b83e: f7fb f887 bl 8006950 800b842: 4602 mov r2, r0 800b844: 6a7b ldr r3, [r7, #36] @ 0x24 800b846: 1ad3 subs r3, r2, r3 800b848: 2b64 cmp r3, #100 @ 0x64 800b84a: d901 bls.n 800b850 { return HAL_TIMEOUT; 800b84c: 2303 movs r3, #3 800b84e: e286 b.n 800bd5e while (LL_RCC_HSE_IsReady() != 0U) 800b850: f7ff fbc6 bl 800afe0 800b854: 4603 mov r3, r0 800b856: 2b00 cmp r3, #0 800b858: d1f1 bne.n 800b83e } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800b85a: 687b ldr r3, [r7, #4] 800b85c: 681b ldr r3, [r3, #0] 800b85e: f003 0302 and.w r3, r3, #2 800b862: 2b00 cmp r3, #0 800b864: d04c beq.n 800b900 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b866: f7ff fd9c bl 800b3a2 800b86a: 61b8 str r0, [r7, #24] const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); 800b86c: f7ff fea2 bl 800b5b4 800b870: 6178 str r0, [r7, #20] if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || 800b872: 69bb ldr r3, [r7, #24] 800b874: 2b04 cmp r3, #4 800b876: d005 beq.n 800b884 800b878: 69bb ldr r3, [r7, #24] 800b87a: 2b0c cmp r3, #12 800b87c: d10e bne.n 800b89c ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSI))) 800b87e: 697b ldr r3, [r7, #20] 800b880: 2b02 cmp r3, #2 800b882: d10b bne.n 800b89c { /* When HSI is used as system clock it will not be disabled */ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) 800b884: 687b ldr r3, [r7, #4] 800b886: 68db ldr r3, [r3, #12] 800b888: 2b00 cmp r3, #0 800b88a: d101 bne.n 800b890 { return HAL_ERROR; 800b88c: 2301 movs r3, #1 800b88e: e266 b.n 800bd5e } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b890: 687b ldr r3, [r7, #4] 800b892: 691b ldr r3, [r3, #16] 800b894: 4618 mov r0, r3 800b896: f7ff fbe5 bl 800b064 if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) 800b89a: e031 b.n 800b900 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800b89c: 687b ldr r3, [r7, #4] 800b89e: 68db ldr r3, [r3, #12] 800b8a0: 2b00 cmp r3, #0 800b8a2: d019 beq.n 800b8d8 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 800b8a4: f7ff fbae bl 800b004 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b8a8: f7fb f852 bl 8006950 800b8ac: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (LL_RCC_HSI_IsReady() == 0U) 800b8ae: e008 b.n 800b8c2 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b8b0: f7fb f84e bl 8006950 800b8b4: 4602 mov r2, r0 800b8b6: 6a7b ldr r3, [r7, #36] @ 0x24 800b8b8: 1ad3 subs r3, r2, r3 800b8ba: 2b02 cmp r3, #2 800b8bc: d901 bls.n 800b8c2 { return HAL_TIMEOUT; 800b8be: 2303 movs r3, #3 800b8c0: e24d b.n 800bd5e while (LL_RCC_HSI_IsReady() == 0U) 800b8c2: f7ff fbbd bl 800b040 800b8c6: 4603 mov r3, r0 800b8c8: 2b00 cmp r3, #0 800b8ca: d0f1 beq.n 800b8b0 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b8cc: 687b ldr r3, [r7, #4] 800b8ce: 691b ldr r3, [r3, #16] 800b8d0: 4618 mov r0, r3 800b8d2: f7ff fbc7 bl 800b064 800b8d6: e013 b.n 800b900 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800b8d8: f7ff fba3 bl 800b022 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b8dc: f7fb f838 bl 8006950 800b8e0: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (LL_RCC_HSI_IsReady() != 0U) 800b8e2: e008 b.n 800b8f6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b8e4: f7fb f834 bl 8006950 800b8e8: 4602 mov r2, r0 800b8ea: 6a7b ldr r3, [r7, #36] @ 0x24 800b8ec: 1ad3 subs r3, r2, r3 800b8ee: 2b02 cmp r3, #2 800b8f0: d901 bls.n 800b8f6 { return HAL_TIMEOUT; 800b8f2: 2303 movs r3, #3 800b8f4: e233 b.n 800bd5e while (LL_RCC_HSI_IsReady() != 0U) 800b8f6: f7ff fba3 bl 800b040 800b8fa: 4603 mov r3, r0 800b8fc: 2b00 cmp r3, #0 800b8fe: d1f1 bne.n 800b8e4 } } } /*------------------------------ LSI Configuration (LSI1 or LSI2) -------------------------*/ if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ 800b900: 687b ldr r3, [r7, #4] 800b902: 681b ldr r3, [r3, #0] 800b904: f003 0308 and.w r3, r3, #8 800b908: 2b00 cmp r3, #0 800b90a: d106 bne.n 800b91a (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2)) 800b90c: 687b ldr r3, [r7, #4] 800b90e: 681b ldr r3, [r3, #0] 800b910: f003 0310 and.w r3, r3, #16 if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ 800b914: 2b00 cmp r3, #0 800b916: f000 80a3 beq.w 800ba60 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800b91a: 687b ldr r3, [r7, #4] 800b91c: 695b ldr r3, [r3, #20] 800b91e: 2b00 cmp r3, #0 800b920: d076 beq.n 800ba10 { /*------------------------------ LSI2 selected by default (when Switch ON) -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) 800b922: 687b ldr r3, [r7, #4] 800b924: 681b ldr r3, [r3, #0] 800b926: f003 0310 and.w r3, r3, #16 800b92a: 2b00 cmp r3, #0 800b92c: d046 beq.n 800b9bc { assert_param(IS_RCC_LSI2_CALIBRATION_VALUE(RCC_OscInitStruct->LSI2CalibrationValue)); /* 1. Check LSI1 state and enable if required */ if (LL_RCC_LSI1_IsReady() == 0U) 800b92e: f7ff fc5a bl 800b1e6 800b932: 4603 mov r3, r0 800b934: 2b00 cmp r3, #0 800b936: d113 bne.n 800b960 { /* This is required to enable LSI1 before enabling LSI2 */ __HAL_RCC_LSI1_ENABLE(); 800b938: f7ff fc33 bl 800b1a2 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b93c: f7fb f808 bl 8006950 800b940: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI1 is ready */ while (LL_RCC_LSI1_IsReady() == 0U) 800b942: e008 b.n 800b956 { if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) 800b944: f7fb f804 bl 8006950 800b948: 4602 mov r2, r0 800b94a: 6a7b ldr r3, [r7, #36] @ 0x24 800b94c: 1ad3 subs r3, r2, r3 800b94e: 2b02 cmp r3, #2 800b950: d901 bls.n 800b956 { return HAL_TIMEOUT; 800b952: 2303 movs r3, #3 800b954: e203 b.n 800bd5e while (LL_RCC_LSI1_IsReady() == 0U) 800b956: f7ff fc46 bl 800b1e6 800b95a: 4603 mov r3, r0 800b95c: 2b00 cmp r3, #0 800b95e: d0f1 beq.n 800b944 } } } /* 2. Enable the Internal Low Speed oscillator (LSI2) and set trimming value */ __HAL_RCC_LSI2_ENABLE(); 800b960: f7ff fc53 bl 800b20a /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b964: f7fa fff4 bl 8006950 800b968: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI2 is ready */ while (LL_RCC_LSI2_IsReady() == 0U) 800b96a: e008 b.n 800b97e { if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) 800b96c: f7fa fff0 bl 8006950 800b970: 4602 mov r2, r0 800b972: 6a7b ldr r3, [r7, #36] @ 0x24 800b974: 1ad3 subs r3, r2, r3 800b976: 2b03 cmp r3, #3 800b978: d901 bls.n 800b97e { return HAL_TIMEOUT; 800b97a: 2303 movs r3, #3 800b97c: e1ef b.n 800bd5e while (LL_RCC_LSI2_IsReady() == 0U) 800b97e: f7ff fc66 bl 800b24e 800b982: 4603 mov r3, r0 800b984: 2b00 cmp r3, #0 800b986: d0f1 beq.n 800b96c } } /* Adjusts the Internal Low Spee oscillator (LSI2) calibration value */ __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->LSI2CalibrationValue); 800b988: 687b ldr r3, [r7, #4] 800b98a: 699b ldr r3, [r3, #24] 800b98c: 4618 mov r0, r3 800b98e: f7ff fc70 bl 800b272 /* 3. Disable LSI1 */ /* LSI1 was initially not enable, require to disable it */ __HAL_RCC_LSI1_DISABLE(); 800b992: f7ff fc17 bl 800b1c4 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b996: f7fa ffdb bl 8006950 800b99a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI1 is disabled */ while (LL_RCC_LSI1_IsReady() != 0U) 800b99c: e008 b.n 800b9b0 { if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) 800b99e: f7fa ffd7 bl 8006950 800b9a2: 4602 mov r2, r0 800b9a4: 6a7b ldr r3, [r7, #36] @ 0x24 800b9a6: 1ad3 subs r3, r2, r3 800b9a8: 2b02 cmp r3, #2 800b9aa: d901 bls.n 800b9b0 { return HAL_TIMEOUT; 800b9ac: 2303 movs r3, #3 800b9ae: e1d6 b.n 800bd5e while (LL_RCC_LSI1_IsReady() != 0U) 800b9b0: f7ff fc19 bl 800b1e6 800b9b4: 4603 mov r3, r0 800b9b6: 2b00 cmp r3, #0 800b9b8: d1f1 bne.n 800b99e 800b9ba: e051 b.n 800ba60 else { /*------------------------------ LSI1 selected (only if LSI2 OFF)-------------------------*/ /* 1. Enable the Internal Low Speed oscillator (LSI1). */ __HAL_RCC_LSI1_ENABLE(); 800b9bc: f7ff fbf1 bl 800b1a2 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b9c0: f7fa ffc6 bl 8006950 800b9c4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI1 is ready */ while (LL_RCC_LSI1_IsReady() == 0U) 800b9c6: e00c b.n 800b9e2 800b9c8: 2000000c .word 0x2000000c 800b9cc: 20000010 .word 0x20000010 { if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) 800b9d0: f7fa ffbe bl 8006950 800b9d4: 4602 mov r2, r0 800b9d6: 6a7b ldr r3, [r7, #36] @ 0x24 800b9d8: 1ad3 subs r3, r2, r3 800b9da: 2b02 cmp r3, #2 800b9dc: d901 bls.n 800b9e2 { return HAL_TIMEOUT; 800b9de: 2303 movs r3, #3 800b9e0: e1bd b.n 800bd5e while (LL_RCC_LSI1_IsReady() == 0U) 800b9e2: f7ff fc00 bl 800b1e6 800b9e6: 4603 mov r3, r0 800b9e8: 2b00 cmp r3, #0 800b9ea: d0f1 beq.n 800b9d0 } } /*2. Switch OFF LSI2*/ /* Disable the Internal Low Speed oscillator (LSI2). */ __HAL_RCC_LSI2_DISABLE(); 800b9ec: f7ff fc1e bl 800b22c /* Wait till LSI2 is disabled */ while (LL_RCC_LSI2_IsReady() != 0U) 800b9f0: e008 b.n 800ba04 { if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) 800b9f2: f7fa ffad bl 8006950 800b9f6: 4602 mov r2, r0 800b9f8: 6a7b ldr r3, [r7, #36] @ 0x24 800b9fa: 1ad3 subs r3, r2, r3 800b9fc: 2b03 cmp r3, #3 800b9fe: d901 bls.n 800ba04 { return HAL_TIMEOUT; 800ba00: 2303 movs r3, #3 800ba02: e1ac b.n 800bd5e while (LL_RCC_LSI2_IsReady() != 0U) 800ba04: f7ff fc23 bl 800b24e 800ba08: 4603 mov r3, r0 800ba0a: 2b00 cmp r3, #0 800ba0c: d1f1 bne.n 800b9f2 800ba0e: e027 b.n 800ba60 } else { /* Disable the Internal Low Speed oscillator (LSI2). */ __HAL_RCC_LSI2_DISABLE(); 800ba10: f7ff fc0c bl 800b22c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba14: f7fa ff9c bl 8006950 800ba18: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI2 is disabled */ while (LL_RCC_LSI2_IsReady() != 0U) 800ba1a: e008 b.n 800ba2e { if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE) 800ba1c: f7fa ff98 bl 8006950 800ba20: 4602 mov r2, r0 800ba22: 6a7b ldr r3, [r7, #36] @ 0x24 800ba24: 1ad3 subs r3, r2, r3 800ba26: 2b03 cmp r3, #3 800ba28: d901 bls.n 800ba2e { return HAL_TIMEOUT; 800ba2a: 2303 movs r3, #3 800ba2c: e197 b.n 800bd5e while (LL_RCC_LSI2_IsReady() != 0U) 800ba2e: f7ff fc0e bl 800b24e 800ba32: 4603 mov r3, r0 800ba34: 2b00 cmp r3, #0 800ba36: d1f1 bne.n 800ba1c } } /* Disable the Internal Low Speed oscillator (LSI1). */ __HAL_RCC_LSI1_DISABLE(); 800ba38: f7ff fbc4 bl 800b1c4 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba3c: f7fa ff88 bl 8006950 800ba40: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI1 is disabled */ while (LL_RCC_LSI1_IsReady() != 0U) 800ba42: e008 b.n 800ba56 { if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) 800ba44: f7fa ff84 bl 8006950 800ba48: 4602 mov r2, r0 800ba4a: 6a7b ldr r3, [r7, #36] @ 0x24 800ba4c: 1ad3 subs r3, r2, r3 800ba4e: 2b02 cmp r3, #2 800ba50: d901 bls.n 800ba56 { return HAL_TIMEOUT; 800ba52: 2303 movs r3, #3 800ba54: e183 b.n 800bd5e while (LL_RCC_LSI1_IsReady() != 0U) 800ba56: f7ff fbc6 bl 800b1e6 800ba5a: 4603 mov r3, r0 800ba5c: 2b00 cmp r3, #0 800ba5e: d1f1 bne.n 800ba44 } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800ba60: 687b ldr r3, [r7, #4] 800ba62: 681b ldr r3, [r3, #0] 800ba64: f003 0304 and.w r3, r3, #4 800ba68: 2b00 cmp r3, #0 800ba6a: d05b beq.n 800bb24 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800ba6c: 4ba7 ldr r3, [pc, #668] @ (800bd0c ) 800ba6e: 681b ldr r3, [r3, #0] 800ba70: f403 7380 and.w r3, r3, #256 @ 0x100 800ba74: 2b00 cmp r3, #0 800ba76: d114 bne.n 800baa2 { /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); 800ba78: f7ff fa54 bl 800af24 /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800ba7c: f7fa ff68 bl 8006950 800ba80: 6278 str r0, [r7, #36] @ 0x24 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800ba82: e008 b.n 800ba96 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800ba84: f7fa ff64 bl 8006950 800ba88: 4602 mov r2, r0 800ba8a: 6a7b ldr r3, [r7, #36] @ 0x24 800ba8c: 1ad3 subs r3, r2, r3 800ba8e: 2b02 cmp r3, #2 800ba90: d901 bls.n 800ba96 { return HAL_TIMEOUT; 800ba92: 2303 movs r3, #3 800ba94: e163 b.n 800bd5e while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800ba96: 4b9d ldr r3, [pc, #628] @ (800bd0c ) 800ba98: 681b ldr r3, [r3, #0] 800ba9a: f403 7380 and.w r3, r3, #256 @ 0x100 800ba9e: 2b00 cmp r3, #0 800baa0: d0f0 beq.n 800ba84 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800baa2: 687b ldr r3, [r7, #4] 800baa4: 689b ldr r3, [r3, #8] 800baa6: 2b01 cmp r3, #1 800baa8: d102 bne.n 800bab0 800baaa: f7ff fb24 bl 800b0f6 800baae: e00c b.n 800baca 800bab0: 687b ldr r3, [r7, #4] 800bab2: 689b ldr r3, [r3, #8] 800bab4: 2b05 cmp r3, #5 800bab6: d104 bne.n 800bac2 800bab8: f7ff fb3f bl 800b13a 800babc: f7ff fb1b bl 800b0f6 800bac0: e003 b.n 800baca 800bac2: f7ff fb29 bl 800b118 800bac6: f7ff fb49 bl 800b15c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800baca: 687b ldr r3, [r7, #4] 800bacc: 689b ldr r3, [r3, #8] 800bace: 2b00 cmp r3, #0 800bad0: d014 beq.n 800bafc { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bad2: f7fa ff3d bl 8006950 800bad6: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() == 0U) 800bad8: e00a b.n 800baf0 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bada: f7fa ff39 bl 8006950 800bade: 4602 mov r2, r0 800bae0: 6a7b ldr r3, [r7, #36] @ 0x24 800bae2: 1ad3 subs r3, r2, r3 800bae4: f241 3288 movw r2, #5000 @ 0x1388 800bae8: 4293 cmp r3, r2 800baea: d901 bls.n 800baf0 { return HAL_TIMEOUT; 800baec: 2303 movs r3, #3 800baee: e136 b.n 800bd5e while (LL_RCC_LSE_IsReady() == 0U) 800baf0: f7ff fb45 bl 800b17e 800baf4: 4603 mov r3, r0 800baf6: 2b00 cmp r3, #0 800baf8: d0ef beq.n 800bada 800bafa: e013 b.n 800bb24 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bafc: f7fa ff28 bl 8006950 800bb00: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (LL_RCC_LSE_IsReady() != 0U) 800bb02: e00a b.n 800bb1a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bb04: f7fa ff24 bl 8006950 800bb08: 4602 mov r2, r0 800bb0a: 6a7b ldr r3, [r7, #36] @ 0x24 800bb0c: 1ad3 subs r3, r2, r3 800bb0e: f241 3288 movw r2, #5000 @ 0x1388 800bb12: 4293 cmp r3, r2 800bb14: d901 bls.n 800bb1a { return HAL_TIMEOUT; 800bb16: 2303 movs r3, #3 800bb18: e121 b.n 800bd5e while (LL_RCC_LSE_IsReady() != 0U) 800bb1a: f7ff fb30 bl 800b17e 800bb1e: 4603 mov r3, r0 800bb20: 2b00 cmp r3, #0 800bb22: d1ef bne.n 800bb04 } } #if defined(RCC_HSI48_SUPPORT) /*------------------------------ HSI48 Configuration -----------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800bb24: 687b ldr r3, [r7, #4] 800bb26: 681b ldr r3, [r3, #0] 800bb28: f003 0340 and.w r3, r3, #64 @ 0x40 800bb2c: 2b00 cmp r3, #0 800bb2e: d02c beq.n 800bb8a { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI State */ if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 800bb30: 687b ldr r3, [r7, #4] 800bb32: 6a9b ldr r3, [r3, #40] @ 0x28 800bb34: 2b00 cmp r3, #0 800bb36: d014 beq.n 800bb62 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800bb38: f7ff faa9 bl 800b08e /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bb3c: f7fa ff08 bl 8006950 800bb40: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (LL_RCC_HSI48_IsReady() == 0U) 800bb42: e008 b.n 800bb56 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800bb44: f7fa ff04 bl 8006950 800bb48: 4602 mov r2, r0 800bb4a: 6a7b ldr r3, [r7, #36] @ 0x24 800bb4c: 1ad3 subs r3, r2, r3 800bb4e: 2b02 cmp r3, #2 800bb50: d901 bls.n 800bb56 { return HAL_TIMEOUT; 800bb52: 2303 movs r3, #3 800bb54: e103 b.n 800bd5e while (LL_RCC_HSI48_IsReady() == 0U) 800bb56: f7ff fabc bl 800b0d2 800bb5a: 4603 mov r3, r0 800bb5c: 2b00 cmp r3, #0 800bb5e: d0f1 beq.n 800bb44 800bb60: e013 b.n 800bb8a } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800bb62: f7ff faa5 bl 800b0b0 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bb66: f7fa fef3 bl 8006950 800bb6a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is disabled */ while (LL_RCC_HSI48_IsReady() != 0U) 800bb6c: e008 b.n 800bb80 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800bb6e: f7fa feef bl 8006950 800bb72: 4602 mov r2, r0 800bb74: 6a7b ldr r3, [r7, #36] @ 0x24 800bb76: 1ad3 subs r3, r2, r3 800bb78: 2b02 cmp r3, #2 800bb7a: d901 bls.n 800bb80 { return HAL_TIMEOUT; 800bb7c: 2303 movs r3, #3 800bb7e: e0ee b.n 800bd5e while (LL_RCC_HSI48_IsReady() != 0U) 800bb80: f7ff faa7 bl 800b0d2 800bb84: 4603 mov r3, r0 800bb86: 2b00 cmp r3, #0 800bb88: d1f1 bne.n 800bb6e #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 800bb8a: 687b ldr r3, [r7, #4] 800bb8c: 6adb ldr r3, [r3, #44] @ 0x2c 800bb8e: 2b00 cmp r3, #0 800bb90: f000 80e4 beq.w 800bd5c { const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800bb94: f7ff fc05 bl 800b3a2 800bb98: 6138 str r0, [r7, #16] const uint32_t temp_pllconfig = RCC->PLLCFGR; 800bb9a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bb9e: 68db ldr r3, [r3, #12] 800bba0: 60fb str r3, [r7, #12] /* PLL On ? */ if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 800bba2: 687b ldr r3, [r7, #4] 800bba4: 6adb ldr r3, [r3, #44] @ 0x2c 800bba6: 2b02 cmp r3, #2 800bba8: f040 80b4 bne.w 800bd14 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Do nothing if PLL configuration is unchanged */ if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800bbac: 68fb ldr r3, [r7, #12] 800bbae: f003 0203 and.w r2, r3, #3 800bbb2: 687b ldr r3, [r7, #4] 800bbb4: 6b1b ldr r3, [r3, #48] @ 0x30 800bbb6: 429a cmp r2, r3 800bbb8: d123 bne.n 800bc02 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 800bbba: 68fb ldr r3, [r7, #12] 800bbbc: f003 0270 and.w r2, r3, #112 @ 0x70 800bbc0: 687b ldr r3, [r7, #4] 800bbc2: 6b5b ldr r3, [r3, #52] @ 0x34 if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800bbc4: 429a cmp r2, r3 800bbc6: d11c bne.n 800bc02 ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || 800bbc8: 68fb ldr r3, [r7, #12] 800bbca: 0a1b lsrs r3, r3, #8 800bbcc: f003 027f and.w r2, r3, #127 @ 0x7f 800bbd0: 687b ldr r3, [r7, #4] 800bbd2: 6b9b ldr r3, [r3, #56] @ 0x38 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 800bbd4: 429a cmp r2, r3 800bbd6: d114 bne.n 800bc02 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 800bbd8: 68fb ldr r3, [r7, #12] 800bbda: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 800bbde: 687b ldr r3, [r7, #4] 800bbe0: 6bdb ldr r3, [r3, #60] @ 0x3c ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) || 800bbe2: 429a cmp r2, r3 800bbe4: d10d bne.n 800bc02 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || 800bbe6: 68fb ldr r3, [r7, #12] 800bbe8: f003 6260 and.w r2, r3, #234881024 @ 0xe000000 800bbec: 687b ldr r3, [r7, #4] 800bbee: 6c1b ldr r3, [r3, #64] @ 0x40 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 800bbf0: 429a cmp r2, r3 800bbf2: d106 bne.n 800bc02 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) 800bbf4: 68fb ldr r3, [r7, #12] 800bbf6: f003 4260 and.w r2, r3, #3758096384 @ 0xe0000000 800bbfa: 687b ldr r3, [r7, #4] 800bbfc: 6c5b ldr r3, [r3, #68] @ 0x44 (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || 800bbfe: 429a cmp r2, r3 800bc00: d05d beq.n 800bcbe { /* Check if the PLL is used as system clock or not */ if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800bc02: 693b ldr r3, [r7, #16] 800bc04: 2b0c cmp r3, #12 800bc06: d058 beq.n 800bcba { #if defined(SAI1) /* Check if main PLL can be updated */ /* Not possible if the source is shared by other enabled PLLSAIx */ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) 800bc08: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bc0c: 681b ldr r3, [r3, #0] 800bc0e: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 800bc12: 2b00 cmp r3, #0 800bc14: d001 beq.n 800bc1a { return HAL_ERROR; 800bc16: 2301 movs r3, #1 800bc18: e0a1 b.n 800bd5e } else #endif /* SAI1 */ { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bc1a: f7ff fc85 bl 800b528 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bc1e: f7fa fe97 bl 8006950 800bc22: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800bc24: e008 b.n 800bc38 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bc26: f7fa fe93 bl 8006950 800bc2a: 4602 mov r2, r0 800bc2c: 6a7b ldr r3, [r7, #36] @ 0x24 800bc2e: 1ad3 subs r3, r2, r3 800bc30: 2b02 cmp r3, #2 800bc32: d901 bls.n 800bc38 { return HAL_TIMEOUT; 800bc34: 2303 movs r3, #3 800bc36: e092 b.n 800bd5e while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800bc38: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bc3c: 681b ldr r3, [r3, #0] 800bc3e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bc42: 2b00 cmp r3, #0 800bc44: d1ef bne.n 800bc26 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800bc46: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bc4a: 68da ldr r2, [r3, #12] 800bc4c: 4b30 ldr r3, [pc, #192] @ (800bd10 ) 800bc4e: 4013 ands r3, r2 800bc50: 687a ldr r2, [r7, #4] 800bc52: 6b11 ldr r1, [r2, #48] @ 0x30 800bc54: 687a ldr r2, [r7, #4] 800bc56: 6b52 ldr r2, [r2, #52] @ 0x34 800bc58: 4311 orrs r1, r2 800bc5a: 687a ldr r2, [r7, #4] 800bc5c: 6b92 ldr r2, [r2, #56] @ 0x38 800bc5e: 0212 lsls r2, r2, #8 800bc60: 4311 orrs r1, r2 800bc62: 687a ldr r2, [r7, #4] 800bc64: 6bd2 ldr r2, [r2, #60] @ 0x3c 800bc66: 4311 orrs r1, r2 800bc68: 687a ldr r2, [r7, #4] 800bc6a: 6c12 ldr r2, [r2, #64] @ 0x40 800bc6c: 4311 orrs r1, r2 800bc6e: 687a ldr r2, [r7, #4] 800bc70: 6c52 ldr r2, [r2, #68] @ 0x44 800bc72: 430a orrs r2, r1 800bc74: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bc78: 4313 orrs r3, r2 800bc7a: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800bc7c: f7ff fc45 bl 800b50a /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 800bc80: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bc84: 68db ldr r3, [r3, #12] 800bc86: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800bc8a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800bc8e: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bc90: f7fa fe5e bl 8006950 800bc94: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800bc96: e008 b.n 800bcaa { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bc98: f7fa fe5a bl 8006950 800bc9c: 4602 mov r2, r0 800bc9e: 6a7b ldr r3, [r7, #36] @ 0x24 800bca0: 1ad3 subs r3, r2, r3 800bca2: 2b02 cmp r3, #2 800bca4: d901 bls.n 800bcaa { return HAL_TIMEOUT; 800bca6: 2303 movs r3, #3 800bca8: e059 b.n 800bd5e while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800bcaa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bcae: 681b ldr r3, [r3, #0] 800bcb0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bcb4: 2b00 cmp r3, #0 800bcb6: d0ef beq.n 800bc98 if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800bcb8: e050 b.n 800bd5c } } else { /* PLL is already used as System core clock */ return HAL_ERROR; 800bcba: 2301 movs r3, #1 800bcbc: e04f b.n 800bd5e } else { /* PLL configuration is unchanged */ /* Re-enable PLL if it was disabled (ie. low power mode) */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800bcbe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bcc2: 681b ldr r3, [r3, #0] 800bcc4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bcc8: 2b00 cmp r3, #0 800bcca: d147 bne.n 800bd5c { /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800bccc: f7ff fc1d bl 800b50a /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 800bcd0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bcd4: 68db ldr r3, [r3, #12] 800bcd6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800bcda: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800bcde: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bce0: f7fa fe36 bl 8006950 800bce4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800bce6: e008 b.n 800bcfa { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bce8: f7fa fe32 bl 8006950 800bcec: 4602 mov r2, r0 800bcee: 6a7b ldr r3, [r7, #36] @ 0x24 800bcf0: 1ad3 subs r3, r2, r3 800bcf2: 2b02 cmp r3, #2 800bcf4: d901 bls.n 800bcfa { return HAL_TIMEOUT; 800bcf6: 2303 movs r3, #3 800bcf8: e031 b.n 800bd5e while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800bcfa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bcfe: 681b ldr r3, [r3, #0] 800bd00: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bd04: 2b00 cmp r3, #0 800bd06: d0ef beq.n 800bce8 800bd08: e028 b.n 800bd5c 800bd0a: bf00 nop 800bd0c: 58000400 .word 0x58000400 800bd10: 11c1808c .word 0x11c1808c } } else { /* Check that PLL is not used as system clock or not */ if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800bd14: 693b ldr r3, [r7, #16] 800bd16: 2b0c cmp r3, #12 800bd18: d01e beq.n 800bd58 { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bd1a: f7ff fc05 bl 800b528 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd1e: f7fa fe17 bl 8006950 800bd22: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800bd24: e008 b.n 800bd38 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bd26: f7fa fe13 bl 8006950 800bd2a: 4602 mov r2, r0 800bd2c: 6a7b ldr r3, [r7, #36] @ 0x24 800bd2e: 1ad3 subs r3, r2, r3 800bd30: 2b02 cmp r3, #2 800bd32: d901 bls.n 800bd38 { return HAL_TIMEOUT; 800bd34: 2303 movs r3, #3 800bd36: e012 b.n 800bd5e while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800bd38: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bd3c: 681b ldr r3, [r3, #0] 800bd3e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bd42: 2b00 cmp r3, #0 800bd44: d1ef bne.n 800bd26 } } /* Disable the PLL source and outputs to save power when PLL is off */ #if defined(SAI1) && defined(USB) CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); 800bd46: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800bd4a: 68da ldr r2, [r3, #12] 800bd4c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800bd50: 4b05 ldr r3, [pc, #20] @ (800bd68 ) 800bd52: 4013 ands r3, r2 800bd54: 60cb str r3, [r1, #12] 800bd56: e001 b.n 800bd5c #endif /* SAI1 && USB */ } else { /* PLL is already used as System core clock */ return HAL_ERROR; 800bd58: 2301 movs r3, #1 800bd5a: e000 b.n 800bd5e } } } return HAL_OK; 800bd5c: 2300 movs r3, #0 } 800bd5e: 4618 mov r0, r3 800bd60: 3734 adds r7, #52 @ 0x34 800bd62: 46bd mov sp, r7 800bd64: bd90 pop {r4, r7, pc} 800bd66: bf00 nop 800bd68: eefefffc .word 0xeefefffc 0800bd6c : * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800bd6c: b580 push {r7, lr} 800bd6e: b084 sub sp, #16 800bd70: af00 add r7, sp, #0 800bd72: 6078 str r0, [r7, #4] 800bd74: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800bd76: 687b ldr r3, [r7, #4] 800bd78: 2b00 cmp r3, #0 800bd7a: d101 bne.n 800bd80 { return HAL_ERROR; 800bd7c: 2301 movs r3, #1 800bd7e: e12d b.n 800bfdc /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK4) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800bd80: 4b98 ldr r3, [pc, #608] @ (800bfe4 ) 800bd82: 681b ldr r3, [r3, #0] 800bd84: f003 0307 and.w r3, r3, #7 800bd88: 683a ldr r2, [r7, #0] 800bd8a: 429a cmp r2, r3 800bd8c: d91b bls.n 800bdc6 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800bd8e: 4b95 ldr r3, [pc, #596] @ (800bfe4 ) 800bd90: 681b ldr r3, [r3, #0] 800bd92: f023 0207 bic.w r2, r3, #7 800bd96: 4993 ldr r1, [pc, #588] @ (800bfe4 ) 800bd98: 683b ldr r3, [r7, #0] 800bd9a: 4313 orrs r3, r2 800bd9c: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd9e: f7fa fdd7 bl 8006950 800bda2: 60f8 str r0, [r7, #12] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != FLatency) 800bda4: e008 b.n 800bdb8 { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 800bda6: f7fa fdd3 bl 8006950 800bdaa: 4602 mov r2, r0 800bdac: 68fb ldr r3, [r7, #12] 800bdae: 1ad3 subs r3, r2, r3 800bdb0: 2b02 cmp r3, #2 800bdb2: d901 bls.n 800bdb8 { return HAL_TIMEOUT; 800bdb4: 2303 movs r3, #3 800bdb6: e111 b.n 800bfdc while (__HAL_FLASH_GET_LATENCY() != FLatency) 800bdb8: 4b8a ldr r3, [pc, #552] @ (800bfe4 ) 800bdba: 681b ldr r3, [r3, #0] 800bdbc: f003 0307 and.w r3, r3, #7 800bdc0: 683a ldr r2, [r7, #0] 800bdc2: 429a cmp r2, r3 800bdc4: d1ef bne.n 800bda6 } } } /*-------------------------- HCLK1 Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800bdc6: 687b ldr r3, [r7, #4] 800bdc8: 681b ldr r3, [r3, #0] 800bdca: f003 0302 and.w r3, r3, #2 800bdce: 2b00 cmp r3, #0 800bdd0: d016 beq.n 800be00 { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); 800bdd2: 687b ldr r3, [r7, #4] 800bdd4: 689b ldr r3, [r3, #8] 800bdd6: 4618 mov r0, r3 800bdd8: f7ff faef bl 800b3ba /* HCLK1 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800bddc: f7fa fdb8 bl 8006950 800bde0: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_HPRE() == 0U) 800bde2: e008 b.n 800bdf6 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800bde4: f7fa fdb4 bl 8006950 800bde8: 4602 mov r2, r0 800bdea: 68fb ldr r3, [r7, #12] 800bdec: 1ad3 subs r3, r2, r3 800bdee: 2b02 cmp r3, #2 800bdf0: d901 bls.n 800bdf6 { return HAL_TIMEOUT; 800bdf2: 2303 movs r3, #3 800bdf4: e0f2 b.n 800bfdc while (LL_RCC_IsActiveFlag_HPRE() == 0U) 800bdf6: f7ff fbe9 bl 800b5cc 800bdfa: 4603 mov r3, r0 800bdfc: 2b00 cmp r3, #0 800bdfe: d0f1 beq.n 800bde4 } } } /*-------------------------- HCLK2 Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2) 800be00: 687b ldr r3, [r7, #4] 800be02: 681b ldr r3, [r3, #0] 800be04: f003 0320 and.w r3, r3, #32 800be08: 2b00 cmp r3, #0 800be0a: d016 beq.n 800be3a { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider)); LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider); 800be0c: 687b ldr r3, [r7, #4] 800be0e: 695b ldr r3, [r3, #20] 800be10: 4618 mov r0, r3 800be12: f7ff fae6 bl 800b3e2 /* HCLK2 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800be16: f7fa fd9b bl 8006950 800be1a: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) 800be1c: e008 b.n 800be30 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800be1e: f7fa fd97 bl 8006950 800be22: 4602 mov r2, r0 800be24: 68fb ldr r3, [r7, #12] 800be26: 1ad3 subs r3, r2, r3 800be28: 2b02 cmp r3, #2 800be2a: d901 bls.n 800be30 { return HAL_TIMEOUT; 800be2c: 2303 movs r3, #3 800be2e: e0d5 b.n 800bfdc while (LL_RCC_IsActiveFlag_C2HPRE() == 0U) 800be30: f7ff fbde bl 800b5f0 800be34: 4603 mov r3, r0 800be36: 2b00 cmp r3, #0 800be38: d0f1 beq.n 800be1e } } } /*-------------------------- HCLK4 Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK4) == RCC_CLOCKTYPE_HCLK4) 800be3a: 687b ldr r3, [r7, #4] 800be3c: 681b ldr r3, [r3, #0] 800be3e: f003 0340 and.w r3, r3, #64 @ 0x40 800be42: 2b00 cmp r3, #0 800be44: d016 beq.n 800be74 { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK4Divider)); LL_RCC_SetAHB4Prescaler(RCC_ClkInitStruct->AHBCLK4Divider); 800be46: 687b ldr r3, [r7, #4] 800be48: 699b ldr r3, [r3, #24] 800be4a: 4618 mov r0, r3 800be4c: f7ff fadf bl 800b40e /* AHB shared prescaler flag when value applied */ tickstart = HAL_GetTick(); 800be50: f7fa fd7e bl 8006950 800be54: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) 800be56: e008 b.n 800be6a { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800be58: f7fa fd7a bl 8006950 800be5c: 4602 mov r2, r0 800be5e: 68fb ldr r3, [r7, #12] 800be60: 1ad3 subs r3, r2, r3 800be62: 2b02 cmp r3, #2 800be64: d901 bls.n 800be6a { return HAL_TIMEOUT; 800be66: 2303 movs r3, #3 800be68: e0b8 b.n 800bfdc while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) 800be6a: f7ff fbd4 bl 800b616 800be6e: 4603 mov r3, r0 800be70: 2b00 cmp r3, #0 800be72: d0f1 beq.n 800be58 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800be74: 687b ldr r3, [r7, #4] 800be76: 681b ldr r3, [r3, #0] 800be78: f003 0304 and.w r3, r3, #4 800be7c: 2b00 cmp r3, #0 800be7e: d016 beq.n 800beae { assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); 800be80: 687b ldr r3, [r7, #4] 800be82: 68db ldr r3, [r3, #12] 800be84: 4618 mov r0, r3 800be86: f7ff fad9 bl 800b43c /* APB1 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800be8a: f7fa fd61 bl 8006950 800be8e: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_PPRE1() == 0U) 800be90: e008 b.n 800bea4 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800be92: f7fa fd5d bl 8006950 800be96: 4602 mov r2, r0 800be98: 68fb ldr r3, [r7, #12] 800be9a: 1ad3 subs r3, r2, r3 800be9c: 2b02 cmp r3, #2 800be9e: d901 bls.n 800bea4 { return HAL_TIMEOUT; 800bea0: 2303 movs r3, #3 800bea2: e09b b.n 800bfdc while (LL_RCC_IsActiveFlag_PPRE1() == 0U) 800bea4: f7ff fbca bl 800b63c 800bea8: 4603 mov r3, r0 800beaa: 2b00 cmp r3, #0 800beac: d0f1 beq.n 800be92 } } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800beae: 687b ldr r3, [r7, #4] 800beb0: 681b ldr r3, [r3, #0] 800beb2: f003 0308 and.w r3, r3, #8 800beb6: 2b00 cmp r3, #0 800beb8: d017 beq.n 800beea { assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); 800beba: 687b ldr r3, [r7, #4] 800bebc: 691b ldr r3, [r3, #16] 800bebe: 00db lsls r3, r3, #3 800bec0: 4618 mov r0, r3 800bec2: f7ff facf bl 800b464 /* APB2 prescaler flag when value applied */ tickstart = HAL_GetTick(); 800bec6: f7fa fd43 bl 8006950 800beca: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_PPRE2() == 0U) 800becc: e008 b.n 800bee0 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) 800bece: f7fa fd3f bl 8006950 800bed2: 4602 mov r2, r0 800bed4: 68fb ldr r3, [r7, #12] 800bed6: 1ad3 subs r3, r2, r3 800bed8: 2b02 cmp r3, #2 800beda: d901 bls.n 800bee0 { return HAL_TIMEOUT; 800bedc: 2303 movs r3, #3 800bede: e07d b.n 800bfdc while (LL_RCC_IsActiveFlag_PPRE2() == 0U) 800bee0: f7ff fbbe bl 800b660 800bee4: 4603 mov r3, r0 800bee6: 2b00 cmp r3, #0 800bee8: d0f1 beq.n 800bece } } } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800beea: 687b ldr r3, [r7, #4] 800beec: 681b ldr r3, [r3, #0] 800beee: f003 0301 and.w r3, r3, #1 800bef2: 2b00 cmp r3, #0 800bef4: d043 beq.n 800bf7e { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800bef6: 687b ldr r3, [r7, #4] 800bef8: 685b ldr r3, [r3, #4] 800befa: 2b02 cmp r3, #2 800befc: d106 bne.n 800bf0c { /* Check the HSE ready flag */ if (LL_RCC_HSE_IsReady() == 0U) 800befe: f7ff f86f bl 800afe0 800bf02: 4603 mov r3, r0 800bf04: 2b00 cmp r3, #0 800bf06: d11e bne.n 800bf46 { return HAL_ERROR; 800bf08: 2301 movs r3, #1 800bf0a: e067 b.n 800bfdc } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800bf0c: 687b ldr r3, [r7, #4] 800bf0e: 685b ldr r3, [r3, #4] 800bf10: 2b03 cmp r3, #3 800bf12: d106 bne.n 800bf22 { /* Check the PLL ready flag */ if (LL_RCC_PLL_IsReady() == 0U) 800bf14: f7ff fb17 bl 800b546 800bf18: 4603 mov r3, r0 800bf1a: 2b00 cmp r3, #0 800bf1c: d113 bne.n 800bf46 { return HAL_ERROR; 800bf1e: 2301 movs r3, #1 800bf20: e05c b.n 800bfdc } } /* MSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) 800bf22: 687b ldr r3, [r7, #4] 800bf24: 685b ldr r3, [r3, #4] 800bf26: 2b00 cmp r3, #0 800bf28: d106 bne.n 800bf38 { /* Check the MSI ready flag */ if (LL_RCC_MSI_IsReady() == 0U) 800bf2a: f7ff f9d7 bl 800b2dc 800bf2e: 4603 mov r3, r0 800bf30: 2b00 cmp r3, #0 800bf32: d108 bne.n 800bf46 { return HAL_ERROR; 800bf34: 2301 movs r3, #1 800bf36: e051 b.n 800bfdc } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (LL_RCC_HSI_IsReady() == 0U) 800bf38: f7ff f882 bl 800b040 800bf3c: 4603 mov r3, r0 800bf3e: 2b00 cmp r3, #0 800bf40: d101 bne.n 800bf46 { return HAL_ERROR; 800bf42: 2301 movs r3, #1 800bf44: e04a b.n 800bfdc } } /* apply system clock switch */ LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); 800bf46: 687b ldr r3, [r7, #4] 800bf48: 685b ldr r3, [r3, #4] 800bf4a: 4618 mov r0, r3 800bf4c: f7ff fa15 bl 800b37a /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf50: f7fa fcfe bl 8006950 800bf54: 60f8 str r0, [r7, #12] /* check system clock source switch status */ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800bf56: e00a b.n 800bf6e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800bf58: f7fa fcfa bl 8006950 800bf5c: 4602 mov r2, r0 800bf5e: 68fb ldr r3, [r7, #12] 800bf60: 1ad3 subs r3, r2, r3 800bf62: f241 3288 movw r2, #5000 @ 0x1388 800bf66: 4293 cmp r3, r2 800bf68: d901 bls.n 800bf6e { return HAL_TIMEOUT; 800bf6a: 2303 movs r3, #3 800bf6c: e036 b.n 800bfdc while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800bf6e: f7ff fa18 bl 800b3a2 800bf72: 4602 mov r2, r0 800bf74: 687b ldr r3, [r7, #4] 800bf76: 685b ldr r3, [r3, #4] 800bf78: 009b lsls r3, r3, #2 800bf7a: 429a cmp r2, r3 800bf7c: d1ec bne.n 800bf58 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800bf7e: 4b19 ldr r3, [pc, #100] @ (800bfe4 ) 800bf80: 681b ldr r3, [r3, #0] 800bf82: f003 0307 and.w r3, r3, #7 800bf86: 683a ldr r2, [r7, #0] 800bf88: 429a cmp r2, r3 800bf8a: d21b bcs.n 800bfc4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800bf8c: 4b15 ldr r3, [pc, #84] @ (800bfe4 ) 800bf8e: 681b ldr r3, [r3, #0] 800bf90: f023 0207 bic.w r2, r3, #7 800bf94: 4913 ldr r1, [pc, #76] @ (800bfe4 ) 800bf96: 683b ldr r3, [r7, #0] 800bf98: 4313 orrs r3, r2 800bf9a: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf9c: f7fa fcd8 bl 8006950 800bfa0: 60f8 str r0, [r7, #12] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != FLatency) 800bfa2: e008 b.n 800bfb6 { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 800bfa4: f7fa fcd4 bl 8006950 800bfa8: 4602 mov r2, r0 800bfaa: 68fb ldr r3, [r7, #12] 800bfac: 1ad3 subs r3, r2, r3 800bfae: 2b02 cmp r3, #2 800bfb0: d901 bls.n 800bfb6 { return HAL_TIMEOUT; 800bfb2: 2303 movs r3, #3 800bfb4: e012 b.n 800bfdc while (__HAL_FLASH_GET_LATENCY() != FLatency) 800bfb6: 4b0b ldr r3, [pc, #44] @ (800bfe4 ) 800bfb8: 681b ldr r3, [r3, #0] 800bfba: f003 0307 and.w r3, r3, #7 800bfbe: 683a ldr r2, [r7, #0] 800bfc0: 429a cmp r2, r3 800bfc2: d1ef bne.n 800bfa4 } /*---------------------------------------------------------------------------*/ /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); 800bfc4: f000 f87e bl 800c0c4 800bfc8: 4603 mov r3, r0 800bfca: 4a07 ldr r2, [pc, #28] @ (800bfe8 ) 800bfcc: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(HAL_GetTickPrio()); 800bfce: f7fa fccb bl 8006968 800bfd2: 4603 mov r3, r0 800bfd4: 4618 mov r0, r3 800bfd6: f7fa fa53 bl 8006480 800bfda: 4603 mov r3, r0 } 800bfdc: 4618 mov r0, r3 800bfde: 3710 adds r7, #16 800bfe0: 46bd mov sp, r7 800bfe2: bd80 pop {r7, pc} 800bfe4: 58004000 .word 0x58004000 800bfe8: 2000000c .word 0x2000000c 0800bfec : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800bfec: b590 push {r4, r7, lr} 800bfee: b085 sub sp, #20 800bff0: af00 add r7, sp, #0 uint32_t pllsource; uint32_t sysclockfreq; uint32_t pllinputfreq; const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800bff2: f7ff f9d6 bl 800b3a2 800bff6: 6078 str r0, [r7, #4] if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) 800bff8: 687b ldr r3, [r7, #4] 800bffa: 2b00 cmp r3, #0 800bffc: d10a bne.n 800c014 { /* Retrieve MSI frequency range in HZ*/ /* MSI used as system clock source */ sysclockfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); 800bffe: f7ff f992 bl 800b326 800c002: 4603 mov r3, r0 800c004: 091b lsrs r3, r3, #4 800c006: f003 030f and.w r3, r3, #15 800c00a: 4a2b ldr r2, [pc, #172] @ (800c0b8 ) 800c00c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800c010: 60fb str r3, [r7, #12] 800c012: e04b b.n 800c0ac } else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) 800c014: 687b ldr r3, [r7, #4] 800c016: 2b04 cmp r3, #4 800c018: d102 bne.n 800c020 { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; 800c01a: 4b28 ldr r3, [pc, #160] @ (800c0bc ) 800c01c: 60fb str r3, [r7, #12] 800c01e: e045 b.n 800c0ac } else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) 800c020: 687b ldr r3, [r7, #4] 800c022: 2b08 cmp r3, #8 800c024: d10a bne.n 800c03c { /* HSE used as system clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) 800c026: f7fe ffab bl 800af80 800c02a: 4603 mov r3, r0 800c02c: 2b01 cmp r3, #1 800c02e: d102 bne.n 800c036 { sysclockfreq = HSE_VALUE / 2U; 800c030: 4b22 ldr r3, [pc, #136] @ (800c0bc ) 800c032: 60fb str r3, [r7, #12] 800c034: e03a b.n 800c0ac } else { sysclockfreq = HSE_VALUE; 800c036: 4b22 ldr r3, [pc, #136] @ (800c0c0 ) 800c038: 60fb str r3, [r7, #12] 800c03a: e037 b.n 800c0ac } } else { /* PLL used as system clock source */ pllsource = LL_RCC_PLL_GetMainSource(); 800c03c: f7ff faba bl 800b5b4 800c040: 6038 str r0, [r7, #0] switch (pllsource) 800c042: 683b ldr r3, [r7, #0] 800c044: 2b02 cmp r3, #2 800c046: d003 beq.n 800c050 800c048: 683b ldr r3, [r7, #0] 800c04a: 2b03 cmp r3, #3 800c04c: d003 beq.n 800c056 800c04e: e00d b.n 800c06c { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; 800c050: 4b1a ldr r3, [pc, #104] @ (800c0bc ) 800c052: 60bb str r3, [r7, #8] break; 800c054: e015 b.n 800c082 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) 800c056: f7fe ff93 bl 800af80 800c05a: 4603 mov r3, r0 800c05c: 2b01 cmp r3, #1 800c05e: d102 bne.n 800c066 { pllinputfreq = HSE_VALUE / 2U; 800c060: 4b16 ldr r3, [pc, #88] @ (800c0bc ) 800c062: 60bb str r3, [r7, #8] } else { pllinputfreq = HSE_VALUE; } break; 800c064: e00d b.n 800c082 pllinputfreq = HSE_VALUE; 800c066: 4b16 ldr r3, [pc, #88] @ (800c0c0 ) 800c068: 60bb str r3, [r7, #8] break; 800c06a: e00a b.n 800c082 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); 800c06c: f7ff f95b bl 800b326 800c070: 4603 mov r3, r0 800c072: 091b lsrs r3, r3, #4 800c074: f003 030f and.w r3, r3, #15 800c078: 4a0f ldr r2, [pc, #60] @ (800c0b8 ) 800c07a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800c07e: 60bb str r3, [r7, #8] break; 800c080: bf00 nop } sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), 800c082: f7ff fa72 bl 800b56a 800c086: 4602 mov r2, r0 800c088: 68bb ldr r3, [r7, #8] 800c08a: fb03 f402 mul.w r4, r3, r2 800c08e: f7ff fa85 bl 800b59c 800c092: 4603 mov r3, r0 800c094: 091b lsrs r3, r3, #4 800c096: 3301 adds r3, #1 800c098: fbb4 f4f3 udiv r4, r4, r3 800c09c: f7ff fa72 bl 800b584 800c0a0: 4603 mov r3, r0 800c0a2: 0f5b lsrs r3, r3, #29 800c0a4: 3301 adds r3, #1 800c0a6: fbb4 f3f3 udiv r3, r4, r3 800c0aa: 60fb str r3, [r7, #12] LL_RCC_PLL_GetR()); } return sysclockfreq; 800c0ac: 68fb ldr r3, [r7, #12] } 800c0ae: 4618 mov r0, r3 800c0b0: 3714 adds r7, #20 800c0b2: 46bd mov sp, r7 800c0b4: bd90 pop {r4, r7, pc} 800c0b6: bf00 nop 800c0b8: 0801e5ac .word 0x0801e5ac 800c0bc: 00f42400 .word 0x00f42400 800c0c0: 01e84800 .word 0x01e84800 0800c0c4 : /** * @brief Return the HCLK frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800c0c4: b598 push {r3, r4, r7, lr} 800c0c6: af00 add r7, sp, #0 /* Get SysClock and Compute HCLK1 frequency ---------------------------*/ return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); 800c0c8: f7ff ff90 bl 800bfec 800c0cc: 4604 mov r4, r0 800c0ce: f7ff f9dd bl 800b48c 800c0d2: 4603 mov r3, r0 800c0d4: 091b lsrs r3, r3, #4 800c0d6: f003 030f and.w r3, r3, #15 800c0da: 4a03 ldr r2, [pc, #12] @ (800c0e8 ) 800c0dc: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800c0e0: fbb4 f3f3 udiv r3, r4, r3 } 800c0e4: 4618 mov r0, r3 800c0e6: bd98 pop {r3, r4, r7, pc} 800c0e8: 0801e54c .word 0x0801e54c 0800c0ec : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800c0ec: b598 push {r3, r4, r7, lr} 800c0ee: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler()))); 800c0f0: f7ff ffe8 bl 800c0c4 800c0f4: 4604 mov r4, r0 800c0f6: f7ff f9fc bl 800b4f2 800c0fa: 4603 mov r3, r0 800c0fc: 0adb lsrs r3, r3, #11 800c0fe: f003 0307 and.w r3, r3, #7 800c102: 4a04 ldr r2, [pc, #16] @ (800c114 ) 800c104: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800c108: f003 031f and.w r3, r3, #31 800c10c: fa24 f303 lsr.w r3, r4, r3 } 800c110: 4618 mov r0, r3 800c112: bd98 pop {r3, r4, r7, pc} 800c114: 0801e58c .word 0x0801e58c 0800c118 : * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800c118: b580 push {r7, lr} 800c11a: b082 sub sp, #8 800c11c: af00 add r7, sp, #0 800c11e: 6078 str r0, [r7, #4] 800c120: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(RCC_ClkInitStruct != (void *)NULL); assert_param(pFLatency != (void *)NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | 800c122: 687b ldr r3, [r7, #4] 800c124: 226f movs r2, #111 @ 0x6f 800c126: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4); /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = LL_RCC_GetSysClkSource(); 800c128: f7ff f93b bl 800b3a2 800c12c: 4602 mov r2, r0 800c12e: 687b ldr r3, [r7, #4] 800c130: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = LL_RCC_GetAHBPrescaler(); 800c132: f7ff f9ab bl 800b48c 800c136: 4602 mov r2, r0 800c138: 687b ldr r3, [r7, #4] 800c13a: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = LL_RCC_GetAPB1Prescaler(); 800c13c: f7ff f9cd bl 800b4da 800c140: 4602 mov r2, r0 800c142: 687b ldr r3, [r7, #4] 800c144: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = LL_RCC_GetAPB2Prescaler(); 800c146: f7ff f9d4 bl 800b4f2 800c14a: 4602 mov r2, r0 800c14c: 687b ldr r3, [r7, #4] 800c14e: 611a str r2, [r3, #16] /* Get the AHBCLK2Divider configuration ------------------------------------*/ RCC_ClkInitStruct->AHBCLK2Divider = LL_C2_RCC_GetAHBPrescaler(); 800c150: f7ff f9a8 bl 800b4a4 800c154: 4602 mov r2, r0 800c156: 687b ldr r3, [r7, #4] 800c158: 615a str r2, [r3, #20] /* Get the AHBCLK4Divider configuration ------------------------------------*/ RCC_ClkInitStruct->AHBCLK4Divider = LL_RCC_GetAHB4Prescaler(); 800c15a: f7ff f9b0 bl 800b4be 800c15e: 4602 mov r2, r0 800c160: 687b ldr r3, [r7, #4] 800c162: 619a str r2, [r3, #24] /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = __HAL_FLASH_GET_LATENCY(); 800c164: 4b04 ldr r3, [pc, #16] @ (800c178 ) 800c166: 681b ldr r3, [r3, #0] 800c168: f003 0207 and.w r2, r3, #7 800c16c: 683b ldr r3, [r7, #0] 800c16e: 601a str r2, [r3, #0] } 800c170: bf00 nop 800c172: 3708 adds r7, #8 800c174: 46bd mov sp, r7 800c176: bd80 pop {r7, pc} 800c178: 58004000 .word 0x58004000 0800c17c : voltage range. * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) { 800c17c: b590 push {r4, r7, lr} 800c17e: b085 sub sp, #20 800c180: af00 add r7, sp, #0 800c182: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range)); /* MSI frequency range in Hz */ if (MSI_Range > RCC_MSIRANGE_11) 800c184: 687b ldr r3, [r7, #4] 800c186: 2bb0 cmp r3, #176 @ 0xb0 800c188: d903 bls.n 800c192 { msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11); 800c18a: 4b15 ldr r3, [pc, #84] @ (800c1e0 ) 800c18c: 6adb ldr r3, [r3, #44] @ 0x2c 800c18e: 60fb str r3, [r7, #12] 800c190: e007 b.n 800c1a2 } else { msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range); 800c192: 687b ldr r3, [r7, #4] 800c194: 091b lsrs r3, r3, #4 800c196: f003 030f and.w r3, r3, #15 800c19a: 4a11 ldr r2, [pc, #68] @ (800c1e0 ) 800c19c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800c1a0: 60fb str r3, [r7, #12] } flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler()); 800c1a2: f7ff f98c bl 800b4be 800c1a6: 4603 mov r3, r0 800c1a8: 091b lsrs r3, r3, #4 800c1aa: f003 030f and.w r3, r3, #15 800c1ae: 4a0d ldr r2, [pc, #52] @ (800c1e4 ) 800c1b0: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800c1b4: 68fa ldr r2, [r7, #12] 800c1b6: fbb2 f3f3 udiv r3, r2, r3 800c1ba: 60bb str r3, [r7, #8] #if defined(PWR_CR1_VOS) return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); 800c1bc: 68bb ldr r3, [r7, #8] 800c1be: 4a0a ldr r2, [pc, #40] @ (800c1e8 ) 800c1c0: fba2 2303 umull r2, r3, r2, r3 800c1c4: 0c9c lsrs r4, r3, #18 800c1c6: f7fe febd bl 800af44 800c1ca: 4603 mov r3, r0 800c1cc: 4619 mov r1, r3 800c1ce: 4620 mov r0, r4 800c1d0: f000 f80c bl 800c1ec 800c1d4: 4603 mov r3, r0 #else return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1); #endif /* PWR_CR1_VOS */ } 800c1d6: 4618 mov r0, r3 800c1d8: 3714 adds r7, #20 800c1da: 46bd mov sp, r7 800c1dc: bd90 pop {r4, r7, pc} 800c1de: bf00 nop 800c1e0: 0801e5ac .word 0x0801e5ac 800c1e4: 0801e54c .word 0x0801e54c 800c1e8: 431bde83 .word 0x431bde83 0800c1ec : * @param Flash_ClkSrcFreq Flash Clock Source (in MHz) * @param VCORE_Voltage Current Vcore voltage (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2) * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) { 800c1ec: b590 push {r4, r7, lr} 800c1ee: b093 sub sp, #76 @ 0x4c 800c1f0: af00 add r7, sp, #0 800c1f2: 6078 str r0, [r7, #4] 800c1f4: 6039 str r1, [r7, #0] /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL}; 800c1f6: 4b37 ldr r3, [pc, #220] @ (800c2d4 ) 800c1f8: f107 0428 add.w r4, r7, #40 @ 0x28 800c1fc: cb0f ldmia r3, {r0, r1, r2, r3} 800c1fe: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(PWR_CR1_VOS) /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL}; 800c202: 4a35 ldr r2, [pc, #212] @ (800c2d8 ) 800c204: f107 031c add.w r3, r7, #28 800c208: ca07 ldmia r2, {r0, r1, r2} 800c20a: e883 0007 stmia.w r3, {r0, r1, r2} #endif /* PWR_CR1_VOS */ /* Flash Latency range */ const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3}; 800c20e: 4b33 ldr r3, [pc, #204] @ (800c2dc ) 800c210: f107 040c add.w r4, r7, #12 800c214: cb0f ldmia r3, {r0, r1, r2, r3} 800c216: e884 000f stmia.w r4, {r0, r1, r2, r3} uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ 800c21a: 2300 movs r3, #0 800c21c: 647b str r3, [r7, #68] @ 0x44 uint32_t tickstart; #if defined(PWR_CR1_VOS) if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) 800c21e: 683b ldr r3, [r7, #0] 800c220: f5b3 7f00 cmp.w r3, #512 @ 0x200 800c224: d11a bne.n 800c25c { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) 800c226: 2300 movs r3, #0 800c228: 643b str r3, [r7, #64] @ 0x40 800c22a: e013 b.n 800c254 { if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) 800c22c: 6c3b ldr r3, [r7, #64] @ 0x40 800c22e: 009b lsls r3, r3, #2 800c230: 3348 adds r3, #72 @ 0x48 800c232: 443b add r3, r7 800c234: f853 3c20 ldr.w r3, [r3, #-32] 800c238: 687a ldr r2, [r7, #4] 800c23a: 429a cmp r2, r3 800c23c: d807 bhi.n 800c24e { latency = FLASH_LATENCY_RANGE[index]; 800c23e: 6c3b ldr r3, [r7, #64] @ 0x40 800c240: 009b lsls r3, r3, #2 800c242: 3348 adds r3, #72 @ 0x48 800c244: 443b add r3, r7 800c246: f853 3c3c ldr.w r3, [r3, #-60] 800c24a: 647b str r3, [r7, #68] @ 0x44 break; 800c24c: e020 b.n 800c290 for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) 800c24e: 6c3b ldr r3, [r7, #64] @ 0x40 800c250: 3301 adds r3, #1 800c252: 643b str r3, [r7, #64] @ 0x40 800c254: 6c3b ldr r3, [r7, #64] @ 0x40 800c256: 2b03 cmp r3, #3 800c258: d9e8 bls.n 800c22c 800c25a: e019 b.n 800c290 } } } else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) 800c25c: 2300 movs r3, #0 800c25e: 63fb str r3, [r7, #60] @ 0x3c 800c260: e013 b.n 800c28a { if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) 800c262: 6bfb ldr r3, [r7, #60] @ 0x3c 800c264: 009b lsls r3, r3, #2 800c266: 3348 adds r3, #72 @ 0x48 800c268: 443b add r3, r7 800c26a: f853 3c2c ldr.w r3, [r3, #-44] 800c26e: 687a ldr r2, [r7, #4] 800c270: 429a cmp r2, r3 800c272: d807 bhi.n 800c284 { latency = FLASH_LATENCY_RANGE[index]; 800c274: 6bfb ldr r3, [r7, #60] @ 0x3c 800c276: 009b lsls r3, r3, #2 800c278: 3348 adds r3, #72 @ 0x48 800c27a: 443b add r3, r7 800c27c: f853 3c3c ldr.w r3, [r3, #-60] 800c280: 647b str r3, [r7, #68] @ 0x44 break; 800c282: e005 b.n 800c290 for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) 800c284: 6bfb ldr r3, [r7, #60] @ 0x3c 800c286: 3301 adds r3, #1 800c288: 63fb str r3, [r7, #60] @ 0x3c 800c28a: 6bfb ldr r3, [r7, #60] @ 0x3c 800c28c: 2b02 cmp r3, #2 800c28e: d9e8 bls.n 800c262 break; } } #endif /* PWR_CR1_VOS */ __HAL_FLASH_SET_LATENCY(latency); 800c290: 4b13 ldr r3, [pc, #76] @ (800c2e0 ) 800c292: 681b ldr r3, [r3, #0] 800c294: f023 0207 bic.w r2, r3, #7 800c298: 4911 ldr r1, [pc, #68] @ (800c2e0 ) 800c29a: 6c7b ldr r3, [r7, #68] @ 0x44 800c29c: 4313 orrs r3, r2 800c29e: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c2a0: f7fa fb56 bl 8006950 800c2a4: 63b8 str r0, [r7, #56] @ 0x38 /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != latency) 800c2a6: e008 b.n 800c2ba { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) 800c2a8: f7fa fb52 bl 8006950 800c2ac: 4602 mov r2, r0 800c2ae: 6bbb ldr r3, [r7, #56] @ 0x38 800c2b0: 1ad3 subs r3, r2, r3 800c2b2: 2b02 cmp r3, #2 800c2b4: d901 bls.n 800c2ba { return HAL_TIMEOUT; 800c2b6: 2303 movs r3, #3 800c2b8: e007 b.n 800c2ca while (__HAL_FLASH_GET_LATENCY() != latency) 800c2ba: 4b09 ldr r3, [pc, #36] @ (800c2e0 ) 800c2bc: 681b ldr r3, [r3, #0] 800c2be: f003 0307 and.w r3, r3, #7 800c2c2: 6c7a ldr r2, [r7, #68] @ 0x44 800c2c4: 429a cmp r2, r3 800c2c6: d1ef bne.n 800c2a8 } } return HAL_OK; 800c2c8: 2300 movs r3, #0 } 800c2ca: 4618 mov r0, r3 800c2cc: 374c adds r7, #76 @ 0x4c 800c2ce: 46bd mov sp, r7 800c2d0: bd90 pop {r4, r7, pc} 800c2d2: bf00 nop 800c2d4: 0801e2d0 .word 0x0801e2d0 800c2d8: 0801e2e0 .word 0x0801e2e0 800c2dc: 0801e2ec .word 0x0801e2ec 800c2e0: 58004000 .word 0x58004000 0800c2e4 : { 800c2e4: b480 push {r7} 800c2e6: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL); 800c2e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c2ec: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c2f0: f003 0301 and.w r3, r3, #1 800c2f4: 2b01 cmp r3, #1 800c2f6: d101 bne.n 800c2fc 800c2f8: 2301 movs r3, #1 800c2fa: e000 b.n 800c2fe 800c2fc: 2300 movs r3, #0 } 800c2fe: 4618 mov r0, r3 800c300: 46bd mov sp, r7 800c302: f85d 7b04 ldr.w r7, [sp], #4 800c306: 4770 bx lr 0800c308 : { 800c308: b480 push {r7} 800c30a: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); 800c30c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c310: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c314: f003 0302 and.w r3, r3, #2 800c318: 2b02 cmp r3, #2 800c31a: d101 bne.n 800c320 800c31c: 2301 movs r3, #1 800c31e: e000 b.n 800c322 800c320: 2300 movs r3, #0 } 800c322: 4618 mov r0, r3 800c324: 46bd mov sp, r7 800c326: f85d 7b04 ldr.w r7, [sp], #4 800c32a: 4770 bx lr 0800c32c : { 800c32c: b480 push {r7} 800c32e: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); 800c330: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c334: 681b ldr r3, [r3, #0] 800c336: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c33a: f043 0304 orr.w r3, r3, #4 800c33e: 6013 str r3, [r2, #0] } 800c340: bf00 nop 800c342: 46bd mov sp, r7 800c344: f85d 7b04 ldr.w r7, [sp], #4 800c348: 4770 bx lr 0800c34a : { 800c34a: b480 push {r7} 800c34c: b083 sub sp, #12 800c34e: af00 add r7, sp, #0 800c350: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source); 800c352: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c356: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800c35a: f423 4240 bic.w r2, r3, #49152 @ 0xc000 800c35e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c362: 687b ldr r3, [r7, #4] 800c364: 4313 orrs r3, r2 800c366: f8c1 3094 str.w r3, [r1, #148] @ 0x94 } 800c36a: bf00 nop 800c36c: 370c adds r7, #12 800c36e: 46bd mov sp, r7 800c370: f85d 7b04 ldr.w r7, [sp], #4 800c374: 4770 bx lr 0800c376 : { 800c376: b480 push {r7} 800c378: b083 sub sp, #12 800c37a: af00 add r7, sp, #0 800c37c: 6078 str r0, [r7, #4] MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource); 800c37e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c382: 6a5b ldr r3, [r3, #36] @ 0x24 800c384: f023 0203 bic.w r2, r3, #3 800c388: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c38c: 687b ldr r3, [r7, #4] 800c38e: 4313 orrs r3, r2 800c390: 624b str r3, [r1, #36] @ 0x24 } 800c392: bf00 nop 800c394: 370c adds r7, #12 800c396: 46bd mov sp, r7 800c398: f85d 7b04 ldr.w r7, [sp], #4 800c39c: 4770 bx lr 0800c39e : { 800c39e: b480 push {r7} 800c3a0: b083 sub sp, #12 800c3a2: af00 add r7, sp, #0 800c3a4: 6078 str r0, [r7, #4] MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler); 800c3a6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c3aa: 6a5b ldr r3, [r3, #36] @ 0x24 800c3ac: f023 0230 bic.w r2, r3, #48 @ 0x30 800c3b0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c3b4: 687b ldr r3, [r7, #4] 800c3b6: 4313 orrs r3, r2 800c3b8: 624b str r3, [r1, #36] @ 0x24 } 800c3ba: bf00 nop 800c3bc: 370c adds r7, #12 800c3be: 46bd mov sp, r7 800c3c0: f85d 7b04 ldr.w r7, [sp], #4 800c3c4: 4770 bx lr 0800c3c6 : { 800c3c6: b480 push {r7} 800c3c8: b083 sub sp, #12 800c3ca: af00 add r7, sp, #0 800c3cc: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource); 800c3ce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c3d2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800c3d6: f023 0203 bic.w r2, r3, #3 800c3da: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c3de: 687b ldr r3, [r7, #4] 800c3e0: 4313 orrs r3, r2 800c3e2: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800c3e6: bf00 nop 800c3e8: 370c adds r7, #12 800c3ea: 46bd mov sp, r7 800c3ec: f85d 7b04 ldr.w r7, [sp], #4 800c3f0: 4770 bx lr 0800c3f2 : { 800c3f2: b480 push {r7} 800c3f4: b083 sub sp, #12 800c3f6: af00 add r7, sp, #0 800c3f8: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); 800c3fa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c3fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800c402: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800c406: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c40a: 687b ldr r3, [r7, #4] 800c40c: 4313 orrs r3, r2 800c40e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800c412: bf00 nop 800c414: 370c adds r7, #12 800c416: 46bd mov sp, r7 800c418: f85d 7b04 ldr.w r7, [sp], #4 800c41c: 4770 bx lr 0800c41e : { 800c41e: b480 push {r7} 800c420: b083 sub sp, #12 800c422: af00 add r7, sp, #0 800c424: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); 800c426: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c42a: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800c42e: 687b ldr r3, [r7, #4] 800c430: 091b lsrs r3, r3, #4 800c432: f403 237f and.w r3, r3, #1044480 @ 0xff000 800c436: 43db mvns r3, r3 800c438: 401a ands r2, r3 800c43a: 687b ldr r3, [r7, #4] 800c43c: 011b lsls r3, r3, #4 800c43e: f403 237f and.w r3, r3, #1044480 @ 0xff000 800c442: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c446: 4313 orrs r3, r2 800c448: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800c44c: bf00 nop 800c44e: 370c adds r7, #12 800c450: 46bd mov sp, r7 800c452: f85d 7b04 ldr.w r7, [sp], #4 800c456: 4770 bx lr 0800c458 : { 800c458: b480 push {r7} 800c45a: b083 sub sp, #12 800c45c: af00 add r7, sp, #0 800c45e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); 800c460: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c464: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800c468: 687b ldr r3, [r7, #4] 800c46a: 0c1b lsrs r3, r3, #16 800c46c: 041b lsls r3, r3, #16 800c46e: 43db mvns r3, r3 800c470: 401a ands r2, r3 800c472: 687b ldr r3, [r7, #4] 800c474: 041b lsls r3, r3, #16 800c476: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c47a: 4313 orrs r3, r2 800c47c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800c480: bf00 nop 800c482: 370c adds r7, #12 800c484: 46bd mov sp, r7 800c486: f85d 7b04 ldr.w r7, [sp], #4 800c48a: 4770 bx lr 0800c48c : { 800c48c: b480 push {r7} 800c48e: b083 sub sp, #12 800c490: af00 add r7, sp, #0 800c492: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource); 800c494: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c498: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800c49c: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 800c4a0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c4a4: 687b ldr r3, [r7, #4] 800c4a6: 4313 orrs r3, r2 800c4a8: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800c4ac: bf00 nop 800c4ae: 370c adds r7, #12 800c4b0: 46bd mov sp, r7 800c4b2: f85d 7b04 ldr.w r7, [sp], #4 800c4b6: 4770 bx lr 0800c4b8 : { 800c4b8: b480 push {r7} 800c4ba: b083 sub sp, #12 800c4bc: af00 add r7, sp, #0 800c4be: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); 800c4c0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c4c4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800c4c8: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000 800c4cc: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c4d0: 687b ldr r3, [r7, #4] 800c4d2: 4313 orrs r3, r2 800c4d4: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800c4d8: bf00 nop 800c4da: 370c adds r7, #12 800c4dc: 46bd mov sp, r7 800c4de: f85d 7b04 ldr.w r7, [sp], #4 800c4e2: 4770 bx lr 0800c4e4 : { 800c4e4: b480 push {r7} 800c4e6: b083 sub sp, #12 800c4e8: af00 add r7, sp, #0 800c4ea: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource); 800c4ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c4f0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800c4f4: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 800c4f8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c4fc: 687b ldr r3, [r7, #4] 800c4fe: 4313 orrs r3, r2 800c500: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800c504: bf00 nop 800c506: 370c adds r7, #12 800c508: 46bd mov sp, r7 800c50a: f85d 7b04 ldr.w r7, [sp], #4 800c50e: 4770 bx lr 0800c510 : { 800c510: b580 push {r7, lr} 800c512: b082 sub sp, #8 800c514: af00 add r7, sp, #0 800c516: 6078 str r0, [r7, #4] LL_RCC_SetCLK48ClockSource(USBxSource); 800c518: 6878 ldr r0, [r7, #4] 800c51a: f7ff ffe3 bl 800c4e4 } 800c51e: bf00 nop 800c520: 3708 adds r7, #8 800c522: 46bd mov sp, r7 800c524: bd80 pop {r7, pc} 0800c526 : { 800c526: b480 push {r7} 800c528: b083 sub sp, #12 800c52a: af00 add r7, sp, #0 800c52c: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); 800c52e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c532: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800c536: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 800c53a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c53e: 687b ldr r3, [r7, #4] 800c540: 4313 orrs r3, r2 800c542: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } 800c546: bf00 nop 800c548: 370c adds r7, #12 800c54a: 46bd mov sp, r7 800c54c: f85d 7b04 ldr.w r7, [sp], #4 800c550: 4770 bx lr 0800c552 : { 800c552: b480 push {r7} 800c554: b083 sub sp, #12 800c556: af00 add r7, sp, #0 800c558: 6078 str r0, [r7, #4] MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 800c55a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c55e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c562: f423 7240 bic.w r2, r3, #768 @ 0x300 800c566: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c56a: 687b ldr r3, [r7, #4] 800c56c: 4313 orrs r3, r2 800c56e: f8c1 3090 str.w r3, [r1, #144] @ 0x90 } 800c572: bf00 nop 800c574: 370c adds r7, #12 800c576: 46bd mov sp, r7 800c578: f85d 7b04 ldr.w r7, [sp], #4 800c57c: 4770 bx lr 0800c57e : { 800c57e: b480 push {r7} 800c580: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 800c582: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c586: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c58a: f403 7340 and.w r3, r3, #768 @ 0x300 } 800c58e: 4618 mov r0, r3 800c590: 46bd mov sp, r7 800c592: f85d 7b04 ldr.w r7, [sp], #4 800c596: 4770 bx lr 0800c598 : { 800c598: b480 push {r7} 800c59a: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 800c59c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c5a0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c5a4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c5a8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c5ac: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800c5b0: bf00 nop 800c5b2: 46bd mov sp, r7 800c5b4: f85d 7b04 ldr.w r7, [sp], #4 800c5b8: 4770 bx lr 0800c5ba : { 800c5ba: b480 push {r7} 800c5bc: af00 add r7, sp, #0 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 800c5be: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c5c2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c5c6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c5ca: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800c5ce: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } 800c5d2: bf00 nop 800c5d4: 46bd mov sp, r7 800c5d6: f85d 7b04 ldr.w r7, [sp], #4 800c5da: 4770 bx lr 0800c5dc : { 800c5dc: b480 push {r7} 800c5de: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 800c5e0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c5e4: 681b ldr r3, [r3, #0] 800c5e6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c5ea: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800c5ee: 6013 str r3, [r2, #0] } 800c5f0: bf00 nop 800c5f2: 46bd mov sp, r7 800c5f4: f85d 7b04 ldr.w r7, [sp], #4 800c5f8: 4770 bx lr 0800c5fa : { 800c5fa: b480 push {r7} 800c5fc: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 800c5fe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c602: 681b ldr r3, [r3, #0] 800c604: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c608: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800c60c: 6013 str r3, [r2, #0] } 800c60e: bf00 nop 800c610: 46bd mov sp, r7 800c612: f85d 7b04 ldr.w r7, [sp], #4 800c616: 4770 bx lr 0800c618 : { 800c618: b480 push {r7} 800c61a: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL); 800c61c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c620: 681b ldr r3, [r3, #0] 800c622: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800c626: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800c62a: d101 bne.n 800c630 800c62c: 2301 movs r3, #1 800c62e: e000 b.n 800c632 800c630: 2300 movs r3, #0 } 800c632: 4618 mov r0, r3 800c634: 46bd mov sp, r7 800c636: f85d 7b04 ldr.w r7, [sp], #4 800c63a: 4770 bx lr 0800c63c : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800c63c: b580 push {r7, lr} 800c63e: b088 sub sp, #32 800c640: af00 add r7, sp, #0 800c642: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800c644: 2300 movs r3, #0 800c646: 77fb strb r3, [r7, #31] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800c648: 2300 movs r3, #0 800c64a: 77bb strb r3, [r7, #30] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); #if defined(SAI1) /*-------------------------- SAI1 clock source configuration ---------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) 800c64c: 687b ldr r3, [r7, #4] 800c64e: 681b ldr r3, [r3, #0] 800c650: f003 0340 and.w r3, r3, #64 @ 0x40 800c654: 2b00 cmp r3, #0 800c656: d034 beq.n 800c6c2 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); switch (PeriphClkInit->Sai1ClockSelection) 800c658: 687b ldr r3, [r7, #4] 800c65a: 6b1b ldr r3, [r3, #48] @ 0x30 800c65c: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 800c660: d021 beq.n 800c6a6 800c662: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000 800c666: d81b bhi.n 800c6a0 800c668: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c66c: d01d beq.n 800c6aa 800c66e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c672: d815 bhi.n 800c6a0 800c674: 2b00 cmp r3, #0 800c676: d00b beq.n 800c690 800c678: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c67c: d110 bne.n 800c6a0 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1 */ /* Enable SAI1 Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI1CLK); 800c67e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c682: 68db ldr r3, [r3, #12] 800c684: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c688: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c68c: 60d3 str r3, [r2, #12] /* SAI1 clock source config set later after clock selection check */ break; 800c68e: e00d b.n 800c6ac case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */ /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1)); 800c690: 687b ldr r3, [r7, #4] 800c692: 3304 adds r3, #4 800c694: 4618 mov r0, r3 800c696: f000 f94d bl 800c934 800c69a: 4603 mov r3, r0 800c69c: 77fb strb r3, [r7, #31] /* SAI1 clock source config set later after clock selection check */ break; 800c69e: e005 b.n 800c6ac case RCC_SAI1CLKSOURCE_HSI: break; default: ret = HAL_ERROR; 800c6a0: 2301 movs r3, #1 800c6a2: 77fb strb r3, [r7, #31] break; 800c6a4: e002 b.n 800c6ac break; 800c6a6: bf00 nop 800c6a8: e000 b.n 800c6ac break; 800c6aa: bf00 nop } if (ret == HAL_OK) 800c6ac: 7ffb ldrb r3, [r7, #31] 800c6ae: 2b00 cmp r3, #0 800c6b0: d105 bne.n 800c6be { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800c6b2: 687b ldr r3, [r7, #4] 800c6b4: 6b1b ldr r3, [r3, #48] @ 0x30 800c6b6: 4618 mov r0, r3 800c6b8: f7ff fee8 bl 800c48c 800c6bc: e001 b.n 800c6c2 } else { /* set overall return value */ status = ret; 800c6be: 7ffb ldrb r3, [r7, #31] 800c6c0: 77bb strb r3, [r7, #30] } } #endif /* SAI1 */ /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800c6c2: 687b ldr r3, [r7, #4] 800c6c4: 681b ldr r3, [r3, #0] 800c6c6: f403 6300 and.w r3, r3, #2048 @ 0x800 800c6ca: 2b00 cmp r3, #0 800c6cc: d046 beq.n 800c75c { uint32_t rtcclocksource = LL_RCC_GetRTCClockSource(); 800c6ce: f7ff ff56 bl 800c57e 800c6d2: 61b8 str r0, [r7, #24] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Configure the clock source only if a different source is expected */ if (rtcclocksource != PeriphClkInit->RTCClockSelection) 800c6d4: 687b ldr r3, [r7, #4] 800c6d6: 6c1b ldr r3, [r3, #64] @ 0x40 800c6d8: 69ba ldr r2, [r7, #24] 800c6da: 429a cmp r2, r3 800c6dc: d03c beq.n 800c758 { /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); 800c6de: f7fe fc21 bl 800af24 /* If a clock source is not yet selected */ if (rtcclocksource == RCC_RTCCLKSOURCE_NONE) 800c6e2: 69bb ldr r3, [r7, #24] 800c6e4: 2b00 cmp r3, #0 800c6e6: d105 bne.n 800c6f4 { /* Directly set the configuration of the clock source selection */ LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection); 800c6e8: 687b ldr r3, [r7, #4] 800c6ea: 6c1b ldr r3, [r3, #64] @ 0x40 800c6ec: 4618 mov r0, r3 800c6ee: f7ff ff30 bl 800c552 800c6f2: e02e b.n 800c752 } else /* A clock source is already selected */ { /* Store the content of BDCR register before the reset of Backup Domain */ uint32_t bdcr = LL_RCC_ReadReg(BDCR); 800c6f4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c6f8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800c6fc: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ LL_RCC_ForceBackupDomainReset(); 800c6fe: f7ff ff4b bl 800c598 LL_RCC_ReleaseBackupDomainReset(); 800c702: f7ff ff5a bl 800c5ba /* Set the value of the clock source selection */ MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection); 800c706: 697b ldr r3, [r7, #20] 800c708: f423 7240 bic.w r2, r3, #768 @ 0x300 800c70c: 687b ldr r3, [r7, #4] 800c70e: 6c1b ldr r3, [r3, #64] @ 0x40 800c710: 4313 orrs r3, r2 800c712: 617b str r3, [r7, #20] /* Restore the content of BDCR register */ LL_RCC_WriteReg(BDCR, bdcr); 800c714: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c718: 697b ldr r3, [r7, #20] 800c71a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (LL_RCC_LSE_IsEnabled() == 1U) 800c71e: f7ff fde1 bl 800c2e4 800c722: 4603 mov r3, r0 800c724: 2b01 cmp r3, #1 800c726: d114 bne.n 800c752 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c728: f7fa f912 bl 8006950 800c72c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() != 1U) 800c72e: e00b b.n 800c748 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800c730: f7fa f90e bl 8006950 800c734: 4602 mov r2, r0 800c736: 693b ldr r3, [r7, #16] 800c738: 1ad3 subs r3, r2, r3 800c73a: f241 3288 movw r2, #5000 @ 0x1388 800c73e: 4293 cmp r3, r2 800c740: d902 bls.n 800c748 { ret = HAL_TIMEOUT; 800c742: 2303 movs r3, #3 800c744: 77fb strb r3, [r7, #31] break; 800c746: e004 b.n 800c752 while (LL_RCC_LSE_IsReady() != 1U) 800c748: f7ff fdde bl 800c308 800c74c: 4603 mov r3, r0 800c74e: 2b01 cmp r3, #1 800c750: d1ee bne.n 800c730 } } } /* set overall return value */ status = ret; 800c752: 7ffb ldrb r3, [r7, #31] 800c754: 77bb strb r3, [r7, #30] 800c756: e001 b.n 800c75c } else { /* set overall return value */ status = ret; 800c758: 7ffb ldrb r3, [r7, #31] 800c75a: 77bb strb r3, [r7, #30] } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 800c75c: 687b ldr r3, [r7, #4] 800c75e: 681b ldr r3, [r3, #0] 800c760: f003 0301 and.w r3, r3, #1 800c764: 2b00 cmp r3, #0 800c766: d004 beq.n 800c772 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 800c768: 687b ldr r3, [r7, #4] 800c76a: 699b ldr r3, [r3, #24] 800c76c: 4618 mov r0, r3 800c76e: f7ff fe2a bl 800c3c6 } #if defined(LPUART1) /*-------------------------- LPUART1 clock source configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800c772: 687b ldr r3, [r7, #4] 800c774: 681b ldr r3, [r3, #0] 800c776: f003 0302 and.w r3, r3, #2 800c77a: 2b00 cmp r3, #0 800c77c: d004 beq.n 800c788 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800c77e: 687b ldr r3, [r7, #4] 800c780: 69db ldr r3, [r3, #28] 800c782: 4618 mov r0, r3 800c784: f7ff fe35 bl 800c3f2 } #endif /* LPUART1 */ /*-------------------------- LPTIM1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) 800c788: 687b ldr r3, [r7, #4] 800c78a: 681b ldr r3, [r3, #0] 800c78c: f003 0310 and.w r3, r3, #16 800c790: 2b00 cmp r3, #0 800c792: d004 beq.n 800c79e { assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800c794: 687b ldr r3, [r7, #4] 800c796: 6a9b ldr r3, [r3, #40] @ 0x28 800c798: 4618 mov r0, r3 800c79a: f7ff fe5d bl 800c458 } /*-------------------------- LPTIM2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) 800c79e: 687b ldr r3, [r7, #4] 800c7a0: 681b ldr r3, [r3, #0] 800c7a2: f003 0320 and.w r3, r3, #32 800c7a6: 2b00 cmp r3, #0 800c7a8: d004 beq.n 800c7b4 { assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800c7aa: 687b ldr r3, [r7, #4] 800c7ac: 6adb ldr r3, [r3, #44] @ 0x2c 800c7ae: 4618 mov r0, r3 800c7b0: f7ff fe52 bl 800c458 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 800c7b4: 687b ldr r3, [r7, #4] 800c7b6: 681b ldr r3, [r3, #0] 800c7b8: f003 0304 and.w r3, r3, #4 800c7bc: 2b00 cmp r3, #0 800c7be: d004 beq.n 800c7ca { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 800c7c0: 687b ldr r3, [r7, #4] 800c7c2: 6a1b ldr r3, [r3, #32] 800c7c4: 4618 mov r0, r3 800c7c6: f7ff fe2a bl 800c41e } #if defined(I2C3) /*-------------------------- I2C3 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 800c7ca: 687b ldr r3, [r7, #4] 800c7cc: 681b ldr r3, [r3, #0] 800c7ce: f003 0308 and.w r3, r3, #8 800c7d2: 2b00 cmp r3, #0 800c7d4: d004 beq.n 800c7e0 { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 800c7d6: 687b ldr r3, [r7, #4] 800c7d8: 6a5b ldr r3, [r3, #36] @ 0x24 800c7da: 4618 mov r0, r3 800c7dc: f7ff fe1f bl 800c41e } #endif /* I2C3 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 800c7e0: 687b ldr r3, [r7, #4] 800c7e2: 681b ldr r3, [r3, #0] 800c7e4: f403 7380 and.w r3, r3, #256 @ 0x100 800c7e8: 2b00 cmp r3, #0 800c7ea: d022 beq.n 800c832 { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800c7ec: 687b ldr r3, [r7, #4] 800c7ee: 6b5b ldr r3, [r3, #52] @ 0x34 800c7f0: 4618 mov r0, r3 800c7f2: f7ff fe8d bl 800c510 if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 800c7f6: 687b ldr r3, [r7, #4] 800c7f8: 6b5b ldr r3, [r3, #52] @ 0x34 800c7fa: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800c7fe: d107 bne.n 800c810 { /* Enable PLLQ output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK); 800c800: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c804: 68db ldr r3, [r3, #12] 800c806: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c80a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800c80e: 60d3 str r3, [r2, #12] } #if defined(SAI1) if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) 800c810: 687b ldr r3, [r7, #4] 800c812: 6b5b ldr r3, [r3, #52] @ 0x34 800c814: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c818: d10b bne.n 800c832 { /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1)); 800c81a: 687b ldr r3, [r7, #4] 800c81c: 3304 adds r3, #4 800c81e: 4618 mov r0, r3 800c820: f000 f8e3 bl 800c9ea 800c824: 4603 mov r3, r0 800c826: 77fb strb r3, [r7, #31] if (ret != HAL_OK) 800c828: 7ffb ldrb r3, [r7, #31] 800c82a: 2b00 cmp r3, #0 800c82c: d001 beq.n 800c832 { /* set overall return value */ status = ret; 800c82e: 7ffb ldrb r3, [r7, #31] 800c830: 77bb strb r3, [r7, #30] #endif /* SAI1 */ } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 800c832: 687b ldr r3, [r7, #4] 800c834: 681b ldr r3, [r3, #0] 800c836: f403 7300 and.w r3, r3, #512 @ 0x200 800c83a: 2b00 cmp r3, #0 800c83c: d02b beq.n 800c896 { /* Check the parameters */ assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); /* Configure the RNG clock source */ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800c83e: 687b ldr r3, [r7, #4] 800c840: 6b9b ldr r3, [r3, #56] @ 0x38 800c842: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800c846: d008 beq.n 800c85a 800c848: 687b ldr r3, [r7, #4] 800c84a: 6b9b ldr r3, [r3, #56] @ 0x38 800c84c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800c850: d003 beq.n 800c85a 800c852: 687b ldr r3, [r7, #4] 800c854: 6b9b ldr r3, [r3, #56] @ 0x38 800c856: 2b00 cmp r3, #0 800c858: d105 bne.n 800c866 800c85a: 687b ldr r3, [r7, #4] 800c85c: 6b9b ldr r3, [r3, #56] @ 0x38 800c85e: 4618 mov r0, r3 800c860: f7ff fe2a bl 800c4b8 800c864: e00a b.n 800c87c 800c866: 687b ldr r3, [r7, #4] 800c868: 6b9b ldr r3, [r3, #56] @ 0x38 800c86a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800c86e: 60fb str r3, [r7, #12] 800c870: 2000 movs r0, #0 800c872: f7ff fe21 bl 800c4b8 800c876: 68f8 ldr r0, [r7, #12] 800c878: f7ff fe34 bl 800c4e4 if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 800c87c: 687b ldr r3, [r7, #4] 800c87e: 6b9b ldr r3, [r3, #56] @ 0x38 800c880: f1b3 5fc0 cmp.w r3, #402653184 @ 0x18000000 800c884: d107 bne.n 800c896 { /* Enable PLLQ output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); 800c886: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c88a: 68db ldr r3, [r3, #12] 800c88c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c890: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800c894: 60d3 str r3, [r2, #12] } } /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800c896: 687b ldr r3, [r7, #4] 800c898: 681b ldr r3, [r3, #0] 800c89a: f403 6380 and.w r3, r3, #1024 @ 0x400 800c89e: 2b00 cmp r3, #0 800c8a0: d022 beq.n 800c8e8 { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800c8a2: 687b ldr r3, [r7, #4] 800c8a4: 6bdb ldr r3, [r3, #60] @ 0x3c 800c8a6: 4618 mov r0, r3 800c8a8: f7ff fe3d bl 800c526 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) 800c8ac: 687b ldr r3, [r7, #4] 800c8ae: 6bdb ldr r3, [r3, #60] @ 0x3c 800c8b0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c8b4: d107 bne.n 800c8c6 { /* Enable RCC_PLL_RNGCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 800c8b6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c8ba: 68db ldr r3, [r3, #12] 800c8bc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800c8c0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c8c4: 60d3 str r3, [r2, #12] } #if defined(SAI1) if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) 800c8c6: 687b ldr r3, [r7, #4] 800c8c8: 6bdb ldr r3, [r3, #60] @ 0x3c 800c8ca: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800c8ce: d10b bne.n 800c8e8 { /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1)); 800c8d0: 687b ldr r3, [r7, #4] 800c8d2: 3304 adds r3, #4 800c8d4: 4618 mov r0, r3 800c8d6: f000 f8e3 bl 800caa0 800c8da: 4603 mov r3, r0 800c8dc: 77fb strb r3, [r7, #31] if (ret != HAL_OK) 800c8de: 7ffb ldrb r3, [r7, #31] 800c8e0: 2b00 cmp r3, #0 800c8e2: d001 beq.n 800c8e8 { /* set overall return value */ status = ret; 800c8e4: 7ffb ldrb r3, [r7, #31] 800c8e6: 77bb strb r3, [r7, #30] } #endif /* SAI1 */ } /*-------------------------- RFWKP clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP) 800c8e8: 687b ldr r3, [r7, #4] 800c8ea: 681b ldr r3, [r3, #0] 800c8ec: f403 5380 and.w r3, r3, #4096 @ 0x1000 800c8f0: 2b00 cmp r3, #0 800c8f2: d004 beq.n 800c8fe { /* Check the parameters */ assert_param(IS_RCC_RFWKPCLKSOURCE(PeriphClkInit->RFWakeUpClockSelection)); /* Configure the RFWKP interface clock source */ __HAL_RCC_RFWAKEUP_CONFIG(PeriphClkInit->RFWakeUpClockSelection); 800c8f4: 687b ldr r3, [r7, #4] 800c8f6: 6c5b ldr r3, [r3, #68] @ 0x44 800c8f8: 4618 mov r0, r3 800c8fa: f7ff fd26 bl 800c34a } #if defined(RCC_SMPS_SUPPORT) /*-------------------------- SMPS clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) 800c8fe: 687b ldr r3, [r7, #4] 800c900: 681b ldr r3, [r3, #0] 800c902: f403 5300 and.w r3, r3, #8192 @ 0x2000 800c906: 2b00 cmp r3, #0 800c908: d009 beq.n 800c91e /* Check the parameters */ assert_param(IS_RCC_SMPSCLKDIV(PeriphClkInit->SmpsDivSelection)); assert_param(IS_RCC_SMPSCLKSOURCE(PeriphClkInit->SmpsClockSelection)); /* Configure the SMPS interface clock division factor */ __HAL_RCC_SMPS_DIV_CONFIG(PeriphClkInit->SmpsDivSelection); 800c90a: 687b ldr r3, [r7, #4] 800c90c: 6cdb ldr r3, [r3, #76] @ 0x4c 800c90e: 4618 mov r0, r3 800c910: f7ff fd45 bl 800c39e /* Configure the SMPS interface clock source */ __HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection); 800c914: 687b ldr r3, [r7, #4] 800c916: 6c9b ldr r3, [r3, #72] @ 0x48 800c918: 4618 mov r0, r3 800c91a: f7ff fd2c bl 800c376 } #endif /* RCC_SMPS_SUPPORT */ return status; 800c91e: 7fbb ldrb r3, [r7, #30] } 800c920: 4618 mov r0, r3 800c922: 3720 adds r7, #32 800c924: 46bd mov sp, r7 800c926: bd80 pop {r7, pc} 0800c928 : * @note Prior to enable the PLL-mode of the MSI for automatic hardware * calibration LSE oscillator is to be enabled with @ref HAL_RCC_OscConfig(). * @retval None */ void HAL_RCCEx_EnableMSIPLLMode(void) { 800c928: b580 push {r7, lr} 800c92a: af00 add r7, sp, #0 LL_RCC_MSI_EnablePLLMode() ; 800c92c: f7ff fcfe bl 800c32c } 800c930: bf00 nop 800c932: bd80 pop {r7, pc} 0800c934 : * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1) { 800c934: b580 push {r7, lr} 800c936: b084 sub sp, #16 800c938: af00 add r7, sp, #0 800c93a: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800c93c: 2300 movs r3, #0 800c93e: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); assert_param(IS_RCC_PLLP_VALUE(PLLSAI1->PLLP)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); /* Disable the PLLSAI1 */ __HAL_RCC_PLLSAI1_DISABLE(); 800c940: f7ff fe5b bl 800c5fa /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c944: f7fa f804 bl 8006950 800c948: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready to be updated */ while (LL_RCC_PLLSAI1_IsReady() != 0U) 800c94a: e009 b.n 800c960 { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800c94c: f7fa f800 bl 8006950 800c950: 4602 mov r2, r0 800c952: 68bb ldr r3, [r7, #8] 800c954: 1ad3 subs r3, r2, r3 800c956: 2b02 cmp r3, #2 800c958: d902 bls.n 800c960 { status = HAL_TIMEOUT; 800c95a: 2303 movs r3, #3 800c95c: 73fb strb r3, [r7, #15] break; 800c95e: e004 b.n 800c96a while (LL_RCC_PLLSAI1_IsReady() != 0U) 800c960: f7ff fe5a bl 800c618 800c964: 4603 mov r3, r0 800c966: 2b00 cmp r3, #0 800c968: d1f0 bne.n 800c94c } } if (status == HAL_OK) 800c96a: 7bfb ldrb r3, [r7, #15] 800c96c: 2b00 cmp r3, #0 800c96e: d137 bne.n 800c9e0 { /* Configure the PLLSAI1 Multiplication factor N */ __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); 800c970: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c974: 691b ldr r3, [r3, #16] 800c976: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 800c97a: 687b ldr r3, [r7, #4] 800c97c: 681b ldr r3, [r3, #0] 800c97e: 021b lsls r3, r3, #8 800c980: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c984: 4313 orrs r3, r2 800c986: 610b str r3, [r1, #16] /* Configure the PLLSAI1 Division factor P */ __HAL_RCC_PLLSAI1_DIVP_CONFIG(PLLSAI1->PLLP); 800c988: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c98c: 691b ldr r3, [r3, #16] 800c98e: f423 1278 bic.w r2, r3, #4063232 @ 0x3e0000 800c992: 687b ldr r3, [r7, #4] 800c994: 685b ldr r3, [r3, #4] 800c996: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c99a: 4313 orrs r3, r2 800c99c: 610b str r3, [r1, #16] /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ __HAL_RCC_PLLSAI1_ENABLE(); 800c99e: f7ff fe1d bl 800c5dc /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c9a2: f7f9 ffd5 bl 8006950 800c9a6: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready */ while (LL_RCC_PLLSAI1_IsReady() != 1U) 800c9a8: e009 b.n 800c9be { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800c9aa: f7f9 ffd1 bl 8006950 800c9ae: 4602 mov r2, r0 800c9b0: 68bb ldr r3, [r7, #8] 800c9b2: 1ad3 subs r3, r2, r3 800c9b4: 2b02 cmp r3, #2 800c9b6: d902 bls.n 800c9be { status = HAL_TIMEOUT; 800c9b8: 2303 movs r3, #3 800c9ba: 73fb strb r3, [r7, #15] break; 800c9bc: e004 b.n 800c9c8 while (LL_RCC_PLLSAI1_IsReady() != 1U) 800c9be: f7ff fe2b bl 800c618 800c9c2: 4603 mov r3, r0 800c9c4: 2b01 cmp r3, #1 800c9c6: d1f0 bne.n 800c9aa } } if (status == HAL_OK) 800c9c8: 7bfb ldrb r3, [r7, #15] 800c9ca: 2b00 cmp r3, #0 800c9cc: d108 bne.n 800c9e0 { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); 800c9ce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800c9d2: 691a ldr r2, [r3, #16] 800c9d4: 687b ldr r3, [r7, #4] 800c9d6: 691b ldr r3, [r3, #16] 800c9d8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800c9dc: 4313 orrs r3, r2 800c9de: 610b str r3, [r1, #16] } } return status; 800c9e0: 7bfb ldrb r3, [r7, #15] } 800c9e2: 4618 mov r0, r3 800c9e4: 3710 adds r7, #16 800c9e6: 46bd mov sp, r7 800c9e8: bd80 pop {r7, pc} 0800c9ea : * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1) { 800c9ea: b580 push {r7, lr} 800c9ec: b084 sub sp, #16 800c9ee: af00 add r7, sp, #0 800c9f0: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800c9f2: 2300 movs r3, #0 800c9f4: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); assert_param(IS_RCC_PLLQ_VALUE(PLLSAI1->PLLQ)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); /* Disable the PLLSAI1 */ __HAL_RCC_PLLSAI1_DISABLE(); 800c9f6: f7ff fe00 bl 800c5fa /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c9fa: f7f9 ffa9 bl 8006950 800c9fe: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready to be updated */ while (LL_RCC_PLLSAI1_IsReady() != 0U) 800ca00: e009 b.n 800ca16 { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800ca02: f7f9 ffa5 bl 8006950 800ca06: 4602 mov r2, r0 800ca08: 68bb ldr r3, [r7, #8] 800ca0a: 1ad3 subs r3, r2, r3 800ca0c: 2b02 cmp r3, #2 800ca0e: d902 bls.n 800ca16 { status = HAL_TIMEOUT; 800ca10: 2303 movs r3, #3 800ca12: 73fb strb r3, [r7, #15] break; 800ca14: e004 b.n 800ca20 while (LL_RCC_PLLSAI1_IsReady() != 0U) 800ca16: f7ff fdff bl 800c618 800ca1a: 4603 mov r3, r0 800ca1c: 2b00 cmp r3, #0 800ca1e: d1f0 bne.n 800ca02 } } if (status == HAL_OK) 800ca20: 7bfb ldrb r3, [r7, #15] 800ca22: 2b00 cmp r3, #0 800ca24: d137 bne.n 800ca96 { /* Configure the PLLSAI1 Multiplication factor N */ __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); 800ca26: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ca2a: 691b ldr r3, [r3, #16] 800ca2c: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 800ca30: 687b ldr r3, [r7, #4] 800ca32: 681b ldr r3, [r3, #0] 800ca34: 021b lsls r3, r3, #8 800ca36: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800ca3a: 4313 orrs r3, r2 800ca3c: 610b str r3, [r1, #16] /* Configure the PLLSAI1 Division factor Q */ __HAL_RCC_PLLSAI1_DIVQ_CONFIG(PLLSAI1->PLLQ); 800ca3e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ca42: 691b ldr r3, [r3, #16] 800ca44: f023 6260 bic.w r2, r3, #234881024 @ 0xe000000 800ca48: 687b ldr r3, [r7, #4] 800ca4a: 689b ldr r3, [r3, #8] 800ca4c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800ca50: 4313 orrs r3, r2 800ca52: 610b str r3, [r1, #16] /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ __HAL_RCC_PLLSAI1_ENABLE(); 800ca54: f7ff fdc2 bl 800c5dc /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ca58: f7f9 ff7a bl 8006950 800ca5c: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready */ while (LL_RCC_PLLSAI1_IsReady() != 1U) 800ca5e: e009 b.n 800ca74 { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800ca60: f7f9 ff76 bl 8006950 800ca64: 4602 mov r2, r0 800ca66: 68bb ldr r3, [r7, #8] 800ca68: 1ad3 subs r3, r2, r3 800ca6a: 2b02 cmp r3, #2 800ca6c: d902 bls.n 800ca74 { status = HAL_TIMEOUT; 800ca6e: 2303 movs r3, #3 800ca70: 73fb strb r3, [r7, #15] break; 800ca72: e004 b.n 800ca7e while (LL_RCC_PLLSAI1_IsReady() != 1U) 800ca74: f7ff fdd0 bl 800c618 800ca78: 4603 mov r3, r0 800ca7a: 2b01 cmp r3, #1 800ca7c: d1f0 bne.n 800ca60 } } if (status == HAL_OK) 800ca7e: 7bfb ldrb r3, [r7, #15] 800ca80: 2b00 cmp r3, #0 800ca82: d108 bne.n 800ca96 { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); 800ca84: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ca88: 691a ldr r2, [r3, #16] 800ca8a: 687b ldr r3, [r7, #4] 800ca8c: 691b ldr r3, [r3, #16] 800ca8e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800ca92: 4313 orrs r3, r2 800ca94: 610b str r3, [r1, #16] } } return status; 800ca96: 7bfb ldrb r3, [r7, #15] } 800ca98: 4618 mov r0, r3 800ca9a: 3710 adds r7, #16 800ca9c: 46bd mov sp, r7 800ca9e: bd80 pop {r7, pc} 0800caa0 : * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1) { 800caa0: b580 push {r7, lr} 800caa2: b084 sub sp, #16 800caa4: af00 add r7, sp, #0 800caa6: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800caa8: 2300 movs r3, #0 800caaa: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN)); assert_param(IS_RCC_PLLR_VALUE(PLLSAI1->PLLR)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut)); /* Disable the PLLSAI1 */ __HAL_RCC_PLLSAI1_DISABLE(); 800caac: f7ff fda5 bl 800c5fa /* Get Start Tick*/ tickstart = HAL_GetTick(); 800cab0: f7f9 ff4e bl 8006950 800cab4: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready to be updated */ while (LL_RCC_PLLSAI1_IsReady() != 0U) 800cab6: e009 b.n 800cacc { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800cab8: f7f9 ff4a bl 8006950 800cabc: 4602 mov r2, r0 800cabe: 68bb ldr r3, [r7, #8] 800cac0: 1ad3 subs r3, r2, r3 800cac2: 2b02 cmp r3, #2 800cac4: d902 bls.n 800cacc { status = HAL_TIMEOUT; 800cac6: 2303 movs r3, #3 800cac8: 73fb strb r3, [r7, #15] break; 800caca: e004 b.n 800cad6 while (LL_RCC_PLLSAI1_IsReady() != 0U) 800cacc: f7ff fda4 bl 800c618 800cad0: 4603 mov r3, r0 800cad2: 2b00 cmp r3, #0 800cad4: d1f0 bne.n 800cab8 } } if (status == HAL_OK) 800cad6: 7bfb ldrb r3, [r7, #15] 800cad8: 2b00 cmp r3, #0 800cada: d137 bne.n 800cb4c { /* Configure the PLLSAI1 Multiplication factor N */ __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN); 800cadc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800cae0: 691b ldr r3, [r3, #16] 800cae2: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 800cae6: 687b ldr r3, [r7, #4] 800cae8: 681b ldr r3, [r3, #0] 800caea: 021b lsls r3, r3, #8 800caec: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800caf0: 4313 orrs r3, r2 800caf2: 610b str r3, [r1, #16] /* Configure the PLLSAI1 Division factor R */ __HAL_RCC_PLLSAI1_DIVR_CONFIG(PLLSAI1->PLLR); 800caf4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800caf8: 691b ldr r3, [r3, #16] 800cafa: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000 800cafe: 687b ldr r3, [r7, #4] 800cb00: 68db ldr r3, [r3, #12] 800cb02: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800cb06: 4313 orrs r3, r2 800cb08: 610b str r3, [r1, #16] /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ __HAL_RCC_PLLSAI1_ENABLE(); 800cb0a: f7ff fd67 bl 800c5dc /* Get Start Tick*/ tickstart = HAL_GetTick(); 800cb0e: f7f9 ff1f bl 8006950 800cb12: 60b8 str r0, [r7, #8] /* Wait till PLLSAI1 is ready */ while (LL_RCC_PLLSAI1_IsReady() != 1U) 800cb14: e009 b.n 800cb2a { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 800cb16: f7f9 ff1b bl 8006950 800cb1a: 4602 mov r2, r0 800cb1c: 68bb ldr r3, [r7, #8] 800cb1e: 1ad3 subs r3, r2, r3 800cb20: 2b02 cmp r3, #2 800cb22: d902 bls.n 800cb2a { status = HAL_TIMEOUT; 800cb24: 2303 movs r3, #3 800cb26: 73fb strb r3, [r7, #15] break; 800cb28: e004 b.n 800cb34 while (LL_RCC_PLLSAI1_IsReady() != 1U) 800cb2a: f7ff fd75 bl 800c618 800cb2e: 4603 mov r3, r0 800cb30: 2b01 cmp r3, #1 800cb32: d1f0 bne.n 800cb16 } } if (status == HAL_OK) 800cb34: 7bfb ldrb r3, [r7, #15] 800cb36: 2b00 cmp r3, #0 800cb38: d108 bne.n 800cb4c { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut); 800cb3a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800cb3e: 691a ldr r2, [r3, #16] 800cb40: 687b ldr r3, [r7, #4] 800cb42: 691b ldr r3, [r3, #16] 800cb44: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800cb48: 4313 orrs r3, r2 800cb4a: 610b str r3, [r1, #16] } } return status; 800cb4c: 7bfb ldrb r3, [r7, #15] } 800cb4e: 4618 mov r0, r3 800cb50: 3710 adds r7, #16 800cb52: 46bd mov sp, r7 800cb54: bd80 pop {r7, pc} 0800cb56 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 800cb56: b580 push {r7, lr} 800cb58: b084 sub sp, #16 800cb5a: af00 add r7, sp, #0 800cb5c: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; /* Check RTC handler validity */ if (hrtc == NULL) 800cb5e: 687b ldr r3, [r7, #4] 800cb60: 2b00 cmp r3, #0 800cb62: d101 bne.n 800cb68 { return HAL_ERROR; 800cb64: 2301 movs r3, #1 800cb66: e07a b.n 800cc5e { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else /* USE_HAL_RTC_REGISTER_CALLBACKS */ if (hrtc->State == HAL_RTC_STATE_RESET) 800cb68: 687b ldr r3, [r7, #4] 800cb6a: f893 3021 ldrb.w r3, [r3, #33] @ 0x21 800cb6e: b2db uxtb r3, r3 800cb70: 2b00 cmp r3, #0 800cb72: d106 bne.n 800cb82 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 800cb74: 687b ldr r3, [r7, #4] 800cb76: 2200 movs r2, #0 800cb78: f883 2020 strb.w r2, [r3, #32] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 800cb7c: 6878 ldr r0, [r7, #4] 800cb7e: f7f9 fb25 bl 80061cc } #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 800cb82: 687b ldr r3, [r7, #4] 800cb84: 2202 movs r2, #2 800cb86: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Check whether the calendar needs to be initialized */ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) 800cb8a: 687b ldr r3, [r7, #4] 800cb8c: 681b ldr r3, [r3, #0] 800cb8e: 68db ldr r3, [r3, #12] 800cb90: f003 0310 and.w r3, r3, #16 800cb94: 2b10 cmp r3, #16 800cb96: d058 beq.n 800cc4a { /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 800cb98: 687b ldr r3, [r7, #4] 800cb9a: 681b ldr r3, [r3, #0] 800cb9c: 22ca movs r2, #202 @ 0xca 800cb9e: 625a str r2, [r3, #36] @ 0x24 800cba0: 687b ldr r3, [r7, #4] 800cba2: 681b ldr r3, [r3, #0] 800cba4: 2253 movs r2, #83 @ 0x53 800cba6: 625a str r2, [r3, #36] @ 0x24 /* Enter Initialization mode */ status = RTC_EnterInitMode(hrtc); 800cba8: 6878 ldr r0, [r7, #4] 800cbaa: f000 f883 bl 800ccb4 800cbae: 4603 mov r3, r0 800cbb0: 73fb strb r3, [r7, #15] if (status == HAL_OK) 800cbb2: 7bfb ldrb r3, [r7, #15] 800cbb4: 2b00 cmp r3, #0 800cbb6: d12c bne.n 800cc12 { /* Clear RTC_CR FMT, OSEL and POL Bits */ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); 800cbb8: 687b ldr r3, [r7, #4] 800cbba: 681b ldr r3, [r3, #0] 800cbbc: 689b ldr r3, [r3, #8] 800cbbe: 687a ldr r2, [r7, #4] 800cbc0: 6812 ldr r2, [r2, #0] 800cbc2: f423 03e0 bic.w r3, r3, #7340032 @ 0x700000 800cbc6: f023 0340 bic.w r3, r3, #64 @ 0x40 800cbca: 6093 str r3, [r2, #8] /* Set RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); 800cbcc: 687b ldr r3, [r7, #4] 800cbce: 681b ldr r3, [r3, #0] 800cbd0: 6899 ldr r1, [r3, #8] 800cbd2: 687b ldr r3, [r7, #4] 800cbd4: 685a ldr r2, [r3, #4] 800cbd6: 687b ldr r3, [r7, #4] 800cbd8: 691b ldr r3, [r3, #16] 800cbda: 431a orrs r2, r3 800cbdc: 687b ldr r3, [r7, #4] 800cbde: 699b ldr r3, [r3, #24] 800cbe0: 431a orrs r2, r3 800cbe2: 687b ldr r3, [r7, #4] 800cbe4: 681b ldr r3, [r3, #0] 800cbe6: 430a orrs r2, r1 800cbe8: 609a str r2, [r3, #8] /* Configure the RTC PRER */ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); 800cbea: 687b ldr r3, [r7, #4] 800cbec: 681b ldr r3, [r3, #0] 800cbee: 687a ldr r2, [r7, #4] 800cbf0: 68d2 ldr r2, [r2, #12] 800cbf2: 611a str r2, [r3, #16] hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); 800cbf4: 687b ldr r3, [r7, #4] 800cbf6: 681b ldr r3, [r3, #0] 800cbf8: 6919 ldr r1, [r3, #16] 800cbfa: 687b ldr r3, [r7, #4] 800cbfc: 689b ldr r3, [r3, #8] 800cbfe: 041a lsls r2, r3, #16 800cc00: 687b ldr r3, [r7, #4] 800cc02: 681b ldr r3, [r3, #0] 800cc04: 430a orrs r2, r1 800cc06: 611a str r2, [r3, #16] /* Exit Initialization mode */ status = RTC_ExitInitMode(hrtc); 800cc08: 6878 ldr r0, [r7, #4] 800cc0a: f000 f88b bl 800cd24 800cc0e: 4603 mov r3, r0 800cc10: 73fb strb r3, [r7, #15] } if (status == HAL_OK) 800cc12: 7bfb ldrb r3, [r7, #15] 800cc14: 2b00 cmp r3, #0 800cc16: d113 bne.n 800cc40 { #if defined(RTC_OR_ALARMOUTTYPE) hrtc->Instance->OR &= (uint32_t)~(RTC_OUTPUT_TYPE_PUSHPULL | RTC_OUTPUT_REMAP_POS1); 800cc18: 687b ldr r3, [r7, #4] 800cc1a: 681b ldr r3, [r3, #0] 800cc1c: 6cda ldr r2, [r3, #76] @ 0x4c 800cc1e: 687b ldr r3, [r7, #4] 800cc20: 681b ldr r3, [r3, #0] 800cc22: f022 0203 bic.w r2, r2, #3 800cc26: 64da str r2, [r3, #76] @ 0x4c hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); 800cc28: 687b ldr r3, [r7, #4] 800cc2a: 681b ldr r3, [r3, #0] 800cc2c: 6cd9 ldr r1, [r3, #76] @ 0x4c 800cc2e: 687b ldr r3, [r7, #4] 800cc30: 69da ldr r2, [r3, #28] 800cc32: 687b ldr r3, [r7, #4] 800cc34: 695b ldr r3, [r3, #20] 800cc36: 431a orrs r2, r3 800cc38: 687b ldr r3, [r7, #4] 800cc3a: 681b ldr r3, [r3, #0] 800cc3c: 430a orrs r2, r1 800cc3e: 64da str r2, [r3, #76] @ 0x4c hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutRemap); #endif /* RTC_OR_ALARMOUTTYPE */ } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800cc40: 687b ldr r3, [r7, #4] 800cc42: 681b ldr r3, [r3, #0] 800cc44: 22ff movs r2, #255 @ 0xff 800cc46: 625a str r2, [r3, #36] @ 0x24 800cc48: e001 b.n 800cc4e } else { /* The calendar is already initialized */ status = HAL_OK; 800cc4a: 2300 movs r3, #0 800cc4c: 73fb strb r3, [r7, #15] } if (status == HAL_OK) 800cc4e: 7bfb ldrb r3, [r7, #15] 800cc50: 2b00 cmp r3, #0 800cc52: d103 bne.n 800cc5c { hrtc->State = HAL_RTC_STATE_READY; 800cc54: 687b ldr r3, [r7, #4] 800cc56: 2201 movs r2, #1 800cc58: f883 2021 strb.w r2, [r3, #33] @ 0x21 } return status; 800cc5c: 7bfb ldrb r3, [r7, #15] } 800cc5e: 4618 mov r0, r3 800cc60: 3710 adds r7, #16 800cc62: 46bd mov sp, r7 800cc64: bd80 pop {r7, pc} ... 0800cc68 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { 800cc68: b580 push {r7, lr} 800cc6a: b084 sub sp, #16 800cc6c: af00 add r7, sp, #0 800cc6e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800cc70: 2300 movs r3, #0 800cc72: 60fb str r3, [r7, #12] /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK)); 800cc74: 687b ldr r3, [r7, #4] 800cc76: 681b ldr r3, [r3, #0] 800cc78: 4a0d ldr r2, [pc, #52] @ (800ccb0 ) 800cc7a: 60da str r2, [r3, #12] /* Get tick */ tickstart = HAL_GetTick(); 800cc7c: f7f9 fe68 bl 8006950 800cc80: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) 800cc82: e009 b.n 800cc98 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800cc84: f7f9 fe64 bl 8006950 800cc88: 4602 mov r2, r0 800cc8a: 68fb ldr r3, [r7, #12] 800cc8c: 1ad3 subs r3, r2, r3 800cc8e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800cc92: d901 bls.n 800cc98 { return HAL_TIMEOUT; 800cc94: 2303 movs r3, #3 800cc96: e007 b.n 800cca8 while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) 800cc98: 687b ldr r3, [r7, #4] 800cc9a: 681b ldr r3, [r3, #0] 800cc9c: 68db ldr r3, [r3, #12] 800cc9e: f003 0320 and.w r3, r3, #32 800cca2: 2b00 cmp r3, #0 800cca4: d0ee beq.n 800cc84 } } return HAL_OK; 800cca6: 2300 movs r3, #0 } 800cca8: 4618 mov r0, r3 800ccaa: 3710 adds r7, #16 800ccac: 46bd mov sp, r7 800ccae: bd80 pop {r7, pc} 800ccb0: 0001ff5f .word 0x0001ff5f 0800ccb4 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { 800ccb4: b580 push {r7, lr} 800ccb6: b084 sub sp, #16 800ccb8: af00 add r7, sp, #0 800ccba: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800ccbc: 2300 movs r3, #0 800ccbe: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 800ccc0: 2300 movs r3, #0 800ccc2: 73fb strb r3, [r7, #15] /* Check that Initialization mode is not already set */ if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) 800ccc4: 687b ldr r3, [r7, #4] 800ccc6: 681b ldr r3, [r3, #0] 800ccc8: 68db ldr r3, [r3, #12] 800ccca: f003 0340 and.w r3, r3, #64 @ 0x40 800ccce: 2b00 cmp r3, #0 800ccd0: d123 bne.n 800cd1a { /* Set INIT bit to enter Initialization mode */ SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); 800ccd2: 687b ldr r3, [r7, #4] 800ccd4: 681b ldr r3, [r3, #0] 800ccd6: 68da ldr r2, [r3, #12] 800ccd8: 687b ldr r3, [r7, #4] 800ccda: 681b ldr r3, [r3, #0] 800ccdc: f042 0280 orr.w r2, r2, #128 @ 0x80 800cce0: 60da str r2, [r3, #12] /* Get tick */ tickstart = HAL_GetTick(); 800cce2: f7f9 fe35 bl 8006950 800cce6: 60b8 str r0, [r7, #8] /* Wait till RTC is in INIT state and if timeout is reached exit */ while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) 800cce8: e00d b.n 800cd06 { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) 800ccea: f7f9 fe31 bl 8006950 800ccee: 4602 mov r2, r0 800ccf0: 68bb ldr r3, [r7, #8] 800ccf2: 1ad3 subs r3, r2, r3 800ccf4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800ccf8: d905 bls.n 800cd06 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 800ccfa: 687b ldr r3, [r7, #4] 800ccfc: 2204 movs r2, #4 800ccfe: f883 2021 strb.w r2, [r3, #33] @ 0x21 status = HAL_ERROR; 800cd02: 2301 movs r3, #1 800cd04: 73fb strb r3, [r7, #15] while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) 800cd06: 687b ldr r3, [r7, #4] 800cd08: 681b ldr r3, [r3, #0] 800cd0a: 68db ldr r3, [r3, #12] 800cd0c: f003 0340 and.w r3, r3, #64 @ 0x40 800cd10: 2b00 cmp r3, #0 800cd12: d102 bne.n 800cd1a 800cd14: 7bfb ldrb r3, [r7, #15] 800cd16: 2b01 cmp r3, #1 800cd18: d1e7 bne.n 800ccea } } } return status; 800cd1a: 7bfb ldrb r3, [r7, #15] } 800cd1c: 4618 mov r0, r3 800cd1e: 3710 adds r7, #16 800cd20: 46bd mov sp, r7 800cd22: bd80 pop {r7, pc} 0800cd24 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) { 800cd24: b580 push {r7, lr} 800cd26: b084 sub sp, #16 800cd28: af00 add r7, sp, #0 800cd2a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800cd2c: 2300 movs r3, #0 800cd2e: 73fb strb r3, [r7, #15] /* Clear INIT bit to exit Initialization mode */ CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); 800cd30: 687b ldr r3, [r7, #4] 800cd32: 681b ldr r3, [r3, #0] 800cd34: 68da ldr r2, [r3, #12] 800cd36: 687b ldr r3, [r7, #4] 800cd38: 681b ldr r3, [r3, #0] 800cd3a: f022 0280 bic.w r2, r2, #128 @ 0x80 800cd3e: 60da str r2, [r3, #12] /* If CR_BYPSHAD bit = 0, wait for synchro */ if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U) 800cd40: 687b ldr r3, [r7, #4] 800cd42: 681b ldr r3, [r3, #0] 800cd44: 689b ldr r3, [r3, #8] 800cd46: f003 0320 and.w r3, r3, #32 800cd4a: 2b00 cmp r3, #0 800cd4c: d10b bne.n 800cd66 { if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 800cd4e: 6878 ldr r0, [r7, #4] 800cd50: f7ff ff8a bl 800cc68 800cd54: 4603 mov r3, r0 800cd56: 2b00 cmp r3, #0 800cd58: d005 beq.n 800cd66 { /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 800cd5a: 687b ldr r3, [r7, #4] 800cd5c: 2204 movs r2, #4 800cd5e: f883 2021 strb.w r2, [r3, #33] @ 0x21 status = HAL_ERROR; 800cd62: 2301 movs r3, #1 800cd64: 73fb strb r3, [r7, #15] } } return status; 800cd66: 7bfb ldrb r3, [r7, #15] } 800cd68: 4618 mov r0, r3 800cd6a: 3710 adds r7, #16 800cd6c: 46bd mov sp, r7 800cd6e: bd80 pop {r7, pc} 0800cd70 : * @param WakeUpCounter Wakeup counter * @param WakeUpClock Wakeup clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { 800cd70: b480 push {r7} 800cd72: b087 sub sp, #28 800cd74: af00 add r7, sp, #0 800cd76: 60f8 str r0, [r7, #12] 800cd78: 60b9 str r1, [r7, #8] 800cd7a: 607a str r2, [r7, #4] __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); 800cd7c: 4b5f ldr r3, [pc, #380] @ (800cefc ) 800cd7e: 681b ldr r3, [r3, #0] 800cd80: 4a5f ldr r2, [pc, #380] @ (800cf00 ) 800cd82: fba2 2303 umull r2, r3, r2, r3 800cd86: 0adb lsrs r3, r3, #11 800cd88: f44f 727a mov.w r2, #1000 @ 0x3e8 800cd8c: fb02 f303 mul.w r3, r2, r3 800cd90: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); 800cd92: 68fb ldr r3, [r7, #12] 800cd94: f893 3020 ldrb.w r3, [r3, #32] 800cd98: 2b01 cmp r3, #1 800cd9a: d101 bne.n 800cda0 800cd9c: 2302 movs r3, #2 800cd9e: e0a7 b.n 800cef0 800cda0: 68fb ldr r3, [r7, #12] 800cda2: 2201 movs r2, #1 800cda4: f883 2020 strb.w r2, [r3, #32] hrtc->State = HAL_RTC_STATE_BUSY; 800cda8: 68fb ldr r3, [r7, #12] 800cdaa: 2202 movs r2, #2 800cdac: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 800cdb0: 68fb ldr r3, [r7, #12] 800cdb2: 681b ldr r3, [r3, #0] 800cdb4: 22ca movs r2, #202 @ 0xca 800cdb6: 625a str r2, [r3, #36] @ 0x24 800cdb8: 68fb ldr r3, [r7, #12] 800cdba: 681b ldr r3, [r3, #0] 800cdbc: 2253 movs r2, #83 @ 0x53 800cdbe: 625a str r2, [r3, #36] @ 0x24 /* Check RTC WUTWF flag is reset only when wakeup timer enabled */ if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) 800cdc0: 68fb ldr r3, [r7, #12] 800cdc2: 681b ldr r3, [r3, #0] 800cdc4: 689b ldr r3, [r3, #8] 800cdc6: f403 6380 and.w r3, r3, #1024 @ 0x400 800cdca: 2b00 cmp r3, #0 800cdcc: d01a beq.n 800ce04 { /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ do { count = count - 1U; 800cdce: 697b ldr r3, [r7, #20] 800cdd0: 3b01 subs r3, #1 800cdd2: 617b str r3, [r7, #20] if (count == 0U) 800cdd4: 697b ldr r3, [r7, #20] 800cdd6: 2b00 cmp r3, #0 800cdd8: d10d bne.n 800cdf6 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800cdda: 68fb ldr r3, [r7, #12] 800cddc: 681b ldr r3, [r3, #0] 800cdde: 22ff movs r2, #255 @ 0xff 800cde0: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_TIMEOUT; 800cde2: 68fb ldr r3, [r7, #12] 800cde4: 2203 movs r2, #3 800cde6: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hrtc); 800cdea: 68fb ldr r3, [r7, #12] 800cdec: 2200 movs r2, #0 800cdee: f883 2020 strb.w r2, [r3, #32] return HAL_TIMEOUT; 800cdf2: 2303 movs r3, #3 800cdf4: e07c b.n 800cef0 } } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U); 800cdf6: 68fb ldr r3, [r7, #12] 800cdf8: 681b ldr r3, [r3, #0] 800cdfa: 68db ldr r3, [r3, #12] 800cdfc: f003 0304 and.w r3, r3, #4 800ce00: 2b00 cmp r3, #0 800ce02: d1e4 bne.n 800cdce } /* Disable the Wakeup timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); 800ce04: 68fb ldr r3, [r7, #12] 800ce06: 681b ldr r3, [r3, #0] 800ce08: 689a ldr r2, [r3, #8] 800ce0a: 68fb ldr r3, [r7, #12] 800ce0c: 681b ldr r3, [r3, #0] 800ce0e: f422 6280 bic.w r2, r2, #1024 @ 0x400 800ce12: 609a str r2, [r3, #8] /* Clear the Wakeup flag */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); 800ce14: 68fb ldr r3, [r7, #12] 800ce16: 681b ldr r3, [r3, #0] 800ce18: 68db ldr r3, [r3, #12] 800ce1a: b2da uxtb r2, r3 800ce1c: 68fb ldr r3, [r7, #12] 800ce1e: 681b ldr r3, [r3, #0] 800ce20: f462 6290 orn r2, r2, #1152 @ 0x480 800ce24: 60da str r2, [r3, #12] /* Reload the counter */ count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); 800ce26: 4b35 ldr r3, [pc, #212] @ (800cefc ) 800ce28: 681b ldr r3, [r3, #0] 800ce2a: 4a35 ldr r2, [pc, #212] @ (800cf00 ) 800ce2c: fba2 2303 umull r2, r3, r2, r3 800ce30: 0adb lsrs r3, r3, #11 800ce32: f44f 727a mov.w r2, #1000 @ 0x3e8 800ce36: fb02 f303 mul.w r3, r2, r3 800ce3a: 617b str r3, [r7, #20] /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ do { count = count - 1U; 800ce3c: 697b ldr r3, [r7, #20] 800ce3e: 3b01 subs r3, #1 800ce40: 617b str r3, [r7, #20] if (count == 0U) 800ce42: 697b ldr r3, [r7, #20] 800ce44: 2b00 cmp r3, #0 800ce46: d10d bne.n 800ce64 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800ce48: 68fb ldr r3, [r7, #12] 800ce4a: 681b ldr r3, [r3, #0] 800ce4c: 22ff movs r2, #255 @ 0xff 800ce4e: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_TIMEOUT; 800ce50: 68fb ldr r3, [r7, #12] 800ce52: 2203 movs r2, #3 800ce54: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hrtc); 800ce58: 68fb ldr r3, [r7, #12] 800ce5a: 2200 movs r2, #0 800ce5c: f883 2020 strb.w r2, [r3, #32] return HAL_TIMEOUT; 800ce60: 2303 movs r3, #3 800ce62: e045 b.n 800cef0 } } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U); 800ce64: 68fb ldr r3, [r7, #12] 800ce66: 681b ldr r3, [r3, #0] 800ce68: 68db ldr r3, [r3, #12] 800ce6a: f003 0304 and.w r3, r3, #4 800ce6e: 2b00 cmp r3, #0 800ce70: d0e4 beq.n 800ce3c /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; 800ce72: 68fb ldr r3, [r7, #12] 800ce74: 681b ldr r3, [r3, #0] 800ce76: 689a ldr r2, [r3, #8] 800ce78: 68fb ldr r3, [r7, #12] 800ce7a: 681b ldr r3, [r3, #0] 800ce7c: f022 0207 bic.w r2, r2, #7 800ce80: 609a str r2, [r3, #8] /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; 800ce82: 68fb ldr r3, [r7, #12] 800ce84: 681b ldr r3, [r3, #0] 800ce86: 6899 ldr r1, [r3, #8] 800ce88: 68fb ldr r3, [r7, #12] 800ce8a: 681b ldr r3, [r3, #0] 800ce8c: 687a ldr r2, [r7, #4] 800ce8e: 430a orrs r2, r1 800ce90: 609a str r2, [r3, #8] /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; 800ce92: 68fb ldr r3, [r7, #12] 800ce94: 681b ldr r3, [r3, #0] 800ce96: 68ba ldr r2, [r7, #8] 800ce98: 615a str r2, [r3, #20] /* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); 800ce9a: 4b1a ldr r3, [pc, #104] @ (800cf04 ) 800ce9c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800cea0: 4a18 ldr r2, [pc, #96] @ (800cf04 ) 800cea2: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800cea6: f8c2 3080 str.w r3, [r2, #128] @ 0x80 __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); 800ceaa: 4b16 ldr r3, [pc, #88] @ (800cf04 ) 800ceac: 681b ldr r3, [r3, #0] 800ceae: 4a15 ldr r2, [pc, #84] @ (800cf04 ) 800ceb0: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800ceb4: 6013 str r3, [r2, #0] /* Configure the interrupt in the RTC_CR register */ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT); 800ceb6: 68fb ldr r3, [r7, #12] 800ceb8: 681b ldr r3, [r3, #0] 800ceba: 689a ldr r2, [r3, #8] 800cebc: 68fb ldr r3, [r7, #12] 800cebe: 681b ldr r3, [r3, #0] 800cec0: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800cec4: 609a str r2, [r3, #8] /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); 800cec6: 68fb ldr r3, [r7, #12] 800cec8: 681b ldr r3, [r3, #0] 800ceca: 689a ldr r2, [r3, #8] 800cecc: 68fb ldr r3, [r7, #12] 800cece: 681b ldr r3, [r3, #0] 800ced0: f442 6280 orr.w r2, r2, #1024 @ 0x400 800ced4: 609a str r2, [r3, #8] /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800ced6: 68fb ldr r3, [r7, #12] 800ced8: 681b ldr r3, [r3, #0] 800ceda: 22ff movs r2, #255 @ 0xff 800cedc: 625a str r2, [r3, #36] @ 0x24 hrtc->State = HAL_RTC_STATE_READY; 800cede: 68fb ldr r3, [r7, #12] 800cee0: 2201 movs r2, #1 800cee2: f883 2021 strb.w r2, [r3, #33] @ 0x21 /* Process Unlocked */ __HAL_UNLOCK(hrtc); 800cee6: 68fb ldr r3, [r7, #12] 800cee8: 2200 movs r2, #0 800ceea: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 800ceee: 2300 movs r3, #0 } 800cef0: 4618 mov r0, r3 800cef2: 371c adds r7, #28 800cef4: 46bd mov sp, r7 800cef6: f85d 7b04 ldr.w r7, [sp], #4 800cefa: 4770 bx lr 800cefc: 2000000c .word 0x2000000c 800cf00: 10624dd3 .word 0x10624dd3 800cf04: 58000800 .word 0x58000800 0800cf08 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 800cf08: b580 push {r7, lr} 800cf0a: b084 sub sp, #16 800cf0c: af00 add r7, sp, #0 800cf0e: 6078 str r0, [r7, #4] uint32_t frxth; /* Check the SPI handle allocation */ if (hspi == NULL) 800cf10: 687b ldr r3, [r7, #4] 800cf12: 2b00 cmp r3, #0 800cf14: d101 bne.n 800cf1a { return HAL_ERROR; 800cf16: 2301 movs r3, #1 800cf18: e095 b.n 800d046 assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 800cf1a: 687b ldr r3, [r7, #4] 800cf1c: 6a5b ldr r3, [r3, #36] @ 0x24 800cf1e: 2b00 cmp r3, #0 800cf20: d108 bne.n 800cf34 { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 800cf22: 687b ldr r3, [r7, #4] 800cf24: 685b ldr r3, [r3, #4] 800cf26: f5b3 7f82 cmp.w r3, #260 @ 0x104 800cf2a: d009 beq.n 800cf40 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 800cf2c: 687b ldr r3, [r7, #4] 800cf2e: 2200 movs r2, #0 800cf30: 61da str r2, [r3, #28] 800cf32: e005 b.n 800cf40 else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 800cf34: 687b ldr r3, [r7, #4] 800cf36: 2200 movs r2, #0 800cf38: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 800cf3a: 687b ldr r3, [r7, #4] 800cf3c: 2200 movs r2, #0 800cf3e: 615a str r2, [r3, #20] { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 800cf40: 687b ldr r3, [r7, #4] 800cf42: 2200 movs r2, #0 800cf44: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 800cf46: 687b ldr r3, [r7, #4] 800cf48: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800cf4c: b2db uxtb r3, r3 800cf4e: 2b00 cmp r3, #0 800cf50: d106 bne.n 800cf60 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 800cf52: 687b ldr r3, [r7, #4] 800cf54: 2200 movs r2, #0 800cf56: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 800cf5a: 6878 ldr r0, [r7, #4] 800cf5c: f7f9 f96c bl 8006238 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 800cf60: 687b ldr r3, [r7, #4] 800cf62: 2202 movs r2, #2 800cf64: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800cf68: 687b ldr r3, [r7, #4] 800cf6a: 681b ldr r3, [r3, #0] 800cf6c: 681a ldr r2, [r3, #0] 800cf6e: 687b ldr r3, [r7, #4] 800cf70: 681b ldr r3, [r3, #0] 800cf72: f022 0240 bic.w r2, r2, #64 @ 0x40 800cf76: 601a str r2, [r3, #0] /* Align by default the rs fifo threshold on the data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 800cf78: 687b ldr r3, [r7, #4] 800cf7a: 68db ldr r3, [r3, #12] 800cf7c: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800cf80: d902 bls.n 800cf88 { frxth = SPI_RXFIFO_THRESHOLD_HF; 800cf82: 2300 movs r3, #0 800cf84: 60fb str r3, [r7, #12] 800cf86: e002 b.n 800cf8e } else { frxth = SPI_RXFIFO_THRESHOLD_QF; 800cf88: f44f 5380 mov.w r3, #4096 @ 0x1000 800cf8c: 60fb str r3, [r7, #12] } /* CRC calculation is valid only for 16Bit and 8 Bit */ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) 800cf8e: 687b ldr r3, [r7, #4] 800cf90: 68db ldr r3, [r3, #12] 800cf92: f5b3 6f70 cmp.w r3, #3840 @ 0xf00 800cf96: d007 beq.n 800cfa8 800cf98: 687b ldr r3, [r7, #4] 800cf9a: 68db ldr r3, [r3, #12] 800cf9c: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800cfa0: d002 beq.n 800cfa8 { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 800cfa2: 687b ldr r3, [r7, #4] 800cfa4: 2200 movs r2, #0 800cfa6: 629a str r2, [r3, #40] @ 0x28 } /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 800cfa8: 687b ldr r3, [r7, #4] 800cfaa: 685b ldr r3, [r3, #4] 800cfac: f403 7282 and.w r2, r3, #260 @ 0x104 800cfb0: 687b ldr r3, [r7, #4] 800cfb2: 689b ldr r3, [r3, #8] 800cfb4: f403 4304 and.w r3, r3, #33792 @ 0x8400 800cfb8: 431a orrs r2, r3 800cfba: 687b ldr r3, [r7, #4] 800cfbc: 691b ldr r3, [r3, #16] 800cfbe: f003 0302 and.w r3, r3, #2 800cfc2: 431a orrs r2, r3 800cfc4: 687b ldr r3, [r7, #4] 800cfc6: 695b ldr r3, [r3, #20] 800cfc8: f003 0301 and.w r3, r3, #1 800cfcc: 431a orrs r2, r3 800cfce: 687b ldr r3, [r7, #4] 800cfd0: 699b ldr r3, [r3, #24] 800cfd2: f403 7300 and.w r3, r3, #512 @ 0x200 800cfd6: 431a orrs r2, r3 800cfd8: 687b ldr r3, [r7, #4] 800cfda: 69db ldr r3, [r3, #28] 800cfdc: f003 0338 and.w r3, r3, #56 @ 0x38 800cfe0: 431a orrs r2, r3 800cfe2: 687b ldr r3, [r7, #4] 800cfe4: 6a1b ldr r3, [r3, #32] 800cfe6: f003 0380 and.w r3, r3, #128 @ 0x80 800cfea: ea42 0103 orr.w r1, r2, r3 800cfee: 687b ldr r3, [r7, #4] 800cff0: 6a9b ldr r3, [r3, #40] @ 0x28 800cff2: f403 5200 and.w r2, r3, #8192 @ 0x2000 800cff6: 687b ldr r3, [r7, #4] 800cff8: 681b ldr r3, [r3, #0] 800cffa: 430a orrs r2, r1 800cffc: 601a str r2, [r3, #0] } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | 800cffe: 687b ldr r3, [r7, #4] 800d000: 699b ldr r3, [r3, #24] 800d002: 0c1b lsrs r3, r3, #16 800d004: f003 0204 and.w r2, r3, #4 800d008: 687b ldr r3, [r7, #4] 800d00a: 6a5b ldr r3, [r3, #36] @ 0x24 800d00c: f003 0310 and.w r3, r3, #16 800d010: 431a orrs r2, r3 800d012: 687b ldr r3, [r7, #4] 800d014: 6b5b ldr r3, [r3, #52] @ 0x34 800d016: f003 0308 and.w r3, r3, #8 800d01a: 431a orrs r2, r3 800d01c: 687b ldr r3, [r7, #4] 800d01e: 68db ldr r3, [r3, #12] 800d020: f403 6370 and.w r3, r3, #3840 @ 0xf00 800d024: ea42 0103 orr.w r1, r2, r3 800d028: 68fb ldr r3, [r7, #12] 800d02a: f403 5280 and.w r2, r3, #4096 @ 0x1000 800d02e: 687b ldr r3, [r7, #4] 800d030: 681b ldr r3, [r3, #0] 800d032: 430a orrs r2, r1 800d034: 605a str r2, [r3, #4] #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800d036: 687b ldr r3, [r7, #4] 800d038: 2200 movs r2, #0 800d03a: 661a str r2, [r3, #96] @ 0x60 hspi->State = HAL_SPI_STATE_READY; 800d03c: 687b ldr r3, [r7, #4] 800d03e: 2201 movs r2, #1 800d040: f883 205d strb.w r2, [r3, #93] @ 0x5d return HAL_OK; 800d044: 2300 movs r3, #0 } 800d046: 4618 mov r0, r3 800d048: 3710 adds r7, #16 800d04a: 46bd mov sp, r7 800d04c: bd80 pop {r7, pc} 0800d04e : * @param Size amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration in ms * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 800d04e: b580 push {r7, lr} 800d050: b088 sub sp, #32 800d052: af00 add r7, sp, #0 800d054: 60f8 str r0, [r7, #12] 800d056: 60b9 str r1, [r7, #8] 800d058: 603b str r3, [r7, #0] 800d05a: 4613 mov r3, r2 800d05c: 80fb strh r3, [r7, #6] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800d05e: f7f9 fc77 bl 8006950 800d062: 61f8 str r0, [r7, #28] initial_TxXferCount = Size; 800d064: 88fb ldrh r3, [r7, #6] 800d066: 837b strh r3, [r7, #26] if (hspi->State != HAL_SPI_STATE_READY) 800d068: 68fb ldr r3, [r7, #12] 800d06a: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d06e: b2db uxtb r3, r3 800d070: 2b01 cmp r3, #1 800d072: d001 beq.n 800d078 { return HAL_BUSY; 800d074: 2302 movs r3, #2 800d076: e15c b.n 800d332 } if ((pData == NULL) || (Size == 0U)) 800d078: 68bb ldr r3, [r7, #8] 800d07a: 2b00 cmp r3, #0 800d07c: d002 beq.n 800d084 800d07e: 88fb ldrh r3, [r7, #6] 800d080: 2b00 cmp r3, #0 800d082: d101 bne.n 800d088 { return HAL_ERROR; 800d084: 2301 movs r3, #1 800d086: e154 b.n 800d332 } /* Process Locked */ __HAL_LOCK(hspi); 800d088: 68fb ldr r3, [r7, #12] 800d08a: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 800d08e: 2b01 cmp r3, #1 800d090: d101 bne.n 800d096 800d092: 2302 movs r3, #2 800d094: e14d b.n 800d332 800d096: 68fb ldr r3, [r7, #12] 800d098: 2201 movs r2, #1 800d09a: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; 800d09e: 68fb ldr r3, [r7, #12] 800d0a0: 2203 movs r2, #3 800d0a2: f883 205d strb.w r2, [r3, #93] @ 0x5d hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800d0a6: 68fb ldr r3, [r7, #12] 800d0a8: 2200 movs r2, #0 800d0aa: 661a str r2, [r3, #96] @ 0x60 hspi->pTxBuffPtr = (const uint8_t *)pData; 800d0ac: 68fb ldr r3, [r7, #12] 800d0ae: 68ba ldr r2, [r7, #8] 800d0b0: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferSize = Size; 800d0b2: 68fb ldr r3, [r7, #12] 800d0b4: 88fa ldrh r2, [r7, #6] 800d0b6: 879a strh r2, [r3, #60] @ 0x3c hspi->TxXferCount = Size; 800d0b8: 68fb ldr r3, [r7, #12] 800d0ba: 88fa ldrh r2, [r7, #6] 800d0bc: 87da strh r2, [r3, #62] @ 0x3e /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; 800d0be: 68fb ldr r3, [r7, #12] 800d0c0: 2200 movs r2, #0 800d0c2: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferSize = 0U; 800d0c4: 68fb ldr r3, [r7, #12] 800d0c6: 2200 movs r2, #0 800d0c8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hspi->RxXferCount = 0U; 800d0cc: 68fb ldr r3, [r7, #12] 800d0ce: 2200 movs r2, #0 800d0d0: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->TxISR = NULL; 800d0d4: 68fb ldr r3, [r7, #12] 800d0d6: 2200 movs r2, #0 800d0d8: 651a str r2, [r3, #80] @ 0x50 hspi->RxISR = NULL; 800d0da: 68fb ldr r3, [r7, #12] 800d0dc: 2200 movs r2, #0 800d0de: 64da str r2, [r3, #76] @ 0x4c /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 800d0e0: 68fb ldr r3, [r7, #12] 800d0e2: 689b ldr r3, [r3, #8] 800d0e4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d0e8: d10f bne.n 800d10a { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 800d0ea: 68fb ldr r3, [r7, #12] 800d0ec: 681b ldr r3, [r3, #0] 800d0ee: 681a ldr r2, [r3, #0] 800d0f0: 68fb ldr r3, [r7, #12] 800d0f2: 681b ldr r3, [r3, #0] 800d0f4: f022 0240 bic.w r2, r2, #64 @ 0x40 800d0f8: 601a str r2, [r3, #0] SPI_1LINE_TX(hspi); 800d0fa: 68fb ldr r3, [r7, #12] 800d0fc: 681b ldr r3, [r3, #0] 800d0fe: 681a ldr r2, [r3, #0] 800d100: 68fb ldr r3, [r7, #12] 800d102: 681b ldr r3, [r3, #0] 800d104: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800d108: 601a str r2, [r3, #0] SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 800d10a: 68fb ldr r3, [r7, #12] 800d10c: 681b ldr r3, [r3, #0] 800d10e: 681b ldr r3, [r3, #0] 800d110: f003 0340 and.w r3, r3, #64 @ 0x40 800d114: 2b40 cmp r3, #64 @ 0x40 800d116: d007 beq.n 800d128 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 800d118: 68fb ldr r3, [r7, #12] 800d11a: 681b ldr r3, [r3, #0] 800d11c: 681a ldr r2, [r3, #0] 800d11e: 68fb ldr r3, [r7, #12] 800d120: 681b ldr r3, [r3, #0] 800d122: f042 0240 orr.w r2, r2, #64 @ 0x40 800d126: 601a str r2, [r3, #0] } /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 800d128: 68fb ldr r3, [r7, #12] 800d12a: 68db ldr r3, [r3, #12] 800d12c: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800d130: d952 bls.n 800d1d8 { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800d132: 68fb ldr r3, [r7, #12] 800d134: 685b ldr r3, [r3, #4] 800d136: 2b00 cmp r3, #0 800d138: d002 beq.n 800d140 800d13a: 8b7b ldrh r3, [r7, #26] 800d13c: 2b01 cmp r3, #1 800d13e: d145 bne.n 800d1cc { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d140: 68fb ldr r3, [r7, #12] 800d142: 6b9b ldr r3, [r3, #56] @ 0x38 800d144: 881a ldrh r2, [r3, #0] 800d146: 68fb ldr r3, [r7, #12] 800d148: 681b ldr r3, [r3, #0] 800d14a: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d14c: 68fb ldr r3, [r7, #12] 800d14e: 6b9b ldr r3, [r3, #56] @ 0x38 800d150: 1c9a adds r2, r3, #2 800d152: 68fb ldr r3, [r7, #12] 800d154: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d156: 68fb ldr r3, [r7, #12] 800d158: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d15a: b29b uxth r3, r3 800d15c: 3b01 subs r3, #1 800d15e: b29a uxth r2, r3 800d160: 68fb ldr r3, [r7, #12] 800d162: 87da strh r2, [r3, #62] @ 0x3e } /* Transmit data in 16 Bit mode */ while (hspi->TxXferCount > 0U) 800d164: e032 b.n 800d1cc { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 800d166: 68fb ldr r3, [r7, #12] 800d168: 681b ldr r3, [r3, #0] 800d16a: 689b ldr r3, [r3, #8] 800d16c: f003 0302 and.w r3, r3, #2 800d170: 2b02 cmp r3, #2 800d172: d112 bne.n 800d19a { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d174: 68fb ldr r3, [r7, #12] 800d176: 6b9b ldr r3, [r3, #56] @ 0x38 800d178: 881a ldrh r2, [r3, #0] 800d17a: 68fb ldr r3, [r7, #12] 800d17c: 681b ldr r3, [r3, #0] 800d17e: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d180: 68fb ldr r3, [r7, #12] 800d182: 6b9b ldr r3, [r3, #56] @ 0x38 800d184: 1c9a adds r2, r3, #2 800d186: 68fb ldr r3, [r7, #12] 800d188: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d18a: 68fb ldr r3, [r7, #12] 800d18c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d18e: b29b uxth r3, r3 800d190: 3b01 subs r3, #1 800d192: b29a uxth r2, r3 800d194: 68fb ldr r3, [r7, #12] 800d196: 87da strh r2, [r3, #62] @ 0x3e 800d198: e018 b.n 800d1cc } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 800d19a: f7f9 fbd9 bl 8006950 800d19e: 4602 mov r2, r0 800d1a0: 69fb ldr r3, [r7, #28] 800d1a2: 1ad3 subs r3, r2, r3 800d1a4: 683a ldr r2, [r7, #0] 800d1a6: 429a cmp r2, r3 800d1a8: d803 bhi.n 800d1b2 800d1aa: 683b ldr r3, [r7, #0] 800d1ac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d1b0: d102 bne.n 800d1b8 800d1b2: 683b ldr r3, [r7, #0] 800d1b4: 2b00 cmp r3, #0 800d1b6: d109 bne.n 800d1cc { hspi->State = HAL_SPI_STATE_READY; 800d1b8: 68fb ldr r3, [r7, #12] 800d1ba: 2201 movs r2, #1 800d1bc: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 800d1c0: 68fb ldr r3, [r7, #12] 800d1c2: 2200 movs r2, #0 800d1c4: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800d1c8: 2303 movs r3, #3 800d1ca: e0b2 b.n 800d332 while (hspi->TxXferCount > 0U) 800d1cc: 68fb ldr r3, [r7, #12] 800d1ce: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d1d0: b29b uxth r3, r3 800d1d2: 2b00 cmp r3, #0 800d1d4: d1c7 bne.n 800d166 800d1d6: e083 b.n 800d2e0 } } /* Transmit data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800d1d8: 68fb ldr r3, [r7, #12] 800d1da: 685b ldr r3, [r3, #4] 800d1dc: 2b00 cmp r3, #0 800d1de: d002 beq.n 800d1e6 800d1e0: 8b7b ldrh r3, [r7, #26] 800d1e2: 2b01 cmp r3, #1 800d1e4: d177 bne.n 800d2d6 { if (hspi->TxXferCount > 1U) 800d1e6: 68fb ldr r3, [r7, #12] 800d1e8: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d1ea: b29b uxth r3, r3 800d1ec: 2b01 cmp r3, #1 800d1ee: d912 bls.n 800d216 { /* write on the data register in packing mode */ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d1f0: 68fb ldr r3, [r7, #12] 800d1f2: 6b9b ldr r3, [r3, #56] @ 0x38 800d1f4: 881a ldrh r2, [r3, #0] 800d1f6: 68fb ldr r3, [r7, #12] 800d1f8: 681b ldr r3, [r3, #0] 800d1fa: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d1fc: 68fb ldr r3, [r7, #12] 800d1fe: 6b9b ldr r3, [r3, #56] @ 0x38 800d200: 1c9a adds r2, r3, #2 800d202: 68fb ldr r3, [r7, #12] 800d204: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 800d206: 68fb ldr r3, [r7, #12] 800d208: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d20a: b29b uxth r3, r3 800d20c: 3b02 subs r3, #2 800d20e: b29a uxth r2, r3 800d210: 68fb ldr r3, [r7, #12] 800d212: 87da strh r2, [r3, #62] @ 0x3e 800d214: e05f b.n 800d2d6 } else { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 800d216: 68fb ldr r3, [r7, #12] 800d218: 6b9a ldr r2, [r3, #56] @ 0x38 800d21a: 68fb ldr r3, [r7, #12] 800d21c: 681b ldr r3, [r3, #0] 800d21e: 330c adds r3, #12 800d220: 7812 ldrb r2, [r2, #0] 800d222: 701a strb r2, [r3, #0] hspi->pTxBuffPtr ++; 800d224: 68fb ldr r3, [r7, #12] 800d226: 6b9b ldr r3, [r3, #56] @ 0x38 800d228: 1c5a adds r2, r3, #1 800d22a: 68fb ldr r3, [r7, #12] 800d22c: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d22e: 68fb ldr r3, [r7, #12] 800d230: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d232: b29b uxth r3, r3 800d234: 3b01 subs r3, #1 800d236: b29a uxth r2, r3 800d238: 68fb ldr r3, [r7, #12] 800d23a: 87da strh r2, [r3, #62] @ 0x3e } } while (hspi->TxXferCount > 0U) 800d23c: e04b b.n 800d2d6 { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 800d23e: 68fb ldr r3, [r7, #12] 800d240: 681b ldr r3, [r3, #0] 800d242: 689b ldr r3, [r3, #8] 800d244: f003 0302 and.w r3, r3, #2 800d248: 2b02 cmp r3, #2 800d24a: d12b bne.n 800d2a4 { if (hspi->TxXferCount > 1U) 800d24c: 68fb ldr r3, [r7, #12] 800d24e: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d250: b29b uxth r3, r3 800d252: 2b01 cmp r3, #1 800d254: d912 bls.n 800d27c { /* write on the data register in packing mode */ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d256: 68fb ldr r3, [r7, #12] 800d258: 6b9b ldr r3, [r3, #56] @ 0x38 800d25a: 881a ldrh r2, [r3, #0] 800d25c: 68fb ldr r3, [r7, #12] 800d25e: 681b ldr r3, [r3, #0] 800d260: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d262: 68fb ldr r3, [r7, #12] 800d264: 6b9b ldr r3, [r3, #56] @ 0x38 800d266: 1c9a adds r2, r3, #2 800d268: 68fb ldr r3, [r7, #12] 800d26a: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 800d26c: 68fb ldr r3, [r7, #12] 800d26e: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d270: b29b uxth r3, r3 800d272: 3b02 subs r3, #2 800d274: b29a uxth r2, r3 800d276: 68fb ldr r3, [r7, #12] 800d278: 87da strh r2, [r3, #62] @ 0x3e 800d27a: e02c b.n 800d2d6 } else { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 800d27c: 68fb ldr r3, [r7, #12] 800d27e: 6b9a ldr r2, [r3, #56] @ 0x38 800d280: 68fb ldr r3, [r7, #12] 800d282: 681b ldr r3, [r3, #0] 800d284: 330c adds r3, #12 800d286: 7812 ldrb r2, [r2, #0] 800d288: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 800d28a: 68fb ldr r3, [r7, #12] 800d28c: 6b9b ldr r3, [r3, #56] @ 0x38 800d28e: 1c5a adds r2, r3, #1 800d290: 68fb ldr r3, [r7, #12] 800d292: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d294: 68fb ldr r3, [r7, #12] 800d296: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d298: b29b uxth r3, r3 800d29a: 3b01 subs r3, #1 800d29c: b29a uxth r2, r3 800d29e: 68fb ldr r3, [r7, #12] 800d2a0: 87da strh r2, [r3, #62] @ 0x3e 800d2a2: e018 b.n 800d2d6 } } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 800d2a4: f7f9 fb54 bl 8006950 800d2a8: 4602 mov r2, r0 800d2aa: 69fb ldr r3, [r7, #28] 800d2ac: 1ad3 subs r3, r2, r3 800d2ae: 683a ldr r2, [r7, #0] 800d2b0: 429a cmp r2, r3 800d2b2: d803 bhi.n 800d2bc 800d2b4: 683b ldr r3, [r7, #0] 800d2b6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d2ba: d102 bne.n 800d2c2 800d2bc: 683b ldr r3, [r7, #0] 800d2be: 2b00 cmp r3, #0 800d2c0: d109 bne.n 800d2d6 { hspi->State = HAL_SPI_STATE_READY; 800d2c2: 68fb ldr r3, [r7, #12] 800d2c4: 2201 movs r2, #1 800d2c6: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 800d2ca: 68fb ldr r3, [r7, #12] 800d2cc: 2200 movs r2, #0 800d2ce: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800d2d2: 2303 movs r3, #3 800d2d4: e02d b.n 800d332 while (hspi->TxXferCount > 0U) 800d2d6: 68fb ldr r3, [r7, #12] 800d2d8: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d2da: b29b uxth r3, r3 800d2dc: 2b00 cmp r3, #0 800d2de: d1ae bne.n 800d23e SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 800d2e0: 69fa ldr r2, [r7, #28] 800d2e2: 6839 ldr r1, [r7, #0] 800d2e4: 68f8 ldr r0, [r7, #12] 800d2e6: f000 ff63 bl 800e1b0 800d2ea: 4603 mov r3, r0 800d2ec: 2b00 cmp r3, #0 800d2ee: d002 beq.n 800d2f6 { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 800d2f0: 68fb ldr r3, [r7, #12] 800d2f2: 2220 movs r2, #32 800d2f4: 661a str r2, [r3, #96] @ 0x60 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 800d2f6: 68fb ldr r3, [r7, #12] 800d2f8: 689b ldr r3, [r3, #8] 800d2fa: 2b00 cmp r3, #0 800d2fc: d10a bne.n 800d314 { __HAL_SPI_CLEAR_OVRFLAG(hspi); 800d2fe: 2300 movs r3, #0 800d300: 617b str r3, [r7, #20] 800d302: 68fb ldr r3, [r7, #12] 800d304: 681b ldr r3, [r3, #0] 800d306: 68db ldr r3, [r3, #12] 800d308: 617b str r3, [r7, #20] 800d30a: 68fb ldr r3, [r7, #12] 800d30c: 681b ldr r3, [r3, #0] 800d30e: 689b ldr r3, [r3, #8] 800d310: 617b str r3, [r7, #20] 800d312: 697b ldr r3, [r7, #20] } hspi->State = HAL_SPI_STATE_READY; 800d314: 68fb ldr r3, [r7, #12] 800d316: 2201 movs r2, #1 800d318: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 800d31c: 68fb ldr r3, [r7, #12] 800d31e: 2200 movs r2, #0 800d320: f883 205c strb.w r2, [r3, #92] @ 0x5c if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800d324: 68fb ldr r3, [r7, #12] 800d326: 6e1b ldr r3, [r3, #96] @ 0x60 800d328: 2b00 cmp r3, #0 800d32a: d001 beq.n 800d330 { return HAL_ERROR; 800d32c: 2301 movs r3, #1 800d32e: e000 b.n 800d332 } else { return HAL_OK; 800d330: 2300 movs r3, #0 } } 800d332: 4618 mov r0, r3 800d334: 3720 adds r7, #32 800d336: 46bd mov sp, r7 800d338: bd80 pop {r7, pc} 0800d33a : * @param Timeout Timeout duration in ms * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { 800d33a: b580 push {r7, lr} 800d33c: b08a sub sp, #40 @ 0x28 800d33e: af00 add r7, sp, #0 800d340: 60f8 str r0, [r7, #12] 800d342: 60b9 str r1, [r7, #8] 800d344: 607a str r2, [r7, #4] 800d346: 807b strh r3, [r7, #2] __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; 800d348: 2301 movs r3, #1 800d34a: 627b str r3, [r7, #36] @ 0x24 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800d34c: f7f9 fb00 bl 8006950 800d350: 6238 str r0, [r7, #32] /* Init temporary variables */ tmp_state = hspi->State; 800d352: 68fb ldr r3, [r7, #12] 800d354: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d358: 77fb strb r3, [r7, #31] tmp_mode = hspi->Init.Mode; 800d35a: 68fb ldr r3, [r7, #12] 800d35c: 685b ldr r3, [r3, #4] 800d35e: 61bb str r3, [r7, #24] initial_TxXferCount = Size; 800d360: 887b ldrh r3, [r7, #2] 800d362: 82fb strh r3, [r7, #22] initial_RxXferCount = Size; 800d364: 887b ldrh r3, [r7, #2] 800d366: 82bb strh r3, [r7, #20] #if (USE_SPI_CRC != 0U) spi_cr1 = READ_REG(hspi->Instance->CR1); spi_cr2 = READ_REG(hspi->Instance->CR2); #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ 800d368: 7ffb ldrb r3, [r7, #31] 800d36a: 2b01 cmp r3, #1 800d36c: d00c beq.n 800d388 800d36e: 69bb ldr r3, [r7, #24] 800d370: f5b3 7f82 cmp.w r3, #260 @ 0x104 800d374: d106 bne.n 800d384 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && 800d376: 68fb ldr r3, [r7, #12] 800d378: 689b ldr r3, [r3, #8] 800d37a: 2b00 cmp r3, #0 800d37c: d102 bne.n 800d384 800d37e: 7ffb ldrb r3, [r7, #31] 800d380: 2b04 cmp r3, #4 800d382: d001 beq.n 800d388 (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; 800d384: 2302 movs r3, #2 800d386: e1f3 b.n 800d770 } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 800d388: 68bb ldr r3, [r7, #8] 800d38a: 2b00 cmp r3, #0 800d38c: d005 beq.n 800d39a 800d38e: 687b ldr r3, [r7, #4] 800d390: 2b00 cmp r3, #0 800d392: d002 beq.n 800d39a 800d394: 887b ldrh r3, [r7, #2] 800d396: 2b00 cmp r3, #0 800d398: d101 bne.n 800d39e { return HAL_ERROR; 800d39a: 2301 movs r3, #1 800d39c: e1e8 b.n 800d770 } /* Process Locked */ __HAL_LOCK(hspi); 800d39e: 68fb ldr r3, [r7, #12] 800d3a0: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 800d3a4: 2b01 cmp r3, #1 800d3a6: d101 bne.n 800d3ac 800d3a8: 2302 movs r3, #2 800d3aa: e1e1 b.n 800d770 800d3ac: 68fb ldr r3, [r7, #12] 800d3ae: 2201 movs r2, #1 800d3b0: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 800d3b4: 68fb ldr r3, [r7, #12] 800d3b6: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d3ba: b2db uxtb r3, r3 800d3bc: 2b04 cmp r3, #4 800d3be: d003 beq.n 800d3c8 { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 800d3c0: 68fb ldr r3, [r7, #12] 800d3c2: 2205 movs r2, #5 800d3c4: f883 205d strb.w r2, [r3, #93] @ 0x5d } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800d3c8: 68fb ldr r3, [r7, #12] 800d3ca: 2200 movs r2, #0 800d3cc: 661a str r2, [r3, #96] @ 0x60 hspi->pRxBuffPtr = (uint8_t *)pRxData; 800d3ce: 68fb ldr r3, [r7, #12] 800d3d0: 687a ldr r2, [r7, #4] 800d3d2: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount = Size; 800d3d4: 68fb ldr r3, [r7, #12] 800d3d6: 887a ldrh r2, [r7, #2] 800d3d8: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->RxXferSize = Size; 800d3dc: 68fb ldr r3, [r7, #12] 800d3de: 887a ldrh r2, [r7, #2] 800d3e0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hspi->pTxBuffPtr = (const uint8_t *)pTxData; 800d3e4: 68fb ldr r3, [r7, #12] 800d3e6: 68ba ldr r2, [r7, #8] 800d3e8: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount = Size; 800d3ea: 68fb ldr r3, [r7, #12] 800d3ec: 887a ldrh r2, [r7, #2] 800d3ee: 87da strh r2, [r3, #62] @ 0x3e hspi->TxXferSize = Size; 800d3f0: 68fb ldr r3, [r7, #12] 800d3f2: 887a ldrh r2, [r7, #2] 800d3f4: 879a strh r2, [r3, #60] @ 0x3c /*Init field not used in handle to zero */ hspi->RxISR = NULL; 800d3f6: 68fb ldr r3, [r7, #12] 800d3f8: 2200 movs r2, #0 800d3fa: 64da str r2, [r3, #76] @ 0x4c hspi->TxISR = NULL; 800d3fc: 68fb ldr r3, [r7, #12] 800d3fe: 2200 movs r2, #0 800d400: 651a str r2, [r3, #80] @ 0x50 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) 800d402: 68fb ldr r3, [r7, #12] 800d404: 68db ldr r3, [r3, #12] 800d406: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800d40a: d802 bhi.n 800d412 800d40c: 8abb ldrh r3, [r7, #20] 800d40e: 2b01 cmp r3, #1 800d410: d908 bls.n 800d424 { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d412: 68fb ldr r3, [r7, #12] 800d414: 681b ldr r3, [r3, #0] 800d416: 685a ldr r2, [r3, #4] 800d418: 68fb ldr r3, [r7, #12] 800d41a: 681b ldr r3, [r3, #0] 800d41c: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800d420: 605a str r2, [r3, #4] 800d422: e007 b.n 800d434 } else { /* Set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d424: 68fb ldr r3, [r7, #12] 800d426: 681b ldr r3, [r3, #0] 800d428: 685a ldr r2, [r3, #4] 800d42a: 68fb ldr r3, [r7, #12] 800d42c: 681b ldr r3, [r3, #0] 800d42e: f442 5280 orr.w r2, r2, #4096 @ 0x1000 800d432: 605a str r2, [r3, #4] } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 800d434: 68fb ldr r3, [r7, #12] 800d436: 681b ldr r3, [r3, #0] 800d438: 681b ldr r3, [r3, #0] 800d43a: f003 0340 and.w r3, r3, #64 @ 0x40 800d43e: 2b40 cmp r3, #64 @ 0x40 800d440: d007 beq.n 800d452 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 800d442: 68fb ldr r3, [r7, #12] 800d444: 681b ldr r3, [r3, #0] 800d446: 681a ldr r2, [r3, #0] 800d448: 68fb ldr r3, [r7, #12] 800d44a: 681b ldr r3, [r3, #0] 800d44c: f042 0240 orr.w r2, r2, #64 @ 0x40 800d450: 601a str r2, [r3, #0] } /* Transmit and Receive data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 800d452: 68fb ldr r3, [r7, #12] 800d454: 68db ldr r3, [r3, #12] 800d456: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800d45a: f240 8083 bls.w 800d564 { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800d45e: 68fb ldr r3, [r7, #12] 800d460: 685b ldr r3, [r3, #4] 800d462: 2b00 cmp r3, #0 800d464: d002 beq.n 800d46c 800d466: 8afb ldrh r3, [r7, #22] 800d468: 2b01 cmp r3, #1 800d46a: d16f bne.n 800d54c { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d46c: 68fb ldr r3, [r7, #12] 800d46e: 6b9b ldr r3, [r3, #56] @ 0x38 800d470: 881a ldrh r2, [r3, #0] 800d472: 68fb ldr r3, [r7, #12] 800d474: 681b ldr r3, [r3, #0] 800d476: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d478: 68fb ldr r3, [r7, #12] 800d47a: 6b9b ldr r3, [r3, #56] @ 0x38 800d47c: 1c9a adds r2, r3, #2 800d47e: 68fb ldr r3, [r7, #12] 800d480: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d482: 68fb ldr r3, [r7, #12] 800d484: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d486: b29b uxth r3, r3 800d488: 3b01 subs r3, #1 800d48a: b29a uxth r2, r3 800d48c: 68fb ldr r3, [r7, #12] 800d48e: 87da strh r2, [r3, #62] @ 0x3e SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 800d490: e05c b.n 800d54c { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 800d492: 68fb ldr r3, [r7, #12] 800d494: 681b ldr r3, [r3, #0] 800d496: 689b ldr r3, [r3, #8] 800d498: f003 0302 and.w r3, r3, #2 800d49c: 2b02 cmp r3, #2 800d49e: d11b bne.n 800d4d8 800d4a0: 68fb ldr r3, [r7, #12] 800d4a2: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d4a4: b29b uxth r3, r3 800d4a6: 2b00 cmp r3, #0 800d4a8: d016 beq.n 800d4d8 800d4aa: 6a7b ldr r3, [r7, #36] @ 0x24 800d4ac: 2b01 cmp r3, #1 800d4ae: d113 bne.n 800d4d8 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d4b0: 68fb ldr r3, [r7, #12] 800d4b2: 6b9b ldr r3, [r3, #56] @ 0x38 800d4b4: 881a ldrh r2, [r3, #0] 800d4b6: 68fb ldr r3, [r7, #12] 800d4b8: 681b ldr r3, [r3, #0] 800d4ba: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d4bc: 68fb ldr r3, [r7, #12] 800d4be: 6b9b ldr r3, [r3, #56] @ 0x38 800d4c0: 1c9a adds r2, r3, #2 800d4c2: 68fb ldr r3, [r7, #12] 800d4c4: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d4c6: 68fb ldr r3, [r7, #12] 800d4c8: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d4ca: b29b uxth r3, r3 800d4cc: 3b01 subs r3, #1 800d4ce: b29a uxth r2, r3 800d4d0: 68fb ldr r3, [r7, #12] 800d4d2: 87da strh r2, [r3, #62] @ 0x3e /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 800d4d4: 2300 movs r3, #0 800d4d6: 627b str r3, [r7, #36] @ 0x24 } #endif /* USE_SPI_CRC */ } /* Check RXNE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 800d4d8: 68fb ldr r3, [r7, #12] 800d4da: 681b ldr r3, [r3, #0] 800d4dc: 689b ldr r3, [r3, #8] 800d4de: f003 0301 and.w r3, r3, #1 800d4e2: 2b01 cmp r3, #1 800d4e4: d11c bne.n 800d520 800d4e6: 68fb ldr r3, [r7, #12] 800d4e8: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d4ec: b29b uxth r3, r3 800d4ee: 2b00 cmp r3, #0 800d4f0: d016 beq.n 800d520 { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 800d4f2: 68fb ldr r3, [r7, #12] 800d4f4: 681b ldr r3, [r3, #0] 800d4f6: 68da ldr r2, [r3, #12] 800d4f8: 68fb ldr r3, [r7, #12] 800d4fa: 6c1b ldr r3, [r3, #64] @ 0x40 800d4fc: b292 uxth r2, r2 800d4fe: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 800d500: 68fb ldr r3, [r7, #12] 800d502: 6c1b ldr r3, [r3, #64] @ 0x40 800d504: 1c9a adds r2, r3, #2 800d506: 68fb ldr r3, [r7, #12] 800d508: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount--; 800d50a: 68fb ldr r3, [r7, #12] 800d50c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d510: b29b uxth r3, r3 800d512: 3b01 subs r3, #1 800d514: b29a uxth r2, r3 800d516: 68fb ldr r3, [r7, #12] 800d518: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 800d51c: 2301 movs r3, #1 800d51e: 627b str r3, [r7, #36] @ 0x24 } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) 800d520: f7f9 fa16 bl 8006950 800d524: 4602 mov r2, r0 800d526: 6a3b ldr r3, [r7, #32] 800d528: 1ad3 subs r3, r2, r3 800d52a: 6b3a ldr r2, [r7, #48] @ 0x30 800d52c: 429a cmp r2, r3 800d52e: d80d bhi.n 800d54c 800d530: 6b3b ldr r3, [r7, #48] @ 0x30 800d532: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d536: d009 beq.n 800d54c { hspi->State = HAL_SPI_STATE_READY; 800d538: 68fb ldr r3, [r7, #12] 800d53a: 2201 movs r2, #1 800d53c: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 800d540: 68fb ldr r3, [r7, #12] 800d542: 2200 movs r2, #0 800d544: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800d548: 2303 movs r3, #3 800d54a: e111 b.n 800d770 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 800d54c: 68fb ldr r3, [r7, #12] 800d54e: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d550: b29b uxth r3, r3 800d552: 2b00 cmp r3, #0 800d554: d19d bne.n 800d492 800d556: 68fb ldr r3, [r7, #12] 800d558: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d55c: b29b uxth r3, r3 800d55e: 2b00 cmp r3, #0 800d560: d197 bne.n 800d492 800d562: e0e5 b.n 800d730 } } /* Transmit and Receive data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 800d564: 68fb ldr r3, [r7, #12] 800d566: 685b ldr r3, [r3, #4] 800d568: 2b00 cmp r3, #0 800d56a: d003 beq.n 800d574 800d56c: 8afb ldrh r3, [r7, #22] 800d56e: 2b01 cmp r3, #1 800d570: f040 80d1 bne.w 800d716 { if (hspi->TxXferCount > 1U) 800d574: 68fb ldr r3, [r7, #12] 800d576: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d578: b29b uxth r3, r3 800d57a: 2b01 cmp r3, #1 800d57c: d912 bls.n 800d5a4 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d57e: 68fb ldr r3, [r7, #12] 800d580: 6b9b ldr r3, [r3, #56] @ 0x38 800d582: 881a ldrh r2, [r3, #0] 800d584: 68fb ldr r3, [r7, #12] 800d586: 681b ldr r3, [r3, #0] 800d588: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d58a: 68fb ldr r3, [r7, #12] 800d58c: 6b9b ldr r3, [r3, #56] @ 0x38 800d58e: 1c9a adds r2, r3, #2 800d590: 68fb ldr r3, [r7, #12] 800d592: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 800d594: 68fb ldr r3, [r7, #12] 800d596: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d598: b29b uxth r3, r3 800d59a: 3b02 subs r3, #2 800d59c: b29a uxth r2, r3 800d59e: 68fb ldr r3, [r7, #12] 800d5a0: 87da strh r2, [r3, #62] @ 0x3e 800d5a2: e0b8 b.n 800d716 } else { *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); 800d5a4: 68fb ldr r3, [r7, #12] 800d5a6: 6b9a ldr r2, [r3, #56] @ 0x38 800d5a8: 68fb ldr r3, [r7, #12] 800d5aa: 681b ldr r3, [r3, #0] 800d5ac: 330c adds r3, #12 800d5ae: 7812 ldrb r2, [r2, #0] 800d5b0: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 800d5b2: 68fb ldr r3, [r7, #12] 800d5b4: 6b9b ldr r3, [r3, #56] @ 0x38 800d5b6: 1c5a adds r2, r3, #1 800d5b8: 68fb ldr r3, [r7, #12] 800d5ba: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d5bc: 68fb ldr r3, [r7, #12] 800d5be: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d5c0: b29b uxth r3, r3 800d5c2: 3b01 subs r3, #1 800d5c4: b29a uxth r2, r3 800d5c6: 68fb ldr r3, [r7, #12] 800d5c8: 87da strh r2, [r3, #62] @ 0x3e SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ } } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 800d5ca: e0a4 b.n 800d716 { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 800d5cc: 68fb ldr r3, [r7, #12] 800d5ce: 681b ldr r3, [r3, #0] 800d5d0: 689b ldr r3, [r3, #8] 800d5d2: f003 0302 and.w r3, r3, #2 800d5d6: 2b02 cmp r3, #2 800d5d8: d134 bne.n 800d644 800d5da: 68fb ldr r3, [r7, #12] 800d5dc: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d5de: b29b uxth r3, r3 800d5e0: 2b00 cmp r3, #0 800d5e2: d02f beq.n 800d644 800d5e4: 6a7b ldr r3, [r7, #36] @ 0x24 800d5e6: 2b01 cmp r3, #1 800d5e8: d12c bne.n 800d644 { if (hspi->TxXferCount > 1U) 800d5ea: 68fb ldr r3, [r7, #12] 800d5ec: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d5ee: b29b uxth r3, r3 800d5f0: 2b01 cmp r3, #1 800d5f2: d912 bls.n 800d61a { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 800d5f4: 68fb ldr r3, [r7, #12] 800d5f6: 6b9b ldr r3, [r3, #56] @ 0x38 800d5f8: 881a ldrh r2, [r3, #0] 800d5fa: 68fb ldr r3, [r7, #12] 800d5fc: 681b ldr r3, [r3, #0] 800d5fe: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 800d600: 68fb ldr r3, [r7, #12] 800d602: 6b9b ldr r3, [r3, #56] @ 0x38 800d604: 1c9a adds r2, r3, #2 800d606: 68fb ldr r3, [r7, #12] 800d608: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 800d60a: 68fb ldr r3, [r7, #12] 800d60c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d60e: b29b uxth r3, r3 800d610: 3b02 subs r3, #2 800d612: b29a uxth r2, r3 800d614: 68fb ldr r3, [r7, #12] 800d616: 87da strh r2, [r3, #62] @ 0x3e 800d618: e012 b.n 800d640 } else { *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); 800d61a: 68fb ldr r3, [r7, #12] 800d61c: 6b9a ldr r2, [r3, #56] @ 0x38 800d61e: 68fb ldr r3, [r7, #12] 800d620: 681b ldr r3, [r3, #0] 800d622: 330c adds r3, #12 800d624: 7812 ldrb r2, [r2, #0] 800d626: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 800d628: 68fb ldr r3, [r7, #12] 800d62a: 6b9b ldr r3, [r3, #56] @ 0x38 800d62c: 1c5a adds r2, r3, #1 800d62e: 68fb ldr r3, [r7, #12] 800d630: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800d632: 68fb ldr r3, [r7, #12] 800d634: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d636: b29b uxth r3, r3 800d638: 3b01 subs r3, #1 800d63a: b29a uxth r2, r3 800d63c: 68fb ldr r3, [r7, #12] 800d63e: 87da strh r2, [r3, #62] @ 0x3e } /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 800d640: 2300 movs r3, #0 800d642: 627b str r3, [r7, #36] @ 0x24 } #endif /* USE_SPI_CRC */ } /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 800d644: 68fb ldr r3, [r7, #12] 800d646: 681b ldr r3, [r3, #0] 800d648: 689b ldr r3, [r3, #8] 800d64a: f003 0301 and.w r3, r3, #1 800d64e: 2b01 cmp r3, #1 800d650: d148 bne.n 800d6e4 800d652: 68fb ldr r3, [r7, #12] 800d654: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d658: b29b uxth r3, r3 800d65a: 2b00 cmp r3, #0 800d65c: d042 beq.n 800d6e4 { if (hspi->RxXferCount > 1U) 800d65e: 68fb ldr r3, [r7, #12] 800d660: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d664: b29b uxth r3, r3 800d666: 2b01 cmp r3, #1 800d668: d923 bls.n 800d6b2 { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 800d66a: 68fb ldr r3, [r7, #12] 800d66c: 681b ldr r3, [r3, #0] 800d66e: 68da ldr r2, [r3, #12] 800d670: 68fb ldr r3, [r7, #12] 800d672: 6c1b ldr r3, [r3, #64] @ 0x40 800d674: b292 uxth r2, r2 800d676: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 800d678: 68fb ldr r3, [r7, #12] 800d67a: 6c1b ldr r3, [r3, #64] @ 0x40 800d67c: 1c9a adds r2, r3, #2 800d67e: 68fb ldr r3, [r7, #12] 800d680: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount -= 2U; 800d682: 68fb ldr r3, [r7, #12] 800d684: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d688: b29b uxth r3, r3 800d68a: 3b02 subs r3, #2 800d68c: b29a uxth r2, r3 800d68e: 68fb ldr r3, [r7, #12] 800d690: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 if (hspi->RxXferCount <= 1U) 800d694: 68fb ldr r3, [r7, #12] 800d696: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d69a: b29b uxth r3, r3 800d69c: 2b01 cmp r3, #1 800d69e: d81f bhi.n 800d6e0 { /* Set RX Fifo threshold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d6a0: 68fb ldr r3, [r7, #12] 800d6a2: 681b ldr r3, [r3, #0] 800d6a4: 685a ldr r2, [r3, #4] 800d6a6: 68fb ldr r3, [r7, #12] 800d6a8: 681b ldr r3, [r3, #0] 800d6aa: f442 5280 orr.w r2, r2, #4096 @ 0x1000 800d6ae: 605a str r2, [r3, #4] 800d6b0: e016 b.n 800d6e0 } } else { (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; 800d6b2: 68fb ldr r3, [r7, #12] 800d6b4: 681b ldr r3, [r3, #0] 800d6b6: f103 020c add.w r2, r3, #12 800d6ba: 68fb ldr r3, [r7, #12] 800d6bc: 6c1b ldr r3, [r3, #64] @ 0x40 800d6be: 7812 ldrb r2, [r2, #0] 800d6c0: b2d2 uxtb r2, r2 800d6c2: 701a strb r2, [r3, #0] hspi->pRxBuffPtr++; 800d6c4: 68fb ldr r3, [r7, #12] 800d6c6: 6c1b ldr r3, [r3, #64] @ 0x40 800d6c8: 1c5a adds r2, r3, #1 800d6ca: 68fb ldr r3, [r7, #12] 800d6cc: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount--; 800d6ce: 68fb ldr r3, [r7, #12] 800d6d0: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d6d4: b29b uxth r3, r3 800d6d6: 3b01 subs r3, #1 800d6d8: b29a uxth r2, r3 800d6da: 68fb ldr r3, [r7, #12] 800d6dc: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 } /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 800d6e0: 2301 movs r3, #1 800d6e2: 627b str r3, [r7, #36] @ 0x24 } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) 800d6e4: f7f9 f934 bl 8006950 800d6e8: 4602 mov r2, r0 800d6ea: 6a3b ldr r3, [r7, #32] 800d6ec: 1ad3 subs r3, r2, r3 800d6ee: 6b3a ldr r2, [r7, #48] @ 0x30 800d6f0: 429a cmp r2, r3 800d6f2: d803 bhi.n 800d6fc 800d6f4: 6b3b ldr r3, [r7, #48] @ 0x30 800d6f6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d6fa: d102 bne.n 800d702 800d6fc: 6b3b ldr r3, [r7, #48] @ 0x30 800d6fe: 2b00 cmp r3, #0 800d700: d109 bne.n 800d716 { hspi->State = HAL_SPI_STATE_READY; 800d702: 68fb ldr r3, [r7, #12] 800d704: 2201 movs r2, #1 800d706: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 800d70a: 68fb ldr r3, [r7, #12] 800d70c: 2200 movs r2, #0 800d70e: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800d712: 2303 movs r3, #3 800d714: e02c b.n 800d770 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 800d716: 68fb ldr r3, [r7, #12] 800d718: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d71a: b29b uxth r3, r3 800d71c: 2b00 cmp r3, #0 800d71e: f47f af55 bne.w 800d5cc 800d722: 68fb ldr r3, [r7, #12] 800d724: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d728: b29b uxth r3, r3 800d72a: 2b00 cmp r3, #0 800d72c: f47f af4e bne.w 800d5cc return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 800d730: 6a3a ldr r2, [r7, #32] 800d732: 6b39 ldr r1, [r7, #48] @ 0x30 800d734: 68f8 ldr r0, [r7, #12] 800d736: f000 fd3b bl 800e1b0 800d73a: 4603 mov r3, r0 800d73c: 2b00 cmp r3, #0 800d73e: d008 beq.n 800d752 { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 800d740: 68fb ldr r3, [r7, #12] 800d742: 2220 movs r2, #32 800d744: 661a str r2, [r3, #96] @ 0x60 __HAL_UNLOCK(hspi); 800d746: 68fb ldr r3, [r7, #12] 800d748: 2200 movs r2, #0 800d74a: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_ERROR; 800d74e: 2301 movs r3, #1 800d750: e00e b.n 800d770 } hspi->State = HAL_SPI_STATE_READY; 800d752: 68fb ldr r3, [r7, #12] 800d754: 2201 movs r2, #1 800d756: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Unlock the process */ __HAL_UNLOCK(hspi); 800d75a: 68fb ldr r3, [r7, #12] 800d75c: 2200 movs r2, #0 800d75e: f883 205c strb.w r2, [r3, #92] @ 0x5c if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800d762: 68fb ldr r3, [r7, #12] 800d764: 6e1b ldr r3, [r3, #96] @ 0x60 800d766: 2b00 cmp r3, #0 800d768: d001 beq.n 800d76e { return HAL_ERROR; 800d76a: 2301 movs r3, #1 800d76c: e000 b.n 800d770 } else { return HAL_OK; 800d76e: 2300 movs r3, #0 } } 800d770: 4618 mov r0, r3 800d772: 3728 adds r7, #40 @ 0x28 800d774: 46bd mov sp, r7 800d776: bd80 pop {r7, pc} 0800d778 : * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { 800d778: b580 push {r7, lr} 800d77a: b086 sub sp, #24 800d77c: af00 add r7, sp, #0 800d77e: 60f8 str r0, [r7, #12] 800d780: 60b9 str r1, [r7, #8] 800d782: 607a str r2, [r7, #4] 800d784: 807b strh r3, [r7, #2] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Init temporary variables */ tmp_state = hspi->State; 800d786: 68fb ldr r3, [r7, #12] 800d788: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d78c: 75fb strb r3, [r7, #23] tmp_mode = hspi->Init.Mode; 800d78e: 68fb ldr r3, [r7, #12] 800d790: 685b ldr r3, [r3, #4] 800d792: 613b str r3, [r7, #16] if (!((tmp_state == HAL_SPI_STATE_READY) || 800d794: 7dfb ldrb r3, [r7, #23] 800d796: 2b01 cmp r3, #1 800d798: d00c beq.n 800d7b4 800d79a: 693b ldr r3, [r7, #16] 800d79c: f5b3 7f82 cmp.w r3, #260 @ 0x104 800d7a0: d106 bne.n 800d7b0 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && 800d7a2: 68fb ldr r3, [r7, #12] 800d7a4: 689b ldr r3, [r3, #8] 800d7a6: 2b00 cmp r3, #0 800d7a8: d102 bne.n 800d7b0 800d7aa: 7dfb ldrb r3, [r7, #23] 800d7ac: 2b04 cmp r3, #4 800d7ae: d001 beq.n 800d7b4 (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; 800d7b0: 2302 movs r3, #2 800d7b2: e158 b.n 800da66 } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 800d7b4: 68bb ldr r3, [r7, #8] 800d7b6: 2b00 cmp r3, #0 800d7b8: d005 beq.n 800d7c6 800d7ba: 687b ldr r3, [r7, #4] 800d7bc: 2b00 cmp r3, #0 800d7be: d002 beq.n 800d7c6 800d7c0: 887b ldrh r3, [r7, #2] 800d7c2: 2b00 cmp r3, #0 800d7c4: d101 bne.n 800d7ca { return HAL_ERROR; 800d7c6: 2301 movs r3, #1 800d7c8: e14d b.n 800da66 } /* Process locked */ __HAL_LOCK(hspi); 800d7ca: 68fb ldr r3, [r7, #12] 800d7cc: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 800d7d0: 2b01 cmp r3, #1 800d7d2: d101 bne.n 800d7d8 800d7d4: 2302 movs r3, #2 800d7d6: e146 b.n 800da66 800d7d8: 68fb ldr r3, [r7, #12] 800d7da: 2201 movs r2, #1 800d7dc: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 800d7e0: 68fb ldr r3, [r7, #12] 800d7e2: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d7e6: b2db uxtb r3, r3 800d7e8: 2b04 cmp r3, #4 800d7ea: d003 beq.n 800d7f4 { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 800d7ec: 68fb ldr r3, [r7, #12] 800d7ee: 2205 movs r2, #5 800d7f0: f883 205d strb.w r2, [r3, #93] @ 0x5d } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800d7f4: 68fb ldr r3, [r7, #12] 800d7f6: 2200 movs r2, #0 800d7f8: 661a str r2, [r3, #96] @ 0x60 hspi->pTxBuffPtr = (const uint8_t *)pTxData; 800d7fa: 68fb ldr r3, [r7, #12] 800d7fc: 68ba ldr r2, [r7, #8] 800d7fe: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferSize = Size; 800d800: 68fb ldr r3, [r7, #12] 800d802: 887a ldrh r2, [r7, #2] 800d804: 879a strh r2, [r3, #60] @ 0x3c hspi->TxXferCount = Size; 800d806: 68fb ldr r3, [r7, #12] 800d808: 887a ldrh r2, [r7, #2] 800d80a: 87da strh r2, [r3, #62] @ 0x3e hspi->pRxBuffPtr = (uint8_t *)pRxData; 800d80c: 68fb ldr r3, [r7, #12] 800d80e: 687a ldr r2, [r7, #4] 800d810: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferSize = Size; 800d812: 68fb ldr r3, [r7, #12] 800d814: 887a ldrh r2, [r7, #2] 800d816: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hspi->RxXferCount = Size; 800d81a: 68fb ldr r3, [r7, #12] 800d81c: 887a ldrh r2, [r7, #2] 800d81e: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 /* Init field not used in handle to zero */ hspi->RxISR = NULL; 800d822: 68fb ldr r3, [r7, #12] 800d824: 2200 movs r2, #0 800d826: 64da str r2, [r3, #76] @ 0x4c hspi->TxISR = NULL; 800d828: 68fb ldr r3, [r7, #12] 800d82a: 2200 movs r2, #0 800d82c: 651a str r2, [r3, #80] @ 0x50 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); 800d82e: 68fb ldr r3, [r7, #12] 800d830: 681b ldr r3, [r3, #0] 800d832: 685a ldr r2, [r3, #4] 800d834: 68fb ldr r3, [r7, #12] 800d836: 681b ldr r3, [r3, #0] 800d838: f422 42c0 bic.w r2, r2, #24576 @ 0x6000 800d83c: 605a str r2, [r3, #4] /* The packing mode management is enabled by the DMA settings according the spi data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 800d83e: 68fb ldr r3, [r7, #12] 800d840: 68db ldr r3, [r3, #12] 800d842: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 800d846: d908 bls.n 800d85a { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d848: 68fb ldr r3, [r7, #12] 800d84a: 681b ldr r3, [r3, #0] 800d84c: 685a ldr r2, [r3, #4] 800d84e: 68fb ldr r3, [r7, #12] 800d850: 681b ldr r3, [r3, #0] 800d852: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800d856: 605a str r2, [r3, #4] 800d858: e06f b.n 800d93a } else { /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d85a: 68fb ldr r3, [r7, #12] 800d85c: 681b ldr r3, [r3, #0] 800d85e: 685a ldr r2, [r3, #4] 800d860: 68fb ldr r3, [r7, #12] 800d862: 681b ldr r3, [r3, #0] 800d864: f442 5280 orr.w r2, r2, #4096 @ 0x1000 800d868: 605a str r2, [r3, #4] if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800d86a: 68fb ldr r3, [r7, #12] 800d86c: 6d5b ldr r3, [r3, #84] @ 0x54 800d86e: 699b ldr r3, [r3, #24] 800d870: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d874: d126 bne.n 800d8c4 { if ((hspi->TxXferSize & 0x1U) == 0x0U) 800d876: 68fb ldr r3, [r7, #12] 800d878: 8f9b ldrh r3, [r3, #60] @ 0x3c 800d87a: f003 0301 and.w r3, r3, #1 800d87e: 2b00 cmp r3, #0 800d880: d10f bne.n 800d8a2 { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); 800d882: 68fb ldr r3, [r7, #12] 800d884: 681b ldr r3, [r3, #0] 800d886: 685a ldr r2, [r3, #4] 800d888: 68fb ldr r3, [r7, #12] 800d88a: 681b ldr r3, [r3, #0] 800d88c: f422 4280 bic.w r2, r2, #16384 @ 0x4000 800d890: 605a str r2, [r3, #4] hspi->TxXferCount = hspi->TxXferCount >> 1U; 800d892: 68fb ldr r3, [r7, #12] 800d894: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d896: b29b uxth r3, r3 800d898: 085b lsrs r3, r3, #1 800d89a: b29a uxth r2, r3 800d89c: 68fb ldr r3, [r7, #12] 800d89e: 87da strh r2, [r3, #62] @ 0x3e 800d8a0: e010 b.n 800d8c4 } else { SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); 800d8a2: 68fb ldr r3, [r7, #12] 800d8a4: 681b ldr r3, [r3, #0] 800d8a6: 685a ldr r2, [r3, #4] 800d8a8: 68fb ldr r3, [r7, #12] 800d8aa: 681b ldr r3, [r3, #0] 800d8ac: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800d8b0: 605a str r2, [r3, #4] hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; 800d8b2: 68fb ldr r3, [r7, #12] 800d8b4: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d8b6: b29b uxth r3, r3 800d8b8: 085b lsrs r3, r3, #1 800d8ba: b29b uxth r3, r3 800d8bc: 3301 adds r3, #1 800d8be: b29a uxth r2, r3 800d8c0: 68fb ldr r3, [r7, #12] 800d8c2: 87da strh r2, [r3, #62] @ 0x3e } } if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800d8c4: 68fb ldr r3, [r7, #12] 800d8c6: 6d9b ldr r3, [r3, #88] @ 0x58 800d8c8: 699b ldr r3, [r3, #24] 800d8ca: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d8ce: d134 bne.n 800d93a { /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 800d8d0: 68fb ldr r3, [r7, #12] 800d8d2: 681b ldr r3, [r3, #0] 800d8d4: 685a ldr r2, [r3, #4] 800d8d6: 68fb ldr r3, [r7, #12] 800d8d8: 681b ldr r3, [r3, #0] 800d8da: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800d8de: 605a str r2, [r3, #4] if ((hspi->RxXferCount & 0x1U) == 0x0U) 800d8e0: 68fb ldr r3, [r7, #12] 800d8e2: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d8e6: b29b uxth r3, r3 800d8e8: f003 0301 and.w r3, r3, #1 800d8ec: 2b00 cmp r3, #0 800d8ee: d111 bne.n 800d914 { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); 800d8f0: 68fb ldr r3, [r7, #12] 800d8f2: 681b ldr r3, [r3, #0] 800d8f4: 685a ldr r2, [r3, #4] 800d8f6: 68fb ldr r3, [r7, #12] 800d8f8: 681b ldr r3, [r3, #0] 800d8fa: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800d8fe: 605a str r2, [r3, #4] hspi->RxXferCount = hspi->RxXferCount >> 1U; 800d900: 68fb ldr r3, [r7, #12] 800d902: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d906: b29b uxth r3, r3 800d908: 085b lsrs r3, r3, #1 800d90a: b29a uxth r2, r3 800d90c: 68fb ldr r3, [r7, #12] 800d90e: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 800d912: e012 b.n 800d93a } else { SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); 800d914: 68fb ldr r3, [r7, #12] 800d916: 681b ldr r3, [r3, #0] 800d918: 685a ldr r2, [r3, #4] 800d91a: 68fb ldr r3, [r7, #12] 800d91c: 681b ldr r3, [r3, #0] 800d91e: f442 5200 orr.w r2, r2, #8192 @ 0x2000 800d922: 605a str r2, [r3, #4] hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; 800d924: 68fb ldr r3, [r7, #12] 800d926: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d92a: b29b uxth r3, r3 800d92c: 085b lsrs r3, r3, #1 800d92e: b29b uxth r3, r3 800d930: 3301 adds r3, #1 800d932: b29a uxth r2, r3 800d934: 68fb ldr r3, [r7, #12] 800d936: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 } } } /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ if (hspi->State == HAL_SPI_STATE_BUSY_RX) 800d93a: 68fb ldr r3, [r7, #12] 800d93c: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800d940: b2db uxtb r3, r3 800d942: 2b04 cmp r3, #4 800d944: d108 bne.n 800d958 { /* Set the SPI Rx DMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; 800d946: 68fb ldr r3, [r7, #12] 800d948: 6d9b ldr r3, [r3, #88] @ 0x58 800d94a: 4a49 ldr r2, [pc, #292] @ (800da70 ) 800d94c: 631a str r2, [r3, #48] @ 0x30 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; 800d94e: 68fb ldr r3, [r7, #12] 800d950: 6d9b ldr r3, [r3, #88] @ 0x58 800d952: 4a48 ldr r2, [pc, #288] @ (800da74 ) 800d954: 62da str r2, [r3, #44] @ 0x2c 800d956: e007 b.n 800d968 } else { /* Set the SPI Tx/Rx DMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; 800d958: 68fb ldr r3, [r7, #12] 800d95a: 6d9b ldr r3, [r3, #88] @ 0x58 800d95c: 4a46 ldr r2, [pc, #280] @ (800da78 ) 800d95e: 631a str r2, [r3, #48] @ 0x30 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; 800d960: 68fb ldr r3, [r7, #12] 800d962: 6d9b ldr r3, [r3, #88] @ 0x58 800d964: 4a45 ldr r2, [pc, #276] @ (800da7c ) 800d966: 62da str r2, [r3, #44] @ 0x2c } /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; 800d968: 68fb ldr r3, [r7, #12] 800d96a: 6d9b ldr r3, [r3, #88] @ 0x58 800d96c: 4a44 ldr r2, [pc, #272] @ (800da80 ) 800d96e: 635a str r2, [r3, #52] @ 0x34 /* Set the DMA AbortCpltCallback */ hspi->hdmarx->XferAbortCallback = NULL; 800d970: 68fb ldr r3, [r7, #12] 800d972: 6d9b ldr r3, [r3, #88] @ 0x58 800d974: 2200 movs r2, #0 800d976: 639a str r2, [r3, #56] @ 0x38 /* Enable the Rx DMA Stream/Channel */ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, 800d978: 68fb ldr r3, [r7, #12] 800d97a: 6d98 ldr r0, [r3, #88] @ 0x58 800d97c: 68fb ldr r3, [r7, #12] 800d97e: 681b ldr r3, [r3, #0] 800d980: 330c adds r3, #12 800d982: 4619 mov r1, r3 800d984: 68fb ldr r3, [r7, #12] 800d986: 6c1b ldr r3, [r3, #64] @ 0x40 800d988: 461a mov r2, r3 hspi->RxXferCount)) 800d98a: 68fb ldr r3, [r7, #12] 800d98c: f8b3 3046 ldrh.w r3, [r3, #70] @ 0x46 800d990: b29b uxth r3, r3 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, 800d992: f7f9 fa07 bl 8006da4 800d996: 4603 mov r3, r0 800d998: 2b00 cmp r3, #0 800d99a: d00b beq.n 800d9b4 { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); 800d99c: 68fb ldr r3, [r7, #12] 800d99e: 6e1b ldr r3, [r3, #96] @ 0x60 800d9a0: f043 0210 orr.w r2, r3, #16 800d9a4: 68fb ldr r3, [r7, #12] 800d9a6: 661a str r2, [r3, #96] @ 0x60 /* Process Unlocked */ __HAL_UNLOCK(hspi); 800d9a8: 68fb ldr r3, [r7, #12] 800d9aa: 2200 movs r2, #0 800d9ac: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_ERROR; 800d9b0: 2301 movs r3, #1 800d9b2: e058 b.n 800da66 } /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); 800d9b4: 68fb ldr r3, [r7, #12] 800d9b6: 681b ldr r3, [r3, #0] 800d9b8: 685a ldr r2, [r3, #4] 800d9ba: 68fb ldr r3, [r7, #12] 800d9bc: 681b ldr r3, [r3, #0] 800d9be: f042 0201 orr.w r2, r2, #1 800d9c2: 605a str r2, [r3, #4] /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing is performed in DMA reception complete callback */ hspi->hdmatx->XferHalfCpltCallback = NULL; 800d9c4: 68fb ldr r3, [r7, #12] 800d9c6: 6d5b ldr r3, [r3, #84] @ 0x54 800d9c8: 2200 movs r2, #0 800d9ca: 631a str r2, [r3, #48] @ 0x30 hspi->hdmatx->XferCpltCallback = NULL; 800d9cc: 68fb ldr r3, [r7, #12] 800d9ce: 6d5b ldr r3, [r3, #84] @ 0x54 800d9d0: 2200 movs r2, #0 800d9d2: 62da str r2, [r3, #44] @ 0x2c hspi->hdmatx->XferErrorCallback = NULL; 800d9d4: 68fb ldr r3, [r7, #12] 800d9d6: 6d5b ldr r3, [r3, #84] @ 0x54 800d9d8: 2200 movs r2, #0 800d9da: 635a str r2, [r3, #52] @ 0x34 hspi->hdmatx->XferAbortCallback = NULL; 800d9dc: 68fb ldr r3, [r7, #12] 800d9de: 6d5b ldr r3, [r3, #84] @ 0x54 800d9e0: 2200 movs r2, #0 800d9e2: 639a str r2, [r3, #56] @ 0x38 /* Enable the Tx DMA Stream/Channel */ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, 800d9e4: 68fb ldr r3, [r7, #12] 800d9e6: 6d58 ldr r0, [r3, #84] @ 0x54 800d9e8: 68fb ldr r3, [r7, #12] 800d9ea: 6b9b ldr r3, [r3, #56] @ 0x38 800d9ec: 4619 mov r1, r3 800d9ee: 68fb ldr r3, [r7, #12] 800d9f0: 681b ldr r3, [r3, #0] 800d9f2: 330c adds r3, #12 800d9f4: 461a mov r2, r3 hspi->TxXferCount)) 800d9f6: 68fb ldr r3, [r7, #12] 800d9f8: 8fdb ldrh r3, [r3, #62] @ 0x3e 800d9fa: b29b uxth r3, r3 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, 800d9fc: f7f9 f9d2 bl 8006da4 800da00: 4603 mov r3, r0 800da02: 2b00 cmp r3, #0 800da04: d00b beq.n 800da1e { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); 800da06: 68fb ldr r3, [r7, #12] 800da08: 6e1b ldr r3, [r3, #96] @ 0x60 800da0a: f043 0210 orr.w r2, r3, #16 800da0e: 68fb ldr r3, [r7, #12] 800da10: 661a str r2, [r3, #96] @ 0x60 /* Process Unlocked */ __HAL_UNLOCK(hspi); 800da12: 68fb ldr r3, [r7, #12] 800da14: 2200 movs r2, #0 800da16: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_ERROR; 800da1a: 2301 movs r3, #1 800da1c: e023 b.n 800da66 } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 800da1e: 68fb ldr r3, [r7, #12] 800da20: 681b ldr r3, [r3, #0] 800da22: 681b ldr r3, [r3, #0] 800da24: f003 0340 and.w r3, r3, #64 @ 0x40 800da28: 2b40 cmp r3, #64 @ 0x40 800da2a: d007 beq.n 800da3c { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 800da2c: 68fb ldr r3, [r7, #12] 800da2e: 681b ldr r3, [r3, #0] 800da30: 681a ldr r2, [r3, #0] 800da32: 68fb ldr r3, [r7, #12] 800da34: 681b ldr r3, [r3, #0] 800da36: f042 0240 orr.w r2, r2, #64 @ 0x40 800da3a: 601a str r2, [r3, #0] } /* Process Unlocked */ __HAL_UNLOCK(hspi); 800da3c: 68fb ldr r3, [r7, #12] 800da3e: 2200 movs r2, #0 800da40: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); 800da44: 68fb ldr r3, [r7, #12] 800da46: 681b ldr r3, [r3, #0] 800da48: 685a ldr r2, [r3, #4] 800da4a: 68fb ldr r3, [r7, #12] 800da4c: 681b ldr r3, [r3, #0] 800da4e: f042 0220 orr.w r2, r2, #32 800da52: 605a str r2, [r3, #4] /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); 800da54: 68fb ldr r3, [r7, #12] 800da56: 681b ldr r3, [r3, #0] 800da58: 685a ldr r2, [r3, #4] 800da5a: 68fb ldr r3, [r7, #12] 800da5c: 681b ldr r3, [r3, #0] 800da5e: f042 0202 orr.w r2, r2, #2 800da62: 605a str r2, [r3, #4] return HAL_OK; 800da64: 2300 movs r3, #0 } 800da66: 4618 mov r0, r3 800da68: 3718 adds r7, #24 800da6a: 46bd mov sp, r7 800da6c: bd80 pop {r7, pc} 800da6e: bf00 nop 800da70: 0800de4d .word 0x0800de4d 800da74: 0800dd15 .word 0x0800dd15 800da78: 0800de69 .word 0x0800de69 800da7c: 0800ddbd .word 0x0800ddbd 800da80: 0800de85 .word 0x0800de85 0800da84 : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) { 800da84: b580 push {r7, lr} 800da86: b08a sub sp, #40 @ 0x28 800da88: af02 add r7, sp, #8 800da8a: 6078 str r0, [r7, #4] HAL_StatusTypeDef errorcode; __IO uint32_t count; __IO uint32_t resetcount; /* Initialized local variable */ errorcode = HAL_OK; 800da8c: 2300 movs r3, #0 800da8e: 77fb strb r3, [r7, #31] resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); 800da90: 4b88 ldr r3, [pc, #544] @ (800dcb4 ) 800da92: 681b ldr r3, [r3, #0] 800da94: 4a88 ldr r2, [pc, #544] @ (800dcb8 ) 800da96: fba2 2303 umull r2, r3, r2, r3 800da9a: 0a5b lsrs r3, r3, #9 800da9c: 2264 movs r2, #100 @ 0x64 800da9e: fb02 f303 mul.w r3, r2, r3 800daa2: 617b str r3, [r7, #20] count = resetcount; 800daa4: 697b ldr r3, [r7, #20] 800daa6: 61bb str r3, [r7, #24] /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); 800daa8: 687b ldr r3, [r7, #4] 800daaa: 681b ldr r3, [r3, #0] 800daac: 685a ldr r2, [r3, #4] 800daae: 687b ldr r3, [r7, #4] 800dab0: 681b ldr r3, [r3, #0] 800dab2: f022 0220 bic.w r2, r2, #32 800dab6: 605a str r2, [r3, #4] /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) 800dab8: 687b ldr r3, [r7, #4] 800daba: 681b ldr r3, [r3, #0] 800dabc: 685b ldr r3, [r3, #4] 800dabe: f003 0380 and.w r3, r3, #128 @ 0x80 800dac2: 2b80 cmp r3, #128 @ 0x80 800dac4: d117 bne.n 800daf6 { hspi->TxISR = SPI_AbortTx_ISR; 800dac6: 687b ldr r3, [r7, #4] 800dac8: 4a7c ldr r2, [pc, #496] @ (800dcbc ) 800daca: 651a str r2, [r3, #80] @ 0x50 /* Wait HAL_SPI_STATE_ABORT state */ do { if (count == 0U) 800dacc: 69bb ldr r3, [r7, #24] 800dace: 2b00 cmp r3, #0 800dad0: d106 bne.n 800dae0 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 800dad2: 687b ldr r3, [r7, #4] 800dad4: 6e1b ldr r3, [r3, #96] @ 0x60 800dad6: f043 0240 orr.w r2, r3, #64 @ 0x40 800dada: 687b ldr r3, [r7, #4] 800dadc: 661a str r2, [r3, #96] @ 0x60 break; 800dade: e008 b.n 800daf2 } count--; 800dae0: 69bb ldr r3, [r7, #24] 800dae2: 3b01 subs r3, #1 800dae4: 61bb str r3, [r7, #24] } while (hspi->State != HAL_SPI_STATE_ABORT); 800dae6: 687b ldr r3, [r7, #4] 800dae8: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800daec: b2db uxtb r3, r3 800daee: 2b07 cmp r3, #7 800daf0: d1ec bne.n 800dacc /* Reset Timeout Counter */ count = resetcount; 800daf2: 697b ldr r3, [r7, #20] 800daf4: 61bb str r3, [r7, #24] } if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) 800daf6: 687b ldr r3, [r7, #4] 800daf8: 681b ldr r3, [r3, #0] 800dafa: 685b ldr r3, [r3, #4] 800dafc: f003 0340 and.w r3, r3, #64 @ 0x40 800db00: 2b40 cmp r3, #64 @ 0x40 800db02: d117 bne.n 800db34 { hspi->RxISR = SPI_AbortRx_ISR; 800db04: 687b ldr r3, [r7, #4] 800db06: 4a6e ldr r2, [pc, #440] @ (800dcc0 ) 800db08: 64da str r2, [r3, #76] @ 0x4c /* Wait HAL_SPI_STATE_ABORT state */ do { if (count == 0U) 800db0a: 69bb ldr r3, [r7, #24] 800db0c: 2b00 cmp r3, #0 800db0e: d106 bne.n 800db1e { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 800db10: 687b ldr r3, [r7, #4] 800db12: 6e1b ldr r3, [r3, #96] @ 0x60 800db14: f043 0240 orr.w r2, r3, #64 @ 0x40 800db18: 687b ldr r3, [r7, #4] 800db1a: 661a str r2, [r3, #96] @ 0x60 break; 800db1c: e008 b.n 800db30 } count--; 800db1e: 69bb ldr r3, [r7, #24] 800db20: 3b01 subs r3, #1 800db22: 61bb str r3, [r7, #24] } while (hspi->State != HAL_SPI_STATE_ABORT); 800db24: 687b ldr r3, [r7, #4] 800db26: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 800db2a: b2db uxtb r3, r3 800db2c: 2b07 cmp r3, #7 800db2e: d1ec bne.n 800db0a /* Reset Timeout Counter */ count = resetcount; 800db30: 697b ldr r3, [r7, #20] 800db32: 61bb str r3, [r7, #24] } /* Disable the SPI DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) 800db34: 687b ldr r3, [r7, #4] 800db36: 681b ldr r3, [r3, #0] 800db38: 685b ldr r3, [r3, #4] 800db3a: f003 0302 and.w r3, r3, #2 800db3e: 2b02 cmp r3, #2 800db40: d141 bne.n 800dbc6 { /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ if (hspi->hdmatx != NULL) 800db42: 687b ldr r3, [r7, #4] 800db44: 6d5b ldr r3, [r3, #84] @ 0x54 800db46: 2b00 cmp r3, #0 800db48: d03d beq.n 800dbc6 { /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ hspi->hdmatx->XferAbortCallback = NULL; 800db4a: 687b ldr r3, [r7, #4] 800db4c: 6d5b ldr r3, [r3, #84] @ 0x54 800db4e: 2200 movs r2, #0 800db50: 639a str r2, [r3, #56] @ 0x38 /* Abort DMA Tx Handle linked to SPI Peripheral */ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) 800db52: 687b ldr r3, [r7, #4] 800db54: 6d5b ldr r3, [r3, #84] @ 0x54 800db56: 4618 mov r0, r3 800db58: f7f9 f99f bl 8006e9a 800db5c: 4603 mov r3, r0 800db5e: 2b00 cmp r3, #0 800db60: d002 beq.n 800db68 { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800db62: 687b ldr r3, [r7, #4] 800db64: 2240 movs r2, #64 @ 0x40 800db66: 661a str r2, [r3, #96] @ 0x60 } /* Disable Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); 800db68: 687b ldr r3, [r7, #4] 800db6a: 681b ldr r3, [r3, #0] 800db6c: 685a ldr r2, [r3, #4] 800db6e: 687b ldr r3, [r7, #4] 800db70: 681b ldr r3, [r3, #0] 800db72: f022 0202 bic.w r2, r2, #2 800db76: 605a str r2, [r3, #4] if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) 800db78: f7f8 feea bl 8006950 800db7c: 4603 mov r3, r0 800db7e: 461a mov r2, r3 800db80: 2164 movs r1, #100 @ 0x64 800db82: 6878 ldr r0, [r7, #4] 800db84: f000 fb14 bl 800e1b0 800db88: 4603 mov r3, r0 800db8a: 2b00 cmp r3, #0 800db8c: d002 beq.n 800db94 { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800db8e: 687b ldr r3, [r7, #4] 800db90: 2240 movs r2, #64 @ 0x40 800db92: 661a str r2, [r3, #96] @ 0x60 } /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); 800db94: 687b ldr r3, [r7, #4] 800db96: 681b ldr r3, [r3, #0] 800db98: 681a ldr r2, [r3, #0] 800db9a: 687b ldr r3, [r7, #4] 800db9c: 681b ldr r3, [r3, #0] 800db9e: f022 0240 bic.w r2, r2, #64 @ 0x40 800dba2: 601a str r2, [r3, #0] /* Empty the FRLVL fifo */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, 800dba4: f7f8 fed4 bl 8006950 800dba8: 4603 mov r3, r0 800dbaa: 9300 str r3, [sp, #0] 800dbac: 2364 movs r3, #100 @ 0x64 800dbae: 2200 movs r2, #0 800dbb0: f44f 61c0 mov.w r1, #1536 @ 0x600 800dbb4: 6878 ldr r0, [r7, #4] 800dbb6: f000 fa0d bl 800dfd4 800dbba: 4603 mov r3, r0 800dbbc: 2b00 cmp r3, #0 800dbbe: d002 beq.n 800dbc6 HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800dbc0: 687b ldr r3, [r7, #4] 800dbc2: 2240 movs r2, #64 @ 0x40 800dbc4: 661a str r2, [r3, #96] @ 0x60 } } } /* Disable the SPI DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) 800dbc6: 687b ldr r3, [r7, #4] 800dbc8: 681b ldr r3, [r3, #0] 800dbca: 685b ldr r3, [r3, #4] 800dbcc: f003 0301 and.w r3, r3, #1 800dbd0: 2b01 cmp r3, #1 800dbd2: d143 bne.n 800dc5c { /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ if (hspi->hdmarx != NULL) 800dbd4: 687b ldr r3, [r7, #4] 800dbd6: 6d9b ldr r3, [r3, #88] @ 0x58 800dbd8: 2b00 cmp r3, #0 800dbda: d03f beq.n 800dc5c { /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ hspi->hdmarx->XferAbortCallback = NULL; 800dbdc: 687b ldr r3, [r7, #4] 800dbde: 6d9b ldr r3, [r3, #88] @ 0x58 800dbe0: 2200 movs r2, #0 800dbe2: 639a str r2, [r3, #56] @ 0x38 /* Abort DMA Rx Handle linked to SPI Peripheral */ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) 800dbe4: 687b ldr r3, [r7, #4] 800dbe6: 6d9b ldr r3, [r3, #88] @ 0x58 800dbe8: 4618 mov r0, r3 800dbea: f7f9 f956 bl 8006e9a 800dbee: 4603 mov r3, r0 800dbf0: 2b00 cmp r3, #0 800dbf2: d002 beq.n 800dbfa { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800dbf4: 687b ldr r3, [r7, #4] 800dbf6: 2240 movs r2, #64 @ 0x40 800dbf8: 661a str r2, [r3, #96] @ 0x60 } /* Disable peripheral */ __HAL_SPI_DISABLE(hspi); 800dbfa: 687b ldr r3, [r7, #4] 800dbfc: 681b ldr r3, [r3, #0] 800dbfe: 681a ldr r2, [r3, #0] 800dc00: 687b ldr r3, [r7, #4] 800dc02: 681b ldr r3, [r3, #0] 800dc04: f022 0240 bic.w r2, r2, #64 @ 0x40 800dc08: 601a str r2, [r3, #0] /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) 800dc0a: f7f8 fea1 bl 8006950 800dc0e: 4603 mov r3, r0 800dc10: 9300 str r3, [sp, #0] 800dc12: 2364 movs r3, #100 @ 0x64 800dc14: 2200 movs r2, #0 800dc16: 2180 movs r1, #128 @ 0x80 800dc18: 6878 ldr r0, [r7, #4] 800dc1a: f000 f953 bl 800dec4 800dc1e: 4603 mov r3, r0 800dc20: 2b00 cmp r3, #0 800dc22: d002 beq.n 800dc2a { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800dc24: 687b ldr r3, [r7, #4] 800dc26: 2240 movs r2, #64 @ 0x40 800dc28: 661a str r2, [r3, #96] @ 0x60 } /* Empty the FRLVL fifo */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, 800dc2a: f7f8 fe91 bl 8006950 800dc2e: 4603 mov r3, r0 800dc30: 9300 str r3, [sp, #0] 800dc32: 2364 movs r3, #100 @ 0x64 800dc34: 2200 movs r2, #0 800dc36: f44f 61c0 mov.w r1, #1536 @ 0x600 800dc3a: 6878 ldr r0, [r7, #4] 800dc3c: f000 f9ca bl 800dfd4 800dc40: 4603 mov r3, r0 800dc42: 2b00 cmp r3, #0 800dc44: d002 beq.n 800dc4c HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800dc46: 687b ldr r3, [r7, #4] 800dc48: 2240 movs r2, #64 @ 0x40 800dc4a: 661a str r2, [r3, #96] @ 0x60 } /* Disable Rx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); 800dc4c: 687b ldr r3, [r7, #4] 800dc4e: 681b ldr r3, [r3, #0] 800dc50: 685a ldr r2, [r3, #4] 800dc52: 687b ldr r3, [r7, #4] 800dc54: 681b ldr r3, [r3, #0] 800dc56: f022 0201 bic.w r2, r2, #1 800dc5a: 605a str r2, [r3, #4] } } /* Reset Tx and Rx transfer counters */ hspi->RxXferCount = 0U; 800dc5c: 687b ldr r3, [r7, #4] 800dc5e: 2200 movs r2, #0 800dc60: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->TxXferCount = 0U; 800dc64: 687b ldr r3, [r7, #4] 800dc66: 2200 movs r2, #0 800dc68: 87da strh r2, [r3, #62] @ 0x3e /* Check error during Abort procedure */ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) 800dc6a: 687b ldr r3, [r7, #4] 800dc6c: 6e1b ldr r3, [r3, #96] @ 0x60 800dc6e: 2b40 cmp r3, #64 @ 0x40 800dc70: d102 bne.n 800dc78 { /* return HAL_Error in case of error during Abort procedure */ errorcode = HAL_ERROR; 800dc72: 2301 movs r3, #1 800dc74: 77fb strb r3, [r7, #31] 800dc76: e002 b.n 800dc7e } else { /* Reset errorCode */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800dc78: 687b ldr r3, [r7, #4] 800dc7a: 2200 movs r2, #0 800dc7c: 661a str r2, [r3, #96] @ 0x60 } /* Clear the Error flags in the SR register */ __HAL_SPI_CLEAR_OVRFLAG(hspi); 800dc7e: 2300 movs r3, #0 800dc80: 613b str r3, [r7, #16] 800dc82: 687b ldr r3, [r7, #4] 800dc84: 681b ldr r3, [r3, #0] 800dc86: 68db ldr r3, [r3, #12] 800dc88: 613b str r3, [r7, #16] 800dc8a: 687b ldr r3, [r7, #4] 800dc8c: 681b ldr r3, [r3, #0] 800dc8e: 689b ldr r3, [r3, #8] 800dc90: 613b str r3, [r7, #16] 800dc92: 693b ldr r3, [r7, #16] __HAL_SPI_CLEAR_FREFLAG(hspi); 800dc94: 2300 movs r3, #0 800dc96: 60fb str r3, [r7, #12] 800dc98: 687b ldr r3, [r7, #4] 800dc9a: 681b ldr r3, [r3, #0] 800dc9c: 689b ldr r3, [r3, #8] 800dc9e: 60fb str r3, [r7, #12] 800dca0: 68fb ldr r3, [r7, #12] /* Restore hspi->state to ready */ hspi->State = HAL_SPI_STATE_READY; 800dca2: 687b ldr r3, [r7, #4] 800dca4: 2201 movs r2, #1 800dca6: f883 205d strb.w r2, [r3, #93] @ 0x5d return errorcode; 800dcaa: 7ffb ldrb r3, [r7, #31] } 800dcac: 4618 mov r0, r3 800dcae: 3720 adds r7, #32 800dcb0: 46bd mov sp, r7 800dcb2: bd80 pop {r7, pc} 800dcb4: 2000000c .word 0x2000000c 800dcb8: 057619f1 .word 0x057619f1 800dcbc: 0800e2fd .word 0x0800e2fd 800dcc0: 0800e23d .word 0x0800e23d 0800dcc4 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { 800dcc4: b480 push {r7} 800dcc6: b083 sub sp, #12 800dcc8: af00 add r7, sp, #0 800dcca: 6078 str r0, [r7, #4] UNUSED(hspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_RxCpltCallback should be implemented in the user file */ } 800dccc: bf00 nop 800dcce: 370c adds r7, #12 800dcd0: 46bd mov sp, r7 800dcd2: f85d 7b04 ldr.w r7, [sp], #4 800dcd6: 4770 bx lr 0800dcd8 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) { 800dcd8: b480 push {r7} 800dcda: b083 sub sp, #12 800dcdc: af00 add r7, sp, #0 800dcde: 6078 str r0, [r7, #4] UNUSED(hspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file */ } 800dce0: bf00 nop 800dce2: 370c adds r7, #12 800dce4: 46bd mov sp, r7 800dce6: f85d 7b04 ldr.w r7, [sp], #4 800dcea: 4770 bx lr 0800dcec : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) { 800dcec: b480 push {r7} 800dcee: b083 sub sp, #12 800dcf0: af00 add r7, sp, #0 800dcf2: 6078 str r0, [r7, #4] UNUSED(hspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file */ } 800dcf4: bf00 nop 800dcf6: 370c adds r7, #12 800dcf8: 46bd mov sp, r7 800dcfa: f85d 7b04 ldr.w r7, [sp], #4 800dcfe: 4770 bx lr 0800dd00 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { 800dd00: b480 push {r7} 800dd02: b083 sub sp, #12 800dd04: af00 add r7, sp, #0 800dd06: 6078 str r0, [r7, #4] the HAL_SPI_ErrorCallback should be implemented in the user file */ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes and user can use HAL_SPI_GetError() API to check the latest error occurred */ } 800dd08: bf00 nop 800dd0a: 370c adds r7, #12 800dd0c: 46bd mov sp, r7 800dd0e: f85d 7b04 ldr.w r7, [sp], #4 800dd12: 4770 bx lr 0800dd14 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 800dd14: b580 push {r7, lr} 800dd16: b084 sub sp, #16 800dd18: af00 add r7, sp, #0 800dd1a: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800dd1c: 687b ldr r3, [r7, #4] 800dd1e: 6a9b ldr r3, [r3, #40] @ 0x28 800dd20: 60fb str r3, [r7, #12] __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800dd22: f7f8 fe15 bl 8006950 800dd26: 60b8 str r0, [r7, #8] /* DMA Normal Mode */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) 800dd28: 687b ldr r3, [r7, #4] 800dd2a: 681b ldr r3, [r3, #0] 800dd2c: 681b ldr r3, [r3, #0] 800dd2e: f003 0320 and.w r3, r3, #32 800dd32: 2b20 cmp r3, #32 800dd34: d03c beq.n 800ddb0 { /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); 800dd36: 68fb ldr r3, [r7, #12] 800dd38: 681b ldr r3, [r3, #0] 800dd3a: 685a ldr r2, [r3, #4] 800dd3c: 68fb ldr r3, [r7, #12] 800dd3e: 681b ldr r3, [r3, #0] 800dd40: f022 0220 bic.w r2, r2, #32 800dd44: 605a str r2, [r3, #4] } } #endif /* USE_SPI_CRC */ /* Check if we are in Master RX 2 line mode */ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) 800dd46: 68fb ldr r3, [r7, #12] 800dd48: 689b ldr r3, [r3, #8] 800dd4a: 2b00 cmp r3, #0 800dd4c: d10d bne.n 800dd6a 800dd4e: 68fb ldr r3, [r7, #12] 800dd50: 685b ldr r3, [r3, #4] 800dd52: f5b3 7f82 cmp.w r3, #260 @ 0x104 800dd56: d108 bne.n 800dd6a { /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); 800dd58: 68fb ldr r3, [r7, #12] 800dd5a: 681b ldr r3, [r3, #0] 800dd5c: 685a ldr r2, [r3, #4] 800dd5e: 68fb ldr r3, [r7, #12] 800dd60: 681b ldr r3, [r3, #0] 800dd62: f022 0203 bic.w r2, r2, #3 800dd66: 605a str r2, [r3, #4] 800dd68: e007 b.n 800dd7a } else { /* Normal case */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); 800dd6a: 68fb ldr r3, [r7, #12] 800dd6c: 681b ldr r3, [r3, #0] 800dd6e: 685a ldr r2, [r3, #4] 800dd70: 68fb ldr r3, [r7, #12] 800dd72: 681b ldr r3, [r3, #0] 800dd74: f022 0201 bic.w r2, r2, #1 800dd78: 605a str r2, [r3, #4] } /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) 800dd7a: 68ba ldr r2, [r7, #8] 800dd7c: 2164 movs r1, #100 @ 0x64 800dd7e: 68f8 ldr r0, [r7, #12] 800dd80: f000 f9be bl 800e100 800dd84: 4603 mov r3, r0 800dd86: 2b00 cmp r3, #0 800dd88: d002 beq.n 800dd90 { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 800dd8a: 68fb ldr r3, [r7, #12] 800dd8c: 2220 movs r2, #32 800dd8e: 661a str r2, [r3, #96] @ 0x60 } hspi->RxXferCount = 0U; 800dd90: 68fb ldr r3, [r7, #12] 800dd92: 2200 movs r2, #0 800dd94: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->State = HAL_SPI_STATE_READY; 800dd98: 68fb ldr r3, [r7, #12] 800dd9a: 2201 movs r2, #1 800dd9c: f883 205d strb.w r2, [r3, #93] @ 0x5d SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } #endif /* USE_SPI_CRC */ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800dda0: 68fb ldr r3, [r7, #12] 800dda2: 6e1b ldr r3, [r3, #96] @ 0x60 800dda4: 2b00 cmp r3, #0 800dda6: d003 beq.n 800ddb0 { /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 800dda8: 68f8 ldr r0, [r7, #12] 800ddaa: f7ff ffa9 bl 800dd00 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; 800ddae: e002 b.n 800ddb6 } /* Call user Rx complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->RxCpltCallback(hspi); #else HAL_SPI_RxCpltCallback(hspi); 800ddb0: 68f8 ldr r0, [r7, #12] 800ddb2: f7ff ff87 bl 800dcc4 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800ddb6: 3710 adds r7, #16 800ddb8: 46bd mov sp, r7 800ddba: bd80 pop {r7, pc} 0800ddbc : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { 800ddbc: b580 push {r7, lr} 800ddbe: b084 sub sp, #16 800ddc0: af00 add r7, sp, #0 800ddc2: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800ddc4: 687b ldr r3, [r7, #4] 800ddc6: 6a9b ldr r3, [r3, #40] @ 0x28 800ddc8: 60fb str r3, [r7, #12] __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 800ddca: f7f8 fdc1 bl 8006950 800ddce: 60b8 str r0, [r7, #8] /* DMA Normal Mode */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) 800ddd0: 687b ldr r3, [r7, #4] 800ddd2: 681b ldr r3, [r3, #0] 800ddd4: 681b ldr r3, [r3, #0] 800ddd6: f003 0320 and.w r3, r3, #32 800ddda: 2b20 cmp r3, #32 800dddc: d030 beq.n 800de40 { /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); 800ddde: 68fb ldr r3, [r7, #12] 800dde0: 681b ldr r3, [r3, #0] 800dde2: 685a ldr r2, [r3, #4] 800dde4: 68fb ldr r3, [r7, #12] 800dde6: 681b ldr r3, [r3, #0] 800dde8: f022 0220 bic.w r2, r2, #32 800ddec: 605a str r2, [r3, #4] } } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) 800ddee: 68ba ldr r2, [r7, #8] 800ddf0: 2164 movs r1, #100 @ 0x64 800ddf2: 68f8 ldr r0, [r7, #12] 800ddf4: f000 f9dc bl 800e1b0 800ddf8: 4603 mov r3, r0 800ddfa: 2b00 cmp r3, #0 800ddfc: d005 beq.n 800de0a { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800ddfe: 68fb ldr r3, [r7, #12] 800de00: 6e1b ldr r3, [r3, #96] @ 0x60 800de02: f043 0220 orr.w r2, r3, #32 800de06: 68fb ldr r3, [r7, #12] 800de08: 661a str r2, [r3, #96] @ 0x60 } /* Disable Rx/Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); 800de0a: 68fb ldr r3, [r7, #12] 800de0c: 681b ldr r3, [r3, #0] 800de0e: 685a ldr r2, [r3, #4] 800de10: 68fb ldr r3, [r7, #12] 800de12: 681b ldr r3, [r3, #0] 800de14: f022 0203 bic.w r2, r2, #3 800de18: 605a str r2, [r3, #4] hspi->TxXferCount = 0U; 800de1a: 68fb ldr r3, [r7, #12] 800de1c: 2200 movs r2, #0 800de1e: 87da strh r2, [r3, #62] @ 0x3e hspi->RxXferCount = 0U; 800de20: 68fb ldr r3, [r7, #12] 800de22: 2200 movs r2, #0 800de24: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->State = HAL_SPI_STATE_READY; 800de28: 68fb ldr r3, [r7, #12] 800de2a: 2201 movs r2, #1 800de2c: f883 205d strb.w r2, [r3, #93] @ 0x5d SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } #endif /* USE_SPI_CRC */ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 800de30: 68fb ldr r3, [r7, #12] 800de32: 6e1b ldr r3, [r3, #96] @ 0x60 800de34: 2b00 cmp r3, #0 800de36: d003 beq.n 800de40 { /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 800de38: 68f8 ldr r0, [r7, #12] 800de3a: f7ff ff61 bl 800dd00 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; 800de3e: e002 b.n 800de46 } /* Call user TxRx complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->TxRxCpltCallback(hspi); #else HAL_SPI_TxRxCpltCallback(hspi); 800de40: 68f8 ldr r0, [r7, #12] 800de42: f7f7 fa9b bl 800537c #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800de46: 3710 adds r7, #16 800de48: 46bd mov sp, r7 800de4a: bd80 pop {r7, pc} 0800de4c : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { 800de4c: b580 push {r7, lr} 800de4e: b084 sub sp, #16 800de50: af00 add r7, sp, #0 800de52: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800de54: 687b ldr r3, [r7, #4] 800de56: 6a9b ldr r3, [r3, #40] @ 0x28 800de58: 60fb str r3, [r7, #12] /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->RxHalfCpltCallback(hspi); #else HAL_SPI_RxHalfCpltCallback(hspi); 800de5a: 68f8 ldr r0, [r7, #12] 800de5c: f7ff ff3c bl 800dcd8 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800de60: bf00 nop 800de62: 3710 adds r7, #16 800de64: 46bd mov sp, r7 800de66: bd80 pop {r7, pc} 0800de68 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { 800de68: b580 push {r7, lr} 800de6a: b084 sub sp, #16 800de6c: af00 add r7, sp, #0 800de6e: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800de70: 687b ldr r3, [r7, #4] 800de72: 6a9b ldr r3, [r3, #40] @ 0x28 800de74: 60fb str r3, [r7, #12] /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->TxRxHalfCpltCallback(hspi); #else HAL_SPI_TxRxHalfCpltCallback(hspi); 800de76: 68f8 ldr r0, [r7, #12] 800de78: f7ff ff38 bl 800dcec #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800de7c: bf00 nop 800de7e: 3710 adds r7, #16 800de80: 46bd mov sp, r7 800de82: bd80 pop {r7, pc} 0800de84 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { 800de84: b580 push {r7, lr} 800de86: b084 sub sp, #16 800de88: af00 add r7, sp, #0 800de8a: 6078 str r0, [r7, #4] SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800de8c: 687b ldr r3, [r7, #4] 800de8e: 6a9b ldr r3, [r3, #40] @ 0x28 800de90: 60fb str r3, [r7, #12] /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); 800de92: 68fb ldr r3, [r7, #12] 800de94: 681b ldr r3, [r3, #0] 800de96: 685a ldr r2, [r3, #4] 800de98: 68fb ldr r3, [r7, #12] 800de9a: 681b ldr r3, [r3, #0] 800de9c: f022 0203 bic.w r2, r2, #3 800dea0: 605a str r2, [r3, #4] SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); 800dea2: 68fb ldr r3, [r7, #12] 800dea4: 6e1b ldr r3, [r3, #96] @ 0x60 800dea6: f043 0210 orr.w r2, r3, #16 800deaa: 68fb ldr r3, [r7, #12] 800deac: 661a str r2, [r3, #96] @ 0x60 hspi->State = HAL_SPI_STATE_READY; 800deae: 68fb ldr r3, [r7, #12] 800deb0: 2201 movs r2, #1 800deb2: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Call user error callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) hspi->ErrorCallback(hspi); #else HAL_SPI_ErrorCallback(hspi); 800deb6: 68f8 ldr r0, [r7, #12] 800deb8: f7ff ff22 bl 800dd00 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } 800debc: bf00 nop 800debe: 3710 adds r7, #16 800dec0: 46bd mov sp, r7 800dec2: bd80 pop {r7, pc} 0800dec4 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { 800dec4: b580 push {r7, lr} 800dec6: b088 sub sp, #32 800dec8: af00 add r7, sp, #0 800deca: 60f8 str r0, [r7, #12] 800decc: 60b9 str r1, [r7, #8] 800dece: 603b str r3, [r7, #0] 800ded0: 4613 mov r3, r2 800ded2: 71fb strb r3, [r7, #7] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 800ded4: f7f8 fd3c bl 8006950 800ded8: 4602 mov r2, r0 800deda: 6abb ldr r3, [r7, #40] @ 0x28 800dedc: 1a9b subs r3, r3, r2 800dede: 683a ldr r2, [r7, #0] 800dee0: 4413 add r3, r2 800dee2: 61fb str r3, [r7, #28] tmp_tickstart = HAL_GetTick(); 800dee4: f7f8 fd34 bl 8006950 800dee8: 61b8 str r0, [r7, #24] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); 800deea: 4b39 ldr r3, [pc, #228] @ (800dfd0 ) 800deec: 681b ldr r3, [r3, #0] 800deee: 015b lsls r3, r3, #5 800def0: 0d1b lsrs r3, r3, #20 800def2: 69fa ldr r2, [r7, #28] 800def4: fb02 f303 mul.w r3, r2, r3 800def8: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 800defa: e055 b.n 800dfa8 { if (Timeout != HAL_MAX_DELAY) 800defc: 683b ldr r3, [r7, #0] 800defe: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800df02: d051 beq.n 800dfa8 { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 800df04: f7f8 fd24 bl 8006950 800df08: 4602 mov r2, r0 800df0a: 69bb ldr r3, [r7, #24] 800df0c: 1ad3 subs r3, r2, r3 800df0e: 69fa ldr r2, [r7, #28] 800df10: 429a cmp r2, r3 800df12: d902 bls.n 800df1a 800df14: 69fb ldr r3, [r7, #28] 800df16: 2b00 cmp r3, #0 800df18: d13d bne.n 800df96 /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 800df1a: 68fb ldr r3, [r7, #12] 800df1c: 681b ldr r3, [r3, #0] 800df1e: 685a ldr r2, [r3, #4] 800df20: 68fb ldr r3, [r7, #12] 800df22: 681b ldr r3, [r3, #0] 800df24: f022 02e0 bic.w r2, r2, #224 @ 0xe0 800df28: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800df2a: 68fb ldr r3, [r7, #12] 800df2c: 685b ldr r3, [r3, #4] 800df2e: f5b3 7f82 cmp.w r3, #260 @ 0x104 800df32: d111 bne.n 800df58 800df34: 68fb ldr r3, [r7, #12] 800df36: 689b ldr r3, [r3, #8] 800df38: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800df3c: d004 beq.n 800df48 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800df3e: 68fb ldr r3, [r7, #12] 800df40: 689b ldr r3, [r3, #8] 800df42: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800df46: d107 bne.n 800df58 { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800df48: 68fb ldr r3, [r7, #12] 800df4a: 681b ldr r3, [r3, #0] 800df4c: 681a ldr r2, [r3, #0] 800df4e: 68fb ldr r3, [r7, #12] 800df50: 681b ldr r3, [r3, #0] 800df52: f022 0240 bic.w r2, r2, #64 @ 0x40 800df56: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 800df58: 68fb ldr r3, [r7, #12] 800df5a: 6a9b ldr r3, [r3, #40] @ 0x28 800df5c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800df60: d10f bne.n 800df82 { SPI_RESET_CRC(hspi); 800df62: 68fb ldr r3, [r7, #12] 800df64: 681b ldr r3, [r3, #0] 800df66: 681a ldr r2, [r3, #0] 800df68: 68fb ldr r3, [r7, #12] 800df6a: 681b ldr r3, [r3, #0] 800df6c: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800df70: 601a str r2, [r3, #0] 800df72: 68fb ldr r3, [r7, #12] 800df74: 681b ldr r3, [r3, #0] 800df76: 681a ldr r2, [r3, #0] 800df78: 68fb ldr r3, [r7, #12] 800df7a: 681b ldr r3, [r3, #0] 800df7c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 800df80: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 800df82: 68fb ldr r3, [r7, #12] 800df84: 2201 movs r2, #1 800df86: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 800df8a: 68fb ldr r3, [r7, #12] 800df8c: 2200 movs r2, #0 800df8e: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800df92: 2303 movs r3, #3 800df94: e018 b.n 800dfc8 } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 800df96: 697b ldr r3, [r7, #20] 800df98: 2b00 cmp r3, #0 800df9a: d102 bne.n 800dfa2 { tmp_timeout = 0U; 800df9c: 2300 movs r3, #0 800df9e: 61fb str r3, [r7, #28] 800dfa0: e002 b.n 800dfa8 } else { count--; 800dfa2: 697b ldr r3, [r7, #20] 800dfa4: 3b01 subs r3, #1 800dfa6: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 800dfa8: 68fb ldr r3, [r7, #12] 800dfaa: 681b ldr r3, [r3, #0] 800dfac: 689a ldr r2, [r3, #8] 800dfae: 68bb ldr r3, [r7, #8] 800dfb0: 4013 ands r3, r2 800dfb2: 68ba ldr r2, [r7, #8] 800dfb4: 429a cmp r2, r3 800dfb6: bf0c ite eq 800dfb8: 2301 moveq r3, #1 800dfba: 2300 movne r3, #0 800dfbc: b2db uxtb r3, r3 800dfbe: 461a mov r2, r3 800dfc0: 79fb ldrb r3, [r7, #7] 800dfc2: 429a cmp r2, r3 800dfc4: d19a bne.n 800defc } } } return HAL_OK; 800dfc6: 2300 movs r3, #0 } 800dfc8: 4618 mov r0, r3 800dfca: 3720 adds r7, #32 800dfcc: 46bd mov sp, r7 800dfce: bd80 pop {r7, pc} 800dfd0: 2000000c .word 0x2000000c 0800dfd4 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { 800dfd4: b580 push {r7, lr} 800dfd6: b08a sub sp, #40 @ 0x28 800dfd8: af00 add r7, sp, #0 800dfda: 60f8 str r0, [r7, #12] 800dfdc: 60b9 str r1, [r7, #8] 800dfde: 607a str r2, [r7, #4] 800dfe0: 603b str r3, [r7, #0] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; 800dfe2: 2300 movs r3, #0 800dfe4: 75fb strb r3, [r7, #23] /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 800dfe6: f7f8 fcb3 bl 8006950 800dfea: 4602 mov r2, r0 800dfec: 6b3b ldr r3, [r7, #48] @ 0x30 800dfee: 1a9b subs r3, r3, r2 800dff0: 683a ldr r2, [r7, #0] 800dff2: 4413 add r3, r2 800dff4: 627b str r3, [r7, #36] @ 0x24 tmp_tickstart = HAL_GetTick(); 800dff6: f7f8 fcab bl 8006950 800dffa: 6238 str r0, [r7, #32] /* Initialize the 8bit temporary pointer */ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; 800dffc: 68fb ldr r3, [r7, #12] 800dffe: 681b ldr r3, [r3, #0] 800e000: 330c adds r3, #12 800e002: 61fb str r3, [r7, #28] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); 800e004: 4b3d ldr r3, [pc, #244] @ (800e0fc ) 800e006: 681a ldr r2, [r3, #0] 800e008: 4613 mov r3, r2 800e00a: 009b lsls r3, r3, #2 800e00c: 4413 add r3, r2 800e00e: 00da lsls r2, r3, #3 800e010: 1ad3 subs r3, r2, r3 800e012: 0d1b lsrs r3, r3, #20 800e014: 6a7a ldr r2, [r7, #36] @ 0x24 800e016: fb02 f303 mul.w r3, r2, r3 800e01a: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 800e01c: e061 b.n 800e0e2 { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) 800e01e: 68bb ldr r3, [r7, #8] 800e020: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 800e024: d107 bne.n 800e036 800e026: 687b ldr r3, [r7, #4] 800e028: 2b00 cmp r3, #0 800e02a: d104 bne.n 800e036 { /* Flush Data Register by a blank read */ tmpreg8 = *ptmpreg8; 800e02c: 69fb ldr r3, [r7, #28] 800e02e: 781b ldrb r3, [r3, #0] 800e030: b2db uxtb r3, r3 800e032: 75fb strb r3, [r7, #23] /* To avoid GCC warning */ UNUSED(tmpreg8); 800e034: 7dfb ldrb r3, [r7, #23] } if (Timeout != HAL_MAX_DELAY) 800e036: 683b ldr r3, [r7, #0] 800e038: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e03c: d051 beq.n 800e0e2 { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 800e03e: f7f8 fc87 bl 8006950 800e042: 4602 mov r2, r0 800e044: 6a3b ldr r3, [r7, #32] 800e046: 1ad3 subs r3, r2, r3 800e048: 6a7a ldr r2, [r7, #36] @ 0x24 800e04a: 429a cmp r2, r3 800e04c: d902 bls.n 800e054 800e04e: 6a7b ldr r3, [r7, #36] @ 0x24 800e050: 2b00 cmp r3, #0 800e052: d13d bne.n 800e0d0 /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 800e054: 68fb ldr r3, [r7, #12] 800e056: 681b ldr r3, [r3, #0] 800e058: 685a ldr r2, [r3, #4] 800e05a: 68fb ldr r3, [r7, #12] 800e05c: 681b ldr r3, [r3, #0] 800e05e: f022 02e0 bic.w r2, r2, #224 @ 0xe0 800e062: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800e064: 68fb ldr r3, [r7, #12] 800e066: 685b ldr r3, [r3, #4] 800e068: f5b3 7f82 cmp.w r3, #260 @ 0x104 800e06c: d111 bne.n 800e092 800e06e: 68fb ldr r3, [r7, #12] 800e070: 689b ldr r3, [r3, #8] 800e072: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800e076: d004 beq.n 800e082 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800e078: 68fb ldr r3, [r7, #12] 800e07a: 689b ldr r3, [r3, #8] 800e07c: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800e080: d107 bne.n 800e092 { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800e082: 68fb ldr r3, [r7, #12] 800e084: 681b ldr r3, [r3, #0] 800e086: 681a ldr r2, [r3, #0] 800e088: 68fb ldr r3, [r7, #12] 800e08a: 681b ldr r3, [r3, #0] 800e08c: f022 0240 bic.w r2, r2, #64 @ 0x40 800e090: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 800e092: 68fb ldr r3, [r7, #12] 800e094: 6a9b ldr r3, [r3, #40] @ 0x28 800e096: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e09a: d10f bne.n 800e0bc { SPI_RESET_CRC(hspi); 800e09c: 68fb ldr r3, [r7, #12] 800e09e: 681b ldr r3, [r3, #0] 800e0a0: 681a ldr r2, [r3, #0] 800e0a2: 68fb ldr r3, [r7, #12] 800e0a4: 681b ldr r3, [r3, #0] 800e0a6: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800e0aa: 601a str r2, [r3, #0] 800e0ac: 68fb ldr r3, [r7, #12] 800e0ae: 681b ldr r3, [r3, #0] 800e0b0: 681a ldr r2, [r3, #0] 800e0b2: 68fb ldr r3, [r7, #12] 800e0b4: 681b ldr r3, [r3, #0] 800e0b6: f442 5200 orr.w r2, r2, #8192 @ 0x2000 800e0ba: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 800e0bc: 68fb ldr r3, [r7, #12] 800e0be: 2201 movs r2, #1 800e0c0: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 800e0c4: 68fb ldr r3, [r7, #12] 800e0c6: 2200 movs r2, #0 800e0c8: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800e0cc: 2303 movs r3, #3 800e0ce: e011 b.n 800e0f4 } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 800e0d0: 69bb ldr r3, [r7, #24] 800e0d2: 2b00 cmp r3, #0 800e0d4: d102 bne.n 800e0dc { tmp_timeout = 0U; 800e0d6: 2300 movs r3, #0 800e0d8: 627b str r3, [r7, #36] @ 0x24 800e0da: e002 b.n 800e0e2 } else { count--; 800e0dc: 69bb ldr r3, [r7, #24] 800e0de: 3b01 subs r3, #1 800e0e0: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 800e0e2: 68fb ldr r3, [r7, #12] 800e0e4: 681b ldr r3, [r3, #0] 800e0e6: 689a ldr r2, [r3, #8] 800e0e8: 68bb ldr r3, [r7, #8] 800e0ea: 4013 ands r3, r2 800e0ec: 687a ldr r2, [r7, #4] 800e0ee: 429a cmp r2, r3 800e0f0: d195 bne.n 800e01e } } } return HAL_OK; 800e0f2: 2300 movs r3, #0 } 800e0f4: 4618 mov r0, r3 800e0f6: 3728 adds r7, #40 @ 0x28 800e0f8: 46bd mov sp, r7 800e0fa: bd80 pop {r7, pc} 800e0fc: 2000000c .word 0x2000000c 0800e100 : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 800e100: b580 push {r7, lr} 800e102: b086 sub sp, #24 800e104: af02 add r7, sp, #8 800e106: 60f8 str r0, [r7, #12] 800e108: 60b9 str r1, [r7, #8] 800e10a: 607a str r2, [r7, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800e10c: 68fb ldr r3, [r7, #12] 800e10e: 685b ldr r3, [r3, #4] 800e110: f5b3 7f82 cmp.w r3, #260 @ 0x104 800e114: d111 bne.n 800e13a 800e116: 68fb ldr r3, [r7, #12] 800e118: 689b ldr r3, [r3, #8] 800e11a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800e11e: d004 beq.n 800e12a || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800e120: 68fb ldr r3, [r7, #12] 800e122: 689b ldr r3, [r3, #8] 800e124: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800e128: d107 bne.n 800e13a { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800e12a: 68fb ldr r3, [r7, #12] 800e12c: 681b ldr r3, [r3, #0] 800e12e: 681a ldr r2, [r3, #0] 800e130: 68fb ldr r3, [r7, #12] 800e132: 681b ldr r3, [r3, #0] 800e134: f022 0240 bic.w r2, r2, #64 @ 0x40 800e138: 601a str r2, [r3, #0] } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 800e13a: 687b ldr r3, [r7, #4] 800e13c: 9300 str r3, [sp, #0] 800e13e: 68bb ldr r3, [r7, #8] 800e140: 2200 movs r2, #0 800e142: 2180 movs r1, #128 @ 0x80 800e144: 68f8 ldr r0, [r7, #12] 800e146: f7ff febd bl 800dec4 800e14a: 4603 mov r3, r0 800e14c: 2b00 cmp r3, #0 800e14e: d007 beq.n 800e160 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800e150: 68fb ldr r3, [r7, #12] 800e152: 6e1b ldr r3, [r3, #96] @ 0x60 800e154: f043 0220 orr.w r2, r3, #32 800e158: 68fb ldr r3, [r7, #12] 800e15a: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800e15c: 2303 movs r3, #3 800e15e: e023 b.n 800e1a8 } if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800e160: 68fb ldr r3, [r7, #12] 800e162: 685b ldr r3, [r3, #4] 800e164: f5b3 7f82 cmp.w r3, #260 @ 0x104 800e168: d11d bne.n 800e1a6 800e16a: 68fb ldr r3, [r7, #12] 800e16c: 689b ldr r3, [r3, #8] 800e16e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800e172: d004 beq.n 800e17e || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800e174: 68fb ldr r3, [r7, #12] 800e176: 689b ldr r3, [r3, #8] 800e178: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800e17c: d113 bne.n 800e1a6 { /* Empty the FRLVL fifo */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 800e17e: 687b ldr r3, [r7, #4] 800e180: 9300 str r3, [sp, #0] 800e182: 68bb ldr r3, [r7, #8] 800e184: 2200 movs r2, #0 800e186: f44f 61c0 mov.w r1, #1536 @ 0x600 800e18a: 68f8 ldr r0, [r7, #12] 800e18c: f7ff ff22 bl 800dfd4 800e190: 4603 mov r3, r0 800e192: 2b00 cmp r3, #0 800e194: d007 beq.n 800e1a6 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800e196: 68fb ldr r3, [r7, #12] 800e198: 6e1b ldr r3, [r3, #96] @ 0x60 800e19a: f043 0220 orr.w r2, r3, #32 800e19e: 68fb ldr r3, [r7, #12] 800e1a0: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800e1a2: 2303 movs r3, #3 800e1a4: e000 b.n 800e1a8 } } return HAL_OK; 800e1a6: 2300 movs r3, #0 } 800e1a8: 4618 mov r0, r3 800e1aa: 3710 adds r7, #16 800e1ac: 46bd mov sp, r7 800e1ae: bd80 pop {r7, pc} 0800e1b0 : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 800e1b0: b580 push {r7, lr} 800e1b2: b086 sub sp, #24 800e1b4: af02 add r7, sp, #8 800e1b6: 60f8 str r0, [r7, #12] 800e1b8: 60b9 str r1, [r7, #8] 800e1ba: 607a str r2, [r7, #4] /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 800e1bc: 687b ldr r3, [r7, #4] 800e1be: 9300 str r3, [sp, #0] 800e1c0: 68bb ldr r3, [r7, #8] 800e1c2: 2200 movs r2, #0 800e1c4: f44f 51c0 mov.w r1, #6144 @ 0x1800 800e1c8: 68f8 ldr r0, [r7, #12] 800e1ca: f7ff ff03 bl 800dfd4 800e1ce: 4603 mov r3, r0 800e1d0: 2b00 cmp r3, #0 800e1d2: d007 beq.n 800e1e4 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800e1d4: 68fb ldr r3, [r7, #12] 800e1d6: 6e1b ldr r3, [r3, #96] @ 0x60 800e1d8: f043 0220 orr.w r2, r3, #32 800e1dc: 68fb ldr r3, [r7, #12] 800e1de: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800e1e0: 2303 movs r3, #3 800e1e2: e027 b.n 800e234 } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 800e1e4: 687b ldr r3, [r7, #4] 800e1e6: 9300 str r3, [sp, #0] 800e1e8: 68bb ldr r3, [r7, #8] 800e1ea: 2200 movs r2, #0 800e1ec: 2180 movs r1, #128 @ 0x80 800e1ee: 68f8 ldr r0, [r7, #12] 800e1f0: f7ff fe68 bl 800dec4 800e1f4: 4603 mov r3, r0 800e1f6: 2b00 cmp r3, #0 800e1f8: d007 beq.n 800e20a { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800e1fa: 68fb ldr r3, [r7, #12] 800e1fc: 6e1b ldr r3, [r3, #96] @ 0x60 800e1fe: f043 0220 orr.w r2, r3, #32 800e202: 68fb ldr r3, [r7, #12] 800e204: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800e206: 2303 movs r3, #3 800e208: e014 b.n 800e234 } /* Control if the RX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 800e20a: 687b ldr r3, [r7, #4] 800e20c: 9300 str r3, [sp, #0] 800e20e: 68bb ldr r3, [r7, #8] 800e210: 2200 movs r2, #0 800e212: f44f 61c0 mov.w r1, #1536 @ 0x600 800e216: 68f8 ldr r0, [r7, #12] 800e218: f7ff fedc bl 800dfd4 800e21c: 4603 mov r3, r0 800e21e: 2b00 cmp r3, #0 800e220: d007 beq.n 800e232 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800e222: 68fb ldr r3, [r7, #12] 800e224: 6e1b ldr r3, [r3, #96] @ 0x60 800e226: f043 0220 orr.w r2, r3, #32 800e22a: 68fb ldr r3, [r7, #12] 800e22c: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800e22e: 2303 movs r3, #3 800e230: e000 b.n 800e234 } return HAL_OK; 800e232: 2300 movs r3, #0 } 800e234: 4618 mov r0, r3 800e236: 3710 adds r7, #16 800e238: 46bd mov sp, r7 800e23a: bd80 pop {r7, pc} 0800e23c : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) { 800e23c: b580 push {r7, lr} 800e23e: b086 sub sp, #24 800e240: af02 add r7, sp, #8 800e242: 6078 str r0, [r7, #4] __IO uint32_t count; /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); 800e244: 687b ldr r3, [r7, #4] 800e246: 681b ldr r3, [r3, #0] 800e248: 681a ldr r2, [r3, #0] 800e24a: 687b ldr r3, [r7, #4] 800e24c: 681b ldr r3, [r3, #0] 800e24e: f022 0240 bic.w r2, r2, #64 @ 0x40 800e252: 601a str r2, [r3, #0] count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); 800e254: 4b27 ldr r3, [pc, #156] @ (800e2f4 ) 800e256: 681b ldr r3, [r3, #0] 800e258: 4a27 ldr r2, [pc, #156] @ (800e2f8 ) 800e25a: fba2 2303 umull r2, r3, r2, r3 800e25e: 0a5b lsrs r3, r3, #9 800e260: 2264 movs r2, #100 @ 0x64 800e262: fb02 f303 mul.w r3, r2, r3 800e266: 60fb str r3, [r7, #12] /* Disable RXNEIE interrupt */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); 800e268: 687b ldr r3, [r7, #4] 800e26a: 681b ldr r3, [r3, #0] 800e26c: 685a ldr r2, [r3, #4] 800e26e: 687b ldr r3, [r7, #4] 800e270: 681b ldr r3, [r3, #0] 800e272: f022 0240 bic.w r2, r2, #64 @ 0x40 800e276: 605a str r2, [r3, #4] /* Check RXNEIE is disabled */ do { if (count == 0U) 800e278: 68fb ldr r3, [r7, #12] 800e27a: 2b00 cmp r3, #0 800e27c: d106 bne.n 800e28c { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 800e27e: 687b ldr r3, [r7, #4] 800e280: 6e1b ldr r3, [r3, #96] @ 0x60 800e282: f043 0240 orr.w r2, r3, #64 @ 0x40 800e286: 687b ldr r3, [r7, #4] 800e288: 661a str r2, [r3, #96] @ 0x60 break; 800e28a: e009 b.n 800e2a0 } count--; 800e28c: 68fb ldr r3, [r7, #12] 800e28e: 3b01 subs r3, #1 800e290: 60fb str r3, [r7, #12] } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); 800e292: 687b ldr r3, [r7, #4] 800e294: 681b ldr r3, [r3, #0] 800e296: 685b ldr r3, [r3, #4] 800e298: f003 0340 and.w r3, r3, #64 @ 0x40 800e29c: 2b40 cmp r3, #64 @ 0x40 800e29e: d0eb beq.n 800e278 /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) 800e2a0: f7f8 fb56 bl 8006950 800e2a4: 4603 mov r3, r0 800e2a6: 9300 str r3, [sp, #0] 800e2a8: 2364 movs r3, #100 @ 0x64 800e2aa: 2200 movs r2, #0 800e2ac: 2180 movs r1, #128 @ 0x80 800e2ae: 6878 ldr r0, [r7, #4] 800e2b0: f7ff fe08 bl 800dec4 800e2b4: 4603 mov r3, r0 800e2b6: 2b00 cmp r3, #0 800e2b8: d002 beq.n 800e2c0 { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800e2ba: 687b ldr r3, [r7, #4] 800e2bc: 2240 movs r2, #64 @ 0x40 800e2be: 661a str r2, [r3, #96] @ 0x60 } /* Empty the FRLVL fifo */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, 800e2c0: f7f8 fb46 bl 8006950 800e2c4: 4603 mov r3, r0 800e2c6: 9300 str r3, [sp, #0] 800e2c8: 2364 movs r3, #100 @ 0x64 800e2ca: 2200 movs r2, #0 800e2cc: f44f 61c0 mov.w r1, #1536 @ 0x600 800e2d0: 6878 ldr r0, [r7, #4] 800e2d2: f7ff fe7f bl 800dfd4 800e2d6: 4603 mov r3, r0 800e2d8: 2b00 cmp r3, #0 800e2da: d002 beq.n 800e2e2 HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800e2dc: 687b ldr r3, [r7, #4] 800e2de: 2240 movs r2, #64 @ 0x40 800e2e0: 661a str r2, [r3, #96] @ 0x60 } hspi->State = HAL_SPI_STATE_ABORT; 800e2e2: 687b ldr r3, [r7, #4] 800e2e4: 2207 movs r2, #7 800e2e6: f883 205d strb.w r2, [r3, #93] @ 0x5d } 800e2ea: bf00 nop 800e2ec: 3710 adds r7, #16 800e2ee: 46bd mov sp, r7 800e2f0: bd80 pop {r7, pc} 800e2f2: bf00 nop 800e2f4: 2000000c .word 0x2000000c 800e2f8: 057619f1 .word 0x057619f1 0800e2fc : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) { 800e2fc: b580 push {r7, lr} 800e2fe: b086 sub sp, #24 800e300: af02 add r7, sp, #8 800e302: 6078 str r0, [r7, #4] __IO uint32_t count; count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); 800e304: 4b4c ldr r3, [pc, #304] @ (800e438 ) 800e306: 681b ldr r3, [r3, #0] 800e308: 4a4c ldr r2, [pc, #304] @ (800e43c ) 800e30a: fba2 2303 umull r2, r3, r2, r3 800e30e: 0a5b lsrs r3, r3, #9 800e310: 2264 movs r2, #100 @ 0x64 800e312: fb02 f303 mul.w r3, r2, r3 800e316: 60fb str r3, [r7, #12] /* Disable TXEIE interrupt */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); 800e318: 687b ldr r3, [r7, #4] 800e31a: 681b ldr r3, [r3, #0] 800e31c: 685a ldr r2, [r3, #4] 800e31e: 687b ldr r3, [r7, #4] 800e320: 681b ldr r3, [r3, #0] 800e322: f022 0280 bic.w r2, r2, #128 @ 0x80 800e326: 605a str r2, [r3, #4] /* Check TXEIE is disabled */ do { if (count == 0U) 800e328: 68fb ldr r3, [r7, #12] 800e32a: 2b00 cmp r3, #0 800e32c: d106 bne.n 800e33c { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 800e32e: 687b ldr r3, [r7, #4] 800e330: 6e1b ldr r3, [r3, #96] @ 0x60 800e332: f043 0240 orr.w r2, r3, #64 @ 0x40 800e336: 687b ldr r3, [r7, #4] 800e338: 661a str r2, [r3, #96] @ 0x60 break; 800e33a: e009 b.n 800e350 } count--; 800e33c: 68fb ldr r3, [r7, #12] 800e33e: 3b01 subs r3, #1 800e340: 60fb str r3, [r7, #12] } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); 800e342: 687b ldr r3, [r7, #4] 800e344: 681b ldr r3, [r3, #0] 800e346: 685b ldr r3, [r3, #4] 800e348: f003 0380 and.w r3, r3, #128 @ 0x80 800e34c: 2b80 cmp r3, #128 @ 0x80 800e34e: d0eb beq.n 800e328 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) 800e350: f7f8 fafe bl 8006950 800e354: 4603 mov r3, r0 800e356: 461a mov r2, r3 800e358: 2164 movs r1, #100 @ 0x64 800e35a: 6878 ldr r0, [r7, #4] 800e35c: f7ff ff28 bl 800e1b0 800e360: 4603 mov r3, r0 800e362: 2b00 cmp r3, #0 800e364: d002 beq.n 800e36c { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800e366: 687b ldr r3, [r7, #4] 800e368: 2240 movs r2, #64 @ 0x40 800e36a: 661a str r2, [r3, #96] @ 0x60 } /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); 800e36c: 687b ldr r3, [r7, #4] 800e36e: 681b ldr r3, [r3, #0] 800e370: 681a ldr r2, [r3, #0] 800e372: 687b ldr r3, [r7, #4] 800e374: 681b ldr r3, [r3, #0] 800e376: f022 0240 bic.w r2, r2, #64 @ 0x40 800e37a: 601a str r2, [r3, #0] /* Empty the FRLVL fifo */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, 800e37c: f7f8 fae8 bl 8006950 800e380: 4603 mov r3, r0 800e382: 9300 str r3, [sp, #0] 800e384: 2364 movs r3, #100 @ 0x64 800e386: 2200 movs r2, #0 800e388: f44f 61c0 mov.w r1, #1536 @ 0x600 800e38c: 6878 ldr r0, [r7, #4] 800e38e: f7ff fe21 bl 800dfd4 800e392: 4603 mov r3, r0 800e394: 2b00 cmp r3, #0 800e396: d002 beq.n 800e39e HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800e398: 687b ldr r3, [r7, #4] 800e39a: 2240 movs r2, #64 @ 0x40 800e39c: 661a str r2, [r3, #96] @ 0x60 } /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) 800e39e: 687b ldr r3, [r7, #4] 800e3a0: 681b ldr r3, [r3, #0] 800e3a2: 685b ldr r3, [r3, #4] 800e3a4: f003 0340 and.w r3, r3, #64 @ 0x40 800e3a8: 2b40 cmp r3, #64 @ 0x40 800e3aa: d13c bne.n 800e426 { /* Disable RXNEIE interrupt */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); 800e3ac: 687b ldr r3, [r7, #4] 800e3ae: 681b ldr r3, [r3, #0] 800e3b0: 685a ldr r2, [r3, #4] 800e3b2: 687b ldr r3, [r7, #4] 800e3b4: 681b ldr r3, [r3, #0] 800e3b6: f022 0240 bic.w r2, r2, #64 @ 0x40 800e3ba: 605a str r2, [r3, #4] /* Check RXNEIE is disabled */ do { if (count == 0U) 800e3bc: 68fb ldr r3, [r7, #12] 800e3be: 2b00 cmp r3, #0 800e3c0: d106 bne.n 800e3d0 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); 800e3c2: 687b ldr r3, [r7, #4] 800e3c4: 6e1b ldr r3, [r3, #96] @ 0x60 800e3c6: f043 0240 orr.w r2, r3, #64 @ 0x40 800e3ca: 687b ldr r3, [r7, #4] 800e3cc: 661a str r2, [r3, #96] @ 0x60 break; 800e3ce: e009 b.n 800e3e4 } count--; 800e3d0: 68fb ldr r3, [r7, #12] 800e3d2: 3b01 subs r3, #1 800e3d4: 60fb str r3, [r7, #12] } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); 800e3d6: 687b ldr r3, [r7, #4] 800e3d8: 681b ldr r3, [r3, #0] 800e3da: 685b ldr r3, [r3, #4] 800e3dc: f003 0340 and.w r3, r3, #64 @ 0x40 800e3e0: 2b40 cmp r3, #64 @ 0x40 800e3e2: d0eb beq.n 800e3bc /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) 800e3e4: f7f8 fab4 bl 8006950 800e3e8: 4603 mov r3, r0 800e3ea: 9300 str r3, [sp, #0] 800e3ec: 2364 movs r3, #100 @ 0x64 800e3ee: 2200 movs r2, #0 800e3f0: 2180 movs r1, #128 @ 0x80 800e3f2: 6878 ldr r0, [r7, #4] 800e3f4: f7ff fd66 bl 800dec4 800e3f8: 4603 mov r3, r0 800e3fa: 2b00 cmp r3, #0 800e3fc: d002 beq.n 800e404 { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800e3fe: 687b ldr r3, [r7, #4] 800e400: 2240 movs r2, #64 @ 0x40 800e402: 661a str r2, [r3, #96] @ 0x60 } /* Empty the FRLVL fifo */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, 800e404: f7f8 faa4 bl 8006950 800e408: 4603 mov r3, r0 800e40a: 9300 str r3, [sp, #0] 800e40c: 2364 movs r3, #100 @ 0x64 800e40e: 2200 movs r2, #0 800e410: f44f 61c0 mov.w r1, #1536 @ 0x600 800e414: 6878 ldr r0, [r7, #4] 800e416: f7ff fddd bl 800dfd4 800e41a: 4603 mov r3, r0 800e41c: 2b00 cmp r3, #0 800e41e: d002 beq.n 800e426 HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; 800e420: 687b ldr r3, [r7, #4] 800e422: 2240 movs r2, #64 @ 0x40 800e424: 661a str r2, [r3, #96] @ 0x60 } } hspi->State = HAL_SPI_STATE_ABORT; 800e426: 687b ldr r3, [r7, #4] 800e428: 2207 movs r2, #7 800e42a: f883 205d strb.w r2, [r3, #93] @ 0x5d } 800e42e: bf00 nop 800e430: 3710 adds r7, #16 800e432: 46bd mov sp, r7 800e434: bd80 pop {r7, pc} 800e436: bf00 nop 800e438: 2000000c .word 0x2000000c 800e43c: 057619f1 .word 0x057619f1 0800e440 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800e440: b580 push {r7, lr} 800e442: b082 sub sp, #8 800e444: af00 add r7, sp, #0 800e446: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800e448: 687b ldr r3, [r7, #4] 800e44a: 2b00 cmp r3, #0 800e44c: d101 bne.n 800e452 { return HAL_ERROR; 800e44e: 2301 movs r3, #1 800e450: e049 b.n 800e4e6 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800e452: 687b ldr r3, [r7, #4] 800e454: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800e458: b2db uxtb r3, r3 800e45a: 2b00 cmp r3, #0 800e45c: d106 bne.n 800e46c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800e45e: 687b ldr r3, [r7, #4] 800e460: 2200 movs r2, #0 800e462: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800e466: 6878 ldr r0, [r7, #4] 800e468: f000 f841 bl 800e4ee #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800e46c: 687b ldr r3, [r7, #4] 800e46e: 2202 movs r2, #2 800e470: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800e474: 687b ldr r3, [r7, #4] 800e476: 681a ldr r2, [r3, #0] 800e478: 687b ldr r3, [r7, #4] 800e47a: 3304 adds r3, #4 800e47c: 4619 mov r1, r3 800e47e: 4610 mov r0, r2 800e480: f000 fb28 bl 800ead4 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800e484: 687b ldr r3, [r7, #4] 800e486: 2201 movs r2, #1 800e488: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800e48c: 687b ldr r3, [r7, #4] 800e48e: 2201 movs r2, #1 800e490: f883 203e strb.w r2, [r3, #62] @ 0x3e 800e494: 687b ldr r3, [r7, #4] 800e496: 2201 movs r2, #1 800e498: f883 203f strb.w r2, [r3, #63] @ 0x3f 800e49c: 687b ldr r3, [r7, #4] 800e49e: 2201 movs r2, #1 800e4a0: f883 2040 strb.w r2, [r3, #64] @ 0x40 800e4a4: 687b ldr r3, [r7, #4] 800e4a6: 2201 movs r2, #1 800e4a8: f883 2041 strb.w r2, [r3, #65] @ 0x41 800e4ac: 687b ldr r3, [r7, #4] 800e4ae: 2201 movs r2, #1 800e4b0: f883 2042 strb.w r2, [r3, #66] @ 0x42 800e4b4: 687b ldr r3, [r7, #4] 800e4b6: 2201 movs r2, #1 800e4b8: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800e4bc: 687b ldr r3, [r7, #4] 800e4be: 2201 movs r2, #1 800e4c0: f883 2044 strb.w r2, [r3, #68] @ 0x44 800e4c4: 687b ldr r3, [r7, #4] 800e4c6: 2201 movs r2, #1 800e4c8: f883 2045 strb.w r2, [r3, #69] @ 0x45 800e4cc: 687b ldr r3, [r7, #4] 800e4ce: 2201 movs r2, #1 800e4d0: f883 2046 strb.w r2, [r3, #70] @ 0x46 800e4d4: 687b ldr r3, [r7, #4] 800e4d6: 2201 movs r2, #1 800e4d8: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800e4dc: 687b ldr r3, [r7, #4] 800e4de: 2201 movs r2, #1 800e4e0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800e4e4: 2300 movs r3, #0 } 800e4e6: 4618 mov r0, r3 800e4e8: 3708 adds r7, #8 800e4ea: 46bd mov sp, r7 800e4ec: bd80 pop {r7, pc} 0800e4ee : * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { 800e4ee: b480 push {r7} 800e4f0: b083 sub sp, #12 800e4f2: af00 add r7, sp, #0 800e4f4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } 800e4f6: bf00 nop 800e4f8: 370c adds r7, #12 800e4fa: 46bd mov sp, r7 800e4fc: f85d 7b04 ldr.w r7, [sp], #4 800e500: 4770 bx lr ... 0800e504 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800e504: b480 push {r7} 800e506: b085 sub sp, #20 800e508: af00 add r7, sp, #0 800e50a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800e50c: 687b ldr r3, [r7, #4] 800e50e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800e512: b2db uxtb r3, r3 800e514: 2b01 cmp r3, #1 800e516: d001 beq.n 800e51c { return HAL_ERROR; 800e518: 2301 movs r3, #1 800e51a: e036 b.n 800e58a } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800e51c: 687b ldr r3, [r7, #4] 800e51e: 2202 movs r2, #2 800e520: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800e524: 687b ldr r3, [r7, #4] 800e526: 681b ldr r3, [r3, #0] 800e528: 68da ldr r2, [r3, #12] 800e52a: 687b ldr r3, [r7, #4] 800e52c: 681b ldr r3, [r3, #0] 800e52e: f042 0201 orr.w r2, r2, #1 800e532: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800e534: 687b ldr r3, [r7, #4] 800e536: 681b ldr r3, [r3, #0] 800e538: 4a17 ldr r2, [pc, #92] @ (800e598 ) 800e53a: 4293 cmp r3, r2 800e53c: d004 beq.n 800e548 800e53e: 687b ldr r3, [r7, #4] 800e540: 681b ldr r3, [r3, #0] 800e542: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e546: d115 bne.n 800e574 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800e548: 687b ldr r3, [r7, #4] 800e54a: 681b ldr r3, [r3, #0] 800e54c: 689a ldr r2, [r3, #8] 800e54e: 4b13 ldr r3, [pc, #76] @ (800e59c ) 800e550: 4013 ands r3, r2 800e552: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800e554: 68fb ldr r3, [r7, #12] 800e556: 2b06 cmp r3, #6 800e558: d015 beq.n 800e586 800e55a: 68fb ldr r3, [r7, #12] 800e55c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e560: d011 beq.n 800e586 { __HAL_TIM_ENABLE(htim); 800e562: 687b ldr r3, [r7, #4] 800e564: 681b ldr r3, [r3, #0] 800e566: 681a ldr r2, [r3, #0] 800e568: 687b ldr r3, [r7, #4] 800e56a: 681b ldr r3, [r3, #0] 800e56c: f042 0201 orr.w r2, r2, #1 800e570: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800e572: e008 b.n 800e586 } } else { __HAL_TIM_ENABLE(htim); 800e574: 687b ldr r3, [r7, #4] 800e576: 681b ldr r3, [r3, #0] 800e578: 681a ldr r2, [r3, #0] 800e57a: 687b ldr r3, [r7, #4] 800e57c: 681b ldr r3, [r3, #0] 800e57e: f042 0201 orr.w r2, r2, #1 800e582: 601a str r2, [r3, #0] 800e584: e000 b.n 800e588 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800e586: bf00 nop } /* Return function status */ return HAL_OK; 800e588: 2300 movs r3, #0 } 800e58a: 4618 mov r0, r3 800e58c: 3714 adds r7, #20 800e58e: 46bd mov sp, r7 800e590: f85d 7b04 ldr.w r7, [sp], #4 800e594: 4770 bx lr 800e596: bf00 nop 800e598: 40012c00 .word 0x40012c00 800e59c: 00010007 .word 0x00010007 0800e5a0 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800e5a0: b580 push {r7, lr} 800e5a2: b082 sub sp, #8 800e5a4: af00 add r7, sp, #0 800e5a6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800e5a8: 687b ldr r3, [r7, #4] 800e5aa: 2b00 cmp r3, #0 800e5ac: d101 bne.n 800e5b2 { return HAL_ERROR; 800e5ae: 2301 movs r3, #1 800e5b0: e049 b.n 800e646 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800e5b2: 687b ldr r3, [r7, #4] 800e5b4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800e5b8: b2db uxtb r3, r3 800e5ba: 2b00 cmp r3, #0 800e5bc: d106 bne.n 800e5cc { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800e5be: 687b ldr r3, [r7, #4] 800e5c0: 2200 movs r2, #0 800e5c2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800e5c6: 6878 ldr r0, [r7, #4] 800e5c8: f7f7 ff08 bl 80063dc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800e5cc: 687b ldr r3, [r7, #4] 800e5ce: 2202 movs r2, #2 800e5d0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800e5d4: 687b ldr r3, [r7, #4] 800e5d6: 681a ldr r2, [r3, #0] 800e5d8: 687b ldr r3, [r7, #4] 800e5da: 3304 adds r3, #4 800e5dc: 4619 mov r1, r3 800e5de: 4610 mov r0, r2 800e5e0: f000 fa78 bl 800ead4 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800e5e4: 687b ldr r3, [r7, #4] 800e5e6: 2201 movs r2, #1 800e5e8: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800e5ec: 687b ldr r3, [r7, #4] 800e5ee: 2201 movs r2, #1 800e5f0: f883 203e strb.w r2, [r3, #62] @ 0x3e 800e5f4: 687b ldr r3, [r7, #4] 800e5f6: 2201 movs r2, #1 800e5f8: f883 203f strb.w r2, [r3, #63] @ 0x3f 800e5fc: 687b ldr r3, [r7, #4] 800e5fe: 2201 movs r2, #1 800e600: f883 2040 strb.w r2, [r3, #64] @ 0x40 800e604: 687b ldr r3, [r7, #4] 800e606: 2201 movs r2, #1 800e608: f883 2041 strb.w r2, [r3, #65] @ 0x41 800e60c: 687b ldr r3, [r7, #4] 800e60e: 2201 movs r2, #1 800e610: f883 2042 strb.w r2, [r3, #66] @ 0x42 800e614: 687b ldr r3, [r7, #4] 800e616: 2201 movs r2, #1 800e618: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800e61c: 687b ldr r3, [r7, #4] 800e61e: 2201 movs r2, #1 800e620: f883 2044 strb.w r2, [r3, #68] @ 0x44 800e624: 687b ldr r3, [r7, #4] 800e626: 2201 movs r2, #1 800e628: f883 2045 strb.w r2, [r3, #69] @ 0x45 800e62c: 687b ldr r3, [r7, #4] 800e62e: 2201 movs r2, #1 800e630: f883 2046 strb.w r2, [r3, #70] @ 0x46 800e634: 687b ldr r3, [r7, #4] 800e636: 2201 movs r2, #1 800e638: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800e63c: 687b ldr r3, [r7, #4] 800e63e: 2201 movs r2, #1 800e640: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800e644: 2300 movs r3, #0 } 800e646: 4618 mov r0, r3 800e648: 3708 adds r7, #8 800e64a: 46bd mov sp, r7 800e64c: bd80 pop {r7, pc} 0800e64e : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800e64e: b580 push {r7, lr} 800e650: b084 sub sp, #16 800e652: af00 add r7, sp, #0 800e654: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800e656: 687b ldr r3, [r7, #4] 800e658: 681b ldr r3, [r3, #0] 800e65a: 68db ldr r3, [r3, #12] 800e65c: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800e65e: 687b ldr r3, [r7, #4] 800e660: 681b ldr r3, [r3, #0] 800e662: 691b ldr r3, [r3, #16] 800e664: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800e666: 68bb ldr r3, [r7, #8] 800e668: f003 0302 and.w r3, r3, #2 800e66c: 2b00 cmp r3, #0 800e66e: d020 beq.n 800e6b2 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800e670: 68fb ldr r3, [r7, #12] 800e672: f003 0302 and.w r3, r3, #2 800e676: 2b00 cmp r3, #0 800e678: d01b beq.n 800e6b2 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800e67a: 687b ldr r3, [r7, #4] 800e67c: 681b ldr r3, [r3, #0] 800e67e: f06f 0202 mvn.w r2, #2 800e682: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800e684: 687b ldr r3, [r7, #4] 800e686: 2201 movs r2, #1 800e688: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800e68a: 687b ldr r3, [r7, #4] 800e68c: 681b ldr r3, [r3, #0] 800e68e: 699b ldr r3, [r3, #24] 800e690: f003 0303 and.w r3, r3, #3 800e694: 2b00 cmp r3, #0 800e696: d003 beq.n 800e6a0 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800e698: 6878 ldr r0, [r7, #4] 800e69a: f000 f9fd bl 800ea98 800e69e: e005 b.n 800e6ac { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800e6a0: 6878 ldr r0, [r7, #4] 800e6a2: f000 f9ef bl 800ea84 HAL_TIM_PWM_PulseFinishedCallback(htim); 800e6a6: 6878 ldr r0, [r7, #4] 800e6a8: f000 fa00 bl 800eaac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800e6ac: 687b ldr r3, [r7, #4] 800e6ae: 2200 movs r2, #0 800e6b0: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800e6b2: 68bb ldr r3, [r7, #8] 800e6b4: f003 0304 and.w r3, r3, #4 800e6b8: 2b00 cmp r3, #0 800e6ba: d020 beq.n 800e6fe { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800e6bc: 68fb ldr r3, [r7, #12] 800e6be: f003 0304 and.w r3, r3, #4 800e6c2: 2b00 cmp r3, #0 800e6c4: d01b beq.n 800e6fe { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800e6c6: 687b ldr r3, [r7, #4] 800e6c8: 681b ldr r3, [r3, #0] 800e6ca: f06f 0204 mvn.w r2, #4 800e6ce: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800e6d0: 687b ldr r3, [r7, #4] 800e6d2: 2202 movs r2, #2 800e6d4: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800e6d6: 687b ldr r3, [r7, #4] 800e6d8: 681b ldr r3, [r3, #0] 800e6da: 699b ldr r3, [r3, #24] 800e6dc: f403 7340 and.w r3, r3, #768 @ 0x300 800e6e0: 2b00 cmp r3, #0 800e6e2: d003 beq.n 800e6ec { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800e6e4: 6878 ldr r0, [r7, #4] 800e6e6: f000 f9d7 bl 800ea98 800e6ea: e005 b.n 800e6f8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800e6ec: 6878 ldr r0, [r7, #4] 800e6ee: f000 f9c9 bl 800ea84 HAL_TIM_PWM_PulseFinishedCallback(htim); 800e6f2: 6878 ldr r0, [r7, #4] 800e6f4: f000 f9da bl 800eaac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800e6f8: 687b ldr r3, [r7, #4] 800e6fa: 2200 movs r2, #0 800e6fc: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800e6fe: 68bb ldr r3, [r7, #8] 800e700: f003 0308 and.w r3, r3, #8 800e704: 2b00 cmp r3, #0 800e706: d020 beq.n 800e74a { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800e708: 68fb ldr r3, [r7, #12] 800e70a: f003 0308 and.w r3, r3, #8 800e70e: 2b00 cmp r3, #0 800e710: d01b beq.n 800e74a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800e712: 687b ldr r3, [r7, #4] 800e714: 681b ldr r3, [r3, #0] 800e716: f06f 0208 mvn.w r2, #8 800e71a: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800e71c: 687b ldr r3, [r7, #4] 800e71e: 2204 movs r2, #4 800e720: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800e722: 687b ldr r3, [r7, #4] 800e724: 681b ldr r3, [r3, #0] 800e726: 69db ldr r3, [r3, #28] 800e728: f003 0303 and.w r3, r3, #3 800e72c: 2b00 cmp r3, #0 800e72e: d003 beq.n 800e738 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800e730: 6878 ldr r0, [r7, #4] 800e732: f000 f9b1 bl 800ea98 800e736: e005 b.n 800e744 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800e738: 6878 ldr r0, [r7, #4] 800e73a: f000 f9a3 bl 800ea84 HAL_TIM_PWM_PulseFinishedCallback(htim); 800e73e: 6878 ldr r0, [r7, #4] 800e740: f000 f9b4 bl 800eaac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800e744: 687b ldr r3, [r7, #4] 800e746: 2200 movs r2, #0 800e748: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800e74a: 68bb ldr r3, [r7, #8] 800e74c: f003 0310 and.w r3, r3, #16 800e750: 2b00 cmp r3, #0 800e752: d020 beq.n 800e796 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800e754: 68fb ldr r3, [r7, #12] 800e756: f003 0310 and.w r3, r3, #16 800e75a: 2b00 cmp r3, #0 800e75c: d01b beq.n 800e796 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800e75e: 687b ldr r3, [r7, #4] 800e760: 681b ldr r3, [r3, #0] 800e762: f06f 0210 mvn.w r2, #16 800e766: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800e768: 687b ldr r3, [r7, #4] 800e76a: 2208 movs r2, #8 800e76c: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800e76e: 687b ldr r3, [r7, #4] 800e770: 681b ldr r3, [r3, #0] 800e772: 69db ldr r3, [r3, #28] 800e774: f403 7340 and.w r3, r3, #768 @ 0x300 800e778: 2b00 cmp r3, #0 800e77a: d003 beq.n 800e784 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800e77c: 6878 ldr r0, [r7, #4] 800e77e: f000 f98b bl 800ea98 800e782: e005 b.n 800e790 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800e784: 6878 ldr r0, [r7, #4] 800e786: f000 f97d bl 800ea84 HAL_TIM_PWM_PulseFinishedCallback(htim); 800e78a: 6878 ldr r0, [r7, #4] 800e78c: f000 f98e bl 800eaac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800e790: 687b ldr r3, [r7, #4] 800e792: 2200 movs r2, #0 800e794: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800e796: 68bb ldr r3, [r7, #8] 800e798: f003 0301 and.w r3, r3, #1 800e79c: 2b00 cmp r3, #0 800e79e: d00c beq.n 800e7ba { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800e7a0: 68fb ldr r3, [r7, #12] 800e7a2: f003 0301 and.w r3, r3, #1 800e7a6: 2b00 cmp r3, #0 800e7a8: d007 beq.n 800e7ba { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800e7aa: 687b ldr r3, [r7, #4] 800e7ac: 681b ldr r3, [r3, #0] 800e7ae: f06f 0201 mvn.w r2, #1 800e7b2: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800e7b4: 6878 ldr r0, [r7, #4] 800e7b6: f7f6 fdc9 bl 800534c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800e7ba: 68bb ldr r3, [r7, #8] 800e7bc: f003 0380 and.w r3, r3, #128 @ 0x80 800e7c0: 2b00 cmp r3, #0 800e7c2: d104 bne.n 800e7ce ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800e7c4: 68bb ldr r3, [r7, #8] 800e7c6: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800e7ca: 2b00 cmp r3, #0 800e7cc: d00c beq.n 800e7e8 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800e7ce: 68fb ldr r3, [r7, #12] 800e7d0: f003 0380 and.w r3, r3, #128 @ 0x80 800e7d4: 2b00 cmp r3, #0 800e7d6: d007 beq.n 800e7e8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800e7d8: 687b ldr r3, [r7, #4] 800e7da: 681b ldr r3, [r3, #0] 800e7dc: f46f 5202 mvn.w r2, #8320 @ 0x2080 800e7e0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800e7e2: 6878 ldr r0, [r7, #4] 800e7e4: f000 fcce bl 800f184 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800e7e8: 68bb ldr r3, [r7, #8] 800e7ea: f403 7380 and.w r3, r3, #256 @ 0x100 800e7ee: 2b00 cmp r3, #0 800e7f0: d00c beq.n 800e80c { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800e7f2: 68fb ldr r3, [r7, #12] 800e7f4: f003 0380 and.w r3, r3, #128 @ 0x80 800e7f8: 2b00 cmp r3, #0 800e7fa: d007 beq.n 800e80c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800e7fc: 687b ldr r3, [r7, #4] 800e7fe: 681b ldr r3, [r3, #0] 800e800: f46f 7280 mvn.w r2, #256 @ 0x100 800e804: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800e806: 6878 ldr r0, [r7, #4] 800e808: f000 fcc6 bl 800f198 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800e80c: 68bb ldr r3, [r7, #8] 800e80e: f003 0340 and.w r3, r3, #64 @ 0x40 800e812: 2b00 cmp r3, #0 800e814: d00c beq.n 800e830 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800e816: 68fb ldr r3, [r7, #12] 800e818: f003 0340 and.w r3, r3, #64 @ 0x40 800e81c: 2b00 cmp r3, #0 800e81e: d007 beq.n 800e830 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800e820: 687b ldr r3, [r7, #4] 800e822: 681b ldr r3, [r3, #0] 800e824: f06f 0240 mvn.w r2, #64 @ 0x40 800e828: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800e82a: 6878 ldr r0, [r7, #4] 800e82c: f000 f948 bl 800eac0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800e830: 68bb ldr r3, [r7, #8] 800e832: f003 0320 and.w r3, r3, #32 800e836: 2b00 cmp r3, #0 800e838: d00c beq.n 800e854 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800e83a: 68fb ldr r3, [r7, #12] 800e83c: f003 0320 and.w r3, r3, #32 800e840: 2b00 cmp r3, #0 800e842: d007 beq.n 800e854 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800e844: 687b ldr r3, [r7, #4] 800e846: 681b ldr r3, [r3, #0] 800e848: f06f 0220 mvn.w r2, #32 800e84c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800e84e: 6878 ldr r0, [r7, #4] 800e850: f000 fc8e bl 800f170 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800e854: bf00 nop 800e856: 3710 adds r7, #16 800e858: 46bd mov sp, r7 800e85a: bd80 pop {r7, pc} 0800e85c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 800e85c: b580 push {r7, lr} 800e85e: b086 sub sp, #24 800e860: af00 add r7, sp, #0 800e862: 60f8 str r0, [r7, #12] 800e864: 60b9 str r1, [r7, #8] 800e866: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800e868: 2300 movs r3, #0 800e86a: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 800e86c: 68fb ldr r3, [r7, #12] 800e86e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800e872: 2b01 cmp r3, #1 800e874: d101 bne.n 800e87a 800e876: 2302 movs r3, #2 800e878: e0ff b.n 800ea7a 800e87a: 68fb ldr r3, [r7, #12] 800e87c: 2201 movs r2, #1 800e87e: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 800e882: 687b ldr r3, [r7, #4] 800e884: 2b14 cmp r3, #20 800e886: f200 80f0 bhi.w 800ea6a 800e88a: a201 add r2, pc, #4 @ (adr r2, 800e890 ) 800e88c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800e890: 0800e8e5 .word 0x0800e8e5 800e894: 0800ea6b .word 0x0800ea6b 800e898: 0800ea6b .word 0x0800ea6b 800e89c: 0800ea6b .word 0x0800ea6b 800e8a0: 0800e925 .word 0x0800e925 800e8a4: 0800ea6b .word 0x0800ea6b 800e8a8: 0800ea6b .word 0x0800ea6b 800e8ac: 0800ea6b .word 0x0800ea6b 800e8b0: 0800e967 .word 0x0800e967 800e8b4: 0800ea6b .word 0x0800ea6b 800e8b8: 0800ea6b .word 0x0800ea6b 800e8bc: 0800ea6b .word 0x0800ea6b 800e8c0: 0800e9a7 .word 0x0800e9a7 800e8c4: 0800ea6b .word 0x0800ea6b 800e8c8: 0800ea6b .word 0x0800ea6b 800e8cc: 0800ea6b .word 0x0800ea6b 800e8d0: 0800e9e9 .word 0x0800e9e9 800e8d4: 0800ea6b .word 0x0800ea6b 800e8d8: 0800ea6b .word 0x0800ea6b 800e8dc: 0800ea6b .word 0x0800ea6b 800e8e0: 0800ea29 .word 0x0800ea29 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 800e8e4: 68fb ldr r3, [r7, #12] 800e8e6: 681b ldr r3, [r3, #0] 800e8e8: 68b9 ldr r1, [r7, #8] 800e8ea: 4618 mov r0, r3 800e8ec: f000 f95c bl 800eba8 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800e8f0: 68fb ldr r3, [r7, #12] 800e8f2: 681b ldr r3, [r3, #0] 800e8f4: 699a ldr r2, [r3, #24] 800e8f6: 68fb ldr r3, [r7, #12] 800e8f8: 681b ldr r3, [r3, #0] 800e8fa: f042 0208 orr.w r2, r2, #8 800e8fe: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800e900: 68fb ldr r3, [r7, #12] 800e902: 681b ldr r3, [r3, #0] 800e904: 699a ldr r2, [r3, #24] 800e906: 68fb ldr r3, [r7, #12] 800e908: 681b ldr r3, [r3, #0] 800e90a: f022 0204 bic.w r2, r2, #4 800e90e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800e910: 68fb ldr r3, [r7, #12] 800e912: 681b ldr r3, [r3, #0] 800e914: 6999 ldr r1, [r3, #24] 800e916: 68bb ldr r3, [r7, #8] 800e918: 691a ldr r2, [r3, #16] 800e91a: 68fb ldr r3, [r7, #12] 800e91c: 681b ldr r3, [r3, #0] 800e91e: 430a orrs r2, r1 800e920: 619a str r2, [r3, #24] break; 800e922: e0a5 b.n 800ea70 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800e924: 68fb ldr r3, [r7, #12] 800e926: 681b ldr r3, [r3, #0] 800e928: 68b9 ldr r1, [r7, #8] 800e92a: 4618 mov r0, r3 800e92c: f000 f9ba bl 800eca4 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800e930: 68fb ldr r3, [r7, #12] 800e932: 681b ldr r3, [r3, #0] 800e934: 699a ldr r2, [r3, #24] 800e936: 68fb ldr r3, [r7, #12] 800e938: 681b ldr r3, [r3, #0] 800e93a: f442 6200 orr.w r2, r2, #2048 @ 0x800 800e93e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800e940: 68fb ldr r3, [r7, #12] 800e942: 681b ldr r3, [r3, #0] 800e944: 699a ldr r2, [r3, #24] 800e946: 68fb ldr r3, [r7, #12] 800e948: 681b ldr r3, [r3, #0] 800e94a: f422 6280 bic.w r2, r2, #1024 @ 0x400 800e94e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800e950: 68fb ldr r3, [r7, #12] 800e952: 681b ldr r3, [r3, #0] 800e954: 6999 ldr r1, [r3, #24] 800e956: 68bb ldr r3, [r7, #8] 800e958: 691b ldr r3, [r3, #16] 800e95a: 021a lsls r2, r3, #8 800e95c: 68fb ldr r3, [r7, #12] 800e95e: 681b ldr r3, [r3, #0] 800e960: 430a orrs r2, r1 800e962: 619a str r2, [r3, #24] break; 800e964: e084 b.n 800ea70 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800e966: 68fb ldr r3, [r7, #12] 800e968: 681b ldr r3, [r3, #0] 800e96a: 68b9 ldr r1, [r7, #8] 800e96c: 4618 mov r0, r3 800e96e: f000 fa15 bl 800ed9c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800e972: 68fb ldr r3, [r7, #12] 800e974: 681b ldr r3, [r3, #0] 800e976: 69da ldr r2, [r3, #28] 800e978: 68fb ldr r3, [r7, #12] 800e97a: 681b ldr r3, [r3, #0] 800e97c: f042 0208 orr.w r2, r2, #8 800e980: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800e982: 68fb ldr r3, [r7, #12] 800e984: 681b ldr r3, [r3, #0] 800e986: 69da ldr r2, [r3, #28] 800e988: 68fb ldr r3, [r7, #12] 800e98a: 681b ldr r3, [r3, #0] 800e98c: f022 0204 bic.w r2, r2, #4 800e990: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 800e992: 68fb ldr r3, [r7, #12] 800e994: 681b ldr r3, [r3, #0] 800e996: 69d9 ldr r1, [r3, #28] 800e998: 68bb ldr r3, [r7, #8] 800e99a: 691a ldr r2, [r3, #16] 800e99c: 68fb ldr r3, [r7, #12] 800e99e: 681b ldr r3, [r3, #0] 800e9a0: 430a orrs r2, r1 800e9a2: 61da str r2, [r3, #28] break; 800e9a4: e064 b.n 800ea70 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800e9a6: 68fb ldr r3, [r7, #12] 800e9a8: 681b ldr r3, [r3, #0] 800e9aa: 68b9 ldr r1, [r7, #8] 800e9ac: 4618 mov r0, r3 800e9ae: f000 fa6f bl 800ee90 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800e9b2: 68fb ldr r3, [r7, #12] 800e9b4: 681b ldr r3, [r3, #0] 800e9b6: 69da ldr r2, [r3, #28] 800e9b8: 68fb ldr r3, [r7, #12] 800e9ba: 681b ldr r3, [r3, #0] 800e9bc: f442 6200 orr.w r2, r2, #2048 @ 0x800 800e9c0: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800e9c2: 68fb ldr r3, [r7, #12] 800e9c4: 681b ldr r3, [r3, #0] 800e9c6: 69da ldr r2, [r3, #28] 800e9c8: 68fb ldr r3, [r7, #12] 800e9ca: 681b ldr r3, [r3, #0] 800e9cc: f422 6280 bic.w r2, r2, #1024 @ 0x400 800e9d0: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800e9d2: 68fb ldr r3, [r7, #12] 800e9d4: 681b ldr r3, [r3, #0] 800e9d6: 69d9 ldr r1, [r3, #28] 800e9d8: 68bb ldr r3, [r7, #8] 800e9da: 691b ldr r3, [r3, #16] 800e9dc: 021a lsls r2, r3, #8 800e9de: 68fb ldr r3, [r7, #12] 800e9e0: 681b ldr r3, [r3, #0] 800e9e2: 430a orrs r2, r1 800e9e4: 61da str r2, [r3, #28] break; 800e9e6: e043 b.n 800ea70 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 800e9e8: 68fb ldr r3, [r7, #12] 800e9ea: 681b ldr r3, [r3, #0] 800e9ec: 68b9 ldr r1, [r7, #8] 800e9ee: 4618 mov r0, r3 800e9f0: f000 faac bl 800ef4c /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 800e9f4: 68fb ldr r3, [r7, #12] 800e9f6: 681b ldr r3, [r3, #0] 800e9f8: 6d5a ldr r2, [r3, #84] @ 0x54 800e9fa: 68fb ldr r3, [r7, #12] 800e9fc: 681b ldr r3, [r3, #0] 800e9fe: f042 0208 orr.w r2, r2, #8 800ea02: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 800ea04: 68fb ldr r3, [r7, #12] 800ea06: 681b ldr r3, [r3, #0] 800ea08: 6d5a ldr r2, [r3, #84] @ 0x54 800ea0a: 68fb ldr r3, [r7, #12] 800ea0c: 681b ldr r3, [r3, #0] 800ea0e: f022 0204 bic.w r2, r2, #4 800ea12: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800ea14: 68fb ldr r3, [r7, #12] 800ea16: 681b ldr r3, [r3, #0] 800ea18: 6d59 ldr r1, [r3, #84] @ 0x54 800ea1a: 68bb ldr r3, [r7, #8] 800ea1c: 691a ldr r2, [r3, #16] 800ea1e: 68fb ldr r3, [r7, #12] 800ea20: 681b ldr r3, [r3, #0] 800ea22: 430a orrs r2, r1 800ea24: 655a str r2, [r3, #84] @ 0x54 break; 800ea26: e023 b.n 800ea70 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 800ea28: 68fb ldr r3, [r7, #12] 800ea2a: 681b ldr r3, [r3, #0] 800ea2c: 68b9 ldr r1, [r7, #8] 800ea2e: 4618 mov r0, r3 800ea30: f000 fae4 bl 800effc /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800ea34: 68fb ldr r3, [r7, #12] 800ea36: 681b ldr r3, [r3, #0] 800ea38: 6d5a ldr r2, [r3, #84] @ 0x54 800ea3a: 68fb ldr r3, [r7, #12] 800ea3c: 681b ldr r3, [r3, #0] 800ea3e: f442 6200 orr.w r2, r2, #2048 @ 0x800 800ea42: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 800ea44: 68fb ldr r3, [r7, #12] 800ea46: 681b ldr r3, [r3, #0] 800ea48: 6d5a ldr r2, [r3, #84] @ 0x54 800ea4a: 68fb ldr r3, [r7, #12] 800ea4c: 681b ldr r3, [r3, #0] 800ea4e: f422 6280 bic.w r2, r2, #1024 @ 0x400 800ea52: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800ea54: 68fb ldr r3, [r7, #12] 800ea56: 681b ldr r3, [r3, #0] 800ea58: 6d59 ldr r1, [r3, #84] @ 0x54 800ea5a: 68bb ldr r3, [r7, #8] 800ea5c: 691b ldr r3, [r3, #16] 800ea5e: 021a lsls r2, r3, #8 800ea60: 68fb ldr r3, [r7, #12] 800ea62: 681b ldr r3, [r3, #0] 800ea64: 430a orrs r2, r1 800ea66: 655a str r2, [r3, #84] @ 0x54 break; 800ea68: e002 b.n 800ea70 } default: status = HAL_ERROR; 800ea6a: 2301 movs r3, #1 800ea6c: 75fb strb r3, [r7, #23] break; 800ea6e: bf00 nop } __HAL_UNLOCK(htim); 800ea70: 68fb ldr r3, [r7, #12] 800ea72: 2200 movs r2, #0 800ea74: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800ea78: 7dfb ldrb r3, [r7, #23] } 800ea7a: 4618 mov r0, r3 800ea7c: 3718 adds r7, #24 800ea7e: 46bd mov sp, r7 800ea80: bd80 pop {r7, pc} 800ea82: bf00 nop 0800ea84 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800ea84: b480 push {r7} 800ea86: b083 sub sp, #12 800ea88: af00 add r7, sp, #0 800ea8a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800ea8c: bf00 nop 800ea8e: 370c adds r7, #12 800ea90: 46bd mov sp, r7 800ea92: f85d 7b04 ldr.w r7, [sp], #4 800ea96: 4770 bx lr 0800ea98 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800ea98: b480 push {r7} 800ea9a: b083 sub sp, #12 800ea9c: af00 add r7, sp, #0 800ea9e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800eaa0: bf00 nop 800eaa2: 370c adds r7, #12 800eaa4: 46bd mov sp, r7 800eaa6: f85d 7b04 ldr.w r7, [sp], #4 800eaaa: 4770 bx lr 0800eaac : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800eaac: b480 push {r7} 800eaae: b083 sub sp, #12 800eab0: af00 add r7, sp, #0 800eab2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 800eab4: bf00 nop 800eab6: 370c adds r7, #12 800eab8: 46bd mov sp, r7 800eaba: f85d 7b04 ldr.w r7, [sp], #4 800eabe: 4770 bx lr 0800eac0 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800eac0: b480 push {r7} 800eac2: b083 sub sp, #12 800eac4: af00 add r7, sp, #0 800eac6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800eac8: bf00 nop 800eaca: 370c adds r7, #12 800eacc: 46bd mov sp, r7 800eace: f85d 7b04 ldr.w r7, [sp], #4 800ead2: 4770 bx lr 0800ead4 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 800ead4: b480 push {r7} 800ead6: b085 sub sp, #20 800ead8: af00 add r7, sp, #0 800eada: 6078 str r0, [r7, #4] 800eadc: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800eade: 687b ldr r3, [r7, #4] 800eae0: 681b ldr r3, [r3, #0] 800eae2: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800eae4: 687b ldr r3, [r7, #4] 800eae6: 4a2d ldr r2, [pc, #180] @ (800eb9c ) 800eae8: 4293 cmp r3, r2 800eaea: d003 beq.n 800eaf4 800eaec: 687b ldr r3, [r7, #4] 800eaee: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800eaf2: d108 bne.n 800eb06 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800eaf4: 68fb ldr r3, [r7, #12] 800eaf6: f023 0370 bic.w r3, r3, #112 @ 0x70 800eafa: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 800eafc: 683b ldr r3, [r7, #0] 800eafe: 685b ldr r3, [r3, #4] 800eb00: 68fa ldr r2, [r7, #12] 800eb02: 4313 orrs r3, r2 800eb04: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800eb06: 687b ldr r3, [r7, #4] 800eb08: 4a24 ldr r2, [pc, #144] @ (800eb9c ) 800eb0a: 4293 cmp r3, r2 800eb0c: d00b beq.n 800eb26 800eb0e: 687b ldr r3, [r7, #4] 800eb10: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800eb14: d007 beq.n 800eb26 800eb16: 687b ldr r3, [r7, #4] 800eb18: 4a21 ldr r2, [pc, #132] @ (800eba0 ) 800eb1a: 4293 cmp r3, r2 800eb1c: d003 beq.n 800eb26 800eb1e: 687b ldr r3, [r7, #4] 800eb20: 4a20 ldr r2, [pc, #128] @ (800eba4 ) 800eb22: 4293 cmp r3, r2 800eb24: d108 bne.n 800eb38 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800eb26: 68fb ldr r3, [r7, #12] 800eb28: f423 7340 bic.w r3, r3, #768 @ 0x300 800eb2c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800eb2e: 683b ldr r3, [r7, #0] 800eb30: 68db ldr r3, [r3, #12] 800eb32: 68fa ldr r2, [r7, #12] 800eb34: 4313 orrs r3, r2 800eb36: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800eb38: 68fb ldr r3, [r7, #12] 800eb3a: f023 0280 bic.w r2, r3, #128 @ 0x80 800eb3e: 683b ldr r3, [r7, #0] 800eb40: 695b ldr r3, [r3, #20] 800eb42: 4313 orrs r3, r2 800eb44: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800eb46: 683b ldr r3, [r7, #0] 800eb48: 689a ldr r2, [r3, #8] 800eb4a: 687b ldr r3, [r7, #4] 800eb4c: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800eb4e: 683b ldr r3, [r7, #0] 800eb50: 681a ldr r2, [r3, #0] 800eb52: 687b ldr r3, [r7, #4] 800eb54: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800eb56: 687b ldr r3, [r7, #4] 800eb58: 4a10 ldr r2, [pc, #64] @ (800eb9c ) 800eb5a: 4293 cmp r3, r2 800eb5c: d007 beq.n 800eb6e 800eb5e: 687b ldr r3, [r7, #4] 800eb60: 4a0f ldr r2, [pc, #60] @ (800eba0 ) 800eb62: 4293 cmp r3, r2 800eb64: d003 beq.n 800eb6e 800eb66: 687b ldr r3, [r7, #4] 800eb68: 4a0e ldr r2, [pc, #56] @ (800eba4 ) 800eb6a: 4293 cmp r3, r2 800eb6c: d103 bne.n 800eb76 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800eb6e: 683b ldr r3, [r7, #0] 800eb70: 691a ldr r2, [r3, #16] 800eb72: 687b ldr r3, [r7, #4] 800eb74: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 800eb76: 687b ldr r3, [r7, #4] 800eb78: 681b ldr r3, [r3, #0] 800eb7a: f043 0204 orr.w r2, r3, #4 800eb7e: 687b ldr r3, [r7, #4] 800eb80: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800eb82: 687b ldr r3, [r7, #4] 800eb84: 2201 movs r2, #1 800eb86: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 800eb88: 687b ldr r3, [r7, #4] 800eb8a: 68fa ldr r2, [r7, #12] 800eb8c: 601a str r2, [r3, #0] } 800eb8e: bf00 nop 800eb90: 3714 adds r7, #20 800eb92: 46bd mov sp, r7 800eb94: f85d 7b04 ldr.w r7, [sp], #4 800eb98: 4770 bx lr 800eb9a: bf00 nop 800eb9c: 40012c00 .word 0x40012c00 800eba0: 40014400 .word 0x40014400 800eba4: 40014800 .word 0x40014800 0800eba8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800eba8: b480 push {r7} 800ebaa: b087 sub sp, #28 800ebac: af00 add r7, sp, #0 800ebae: 6078 str r0, [r7, #4] 800ebb0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ebb2: 687b ldr r3, [r7, #4] 800ebb4: 6a1b ldr r3, [r3, #32] 800ebb6: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 800ebb8: 687b ldr r3, [r7, #4] 800ebba: 6a1b ldr r3, [r3, #32] 800ebbc: f023 0201 bic.w r2, r3, #1 800ebc0: 687b ldr r3, [r7, #4] 800ebc2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ebc4: 687b ldr r3, [r7, #4] 800ebc6: 685b ldr r3, [r3, #4] 800ebc8: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800ebca: 687b ldr r3, [r7, #4] 800ebcc: 699b ldr r3, [r3, #24] 800ebce: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800ebd0: 68fb ldr r3, [r7, #12] 800ebd2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ebd6: f023 0370 bic.w r3, r3, #112 @ 0x70 800ebda: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 800ebdc: 68fb ldr r3, [r7, #12] 800ebde: f023 0303 bic.w r3, r3, #3 800ebe2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800ebe4: 683b ldr r3, [r7, #0] 800ebe6: 681b ldr r3, [r3, #0] 800ebe8: 68fa ldr r2, [r7, #12] 800ebea: 4313 orrs r3, r2 800ebec: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800ebee: 697b ldr r3, [r7, #20] 800ebf0: f023 0302 bic.w r3, r3, #2 800ebf4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800ebf6: 683b ldr r3, [r7, #0] 800ebf8: 689b ldr r3, [r3, #8] 800ebfa: 697a ldr r2, [r7, #20] 800ebfc: 4313 orrs r3, r2 800ebfe: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 800ec00: 687b ldr r3, [r7, #4] 800ec02: 4a25 ldr r2, [pc, #148] @ (800ec98 ) 800ec04: 4293 cmp r3, r2 800ec06: d007 beq.n 800ec18 800ec08: 687b ldr r3, [r7, #4] 800ec0a: 4a24 ldr r2, [pc, #144] @ (800ec9c ) 800ec0c: 4293 cmp r3, r2 800ec0e: d003 beq.n 800ec18 800ec10: 687b ldr r3, [r7, #4] 800ec12: 4a23 ldr r2, [pc, #140] @ (800eca0 ) 800ec14: 4293 cmp r3, r2 800ec16: d10e bne.n 800ec36 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 1N: Reset the CC1NE Bit */ TIMx->CCER &= ~TIM_CCER_CC1NE; 800ec18: 687b ldr r3, [r7, #4] 800ec1a: 6a1b ldr r3, [r3, #32] 800ec1c: f023 0204 bic.w r2, r3, #4 800ec20: 687b ldr r3, [r7, #4] 800ec22: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 800ec24: 697b ldr r3, [r7, #20] 800ec26: f023 0308 bic.w r3, r3, #8 800ec2a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 800ec2c: 683b ldr r3, [r7, #0] 800ec2e: 68db ldr r3, [r3, #12] 800ec30: 697a ldr r2, [r7, #20] 800ec32: 4313 orrs r3, r2 800ec34: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ec36: 687b ldr r3, [r7, #4] 800ec38: 4a17 ldr r2, [pc, #92] @ (800ec98 ) 800ec3a: 4293 cmp r3, r2 800ec3c: d007 beq.n 800ec4e 800ec3e: 687b ldr r3, [r7, #4] 800ec40: 4a17 ldr r2, [pc, #92] @ (800eca0 ) 800ec42: 4293 cmp r3, r2 800ec44: d003 beq.n 800ec4e 800ec46: 687b ldr r3, [r7, #4] 800ec48: 4a14 ldr r2, [pc, #80] @ (800ec9c ) 800ec4a: 4293 cmp r3, r2 800ec4c: d111 bne.n 800ec72 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800ec4e: 693b ldr r3, [r7, #16] 800ec50: f423 7380 bic.w r3, r3, #256 @ 0x100 800ec54: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800ec56: 693b ldr r3, [r7, #16] 800ec58: f423 7300 bic.w r3, r3, #512 @ 0x200 800ec5c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800ec5e: 683b ldr r3, [r7, #0] 800ec60: 695b ldr r3, [r3, #20] 800ec62: 693a ldr r2, [r7, #16] 800ec64: 4313 orrs r3, r2 800ec66: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800ec68: 683b ldr r3, [r7, #0] 800ec6a: 699b ldr r3, [r3, #24] 800ec6c: 693a ldr r2, [r7, #16] 800ec6e: 4313 orrs r3, r2 800ec70: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ec72: 687b ldr r3, [r7, #4] 800ec74: 693a ldr r2, [r7, #16] 800ec76: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800ec78: 687b ldr r3, [r7, #4] 800ec7a: 68fa ldr r2, [r7, #12] 800ec7c: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800ec7e: 683b ldr r3, [r7, #0] 800ec80: 685a ldr r2, [r3, #4] 800ec82: 687b ldr r3, [r7, #4] 800ec84: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800ec86: 687b ldr r3, [r7, #4] 800ec88: 697a ldr r2, [r7, #20] 800ec8a: 621a str r2, [r3, #32] } 800ec8c: bf00 nop 800ec8e: 371c adds r7, #28 800ec90: 46bd mov sp, r7 800ec92: f85d 7b04 ldr.w r7, [sp], #4 800ec96: 4770 bx lr 800ec98: 40012c00 .word 0x40012c00 800ec9c: 40014800 .word 0x40014800 800eca0: 40014400 .word 0x40014400 0800eca4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800eca4: b480 push {r7} 800eca6: b087 sub sp, #28 800eca8: af00 add r7, sp, #0 800ecaa: 6078 str r0, [r7, #4] 800ecac: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ecae: 687b ldr r3, [r7, #4] 800ecb0: 6a1b ldr r3, [r3, #32] 800ecb2: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 800ecb4: 687b ldr r3, [r7, #4] 800ecb6: 6a1b ldr r3, [r3, #32] 800ecb8: f023 0210 bic.w r2, r3, #16 800ecbc: 687b ldr r3, [r7, #4] 800ecbe: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ecc0: 687b ldr r3, [r7, #4] 800ecc2: 685b ldr r3, [r3, #4] 800ecc4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800ecc6: 687b ldr r3, [r7, #4] 800ecc8: 699b ldr r3, [r3, #24] 800ecca: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 800eccc: 68fb ldr r3, [r7, #12] 800ecce: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800ecd2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ecd6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 800ecd8: 68fb ldr r3, [r7, #12] 800ecda: f423 7340 bic.w r3, r3, #768 @ 0x300 800ecde: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800ece0: 683b ldr r3, [r7, #0] 800ece2: 681b ldr r3, [r3, #0] 800ece4: 021b lsls r3, r3, #8 800ece6: 68fa ldr r2, [r7, #12] 800ece8: 4313 orrs r3, r2 800ecea: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 800ecec: 697b ldr r3, [r7, #20] 800ecee: f023 0320 bic.w r3, r3, #32 800ecf2: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 800ecf4: 683b ldr r3, [r7, #0] 800ecf6: 689b ldr r3, [r3, #8] 800ecf8: 011b lsls r3, r3, #4 800ecfa: 697a ldr r2, [r7, #20] 800ecfc: 4313 orrs r3, r2 800ecfe: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800ed00: 687b ldr r3, [r7, #4] 800ed02: 4a23 ldr r2, [pc, #140] @ (800ed90 ) 800ed04: 4293 cmp r3, r2 800ed06: d10f bne.n 800ed28 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 2N: Reset the CC2NE Bit */ TIMx->CCER &= ~TIM_CCER_CC2NE; 800ed08: 687b ldr r3, [r7, #4] 800ed0a: 6a1b ldr r3, [r3, #32] 800ed0c: f023 0240 bic.w r2, r3, #64 @ 0x40 800ed10: 687b ldr r3, [r7, #4] 800ed12: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800ed14: 697b ldr r3, [r7, #20] 800ed16: f023 0380 bic.w r3, r3, #128 @ 0x80 800ed1a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 800ed1c: 683b ldr r3, [r7, #0] 800ed1e: 68db ldr r3, [r3, #12] 800ed20: 011b lsls r3, r3, #4 800ed22: 697a ldr r2, [r7, #20] 800ed24: 4313 orrs r3, r2 800ed26: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ed28: 687b ldr r3, [r7, #4] 800ed2a: 4a19 ldr r2, [pc, #100] @ (800ed90 ) 800ed2c: 4293 cmp r3, r2 800ed2e: d007 beq.n 800ed40 800ed30: 687b ldr r3, [r7, #4] 800ed32: 4a18 ldr r2, [pc, #96] @ (800ed94 ) 800ed34: 4293 cmp r3, r2 800ed36: d003 beq.n 800ed40 800ed38: 687b ldr r3, [r7, #4] 800ed3a: 4a17 ldr r2, [pc, #92] @ (800ed98 ) 800ed3c: 4293 cmp r3, r2 800ed3e: d113 bne.n 800ed68 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 800ed40: 693b ldr r3, [r7, #16] 800ed42: f423 6380 bic.w r3, r3, #1024 @ 0x400 800ed46: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 800ed48: 693b ldr r3, [r7, #16] 800ed4a: f423 6300 bic.w r3, r3, #2048 @ 0x800 800ed4e: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 800ed50: 683b ldr r3, [r7, #0] 800ed52: 695b ldr r3, [r3, #20] 800ed54: 009b lsls r3, r3, #2 800ed56: 693a ldr r2, [r7, #16] 800ed58: 4313 orrs r3, r2 800ed5a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 800ed5c: 683b ldr r3, [r7, #0] 800ed5e: 699b ldr r3, [r3, #24] 800ed60: 009b lsls r3, r3, #2 800ed62: 693a ldr r2, [r7, #16] 800ed64: 4313 orrs r3, r2 800ed66: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ed68: 687b ldr r3, [r7, #4] 800ed6a: 693a ldr r2, [r7, #16] 800ed6c: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800ed6e: 687b ldr r3, [r7, #4] 800ed70: 68fa ldr r2, [r7, #12] 800ed72: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800ed74: 683b ldr r3, [r7, #0] 800ed76: 685a ldr r2, [r3, #4] 800ed78: 687b ldr r3, [r7, #4] 800ed7a: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800ed7c: 687b ldr r3, [r7, #4] 800ed7e: 697a ldr r2, [r7, #20] 800ed80: 621a str r2, [r3, #32] } 800ed82: bf00 nop 800ed84: 371c adds r7, #28 800ed86: 46bd mov sp, r7 800ed88: f85d 7b04 ldr.w r7, [sp], #4 800ed8c: 4770 bx lr 800ed8e: bf00 nop 800ed90: 40012c00 .word 0x40012c00 800ed94: 40014400 .word 0x40014400 800ed98: 40014800 .word 0x40014800 0800ed9c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ed9c: b480 push {r7} 800ed9e: b087 sub sp, #28 800eda0: af00 add r7, sp, #0 800eda2: 6078 str r0, [r7, #4] 800eda4: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800eda6: 687b ldr r3, [r7, #4] 800eda8: 6a1b ldr r3, [r3, #32] 800edaa: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 800edac: 687b ldr r3, [r7, #4] 800edae: 6a1b ldr r3, [r3, #32] 800edb0: f423 7280 bic.w r2, r3, #256 @ 0x100 800edb4: 687b ldr r3, [r7, #4] 800edb6: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800edb8: 687b ldr r3, [r7, #4] 800edba: 685b ldr r3, [r3, #4] 800edbc: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800edbe: 687b ldr r3, [r7, #4] 800edc0: 69db ldr r3, [r3, #28] 800edc2: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 800edc4: 68fb ldr r3, [r7, #12] 800edc6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800edca: f023 0370 bic.w r3, r3, #112 @ 0x70 800edce: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 800edd0: 68fb ldr r3, [r7, #12] 800edd2: f023 0303 bic.w r3, r3, #3 800edd6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800edd8: 683b ldr r3, [r7, #0] 800edda: 681b ldr r3, [r3, #0] 800eddc: 68fa ldr r2, [r7, #12] 800edde: 4313 orrs r3, r2 800ede0: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 800ede2: 697b ldr r3, [r7, #20] 800ede4: f423 7300 bic.w r3, r3, #512 @ 0x200 800ede8: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800edea: 683b ldr r3, [r7, #0] 800edec: 689b ldr r3, [r3, #8] 800edee: 021b lsls r3, r3, #8 800edf0: 697a ldr r2, [r7, #20] 800edf2: 4313 orrs r3, r2 800edf4: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 800edf6: 687b ldr r3, [r7, #4] 800edf8: 4a22 ldr r2, [pc, #136] @ (800ee84 ) 800edfa: 4293 cmp r3, r2 800edfc: d10f bne.n 800ee1e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Disable the Channel 3N: Reset the CC3NE Bit */ TIMx->CCER &= ~TIM_CCER_CC3NE; 800edfe: 687b ldr r3, [r7, #4] 800ee00: 6a1b ldr r3, [r3, #32] 800ee02: f423 6280 bic.w r2, r3, #1024 @ 0x400 800ee06: 687b ldr r3, [r7, #4] 800ee08: 621a str r2, [r3, #32] /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 800ee0a: 697b ldr r3, [r7, #20] 800ee0c: f423 6300 bic.w r3, r3, #2048 @ 0x800 800ee10: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800ee12: 683b ldr r3, [r7, #0] 800ee14: 68db ldr r3, [r3, #12] 800ee16: 021b lsls r3, r3, #8 800ee18: 697a ldr r2, [r7, #20] 800ee1a: 4313 orrs r3, r2 800ee1c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ee1e: 687b ldr r3, [r7, #4] 800ee20: 4a18 ldr r2, [pc, #96] @ (800ee84 ) 800ee22: 4293 cmp r3, r2 800ee24: d007 beq.n 800ee36 800ee26: 687b ldr r3, [r7, #4] 800ee28: 4a17 ldr r2, [pc, #92] @ (800ee88 ) 800ee2a: 4293 cmp r3, r2 800ee2c: d003 beq.n 800ee36 800ee2e: 687b ldr r3, [r7, #4] 800ee30: 4a16 ldr r2, [pc, #88] @ (800ee8c ) 800ee32: 4293 cmp r3, r2 800ee34: d113 bne.n 800ee5e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 800ee36: 693b ldr r3, [r7, #16] 800ee38: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800ee3c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800ee3e: 693b ldr r3, [r7, #16] 800ee40: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800ee44: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 800ee46: 683b ldr r3, [r7, #0] 800ee48: 695b ldr r3, [r3, #20] 800ee4a: 011b lsls r3, r3, #4 800ee4c: 693a ldr r2, [r7, #16] 800ee4e: 4313 orrs r3, r2 800ee50: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800ee52: 683b ldr r3, [r7, #0] 800ee54: 699b ldr r3, [r3, #24] 800ee56: 011b lsls r3, r3, #4 800ee58: 693a ldr r2, [r7, #16] 800ee5a: 4313 orrs r3, r2 800ee5c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ee5e: 687b ldr r3, [r7, #4] 800ee60: 693a ldr r2, [r7, #16] 800ee62: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800ee64: 687b ldr r3, [r7, #4] 800ee66: 68fa ldr r2, [r7, #12] 800ee68: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 800ee6a: 683b ldr r3, [r7, #0] 800ee6c: 685a ldr r2, [r3, #4] 800ee6e: 687b ldr r3, [r7, #4] 800ee70: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800ee72: 687b ldr r3, [r7, #4] 800ee74: 697a ldr r2, [r7, #20] 800ee76: 621a str r2, [r3, #32] } 800ee78: bf00 nop 800ee7a: 371c adds r7, #28 800ee7c: 46bd mov sp, r7 800ee7e: f85d 7b04 ldr.w r7, [sp], #4 800ee82: 4770 bx lr 800ee84: 40012c00 .word 0x40012c00 800ee88: 40014400 .word 0x40014400 800ee8c: 40014800 .word 0x40014800 0800ee90 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ee90: b480 push {r7} 800ee92: b087 sub sp, #28 800ee94: af00 add r7, sp, #0 800ee96: 6078 str r0, [r7, #4] 800ee98: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ee9a: 687b ldr r3, [r7, #4] 800ee9c: 6a1b ldr r3, [r3, #32] 800ee9e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 800eea0: 687b ldr r3, [r7, #4] 800eea2: 6a1b ldr r3, [r3, #32] 800eea4: f423 5280 bic.w r2, r3, #4096 @ 0x1000 800eea8: 687b ldr r3, [r7, #4] 800eeaa: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800eeac: 687b ldr r3, [r7, #4] 800eeae: 685b ldr r3, [r3, #4] 800eeb0: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800eeb2: 687b ldr r3, [r7, #4] 800eeb4: 69db ldr r3, [r3, #28] 800eeb6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 800eeb8: 68fb ldr r3, [r7, #12] 800eeba: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800eebe: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800eec2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 800eec4: 68fb ldr r3, [r7, #12] 800eec6: f423 7340 bic.w r3, r3, #768 @ 0x300 800eeca: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800eecc: 683b ldr r3, [r7, #0] 800eece: 681b ldr r3, [r3, #0] 800eed0: 021b lsls r3, r3, #8 800eed2: 68fa ldr r2, [r7, #12] 800eed4: 4313 orrs r3, r2 800eed6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 800eed8: 693b ldr r3, [r7, #16] 800eeda: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800eede: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 800eee0: 683b ldr r3, [r7, #0] 800eee2: 689b ldr r3, [r3, #8] 800eee4: 031b lsls r3, r3, #12 800eee6: 693a ldr r2, [r7, #16] 800eee8: 4313 orrs r3, r2 800eeea: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800eeec: 687b ldr r3, [r7, #4] 800eeee: 4a14 ldr r2, [pc, #80] @ (800ef40 ) 800eef0: 4293 cmp r3, r2 800eef2: d007 beq.n 800ef04 800eef4: 687b ldr r3, [r7, #4] 800eef6: 4a13 ldr r2, [pc, #76] @ (800ef44 ) 800eef8: 4293 cmp r3, r2 800eefa: d003 beq.n 800ef04 800eefc: 687b ldr r3, [r7, #4] 800eefe: 4a12 ldr r2, [pc, #72] @ (800ef48 ) 800ef00: 4293 cmp r3, r2 800ef02: d109 bne.n 800ef18 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 800ef04: 697b ldr r3, [r7, #20] 800ef06: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800ef0a: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 800ef0c: 683b ldr r3, [r7, #0] 800ef0e: 695b ldr r3, [r3, #20] 800ef10: 019b lsls r3, r3, #6 800ef12: 697a ldr r2, [r7, #20] 800ef14: 4313 orrs r3, r2 800ef16: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ef18: 687b ldr r3, [r7, #4] 800ef1a: 697a ldr r2, [r7, #20] 800ef1c: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800ef1e: 687b ldr r3, [r7, #4] 800ef20: 68fa ldr r2, [r7, #12] 800ef22: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 800ef24: 683b ldr r3, [r7, #0] 800ef26: 685a ldr r2, [r3, #4] 800ef28: 687b ldr r3, [r7, #4] 800ef2a: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800ef2c: 687b ldr r3, [r7, #4] 800ef2e: 693a ldr r2, [r7, #16] 800ef30: 621a str r2, [r3, #32] } 800ef32: bf00 nop 800ef34: 371c adds r7, #28 800ef36: 46bd mov sp, r7 800ef38: f85d 7b04 ldr.w r7, [sp], #4 800ef3c: 4770 bx lr 800ef3e: bf00 nop 800ef40: 40012c00 .word 0x40012c00 800ef44: 40014400 .word 0x40014400 800ef48: 40014800 .word 0x40014800 0800ef4c : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ef4c: b480 push {r7} 800ef4e: b087 sub sp, #28 800ef50: af00 add r7, sp, #0 800ef52: 6078 str r0, [r7, #4] 800ef54: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ef56: 687b ldr r3, [r7, #4] 800ef58: 6a1b ldr r3, [r3, #32] 800ef5a: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 800ef5c: 687b ldr r3, [r7, #4] 800ef5e: 6a1b ldr r3, [r3, #32] 800ef60: f423 3280 bic.w r2, r3, #65536 @ 0x10000 800ef64: 687b ldr r3, [r7, #4] 800ef66: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ef68: 687b ldr r3, [r7, #4] 800ef6a: 685b ldr r3, [r3, #4] 800ef6c: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 800ef6e: 687b ldr r3, [r7, #4] 800ef70: 6d5b ldr r3, [r3, #84] @ 0x54 800ef72: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 800ef74: 68fb ldr r3, [r7, #12] 800ef76: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ef7a: f023 0370 bic.w r3, r3, #112 @ 0x70 800ef7e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800ef80: 683b ldr r3, [r7, #0] 800ef82: 681b ldr r3, [r3, #0] 800ef84: 68fa ldr r2, [r7, #12] 800ef86: 4313 orrs r3, r2 800ef88: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 800ef8a: 693b ldr r3, [r7, #16] 800ef8c: f423 3300 bic.w r3, r3, #131072 @ 0x20000 800ef90: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 800ef92: 683b ldr r3, [r7, #0] 800ef94: 689b ldr r3, [r3, #8] 800ef96: 041b lsls r3, r3, #16 800ef98: 693a ldr r2, [r7, #16] 800ef9a: 4313 orrs r3, r2 800ef9c: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ef9e: 687b ldr r3, [r7, #4] 800efa0: 4a13 ldr r2, [pc, #76] @ (800eff0 ) 800efa2: 4293 cmp r3, r2 800efa4: d007 beq.n 800efb6 800efa6: 687b ldr r3, [r7, #4] 800efa8: 4a12 ldr r2, [pc, #72] @ (800eff4 ) 800efaa: 4293 cmp r3, r2 800efac: d003 beq.n 800efb6 800efae: 687b ldr r3, [r7, #4] 800efb0: 4a11 ldr r2, [pc, #68] @ (800eff8 ) 800efb2: 4293 cmp r3, r2 800efb4: d109 bne.n 800efca { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 800efb6: 697b ldr r3, [r7, #20] 800efb8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800efbc: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 800efbe: 683b ldr r3, [r7, #0] 800efc0: 695b ldr r3, [r3, #20] 800efc2: 021b lsls r3, r3, #8 800efc4: 697a ldr r2, [r7, #20] 800efc6: 4313 orrs r3, r2 800efc8: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800efca: 687b ldr r3, [r7, #4] 800efcc: 697a ldr r2, [r7, #20] 800efce: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 800efd0: 687b ldr r3, [r7, #4] 800efd2: 68fa ldr r2, [r7, #12] 800efd4: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 800efd6: 683b ldr r3, [r7, #0] 800efd8: 685a ldr r2, [r3, #4] 800efda: 687b ldr r3, [r7, #4] 800efdc: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800efde: 687b ldr r3, [r7, #4] 800efe0: 693a ldr r2, [r7, #16] 800efe2: 621a str r2, [r3, #32] } 800efe4: bf00 nop 800efe6: 371c adds r7, #28 800efe8: 46bd mov sp, r7 800efea: f85d 7b04 ldr.w r7, [sp], #4 800efee: 4770 bx lr 800eff0: 40012c00 .word 0x40012c00 800eff4: 40014400 .word 0x40014400 800eff8: 40014800 .word 0x40014800 0800effc : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800effc: b480 push {r7} 800effe: b087 sub sp, #28 800f000: af00 add r7, sp, #0 800f002: 6078 str r0, [r7, #4] 800f004: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800f006: 687b ldr r3, [r7, #4] 800f008: 6a1b ldr r3, [r3, #32] 800f00a: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 800f00c: 687b ldr r3, [r7, #4] 800f00e: 6a1b ldr r3, [r3, #32] 800f010: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 800f014: 687b ldr r3, [r7, #4] 800f016: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800f018: 687b ldr r3, [r7, #4] 800f01a: 685b ldr r3, [r3, #4] 800f01c: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 800f01e: 687b ldr r3, [r7, #4] 800f020: 6d5b ldr r3, [r3, #84] @ 0x54 800f022: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 800f024: 68fb ldr r3, [r7, #12] 800f026: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800f02a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f02e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800f030: 683b ldr r3, [r7, #0] 800f032: 681b ldr r3, [r3, #0] 800f034: 021b lsls r3, r3, #8 800f036: 68fa ldr r2, [r7, #12] 800f038: 4313 orrs r3, r2 800f03a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 800f03c: 693b ldr r3, [r7, #16] 800f03e: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 800f042: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 800f044: 683b ldr r3, [r7, #0] 800f046: 689b ldr r3, [r3, #8] 800f048: 051b lsls r3, r3, #20 800f04a: 693a ldr r2, [r7, #16] 800f04c: 4313 orrs r3, r2 800f04e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800f050: 687b ldr r3, [r7, #4] 800f052: 4a14 ldr r2, [pc, #80] @ (800f0a4 ) 800f054: 4293 cmp r3, r2 800f056: d007 beq.n 800f068 800f058: 687b ldr r3, [r7, #4] 800f05a: 4a13 ldr r2, [pc, #76] @ (800f0a8 ) 800f05c: 4293 cmp r3, r2 800f05e: d003 beq.n 800f068 800f060: 687b ldr r3, [r7, #4] 800f062: 4a12 ldr r2, [pc, #72] @ (800f0ac ) 800f064: 4293 cmp r3, r2 800f066: d109 bne.n 800f07c { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 800f068: 697b ldr r3, [r7, #20] 800f06a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800f06e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 800f070: 683b ldr r3, [r7, #0] 800f072: 695b ldr r3, [r3, #20] 800f074: 029b lsls r3, r3, #10 800f076: 697a ldr r2, [r7, #20] 800f078: 4313 orrs r3, r2 800f07a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800f07c: 687b ldr r3, [r7, #4] 800f07e: 697a ldr r2, [r7, #20] 800f080: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 800f082: 687b ldr r3, [r7, #4] 800f084: 68fa ldr r2, [r7, #12] 800f086: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 800f088: 683b ldr r3, [r7, #0] 800f08a: 685a ldr r2, [r3, #4] 800f08c: 687b ldr r3, [r7, #4] 800f08e: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800f090: 687b ldr r3, [r7, #4] 800f092: 693a ldr r2, [r7, #16] 800f094: 621a str r2, [r3, #32] } 800f096: bf00 nop 800f098: 371c adds r7, #28 800f09a: 46bd mov sp, r7 800f09c: f85d 7b04 ldr.w r7, [sp], #4 800f0a0: 4770 bx lr 800f0a2: bf00 nop 800f0a4: 40012c00 .word 0x40012c00 800f0a8: 40014400 .word 0x40014400 800f0ac: 40014800 .word 0x40014800 0800f0b0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 800f0b0: b480 push {r7} 800f0b2: b085 sub sp, #20 800f0b4: af00 add r7, sp, #0 800f0b6: 6078 str r0, [r7, #4] 800f0b8: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800f0ba: 687b ldr r3, [r7, #4] 800f0bc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800f0c0: 2b01 cmp r3, #1 800f0c2: d101 bne.n 800f0c8 800f0c4: 2302 movs r3, #2 800f0c6: e04a b.n 800f15e 800f0c8: 687b ldr r3, [r7, #4] 800f0ca: 2201 movs r2, #1 800f0cc: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 800f0d0: 687b ldr r3, [r7, #4] 800f0d2: 2202 movs r2, #2 800f0d4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800f0d8: 687b ldr r3, [r7, #4] 800f0da: 681b ldr r3, [r3, #0] 800f0dc: 685b ldr r3, [r3, #4] 800f0de: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 800f0e0: 687b ldr r3, [r7, #4] 800f0e2: 681b ldr r3, [r3, #0] 800f0e4: 689b ldr r3, [r3, #8] 800f0e6: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800f0e8: 687b ldr r3, [r7, #4] 800f0ea: 681b ldr r3, [r3, #0] 800f0ec: 4a1f ldr r2, [pc, #124] @ (800f16c ) 800f0ee: 4293 cmp r3, r2 800f0f0: d108 bne.n 800f104 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 800f0f2: 68fb ldr r3, [r7, #12] 800f0f4: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 800f0f8: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 800f0fa: 683b ldr r3, [r7, #0] 800f0fc: 685b ldr r3, [r3, #4] 800f0fe: 68fa ldr r2, [r7, #12] 800f100: 4313 orrs r3, r2 800f102: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800f104: 68fb ldr r3, [r7, #12] 800f106: f023 0370 bic.w r3, r3, #112 @ 0x70 800f10a: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800f10c: 683b ldr r3, [r7, #0] 800f10e: 681b ldr r3, [r3, #0] 800f110: 68fa ldr r2, [r7, #12] 800f112: 4313 orrs r3, r2 800f114: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800f116: 687b ldr r3, [r7, #4] 800f118: 681b ldr r3, [r3, #0] 800f11a: 68fa ldr r2, [r7, #12] 800f11c: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f11e: 687b ldr r3, [r7, #4] 800f120: 681b ldr r3, [r3, #0] 800f122: 4a12 ldr r2, [pc, #72] @ (800f16c ) 800f124: 4293 cmp r3, r2 800f126: d004 beq.n 800f132 800f128: 687b ldr r3, [r7, #4] 800f12a: 681b ldr r3, [r3, #0] 800f12c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f130: d10c bne.n 800f14c { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 800f132: 68bb ldr r3, [r7, #8] 800f134: f023 0380 bic.w r3, r3, #128 @ 0x80 800f138: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800f13a: 683b ldr r3, [r7, #0] 800f13c: 689b ldr r3, [r3, #8] 800f13e: 68ba ldr r2, [r7, #8] 800f140: 4313 orrs r3, r2 800f142: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800f144: 687b ldr r3, [r7, #4] 800f146: 681b ldr r3, [r3, #0] 800f148: 68ba ldr r2, [r7, #8] 800f14a: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 800f14c: 687b ldr r3, [r7, #4] 800f14e: 2201 movs r2, #1 800f150: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800f154: 687b ldr r3, [r7, #4] 800f156: 2200 movs r2, #0 800f158: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 800f15c: 2300 movs r3, #0 } 800f15e: 4618 mov r0, r3 800f160: 3714 adds r7, #20 800f162: 46bd mov sp, r7 800f164: f85d 7b04 ldr.w r7, [sp], #4 800f168: 4770 bx lr 800f16a: bf00 nop 800f16c: 40012c00 .word 0x40012c00 0800f170 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 800f170: b480 push {r7} 800f172: b083 sub sp, #12 800f174: af00 add r7, sp, #0 800f176: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 800f178: bf00 nop 800f17a: 370c adds r7, #12 800f17c: 46bd mov sp, r7 800f17e: f85d 7b04 ldr.w r7, [sp], #4 800f182: 4770 bx lr 0800f184 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 800f184: b480 push {r7} 800f186: b083 sub sp, #12 800f188: af00 add r7, sp, #0 800f18a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 800f18c: bf00 nop 800f18e: 370c adds r7, #12 800f190: 46bd mov sp, r7 800f192: f85d 7b04 ldr.w r7, [sp], #4 800f196: 4770 bx lr 0800f198 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 800f198: b480 push {r7} 800f19a: b083 sub sp, #12 800f19c: af00 add r7, sp, #0 800f19e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 800f1a0: bf00 nop 800f1a2: 370c adds r7, #12 800f1a4: 46bd mov sp, r7 800f1a6: f85d 7b04 ldr.w r7, [sp], #4 800f1aa: 4770 bx lr 0800f1ac : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { 800f1ac: b480 push {r7} 800f1ae: b085 sub sp, #20 800f1b0: af00 add r7, sp, #0 800f1b2: 6078 str r0, [r7, #4] uint32_t winterruptmask; /* Clear pending interrupts */ USBx->ISTR = 0U; 800f1b4: 687b ldr r3, [r7, #4] 800f1b6: 2200 movs r2, #0 800f1b8: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | 800f1bc: f64b 7380 movw r3, #49024 @ 0xbf80 800f1c0: 60fb str r3, [r7, #12] USB_CNTR_SUSPM | USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Set interrupt mask */ USBx->CNTR = (uint16_t)winterruptmask; 800f1c2: 68fb ldr r3, [r7, #12] 800f1c4: b29a uxth r2, r3 800f1c6: 687b ldr r3, [r7, #4] 800f1c8: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 return HAL_OK; 800f1cc: 2300 movs r3, #0 } 800f1ce: 4618 mov r0, r3 800f1d0: 3714 adds r7, #20 800f1d2: 46bd mov sp, r7 800f1d4: f85d 7b04 ldr.w r7, [sp], #4 800f1d8: 4770 bx lr 0800f1da : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { 800f1da: b480 push {r7} 800f1dc: b085 sub sp, #20 800f1de: af00 add r7, sp, #0 800f1e0: 6078 str r0, [r7, #4] uint32_t winterruptmask; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | 800f1e2: f64b 7380 movw r3, #49024 @ 0xbf80 800f1e6: 60fb str r3, [r7, #12] USB_CNTR_SUSPM | USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Clear interrupt mask */ USBx->CNTR &= (uint16_t)(~winterruptmask); 800f1e8: 687b ldr r3, [r7, #4] 800f1ea: f8b3 3040 ldrh.w r3, [r3, #64] @ 0x40 800f1ee: b29a uxth r2, r3 800f1f0: 68fb ldr r3, [r7, #12] 800f1f2: b29b uxth r3, r3 800f1f4: 43db mvns r3, r3 800f1f6: b29b uxth r3, r3 800f1f8: 4013 ands r3, r2 800f1fa: b29a uxth r2, r3 800f1fc: 687b ldr r3, [r7, #4] 800f1fe: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 return HAL_OK; 800f202: 2300 movs r3, #0 } 800f204: 4618 mov r0, r3 800f206: 3714 adds r7, #20 800f208: 46bd mov sp, r7 800f20a: f85d 7b04 ldr.w r7, [sp], #4 800f20e: 4770 bx lr 0800f210 : * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { 800f210: b480 push {r7} 800f212: b085 sub sp, #20 800f214: af00 add r7, sp, #0 800f216: 60f8 str r0, [r7, #12] 800f218: 1d3b adds r3, r7, #4 800f21a: e883 0006 stmia.w r3, {r1, r2} /* Prevent unused argument(s) compilation warning */ UNUSED(cfg); /* Init Device */ /* CNTR_FRES = 1 */ USBx->CNTR = (uint16_t)USB_CNTR_FRES; 800f21e: 68fb ldr r3, [r7, #12] 800f220: 2201 movs r2, #1 800f222: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* CNTR_FRES = 0 */ USBx->CNTR = 0U; 800f226: 68fb ldr r3, [r7, #12] 800f228: 2200 movs r2, #0 800f22a: f8a3 2040 strh.w r2, [r3, #64] @ 0x40 /* Clear pending interrupts */ USBx->ISTR = 0U; 800f22e: 68fb ldr r3, [r7, #12] 800f230: 2200 movs r2, #0 800f232: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; 800f236: 68fb ldr r3, [r7, #12] 800f238: 2200 movs r2, #0 800f23a: f8a3 2050 strh.w r2, [r3, #80] @ 0x50 return HAL_OK; 800f23e: 2300 movs r3, #0 } 800f240: 4618 mov r0, r3 800f242: 3714 adds r7, #20 800f244: 46bd mov sp, r7 800f246: f85d 7b04 ldr.w r7, [sp], #4 800f24a: 4770 bx lr 0800f24c : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800f24c: b480 push {r7} 800f24e: b0a7 sub sp, #156 @ 0x9c 800f250: af00 add r7, sp, #0 800f252: 6078 str r0, [r7, #4] 800f254: 6039 str r1, [r7, #0] HAL_StatusTypeDef ret = HAL_OK; 800f256: 2300 movs r3, #0 800f258: f887 3097 strb.w r3, [r7, #151] @ 0x97 uint16_t wEpRegVal; wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; 800f25c: 687a ldr r2, [r7, #4] 800f25e: 683b ldr r3, [r7, #0] 800f260: 781b ldrb r3, [r3, #0] 800f262: 009b lsls r3, r3, #2 800f264: 4413 add r3, r2 800f266: 881b ldrh r3, [r3, #0] 800f268: b29b uxth r3, r3 800f26a: f423 43ec bic.w r3, r3, #30208 @ 0x7600 800f26e: f023 0370 bic.w r3, r3, #112 @ 0x70 800f272: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 /* initialize Endpoint */ switch (ep->type) 800f276: 683b ldr r3, [r7, #0] 800f278: 78db ldrb r3, [r3, #3] 800f27a: 2b03 cmp r3, #3 800f27c: d81f bhi.n 800f2be 800f27e: a201 add r2, pc, #4 @ (adr r2, 800f284 ) 800f280: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f284: 0800f295 .word 0x0800f295 800f288: 0800f2b1 .word 0x0800f2b1 800f28c: 0800f2c7 .word 0x0800f2c7 800f290: 0800f2a3 .word 0x0800f2a3 { case EP_TYPE_CTRL: wEpRegVal |= USB_EP_CONTROL; 800f294: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800f298: f443 7300 orr.w r3, r3, #512 @ 0x200 800f29c: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 break; 800f2a0: e012 b.n 800f2c8 case EP_TYPE_BULK: wEpRegVal |= USB_EP_BULK; break; case EP_TYPE_INTR: wEpRegVal |= USB_EP_INTERRUPT; 800f2a2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800f2a6: f443 63c0 orr.w r3, r3, #1536 @ 0x600 800f2aa: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 break; 800f2ae: e00b b.n 800f2c8 case EP_TYPE_ISOC: wEpRegVal |= USB_EP_ISOCHRONOUS; 800f2b0: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800f2b4: f443 6380 orr.w r3, r3, #1024 @ 0x400 800f2b8: f8a7 3094 strh.w r3, [r7, #148] @ 0x94 break; 800f2bc: e004 b.n 800f2c8 default: ret = HAL_ERROR; 800f2be: 2301 movs r3, #1 800f2c0: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800f2c4: e000 b.n 800f2c8 break; 800f2c6: bf00 nop } PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); 800f2c8: 687a ldr r2, [r7, #4] 800f2ca: 683b ldr r3, [r7, #0] 800f2cc: 781b ldrb r3, [r3, #0] 800f2ce: 009b lsls r3, r3, #2 800f2d0: 441a add r2, r3 800f2d2: f8b7 3094 ldrh.w r3, [r7, #148] @ 0x94 800f2d6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f2da: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f2de: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f2e2: f043 0380 orr.w r3, r3, #128 @ 0x80 800f2e6: b29b uxth r3, r3 800f2e8: 8013 strh r3, [r2, #0] PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); 800f2ea: 687a ldr r2, [r7, #4] 800f2ec: 683b ldr r3, [r7, #0] 800f2ee: 781b ldrb r3, [r3, #0] 800f2f0: 009b lsls r3, r3, #2 800f2f2: 4413 add r3, r2 800f2f4: 881b ldrh r3, [r3, #0] 800f2f6: b29b uxth r3, r3 800f2f8: b21b sxth r3, r3 800f2fa: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f2fe: f023 0370 bic.w r3, r3, #112 @ 0x70 800f302: b21a sxth r2, r3 800f304: 683b ldr r3, [r7, #0] 800f306: 781b ldrb r3, [r3, #0] 800f308: b21b sxth r3, r3 800f30a: 4313 orrs r3, r2 800f30c: b21b sxth r3, r3 800f30e: f8a7 3086 strh.w r3, [r7, #134] @ 0x86 800f312: 687a ldr r2, [r7, #4] 800f314: 683b ldr r3, [r7, #0] 800f316: 781b ldrb r3, [r3, #0] 800f318: 009b lsls r3, r3, #2 800f31a: 441a add r2, r3 800f31c: f8b7 3086 ldrh.w r3, [r7, #134] @ 0x86 800f320: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f324: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f328: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f32c: f043 0380 orr.w r3, r3, #128 @ 0x80 800f330: b29b uxth r3, r3 800f332: 8013 strh r3, [r2, #0] if (ep->doublebuffer == 0U) 800f334: 683b ldr r3, [r7, #0] 800f336: 7b1b ldrb r3, [r3, #12] 800f338: 2b00 cmp r3, #0 800f33a: f040 8180 bne.w 800f63e { if (ep->is_in != 0U) 800f33e: 683b ldr r3, [r7, #0] 800f340: 785b ldrb r3, [r3, #1] 800f342: 2b00 cmp r3, #0 800f344: f000 8084 beq.w 800f450 { /*Set the endpoint Transmit buffer address */ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); 800f348: 687b ldr r3, [r7, #4] 800f34a: 61bb str r3, [r7, #24] 800f34c: 687b ldr r3, [r7, #4] 800f34e: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f352: b29b uxth r3, r3 800f354: 461a mov r2, r3 800f356: 69bb ldr r3, [r7, #24] 800f358: 4413 add r3, r2 800f35a: 61bb str r3, [r7, #24] 800f35c: 683b ldr r3, [r7, #0] 800f35e: 781b ldrb r3, [r3, #0] 800f360: 00da lsls r2, r3, #3 800f362: 69bb ldr r3, [r7, #24] 800f364: 4413 add r3, r2 800f366: f503 6380 add.w r3, r3, #1024 @ 0x400 800f36a: 617b str r3, [r7, #20] 800f36c: 683b ldr r3, [r7, #0] 800f36e: 88db ldrh r3, [r3, #6] 800f370: 085b lsrs r3, r3, #1 800f372: b29b uxth r3, r3 800f374: 005b lsls r3, r3, #1 800f376: b29a uxth r2, r3 800f378: 697b ldr r3, [r7, #20] 800f37a: 801a strh r2, [r3, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800f37c: 687a ldr r2, [r7, #4] 800f37e: 683b ldr r3, [r7, #0] 800f380: 781b ldrb r3, [r3, #0] 800f382: 009b lsls r3, r3, #2 800f384: 4413 add r3, r2 800f386: 881b ldrh r3, [r3, #0] 800f388: 827b strh r3, [r7, #18] 800f38a: 8a7b ldrh r3, [r7, #18] 800f38c: f003 0340 and.w r3, r3, #64 @ 0x40 800f390: 2b00 cmp r3, #0 800f392: d01b beq.n 800f3cc 800f394: 687a ldr r2, [r7, #4] 800f396: 683b ldr r3, [r7, #0] 800f398: 781b ldrb r3, [r3, #0] 800f39a: 009b lsls r3, r3, #2 800f39c: 4413 add r3, r2 800f39e: 881b ldrh r3, [r3, #0] 800f3a0: b29b uxth r3, r3 800f3a2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f3a6: f023 0370 bic.w r3, r3, #112 @ 0x70 800f3aa: 823b strh r3, [r7, #16] 800f3ac: 687a ldr r2, [r7, #4] 800f3ae: 683b ldr r3, [r7, #0] 800f3b0: 781b ldrb r3, [r3, #0] 800f3b2: 009b lsls r3, r3, #2 800f3b4: 441a add r2, r3 800f3b6: 8a3b ldrh r3, [r7, #16] 800f3b8: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f3bc: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f3c0: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f3c4: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800f3c8: b29b uxth r3, r3 800f3ca: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800f3cc: 683b ldr r3, [r7, #0] 800f3ce: 78db ldrb r3, [r3, #3] 800f3d0: 2b01 cmp r3, #1 800f3d2: d020 beq.n 800f416 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 800f3d4: 687a ldr r2, [r7, #4] 800f3d6: 683b ldr r3, [r7, #0] 800f3d8: 781b ldrb r3, [r3, #0] 800f3da: 009b lsls r3, r3, #2 800f3dc: 4413 add r3, r2 800f3de: 881b ldrh r3, [r3, #0] 800f3e0: b29b uxth r3, r3 800f3e2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f3e6: f023 0340 bic.w r3, r3, #64 @ 0x40 800f3ea: 81bb strh r3, [r7, #12] 800f3ec: 89bb ldrh r3, [r7, #12] 800f3ee: f083 0320 eor.w r3, r3, #32 800f3f2: 81bb strh r3, [r7, #12] 800f3f4: 687a ldr r2, [r7, #4] 800f3f6: 683b ldr r3, [r7, #0] 800f3f8: 781b ldrb r3, [r3, #0] 800f3fa: 009b lsls r3, r3, #2 800f3fc: 441a add r2, r3 800f3fe: 89bb ldrh r3, [r7, #12] 800f400: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f404: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f408: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f40c: f043 0380 orr.w r3, r3, #128 @ 0x80 800f410: b29b uxth r3, r3 800f412: 8013 strh r3, [r2, #0] 800f414: e3f9 b.n 800fc0a } else { /* Configure TX Endpoint to disabled state */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800f416: 687a ldr r2, [r7, #4] 800f418: 683b ldr r3, [r7, #0] 800f41a: 781b ldrb r3, [r3, #0] 800f41c: 009b lsls r3, r3, #2 800f41e: 4413 add r3, r2 800f420: 881b ldrh r3, [r3, #0] 800f422: b29b uxth r3, r3 800f424: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f428: f023 0340 bic.w r3, r3, #64 @ 0x40 800f42c: 81fb strh r3, [r7, #14] 800f42e: 687a ldr r2, [r7, #4] 800f430: 683b ldr r3, [r7, #0] 800f432: 781b ldrb r3, [r3, #0] 800f434: 009b lsls r3, r3, #2 800f436: 441a add r2, r3 800f438: 89fb ldrh r3, [r7, #14] 800f43a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f43e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f442: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f446: f043 0380 orr.w r3, r3, #128 @ 0x80 800f44a: b29b uxth r3, r3 800f44c: 8013 strh r3, [r2, #0] 800f44e: e3dc b.n 800fc0a } } else { /* Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); 800f450: 687b ldr r3, [r7, #4] 800f452: 633b str r3, [r7, #48] @ 0x30 800f454: 687b ldr r3, [r7, #4] 800f456: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f45a: b29b uxth r3, r3 800f45c: 461a mov r2, r3 800f45e: 6b3b ldr r3, [r7, #48] @ 0x30 800f460: 4413 add r3, r2 800f462: 633b str r3, [r7, #48] @ 0x30 800f464: 683b ldr r3, [r7, #0] 800f466: 781b ldrb r3, [r3, #0] 800f468: 00da lsls r2, r3, #3 800f46a: 6b3b ldr r3, [r7, #48] @ 0x30 800f46c: 4413 add r3, r2 800f46e: f203 4304 addw r3, r3, #1028 @ 0x404 800f472: 62fb str r3, [r7, #44] @ 0x2c 800f474: 683b ldr r3, [r7, #0] 800f476: 88db ldrh r3, [r3, #6] 800f478: 085b lsrs r3, r3, #1 800f47a: b29b uxth r3, r3 800f47c: 005b lsls r3, r3, #1 800f47e: b29a uxth r2, r3 800f480: 6afb ldr r3, [r7, #44] @ 0x2c 800f482: 801a strh r2, [r3, #0] /* Set the endpoint Receive buffer counter */ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); 800f484: 687b ldr r3, [r7, #4] 800f486: 62bb str r3, [r7, #40] @ 0x28 800f488: 687b ldr r3, [r7, #4] 800f48a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f48e: b29b uxth r3, r3 800f490: 461a mov r2, r3 800f492: 6abb ldr r3, [r7, #40] @ 0x28 800f494: 4413 add r3, r2 800f496: 62bb str r3, [r7, #40] @ 0x28 800f498: 683b ldr r3, [r7, #0] 800f49a: 781b ldrb r3, [r3, #0] 800f49c: 00da lsls r2, r3, #3 800f49e: 6abb ldr r3, [r7, #40] @ 0x28 800f4a0: 4413 add r3, r2 800f4a2: f203 4306 addw r3, r3, #1030 @ 0x406 800f4a6: 627b str r3, [r7, #36] @ 0x24 800f4a8: 6a7b ldr r3, [r7, #36] @ 0x24 800f4aa: 881b ldrh r3, [r3, #0] 800f4ac: b29b uxth r3, r3 800f4ae: f3c3 0309 ubfx r3, r3, #0, #10 800f4b2: b29a uxth r2, r3 800f4b4: 6a7b ldr r3, [r7, #36] @ 0x24 800f4b6: 801a strh r2, [r3, #0] 800f4b8: 683b ldr r3, [r7, #0] 800f4ba: 691b ldr r3, [r3, #16] 800f4bc: 2b00 cmp r3, #0 800f4be: d10a bne.n 800f4d6 800f4c0: 6a7b ldr r3, [r7, #36] @ 0x24 800f4c2: 881b ldrh r3, [r3, #0] 800f4c4: b29b uxth r3, r3 800f4c6: ea6f 4343 mvn.w r3, r3, lsl #17 800f4ca: ea6f 4353 mvn.w r3, r3, lsr #17 800f4ce: b29a uxth r2, r3 800f4d0: 6a7b ldr r3, [r7, #36] @ 0x24 800f4d2: 801a strh r2, [r3, #0] 800f4d4: e041 b.n 800f55a 800f4d6: 683b ldr r3, [r7, #0] 800f4d8: 691b ldr r3, [r3, #16] 800f4da: 2b3e cmp r3, #62 @ 0x3e 800f4dc: d81c bhi.n 800f518 800f4de: 683b ldr r3, [r7, #0] 800f4e0: 691b ldr r3, [r3, #16] 800f4e2: 085b lsrs r3, r3, #1 800f4e4: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800f4e8: 683b ldr r3, [r7, #0] 800f4ea: 691b ldr r3, [r3, #16] 800f4ec: f003 0301 and.w r3, r3, #1 800f4f0: 2b00 cmp r3, #0 800f4f2: d004 beq.n 800f4fe 800f4f4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800f4f8: 3301 adds r3, #1 800f4fa: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800f4fe: 6a7b ldr r3, [r7, #36] @ 0x24 800f500: 881b ldrh r3, [r3, #0] 800f502: b29a uxth r2, r3 800f504: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800f508: b29b uxth r3, r3 800f50a: 029b lsls r3, r3, #10 800f50c: b29b uxth r3, r3 800f50e: 4313 orrs r3, r2 800f510: b29a uxth r2, r3 800f512: 6a7b ldr r3, [r7, #36] @ 0x24 800f514: 801a strh r2, [r3, #0] 800f516: e020 b.n 800f55a 800f518: 683b ldr r3, [r7, #0] 800f51a: 691b ldr r3, [r3, #16] 800f51c: 095b lsrs r3, r3, #5 800f51e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800f522: 683b ldr r3, [r7, #0] 800f524: 691b ldr r3, [r3, #16] 800f526: f003 031f and.w r3, r3, #31 800f52a: 2b00 cmp r3, #0 800f52c: d104 bne.n 800f538 800f52e: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800f532: 3b01 subs r3, #1 800f534: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800f538: 6a7b ldr r3, [r7, #36] @ 0x24 800f53a: 881b ldrh r3, [r3, #0] 800f53c: b29a uxth r2, r3 800f53e: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800f542: b29b uxth r3, r3 800f544: 029b lsls r3, r3, #10 800f546: b29b uxth r3, r3 800f548: 4313 orrs r3, r2 800f54a: b29b uxth r3, r3 800f54c: ea6f 4343 mvn.w r3, r3, lsl #17 800f550: ea6f 4353 mvn.w r3, r3, lsr #17 800f554: b29a uxth r2, r3 800f556: 6a7b ldr r3, [r7, #36] @ 0x24 800f558: 801a strh r2, [r3, #0] PCD_CLEAR_RX_DTOG(USBx, ep->num); 800f55a: 687a ldr r2, [r7, #4] 800f55c: 683b ldr r3, [r7, #0] 800f55e: 781b ldrb r3, [r3, #0] 800f560: 009b lsls r3, r3, #2 800f562: 4413 add r3, r2 800f564: 881b ldrh r3, [r3, #0] 800f566: 847b strh r3, [r7, #34] @ 0x22 800f568: 8c7b ldrh r3, [r7, #34] @ 0x22 800f56a: f403 4380 and.w r3, r3, #16384 @ 0x4000 800f56e: 2b00 cmp r3, #0 800f570: d01b beq.n 800f5aa 800f572: 687a ldr r2, [r7, #4] 800f574: 683b ldr r3, [r7, #0] 800f576: 781b ldrb r3, [r3, #0] 800f578: 009b lsls r3, r3, #2 800f57a: 4413 add r3, r2 800f57c: 881b ldrh r3, [r3, #0] 800f57e: b29b uxth r3, r3 800f580: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f584: f023 0370 bic.w r3, r3, #112 @ 0x70 800f588: 843b strh r3, [r7, #32] 800f58a: 687a ldr r2, [r7, #4] 800f58c: 683b ldr r3, [r7, #0] 800f58e: 781b ldrb r3, [r3, #0] 800f590: 009b lsls r3, r3, #2 800f592: 441a add r2, r3 800f594: 8c3b ldrh r3, [r7, #32] 800f596: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f59a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f59e: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800f5a2: f043 0380 orr.w r3, r3, #128 @ 0x80 800f5a6: b29b uxth r3, r3 800f5a8: 8013 strh r3, [r2, #0] if (ep->num == 0U) 800f5aa: 683b ldr r3, [r7, #0] 800f5ac: 781b ldrb r3, [r3, #0] 800f5ae: 2b00 cmp r3, #0 800f5b0: d124 bne.n 800f5fc { /* Configure VALID status for EP0 */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 800f5b2: 687a ldr r2, [r7, #4] 800f5b4: 683b ldr r3, [r7, #0] 800f5b6: 781b ldrb r3, [r3, #0] 800f5b8: 009b lsls r3, r3, #2 800f5ba: 4413 add r3, r2 800f5bc: 881b ldrh r3, [r3, #0] 800f5be: b29b uxth r3, r3 800f5c0: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800f5c4: f023 0370 bic.w r3, r3, #112 @ 0x70 800f5c8: 83bb strh r3, [r7, #28] 800f5ca: 8bbb ldrh r3, [r7, #28] 800f5cc: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800f5d0: 83bb strh r3, [r7, #28] 800f5d2: 8bbb ldrh r3, [r7, #28] 800f5d4: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800f5d8: 83bb strh r3, [r7, #28] 800f5da: 687a ldr r2, [r7, #4] 800f5dc: 683b ldr r3, [r7, #0] 800f5de: 781b ldrb r3, [r3, #0] 800f5e0: 009b lsls r3, r3, #2 800f5e2: 441a add r2, r3 800f5e4: 8bbb ldrh r3, [r7, #28] 800f5e6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f5ea: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f5ee: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f5f2: f043 0380 orr.w r3, r3, #128 @ 0x80 800f5f6: b29b uxth r3, r3 800f5f8: 8013 strh r3, [r2, #0] 800f5fa: e306 b.n 800fc0a } else { /* Configure NAK status for OUT Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); 800f5fc: 687a ldr r2, [r7, #4] 800f5fe: 683b ldr r3, [r7, #0] 800f600: 781b ldrb r3, [r3, #0] 800f602: 009b lsls r3, r3, #2 800f604: 4413 add r3, r2 800f606: 881b ldrh r3, [r3, #0] 800f608: b29b uxth r3, r3 800f60a: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800f60e: f023 0370 bic.w r3, r3, #112 @ 0x70 800f612: 83fb strh r3, [r7, #30] 800f614: 8bfb ldrh r3, [r7, #30] 800f616: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800f61a: 83fb strh r3, [r7, #30] 800f61c: 687a ldr r2, [r7, #4] 800f61e: 683b ldr r3, [r7, #0] 800f620: 781b ldrb r3, [r3, #0] 800f622: 009b lsls r3, r3, #2 800f624: 441a add r2, r3 800f626: 8bfb ldrh r3, [r7, #30] 800f628: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f62c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f630: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f634: f043 0380 orr.w r3, r3, #128 @ 0x80 800f638: b29b uxth r3, r3 800f63a: 8013 strh r3, [r2, #0] 800f63c: e2e5 b.n 800fc0a } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer */ else { if (ep->type == EP_TYPE_BULK) 800f63e: 683b ldr r3, [r7, #0] 800f640: 78db ldrb r3, [r3, #3] 800f642: 2b02 cmp r3, #2 800f644: d11e bne.n 800f684 { /* Set bulk endpoint as double buffered */ PCD_SET_BULK_EP_DBUF(USBx, ep->num); 800f646: 687a ldr r2, [r7, #4] 800f648: 683b ldr r3, [r7, #0] 800f64a: 781b ldrb r3, [r3, #0] 800f64c: 009b lsls r3, r3, #2 800f64e: 4413 add r3, r2 800f650: 881b ldrh r3, [r3, #0] 800f652: b29b uxth r3, r3 800f654: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f658: f023 0370 bic.w r3, r3, #112 @ 0x70 800f65c: f8a7 3082 strh.w r3, [r7, #130] @ 0x82 800f660: 687a ldr r2, [r7, #4] 800f662: 683b ldr r3, [r7, #0] 800f664: 781b ldrb r3, [r3, #0] 800f666: 009b lsls r3, r3, #2 800f668: 441a add r2, r3 800f66a: f8b7 3082 ldrh.w r3, [r7, #130] @ 0x82 800f66e: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f672: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f676: f443 4301 orr.w r3, r3, #33024 @ 0x8100 800f67a: f043 0380 orr.w r3, r3, #128 @ 0x80 800f67e: b29b uxth r3, r3 800f680: 8013 strh r3, [r2, #0] 800f682: e01d b.n 800f6c0 } else { /* Set the ISOC endpoint in double buffer mode */ PCD_CLEAR_EP_KIND(USBx, ep->num); 800f684: 687a ldr r2, [r7, #4] 800f686: 683b ldr r3, [r7, #0] 800f688: 781b ldrb r3, [r3, #0] 800f68a: 009b lsls r3, r3, #2 800f68c: 4413 add r3, r2 800f68e: 881b ldrh r3, [r3, #0] 800f690: b29b uxth r3, r3 800f692: f423 43e2 bic.w r3, r3, #28928 @ 0x7100 800f696: f023 0370 bic.w r3, r3, #112 @ 0x70 800f69a: f8a7 3084 strh.w r3, [r7, #132] @ 0x84 800f69e: 687a ldr r2, [r7, #4] 800f6a0: 683b ldr r3, [r7, #0] 800f6a2: 781b ldrb r3, [r3, #0] 800f6a4: 009b lsls r3, r3, #2 800f6a6: 441a add r2, r3 800f6a8: f8b7 3084 ldrh.w r3, [r7, #132] @ 0x84 800f6ac: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f6b0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f6b4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f6b8: f043 0380 orr.w r3, r3, #128 @ 0x80 800f6bc: b29b uxth r3, r3 800f6be: 8013 strh r3, [r2, #0] } /* Set buffer address for double buffered mode */ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); 800f6c0: 687b ldr r3, [r7, #4] 800f6c2: 67fb str r3, [r7, #124] @ 0x7c 800f6c4: 687b ldr r3, [r7, #4] 800f6c6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f6ca: b29b uxth r3, r3 800f6cc: 461a mov r2, r3 800f6ce: 6ffb ldr r3, [r7, #124] @ 0x7c 800f6d0: 4413 add r3, r2 800f6d2: 67fb str r3, [r7, #124] @ 0x7c 800f6d4: 683b ldr r3, [r7, #0] 800f6d6: 781b ldrb r3, [r3, #0] 800f6d8: 00da lsls r2, r3, #3 800f6da: 6ffb ldr r3, [r7, #124] @ 0x7c 800f6dc: 4413 add r3, r2 800f6de: f503 6380 add.w r3, r3, #1024 @ 0x400 800f6e2: 67bb str r3, [r7, #120] @ 0x78 800f6e4: 683b ldr r3, [r7, #0] 800f6e6: 891b ldrh r3, [r3, #8] 800f6e8: 085b lsrs r3, r3, #1 800f6ea: b29b uxth r3, r3 800f6ec: 005b lsls r3, r3, #1 800f6ee: b29a uxth r2, r3 800f6f0: 6fbb ldr r3, [r7, #120] @ 0x78 800f6f2: 801a strh r2, [r3, #0] 800f6f4: 687b ldr r3, [r7, #4] 800f6f6: 677b str r3, [r7, #116] @ 0x74 800f6f8: 687b ldr r3, [r7, #4] 800f6fa: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f6fe: b29b uxth r3, r3 800f700: 461a mov r2, r3 800f702: 6f7b ldr r3, [r7, #116] @ 0x74 800f704: 4413 add r3, r2 800f706: 677b str r3, [r7, #116] @ 0x74 800f708: 683b ldr r3, [r7, #0] 800f70a: 781b ldrb r3, [r3, #0] 800f70c: 00da lsls r2, r3, #3 800f70e: 6f7b ldr r3, [r7, #116] @ 0x74 800f710: 4413 add r3, r2 800f712: f203 4304 addw r3, r3, #1028 @ 0x404 800f716: 673b str r3, [r7, #112] @ 0x70 800f718: 683b ldr r3, [r7, #0] 800f71a: 895b ldrh r3, [r3, #10] 800f71c: 085b lsrs r3, r3, #1 800f71e: b29b uxth r3, r3 800f720: 005b lsls r3, r3, #1 800f722: b29a uxth r2, r3 800f724: 6f3b ldr r3, [r7, #112] @ 0x70 800f726: 801a strh r2, [r3, #0] if (ep->is_in == 0U) 800f728: 683b ldr r3, [r7, #0] 800f72a: 785b ldrb r3, [r3, #1] 800f72c: 2b00 cmp r3, #0 800f72e: f040 81af bne.w 800fa90 { /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800f732: 687a ldr r2, [r7, #4] 800f734: 683b ldr r3, [r7, #0] 800f736: 781b ldrb r3, [r3, #0] 800f738: 009b lsls r3, r3, #2 800f73a: 4413 add r3, r2 800f73c: 881b ldrh r3, [r3, #0] 800f73e: f8a7 3060 strh.w r3, [r7, #96] @ 0x60 800f742: f8b7 3060 ldrh.w r3, [r7, #96] @ 0x60 800f746: f403 4380 and.w r3, r3, #16384 @ 0x4000 800f74a: 2b00 cmp r3, #0 800f74c: d01d beq.n 800f78a 800f74e: 687a ldr r2, [r7, #4] 800f750: 683b ldr r3, [r7, #0] 800f752: 781b ldrb r3, [r3, #0] 800f754: 009b lsls r3, r3, #2 800f756: 4413 add r3, r2 800f758: 881b ldrh r3, [r3, #0] 800f75a: b29b uxth r3, r3 800f75c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f760: f023 0370 bic.w r3, r3, #112 @ 0x70 800f764: f8a7 305e strh.w r3, [r7, #94] @ 0x5e 800f768: 687a ldr r2, [r7, #4] 800f76a: 683b ldr r3, [r7, #0] 800f76c: 781b ldrb r3, [r3, #0] 800f76e: 009b lsls r3, r3, #2 800f770: 441a add r2, r3 800f772: f8b7 305e ldrh.w r3, [r7, #94] @ 0x5e 800f776: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f77a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f77e: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800f782: f043 0380 orr.w r3, r3, #128 @ 0x80 800f786: b29b uxth r3, r3 800f788: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800f78a: 687a ldr r2, [r7, #4] 800f78c: 683b ldr r3, [r7, #0] 800f78e: 781b ldrb r3, [r3, #0] 800f790: 009b lsls r3, r3, #2 800f792: 4413 add r3, r2 800f794: 881b ldrh r3, [r3, #0] 800f796: f8a7 305c strh.w r3, [r7, #92] @ 0x5c 800f79a: f8b7 305c ldrh.w r3, [r7, #92] @ 0x5c 800f79e: f003 0340 and.w r3, r3, #64 @ 0x40 800f7a2: 2b00 cmp r3, #0 800f7a4: d01d beq.n 800f7e2 800f7a6: 687a ldr r2, [r7, #4] 800f7a8: 683b ldr r3, [r7, #0] 800f7aa: 781b ldrb r3, [r3, #0] 800f7ac: 009b lsls r3, r3, #2 800f7ae: 4413 add r3, r2 800f7b0: 881b ldrh r3, [r3, #0] 800f7b2: b29b uxth r3, r3 800f7b4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800f7b8: f023 0370 bic.w r3, r3, #112 @ 0x70 800f7bc: f8a7 305a strh.w r3, [r7, #90] @ 0x5a 800f7c0: 687a ldr r2, [r7, #4] 800f7c2: 683b ldr r3, [r7, #0] 800f7c4: 781b ldrb r3, [r3, #0] 800f7c6: 009b lsls r3, r3, #2 800f7c8: 441a add r2, r3 800f7ca: f8b7 305a ldrh.w r3, [r7, #90] @ 0x5a 800f7ce: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800f7d2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800f7d6: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800f7da: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800f7de: b29b uxth r3, r3 800f7e0: 8013 strh r3, [r2, #0] /* Set endpoint RX count */ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); 800f7e2: 683b ldr r3, [r7, #0] 800f7e4: 785b ldrb r3, [r3, #1] 800f7e6: 2b00 cmp r3, #0 800f7e8: d16b bne.n 800f8c2 800f7ea: 687b ldr r3, [r7, #4] 800f7ec: 64fb str r3, [r7, #76] @ 0x4c 800f7ee: 687b ldr r3, [r7, #4] 800f7f0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f7f4: b29b uxth r3, r3 800f7f6: 461a mov r2, r3 800f7f8: 6cfb ldr r3, [r7, #76] @ 0x4c 800f7fa: 4413 add r3, r2 800f7fc: 64fb str r3, [r7, #76] @ 0x4c 800f7fe: 683b ldr r3, [r7, #0] 800f800: 781b ldrb r3, [r3, #0] 800f802: 00da lsls r2, r3, #3 800f804: 6cfb ldr r3, [r7, #76] @ 0x4c 800f806: 4413 add r3, r2 800f808: f203 4302 addw r3, r3, #1026 @ 0x402 800f80c: 64bb str r3, [r7, #72] @ 0x48 800f80e: 6cbb ldr r3, [r7, #72] @ 0x48 800f810: 881b ldrh r3, [r3, #0] 800f812: b29b uxth r3, r3 800f814: f3c3 0309 ubfx r3, r3, #0, #10 800f818: b29a uxth r2, r3 800f81a: 6cbb ldr r3, [r7, #72] @ 0x48 800f81c: 801a strh r2, [r3, #0] 800f81e: 683b ldr r3, [r7, #0] 800f820: 691b ldr r3, [r3, #16] 800f822: 2b00 cmp r3, #0 800f824: d10a bne.n 800f83c 800f826: 6cbb ldr r3, [r7, #72] @ 0x48 800f828: 881b ldrh r3, [r3, #0] 800f82a: b29b uxth r3, r3 800f82c: ea6f 4343 mvn.w r3, r3, lsl #17 800f830: ea6f 4353 mvn.w r3, r3, lsr #17 800f834: b29a uxth r2, r3 800f836: 6cbb ldr r3, [r7, #72] @ 0x48 800f838: 801a strh r2, [r3, #0] 800f83a: e05d b.n 800f8f8 800f83c: 683b ldr r3, [r7, #0] 800f83e: 691b ldr r3, [r3, #16] 800f840: 2b3e cmp r3, #62 @ 0x3e 800f842: d81c bhi.n 800f87e 800f844: 683b ldr r3, [r7, #0] 800f846: 691b ldr r3, [r3, #16] 800f848: 085b lsrs r3, r3, #1 800f84a: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800f84e: 683b ldr r3, [r7, #0] 800f850: 691b ldr r3, [r3, #16] 800f852: f003 0301 and.w r3, r3, #1 800f856: 2b00 cmp r3, #0 800f858: d004 beq.n 800f864 800f85a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800f85e: 3301 adds r3, #1 800f860: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800f864: 6cbb ldr r3, [r7, #72] @ 0x48 800f866: 881b ldrh r3, [r3, #0] 800f868: b29a uxth r2, r3 800f86a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800f86e: b29b uxth r3, r3 800f870: 029b lsls r3, r3, #10 800f872: b29b uxth r3, r3 800f874: 4313 orrs r3, r2 800f876: b29a uxth r2, r3 800f878: 6cbb ldr r3, [r7, #72] @ 0x48 800f87a: 801a strh r2, [r3, #0] 800f87c: e03c b.n 800f8f8 800f87e: 683b ldr r3, [r7, #0] 800f880: 691b ldr r3, [r3, #16] 800f882: 095b lsrs r3, r3, #5 800f884: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800f888: 683b ldr r3, [r7, #0] 800f88a: 691b ldr r3, [r3, #16] 800f88c: f003 031f and.w r3, r3, #31 800f890: 2b00 cmp r3, #0 800f892: d104 bne.n 800f89e 800f894: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800f898: 3b01 subs r3, #1 800f89a: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800f89e: 6cbb ldr r3, [r7, #72] @ 0x48 800f8a0: 881b ldrh r3, [r3, #0] 800f8a2: b29a uxth r2, r3 800f8a4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800f8a8: b29b uxth r3, r3 800f8aa: 029b lsls r3, r3, #10 800f8ac: b29b uxth r3, r3 800f8ae: 4313 orrs r3, r2 800f8b0: b29b uxth r3, r3 800f8b2: ea6f 4343 mvn.w r3, r3, lsl #17 800f8b6: ea6f 4353 mvn.w r3, r3, lsr #17 800f8ba: b29a uxth r2, r3 800f8bc: 6cbb ldr r3, [r7, #72] @ 0x48 800f8be: 801a strh r2, [r3, #0] 800f8c0: e01a b.n 800f8f8 800f8c2: 683b ldr r3, [r7, #0] 800f8c4: 785b ldrb r3, [r3, #1] 800f8c6: 2b01 cmp r3, #1 800f8c8: d116 bne.n 800f8f8 800f8ca: 687b ldr r3, [r7, #4] 800f8cc: 657b str r3, [r7, #84] @ 0x54 800f8ce: 687b ldr r3, [r7, #4] 800f8d0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f8d4: b29b uxth r3, r3 800f8d6: 461a mov r2, r3 800f8d8: 6d7b ldr r3, [r7, #84] @ 0x54 800f8da: 4413 add r3, r2 800f8dc: 657b str r3, [r7, #84] @ 0x54 800f8de: 683b ldr r3, [r7, #0] 800f8e0: 781b ldrb r3, [r3, #0] 800f8e2: 00da lsls r2, r3, #3 800f8e4: 6d7b ldr r3, [r7, #84] @ 0x54 800f8e6: 4413 add r3, r2 800f8e8: f203 4302 addw r3, r3, #1026 @ 0x402 800f8ec: 653b str r3, [r7, #80] @ 0x50 800f8ee: 683b ldr r3, [r7, #0] 800f8f0: 691b ldr r3, [r3, #16] 800f8f2: b29a uxth r2, r3 800f8f4: 6d3b ldr r3, [r7, #80] @ 0x50 800f8f6: 801a strh r2, [r3, #0] 800f8f8: 687b ldr r3, [r7, #4] 800f8fa: 647b str r3, [r7, #68] @ 0x44 800f8fc: 683b ldr r3, [r7, #0] 800f8fe: 785b ldrb r3, [r3, #1] 800f900: 2b00 cmp r3, #0 800f902: d16b bne.n 800f9dc 800f904: 687b ldr r3, [r7, #4] 800f906: 63fb str r3, [r7, #60] @ 0x3c 800f908: 687b ldr r3, [r7, #4] 800f90a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f90e: b29b uxth r3, r3 800f910: 461a mov r2, r3 800f912: 6bfb ldr r3, [r7, #60] @ 0x3c 800f914: 4413 add r3, r2 800f916: 63fb str r3, [r7, #60] @ 0x3c 800f918: 683b ldr r3, [r7, #0] 800f91a: 781b ldrb r3, [r3, #0] 800f91c: 00da lsls r2, r3, #3 800f91e: 6bfb ldr r3, [r7, #60] @ 0x3c 800f920: 4413 add r3, r2 800f922: f203 4306 addw r3, r3, #1030 @ 0x406 800f926: 63bb str r3, [r7, #56] @ 0x38 800f928: 6bbb ldr r3, [r7, #56] @ 0x38 800f92a: 881b ldrh r3, [r3, #0] 800f92c: b29b uxth r3, r3 800f92e: f3c3 0309 ubfx r3, r3, #0, #10 800f932: b29a uxth r2, r3 800f934: 6bbb ldr r3, [r7, #56] @ 0x38 800f936: 801a strh r2, [r3, #0] 800f938: 683b ldr r3, [r7, #0] 800f93a: 691b ldr r3, [r3, #16] 800f93c: 2b00 cmp r3, #0 800f93e: d10a bne.n 800f956 800f940: 6bbb ldr r3, [r7, #56] @ 0x38 800f942: 881b ldrh r3, [r3, #0] 800f944: b29b uxth r3, r3 800f946: ea6f 4343 mvn.w r3, r3, lsl #17 800f94a: ea6f 4353 mvn.w r3, r3, lsr #17 800f94e: b29a uxth r2, r3 800f950: 6bbb ldr r3, [r7, #56] @ 0x38 800f952: 801a strh r2, [r3, #0] 800f954: e05b b.n 800fa0e 800f956: 683b ldr r3, [r7, #0] 800f958: 691b ldr r3, [r3, #16] 800f95a: 2b3e cmp r3, #62 @ 0x3e 800f95c: d81c bhi.n 800f998 800f95e: 683b ldr r3, [r7, #0] 800f960: 691b ldr r3, [r3, #16] 800f962: 085b lsrs r3, r3, #1 800f964: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800f968: 683b ldr r3, [r7, #0] 800f96a: 691b ldr r3, [r3, #16] 800f96c: f003 0301 and.w r3, r3, #1 800f970: 2b00 cmp r3, #0 800f972: d004 beq.n 800f97e 800f974: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800f978: 3301 adds r3, #1 800f97a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800f97e: 6bbb ldr r3, [r7, #56] @ 0x38 800f980: 881b ldrh r3, [r3, #0] 800f982: b29a uxth r2, r3 800f984: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800f988: b29b uxth r3, r3 800f98a: 029b lsls r3, r3, #10 800f98c: b29b uxth r3, r3 800f98e: 4313 orrs r3, r2 800f990: b29a uxth r2, r3 800f992: 6bbb ldr r3, [r7, #56] @ 0x38 800f994: 801a strh r2, [r3, #0] 800f996: e03a b.n 800fa0e 800f998: 683b ldr r3, [r7, #0] 800f99a: 691b ldr r3, [r3, #16] 800f99c: 095b lsrs r3, r3, #5 800f99e: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800f9a2: 683b ldr r3, [r7, #0] 800f9a4: 691b ldr r3, [r3, #16] 800f9a6: f003 031f and.w r3, r3, #31 800f9aa: 2b00 cmp r3, #0 800f9ac: d104 bne.n 800f9b8 800f9ae: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800f9b2: 3b01 subs r3, #1 800f9b4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800f9b8: 6bbb ldr r3, [r7, #56] @ 0x38 800f9ba: 881b ldrh r3, [r3, #0] 800f9bc: b29a uxth r2, r3 800f9be: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800f9c2: b29b uxth r3, r3 800f9c4: 029b lsls r3, r3, #10 800f9c6: b29b uxth r3, r3 800f9c8: 4313 orrs r3, r2 800f9ca: b29b uxth r3, r3 800f9cc: ea6f 4343 mvn.w r3, r3, lsl #17 800f9d0: ea6f 4353 mvn.w r3, r3, lsr #17 800f9d4: b29a uxth r2, r3 800f9d6: 6bbb ldr r3, [r7, #56] @ 0x38 800f9d8: 801a strh r2, [r3, #0] 800f9da: e018 b.n 800fa0e 800f9dc: 683b ldr r3, [r7, #0] 800f9de: 785b ldrb r3, [r3, #1] 800f9e0: 2b01 cmp r3, #1 800f9e2: d114 bne.n 800fa0e 800f9e4: 687b ldr r3, [r7, #4] 800f9e6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 800f9ea: b29b uxth r3, r3 800f9ec: 461a mov r2, r3 800f9ee: 6c7b ldr r3, [r7, #68] @ 0x44 800f9f0: 4413 add r3, r2 800f9f2: 647b str r3, [r7, #68] @ 0x44 800f9f4: 683b ldr r3, [r7, #0] 800f9f6: 781b ldrb r3, [r3, #0] 800f9f8: 00da lsls r2, r3, #3 800f9fa: 6c7b ldr r3, [r7, #68] @ 0x44 800f9fc: 4413 add r3, r2 800f9fe: f203 4306 addw r3, r3, #1030 @ 0x406 800fa02: 643b str r3, [r7, #64] @ 0x40 800fa04: 683b ldr r3, [r7, #0] 800fa06: 691b ldr r3, [r3, #16] 800fa08: b29a uxth r2, r3 800fa0a: 6c3b ldr r3, [r7, #64] @ 0x40 800fa0c: 801a strh r2, [r3, #0] /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 800fa0e: 687a ldr r2, [r7, #4] 800fa10: 683b ldr r3, [r7, #0] 800fa12: 781b ldrb r3, [r3, #0] 800fa14: 009b lsls r3, r3, #2 800fa16: 4413 add r3, r2 800fa18: 881b ldrh r3, [r3, #0] 800fa1a: b29b uxth r3, r3 800fa1c: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800fa20: f023 0370 bic.w r3, r3, #112 @ 0x70 800fa24: 86fb strh r3, [r7, #54] @ 0x36 800fa26: 8efb ldrh r3, [r7, #54] @ 0x36 800fa28: f483 5380 eor.w r3, r3, #4096 @ 0x1000 800fa2c: 86fb strh r3, [r7, #54] @ 0x36 800fa2e: 8efb ldrh r3, [r7, #54] @ 0x36 800fa30: f483 5300 eor.w r3, r3, #8192 @ 0x2000 800fa34: 86fb strh r3, [r7, #54] @ 0x36 800fa36: 687a ldr r2, [r7, #4] 800fa38: 683b ldr r3, [r7, #0] 800fa3a: 781b ldrb r3, [r3, #0] 800fa3c: 009b lsls r3, r3, #2 800fa3e: 441a add r2, r3 800fa40: 8efb ldrh r3, [r7, #54] @ 0x36 800fa42: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fa46: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fa4a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fa4e: f043 0380 orr.w r3, r3, #128 @ 0x80 800fa52: b29b uxth r3, r3 800fa54: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800fa56: 687a ldr r2, [r7, #4] 800fa58: 683b ldr r3, [r7, #0] 800fa5a: 781b ldrb r3, [r3, #0] 800fa5c: 009b lsls r3, r3, #2 800fa5e: 4413 add r3, r2 800fa60: 881b ldrh r3, [r3, #0] 800fa62: b29b uxth r3, r3 800fa64: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fa68: f023 0340 bic.w r3, r3, #64 @ 0x40 800fa6c: 86bb strh r3, [r7, #52] @ 0x34 800fa6e: 687a ldr r2, [r7, #4] 800fa70: 683b ldr r3, [r7, #0] 800fa72: 781b ldrb r3, [r3, #0] 800fa74: 009b lsls r3, r3, #2 800fa76: 441a add r2, r3 800fa78: 8ebb ldrh r3, [r7, #52] @ 0x34 800fa7a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fa7e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fa82: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fa86: f043 0380 orr.w r3, r3, #128 @ 0x80 800fa8a: b29b uxth r3, r3 800fa8c: 8013 strh r3, [r2, #0] 800fa8e: e0bc b.n 800fc0a } else { /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800fa90: 687a ldr r2, [r7, #4] 800fa92: 683b ldr r3, [r7, #0] 800fa94: 781b ldrb r3, [r3, #0] 800fa96: 009b lsls r3, r3, #2 800fa98: 4413 add r3, r2 800fa9a: 881b ldrh r3, [r3, #0] 800fa9c: f8a7 306e strh.w r3, [r7, #110] @ 0x6e 800faa0: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 800faa4: f403 4380 and.w r3, r3, #16384 @ 0x4000 800faa8: 2b00 cmp r3, #0 800faaa: d01d beq.n 800fae8 800faac: 687a ldr r2, [r7, #4] 800faae: 683b ldr r3, [r7, #0] 800fab0: 781b ldrb r3, [r3, #0] 800fab2: 009b lsls r3, r3, #2 800fab4: 4413 add r3, r2 800fab6: 881b ldrh r3, [r3, #0] 800fab8: b29b uxth r3, r3 800faba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fabe: f023 0370 bic.w r3, r3, #112 @ 0x70 800fac2: f8a7 306c strh.w r3, [r7, #108] @ 0x6c 800fac6: 687a ldr r2, [r7, #4] 800fac8: 683b ldr r3, [r7, #0] 800faca: 781b ldrb r3, [r3, #0] 800facc: 009b lsls r3, r3, #2 800face: 441a add r2, r3 800fad0: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 800fad4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fad8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fadc: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800fae0: f043 0380 orr.w r3, r3, #128 @ 0x80 800fae4: b29b uxth r3, r3 800fae6: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800fae8: 687a ldr r2, [r7, #4] 800faea: 683b ldr r3, [r7, #0] 800faec: 781b ldrb r3, [r3, #0] 800faee: 009b lsls r3, r3, #2 800faf0: 4413 add r3, r2 800faf2: 881b ldrh r3, [r3, #0] 800faf4: f8a7 306a strh.w r3, [r7, #106] @ 0x6a 800faf8: f8b7 306a ldrh.w r3, [r7, #106] @ 0x6a 800fafc: f003 0340 and.w r3, r3, #64 @ 0x40 800fb00: 2b00 cmp r3, #0 800fb02: d01d beq.n 800fb40 800fb04: 687a ldr r2, [r7, #4] 800fb06: 683b ldr r3, [r7, #0] 800fb08: 781b ldrb r3, [r3, #0] 800fb0a: 009b lsls r3, r3, #2 800fb0c: 4413 add r3, r2 800fb0e: 881b ldrh r3, [r3, #0] 800fb10: b29b uxth r3, r3 800fb12: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fb16: f023 0370 bic.w r3, r3, #112 @ 0x70 800fb1a: f8a7 3068 strh.w r3, [r7, #104] @ 0x68 800fb1e: 687a ldr r2, [r7, #4] 800fb20: 683b ldr r3, [r7, #0] 800fb22: 781b ldrb r3, [r3, #0] 800fb24: 009b lsls r3, r3, #2 800fb26: 441a add r2, r3 800fb28: f8b7 3068 ldrh.w r3, [r7, #104] @ 0x68 800fb2c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fb30: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fb34: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fb38: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800fb3c: b29b uxth r3, r3 800fb3e: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 800fb40: 683b ldr r3, [r7, #0] 800fb42: 78db ldrb r3, [r3, #3] 800fb44: 2b01 cmp r3, #1 800fb46: d024 beq.n 800fb92 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 800fb48: 687a ldr r2, [r7, #4] 800fb4a: 683b ldr r3, [r7, #0] 800fb4c: 781b ldrb r3, [r3, #0] 800fb4e: 009b lsls r3, r3, #2 800fb50: 4413 add r3, r2 800fb52: 881b ldrh r3, [r3, #0] 800fb54: b29b uxth r3, r3 800fb56: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fb5a: f023 0340 bic.w r3, r3, #64 @ 0x40 800fb5e: f8a7 3064 strh.w r3, [r7, #100] @ 0x64 800fb62: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64 800fb66: f083 0320 eor.w r3, r3, #32 800fb6a: f8a7 3064 strh.w r3, [r7, #100] @ 0x64 800fb6e: 687a ldr r2, [r7, #4] 800fb70: 683b ldr r3, [r7, #0] 800fb72: 781b ldrb r3, [r3, #0] 800fb74: 009b lsls r3, r3, #2 800fb76: 441a add r2, r3 800fb78: f8b7 3064 ldrh.w r3, [r7, #100] @ 0x64 800fb7c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fb80: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fb84: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fb88: f043 0380 orr.w r3, r3, #128 @ 0x80 800fb8c: b29b uxth r3, r3 800fb8e: 8013 strh r3, [r2, #0] 800fb90: e01d b.n 800fbce } else { /* Configure TX Endpoint to disabled state */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800fb92: 687a ldr r2, [r7, #4] 800fb94: 683b ldr r3, [r7, #0] 800fb96: 781b ldrb r3, [r3, #0] 800fb98: 009b lsls r3, r3, #2 800fb9a: 4413 add r3, r2 800fb9c: 881b ldrh r3, [r3, #0] 800fb9e: b29b uxth r3, r3 800fba0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fba4: f023 0340 bic.w r3, r3, #64 @ 0x40 800fba8: f8a7 3066 strh.w r3, [r7, #102] @ 0x66 800fbac: 687a ldr r2, [r7, #4] 800fbae: 683b ldr r3, [r7, #0] 800fbb0: 781b ldrb r3, [r3, #0] 800fbb2: 009b lsls r3, r3, #2 800fbb4: 441a add r2, r3 800fbb6: f8b7 3066 ldrh.w r3, [r7, #102] @ 0x66 800fbba: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fbbe: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fbc2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fbc6: f043 0380 orr.w r3, r3, #128 @ 0x80 800fbca: b29b uxth r3, r3 800fbcc: 8013 strh r3, [r2, #0] } PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800fbce: 687a ldr r2, [r7, #4] 800fbd0: 683b ldr r3, [r7, #0] 800fbd2: 781b ldrb r3, [r3, #0] 800fbd4: 009b lsls r3, r3, #2 800fbd6: 4413 add r3, r2 800fbd8: 881b ldrh r3, [r3, #0] 800fbda: b29b uxth r3, r3 800fbdc: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800fbe0: f023 0370 bic.w r3, r3, #112 @ 0x70 800fbe4: f8a7 3062 strh.w r3, [r7, #98] @ 0x62 800fbe8: 687a ldr r2, [r7, #4] 800fbea: 683b ldr r3, [r7, #0] 800fbec: 781b ldrb r3, [r3, #0] 800fbee: 009b lsls r3, r3, #2 800fbf0: 441a add r2, r3 800fbf2: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62 800fbf6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fbfa: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fbfe: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fc02: f043 0380 orr.w r3, r3, #128 @ 0x80 800fc06: b29b uxth r3, r3 800fc08: 8013 strh r3, [r2, #0] } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return ret; 800fc0a: f897 3097 ldrb.w r3, [r7, #151] @ 0x97 } 800fc0e: 4618 mov r0, r3 800fc10: 379c adds r7, #156 @ 0x9c 800fc12: 46bd mov sp, r7 800fc14: f85d 7b04 ldr.w r7, [sp], #4 800fc18: 4770 bx lr 800fc1a: bf00 nop 0800fc1c : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800fc1c: b480 push {r7} 800fc1e: b08d sub sp, #52 @ 0x34 800fc20: af00 add r7, sp, #0 800fc22: 6078 str r0, [r7, #4] 800fc24: 6039 str r1, [r7, #0] if (ep->doublebuffer == 0U) 800fc26: 683b ldr r3, [r7, #0] 800fc28: 7b1b ldrb r3, [r3, #12] 800fc2a: 2b00 cmp r3, #0 800fc2c: f040 808e bne.w 800fd4c { if (ep->is_in != 0U) 800fc30: 683b ldr r3, [r7, #0] 800fc32: 785b ldrb r3, [r3, #1] 800fc34: 2b00 cmp r3, #0 800fc36: d044 beq.n 800fcc2 { PCD_CLEAR_TX_DTOG(USBx, ep->num); 800fc38: 687a ldr r2, [r7, #4] 800fc3a: 683b ldr r3, [r7, #0] 800fc3c: 781b ldrb r3, [r3, #0] 800fc3e: 009b lsls r3, r3, #2 800fc40: 4413 add r3, r2 800fc42: 881b ldrh r3, [r3, #0] 800fc44: 81bb strh r3, [r7, #12] 800fc46: 89bb ldrh r3, [r7, #12] 800fc48: f003 0340 and.w r3, r3, #64 @ 0x40 800fc4c: 2b00 cmp r3, #0 800fc4e: d01b beq.n 800fc88 800fc50: 687a ldr r2, [r7, #4] 800fc52: 683b ldr r3, [r7, #0] 800fc54: 781b ldrb r3, [r3, #0] 800fc56: 009b lsls r3, r3, #2 800fc58: 4413 add r3, r2 800fc5a: 881b ldrh r3, [r3, #0] 800fc5c: b29b uxth r3, r3 800fc5e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fc62: f023 0370 bic.w r3, r3, #112 @ 0x70 800fc66: 817b strh r3, [r7, #10] 800fc68: 687a ldr r2, [r7, #4] 800fc6a: 683b ldr r3, [r7, #0] 800fc6c: 781b ldrb r3, [r3, #0] 800fc6e: 009b lsls r3, r3, #2 800fc70: 441a add r2, r3 800fc72: 897b ldrh r3, [r7, #10] 800fc74: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fc78: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fc7c: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fc80: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800fc84: b29b uxth r3, r3 800fc86: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800fc88: 687a ldr r2, [r7, #4] 800fc8a: 683b ldr r3, [r7, #0] 800fc8c: 781b ldrb r3, [r3, #0] 800fc8e: 009b lsls r3, r3, #2 800fc90: 4413 add r3, r2 800fc92: 881b ldrh r3, [r3, #0] 800fc94: b29b uxth r3, r3 800fc96: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fc9a: f023 0340 bic.w r3, r3, #64 @ 0x40 800fc9e: 813b strh r3, [r7, #8] 800fca0: 687a ldr r2, [r7, #4] 800fca2: 683b ldr r3, [r7, #0] 800fca4: 781b ldrb r3, [r3, #0] 800fca6: 009b lsls r3, r3, #2 800fca8: 441a add r2, r3 800fcaa: 893b ldrh r3, [r7, #8] 800fcac: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fcb0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fcb4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fcb8: f043 0380 orr.w r3, r3, #128 @ 0x80 800fcbc: b29b uxth r3, r3 800fcbe: 8013 strh r3, [r2, #0] 800fcc0: e192 b.n 800ffe8 } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); 800fcc2: 687a ldr r2, [r7, #4] 800fcc4: 683b ldr r3, [r7, #0] 800fcc6: 781b ldrb r3, [r3, #0] 800fcc8: 009b lsls r3, r3, #2 800fcca: 4413 add r3, r2 800fccc: 881b ldrh r3, [r3, #0] 800fcce: 827b strh r3, [r7, #18] 800fcd0: 8a7b ldrh r3, [r7, #18] 800fcd2: f403 4380 and.w r3, r3, #16384 @ 0x4000 800fcd6: 2b00 cmp r3, #0 800fcd8: d01b beq.n 800fd12 800fcda: 687a ldr r2, [r7, #4] 800fcdc: 683b ldr r3, [r7, #0] 800fcde: 781b ldrb r3, [r3, #0] 800fce0: 009b lsls r3, r3, #2 800fce2: 4413 add r3, r2 800fce4: 881b ldrh r3, [r3, #0] 800fce6: b29b uxth r3, r3 800fce8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fcec: f023 0370 bic.w r3, r3, #112 @ 0x70 800fcf0: 823b strh r3, [r7, #16] 800fcf2: 687a ldr r2, [r7, #4] 800fcf4: 683b ldr r3, [r7, #0] 800fcf6: 781b ldrb r3, [r3, #0] 800fcf8: 009b lsls r3, r3, #2 800fcfa: 441a add r2, r3 800fcfc: 8a3b ldrh r3, [r7, #16] 800fcfe: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fd02: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fd06: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800fd0a: f043 0380 orr.w r3, r3, #128 @ 0x80 800fd0e: b29b uxth r3, r3 800fd10: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800fd12: 687a ldr r2, [r7, #4] 800fd14: 683b ldr r3, [r7, #0] 800fd16: 781b ldrb r3, [r3, #0] 800fd18: 009b lsls r3, r3, #2 800fd1a: 4413 add r3, r2 800fd1c: 881b ldrh r3, [r3, #0] 800fd1e: b29b uxth r3, r3 800fd20: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800fd24: f023 0370 bic.w r3, r3, #112 @ 0x70 800fd28: 81fb strh r3, [r7, #14] 800fd2a: 687a ldr r2, [r7, #4] 800fd2c: 683b ldr r3, [r7, #0] 800fd2e: 781b ldrb r3, [r3, #0] 800fd30: 009b lsls r3, r3, #2 800fd32: 441a add r2, r3 800fd34: 89fb ldrh r3, [r7, #14] 800fd36: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fd3a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fd3e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fd42: f043 0380 orr.w r3, r3, #128 @ 0x80 800fd46: b29b uxth r3, r3 800fd48: 8013 strh r3, [r2, #0] 800fd4a: e14d b.n 800ffe8 } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer */ else { if (ep->is_in == 0U) 800fd4c: 683b ldr r3, [r7, #0] 800fd4e: 785b ldrb r3, [r3, #1] 800fd50: 2b00 cmp r3, #0 800fd52: f040 80a5 bne.w 800fea0 { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800fd56: 687a ldr r2, [r7, #4] 800fd58: 683b ldr r3, [r7, #0] 800fd5a: 781b ldrb r3, [r3, #0] 800fd5c: 009b lsls r3, r3, #2 800fd5e: 4413 add r3, r2 800fd60: 881b ldrh r3, [r3, #0] 800fd62: 843b strh r3, [r7, #32] 800fd64: 8c3b ldrh r3, [r7, #32] 800fd66: f403 4380 and.w r3, r3, #16384 @ 0x4000 800fd6a: 2b00 cmp r3, #0 800fd6c: d01b beq.n 800fda6 800fd6e: 687a ldr r2, [r7, #4] 800fd70: 683b ldr r3, [r7, #0] 800fd72: 781b ldrb r3, [r3, #0] 800fd74: 009b lsls r3, r3, #2 800fd76: 4413 add r3, r2 800fd78: 881b ldrh r3, [r3, #0] 800fd7a: b29b uxth r3, r3 800fd7c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fd80: f023 0370 bic.w r3, r3, #112 @ 0x70 800fd84: 83fb strh r3, [r7, #30] 800fd86: 687a ldr r2, [r7, #4] 800fd88: 683b ldr r3, [r7, #0] 800fd8a: 781b ldrb r3, [r3, #0] 800fd8c: 009b lsls r3, r3, #2 800fd8e: 441a add r2, r3 800fd90: 8bfb ldrh r3, [r7, #30] 800fd92: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fd96: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fd9a: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800fd9e: f043 0380 orr.w r3, r3, #128 @ 0x80 800fda2: b29b uxth r3, r3 800fda4: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800fda6: 687a ldr r2, [r7, #4] 800fda8: 683b ldr r3, [r7, #0] 800fdaa: 781b ldrb r3, [r3, #0] 800fdac: 009b lsls r3, r3, #2 800fdae: 4413 add r3, r2 800fdb0: 881b ldrh r3, [r3, #0] 800fdb2: 83bb strh r3, [r7, #28] 800fdb4: 8bbb ldrh r3, [r7, #28] 800fdb6: f003 0340 and.w r3, r3, #64 @ 0x40 800fdba: 2b00 cmp r3, #0 800fdbc: d01b beq.n 800fdf6 800fdbe: 687a ldr r2, [r7, #4] 800fdc0: 683b ldr r3, [r7, #0] 800fdc2: 781b ldrb r3, [r3, #0] 800fdc4: 009b lsls r3, r3, #2 800fdc6: 4413 add r3, r2 800fdc8: 881b ldrh r3, [r3, #0] 800fdca: b29b uxth r3, r3 800fdcc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fdd0: f023 0370 bic.w r3, r3, #112 @ 0x70 800fdd4: 837b strh r3, [r7, #26] 800fdd6: 687a ldr r2, [r7, #4] 800fdd8: 683b ldr r3, [r7, #0] 800fdda: 781b ldrb r3, [r3, #0] 800fddc: 009b lsls r3, r3, #2 800fdde: 441a add r2, r3 800fde0: 8b7b ldrh r3, [r7, #26] 800fde2: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fde6: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fdea: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fdee: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800fdf2: b29b uxth r3, r3 800fdf4: 8013 strh r3, [r2, #0] /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); 800fdf6: 687a ldr r2, [r7, #4] 800fdf8: 683b ldr r3, [r7, #0] 800fdfa: 781b ldrb r3, [r3, #0] 800fdfc: 009b lsls r3, r3, #2 800fdfe: 4413 add r3, r2 800fe00: 881b ldrh r3, [r3, #0] 800fe02: b29b uxth r3, r3 800fe04: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fe08: f023 0370 bic.w r3, r3, #112 @ 0x70 800fe0c: 833b strh r3, [r7, #24] 800fe0e: 687a ldr r2, [r7, #4] 800fe10: 683b ldr r3, [r7, #0] 800fe12: 781b ldrb r3, [r3, #0] 800fe14: 009b lsls r3, r3, #2 800fe16: 441a add r2, r3 800fe18: 8b3b ldrh r3, [r7, #24] 800fe1a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fe1e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fe22: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fe26: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800fe2a: b29b uxth r3, r3 800fe2c: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800fe2e: 687a ldr r2, [r7, #4] 800fe30: 683b ldr r3, [r7, #0] 800fe32: 781b ldrb r3, [r3, #0] 800fe34: 009b lsls r3, r3, #2 800fe36: 4413 add r3, r2 800fe38: 881b ldrh r3, [r3, #0] 800fe3a: b29b uxth r3, r3 800fe3c: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800fe40: f023 0370 bic.w r3, r3, #112 @ 0x70 800fe44: 82fb strh r3, [r7, #22] 800fe46: 687a ldr r2, [r7, #4] 800fe48: 683b ldr r3, [r7, #0] 800fe4a: 781b ldrb r3, [r3, #0] 800fe4c: 009b lsls r3, r3, #2 800fe4e: 441a add r2, r3 800fe50: 8afb ldrh r3, [r7, #22] 800fe52: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fe56: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fe5a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fe5e: f043 0380 orr.w r3, r3, #128 @ 0x80 800fe62: b29b uxth r3, r3 800fe64: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800fe66: 687a ldr r2, [r7, #4] 800fe68: 683b ldr r3, [r7, #0] 800fe6a: 781b ldrb r3, [r3, #0] 800fe6c: 009b lsls r3, r3, #2 800fe6e: 4413 add r3, r2 800fe70: 881b ldrh r3, [r3, #0] 800fe72: b29b uxth r3, r3 800fe74: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800fe78: f023 0340 bic.w r3, r3, #64 @ 0x40 800fe7c: 82bb strh r3, [r7, #20] 800fe7e: 687a ldr r2, [r7, #4] 800fe80: 683b ldr r3, [r7, #0] 800fe82: 781b ldrb r3, [r3, #0] 800fe84: 009b lsls r3, r3, #2 800fe86: 441a add r2, r3 800fe88: 8abb ldrh r3, [r7, #20] 800fe8a: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fe8e: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fe92: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800fe96: f043 0380 orr.w r3, r3, #128 @ 0x80 800fe9a: b29b uxth r3, r3 800fe9c: 8013 strh r3, [r2, #0] 800fe9e: e0a3 b.n 800ffe8 } else { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); 800fea0: 687a ldr r2, [r7, #4] 800fea2: 683b ldr r3, [r7, #0] 800fea4: 781b ldrb r3, [r3, #0] 800fea6: 009b lsls r3, r3, #2 800fea8: 4413 add r3, r2 800feaa: 881b ldrh r3, [r3, #0] 800feac: 85fb strh r3, [r7, #46] @ 0x2e 800feae: 8dfb ldrh r3, [r7, #46] @ 0x2e 800feb0: f403 4380 and.w r3, r3, #16384 @ 0x4000 800feb4: 2b00 cmp r3, #0 800feb6: d01b beq.n 800fef0 800feb8: 687a ldr r2, [r7, #4] 800feba: 683b ldr r3, [r7, #0] 800febc: 781b ldrb r3, [r3, #0] 800febe: 009b lsls r3, r3, #2 800fec0: 4413 add r3, r2 800fec2: 881b ldrh r3, [r3, #0] 800fec4: b29b uxth r3, r3 800fec6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800feca: f023 0370 bic.w r3, r3, #112 @ 0x70 800fece: 85bb strh r3, [r7, #44] @ 0x2c 800fed0: 687a ldr r2, [r7, #4] 800fed2: 683b ldr r3, [r7, #0] 800fed4: 781b ldrb r3, [r3, #0] 800fed6: 009b lsls r3, r3, #2 800fed8: 441a add r2, r3 800feda: 8dbb ldrh r3, [r7, #44] @ 0x2c 800fedc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800fee0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800fee4: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800fee8: f043 0380 orr.w r3, r3, #128 @ 0x80 800feec: b29b uxth r3, r3 800feee: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); 800fef0: 687a ldr r2, [r7, #4] 800fef2: 683b ldr r3, [r7, #0] 800fef4: 781b ldrb r3, [r3, #0] 800fef6: 009b lsls r3, r3, #2 800fef8: 4413 add r3, r2 800fefa: 881b ldrh r3, [r3, #0] 800fefc: 857b strh r3, [r7, #42] @ 0x2a 800fefe: 8d7b ldrh r3, [r7, #42] @ 0x2a 800ff00: f003 0340 and.w r3, r3, #64 @ 0x40 800ff04: 2b00 cmp r3, #0 800ff06: d01b beq.n 800ff40 800ff08: 687a ldr r2, [r7, #4] 800ff0a: 683b ldr r3, [r7, #0] 800ff0c: 781b ldrb r3, [r3, #0] 800ff0e: 009b lsls r3, r3, #2 800ff10: 4413 add r3, r2 800ff12: 881b ldrh r3, [r3, #0] 800ff14: b29b uxth r3, r3 800ff16: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ff1a: f023 0370 bic.w r3, r3, #112 @ 0x70 800ff1e: 853b strh r3, [r7, #40] @ 0x28 800ff20: 687a ldr r2, [r7, #4] 800ff22: 683b ldr r3, [r7, #0] 800ff24: 781b ldrb r3, [r3, #0] 800ff26: 009b lsls r3, r3, #2 800ff28: 441a add r2, r3 800ff2a: 8d3b ldrh r3, [r7, #40] @ 0x28 800ff2c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ff30: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ff34: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ff38: f043 03c0 orr.w r3, r3, #192 @ 0xc0 800ff3c: b29b uxth r3, r3 800ff3e: 8013 strh r3, [r2, #0] PCD_RX_DTOG(USBx, ep->num); 800ff40: 687a ldr r2, [r7, #4] 800ff42: 683b ldr r3, [r7, #0] 800ff44: 781b ldrb r3, [r3, #0] 800ff46: 009b lsls r3, r3, #2 800ff48: 4413 add r3, r2 800ff4a: 881b ldrh r3, [r3, #0] 800ff4c: b29b uxth r3, r3 800ff4e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ff52: f023 0370 bic.w r3, r3, #112 @ 0x70 800ff56: 84fb strh r3, [r7, #38] @ 0x26 800ff58: 687a ldr r2, [r7, #4] 800ff5a: 683b ldr r3, [r7, #0] 800ff5c: 781b ldrb r3, [r3, #0] 800ff5e: 009b lsls r3, r3, #2 800ff60: 441a add r2, r3 800ff62: 8cfb ldrh r3, [r7, #38] @ 0x26 800ff64: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ff68: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ff6c: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800ff70: f043 0380 orr.w r3, r3, #128 @ 0x80 800ff74: b29b uxth r3, r3 800ff76: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 800ff78: 687a ldr r2, [r7, #4] 800ff7a: 683b ldr r3, [r7, #0] 800ff7c: 781b ldrb r3, [r3, #0] 800ff7e: 009b lsls r3, r3, #2 800ff80: 4413 add r3, r2 800ff82: 881b ldrh r3, [r3, #0] 800ff84: b29b uxth r3, r3 800ff86: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 800ff8a: f023 0340 bic.w r3, r3, #64 @ 0x40 800ff8e: 84bb strh r3, [r7, #36] @ 0x24 800ff90: 687a ldr r2, [r7, #4] 800ff92: 683b ldr r3, [r7, #0] 800ff94: 781b ldrb r3, [r3, #0] 800ff96: 009b lsls r3, r3, #2 800ff98: 441a add r2, r3 800ff9a: 8cbb ldrh r3, [r7, #36] @ 0x24 800ff9c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ffa0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ffa4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ffa8: f043 0380 orr.w r3, r3, #128 @ 0x80 800ffac: b29b uxth r3, r3 800ffae: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 800ffb0: 687a ldr r2, [r7, #4] 800ffb2: 683b ldr r3, [r7, #0] 800ffb4: 781b ldrb r3, [r3, #0] 800ffb6: 009b lsls r3, r3, #2 800ffb8: 4413 add r3, r2 800ffba: 881b ldrh r3, [r3, #0] 800ffbc: b29b uxth r3, r3 800ffbe: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800ffc2: f023 0370 bic.w r3, r3, #112 @ 0x70 800ffc6: 847b strh r3, [r7, #34] @ 0x22 800ffc8: 687a ldr r2, [r7, #4] 800ffca: 683b ldr r3, [r7, #0] 800ffcc: 781b ldrb r3, [r3, #0] 800ffce: 009b lsls r3, r3, #2 800ffd0: 441a add r2, r3 800ffd2: 8c7b ldrh r3, [r7, #34] @ 0x22 800ffd4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 800ffd8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 800ffdc: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800ffe0: f043 0380 orr.w r3, r3, #128 @ 0x80 800ffe4: b29b uxth r3, r3 800ffe6: 8013 strh r3, [r2, #0] } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; 800ffe8: 2300 movs r3, #0 } 800ffea: 4618 mov r0, r3 800ffec: 3734 adds r7, #52 @ 0x34 800ffee: 46bd mov sp, r7 800fff0: f85d 7b04 ldr.w r7, [sp], #4 800fff4: 4770 bx lr 0800fff6 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 800fff6: b580 push {r7, lr} 800fff8: b0ac sub sp, #176 @ 0xb0 800fffa: af00 add r7, sp, #0 800fffc: 6078 str r0, [r7, #4] 800fffe: 6039 str r1, [r7, #0] uint16_t pmabuffer; uint16_t wEPVal; #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* IN endpoint */ if (ep->is_in == 1U) 8010000: 683b ldr r3, [r7, #0] 8010002: 785b ldrb r3, [r3, #1] 8010004: 2b01 cmp r3, #1 8010006: f040 84ca bne.w 801099e { /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) 801000a: 683b ldr r3, [r7, #0] 801000c: 699a ldr r2, [r3, #24] 801000e: 683b ldr r3, [r7, #0] 8010010: 691b ldr r3, [r3, #16] 8010012: 429a cmp r2, r3 8010014: d904 bls.n 8010020 { len = ep->maxpacket; 8010016: 683b ldr r3, [r7, #0] 8010018: 691b ldr r3, [r3, #16] 801001a: f8c7 30ac str.w r3, [r7, #172] @ 0xac 801001e: e003 b.n 8010028 } else { len = ep->xfer_len; 8010020: 683b ldr r3, [r7, #0] 8010022: 699b ldr r3, [r3, #24] 8010024: f8c7 30ac str.w r3, [r7, #172] @ 0xac } /* configure and validate Tx endpoint */ if (ep->doublebuffer == 0U) 8010028: 683b ldr r3, [r7, #0] 801002a: 7b1b ldrb r3, [r3, #12] 801002c: 2b00 cmp r3, #0 801002e: d122 bne.n 8010076 { USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); 8010030: 683b ldr r3, [r7, #0] 8010032: 6959 ldr r1, [r3, #20] 8010034: 683b ldr r3, [r7, #0] 8010036: 88da ldrh r2, [r3, #6] 8010038: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801003c: b29b uxth r3, r3 801003e: 6878 ldr r0, [r7, #4] 8010040: f000 febd bl 8010dbe PCD_SET_EP_TX_CNT(USBx, ep->num, len); 8010044: 687b ldr r3, [r7, #4] 8010046: 613b str r3, [r7, #16] 8010048: 687b ldr r3, [r7, #4] 801004a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 801004e: b29b uxth r3, r3 8010050: 461a mov r2, r3 8010052: 693b ldr r3, [r7, #16] 8010054: 4413 add r3, r2 8010056: 613b str r3, [r7, #16] 8010058: 683b ldr r3, [r7, #0] 801005a: 781b ldrb r3, [r3, #0] 801005c: 00da lsls r2, r3, #3 801005e: 693b ldr r3, [r7, #16] 8010060: 4413 add r3, r2 8010062: f203 4302 addw r3, r3, #1026 @ 0x402 8010066: 60fb str r3, [r7, #12] 8010068: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801006c: b29a uxth r2, r3 801006e: 68fb ldr r3, [r7, #12] 8010070: 801a strh r2, [r3, #0] 8010072: f000 bc6f b.w 8010954 } #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* double buffer bulk management */ if (ep->type == EP_TYPE_BULK) 8010076: 683b ldr r3, [r7, #0] 8010078: 78db ldrb r3, [r3, #3] 801007a: 2b02 cmp r3, #2 801007c: f040 831e bne.w 80106bc { if (ep->xfer_len_db > ep->maxpacket) 8010080: 683b ldr r3, [r7, #0] 8010082: 6a1a ldr r2, [r3, #32] 8010084: 683b ldr r3, [r7, #0] 8010086: 691b ldr r3, [r3, #16] 8010088: 429a cmp r2, r3 801008a: f240 82cf bls.w 801062c { /* enable double buffer */ PCD_SET_BULK_EP_DBUF(USBx, ep->num); 801008e: 687a ldr r2, [r7, #4] 8010090: 683b ldr r3, [r7, #0] 8010092: 781b ldrb r3, [r3, #0] 8010094: 009b lsls r3, r3, #2 8010096: 4413 add r3, r2 8010098: 881b ldrh r3, [r3, #0] 801009a: b29b uxth r3, r3 801009c: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80100a0: f023 0370 bic.w r3, r3, #112 @ 0x70 80100a4: f8a7 3056 strh.w r3, [r7, #86] @ 0x56 80100a8: 687a ldr r2, [r7, #4] 80100aa: 683b ldr r3, [r7, #0] 80100ac: 781b ldrb r3, [r3, #0] 80100ae: 009b lsls r3, r3, #2 80100b0: 441a add r2, r3 80100b2: f8b7 3056 ldrh.w r3, [r7, #86] @ 0x56 80100b6: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80100ba: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80100be: f443 4301 orr.w r3, r3, #33024 @ 0x8100 80100c2: f043 0380 orr.w r3, r3, #128 @ 0x80 80100c6: b29b uxth r3, r3 80100c8: 8013 strh r3, [r2, #0] /* each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; 80100ca: 683b ldr r3, [r7, #0] 80100cc: 6a1a ldr r2, [r3, #32] 80100ce: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80100d2: 1ad2 subs r2, r2, r3 80100d4: 683b ldr r3, [r7, #0] 80100d6: 621a str r2, [r3, #32] /* Fill the two first buffer in the Buffer0 & Buffer1 */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) 80100d8: 687a ldr r2, [r7, #4] 80100da: 683b ldr r3, [r7, #0] 80100dc: 781b ldrb r3, [r3, #0] 80100de: 009b lsls r3, r3, #2 80100e0: 4413 add r3, r2 80100e2: 881b ldrh r3, [r3, #0] 80100e4: b29b uxth r3, r3 80100e6: f003 0340 and.w r3, r3, #64 @ 0x40 80100ea: 2b00 cmp r3, #0 80100ec: f000 814f beq.w 801038e { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 80100f0: 687b ldr r3, [r7, #4] 80100f2: 633b str r3, [r7, #48] @ 0x30 80100f4: 683b ldr r3, [r7, #0] 80100f6: 785b ldrb r3, [r3, #1] 80100f8: 2b00 cmp r3, #0 80100fa: d16b bne.n 80101d4 80100fc: 687b ldr r3, [r7, #4] 80100fe: 62bb str r3, [r7, #40] @ 0x28 8010100: 687b ldr r3, [r7, #4] 8010102: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8010106: b29b uxth r3, r3 8010108: 461a mov r2, r3 801010a: 6abb ldr r3, [r7, #40] @ 0x28 801010c: 4413 add r3, r2 801010e: 62bb str r3, [r7, #40] @ 0x28 8010110: 683b ldr r3, [r7, #0] 8010112: 781b ldrb r3, [r3, #0] 8010114: 00da lsls r2, r3, #3 8010116: 6abb ldr r3, [r7, #40] @ 0x28 8010118: 4413 add r3, r2 801011a: f203 4306 addw r3, r3, #1030 @ 0x406 801011e: 627b str r3, [r7, #36] @ 0x24 8010120: 6a7b ldr r3, [r7, #36] @ 0x24 8010122: 881b ldrh r3, [r3, #0] 8010124: b29b uxth r3, r3 8010126: f3c3 0309 ubfx r3, r3, #0, #10 801012a: b29a uxth r2, r3 801012c: 6a7b ldr r3, [r7, #36] @ 0x24 801012e: 801a strh r2, [r3, #0] 8010130: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010134: 2b00 cmp r3, #0 8010136: d10a bne.n 801014e 8010138: 6a7b ldr r3, [r7, #36] @ 0x24 801013a: 881b ldrh r3, [r3, #0] 801013c: b29b uxth r3, r3 801013e: ea6f 4343 mvn.w r3, r3, lsl #17 8010142: ea6f 4353 mvn.w r3, r3, lsr #17 8010146: b29a uxth r2, r3 8010148: 6a7b ldr r3, [r7, #36] @ 0x24 801014a: 801a strh r2, [r3, #0] 801014c: e05b b.n 8010206 801014e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010152: 2b3e cmp r3, #62 @ 0x3e 8010154: d81c bhi.n 8010190 8010156: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801015a: 085b lsrs r3, r3, #1 801015c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8010160: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010164: f003 0301 and.w r3, r3, #1 8010168: 2b00 cmp r3, #0 801016a: d004 beq.n 8010176 801016c: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8010170: 3301 adds r3, #1 8010172: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8010176: 6a7b ldr r3, [r7, #36] @ 0x24 8010178: 881b ldrh r3, [r3, #0] 801017a: b29a uxth r2, r3 801017c: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8010180: b29b uxth r3, r3 8010182: 029b lsls r3, r3, #10 8010184: b29b uxth r3, r3 8010186: 4313 orrs r3, r2 8010188: b29a uxth r2, r3 801018a: 6a7b ldr r3, [r7, #36] @ 0x24 801018c: 801a strh r2, [r3, #0] 801018e: e03a b.n 8010206 8010190: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010194: 095b lsrs r3, r3, #5 8010196: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 801019a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801019e: f003 031f and.w r3, r3, #31 80101a2: 2b00 cmp r3, #0 80101a4: d104 bne.n 80101b0 80101a6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80101aa: 3b01 subs r3, #1 80101ac: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 80101b0: 6a7b ldr r3, [r7, #36] @ 0x24 80101b2: 881b ldrh r3, [r3, #0] 80101b4: b29a uxth r2, r3 80101b6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80101ba: b29b uxth r3, r3 80101bc: 029b lsls r3, r3, #10 80101be: b29b uxth r3, r3 80101c0: 4313 orrs r3, r2 80101c2: b29b uxth r3, r3 80101c4: ea6f 4343 mvn.w r3, r3, lsl #17 80101c8: ea6f 4353 mvn.w r3, r3, lsr #17 80101cc: b29a uxth r2, r3 80101ce: 6a7b ldr r3, [r7, #36] @ 0x24 80101d0: 801a strh r2, [r3, #0] 80101d2: e018 b.n 8010206 80101d4: 683b ldr r3, [r7, #0] 80101d6: 785b ldrb r3, [r3, #1] 80101d8: 2b01 cmp r3, #1 80101da: d114 bne.n 8010206 80101dc: 687b ldr r3, [r7, #4] 80101de: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80101e2: b29b uxth r3, r3 80101e4: 461a mov r2, r3 80101e6: 6b3b ldr r3, [r7, #48] @ 0x30 80101e8: 4413 add r3, r2 80101ea: 633b str r3, [r7, #48] @ 0x30 80101ec: 683b ldr r3, [r7, #0] 80101ee: 781b ldrb r3, [r3, #0] 80101f0: 00da lsls r2, r3, #3 80101f2: 6b3b ldr r3, [r7, #48] @ 0x30 80101f4: 4413 add r3, r2 80101f6: f203 4306 addw r3, r3, #1030 @ 0x406 80101fa: 62fb str r3, [r7, #44] @ 0x2c 80101fc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010200: b29a uxth r2, r3 8010202: 6afb ldr r3, [r7, #44] @ 0x2c 8010204: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 8010206: 683b ldr r3, [r7, #0] 8010208: 895b ldrh r3, [r3, #10] 801020a: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 801020e: 683b ldr r3, [r7, #0] 8010210: 6959 ldr r1, [r3, #20] 8010212: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010216: b29b uxth r3, r3 8010218: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 801021c: 6878 ldr r0, [r7, #4] 801021e: f000 fdce bl 8010dbe ep->xfer_buff += len; 8010222: 683b ldr r3, [r7, #0] 8010224: 695a ldr r2, [r3, #20] 8010226: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801022a: 441a add r2, r3 801022c: 683b ldr r3, [r7, #0] 801022e: 615a str r2, [r3, #20] if (ep->xfer_len_db > ep->maxpacket) 8010230: 683b ldr r3, [r7, #0] 8010232: 6a1a ldr r2, [r3, #32] 8010234: 683b ldr r3, [r7, #0] 8010236: 691b ldr r3, [r3, #16] 8010238: 429a cmp r2, r3 801023a: d907 bls.n 801024c { ep->xfer_len_db -= len; 801023c: 683b ldr r3, [r7, #0] 801023e: 6a1a ldr r2, [r3, #32] 8010240: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010244: 1ad2 subs r2, r2, r3 8010246: 683b ldr r3, [r7, #0] 8010248: 621a str r2, [r3, #32] 801024a: e006 b.n 801025a } else { len = ep->xfer_len_db; 801024c: 683b ldr r3, [r7, #0] 801024e: 6a1b ldr r3, [r3, #32] 8010250: f8c7 30ac str.w r3, [r7, #172] @ 0xac ep->xfer_len_db = 0U; 8010254: 683b ldr r3, [r7, #0] 8010256: 2200 movs r2, #0 8010258: 621a str r2, [r3, #32] } /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 801025a: 683b ldr r3, [r7, #0] 801025c: 785b ldrb r3, [r3, #1] 801025e: 2b00 cmp r3, #0 8010260: d16b bne.n 801033a 8010262: 687b ldr r3, [r7, #4] 8010264: 61bb str r3, [r7, #24] 8010266: 687b ldr r3, [r7, #4] 8010268: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 801026c: b29b uxth r3, r3 801026e: 461a mov r2, r3 8010270: 69bb ldr r3, [r7, #24] 8010272: 4413 add r3, r2 8010274: 61bb str r3, [r7, #24] 8010276: 683b ldr r3, [r7, #0] 8010278: 781b ldrb r3, [r3, #0] 801027a: 00da lsls r2, r3, #3 801027c: 69bb ldr r3, [r7, #24] 801027e: 4413 add r3, r2 8010280: f203 4302 addw r3, r3, #1026 @ 0x402 8010284: 617b str r3, [r7, #20] 8010286: 697b ldr r3, [r7, #20] 8010288: 881b ldrh r3, [r3, #0] 801028a: b29b uxth r3, r3 801028c: f3c3 0309 ubfx r3, r3, #0, #10 8010290: b29a uxth r2, r3 8010292: 697b ldr r3, [r7, #20] 8010294: 801a strh r2, [r3, #0] 8010296: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801029a: 2b00 cmp r3, #0 801029c: d10a bne.n 80102b4 801029e: 697b ldr r3, [r7, #20] 80102a0: 881b ldrh r3, [r3, #0] 80102a2: b29b uxth r3, r3 80102a4: ea6f 4343 mvn.w r3, r3, lsl #17 80102a8: ea6f 4353 mvn.w r3, r3, lsr #17 80102ac: b29a uxth r2, r3 80102ae: 697b ldr r3, [r7, #20] 80102b0: 801a strh r2, [r3, #0] 80102b2: e05d b.n 8010370 80102b4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80102b8: 2b3e cmp r3, #62 @ 0x3e 80102ba: d81c bhi.n 80102f6 80102bc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80102c0: 085b lsrs r3, r3, #1 80102c2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 80102c6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80102ca: f003 0301 and.w r3, r3, #1 80102ce: 2b00 cmp r3, #0 80102d0: d004 beq.n 80102dc 80102d2: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 80102d6: 3301 adds r3, #1 80102d8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 80102dc: 697b ldr r3, [r7, #20] 80102de: 881b ldrh r3, [r3, #0] 80102e0: b29a uxth r2, r3 80102e2: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 80102e6: b29b uxth r3, r3 80102e8: 029b lsls r3, r3, #10 80102ea: b29b uxth r3, r3 80102ec: 4313 orrs r3, r2 80102ee: b29a uxth r2, r3 80102f0: 697b ldr r3, [r7, #20] 80102f2: 801a strh r2, [r3, #0] 80102f4: e03c b.n 8010370 80102f6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80102fa: 095b lsrs r3, r3, #5 80102fc: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 8010300: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010304: f003 031f and.w r3, r3, #31 8010308: 2b00 cmp r3, #0 801030a: d104 bne.n 8010316 801030c: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8010310: 3b01 subs r3, #1 8010312: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 8010316: 697b ldr r3, [r7, #20] 8010318: 881b ldrh r3, [r3, #0] 801031a: b29a uxth r2, r3 801031c: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8010320: b29b uxth r3, r3 8010322: 029b lsls r3, r3, #10 8010324: b29b uxth r3, r3 8010326: 4313 orrs r3, r2 8010328: b29b uxth r3, r3 801032a: ea6f 4343 mvn.w r3, r3, lsl #17 801032e: ea6f 4353 mvn.w r3, r3, lsr #17 8010332: b29a uxth r2, r3 8010334: 697b ldr r3, [r7, #20] 8010336: 801a strh r2, [r3, #0] 8010338: e01a b.n 8010370 801033a: 683b ldr r3, [r7, #0] 801033c: 785b ldrb r3, [r3, #1] 801033e: 2b01 cmp r3, #1 8010340: d116 bne.n 8010370 8010342: 687b ldr r3, [r7, #4] 8010344: 623b str r3, [r7, #32] 8010346: 687b ldr r3, [r7, #4] 8010348: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 801034c: b29b uxth r3, r3 801034e: 461a mov r2, r3 8010350: 6a3b ldr r3, [r7, #32] 8010352: 4413 add r3, r2 8010354: 623b str r3, [r7, #32] 8010356: 683b ldr r3, [r7, #0] 8010358: 781b ldrb r3, [r3, #0] 801035a: 00da lsls r2, r3, #3 801035c: 6a3b ldr r3, [r7, #32] 801035e: 4413 add r3, r2 8010360: f203 4302 addw r3, r3, #1026 @ 0x402 8010364: 61fb str r3, [r7, #28] 8010366: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801036a: b29a uxth r2, r3 801036c: 69fb ldr r3, [r7, #28] 801036e: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 8010370: 683b ldr r3, [r7, #0] 8010372: 891b ldrh r3, [r3, #8] 8010374: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 8010378: 683b ldr r3, [r7, #0] 801037a: 6959 ldr r1, [r3, #20] 801037c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010380: b29b uxth r3, r3 8010382: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 8010386: 6878 ldr r0, [r7, #4] 8010388: f000 fd19 bl 8010dbe 801038c: e2e2 b.n 8010954 } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 801038e: 683b ldr r3, [r7, #0] 8010390: 785b ldrb r3, [r3, #1] 8010392: 2b00 cmp r3, #0 8010394: d16b bne.n 801046e 8010396: 687b ldr r3, [r7, #4] 8010398: 64bb str r3, [r7, #72] @ 0x48 801039a: 687b ldr r3, [r7, #4] 801039c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80103a0: b29b uxth r3, r3 80103a2: 461a mov r2, r3 80103a4: 6cbb ldr r3, [r7, #72] @ 0x48 80103a6: 4413 add r3, r2 80103a8: 64bb str r3, [r7, #72] @ 0x48 80103aa: 683b ldr r3, [r7, #0] 80103ac: 781b ldrb r3, [r3, #0] 80103ae: 00da lsls r2, r3, #3 80103b0: 6cbb ldr r3, [r7, #72] @ 0x48 80103b2: 4413 add r3, r2 80103b4: f203 4302 addw r3, r3, #1026 @ 0x402 80103b8: 647b str r3, [r7, #68] @ 0x44 80103ba: 6c7b ldr r3, [r7, #68] @ 0x44 80103bc: 881b ldrh r3, [r3, #0] 80103be: b29b uxth r3, r3 80103c0: f3c3 0309 ubfx r3, r3, #0, #10 80103c4: b29a uxth r2, r3 80103c6: 6c7b ldr r3, [r7, #68] @ 0x44 80103c8: 801a strh r2, [r3, #0] 80103ca: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80103ce: 2b00 cmp r3, #0 80103d0: d10a bne.n 80103e8 80103d2: 6c7b ldr r3, [r7, #68] @ 0x44 80103d4: 881b ldrh r3, [r3, #0] 80103d6: b29b uxth r3, r3 80103d8: ea6f 4343 mvn.w r3, r3, lsl #17 80103dc: ea6f 4353 mvn.w r3, r3, lsr #17 80103e0: b29a uxth r2, r3 80103e2: 6c7b ldr r3, [r7, #68] @ 0x44 80103e4: 801a strh r2, [r3, #0] 80103e6: e05d b.n 80104a4 80103e8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80103ec: 2b3e cmp r3, #62 @ 0x3e 80103ee: d81c bhi.n 801042a 80103f0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80103f4: 085b lsrs r3, r3, #1 80103f6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 80103fa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80103fe: f003 0301 and.w r3, r3, #1 8010402: 2b00 cmp r3, #0 8010404: d004 beq.n 8010410 8010406: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801040a: 3301 adds r3, #1 801040c: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8010410: 6c7b ldr r3, [r7, #68] @ 0x44 8010412: 881b ldrh r3, [r3, #0] 8010414: b29a uxth r2, r3 8010416: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801041a: b29b uxth r3, r3 801041c: 029b lsls r3, r3, #10 801041e: b29b uxth r3, r3 8010420: 4313 orrs r3, r2 8010422: b29a uxth r2, r3 8010424: 6c7b ldr r3, [r7, #68] @ 0x44 8010426: 801a strh r2, [r3, #0] 8010428: e03c b.n 80104a4 801042a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801042e: 095b lsrs r3, r3, #5 8010430: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8010434: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010438: f003 031f and.w r3, r3, #31 801043c: 2b00 cmp r3, #0 801043e: d104 bne.n 801044a 8010440: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8010444: 3b01 subs r3, #1 8010446: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 801044a: 6c7b ldr r3, [r7, #68] @ 0x44 801044c: 881b ldrh r3, [r3, #0] 801044e: b29a uxth r2, r3 8010450: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8010454: b29b uxth r3, r3 8010456: 029b lsls r3, r3, #10 8010458: b29b uxth r3, r3 801045a: 4313 orrs r3, r2 801045c: b29b uxth r3, r3 801045e: ea6f 4343 mvn.w r3, r3, lsl #17 8010462: ea6f 4353 mvn.w r3, r3, lsr #17 8010466: b29a uxth r2, r3 8010468: 6c7b ldr r3, [r7, #68] @ 0x44 801046a: 801a strh r2, [r3, #0] 801046c: e01a b.n 80104a4 801046e: 683b ldr r3, [r7, #0] 8010470: 785b ldrb r3, [r3, #1] 8010472: 2b01 cmp r3, #1 8010474: d116 bne.n 80104a4 8010476: 687b ldr r3, [r7, #4] 8010478: 653b str r3, [r7, #80] @ 0x50 801047a: 687b ldr r3, [r7, #4] 801047c: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8010480: b29b uxth r3, r3 8010482: 461a mov r2, r3 8010484: 6d3b ldr r3, [r7, #80] @ 0x50 8010486: 4413 add r3, r2 8010488: 653b str r3, [r7, #80] @ 0x50 801048a: 683b ldr r3, [r7, #0] 801048c: 781b ldrb r3, [r3, #0] 801048e: 00da lsls r2, r3, #3 8010490: 6d3b ldr r3, [r7, #80] @ 0x50 8010492: 4413 add r3, r2 8010494: f203 4302 addw r3, r3, #1026 @ 0x402 8010498: 64fb str r3, [r7, #76] @ 0x4c 801049a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801049e: b29a uxth r2, r3 80104a0: 6cfb ldr r3, [r7, #76] @ 0x4c 80104a2: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 80104a4: 683b ldr r3, [r7, #0] 80104a6: 891b ldrh r3, [r3, #8] 80104a8: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 80104ac: 683b ldr r3, [r7, #0] 80104ae: 6959 ldr r1, [r3, #20] 80104b0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80104b4: b29b uxth r3, r3 80104b6: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 80104ba: 6878 ldr r0, [r7, #4] 80104bc: f000 fc7f bl 8010dbe ep->xfer_buff += len; 80104c0: 683b ldr r3, [r7, #0] 80104c2: 695a ldr r2, [r3, #20] 80104c4: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80104c8: 441a add r2, r3 80104ca: 683b ldr r3, [r7, #0] 80104cc: 615a str r2, [r3, #20] if (ep->xfer_len_db > ep->maxpacket) 80104ce: 683b ldr r3, [r7, #0] 80104d0: 6a1a ldr r2, [r3, #32] 80104d2: 683b ldr r3, [r7, #0] 80104d4: 691b ldr r3, [r3, #16] 80104d6: 429a cmp r2, r3 80104d8: d907 bls.n 80104ea { ep->xfer_len_db -= len; 80104da: 683b ldr r3, [r7, #0] 80104dc: 6a1a ldr r2, [r3, #32] 80104de: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80104e2: 1ad2 subs r2, r2, r3 80104e4: 683b ldr r3, [r7, #0] 80104e6: 621a str r2, [r3, #32] 80104e8: e006 b.n 80104f8 } else { len = ep->xfer_len_db; 80104ea: 683b ldr r3, [r7, #0] 80104ec: 6a1b ldr r3, [r3, #32] 80104ee: f8c7 30ac str.w r3, [r7, #172] @ 0xac ep->xfer_len_db = 0U; 80104f2: 683b ldr r3, [r7, #0] 80104f4: 2200 movs r2, #0 80104f6: 621a str r2, [r3, #32] } /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 80104f8: 687b ldr r3, [r7, #4] 80104fa: 643b str r3, [r7, #64] @ 0x40 80104fc: 683b ldr r3, [r7, #0] 80104fe: 785b ldrb r3, [r3, #1] 8010500: 2b00 cmp r3, #0 8010502: d16b bne.n 80105dc 8010504: 687b ldr r3, [r7, #4] 8010506: 63bb str r3, [r7, #56] @ 0x38 8010508: 687b ldr r3, [r7, #4] 801050a: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 801050e: b29b uxth r3, r3 8010510: 461a mov r2, r3 8010512: 6bbb ldr r3, [r7, #56] @ 0x38 8010514: 4413 add r3, r2 8010516: 63bb str r3, [r7, #56] @ 0x38 8010518: 683b ldr r3, [r7, #0] 801051a: 781b ldrb r3, [r3, #0] 801051c: 00da lsls r2, r3, #3 801051e: 6bbb ldr r3, [r7, #56] @ 0x38 8010520: 4413 add r3, r2 8010522: f203 4306 addw r3, r3, #1030 @ 0x406 8010526: 637b str r3, [r7, #52] @ 0x34 8010528: 6b7b ldr r3, [r7, #52] @ 0x34 801052a: 881b ldrh r3, [r3, #0] 801052c: b29b uxth r3, r3 801052e: f3c3 0309 ubfx r3, r3, #0, #10 8010532: b29a uxth r2, r3 8010534: 6b7b ldr r3, [r7, #52] @ 0x34 8010536: 801a strh r2, [r3, #0] 8010538: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801053c: 2b00 cmp r3, #0 801053e: d10a bne.n 8010556 8010540: 6b7b ldr r3, [r7, #52] @ 0x34 8010542: 881b ldrh r3, [r3, #0] 8010544: b29b uxth r3, r3 8010546: ea6f 4343 mvn.w r3, r3, lsl #17 801054a: ea6f 4353 mvn.w r3, r3, lsr #17 801054e: b29a uxth r2, r3 8010550: 6b7b ldr r3, [r7, #52] @ 0x34 8010552: 801a strh r2, [r3, #0] 8010554: e05b b.n 801060e 8010556: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801055a: 2b3e cmp r3, #62 @ 0x3e 801055c: d81c bhi.n 8010598 801055e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010562: 085b lsrs r3, r3, #1 8010564: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8010568: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801056c: f003 0301 and.w r3, r3, #1 8010570: 2b00 cmp r3, #0 8010572: d004 beq.n 801057e 8010574: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8010578: 3301 adds r3, #1 801057a: f8c7 309c str.w r3, [r7, #156] @ 0x9c 801057e: 6b7b ldr r3, [r7, #52] @ 0x34 8010580: 881b ldrh r3, [r3, #0] 8010582: b29a uxth r2, r3 8010584: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8010588: b29b uxth r3, r3 801058a: 029b lsls r3, r3, #10 801058c: b29b uxth r3, r3 801058e: 4313 orrs r3, r2 8010590: b29a uxth r2, r3 8010592: 6b7b ldr r3, [r7, #52] @ 0x34 8010594: 801a strh r2, [r3, #0] 8010596: e03a b.n 801060e 8010598: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801059c: 095b lsrs r3, r3, #5 801059e: f8c7 309c str.w r3, [r7, #156] @ 0x9c 80105a2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80105a6: f003 031f and.w r3, r3, #31 80105aa: 2b00 cmp r3, #0 80105ac: d104 bne.n 80105b8 80105ae: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80105b2: 3b01 subs r3, #1 80105b4: f8c7 309c str.w r3, [r7, #156] @ 0x9c 80105b8: 6b7b ldr r3, [r7, #52] @ 0x34 80105ba: 881b ldrh r3, [r3, #0] 80105bc: b29a uxth r2, r3 80105be: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80105c2: b29b uxth r3, r3 80105c4: 029b lsls r3, r3, #10 80105c6: b29b uxth r3, r3 80105c8: 4313 orrs r3, r2 80105ca: b29b uxth r3, r3 80105cc: ea6f 4343 mvn.w r3, r3, lsl #17 80105d0: ea6f 4353 mvn.w r3, r3, lsr #17 80105d4: b29a uxth r2, r3 80105d6: 6b7b ldr r3, [r7, #52] @ 0x34 80105d8: 801a strh r2, [r3, #0] 80105da: e018 b.n 801060e 80105dc: 683b ldr r3, [r7, #0] 80105de: 785b ldrb r3, [r3, #1] 80105e0: 2b01 cmp r3, #1 80105e2: d114 bne.n 801060e 80105e4: 687b ldr r3, [r7, #4] 80105e6: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80105ea: b29b uxth r3, r3 80105ec: 461a mov r2, r3 80105ee: 6c3b ldr r3, [r7, #64] @ 0x40 80105f0: 4413 add r3, r2 80105f2: 643b str r3, [r7, #64] @ 0x40 80105f4: 683b ldr r3, [r7, #0] 80105f6: 781b ldrb r3, [r3, #0] 80105f8: 00da lsls r2, r3, #3 80105fa: 6c3b ldr r3, [r7, #64] @ 0x40 80105fc: 4413 add r3, r2 80105fe: f203 4306 addw r3, r3, #1030 @ 0x406 8010602: 63fb str r3, [r7, #60] @ 0x3c 8010604: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010608: b29a uxth r2, r3 801060a: 6bfb ldr r3, [r7, #60] @ 0x3c 801060c: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 801060e: 683b ldr r3, [r7, #0] 8010610: 895b ldrh r3, [r3, #10] 8010612: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 8010616: 683b ldr r3, [r7, #0] 8010618: 6959 ldr r1, [r3, #20] 801061a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801061e: b29b uxth r3, r3 8010620: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 8010624: 6878 ldr r0, [r7, #4] 8010626: f000 fbca bl 8010dbe 801062a: e193 b.n 8010954 } } /* auto Switch to single buffer mode when transfer xfer_len_db; 801062c: 683b ldr r3, [r7, #0] 801062e: 6a1b ldr r3, [r3, #32] 8010630: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* disable double buffer mode for Bulk endpoint */ PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); 8010634: 687a ldr r2, [r7, #4] 8010636: 683b ldr r3, [r7, #0] 8010638: 781b ldrb r3, [r3, #0] 801063a: 009b lsls r3, r3, #2 801063c: 4413 add r3, r2 801063e: 881b ldrh r3, [r3, #0] 8010640: b29b uxth r3, r3 8010642: f423 43e2 bic.w r3, r3, #28928 @ 0x7100 8010646: f023 0370 bic.w r3, r3, #112 @ 0x70 801064a: f8a7 3062 strh.w r3, [r7, #98] @ 0x62 801064e: 687a ldr r2, [r7, #4] 8010650: 683b ldr r3, [r7, #0] 8010652: 781b ldrb r3, [r3, #0] 8010654: 009b lsls r3, r3, #2 8010656: 441a add r2, r3 8010658: f8b7 3062 ldrh.w r3, [r7, #98] @ 0x62 801065c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010660: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010664: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010668: f043 0380 orr.w r3, r3, #128 @ 0x80 801066c: b29b uxth r3, r3 801066e: 8013 strh r3, [r2, #0] /* Set Tx count with nbre of byte to be transmitted */ PCD_SET_EP_TX_CNT(USBx, ep->num, len); 8010670: 687b ldr r3, [r7, #4] 8010672: 65fb str r3, [r7, #92] @ 0x5c 8010674: 687b ldr r3, [r7, #4] 8010676: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 801067a: b29b uxth r3, r3 801067c: 461a mov r2, r3 801067e: 6dfb ldr r3, [r7, #92] @ 0x5c 8010680: 4413 add r3, r2 8010682: 65fb str r3, [r7, #92] @ 0x5c 8010684: 683b ldr r3, [r7, #0] 8010686: 781b ldrb r3, [r3, #0] 8010688: 00da lsls r2, r3, #3 801068a: 6dfb ldr r3, [r7, #92] @ 0x5c 801068c: 4413 add r3, r2 801068e: f203 4302 addw r3, r3, #1026 @ 0x402 8010692: 65bb str r3, [r7, #88] @ 0x58 8010694: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010698: b29a uxth r2, r3 801069a: 6dbb ldr r3, [r7, #88] @ 0x58 801069c: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 801069e: 683b ldr r3, [r7, #0] 80106a0: 891b ldrh r3, [r3, #8] 80106a2: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 80106a6: 683b ldr r3, [r7, #0] 80106a8: 6959 ldr r1, [r3, #20] 80106aa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80106ae: b29b uxth r3, r3 80106b0: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 80106b4: 6878 ldr r0, [r7, #4] 80106b6: f000 fb82 bl 8010dbe 80106ba: e14b b.n 8010954 } } else /* Manage isochronous double buffer IN mode */ { /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; 80106bc: 683b ldr r3, [r7, #0] 80106be: 6a1a ldr r2, [r3, #32] 80106c0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80106c4: 1ad2 subs r2, r2, r3 80106c6: 683b ldr r3, [r7, #0] 80106c8: 621a str r2, [r3, #32] /* Fill the data buffer */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) 80106ca: 687a ldr r2, [r7, #4] 80106cc: 683b ldr r3, [r7, #0] 80106ce: 781b ldrb r3, [r3, #0] 80106d0: 009b lsls r3, r3, #2 80106d2: 4413 add r3, r2 80106d4: 881b ldrh r3, [r3, #0] 80106d6: b29b uxth r3, r3 80106d8: f003 0340 and.w r3, r3, #64 @ 0x40 80106dc: 2b00 cmp r3, #0 80106de: f000 809a beq.w 8010816 { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 80106e2: 687b ldr r3, [r7, #4] 80106e4: 673b str r3, [r7, #112] @ 0x70 80106e6: 683b ldr r3, [r7, #0] 80106e8: 785b ldrb r3, [r3, #1] 80106ea: 2b00 cmp r3, #0 80106ec: d16b bne.n 80107c6 80106ee: 687b ldr r3, [r7, #4] 80106f0: 66bb str r3, [r7, #104] @ 0x68 80106f2: 687b ldr r3, [r7, #4] 80106f4: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80106f8: b29b uxth r3, r3 80106fa: 461a mov r2, r3 80106fc: 6ebb ldr r3, [r7, #104] @ 0x68 80106fe: 4413 add r3, r2 8010700: 66bb str r3, [r7, #104] @ 0x68 8010702: 683b ldr r3, [r7, #0] 8010704: 781b ldrb r3, [r3, #0] 8010706: 00da lsls r2, r3, #3 8010708: 6ebb ldr r3, [r7, #104] @ 0x68 801070a: 4413 add r3, r2 801070c: f203 4306 addw r3, r3, #1030 @ 0x406 8010710: 667b str r3, [r7, #100] @ 0x64 8010712: 6e7b ldr r3, [r7, #100] @ 0x64 8010714: 881b ldrh r3, [r3, #0] 8010716: b29b uxth r3, r3 8010718: f3c3 0309 ubfx r3, r3, #0, #10 801071c: b29a uxth r2, r3 801071e: 6e7b ldr r3, [r7, #100] @ 0x64 8010720: 801a strh r2, [r3, #0] 8010722: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010726: 2b00 cmp r3, #0 8010728: d10a bne.n 8010740 801072a: 6e7b ldr r3, [r7, #100] @ 0x64 801072c: 881b ldrh r3, [r3, #0] 801072e: b29b uxth r3, r3 8010730: ea6f 4343 mvn.w r3, r3, lsl #17 8010734: ea6f 4353 mvn.w r3, r3, lsr #17 8010738: b29a uxth r2, r3 801073a: 6e7b ldr r3, [r7, #100] @ 0x64 801073c: 801a strh r2, [r3, #0] 801073e: e05b b.n 80107f8 8010740: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010744: 2b3e cmp r3, #62 @ 0x3e 8010746: d81c bhi.n 8010782 8010748: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801074c: 085b lsrs r3, r3, #1 801074e: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8010752: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010756: f003 0301 and.w r3, r3, #1 801075a: 2b00 cmp r3, #0 801075c: d004 beq.n 8010768 801075e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8010762: 3301 adds r3, #1 8010764: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8010768: 6e7b ldr r3, [r7, #100] @ 0x64 801076a: 881b ldrh r3, [r3, #0] 801076c: b29a uxth r2, r3 801076e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8010772: b29b uxth r3, r3 8010774: 029b lsls r3, r3, #10 8010776: b29b uxth r3, r3 8010778: 4313 orrs r3, r2 801077a: b29a uxth r2, r3 801077c: 6e7b ldr r3, [r7, #100] @ 0x64 801077e: 801a strh r2, [r3, #0] 8010780: e03a b.n 80107f8 8010782: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010786: 095b lsrs r3, r3, #5 8010788: f8c7 3098 str.w r3, [r7, #152] @ 0x98 801078c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010790: f003 031f and.w r3, r3, #31 8010794: 2b00 cmp r3, #0 8010796: d104 bne.n 80107a2 8010798: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 801079c: 3b01 subs r3, #1 801079e: f8c7 3098 str.w r3, [r7, #152] @ 0x98 80107a2: 6e7b ldr r3, [r7, #100] @ 0x64 80107a4: 881b ldrh r3, [r3, #0] 80107a6: b29a uxth r2, r3 80107a8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80107ac: b29b uxth r3, r3 80107ae: 029b lsls r3, r3, #10 80107b0: b29b uxth r3, r3 80107b2: 4313 orrs r3, r2 80107b4: b29b uxth r3, r3 80107b6: ea6f 4343 mvn.w r3, r3, lsl #17 80107ba: ea6f 4353 mvn.w r3, r3, lsr #17 80107be: b29a uxth r2, r3 80107c0: 6e7b ldr r3, [r7, #100] @ 0x64 80107c2: 801a strh r2, [r3, #0] 80107c4: e018 b.n 80107f8 80107c6: 683b ldr r3, [r7, #0] 80107c8: 785b ldrb r3, [r3, #1] 80107ca: 2b01 cmp r3, #1 80107cc: d114 bne.n 80107f8 80107ce: 687b ldr r3, [r7, #4] 80107d0: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 80107d4: b29b uxth r3, r3 80107d6: 461a mov r2, r3 80107d8: 6f3b ldr r3, [r7, #112] @ 0x70 80107da: 4413 add r3, r2 80107dc: 673b str r3, [r7, #112] @ 0x70 80107de: 683b ldr r3, [r7, #0] 80107e0: 781b ldrb r3, [r3, #0] 80107e2: 00da lsls r2, r3, #3 80107e4: 6f3b ldr r3, [r7, #112] @ 0x70 80107e6: 4413 add r3, r2 80107e8: f203 4306 addw r3, r3, #1030 @ 0x406 80107ec: 66fb str r3, [r7, #108] @ 0x6c 80107ee: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80107f2: b29a uxth r2, r3 80107f4: 6efb ldr r3, [r7, #108] @ 0x6c 80107f6: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; 80107f8: 683b ldr r3, [r7, #0] 80107fa: 895b ldrh r3, [r3, #10] 80107fc: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 8010800: 683b ldr r3, [r7, #0] 8010802: 6959 ldr r1, [r3, #20] 8010804: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010808: b29b uxth r3, r3 801080a: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 801080e: 6878 ldr r0, [r7, #4] 8010810: f000 fad5 bl 8010dbe 8010814: e09e b.n 8010954 } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 8010816: 683b ldr r3, [r7, #0] 8010818: 785b ldrb r3, [r3, #1] 801081a: 2b00 cmp r3, #0 801081c: d16b bne.n 80108f6 801081e: 687b ldr r3, [r7, #4] 8010820: 67fb str r3, [r7, #124] @ 0x7c 8010822: 687b ldr r3, [r7, #4] 8010824: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 8010828: b29b uxth r3, r3 801082a: 461a mov r2, r3 801082c: 6ffb ldr r3, [r7, #124] @ 0x7c 801082e: 4413 add r3, r2 8010830: 67fb str r3, [r7, #124] @ 0x7c 8010832: 683b ldr r3, [r7, #0] 8010834: 781b ldrb r3, [r3, #0] 8010836: 00da lsls r2, r3, #3 8010838: 6ffb ldr r3, [r7, #124] @ 0x7c 801083a: 4413 add r3, r2 801083c: f203 4302 addw r3, r3, #1026 @ 0x402 8010840: 67bb str r3, [r7, #120] @ 0x78 8010842: 6fbb ldr r3, [r7, #120] @ 0x78 8010844: 881b ldrh r3, [r3, #0] 8010846: b29b uxth r3, r3 8010848: f3c3 0309 ubfx r3, r3, #0, #10 801084c: b29a uxth r2, r3 801084e: 6fbb ldr r3, [r7, #120] @ 0x78 8010850: 801a strh r2, [r3, #0] 8010852: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010856: 2b00 cmp r3, #0 8010858: d10a bne.n 8010870 801085a: 6fbb ldr r3, [r7, #120] @ 0x78 801085c: 881b ldrh r3, [r3, #0] 801085e: b29b uxth r3, r3 8010860: ea6f 4343 mvn.w r3, r3, lsl #17 8010864: ea6f 4353 mvn.w r3, r3, lsr #17 8010868: b29a uxth r2, r3 801086a: 6fbb ldr r3, [r7, #120] @ 0x78 801086c: 801a strh r2, [r3, #0] 801086e: e063 b.n 8010938 8010870: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010874: 2b3e cmp r3, #62 @ 0x3e 8010876: d81c bhi.n 80108b2 8010878: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801087c: 085b lsrs r3, r3, #1 801087e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8010882: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010886: f003 0301 and.w r3, r3, #1 801088a: 2b00 cmp r3, #0 801088c: d004 beq.n 8010898 801088e: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 8010892: 3301 adds r3, #1 8010894: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8010898: 6fbb ldr r3, [r7, #120] @ 0x78 801089a: 881b ldrh r3, [r3, #0] 801089c: b29a uxth r2, r3 801089e: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 80108a2: b29b uxth r3, r3 80108a4: 029b lsls r3, r3, #10 80108a6: b29b uxth r3, r3 80108a8: 4313 orrs r3, r2 80108aa: b29a uxth r2, r3 80108ac: 6fbb ldr r3, [r7, #120] @ 0x78 80108ae: 801a strh r2, [r3, #0] 80108b0: e042 b.n 8010938 80108b2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80108b6: 095b lsrs r3, r3, #5 80108b8: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80108bc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80108c0: f003 031f and.w r3, r3, #31 80108c4: 2b00 cmp r3, #0 80108c6: d104 bne.n 80108d2 80108c8: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 80108cc: 3b01 subs r3, #1 80108ce: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80108d2: 6fbb ldr r3, [r7, #120] @ 0x78 80108d4: 881b ldrh r3, [r3, #0] 80108d6: b29a uxth r2, r3 80108d8: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 80108dc: b29b uxth r3, r3 80108de: 029b lsls r3, r3, #10 80108e0: b29b uxth r3, r3 80108e2: 4313 orrs r3, r2 80108e4: b29b uxth r3, r3 80108e6: ea6f 4343 mvn.w r3, r3, lsl #17 80108ea: ea6f 4353 mvn.w r3, r3, lsr #17 80108ee: b29a uxth r2, r3 80108f0: 6fbb ldr r3, [r7, #120] @ 0x78 80108f2: 801a strh r2, [r3, #0] 80108f4: e020 b.n 8010938 80108f6: 683b ldr r3, [r7, #0] 80108f8: 785b ldrb r3, [r3, #1] 80108fa: 2b01 cmp r3, #1 80108fc: d11c bne.n 8010938 80108fe: 687b ldr r3, [r7, #4] 8010900: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8010904: 687b ldr r3, [r7, #4] 8010906: f8b3 3050 ldrh.w r3, [r3, #80] @ 0x50 801090a: b29b uxth r3, r3 801090c: 461a mov r2, r3 801090e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8010912: 4413 add r3, r2 8010914: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8010918: 683b ldr r3, [r7, #0] 801091a: 781b ldrb r3, [r3, #0] 801091c: 00da lsls r2, r3, #3 801091e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8010922: 4413 add r3, r2 8010924: f203 4302 addw r3, r3, #1026 @ 0x402 8010928: f8c7 3080 str.w r3, [r7, #128] @ 0x80 801092c: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010930: b29a uxth r2, r3 8010932: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8010936: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; 8010938: 683b ldr r3, [r7, #0] 801093a: 891b ldrh r3, [r3, #8] 801093c: f8a7 3076 strh.w r3, [r7, #118] @ 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); 8010940: 683b ldr r3, [r7, #0] 8010942: 6959 ldr r1, [r3, #20] 8010944: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8010948: b29b uxth r3, r3 801094a: f8b7 2076 ldrh.w r2, [r7, #118] @ 0x76 801094e: 6878 ldr r0, [r7, #4] 8010950: f000 fa35 bl 8010dbe } } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); 8010954: 687a ldr r2, [r7, #4] 8010956: 683b ldr r3, [r7, #0] 8010958: 781b ldrb r3, [r3, #0] 801095a: 009b lsls r3, r3, #2 801095c: 4413 add r3, r2 801095e: 881b ldrh r3, [r3, #0] 8010960: b29b uxth r3, r3 8010962: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010966: f023 0340 bic.w r3, r3, #64 @ 0x40 801096a: 817b strh r3, [r7, #10] 801096c: 897b ldrh r3, [r7, #10] 801096e: f083 0310 eor.w r3, r3, #16 8010972: 817b strh r3, [r7, #10] 8010974: 897b ldrh r3, [r7, #10] 8010976: f083 0320 eor.w r3, r3, #32 801097a: 817b strh r3, [r7, #10] 801097c: 687a ldr r2, [r7, #4] 801097e: 683b ldr r3, [r7, #0] 8010980: 781b ldrb r3, [r3, #0] 8010982: 009b lsls r3, r3, #2 8010984: 441a add r2, r3 8010986: 897b ldrh r3, [r7, #10] 8010988: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 801098c: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010990: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010994: f043 0380 orr.w r3, r3, #128 @ 0x80 8010998: b29b uxth r3, r3 801099a: 8013 strh r3, [r2, #0] 801099c: e0d5 b.n 8010b4a } else /* OUT endpoint */ { if (ep->doublebuffer == 0U) 801099e: 683b ldr r3, [r7, #0] 80109a0: 7b1b ldrb r3, [r3, #12] 80109a2: 2b00 cmp r3, #0 80109a4: d156 bne.n 8010a54 { if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) 80109a6: 683b ldr r3, [r7, #0] 80109a8: 699b ldr r3, [r3, #24] 80109aa: 2b00 cmp r3, #0 80109ac: d122 bne.n 80109f4 80109ae: 683b ldr r3, [r7, #0] 80109b0: 78db ldrb r3, [r3, #3] 80109b2: 2b00 cmp r3, #0 80109b4: d11e bne.n 80109f4 { /* This is a status out stage set the OUT_STATUS */ PCD_SET_OUT_STATUS(USBx, ep->num); 80109b6: 687a ldr r2, [r7, #4] 80109b8: 683b ldr r3, [r7, #0] 80109ba: 781b ldrb r3, [r3, #0] 80109bc: 009b lsls r3, r3, #2 80109be: 4413 add r3, r2 80109c0: 881b ldrh r3, [r3, #0] 80109c2: b29b uxth r3, r3 80109c4: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80109c8: f023 0370 bic.w r3, r3, #112 @ 0x70 80109cc: f8a7 308e strh.w r3, [r7, #142] @ 0x8e 80109d0: 687a ldr r2, [r7, #4] 80109d2: 683b ldr r3, [r7, #0] 80109d4: 781b ldrb r3, [r3, #0] 80109d6: 009b lsls r3, r3, #2 80109d8: 441a add r2, r3 80109da: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 80109de: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 80109e2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 80109e6: f443 4301 orr.w r3, r3, #33024 @ 0x8100 80109ea: f043 0380 orr.w r3, r3, #128 @ 0x80 80109ee: b29b uxth r3, r3 80109f0: 8013 strh r3, [r2, #0] 80109f2: e01d b.n 8010a30 } else { PCD_CLEAR_OUT_STATUS(USBx, ep->num); 80109f4: 687a ldr r2, [r7, #4] 80109f6: 683b ldr r3, [r7, #0] 80109f8: 781b ldrb r3, [r3, #0] 80109fa: 009b lsls r3, r3, #2 80109fc: 4413 add r3, r2 80109fe: 881b ldrh r3, [r3, #0] 8010a00: b29b uxth r3, r3 8010a02: f423 43e2 bic.w r3, r3, #28928 @ 0x7100 8010a06: f023 0370 bic.w r3, r3, #112 @ 0x70 8010a0a: f8a7 308c strh.w r3, [r7, #140] @ 0x8c 8010a0e: 687a ldr r2, [r7, #4] 8010a10: 683b ldr r3, [r7, #0] 8010a12: 781b ldrb r3, [r3, #0] 8010a14: 009b lsls r3, r3, #2 8010a16: 441a add r2, r3 8010a18: f8b7 308c ldrh.w r3, [r7, #140] @ 0x8c 8010a1c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010a20: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010a24: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010a28: f043 0380 orr.w r3, r3, #128 @ 0x80 8010a2c: b29b uxth r3, r3 8010a2e: 8013 strh r3, [r2, #0] } /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) 8010a30: 683b ldr r3, [r7, #0] 8010a32: 699a ldr r2, [r3, #24] 8010a34: 683b ldr r3, [r7, #0] 8010a36: 691b ldr r3, [r3, #16] 8010a38: 429a cmp r2, r3 8010a3a: d907 bls.n 8010a4c { ep->xfer_len -= ep->maxpacket; 8010a3c: 683b ldr r3, [r7, #0] 8010a3e: 699a ldr r2, [r3, #24] 8010a40: 683b ldr r3, [r7, #0] 8010a42: 691b ldr r3, [r3, #16] 8010a44: 1ad2 subs r2, r2, r3 8010a46: 683b ldr r3, [r7, #0] 8010a48: 619a str r2, [r3, #24] 8010a4a: e054 b.n 8010af6 } else { ep->xfer_len = 0U; 8010a4c: 683b ldr r3, [r7, #0] 8010a4e: 2200 movs r2, #0 8010a50: 619a str r2, [r3, #24] 8010a52: e050 b.n 8010af6 #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) 8010a54: 683b ldr r3, [r7, #0] 8010a56: 78db ldrb r3, [r3, #3] 8010a58: 2b02 cmp r3, #2 8010a5a: d142 bne.n 8010ae2 { /* Coming from ISR */ if (ep->xfer_count != 0U) 8010a5c: 683b ldr r3, [r7, #0] 8010a5e: 69db ldr r3, [r3, #28] 8010a60: 2b00 cmp r3, #0 8010a62: d048 beq.n 8010af6 { /* Update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); 8010a64: 687a ldr r2, [r7, #4] 8010a66: 683b ldr r3, [r7, #0] 8010a68: 781b ldrb r3, [r3, #0] 8010a6a: 009b lsls r3, r3, #2 8010a6c: 4413 add r3, r2 8010a6e: 881b ldrh r3, [r3, #0] 8010a70: f8a7 3092 strh.w r3, [r7, #146] @ 0x92 /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || 8010a74: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 8010a78: f403 4380 and.w r3, r3, #16384 @ 0x4000 8010a7c: 2b00 cmp r3, #0 8010a7e: d005 beq.n 8010a8c 8010a80: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 8010a84: f003 0340 and.w r3, r3, #64 @ 0x40 8010a88: 2b00 cmp r3, #0 8010a8a: d10b bne.n 8010aa4 (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) 8010a8c: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 8010a90: f403 4380 and.w r3, r3, #16384 @ 0x4000 if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || 8010a94: 2b00 cmp r3, #0 8010a96: d12e bne.n 8010af6 (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) 8010a98: f8b7 3092 ldrh.w r3, [r7, #146] @ 0x92 8010a9c: f003 0340 and.w r3, r3, #64 @ 0x40 8010aa0: 2b00 cmp r3, #0 8010aa2: d128 bne.n 8010af6 { PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); 8010aa4: 687a ldr r2, [r7, #4] 8010aa6: 683b ldr r3, [r7, #0] 8010aa8: 781b ldrb r3, [r3, #0] 8010aaa: 009b lsls r3, r3, #2 8010aac: 4413 add r3, r2 8010aae: 881b ldrh r3, [r3, #0] 8010ab0: b29b uxth r3, r3 8010ab2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010ab6: f023 0370 bic.w r3, r3, #112 @ 0x70 8010aba: f8a7 3090 strh.w r3, [r7, #144] @ 0x90 8010abe: 687a ldr r2, [r7, #4] 8010ac0: 683b ldr r3, [r7, #0] 8010ac2: 781b ldrb r3, [r3, #0] 8010ac4: 009b lsls r3, r3, #2 8010ac6: 441a add r2, r3 8010ac8: f8b7 3090 ldrh.w r3, [r7, #144] @ 0x90 8010acc: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010ad0: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010ad4: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010ad8: f043 03c0 orr.w r3, r3, #192 @ 0xc0 8010adc: b29b uxth r3, r3 8010ade: 8013 strh r3, [r2, #0] 8010ae0: e009 b.n 8010af6 } } } /* iso out double */ else if (ep->type == EP_TYPE_ISOC) 8010ae2: 683b ldr r3, [r7, #0] 8010ae4: 78db ldrb r3, [r3, #3] 8010ae6: 2b01 cmp r3, #1 8010ae8: d103 bne.n 8010af2 { /* Only single packet transfer supported in FS */ ep->xfer_len = 0U; 8010aea: 683b ldr r3, [r7, #0] 8010aec: 2200 movs r2, #0 8010aee: 619a str r2, [r3, #24] 8010af0: e001 b.n 8010af6 } else { return HAL_ERROR; 8010af2: 2301 movs r3, #1 8010af4: e02a b.n 8010b4c } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 8010af6: 687a ldr r2, [r7, #4] 8010af8: 683b ldr r3, [r7, #0] 8010afa: 781b ldrb r3, [r3, #0] 8010afc: 009b lsls r3, r3, #2 8010afe: 4413 add r3, r2 8010b00: 881b ldrh r3, [r3, #0] 8010b02: b29b uxth r3, r3 8010b04: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010b08: f023 0370 bic.w r3, r3, #112 @ 0x70 8010b0c: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 8010b10: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8010b14: f483 5380 eor.w r3, r3, #4096 @ 0x1000 8010b18: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 8010b1c: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8010b20: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8010b24: f8a7 308a strh.w r3, [r7, #138] @ 0x8a 8010b28: 687a ldr r2, [r7, #4] 8010b2a: 683b ldr r3, [r7, #0] 8010b2c: 781b ldrb r3, [r3, #0] 8010b2e: 009b lsls r3, r3, #2 8010b30: 441a add r2, r3 8010b32: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8010b36: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010b3a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010b3e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010b42: f043 0380 orr.w r3, r3, #128 @ 0x80 8010b46: b29b uxth r3, r3 8010b48: 8013 strh r3, [r2, #0] } return HAL_OK; 8010b4a: 2300 movs r3, #0 } 8010b4c: 4618 mov r0, r3 8010b4e: 37b0 adds r7, #176 @ 0xb0 8010b50: 46bd mov sp, r7 8010b52: bd80 pop {r7, pc} 08010b54 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 8010b54: b480 push {r7} 8010b56: b085 sub sp, #20 8010b58: af00 add r7, sp, #0 8010b5a: 6078 str r0, [r7, #4] 8010b5c: 6039 str r1, [r7, #0] if (ep->is_in != 0U) 8010b5e: 683b ldr r3, [r7, #0] 8010b60: 785b ldrb r3, [r3, #1] 8010b62: 2b00 cmp r3, #0 8010b64: d020 beq.n 8010ba8 { PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); 8010b66: 687a ldr r2, [r7, #4] 8010b68: 683b ldr r3, [r7, #0] 8010b6a: 781b ldrb r3, [r3, #0] 8010b6c: 009b lsls r3, r3, #2 8010b6e: 4413 add r3, r2 8010b70: 881b ldrh r3, [r3, #0] 8010b72: b29b uxth r3, r3 8010b74: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010b78: f023 0340 bic.w r3, r3, #64 @ 0x40 8010b7c: 81bb strh r3, [r7, #12] 8010b7e: 89bb ldrh r3, [r7, #12] 8010b80: f083 0310 eor.w r3, r3, #16 8010b84: 81bb strh r3, [r7, #12] 8010b86: 687a ldr r2, [r7, #4] 8010b88: 683b ldr r3, [r7, #0] 8010b8a: 781b ldrb r3, [r3, #0] 8010b8c: 009b lsls r3, r3, #2 8010b8e: 441a add r2, r3 8010b90: 89bb ldrh r3, [r7, #12] 8010b92: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010b96: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010b9a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010b9e: f043 0380 orr.w r3, r3, #128 @ 0x80 8010ba2: b29b uxth r3, r3 8010ba4: 8013 strh r3, [r2, #0] 8010ba6: e01f b.n 8010be8 } else { PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); 8010ba8: 687a ldr r2, [r7, #4] 8010baa: 683b ldr r3, [r7, #0] 8010bac: 781b ldrb r3, [r3, #0] 8010bae: 009b lsls r3, r3, #2 8010bb0: 4413 add r3, r2 8010bb2: 881b ldrh r3, [r3, #0] 8010bb4: b29b uxth r3, r3 8010bb6: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010bba: f023 0370 bic.w r3, r3, #112 @ 0x70 8010bbe: 81fb strh r3, [r7, #14] 8010bc0: 89fb ldrh r3, [r7, #14] 8010bc2: f483 5380 eor.w r3, r3, #4096 @ 0x1000 8010bc6: 81fb strh r3, [r7, #14] 8010bc8: 687a ldr r2, [r7, #4] 8010bca: 683b ldr r3, [r7, #0] 8010bcc: 781b ldrb r3, [r3, #0] 8010bce: 009b lsls r3, r3, #2 8010bd0: 441a add r2, r3 8010bd2: 89fb ldrh r3, [r7, #14] 8010bd4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010bd8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010bdc: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010be0: f043 0380 orr.w r3, r3, #128 @ 0x80 8010be4: b29b uxth r3, r3 8010be6: 8013 strh r3, [r2, #0] } return HAL_OK; 8010be8: 2300 movs r3, #0 } 8010bea: 4618 mov r0, r3 8010bec: 3714 adds r7, #20 8010bee: 46bd mov sp, r7 8010bf0: f85d 7b04 ldr.w r7, [sp], #4 8010bf4: 4770 bx lr 08010bf6 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { 8010bf6: b480 push {r7} 8010bf8: b087 sub sp, #28 8010bfa: af00 add r7, sp, #0 8010bfc: 6078 str r0, [r7, #4] 8010bfe: 6039 str r1, [r7, #0] if (ep->is_in != 0U) 8010c00: 683b ldr r3, [r7, #0] 8010c02: 785b ldrb r3, [r3, #1] 8010c04: 2b00 cmp r3, #0 8010c06: d04c beq.n 8010ca2 { PCD_CLEAR_TX_DTOG(USBx, ep->num); 8010c08: 687a ldr r2, [r7, #4] 8010c0a: 683b ldr r3, [r7, #0] 8010c0c: 781b ldrb r3, [r3, #0] 8010c0e: 009b lsls r3, r3, #2 8010c10: 4413 add r3, r2 8010c12: 881b ldrh r3, [r3, #0] 8010c14: 823b strh r3, [r7, #16] 8010c16: 8a3b ldrh r3, [r7, #16] 8010c18: f003 0340 and.w r3, r3, #64 @ 0x40 8010c1c: 2b00 cmp r3, #0 8010c1e: d01b beq.n 8010c58 8010c20: 687a ldr r2, [r7, #4] 8010c22: 683b ldr r3, [r7, #0] 8010c24: 781b ldrb r3, [r3, #0] 8010c26: 009b lsls r3, r3, #2 8010c28: 4413 add r3, r2 8010c2a: 881b ldrh r3, [r3, #0] 8010c2c: b29b uxth r3, r3 8010c2e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010c32: f023 0370 bic.w r3, r3, #112 @ 0x70 8010c36: 81fb strh r3, [r7, #14] 8010c38: 687a ldr r2, [r7, #4] 8010c3a: 683b ldr r3, [r7, #0] 8010c3c: 781b ldrb r3, [r3, #0] 8010c3e: 009b lsls r3, r3, #2 8010c40: 441a add r2, r3 8010c42: 89fb ldrh r3, [r7, #14] 8010c44: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010c48: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010c4c: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010c50: f043 03c0 orr.w r3, r3, #192 @ 0xc0 8010c54: b29b uxth r3, r3 8010c56: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8010c58: 683b ldr r3, [r7, #0] 8010c5a: 78db ldrb r3, [r3, #3] 8010c5c: 2b01 cmp r3, #1 8010c5e: d06c beq.n 8010d3a { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 8010c60: 687a ldr r2, [r7, #4] 8010c62: 683b ldr r3, [r7, #0] 8010c64: 781b ldrb r3, [r3, #0] 8010c66: 009b lsls r3, r3, #2 8010c68: 4413 add r3, r2 8010c6a: 881b ldrh r3, [r3, #0] 8010c6c: b29b uxth r3, r3 8010c6e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010c72: f023 0340 bic.w r3, r3, #64 @ 0x40 8010c76: 81bb strh r3, [r7, #12] 8010c78: 89bb ldrh r3, [r7, #12] 8010c7a: f083 0320 eor.w r3, r3, #32 8010c7e: 81bb strh r3, [r7, #12] 8010c80: 687a ldr r2, [r7, #4] 8010c82: 683b ldr r3, [r7, #0] 8010c84: 781b ldrb r3, [r3, #0] 8010c86: 009b lsls r3, r3, #2 8010c88: 441a add r2, r3 8010c8a: 89bb ldrh r3, [r7, #12] 8010c8c: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010c90: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010c94: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010c98: f043 0380 orr.w r3, r3, #128 @ 0x80 8010c9c: b29b uxth r3, r3 8010c9e: 8013 strh r3, [r2, #0] 8010ca0: e04b b.n 8010d3a } } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); 8010ca2: 687a ldr r2, [r7, #4] 8010ca4: 683b ldr r3, [r7, #0] 8010ca6: 781b ldrb r3, [r3, #0] 8010ca8: 009b lsls r3, r3, #2 8010caa: 4413 add r3, r2 8010cac: 881b ldrh r3, [r3, #0] 8010cae: 82fb strh r3, [r7, #22] 8010cb0: 8afb ldrh r3, [r7, #22] 8010cb2: f403 4380 and.w r3, r3, #16384 @ 0x4000 8010cb6: 2b00 cmp r3, #0 8010cb8: d01b beq.n 8010cf2 8010cba: 687a ldr r2, [r7, #4] 8010cbc: 683b ldr r3, [r7, #0] 8010cbe: 781b ldrb r3, [r3, #0] 8010cc0: 009b lsls r3, r3, #2 8010cc2: 4413 add r3, r2 8010cc4: 881b ldrh r3, [r3, #0] 8010cc6: b29b uxth r3, r3 8010cc8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 8010ccc: f023 0370 bic.w r3, r3, #112 @ 0x70 8010cd0: 82bb strh r3, [r7, #20] 8010cd2: 687a ldr r2, [r7, #4] 8010cd4: 683b ldr r3, [r7, #0] 8010cd6: 781b ldrb r3, [r3, #0] 8010cd8: 009b lsls r3, r3, #2 8010cda: 441a add r2, r3 8010cdc: 8abb ldrh r3, [r7, #20] 8010cde: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010ce2: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010ce6: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8010cea: f043 0380 orr.w r3, r3, #128 @ 0x80 8010cee: b29b uxth r3, r3 8010cf0: 8013 strh r3, [r2, #0] /* Configure VALID status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 8010cf2: 687a ldr r2, [r7, #4] 8010cf4: 683b ldr r3, [r7, #0] 8010cf6: 781b ldrb r3, [r3, #0] 8010cf8: 009b lsls r3, r3, #2 8010cfa: 4413 add r3, r2 8010cfc: 881b ldrh r3, [r3, #0] 8010cfe: b29b uxth r3, r3 8010d00: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010d04: f023 0370 bic.w r3, r3, #112 @ 0x70 8010d08: 827b strh r3, [r7, #18] 8010d0a: 8a7b ldrh r3, [r7, #18] 8010d0c: f483 5380 eor.w r3, r3, #4096 @ 0x1000 8010d10: 827b strh r3, [r7, #18] 8010d12: 8a7b ldrh r3, [r7, #18] 8010d14: f483 5300 eor.w r3, r3, #8192 @ 0x2000 8010d18: 827b strh r3, [r7, #18] 8010d1a: 687a ldr r2, [r7, #4] 8010d1c: 683b ldr r3, [r7, #0] 8010d1e: 781b ldrb r3, [r3, #0] 8010d20: 009b lsls r3, r3, #2 8010d22: 441a add r2, r3 8010d24: 8a7b ldrh r3, [r7, #18] 8010d26: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8010d2a: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8010d2e: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8010d32: f043 0380 orr.w r3, r3, #128 @ 0x80 8010d36: b29b uxth r3, r3 8010d38: 8013 strh r3, [r2, #0] } return HAL_OK; 8010d3a: 2300 movs r3, #0 } 8010d3c: 4618 mov r0, r3 8010d3e: 371c adds r7, #28 8010d40: 46bd mov sp, r7 8010d42: f85d 7b04 ldr.w r7, [sp], #4 8010d46: 4770 bx lr 08010d48 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) { 8010d48: b480 push {r7} 8010d4a: b083 sub sp, #12 8010d4c: af00 add r7, sp, #0 8010d4e: 6078 str r0, [r7, #4] 8010d50: 460b mov r3, r1 8010d52: 70fb strb r3, [r7, #3] if (address == 0U) 8010d54: 78fb ldrb r3, [r7, #3] 8010d56: 2b00 cmp r3, #0 8010d58: d103 bne.n 8010d62 { /* set device address and enable function */ USBx->DADDR = (uint16_t)USB_DADDR_EF; 8010d5a: 687b ldr r3, [r7, #4] 8010d5c: 2280 movs r2, #128 @ 0x80 8010d5e: f8a3 204c strh.w r2, [r3, #76] @ 0x4c } return HAL_OK; 8010d62: 2300 movs r3, #0 } 8010d64: 4618 mov r0, r3 8010d66: 370c adds r7, #12 8010d68: 46bd mov sp, r7 8010d6a: f85d 7b04 ldr.w r7, [sp], #4 8010d6e: 4770 bx lr 08010d70 : * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { 8010d70: b480 push {r7} 8010d72: b083 sub sp, #12 8010d74: af00 add r7, sp, #0 8010d76: 6078 str r0, [r7, #4] /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ USBx->BCDR |= (uint16_t)USB_BCDR_DPPU; 8010d78: 687b ldr r3, [r7, #4] 8010d7a: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58 8010d7e: b29b uxth r3, r3 8010d80: ea6f 4343 mvn.w r3, r3, lsl #17 8010d84: ea6f 4353 mvn.w r3, r3, lsr #17 8010d88: b29a uxth r2, r3 8010d8a: 687b ldr r3, [r7, #4] 8010d8c: f8a3 2058 strh.w r2, [r3, #88] @ 0x58 return HAL_OK; 8010d90: 2300 movs r3, #0 } 8010d92: 4618 mov r0, r3 8010d94: 370c adds r7, #12 8010d96: 46bd mov sp, r7 8010d98: f85d 7b04 ldr.w r7, [sp], #4 8010d9c: 4770 bx lr 08010d9e : * @brief USB_ReadInterrupts return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) { 8010d9e: b480 push {r7} 8010da0: b085 sub sp, #20 8010da2: af00 add r7, sp, #0 8010da4: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->ISTR; 8010da6: 687b ldr r3, [r7, #4] 8010da8: f8b3 3044 ldrh.w r3, [r3, #68] @ 0x44 8010dac: b29b uxth r3, r3 8010dae: 60fb str r3, [r7, #12] return tmpreg; 8010db0: 68fb ldr r3, [r7, #12] } 8010db2: 4618 mov r0, r3 8010db4: 3714 adds r7, #20 8010db6: 46bd mov sp, r7 8010db8: f85d 7b04 ldr.w r7, [sp], #4 8010dbc: 4770 bx lr 08010dbe : * @param wPMABufAddr address into PMA. * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { 8010dbe: b480 push {r7} 8010dc0: b08b sub sp, #44 @ 0x2c 8010dc2: af00 add r7, sp, #0 8010dc4: 60f8 str r0, [r7, #12] 8010dc6: 60b9 str r1, [r7, #8] 8010dc8: 4611 mov r1, r2 8010dca: 461a mov r2, r3 8010dcc: 460b mov r3, r1 8010dce: 80fb strh r3, [r7, #6] 8010dd0: 4613 mov r3, r2 8010dd2: 80bb strh r3, [r7, #4] uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; 8010dd4: 88bb ldrh r3, [r7, #4] 8010dd6: 3301 adds r3, #1 8010dd8: 085b lsrs r3, r3, #1 8010dda: 61bb str r3, [r7, #24] uint32_t BaseAddr = (uint32_t)USBx; 8010ddc: 68fb ldr r3, [r7, #12] 8010dde: 617b str r3, [r7, #20] uint32_t count; uint16_t WrVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; 8010de0: 68bb ldr r3, [r7, #8] 8010de2: 61fb str r3, [r7, #28] pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); 8010de4: 88fa ldrh r2, [r7, #6] 8010de6: 697b ldr r3, [r7, #20] 8010de8: 4413 add r3, r2 8010dea: f503 6380 add.w r3, r3, #1024 @ 0x400 8010dee: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) 8010df0: 69bb ldr r3, [r7, #24] 8010df2: 627b str r3, [r7, #36] @ 0x24 8010df4: e01c b.n 8010e30 { WrVal = pBuf[0]; 8010df6: 69fb ldr r3, [r7, #28] 8010df8: 781b ldrb r3, [r3, #0] 8010dfa: 827b strh r3, [r7, #18] WrVal |= (uint16_t)pBuf[1] << 8; 8010dfc: 69fb ldr r3, [r7, #28] 8010dfe: 3301 adds r3, #1 8010e00: 781b ldrb r3, [r3, #0] 8010e02: b21b sxth r3, r3 8010e04: 021b lsls r3, r3, #8 8010e06: b21a sxth r2, r3 8010e08: f9b7 3012 ldrsh.w r3, [r7, #18] 8010e0c: 4313 orrs r3, r2 8010e0e: b21b sxth r3, r3 8010e10: 827b strh r3, [r7, #18] *pdwVal = (WrVal & 0xFFFFU); 8010e12: 6a3b ldr r3, [r7, #32] 8010e14: 8a7a ldrh r2, [r7, #18] 8010e16: 801a strh r2, [r3, #0] pdwVal++; 8010e18: 6a3b ldr r3, [r7, #32] 8010e1a: 3302 adds r3, #2 8010e1c: 623b str r3, [r7, #32] #if PMA_ACCESS > 1U pdwVal++; #endif /* PMA_ACCESS */ pBuf++; 8010e1e: 69fb ldr r3, [r7, #28] 8010e20: 3301 adds r3, #1 8010e22: 61fb str r3, [r7, #28] pBuf++; 8010e24: 69fb ldr r3, [r7, #28] 8010e26: 3301 adds r3, #1 8010e28: 61fb str r3, [r7, #28] for (count = n; count != 0U; count--) 8010e2a: 6a7b ldr r3, [r7, #36] @ 0x24 8010e2c: 3b01 subs r3, #1 8010e2e: 627b str r3, [r7, #36] @ 0x24 8010e30: 6a7b ldr r3, [r7, #36] @ 0x24 8010e32: 2b00 cmp r3, #0 8010e34: d1df bne.n 8010df6 } } 8010e36: bf00 nop 8010e38: bf00 nop 8010e3a: 372c adds r7, #44 @ 0x2c 8010e3c: 46bd mov sp, r7 8010e3e: f85d 7b04 ldr.w r7, [sp], #4 8010e42: 4770 bx lr 08010e44 : * @param wPMABufAddr address into PMA. * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { 8010e44: b480 push {r7} 8010e46: b08b sub sp, #44 @ 0x2c 8010e48: af00 add r7, sp, #0 8010e4a: 60f8 str r0, [r7, #12] 8010e4c: 60b9 str r1, [r7, #8] 8010e4e: 4611 mov r1, r2 8010e50: 461a mov r2, r3 8010e52: 460b mov r3, r1 8010e54: 80fb strh r3, [r7, #6] 8010e56: 4613 mov r3, r2 8010e58: 80bb strh r3, [r7, #4] uint32_t n = (uint32_t)wNBytes >> 1; 8010e5a: 88bb ldrh r3, [r7, #4] 8010e5c: 085b lsrs r3, r3, #1 8010e5e: b29b uxth r3, r3 8010e60: 61bb str r3, [r7, #24] uint32_t BaseAddr = (uint32_t)USBx; 8010e62: 68fb ldr r3, [r7, #12] 8010e64: 617b str r3, [r7, #20] uint32_t count; uint32_t RdVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; 8010e66: 68bb ldr r3, [r7, #8] 8010e68: 61fb str r3, [r7, #28] pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); 8010e6a: 88fa ldrh r2, [r7, #6] 8010e6c: 697b ldr r3, [r7, #20] 8010e6e: 4413 add r3, r2 8010e70: f503 6380 add.w r3, r3, #1024 @ 0x400 8010e74: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) 8010e76: 69bb ldr r3, [r7, #24] 8010e78: 627b str r3, [r7, #36] @ 0x24 8010e7a: e018 b.n 8010eae { RdVal = *(__IO uint16_t *)pdwVal; 8010e7c: 6a3b ldr r3, [r7, #32] 8010e7e: 881b ldrh r3, [r3, #0] 8010e80: b29b uxth r3, r3 8010e82: 613b str r3, [r7, #16] pdwVal++; 8010e84: 6a3b ldr r3, [r7, #32] 8010e86: 3302 adds r3, #2 8010e88: 623b str r3, [r7, #32] *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); 8010e8a: 693b ldr r3, [r7, #16] 8010e8c: b2da uxtb r2, r3 8010e8e: 69fb ldr r3, [r7, #28] 8010e90: 701a strb r2, [r3, #0] pBuf++; 8010e92: 69fb ldr r3, [r7, #28] 8010e94: 3301 adds r3, #1 8010e96: 61fb str r3, [r7, #28] *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU); 8010e98: 693b ldr r3, [r7, #16] 8010e9a: 0a1b lsrs r3, r3, #8 8010e9c: b2da uxtb r2, r3 8010e9e: 69fb ldr r3, [r7, #28] 8010ea0: 701a strb r2, [r3, #0] pBuf++; 8010ea2: 69fb ldr r3, [r7, #28] 8010ea4: 3301 adds r3, #1 8010ea6: 61fb str r3, [r7, #28] for (count = n; count != 0U; count--) 8010ea8: 6a7b ldr r3, [r7, #36] @ 0x24 8010eaa: 3b01 subs r3, #1 8010eac: 627b str r3, [r7, #36] @ 0x24 8010eae: 6a7b ldr r3, [r7, #36] @ 0x24 8010eb0: 2b00 cmp r3, #0 8010eb2: d1e3 bne.n 8010e7c #if PMA_ACCESS > 1U pdwVal++; #endif /* PMA_ACCESS */ } if ((wNBytes % 2U) != 0U) 8010eb4: 88bb ldrh r3, [r7, #4] 8010eb6: f003 0301 and.w r3, r3, #1 8010eba: b29b uxth r3, r3 8010ebc: 2b00 cmp r3, #0 8010ebe: d007 beq.n 8010ed0 { RdVal = *pdwVal; 8010ec0: 6a3b ldr r3, [r7, #32] 8010ec2: 881b ldrh r3, [r3, #0] 8010ec4: b29b uxth r3, r3 8010ec6: 613b str r3, [r7, #16] *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); 8010ec8: 693b ldr r3, [r7, #16] 8010eca: b2da uxtb r2, r3 8010ecc: 69fb ldr r3, [r7, #28] 8010ece: 701a strb r2, [r3, #0] } } 8010ed0: bf00 nop 8010ed2: 372c adds r7, #44 @ 0x2c 8010ed4: 46bd mov sp, r7 8010ed6: f85d 7b04 ldr.w r7, [sp], #4 8010eda: 4770 bx lr 08010edc : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8010edc: b580 push {r7, lr} 8010ede: b084 sub sp, #16 8010ee0: af00 add r7, sp, #0 8010ee2: 6078 str r0, [r7, #4] 8010ee4: 460b mov r3, r1 8010ee6: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_CDC_HandleTypeDef *hcdc; hcdc = (USBD_CDC_HandleTypeDef *)USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); 8010ee8: f44f 7007 mov.w r0, #540 @ 0x21c 8010eec: f008 f9ca bl 8019284 8010ef0: 60f8 str r0, [r7, #12] if (hcdc == NULL) 8010ef2: 68fb ldr r3, [r7, #12] 8010ef4: 2b00 cmp r3, #0 8010ef6: d109 bne.n 8010f0c { pdev->pClassDataCmsit[pdev->classId] = NULL; 8010ef8: 687b ldr r3, [r7, #4] 8010efa: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010efe: 687b ldr r3, [r7, #4] 8010f00: 32b0 adds r2, #176 @ 0xb0 8010f02: 2100 movs r1, #0 8010f04: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; 8010f08: 2302 movs r3, #2 8010f0a: e0d4 b.n 80110b6 } (void)USBD_memset(hcdc, 0, sizeof(USBD_CDC_HandleTypeDef)); 8010f0c: f44f 7207 mov.w r2, #540 @ 0x21c 8010f10: 2100 movs r1, #0 8010f12: 68f8 ldr r0, [r7, #12] 8010f14: f009 f9e6 bl 801a2e4 pdev->pClassDataCmsit[pdev->classId] = (void *)hcdc; 8010f18: 687b ldr r3, [r7, #4] 8010f1a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010f1e: 687b ldr r3, [r7, #4] 8010f20: 32b0 adds r2, #176 @ 0xb0 8010f22: 68f9 ldr r1, [r7, #12] 8010f24: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; 8010f28: 687b ldr r3, [r7, #4] 8010f2a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8010f2e: 687b ldr r3, [r7, #4] 8010f30: 32b0 adds r2, #176 @ 0xb0 8010f32: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8010f36: 687b ldr r3, [r7, #4] 8010f38: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) 8010f3c: 687b ldr r3, [r7, #4] 8010f3e: 7c1b ldrb r3, [r3, #16] 8010f40: 2b00 cmp r3, #0 8010f42: d138 bne.n 8010fb6 { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK, 8010f44: 4b5e ldr r3, [pc, #376] @ (80110c0 ) 8010f46: 7819 ldrb r1, [r3, #0] 8010f48: f44f 7300 mov.w r3, #512 @ 0x200 8010f4c: 2202 movs r2, #2 8010f4e: 6878 ldr r0, [r7, #4] 8010f50: f008 f83f bl 8018fd2 CDC_DATA_HS_IN_PACKET_SIZE); pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U; 8010f54: 4b5a ldr r3, [pc, #360] @ (80110c0 ) 8010f56: 781b ldrb r3, [r3, #0] 8010f58: f003 020f and.w r2, r3, #15 8010f5c: 6879 ldr r1, [r7, #4] 8010f5e: 4613 mov r3, r2 8010f60: 009b lsls r3, r3, #2 8010f62: 4413 add r3, r2 8010f64: 009b lsls r3, r3, #2 8010f66: 440b add r3, r1 8010f68: 3323 adds r3, #35 @ 0x23 8010f6a: 2201 movs r2, #1 8010f6c: 701a strb r2, [r3, #0] /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK, 8010f6e: 4b55 ldr r3, [pc, #340] @ (80110c4 ) 8010f70: 7819 ldrb r1, [r3, #0] 8010f72: f44f 7300 mov.w r3, #512 @ 0x200 8010f76: 2202 movs r2, #2 8010f78: 6878 ldr r0, [r7, #4] 8010f7a: f008 f82a bl 8018fd2 CDC_DATA_HS_OUT_PACKET_SIZE); pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U; 8010f7e: 4b51 ldr r3, [pc, #324] @ (80110c4 ) 8010f80: 781b ldrb r3, [r3, #0] 8010f82: f003 020f and.w r2, r3, #15 8010f86: 6879 ldr r1, [r7, #4] 8010f88: 4613 mov r3, r2 8010f8a: 009b lsls r3, r3, #2 8010f8c: 4413 add r3, r2 8010f8e: 009b lsls r3, r3, #2 8010f90: 440b add r3, r1 8010f92: f203 1363 addw r3, r3, #355 @ 0x163 8010f96: 2201 movs r2, #1 8010f98: 701a strb r2, [r3, #0] /* Set bInterval for CDC CMD Endpoint */ pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_HS_BINTERVAL; 8010f9a: 4b4b ldr r3, [pc, #300] @ (80110c8 ) 8010f9c: 781b ldrb r3, [r3, #0] 8010f9e: f003 020f and.w r2, r3, #15 8010fa2: 6879 ldr r1, [r7, #4] 8010fa4: 4613 mov r3, r2 8010fa6: 009b lsls r3, r3, #2 8010fa8: 4413 add r3, r2 8010faa: 009b lsls r3, r3, #2 8010fac: 440b add r3, r1 8010fae: 331c adds r3, #28 8010fb0: 2210 movs r2, #16 8010fb2: 601a str r2, [r3, #0] 8010fb4: e035 b.n 8011022 } else { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK, 8010fb6: 4b42 ldr r3, [pc, #264] @ (80110c0 ) 8010fb8: 7819 ldrb r1, [r3, #0] 8010fba: 2340 movs r3, #64 @ 0x40 8010fbc: 2202 movs r2, #2 8010fbe: 6878 ldr r0, [r7, #4] 8010fc0: f008 f807 bl 8018fd2 CDC_DATA_FS_IN_PACKET_SIZE); pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U; 8010fc4: 4b3e ldr r3, [pc, #248] @ (80110c0 ) 8010fc6: 781b ldrb r3, [r3, #0] 8010fc8: f003 020f and.w r2, r3, #15 8010fcc: 6879 ldr r1, [r7, #4] 8010fce: 4613 mov r3, r2 8010fd0: 009b lsls r3, r3, #2 8010fd2: 4413 add r3, r2 8010fd4: 009b lsls r3, r3, #2 8010fd6: 440b add r3, r1 8010fd8: 3323 adds r3, #35 @ 0x23 8010fda: 2201 movs r2, #1 8010fdc: 701a strb r2, [r3, #0] /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK, 8010fde: 4b39 ldr r3, [pc, #228] @ (80110c4 ) 8010fe0: 7819 ldrb r1, [r3, #0] 8010fe2: 2340 movs r3, #64 @ 0x40 8010fe4: 2202 movs r2, #2 8010fe6: 6878 ldr r0, [r7, #4] 8010fe8: f007 fff3 bl 8018fd2 CDC_DATA_FS_OUT_PACKET_SIZE); pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U; 8010fec: 4b35 ldr r3, [pc, #212] @ (80110c4 ) 8010fee: 781b ldrb r3, [r3, #0] 8010ff0: f003 020f and.w r2, r3, #15 8010ff4: 6879 ldr r1, [r7, #4] 8010ff6: 4613 mov r3, r2 8010ff8: 009b lsls r3, r3, #2 8010ffa: 4413 add r3, r2 8010ffc: 009b lsls r3, r3, #2 8010ffe: 440b add r3, r1 8011000: f203 1363 addw r3, r3, #355 @ 0x163 8011004: 2201 movs r2, #1 8011006: 701a strb r2, [r3, #0] /* Set bInterval for CMD Endpoint */ pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_FS_BINTERVAL; 8011008: 4b2f ldr r3, [pc, #188] @ (80110c8 ) 801100a: 781b ldrb r3, [r3, #0] 801100c: f003 020f and.w r2, r3, #15 8011010: 6879 ldr r1, [r7, #4] 8011012: 4613 mov r3, r2 8011014: 009b lsls r3, r3, #2 8011016: 4413 add r3, r2 8011018: 009b lsls r3, r3, #2 801101a: 440b add r3, r1 801101c: 331c adds r3, #28 801101e: 2210 movs r2, #16 8011020: 601a str r2, [r3, #0] } /* Open Command IN EP */ (void)USBD_LL_OpenEP(pdev, CDCCmdEpAdd, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); 8011022: 4b29 ldr r3, [pc, #164] @ (80110c8 ) 8011024: 7819 ldrb r1, [r3, #0] 8011026: 2308 movs r3, #8 8011028: 2203 movs r2, #3 801102a: 6878 ldr r0, [r7, #4] 801102c: f007 ffd1 bl 8018fd2 pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 1U; 8011030: 4b25 ldr r3, [pc, #148] @ (80110c8 ) 8011032: 781b ldrb r3, [r3, #0] 8011034: f003 020f and.w r2, r3, #15 8011038: 6879 ldr r1, [r7, #4] 801103a: 4613 mov r3, r2 801103c: 009b lsls r3, r3, #2 801103e: 4413 add r3, r2 8011040: 009b lsls r3, r3, #2 8011042: 440b add r3, r1 8011044: 3323 adds r3, #35 @ 0x23 8011046: 2201 movs r2, #1 8011048: 701a strb r2, [r3, #0] hcdc->RxBuffer = NULL; 801104a: 68fb ldr r3, [r7, #12] 801104c: 2200 movs r2, #0 801104e: f8c3 2204 str.w r2, [r3, #516] @ 0x204 /* Init physical Interface components */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Init(); 8011052: 687b ldr r3, [r7, #4] 8011054: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8011058: 687a ldr r2, [r7, #4] 801105a: 33b0 adds r3, #176 @ 0xb0 801105c: 009b lsls r3, r3, #2 801105e: 4413 add r3, r2 8011060: 685b ldr r3, [r3, #4] 8011062: 681b ldr r3, [r3, #0] 8011064: 4798 blx r3 /* Init Xfer states */ hcdc->TxState = 0U; 8011066: 68fb ldr r3, [r7, #12] 8011068: 2200 movs r2, #0 801106a: f8c3 2214 str.w r2, [r3, #532] @ 0x214 hcdc->RxState = 0U; 801106e: 68fb ldr r3, [r7, #12] 8011070: 2200 movs r2, #0 8011072: f8c3 2218 str.w r2, [r3, #536] @ 0x218 if (hcdc->RxBuffer == NULL) 8011076: 68fb ldr r3, [r7, #12] 8011078: f8d3 3204 ldr.w r3, [r3, #516] @ 0x204 801107c: 2b00 cmp r3, #0 801107e: d101 bne.n 8011084 { return (uint8_t)USBD_EMEM; 8011080: 2302 movs r3, #2 8011082: e018 b.n 80110b6 } if (pdev->dev_speed == USBD_SPEED_HIGH) 8011084: 687b ldr r3, [r7, #4] 8011086: 7c1b ldrb r3, [r3, #16] 8011088: 2b00 cmp r3, #0 801108a: d10a bne.n 80110a2 { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, 801108c: 4b0d ldr r3, [pc, #52] @ (80110c4 ) 801108e: 7819 ldrb r1, [r3, #0] 8011090: 68fb ldr r3, [r7, #12] 8011092: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8011096: f44f 7300 mov.w r3, #512 @ 0x200 801109a: 6878 ldr r0, [r7, #4] 801109c: f008 f888 bl 80191b0 80110a0: e008 b.n 80110b4 CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, 80110a2: 4b08 ldr r3, [pc, #32] @ (80110c4 ) 80110a4: 7819 ldrb r1, [r3, #0] 80110a6: 68fb ldr r3, [r7, #12] 80110a8: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 80110ac: 2340 movs r3, #64 @ 0x40 80110ae: 6878 ldr r0, [r7, #4] 80110b0: f008 f87e bl 80191b0 CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 80110b4: 2300 movs r3, #0 } 80110b6: 4618 mov r0, r3 80110b8: 3710 adds r7, #16 80110ba: 46bd mov sp, r7 80110bc: bd80 pop {r7, pc} 80110be: bf00 nop 80110c0: 2000009f .word 0x2000009f 80110c4: 200000a0 .word 0x200000a0 80110c8: 200000a1 .word 0x200000a1 080110cc : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80110cc: b580 push {r7, lr} 80110ce: b082 sub sp, #8 80110d0: af00 add r7, sp, #0 80110d2: 6078 str r0, [r7, #4] 80110d4: 460b mov r3, r1 80110d6: 70fb strb r3, [r7, #3] CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ /* Close EP IN */ (void)USBD_LL_CloseEP(pdev, CDCInEpAdd); 80110d8: 4b3a ldr r3, [pc, #232] @ (80111c4 ) 80110da: 781b ldrb r3, [r3, #0] 80110dc: 4619 mov r1, r3 80110de: 6878 ldr r0, [r7, #4] 80110e0: f007 ff9d bl 801901e pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 0U; 80110e4: 4b37 ldr r3, [pc, #220] @ (80111c4 ) 80110e6: 781b ldrb r3, [r3, #0] 80110e8: f003 020f and.w r2, r3, #15 80110ec: 6879 ldr r1, [r7, #4] 80110ee: 4613 mov r3, r2 80110f0: 009b lsls r3, r3, #2 80110f2: 4413 add r3, r2 80110f4: 009b lsls r3, r3, #2 80110f6: 440b add r3, r1 80110f8: 3323 adds r3, #35 @ 0x23 80110fa: 2200 movs r2, #0 80110fc: 701a strb r2, [r3, #0] /* Close EP OUT */ (void)USBD_LL_CloseEP(pdev, CDCOutEpAdd); 80110fe: 4b32 ldr r3, [pc, #200] @ (80111c8 ) 8011100: 781b ldrb r3, [r3, #0] 8011102: 4619 mov r1, r3 8011104: 6878 ldr r0, [r7, #4] 8011106: f007 ff8a bl 801901e pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 0U; 801110a: 4b2f ldr r3, [pc, #188] @ (80111c8 ) 801110c: 781b ldrb r3, [r3, #0] 801110e: f003 020f and.w r2, r3, #15 8011112: 6879 ldr r1, [r7, #4] 8011114: 4613 mov r3, r2 8011116: 009b lsls r3, r3, #2 8011118: 4413 add r3, r2 801111a: 009b lsls r3, r3, #2 801111c: 440b add r3, r1 801111e: f203 1363 addw r3, r3, #355 @ 0x163 8011122: 2200 movs r2, #0 8011124: 701a strb r2, [r3, #0] /* Close Command IN EP */ (void)USBD_LL_CloseEP(pdev, CDCCmdEpAdd); 8011126: 4b29 ldr r3, [pc, #164] @ (80111cc ) 8011128: 781b ldrb r3, [r3, #0] 801112a: 4619 mov r1, r3 801112c: 6878 ldr r0, [r7, #4] 801112e: f007 ff76 bl 801901e pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 0U; 8011132: 4b26 ldr r3, [pc, #152] @ (80111cc ) 8011134: 781b ldrb r3, [r3, #0] 8011136: f003 020f and.w r2, r3, #15 801113a: 6879 ldr r1, [r7, #4] 801113c: 4613 mov r3, r2 801113e: 009b lsls r3, r3, #2 8011140: 4413 add r3, r2 8011142: 009b lsls r3, r3, #2 8011144: 440b add r3, r1 8011146: 3323 adds r3, #35 @ 0x23 8011148: 2200 movs r2, #0 801114a: 701a strb r2, [r3, #0] pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = 0U; 801114c: 4b1f ldr r3, [pc, #124] @ (80111cc ) 801114e: 781b ldrb r3, [r3, #0] 8011150: f003 020f and.w r2, r3, #15 8011154: 6879 ldr r1, [r7, #4] 8011156: 4613 mov r3, r2 8011158: 009b lsls r3, r3, #2 801115a: 4413 add r3, r2 801115c: 009b lsls r3, r3, #2 801115e: 440b add r3, r1 8011160: 331c adds r3, #28 8011162: 2200 movs r2, #0 8011164: 601a str r2, [r3, #0] /* DeInit physical Interface components */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) 8011166: 687b ldr r3, [r7, #4] 8011168: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 801116c: 687b ldr r3, [r7, #4] 801116e: 32b0 adds r2, #176 @ 0xb0 8011170: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011174: 2b00 cmp r3, #0 8011176: d01f beq.n 80111b8 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->DeInit(); 8011178: 687b ldr r3, [r7, #4] 801117a: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 801117e: 687a ldr r2, [r7, #4] 8011180: 33b0 adds r3, #176 @ 0xb0 8011182: 009b lsls r3, r3, #2 8011184: 4413 add r3, r2 8011186: 685b ldr r3, [r3, #4] 8011188: 685b ldr r3, [r3, #4] 801118a: 4798 blx r3 (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); 801118c: 687b ldr r3, [r7, #4] 801118e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8011192: 687b ldr r3, [r7, #4] 8011194: 32b0 adds r2, #176 @ 0xb0 8011196: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801119a: 4618 mov r0, r3 801119c: f008 f880 bl 80192a0 pdev->pClassDataCmsit[pdev->classId] = NULL; 80111a0: 687b ldr r3, [r7, #4] 80111a2: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80111a6: 687b ldr r3, [r7, #4] 80111a8: 32b0 adds r2, #176 @ 0xb0 80111aa: 2100 movs r1, #0 80111ac: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = NULL; 80111b0: 687b ldr r3, [r7, #4] 80111b2: 2200 movs r2, #0 80111b4: f8c3 22bc str.w r2, [r3, #700] @ 0x2bc } return (uint8_t)USBD_OK; 80111b8: 2300 movs r3, #0 } 80111ba: 4618 mov r0, r3 80111bc: 3708 adds r7, #8 80111be: 46bd mov sp, r7 80111c0: bd80 pop {r7, pc} 80111c2: bf00 nop 80111c4: 2000009f .word 0x2000009f 80111c8: 200000a0 .word 0x200000a0 80111cc: 200000a1 .word 0x200000a1 080111d0 : * @param req: usb requests * @retval status */ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80111d0: b580 push {r7, lr} 80111d2: b086 sub sp, #24 80111d4: af00 add r7, sp, #0 80111d6: 6078 str r0, [r7, #4] 80111d8: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80111da: 687b ldr r3, [r7, #4] 80111dc: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80111e0: 687b ldr r3, [r7, #4] 80111e2: 32b0 adds r2, #176 @ 0xb0 80111e4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80111e8: 613b str r3, [r7, #16] uint16_t len; uint8_t ifalt = 0U; 80111ea: 2300 movs r3, #0 80111ec: 737b strb r3, [r7, #13] uint16_t status_info = 0U; 80111ee: 2300 movs r3, #0 80111f0: 817b strh r3, [r7, #10] USBD_StatusTypeDef ret = USBD_OK; 80111f2: 2300 movs r3, #0 80111f4: 75fb strb r3, [r7, #23] if (hcdc == NULL) 80111f6: 693b ldr r3, [r7, #16] 80111f8: 2b00 cmp r3, #0 80111fa: d101 bne.n 8011200 { return (uint8_t)USBD_FAIL; 80111fc: 2303 movs r3, #3 80111fe: e0bf b.n 8011380 } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8011200: 683b ldr r3, [r7, #0] 8011202: 781b ldrb r3, [r3, #0] 8011204: f003 0360 and.w r3, r3, #96 @ 0x60 8011208: 2b00 cmp r3, #0 801120a: d050 beq.n 80112ae 801120c: 2b20 cmp r3, #32 801120e: f040 80af bne.w 8011370 { case USB_REQ_TYPE_CLASS: if (req->wLength != 0U) 8011212: 683b ldr r3, [r7, #0] 8011214: 88db ldrh r3, [r3, #6] 8011216: 2b00 cmp r3, #0 8011218: d03a beq.n 8011290 { if ((req->bmRequest & 0x80U) != 0U) 801121a: 683b ldr r3, [r7, #0] 801121c: 781b ldrb r3, [r3, #0] 801121e: b25b sxtb r3, r3 8011220: 2b00 cmp r3, #0 8011222: da1b bge.n 801125c { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, 8011224: 687b ldr r3, [r7, #4] 8011226: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 801122a: 687a ldr r2, [r7, #4] 801122c: 33b0 adds r3, #176 @ 0xb0 801122e: 009b lsls r3, r3, #2 8011230: 4413 add r3, r2 8011232: 685b ldr r3, [r3, #4] 8011234: 689b ldr r3, [r3, #8] 8011236: 683a ldr r2, [r7, #0] 8011238: 7850 ldrb r0, [r2, #1] (uint8_t *)hcdc->data, 801123a: 6939 ldr r1, [r7, #16] ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, 801123c: 683a ldr r2, [r7, #0] 801123e: 88d2 ldrh r2, [r2, #6] 8011240: 4798 blx r3 req->wLength); len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength); 8011242: 683b ldr r3, [r7, #0] 8011244: 88db ldrh r3, [r3, #6] 8011246: 2b07 cmp r3, #7 8011248: bf28 it cs 801124a: 2307 movcs r3, #7 801124c: 81fb strh r3, [r7, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len); 801124e: 693b ldr r3, [r7, #16] 8011250: 89fa ldrh r2, [r7, #14] 8011252: 4619 mov r1, r3 8011254: 6878 ldr r0, [r7, #4] 8011256: f001 fd41 bl 8012cdc else { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, (uint8_t *)req, 0U); } break; 801125a: e090 b.n 801137e hcdc->CmdOpCode = req->bRequest; 801125c: 683b ldr r3, [r7, #0] 801125e: 785a ldrb r2, [r3, #1] 8011260: 693b ldr r3, [r7, #16] 8011262: f883 2200 strb.w r2, [r3, #512] @ 0x200 hcdc->CmdLength = (uint8_t)MIN(req->wLength, USB_MAX_EP0_SIZE); 8011266: 683b ldr r3, [r7, #0] 8011268: 88db ldrh r3, [r3, #6] 801126a: 2b3f cmp r3, #63 @ 0x3f 801126c: d803 bhi.n 8011276 801126e: 683b ldr r3, [r7, #0] 8011270: 88db ldrh r3, [r3, #6] 8011272: b2da uxtb r2, r3 8011274: e000 b.n 8011278 8011276: 2240 movs r2, #64 @ 0x40 8011278: 693b ldr r3, [r7, #16] 801127a: f883 2201 strb.w r2, [r3, #513] @ 0x201 (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, hcdc->CmdLength); 801127e: 6939 ldr r1, [r7, #16] 8011280: 693b ldr r3, [r7, #16] 8011282: f893 3201 ldrb.w r3, [r3, #513] @ 0x201 8011286: 461a mov r2, r3 8011288: 6878 ldr r0, [r7, #4] 801128a: f001 fd56 bl 8012d3a break; 801128e: e076 b.n 801137e ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, 8011290: 687b ldr r3, [r7, #4] 8011292: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8011296: 687a ldr r2, [r7, #4] 8011298: 33b0 adds r3, #176 @ 0xb0 801129a: 009b lsls r3, r3, #2 801129c: 4413 add r3, r2 801129e: 685b ldr r3, [r3, #4] 80112a0: 689b ldr r3, [r3, #8] 80112a2: 683a ldr r2, [r7, #0] 80112a4: 7850 ldrb r0, [r2, #1] 80112a6: 2200 movs r2, #0 80112a8: 6839 ldr r1, [r7, #0] 80112aa: 4798 blx r3 break; 80112ac: e067 b.n 801137e case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80112ae: 683b ldr r3, [r7, #0] 80112b0: 785b ldrb r3, [r3, #1] 80112b2: 2b0b cmp r3, #11 80112b4: d851 bhi.n 801135a 80112b6: a201 add r2, pc, #4 @ (adr r2, 80112bc ) 80112b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80112bc: 080112ed .word 0x080112ed 80112c0: 08011369 .word 0x08011369 80112c4: 0801135b .word 0x0801135b 80112c8: 0801135b .word 0x0801135b 80112cc: 0801135b .word 0x0801135b 80112d0: 0801135b .word 0x0801135b 80112d4: 0801135b .word 0x0801135b 80112d8: 0801135b .word 0x0801135b 80112dc: 0801135b .word 0x0801135b 80112e0: 0801135b .word 0x0801135b 80112e4: 08011317 .word 0x08011317 80112e8: 08011341 .word 0x08011341 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 80112ec: 687b ldr r3, [r7, #4] 80112ee: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80112f2: b2db uxtb r3, r3 80112f4: 2b03 cmp r3, #3 80112f6: d107 bne.n 8011308 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 80112f8: f107 030a add.w r3, r7, #10 80112fc: 2202 movs r2, #2 80112fe: 4619 mov r1, r3 8011300: 6878 ldr r0, [r7, #4] 8011302: f001 fceb bl 8012cdc else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8011306: e032 b.n 801136e USBD_CtlError(pdev, req); 8011308: 6839 ldr r1, [r7, #0] 801130a: 6878 ldr r0, [r7, #4] 801130c: f001 fc69 bl 8012be2 ret = USBD_FAIL; 8011310: 2303 movs r3, #3 8011312: 75fb strb r3, [r7, #23] break; 8011314: e02b b.n 801136e case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011316: 687b ldr r3, [r7, #4] 8011318: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 801131c: b2db uxtb r3, r3 801131e: 2b03 cmp r3, #3 8011320: d107 bne.n 8011332 { (void)USBD_CtlSendData(pdev, &ifalt, 1U); 8011322: f107 030d add.w r3, r7, #13 8011326: 2201 movs r2, #1 8011328: 4619 mov r1, r3 801132a: 6878 ldr r0, [r7, #4] 801132c: f001 fcd6 bl 8012cdc else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8011330: e01d b.n 801136e USBD_CtlError(pdev, req); 8011332: 6839 ldr r1, [r7, #0] 8011334: 6878 ldr r0, [r7, #4] 8011336: f001 fc54 bl 8012be2 ret = USBD_FAIL; 801133a: 2303 movs r3, #3 801133c: 75fb strb r3, [r7, #23] break; 801133e: e016 b.n 801136e case USB_REQ_SET_INTERFACE: if (pdev->dev_state != USBD_STATE_CONFIGURED) 8011340: 687b ldr r3, [r7, #4] 8011342: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011346: b2db uxtb r3, r3 8011348: 2b03 cmp r3, #3 801134a: d00f beq.n 801136c { USBD_CtlError(pdev, req); 801134c: 6839 ldr r1, [r7, #0] 801134e: 6878 ldr r0, [r7, #4] 8011350: f001 fc47 bl 8012be2 ret = USBD_FAIL; 8011354: 2303 movs r3, #3 8011356: 75fb strb r3, [r7, #23] } break; 8011358: e008 b.n 801136c case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 801135a: 6839 ldr r1, [r7, #0] 801135c: 6878 ldr r0, [r7, #4] 801135e: f001 fc40 bl 8012be2 ret = USBD_FAIL; 8011362: 2303 movs r3, #3 8011364: 75fb strb r3, [r7, #23] break; 8011366: e002 b.n 801136e break; 8011368: bf00 nop 801136a: e008 b.n 801137e break; 801136c: bf00 nop } break; 801136e: e006 b.n 801137e default: USBD_CtlError(pdev, req); 8011370: 6839 ldr r1, [r7, #0] 8011372: 6878 ldr r0, [r7, #4] 8011374: f001 fc35 bl 8012be2 ret = USBD_FAIL; 8011378: 2303 movs r3, #3 801137a: 75fb strb r3, [r7, #23] break; 801137c: bf00 nop } return (uint8_t)ret; 801137e: 7dfb ldrb r3, [r7, #23] } 8011380: 4618 mov r0, r3 8011382: 3718 adds r7, #24 8011384: 46bd mov sp, r7 8011386: bd80 pop {r7, pc} 08011388 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8011388: b580 push {r7, lr} 801138a: b084 sub sp, #16 801138c: af00 add r7, sp, #0 801138e: 6078 str r0, [r7, #4] 8011390: 460b mov r3, r1 8011392: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc; PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef *)pdev->pData; 8011394: 687b ldr r3, [r7, #4] 8011396: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 801139a: 60fb str r3, [r7, #12] if (pdev->pClassDataCmsit[pdev->classId] == NULL) 801139c: 687b ldr r3, [r7, #4] 801139e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80113a2: 687b ldr r3, [r7, #4] 80113a4: 32b0 adds r2, #176 @ 0xb0 80113a6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80113aa: 2b00 cmp r3, #0 80113ac: d101 bne.n 80113b2 { return (uint8_t)USBD_FAIL; 80113ae: 2303 movs r3, #3 80113b0: e065 b.n 801147e } hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80113b2: 687b ldr r3, [r7, #4] 80113b4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80113b8: 687b ldr r3, [r7, #4] 80113ba: 32b0 adds r2, #176 @ 0xb0 80113bc: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80113c0: 60bb str r3, [r7, #8] if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) && 80113c2: 78fb ldrb r3, [r7, #3] 80113c4: f003 020f and.w r2, r3, #15 80113c8: 6879 ldr r1, [r7, #4] 80113ca: 4613 mov r3, r2 80113cc: 009b lsls r3, r3, #2 80113ce: 4413 add r3, r2 80113d0: 009b lsls r3, r3, #2 80113d2: 440b add r3, r1 80113d4: 3314 adds r3, #20 80113d6: 681b ldr r3, [r3, #0] 80113d8: 2b00 cmp r3, #0 80113da: d02f beq.n 801143c ((pdev->ep_in[epnum & 0xFU].total_length % hpcd->IN_ep[epnum & 0xFU].maxpacket) == 0U)) 80113dc: 78fb ldrb r3, [r7, #3] 80113de: f003 020f and.w r2, r3, #15 80113e2: 6879 ldr r1, [r7, #4] 80113e4: 4613 mov r3, r2 80113e6: 009b lsls r3, r3, #2 80113e8: 4413 add r3, r2 80113ea: 009b lsls r3, r3, #2 80113ec: 440b add r3, r1 80113ee: 3314 adds r3, #20 80113f0: 681a ldr r2, [r3, #0] 80113f2: 78fb ldrb r3, [r7, #3] 80113f4: f003 010f and.w r1, r3, #15 80113f8: 68f8 ldr r0, [r7, #12] 80113fa: 460b mov r3, r1 80113fc: 009b lsls r3, r3, #2 80113fe: 440b add r3, r1 8011400: 00db lsls r3, r3, #3 8011402: 4403 add r3, r0 8011404: 3320 adds r3, #32 8011406: 681b ldr r3, [r3, #0] 8011408: fbb2 f1f3 udiv r1, r2, r3 801140c: fb01 f303 mul.w r3, r1, r3 8011410: 1ad3 subs r3, r2, r3 if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) && 8011412: 2b00 cmp r3, #0 8011414: d112 bne.n 801143c { /* Update the packet total length */ pdev->ep_in[epnum & 0xFU].total_length = 0U; 8011416: 78fb ldrb r3, [r7, #3] 8011418: f003 020f and.w r2, r3, #15 801141c: 6879 ldr r1, [r7, #4] 801141e: 4613 mov r3, r2 8011420: 009b lsls r3, r3, #2 8011422: 4413 add r3, r2 8011424: 009b lsls r3, r3, #2 8011426: 440b add r3, r1 8011428: 3314 adds r3, #20 801142a: 2200 movs r2, #0 801142c: 601a str r2, [r3, #0] /* Send ZLP */ (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); 801142e: 78f9 ldrb r1, [r7, #3] 8011430: 2300 movs r3, #0 8011432: 2200 movs r2, #0 8011434: 6878 ldr r0, [r7, #4] 8011436: f007 fe9a bl 801916e 801143a: e01f b.n 801147c } else { hcdc->TxState = 0U; 801143c: 68bb ldr r3, [r7, #8] 801143e: 2200 movs r2, #0 8011440: f8c3 2214 str.w r2, [r3, #532] @ 0x214 if (((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt != NULL) 8011444: 687b ldr r3, [r7, #4] 8011446: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 801144a: 687a ldr r2, [r7, #4] 801144c: 33b0 adds r3, #176 @ 0xb0 801144e: 009b lsls r3, r3, #2 8011450: 4413 add r3, r2 8011452: 685b ldr r3, [r3, #4] 8011454: 691b ldr r3, [r3, #16] 8011456: 2b00 cmp r3, #0 8011458: d010 beq.n 801147c { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); 801145a: 687b ldr r3, [r7, #4] 801145c: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 8011460: 687a ldr r2, [r7, #4] 8011462: 33b0 adds r3, #176 @ 0xb0 8011464: 009b lsls r3, r3, #2 8011466: 4413 add r3, r2 8011468: 685b ldr r3, [r3, #4] 801146a: 691b ldr r3, [r3, #16] 801146c: 68ba ldr r2, [r7, #8] 801146e: f8d2 0208 ldr.w r0, [r2, #520] @ 0x208 8011472: 68ba ldr r2, [r7, #8] 8011474: f502 7104 add.w r1, r2, #528 @ 0x210 8011478: 78fa ldrb r2, [r7, #3] 801147a: 4798 blx r3 } } return (uint8_t)USBD_OK; 801147c: 2300 movs r3, #0 } 801147e: 4618 mov r0, r3 8011480: 3710 adds r7, #16 8011482: 46bd mov sp, r7 8011484: bd80 pop {r7, pc} 08011486 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8011486: b580 push {r7, lr} 8011488: b084 sub sp, #16 801148a: af00 add r7, sp, #0 801148c: 6078 str r0, [r7, #4] 801148e: 460b mov r3, r1 8011490: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8011492: 687b ldr r3, [r7, #4] 8011494: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8011498: 687b ldr r3, [r7, #4] 801149a: 32b0 adds r2, #176 @ 0xb0 801149c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80114a0: 60fb str r3, [r7, #12] if (pdev->pClassDataCmsit[pdev->classId] == NULL) 80114a2: 687b ldr r3, [r7, #4] 80114a4: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 80114a8: 687b ldr r3, [r7, #4] 80114aa: 32b0 adds r2, #176 @ 0xb0 80114ac: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80114b0: 2b00 cmp r3, #0 80114b2: d101 bne.n 80114b8 { return (uint8_t)USBD_FAIL; 80114b4: 2303 movs r3, #3 80114b6: e01a b.n 80114ee } /* Get the received data length */ hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); 80114b8: 78fb ldrb r3, [r7, #3] 80114ba: 4619 mov r1, r3 80114bc: 6878 ldr r0, [r7, #4] 80114be: f007 fe98 bl 80191f2 80114c2: 4602 mov r2, r0 80114c4: 68fb ldr r3, [r7, #12] 80114c6: f8c3 220c str.w r2, [r3, #524] @ 0x20c /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Receive(hcdc->RxBuffer, &hcdc->RxLength); 80114ca: 687b ldr r3, [r7, #4] 80114cc: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 80114d0: 687a ldr r2, [r7, #4] 80114d2: 33b0 adds r3, #176 @ 0xb0 80114d4: 009b lsls r3, r3, #2 80114d6: 4413 add r3, r2 80114d8: 685b ldr r3, [r3, #4] 80114da: 68db ldr r3, [r3, #12] 80114dc: 68fa ldr r2, [r7, #12] 80114de: f8d2 0204 ldr.w r0, [r2, #516] @ 0x204 80114e2: 68fa ldr r2, [r7, #12] 80114e4: f502 7203 add.w r2, r2, #524 @ 0x20c 80114e8: 4611 mov r1, r2 80114ea: 4798 blx r3 return (uint8_t)USBD_OK; 80114ec: 2300 movs r3, #0 } 80114ee: 4618 mov r0, r3 80114f0: 3710 adds r7, #16 80114f2: 46bd mov sp, r7 80114f4: bd80 pop {r7, pc} 080114f6 : * Handle EP0 Rx Ready event * @param pdev: device instance * @retval status */ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) { 80114f6: b580 push {r7, lr} 80114f8: b084 sub sp, #16 80114fa: af00 add r7, sp, #0 80114fc: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 80114fe: 687b ldr r3, [r7, #4] 8011500: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8011504: 687b ldr r3, [r7, #4] 8011506: 32b0 adds r2, #176 @ 0xb0 8011508: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801150c: 60fb str r3, [r7, #12] if (hcdc == NULL) 801150e: 68fb ldr r3, [r7, #12] 8011510: 2b00 cmp r3, #0 8011512: d101 bne.n 8011518 { return (uint8_t)USBD_FAIL; 8011514: 2303 movs r3, #3 8011516: e024 b.n 8011562 } if ((pdev->pUserData[pdev->classId] != NULL) && (hcdc->CmdOpCode != 0xFFU)) 8011518: 687b ldr r3, [r7, #4] 801151a: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 801151e: 687a ldr r2, [r7, #4] 8011520: 33b0 adds r3, #176 @ 0xb0 8011522: 009b lsls r3, r3, #2 8011524: 4413 add r3, r2 8011526: 685b ldr r3, [r3, #4] 8011528: 2b00 cmp r3, #0 801152a: d019 beq.n 8011560 801152c: 68fb ldr r3, [r7, #12] 801152e: f893 3200 ldrb.w r3, [r3, #512] @ 0x200 8011532: 2bff cmp r3, #255 @ 0xff 8011534: d014 beq.n 8011560 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode, 8011536: 687b ldr r3, [r7, #4] 8011538: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 801153c: 687a ldr r2, [r7, #4] 801153e: 33b0 adds r3, #176 @ 0xb0 8011540: 009b lsls r3, r3, #2 8011542: 4413 add r3, r2 8011544: 685b ldr r3, [r3, #4] 8011546: 689b ldr r3, [r3, #8] 8011548: 68fa ldr r2, [r7, #12] 801154a: f892 0200 ldrb.w r0, [r2, #512] @ 0x200 (uint8_t *)hcdc->data, 801154e: 68f9 ldr r1, [r7, #12] (uint16_t)hcdc->CmdLength); 8011550: 68fa ldr r2, [r7, #12] 8011552: f892 2201 ldrb.w r2, [r2, #513] @ 0x201 ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode, 8011556: 4798 blx r3 hcdc->CmdOpCode = 0xFFU; 8011558: 68fb ldr r3, [r7, #12] 801155a: 22ff movs r2, #255 @ 0xff 801155c: f883 2200 strb.w r2, [r3, #512] @ 0x200 } return (uint8_t)USBD_OK; 8011560: 2300 movs r3, #0 } 8011562: 4618 mov r0, r3 8011564: 3710 adds r7, #16 8011566: 46bd mov sp, r7 8011568: bd80 pop {r7, pc} ... 0801156c : * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) { 801156c: b580 push {r7, lr} 801156e: b086 sub sp, #24 8011570: af00 add r7, sp, #0 8011572: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); 8011574: 2182 movs r1, #130 @ 0x82 8011576: 4818 ldr r0, [pc, #96] @ (80115d8 ) 8011578: f000 fcd0 bl 8011f1c 801157c: 6178 str r0, [r7, #20] USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); 801157e: 2101 movs r1, #1 8011580: 4815 ldr r0, [pc, #84] @ (80115d8 ) 8011582: f000 fccb bl 8011f1c 8011586: 6138 str r0, [r7, #16] USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); 8011588: 2181 movs r1, #129 @ 0x81 801158a: 4813 ldr r0, [pc, #76] @ (80115d8 ) 801158c: f000 fcc6 bl 8011f1c 8011590: 60f8 str r0, [r7, #12] if (pEpCmdDesc != NULL) 8011592: 697b ldr r3, [r7, #20] 8011594: 2b00 cmp r3, #0 8011596: d002 beq.n 801159e { pEpCmdDesc->bInterval = CDC_FS_BINTERVAL; 8011598: 697b ldr r3, [r7, #20] 801159a: 2210 movs r2, #16 801159c: 719a strb r2, [r3, #6] } if (pEpOutDesc != NULL) 801159e: 693b ldr r3, [r7, #16] 80115a0: 2b00 cmp r3, #0 80115a2: d006 beq.n 80115b2 { pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; 80115a4: 693b ldr r3, [r7, #16] 80115a6: 2200 movs r2, #0 80115a8: f042 0240 orr.w r2, r2, #64 @ 0x40 80115ac: 711a strb r2, [r3, #4] 80115ae: 2200 movs r2, #0 80115b0: 715a strb r2, [r3, #5] } if (pEpInDesc != NULL) 80115b2: 68fb ldr r3, [r7, #12] 80115b4: 2b00 cmp r3, #0 80115b6: d006 beq.n 80115c6 { pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; 80115b8: 68fb ldr r3, [r7, #12] 80115ba: 2200 movs r2, #0 80115bc: f042 0240 orr.w r2, r2, #64 @ 0x40 80115c0: 711a strb r2, [r3, #4] 80115c2: 2200 movs r2, #0 80115c4: 715a strb r2, [r3, #5] } *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); 80115c6: 687b ldr r3, [r7, #4] 80115c8: 2243 movs r2, #67 @ 0x43 80115ca: 801a strh r2, [r3, #0] return USBD_CDC_CfgDesc; 80115cc: 4b02 ldr r3, [pc, #8] @ (80115d8 ) } 80115ce: 4618 mov r0, r3 80115d0: 3718 adds r7, #24 80115d2: 46bd mov sp, r7 80115d4: bd80 pop {r7, pc} 80115d6: bf00 nop 80115d8: 2000005c .word 0x2000005c 080115dc : * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) { 80115dc: b580 push {r7, lr} 80115de: b086 sub sp, #24 80115e0: af00 add r7, sp, #0 80115e2: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); 80115e4: 2182 movs r1, #130 @ 0x82 80115e6: 4818 ldr r0, [pc, #96] @ (8011648 ) 80115e8: f000 fc98 bl 8011f1c 80115ec: 6178 str r0, [r7, #20] USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); 80115ee: 2101 movs r1, #1 80115f0: 4815 ldr r0, [pc, #84] @ (8011648 ) 80115f2: f000 fc93 bl 8011f1c 80115f6: 6138 str r0, [r7, #16] USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); 80115f8: 2181 movs r1, #129 @ 0x81 80115fa: 4813 ldr r0, [pc, #76] @ (8011648 ) 80115fc: f000 fc8e bl 8011f1c 8011600: 60f8 str r0, [r7, #12] if (pEpCmdDesc != NULL) 8011602: 697b ldr r3, [r7, #20] 8011604: 2b00 cmp r3, #0 8011606: d002 beq.n 801160e { pEpCmdDesc->bInterval = CDC_HS_BINTERVAL; 8011608: 697b ldr r3, [r7, #20] 801160a: 2210 movs r2, #16 801160c: 719a strb r2, [r3, #6] } if (pEpOutDesc != NULL) 801160e: 693b ldr r3, [r7, #16] 8011610: 2b00 cmp r3, #0 8011612: d006 beq.n 8011622 { pEpOutDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE; 8011614: 693b ldr r3, [r7, #16] 8011616: 2200 movs r2, #0 8011618: 711a strb r2, [r3, #4] 801161a: 2200 movs r2, #0 801161c: f042 0202 orr.w r2, r2, #2 8011620: 715a strb r2, [r3, #5] } if (pEpInDesc != NULL) 8011622: 68fb ldr r3, [r7, #12] 8011624: 2b00 cmp r3, #0 8011626: d006 beq.n 8011636 { pEpInDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE; 8011628: 68fb ldr r3, [r7, #12] 801162a: 2200 movs r2, #0 801162c: 711a strb r2, [r3, #4] 801162e: 2200 movs r2, #0 8011630: f042 0202 orr.w r2, r2, #2 8011634: 715a strb r2, [r3, #5] } *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); 8011636: 687b ldr r3, [r7, #4] 8011638: 2243 movs r2, #67 @ 0x43 801163a: 801a strh r2, [r3, #0] return USBD_CDC_CfgDesc; 801163c: 4b02 ldr r3, [pc, #8] @ (8011648 ) } 801163e: 4618 mov r0, r3 8011640: 3718 adds r7, #24 8011642: 46bd mov sp, r7 8011644: bd80 pop {r7, pc} 8011646: bf00 nop 8011648: 2000005c .word 0x2000005c 0801164c : * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) { 801164c: b580 push {r7, lr} 801164e: b086 sub sp, #24 8011650: af00 add r7, sp, #0 8011652: 6078 str r0, [r7, #4] USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); 8011654: 2182 movs r1, #130 @ 0x82 8011656: 4818 ldr r0, [pc, #96] @ (80116b8 ) 8011658: f000 fc60 bl 8011f1c 801165c: 6178 str r0, [r7, #20] USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); 801165e: 2101 movs r1, #1 8011660: 4815 ldr r0, [pc, #84] @ (80116b8 ) 8011662: f000 fc5b bl 8011f1c 8011666: 6138 str r0, [r7, #16] USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); 8011668: 2181 movs r1, #129 @ 0x81 801166a: 4813 ldr r0, [pc, #76] @ (80116b8 ) 801166c: f000 fc56 bl 8011f1c 8011670: 60f8 str r0, [r7, #12] if (pEpCmdDesc != NULL) 8011672: 697b ldr r3, [r7, #20] 8011674: 2b00 cmp r3, #0 8011676: d002 beq.n 801167e { pEpCmdDesc->bInterval = CDC_FS_BINTERVAL; 8011678: 697b ldr r3, [r7, #20] 801167a: 2210 movs r2, #16 801167c: 719a strb r2, [r3, #6] } if (pEpOutDesc != NULL) 801167e: 693b ldr r3, [r7, #16] 8011680: 2b00 cmp r3, #0 8011682: d006 beq.n 8011692 { pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; 8011684: 693b ldr r3, [r7, #16] 8011686: 2200 movs r2, #0 8011688: f042 0240 orr.w r2, r2, #64 @ 0x40 801168c: 711a strb r2, [r3, #4] 801168e: 2200 movs r2, #0 8011690: 715a strb r2, [r3, #5] } if (pEpInDesc != NULL) 8011692: 68fb ldr r3, [r7, #12] 8011694: 2b00 cmp r3, #0 8011696: d006 beq.n 80116a6 { pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; 8011698: 68fb ldr r3, [r7, #12] 801169a: 2200 movs r2, #0 801169c: f042 0240 orr.w r2, r2, #64 @ 0x40 80116a0: 711a strb r2, [r3, #4] 80116a2: 2200 movs r2, #0 80116a4: 715a strb r2, [r3, #5] } *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); 80116a6: 687b ldr r3, [r7, #4] 80116a8: 2243 movs r2, #67 @ 0x43 80116aa: 801a strh r2, [r3, #0] return USBD_CDC_CfgDesc; 80116ac: 4b02 ldr r3, [pc, #8] @ (80116b8 ) } 80116ae: 4618 mov r0, r3 80116b0: 3718 adds r7, #24 80116b2: 46bd mov sp, r7 80116b4: bd80 pop {r7, pc} 80116b6: bf00 nop 80116b8: 2000005c .word 0x2000005c 080116bc : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) { 80116bc: b480 push {r7} 80116be: b083 sub sp, #12 80116c0: af00 add r7, sp, #0 80116c2: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); 80116c4: 687b ldr r3, [r7, #4] 80116c6: 220a movs r2, #10 80116c8: 801a strh r2, [r3, #0] return USBD_CDC_DeviceQualifierDesc; 80116ca: 4b03 ldr r3, [pc, #12] @ (80116d8 ) } 80116cc: 4618 mov r0, r3 80116ce: 370c adds r7, #12 80116d0: 46bd mov sp, r7 80116d2: f85d 7b04 ldr.w r7, [sp], #4 80116d6: 4770 bx lr 80116d8: 20000018 .word 0x20000018 080116dc : * @param fops: CD Interface callback * @retval status */ uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops) { 80116dc: b480 push {r7} 80116de: b083 sub sp, #12 80116e0: af00 add r7, sp, #0 80116e2: 6078 str r0, [r7, #4] 80116e4: 6039 str r1, [r7, #0] if (fops == NULL) 80116e6: 683b ldr r3, [r7, #0] 80116e8: 2b00 cmp r3, #0 80116ea: d101 bne.n 80116f0 { return (uint8_t)USBD_FAIL; 80116ec: 2303 movs r3, #3 80116ee: e009 b.n 8011704 } pdev->pUserData[pdev->classId] = fops; 80116f0: 687b ldr r3, [r7, #4] 80116f2: f8d3 32d4 ldr.w r3, [r3, #724] @ 0x2d4 80116f6: 687a ldr r2, [r7, #4] 80116f8: 33b0 adds r3, #176 @ 0xb0 80116fa: 009b lsls r3, r3, #2 80116fc: 4413 add r3, r2 80116fe: 683a ldr r2, [r7, #0] 8011700: 605a str r2, [r3, #4] return (uint8_t)USBD_OK; 8011702: 2300 movs r3, #0 } 8011704: 4618 mov r0, r3 8011706: 370c adds r7, #12 8011708: 46bd mov sp, r7 801170a: f85d 7b04 ldr.w r7, [sp], #4 801170e: 4770 bx lr 08011710 : { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint32_t length) { 8011710: b480 push {r7} 8011712: b087 sub sp, #28 8011714: af00 add r7, sp, #0 8011716: 60f8 str r0, [r7, #12] 8011718: 60b9 str r1, [r7, #8] 801171a: 607a str r2, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 801171c: 68fb ldr r3, [r7, #12] 801171e: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8011722: 68fb ldr r3, [r7, #12] 8011724: 32b0 adds r2, #176 @ 0xb0 8011726: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801172a: 617b str r3, [r7, #20] #endif /* USE_USBD_COMPOSITE */ if (hcdc == NULL) 801172c: 697b ldr r3, [r7, #20] 801172e: 2b00 cmp r3, #0 8011730: d101 bne.n 8011736 { return (uint8_t)USBD_FAIL; 8011732: 2303 movs r3, #3 8011734: e008 b.n 8011748 } hcdc->TxBuffer = pbuff; 8011736: 697b ldr r3, [r7, #20] 8011738: 68ba ldr r2, [r7, #8] 801173a: f8c3 2208 str.w r2, [r3, #520] @ 0x208 hcdc->TxLength = length; 801173e: 697b ldr r3, [r7, #20] 8011740: 687a ldr r2, [r7, #4] 8011742: f8c3 2210 str.w r2, [r3, #528] @ 0x210 return (uint8_t)USBD_OK; 8011746: 2300 movs r3, #0 } 8011748: 4618 mov r0, r3 801174a: 371c adds r7, #28 801174c: 46bd mov sp, r7 801174e: f85d 7b04 ldr.w r7, [sp], #4 8011752: 4770 bx lr 08011754 : * @param pdev: device instance * @param pbuff: Rx Buffer * @retval status */ uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) { 8011754: b480 push {r7} 8011756: b085 sub sp, #20 8011758: af00 add r7, sp, #0 801175a: 6078 str r0, [r7, #4] 801175c: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 801175e: 687b ldr r3, [r7, #4] 8011760: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8011764: 687b ldr r3, [r7, #4] 8011766: 32b0 adds r2, #176 @ 0xb0 8011768: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801176c: 60fb str r3, [r7, #12] if (hcdc == NULL) 801176e: 68fb ldr r3, [r7, #12] 8011770: 2b00 cmp r3, #0 8011772: d101 bne.n 8011778 { return (uint8_t)USBD_FAIL; 8011774: 2303 movs r3, #3 8011776: e004 b.n 8011782 } hcdc->RxBuffer = pbuff; 8011778: 68fb ldr r3, [r7, #12] 801177a: 683a ldr r2, [r7, #0] 801177c: f8c3 2204 str.w r2, [r3, #516] @ 0x204 return (uint8_t)USBD_OK; 8011780: 2300 movs r3, #0 } 8011782: 4618 mov r0, r3 8011784: 3714 adds r7, #20 8011786: 46bd mov sp, r7 8011788: f85d 7b04 ldr.w r7, [sp], #4 801178c: 4770 bx lr ... 08011790 : uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t ClassId) { USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; #else uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) { 8011790: b580 push {r7, lr} 8011792: b084 sub sp, #16 8011794: af00 add r7, sp, #0 8011796: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8011798: 687b ldr r3, [r7, #4] 801179a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 801179e: 687b ldr r3, [r7, #4] 80117a0: 32b0 adds r2, #176 @ 0xb0 80117a2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80117a6: 60bb str r3, [r7, #8] #endif /* USE_USBD_COMPOSITE */ USBD_StatusTypeDef ret = USBD_BUSY; 80117a8: 2301 movs r3, #1 80117aa: 73fb strb r3, [r7, #15] #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, ClassId); #endif /* USE_USBD_COMPOSITE */ if (hcdc == NULL) 80117ac: 68bb ldr r3, [r7, #8] 80117ae: 2b00 cmp r3, #0 80117b0: d101 bne.n 80117b6 { return (uint8_t)USBD_FAIL; 80117b2: 2303 movs r3, #3 80117b4: e025 b.n 8011802 } if (hcdc->TxState == 0U) 80117b6: 68bb ldr r3, [r7, #8] 80117b8: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214 80117bc: 2b00 cmp r3, #0 80117be: d11f bne.n 8011800 { /* Tx Transfer in progress */ hcdc->TxState = 1U; 80117c0: 68bb ldr r3, [r7, #8] 80117c2: 2201 movs r2, #1 80117c4: f8c3 2214 str.w r2, [r3, #532] @ 0x214 /* Update the packet total length */ pdev->ep_in[CDCInEpAdd & 0xFU].total_length = hcdc->TxLength; 80117c8: 4b10 ldr r3, [pc, #64] @ (801180c ) 80117ca: 781b ldrb r3, [r3, #0] 80117cc: f003 020f and.w r2, r3, #15 80117d0: 68bb ldr r3, [r7, #8] 80117d2: f8d3 1210 ldr.w r1, [r3, #528] @ 0x210 80117d6: 6878 ldr r0, [r7, #4] 80117d8: 4613 mov r3, r2 80117da: 009b lsls r3, r3, #2 80117dc: 4413 add r3, r2 80117de: 009b lsls r3, r3, #2 80117e0: 4403 add r3, r0 80117e2: 3314 adds r3, #20 80117e4: 6019 str r1, [r3, #0] /* Transmit next packet */ (void)USBD_LL_Transmit(pdev, CDCInEpAdd, hcdc->TxBuffer, hcdc->TxLength); 80117e6: 4b09 ldr r3, [pc, #36] @ (801180c ) 80117e8: 7819 ldrb r1, [r3, #0] 80117ea: 68bb ldr r3, [r7, #8] 80117ec: f8d3 2208 ldr.w r2, [r3, #520] @ 0x208 80117f0: 68bb ldr r3, [r7, #8] 80117f2: f8d3 3210 ldr.w r3, [r3, #528] @ 0x210 80117f6: 6878 ldr r0, [r7, #4] 80117f8: f007 fcb9 bl 801916e ret = USBD_OK; 80117fc: 2300 movs r3, #0 80117fe: 73fb strb r3, [r7, #15] } return (uint8_t)ret; 8011800: 7bfb ldrb r3, [r7, #15] } 8011802: 4618 mov r0, r3 8011804: 3710 adds r7, #16 8011806: 46bd mov sp, r7 8011808: bd80 pop {r7, pc} 801180a: bf00 nop 801180c: 2000009f .word 0x2000009f 08011810 : * prepare OUT Endpoint for reception * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { 8011810: b580 push {r7, lr} 8011812: b084 sub sp, #16 8011814: af00 add r7, sp, #0 8011816: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; 8011818: 687b ldr r3, [r7, #4] 801181a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 801181e: 687b ldr r3, [r7, #4] 8011820: 32b0 adds r2, #176 @ 0xb0 8011822: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011826: 60fb str r3, [r7, #12] #ifdef USE_USBD_COMPOSITE /* Get the Endpoints addresses allocated for this class instance */ CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->pClassDataCmsit[pdev->classId] == NULL) 8011828: 687b ldr r3, [r7, #4] 801182a: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 801182e: 687b ldr r3, [r7, #4] 8011830: 32b0 adds r2, #176 @ 0xb0 8011832: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011836: 2b00 cmp r3, #0 8011838: d101 bne.n 801183e { return (uint8_t)USBD_FAIL; 801183a: 2303 movs r3, #3 801183c: e018 b.n 8011870 } if (pdev->dev_speed == USBD_SPEED_HIGH) 801183e: 687b ldr r3, [r7, #4] 8011840: 7c1b ldrb r3, [r3, #16] 8011842: 2b00 cmp r3, #0 8011844: d10a bne.n 801185c { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, 8011846: 4b0c ldr r3, [pc, #48] @ (8011878 ) 8011848: 7819 ldrb r1, [r3, #0] 801184a: 68fb ldr r3, [r7, #12] 801184c: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8011850: f44f 7300 mov.w r3, #512 @ 0x200 8011854: 6878 ldr r0, [r7, #4] 8011856: f007 fcab bl 80191b0 801185a: e008 b.n 801186e CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, 801185c: 4b06 ldr r3, [pc, #24] @ (8011878 ) 801185e: 7819 ldrb r1, [r3, #0] 8011860: 68fb ldr r3, [r7, #12] 8011862: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204 8011866: 2340 movs r3, #64 @ 0x40 8011868: 6878 ldr r0, [r7, #4] 801186a: f007 fca1 bl 80191b0 CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 801186e: 2300 movs r3, #0 } 8011870: 4618 mov r0, r3 8011872: 3710 adds r7, #16 8011874: 46bd mov sp, r7 8011876: bd80 pop {r7, pc} 8011878: 200000a0 .word 0x200000a0 0801187c : * @param id: Low level core index * @retval status: USBD Status */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 801187c: b580 push {r7, lr} 801187e: b086 sub sp, #24 8011880: af00 add r7, sp, #0 8011882: 60f8 str r0, [r7, #12] 8011884: 60b9 str r1, [r7, #8] 8011886: 4613 mov r3, r2 8011888: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 801188a: 68fb ldr r3, [r7, #12] 801188c: 2b00 cmp r3, #0 801188e: d101 bne.n 8011894 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 8011890: 2303 movs r3, #3 8011892: e01f b.n 80118d4 pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; 8011894: 68fb ldr r3, [r7, #12] 8011896: 2200 movs r2, #0 8011898: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 pdev->pUserData[0] = NULL; 801189c: 68fb ldr r3, [r7, #12] 801189e: 2200 movs r2, #0 80118a0: f8c3 22c4 str.w r2, [r3, #708] @ 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; 80118a4: 68fb ldr r3, [r7, #12] 80118a6: 2200 movs r2, #0 80118a8: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) 80118ac: 68bb ldr r3, [r7, #8] 80118ae: 2b00 cmp r3, #0 80118b0: d003 beq.n 80118ba { pdev->pDesc = pdesc; 80118b2: 68fb ldr r3, [r7, #12] 80118b4: 68ba ldr r2, [r7, #8] 80118b6: f8c3 22b4 str.w r2, [r3, #692] @ 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 80118ba: 68fb ldr r3, [r7, #12] 80118bc: 2201 movs r2, #1 80118be: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->id = id; 80118c2: 68fb ldr r3, [r7, #12] 80118c4: 79fa ldrb r2, [r7, #7] 80118c6: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 80118c8: 68f8 ldr r0, [r7, #12] 80118ca: f007 fb05 bl 8018ed8 80118ce: 4603 mov r3, r0 80118d0: 75fb strb r3, [r7, #23] return ret; 80118d2: 7dfb ldrb r3, [r7, #23] } 80118d4: 4618 mov r0, r3 80118d6: 3718 adds r7, #24 80118d8: 46bd mov sp, r7 80118da: bd80 pop {r7, pc} 080118dc : * @param pdev: Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 80118dc: b580 push {r7, lr} 80118de: b084 sub sp, #16 80118e0: af00 add r7, sp, #0 80118e2: 6078 str r0, [r7, #4] 80118e4: 6039 str r1, [r7, #0] uint16_t len = 0U; 80118e6: 2300 movs r3, #0 80118e8: 81fb strh r3, [r7, #14] if (pclass == NULL) 80118ea: 683b ldr r3, [r7, #0] 80118ec: 2b00 cmp r3, #0 80118ee: d101 bne.n 80118f4 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; 80118f0: 2303 movs r3, #3 80118f2: e025 b.n 8011940 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; 80118f4: 687b ldr r3, [r7, #4] 80118f6: 683a ldr r2, [r7, #0] 80118f8: f8c3 22b8 str.w r2, [r3, #696] @ 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) 80118fc: 687b ldr r3, [r7, #4] 80118fe: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8011902: 687b ldr r3, [r7, #4] 8011904: 32ae adds r2, #174 @ 0xae 8011906: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801190a: 6adb ldr r3, [r3, #44] @ 0x2c 801190c: 2b00 cmp r3, #0 801190e: d00f beq.n 8011930 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); 8011910: 687b ldr r3, [r7, #4] 8011912: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8011916: 687b ldr r3, [r7, #4] 8011918: 32ae adds r2, #174 @ 0xae 801191a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801191e: 6adb ldr r3, [r3, #44] @ 0x2c 8011920: f107 020e add.w r2, r7, #14 8011924: 4610 mov r0, r2 8011926: 4798 blx r3 8011928: 4602 mov r2, r0 801192a: 687b ldr r3, [r7, #4] 801192c: f8c3 22d0 str.w r2, [r3, #720] @ 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses++; 8011930: 687b ldr r3, [r7, #4] 8011932: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8011936: 1c5a adds r2, r3, #1 8011938: 687b ldr r3, [r7, #4] 801193a: f8c3 22d8 str.w r2, [r3, #728] @ 0x2d8 return USBD_OK; 801193e: 2300 movs r3, #0 } 8011940: 4618 mov r0, r3 8011942: 3710 adds r7, #16 8011944: 46bd mov sp, r7 8011946: bd80 pop {r7, pc} 08011948 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 8011948: b580 push {r7, lr} 801194a: b082 sub sp, #8 801194c: af00 add r7, sp, #0 801194e: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); 8011950: 6878 ldr r0, [r7, #4] 8011952: f007 fb23 bl 8018f9c 8011956: 4603 mov r3, r0 } 8011958: 4618 mov r0, r3 801195a: 3708 adds r7, #8 801195c: 46bd mov sp, r7 801195e: bd80 pop {r7, pc} 08011960 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 8011960: b480 push {r7} 8011962: b083 sub sp, #12 8011964: af00 add r7, sp, #0 8011966: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 8011968: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } 801196a: 4618 mov r0, r3 801196c: 370c adds r7, #12 801196e: 46bd mov sp, r7 8011970: f85d 7b04 ldr.w r7, [sp], #4 8011974: 4770 bx lr 08011976 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8011976: b580 push {r7, lr} 8011978: b084 sub sp, #16 801197a: af00 add r7, sp, #0 801197c: 6078 str r0, [r7, #4] 801197e: 460b mov r3, r1 8011980: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 8011982: 2300 movs r3, #0 8011984: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) 8011986: 687b ldr r3, [r7, #4] 8011988: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 801198c: 2b00 cmp r3, #0 801198e: d009 beq.n 80119a4 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); 8011990: 687b ldr r3, [r7, #4] 8011992: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011996: 681b ldr r3, [r3, #0] 8011998: 78fa ldrb r2, [r7, #3] 801199a: 4611 mov r1, r2 801199c: 6878 ldr r0, [r7, #4] 801199e: 4798 blx r3 80119a0: 4603 mov r3, r0 80119a2: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 80119a4: 7bfb ldrb r3, [r7, #15] } 80119a6: 4618 mov r0, r3 80119a8: 3710 adds r7, #16 80119aa: 46bd mov sp, r7 80119ac: bd80 pop {r7, pc} 080119ae : * @param pdev: device instance * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80119ae: b580 push {r7, lr} 80119b0: b084 sub sp, #16 80119b2: af00 add r7, sp, #0 80119b4: 6078 str r0, [r7, #4] 80119b6: 460b mov r3, r1 80119b8: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; 80119ba: 2300 movs r3, #0 80119bc: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) 80119be: 687b ldr r3, [r7, #4] 80119c0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80119c4: 685b ldr r3, [r3, #4] 80119c6: 78fa ldrb r2, [r7, #3] 80119c8: 4611 mov r1, r2 80119ca: 6878 ldr r0, [r7, #4] 80119cc: 4798 blx r3 80119ce: 4603 mov r3, r0 80119d0: 2b00 cmp r3, #0 80119d2: d001 beq.n 80119d8 { ret = USBD_FAIL; 80119d4: 2303 movs r3, #3 80119d6: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; 80119d8: 7bfb ldrb r3, [r7, #15] } 80119da: 4618 mov r0, r3 80119dc: 3710 adds r7, #16 80119de: 46bd mov sp, r7 80119e0: bd80 pop {r7, pc} 080119e2 : * @param pdev: device instance * @param psetup: setup packet buffer pointer * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 80119e2: b580 push {r7, lr} 80119e4: b084 sub sp, #16 80119e6: af00 add r7, sp, #0 80119e8: 6078 str r0, [r7, #4] 80119ea: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 80119ec: 687b ldr r3, [r7, #4] 80119ee: f203 23aa addw r3, r3, #682 @ 0x2aa 80119f2: 6839 ldr r1, [r7, #0] 80119f4: 4618 mov r0, r3 80119f6: f001 f8ba bl 8012b6e pdev->ep0_state = USBD_EP0_SETUP; 80119fa: 687b ldr r3, [r7, #4] 80119fc: 2201 movs r2, #1 80119fe: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep0_data_len = pdev->request.wLength; 8011a02: 687b ldr r3, [r7, #4] 8011a04: f8b3 32b0 ldrh.w r3, [r3, #688] @ 0x2b0 8011a08: 461a mov r2, r3 8011a0a: 687b ldr r3, [r7, #4] 8011a0c: f8c3 2298 str.w r2, [r3, #664] @ 0x298 switch (pdev->request.bmRequest & 0x1FU) 8011a10: 687b ldr r3, [r7, #4] 8011a12: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8011a16: f003 031f and.w r3, r3, #31 8011a1a: 2b02 cmp r3, #2 8011a1c: d01a beq.n 8011a54 8011a1e: 2b02 cmp r3, #2 8011a20: d822 bhi.n 8011a68 8011a22: 2b00 cmp r3, #0 8011a24: d002 beq.n 8011a2c 8011a26: 2b01 cmp r3, #1 8011a28: d00a beq.n 8011a40 8011a2a: e01d b.n 8011a68 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 8011a2c: 687b ldr r3, [r7, #4] 8011a2e: f203 23aa addw r3, r3, #682 @ 0x2aa 8011a32: 4619 mov r1, r3 8011a34: 6878 ldr r0, [r7, #4] 8011a36: f000 fae5 bl 8012004 8011a3a: 4603 mov r3, r0 8011a3c: 73fb strb r3, [r7, #15] break; 8011a3e: e020 b.n 8011a82 case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 8011a40: 687b ldr r3, [r7, #4] 8011a42: f203 23aa addw r3, r3, #682 @ 0x2aa 8011a46: 4619 mov r1, r3 8011a48: 6878 ldr r0, [r7, #4] 8011a4a: f000 fb4d bl 80120e8 8011a4e: 4603 mov r3, r0 8011a50: 73fb strb r3, [r7, #15] break; 8011a52: e016 b.n 8011a82 case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8011a54: 687b ldr r3, [r7, #4] 8011a56: f203 23aa addw r3, r3, #682 @ 0x2aa 8011a5a: 4619 mov r1, r3 8011a5c: 6878 ldr r0, [r7, #4] 8011a5e: f000 fbaf bl 80121c0 8011a62: 4603 mov r3, r0 8011a64: 73fb strb r3, [r7, #15] break; 8011a66: e00c b.n 8011a82 default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 8011a68: 687b ldr r3, [r7, #4] 8011a6a: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8011a6e: f023 037f bic.w r3, r3, #127 @ 0x7f 8011a72: b2db uxtb r3, r3 8011a74: 4619 mov r1, r3 8011a76: 6878 ldr r0, [r7, #4] 8011a78: f007 faf0 bl 801905c 8011a7c: 4603 mov r3, r0 8011a7e: 73fb strb r3, [r7, #15] break; 8011a80: bf00 nop } return ret; 8011a82: 7bfb ldrb r3, [r7, #15] } 8011a84: 4618 mov r0, r3 8011a86: 3710 adds r7, #16 8011a88: 46bd mov sp, r7 8011a8a: bd80 pop {r7, pc} 08011a8c : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8011a8c: b580 push {r7, lr} 8011a8e: b086 sub sp, #24 8011a90: af00 add r7, sp, #0 8011a92: 60f8 str r0, [r7, #12] 8011a94: 460b mov r3, r1 8011a96: 607a str r2, [r7, #4] 8011a98: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; 8011a9a: 2300 movs r3, #0 8011a9c: 75fb strb r3, [r7, #23] uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8011a9e: 7afb ldrb r3, [r7, #11] 8011aa0: 2b00 cmp r3, #0 8011aa2: d177 bne.n 8011b94 { pep = &pdev->ep_out[0]; 8011aa4: 68fb ldr r3, [r7, #12] 8011aa6: f503 73aa add.w r3, r3, #340 @ 0x154 8011aaa: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 8011aac: 68fb ldr r3, [r7, #12] 8011aae: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8011ab2: 2b03 cmp r3, #3 8011ab4: f040 80a1 bne.w 8011bfa { if (pep->rem_length > pep->maxpacket) 8011ab8: 693b ldr r3, [r7, #16] 8011aba: 685b ldr r3, [r3, #4] 8011abc: 693a ldr r2, [r7, #16] 8011abe: 8992 ldrh r2, [r2, #12] 8011ac0: 4293 cmp r3, r2 8011ac2: d91c bls.n 8011afe { pep->rem_length -= pep->maxpacket; 8011ac4: 693b ldr r3, [r7, #16] 8011ac6: 685b ldr r3, [r3, #4] 8011ac8: 693a ldr r2, [r7, #16] 8011aca: 8992 ldrh r2, [r2, #12] 8011acc: 1a9a subs r2, r3, r2 8011ace: 693b ldr r3, [r7, #16] 8011ad0: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8011ad2: 693b ldr r3, [r7, #16] 8011ad4: 691b ldr r3, [r3, #16] 8011ad6: 693a ldr r2, [r7, #16] 8011ad8: 8992 ldrh r2, [r2, #12] 8011ada: 441a add r2, r3 8011adc: 693b ldr r3, [r7, #16] 8011ade: 611a str r2, [r3, #16] (void)USBD_CtlContinueRx(pdev, pep->pbuffer, MAX(pep->rem_length, pep->maxpacket)); 8011ae0: 693b ldr r3, [r7, #16] 8011ae2: 6919 ldr r1, [r3, #16] 8011ae4: 693b ldr r3, [r7, #16] 8011ae6: 899b ldrh r3, [r3, #12] 8011ae8: 461a mov r2, r3 8011aea: 693b ldr r3, [r7, #16] 8011aec: 685b ldr r3, [r3, #4] 8011aee: 4293 cmp r3, r2 8011af0: bf38 it cc 8011af2: 4613 movcc r3, r2 8011af4: 461a mov r2, r3 8011af6: 68f8 ldr r0, [r7, #12] 8011af8: f001 f940 bl 8012d7c 8011afc: e07d b.n 8011bfa } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) 8011afe: 68fb ldr r3, [r7, #12] 8011b00: f893 32aa ldrb.w r3, [r3, #682] @ 0x2aa 8011b04: f003 031f and.w r3, r3, #31 8011b08: 2b02 cmp r3, #2 8011b0a: d014 beq.n 8011b36 8011b0c: 2b02 cmp r3, #2 8011b0e: d81d bhi.n 8011b4c 8011b10: 2b00 cmp r3, #0 8011b12: d002 beq.n 8011b1a 8011b14: 2b01 cmp r3, #1 8011b16: d003 beq.n 8011b20 8011b18: e018 b.n 8011b4c { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; 8011b1a: 2300 movs r3, #0 8011b1c: 75bb strb r3, [r7, #22] break; 8011b1e: e018 b.n 8011b52 case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); 8011b20: 68fb ldr r3, [r7, #12] 8011b22: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8011b26: b2db uxtb r3, r3 8011b28: 4619 mov r1, r3 8011b2a: 68f8 ldr r0, [r7, #12] 8011b2c: f000 f9dc bl 8011ee8 8011b30: 4603 mov r3, r0 8011b32: 75bb strb r3, [r7, #22] break; 8011b34: e00d b.n 8011b52 case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); 8011b36: 68fb ldr r3, [r7, #12] 8011b38: f8b3 32ae ldrh.w r3, [r3, #686] @ 0x2ae 8011b3c: b2db uxtb r3, r3 8011b3e: 4619 mov r1, r3 8011b40: 68f8 ldr r0, [r7, #12] 8011b42: f000 f9de bl 8011f02 8011b46: 4603 mov r3, r0 8011b48: 75bb strb r3, [r7, #22] break; 8011b4a: e002 b.n 8011b52 default: /* Back to the first class in case of doubt */ idx = 0U; 8011b4c: 2300 movs r3, #0 8011b4e: 75bb strb r3, [r7, #22] break; 8011b50: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) 8011b52: 7dbb ldrb r3, [r7, #22] 8011b54: 2b00 cmp r3, #0 8011b56: d119 bne.n 8011b8c { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011b58: 68fb ldr r3, [r7, #12] 8011b5a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011b5e: b2db uxtb r3, r3 8011b60: 2b03 cmp r3, #3 8011b62: d113 bne.n 8011b8c { if (pdev->pClass[idx]->EP0_RxReady != NULL) 8011b64: 7dba ldrb r2, [r7, #22] 8011b66: 68fb ldr r3, [r7, #12] 8011b68: 32ae adds r2, #174 @ 0xae 8011b6a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011b6e: 691b ldr r3, [r3, #16] 8011b70: 2b00 cmp r3, #0 8011b72: d00b beq.n 8011b8c { pdev->classId = idx; 8011b74: 7dba ldrb r2, [r7, #22] 8011b76: 68fb ldr r3, [r7, #12] 8011b78: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); 8011b7c: 7dba ldrb r2, [r7, #22] 8011b7e: 68fb ldr r3, [r7, #12] 8011b80: 32ae adds r2, #174 @ 0xae 8011b82: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011b86: 691b ldr r3, [r3, #16] 8011b88: 68f8 ldr r0, [r7, #12] 8011b8a: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); 8011b8c: 68f8 ldr r0, [r7, #12] 8011b8e: f001 f906 bl 8012d9e 8011b92: e032 b.n 8011bfa } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); 8011b94: 7afb ldrb r3, [r7, #11] 8011b96: f003 037f and.w r3, r3, #127 @ 0x7f 8011b9a: b2db uxtb r3, r3 8011b9c: 4619 mov r1, r3 8011b9e: 68f8 ldr r0, [r7, #12] 8011ba0: f000 f9af bl 8011f02 8011ba4: 4603 mov r3, r0 8011ba6: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8011ba8: 7dbb ldrb r3, [r7, #22] 8011baa: 2bff cmp r3, #255 @ 0xff 8011bac: d025 beq.n 8011bfa 8011bae: 7dbb ldrb r3, [r7, #22] 8011bb0: 2b00 cmp r3, #0 8011bb2: d122 bne.n 8011bfa { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011bb4: 68fb ldr r3, [r7, #12] 8011bb6: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011bba: b2db uxtb r3, r3 8011bbc: 2b03 cmp r3, #3 8011bbe: d117 bne.n 8011bf0 { if (pdev->pClass[idx]->DataOut != NULL) 8011bc0: 7dba ldrb r2, [r7, #22] 8011bc2: 68fb ldr r3, [r7, #12] 8011bc4: 32ae adds r2, #174 @ 0xae 8011bc6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011bca: 699b ldr r3, [r3, #24] 8011bcc: 2b00 cmp r3, #0 8011bce: d00f beq.n 8011bf0 { pdev->classId = idx; 8011bd0: 7dba ldrb r2, [r7, #22] 8011bd2: 68fb ldr r3, [r7, #12] 8011bd4: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); 8011bd8: 7dba ldrb r2, [r7, #22] 8011bda: 68fb ldr r3, [r7, #12] 8011bdc: 32ae adds r2, #174 @ 0xae 8011bde: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011be2: 699b ldr r3, [r3, #24] 8011be4: 7afa ldrb r2, [r7, #11] 8011be6: 4611 mov r1, r2 8011be8: 68f8 ldr r0, [r7, #12] 8011bea: 4798 blx r3 8011bec: 4603 mov r3, r0 8011bee: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) 8011bf0: 7dfb ldrb r3, [r7, #23] 8011bf2: 2b00 cmp r3, #0 8011bf4: d001 beq.n 8011bfa { return ret; 8011bf6: 7dfb ldrb r3, [r7, #23] 8011bf8: e000 b.n 8011bfc } } } return USBD_OK; 8011bfa: 2300 movs r3, #0 } 8011bfc: 4618 mov r0, r3 8011bfe: 3718 adds r7, #24 8011c00: 46bd mov sp, r7 8011c02: bd80 pop {r7, pc} 08011c04 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8011c04: b580 push {r7, lr} 8011c06: b086 sub sp, #24 8011c08: af00 add r7, sp, #0 8011c0a: 60f8 str r0, [r7, #12] 8011c0c: 460b mov r3, r1 8011c0e: 607a str r2, [r7, #4] 8011c10: 72fb strb r3, [r7, #11] USBD_StatusTypeDef ret; uint8_t idx; UNUSED(pdata); if (epnum == 0U) 8011c12: 7afb ldrb r3, [r7, #11] 8011c14: 2b00 cmp r3, #0 8011c16: d178 bne.n 8011d0a { pep = &pdev->ep_in[0]; 8011c18: 68fb ldr r3, [r7, #12] 8011c1a: 3314 adds r3, #20 8011c1c: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 8011c1e: 68fb ldr r3, [r7, #12] 8011c20: f8d3 3294 ldr.w r3, [r3, #660] @ 0x294 8011c24: 2b02 cmp r3, #2 8011c26: d163 bne.n 8011cf0 { if (pep->rem_length > pep->maxpacket) 8011c28: 693b ldr r3, [r7, #16] 8011c2a: 685b ldr r3, [r3, #4] 8011c2c: 693a ldr r2, [r7, #16] 8011c2e: 8992 ldrh r2, [r2, #12] 8011c30: 4293 cmp r3, r2 8011c32: d91c bls.n 8011c6e { pep->rem_length -= pep->maxpacket; 8011c34: 693b ldr r3, [r7, #16] 8011c36: 685b ldr r3, [r3, #4] 8011c38: 693a ldr r2, [r7, #16] 8011c3a: 8992 ldrh r2, [r2, #12] 8011c3c: 1a9a subs r2, r3, r2 8011c3e: 693b ldr r3, [r7, #16] 8011c40: 605a str r2, [r3, #4] pep->pbuffer += pep->maxpacket; 8011c42: 693b ldr r3, [r7, #16] 8011c44: 691b ldr r3, [r3, #16] 8011c46: 693a ldr r2, [r7, #16] 8011c48: 8992 ldrh r2, [r2, #12] 8011c4a: 441a add r2, r3 8011c4c: 693b ldr r3, [r7, #16] 8011c4e: 611a str r2, [r3, #16] (void)USBD_CtlContinueSendData(pdev, pep->pbuffer, pep->rem_length); 8011c50: 693b ldr r3, [r7, #16] 8011c52: 6919 ldr r1, [r3, #16] 8011c54: 693b ldr r3, [r7, #16] 8011c56: 685b ldr r3, [r3, #4] 8011c58: 461a mov r2, r3 8011c5a: 68f8 ldr r0, [r7, #12] 8011c5c: f001 f85c bl 8012d18 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8011c60: 2300 movs r3, #0 8011c62: 2200 movs r2, #0 8011c64: 2100 movs r1, #0 8011c66: 68f8 ldr r0, [r7, #12] 8011c68: f007 faa2 bl 80191b0 8011c6c: e040 b.n 8011cf0 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 8011c6e: 693b ldr r3, [r7, #16] 8011c70: 899b ldrh r3, [r3, #12] 8011c72: 461a mov r2, r3 8011c74: 693b ldr r3, [r7, #16] 8011c76: 685b ldr r3, [r3, #4] 8011c78: 429a cmp r2, r3 8011c7a: d11c bne.n 8011cb6 (pep->total_length >= pep->maxpacket) && 8011c7c: 693b ldr r3, [r7, #16] 8011c7e: 681b ldr r3, [r3, #0] 8011c80: 693a ldr r2, [r7, #16] 8011c82: 8992 ldrh r2, [r2, #12] if ((pep->maxpacket == pep->rem_length) && 8011c84: 4293 cmp r3, r2 8011c86: d316 bcc.n 8011cb6 (pep->total_length < pdev->ep0_data_len)) 8011c88: 693b ldr r3, [r7, #16] 8011c8a: 681a ldr r2, [r3, #0] 8011c8c: 68fb ldr r3, [r7, #12] 8011c8e: f8d3 3298 ldr.w r3, [r3, #664] @ 0x298 (pep->total_length >= pep->maxpacket) && 8011c92: 429a cmp r2, r3 8011c94: d20f bcs.n 8011cb6 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8011c96: 2200 movs r2, #0 8011c98: 2100 movs r1, #0 8011c9a: 68f8 ldr r0, [r7, #12] 8011c9c: f001 f83c bl 8012d18 pdev->ep0_data_len = 0U; 8011ca0: 68fb ldr r3, [r7, #12] 8011ca2: 2200 movs r2, #0 8011ca4: f8c3 2298 str.w r2, [r3, #664] @ 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8011ca8: 2300 movs r3, #0 8011caa: 2200 movs r2, #0 8011cac: 2100 movs r1, #0 8011cae: 68f8 ldr r0, [r7, #12] 8011cb0: f007 fa7e bl 80191b0 8011cb4: e01c b.n 8011cf0 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011cb6: 68fb ldr r3, [r7, #12] 8011cb8: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011cbc: b2db uxtb r3, r3 8011cbe: 2b03 cmp r3, #3 8011cc0: d10f bne.n 8011ce2 { if (pdev->pClass[0]->EP0_TxSent != NULL) 8011cc2: 68fb ldr r3, [r7, #12] 8011cc4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011cc8: 68db ldr r3, [r3, #12] 8011cca: 2b00 cmp r3, #0 8011ccc: d009 beq.n 8011ce2 { pdev->classId = 0U; 8011cce: 68fb ldr r3, [r7, #12] 8011cd0: 2200 movs r2, #0 8011cd2: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); 8011cd6: 68fb ldr r3, [r7, #12] 8011cd8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011cdc: 68db ldr r3, [r3, #12] 8011cde: 68f8 ldr r0, [r7, #12] 8011ce0: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8011ce2: 2180 movs r1, #128 @ 0x80 8011ce4: 68f8 ldr r0, [r7, #12] 8011ce6: f007 f9b9 bl 801905c (void)USBD_CtlReceiveStatus(pdev); 8011cea: 68f8 ldr r0, [r7, #12] 8011cec: f001 f86a bl 8012dc4 } } } if (pdev->dev_test_mode != 0U) 8011cf0: 68fb ldr r3, [r7, #12] 8011cf2: f893 32a0 ldrb.w r3, [r3, #672] @ 0x2a0 8011cf6: 2b00 cmp r3, #0 8011cf8: d03a beq.n 8011d70 { (void)USBD_RunTestMode(pdev); 8011cfa: 68f8 ldr r0, [r7, #12] 8011cfc: f7ff fe30 bl 8011960 pdev->dev_test_mode = 0U; 8011d00: 68fb ldr r3, [r7, #12] 8011d02: 2200 movs r2, #0 8011d04: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 8011d08: e032 b.n 8011d70 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); 8011d0a: 7afb ldrb r3, [r7, #11] 8011d0c: f063 037f orn r3, r3, #127 @ 0x7f 8011d10: b2db uxtb r3, r3 8011d12: 4619 mov r1, r3 8011d14: 68f8 ldr r0, [r7, #12] 8011d16: f000 f8f4 bl 8011f02 8011d1a: 4603 mov r3, r0 8011d1c: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8011d1e: 7dfb ldrb r3, [r7, #23] 8011d20: 2bff cmp r3, #255 @ 0xff 8011d22: d025 beq.n 8011d70 8011d24: 7dfb ldrb r3, [r7, #23] 8011d26: 2b00 cmp r3, #0 8011d28: d122 bne.n 8011d70 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011d2a: 68fb ldr r3, [r7, #12] 8011d2c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011d30: b2db uxtb r3, r3 8011d32: 2b03 cmp r3, #3 8011d34: d11c bne.n 8011d70 { if (pdev->pClass[idx]->DataIn != NULL) 8011d36: 7dfa ldrb r2, [r7, #23] 8011d38: 68fb ldr r3, [r7, #12] 8011d3a: 32ae adds r2, #174 @ 0xae 8011d3c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011d40: 695b ldr r3, [r3, #20] 8011d42: 2b00 cmp r3, #0 8011d44: d014 beq.n 8011d70 { pdev->classId = idx; 8011d46: 7dfa ldrb r2, [r7, #23] 8011d48: 68fb ldr r3, [r7, #12] 8011d4a: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); 8011d4e: 7dfa ldrb r2, [r7, #23] 8011d50: 68fb ldr r3, [r7, #12] 8011d52: 32ae adds r2, #174 @ 0xae 8011d54: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8011d58: 695b ldr r3, [r3, #20] 8011d5a: 7afa ldrb r2, [r7, #11] 8011d5c: 4611 mov r1, r2 8011d5e: 68f8 ldr r0, [r7, #12] 8011d60: 4798 blx r3 8011d62: 4603 mov r3, r0 8011d64: 75bb strb r3, [r7, #22] if (ret != USBD_OK) 8011d66: 7dbb ldrb r3, [r7, #22] 8011d68: 2b00 cmp r3, #0 8011d6a: d001 beq.n 8011d70 { return ret; 8011d6c: 7dbb ldrb r3, [r7, #22] 8011d6e: e000 b.n 8011d72 } } } } return USBD_OK; 8011d70: 2300 movs r3, #0 } 8011d72: 4618 mov r0, r3 8011d74: 3718 adds r7, #24 8011d76: 46bd mov sp, r7 8011d78: bd80 pop {r7, pc} 08011d7a : * Handle Reset event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 8011d7a: b580 push {r7, lr} 8011d7c: b084 sub sp, #16 8011d7e: af00 add r7, sp, #0 8011d80: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; 8011d82: 2300 movs r3, #0 8011d84: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 8011d86: 687b ldr r3, [r7, #4] 8011d88: 2201 movs r2, #1 8011d8a: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->ep0_state = USBD_EP0_IDLE; 8011d8e: 687b ldr r3, [r7, #4] 8011d90: 2200 movs r2, #0 8011d92: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->dev_config = 0U; 8011d96: 687b ldr r3, [r7, #4] 8011d98: 2200 movs r2, #0 8011d9a: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 8011d9c: 687b ldr r3, [r7, #4] 8011d9e: 2200 movs r2, #0 8011da0: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 pdev->dev_test_mode = 0U; 8011da4: 687b ldr r3, [r7, #4] 8011da6: 2200 movs r2, #0 8011da8: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 } } } #else if (pdev->pClass[0] != NULL) 8011dac: 687b ldr r3, [r7, #4] 8011dae: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011db2: 2b00 cmp r3, #0 8011db4: d014 beq.n 8011de0 { if (pdev->pClass[0]->DeInit != NULL) 8011db6: 687b ldr r3, [r7, #4] 8011db8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011dbc: 685b ldr r3, [r3, #4] 8011dbe: 2b00 cmp r3, #0 8011dc0: d00e beq.n 8011de0 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) 8011dc2: 687b ldr r3, [r7, #4] 8011dc4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011dc8: 685b ldr r3, [r3, #4] 8011dca: 687a ldr r2, [r7, #4] 8011dcc: 6852 ldr r2, [r2, #4] 8011dce: b2d2 uxtb r2, r2 8011dd0: 4611 mov r1, r2 8011dd2: 6878 ldr r0, [r7, #4] 8011dd4: 4798 blx r3 8011dd6: 4603 mov r3, r0 8011dd8: 2b00 cmp r3, #0 8011dda: d001 beq.n 8011de0 { ret = USBD_FAIL; 8011ddc: 2303 movs r3, #3 8011dde: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8011de0: 2340 movs r3, #64 @ 0x40 8011de2: 2200 movs r2, #0 8011de4: 2100 movs r1, #0 8011de6: 6878 ldr r0, [r7, #4] 8011de8: f007 f8f3 bl 8018fd2 pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8011dec: 687b ldr r3, [r7, #4] 8011dee: 2201 movs r2, #1 8011df0: f883 2163 strb.w r2, [r3, #355] @ 0x163 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 8011df4: 687b ldr r3, [r7, #4] 8011df6: 2240 movs r2, #64 @ 0x40 8011df8: f8a3 2160 strh.w r2, [r3, #352] @ 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8011dfc: 2340 movs r3, #64 @ 0x40 8011dfe: 2200 movs r2, #0 8011e00: 2180 movs r1, #128 @ 0x80 8011e02: 6878 ldr r0, [r7, #4] 8011e04: f007 f8e5 bl 8018fd2 pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8011e08: 687b ldr r3, [r7, #4] 8011e0a: 2201 movs r2, #1 8011e0c: f883 2023 strb.w r2, [r3, #35] @ 0x23 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8011e10: 687b ldr r3, [r7, #4] 8011e12: 2240 movs r2, #64 @ 0x40 8011e14: 841a strh r2, [r3, #32] return ret; 8011e16: 7bfb ldrb r3, [r7, #15] } 8011e18: 4618 mov r0, r3 8011e1a: 3710 adds r7, #16 8011e1c: 46bd mov sp, r7 8011e1e: bd80 pop {r7, pc} 08011e20 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8011e20: b480 push {r7} 8011e22: b083 sub sp, #12 8011e24: af00 add r7, sp, #0 8011e26: 6078 str r0, [r7, #4] 8011e28: 460b mov r3, r1 8011e2a: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8011e2c: 687b ldr r3, [r7, #4] 8011e2e: 78fa ldrb r2, [r7, #3] 8011e30: 741a strb r2, [r3, #16] return USBD_OK; 8011e32: 2300 movs r3, #0 } 8011e34: 4618 mov r0, r3 8011e36: 370c adds r7, #12 8011e38: 46bd mov sp, r7 8011e3a: f85d 7b04 ldr.w r7, [sp], #4 8011e3e: 4770 bx lr 08011e40 : * Handle Suspend event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8011e40: b480 push {r7} 8011e42: b083 sub sp, #12 8011e44: af00 add r7, sp, #0 8011e46: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) 8011e48: 687b ldr r3, [r7, #4] 8011e4a: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011e4e: b2db uxtb r3, r3 8011e50: 2b04 cmp r3, #4 8011e52: d006 beq.n 8011e62 { pdev->dev_old_state = pdev->dev_state; 8011e54: 687b ldr r3, [r7, #4] 8011e56: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011e5a: b2da uxtb r2, r3 8011e5c: 687b ldr r3, [r7, #4] 8011e5e: f883 229d strb.w r2, [r3, #669] @ 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; 8011e62: 687b ldr r3, [r7, #4] 8011e64: 2204 movs r2, #4 8011e66: f883 229c strb.w r2, [r3, #668] @ 0x29c return USBD_OK; 8011e6a: 2300 movs r3, #0 } 8011e6c: 4618 mov r0, r3 8011e6e: 370c adds r7, #12 8011e70: 46bd mov sp, r7 8011e72: f85d 7b04 ldr.w r7, [sp], #4 8011e76: 4770 bx lr 08011e78 : * Handle Resume event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 8011e78: b480 push {r7} 8011e7a: b083 sub sp, #12 8011e7c: af00 add r7, sp, #0 8011e7e: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 8011e80: 687b ldr r3, [r7, #4] 8011e82: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011e86: b2db uxtb r3, r3 8011e88: 2b04 cmp r3, #4 8011e8a: d106 bne.n 8011e9a { pdev->dev_state = pdev->dev_old_state; 8011e8c: 687b ldr r3, [r7, #4] 8011e8e: f893 329d ldrb.w r3, [r3, #669] @ 0x29d 8011e92: b2da uxtb r2, r3 8011e94: 687b ldr r3, [r7, #4] 8011e96: f883 229c strb.w r2, [r3, #668] @ 0x29c } return USBD_OK; 8011e9a: 2300 movs r3, #0 } 8011e9c: 4618 mov r0, r3 8011e9e: 370c adds r7, #12 8011ea0: 46bd mov sp, r7 8011ea2: f85d 7b04 ldr.w r7, [sp], #4 8011ea6: 4770 bx lr 08011ea8 : * Handle SOF event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 8011ea8: b580 push {r7, lr} 8011eaa: b082 sub sp, #8 8011eac: af00 add r7, sp, #0 8011eae: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) 8011eb0: 687b ldr r3, [r7, #4] 8011eb2: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8011eb6: b2db uxtb r3, r3 8011eb8: 2b03 cmp r3, #3 8011eba: d110 bne.n 8011ede } } } } #else if (pdev->pClass[0] != NULL) 8011ebc: 687b ldr r3, [r7, #4] 8011ebe: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011ec2: 2b00 cmp r3, #0 8011ec4: d00b beq.n 8011ede { if (pdev->pClass[0]->SOF != NULL) 8011ec6: 687b ldr r3, [r7, #4] 8011ec8: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011ecc: 69db ldr r3, [r3, #28] 8011ece: 2b00 cmp r3, #0 8011ed0: d005 beq.n 8011ede { (void)pdev->pClass[0]->SOF(pdev); 8011ed2: 687b ldr r3, [r7, #4] 8011ed4: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8011ed8: 69db ldr r3, [r3, #28] 8011eda: 6878 ldr r0, [r7, #4] 8011edc: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; 8011ede: 2300 movs r3, #0 } 8011ee0: 4618 mov r0, r3 8011ee2: 3708 adds r7, #8 8011ee4: 46bd mov sp, r7 8011ee6: bd80 pop {r7, pc} 08011ee8 : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { 8011ee8: b480 push {r7} 8011eea: b083 sub sp, #12 8011eec: af00 add r7, sp, #0 8011eee: 6078 str r0, [r7, #4] 8011ef0: 460b mov r3, r1 8011ef2: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8011ef4: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8011ef6: 4618 mov r0, r3 8011ef8: 370c adds r7, #12 8011efa: 46bd mov sp, r7 8011efc: f85d 7b04 ldr.w r7, [sp], #4 8011f00: 4770 bx lr 08011f02 : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { 8011f02: b480 push {r7} 8011f04: b083 sub sp, #12 8011f06: af00 add r7, sp, #0 8011f08: 6078 str r0, [r7, #4] 8011f0a: 460b mov r3, r1 8011f0c: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; 8011f0e: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } 8011f10: 4618 mov r0, r3 8011f12: 370c adds r7, #12 8011f14: 46bd mov sp, r7 8011f16: f85d 7b04 ldr.w r7, [sp], #4 8011f1a: 4770 bx lr 08011f1c : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { 8011f1c: b580 push {r7, lr} 8011f1e: b086 sub sp, #24 8011f20: af00 add r7, sp, #0 8011f22: 6078 str r0, [r7, #4] 8011f24: 460b mov r3, r1 8011f26: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; 8011f28: 687b ldr r3, [r7, #4] 8011f2a: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; 8011f2c: 687b ldr r3, [r7, #4] 8011f2e: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; 8011f30: 2300 movs r3, #0 8011f32: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) 8011f34: 68fb ldr r3, [r7, #12] 8011f36: 885b ldrh r3, [r3, #2] 8011f38: b29b uxth r3, r3 8011f3a: 68fa ldr r2, [r7, #12] 8011f3c: 7812 ldrb r2, [r2, #0] 8011f3e: 4293 cmp r3, r2 8011f40: d91f bls.n 8011f82 { ptr = desc->bLength; 8011f42: 68fb ldr r3, [r7, #12] 8011f44: 781b ldrb r3, [r3, #0] 8011f46: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) 8011f48: e013 b.n 8011f72 { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); 8011f4a: f107 030a add.w r3, r7, #10 8011f4e: 4619 mov r1, r3 8011f50: 6978 ldr r0, [r7, #20] 8011f52: f000 f81b bl 8011f8c 8011f56: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) 8011f58: 697b ldr r3, [r7, #20] 8011f5a: 785b ldrb r3, [r3, #1] 8011f5c: 2b05 cmp r3, #5 8011f5e: d108 bne.n 8011f72 { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; 8011f60: 697b ldr r3, [r7, #20] 8011f62: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) 8011f64: 693b ldr r3, [r7, #16] 8011f66: 789b ldrb r3, [r3, #2] 8011f68: 78fa ldrb r2, [r7, #3] 8011f6a: 429a cmp r2, r3 8011f6c: d008 beq.n 8011f80 { break; } else { pEpDesc = NULL; 8011f6e: 2300 movs r3, #0 8011f70: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) 8011f72: 68fb ldr r3, [r7, #12] 8011f74: 885b ldrh r3, [r3, #2] 8011f76: b29a uxth r2, r3 8011f78: 897b ldrh r3, [r7, #10] 8011f7a: 429a cmp r2, r3 8011f7c: d8e5 bhi.n 8011f4a 8011f7e: e000 b.n 8011f82 break; 8011f80: bf00 nop } } } } return (void *)pEpDesc; 8011f82: 693b ldr r3, [r7, #16] } 8011f84: 4618 mov r0, r3 8011f86: 3718 adds r7, #24 8011f88: 46bd mov sp, r7 8011f8a: bd80 pop {r7, pc} 08011f8c : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { 8011f8c: b480 push {r7} 8011f8e: b085 sub sp, #20 8011f90: af00 add r7, sp, #0 8011f92: 6078 str r0, [r7, #4] 8011f94: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; 8011f96: 687b ldr r3, [r7, #4] 8011f98: 60fb str r3, [r7, #12] *ptr += pnext->bLength; 8011f9a: 683b ldr r3, [r7, #0] 8011f9c: 881b ldrh r3, [r3, #0] 8011f9e: 68fa ldr r2, [r7, #12] 8011fa0: 7812 ldrb r2, [r2, #0] 8011fa2: 4413 add r3, r2 8011fa4: b29a uxth r2, r3 8011fa6: 683b ldr r3, [r7, #0] 8011fa8: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); 8011faa: 68fb ldr r3, [r7, #12] 8011fac: 781b ldrb r3, [r3, #0] 8011fae: 461a mov r2, r3 8011fb0: 687b ldr r3, [r7, #4] 8011fb2: 4413 add r3, r2 8011fb4: 60fb str r3, [r7, #12] return (pnext); 8011fb6: 68fb ldr r3, [r7, #12] } 8011fb8: 4618 mov r0, r3 8011fba: 3714 adds r7, #20 8011fbc: 46bd mov sp, r7 8011fbe: f85d 7b04 ldr.w r7, [sp], #4 8011fc2: 4770 bx lr 08011fc4 : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 8011fc4: b480 push {r7} 8011fc6: b087 sub sp, #28 8011fc8: af00 add r7, sp, #0 8011fca: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; 8011fcc: 687b ldr r3, [r7, #4] 8011fce: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 8011fd0: 697b ldr r3, [r7, #20] 8011fd2: 781b ldrb r3, [r3, #0] 8011fd4: 827b strh r3, [r7, #18] _pbuff++; 8011fd6: 697b ldr r3, [r7, #20] 8011fd8: 3301 adds r3, #1 8011fda: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8011fdc: 697b ldr r3, [r7, #20] 8011fde: 781b ldrb r3, [r3, #0] 8011fe0: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 8011fe2: f9b7 3010 ldrsh.w r3, [r7, #16] 8011fe6: 021b lsls r3, r3, #8 8011fe8: b21a sxth r2, r3 8011fea: f9b7 3012 ldrsh.w r3, [r7, #18] 8011fee: 4313 orrs r3, r2 8011ff0: b21b sxth r3, r3 8011ff2: 81fb strh r3, [r7, #14] return _SwapVal; 8011ff4: 89fb ldrh r3, [r7, #14] } 8011ff6: 4618 mov r0, r3 8011ff8: 371c adds r7, #28 8011ffa: 46bd mov sp, r7 8011ffc: f85d 7b04 ldr.w r7, [sp], #4 8012000: 4770 bx lr ... 08012004 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012004: b580 push {r7, lr} 8012006: b084 sub sp, #16 8012008: af00 add r7, sp, #0 801200a: 6078 str r0, [r7, #4] 801200c: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 801200e: 2300 movs r3, #0 8012010: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8012012: 683b ldr r3, [r7, #0] 8012014: 781b ldrb r3, [r3, #0] 8012016: f003 0360 and.w r3, r3, #96 @ 0x60 801201a: 2b40 cmp r3, #64 @ 0x40 801201c: d005 beq.n 801202a 801201e: 2b40 cmp r3, #64 @ 0x40 8012020: d857 bhi.n 80120d2 8012022: 2b00 cmp r3, #0 8012024: d00f beq.n 8012046 8012026: 2b20 cmp r3, #32 8012028: d153 bne.n 80120d2 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); 801202a: 687b ldr r3, [r7, #4] 801202c: f8d3 22d4 ldr.w r2, [r3, #724] @ 0x2d4 8012030: 687b ldr r3, [r7, #4] 8012032: 32ae adds r2, #174 @ 0xae 8012034: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8012038: 689b ldr r3, [r3, #8] 801203a: 6839 ldr r1, [r7, #0] 801203c: 6878 ldr r0, [r7, #4] 801203e: 4798 blx r3 8012040: 4603 mov r3, r0 8012042: 73fb strb r3, [r7, #15] break; 8012044: e04a b.n 80120dc case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8012046: 683b ldr r3, [r7, #0] 8012048: 785b ldrb r3, [r3, #1] 801204a: 2b09 cmp r3, #9 801204c: d83b bhi.n 80120c6 801204e: a201 add r2, pc, #4 @ (adr r2, 8012054 ) 8012050: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012054: 080120a9 .word 0x080120a9 8012058: 080120bd .word 0x080120bd 801205c: 080120c7 .word 0x080120c7 8012060: 080120b3 .word 0x080120b3 8012064: 080120c7 .word 0x080120c7 8012068: 08012087 .word 0x08012087 801206c: 0801207d .word 0x0801207d 8012070: 080120c7 .word 0x080120c7 8012074: 0801209f .word 0x0801209f 8012078: 08012091 .word 0x08012091 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 801207c: 6839 ldr r1, [r7, #0] 801207e: 6878 ldr r0, [r7, #4] 8012080: f000 fa3e bl 8012500 break; 8012084: e024 b.n 80120d0 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 8012086: 6839 ldr r1, [r7, #0] 8012088: 6878 ldr r0, [r7, #4] 801208a: f000 fbcd bl 8012828 break; 801208e: e01f b.n 80120d0 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 8012090: 6839 ldr r1, [r7, #0] 8012092: 6878 ldr r0, [r7, #4] 8012094: f000 fc0c bl 80128b0 8012098: 4603 mov r3, r0 801209a: 73fb strb r3, [r7, #15] break; 801209c: e018 b.n 80120d0 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 801209e: 6839 ldr r1, [r7, #0] 80120a0: 6878 ldr r0, [r7, #4] 80120a2: f000 fcaf bl 8012a04 break; 80120a6: e013 b.n 80120d0 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 80120a8: 6839 ldr r1, [r7, #0] 80120aa: 6878 ldr r0, [r7, #4] 80120ac: f000 fce0 bl 8012a70 break; 80120b0: e00e b.n 80120d0 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 80120b2: 6839 ldr r1, [r7, #0] 80120b4: 6878 ldr r0, [r7, #4] 80120b6: f000 fd0f bl 8012ad8 break; 80120ba: e009 b.n 80120d0 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 80120bc: 6839 ldr r1, [r7, #0] 80120be: 6878 ldr r0, [r7, #4] 80120c0: f000 fd33 bl 8012b2a break; 80120c4: e004 b.n 80120d0 default: USBD_CtlError(pdev, req); 80120c6: 6839 ldr r1, [r7, #0] 80120c8: 6878 ldr r0, [r7, #4] 80120ca: f000 fd8a bl 8012be2 break; 80120ce: bf00 nop } break; 80120d0: e004 b.n 80120dc default: USBD_CtlError(pdev, req); 80120d2: 6839 ldr r1, [r7, #0] 80120d4: 6878 ldr r0, [r7, #4] 80120d6: f000 fd84 bl 8012be2 break; 80120da: bf00 nop } return ret; 80120dc: 7bfb ldrb r3, [r7, #15] } 80120de: 4618 mov r0, r3 80120e0: 3710 adds r7, #16 80120e2: 46bd mov sp, r7 80120e4: bd80 pop {r7, pc} 80120e6: bf00 nop 080120e8 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80120e8: b580 push {r7, lr} 80120ea: b084 sub sp, #16 80120ec: af00 add r7, sp, #0 80120ee: 6078 str r0, [r7, #4] 80120f0: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 80120f2: 2300 movs r3, #0 80120f4: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) 80120f6: 683b ldr r3, [r7, #0] 80120f8: 781b ldrb r3, [r3, #0] 80120fa: f003 0360 and.w r3, r3, #96 @ 0x60 80120fe: 2b40 cmp r3, #64 @ 0x40 8012100: d005 beq.n 801210e 8012102: 2b40 cmp r3, #64 @ 0x40 8012104: d852 bhi.n 80121ac 8012106: 2b00 cmp r3, #0 8012108: d001 beq.n 801210e 801210a: 2b20 cmp r3, #32 801210c: d14e bne.n 80121ac { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 801210e: 687b ldr r3, [r7, #4] 8012110: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8012114: b2db uxtb r3, r3 8012116: 3b01 subs r3, #1 8012118: 2b02 cmp r3, #2 801211a: d840 bhi.n 801219e { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 801211c: 683b ldr r3, [r7, #0] 801211e: 889b ldrh r3, [r3, #4] 8012120: b2db uxtb r3, r3 8012122: 2b01 cmp r3, #1 8012124: d836 bhi.n 8012194 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); 8012126: 683b ldr r3, [r7, #0] 8012128: 889b ldrh r3, [r3, #4] 801212a: b2db uxtb r3, r3 801212c: 4619 mov r1, r3 801212e: 6878 ldr r0, [r7, #4] 8012130: f7ff feda bl 8011ee8 8012134: 4603 mov r3, r0 8012136: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8012138: 7bbb ldrb r3, [r7, #14] 801213a: 2bff cmp r3, #255 @ 0xff 801213c: d01d beq.n 801217a 801213e: 7bbb ldrb r3, [r7, #14] 8012140: 2b00 cmp r3, #0 8012142: d11a bne.n 801217a { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8012144: 7bba ldrb r2, [r7, #14] 8012146: 687b ldr r3, [r7, #4] 8012148: 32ae adds r2, #174 @ 0xae 801214a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801214e: 689b ldr r3, [r3, #8] 8012150: 2b00 cmp r3, #0 8012152: d00f beq.n 8012174 { pdev->classId = idx; 8012154: 7bba ldrb r2, [r7, #14] 8012156: 687b ldr r3, [r7, #4] 8012158: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 801215c: 7bba ldrb r2, [r7, #14] 801215e: 687b ldr r3, [r7, #4] 8012160: 32ae adds r2, #174 @ 0xae 8012162: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8012166: 689b ldr r3, [r3, #8] 8012168: 6839 ldr r1, [r7, #0] 801216a: 6878 ldr r0, [r7, #4] 801216c: 4798 blx r3 801216e: 4603 mov r3, r0 8012170: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8012172: e004 b.n 801217e } else { /* should never reach this condition */ ret = USBD_FAIL; 8012174: 2303 movs r3, #3 8012176: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) 8012178: e001 b.n 801217e } } else { /* No relative interface found */ ret = USBD_FAIL; 801217a: 2303 movs r3, #3 801217c: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) 801217e: 683b ldr r3, [r7, #0] 8012180: 88db ldrh r3, [r3, #6] 8012182: 2b00 cmp r3, #0 8012184: d110 bne.n 80121a8 8012186: 7bfb ldrb r3, [r7, #15] 8012188: 2b00 cmp r3, #0 801218a: d10d bne.n 80121a8 { (void)USBD_CtlSendStatus(pdev); 801218c: 6878 ldr r0, [r7, #4] 801218e: f000 fe06 bl 8012d9e } else { USBD_CtlError(pdev, req); } break; 8012192: e009 b.n 80121a8 USBD_CtlError(pdev, req); 8012194: 6839 ldr r1, [r7, #0] 8012196: 6878 ldr r0, [r7, #4] 8012198: f000 fd23 bl 8012be2 break; 801219c: e004 b.n 80121a8 default: USBD_CtlError(pdev, req); 801219e: 6839 ldr r1, [r7, #0] 80121a0: 6878 ldr r0, [r7, #4] 80121a2: f000 fd1e bl 8012be2 break; 80121a6: e000 b.n 80121aa break; 80121a8: bf00 nop } break; 80121aa: e004 b.n 80121b6 default: USBD_CtlError(pdev, req); 80121ac: 6839 ldr r1, [r7, #0] 80121ae: 6878 ldr r0, [r7, #4] 80121b0: f000 fd17 bl 8012be2 break; 80121b4: bf00 nop } return ret; 80121b6: 7bfb ldrb r3, [r7, #15] } 80121b8: 4618 mov r0, r3 80121ba: 3710 adds r7, #16 80121bc: 46bd mov sp, r7 80121be: bd80 pop {r7, pc} 080121c0 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80121c0: b580 push {r7, lr} 80121c2: b084 sub sp, #16 80121c4: af00 add r7, sp, #0 80121c6: 6078 str r0, [r7, #4] 80121c8: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; 80121ca: 2300 movs r3, #0 80121cc: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 80121ce: 683b ldr r3, [r7, #0] 80121d0: 889b ldrh r3, [r3, #4] 80121d2: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 80121d4: 683b ldr r3, [r7, #0] 80121d6: 781b ldrb r3, [r3, #0] 80121d8: f003 0360 and.w r3, r3, #96 @ 0x60 80121dc: 2b40 cmp r3, #64 @ 0x40 80121de: d007 beq.n 80121f0 80121e0: 2b40 cmp r3, #64 @ 0x40 80121e2: f200 8181 bhi.w 80124e8 80121e6: 2b00 cmp r3, #0 80121e8: d02a beq.n 8012240 80121ea: 2b20 cmp r3, #32 80121ec: f040 817c bne.w 80124e8 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); 80121f0: 7bbb ldrb r3, [r7, #14] 80121f2: 4619 mov r1, r3 80121f4: 6878 ldr r0, [r7, #4] 80121f6: f7ff fe84 bl 8011f02 80121fa: 4603 mov r3, r0 80121fc: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 80121fe: 7b7b ldrb r3, [r7, #13] 8012200: 2bff cmp r3, #255 @ 0xff 8012202: f000 8176 beq.w 80124f2 8012206: 7b7b ldrb r3, [r7, #13] 8012208: 2b00 cmp r3, #0 801220a: f040 8172 bne.w 80124f2 { pdev->classId = idx; 801220e: 7b7a ldrb r2, [r7, #13] 8012210: 687b ldr r3, [r7, #4] 8012212: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8012216: 7b7a ldrb r2, [r7, #13] 8012218: 687b ldr r3, [r7, #4] 801221a: 32ae adds r2, #174 @ 0xae 801221c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8012220: 689b ldr r3, [r3, #8] 8012222: 2b00 cmp r3, #0 8012224: f000 8165 beq.w 80124f2 { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); 8012228: 7b7a ldrb r2, [r7, #13] 801222a: 687b ldr r3, [r7, #4] 801222c: 32ae adds r2, #174 @ 0xae 801222e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8012232: 689b ldr r3, [r3, #8] 8012234: 6839 ldr r1, [r7, #0] 8012236: 6878 ldr r0, [r7, #4] 8012238: 4798 blx r3 801223a: 4603 mov r3, r0 801223c: 73fb strb r3, [r7, #15] } } break; 801223e: e158 b.n 80124f2 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8012240: 683b ldr r3, [r7, #0] 8012242: 785b ldrb r3, [r3, #1] 8012244: 2b03 cmp r3, #3 8012246: d008 beq.n 801225a 8012248: 2b03 cmp r3, #3 801224a: f300 8147 bgt.w 80124dc 801224e: 2b00 cmp r3, #0 8012250: f000 809b beq.w 801238a 8012254: 2b01 cmp r3, #1 8012256: d03c beq.n 80122d2 8012258: e140 b.n 80124dc { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 801225a: 687b ldr r3, [r7, #4] 801225c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8012260: b2db uxtb r3, r3 8012262: 2b02 cmp r3, #2 8012264: d002 beq.n 801226c 8012266: 2b03 cmp r3, #3 8012268: d016 beq.n 8012298 801226a: e02c b.n 80122c6 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 801226c: 7bbb ldrb r3, [r7, #14] 801226e: 2b00 cmp r3, #0 8012270: d00d beq.n 801228e 8012272: 7bbb ldrb r3, [r7, #14] 8012274: 2b80 cmp r3, #128 @ 0x80 8012276: d00a beq.n 801228e { (void)USBD_LL_StallEP(pdev, ep_addr); 8012278: 7bbb ldrb r3, [r7, #14] 801227a: 4619 mov r1, r3 801227c: 6878 ldr r0, [r7, #4] 801227e: f006 feed bl 801905c (void)USBD_LL_StallEP(pdev, 0x80U); 8012282: 2180 movs r1, #128 @ 0x80 8012284: 6878 ldr r0, [r7, #4] 8012286: f006 fee9 bl 801905c 801228a: bf00 nop } else { USBD_CtlError(pdev, req); } break; 801228c: e020 b.n 80122d0 USBD_CtlError(pdev, req); 801228e: 6839 ldr r1, [r7, #0] 8012290: 6878 ldr r0, [r7, #4] 8012292: f000 fca6 bl 8012be2 break; 8012296: e01b b.n 80122d0 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8012298: 683b ldr r3, [r7, #0] 801229a: 885b ldrh r3, [r3, #2] 801229c: 2b00 cmp r3, #0 801229e: d10e bne.n 80122be { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 80122a0: 7bbb ldrb r3, [r7, #14] 80122a2: 2b00 cmp r3, #0 80122a4: d00b beq.n 80122be 80122a6: 7bbb ldrb r3, [r7, #14] 80122a8: 2b80 cmp r3, #128 @ 0x80 80122aa: d008 beq.n 80122be 80122ac: 683b ldr r3, [r7, #0] 80122ae: 88db ldrh r3, [r3, #6] 80122b0: 2b00 cmp r3, #0 80122b2: d104 bne.n 80122be { (void)USBD_LL_StallEP(pdev, ep_addr); 80122b4: 7bbb ldrb r3, [r7, #14] 80122b6: 4619 mov r1, r3 80122b8: 6878 ldr r0, [r7, #4] 80122ba: f006 fecf bl 801905c } } (void)USBD_CtlSendStatus(pdev); 80122be: 6878 ldr r0, [r7, #4] 80122c0: f000 fd6d bl 8012d9e break; 80122c4: e004 b.n 80122d0 default: USBD_CtlError(pdev, req); 80122c6: 6839 ldr r1, [r7, #0] 80122c8: 6878 ldr r0, [r7, #4] 80122ca: f000 fc8a bl 8012be2 break; 80122ce: bf00 nop } break; 80122d0: e109 b.n 80124e6 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 80122d2: 687b ldr r3, [r7, #4] 80122d4: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80122d8: b2db uxtb r3, r3 80122da: 2b02 cmp r3, #2 80122dc: d002 beq.n 80122e4 80122de: 2b03 cmp r3, #3 80122e0: d016 beq.n 8012310 80122e2: e04b b.n 801237c { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 80122e4: 7bbb ldrb r3, [r7, #14] 80122e6: 2b00 cmp r3, #0 80122e8: d00d beq.n 8012306 80122ea: 7bbb ldrb r3, [r7, #14] 80122ec: 2b80 cmp r3, #128 @ 0x80 80122ee: d00a beq.n 8012306 { (void)USBD_LL_StallEP(pdev, ep_addr); 80122f0: 7bbb ldrb r3, [r7, #14] 80122f2: 4619 mov r1, r3 80122f4: 6878 ldr r0, [r7, #4] 80122f6: f006 feb1 bl 801905c (void)USBD_LL_StallEP(pdev, 0x80U); 80122fa: 2180 movs r1, #128 @ 0x80 80122fc: 6878 ldr r0, [r7, #4] 80122fe: f006 fead bl 801905c 8012302: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8012304: e040 b.n 8012388 USBD_CtlError(pdev, req); 8012306: 6839 ldr r1, [r7, #0] 8012308: 6878 ldr r0, [r7, #4] 801230a: f000 fc6a bl 8012be2 break; 801230e: e03b b.n 8012388 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8012310: 683b ldr r3, [r7, #0] 8012312: 885b ldrh r3, [r3, #2] 8012314: 2b00 cmp r3, #0 8012316: d136 bne.n 8012386 { if ((ep_addr & 0x7FU) != 0x00U) 8012318: 7bbb ldrb r3, [r7, #14] 801231a: f003 037f and.w r3, r3, #127 @ 0x7f 801231e: 2b00 cmp r3, #0 8012320: d004 beq.n 801232c { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 8012322: 7bbb ldrb r3, [r7, #14] 8012324: 4619 mov r1, r3 8012326: 6878 ldr r0, [r7, #4] 8012328: f006 feb7 bl 801909a } (void)USBD_CtlSendStatus(pdev); 801232c: 6878 ldr r0, [r7, #4] 801232e: f000 fd36 bl 8012d9e /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); 8012332: 7bbb ldrb r3, [r7, #14] 8012334: 4619 mov r1, r3 8012336: 6878 ldr r0, [r7, #4] 8012338: f7ff fde3 bl 8011f02 801233c: 4603 mov r3, r0 801233e: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) 8012340: 7b7b ldrb r3, [r7, #13] 8012342: 2bff cmp r3, #255 @ 0xff 8012344: d01f beq.n 8012386 8012346: 7b7b ldrb r3, [r7, #13] 8012348: 2b00 cmp r3, #0 801234a: d11c bne.n 8012386 { pdev->classId = idx; 801234c: 7b7a ldrb r2, [r7, #13] 801234e: 687b ldr r3, [r7, #4] 8012350: f8c3 22d4 str.w r2, [r3, #724] @ 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) 8012354: 7b7a ldrb r2, [r7, #13] 8012356: 687b ldr r3, [r7, #4] 8012358: 32ae adds r2, #174 @ 0xae 801235a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801235e: 689b ldr r3, [r3, #8] 8012360: 2b00 cmp r3, #0 8012362: d010 beq.n 8012386 { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); 8012364: 7b7a ldrb r2, [r7, #13] 8012366: 687b ldr r3, [r7, #4] 8012368: 32ae adds r2, #174 @ 0xae 801236a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801236e: 689b ldr r3, [r3, #8] 8012370: 6839 ldr r1, [r7, #0] 8012372: 6878 ldr r0, [r7, #4] 8012374: 4798 blx r3 8012376: 4603 mov r3, r0 8012378: 73fb strb r3, [r7, #15] } } } break; 801237a: e004 b.n 8012386 default: USBD_CtlError(pdev, req); 801237c: 6839 ldr r1, [r7, #0] 801237e: 6878 ldr r0, [r7, #4] 8012380: f000 fc2f bl 8012be2 break; 8012384: e000 b.n 8012388 break; 8012386: bf00 nop } break; 8012388: e0ad b.n 80124e6 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 801238a: 687b ldr r3, [r7, #4] 801238c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8012390: b2db uxtb r3, r3 8012392: 2b02 cmp r3, #2 8012394: d002 beq.n 801239c 8012396: 2b03 cmp r3, #3 8012398: d033 beq.n 8012402 801239a: e099 b.n 80124d0 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 801239c: 7bbb ldrb r3, [r7, #14] 801239e: 2b00 cmp r3, #0 80123a0: d007 beq.n 80123b2 80123a2: 7bbb ldrb r3, [r7, #14] 80123a4: 2b80 cmp r3, #128 @ 0x80 80123a6: d004 beq.n 80123b2 { USBD_CtlError(pdev, req); 80123a8: 6839 ldr r1, [r7, #0] 80123aa: 6878 ldr r0, [r7, #4] 80123ac: f000 fc19 bl 8012be2 break; 80123b0: e093 b.n 80124da } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80123b2: f997 300e ldrsb.w r3, [r7, #14] 80123b6: 2b00 cmp r3, #0 80123b8: da0b bge.n 80123d2 80123ba: 7bbb ldrb r3, [r7, #14] 80123bc: f003 027f and.w r2, r3, #127 @ 0x7f 80123c0: 4613 mov r3, r2 80123c2: 009b lsls r3, r3, #2 80123c4: 4413 add r3, r2 80123c6: 009b lsls r3, r3, #2 80123c8: 3310 adds r3, #16 80123ca: 687a ldr r2, [r7, #4] 80123cc: 4413 add r3, r2 80123ce: 3304 adds r3, #4 80123d0: e00b b.n 80123ea &pdev->ep_out[ep_addr & 0x7FU]; 80123d2: 7bbb ldrb r3, [r7, #14] 80123d4: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 80123d8: 4613 mov r3, r2 80123da: 009b lsls r3, r3, #2 80123dc: 4413 add r3, r2 80123de: 009b lsls r3, r3, #2 80123e0: f503 73a8 add.w r3, r3, #336 @ 0x150 80123e4: 687a ldr r2, [r7, #4] 80123e6: 4413 add r3, r2 80123e8: 3304 adds r3, #4 80123ea: 60bb str r3, [r7, #8] pep->status = 0x0000U; 80123ec: 68bb ldr r3, [r7, #8] 80123ee: 2200 movs r2, #0 80123f0: 739a strb r2, [r3, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 80123f2: 68bb ldr r3, [r7, #8] 80123f4: 330e adds r3, #14 80123f6: 2202 movs r2, #2 80123f8: 4619 mov r1, r3 80123fa: 6878 ldr r0, [r7, #4] 80123fc: f000 fc6e bl 8012cdc break; 8012400: e06b b.n 80124da case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 8012402: f997 300e ldrsb.w r3, [r7, #14] 8012406: 2b00 cmp r3, #0 8012408: da11 bge.n 801242e { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 801240a: 7bbb ldrb r3, [r7, #14] 801240c: f003 020f and.w r2, r3, #15 8012410: 6879 ldr r1, [r7, #4] 8012412: 4613 mov r3, r2 8012414: 009b lsls r3, r3, #2 8012416: 4413 add r3, r2 8012418: 009b lsls r3, r3, #2 801241a: 440b add r3, r1 801241c: 3323 adds r3, #35 @ 0x23 801241e: 781b ldrb r3, [r3, #0] 8012420: 2b00 cmp r3, #0 8012422: d117 bne.n 8012454 { USBD_CtlError(pdev, req); 8012424: 6839 ldr r1, [r7, #0] 8012426: 6878 ldr r0, [r7, #4] 8012428: f000 fbdb bl 8012be2 break; 801242c: e055 b.n 80124da } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 801242e: 7bbb ldrb r3, [r7, #14] 8012430: f003 020f and.w r2, r3, #15 8012434: 6879 ldr r1, [r7, #4] 8012436: 4613 mov r3, r2 8012438: 009b lsls r3, r3, #2 801243a: 4413 add r3, r2 801243c: 009b lsls r3, r3, #2 801243e: 440b add r3, r1 8012440: f203 1363 addw r3, r3, #355 @ 0x163 8012444: 781b ldrb r3, [r3, #0] 8012446: 2b00 cmp r3, #0 8012448: d104 bne.n 8012454 { USBD_CtlError(pdev, req); 801244a: 6839 ldr r1, [r7, #0] 801244c: 6878 ldr r0, [r7, #4] 801244e: f000 fbc8 bl 8012be2 break; 8012452: e042 b.n 80124da } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8012454: f997 300e ldrsb.w r3, [r7, #14] 8012458: 2b00 cmp r3, #0 801245a: da0b bge.n 8012474 801245c: 7bbb ldrb r3, [r7, #14] 801245e: f003 027f and.w r2, r3, #127 @ 0x7f 8012462: 4613 mov r3, r2 8012464: 009b lsls r3, r3, #2 8012466: 4413 add r3, r2 8012468: 009b lsls r3, r3, #2 801246a: 3310 adds r3, #16 801246c: 687a ldr r2, [r7, #4] 801246e: 4413 add r3, r2 8012470: 3304 adds r3, #4 8012472: e00b b.n 801248c &pdev->ep_out[ep_addr & 0x7FU]; 8012474: 7bbb ldrb r3, [r7, #14] 8012476: f003 027f and.w r2, r3, #127 @ 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 801247a: 4613 mov r3, r2 801247c: 009b lsls r3, r3, #2 801247e: 4413 add r3, r2 8012480: 009b lsls r3, r3, #2 8012482: f503 73a8 add.w r3, r3, #336 @ 0x150 8012486: 687a ldr r2, [r7, #4] 8012488: 4413 add r3, r2 801248a: 3304 adds r3, #4 801248c: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 801248e: 7bbb ldrb r3, [r7, #14] 8012490: 2b00 cmp r3, #0 8012492: d002 beq.n 801249a 8012494: 7bbb ldrb r3, [r7, #14] 8012496: 2b80 cmp r3, #128 @ 0x80 8012498: d103 bne.n 80124a2 { pep->status = 0x0000U; 801249a: 68bb ldr r3, [r7, #8] 801249c: 2200 movs r2, #0 801249e: 739a strb r2, [r3, #14] 80124a0: e00e b.n 80124c0 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 80124a2: 7bbb ldrb r3, [r7, #14] 80124a4: 4619 mov r1, r3 80124a6: 6878 ldr r0, [r7, #4] 80124a8: f006 fe16 bl 80190d8 80124ac: 4603 mov r3, r0 80124ae: 2b00 cmp r3, #0 80124b0: d003 beq.n 80124ba { pep->status = 0x0001U; 80124b2: 68bb ldr r3, [r7, #8] 80124b4: 2201 movs r2, #1 80124b6: 739a strb r2, [r3, #14] 80124b8: e002 b.n 80124c0 } else { pep->status = 0x0000U; 80124ba: 68bb ldr r3, [r7, #8] 80124bc: 2200 movs r2, #0 80124be: 739a strb r2, [r3, #14] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 80124c0: 68bb ldr r3, [r7, #8] 80124c2: 330e adds r3, #14 80124c4: 2202 movs r2, #2 80124c6: 4619 mov r1, r3 80124c8: 6878 ldr r0, [r7, #4] 80124ca: f000 fc07 bl 8012cdc break; 80124ce: e004 b.n 80124da default: USBD_CtlError(pdev, req); 80124d0: 6839 ldr r1, [r7, #0] 80124d2: 6878 ldr r0, [r7, #4] 80124d4: f000 fb85 bl 8012be2 break; 80124d8: bf00 nop } break; 80124da: e004 b.n 80124e6 default: USBD_CtlError(pdev, req); 80124dc: 6839 ldr r1, [r7, #0] 80124de: 6878 ldr r0, [r7, #4] 80124e0: f000 fb7f bl 8012be2 break; 80124e4: bf00 nop } break; 80124e6: e005 b.n 80124f4 default: USBD_CtlError(pdev, req); 80124e8: 6839 ldr r1, [r7, #0] 80124ea: 6878 ldr r0, [r7, #4] 80124ec: f000 fb79 bl 8012be2 break; 80124f0: e000 b.n 80124f4 break; 80124f2: bf00 nop } return ret; 80124f4: 7bfb ldrb r3, [r7, #15] } 80124f6: 4618 mov r0, r3 80124f8: 3710 adds r7, #16 80124fa: 46bd mov sp, r7 80124fc: bd80 pop {r7, pc} ... 08012500 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012500: b580 push {r7, lr} 8012502: b084 sub sp, #16 8012504: af00 add r7, sp, #0 8012506: 6078 str r0, [r7, #4] 8012508: 6039 str r1, [r7, #0] uint16_t len = 0U; 801250a: 2300 movs r3, #0 801250c: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 801250e: 2300 movs r3, #0 8012510: 60fb str r3, [r7, #12] uint8_t err = 0U; 8012512: 2300 movs r3, #0 8012514: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 8012516: 683b ldr r3, [r7, #0] 8012518: 885b ldrh r3, [r3, #2] 801251a: 0a1b lsrs r3, r3, #8 801251c: b29b uxth r3, r3 801251e: 3b01 subs r3, #1 8012520: 2b0e cmp r3, #14 8012522: f200 8152 bhi.w 80127ca 8012526: a201 add r2, pc, #4 @ (adr r2, 801252c ) 8012528: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801252c: 0801259d .word 0x0801259d 8012530: 080125b5 .word 0x080125b5 8012534: 080125f5 .word 0x080125f5 8012538: 080127cb .word 0x080127cb 801253c: 080127cb .word 0x080127cb 8012540: 0801276b .word 0x0801276b 8012544: 08012797 .word 0x08012797 8012548: 080127cb .word 0x080127cb 801254c: 080127cb .word 0x080127cb 8012550: 080127cb .word 0x080127cb 8012554: 080127cb .word 0x080127cb 8012558: 080127cb .word 0x080127cb 801255c: 080127cb .word 0x080127cb 8012560: 080127cb .word 0x080127cb 8012564: 08012569 .word 0x08012569 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 8012568: 687b ldr r3, [r7, #4] 801256a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 801256e: 69db ldr r3, [r3, #28] 8012570: 2b00 cmp r3, #0 8012572: d00b beq.n 801258c { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 8012574: 687b ldr r3, [r7, #4] 8012576: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 801257a: 69db ldr r3, [r3, #28] 801257c: 687a ldr r2, [r7, #4] 801257e: 7c12 ldrb r2, [r2, #16] 8012580: f107 0108 add.w r1, r7, #8 8012584: 4610 mov r0, r2 8012586: 4798 blx r3 8012588: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 801258a: e126 b.n 80127da USBD_CtlError(pdev, req); 801258c: 6839 ldr r1, [r7, #0] 801258e: 6878 ldr r0, [r7, #4] 8012590: f000 fb27 bl 8012be2 err++; 8012594: 7afb ldrb r3, [r7, #11] 8012596: 3301 adds r3, #1 8012598: 72fb strb r3, [r7, #11] break; 801259a: e11e b.n 80127da #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 801259c: 687b ldr r3, [r7, #4] 801259e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80125a2: 681b ldr r3, [r3, #0] 80125a4: 687a ldr r2, [r7, #4] 80125a6: 7c12 ldrb r2, [r2, #16] 80125a8: f107 0108 add.w r1, r7, #8 80125ac: 4610 mov r0, r2 80125ae: 4798 blx r3 80125b0: 60f8 str r0, [r7, #12] break; 80125b2: e112 b.n 80127da case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 80125b4: 687b ldr r3, [r7, #4] 80125b6: 7c1b ldrb r3, [r3, #16] 80125b8: 2b00 cmp r3, #0 80125ba: d10d bne.n 80125d8 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); 80125bc: 687b ldr r3, [r7, #4] 80125be: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80125c2: 6a9b ldr r3, [r3, #40] @ 0x28 80125c4: f107 0208 add.w r2, r7, #8 80125c8: 4610 mov r0, r2 80125ca: 4798 blx r3 80125cc: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 80125ce: 68fb ldr r3, [r7, #12] 80125d0: 3301 adds r3, #1 80125d2: 2202 movs r2, #2 80125d4: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 80125d6: e100 b.n 80127da pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); 80125d8: 687b ldr r3, [r7, #4] 80125da: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80125de: 6adb ldr r3, [r3, #44] @ 0x2c 80125e0: f107 0208 add.w r2, r7, #8 80125e4: 4610 mov r0, r2 80125e6: 4798 blx r3 80125e8: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 80125ea: 68fb ldr r3, [r7, #12] 80125ec: 3301 adds r3, #1 80125ee: 2202 movs r2, #2 80125f0: 701a strb r2, [r3, #0] break; 80125f2: e0f2 b.n 80127da case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 80125f4: 683b ldr r3, [r7, #0] 80125f6: 885b ldrh r3, [r3, #2] 80125f8: b2db uxtb r3, r3 80125fa: 2b05 cmp r3, #5 80125fc: f200 80ac bhi.w 8012758 8012600: a201 add r2, pc, #4 @ (adr r2, 8012608 ) 8012602: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012606: bf00 nop 8012608: 08012621 .word 0x08012621 801260c: 08012655 .word 0x08012655 8012610: 08012689 .word 0x08012689 8012614: 080126bd .word 0x080126bd 8012618: 080126f1 .word 0x080126f1 801261c: 08012725 .word 0x08012725 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 8012620: 687b ldr r3, [r7, #4] 8012622: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8012626: 685b ldr r3, [r3, #4] 8012628: 2b00 cmp r3, #0 801262a: d00b beq.n 8012644 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 801262c: 687b ldr r3, [r7, #4] 801262e: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8012632: 685b ldr r3, [r3, #4] 8012634: 687a ldr r2, [r7, #4] 8012636: 7c12 ldrb r2, [r2, #16] 8012638: f107 0108 add.w r1, r7, #8 801263c: 4610 mov r0, r2 801263e: 4798 blx r3 8012640: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8012642: e091 b.n 8012768 USBD_CtlError(pdev, req); 8012644: 6839 ldr r1, [r7, #0] 8012646: 6878 ldr r0, [r7, #4] 8012648: f000 facb bl 8012be2 err++; 801264c: 7afb ldrb r3, [r7, #11] 801264e: 3301 adds r3, #1 8012650: 72fb strb r3, [r7, #11] break; 8012652: e089 b.n 8012768 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 8012654: 687b ldr r3, [r7, #4] 8012656: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 801265a: 689b ldr r3, [r3, #8] 801265c: 2b00 cmp r3, #0 801265e: d00b beq.n 8012678 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 8012660: 687b ldr r3, [r7, #4] 8012662: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8012666: 689b ldr r3, [r3, #8] 8012668: 687a ldr r2, [r7, #4] 801266a: 7c12 ldrb r2, [r2, #16] 801266c: f107 0108 add.w r1, r7, #8 8012670: 4610 mov r0, r2 8012672: 4798 blx r3 8012674: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8012676: e077 b.n 8012768 USBD_CtlError(pdev, req); 8012678: 6839 ldr r1, [r7, #0] 801267a: 6878 ldr r0, [r7, #4] 801267c: f000 fab1 bl 8012be2 err++; 8012680: 7afb ldrb r3, [r7, #11] 8012682: 3301 adds r3, #1 8012684: 72fb strb r3, [r7, #11] break; 8012686: e06f b.n 8012768 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 8012688: 687b ldr r3, [r7, #4] 801268a: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 801268e: 68db ldr r3, [r3, #12] 8012690: 2b00 cmp r3, #0 8012692: d00b beq.n 80126ac { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 8012694: 687b ldr r3, [r7, #4] 8012696: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 801269a: 68db ldr r3, [r3, #12] 801269c: 687a ldr r2, [r7, #4] 801269e: 7c12 ldrb r2, [r2, #16] 80126a0: f107 0108 add.w r1, r7, #8 80126a4: 4610 mov r0, r2 80126a6: 4798 blx r3 80126a8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80126aa: e05d b.n 8012768 USBD_CtlError(pdev, req); 80126ac: 6839 ldr r1, [r7, #0] 80126ae: 6878 ldr r0, [r7, #4] 80126b0: f000 fa97 bl 8012be2 err++; 80126b4: 7afb ldrb r3, [r7, #11] 80126b6: 3301 adds r3, #1 80126b8: 72fb strb r3, [r7, #11] break; 80126ba: e055 b.n 8012768 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 80126bc: 687b ldr r3, [r7, #4] 80126be: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80126c2: 691b ldr r3, [r3, #16] 80126c4: 2b00 cmp r3, #0 80126c6: d00b beq.n 80126e0 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 80126c8: 687b ldr r3, [r7, #4] 80126ca: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80126ce: 691b ldr r3, [r3, #16] 80126d0: 687a ldr r2, [r7, #4] 80126d2: 7c12 ldrb r2, [r2, #16] 80126d4: f107 0108 add.w r1, r7, #8 80126d8: 4610 mov r0, r2 80126da: 4798 blx r3 80126dc: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 80126de: e043 b.n 8012768 USBD_CtlError(pdev, req); 80126e0: 6839 ldr r1, [r7, #0] 80126e2: 6878 ldr r0, [r7, #4] 80126e4: f000 fa7d bl 8012be2 err++; 80126e8: 7afb ldrb r3, [r7, #11] 80126ea: 3301 adds r3, #1 80126ec: 72fb strb r3, [r7, #11] break; 80126ee: e03b b.n 8012768 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 80126f0: 687b ldr r3, [r7, #4] 80126f2: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 80126f6: 695b ldr r3, [r3, #20] 80126f8: 2b00 cmp r3, #0 80126fa: d00b beq.n 8012714 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 80126fc: 687b ldr r3, [r7, #4] 80126fe: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8012702: 695b ldr r3, [r3, #20] 8012704: 687a ldr r2, [r7, #4] 8012706: 7c12 ldrb r2, [r2, #16] 8012708: f107 0108 add.w r1, r7, #8 801270c: 4610 mov r0, r2 801270e: 4798 blx r3 8012710: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8012712: e029 b.n 8012768 USBD_CtlError(pdev, req); 8012714: 6839 ldr r1, [r7, #0] 8012716: 6878 ldr r0, [r7, #4] 8012718: f000 fa63 bl 8012be2 err++; 801271c: 7afb ldrb r3, [r7, #11] 801271e: 3301 adds r3, #1 8012720: 72fb strb r3, [r7, #11] break; 8012722: e021 b.n 8012768 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8012724: 687b ldr r3, [r7, #4] 8012726: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 801272a: 699b ldr r3, [r3, #24] 801272c: 2b00 cmp r3, #0 801272e: d00b beq.n 8012748 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8012730: 687b ldr r3, [r7, #4] 8012732: f8d3 32b4 ldr.w r3, [r3, #692] @ 0x2b4 8012736: 699b ldr r3, [r3, #24] 8012738: 687a ldr r2, [r7, #4] 801273a: 7c12 ldrb r2, [r2, #16] 801273c: f107 0108 add.w r1, r7, #8 8012740: 4610 mov r0, r2 8012742: 4798 blx r3 8012744: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8012746: e00f b.n 8012768 USBD_CtlError(pdev, req); 8012748: 6839 ldr r1, [r7, #0] 801274a: 6878 ldr r0, [r7, #4] 801274c: f000 fa49 bl 8012be2 err++; 8012750: 7afb ldrb r3, [r7, #11] 8012752: 3301 adds r3, #1 8012754: 72fb strb r3, [r7, #11] break; 8012756: e007 b.n 8012768 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8012758: 6839 ldr r1, [r7, #0] 801275a: 6878 ldr r0, [r7, #4] 801275c: f000 fa41 bl 8012be2 err++; 8012760: 7afb ldrb r3, [r7, #11] 8012762: 3301 adds r3, #1 8012764: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; 8012766: bf00 nop } break; 8012768: e037 b.n 80127da case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 801276a: 687b ldr r3, [r7, #4] 801276c: 7c1b ldrb r3, [r3, #16] 801276e: 2b00 cmp r3, #0 8012770: d109 bne.n 8012786 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); 8012772: 687b ldr r3, [r7, #4] 8012774: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 8012778: 6b5b ldr r3, [r3, #52] @ 0x34 801277a: f107 0208 add.w r2, r7, #8 801277e: 4610 mov r0, r2 8012780: 4798 blx r3 8012782: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8012784: e029 b.n 80127da USBD_CtlError(pdev, req); 8012786: 6839 ldr r1, [r7, #0] 8012788: 6878 ldr r0, [r7, #4] 801278a: f000 fa2a bl 8012be2 err++; 801278e: 7afb ldrb r3, [r7, #11] 8012790: 3301 adds r3, #1 8012792: 72fb strb r3, [r7, #11] break; 8012794: e021 b.n 80127da case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8012796: 687b ldr r3, [r7, #4] 8012798: 7c1b ldrb r3, [r3, #16] 801279a: 2b00 cmp r3, #0 801279c: d10d bne.n 80127ba pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); 801279e: 687b ldr r3, [r7, #4] 80127a0: f8d3 32b8 ldr.w r3, [r3, #696] @ 0x2b8 80127a4: 6b1b ldr r3, [r3, #48] @ 0x30 80127a6: f107 0208 add.w r2, r7, #8 80127aa: 4610 mov r0, r2 80127ac: 4798 blx r3 80127ae: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 80127b0: 68fb ldr r3, [r7, #12] 80127b2: 3301 adds r3, #1 80127b4: 2207 movs r2, #7 80127b6: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 80127b8: e00f b.n 80127da USBD_CtlError(pdev, req); 80127ba: 6839 ldr r1, [r7, #0] 80127bc: 6878 ldr r0, [r7, #4] 80127be: f000 fa10 bl 8012be2 err++; 80127c2: 7afb ldrb r3, [r7, #11] 80127c4: 3301 adds r3, #1 80127c6: 72fb strb r3, [r7, #11] break; 80127c8: e007 b.n 80127da default: USBD_CtlError(pdev, req); 80127ca: 6839 ldr r1, [r7, #0] 80127cc: 6878 ldr r0, [r7, #4] 80127ce: f000 fa08 bl 8012be2 err++; 80127d2: 7afb ldrb r3, [r7, #11] 80127d4: 3301 adds r3, #1 80127d6: 72fb strb r3, [r7, #11] break; 80127d8: bf00 nop } if (err != 0U) 80127da: 7afb ldrb r3, [r7, #11] 80127dc: 2b00 cmp r3, #0 80127de: d11e bne.n 801281e { return; } if (req->wLength != 0U) 80127e0: 683b ldr r3, [r7, #0] 80127e2: 88db ldrh r3, [r3, #6] 80127e4: 2b00 cmp r3, #0 80127e6: d016 beq.n 8012816 { if (len != 0U) 80127e8: 893b ldrh r3, [r7, #8] 80127ea: 2b00 cmp r3, #0 80127ec: d00e beq.n 801280c { len = MIN(len, req->wLength); 80127ee: 683b ldr r3, [r7, #0] 80127f0: 88da ldrh r2, [r3, #6] 80127f2: 893b ldrh r3, [r7, #8] 80127f4: 4293 cmp r3, r2 80127f6: bf28 it cs 80127f8: 4613 movcs r3, r2 80127fa: b29b uxth r3, r3 80127fc: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 80127fe: 893b ldrh r3, [r7, #8] 8012800: 461a mov r2, r3 8012802: 68f9 ldr r1, [r7, #12] 8012804: 6878 ldr r0, [r7, #4] 8012806: f000 fa69 bl 8012cdc 801280a: e009 b.n 8012820 } else { USBD_CtlError(pdev, req); 801280c: 6839 ldr r1, [r7, #0] 801280e: 6878 ldr r0, [r7, #4] 8012810: f000 f9e7 bl 8012be2 8012814: e004 b.n 8012820 } } else { (void)USBD_CtlSendStatus(pdev); 8012816: 6878 ldr r0, [r7, #4] 8012818: f000 fac1 bl 8012d9e 801281c: e000 b.n 8012820 return; 801281e: bf00 nop } } 8012820: 3710 adds r7, #16 8012822: 46bd mov sp, r7 8012824: bd80 pop {r7, pc} 8012826: bf00 nop 08012828 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012828: b580 push {r7, lr} 801282a: b084 sub sp, #16 801282c: af00 add r7, sp, #0 801282e: 6078 str r0, [r7, #4] 8012830: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8012832: 683b ldr r3, [r7, #0] 8012834: 889b ldrh r3, [r3, #4] 8012836: 2b00 cmp r3, #0 8012838: d131 bne.n 801289e 801283a: 683b ldr r3, [r7, #0] 801283c: 88db ldrh r3, [r3, #6] 801283e: 2b00 cmp r3, #0 8012840: d12d bne.n 801289e 8012842: 683b ldr r3, [r7, #0] 8012844: 885b ldrh r3, [r3, #2] 8012846: 2b7f cmp r3, #127 @ 0x7f 8012848: d829 bhi.n 801289e { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 801284a: 683b ldr r3, [r7, #0] 801284c: 885b ldrh r3, [r3, #2] 801284e: b2db uxtb r3, r3 8012850: f003 037f and.w r3, r3, #127 @ 0x7f 8012854: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8012856: 687b ldr r3, [r7, #4] 8012858: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 801285c: b2db uxtb r3, r3 801285e: 2b03 cmp r3, #3 8012860: d104 bne.n 801286c { USBD_CtlError(pdev, req); 8012862: 6839 ldr r1, [r7, #0] 8012864: 6878 ldr r0, [r7, #4] 8012866: f000 f9bc bl 8012be2 if (pdev->dev_state == USBD_STATE_CONFIGURED) 801286a: e01d b.n 80128a8 } else { pdev->dev_address = dev_addr; 801286c: 687b ldr r3, [r7, #4] 801286e: 7bfa ldrb r2, [r7, #15] 8012870: f883 229e strb.w r2, [r3, #670] @ 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8012874: 7bfb ldrb r3, [r7, #15] 8012876: 4619 mov r1, r3 8012878: 6878 ldr r0, [r7, #4] 801287a: f006 fc59 bl 8019130 (void)USBD_CtlSendStatus(pdev); 801287e: 6878 ldr r0, [r7, #4] 8012880: f000 fa8d bl 8012d9e if (dev_addr != 0U) 8012884: 7bfb ldrb r3, [r7, #15] 8012886: 2b00 cmp r3, #0 8012888: d004 beq.n 8012894 { pdev->dev_state = USBD_STATE_ADDRESSED; 801288a: 687b ldr r3, [r7, #4] 801288c: 2202 movs r2, #2 801288e: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8012892: e009 b.n 80128a8 } else { pdev->dev_state = USBD_STATE_DEFAULT; 8012894: 687b ldr r3, [r7, #4] 8012896: 2201 movs r2, #1 8012898: f883 229c strb.w r2, [r3, #668] @ 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 801289c: e004 b.n 80128a8 } } } else { USBD_CtlError(pdev, req); 801289e: 6839 ldr r1, [r7, #0] 80128a0: 6878 ldr r0, [r7, #4] 80128a2: f000 f99e bl 8012be2 } } 80128a6: bf00 nop 80128a8: bf00 nop 80128aa: 3710 adds r7, #16 80128ac: 46bd mov sp, r7 80128ae: bd80 pop {r7, pc} 080128b0 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80128b0: b580 push {r7, lr} 80128b2: b084 sub sp, #16 80128b4: af00 add r7, sp, #0 80128b6: 6078 str r0, [r7, #4] 80128b8: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 80128ba: 2300 movs r3, #0 80128bc: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 80128be: 683b ldr r3, [r7, #0] 80128c0: 885b ldrh r3, [r3, #2] 80128c2: b2da uxtb r2, r3 80128c4: 4b4e ldr r3, [pc, #312] @ (8012a00 ) 80128c6: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 80128c8: 4b4d ldr r3, [pc, #308] @ (8012a00 ) 80128ca: 781b ldrb r3, [r3, #0] 80128cc: 2b01 cmp r3, #1 80128ce: d905 bls.n 80128dc { USBD_CtlError(pdev, req); 80128d0: 6839 ldr r1, [r7, #0] 80128d2: 6878 ldr r0, [r7, #4] 80128d4: f000 f985 bl 8012be2 return USBD_FAIL; 80128d8: 2303 movs r3, #3 80128da: e08c b.n 80129f6 } switch (pdev->dev_state) 80128dc: 687b ldr r3, [r7, #4] 80128de: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 80128e2: b2db uxtb r3, r3 80128e4: 2b02 cmp r3, #2 80128e6: d002 beq.n 80128ee 80128e8: 2b03 cmp r3, #3 80128ea: d029 beq.n 8012940 80128ec: e075 b.n 80129da { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 80128ee: 4b44 ldr r3, [pc, #272] @ (8012a00 ) 80128f0: 781b ldrb r3, [r3, #0] 80128f2: 2b00 cmp r3, #0 80128f4: d020 beq.n 8012938 { pdev->dev_config = cfgidx; 80128f6: 4b42 ldr r3, [pc, #264] @ (8012a00 ) 80128f8: 781b ldrb r3, [r3, #0] 80128fa: 461a mov r2, r3 80128fc: 687b ldr r3, [r7, #4] 80128fe: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8012900: 4b3f ldr r3, [pc, #252] @ (8012a00 ) 8012902: 781b ldrb r3, [r3, #0] 8012904: 4619 mov r1, r3 8012906: 6878 ldr r0, [r7, #4] 8012908: f7ff f835 bl 8011976 801290c: 4603 mov r3, r0 801290e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8012910: 7bfb ldrb r3, [r7, #15] 8012912: 2b00 cmp r3, #0 8012914: d008 beq.n 8012928 { USBD_CtlError(pdev, req); 8012916: 6839 ldr r1, [r7, #0] 8012918: 6878 ldr r0, [r7, #4] 801291a: f000 f962 bl 8012be2 pdev->dev_state = USBD_STATE_ADDRESSED; 801291e: 687b ldr r3, [r7, #4] 8012920: 2202 movs r2, #2 8012922: f883 229c strb.w r2, [r3, #668] @ 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; 8012926: e065 b.n 80129f4 (void)USBD_CtlSendStatus(pdev); 8012928: 6878 ldr r0, [r7, #4] 801292a: f000 fa38 bl 8012d9e pdev->dev_state = USBD_STATE_CONFIGURED; 801292e: 687b ldr r3, [r7, #4] 8012930: 2203 movs r2, #3 8012932: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 8012936: e05d b.n 80129f4 (void)USBD_CtlSendStatus(pdev); 8012938: 6878 ldr r0, [r7, #4] 801293a: f000 fa30 bl 8012d9e break; 801293e: e059 b.n 80129f4 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8012940: 4b2f ldr r3, [pc, #188] @ (8012a00 ) 8012942: 781b ldrb r3, [r3, #0] 8012944: 2b00 cmp r3, #0 8012946: d112 bne.n 801296e { pdev->dev_state = USBD_STATE_ADDRESSED; 8012948: 687b ldr r3, [r7, #4] 801294a: 2202 movs r2, #2 801294c: f883 229c strb.w r2, [r3, #668] @ 0x29c pdev->dev_config = cfgidx; 8012950: 4b2b ldr r3, [pc, #172] @ (8012a00 ) 8012952: 781b ldrb r3, [r3, #0] 8012954: 461a mov r2, r3 8012956: 687b ldr r3, [r7, #4] 8012958: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 801295a: 4b29 ldr r3, [pc, #164] @ (8012a00 ) 801295c: 781b ldrb r3, [r3, #0] 801295e: 4619 mov r1, r3 8012960: 6878 ldr r0, [r7, #4] 8012962: f7ff f824 bl 80119ae (void)USBD_CtlSendStatus(pdev); 8012966: 6878 ldr r0, [r7, #4] 8012968: f000 fa19 bl 8012d9e } else { (void)USBD_CtlSendStatus(pdev); } break; 801296c: e042 b.n 80129f4 else if (cfgidx != pdev->dev_config) 801296e: 4b24 ldr r3, [pc, #144] @ (8012a00 ) 8012970: 781b ldrb r3, [r3, #0] 8012972: 461a mov r2, r3 8012974: 687b ldr r3, [r7, #4] 8012976: 685b ldr r3, [r3, #4] 8012978: 429a cmp r2, r3 801297a: d02a beq.n 80129d2 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 801297c: 687b ldr r3, [r7, #4] 801297e: 685b ldr r3, [r3, #4] 8012980: b2db uxtb r3, r3 8012982: 4619 mov r1, r3 8012984: 6878 ldr r0, [r7, #4] 8012986: f7ff f812 bl 80119ae pdev->dev_config = cfgidx; 801298a: 4b1d ldr r3, [pc, #116] @ (8012a00 ) 801298c: 781b ldrb r3, [r3, #0] 801298e: 461a mov r2, r3 8012990: 687b ldr r3, [r7, #4] 8012992: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8012994: 4b1a ldr r3, [pc, #104] @ (8012a00 ) 8012996: 781b ldrb r3, [r3, #0] 8012998: 4619 mov r1, r3 801299a: 6878 ldr r0, [r7, #4] 801299c: f7fe ffeb bl 8011976 80129a0: 4603 mov r3, r0 80129a2: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 80129a4: 7bfb ldrb r3, [r7, #15] 80129a6: 2b00 cmp r3, #0 80129a8: d00f beq.n 80129ca USBD_CtlError(pdev, req); 80129aa: 6839 ldr r1, [r7, #0] 80129ac: 6878 ldr r0, [r7, #4] 80129ae: f000 f918 bl 8012be2 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 80129b2: 687b ldr r3, [r7, #4] 80129b4: 685b ldr r3, [r3, #4] 80129b6: b2db uxtb r3, r3 80129b8: 4619 mov r1, r3 80129ba: 6878 ldr r0, [r7, #4] 80129bc: f7fe fff7 bl 80119ae pdev->dev_state = USBD_STATE_ADDRESSED; 80129c0: 687b ldr r3, [r7, #4] 80129c2: 2202 movs r2, #2 80129c4: f883 229c strb.w r2, [r3, #668] @ 0x29c break; 80129c8: e014 b.n 80129f4 (void)USBD_CtlSendStatus(pdev); 80129ca: 6878 ldr r0, [r7, #4] 80129cc: f000 f9e7 bl 8012d9e break; 80129d0: e010 b.n 80129f4 (void)USBD_CtlSendStatus(pdev); 80129d2: 6878 ldr r0, [r7, #4] 80129d4: f000 f9e3 bl 8012d9e break; 80129d8: e00c b.n 80129f4 default: USBD_CtlError(pdev, req); 80129da: 6839 ldr r1, [r7, #0] 80129dc: 6878 ldr r0, [r7, #4] 80129de: f000 f900 bl 8012be2 (void)USBD_ClrClassConfig(pdev, cfgidx); 80129e2: 4b07 ldr r3, [pc, #28] @ (8012a00 ) 80129e4: 781b ldrb r3, [r3, #0] 80129e6: 4619 mov r1, r3 80129e8: 6878 ldr r0, [r7, #4] 80129ea: f7fe ffe0 bl 80119ae ret = USBD_FAIL; 80129ee: 2303 movs r3, #3 80129f0: 73fb strb r3, [r7, #15] break; 80129f2: bf00 nop } return ret; 80129f4: 7bfb ldrb r3, [r7, #15] } 80129f6: 4618 mov r0, r3 80129f8: 3710 adds r7, #16 80129fa: 46bd mov sp, r7 80129fc: bd80 pop {r7, pc} 80129fe: bf00 nop 8012a00: 20000784 .word 0x20000784 08012a04 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012a04: b580 push {r7, lr} 8012a06: b082 sub sp, #8 8012a08: af00 add r7, sp, #0 8012a0a: 6078 str r0, [r7, #4] 8012a0c: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8012a0e: 683b ldr r3, [r7, #0] 8012a10: 88db ldrh r3, [r3, #6] 8012a12: 2b01 cmp r3, #1 8012a14: d004 beq.n 8012a20 { USBD_CtlError(pdev, req); 8012a16: 6839 ldr r1, [r7, #0] 8012a18: 6878 ldr r0, [r7, #4] 8012a1a: f000 f8e2 bl 8012be2 default: USBD_CtlError(pdev, req); break; } } } 8012a1e: e023 b.n 8012a68 switch (pdev->dev_state) 8012a20: 687b ldr r3, [r7, #4] 8012a22: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8012a26: b2db uxtb r3, r3 8012a28: 2b02 cmp r3, #2 8012a2a: dc02 bgt.n 8012a32 8012a2c: 2b00 cmp r3, #0 8012a2e: dc03 bgt.n 8012a38 8012a30: e015 b.n 8012a5e 8012a32: 2b03 cmp r3, #3 8012a34: d00b beq.n 8012a4e 8012a36: e012 b.n 8012a5e pdev->dev_default_config = 0U; 8012a38: 687b ldr r3, [r7, #4] 8012a3a: 2200 movs r2, #0 8012a3c: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 8012a3e: 687b ldr r3, [r7, #4] 8012a40: 3308 adds r3, #8 8012a42: 2201 movs r2, #1 8012a44: 4619 mov r1, r3 8012a46: 6878 ldr r0, [r7, #4] 8012a48: f000 f948 bl 8012cdc break; 8012a4c: e00c b.n 8012a68 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 8012a4e: 687b ldr r3, [r7, #4] 8012a50: 3304 adds r3, #4 8012a52: 2201 movs r2, #1 8012a54: 4619 mov r1, r3 8012a56: 6878 ldr r0, [r7, #4] 8012a58: f000 f940 bl 8012cdc break; 8012a5c: e004 b.n 8012a68 USBD_CtlError(pdev, req); 8012a5e: 6839 ldr r1, [r7, #0] 8012a60: 6878 ldr r0, [r7, #4] 8012a62: f000 f8be bl 8012be2 break; 8012a66: bf00 nop } 8012a68: bf00 nop 8012a6a: 3708 adds r7, #8 8012a6c: 46bd mov sp, r7 8012a6e: bd80 pop {r7, pc} 08012a70 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012a70: b580 push {r7, lr} 8012a72: b082 sub sp, #8 8012a74: af00 add r7, sp, #0 8012a76: 6078 str r0, [r7, #4] 8012a78: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8012a7a: 687b ldr r3, [r7, #4] 8012a7c: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8012a80: b2db uxtb r3, r3 8012a82: 3b01 subs r3, #1 8012a84: 2b02 cmp r3, #2 8012a86: d81e bhi.n 8012ac6 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 8012a88: 683b ldr r3, [r7, #0] 8012a8a: 88db ldrh r3, [r3, #6] 8012a8c: 2b02 cmp r3, #2 8012a8e: d004 beq.n 8012a9a { USBD_CtlError(pdev, req); 8012a90: 6839 ldr r1, [r7, #0] 8012a92: 6878 ldr r0, [r7, #4] 8012a94: f000 f8a5 bl 8012be2 break; 8012a98: e01a b.n 8012ad0 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8012a9a: 687b ldr r3, [r7, #4] 8012a9c: 2201 movs r2, #1 8012a9e: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) 8012aa0: 687b ldr r3, [r7, #4] 8012aa2: f8d3 32a4 ldr.w r3, [r3, #676] @ 0x2a4 8012aa6: 2b00 cmp r3, #0 8012aa8: d005 beq.n 8012ab6 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8012aaa: 687b ldr r3, [r7, #4] 8012aac: 68db ldr r3, [r3, #12] 8012aae: f043 0202 orr.w r2, r3, #2 8012ab2: 687b ldr r3, [r7, #4] 8012ab4: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 8012ab6: 687b ldr r3, [r7, #4] 8012ab8: 330c adds r3, #12 8012aba: 2202 movs r2, #2 8012abc: 4619 mov r1, r3 8012abe: 6878 ldr r0, [r7, #4] 8012ac0: f000 f90c bl 8012cdc break; 8012ac4: e004 b.n 8012ad0 default: USBD_CtlError(pdev, req); 8012ac6: 6839 ldr r1, [r7, #0] 8012ac8: 6878 ldr r0, [r7, #4] 8012aca: f000 f88a bl 8012be2 break; 8012ace: bf00 nop } } 8012ad0: bf00 nop 8012ad2: 3708 adds r7, #8 8012ad4: 46bd mov sp, r7 8012ad6: bd80 pop {r7, pc} 08012ad8 : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012ad8: b580 push {r7, lr} 8012ada: b082 sub sp, #8 8012adc: af00 add r7, sp, #0 8012ade: 6078 str r0, [r7, #4] 8012ae0: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8012ae2: 683b ldr r3, [r7, #0] 8012ae4: 885b ldrh r3, [r3, #2] 8012ae6: 2b01 cmp r3, #1 8012ae8: d107 bne.n 8012afa { pdev->dev_remote_wakeup = 1U; 8012aea: 687b ldr r3, [r7, #4] 8012aec: 2201 movs r2, #1 8012aee: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8012af2: 6878 ldr r0, [r7, #4] 8012af4: f000 f953 bl 8012d9e } else { USBD_CtlError(pdev, req); } } 8012af8: e013 b.n 8012b22 else if (req->wValue == USB_FEATURE_TEST_MODE) 8012afa: 683b ldr r3, [r7, #0] 8012afc: 885b ldrh r3, [r3, #2] 8012afe: 2b02 cmp r3, #2 8012b00: d10b bne.n 8012b1a pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); 8012b02: 683b ldr r3, [r7, #0] 8012b04: 889b ldrh r3, [r3, #4] 8012b06: 0a1b lsrs r3, r3, #8 8012b08: b29b uxth r3, r3 8012b0a: b2da uxtb r2, r3 8012b0c: 687b ldr r3, [r7, #4] 8012b0e: f883 22a0 strb.w r2, [r3, #672] @ 0x2a0 (void)USBD_CtlSendStatus(pdev); 8012b12: 6878 ldr r0, [r7, #4] 8012b14: f000 f943 bl 8012d9e } 8012b18: e003 b.n 8012b22 USBD_CtlError(pdev, req); 8012b1a: 6839 ldr r1, [r7, #0] 8012b1c: 6878 ldr r0, [r7, #4] 8012b1e: f000 f860 bl 8012be2 } 8012b22: bf00 nop 8012b24: 3708 adds r7, #8 8012b26: 46bd mov sp, r7 8012b28: bd80 pop {r7, pc} 08012b2a : * @param pdev: device instance * @param req: usb request * @retval None */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012b2a: b580 push {r7, lr} 8012b2c: b082 sub sp, #8 8012b2e: af00 add r7, sp, #0 8012b30: 6078 str r0, [r7, #4] 8012b32: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8012b34: 687b ldr r3, [r7, #4] 8012b36: f893 329c ldrb.w r3, [r3, #668] @ 0x29c 8012b3a: b2db uxtb r3, r3 8012b3c: 3b01 subs r3, #1 8012b3e: 2b02 cmp r3, #2 8012b40: d80b bhi.n 8012b5a { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8012b42: 683b ldr r3, [r7, #0] 8012b44: 885b ldrh r3, [r3, #2] 8012b46: 2b01 cmp r3, #1 8012b48: d10c bne.n 8012b64 { pdev->dev_remote_wakeup = 0U; 8012b4a: 687b ldr r3, [r7, #4] 8012b4c: 2200 movs r2, #0 8012b4e: f8c3 22a4 str.w r2, [r3, #676] @ 0x2a4 (void)USBD_CtlSendStatus(pdev); 8012b52: 6878 ldr r0, [r7, #4] 8012b54: f000 f923 bl 8012d9e } break; 8012b58: e004 b.n 8012b64 default: USBD_CtlError(pdev, req); 8012b5a: 6839 ldr r1, [r7, #0] 8012b5c: 6878 ldr r0, [r7, #4] 8012b5e: f000 f840 bl 8012be2 break; 8012b62: e000 b.n 8012b66 break; 8012b64: bf00 nop } } 8012b66: bf00 nop 8012b68: 3708 adds r7, #8 8012b6a: 46bd mov sp, r7 8012b6c: bd80 pop {r7, pc} 08012b6e : * @param req: usb request * @param pdata: setup data pointer * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 8012b6e: b580 push {r7, lr} 8012b70: b084 sub sp, #16 8012b72: af00 add r7, sp, #0 8012b74: 6078 str r0, [r7, #4] 8012b76: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 8012b78: 683b ldr r3, [r7, #0] 8012b7a: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 8012b7c: 68fb ldr r3, [r7, #12] 8012b7e: 781a ldrb r2, [r3, #0] 8012b80: 687b ldr r3, [r7, #4] 8012b82: 701a strb r2, [r3, #0] pbuff++; 8012b84: 68fb ldr r3, [r7, #12] 8012b86: 3301 adds r3, #1 8012b88: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 8012b8a: 68fb ldr r3, [r7, #12] 8012b8c: 781a ldrb r2, [r3, #0] 8012b8e: 687b ldr r3, [r7, #4] 8012b90: 705a strb r2, [r3, #1] pbuff++; 8012b92: 68fb ldr r3, [r7, #12] 8012b94: 3301 adds r3, #1 8012b96: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 8012b98: 68f8 ldr r0, [r7, #12] 8012b9a: f7ff fa13 bl 8011fc4 8012b9e: 4603 mov r3, r0 8012ba0: 461a mov r2, r3 8012ba2: 687b ldr r3, [r7, #4] 8012ba4: 805a strh r2, [r3, #2] pbuff++; 8012ba6: 68fb ldr r3, [r7, #12] 8012ba8: 3301 adds r3, #1 8012baa: 60fb str r3, [r7, #12] pbuff++; 8012bac: 68fb ldr r3, [r7, #12] 8012bae: 3301 adds r3, #1 8012bb0: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 8012bb2: 68f8 ldr r0, [r7, #12] 8012bb4: f7ff fa06 bl 8011fc4 8012bb8: 4603 mov r3, r0 8012bba: 461a mov r2, r3 8012bbc: 687b ldr r3, [r7, #4] 8012bbe: 809a strh r2, [r3, #4] pbuff++; 8012bc0: 68fb ldr r3, [r7, #12] 8012bc2: 3301 adds r3, #1 8012bc4: 60fb str r3, [r7, #12] pbuff++; 8012bc6: 68fb ldr r3, [r7, #12] 8012bc8: 3301 adds r3, #1 8012bca: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 8012bcc: 68f8 ldr r0, [r7, #12] 8012bce: f7ff f9f9 bl 8011fc4 8012bd2: 4603 mov r3, r0 8012bd4: 461a mov r2, r3 8012bd6: 687b ldr r3, [r7, #4] 8012bd8: 80da strh r2, [r3, #6] } 8012bda: bf00 nop 8012bdc: 3710 adds r7, #16 8012bde: 46bd mov sp, r7 8012be0: bd80 pop {r7, pc} 08012be2 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8012be2: b580 push {r7, lr} 8012be4: b082 sub sp, #8 8012be6: af00 add r7, sp, #0 8012be8: 6078 str r0, [r7, #4] 8012bea: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 8012bec: 2180 movs r1, #128 @ 0x80 8012bee: 6878 ldr r0, [r7, #4] 8012bf0: f006 fa34 bl 801905c (void)USBD_LL_StallEP(pdev, 0U); 8012bf4: 2100 movs r1, #0 8012bf6: 6878 ldr r0, [r7, #4] 8012bf8: f006 fa30 bl 801905c } 8012bfc: bf00 nop 8012bfe: 3708 adds r7, #8 8012c00: 46bd mov sp, r7 8012c02: bd80 pop {r7, pc} 08012c04 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8012c04: b580 push {r7, lr} 8012c06: b086 sub sp, #24 8012c08: af00 add r7, sp, #0 8012c0a: 60f8 str r0, [r7, #12] 8012c0c: 60b9 str r1, [r7, #8] 8012c0e: 607a str r2, [r7, #4] uint8_t idx = 0U; 8012c10: 2300 movs r3, #0 8012c12: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8012c14: 68fb ldr r3, [r7, #12] 8012c16: 2b00 cmp r3, #0 8012c18: d042 beq.n 8012ca0 { return; } pdesc = desc; 8012c1a: 68fb ldr r3, [r7, #12] 8012c1c: 613b str r3, [r7, #16] *len = MIN(USBD_MAX_STR_DESC_SIZ, ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U); 8012c1e: 6938 ldr r0, [r7, #16] 8012c20: f000 f842 bl 8012ca8 8012c24: 4603 mov r3, r0 8012c26: 3301 adds r3, #1 8012c28: 005b lsls r3, r3, #1 8012c2a: f5b3 7f00 cmp.w r3, #512 @ 0x200 8012c2e: d808 bhi.n 8012c42 8012c30: 6938 ldr r0, [r7, #16] 8012c32: f000 f839 bl 8012ca8 8012c36: 4603 mov r3, r0 8012c38: 3301 adds r3, #1 8012c3a: b29b uxth r3, r3 8012c3c: 005b lsls r3, r3, #1 8012c3e: b29a uxth r2, r3 8012c40: e001 b.n 8012c46 8012c42: f44f 7200 mov.w r2, #512 @ 0x200 8012c46: 687b ldr r3, [r7, #4] 8012c48: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 8012c4a: 7dfb ldrb r3, [r7, #23] 8012c4c: 68ba ldr r2, [r7, #8] 8012c4e: 4413 add r3, r2 8012c50: 687a ldr r2, [r7, #4] 8012c52: 7812 ldrb r2, [r2, #0] 8012c54: 701a strb r2, [r3, #0] idx++; 8012c56: 7dfb ldrb r3, [r7, #23] 8012c58: 3301 adds r3, #1 8012c5a: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 8012c5c: 7dfb ldrb r3, [r7, #23] 8012c5e: 68ba ldr r2, [r7, #8] 8012c60: 4413 add r3, r2 8012c62: 2203 movs r2, #3 8012c64: 701a strb r2, [r3, #0] idx++; 8012c66: 7dfb ldrb r3, [r7, #23] 8012c68: 3301 adds r3, #1 8012c6a: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8012c6c: e013 b.n 8012c96 { unicode[idx] = *pdesc; 8012c6e: 7dfb ldrb r3, [r7, #23] 8012c70: 68ba ldr r2, [r7, #8] 8012c72: 4413 add r3, r2 8012c74: 693a ldr r2, [r7, #16] 8012c76: 7812 ldrb r2, [r2, #0] 8012c78: 701a strb r2, [r3, #0] pdesc++; 8012c7a: 693b ldr r3, [r7, #16] 8012c7c: 3301 adds r3, #1 8012c7e: 613b str r3, [r7, #16] idx++; 8012c80: 7dfb ldrb r3, [r7, #23] 8012c82: 3301 adds r3, #1 8012c84: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 8012c86: 7dfb ldrb r3, [r7, #23] 8012c88: 68ba ldr r2, [r7, #8] 8012c8a: 4413 add r3, r2 8012c8c: 2200 movs r2, #0 8012c8e: 701a strb r2, [r3, #0] idx++; 8012c90: 7dfb ldrb r3, [r7, #23] 8012c92: 3301 adds r3, #1 8012c94: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8012c96: 693b ldr r3, [r7, #16] 8012c98: 781b ldrb r3, [r3, #0] 8012c9a: 2b00 cmp r3, #0 8012c9c: d1e7 bne.n 8012c6e 8012c9e: e000 b.n 8012ca2 return; 8012ca0: bf00 nop } } 8012ca2: 3718 adds r7, #24 8012ca4: 46bd mov sp, r7 8012ca6: bd80 pop {r7, pc} 08012ca8 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 8012ca8: b480 push {r7} 8012caa: b085 sub sp, #20 8012cac: af00 add r7, sp, #0 8012cae: 6078 str r0, [r7, #4] uint8_t len = 0U; 8012cb0: 2300 movs r3, #0 8012cb2: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 8012cb4: 687b ldr r3, [r7, #4] 8012cb6: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8012cb8: e005 b.n 8012cc6 { len++; 8012cba: 7bfb ldrb r3, [r7, #15] 8012cbc: 3301 adds r3, #1 8012cbe: 73fb strb r3, [r7, #15] pbuff++; 8012cc0: 68bb ldr r3, [r7, #8] 8012cc2: 3301 adds r3, #1 8012cc4: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 8012cc6: 68bb ldr r3, [r7, #8] 8012cc8: 781b ldrb r3, [r3, #0] 8012cca: 2b00 cmp r3, #0 8012ccc: d1f5 bne.n 8012cba } return len; 8012cce: 7bfb ldrb r3, [r7, #15] } 8012cd0: 4618 mov r0, r3 8012cd2: 3714 adds r7, #20 8012cd4: 46bd mov sp, r7 8012cd6: f85d 7b04 ldr.w r7, [sp], #4 8012cda: 4770 bx lr 08012cdc : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8012cdc: b580 push {r7, lr} 8012cde: b084 sub sp, #16 8012ce0: af00 add r7, sp, #0 8012ce2: 60f8 str r0, [r7, #12] 8012ce4: 60b9 str r1, [r7, #8] 8012ce6: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 8012ce8: 68fb ldr r3, [r7, #12] 8012cea: 2202 movs r2, #2 8012cec: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_in[0].total_length = len; 8012cf0: 68fb ldr r3, [r7, #12] 8012cf2: 687a ldr r2, [r7, #4] 8012cf4: 615a str r2, [r3, #20] pdev->ep_in[0].pbuffer = pbuf; 8012cf6: 68fb ldr r3, [r7, #12] 8012cf8: 68ba ldr r2, [r7, #8] 8012cfa: 625a str r2, [r3, #36] @ 0x24 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 8012cfc: 68fb ldr r3, [r7, #12] 8012cfe: 687a ldr r2, [r7, #4] 8012d00: 619a str r2, [r3, #24] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8012d02: 687b ldr r3, [r7, #4] 8012d04: 68ba ldr r2, [r7, #8] 8012d06: 2100 movs r1, #0 8012d08: 68f8 ldr r0, [r7, #12] 8012d0a: f006 fa30 bl 801916e return USBD_OK; 8012d0e: 2300 movs r3, #0 } 8012d10: 4618 mov r0, r3 8012d12: 3710 adds r7, #16 8012d14: 46bd mov sp, r7 8012d16: bd80 pop {r7, pc} 08012d18 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8012d18: b580 push {r7, lr} 8012d1a: b084 sub sp, #16 8012d1c: af00 add r7, sp, #0 8012d1e: 60f8 str r0, [r7, #12] 8012d20: 60b9 str r1, [r7, #8] 8012d22: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8012d24: 687b ldr r3, [r7, #4] 8012d26: 68ba ldr r2, [r7, #8] 8012d28: 2100 movs r1, #0 8012d2a: 68f8 ldr r0, [r7, #12] 8012d2c: f006 fa1f bl 801916e return USBD_OK; 8012d30: 2300 movs r3, #0 } 8012d32: 4618 mov r0, r3 8012d34: 3710 adds r7, #16 8012d36: 46bd mov sp, r7 8012d38: bd80 pop {r7, pc} 08012d3a : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8012d3a: b580 push {r7, lr} 8012d3c: b084 sub sp, #16 8012d3e: af00 add r7, sp, #0 8012d40: 60f8 str r0, [r7, #12] 8012d42: 60b9 str r1, [r7, #8] 8012d44: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_OUT; 8012d46: 68fb ldr r3, [r7, #12] 8012d48: 2203 movs r2, #3 8012d4a: f8c3 2294 str.w r2, [r3, #660] @ 0x294 pdev->ep_out[0].total_length = len; 8012d4e: 68fb ldr r3, [r7, #12] 8012d50: 687a ldr r2, [r7, #4] 8012d52: f8c3 2154 str.w r2, [r3, #340] @ 0x154 pdev->ep_out[0].pbuffer = pbuf; 8012d56: 68fb ldr r3, [r7, #12] 8012d58: 68ba ldr r2, [r7, #8] 8012d5a: f8c3 2164 str.w r2, [r3, #356] @ 0x164 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_out[0].rem_length = 0U; #else pdev->ep_out[0].rem_length = len; 8012d5e: 68fb ldr r3, [r7, #12] 8012d60: 687a ldr r2, [r7, #4] 8012d62: f8c3 2158 str.w r2, [r3, #344] @ 0x158 #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8012d66: 687b ldr r3, [r7, #4] 8012d68: 68ba ldr r2, [r7, #8] 8012d6a: 2100 movs r1, #0 8012d6c: 68f8 ldr r0, [r7, #12] 8012d6e: f006 fa1f bl 80191b0 return USBD_OK; 8012d72: 2300 movs r3, #0 } 8012d74: 4618 mov r0, r3 8012d76: 3710 adds r7, #16 8012d78: 46bd mov sp, r7 8012d7a: bd80 pop {r7, pc} 08012d7c : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8012d7c: b580 push {r7, lr} 8012d7e: b084 sub sp, #16 8012d80: af00 add r7, sp, #0 8012d82: 60f8 str r0, [r7, #12] 8012d84: 60b9 str r1, [r7, #8] 8012d86: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 8012d88: 687b ldr r3, [r7, #4] 8012d8a: 68ba ldr r2, [r7, #8] 8012d8c: 2100 movs r1, #0 8012d8e: 68f8 ldr r0, [r7, #12] 8012d90: f006 fa0e bl 80191b0 return USBD_OK; 8012d94: 2300 movs r3, #0 } 8012d96: 4618 mov r0, r3 8012d98: 3710 adds r7, #16 8012d9a: 46bd mov sp, r7 8012d9c: bd80 pop {r7, pc} 08012d9e : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 8012d9e: b580 push {r7, lr} 8012da0: b082 sub sp, #8 8012da2: af00 add r7, sp, #0 8012da4: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 8012da6: 687b ldr r3, [r7, #4] 8012da8: 2204 movs r2, #4 8012daa: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 8012dae: 2300 movs r3, #0 8012db0: 2200 movs r2, #0 8012db2: 2100 movs r1, #0 8012db4: 6878 ldr r0, [r7, #4] 8012db6: f006 f9da bl 801916e return USBD_OK; 8012dba: 2300 movs r3, #0 } 8012dbc: 4618 mov r0, r3 8012dbe: 3708 adds r7, #8 8012dc0: 46bd mov sp, r7 8012dc2: bd80 pop {r7, pc} 08012dc4 : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 8012dc4: b580 push {r7, lr} 8012dc6: b082 sub sp, #8 8012dc8: af00 add r7, sp, #0 8012dca: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 8012dcc: 687b ldr r3, [r7, #4] 8012dce: 2205 movs r2, #5 8012dd0: f8c3 2294 str.w r2, [r3, #660] @ 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8012dd4: 2300 movs r3, #0 8012dd6: 2200 movs r2, #0 8012dd8: 2100 movs r1, #0 8012dda: 6878 ldr r0, [r7, #4] 8012ddc: f006 f9e8 bl 80191b0 return USBD_OK; 8012de0: 2300 movs r3, #0 } 8012de2: 4618 mov r0, r3 8012de4: 3708 adds r7, #8 8012de6: 46bd mov sp, r7 8012de8: bd80 pop {r7, pc} 08012dea : return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); } SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket ) { 8012dea: b580 push {r7, lr} 8012dec: b088 sub sp, #32 8012dee: af00 add r7, sp, #0 8012df0: 6078 str r0, [r7, #4] * Buffer is large enough to hold command complete without payload */ uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE]; TL_EvtPacket_t * p_rsp; p_rsp = (TL_EvtPacket_t *)local_buffer; 8012df2: f107 030c add.w r3, r7, #12 8012df6: 61fb str r3, [r7, #28] shci_send( SHCI_OPCODE_C2_DEBUG_INIT, sizeof( SHCI_C2_DEBUG_init_Cmd_Param_t ), (uint8_t*)&pCmdPacket->Param, 8012df8: 687b ldr r3, [r7, #4] 8012dfa: f103 020c add.w r2, r3, #12 shci_send( SHCI_OPCODE_C2_DEBUG_INIT, 8012dfe: 69fb ldr r3, [r7, #28] 8012e00: 210f movs r1, #15 8012e02: f64f 4068 movw r0, #64616 @ 0xfc68 8012e06: f000 f935 bl 8013074 p_rsp ); return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); 8012e0a: 69fb ldr r3, [r7, #28] 8012e0c: 330b adds r3, #11 8012e0e: 78db ldrb r3, [r3, #3] } 8012e10: 4618 mov r0, r3 8012e12: 3720 adds r7, #32 8012e14: 46bd mov sp, r7 8012e16: bd80 pop {r7, pc} 08012e18 : return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); } SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket) { 8012e18: b580 push {r7, lr} 8012e1a: b088 sub sp, #32 8012e1c: af00 add r7, sp, #0 8012e1e: 6078 str r0, [r7, #4] * Buffer is large enough to hold command complete without payload */ uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE]; TL_EvtPacket_t * p_rsp; p_rsp = (TL_EvtPacket_t *)local_buffer; 8012e20: f107 030c add.w r3, r7, #12 8012e24: 61fb str r3, [r7, #28] shci_send( SHCI_OPCODE_C2_CONFIG, 8012e26: 69fb ldr r3, [r7, #28] 8012e28: 687a ldr r2, [r7, #4] 8012e2a: 2110 movs r1, #16 8012e2c: f64f 4075 movw r0, #64629 @ 0xfc75 8012e30: f000 f920 bl 8013074 sizeof(SHCI_C2_CONFIG_Cmd_Param_t), (uint8_t*)pCmdPacket, p_rsp ); return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]); 8012e34: 69fb ldr r3, [r7, #28] 8012e36: 330b adds r3, #11 8012e38: 78db ldrb r3, [r3, #3] } 8012e3a: 4618 mov r0, r3 8012e3c: 3720 adds r7, #32 8012e3e: 46bd mov sp, r7 8012e40: bd80 pop {r7, pc} ... 08012e44 : * Local System COMMAND * These commands are NOT sent to the CPU2 */ SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo ) { 8012e44: b480 push {r7} 8012e46: b08b sub sp, #44 @ 0x2c 8012e48: af00 add r7, sp, #0 8012e4a: 6078 str r0, [r7, #4] uint32_t ipccdba = 0; 8012e4c: 2300 movs r3, #0 8012e4e: 613b str r3, [r7, #16] MB_RefTable_t * p_RefTable = NULL; 8012e50: 2300 movs r3, #0 8012e52: 60fb str r3, [r7, #12] uint32_t wireless_firmware_version = 0; 8012e54: 2300 movs r3, #0 8012e56: 627b str r3, [r7, #36] @ 0x24 uint32_t wireless_firmware_memorySize = 0; 8012e58: 2300 movs r3, #0 8012e5a: 623b str r3, [r7, #32] uint32_t wireless_firmware_infoStack = 0; 8012e5c: 2300 movs r3, #0 8012e5e: 61fb str r3, [r7, #28] MB_FUS_DeviceInfoTable_t * p_fus_device_info_table = NULL; 8012e60: 2300 movs r3, #0 8012e62: 60bb str r3, [r7, #8] uint32_t fus_version = 0; 8012e64: 2300 movs r3, #0 8012e66: 61bb str r3, [r7, #24] uint32_t fus_memorySize = 0; 8012e68: 2300 movs r3, #0 8012e6a: 617b str r3, [r7, #20] ipccdba = READ_BIT( FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA ); 8012e6c: 4b4a ldr r3, [pc, #296] @ (8012f98 ) 8012e6e: 6bdb ldr r3, [r3, #60] @ 0x3c 8012e70: f3c3 030d ubfx r3, r3, #0, #14 8012e74: 613b str r3, [r7, #16] /** * The Device Info Table mapping depends on which firmware is running on CPU2. * If the FUS is running on CPU2, FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD shall be written in the table. * Otherwise, it means the Wireless Firmware is running on the CPU2 */ p_fus_device_info_table = (MB_FUS_DeviceInfoTable_t*)(*(uint32_t*)((ipccdba<<2) + SRAM2A_BASE)); 8012e76: 693b ldr r3, [r7, #16] 8012e78: 009b lsls r3, r3, #2 8012e7a: f103 5300 add.w r3, r3, #536870912 @ 0x20000000 8012e7e: f503 3340 add.w r3, r3, #196608 @ 0x30000 8012e82: 681b ldr r3, [r3, #0] 8012e84: 60bb str r3, [r7, #8] if(p_fus_device_info_table->DeviceInfoTableState == FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD) 8012e86: 68bb ldr r3, [r7, #8] 8012e88: 681b ldr r3, [r3, #0] 8012e8a: 4a44 ldr r2, [pc, #272] @ (8012f9c ) 8012e8c: 4293 cmp r3, r2 8012e8e: d10f bne.n 8012eb0 /* The FUS is running on CPU2 */ /** * Retrieve the WirelessFwInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ wireless_firmware_version = p_fus_device_info_table->WirelessStackVersion; 8012e90: 68bb ldr r3, [r7, #8] 8012e92: 695b ldr r3, [r3, #20] 8012e94: 627b str r3, [r7, #36] @ 0x24 wireless_firmware_memorySize = p_fus_device_info_table->WirelessStackMemorySize; 8012e96: 68bb ldr r3, [r7, #8] 8012e98: 699b ldr r3, [r3, #24] 8012e9a: 623b str r3, [r7, #32] wireless_firmware_infoStack = p_fus_device_info_table->WirelessFirmwareBleInfo; 8012e9c: 68bb ldr r3, [r7, #8] 8012e9e: 69db ldr r3, [r3, #28] 8012ea0: 61fb str r3, [r7, #28] /** * Retrieve the FusInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ fus_version = p_fus_device_info_table->FusVersion; 8012ea2: 68bb ldr r3, [r7, #8] 8012ea4: 68db ldr r3, [r3, #12] 8012ea6: 61bb str r3, [r7, #24] fus_memorySize = p_fus_device_info_table->FusMemorySize; 8012ea8: 68bb ldr r3, [r7, #8] 8012eaa: 691b ldr r3, [r3, #16] 8012eac: 617b str r3, [r7, #20] 8012eae: e01a b.n 8012ee6 } else { /* The Wireless Firmware is running on CPU2 */ p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE); 8012eb0: 693b ldr r3, [r7, #16] 8012eb2: 009b lsls r3, r3, #2 8012eb4: f103 5300 add.w r3, r3, #536870912 @ 0x20000000 8012eb8: f503 3340 add.w r3, r3, #196608 @ 0x30000 8012ebc: 60fb str r3, [r7, #12] /** * Retrieve the WirelessFwInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ wireless_firmware_version = p_RefTable->p_device_info_table->WirelessFwInfoTable.Version; 8012ebe: 68fb ldr r3, [r7, #12] 8012ec0: 681b ldr r3, [r3, #0] 8012ec2: 691b ldr r3, [r3, #16] 8012ec4: 627b str r3, [r7, #36] @ 0x24 wireless_firmware_memorySize = p_RefTable->p_device_info_table->WirelessFwInfoTable.MemorySize; 8012ec6: 68fb ldr r3, [r7, #12] 8012ec8: 681b ldr r3, [r3, #0] 8012eca: 695b ldr r3, [r3, #20] 8012ecc: 623b str r3, [r7, #32] wireless_firmware_infoStack = p_RefTable->p_device_info_table->WirelessFwInfoTable.InfoStack; 8012ece: 68fb ldr r3, [r7, #12] 8012ed0: 681b ldr r3, [r3, #0] 8012ed2: 699b ldr r3, [r3, #24] 8012ed4: 61fb str r3, [r7, #28] /** * Retrieve the FusInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ fus_version = p_RefTable->p_device_info_table->FusInfoTable.Version; 8012ed6: 68fb ldr r3, [r7, #12] 8012ed8: 681b ldr r3, [r3, #0] 8012eda: 685b ldr r3, [r3, #4] 8012edc: 61bb str r3, [r7, #24] fus_memorySize = p_RefTable->p_device_info_table->FusInfoTable.MemorySize; 8012ede: 68fb ldr r3, [r7, #12] 8012ee0: 681b ldr r3, [r3, #0] 8012ee2: 689b ldr r3, [r3, #8] 8012ee4: 617b str r3, [r7, #20] /** * Retrieve the WirelessFwInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ pWirelessInfo->VersionMajor = ((wireless_firmware_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET); 8012ee6: 6a7b ldr r3, [r7, #36] @ 0x24 8012ee8: 0e1b lsrs r3, r3, #24 8012eea: b2da uxtb r2, r3 8012eec: 687b ldr r3, [r7, #4] 8012eee: 701a strb r2, [r3, #0] pWirelessInfo->VersionMinor = ((wireless_firmware_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET); 8012ef0: 6a7b ldr r3, [r7, #36] @ 0x24 8012ef2: 0c1b lsrs r3, r3, #16 8012ef4: b2da uxtb r2, r3 8012ef6: 687b ldr r3, [r7, #4] 8012ef8: 705a strb r2, [r3, #1] pWirelessInfo->VersionSub = ((wireless_firmware_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET); 8012efa: 6a7b ldr r3, [r7, #36] @ 0x24 8012efc: 0a1b lsrs r3, r3, #8 8012efe: b2da uxtb r2, r3 8012f00: 687b ldr r3, [r7, #4] 8012f02: 709a strb r2, [r3, #2] pWirelessInfo->VersionBranch = ((wireless_firmware_version & INFO_VERSION_BRANCH_MASK) >> INFO_VERSION_BRANCH_OFFSET); 8012f04: 6a7b ldr r3, [r7, #36] @ 0x24 8012f06: 091b lsrs r3, r3, #4 8012f08: b2db uxtb r3, r3 8012f0a: f003 030f and.w r3, r3, #15 8012f0e: b2da uxtb r2, r3 8012f10: 687b ldr r3, [r7, #4] 8012f12: 70da strb r2, [r3, #3] pWirelessInfo->VersionReleaseType = ((wireless_firmware_version & INFO_VERSION_TYPE_MASK) >> INFO_VERSION_TYPE_OFFSET); 8012f14: 6a7b ldr r3, [r7, #36] @ 0x24 8012f16: b2db uxtb r3, r3 8012f18: f003 030f and.w r3, r3, #15 8012f1c: b2da uxtb r2, r3 8012f1e: 687b ldr r3, [r7, #4] 8012f20: 711a strb r2, [r3, #4] pWirelessInfo->MemorySizeSram2B = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET); 8012f22: 6a3b ldr r3, [r7, #32] 8012f24: 0e1b lsrs r3, r3, #24 8012f26: b2da uxtb r2, r3 8012f28: 687b ldr r3, [r7, #4] 8012f2a: 715a strb r2, [r3, #5] pWirelessInfo->MemorySizeSram2A = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET); 8012f2c: 6a3b ldr r3, [r7, #32] 8012f2e: 0c1b lsrs r3, r3, #16 8012f30: b2da uxtb r2, r3 8012f32: 687b ldr r3, [r7, #4] 8012f34: 719a strb r2, [r3, #6] pWirelessInfo->MemorySizeSram1 = ((wireless_firmware_memorySize & INFO_SIZE_SRAM1_MASK) >> INFO_SIZE_SRAM1_OFFSET); 8012f36: 6a3b ldr r3, [r7, #32] 8012f38: 0a1b lsrs r3, r3, #8 8012f3a: b2da uxtb r2, r3 8012f3c: 687b ldr r3, [r7, #4] 8012f3e: 71da strb r2, [r3, #7] pWirelessInfo->MemorySizeFlash = ((wireless_firmware_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET); 8012f40: 6a3b ldr r3, [r7, #32] 8012f42: b2da uxtb r2, r3 8012f44: 687b ldr r3, [r7, #4] 8012f46: 721a strb r2, [r3, #8] pWirelessInfo->StackType = ((wireless_firmware_infoStack & INFO_STACK_TYPE_MASK) >> INFO_STACK_TYPE_OFFSET); 8012f48: 69fb ldr r3, [r7, #28] 8012f4a: b2da uxtb r2, r3 8012f4c: 687b ldr r3, [r7, #4] 8012f4e: 725a strb r2, [r3, #9] /** * Retrieve the FusInfoTable * This table is stored in RAM at startup during the TL (transport layer) initialization */ pWirelessInfo->FusVersionMajor = ((fus_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET); 8012f50: 69bb ldr r3, [r7, #24] 8012f52: 0e1b lsrs r3, r3, #24 8012f54: b2da uxtb r2, r3 8012f56: 687b ldr r3, [r7, #4] 8012f58: 729a strb r2, [r3, #10] pWirelessInfo->FusVersionMinor = ((fus_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET); 8012f5a: 69bb ldr r3, [r7, #24] 8012f5c: 0c1b lsrs r3, r3, #16 8012f5e: b2da uxtb r2, r3 8012f60: 687b ldr r3, [r7, #4] 8012f62: 72da strb r2, [r3, #11] pWirelessInfo->FusVersionSub = ((fus_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET); 8012f64: 69bb ldr r3, [r7, #24] 8012f66: 0a1b lsrs r3, r3, #8 8012f68: b2da uxtb r2, r3 8012f6a: 687b ldr r3, [r7, #4] 8012f6c: 731a strb r2, [r3, #12] pWirelessInfo->FusMemorySizeSram2B = ((fus_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET); 8012f6e: 697b ldr r3, [r7, #20] 8012f70: 0e1b lsrs r3, r3, #24 8012f72: b2da uxtb r2, r3 8012f74: 687b ldr r3, [r7, #4] 8012f76: 735a strb r2, [r3, #13] pWirelessInfo->FusMemorySizeSram2A = ((fus_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET); 8012f78: 697b ldr r3, [r7, #20] 8012f7a: 0c1b lsrs r3, r3, #16 8012f7c: b2da uxtb r2, r3 8012f7e: 687b ldr r3, [r7, #4] 8012f80: 739a strb r2, [r3, #14] pWirelessInfo->FusMemorySizeFlash = ((fus_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET); 8012f82: 697b ldr r3, [r7, #20] 8012f84: b2da uxtb r2, r3 8012f86: 687b ldr r3, [r7, #4] 8012f88: 73da strb r2, [r3, #15] return (SHCI_Success); 8012f8a: 2300 movs r3, #0 } 8012f8c: 4618 mov r0, r3 8012f8e: 372c adds r7, #44 @ 0x2c 8012f90: 46bd mov sp, r7 8012f92: f85d 7b04 ldr.w r7, [sp], #4 8012f96: 4770 bx lr 8012f98: 58004000 .word 0x58004000 8012f9c: a94656b9 .word 0xa94656b9 08012fa0 : static void TlUserEvtReceived(TL_EvtPacket_t *shcievt); static void TlInit( TL_CmdPacket_t * p_cmdbuffer ); /* Interface ------- ---------------------------------------------------------*/ void shci_init(void(* UserEvtRx)(void* pData), void* pConf) { 8012fa0: b580 push {r7, lr} 8012fa2: b082 sub sp, #8 8012fa4: af00 add r7, sp, #0 8012fa6: 6078 str r0, [r7, #4] 8012fa8: 6039 str r1, [r7, #0] StatusNotCallBackFunction = ((SHCI_TL_HciInitConf_t *)pConf)->StatusNotCallBack; 8012faa: 683b ldr r3, [r7, #0] 8012fac: 685b ldr r3, [r3, #4] 8012fae: 4a08 ldr r2, [pc, #32] @ (8012fd0 ) 8012fb0: 6013 str r3, [r2, #0] shciContext.UserEvtRx = UserEvtRx; 8012fb2: 4a08 ldr r2, [pc, #32] @ (8012fd4 ) 8012fb4: 687b ldr r3, [r7, #4] 8012fb6: 61d3 str r3, [r2, #28] shci_register_io_bus (&shciContext.io); 8012fb8: 4806 ldr r0, [pc, #24] @ (8012fd4 ) 8012fba: f000 f915 bl 80131e8 TlInit((TL_CmdPacket_t *)(((SHCI_TL_HciInitConf_t *)pConf)->p_cmdbuffer)); 8012fbe: 683b ldr r3, [r7, #0] 8012fc0: 681b ldr r3, [r3, #0] 8012fc2: 4618 mov r0, r3 8012fc4: f000 f898 bl 80130f8 return; 8012fc8: bf00 nop } 8012fca: 3708 adds r7, #8 8012fcc: 46bd mov sp, r7 8012fce: bd80 pop {r7, pc} 8012fd0: 200007a8 .word 0x200007a8 8012fd4: 20000788 .word 0x20000788 08012fd8 : void shci_user_evt_proc(void) { 8012fd8: b580 push {r7, lr} 8012fda: b084 sub sp, #16 8012fdc: af00 add r7, sp, #0 /** * It is more secure to use LST_remove_head()/LST_insert_head() compare to LST_get_next_node()/LST_remove_node() * in case the user overwrite the header where the next/prev pointers are located */ if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable)) 8012fde: 4822 ldr r0, [pc, #136] @ (8013068 ) 8012fe0: f000 fb52 bl 8013688 8012fe4: 4603 mov r3, r0 8012fe6: 2b00 cmp r3, #0 8012fe8: d12b bne.n 8013042 8012fea: 4b20 ldr r3, [pc, #128] @ (801306c ) 8012fec: 781b ldrb r3, [r3, #0] 8012fee: 2b00 cmp r3, #0 8012ff0: d027 beq.n 8013042 { LST_remove_head ( &SHciAsynchEventQueue, (tListNode **)&phcievtbuffer ); 8012ff2: f107 030c add.w r3, r7, #12 8012ff6: 4619 mov r1, r3 8012ff8: 481b ldr r0, [pc, #108] @ (8013068 ) 8012ffa: f000 fbd4 bl 80137a6 if (shciContext.UserEvtRx != NULL) 8012ffe: 4b1c ldr r3, [pc, #112] @ (8013070 ) 8013000: 69db ldr r3, [r3, #28] 8013002: 2b00 cmp r3, #0 8013004: d00c beq.n 8013020 { UserEvtRxParam.pckt = phcievtbuffer; 8013006: 68fb ldr r3, [r7, #12] 8013008: 60bb str r3, [r7, #8] UserEvtRxParam.status = SHCI_TL_UserEventFlow_Enable; 801300a: 2301 movs r3, #1 801300c: 713b strb r3, [r7, #4] shciContext.UserEvtRx((void *)&UserEvtRxParam); 801300e: 4b18 ldr r3, [pc, #96] @ (8013070 ) 8013010: 69db ldr r3, [r3, #28] 8013012: 1d3a adds r2, r7, #4 8013014: 4610 mov r0, r2 8013016: 4798 blx r3 SHCI_TL_UserEventFlow = UserEvtRxParam.status; 8013018: 793a ldrb r2, [r7, #4] 801301a: 4b14 ldr r3, [pc, #80] @ (801306c ) 801301c: 701a strb r2, [r3, #0] 801301e: e002 b.n 8013026 } else { SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable; 8013020: 4b12 ldr r3, [pc, #72] @ (801306c ) 8013022: 2201 movs r2, #1 8013024: 701a strb r2, [r3, #0] } if(SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable) 8013026: 4b11 ldr r3, [pc, #68] @ (801306c ) 8013028: 781b ldrb r3, [r3, #0] 801302a: 2b00 cmp r3, #0 801302c: d004 beq.n 8013038 { TL_MM_EvtDone( phcievtbuffer ); 801302e: 68fb ldr r3, [r7, #12] 8013030: 4618 mov r0, r3 8013032: f000 fa25 bl 8013480 8013036: e004 b.n 8013042 else { /** * put back the event in the queue */ LST_insert_head ( &SHciAsynchEventQueue, (tListNode *)phcievtbuffer ); 8013038: 68fb ldr r3, [r7, #12] 801303a: 4619 mov r1, r3 801303c: 480a ldr r0, [pc, #40] @ (8013068 ) 801303e: f000 fb45 bl 80136cc } } if((LST_is_empty(&SHciAsynchEventQueue) == FALSE) && (SHCI_TL_UserEventFlow != SHCI_TL_UserEventFlow_Disable)) 8013042: 4809 ldr r0, [pc, #36] @ (8013068 ) 8013044: f000 fb20 bl 8013688 8013048: 4603 mov r3, r0 801304a: 2b00 cmp r3, #0 801304c: d107 bne.n 801305e 801304e: 4b07 ldr r3, [pc, #28] @ (801306c ) 8013050: 781b ldrb r3, [r3, #0] 8013052: 2b00 cmp r3, #0 8013054: d003 beq.n 801305e { shci_notify_asynch_evt((void*) &SHciAsynchEventQueue); 8013056: 4804 ldr r0, [pc, #16] @ (8013068 ) 8013058: f7ef fb04 bl 8002664 } return; 801305c: bf00 nop 801305e: bf00 nop } 8013060: 3710 adds r7, #16 8013062: 46bd mov sp, r7 8013064: bd80 pop {r7, pc} 8013066: bf00 nop 8013068: 200002d8 .word 0x200002d8 801306c: 200002e8 .word 0x200002e8 8013070: 20000788 .word 0x20000788 08013074 : return; } void shci_send( uint16_t cmd_code, uint8_t len_cmd_payload, uint8_t * p_cmd_payload, TL_EvtPacket_t * p_rsp ) { 8013074: b580 push {r7, lr} 8013076: b084 sub sp, #16 8013078: af00 add r7, sp, #0 801307a: 60ba str r2, [r7, #8] 801307c: 607b str r3, [r7, #4] 801307e: 4603 mov r3, r0 8013080: 81fb strh r3, [r7, #14] 8013082: 460b mov r3, r1 8013084: 737b strb r3, [r7, #13] Cmd_SetStatus(SHCI_TL_CmdBusy); 8013086: 2000 movs r0, #0 8013088: f000 f868 bl 801315c pCmdBuffer->cmdserial.cmd.cmdcode = cmd_code; 801308c: 4b17 ldr r3, [pc, #92] @ (80130ec ) 801308e: 681b ldr r3, [r3, #0] 8013090: 89fa ldrh r2, [r7, #14] 8013092: f8a3 2009 strh.w r2, [r3, #9] pCmdBuffer->cmdserial.cmd.plen = len_cmd_payload; 8013096: 4b15 ldr r3, [pc, #84] @ (80130ec ) 8013098: 681b ldr r3, [r3, #0] 801309a: 7b7a ldrb r2, [r7, #13] 801309c: 72da strb r2, [r3, #11] memcpy(pCmdBuffer->cmdserial.cmd.payload, p_cmd_payload, len_cmd_payload ); 801309e: 4b13 ldr r3, [pc, #76] @ (80130ec ) 80130a0: 681b ldr r3, [r3, #0] 80130a2: 330c adds r3, #12 80130a4: 7b7a ldrb r2, [r7, #13] 80130a6: 68b9 ldr r1, [r7, #8] 80130a8: 4618 mov r0, r3 80130aa: f007 f9f8 bl 801a49e CmdRspStatusFlag = SHCI_TL_CMD_RESP_WAIT; 80130ae: 4b10 ldr r3, [pc, #64] @ (80130f0 ) 80130b0: 2201 movs r2, #1 80130b2: 701a strb r2, [r3, #0] shciContext.io.Send(0,0); 80130b4: 4b0f ldr r3, [pc, #60] @ (80130f4 ) 80130b6: 691b ldr r3, [r3, #16] 80130b8: 2100 movs r1, #0 80130ba: 2000 movs r0, #0 80130bc: 4798 blx r3 shci_cmd_resp_wait(SHCI_TL_DEFAULT_TIMEOUT); 80130be: f248 00e8 movw r0, #33000 @ 0x80e8 80130c2: f7ef faef bl 80026a4 /** * The command complete of a system command does not have the header * It starts immediately with the evtserial field */ memcpy( &(p_rsp->evtserial), pCmdBuffer, ((TL_EvtSerial_t*)pCmdBuffer)->evt.plen + TL_EVT_HDR_SIZE ); 80130c6: 687b ldr r3, [r7, #4] 80130c8: f103 0008 add.w r0, r3, #8 80130cc: 4b07 ldr r3, [pc, #28] @ (80130ec ) 80130ce: 6819 ldr r1, [r3, #0] 80130d0: 4b06 ldr r3, [pc, #24] @ (80130ec ) 80130d2: 681b ldr r3, [r3, #0] 80130d4: 789b ldrb r3, [r3, #2] 80130d6: 3303 adds r3, #3 80130d8: 461a mov r2, r3 80130da: f007 f9e0 bl 801a49e Cmd_SetStatus(SHCI_TL_CmdAvailable); 80130de: 2001 movs r0, #1 80130e0: f000 f83c bl 801315c return; 80130e4: bf00 nop } 80130e6: 3710 adds r7, #16 80130e8: 46bd mov sp, r7 80130ea: bd80 pop {r7, pc} 80130ec: 200002e4 .word 0x200002e4 80130f0: 200007ac .word 0x200007ac 80130f4: 20000788 .word 0x20000788 080130f8 : /* Private functions ---------------------------------------------------------*/ static void TlInit( TL_CmdPacket_t * p_cmdbuffer ) { 80130f8: b580 push {r7, lr} 80130fa: b086 sub sp, #24 80130fc: af00 add r7, sp, #0 80130fe: 6078 str r0, [r7, #4] TL_SYS_InitConf_t Conf; pCmdBuffer = p_cmdbuffer; 8013100: 4a10 ldr r2, [pc, #64] @ (8013144 ) 8013102: 687b ldr r3, [r7, #4] 8013104: 6013 str r3, [r2, #0] LST_init_head (&SHciAsynchEventQueue); 8013106: 4810 ldr r0, [pc, #64] @ (8013148 ) 8013108: f000 faae bl 8013668 Cmd_SetStatus(SHCI_TL_CmdAvailable); 801310c: 2001 movs r0, #1 801310e: f000 f825 bl 801315c SHCI_TL_UserEventFlow = SHCI_TL_UserEventFlow_Enable; 8013112: 4b0e ldr r3, [pc, #56] @ (801314c ) 8013114: 2201 movs r2, #1 8013116: 701a strb r2, [r3, #0] /* Initialize low level driver */ if (shciContext.io.Init) 8013118: 4b0d ldr r3, [pc, #52] @ (8013150 ) 801311a: 681b ldr r3, [r3, #0] 801311c: 2b00 cmp r3, #0 801311e: d00c beq.n 801313a { Conf.p_cmdbuffer = (uint8_t *)p_cmdbuffer; 8013120: 687b ldr r3, [r7, #4] 8013122: 617b str r3, [r7, #20] Conf.IoBusCallBackCmdEvt = TlCmdEvtReceived; 8013124: 4b0b ldr r3, [pc, #44] @ (8013154 ) 8013126: 60fb str r3, [r7, #12] Conf.IoBusCallBackUserEvt = TlUserEvtReceived; 8013128: 4b0b ldr r3, [pc, #44] @ (8013158 ) 801312a: 613b str r3, [r7, #16] shciContext.io.Init(&Conf); 801312c: 4b08 ldr r3, [pc, #32] @ (8013150 ) 801312e: 681b ldr r3, [r3, #0] 8013130: f107 020c add.w r2, r7, #12 8013134: 4610 mov r0, r2 8013136: 4798 blx r3 } return; 8013138: bf00 nop 801313a: bf00 nop } 801313c: 3718 adds r7, #24 801313e: 46bd mov sp, r7 8013140: bd80 pop {r7, pc} 8013142: bf00 nop 8013144: 200002e4 .word 0x200002e4 8013148: 200002d8 .word 0x200002d8 801314c: 200002e8 .word 0x200002e8 8013150: 20000788 .word 0x20000788 8013154: 080131ad .word 0x080131ad 8013158: 080131c5 .word 0x080131c5 0801315c : static void Cmd_SetStatus(SHCI_TL_CmdStatus_t shcicmdstatus) { 801315c: b580 push {r7, lr} 801315e: b082 sub sp, #8 8013160: af00 add r7, sp, #0 8013162: 4603 mov r3, r0 8013164: 71fb strb r3, [r7, #7] if(shcicmdstatus == SHCI_TL_CmdBusy) 8013166: 79fb ldrb r3, [r7, #7] 8013168: 2b00 cmp r3, #0 801316a: d10b bne.n 8013184 { if(StatusNotCallBackFunction != 0) 801316c: 4b0d ldr r3, [pc, #52] @ (80131a4 ) 801316e: 681b ldr r3, [r3, #0] 8013170: 2b00 cmp r3, #0 8013172: d003 beq.n 801317c { StatusNotCallBackFunction( SHCI_TL_CmdBusy ); 8013174: 4b0b ldr r3, [pc, #44] @ (80131a4 ) 8013176: 681b ldr r3, [r3, #0] 8013178: 2000 movs r0, #0 801317a: 4798 blx r3 } SHCICmdStatus = SHCI_TL_CmdBusy; 801317c: 4b0a ldr r3, [pc, #40] @ (80131a8 ) 801317e: 2200 movs r2, #0 8013180: 701a strb r2, [r3, #0] { StatusNotCallBackFunction( SHCI_TL_CmdAvailable ); } } return; 8013182: e00b b.n 801319c SHCICmdStatus = SHCI_TL_CmdAvailable; 8013184: 4b08 ldr r3, [pc, #32] @ (80131a8 ) 8013186: 2201 movs r2, #1 8013188: 701a strb r2, [r3, #0] if(StatusNotCallBackFunction != 0) 801318a: 4b06 ldr r3, [pc, #24] @ (80131a4 ) 801318c: 681b ldr r3, [r3, #0] 801318e: 2b00 cmp r3, #0 8013190: d004 beq.n 801319c StatusNotCallBackFunction( SHCI_TL_CmdAvailable ); 8013192: 4b04 ldr r3, [pc, #16] @ (80131a4 ) 8013194: 681b ldr r3, [r3, #0] 8013196: 2001 movs r0, #1 8013198: 4798 blx r3 return; 801319a: bf00 nop 801319c: bf00 nop } 801319e: 3708 adds r7, #8 80131a0: 46bd mov sp, r7 80131a2: bd80 pop {r7, pc} 80131a4: 200007a8 .word 0x200007a8 80131a8: 200002e0 .word 0x200002e0 080131ac : static void TlCmdEvtReceived(TL_EvtPacket_t *shcievt) { 80131ac: b580 push {r7, lr} 80131ae: b082 sub sp, #8 80131b0: af00 add r7, sp, #0 80131b2: 6078 str r0, [r7, #4] (void)(shcievt); shci_cmd_resp_release(0); /**< Notify the application the Cmd response has been received */ 80131b4: 2000 movs r0, #0 80131b6: f7ef fa65 bl 8002684 return; 80131ba: bf00 nop } 80131bc: 3708 adds r7, #8 80131be: 46bd mov sp, r7 80131c0: bd80 pop {r7, pc} ... 080131c4 : static void TlUserEvtReceived(TL_EvtPacket_t *shcievt) { 80131c4: b580 push {r7, lr} 80131c6: b082 sub sp, #8 80131c8: af00 add r7, sp, #0 80131ca: 6078 str r0, [r7, #4] LST_insert_tail(&SHciAsynchEventQueue, (tListNode *)shcievt); 80131cc: 6879 ldr r1, [r7, #4] 80131ce: 4805 ldr r0, [pc, #20] @ (80131e4 ) 80131d0: f000 faa2 bl 8013718 shci_notify_asynch_evt((void*) &SHciAsynchEventQueue); /**< Notify the application a full HCI event has been received */ 80131d4: 4803 ldr r0, [pc, #12] @ (80131e4 ) 80131d6: f7ef fa45 bl 8002664 return; 80131da: bf00 nop } 80131dc: 3708 adds r7, #8 80131de: 46bd mov sp, r7 80131e0: bd80 pop {r7, pc} 80131e2: bf00 nop 80131e4: 200002d8 .word 0x200002d8 080131e8 : #include "shci_tl.h" #include "tl.h" void shci_register_io_bus(tSHciIO* fops) { 80131e8: b480 push {r7} 80131ea: b083 sub sp, #12 80131ec: af00 add r7, sp, #0 80131ee: 6078 str r0, [r7, #4] /* Register IO bus services */ fops->Init = TL_SYS_Init; 80131f0: 687b ldr r3, [r7, #4] 80131f2: 4a05 ldr r2, [pc, #20] @ (8013208 ) 80131f4: 601a str r2, [r3, #0] fops->Send = TL_SYS_SendCmd; 80131f6: 687b ldr r3, [r7, #4] 80131f8: 4a04 ldr r2, [pc, #16] @ (801320c ) 80131fa: 611a str r2, [r3, #16] return; 80131fc: bf00 nop } 80131fe: 370c adds r7, #12 8013200: 46bd mov sp, r7 8013202: f85d 7b04 ldr.w r7, [sp], #4 8013206: 4770 bx lr 8013208: 0801330d .word 0x0801330d 801320c: 08013361 .word 0x08013361 08013210 : /****************************************************************************** * GENERAL - refer to AN5289 for functions description. ******************************************************************************/ void TL_Enable( void ) { 8013210: b580 push {r7, lr} 8013212: af00 add r7, sp, #0 HW_IPCC_Enable(); 8013214: f005 f9f6 bl 8018604 return; 8013218: bf00 nop } 801321a: bd80 pop {r7, pc} 0801321c : void TL_Init( void ) { 801321c: b580 push {r7, lr} 801321e: af00 add r7, sp, #0 TL_RefTable.p_device_info_table = &TL_DeviceInfoTable; 8013220: 4b10 ldr r3, [pc, #64] @ (8013264 ) 8013222: 4a11 ldr r2, [pc, #68] @ (8013268 ) 8013224: 601a str r2, [r3, #0] TL_RefTable.p_ble_table = &TL_BleTable; 8013226: 4b0f ldr r3, [pc, #60] @ (8013264 ) 8013228: 4a10 ldr r2, [pc, #64] @ (801326c ) 801322a: 605a str r2, [r3, #4] TL_RefTable.p_thread_table = &TL_ThreadTable; 801322c: 4b0d ldr r3, [pc, #52] @ (8013264 ) 801322e: 4a10 ldr r2, [pc, #64] @ (8013270 ) 8013230: 609a str r2, [r3, #8] TL_RefTable.p_lld_tests_table = &TL_LldTestsTable; 8013232: 4b0c ldr r3, [pc, #48] @ (8013264 ) 8013234: 4a0f ldr r2, [pc, #60] @ (8013274 ) 8013236: 621a str r2, [r3, #32] TL_RefTable.p_ble_lld_table = &TL_BleLldTable; 8013238: 4b0a ldr r3, [pc, #40] @ (8013264 ) 801323a: 4a0f ldr r2, [pc, #60] @ (8013278 ) 801323c: 625a str r2, [r3, #36] @ 0x24 TL_RefTable.p_sys_table = &TL_SysTable; 801323e: 4b09 ldr r3, [pc, #36] @ (8013264 ) 8013240: 4a0e ldr r2, [pc, #56] @ (801327c ) 8013242: 60da str r2, [r3, #12] TL_RefTable.p_mem_manager_table = &TL_MemManagerTable; 8013244: 4b07 ldr r3, [pc, #28] @ (8013264 ) 8013246: 4a0e ldr r2, [pc, #56] @ (8013280 ) 8013248: 611a str r2, [r3, #16] TL_RefTable.p_traces_table = &TL_TracesTable; 801324a: 4b06 ldr r3, [pc, #24] @ (8013264 ) 801324c: 4a0d ldr r2, [pc, #52] @ (8013284 ) 801324e: 615a str r2, [r3, #20] TL_RefTable.p_mac_802_15_4_table = &TL_Mac_802_15_4_Table; 8013250: 4b04 ldr r3, [pc, #16] @ (8013264 ) 8013252: 4a0d ldr r2, [pc, #52] @ (8013288 ) 8013254: 619a str r2, [r3, #24] TL_RefTable.p_zigbee_table = &TL_Zigbee_Table; 8013256: 4b03 ldr r3, [pc, #12] @ (8013264 ) 8013258: 4a0c ldr r2, [pc, #48] @ (801328c ) 801325a: 61da str r2, [r3, #28] HW_IPCC_Init(); 801325c: f005 f9e6 bl 801862c return; 8013260: bf00 nop } 8013262: bd80 pop {r7, pc} 8013264: 20030000 .word 0x20030000 8013268: 20030028 .word 0x20030028 801326c: 20030048 .word 0x20030048 8013270: 20030058 .word 0x20030058 8013274: 20030068 .word 0x20030068 8013278: 20030070 .word 0x20030070 801327c: 20030078 .word 0x20030078 8013280: 20030080 .word 0x20030080 8013284: 2003009c .word 0x2003009c 8013288: 200300a0 .word 0x200300a0 801328c: 200300ac .word 0x200300ac 08013290 : return 0; } void HW_IPCC_BLE_RxEvtNot(void) { 8013290: b580 push {r7, lr} 8013292: b082 sub sp, #8 8013294: af00 add r7, sp, #0 TL_EvtPacket_t *phcievt; while(LST_is_empty(&EvtQueue) == FALSE) 8013296: e01c b.n 80132d2 { LST_remove_head (&EvtQueue, (tListNode **)&phcievt); 8013298: 1d3b adds r3, r7, #4 801329a: 4619 mov r1, r3 801329c: 4812 ldr r0, [pc, #72] @ (80132e8 ) 801329e: f000 fa82 bl 80137a6 if ( ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CS_OPCODE) || ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CC_OPCODE ) ) 80132a2: 687b ldr r3, [r7, #4] 80132a4: 7a5b ldrb r3, [r3, #9] 80132a6: 2b0f cmp r3, #15 80132a8: d003 beq.n 80132b2 80132aa: 687b ldr r3, [r7, #4] 80132ac: 7a5b ldrb r3, [r3, #9] 80132ae: 2b0e cmp r3, #14 80132b0: d105 bne.n 80132be { OutputDbgTrace(TL_MB_BLE_CMD_RSP, (uint8_t*)phcievt); 80132b2: 687b ldr r3, [r7, #4] 80132b4: 4619 mov r1, r3 80132b6: 2002 movs r0, #2 80132b8: f000 f950 bl 801355c 80132bc: e004 b.n 80132c8 } else { OutputDbgTrace(TL_MB_BLE_ASYNCH_EVT, (uint8_t*)phcievt); 80132be: 687b ldr r3, [r7, #4] 80132c0: 4619 mov r1, r3 80132c2: 2005 movs r0, #5 80132c4: f000 f94a bl 801355c } BLE_IoBusEvtCallBackFunction(phcievt); 80132c8: 4b08 ldr r3, [pc, #32] @ (80132ec ) 80132ca: 681b ldr r3, [r3, #0] 80132cc: 687a ldr r2, [r7, #4] 80132ce: 4610 mov r0, r2 80132d0: 4798 blx r3 while(LST_is_empty(&EvtQueue) == FALSE) 80132d2: 4805 ldr r0, [pc, #20] @ (80132e8 ) 80132d4: f000 f9d8 bl 8013688 80132d8: 4603 mov r3, r0 80132da: 2b00 cmp r3, #0 80132dc: d0dc beq.n 8013298 } return; 80132de: bf00 nop } 80132e0: 3708 adds r7, #8 80132e2: 46bd mov sp, r7 80132e4: bd80 pop {r7, pc} 80132e6: bf00 nop 80132e8: 200300c8 .word 0x200300c8 80132ec: 200007b8 .word 0x200007b8 080132f0 : return 0; } void HW_IPCC_BLE_AclDataAckNot(void) { 80132f0: b580 push {r7, lr} 80132f2: af00 add r7, sp, #0 OutputDbgTrace(TL_MB_ACL_DATA_RSP, (uint8_t*)NULL); 80132f4: 2100 movs r1, #0 80132f6: 2004 movs r0, #4 80132f8: f000 f930 bl 801355c BLE_IoBusAclDataTxAck( ); 80132fc: 4b02 ldr r3, [pc, #8] @ (8013308 ) 80132fe: 681b ldr r3, [r3, #0] 8013300: 4798 blx r3 return; 8013302: bf00 nop } 8013304: bd80 pop {r7, pc} 8013306: bf00 nop 8013308: 200007bc .word 0x200007bc 0801330c : /****************************************************************************** * SYSTEM ******************************************************************************/ int32_t TL_SYS_Init( void* pConf ) { 801330c: b580 push {r7, lr} 801330e: b084 sub sp, #16 8013310: af00 add r7, sp, #0 8013312: 6078 str r0, [r7, #4] MB_SysTable_t * p_systable; TL_SYS_InitConf_t *pInitHciConf = (TL_SYS_InitConf_t *) pConf; 8013314: 687b ldr r3, [r7, #4] 8013316: 60fb str r3, [r7, #12] LST_init_head (&SystemEvtQueue); 8013318: 480d ldr r0, [pc, #52] @ (8013350 ) 801331a: f000 f9a5 bl 8013668 p_systable = TL_RefTable.p_sys_table; 801331e: 4b0d ldr r3, [pc, #52] @ (8013354 ) 8013320: 68db ldr r3, [r3, #12] 8013322: 60bb str r3, [r7, #8] p_systable->pcmd_buffer = pInitHciConf->p_cmdbuffer; 8013324: 68fb ldr r3, [r7, #12] 8013326: 689a ldr r2, [r3, #8] 8013328: 68bb ldr r3, [r7, #8] 801332a: 601a str r2, [r3, #0] p_systable->sys_queue = (uint8_t*)&SystemEvtQueue; 801332c: 68bb ldr r3, [r7, #8] 801332e: 4a08 ldr r2, [pc, #32] @ (8013350 ) 8013330: 605a str r2, [r3, #4] HW_IPCC_SYS_Init(); 8013332: f005 f9b9 bl 80186a8 SYS_CMD_IoBusCallBackFunction = pInitHciConf->IoBusCallBackCmdEvt; 8013336: 68fb ldr r3, [r7, #12] 8013338: 681b ldr r3, [r3, #0] 801333a: 4a07 ldr r2, [pc, #28] @ (8013358 ) 801333c: 6013 str r3, [r2, #0] SYS_EVT_IoBusCallBackFunction = pInitHciConf->IoBusCallBackUserEvt; 801333e: 68fb ldr r3, [r7, #12] 8013340: 685b ldr r3, [r3, #4] 8013342: 4a06 ldr r2, [pc, #24] @ (801335c ) 8013344: 6013 str r3, [r2, #0] return 0; 8013346: 2300 movs r3, #0 } 8013348: 4618 mov r0, r3 801334a: 3710 adds r7, #16 801334c: 46bd mov sp, r7 801334e: bd80 pop {r7, pc} 8013350: 200300d0 .word 0x200300d0 8013354: 20030000 .word 0x20030000 8013358: 200007c0 .word 0x200007c0 801335c: 200007c4 .word 0x200007c4 08013360 : int32_t TL_SYS_SendCmd( uint8_t* buffer, uint16_t size ) { 8013360: b580 push {r7, lr} 8013362: b082 sub sp, #8 8013364: af00 add r7, sp, #0 8013366: 6078 str r0, [r7, #4] 8013368: 460b mov r3, r1 801336a: 807b strh r3, [r7, #2] (void)(buffer); (void)(size); ((TL_CmdPacket_t *)(TL_RefTable.p_sys_table->pcmd_buffer))->cmdserial.type = TL_SYSCMD_PKT_TYPE; 801336c: 4b09 ldr r3, [pc, #36] @ (8013394 ) 801336e: 68db ldr r3, [r3, #12] 8013370: 681b ldr r3, [r3, #0] 8013372: 2210 movs r2, #16 8013374: 721a strb r2, [r3, #8] OutputDbgTrace(TL_MB_SYS_CMD, TL_RefTable.p_sys_table->pcmd_buffer); 8013376: 4b07 ldr r3, [pc, #28] @ (8013394 ) 8013378: 68db ldr r3, [r3, #12] 801337a: 681b ldr r3, [r3, #0] 801337c: 4619 mov r1, r3 801337e: 2006 movs r0, #6 8013380: f000 f8ec bl 801355c HW_IPCC_SYS_SendCmd(); 8013384: f005 f9aa bl 80186dc return 0; 8013388: 2300 movs r3, #0 } 801338a: 4618 mov r0, r3 801338c: 3708 adds r7, #8 801338e: 46bd mov sp, r7 8013390: bd80 pop {r7, pc} 8013392: bf00 nop 8013394: 20030000 .word 0x20030000 08013398 : void HW_IPCC_SYS_CmdEvtNot(void) { 8013398: b580 push {r7, lr} 801339a: af00 add r7, sp, #0 OutputDbgTrace(TL_MB_SYS_CMD_RSP, (uint8_t*)(TL_RefTable.p_sys_table->pcmd_buffer) ); 801339c: 4b07 ldr r3, [pc, #28] @ (80133bc ) 801339e: 68db ldr r3, [r3, #12] 80133a0: 681b ldr r3, [r3, #0] 80133a2: 4619 mov r1, r3 80133a4: 2007 movs r0, #7 80133a6: f000 f8d9 bl 801355c SYS_CMD_IoBusCallBackFunction( (TL_EvtPacket_t*)(TL_RefTable.p_sys_table->pcmd_buffer) ); 80133aa: 4b05 ldr r3, [pc, #20] @ (80133c0 ) 80133ac: 681b ldr r3, [r3, #0] 80133ae: 4a03 ldr r2, [pc, #12] @ (80133bc ) 80133b0: 68d2 ldr r2, [r2, #12] 80133b2: 6812 ldr r2, [r2, #0] 80133b4: 4610 mov r0, r2 80133b6: 4798 blx r3 return; 80133b8: bf00 nop } 80133ba: bd80 pop {r7, pc} 80133bc: 20030000 .word 0x20030000 80133c0: 200007c0 .word 0x200007c0 080133c4 : void HW_IPCC_SYS_EvtNot( void ) { 80133c4: b580 push {r7, lr} 80133c6: b082 sub sp, #8 80133c8: af00 add r7, sp, #0 TL_EvtPacket_t *p_evt; while(LST_is_empty(&SystemEvtQueue) == FALSE) 80133ca: e00e b.n 80133ea { LST_remove_head (&SystemEvtQueue, (tListNode **)&p_evt); 80133cc: 1d3b adds r3, r7, #4 80133ce: 4619 mov r1, r3 80133d0: 480b ldr r0, [pc, #44] @ (8013400 ) 80133d2: f000 f9e8 bl 80137a6 OutputDbgTrace(TL_MB_SYS_ASYNCH_EVT, (uint8_t*)p_evt ); 80133d6: 687b ldr r3, [r7, #4] 80133d8: 4619 mov r1, r3 80133da: 2008 movs r0, #8 80133dc: f000 f8be bl 801355c SYS_EVT_IoBusCallBackFunction( p_evt ); 80133e0: 4b08 ldr r3, [pc, #32] @ (8013404 ) 80133e2: 681b ldr r3, [r3, #0] 80133e4: 687a ldr r2, [r7, #4] 80133e6: 4610 mov r0, r2 80133e8: 4798 blx r3 while(LST_is_empty(&SystemEvtQueue) == FALSE) 80133ea: 4805 ldr r0, [pc, #20] @ (8013400 ) 80133ec: f000 f94c bl 8013688 80133f0: 4603 mov r3, r0 80133f2: 2b00 cmp r3, #0 80133f4: d0ea beq.n 80133cc } return; 80133f6: bf00 nop } 80133f8: 3708 adds r7, #8 80133fa: 46bd mov sp, r7 80133fc: bd80 pop {r7, pc} 80133fe: bf00 nop 8013400: 200300d0 .word 0x200300d0 8013404: 200007c4 .word 0x200007c4 08013408 : /****************************************************************************** * MEMORY MANAGER ******************************************************************************/ void TL_MM_Init( TL_MM_Config_t *p_Config ) { 8013408: b580 push {r7, lr} 801340a: b082 sub sp, #8 801340c: af00 add r7, sp, #0 801340e: 6078 str r0, [r7, #4] static MB_MemManagerTable_t * p_mem_manager_table; LST_init_head (&FreeBufQueue); 8013410: 4817 ldr r0, [pc, #92] @ (8013470 ) 8013412: f000 f929 bl 8013668 LST_init_head (&LocalFreeBufQueue); 8013416: 4817 ldr r0, [pc, #92] @ (8013474 ) 8013418: f000 f926 bl 8013668 p_mem_manager_table = TL_RefTable.p_mem_manager_table; 801341c: 4b16 ldr r3, [pc, #88] @ (8013478 ) 801341e: 691b ldr r3, [r3, #16] 8013420: 4a16 ldr r2, [pc, #88] @ (801347c ) 8013422: 6013 str r3, [r2, #0] p_mem_manager_table->blepool = p_Config->p_AsynchEvtPool; 8013424: 4b15 ldr r3, [pc, #84] @ (801347c ) 8013426: 681b ldr r3, [r3, #0] 8013428: 687a ldr r2, [r7, #4] 801342a: 6892 ldr r2, [r2, #8] 801342c: 609a str r2, [r3, #8] p_mem_manager_table->blepoolsize = p_Config->AsynchEvtPoolSize; 801342e: 4b13 ldr r3, [pc, #76] @ (801347c ) 8013430: 681b ldr r3, [r3, #0] 8013432: 687a ldr r2, [r7, #4] 8013434: 68d2 ldr r2, [r2, #12] 8013436: 60da str r2, [r3, #12] p_mem_manager_table->pevt_free_buffer_queue = (uint8_t*)&FreeBufQueue; 8013438: 4b10 ldr r3, [pc, #64] @ (801347c ) 801343a: 681b ldr r3, [r3, #0] 801343c: 4a0c ldr r2, [pc, #48] @ (8013470 ) 801343e: 611a str r2, [r3, #16] p_mem_manager_table->spare_ble_buffer = p_Config->p_BleSpareEvtBuffer; 8013440: 4b0e ldr r3, [pc, #56] @ (801347c ) 8013442: 681b ldr r3, [r3, #0] 8013444: 687a ldr r2, [r7, #4] 8013446: 6812 ldr r2, [r2, #0] 8013448: 601a str r2, [r3, #0] p_mem_manager_table->spare_sys_buffer = p_Config->p_SystemSpareEvtBuffer; 801344a: 4b0c ldr r3, [pc, #48] @ (801347c ) 801344c: 681b ldr r3, [r3, #0] 801344e: 687a ldr r2, [r7, #4] 8013450: 6852 ldr r2, [r2, #4] 8013452: 605a str r2, [r3, #4] p_mem_manager_table->traces_evt_pool = p_Config->p_TracesEvtPool; 8013454: 4b09 ldr r3, [pc, #36] @ (801347c ) 8013456: 681b ldr r3, [r3, #0] 8013458: 687a ldr r2, [r7, #4] 801345a: 6912 ldr r2, [r2, #16] 801345c: 615a str r2, [r3, #20] p_mem_manager_table->tracespoolsize = p_Config->TracesEvtPoolSize; 801345e: 4b07 ldr r3, [pc, #28] @ (801347c ) 8013460: 681b ldr r3, [r3, #0] 8013462: 687a ldr r2, [r7, #4] 8013464: 6952 ldr r2, [r2, #20] 8013466: 619a str r2, [r3, #24] return; 8013468: bf00 nop } 801346a: 3708 adds r7, #8 801346c: 46bd mov sp, r7 801346e: bd80 pop {r7, pc} 8013470: 200300b8 .word 0x200300b8 8013474: 200007b0 .word 0x200007b0 8013478: 20030000 .word 0x20030000 801347c: 200007c8 .word 0x200007c8 08013480 : void TL_MM_EvtDone(TL_EvtPacket_t * phcievt) { 8013480: b580 push {r7, lr} 8013482: b082 sub sp, #8 8013484: af00 add r7, sp, #0 8013486: 6078 str r0, [r7, #4] LST_insert_tail(&LocalFreeBufQueue, (tListNode *)phcievt); 8013488: 6879 ldr r1, [r7, #4] 801348a: 4807 ldr r0, [pc, #28] @ (80134a8 ) 801348c: f000 f944 bl 8013718 OutputDbgTrace(TL_MB_MM_RELEASE_BUFFER, (uint8_t*)phcievt); 8013490: 6879 ldr r1, [r7, #4] 8013492: 2000 movs r0, #0 8013494: f000 f862 bl 801355c HW_IPCC_MM_SendFreeBuf( SendFreeBuf ); 8013498: 4804 ldr r0, [pc, #16] @ (80134ac ) 801349a: f005 f965 bl 8018768 return; 801349e: bf00 nop } 80134a0: 3708 adds r7, #8 80134a2: 46bd mov sp, r7 80134a4: bd80 pop {r7, pc} 80134a6: bf00 nop 80134a8: 200007b0 .word 0x200007b0 80134ac: 080134b1 .word 0x080134b1 080134b0 : static void SendFreeBuf( void ) { 80134b0: b580 push {r7, lr} 80134b2: b082 sub sp, #8 80134b4: af00 add r7, sp, #0 tListNode *p_node; while ( FALSE == LST_is_empty (&LocalFreeBufQueue) ) 80134b6: e00c b.n 80134d2 { LST_remove_head( &LocalFreeBufQueue, (tListNode **)&p_node ); 80134b8: 1d3b adds r3, r7, #4 80134ba: 4619 mov r1, r3 80134bc: 480a ldr r0, [pc, #40] @ (80134e8 ) 80134be: f000 f972 bl 80137a6 LST_insert_tail( (tListNode*)(TL_RefTable.p_mem_manager_table->pevt_free_buffer_queue), p_node ); 80134c2: 4b0a ldr r3, [pc, #40] @ (80134ec ) 80134c4: 691b ldr r3, [r3, #16] 80134c6: 691b ldr r3, [r3, #16] 80134c8: 687a ldr r2, [r7, #4] 80134ca: 4611 mov r1, r2 80134cc: 4618 mov r0, r3 80134ce: f000 f923 bl 8013718 while ( FALSE == LST_is_empty (&LocalFreeBufQueue) ) 80134d2: 4805 ldr r0, [pc, #20] @ (80134e8 ) 80134d4: f000 f8d8 bl 8013688 80134d8: 4603 mov r3, r0 80134da: 2b00 cmp r3, #0 80134dc: d0ec beq.n 80134b8 } return; 80134de: bf00 nop } 80134e0: 3708 adds r7, #8 80134e2: 46bd mov sp, r7 80134e4: bd80 pop {r7, pc} 80134e6: bf00 nop 80134e8: 200007b0 .word 0x200007b0 80134ec: 20030000 .word 0x20030000 080134f0 : /****************************************************************************** * TRACES ******************************************************************************/ void TL_TRACES_Init( void ) { 80134f0: b580 push {r7, lr} 80134f2: af00 add r7, sp, #0 LST_init_head (&TracesEvtQueue); 80134f4: 4805 ldr r0, [pc, #20] @ (801350c ) 80134f6: f000 f8b7 bl 8013668 TL_RefTable.p_traces_table->traces_queue = (uint8_t*)&TracesEvtQueue; 80134fa: 4b05 ldr r3, [pc, #20] @ (8013510 ) 80134fc: 695b ldr r3, [r3, #20] 80134fe: 4a03 ldr r2, [pc, #12] @ (801350c ) 8013500: 601a str r2, [r3, #0] HW_IPCC_TRACES_Init(); 8013502: f005 f983 bl 801880c return; 8013506: bf00 nop } 8013508: bd80 pop {r7, pc} 801350a: bf00 nop 801350c: 200300c0 .word 0x200300c0 8013510: 20030000 .word 0x20030000 08013514 : void HW_IPCC_TRACES_EvtNot(void) { 8013514: b580 push {r7, lr} 8013516: b082 sub sp, #8 8013518: af00 add r7, sp, #0 TL_EvtPacket_t *phcievt; while(LST_is_empty(&TracesEvtQueue) == FALSE) 801351a: e008 b.n 801352e { LST_remove_head (&TracesEvtQueue, (tListNode **)&phcievt); 801351c: 1d3b adds r3, r7, #4 801351e: 4619 mov r1, r3 8013520: 4808 ldr r0, [pc, #32] @ (8013544 ) 8013522: f000 f940 bl 80137a6 TL_TRACES_EvtReceived( phcievt ); 8013526: 687b ldr r3, [r7, #4] 8013528: 4618 mov r0, r3 801352a: f000 f80d bl 8013548 while(LST_is_empty(&TracesEvtQueue) == FALSE) 801352e: 4805 ldr r0, [pc, #20] @ (8013544 ) 8013530: f000 f8aa bl 8013688 8013534: 4603 mov r3, r0 8013536: 2b00 cmp r3, #0 8013538: d0f0 beq.n 801351c } return; 801353a: bf00 nop } 801353c: 3708 adds r7, #8 801353e: 46bd mov sp, r7 8013540: bd80 pop {r7, pc} 8013542: bf00 nop 8013544: 200300c0 .word 0x200300c0 08013548 : __WEAK void TL_TRACES_EvtReceived( TL_EvtPacket_t * hcievt ) { 8013548: b480 push {r7} 801354a: b083 sub sp, #12 801354c: af00 add r7, sp, #0 801354e: 6078 str r0, [r7, #4] (void)(hcievt); } 8013550: bf00 nop 8013552: 370c adds r7, #12 8013554: 46bd mov sp, r7 8013556: f85d 7b04 ldr.w r7, [sp], #4 801355a: 4770 bx lr 0801355c : /****************************************************************************** * DEBUG INFORMATION ******************************************************************************/ static void OutputDbgTrace(TL_MB_PacketType_t packet_type, uint8_t* buffer) { 801355c: b480 push {r7} 801355e: b087 sub sp, #28 8013560: af00 add r7, sp, #0 8013562: 4603 mov r3, r0 8013564: 6039 str r1, [r7, #0] 8013566: 71fb strb r3, [r7, #7] TL_EvtPacket_t *p_evt_packet; TL_CmdPacket_t *p_cmd_packet; TL_AclDataPacket_t *p_acldata_packet; TL_EvtSerial_t *p_cmd_rsp_packet; switch(packet_type) 8013568: 79fb ldrb r3, [r7, #7] 801356a: 2b08 cmp r3, #8 801356c: d84c bhi.n 8013608 801356e: a201 add r2, pc, #4 @ (adr r2, 8013574 ) 8013570: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8013574: 08013599 .word 0x08013599 8013578: 080135bd .word 0x080135bd 801357c: 080135c9 .word 0x080135c9 8013580: 080135c3 .word 0x080135c3 8013584: 08013609 .word 0x08013609 8013588: 080135dd .word 0x080135dd 801358c: 080135e9 .word 0x080135e9 8013590: 080135ef .word 0x080135ef 8013594: 080135fd .word 0x080135fd { case TL_MB_MM_RELEASE_BUFFER: p_evt_packet = (TL_EvtPacket_t*)buffer; 8013598: 683b ldr r3, [r7, #0] 801359a: 617b str r3, [r7, #20] switch(p_evt_packet->evtserial.evt.evtcode) 801359c: 697b ldr r3, [r7, #20] 801359e: 7a5b ldrb r3, [r3, #9] 80135a0: 2bff cmp r3, #255 @ 0xff 80135a2: d005 beq.n 80135b0 80135a4: 2bff cmp r3, #255 @ 0xff 80135a6: dc05 bgt.n 80135b4 80135a8: 2b0e cmp r3, #14 80135aa: d005 beq.n 80135b8 80135ac: 2b0f cmp r3, #15 break; default: TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode); TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet); break; 80135ae: e001 b.n 80135b4 break; 80135b0: bf00 nop 80135b2: e02a b.n 801360a break; 80135b4: bf00 nop 80135b6: e028 b.n 801360a break; 80135b8: bf00 nop } TL_MM_DBG_MSG("\r\n"); break; 80135ba: e026 b.n 801360a case TL_MB_BLE_CMD: p_cmd_packet = (TL_CmdPacket_t*)buffer; 80135bc: 683b ldr r3, [r7, #0] 80135be: 60fb str r3, [r7, #12] TL_HCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, ""); } TL_HCI_CMD_DBG_MSG("\r\n"); TL_HCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE); break; 80135c0: e023 b.n 801360a case TL_MB_ACL_DATA: (void)p_acldata_packet; p_acldata_packet = (TL_AclDataPacket_t*)buffer; 80135c2: 683b ldr r3, [r7, #0] 80135c4: 60bb str r3, [r7, #8] TL_HCI_CMD_DBG_MSG(" payload:"); TL_HCI_CMD_DBG_BUF(p_acldata_packet->AclDataSerial.acl_data, p_acldata_packet->AclDataSerial.length, ""); }*/ TL_HCI_CMD_DBG_MSG("\r\n"); /*TL_HCI_CMD_DBG_RAW(&p_acldata_packet->AclDataSerial, p_acldata_packet->AclDataSerial.length+TL_CMD_HDR_SIZE);*/ break; 80135c6: e020 b.n 801360a TL_HCI_CMD_DBG_MSG(" ACL Data Tx Ack received"); TL_HCI_CMD_DBG_MSG("\r\n"); break; case TL_MB_BLE_CMD_RSP: p_evt_packet = (TL_EvtPacket_t*)buffer; 80135c8: 683b ldr r3, [r7, #0] 80135ca: 617b str r3, [r7, #20] switch(p_evt_packet->evtserial.evt.evtcode) 80135cc: 697b ldr r3, [r7, #20] 80135ce: 7a5b ldrb r3, [r3, #9] 80135d0: 2b0e cmp r3, #14 80135d2: d001 beq.n 80135d8 80135d4: 2b0f cmp r3, #15 } break; default: TL_HCI_CMD_DBG_MSG("unknown ble rsp received: %02X", p_evt_packet->evtserial.evt.evtcode); break; 80135d6: e000 b.n 80135da break; 80135d8: bf00 nop } TL_HCI_CMD_DBG_MSG("\r\n"); TL_HCI_CMD_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); break; 80135da: e016 b.n 801360a case TL_MB_BLE_ASYNCH_EVT: p_evt_packet = (TL_EvtPacket_t*)buffer; 80135dc: 683b ldr r3, [r7, #0] 80135de: 617b str r3, [r7, #20] if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE) 80135e0: 697b ldr r3, [r7, #20] 80135e2: 7a5b ldrb r3, [r3, #9] 80135e4: 2bff cmp r3, #255 @ 0xff } TL_HCI_EVT_DBG_MSG("\r\n"); TL_HCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); break; 80135e6: e010 b.n 801360a case TL_MB_SYS_CMD: p_cmd_packet = (TL_CmdPacket_t*)buffer; 80135e8: 683b ldr r3, [r7, #0] 80135ea: 60fb str r3, [r7, #12] TL_SHCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, ""); } TL_SHCI_CMD_DBG_MSG("\r\n"); TL_SHCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE); break; 80135ec: e00d b.n 801360a case TL_MB_SYS_CMD_RSP: p_cmd_rsp_packet = (TL_EvtSerial_t*)buffer; 80135ee: 683b ldr r3, [r7, #0] 80135f0: 613b str r3, [r7, #16] switch(p_cmd_rsp_packet->evt.evtcode) 80135f2: 693b ldr r3, [r7, #16] 80135f4: 785b ldrb r3, [r3, #1] 80135f6: 2b0e cmp r3, #14 } break; default: TL_SHCI_CMD_DBG_MSG("unknown sys rsp received: %02X", p_cmd_rsp_packet->evt.evtcode); break; 80135f8: bf00 nop } TL_SHCI_CMD_DBG_MSG("\r\n"); TL_SHCI_CMD_DBG_RAW(&p_cmd_rsp_packet->evt, p_cmd_rsp_packet->evt.plen+TL_EVT_HDR_SIZE); break; 80135fa: e006 b.n 801360a case TL_MB_SYS_ASYNCH_EVT: p_evt_packet = (TL_EvtPacket_t*)buffer; 80135fc: 683b ldr r3, [r7, #0] 80135fe: 617b str r3, [r7, #20] if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE) 8013600: 697b ldr r3, [r7, #20] 8013602: 7a5b ldrb r3, [r3, #9] 8013604: 2bff cmp r3, #255 @ 0xff } TL_SHCI_EVT_DBG_MSG("\r\n"); TL_SHCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE); break; 8013606: e000 b.n 801360a default: break; 8013608: bf00 nop } return; 801360a: bf00 nop } 801360c: 371c adds r7, #28 801360e: 46bd mov sp, r7 8013610: f85d 7b04 ldr.w r7, [sp], #4 8013614: 4770 bx lr 8013616: bf00 nop 08013618 : /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Functions Definition ------------------------------------------------------*/ uint8_t * OTP_Read( uint8_t id ) { 8013618: b480 push {r7} 801361a: b085 sub sp, #20 801361c: af00 add r7, sp, #0 801361e: 4603 mov r3, r0 8013620: 71fb strb r3, [r7, #7] uint8_t *p_id; p_id = (uint8_t*)(CFG_OTP_END_ADRESS - 7) ; 8013622: 4b0f ldr r3, [pc, #60] @ (8013660 ) 8013624: 60fb str r3, [r7, #12] while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) ) 8013626: e002 b.n 801362e { p_id -= 8 ; 8013628: 68fb ldr r3, [r7, #12] 801362a: 3b08 subs r3, #8 801362c: 60fb str r3, [r7, #12] while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) ) 801362e: 68fb ldr r3, [r7, #12] 8013630: 3307 adds r3, #7 8013632: 781b ldrb r3, [r3, #0] 8013634: 79fa ldrb r2, [r7, #7] 8013636: 429a cmp r2, r3 8013638: d003 beq.n 8013642 801363a: 68fb ldr r3, [r7, #12] 801363c: 4a09 ldr r2, [pc, #36] @ (8013664 ) 801363e: 4293 cmp r3, r2 8013640: d1f2 bne.n 8013628 } if((*( p_id + 7 )) != id) 8013642: 68fb ldr r3, [r7, #12] 8013644: 3307 adds r3, #7 8013646: 781b ldrb r3, [r3, #0] 8013648: 79fa ldrb r2, [r7, #7] 801364a: 429a cmp r2, r3 801364c: d001 beq.n 8013652 { p_id = 0 ; 801364e: 2300 movs r3, #0 8013650: 60fb str r3, [r7, #12] } return p_id ; 8013652: 68fb ldr r3, [r7, #12] } 8013654: 4618 mov r0, r3 8013656: 3714 adds r7, #20 8013658: 46bd mov sp, r7 801365a: f85d 7b04 ldr.w r7, [sp], #4 801365e: 4770 bx lr 8013660: 1fff73f8 .word 0x1fff73f8 8013664: 1fff7000 .word 0x1fff7000 08013668 : /****************************************************************************** * Function Definitions ******************************************************************************/ void LST_init_head (tListNode * listHead) { 8013668: b480 push {r7} 801366a: b083 sub sp, #12 801366c: af00 add r7, sp, #0 801366e: 6078 str r0, [r7, #4] listHead->next = listHead; 8013670: 687b ldr r3, [r7, #4] 8013672: 687a ldr r2, [r7, #4] 8013674: 601a str r2, [r3, #0] listHead->prev = listHead; 8013676: 687b ldr r3, [r7, #4] 8013678: 687a ldr r2, [r7, #4] 801367a: 605a str r2, [r3, #4] } 801367c: bf00 nop 801367e: 370c adds r7, #12 8013680: 46bd mov sp, r7 8013682: f85d 7b04 ldr.w r7, [sp], #4 8013686: 4770 bx lr 08013688 : uint8_t LST_is_empty (tListNode * listHead) { 8013688: b480 push {r7} 801368a: b087 sub sp, #28 801368c: af00 add r7, sp, #0 801368e: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8013690: f3ef 8310 mrs r3, PRIMASK 8013694: 60fb str r3, [r7, #12] return(result); 8013696: 68fb ldr r3, [r7, #12] uint32_t primask_bit; uint8_t return_value; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 8013698: 613b str r3, [r7, #16] __ASM volatile ("cpsid i" : : : "memory"); 801369a: b672 cpsid i } 801369c: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ if(listHead->next == listHead) 801369e: 687b ldr r3, [r7, #4] 80136a0: 681b ldr r3, [r3, #0] 80136a2: 687a ldr r2, [r7, #4] 80136a4: 429a cmp r2, r3 80136a6: d102 bne.n 80136ae { return_value = TRUE; 80136a8: 2301 movs r3, #1 80136aa: 75fb strb r3, [r7, #23] 80136ac: e001 b.n 80136b2 } else { return_value = FALSE; 80136ae: 2300 movs r3, #0 80136b0: 75fb strb r3, [r7, #23] 80136b2: 693b ldr r3, [r7, #16] 80136b4: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80136b6: 68bb ldr r3, [r7, #8] 80136b8: f383 8810 msr PRIMASK, r3 } 80136bc: bf00 nop } __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ return return_value; 80136be: 7dfb ldrb r3, [r7, #23] } 80136c0: 4618 mov r0, r3 80136c2: 371c adds r7, #28 80136c4: 46bd mov sp, r7 80136c6: f85d 7b04 ldr.w r7, [sp], #4 80136ca: 4770 bx lr 080136cc : void LST_insert_head (tListNode * listHead, tListNode * node) { 80136cc: b480 push {r7} 80136ce: b087 sub sp, #28 80136d0: af00 add r7, sp, #0 80136d2: 6078 str r0, [r7, #4] 80136d4: 6039 str r1, [r7, #0] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80136d6: f3ef 8310 mrs r3, PRIMASK 80136da: 60fb str r3, [r7, #12] return(result); 80136dc: 68fb ldr r3, [r7, #12] uint32_t primask_bit; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 80136de: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 80136e0: b672 cpsid i } 80136e2: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ node->next = listHead->next; 80136e4: 687b ldr r3, [r7, #4] 80136e6: 681a ldr r2, [r3, #0] 80136e8: 683b ldr r3, [r7, #0] 80136ea: 601a str r2, [r3, #0] node->prev = listHead; 80136ec: 683b ldr r3, [r7, #0] 80136ee: 687a ldr r2, [r7, #4] 80136f0: 605a str r2, [r3, #4] listHead->next = node; 80136f2: 687b ldr r3, [r7, #4] 80136f4: 683a ldr r2, [r7, #0] 80136f6: 601a str r2, [r3, #0] (node->next)->prev = node; 80136f8: 683b ldr r3, [r7, #0] 80136fa: 681b ldr r3, [r3, #0] 80136fc: 683a ldr r2, [r7, #0] 80136fe: 605a str r2, [r3, #4] 8013700: 697b ldr r3, [r7, #20] 8013702: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8013704: 693b ldr r3, [r7, #16] 8013706: f383 8810 msr PRIMASK, r3 } 801370a: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ } 801370c: bf00 nop 801370e: 371c adds r7, #28 8013710: 46bd mov sp, r7 8013712: f85d 7b04 ldr.w r7, [sp], #4 8013716: 4770 bx lr 08013718 : void LST_insert_tail (tListNode * listHead, tListNode * node) { 8013718: b480 push {r7} 801371a: b087 sub sp, #28 801371c: af00 add r7, sp, #0 801371e: 6078 str r0, [r7, #4] 8013720: 6039 str r1, [r7, #0] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8013722: f3ef 8310 mrs r3, PRIMASK 8013726: 60fb str r3, [r7, #12] return(result); 8013728: 68fb ldr r3, [r7, #12] uint32_t primask_bit; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 801372a: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 801372c: b672 cpsid i } 801372e: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ node->next = listHead; 8013730: 683b ldr r3, [r7, #0] 8013732: 687a ldr r2, [r7, #4] 8013734: 601a str r2, [r3, #0] node->prev = listHead->prev; 8013736: 687b ldr r3, [r7, #4] 8013738: 685a ldr r2, [r3, #4] 801373a: 683b ldr r3, [r7, #0] 801373c: 605a str r2, [r3, #4] listHead->prev = node; 801373e: 687b ldr r3, [r7, #4] 8013740: 683a ldr r2, [r7, #0] 8013742: 605a str r2, [r3, #4] (node->prev)->next = node; 8013744: 683b ldr r3, [r7, #0] 8013746: 685b ldr r3, [r3, #4] 8013748: 683a ldr r2, [r7, #0] 801374a: 601a str r2, [r3, #0] 801374c: 697b ldr r3, [r7, #20] 801374e: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8013750: 693b ldr r3, [r7, #16] 8013752: f383 8810 msr PRIMASK, r3 } 8013756: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ } 8013758: bf00 nop 801375a: 371c adds r7, #28 801375c: 46bd mov sp, r7 801375e: f85d 7b04 ldr.w r7, [sp], #4 8013762: 4770 bx lr 08013764 : void LST_remove_node (tListNode * node) { 8013764: b480 push {r7} 8013766: b087 sub sp, #28 8013768: af00 add r7, sp, #0 801376a: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 801376c: f3ef 8310 mrs r3, PRIMASK 8013770: 60fb str r3, [r7, #12] return(result); 8013772: 68fb ldr r3, [r7, #12] uint32_t primask_bit; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 8013774: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 8013776: b672 cpsid i } 8013778: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ (node->prev)->next = node->next; 801377a: 687b ldr r3, [r7, #4] 801377c: 685b ldr r3, [r3, #4] 801377e: 687a ldr r2, [r7, #4] 8013780: 6812 ldr r2, [r2, #0] 8013782: 601a str r2, [r3, #0] (node->next)->prev = node->prev; 8013784: 687b ldr r3, [r7, #4] 8013786: 681b ldr r3, [r3, #0] 8013788: 687a ldr r2, [r7, #4] 801378a: 6852 ldr r2, [r2, #4] 801378c: 605a str r2, [r3, #4] 801378e: 697b ldr r3, [r7, #20] 8013790: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8013792: 693b ldr r3, [r7, #16] 8013794: f383 8810 msr PRIMASK, r3 } 8013798: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ } 801379a: bf00 nop 801379c: 371c adds r7, #28 801379e: 46bd mov sp, r7 80137a0: f85d 7b04 ldr.w r7, [sp], #4 80137a4: 4770 bx lr 080137a6 : void LST_remove_head (tListNode * listHead, tListNode ** node ) { 80137a6: b580 push {r7, lr} 80137a8: b086 sub sp, #24 80137aa: af00 add r7, sp, #0 80137ac: 6078 str r0, [r7, #4] 80137ae: 6039 str r1, [r7, #0] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80137b0: f3ef 8310 mrs r3, PRIMASK 80137b4: 60fb str r3, [r7, #12] return(result); 80137b6: 68fb ldr r3, [r7, #12] uint32_t primask_bit; primask_bit = __get_PRIMASK(); /**< backup PRIMASK bit */ 80137b8: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 80137ba: b672 cpsid i } 80137bc: bf00 nop __disable_irq(); /**< Disable all interrupts by setting PRIMASK bit on Cortex*/ *node = listHead->next; 80137be: 687b ldr r3, [r7, #4] 80137c0: 681a ldr r2, [r3, #0] 80137c2: 683b ldr r3, [r7, #0] 80137c4: 601a str r2, [r3, #0] LST_remove_node (listHead->next); 80137c6: 687b ldr r3, [r7, #4] 80137c8: 681b ldr r3, [r3, #0] 80137ca: 4618 mov r0, r3 80137cc: f7ff ffca bl 8013764 80137d0: 697b ldr r3, [r7, #20] 80137d2: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80137d4: 693b ldr r3, [r7, #16] 80137d6: f383 8810 msr PRIMASK, r3 } 80137da: bf00 nop __set_PRIMASK(primask_bit); /**< Restore PRIMASK bit*/ } 80137dc: bf00 nop 80137de: 3718 adds r7, #24 80137e0: 46bd mov sp, r7 80137e2: bd80 pop {r7, pc} 080137e4 <__NVIC_SetPriority>: { 80137e4: b480 push {r7} 80137e6: b083 sub sp, #12 80137e8: af00 add r7, sp, #0 80137ea: 4603 mov r3, r0 80137ec: 6039 str r1, [r7, #0] 80137ee: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80137f0: f997 3007 ldrsb.w r3, [r7, #7] 80137f4: 2b00 cmp r3, #0 80137f6: db0a blt.n 801380e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80137f8: 683b ldr r3, [r7, #0] 80137fa: b2da uxtb r2, r3 80137fc: 490c ldr r1, [pc, #48] @ (8013830 <__NVIC_SetPriority+0x4c>) 80137fe: f997 3007 ldrsb.w r3, [r7, #7] 8013802: 0112 lsls r2, r2, #4 8013804: b2d2 uxtb r2, r2 8013806: 440b add r3, r1 8013808: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 801380c: e00a b.n 8013824 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 801380e: 683b ldr r3, [r7, #0] 8013810: b2da uxtb r2, r3 8013812: 4908 ldr r1, [pc, #32] @ (8013834 <__NVIC_SetPriority+0x50>) 8013814: 79fb ldrb r3, [r7, #7] 8013816: f003 030f and.w r3, r3, #15 801381a: 3b04 subs r3, #4 801381c: 0112 lsls r2, r2, #4 801381e: b2d2 uxtb r2, r2 8013820: 440b add r3, r1 8013822: 761a strb r2, [r3, #24] } 8013824: bf00 nop 8013826: 370c adds r7, #12 8013828: 46bd mov sp, r7 801382a: f85d 7b04 ldr.w r7, [sp], #4 801382e: 4770 bx lr 8013830: e000e100 .word 0xe000e100 8013834: e000ed00 .word 0xe000ed00 08013838 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 8013838: b580 push {r7, lr} 801383a: af00 add r7, sp, #0 #if (configUSE_TICKLESS_IDLE == 0) /* Clear overflow flag */ SysTick->CTRL; 801383c: 4b05 ldr r3, [pc, #20] @ (8013854 ) 801383e: 681b ldr r3, [r3, #0] #endif if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 8013840: f002 ff64 bl 801670c 8013844: 4603 mov r3, r0 8013846: 2b01 cmp r3, #1 8013848: d001 beq.n 801384e /* Call tick handler */ xPortSysTickHandler(); 801384a: f004 faf5 bl 8017e38 } } 801384e: bf00 nop 8013850: bd80 pop {r7, pc} 8013852: bf00 nop 8013854: e000e010 .word 0xe000e010 08013858 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 8013858: b580 push {r7, lr} 801385a: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc instruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQn, 0U); 801385c: 2100 movs r1, #0 801385e: f06f 0004 mvn.w r0, #4 8013862: f7ff ffbf bl 80137e4 <__NVIC_SetPriority> #endif } 8013866: bf00 nop 8013868: bd80 pop {r7, pc} 0801386a : #endif /* Determine if CPU executes from interrupt context or if interrupts are masked. */ __STATIC_INLINE uint32_t IRQ_Context (void) { 801386a: b580 push {r7, lr} 801386c: b086 sub sp, #24 801386e: af00 add r7, sp, #0 uint32_t irq; BaseType_t state; irq = 0U; 8013870: 2300 movs r3, #0 8013872: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013874: f3ef 8305 mrs r3, IPSR 8013878: 60fb str r3, [r7, #12] return(result); 801387a: 68fb ldr r3, [r7, #12] if (IS_IRQ_MODE()) { 801387c: 2b00 cmp r3, #0 801387e: d002 beq.n 8013886 /* Called from interrupt context */ irq = 1U; 8013880: 2301 movs r3, #1 8013882: 617b str r3, [r7, #20] 8013884: e013 b.n 80138ae } else { /* Get FreeRTOS scheduler state */ state = xTaskGetSchedulerState(); 8013886: f002 ff41 bl 801670c 801388a: 6138 str r0, [r7, #16] if (state != taskSCHEDULER_NOT_STARTED) { 801388c: 693b ldr r3, [r7, #16] 801388e: 2b01 cmp r3, #1 8013890: d00d beq.n 80138ae __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8013892: f3ef 8310 mrs r3, PRIMASK 8013896: 60bb str r3, [r7, #8] return(result); 8013898: 68bb ldr r3, [r7, #8] /* Scheduler was started */ if (IS_IRQ_MASKED()) { 801389a: 2b00 cmp r3, #0 801389c: d105 bne.n 80138aa __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 801389e: f3ef 8311 mrs r3, BASEPRI 80138a2: 607b str r3, [r7, #4] return(result); 80138a4: 687b ldr r3, [r7, #4] 80138a6: 2b00 cmp r3, #0 80138a8: d001 beq.n 80138ae /* Interrupts are masked */ irq = 1U; 80138aa: 2301 movs r3, #1 80138ac: 617b str r3, [r7, #20] } } } /* Return context, 0: thread context, 1: IRQ context */ return (irq); 80138ae: 697b ldr r3, [r7, #20] } 80138b0: 4618 mov r0, r3 80138b2: 3718 adds r7, #24 80138b4: 46bd mov sp, r7 80138b6: bd80 pop {r7, pc} 080138b8 : /* ==== Kernel Management Functions ==== */ /* Initialize the RTOS Kernel. */ osStatus_t osKernelInitialize (void) { 80138b8: b580 push {r7, lr} 80138ba: b082 sub sp, #8 80138bc: af00 add r7, sp, #0 osStatus_t stat; BaseType_t state; if (IRQ_Context() != 0U) { 80138be: f7ff ffd4 bl 801386a 80138c2: 4603 mov r3, r0 80138c4: 2b00 cmp r3, #0 80138c6: d003 beq.n 80138d0 stat = osErrorISR; 80138c8: f06f 0305 mvn.w r3, #5 80138cc: 607b str r3, [r7, #4] 80138ce: e012 b.n 80138f6 } else { state = xTaskGetSchedulerState(); 80138d0: f002 ff1c bl 801670c 80138d4: 6038 str r0, [r7, #0] /* Initialize if scheduler not started and not initialized before */ if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelInactive)) { 80138d6: 683b ldr r3, [r7, #0] 80138d8: 2b01 cmp r3, #1 80138da: d109 bne.n 80138f0 80138dc: 4b08 ldr r3, [pc, #32] @ (8013900 ) 80138de: 681b ldr r3, [r3, #0] 80138e0: 2b00 cmp r3, #0 80138e2: d105 bne.n 80138f0 #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) /* Initialize the memory regions when using heap_5 variant */ vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 80138e4: 4b06 ldr r3, [pc, #24] @ (8013900 ) 80138e6: 2201 movs r2, #1 80138e8: 601a str r2, [r3, #0] stat = osOK; 80138ea: 2300 movs r3, #0 80138ec: 607b str r3, [r7, #4] 80138ee: e002 b.n 80138f6 } else { stat = osError; 80138f0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80138f4: 607b str r3, [r7, #4] } } /* Return execution status */ return (stat); 80138f6: 687b ldr r3, [r7, #4] } 80138f8: 4618 mov r0, r3 80138fa: 3708 adds r7, #8 80138fc: 46bd mov sp, r7 80138fe: bd80 pop {r7, pc} 8013900: 200007cc .word 0x200007cc 08013904 : } /* Start the RTOS Kernel scheduler. */ osStatus_t osKernelStart (void) { 8013904: b580 push {r7, lr} 8013906: b082 sub sp, #8 8013908: af00 add r7, sp, #0 osStatus_t stat; BaseType_t state; if (IRQ_Context() != 0U) { 801390a: f7ff ffae bl 801386a 801390e: 4603 mov r3, r0 8013910: 2b00 cmp r3, #0 8013912: d003 beq.n 801391c stat = osErrorISR; 8013914: f06f 0305 mvn.w r3, #5 8013918: 607b str r3, [r7, #4] 801391a: e016 b.n 801394a } else { state = xTaskGetSchedulerState(); 801391c: f002 fef6 bl 801670c 8013920: 6038 str r0, [r7, #0] /* Start scheduler if initialized and not started before */ if ((state == taskSCHEDULER_NOT_STARTED) && (KernelState == osKernelReady)) { 8013922: 683b ldr r3, [r7, #0] 8013924: 2b01 cmp r3, #1 8013926: d10d bne.n 8013944 8013928: 4b0a ldr r3, [pc, #40] @ (8013954 ) 801392a: 681b ldr r3, [r3, #0] 801392c: 2b01 cmp r3, #1 801392e: d109 bne.n 8013944 /* Ensure SVC priority is at the reset value */ SVC_Setup(); 8013930: f7ff ff92 bl 8013858 /* Change state to ensure correct API flow */ KernelState = osKernelRunning; 8013934: 4b07 ldr r3, [pc, #28] @ (8013954 ) 8013936: 2202 movs r2, #2 8013938: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 801393a: f002 f8f1 bl 8015b20 stat = osOK; 801393e: 2300 movs r3, #0 8013940: 607b str r3, [r7, #4] 8013942: e002 b.n 801394a } else { stat = osError; 8013944: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013948: 607b str r3, [r7, #4] } } /* Return execution status */ return (stat); 801394a: 687b ldr r3, [r7, #4] } 801394c: 4618 mov r0, r3 801394e: 3708 adds r7, #8 8013950: 46bd mov sp, r7 8013952: bd80 pop {r7, pc} 8013954: 200007cc .word 0x200007cc 08013958 : Limitations: - The memory for control block and stack must be provided in the osThreadAttr_t structure in order to allocate object statically. - Attribute osThreadJoinable is not supported, NULL is returned if used. */ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 8013958: b580 push {r7, lr} 801395a: b08e sub sp, #56 @ 0x38 801395c: af04 add r7, sp, #16 801395e: 60f8 str r0, [r7, #12] 8013960: 60b9 str r1, [r7, #8] 8013962: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 8013964: 2300 movs r3, #0 8013966: 617b str r3, [r7, #20] if ((IRQ_Context() == 0U) && (func != NULL)) { 8013968: f7ff ff7f bl 801386a 801396c: 4603 mov r3, r0 801396e: 2b00 cmp r3, #0 8013970: d17f bne.n 8013a72 8013972: 68fb ldr r3, [r7, #12] 8013974: 2b00 cmp r3, #0 8013976: d07c beq.n 8013a72 stack = configMINIMAL_STACK_SIZE; 8013978: f44f 7300 mov.w r3, #512 @ 0x200 801397c: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 801397e: 2318 movs r3, #24 8013980: 61fb str r3, [r7, #28] name = NULL; 8013982: 2300 movs r3, #0 8013984: 627b str r3, [r7, #36] @ 0x24 mem = -1; 8013986: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801398a: 61bb str r3, [r7, #24] if (attr != NULL) { 801398c: 687b ldr r3, [r7, #4] 801398e: 2b00 cmp r3, #0 8013990: d045 beq.n 8013a1e if (attr->name != NULL) { 8013992: 687b ldr r3, [r7, #4] 8013994: 681b ldr r3, [r3, #0] 8013996: 2b00 cmp r3, #0 8013998: d002 beq.n 80139a0 name = attr->name; 801399a: 687b ldr r3, [r7, #4] 801399c: 681b ldr r3, [r3, #0] 801399e: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 80139a0: 687b ldr r3, [r7, #4] 80139a2: 699b ldr r3, [r3, #24] 80139a4: 2b00 cmp r3, #0 80139a6: d002 beq.n 80139ae prio = (UBaseType_t)attr->priority; 80139a8: 687b ldr r3, [r7, #4] 80139aa: 699b ldr r3, [r3, #24] 80139ac: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 80139ae: 69fb ldr r3, [r7, #28] 80139b0: 2b00 cmp r3, #0 80139b2: d008 beq.n 80139c6 80139b4: 69fb ldr r3, [r7, #28] 80139b6: 2b38 cmp r3, #56 @ 0x38 80139b8: d805 bhi.n 80139c6 80139ba: 687b ldr r3, [r7, #4] 80139bc: 685b ldr r3, [r3, #4] 80139be: f003 0301 and.w r3, r3, #1 80139c2: 2b00 cmp r3, #0 80139c4: d001 beq.n 80139ca /* Invalid priority or unsupported osThreadJoinable attribute used */ return (NULL); 80139c6: 2300 movs r3, #0 80139c8: e054 b.n 8013a74 } if (attr->stack_size > 0U) { 80139ca: 687b ldr r3, [r7, #4] 80139cc: 695b ldr r3, [r3, #20] 80139ce: 2b00 cmp r3, #0 80139d0: d003 beq.n 80139da /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 80139d2: 687b ldr r3, [r7, #4] 80139d4: 695b ldr r3, [r3, #20] 80139d6: 089b lsrs r3, r3, #2 80139d8: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80139da: 687b ldr r3, [r7, #4] 80139dc: 689b ldr r3, [r3, #8] 80139de: 2b00 cmp r3, #0 80139e0: d00e beq.n 8013a00 80139e2: 687b ldr r3, [r7, #4] 80139e4: 68db ldr r3, [r3, #12] 80139e6: 2bab cmp r3, #171 @ 0xab 80139e8: d90a bls.n 8013a00 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80139ea: 687b ldr r3, [r7, #4] 80139ec: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80139ee: 2b00 cmp r3, #0 80139f0: d006 beq.n 8013a00 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80139f2: 687b ldr r3, [r7, #4] 80139f4: 695b ldr r3, [r3, #20] 80139f6: 2b00 cmp r3, #0 80139f8: d002 beq.n 8013a00 /* The memory for control block and stack is provided, use static object */ mem = 1; 80139fa: 2301 movs r3, #1 80139fc: 61bb str r3, [r7, #24] 80139fe: e010 b.n 8013a22 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 8013a00: 687b ldr r3, [r7, #4] 8013a02: 689b ldr r3, [r3, #8] 8013a04: 2b00 cmp r3, #0 8013a06: d10c bne.n 8013a22 8013a08: 687b ldr r3, [r7, #4] 8013a0a: 68db ldr r3, [r3, #12] 8013a0c: 2b00 cmp r3, #0 8013a0e: d108 bne.n 8013a22 8013a10: 687b ldr r3, [r7, #4] 8013a12: 691b ldr r3, [r3, #16] 8013a14: 2b00 cmp r3, #0 8013a16: d104 bne.n 8013a22 /* Control block and stack memory will be allocated from the dynamic pool */ mem = 0; 8013a18: 2300 movs r3, #0 8013a1a: 61bb str r3, [r7, #24] 8013a1c: e001 b.n 8013a22 } } } else { mem = 0; 8013a1e: 2300 movs r3, #0 8013a20: 61bb str r3, [r7, #24] } if (mem == 1) { 8013a22: 69bb ldr r3, [r7, #24] 8013a24: 2b01 cmp r3, #1 8013a26: d110 bne.n 8013a4a #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8013a28: 687b ldr r3, [r7, #4] 8013a2a: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 8013a2c: 687a ldr r2, [r7, #4] 8013a2e: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8013a30: 9202 str r2, [sp, #8] 8013a32: 9301 str r3, [sp, #4] 8013a34: 69fb ldr r3, [r7, #28] 8013a36: 9300 str r3, [sp, #0] 8013a38: 68bb ldr r3, [r7, #8] 8013a3a: 6a3a ldr r2, [r7, #32] 8013a3c: 6a79 ldr r1, [r7, #36] @ 0x24 8013a3e: 68f8 ldr r0, [r7, #12] 8013a40: f001 fe80 bl 8015744 8013a44: 4603 mov r3, r0 8013a46: 617b str r3, [r7, #20] 8013a48: e013 b.n 8013a72 #endif } else { if (mem == 0) { 8013a4a: 69bb ldr r3, [r7, #24] 8013a4c: 2b00 cmp r3, #0 8013a4e: d110 bne.n 8013a72 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (configSTACK_DEPTH_TYPE)stack, argument, prio, &hTask) != pdPASS) { 8013a50: 6a3b ldr r3, [r7, #32] 8013a52: b29a uxth r2, r3 8013a54: f107 0314 add.w r3, r7, #20 8013a58: 9301 str r3, [sp, #4] 8013a5a: 69fb ldr r3, [r7, #28] 8013a5c: 9300 str r3, [sp, #0] 8013a5e: 68bb ldr r3, [r7, #8] 8013a60: 6a79 ldr r1, [r7, #36] @ 0x24 8013a62: 68f8 ldr r0, [r7, #12] 8013a64: f001 fed3 bl 801580e 8013a68: 4603 mov r3, r0 8013a6a: 2b01 cmp r3, #1 8013a6c: d001 beq.n 8013a72 hTask = NULL; 8013a6e: 2300 movs r3, #0 8013a70: 617b str r3, [r7, #20] } } } /* Return thread ID */ return ((osThreadId_t)hTask); 8013a72: 697b ldr r3, [r7, #20] } 8013a74: 4618 mov r0, r3 8013a76: 3728 adds r7, #40 @ 0x28 8013a78: 46bd mov sp, r7 8013a7a: bd80 pop {r7, pc} 08013a7c : } /* Return the thread ID of the current running thread. */ osThreadId_t osThreadGetId (void) { 8013a7c: b580 push {r7, lr} 8013a7e: b082 sub sp, #8 8013a80: af00 add r7, sp, #0 osThreadId_t id; id = (osThreadId_t)xTaskGetCurrentTaskHandle(); 8013a82: f002 fe33 bl 80166ec 8013a86: 6078 str r0, [r7, #4] /* Return thread ID */ return (id); 8013a88: 687b ldr r3, [r7, #4] } 8013a8a: 4618 mov r0, r3 8013a8c: 3708 adds r7, #8 8013a8e: 46bd mov sp, r7 8013a90: bd80 pop {r7, pc} ... 08013a94 : #if (configUSE_OS2_THREAD_FLAGS == 1) /* Set the specified Thread Flags of a thread. */ uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { 8013a94: b580 push {r7, lr} 8013a96: b088 sub sp, #32 8013a98: af02 add r7, sp, #8 8013a9a: 6078 str r0, [r7, #4] 8013a9c: 6039 str r1, [r7, #0] TaskHandle_t hTask = (TaskHandle_t)thread_id; 8013a9e: 687b ldr r3, [r7, #4] 8013aa0: 617b str r3, [r7, #20] uint32_t rflags; BaseType_t yield; if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) { 8013aa2: 697b ldr r3, [r7, #20] 8013aa4: 2b00 cmp r3, #0 8013aa6: d002 beq.n 8013aae 8013aa8: 683b ldr r3, [r7, #0] 8013aaa: 2b00 cmp r3, #0 8013aac: da03 bge.n 8013ab6 rflags = (uint32_t)osErrorParameter; 8013aae: f06f 0303 mvn.w r3, #3 8013ab2: 613b str r3, [r7, #16] 8013ab4: e03c b.n 8013b30 } else { rflags = (uint32_t)osError; 8013ab6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013aba: 613b str r3, [r7, #16] if (IRQ_Context() != 0U) { 8013abc: f7ff fed5 bl 801386a 8013ac0: 4603 mov r3, r0 8013ac2: 2b00 cmp r3, #0 8013ac4: d023 beq.n 8013b0e yield = pdFALSE; 8013ac6: 2300 movs r3, #0 8013ac8: 60fb str r3, [r7, #12] (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield); 8013aca: f107 030c add.w r3, r7, #12 8013ace: 9301 str r3, [sp, #4] 8013ad0: 2300 movs r3, #0 8013ad2: 9300 str r3, [sp, #0] 8013ad4: 2301 movs r3, #1 8013ad6: 683a ldr r2, [r7, #0] 8013ad8: 2100 movs r1, #0 8013ada: 6978 ldr r0, [r7, #20] 8013adc: f003 fa2c bl 8016f38 (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL); 8013ae0: 2300 movs r3, #0 8013ae2: 9301 str r3, [sp, #4] 8013ae4: f107 0310 add.w r3, r7, #16 8013ae8: 9300 str r3, [sp, #0] 8013aea: 2300 movs r3, #0 8013aec: 2200 movs r2, #0 8013aee: 2100 movs r1, #0 8013af0: 6978 ldr r0, [r7, #20] 8013af2: f003 fa21 bl 8016f38 portYIELD_FROM_ISR (yield); 8013af6: 68fb ldr r3, [r7, #12] 8013af8: 2b00 cmp r3, #0 8013afa: d019 beq.n 8013b30 8013afc: 4b0f ldr r3, [pc, #60] @ (8013b3c ) 8013afe: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013b02: 601a str r2, [r3, #0] 8013b04: f3bf 8f4f dsb sy 8013b08: f3bf 8f6f isb sy 8013b0c: e010 b.n 8013b30 } else { (void)xTaskNotify (hTask, flags, eSetBits); 8013b0e: 2300 movs r3, #0 8013b10: 9300 str r3, [sp, #0] 8013b12: 2301 movs r3, #1 8013b14: 683a ldr r2, [r7, #0] 8013b16: 2100 movs r1, #0 8013b18: 6978 ldr r0, [r7, #20] 8013b1a: f003 f8e5 bl 8016ce8 (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags); 8013b1e: f107 0310 add.w r3, r7, #16 8013b22: 9300 str r3, [sp, #0] 8013b24: 2300 movs r3, #0 8013b26: 2200 movs r2, #0 8013b28: 2100 movs r1, #0 8013b2a: 6978 ldr r0, [r7, #20] 8013b2c: f003 f8dc bl 8016ce8 } } /* Return flags after setting */ return (rflags); 8013b30: 693b ldr r3, [r7, #16] } 8013b32: 4618 mov r0, r3 8013b34: 3718 adds r7, #24 8013b36: 46bd mov sp, r7 8013b38: bd80 pop {r7, pc} 8013b3a: bf00 nop 8013b3c: e000ed04 .word 0xe000ed04 08013b40 : } /* Wait for one or more Thread Flags of the current running thread to become signaled. */ uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { 8013b40: b580 push {r7, lr} 8013b42: b08e sub sp, #56 @ 0x38 8013b44: af02 add r7, sp, #8 8013b46: 60f8 str r0, [r7, #12] 8013b48: 60b9 str r1, [r7, #8] 8013b4a: 607a str r2, [r7, #4] uint32_t rflags, nval; uint32_t clear; TickType_t t0, td, tout; BaseType_t rval; if (IRQ_Context() != 0U) { 8013b4c: f7ff fe8d bl 801386a 8013b50: 4603 mov r3, r0 8013b52: 2b00 cmp r3, #0 8013b54: d003 beq.n 8013b5e rflags = (uint32_t)osErrorISR; 8013b56: f06f 0305 mvn.w r3, #5 8013b5a: 62fb str r3, [r7, #44] @ 0x2c 8013b5c: e06e b.n 8013c3c } else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { 8013b5e: 68fb ldr r3, [r7, #12] 8013b60: 2b00 cmp r3, #0 8013b62: da03 bge.n 8013b6c rflags = (uint32_t)osErrorParameter; 8013b64: f06f 0303 mvn.w r3, #3 8013b68: 62fb str r3, [r7, #44] @ 0x2c 8013b6a: e067 b.n 8013c3c } else { if ((options & osFlagsNoClear) == osFlagsNoClear) { 8013b6c: 68bb ldr r3, [r7, #8] 8013b6e: f003 0302 and.w r3, r3, #2 8013b72: 2b00 cmp r3, #0 8013b74: d002 beq.n 8013b7c clear = 0U; 8013b76: 2300 movs r3, #0 8013b78: 62bb str r3, [r7, #40] @ 0x28 8013b7a: e001 b.n 8013b80 } else { clear = flags; 8013b7c: 68fb ldr r3, [r7, #12] 8013b7e: 62bb str r3, [r7, #40] @ 0x28 } rflags = 0U; 8013b80: 2300 movs r3, #0 8013b82: 62fb str r3, [r7, #44] @ 0x2c tout = timeout; 8013b84: 687b ldr r3, [r7, #4] 8013b86: 627b str r3, [r7, #36] @ 0x24 t0 = xTaskGetTickCount(); 8013b88: f002 f94a bl 8015e20 8013b8c: 6238 str r0, [r7, #32] do { rval = xTaskNotifyWait (0, clear, &nval, tout); 8013b8e: f107 0214 add.w r2, r7, #20 8013b92: 6a7b ldr r3, [r7, #36] @ 0x24 8013b94: 9300 str r3, [sp, #0] 8013b96: 4613 mov r3, r2 8013b98: 6aba ldr r2, [r7, #40] @ 0x28 8013b9a: 2100 movs r1, #0 8013b9c: 2000 movs r0, #0 8013b9e: f003 f823 bl 8016be8 8013ba2: 61f8 str r0, [r7, #28] if (rval == pdPASS) { 8013ba4: 69fb ldr r3, [r7, #28] 8013ba6: 2b01 cmp r3, #1 8013ba8: d137 bne.n 8013c1a rflags &= flags; 8013baa: 6afa ldr r2, [r7, #44] @ 0x2c 8013bac: 68fb ldr r3, [r7, #12] 8013bae: 4013 ands r3, r2 8013bb0: 62fb str r3, [r7, #44] @ 0x2c rflags |= nval; 8013bb2: 697b ldr r3, [r7, #20] 8013bb4: 6afa ldr r2, [r7, #44] @ 0x2c 8013bb6: 4313 orrs r3, r2 8013bb8: 62fb str r3, [r7, #44] @ 0x2c if ((options & osFlagsWaitAll) == osFlagsWaitAll) { 8013bba: 68bb ldr r3, [r7, #8] 8013bbc: f003 0301 and.w r3, r3, #1 8013bc0: 2b00 cmp r3, #0 8013bc2: d00c beq.n 8013bde if ((flags & rflags) == flags) { 8013bc4: 68fa ldr r2, [r7, #12] 8013bc6: 6afb ldr r3, [r7, #44] @ 0x2c 8013bc8: 4013 ands r3, r2 8013bca: 68fa ldr r2, [r7, #12] 8013bcc: 429a cmp r2, r3 8013bce: d032 beq.n 8013c36 break; } else { if (timeout == 0U) { 8013bd0: 687b ldr r3, [r7, #4] 8013bd2: 2b00 cmp r3, #0 8013bd4: d10f bne.n 8013bf6 rflags = (uint32_t)osErrorResource; 8013bd6: f06f 0302 mvn.w r3, #2 8013bda: 62fb str r3, [r7, #44] @ 0x2c break; 8013bdc: e02e b.n 8013c3c } } } else { if ((flags & rflags) != 0) { 8013bde: 68fa ldr r2, [r7, #12] 8013be0: 6afb ldr r3, [r7, #44] @ 0x2c 8013be2: 4013 ands r3, r2 8013be4: 2b00 cmp r3, #0 8013be6: d128 bne.n 8013c3a break; } else { if (timeout == 0U) { 8013be8: 687b ldr r3, [r7, #4] 8013bea: 2b00 cmp r3, #0 8013bec: d103 bne.n 8013bf6 rflags = (uint32_t)osErrorResource; 8013bee: f06f 0302 mvn.w r3, #2 8013bf2: 62fb str r3, [r7, #44] @ 0x2c break; 8013bf4: e022 b.n 8013c3c } } } /* Update timeout */ td = xTaskGetTickCount() - t0; 8013bf6: f002 f913 bl 8015e20 8013bfa: 4602 mov r2, r0 8013bfc: 6a3b ldr r3, [r7, #32] 8013bfe: 1ad3 subs r3, r2, r3 8013c00: 61bb str r3, [r7, #24] if (td > timeout) { 8013c02: 69ba ldr r2, [r7, #24] 8013c04: 687b ldr r3, [r7, #4] 8013c06: 429a cmp r2, r3 8013c08: d902 bls.n 8013c10 tout = 0; 8013c0a: 2300 movs r3, #0 8013c0c: 627b str r3, [r7, #36] @ 0x24 8013c0e: e00e b.n 8013c2e } else { tout = timeout - td; 8013c10: 687a ldr r2, [r7, #4] 8013c12: 69bb ldr r3, [r7, #24] 8013c14: 1ad3 subs r3, r2, r3 8013c16: 627b str r3, [r7, #36] @ 0x24 8013c18: e009 b.n 8013c2e } } else { if (timeout == 0) { 8013c1a: 687b ldr r3, [r7, #4] 8013c1c: 2b00 cmp r3, #0 8013c1e: d103 bne.n 8013c28 rflags = (uint32_t)osErrorResource; 8013c20: f06f 0302 mvn.w r3, #2 8013c24: 62fb str r3, [r7, #44] @ 0x2c 8013c26: e002 b.n 8013c2e } else { rflags = (uint32_t)osErrorTimeout; 8013c28: f06f 0301 mvn.w r3, #1 8013c2c: 62fb str r3, [r7, #44] @ 0x2c } } } while (rval != pdFAIL); 8013c2e: 69fb ldr r3, [r7, #28] 8013c30: 2b00 cmp r3, #0 8013c32: d1ac bne.n 8013b8e 8013c34: e002 b.n 8013c3c break; 8013c36: bf00 nop 8013c38: e000 b.n 8013c3c break; 8013c3a: bf00 nop } /* Return flags before clearing */ return (rflags); 8013c3c: 6afb ldr r3, [r7, #44] @ 0x2c } 8013c3e: 4618 mov r0, r3 8013c40: 3730 adds r7, #48 @ 0x30 8013c42: 46bd mov sp, r7 8013c44: bd80 pop {r7, pc} 08013c46 : Limitations: - Priority inherit protocol is used by default, osMutexPrioInherit attribute is ignored. - Robust mutex is not supported, NULL is returned if used. */ osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 8013c46: b580 push {r7, lr} 8013c48: b086 sub sp, #24 8013c4a: af00 add r7, sp, #0 8013c4c: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; uint32_t type; uint32_t rmtx; int32_t mem; hMutex = NULL; 8013c4e: 2300 movs r3, #0 8013c50: 617b str r3, [r7, #20] if (IRQ_Context() == 0U) { 8013c52: f7ff fe0a bl 801386a 8013c56: 4603 mov r3, r0 8013c58: 2b00 cmp r3, #0 8013c5a: d174 bne.n 8013d46 if (attr != NULL) { 8013c5c: 687b ldr r3, [r7, #4] 8013c5e: 2b00 cmp r3, #0 8013c60: d003 beq.n 8013c6a type = attr->attr_bits; 8013c62: 687b ldr r3, [r7, #4] 8013c64: 685b ldr r3, [r3, #4] 8013c66: 613b str r3, [r7, #16] 8013c68: e001 b.n 8013c6e } else { type = 0U; 8013c6a: 2300 movs r3, #0 8013c6c: 613b str r3, [r7, #16] } if ((type & osMutexRecursive) == osMutexRecursive) { 8013c6e: 693b ldr r3, [r7, #16] 8013c70: f003 0301 and.w r3, r3, #1 8013c74: 2b00 cmp r3, #0 8013c76: d002 beq.n 8013c7e rmtx = 1U; 8013c78: 2301 movs r3, #1 8013c7a: 60fb str r3, [r7, #12] 8013c7c: e001 b.n 8013c82 } else { rmtx = 0U; 8013c7e: 2300 movs r3, #0 8013c80: 60fb str r3, [r7, #12] } if ((type & osMutexRobust) != osMutexRobust) { 8013c82: 693b ldr r3, [r7, #16] 8013c84: f003 0308 and.w r3, r3, #8 8013c88: 2b00 cmp r3, #0 8013c8a: d15c bne.n 8013d46 mem = -1; 8013c8c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013c90: 60bb str r3, [r7, #8] if (attr != NULL) { 8013c92: 687b ldr r3, [r7, #4] 8013c94: 2b00 cmp r3, #0 8013c96: d015 beq.n 8013cc4 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 8013c98: 687b ldr r3, [r7, #4] 8013c9a: 689b ldr r3, [r3, #8] 8013c9c: 2b00 cmp r3, #0 8013c9e: d006 beq.n 8013cae 8013ca0: 687b ldr r3, [r7, #4] 8013ca2: 68db ldr r3, [r3, #12] 8013ca4: 2b4f cmp r3, #79 @ 0x4f 8013ca6: d902 bls.n 8013cae /* The memory for control block is provided, use static object */ mem = 1; 8013ca8: 2301 movs r3, #1 8013caa: 60bb str r3, [r7, #8] 8013cac: e00c b.n 8013cc8 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8013cae: 687b ldr r3, [r7, #4] 8013cb0: 689b ldr r3, [r3, #8] 8013cb2: 2b00 cmp r3, #0 8013cb4: d108 bne.n 8013cc8 8013cb6: 687b ldr r3, [r7, #4] 8013cb8: 68db ldr r3, [r3, #12] 8013cba: 2b00 cmp r3, #0 8013cbc: d104 bne.n 8013cc8 /* Control block will be allocated from the dynamic pool */ mem = 0; 8013cbe: 2300 movs r3, #0 8013cc0: 60bb str r3, [r7, #8] 8013cc2: e001 b.n 8013cc8 } } } else { mem = 0; 8013cc4: 2300 movs r3, #0 8013cc6: 60bb str r3, [r7, #8] } if (mem == 1) { 8013cc8: 68bb ldr r3, [r7, #8] 8013cca: 2b01 cmp r3, #1 8013ccc: d112 bne.n 8013cf4 #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 8013cce: 68fb ldr r3, [r7, #12] 8013cd0: 2b00 cmp r3, #0 8013cd2: d007 beq.n 8013ce4 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 8013cd4: 687b ldr r3, [r7, #4] 8013cd6: 689b ldr r3, [r3, #8] 8013cd8: 4619 mov r1, r3 8013cda: 2004 movs r0, #4 8013cdc: f000 fd63 bl 80147a6 8013ce0: 6178 str r0, [r7, #20] 8013ce2: e016 b.n 8013d12 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 8013ce4: 687b ldr r3, [r7, #4] 8013ce6: 689b ldr r3, [r3, #8] 8013ce8: 4619 mov r1, r3 8013cea: 2001 movs r0, #1 8013cec: f000 fd5b bl 80147a6 8013cf0: 6178 str r0, [r7, #20] 8013cf2: e00e b.n 8013d12 } #endif } else { if (mem == 0) { 8013cf4: 68bb ldr r3, [r7, #8] 8013cf6: 2b00 cmp r3, #0 8013cf8: d10b bne.n 8013d12 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 8013cfa: 68fb ldr r3, [r7, #12] 8013cfc: 2b00 cmp r3, #0 8013cfe: d004 beq.n 8013d0a #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 8013d00: 2004 movs r0, #4 8013d02: f000 fd38 bl 8014776 8013d06: 6178 str r0, [r7, #20] 8013d08: e003 b.n 8013d12 #endif } else { hMutex = xSemaphoreCreateMutex (); 8013d0a: 2001 movs r0, #1 8013d0c: f000 fd33 bl 8014776 8013d10: 6178 str r0, [r7, #20] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8013d12: 697b ldr r3, [r7, #20] 8013d14: 2b00 cmp r3, #0 8013d16: d00c beq.n 8013d32 if ((attr != NULL) && (attr->name != NULL)) { 8013d18: 687b ldr r3, [r7, #4] 8013d1a: 2b00 cmp r3, #0 8013d1c: d009 beq.n 8013d32 8013d1e: 687b ldr r3, [r7, #4] 8013d20: 681b ldr r3, [r3, #0] 8013d22: 2b00 cmp r3, #0 8013d24: d005 beq.n 8013d32 /* Only non-NULL name objects are added to the Queue Registry */ vQueueAddToRegistry (hMutex, attr->name); 8013d26: 687b ldr r3, [r7, #4] 8013d28: 681b ldr r3, [r3, #0] 8013d2a: 4619 mov r1, r3 8013d2c: 6978 ldr r0, [r7, #20] 8013d2e: f001 fc4b bl 80155c8 } } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 8013d32: 697b ldr r3, [r7, #20] 8013d34: 2b00 cmp r3, #0 8013d36: d006 beq.n 8013d46 8013d38: 68fb ldr r3, [r7, #12] 8013d3a: 2b00 cmp r3, #0 8013d3c: d003 beq.n 8013d46 /* Set LSB as 'recursive mutex flag' */ hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 8013d3e: 697b ldr r3, [r7, #20] 8013d40: f043 0301 orr.w r3, r3, #1 8013d44: 617b str r3, [r7, #20] } } } /* Return mutex ID */ return ((osMutexId_t)hMutex); 8013d46: 697b ldr r3, [r7, #20] } 8013d48: 4618 mov r0, r3 8013d4a: 3718 adds r7, #24 8013d4c: 46bd mov sp, r7 8013d4e: bd80 pop {r7, pc} 08013d50 : /* Acquire a Mutex or timeout if it is locked. */ osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 8013d50: b580 push {r7, lr} 8013d52: b086 sub sp, #24 8013d54: af00 add r7, sp, #0 8013d56: 6078 str r0, [r7, #4] 8013d58: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8013d5a: 687b ldr r3, [r7, #4] 8013d5c: f023 0301 bic.w r3, r3, #1 8013d60: 613b str r3, [r7, #16] /* Extract recursive mutex flag */ rmtx = (uint32_t)mutex_id & 1U; 8013d62: 687b ldr r3, [r7, #4] 8013d64: f003 0301 and.w r3, r3, #1 8013d68: 60fb str r3, [r7, #12] stat = osOK; 8013d6a: 2300 movs r3, #0 8013d6c: 617b str r3, [r7, #20] if (IRQ_Context() != 0U) { 8013d6e: f7ff fd7c bl 801386a 8013d72: 4603 mov r3, r0 8013d74: 2b00 cmp r3, #0 8013d76: d003 beq.n 8013d80 stat = osErrorISR; 8013d78: f06f 0305 mvn.w r3, #5 8013d7c: 617b str r3, [r7, #20] 8013d7e: e02c b.n 8013dda } else if (hMutex == NULL) { 8013d80: 693b ldr r3, [r7, #16] 8013d82: 2b00 cmp r3, #0 8013d84: d103 bne.n 8013d8e stat = osErrorParameter; 8013d86: f06f 0303 mvn.w r3, #3 8013d8a: 617b str r3, [r7, #20] 8013d8c: e025 b.n 8013dda } else { if (rmtx != 0U) { 8013d8e: 68fb ldr r3, [r7, #12] 8013d90: 2b00 cmp r3, #0 8013d92: d011 beq.n 8013db8 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 8013d94: 6839 ldr r1, [r7, #0] 8013d96: 6938 ldr r0, [r7, #16] 8013d98: f000 fd55 bl 8014846 8013d9c: 4603 mov r3, r0 8013d9e: 2b01 cmp r3, #1 8013da0: d01b beq.n 8013dda if (timeout != 0U) { 8013da2: 683b ldr r3, [r7, #0] 8013da4: 2b00 cmp r3, #0 8013da6: d003 beq.n 8013db0 stat = osErrorTimeout; 8013da8: f06f 0301 mvn.w r3, #1 8013dac: 617b str r3, [r7, #20] 8013dae: e014 b.n 8013dda } else { stat = osErrorResource; 8013db0: f06f 0302 mvn.w r3, #2 8013db4: 617b str r3, [r7, #20] 8013db6: e010 b.n 8013dda } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 8013db8: 6839 ldr r1, [r7, #0] 8013dba: 6938 ldr r0, [r7, #16] 8013dbc: f001 f91e bl 8014ffc 8013dc0: 4603 mov r3, r0 8013dc2: 2b01 cmp r3, #1 8013dc4: d009 beq.n 8013dda if (timeout != 0U) { 8013dc6: 683b ldr r3, [r7, #0] 8013dc8: 2b00 cmp r3, #0 8013dca: d003 beq.n 8013dd4 stat = osErrorTimeout; 8013dcc: f06f 0301 mvn.w r3, #1 8013dd0: 617b str r3, [r7, #20] 8013dd2: e002 b.n 8013dda } else { stat = osErrorResource; 8013dd4: f06f 0302 mvn.w r3, #2 8013dd8: 617b str r3, [r7, #20] } } } /* Return execution status */ return (stat); 8013dda: 697b ldr r3, [r7, #20] } 8013ddc: 4618 mov r0, r3 8013dde: 3718 adds r7, #24 8013de0: 46bd mov sp, r7 8013de2: bd80 pop {r7, pc} 08013de4 : /* Release a Mutex that was acquired by osMutexAcquire. */ osStatus_t osMutexRelease (osMutexId_t mutex_id) { 8013de4: b580 push {r7, lr} 8013de6: b086 sub sp, #24 8013de8: af00 add r7, sp, #0 8013dea: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8013dec: 687b ldr r3, [r7, #4] 8013dee: f023 0301 bic.w r3, r3, #1 8013df2: 613b str r3, [r7, #16] /* Extract recursive mutex flag */ rmtx = (uint32_t)mutex_id & 1U; 8013df4: 687b ldr r3, [r7, #4] 8013df6: f003 0301 and.w r3, r3, #1 8013dfa: 60fb str r3, [r7, #12] stat = osOK; 8013dfc: 2300 movs r3, #0 8013dfe: 617b str r3, [r7, #20] if (IRQ_Context() != 0U) { 8013e00: f7ff fd33 bl 801386a 8013e04: 4603 mov r3, r0 8013e06: 2b00 cmp r3, #0 8013e08: d003 beq.n 8013e12 stat = osErrorISR; 8013e0a: f06f 0305 mvn.w r3, #5 8013e0e: 617b str r3, [r7, #20] 8013e10: e01f b.n 8013e52 } else if (hMutex == NULL) { 8013e12: 693b ldr r3, [r7, #16] 8013e14: 2b00 cmp r3, #0 8013e16: d103 bne.n 8013e20 stat = osErrorParameter; 8013e18: f06f 0303 mvn.w r3, #3 8013e1c: 617b str r3, [r7, #20] 8013e1e: e018 b.n 8013e52 } else { if (rmtx != 0U) { 8013e20: 68fb ldr r3, [r7, #12] 8013e22: 2b00 cmp r3, #0 8013e24: d009 beq.n 8013e3a #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 8013e26: 6938 ldr r0, [r7, #16] 8013e28: f000 fcd8 bl 80147dc 8013e2c: 4603 mov r3, r0 8013e2e: 2b01 cmp r3, #1 8013e30: d00f beq.n 8013e52 stat = osErrorResource; 8013e32: f06f 0302 mvn.w r3, #2 8013e36: 617b str r3, [r7, #20] 8013e38: e00b b.n 8013e52 } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 8013e3a: 2300 movs r3, #0 8013e3c: 2200 movs r2, #0 8013e3e: 2100 movs r1, #0 8013e40: 6938 ldr r0, [r7, #16] 8013e42: f000 fd99 bl 8014978 8013e46: 4603 mov r3, r0 8013e48: 2b01 cmp r3, #1 8013e4a: d002 beq.n 8013e52 stat = osErrorResource; 8013e4c: f06f 0302 mvn.w r3, #2 8013e50: 617b str r3, [r7, #20] } } } /* Return execution status */ return (stat); 8013e52: 697b ldr r3, [r7, #20] } 8013e54: 4618 mov r0, r3 8013e56: 3718 adds r7, #24 8013e58: 46bd mov sp, r7 8013e5a: bd80 pop {r7, pc} 08013e5c : /* ==== Semaphore Management Functions ==== */ /* Create and Initialize a Semaphore object. */ osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { 8013e5c: b580 push {r7, lr} 8013e5e: b088 sub sp, #32 8013e60: af02 add r7, sp, #8 8013e62: 60f8 str r0, [r7, #12] 8013e64: 60b9 str r1, [r7, #8] 8013e66: 607a str r2, [r7, #4] SemaphoreHandle_t hSemaphore; int32_t mem; hSemaphore = NULL; 8013e68: 2300 movs r3, #0 8013e6a: 617b str r3, [r7, #20] if ((IRQ_Context() == 0U) && (max_count > 0U) && (initial_count <= max_count)) { 8013e6c: f7ff fcfd bl 801386a 8013e70: 4603 mov r3, r0 8013e72: 2b00 cmp r3, #0 8013e74: d175 bne.n 8013f62 8013e76: 68fb ldr r3, [r7, #12] 8013e78: 2b00 cmp r3, #0 8013e7a: d072 beq.n 8013f62 8013e7c: 68ba ldr r2, [r7, #8] 8013e7e: 68fb ldr r3, [r7, #12] 8013e80: 429a cmp r2, r3 8013e82: d86e bhi.n 8013f62 mem = -1; 8013e84: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013e88: 613b str r3, [r7, #16] if (attr != NULL) { 8013e8a: 687b ldr r3, [r7, #4] 8013e8c: 2b00 cmp r3, #0 8013e8e: d015 beq.n 8013ebc if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 8013e90: 687b ldr r3, [r7, #4] 8013e92: 689b ldr r3, [r3, #8] 8013e94: 2b00 cmp r3, #0 8013e96: d006 beq.n 8013ea6 8013e98: 687b ldr r3, [r7, #4] 8013e9a: 68db ldr r3, [r3, #12] 8013e9c: 2b4f cmp r3, #79 @ 0x4f 8013e9e: d902 bls.n 8013ea6 /* The memory for control block is provided, use static object */ mem = 1; 8013ea0: 2301 movs r3, #1 8013ea2: 613b str r3, [r7, #16] 8013ea4: e00c b.n 8013ec0 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8013ea6: 687b ldr r3, [r7, #4] 8013ea8: 689b ldr r3, [r3, #8] 8013eaa: 2b00 cmp r3, #0 8013eac: d108 bne.n 8013ec0 8013eae: 687b ldr r3, [r7, #4] 8013eb0: 68db ldr r3, [r3, #12] 8013eb2: 2b00 cmp r3, #0 8013eb4: d104 bne.n 8013ec0 /* Control block will be allocated from the dynamic pool */ mem = 0; 8013eb6: 2300 movs r3, #0 8013eb8: 613b str r3, [r7, #16] 8013eba: e001 b.n 8013ec0 } } } else { mem = 0; 8013ebc: 2300 movs r3, #0 8013ebe: 613b str r3, [r7, #16] } if (mem != -1) { 8013ec0: 693b ldr r3, [r7, #16] 8013ec2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013ec6: d04c beq.n 8013f62 if (max_count == 1U) { 8013ec8: 68fb ldr r3, [r7, #12] 8013eca: 2b01 cmp r3, #1 8013ecc: d128 bne.n 8013f20 if (mem == 1) { 8013ece: 693b ldr r3, [r7, #16] 8013ed0: 2b01 cmp r3, #1 8013ed2: d10a bne.n 8013eea #if (configSUPPORT_STATIC_ALLOCATION == 1) hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem); 8013ed4: 687b ldr r3, [r7, #4] 8013ed6: 689b ldr r3, [r3, #8] 8013ed8: 2203 movs r2, #3 8013eda: 9200 str r2, [sp, #0] 8013edc: 2200 movs r2, #0 8013ede: 2100 movs r1, #0 8013ee0: 2001 movs r0, #1 8013ee2: f000 fb57 bl 8014594 8013ee6: 6178 str r0, [r7, #20] 8013ee8: e005 b.n 8013ef6 #endif } else { #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hSemaphore = xSemaphoreCreateBinary(); 8013eea: 2203 movs r2, #3 8013eec: 2100 movs r1, #0 8013eee: 2001 movs r0, #1 8013ef0: f000 fbb1 bl 8014656 8013ef4: 6178 str r0, [r7, #20] #endif } if ((hSemaphore != NULL) && (initial_count != 0U)) { 8013ef6: 697b ldr r3, [r7, #20] 8013ef8: 2b00 cmp r3, #0 8013efa: d022 beq.n 8013f42 8013efc: 68bb ldr r3, [r7, #8] 8013efe: 2b00 cmp r3, #0 8013f00: d01f beq.n 8013f42 if (xSemaphoreGive (hSemaphore) != pdPASS) { 8013f02: 2300 movs r3, #0 8013f04: 2200 movs r2, #0 8013f06: 2100 movs r1, #0 8013f08: 6978 ldr r0, [r7, #20] 8013f0a: f000 fd35 bl 8014978 8013f0e: 4603 mov r3, r0 8013f10: 2b01 cmp r3, #1 8013f12: d016 beq.n 8013f42 vSemaphoreDelete (hSemaphore); 8013f14: 6978 ldr r0, [r7, #20] 8013f16: f001 fa0b bl 8015330 hSemaphore = NULL; 8013f1a: 2300 movs r3, #0 8013f1c: 617b str r3, [r7, #20] 8013f1e: e010 b.n 8013f42 } } } else { if (mem == 1) { 8013f20: 693b ldr r3, [r7, #16] 8013f22: 2b01 cmp r3, #1 8013f24: d108 bne.n 8013f38 #if (configSUPPORT_STATIC_ALLOCATION == 1) hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem); 8013f26: 687b ldr r3, [r7, #4] 8013f28: 689b ldr r3, [r3, #8] 8013f2a: 461a mov r2, r3 8013f2c: 68b9 ldr r1, [r7, #8] 8013f2e: 68f8 ldr r0, [r7, #12] 8013f30: f000 fcc0 bl 80148b4 8013f34: 6178 str r0, [r7, #20] 8013f36: e004 b.n 8013f42 #endif } else { #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hSemaphore = xSemaphoreCreateCounting (max_count, initial_count); 8013f38: 68b9 ldr r1, [r7, #8] 8013f3a: 68f8 ldr r0, [r7, #12] 8013f3c: f000 fced bl 801491a 8013f40: 6178 str r0, [r7, #20] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hSemaphore != NULL) { 8013f42: 697b ldr r3, [r7, #20] 8013f44: 2b00 cmp r3, #0 8013f46: d00c beq.n 8013f62 if ((attr != NULL) && (attr->name != NULL)) { 8013f48: 687b ldr r3, [r7, #4] 8013f4a: 2b00 cmp r3, #0 8013f4c: d009 beq.n 8013f62 8013f4e: 687b ldr r3, [r7, #4] 8013f50: 681b ldr r3, [r3, #0] 8013f52: 2b00 cmp r3, #0 8013f54: d005 beq.n 8013f62 /* Only non-NULL name objects are added to the Queue Registry */ vQueueAddToRegistry (hSemaphore, attr->name); 8013f56: 687b ldr r3, [r7, #4] 8013f58: 681b ldr r3, [r3, #0] 8013f5a: 4619 mov r1, r3 8013f5c: 6978 ldr r0, [r7, #20] 8013f5e: f001 fb33 bl 80155c8 #endif } } /* Return semaphore ID */ return ((osSemaphoreId_t)hSemaphore); 8013f62: 697b ldr r3, [r7, #20] } 8013f64: 4618 mov r0, r3 8013f66: 3718 adds r7, #24 8013f68: 46bd mov sp, r7 8013f6a: bd80 pop {r7, pc} 08013f6c : /* Acquire a Semaphore token or timeout if no tokens are available. */ osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { 8013f6c: b580 push {r7, lr} 8013f6e: b086 sub sp, #24 8013f70: af00 add r7, sp, #0 8013f72: 6078 str r0, [r7, #4] 8013f74: 6039 str r1, [r7, #0] SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; 8013f76: 687b ldr r3, [r7, #4] 8013f78: 613b str r3, [r7, #16] osStatus_t stat; BaseType_t yield; stat = osOK; 8013f7a: 2300 movs r3, #0 8013f7c: 617b str r3, [r7, #20] if (hSemaphore == NULL) { 8013f7e: 693b ldr r3, [r7, #16] 8013f80: 2b00 cmp r3, #0 8013f82: d103 bne.n 8013f8c stat = osErrorParameter; 8013f84: f06f 0303 mvn.w r3, #3 8013f88: 617b str r3, [r7, #20] 8013f8a: e038 b.n 8013ffe } else if (IRQ_Context() != 0U) { 8013f8c: f7ff fc6d bl 801386a 8013f90: 4603 mov r3, r0 8013f92: 2b00 cmp r3, #0 8013f94: d022 beq.n 8013fdc if (timeout != 0U) { 8013f96: 683b ldr r3, [r7, #0] 8013f98: 2b00 cmp r3, #0 8013f9a: d003 beq.n 8013fa4 stat = osErrorParameter; 8013f9c: f06f 0303 mvn.w r3, #3 8013fa0: 617b str r3, [r7, #20] 8013fa2: e02c b.n 8013ffe } else { yield = pdFALSE; 8013fa4: 2300 movs r3, #0 8013fa6: 60fb str r3, [r7, #12] if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) { 8013fa8: f107 030c add.w r3, r7, #12 8013fac: 461a mov r2, r3 8013fae: 2100 movs r1, #0 8013fb0: 6938 ldr r0, [r7, #16] 8013fb2: f001 f923 bl 80151fc 8013fb6: 4603 mov r3, r0 8013fb8: 2b01 cmp r3, #1 8013fba: d003 beq.n 8013fc4 stat = osErrorResource; 8013fbc: f06f 0302 mvn.w r3, #2 8013fc0: 617b str r3, [r7, #20] 8013fc2: e01c b.n 8013ffe } else { portYIELD_FROM_ISR (yield); 8013fc4: 68fb ldr r3, [r7, #12] 8013fc6: 2b00 cmp r3, #0 8013fc8: d019 beq.n 8013ffe 8013fca: 4b0f ldr r3, [pc, #60] @ (8014008 ) 8013fcc: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013fd0: 601a str r2, [r3, #0] 8013fd2: f3bf 8f4f dsb sy 8013fd6: f3bf 8f6f isb sy 8013fda: e010 b.n 8013ffe } } } else { if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) { 8013fdc: 6839 ldr r1, [r7, #0] 8013fde: 6938 ldr r0, [r7, #16] 8013fe0: f001 f80c bl 8014ffc 8013fe4: 4603 mov r3, r0 8013fe6: 2b01 cmp r3, #1 8013fe8: d009 beq.n 8013ffe if (timeout != 0U) { 8013fea: 683b ldr r3, [r7, #0] 8013fec: 2b00 cmp r3, #0 8013fee: d003 beq.n 8013ff8 stat = osErrorTimeout; 8013ff0: f06f 0301 mvn.w r3, #1 8013ff4: 617b str r3, [r7, #20] 8013ff6: e002 b.n 8013ffe } else { stat = osErrorResource; 8013ff8: f06f 0302 mvn.w r3, #2 8013ffc: 617b str r3, [r7, #20] } } } /* Return execution status */ return (stat); 8013ffe: 697b ldr r3, [r7, #20] } 8014000: 4618 mov r0, r3 8014002: 3718 adds r7, #24 8014004: 46bd mov sp, r7 8014006: bd80 pop {r7, pc} 8014008: e000ed04 .word 0xe000ed04 0801400c : /* Release a Semaphore token up to the initial maximum count. */ osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { 801400c: b580 push {r7, lr} 801400e: b086 sub sp, #24 8014010: af00 add r7, sp, #0 8014012: 6078 str r0, [r7, #4] SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; 8014014: 687b ldr r3, [r7, #4] 8014016: 613b str r3, [r7, #16] osStatus_t stat; BaseType_t yield; stat = osOK; 8014018: 2300 movs r3, #0 801401a: 617b str r3, [r7, #20] if (hSemaphore == NULL) { 801401c: 693b ldr r3, [r7, #16] 801401e: 2b00 cmp r3, #0 8014020: d103 bne.n 801402a stat = osErrorParameter; 8014022: f06f 0303 mvn.w r3, #3 8014026: 617b str r3, [r7, #20] 8014028: e02b b.n 8014082 } else if (IRQ_Context() != 0U) { 801402a: f7ff fc1e bl 801386a 801402e: 4603 mov r3, r0 8014030: 2b00 cmp r3, #0 8014032: d01a beq.n 801406a yield = pdFALSE; 8014034: 2300 movs r3, #0 8014036: 60fb str r3, [r7, #12] if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) { 8014038: f107 030c add.w r3, r7, #12 801403c: 4619 mov r1, r3 801403e: 6938 ldr r0, [r7, #16] 8014040: f000 fe52 bl 8014ce8 8014044: 4603 mov r3, r0 8014046: 2b01 cmp r3, #1 8014048: d003 beq.n 8014052 stat = osErrorResource; 801404a: f06f 0302 mvn.w r3, #2 801404e: 617b str r3, [r7, #20] 8014050: e017 b.n 8014082 } else { portYIELD_FROM_ISR (yield); 8014052: 68fb ldr r3, [r7, #12] 8014054: 2b00 cmp r3, #0 8014056: d014 beq.n 8014082 8014058: 4b0c ldr r3, [pc, #48] @ (801408c ) 801405a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801405e: 601a str r2, [r3, #0] 8014060: f3bf 8f4f dsb sy 8014064: f3bf 8f6f isb sy 8014068: e00b b.n 8014082 } } else { if (xSemaphoreGive (hSemaphore) != pdPASS) { 801406a: 2300 movs r3, #0 801406c: 2200 movs r2, #0 801406e: 2100 movs r1, #0 8014070: 6938 ldr r0, [r7, #16] 8014072: f000 fc81 bl 8014978 8014076: 4603 mov r3, r0 8014078: 2b01 cmp r3, #1 801407a: d002 beq.n 8014082 stat = osErrorResource; 801407c: f06f 0302 mvn.w r3, #2 8014080: 617b str r3, [r7, #20] } } /* Return execution status */ return (stat); 8014082: 697b ldr r3, [r7, #20] } 8014084: 4618 mov r0, r3 8014086: 3718 adds r7, #24 8014088: 46bd mov sp, r7 801408a: bd80 pop {r7, pc} 801408c: e000ed04 .word 0xe000ed04 08014090 : Limitations: - The memory for control block and and message data must be provided in the osThreadAttr_t structure in order to allocate object statically. */ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 8014090: b580 push {r7, lr} 8014092: b088 sub sp, #32 8014094: af02 add r7, sp, #8 8014096: 60f8 str r0, [r7, #12] 8014098: 60b9 str r1, [r7, #8] 801409a: 607a str r2, [r7, #4] QueueHandle_t hQueue; int32_t mem; hQueue = NULL; 801409c: 2300 movs r3, #0 801409e: 617b str r3, [r7, #20] if ((IRQ_Context() == 0U) && (msg_count > 0U) && (msg_size > 0U)) { 80140a0: f7ff fbe3 bl 801386a 80140a4: 4603 mov r3, r0 80140a6: 2b00 cmp r3, #0 80140a8: d15f bne.n 801416a 80140aa: 68fb ldr r3, [r7, #12] 80140ac: 2b00 cmp r3, #0 80140ae: d05c beq.n 801416a 80140b0: 68bb ldr r3, [r7, #8] 80140b2: 2b00 cmp r3, #0 80140b4: d059 beq.n 801416a mem = -1; 80140b6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80140ba: 613b str r3, [r7, #16] if (attr != NULL) { 80140bc: 687b ldr r3, [r7, #4] 80140be: 2b00 cmp r3, #0 80140c0: d029 beq.n 8014116 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 80140c2: 687b ldr r3, [r7, #4] 80140c4: 689b ldr r3, [r3, #8] 80140c6: 2b00 cmp r3, #0 80140c8: d012 beq.n 80140f0 80140ca: 687b ldr r3, [r7, #4] 80140cc: 68db ldr r3, [r3, #12] 80140ce: 2b4f cmp r3, #79 @ 0x4f 80140d0: d90e bls.n 80140f0 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 80140d2: 687b ldr r3, [r7, #4] 80140d4: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 80140d6: 2b00 cmp r3, #0 80140d8: d00a beq.n 80140f0 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 80140da: 687b ldr r3, [r7, #4] 80140dc: 695a ldr r2, [r3, #20] 80140de: 68fb ldr r3, [r7, #12] 80140e0: 68b9 ldr r1, [r7, #8] 80140e2: fb01 f303 mul.w r3, r1, r3 80140e6: 429a cmp r2, r3 80140e8: d302 bcc.n 80140f0 /* The memory for control block and message data is provided, use static object */ mem = 1; 80140ea: 2301 movs r3, #1 80140ec: 613b str r3, [r7, #16] 80140ee: e014 b.n 801411a } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 80140f0: 687b ldr r3, [r7, #4] 80140f2: 689b ldr r3, [r3, #8] 80140f4: 2b00 cmp r3, #0 80140f6: d110 bne.n 801411a 80140f8: 687b ldr r3, [r7, #4] 80140fa: 68db ldr r3, [r3, #12] 80140fc: 2b00 cmp r3, #0 80140fe: d10c bne.n 801411a (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8014100: 687b ldr r3, [r7, #4] 8014102: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8014104: 2b00 cmp r3, #0 8014106: d108 bne.n 801411a (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8014108: 687b ldr r3, [r7, #4] 801410a: 695b ldr r3, [r3, #20] 801410c: 2b00 cmp r3, #0 801410e: d104 bne.n 801411a /* Control block will be allocated from the dynamic pool */ mem = 0; 8014110: 2300 movs r3, #0 8014112: 613b str r3, [r7, #16] 8014114: e001 b.n 801411a } } } else { mem = 0; 8014116: 2300 movs r3, #0 8014118: 613b str r3, [r7, #16] } if (mem == 1) { 801411a: 693b ldr r3, [r7, #16] 801411c: 2b01 cmp r3, #1 801411e: d10b bne.n 8014138 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8014120: 687b ldr r3, [r7, #4] 8014122: 691a ldr r2, [r3, #16] 8014124: 687b ldr r3, [r7, #4] 8014126: 689b ldr r3, [r3, #8] 8014128: 2100 movs r1, #0 801412a: 9100 str r1, [sp, #0] 801412c: 68b9 ldr r1, [r7, #8] 801412e: 68f8 ldr r0, [r7, #12] 8014130: f000 fa30 bl 8014594 8014134: 6178 str r0, [r7, #20] 8014136: e008 b.n 801414a #endif } else { if (mem == 0) { 8014138: 693b ldr r3, [r7, #16] 801413a: 2b00 cmp r3, #0 801413c: d105 bne.n 801414a #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 801413e: 2200 movs r2, #0 8014140: 68b9 ldr r1, [r7, #8] 8014142: 68f8 ldr r0, [r7, #12] 8014144: f000 fa87 bl 8014656 8014148: 6178 str r0, [r7, #20] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 801414a: 697b ldr r3, [r7, #20] 801414c: 2b00 cmp r3, #0 801414e: d00c beq.n 801416a if ((attr != NULL) && (attr->name != NULL)) { 8014150: 687b ldr r3, [r7, #4] 8014152: 2b00 cmp r3, #0 8014154: d009 beq.n 801416a 8014156: 687b ldr r3, [r7, #4] 8014158: 681b ldr r3, [r3, #0] 801415a: 2b00 cmp r3, #0 801415c: d005 beq.n 801416a /* Only non-NULL name objects are added to the Queue Registry */ vQueueAddToRegistry (hQueue, attr->name); 801415e: 687b ldr r3, [r7, #4] 8014160: 681b ldr r3, [r3, #0] 8014162: 4619 mov r1, r3 8014164: 6978 ldr r0, [r7, #20] 8014166: f001 fa2f bl 80155c8 #endif } /* Return message queue ID */ return ((osMessageQueueId_t)hQueue); 801416a: 697b ldr r3, [r7, #20] } 801416c: 4618 mov r0, r3 801416e: 3718 adds r7, #24 8014170: 46bd mov sp, r7 8014172: bd80 pop {r7, pc} 08014174 : Put a Message into a Queue or timeout if Queue is full. Limitations: - Message priority is ignored */ osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 8014174: b580 push {r7, lr} 8014176: b088 sub sp, #32 8014178: af00 add r7, sp, #0 801417a: 60f8 str r0, [r7, #12] 801417c: 60b9 str r1, [r7, #8] 801417e: 603b str r3, [r7, #0] 8014180: 4613 mov r3, r2 8014182: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8014184: 68fb ldr r3, [r7, #12] 8014186: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8014188: 2300 movs r3, #0 801418a: 61fb str r3, [r7, #28] if (IRQ_Context() != 0U) { 801418c: f7ff fb6d bl 801386a 8014190: 4603 mov r3, r0 8014192: 2b00 cmp r3, #0 8014194: d028 beq.n 80141e8 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8014196: 69bb ldr r3, [r7, #24] 8014198: 2b00 cmp r3, #0 801419a: d005 beq.n 80141a8 801419c: 68bb ldr r3, [r7, #8] 801419e: 2b00 cmp r3, #0 80141a0: d002 beq.n 80141a8 80141a2: 683b ldr r3, [r7, #0] 80141a4: 2b00 cmp r3, #0 80141a6: d003 beq.n 80141b0 stat = osErrorParameter; 80141a8: f06f 0303 mvn.w r3, #3 80141ac: 61fb str r3, [r7, #28] 80141ae: e038 b.n 8014222 } else { yield = pdFALSE; 80141b0: 2300 movs r3, #0 80141b2: 617b str r3, [r7, #20] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 80141b4: f107 0214 add.w r2, r7, #20 80141b8: 2300 movs r3, #0 80141ba: 68b9 ldr r1, [r7, #8] 80141bc: 69b8 ldr r0, [r7, #24] 80141be: f000 fcdd bl 8014b7c 80141c2: 4603 mov r3, r0 80141c4: 2b01 cmp r3, #1 80141c6: d003 beq.n 80141d0 stat = osErrorResource; 80141c8: f06f 0302 mvn.w r3, #2 80141cc: 61fb str r3, [r7, #28] 80141ce: e028 b.n 8014222 } else { portYIELD_FROM_ISR (yield); 80141d0: 697b ldr r3, [r7, #20] 80141d2: 2b00 cmp r3, #0 80141d4: d025 beq.n 8014222 80141d6: 4b15 ldr r3, [pc, #84] @ (801422c ) 80141d8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80141dc: 601a str r2, [r3, #0] 80141de: f3bf 8f4f dsb sy 80141e2: f3bf 8f6f isb sy 80141e6: e01c b.n 8014222 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 80141e8: 69bb ldr r3, [r7, #24] 80141ea: 2b00 cmp r3, #0 80141ec: d002 beq.n 80141f4 80141ee: 68bb ldr r3, [r7, #8] 80141f0: 2b00 cmp r3, #0 80141f2: d103 bne.n 80141fc stat = osErrorParameter; 80141f4: f06f 0303 mvn.w r3, #3 80141f8: 61fb str r3, [r7, #28] 80141fa: e012 b.n 8014222 } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 80141fc: 2300 movs r3, #0 80141fe: 683a ldr r2, [r7, #0] 8014200: 68b9 ldr r1, [r7, #8] 8014202: 69b8 ldr r0, [r7, #24] 8014204: f000 fbb8 bl 8014978 8014208: 4603 mov r3, r0 801420a: 2b01 cmp r3, #1 801420c: d009 beq.n 8014222 if (timeout != 0U) { 801420e: 683b ldr r3, [r7, #0] 8014210: 2b00 cmp r3, #0 8014212: d003 beq.n 801421c stat = osErrorTimeout; 8014214: f06f 0301 mvn.w r3, #1 8014218: 61fb str r3, [r7, #28] 801421a: e002 b.n 8014222 } else { stat = osErrorResource; 801421c: f06f 0302 mvn.w r3, #2 8014220: 61fb str r3, [r7, #28] } } } /* Return execution status */ return (stat); 8014222: 69fb ldr r3, [r7, #28] } 8014224: 4618 mov r0, r3 8014226: 3720 adds r7, #32 8014228: 46bd mov sp, r7 801422a: bd80 pop {r7, pc} 801422c: e000ed04 .word 0xe000ed04 08014230 : Get a Message from a Queue or timeout if Queue is empty. Limitations: - Message priority is ignored */ osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 8014230: b580 push {r7, lr} 8014232: b088 sub sp, #32 8014234: af00 add r7, sp, #0 8014236: 60f8 str r0, [r7, #12] 8014238: 60b9 str r1, [r7, #8] 801423a: 607a str r2, [r7, #4] 801423c: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 801423e: 68fb ldr r3, [r7, #12] 8014240: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8014242: 2300 movs r3, #0 8014244: 61fb str r3, [r7, #28] if (IRQ_Context() != 0U) { 8014246: f7ff fb10 bl 801386a 801424a: 4603 mov r3, r0 801424c: 2b00 cmp r3, #0 801424e: d028 beq.n 80142a2 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8014250: 69bb ldr r3, [r7, #24] 8014252: 2b00 cmp r3, #0 8014254: d005 beq.n 8014262 8014256: 68bb ldr r3, [r7, #8] 8014258: 2b00 cmp r3, #0 801425a: d002 beq.n 8014262 801425c: 683b ldr r3, [r7, #0] 801425e: 2b00 cmp r3, #0 8014260: d003 beq.n 801426a stat = osErrorParameter; 8014262: f06f 0303 mvn.w r3, #3 8014266: 61fb str r3, [r7, #28] 8014268: e037 b.n 80142da } else { yield = pdFALSE; 801426a: 2300 movs r3, #0 801426c: 617b str r3, [r7, #20] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 801426e: f107 0314 add.w r3, r7, #20 8014272: 461a mov r2, r3 8014274: 68b9 ldr r1, [r7, #8] 8014276: 69b8 ldr r0, [r7, #24] 8014278: f000 ffc0 bl 80151fc 801427c: 4603 mov r3, r0 801427e: 2b01 cmp r3, #1 8014280: d003 beq.n 801428a stat = osErrorResource; 8014282: f06f 0302 mvn.w r3, #2 8014286: 61fb str r3, [r7, #28] 8014288: e027 b.n 80142da } else { portYIELD_FROM_ISR (yield); 801428a: 697b ldr r3, [r7, #20] 801428c: 2b00 cmp r3, #0 801428e: d024 beq.n 80142da 8014290: 4b14 ldr r3, [pc, #80] @ (80142e4 ) 8014292: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014296: 601a str r2, [r3, #0] 8014298: f3bf 8f4f dsb sy 801429c: f3bf 8f6f isb sy 80142a0: e01b b.n 80142da } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 80142a2: 69bb ldr r3, [r7, #24] 80142a4: 2b00 cmp r3, #0 80142a6: d002 beq.n 80142ae 80142a8: 68bb ldr r3, [r7, #8] 80142aa: 2b00 cmp r3, #0 80142ac: d103 bne.n 80142b6 stat = osErrorParameter; 80142ae: f06f 0303 mvn.w r3, #3 80142b2: 61fb str r3, [r7, #28] 80142b4: e011 b.n 80142da } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 80142b6: 683a ldr r2, [r7, #0] 80142b8: 68b9 ldr r1, [r7, #8] 80142ba: 69b8 ldr r0, [r7, #24] 80142bc: f000 fdbc bl 8014e38 80142c0: 4603 mov r3, r0 80142c2: 2b01 cmp r3, #1 80142c4: d009 beq.n 80142da if (timeout != 0U) { 80142c6: 683b ldr r3, [r7, #0] 80142c8: 2b00 cmp r3, #0 80142ca: d003 beq.n 80142d4 stat = osErrorTimeout; 80142cc: f06f 0301 mvn.w r3, #1 80142d0: 61fb str r3, [r7, #28] 80142d2: e002 b.n 80142da } else { stat = osErrorResource; 80142d4: f06f 0302 mvn.w r3, #2 80142d8: 61fb str r3, [r7, #28] } } } /* Return execution status */ return (stat); 80142da: 69fb ldr r3, [r7, #28] } 80142dc: 4618 mov r0, r3 80142de: 3720 adds r7, #32 80142e0: 46bd mov sp, r7 80142e2: bd80 pop {r7, pc} 80142e4: e000ed04 .word 0xe000ed04 080142e8 : #if (configSUPPORT_STATIC_ALLOCATION == 1) /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 80142e8: b480 push {r7} 80142ea: b085 sub sp, #20 80142ec: af00 add r7, sp, #0 80142ee: 60f8 str r0, [r7, #12] 80142f0: 60b9 str r1, [r7, #8] 80142f2: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 80142f4: 68fb ldr r3, [r7, #12] 80142f6: 4a07 ldr r2, [pc, #28] @ (8014314 ) 80142f8: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 80142fa: 68bb ldr r3, [r7, #8] 80142fc: 4a06 ldr r2, [pc, #24] @ (8014318 ) 80142fe: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8014300: 687b ldr r3, [r7, #4] 8014302: f44f 7200 mov.w r2, #512 @ 0x200 8014306: 601a str r2, [r3, #0] } 8014308: bf00 nop 801430a: 3714 adds r7, #20 801430c: 46bd mov sp, r7 801430e: f85d 7b04 ldr.w r7, [sp], #4 8014312: 4770 bx lr 8014314: 200007d0 .word 0x200007d0 8014318: 2000087c .word 0x2000087c 0801431c : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 801431c: b480 push {r7} 801431e: b085 sub sp, #20 8014320: af00 add r7, sp, #0 8014322: 60f8 str r0, [r7, #12] 8014324: 60b9 str r1, [r7, #8] 8014326: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 8014328: 68fb ldr r3, [r7, #12] 801432a: 4a07 ldr r2, [pc, #28] @ (8014348 ) 801432c: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 801432e: 68bb ldr r3, [r7, #8] 8014330: 4a06 ldr r2, [pc, #24] @ (801434c ) 8014332: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8014334: 687b ldr r3, [r7, #4] 8014336: f44f 6280 mov.w r2, #1024 @ 0x400 801433a: 601a str r2, [r3, #0] } 801433c: bf00 nop 801433e: 3714 adds r7, #20 8014340: 46bd mov sp, r7 8014342: f85d 7b04 ldr.w r7, [sp], #4 8014346: 4770 bx lr 8014348: 2000107c .word 0x2000107c 801434c: 20001128 .word 0x20001128 08014350 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8014350: b480 push {r7} 8014352: b083 sub sp, #12 8014354: af00 add r7, sp, #0 8014356: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the * end of the list. To initialise the list the list end is inserted * as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8014358: 687b ldr r3, [r7, #4] 801435a: f103 0208 add.w r2, r3, #8 801435e: 687b ldr r3, [r7, #4] 8014360: 605a str r2, [r3, #4] listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); /* The list end value is the highest possible value in the list to * ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 8014362: 687b ldr r3, [r7, #4] 8014364: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8014368: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know * when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 801436a: 687b ldr r3, [r7, #4] 801436c: f103 0208 add.w r2, r3, #8 8014370: 687b ldr r3, [r7, #4] 8014372: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8014374: 687b ldr r3, [r7, #4] 8014376: f103 0208 add.w r2, r3, #8 801437a: 687b ldr r3, [r7, #4] 801437c: 611a str r2, [r3, #16] pxList->xListEnd.pxContainer = NULL; listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); } #endif pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 801437e: 687b ldr r3, [r7, #4] 8014380: 2200 movs r2, #0 8014382: 601a str r2, [r3, #0] /* Write known values into the list if * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 8014384: bf00 nop 8014386: 370c adds r7, #12 8014388: 46bd mov sp, r7 801438a: f85d 7b04 ldr.w r7, [sp], #4 801438e: 4770 bx lr 08014390 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 8014390: b480 push {r7} 8014392: b083 sub sp, #12 8014394: af00 add r7, sp, #0 8014396: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 8014398: 687b ldr r3, [r7, #4] 801439a: 2200 movs r2, #0 801439c: 611a str r2, [r3, #16] /* Write known values into the list item if * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 801439e: bf00 nop 80143a0: 370c adds r7, #12 80143a2: 46bd mov sp, r7 80143a4: f85d 7b04 ldr.w r7, [sp], #4 80143a8: 4770 bx lr 080143aa : } /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 80143aa: b480 push {r7} 80143ac: b085 sub sp, #20 80143ae: af00 add r7, sp, #0 80143b0: 6078 str r0, [r7, #4] 80143b2: 6039 str r1, [r7, #0] ListItem_t * pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 80143b4: 683b ldr r3, [r7, #0] 80143b6: 681b ldr r3, [r3, #0] 80143b8: 60bb str r3, [r7, #8] * new list item should be placed after it. This ensures that TCBs which are * stored in ready lists (all of which have the same xItemValue value) get a * share of the CPU. However, if the xItemValue is the same as the back marker * the iteration loop below will not end. Therefore the value is checked * first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 80143ba: 68bb ldr r3, [r7, #8] 80143bc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80143c0: d103 bne.n 80143ca { pxIterator = pxList->xListEnd.pxPrevious; 80143c2: 687b ldr r3, [r7, #4] 80143c4: 691b ldr r3, [r3, #16] 80143c6: 60fb str r3, [r7, #12] 80143c8: e00c b.n 80143e4 * 5) If the FreeRTOS port supports interrupt nesting then ensure that * the priority of the tick interrupt is at or below * configMAX_SYSCALL_INTERRUPT_PRIORITY. **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 80143ca: 687b ldr r3, [r7, #4] 80143cc: 3308 adds r3, #8 80143ce: 60fb str r3, [r7, #12] 80143d0: e002 b.n 80143d8 80143d2: 68fb ldr r3, [r7, #12] 80143d4: 685b ldr r3, [r3, #4] 80143d6: 60fb str r3, [r7, #12] 80143d8: 68fb ldr r3, [r7, #12] 80143da: 685b ldr r3, [r3, #4] 80143dc: 681b ldr r3, [r3, #0] 80143de: 68ba ldr r2, [r7, #8] 80143e0: 429a cmp r2, r3 80143e2: d2f6 bcs.n 80143d2 /* There is nothing to do here, just iterating to the wanted * insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 80143e4: 68fb ldr r3, [r7, #12] 80143e6: 685a ldr r2, [r3, #4] 80143e8: 683b ldr r3, [r7, #0] 80143ea: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 80143ec: 683b ldr r3, [r7, #0] 80143ee: 685b ldr r3, [r3, #4] 80143f0: 683a ldr r2, [r7, #0] 80143f2: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 80143f4: 683b ldr r3, [r7, #0] 80143f6: 68fa ldr r2, [r7, #12] 80143f8: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 80143fa: 68fb ldr r3, [r7, #12] 80143fc: 683a ldr r2, [r7, #0] 80143fe: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the * item later. */ pxNewListItem->pxContainer = pxList; 8014400: 683b ldr r3, [r7, #0] 8014402: 687a ldr r2, [r7, #4] 8014404: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8014406: 687b ldr r3, [r7, #4] 8014408: 681b ldr r3, [r3, #0] 801440a: 1c5a adds r2, r3, #1 801440c: 687b ldr r3, [r7, #4] 801440e: 601a str r2, [r3, #0] } 8014410: bf00 nop 8014412: 3714 adds r7, #20 8014414: 46bd mov sp, r7 8014416: f85d 7b04 ldr.w r7, [sp], #4 801441a: 4770 bx lr 0801441c : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 801441c: b480 push {r7} 801441e: b085 sub sp, #20 8014420: af00 add r7, sp, #0 8014422: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list * item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8014424: 687b ldr r3, [r7, #4] 8014426: 691b ldr r3, [r3, #16] 8014428: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 801442a: 687b ldr r3, [r7, #4] 801442c: 685b ldr r3, [r3, #4] 801442e: 687a ldr r2, [r7, #4] 8014430: 6892 ldr r2, [r2, #8] 8014432: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8014434: 687b ldr r3, [r7, #4] 8014436: 689b ldr r3, [r3, #8] 8014438: 687a ldr r2, [r7, #4] 801443a: 6852 ldr r2, [r2, #4] 801443c: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 801443e: 68fb ldr r3, [r7, #12] 8014440: 685b ldr r3, [r3, #4] 8014442: 687a ldr r2, [r7, #4] 8014444: 429a cmp r2, r3 8014446: d103 bne.n 8014450 { pxList->pxIndex = pxItemToRemove->pxPrevious; 8014448: 687b ldr r3, [r7, #4] 801444a: 689a ldr r2, [r3, #8] 801444c: 68fb ldr r3, [r7, #12] 801444e: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8014450: 687b ldr r3, [r7, #4] 8014452: 2200 movs r2, #0 8014454: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8014456: 68fb ldr r3, [r7, #12] 8014458: 681b ldr r3, [r3, #0] 801445a: 1e5a subs r2, r3, #1 801445c: 68fb ldr r3, [r7, #12] 801445e: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8014460: 68fb ldr r3, [r7, #12] 8014462: 681b ldr r3, [r3, #0] } 8014464: 4618 mov r0, r3 8014466: 3714 adds r7, #20 8014468: 46bd mov sp, r7 801446a: f85d 7b04 ldr.w r7, [sp], #4 801446e: 4770 bx lr 08014470 : } while( 0 ) /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 8014470: b580 push {r7, lr} 8014472: b086 sub sp, #24 8014474: af00 add r7, sp, #0 8014476: 6078 str r0, [r7, #4] 8014478: 6039 str r1, [r7, #0] BaseType_t xReturn = pdPASS; 801447a: 2301 movs r3, #1 801447c: 617b str r3, [r7, #20] Queue_t * const pxQueue = xQueue; 801447e: 687b ldr r3, [r7, #4] 8014480: 613b str r3, [r7, #16] configASSERT( pxQueue ); 8014482: 693b ldr r3, [r7, #16] 8014484: 2b00 cmp r3, #0 8014486: d10b bne.n 80144a0 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8014488: f04f 0350 mov.w r3, #80 @ 0x50 801448c: f383 8811 msr BASEPRI, r3 8014490: f3bf 8f6f isb sy 8014494: f3bf 8f4f dsb sy 8014498: 60fb str r3, [r7, #12] " msr basepri, %0 \n"\ " isb \n"\ " dsb \n"\ : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 801449a: bf00 nop 801449c: bf00 nop 801449e: e7fd b.n 801449c if( ( pxQueue != NULL ) && 80144a0: 693b ldr r3, [r7, #16] 80144a2: 2b00 cmp r3, #0 80144a4: d05d beq.n 8014562 ( pxQueue->uxLength >= 1U ) && 80144a6: 693b ldr r3, [r7, #16] 80144a8: 6bdb ldr r3, [r3, #60] @ 0x3c if( ( pxQueue != NULL ) && 80144aa: 2b00 cmp r3, #0 80144ac: d059 beq.n 8014562 /* Check for multiplication overflow. */ ( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) ) 80144ae: 693b ldr r3, [r7, #16] 80144b0: 6c1a ldr r2, [r3, #64] @ 0x40 80144b2: 693b ldr r3, [r7, #16] 80144b4: 6bdb ldr r3, [r3, #60] @ 0x3c 80144b6: 2100 movs r1, #0 80144b8: fba3 2302 umull r2, r3, r3, r2 80144bc: 2b00 cmp r3, #0 80144be: d000 beq.n 80144c2 80144c0: 2101 movs r1, #1 80144c2: 460b mov r3, r1 ( pxQueue->uxLength >= 1U ) && 80144c4: 2b00 cmp r3, #0 80144c6: d14c bne.n 8014562 { taskENTER_CRITICAL(); 80144c8: f003 fc22 bl 8017d10 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 80144cc: 693b ldr r3, [r7, #16] 80144ce: 681a ldr r2, [r3, #0] 80144d0: 693b ldr r3, [r7, #16] 80144d2: 6bdb ldr r3, [r3, #60] @ 0x3c 80144d4: 6939 ldr r1, [r7, #16] 80144d6: 6c09 ldr r1, [r1, #64] @ 0x40 80144d8: fb01 f303 mul.w r3, r1, r3 80144dc: 441a add r2, r3 80144de: 693b ldr r3, [r7, #16] 80144e0: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 80144e2: 693b ldr r3, [r7, #16] 80144e4: 2200 movs r2, #0 80144e6: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 80144e8: 693b ldr r3, [r7, #16] 80144ea: 681a ldr r2, [r3, #0] 80144ec: 693b ldr r3, [r7, #16] 80144ee: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 80144f0: 693b ldr r3, [r7, #16] 80144f2: 681a ldr r2, [r3, #0] 80144f4: 693b ldr r3, [r7, #16] 80144f6: 6bdb ldr r3, [r3, #60] @ 0x3c 80144f8: 3b01 subs r3, #1 80144fa: 6939 ldr r1, [r7, #16] 80144fc: 6c09 ldr r1, [r1, #64] @ 0x40 80144fe: fb01 f303 mul.w r3, r1, r3 8014502: 441a add r2, r3 8014504: 693b ldr r3, [r7, #16] 8014506: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8014508: 693b ldr r3, [r7, #16] 801450a: 22ff movs r2, #255 @ 0xff 801450c: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8014510: 693b ldr r3, [r7, #16] 8014512: 22ff movs r2, #255 @ 0xff 8014514: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8014518: 683b ldr r3, [r7, #0] 801451a: 2b00 cmp r3, #0 801451c: d114 bne.n 8014548 /* If there are tasks blocked waiting to read from the queue, then * the tasks will remain blocked as after this function exits the queue * will still be empty. If there are tasks blocked waiting to write to * the queue, then one should be unblocked as after this function exits * it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 801451e: 693b ldr r3, [r7, #16] 8014520: 691b ldr r3, [r3, #16] 8014522: 2b00 cmp r3, #0 8014524: d01a beq.n 801455c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014526: 693b ldr r3, [r7, #16] 8014528: 3310 adds r3, #16 801452a: 4618 mov r0, r3 801452c: f001 fea2 bl 8016274 8014530: 4603 mov r3, r0 8014532: 2b00 cmp r3, #0 8014534: d012 beq.n 801455c { queueYIELD_IF_USING_PREEMPTION(); 8014536: 4b16 ldr r3, [pc, #88] @ (8014590 ) 8014538: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801453c: 601a str r2, [r3, #0] 801453e: f3bf 8f4f dsb sy 8014542: f3bf 8f6f isb sy 8014546: e009 b.n 801455c } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8014548: 693b ldr r3, [r7, #16] 801454a: 3310 adds r3, #16 801454c: 4618 mov r0, r3 801454e: f7ff feff bl 8014350 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8014552: 693b ldr r3, [r7, #16] 8014554: 3324 adds r3, #36 @ 0x24 8014556: 4618 mov r0, r3 8014558: f7ff fefa bl 8014350 } } taskEXIT_CRITICAL(); 801455c: f003 fc0a bl 8017d74 8014560: e001 b.n 8014566 } else { xReturn = pdFAIL; 8014562: 2300 movs r3, #0 8014564: 617b str r3, [r7, #20] } configASSERT( xReturn != pdFAIL ); 8014566: 697b ldr r3, [r7, #20] 8014568: 2b00 cmp r3, #0 801456a: d10b bne.n 8014584 __asm volatile 801456c: f04f 0350 mov.w r3, #80 @ 0x50 8014570: f383 8811 msr BASEPRI, r3 8014574: f3bf 8f6f isb sy 8014578: f3bf 8f4f dsb sy 801457c: 60bb str r3, [r7, #8] } 801457e: bf00 nop 8014580: bf00 nop 8014582: e7fd b.n 8014580 /* A value is returned for calling semantic consistency with previous * versions. */ return xReturn; 8014584: 697b ldr r3, [r7, #20] } 8014586: 4618 mov r0, r3 8014588: 3718 adds r7, #24 801458a: 46bd mov sp, r7 801458c: bd80 pop {r7, pc} 801458e: bf00 nop 8014590: e000ed04 .word 0xe000ed04 08014594 : QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t * pucQueueStorage, StaticQueue_t * pxStaticQueue, const uint8_t ucQueueType ) { 8014594: b580 push {r7, lr} 8014596: b08c sub sp, #48 @ 0x30 8014598: af02 add r7, sp, #8 801459a: 60f8 str r0, [r7, #12] 801459c: 60b9 str r1, [r7, #8] 801459e: 607a str r2, [r7, #4] 80145a0: 603b str r3, [r7, #0] Queue_t * pxNewQueue = NULL; 80145a2: 2300 movs r3, #0 80145a4: 627b str r3, [r7, #36] @ 0x24 /* The StaticQueue_t structure and the queue storage area must be * supplied. */ configASSERT( pxStaticQueue ); 80145a6: 683b ldr r3, [r7, #0] 80145a8: 2b00 cmp r3, #0 80145aa: d10b bne.n 80145c4 __asm volatile 80145ac: f04f 0350 mov.w r3, #80 @ 0x50 80145b0: f383 8811 msr BASEPRI, r3 80145b4: f3bf 8f6f isb sy 80145b8: f3bf 8f4f dsb sy 80145bc: 623b str r3, [r7, #32] } 80145be: bf00 nop 80145c0: bf00 nop 80145c2: e7fd b.n 80145c0 if( ( uxQueueLength > ( UBaseType_t ) 0 ) && 80145c4: 68fb ldr r3, [r7, #12] 80145c6: 2b00 cmp r3, #0 80145c8: d031 beq.n 801462e 80145ca: 683b ldr r3, [r7, #0] 80145cc: 2b00 cmp r3, #0 80145ce: d02e beq.n 801462e ( pxStaticQueue != NULL ) && 80145d0: 687b ldr r3, [r7, #4] 80145d2: 2b00 cmp r3, #0 80145d4: d002 beq.n 80145dc /* A queue storage area should be provided if the item size is not 0, and * should not be provided if the item size is 0. */ ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ) && 80145d6: 68bb ldr r3, [r7, #8] 80145d8: 2b00 cmp r3, #0 80145da: d028 beq.n 801462e 80145dc: 687b ldr r3, [r7, #4] 80145de: 2b00 cmp r3, #0 80145e0: d102 bne.n 80145e8 ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ) ) 80145e2: 68bb ldr r3, [r7, #8] 80145e4: 2b00 cmp r3, #0 80145e6: d122 bne.n 801462e #if ( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a * variable of type StaticQueue_t or StaticSemaphore_t equals the size of * the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 80145e8: 2350 movs r3, #80 @ 0x50 80145ea: 617b str r3, [r7, #20] /* This assertion cannot be branch covered in unit tests */ configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */ 80145ec: 697b ldr r3, [r7, #20] 80145ee: 2b50 cmp r3, #80 @ 0x50 80145f0: d00b beq.n 801460a __asm volatile 80145f2: f04f 0350 mov.w r3, #80 @ 0x50 80145f6: f383 8811 msr BASEPRI, r3 80145fa: f3bf 8f6f isb sy 80145fe: f3bf 8f4f dsb sy 8014602: 61fb str r3, [r7, #28] } 8014604: bf00 nop 8014606: bf00 nop 8014608: e7fd b.n 8014606 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 801460a: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. * The address of a statically allocated storage area was also passed in * but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 801460c: 683b ldr r3, [r7, #0] 801460e: 627b str r3, [r7, #36] @ 0x24 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so * note this queue was allocated statically in case the queue is * later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8014610: 6a7b ldr r3, [r7, #36] @ 0x24 8014612: 2201 movs r2, #1 8014614: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014618: f897 2030 ldrb.w r2, [r7, #48] @ 0x30 801461c: 6a7b ldr r3, [r7, #36] @ 0x24 801461e: 9300 str r3, [sp, #0] 8014620: 4613 mov r3, r2 8014622: 687a ldr r2, [r7, #4] 8014624: 68b9 ldr r1, [r7, #8] 8014626: 68f8 ldr r0, [r7, #12] 8014628: f000 f868 bl 80146fc 801462c: e00e b.n 801464c } else { configASSERT( pxNewQueue ); 801462e: 6a7b ldr r3, [r7, #36] @ 0x24 8014630: 2b00 cmp r3, #0 8014632: d10b bne.n 801464c __asm volatile 8014634: f04f 0350 mov.w r3, #80 @ 0x50 8014638: f383 8811 msr BASEPRI, r3 801463c: f3bf 8f6f isb sy 8014640: f3bf 8f4f dsb sy 8014644: 61bb str r3, [r7, #24] } 8014646: bf00 nop 8014648: bf00 nop 801464a: e7fd b.n 8014648 mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 801464c: 6a7b ldr r3, [r7, #36] @ 0x24 } 801464e: 4618 mov r0, r3 8014650: 3728 adds r7, #40 @ 0x28 8014652: 46bd mov sp, r7 8014654: bd80 pop {r7, pc} 08014656 : #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 8014656: b580 push {r7, lr} 8014658: b08a sub sp, #40 @ 0x28 801465a: af02 add r7, sp, #8 801465c: 60f8 str r0, [r7, #12] 801465e: 60b9 str r1, [r7, #8] 8014660: 4613 mov r3, r2 8014662: 71fb strb r3, [r7, #7] Queue_t * pxNewQueue = NULL; 8014664: 2300 movs r3, #0 8014666: 61fb str r3, [r7, #28] size_t xQueueSizeInBytes; uint8_t * pucQueueStorage; if( ( uxQueueLength > ( UBaseType_t ) 0 ) && 8014668: 68fb ldr r3, [r7, #12] 801466a: 2b00 cmp r3, #0 801466c: d032 beq.n 80146d4 /* Check for multiplication overflow. */ ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) && 801466e: 2100 movs r1, #0 8014670: 68ba ldr r2, [r7, #8] 8014672: 68fb ldr r3, [r7, #12] 8014674: fba3 2302 umull r2, r3, r3, r2 8014678: 2b00 cmp r3, #0 801467a: d000 beq.n 801467e 801467c: 2101 movs r1, #1 801467e: 460b mov r3, r1 if( ( uxQueueLength > ( UBaseType_t ) 0 ) && 8014680: 2b00 cmp r3, #0 8014682: d127 bne.n 80146d4 /* Check for addition overflow. */ ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) ) 8014684: 68fb ldr r3, [r7, #12] 8014686: 68ba ldr r2, [r7, #8] 8014688: fb02 f303 mul.w r3, r2, r3 ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) && 801468c: f113 0f51 cmn.w r3, #81 @ 0x51 8014690: d820 bhi.n 80146d4 { /* Allocate enough space to hold the maximum number of items that * can be in the queue at any time. It is valid for uxItemSize to be * zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014692: 68fb ldr r3, [r7, #12] 8014694: 68ba ldr r2, [r7, #8] 8014696: fb02 f303 mul.w r3, r2, r3 801469a: 61bb str r3, [r7, #24] * alignment requirements of the Queue_t structure - which in this case * is an int8_t *. Therefore, whenever the stack alignment requirements * are greater than or equal to the pointer to char requirements the cast * is safe. In other cases alignment requirements are not strict (one or * two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 801469c: 69bb ldr r3, [r7, #24] 801469e: 3350 adds r3, #80 @ 0x50 80146a0: 4618 mov r0, r3 80146a2: f003 fc5d bl 8017f60 80146a6: 61f8 str r0, [r7, #28] if( pxNewQueue != NULL ) 80146a8: 69fb ldr r3, [r7, #28] 80146aa: 2b00 cmp r3, #0 80146ac: d021 beq.n 80146f2 { /* Jump past the queue structure to find the location of the queue * storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 80146ae: 69fb ldr r3, [r7, #28] 80146b0: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 80146b2: 697b ldr r3, [r7, #20] 80146b4: 3350 adds r3, #80 @ 0x50 80146b6: 617b str r3, [r7, #20] #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so * note this task was created dynamically in case it is later * deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 80146b8: 69fb ldr r3, [r7, #28] 80146ba: 2200 movs r2, #0 80146bc: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 80146c0: 79fa ldrb r2, [r7, #7] 80146c2: 69fb ldr r3, [r7, #28] 80146c4: 9300 str r3, [sp, #0] 80146c6: 4613 mov r3, r2 80146c8: 697a ldr r2, [r7, #20] 80146ca: 68b9 ldr r1, [r7, #8] 80146cc: 68f8 ldr r0, [r7, #12] 80146ce: f000 f815 bl 80146fc if( pxNewQueue != NULL ) 80146d2: e00e b.n 80146f2 mtCOVERAGE_TEST_MARKER(); } } else { configASSERT( pxNewQueue ); 80146d4: 69fb ldr r3, [r7, #28] 80146d6: 2b00 cmp r3, #0 80146d8: d10b bne.n 80146f2 __asm volatile 80146da: f04f 0350 mov.w r3, #80 @ 0x50 80146de: f383 8811 msr BASEPRI, r3 80146e2: f3bf 8f6f isb sy 80146e6: f3bf 8f4f dsb sy 80146ea: 613b str r3, [r7, #16] } 80146ec: bf00 nop 80146ee: bf00 nop 80146f0: e7fd b.n 80146ee mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 80146f2: 69fb ldr r3, [r7, #28] } 80146f4: 4618 mov r0, r3 80146f6: 3720 adds r7, #32 80146f8: 46bd mov sp, r7 80146fa: bd80 pop {r7, pc} 080146fc : static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t * pucQueueStorage, const uint8_t ucQueueType, Queue_t * pxNewQueue ) { 80146fc: b580 push {r7, lr} 80146fe: b084 sub sp, #16 8014700: af00 add r7, sp, #0 8014702: 60f8 str r0, [r7, #12] 8014704: 60b9 str r1, [r7, #8] 8014706: 607a str r2, [r7, #4] 8014708: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should * configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 801470a: 68bb ldr r3, [r7, #8] 801470c: 2b00 cmp r3, #0 801470e: d103 bne.n 8014718 { /* No RAM was allocated for the queue storage area, but PC head cannot * be set to NULL because NULL is used as a key to say the queue is used as * a mutex. Therefore just set pcHead to point to the queue as a benign * value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8014710: 69bb ldr r3, [r7, #24] 8014712: 69ba ldr r2, [r7, #24] 8014714: 601a str r2, [r3, #0] 8014716: e002 b.n 801471e } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8014718: 69bb ldr r3, [r7, #24] 801471a: 687a ldr r2, [r7, #4] 801471c: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is * defined. */ pxNewQueue->uxLength = uxQueueLength; 801471e: 69bb ldr r3, [r7, #24] 8014720: 68fa ldr r2, [r7, #12] 8014722: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8014724: 69bb ldr r3, [r7, #24] 8014726: 68ba ldr r2, [r7, #8] 8014728: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 801472a: 2101 movs r1, #1 801472c: 69b8 ldr r0, [r7, #24] 801472e: f7ff fe9f bl 8014470 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8014732: 69bb ldr r3, [r7, #24] 8014734: 78fa ldrb r2, [r7, #3] 8014736: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 801473a: bf00 nop 801473c: 3710 adds r7, #16 801473e: 46bd mov sp, r7 8014740: bd80 pop {r7, pc} 08014742 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t * pxNewQueue ) { 8014742: b580 push {r7, lr} 8014744: b082 sub sp, #8 8014746: af00 add r7, sp, #0 8014748: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 801474a: 687b ldr r3, [r7, #4] 801474c: 2b00 cmp r3, #0 801474e: d00e beq.n 801476e { /* The queue create function will set all the queue structure members * correctly for a generic queue, but this function is creating a * mutex. Overwrite those members that need to be set differently - * in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8014750: 687b ldr r3, [r7, #4] 8014752: 2200 movs r2, #0 8014754: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8014756: 687b ldr r3, [r7, #4] 8014758: 2200 movs r2, #0 801475a: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 801475c: 687b ldr r3, [r7, #4] 801475e: 2200 movs r2, #0 8014760: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8014762: 2300 movs r3, #0 8014764: 2200 movs r2, #0 8014766: 2100 movs r1, #0 8014768: 6878 ldr r0, [r7, #4] 801476a: f000 f905 bl 8014978 } else { traceCREATE_MUTEX_FAILED(); } } 801476e: bf00 nop 8014770: 3708 adds r7, #8 8014772: 46bd mov sp, r7 8014774: bd80 pop {r7, pc} 08014776 : /*-----------------------------------------------------------*/ #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 8014776: b580 push {r7, lr} 8014778: b086 sub sp, #24 801477a: af00 add r7, sp, #0 801477c: 4603 mov r3, r0 801477e: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014780: 2301 movs r3, #1 8014782: 617b str r3, [r7, #20] 8014784: 2300 movs r3, #0 8014786: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 8014788: 79fb ldrb r3, [r7, #7] 801478a: 461a mov r2, r3 801478c: 6939 ldr r1, [r7, #16] 801478e: 6978 ldr r0, [r7, #20] 8014790: f7ff ff61 bl 8014656 8014794: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014796: 68f8 ldr r0, [r7, #12] 8014798: f7ff ffd3 bl 8014742 return xNewQueue; 801479c: 68fb ldr r3, [r7, #12] } 801479e: 4618 mov r0, r3 80147a0: 3718 adds r7, #24 80147a2: 46bd mov sp, r7 80147a4: bd80 pop {r7, pc} 080147a6 : #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t * pxStaticQueue ) { 80147a6: b580 push {r7, lr} 80147a8: b088 sub sp, #32 80147aa: af02 add r7, sp, #8 80147ac: 4603 mov r3, r0 80147ae: 6039 str r1, [r7, #0] 80147b0: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 80147b2: 2301 movs r3, #1 80147b4: 617b str r3, [r7, #20] 80147b6: 2300 movs r3, #0 80147b8: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if * configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 80147ba: 79fb ldrb r3, [r7, #7] 80147bc: 9300 str r3, [sp, #0] 80147be: 683b ldr r3, [r7, #0] 80147c0: 2200 movs r2, #0 80147c2: 6939 ldr r1, [r7, #16] 80147c4: 6978 ldr r0, [r7, #20] 80147c6: f7ff fee5 bl 8014594 80147ca: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 80147cc: 68f8 ldr r0, [r7, #12] 80147ce: f7ff ffb8 bl 8014742 return xNewQueue; 80147d2: 68fb ldr r3, [r7, #12] } 80147d4: 4618 mov r0, r3 80147d6: 3718 adds r7, #24 80147d8: 46bd mov sp, r7 80147da: bd80 pop {r7, pc} 080147dc : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 80147dc: b590 push {r4, r7, lr} 80147de: b087 sub sp, #28 80147e0: af00 add r7, sp, #0 80147e2: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 80147e4: 687b ldr r3, [r7, #4] 80147e6: 613b str r3, [r7, #16] configASSERT( pxMutex ); 80147e8: 693b ldr r3, [r7, #16] 80147ea: 2b00 cmp r3, #0 80147ec: d10b bne.n 8014806 __asm volatile 80147ee: f04f 0350 mov.w r3, #80 @ 0x50 80147f2: f383 8811 msr BASEPRI, r3 80147f6: f3bf 8f6f isb sy 80147fa: f3bf 8f4f dsb sy 80147fe: 60fb str r3, [r7, #12] } 8014800: bf00 nop 8014802: bf00 nop 8014804: e7fd b.n 8014802 * change outside of this task. If this task does not hold the mutex then * pxMutexHolder can never coincidentally equal the tasks handle, and as * this is the only condition we are interested in it does not matter if * pxMutexHolder is accessed simultaneously by another task. Therefore no * mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014806: 693b ldr r3, [r7, #16] 8014808: 689c ldr r4, [r3, #8] 801480a: f001 ff6f bl 80166ec 801480e: 4603 mov r3, r0 8014810: 429c cmp r4, r3 8014812: d111 bne.n 8014838 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to * the task handle, therefore no underflow check is required. Also, * uxRecursiveCallCount is only modified by the mutex holder, and as * there can only be one, no mutual exclusion is required to modify the * uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8014814: 693b ldr r3, [r7, #16] 8014816: 68db ldr r3, [r3, #12] 8014818: 1e5a subs r2, r3, #1 801481a: 693b ldr r3, [r7, #16] 801481c: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 801481e: 693b ldr r3, [r7, #16] 8014820: 68db ldr r3, [r3, #12] 8014822: 2b00 cmp r3, #0 8014824: d105 bne.n 8014832 { /* Return the mutex. This will automatically unblock any other * task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8014826: 2300 movs r3, #0 8014828: 2200 movs r2, #0 801482a: 2100 movs r1, #0 801482c: 6938 ldr r0, [r7, #16] 801482e: f000 f8a3 bl 8014978 else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8014832: 2301 movs r3, #1 8014834: 617b str r3, [r7, #20] 8014836: e001 b.n 801483c } else { /* The mutex cannot be given because the calling task is not the * holder. */ xReturn = pdFAIL; 8014838: 2300 movs r3, #0 801483a: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 801483c: 697b ldr r3, [r7, #20] } 801483e: 4618 mov r0, r3 8014840: 371c adds r7, #28 8014842: 46bd mov sp, r7 8014844: bd90 pop {r4, r7, pc} 08014846 : #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 8014846: b590 push {r4, r7, lr} 8014848: b087 sub sp, #28 801484a: af00 add r7, sp, #0 801484c: 6078 str r0, [r7, #4] 801484e: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014850: 687b ldr r3, [r7, #4] 8014852: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014854: 693b ldr r3, [r7, #16] 8014856: 2b00 cmp r3, #0 8014858: d10b bne.n 8014872 __asm volatile 801485a: f04f 0350 mov.w r3, #80 @ 0x50 801485e: f383 8811 msr BASEPRI, r3 8014862: f3bf 8f6f isb sy 8014866: f3bf 8f4f dsb sy 801486a: 60fb str r3, [r7, #12] } 801486c: bf00 nop 801486e: bf00 nop 8014870: e7fd b.n 801486e /* Comments regarding mutual exclusion as per those within * xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014872: 693b ldr r3, [r7, #16] 8014874: 689c ldr r4, [r3, #8] 8014876: f001 ff39 bl 80166ec 801487a: 4603 mov r3, r0 801487c: 429c cmp r4, r3 801487e: d107 bne.n 8014890 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014880: 693b ldr r3, [r7, #16] 8014882: 68db ldr r3, [r3, #12] 8014884: 1c5a adds r2, r3, #1 8014886: 693b ldr r3, [r7, #16] 8014888: 60da str r2, [r3, #12] xReturn = pdPASS; 801488a: 2301 movs r3, #1 801488c: 617b str r3, [r7, #20] 801488e: e00c b.n 80148aa } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 8014890: 6839 ldr r1, [r7, #0] 8014892: 6938 ldr r0, [r7, #16] 8014894: f000 fbb2 bl 8014ffc 8014898: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully * obtained. The calling task may have entered the Blocked state * before reaching here. */ if( xReturn != pdFAIL ) 801489a: 697b ldr r3, [r7, #20] 801489c: 2b00 cmp r3, #0 801489e: d004 beq.n 80148aa { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 80148a0: 693b ldr r3, [r7, #16] 80148a2: 68db ldr r3, [r3, #12] 80148a4: 1c5a adds r2, r3, #1 80148a6: 693b ldr r3, [r7, #16] 80148a8: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 80148aa: 697b ldr r3, [r7, #20] } 80148ac: 4618 mov r0, r3 80148ae: 371c adds r7, #28 80148b0: 46bd mov sp, r7 80148b2: bd90 pop {r4, r7, pc} 080148b4 : #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t * pxStaticQueue ) { 80148b4: b580 push {r7, lr} 80148b6: b088 sub sp, #32 80148b8: af02 add r7, sp, #8 80148ba: 60f8 str r0, [r7, #12] 80148bc: 60b9 str r1, [r7, #8] 80148be: 607a str r2, [r7, #4] QueueHandle_t xHandle = NULL; 80148c0: 2300 movs r3, #0 80148c2: 617b str r3, [r7, #20] if( ( uxMaxCount != 0 ) && 80148c4: 68fb ldr r3, [r7, #12] 80148c6: 2b00 cmp r3, #0 80148c8: d013 beq.n 80148f2 80148ca: 68ba ldr r2, [r7, #8] 80148cc: 68fb ldr r3, [r7, #12] 80148ce: 429a cmp r2, r3 80148d0: d80f bhi.n 80148f2 ( uxInitialCount <= uxMaxCount ) ) { xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); 80148d2: 2302 movs r3, #2 80148d4: 9300 str r3, [sp, #0] 80148d6: 687b ldr r3, [r7, #4] 80148d8: 2200 movs r2, #0 80148da: 2100 movs r1, #0 80148dc: 68f8 ldr r0, [r7, #12] 80148de: f7ff fe59 bl 8014594 80148e2: 6178 str r0, [r7, #20] if( xHandle != NULL ) 80148e4: 697b ldr r3, [r7, #20] 80148e6: 2b00 cmp r3, #0 80148e8: d012 beq.n 8014910 { ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; 80148ea: 697b ldr r3, [r7, #20] 80148ec: 68ba ldr r2, [r7, #8] 80148ee: 639a str r2, [r3, #56] @ 0x38 if( xHandle != NULL ) 80148f0: e00e b.n 8014910 traceCREATE_COUNTING_SEMAPHORE_FAILED(); } } else { configASSERT( xHandle ); 80148f2: 697b ldr r3, [r7, #20] 80148f4: 2b00 cmp r3, #0 80148f6: d10b bne.n 8014910 __asm volatile 80148f8: f04f 0350 mov.w r3, #80 @ 0x50 80148fc: f383 8811 msr BASEPRI, r3 8014900: f3bf 8f6f isb sy 8014904: f3bf 8f4f dsb sy 8014908: 613b str r3, [r7, #16] } 801490a: bf00 nop 801490c: bf00 nop 801490e: e7fd b.n 801490c mtCOVERAGE_TEST_MARKER(); } return xHandle; 8014910: 697b ldr r3, [r7, #20] } 8014912: 4618 mov r0, r3 8014914: 3718 adds r7, #24 8014916: 46bd mov sp, r7 8014918: bd80 pop {r7, pc} 0801491a : #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) { 801491a: b580 push {r7, lr} 801491c: b084 sub sp, #16 801491e: af00 add r7, sp, #0 8014920: 6078 str r0, [r7, #4] 8014922: 6039 str r1, [r7, #0] QueueHandle_t xHandle = NULL; 8014924: 2300 movs r3, #0 8014926: 60fb str r3, [r7, #12] if( ( uxMaxCount != 0 ) && 8014928: 687b ldr r3, [r7, #4] 801492a: 2b00 cmp r3, #0 801492c: d010 beq.n 8014950 801492e: 683a ldr r2, [r7, #0] 8014930: 687b ldr r3, [r7, #4] 8014932: 429a cmp r2, r3 8014934: d80c bhi.n 8014950 ( uxInitialCount <= uxMaxCount ) ) { xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); 8014936: 2202 movs r2, #2 8014938: 2100 movs r1, #0 801493a: 6878 ldr r0, [r7, #4] 801493c: f7ff fe8b bl 8014656 8014940: 60f8 str r0, [r7, #12] if( xHandle != NULL ) 8014942: 68fb ldr r3, [r7, #12] 8014944: 2b00 cmp r3, #0 8014946: d012 beq.n 801496e { ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; 8014948: 68fb ldr r3, [r7, #12] 801494a: 683a ldr r2, [r7, #0] 801494c: 639a str r2, [r3, #56] @ 0x38 if( xHandle != NULL ) 801494e: e00e b.n 801496e traceCREATE_COUNTING_SEMAPHORE_FAILED(); } } else { configASSERT( xHandle ); 8014950: 68fb ldr r3, [r7, #12] 8014952: 2b00 cmp r3, #0 8014954: d10b bne.n 801496e __asm volatile 8014956: f04f 0350 mov.w r3, #80 @ 0x50 801495a: f383 8811 msr BASEPRI, r3 801495e: f3bf 8f6f isb sy 8014962: f3bf 8f4f dsb sy 8014966: 60bb str r3, [r7, #8] } 8014968: bf00 nop 801496a: bf00 nop 801496c: e7fd b.n 801496a mtCOVERAGE_TEST_MARKER(); } return xHandle; 801496e: 68fb ldr r3, [r7, #12] } 8014970: 4618 mov r0, r3 8014972: 3710 adds r7, #16 8014974: 46bd mov sp, r7 8014976: bd80 pop {r7, pc} 08014978 : BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8014978: b580 push {r7, lr} 801497a: b08e sub sp, #56 @ 0x38 801497c: af00 add r7, sp, #0 801497e: 60f8 str r0, [r7, #12] 8014980: 60b9 str r1, [r7, #8] 8014982: 607a str r2, [r7, #4] 8014984: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8014986: 2300 movs r3, #0 8014988: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801498a: 68fb ldr r3, [r7, #12] 801498c: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 801498e: 6b3b ldr r3, [r7, #48] @ 0x30 8014990: 2b00 cmp r3, #0 8014992: d10b bne.n 80149ac __asm volatile 8014994: f04f 0350 mov.w r3, #80 @ 0x50 8014998: f383 8811 msr BASEPRI, r3 801499c: f3bf 8f6f isb sy 80149a0: f3bf 8f4f dsb sy 80149a4: 62bb str r3, [r7, #40] @ 0x28 } 80149a6: bf00 nop 80149a8: bf00 nop 80149aa: e7fd b.n 80149a8 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 80149ac: 68bb ldr r3, [r7, #8] 80149ae: 2b00 cmp r3, #0 80149b0: d103 bne.n 80149ba 80149b2: 6b3b ldr r3, [r7, #48] @ 0x30 80149b4: 6c1b ldr r3, [r3, #64] @ 0x40 80149b6: 2b00 cmp r3, #0 80149b8: d101 bne.n 80149be 80149ba: 2301 movs r3, #1 80149bc: e000 b.n 80149c0 80149be: 2300 movs r3, #0 80149c0: 2b00 cmp r3, #0 80149c2: d10b bne.n 80149dc __asm volatile 80149c4: f04f 0350 mov.w r3, #80 @ 0x50 80149c8: f383 8811 msr BASEPRI, r3 80149cc: f3bf 8f6f isb sy 80149d0: f3bf 8f4f dsb sy 80149d4: 627b str r3, [r7, #36] @ 0x24 } 80149d6: bf00 nop 80149d8: bf00 nop 80149da: e7fd b.n 80149d8 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 80149dc: 683b ldr r3, [r7, #0] 80149de: 2b02 cmp r3, #2 80149e0: d103 bne.n 80149ea 80149e2: 6b3b ldr r3, [r7, #48] @ 0x30 80149e4: 6bdb ldr r3, [r3, #60] @ 0x3c 80149e6: 2b01 cmp r3, #1 80149e8: d101 bne.n 80149ee 80149ea: 2301 movs r3, #1 80149ec: e000 b.n 80149f0 80149ee: 2300 movs r3, #0 80149f0: 2b00 cmp r3, #0 80149f2: d10b bne.n 8014a0c __asm volatile 80149f4: f04f 0350 mov.w r3, #80 @ 0x50 80149f8: f383 8811 msr BASEPRI, r3 80149fc: f3bf 8f6f isb sy 8014a00: f3bf 8f4f dsb sy 8014a04: 623b str r3, [r7, #32] } 8014a06: bf00 nop 8014a08: bf00 nop 8014a0a: e7fd b.n 8014a08 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014a0c: f001 fe7e bl 801670c 8014a10: 4603 mov r3, r0 8014a12: 2b00 cmp r3, #0 8014a14: d102 bne.n 8014a1c 8014a16: 687b ldr r3, [r7, #4] 8014a18: 2b00 cmp r3, #0 8014a1a: d101 bne.n 8014a20 8014a1c: 2301 movs r3, #1 8014a1e: e000 b.n 8014a22 8014a20: 2300 movs r3, #0 8014a22: 2b00 cmp r3, #0 8014a24: d10b bne.n 8014a3e __asm volatile 8014a26: f04f 0350 mov.w r3, #80 @ 0x50 8014a2a: f383 8811 msr BASEPRI, r3 8014a2e: f3bf 8f6f isb sy 8014a32: f3bf 8f4f dsb sy 8014a36: 61fb str r3, [r7, #28] } 8014a38: bf00 nop 8014a3a: bf00 nop 8014a3c: e7fd b.n 8014a3a /*lint -save -e904 This function relaxes the coding standard somewhat to * allow return statements within the function itself. This is done in the * interest of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); 8014a3e: f003 f967 bl 8017d10 { /* Is there room on the queue now? The running task must be the * highest priority task wanting to access the queue. If the head item * in the queue is to be overwritten then it does not matter if the * queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014a42: 6b3b ldr r3, [r7, #48] @ 0x30 8014a44: 6b9a ldr r2, [r3, #56] @ 0x38 8014a46: 6b3b ldr r3, [r7, #48] @ 0x30 8014a48: 6bdb ldr r3, [r3, #60] @ 0x3c 8014a4a: 429a cmp r2, r3 8014a4c: d302 bcc.n 8014a54 8014a4e: 683b ldr r3, [r7, #0] 8014a50: 2b02 cmp r3, #2 8014a52: d129 bne.n 8014aa8 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8014a54: 683a ldr r2, [r7, #0] 8014a56: 68b9 ldr r1, [r7, #8] 8014a58: 6b38 ldr r0, [r7, #48] @ 0x30 8014a5a: f000 fca5 bl 80153a8 8014a5e: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the * queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014a60: 6b3b ldr r3, [r7, #48] @ 0x30 8014a62: 6a5b ldr r3, [r3, #36] @ 0x24 8014a64: 2b00 cmp r3, #0 8014a66: d010 beq.n 8014a8a { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014a68: 6b3b ldr r3, [r7, #48] @ 0x30 8014a6a: 3324 adds r3, #36 @ 0x24 8014a6c: 4618 mov r0, r3 8014a6e: f001 fc01 bl 8016274 8014a72: 4603 mov r3, r0 8014a74: 2b00 cmp r3, #0 8014a76: d013 beq.n 8014aa0 { /* The unblocked task has a priority higher than * our own so yield immediately. Yes it is ok to do * this from within the critical section - the kernel * takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8014a78: 4b3f ldr r3, [pc, #252] @ (8014b78 ) 8014a7a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014a7e: 601a str r2, [r3, #0] 8014a80: f3bf 8f4f dsb sy 8014a84: f3bf 8f6f isb sy 8014a88: e00a b.n 8014aa0 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8014a8a: 6afb ldr r3, [r7, #44] @ 0x2c 8014a8c: 2b00 cmp r3, #0 8014a8e: d007 beq.n 8014aa0 { /* This path is a special case that will only get * executed if the task was holding multiple mutexes and * the mutexes were given back in an order that is * different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8014a90: 4b39 ldr r3, [pc, #228] @ (8014b78 ) 8014a92: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014a96: 601a str r2, [r3, #0] 8014a98: f3bf 8f4f dsb sy 8014a9c: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8014aa0: f003 f968 bl 8017d74 return pdPASS; 8014aa4: 2301 movs r3, #1 8014aa6: e063 b.n 8014b70 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014aa8: 687b ldr r3, [r7, #4] 8014aaa: 2b00 cmp r3, #0 8014aac: d103 bne.n 8014ab6 { /* The queue was full and no block time is specified (or * the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014aae: f003 f961 bl 8017d74 /* Return to the original privilege level before exiting * the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014ab2: 2300 movs r3, #0 8014ab4: e05c b.n 8014b70 } else if( xEntryTimeSet == pdFALSE ) 8014ab6: 6b7b ldr r3, [r7, #52] @ 0x34 8014ab8: 2b00 cmp r3, #0 8014aba: d106 bne.n 8014aca { /* The queue was full and a block time was specified so * configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014abc: f107 0314 add.w r3, r7, #20 8014ac0: 4618 mov r0, r3 8014ac2: f001 fcaf bl 8016424 xEntryTimeSet = pdTRUE; 8014ac6: 2301 movs r3, #1 8014ac8: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014aca: f003 f953 bl 8017d74 /* Interrupts and other tasks can send to and receive from the queue * now the critical section has been exited. */ vTaskSuspendAll(); 8014ace: f001 f89b bl 8015c08 prvLockQueue( pxQueue ); 8014ad2: f003 f91d bl 8017d10 8014ad6: 6b3b ldr r3, [r7, #48] @ 0x30 8014ad8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014adc: b25b sxtb r3, r3 8014ade: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014ae2: d103 bne.n 8014aec 8014ae4: 6b3b ldr r3, [r7, #48] @ 0x30 8014ae6: 2200 movs r2, #0 8014ae8: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014aec: 6b3b ldr r3, [r7, #48] @ 0x30 8014aee: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014af2: b25b sxtb r3, r3 8014af4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014af8: d103 bne.n 8014b02 8014afa: 6b3b ldr r3, [r7, #48] @ 0x30 8014afc: 2200 movs r2, #0 8014afe: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014b02: f003 f937 bl 8017d74 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014b06: 1d3a adds r2, r7, #4 8014b08: f107 0314 add.w r3, r7, #20 8014b0c: 4611 mov r1, r2 8014b0e: 4618 mov r0, r3 8014b10: f001 fc9e bl 8016450 8014b14: 4603 mov r3, r0 8014b16: 2b00 cmp r3, #0 8014b18: d124 bne.n 8014b64 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 8014b1a: 6b38 ldr r0, [r7, #48] @ 0x30 8014b1c: f000 fd3c bl 8015598 8014b20: 4603 mov r3, r0 8014b22: 2b00 cmp r3, #0 8014b24: d018 beq.n 8014b58 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 8014b26: 6b3b ldr r3, [r7, #48] @ 0x30 8014b28: 3310 adds r3, #16 8014b2a: 687a ldr r2, [r7, #4] 8014b2c: 4611 mov r1, r2 8014b2e: 4618 mov r0, r3 8014b30: f001 fb34 bl 801619c /* Unlocking the queue means queue events can effect the * event list. It is possible that interrupts occurring now * remove this task from the event list again - but as the * scheduler is suspended the task will go onto the pending * ready list instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8014b34: 6b38 ldr r0, [r7, #48] @ 0x30 8014b36: f000 fcc7 bl 80154c8 /* Resuming the scheduler will move tasks from the pending * ready list into the ready list - so it is feasible that this * task is already in the ready list before it yields - in which * case the yield will not cause a context switch unless there * is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 8014b3a: f001 f873 bl 8015c24 8014b3e: 4603 mov r3, r0 8014b40: 2b00 cmp r3, #0 8014b42: f47f af7c bne.w 8014a3e { portYIELD_WITHIN_API(); 8014b46: 4b0c ldr r3, [pc, #48] @ (8014b78 ) 8014b48: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014b4c: 601a str r2, [r3, #0] 8014b4e: f3bf 8f4f dsb sy 8014b52: f3bf 8f6f isb sy 8014b56: e772 b.n 8014a3e } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 8014b58: 6b38 ldr r0, [r7, #48] @ 0x30 8014b5a: f000 fcb5 bl 80154c8 ( void ) xTaskResumeAll(); 8014b5e: f001 f861 bl 8015c24 8014b62: e76c b.n 8014a3e } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8014b64: 6b38 ldr r0, [r7, #48] @ 0x30 8014b66: f000 fcaf bl 80154c8 ( void ) xTaskResumeAll(); 8014b6a: f001 f85b bl 8015c24 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014b6e: 2300 movs r3, #0 } } /*lint -restore */ } 8014b70: 4618 mov r0, r3 8014b72: 3738 adds r7, #56 @ 0x38 8014b74: 46bd mov sp, r7 8014b76: bd80 pop {r7, pc} 8014b78: e000ed04 .word 0xe000ed04 08014b7c : BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8014b7c: b580 push {r7, lr} 8014b7e: b092 sub sp, #72 @ 0x48 8014b80: af00 add r7, sp, #0 8014b82: 60f8 str r0, [r7, #12] 8014b84: 60b9 str r1, [r7, #8] 8014b86: 607a str r2, [r7, #4] 8014b88: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014b8a: 68fb ldr r3, [r7, #12] 8014b8c: 643b str r3, [r7, #64] @ 0x40 configASSERT( pxQueue ); 8014b8e: 6c3b ldr r3, [r7, #64] @ 0x40 8014b90: 2b00 cmp r3, #0 8014b92: d10b bne.n 8014bac __asm volatile 8014b94: f04f 0350 mov.w r3, #80 @ 0x50 8014b98: f383 8811 msr BASEPRI, r3 8014b9c: f3bf 8f6f isb sy 8014ba0: f3bf 8f4f dsb sy 8014ba4: 62fb str r3, [r7, #44] @ 0x2c } 8014ba6: bf00 nop 8014ba8: bf00 nop 8014baa: e7fd b.n 8014ba8 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014bac: 68bb ldr r3, [r7, #8] 8014bae: 2b00 cmp r3, #0 8014bb0: d103 bne.n 8014bba 8014bb2: 6c3b ldr r3, [r7, #64] @ 0x40 8014bb4: 6c1b ldr r3, [r3, #64] @ 0x40 8014bb6: 2b00 cmp r3, #0 8014bb8: d101 bne.n 8014bbe 8014bba: 2301 movs r3, #1 8014bbc: e000 b.n 8014bc0 8014bbe: 2300 movs r3, #0 8014bc0: 2b00 cmp r3, #0 8014bc2: d10b bne.n 8014bdc __asm volatile 8014bc4: f04f 0350 mov.w r3, #80 @ 0x50 8014bc8: f383 8811 msr BASEPRI, r3 8014bcc: f3bf 8f6f isb sy 8014bd0: f3bf 8f4f dsb sy 8014bd4: 62bb str r3, [r7, #40] @ 0x28 } 8014bd6: bf00 nop 8014bd8: bf00 nop 8014bda: e7fd b.n 8014bd8 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014bdc: 683b ldr r3, [r7, #0] 8014bde: 2b02 cmp r3, #2 8014be0: d103 bne.n 8014bea 8014be2: 6c3b ldr r3, [r7, #64] @ 0x40 8014be4: 6bdb ldr r3, [r3, #60] @ 0x3c 8014be6: 2b01 cmp r3, #1 8014be8: d101 bne.n 8014bee 8014bea: 2301 movs r3, #1 8014bec: e000 b.n 8014bf0 8014bee: 2300 movs r3, #0 8014bf0: 2b00 cmp r3, #0 8014bf2: d10b bne.n 8014c0c __asm volatile 8014bf4: f04f 0350 mov.w r3, #80 @ 0x50 8014bf8: f383 8811 msr BASEPRI, r3 8014bfc: f3bf 8f6f isb sy 8014c00: f3bf 8f4f dsb sy 8014c04: 627b str r3, [r7, #36] @ 0x24 } 8014c06: bf00 nop 8014c08: bf00 nop 8014c0a: e7fd b.n 8014c08 * that have been assigned a priority at or (logically) below the maximum * system call interrupt priority. FreeRTOS maintains a separate interrupt * safe API to ensure interrupt entry is as fast and as simple as possible. * More information (albeit Cortex-M specific) is provided on the following * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8014c0c: f003 f966 bl 8017edc portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 8014c10: f3ef 8211 mrs r2, BASEPRI 8014c14: f04f 0350 mov.w r3, #80 @ 0x50 8014c18: f383 8811 msr BASEPRI, r3 8014c1c: f3bf 8f6f isb sy 8014c20: f3bf 8f4f dsb sy 8014c24: 623a str r2, [r7, #32] 8014c26: 61fb str r3, [r7, #28] : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler * warnings. */ return ulOriginalBASEPRI; 8014c28: 6a3b ldr r3, [r7, #32] /* Similar to xQueueGenericSend, except without blocking if there is no room * in the queue. Also don't directly wake a task that was blocked on a queue * read, instead return a flag to say whether a context switch is required or * not (i.e. has a task with a higher priority than us been woken by this * post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8014c2a: 63fb str r3, [r7, #60] @ 0x3c { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014c2c: 6c3b ldr r3, [r7, #64] @ 0x40 8014c2e: 6b9a ldr r2, [r3, #56] @ 0x38 8014c30: 6c3b ldr r3, [r7, #64] @ 0x40 8014c32: 6bdb ldr r3, [r3, #60] @ 0x3c 8014c34: 429a cmp r2, r3 8014c36: d302 bcc.n 8014c3e 8014c38: 683b ldr r3, [r7, #0] 8014c3a: 2b02 cmp r3, #2 8014c3c: d147 bne.n 8014cce { const int8_t cTxLock = pxQueue->cTxLock; 8014c3e: 6c3b ldr r3, [r7, #64] @ 0x40 8014c40: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014c44: f887 303b strb.w r3, [r7, #59] @ 0x3b const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 8014c48: 6c3b ldr r3, [r7, #64] @ 0x40 8014c4a: 6b9b ldr r3, [r3, #56] @ 0x38 8014c4c: 637b str r3, [r7, #52] @ 0x34 /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a * semaphore or mutex. That means prvCopyDataToQueue() cannot result * in a task disinheriting a priority and prvCopyDataToQueue() can be * called here even though the disinherit function does not check if * the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8014c4e: 683a ldr r2, [r7, #0] 8014c50: 68b9 ldr r1, [r7, #8] 8014c52: 6c38 ldr r0, [r7, #64] @ 0x40 8014c54: f000 fba8 bl 80153a8 /* The event list is not altered if the queue is locked. This will * be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 8014c58: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b 8014c5c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014c60: d112 bne.n 8014c88 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014c62: 6c3b ldr r3, [r7, #64] @ 0x40 8014c64: 6a5b ldr r3, [r3, #36] @ 0x24 8014c66: 2b00 cmp r3, #0 8014c68: d02e beq.n 8014cc8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014c6a: 6c3b ldr r3, [r7, #64] @ 0x40 8014c6c: 3324 adds r3, #36 @ 0x24 8014c6e: 4618 mov r0, r3 8014c70: f001 fb00 bl 8016274 8014c74: 4603 mov r3, r0 8014c76: 2b00 cmp r3, #0 8014c78: d026 beq.n 8014cc8 { /* The task waiting has a higher priority so record that a * context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8014c7a: 687b ldr r3, [r7, #4] 8014c7c: 2b00 cmp r3, #0 8014c7e: d023 beq.n 8014cc8 { *pxHigherPriorityTaskWoken = pdTRUE; 8014c80: 687b ldr r3, [r7, #4] 8014c82: 2201 movs r2, #1 8014c84: 601a str r2, [r3, #0] 8014c86: e01f b.n 8014cc8 } else { /* Increment the lock count so the task that unlocks the queue * knows that data was posted while it was locked. */ prvIncrementQueueTxLock( pxQueue, cTxLock ); 8014c88: f001 f8da bl 8015e40 8014c8c: 6338 str r0, [r7, #48] @ 0x30 8014c8e: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b 8014c92: 6b3a ldr r2, [r7, #48] @ 0x30 8014c94: 429a cmp r2, r3 8014c96: d917 bls.n 8014cc8 8014c98: f997 303b ldrsb.w r3, [r7, #59] @ 0x3b 8014c9c: 2b7f cmp r3, #127 @ 0x7f 8014c9e: d10b bne.n 8014cb8 __asm volatile 8014ca0: f04f 0350 mov.w r3, #80 @ 0x50 8014ca4: f383 8811 msr BASEPRI, r3 8014ca8: f3bf 8f6f isb sy 8014cac: f3bf 8f4f dsb sy 8014cb0: 61bb str r3, [r7, #24] } 8014cb2: bf00 nop 8014cb4: bf00 nop 8014cb6: e7fd b.n 8014cb4 8014cb8: f897 303b ldrb.w r3, [r7, #59] @ 0x3b 8014cbc: 3301 adds r3, #1 8014cbe: b2db uxtb r3, r3 8014cc0: b25a sxtb r2, r3 8014cc2: 6c3b ldr r3, [r7, #64] @ 0x40 8014cc4: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8014cc8: 2301 movs r3, #1 8014cca: 647b str r3, [r7, #68] @ 0x44 { 8014ccc: e001 b.n 8014cd2 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 8014cce: 2300 movs r3, #0 8014cd0: 647b str r3, [r7, #68] @ 0x44 8014cd2: 6bfb ldr r3, [r7, #60] @ 0x3c 8014cd4: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8014cd6: 697b ldr r3, [r7, #20] 8014cd8: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory" ); } 8014cdc: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8014cde: 6c7b ldr r3, [r7, #68] @ 0x44 } 8014ce0: 4618 mov r0, r3 8014ce2: 3748 adds r7, #72 @ 0x48 8014ce4: 46bd mov sp, r7 8014ce6: bd80 pop {r7, pc} 08014ce8 : /*-----------------------------------------------------------*/ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) { 8014ce8: b580 push {r7, lr} 8014cea: b090 sub sp, #64 @ 0x40 8014cec: af00 add r7, sp, #0 8014cee: 6078 str r0, [r7, #4] 8014cf0: 6039 str r1, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014cf2: 687b ldr r3, [r7, #4] 8014cf4: 63bb str r3, [r7, #56] @ 0x38 * item size is 0. Don't directly wake a task that was blocked on a queue * read, instead return a flag to say whether a context switch is required or * not (i.e. has a task with a higher priority than us been woken by this * post). */ configASSERT( pxQueue ); 8014cf6: 6bbb ldr r3, [r7, #56] @ 0x38 8014cf8: 2b00 cmp r3, #0 8014cfa: d10b bne.n 8014d14 __asm volatile 8014cfc: f04f 0350 mov.w r3, #80 @ 0x50 8014d00: f383 8811 msr BASEPRI, r3 8014d04: f3bf 8f6f isb sy 8014d08: f3bf 8f4f dsb sy 8014d0c: 627b str r3, [r7, #36] @ 0x24 } 8014d0e: bf00 nop 8014d10: bf00 nop 8014d12: e7fd b.n 8014d10 /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() * if the item size is not 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 8014d14: 6bbb ldr r3, [r7, #56] @ 0x38 8014d16: 6c1b ldr r3, [r3, #64] @ 0x40 8014d18: 2b00 cmp r3, #0 8014d1a: d00b beq.n 8014d34 __asm volatile 8014d1c: f04f 0350 mov.w r3, #80 @ 0x50 8014d20: f383 8811 msr BASEPRI, r3 8014d24: f3bf 8f6f isb sy 8014d28: f3bf 8f4f dsb sy 8014d2c: 623b str r3, [r7, #32] } 8014d2e: bf00 nop 8014d30: bf00 nop 8014d32: e7fd b.n 8014d30 /* Normally a mutex would not be given from an interrupt, especially if * there is a mutex holder, as priority inheritance makes no sense for an * interrupts, only tasks. */ configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); 8014d34: 6bbb ldr r3, [r7, #56] @ 0x38 8014d36: 681b ldr r3, [r3, #0] 8014d38: 2b00 cmp r3, #0 8014d3a: d103 bne.n 8014d44 8014d3c: 6bbb ldr r3, [r7, #56] @ 0x38 8014d3e: 689b ldr r3, [r3, #8] 8014d40: 2b00 cmp r3, #0 8014d42: d101 bne.n 8014d48 8014d44: 2301 movs r3, #1 8014d46: e000 b.n 8014d4a 8014d48: 2300 movs r3, #0 8014d4a: 2b00 cmp r3, #0 8014d4c: d10b bne.n 8014d66 __asm volatile 8014d4e: f04f 0350 mov.w r3, #80 @ 0x50 8014d52: f383 8811 msr BASEPRI, r3 8014d56: f3bf 8f6f isb sy 8014d5a: f3bf 8f4f dsb sy 8014d5e: 61fb str r3, [r7, #28] } 8014d60: bf00 nop 8014d62: bf00 nop 8014d64: e7fd b.n 8014d62 * that have been assigned a priority at or (logically) below the maximum * system call interrupt priority. FreeRTOS maintains a separate interrupt * safe API to ensure interrupt entry is as fast and as simple as possible. * More information (albeit Cortex-M specific) is provided on the following * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8014d66: f003 f8b9 bl 8017edc __asm volatile 8014d6a: f3ef 8211 mrs r2, BASEPRI 8014d6e: f04f 0350 mov.w r3, #80 @ 0x50 8014d72: f383 8811 msr BASEPRI, r3 8014d76: f3bf 8f6f isb sy 8014d7a: f3bf 8f4f dsb sy 8014d7e: 61ba str r2, [r7, #24] 8014d80: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 8014d82: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8014d84: 637b str r3, [r7, #52] @ 0x34 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014d86: 6bbb ldr r3, [r7, #56] @ 0x38 8014d88: 6b9b ldr r3, [r3, #56] @ 0x38 8014d8a: 633b str r3, [r7, #48] @ 0x30 /* When the queue is used to implement a semaphore no data is ever * moved through the queue but it is still valid to see if the queue 'has * space'. */ if( uxMessagesWaiting < pxQueue->uxLength ) 8014d8c: 6bbb ldr r3, [r7, #56] @ 0x38 8014d8e: 6bdb ldr r3, [r3, #60] @ 0x3c 8014d90: 6b3a ldr r2, [r7, #48] @ 0x30 8014d92: 429a cmp r2, r3 8014d94: d243 bcs.n 8014e1e { const int8_t cTxLock = pxQueue->cTxLock; 8014d96: 6bbb ldr r3, [r7, #56] @ 0x38 8014d98: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014d9c: f887 302f strb.w r3, [r7, #47] @ 0x2f * holder - and if there is a mutex holder then the mutex cannot be * given from an ISR. As this is the ISR version of the function it * can be assumed there is no mutex holder and no need to determine if * priority disinheritance is needed. Simply increase the count of * messages (semaphores) available. */ pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8014da0: 6b3b ldr r3, [r7, #48] @ 0x30 8014da2: 1c5a adds r2, r3, #1 8014da4: 6bbb ldr r3, [r7, #56] @ 0x38 8014da6: 639a str r2, [r3, #56] @ 0x38 /* The event list is not altered if the queue is locked. This will * be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 8014da8: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 8014dac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014db0: d112 bne.n 8014dd8 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014db2: 6bbb ldr r3, [r7, #56] @ 0x38 8014db4: 6a5b ldr r3, [r3, #36] @ 0x24 8014db6: 2b00 cmp r3, #0 8014db8: d02e beq.n 8014e18 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014dba: 6bbb ldr r3, [r7, #56] @ 0x38 8014dbc: 3324 adds r3, #36 @ 0x24 8014dbe: 4618 mov r0, r3 8014dc0: f001 fa58 bl 8016274 8014dc4: 4603 mov r3, r0 8014dc6: 2b00 cmp r3, #0 8014dc8: d026 beq.n 8014e18 { /* The task waiting has a higher priority so record that a * context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8014dca: 683b ldr r3, [r7, #0] 8014dcc: 2b00 cmp r3, #0 8014dce: d023 beq.n 8014e18 { *pxHigherPriorityTaskWoken = pdTRUE; 8014dd0: 683b ldr r3, [r7, #0] 8014dd2: 2201 movs r2, #1 8014dd4: 601a str r2, [r3, #0] 8014dd6: e01f b.n 8014e18 } else { /* Increment the lock count so the task that unlocks the queue * knows that data was posted while it was locked. */ prvIncrementQueueTxLock( pxQueue, cTxLock ); 8014dd8: f001 f832 bl 8015e40 8014ddc: 62b8 str r0, [r7, #40] @ 0x28 8014dde: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 8014de2: 6aba ldr r2, [r7, #40] @ 0x28 8014de4: 429a cmp r2, r3 8014de6: d917 bls.n 8014e18 8014de8: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 8014dec: 2b7f cmp r3, #127 @ 0x7f 8014dee: d10b bne.n 8014e08 __asm volatile 8014df0: f04f 0350 mov.w r3, #80 @ 0x50 8014df4: f383 8811 msr BASEPRI, r3 8014df8: f3bf 8f6f isb sy 8014dfc: f3bf 8f4f dsb sy 8014e00: 613b str r3, [r7, #16] } 8014e02: bf00 nop 8014e04: bf00 nop 8014e06: e7fd b.n 8014e04 8014e08: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8014e0c: 3301 adds r3, #1 8014e0e: b2db uxtb r3, r3 8014e10: b25a sxtb r2, r3 8014e12: 6bbb ldr r3, [r7, #56] @ 0x38 8014e14: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8014e18: 2301 movs r3, #1 8014e1a: 63fb str r3, [r7, #60] @ 0x3c 8014e1c: e001 b.n 8014e22 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 8014e1e: 2300 movs r3, #0 8014e20: 63fb str r3, [r7, #60] @ 0x3c 8014e22: 6b7b ldr r3, [r7, #52] @ 0x34 8014e24: 60fb str r3, [r7, #12] __asm volatile 8014e26: 68fb ldr r3, [r7, #12] 8014e28: f383 8811 msr BASEPRI, r3 } 8014e2c: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8014e2e: 6bfb ldr r3, [r7, #60] @ 0x3c } 8014e30: 4618 mov r0, r3 8014e32: 3740 adds r7, #64 @ 0x40 8014e34: 46bd mov sp, r7 8014e36: bd80 pop {r7, pc} 08014e38 : /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 8014e38: b580 push {r7, lr} 8014e3a: b08c sub sp, #48 @ 0x30 8014e3c: af00 add r7, sp, #0 8014e3e: 60f8 str r0, [r7, #12] 8014e40: 60b9 str r1, [r7, #8] 8014e42: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 8014e44: 2300 movs r3, #0 8014e46: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014e48: 68fb ldr r3, [r7, #12] 8014e4a: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8014e4c: 6abb ldr r3, [r7, #40] @ 0x28 8014e4e: 2b00 cmp r3, #0 8014e50: d10b bne.n 8014e6a __asm volatile 8014e52: f04f 0350 mov.w r3, #80 @ 0x50 8014e56: f383 8811 msr BASEPRI, r3 8014e5a: f3bf 8f6f isb sy 8014e5e: f3bf 8f4f dsb sy 8014e62: 623b str r3, [r7, #32] } 8014e64: bf00 nop 8014e66: bf00 nop 8014e68: e7fd b.n 8014e66 /* The buffer into which data is received can only be NULL if the data size * is zero (so no data is copied into the buffer). */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014e6a: 68bb ldr r3, [r7, #8] 8014e6c: 2b00 cmp r3, #0 8014e6e: d103 bne.n 8014e78 8014e70: 6abb ldr r3, [r7, #40] @ 0x28 8014e72: 6c1b ldr r3, [r3, #64] @ 0x40 8014e74: 2b00 cmp r3, #0 8014e76: d101 bne.n 8014e7c 8014e78: 2301 movs r3, #1 8014e7a: e000 b.n 8014e7e 8014e7c: 2300 movs r3, #0 8014e7e: 2b00 cmp r3, #0 8014e80: d10b bne.n 8014e9a __asm volatile 8014e82: f04f 0350 mov.w r3, #80 @ 0x50 8014e86: f383 8811 msr BASEPRI, r3 8014e8a: f3bf 8f6f isb sy 8014e8e: f3bf 8f4f dsb sy 8014e92: 61fb str r3, [r7, #28] } 8014e94: bf00 nop 8014e96: bf00 nop 8014e98: e7fd b.n 8014e96 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014e9a: f001 fc37 bl 801670c 8014e9e: 4603 mov r3, r0 8014ea0: 2b00 cmp r3, #0 8014ea2: d102 bne.n 8014eaa 8014ea4: 687b ldr r3, [r7, #4] 8014ea6: 2b00 cmp r3, #0 8014ea8: d101 bne.n 8014eae 8014eaa: 2301 movs r3, #1 8014eac: e000 b.n 8014eb0 8014eae: 2300 movs r3, #0 8014eb0: 2b00 cmp r3, #0 8014eb2: d10b bne.n 8014ecc __asm volatile 8014eb4: f04f 0350 mov.w r3, #80 @ 0x50 8014eb8: f383 8811 msr BASEPRI, r3 8014ebc: f3bf 8f6f isb sy 8014ec0: f3bf 8f4f dsb sy 8014ec4: 61bb str r3, [r7, #24] } 8014ec6: bf00 nop 8014ec8: bf00 nop 8014eca: e7fd b.n 8014ec8 /*lint -save -e904 This function relaxes the coding standard somewhat to * allow return statements within the function itself. This is done in the * interest of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); 8014ecc: f002 ff20 bl 8017d10 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014ed0: 6abb ldr r3, [r7, #40] @ 0x28 8014ed2: 6b9b ldr r3, [r3, #56] @ 0x38 8014ed4: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task * must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014ed6: 6a7b ldr r3, [r7, #36] @ 0x24 8014ed8: 2b00 cmp r3, #0 8014eda: d01f beq.n 8014f1c { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 8014edc: 68b9 ldr r1, [r7, #8] 8014ede: 6ab8 ldr r0, [r7, #40] @ 0x28 8014ee0: f000 facc bl 801547c traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8014ee4: 6a7b ldr r3, [r7, #36] @ 0x24 8014ee6: 1e5a subs r2, r3, #1 8014ee8: 6abb ldr r3, [r7, #40] @ 0x28 8014eea: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to * post to the queue? If so, unblock the highest priority waiting * task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014eec: 6abb ldr r3, [r7, #40] @ 0x28 8014eee: 691b ldr r3, [r3, #16] 8014ef0: 2b00 cmp r3, #0 8014ef2: d00f beq.n 8014f14 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014ef4: 6abb ldr r3, [r7, #40] @ 0x28 8014ef6: 3310 adds r3, #16 8014ef8: 4618 mov r0, r3 8014efa: f001 f9bb bl 8016274 8014efe: 4603 mov r3, r0 8014f00: 2b00 cmp r3, #0 8014f02: d007 beq.n 8014f14 { queueYIELD_IF_USING_PREEMPTION(); 8014f04: 4b3c ldr r3, [pc, #240] @ (8014ff8 ) 8014f06: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014f0a: 601a str r2, [r3, #0] 8014f0c: f3bf 8f4f dsb sy 8014f10: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8014f14: f002 ff2e bl 8017d74 return pdPASS; 8014f18: 2301 movs r3, #1 8014f1a: e069 b.n 8014ff0 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014f1c: 687b ldr r3, [r7, #4] 8014f1e: 2b00 cmp r3, #0 8014f20: d103 bne.n 8014f2a { /* The queue was empty and no block time is specified (or * the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014f22: f002 ff27 bl 8017d74 traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014f26: 2300 movs r3, #0 8014f28: e062 b.n 8014ff0 } else if( xEntryTimeSet == pdFALSE ) 8014f2a: 6afb ldr r3, [r7, #44] @ 0x2c 8014f2c: 2b00 cmp r3, #0 8014f2e: d106 bne.n 8014f3e { /* The queue was empty and a block time was specified so * configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014f30: f107 0310 add.w r3, r7, #16 8014f34: 4618 mov r0, r3 8014f36: f001 fa75 bl 8016424 xEntryTimeSet = pdTRUE; 8014f3a: 2301 movs r3, #1 8014f3c: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014f3e: f002 ff19 bl 8017d74 /* Interrupts and other tasks can send to and receive from the queue * now the critical section has been exited. */ vTaskSuspendAll(); 8014f42: f000 fe61 bl 8015c08 prvLockQueue( pxQueue ); 8014f46: f002 fee3 bl 8017d10 8014f4a: 6abb ldr r3, [r7, #40] @ 0x28 8014f4c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014f50: b25b sxtb r3, r3 8014f52: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f56: d103 bne.n 8014f60 8014f58: 6abb ldr r3, [r7, #40] @ 0x28 8014f5a: 2200 movs r2, #0 8014f5c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014f60: 6abb ldr r3, [r7, #40] @ 0x28 8014f62: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014f66: b25b sxtb r3, r3 8014f68: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f6c: d103 bne.n 8014f76 8014f6e: 6abb ldr r3, [r7, #40] @ 0x28 8014f70: 2200 movs r2, #0 8014f72: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014f76: f002 fefd bl 8017d74 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014f7a: 1d3a adds r2, r7, #4 8014f7c: f107 0310 add.w r3, r7, #16 8014f80: 4611 mov r1, r2 8014f82: 4618 mov r0, r3 8014f84: f001 fa64 bl 8016450 8014f88: 4603 mov r3, r0 8014f8a: 2b00 cmp r3, #0 8014f8c: d123 bne.n 8014fd6 { /* The timeout has not expired. If the queue is still empty place * the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014f8e: 6ab8 ldr r0, [r7, #40] @ 0x28 8014f90: f000 faec bl 801556c 8014f94: 4603 mov r3, r0 8014f96: 2b00 cmp r3, #0 8014f98: d017 beq.n 8014fca { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8014f9a: 6abb ldr r3, [r7, #40] @ 0x28 8014f9c: 3324 adds r3, #36 @ 0x24 8014f9e: 687a ldr r2, [r7, #4] 8014fa0: 4611 mov r1, r2 8014fa2: 4618 mov r0, r3 8014fa4: f001 f8fa bl 801619c prvUnlockQueue( pxQueue ); 8014fa8: 6ab8 ldr r0, [r7, #40] @ 0x28 8014faa: f000 fa8d bl 80154c8 if( xTaskResumeAll() == pdFALSE ) 8014fae: f000 fe39 bl 8015c24 8014fb2: 4603 mov r3, r0 8014fb4: 2b00 cmp r3, #0 8014fb6: d189 bne.n 8014ecc { portYIELD_WITHIN_API(); 8014fb8: 4b0f ldr r3, [pc, #60] @ (8014ff8 ) 8014fba: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014fbe: 601a str r2, [r3, #0] 8014fc0: f3bf 8f4f dsb sy 8014fc4: f3bf 8f6f isb sy 8014fc8: e780 b.n 8014ecc } else { /* The queue contains data again. Loop back to try and read the * data. */ prvUnlockQueue( pxQueue ); 8014fca: 6ab8 ldr r0, [r7, #40] @ 0x28 8014fcc: f000 fa7c bl 80154c8 ( void ) xTaskResumeAll(); 8014fd0: f000 fe28 bl 8015c24 8014fd4: e77a b.n 8014ecc } else { /* Timed out. If there is no data in the queue exit, otherwise loop * back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 8014fd6: 6ab8 ldr r0, [r7, #40] @ 0x28 8014fd8: f000 fa76 bl 80154c8 ( void ) xTaskResumeAll(); 8014fdc: f000 fe22 bl 8015c24 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014fe0: 6ab8 ldr r0, [r7, #40] @ 0x28 8014fe2: f000 fac3 bl 801556c 8014fe6: 4603 mov r3, r0 8014fe8: 2b00 cmp r3, #0 8014fea: f43f af6f beq.w 8014ecc { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014fee: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8014ff0: 4618 mov r0, r3 8014ff2: 3730 adds r7, #48 @ 0x30 8014ff4: 46bd mov sp, r7 8014ff6: bd80 pop {r7, pc} 8014ff8: e000ed04 .word 0xe000ed04 08014ffc : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 8014ffc: b580 push {r7, lr} 8014ffe: b08c sub sp, #48 @ 0x30 8015000: af00 add r7, sp, #0 8015002: 6078 str r0, [r7, #4] 8015004: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 8015006: 2300 movs r3, #0 8015008: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801500a: 687b ldr r3, [r7, #4] 801500c: 627b str r3, [r7, #36] @ 0x24 #if ( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 801500e: 2300 movs r3, #0 8015010: 62bb str r3, [r7, #40] @ 0x28 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8015012: 6a7b ldr r3, [r7, #36] @ 0x24 8015014: 2b00 cmp r3, #0 8015016: d10b bne.n 8015030 __asm volatile 8015018: f04f 0350 mov.w r3, #80 @ 0x50 801501c: f383 8811 msr BASEPRI, r3 8015020: f3bf 8f6f isb sy 8015024: f3bf 8f4f dsb sy 8015028: 61bb str r3, [r7, #24] } 801502a: bf00 nop 801502c: bf00 nop 801502e: e7fd b.n 801502c /* Check this really is a semaphore, in which case the item size will be * 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 8015030: 6a7b ldr r3, [r7, #36] @ 0x24 8015032: 6c1b ldr r3, [r3, #64] @ 0x40 8015034: 2b00 cmp r3, #0 8015036: d00b beq.n 8015050 __asm volatile 8015038: f04f 0350 mov.w r3, #80 @ 0x50 801503c: f383 8811 msr BASEPRI, r3 8015040: f3bf 8f6f isb sy 8015044: f3bf 8f4f dsb sy 8015048: 617b str r3, [r7, #20] } 801504a: bf00 nop 801504c: bf00 nop 801504e: e7fd b.n 801504c /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8015050: f001 fb5c bl 801670c 8015054: 4603 mov r3, r0 8015056: 2b00 cmp r3, #0 8015058: d102 bne.n 8015060 801505a: 683b ldr r3, [r7, #0] 801505c: 2b00 cmp r3, #0 801505e: d101 bne.n 8015064 8015060: 2301 movs r3, #1 8015062: e000 b.n 8015066 8015064: 2300 movs r3, #0 8015066: 2b00 cmp r3, #0 8015068: d10b bne.n 8015082 __asm volatile 801506a: f04f 0350 mov.w r3, #80 @ 0x50 801506e: f383 8811 msr BASEPRI, r3 8015072: f3bf 8f6f isb sy 8015076: f3bf 8f4f dsb sy 801507a: 613b str r3, [r7, #16] } 801507c: bf00 nop 801507e: bf00 nop 8015080: e7fd b.n 801507e /*lint -save -e904 This function relaxes the coding standard somewhat to allow return * statements within the function itself. This is done in the interest * of execution time efficiency. */ for( ; ; ) { taskENTER_CRITICAL(); 8015082: f002 fe45 bl 8017d10 { /* Semaphores are queues with an item size of 0, and where the * number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 8015086: 6a7b ldr r3, [r7, #36] @ 0x24 8015088: 6b9b ldr r3, [r3, #56] @ 0x38 801508a: 623b str r3, [r7, #32] /* Is there data in the queue now? To be running the calling task * must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 801508c: 6a3b ldr r3, [r7, #32] 801508e: 2b00 cmp r3, #0 8015090: d024 beq.n 80150dc { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the * messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 8015092: 6a3b ldr r3, [r7, #32] 8015094: 1e5a subs r2, r3, #1 8015096: 6a7b ldr r3, [r7, #36] @ 0x24 8015098: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801509a: 6a7b ldr r3, [r7, #36] @ 0x24 801509c: 681b ldr r3, [r3, #0] 801509e: 2b00 cmp r3, #0 80150a0: d104 bne.n 80150ac { /* Record the information required to implement * priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 80150a2: f001 fd25 bl 8016af0 80150a6: 4602 mov r2, r0 80150a8: 6a7b ldr r3, [r7, #36] @ 0x24 80150aa: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the * semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80150ac: 6a7b ldr r3, [r7, #36] @ 0x24 80150ae: 691b ldr r3, [r3, #16] 80150b0: 2b00 cmp r3, #0 80150b2: d00f beq.n 80150d4 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80150b4: 6a7b ldr r3, [r7, #36] @ 0x24 80150b6: 3310 adds r3, #16 80150b8: 4618 mov r0, r3 80150ba: f001 f8db bl 8016274 80150be: 4603 mov r3, r0 80150c0: 2b00 cmp r3, #0 80150c2: d007 beq.n 80150d4 { queueYIELD_IF_USING_PREEMPTION(); 80150c4: 4b4c ldr r3, [pc, #304] @ (80151f8 ) 80150c6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80150ca: 601a str r2, [r3, #0] 80150cc: f3bf 8f4f dsb sy 80150d0: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80150d4: f002 fe4e bl 8017d74 return pdPASS; 80150d8: 2301 movs r3, #1 80150da: e089 b.n 80151f0 } else { if( xTicksToWait == ( TickType_t ) 0 ) 80150dc: 683b ldr r3, [r7, #0] 80150de: 2b00 cmp r3, #0 80150e0: d103 bne.n 80150ea { /* The semaphore count was 0 and no block time is specified * (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 80150e2: f002 fe47 bl 8017d74 traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80150e6: 2300 movs r3, #0 80150e8: e082 b.n 80151f0 } else if( xEntryTimeSet == pdFALSE ) 80150ea: 6afb ldr r3, [r7, #44] @ 0x2c 80150ec: 2b00 cmp r3, #0 80150ee: d106 bne.n 80150fe { /* The semaphore count was 0 and a block time was specified * so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 80150f0: f107 0308 add.w r3, r7, #8 80150f4: 4618 mov r0, r3 80150f6: f001 f995 bl 8016424 xEntryTimeSet = pdTRUE; 80150fa: 2301 movs r3, #1 80150fc: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 80150fe: f002 fe39 bl 8017d74 /* Interrupts and other tasks can give to and take from the semaphore * now the critical section has been exited. */ vTaskSuspendAll(); 8015102: f000 fd81 bl 8015c08 prvLockQueue( pxQueue ); 8015106: f002 fe03 bl 8017d10 801510a: 6a7b ldr r3, [r7, #36] @ 0x24 801510c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8015110: b25b sxtb r3, r3 8015112: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015116: d103 bne.n 8015120 8015118: 6a7b ldr r3, [r7, #36] @ 0x24 801511a: 2200 movs r2, #0 801511c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8015120: 6a7b ldr r3, [r7, #36] @ 0x24 8015122: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015126: b25b sxtb r3, r3 8015128: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801512c: d103 bne.n 8015136 801512e: 6a7b ldr r3, [r7, #36] @ 0x24 8015130: 2200 movs r2, #0 8015132: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015136: f002 fe1d bl 8017d74 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 801513a: 463a mov r2, r7 801513c: f107 0308 add.w r3, r7, #8 8015140: 4611 mov r1, r2 8015142: 4618 mov r0, r3 8015144: f001 f984 bl 8016450 8015148: 4603 mov r3, r0 801514a: 2b00 cmp r3, #0 801514c: d132 bne.n 80151b4 { /* A block time is specified and not expired. If the semaphore * count is 0 then enter the Blocked state to wait for a semaphore to * become available. As semaphores are implemented with queues the * queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 801514e: 6a78 ldr r0, [r7, #36] @ 0x24 8015150: f000 fa0c bl 801556c 8015154: 4603 mov r3, r0 8015156: 2b00 cmp r3, #0 8015158: d026 beq.n 80151a8 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801515a: 6a7b ldr r3, [r7, #36] @ 0x24 801515c: 681b ldr r3, [r3, #0] 801515e: 2b00 cmp r3, #0 8015160: d109 bne.n 8015176 { taskENTER_CRITICAL(); 8015162: f002 fdd5 bl 8017d10 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 8015166: 6a7b ldr r3, [r7, #36] @ 0x24 8015168: 689b ldr r3, [r3, #8] 801516a: 4618 mov r0, r3 801516c: f001 faec bl 8016748 8015170: 62b8 str r0, [r7, #40] @ 0x28 } taskEXIT_CRITICAL(); 8015172: f002 fdff bl 8017d74 mtCOVERAGE_TEST_MARKER(); } } #endif /* if ( configUSE_MUTEXES == 1 ) */ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8015176: 6a7b ldr r3, [r7, #36] @ 0x24 8015178: 3324 adds r3, #36 @ 0x24 801517a: 683a ldr r2, [r7, #0] 801517c: 4611 mov r1, r2 801517e: 4618 mov r0, r3 8015180: f001 f80c bl 801619c prvUnlockQueue( pxQueue ); 8015184: 6a78 ldr r0, [r7, #36] @ 0x24 8015186: f000 f99f bl 80154c8 if( xTaskResumeAll() == pdFALSE ) 801518a: f000 fd4b bl 8015c24 801518e: 4603 mov r3, r0 8015190: 2b00 cmp r3, #0 8015192: f47f af76 bne.w 8015082 { portYIELD_WITHIN_API(); 8015196: 4b18 ldr r3, [pc, #96] @ (80151f8 ) 8015198: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801519c: 601a str r2, [r3, #0] 801519e: f3bf 8f4f dsb sy 80151a2: f3bf 8f6f isb sy 80151a6: e76c b.n 8015082 } else { /* There was no timeout and the semaphore count was not 0, so * attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 80151a8: 6a78 ldr r0, [r7, #36] @ 0x24 80151aa: f000 f98d bl 80154c8 ( void ) xTaskResumeAll(); 80151ae: f000 fd39 bl 8015c24 80151b2: e766 b.n 8015082 } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 80151b4: 6a78 ldr r0, [r7, #36] @ 0x24 80151b6: f000 f987 bl 80154c8 ( void ) xTaskResumeAll(); 80151ba: f000 fd33 bl 8015c24 /* If the semaphore count is 0 exit now as the timeout has * expired. Otherwise return to attempt to take the semaphore that is * known to be available. As semaphores are implemented by queues the * queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80151be: 6a78 ldr r0, [r7, #36] @ 0x24 80151c0: f000 f9d4 bl 801556c 80151c4: 4603 mov r3, r0 80151c6: 2b00 cmp r3, #0 80151c8: f43f af5b beq.w 8015082 #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to * test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 80151cc: 6abb ldr r3, [r7, #40] @ 0x28 80151ce: 2b00 cmp r3, #0 80151d0: d00d beq.n 80151ee { taskENTER_CRITICAL(); 80151d2: f002 fd9d bl 8017d10 /* This task blocking on the mutex caused another * task to inherit this task's priority. Now this task * has timed out the priority should be disinherited * again, but only as low as the next highest priority * task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 80151d6: 6a78 ldr r0, [r7, #36] @ 0x24 80151d8: f000 f8ce bl 8015378 80151dc: 61f8 str r0, [r7, #28] vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 80151de: 6a7b ldr r3, [r7, #36] @ 0x24 80151e0: 689b ldr r3, [r3, #8] 80151e2: 69f9 ldr r1, [r7, #28] 80151e4: 4618 mov r0, r3 80151e6: f001 fbd7 bl 8016998 } taskEXIT_CRITICAL(); 80151ea: f002 fdc3 bl 8017d74 } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80151ee: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 80151f0: 4618 mov r0, r3 80151f2: 3730 adds r7, #48 @ 0x30 80151f4: 46bd mov sp, r7 80151f6: bd80 pop {r7, pc} 80151f8: e000ed04 .word 0xe000ed04 080151fc : /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 80151fc: b580 push {r7, lr} 80151fe: b090 sub sp, #64 @ 0x40 8015200: af00 add r7, sp, #0 8015202: 60f8 str r0, [r7, #12] 8015204: 60b9 str r1, [r7, #8] 8015206: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8015208: 68fb ldr r3, [r7, #12] 801520a: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 801520c: 6bbb ldr r3, [r7, #56] @ 0x38 801520e: 2b00 cmp r3, #0 8015210: d10b bne.n 801522a __asm volatile 8015212: f04f 0350 mov.w r3, #80 @ 0x50 8015216: f383 8811 msr BASEPRI, r3 801521a: f3bf 8f6f isb sy 801521e: f3bf 8f4f dsb sy 8015222: 627b str r3, [r7, #36] @ 0x24 } 8015224: bf00 nop 8015226: bf00 nop 8015228: e7fd b.n 8015226 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 801522a: 68bb ldr r3, [r7, #8] 801522c: 2b00 cmp r3, #0 801522e: d103 bne.n 8015238 8015230: 6bbb ldr r3, [r7, #56] @ 0x38 8015232: 6c1b ldr r3, [r3, #64] @ 0x40 8015234: 2b00 cmp r3, #0 8015236: d101 bne.n 801523c 8015238: 2301 movs r3, #1 801523a: e000 b.n 801523e 801523c: 2300 movs r3, #0 801523e: 2b00 cmp r3, #0 8015240: d10b bne.n 801525a __asm volatile 8015242: f04f 0350 mov.w r3, #80 @ 0x50 8015246: f383 8811 msr BASEPRI, r3 801524a: f3bf 8f6f isb sy 801524e: f3bf 8f4f dsb sy 8015252: 623b str r3, [r7, #32] } 8015254: bf00 nop 8015256: bf00 nop 8015258: e7fd b.n 8015256 * that have been assigned a priority at or (logically) below the maximum * system call interrupt priority. FreeRTOS maintains a separate interrupt * safe API to ensure interrupt entry is as fast and as simple as possible. * More information (albeit Cortex-M specific) is provided on the following * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 801525a: f002 fe3f bl 8017edc __asm volatile 801525e: f3ef 8211 mrs r2, BASEPRI 8015262: f04f 0350 mov.w r3, #80 @ 0x50 8015266: f383 8811 msr BASEPRI, r3 801526a: f3bf 8f6f isb sy 801526e: f3bf 8f4f dsb sy 8015272: 61fa str r2, [r7, #28] 8015274: 61bb str r3, [r7, #24] return ulOriginalBASEPRI; 8015276: 69fb ldr r3, [r7, #28] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8015278: 637b str r3, [r7, #52] @ 0x34 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 801527a: 6bbb ldr r3, [r7, #56] @ 0x38 801527c: 6b9b ldr r3, [r3, #56] @ 0x38 801527e: 633b str r3, [r7, #48] @ 0x30 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8015280: 6b3b ldr r3, [r7, #48] @ 0x30 8015282: 2b00 cmp r3, #0 8015284: d047 beq.n 8015316 { const int8_t cRxLock = pxQueue->cRxLock; 8015286: 6bbb ldr r3, [r7, #56] @ 0x38 8015288: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801528c: f887 302f strb.w r3, [r7, #47] @ 0x2f traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 8015290: 68b9 ldr r1, [r7, #8] 8015292: 6bb8 ldr r0, [r7, #56] @ 0x38 8015294: f000 f8f2 bl 801547c pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8015298: 6b3b ldr r3, [r7, #48] @ 0x30 801529a: 1e5a subs r2, r3, #1 801529c: 6bbb ldr r3, [r7, #56] @ 0x38 801529e: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. * Instead update the lock count so the task that unlocks the queue * will know that an ISR has removed data while the queue was * locked. */ if( cRxLock == queueUNLOCKED ) 80152a0: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 80152a4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80152a8: d112 bne.n 80152d0 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80152aa: 6bbb ldr r3, [r7, #56] @ 0x38 80152ac: 691b ldr r3, [r3, #16] 80152ae: 2b00 cmp r3, #0 80152b0: d02e beq.n 8015310 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80152b2: 6bbb ldr r3, [r7, #56] @ 0x38 80152b4: 3310 adds r3, #16 80152b6: 4618 mov r0, r3 80152b8: f000 ffdc bl 8016274 80152bc: 4603 mov r3, r0 80152be: 2b00 cmp r3, #0 80152c0: d026 beq.n 8015310 { /* The task waiting has a higher priority than us so * force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 80152c2: 687b ldr r3, [r7, #4] 80152c4: 2b00 cmp r3, #0 80152c6: d023 beq.n 8015310 { *pxHigherPriorityTaskWoken = pdTRUE; 80152c8: 687b ldr r3, [r7, #4] 80152ca: 2201 movs r2, #1 80152cc: 601a str r2, [r3, #0] 80152ce: e01f b.n 8015310 } else { /* Increment the lock count so the task that unlocks the queue * knows that data was removed while it was locked. */ prvIncrementQueueRxLock( pxQueue, cRxLock ); 80152d0: f000 fdb6 bl 8015e40 80152d4: 62b8 str r0, [r7, #40] @ 0x28 80152d6: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 80152da: 6aba ldr r2, [r7, #40] @ 0x28 80152dc: 429a cmp r2, r3 80152de: d917 bls.n 8015310 80152e0: f997 302f ldrsb.w r3, [r7, #47] @ 0x2f 80152e4: 2b7f cmp r3, #127 @ 0x7f 80152e6: d10b bne.n 8015300 __asm volatile 80152e8: f04f 0350 mov.w r3, #80 @ 0x50 80152ec: f383 8811 msr BASEPRI, r3 80152f0: f3bf 8f6f isb sy 80152f4: f3bf 8f4f dsb sy 80152f8: 617b str r3, [r7, #20] } 80152fa: bf00 nop 80152fc: bf00 nop 80152fe: e7fd b.n 80152fc 8015300: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8015304: 3301 adds r3, #1 8015306: b2db uxtb r3, r3 8015308: b25a sxtb r2, r3 801530a: 6bbb ldr r3, [r7, #56] @ 0x38 801530c: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 8015310: 2301 movs r3, #1 8015312: 63fb str r3, [r7, #60] @ 0x3c 8015314: e001 b.n 801531a } else { xReturn = pdFAIL; 8015316: 2300 movs r3, #0 8015318: 63fb str r3, [r7, #60] @ 0x3c 801531a: 6b7b ldr r3, [r7, #52] @ 0x34 801531c: 613b str r3, [r7, #16] __asm volatile 801531e: 693b ldr r3, [r7, #16] 8015320: f383 8811 msr BASEPRI, r3 } 8015324: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8015326: 6bfb ldr r3, [r7, #60] @ 0x3c } 8015328: 4618 mov r0, r3 801532a: 3740 adds r7, #64 @ 0x40 801532c: 46bd mov sp, r7 801532e: bd80 pop {r7, pc} 08015330 : return uxReturn; } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ /*-----------------------------------------------------------*/ void vQueueDelete( QueueHandle_t xQueue ) { 8015330: b580 push {r7, lr} 8015332: b084 sub sp, #16 8015334: af00 add r7, sp, #0 8015336: 6078 str r0, [r7, #4] Queue_t * const pxQueue = xQueue; 8015338: 687b ldr r3, [r7, #4] 801533a: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 801533c: 68fb ldr r3, [r7, #12] 801533e: 2b00 cmp r3, #0 8015340: d10b bne.n 801535a __asm volatile 8015342: f04f 0350 mov.w r3, #80 @ 0x50 8015346: f383 8811 msr BASEPRI, r3 801534a: f3bf 8f6f isb sy 801534e: f3bf 8f4f dsb sy 8015352: 60bb str r3, [r7, #8] } 8015354: bf00 nop 8015356: bf00 nop 8015358: e7fd b.n 8015356 traceQUEUE_DELETE( pxQueue ); #if ( configQUEUE_REGISTRY_SIZE > 0 ) { vQueueUnregisterQueue( pxQueue ); 801535a: 68f8 ldr r0, [r7, #12] 801535c: f000 f984 bl 8015668 } #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) { /* The queue could have been allocated statically or dynamically, so * check before attempting to free the memory. */ if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) 8015360: 68fb ldr r3, [r7, #12] 8015362: f893 3046 ldrb.w r3, [r3, #70] @ 0x46 8015366: 2b00 cmp r3, #0 8015368: d102 bne.n 8015370 { vPortFree( pxQueue ); 801536a: 68f8 ldr r0, [r7, #12] 801536c: f002 fec4 bl 80180f8 /* The queue must have been statically allocated, so is not going to be * deleted. Avoid compiler warnings about the unused parameter. */ ( void ) pxQueue; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8015370: bf00 nop 8015372: 3710 adds r7, #16 8015374: 46bd mov sp, r7 8015376: bd80 pop {r7, pc} 08015378 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 8015378: b480 push {r7} 801537a: b085 sub sp, #20 801537c: af00 add r7, sp, #0 801537e: 6078 str r0, [r7, #4] * priority, but the waiting task times out, then the holder should * disinherit the priority - but only down to the highest priority of any * other tasks that are waiting for the same mutex. For this purpose, * return the priority of the highest priority task that is waiting for the * mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 8015380: 687b ldr r3, [r7, #4] 8015382: 6a5b ldr r3, [r3, #36] @ 0x24 8015384: 2b00 cmp r3, #0 8015386: d006 beq.n 8015396 { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 8015388: 687b ldr r3, [r7, #4] 801538a: 6b1b ldr r3, [r3, #48] @ 0x30 801538c: 681b ldr r3, [r3, #0] 801538e: f1c3 0338 rsb r3, r3, #56 @ 0x38 8015392: 60fb str r3, [r7, #12] 8015394: e001 b.n 801539a } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 8015396: 2300 movs r3, #0 8015398: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 801539a: 68fb ldr r3, [r7, #12] } 801539c: 4618 mov r0, r3 801539e: 3714 adds r7, #20 80153a0: 46bd mov sp, r7 80153a2: f85d 7b04 ldr.w r7, [sp], #4 80153a6: 4770 bx lr 080153a8 : /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void * pvItemToQueue, const BaseType_t xPosition ) { 80153a8: b580 push {r7, lr} 80153aa: b086 sub sp, #24 80153ac: af00 add r7, sp, #0 80153ae: 60f8 str r0, [r7, #12] 80153b0: 60b9 str r1, [r7, #8] 80153b2: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 80153b4: 2300 movs r3, #0 80153b6: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80153b8: 68fb ldr r3, [r7, #12] 80153ba: 6b9b ldr r3, [r3, #56] @ 0x38 80153bc: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 80153be: 68fb ldr r3, [r7, #12] 80153c0: 6c1b ldr r3, [r3, #64] @ 0x40 80153c2: 2b00 cmp r3, #0 80153c4: d10d bne.n 80153e2 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80153c6: 68fb ldr r3, [r7, #12] 80153c8: 681b ldr r3, [r3, #0] 80153ca: 2b00 cmp r3, #0 80153cc: d14d bne.n 801546a { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 80153ce: 68fb ldr r3, [r7, #12] 80153d0: 689b ldr r3, [r3, #8] 80153d2: 4618 mov r0, r3 80153d4: f001 fa48 bl 8016868 80153d8: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 80153da: 68fb ldr r3, [r7, #12] 80153dc: 2200 movs r2, #0 80153de: 609a str r2, [r3, #8] 80153e0: e043 b.n 801546a mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 80153e2: 687b ldr r3, [r7, #4] 80153e4: 2b00 cmp r3, #0 80153e6: d119 bne.n 801541c { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 80153e8: 68fb ldr r3, [r7, #12] 80153ea: 6858 ldr r0, [r3, #4] 80153ec: 68fb ldr r3, [r7, #12] 80153ee: 6c1b ldr r3, [r3, #64] @ 0x40 80153f0: 461a mov r2, r3 80153f2: 68b9 ldr r1, [r7, #8] 80153f4: f005 f853 bl 801a49e pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 80153f8: 68fb ldr r3, [r7, #12] 80153fa: 685a ldr r2, [r3, #4] 80153fc: 68fb ldr r3, [r7, #12] 80153fe: 6c1b ldr r3, [r3, #64] @ 0x40 8015400: 441a add r2, r3 8015402: 68fb ldr r3, [r7, #12] 8015404: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8015406: 68fb ldr r3, [r7, #12] 8015408: 685a ldr r2, [r3, #4] 801540a: 68fb ldr r3, [r7, #12] 801540c: 689b ldr r3, [r3, #8] 801540e: 429a cmp r2, r3 8015410: d32b bcc.n 801546a { pxQueue->pcWriteTo = pxQueue->pcHead; 8015412: 68fb ldr r3, [r7, #12] 8015414: 681a ldr r2, [r3, #0] 8015416: 68fb ldr r3, [r7, #12] 8015418: 605a str r2, [r3, #4] 801541a: e026 b.n 801546a mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 801541c: 68fb ldr r3, [r7, #12] 801541e: 68d8 ldr r0, [r3, #12] 8015420: 68fb ldr r3, [r7, #12] 8015422: 6c1b ldr r3, [r3, #64] @ 0x40 8015424: 461a mov r2, r3 8015426: 68b9 ldr r1, [r7, #8] 8015428: f005 f839 bl 801a49e pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 801542c: 68fb ldr r3, [r7, #12] 801542e: 68da ldr r2, [r3, #12] 8015430: 68fb ldr r3, [r7, #12] 8015432: 6c1b ldr r3, [r3, #64] @ 0x40 8015434: 425b negs r3, r3 8015436: 441a add r2, r3 8015438: 68fb ldr r3, [r7, #12] 801543a: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 801543c: 68fb ldr r3, [r7, #12] 801543e: 68da ldr r2, [r3, #12] 8015440: 68fb ldr r3, [r7, #12] 8015442: 681b ldr r3, [r3, #0] 8015444: 429a cmp r2, r3 8015446: d207 bcs.n 8015458 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 8015448: 68fb ldr r3, [r7, #12] 801544a: 689a ldr r2, [r3, #8] 801544c: 68fb ldr r3, [r7, #12] 801544e: 6c1b ldr r3, [r3, #64] @ 0x40 8015450: 425b negs r3, r3 8015452: 441a add r2, r3 8015454: 68fb ldr r3, [r7, #12] 8015456: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8015458: 687b ldr r3, [r7, #4] 801545a: 2b02 cmp r3, #2 801545c: d105 bne.n 801546a { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 801545e: 693b ldr r3, [r7, #16] 8015460: 2b00 cmp r3, #0 8015462: d002 beq.n 801546a { /* An item is not being added but overwritten, so subtract * one from the recorded number of items in the queue so when * one is added again below the number of recorded items remains * correct. */ --uxMessagesWaiting; 8015464: 693b ldr r3, [r7, #16] 8015466: 3b01 subs r3, #1 8015468: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 801546a: 693b ldr r3, [r7, #16] 801546c: 1c5a adds r2, r3, #1 801546e: 68fb ldr r3, [r7, #12] 8015470: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8015472: 697b ldr r3, [r7, #20] } 8015474: 4618 mov r0, r3 8015476: 3718 adds r7, #24 8015478: 46bd mov sp, r7 801547a: bd80 pop {r7, pc} 0801547c : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 801547c: b580 push {r7, lr} 801547e: b082 sub sp, #8 8015480: af00 add r7, sp, #0 8015482: 6078 str r0, [r7, #4] 8015484: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 8015486: 687b ldr r3, [r7, #4] 8015488: 6c1b ldr r3, [r3, #64] @ 0x40 801548a: 2b00 cmp r3, #0 801548c: d018 beq.n 80154c0 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 801548e: 687b ldr r3, [r7, #4] 8015490: 68da ldr r2, [r3, #12] 8015492: 687b ldr r3, [r7, #4] 8015494: 6c1b ldr r3, [r3, #64] @ 0x40 8015496: 441a add r2, r3 8015498: 687b ldr r3, [r7, #4] 801549a: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 801549c: 687b ldr r3, [r7, #4] 801549e: 68da ldr r2, [r3, #12] 80154a0: 687b ldr r3, [r7, #4] 80154a2: 689b ldr r3, [r3, #8] 80154a4: 429a cmp r2, r3 80154a6: d303 bcc.n 80154b0 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 80154a8: 687b ldr r3, [r7, #4] 80154aa: 681a ldr r2, [r3, #0] 80154ac: 687b ldr r3, [r7, #4] 80154ae: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 80154b0: 687b ldr r3, [r7, #4] 80154b2: 68d9 ldr r1, [r3, #12] 80154b4: 687b ldr r3, [r7, #4] 80154b6: 6c1b ldr r3, [r3, #64] @ 0x40 80154b8: 461a mov r2, r3 80154ba: 6838 ldr r0, [r7, #0] 80154bc: f004 ffef bl 801a49e } } 80154c0: bf00 nop 80154c2: 3708 adds r7, #8 80154c4: 46bd mov sp, r7 80154c6: bd80 pop {r7, pc} 080154c8 : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 80154c8: b580 push {r7, lr} 80154ca: b084 sub sp, #16 80154cc: af00 add r7, sp, #0 80154ce: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or * removed from the queue while the queue was locked. When a queue is * locked items can be added or removed, but the event lists cannot be * updated. */ taskENTER_CRITICAL(); 80154d0: f002 fc1e bl 8017d10 { int8_t cTxLock = pxQueue->cTxLock; 80154d4: 687b ldr r3, [r7, #4] 80154d6: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80154da: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 80154dc: e011 b.n 8015502 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to * the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80154de: 687b ldr r3, [r7, #4] 80154e0: 6a5b ldr r3, [r3, #36] @ 0x24 80154e2: 2b00 cmp r3, #0 80154e4: d012 beq.n 801550c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80154e6: 687b ldr r3, [r7, #4] 80154e8: 3324 adds r3, #36 @ 0x24 80154ea: 4618 mov r0, r3 80154ec: f000 fec2 bl 8016274 80154f0: 4603 mov r3, r0 80154f2: 2b00 cmp r3, #0 80154f4: d001 beq.n 80154fa { /* The task waiting has a higher priority so record that * a context switch is required. */ vTaskMissedYield(); 80154f6: f001 f813 bl 8016520 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 80154fa: 7bfb ldrb r3, [r7, #15] 80154fc: 3b01 subs r3, #1 80154fe: b2db uxtb r3, r3 8015500: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8015502: f997 300f ldrsb.w r3, [r7, #15] 8015506: 2b00 cmp r3, #0 8015508: dce9 bgt.n 80154de 801550a: e000 b.n 801550e break; 801550c: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 801550e: 687b ldr r3, [r7, #4] 8015510: 22ff movs r2, #255 @ 0xff 8015512: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 8015516: f002 fc2d bl 8017d74 /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 801551a: f002 fbf9 bl 8017d10 { int8_t cRxLock = pxQueue->cRxLock; 801551e: 687b ldr r3, [r7, #4] 8015520: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8015524: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8015526: e011 b.n 801554c { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8015528: 687b ldr r3, [r7, #4] 801552a: 691b ldr r3, [r3, #16] 801552c: 2b00 cmp r3, #0 801552e: d012 beq.n 8015556 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8015530: 687b ldr r3, [r7, #4] 8015532: 3310 adds r3, #16 8015534: 4618 mov r0, r3 8015536: f000 fe9d bl 8016274 801553a: 4603 mov r3, r0 801553c: 2b00 cmp r3, #0 801553e: d001 beq.n 8015544 { vTaskMissedYield(); 8015540: f000 ffee bl 8016520 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 8015544: 7bbb ldrb r3, [r7, #14] 8015546: 3b01 subs r3, #1 8015548: b2db uxtb r3, r3 801554a: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 801554c: f997 300e ldrsb.w r3, [r7, #14] 8015550: 2b00 cmp r3, #0 8015552: dce9 bgt.n 8015528 8015554: e000 b.n 8015558 } else { break; 8015556: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8015558: 687b ldr r3, [r7, #4] 801555a: 22ff movs r2, #255 @ 0xff 801555c: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 8015560: f002 fc08 bl 8017d74 } 8015564: bf00 nop 8015566: 3710 adds r7, #16 8015568: 46bd mov sp, r7 801556a: bd80 pop {r7, pc} 0801556c : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) { 801556c: b580 push {r7, lr} 801556e: b084 sub sp, #16 8015570: af00 add r7, sp, #0 8015572: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8015574: f002 fbcc bl 8017d10 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 8015578: 687b ldr r3, [r7, #4] 801557a: 6b9b ldr r3, [r3, #56] @ 0x38 801557c: 2b00 cmp r3, #0 801557e: d102 bne.n 8015586 { xReturn = pdTRUE; 8015580: 2301 movs r3, #1 8015582: 60fb str r3, [r7, #12] 8015584: e001 b.n 801558a } else { xReturn = pdFALSE; 8015586: 2300 movs r3, #0 8015588: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 801558a: f002 fbf3 bl 8017d74 return xReturn; 801558e: 68fb ldr r3, [r7, #12] } 8015590: 4618 mov r0, r3 8015592: 3710 adds r7, #16 8015594: 46bd mov sp, r7 8015596: bd80 pop {r7, pc} 08015598 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) { 8015598: b580 push {r7, lr} 801559a: b084 sub sp, #16 801559c: af00 add r7, sp, #0 801559e: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 80155a0: f002 fbb6 bl 8017d10 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 80155a4: 687b ldr r3, [r7, #4] 80155a6: 6b9a ldr r2, [r3, #56] @ 0x38 80155a8: 687b ldr r3, [r7, #4] 80155aa: 6bdb ldr r3, [r3, #60] @ 0x3c 80155ac: 429a cmp r2, r3 80155ae: d102 bne.n 80155b6 { xReturn = pdTRUE; 80155b0: 2301 movs r3, #1 80155b2: 60fb str r3, [r7, #12] 80155b4: e001 b.n 80155ba } else { xReturn = pdFALSE; 80155b6: 2300 movs r3, #0 80155b8: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 80155ba: f002 fbdb bl 8017d74 return xReturn; 80155be: 68fb ldr r3, [r7, #12] } 80155c0: 4618 mov r0, r3 80155c2: 3710 adds r7, #16 80155c4: 46bd mov sp, r7 80155c6: bd80 pop {r7, pc} 080155c8 : #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 80155c8: b480 push {r7} 80155ca: b087 sub sp, #28 80155cc: af00 add r7, sp, #0 80155ce: 6078 str r0, [r7, #4] 80155d0: 6039 str r1, [r7, #0] UBaseType_t ux; QueueRegistryItem_t * pxEntryToWrite = NULL; 80155d2: 2300 movs r3, #0 80155d4: 613b str r3, [r7, #16] configASSERT( xQueue ); 80155d6: 687b ldr r3, [r7, #4] 80155d8: 2b00 cmp r3, #0 80155da: d10b bne.n 80155f4 __asm volatile 80155dc: f04f 0350 mov.w r3, #80 @ 0x50 80155e0: f383 8811 msr BASEPRI, r3 80155e4: f3bf 8f6f isb sy 80155e8: f3bf 8f4f dsb sy 80155ec: 60fb str r3, [r7, #12] } 80155ee: bf00 nop 80155f0: bf00 nop 80155f2: e7fd b.n 80155f0 if( pcQueueName != NULL ) 80155f4: 683b ldr r3, [r7, #0] 80155f6: 2b00 cmp r3, #0 80155f8: d024 beq.n 8015644 { /* See if there is an empty space in the registry. A NULL name denotes * a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 80155fa: 2300 movs r3, #0 80155fc: 617b str r3, [r7, #20] 80155fe: e01e b.n 801563e { /* Replace an existing entry if the queue is already in the registry. */ if( xQueue == xQueueRegistry[ ux ].xHandle ) 8015600: 4a18 ldr r2, [pc, #96] @ (8015664 ) 8015602: 697b ldr r3, [r7, #20] 8015604: 00db lsls r3, r3, #3 8015606: 4413 add r3, r2 8015608: 685b ldr r3, [r3, #4] 801560a: 687a ldr r2, [r7, #4] 801560c: 429a cmp r2, r3 801560e: d105 bne.n 801561c { pxEntryToWrite = &( xQueueRegistry[ ux ] ); 8015610: 697b ldr r3, [r7, #20] 8015612: 00db lsls r3, r3, #3 8015614: 4a13 ldr r2, [pc, #76] @ (8015664 ) 8015616: 4413 add r3, r2 8015618: 613b str r3, [r7, #16] break; 801561a: e013 b.n 8015644 } /* Otherwise, store in the next empty location */ else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) ) 801561c: 693b ldr r3, [r7, #16] 801561e: 2b00 cmp r3, #0 8015620: d10a bne.n 8015638 8015622: 4a10 ldr r2, [pc, #64] @ (8015664 ) 8015624: 697b ldr r3, [r7, #20] 8015626: f852 3033 ldr.w r3, [r2, r3, lsl #3] 801562a: 2b00 cmp r3, #0 801562c: d104 bne.n 8015638 { pxEntryToWrite = &( xQueueRegistry[ ux ] ); 801562e: 697b ldr r3, [r7, #20] 8015630: 00db lsls r3, r3, #3 8015632: 4a0c ldr r2, [pc, #48] @ (8015664 ) 8015634: 4413 add r3, r2 8015636: 613b str r3, [r7, #16] for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8015638: 697b ldr r3, [r7, #20] 801563a: 3301 adds r3, #1 801563c: 617b str r3, [r7, #20] 801563e: 697b ldr r3, [r7, #20] 8015640: 2b07 cmp r3, #7 8015642: d9dd bls.n 8015600 mtCOVERAGE_TEST_MARKER(); } } } if( pxEntryToWrite != NULL ) 8015644: 693b ldr r3, [r7, #16] 8015646: 2b00 cmp r3, #0 8015648: d005 beq.n 8015656 { /* Store the information on this queue. */ pxEntryToWrite->pcQueueName = pcQueueName; 801564a: 693b ldr r3, [r7, #16] 801564c: 683a ldr r2, [r7, #0] 801564e: 601a str r2, [r3, #0] pxEntryToWrite->xHandle = xQueue; 8015650: 693b ldr r3, [r7, #16] 8015652: 687a ldr r2, [r7, #4] 8015654: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); } } 8015656: bf00 nop 8015658: 371c adds r7, #28 801565a: 46bd mov sp, r7 801565c: f85d 7b04 ldr.w r7, [sp], #4 8015660: 4770 bx lr 8015662: bf00 nop 8015664: 20002128 .word 0x20002128 08015668 : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueUnregisterQueue( QueueHandle_t xQueue ) { 8015668: b480 push {r7} 801566a: b085 sub sp, #20 801566c: af00 add r7, sp, #0 801566e: 6078 str r0, [r7, #4] UBaseType_t ux; configASSERT( xQueue ); 8015670: 687b ldr r3, [r7, #4] 8015672: 2b00 cmp r3, #0 8015674: d10b bne.n 801568e __asm volatile 8015676: f04f 0350 mov.w r3, #80 @ 0x50 801567a: f383 8811 msr BASEPRI, r3 801567e: f3bf 8f6f isb sy 8015682: f3bf 8f4f dsb sy 8015686: 60bb str r3, [r7, #8] } 8015688: bf00 nop 801568a: bf00 nop 801568c: e7fd b.n 801568a /* See if the handle of the queue being unregistered in actually in the * registry. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 801568e: 2300 movs r3, #0 8015690: 60fb str r3, [r7, #12] 8015692: e016 b.n 80156c2 { if( xQueueRegistry[ ux ].xHandle == xQueue ) 8015694: 4a10 ldr r2, [pc, #64] @ (80156d8 ) 8015696: 68fb ldr r3, [r7, #12] 8015698: 00db lsls r3, r3, #3 801569a: 4413 add r3, r2 801569c: 685b ldr r3, [r3, #4] 801569e: 687a ldr r2, [r7, #4] 80156a0: 429a cmp r2, r3 80156a2: d10b bne.n 80156bc { /* Set the name to NULL to show that this slot if free again. */ xQueueRegistry[ ux ].pcQueueName = NULL; 80156a4: 4a0c ldr r2, [pc, #48] @ (80156d8 ) 80156a6: 68fb ldr r3, [r7, #12] 80156a8: 2100 movs r1, #0 80156aa: f842 1033 str.w r1, [r2, r3, lsl #3] /* Set the handle to NULL to ensure the same queue handle cannot * appear in the registry twice if it is added, removed, then * added again. */ xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; 80156ae: 4a0a ldr r2, [pc, #40] @ (80156d8 ) 80156b0: 68fb ldr r3, [r7, #12] 80156b2: 00db lsls r3, r3, #3 80156b4: 4413 add r3, r2 80156b6: 2200 movs r2, #0 80156b8: 605a str r2, [r3, #4] break; 80156ba: e006 b.n 80156ca for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 80156bc: 68fb ldr r3, [r7, #12] 80156be: 3301 adds r3, #1 80156c0: 60fb str r3, [r7, #12] 80156c2: 68fb ldr r3, [r7, #12] 80156c4: 2b07 cmp r3, #7 80156c6: d9e5 bls.n 8015694 else { mtCOVERAGE_TEST_MARKER(); } } } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ 80156c8: bf00 nop 80156ca: bf00 nop 80156cc: 3714 adds r7, #20 80156ce: 46bd mov sp, r7 80156d0: f85d 7b04 ldr.w r7, [sp], #4 80156d4: 4770 bx lr 80156d6: bf00 nop 80156d8: 20002128 .word 0x20002128 080156dc : #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 80156dc: b580 push {r7, lr} 80156de: b086 sub sp, #24 80156e0: af00 add r7, sp, #0 80156e2: 60f8 str r0, [r7, #12] 80156e4: 60b9 str r1, [r7, #8] 80156e6: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 80156e8: 68fb ldr r3, [r7, #12] 80156ea: 617b str r3, [r7, #20] * will not actually cause the task to block, just place it on a blocked * list. It will not block until the scheduler is unlocked - at which * time a yield will be performed. If an item is added to the queue while * the queue is locked, and the calling task blocks on the queue, then the * calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 80156ec: f002 fb10 bl 8017d10 80156f0: 697b ldr r3, [r7, #20] 80156f2: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80156f6: b25b sxtb r3, r3 80156f8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80156fc: d103 bne.n 8015706 80156fe: 697b ldr r3, [r7, #20] 8015700: 2200 movs r2, #0 8015702: f883 2044 strb.w r2, [r3, #68] @ 0x44 8015706: 697b ldr r3, [r7, #20] 8015708: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801570c: b25b sxtb r3, r3 801570e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015712: d103 bne.n 801571c 8015714: 697b ldr r3, [r7, #20] 8015716: 2200 movs r2, #0 8015718: f883 2045 strb.w r2, [r3, #69] @ 0x45 801571c: f002 fb2a bl 8017d74 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8015720: 697b ldr r3, [r7, #20] 8015722: 6b9b ldr r3, [r3, #56] @ 0x38 8015724: 2b00 cmp r3, #0 8015726: d106 bne.n 8015736 { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8015728: 697b ldr r3, [r7, #20] 801572a: 3324 adds r3, #36 @ 0x24 801572c: 687a ldr r2, [r7, #4] 801572e: 68b9 ldr r1, [r7, #8] 8015730: 4618 mov r0, r3 8015732: f000 fd59 bl 80161e8 else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8015736: 6978 ldr r0, [r7, #20] 8015738: f7ff fec6 bl 80154c8 } 801573c: bf00 nop 801573e: 3718 adds r7, #24 8015740: 46bd mov sp, r7 8015742: bd80 pop {r7, pc} 08015744 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8015744: b580 push {r7, lr} 8015746: b08e sub sp, #56 @ 0x38 8015748: af04 add r7, sp, #16 801574a: 60f8 str r0, [r7, #12] 801574c: 60b9 str r1, [r7, #8] 801574e: 607a str r2, [r7, #4] 8015750: 603b str r3, [r7, #0] TCB_t * pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8015752: 6b7b ldr r3, [r7, #52] @ 0x34 8015754: 2b00 cmp r3, #0 8015756: d10b bne.n 8015770 __asm volatile 8015758: f04f 0350 mov.w r3, #80 @ 0x50 801575c: f383 8811 msr BASEPRI, r3 8015760: f3bf 8f6f isb sy 8015764: f3bf 8f4f dsb sy 8015768: 623b str r3, [r7, #32] } 801576a: bf00 nop 801576c: bf00 nop 801576e: e7fd b.n 801576c configASSERT( pxTaskBuffer != NULL ); 8015770: 6bbb ldr r3, [r7, #56] @ 0x38 8015772: 2b00 cmp r3, #0 8015774: d10b bne.n 801578e __asm volatile 8015776: f04f 0350 mov.w r3, #80 @ 0x50 801577a: f383 8811 msr BASEPRI, r3 801577e: f3bf 8f6f isb sy 8015782: f3bf 8f4f dsb sy 8015786: 61fb str r3, [r7, #28] } 8015788: bf00 nop 801578a: bf00 nop 801578c: e7fd b.n 801578a #if ( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a * variable of type StaticTask_t equals the size of the real task * structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 801578e: 23ac movs r3, #172 @ 0xac 8015790: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8015792: 693b ldr r3, [r7, #16] 8015794: 2bac cmp r3, #172 @ 0xac 8015796: d00b beq.n 80157b0 __asm volatile 8015798: f04f 0350 mov.w r3, #80 @ 0x50 801579c: f383 8811 msr BASEPRI, r3 80157a0: f3bf 8f6f isb sy 80157a4: f3bf 8f4f dsb sy 80157a8: 61bb str r3, [r7, #24] } 80157aa: bf00 nop 80157ac: bf00 nop 80157ae: e7fd b.n 80157ac ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 80157b0: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 80157b2: 6bbb ldr r3, [r7, #56] @ 0x38 80157b4: 2b00 cmp r3, #0 80157b6: d023 beq.n 8015800 80157b8: 6b7b ldr r3, [r7, #52] @ 0x34 80157ba: 2b00 cmp r3, #0 80157bc: d020 beq.n 8015800 { /* The memory used for the task's TCB and stack are passed into this * function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 80157be: 6bbb ldr r3, [r7, #56] @ 0x38 80157c0: 627b str r3, [r7, #36] @ 0x24 memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); 80157c2: 22ac movs r2, #172 @ 0xac 80157c4: 2100 movs r1, #0 80157c6: 6a78 ldr r0, [r7, #36] @ 0x24 80157c8: f004 fd8c bl 801a2e4 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 80157cc: 6a7b ldr r3, [r7, #36] @ 0x24 80157ce: 6b7a ldr r2, [r7, #52] @ 0x34 80157d0: 631a str r2, [r3, #48] @ 0x30 #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this * task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 80157d2: 6a7b ldr r3, [r7, #36] @ 0x24 80157d4: 2202 movs r2, #2 80157d6: f883 20aa strb.w r2, [r3, #170] @ 0xaa } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 80157da: 2300 movs r3, #0 80157dc: 9303 str r3, [sp, #12] 80157de: 6a7b ldr r3, [r7, #36] @ 0x24 80157e0: 9302 str r3, [sp, #8] 80157e2: f107 0314 add.w r3, r7, #20 80157e6: 9301 str r3, [sp, #4] 80157e8: 6b3b ldr r3, [r7, #48] @ 0x30 80157ea: 9300 str r3, [sp, #0] 80157ec: 683b ldr r3, [r7, #0] 80157ee: 687a ldr r2, [r7, #4] 80157f0: 68b9 ldr r1, [r7, #8] 80157f2: 68f8 ldr r0, [r7, #12] 80157f4: f000 f856 bl 80158a4 prvAddNewTaskToReadyList( pxNewTCB ); 80157f8: 6a78 ldr r0, [r7, #36] @ 0x24 80157fa: f000 f8f9 bl 80159f0 80157fe: e001 b.n 8015804 } else { xReturn = NULL; 8015800: 2300 movs r3, #0 8015802: 617b str r3, [r7, #20] } return xReturn; 8015804: 697b ldr r3, [r7, #20] } 8015806: 4618 mov r0, r3 8015808: 3728 adds r7, #40 @ 0x28 801580a: 46bd mov sp, r7 801580c: bd80 pop {r7, pc} 0801580e : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 801580e: b580 push {r7, lr} 8015810: b08c sub sp, #48 @ 0x30 8015812: af04 add r7, sp, #16 8015814: 60f8 str r0, [r7, #12] 8015816: 60b9 str r1, [r7, #8] 8015818: 603b str r3, [r7, #0] 801581a: 4613 mov r3, r2 801581c: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t * pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMallocStack( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 801581e: 88fb ldrh r3, [r7, #6] 8015820: 009b lsls r3, r3, #2 8015822: 4618 mov r0, r3 8015824: f002 fb9c bl 8017f60 8015828: 6178 str r0, [r7, #20] if( pxStack != NULL ) 801582a: 697b ldr r3, [r7, #20] 801582c: 2b00 cmp r3, #0 801582e: d013 beq.n 8015858 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8015830: 20ac movs r0, #172 @ 0xac 8015832: f002 fb95 bl 8017f60 8015836: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8015838: 69fb ldr r3, [r7, #28] 801583a: 2b00 cmp r3, #0 801583c: d008 beq.n 8015850 { memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); 801583e: 22ac movs r2, #172 @ 0xac 8015840: 2100 movs r1, #0 8015842: 69f8 ldr r0, [r7, #28] 8015844: f004 fd4e bl 801a2e4 /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8015848: 69fb ldr r3, [r7, #28] 801584a: 697a ldr r2, [r7, #20] 801584c: 631a str r2, [r3, #48] @ 0x30 801584e: e005 b.n 801585c } else { /* The stack cannot be used as the TCB was not created. Free * it again. */ vPortFreeStack( pxStack ); 8015850: 6978 ldr r0, [r7, #20] 8015852: f002 fc51 bl 80180f8 8015856: e001 b.n 801585c } } else { pxNewTCB = NULL; 8015858: 2300 movs r3, #0 801585a: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 801585c: 69fb ldr r3, [r7, #28] 801585e: 2b00 cmp r3, #0 8015860: d017 beq.n 8015892 { #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this * task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8015862: 69fb ldr r3, [r7, #28] 8015864: 2200 movs r2, #0 8015866: f883 20aa strb.w r2, [r3, #170] @ 0xaa } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 801586a: 88fa ldrh r2, [r7, #6] 801586c: 2300 movs r3, #0 801586e: 9303 str r3, [sp, #12] 8015870: 69fb ldr r3, [r7, #28] 8015872: 9302 str r3, [sp, #8] 8015874: 6afb ldr r3, [r7, #44] @ 0x2c 8015876: 9301 str r3, [sp, #4] 8015878: 6abb ldr r3, [r7, #40] @ 0x28 801587a: 9300 str r3, [sp, #0] 801587c: 683b ldr r3, [r7, #0] 801587e: 68b9 ldr r1, [r7, #8] 8015880: 68f8 ldr r0, [r7, #12] 8015882: f000 f80f bl 80158a4 prvAddNewTaskToReadyList( pxNewTCB ); 8015886: 69f8 ldr r0, [r7, #28] 8015888: f000 f8b2 bl 80159f0 xReturn = pdPASS; 801588c: 2301 movs r3, #1 801588e: 61bb str r3, [r7, #24] 8015890: e002 b.n 8015898 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8015892: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015896: 61bb str r3, [r7, #24] } return xReturn; 8015898: 69bb ldr r3, [r7, #24] } 801589a: 4618 mov r0, r3 801589c: 3720 adds r7, #32 801589e: 46bd mov sp, r7 80158a0: bd80 pop {r7, pc} ... 080158a4 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t * pxNewTCB, const MemoryRegion_t * const xRegions ) { 80158a4: b580 push {r7, lr} 80158a6: b088 sub sp, #32 80158a8: af00 add r7, sp, #0 80158aa: 60f8 str r0, [r7, #12] 80158ac: 60b9 str r1, [r7, #8] 80158ae: 607a str r2, [r7, #4] 80158b0: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 80158b2: 6b3b ldr r3, [r7, #48] @ 0x30 80158b4: 6b18 ldr r0, [r3, #48] @ 0x30 80158b6: 687b ldr r3, [r7, #4] 80158b8: 009b lsls r3, r3, #2 80158ba: 461a mov r2, r3 80158bc: 21a5 movs r1, #165 @ 0xa5 80158be: f004 fd11 bl 801a2e4 * grows from high memory to low (as per the 80x86) or vice versa. * portSTACK_GROWTH is used to make the result positive or negative as required * by the port. */ #if ( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 80158c2: 6b3b ldr r3, [r7, #48] @ 0x30 80158c4: 6b1a ldr r2, [r3, #48] @ 0x30 80158c6: 687b ldr r3, [r7, #4] 80158c8: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 80158cc: 3b01 subs r3, #1 80158ce: 009b lsls r3, r3, #2 80158d0: 4413 add r3, r2 80158d2: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 80158d4: 69bb ldr r3, [r7, #24] 80158d6: f023 0307 bic.w r3, r3, #7 80158da: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 80158dc: 69bb ldr r3, [r7, #24] 80158de: f003 0307 and.w r3, r3, #7 80158e2: 2b00 cmp r3, #0 80158e4: d00b beq.n 80158fe __asm volatile 80158e6: f04f 0350 mov.w r3, #80 @ 0x50 80158ea: f383 8811 msr BASEPRI, r3 80158ee: f3bf 8f6f isb sy 80158f2: f3bf 8f4f dsb sy 80158f6: 617b str r3, [r7, #20] } 80158f8: bf00 nop 80158fa: bf00 nop 80158fc: e7fd b.n 80158fa pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 80158fe: 68bb ldr r3, [r7, #8] 8015900: 2b00 cmp r3, #0 8015902: d01e beq.n 8015942 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015904: 2300 movs r3, #0 8015906: 61fb str r3, [r7, #28] 8015908: e012 b.n 8015930 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 801590a: 68ba ldr r2, [r7, #8] 801590c: 69fb ldr r3, [r7, #28] 801590e: 4413 add r3, r2 8015910: 7819 ldrb r1, [r3, #0] 8015912: 6b3a ldr r2, [r7, #48] @ 0x30 8015914: 69fb ldr r3, [r7, #28] 8015916: 4413 add r3, r2 8015918: 3334 adds r3, #52 @ 0x34 801591a: 460a mov r2, r1 801591c: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than * configMAX_TASK_NAME_LEN characters just in case the memory after the * string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 801591e: 68ba ldr r2, [r7, #8] 8015920: 69fb ldr r3, [r7, #28] 8015922: 4413 add r3, r2 8015924: 781b ldrb r3, [r3, #0] 8015926: 2b00 cmp r3, #0 8015928: d006 beq.n 8015938 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 801592a: 69fb ldr r3, [r7, #28] 801592c: 3301 adds r3, #1 801592e: 61fb str r3, [r7, #28] 8015930: 69fb ldr r3, [r7, #28] 8015932: 2b0f cmp r3, #15 8015934: d9e9 bls.n 801590a 8015936: e000 b.n 801593a { break; 8015938: bf00 nop } } /* Ensure the name string is terminated in the case that the string length * was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 801593a: 6b3b ldr r3, [r7, #48] @ 0x30 801593c: 2200 movs r2, #0 801593e: f883 2043 strb.w r2, [r3, #67] @ 0x43 { mtCOVERAGE_TEST_MARKER(); } /* This is used as an array index so must ensure it's not too large. */ configASSERT( uxPriority < configMAX_PRIORITIES ); 8015942: 6abb ldr r3, [r7, #40] @ 0x28 8015944: 2b37 cmp r3, #55 @ 0x37 8015946: d90b bls.n 8015960 __asm volatile 8015948: f04f 0350 mov.w r3, #80 @ 0x50 801594c: f383 8811 msr BASEPRI, r3 8015950: f3bf 8f6f isb sy 8015954: f3bf 8f4f dsb sy 8015958: 613b str r3, [r7, #16] } 801595a: bf00 nop 801595c: bf00 nop 801595e: e7fd b.n 801595c if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8015960: 6abb ldr r3, [r7, #40] @ 0x28 8015962: 2b37 cmp r3, #55 @ 0x37 8015964: d901 bls.n 801596a { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8015966: 2337 movs r3, #55 @ 0x37 8015968: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 801596a: 6b3b ldr r3, [r7, #48] @ 0x30 801596c: 6aba ldr r2, [r7, #40] @ 0x28 801596e: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 8015970: 6b3b ldr r3, [r7, #48] @ 0x30 8015972: 6aba ldr r2, [r7, #40] @ 0x28 8015974: 64da str r2, [r3, #76] @ 0x4c } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8015976: 6b3b ldr r3, [r7, #48] @ 0x30 8015978: 3304 adds r3, #4 801597a: 4618 mov r0, r3 801597c: f7fe fd08 bl 8014390 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8015980: 6b3b ldr r3, [r7, #48] @ 0x30 8015982: 3318 adds r3, #24 8015984: 4618 mov r0, r3 8015986: f7fe fd03 bl 8014390 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get * back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 801598a: 6b3b ldr r3, [r7, #48] @ 0x30 801598c: 6b3a ldr r2, [r7, #48] @ 0x30 801598e: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015990: 6abb ldr r3, [r7, #40] @ 0x28 8015992: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015996: 6b3b ldr r3, [r7, #48] @ 0x30 8015998: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 801599a: 6b3b ldr r3, [r7, #48] @ 0x30 801599c: 6b3a ldr r2, [r7, #48] @ 0x30 801599e: 625a str r2, [r3, #36] @ 0x24 #endif #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) { /* Allocate and initialize memory for the task's TLS Block. */ configINIT_TLS_BLOCK( pxNewTCB->xTLSBlock, pxTopOfStack ); 80159a0: 6b3b ldr r3, [r7, #48] @ 0x30 80159a2: 3354 adds r3, #84 @ 0x54 80159a4: 224c movs r2, #76 @ 0x4c 80159a6: 2100 movs r1, #0 80159a8: 4618 mov r0, r3 80159aa: f004 fc9b bl 801a2e4 80159ae: 6b3b ldr r3, [r7, #48] @ 0x30 80159b0: 4a0c ldr r2, [pc, #48] @ (80159e4 ) 80159b2: 659a str r2, [r3, #88] @ 0x58 80159b4: 6b3b ldr r3, [r7, #48] @ 0x30 80159b6: 4a0c ldr r2, [pc, #48] @ (80159e8 ) 80159b8: 65da str r2, [r3, #92] @ 0x5c 80159ba: 6b3b ldr r3, [r7, #48] @ 0x30 80159bc: 4a0b ldr r2, [pc, #44] @ (80159ec ) 80159be: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 80159c0: 683a ldr r2, [r7, #0] 80159c2: 68f9 ldr r1, [r7, #12] 80159c4: 69b8 ldr r0, [r7, #24] 80159c6: f002 f857 bl 8017a78 80159ca: 4602 mov r2, r0 80159cc: 6b3b ldr r3, [r7, #48] @ 0x30 80159ce: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 80159d0: 6afb ldr r3, [r7, #44] @ 0x2c 80159d2: 2b00 cmp r3, #0 80159d4: d002 beq.n 80159dc { /* Pass the handle out in an anonymous way. The handle can be used to * change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 80159d6: 6afb ldr r3, [r7, #44] @ 0x2c 80159d8: 6b3a ldr r2, [r7, #48] @ 0x30 80159da: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 80159dc: bf00 nop 80159de: 3720 adds r7, #32 80159e0: 46bd mov sp, r7 80159e2: bd80 pop {r7, pc} 80159e4: 20013b9c .word 0x20013b9c 80159e8: 20013c04 .word 0x20013c04 80159ec: 20013c6c .word 0x20013c6c 080159f0 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) { 80159f0: b580 push {r7, lr} 80159f2: b084 sub sp, #16 80159f4: af00 add r7, sp, #0 80159f6: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being * updated. */ taskENTER_CRITICAL(); 80159f8: f002 f98a bl 8017d10 { uxCurrentNumberOfTasks++; 80159fc: 4b41 ldr r3, [pc, #260] @ (8015b04 ) 80159fe: 681b ldr r3, [r3, #0] 8015a00: 3301 adds r3, #1 8015a02: 4a40 ldr r2, [pc, #256] @ (8015b04 ) 8015a04: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8015a06: 4b40 ldr r3, [pc, #256] @ (8015b08 ) 8015a08: 681b ldr r3, [r3, #0] 8015a0a: 2b00 cmp r3, #0 8015a0c: d109 bne.n 8015a22 { /* There are no other tasks, or all the other tasks are in * the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 8015a0e: 4a3e ldr r2, [pc, #248] @ (8015b08 ) 8015a10: 687b ldr r3, [r7, #4] 8015a12: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8015a14: 4b3b ldr r3, [pc, #236] @ (8015b04 ) 8015a16: 681b ldr r3, [r3, #0] 8015a18: 2b01 cmp r3, #1 8015a1a: d110 bne.n 8015a3e { /* This is the first task to be created so do the preliminary * initialisation required. We will not recover if this call * fails, but we will report the failure. */ prvInitialiseTaskLists(); 8015a1c: f000 fda4 bl 8016568 8015a20: e00d b.n 8015a3e else { /* If the scheduler is not already running, make this task the * current task if it is the highest priority task to be created * so far. */ if( xSchedulerRunning == pdFALSE ) 8015a22: 4b3a ldr r3, [pc, #232] @ (8015b0c ) 8015a24: 681b ldr r3, [r3, #0] 8015a26: 2b00 cmp r3, #0 8015a28: d109 bne.n 8015a3e { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 8015a2a: 4b37 ldr r3, [pc, #220] @ (8015b08 ) 8015a2c: 681b ldr r3, [r3, #0] 8015a2e: 6ada ldr r2, [r3, #44] @ 0x2c 8015a30: 687b ldr r3, [r7, #4] 8015a32: 6adb ldr r3, [r3, #44] @ 0x2c 8015a34: 429a cmp r2, r3 8015a36: d802 bhi.n 8015a3e { pxCurrentTCB = pxNewTCB; 8015a38: 4a33 ldr r2, [pc, #204] @ (8015b08 ) 8015a3a: 687b ldr r3, [r7, #4] 8015a3c: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 8015a3e: 4b34 ldr r3, [pc, #208] @ (8015b10 ) 8015a40: 681b ldr r3, [r3, #0] 8015a42: 3301 adds r3, #1 8015a44: 4a32 ldr r2, [pc, #200] @ (8015b10 ) 8015a46: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 8015a48: 4b31 ldr r3, [pc, #196] @ (8015b10 ) 8015a4a: 681a ldr r2, [r3, #0] 8015a4c: 687b ldr r3, [r7, #4] 8015a4e: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 8015a50: 687b ldr r3, [r7, #4] 8015a52: 6ada ldr r2, [r3, #44] @ 0x2c 8015a54: 4b2f ldr r3, [pc, #188] @ (8015b14 ) 8015a56: 681b ldr r3, [r3, #0] 8015a58: 429a cmp r2, r3 8015a5a: d903 bls.n 8015a64 8015a5c: 687b ldr r3, [r7, #4] 8015a5e: 6adb ldr r3, [r3, #44] @ 0x2c 8015a60: 4a2c ldr r2, [pc, #176] @ (8015b14 ) 8015a62: 6013 str r3, [r2, #0] 8015a64: 687b ldr r3, [r7, #4] 8015a66: 6ada ldr r2, [r3, #44] @ 0x2c 8015a68: 492b ldr r1, [pc, #172] @ (8015b18 ) 8015a6a: 4613 mov r3, r2 8015a6c: 009b lsls r3, r3, #2 8015a6e: 4413 add r3, r2 8015a70: 009b lsls r3, r3, #2 8015a72: 440b add r3, r1 8015a74: 3304 adds r3, #4 8015a76: 681b ldr r3, [r3, #0] 8015a78: 60fb str r3, [r7, #12] 8015a7a: 687b ldr r3, [r7, #4] 8015a7c: 68fa ldr r2, [r7, #12] 8015a7e: 609a str r2, [r3, #8] 8015a80: 68fb ldr r3, [r7, #12] 8015a82: 689a ldr r2, [r3, #8] 8015a84: 687b ldr r3, [r7, #4] 8015a86: 60da str r2, [r3, #12] 8015a88: 68fb ldr r3, [r7, #12] 8015a8a: 689b ldr r3, [r3, #8] 8015a8c: 687a ldr r2, [r7, #4] 8015a8e: 3204 adds r2, #4 8015a90: 605a str r2, [r3, #4] 8015a92: 687b ldr r3, [r7, #4] 8015a94: 1d1a adds r2, r3, #4 8015a96: 68fb ldr r3, [r7, #12] 8015a98: 609a str r2, [r3, #8] 8015a9a: 687b ldr r3, [r7, #4] 8015a9c: 6ada ldr r2, [r3, #44] @ 0x2c 8015a9e: 4613 mov r3, r2 8015aa0: 009b lsls r3, r3, #2 8015aa2: 4413 add r3, r2 8015aa4: 009b lsls r3, r3, #2 8015aa6: 4a1c ldr r2, [pc, #112] @ (8015b18 ) 8015aa8: 441a add r2, r3 8015aaa: 687b ldr r3, [r7, #4] 8015aac: 615a str r2, [r3, #20] 8015aae: 687b ldr r3, [r7, #4] 8015ab0: 6ada ldr r2, [r3, #44] @ 0x2c 8015ab2: 4919 ldr r1, [pc, #100] @ (8015b18 ) 8015ab4: 4613 mov r3, r2 8015ab6: 009b lsls r3, r3, #2 8015ab8: 4413 add r3, r2 8015aba: 009b lsls r3, r3, #2 8015abc: 440b add r3, r1 8015abe: 681b ldr r3, [r3, #0] 8015ac0: 1c59 adds r1, r3, #1 8015ac2: 4815 ldr r0, [pc, #84] @ (8015b18 ) 8015ac4: 4613 mov r3, r2 8015ac6: 009b lsls r3, r3, #2 8015ac8: 4413 add r3, r2 8015aca: 009b lsls r3, r3, #2 8015acc: 4403 add r3, r0 8015ace: 6019 str r1, [r3, #0] portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 8015ad0: f002 f950 bl 8017d74 if( xSchedulerRunning != pdFALSE ) 8015ad4: 4b0d ldr r3, [pc, #52] @ (8015b0c ) 8015ad6: 681b ldr r3, [r3, #0] 8015ad8: 2b00 cmp r3, #0 8015ada: d00e beq.n 8015afa { /* If the created task is of a higher priority than the current task * then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8015adc: 4b0a ldr r3, [pc, #40] @ (8015b08 ) 8015ade: 681b ldr r3, [r3, #0] 8015ae0: 6ada ldr r2, [r3, #44] @ 0x2c 8015ae2: 687b ldr r3, [r7, #4] 8015ae4: 6adb ldr r3, [r3, #44] @ 0x2c 8015ae6: 429a cmp r2, r3 8015ae8: d207 bcs.n 8015afa { taskYIELD_IF_USING_PREEMPTION(); 8015aea: 4b0c ldr r3, [pc, #48] @ (8015b1c ) 8015aec: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015af0: 601a str r2, [r3, #0] 8015af2: f3bf 8f4f dsb sy 8015af6: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8015afa: bf00 nop 8015afc: 3710 adds r7, #16 8015afe: 46bd mov sp, r7 8015b00: bd80 pop {r7, pc} 8015b02: bf00 nop 8015b04: 2000263c .word 0x2000263c 8015b08: 20002168 .word 0x20002168 8015b0c: 20002648 .word 0x20002648 8015b10: 20002658 .word 0x20002658 8015b14: 20002644 .word 0x20002644 8015b18: 2000216c .word 0x2000216c 8015b1c: e000ed04 .word 0xe000ed04 08015b20 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 8015b20: b580 push {r7, lr} 8015b22: b08a sub sp, #40 @ 0x28 8015b24: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t * pxIdleTaskTCBBuffer = NULL; 8015b26: 2300 movs r3, #0 8015b28: 60bb str r3, [r7, #8] StackType_t * pxIdleTaskStackBuffer = NULL; 8015b2a: 2300 movs r3, #0 8015b2c: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the * address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 8015b2e: 463a mov r2, r7 8015b30: 1d39 adds r1, r7, #4 8015b32: f107 0308 add.w r3, r7, #8 8015b36: 4618 mov r0, r3 8015b38: f7fe fbd6 bl 80142e8 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 8015b3c: 6839 ldr r1, [r7, #0] 8015b3e: 687b ldr r3, [r7, #4] 8015b40: 68ba ldr r2, [r7, #8] 8015b42: 9202 str r2, [sp, #8] 8015b44: 9301 str r3, [sp, #4] 8015b46: 2300 movs r3, #0 8015b48: 9300 str r3, [sp, #0] 8015b4a: 2300 movs r3, #0 8015b4c: 460a mov r2, r1 8015b4e: 4925 ldr r1, [pc, #148] @ (8015be4 ) 8015b50: 4825 ldr r0, [pc, #148] @ (8015be8 ) 8015b52: f7ff fdf7 bl 8015744 8015b56: 4603 mov r3, r0 8015b58: 4a24 ldr r2, [pc, #144] @ (8015bec ) 8015b5a: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 8015b5c: 4b23 ldr r3, [pc, #140] @ (8015bec ) 8015b5e: 681b ldr r3, [r3, #0] 8015b60: 2b00 cmp r3, #0 8015b62: d002 beq.n 8015b6a { xReturn = pdPASS; 8015b64: 2301 movs r3, #1 8015b66: 617b str r3, [r7, #20] 8015b68: e001 b.n 8015b6e } else { xReturn = pdFAIL; 8015b6a: 2300 movs r3, #0 8015b6c: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 8015b6e: 697b ldr r3, [r7, #20] 8015b70: 2b01 cmp r3, #1 8015b72: d102 bne.n 8015b7a { xReturn = xTimerCreateTimerTask(); 8015b74: f001 fcb8 bl 80174e8 8015b78: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 8015b7a: 697b ldr r3, [r7, #20] 8015b7c: 2b01 cmp r3, #1 8015b7e: d11b bne.n 8015bb8 __asm volatile 8015b80: f04f 0350 mov.w r3, #80 @ 0x50 8015b84: f383 8811 msr BASEPRI, r3 8015b88: f3bf 8f6f isb sy 8015b8c: f3bf 8f4f dsb sy 8015b90: 613b str r3, [r7, #16] } 8015b92: bf00 nop #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) { /* Switch C-Runtime's TLS Block to point to the TLS * block specific to the task that will run first. */ configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); 8015b94: 4b16 ldr r3, [pc, #88] @ (8015bf0 ) 8015b96: 681b ldr r3, [r3, #0] 8015b98: 3354 adds r3, #84 @ 0x54 8015b9a: 4a16 ldr r2, [pc, #88] @ (8015bf4 ) 8015b9c: 6013 str r3, [r2, #0] } #endif xNextTaskUnblockTime = portMAX_DELAY; 8015b9e: 4b16 ldr r3, [pc, #88] @ (8015bf8 ) 8015ba0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015ba4: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8015ba6: 4b15 ldr r3, [pc, #84] @ (8015bfc ) 8015ba8: 2201 movs r2, #1 8015baa: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 8015bac: 4b14 ldr r3, [pc, #80] @ (8015c00 ) 8015bae: 2200 movs r2, #0 8015bb0: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the * portable interface. */ xPortStartScheduler(); 8015bb2: f001 ffef bl 8017b94 8015bb6: e00f b.n 8015bd8 else { /* This line will only be reached if the kernel could not be started, * because there was not enough FreeRTOS heap to create the idle task * or the timer task. */ configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8015bb8: 697b ldr r3, [r7, #20] 8015bba: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015bbe: d10b bne.n 8015bd8 __asm volatile 8015bc0: f04f 0350 mov.w r3, #80 @ 0x50 8015bc4: f383 8811 msr BASEPRI, r3 8015bc8: f3bf 8f6f isb sy 8015bcc: f3bf 8f4f dsb sy 8015bd0: 60fb str r3, [r7, #12] } 8015bd2: bf00 nop 8015bd4: bf00 nop 8015bd6: e7fd b.n 8015bd4 * meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority * from getting optimized out as it is no longer used by the kernel. */ ( void ) uxTopUsedPriority; 8015bd8: 4b0a ldr r3, [pc, #40] @ (8015c04 ) 8015bda: 681b ldr r3, [r3, #0] } 8015bdc: bf00 nop 8015bde: 3718 adds r7, #24 8015be0: 46bd mov sp, r7 8015be2: bd80 pop {r7, pc} 8015be4: 0801e2fc .word 0x0801e2fc 8015be8: 08016539 .word 0x08016539 8015bec: 20002660 .word 0x20002660 8015bf0: 20002168 .word 0x20002168 8015bf4: 2000011c .word 0x2000011c 8015bf8: 2000265c .word 0x2000265c 8015bfc: 20002648 .word 0x20002648 8015c00: 20002640 .word 0x20002640 8015c04: 0801e5ec .word 0x0801e5ec 08015c08 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 8015c08: b480 push {r7} 8015c0a: af00 add r7, sp, #0 * do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment * is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8015c0c: 4b04 ldr r3, [pc, #16] @ (8015c20 ) 8015c0e: 681b ldr r3, [r3, #0] 8015c10: 3301 adds r3, #1 8015c12: 4a03 ldr r2, [pc, #12] @ (8015c20 ) 8015c14: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place * the above increment elsewhere. */ portMEMORY_BARRIER(); } 8015c16: bf00 nop 8015c18: 46bd mov sp, r7 8015c1a: f85d 7b04 ldr.w r7, [sp], #4 8015c1e: 4770 bx lr 8015c20: 20002664 .word 0x20002664 08015c24 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 8015c24: b580 push {r7, lr} 8015c26: b088 sub sp, #32 8015c28: af00 add r7, sp, #0 TCB_t * pxTCB = NULL; 8015c2a: 2300 movs r3, #0 8015c2c: 61fb str r3, [r7, #28] BaseType_t xAlreadyYielded = pdFALSE; 8015c2e: 2300 movs r3, #0 8015c30: 61bb str r3, [r7, #24] /* If uxSchedulerSuspended is zero then this function does not match a * previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U ); 8015c32: 4b72 ldr r3, [pc, #456] @ (8015dfc ) 8015c34: 681b ldr r3, [r3, #0] 8015c36: 2b00 cmp r3, #0 8015c38: d10b bne.n 8015c52 __asm volatile 8015c3a: f04f 0350 mov.w r3, #80 @ 0x50 8015c3e: f383 8811 msr BASEPRI, r3 8015c42: f3bf 8f6f isb sy 8015c46: f3bf 8f4f dsb sy 8015c4a: 607b str r3, [r7, #4] } 8015c4c: bf00 nop 8015c4e: bf00 nop 8015c50: e7fd b.n 8015c4e /* It is possible that an ISR caused a task to be removed from an event * list while the scheduler was suspended. If this was the case then the * removed task will have been added to the xPendingReadyList. Once the * scheduler has been resumed it is safe to move all the pending ready * tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 8015c52: f002 f85d bl 8017d10 { --uxSchedulerSuspended; 8015c56: 4b69 ldr r3, [pc, #420] @ (8015dfc ) 8015c58: 681b ldr r3, [r3, #0] 8015c5a: 3b01 subs r3, #1 8015c5c: 4a67 ldr r2, [pc, #412] @ (8015dfc ) 8015c5e: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 8015c60: 4b66 ldr r3, [pc, #408] @ (8015dfc ) 8015c62: 681b ldr r3, [r3, #0] 8015c64: 2b00 cmp r3, #0 8015c66: f040 80c1 bne.w 8015dec { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 8015c6a: 4b65 ldr r3, [pc, #404] @ (8015e00 ) 8015c6c: 681b ldr r3, [r3, #0] 8015c6e: 2b00 cmp r3, #0 8015c70: f000 80bc beq.w 8015dec { /* Move any readied tasks from the pending list into the * appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8015c74: e08b b.n 8015d8e { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015c76: 4b63 ldr r3, [pc, #396] @ (8015e04 ) 8015c78: 68db ldr r3, [r3, #12] 8015c7a: 68db ldr r3, [r3, #12] 8015c7c: 61fb str r3, [r7, #28] listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); 8015c7e: 69fb ldr r3, [r7, #28] 8015c80: 6a9b ldr r3, [r3, #40] @ 0x28 8015c82: 613b str r3, [r7, #16] 8015c84: 69fb ldr r3, [r7, #28] 8015c86: 69db ldr r3, [r3, #28] 8015c88: 69fa ldr r2, [r7, #28] 8015c8a: 6a12 ldr r2, [r2, #32] 8015c8c: 609a str r2, [r3, #8] 8015c8e: 69fb ldr r3, [r7, #28] 8015c90: 6a1b ldr r3, [r3, #32] 8015c92: 69fa ldr r2, [r7, #28] 8015c94: 69d2 ldr r2, [r2, #28] 8015c96: 605a str r2, [r3, #4] 8015c98: 693b ldr r3, [r7, #16] 8015c9a: 685a ldr r2, [r3, #4] 8015c9c: 69fb ldr r3, [r7, #28] 8015c9e: 3318 adds r3, #24 8015ca0: 429a cmp r2, r3 8015ca2: d103 bne.n 8015cac 8015ca4: 69fb ldr r3, [r7, #28] 8015ca6: 6a1a ldr r2, [r3, #32] 8015ca8: 693b ldr r3, [r7, #16] 8015caa: 605a str r2, [r3, #4] 8015cac: 69fb ldr r3, [r7, #28] 8015cae: 2200 movs r2, #0 8015cb0: 629a str r2, [r3, #40] @ 0x28 8015cb2: 693b ldr r3, [r7, #16] 8015cb4: 681b ldr r3, [r3, #0] 8015cb6: 1e5a subs r2, r3, #1 8015cb8: 693b ldr r3, [r7, #16] 8015cba: 601a str r2, [r3, #0] portMEMORY_BARRIER(); listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 8015cbc: 69fb ldr r3, [r7, #28] 8015cbe: 695b ldr r3, [r3, #20] 8015cc0: 60fb str r3, [r7, #12] 8015cc2: 69fb ldr r3, [r7, #28] 8015cc4: 689b ldr r3, [r3, #8] 8015cc6: 69fa ldr r2, [r7, #28] 8015cc8: 68d2 ldr r2, [r2, #12] 8015cca: 609a str r2, [r3, #8] 8015ccc: 69fb ldr r3, [r7, #28] 8015cce: 68db ldr r3, [r3, #12] 8015cd0: 69fa ldr r2, [r7, #28] 8015cd2: 6892 ldr r2, [r2, #8] 8015cd4: 605a str r2, [r3, #4] 8015cd6: 68fb ldr r3, [r7, #12] 8015cd8: 685a ldr r2, [r3, #4] 8015cda: 69fb ldr r3, [r7, #28] 8015cdc: 3304 adds r3, #4 8015cde: 429a cmp r2, r3 8015ce0: d103 bne.n 8015cea 8015ce2: 69fb ldr r3, [r7, #28] 8015ce4: 68da ldr r2, [r3, #12] 8015ce6: 68fb ldr r3, [r7, #12] 8015ce8: 605a str r2, [r3, #4] 8015cea: 69fb ldr r3, [r7, #28] 8015cec: 2200 movs r2, #0 8015cee: 615a str r2, [r3, #20] 8015cf0: 68fb ldr r3, [r7, #12] 8015cf2: 681b ldr r3, [r3, #0] 8015cf4: 1e5a subs r2, r3, #1 8015cf6: 68fb ldr r3, [r7, #12] 8015cf8: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxTCB ); 8015cfa: 69fb ldr r3, [r7, #28] 8015cfc: 6ada ldr r2, [r3, #44] @ 0x2c 8015cfe: 4b42 ldr r3, [pc, #264] @ (8015e08 ) 8015d00: 681b ldr r3, [r3, #0] 8015d02: 429a cmp r2, r3 8015d04: d903 bls.n 8015d0e 8015d06: 69fb ldr r3, [r7, #28] 8015d08: 6adb ldr r3, [r3, #44] @ 0x2c 8015d0a: 4a3f ldr r2, [pc, #252] @ (8015e08 ) 8015d0c: 6013 str r3, [r2, #0] 8015d0e: 69fb ldr r3, [r7, #28] 8015d10: 6ada ldr r2, [r3, #44] @ 0x2c 8015d12: 493e ldr r1, [pc, #248] @ (8015e0c ) 8015d14: 4613 mov r3, r2 8015d16: 009b lsls r3, r3, #2 8015d18: 4413 add r3, r2 8015d1a: 009b lsls r3, r3, #2 8015d1c: 440b add r3, r1 8015d1e: 3304 adds r3, #4 8015d20: 681b ldr r3, [r3, #0] 8015d22: 60bb str r3, [r7, #8] 8015d24: 69fb ldr r3, [r7, #28] 8015d26: 68ba ldr r2, [r7, #8] 8015d28: 609a str r2, [r3, #8] 8015d2a: 68bb ldr r3, [r7, #8] 8015d2c: 689a ldr r2, [r3, #8] 8015d2e: 69fb ldr r3, [r7, #28] 8015d30: 60da str r2, [r3, #12] 8015d32: 68bb ldr r3, [r7, #8] 8015d34: 689b ldr r3, [r3, #8] 8015d36: 69fa ldr r2, [r7, #28] 8015d38: 3204 adds r2, #4 8015d3a: 605a str r2, [r3, #4] 8015d3c: 69fb ldr r3, [r7, #28] 8015d3e: 1d1a adds r2, r3, #4 8015d40: 68bb ldr r3, [r7, #8] 8015d42: 609a str r2, [r3, #8] 8015d44: 69fb ldr r3, [r7, #28] 8015d46: 6ada ldr r2, [r3, #44] @ 0x2c 8015d48: 4613 mov r3, r2 8015d4a: 009b lsls r3, r3, #2 8015d4c: 4413 add r3, r2 8015d4e: 009b lsls r3, r3, #2 8015d50: 4a2e ldr r2, [pc, #184] @ (8015e0c ) 8015d52: 441a add r2, r3 8015d54: 69fb ldr r3, [r7, #28] 8015d56: 615a str r2, [r3, #20] 8015d58: 69fb ldr r3, [r7, #28] 8015d5a: 6ada ldr r2, [r3, #44] @ 0x2c 8015d5c: 492b ldr r1, [pc, #172] @ (8015e0c ) 8015d5e: 4613 mov r3, r2 8015d60: 009b lsls r3, r3, #2 8015d62: 4413 add r3, r2 8015d64: 009b lsls r3, r3, #2 8015d66: 440b add r3, r1 8015d68: 681b ldr r3, [r3, #0] 8015d6a: 1c59 adds r1, r3, #1 8015d6c: 4827 ldr r0, [pc, #156] @ (8015e0c ) 8015d6e: 4613 mov r3, r2 8015d70: 009b lsls r3, r3, #2 8015d72: 4413 add r3, r2 8015d74: 009b lsls r3, r3, #2 8015d76: 4403 add r3, r0 8015d78: 6019 str r1, [r3, #0] /* If the moved task has a priority higher than the current * task then a yield must be performed. */ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8015d7a: 69fb ldr r3, [r7, #28] 8015d7c: 6ada ldr r2, [r3, #44] @ 0x2c 8015d7e: 4b24 ldr r3, [pc, #144] @ (8015e10 ) 8015d80: 681b ldr r3, [r3, #0] 8015d82: 6adb ldr r3, [r3, #44] @ 0x2c 8015d84: 429a cmp r2, r3 8015d86: d902 bls.n 8015d8e { xYieldPending = pdTRUE; 8015d88: 4b22 ldr r3, [pc, #136] @ (8015e14 ) 8015d8a: 2201 movs r2, #1 8015d8c: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8015d8e: 4b1d ldr r3, [pc, #116] @ (8015e04 ) 8015d90: 681b ldr r3, [r3, #0] 8015d92: 2b00 cmp r3, #0 8015d94: f47f af6f bne.w 8015c76 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 8015d98: 69fb ldr r3, [r7, #28] 8015d9a: 2b00 cmp r3, #0 8015d9c: d001 beq.n 8015da2 * which may have prevented the next unblock time from being * re-calculated, in which case re-calculate it now. Mainly * important for low power tickless implementations, where * this can prevent an unnecessary exit from low power * state. */ prvResetNextTaskUnblockTime(); 8015d9e: f000 fc89 bl 80166b4 /* If any ticks occurred while the scheduler was suspended then * they should be processed now. This ensures the tick count does * not slip, and that any delayed tasks are resumed at the correct * time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8015da2: 4b1d ldr r3, [pc, #116] @ (8015e18 ) 8015da4: 681b ldr r3, [r3, #0] 8015da6: 617b str r3, [r7, #20] if( xPendedCounts > ( TickType_t ) 0U ) 8015da8: 697b ldr r3, [r7, #20] 8015daa: 2b00 cmp r3, #0 8015dac: d010 beq.n 8015dd0 { do { if( xTaskIncrementTick() != pdFALSE ) 8015dae: f000 f853 bl 8015e58 8015db2: 4603 mov r3, r0 8015db4: 2b00 cmp r3, #0 8015db6: d002 beq.n 8015dbe { xYieldPending = pdTRUE; 8015db8: 4b16 ldr r3, [pc, #88] @ (8015e14 ) 8015dba: 2201 movs r2, #1 8015dbc: 601a str r2, [r3, #0] else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8015dbe: 697b ldr r3, [r7, #20] 8015dc0: 3b01 subs r3, #1 8015dc2: 617b str r3, [r7, #20] } while( xPendedCounts > ( TickType_t ) 0U ); 8015dc4: 697b ldr r3, [r7, #20] 8015dc6: 2b00 cmp r3, #0 8015dc8: d1f1 bne.n 8015dae xPendedTicks = 0; 8015dca: 4b13 ldr r3, [pc, #76] @ (8015e18 ) 8015dcc: 2200 movs r2, #0 8015dce: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8015dd0: 4b10 ldr r3, [pc, #64] @ (8015e14 ) 8015dd2: 681b ldr r3, [r3, #0] 8015dd4: 2b00 cmp r3, #0 8015dd6: d009 beq.n 8015dec { #if ( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 8015dd8: 2301 movs r3, #1 8015dda: 61bb str r3, [r7, #24] } #endif taskYIELD_IF_USING_PREEMPTION(); 8015ddc: 4b0f ldr r3, [pc, #60] @ (8015e1c ) 8015dde: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015de2: 601a str r2, [r3, #0] 8015de4: f3bf 8f4f dsb sy 8015de8: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8015dec: f001 ffc2 bl 8017d74 return xAlreadyYielded; 8015df0: 69bb ldr r3, [r7, #24] } 8015df2: 4618 mov r0, r3 8015df4: 3720 adds r7, #32 8015df6: 46bd mov sp, r7 8015df8: bd80 pop {r7, pc} 8015dfa: bf00 nop 8015dfc: 20002664 .word 0x20002664 8015e00: 2000263c .word 0x2000263c 8015e04: 200025fc .word 0x200025fc 8015e08: 20002644 .word 0x20002644 8015e0c: 2000216c .word 0x2000216c 8015e10: 20002168 .word 0x20002168 8015e14: 20002650 .word 0x20002650 8015e18: 2000264c .word 0x2000264c 8015e1c: e000ed04 .word 0xe000ed04 08015e20 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 8015e20: b480 push {r7} 8015e22: b083 sub sp, #12 8015e24: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 8015e26: 4b05 ldr r3, [pc, #20] @ (8015e3c ) 8015e28: 681b ldr r3, [r3, #0] 8015e2a: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 8015e2c: 687b ldr r3, [r7, #4] } 8015e2e: 4618 mov r0, r3 8015e30: 370c adds r7, #12 8015e32: 46bd mov sp, r7 8015e34: f85d 7b04 ldr.w r7, [sp], #4 8015e38: 4770 bx lr 8015e3a: bf00 nop 8015e3c: 20002640 .word 0x20002640 08015e40 : return xReturn; } /*-----------------------------------------------------------*/ UBaseType_t uxTaskGetNumberOfTasks( void ) { 8015e40: b480 push {r7} 8015e42: af00 add r7, sp, #0 /* A critical section is not required because the variables are of type * BaseType_t. */ return uxCurrentNumberOfTasks; 8015e44: 4b03 ldr r3, [pc, #12] @ (8015e54 ) 8015e46: 681b ldr r3, [r3, #0] } 8015e48: 4618 mov r0, r3 8015e4a: 46bd mov sp, r7 8015e4c: f85d 7b04 ldr.w r7, [sp], #4 8015e50: 4770 bx lr 8015e52: bf00 nop 8015e54: 2000263c .word 0x2000263c 08015e58 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 8015e58: b580 push {r7, lr} 8015e5a: b08a sub sp, #40 @ 0x28 8015e5c: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 8015e5e: 2300 movs r3, #0 8015e60: 627b str r3, [r7, #36] @ 0x24 /* Called by the portable layer each time a tick interrupt occurs. * Increments the tick then checks to see if the new tick value will cause any * tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 8015e62: 4b7e ldr r3, [pc, #504] @ (801605c ) 8015e64: 681b ldr r3, [r3, #0] 8015e66: 2b00 cmp r3, #0 8015e68: f040 80ee bne.w 8016048 { /* Minor optimisation. The tick count cannot change in this * block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 8015e6c: 4b7c ldr r3, [pc, #496] @ (8016060 ) 8015e6e: 681b ldr r3, [r3, #0] 8015e70: 3301 adds r3, #1 8015e72: 623b str r3, [r7, #32] /* Increment the RTOS tick, switching the delayed and overflowed * delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8015e74: 4a7a ldr r2, [pc, #488] @ (8016060 ) 8015e76: 6a3b ldr r3, [r7, #32] 8015e78: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 8015e7a: 6a3b ldr r3, [r7, #32] 8015e7c: 2b00 cmp r3, #0 8015e7e: d121 bne.n 8015ec4 { taskSWITCH_DELAYED_LISTS(); 8015e80: 4b78 ldr r3, [pc, #480] @ (8016064 ) 8015e82: 681b ldr r3, [r3, #0] 8015e84: 681b ldr r3, [r3, #0] 8015e86: 2b00 cmp r3, #0 8015e88: d00b beq.n 8015ea2 __asm volatile 8015e8a: f04f 0350 mov.w r3, #80 @ 0x50 8015e8e: f383 8811 msr BASEPRI, r3 8015e92: f3bf 8f6f isb sy 8015e96: f3bf 8f4f dsb sy 8015e9a: 607b str r3, [r7, #4] } 8015e9c: bf00 nop 8015e9e: bf00 nop 8015ea0: e7fd b.n 8015e9e 8015ea2: 4b70 ldr r3, [pc, #448] @ (8016064 ) 8015ea4: 681b ldr r3, [r3, #0] 8015ea6: 61fb str r3, [r7, #28] 8015ea8: 4b6f ldr r3, [pc, #444] @ (8016068 ) 8015eaa: 681b ldr r3, [r3, #0] 8015eac: 4a6d ldr r2, [pc, #436] @ (8016064 ) 8015eae: 6013 str r3, [r2, #0] 8015eb0: 4a6d ldr r2, [pc, #436] @ (8016068 ) 8015eb2: 69fb ldr r3, [r7, #28] 8015eb4: 6013 str r3, [r2, #0] 8015eb6: 4b6d ldr r3, [pc, #436] @ (801606c ) 8015eb8: 681b ldr r3, [r3, #0] 8015eba: 3301 adds r3, #1 8015ebc: 4a6b ldr r2, [pc, #428] @ (801606c ) 8015ebe: 6013 str r3, [r2, #0] 8015ec0: f000 fbf8 bl 80166b4 /* See if this tick has made a timeout expire. Tasks are stored in * the queue in the order of their wake time - meaning once one task * has been found whose block time has not expired there is no need to * look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8015ec4: 4b6a ldr r3, [pc, #424] @ (8016070 ) 8015ec6: 681b ldr r3, [r3, #0] 8015ec8: 6a3a ldr r2, [r7, #32] 8015eca: 429a cmp r2, r3 8015ecc: f0c0 80a7 bcc.w 801601e { for( ; ; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8015ed0: 4b64 ldr r3, [pc, #400] @ (8016064 ) 8015ed2: 681b ldr r3, [r3, #0] 8015ed4: 681b ldr r3, [r3, #0] 8015ed6: 2b00 cmp r3, #0 8015ed8: d104 bne.n 8015ee4 /* The delayed list is empty. Set xNextTaskUnblockTime * to the maximum possible value so it is extremely * unlikely that the * if( xTickCount >= xNextTaskUnblockTime ) test will pass * next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015eda: 4b65 ldr r3, [pc, #404] @ (8016070 ) 8015edc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015ee0: 601a str r2, [r3, #0] break; 8015ee2: e09c b.n 801601e { /* The delayed list is not empty, get the value of the * item at the head of the delayed list. This is the time * at which the task at the head of the delayed list must * be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015ee4: 4b5f ldr r3, [pc, #380] @ (8016064 ) 8015ee6: 681b ldr r3, [r3, #0] 8015ee8: 68db ldr r3, [r3, #12] 8015eea: 68db ldr r3, [r3, #12] 8015eec: 61bb str r3, [r7, #24] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8015eee: 69bb ldr r3, [r7, #24] 8015ef0: 685b ldr r3, [r3, #4] 8015ef2: 617b str r3, [r7, #20] if( xConstTickCount < xItemValue ) 8015ef4: 6a3a ldr r2, [r7, #32] 8015ef6: 697b ldr r3, [r7, #20] 8015ef8: 429a cmp r2, r3 8015efa: d203 bcs.n 8015f04 /* It is not time to unblock this item yet, but the * item value is the time at which the task at the head * of the blocked list must be removed from the Blocked * state - so record the item value in * xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 8015efc: 4a5c ldr r2, [pc, #368] @ (8016070 ) 8015efe: 697b ldr r3, [r7, #20] 8015f00: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deemed easier to understand with multiple breaks. */ 8015f02: e08c b.n 801601e { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 8015f04: 69bb ldr r3, [r7, #24] 8015f06: 695b ldr r3, [r3, #20] 8015f08: 613b str r3, [r7, #16] 8015f0a: 69bb ldr r3, [r7, #24] 8015f0c: 689b ldr r3, [r3, #8] 8015f0e: 69ba ldr r2, [r7, #24] 8015f10: 68d2 ldr r2, [r2, #12] 8015f12: 609a str r2, [r3, #8] 8015f14: 69bb ldr r3, [r7, #24] 8015f16: 68db ldr r3, [r3, #12] 8015f18: 69ba ldr r2, [r7, #24] 8015f1a: 6892 ldr r2, [r2, #8] 8015f1c: 605a str r2, [r3, #4] 8015f1e: 693b ldr r3, [r7, #16] 8015f20: 685a ldr r2, [r3, #4] 8015f22: 69bb ldr r3, [r7, #24] 8015f24: 3304 adds r3, #4 8015f26: 429a cmp r2, r3 8015f28: d103 bne.n 8015f32 8015f2a: 69bb ldr r3, [r7, #24] 8015f2c: 68da ldr r2, [r3, #12] 8015f2e: 693b ldr r3, [r7, #16] 8015f30: 605a str r2, [r3, #4] 8015f32: 69bb ldr r3, [r7, #24] 8015f34: 2200 movs r2, #0 8015f36: 615a str r2, [r3, #20] 8015f38: 693b ldr r3, [r7, #16] 8015f3a: 681b ldr r3, [r3, #0] 8015f3c: 1e5a subs r2, r3, #1 8015f3e: 693b ldr r3, [r7, #16] 8015f40: 601a str r2, [r3, #0] /* Is the task waiting on an event also? If so remove * it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 8015f42: 69bb ldr r3, [r7, #24] 8015f44: 6a9b ldr r3, [r3, #40] @ 0x28 8015f46: 2b00 cmp r3, #0 8015f48: d01e beq.n 8015f88 { listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); 8015f4a: 69bb ldr r3, [r7, #24] 8015f4c: 6a9b ldr r3, [r3, #40] @ 0x28 8015f4e: 60fb str r3, [r7, #12] 8015f50: 69bb ldr r3, [r7, #24] 8015f52: 69db ldr r3, [r3, #28] 8015f54: 69ba ldr r2, [r7, #24] 8015f56: 6a12 ldr r2, [r2, #32] 8015f58: 609a str r2, [r3, #8] 8015f5a: 69bb ldr r3, [r7, #24] 8015f5c: 6a1b ldr r3, [r3, #32] 8015f5e: 69ba ldr r2, [r7, #24] 8015f60: 69d2 ldr r2, [r2, #28] 8015f62: 605a str r2, [r3, #4] 8015f64: 68fb ldr r3, [r7, #12] 8015f66: 685a ldr r2, [r3, #4] 8015f68: 69bb ldr r3, [r7, #24] 8015f6a: 3318 adds r3, #24 8015f6c: 429a cmp r2, r3 8015f6e: d103 bne.n 8015f78 8015f70: 69bb ldr r3, [r7, #24] 8015f72: 6a1a ldr r2, [r3, #32] 8015f74: 68fb ldr r3, [r7, #12] 8015f76: 605a str r2, [r3, #4] 8015f78: 69bb ldr r3, [r7, #24] 8015f7a: 2200 movs r2, #0 8015f7c: 629a str r2, [r3, #40] @ 0x28 8015f7e: 68fb ldr r3, [r7, #12] 8015f80: 681b ldr r3, [r3, #0] 8015f82: 1e5a subs r2, r3, #1 8015f84: 68fb ldr r3, [r7, #12] 8015f86: 601a str r2, [r3, #0] mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready * list. */ prvAddTaskToReadyList( pxTCB ); 8015f88: 69bb ldr r3, [r7, #24] 8015f8a: 6ada ldr r2, [r3, #44] @ 0x2c 8015f8c: 4b39 ldr r3, [pc, #228] @ (8016074 ) 8015f8e: 681b ldr r3, [r3, #0] 8015f90: 429a cmp r2, r3 8015f92: d903 bls.n 8015f9c 8015f94: 69bb ldr r3, [r7, #24] 8015f96: 6adb ldr r3, [r3, #44] @ 0x2c 8015f98: 4a36 ldr r2, [pc, #216] @ (8016074 ) 8015f9a: 6013 str r3, [r2, #0] 8015f9c: 69bb ldr r3, [r7, #24] 8015f9e: 6ada ldr r2, [r3, #44] @ 0x2c 8015fa0: 4935 ldr r1, [pc, #212] @ (8016078 ) 8015fa2: 4613 mov r3, r2 8015fa4: 009b lsls r3, r3, #2 8015fa6: 4413 add r3, r2 8015fa8: 009b lsls r3, r3, #2 8015faa: 440b add r3, r1 8015fac: 3304 adds r3, #4 8015fae: 681b ldr r3, [r3, #0] 8015fb0: 60bb str r3, [r7, #8] 8015fb2: 69bb ldr r3, [r7, #24] 8015fb4: 68ba ldr r2, [r7, #8] 8015fb6: 609a str r2, [r3, #8] 8015fb8: 68bb ldr r3, [r7, #8] 8015fba: 689a ldr r2, [r3, #8] 8015fbc: 69bb ldr r3, [r7, #24] 8015fbe: 60da str r2, [r3, #12] 8015fc0: 68bb ldr r3, [r7, #8] 8015fc2: 689b ldr r3, [r3, #8] 8015fc4: 69ba ldr r2, [r7, #24] 8015fc6: 3204 adds r2, #4 8015fc8: 605a str r2, [r3, #4] 8015fca: 69bb ldr r3, [r7, #24] 8015fcc: 1d1a adds r2, r3, #4 8015fce: 68bb ldr r3, [r7, #8] 8015fd0: 609a str r2, [r3, #8] 8015fd2: 69bb ldr r3, [r7, #24] 8015fd4: 6ada ldr r2, [r3, #44] @ 0x2c 8015fd6: 4613 mov r3, r2 8015fd8: 009b lsls r3, r3, #2 8015fda: 4413 add r3, r2 8015fdc: 009b lsls r3, r3, #2 8015fde: 4a26 ldr r2, [pc, #152] @ (8016078 ) 8015fe0: 441a add r2, r3 8015fe2: 69bb ldr r3, [r7, #24] 8015fe4: 615a str r2, [r3, #20] 8015fe6: 69bb ldr r3, [r7, #24] 8015fe8: 6ada ldr r2, [r3, #44] @ 0x2c 8015fea: 4923 ldr r1, [pc, #140] @ (8016078 ) 8015fec: 4613 mov r3, r2 8015fee: 009b lsls r3, r3, #2 8015ff0: 4413 add r3, r2 8015ff2: 009b lsls r3, r3, #2 8015ff4: 440b add r3, r1 8015ff6: 681b ldr r3, [r3, #0] 8015ff8: 1c59 adds r1, r3, #1 8015ffa: 481f ldr r0, [pc, #124] @ (8016078 ) 8015ffc: 4613 mov r3, r2 8015ffe: 009b lsls r3, r3, #2 8016000: 4413 add r3, r2 8016002: 009b lsls r3, r3, #2 8016004: 4403 add r3, r0 8016006: 6019 str r1, [r3, #0] * task. * The case of equal priority tasks sharing * processing time (which happens when both * preemption and time slicing are on) is * handled below.*/ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016008: 69bb ldr r3, [r7, #24] 801600a: 6ada ldr r2, [r3, #44] @ 0x2c 801600c: 4b1b ldr r3, [pc, #108] @ (801607c ) 801600e: 681b ldr r3, [r3, #0] 8016010: 6adb ldr r3, [r3, #44] @ 0x2c 8016012: 429a cmp r2, r3 8016014: f67f af5c bls.w 8015ed0 { xSwitchRequired = pdTRUE; 8016018: 2301 movs r3, #1 801601a: 627b str r3, [r7, #36] @ 0x24 if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 801601c: e758 b.n 8015ed0 /* Tasks of equal priority to the currently running task will share * processing time (time slice) if preemption is on, and the application * writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 801601e: 4b17 ldr r3, [pc, #92] @ (801607c ) 8016020: 681b ldr r3, [r3, #0] 8016022: 6ada ldr r2, [r3, #44] @ 0x2c 8016024: 4914 ldr r1, [pc, #80] @ (8016078 ) 8016026: 4613 mov r3, r2 8016028: 009b lsls r3, r3, #2 801602a: 4413 add r3, r2 801602c: 009b lsls r3, r3, #2 801602e: 440b add r3, r1 8016030: 681b ldr r3, [r3, #0] 8016032: 2b01 cmp r3, #1 8016034: d901 bls.n 801603a { xSwitchRequired = pdTRUE; 8016036: 2301 movs r3, #1 8016038: 627b str r3, [r7, #36] @ 0x24 } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 801603a: 4b11 ldr r3, [pc, #68] @ (8016080 ) 801603c: 681b ldr r3, [r3, #0] 801603e: 2b00 cmp r3, #0 8016040: d007 beq.n 8016052 { xSwitchRequired = pdTRUE; 8016042: 2301 movs r3, #1 8016044: 627b str r3, [r7, #36] @ 0x24 8016046: e004 b.n 8016052 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 8016048: 4b0e ldr r3, [pc, #56] @ (8016084 ) 801604a: 681b ldr r3, [r3, #0] 801604c: 3301 adds r3, #1 801604e: 4a0d ldr r2, [pc, #52] @ (8016084 ) 8016050: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8016052: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016054: 4618 mov r0, r3 8016056: 3728 adds r7, #40 @ 0x28 8016058: 46bd mov sp, r7 801605a: bd80 pop {r7, pc} 801605c: 20002664 .word 0x20002664 8016060: 20002640 .word 0x20002640 8016064: 200025f4 .word 0x200025f4 8016068: 200025f8 .word 0x200025f8 801606c: 20002654 .word 0x20002654 8016070: 2000265c .word 0x2000265c 8016074: 20002644 .word 0x20002644 8016078: 2000216c .word 0x2000216c 801607c: 20002168 .word 0x20002168 8016080: 20002650 .word 0x20002650 8016084: 2000264c .word 0x2000264c 08016088 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 8016088: b580 push {r7, lr} 801608a: b086 sub sp, #24 801608c: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) 0U ) 801608e: 4b3d ldr r3, [pc, #244] @ (8016184 ) 8016090: 681b ldr r3, [r3, #0] 8016092: 2b00 cmp r3, #0 8016094: d003 beq.n 801609e { /* The scheduler is currently suspended - do not allow a context * switch. */ xYieldPending = pdTRUE; 8016096: 4b3c ldr r3, [pc, #240] @ (8016188 ) 8016098: 2201 movs r2, #1 801609a: 601a str r2, [r3, #0] * Block specific to this task. */ configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); } #endif } } 801609c: e06d b.n 801617a xYieldPending = pdFALSE; 801609e: 4b3a ldr r3, [pc, #232] @ (8016188 ) 80160a0: 2200 movs r2, #0 80160a2: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 80160a4: 4b39 ldr r3, [pc, #228] @ (801618c ) 80160a6: 681b ldr r3, [r3, #0] 80160a8: 6b1b ldr r3, [r3, #48] @ 0x30 80160aa: 613b str r3, [r7, #16] 80160ac: f04f 33a5 mov.w r3, #2779096485 @ 0xa5a5a5a5 80160b0: 60fb str r3, [r7, #12] 80160b2: 693b ldr r3, [r7, #16] 80160b4: 681b ldr r3, [r3, #0] 80160b6: 68fa ldr r2, [r7, #12] 80160b8: 429a cmp r2, r3 80160ba: d111 bne.n 80160e0 80160bc: 693b ldr r3, [r7, #16] 80160be: 3304 adds r3, #4 80160c0: 681b ldr r3, [r3, #0] 80160c2: 68fa ldr r2, [r7, #12] 80160c4: 429a cmp r2, r3 80160c6: d10b bne.n 80160e0 80160c8: 693b ldr r3, [r7, #16] 80160ca: 3308 adds r3, #8 80160cc: 681b ldr r3, [r3, #0] 80160ce: 68fa ldr r2, [r7, #12] 80160d0: 429a cmp r2, r3 80160d2: d105 bne.n 80160e0 80160d4: 693b ldr r3, [r7, #16] 80160d6: 330c adds r3, #12 80160d8: 681b ldr r3, [r3, #0] 80160da: 68fa ldr r2, [r7, #12] 80160dc: 429a cmp r2, r3 80160de: d008 beq.n 80160f2 80160e0: 4b2a ldr r3, [pc, #168] @ (801618c ) 80160e2: 681a ldr r2, [r3, #0] 80160e4: 4b29 ldr r3, [pc, #164] @ (801618c ) 80160e6: 681b ldr r3, [r3, #0] 80160e8: 3334 adds r3, #52 @ 0x34 80160ea: 4619 mov r1, r3 80160ec: 4610 mov r0, r2 80160ee: f7ec faeb bl 80026c8 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80160f2: 4b27 ldr r3, [pc, #156] @ (8016190 ) 80160f4: 681b ldr r3, [r3, #0] 80160f6: 617b str r3, [r7, #20] 80160f8: e011 b.n 801611e 80160fa: 697b ldr r3, [r7, #20] 80160fc: 2b00 cmp r3, #0 80160fe: d10b bne.n 8016118 __asm volatile 8016100: f04f 0350 mov.w r3, #80 @ 0x50 8016104: f383 8811 msr BASEPRI, r3 8016108: f3bf 8f6f isb sy 801610c: f3bf 8f4f dsb sy 8016110: 607b str r3, [r7, #4] } 8016112: bf00 nop 8016114: bf00 nop 8016116: e7fd b.n 8016114 8016118: 697b ldr r3, [r7, #20] 801611a: 3b01 subs r3, #1 801611c: 617b str r3, [r7, #20] 801611e: 491d ldr r1, [pc, #116] @ (8016194 ) 8016120: 697a ldr r2, [r7, #20] 8016122: 4613 mov r3, r2 8016124: 009b lsls r3, r3, #2 8016126: 4413 add r3, r2 8016128: 009b lsls r3, r3, #2 801612a: 440b add r3, r1 801612c: 681b ldr r3, [r3, #0] 801612e: 2b00 cmp r3, #0 8016130: d0e3 beq.n 80160fa 8016132: 697a ldr r2, [r7, #20] 8016134: 4613 mov r3, r2 8016136: 009b lsls r3, r3, #2 8016138: 4413 add r3, r2 801613a: 009b lsls r3, r3, #2 801613c: 4a15 ldr r2, [pc, #84] @ (8016194 ) 801613e: 4413 add r3, r2 8016140: 60bb str r3, [r7, #8] 8016142: 68bb ldr r3, [r7, #8] 8016144: 685b ldr r3, [r3, #4] 8016146: 685a ldr r2, [r3, #4] 8016148: 68bb ldr r3, [r7, #8] 801614a: 605a str r2, [r3, #4] 801614c: 68bb ldr r3, [r7, #8] 801614e: 685a ldr r2, [r3, #4] 8016150: 68bb ldr r3, [r7, #8] 8016152: 3308 adds r3, #8 8016154: 429a cmp r2, r3 8016156: d103 bne.n 8016160 8016158: 68bb ldr r3, [r7, #8] 801615a: 68da ldr r2, [r3, #12] 801615c: 68bb ldr r3, [r7, #8] 801615e: 605a str r2, [r3, #4] 8016160: 68bb ldr r3, [r7, #8] 8016162: 685b ldr r3, [r3, #4] 8016164: 68db ldr r3, [r3, #12] 8016166: 4a09 ldr r2, [pc, #36] @ (801618c ) 8016168: 6013 str r3, [r2, #0] 801616a: 4a09 ldr r2, [pc, #36] @ (8016190 ) 801616c: 697b ldr r3, [r7, #20] 801616e: 6013 str r3, [r2, #0] configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); 8016170: 4b06 ldr r3, [pc, #24] @ (801618c ) 8016172: 681b ldr r3, [r3, #0] 8016174: 3354 adds r3, #84 @ 0x54 8016176: 4a08 ldr r2, [pc, #32] @ (8016198 ) 8016178: 6013 str r3, [r2, #0] } 801617a: bf00 nop 801617c: 3718 adds r7, #24 801617e: 46bd mov sp, r7 8016180: bd80 pop {r7, pc} 8016182: bf00 nop 8016184: 20002664 .word 0x20002664 8016188: 20002650 .word 0x20002650 801618c: 20002168 .word 0x20002168 8016190: 20002644 .word 0x20002644 8016194: 2000216c .word 0x2000216c 8016198: 2000011c .word 0x2000011c 0801619c : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 801619c: b580 push {r7, lr} 801619e: b084 sub sp, #16 80161a0: af00 add r7, sp, #0 80161a2: 6078 str r0, [r7, #4] 80161a4: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 80161a6: 687b ldr r3, [r7, #4] 80161a8: 2b00 cmp r3, #0 80161aa: d10b bne.n 80161c4 __asm volatile 80161ac: f04f 0350 mov.w r3, #80 @ 0x50 80161b0: f383 8811 msr BASEPRI, r3 80161b4: f3bf 8f6f isb sy 80161b8: f3bf 8f4f dsb sy 80161bc: 60fb str r3, [r7, #12] } 80161be: bf00 nop 80161c0: bf00 nop 80161c2: e7fd b.n 80161c0 * xItemValue = ( configMAX_PRIORITIES - uxPriority ) * Therefore, the event list is sorted in descending priority order. * * The queue that contains the event list is locked, preventing * simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80161c4: 4b07 ldr r3, [pc, #28] @ (80161e4 ) 80161c6: 681b ldr r3, [r3, #0] 80161c8: 3318 adds r3, #24 80161ca: 4619 mov r1, r3 80161cc: 6878 ldr r0, [r7, #4] 80161ce: f7fe f8ec bl 80143aa prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 80161d2: 2101 movs r1, #1 80161d4: 6838 ldr r0, [r7, #0] 80161d6: f001 f919 bl 801740c } 80161da: bf00 nop 80161dc: 3710 adds r7, #16 80161de: 46bd mov sp, r7 80161e0: bd80 pop {r7, pc} 80161e2: bf00 nop 80161e4: 20002168 .word 0x20002168 080161e8 : #if ( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 80161e8: b580 push {r7, lr} 80161ea: b086 sub sp, #24 80161ec: af00 add r7, sp, #0 80161ee: 60f8 str r0, [r7, #12] 80161f0: 60b9 str r1, [r7, #8] 80161f2: 607a str r2, [r7, #4] configASSERT( pxEventList ); 80161f4: 68fb ldr r3, [r7, #12] 80161f6: 2b00 cmp r3, #0 80161f8: d10b bne.n 8016212 __asm volatile 80161fa: f04f 0350 mov.w r3, #80 @ 0x50 80161fe: f383 8811 msr BASEPRI, r3 8016202: f3bf 8f6f isb sy 8016206: f3bf 8f4f dsb sy 801620a: 613b str r3, [r7, #16] } 801620c: bf00 nop 801620e: bf00 nop 8016210: e7fd b.n 801620e /* Place the event list item of the TCB in the appropriate event list. * In this case it is assume that this is the only task that is going to * be waiting on this event list, so the faster vListInsertEnd() function * can be used in place of vListInsert. */ listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8016212: 68fb ldr r3, [r7, #12] 8016214: 685b ldr r3, [r3, #4] 8016216: 617b str r3, [r7, #20] 8016218: 4b15 ldr r3, [pc, #84] @ (8016270 ) 801621a: 681b ldr r3, [r3, #0] 801621c: 697a ldr r2, [r7, #20] 801621e: 61da str r2, [r3, #28] 8016220: 4b13 ldr r3, [pc, #76] @ (8016270 ) 8016222: 681b ldr r3, [r3, #0] 8016224: 697a ldr r2, [r7, #20] 8016226: 6892 ldr r2, [r2, #8] 8016228: 621a str r2, [r3, #32] 801622a: 4b11 ldr r3, [pc, #68] @ (8016270 ) 801622c: 681a ldr r2, [r3, #0] 801622e: 697b ldr r3, [r7, #20] 8016230: 689b ldr r3, [r3, #8] 8016232: 3218 adds r2, #24 8016234: 605a str r2, [r3, #4] 8016236: 4b0e ldr r3, [pc, #56] @ (8016270 ) 8016238: 681b ldr r3, [r3, #0] 801623a: f103 0218 add.w r2, r3, #24 801623e: 697b ldr r3, [r7, #20] 8016240: 609a str r2, [r3, #8] 8016242: 4b0b ldr r3, [pc, #44] @ (8016270 ) 8016244: 681b ldr r3, [r3, #0] 8016246: 68fa ldr r2, [r7, #12] 8016248: 629a str r2, [r3, #40] @ 0x28 801624a: 68fb ldr r3, [r7, #12] 801624c: 681b ldr r3, [r3, #0] 801624e: 1c5a adds r2, r3, #1 8016250: 68fb ldr r3, [r7, #12] 8016252: 601a str r2, [r3, #0] /* If the task should block indefinitely then set the block time to a * value that will be recognised as an indefinite delay inside the * prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 8016254: 687b ldr r3, [r7, #4] 8016256: 2b00 cmp r3, #0 8016258: d002 beq.n 8016260 { xTicksToWait = portMAX_DELAY; 801625a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801625e: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 8016260: 6879 ldr r1, [r7, #4] 8016262: 68b8 ldr r0, [r7, #8] 8016264: f001 f8d2 bl 801740c } 8016268: bf00 nop 801626a: 3718 adds r7, #24 801626c: 46bd mov sp, r7 801626e: bd80 pop {r7, pc} 8016270: 20002168 .word 0x20002168 08016274 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 8016274: b480 push {r7} 8016276: b08b sub sp, #44 @ 0x2c 8016278: af00 add r7, sp, #0 801627a: 6078 str r0, [r7, #4] * get called - the lock count on the queue will get modified instead. This * means exclusive access to the event list is guaranteed here. * * This function assumes that a check has already been made to ensure that * pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801627c: 687b ldr r3, [r7, #4] 801627e: 68db ldr r3, [r3, #12] 8016280: 68db ldr r3, [r3, #12] 8016282: 623b str r3, [r7, #32] configASSERT( pxUnblockedTCB ); 8016284: 6a3b ldr r3, [r7, #32] 8016286: 2b00 cmp r3, #0 8016288: d10b bne.n 80162a2 __asm volatile 801628a: f04f 0350 mov.w r3, #80 @ 0x50 801628e: f383 8811 msr BASEPRI, r3 8016292: f3bf 8f6f isb sy 8016296: f3bf 8f4f dsb sy 801629a: 60fb str r3, [r7, #12] } 801629c: bf00 nop 801629e: bf00 nop 80162a0: e7fd b.n 801629e listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) ); 80162a2: 6a3b ldr r3, [r7, #32] 80162a4: 6a9b ldr r3, [r3, #40] @ 0x28 80162a6: 61fb str r3, [r7, #28] 80162a8: 6a3b ldr r3, [r7, #32] 80162aa: 69db ldr r3, [r3, #28] 80162ac: 6a3a ldr r2, [r7, #32] 80162ae: 6a12 ldr r2, [r2, #32] 80162b0: 609a str r2, [r3, #8] 80162b2: 6a3b ldr r3, [r7, #32] 80162b4: 6a1b ldr r3, [r3, #32] 80162b6: 6a3a ldr r2, [r7, #32] 80162b8: 69d2 ldr r2, [r2, #28] 80162ba: 605a str r2, [r3, #4] 80162bc: 69fb ldr r3, [r7, #28] 80162be: 685a ldr r2, [r3, #4] 80162c0: 6a3b ldr r3, [r7, #32] 80162c2: 3318 adds r3, #24 80162c4: 429a cmp r2, r3 80162c6: d103 bne.n 80162d0 80162c8: 6a3b ldr r3, [r7, #32] 80162ca: 6a1a ldr r2, [r3, #32] 80162cc: 69fb ldr r3, [r7, #28] 80162ce: 605a str r2, [r3, #4] 80162d0: 6a3b ldr r3, [r7, #32] 80162d2: 2200 movs r2, #0 80162d4: 629a str r2, [r3, #40] @ 0x28 80162d6: 69fb ldr r3, [r7, #28] 80162d8: 681b ldr r3, [r3, #0] 80162da: 1e5a subs r2, r3, #1 80162dc: 69fb ldr r3, [r7, #28] 80162de: 601a str r2, [r3, #0] if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 80162e0: 4b4a ldr r3, [pc, #296] @ (801640c ) 80162e2: 681b ldr r3, [r3, #0] 80162e4: 2b00 cmp r3, #0 80162e6: d15f bne.n 80163a8 { listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); 80162e8: 6a3b ldr r3, [r7, #32] 80162ea: 695b ldr r3, [r3, #20] 80162ec: 617b str r3, [r7, #20] 80162ee: 6a3b ldr r3, [r7, #32] 80162f0: 689b ldr r3, [r3, #8] 80162f2: 6a3a ldr r2, [r7, #32] 80162f4: 68d2 ldr r2, [r2, #12] 80162f6: 609a str r2, [r3, #8] 80162f8: 6a3b ldr r3, [r7, #32] 80162fa: 68db ldr r3, [r3, #12] 80162fc: 6a3a ldr r2, [r7, #32] 80162fe: 6892 ldr r2, [r2, #8] 8016300: 605a str r2, [r3, #4] 8016302: 697b ldr r3, [r7, #20] 8016304: 685a ldr r2, [r3, #4] 8016306: 6a3b ldr r3, [r7, #32] 8016308: 3304 adds r3, #4 801630a: 429a cmp r2, r3 801630c: d103 bne.n 8016316 801630e: 6a3b ldr r3, [r7, #32] 8016310: 68da ldr r2, [r3, #12] 8016312: 697b ldr r3, [r7, #20] 8016314: 605a str r2, [r3, #4] 8016316: 6a3b ldr r3, [r7, #32] 8016318: 2200 movs r2, #0 801631a: 615a str r2, [r3, #20] 801631c: 697b ldr r3, [r7, #20] 801631e: 681b ldr r3, [r3, #0] 8016320: 1e5a subs r2, r3, #1 8016322: 697b ldr r3, [r7, #20] 8016324: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxUnblockedTCB ); 8016326: 6a3b ldr r3, [r7, #32] 8016328: 6ada ldr r2, [r3, #44] @ 0x2c 801632a: 4b39 ldr r3, [pc, #228] @ (8016410 ) 801632c: 681b ldr r3, [r3, #0] 801632e: 429a cmp r2, r3 8016330: d903 bls.n 801633a 8016332: 6a3b ldr r3, [r7, #32] 8016334: 6adb ldr r3, [r3, #44] @ 0x2c 8016336: 4a36 ldr r2, [pc, #216] @ (8016410 ) 8016338: 6013 str r3, [r2, #0] 801633a: 6a3b ldr r3, [r7, #32] 801633c: 6ada ldr r2, [r3, #44] @ 0x2c 801633e: 4935 ldr r1, [pc, #212] @ (8016414 ) 8016340: 4613 mov r3, r2 8016342: 009b lsls r3, r3, #2 8016344: 4413 add r3, r2 8016346: 009b lsls r3, r3, #2 8016348: 440b add r3, r1 801634a: 3304 adds r3, #4 801634c: 681b ldr r3, [r3, #0] 801634e: 613b str r3, [r7, #16] 8016350: 6a3b ldr r3, [r7, #32] 8016352: 693a ldr r2, [r7, #16] 8016354: 609a str r2, [r3, #8] 8016356: 693b ldr r3, [r7, #16] 8016358: 689a ldr r2, [r3, #8] 801635a: 6a3b ldr r3, [r7, #32] 801635c: 60da str r2, [r3, #12] 801635e: 693b ldr r3, [r7, #16] 8016360: 689b ldr r3, [r3, #8] 8016362: 6a3a ldr r2, [r7, #32] 8016364: 3204 adds r2, #4 8016366: 605a str r2, [r3, #4] 8016368: 6a3b ldr r3, [r7, #32] 801636a: 1d1a adds r2, r3, #4 801636c: 693b ldr r3, [r7, #16] 801636e: 609a str r2, [r3, #8] 8016370: 6a3b ldr r3, [r7, #32] 8016372: 6ada ldr r2, [r3, #44] @ 0x2c 8016374: 4613 mov r3, r2 8016376: 009b lsls r3, r3, #2 8016378: 4413 add r3, r2 801637a: 009b lsls r3, r3, #2 801637c: 4a25 ldr r2, [pc, #148] @ (8016414 ) 801637e: 441a add r2, r3 8016380: 6a3b ldr r3, [r7, #32] 8016382: 615a str r2, [r3, #20] 8016384: 6a3b ldr r3, [r7, #32] 8016386: 6ada ldr r2, [r3, #44] @ 0x2c 8016388: 4922 ldr r1, [pc, #136] @ (8016414 ) 801638a: 4613 mov r3, r2 801638c: 009b lsls r3, r3, #2 801638e: 4413 add r3, r2 8016390: 009b lsls r3, r3, #2 8016392: 440b add r3, r1 8016394: 681b ldr r3, [r3, #0] 8016396: 1c59 adds r1, r3, #1 8016398: 481e ldr r0, [pc, #120] @ (8016414 ) 801639a: 4613 mov r3, r2 801639c: 009b lsls r3, r3, #2 801639e: 4413 add r3, r2 80163a0: 009b lsls r3, r3, #2 80163a2: 4403 add r3, r0 80163a4: 6019 str r1, [r3, #0] 80163a6: e01b b.n 80163e0 } else { /* The delayed and ready lists cannot be accessed, so hold this task * pending until the scheduler is resumed. */ listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 80163a8: 4b1b ldr r3, [pc, #108] @ (8016418 ) 80163aa: 685b ldr r3, [r3, #4] 80163ac: 61bb str r3, [r7, #24] 80163ae: 6a3b ldr r3, [r7, #32] 80163b0: 69ba ldr r2, [r7, #24] 80163b2: 61da str r2, [r3, #28] 80163b4: 69bb ldr r3, [r7, #24] 80163b6: 689a ldr r2, [r3, #8] 80163b8: 6a3b ldr r3, [r7, #32] 80163ba: 621a str r2, [r3, #32] 80163bc: 69bb ldr r3, [r7, #24] 80163be: 689b ldr r3, [r3, #8] 80163c0: 6a3a ldr r2, [r7, #32] 80163c2: 3218 adds r2, #24 80163c4: 605a str r2, [r3, #4] 80163c6: 6a3b ldr r3, [r7, #32] 80163c8: f103 0218 add.w r2, r3, #24 80163cc: 69bb ldr r3, [r7, #24] 80163ce: 609a str r2, [r3, #8] 80163d0: 6a3b ldr r3, [r7, #32] 80163d2: 4a11 ldr r2, [pc, #68] @ (8016418 ) 80163d4: 629a str r2, [r3, #40] @ 0x28 80163d6: 4b10 ldr r3, [pc, #64] @ (8016418 ) 80163d8: 681b ldr r3, [r3, #0] 80163da: 3301 adds r3, #1 80163dc: 4a0e ldr r2, [pc, #56] @ (8016418 ) 80163de: 6013 str r3, [r2, #0] } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 80163e0: 6a3b ldr r3, [r7, #32] 80163e2: 6ada ldr r2, [r3, #44] @ 0x2c 80163e4: 4b0d ldr r3, [pc, #52] @ (801641c ) 80163e6: 681b ldr r3, [r3, #0] 80163e8: 6adb ldr r3, [r3, #44] @ 0x2c 80163ea: 429a cmp r2, r3 80163ec: d905 bls.n 80163fa { /* Return true if the task removed from the event list has a higher * priority than the calling task. This allows the calling task to know if * it should force a context switch now. */ xReturn = pdTRUE; 80163ee: 2301 movs r3, #1 80163f0: 627b str r3, [r7, #36] @ 0x24 /* Mark that a yield is pending in case the user is not using the * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80163f2: 4b0b ldr r3, [pc, #44] @ (8016420 ) 80163f4: 2201 movs r2, #1 80163f6: 601a str r2, [r3, #0] 80163f8: e001 b.n 80163fe } else { xReturn = pdFALSE; 80163fa: 2300 movs r3, #0 80163fc: 627b str r3, [r7, #36] @ 0x24 } return xReturn; 80163fe: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016400: 4618 mov r0, r3 8016402: 372c adds r7, #44 @ 0x2c 8016404: 46bd mov sp, r7 8016406: f85d 7b04 ldr.w r7, [sp], #4 801640a: 4770 bx lr 801640c: 20002664 .word 0x20002664 8016410: 20002644 .word 0x20002644 8016414: 2000216c .word 0x2000216c 8016418: 200025fc .word 0x200025fc 801641c: 20002168 .word 0x20002168 8016420: 20002650 .word 0x20002650 08016424 : taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8016424: b480 push {r7} 8016426: b083 sub sp, #12 8016428: af00 add r7, sp, #0 801642a: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 801642c: 4b06 ldr r3, [pc, #24] @ (8016448 ) 801642e: 681a ldr r2, [r3, #0] 8016430: 687b ldr r3, [r7, #4] 8016432: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8016434: 4b05 ldr r3, [pc, #20] @ (801644c ) 8016436: 681a ldr r2, [r3, #0] 8016438: 687b ldr r3, [r7, #4] 801643a: 605a str r2, [r3, #4] } 801643c: bf00 nop 801643e: 370c adds r7, #12 8016440: 46bd mov sp, r7 8016442: f85d 7b04 ldr.w r7, [sp], #4 8016446: 4770 bx lr 8016448: 20002654 .word 0x20002654 801644c: 20002640 .word 0x20002640 08016450 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8016450: b580 push {r7, lr} 8016452: b088 sub sp, #32 8016454: af00 add r7, sp, #0 8016456: 6078 str r0, [r7, #4] 8016458: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 801645a: 687b ldr r3, [r7, #4] 801645c: 2b00 cmp r3, #0 801645e: d10b bne.n 8016478 __asm volatile 8016460: f04f 0350 mov.w r3, #80 @ 0x50 8016464: f383 8811 msr BASEPRI, r3 8016468: f3bf 8f6f isb sy 801646c: f3bf 8f4f dsb sy 8016470: 613b str r3, [r7, #16] } 8016472: bf00 nop 8016474: bf00 nop 8016476: e7fd b.n 8016474 configASSERT( pxTicksToWait ); 8016478: 683b ldr r3, [r7, #0] 801647a: 2b00 cmp r3, #0 801647c: d10b bne.n 8016496 __asm volatile 801647e: f04f 0350 mov.w r3, #80 @ 0x50 8016482: f383 8811 msr BASEPRI, r3 8016486: f3bf 8f6f isb sy 801648a: f3bf 8f4f dsb sy 801648e: 60fb str r3, [r7, #12] } 8016490: bf00 nop 8016492: bf00 nop 8016494: e7fd b.n 8016492 taskENTER_CRITICAL(); 8016496: f001 fc3b bl 8017d10 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 801649a: 4b1f ldr r3, [pc, #124] @ (8016518 ) 801649c: 681b ldr r3, [r3, #0] 801649e: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 80164a0: 687b ldr r3, [r7, #4] 80164a2: 685b ldr r3, [r3, #4] 80164a4: 69ba ldr r2, [r7, #24] 80164a6: 1ad3 subs r3, r2, r3 80164a8: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 80164aa: 683b ldr r3, [r7, #0] 80164ac: 681b ldr r3, [r3, #0] 80164ae: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80164b2: d102 bne.n 80164ba { /* If INCLUDE_vTaskSuspend is set to 1 and the block time * specified is the maximum block time then the task should block * indefinitely, and therefore never time out. */ xReturn = pdFALSE; 80164b4: 2300 movs r3, #0 80164b6: 61fb str r3, [r7, #28] 80164b8: e026 b.n 8016508 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 80164ba: 687b ldr r3, [r7, #4] 80164bc: 681a ldr r2, [r3, #0] 80164be: 4b17 ldr r3, [pc, #92] @ (801651c ) 80164c0: 681b ldr r3, [r3, #0] 80164c2: 429a cmp r2, r3 80164c4: d00a beq.n 80164dc 80164c6: 687b ldr r3, [r7, #4] 80164c8: 685b ldr r3, [r3, #4] 80164ca: 69ba ldr r2, [r7, #24] 80164cc: 429a cmp r2, r3 80164ce: d305 bcc.n 80164dc /* The tick count is greater than the time at which * vTaskSetTimeout() was called, but has also overflowed since * vTaskSetTimeOut() was called. It must have wrapped all the way * around and gone past again. This passed since vTaskSetTimeout() * was called. */ xReturn = pdTRUE; 80164d0: 2301 movs r3, #1 80164d2: 61fb str r3, [r7, #28] *pxTicksToWait = ( TickType_t ) 0; 80164d4: 683b ldr r3, [r7, #0] 80164d6: 2200 movs r2, #0 80164d8: 601a str r2, [r3, #0] 80164da: e015 b.n 8016508 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 80164dc: 683b ldr r3, [r7, #0] 80164de: 681b ldr r3, [r3, #0] 80164e0: 697a ldr r2, [r7, #20] 80164e2: 429a cmp r2, r3 80164e4: d20b bcs.n 80164fe { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 80164e6: 683b ldr r3, [r7, #0] 80164e8: 681a ldr r2, [r3, #0] 80164ea: 697b ldr r3, [r7, #20] 80164ec: 1ad2 subs r2, r2, r3 80164ee: 683b ldr r3, [r7, #0] 80164f0: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 80164f2: 6878 ldr r0, [r7, #4] 80164f4: f7ff ff96 bl 8016424 xReturn = pdFALSE; 80164f8: 2300 movs r3, #0 80164fa: 61fb str r3, [r7, #28] 80164fc: e004 b.n 8016508 } else { *pxTicksToWait = ( TickType_t ) 0; 80164fe: 683b ldr r3, [r7, #0] 8016500: 2200 movs r2, #0 8016502: 601a str r2, [r3, #0] xReturn = pdTRUE; 8016504: 2301 movs r3, #1 8016506: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 8016508: f001 fc34 bl 8017d74 return xReturn; 801650c: 69fb ldr r3, [r7, #28] } 801650e: 4618 mov r0, r3 8016510: 3720 adds r7, #32 8016512: 46bd mov sp, r7 8016514: bd80 pop {r7, pc} 8016516: bf00 nop 8016518: 20002640 .word 0x20002640 801651c: 20002654 .word 0x20002654 08016520 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 8016520: b480 push {r7} 8016522: af00 add r7, sp, #0 xYieldPending = pdTRUE; 8016524: 4b03 ldr r3, [pc, #12] @ (8016534 ) 8016526: 2201 movs r2, #1 8016528: 601a str r2, [r3, #0] } 801652a: bf00 nop 801652c: 46bd mov sp, r7 801652e: f85d 7b04 ldr.w r7, [sp], #4 8016532: 4770 bx lr 8016534: 20002650 .word 0x20002650 08016538 : * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8016538: b580 push {r7, lr} 801653a: b082 sub sp, #8 801653c: af00 add r7, sp, #0 801653e: 6078 str r0, [r7, #4] for( ; ; ) { /* See if any tasks have deleted themselves - if so then the idle task * is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8016540: f000 f852 bl 80165e8 * * A critical region is not required here as we are just reading from * the list, and an occasional incorrect value will not matter. If * the ready list at the idle priority contains more than one task * then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 8016544: 4b06 ldr r3, [pc, #24] @ (8016560 ) 8016546: 681b ldr r3, [r3, #0] 8016548: 2b01 cmp r3, #1 801654a: d9f9 bls.n 8016540 { taskYIELD(); 801654c: 4b05 ldr r3, [pc, #20] @ (8016564 ) 801654e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016552: 601a str r2, [r3, #0] 8016554: f3bf 8f4f dsb sy 8016558: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 801655c: e7f0 b.n 8016540 801655e: bf00 nop 8016560: 2000216c .word 0x2000216c 8016564: e000ed04 .word 0xe000ed04 08016568 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8016568: b580 push {r7, lr} 801656a: b082 sub sp, #8 801656c: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 801656e: 2300 movs r3, #0 8016570: 607b str r3, [r7, #4] 8016572: e00c b.n 801658e { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8016574: 687a ldr r2, [r7, #4] 8016576: 4613 mov r3, r2 8016578: 009b lsls r3, r3, #2 801657a: 4413 add r3, r2 801657c: 009b lsls r3, r3, #2 801657e: 4a12 ldr r2, [pc, #72] @ (80165c8 ) 8016580: 4413 add r3, r2 8016582: 4618 mov r0, r3 8016584: f7fd fee4 bl 8014350 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8016588: 687b ldr r3, [r7, #4] 801658a: 3301 adds r3, #1 801658c: 607b str r3, [r7, #4] 801658e: 687b ldr r3, [r7, #4] 8016590: 2b37 cmp r3, #55 @ 0x37 8016592: d9ef bls.n 8016574 } vListInitialise( &xDelayedTaskList1 ); 8016594: 480d ldr r0, [pc, #52] @ (80165cc ) 8016596: f7fd fedb bl 8014350 vListInitialise( &xDelayedTaskList2 ); 801659a: 480d ldr r0, [pc, #52] @ (80165d0 ) 801659c: f7fd fed8 bl 8014350 vListInitialise( &xPendingReadyList ); 80165a0: 480c ldr r0, [pc, #48] @ (80165d4 ) 80165a2: f7fd fed5 bl 8014350 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 80165a6: 480c ldr r0, [pc, #48] @ (80165d8 ) 80165a8: f7fd fed2 bl 8014350 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 80165ac: 480b ldr r0, [pc, #44] @ (80165dc ) 80165ae: f7fd fecf bl 8014350 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList * using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 80165b2: 4b0b ldr r3, [pc, #44] @ (80165e0 ) 80165b4: 4a05 ldr r2, [pc, #20] @ (80165cc ) 80165b6: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 80165b8: 4b0a ldr r3, [pc, #40] @ (80165e4 ) 80165ba: 4a05 ldr r2, [pc, #20] @ (80165d0 ) 80165bc: 601a str r2, [r3, #0] } 80165be: bf00 nop 80165c0: 3708 adds r7, #8 80165c2: 46bd mov sp, r7 80165c4: bd80 pop {r7, pc} 80165c6: bf00 nop 80165c8: 2000216c .word 0x2000216c 80165cc: 200025cc .word 0x200025cc 80165d0: 200025e0 .word 0x200025e0 80165d4: 200025fc .word 0x200025fc 80165d8: 20002610 .word 0x20002610 80165dc: 20002628 .word 0x20002628 80165e0: 200025f4 .word 0x200025f4 80165e4: 200025f8 .word 0x200025f8 080165e8 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 80165e8: b580 push {r7, lr} 80165ea: b082 sub sp, #8 80165ec: af00 add r7, sp, #0 { TCB_t * pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() * being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 80165ee: e019 b.n 8016624 { taskENTER_CRITICAL(); 80165f0: f001 fb8e bl 8017d10 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80165f4: 4b10 ldr r3, [pc, #64] @ (8016638 ) 80165f6: 68db ldr r3, [r3, #12] 80165f8: 68db ldr r3, [r3, #12] 80165fa: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80165fc: 687b ldr r3, [r7, #4] 80165fe: 3304 adds r3, #4 8016600: 4618 mov r0, r3 8016602: f7fd ff0b bl 801441c --uxCurrentNumberOfTasks; 8016606: 4b0d ldr r3, [pc, #52] @ (801663c ) 8016608: 681b ldr r3, [r3, #0] 801660a: 3b01 subs r3, #1 801660c: 4a0b ldr r2, [pc, #44] @ (801663c ) 801660e: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 8016610: 4b0b ldr r3, [pc, #44] @ (8016640 ) 8016612: 681b ldr r3, [r3, #0] 8016614: 3b01 subs r3, #1 8016616: 4a0a ldr r2, [pc, #40] @ (8016640 ) 8016618: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 801661a: f001 fbab bl 8017d74 prvDeleteTCB( pxTCB ); 801661e: 6878 ldr r0, [r7, #4] 8016620: f000 f810 bl 8016644 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8016624: 4b06 ldr r3, [pc, #24] @ (8016640 ) 8016626: 681b ldr r3, [r3, #0] 8016628: 2b00 cmp r3, #0 801662a: d1e1 bne.n 80165f0 } } #endif /* INCLUDE_vTaskDelete */ } 801662c: bf00 nop 801662e: bf00 nop 8016630: 3708 adds r7, #8 8016632: 46bd mov sp, r7 8016634: bd80 pop {r7, pc} 8016636: bf00 nop 8016638: 20002610 .word 0x20002610 801663c: 2000263c .word 0x2000263c 8016640: 20002624 .word 0x20002624 08016644 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t * pxTCB ) { 8016644: b580 push {r7, lr} 8016646: b084 sub sp, #16 8016648: af00 add r7, sp, #0 801664a: 6078 str r0, [r7, #4] portCLEAN_UP_TCB( pxTCB ); #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) { /* Free up the memory allocated for the task's TLS Block. */ configDEINIT_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); 801664c: 4b18 ldr r3, [pc, #96] @ (80166b0 ) 801664e: 681b ldr r3, [r3, #0] 8016650: 3354 adds r3, #84 @ 0x54 8016652: 4618 mov r0, r3 8016654: f003 fe62 bl 801a31c <_reclaim_reent> #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so * check what was statically allocated before trying to free the * memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8016658: 687b ldr r3, [r7, #4] 801665a: f893 30aa ldrb.w r3, [r3, #170] @ 0xaa 801665e: 2b00 cmp r3, #0 8016660: d108 bne.n 8016674 { /* Both the stack and TCB were allocated dynamically, so both * must be freed. */ vPortFreeStack( pxTCB->pxStack ); 8016662: 687b ldr r3, [r7, #4] 8016664: 6b1b ldr r3, [r3, #48] @ 0x30 8016666: 4618 mov r0, r3 8016668: f001 fd46 bl 80180f8 vPortFree( pxTCB ); 801666c: 6878 ldr r0, [r7, #4] 801666e: f001 fd43 bl 80180f8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8016672: e019 b.n 80166a8 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8016674: 687b ldr r3, [r7, #4] 8016676: f893 30aa ldrb.w r3, [r3, #170] @ 0xaa 801667a: 2b01 cmp r3, #1 801667c: d103 bne.n 8016686 vPortFree( pxTCB ); 801667e: 6878 ldr r0, [r7, #4] 8016680: f001 fd3a bl 80180f8 } 8016684: e010 b.n 80166a8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8016686: 687b ldr r3, [r7, #4] 8016688: f893 30aa ldrb.w r3, [r3, #170] @ 0xaa 801668c: 2b02 cmp r3, #2 801668e: d00b beq.n 80166a8 __asm volatile 8016690: f04f 0350 mov.w r3, #80 @ 0x50 8016694: f383 8811 msr BASEPRI, r3 8016698: f3bf 8f6f isb sy 801669c: f3bf 8f4f dsb sy 80166a0: 60fb str r3, [r7, #12] } 80166a2: bf00 nop 80166a4: bf00 nop 80166a6: e7fd b.n 80166a4 } 80166a8: bf00 nop 80166aa: 3710 adds r7, #16 80166ac: 46bd mov sp, r7 80166ae: bd80 pop {r7, pc} 80166b0: 20002168 .word 0x20002168 080166b4 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 80166b4: b480 push {r7} 80166b6: af00 add r7, sp, #0 if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80166b8: 4b0a ldr r3, [pc, #40] @ (80166e4 ) 80166ba: 681b ldr r3, [r3, #0] 80166bc: 681b ldr r3, [r3, #0] 80166be: 2b00 cmp r3, #0 80166c0: d104 bne.n 80166cc { /* The new current delayed list is empty. Set xNextTaskUnblockTime to * the maximum possible value so it is extremely unlikely that the * if( xTickCount >= xNextTaskUnblockTime ) test will pass until * there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 80166c2: 4b09 ldr r3, [pc, #36] @ (80166e8 ) 80166c4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80166c8: 601a str r2, [r3, #0] * the item at the head of the delayed list. This is the time at * which the task at the head of the delayed list should be removed * from the Blocked state. */ xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList ); } } 80166ca: e005 b.n 80166d8 xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList ); 80166cc: 4b05 ldr r3, [pc, #20] @ (80166e4 ) 80166ce: 681b ldr r3, [r3, #0] 80166d0: 68db ldr r3, [r3, #12] 80166d2: 681b ldr r3, [r3, #0] 80166d4: 4a04 ldr r2, [pc, #16] @ (80166e8 ) 80166d6: 6013 str r3, [r2, #0] } 80166d8: bf00 nop 80166da: 46bd mov sp, r7 80166dc: f85d 7b04 ldr.w r7, [sp], #4 80166e0: 4770 bx lr 80166e2: bf00 nop 80166e4: 200025f4 .word 0x200025f4 80166e8: 2000265c .word 0x2000265c 080166ec : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 80166ec: b480 push {r7} 80166ee: b083 sub sp, #12 80166f0: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from * an interrupt and the current TCB will always be the same for any * individual execution thread. */ xReturn = pxCurrentTCB; 80166f2: 4b05 ldr r3, [pc, #20] @ (8016708 ) 80166f4: 681b ldr r3, [r3, #0] 80166f6: 607b str r3, [r7, #4] return xReturn; 80166f8: 687b ldr r3, [r7, #4] } 80166fa: 4618 mov r0, r3 80166fc: 370c adds r7, #12 80166fe: 46bd mov sp, r7 8016700: f85d 7b04 ldr.w r7, [sp], #4 8016704: 4770 bx lr 8016706: bf00 nop 8016708: 20002168 .word 0x20002168 0801670c : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 801670c: b480 push {r7} 801670e: b083 sub sp, #12 8016710: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8016712: 4b0b ldr r3, [pc, #44] @ (8016740 ) 8016714: 681b ldr r3, [r3, #0] 8016716: 2b00 cmp r3, #0 8016718: d102 bne.n 8016720 { xReturn = taskSCHEDULER_NOT_STARTED; 801671a: 2301 movs r3, #1 801671c: 607b str r3, [r7, #4] 801671e: e008 b.n 8016732 } else { if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 8016720: 4b08 ldr r3, [pc, #32] @ (8016744 ) 8016722: 681b ldr r3, [r3, #0] 8016724: 2b00 cmp r3, #0 8016726: d102 bne.n 801672e { xReturn = taskSCHEDULER_RUNNING; 8016728: 2302 movs r3, #2 801672a: 607b str r3, [r7, #4] 801672c: e001 b.n 8016732 } else { xReturn = taskSCHEDULER_SUSPENDED; 801672e: 2300 movs r3, #0 8016730: 607b str r3, [r7, #4] } } return xReturn; 8016732: 687b ldr r3, [r7, #4] } 8016734: 4618 mov r0, r3 8016736: 370c adds r7, #12 8016738: 46bd mov sp, r7 801673a: f85d 7b04 ldr.w r7, [sp], #4 801673e: 4770 bx lr 8016740: 20002648 .word 0x20002648 8016744: 20002664 .word 0x20002664 08016748 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8016748: b580 push {r7, lr} 801674a: b086 sub sp, #24 801674c: af00 add r7, sp, #0 801674e: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8016750: 687b ldr r3, [r7, #4] 8016752: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8016754: 2300 movs r3, #0 8016756: 617b str r3, [r7, #20] /* If the mutex was given back by an interrupt while the queue was * locked then the mutex holder might now be NULL. _RB_ Is this still * needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8016758: 687b ldr r3, [r7, #4] 801675a: 2b00 cmp r3, #0 801675c: d079 beq.n 8016852 { /* If the holder of the mutex has a priority below the priority of * the task attempting to obtain the mutex then it will temporarily * inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 801675e: 693b ldr r3, [r7, #16] 8016760: 6ada ldr r2, [r3, #44] @ 0x2c 8016762: 4b3e ldr r3, [pc, #248] @ (801685c ) 8016764: 681b ldr r3, [r3, #0] 8016766: 6adb ldr r3, [r3, #44] @ 0x2c 8016768: 429a cmp r2, r3 801676a: d269 bcs.n 8016840 { /* Adjust the mutex holder state to account for its new * priority. Only reset the event list item value if the value is * not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 801676c: 693b ldr r3, [r7, #16] 801676e: 699b ldr r3, [r3, #24] 8016770: 2b00 cmp r3, #0 8016772: db06 blt.n 8016782 { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016774: 4b39 ldr r3, [pc, #228] @ (801685c ) 8016776: 681b ldr r3, [r3, #0] 8016778: 6adb ldr r3, [r3, #44] @ 0x2c 801677a: f1c3 0238 rsb r2, r3, #56 @ 0x38 801677e: 693b ldr r3, [r7, #16] 8016780: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need * to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8016782: 693b ldr r3, [r7, #16] 8016784: 6959 ldr r1, [r3, #20] 8016786: 693b ldr r3, [r7, #16] 8016788: 6ada ldr r2, [r3, #44] @ 0x2c 801678a: 4613 mov r3, r2 801678c: 009b lsls r3, r3, #2 801678e: 4413 add r3, r2 8016790: 009b lsls r3, r3, #2 8016792: 4a33 ldr r2, [pc, #204] @ (8016860 ) 8016794: 4413 add r3, r2 8016796: 4299 cmp r1, r3 8016798: d14a bne.n 8016830 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 801679a: 693b ldr r3, [r7, #16] 801679c: 3304 adds r3, #4 801679e: 4618 mov r0, r3 80167a0: f7fd fe3c bl 801441c { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 80167a4: 4b2d ldr r3, [pc, #180] @ (801685c ) 80167a6: 681b ldr r3, [r3, #0] 80167a8: 6ada ldr r2, [r3, #44] @ 0x2c 80167aa: 693b ldr r3, [r7, #16] 80167ac: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 80167ae: 693b ldr r3, [r7, #16] 80167b0: 6ada ldr r2, [r3, #44] @ 0x2c 80167b2: 4b2c ldr r3, [pc, #176] @ (8016864 ) 80167b4: 681b ldr r3, [r3, #0] 80167b6: 429a cmp r2, r3 80167b8: d903 bls.n 80167c2 80167ba: 693b ldr r3, [r7, #16] 80167bc: 6adb ldr r3, [r3, #44] @ 0x2c 80167be: 4a29 ldr r2, [pc, #164] @ (8016864 ) 80167c0: 6013 str r3, [r2, #0] 80167c2: 693b ldr r3, [r7, #16] 80167c4: 6ada ldr r2, [r3, #44] @ 0x2c 80167c6: 4926 ldr r1, [pc, #152] @ (8016860 ) 80167c8: 4613 mov r3, r2 80167ca: 009b lsls r3, r3, #2 80167cc: 4413 add r3, r2 80167ce: 009b lsls r3, r3, #2 80167d0: 440b add r3, r1 80167d2: 3304 adds r3, #4 80167d4: 681b ldr r3, [r3, #0] 80167d6: 60fb str r3, [r7, #12] 80167d8: 693b ldr r3, [r7, #16] 80167da: 68fa ldr r2, [r7, #12] 80167dc: 609a str r2, [r3, #8] 80167de: 68fb ldr r3, [r7, #12] 80167e0: 689a ldr r2, [r3, #8] 80167e2: 693b ldr r3, [r7, #16] 80167e4: 60da str r2, [r3, #12] 80167e6: 68fb ldr r3, [r7, #12] 80167e8: 689b ldr r3, [r3, #8] 80167ea: 693a ldr r2, [r7, #16] 80167ec: 3204 adds r2, #4 80167ee: 605a str r2, [r3, #4] 80167f0: 693b ldr r3, [r7, #16] 80167f2: 1d1a adds r2, r3, #4 80167f4: 68fb ldr r3, [r7, #12] 80167f6: 609a str r2, [r3, #8] 80167f8: 693b ldr r3, [r7, #16] 80167fa: 6ada ldr r2, [r3, #44] @ 0x2c 80167fc: 4613 mov r3, r2 80167fe: 009b lsls r3, r3, #2 8016800: 4413 add r3, r2 8016802: 009b lsls r3, r3, #2 8016804: 4a16 ldr r2, [pc, #88] @ (8016860 ) 8016806: 441a add r2, r3 8016808: 693b ldr r3, [r7, #16] 801680a: 615a str r2, [r3, #20] 801680c: 693b ldr r3, [r7, #16] 801680e: 6ada ldr r2, [r3, #44] @ 0x2c 8016810: 4913 ldr r1, [pc, #76] @ (8016860 ) 8016812: 4613 mov r3, r2 8016814: 009b lsls r3, r3, #2 8016816: 4413 add r3, r2 8016818: 009b lsls r3, r3, #2 801681a: 440b add r3, r1 801681c: 681b ldr r3, [r3, #0] 801681e: 1c59 adds r1, r3, #1 8016820: 480f ldr r0, [pc, #60] @ (8016860 ) 8016822: 4613 mov r3, r2 8016824: 009b lsls r3, r3, #2 8016826: 4413 add r3, r2 8016828: 009b lsls r3, r3, #2 801682a: 4403 add r3, r0 801682c: 6019 str r1, [r3, #0] 801682e: e004 b.n 801683a } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016830: 4b0a ldr r3, [pc, #40] @ (801685c ) 8016832: 681b ldr r3, [r3, #0] 8016834: 6ada ldr r2, [r3, #44] @ 0x2c 8016836: 693b ldr r3, [r7, #16] 8016838: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 801683a: 2301 movs r3, #1 801683c: 617b str r3, [r7, #20] 801683e: e008 b.n 8016852 } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8016840: 693b ldr r3, [r7, #16] 8016842: 6cda ldr r2, [r3, #76] @ 0x4c 8016844: 4b05 ldr r3, [pc, #20] @ (801685c ) 8016846: 681b ldr r3, [r3, #0] 8016848: 6adb ldr r3, [r3, #44] @ 0x2c 801684a: 429a cmp r2, r3 801684c: d201 bcs.n 8016852 * current priority of the mutex holder is not lower than the * priority of the task attempting to take the mutex. * Therefore the mutex holder must have already inherited a * priority, but inheritance would have occurred if that had * not been the case. */ xReturn = pdTRUE; 801684e: 2301 movs r3, #1 8016850: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016852: 697b ldr r3, [r7, #20] } 8016854: 4618 mov r0, r3 8016856: 3718 adds r7, #24 8016858: 46bd mov sp, r7 801685a: bd80 pop {r7, pc} 801685c: 20002168 .word 0x20002168 8016860: 2000216c .word 0x2000216c 8016864: 20002644 .word 0x20002644 08016868 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8016868: b580 push {r7, lr} 801686a: b088 sub sp, #32 801686c: af00 add r7, sp, #0 801686e: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8016870: 687b ldr r3, [r7, #4] 8016872: 61bb str r3, [r7, #24] BaseType_t xReturn = pdFALSE; 8016874: 2300 movs r3, #0 8016876: 61fb str r3, [r7, #28] if( pxMutexHolder != NULL ) 8016878: 687b ldr r3, [r7, #4] 801687a: 2b00 cmp r3, #0 801687c: f000 8081 beq.w 8016982 { /* A task can only have an inherited priority if it holds the mutex. * If the mutex is held by a task then it cannot be given from an * interrupt, and if a mutex is given by the holding task then it must * be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8016880: 4b42 ldr r3, [pc, #264] @ (801698c ) 8016882: 681b ldr r3, [r3, #0] 8016884: 69ba ldr r2, [r7, #24] 8016886: 429a cmp r2, r3 8016888: d00b beq.n 80168a2 __asm volatile 801688a: f04f 0350 mov.w r3, #80 @ 0x50 801688e: f383 8811 msr BASEPRI, r3 8016892: f3bf 8f6f isb sy 8016896: f3bf 8f4f dsb sy 801689a: 613b str r3, [r7, #16] } 801689c: bf00 nop 801689e: bf00 nop 80168a0: e7fd b.n 801689e configASSERT( pxTCB->uxMutexesHeld ); 80168a2: 69bb ldr r3, [r7, #24] 80168a4: 6d1b ldr r3, [r3, #80] @ 0x50 80168a6: 2b00 cmp r3, #0 80168a8: d10b bne.n 80168c2 __asm volatile 80168aa: f04f 0350 mov.w r3, #80 @ 0x50 80168ae: f383 8811 msr BASEPRI, r3 80168b2: f3bf 8f6f isb sy 80168b6: f3bf 8f4f dsb sy 80168ba: 60fb str r3, [r7, #12] } 80168bc: bf00 nop 80168be: bf00 nop 80168c0: e7fd b.n 80168be ( pxTCB->uxMutexesHeld )--; 80168c2: 69bb ldr r3, [r7, #24] 80168c4: 6d1b ldr r3, [r3, #80] @ 0x50 80168c6: 1e5a subs r2, r3, #1 80168c8: 69bb ldr r3, [r7, #24] 80168ca: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another * task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 80168cc: 69bb ldr r3, [r7, #24] 80168ce: 6ada ldr r2, [r3, #44] @ 0x2c 80168d0: 69bb ldr r3, [r7, #24] 80168d2: 6cdb ldr r3, [r3, #76] @ 0x4c 80168d4: 429a cmp r2, r3 80168d6: d054 beq.n 8016982 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 80168d8: 69bb ldr r3, [r7, #24] 80168da: 6d1b ldr r3, [r3, #80] @ 0x50 80168dc: 2b00 cmp r3, #0 80168de: d150 bne.n 8016982 /* A task can only have an inherited priority if it holds * the mutex. If the mutex is held by a task then it cannot be * given from an interrupt, and if a mutex is given by the * holding task then it must be the running state task. Remove * the holding task from the ready list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80168e0: 69bb ldr r3, [r7, #24] 80168e2: 3304 adds r3, #4 80168e4: 4618 mov r0, r3 80168e6: f7fd fd99 bl 801441c } /* Disinherit the priority before adding the task into the * new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 80168ea: 69bb ldr r3, [r7, #24] 80168ec: 6cda ldr r2, [r3, #76] @ 0x4c 80168ee: 69bb ldr r3, [r7, #24] 80168f0: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for * any other purpose if this task is running, and it must be * running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80168f2: 69bb ldr r3, [r7, #24] 80168f4: 6adb ldr r3, [r3, #44] @ 0x2c 80168f6: f1c3 0238 rsb r2, r3, #56 @ 0x38 80168fa: 69bb ldr r3, [r7, #24] 80168fc: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 80168fe: 69bb ldr r3, [r7, #24] 8016900: 6ada ldr r2, [r3, #44] @ 0x2c 8016902: 4b23 ldr r3, [pc, #140] @ (8016990 ) 8016904: 681b ldr r3, [r3, #0] 8016906: 429a cmp r2, r3 8016908: d903 bls.n 8016912 801690a: 69bb ldr r3, [r7, #24] 801690c: 6adb ldr r3, [r3, #44] @ 0x2c 801690e: 4a20 ldr r2, [pc, #128] @ (8016990 ) 8016910: 6013 str r3, [r2, #0] 8016912: 69bb ldr r3, [r7, #24] 8016914: 6ada ldr r2, [r3, #44] @ 0x2c 8016916: 491f ldr r1, [pc, #124] @ (8016994 ) 8016918: 4613 mov r3, r2 801691a: 009b lsls r3, r3, #2 801691c: 4413 add r3, r2 801691e: 009b lsls r3, r3, #2 8016920: 440b add r3, r1 8016922: 3304 adds r3, #4 8016924: 681b ldr r3, [r3, #0] 8016926: 617b str r3, [r7, #20] 8016928: 69bb ldr r3, [r7, #24] 801692a: 697a ldr r2, [r7, #20] 801692c: 609a str r2, [r3, #8] 801692e: 697b ldr r3, [r7, #20] 8016930: 689a ldr r2, [r3, #8] 8016932: 69bb ldr r3, [r7, #24] 8016934: 60da str r2, [r3, #12] 8016936: 697b ldr r3, [r7, #20] 8016938: 689b ldr r3, [r3, #8] 801693a: 69ba ldr r2, [r7, #24] 801693c: 3204 adds r2, #4 801693e: 605a str r2, [r3, #4] 8016940: 69bb ldr r3, [r7, #24] 8016942: 1d1a adds r2, r3, #4 8016944: 697b ldr r3, [r7, #20] 8016946: 609a str r2, [r3, #8] 8016948: 69bb ldr r3, [r7, #24] 801694a: 6ada ldr r2, [r3, #44] @ 0x2c 801694c: 4613 mov r3, r2 801694e: 009b lsls r3, r3, #2 8016950: 4413 add r3, r2 8016952: 009b lsls r3, r3, #2 8016954: 4a0f ldr r2, [pc, #60] @ (8016994 ) 8016956: 441a add r2, r3 8016958: 69bb ldr r3, [r7, #24] 801695a: 615a str r2, [r3, #20] 801695c: 69bb ldr r3, [r7, #24] 801695e: 6ada ldr r2, [r3, #44] @ 0x2c 8016960: 490c ldr r1, [pc, #48] @ (8016994 ) 8016962: 4613 mov r3, r2 8016964: 009b lsls r3, r3, #2 8016966: 4413 add r3, r2 8016968: 009b lsls r3, r3, #2 801696a: 440b add r3, r1 801696c: 681b ldr r3, [r3, #0] 801696e: 1c59 adds r1, r3, #1 8016970: 4808 ldr r0, [pc, #32] @ (8016994 ) 8016972: 4613 mov r3, r2 8016974: 009b lsls r3, r3, #2 8016976: 4413 add r3, r2 8016978: 009b lsls r3, r3, #2 801697a: 4403 add r3, r0 801697c: 6019 str r1, [r3, #0] * in an order different to that in which they were taken. * If a context switch did not occur when the first mutex was * returned, even if a task was waiting on it, then a context * switch should occur when the last mutex is returned whether * a task is waiting on it or not. */ xReturn = pdTRUE; 801697e: 2301 movs r3, #1 8016980: 61fb str r3, [r7, #28] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016982: 69fb ldr r3, [r7, #28] } 8016984: 4618 mov r0, r3 8016986: 3720 adds r7, #32 8016988: 46bd mov sp, r7 801698a: bd80 pop {r7, pc} 801698c: 20002168 .word 0x20002168 8016990: 20002644 .word 0x20002644 8016994: 2000216c .word 0x2000216c 08016998 : #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 8016998: b580 push {r7, lr} 801699a: b08a sub sp, #40 @ 0x28 801699c: af00 add r7, sp, #0 801699e: 6078 str r0, [r7, #4] 80169a0: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 80169a2: 687b ldr r3, [r7, #4] 80169a4: 623b str r3, [r7, #32] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 80169a6: 2301 movs r3, #1 80169a8: 61fb str r3, [r7, #28] if( pxMutexHolder != NULL ) 80169aa: 687b ldr r3, [r7, #4] 80169ac: 2b00 cmp r3, #0 80169ae: f000 8095 beq.w 8016adc { /* If pxMutexHolder is not NULL then the holder must hold at least * one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 80169b2: 6a3b ldr r3, [r7, #32] 80169b4: 6d1b ldr r3, [r3, #80] @ 0x50 80169b6: 2b00 cmp r3, #0 80169b8: d10b bne.n 80169d2 __asm volatile 80169ba: f04f 0350 mov.w r3, #80 @ 0x50 80169be: f383 8811 msr BASEPRI, r3 80169c2: f3bf 8f6f isb sy 80169c6: f3bf 8f4f dsb sy 80169ca: 613b str r3, [r7, #16] } 80169cc: bf00 nop 80169ce: bf00 nop 80169d0: e7fd b.n 80169ce /* Determine the priority to which the priority of the task that * holds the mutex should be set. This will be the greater of the * holding task's base priority and the priority of the highest * priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 80169d2: 6a3b ldr r3, [r7, #32] 80169d4: 6cdb ldr r3, [r3, #76] @ 0x4c 80169d6: 683a ldr r2, [r7, #0] 80169d8: 429a cmp r2, r3 80169da: d902 bls.n 80169e2 { uxPriorityToUse = uxHighestPriorityWaitingTask; 80169dc: 683b ldr r3, [r7, #0] 80169de: 627b str r3, [r7, #36] @ 0x24 80169e0: e002 b.n 80169e8 } else { uxPriorityToUse = pxTCB->uxBasePriority; 80169e2: 6a3b ldr r3, [r7, #32] 80169e4: 6cdb ldr r3, [r3, #76] @ 0x4c 80169e6: 627b str r3, [r7, #36] @ 0x24 } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 80169e8: 6a3b ldr r3, [r7, #32] 80169ea: 6adb ldr r3, [r3, #44] @ 0x2c 80169ec: 6a7a ldr r2, [r7, #36] @ 0x24 80169ee: 429a cmp r2, r3 80169f0: d074 beq.n 8016adc { /* Only disinherit if no other mutexes are held. This is a * simplification in the priority inheritance implementation. If * the task that holds the mutex is also holding other mutexes then * the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 80169f2: 6a3b ldr r3, [r7, #32] 80169f4: 6d1b ldr r3, [r3, #80] @ 0x50 80169f6: 69fa ldr r2, [r7, #28] 80169f8: 429a cmp r2, r3 80169fa: d16f bne.n 8016adc { /* If a task has timed out because it already holds the * mutex it was trying to obtain then it cannot of inherited * its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 80169fc: 4b39 ldr r3, [pc, #228] @ (8016ae4 ) 80169fe: 681b ldr r3, [r3, #0] 8016a00: 6a3a ldr r2, [r7, #32] 8016a02: 429a cmp r2, r3 8016a04: d10b bne.n 8016a1e __asm volatile 8016a06: f04f 0350 mov.w r3, #80 @ 0x50 8016a0a: f383 8811 msr BASEPRI, r3 8016a0e: f3bf 8f6f isb sy 8016a12: f3bf 8f4f dsb sy 8016a16: 60fb str r3, [r7, #12] } 8016a18: bf00 nop 8016a1a: bf00 nop 8016a1c: e7fd b.n 8016a1a /* Disinherit the priority, remembering the previous * priority to facilitate determining the subject task's * state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 8016a1e: 6a3b ldr r3, [r7, #32] 8016a20: 6adb ldr r3, [r3, #44] @ 0x2c 8016a22: 61bb str r3, [r7, #24] pxTCB->uxPriority = uxPriorityToUse; 8016a24: 6a3b ldr r3, [r7, #32] 8016a26: 6a7a ldr r2, [r7, #36] @ 0x24 8016a28: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not * being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016a2a: 6a3b ldr r3, [r7, #32] 8016a2c: 699b ldr r3, [r3, #24] 8016a2e: 2b00 cmp r3, #0 8016a30: db04 blt.n 8016a3c { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016a32: 6a7b ldr r3, [r7, #36] @ 0x24 8016a34: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016a38: 6a3b ldr r3, [r7, #32] 8016a3a: 619a str r2, [r3, #24] * then the task that holds the mutex could be in either the * Ready, Blocked or Suspended states. Only remove the task * from its current state list if it is in the Ready state as * the task's priority is going to change and there is one * Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 8016a3c: 6a3b ldr r3, [r7, #32] 8016a3e: 6959 ldr r1, [r3, #20] 8016a40: 69ba ldr r2, [r7, #24] 8016a42: 4613 mov r3, r2 8016a44: 009b lsls r3, r3, #2 8016a46: 4413 add r3, r2 8016a48: 009b lsls r3, r3, #2 8016a4a: 4a27 ldr r2, [pc, #156] @ (8016ae8 ) 8016a4c: 4413 add r3, r2 8016a4e: 4299 cmp r1, r3 8016a50: d144 bne.n 8016adc { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016a52: 6a3b ldr r3, [r7, #32] 8016a54: 3304 adds r3, #4 8016a56: 4618 mov r0, r3 8016a58: f7fd fce0 bl 801441c else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8016a5c: 6a3b ldr r3, [r7, #32] 8016a5e: 6ada ldr r2, [r3, #44] @ 0x2c 8016a60: 4b22 ldr r3, [pc, #136] @ (8016aec ) 8016a62: 681b ldr r3, [r3, #0] 8016a64: 429a cmp r2, r3 8016a66: d903 bls.n 8016a70 8016a68: 6a3b ldr r3, [r7, #32] 8016a6a: 6adb ldr r3, [r3, #44] @ 0x2c 8016a6c: 4a1f ldr r2, [pc, #124] @ (8016aec ) 8016a6e: 6013 str r3, [r2, #0] 8016a70: 6a3b ldr r3, [r7, #32] 8016a72: 6ada ldr r2, [r3, #44] @ 0x2c 8016a74: 491c ldr r1, [pc, #112] @ (8016ae8 ) 8016a76: 4613 mov r3, r2 8016a78: 009b lsls r3, r3, #2 8016a7a: 4413 add r3, r2 8016a7c: 009b lsls r3, r3, #2 8016a7e: 440b add r3, r1 8016a80: 3304 adds r3, #4 8016a82: 681b ldr r3, [r3, #0] 8016a84: 617b str r3, [r7, #20] 8016a86: 6a3b ldr r3, [r7, #32] 8016a88: 697a ldr r2, [r7, #20] 8016a8a: 609a str r2, [r3, #8] 8016a8c: 697b ldr r3, [r7, #20] 8016a8e: 689a ldr r2, [r3, #8] 8016a90: 6a3b ldr r3, [r7, #32] 8016a92: 60da str r2, [r3, #12] 8016a94: 697b ldr r3, [r7, #20] 8016a96: 689b ldr r3, [r3, #8] 8016a98: 6a3a ldr r2, [r7, #32] 8016a9a: 3204 adds r2, #4 8016a9c: 605a str r2, [r3, #4] 8016a9e: 6a3b ldr r3, [r7, #32] 8016aa0: 1d1a adds r2, r3, #4 8016aa2: 697b ldr r3, [r7, #20] 8016aa4: 609a str r2, [r3, #8] 8016aa6: 6a3b ldr r3, [r7, #32] 8016aa8: 6ada ldr r2, [r3, #44] @ 0x2c 8016aaa: 4613 mov r3, r2 8016aac: 009b lsls r3, r3, #2 8016aae: 4413 add r3, r2 8016ab0: 009b lsls r3, r3, #2 8016ab2: 4a0d ldr r2, [pc, #52] @ (8016ae8 ) 8016ab4: 441a add r2, r3 8016ab6: 6a3b ldr r3, [r7, #32] 8016ab8: 615a str r2, [r3, #20] 8016aba: 6a3b ldr r3, [r7, #32] 8016abc: 6ada ldr r2, [r3, #44] @ 0x2c 8016abe: 490a ldr r1, [pc, #40] @ (8016ae8 ) 8016ac0: 4613 mov r3, r2 8016ac2: 009b lsls r3, r3, #2 8016ac4: 4413 add r3, r2 8016ac6: 009b lsls r3, r3, #2 8016ac8: 440b add r3, r1 8016aca: 681b ldr r3, [r3, #0] 8016acc: 1c59 adds r1, r3, #1 8016ace: 4806 ldr r0, [pc, #24] @ (8016ae8 ) 8016ad0: 4613 mov r3, r2 8016ad2: 009b lsls r3, r3, #2 8016ad4: 4413 add r3, r2 8016ad6: 009b lsls r3, r3, #2 8016ad8: 4403 add r3, r0 8016ada: 6019 str r1, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8016adc: bf00 nop 8016ade: 3728 adds r7, #40 @ 0x28 8016ae0: 46bd mov sp, r7 8016ae2: bd80 pop {r7, pc} 8016ae4: 20002168 .word 0x20002168 8016ae8: 2000216c .word 0x2000216c 8016aec: 20002644 .word 0x20002644 08016af0 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 8016af0: b480 push {r7} 8016af2: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created * then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 8016af4: 4b07 ldr r3, [pc, #28] @ (8016b14 ) 8016af6: 681b ldr r3, [r3, #0] 8016af8: 2b00 cmp r3, #0 8016afa: d004 beq.n 8016b06 { ( pxCurrentTCB->uxMutexesHeld )++; 8016afc: 4b05 ldr r3, [pc, #20] @ (8016b14 ) 8016afe: 681b ldr r3, [r3, #0] 8016b00: 6d1a ldr r2, [r3, #80] @ 0x50 8016b02: 3201 adds r2, #1 8016b04: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 8016b06: 4b03 ldr r3, [pc, #12] @ (8016b14 ) 8016b08: 681b ldr r3, [r3, #0] } 8016b0a: 4618 mov r0, r3 8016b0c: 46bd mov sp, r7 8016b0e: f85d 7b04 ldr.w r7, [sp], #4 8016b12: 4770 bx lr 8016b14: 20002168 .word 0x20002168 08016b18 : #if ( configUSE_TASK_NOTIFICATIONS == 1 ) uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait, BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) { 8016b18: b580 push {r7, lr} 8016b1a: b086 sub sp, #24 8016b1c: af00 add r7, sp, #0 8016b1e: 60f8 str r0, [r7, #12] 8016b20: 60b9 str r1, [r7, #8] 8016b22: 607a str r2, [r7, #4] uint32_t ulReturn; configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 8016b24: 68fb ldr r3, [r7, #12] 8016b26: 2b01 cmp r3, #1 8016b28: d90b bls.n 8016b42 __asm volatile 8016b2a: f04f 0350 mov.w r3, #80 @ 0x50 8016b2e: f383 8811 msr BASEPRI, r3 8016b32: f3bf 8f6f isb sy 8016b36: f3bf 8f4f dsb sy 8016b3a: 613b str r3, [r7, #16] } 8016b3c: bf00 nop 8016b3e: bf00 nop 8016b40: e7fd b.n 8016b3e taskENTER_CRITICAL(); 8016b42: f001 f8e5 bl 8017d10 { /* Only block if the notification count is not already non-zero. */ if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL ) 8016b46: 4b26 ldr r3, [pc, #152] @ (8016be0 ) 8016b48: 681b ldr r3, [r3, #0] 8016b4a: 68fa ldr r2, [r7, #12] 8016b4c: 3228 adds r2, #40 @ 0x28 8016b4e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8016b52: 2b00 cmp r3, #0 8016b54: d115 bne.n 8016b82 { /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; 8016b56: 4b22 ldr r3, [pc, #136] @ (8016be0 ) 8016b58: 681a ldr r2, [r3, #0] 8016b5a: 68fb ldr r3, [r7, #12] 8016b5c: 4413 add r3, r2 8016b5e: 33a8 adds r3, #168 @ 0xa8 8016b60: 2201 movs r2, #1 8016b62: 701a strb r2, [r3, #0] if( xTicksToWait > ( TickType_t ) 0 ) 8016b64: 687b ldr r3, [r7, #4] 8016b66: 2b00 cmp r3, #0 8016b68: d00b beq.n 8016b82 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016b6a: 2101 movs r1, #1 8016b6c: 6878 ldr r0, [r7, #4] 8016b6e: f000 fc4d bl 801740c /* All ports are written to allow a yield in a critical * section (some will yield immediately, others wait until the * critical section exits) - but it is not something that * application code should ever do. */ portYIELD_WITHIN_API(); 8016b72: 4b1c ldr r3, [pc, #112] @ (8016be4 ) 8016b74: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016b78: 601a str r2, [r3, #0] 8016b7a: f3bf 8f4f dsb sy 8016b7e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016b82: f001 f8f7 bl 8017d74 taskENTER_CRITICAL(); 8016b86: f001 f8c3 bl 8017d10 { traceTASK_NOTIFY_TAKE( uxIndexToWait ); ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; 8016b8a: 4b15 ldr r3, [pc, #84] @ (8016be0 ) 8016b8c: 681b ldr r3, [r3, #0] 8016b8e: 68fa ldr r2, [r7, #12] 8016b90: 3228 adds r2, #40 @ 0x28 8016b92: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8016b96: 617b str r3, [r7, #20] if( ulReturn != 0UL ) 8016b98: 697b ldr r3, [r7, #20] 8016b9a: 2b00 cmp r3, #0 8016b9c: d012 beq.n 8016bc4 { if( xClearCountOnExit != pdFALSE ) 8016b9e: 68bb ldr r3, [r7, #8] 8016ba0: 2b00 cmp r3, #0 8016ba2: d007 beq.n 8016bb4 { pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL; 8016ba4: 4b0e ldr r3, [pc, #56] @ (8016be0 ) 8016ba6: 681b ldr r3, [r3, #0] 8016ba8: 68fa ldr r2, [r7, #12] 8016baa: 3228 adds r2, #40 @ 0x28 8016bac: 2100 movs r1, #0 8016bae: f843 1022 str.w r1, [r3, r2, lsl #2] 8016bb2: e007 b.n 8016bc4 } else { pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1; 8016bb4: 4b0a ldr r3, [pc, #40] @ (8016be0 ) 8016bb6: 681b ldr r3, [r3, #0] 8016bb8: 697a ldr r2, [r7, #20] 8016bba: 1e51 subs r1, r2, #1 8016bbc: 68fa ldr r2, [r7, #12] 8016bbe: 3228 adds r2, #40 @ 0x28 8016bc0: f843 1022 str.w r1, [r3, r2, lsl #2] else { mtCOVERAGE_TEST_MARKER(); } pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; 8016bc4: 4b06 ldr r3, [pc, #24] @ (8016be0 ) 8016bc6: 681a ldr r2, [r3, #0] 8016bc8: 68fb ldr r3, [r7, #12] 8016bca: 4413 add r3, r2 8016bcc: 33a8 adds r3, #168 @ 0xa8 8016bce: 2200 movs r2, #0 8016bd0: 701a strb r2, [r3, #0] } taskEXIT_CRITICAL(); 8016bd2: f001 f8cf bl 8017d74 return ulReturn; 8016bd6: 697b ldr r3, [r7, #20] } 8016bd8: 4618 mov r0, r3 8016bda: 3718 adds r7, #24 8016bdc: 46bd mov sp, r7 8016bde: bd80 pop {r7, pc} 8016be0: 20002168 .word 0x20002168 8016be4: e000ed04 .word 0xe000ed04 08016be8 : BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t * pulNotificationValue, TickType_t xTicksToWait ) { 8016be8: b580 push {r7, lr} 8016bea: b086 sub sp, #24 8016bec: af00 add r7, sp, #0 8016bee: 60f8 str r0, [r7, #12] 8016bf0: 60b9 str r1, [r7, #8] 8016bf2: 607a str r2, [r7, #4] 8016bf4: 603b str r3, [r7, #0] BaseType_t xReturn; configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 8016bf6: 68fb ldr r3, [r7, #12] 8016bf8: 2b01 cmp r3, #1 8016bfa: d90b bls.n 8016c14 __asm volatile 8016bfc: f04f 0350 mov.w r3, #80 @ 0x50 8016c00: f383 8811 msr BASEPRI, r3 8016c04: f3bf 8f6f isb sy 8016c08: f3bf 8f4f dsb sy 8016c0c: 613b str r3, [r7, #16] } 8016c0e: bf00 nop 8016c10: bf00 nop 8016c12: e7fd b.n 8016c10 taskENTER_CRITICAL(); 8016c14: f001 f87c bl 8017d10 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) 8016c18: 4b31 ldr r3, [pc, #196] @ (8016ce0 ) 8016c1a: 681a ldr r2, [r3, #0] 8016c1c: 68fb ldr r3, [r7, #12] 8016c1e: 4413 add r3, r2 8016c20: 33a8 adds r3, #168 @ 0xa8 8016c22: 781b ldrb r3, [r3, #0] 8016c24: b2db uxtb r3, r3 8016c26: 2b02 cmp r3, #2 8016c28: d022 beq.n 8016c70 { /* Clear bits in the task's notification value as bits may get * set by the notifying task or interrupt. This can be used to * clear the value to zero. */ pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry; 8016c2a: 4b2d ldr r3, [pc, #180] @ (8016ce0 ) 8016c2c: 681b ldr r3, [r3, #0] 8016c2e: 68fa ldr r2, [r7, #12] 8016c30: 3228 adds r2, #40 @ 0x28 8016c32: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8016c36: 68ba ldr r2, [r7, #8] 8016c38: 43d2 mvns r2, r2 8016c3a: 4011 ands r1, r2 8016c3c: 68fa ldr r2, [r7, #12] 8016c3e: 3228 adds r2, #40 @ 0x28 8016c40: f843 1022 str.w r1, [r3, r2, lsl #2] /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; 8016c44: 4b26 ldr r3, [pc, #152] @ (8016ce0 ) 8016c46: 681a ldr r2, [r3, #0] 8016c48: 68fb ldr r3, [r7, #12] 8016c4a: 4413 add r3, r2 8016c4c: 33a8 adds r3, #168 @ 0xa8 8016c4e: 2201 movs r2, #1 8016c50: 701a strb r2, [r3, #0] if( xTicksToWait > ( TickType_t ) 0 ) 8016c52: 6a3b ldr r3, [r7, #32] 8016c54: 2b00 cmp r3, #0 8016c56: d00b beq.n 8016c70 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016c58: 2101 movs r1, #1 8016c5a: 6a38 ldr r0, [r7, #32] 8016c5c: f000 fbd6 bl 801740c /* All ports are written to allow a yield in a critical * section (some will yield immediately, others wait until the * critical section exits) - but it is not something that * application code should ever do. */ portYIELD_WITHIN_API(); 8016c60: 4b20 ldr r3, [pc, #128] @ (8016ce4 ) 8016c62: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016c66: 601a str r2, [r3, #0] 8016c68: f3bf 8f4f dsb sy 8016c6c: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016c70: f001 f880 bl 8017d74 taskENTER_CRITICAL(); 8016c74: f001 f84c bl 8017d10 { traceTASK_NOTIFY_WAIT( uxIndexToWait ); if( pulNotificationValue != NULL ) 8016c78: 683b ldr r3, [r7, #0] 8016c7a: 2b00 cmp r3, #0 8016c7c: d007 beq.n 8016c8e { /* Output the current notification value, which may or may not * have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; 8016c7e: 4b18 ldr r3, [pc, #96] @ (8016ce0 ) 8016c80: 681b ldr r3, [r3, #0] 8016c82: 68fa ldr r2, [r7, #12] 8016c84: 3228 adds r2, #40 @ 0x28 8016c86: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8016c8a: 683b ldr r3, [r7, #0] 8016c8c: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the * blocked state (because a notification was already pending) or the * task unblocked because of a notification. Otherwise the task * unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) 8016c8e: 4b14 ldr r3, [pc, #80] @ (8016ce0 ) 8016c90: 681a ldr r2, [r3, #0] 8016c92: 68fb ldr r3, [r7, #12] 8016c94: 4413 add r3, r2 8016c96: 33a8 adds r3, #168 @ 0xa8 8016c98: 781b ldrb r3, [r3, #0] 8016c9a: b2db uxtb r3, r3 8016c9c: 2b02 cmp r3, #2 8016c9e: d002 beq.n 8016ca6 { /* A notification was not received. */ xReturn = pdFALSE; 8016ca0: 2300 movs r3, #0 8016ca2: 617b str r3, [r7, #20] 8016ca4: e00e b.n 8016cc4 } else { /* A notification was already pending or a notification was * received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit; 8016ca6: 4b0e ldr r3, [pc, #56] @ (8016ce0 ) 8016ca8: 681b ldr r3, [r3, #0] 8016caa: 68fa ldr r2, [r7, #12] 8016cac: 3228 adds r2, #40 @ 0x28 8016cae: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8016cb2: 687a ldr r2, [r7, #4] 8016cb4: 43d2 mvns r2, r2 8016cb6: 4011 ands r1, r2 8016cb8: 68fa ldr r2, [r7, #12] 8016cba: 3228 adds r2, #40 @ 0x28 8016cbc: f843 1022 str.w r1, [r3, r2, lsl #2] xReturn = pdTRUE; 8016cc0: 2301 movs r3, #1 8016cc2: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; 8016cc4: 4b06 ldr r3, [pc, #24] @ (8016ce0 ) 8016cc6: 681a ldr r2, [r3, #0] 8016cc8: 68fb ldr r3, [r7, #12] 8016cca: 4413 add r3, r2 8016ccc: 33a8 adds r3, #168 @ 0xa8 8016cce: 2200 movs r2, #0 8016cd0: 701a strb r2, [r3, #0] } taskEXIT_CRITICAL(); 8016cd2: f001 f84f bl 8017d74 return xReturn; 8016cd6: 697b ldr r3, [r7, #20] } 8016cd8: 4618 mov r0, r3 8016cda: 3718 adds r7, #24 8016cdc: 46bd mov sp, r7 8016cde: bd80 pop {r7, pc} 8016ce0: 20002168 .word 0x20002168 8016ce4: e000ed04 .word 0xe000ed04 08016ce8 : BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t * pulPreviousNotificationValue ) { 8016ce8: b580 push {r7, lr} 8016cea: b08e sub sp, #56 @ 0x38 8016cec: af00 add r7, sp, #0 8016cee: 60f8 str r0, [r7, #12] 8016cf0: 60b9 str r1, [r7, #8] 8016cf2: 607a str r2, [r7, #4] 8016cf4: 70fb strb r3, [r7, #3] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 8016cf6: 2301 movs r3, #1 8016cf8: 637b str r3, [r7, #52] @ 0x34 uint8_t ucOriginalNotifyState; configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 8016cfa: 68bb ldr r3, [r7, #8] 8016cfc: 2b01 cmp r3, #1 8016cfe: d90b bls.n 8016d18 __asm volatile 8016d00: f04f 0350 mov.w r3, #80 @ 0x50 8016d04: f383 8811 msr BASEPRI, r3 8016d08: f3bf 8f6f isb sy 8016d0c: f3bf 8f4f dsb sy 8016d10: 623b str r3, [r7, #32] } 8016d12: bf00 nop 8016d14: bf00 nop 8016d16: e7fd b.n 8016d14 configASSERT( xTaskToNotify ); 8016d18: 68fb ldr r3, [r7, #12] 8016d1a: 2b00 cmp r3, #0 8016d1c: d10b bne.n 8016d36 __asm volatile 8016d1e: f04f 0350 mov.w r3, #80 @ 0x50 8016d22: f383 8811 msr BASEPRI, r3 8016d26: f3bf 8f6f isb sy 8016d2a: f3bf 8f4f dsb sy 8016d2e: 61fb str r3, [r7, #28] } 8016d30: bf00 nop 8016d32: bf00 nop 8016d34: e7fd b.n 8016d32 pxTCB = xTaskToNotify; 8016d36: 68fb ldr r3, [r7, #12] 8016d38: 633b str r3, [r7, #48] @ 0x30 taskENTER_CRITICAL(); 8016d3a: f000 ffe9 bl 8017d10 { if( pulPreviousNotificationValue != NULL ) 8016d3e: 6c3b ldr r3, [r7, #64] @ 0x40 8016d40: 2b00 cmp r3, #0 8016d42: d006 beq.n 8016d52 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; 8016d44: 6b3b ldr r3, [r7, #48] @ 0x30 8016d46: 68ba ldr r2, [r7, #8] 8016d48: 3228 adds r2, #40 @ 0x28 8016d4a: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8016d4e: 6c3b ldr r3, [r7, #64] @ 0x40 8016d50: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; 8016d52: 6b3a ldr r2, [r7, #48] @ 0x30 8016d54: 68bb ldr r3, [r7, #8] 8016d56: 4413 add r3, r2 8016d58: 33a8 adds r3, #168 @ 0xa8 8016d5a: 781b ldrb r3, [r3, #0] 8016d5c: f887 302f strb.w r3, [r7, #47] @ 0x2f pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; 8016d60: 6b3a ldr r2, [r7, #48] @ 0x30 8016d62: 68bb ldr r3, [r7, #8] 8016d64: 4413 add r3, r2 8016d66: 33a8 adds r3, #168 @ 0xa8 8016d68: 2202 movs r2, #2 8016d6a: 701a strb r2, [r3, #0] switch( eAction ) 8016d6c: 78fb ldrb r3, [r7, #3] 8016d6e: 2b04 cmp r3, #4 8016d70: d83b bhi.n 8016dea 8016d72: a201 add r2, pc, #4 @ (adr r2, 8016d78 ) 8016d74: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016d78: 08016e0b .word 0x08016e0b 8016d7c: 08016d8d .word 0x08016d8d 8016d80: 08016da9 .word 0x08016da9 8016d84: 08016dc1 .word 0x08016dc1 8016d88: 08016dcf .word 0x08016dcf { case eSetBits: pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; 8016d8c: 6b3b ldr r3, [r7, #48] @ 0x30 8016d8e: 68ba ldr r2, [r7, #8] 8016d90: 3228 adds r2, #40 @ 0x28 8016d92: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8016d96: 687b ldr r3, [r7, #4] 8016d98: ea42 0103 orr.w r1, r2, r3 8016d9c: 6b3b ldr r3, [r7, #48] @ 0x30 8016d9e: 68ba ldr r2, [r7, #8] 8016da0: 3228 adds r2, #40 @ 0x28 8016da2: f843 1022 str.w r1, [r3, r2, lsl #2] break; 8016da6: e033 b.n 8016e10 case eIncrement: ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; 8016da8: 6b3b ldr r3, [r7, #48] @ 0x30 8016daa: 68ba ldr r2, [r7, #8] 8016dac: 3228 adds r2, #40 @ 0x28 8016dae: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8016db2: 1c59 adds r1, r3, #1 8016db4: 6b3b ldr r3, [r7, #48] @ 0x30 8016db6: 68ba ldr r2, [r7, #8] 8016db8: 3228 adds r2, #40 @ 0x28 8016dba: f843 1022 str.w r1, [r3, r2, lsl #2] break; 8016dbe: e027 b.n 8016e10 case eSetValueWithOverwrite: pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; 8016dc0: 6b3b ldr r3, [r7, #48] @ 0x30 8016dc2: 68ba ldr r2, [r7, #8] 8016dc4: 3228 adds r2, #40 @ 0x28 8016dc6: 6879 ldr r1, [r7, #4] 8016dc8: f843 1022 str.w r1, [r3, r2, lsl #2] break; 8016dcc: e020 b.n 8016e10 case eSetValueWithoutOverwrite: if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016dce: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8016dd2: 2b02 cmp r3, #2 8016dd4: d006 beq.n 8016de4 { pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; 8016dd6: 6b3b ldr r3, [r7, #48] @ 0x30 8016dd8: 68ba ldr r2, [r7, #8] 8016dda: 3228 adds r2, #40 @ 0x28 8016ddc: 6879 ldr r1, [r7, #4] 8016dde: f843 1022 str.w r1, [r3, r2, lsl #2] { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016de2: e015 b.n 8016e10 xReturn = pdFAIL; 8016de4: 2300 movs r3, #0 8016de6: 637b str r3, [r7, #52] @ 0x34 break; 8016de8: e012 b.n 8016e10 default: /* Should not get here if all enums are handled. * Artificially force an assert by testing a value the * compiler can't assume is const. */ configASSERT( xTickCount == ( TickType_t ) 0 ); 8016dea: 4b4e ldr r3, [pc, #312] @ (8016f24 ) 8016dec: 681b ldr r3, [r3, #0] 8016dee: 2b00 cmp r3, #0 8016df0: d00d beq.n 8016e0e __asm volatile 8016df2: f04f 0350 mov.w r3, #80 @ 0x50 8016df6: f383 8811 msr BASEPRI, r3 8016dfa: f3bf 8f6f isb sy 8016dfe: f3bf 8f4f dsb sy 8016e02: 61bb str r3, [r7, #24] } 8016e04: bf00 nop 8016e06: bf00 nop 8016e08: e7fd b.n 8016e06 break; 8016e0a: bf00 nop 8016e0c: e000 b.n 8016e10 break; 8016e0e: bf00 nop traceTASK_NOTIFY( uxIndexToNotify ); /* If the task is in the blocked state specifically to wait for a * notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8016e10: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8016e14: 2b01 cmp r3, #1 8016e16: d17d bne.n 8016f14 { listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 8016e18: 6b3b ldr r3, [r7, #48] @ 0x30 8016e1a: 695b ldr r3, [r3, #20] 8016e1c: 62bb str r3, [r7, #40] @ 0x28 8016e1e: 6b3b ldr r3, [r7, #48] @ 0x30 8016e20: 689b ldr r3, [r3, #8] 8016e22: 6b3a ldr r2, [r7, #48] @ 0x30 8016e24: 68d2 ldr r2, [r2, #12] 8016e26: 609a str r2, [r3, #8] 8016e28: 6b3b ldr r3, [r7, #48] @ 0x30 8016e2a: 68db ldr r3, [r3, #12] 8016e2c: 6b3a ldr r2, [r7, #48] @ 0x30 8016e2e: 6892 ldr r2, [r2, #8] 8016e30: 605a str r2, [r3, #4] 8016e32: 6abb ldr r3, [r7, #40] @ 0x28 8016e34: 685a ldr r2, [r3, #4] 8016e36: 6b3b ldr r3, [r7, #48] @ 0x30 8016e38: 3304 adds r3, #4 8016e3a: 429a cmp r2, r3 8016e3c: d103 bne.n 8016e46 8016e3e: 6b3b ldr r3, [r7, #48] @ 0x30 8016e40: 68da ldr r2, [r3, #12] 8016e42: 6abb ldr r3, [r7, #40] @ 0x28 8016e44: 605a str r2, [r3, #4] 8016e46: 6b3b ldr r3, [r7, #48] @ 0x30 8016e48: 2200 movs r2, #0 8016e4a: 615a str r2, [r3, #20] 8016e4c: 6abb ldr r3, [r7, #40] @ 0x28 8016e4e: 681b ldr r3, [r3, #0] 8016e50: 1e5a subs r2, r3, #1 8016e52: 6abb ldr r3, [r7, #40] @ 0x28 8016e54: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxTCB ); 8016e56: 6b3b ldr r3, [r7, #48] @ 0x30 8016e58: 6ada ldr r2, [r3, #44] @ 0x2c 8016e5a: 4b33 ldr r3, [pc, #204] @ (8016f28 ) 8016e5c: 681b ldr r3, [r3, #0] 8016e5e: 429a cmp r2, r3 8016e60: d903 bls.n 8016e6a 8016e62: 6b3b ldr r3, [r7, #48] @ 0x30 8016e64: 6adb ldr r3, [r3, #44] @ 0x2c 8016e66: 4a30 ldr r2, [pc, #192] @ (8016f28 ) 8016e68: 6013 str r3, [r2, #0] 8016e6a: 6b3b ldr r3, [r7, #48] @ 0x30 8016e6c: 6ada ldr r2, [r3, #44] @ 0x2c 8016e6e: 492f ldr r1, [pc, #188] @ (8016f2c ) 8016e70: 4613 mov r3, r2 8016e72: 009b lsls r3, r3, #2 8016e74: 4413 add r3, r2 8016e76: 009b lsls r3, r3, #2 8016e78: 440b add r3, r1 8016e7a: 3304 adds r3, #4 8016e7c: 681b ldr r3, [r3, #0] 8016e7e: 627b str r3, [r7, #36] @ 0x24 8016e80: 6b3b ldr r3, [r7, #48] @ 0x30 8016e82: 6a7a ldr r2, [r7, #36] @ 0x24 8016e84: 609a str r2, [r3, #8] 8016e86: 6a7b ldr r3, [r7, #36] @ 0x24 8016e88: 689a ldr r2, [r3, #8] 8016e8a: 6b3b ldr r3, [r7, #48] @ 0x30 8016e8c: 60da str r2, [r3, #12] 8016e8e: 6a7b ldr r3, [r7, #36] @ 0x24 8016e90: 689b ldr r3, [r3, #8] 8016e92: 6b3a ldr r2, [r7, #48] @ 0x30 8016e94: 3204 adds r2, #4 8016e96: 605a str r2, [r3, #4] 8016e98: 6b3b ldr r3, [r7, #48] @ 0x30 8016e9a: 1d1a adds r2, r3, #4 8016e9c: 6a7b ldr r3, [r7, #36] @ 0x24 8016e9e: 609a str r2, [r3, #8] 8016ea0: 6b3b ldr r3, [r7, #48] @ 0x30 8016ea2: 6ada ldr r2, [r3, #44] @ 0x2c 8016ea4: 4613 mov r3, r2 8016ea6: 009b lsls r3, r3, #2 8016ea8: 4413 add r3, r2 8016eaa: 009b lsls r3, r3, #2 8016eac: 4a1f ldr r2, [pc, #124] @ (8016f2c ) 8016eae: 441a add r2, r3 8016eb0: 6b3b ldr r3, [r7, #48] @ 0x30 8016eb2: 615a str r2, [r3, #20] 8016eb4: 6b3b ldr r3, [r7, #48] @ 0x30 8016eb6: 6ada ldr r2, [r3, #44] @ 0x2c 8016eb8: 491c ldr r1, [pc, #112] @ (8016f2c ) 8016eba: 4613 mov r3, r2 8016ebc: 009b lsls r3, r3, #2 8016ebe: 4413 add r3, r2 8016ec0: 009b lsls r3, r3, #2 8016ec2: 440b add r3, r1 8016ec4: 681b ldr r3, [r3, #0] 8016ec6: 1c59 adds r1, r3, #1 8016ec8: 4818 ldr r0, [pc, #96] @ (8016f2c ) 8016eca: 4613 mov r3, r2 8016ecc: 009b lsls r3, r3, #2 8016ece: 4413 add r3, r2 8016ed0: 009b lsls r3, r3, #2 8016ed2: 4403 add r3, r0 8016ed4: 6019 str r1, [r3, #0] /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8016ed6: 6b3b ldr r3, [r7, #48] @ 0x30 8016ed8: 6a9b ldr r3, [r3, #40] @ 0x28 8016eda: 2b00 cmp r3, #0 8016edc: d00b beq.n 8016ef6 __asm volatile 8016ede: f04f 0350 mov.w r3, #80 @ 0x50 8016ee2: f383 8811 msr BASEPRI, r3 8016ee6: f3bf 8f6f isb sy 8016eea: f3bf 8f4f dsb sy 8016eee: 617b str r3, [r7, #20] } 8016ef0: bf00 nop 8016ef2: bf00 nop 8016ef4: e7fd b.n 8016ef2 * earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016ef6: 6b3b ldr r3, [r7, #48] @ 0x30 8016ef8: 6ada ldr r2, [r3, #44] @ 0x2c 8016efa: 4b0d ldr r3, [pc, #52] @ (8016f30 ) 8016efc: 681b ldr r3, [r3, #0] 8016efe: 6adb ldr r3, [r3, #44] @ 0x2c 8016f00: 429a cmp r2, r3 8016f02: d907 bls.n 8016f14 { /* The notified task has a priority above the currently * executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016f04: 4b0b ldr r3, [pc, #44] @ (8016f34 ) 8016f06: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016f0a: 601a str r2, [r3, #0] 8016f0c: f3bf 8f4f dsb sy 8016f10: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016f14: f000 ff2e bl 8017d74 return xReturn; 8016f18: 6b7b ldr r3, [r7, #52] @ 0x34 } 8016f1a: 4618 mov r0, r3 8016f1c: 3738 adds r7, #56 @ 0x38 8016f1e: 46bd mov sp, r7 8016f20: bd80 pop {r7, pc} 8016f22: bf00 nop 8016f24: 20002640 .word 0x20002640 8016f28: 20002644 .word 0x20002644 8016f2c: 2000216c .word 0x2000216c 8016f30: 20002168 .word 0x20002168 8016f34: e000ed04 .word 0xe000ed04 08016f38 : UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t * pulPreviousNotificationValue, BaseType_t * pxHigherPriorityTaskWoken ) { 8016f38: b580 push {r7, lr} 8016f3a: b092 sub sp, #72 @ 0x48 8016f3c: af00 add r7, sp, #0 8016f3e: 60f8 str r0, [r7, #12] 8016f40: 60b9 str r1, [r7, #8] 8016f42: 607a str r2, [r7, #4] 8016f44: 70fb strb r3, [r7, #3] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8016f46: 2301 movs r3, #1 8016f48: 647b str r3, [r7, #68] @ 0x44 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016f4a: 68fb ldr r3, [r7, #12] 8016f4c: 2b00 cmp r3, #0 8016f4e: d10b bne.n 8016f68 __asm volatile 8016f50: f04f 0350 mov.w r3, #80 @ 0x50 8016f54: f383 8811 msr BASEPRI, r3 8016f58: f3bf 8f6f isb sy 8016f5c: f3bf 8f4f dsb sy 8016f60: 62bb str r3, [r7, #40] @ 0x28 } 8016f62: bf00 nop 8016f64: bf00 nop 8016f66: e7fd b.n 8016f64 configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 8016f68: 68bb ldr r3, [r7, #8] 8016f6a: 2b01 cmp r3, #1 8016f6c: d90b bls.n 8016f86 __asm volatile 8016f6e: f04f 0350 mov.w r3, #80 @ 0x50 8016f72: f383 8811 msr BASEPRI, r3 8016f76: f3bf 8f6f isb sy 8016f7a: f3bf 8f4f dsb sy 8016f7e: 627b str r3, [r7, #36] @ 0x24 } 8016f80: bf00 nop 8016f82: bf00 nop 8016f84: e7fd b.n 8016f82 * below the maximum system call interrupt priority. FreeRTOS maintains a * separate interrupt safe API to ensure interrupt entry is as fast and as * simple as possible. More information (albeit Cortex-M specific) is * provided on the following link: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8016f86: f000 ffa9 bl 8017edc pxTCB = xTaskToNotify; 8016f8a: 68fb ldr r3, [r7, #12] 8016f8c: 643b str r3, [r7, #64] @ 0x40 __asm volatile 8016f8e: f3ef 8211 mrs r2, BASEPRI 8016f92: f04f 0350 mov.w r3, #80 @ 0x50 8016f96: f383 8811 msr BASEPRI, r3 8016f9a: f3bf 8f6f isb sy 8016f9e: f3bf 8f4f dsb sy 8016fa2: 623a str r2, [r7, #32] 8016fa4: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 8016fa6: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8016fa8: 63fb str r3, [r7, #60] @ 0x3c { if( pulPreviousNotificationValue != NULL ) 8016faa: 6d3b ldr r3, [r7, #80] @ 0x50 8016fac: 2b00 cmp r3, #0 8016fae: d006 beq.n 8016fbe { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; 8016fb0: 6c3b ldr r3, [r7, #64] @ 0x40 8016fb2: 68ba ldr r2, [r7, #8] 8016fb4: 3228 adds r2, #40 @ 0x28 8016fb6: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8016fba: 6d3b ldr r3, [r7, #80] @ 0x50 8016fbc: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; 8016fbe: 6c3a ldr r2, [r7, #64] @ 0x40 8016fc0: 68bb ldr r3, [r7, #8] 8016fc2: 4413 add r3, r2 8016fc4: 33a8 adds r3, #168 @ 0xa8 8016fc6: 781b ldrb r3, [r3, #0] 8016fc8: f887 303b strb.w r3, [r7, #59] @ 0x3b pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; 8016fcc: 6c3a ldr r2, [r7, #64] @ 0x40 8016fce: 68bb ldr r3, [r7, #8] 8016fd0: 4413 add r3, r2 8016fd2: 33a8 adds r3, #168 @ 0xa8 8016fd4: 2202 movs r2, #2 8016fd6: 701a strb r2, [r3, #0] switch( eAction ) 8016fd8: 78fb ldrb r3, [r7, #3] 8016fda: 2b04 cmp r3, #4 8016fdc: d83b bhi.n 8017056 8016fde: a201 add r2, pc, #4 @ (adr r2, 8016fe4 ) 8016fe0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016fe4: 08017077 .word 0x08017077 8016fe8: 08016ff9 .word 0x08016ff9 8016fec: 08017015 .word 0x08017015 8016ff0: 0801702d .word 0x0801702d 8016ff4: 0801703b .word 0x0801703b { case eSetBits: pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; 8016ff8: 6c3b ldr r3, [r7, #64] @ 0x40 8016ffa: 68ba ldr r2, [r7, #8] 8016ffc: 3228 adds r2, #40 @ 0x28 8016ffe: f853 2022 ldr.w r2, [r3, r2, lsl #2] 8017002: 687b ldr r3, [r7, #4] 8017004: ea42 0103 orr.w r1, r2, r3 8017008: 6c3b ldr r3, [r7, #64] @ 0x40 801700a: 68ba ldr r2, [r7, #8] 801700c: 3228 adds r2, #40 @ 0x28 801700e: f843 1022 str.w r1, [r3, r2, lsl #2] break; 8017012: e033 b.n 801707c case eIncrement: ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; 8017014: 6c3b ldr r3, [r7, #64] @ 0x40 8017016: 68ba ldr r2, [r7, #8] 8017018: 3228 adds r2, #40 @ 0x28 801701a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 801701e: 1c59 adds r1, r3, #1 8017020: 6c3b ldr r3, [r7, #64] @ 0x40 8017022: 68ba ldr r2, [r7, #8] 8017024: 3228 adds r2, #40 @ 0x28 8017026: f843 1022 str.w r1, [r3, r2, lsl #2] break; 801702a: e027 b.n 801707c case eSetValueWithOverwrite: pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; 801702c: 6c3b ldr r3, [r7, #64] @ 0x40 801702e: 68ba ldr r2, [r7, #8] 8017030: 3228 adds r2, #40 @ 0x28 8017032: 6879 ldr r1, [r7, #4] 8017034: f843 1022 str.w r1, [r3, r2, lsl #2] break; 8017038: e020 b.n 801707c case eSetValueWithoutOverwrite: if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 801703a: f897 303b ldrb.w r3, [r7, #59] @ 0x3b 801703e: 2b02 cmp r3, #2 8017040: d006 beq.n 8017050 { pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; 8017042: 6c3b ldr r3, [r7, #64] @ 0x40 8017044: 68ba ldr r2, [r7, #8] 8017046: 3228 adds r2, #40 @ 0x28 8017048: 6879 ldr r1, [r7, #4] 801704a: f843 1022 str.w r1, [r3, r2, lsl #2] { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 801704e: e015 b.n 801707c xReturn = pdFAIL; 8017050: 2300 movs r3, #0 8017052: 647b str r3, [r7, #68] @ 0x44 break; 8017054: e012 b.n 801707c default: /* Should not get here if all enums are handled. * Artificially force an assert by testing a value the * compiler can't assume is const. */ configASSERT( xTickCount == ( TickType_t ) 0 ); 8017056: 4b61 ldr r3, [pc, #388] @ (80171dc ) 8017058: 681b ldr r3, [r3, #0] 801705a: 2b00 cmp r3, #0 801705c: d00d beq.n 801707a __asm volatile 801705e: f04f 0350 mov.w r3, #80 @ 0x50 8017062: f383 8811 msr BASEPRI, r3 8017066: f3bf 8f6f isb sy 801706a: f3bf 8f4f dsb sy 801706e: 61bb str r3, [r7, #24] } 8017070: bf00 nop 8017072: bf00 nop 8017074: e7fd b.n 8017072 break; 8017076: bf00 nop 8017078: e000 b.n 801707c break; 801707a: bf00 nop traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ); /* If the task is in the blocked state specifically to wait for a * notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 801707c: f897 303b ldrb.w r3, [r7, #59] @ 0x3b 8017080: 2b01 cmp r3, #1 8017082: f040 80a0 bne.w 80171c6 { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8017086: 6c3b ldr r3, [r7, #64] @ 0x40 8017088: 6a9b ldr r3, [r3, #40] @ 0x28 801708a: 2b00 cmp r3, #0 801708c: d00b beq.n 80170a6 __asm volatile 801708e: f04f 0350 mov.w r3, #80 @ 0x50 8017092: f383 8811 msr BASEPRI, r3 8017096: f3bf 8f6f isb sy 801709a: f3bf 8f4f dsb sy 801709e: 617b str r3, [r7, #20] } 80170a0: bf00 nop 80170a2: bf00 nop 80170a4: e7fd b.n 80170a2 if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 80170a6: 4b4e ldr r3, [pc, #312] @ (80171e0 ) 80170a8: 681b ldr r3, [r3, #0] 80170aa: 2b00 cmp r3, #0 80170ac: d15f bne.n 801716e { listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 80170ae: 6c3b ldr r3, [r7, #64] @ 0x40 80170b0: 695b ldr r3, [r3, #20] 80170b2: 633b str r3, [r7, #48] @ 0x30 80170b4: 6c3b ldr r3, [r7, #64] @ 0x40 80170b6: 689b ldr r3, [r3, #8] 80170b8: 6c3a ldr r2, [r7, #64] @ 0x40 80170ba: 68d2 ldr r2, [r2, #12] 80170bc: 609a str r2, [r3, #8] 80170be: 6c3b ldr r3, [r7, #64] @ 0x40 80170c0: 68db ldr r3, [r3, #12] 80170c2: 6c3a ldr r2, [r7, #64] @ 0x40 80170c4: 6892 ldr r2, [r2, #8] 80170c6: 605a str r2, [r3, #4] 80170c8: 6b3b ldr r3, [r7, #48] @ 0x30 80170ca: 685a ldr r2, [r3, #4] 80170cc: 6c3b ldr r3, [r7, #64] @ 0x40 80170ce: 3304 adds r3, #4 80170d0: 429a cmp r2, r3 80170d2: d103 bne.n 80170dc 80170d4: 6c3b ldr r3, [r7, #64] @ 0x40 80170d6: 68da ldr r2, [r3, #12] 80170d8: 6b3b ldr r3, [r7, #48] @ 0x30 80170da: 605a str r2, [r3, #4] 80170dc: 6c3b ldr r3, [r7, #64] @ 0x40 80170de: 2200 movs r2, #0 80170e0: 615a str r2, [r3, #20] 80170e2: 6b3b ldr r3, [r7, #48] @ 0x30 80170e4: 681b ldr r3, [r3, #0] 80170e6: 1e5a subs r2, r3, #1 80170e8: 6b3b ldr r3, [r7, #48] @ 0x30 80170ea: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxTCB ); 80170ec: 6c3b ldr r3, [r7, #64] @ 0x40 80170ee: 6ada ldr r2, [r3, #44] @ 0x2c 80170f0: 4b3c ldr r3, [pc, #240] @ (80171e4 ) 80170f2: 681b ldr r3, [r3, #0] 80170f4: 429a cmp r2, r3 80170f6: d903 bls.n 8017100 80170f8: 6c3b ldr r3, [r7, #64] @ 0x40 80170fa: 6adb ldr r3, [r3, #44] @ 0x2c 80170fc: 4a39 ldr r2, [pc, #228] @ (80171e4 ) 80170fe: 6013 str r3, [r2, #0] 8017100: 6c3b ldr r3, [r7, #64] @ 0x40 8017102: 6ada ldr r2, [r3, #44] @ 0x2c 8017104: 4938 ldr r1, [pc, #224] @ (80171e8 ) 8017106: 4613 mov r3, r2 8017108: 009b lsls r3, r3, #2 801710a: 4413 add r3, r2 801710c: 009b lsls r3, r3, #2 801710e: 440b add r3, r1 8017110: 3304 adds r3, #4 8017112: 681b ldr r3, [r3, #0] 8017114: 62fb str r3, [r7, #44] @ 0x2c 8017116: 6c3b ldr r3, [r7, #64] @ 0x40 8017118: 6afa ldr r2, [r7, #44] @ 0x2c 801711a: 609a str r2, [r3, #8] 801711c: 6afb ldr r3, [r7, #44] @ 0x2c 801711e: 689a ldr r2, [r3, #8] 8017120: 6c3b ldr r3, [r7, #64] @ 0x40 8017122: 60da str r2, [r3, #12] 8017124: 6afb ldr r3, [r7, #44] @ 0x2c 8017126: 689b ldr r3, [r3, #8] 8017128: 6c3a ldr r2, [r7, #64] @ 0x40 801712a: 3204 adds r2, #4 801712c: 605a str r2, [r3, #4] 801712e: 6c3b ldr r3, [r7, #64] @ 0x40 8017130: 1d1a adds r2, r3, #4 8017132: 6afb ldr r3, [r7, #44] @ 0x2c 8017134: 609a str r2, [r3, #8] 8017136: 6c3b ldr r3, [r7, #64] @ 0x40 8017138: 6ada ldr r2, [r3, #44] @ 0x2c 801713a: 4613 mov r3, r2 801713c: 009b lsls r3, r3, #2 801713e: 4413 add r3, r2 8017140: 009b lsls r3, r3, #2 8017142: 4a29 ldr r2, [pc, #164] @ (80171e8 ) 8017144: 441a add r2, r3 8017146: 6c3b ldr r3, [r7, #64] @ 0x40 8017148: 615a str r2, [r3, #20] 801714a: 6c3b ldr r3, [r7, #64] @ 0x40 801714c: 6ada ldr r2, [r3, #44] @ 0x2c 801714e: 4926 ldr r1, [pc, #152] @ (80171e8 ) 8017150: 4613 mov r3, r2 8017152: 009b lsls r3, r3, #2 8017154: 4413 add r3, r2 8017156: 009b lsls r3, r3, #2 8017158: 440b add r3, r1 801715a: 681b ldr r3, [r3, #0] 801715c: 1c59 adds r1, r3, #1 801715e: 4822 ldr r0, [pc, #136] @ (80171e8 ) 8017160: 4613 mov r3, r2 8017162: 009b lsls r3, r3, #2 8017164: 4413 add r3, r2 8017166: 009b lsls r3, r3, #2 8017168: 4403 add r3, r0 801716a: 6019 str r1, [r3, #0] 801716c: e01b b.n 80171a6 } else { /* The delayed and ready lists cannot be accessed, so hold * this task pending until the scheduler is resumed. */ listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 801716e: 4b1f ldr r3, [pc, #124] @ (80171ec ) 8017170: 685b ldr r3, [r3, #4] 8017172: 637b str r3, [r7, #52] @ 0x34 8017174: 6c3b ldr r3, [r7, #64] @ 0x40 8017176: 6b7a ldr r2, [r7, #52] @ 0x34 8017178: 61da str r2, [r3, #28] 801717a: 6b7b ldr r3, [r7, #52] @ 0x34 801717c: 689a ldr r2, [r3, #8] 801717e: 6c3b ldr r3, [r7, #64] @ 0x40 8017180: 621a str r2, [r3, #32] 8017182: 6b7b ldr r3, [r7, #52] @ 0x34 8017184: 689b ldr r3, [r3, #8] 8017186: 6c3a ldr r2, [r7, #64] @ 0x40 8017188: 3218 adds r2, #24 801718a: 605a str r2, [r3, #4] 801718c: 6c3b ldr r3, [r7, #64] @ 0x40 801718e: f103 0218 add.w r2, r3, #24 8017192: 6b7b ldr r3, [r7, #52] @ 0x34 8017194: 609a str r2, [r3, #8] 8017196: 6c3b ldr r3, [r7, #64] @ 0x40 8017198: 4a14 ldr r2, [pc, #80] @ (80171ec ) 801719a: 629a str r2, [r3, #40] @ 0x28 801719c: 4b13 ldr r3, [pc, #76] @ (80171ec ) 801719e: 681b ldr r3, [r3, #0] 80171a0: 3301 adds r3, #1 80171a2: 4a12 ldr r2, [pc, #72] @ (80171ec ) 80171a4: 6013 str r3, [r2, #0] } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80171a6: 6c3b ldr r3, [r7, #64] @ 0x40 80171a8: 6ada ldr r2, [r3, #44] @ 0x2c 80171aa: 4b11 ldr r3, [pc, #68] @ (80171f0 ) 80171ac: 681b ldr r3, [r3, #0] 80171ae: 6adb ldr r3, [r3, #44] @ 0x2c 80171b0: 429a cmp r2, r3 80171b2: d908 bls.n 80171c6 { /* The notified task has a priority above the currently * executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80171b4: 6d7b ldr r3, [r7, #84] @ 0x54 80171b6: 2b00 cmp r3, #0 80171b8: d002 beq.n 80171c0 { *pxHigherPriorityTaskWoken = pdTRUE; 80171ba: 6d7b ldr r3, [r7, #84] @ 0x54 80171bc: 2201 movs r2, #1 80171be: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not * using the "xHigherPriorityTaskWoken" parameter to an ISR * safe FreeRTOS function. */ xYieldPending = pdTRUE; 80171c0: 4b0c ldr r3, [pc, #48] @ (80171f4 ) 80171c2: 2201 movs r2, #1 80171c4: 601a str r2, [r3, #0] 80171c6: 6bfb ldr r3, [r7, #60] @ 0x3c 80171c8: 613b str r3, [r7, #16] __asm volatile 80171ca: 693b ldr r3, [r7, #16] 80171cc: f383 8811 msr BASEPRI, r3 } 80171d0: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 80171d2: 6c7b ldr r3, [r7, #68] @ 0x44 } 80171d4: 4618 mov r0, r3 80171d6: 3748 adds r7, #72 @ 0x48 80171d8: 46bd mov sp, r7 80171da: bd80 pop {r7, pc} 80171dc: 20002640 .word 0x20002640 80171e0: 20002664 .word 0x20002664 80171e4: 20002644 .word 0x20002644 80171e8: 2000216c .word 0x2000216c 80171ec: 200025fc .word 0x200025fc 80171f0: 20002168 .word 0x20002168 80171f4: 20002650 .word 0x20002650 080171f8 : #if ( configUSE_TASK_NOTIFICATIONS == 1 ) void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, BaseType_t * pxHigherPriorityTaskWoken ) { 80171f8: b580 push {r7, lr} 80171fa: b090 sub sp, #64 @ 0x40 80171fc: af00 add r7, sp, #0 80171fe: 60f8 str r0, [r7, #12] 8017200: 60b9 str r1, [r7, #8] 8017202: 607a str r2, [r7, #4] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8017204: 68fb ldr r3, [r7, #12] 8017206: 2b00 cmp r3, #0 8017208: d10b bne.n 8017222 __asm volatile 801720a: f04f 0350 mov.w r3, #80 @ 0x50 801720e: f383 8811 msr BASEPRI, r3 8017212: f3bf 8f6f isb sy 8017216: f3bf 8f4f dsb sy 801721a: 627b str r3, [r7, #36] @ 0x24 } 801721c: bf00 nop 801721e: bf00 nop 8017220: e7fd b.n 801721e configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); 8017222: 68bb ldr r3, [r7, #8] 8017224: 2b01 cmp r3, #1 8017226: d90b bls.n 8017240 __asm volatile 8017228: f04f 0350 mov.w r3, #80 @ 0x50 801722c: f383 8811 msr BASEPRI, r3 8017230: f3bf 8f6f isb sy 8017234: f3bf 8f4f dsb sy 8017238: 623b str r3, [r7, #32] } 801723a: bf00 nop 801723c: bf00 nop 801723e: e7fd b.n 801723c * below the maximum system call interrupt priority. FreeRTOS maintains a * separate interrupt safe API to ensure interrupt entry is as fast and as * simple as possible. More information (albeit Cortex-M specific) is * provided on the following link: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8017240: f000 fe4c bl 8017edc pxTCB = xTaskToNotify; 8017244: 68fb ldr r3, [r7, #12] 8017246: 63fb str r3, [r7, #60] @ 0x3c __asm volatile 8017248: f3ef 8211 mrs r2, BASEPRI 801724c: f04f 0350 mov.w r3, #80 @ 0x50 8017250: f383 8811 msr BASEPRI, r3 8017254: f3bf 8f6f isb sy 8017258: f3bf 8f4f dsb sy 801725c: 61fa str r2, [r7, #28] 801725e: 61bb str r3, [r7, #24] return ulOriginalBASEPRI; 8017260: 69fb ldr r3, [r7, #28] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8017262: 63bb str r3, [r7, #56] @ 0x38 { ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; 8017264: 6bfa ldr r2, [r7, #60] @ 0x3c 8017266: 68bb ldr r3, [r7, #8] 8017268: 4413 add r3, r2 801726a: 33a8 adds r3, #168 @ 0xa8 801726c: 781b ldrb r3, [r3, #0] 801726e: f887 3037 strb.w r3, [r7, #55] @ 0x37 pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; 8017272: 6bfa ldr r2, [r7, #60] @ 0x3c 8017274: 68bb ldr r3, [r7, #8] 8017276: 4413 add r3, r2 8017278: 33a8 adds r3, #168 @ 0xa8 801727a: 2202 movs r2, #2 801727c: 701a strb r2, [r3, #0] /* 'Giving' is equivalent to incrementing a count in a counting * semaphore. */ ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; 801727e: 6bfb ldr r3, [r7, #60] @ 0x3c 8017280: 68ba ldr r2, [r7, #8] 8017282: 3228 adds r2, #40 @ 0x28 8017284: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8017288: 1c59 adds r1, r3, #1 801728a: 6bfb ldr r3, [r7, #60] @ 0x3c 801728c: 68ba ldr r2, [r7, #8] 801728e: 3228 adds r2, #40 @ 0x28 8017290: f843 1022 str.w r1, [r3, r2, lsl #2] traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ); /* If the task is in the blocked state specifically to wait for a * notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8017294: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8017298: 2b01 cmp r3, #1 801729a: f040 80a0 bne.w 80173de { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 801729e: 6bfb ldr r3, [r7, #60] @ 0x3c 80172a0: 6a9b ldr r3, [r3, #40] @ 0x28 80172a2: 2b00 cmp r3, #0 80172a4: d00b beq.n 80172be __asm volatile 80172a6: f04f 0350 mov.w r3, #80 @ 0x50 80172aa: f383 8811 msr BASEPRI, r3 80172ae: f3bf 8f6f isb sy 80172b2: f3bf 8f4f dsb sy 80172b6: 617b str r3, [r7, #20] } 80172b8: bf00 nop 80172ba: bf00 nop 80172bc: e7fd b.n 80172ba if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) 80172be: 4b4d ldr r3, [pc, #308] @ (80173f4 ) 80172c0: 681b ldr r3, [r3, #0] 80172c2: 2b00 cmp r3, #0 80172c4: d15f bne.n 8017386 { listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); 80172c6: 6bfb ldr r3, [r7, #60] @ 0x3c 80172c8: 695b ldr r3, [r3, #20] 80172ca: 62fb str r3, [r7, #44] @ 0x2c 80172cc: 6bfb ldr r3, [r7, #60] @ 0x3c 80172ce: 689b ldr r3, [r3, #8] 80172d0: 6bfa ldr r2, [r7, #60] @ 0x3c 80172d2: 68d2 ldr r2, [r2, #12] 80172d4: 609a str r2, [r3, #8] 80172d6: 6bfb ldr r3, [r7, #60] @ 0x3c 80172d8: 68db ldr r3, [r3, #12] 80172da: 6bfa ldr r2, [r7, #60] @ 0x3c 80172dc: 6892 ldr r2, [r2, #8] 80172de: 605a str r2, [r3, #4] 80172e0: 6afb ldr r3, [r7, #44] @ 0x2c 80172e2: 685a ldr r2, [r3, #4] 80172e4: 6bfb ldr r3, [r7, #60] @ 0x3c 80172e6: 3304 adds r3, #4 80172e8: 429a cmp r2, r3 80172ea: d103 bne.n 80172f4 80172ec: 6bfb ldr r3, [r7, #60] @ 0x3c 80172ee: 68da ldr r2, [r3, #12] 80172f0: 6afb ldr r3, [r7, #44] @ 0x2c 80172f2: 605a str r2, [r3, #4] 80172f4: 6bfb ldr r3, [r7, #60] @ 0x3c 80172f6: 2200 movs r2, #0 80172f8: 615a str r2, [r3, #20] 80172fa: 6afb ldr r3, [r7, #44] @ 0x2c 80172fc: 681b ldr r3, [r3, #0] 80172fe: 1e5a subs r2, r3, #1 8017300: 6afb ldr r3, [r7, #44] @ 0x2c 8017302: 601a str r2, [r3, #0] prvAddTaskToReadyList( pxTCB ); 8017304: 6bfb ldr r3, [r7, #60] @ 0x3c 8017306: 6ada ldr r2, [r3, #44] @ 0x2c 8017308: 4b3b ldr r3, [pc, #236] @ (80173f8 ) 801730a: 681b ldr r3, [r3, #0] 801730c: 429a cmp r2, r3 801730e: d903 bls.n 8017318 8017310: 6bfb ldr r3, [r7, #60] @ 0x3c 8017312: 6adb ldr r3, [r3, #44] @ 0x2c 8017314: 4a38 ldr r2, [pc, #224] @ (80173f8 ) 8017316: 6013 str r3, [r2, #0] 8017318: 6bfb ldr r3, [r7, #60] @ 0x3c 801731a: 6ada ldr r2, [r3, #44] @ 0x2c 801731c: 4937 ldr r1, [pc, #220] @ (80173fc ) 801731e: 4613 mov r3, r2 8017320: 009b lsls r3, r3, #2 8017322: 4413 add r3, r2 8017324: 009b lsls r3, r3, #2 8017326: 440b add r3, r1 8017328: 3304 adds r3, #4 801732a: 681b ldr r3, [r3, #0] 801732c: 62bb str r3, [r7, #40] @ 0x28 801732e: 6bfb ldr r3, [r7, #60] @ 0x3c 8017330: 6aba ldr r2, [r7, #40] @ 0x28 8017332: 609a str r2, [r3, #8] 8017334: 6abb ldr r3, [r7, #40] @ 0x28 8017336: 689a ldr r2, [r3, #8] 8017338: 6bfb ldr r3, [r7, #60] @ 0x3c 801733a: 60da str r2, [r3, #12] 801733c: 6abb ldr r3, [r7, #40] @ 0x28 801733e: 689b ldr r3, [r3, #8] 8017340: 6bfa ldr r2, [r7, #60] @ 0x3c 8017342: 3204 adds r2, #4 8017344: 605a str r2, [r3, #4] 8017346: 6bfb ldr r3, [r7, #60] @ 0x3c 8017348: 1d1a adds r2, r3, #4 801734a: 6abb ldr r3, [r7, #40] @ 0x28 801734c: 609a str r2, [r3, #8] 801734e: 6bfb ldr r3, [r7, #60] @ 0x3c 8017350: 6ada ldr r2, [r3, #44] @ 0x2c 8017352: 4613 mov r3, r2 8017354: 009b lsls r3, r3, #2 8017356: 4413 add r3, r2 8017358: 009b lsls r3, r3, #2 801735a: 4a28 ldr r2, [pc, #160] @ (80173fc ) 801735c: 441a add r2, r3 801735e: 6bfb ldr r3, [r7, #60] @ 0x3c 8017360: 615a str r2, [r3, #20] 8017362: 6bfb ldr r3, [r7, #60] @ 0x3c 8017364: 6ada ldr r2, [r3, #44] @ 0x2c 8017366: 4925 ldr r1, [pc, #148] @ (80173fc ) 8017368: 4613 mov r3, r2 801736a: 009b lsls r3, r3, #2 801736c: 4413 add r3, r2 801736e: 009b lsls r3, r3, #2 8017370: 440b add r3, r1 8017372: 681b ldr r3, [r3, #0] 8017374: 1c59 adds r1, r3, #1 8017376: 4821 ldr r0, [pc, #132] @ (80173fc ) 8017378: 4613 mov r3, r2 801737a: 009b lsls r3, r3, #2 801737c: 4413 add r3, r2 801737e: 009b lsls r3, r3, #2 8017380: 4403 add r3, r0 8017382: 6019 str r1, [r3, #0] 8017384: e01b b.n 80173be } else { /* The delayed and ready lists cannot be accessed, so hold * this task pending until the scheduler is resumed. */ listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 8017386: 4b1e ldr r3, [pc, #120] @ (8017400 ) 8017388: 685b ldr r3, [r3, #4] 801738a: 633b str r3, [r7, #48] @ 0x30 801738c: 6bfb ldr r3, [r7, #60] @ 0x3c 801738e: 6b3a ldr r2, [r7, #48] @ 0x30 8017390: 61da str r2, [r3, #28] 8017392: 6b3b ldr r3, [r7, #48] @ 0x30 8017394: 689a ldr r2, [r3, #8] 8017396: 6bfb ldr r3, [r7, #60] @ 0x3c 8017398: 621a str r2, [r3, #32] 801739a: 6b3b ldr r3, [r7, #48] @ 0x30 801739c: 689b ldr r3, [r3, #8] 801739e: 6bfa ldr r2, [r7, #60] @ 0x3c 80173a0: 3218 adds r2, #24 80173a2: 605a str r2, [r3, #4] 80173a4: 6bfb ldr r3, [r7, #60] @ 0x3c 80173a6: f103 0218 add.w r2, r3, #24 80173aa: 6b3b ldr r3, [r7, #48] @ 0x30 80173ac: 609a str r2, [r3, #8] 80173ae: 6bfb ldr r3, [r7, #60] @ 0x3c 80173b0: 4a13 ldr r2, [pc, #76] @ (8017400 ) 80173b2: 629a str r2, [r3, #40] @ 0x28 80173b4: 4b12 ldr r3, [pc, #72] @ (8017400 ) 80173b6: 681b ldr r3, [r3, #0] 80173b8: 3301 adds r3, #1 80173ba: 4a11 ldr r2, [pc, #68] @ (8017400 ) 80173bc: 6013 str r3, [r2, #0] } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80173be: 6bfb ldr r3, [r7, #60] @ 0x3c 80173c0: 6ada ldr r2, [r3, #44] @ 0x2c 80173c2: 4b10 ldr r3, [pc, #64] @ (8017404 ) 80173c4: 681b ldr r3, [r3, #0] 80173c6: 6adb ldr r3, [r3, #44] @ 0x2c 80173c8: 429a cmp r2, r3 80173ca: d908 bls.n 80173de { /* The notified task has a priority above the currently * executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80173cc: 687b ldr r3, [r7, #4] 80173ce: 2b00 cmp r3, #0 80173d0: d002 beq.n 80173d8 { *pxHigherPriorityTaskWoken = pdTRUE; 80173d2: 687b ldr r3, [r7, #4] 80173d4: 2201 movs r2, #1 80173d6: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not * using the "xHigherPriorityTaskWoken" parameter in an ISR * safe FreeRTOS function. */ xYieldPending = pdTRUE; 80173d8: 4b0b ldr r3, [pc, #44] @ (8017408 ) 80173da: 2201 movs r2, #1 80173dc: 601a str r2, [r3, #0] 80173de: 6bbb ldr r3, [r7, #56] @ 0x38 80173e0: 613b str r3, [r7, #16] __asm volatile 80173e2: 693b ldr r3, [r7, #16] 80173e4: f383 8811 msr BASEPRI, r3 } 80173e8: bf00 nop mtCOVERAGE_TEST_MARKER(); } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); } 80173ea: bf00 nop 80173ec: 3740 adds r7, #64 @ 0x40 80173ee: 46bd mov sp, r7 80173f0: bd80 pop {r7, pc} 80173f2: bf00 nop 80173f4: 20002664 .word 0x20002664 80173f8: 20002644 .word 0x20002644 80173fc: 2000216c .word 0x2000216c 8017400: 200025fc .word 0x200025fc 8017404: 20002168 .word 0x20002168 8017408: 20002650 .word 0x20002650 0801740c : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 801740c: b580 push {r7, lr} 801740e: b086 sub sp, #24 8017410: af00 add r7, sp, #0 8017412: 6078 str r0, [r7, #4] 8017414: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8017416: 4b2e ldr r3, [pc, #184] @ (80174d0 ) 8017418: 681b ldr r3, [r3, #0] 801741a: 617b str r3, [r7, #20] } #endif /* Remove the task from the ready list before adding it to the blocked list * as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 801741c: 4b2d ldr r3, [pc, #180] @ (80174d4 ) 801741e: 681b ldr r3, [r3, #0] 8017420: 3304 adds r3, #4 8017422: 4618 mov r0, r3 8017424: f7fc fffa bl 801441c mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8017428: 687b ldr r3, [r7, #4] 801742a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801742e: d124 bne.n 801747a 8017430: 683b ldr r3, [r7, #0] 8017432: 2b00 cmp r3, #0 8017434: d021 beq.n 801747a { /* Add the task to the suspended task list instead of a delayed task * list to ensure it is not woken by a timing event. It will block * indefinitely. */ listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8017436: 4b28 ldr r3, [pc, #160] @ (80174d8 ) 8017438: 685b ldr r3, [r3, #4] 801743a: 613b str r3, [r7, #16] 801743c: 4b25 ldr r3, [pc, #148] @ (80174d4 ) 801743e: 681b ldr r3, [r3, #0] 8017440: 693a ldr r2, [r7, #16] 8017442: 609a str r2, [r3, #8] 8017444: 4b23 ldr r3, [pc, #140] @ (80174d4 ) 8017446: 681b ldr r3, [r3, #0] 8017448: 693a ldr r2, [r7, #16] 801744a: 6892 ldr r2, [r2, #8] 801744c: 60da str r2, [r3, #12] 801744e: 4b21 ldr r3, [pc, #132] @ (80174d4 ) 8017450: 681a ldr r2, [r3, #0] 8017452: 693b ldr r3, [r7, #16] 8017454: 689b ldr r3, [r3, #8] 8017456: 3204 adds r2, #4 8017458: 605a str r2, [r3, #4] 801745a: 4b1e ldr r3, [pc, #120] @ (80174d4 ) 801745c: 681b ldr r3, [r3, #0] 801745e: 1d1a adds r2, r3, #4 8017460: 693b ldr r3, [r7, #16] 8017462: 609a str r2, [r3, #8] 8017464: 4b1b ldr r3, [pc, #108] @ (80174d4 ) 8017466: 681b ldr r3, [r3, #0] 8017468: 4a1b ldr r2, [pc, #108] @ (80174d8 ) 801746a: 615a str r2, [r3, #20] 801746c: 4b1a ldr r3, [pc, #104] @ (80174d8 ) 801746e: 681b ldr r3, [r3, #0] 8017470: 3301 adds r3, #1 8017472: 4a19 ldr r2, [pc, #100] @ (80174d8 ) 8017474: 6013 str r3, [r2, #0] 8017476: bf00 nop /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8017478: e026 b.n 80174c8 xTimeToWake = xConstTickCount + xTicksToWait; 801747a: 697a ldr r2, [r7, #20] 801747c: 687b ldr r3, [r7, #4] 801747e: 4413 add r3, r2 8017480: 60fb str r3, [r7, #12] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 8017482: 4b14 ldr r3, [pc, #80] @ (80174d4 ) 8017484: 681b ldr r3, [r3, #0] 8017486: 68fa ldr r2, [r7, #12] 8017488: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 801748a: 68fa ldr r2, [r7, #12] 801748c: 697b ldr r3, [r7, #20] 801748e: 429a cmp r2, r3 8017490: d209 bcs.n 80174a6 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8017492: 4b12 ldr r3, [pc, #72] @ (80174dc ) 8017494: 681a ldr r2, [r3, #0] 8017496: 4b0f ldr r3, [pc, #60] @ (80174d4 ) 8017498: 681b ldr r3, [r3, #0] 801749a: 3304 adds r3, #4 801749c: 4619 mov r1, r3 801749e: 4610 mov r0, r2 80174a0: f7fc ff83 bl 80143aa } 80174a4: e010 b.n 80174c8 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80174a6: 4b0e ldr r3, [pc, #56] @ (80174e0 ) 80174a8: 681a ldr r2, [r3, #0] 80174aa: 4b0a ldr r3, [pc, #40] @ (80174d4 ) 80174ac: 681b ldr r3, [r3, #0] 80174ae: 3304 adds r3, #4 80174b0: 4619 mov r1, r3 80174b2: 4610 mov r0, r2 80174b4: f7fc ff79 bl 80143aa if( xTimeToWake < xNextTaskUnblockTime ) 80174b8: 4b0a ldr r3, [pc, #40] @ (80174e4 ) 80174ba: 681b ldr r3, [r3, #0] 80174bc: 68fa ldr r2, [r7, #12] 80174be: 429a cmp r2, r3 80174c0: d202 bcs.n 80174c8 xNextTaskUnblockTime = xTimeToWake; 80174c2: 4a08 ldr r2, [pc, #32] @ (80174e4 ) 80174c4: 68fb ldr r3, [r7, #12] 80174c6: 6013 str r3, [r2, #0] } 80174c8: bf00 nop 80174ca: 3718 adds r7, #24 80174cc: 46bd mov sp, r7 80174ce: bd80 pop {r7, pc} 80174d0: 20002640 .word 0x20002640 80174d4: 20002168 .word 0x20002168 80174d8: 20002628 .word 0x20002628 80174dc: 200025f8 .word 0x200025f8 80174e0: 200025f4 .word 0x200025f4 80174e4: 2000265c .word 0x2000265c 080174e8 : TimerCallbackFunction_t pxCallbackFunction, Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 80174e8: b580 push {r7, lr} 80174ea: b08a sub sp, #40 @ 0x28 80174ec: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 80174ee: 2300 movs r3, #0 80174f0: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if * configUSE_TIMERS is set to 1. Check that the infrastructure used by the * timer service task has been created/initialised. If timers have already * been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 80174f2: f000 fa81 bl 80179f8 if( xTimerQueue != NULL ) 80174f6: 4b1d ldr r3, [pc, #116] @ (801756c ) 80174f8: 681b ldr r3, [r3, #0] 80174fa: 2b00 cmp r3, #0 80174fc: d021 beq.n 8017542 { #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t * pxTimerTaskTCBBuffer = NULL; 80174fe: 2300 movs r3, #0 8017500: 60fb str r3, [r7, #12] StackType_t * pxTimerTaskStackBuffer = NULL; 8017502: 2300 movs r3, #0 8017504: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 8017506: 1d3a adds r2, r7, #4 8017508: f107 0108 add.w r1, r7, #8 801750c: f107 030c add.w r3, r7, #12 8017510: 4618 mov r0, r3 8017512: f7fc ff03 bl 801431c xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 8017516: 6879 ldr r1, [r7, #4] 8017518: 68bb ldr r3, [r7, #8] 801751a: 68fa ldr r2, [r7, #12] 801751c: 9202 str r2, [sp, #8] 801751e: 9301 str r3, [sp, #4] 8017520: 2302 movs r3, #2 8017522: 9300 str r3, [sp, #0] 8017524: 2300 movs r3, #0 8017526: 460a mov r2, r1 8017528: 4911 ldr r1, [pc, #68] @ (8017570 ) 801752a: 4812 ldr r0, [pc, #72] @ (8017574 ) 801752c: f7fe f90a bl 8015744 8017530: 4603 mov r3, r0 8017532: 4a11 ldr r2, [pc, #68] @ (8017578 ) 8017534: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 8017536: 4b10 ldr r3, [pc, #64] @ (8017578 ) 8017538: 681b ldr r3, [r3, #0] 801753a: 2b00 cmp r3, #0 801753c: d001 beq.n 8017542 { xReturn = pdPASS; 801753e: 2301 movs r3, #1 8017540: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 8017542: 697b ldr r3, [r7, #20] 8017544: 2b00 cmp r3, #0 8017546: d10b bne.n 8017560 __asm volatile 8017548: f04f 0350 mov.w r3, #80 @ 0x50 801754c: f383 8811 msr BASEPRI, r3 8017550: f3bf 8f6f isb sy 8017554: f3bf 8f4f dsb sy 8017558: 613b str r3, [r7, #16] } 801755a: bf00 nop 801755c: bf00 nop 801755e: e7fd b.n 801755c return xReturn; 8017560: 697b ldr r3, [r7, #20] } 8017562: 4618 mov r0, r3 8017564: 3718 adds r7, #24 8017566: 46bd mov sp, r7 8017568: bd80 pop {r7, pc} 801756a: bf00 nop 801756c: 20002698 .word 0x20002698 8017570: 0801e304 .word 0x0801e304 8017574: 08017621 .word 0x08017621 8017578: 2000269c .word 0x2000269c 0801757c : /*-----------------------------------------------------------*/ static void prvReloadTimer( Timer_t * const pxTimer, TickType_t xExpiredTime, const TickType_t xTimeNow ) { 801757c: b580 push {r7, lr} 801757e: b084 sub sp, #16 8017580: af00 add r7, sp, #0 8017582: 60f8 str r0, [r7, #12] 8017584: 60b9 str r1, [r7, #8] 8017586: 607a str r2, [r7, #4] /* Insert the timer into the appropriate list for the next expiry time. * If the next expiry time has already passed, advance the expiry time, * call the callback function, and try again. */ while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE ) 8017588: e008 b.n 801759c { /* Advance the expiry time. */ xExpiredTime += pxTimer->xTimerPeriodInTicks; 801758a: 68fb ldr r3, [r7, #12] 801758c: 699b ldr r3, [r3, #24] 801758e: 68ba ldr r2, [r7, #8] 8017590: 4413 add r3, r2 8017592: 60bb str r3, [r7, #8] /* Call the timer callback. */ traceTIMER_EXPIRED( pxTimer ); pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8017594: 68fb ldr r3, [r7, #12] 8017596: 6a1b ldr r3, [r3, #32] 8017598: 68f8 ldr r0, [r7, #12] 801759a: 4798 blx r3 while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE ) 801759c: 68fb ldr r3, [r7, #12] 801759e: 699a ldr r2, [r3, #24] 80175a0: 68bb ldr r3, [r7, #8] 80175a2: 18d1 adds r1, r2, r3 80175a4: 68bb ldr r3, [r7, #8] 80175a6: 687a ldr r2, [r7, #4] 80175a8: 68f8 ldr r0, [r7, #12] 80175aa: f000 f8df bl 801776c 80175ae: 4603 mov r3, r0 80175b0: 2b00 cmp r3, #0 80175b2: d1ea bne.n 801758a } } 80175b4: bf00 nop 80175b6: bf00 nop 80175b8: 3710 adds r7, #16 80175ba: 46bd mov sp, r7 80175bc: bd80 pop {r7, pc} ... 080175c0 : /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 80175c0: b580 push {r7, lr} 80175c2: b084 sub sp, #16 80175c4: af00 add r7, sp, #0 80175c6: 6078 str r0, [r7, #4] 80175c8: 6039 str r1, [r7, #0] Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80175ca: 4b14 ldr r3, [pc, #80] @ (801761c ) 80175cc: 681b ldr r3, [r3, #0] 80175ce: 68db ldr r3, [r3, #12] 80175d0: 68db ldr r3, [r3, #12] 80175d2: 60fb str r3, [r7, #12] /* Remove the timer from the list of active timers. A check has already * been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 80175d4: 68fb ldr r3, [r7, #12] 80175d6: 3304 adds r3, #4 80175d8: 4618 mov r0, r3 80175da: f7fc ff1f bl 801441c /* If the timer is an auto-reload timer then calculate the next * expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80175de: 68fb ldr r3, [r7, #12] 80175e0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80175e4: f003 0304 and.w r3, r3, #4 80175e8: 2b00 cmp r3, #0 80175ea: d005 beq.n 80175f8 { prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow ); 80175ec: 683a ldr r2, [r7, #0] 80175ee: 6879 ldr r1, [r7, #4] 80175f0: 68f8 ldr r0, [r7, #12] 80175f2: f7ff ffc3 bl 801757c 80175f6: e008 b.n 801760a } else { pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); 80175f8: 68fb ldr r3, [r7, #12] 80175fa: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80175fe: f023 0301 bic.w r3, r3, #1 8017602: b2da uxtb r2, r3 8017604: 68fb ldr r3, [r7, #12] 8017606: f883 2028 strb.w r2, [r3, #40] @ 0x28 } /* Call the timer callback. */ traceTIMER_EXPIRED( pxTimer ); pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 801760a: 68fb ldr r3, [r7, #12] 801760c: 6a1b ldr r3, [r3, #32] 801760e: 68f8 ldr r0, [r7, #12] 8017610: 4798 blx r3 } 8017612: bf00 nop 8017614: 3710 adds r7, #16 8017616: 46bd mov sp, r7 8017618: bd80 pop {r7, pc} 801761a: bf00 nop 801761c: 20002690 .word 0x20002690 08017620 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8017620: b580 push {r7, lr} 8017622: b084 sub sp, #16 8017624: af00 add r7, sp, #0 8017626: 6078 str r0, [r7, #4] for( ; ; ) { /* Query the timers list to see if it contains any timers, and if so, * obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8017628: f107 0308 add.w r3, r7, #8 801762c: 4618 mov r0, r3 801762e: f000 f859 bl 80176e4 8017632: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task * until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 8017634: 68bb ldr r3, [r7, #8] 8017636: 4619 mov r1, r3 8017638: 68f8 ldr r0, [r7, #12] 801763a: f000 f805 bl 8017648 /* Empty the command queue. */ prvProcessReceivedCommands(); 801763e: f000 f8d7 bl 80177f0 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8017642: bf00 nop 8017644: e7f0 b.n 8017628 ... 08017648 : } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8017648: b580 push {r7, lr} 801764a: b084 sub sp, #16 801764c: af00 add r7, sp, #0 801764e: 6078 str r0, [r7, #4] 8017650: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 8017652: f7fe fad9 bl 8015c08 /* Obtain the time now to make an assessment as to whether the timer * has expired or not. If obtaining the time causes the lists to switch * then don't process this timer as any timers that remained in the list * when the lists were switched will have been processed within the * prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8017656: f107 0308 add.w r3, r7, #8 801765a: 4618 mov r0, r3 801765c: f000 f866 bl 801772c 8017660: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 8017662: 68bb ldr r3, [r7, #8] 8017664: 2b00 cmp r3, #0 8017666: d130 bne.n 80176ca { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8017668: 683b ldr r3, [r7, #0] 801766a: 2b00 cmp r3, #0 801766c: d10a bne.n 8017684 801766e: 687a ldr r2, [r7, #4] 8017670: 68fb ldr r3, [r7, #12] 8017672: 429a cmp r2, r3 8017674: d806 bhi.n 8017684 { ( void ) xTaskResumeAll(); 8017676: f7fe fad5 bl 8015c24 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 801767a: 68f9 ldr r1, [r7, #12] 801767c: 6878 ldr r0, [r7, #4] 801767e: f7ff ff9f bl 80175c0 else { ( void ) xTaskResumeAll(); } } } 8017682: e024 b.n 80176ce if( xListWasEmpty != pdFALSE ) 8017684: 683b ldr r3, [r7, #0] 8017686: 2b00 cmp r3, #0 8017688: d008 beq.n 801769c xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 801768a: 4b13 ldr r3, [pc, #76] @ (80176d8 ) 801768c: 681b ldr r3, [r3, #0] 801768e: 681b ldr r3, [r3, #0] 8017690: 2b00 cmp r3, #0 8017692: d101 bne.n 8017698 8017694: 2301 movs r3, #1 8017696: e000 b.n 801769a 8017698: 2300 movs r3, #0 801769a: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 801769c: 4b0f ldr r3, [pc, #60] @ (80176dc ) 801769e: 6818 ldr r0, [r3, #0] 80176a0: 687a ldr r2, [r7, #4] 80176a2: 68fb ldr r3, [r7, #12] 80176a4: 1ad3 subs r3, r2, r3 80176a6: 683a ldr r2, [r7, #0] 80176a8: 4619 mov r1, r3 80176aa: f7fe f817 bl 80156dc if( xTaskResumeAll() == pdFALSE ) 80176ae: f7fe fab9 bl 8015c24 80176b2: 4603 mov r3, r0 80176b4: 2b00 cmp r3, #0 80176b6: d10a bne.n 80176ce portYIELD_WITHIN_API(); 80176b8: 4b09 ldr r3, [pc, #36] @ (80176e0 ) 80176ba: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80176be: 601a str r2, [r3, #0] 80176c0: f3bf 8f4f dsb sy 80176c4: f3bf 8f6f isb sy } 80176c8: e001 b.n 80176ce ( void ) xTaskResumeAll(); 80176ca: f7fe faab bl 8015c24 } 80176ce: bf00 nop 80176d0: 3710 adds r7, #16 80176d2: 46bd mov sp, r7 80176d4: bd80 pop {r7, pc} 80176d6: bf00 nop 80176d8: 20002694 .word 0x20002694 80176dc: 20002698 .word 0x20002698 80176e0: e000ed04 .word 0xe000ed04 080176e4 : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 80176e4: b480 push {r7} 80176e6: b085 sub sp, #20 80176e8: af00 add r7, sp, #0 80176ea: 6078 str r0, [r7, #4] * the timer with the nearest expiry time will expire. If there are no * active timers then just set the next expire time to 0. That will cause * this task to unblock when the tick count overflows, at which point the * timer lists will be switched and the next expiry time can be * re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 80176ec: 4b0e ldr r3, [pc, #56] @ (8017728 ) 80176ee: 681b ldr r3, [r3, #0] 80176f0: 681b ldr r3, [r3, #0] 80176f2: 2b00 cmp r3, #0 80176f4: d101 bne.n 80176fa 80176f6: 2201 movs r2, #1 80176f8: e000 b.n 80176fc 80176fa: 2200 movs r2, #0 80176fc: 687b ldr r3, [r7, #4] 80176fe: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8017700: 687b ldr r3, [r7, #4] 8017702: 681b ldr r3, [r3, #0] 8017704: 2b00 cmp r3, #0 8017706: d105 bne.n 8017714 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8017708: 4b07 ldr r3, [pc, #28] @ (8017728 ) 801770a: 681b ldr r3, [r3, #0] 801770c: 68db ldr r3, [r3, #12] 801770e: 681b ldr r3, [r3, #0] 8017710: 60fb str r3, [r7, #12] 8017712: e001 b.n 8017718 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8017714: 2300 movs r3, #0 8017716: 60fb str r3, [r7, #12] } return xNextExpireTime; 8017718: 68fb ldr r3, [r7, #12] } 801771a: 4618 mov r0, r3 801771c: 3714 adds r7, #20 801771e: 46bd mov sp, r7 8017720: f85d 7b04 ldr.w r7, [sp], #4 8017724: 4770 bx lr 8017726: bf00 nop 8017728: 20002690 .word 0x20002690 0801772c : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 801772c: b580 push {r7, lr} 801772e: b084 sub sp, #16 8017730: af00 add r7, sp, #0 8017732: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 8017734: f7fe fb74 bl 8015e20 8017738: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 801773a: 4b0b ldr r3, [pc, #44] @ (8017768 ) 801773c: 681b ldr r3, [r3, #0] 801773e: 68fa ldr r2, [r7, #12] 8017740: 429a cmp r2, r3 8017742: d205 bcs.n 8017750 { prvSwitchTimerLists(); 8017744: f000 f932 bl 80179ac *pxTimerListsWereSwitched = pdTRUE; 8017748: 687b ldr r3, [r7, #4] 801774a: 2201 movs r2, #1 801774c: 601a str r2, [r3, #0] 801774e: e002 b.n 8017756 } else { *pxTimerListsWereSwitched = pdFALSE; 8017750: 687b ldr r3, [r7, #4] 8017752: 2200 movs r2, #0 8017754: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 8017756: 4a04 ldr r2, [pc, #16] @ (8017768 ) 8017758: 68fb ldr r3, [r7, #12] 801775a: 6013 str r3, [r2, #0] return xTimeNow; 801775c: 68fb ldr r3, [r7, #12] } 801775e: 4618 mov r0, r3 8017760: 3710 adds r7, #16 8017762: 46bd mov sp, r7 8017764: bd80 pop {r7, pc} 8017766: bf00 nop 8017768: 200026a0 .word 0x200026a0 0801776c : static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 801776c: b580 push {r7, lr} 801776e: b086 sub sp, #24 8017770: af00 add r7, sp, #0 8017772: 60f8 str r0, [r7, #12] 8017774: 60b9 str r1, [r7, #8] 8017776: 607a str r2, [r7, #4] 8017778: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 801777a: 2300 movs r3, #0 801777c: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 801777e: 68fb ldr r3, [r7, #12] 8017780: 68ba ldr r2, [r7, #8] 8017782: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8017784: 68fb ldr r3, [r7, #12] 8017786: 68fa ldr r2, [r7, #12] 8017788: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 801778a: 68ba ldr r2, [r7, #8] 801778c: 687b ldr r3, [r7, #4] 801778e: 429a cmp r2, r3 8017790: d812 bhi.n 80177b8 { /* Has the expiry time elapsed between the command to start/reset a * timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8017792: 687a ldr r2, [r7, #4] 8017794: 683b ldr r3, [r7, #0] 8017796: 1ad2 subs r2, r2, r3 8017798: 68fb ldr r3, [r7, #12] 801779a: 699b ldr r3, [r3, #24] 801779c: 429a cmp r2, r3 801779e: d302 bcc.n 80177a6 { /* The time between a command being issued and the command being * processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 80177a0: 2301 movs r3, #1 80177a2: 617b str r3, [r7, #20] 80177a4: e01b b.n 80177de } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 80177a6: 4b10 ldr r3, [pc, #64] @ (80177e8 ) 80177a8: 681a ldr r2, [r3, #0] 80177aa: 68fb ldr r3, [r7, #12] 80177ac: 3304 adds r3, #4 80177ae: 4619 mov r1, r3 80177b0: 4610 mov r0, r2 80177b2: f7fc fdfa bl 80143aa 80177b6: e012 b.n 80177de } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 80177b8: 687a ldr r2, [r7, #4] 80177ba: 683b ldr r3, [r7, #0] 80177bc: 429a cmp r2, r3 80177be: d206 bcs.n 80177ce 80177c0: 68ba ldr r2, [r7, #8] 80177c2: 683b ldr r3, [r7, #0] 80177c4: 429a cmp r2, r3 80177c6: d302 bcc.n 80177ce { /* If, since the command was issued, the tick count has overflowed * but the expiry time has not, then the timer must have already passed * its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 80177c8: 2301 movs r3, #1 80177ca: 617b str r3, [r7, #20] 80177cc: e007 b.n 80177de } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80177ce: 4b07 ldr r3, [pc, #28] @ (80177ec ) 80177d0: 681a ldr r2, [r3, #0] 80177d2: 68fb ldr r3, [r7, #12] 80177d4: 3304 adds r3, #4 80177d6: 4619 mov r1, r3 80177d8: 4610 mov r0, r2 80177da: f7fc fde6 bl 80143aa } } return xProcessTimerNow; 80177de: 697b ldr r3, [r7, #20] } 80177e0: 4618 mov r0, r3 80177e2: 3718 adds r7, #24 80177e4: 46bd mov sp, r7 80177e6: bd80 pop {r7, pc} 80177e8: 20002694 .word 0x20002694 80177ec: 20002690 .word 0x20002690 080177f0 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 80177f0: b580 push {r7, lr} 80177f2: b08a sub sp, #40 @ 0x28 80177f4: af00 add r7, sp, #0 DaemonTaskMessage_t xMessage; Timer_t * pxTimer; BaseType_t xTimerListsWereSwitched; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 80177f6: e0c7 b.n 8017988 { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer * commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 80177f8: 687b ldr r3, [r7, #4] 80177fa: 2b00 cmp r3, #0 80177fc: da19 bge.n 8017832 { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 80177fe: 1d3b adds r3, r7, #4 8017800: 3304 adds r3, #4 8017802: 627b str r3, [r7, #36] @ 0x24 /* The timer uses the xCallbackParameters member to request a * callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 8017804: 6a7b ldr r3, [r7, #36] @ 0x24 8017806: 2b00 cmp r3, #0 8017808: d10b bne.n 8017822 __asm volatile 801780a: f04f 0350 mov.w r3, #80 @ 0x50 801780e: f383 8811 msr BASEPRI, r3 8017812: f3bf 8f6f isb sy 8017816: f3bf 8f4f dsb sy 801781a: 61bb str r3, [r7, #24] } 801781c: bf00 nop 801781e: bf00 nop 8017820: e7fd b.n 801781e /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 8017822: 6a7b ldr r3, [r7, #36] @ 0x24 8017824: 681b ldr r3, [r3, #0] 8017826: 6a7a ldr r2, [r7, #36] @ 0x24 8017828: 6850 ldr r0, [r2, #4] 801782a: 6a7a ldr r2, [r7, #36] @ 0x24 801782c: 6892 ldr r2, [r2, #8] 801782e: 4611 mov r1, r2 8017830: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended * function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 8017832: 687b ldr r3, [r7, #4] 8017834: 2b00 cmp r3, #0 8017836: f2c0 80a7 blt.w 8017988 { /* The messages uses the xTimerParameters member to work on a * software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 801783a: 68fb ldr r3, [r7, #12] 801783c: 623b str r3, [r7, #32] if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 801783e: 6a3b ldr r3, [r7, #32] 8017840: 695b ldr r3, [r3, #20] 8017842: 2b00 cmp r3, #0 8017844: d004 beq.n 8017850 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8017846: 6a3b ldr r3, [r7, #32] 8017848: 3304 adds r3, #4 801784a: 4618 mov r0, r3 801784c: f7fc fde6 bl 801441c * it must be present in the function call. prvSampleTimeNow() must be * called after the message is received from xTimerQueue so there is no * possibility of a higher priority task adding a message to the message * queue with a time that is ahead of the timer daemon task (because it * pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8017850: 463b mov r3, r7 8017852: 4618 mov r0, r3 8017854: f7ff ff6a bl 801772c 8017858: 61f8 str r0, [r7, #28] switch( xMessage.xMessageID ) 801785a: 687b ldr r3, [r7, #4] 801785c: 3b01 subs r3, #1 801785e: 2b08 cmp r3, #8 8017860: f200 808f bhi.w 8017982 8017864: a201 add r2, pc, #4 @ (adr r2, 801786c ) 8017866: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801786a: bf00 nop 801786c: 08017891 .word 0x08017891 8017870: 08017891 .word 0x08017891 8017874: 080178f9 .word 0x080178f9 8017878: 0801790d .word 0x0801790d 801787c: 08017959 .word 0x08017959 8017880: 08017891 .word 0x08017891 8017884: 08017891 .word 0x08017891 8017888: 080178f9 .word 0x080178f9 801788c: 0801790d .word 0x0801790d case tmrCOMMAND_START: case tmrCOMMAND_START_FROM_ISR: case tmrCOMMAND_RESET: case tmrCOMMAND_RESET_FROM_ISR: /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8017890: 6a3b ldr r3, [r7, #32] 8017892: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017896: f043 0301 orr.w r3, r3, #1 801789a: b2da uxtb r2, r3 801789c: 6a3b ldr r3, [r7, #32] 801789e: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 80178a2: 68ba ldr r2, [r7, #8] 80178a4: 6a3b ldr r3, [r7, #32] 80178a6: 699b ldr r3, [r3, #24] 80178a8: 18d1 adds r1, r2, r3 80178aa: 68bb ldr r3, [r7, #8] 80178ac: 69fa ldr r2, [r7, #28] 80178ae: 6a38 ldr r0, [r7, #32] 80178b0: f7ff ff5c bl 801776c 80178b4: 4603 mov r3, r0 80178b6: 2b00 cmp r3, #0 80178b8: d065 beq.n 8017986 { /* The timer expired before it was added to the active * timer list. Process it now. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80178ba: 6a3b ldr r3, [r7, #32] 80178bc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80178c0: f003 0304 and.w r3, r3, #4 80178c4: 2b00 cmp r3, #0 80178c6: d009 beq.n 80178dc { prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow ); 80178c8: 68ba ldr r2, [r7, #8] 80178ca: 6a3b ldr r3, [r7, #32] 80178cc: 699b ldr r3, [r3, #24] 80178ce: 4413 add r3, r2 80178d0: 69fa ldr r2, [r7, #28] 80178d2: 4619 mov r1, r3 80178d4: 6a38 ldr r0, [r7, #32] 80178d6: f7ff fe51 bl 801757c 80178da: e008 b.n 80178ee } else { pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); 80178dc: 6a3b ldr r3, [r7, #32] 80178de: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80178e2: f023 0301 bic.w r3, r3, #1 80178e6: b2da uxtb r2, r3 80178e8: 6a3b ldr r3, [r7, #32] 80178ea: f883 2028 strb.w r2, [r3, #40] @ 0x28 } /* Call the timer callback. */ traceTIMER_EXPIRED( pxTimer ); pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80178ee: 6a3b ldr r3, [r7, #32] 80178f0: 6a1b ldr r3, [r3, #32] 80178f2: 6a38 ldr r0, [r7, #32] 80178f4: 4798 blx r3 else { mtCOVERAGE_TEST_MARKER(); } break; 80178f6: e046 b.n 8017986 case tmrCOMMAND_STOP: case tmrCOMMAND_STOP_FROM_ISR: /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); 80178f8: 6a3b ldr r3, [r7, #32] 80178fa: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80178fe: f023 0301 bic.w r3, r3, #1 8017902: b2da uxtb r2, r3 8017904: 6a3b ldr r3, [r7, #32] 8017906: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 801790a: e03d b.n 8017988 case tmrCOMMAND_CHANGE_PERIOD: case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 801790c: 6a3b ldr r3, [r7, #32] 801790e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017912: f043 0301 orr.w r3, r3, #1 8017916: b2da uxtb r2, r3 8017918: 6a3b ldr r3, [r7, #32] 801791a: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 801791e: 68ba ldr r2, [r7, #8] 8017920: 6a3b ldr r3, [r7, #32] 8017922: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 8017924: 6a3b ldr r3, [r7, #32] 8017926: 699b ldr r3, [r3, #24] 8017928: 2b00 cmp r3, #0 801792a: d10b bne.n 8017944 __asm volatile 801792c: f04f 0350 mov.w r3, #80 @ 0x50 8017930: f383 8811 msr BASEPRI, r3 8017934: f3bf 8f6f isb sy 8017938: f3bf 8f4f dsb sy 801793c: 617b str r3, [r7, #20] } 801793e: bf00 nop 8017940: bf00 nop 8017942: e7fd b.n 8017940 * be longer or shorter than the old one. The command time is * therefore set to the current time, and as the period cannot * be zero the next expiry time can only be in the future, * meaning (unlike for the xTimerStart() case above) there is * no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 8017944: 6a3b ldr r3, [r7, #32] 8017946: 699a ldr r2, [r3, #24] 8017948: 69fb ldr r3, [r7, #28] 801794a: 18d1 adds r1, r2, r3 801794c: 69fb ldr r3, [r7, #28] 801794e: 69fa ldr r2, [r7, #28] 8017950: 6a38 ldr r0, [r7, #32] 8017952: f7ff ff0b bl 801776c break; 8017956: e017 b.n 8017988 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, * just free up the memory if the memory was dynamically * allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 8017958: 6a3b ldr r3, [r7, #32] 801795a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801795e: f003 0302 and.w r3, r3, #2 8017962: 2b00 cmp r3, #0 8017964: d103 bne.n 801796e { vPortFree( pxTimer ); 8017966: 6a38 ldr r0, [r7, #32] 8017968: f000 fbc6 bl 80180f8 * no need to free the memory - just mark the timer as * "not active". */ pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 801796c: e00c b.n 8017988 pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); 801796e: 6a3b ldr r3, [r7, #32] 8017970: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017974: f023 0301 bic.w r3, r3, #1 8017978: b2da uxtb r2, r3 801797a: 6a3b ldr r3, [r7, #32] 801797c: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8017980: e002 b.n 8017988 default: /* Don't expect to get here. */ break; 8017982: bf00 nop 8017984: e000 b.n 8017988 break; 8017986: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8017988: 4b07 ldr r3, [pc, #28] @ (80179a8 ) 801798a: 681b ldr r3, [r3, #0] 801798c: 1d39 adds r1, r7, #4 801798e: 2200 movs r2, #0 8017990: 4618 mov r0, r3 8017992: f7fd fa51 bl 8014e38 8017996: 4603 mov r3, r0 8017998: 2b00 cmp r3, #0 801799a: f47f af2d bne.w 80177f8 } } } } 801799e: bf00 nop 80179a0: bf00 nop 80179a2: 3728 adds r7, #40 @ 0x28 80179a4: 46bd mov sp, r7 80179a6: bd80 pop {r7, pc} 80179a8: 20002698 .word 0x20002698 080179ac : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 80179ac: b580 push {r7, lr} 80179ae: b082 sub sp, #8 80179b0: af00 add r7, sp, #0 /* The tick count has overflowed. The timer lists must be switched. * If there are any timers still referenced from the current timer list * then they must have expired and should be processed before the lists * are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 80179b2: e009 b.n 80179c8 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 80179b4: 4b0e ldr r3, [pc, #56] @ (80179f0 ) 80179b6: 681b ldr r3, [r3, #0] 80179b8: 68db ldr r3, [r3, #12] 80179ba: 681b ldr r3, [r3, #0] 80179bc: 603b str r3, [r7, #0] /* Process the expired timer. For auto-reload timers, be careful to * process only expirations that occur on the current list. Further * expirations must wait until after the lists are switched. */ prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW ); 80179be: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80179c2: 6838 ldr r0, [r7, #0] 80179c4: f7ff fdfc bl 80175c0 while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 80179c8: 4b09 ldr r3, [pc, #36] @ (80179f0 ) 80179ca: 681b ldr r3, [r3, #0] 80179cc: 681b ldr r3, [r3, #0] 80179ce: 2b00 cmp r3, #0 80179d0: d1f0 bne.n 80179b4 } pxTemp = pxCurrentTimerList; 80179d2: 4b07 ldr r3, [pc, #28] @ (80179f0 ) 80179d4: 681b ldr r3, [r3, #0] 80179d6: 607b str r3, [r7, #4] pxCurrentTimerList = pxOverflowTimerList; 80179d8: 4b06 ldr r3, [pc, #24] @ (80179f4 ) 80179da: 681b ldr r3, [r3, #0] 80179dc: 4a04 ldr r2, [pc, #16] @ (80179f0 ) 80179de: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 80179e0: 4a04 ldr r2, [pc, #16] @ (80179f4 ) 80179e2: 687b ldr r3, [r7, #4] 80179e4: 6013 str r3, [r2, #0] } 80179e6: bf00 nop 80179e8: 3708 adds r7, #8 80179ea: 46bd mov sp, r7 80179ec: bd80 pop {r7, pc} 80179ee: bf00 nop 80179f0: 20002690 .word 0x20002690 80179f4: 20002694 .word 0x20002694 080179f8 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 80179f8: b580 push {r7, lr} 80179fa: b082 sub sp, #8 80179fc: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the * queue used to communicate with the timer service, have been * initialised. */ taskENTER_CRITICAL(); 80179fe: f000 f987 bl 8017d10 { if( xTimerQueue == NULL ) 8017a02: 4b15 ldr r3, [pc, #84] @ (8017a58 ) 8017a04: 681b ldr r3, [r3, #0] 8017a06: 2b00 cmp r3, #0 8017a08: d120 bne.n 8017a4c { vListInitialise( &xActiveTimerList1 ); 8017a0a: 4814 ldr r0, [pc, #80] @ (8017a5c ) 8017a0c: f7fc fca0 bl 8014350 vListInitialise( &xActiveTimerList2 ); 8017a10: 4813 ldr r0, [pc, #76] @ (8017a60 ) 8017a12: f7fc fc9d bl 8014350 pxCurrentTimerList = &xActiveTimerList1; 8017a16: 4b13 ldr r3, [pc, #76] @ (8017a64 ) 8017a18: 4a10 ldr r2, [pc, #64] @ (8017a5c ) 8017a1a: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8017a1c: 4b12 ldr r3, [pc, #72] @ (8017a68 ) 8017a1e: 4a10 ldr r2, [pc, #64] @ (8017a60 ) 8017a20: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case * configSUPPORT_DYNAMIC_ALLOCATION is 0. */ PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 8017a22: 2300 movs r3, #0 8017a24: 9300 str r3, [sp, #0] 8017a26: 4b11 ldr r3, [pc, #68] @ (8017a6c ) 8017a28: 4a11 ldr r2, [pc, #68] @ (8017a70 ) 8017a2a: 2110 movs r1, #16 8017a2c: 200a movs r0, #10 8017a2e: f7fc fdb1 bl 8014594 8017a32: 4603 mov r3, r0 8017a34: 4a08 ldr r2, [pc, #32] @ (8017a58 ) 8017a36: 6013 str r3, [r2, #0] } #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8017a38: 4b07 ldr r3, [pc, #28] @ (8017a58 ) 8017a3a: 681b ldr r3, [r3, #0] 8017a3c: 2b00 cmp r3, #0 8017a3e: d005 beq.n 8017a4c { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8017a40: 4b05 ldr r3, [pc, #20] @ (8017a58 ) 8017a42: 681b ldr r3, [r3, #0] 8017a44: 490b ldr r1, [pc, #44] @ (8017a74 ) 8017a46: 4618 mov r0, r3 8017a48: f7fd fdbe bl 80155c8 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8017a4c: f000 f992 bl 8017d74 } 8017a50: bf00 nop 8017a52: 46bd mov sp, r7 8017a54: bd80 pop {r7, pc} 8017a56: bf00 nop 8017a58: 20002698 .word 0x20002698 8017a5c: 20002668 .word 0x20002668 8017a60: 2000267c .word 0x2000267c 8017a64: 20002690 .word 0x20002690 8017a68: 20002694 .word 0x20002694 8017a6c: 20002744 .word 0x20002744 8017a70: 200026a4 .word 0x200026a4 8017a74: 0801e30c .word 0x0801e30c 08017a78 : * See header file for description. */ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void * pvParameters ) { 8017a78: b480 push {r7} 8017a7a: b085 sub sp, #20 8017a7c: af00 add r7, sp, #0 8017a7e: 60f8 str r0, [r7, #12] 8017a80: 60b9 str r1, [r7, #8] 8017a82: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch * interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit * of interrupts, and to ensure alignment. */ pxTopOfStack--; 8017a84: 68fb ldr r3, [r7, #12] 8017a86: 3b04 subs r3, #4 8017a88: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 8017a8a: 68fb ldr r3, [r7, #12] 8017a8c: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8017a90: 601a str r2, [r3, #0] pxTopOfStack--; 8017a92: 68fb ldr r3, [r7, #12] 8017a94: 3b04 subs r3, #4 8017a96: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 8017a98: 68bb ldr r3, [r7, #8] 8017a9a: f023 0201 bic.w r2, r3, #1 8017a9e: 68fb ldr r3, [r7, #12] 8017aa0: 601a str r2, [r3, #0] pxTopOfStack--; 8017aa2: 68fb ldr r3, [r7, #12] 8017aa4: 3b04 subs r3, #4 8017aa6: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 8017aa8: 4a0c ldr r2, [pc, #48] @ (8017adc ) 8017aaa: 68fb ldr r3, [r7, #12] 8017aac: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8017aae: 68fb ldr r3, [r7, #12] 8017ab0: 3b14 subs r3, #20 8017ab2: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8017ab4: 687a ldr r2, [r7, #4] 8017ab6: 68fb ldr r3, [r7, #12] 8017ab8: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its * own exec return value. */ pxTopOfStack--; 8017aba: 68fb ldr r3, [r7, #12] 8017abc: 3b04 subs r3, #4 8017abe: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8017ac0: 68fb ldr r3, [r7, #12] 8017ac2: f06f 0202 mvn.w r2, #2 8017ac6: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8017ac8: 68fb ldr r3, [r7, #12] 8017aca: 3b20 subs r3, #32 8017acc: 60fb str r3, [r7, #12] return pxTopOfStack; 8017ace: 68fb ldr r3, [r7, #12] } 8017ad0: 4618 mov r0, r3 8017ad2: 3714 adds r7, #20 8017ad4: 46bd mov sp, r7 8017ad6: f85d 7b04 ldr.w r7, [sp], #4 8017ada: 4770 bx lr 8017adc: 08017ae1 .word 0x08017ae1 08017ae0 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8017ae0: b480 push {r7} 8017ae2: b085 sub sp, #20 8017ae4: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8017ae6: 2300 movs r3, #0 8017ae8: 607b str r3, [r7, #4] * its caller as there is nothing to return to. If a task wants to exit it * should instead call vTaskDelete( NULL ). * * Artificially force an assert() to be triggered if configASSERT() is * defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8017aea: 4b13 ldr r3, [pc, #76] @ (8017b38 ) 8017aec: 681b ldr r3, [r3, #0] 8017aee: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017af2: d00b beq.n 8017b0c __asm volatile 8017af4: f04f 0350 mov.w r3, #80 @ 0x50 8017af8: f383 8811 msr BASEPRI, r3 8017afc: f3bf 8f6f isb sy 8017b00: f3bf 8f4f dsb sy 8017b04: 60fb str r3, [r7, #12] } 8017b06: bf00 nop 8017b08: bf00 nop 8017b0a: e7fd b.n 8017b08 __asm volatile 8017b0c: f04f 0350 mov.w r3, #80 @ 0x50 8017b10: f383 8811 msr BASEPRI, r3 8017b14: f3bf 8f6f isb sy 8017b18: f3bf 8f4f dsb sy 8017b1c: 60bb str r3, [r7, #8] } 8017b1e: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8017b20: bf00 nop 8017b22: 687b ldr r3, [r7, #4] 8017b24: 2b00 cmp r3, #0 8017b26: d0fc beq.n 8017b22 * about code appearing after this function is called - making ulDummy * volatile makes the compiler think the function could return and * therefore not output an 'unreachable code' warning for code that appears * after it. */ } } 8017b28: bf00 nop 8017b2a: bf00 nop 8017b2c: 3714 adds r7, #20 8017b2e: 46bd mov sp, r7 8017b30: f85d 7b04 ldr.w r7, [sp], #4 8017b34: 4770 bx lr 8017b36: bf00 nop 8017b38: 200000a4 .word 0x200000a4 8017b3c: 00000000 .word 0x00000000 08017b40 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8017b40: 4b07 ldr r3, [pc, #28] @ (8017b60 ) 8017b42: 6819 ldr r1, [r3, #0] 8017b44: 6808 ldr r0, [r1, #0] 8017b46: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017b4a: f380 8809 msr PSP, r0 8017b4e: f3bf 8f6f isb sy 8017b52: f04f 0000 mov.w r0, #0 8017b56: f380 8811 msr BASEPRI, r0 8017b5a: 4770 bx lr 8017b5c: f3af 8000 nop.w 08017b60 : 8017b60: 20002168 .word 0x20002168 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8017b64: bf00 nop 8017b66: bf00 nop 08017b68 : { /* Start the first task. This also clears the bit that indicates the FPU is * in use in case the FPU was used before the scheduler was started - which * would otherwise result in the unnecessary leaving of space in the SVC stack * for lazy saving of FPU registers. */ __asm volatile ( 8017b68: 4808 ldr r0, [pc, #32] @ (8017b8c ) 8017b6a: 6800 ldr r0, [r0, #0] 8017b6c: 6800 ldr r0, [r0, #0] 8017b6e: f380 8808 msr MSP, r0 8017b72: f04f 0000 mov.w r0, #0 8017b76: f380 8814 msr CONTROL, r0 8017b7a: b662 cpsie i 8017b7c: b661 cpsie f 8017b7e: f3bf 8f4f dsb sy 8017b82: f3bf 8f6f isb sy 8017b86: df00 svc 0 8017b88: bf00 nop 8017b8a: 0000 .short 0x0000 8017b8c: e000ed08 .word 0xe000ed08 " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" " .ltorg \n" ); } 8017b90: bf00 nop 8017b92: bf00 nop 08017b94 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 8017b94: b580 push {r7, lr} 8017b96: b088 sub sp, #32 8017b98: af00 add r7, sp, #0 /* This port can be used on all revisions of the Cortex-M7 core other than * the r0p1 parts. r0p1 parts should use the port from the * /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 8017b9a: 4b54 ldr r3, [pc, #336] @ (8017cec ) 8017b9c: 681b ldr r3, [r3, #0] 8017b9e: 4a54 ldr r2, [pc, #336] @ (8017cf0 ) 8017ba0: 4293 cmp r3, r2 8017ba2: d10b bne.n 8017bbc __asm volatile 8017ba4: f04f 0350 mov.w r3, #80 @ 0x50 8017ba8: f383 8811 msr BASEPRI, r3 8017bac: f3bf 8f6f isb sy 8017bb0: f3bf 8f4f dsb sy 8017bb4: 617b str r3, [r7, #20] } 8017bb6: bf00 nop 8017bb8: bf00 nop 8017bba: e7fd b.n 8017bb8 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 8017bbc: 4b4b ldr r3, [pc, #300] @ (8017cec ) 8017bbe: 681b ldr r3, [r3, #0] 8017bc0: 4a4c ldr r2, [pc, #304] @ (8017cf4 ) 8017bc2: 4293 cmp r3, r2 8017bc4: d10b bne.n 8017bde __asm volatile 8017bc6: f04f 0350 mov.w r3, #80 @ 0x50 8017bca: f383 8811 msr BASEPRI, r3 8017bce: f3bf 8f6f isb sy 8017bd2: f3bf 8f4f dsb sy 8017bd6: 61bb str r3, [r7, #24] } 8017bd8: bf00 nop 8017bda: bf00 nop 8017bdc: e7fd b.n 8017bda #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; volatile uint32_t ulImplementedPrioBits = 0; 8017bde: 2300 movs r3, #0 8017be0: 607b str r3, [r7, #4] volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 8017be2: 4b45 ldr r3, [pc, #276] @ (8017cf8 ) 8017be4: 61fb str r3, [r7, #28] * functions can be called. ISR safe functions are those that end in * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * * Save the interrupt priority value that is about to be clobbered. */ ucOriginalPriority = *pucFirstUserPriorityRegister; 8017be6: 69fb ldr r3, [r7, #28] 8017be8: 781b ldrb r3, [r3, #0] 8017bea: b2db uxtb r3, r3 8017bec: 72fb strb r3, [r7, #11] /* Determine the number of priority bits available. First write to all * possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8017bee: 69fb ldr r3, [r7, #28] 8017bf0: 22ff movs r2, #255 @ 0xff 8017bf2: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 8017bf4: 69fb ldr r3, [r7, #28] 8017bf6: 781b ldrb r3, [r3, #0] 8017bf8: b2db uxtb r3, r3 8017bfa: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8017bfc: 78fb ldrb r3, [r7, #3] 8017bfe: b2db uxtb r3, r3 8017c00: f003 0350 and.w r3, r3, #80 @ 0x50 8017c04: b2da uxtb r2, r3 8017c06: 4b3d ldr r3, [pc, #244] @ (8017cfc ) 8017c08: 701a strb r2, [r3, #0] * accounting for the number of priority bits supported by the * hardware. A priority of 0 is invalid because setting the BASEPRI * register to 0 unmasks all interrupts, and interrupts with priority 0 * cannot be masked using BASEPRI. * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); 8017c0a: 4b3c ldr r3, [pc, #240] @ (8017cfc ) 8017c0c: 781b ldrb r3, [r3, #0] 8017c0e: 2b00 cmp r3, #0 8017c10: d10b bne.n 8017c2a __asm volatile 8017c12: f04f 0350 mov.w r3, #80 @ 0x50 8017c16: f383 8811 msr BASEPRI, r3 8017c1a: f3bf 8f6f isb sy 8017c1e: f3bf 8f4f dsb sy 8017c22: 613b str r3, [r7, #16] } 8017c24: bf00 nop 8017c26: bf00 nop 8017c28: e7fd b.n 8017c26 /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); 8017c2a: 78fb ldrb r3, [r7, #3] 8017c2c: b2db uxtb r3, r3 8017c2e: 43db mvns r3, r3 8017c30: f003 0350 and.w r3, r3, #80 @ 0x50 8017c34: 2b00 cmp r3, #0 8017c36: d013 beq.n 8017c60 __asm volatile 8017c38: f04f 0350 mov.w r3, #80 @ 0x50 8017c3c: f383 8811 msr BASEPRI, r3 8017c40: f3bf 8f6f isb sy 8017c44: f3bf 8f4f dsb sy 8017c48: 60fb str r3, [r7, #12] } 8017c4a: bf00 nop 8017c4c: bf00 nop 8017c4e: e7fd b.n 8017c4c /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; 8017c50: 687b ldr r3, [r7, #4] 8017c52: 3301 adds r3, #1 8017c54: 607b str r3, [r7, #4] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8017c56: 78fb ldrb r3, [r7, #3] 8017c58: b2db uxtb r3, r3 8017c5a: 005b lsls r3, r3, #1 8017c5c: b2db uxtb r3, r3 8017c5e: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017c60: 78fb ldrb r3, [r7, #3] 8017c62: b2db uxtb r3, r3 8017c64: f003 0380 and.w r3, r3, #128 @ 0x80 8017c68: 2b80 cmp r3, #128 @ 0x80 8017c6a: d0f1 beq.n 8017c50 } if( ulImplementedPrioBits == 8 ) 8017c6c: 687b ldr r3, [r7, #4] 8017c6e: 2b08 cmp r3, #8 8017c70: d103 bne.n 8017c7a * * The following assert ensures that the sub-priority bit in the * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; 8017c72: 4b23 ldr r3, [pc, #140] @ (8017d00 ) 8017c74: 2200 movs r2, #0 8017c76: 601a str r2, [r3, #0] 8017c78: e004 b.n 8017c84 } else { ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; 8017c7a: 687b ldr r3, [r7, #4] 8017c7c: f1c3 0307 rsb r3, r3, #7 8017c80: 4a1f ldr r2, [pc, #124] @ (8017d00 ) 8017c82: 6013 str r3, [r2, #0] } /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 8017c84: 4b1e ldr r3, [pc, #120] @ (8017d00 ) 8017c86: 681b ldr r3, [r3, #0] 8017c88: 021b lsls r3, r3, #8 8017c8a: 4a1d ldr r2, [pc, #116] @ (8017d00 ) 8017c8c: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8017c8e: 4b1c ldr r3, [pc, #112] @ (8017d00 ) 8017c90: 681b ldr r3, [r3, #0] 8017c92: f403 63e0 and.w r3, r3, #1792 @ 0x700 8017c96: 4a1a ldr r2, [pc, #104] @ (8017d00 ) 8017c98: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original * value. */ *pucFirstUserPriorityRegister = ucOriginalPriority; 8017c9a: 7afb ldrb r3, [r7, #11] 8017c9c: b2da uxtb r2, r3 8017c9e: 69fb ldr r3, [r7, #28] 8017ca0: 701a strb r2, [r3, #0] } #endif /* configASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; 8017ca2: 4b18 ldr r3, [pc, #96] @ (8017d04 ) 8017ca4: 681b ldr r3, [r3, #0] 8017ca6: 4a17 ldr r2, [pc, #92] @ (8017d04 ) 8017ca8: f443 037f orr.w r3, r3, #16711680 @ 0xff0000 8017cac: 6013 str r3, [r2, #0] portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; 8017cae: 4b15 ldr r3, [pc, #84] @ (8017d04 ) 8017cb0: 681b ldr r3, [r3, #0] 8017cb2: 4a14 ldr r2, [pc, #80] @ (8017d04 ) 8017cb4: f043 437f orr.w r3, r3, #4278190080 @ 0xff000000 8017cb8: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ vPortSetupTimerInterrupt(); 8017cba: f000 f8df bl 8017e7c /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8017cbe: 4b12 ldr r3, [pc, #72] @ (8017d08 ) 8017cc0: 2200 movs r2, #0 8017cc2: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 8017cc4: f000 f8fe bl 8017ec4 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8017cc8: 4b10 ldr r3, [pc, #64] @ (8017d0c ) 8017cca: 681b ldr r3, [r3, #0] 8017ccc: 4a0f ldr r2, [pc, #60] @ (8017d0c ) 8017cce: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 8017cd2: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 8017cd4: f7ff ff48 bl 8017b68 * exit error function to prevent compiler warnings about a static function * not being called in the case that the application writer overrides this * functionality by defining configTASK_RETURN_ADDRESS. Call * vTaskSwitchContext() so link time optimisation does not remove the * symbol. */ vTaskSwitchContext(); 8017cd8: f7fe f9d6 bl 8016088 prvTaskExitError(); 8017cdc: f7ff ff00 bl 8017ae0 /* Should not get here! */ return 0; 8017ce0: 2300 movs r3, #0 } 8017ce2: 4618 mov r0, r3 8017ce4: 3720 adds r7, #32 8017ce6: 46bd mov sp, r7 8017ce8: bd80 pop {r7, pc} 8017cea: bf00 nop 8017cec: e000ed00 .word 0xe000ed00 8017cf0: 410fc271 .word 0x410fc271 8017cf4: 410fc270 .word 0x410fc270 8017cf8: e000e400 .word 0xe000e400 8017cfc: 20002794 .word 0x20002794 8017d00: 20002798 .word 0x20002798 8017d04: e000ed20 .word 0xe000ed20 8017d08: 200000a4 .word 0x200000a4 8017d0c: e000ef34 .word 0xe000ef34 08017d10 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8017d10: b480 push {r7} 8017d12: b083 sub sp, #12 8017d14: af00 add r7, sp, #0 __asm volatile 8017d16: f04f 0350 mov.w r3, #80 @ 0x50 8017d1a: f383 8811 msr BASEPRI, r3 8017d1e: f3bf 8f6f isb sy 8017d22: f3bf 8f4f dsb sy 8017d26: 607b str r3, [r7, #4] } 8017d28: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8017d2a: 4b10 ldr r3, [pc, #64] @ (8017d6c ) 8017d2c: 681b ldr r3, [r3, #0] 8017d2e: 3301 adds r3, #1 8017d30: 4a0e ldr r2, [pc, #56] @ (8017d6c ) 8017d32: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so * assert() if it is being called from an interrupt context. Only API * functions that end in "FromISR" can be used in an interrupt. Only assert if * the critical nesting count is 1 to protect against recursive calls if the * assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8017d34: 4b0d ldr r3, [pc, #52] @ (8017d6c ) 8017d36: 681b ldr r3, [r3, #0] 8017d38: 2b01 cmp r3, #1 8017d3a: d110 bne.n 8017d5e { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8017d3c: 4b0c ldr r3, [pc, #48] @ (8017d70 ) 8017d3e: 681b ldr r3, [r3, #0] 8017d40: b2db uxtb r3, r3 8017d42: 2b00 cmp r3, #0 8017d44: d00b beq.n 8017d5e __asm volatile 8017d46: f04f 0350 mov.w r3, #80 @ 0x50 8017d4a: f383 8811 msr BASEPRI, r3 8017d4e: f3bf 8f6f isb sy 8017d52: f3bf 8f4f dsb sy 8017d56: 603b str r3, [r7, #0] } 8017d58: bf00 nop 8017d5a: bf00 nop 8017d5c: e7fd b.n 8017d5a } } 8017d5e: bf00 nop 8017d60: 370c adds r7, #12 8017d62: 46bd mov sp, r7 8017d64: f85d 7b04 ldr.w r7, [sp], #4 8017d68: 4770 bx lr 8017d6a: bf00 nop 8017d6c: 200000a4 .word 0x200000a4 8017d70: e000ed04 .word 0xe000ed04 08017d74 : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8017d74: b480 push {r7} 8017d76: b083 sub sp, #12 8017d78: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8017d7a: 4b12 ldr r3, [pc, #72] @ (8017dc4 ) 8017d7c: 681b ldr r3, [r3, #0] 8017d7e: 2b00 cmp r3, #0 8017d80: d10b bne.n 8017d9a __asm volatile 8017d82: f04f 0350 mov.w r3, #80 @ 0x50 8017d86: f383 8811 msr BASEPRI, r3 8017d8a: f3bf 8f6f isb sy 8017d8e: f3bf 8f4f dsb sy 8017d92: 607b str r3, [r7, #4] } 8017d94: bf00 nop 8017d96: bf00 nop 8017d98: e7fd b.n 8017d96 uxCriticalNesting--; 8017d9a: 4b0a ldr r3, [pc, #40] @ (8017dc4 ) 8017d9c: 681b ldr r3, [r3, #0] 8017d9e: 3b01 subs r3, #1 8017da0: 4a08 ldr r2, [pc, #32] @ (8017dc4 ) 8017da2: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8017da4: 4b07 ldr r3, [pc, #28] @ (8017dc4 ) 8017da6: 681b ldr r3, [r3, #0] 8017da8: 2b00 cmp r3, #0 8017daa: d105 bne.n 8017db8 8017dac: 2300 movs r3, #0 8017dae: 603b str r3, [r7, #0] __asm volatile 8017db0: 683b ldr r3, [r7, #0] 8017db2: f383 8811 msr BASEPRI, r3 } 8017db6: bf00 nop { portENABLE_INTERRUPTS(); } } 8017db8: bf00 nop 8017dba: 370c adds r7, #12 8017dbc: 46bd mov sp, r7 8017dbe: f85d 7b04 ldr.w r7, [sp], #4 8017dc2: 4770 bx lr 8017dc4: 200000a4 .word 0x200000a4 ... 08017dd0 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8017dd0: f3ef 8009 mrs r0, PSP 8017dd4: f3bf 8f6f isb sy 8017dd8: 4b15 ldr r3, [pc, #84] @ (8017e30 ) 8017dda: 681a ldr r2, [r3, #0] 8017ddc: f01e 0f10 tst.w lr, #16 8017de0: bf08 it eq 8017de2: ed20 8a10 vstmdbeq r0!, {s16-s31} 8017de6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017dea: 6010 str r0, [r2, #0] 8017dec: b409 push {r0, r3} 8017dee: f04f 0050 mov.w r0, #80 @ 0x50 8017df2: f380 8811 msr BASEPRI, r0 8017df6: f3bf 8f4f dsb sy 8017dfa: f3bf 8f6f isb sy 8017dfe: f7fe f943 bl 8016088 8017e02: f04f 0000 mov.w r0, #0 8017e06: f380 8811 msr BASEPRI, r0 8017e0a: bc09 pop {r0, r3} 8017e0c: 6819 ldr r1, [r3, #0] 8017e0e: 6808 ldr r0, [r1, #0] 8017e10: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017e14: f01e 0f10 tst.w lr, #16 8017e18: bf08 it eq 8017e1a: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8017e1e: f380 8809 msr PSP, r0 8017e22: f3bf 8f6f isb sy 8017e26: 4770 bx lr 8017e28: f3af 8000 nop.w 8017e2c: f3af 8000 nop.w 08017e30 : 8017e30: 20002168 .word 0x20002168 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); } 8017e34: bf00 nop 8017e36: bf00 nop 08017e38 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017e38: b580 push {r7, lr} 8017e3a: b082 sub sp, #8 8017e3c: af00 add r7, sp, #0 __asm volatile 8017e3e: f04f 0350 mov.w r3, #80 @ 0x50 8017e42: f383 8811 msr BASEPRI, r3 8017e46: f3bf 8f6f isb sy 8017e4a: f3bf 8f4f dsb sy 8017e4e: 607b str r3, [r7, #4] } 8017e50: bf00 nop * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8017e52: f7fe f801 bl 8015e58 8017e56: 4603 mov r3, r0 8017e58: 2b00 cmp r3, #0 8017e5a: d003 beq.n 8017e64 { /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 8017e5c: 4b06 ldr r3, [pc, #24] @ (8017e78 ) 8017e5e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8017e62: 601a str r2, [r3, #0] 8017e64: 2300 movs r3, #0 8017e66: 603b str r3, [r7, #0] __asm volatile 8017e68: 683b ldr r3, [r7, #0] 8017e6a: f383 8811 msr BASEPRI, r3 } 8017e6e: bf00 nop } } portENABLE_INTERRUPTS(); } 8017e70: bf00 nop 8017e72: 3708 adds r7, #8 8017e74: 46bd mov sp, r7 8017e76: bd80 pop {r7, pc} 8017e78: e000ed04 .word 0xe000ed04 08017e7c : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) { 8017e7c: b480 push {r7} 8017e7e: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8017e80: 4b0b ldr r3, [pc, #44] @ (8017eb0 ) 8017e82: 2200 movs r2, #0 8017e84: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8017e86: 4b0b ldr r3, [pc, #44] @ (8017eb4 ) 8017e88: 2200 movs r2, #0 8017e8a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 8017e8c: 4b0a ldr r3, [pc, #40] @ (8017eb8 ) 8017e8e: 681b ldr r3, [r3, #0] 8017e90: 4a0a ldr r2, [pc, #40] @ (8017ebc ) 8017e92: fba2 2303 umull r2, r3, r2, r3 8017e96: 099b lsrs r3, r3, #6 8017e98: 4a09 ldr r2, [pc, #36] @ (8017ec0 ) 8017e9a: 3b01 subs r3, #1 8017e9c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 8017e9e: 4b04 ldr r3, [pc, #16] @ (8017eb0 ) 8017ea0: 2207 movs r2, #7 8017ea2: 601a str r2, [r3, #0] } 8017ea4: bf00 nop 8017ea6: 46bd mov sp, r7 8017ea8: f85d 7b04 ldr.w r7, [sp], #4 8017eac: 4770 bx lr 8017eae: bf00 nop 8017eb0: e000e010 .word 0xe000e010 8017eb4: e000e018 .word 0xe000e018 8017eb8: 2000000c .word 0x2000000c 8017ebc: 10624dd3 .word 0x10624dd3 8017ec0: e000e014 .word 0xe000e014 08017ec4 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8017ec4: f8df 000c ldr.w r0, [pc, #12] @ 8017ed4 8017ec8: 6801 ldr r1, [r0, #0] 8017eca: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8017ece: 6001 str r1, [r0, #0] 8017ed0: 4770 bx lr 8017ed2: 0000 .short 0x0000 8017ed4: e000ed88 .word 0xe000ed88 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 \n" " .ltorg \n" ); } 8017ed8: bf00 nop 8017eda: bf00 nop 08017edc : /*-----------------------------------------------------------*/ #if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8017edc: b480 push {r7} 8017ede: b085 sub sp, #20 8017ee0: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); 8017ee2: f3ef 8305 mrs r3, IPSR 8017ee6: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8017ee8: 68fb ldr r3, [r7, #12] 8017eea: 2b0f cmp r3, #15 8017eec: d915 bls.n 8017f1a { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 8017eee: 4a18 ldr r2, [pc, #96] @ (8017f50 ) 8017ef0: 68fb ldr r3, [r7, #12] 8017ef2: 4413 add r3, r2 8017ef4: 781b ldrb r3, [r3, #0] 8017ef6: 72fb strb r3, [r7, #11] * interrupt entry is as fast and simple as possible. * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html * https://www.FreeRTOS.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8017ef8: 4b16 ldr r3, [pc, #88] @ (8017f54 ) 8017efa: 781b ldrb r3, [r3, #0] 8017efc: 7afa ldrb r2, [r7, #11] 8017efe: 429a cmp r2, r3 8017f00: d20b bcs.n 8017f1a __asm volatile 8017f02: f04f 0350 mov.w r3, #80 @ 0x50 8017f06: f383 8811 msr BASEPRI, r3 8017f0a: f3bf 8f6f isb sy 8017f0e: f3bf 8f4f dsb sy 8017f12: 607b str r3, [r7, #4] } 8017f14: bf00 nop 8017f16: bf00 nop 8017f18: e7fd b.n 8017f16 * configuration then the correct setting can be achieved on all Cortex-M * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the * scheduler. Note however that some vendor specific peripheral libraries * assume a non-zero priority group setting, in which cases using a value * of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8017f1a: 4b0f ldr r3, [pc, #60] @ (8017f58 ) 8017f1c: 681b ldr r3, [r3, #0] 8017f1e: f403 62e0 and.w r2, r3, #1792 @ 0x700 8017f22: 4b0e ldr r3, [pc, #56] @ (8017f5c ) 8017f24: 681b ldr r3, [r3, #0] 8017f26: 429a cmp r2, r3 8017f28: d90b bls.n 8017f42 __asm volatile 8017f2a: f04f 0350 mov.w r3, #80 @ 0x50 8017f2e: f383 8811 msr BASEPRI, r3 8017f32: f3bf 8f6f isb sy 8017f36: f3bf 8f4f dsb sy 8017f3a: 603b str r3, [r7, #0] } 8017f3c: bf00 nop 8017f3e: bf00 nop 8017f40: e7fd b.n 8017f3e } 8017f42: bf00 nop 8017f44: 3714 adds r7, #20 8017f46: 46bd mov sp, r7 8017f48: f85d 7b04 ldr.w r7, [sp], #4 8017f4c: 4770 bx lr 8017f4e: bf00 nop 8017f50: e000e3f0 .word 0xe000e3f0 8017f54: 20002794 .word 0x20002794 8017f58: e000ed0c .word 0xe000ed0c 8017f5c: 20002798 .word 0x20002798 08017f60 : PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0; /*-----------------------------------------------------------*/ void * pvPortMalloc( size_t xWantedSize ) { 8017f60: b580 push {r7, lr} 8017f62: b08a sub sp, #40 @ 0x28 8017f64: af00 add r7, sp, #0 8017f66: 6078 str r0, [r7, #4] BlockLink_t * pxBlock; BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; 8017f68: 2300 movs r3, #0 8017f6a: 61fb str r3, [r7, #28] size_t xAdditionalRequiredSize; vTaskSuspendAll(); 8017f6c: f7fd fe4c bl 8015c08 { /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 8017f70: 4b5c ldr r3, [pc, #368] @ (80180e4 ) 8017f72: 681b ldr r3, [r3, #0] 8017f74: 2b00 cmp r3, #0 8017f76: d101 bne.n 8017f7c { prvHeapInit(); 8017f78: f000 f918 bl 80181ac else { mtCOVERAGE_TEST_MARKER(); } if( xWantedSize > 0 ) 8017f7c: 687b ldr r3, [r7, #4] 8017f7e: 2b00 cmp r3, #0 8017f80: d022 beq.n 8017fc8 { /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) 8017f82: 2308 movs r3, #8 8017f84: 43db mvns r3, r3 8017f86: 687a ldr r2, [r7, #4] 8017f88: 429a cmp r2, r3 8017f8a: d81b bhi.n 8017fc4 { xWantedSize += xHeapStructSize; 8017f8c: 2208 movs r2, #8 8017f8e: 687b ldr r3, [r7, #4] 8017f90: 4413 add r3, r2 8017f92: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number * of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8017f94: 687b ldr r3, [r7, #4] 8017f96: f003 0307 and.w r3, r3, #7 8017f9a: 2b00 cmp r3, #0 8017f9c: d014 beq.n 8017fc8 { /* Byte alignment required. */ xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); 8017f9e: 687b ldr r3, [r7, #4] 8017fa0: f003 0307 and.w r3, r3, #7 8017fa4: f1c3 0308 rsb r3, r3, #8 8017fa8: 61bb str r3, [r7, #24] if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) 8017faa: 69bb ldr r3, [r7, #24] 8017fac: 43db mvns r3, r3 8017fae: 687a ldr r2, [r7, #4] 8017fb0: 429a cmp r2, r3 8017fb2: d804 bhi.n 8017fbe { xWantedSize += xAdditionalRequiredSize; 8017fb4: 687a ldr r2, [r7, #4] 8017fb6: 69bb ldr r3, [r7, #24] 8017fb8: 4413 add r3, r2 8017fba: 607b str r3, [r7, #4] 8017fbc: e004 b.n 8017fc8 } else { xWantedSize = 0; 8017fbe: 2300 movs r3, #0 8017fc0: 607b str r3, [r7, #4] 8017fc2: e001 b.n 8017fc8 mtCOVERAGE_TEST_MARKER(); } } else { xWantedSize = 0; 8017fc4: 2300 movs r3, #0 8017fc6: 607b str r3, [r7, #4] /* Check the block size we are trying to allocate is not so large that the * top bit is set. The top bit of the block size member of the BlockLink_t * structure is used to determine who owns the block - the application or * the kernel, so it must be free. */ if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) 8017fc8: 687b ldr r3, [r7, #4] 8017fca: 2b00 cmp r3, #0 8017fcc: db71 blt.n 80180b2 { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 8017fce: 687b ldr r3, [r7, #4] 8017fd0: 2b00 cmp r3, #0 8017fd2: d06e beq.n 80180b2 8017fd4: 4b44 ldr r3, [pc, #272] @ (80180e8 ) 8017fd6: 681b ldr r3, [r3, #0] 8017fd8: 687a ldr r2, [r7, #4] 8017fda: 429a cmp r2, r3 8017fdc: d869 bhi.n 80180b2 { /* Traverse the list from the start (lowest address) block until * one of adequate size is found. */ pxPreviousBlock = &xStart; 8017fde: 4b43 ldr r3, [pc, #268] @ (80180ec ) 8017fe0: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 8017fe2: 4b42 ldr r3, [pc, #264] @ (80180ec ) 8017fe4: 681b ldr r3, [r3, #0] 8017fe6: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017fe8: e004 b.n 8017ff4 { pxPreviousBlock = pxBlock; 8017fea: 6a7b ldr r3, [r7, #36] @ 0x24 8017fec: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 8017fee: 6a7b ldr r3, [r7, #36] @ 0x24 8017ff0: 681b ldr r3, [r3, #0] 8017ff2: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017ff4: 6a7b ldr r3, [r7, #36] @ 0x24 8017ff6: 685b ldr r3, [r3, #4] 8017ff8: 687a ldr r2, [r7, #4] 8017ffa: 429a cmp r2, r3 8017ffc: d903 bls.n 8018006 8017ffe: 6a7b ldr r3, [r7, #36] @ 0x24 8018000: 681b ldr r3, [r3, #0] 8018002: 2b00 cmp r3, #0 8018004: d1f1 bne.n 8017fea } /* If the end marker was reached then a block of adequate size * was not found. */ if( pxBlock != pxEnd ) 8018006: 4b37 ldr r3, [pc, #220] @ (80180e4 ) 8018008: 681b ldr r3, [r3, #0] 801800a: 6a7a ldr r2, [r7, #36] @ 0x24 801800c: 429a cmp r2, r3 801800e: d050 beq.n 80180b2 { /* Return the memory space pointed to - jumping over the * BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 8018010: 6a3b ldr r3, [r7, #32] 8018012: 681b ldr r3, [r3, #0] 8018014: 2208 movs r2, #8 8018016: 4413 add r3, r2 8018018: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out * of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 801801a: 6a7b ldr r3, [r7, #36] @ 0x24 801801c: 681a ldr r2, [r3, #0] 801801e: 6a3b ldr r3, [r7, #32] 8018020: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into * two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 8018022: 6a7b ldr r3, [r7, #36] @ 0x24 8018024: 685a ldr r2, [r3, #4] 8018026: 687b ldr r3, [r7, #4] 8018028: 1ad2 subs r2, r2, r3 801802a: 2308 movs r3, #8 801802c: 005b lsls r3, r3, #1 801802e: 429a cmp r2, r3 8018030: d920 bls.n 8018074 { /* This block is to be split into two. Create a new * block following the number of bytes requested. The void * cast is used to prevent byte alignment warnings from the * compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 8018032: 6a7a ldr r2, [r7, #36] @ 0x24 8018034: 687b ldr r3, [r7, #4] 8018036: 4413 add r3, r2 8018038: 617b str r3, [r7, #20] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 801803a: 697b ldr r3, [r7, #20] 801803c: f003 0307 and.w r3, r3, #7 8018040: 2b00 cmp r3, #0 8018042: d00b beq.n 801805c __asm volatile 8018044: f04f 0350 mov.w r3, #80 @ 0x50 8018048: f383 8811 msr BASEPRI, r3 801804c: f3bf 8f6f isb sy 8018050: f3bf 8f4f dsb sy 8018054: 613b str r3, [r7, #16] } 8018056: bf00 nop 8018058: bf00 nop 801805a: e7fd b.n 8018058 /* Calculate the sizes of two blocks split from the * single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 801805c: 6a7b ldr r3, [r7, #36] @ 0x24 801805e: 685a ldr r2, [r3, #4] 8018060: 687b ldr r3, [r7, #4] 8018062: 1ad2 subs r2, r2, r3 8018064: 697b ldr r3, [r7, #20] 8018066: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 8018068: 6a7b ldr r3, [r7, #36] @ 0x24 801806a: 687a ldr r2, [r7, #4] 801806c: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 801806e: 6978 ldr r0, [r7, #20] 8018070: f000 f8f8 bl 8018264 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 8018074: 4b1c ldr r3, [pc, #112] @ (80180e8 ) 8018076: 681a ldr r2, [r3, #0] 8018078: 6a7b ldr r3, [r7, #36] @ 0x24 801807a: 685b ldr r3, [r3, #4] 801807c: 1ad3 subs r3, r2, r3 801807e: 4a1a ldr r2, [pc, #104] @ (80180e8 ) 8018080: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 8018082: 4b19 ldr r3, [pc, #100] @ (80180e8 ) 8018084: 681a ldr r2, [r3, #0] 8018086: 4b1a ldr r3, [pc, #104] @ (80180f0 ) 8018088: 681b ldr r3, [r3, #0] 801808a: 429a cmp r2, r3 801808c: d203 bcs.n 8018096 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 801808e: 4b16 ldr r3, [pc, #88] @ (80180e8 ) 8018090: 681b ldr r3, [r3, #0] 8018092: 4a17 ldr r2, [pc, #92] @ (80180f0 ) 8018094: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned * by the application and has no "next" block. */ heapALLOCATE_BLOCK( pxBlock ); 8018096: 6a7b ldr r3, [r7, #36] @ 0x24 8018098: 685b ldr r3, [r3, #4] 801809a: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 801809e: 6a7b ldr r3, [r7, #36] @ 0x24 80180a0: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 80180a2: 6a7b ldr r3, [r7, #36] @ 0x24 80180a4: 2200 movs r2, #0 80180a6: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 80180a8: 4b12 ldr r3, [pc, #72] @ (80180f4 ) 80180aa: 681b ldr r3, [r3, #0] 80180ac: 3301 adds r3, #1 80180ae: 4a11 ldr r2, [pc, #68] @ (80180f4 ) 80180b0: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 80180b2: f7fd fdb7 bl 8015c24 mtCOVERAGE_TEST_MARKER(); } } #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 80180b6: 69fb ldr r3, [r7, #28] 80180b8: f003 0307 and.w r3, r3, #7 80180bc: 2b00 cmp r3, #0 80180be: d00b beq.n 80180d8 __asm volatile 80180c0: f04f 0350 mov.w r3, #80 @ 0x50 80180c4: f383 8811 msr BASEPRI, r3 80180c8: f3bf 8f6f isb sy 80180cc: f3bf 8f4f dsb sy 80180d0: 60fb str r3, [r7, #12] } 80180d2: bf00 nop 80180d4: bf00 nop 80180d6: e7fd b.n 80180d4 return pvReturn; 80180d8: 69fb ldr r3, [r7, #28] } 80180da: 4618 mov r0, r3 80180dc: 3728 adds r7, #40 @ 0x28 80180de: 46bd mov sp, r7 80180e0: bd80 pop {r7, pc} 80180e2: bf00 nop 80180e4: 200121a4 .word 0x200121a4 80180e8: 200121a8 .word 0x200121a8 80180ec: 2001219c .word 0x2001219c 80180f0: 200121ac .word 0x200121ac 80180f4: 200121b0 .word 0x200121b0 080180f8 : /*-----------------------------------------------------------*/ void vPortFree( void * pv ) { 80180f8: b580 push {r7, lr} 80180fa: b086 sub sp, #24 80180fc: af00 add r7, sp, #0 80180fe: 6078 str r0, [r7, #4] uint8_t * puc = ( uint8_t * ) pv; 8018100: 687b ldr r3, [r7, #4] 8018102: 617b str r3, [r7, #20] BlockLink_t * pxLink; if( pv != NULL ) 8018104: 687b ldr r3, [r7, #4] 8018106: 2b00 cmp r3, #0 8018108: d047 beq.n 801819a { /* The memory being freed will have an BlockLink_t structure immediately * before it. */ puc -= xHeapStructSize; 801810a: 2308 movs r3, #8 801810c: 425b negs r3, r3 801810e: 697a ldr r2, [r7, #20] 8018110: 4413 add r3, r2 8018112: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 8018114: 697b ldr r3, [r7, #20] 8018116: 613b str r3, [r7, #16] configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); 8018118: 693b ldr r3, [r7, #16] 801811a: 685b ldr r3, [r3, #4] 801811c: 2b00 cmp r3, #0 801811e: db0b blt.n 8018138 __asm volatile 8018120: f04f 0350 mov.w r3, #80 @ 0x50 8018124: f383 8811 msr BASEPRI, r3 8018128: f3bf 8f6f isb sy 801812c: f3bf 8f4f dsb sy 8018130: 60fb str r3, [r7, #12] } 8018132: bf00 nop 8018134: bf00 nop 8018136: e7fd b.n 8018134 configASSERT( pxLink->pxNextFreeBlock == NULL ); 8018138: 693b ldr r3, [r7, #16] 801813a: 681b ldr r3, [r3, #0] 801813c: 2b00 cmp r3, #0 801813e: d00b beq.n 8018158 __asm volatile 8018140: f04f 0350 mov.w r3, #80 @ 0x50 8018144: f383 8811 msr BASEPRI, r3 8018148: f3bf 8f6f isb sy 801814c: f3bf 8f4f dsb sy 8018150: 60bb str r3, [r7, #8] } 8018152: bf00 nop 8018154: bf00 nop 8018156: e7fd b.n 8018154 if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) 8018158: 693b ldr r3, [r7, #16] 801815a: 685b ldr r3, [r3, #4] 801815c: 2b00 cmp r3, #0 801815e: da1c bge.n 801819a { if( pxLink->pxNextFreeBlock == NULL ) 8018160: 693b ldr r3, [r7, #16] 8018162: 681b ldr r3, [r3, #0] 8018164: 2b00 cmp r3, #0 8018166: d118 bne.n 801819a { /* The block is being returned to the heap - it is no longer * allocated. */ heapFREE_BLOCK( pxLink ); 8018168: 693b ldr r3, [r7, #16] 801816a: 685b ldr r3, [r3, #4] 801816c: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8018170: 693b ldr r3, [r7, #16] 8018172: 605a str r2, [r3, #4] { ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); } #endif vTaskSuspendAll(); 8018174: f7fd fd48 bl 8015c08 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 8018178: 693b ldr r3, [r7, #16] 801817a: 685a ldr r2, [r3, #4] 801817c: 4b09 ldr r3, [pc, #36] @ (80181a4 ) 801817e: 681b ldr r3, [r3, #0] 8018180: 4413 add r3, r2 8018182: 4a08 ldr r2, [pc, #32] @ (80181a4 ) 8018184: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 8018186: 6938 ldr r0, [r7, #16] 8018188: f000 f86c bl 8018264 xNumberOfSuccessfulFrees++; 801818c: 4b06 ldr r3, [pc, #24] @ (80181a8 ) 801818e: 681b ldr r3, [r3, #0] 8018190: 3301 adds r3, #1 8018192: 4a05 ldr r2, [pc, #20] @ (80181a8 ) 8018194: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8018196: f7fd fd45 bl 8015c24 else { mtCOVERAGE_TEST_MARKER(); } } } 801819a: bf00 nop 801819c: 3718 adds r7, #24 801819e: 46bd mov sp, r7 80181a0: bd80 pop {r7, pc} 80181a2: bf00 nop 80181a4: 200121a8 .word 0x200121a8 80181a8: 200121b4 .word 0x200121b4 080181ac : return pv; } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ { 80181ac: b480 push {r7} 80181ae: b085 sub sp, #20 80181b0: af00 add r7, sp, #0 BlockLink_t * pxFirstFreeBlock; uint8_t * pucAlignedHeap; portPOINTER_SIZE_TYPE uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 80181b2: f44f 437a mov.w r3, #64000 @ 0xfa00 80181b6: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( portPOINTER_SIZE_TYPE ) ucHeap; 80181b8: 4b25 ldr r3, [pc, #148] @ (8018250 ) 80181ba: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 80181bc: 68fb ldr r3, [r7, #12] 80181be: f003 0307 and.w r3, r3, #7 80181c2: 2b00 cmp r3, #0 80181c4: d00c beq.n 80181e0 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 80181c6: 68fb ldr r3, [r7, #12] 80181c8: 3307 adds r3, #7 80181ca: 60fb str r3, [r7, #12] uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); 80181cc: 68fb ldr r3, [r7, #12] 80181ce: f023 0307 bic.w r3, r3, #7 80181d2: 60fb str r3, [r7, #12] xTotalHeapSize -= ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) ucHeap ); 80181d4: 68ba ldr r2, [r7, #8] 80181d6: 68fb ldr r3, [r7, #12] 80181d8: 1ad3 subs r3, r2, r3 80181da: 4a1d ldr r2, [pc, #116] @ (8018250 ) 80181dc: 4413 add r3, r2 80181de: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 80181e0: 68fb ldr r3, [r7, #12] 80181e2: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free * blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 80181e4: 4a1b ldr r2, [pc, #108] @ (8018254 ) 80181e6: 687b ldr r3, [r7, #4] 80181e8: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 80181ea: 4b1a ldr r3, [pc, #104] @ (8018254 ) 80181ec: 2200 movs r2, #0 80181ee: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted * at the end of the heap space. */ uxAddress = ( portPOINTER_SIZE_TYPE ) ( pucAlignedHeap + xTotalHeapSize ); 80181f0: 687a ldr r2, [r7, #4] 80181f2: 68bb ldr r3, [r7, #8] 80181f4: 4413 add r3, r2 80181f6: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 80181f8: 2208 movs r2, #8 80181fa: 68fb ldr r3, [r7, #12] 80181fc: 1a9b subs r3, r3, r2 80181fe: 60fb str r3, [r7, #12] uxAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); 8018200: 68fb ldr r3, [r7, #12] 8018202: f023 0307 bic.w r3, r3, #7 8018206: 60fb str r3, [r7, #12] pxEnd = ( BlockLink_t * ) uxAddress; 8018208: 68fb ldr r3, [r7, #12] 801820a: 4a13 ldr r2, [pc, #76] @ (8018258 ) 801820c: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 801820e: 4b12 ldr r3, [pc, #72] @ (8018258 ) 8018210: 681b ldr r3, [r3, #0] 8018212: 2200 movs r2, #0 8018214: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 8018216: 4b10 ldr r3, [pc, #64] @ (8018258 ) 8018218: 681b ldr r3, [r3, #0] 801821a: 2200 movs r2, #0 801821c: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the * entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap; 801821e: 687b ldr r3, [r7, #4] 8018220: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock ); 8018222: 683b ldr r3, [r7, #0] 8018224: 68fa ldr r2, [r7, #12] 8018226: 1ad2 subs r2, r2, r3 8018228: 683b ldr r3, [r7, #0] 801822a: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 801822c: 4b0a ldr r3, [pc, #40] @ (8018258 ) 801822e: 681a ldr r2, [r3, #0] 8018230: 683b ldr r3, [r7, #0] 8018232: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8018234: 683b ldr r3, [r7, #0] 8018236: 685b ldr r3, [r3, #4] 8018238: 4a08 ldr r2, [pc, #32] @ (801825c ) 801823a: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 801823c: 683b ldr r3, [r7, #0] 801823e: 685b ldr r3, [r3, #4] 8018240: 4a07 ldr r2, [pc, #28] @ (8018260 ) 8018242: 6013 str r3, [r2, #0] } 8018244: bf00 nop 8018246: 3714 adds r7, #20 8018248: 46bd mov sp, r7 801824a: f85d 7b04 ldr.w r7, [sp], #4 801824e: 4770 bx lr 8018250: 2000279c .word 0x2000279c 8018254: 2001219c .word 0x2001219c 8018258: 200121a4 .word 0x200121a4 801825c: 200121ac .word 0x200121ac 8018260: 200121a8 .word 0x200121a8 08018264 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ { 8018264: b480 push {r7} 8018266: b085 sub sp, #20 8018268: af00 add r7, sp, #0 801826a: 6078 str r0, [r7, #4] BlockLink_t * pxIterator; uint8_t * puc; /* Iterate through the list until a block is found that has a higher address * than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 801826c: 4b28 ldr r3, [pc, #160] @ (8018310 ) 801826e: 60fb str r3, [r7, #12] 8018270: e002 b.n 8018278 8018272: 68fb ldr r3, [r7, #12] 8018274: 681b ldr r3, [r3, #0] 8018276: 60fb str r3, [r7, #12] 8018278: 68fb ldr r3, [r7, #12] 801827a: 681b ldr r3, [r3, #0] 801827c: 687a ldr r2, [r7, #4] 801827e: 429a cmp r2, r3 8018280: d8f7 bhi.n 8018272 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after * make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8018282: 68fb ldr r3, [r7, #12] 8018284: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8018286: 68fb ldr r3, [r7, #12] 8018288: 685b ldr r3, [r3, #4] 801828a: 68ba ldr r2, [r7, #8] 801828c: 4413 add r3, r2 801828e: 687a ldr r2, [r7, #4] 8018290: 429a cmp r2, r3 8018292: d108 bne.n 80182a6 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 8018294: 68fb ldr r3, [r7, #12] 8018296: 685a ldr r2, [r3, #4] 8018298: 687b ldr r3, [r7, #4] 801829a: 685b ldr r3, [r3, #4] 801829c: 441a add r2, r3 801829e: 68fb ldr r3, [r7, #12] 80182a0: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 80182a2: 68fb ldr r3, [r7, #12] 80182a4: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before * make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 80182a6: 687b ldr r3, [r7, #4] 80182a8: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 80182aa: 687b ldr r3, [r7, #4] 80182ac: 685b ldr r3, [r3, #4] 80182ae: 68ba ldr r2, [r7, #8] 80182b0: 441a add r2, r3 80182b2: 68fb ldr r3, [r7, #12] 80182b4: 681b ldr r3, [r3, #0] 80182b6: 429a cmp r2, r3 80182b8: d118 bne.n 80182ec { if( pxIterator->pxNextFreeBlock != pxEnd ) 80182ba: 68fb ldr r3, [r7, #12] 80182bc: 681a ldr r2, [r3, #0] 80182be: 4b15 ldr r3, [pc, #84] @ (8018314 ) 80182c0: 681b ldr r3, [r3, #0] 80182c2: 429a cmp r2, r3 80182c4: d00d beq.n 80182e2 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 80182c6: 687b ldr r3, [r7, #4] 80182c8: 685a ldr r2, [r3, #4] 80182ca: 68fb ldr r3, [r7, #12] 80182cc: 681b ldr r3, [r3, #0] 80182ce: 685b ldr r3, [r3, #4] 80182d0: 441a add r2, r3 80182d2: 687b ldr r3, [r7, #4] 80182d4: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 80182d6: 68fb ldr r3, [r7, #12] 80182d8: 681b ldr r3, [r3, #0] 80182da: 681a ldr r2, [r3, #0] 80182dc: 687b ldr r3, [r7, #4] 80182de: 601a str r2, [r3, #0] 80182e0: e008 b.n 80182f4 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 80182e2: 4b0c ldr r3, [pc, #48] @ (8018314 ) 80182e4: 681a ldr r2, [r3, #0] 80182e6: 687b ldr r3, [r7, #4] 80182e8: 601a str r2, [r3, #0] 80182ea: e003 b.n 80182f4 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 80182ec: 68fb ldr r3, [r7, #12] 80182ee: 681a ldr r2, [r3, #0] 80182f0: 687b ldr r3, [r7, #4] 80182f2: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block * before and the block after, then it's pxNextFreeBlock pointer will have * already been set, and should not be set here as that would make it point * to itself. */ if( pxIterator != pxBlockToInsert ) 80182f4: 68fa ldr r2, [r7, #12] 80182f6: 687b ldr r3, [r7, #4] 80182f8: 429a cmp r2, r3 80182fa: d002 beq.n 8018302 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 80182fc: 68fb ldr r3, [r7, #12] 80182fe: 687a ldr r2, [r7, #4] 8018300: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8018302: bf00 nop 8018304: 3714 adds r7, #20 8018306: 46bd mov sp, r7 8018308: f85d 7b04 ldr.w r7, [sp], #4 801830c: 4770 bx lr 801830e: bf00 nop 8018310: 2001219c .word 0x2001219c 8018314: 200121a4 .word 0x200121a4 08018318 : { 8018318: b480 push {r7} 801831a: af00 add r7, sp, #0 SET_BIT(PWR->CR4, PWR_CR4_C2BOOT); 801831c: 4b05 ldr r3, [pc, #20] @ (8018334 ) 801831e: 68db ldr r3, [r3, #12] 8018320: 4a04 ldr r2, [pc, #16] @ (8018334 ) 8018322: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8018326: 60d3 str r3, [r2, #12] } 8018328: bf00 nop 801832a: 46bd mov sp, r7 801832c: f85d 7b04 ldr.w r7, [sp], #4 8018330: 4770 bx lr 8018332: bf00 nop 8018334: 58000400 .word 0x58000400 08018338 : { 8018338: b480 push {r7} 801833a: b083 sub sp, #12 801833c: af00 add r7, sp, #0 801833e: 6078 str r0, [r7, #4] SET_BIT(EXTI->C2EMR2, ExtiLine); 8018340: 4b06 ldr r3, [pc, #24] @ (801835c ) 8018342: f8d3 20d4 ldr.w r2, [r3, #212] @ 0xd4 8018346: 4905 ldr r1, [pc, #20] @ (801835c ) 8018348: 687b ldr r3, [r7, #4] 801834a: 4313 orrs r3, r2 801834c: f8c1 30d4 str.w r3, [r1, #212] @ 0xd4 } 8018350: bf00 nop 8018352: 370c adds r7, #12 8018354: 46bd mov sp, r7 8018356: f85d 7b04 ldr.w r7, [sp], #4 801835a: 4770 bx lr 801835c: 58000800 .word 0x58000800 08018360 : * @arg @ref LL_EXTI_LINE_41 * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) { 8018360: b480 push {r7} 8018362: b083 sub sp, #12 8018364: af00 add r7, sp, #0 8018366: 6078 str r0, [r7, #4] SET_BIT(EXTI->RTSR2, ExtiLine); 8018368: 4b05 ldr r3, [pc, #20] @ (8018380 ) 801836a: 6a1a ldr r2, [r3, #32] 801836c: 4904 ldr r1, [pc, #16] @ (8018380 ) 801836e: 687b ldr r3, [r7, #4] 8018370: 4313 orrs r3, r2 8018372: 620b str r3, [r1, #32] } 8018374: bf00 nop 8018376: 370c adds r7, #12 8018378: 46bd mov sp, r7 801837a: f85d 7b04 ldr.w r7, [sp], #4 801837e: 4770 bx lr 8018380: 58000800 .word 0x58000800 08018384 : { 8018384: b480 push {r7} 8018386: b085 sub sp, #20 8018388: af00 add r7, sp, #0 801838a: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB3ENR, Periphs); 801838c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8018390: 6d1a ldr r2, [r3, #80] @ 0x50 8018392: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8018396: 687b ldr r3, [r7, #4] 8018398: 4313 orrs r3, r2 801839a: 650b str r3, [r1, #80] @ 0x50 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 801839c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80183a0: 6d1a ldr r2, [r3, #80] @ 0x50 80183a2: 687b ldr r3, [r7, #4] 80183a4: 4013 ands r3, r2 80183a6: 60fb str r3, [r7, #12] (void)tmpreg; 80183a8: 68fb ldr r3, [r7, #12] } 80183aa: bf00 nop 80183ac: 3714 adds r7, #20 80183ae: 46bd mov sp, r7 80183b0: f85d 7b04 ldr.w r7, [sp], #4 80183b4: 4770 bx lr 080183b6 : * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH * @retval None */ __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) { 80183b6: b480 push {r7} 80183b8: b085 sub sp, #20 80183ba: af00 add r7, sp, #0 80183bc: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->C2AHB3ENR, Periphs); 80183be: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80183c2: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 80183c6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80183ca: 687b ldr r3, [r7, #4] 80183cc: 4313 orrs r3, r2 80183ce: f8c1 3150 str.w r3, [r1, #336] @ 0x150 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs); 80183d2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80183d6: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 80183da: 687b ldr r3, [r7, #4] 80183dc: 4013 ands r3, r2 80183de: 60fb str r3, [r7, #12] (void)tmpreg; 80183e0: 68fb ldr r3, [r7, #12] } 80183e2: bf00 nop 80183e4: 3714 adds r7, #20 80183e6: 46bd mov sp, r7 80183e8: f85d 7b04 ldr.w r7, [sp], #4 80183ec: 4770 bx lr 080183ee : * @rmtoll C1CR TXFIE LL_C1_IPCC_EnableIT_TXF * @param IPCCx IPCC Instance. * @retval None */ __STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx) { 80183ee: b480 push {r7} 80183f0: b083 sub sp, #12 80183f2: af00 add r7, sp, #0 80183f4: 6078 str r0, [r7, #4] SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE); 80183f6: 687b ldr r3, [r7, #4] 80183f8: 681b ldr r3, [r3, #0] 80183fa: f443 3280 orr.w r2, r3, #65536 @ 0x10000 80183fe: 687b ldr r3, [r7, #4] 8018400: 601a str r2, [r3, #0] } 8018402: bf00 nop 8018404: 370c adds r7, #12 8018406: 46bd mov sp, r7 8018408: f85d 7b04 ldr.w r7, [sp], #4 801840c: 4770 bx lr 0801840e : * @rmtoll C1CR RXOIE LL_C1_IPCC_EnableIT_RXO * @param IPCCx IPCC Instance. * @retval None */ __STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx) { 801840e: b480 push {r7} 8018410: b083 sub sp, #12 8018412: af00 add r7, sp, #0 8018414: 6078 str r0, [r7, #4] SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE); 8018416: 687b ldr r3, [r7, #4] 8018418: 681b ldr r3, [r3, #0] 801841a: f043 0201 orr.w r2, r3, #1 801841e: 687b ldr r3, [r7, #4] 8018420: 601a str r2, [r3, #0] } 8018422: bf00 nop 8018424: 370c adds r7, #12 8018426: 46bd mov sp, r7 8018428: f85d 7b04 ldr.w r7, [sp], #4 801842c: 4770 bx lr 0801842e : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) { 801842e: b480 push {r7} 8018430: b083 sub sp, #12 8018432: af00 add r7, sp, #0 8018434: 6078 str r0, [r7, #4] 8018436: 6039 str r1, [r7, #0] CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); 8018438: 687b ldr r3, [r7, #4] 801843a: 685a ldr r2, [r3, #4] 801843c: 683b ldr r3, [r7, #0] 801843e: 041b lsls r3, r3, #16 8018440: 43db mvns r3, r3 8018442: 401a ands r2, r3 8018444: 687b ldr r3, [r7, #4] 8018446: 605a str r2, [r3, #4] } 8018448: bf00 nop 801844a: 370c adds r7, #12 801844c: 46bd mov sp, r7 801844e: f85d 7b04 ldr.w r7, [sp], #4 8018452: 4770 bx lr 08018454 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) { 8018454: b480 push {r7} 8018456: b083 sub sp, #12 8018458: af00 add r7, sp, #0 801845a: 6078 str r0, [r7, #4] 801845c: 6039 str r1, [r7, #0] SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos); 801845e: 687b ldr r3, [r7, #4] 8018460: 685a ldr r2, [r3, #4] 8018462: 683b ldr r3, [r7, #0] 8018464: 041b lsls r3, r3, #16 8018466: 431a orrs r2, r3 8018468: 687b ldr r3, [r7, #4] 801846a: 605a str r2, [r3, #4] } 801846c: bf00 nop 801846e: 370c adds r7, #12 8018470: 46bd mov sp, r7 8018472: f85d 7b04 ldr.w r7, [sp], #4 8018476: 4770 bx lr 08018478 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel) { 8018478: b480 push {r7} 801847a: b083 sub sp, #12 801847c: af00 add r7, sp, #0 801847e: 6078 str r0, [r7, #4] 8018480: 6039 str r1, [r7, #0] CLEAR_BIT(IPCCx->C1MR, Channel); 8018482: 687b ldr r3, [r7, #4] 8018484: 685a ldr r2, [r3, #4] 8018486: 683b ldr r3, [r7, #0] 8018488: 43db mvns r3, r3 801848a: 401a ands r2, r3 801848c: 687b ldr r3, [r7, #4] 801848e: 605a str r2, [r3, #4] } 8018490: bf00 nop 8018492: 370c adds r7, #12 8018494: 46bd mov sp, r7 8018496: f85d 7b04 ldr.w r7, [sp], #4 801849a: 4770 bx lr 0801849c : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel) { 801849c: b480 push {r7} 801849e: b083 sub sp, #12 80184a0: af00 add r7, sp, #0 80184a2: 6078 str r0, [r7, #4] 80184a4: 6039 str r1, [r7, #0] WRITE_REG(IPCCx->C1SCR, Channel); 80184a6: 687b ldr r3, [r7, #4] 80184a8: 683a ldr r2, [r7, #0] 80184aa: 609a str r2, [r3, #8] } 80184ac: bf00 nop 80184ae: 370c adds r7, #12 80184b0: 46bd mov sp, r7 80184b2: f85d 7b04 ldr.w r7, [sp], #4 80184b6: 4770 bx lr 080184b8 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval None */ __STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel) { 80184b8: b480 push {r7} 80184ba: b083 sub sp, #12 80184bc: af00 add r7, sp, #0 80184be: 6078 str r0, [r7, #4] 80184c0: 6039 str r1, [r7, #0] WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos); 80184c2: 683b ldr r3, [r7, #0] 80184c4: 041a lsls r2, r3, #16 80184c6: 687b ldr r3, [r7, #4] 80184c8: 609a str r2, [r3, #8] } 80184ca: bf00 nop 80184cc: 370c adds r7, #12 80184ce: 46bd mov sp, r7 80184d0: f85d 7b04 ldr.w r7, [sp], #4 80184d4: 4770 bx lr 080184d6 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel) { 80184d6: b480 push {r7} 80184d8: b083 sub sp, #12 80184da: af00 add r7, sp, #0 80184dc: 6078 str r0, [r7, #4] 80184de: 6039 str r1, [r7, #0] return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL); 80184e0: 687b ldr r3, [r7, #4] 80184e2: 68da ldr r2, [r3, #12] 80184e4: 683b ldr r3, [r7, #0] 80184e6: 4013 ands r3, r2 80184e8: 683a ldr r2, [r7, #0] 80184ea: 429a cmp r2, r3 80184ec: d101 bne.n 80184f2 80184ee: 2301 movs r3, #1 80184f0: e000 b.n 80184f4 80184f2: 2300 movs r3, #0 } 80184f4: 4618 mov r0, r3 80184f6: 370c adds r7, #12 80184f8: 46bd mov sp, r7 80184fa: f85d 7b04 ldr.w r7, [sp], #4 80184fe: 4770 bx lr 08018500 : * @arg @ref LL_IPCC_CHANNEL_5 * @arg @ref LL_IPCC_CHANNEL_6 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef const *const IPCCx, uint32_t Channel) { 8018500: b480 push {r7} 8018502: b083 sub sp, #12 8018504: af00 add r7, sp, #0 8018506: 6078 str r0, [r7, #4] 8018508: 6039 str r1, [r7, #0] return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL); 801850a: 687b ldr r3, [r7, #4] 801850c: 69da ldr r2, [r3, #28] 801850e: 683b ldr r3, [r7, #0] 8018510: 4013 ands r3, r2 8018512: 683a ldr r2, [r7, #0] 8018514: 429a cmp r2, r3 8018516: d101 bne.n 801851c 8018518: 2301 movs r3, #1 801851a: e000 b.n 801851e 801851c: 2300 movs r3, #0 } 801851e: 4618 mov r0, r3 8018520: 370c adds r7, #12 8018522: 46bd mov sp, r7 8018524: f85d 7b04 ldr.w r7, [sp], #4 8018528: 4770 bx lr ... 0801852c : /****************************************************************************** * INTERRUPT HANDLER ******************************************************************************/ void HW_IPCC_Rx_Handler( void ) { 801852c: b580 push {r7, lr} 801852e: af00 add r7, sp, #0 if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL )) 8018530: 2102 movs r1, #2 8018532: 4818 ldr r0, [pc, #96] @ (8018594 ) 8018534: f7ff ffe4 bl 8018500 8018538: 4603 mov r3, r0 801853a: 2b00 cmp r3, #0 801853c: d008 beq.n 8018550 801853e: 4b15 ldr r3, [pc, #84] @ (8018594 ) 8018540: 685b ldr r3, [r3, #4] 8018542: f003 0302 and.w r3, r3, #2 8018546: 2b00 cmp r3, #0 8018548: d102 bne.n 8018550 { HW_IPCC_SYS_EvtHandler(); 801854a: f000 f901 bl 8018750 801854e: e01e b.n 801858e else if (HW_IPCC_RX_PENDING( HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL )) { HW_IPCC_ZIGBEE_StackM0RequestHandler(); } #endif /* ZIGBEE_WB */ else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL )) 8018550: 2101 movs r1, #1 8018552: 4810 ldr r0, [pc, #64] @ (8018594 ) 8018554: f7ff ffd4 bl 8018500 8018558: 4603 mov r3, r0 801855a: 2b00 cmp r3, #0 801855c: d008 beq.n 8018570 801855e: 4b0d ldr r3, [pc, #52] @ (8018594 ) 8018560: 685b ldr r3, [r3, #4] 8018562: f003 0301 and.w r3, r3, #1 8018566: 2b00 cmp r3, #0 8018568: d102 bne.n 8018570 { HW_IPCC_BLE_EvtHandler(); 801856a: f000 f875 bl 8018658 801856e: e00e b.n 801858e } else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL )) 8018570: 2108 movs r1, #8 8018572: 4808 ldr r0, [pc, #32] @ (8018594 ) 8018574: f7ff ffc4 bl 8018500 8018578: 4603 mov r3, r0 801857a: 2b00 cmp r3, #0 801857c: d008 beq.n 8018590 801857e: 4b05 ldr r3, [pc, #20] @ (8018594 ) 8018580: 685b ldr r3, [r3, #4] 8018582: f003 0308 and.w r3, r3, #8 8018586: 2b00 cmp r3, #0 8018588: d102 bne.n 8018590 { HW_IPCC_TRACES_EvtHandler(); 801858a: f000 f959 bl 8018840 } return; 801858e: bf00 nop 8018590: bf00 nop } 8018592: bd80 pop {r7, pc} 8018594: 58000c00 .word 0x58000c00 08018598 : void HW_IPCC_Tx_Handler( void ) { 8018598: b580 push {r7, lr} 801859a: af00 add r7, sp, #0 if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL )) 801859c: 2102 movs r1, #2 801859e: 4818 ldr r0, [pc, #96] @ (8018600 ) 80185a0: f7ff ff99 bl 80184d6 80185a4: 4603 mov r3, r0 80185a6: 2b00 cmp r3, #0 80185a8: d108 bne.n 80185bc 80185aa: 4b15 ldr r3, [pc, #84] @ (8018600 ) 80185ac: 685b ldr r3, [r3, #4] 80185ae: f403 3300 and.w r3, r3, #131072 @ 0x20000 80185b2: 2b00 cmp r3, #0 80185b4: d102 bne.n 80185bc { HW_IPCC_SYS_CmdEvtHandler(); 80185b6: f000 f8af bl 8018718 80185ba: e01e b.n 80185fa if (HW_IPCC_TX_PENDING( HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL )) { HW_IPCC_ZIGBEE_CmdEvtHandler(); } #endif /* ZIGBEE_WB */ else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL )) 80185bc: 2108 movs r1, #8 80185be: 4810 ldr r0, [pc, #64] @ (8018600 ) 80185c0: f7ff ff89 bl 80184d6 80185c4: 4603 mov r3, r0 80185c6: 2b00 cmp r3, #0 80185c8: d108 bne.n 80185dc 80185ca: 4b0d ldr r3, [pc, #52] @ (8018600 ) 80185cc: 685b ldr r3, [r3, #4] 80185ce: f403 2300 and.w r3, r3, #524288 @ 0x80000 80185d2: 2b00 cmp r3, #0 80185d4: d102 bne.n 80185dc { HW_IPCC_MM_FreeBufHandler(); 80185d6: f000 f8f5 bl 80187c4 80185da: e00e b.n 80185fa } else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL )) 80185dc: 2120 movs r1, #32 80185de: 4808 ldr r0, [pc, #32] @ (8018600 ) 80185e0: f7ff ff79 bl 80184d6 80185e4: 4603 mov r3, r0 80185e6: 2b00 cmp r3, #0 80185e8: d108 bne.n 80185fc 80185ea: 4b05 ldr r3, [pc, #20] @ (8018600 ) 80185ec: 685b ldr r3, [r3, #4] 80185ee: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80185f2: 2b00 cmp r3, #0 80185f4: d102 bne.n 80185fc { HW_IPCC_BLE_AclDataEvtHandler(); 80185f6: f000 f83b bl 8018670 } return; 80185fa: bf00 nop 80185fc: bf00 nop } 80185fe: bd80 pop {r7, pc} 8018600: 58000c00 .word 0x58000c00 08018604 : /****************************************************************************** * GENERAL ******************************************************************************/ void HW_IPCC_Enable( void ) { 8018604: b580 push {r7, lr} 8018606: af00 add r7, sp, #0 /** * Such as IPCC IP available to the CPU2, it is required to keep the IPCC clock running * when FUS is running on CPU2 and CPU1 enters deep sleep mode */ LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC); 8018608: f44f 1080 mov.w r0, #1048576 @ 0x100000 801860c: f7ff fed3 bl 80183b6 /** * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2 */ LL_EXTI_EnableRisingTrig_32_63( LL_EXTI_LINE_41 ); 8018610: f44f 7000 mov.w r0, #512 @ 0x200 8018614: f7ff fea4 bl 8018360 /* It is required to have at least a system clock cycle before a SEV after LL_EXTI_EnableRisingTrig_32_63() */ LL_C2_EXTI_EnableEvent_32_63( LL_EXTI_LINE_41 ); 8018618: f44f 7000 mov.w r0, #512 @ 0x200 801861c: f7ff fe8c bl 8018338 * When the CPU2 receives that command, it waits for its event input to be set to restart the CPU2 firmware. * This is required because once C2BOOT has been set once, a clear/set on C2BOOT has no effect. * When SHCI_C2_Reinit( ) is not called, generating an event to the CPU2 does not have any effect * So, by default, the application shall both set the event flag and set the C2BOOT bit. */ __SEV( ); /* Set the internal event flag and send an event to the CPU2 */ 8018620: bf40 sev __WFE( ); /* Clear the internal event flag */ 8018622: bf20 wfe LL_PWR_EnableBootC2( ); 8018624: f7ff fe78 bl 8018318 return; 8018628: bf00 nop } 801862a: bd80 pop {r7, pc} 0801862c : void HW_IPCC_Init( void ) { 801862c: b580 push {r7, lr} 801862e: af00 add r7, sp, #0 LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC ); 8018630: f44f 1080 mov.w r0, #1048576 @ 0x100000 8018634: f7ff fea6 bl 8018384 LL_C1_IPCC_EnableIT_RXO( IPCC ); 8018638: 4806 ldr r0, [pc, #24] @ (8018654 ) 801863a: f7ff fee8 bl 801840e LL_C1_IPCC_EnableIT_TXF( IPCC ); 801863e: 4805 ldr r0, [pc, #20] @ (8018654 ) 8018640: f7ff fed5 bl 80183ee HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn); 8018644: 202c movs r0, #44 @ 0x2c 8018646: f7ee facd bl 8006be4 HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn); 801864a: 202d movs r0, #45 @ 0x2d 801864c: f7ee faca bl 8006be4 return; 8018650: bf00 nop } 8018652: bd80 pop {r7, pc} 8018654: 58000c00 .word 0x58000c00 08018658 : return; } static void HW_IPCC_BLE_EvtHandler( void ) { 8018658: b580 push {r7, lr} 801865a: af00 add r7, sp, #0 HW_IPCC_BLE_RxEvtNot(); 801865c: f7fa fe18 bl 8013290 LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL ); 8018660: 2101 movs r1, #1 8018662: 4802 ldr r0, [pc, #8] @ (801866c ) 8018664: f7ff ff1a bl 801849c return; 8018668: bf00 nop } 801866a: bd80 pop {r7, pc} 801866c: 58000c00 .word 0x58000c00 08018670 : return; } static void HW_IPCC_BLE_AclDataEvtHandler( void ) { 8018670: b580 push {r7, lr} 8018672: b084 sub sp, #16 8018674: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8018676: f3ef 8310 mrs r3, PRIMASK 801867a: 607b str r3, [r7, #4] return(result); 801867c: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 801867e: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 8018680: b672 cpsid i } 8018682: bf00 nop LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL ); 8018684: 2120 movs r1, #32 8018686: 4807 ldr r0, [pc, #28] @ (80186a4 ) 8018688: f7ff fee4 bl 8018454 801868c: 68fb ldr r3, [r7, #12] 801868e: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8018690: 68bb ldr r3, [r7, #8] 8018692: f383 8810 msr PRIMASK, r3 } 8018696: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); HW_IPCC_BLE_AclDataAckNot(); 8018698: f7fa fe2a bl 80132f0 return; 801869c: bf00 nop } 801869e: 3710 adds r7, #16 80186a0: 46bd mov sp, r7 80186a2: bd80 pop {r7, pc} 80186a4: 58000c00 .word 0x58000c00 080186a8 : /****************************************************************************** * SYSTEM ******************************************************************************/ void HW_IPCC_SYS_Init( void ) { 80186a8: b580 push {r7, lr} 80186aa: b084 sub sp, #16 80186ac: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80186ae: f3ef 8310 mrs r3, PRIMASK 80186b2: 607b str r3, [r7, #4] return(result); 80186b4: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 80186b6: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 80186b8: b672 cpsid i } 80186ba: bf00 nop LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL ); 80186bc: 2102 movs r1, #2 80186be: 4806 ldr r0, [pc, #24] @ (80186d8 ) 80186c0: f7ff feda bl 8018478 80186c4: 68fb ldr r3, [r7, #12] 80186c6: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80186c8: 68bb ldr r3, [r7, #8] 80186ca: f383 8810 msr PRIMASK, r3 } 80186ce: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); return; 80186d0: bf00 nop } 80186d2: 3710 adds r7, #16 80186d4: 46bd mov sp, r7 80186d6: bd80 pop {r7, pc} 80186d8: 58000c00 .word 0x58000c00 080186dc : void HW_IPCC_SYS_SendCmd( void ) { 80186dc: b580 push {r7, lr} 80186de: b084 sub sp, #16 80186e0: af00 add r7, sp, #0 LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); 80186e2: 2102 movs r1, #2 80186e4: 480b ldr r0, [pc, #44] @ (8018714 ) 80186e6: f7ff fee7 bl 80184b8 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80186ea: f3ef 8310 mrs r3, PRIMASK 80186ee: 607b str r3, [r7, #4] return(result); 80186f0: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 80186f2: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 80186f4: b672 cpsid i } 80186f6: bf00 nop LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); 80186f8: 2102 movs r1, #2 80186fa: 4806 ldr r0, [pc, #24] @ (8018714 ) 80186fc: f7ff fe97 bl 801842e 8018700: 68fb ldr r3, [r7, #12] 8018702: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8018704: 68bb ldr r3, [r7, #8] 8018706: f383 8810 msr PRIMASK, r3 } 801870a: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); return; 801870c: bf00 nop } 801870e: 3710 adds r7, #16 8018710: 46bd mov sp, r7 8018712: bd80 pop {r7, pc} 8018714: 58000c00 .word 0x58000c00 08018718 : static void HW_IPCC_SYS_CmdEvtHandler( void ) { 8018718: b580 push {r7, lr} 801871a: b084 sub sp, #16 801871c: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 801871e: f3ef 8310 mrs r3, PRIMASK 8018722: 607b str r3, [r7, #4] return(result); 8018724: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 8018726: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 8018728: b672 cpsid i } 801872a: bf00 nop LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ); 801872c: 2102 movs r1, #2 801872e: 4807 ldr r0, [pc, #28] @ (801874c ) 8018730: f7ff fe90 bl 8018454 8018734: 68fb ldr r3, [r7, #12] 8018736: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8018738: 68bb ldr r3, [r7, #8] 801873a: f383 8810 msr PRIMASK, r3 } 801873e: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); HW_IPCC_SYS_CmdEvtNot(); 8018740: f7fa fe2a bl 8013398 return; 8018744: bf00 nop } 8018746: 3710 adds r7, #16 8018748: 46bd mov sp, r7 801874a: bd80 pop {r7, pc} 801874c: 58000c00 .word 0x58000c00 08018750 : static void HW_IPCC_SYS_EvtHandler( void ) { 8018750: b580 push {r7, lr} 8018752: af00 add r7, sp, #0 HW_IPCC_SYS_EvtNot(); 8018754: f7fa fe36 bl 80133c4 LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL ); 8018758: 2102 movs r1, #2 801875a: 4802 ldr r0, [pc, #8] @ (8018764 ) 801875c: f7ff fe9e bl 801849c return; 8018760: bf00 nop } 8018762: bd80 pop {r7, pc} 8018764: 58000c00 .word 0x58000c00 08018768 : /****************************************************************************** * MEMORY MANAGER ******************************************************************************/ void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) ) { 8018768: b580 push {r7, lr} 801876a: b086 sub sp, #24 801876c: af00 add r7, sp, #0 801876e: 6078 str r0, [r7, #4] if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) ) 8018770: 2108 movs r1, #8 8018772: 4812 ldr r0, [pc, #72] @ (80187bc ) 8018774: f7ff feaf bl 80184d6 8018778: 4603 mov r3, r0 801877a: 2b00 cmp r3, #0 801877c: d013 beq.n 80187a6 { FreeBufCb = cb; 801877e: 4a10 ldr r2, [pc, #64] @ (80187c0 ) 8018780: 687b ldr r3, [r7, #4] 8018782: 6013 str r3, [r2, #0] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8018784: f3ef 8310 mrs r3, PRIMASK 8018788: 60fb str r3, [r7, #12] return(result); 801878a: 68fb ldr r3, [r7, #12] UTILS_ENTER_CRITICAL_SECTION(); 801878c: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 801878e: b672 cpsid i } 8018790: bf00 nop LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); 8018792: 2108 movs r1, #8 8018794: 4809 ldr r0, [pc, #36] @ (80187bc ) 8018796: f7ff fe4a bl 801842e 801879a: 697b ldr r3, [r7, #20] 801879c: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 801879e: 693b ldr r3, [r7, #16] 80187a0: f383 8810 msr PRIMASK, r3 } 80187a4: e005 b.n 80187b2 UTILS_EXIT_CRITICAL_SECTION(); } else { cb(); 80187a6: 687b ldr r3, [r7, #4] 80187a8: 4798 blx r3 LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); 80187aa: 2108 movs r1, #8 80187ac: 4803 ldr r0, [pc, #12] @ (80187bc ) 80187ae: f7ff fe83 bl 80184b8 } return; 80187b2: bf00 nop } 80187b4: 3718 adds r7, #24 80187b6: 46bd mov sp, r7 80187b8: bd80 pop {r7, pc} 80187ba: bf00 nop 80187bc: 58000c00 .word 0x58000c00 80187c0: 200121b8 .word 0x200121b8 080187c4 : static void HW_IPCC_MM_FreeBufHandler( void ) { 80187c4: b580 push {r7, lr} 80187c6: b084 sub sp, #16 80187c8: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80187ca: f3ef 8310 mrs r3, PRIMASK 80187ce: 607b str r3, [r7, #4] return(result); 80187d0: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 80187d2: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 80187d4: b672 cpsid i } 80187d6: bf00 nop LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); 80187d8: 2108 movs r1, #8 80187da: 480a ldr r0, [pc, #40] @ (8018804 ) 80187dc: f7ff fe3a bl 8018454 80187e0: 68fb ldr r3, [r7, #12] 80187e2: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80187e4: 68bb ldr r3, [r7, #8] 80187e6: f383 8810 msr PRIMASK, r3 } 80187ea: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); FreeBufCb(); 80187ec: 4b06 ldr r3, [pc, #24] @ (8018808 ) 80187ee: 681b ldr r3, [r3, #0] 80187f0: 4798 blx r3 LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ); 80187f2: 2108 movs r1, #8 80187f4: 4803 ldr r0, [pc, #12] @ (8018804 ) 80187f6: f7ff fe5f bl 80184b8 return; 80187fa: bf00 nop } 80187fc: 3710 adds r7, #16 80187fe: 46bd mov sp, r7 8018800: bd80 pop {r7, pc} 8018802: bf00 nop 8018804: 58000c00 .word 0x58000c00 8018808: 200121b8 .word 0x200121b8 0801880c : /****************************************************************************** * TRACES ******************************************************************************/ void HW_IPCC_TRACES_Init( void ) { 801880c: b580 push {r7, lr} 801880e: b084 sub sp, #16 8018810: af00 add r7, sp, #0 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8018812: f3ef 8310 mrs r3, PRIMASK 8018816: 607b str r3, [r7, #4] return(result); 8018818: 687b ldr r3, [r7, #4] UTILS_ENTER_CRITICAL_SECTION(); 801881a: 60fb str r3, [r7, #12] __ASM volatile ("cpsid i" : : : "memory"); 801881c: b672 cpsid i } 801881e: bf00 nop LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL ); 8018820: 2108 movs r1, #8 8018822: 4806 ldr r0, [pc, #24] @ (801883c ) 8018824: f7ff fe28 bl 8018478 8018828: 68fb ldr r3, [r7, #12] 801882a: 60bb str r3, [r7, #8] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 801882c: 68bb ldr r3, [r7, #8] 801882e: f383 8810 msr PRIMASK, r3 } 8018832: bf00 nop UTILS_EXIT_CRITICAL_SECTION(); return; 8018834: bf00 nop } 8018836: 3710 adds r7, #16 8018838: 46bd mov sp, r7 801883a: bd80 pop {r7, pc} 801883c: 58000c00 .word 0x58000c00 08018840 : static void HW_IPCC_TRACES_EvtHandler( void ) { 8018840: b580 push {r7, lr} 8018842: af00 add r7, sp, #0 HW_IPCC_TRACES_EvtNot(); 8018844: f7fa fe66 bl 8013514 LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL ); 8018848: 2108 movs r1, #8 801884a: 4802 ldr r0, [pc, #8] @ (8018854 ) 801884c: f7ff fe26 bl 801849c return; 8018850: bf00 nop } 8018852: bd80 pop {r7, pc} 8018854: 58000c00 .word 0x58000c00 08018858 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_Device_Init(void) { 8018858: b580 push {r7, lr} 801885a: af00 add r7, sp, #0 /* USER CODE BEGIN USB_Device_Init_PreTreatment */ /* USER CODE END USB_Device_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &CDC_Desc, DEVICE_FS) != USBD_OK) { 801885c: 2200 movs r2, #0 801885e: 4912 ldr r1, [pc, #72] @ (80188a8 ) 8018860: 4812 ldr r0, [pc, #72] @ (80188ac ) 8018862: f7f9 f80b bl 801187c 8018866: 4603 mov r3, r0 8018868: 2b00 cmp r3, #0 801886a: d001 beq.n 8018870 Error_Handler(); 801886c: f7ec fd80 bl 8005370 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) { 8018870: 490f ldr r1, [pc, #60] @ (80188b0 ) 8018872: 480e ldr r0, [pc, #56] @ (80188ac ) 8018874: f7f9 f832 bl 80118dc 8018878: 4603 mov r3, r0 801887a: 2b00 cmp r3, #0 801887c: d001 beq.n 8018882 Error_Handler(); 801887e: f7ec fd77 bl 8005370 } if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) { 8018882: 490c ldr r1, [pc, #48] @ (80188b4 ) 8018884: 4809 ldr r0, [pc, #36] @ (80188ac ) 8018886: f7f8 ff29 bl 80116dc 801888a: 4603 mov r3, r0 801888c: 2b00 cmp r3, #0 801888e: d001 beq.n 8018894 Error_Handler(); 8018890: f7ec fd6e bl 8005370 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) { 8018894: 4805 ldr r0, [pc, #20] @ (80188ac ) 8018896: f7f9 f857 bl 8011948 801889a: 4603 mov r3, r0 801889c: 2b00 cmp r3, #0 801889e: d001 beq.n 80188a4 Error_Handler(); 80188a0: f7ec fd66 bl 8005370 } /* USER CODE BEGIN USB_Device_Init_PostTreatment */ /* USER CODE END USB_Device_Init_PostTreatment */ } 80188a4: bf00 nop 80188a6: bd80 pop {r7, pc} 80188a8: 200000bc .word 0x200000bc 80188ac: 200121bc .word 0x200121bc 80188b0: 20000024 .word 0x20000024 80188b4: 200000a8 .word 0x200000a8 080188b8 : /** * @brief Initializes the CDC media low layer over the FS USB IP * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Init_FS(void) { 80188b8: b580 push {r7, lr} 80188ba: af00 add r7, sp, #0 /* USER CODE BEGIN 3 */ /* Set Application Buffers */ USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); 80188bc: 2200 movs r2, #0 80188be: 4905 ldr r1, [pc, #20] @ (80188d4 ) 80188c0: 4805 ldr r0, [pc, #20] @ (80188d8 ) 80188c2: f7f8 ff25 bl 8011710 USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); 80188c6: 4905 ldr r1, [pc, #20] @ (80188dc ) 80188c8: 4803 ldr r0, [pc, #12] @ (80188d8 ) 80188ca: f7f8 ff43 bl 8011754 return (USBD_OK); 80188ce: 2300 movs r3, #0 /* USER CODE END 3 */ } 80188d0: 4618 mov r0, r3 80188d2: bd80 pop {r7, pc} 80188d4: 20012c98 .word 0x20012c98 80188d8: 200121bc .word 0x200121bc 80188dc: 20012498 .word 0x20012498 080188e0 : /** * @brief DeInitializes the CDC media low layer * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_DeInit_FS(void) { 80188e0: b480 push {r7} 80188e2: af00 add r7, sp, #0 /* USER CODE BEGIN 4 */ return (USBD_OK); 80188e4: 2300 movs r3, #0 /* USER CODE END 4 */ } 80188e6: 4618 mov r0, r3 80188e8: 46bd mov sp, r7 80188ea: f85d 7b04 ldr.w r7, [sp], #4 80188ee: 4770 bx lr 080188f0 : * @param pbuf: Buffer containing command data (request parameters) * @param length: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { 80188f0: b480 push {r7} 80188f2: b083 sub sp, #12 80188f4: af00 add r7, sp, #0 80188f6: 4603 mov r3, r0 80188f8: 6039 str r1, [r7, #0] 80188fa: 71fb strb r3, [r7, #7] 80188fc: 4613 mov r3, r2 80188fe: 80bb strh r3, [r7, #4] /* USER CODE BEGIN 5 */ switch(cmd) 8018900: 79fb ldrb r3, [r7, #7] 8018902: 2b23 cmp r3, #35 @ 0x23 8018904: d84a bhi.n 801899c 8018906: a201 add r2, pc, #4 @ (adr r2, 801890c ) 8018908: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801890c: 0801899d .word 0x0801899d 8018910: 0801899d .word 0x0801899d 8018914: 0801899d .word 0x0801899d 8018918: 0801899d .word 0x0801899d 801891c: 0801899d .word 0x0801899d 8018920: 0801899d .word 0x0801899d 8018924: 0801899d .word 0x0801899d 8018928: 0801899d .word 0x0801899d 801892c: 0801899d .word 0x0801899d 8018930: 0801899d .word 0x0801899d 8018934: 0801899d .word 0x0801899d 8018938: 0801899d .word 0x0801899d 801893c: 0801899d .word 0x0801899d 8018940: 0801899d .word 0x0801899d 8018944: 0801899d .word 0x0801899d 8018948: 0801899d .word 0x0801899d 801894c: 0801899d .word 0x0801899d 8018950: 0801899d .word 0x0801899d 8018954: 0801899d .word 0x0801899d 8018958: 0801899d .word 0x0801899d 801895c: 0801899d .word 0x0801899d 8018960: 0801899d .word 0x0801899d 8018964: 0801899d .word 0x0801899d 8018968: 0801899d .word 0x0801899d 801896c: 0801899d .word 0x0801899d 8018970: 0801899d .word 0x0801899d 8018974: 0801899d .word 0x0801899d 8018978: 0801899d .word 0x0801899d 801897c: 0801899d .word 0x0801899d 8018980: 0801899d .word 0x0801899d 8018984: 0801899d .word 0x0801899d 8018988: 0801899d .word 0x0801899d 801898c: 0801899d .word 0x0801899d 8018990: 0801899d .word 0x0801899d 8018994: 0801899d .word 0x0801899d 8018998: 0801899d .word 0x0801899d case CDC_SEND_BREAK: break; default: break; 801899c: bf00 nop } return (USBD_OK); 801899e: 2300 movs r3, #0 /* USER CODE END 5 */ } 80189a0: 4618 mov r0, r3 80189a2: 370c adds r7, #12 80189a4: 46bd mov sp, r7 80189a6: f85d 7b04 ldr.w r7, [sp], #4 80189aa: 4770 bx lr 080189ac : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { 80189ac: b580 push {r7, lr} 80189ae: b082 sub sp, #8 80189b0: af00 add r7, sp, #0 80189b2: 6078 str r0, [r7, #4] 80189b4: 6039 str r1, [r7, #0] /* USER CODE BEGIN 6 */ USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); 80189b6: 6879 ldr r1, [r7, #4] 80189b8: 4805 ldr r0, [pc, #20] @ (80189d0 ) 80189ba: f7f8 fecb bl 8011754 USBD_CDC_ReceivePacket(&hUsbDeviceFS); 80189be: 4804 ldr r0, [pc, #16] @ (80189d0 ) 80189c0: f7f8 ff26 bl 8011810 return (USBD_OK); 80189c4: 2300 movs r3, #0 /* USER CODE END 6 */ } 80189c6: 4618 mov r0, r3 80189c8: 3708 adds r7, #8 80189ca: 46bd mov sp, r7 80189cc: bd80 pop {r7, pc} 80189ce: bf00 nop 80189d0: 200121bc .word 0x200121bc 080189d4 : * @param Buf: Buffer of data to be sent * @param Len: Number of data to be sent (in bytes) * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) { 80189d4: b580 push {r7, lr} 80189d6: b084 sub sp, #16 80189d8: af00 add r7, sp, #0 80189da: 6078 str r0, [r7, #4] 80189dc: 460b mov r3, r1 80189de: 807b strh r3, [r7, #2] uint8_t result = USBD_OK; 80189e0: 2300 movs r3, #0 80189e2: 73fb strb r3, [r7, #15] /* USER CODE BEGIN 7 */ USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; 80189e4: 4b0d ldr r3, [pc, #52] @ (8018a1c ) 80189e6: f8d3 32bc ldr.w r3, [r3, #700] @ 0x2bc 80189ea: 60bb str r3, [r7, #8] if (hcdc->TxState != 0){ 80189ec: 68bb ldr r3, [r7, #8] 80189ee: f8d3 3214 ldr.w r3, [r3, #532] @ 0x214 80189f2: 2b00 cmp r3, #0 80189f4: d001 beq.n 80189fa return USBD_BUSY; 80189f6: 2301 movs r3, #1 80189f8: e00b b.n 8018a12 } USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); 80189fa: 887b ldrh r3, [r7, #2] 80189fc: 461a mov r2, r3 80189fe: 6879 ldr r1, [r7, #4] 8018a00: 4806 ldr r0, [pc, #24] @ (8018a1c ) 8018a02: f7f8 fe85 bl 8011710 result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); 8018a06: 4805 ldr r0, [pc, #20] @ (8018a1c ) 8018a08: f7f8 fec2 bl 8011790 8018a0c: 4603 mov r3, r0 8018a0e: 73fb strb r3, [r7, #15] /* USER CODE END 7 */ return result; 8018a10: 7bfb ldrb r3, [r7, #15] } 8018a12: 4618 mov r0, r3 8018a14: 3710 adds r7, #16 8018a16: 46bd mov sp, r7 8018a18: bd80 pop {r7, pc} 8018a1a: bf00 nop 8018a1c: 200121bc .word 0x200121bc 08018a20 : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum) { 8018a20: b480 push {r7} 8018a22: b087 sub sp, #28 8018a24: af00 add r7, sp, #0 8018a26: 60f8 str r0, [r7, #12] 8018a28: 60b9 str r1, [r7, #8] 8018a2a: 4613 mov r3, r2 8018a2c: 71fb strb r3, [r7, #7] uint8_t result = USBD_OK; 8018a2e: 2300 movs r3, #0 8018a30: 75fb strb r3, [r7, #23] /* USER CODE BEGIN 13 */ UNUSED(Buf); UNUSED(Len); UNUSED(epnum); /* USER CODE END 13 */ return result; 8018a32: f997 3017 ldrsb.w r3, [r7, #23] } 8018a36: 4618 mov r0, r3 8018a38: 371c adds r7, #28 8018a3a: 46bd mov sp, r7 8018a3c: f85d 7b04 ldr.w r7, [sp], #4 8018a40: 4770 bx lr ... 08018a44 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018a44: b480 push {r7} 8018a46: b083 sub sp, #12 8018a48: af00 add r7, sp, #0 8018a4a: 4603 mov r3, r0 8018a4c: 6039 str r1, [r7, #0] 8018a4e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_CDC_DeviceDesc); 8018a50: 683b ldr r3, [r7, #0] 8018a52: 2212 movs r2, #18 8018a54: 801a strh r2, [r3, #0] return USBD_CDC_DeviceDesc; 8018a56: 4b03 ldr r3, [pc, #12] @ (8018a64 ) } 8018a58: 4618 mov r0, r3 8018a5a: 370c adds r7, #12 8018a5c: 46bd mov sp, r7 8018a5e: f85d 7b04 ldr.w r7, [sp], #4 8018a62: 4770 bx lr 8018a64: 200000dc .word 0x200000dc 08018a68 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018a68: b480 push {r7} 8018a6a: b083 sub sp, #12 8018a6c: af00 add r7, sp, #0 8018a6e: 4603 mov r3, r0 8018a70: 6039 str r1, [r7, #0] 8018a72: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 8018a74: 683b ldr r3, [r7, #0] 8018a76: 2204 movs r2, #4 8018a78: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 8018a7a: 4b03 ldr r3, [pc, #12] @ (8018a88 ) } 8018a7c: 4618 mov r0, r3 8018a7e: 370c adds r7, #12 8018a80: 46bd mov sp, r7 8018a82: f85d 7b04 ldr.w r7, [sp], #4 8018a86: 4770 bx lr 8018a88: 200000f0 .word 0x200000f0 08018a8c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018a8c: b580 push {r7, lr} 8018a8e: b082 sub sp, #8 8018a90: af00 add r7, sp, #0 8018a92: 4603 mov r3, r0 8018a94: 6039 str r1, [r7, #0] 8018a96: 71fb strb r3, [r7, #7] if(speed == 0) 8018a98: 79fb ldrb r3, [r7, #7] 8018a9a: 2b00 cmp r3, #0 8018a9c: d105 bne.n 8018aaa { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length); 8018a9e: 683a ldr r2, [r7, #0] 8018aa0: 4907 ldr r1, [pc, #28] @ (8018ac0 ) 8018aa2: 4808 ldr r0, [pc, #32] @ (8018ac4 ) 8018aa4: f7fa f8ae bl 8012c04 8018aa8: e004 b.n 8018ab4 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_StrDesc, length); 8018aaa: 683a ldr r2, [r7, #0] 8018aac: 4904 ldr r1, [pc, #16] @ (8018ac0 ) 8018aae: 4805 ldr r0, [pc, #20] @ (8018ac4 ) 8018ab0: f7fa f8a8 bl 8012c04 } return USBD_StrDesc; 8018ab4: 4b02 ldr r3, [pc, #8] @ (8018ac0 ) } 8018ab6: 4618 mov r0, r3 8018ab8: 3708 adds r7, #8 8018aba: 46bd mov sp, r7 8018abc: bd80 pop {r7, pc} 8018abe: bf00 nop 8018ac0: 20013498 .word 0x20013498 8018ac4: 0801e314 .word 0x0801e314 08018ac8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018ac8: b580 push {r7, lr} 8018aca: b082 sub sp, #8 8018acc: af00 add r7, sp, #0 8018ace: 4603 mov r3, r0 8018ad0: 6039 str r1, [r7, #0] 8018ad2: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 8018ad4: 683a ldr r2, [r7, #0] 8018ad6: 4904 ldr r1, [pc, #16] @ (8018ae8 ) 8018ad8: 4804 ldr r0, [pc, #16] @ (8018aec ) 8018ada: f7fa f893 bl 8012c04 return USBD_StrDesc; 8018ade: 4b02 ldr r3, [pc, #8] @ (8018ae8 ) } 8018ae0: 4618 mov r0, r3 8018ae2: 3708 adds r7, #8 8018ae4: 46bd mov sp, r7 8018ae6: bd80 pop {r7, pc} 8018ae8: 20013498 .word 0x20013498 8018aec: 0801e32c .word 0x0801e32c 08018af0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018af0: b580 push {r7, lr} 8018af2: b082 sub sp, #8 8018af4: af00 add r7, sp, #0 8018af6: 4603 mov r3, r0 8018af8: 6039 str r1, [r7, #0] 8018afa: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 8018afc: 683b ldr r3, [r7, #0] 8018afe: 221a movs r2, #26 8018b00: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 8018b02: f000 f843 bl 8018b8c /* USER CODE BEGIN USBD_CDC_SerialStrDescriptor */ /* USER CODE END USBD_CDC_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 8018b06: 4b02 ldr r3, [pc, #8] @ (8018b10 ) } 8018b08: 4618 mov r0, r3 8018b0a: 3708 adds r7, #8 8018b0c: 46bd mov sp, r7 8018b0e: bd80 pop {r7, pc} 8018b10: 200000f4 .word 0x200000f4 08018b14 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018b14: b580 push {r7, lr} 8018b16: b082 sub sp, #8 8018b18: af00 add r7, sp, #0 8018b1a: 4603 mov r3, r0 8018b1c: 6039 str r1, [r7, #0] 8018b1e: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 8018b20: 79fb ldrb r3, [r7, #7] 8018b22: 2b00 cmp r3, #0 8018b24: d105 bne.n 8018b32 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length); 8018b26: 683a ldr r2, [r7, #0] 8018b28: 4907 ldr r1, [pc, #28] @ (8018b48 ) 8018b2a: 4808 ldr r0, [pc, #32] @ (8018b4c ) 8018b2c: f7fa f86a bl 8012c04 8018b30: e004 b.n 8018b3c } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING, USBD_StrDesc, length); 8018b32: 683a ldr r2, [r7, #0] 8018b34: 4904 ldr r1, [pc, #16] @ (8018b48 ) 8018b36: 4805 ldr r0, [pc, #20] @ (8018b4c ) 8018b38: f7fa f864 bl 8012c04 } return USBD_StrDesc; 8018b3c: 4b02 ldr r3, [pc, #8] @ (8018b48 ) } 8018b3e: 4618 mov r0, r3 8018b40: 3708 adds r7, #8 8018b42: 46bd mov sp, r7 8018b44: bd80 pop {r7, pc} 8018b46: bf00 nop 8018b48: 20013498 .word 0x20013498 8018b4c: 0801e340 .word 0x0801e340 08018b50 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_CDC_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8018b50: b580 push {r7, lr} 8018b52: b082 sub sp, #8 8018b54: af00 add r7, sp, #0 8018b56: 4603 mov r3, r0 8018b58: 6039 str r1, [r7, #0] 8018b5a: 71fb strb r3, [r7, #7] if(speed == 0) 8018b5c: 79fb ldrb r3, [r7, #7] 8018b5e: 2b00 cmp r3, #0 8018b60: d105 bne.n 8018b6e { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length); 8018b62: 683a ldr r2, [r7, #0] 8018b64: 4907 ldr r1, [pc, #28] @ (8018b84 ) 8018b66: 4808 ldr r0, [pc, #32] @ (8018b88 ) 8018b68: f7fa f84c bl 8012c04 8018b6c: e004 b.n 8018b78 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING, USBD_StrDesc, length); 8018b6e: 683a ldr r2, [r7, #0] 8018b70: 4904 ldr r1, [pc, #16] @ (8018b84 ) 8018b72: 4805 ldr r0, [pc, #20] @ (8018b88 ) 8018b74: f7fa f846 bl 8012c04 } return USBD_StrDesc; 8018b78: 4b02 ldr r3, [pc, #8] @ (8018b84 ) } 8018b7a: 4618 mov r0, r3 8018b7c: 3708 adds r7, #8 8018b7e: 46bd mov sp, r7 8018b80: bd80 pop {r7, pc} 8018b82: bf00 nop 8018b84: 20013498 .word 0x20013498 8018b88: 0801e34c .word 0x0801e34c 08018b8c : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 8018b8c: b580 push {r7, lr} 8018b8e: b084 sub sp, #16 8018b90: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 8018b92: 4b0f ldr r3, [pc, #60] @ (8018bd0 ) 8018b94: 681b ldr r3, [r3, #0] 8018b96: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 8018b98: 4b0e ldr r3, [pc, #56] @ (8018bd4 ) 8018b9a: 681b ldr r3, [r3, #0] 8018b9c: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 8018b9e: 4b0e ldr r3, [pc, #56] @ (8018bd8 ) 8018ba0: 681b ldr r3, [r3, #0] 8018ba2: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 8018ba4: 68fa ldr r2, [r7, #12] 8018ba6: 687b ldr r3, [r7, #4] 8018ba8: 4413 add r3, r2 8018baa: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 8018bac: 68fb ldr r3, [r7, #12] 8018bae: 2b00 cmp r3, #0 8018bb0: d009 beq.n 8018bc6 { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 8018bb2: 2208 movs r2, #8 8018bb4: 4909 ldr r1, [pc, #36] @ (8018bdc ) 8018bb6: 68f8 ldr r0, [r7, #12] 8018bb8: f000 f814 bl 8018be4 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 8018bbc: 2204 movs r2, #4 8018bbe: 4908 ldr r1, [pc, #32] @ (8018be0 ) 8018bc0: 68b8 ldr r0, [r7, #8] 8018bc2: f000 f80f bl 8018be4 } } 8018bc6: bf00 nop 8018bc8: 3710 adds r7, #16 8018bca: 46bd mov sp, r7 8018bcc: bd80 pop {r7, pc} 8018bce: bf00 nop 8018bd0: 1fff7590 .word 0x1fff7590 8018bd4: 1fff7594 .word 0x1fff7594 8018bd8: 1fff7598 .word 0x1fff7598 8018bdc: 200000f6 .word 0x200000f6 8018be0: 20000106 .word 0x20000106 08018be4 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 8018be4: b480 push {r7} 8018be6: b087 sub sp, #28 8018be8: af00 add r7, sp, #0 8018bea: 60f8 str r0, [r7, #12] 8018bec: 60b9 str r1, [r7, #8] 8018bee: 4613 mov r3, r2 8018bf0: 71fb strb r3, [r7, #7] uint8_t idx = 0; 8018bf2: 2300 movs r3, #0 8018bf4: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 8018bf6: 2300 movs r3, #0 8018bf8: 75fb strb r3, [r7, #23] 8018bfa: e027 b.n 8018c4c { if (((value >> 28)) < 0xA) 8018bfc: 68fb ldr r3, [r7, #12] 8018bfe: 0f1b lsrs r3, r3, #28 8018c00: 2b09 cmp r3, #9 8018c02: d80b bhi.n 8018c1c { pbuf[2 * idx] = (value >> 28) + '0'; 8018c04: 68fb ldr r3, [r7, #12] 8018c06: 0f1b lsrs r3, r3, #28 8018c08: b2da uxtb r2, r3 8018c0a: 7dfb ldrb r3, [r7, #23] 8018c0c: 005b lsls r3, r3, #1 8018c0e: 4619 mov r1, r3 8018c10: 68bb ldr r3, [r7, #8] 8018c12: 440b add r3, r1 8018c14: 3230 adds r2, #48 @ 0x30 8018c16: b2d2 uxtb r2, r2 8018c18: 701a strb r2, [r3, #0] 8018c1a: e00a b.n 8018c32 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 8018c1c: 68fb ldr r3, [r7, #12] 8018c1e: 0f1b lsrs r3, r3, #28 8018c20: b2da uxtb r2, r3 8018c22: 7dfb ldrb r3, [r7, #23] 8018c24: 005b lsls r3, r3, #1 8018c26: 4619 mov r1, r3 8018c28: 68bb ldr r3, [r7, #8] 8018c2a: 440b add r3, r1 8018c2c: 3237 adds r2, #55 @ 0x37 8018c2e: b2d2 uxtb r2, r2 8018c30: 701a strb r2, [r3, #0] } value = value << 4; 8018c32: 68fb ldr r3, [r7, #12] 8018c34: 011b lsls r3, r3, #4 8018c36: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 8018c38: 7dfb ldrb r3, [r7, #23] 8018c3a: 005b lsls r3, r3, #1 8018c3c: 3301 adds r3, #1 8018c3e: 68ba ldr r2, [r7, #8] 8018c40: 4413 add r3, r2 8018c42: 2200 movs r2, #0 8018c44: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 8018c46: 7dfb ldrb r3, [r7, #23] 8018c48: 3301 adds r3, #1 8018c4a: 75fb strb r3, [r7, #23] 8018c4c: 7dfa ldrb r2, [r7, #23] 8018c4e: 79fb ldrb r3, [r7, #7] 8018c50: 429a cmp r2, r3 8018c52: d3d3 bcc.n 8018bfc } } 8018c54: bf00 nop 8018c56: bf00 nop 8018c58: 371c adds r7, #28 8018c5a: 46bd mov sp, r7 8018c5c: f85d 7b04 ldr.w r7, [sp], #4 8018c60: 4770 bx lr 08018c62 : { 8018c62: b480 push {r7} 8018c64: b085 sub sp, #20 8018c66: af00 add r7, sp, #0 8018c68: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB2ENR, Periphs); 8018c6a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8018c6e: 6cda ldr r2, [r3, #76] @ 0x4c 8018c70: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8018c74: 687b ldr r3, [r7, #4] 8018c76: 4313 orrs r3, r2 8018c78: 64cb str r3, [r1, #76] @ 0x4c tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 8018c7a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8018c7e: 6cda ldr r2, [r3, #76] @ 0x4c 8018c80: 687b ldr r3, [r7, #4] 8018c82: 4013 ands r3, r2 8018c84: 60fb str r3, [r7, #12] (void)tmpreg; 8018c86: 68fb ldr r3, [r7, #12] } 8018c88: bf00 nop 8018c8a: 3714 adds r7, #20 8018c8c: 46bd mov sp, r7 8018c8e: f85d 7b04 ldr.w r7, [sp], #4 8018c92: 4770 bx lr 08018c94 : { 8018c94: b480 push {r7} 8018c96: b085 sub sp, #20 8018c98: af00 add r7, sp, #0 8018c9a: 6078 str r0, [r7, #4] SET_BIT(RCC->APB1ENR1, Periphs); 8018c9c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8018ca0: 6d9a ldr r2, [r3, #88] @ 0x58 8018ca2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8018ca6: 687b ldr r3, [r7, #4] 8018ca8: 4313 orrs r3, r2 8018caa: 658b str r3, [r1, #88] @ 0x58 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 8018cac: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8018cb0: 6d9a ldr r2, [r3, #88] @ 0x58 8018cb2: 687b ldr r3, [r7, #4] 8018cb4: 4013 ands r3, r2 8018cb6: 60fb str r3, [r7, #12] (void)tmpreg; 8018cb8: 68fb ldr r3, [r7, #12] } 8018cba: bf00 nop 8018cbc: 3714 adds r7, #20 8018cbe: 46bd mov sp, r7 8018cc0: f85d 7b04 ldr.w r7, [sp], #4 8018cc4: 4770 bx lr ... 08018cc8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) #else void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018cc8: b580 push {r7, lr} 8018cca: b09c sub sp, #112 @ 0x70 8018ccc: af00 add r7, sp, #0 8018cce: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8018cd0: f107 035c add.w r3, r7, #92 @ 0x5c 8018cd4: 2200 movs r2, #0 8018cd6: 601a str r2, [r3, #0] 8018cd8: 605a str r2, [r3, #4] 8018cda: 609a str r2, [r3, #8] 8018cdc: 60da str r2, [r3, #12] 8018cde: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8018ce0: f107 030c add.w r3, r7, #12 8018ce4: 2250 movs r2, #80 @ 0x50 8018ce6: 2100 movs r1, #0 8018ce8: 4618 mov r0, r3 8018cea: f001 fafb bl 801a2e4 if(pcdHandle->Instance==USB) 8018cee: 687b ldr r3, [r7, #4] 8018cf0: 681b ldr r3, [r3, #0] 8018cf2: 4a23 ldr r2, [pc, #140] @ (8018d80 ) 8018cf4: 4293 cmp r3, r2 8018cf6: d13e bne.n 8018d76 /* USER CODE END USB_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; 8018cf8: f44f 7380 mov.w r3, #256 @ 0x100 8018cfc: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLLSAI1.PLLN = 24; 8018cfe: 2318 movs r3, #24 8018d00: 613b str r3, [r7, #16] PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2; 8018d02: f44f 3300 mov.w r3, #131072 @ 0x20000 8018d06: 617b str r3, [r7, #20] PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2; 8018d08: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8018d0c: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2; 8018d0e: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8018d12: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK; 8018d14: f04f 7380 mov.w r3, #16777216 @ 0x1000000 8018d18: 623b str r3, [r7, #32] PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; 8018d1a: f04f 6380 mov.w r3, #67108864 @ 0x4000000 8018d1e: 643b str r3, [r7, #64] @ 0x40 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8018d20: f107 030c add.w r3, r7, #12 8018d24: 4618 mov r0, r3 8018d26: f7f3 fc89 bl 800c63c 8018d2a: 4603 mov r3, r0 8018d2c: 2b00 cmp r3, #0 8018d2e: d001 beq.n 8018d34 { Error_Handler(); 8018d30: f7ec fb1e bl 8005370 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8018d34: 2001 movs r0, #1 8018d36: f7ff ff94 bl 8018c62 /**USB GPIO Configuration PA11 ------> USB_DM PA12 ------> USB_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 8018d3a: f44f 53c0 mov.w r3, #6144 @ 0x1800 8018d3e: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8018d40: 2302 movs r3, #2 8018d42: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Pull = GPIO_NOPULL; 8018d44: 2300 movs r3, #0 8018d46: 667b str r3, [r7, #100] @ 0x64 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8018d48: 2303 movs r3, #3 8018d4a: 66bb str r3, [r7, #104] @ 0x68 GPIO_InitStruct.Alternate = GPIO_AF10_USB; 8018d4c: 230a movs r3, #10 8018d4e: 66fb str r3, [r7, #108] @ 0x6c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8018d50: f107 035c add.w r3, r7, #92 @ 0x5c 8018d54: 4619 mov r1, r3 8018d56: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8018d5a: f7ee fabb bl 80072d4 /* Peripheral clock enable */ __HAL_RCC_USB_CLK_ENABLE(); 8018d5e: f04f 6080 mov.w r0, #67108864 @ 0x4000000 8018d62: f7ff ff97 bl 8018c94 /* Peripheral interrupt init */ HAL_NVIC_SetPriority(USB_LP_IRQn, 5, 0); 8018d66: 2200 movs r2, #0 8018d68: 2105 movs r1, #5 8018d6a: 2014 movs r0, #20 8018d6c: f7ed ff20 bl 8006bb0 HAL_NVIC_EnableIRQ(USB_LP_IRQn); 8018d70: 2014 movs r0, #20 8018d72: f7ed ff37 bl 8006be4 /* USER CODE BEGIN USB_MspInit 1 */ /* USER CODE END USB_MspInit 1 */ } } 8018d76: bf00 nop 8018d78: 3770 adds r7, #112 @ 0x70 8018d7a: 46bd mov sp, r7 8018d7c: bd80 pop {r7, pc} 8018d7e: bf00 nop 8018d80: 40006800 .word 0x40006800 08018d84 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018d84: b580 push {r7, lr} 8018d86: b082 sub sp, #8 8018d88: af00 add r7, sp, #0 8018d8a: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PreTreatment */ /* USER CODE END HAL_PCD_SetupStageCallback_PreTreatment */ USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 8018d8c: 687b ldr r3, [r7, #4] 8018d8e: f8d3 22d8 ldr.w r2, [r3, #728] @ 0x2d8 8018d92: 687b ldr r3, [r7, #4] 8018d94: f503 7326 add.w r3, r3, #664 @ 0x298 8018d98: 4619 mov r1, r3 8018d9a: 4610 mov r0, r2 8018d9c: f7f8 fe21 bl 80119e2 /* USER CODE BEGIN HAL_PCD_SetupStageCallback_PostTreatment */ /* USER CODE END HAL_PCD_SetupStageCallback_PostTreatment */ } 8018da0: bf00 nop 8018da2: 3708 adds r7, #8 8018da4: 46bd mov sp, r7 8018da6: bd80 pop {r7, pc} 08018da8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018da8: b580 push {r7, lr} 8018daa: b082 sub sp, #8 8018dac: af00 add r7, sp, #0 8018dae: 6078 str r0, [r7, #4] 8018db0: 460b mov r3, r1 8018db2: 70fb strb r3, [r7, #3] /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PreTreatment */ /* USER CODE END HAL_PCD_DataOutStageCallback_PreTreatment */ USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 8018db4: 687b ldr r3, [r7, #4] 8018db6: f8d3 02d8 ldr.w r0, [r3, #728] @ 0x2d8 8018dba: 78fa ldrb r2, [r7, #3] 8018dbc: 6879 ldr r1, [r7, #4] 8018dbe: 4613 mov r3, r2 8018dc0: 009b lsls r3, r3, #2 8018dc2: 4413 add r3, r2 8018dc4: 00db lsls r3, r3, #3 8018dc6: 440b add r3, r1 8018dc8: f503 73b2 add.w r3, r3, #356 @ 0x164 8018dcc: 681a ldr r2, [r3, #0] 8018dce: 78fb ldrb r3, [r7, #3] 8018dd0: 4619 mov r1, r3 8018dd2: f7f8 fe5b bl 8011a8c /* USER CODE BEGIN HAL_PCD_DataOutStageCallback_PostTreatment */ /* USER CODE END HAL_PCD_DataOutStageCallback_PostTreatment */ } 8018dd6: bf00 nop 8018dd8: 3708 adds r7, #8 8018dda: 46bd mov sp, r7 8018ddc: bd80 pop {r7, pc} 08018dde : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018dde: b580 push {r7, lr} 8018de0: b082 sub sp, #8 8018de2: af00 add r7, sp, #0 8018de4: 6078 str r0, [r7, #4] 8018de6: 460b mov r3, r1 8018de8: 70fb strb r3, [r7, #3] /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PreTreatment */ /* USER CODE END HAL_PCD_DataInStageCallback_PreTreatment */ USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 8018dea: 687b ldr r3, [r7, #4] 8018dec: f8d3 02d8 ldr.w r0, [r3, #728] @ 0x2d8 8018df0: 78fa ldrb r2, [r7, #3] 8018df2: 6879 ldr r1, [r7, #4] 8018df4: 4613 mov r3, r2 8018df6: 009b lsls r3, r3, #2 8018df8: 4413 add r3, r2 8018dfa: 00db lsls r3, r3, #3 8018dfc: 440b add r3, r1 8018dfe: 3324 adds r3, #36 @ 0x24 8018e00: 681a ldr r2, [r3, #0] 8018e02: 78fb ldrb r3, [r7, #3] 8018e04: 4619 mov r1, r3 8018e06: f7f8 fefd bl 8011c04 /* USER CODE BEGIN HAL_PCD_DataInStageCallback_PostTreatment */ /* USER CODE END HAL_PCD_DataInStageCallback_PostTreatment */ } 8018e0a: bf00 nop 8018e0c: 3708 adds r7, #8 8018e0e: 46bd mov sp, r7 8018e10: bd80 pop {r7, pc} 08018e12 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018e12: b580 push {r7, lr} 8018e14: b082 sub sp, #8 8018e16: af00 add r7, sp, #0 8018e18: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_SOFCallback_PreTreatment */ /* USER CODE END HAL_PCD_SOFCallback_PreTreatment */ USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 8018e1a: 687b ldr r3, [r7, #4] 8018e1c: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8018e20: 4618 mov r0, r3 8018e22: f7f9 f841 bl 8011ea8 /* USER CODE BEGIN HAL_PCD_SOFCallback_PostTreatment */ /* USER CODE END HAL_PCD_SOFCallback_PostTreatment */ } 8018e26: bf00 nop 8018e28: 3708 adds r7, #8 8018e2a: 46bd mov sp, r7 8018e2c: bd80 pop {r7, pc} 08018e2e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018e2e: b580 push {r7, lr} 8018e30: b084 sub sp, #16 8018e32: af00 add r7, sp, #0 8018e34: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_ResetCallback_PreTreatment */ /* USER CODE END HAL_PCD_ResetCallback_PreTreatment */ USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 8018e36: 2301 movs r3, #1 8018e38: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed != PCD_SPEED_FULL) 8018e3a: 687b ldr r3, [r7, #4] 8018e3c: 795b ldrb r3, [r3, #5] 8018e3e: 2b02 cmp r3, #2 8018e40: d001 beq.n 8018e46 { Error_Handler(); 8018e42: f7ec fa95 bl 8005370 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 8018e46: 687b ldr r3, [r7, #4] 8018e48: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8018e4c: 7bfa ldrb r2, [r7, #15] 8018e4e: 4611 mov r1, r2 8018e50: 4618 mov r0, r3 8018e52: f7f8 ffe5 bl 8011e20 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 8018e56: 687b ldr r3, [r7, #4] 8018e58: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8018e5c: 4618 mov r0, r3 8018e5e: f7f8 ff8c bl 8011d7a /* USER CODE BEGIN HAL_PCD_ResetCallback_PostTreatment */ /* USER CODE END HAL_PCD_ResetCallback_PostTreatment */ } 8018e62: bf00 nop 8018e64: 3710 adds r7, #16 8018e66: 46bd mov sp, r7 8018e68: bd80 pop {r7, pc} ... 08018e6c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018e6c: b580 push {r7, lr} 8018e6e: b082 sub sp, #8 8018e70: af00 add r7, sp, #0 8018e72: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_SuspendCallback_PreTreatment */ /* USER CODE END HAL_PCD_SuspendCallback_PreTreatment */ /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 8018e74: 687b ldr r3, [r7, #4] 8018e76: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8018e7a: 4618 mov r0, r3 8018e7c: f7f8 ffe0 bl 8011e40 /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 8018e80: 687b ldr r3, [r7, #4] 8018e82: 7a5b ldrb r3, [r3, #9] 8018e84: 2b00 cmp r3, #0 8018e86: d005 beq.n 8018e94 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 8018e88: 4b04 ldr r3, [pc, #16] @ (8018e9c ) 8018e8a: 691b ldr r3, [r3, #16] 8018e8c: 4a03 ldr r2, [pc, #12] @ (8018e9c ) 8018e8e: f043 0306 orr.w r3, r3, #6 8018e92: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ /* USER CODE BEGIN HAL_PCD_SuspendCallback_PostTreatment */ /* USER CODE END HAL_PCD_SuspendCallback_PostTreatment */ } 8018e94: bf00 nop 8018e96: 3708 adds r7, #8 8018e98: 46bd mov sp, r7 8018e9a: bd80 pop {r7, pc} 8018e9c: e000ed00 .word 0xe000ed00 08018ea0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8018ea0: b580 push {r7, lr} 8018ea2: b082 sub sp, #8 8018ea4: af00 add r7, sp, #0 8018ea6: 6078 str r0, [r7, #4] /* USER CODE BEGIN HAL_PCD_ResumeCallback_PreTreatment */ /* USER CODE END HAL_PCD_ResumeCallback_PreTreatment */ /* USER CODE BEGIN 3 */ if (hpcd->Init.low_power_enable) 8018ea8: 687b ldr r3, [r7, #4] 8018eaa: 7a5b ldrb r3, [r3, #9] 8018eac: 2b00 cmp r3, #0 8018eae: d007 beq.n 8018ec0 { /* Reset SLEEPDEEP bit of Cortex System Control Register. */ SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 8018eb0: 4b08 ldr r3, [pc, #32] @ (8018ed4 ) 8018eb2: 691b ldr r3, [r3, #16] 8018eb4: 4a07 ldr r2, [pc, #28] @ (8018ed4 ) 8018eb6: f023 0306 bic.w r3, r3, #6 8018eba: 6113 str r3, [r2, #16] SystemClockConfig_Resume(); 8018ebc: f000 f9fa bl 80192b4 } /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 8018ec0: 687b ldr r3, [r7, #4] 8018ec2: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 8018ec6: 4618 mov r0, r3 8018ec8: f7f8 ffd6 bl 8011e78 /* USER CODE BEGIN HAL_PCD_ResumeCallback_PostTreatment */ /* USER CODE END HAL_PCD_ResumeCallback_PostTreatment */ } 8018ecc: bf00 nop 8018ece: 3708 adds r7, #8 8018ed0: 46bd mov sp, r7 8018ed2: bd80 pop {r7, pc} 8018ed4: e000ed00 .word 0xe000ed00 08018ed8 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 8018ed8: b580 push {r7, lr} 8018eda: b082 sub sp, #8 8018edc: af00 add r7, sp, #0 8018ede: 6078 str r0, [r7, #4] /* Init USB Ip. */ hpcd_USB_FS.pData = pdev; 8018ee0: 4a2c ldr r2, [pc, #176] @ (8018f94 ) 8018ee2: 687b ldr r3, [r7, #4] 8018ee4: f8c2 32d8 str.w r3, [r2, #728] @ 0x2d8 /* Link the driver to the stack. */ pdev->pData = &hpcd_USB_FS; 8018ee8: 687b ldr r3, [r7, #4] 8018eea: 4a2a ldr r2, [pc, #168] @ (8018f94 ) 8018eec: f8c3 22c8 str.w r2, [r3, #712] @ 0x2c8 /* Enable USB power on Pwrctrl CR2 register. */ HAL_PWREx_EnableVddUSB(); 8018ef0: f7f2 f836 bl 800af60 hpcd_USB_FS.Instance = USB; 8018ef4: 4b27 ldr r3, [pc, #156] @ (8018f94 ) 8018ef6: 4a28 ldr r2, [pc, #160] @ (8018f98 ) 8018ef8: 601a str r2, [r3, #0] hpcd_USB_FS.Init.dev_endpoints = 8; 8018efa: 4b26 ldr r3, [pc, #152] @ (8018f94 ) 8018efc: 2208 movs r2, #8 8018efe: 711a strb r2, [r3, #4] hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; 8018f00: 4b24 ldr r3, [pc, #144] @ (8018f94 ) 8018f02: 2202 movs r2, #2 8018f04: 715a strb r2, [r3, #5] hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 8018f06: 4b23 ldr r3, [pc, #140] @ (8018f94 ) 8018f08: 2202 movs r2, #2 8018f0a: 71da strb r2, [r3, #7] hpcd_USB_FS.Init.Sof_enable = DISABLE; 8018f0c: 4b21 ldr r3, [pc, #132] @ (8018f94 ) 8018f0e: 2200 movs r2, #0 8018f10: 721a strb r2, [r3, #8] hpcd_USB_FS.Init.low_power_enable = DISABLE; 8018f12: 4b20 ldr r3, [pc, #128] @ (8018f94 ) 8018f14: 2200 movs r2, #0 8018f16: 725a strb r2, [r3, #9] hpcd_USB_FS.Init.lpm_enable = DISABLE; 8018f18: 4b1e ldr r3, [pc, #120] @ (8018f94 ) 8018f1a: 2200 movs r2, #0 8018f1c: 729a strb r2, [r3, #10] hpcd_USB_FS.Init.battery_charging_enable = DISABLE; 8018f1e: 4b1d ldr r3, [pc, #116] @ (8018f94 ) 8018f20: 2200 movs r2, #0 8018f22: 72da strb r2, [r3, #11] /* register Msp Callbacks (before the Init) */ HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPINIT_CB_ID, PCD_MspInit); HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_MSPDEINIT_CB_ID, PCD_MspDeInit); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) 8018f24: 481b ldr r0, [pc, #108] @ (8018f94 ) 8018f26: f7f0 fabb bl 80094a0 8018f2a: 4603 mov r3, r0 8018f2c: 2b00 cmp r3, #0 8018f2e: d001 beq.n 8018f34 { Error_Handler( ); 8018f30: f7ec fa1e bl 8005370 /* USER CODE BEGIN RegisterCallBackSecondPart */ /* USER CODE END RegisterCallBackSecondPart */ #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* USER CODE BEGIN EndPoint_Configuration */ HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); 8018f34: 687b ldr r3, [r7, #4] 8018f36: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 8018f3a: 2318 movs r3, #24 8018f3c: 2200 movs r2, #0 8018f3e: 2100 movs r1, #0 8018f40: f7f1 ff83 bl 800ae4a HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); 8018f44: 687b ldr r3, [r7, #4] 8018f46: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 8018f4a: 2358 movs r3, #88 @ 0x58 8018f4c: 2200 movs r2, #0 8018f4e: 2180 movs r1, #128 @ 0x80 8018f50: f7f1 ff7b bl 800ae4a /* USER CODE END EndPoint_Configuration */ /* USER CODE BEGIN EndPoint_Configuration_CDC */ HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); 8018f54: 687b ldr r3, [r7, #4] 8018f56: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 8018f5a: 23c0 movs r3, #192 @ 0xc0 8018f5c: 2200 movs r2, #0 8018f5e: 2181 movs r1, #129 @ 0x81 8018f60: f7f1 ff73 bl 800ae4a HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); 8018f64: 687b ldr r3, [r7, #4] 8018f66: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 8018f6a: f44f 7388 mov.w r3, #272 @ 0x110 8018f6e: 2200 movs r2, #0 8018f70: 2101 movs r1, #1 8018f72: f7f1 ff6a bl 800ae4a HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); 8018f76: 687b ldr r3, [r7, #4] 8018f78: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 8018f7c: f44f 7380 mov.w r3, #256 @ 0x100 8018f80: 2200 movs r2, #0 8018f82: 2182 movs r1, #130 @ 0x82 8018f84: f7f1 ff61 bl 800ae4a /* USER CODE END EndPoint_Configuration_CDC */ return USBD_OK; 8018f88: 2300 movs r3, #0 } 8018f8a: 4618 mov r0, r3 8018f8c: 3708 adds r7, #8 8018f8e: 46bd mov sp, r7 8018f90: bd80 pop {r7, pc} 8018f92: bf00 nop 8018f94: 20013698 .word 0x20013698 8018f98: 40006800 .word 0x40006800 08018f9c : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 8018f9c: b580 push {r7, lr} 8018f9e: b084 sub sp, #16 8018fa0: af00 add r7, sp, #0 8018fa2: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 8018fa4: 2300 movs r3, #0 8018fa6: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8018fa8: 2300 movs r3, #0 8018faa: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 8018fac: 687b ldr r3, [r7, #4] 8018fae: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 8018fb2: 4618 mov r0, r3 8018fb4: f7f0 fb42 bl 800963c 8018fb8: 4603 mov r3, r0 8018fba: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8018fbc: 7bfb ldrb r3, [r7, #15] 8018fbe: 4618 mov r0, r3 8018fc0: f000 f97e bl 80192c0 8018fc4: 4603 mov r3, r0 8018fc6: 73bb strb r3, [r7, #14] return usb_status; 8018fc8: 7bbb ldrb r3, [r7, #14] } 8018fca: 4618 mov r0, r3 8018fcc: 3710 adds r7, #16 8018fce: 46bd mov sp, r7 8018fd0: bd80 pop {r7, pc} 08018fd2 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 8018fd2: b580 push {r7, lr} 8018fd4: b084 sub sp, #16 8018fd6: af00 add r7, sp, #0 8018fd8: 6078 str r0, [r7, #4] 8018fda: 4608 mov r0, r1 8018fdc: 4611 mov r1, r2 8018fde: 461a mov r2, r3 8018fe0: 4603 mov r3, r0 8018fe2: 70fb strb r3, [r7, #3] 8018fe4: 460b mov r3, r1 8018fe6: 70bb strb r3, [r7, #2] 8018fe8: 4613 mov r3, r2 8018fea: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 8018fec: 2300 movs r3, #0 8018fee: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8018ff0: 2300 movs r3, #0 8018ff2: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 8018ff4: 687b ldr r3, [r7, #4] 8018ff6: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 8018ffa: 78bb ldrb r3, [r7, #2] 8018ffc: 883a ldrh r2, [r7, #0] 8018ffe: 78f9 ldrb r1, [r7, #3] 8019000: f7f0 fc89 bl 8009916 8019004: 4603 mov r3, r0 8019006: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8019008: 7bfb ldrb r3, [r7, #15] 801900a: 4618 mov r0, r3 801900c: f000 f958 bl 80192c0 8019010: 4603 mov r3, r0 8019012: 73bb strb r3, [r7, #14] return usb_status; 8019014: 7bbb ldrb r3, [r7, #14] } 8019016: 4618 mov r0, r3 8019018: 3710 adds r7, #16 801901a: 46bd mov sp, r7 801901c: bd80 pop {r7, pc} 0801901e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 801901e: b580 push {r7, lr} 8019020: b084 sub sp, #16 8019022: af00 add r7, sp, #0 8019024: 6078 str r0, [r7, #4] 8019026: 460b mov r3, r1 8019028: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 801902a: 2300 movs r3, #0 801902c: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 801902e: 2300 movs r3, #0 8019030: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 8019032: 687b ldr r3, [r7, #4] 8019034: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 8019038: 78fa ldrb r2, [r7, #3] 801903a: 4611 mov r1, r2 801903c: 4618 mov r0, r3 801903e: f7f0 fcc9 bl 80099d4 8019042: 4603 mov r3, r0 8019044: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8019046: 7bfb ldrb r3, [r7, #15] 8019048: 4618 mov r0, r3 801904a: f000 f939 bl 80192c0 801904e: 4603 mov r3, r0 8019050: 73bb strb r3, [r7, #14] return usb_status; 8019052: 7bbb ldrb r3, [r7, #14] } 8019054: 4618 mov r0, r3 8019056: 3710 adds r7, #16 8019058: 46bd mov sp, r7 801905a: bd80 pop {r7, pc} 0801905c : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 801905c: b580 push {r7, lr} 801905e: b084 sub sp, #16 8019060: af00 add r7, sp, #0 8019062: 6078 str r0, [r7, #4] 8019064: 460b mov r3, r1 8019066: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 8019068: 2300 movs r3, #0 801906a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 801906c: 2300 movs r3, #0 801906e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 8019070: 687b ldr r3, [r7, #4] 8019072: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 8019076: 78fa ldrb r2, [r7, #3] 8019078: 4611 mov r1, r2 801907a: 4618 mov r0, r3 801907c: f7f0 fd72 bl 8009b64 8019080: 4603 mov r3, r0 8019082: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8019084: 7bfb ldrb r3, [r7, #15] 8019086: 4618 mov r0, r3 8019088: f000 f91a bl 80192c0 801908c: 4603 mov r3, r0 801908e: 73bb strb r3, [r7, #14] return usb_status; 8019090: 7bbb ldrb r3, [r7, #14] } 8019092: 4618 mov r0, r3 8019094: 3710 adds r7, #16 8019096: 46bd mov sp, r7 8019098: bd80 pop {r7, pc} 0801909a : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 801909a: b580 push {r7, lr} 801909c: b084 sub sp, #16 801909e: af00 add r7, sp, #0 80190a0: 6078 str r0, [r7, #4] 80190a2: 460b mov r3, r1 80190a4: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 80190a6: 2300 movs r3, #0 80190a8: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 80190aa: 2300 movs r3, #0 80190ac: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 80190ae: 687b ldr r3, [r7, #4] 80190b0: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 80190b4: 78fa ldrb r2, [r7, #3] 80190b6: 4611 mov r1, r2 80190b8: 4618 mov r0, r3 80190ba: f7f0 fda5 bl 8009c08 80190be: 4603 mov r3, r0 80190c0: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 80190c2: 7bfb ldrb r3, [r7, #15] 80190c4: 4618 mov r0, r3 80190c6: f000 f8fb bl 80192c0 80190ca: 4603 mov r3, r0 80190cc: 73bb strb r3, [r7, #14] return usb_status; 80190ce: 7bbb ldrb r3, [r7, #14] } 80190d0: 4618 mov r0, r3 80190d2: 3710 adds r7, #16 80190d4: 46bd mov sp, r7 80190d6: bd80 pop {r7, pc} 080190d8 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 80190d8: b480 push {r7} 80190da: b085 sub sp, #20 80190dc: af00 add r7, sp, #0 80190de: 6078 str r0, [r7, #4] 80190e0: 460b mov r3, r1 80190e2: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 80190e4: 687b ldr r3, [r7, #4] 80190e6: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 80190ea: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 80190ec: f997 3003 ldrsb.w r3, [r7, #3] 80190f0: 2b00 cmp r3, #0 80190f2: da0b bge.n 801910c { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 80190f4: 78fb ldrb r3, [r7, #3] 80190f6: f003 027f and.w r2, r3, #127 @ 0x7f 80190fa: 68f9 ldr r1, [r7, #12] 80190fc: 4613 mov r3, r2 80190fe: 009b lsls r3, r3, #2 8019100: 4413 add r3, r2 8019102: 00db lsls r3, r3, #3 8019104: 440b add r3, r1 8019106: 3312 adds r3, #18 8019108: 781b ldrb r3, [r3, #0] 801910a: e00b b.n 8019124 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 801910c: 78fb ldrb r3, [r7, #3] 801910e: f003 027f and.w r2, r3, #127 @ 0x7f 8019112: 68f9 ldr r1, [r7, #12] 8019114: 4613 mov r3, r2 8019116: 009b lsls r3, r3, #2 8019118: 4413 add r3, r2 801911a: 00db lsls r3, r3, #3 801911c: 440b add r3, r1 801911e: f503 73a9 add.w r3, r3, #338 @ 0x152 8019122: 781b ldrb r3, [r3, #0] } } 8019124: 4618 mov r0, r3 8019126: 3714 adds r7, #20 8019128: 46bd mov sp, r7 801912a: f85d 7b04 ldr.w r7, [sp], #4 801912e: 4770 bx lr 08019130 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 8019130: b580 push {r7, lr} 8019132: b084 sub sp, #16 8019134: af00 add r7, sp, #0 8019136: 6078 str r0, [r7, #4] 8019138: 460b mov r3, r1 801913a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 801913c: 2300 movs r3, #0 801913e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8019140: 2300 movs r3, #0 8019142: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 8019144: 687b ldr r3, [r7, #4] 8019146: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 801914a: 78fa ldrb r2, [r7, #3] 801914c: 4611 mov r1, r2 801914e: 4618 mov r0, r3 8019150: f7f0 fbbd bl 80098ce 8019154: 4603 mov r3, r0 8019156: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8019158: 7bfb ldrb r3, [r7, #15] 801915a: 4618 mov r0, r3 801915c: f000 f8b0 bl 80192c0 8019160: 4603 mov r3, r0 8019162: 73bb strb r3, [r7, #14] return usb_status; 8019164: 7bbb ldrb r3, [r7, #14] } 8019166: 4618 mov r0, r3 8019168: 3710 adds r7, #16 801916a: 46bd mov sp, r7 801916c: bd80 pop {r7, pc} 0801916e : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 801916e: b580 push {r7, lr} 8019170: b086 sub sp, #24 8019172: af00 add r7, sp, #0 8019174: 60f8 str r0, [r7, #12] 8019176: 607a str r2, [r7, #4] 8019178: 603b str r3, [r7, #0] 801917a: 460b mov r3, r1 801917c: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 801917e: 2300 movs r3, #0 8019180: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 8019182: 2300 movs r3, #0 8019184: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 8019186: 68fb ldr r3, [r7, #12] 8019188: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 801918c: 7af9 ldrb r1, [r7, #11] 801918e: 683b ldr r3, [r7, #0] 8019190: 687a ldr r2, [r7, #4] 8019192: f7f0 fcb0 bl 8009af6 8019196: 4603 mov r3, r0 8019198: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 801919a: 7dfb ldrb r3, [r7, #23] 801919c: 4618 mov r0, r3 801919e: f000 f88f bl 80192c0 80191a2: 4603 mov r3, r0 80191a4: 75bb strb r3, [r7, #22] return usb_status; 80191a6: 7dbb ldrb r3, [r7, #22] } 80191a8: 4618 mov r0, r3 80191aa: 3718 adds r7, #24 80191ac: 46bd mov sp, r7 80191ae: bd80 pop {r7, pc} 080191b0 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 80191b0: b580 push {r7, lr} 80191b2: b086 sub sp, #24 80191b4: af00 add r7, sp, #0 80191b6: 60f8 str r0, [r7, #12] 80191b8: 607a str r2, [r7, #4] 80191ba: 603b str r3, [r7, #0] 80191bc: 460b mov r3, r1 80191be: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 80191c0: 2300 movs r3, #0 80191c2: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 80191c4: 2300 movs r3, #0 80191c6: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 80191c8: 68fb ldr r3, [r7, #12] 80191ca: f8d3 02c8 ldr.w r0, [r3, #712] @ 0x2c8 80191ce: 7af9 ldrb r1, [r7, #11] 80191d0: 683b ldr r3, [r7, #0] 80191d2: 687a ldr r2, [r7, #4] 80191d4: f7f0 fc46 bl 8009a64 80191d8: 4603 mov r3, r0 80191da: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 80191dc: 7dfb ldrb r3, [r7, #23] 80191de: 4618 mov r0, r3 80191e0: f000 f86e bl 80192c0 80191e4: 4603 mov r3, r0 80191e6: 75bb strb r3, [r7, #22] return usb_status; 80191e8: 7dbb ldrb r3, [r7, #22] } 80191ea: 4618 mov r0, r3 80191ec: 3718 adds r7, #24 80191ee: 46bd mov sp, r7 80191f0: bd80 pop {r7, pc} 080191f2 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Received Data Size */ uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 80191f2: b580 push {r7, lr} 80191f4: b082 sub sp, #8 80191f6: af00 add r7, sp, #0 80191f8: 6078 str r0, [r7, #4] 80191fa: 460b mov r3, r1 80191fc: 70fb strb r3, [r7, #3] return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); 80191fe: 687b ldr r3, [r7, #4] 8019200: f8d3 32c8 ldr.w r3, [r3, #712] @ 0x2c8 8019204: 78fa ldrb r2, [r7, #3] 8019206: 4611 mov r1, r2 8019208: 4618 mov r0, r3 801920a: f7f0 fc5c bl 8009ac6 801920e: 4603 mov r3, r0 } 8019210: 4618 mov r0, r3 8019212: 3708 adds r7, #8 8019214: 46bd mov sp, r7 8019216: bd80 pop {r7, pc} 08019218 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) #else void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8019218: b580 push {r7, lr} 801921a: b082 sub sp, #8 801921c: af00 add r7, sp, #0 801921e: 6078 str r0, [r7, #4] 8019220: 460b mov r3, r1 8019222: 70fb strb r3, [r7, #3] /* USER CODE BEGIN LPM_Callback */ switch (msg) 8019224: 78fb ldrb r3, [r7, #3] 8019226: 2b00 cmp r3, #0 8019228: d002 beq.n 8019230 801922a: 2b01 cmp r3, #1 801922c: d013 beq.n 8019256 SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } /* USER CODE END LPM_Callback */ } 801922e: e023 b.n 8019278 if (hpcd->Init.low_power_enable) 8019230: 687b ldr r3, [r7, #4] 8019232: 7a5b ldrb r3, [r3, #9] 8019234: 2b00 cmp r3, #0 8019236: d007 beq.n 8019248 SystemClockConfig_Resume(); 8019238: f000 f83c bl 80192b4 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 801923c: 4b10 ldr r3, [pc, #64] @ (8019280 ) 801923e: 691b ldr r3, [r3, #16] 8019240: 4a0f ldr r2, [pc, #60] @ (8019280 ) 8019242: f023 0306 bic.w r3, r3, #6 8019246: 6113 str r3, [r2, #16] USBD_LL_Resume(hpcd->pData); 8019248: 687b ldr r3, [r7, #4] 801924a: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 801924e: 4618 mov r0, r3 8019250: f7f8 fe12 bl 8011e78 break; 8019254: e010 b.n 8019278 USBD_LL_Suspend(hpcd->pData); 8019256: 687b ldr r3, [r7, #4] 8019258: f8d3 32d8 ldr.w r3, [r3, #728] @ 0x2d8 801925c: 4618 mov r0, r3 801925e: f7f8 fdef bl 8011e40 if (hpcd->Init.low_power_enable) 8019262: 687b ldr r3, [r7, #4] 8019264: 7a5b ldrb r3, [r3, #9] 8019266: 2b00 cmp r3, #0 8019268: d005 beq.n 8019276 SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 801926a: 4b05 ldr r3, [pc, #20] @ (8019280 ) 801926c: 691b ldr r3, [r3, #16] 801926e: 4a04 ldr r2, [pc, #16] @ (8019280 ) 8019270: f043 0306 orr.w r3, r3, #6 8019274: 6113 str r3, [r2, #16] break; 8019276: bf00 nop } 8019278: bf00 nop 801927a: 3708 adds r7, #8 801927c: 46bd mov sp, r7 801927e: bd80 pop {r7, pc} 8019280: e000ed00 .word 0xe000ed00 08019284 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 8019284: b480 push {r7} 8019286: b083 sub sp, #12 8019288: af00 add r7, sp, #0 801928a: 6078 str r0, [r7, #4] UNUSED(size); static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 801928c: 4b03 ldr r3, [pc, #12] @ (801929c ) } 801928e: 4618 mov r0, r3 8019290: 370c adds r7, #12 8019292: 46bd mov sp, r7 8019294: f85d 7b04 ldr.w r7, [sp], #4 8019298: 4770 bx lr 801929a: bf00 nop 801929c: 20013974 .word 0x20013974 080192a0 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 80192a0: b480 push {r7} 80192a2: b083 sub sp, #12 80192a4: af00 add r7, sp, #0 80192a6: 6078 str r0, [r7, #4] UNUSED(p); } 80192a8: bf00 nop 80192aa: 370c adds r7, #12 80192ac: 46bd mov sp, r7 80192ae: f85d 7b04 ldr.w r7, [sp], #4 80192b2: 4770 bx lr 080192b4 : * @brief Configures system clock after wake-up from USB resume callBack: * enable HSI, PLL and select PLL as system clock source. * @retval None */ static void SystemClockConfig_Resume(void) { 80192b4: b580 push {r7, lr} 80192b6: af00 add r7, sp, #0 SystemClock_Config(); 80192b8: f7eb fb4a bl 8004950 } 80192bc: bf00 nop 80192be: bd80 pop {r7, pc} 080192c0 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 80192c0: b480 push {r7} 80192c2: b085 sub sp, #20 80192c4: af00 add r7, sp, #0 80192c6: 4603 mov r3, r0 80192c8: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 80192ca: 2300 movs r3, #0 80192cc: 73fb strb r3, [r7, #15] switch (hal_status) 80192ce: 79fb ldrb r3, [r7, #7] 80192d0: 2b03 cmp r3, #3 80192d2: d817 bhi.n 8019304 80192d4: a201 add r2, pc, #4 @ (adr r2, 80192dc ) 80192d6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80192da: bf00 nop 80192dc: 080192ed .word 0x080192ed 80192e0: 080192f3 .word 0x080192f3 80192e4: 080192f9 .word 0x080192f9 80192e8: 080192ff .word 0x080192ff { case HAL_OK : usb_status = USBD_OK; 80192ec: 2300 movs r3, #0 80192ee: 73fb strb r3, [r7, #15] break; 80192f0: e00b b.n 801930a case HAL_ERROR : usb_status = USBD_FAIL; 80192f2: 2303 movs r3, #3 80192f4: 73fb strb r3, [r7, #15] break; 80192f6: e008 b.n 801930a case HAL_BUSY : usb_status = USBD_BUSY; 80192f8: 2301 movs r3, #1 80192fa: 73fb strb r3, [r7, #15] break; 80192fc: e005 b.n 801930a case HAL_TIMEOUT : usb_status = USBD_FAIL; 80192fe: 2303 movs r3, #3 8019300: 73fb strb r3, [r7, #15] break; 8019302: e002 b.n 801930a default : usb_status = USBD_FAIL; 8019304: 2303 movs r3, #3 8019306: 73fb strb r3, [r7, #15] break; 8019308: bf00 nop } return usb_status; 801930a: 7bfb ldrb r3, [r7, #15] } 801930c: 4618 mov r0, r3 801930e: 3714 adds r7, #20 8019310: 46bd mov sp, r7 8019312: f85d 7b04 ldr.w r7, [sp], #4 8019316: 4770 bx lr 08019318 : /** @addtogroup TINY_LPM_Exported_function * @{ */ void UTIL_LPM_Init( void ) { 8019318: b480 push {r7} 801931a: af00 add r7, sp, #0 StopModeDisable = UTIL_LPM_NO_BIT_SET; 801931c: 4b05 ldr r3, [pc, #20] @ (8019334 ) 801931e: 2200 movs r2, #0 8019320: 601a str r2, [r3, #0] OffModeDisable = UTIL_LPM_NO_BIT_SET; 8019322: 4b05 ldr r3, [pc, #20] @ (8019338 ) 8019324: 2200 movs r2, #0 8019326: 601a str r2, [r3, #0] UTIL_LPM_INIT_CRITICAL_SECTION( ); } 8019328: bf00 nop 801932a: 46bd mov sp, r7 801932c: f85d 7b04 ldr.w r7, [sp], #4 8019330: 4770 bx lr 8019332: bf00 nop 8019334: 20013b94 .word 0x20013b94 8019338: 20013b98 .word 0x20013b98 0801933c : UTIL_LPM_EXIT_CRITICAL_SECTION( ); } void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) { 801933c: b480 push {r7} 801933e: b087 sub sp, #28 8019340: af00 add r7, sp, #0 8019342: 6078 str r0, [r7, #4] 8019344: 460b mov r3, r1 8019346: 70fb strb r3, [r7, #3] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8019348: f3ef 8310 mrs r3, PRIMASK 801934c: 613b str r3, [r7, #16] return(result); 801934e: 693b ldr r3, [r7, #16] UTIL_LPM_ENTER_CRITICAL_SECTION( ); 8019350: 617b str r3, [r7, #20] __ASM volatile ("cpsid i" : : : "memory"); 8019352: b672 cpsid i } 8019354: bf00 nop switch(state) 8019356: 78fb ldrb r3, [r7, #3] 8019358: 2b00 cmp r3, #0 801935a: d008 beq.n 801936e 801935c: 2b01 cmp r3, #1 801935e: d10e bne.n 801937e { case UTIL_LPM_DISABLE: { OffModeDisable |= lpm_id_bm; 8019360: 4b0d ldr r3, [pc, #52] @ (8019398 ) 8019362: 681a ldr r2, [r3, #0] 8019364: 687b ldr r3, [r7, #4] 8019366: 4313 orrs r3, r2 8019368: 4a0b ldr r2, [pc, #44] @ (8019398 ) 801936a: 6013 str r3, [r2, #0] break; 801936c: e008 b.n 8019380 } case UTIL_LPM_ENABLE: { OffModeDisable &= ( ~lpm_id_bm ); 801936e: 687b ldr r3, [r7, #4] 8019370: 43da mvns r2, r3 8019372: 4b09 ldr r3, [pc, #36] @ (8019398 ) 8019374: 681b ldr r3, [r3, #0] 8019376: 4013 ands r3, r2 8019378: 4a07 ldr r2, [pc, #28] @ (8019398 ) 801937a: 6013 str r3, [r2, #0] break; 801937c: e000 b.n 8019380 } default : { break; 801937e: bf00 nop 8019380: 697b ldr r3, [r7, #20] 8019382: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8019384: 68fb ldr r3, [r7, #12] 8019386: f383 8810 msr PRIMASK, r3 } 801938a: bf00 nop } } UTIL_LPM_EXIT_CRITICAL_SECTION( ); } 801938c: bf00 nop 801938e: 371c adds r7, #28 8019390: 46bd mov sp, r7 8019392: f85d 7b04 ldr.w r7, [sp], #4 8019396: 4770 bx lr 8019398: 20013b98 .word 0x20013b98 0801939c <__cvt>: 801939c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 80193a0: ec57 6b10 vmov r6, r7, d0 80193a4: 2f00 cmp r7, #0 80193a6: 460c mov r4, r1 80193a8: 4619 mov r1, r3 80193aa: 463b mov r3, r7 80193ac: bfbb ittet lt 80193ae: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000 80193b2: 461f movlt r7, r3 80193b4: 2300 movge r3, #0 80193b6: 232d movlt r3, #45 @ 0x2d 80193b8: 700b strb r3, [r1, #0] 80193ba: 9b0d ldr r3, [sp, #52] @ 0x34 80193bc: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 80193c0: 4691 mov r9, r2 80193c2: f023 0820 bic.w r8, r3, #32 80193c6: bfbc itt lt 80193c8: 4632 movlt r2, r6 80193ca: 4616 movlt r6, r2 80193cc: f1b8 0f46 cmp.w r8, #70 @ 0x46 80193d0: d005 beq.n 80193de <__cvt+0x42> 80193d2: f1b8 0f45 cmp.w r8, #69 @ 0x45 80193d6: d100 bne.n 80193da <__cvt+0x3e> 80193d8: 3401 adds r4, #1 80193da: 2102 movs r1, #2 80193dc: e000 b.n 80193e0 <__cvt+0x44> 80193de: 2103 movs r1, #3 80193e0: ab03 add r3, sp, #12 80193e2: 9301 str r3, [sp, #4] 80193e4: ab02 add r3, sp, #8 80193e6: 9300 str r3, [sp, #0] 80193e8: ec47 6b10 vmov d0, r6, r7 80193ec: 4653 mov r3, sl 80193ee: 4622 mov r2, r4 80193f0: f001 f8f2 bl 801a5d8 <_dtoa_r> 80193f4: f1b8 0f47 cmp.w r8, #71 @ 0x47 80193f8: 4605 mov r5, r0 80193fa: d119 bne.n 8019430 <__cvt+0x94> 80193fc: f019 0f01 tst.w r9, #1 8019400: d00e beq.n 8019420 <__cvt+0x84> 8019402: eb00 0904 add.w r9, r0, r4 8019406: 2200 movs r2, #0 8019408: 2300 movs r3, #0 801940a: 4630 mov r0, r6 801940c: 4639 mov r1, r7 801940e: f7e7 fb33 bl 8000a78 <__aeabi_dcmpeq> 8019412: b108 cbz r0, 8019418 <__cvt+0x7c> 8019414: f8cd 900c str.w r9, [sp, #12] 8019418: 2230 movs r2, #48 @ 0x30 801941a: 9b03 ldr r3, [sp, #12] 801941c: 454b cmp r3, r9 801941e: d31e bcc.n 801945e <__cvt+0xc2> 8019420: 9b03 ldr r3, [sp, #12] 8019422: 9a0e ldr r2, [sp, #56] @ 0x38 8019424: 1b5b subs r3, r3, r5 8019426: 4628 mov r0, r5 8019428: 6013 str r3, [r2, #0] 801942a: b004 add sp, #16 801942c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8019430: f1b8 0f46 cmp.w r8, #70 @ 0x46 8019434: eb00 0904 add.w r9, r0, r4 8019438: d1e5 bne.n 8019406 <__cvt+0x6a> 801943a: 7803 ldrb r3, [r0, #0] 801943c: 2b30 cmp r3, #48 @ 0x30 801943e: d10a bne.n 8019456 <__cvt+0xba> 8019440: 2200 movs r2, #0 8019442: 2300 movs r3, #0 8019444: 4630 mov r0, r6 8019446: 4639 mov r1, r7 8019448: f7e7 fb16 bl 8000a78 <__aeabi_dcmpeq> 801944c: b918 cbnz r0, 8019456 <__cvt+0xba> 801944e: f1c4 0401 rsb r4, r4, #1 8019452: f8ca 4000 str.w r4, [sl] 8019456: f8da 3000 ldr.w r3, [sl] 801945a: 4499 add r9, r3 801945c: e7d3 b.n 8019406 <__cvt+0x6a> 801945e: 1c59 adds r1, r3, #1 8019460: 9103 str r1, [sp, #12] 8019462: 701a strb r2, [r3, #0] 8019464: e7d9 b.n 801941a <__cvt+0x7e> 08019466 <__exponent>: 8019466: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8019468: 2900 cmp r1, #0 801946a: bfba itte lt 801946c: 4249 neglt r1, r1 801946e: 232d movlt r3, #45 @ 0x2d 8019470: 232b movge r3, #43 @ 0x2b 8019472: 2909 cmp r1, #9 8019474: 7002 strb r2, [r0, #0] 8019476: 7043 strb r3, [r0, #1] 8019478: dd29 ble.n 80194ce <__exponent+0x68> 801947a: f10d 0407 add.w r4, sp, #7 801947e: 4625 mov r5, r4 8019480: 270a movs r7, #10 8019482: 4622 mov r2, r4 8019484: fbb1 f6f7 udiv r6, r1, r7 8019488: fb07 1316 mls r3, r7, r6, r1 801948c: 3330 adds r3, #48 @ 0x30 801948e: f802 3c01 strb.w r3, [r2, #-1] 8019492: 460b mov r3, r1 8019494: 2b63 cmp r3, #99 @ 0x63 8019496: f104 34ff add.w r4, r4, #4294967295 @ 0xffffffff 801949a: 4631 mov r1, r6 801949c: dcf1 bgt.n 8019482 <__exponent+0x1c> 801949e: 3130 adds r1, #48 @ 0x30 80194a0: 1e93 subs r3, r2, #2 80194a2: f804 1c01 strb.w r1, [r4, #-1] 80194a6: 1c41 adds r1, r0, #1 80194a8: 461c mov r4, r3 80194aa: 42ab cmp r3, r5 80194ac: d30a bcc.n 80194c4 <__exponent+0x5e> 80194ae: f10d 0309 add.w r3, sp, #9 80194b2: 1a9b subs r3, r3, r2 80194b4: 42a5 cmp r5, r4 80194b6: bf38 it cc 80194b8: 2300 movcc r3, #0 80194ba: 1c82 adds r2, r0, #2 80194bc: 4413 add r3, r2 80194be: 1a18 subs r0, r3, r0 80194c0: b003 add sp, #12 80194c2: bdf0 pop {r4, r5, r6, r7, pc} 80194c4: f813 6b01 ldrb.w r6, [r3], #1 80194c8: f801 6f01 strb.w r6, [r1, #1]! 80194cc: e7ed b.n 80194aa <__exponent+0x44> 80194ce: 2330 movs r3, #48 @ 0x30 80194d0: 3130 adds r1, #48 @ 0x30 80194d2: 7083 strb r3, [r0, #2] 80194d4: 70c1 strb r1, [r0, #3] 80194d6: 1d03 adds r3, r0, #4 80194d8: e7f1 b.n 80194be <__exponent+0x58> ... 080194dc <_printf_float>: 80194dc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80194e0: b08d sub sp, #52 @ 0x34 80194e2: 460c mov r4, r1 80194e4: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58 80194e8: 4616 mov r6, r2 80194ea: 461f mov r7, r3 80194ec: 4605 mov r5, r0 80194ee: f000 ff01 bl 801a2f4 <_localeconv_r> 80194f2: 6803 ldr r3, [r0, #0] 80194f4: 9306 str r3, [sp, #24] 80194f6: 4618 mov r0, r3 80194f8: f7e6 fe92 bl 8000220 80194fc: 2300 movs r3, #0 80194fe: 930a str r3, [sp, #40] @ 0x28 8019500: f8d8 3000 ldr.w r3, [r8] 8019504: f894 a018 ldrb.w sl, [r4, #24] 8019508: f8d4 b000 ldr.w fp, [r4] 801950c: 9007 str r0, [sp, #28] 801950e: 3307 adds r3, #7 8019510: f023 0307 bic.w r3, r3, #7 8019514: ecb3 7b02 vldmia r3!, {d7} 8019518: ed8d 7b04 vstr d7, [sp, #16] 801951c: f8c8 3000 str.w r3, [r8] 8019520: e9dd 8304 ldrd r8, r3, [sp, #16] 8019524: f023 4900 bic.w r9, r3, #2147483648 @ 0x80000000 8019528: ed84 7b12 vstr d7, [r4, #72] @ 0x48 801952c: 4b9c ldr r3, [pc, #624] @ (80197a0 <_printf_float+0x2c4>) 801952e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8019532: 4640 mov r0, r8 8019534: 4649 mov r1, r9 8019536: f7e7 fad1 bl 8000adc <__aeabi_dcmpun> 801953a: bb70 cbnz r0, 801959a <_printf_float+0xbe> 801953c: 4b98 ldr r3, [pc, #608] @ (80197a0 <_printf_float+0x2c4>) 801953e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8019542: 4640 mov r0, r8 8019544: 4649 mov r1, r9 8019546: f7e7 faab bl 8000aa0 <__aeabi_dcmple> 801954a: bb30 cbnz r0, 801959a <_printf_float+0xbe> 801954c: e9dd 0104 ldrd r0, r1, [sp, #16] 8019550: 2200 movs r2, #0 8019552: 2300 movs r3, #0 8019554: f7e7 fa9a bl 8000a8c <__aeabi_dcmplt> 8019558: b110 cbz r0, 8019560 <_printf_float+0x84> 801955a: 232d movs r3, #45 @ 0x2d 801955c: f884 3043 strb.w r3, [r4, #67] @ 0x43 8019560: 4a90 ldr r2, [pc, #576] @ (80197a4 <_printf_float+0x2c8>) 8019562: 4b91 ldr r3, [pc, #580] @ (80197a8 <_printf_float+0x2cc>) 8019564: f1ba 0f47 cmp.w sl, #71 @ 0x47 8019568: bf8c ite hi 801956a: 4690 movhi r8, r2 801956c: 4698 movls r8, r3 801956e: 2303 movs r3, #3 8019570: 6123 str r3, [r4, #16] 8019572: f02b 0304 bic.w r3, fp, #4 8019576: 6023 str r3, [r4, #0] 8019578: f04f 0900 mov.w r9, #0 801957c: 9700 str r7, [sp, #0] 801957e: 4633 mov r3, r6 8019580: aa0b add r2, sp, #44 @ 0x2c 8019582: 4621 mov r1, r4 8019584: 4628 mov r0, r5 8019586: f000 f9d1 bl 801992c <_printf_common> 801958a: 3001 adds r0, #1 801958c: f040 808c bne.w 80196a8 <_printf_float+0x1cc> 8019590: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8019594: b00d add sp, #52 @ 0x34 8019596: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801959a: e9dd 2304 ldrd r2, r3, [sp, #16] 801959e: 4610 mov r0, r2 80195a0: 4619 mov r1, r3 80195a2: f7e7 fa9b bl 8000adc <__aeabi_dcmpun> 80195a6: b140 cbz r0, 80195ba <_printf_float+0xde> 80195a8: 9b05 ldr r3, [sp, #20] 80195aa: 4a80 ldr r2, [pc, #512] @ (80197ac <_printf_float+0x2d0>) 80195ac: 2b00 cmp r3, #0 80195ae: bfbc itt lt 80195b0: 232d movlt r3, #45 @ 0x2d 80195b2: f884 3043 strblt.w r3, [r4, #67] @ 0x43 80195b6: 4b7e ldr r3, [pc, #504] @ (80197b0 <_printf_float+0x2d4>) 80195b8: e7d4 b.n 8019564 <_printf_float+0x88> 80195ba: 6863 ldr r3, [r4, #4] 80195bc: 1c5a adds r2, r3, #1 80195be: f00a 09df and.w r9, sl, #223 @ 0xdf 80195c2: d13b bne.n 801963c <_printf_float+0x160> 80195c4: 2306 movs r3, #6 80195c6: 6063 str r3, [r4, #4] 80195c8: f44b 6280 orr.w r2, fp, #1024 @ 0x400 80195cc: 2300 movs r3, #0 80195ce: 6022 str r2, [r4, #0] 80195d0: 9303 str r3, [sp, #12] 80195d2: ab0a add r3, sp, #40 @ 0x28 80195d4: e9cd a301 strd sl, r3, [sp, #4] 80195d8: ab09 add r3, sp, #36 @ 0x24 80195da: 9300 str r3, [sp, #0] 80195dc: 6861 ldr r1, [r4, #4] 80195de: ed9d 0b04 vldr d0, [sp, #16] 80195e2: f10d 0323 add.w r3, sp, #35 @ 0x23 80195e6: 4628 mov r0, r5 80195e8: f7ff fed8 bl 801939c <__cvt> 80195ec: f1b9 0f47 cmp.w r9, #71 @ 0x47 80195f0: 9909 ldr r1, [sp, #36] @ 0x24 80195f2: 4680 mov r8, r0 80195f4: d129 bne.n 801964a <_printf_float+0x16e> 80195f6: 1cc8 adds r0, r1, #3 80195f8: db02 blt.n 8019600 <_printf_float+0x124> 80195fa: 6863 ldr r3, [r4, #4] 80195fc: 428b cmp r3, r1 80195fe: da41 bge.n 8019684 <_printf_float+0x1a8> 8019600: f1aa 0a02 sub.w sl, sl, #2 8019604: fa5f fa8a uxtb.w sl, sl 8019608: 3901 subs r1, #1 801960a: 4652 mov r2, sl 801960c: f104 0050 add.w r0, r4, #80 @ 0x50 8019610: 9109 str r1, [sp, #36] @ 0x24 8019612: f7ff ff28 bl 8019466 <__exponent> 8019616: 9a0a ldr r2, [sp, #40] @ 0x28 8019618: 1813 adds r3, r2, r0 801961a: 2a01 cmp r2, #1 801961c: 4681 mov r9, r0 801961e: 6123 str r3, [r4, #16] 8019620: dc02 bgt.n 8019628 <_printf_float+0x14c> 8019622: 6822 ldr r2, [r4, #0] 8019624: 07d2 lsls r2, r2, #31 8019626: d501 bpl.n 801962c <_printf_float+0x150> 8019628: 3301 adds r3, #1 801962a: 6123 str r3, [r4, #16] 801962c: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23 8019630: 2b00 cmp r3, #0 8019632: d0a3 beq.n 801957c <_printf_float+0xa0> 8019634: 232d movs r3, #45 @ 0x2d 8019636: f884 3043 strb.w r3, [r4, #67] @ 0x43 801963a: e79f b.n 801957c <_printf_float+0xa0> 801963c: f1b9 0f47 cmp.w r9, #71 @ 0x47 8019640: d1c2 bne.n 80195c8 <_printf_float+0xec> 8019642: 2b00 cmp r3, #0 8019644: d1c0 bne.n 80195c8 <_printf_float+0xec> 8019646: 2301 movs r3, #1 8019648: e7bd b.n 80195c6 <_printf_float+0xea> 801964a: f1ba 0f65 cmp.w sl, #101 @ 0x65 801964e: d9db bls.n 8019608 <_printf_float+0x12c> 8019650: f1ba 0f66 cmp.w sl, #102 @ 0x66 8019654: d118 bne.n 8019688 <_printf_float+0x1ac> 8019656: 2900 cmp r1, #0 8019658: 6863 ldr r3, [r4, #4] 801965a: dd0b ble.n 8019674 <_printf_float+0x198> 801965c: 6121 str r1, [r4, #16] 801965e: b913 cbnz r3, 8019666 <_printf_float+0x18a> 8019660: 6822 ldr r2, [r4, #0] 8019662: 07d0 lsls r0, r2, #31 8019664: d502 bpl.n 801966c <_printf_float+0x190> 8019666: 3301 adds r3, #1 8019668: 440b add r3, r1 801966a: 6123 str r3, [r4, #16] 801966c: 65a1 str r1, [r4, #88] @ 0x58 801966e: f04f 0900 mov.w r9, #0 8019672: e7db b.n 801962c <_printf_float+0x150> 8019674: b913 cbnz r3, 801967c <_printf_float+0x1a0> 8019676: 6822 ldr r2, [r4, #0] 8019678: 07d2 lsls r2, r2, #31 801967a: d501 bpl.n 8019680 <_printf_float+0x1a4> 801967c: 3302 adds r3, #2 801967e: e7f4 b.n 801966a <_printf_float+0x18e> 8019680: 2301 movs r3, #1 8019682: e7f2 b.n 801966a <_printf_float+0x18e> 8019684: f04f 0a67 mov.w sl, #103 @ 0x67 8019688: 9b0a ldr r3, [sp, #40] @ 0x28 801968a: 428b cmp r3, r1 801968c: dc05 bgt.n 801969a <_printf_float+0x1be> 801968e: 6823 ldr r3, [r4, #0] 8019690: 6121 str r1, [r4, #16] 8019692: 07d8 lsls r0, r3, #31 8019694: d5ea bpl.n 801966c <_printf_float+0x190> 8019696: 1c4b adds r3, r1, #1 8019698: e7e7 b.n 801966a <_printf_float+0x18e> 801969a: 2900 cmp r1, #0 801969c: bfd4 ite le 801969e: f1c1 0202 rsble r2, r1, #2 80196a2: 2201 movgt r2, #1 80196a4: 4413 add r3, r2 80196a6: e7e0 b.n 801966a <_printf_float+0x18e> 80196a8: 6823 ldr r3, [r4, #0] 80196aa: 055a lsls r2, r3, #21 80196ac: d407 bmi.n 80196be <_printf_float+0x1e2> 80196ae: 6923 ldr r3, [r4, #16] 80196b0: 4642 mov r2, r8 80196b2: 4631 mov r1, r6 80196b4: 4628 mov r0, r5 80196b6: 47b8 blx r7 80196b8: 3001 adds r0, #1 80196ba: d12b bne.n 8019714 <_printf_float+0x238> 80196bc: e768 b.n 8019590 <_printf_float+0xb4> 80196be: f1ba 0f65 cmp.w sl, #101 @ 0x65 80196c2: f240 80dd bls.w 8019880 <_printf_float+0x3a4> 80196c6: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 80196ca: 2200 movs r2, #0 80196cc: 2300 movs r3, #0 80196ce: f7e7 f9d3 bl 8000a78 <__aeabi_dcmpeq> 80196d2: 2800 cmp r0, #0 80196d4: d033 beq.n 801973e <_printf_float+0x262> 80196d6: 4a37 ldr r2, [pc, #220] @ (80197b4 <_printf_float+0x2d8>) 80196d8: 2301 movs r3, #1 80196da: 4631 mov r1, r6 80196dc: 4628 mov r0, r5 80196de: 47b8 blx r7 80196e0: 3001 adds r0, #1 80196e2: f43f af55 beq.w 8019590 <_printf_float+0xb4> 80196e6: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24 80196ea: 4543 cmp r3, r8 80196ec: db02 blt.n 80196f4 <_printf_float+0x218> 80196ee: 6823 ldr r3, [r4, #0] 80196f0: 07d8 lsls r0, r3, #31 80196f2: d50f bpl.n 8019714 <_printf_float+0x238> 80196f4: e9dd 2306 ldrd r2, r3, [sp, #24] 80196f8: 4631 mov r1, r6 80196fa: 4628 mov r0, r5 80196fc: 47b8 blx r7 80196fe: 3001 adds r0, #1 8019700: f43f af46 beq.w 8019590 <_printf_float+0xb4> 8019704: f04f 0900 mov.w r9, #0 8019708: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 801970c: f104 0a1a add.w sl, r4, #26 8019710: 45c8 cmp r8, r9 8019712: dc09 bgt.n 8019728 <_printf_float+0x24c> 8019714: 6823 ldr r3, [r4, #0] 8019716: 079b lsls r3, r3, #30 8019718: f100 8103 bmi.w 8019922 <_printf_float+0x446> 801971c: 68e0 ldr r0, [r4, #12] 801971e: 9b0b ldr r3, [sp, #44] @ 0x2c 8019720: 4298 cmp r0, r3 8019722: bfb8 it lt 8019724: 4618 movlt r0, r3 8019726: e735 b.n 8019594 <_printf_float+0xb8> 8019728: 2301 movs r3, #1 801972a: 4652 mov r2, sl 801972c: 4631 mov r1, r6 801972e: 4628 mov r0, r5 8019730: 47b8 blx r7 8019732: 3001 adds r0, #1 8019734: f43f af2c beq.w 8019590 <_printf_float+0xb4> 8019738: f109 0901 add.w r9, r9, #1 801973c: e7e8 b.n 8019710 <_printf_float+0x234> 801973e: 9b09 ldr r3, [sp, #36] @ 0x24 8019740: 2b00 cmp r3, #0 8019742: dc39 bgt.n 80197b8 <_printf_float+0x2dc> 8019744: 4a1b ldr r2, [pc, #108] @ (80197b4 <_printf_float+0x2d8>) 8019746: 2301 movs r3, #1 8019748: 4631 mov r1, r6 801974a: 4628 mov r0, r5 801974c: 47b8 blx r7 801974e: 3001 adds r0, #1 8019750: f43f af1e beq.w 8019590 <_printf_float+0xb4> 8019754: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24 8019758: ea59 0303 orrs.w r3, r9, r3 801975c: d102 bne.n 8019764 <_printf_float+0x288> 801975e: 6823 ldr r3, [r4, #0] 8019760: 07d9 lsls r1, r3, #31 8019762: d5d7 bpl.n 8019714 <_printf_float+0x238> 8019764: e9dd 2306 ldrd r2, r3, [sp, #24] 8019768: 4631 mov r1, r6 801976a: 4628 mov r0, r5 801976c: 47b8 blx r7 801976e: 3001 adds r0, #1 8019770: f43f af0e beq.w 8019590 <_printf_float+0xb4> 8019774: f04f 0a00 mov.w sl, #0 8019778: f104 0b1a add.w fp, r4, #26 801977c: 9b09 ldr r3, [sp, #36] @ 0x24 801977e: 425b negs r3, r3 8019780: 4553 cmp r3, sl 8019782: dc01 bgt.n 8019788 <_printf_float+0x2ac> 8019784: 464b mov r3, r9 8019786: e793 b.n 80196b0 <_printf_float+0x1d4> 8019788: 2301 movs r3, #1 801978a: 465a mov r2, fp 801978c: 4631 mov r1, r6 801978e: 4628 mov r0, r5 8019790: 47b8 blx r7 8019792: 3001 adds r0, #1 8019794: f43f aefc beq.w 8019590 <_printf_float+0xb4> 8019798: f10a 0a01 add.w sl, sl, #1 801979c: e7ee b.n 801977c <_printf_float+0x2a0> 801979e: bf00 nop 80197a0: 7fefffff .word 0x7fefffff 80197a4: 0801e5f4 .word 0x0801e5f4 80197a8: 0801e5f0 .word 0x0801e5f0 80197ac: 0801e5fc .word 0x0801e5fc 80197b0: 0801e5f8 .word 0x0801e5f8 80197b4: 0801e600 .word 0x0801e600 80197b8: 6da3 ldr r3, [r4, #88] @ 0x58 80197ba: f8dd a028 ldr.w sl, [sp, #40] @ 0x28 80197be: 4553 cmp r3, sl 80197c0: bfa8 it ge 80197c2: 4653 movge r3, sl 80197c4: 2b00 cmp r3, #0 80197c6: 4699 mov r9, r3 80197c8: dc36 bgt.n 8019838 <_printf_float+0x35c> 80197ca: f04f 0b00 mov.w fp, #0 80197ce: ea29 79e9 bic.w r9, r9, r9, asr #31 80197d2: f104 021a add.w r2, r4, #26 80197d6: 6da3 ldr r3, [r4, #88] @ 0x58 80197d8: 9304 str r3, [sp, #16] 80197da: eba3 0309 sub.w r3, r3, r9 80197de: 455b cmp r3, fp 80197e0: dc31 bgt.n 8019846 <_printf_float+0x36a> 80197e2: 9b09 ldr r3, [sp, #36] @ 0x24 80197e4: 459a cmp sl, r3 80197e6: dc3a bgt.n 801985e <_printf_float+0x382> 80197e8: 6823 ldr r3, [r4, #0] 80197ea: 07da lsls r2, r3, #31 80197ec: d437 bmi.n 801985e <_printf_float+0x382> 80197ee: 9b09 ldr r3, [sp, #36] @ 0x24 80197f0: ebaa 0903 sub.w r9, sl, r3 80197f4: 9b04 ldr r3, [sp, #16] 80197f6: ebaa 0303 sub.w r3, sl, r3 80197fa: 4599 cmp r9, r3 80197fc: bfa8 it ge 80197fe: 4699 movge r9, r3 8019800: f1b9 0f00 cmp.w r9, #0 8019804: dc33 bgt.n 801986e <_printf_float+0x392> 8019806: f04f 0800 mov.w r8, #0 801980a: ea29 79e9 bic.w r9, r9, r9, asr #31 801980e: f104 0b1a add.w fp, r4, #26 8019812: 9b09 ldr r3, [sp, #36] @ 0x24 8019814: ebaa 0303 sub.w r3, sl, r3 8019818: eba3 0309 sub.w r3, r3, r9 801981c: 4543 cmp r3, r8 801981e: f77f af79 ble.w 8019714 <_printf_float+0x238> 8019822: 2301 movs r3, #1 8019824: 465a mov r2, fp 8019826: 4631 mov r1, r6 8019828: 4628 mov r0, r5 801982a: 47b8 blx r7 801982c: 3001 adds r0, #1 801982e: f43f aeaf beq.w 8019590 <_printf_float+0xb4> 8019832: f108 0801 add.w r8, r8, #1 8019836: e7ec b.n 8019812 <_printf_float+0x336> 8019838: 4642 mov r2, r8 801983a: 4631 mov r1, r6 801983c: 4628 mov r0, r5 801983e: 47b8 blx r7 8019840: 3001 adds r0, #1 8019842: d1c2 bne.n 80197ca <_printf_float+0x2ee> 8019844: e6a4 b.n 8019590 <_printf_float+0xb4> 8019846: 2301 movs r3, #1 8019848: 4631 mov r1, r6 801984a: 4628 mov r0, r5 801984c: 9204 str r2, [sp, #16] 801984e: 47b8 blx r7 8019850: 3001 adds r0, #1 8019852: f43f ae9d beq.w 8019590 <_printf_float+0xb4> 8019856: 9a04 ldr r2, [sp, #16] 8019858: f10b 0b01 add.w fp, fp, #1 801985c: e7bb b.n 80197d6 <_printf_float+0x2fa> 801985e: e9dd 2306 ldrd r2, r3, [sp, #24] 8019862: 4631 mov r1, r6 8019864: 4628 mov r0, r5 8019866: 47b8 blx r7 8019868: 3001 adds r0, #1 801986a: d1c0 bne.n 80197ee <_printf_float+0x312> 801986c: e690 b.n 8019590 <_printf_float+0xb4> 801986e: 9a04 ldr r2, [sp, #16] 8019870: 464b mov r3, r9 8019872: 4442 add r2, r8 8019874: 4631 mov r1, r6 8019876: 4628 mov r0, r5 8019878: 47b8 blx r7 801987a: 3001 adds r0, #1 801987c: d1c3 bne.n 8019806 <_printf_float+0x32a> 801987e: e687 b.n 8019590 <_printf_float+0xb4> 8019880: f8dd a028 ldr.w sl, [sp, #40] @ 0x28 8019884: f1ba 0f01 cmp.w sl, #1 8019888: dc01 bgt.n 801988e <_printf_float+0x3b2> 801988a: 07db lsls r3, r3, #31 801988c: d536 bpl.n 80198fc <_printf_float+0x420> 801988e: 2301 movs r3, #1 8019890: 4642 mov r2, r8 8019892: 4631 mov r1, r6 8019894: 4628 mov r0, r5 8019896: 47b8 blx r7 8019898: 3001 adds r0, #1 801989a: f43f ae79 beq.w 8019590 <_printf_float+0xb4> 801989e: e9dd 2306 ldrd r2, r3, [sp, #24] 80198a2: 4631 mov r1, r6 80198a4: 4628 mov r0, r5 80198a6: 47b8 blx r7 80198a8: 3001 adds r0, #1 80198aa: f43f ae71 beq.w 8019590 <_printf_float+0xb4> 80198ae: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48 80198b2: 2200 movs r2, #0 80198b4: 2300 movs r3, #0 80198b6: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 80198ba: f7e7 f8dd bl 8000a78 <__aeabi_dcmpeq> 80198be: b9c0 cbnz r0, 80198f2 <_printf_float+0x416> 80198c0: 4653 mov r3, sl 80198c2: f108 0201 add.w r2, r8, #1 80198c6: 4631 mov r1, r6 80198c8: 4628 mov r0, r5 80198ca: 47b8 blx r7 80198cc: 3001 adds r0, #1 80198ce: d10c bne.n 80198ea <_printf_float+0x40e> 80198d0: e65e b.n 8019590 <_printf_float+0xb4> 80198d2: 2301 movs r3, #1 80198d4: 465a mov r2, fp 80198d6: 4631 mov r1, r6 80198d8: 4628 mov r0, r5 80198da: 47b8 blx r7 80198dc: 3001 adds r0, #1 80198de: f43f ae57 beq.w 8019590 <_printf_float+0xb4> 80198e2: f108 0801 add.w r8, r8, #1 80198e6: 45d0 cmp r8, sl 80198e8: dbf3 blt.n 80198d2 <_printf_float+0x3f6> 80198ea: 464b mov r3, r9 80198ec: f104 0250 add.w r2, r4, #80 @ 0x50 80198f0: e6df b.n 80196b2 <_printf_float+0x1d6> 80198f2: f04f 0800 mov.w r8, #0 80198f6: f104 0b1a add.w fp, r4, #26 80198fa: e7f4 b.n 80198e6 <_printf_float+0x40a> 80198fc: 2301 movs r3, #1 80198fe: 4642 mov r2, r8 8019900: e7e1 b.n 80198c6 <_printf_float+0x3ea> 8019902: 2301 movs r3, #1 8019904: 464a mov r2, r9 8019906: 4631 mov r1, r6 8019908: 4628 mov r0, r5 801990a: 47b8 blx r7 801990c: 3001 adds r0, #1 801990e: f43f ae3f beq.w 8019590 <_printf_float+0xb4> 8019912: f108 0801 add.w r8, r8, #1 8019916: 68e3 ldr r3, [r4, #12] 8019918: 990b ldr r1, [sp, #44] @ 0x2c 801991a: 1a5b subs r3, r3, r1 801991c: 4543 cmp r3, r8 801991e: dcf0 bgt.n 8019902 <_printf_float+0x426> 8019920: e6fc b.n 801971c <_printf_float+0x240> 8019922: f04f 0800 mov.w r8, #0 8019926: f104 0919 add.w r9, r4, #25 801992a: e7f4 b.n 8019916 <_printf_float+0x43a> 0801992c <_printf_common>: 801992c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8019930: 4616 mov r6, r2 8019932: 4698 mov r8, r3 8019934: 688a ldr r2, [r1, #8] 8019936: 690b ldr r3, [r1, #16] 8019938: f8dd 9020 ldr.w r9, [sp, #32] 801993c: 4293 cmp r3, r2 801993e: bfb8 it lt 8019940: 4613 movlt r3, r2 8019942: 6033 str r3, [r6, #0] 8019944: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 8019948: 4607 mov r7, r0 801994a: 460c mov r4, r1 801994c: b10a cbz r2, 8019952 <_printf_common+0x26> 801994e: 3301 adds r3, #1 8019950: 6033 str r3, [r6, #0] 8019952: 6823 ldr r3, [r4, #0] 8019954: 0699 lsls r1, r3, #26 8019956: bf42 ittt mi 8019958: 6833 ldrmi r3, [r6, #0] 801995a: 3302 addmi r3, #2 801995c: 6033 strmi r3, [r6, #0] 801995e: 6825 ldr r5, [r4, #0] 8019960: f015 0506 ands.w r5, r5, #6 8019964: d106 bne.n 8019974 <_printf_common+0x48> 8019966: f104 0a19 add.w sl, r4, #25 801996a: 68e3 ldr r3, [r4, #12] 801996c: 6832 ldr r2, [r6, #0] 801996e: 1a9b subs r3, r3, r2 8019970: 42ab cmp r3, r5 8019972: dc26 bgt.n 80199c2 <_printf_common+0x96> 8019974: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 8019978: 6822 ldr r2, [r4, #0] 801997a: 3b00 subs r3, #0 801997c: bf18 it ne 801997e: 2301 movne r3, #1 8019980: 0692 lsls r2, r2, #26 8019982: d42b bmi.n 80199dc <_printf_common+0xb0> 8019984: f104 0243 add.w r2, r4, #67 @ 0x43 8019988: 4641 mov r1, r8 801998a: 4638 mov r0, r7 801998c: 47c8 blx r9 801998e: 3001 adds r0, #1 8019990: d01e beq.n 80199d0 <_printf_common+0xa4> 8019992: 6823 ldr r3, [r4, #0] 8019994: 6922 ldr r2, [r4, #16] 8019996: f003 0306 and.w r3, r3, #6 801999a: 2b04 cmp r3, #4 801999c: bf02 ittt eq 801999e: 68e5 ldreq r5, [r4, #12] 80199a0: 6833 ldreq r3, [r6, #0] 80199a2: 1aed subeq r5, r5, r3 80199a4: 68a3 ldr r3, [r4, #8] 80199a6: bf0c ite eq 80199a8: ea25 75e5 biceq.w r5, r5, r5, asr #31 80199ac: 2500 movne r5, #0 80199ae: 4293 cmp r3, r2 80199b0: bfc4 itt gt 80199b2: 1a9b subgt r3, r3, r2 80199b4: 18ed addgt r5, r5, r3 80199b6: 2600 movs r6, #0 80199b8: 341a adds r4, #26 80199ba: 42b5 cmp r5, r6 80199bc: d11a bne.n 80199f4 <_printf_common+0xc8> 80199be: 2000 movs r0, #0 80199c0: e008 b.n 80199d4 <_printf_common+0xa8> 80199c2: 2301 movs r3, #1 80199c4: 4652 mov r2, sl 80199c6: 4641 mov r1, r8 80199c8: 4638 mov r0, r7 80199ca: 47c8 blx r9 80199cc: 3001 adds r0, #1 80199ce: d103 bne.n 80199d8 <_printf_common+0xac> 80199d0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80199d4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80199d8: 3501 adds r5, #1 80199da: e7c6 b.n 801996a <_printf_common+0x3e> 80199dc: 18e1 adds r1, r4, r3 80199de: 1c5a adds r2, r3, #1 80199e0: 2030 movs r0, #48 @ 0x30 80199e2: f881 0043 strb.w r0, [r1, #67] @ 0x43 80199e6: 4422 add r2, r4 80199e8: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 80199ec: f882 1043 strb.w r1, [r2, #67] @ 0x43 80199f0: 3302 adds r3, #2 80199f2: e7c7 b.n 8019984 <_printf_common+0x58> 80199f4: 2301 movs r3, #1 80199f6: 4622 mov r2, r4 80199f8: 4641 mov r1, r8 80199fa: 4638 mov r0, r7 80199fc: 47c8 blx r9 80199fe: 3001 adds r0, #1 8019a00: d0e6 beq.n 80199d0 <_printf_common+0xa4> 8019a02: 3601 adds r6, #1 8019a04: e7d9 b.n 80199ba <_printf_common+0x8e> ... 08019a08 <_printf_i>: 8019a08: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8019a0c: 7e0d ldrb r5, [r1, #24] 8019a0e: b085 sub sp, #20 8019a10: 2d78 cmp r5, #120 @ 0x78 8019a12: 4690 mov r8, r2 8019a14: 9e0c ldr r6, [sp, #48] @ 0x30 8019a16: 4607 mov r7, r0 8019a18: 460c mov r4, r1 8019a1a: 4699 mov r9, r3 8019a1c: f101 0243 add.w r2, r1, #67 @ 0x43 8019a20: d807 bhi.n 8019a32 <_printf_i+0x2a> 8019a22: 2d62 cmp r5, #98 @ 0x62 8019a24: d80a bhi.n 8019a3c <_printf_i+0x34> 8019a26: 2d00 cmp r5, #0 8019a28: f000 80d7 beq.w 8019bda <_printf_i+0x1d2> 8019a2c: 2d58 cmp r5, #88 @ 0x58 8019a2e: f000 80bc beq.w 8019baa <_printf_i+0x1a2> 8019a32: f104 0642 add.w r6, r4, #66 @ 0x42 8019a36: f884 5042 strb.w r5, [r4, #66] @ 0x42 8019a3a: e03b b.n 8019ab4 <_printf_i+0xac> 8019a3c: f1a5 0363 sub.w r3, r5, #99 @ 0x63 8019a40: 2b15 cmp r3, #21 8019a42: d8f6 bhi.n 8019a32 <_printf_i+0x2a> 8019a44: a101 add r1, pc, #4 @ (adr r1, 8019a4c <_printf_i+0x44>) 8019a46: f851 f023 ldr.w pc, [r1, r3, lsl #2] 8019a4a: bf00 nop 8019a4c: 08019aa5 .word 0x08019aa5 8019a50: 08019ab9 .word 0x08019ab9 8019a54: 08019a33 .word 0x08019a33 8019a58: 08019a33 .word 0x08019a33 8019a5c: 08019a33 .word 0x08019a33 8019a60: 08019a33 .word 0x08019a33 8019a64: 08019ab9 .word 0x08019ab9 8019a68: 08019a33 .word 0x08019a33 8019a6c: 08019a33 .word 0x08019a33 8019a70: 08019a33 .word 0x08019a33 8019a74: 08019a33 .word 0x08019a33 8019a78: 08019bc1 .word 0x08019bc1 8019a7c: 08019ae3 .word 0x08019ae3 8019a80: 08019b73 .word 0x08019b73 8019a84: 08019a33 .word 0x08019a33 8019a88: 08019a33 .word 0x08019a33 8019a8c: 08019be3 .word 0x08019be3 8019a90: 08019a33 .word 0x08019a33 8019a94: 08019ae3 .word 0x08019ae3 8019a98: 08019a33 .word 0x08019a33 8019a9c: 08019a33 .word 0x08019a33 8019aa0: 08019b7b .word 0x08019b7b 8019aa4: 6833 ldr r3, [r6, #0] 8019aa6: 1d1a adds r2, r3, #4 8019aa8: 681b ldr r3, [r3, #0] 8019aaa: 6032 str r2, [r6, #0] 8019aac: f104 0642 add.w r6, r4, #66 @ 0x42 8019ab0: f884 3042 strb.w r3, [r4, #66] @ 0x42 8019ab4: 2301 movs r3, #1 8019ab6: e0a1 b.n 8019bfc <_printf_i+0x1f4> 8019ab8: 6833 ldr r3, [r6, #0] 8019aba: 6820 ldr r0, [r4, #0] 8019abc: 1d19 adds r1, r3, #4 8019abe: 6031 str r1, [r6, #0] 8019ac0: 0606 lsls r6, r0, #24 8019ac2: d501 bpl.n 8019ac8 <_printf_i+0xc0> 8019ac4: 681d ldr r5, [r3, #0] 8019ac6: e003 b.n 8019ad0 <_printf_i+0xc8> 8019ac8: 0645 lsls r5, r0, #25 8019aca: d5fb bpl.n 8019ac4 <_printf_i+0xbc> 8019acc: f9b3 5000 ldrsh.w r5, [r3] 8019ad0: 2d00 cmp r5, #0 8019ad2: da03 bge.n 8019adc <_printf_i+0xd4> 8019ad4: 232d movs r3, #45 @ 0x2d 8019ad6: 426d negs r5, r5 8019ad8: f884 3043 strb.w r3, [r4, #67] @ 0x43 8019adc: 485b ldr r0, [pc, #364] @ (8019c4c <_printf_i+0x244>) 8019ade: 230a movs r3, #10 8019ae0: e011 b.n 8019b06 <_printf_i+0xfe> 8019ae2: 6821 ldr r1, [r4, #0] 8019ae4: 6833 ldr r3, [r6, #0] 8019ae6: 0608 lsls r0, r1, #24 8019ae8: f853 5b04 ldr.w r5, [r3], #4 8019aec: d402 bmi.n 8019af4 <_printf_i+0xec> 8019aee: 0649 lsls r1, r1, #25 8019af0: bf48 it mi 8019af2: b2ad uxthmi r5, r5 8019af4: 6033 str r3, [r6, #0] 8019af6: 7e23 ldrb r3, [r4, #24] 8019af8: 4854 ldr r0, [pc, #336] @ (8019c4c <_printf_i+0x244>) 8019afa: 2b6f cmp r3, #111 @ 0x6f 8019afc: d15c bne.n 8019bb8 <_printf_i+0x1b0> 8019afe: 2308 movs r3, #8 8019b00: 2100 movs r1, #0 8019b02: f884 1043 strb.w r1, [r4, #67] @ 0x43 8019b06: 6866 ldr r6, [r4, #4] 8019b08: 60a6 str r6, [r4, #8] 8019b0a: 2e00 cmp r6, #0 8019b0c: db05 blt.n 8019b1a <_printf_i+0x112> 8019b0e: 6821 ldr r1, [r4, #0] 8019b10: 432e orrs r6, r5 8019b12: f021 0104 bic.w r1, r1, #4 8019b16: 6021 str r1, [r4, #0] 8019b18: d050 beq.n 8019bbc <_printf_i+0x1b4> 8019b1a: 4616 mov r6, r2 8019b1c: fbb5 f1f3 udiv r1, r5, r3 8019b20: fb03 5c11 mls ip, r3, r1, r5 8019b24: f810 c00c ldrb.w ip, [r0, ip] 8019b28: f806 cd01 strb.w ip, [r6, #-1]! 8019b2c: 46ac mov ip, r5 8019b2e: 4563 cmp r3, ip 8019b30: 460d mov r5, r1 8019b32: d9f3 bls.n 8019b1c <_printf_i+0x114> 8019b34: 2b08 cmp r3, #8 8019b36: d10b bne.n 8019b50 <_printf_i+0x148> 8019b38: 6823 ldr r3, [r4, #0] 8019b3a: 07db lsls r3, r3, #31 8019b3c: d508 bpl.n 8019b50 <_printf_i+0x148> 8019b3e: 6923 ldr r3, [r4, #16] 8019b40: 6861 ldr r1, [r4, #4] 8019b42: 4299 cmp r1, r3 8019b44: bfde ittt le 8019b46: 2330 movle r3, #48 @ 0x30 8019b48: f806 3c01 strble.w r3, [r6, #-1] 8019b4c: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 8019b50: 1b92 subs r2, r2, r6 8019b52: 6122 str r2, [r4, #16] 8019b54: f8cd 9000 str.w r9, [sp] 8019b58: 4643 mov r3, r8 8019b5a: aa03 add r2, sp, #12 8019b5c: 4621 mov r1, r4 8019b5e: 4638 mov r0, r7 8019b60: f7ff fee4 bl 801992c <_printf_common> 8019b64: 3001 adds r0, #1 8019b66: d14e bne.n 8019c06 <_printf_i+0x1fe> 8019b68: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8019b6c: b005 add sp, #20 8019b6e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8019b72: 6823 ldr r3, [r4, #0] 8019b74: f043 0320 orr.w r3, r3, #32 8019b78: 6023 str r3, [r4, #0] 8019b7a: 4835 ldr r0, [pc, #212] @ (8019c50 <_printf_i+0x248>) 8019b7c: 2578 movs r5, #120 @ 0x78 8019b7e: f884 5045 strb.w r5, [r4, #69] @ 0x45 8019b82: 6823 ldr r3, [r4, #0] 8019b84: 6831 ldr r1, [r6, #0] 8019b86: f013 0f80 tst.w r3, #128 @ 0x80 8019b8a: f851 5b04 ldr.w r5, [r1], #4 8019b8e: d103 bne.n 8019b98 <_printf_i+0x190> 8019b90: f013 0f40 tst.w r3, #64 @ 0x40 8019b94: bf18 it ne 8019b96: b2ad uxthne r5, r5 8019b98: 6031 str r1, [r6, #0] 8019b9a: 07d9 lsls r1, r3, #31 8019b9c: bf44 itt mi 8019b9e: f043 0320 orrmi.w r3, r3, #32 8019ba2: 6023 strmi r3, [r4, #0] 8019ba4: b11d cbz r5, 8019bae <_printf_i+0x1a6> 8019ba6: 2310 movs r3, #16 8019ba8: e7aa b.n 8019b00 <_printf_i+0xf8> 8019baa: 4828 ldr r0, [pc, #160] @ (8019c4c <_printf_i+0x244>) 8019bac: e7e7 b.n 8019b7e <_printf_i+0x176> 8019bae: 6823 ldr r3, [r4, #0] 8019bb0: f023 0320 bic.w r3, r3, #32 8019bb4: 6023 str r3, [r4, #0] 8019bb6: e7f6 b.n 8019ba6 <_printf_i+0x19e> 8019bb8: 230a movs r3, #10 8019bba: e7a1 b.n 8019b00 <_printf_i+0xf8> 8019bbc: 4616 mov r6, r2 8019bbe: e7b9 b.n 8019b34 <_printf_i+0x12c> 8019bc0: 6833 ldr r3, [r6, #0] 8019bc2: 6825 ldr r5, [r4, #0] 8019bc4: 6961 ldr r1, [r4, #20] 8019bc6: 1d18 adds r0, r3, #4 8019bc8: 6030 str r0, [r6, #0] 8019bca: 062e lsls r6, r5, #24 8019bcc: 681b ldr r3, [r3, #0] 8019bce: d501 bpl.n 8019bd4 <_printf_i+0x1cc> 8019bd0: 6019 str r1, [r3, #0] 8019bd2: e002 b.n 8019bda <_printf_i+0x1d2> 8019bd4: 0668 lsls r0, r5, #25 8019bd6: d5fb bpl.n 8019bd0 <_printf_i+0x1c8> 8019bd8: 8019 strh r1, [r3, #0] 8019bda: 2300 movs r3, #0 8019bdc: 6123 str r3, [r4, #16] 8019bde: 4616 mov r6, r2 8019be0: e7b8 b.n 8019b54 <_printf_i+0x14c> 8019be2: 6833 ldr r3, [r6, #0] 8019be4: 1d1a adds r2, r3, #4 8019be6: 6032 str r2, [r6, #0] 8019be8: 681e ldr r6, [r3, #0] 8019bea: 6862 ldr r2, [r4, #4] 8019bec: 2100 movs r1, #0 8019bee: 4630 mov r0, r6 8019bf0: f7e6 fac6 bl 8000180 8019bf4: b108 cbz r0, 8019bfa <_printf_i+0x1f2> 8019bf6: 1b80 subs r0, r0, r6 8019bf8: 6060 str r0, [r4, #4] 8019bfa: 6863 ldr r3, [r4, #4] 8019bfc: 6123 str r3, [r4, #16] 8019bfe: 2300 movs r3, #0 8019c00: f884 3043 strb.w r3, [r4, #67] @ 0x43 8019c04: e7a6 b.n 8019b54 <_printf_i+0x14c> 8019c06: 6923 ldr r3, [r4, #16] 8019c08: 4632 mov r2, r6 8019c0a: 4641 mov r1, r8 8019c0c: 4638 mov r0, r7 8019c0e: 47c8 blx r9 8019c10: 3001 adds r0, #1 8019c12: d0a9 beq.n 8019b68 <_printf_i+0x160> 8019c14: 6823 ldr r3, [r4, #0] 8019c16: 079b lsls r3, r3, #30 8019c18: d413 bmi.n 8019c42 <_printf_i+0x23a> 8019c1a: 68e0 ldr r0, [r4, #12] 8019c1c: 9b03 ldr r3, [sp, #12] 8019c1e: 4298 cmp r0, r3 8019c20: bfb8 it lt 8019c22: 4618 movlt r0, r3 8019c24: e7a2 b.n 8019b6c <_printf_i+0x164> 8019c26: 2301 movs r3, #1 8019c28: 4632 mov r2, r6 8019c2a: 4641 mov r1, r8 8019c2c: 4638 mov r0, r7 8019c2e: 47c8 blx r9 8019c30: 3001 adds r0, #1 8019c32: d099 beq.n 8019b68 <_printf_i+0x160> 8019c34: 3501 adds r5, #1 8019c36: 68e3 ldr r3, [r4, #12] 8019c38: 9903 ldr r1, [sp, #12] 8019c3a: 1a5b subs r3, r3, r1 8019c3c: 42ab cmp r3, r5 8019c3e: dcf2 bgt.n 8019c26 <_printf_i+0x21e> 8019c40: e7eb b.n 8019c1a <_printf_i+0x212> 8019c42: 2500 movs r5, #0 8019c44: f104 0619 add.w r6, r4, #25 8019c48: e7f5 b.n 8019c36 <_printf_i+0x22e> 8019c4a: bf00 nop 8019c4c: 0801e602 .word 0x0801e602 8019c50: 0801e613 .word 0x0801e613 08019c54 <_scanf_float>: 8019c54: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8019c58: b087 sub sp, #28 8019c5a: 4691 mov r9, r2 8019c5c: 9303 str r3, [sp, #12] 8019c5e: 688b ldr r3, [r1, #8] 8019c60: 1e5a subs r2, r3, #1 8019c62: f5b2 7fae cmp.w r2, #348 @ 0x15c 8019c66: bf81 itttt hi 8019c68: f46f 75ae mvnhi.w r5, #348 @ 0x15c 8019c6c: eb03 0b05 addhi.w fp, r3, r5 8019c70: f240 135d movwhi r3, #349 @ 0x15d 8019c74: 608b strhi r3, [r1, #8] 8019c76: 680b ldr r3, [r1, #0] 8019c78: 460a mov r2, r1 8019c7a: f04f 0500 mov.w r5, #0 8019c7e: f443 63f0 orr.w r3, r3, #1920 @ 0x780 8019c82: f842 3b1c str.w r3, [r2], #28 8019c86: e9cd 5504 strd r5, r5, [sp, #16] 8019c8a: 4680 mov r8, r0 8019c8c: 460c mov r4, r1 8019c8e: bf98 it ls 8019c90: f04f 0b00 movls.w fp, #0 8019c94: 9201 str r2, [sp, #4] 8019c96: 4616 mov r6, r2 8019c98: 46aa mov sl, r5 8019c9a: 462f mov r7, r5 8019c9c: 9502 str r5, [sp, #8] 8019c9e: 68a2 ldr r2, [r4, #8] 8019ca0: b15a cbz r2, 8019cba <_scanf_float+0x66> 8019ca2: f8d9 3000 ldr.w r3, [r9] 8019ca6: 781b ldrb r3, [r3, #0] 8019ca8: 2b4e cmp r3, #78 @ 0x4e 8019caa: d863 bhi.n 8019d74 <_scanf_float+0x120> 8019cac: 2b40 cmp r3, #64 @ 0x40 8019cae: d83b bhi.n 8019d28 <_scanf_float+0xd4> 8019cb0: f1a3 012b sub.w r1, r3, #43 @ 0x2b 8019cb4: b2c8 uxtb r0, r1 8019cb6: 280e cmp r0, #14 8019cb8: d939 bls.n 8019d2e <_scanf_float+0xda> 8019cba: b11f cbz r7, 8019cc4 <_scanf_float+0x70> 8019cbc: 6823 ldr r3, [r4, #0] 8019cbe: f423 7380 bic.w r3, r3, #256 @ 0x100 8019cc2: 6023 str r3, [r4, #0] 8019cc4: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 8019cc8: f1ba 0f01 cmp.w sl, #1 8019ccc: f200 8114 bhi.w 8019ef8 <_scanf_float+0x2a4> 8019cd0: 9b01 ldr r3, [sp, #4] 8019cd2: 429e cmp r6, r3 8019cd4: f200 8105 bhi.w 8019ee2 <_scanf_float+0x28e> 8019cd8: 2001 movs r0, #1 8019cda: b007 add sp, #28 8019cdc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8019ce0: f1a3 0261 sub.w r2, r3, #97 @ 0x61 8019ce4: 2a0d cmp r2, #13 8019ce6: d8e8 bhi.n 8019cba <_scanf_float+0x66> 8019ce8: a101 add r1, pc, #4 @ (adr r1, 8019cf0 <_scanf_float+0x9c>) 8019cea: f851 f022 ldr.w pc, [r1, r2, lsl #2] 8019cee: bf00 nop 8019cf0: 08019e39 .word 0x08019e39 8019cf4: 08019cbb .word 0x08019cbb 8019cf8: 08019cbb .word 0x08019cbb 8019cfc: 08019cbb .word 0x08019cbb 8019d00: 08019e95 .word 0x08019e95 8019d04: 08019e6f .word 0x08019e6f 8019d08: 08019cbb .word 0x08019cbb 8019d0c: 08019cbb .word 0x08019cbb 8019d10: 08019e47 .word 0x08019e47 8019d14: 08019cbb .word 0x08019cbb 8019d18: 08019cbb .word 0x08019cbb 8019d1c: 08019cbb .word 0x08019cbb 8019d20: 08019cbb .word 0x08019cbb 8019d24: 08019e03 .word 0x08019e03 8019d28: f1a3 0241 sub.w r2, r3, #65 @ 0x41 8019d2c: e7da b.n 8019ce4 <_scanf_float+0x90> 8019d2e: 290e cmp r1, #14 8019d30: d8c3 bhi.n 8019cba <_scanf_float+0x66> 8019d32: a001 add r0, pc, #4 @ (adr r0, 8019d38 <_scanf_float+0xe4>) 8019d34: f850 f021 ldr.w pc, [r0, r1, lsl #2] 8019d38: 08019df3 .word 0x08019df3 8019d3c: 08019cbb .word 0x08019cbb 8019d40: 08019df3 .word 0x08019df3 8019d44: 08019e83 .word 0x08019e83 8019d48: 08019cbb .word 0x08019cbb 8019d4c: 08019d95 .word 0x08019d95 8019d50: 08019dd9 .word 0x08019dd9 8019d54: 08019dd9 .word 0x08019dd9 8019d58: 08019dd9 .word 0x08019dd9 8019d5c: 08019dd9 .word 0x08019dd9 8019d60: 08019dd9 .word 0x08019dd9 8019d64: 08019dd9 .word 0x08019dd9 8019d68: 08019dd9 .word 0x08019dd9 8019d6c: 08019dd9 .word 0x08019dd9 8019d70: 08019dd9 .word 0x08019dd9 8019d74: 2b6e cmp r3, #110 @ 0x6e 8019d76: d809 bhi.n 8019d8c <_scanf_float+0x138> 8019d78: 2b60 cmp r3, #96 @ 0x60 8019d7a: d8b1 bhi.n 8019ce0 <_scanf_float+0x8c> 8019d7c: 2b54 cmp r3, #84 @ 0x54 8019d7e: d07b beq.n 8019e78 <_scanf_float+0x224> 8019d80: 2b59 cmp r3, #89 @ 0x59 8019d82: d19a bne.n 8019cba <_scanf_float+0x66> 8019d84: 2d07 cmp r5, #7 8019d86: d198 bne.n 8019cba <_scanf_float+0x66> 8019d88: 2508 movs r5, #8 8019d8a: e02f b.n 8019dec <_scanf_float+0x198> 8019d8c: 2b74 cmp r3, #116 @ 0x74 8019d8e: d073 beq.n 8019e78 <_scanf_float+0x224> 8019d90: 2b79 cmp r3, #121 @ 0x79 8019d92: e7f6 b.n 8019d82 <_scanf_float+0x12e> 8019d94: 6821 ldr r1, [r4, #0] 8019d96: 05c8 lsls r0, r1, #23 8019d98: d51e bpl.n 8019dd8 <_scanf_float+0x184> 8019d9a: f021 0180 bic.w r1, r1, #128 @ 0x80 8019d9e: 6021 str r1, [r4, #0] 8019da0: 3701 adds r7, #1 8019da2: f1bb 0f00 cmp.w fp, #0 8019da6: d003 beq.n 8019db0 <_scanf_float+0x15c> 8019da8: 3201 adds r2, #1 8019daa: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff 8019dae: 60a2 str r2, [r4, #8] 8019db0: 68a3 ldr r3, [r4, #8] 8019db2: 3b01 subs r3, #1 8019db4: 60a3 str r3, [r4, #8] 8019db6: 6923 ldr r3, [r4, #16] 8019db8: 3301 adds r3, #1 8019dba: 6123 str r3, [r4, #16] 8019dbc: f8d9 3004 ldr.w r3, [r9, #4] 8019dc0: 3b01 subs r3, #1 8019dc2: 2b00 cmp r3, #0 8019dc4: f8c9 3004 str.w r3, [r9, #4] 8019dc8: f340 8082 ble.w 8019ed0 <_scanf_float+0x27c> 8019dcc: f8d9 3000 ldr.w r3, [r9] 8019dd0: 3301 adds r3, #1 8019dd2: f8c9 3000 str.w r3, [r9] 8019dd6: e762 b.n 8019c9e <_scanf_float+0x4a> 8019dd8: eb1a 0105 adds.w r1, sl, r5 8019ddc: f47f af6d bne.w 8019cba <_scanf_float+0x66> 8019de0: 6822 ldr r2, [r4, #0] 8019de2: f422 72c0 bic.w r2, r2, #384 @ 0x180 8019de6: 6022 str r2, [r4, #0] 8019de8: 460d mov r5, r1 8019dea: 468a mov sl, r1 8019dec: f806 3b01 strb.w r3, [r6], #1 8019df0: e7de b.n 8019db0 <_scanf_float+0x15c> 8019df2: 6822 ldr r2, [r4, #0] 8019df4: 0610 lsls r0, r2, #24 8019df6: f57f af60 bpl.w 8019cba <_scanf_float+0x66> 8019dfa: f022 0280 bic.w r2, r2, #128 @ 0x80 8019dfe: 6022 str r2, [r4, #0] 8019e00: e7f4 b.n 8019dec <_scanf_float+0x198> 8019e02: f1ba 0f00 cmp.w sl, #0 8019e06: d10c bne.n 8019e22 <_scanf_float+0x1ce> 8019e08: b977 cbnz r7, 8019e28 <_scanf_float+0x1d4> 8019e0a: 6822 ldr r2, [r4, #0] 8019e0c: f402 61e0 and.w r1, r2, #1792 @ 0x700 8019e10: f5b1 6fe0 cmp.w r1, #1792 @ 0x700 8019e14: d108 bne.n 8019e28 <_scanf_float+0x1d4> 8019e16: f422 62f0 bic.w r2, r2, #1920 @ 0x780 8019e1a: 6022 str r2, [r4, #0] 8019e1c: f04f 0a01 mov.w sl, #1 8019e20: e7e4 b.n 8019dec <_scanf_float+0x198> 8019e22: f1ba 0f02 cmp.w sl, #2 8019e26: d050 beq.n 8019eca <_scanf_float+0x276> 8019e28: 2d01 cmp r5, #1 8019e2a: d002 beq.n 8019e32 <_scanf_float+0x1de> 8019e2c: 2d04 cmp r5, #4 8019e2e: f47f af44 bne.w 8019cba <_scanf_float+0x66> 8019e32: 3501 adds r5, #1 8019e34: b2ed uxtb r5, r5 8019e36: e7d9 b.n 8019dec <_scanf_float+0x198> 8019e38: f1ba 0f01 cmp.w sl, #1 8019e3c: f47f af3d bne.w 8019cba <_scanf_float+0x66> 8019e40: f04f 0a02 mov.w sl, #2 8019e44: e7d2 b.n 8019dec <_scanf_float+0x198> 8019e46: b975 cbnz r5, 8019e66 <_scanf_float+0x212> 8019e48: 2f00 cmp r7, #0 8019e4a: f47f af37 bne.w 8019cbc <_scanf_float+0x68> 8019e4e: 6822 ldr r2, [r4, #0] 8019e50: f402 61e0 and.w r1, r2, #1792 @ 0x700 8019e54: f5b1 6fe0 cmp.w r1, #1792 @ 0x700 8019e58: f040 8102 bne.w 801a060 <_scanf_float+0x40c> 8019e5c: f422 62f0 bic.w r2, r2, #1920 @ 0x780 8019e60: 6022 str r2, [r4, #0] 8019e62: 2501 movs r5, #1 8019e64: e7c2 b.n 8019dec <_scanf_float+0x198> 8019e66: 2d03 cmp r5, #3 8019e68: d0e3 beq.n 8019e32 <_scanf_float+0x1de> 8019e6a: 2d05 cmp r5, #5 8019e6c: e7df b.n 8019e2e <_scanf_float+0x1da> 8019e6e: 2d02 cmp r5, #2 8019e70: f47f af23 bne.w 8019cba <_scanf_float+0x66> 8019e74: 2503 movs r5, #3 8019e76: e7b9 b.n 8019dec <_scanf_float+0x198> 8019e78: 2d06 cmp r5, #6 8019e7a: f47f af1e bne.w 8019cba <_scanf_float+0x66> 8019e7e: 2507 movs r5, #7 8019e80: e7b4 b.n 8019dec <_scanf_float+0x198> 8019e82: 6822 ldr r2, [r4, #0] 8019e84: 0591 lsls r1, r2, #22 8019e86: f57f af18 bpl.w 8019cba <_scanf_float+0x66> 8019e8a: f422 7220 bic.w r2, r2, #640 @ 0x280 8019e8e: 6022 str r2, [r4, #0] 8019e90: 9702 str r7, [sp, #8] 8019e92: e7ab b.n 8019dec <_scanf_float+0x198> 8019e94: 6822 ldr r2, [r4, #0] 8019e96: f402 61a0 and.w r1, r2, #1280 @ 0x500 8019e9a: f5b1 6f80 cmp.w r1, #1024 @ 0x400 8019e9e: d005 beq.n 8019eac <_scanf_float+0x258> 8019ea0: 0550 lsls r0, r2, #21 8019ea2: f57f af0a bpl.w 8019cba <_scanf_float+0x66> 8019ea6: 2f00 cmp r7, #0 8019ea8: f000 80da beq.w 801a060 <_scanf_float+0x40c> 8019eac: 0591 lsls r1, r2, #22 8019eae: bf58 it pl 8019eb0: 9902 ldrpl r1, [sp, #8] 8019eb2: f422 62f0 bic.w r2, r2, #1920 @ 0x780 8019eb6: bf58 it pl 8019eb8: 1a79 subpl r1, r7, r1 8019eba: f442 72c0 orr.w r2, r2, #384 @ 0x180 8019ebe: bf58 it pl 8019ec0: e9cd 1604 strdpl r1, r6, [sp, #16] 8019ec4: 6022 str r2, [r4, #0] 8019ec6: 2700 movs r7, #0 8019ec8: e790 b.n 8019dec <_scanf_float+0x198> 8019eca: f04f 0a03 mov.w sl, #3 8019ece: e78d b.n 8019dec <_scanf_float+0x198> 8019ed0: f8d4 3180 ldr.w r3, [r4, #384] @ 0x180 8019ed4: 4649 mov r1, r9 8019ed6: 4640 mov r0, r8 8019ed8: 4798 blx r3 8019eda: 2800 cmp r0, #0 8019edc: f43f aedf beq.w 8019c9e <_scanf_float+0x4a> 8019ee0: e6eb b.n 8019cba <_scanf_float+0x66> 8019ee2: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 8019ee6: f816 1d01 ldrb.w r1, [r6, #-1]! 8019eea: 464a mov r2, r9 8019eec: 4640 mov r0, r8 8019eee: 4798 blx r3 8019ef0: 6923 ldr r3, [r4, #16] 8019ef2: 3b01 subs r3, #1 8019ef4: 6123 str r3, [r4, #16] 8019ef6: e6eb b.n 8019cd0 <_scanf_float+0x7c> 8019ef8: 1e6b subs r3, r5, #1 8019efa: 2b06 cmp r3, #6 8019efc: d824 bhi.n 8019f48 <_scanf_float+0x2f4> 8019efe: 2d02 cmp r5, #2 8019f00: d836 bhi.n 8019f70 <_scanf_float+0x31c> 8019f02: 9b01 ldr r3, [sp, #4] 8019f04: 429e cmp r6, r3 8019f06: f67f aee7 bls.w 8019cd8 <_scanf_float+0x84> 8019f0a: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 8019f0e: f816 1d01 ldrb.w r1, [r6, #-1]! 8019f12: 464a mov r2, r9 8019f14: 4640 mov r0, r8 8019f16: 4798 blx r3 8019f18: 6923 ldr r3, [r4, #16] 8019f1a: 3b01 subs r3, #1 8019f1c: 6123 str r3, [r4, #16] 8019f1e: e7f0 b.n 8019f02 <_scanf_float+0x2ae> 8019f20: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 8019f24: f81b 1d01 ldrb.w r1, [fp, #-1]! 8019f28: 464a mov r2, r9 8019f2a: 4640 mov r0, r8 8019f2c: 4798 blx r3 8019f2e: 6923 ldr r3, [r4, #16] 8019f30: 3b01 subs r3, #1 8019f32: 6123 str r3, [r4, #16] 8019f34: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff 8019f38: fa5f fa8a uxtb.w sl, sl 8019f3c: f1ba 0f02 cmp.w sl, #2 8019f40: d1ee bne.n 8019f20 <_scanf_float+0x2cc> 8019f42: 3d03 subs r5, #3 8019f44: b2ed uxtb r5, r5 8019f46: 1b76 subs r6, r6, r5 8019f48: 6823 ldr r3, [r4, #0] 8019f4a: 05da lsls r2, r3, #23 8019f4c: d530 bpl.n 8019fb0 <_scanf_float+0x35c> 8019f4e: 055d lsls r5, r3, #21 8019f50: d511 bpl.n 8019f76 <_scanf_float+0x322> 8019f52: 9b01 ldr r3, [sp, #4] 8019f54: 429e cmp r6, r3 8019f56: f67f aebf bls.w 8019cd8 <_scanf_float+0x84> 8019f5a: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 8019f5e: f816 1d01 ldrb.w r1, [r6, #-1]! 8019f62: 464a mov r2, r9 8019f64: 4640 mov r0, r8 8019f66: 4798 blx r3 8019f68: 6923 ldr r3, [r4, #16] 8019f6a: 3b01 subs r3, #1 8019f6c: 6123 str r3, [r4, #16] 8019f6e: e7f0 b.n 8019f52 <_scanf_float+0x2fe> 8019f70: 46aa mov sl, r5 8019f72: 46b3 mov fp, r6 8019f74: e7de b.n 8019f34 <_scanf_float+0x2e0> 8019f76: f816 1c01 ldrb.w r1, [r6, #-1] 8019f7a: 6923 ldr r3, [r4, #16] 8019f7c: 2965 cmp r1, #101 @ 0x65 8019f7e: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 8019f82: f106 35ff add.w r5, r6, #4294967295 @ 0xffffffff 8019f86: 6123 str r3, [r4, #16] 8019f88: d00c beq.n 8019fa4 <_scanf_float+0x350> 8019f8a: 2945 cmp r1, #69 @ 0x45 8019f8c: d00a beq.n 8019fa4 <_scanf_float+0x350> 8019f8e: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 8019f92: 464a mov r2, r9 8019f94: 4640 mov r0, r8 8019f96: 4798 blx r3 8019f98: 6923 ldr r3, [r4, #16] 8019f9a: f816 1c02 ldrb.w r1, [r6, #-2] 8019f9e: 3b01 subs r3, #1 8019fa0: 1eb5 subs r5, r6, #2 8019fa2: 6123 str r3, [r4, #16] 8019fa4: f8d4 317c ldr.w r3, [r4, #380] @ 0x17c 8019fa8: 464a mov r2, r9 8019faa: 4640 mov r0, r8 8019fac: 4798 blx r3 8019fae: 462e mov r6, r5 8019fb0: 6822 ldr r2, [r4, #0] 8019fb2: f012 0210 ands.w r2, r2, #16 8019fb6: d001 beq.n 8019fbc <_scanf_float+0x368> 8019fb8: 2000 movs r0, #0 8019fba: e68e b.n 8019cda <_scanf_float+0x86> 8019fbc: 7032 strb r2, [r6, #0] 8019fbe: 6823 ldr r3, [r4, #0] 8019fc0: f403 63c0 and.w r3, r3, #1536 @ 0x600 8019fc4: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8019fc8: d124 bne.n 801a014 <_scanf_float+0x3c0> 8019fca: 9b02 ldr r3, [sp, #8] 8019fcc: 429f cmp r7, r3 8019fce: d00a beq.n 8019fe6 <_scanf_float+0x392> 8019fd0: 1bda subs r2, r3, r7 8019fd2: f204 136f addw r3, r4, #367 @ 0x16f 8019fd6: 429e cmp r6, r3 8019fd8: bf28 it cs 8019fda: f504 76b7 addcs.w r6, r4, #366 @ 0x16e 8019fde: 4921 ldr r1, [pc, #132] @ (801a064 <_scanf_float+0x410>) 8019fe0: 4630 mov r0, r6 8019fe2: f000 f919 bl 801a218 8019fe6: 9901 ldr r1, [sp, #4] 8019fe8: 2200 movs r2, #0 8019fea: 4640 mov r0, r8 8019fec: f002 fc84 bl 801c8f8 <_strtod_r> 8019ff0: 9b03 ldr r3, [sp, #12] 8019ff2: 6821 ldr r1, [r4, #0] 8019ff4: 681b ldr r3, [r3, #0] 8019ff6: 0788 lsls r0, r1, #30 8019ff8: ec57 6b10 vmov r6, r7, d0 8019ffc: f103 0204 add.w r2, r3, #4 801a000: d515 bpl.n 801a02e <_scanf_float+0x3da> 801a002: 9903 ldr r1, [sp, #12] 801a004: 600a str r2, [r1, #0] 801a006: 681b ldr r3, [r3, #0] 801a008: e9c3 6700 strd r6, r7, [r3] 801a00c: 68e3 ldr r3, [r4, #12] 801a00e: 3301 adds r3, #1 801a010: 60e3 str r3, [r4, #12] 801a012: e7d1 b.n 8019fb8 <_scanf_float+0x364> 801a014: 9b04 ldr r3, [sp, #16] 801a016: 2b00 cmp r3, #0 801a018: d0e5 beq.n 8019fe6 <_scanf_float+0x392> 801a01a: 9905 ldr r1, [sp, #20] 801a01c: 230a movs r3, #10 801a01e: 3101 adds r1, #1 801a020: 4640 mov r0, r8 801a022: f002 fce9 bl 801c9f8 <_strtol_r> 801a026: 9b04 ldr r3, [sp, #16] 801a028: 9e05 ldr r6, [sp, #20] 801a02a: 1ac2 subs r2, r0, r3 801a02c: e7d1 b.n 8019fd2 <_scanf_float+0x37e> 801a02e: f011 0f04 tst.w r1, #4 801a032: 9903 ldr r1, [sp, #12] 801a034: 600a str r2, [r1, #0] 801a036: d1e6 bne.n 801a006 <_scanf_float+0x3b2> 801a038: 681d ldr r5, [r3, #0] 801a03a: 4632 mov r2, r6 801a03c: 463b mov r3, r7 801a03e: 4630 mov r0, r6 801a040: 4639 mov r1, r7 801a042: f7e6 fd4b bl 8000adc <__aeabi_dcmpun> 801a046: b128 cbz r0, 801a054 <_scanf_float+0x400> 801a048: 4807 ldr r0, [pc, #28] @ (801a068 <_scanf_float+0x414>) 801a04a: f000 fa37 bl 801a4bc 801a04e: ed85 0a00 vstr s0, [r5] 801a052: e7db b.n 801a00c <_scanf_float+0x3b8> 801a054: 4630 mov r0, r6 801a056: 4639 mov r1, r7 801a058: f7e6 fd9e bl 8000b98 <__aeabi_d2f> 801a05c: 6028 str r0, [r5, #0] 801a05e: e7d5 b.n 801a00c <_scanf_float+0x3b8> 801a060: 2700 movs r7, #0 801a062: e62f b.n 8019cc4 <_scanf_float+0x70> 801a064: 0801e624 .word 0x0801e624 801a068: 0801e765 .word 0x0801e765 0801a06c : 801a06c: 2300 movs r3, #0 801a06e: b510 push {r4, lr} 801a070: 4604 mov r4, r0 801a072: e9c0 3300 strd r3, r3, [r0] 801a076: e9c0 3304 strd r3, r3, [r0, #16] 801a07a: 6083 str r3, [r0, #8] 801a07c: 8181 strh r1, [r0, #12] 801a07e: 6643 str r3, [r0, #100] @ 0x64 801a080: 81c2 strh r2, [r0, #14] 801a082: 6183 str r3, [r0, #24] 801a084: 4619 mov r1, r3 801a086: 2208 movs r2, #8 801a088: 305c adds r0, #92 @ 0x5c 801a08a: f000 f92b bl 801a2e4 801a08e: 4b0d ldr r3, [pc, #52] @ (801a0c4 ) 801a090: 6263 str r3, [r4, #36] @ 0x24 801a092: 4b0d ldr r3, [pc, #52] @ (801a0c8 ) 801a094: 62a3 str r3, [r4, #40] @ 0x28 801a096: 4b0d ldr r3, [pc, #52] @ (801a0cc ) 801a098: 62e3 str r3, [r4, #44] @ 0x2c 801a09a: 4b0d ldr r3, [pc, #52] @ (801a0d0 ) 801a09c: 6323 str r3, [r4, #48] @ 0x30 801a09e: 4b0d ldr r3, [pc, #52] @ (801a0d4 ) 801a0a0: 6224 str r4, [r4, #32] 801a0a2: 429c cmp r4, r3 801a0a4: d006 beq.n 801a0b4 801a0a6: f103 0268 add.w r2, r3, #104 @ 0x68 801a0aa: 4294 cmp r4, r2 801a0ac: d002 beq.n 801a0b4 801a0ae: 33d0 adds r3, #208 @ 0xd0 801a0b0: 429c cmp r4, r3 801a0b2: d105 bne.n 801a0c0 801a0b4: f104 0058 add.w r0, r4, #88 @ 0x58 801a0b8: e8bd 4010 ldmia.w sp!, {r4, lr} 801a0bc: f000 b9ec b.w 801a498 <__retarget_lock_init_recursive> 801a0c0: bd10 pop {r4, pc} 801a0c2: bf00 nop 801a0c4: 0801a25d .word 0x0801a25d 801a0c8: 0801a27f .word 0x0801a27f 801a0cc: 0801a2b7 .word 0x0801a2b7 801a0d0: 0801a2dd .word 0x0801a2dd 801a0d4: 20013b9c .word 0x20013b9c 0801a0d8 : 801a0d8: 4a02 ldr r2, [pc, #8] @ (801a0e4 ) 801a0da: 4903 ldr r1, [pc, #12] @ (801a0e8 ) 801a0dc: 4803 ldr r0, [pc, #12] @ (801a0ec ) 801a0de: f000 b86b b.w 801a1b8 <_fwalk_sglue> 801a0e2: bf00 nop 801a0e4: 20000110 .word 0x20000110 801a0e8: 0801d02d .word 0x0801d02d 801a0ec: 20000120 .word 0x20000120 0801a0f0 : 801a0f0: 6841 ldr r1, [r0, #4] 801a0f2: 4b0c ldr r3, [pc, #48] @ (801a124 ) 801a0f4: 4299 cmp r1, r3 801a0f6: b510 push {r4, lr} 801a0f8: 4604 mov r4, r0 801a0fa: d001 beq.n 801a100 801a0fc: f002 ff96 bl 801d02c <_fflush_r> 801a100: 68a1 ldr r1, [r4, #8] 801a102: 4b09 ldr r3, [pc, #36] @ (801a128 ) 801a104: 4299 cmp r1, r3 801a106: d002 beq.n 801a10e 801a108: 4620 mov r0, r4 801a10a: f002 ff8f bl 801d02c <_fflush_r> 801a10e: 68e1 ldr r1, [r4, #12] 801a110: 4b06 ldr r3, [pc, #24] @ (801a12c ) 801a112: 4299 cmp r1, r3 801a114: d004 beq.n 801a120 801a116: 4620 mov r0, r4 801a118: e8bd 4010 ldmia.w sp!, {r4, lr} 801a11c: f002 bf86 b.w 801d02c <_fflush_r> 801a120: bd10 pop {r4, pc} 801a122: bf00 nop 801a124: 20013b9c .word 0x20013b9c 801a128: 20013c04 .word 0x20013c04 801a12c: 20013c6c .word 0x20013c6c 0801a130 : 801a130: 4b0c ldr r3, [pc, #48] @ (801a164 ) 801a132: 4a0d ldr r2, [pc, #52] @ (801a168 ) 801a134: 480d ldr r0, [pc, #52] @ (801a16c ) 801a136: b510 push {r4, lr} 801a138: 2104 movs r1, #4 801a13a: 601a str r2, [r3, #0] 801a13c: 2200 movs r2, #0 801a13e: f7ff ff95 bl 801a06c 801a142: 4b0a ldr r3, [pc, #40] @ (801a16c ) 801a144: 2201 movs r2, #1 801a146: 461c mov r4, r3 801a148: 2109 movs r1, #9 801a14a: f103 0068 add.w r0, r3, #104 @ 0x68 801a14e: f7ff ff8d bl 801a06c 801a152: f104 00d0 add.w r0, r4, #208 @ 0xd0 801a156: 2202 movs r2, #2 801a158: e8bd 4010 ldmia.w sp!, {r4, lr} 801a15c: 2112 movs r1, #18 801a15e: f7ff bf85 b.w 801a06c 801a162: bf00 nop 801a164: 20013cd4 .word 0x20013cd4 801a168: 0801a0d9 .word 0x0801a0d9 801a16c: 20013b9c .word 0x20013b9c 0801a170 <__sfp_lock_acquire>: 801a170: 4801 ldr r0, [pc, #4] @ (801a178 <__sfp_lock_acquire+0x8>) 801a172: f000 b992 b.w 801a49a <__retarget_lock_acquire_recursive> 801a176: bf00 nop 801a178: 20013cdd .word 0x20013cdd 0801a17c <__sfp_lock_release>: 801a17c: 4801 ldr r0, [pc, #4] @ (801a184 <__sfp_lock_release+0x8>) 801a17e: f000 b98d b.w 801a49c <__retarget_lock_release_recursive> 801a182: bf00 nop 801a184: 20013cdd .word 0x20013cdd 0801a188 <__sinit>: 801a188: b510 push {r4, lr} 801a18a: 4604 mov r4, r0 801a18c: f7ff fff0 bl 801a170 <__sfp_lock_acquire> 801a190: 6a23 ldr r3, [r4, #32] 801a192: b11b cbz r3, 801a19c <__sinit+0x14> 801a194: e8bd 4010 ldmia.w sp!, {r4, lr} 801a198: f7ff bff0 b.w 801a17c <__sfp_lock_release> 801a19c: 4b04 ldr r3, [pc, #16] @ (801a1b0 <__sinit+0x28>) 801a19e: 6223 str r3, [r4, #32] 801a1a0: 4b04 ldr r3, [pc, #16] @ (801a1b4 <__sinit+0x2c>) 801a1a2: 681b ldr r3, [r3, #0] 801a1a4: 2b00 cmp r3, #0 801a1a6: d1f5 bne.n 801a194 <__sinit+0xc> 801a1a8: f7ff ffc2 bl 801a130 801a1ac: e7f2 b.n 801a194 <__sinit+0xc> 801a1ae: bf00 nop 801a1b0: 0801a0f1 .word 0x0801a0f1 801a1b4: 20013cd4 .word 0x20013cd4 0801a1b8 <_fwalk_sglue>: 801a1b8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801a1bc: 4607 mov r7, r0 801a1be: 4688 mov r8, r1 801a1c0: 4614 mov r4, r2 801a1c2: 2600 movs r6, #0 801a1c4: e9d4 9501 ldrd r9, r5, [r4, #4] 801a1c8: f1b9 0901 subs.w r9, r9, #1 801a1cc: d505 bpl.n 801a1da <_fwalk_sglue+0x22> 801a1ce: 6824 ldr r4, [r4, #0] 801a1d0: 2c00 cmp r4, #0 801a1d2: d1f7 bne.n 801a1c4 <_fwalk_sglue+0xc> 801a1d4: 4630 mov r0, r6 801a1d6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801a1da: 89ab ldrh r3, [r5, #12] 801a1dc: 2b01 cmp r3, #1 801a1de: d907 bls.n 801a1f0 <_fwalk_sglue+0x38> 801a1e0: f9b5 300e ldrsh.w r3, [r5, #14] 801a1e4: 3301 adds r3, #1 801a1e6: d003 beq.n 801a1f0 <_fwalk_sglue+0x38> 801a1e8: 4629 mov r1, r5 801a1ea: 4638 mov r0, r7 801a1ec: 47c0 blx r8 801a1ee: 4306 orrs r6, r0 801a1f0: 3568 adds r5, #104 @ 0x68 801a1f2: e7e9 b.n 801a1c8 <_fwalk_sglue+0x10> 0801a1f4 : 801a1f4: b40f push {r0, r1, r2, r3} 801a1f6: b507 push {r0, r1, r2, lr} 801a1f8: 4906 ldr r1, [pc, #24] @ (801a214 ) 801a1fa: ab04 add r3, sp, #16 801a1fc: 6808 ldr r0, [r1, #0] 801a1fe: f853 2b04 ldr.w r2, [r3], #4 801a202: 6881 ldr r1, [r0, #8] 801a204: 9301 str r3, [sp, #4] 801a206: f002 fd7b bl 801cd00 <_vfiprintf_r> 801a20a: b003 add sp, #12 801a20c: f85d eb04 ldr.w lr, [sp], #4 801a210: b004 add sp, #16 801a212: 4770 bx lr 801a214: 2000011c .word 0x2000011c 0801a218 : 801a218: b40e push {r1, r2, r3} 801a21a: b510 push {r4, lr} 801a21c: b09d sub sp, #116 @ 0x74 801a21e: ab1f add r3, sp, #124 @ 0x7c 801a220: 9002 str r0, [sp, #8] 801a222: 9006 str r0, [sp, #24] 801a224: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000 801a228: 480a ldr r0, [pc, #40] @ (801a254 ) 801a22a: 9107 str r1, [sp, #28] 801a22c: 9104 str r1, [sp, #16] 801a22e: 490a ldr r1, [pc, #40] @ (801a258 ) 801a230: f853 2b04 ldr.w r2, [r3], #4 801a234: 9105 str r1, [sp, #20] 801a236: 2400 movs r4, #0 801a238: a902 add r1, sp, #8 801a23a: 6800 ldr r0, [r0, #0] 801a23c: 9301 str r3, [sp, #4] 801a23e: 941b str r4, [sp, #108] @ 0x6c 801a240: f002 fc3c bl 801cabc <_svfiprintf_r> 801a244: 9b02 ldr r3, [sp, #8] 801a246: 701c strb r4, [r3, #0] 801a248: b01d add sp, #116 @ 0x74 801a24a: e8bd 4010 ldmia.w sp!, {r4, lr} 801a24e: b003 add sp, #12 801a250: 4770 bx lr 801a252: bf00 nop 801a254: 2000011c .word 0x2000011c 801a258: ffff0208 .word 0xffff0208 0801a25c <__sread>: 801a25c: b510 push {r4, lr} 801a25e: 460c mov r4, r1 801a260: f9b1 100e ldrsh.w r1, [r1, #14] 801a264: f000 f8ca bl 801a3fc <_read_r> 801a268: 2800 cmp r0, #0 801a26a: bfab itete ge 801a26c: 6d63 ldrge r3, [r4, #84] @ 0x54 801a26e: 89a3 ldrhlt r3, [r4, #12] 801a270: 181b addge r3, r3, r0 801a272: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 801a276: bfac ite ge 801a278: 6563 strge r3, [r4, #84] @ 0x54 801a27a: 81a3 strhlt r3, [r4, #12] 801a27c: bd10 pop {r4, pc} 0801a27e <__swrite>: 801a27e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801a282: 461f mov r7, r3 801a284: 898b ldrh r3, [r1, #12] 801a286: 05db lsls r3, r3, #23 801a288: 4605 mov r5, r0 801a28a: 460c mov r4, r1 801a28c: 4616 mov r6, r2 801a28e: d505 bpl.n 801a29c <__swrite+0x1e> 801a290: f9b1 100e ldrsh.w r1, [r1, #14] 801a294: 2302 movs r3, #2 801a296: 2200 movs r2, #0 801a298: f000 f89e bl 801a3d8 <_lseek_r> 801a29c: 89a3 ldrh r3, [r4, #12] 801a29e: f9b4 100e ldrsh.w r1, [r4, #14] 801a2a2: f423 5380 bic.w r3, r3, #4096 @ 0x1000 801a2a6: 81a3 strh r3, [r4, #12] 801a2a8: 4632 mov r2, r6 801a2aa: 463b mov r3, r7 801a2ac: 4628 mov r0, r5 801a2ae: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801a2b2: f000 b8b5 b.w 801a420 <_write_r> 0801a2b6 <__sseek>: 801a2b6: b510 push {r4, lr} 801a2b8: 460c mov r4, r1 801a2ba: f9b1 100e ldrsh.w r1, [r1, #14] 801a2be: f000 f88b bl 801a3d8 <_lseek_r> 801a2c2: f9b4 300c ldrsh.w r3, [r4, #12] 801a2c6: 1c42 adds r2, r0, #1 801a2c8: bf0b itete eq 801a2ca: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 801a2ce: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 801a2d2: 81a3 strheq r3, [r4, #12] 801a2d4: 81a3 strhne r3, [r4, #12] 801a2d6: bf18 it ne 801a2d8: 6560 strne r0, [r4, #84] @ 0x54 801a2da: bd10 pop {r4, pc} 0801a2dc <__sclose>: 801a2dc: f9b1 100e ldrsh.w r1, [r1, #14] 801a2e0: f000 b80c b.w 801a2fc <_close_r> 0801a2e4 : 801a2e4: 4402 add r2, r0 801a2e6: 4603 mov r3, r0 801a2e8: 4293 cmp r3, r2 801a2ea: d100 bne.n 801a2ee 801a2ec: 4770 bx lr 801a2ee: f803 1b01 strb.w r1, [r3], #1 801a2f2: e7f9 b.n 801a2e8 0801a2f4 <_localeconv_r>: 801a2f4: 4800 ldr r0, [pc, #0] @ (801a2f8 <_localeconv_r+0x4>) 801a2f6: 4770 bx lr 801a2f8: 2000025c .word 0x2000025c 0801a2fc <_close_r>: 801a2fc: b538 push {r3, r4, r5, lr} 801a2fe: 4d06 ldr r5, [pc, #24] @ (801a318 <_close_r+0x1c>) 801a300: 2300 movs r3, #0 801a302: 4604 mov r4, r0 801a304: 4608 mov r0, r1 801a306: 602b str r3, [r5, #0] 801a308: f7ec f9f8 bl 80066fc <_close> 801a30c: 1c43 adds r3, r0, #1 801a30e: d102 bne.n 801a316 <_close_r+0x1a> 801a310: 682b ldr r3, [r5, #0] 801a312: b103 cbz r3, 801a316 <_close_r+0x1a> 801a314: 6023 str r3, [r4, #0] 801a316: bd38 pop {r3, r4, r5, pc} 801a318: 20013cd8 .word 0x20013cd8 0801a31c <_reclaim_reent>: 801a31c: 4b2d ldr r3, [pc, #180] @ (801a3d4 <_reclaim_reent+0xb8>) 801a31e: 681b ldr r3, [r3, #0] 801a320: 4283 cmp r3, r0 801a322: b570 push {r4, r5, r6, lr} 801a324: 4604 mov r4, r0 801a326: d053 beq.n 801a3d0 <_reclaim_reent+0xb4> 801a328: 69c3 ldr r3, [r0, #28] 801a32a: b31b cbz r3, 801a374 <_reclaim_reent+0x58> 801a32c: 68db ldr r3, [r3, #12] 801a32e: b163 cbz r3, 801a34a <_reclaim_reent+0x2e> 801a330: 2500 movs r5, #0 801a332: 69e3 ldr r3, [r4, #28] 801a334: 68db ldr r3, [r3, #12] 801a336: 5959 ldr r1, [r3, r5] 801a338: b9b1 cbnz r1, 801a368 <_reclaim_reent+0x4c> 801a33a: 3504 adds r5, #4 801a33c: 2d80 cmp r5, #128 @ 0x80 801a33e: d1f8 bne.n 801a332 <_reclaim_reent+0x16> 801a340: 69e3 ldr r3, [r4, #28] 801a342: 4620 mov r0, r4 801a344: 68d9 ldr r1, [r3, #12] 801a346: f000 ff23 bl 801b190 <_free_r> 801a34a: 69e3 ldr r3, [r4, #28] 801a34c: 6819 ldr r1, [r3, #0] 801a34e: b111 cbz r1, 801a356 <_reclaim_reent+0x3a> 801a350: 4620 mov r0, r4 801a352: f000 ff1d bl 801b190 <_free_r> 801a356: 69e3 ldr r3, [r4, #28] 801a358: 689d ldr r5, [r3, #8] 801a35a: b15d cbz r5, 801a374 <_reclaim_reent+0x58> 801a35c: 4629 mov r1, r5 801a35e: 4620 mov r0, r4 801a360: 682d ldr r5, [r5, #0] 801a362: f000 ff15 bl 801b190 <_free_r> 801a366: e7f8 b.n 801a35a <_reclaim_reent+0x3e> 801a368: 680e ldr r6, [r1, #0] 801a36a: 4620 mov r0, r4 801a36c: f000 ff10 bl 801b190 <_free_r> 801a370: 4631 mov r1, r6 801a372: e7e1 b.n 801a338 <_reclaim_reent+0x1c> 801a374: 6961 ldr r1, [r4, #20] 801a376: b111 cbz r1, 801a37e <_reclaim_reent+0x62> 801a378: 4620 mov r0, r4 801a37a: f000 ff09 bl 801b190 <_free_r> 801a37e: 69e1 ldr r1, [r4, #28] 801a380: b111 cbz r1, 801a388 <_reclaim_reent+0x6c> 801a382: 4620 mov r0, r4 801a384: f000 ff04 bl 801b190 <_free_r> 801a388: 6b21 ldr r1, [r4, #48] @ 0x30 801a38a: b111 cbz r1, 801a392 <_reclaim_reent+0x76> 801a38c: 4620 mov r0, r4 801a38e: f000 feff bl 801b190 <_free_r> 801a392: 6b61 ldr r1, [r4, #52] @ 0x34 801a394: b111 cbz r1, 801a39c <_reclaim_reent+0x80> 801a396: 4620 mov r0, r4 801a398: f000 fefa bl 801b190 <_free_r> 801a39c: 6ba1 ldr r1, [r4, #56] @ 0x38 801a39e: b111 cbz r1, 801a3a6 <_reclaim_reent+0x8a> 801a3a0: 4620 mov r0, r4 801a3a2: f000 fef5 bl 801b190 <_free_r> 801a3a6: 6ca1 ldr r1, [r4, #72] @ 0x48 801a3a8: b111 cbz r1, 801a3b0 <_reclaim_reent+0x94> 801a3aa: 4620 mov r0, r4 801a3ac: f000 fef0 bl 801b190 <_free_r> 801a3b0: 6c61 ldr r1, [r4, #68] @ 0x44 801a3b2: b111 cbz r1, 801a3ba <_reclaim_reent+0x9e> 801a3b4: 4620 mov r0, r4 801a3b6: f000 feeb bl 801b190 <_free_r> 801a3ba: 6ae1 ldr r1, [r4, #44] @ 0x2c 801a3bc: b111 cbz r1, 801a3c4 <_reclaim_reent+0xa8> 801a3be: 4620 mov r0, r4 801a3c0: f000 fee6 bl 801b190 <_free_r> 801a3c4: 6a23 ldr r3, [r4, #32] 801a3c6: b11b cbz r3, 801a3d0 <_reclaim_reent+0xb4> 801a3c8: 4620 mov r0, r4 801a3ca: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 801a3ce: 4718 bx r3 801a3d0: bd70 pop {r4, r5, r6, pc} 801a3d2: bf00 nop 801a3d4: 2000011c .word 0x2000011c 0801a3d8 <_lseek_r>: 801a3d8: b538 push {r3, r4, r5, lr} 801a3da: 4d07 ldr r5, [pc, #28] @ (801a3f8 <_lseek_r+0x20>) 801a3dc: 4604 mov r4, r0 801a3de: 4608 mov r0, r1 801a3e0: 4611 mov r1, r2 801a3e2: 2200 movs r2, #0 801a3e4: 602a str r2, [r5, #0] 801a3e6: 461a mov r2, r3 801a3e8: f7ec f9af bl 800674a <_lseek> 801a3ec: 1c43 adds r3, r0, #1 801a3ee: d102 bne.n 801a3f6 <_lseek_r+0x1e> 801a3f0: 682b ldr r3, [r5, #0] 801a3f2: b103 cbz r3, 801a3f6 <_lseek_r+0x1e> 801a3f4: 6023 str r3, [r4, #0] 801a3f6: bd38 pop {r3, r4, r5, pc} 801a3f8: 20013cd8 .word 0x20013cd8 0801a3fc <_read_r>: 801a3fc: b538 push {r3, r4, r5, lr} 801a3fe: 4d07 ldr r5, [pc, #28] @ (801a41c <_read_r+0x20>) 801a400: 4604 mov r4, r0 801a402: 4608 mov r0, r1 801a404: 4611 mov r1, r2 801a406: 2200 movs r2, #0 801a408: 602a str r2, [r5, #0] 801a40a: 461a mov r2, r3 801a40c: f7ec f959 bl 80066c2 <_read> 801a410: 1c43 adds r3, r0, #1 801a412: d102 bne.n 801a41a <_read_r+0x1e> 801a414: 682b ldr r3, [r5, #0] 801a416: b103 cbz r3, 801a41a <_read_r+0x1e> 801a418: 6023 str r3, [r4, #0] 801a41a: bd38 pop {r3, r4, r5, pc} 801a41c: 20013cd8 .word 0x20013cd8 0801a420 <_write_r>: 801a420: b538 push {r3, r4, r5, lr} 801a422: 4d07 ldr r5, [pc, #28] @ (801a440 <_write_r+0x20>) 801a424: 4604 mov r4, r0 801a426: 4608 mov r0, r1 801a428: 4611 mov r1, r2 801a42a: 2200 movs r2, #0 801a42c: 602a str r2, [r5, #0] 801a42e: 461a mov r2, r3 801a430: f7ea fa00 bl 8004834 <_write> 801a434: 1c43 adds r3, r0, #1 801a436: d102 bne.n 801a43e <_write_r+0x1e> 801a438: 682b ldr r3, [r5, #0] 801a43a: b103 cbz r3, 801a43e <_write_r+0x1e> 801a43c: 6023 str r3, [r4, #0] 801a43e: bd38 pop {r3, r4, r5, pc} 801a440: 20013cd8 .word 0x20013cd8 0801a444 <__errno>: 801a444: 4b01 ldr r3, [pc, #4] @ (801a44c <__errno+0x8>) 801a446: 6818 ldr r0, [r3, #0] 801a448: 4770 bx lr 801a44a: bf00 nop 801a44c: 2000011c .word 0x2000011c 0801a450 <__libc_init_array>: 801a450: b570 push {r4, r5, r6, lr} 801a452: 4b0d ldr r3, [pc, #52] @ (801a488 <__libc_init_array+0x38>) 801a454: 4d0d ldr r5, [pc, #52] @ (801a48c <__libc_init_array+0x3c>) 801a456: 1b5b subs r3, r3, r5 801a458: 109c asrs r4, r3, #2 801a45a: 2600 movs r6, #0 801a45c: 42a6 cmp r6, r4 801a45e: d109 bne.n 801a474 <__libc_init_array+0x24> 801a460: f003 fcae bl 801ddc0 <_init> 801a464: 4d0a ldr r5, [pc, #40] @ (801a490 <__libc_init_array+0x40>) 801a466: 4b0b ldr r3, [pc, #44] @ (801a494 <__libc_init_array+0x44>) 801a468: 1b5b subs r3, r3, r5 801a46a: 109c asrs r4, r3, #2 801a46c: 2600 movs r6, #0 801a46e: 42a6 cmp r6, r4 801a470: d105 bne.n 801a47e <__libc_init_array+0x2e> 801a472: bd70 pop {r4, r5, r6, pc} 801a474: f855 3b04 ldr.w r3, [r5], #4 801a478: 4798 blx r3 801a47a: 3601 adds r6, #1 801a47c: e7ee b.n 801a45c <__libc_init_array+0xc> 801a47e: f855 3b04 ldr.w r3, [r5], #4 801a482: 4798 blx r3 801a484: 3601 adds r6, #1 801a486: e7f2 b.n 801a46e <__libc_init_array+0x1e> 801a488: 0801ea38 .word 0x0801ea38 801a48c: 0801ea38 .word 0x0801ea38 801a490: 0801ea38 .word 0x0801ea38 801a494: 0801ea3c .word 0x0801ea3c 0801a498 <__retarget_lock_init_recursive>: 801a498: 4770 bx lr 0801a49a <__retarget_lock_acquire_recursive>: 801a49a: 4770 bx lr 0801a49c <__retarget_lock_release_recursive>: 801a49c: 4770 bx lr 0801a49e : 801a49e: 440a add r2, r1 801a4a0: 4291 cmp r1, r2 801a4a2: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 801a4a6: d100 bne.n 801a4aa 801a4a8: 4770 bx lr 801a4aa: b510 push {r4, lr} 801a4ac: f811 4b01 ldrb.w r4, [r1], #1 801a4b0: f803 4f01 strb.w r4, [r3, #1]! 801a4b4: 4291 cmp r1, r2 801a4b6: d1f9 bne.n 801a4ac 801a4b8: bd10 pop {r4, pc} ... 0801a4bc : 801a4bc: ed9f 0a01 vldr s0, [pc, #4] @ 801a4c4 801a4c0: 4770 bx lr 801a4c2: bf00 nop 801a4c4: 7fc00000 .word 0x7fc00000 0801a4c8 : 801a4c8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801a4cc: 6903 ldr r3, [r0, #16] 801a4ce: 690c ldr r4, [r1, #16] 801a4d0: 42a3 cmp r3, r4 801a4d2: 4607 mov r7, r0 801a4d4: db7e blt.n 801a5d4 801a4d6: 3c01 subs r4, #1 801a4d8: f101 0814 add.w r8, r1, #20 801a4dc: 00a3 lsls r3, r4, #2 801a4de: f100 0514 add.w r5, r0, #20 801a4e2: 9300 str r3, [sp, #0] 801a4e4: eb05 0384 add.w r3, r5, r4, lsl #2 801a4e8: 9301 str r3, [sp, #4] 801a4ea: f858 3024 ldr.w r3, [r8, r4, lsl #2] 801a4ee: f855 2024 ldr.w r2, [r5, r4, lsl #2] 801a4f2: 3301 adds r3, #1 801a4f4: 429a cmp r2, r3 801a4f6: eb08 0984 add.w r9, r8, r4, lsl #2 801a4fa: fbb2 f6f3 udiv r6, r2, r3 801a4fe: d32e bcc.n 801a55e 801a500: f04f 0a00 mov.w sl, #0 801a504: 46c4 mov ip, r8 801a506: 46ae mov lr, r5 801a508: 46d3 mov fp, sl 801a50a: f85c 3b04 ldr.w r3, [ip], #4 801a50e: b298 uxth r0, r3 801a510: fb06 a000 mla r0, r6, r0, sl 801a514: 0c02 lsrs r2, r0, #16 801a516: 0c1b lsrs r3, r3, #16 801a518: fb06 2303 mla r3, r6, r3, r2 801a51c: f8de 2000 ldr.w r2, [lr] 801a520: b280 uxth r0, r0 801a522: b292 uxth r2, r2 801a524: 1a12 subs r2, r2, r0 801a526: 445a add r2, fp 801a528: f8de 0000 ldr.w r0, [lr] 801a52c: ea4f 4a13 mov.w sl, r3, lsr #16 801a530: b29b uxth r3, r3 801a532: ebc3 4322 rsb r3, r3, r2, asr #16 801a536: eb03 4310 add.w r3, r3, r0, lsr #16 801a53a: b292 uxth r2, r2 801a53c: ea42 4203 orr.w r2, r2, r3, lsl #16 801a540: 45e1 cmp r9, ip 801a542: f84e 2b04 str.w r2, [lr], #4 801a546: ea4f 4b23 mov.w fp, r3, asr #16 801a54a: d2de bcs.n 801a50a 801a54c: 9b00 ldr r3, [sp, #0] 801a54e: 58eb ldr r3, [r5, r3] 801a550: b92b cbnz r3, 801a55e 801a552: 9b01 ldr r3, [sp, #4] 801a554: 3b04 subs r3, #4 801a556: 429d cmp r5, r3 801a558: 461a mov r2, r3 801a55a: d32f bcc.n 801a5bc 801a55c: 613c str r4, [r7, #16] 801a55e: 4638 mov r0, r7 801a560: f001 f9dc bl 801b91c <__mcmp> 801a564: 2800 cmp r0, #0 801a566: db25 blt.n 801a5b4 801a568: 4629 mov r1, r5 801a56a: 2000 movs r0, #0 801a56c: f858 2b04 ldr.w r2, [r8], #4 801a570: f8d1 c000 ldr.w ip, [r1] 801a574: fa1f fe82 uxth.w lr, r2 801a578: fa1f f38c uxth.w r3, ip 801a57c: eba3 030e sub.w r3, r3, lr 801a580: 4403 add r3, r0 801a582: 0c12 lsrs r2, r2, #16 801a584: ebc2 4223 rsb r2, r2, r3, asr #16 801a588: eb02 421c add.w r2, r2, ip, lsr #16 801a58c: b29b uxth r3, r3 801a58e: ea43 4302 orr.w r3, r3, r2, lsl #16 801a592: 45c1 cmp r9, r8 801a594: f841 3b04 str.w r3, [r1], #4 801a598: ea4f 4022 mov.w r0, r2, asr #16 801a59c: d2e6 bcs.n 801a56c 801a59e: f855 2024 ldr.w r2, [r5, r4, lsl #2] 801a5a2: eb05 0384 add.w r3, r5, r4, lsl #2 801a5a6: b922 cbnz r2, 801a5b2 801a5a8: 3b04 subs r3, #4 801a5aa: 429d cmp r5, r3 801a5ac: 461a mov r2, r3 801a5ae: d30b bcc.n 801a5c8 801a5b0: 613c str r4, [r7, #16] 801a5b2: 3601 adds r6, #1 801a5b4: 4630 mov r0, r6 801a5b6: b003 add sp, #12 801a5b8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801a5bc: 6812 ldr r2, [r2, #0] 801a5be: 3b04 subs r3, #4 801a5c0: 2a00 cmp r2, #0 801a5c2: d1cb bne.n 801a55c 801a5c4: 3c01 subs r4, #1 801a5c6: e7c6 b.n 801a556 801a5c8: 6812 ldr r2, [r2, #0] 801a5ca: 3b04 subs r3, #4 801a5cc: 2a00 cmp r2, #0 801a5ce: d1ef bne.n 801a5b0 801a5d0: 3c01 subs r4, #1 801a5d2: e7ea b.n 801a5aa 801a5d4: 2000 movs r0, #0 801a5d6: e7ee b.n 801a5b6 0801a5d8 <_dtoa_r>: 801a5d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801a5dc: b099 sub sp, #100 @ 0x64 801a5de: ed8d 0b0e vstr d0, [sp, #56] @ 0x38 801a5e2: 920c str r2, [sp, #48] @ 0x30 801a5e4: 69c2 ldr r2, [r0, #28] 801a5e6: 9c22 ldr r4, [sp, #136] @ 0x88 801a5e8: 910a str r1, [sp, #40] @ 0x28 801a5ea: ec57 6b10 vmov r6, r7, d0 801a5ee: 4681 mov r9, r0 801a5f0: 9313 str r3, [sp, #76] @ 0x4c 801a5f2: b982 cbnz r2, 801a616 <_dtoa_r+0x3e> 801a5f4: 2010 movs r0, #16 801a5f6: f000 fe15 bl 801b224 801a5fa: 4602 mov r2, r0 801a5fc: f8c9 001c str.w r0, [r9, #28] 801a600: b920 cbnz r0, 801a60c <_dtoa_r+0x34> 801a602: 4bab ldr r3, [pc, #684] @ (801a8b0 <_dtoa_r+0x2d8>) 801a604: 21ef movs r1, #239 @ 0xef 801a606: 48ab ldr r0, [pc, #684] @ (801a8b4 <_dtoa_r+0x2dc>) 801a608: f002 fe0e bl 801d228 <__assert_func> 801a60c: 2300 movs r3, #0 801a60e: e9c0 3301 strd r3, r3, [r0, #4] 801a612: 6003 str r3, [r0, #0] 801a614: 60c3 str r3, [r0, #12] 801a616: 6811 ldr r1, [r2, #0] 801a618: b159 cbz r1, 801a632 <_dtoa_r+0x5a> 801a61a: 6852 ldr r2, [r2, #4] 801a61c: 604a str r2, [r1, #4] 801a61e: 2301 movs r3, #1 801a620: 4093 lsls r3, r2 801a622: 608b str r3, [r1, #8] 801a624: 4648 mov r0, r9 801a626: f000 fef1 bl 801b40c <_Bfree> 801a62a: f8d9 301c ldr.w r3, [r9, #28] 801a62e: 2200 movs r2, #0 801a630: 601a str r2, [r3, #0] 801a632: f1b7 0800 subs.w r8, r7, #0 801a636: bfb5 itete lt 801a638: 2301 movlt r3, #1 801a63a: 2300 movge r3, #0 801a63c: 6023 strlt r3, [r4, #0] 801a63e: 6023 strge r3, [r4, #0] 801a640: 4b9d ldr r3, [pc, #628] @ (801a8b8 <_dtoa_r+0x2e0>) 801a642: bfbc itt lt 801a644: f028 4800 biclt.w r8, r8, #2147483648 @ 0x80000000 801a648: f8cd 803c strlt.w r8, [sp, #60] @ 0x3c 801a64c: ea33 0308 bics.w r3, r3, r8 801a650: d11a bne.n 801a688 <_dtoa_r+0xb0> 801a652: 9a13 ldr r2, [sp, #76] @ 0x4c 801a654: f3c8 0813 ubfx r8, r8, #0, #20 801a658: f242 730f movw r3, #9999 @ 0x270f 801a65c: ea58 0806 orrs.w r8, r8, r6 801a660: 6013 str r3, [r2, #0] 801a662: f000 8568 beq.w 801b136 <_dtoa_r+0xb5e> 801a666: 9b23 ldr r3, [sp, #140] @ 0x8c 801a668: b953 cbnz r3, 801a680 <_dtoa_r+0xa8> 801a66a: 4b94 ldr r3, [pc, #592] @ (801a8bc <_dtoa_r+0x2e4>) 801a66c: e021 b.n 801a6b2 <_dtoa_r+0xda> 801a66e: 4b94 ldr r3, [pc, #592] @ (801a8c0 <_dtoa_r+0x2e8>) 801a670: 9300 str r3, [sp, #0] 801a672: 3308 adds r3, #8 801a674: 9a23 ldr r2, [sp, #140] @ 0x8c 801a676: 6013 str r3, [r2, #0] 801a678: 9800 ldr r0, [sp, #0] 801a67a: b019 add sp, #100 @ 0x64 801a67c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801a680: 4b8e ldr r3, [pc, #568] @ (801a8bc <_dtoa_r+0x2e4>) 801a682: 9300 str r3, [sp, #0] 801a684: 3303 adds r3, #3 801a686: e7f5 b.n 801a674 <_dtoa_r+0x9c> 801a688: ed9d 7b0e vldr d7, [sp, #56] @ 0x38 801a68c: 2200 movs r2, #0 801a68e: ec51 0b17 vmov r0, r1, d7 801a692: 2300 movs r3, #0 801a694: ed8d 7b06 vstr d7, [sp, #24] 801a698: f7e6 f9ee bl 8000a78 <__aeabi_dcmpeq> 801a69c: 4682 mov sl, r0 801a69e: b150 cbz r0, 801a6b6 <_dtoa_r+0xde> 801a6a0: 9a13 ldr r2, [sp, #76] @ 0x4c 801a6a2: 2301 movs r3, #1 801a6a4: 6013 str r3, [r2, #0] 801a6a6: 9b23 ldr r3, [sp, #140] @ 0x8c 801a6a8: b113 cbz r3, 801a6b0 <_dtoa_r+0xd8> 801a6aa: 9a23 ldr r2, [sp, #140] @ 0x8c 801a6ac: 4b85 ldr r3, [pc, #532] @ (801a8c4 <_dtoa_r+0x2ec>) 801a6ae: 6013 str r3, [r2, #0] 801a6b0: 4b85 ldr r3, [pc, #532] @ (801a8c8 <_dtoa_r+0x2f0>) 801a6b2: 9300 str r3, [sp, #0] 801a6b4: e7e0 b.n 801a678 <_dtoa_r+0xa0> 801a6b6: ed9d 0b06 vldr d0, [sp, #24] 801a6ba: aa16 add r2, sp, #88 @ 0x58 801a6bc: a917 add r1, sp, #92 @ 0x5c 801a6be: 4648 mov r0, r9 801a6c0: f001 fa50 bl 801bb64 <__d2b> 801a6c4: ea5f 5418 movs.w r4, r8, lsr #20 801a6c8: 9d16 ldr r5, [sp, #88] @ 0x58 801a6ca: 9001 str r0, [sp, #4] 801a6cc: d079 beq.n 801a7c2 <_dtoa_r+0x1ea> 801a6ce: 9b07 ldr r3, [sp, #28] 801a6d0: f8cd a050 str.w sl, [sp, #80] @ 0x50 801a6d4: f3c3 0313 ubfx r3, r3, #0, #20 801a6d8: e9dd 0106 ldrd r0, r1, [sp, #24] 801a6dc: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000 801a6e0: f443 1340 orr.w r3, r3, #3145728 @ 0x300000 801a6e4: f2a4 34ff subw r4, r4, #1023 @ 0x3ff 801a6e8: 4619 mov r1, r3 801a6ea: 2200 movs r2, #0 801a6ec: 4b77 ldr r3, [pc, #476] @ (801a8cc <_dtoa_r+0x2f4>) 801a6ee: f7e5 fda3 bl 8000238 <__aeabi_dsub> 801a6f2: a369 add r3, pc, #420 @ (adr r3, 801a898 <_dtoa_r+0x2c0>) 801a6f4: e9d3 2300 ldrd r2, r3, [r3] 801a6f8: f7e5 ff56 bl 80005a8 <__aeabi_dmul> 801a6fc: a368 add r3, pc, #416 @ (adr r3, 801a8a0 <_dtoa_r+0x2c8>) 801a6fe: e9d3 2300 ldrd r2, r3, [r3] 801a702: f7e5 fd9b bl 800023c <__adddf3> 801a706: 4606 mov r6, r0 801a708: 4620 mov r0, r4 801a70a: 460f mov r7, r1 801a70c: f7e5 fee2 bl 80004d4 <__aeabi_i2d> 801a710: a365 add r3, pc, #404 @ (adr r3, 801a8a8 <_dtoa_r+0x2d0>) 801a712: e9d3 2300 ldrd r2, r3, [r3] 801a716: f7e5 ff47 bl 80005a8 <__aeabi_dmul> 801a71a: 4602 mov r2, r0 801a71c: 460b mov r3, r1 801a71e: 4630 mov r0, r6 801a720: 4639 mov r1, r7 801a722: f7e5 fd8b bl 800023c <__adddf3> 801a726: 4606 mov r6, r0 801a728: 460f mov r7, r1 801a72a: f7e6 f9ed bl 8000b08 <__aeabi_d2iz> 801a72e: 2200 movs r2, #0 801a730: 4680 mov r8, r0 801a732: 2300 movs r3, #0 801a734: 4630 mov r0, r6 801a736: 4639 mov r1, r7 801a738: f7e6 f9a8 bl 8000a8c <__aeabi_dcmplt> 801a73c: b148 cbz r0, 801a752 <_dtoa_r+0x17a> 801a73e: 4640 mov r0, r8 801a740: f7e5 fec8 bl 80004d4 <__aeabi_i2d> 801a744: 4632 mov r2, r6 801a746: 463b mov r3, r7 801a748: f7e6 f996 bl 8000a78 <__aeabi_dcmpeq> 801a74c: b908 cbnz r0, 801a752 <_dtoa_r+0x17a> 801a74e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 801a752: f1b8 0f16 cmp.w r8, #22 801a756: d851 bhi.n 801a7fc <_dtoa_r+0x224> 801a758: 4b5d ldr r3, [pc, #372] @ (801a8d0 <_dtoa_r+0x2f8>) 801a75a: eb03 03c8 add.w r3, r3, r8, lsl #3 801a75e: e9d3 2300 ldrd r2, r3, [r3] 801a762: e9dd 0106 ldrd r0, r1, [sp, #24] 801a766: f7e6 f991 bl 8000a8c <__aeabi_dcmplt> 801a76a: 2800 cmp r0, #0 801a76c: d048 beq.n 801a800 <_dtoa_r+0x228> 801a76e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 801a772: 2300 movs r3, #0 801a774: 9312 str r3, [sp, #72] @ 0x48 801a776: 1b2d subs r5, r5, r4 801a778: 1e6b subs r3, r5, #1 801a77a: 9308 str r3, [sp, #32] 801a77c: bf43 ittte mi 801a77e: 2300 movmi r3, #0 801a780: f1c5 0701 rsbmi r7, r5, #1 801a784: 9308 strmi r3, [sp, #32] 801a786: 2700 movpl r7, #0 801a788: f1b8 0f00 cmp.w r8, #0 801a78c: db3a blt.n 801a804 <_dtoa_r+0x22c> 801a78e: 9b08 ldr r3, [sp, #32] 801a790: f8cd 8034 str.w r8, [sp, #52] @ 0x34 801a794: 4443 add r3, r8 801a796: 9308 str r3, [sp, #32] 801a798: 2300 movs r3, #0 801a79a: 9309 str r3, [sp, #36] @ 0x24 801a79c: 9b0a ldr r3, [sp, #40] @ 0x28 801a79e: 2b09 cmp r3, #9 801a7a0: d862 bhi.n 801a868 <_dtoa_r+0x290> 801a7a2: 2b05 cmp r3, #5 801a7a4: bfc4 itt gt 801a7a6: 3b04 subgt r3, #4 801a7a8: 930a strgt r3, [sp, #40] @ 0x28 801a7aa: 9b0a ldr r3, [sp, #40] @ 0x28 801a7ac: f1a3 0302 sub.w r3, r3, #2 801a7b0: bfcc ite gt 801a7b2: 2400 movgt r4, #0 801a7b4: 2401 movle r4, #1 801a7b6: 2b03 cmp r3, #3 801a7b8: d862 bhi.n 801a880 <_dtoa_r+0x2a8> 801a7ba: e8df f003 tbb [pc, r3] 801a7be: 5351 .short 0x5351 801a7c0: 2b36 .short 0x2b36 801a7c2: 9c17 ldr r4, [sp, #92] @ 0x5c 801a7c4: 442c add r4, r5 801a7c6: f204 4332 addw r3, r4, #1074 @ 0x432 801a7ca: 2b20 cmp r3, #32 801a7cc: bfc1 itttt gt 801a7ce: f1c3 0340 rsbgt r3, r3, #64 @ 0x40 801a7d2: fa08 f803 lslgt.w r8, r8, r3 801a7d6: f204 4312 addwgt r3, r4, #1042 @ 0x412 801a7da: fa26 f303 lsrgt.w r3, r6, r3 801a7de: bfd6 itet le 801a7e0: f1c3 0320 rsble r3, r3, #32 801a7e4: ea48 0003 orrgt.w r0, r8, r3 801a7e8: fa06 f003 lslle.w r0, r6, r3 801a7ec: f7e5 fe62 bl 80004b4 <__aeabi_ui2d> 801a7f0: 2201 movs r2, #1 801a7f2: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000 801a7f6: 3c01 subs r4, #1 801a7f8: 9214 str r2, [sp, #80] @ 0x50 801a7fa: e775 b.n 801a6e8 <_dtoa_r+0x110> 801a7fc: 2301 movs r3, #1 801a7fe: e7b9 b.n 801a774 <_dtoa_r+0x19c> 801a800: 9012 str r0, [sp, #72] @ 0x48 801a802: e7b8 b.n 801a776 <_dtoa_r+0x19e> 801a804: f1c8 0300 rsb r3, r8, #0 801a808: 9309 str r3, [sp, #36] @ 0x24 801a80a: 2300 movs r3, #0 801a80c: eba7 0708 sub.w r7, r7, r8 801a810: 930d str r3, [sp, #52] @ 0x34 801a812: e7c3 b.n 801a79c <_dtoa_r+0x1c4> 801a814: 2301 movs r3, #1 801a816: 930b str r3, [sp, #44] @ 0x2c 801a818: 9b0c ldr r3, [sp, #48] @ 0x30 801a81a: 4443 add r3, r8 801a81c: 9305 str r3, [sp, #20] 801a81e: 3301 adds r3, #1 801a820: 2b01 cmp r3, #1 801a822: 9304 str r3, [sp, #16] 801a824: bfb8 it lt 801a826: 2301 movlt r3, #1 801a828: e006 b.n 801a838 <_dtoa_r+0x260> 801a82a: 2301 movs r3, #1 801a82c: 930b str r3, [sp, #44] @ 0x2c 801a82e: 9b0c ldr r3, [sp, #48] @ 0x30 801a830: 2b00 cmp r3, #0 801a832: dd28 ble.n 801a886 <_dtoa_r+0x2ae> 801a834: e9cd 3304 strd r3, r3, [sp, #16] 801a838: f8d9 001c ldr.w r0, [r9, #28] 801a83c: 2100 movs r1, #0 801a83e: 2204 movs r2, #4 801a840: f102 0514 add.w r5, r2, #20 801a844: 429d cmp r5, r3 801a846: d923 bls.n 801a890 <_dtoa_r+0x2b8> 801a848: 6041 str r1, [r0, #4] 801a84a: 4648 mov r0, r9 801a84c: f000 fda0 bl 801b390 <_Balloc> 801a850: 9000 str r0, [sp, #0] 801a852: 2800 cmp r0, #0 801a854: d140 bne.n 801a8d8 <_dtoa_r+0x300> 801a856: 4b1f ldr r3, [pc, #124] @ (801a8d4 <_dtoa_r+0x2fc>) 801a858: 4602 mov r2, r0 801a85a: f240 11af movw r1, #431 @ 0x1af 801a85e: e6d2 b.n 801a606 <_dtoa_r+0x2e> 801a860: 2300 movs r3, #0 801a862: e7e3 b.n 801a82c <_dtoa_r+0x254> 801a864: 2300 movs r3, #0 801a866: e7d6 b.n 801a816 <_dtoa_r+0x23e> 801a868: 2401 movs r4, #1 801a86a: 2300 movs r3, #0 801a86c: e9cd 340a strd r3, r4, [sp, #40] @ 0x28 801a870: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801a874: e9cd 3304 strd r3, r3, [sp, #16] 801a878: 2200 movs r2, #0 801a87a: 2312 movs r3, #18 801a87c: 920c str r2, [sp, #48] @ 0x30 801a87e: e7db b.n 801a838 <_dtoa_r+0x260> 801a880: 2301 movs r3, #1 801a882: 930b str r3, [sp, #44] @ 0x2c 801a884: e7f4 b.n 801a870 <_dtoa_r+0x298> 801a886: 2301 movs r3, #1 801a888: e9cd 3304 strd r3, r3, [sp, #16] 801a88c: 461a mov r2, r3 801a88e: e7f5 b.n 801a87c <_dtoa_r+0x2a4> 801a890: 3101 adds r1, #1 801a892: 0052 lsls r2, r2, #1 801a894: e7d4 b.n 801a840 <_dtoa_r+0x268> 801a896: bf00 nop 801a898: 636f4361 .word 0x636f4361 801a89c: 3fd287a7 .word 0x3fd287a7 801a8a0: 8b60c8b3 .word 0x8b60c8b3 801a8a4: 3fc68a28 .word 0x3fc68a28 801a8a8: 509f79fb .word 0x509f79fb 801a8ac: 3fd34413 .word 0x3fd34413 801a8b0: 0801e636 .word 0x0801e636 801a8b4: 0801e64d .word 0x0801e64d 801a8b8: 7ff00000 .word 0x7ff00000 801a8bc: 0801e632 .word 0x0801e632 801a8c0: 0801e629 .word 0x0801e629 801a8c4: 0801e601 .word 0x0801e601 801a8c8: 0801e600 .word 0x0801e600 801a8cc: 3ff80000 .word 0x3ff80000 801a8d0: 0801e800 .word 0x0801e800 801a8d4: 0801e6a5 .word 0x0801e6a5 801a8d8: f8d9 301c ldr.w r3, [r9, #28] 801a8dc: 9a00 ldr r2, [sp, #0] 801a8de: 601a str r2, [r3, #0] 801a8e0: 9b04 ldr r3, [sp, #16] 801a8e2: 2b0e cmp r3, #14 801a8e4: f200 80a1 bhi.w 801aa2a <_dtoa_r+0x452> 801a8e8: 2c00 cmp r4, #0 801a8ea: f000 809e beq.w 801aa2a <_dtoa_r+0x452> 801a8ee: f1b8 0f00 cmp.w r8, #0 801a8f2: dd36 ble.n 801a962 <_dtoa_r+0x38a> 801a8f4: 4b9e ldr r3, [pc, #632] @ (801ab70 <_dtoa_r+0x598>) 801a8f6: f008 020f and.w r2, r8, #15 801a8fa: eb03 03c2 add.w r3, r3, r2, lsl #3 801a8fe: f418 7f80 tst.w r8, #256 @ 0x100 801a902: e9d3 ab00 ldrd sl, fp, [r3] 801a906: ea4f 1528 mov.w r5, r8, asr #4 801a90a: d016 beq.n 801a93a <_dtoa_r+0x362> 801a90c: 4b99 ldr r3, [pc, #612] @ (801ab74 <_dtoa_r+0x59c>) 801a90e: e9dd 0106 ldrd r0, r1, [sp, #24] 801a912: e9d3 2308 ldrd r2, r3, [r3, #32] 801a916: f7e5 ff71 bl 80007fc <__aeabi_ddiv> 801a91a: e9cd 0102 strd r0, r1, [sp, #8] 801a91e: f005 050f and.w r5, r5, #15 801a922: 2403 movs r4, #3 801a924: 4e93 ldr r6, [pc, #588] @ (801ab74 <_dtoa_r+0x59c>) 801a926: b975 cbnz r5, 801a946 <_dtoa_r+0x36e> 801a928: e9dd 0102 ldrd r0, r1, [sp, #8] 801a92c: 4652 mov r2, sl 801a92e: 465b mov r3, fp 801a930: f7e5 ff64 bl 80007fc <__aeabi_ddiv> 801a934: 4682 mov sl, r0 801a936: 468b mov fp, r1 801a938: e02d b.n 801a996 <_dtoa_r+0x3be> 801a93a: ed9d 7b06 vldr d7, [sp, #24] 801a93e: 2402 movs r4, #2 801a940: ed8d 7b02 vstr d7, [sp, #8] 801a944: e7ee b.n 801a924 <_dtoa_r+0x34c> 801a946: 07e9 lsls r1, r5, #31 801a948: d508 bpl.n 801a95c <_dtoa_r+0x384> 801a94a: 4650 mov r0, sl 801a94c: 4659 mov r1, fp 801a94e: e9d6 2300 ldrd r2, r3, [r6] 801a952: f7e5 fe29 bl 80005a8 <__aeabi_dmul> 801a956: 3401 adds r4, #1 801a958: 4682 mov sl, r0 801a95a: 468b mov fp, r1 801a95c: 106d asrs r5, r5, #1 801a95e: 3608 adds r6, #8 801a960: e7e1 b.n 801a926 <_dtoa_r+0x34e> 801a962: f000 80ad beq.w 801aac0 <_dtoa_r+0x4e8> 801a966: f1c8 0500 rsb r5, r8, #0 801a96a: 4b81 ldr r3, [pc, #516] @ (801ab70 <_dtoa_r+0x598>) 801a96c: 4e81 ldr r6, [pc, #516] @ (801ab74 <_dtoa_r+0x59c>) 801a96e: f005 020f and.w r2, r5, #15 801a972: eb03 03c2 add.w r3, r3, r2, lsl #3 801a976: e9d3 2300 ldrd r2, r3, [r3] 801a97a: e9dd 0106 ldrd r0, r1, [sp, #24] 801a97e: f7e5 fe13 bl 80005a8 <__aeabi_dmul> 801a982: 112d asrs r5, r5, #4 801a984: 4682 mov sl, r0 801a986: 468b mov fp, r1 801a988: 2300 movs r3, #0 801a98a: 2402 movs r4, #2 801a98c: 2d00 cmp r5, #0 801a98e: f040 808c bne.w 801aaaa <_dtoa_r+0x4d2> 801a992: 2b00 cmp r3, #0 801a994: d1ce bne.n 801a934 <_dtoa_r+0x35c> 801a996: 9b12 ldr r3, [sp, #72] @ 0x48 801a998: 2b00 cmp r3, #0 801a99a: f000 8095 beq.w 801aac8 <_dtoa_r+0x4f0> 801a99e: 4b76 ldr r3, [pc, #472] @ (801ab78 <_dtoa_r+0x5a0>) 801a9a0: 2200 movs r2, #0 801a9a2: 4650 mov r0, sl 801a9a4: 4659 mov r1, fp 801a9a6: f7e6 f871 bl 8000a8c <__aeabi_dcmplt> 801a9aa: 2800 cmp r0, #0 801a9ac: f000 808c beq.w 801aac8 <_dtoa_r+0x4f0> 801a9b0: 9b04 ldr r3, [sp, #16] 801a9b2: 2b00 cmp r3, #0 801a9b4: f000 8088 beq.w 801aac8 <_dtoa_r+0x4f0> 801a9b8: 9b05 ldr r3, [sp, #20] 801a9ba: 2b00 cmp r3, #0 801a9bc: dd35 ble.n 801aa2a <_dtoa_r+0x452> 801a9be: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff 801a9c2: 9302 str r3, [sp, #8] 801a9c4: 4650 mov r0, sl 801a9c6: 4659 mov r1, fp 801a9c8: 4b6c ldr r3, [pc, #432] @ (801ab7c <_dtoa_r+0x5a4>) 801a9ca: 2200 movs r2, #0 801a9cc: f7e5 fdec bl 80005a8 <__aeabi_dmul> 801a9d0: 9e05 ldr r6, [sp, #20] 801a9d2: 4682 mov sl, r0 801a9d4: 468b mov fp, r1 801a9d6: 3401 adds r4, #1 801a9d8: 4620 mov r0, r4 801a9da: f7e5 fd7b bl 80004d4 <__aeabi_i2d> 801a9de: 4652 mov r2, sl 801a9e0: 465b mov r3, fp 801a9e2: f7e5 fde1 bl 80005a8 <__aeabi_dmul> 801a9e6: 4b66 ldr r3, [pc, #408] @ (801ab80 <_dtoa_r+0x5a8>) 801a9e8: 2200 movs r2, #0 801a9ea: f7e5 fc27 bl 800023c <__adddf3> 801a9ee: 4604 mov r4, r0 801a9f0: f1a1 7550 sub.w r5, r1, #54525952 @ 0x3400000 801a9f4: e9cd 4510 strd r4, r5, [sp, #64] @ 0x40 801a9f8: 2e00 cmp r6, #0 801a9fa: d169 bne.n 801aad0 <_dtoa_r+0x4f8> 801a9fc: 4b61 ldr r3, [pc, #388] @ (801ab84 <_dtoa_r+0x5ac>) 801a9fe: 2200 movs r2, #0 801aa00: 4650 mov r0, sl 801aa02: 4659 mov r1, fp 801aa04: f7e5 fc18 bl 8000238 <__aeabi_dsub> 801aa08: 4622 mov r2, r4 801aa0a: 462b mov r3, r5 801aa0c: 4682 mov sl, r0 801aa0e: 468b mov fp, r1 801aa10: f7e6 f85a bl 8000ac8 <__aeabi_dcmpgt> 801aa14: 2800 cmp r0, #0 801aa16: f040 8294 bne.w 801af42 <_dtoa_r+0x96a> 801aa1a: 4622 mov r2, r4 801aa1c: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 801aa20: 4650 mov r0, sl 801aa22: 4659 mov r1, fp 801aa24: f7e6 f832 bl 8000a8c <__aeabi_dcmplt> 801aa28: bb20 cbnz r0, 801aa74 <_dtoa_r+0x49c> 801aa2a: 9b17 ldr r3, [sp, #92] @ 0x5c 801aa2c: 2b00 cmp r3, #0 801aa2e: f2c0 8160 blt.w 801acf2 <_dtoa_r+0x71a> 801aa32: f1b8 0f0e cmp.w r8, #14 801aa36: f300 815c bgt.w 801acf2 <_dtoa_r+0x71a> 801aa3a: 4b4d ldr r3, [pc, #308] @ (801ab70 <_dtoa_r+0x598>) 801aa3c: eb03 03c8 add.w r3, r3, r8, lsl #3 801aa40: e9d3 ab00 ldrd sl, fp, [r3] 801aa44: 9b0c ldr r3, [sp, #48] @ 0x30 801aa46: 2b00 cmp r3, #0 801aa48: f280 80ee bge.w 801ac28 <_dtoa_r+0x650> 801aa4c: 9b04 ldr r3, [sp, #16] 801aa4e: 2b00 cmp r3, #0 801aa50: f300 80ea bgt.w 801ac28 <_dtoa_r+0x650> 801aa54: d10e bne.n 801aa74 <_dtoa_r+0x49c> 801aa56: 4b4b ldr r3, [pc, #300] @ (801ab84 <_dtoa_r+0x5ac>) 801aa58: 2200 movs r2, #0 801aa5a: 4650 mov r0, sl 801aa5c: 4659 mov r1, fp 801aa5e: f7e5 fda3 bl 80005a8 <__aeabi_dmul> 801aa62: 4602 mov r2, r0 801aa64: 460b mov r3, r1 801aa66: e9dd 0106 ldrd r0, r1, [sp, #24] 801aa6a: f7e6 f819 bl 8000aa0 <__aeabi_dcmple> 801aa6e: 2800 cmp r0, #0 801aa70: f000 826a beq.w 801af48 <_dtoa_r+0x970> 801aa74: 2500 movs r5, #0 801aa76: 462c mov r4, r5 801aa78: 9b0c ldr r3, [sp, #48] @ 0x30 801aa7a: 9e00 ldr r6, [sp, #0] 801aa7c: 43db mvns r3, r3 801aa7e: 9302 str r3, [sp, #8] 801aa80: 4627 mov r7, r4 801aa82: 2400 movs r4, #0 801aa84: 4629 mov r1, r5 801aa86: 4648 mov r0, r9 801aa88: f000 fcc0 bl 801b40c <_Bfree> 801aa8c: 2f00 cmp r7, #0 801aa8e: f000 80c1 beq.w 801ac14 <_dtoa_r+0x63c> 801aa92: b12c cbz r4, 801aaa0 <_dtoa_r+0x4c8> 801aa94: 42bc cmp r4, r7 801aa96: d003 beq.n 801aaa0 <_dtoa_r+0x4c8> 801aa98: 4621 mov r1, r4 801aa9a: 4648 mov r0, r9 801aa9c: f000 fcb6 bl 801b40c <_Bfree> 801aaa0: 4639 mov r1, r7 801aaa2: 4648 mov r0, r9 801aaa4: f000 fcb2 bl 801b40c <_Bfree> 801aaa8: e0b4 b.n 801ac14 <_dtoa_r+0x63c> 801aaaa: 07ea lsls r2, r5, #31 801aaac: d505 bpl.n 801aaba <_dtoa_r+0x4e2> 801aaae: e9d6 2300 ldrd r2, r3, [r6] 801aab2: f7e5 fd79 bl 80005a8 <__aeabi_dmul> 801aab6: 3401 adds r4, #1 801aab8: 2301 movs r3, #1 801aaba: 106d asrs r5, r5, #1 801aabc: 3608 adds r6, #8 801aabe: e765 b.n 801a98c <_dtoa_r+0x3b4> 801aac0: e9dd ab06 ldrd sl, fp, [sp, #24] 801aac4: 2402 movs r4, #2 801aac6: e766 b.n 801a996 <_dtoa_r+0x3be> 801aac8: 9e04 ldr r6, [sp, #16] 801aaca: f8cd 8008 str.w r8, [sp, #8] 801aace: e783 b.n 801a9d8 <_dtoa_r+0x400> 801aad0: 4b27 ldr r3, [pc, #156] @ (801ab70 <_dtoa_r+0x598>) 801aad2: eb03 03c6 add.w r3, r3, r6, lsl #3 801aad6: e953 0102 ldrd r0, r1, [r3, #-8] 801aada: 9b0b ldr r3, [sp, #44] @ 0x2c 801aadc: 2b00 cmp r3, #0 801aade: d055 beq.n 801ab8c <_dtoa_r+0x5b4> 801aae0: 4602 mov r2, r0 801aae2: 460b mov r3, r1 801aae4: 2000 movs r0, #0 801aae6: 4928 ldr r1, [pc, #160] @ (801ab88 <_dtoa_r+0x5b0>) 801aae8: f7e5 fe88 bl 80007fc <__aeabi_ddiv> 801aaec: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801aaf0: f7e5 fba2 bl 8000238 <__aeabi_dsub> 801aaf4: 9b00 ldr r3, [sp, #0] 801aaf6: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801aafa: 199d adds r5, r3, r6 801aafc: 461e mov r6, r3 801aafe: 4659 mov r1, fp 801ab00: 4650 mov r0, sl 801ab02: f7e6 f801 bl 8000b08 <__aeabi_d2iz> 801ab06: 4604 mov r4, r0 801ab08: f7e5 fce4 bl 80004d4 <__aeabi_i2d> 801ab0c: 4602 mov r2, r0 801ab0e: 460b mov r3, r1 801ab10: 4650 mov r0, sl 801ab12: 4659 mov r1, fp 801ab14: f7e5 fb90 bl 8000238 <__aeabi_dsub> 801ab18: 3430 adds r4, #48 @ 0x30 801ab1a: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801ab1e: f806 4b01 strb.w r4, [r6], #1 801ab22: 4682 mov sl, r0 801ab24: 468b mov fp, r1 801ab26: f7e5 ffb1 bl 8000a8c <__aeabi_dcmplt> 801ab2a: 2800 cmp r0, #0 801ab2c: d172 bne.n 801ac14 <_dtoa_r+0x63c> 801ab2e: 4652 mov r2, sl 801ab30: 465b mov r3, fp 801ab32: 4911 ldr r1, [pc, #68] @ (801ab78 <_dtoa_r+0x5a0>) 801ab34: 2000 movs r0, #0 801ab36: f7e5 fb7f bl 8000238 <__aeabi_dsub> 801ab3a: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801ab3e: f7e5 ffa5 bl 8000a8c <__aeabi_dcmplt> 801ab42: 2800 cmp r0, #0 801ab44: f040 80b6 bne.w 801acb4 <_dtoa_r+0x6dc> 801ab48: 42ae cmp r6, r5 801ab4a: f43f af6e beq.w 801aa2a <_dtoa_r+0x452> 801ab4e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 801ab52: 4b0a ldr r3, [pc, #40] @ (801ab7c <_dtoa_r+0x5a4>) 801ab54: 2200 movs r2, #0 801ab56: f7e5 fd27 bl 80005a8 <__aeabi_dmul> 801ab5a: 4b08 ldr r3, [pc, #32] @ (801ab7c <_dtoa_r+0x5a4>) 801ab5c: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801ab60: 2200 movs r2, #0 801ab62: 4650 mov r0, sl 801ab64: 4659 mov r1, fp 801ab66: f7e5 fd1f bl 80005a8 <__aeabi_dmul> 801ab6a: 4682 mov sl, r0 801ab6c: 468b mov fp, r1 801ab6e: e7c6 b.n 801aafe <_dtoa_r+0x526> 801ab70: 0801e800 .word 0x0801e800 801ab74: 0801e7d8 .word 0x0801e7d8 801ab78: 3ff00000 .word 0x3ff00000 801ab7c: 40240000 .word 0x40240000 801ab80: 401c0000 .word 0x401c0000 801ab84: 40140000 .word 0x40140000 801ab88: 3fe00000 .word 0x3fe00000 801ab8c: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801ab90: f7e5 fd0a bl 80005a8 <__aeabi_dmul> 801ab94: 9b00 ldr r3, [sp, #0] 801ab96: 9d00 ldr r5, [sp, #0] 801ab98: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 801ab9c: 4433 add r3, r6 801ab9e: 9315 str r3, [sp, #84] @ 0x54 801aba0: 4659 mov r1, fp 801aba2: 4650 mov r0, sl 801aba4: f7e5 ffb0 bl 8000b08 <__aeabi_d2iz> 801aba8: 4604 mov r4, r0 801abaa: f7e5 fc93 bl 80004d4 <__aeabi_i2d> 801abae: 3430 adds r4, #48 @ 0x30 801abb0: 460b mov r3, r1 801abb2: 4602 mov r2, r0 801abb4: 4659 mov r1, fp 801abb6: 4650 mov r0, sl 801abb8: f7e5 fb3e bl 8000238 <__aeabi_dsub> 801abbc: f805 4b01 strb.w r4, [r5], #1 801abc0: 9b15 ldr r3, [sp, #84] @ 0x54 801abc2: 429d cmp r5, r3 801abc4: 4682 mov sl, r0 801abc6: 468b mov fp, r1 801abc8: d127 bne.n 801ac1a <_dtoa_r+0x642> 801abca: 9b00 ldr r3, [sp, #0] 801abcc: 2200 movs r2, #0 801abce: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 801abd2: 441e add r6, r3 801abd4: 4bb3 ldr r3, [pc, #716] @ (801aea4 <_dtoa_r+0x8cc>) 801abd6: f7e5 fb31 bl 800023c <__adddf3> 801abda: 4602 mov r2, r0 801abdc: 460b mov r3, r1 801abde: 4650 mov r0, sl 801abe0: 4659 mov r1, fp 801abe2: f7e5 ff71 bl 8000ac8 <__aeabi_dcmpgt> 801abe6: 2800 cmp r0, #0 801abe8: d164 bne.n 801acb4 <_dtoa_r+0x6dc> 801abea: e9dd 2310 ldrd r2, r3, [sp, #64] @ 0x40 801abee: 49ad ldr r1, [pc, #692] @ (801aea4 <_dtoa_r+0x8cc>) 801abf0: 2000 movs r0, #0 801abf2: f7e5 fb21 bl 8000238 <__aeabi_dsub> 801abf6: 4602 mov r2, r0 801abf8: 460b mov r3, r1 801abfa: 4650 mov r0, sl 801abfc: 4659 mov r1, fp 801abfe: f7e5 ff45 bl 8000a8c <__aeabi_dcmplt> 801ac02: 2800 cmp r0, #0 801ac04: f43f af11 beq.w 801aa2a <_dtoa_r+0x452> 801ac08: 4633 mov r3, r6 801ac0a: f816 2d01 ldrb.w r2, [r6, #-1]! 801ac0e: 2a30 cmp r2, #48 @ 0x30 801ac10: d0fa beq.n 801ac08 <_dtoa_r+0x630> 801ac12: 461e mov r6, r3 801ac14: f8dd 8008 ldr.w r8, [sp, #8] 801ac18: e03a b.n 801ac90 <_dtoa_r+0x6b8> 801ac1a: 4ba3 ldr r3, [pc, #652] @ (801aea8 <_dtoa_r+0x8d0>) 801ac1c: 2200 movs r2, #0 801ac1e: f7e5 fcc3 bl 80005a8 <__aeabi_dmul> 801ac22: 4682 mov sl, r0 801ac24: 468b mov fp, r1 801ac26: e7bb b.n 801aba0 <_dtoa_r+0x5c8> 801ac28: 9e00 ldr r6, [sp, #0] 801ac2a: 4652 mov r2, sl 801ac2c: 465b mov r3, fp 801ac2e: e9dd 0106 ldrd r0, r1, [sp, #24] 801ac32: f7e5 fde3 bl 80007fc <__aeabi_ddiv> 801ac36: f7e5 ff67 bl 8000b08 <__aeabi_d2iz> 801ac3a: 4607 mov r7, r0 801ac3c: f7e5 fc4a bl 80004d4 <__aeabi_i2d> 801ac40: 4652 mov r2, sl 801ac42: 465b mov r3, fp 801ac44: f7e5 fcb0 bl 80005a8 <__aeabi_dmul> 801ac48: 4602 mov r2, r0 801ac4a: 460b mov r3, r1 801ac4c: e9dd 0106 ldrd r0, r1, [sp, #24] 801ac50: f7e5 faf2 bl 8000238 <__aeabi_dsub> 801ac54: f107 0c30 add.w ip, r7, #48 @ 0x30 801ac58: 9c00 ldr r4, [sp, #0] 801ac5a: f806 cb01 strb.w ip, [r6], #1 801ac5e: eba6 0c04 sub.w ip, r6, r4 801ac62: 9c04 ldr r4, [sp, #16] 801ac64: 4564 cmp r4, ip 801ac66: 4602 mov r2, r0 801ac68: 460b mov r3, r1 801ac6a: d133 bne.n 801acd4 <_dtoa_r+0x6fc> 801ac6c: f7e5 fae6 bl 800023c <__adddf3> 801ac70: 4652 mov r2, sl 801ac72: 465b mov r3, fp 801ac74: 4604 mov r4, r0 801ac76: 460d mov r5, r1 801ac78: f7e5 ff26 bl 8000ac8 <__aeabi_dcmpgt> 801ac7c: b9c0 cbnz r0, 801acb0 <_dtoa_r+0x6d8> 801ac7e: 4652 mov r2, sl 801ac80: 465b mov r3, fp 801ac82: 4620 mov r0, r4 801ac84: 4629 mov r1, r5 801ac86: f7e5 fef7 bl 8000a78 <__aeabi_dcmpeq> 801ac8a: b108 cbz r0, 801ac90 <_dtoa_r+0x6b8> 801ac8c: 07fb lsls r3, r7, #31 801ac8e: d40f bmi.n 801acb0 <_dtoa_r+0x6d8> 801ac90: 9901 ldr r1, [sp, #4] 801ac92: 4648 mov r0, r9 801ac94: f000 fbba bl 801b40c <_Bfree> 801ac98: 2300 movs r3, #0 801ac9a: 9a13 ldr r2, [sp, #76] @ 0x4c 801ac9c: 7033 strb r3, [r6, #0] 801ac9e: f108 0301 add.w r3, r8, #1 801aca2: 6013 str r3, [r2, #0] 801aca4: 9b23 ldr r3, [sp, #140] @ 0x8c 801aca6: 2b00 cmp r3, #0 801aca8: f43f ace6 beq.w 801a678 <_dtoa_r+0xa0> 801acac: 601e str r6, [r3, #0] 801acae: e4e3 b.n 801a678 <_dtoa_r+0xa0> 801acb0: f8cd 8008 str.w r8, [sp, #8] 801acb4: 4633 mov r3, r6 801acb6: 461e mov r6, r3 801acb8: f813 2d01 ldrb.w r2, [r3, #-1]! 801acbc: 2a39 cmp r2, #57 @ 0x39 801acbe: d106 bne.n 801acce <_dtoa_r+0x6f6> 801acc0: 9a00 ldr r2, [sp, #0] 801acc2: 429a cmp r2, r3 801acc4: d1f7 bne.n 801acb6 <_dtoa_r+0x6de> 801acc6: 9a02 ldr r2, [sp, #8] 801acc8: 3201 adds r2, #1 801acca: 9202 str r2, [sp, #8] 801accc: 2230 movs r2, #48 @ 0x30 801acce: 3201 adds r2, #1 801acd0: 701a strb r2, [r3, #0] 801acd2: e79f b.n 801ac14 <_dtoa_r+0x63c> 801acd4: 4b74 ldr r3, [pc, #464] @ (801aea8 <_dtoa_r+0x8d0>) 801acd6: 2200 movs r2, #0 801acd8: f7e5 fc66 bl 80005a8 <__aeabi_dmul> 801acdc: 4602 mov r2, r0 801acde: 460b mov r3, r1 801ace0: e9cd 2306 strd r2, r3, [sp, #24] 801ace4: 2200 movs r2, #0 801ace6: 2300 movs r3, #0 801ace8: f7e5 fec6 bl 8000a78 <__aeabi_dcmpeq> 801acec: 2800 cmp r0, #0 801acee: d09c beq.n 801ac2a <_dtoa_r+0x652> 801acf0: e7ce b.n 801ac90 <_dtoa_r+0x6b8> 801acf2: 9a0b ldr r2, [sp, #44] @ 0x2c 801acf4: 2a00 cmp r2, #0 801acf6: f000 80e3 beq.w 801aec0 <_dtoa_r+0x8e8> 801acfa: 9a0a ldr r2, [sp, #40] @ 0x28 801acfc: 2a01 cmp r2, #1 801acfe: f300 80c2 bgt.w 801ae86 <_dtoa_r+0x8ae> 801ad02: 9a14 ldr r2, [sp, #80] @ 0x50 801ad04: 2a00 cmp r2, #0 801ad06: f000 80ba beq.w 801ae7e <_dtoa_r+0x8a6> 801ad0a: f203 4333 addw r3, r3, #1075 @ 0x433 801ad0e: 9d09 ldr r5, [sp, #36] @ 0x24 801ad10: 463e mov r6, r7 801ad12: 9a08 ldr r2, [sp, #32] 801ad14: 2101 movs r1, #1 801ad16: 441a add r2, r3 801ad18: 4648 mov r0, r9 801ad1a: 441f add r7, r3 801ad1c: 9208 str r2, [sp, #32] 801ad1e: f000 fc73 bl 801b608 <__i2b> 801ad22: 4604 mov r4, r0 801ad24: b156 cbz r6, 801ad3c <_dtoa_r+0x764> 801ad26: 9b08 ldr r3, [sp, #32] 801ad28: 2b00 cmp r3, #0 801ad2a: dd07 ble.n 801ad3c <_dtoa_r+0x764> 801ad2c: 42b3 cmp r3, r6 801ad2e: 9a08 ldr r2, [sp, #32] 801ad30: bfa8 it ge 801ad32: 4633 movge r3, r6 801ad34: 1aff subs r7, r7, r3 801ad36: 1af6 subs r6, r6, r3 801ad38: 1ad3 subs r3, r2, r3 801ad3a: 9308 str r3, [sp, #32] 801ad3c: 9b09 ldr r3, [sp, #36] @ 0x24 801ad3e: b30b cbz r3, 801ad84 <_dtoa_r+0x7ac> 801ad40: 9b0b ldr r3, [sp, #44] @ 0x2c 801ad42: 2b00 cmp r3, #0 801ad44: f000 80c3 beq.w 801aece <_dtoa_r+0x8f6> 801ad48: 2d00 cmp r5, #0 801ad4a: f000 80bd beq.w 801aec8 <_dtoa_r+0x8f0> 801ad4e: 4621 mov r1, r4 801ad50: 462a mov r2, r5 801ad52: 4648 mov r0, r9 801ad54: f000 fd18 bl 801b788 <__pow5mult> 801ad58: 9a01 ldr r2, [sp, #4] 801ad5a: 4601 mov r1, r0 801ad5c: 4604 mov r4, r0 801ad5e: 4648 mov r0, r9 801ad60: f000 fc68 bl 801b634 <__multiply> 801ad64: 9901 ldr r1, [sp, #4] 801ad66: 4682 mov sl, r0 801ad68: 4648 mov r0, r9 801ad6a: f000 fb4f bl 801b40c <_Bfree> 801ad6e: 9b09 ldr r3, [sp, #36] @ 0x24 801ad70: 1b5b subs r3, r3, r5 801ad72: 9309 str r3, [sp, #36] @ 0x24 801ad74: f000 80ae beq.w 801aed4 <_dtoa_r+0x8fc> 801ad78: 9a09 ldr r2, [sp, #36] @ 0x24 801ad7a: 4651 mov r1, sl 801ad7c: 4648 mov r0, r9 801ad7e: f000 fd03 bl 801b788 <__pow5mult> 801ad82: 9001 str r0, [sp, #4] 801ad84: 2101 movs r1, #1 801ad86: 4648 mov r0, r9 801ad88: f000 fc3e bl 801b608 <__i2b> 801ad8c: 9b0d ldr r3, [sp, #52] @ 0x34 801ad8e: 4605 mov r5, r0 801ad90: 2b00 cmp r3, #0 801ad92: f000 81d7 beq.w 801b144 <_dtoa_r+0xb6c> 801ad96: 461a mov r2, r3 801ad98: 4601 mov r1, r0 801ad9a: 4648 mov r0, r9 801ad9c: f000 fcf4 bl 801b788 <__pow5mult> 801ada0: 9b0a ldr r3, [sp, #40] @ 0x28 801ada2: 2b01 cmp r3, #1 801ada4: 4605 mov r5, r0 801ada6: f300 809d bgt.w 801aee4 <_dtoa_r+0x90c> 801adaa: 9b0e ldr r3, [sp, #56] @ 0x38 801adac: 2b00 cmp r3, #0 801adae: f040 8094 bne.w 801aeda <_dtoa_r+0x902> 801adb2: 9b0f ldr r3, [sp, #60] @ 0x3c 801adb4: f3c3 0313 ubfx r3, r3, #0, #20 801adb8: 2b00 cmp r3, #0 801adba: f040 808e bne.w 801aeda <_dtoa_r+0x902> 801adbe: 9b0f ldr r3, [sp, #60] @ 0x3c 801adc0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 801adc4: 0d1b lsrs r3, r3, #20 801adc6: 051b lsls r3, r3, #20 801adc8: 2b00 cmp r3, #0 801adca: f000 8089 beq.w 801aee0 <_dtoa_r+0x908> 801adce: 9b08 ldr r3, [sp, #32] 801add0: 3301 adds r3, #1 801add2: 3701 adds r7, #1 801add4: 9308 str r3, [sp, #32] 801add6: f04f 0a01 mov.w sl, #1 801adda: 9b0d ldr r3, [sp, #52] @ 0x34 801addc: 2b00 cmp r3, #0 801adde: f000 81b7 beq.w 801b150 <_dtoa_r+0xb78> 801ade2: 692b ldr r3, [r5, #16] 801ade4: eb05 0383 add.w r3, r5, r3, lsl #2 801ade8: 6918 ldr r0, [r3, #16] 801adea: f000 fbc1 bl 801b570 <__hi0bits> 801adee: f1c0 0020 rsb r0, r0, #32 801adf2: 9b08 ldr r3, [sp, #32] 801adf4: 4418 add r0, r3 801adf6: f010 001f ands.w r0, r0, #31 801adfa: d07e beq.n 801aefa <_dtoa_r+0x922> 801adfc: f1c0 0320 rsb r3, r0, #32 801ae00: 2b04 cmp r3, #4 801ae02: dd72 ble.n 801aeea <_dtoa_r+0x912> 801ae04: 9b08 ldr r3, [sp, #32] 801ae06: f1c0 001c rsb r0, r0, #28 801ae0a: 4403 add r3, r0 801ae0c: 4407 add r7, r0 801ae0e: 4406 add r6, r0 801ae10: 9308 str r3, [sp, #32] 801ae12: 2f00 cmp r7, #0 801ae14: dd05 ble.n 801ae22 <_dtoa_r+0x84a> 801ae16: 9901 ldr r1, [sp, #4] 801ae18: 463a mov r2, r7 801ae1a: 4648 mov r0, r9 801ae1c: f000 fd10 bl 801b840 <__lshift> 801ae20: 9001 str r0, [sp, #4] 801ae22: 9b08 ldr r3, [sp, #32] 801ae24: 2b00 cmp r3, #0 801ae26: dd05 ble.n 801ae34 <_dtoa_r+0x85c> 801ae28: 4629 mov r1, r5 801ae2a: 461a mov r2, r3 801ae2c: 4648 mov r0, r9 801ae2e: f000 fd07 bl 801b840 <__lshift> 801ae32: 4605 mov r5, r0 801ae34: 9b12 ldr r3, [sp, #72] @ 0x48 801ae36: 2b00 cmp r3, #0 801ae38: d061 beq.n 801aefe <_dtoa_r+0x926> 801ae3a: 9801 ldr r0, [sp, #4] 801ae3c: 4629 mov r1, r5 801ae3e: f000 fd6d bl 801b91c <__mcmp> 801ae42: 2800 cmp r0, #0 801ae44: da5b bge.n 801aefe <_dtoa_r+0x926> 801ae46: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff 801ae4a: 9302 str r3, [sp, #8] 801ae4c: 9901 ldr r1, [sp, #4] 801ae4e: 2300 movs r3, #0 801ae50: 220a movs r2, #10 801ae52: 4648 mov r0, r9 801ae54: f000 fafc bl 801b450 <__multadd> 801ae58: 9b0b ldr r3, [sp, #44] @ 0x2c 801ae5a: 9001 str r0, [sp, #4] 801ae5c: 2b00 cmp r3, #0 801ae5e: f000 8179 beq.w 801b154 <_dtoa_r+0xb7c> 801ae62: 2300 movs r3, #0 801ae64: 4621 mov r1, r4 801ae66: 220a movs r2, #10 801ae68: 4648 mov r0, r9 801ae6a: f000 faf1 bl 801b450 <__multadd> 801ae6e: 9b05 ldr r3, [sp, #20] 801ae70: 2b00 cmp r3, #0 801ae72: 4604 mov r4, r0 801ae74: dc72 bgt.n 801af5c <_dtoa_r+0x984> 801ae76: 9b0a ldr r3, [sp, #40] @ 0x28 801ae78: 2b02 cmp r3, #2 801ae7a: dc49 bgt.n 801af10 <_dtoa_r+0x938> 801ae7c: e06e b.n 801af5c <_dtoa_r+0x984> 801ae7e: 9b16 ldr r3, [sp, #88] @ 0x58 801ae80: f1c3 0336 rsb r3, r3, #54 @ 0x36 801ae84: e743 b.n 801ad0e <_dtoa_r+0x736> 801ae86: 9b04 ldr r3, [sp, #16] 801ae88: 1e5d subs r5, r3, #1 801ae8a: 9b09 ldr r3, [sp, #36] @ 0x24 801ae8c: 42ab cmp r3, r5 801ae8e: db0d blt.n 801aeac <_dtoa_r+0x8d4> 801ae90: 1b5d subs r5, r3, r5 801ae92: 9b04 ldr r3, [sp, #16] 801ae94: 2b00 cmp r3, #0 801ae96: f6bf af3b bge.w 801ad10 <_dtoa_r+0x738> 801ae9a: 9b04 ldr r3, [sp, #16] 801ae9c: 1afe subs r6, r7, r3 801ae9e: 2300 movs r3, #0 801aea0: e737 b.n 801ad12 <_dtoa_r+0x73a> 801aea2: bf00 nop 801aea4: 3fe00000 .word 0x3fe00000 801aea8: 40240000 .word 0x40240000 801aeac: 9b09 ldr r3, [sp, #36] @ 0x24 801aeae: 9a0d ldr r2, [sp, #52] @ 0x34 801aeb0: 9509 str r5, [sp, #36] @ 0x24 801aeb2: 1aeb subs r3, r5, r3 801aeb4: 441a add r2, r3 801aeb6: 920d str r2, [sp, #52] @ 0x34 801aeb8: 9b04 ldr r3, [sp, #16] 801aeba: 463e mov r6, r7 801aebc: 2500 movs r5, #0 801aebe: e728 b.n 801ad12 <_dtoa_r+0x73a> 801aec0: 9d09 ldr r5, [sp, #36] @ 0x24 801aec2: 9c0b ldr r4, [sp, #44] @ 0x2c 801aec4: 463e mov r6, r7 801aec6: e72d b.n 801ad24 <_dtoa_r+0x74c> 801aec8: f8dd a004 ldr.w sl, [sp, #4] 801aecc: e754 b.n 801ad78 <_dtoa_r+0x7a0> 801aece: 9a09 ldr r2, [sp, #36] @ 0x24 801aed0: 9901 ldr r1, [sp, #4] 801aed2: e753 b.n 801ad7c <_dtoa_r+0x7a4> 801aed4: f8cd a004 str.w sl, [sp, #4] 801aed8: e754 b.n 801ad84 <_dtoa_r+0x7ac> 801aeda: f04f 0a00 mov.w sl, #0 801aede: e77c b.n 801adda <_dtoa_r+0x802> 801aee0: 469a mov sl, r3 801aee2: e77a b.n 801adda <_dtoa_r+0x802> 801aee4: f04f 0a00 mov.w sl, #0 801aee8: e77b b.n 801ade2 <_dtoa_r+0x80a> 801aeea: d092 beq.n 801ae12 <_dtoa_r+0x83a> 801aeec: 9a08 ldr r2, [sp, #32] 801aeee: 331c adds r3, #28 801aef0: 441a add r2, r3 801aef2: 441f add r7, r3 801aef4: 441e add r6, r3 801aef6: 9208 str r2, [sp, #32] 801aef8: e78b b.n 801ae12 <_dtoa_r+0x83a> 801aefa: 4603 mov r3, r0 801aefc: e7f6 b.n 801aeec <_dtoa_r+0x914> 801aefe: 9b04 ldr r3, [sp, #16] 801af00: f8cd 8008 str.w r8, [sp, #8] 801af04: 2b00 cmp r3, #0 801af06: dc23 bgt.n 801af50 <_dtoa_r+0x978> 801af08: 9305 str r3, [sp, #20] 801af0a: 9b0a ldr r3, [sp, #40] @ 0x28 801af0c: 2b02 cmp r3, #2 801af0e: dd21 ble.n 801af54 <_dtoa_r+0x97c> 801af10: 9b05 ldr r3, [sp, #20] 801af12: 2b00 cmp r3, #0 801af14: f47f adb0 bne.w 801aa78 <_dtoa_r+0x4a0> 801af18: 4629 mov r1, r5 801af1a: 2205 movs r2, #5 801af1c: 4648 mov r0, r9 801af1e: f000 fa97 bl 801b450 <__multadd> 801af22: 4601 mov r1, r0 801af24: 4605 mov r5, r0 801af26: 9801 ldr r0, [sp, #4] 801af28: f000 fcf8 bl 801b91c <__mcmp> 801af2c: 2800 cmp r0, #0 801af2e: f77f ada3 ble.w 801aa78 <_dtoa_r+0x4a0> 801af32: 9e00 ldr r6, [sp, #0] 801af34: 2331 movs r3, #49 @ 0x31 801af36: f806 3b01 strb.w r3, [r6], #1 801af3a: 9b02 ldr r3, [sp, #8] 801af3c: 3301 adds r3, #1 801af3e: 9302 str r3, [sp, #8] 801af40: e59e b.n 801aa80 <_dtoa_r+0x4a8> 801af42: 4635 mov r5, r6 801af44: 462c mov r4, r5 801af46: e7f4 b.n 801af32 <_dtoa_r+0x95a> 801af48: 9d04 ldr r5, [sp, #16] 801af4a: f8cd 8008 str.w r8, [sp, #8] 801af4e: e7f9 b.n 801af44 <_dtoa_r+0x96c> 801af50: 9b04 ldr r3, [sp, #16] 801af52: 9305 str r3, [sp, #20] 801af54: 9b0b ldr r3, [sp, #44] @ 0x2c 801af56: 2b00 cmp r3, #0 801af58: f000 8100 beq.w 801b15c <_dtoa_r+0xb84> 801af5c: 2e00 cmp r6, #0 801af5e: dd05 ble.n 801af6c <_dtoa_r+0x994> 801af60: 4621 mov r1, r4 801af62: 4632 mov r2, r6 801af64: 4648 mov r0, r9 801af66: f000 fc6b bl 801b840 <__lshift> 801af6a: 4604 mov r4, r0 801af6c: f1ba 0f00 cmp.w sl, #0 801af70: d05a beq.n 801b028 <_dtoa_r+0xa50> 801af72: 6861 ldr r1, [r4, #4] 801af74: 4648 mov r0, r9 801af76: f000 fa0b bl 801b390 <_Balloc> 801af7a: 4606 mov r6, r0 801af7c: b928 cbnz r0, 801af8a <_dtoa_r+0x9b2> 801af7e: 4b82 ldr r3, [pc, #520] @ (801b188 <_dtoa_r+0xbb0>) 801af80: 4602 mov r2, r0 801af82: f240 21ef movw r1, #751 @ 0x2ef 801af86: f7ff bb3e b.w 801a606 <_dtoa_r+0x2e> 801af8a: 6922 ldr r2, [r4, #16] 801af8c: 3202 adds r2, #2 801af8e: 0092 lsls r2, r2, #2 801af90: f104 010c add.w r1, r4, #12 801af94: 300c adds r0, #12 801af96: f7ff fa82 bl 801a49e 801af9a: 2201 movs r2, #1 801af9c: 4631 mov r1, r6 801af9e: 4648 mov r0, r9 801afa0: f000 fc4e bl 801b840 <__lshift> 801afa4: 4607 mov r7, r0 801afa6: 9b00 ldr r3, [sp, #0] 801afa8: 9a00 ldr r2, [sp, #0] 801afaa: f103 0b01 add.w fp, r3, #1 801afae: 9b05 ldr r3, [sp, #20] 801afb0: 4413 add r3, r2 801afb2: 9306 str r3, [sp, #24] 801afb4: 9b0e ldr r3, [sp, #56] @ 0x38 801afb6: f003 0301 and.w r3, r3, #1 801afba: 9308 str r3, [sp, #32] 801afbc: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff 801afc0: 4629 mov r1, r5 801afc2: 9801 ldr r0, [sp, #4] 801afc4: 9304 str r3, [sp, #16] 801afc6: f7ff fa7f bl 801a4c8 801afca: 4621 mov r1, r4 801afcc: 9005 str r0, [sp, #20] 801afce: f100 0a30 add.w sl, r0, #48 @ 0x30 801afd2: 9801 ldr r0, [sp, #4] 801afd4: f000 fca2 bl 801b91c <__mcmp> 801afd8: 463a mov r2, r7 801afda: 4680 mov r8, r0 801afdc: 4629 mov r1, r5 801afde: 4648 mov r0, r9 801afe0: f000 fcb8 bl 801b954 <__mdiff> 801afe4: 68c2 ldr r2, [r0, #12] 801afe6: 4606 mov r6, r0 801afe8: bb02 cbnz r2, 801b02c <_dtoa_r+0xa54> 801afea: 4601 mov r1, r0 801afec: 9801 ldr r0, [sp, #4] 801afee: f000 fc95 bl 801b91c <__mcmp> 801aff2: 4602 mov r2, r0 801aff4: 4631 mov r1, r6 801aff6: 4648 mov r0, r9 801aff8: 9209 str r2, [sp, #36] @ 0x24 801affa: f000 fa07 bl 801b40c <_Bfree> 801affe: e9dd 2309 ldrd r2, r3, [sp, #36] @ 0x24 801b002: ea42 0103 orr.w r1, r2, r3 801b006: 9b08 ldr r3, [sp, #32] 801b008: 4319 orrs r1, r3 801b00a: 465e mov r6, fp 801b00c: d110 bne.n 801b030 <_dtoa_r+0xa58> 801b00e: f1ba 0f39 cmp.w sl, #57 @ 0x39 801b012: d02b beq.n 801b06c <_dtoa_r+0xa94> 801b014: f1b8 0f00 cmp.w r8, #0 801b018: dd02 ble.n 801b020 <_dtoa_r+0xa48> 801b01a: 9b05 ldr r3, [sp, #20] 801b01c: f103 0a31 add.w sl, r3, #49 @ 0x31 801b020: 9b04 ldr r3, [sp, #16] 801b022: f883 a000 strb.w sl, [r3] 801b026: e52d b.n 801aa84 <_dtoa_r+0x4ac> 801b028: 4627 mov r7, r4 801b02a: e7bc b.n 801afa6 <_dtoa_r+0x9ce> 801b02c: 2201 movs r2, #1 801b02e: e7e1 b.n 801aff4 <_dtoa_r+0xa1c> 801b030: f1b8 0f00 cmp.w r8, #0 801b034: db06 blt.n 801b044 <_dtoa_r+0xa6c> 801b036: 9b0a ldr r3, [sp, #40] @ 0x28 801b038: ea48 0803 orr.w r8, r8, r3 801b03c: 9b08 ldr r3, [sp, #32] 801b03e: ea58 0803 orrs.w r8, r8, r3 801b042: d120 bne.n 801b086 <_dtoa_r+0xaae> 801b044: 2a00 cmp r2, #0 801b046: ddeb ble.n 801b020 <_dtoa_r+0xa48> 801b048: 9901 ldr r1, [sp, #4] 801b04a: 2201 movs r2, #1 801b04c: 4648 mov r0, r9 801b04e: f000 fbf7 bl 801b840 <__lshift> 801b052: 4629 mov r1, r5 801b054: 9001 str r0, [sp, #4] 801b056: f000 fc61 bl 801b91c <__mcmp> 801b05a: 2800 cmp r0, #0 801b05c: dc03 bgt.n 801b066 <_dtoa_r+0xa8e> 801b05e: d1df bne.n 801b020 <_dtoa_r+0xa48> 801b060: f01a 0f01 tst.w sl, #1 801b064: d0dc beq.n 801b020 <_dtoa_r+0xa48> 801b066: f1ba 0f39 cmp.w sl, #57 @ 0x39 801b06a: d1d6 bne.n 801b01a <_dtoa_r+0xa42> 801b06c: 9a04 ldr r2, [sp, #16] 801b06e: 2339 movs r3, #57 @ 0x39 801b070: 7013 strb r3, [r2, #0] 801b072: 4633 mov r3, r6 801b074: 461e mov r6, r3 801b076: 3b01 subs r3, #1 801b078: f816 2c01 ldrb.w r2, [r6, #-1] 801b07c: 2a39 cmp r2, #57 @ 0x39 801b07e: d052 beq.n 801b126 <_dtoa_r+0xb4e> 801b080: 3201 adds r2, #1 801b082: 701a strb r2, [r3, #0] 801b084: e4fe b.n 801aa84 <_dtoa_r+0x4ac> 801b086: 2a00 cmp r2, #0 801b088: dd07 ble.n 801b09a <_dtoa_r+0xac2> 801b08a: f1ba 0f39 cmp.w sl, #57 @ 0x39 801b08e: d0ed beq.n 801b06c <_dtoa_r+0xa94> 801b090: 9a04 ldr r2, [sp, #16] 801b092: f10a 0301 add.w r3, sl, #1 801b096: 7013 strb r3, [r2, #0] 801b098: e4f4 b.n 801aa84 <_dtoa_r+0x4ac> 801b09a: 9b06 ldr r3, [sp, #24] 801b09c: f80b ac01 strb.w sl, [fp, #-1] 801b0a0: 455b cmp r3, fp 801b0a2: d02a beq.n 801b0fa <_dtoa_r+0xb22> 801b0a4: 9901 ldr r1, [sp, #4] 801b0a6: 2300 movs r3, #0 801b0a8: 220a movs r2, #10 801b0aa: 4648 mov r0, r9 801b0ac: f000 f9d0 bl 801b450 <__multadd> 801b0b0: 42bc cmp r4, r7 801b0b2: 9001 str r0, [sp, #4] 801b0b4: f04f 0300 mov.w r3, #0 801b0b8: f04f 020a mov.w r2, #10 801b0bc: 4621 mov r1, r4 801b0be: 4648 mov r0, r9 801b0c0: d106 bne.n 801b0d0 <_dtoa_r+0xaf8> 801b0c2: f000 f9c5 bl 801b450 <__multadd> 801b0c6: 4604 mov r4, r0 801b0c8: 4607 mov r7, r0 801b0ca: f10b 0b01 add.w fp, fp, #1 801b0ce: e775 b.n 801afbc <_dtoa_r+0x9e4> 801b0d0: f000 f9be bl 801b450 <__multadd> 801b0d4: 4639 mov r1, r7 801b0d6: 4604 mov r4, r0 801b0d8: 2300 movs r3, #0 801b0da: 220a movs r2, #10 801b0dc: 4648 mov r0, r9 801b0de: f000 f9b7 bl 801b450 <__multadd> 801b0e2: 4607 mov r7, r0 801b0e4: e7f1 b.n 801b0ca <_dtoa_r+0xaf2> 801b0e6: 9b05 ldr r3, [sp, #20] 801b0e8: 1e5e subs r6, r3, #1 801b0ea: 2b00 cmp r3, #0 801b0ec: 9b00 ldr r3, [sp, #0] 801b0ee: bfd8 it le 801b0f0: 2600 movle r6, #0 801b0f2: 1c5a adds r2, r3, #1 801b0f4: 4627 mov r7, r4 801b0f6: 4416 add r6, r2 801b0f8: 2400 movs r4, #0 801b0fa: 9901 ldr r1, [sp, #4] 801b0fc: 2201 movs r2, #1 801b0fe: 4648 mov r0, r9 801b100: f000 fb9e bl 801b840 <__lshift> 801b104: 4629 mov r1, r5 801b106: 9001 str r0, [sp, #4] 801b108: f000 fc08 bl 801b91c <__mcmp> 801b10c: 2800 cmp r0, #0 801b10e: dcb0 bgt.n 801b072 <_dtoa_r+0xa9a> 801b110: d102 bne.n 801b118 <_dtoa_r+0xb40> 801b112: f01a 0f01 tst.w sl, #1 801b116: d1ac bne.n 801b072 <_dtoa_r+0xa9a> 801b118: 4633 mov r3, r6 801b11a: 461e mov r6, r3 801b11c: f813 2d01 ldrb.w r2, [r3, #-1]! 801b120: 2a30 cmp r2, #48 @ 0x30 801b122: d0fa beq.n 801b11a <_dtoa_r+0xb42> 801b124: e4ae b.n 801aa84 <_dtoa_r+0x4ac> 801b126: 9a00 ldr r2, [sp, #0] 801b128: 429a cmp r2, r3 801b12a: d1a3 bne.n 801b074 <_dtoa_r+0xa9c> 801b12c: 9b02 ldr r3, [sp, #8] 801b12e: 3301 adds r3, #1 801b130: 9302 str r3, [sp, #8] 801b132: 2331 movs r3, #49 @ 0x31 801b134: e7af b.n 801b096 <_dtoa_r+0xabe> 801b136: 9b23 ldr r3, [sp, #140] @ 0x8c 801b138: 2b00 cmp r3, #0 801b13a: f47f aa98 bne.w 801a66e <_dtoa_r+0x96> 801b13e: 4b13 ldr r3, [pc, #76] @ (801b18c <_dtoa_r+0xbb4>) 801b140: f7ff bab7 b.w 801a6b2 <_dtoa_r+0xda> 801b144: 9b0a ldr r3, [sp, #40] @ 0x28 801b146: 2b01 cmp r3, #1 801b148: f77f ae2f ble.w 801adaa <_dtoa_r+0x7d2> 801b14c: f8dd a034 ldr.w sl, [sp, #52] @ 0x34 801b150: 2001 movs r0, #1 801b152: e64e b.n 801adf2 <_dtoa_r+0x81a> 801b154: 9b05 ldr r3, [sp, #20] 801b156: 2b00 cmp r3, #0 801b158: f77f aed7 ble.w 801af0a <_dtoa_r+0x932> 801b15c: 9e00 ldr r6, [sp, #0] 801b15e: 9801 ldr r0, [sp, #4] 801b160: 4629 mov r1, r5 801b162: f7ff f9b1 bl 801a4c8 801b166: f100 0a30 add.w sl, r0, #48 @ 0x30 801b16a: 9b00 ldr r3, [sp, #0] 801b16c: f806 ab01 strb.w sl, [r6], #1 801b170: 1af2 subs r2, r6, r3 801b172: 9b05 ldr r3, [sp, #20] 801b174: 4293 cmp r3, r2 801b176: ddb6 ble.n 801b0e6 <_dtoa_r+0xb0e> 801b178: 9901 ldr r1, [sp, #4] 801b17a: 2300 movs r3, #0 801b17c: 220a movs r2, #10 801b17e: 4648 mov r0, r9 801b180: f000 f966 bl 801b450 <__multadd> 801b184: 9001 str r0, [sp, #4] 801b186: e7ea b.n 801b15e <_dtoa_r+0xb86> 801b188: 0801e6a5 .word 0x0801e6a5 801b18c: 0801e629 .word 0x0801e629 0801b190 <_free_r>: 801b190: b538 push {r3, r4, r5, lr} 801b192: 4605 mov r5, r0 801b194: 2900 cmp r1, #0 801b196: d041 beq.n 801b21c <_free_r+0x8c> 801b198: f851 3c04 ldr.w r3, [r1, #-4] 801b19c: 1f0c subs r4, r1, #4 801b19e: 2b00 cmp r3, #0 801b1a0: bfb8 it lt 801b1a2: 18e4 addlt r4, r4, r3 801b1a4: f000 f8e8 bl 801b378 <__malloc_lock> 801b1a8: 4a1d ldr r2, [pc, #116] @ (801b220 <_free_r+0x90>) 801b1aa: 6813 ldr r3, [r2, #0] 801b1ac: b933 cbnz r3, 801b1bc <_free_r+0x2c> 801b1ae: 6063 str r3, [r4, #4] 801b1b0: 6014 str r4, [r2, #0] 801b1b2: 4628 mov r0, r5 801b1b4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 801b1b8: f000 b8e4 b.w 801b384 <__malloc_unlock> 801b1bc: 42a3 cmp r3, r4 801b1be: d908 bls.n 801b1d2 <_free_r+0x42> 801b1c0: 6820 ldr r0, [r4, #0] 801b1c2: 1821 adds r1, r4, r0 801b1c4: 428b cmp r3, r1 801b1c6: bf01 itttt eq 801b1c8: 6819 ldreq r1, [r3, #0] 801b1ca: 685b ldreq r3, [r3, #4] 801b1cc: 1809 addeq r1, r1, r0 801b1ce: 6021 streq r1, [r4, #0] 801b1d0: e7ed b.n 801b1ae <_free_r+0x1e> 801b1d2: 461a mov r2, r3 801b1d4: 685b ldr r3, [r3, #4] 801b1d6: b10b cbz r3, 801b1dc <_free_r+0x4c> 801b1d8: 42a3 cmp r3, r4 801b1da: d9fa bls.n 801b1d2 <_free_r+0x42> 801b1dc: 6811 ldr r1, [r2, #0] 801b1de: 1850 adds r0, r2, r1 801b1e0: 42a0 cmp r0, r4 801b1e2: d10b bne.n 801b1fc <_free_r+0x6c> 801b1e4: 6820 ldr r0, [r4, #0] 801b1e6: 4401 add r1, r0 801b1e8: 1850 adds r0, r2, r1 801b1ea: 4283 cmp r3, r0 801b1ec: 6011 str r1, [r2, #0] 801b1ee: d1e0 bne.n 801b1b2 <_free_r+0x22> 801b1f0: 6818 ldr r0, [r3, #0] 801b1f2: 685b ldr r3, [r3, #4] 801b1f4: 6053 str r3, [r2, #4] 801b1f6: 4408 add r0, r1 801b1f8: 6010 str r0, [r2, #0] 801b1fa: e7da b.n 801b1b2 <_free_r+0x22> 801b1fc: d902 bls.n 801b204 <_free_r+0x74> 801b1fe: 230c movs r3, #12 801b200: 602b str r3, [r5, #0] 801b202: e7d6 b.n 801b1b2 <_free_r+0x22> 801b204: 6820 ldr r0, [r4, #0] 801b206: 1821 adds r1, r4, r0 801b208: 428b cmp r3, r1 801b20a: bf04 itt eq 801b20c: 6819 ldreq r1, [r3, #0] 801b20e: 685b ldreq r3, [r3, #4] 801b210: 6063 str r3, [r4, #4] 801b212: bf04 itt eq 801b214: 1809 addeq r1, r1, r0 801b216: 6021 streq r1, [r4, #0] 801b218: 6054 str r4, [r2, #4] 801b21a: e7ca b.n 801b1b2 <_free_r+0x22> 801b21c: bd38 pop {r3, r4, r5, pc} 801b21e: bf00 nop 801b220: 20013ce4 .word 0x20013ce4 0801b224 : 801b224: 4b02 ldr r3, [pc, #8] @ (801b230 ) 801b226: 4601 mov r1, r0 801b228: 6818 ldr r0, [r3, #0] 801b22a: f000 b825 b.w 801b278 <_malloc_r> 801b22e: bf00 nop 801b230: 2000011c .word 0x2000011c 0801b234 : 801b234: b570 push {r4, r5, r6, lr} 801b236: 4e0f ldr r6, [pc, #60] @ (801b274 ) 801b238: 460c mov r4, r1 801b23a: 6831 ldr r1, [r6, #0] 801b23c: 4605 mov r5, r0 801b23e: b911 cbnz r1, 801b246 801b240: f001 ffda bl 801d1f8 <_sbrk_r> 801b244: 6030 str r0, [r6, #0] 801b246: 4621 mov r1, r4 801b248: 4628 mov r0, r5 801b24a: f001 ffd5 bl 801d1f8 <_sbrk_r> 801b24e: 1c43 adds r3, r0, #1 801b250: d103 bne.n 801b25a 801b252: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 801b256: 4620 mov r0, r4 801b258: bd70 pop {r4, r5, r6, pc} 801b25a: 1cc4 adds r4, r0, #3 801b25c: f024 0403 bic.w r4, r4, #3 801b260: 42a0 cmp r0, r4 801b262: d0f8 beq.n 801b256 801b264: 1a21 subs r1, r4, r0 801b266: 4628 mov r0, r5 801b268: f001 ffc6 bl 801d1f8 <_sbrk_r> 801b26c: 3001 adds r0, #1 801b26e: d1f2 bne.n 801b256 801b270: e7ef b.n 801b252 801b272: bf00 nop 801b274: 20013ce0 .word 0x20013ce0 0801b278 <_malloc_r>: 801b278: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801b27c: 1ccd adds r5, r1, #3 801b27e: f025 0503 bic.w r5, r5, #3 801b282: 3508 adds r5, #8 801b284: 2d0c cmp r5, #12 801b286: bf38 it cc 801b288: 250c movcc r5, #12 801b28a: 2d00 cmp r5, #0 801b28c: 4606 mov r6, r0 801b28e: db01 blt.n 801b294 <_malloc_r+0x1c> 801b290: 42a9 cmp r1, r5 801b292: d904 bls.n 801b29e <_malloc_r+0x26> 801b294: 230c movs r3, #12 801b296: 6033 str r3, [r6, #0] 801b298: 2000 movs r0, #0 801b29a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801b29e: f8df 80d4 ldr.w r8, [pc, #212] @ 801b374 <_malloc_r+0xfc> 801b2a2: f000 f869 bl 801b378 <__malloc_lock> 801b2a6: f8d8 3000 ldr.w r3, [r8] 801b2aa: 461c mov r4, r3 801b2ac: bb44 cbnz r4, 801b300 <_malloc_r+0x88> 801b2ae: 4629 mov r1, r5 801b2b0: 4630 mov r0, r6 801b2b2: f7ff ffbf bl 801b234 801b2b6: 1c43 adds r3, r0, #1 801b2b8: 4604 mov r4, r0 801b2ba: d158 bne.n 801b36e <_malloc_r+0xf6> 801b2bc: f8d8 4000 ldr.w r4, [r8] 801b2c0: 4627 mov r7, r4 801b2c2: 2f00 cmp r7, #0 801b2c4: d143 bne.n 801b34e <_malloc_r+0xd6> 801b2c6: 2c00 cmp r4, #0 801b2c8: d04b beq.n 801b362 <_malloc_r+0xea> 801b2ca: 6823 ldr r3, [r4, #0] 801b2cc: 4639 mov r1, r7 801b2ce: 4630 mov r0, r6 801b2d0: eb04 0903 add.w r9, r4, r3 801b2d4: f001 ff90 bl 801d1f8 <_sbrk_r> 801b2d8: 4581 cmp r9, r0 801b2da: d142 bne.n 801b362 <_malloc_r+0xea> 801b2dc: 6821 ldr r1, [r4, #0] 801b2de: 1a6d subs r5, r5, r1 801b2e0: 4629 mov r1, r5 801b2e2: 4630 mov r0, r6 801b2e4: f7ff ffa6 bl 801b234 801b2e8: 3001 adds r0, #1 801b2ea: d03a beq.n 801b362 <_malloc_r+0xea> 801b2ec: 6823 ldr r3, [r4, #0] 801b2ee: 442b add r3, r5 801b2f0: 6023 str r3, [r4, #0] 801b2f2: f8d8 3000 ldr.w r3, [r8] 801b2f6: 685a ldr r2, [r3, #4] 801b2f8: bb62 cbnz r2, 801b354 <_malloc_r+0xdc> 801b2fa: f8c8 7000 str.w r7, [r8] 801b2fe: e00f b.n 801b320 <_malloc_r+0xa8> 801b300: 6822 ldr r2, [r4, #0] 801b302: 1b52 subs r2, r2, r5 801b304: d420 bmi.n 801b348 <_malloc_r+0xd0> 801b306: 2a0b cmp r2, #11 801b308: d917 bls.n 801b33a <_malloc_r+0xc2> 801b30a: 1961 adds r1, r4, r5 801b30c: 42a3 cmp r3, r4 801b30e: 6025 str r5, [r4, #0] 801b310: bf18 it ne 801b312: 6059 strne r1, [r3, #4] 801b314: 6863 ldr r3, [r4, #4] 801b316: bf08 it eq 801b318: f8c8 1000 streq.w r1, [r8] 801b31c: 5162 str r2, [r4, r5] 801b31e: 604b str r3, [r1, #4] 801b320: 4630 mov r0, r6 801b322: f000 f82f bl 801b384 <__malloc_unlock> 801b326: f104 000b add.w r0, r4, #11 801b32a: 1d23 adds r3, r4, #4 801b32c: f020 0007 bic.w r0, r0, #7 801b330: 1ac2 subs r2, r0, r3 801b332: bf1c itt ne 801b334: 1a1b subne r3, r3, r0 801b336: 50a3 strne r3, [r4, r2] 801b338: e7af b.n 801b29a <_malloc_r+0x22> 801b33a: 6862 ldr r2, [r4, #4] 801b33c: 42a3 cmp r3, r4 801b33e: bf0c ite eq 801b340: f8c8 2000 streq.w r2, [r8] 801b344: 605a strne r2, [r3, #4] 801b346: e7eb b.n 801b320 <_malloc_r+0xa8> 801b348: 4623 mov r3, r4 801b34a: 6864 ldr r4, [r4, #4] 801b34c: e7ae b.n 801b2ac <_malloc_r+0x34> 801b34e: 463c mov r4, r7 801b350: 687f ldr r7, [r7, #4] 801b352: e7b6 b.n 801b2c2 <_malloc_r+0x4a> 801b354: 461a mov r2, r3 801b356: 685b ldr r3, [r3, #4] 801b358: 42a3 cmp r3, r4 801b35a: d1fb bne.n 801b354 <_malloc_r+0xdc> 801b35c: 2300 movs r3, #0 801b35e: 6053 str r3, [r2, #4] 801b360: e7de b.n 801b320 <_malloc_r+0xa8> 801b362: 230c movs r3, #12 801b364: 6033 str r3, [r6, #0] 801b366: 4630 mov r0, r6 801b368: f000 f80c bl 801b384 <__malloc_unlock> 801b36c: e794 b.n 801b298 <_malloc_r+0x20> 801b36e: 6005 str r5, [r0, #0] 801b370: e7d6 b.n 801b320 <_malloc_r+0xa8> 801b372: bf00 nop 801b374: 20013ce4 .word 0x20013ce4 0801b378 <__malloc_lock>: 801b378: 4801 ldr r0, [pc, #4] @ (801b380 <__malloc_lock+0x8>) 801b37a: f7ff b88e b.w 801a49a <__retarget_lock_acquire_recursive> 801b37e: bf00 nop 801b380: 20013cdc .word 0x20013cdc 0801b384 <__malloc_unlock>: 801b384: 4801 ldr r0, [pc, #4] @ (801b38c <__malloc_unlock+0x8>) 801b386: f7ff b889 b.w 801a49c <__retarget_lock_release_recursive> 801b38a: bf00 nop 801b38c: 20013cdc .word 0x20013cdc 0801b390 <_Balloc>: 801b390: b570 push {r4, r5, r6, lr} 801b392: 69c4 ldr r4, [r0, #28] 801b394: 4605 mov r5, r0 801b396: 460e mov r6, r1 801b398: b984 cbnz r4, 801b3bc <_Balloc+0x2c> 801b39a: 2010 movs r0, #16 801b39c: f7ff ff42 bl 801b224 801b3a0: 4604 mov r4, r0 801b3a2: 61e8 str r0, [r5, #28] 801b3a4: b928 cbnz r0, 801b3b2 <_Balloc+0x22> 801b3a6: 4602 mov r2, r0 801b3a8: 4b16 ldr r3, [pc, #88] @ (801b404 <_Balloc+0x74>) 801b3aa: 4817 ldr r0, [pc, #92] @ (801b408 <_Balloc+0x78>) 801b3ac: 216b movs r1, #107 @ 0x6b 801b3ae: f001 ff3b bl 801d228 <__assert_func> 801b3b2: 2300 movs r3, #0 801b3b4: e9c0 3301 strd r3, r3, [r0, #4] 801b3b8: 6003 str r3, [r0, #0] 801b3ba: 60c3 str r3, [r0, #12] 801b3bc: 68e3 ldr r3, [r4, #12] 801b3be: b953 cbnz r3, 801b3d6 <_Balloc+0x46> 801b3c0: 2221 movs r2, #33 @ 0x21 801b3c2: 2104 movs r1, #4 801b3c4: 4628 mov r0, r5 801b3c6: f001 ff4d bl 801d264 <_calloc_r> 801b3ca: 69eb ldr r3, [r5, #28] 801b3cc: 60e0 str r0, [r4, #12] 801b3ce: 68db ldr r3, [r3, #12] 801b3d0: b90b cbnz r3, 801b3d6 <_Balloc+0x46> 801b3d2: 2000 movs r0, #0 801b3d4: bd70 pop {r4, r5, r6, pc} 801b3d6: f853 0026 ldr.w r0, [r3, r6, lsl #2] 801b3da: b130 cbz r0, 801b3ea <_Balloc+0x5a> 801b3dc: 6802 ldr r2, [r0, #0] 801b3de: f843 2026 str.w r2, [r3, r6, lsl #2] 801b3e2: 2300 movs r3, #0 801b3e4: e9c0 3303 strd r3, r3, [r0, #12] 801b3e8: e7f4 b.n 801b3d4 <_Balloc+0x44> 801b3ea: 2101 movs r1, #1 801b3ec: fa01 f406 lsl.w r4, r1, r6 801b3f0: 1d62 adds r2, r4, #5 801b3f2: 0092 lsls r2, r2, #2 801b3f4: 4628 mov r0, r5 801b3f6: f001 ff35 bl 801d264 <_calloc_r> 801b3fa: 2800 cmp r0, #0 801b3fc: d0e9 beq.n 801b3d2 <_Balloc+0x42> 801b3fe: e9c0 6401 strd r6, r4, [r0, #4] 801b402: e7ee b.n 801b3e2 <_Balloc+0x52> 801b404: 0801e636 .word 0x0801e636 801b408: 0801e6b6 .word 0x0801e6b6 0801b40c <_Bfree>: 801b40c: b570 push {r4, r5, r6, lr} 801b40e: 69c6 ldr r6, [r0, #28] 801b410: 4605 mov r5, r0 801b412: 460c mov r4, r1 801b414: b976 cbnz r6, 801b434 <_Bfree+0x28> 801b416: 2010 movs r0, #16 801b418: f7ff ff04 bl 801b224 801b41c: 4602 mov r2, r0 801b41e: 61e8 str r0, [r5, #28] 801b420: b920 cbnz r0, 801b42c <_Bfree+0x20> 801b422: 4b09 ldr r3, [pc, #36] @ (801b448 <_Bfree+0x3c>) 801b424: 4809 ldr r0, [pc, #36] @ (801b44c <_Bfree+0x40>) 801b426: 218f movs r1, #143 @ 0x8f 801b428: f001 fefe bl 801d228 <__assert_func> 801b42c: e9c0 6601 strd r6, r6, [r0, #4] 801b430: 6006 str r6, [r0, #0] 801b432: 60c6 str r6, [r0, #12] 801b434: b13c cbz r4, 801b446 <_Bfree+0x3a> 801b436: 69eb ldr r3, [r5, #28] 801b438: 6862 ldr r2, [r4, #4] 801b43a: 68db ldr r3, [r3, #12] 801b43c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 801b440: 6021 str r1, [r4, #0] 801b442: f843 4022 str.w r4, [r3, r2, lsl #2] 801b446: bd70 pop {r4, r5, r6, pc} 801b448: 0801e636 .word 0x0801e636 801b44c: 0801e6b6 .word 0x0801e6b6 0801b450 <__multadd>: 801b450: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801b454: 690d ldr r5, [r1, #16] 801b456: 4607 mov r7, r0 801b458: 460c mov r4, r1 801b45a: 461e mov r6, r3 801b45c: f101 0c14 add.w ip, r1, #20 801b460: 2000 movs r0, #0 801b462: f8dc 3000 ldr.w r3, [ip] 801b466: b299 uxth r1, r3 801b468: fb02 6101 mla r1, r2, r1, r6 801b46c: 0c1e lsrs r6, r3, #16 801b46e: 0c0b lsrs r3, r1, #16 801b470: fb02 3306 mla r3, r2, r6, r3 801b474: b289 uxth r1, r1 801b476: 3001 adds r0, #1 801b478: eb01 4103 add.w r1, r1, r3, lsl #16 801b47c: 4285 cmp r5, r0 801b47e: f84c 1b04 str.w r1, [ip], #4 801b482: ea4f 4613 mov.w r6, r3, lsr #16 801b486: dcec bgt.n 801b462 <__multadd+0x12> 801b488: b30e cbz r6, 801b4ce <__multadd+0x7e> 801b48a: 68a3 ldr r3, [r4, #8] 801b48c: 42ab cmp r3, r5 801b48e: dc19 bgt.n 801b4c4 <__multadd+0x74> 801b490: 6861 ldr r1, [r4, #4] 801b492: 4638 mov r0, r7 801b494: 3101 adds r1, #1 801b496: f7ff ff7b bl 801b390 <_Balloc> 801b49a: 4680 mov r8, r0 801b49c: b928 cbnz r0, 801b4aa <__multadd+0x5a> 801b49e: 4602 mov r2, r0 801b4a0: 4b0c ldr r3, [pc, #48] @ (801b4d4 <__multadd+0x84>) 801b4a2: 480d ldr r0, [pc, #52] @ (801b4d8 <__multadd+0x88>) 801b4a4: 21ba movs r1, #186 @ 0xba 801b4a6: f001 febf bl 801d228 <__assert_func> 801b4aa: 6922 ldr r2, [r4, #16] 801b4ac: 3202 adds r2, #2 801b4ae: f104 010c add.w r1, r4, #12 801b4b2: 0092 lsls r2, r2, #2 801b4b4: 300c adds r0, #12 801b4b6: f7fe fff2 bl 801a49e 801b4ba: 4621 mov r1, r4 801b4bc: 4638 mov r0, r7 801b4be: f7ff ffa5 bl 801b40c <_Bfree> 801b4c2: 4644 mov r4, r8 801b4c4: eb04 0385 add.w r3, r4, r5, lsl #2 801b4c8: 3501 adds r5, #1 801b4ca: 615e str r6, [r3, #20] 801b4cc: 6125 str r5, [r4, #16] 801b4ce: 4620 mov r0, r4 801b4d0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801b4d4: 0801e6a5 .word 0x0801e6a5 801b4d8: 0801e6b6 .word 0x0801e6b6 0801b4dc <__s2b>: 801b4dc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801b4e0: 460c mov r4, r1 801b4e2: 4615 mov r5, r2 801b4e4: 461f mov r7, r3 801b4e6: 2209 movs r2, #9 801b4e8: 3308 adds r3, #8 801b4ea: 4606 mov r6, r0 801b4ec: fb93 f3f2 sdiv r3, r3, r2 801b4f0: 2100 movs r1, #0 801b4f2: 2201 movs r2, #1 801b4f4: 429a cmp r2, r3 801b4f6: db09 blt.n 801b50c <__s2b+0x30> 801b4f8: 4630 mov r0, r6 801b4fa: f7ff ff49 bl 801b390 <_Balloc> 801b4fe: b940 cbnz r0, 801b512 <__s2b+0x36> 801b500: 4602 mov r2, r0 801b502: 4b19 ldr r3, [pc, #100] @ (801b568 <__s2b+0x8c>) 801b504: 4819 ldr r0, [pc, #100] @ (801b56c <__s2b+0x90>) 801b506: 21d3 movs r1, #211 @ 0xd3 801b508: f001 fe8e bl 801d228 <__assert_func> 801b50c: 0052 lsls r2, r2, #1 801b50e: 3101 adds r1, #1 801b510: e7f0 b.n 801b4f4 <__s2b+0x18> 801b512: 9b08 ldr r3, [sp, #32] 801b514: 6143 str r3, [r0, #20] 801b516: 2d09 cmp r5, #9 801b518: f04f 0301 mov.w r3, #1 801b51c: 6103 str r3, [r0, #16] 801b51e: dd16 ble.n 801b54e <__s2b+0x72> 801b520: f104 0809 add.w r8, r4, #9 801b524: 46c1 mov r9, r8 801b526: 442c add r4, r5 801b528: f819 3b01 ldrb.w r3, [r9], #1 801b52c: 4601 mov r1, r0 801b52e: 3b30 subs r3, #48 @ 0x30 801b530: 220a movs r2, #10 801b532: 4630 mov r0, r6 801b534: f7ff ff8c bl 801b450 <__multadd> 801b538: 45a1 cmp r9, r4 801b53a: d1f5 bne.n 801b528 <__s2b+0x4c> 801b53c: 44a8 add r8, r5 801b53e: f1a8 0408 sub.w r4, r8, #8 801b542: 1b2d subs r5, r5, r4 801b544: 1963 adds r3, r4, r5 801b546: 429f cmp r7, r3 801b548: dc04 bgt.n 801b554 <__s2b+0x78> 801b54a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801b54e: 340a adds r4, #10 801b550: 2509 movs r5, #9 801b552: e7f6 b.n 801b542 <__s2b+0x66> 801b554: f814 3b01 ldrb.w r3, [r4], #1 801b558: 4601 mov r1, r0 801b55a: 3b30 subs r3, #48 @ 0x30 801b55c: 220a movs r2, #10 801b55e: 4630 mov r0, r6 801b560: f7ff ff76 bl 801b450 <__multadd> 801b564: e7ee b.n 801b544 <__s2b+0x68> 801b566: bf00 nop 801b568: 0801e6a5 .word 0x0801e6a5 801b56c: 0801e6b6 .word 0x0801e6b6 0801b570 <__hi0bits>: 801b570: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 801b574: 4603 mov r3, r0 801b576: bf36 itet cc 801b578: 0403 lslcc r3, r0, #16 801b57a: 2000 movcs r0, #0 801b57c: 2010 movcc r0, #16 801b57e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 801b582: bf3c itt cc 801b584: 021b lslcc r3, r3, #8 801b586: 3008 addcc r0, #8 801b588: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 801b58c: bf3c itt cc 801b58e: 011b lslcc r3, r3, #4 801b590: 3004 addcc r0, #4 801b592: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 801b596: bf3c itt cc 801b598: 009b lslcc r3, r3, #2 801b59a: 3002 addcc r0, #2 801b59c: 2b00 cmp r3, #0 801b59e: db05 blt.n 801b5ac <__hi0bits+0x3c> 801b5a0: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 801b5a4: f100 0001 add.w r0, r0, #1 801b5a8: bf08 it eq 801b5aa: 2020 moveq r0, #32 801b5ac: 4770 bx lr 0801b5ae <__lo0bits>: 801b5ae: 6803 ldr r3, [r0, #0] 801b5b0: 4602 mov r2, r0 801b5b2: f013 0007 ands.w r0, r3, #7 801b5b6: d00b beq.n 801b5d0 <__lo0bits+0x22> 801b5b8: 07d9 lsls r1, r3, #31 801b5ba: d421 bmi.n 801b600 <__lo0bits+0x52> 801b5bc: 0798 lsls r0, r3, #30 801b5be: bf49 itett mi 801b5c0: 085b lsrmi r3, r3, #1 801b5c2: 089b lsrpl r3, r3, #2 801b5c4: 2001 movmi r0, #1 801b5c6: 6013 strmi r3, [r2, #0] 801b5c8: bf5c itt pl 801b5ca: 6013 strpl r3, [r2, #0] 801b5cc: 2002 movpl r0, #2 801b5ce: 4770 bx lr 801b5d0: b299 uxth r1, r3 801b5d2: b909 cbnz r1, 801b5d8 <__lo0bits+0x2a> 801b5d4: 0c1b lsrs r3, r3, #16 801b5d6: 2010 movs r0, #16 801b5d8: b2d9 uxtb r1, r3 801b5da: b909 cbnz r1, 801b5e0 <__lo0bits+0x32> 801b5dc: 3008 adds r0, #8 801b5de: 0a1b lsrs r3, r3, #8 801b5e0: 0719 lsls r1, r3, #28 801b5e2: bf04 itt eq 801b5e4: 091b lsreq r3, r3, #4 801b5e6: 3004 addeq r0, #4 801b5e8: 0799 lsls r1, r3, #30 801b5ea: bf04 itt eq 801b5ec: 089b lsreq r3, r3, #2 801b5ee: 3002 addeq r0, #2 801b5f0: 07d9 lsls r1, r3, #31 801b5f2: d403 bmi.n 801b5fc <__lo0bits+0x4e> 801b5f4: 085b lsrs r3, r3, #1 801b5f6: f100 0001 add.w r0, r0, #1 801b5fa: d003 beq.n 801b604 <__lo0bits+0x56> 801b5fc: 6013 str r3, [r2, #0] 801b5fe: 4770 bx lr 801b600: 2000 movs r0, #0 801b602: 4770 bx lr 801b604: 2020 movs r0, #32 801b606: 4770 bx lr 0801b608 <__i2b>: 801b608: b510 push {r4, lr} 801b60a: 460c mov r4, r1 801b60c: 2101 movs r1, #1 801b60e: f7ff febf bl 801b390 <_Balloc> 801b612: 4602 mov r2, r0 801b614: b928 cbnz r0, 801b622 <__i2b+0x1a> 801b616: 4b05 ldr r3, [pc, #20] @ (801b62c <__i2b+0x24>) 801b618: 4805 ldr r0, [pc, #20] @ (801b630 <__i2b+0x28>) 801b61a: f240 1145 movw r1, #325 @ 0x145 801b61e: f001 fe03 bl 801d228 <__assert_func> 801b622: 2301 movs r3, #1 801b624: 6144 str r4, [r0, #20] 801b626: 6103 str r3, [r0, #16] 801b628: bd10 pop {r4, pc} 801b62a: bf00 nop 801b62c: 0801e6a5 .word 0x0801e6a5 801b630: 0801e6b6 .word 0x0801e6b6 0801b634 <__multiply>: 801b634: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801b638: f8d1 9010 ldr.w r9, [r1, #16] 801b63c: f8d2 a010 ldr.w sl, [r2, #16] 801b640: 45d1 cmp r9, sl 801b642: b085 sub sp, #20 801b644: 4688 mov r8, r1 801b646: 4614 mov r4, r2 801b648: db04 blt.n 801b654 <__multiply+0x20> 801b64a: 4653 mov r3, sl 801b64c: 460c mov r4, r1 801b64e: 46ca mov sl, r9 801b650: 4690 mov r8, r2 801b652: 4699 mov r9, r3 801b654: 68a3 ldr r3, [r4, #8] 801b656: 6861 ldr r1, [r4, #4] 801b658: eb0a 0609 add.w r6, sl, r9 801b65c: 42b3 cmp r3, r6 801b65e: bfb8 it lt 801b660: 3101 addlt r1, #1 801b662: f7ff fe95 bl 801b390 <_Balloc> 801b666: b930 cbnz r0, 801b676 <__multiply+0x42> 801b668: 4602 mov r2, r0 801b66a: 4b45 ldr r3, [pc, #276] @ (801b780 <__multiply+0x14c>) 801b66c: 4845 ldr r0, [pc, #276] @ (801b784 <__multiply+0x150>) 801b66e: f44f 71b1 mov.w r1, #354 @ 0x162 801b672: f001 fdd9 bl 801d228 <__assert_func> 801b676: f100 0514 add.w r5, r0, #20 801b67a: eb05 0786 add.w r7, r5, r6, lsl #2 801b67e: 462b mov r3, r5 801b680: 2200 movs r2, #0 801b682: 42bb cmp r3, r7 801b684: d31f bcc.n 801b6c6 <__multiply+0x92> 801b686: f104 0c14 add.w ip, r4, #20 801b68a: f108 0114 add.w r1, r8, #20 801b68e: eb0c 038a add.w r3, ip, sl, lsl #2 801b692: eb01 0289 add.w r2, r1, r9, lsl #2 801b696: 9202 str r2, [sp, #8] 801b698: 1b1a subs r2, r3, r4 801b69a: 3a15 subs r2, #21 801b69c: f022 0203 bic.w r2, r2, #3 801b6a0: 3415 adds r4, #21 801b6a2: 429c cmp r4, r3 801b6a4: bf88 it hi 801b6a6: 2200 movhi r2, #0 801b6a8: 9201 str r2, [sp, #4] 801b6aa: 9a02 ldr r2, [sp, #8] 801b6ac: 9103 str r1, [sp, #12] 801b6ae: 428a cmp r2, r1 801b6b0: d80c bhi.n 801b6cc <__multiply+0x98> 801b6b2: 2e00 cmp r6, #0 801b6b4: dd03 ble.n 801b6be <__multiply+0x8a> 801b6b6: f857 3d04 ldr.w r3, [r7, #-4]! 801b6ba: 2b00 cmp r3, #0 801b6bc: d05d beq.n 801b77a <__multiply+0x146> 801b6be: 6106 str r6, [r0, #16] 801b6c0: b005 add sp, #20 801b6c2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801b6c6: f843 2b04 str.w r2, [r3], #4 801b6ca: e7da b.n 801b682 <__multiply+0x4e> 801b6cc: f8b1 a000 ldrh.w sl, [r1] 801b6d0: f1ba 0f00 cmp.w sl, #0 801b6d4: d024 beq.n 801b720 <__multiply+0xec> 801b6d6: 46e0 mov r8, ip 801b6d8: 46a9 mov r9, r5 801b6da: f04f 0e00 mov.w lr, #0 801b6de: f858 2b04 ldr.w r2, [r8], #4 801b6e2: f8d9 4000 ldr.w r4, [r9] 801b6e6: fa1f fb82 uxth.w fp, r2 801b6ea: b2a4 uxth r4, r4 801b6ec: fb0a 440b mla r4, sl, fp, r4 801b6f0: ea4f 4b12 mov.w fp, r2, lsr #16 801b6f4: f8d9 2000 ldr.w r2, [r9] 801b6f8: 4474 add r4, lr 801b6fa: ea4f 4e12 mov.w lr, r2, lsr #16 801b6fe: fb0a e20b mla r2, sl, fp, lr 801b702: eb02 4214 add.w r2, r2, r4, lsr #16 801b706: b2a4 uxth r4, r4 801b708: ea44 4402 orr.w r4, r4, r2, lsl #16 801b70c: 4543 cmp r3, r8 801b70e: f849 4b04 str.w r4, [r9], #4 801b712: ea4f 4e12 mov.w lr, r2, lsr #16 801b716: d8e2 bhi.n 801b6de <__multiply+0xaa> 801b718: 9a01 ldr r2, [sp, #4] 801b71a: 18aa adds r2, r5, r2 801b71c: f8c2 e004 str.w lr, [r2, #4] 801b720: 9a03 ldr r2, [sp, #12] 801b722: f8b2 8002 ldrh.w r8, [r2, #2] 801b726: 3104 adds r1, #4 801b728: f1b8 0f00 cmp.w r8, #0 801b72c: d023 beq.n 801b776 <__multiply+0x142> 801b72e: 682a ldr r2, [r5, #0] 801b730: 46e6 mov lr, ip 801b732: 4691 mov r9, r2 801b734: 46aa mov sl, r5 801b736: f04f 0b00 mov.w fp, #0 801b73a: f8be 4000 ldrh.w r4, [lr] 801b73e: fb08 b404 mla r4, r8, r4, fp 801b742: eb04 4419 add.w r4, r4, r9, lsr #16 801b746: b292 uxth r2, r2 801b748: ea42 4204 orr.w r2, r2, r4, lsl #16 801b74c: f84a 2b04 str.w r2, [sl], #4 801b750: f85e 2b04 ldr.w r2, [lr], #4 801b754: f8da 9000 ldr.w r9, [sl] 801b758: ea4f 4b12 mov.w fp, r2, lsr #16 801b75c: fa1f f289 uxth.w r2, r9 801b760: fb08 220b mla r2, r8, fp, r2 801b764: eb02 4214 add.w r2, r2, r4, lsr #16 801b768: 4573 cmp r3, lr 801b76a: ea4f 4b12 mov.w fp, r2, lsr #16 801b76e: d8e4 bhi.n 801b73a <__multiply+0x106> 801b770: 9c01 ldr r4, [sp, #4] 801b772: 192c adds r4, r5, r4 801b774: 6062 str r2, [r4, #4] 801b776: 3504 adds r5, #4 801b778: e797 b.n 801b6aa <__multiply+0x76> 801b77a: 3e01 subs r6, #1 801b77c: e799 b.n 801b6b2 <__multiply+0x7e> 801b77e: bf00 nop 801b780: 0801e6a5 .word 0x0801e6a5 801b784: 0801e6b6 .word 0x0801e6b6 0801b788 <__pow5mult>: 801b788: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 801b78c: 4617 mov r7, r2 801b78e: f012 0203 ands.w r2, r2, #3 801b792: 4680 mov r8, r0 801b794: 460d mov r5, r1 801b796: d007 beq.n 801b7a8 <__pow5mult+0x20> 801b798: 4c26 ldr r4, [pc, #152] @ (801b834 <__pow5mult+0xac>) 801b79a: 3a01 subs r2, #1 801b79c: 2300 movs r3, #0 801b79e: f854 2022 ldr.w r2, [r4, r2, lsl #2] 801b7a2: f7ff fe55 bl 801b450 <__multadd> 801b7a6: 4605 mov r5, r0 801b7a8: 10bf asrs r7, r7, #2 801b7aa: d03f beq.n 801b82c <__pow5mult+0xa4> 801b7ac: f8d8 401c ldr.w r4, [r8, #28] 801b7b0: b994 cbnz r4, 801b7d8 <__pow5mult+0x50> 801b7b2: 2010 movs r0, #16 801b7b4: f7ff fd36 bl 801b224 801b7b8: 4604 mov r4, r0 801b7ba: f8c8 001c str.w r0, [r8, #28] 801b7be: b930 cbnz r0, 801b7ce <__pow5mult+0x46> 801b7c0: 4602 mov r2, r0 801b7c2: 4b1d ldr r3, [pc, #116] @ (801b838 <__pow5mult+0xb0>) 801b7c4: 481d ldr r0, [pc, #116] @ (801b83c <__pow5mult+0xb4>) 801b7c6: f240 11b3 movw r1, #435 @ 0x1b3 801b7ca: f001 fd2d bl 801d228 <__assert_func> 801b7ce: 2300 movs r3, #0 801b7d0: e9c0 3301 strd r3, r3, [r0, #4] 801b7d4: 6003 str r3, [r0, #0] 801b7d6: 60c3 str r3, [r0, #12] 801b7d8: 68a6 ldr r6, [r4, #8] 801b7da: b946 cbnz r6, 801b7ee <__pow5mult+0x66> 801b7dc: f240 2171 movw r1, #625 @ 0x271 801b7e0: 4640 mov r0, r8 801b7e2: f7ff ff11 bl 801b608 <__i2b> 801b7e6: 2300 movs r3, #0 801b7e8: 60a0 str r0, [r4, #8] 801b7ea: 4606 mov r6, r0 801b7ec: 6003 str r3, [r0, #0] 801b7ee: 462c mov r4, r5 801b7f0: f04f 0900 mov.w r9, #0 801b7f4: f007 0301 and.w r3, r7, #1 801b7f8: 107f asrs r7, r7, #1 801b7fa: b153 cbz r3, 801b812 <__pow5mult+0x8a> 801b7fc: 4629 mov r1, r5 801b7fe: 4632 mov r2, r6 801b800: 4640 mov r0, r8 801b802: f7ff ff17 bl 801b634 <__multiply> 801b806: 4621 mov r1, r4 801b808: 4605 mov r5, r0 801b80a: 4640 mov r0, r8 801b80c: f7ff fdfe bl 801b40c <_Bfree> 801b810: b167 cbz r7, 801b82c <__pow5mult+0xa4> 801b812: 6830 ldr r0, [r6, #0] 801b814: b938 cbnz r0, 801b826 <__pow5mult+0x9e> 801b816: 4632 mov r2, r6 801b818: 4631 mov r1, r6 801b81a: 4640 mov r0, r8 801b81c: f7ff ff0a bl 801b634 <__multiply> 801b820: 6030 str r0, [r6, #0] 801b822: f8c0 9000 str.w r9, [r0] 801b826: 4606 mov r6, r0 801b828: 462c mov r4, r5 801b82a: e7e3 b.n 801b7f4 <__pow5mult+0x6c> 801b82c: 4628 mov r0, r5 801b82e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801b832: bf00 nop 801b834: 0801e7c8 .word 0x0801e7c8 801b838: 0801e636 .word 0x0801e636 801b83c: 0801e6b6 .word 0x0801e6b6 0801b840 <__lshift>: 801b840: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801b844: 460c mov r4, r1 801b846: 6849 ldr r1, [r1, #4] 801b848: 6923 ldr r3, [r4, #16] 801b84a: eb03 1862 add.w r8, r3, r2, asr #5 801b84e: 68a3 ldr r3, [r4, #8] 801b850: 4607 mov r7, r0 801b852: 4615 mov r5, r2 801b854: ea4f 1a62 mov.w sl, r2, asr #5 801b858: f108 0901 add.w r9, r8, #1 801b85c: 454b cmp r3, r9 801b85e: db0b blt.n 801b878 <__lshift+0x38> 801b860: 4638 mov r0, r7 801b862: f7ff fd95 bl 801b390 <_Balloc> 801b866: 4606 mov r6, r0 801b868: b948 cbnz r0, 801b87e <__lshift+0x3e> 801b86a: 4602 mov r2, r0 801b86c: 4b29 ldr r3, [pc, #164] @ (801b914 <__lshift+0xd4>) 801b86e: 482a ldr r0, [pc, #168] @ (801b918 <__lshift+0xd8>) 801b870: f44f 71ef mov.w r1, #478 @ 0x1de 801b874: f001 fcd8 bl 801d228 <__assert_func> 801b878: 3101 adds r1, #1 801b87a: 005b lsls r3, r3, #1 801b87c: e7ee b.n 801b85c <__lshift+0x1c> 801b87e: 2300 movs r3, #0 801b880: f100 0c14 add.w ip, r0, #20 801b884: f100 0210 add.w r2, r0, #16 801b888: 4619 mov r1, r3 801b88a: 4553 cmp r3, sl 801b88c: db35 blt.n 801b8fa <__lshift+0xba> 801b88e: 6922 ldr r2, [r4, #16] 801b890: ea2a 7aea bic.w sl, sl, sl, asr #31 801b894: eb0c 0c8a add.w ip, ip, sl, lsl #2 801b898: f104 0314 add.w r3, r4, #20 801b89c: f015 0e1f ands.w lr, r5, #31 801b8a0: 4661 mov r1, ip 801b8a2: eb03 0282 add.w r2, r3, r2, lsl #2 801b8a6: d02c beq.n 801b902 <__lshift+0xc2> 801b8a8: f1ce 0a20 rsb sl, lr, #32 801b8ac: 2500 movs r5, #0 801b8ae: 6818 ldr r0, [r3, #0] 801b8b0: 468b mov fp, r1 801b8b2: fa00 f00e lsl.w r0, r0, lr 801b8b6: 4328 orrs r0, r5 801b8b8: f8cb 0000 str.w r0, [fp] 801b8bc: f853 5b04 ldr.w r5, [r3], #4 801b8c0: 429a cmp r2, r3 801b8c2: f101 0104 add.w r1, r1, #4 801b8c6: fa25 f50a lsr.w r5, r5, sl 801b8ca: d8f0 bhi.n 801b8ae <__lshift+0x6e> 801b8cc: 1b13 subs r3, r2, r4 801b8ce: 3b15 subs r3, #21 801b8d0: f023 0303 bic.w r3, r3, #3 801b8d4: f104 0115 add.w r1, r4, #21 801b8d8: 428a cmp r2, r1 801b8da: bf38 it cc 801b8dc: 2300 movcc r3, #0 801b8de: 449c add ip, r3 801b8e0: f8cc 5004 str.w r5, [ip, #4] 801b8e4: b905 cbnz r5, 801b8e8 <__lshift+0xa8> 801b8e6: 46c1 mov r9, r8 801b8e8: 4638 mov r0, r7 801b8ea: f8c6 9010 str.w r9, [r6, #16] 801b8ee: 4621 mov r1, r4 801b8f0: f7ff fd8c bl 801b40c <_Bfree> 801b8f4: 4630 mov r0, r6 801b8f6: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 801b8fa: f842 1f04 str.w r1, [r2, #4]! 801b8fe: 3301 adds r3, #1 801b900: e7c3 b.n 801b88a <__lshift+0x4a> 801b902: f853 5b04 ldr.w r5, [r3], #4 801b906: 600d str r5, [r1, #0] 801b908: 429a cmp r2, r3 801b90a: f101 0104 add.w r1, r1, #4 801b90e: d8f8 bhi.n 801b902 <__lshift+0xc2> 801b910: e7e9 b.n 801b8e6 <__lshift+0xa6> 801b912: bf00 nop 801b914: 0801e6a5 .word 0x0801e6a5 801b918: 0801e6b6 .word 0x0801e6b6 0801b91c <__mcmp>: 801b91c: 690a ldr r2, [r1, #16] 801b91e: 4603 mov r3, r0 801b920: 6900 ldr r0, [r0, #16] 801b922: 1a80 subs r0, r0, r2 801b924: b530 push {r4, r5, lr} 801b926: d10e bne.n 801b946 <__mcmp+0x2a> 801b928: 3314 adds r3, #20 801b92a: 3114 adds r1, #20 801b92c: eb03 0482 add.w r4, r3, r2, lsl #2 801b930: eb01 0182 add.w r1, r1, r2, lsl #2 801b934: f854 5d04 ldr.w r5, [r4, #-4]! 801b938: f851 2d04 ldr.w r2, [r1, #-4]! 801b93c: 4295 cmp r5, r2 801b93e: d003 beq.n 801b948 <__mcmp+0x2c> 801b940: d205 bcs.n 801b94e <__mcmp+0x32> 801b942: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801b946: bd30 pop {r4, r5, pc} 801b948: 42a3 cmp r3, r4 801b94a: d3f3 bcc.n 801b934 <__mcmp+0x18> 801b94c: e7fb b.n 801b946 <__mcmp+0x2a> 801b94e: 2001 movs r0, #1 801b950: e7f9 b.n 801b946 <__mcmp+0x2a> ... 0801b954 <__mdiff>: 801b954: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801b958: 468a mov sl, r1 801b95a: 4606 mov r6, r0 801b95c: 4611 mov r1, r2 801b95e: 4650 mov r0, sl 801b960: 4614 mov r4, r2 801b962: f7ff ffdb bl 801b91c <__mcmp> 801b966: 1e05 subs r5, r0, #0 801b968: d112 bne.n 801b990 <__mdiff+0x3c> 801b96a: 4629 mov r1, r5 801b96c: 4630 mov r0, r6 801b96e: f7ff fd0f bl 801b390 <_Balloc> 801b972: 4602 mov r2, r0 801b974: b928 cbnz r0, 801b982 <__mdiff+0x2e> 801b976: 4b41 ldr r3, [pc, #260] @ (801ba7c <__mdiff+0x128>) 801b978: f240 2137 movw r1, #567 @ 0x237 801b97c: 4840 ldr r0, [pc, #256] @ (801ba80 <__mdiff+0x12c>) 801b97e: f001 fc53 bl 801d228 <__assert_func> 801b982: 2301 movs r3, #1 801b984: e9c0 3504 strd r3, r5, [r0, #16] 801b988: 4610 mov r0, r2 801b98a: b003 add sp, #12 801b98c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801b990: bfbc itt lt 801b992: 4653 movlt r3, sl 801b994: 46a2 movlt sl, r4 801b996: 4630 mov r0, r6 801b998: f8da 1004 ldr.w r1, [sl, #4] 801b99c: bfba itte lt 801b99e: 461c movlt r4, r3 801b9a0: 2501 movlt r5, #1 801b9a2: 2500 movge r5, #0 801b9a4: f7ff fcf4 bl 801b390 <_Balloc> 801b9a8: 4602 mov r2, r0 801b9aa: b918 cbnz r0, 801b9b4 <__mdiff+0x60> 801b9ac: 4b33 ldr r3, [pc, #204] @ (801ba7c <__mdiff+0x128>) 801b9ae: f240 2145 movw r1, #581 @ 0x245 801b9b2: e7e3 b.n 801b97c <__mdiff+0x28> 801b9b4: f8da 7010 ldr.w r7, [sl, #16] 801b9b8: 6926 ldr r6, [r4, #16] 801b9ba: 60c5 str r5, [r0, #12] 801b9bc: f10a 0914 add.w r9, sl, #20 801b9c0: f104 0e14 add.w lr, r4, #20 801b9c4: f100 0514 add.w r5, r0, #20 801b9c8: f10a 0310 add.w r3, sl, #16 801b9cc: eb09 0887 add.w r8, r9, r7, lsl #2 801b9d0: eb0e 0686 add.w r6, lr, r6, lsl #2 801b9d4: 9301 str r3, [sp, #4] 801b9d6: 46ab mov fp, r5 801b9d8: f04f 0c00 mov.w ip, #0 801b9dc: 9b01 ldr r3, [sp, #4] 801b9de: f85e 0b04 ldr.w r0, [lr], #4 801b9e2: f853 af04 ldr.w sl, [r3, #4]! 801b9e6: 9301 str r3, [sp, #4] 801b9e8: fa1f f38a uxth.w r3, sl 801b9ec: 4619 mov r1, r3 801b9ee: b283 uxth r3, r0 801b9f0: 1acb subs r3, r1, r3 801b9f2: 0c00 lsrs r0, r0, #16 801b9f4: 4463 add r3, ip 801b9f6: ebc0 401a rsb r0, r0, sl, lsr #16 801b9fa: eb00 4023 add.w r0, r0, r3, asr #16 801b9fe: b29b uxth r3, r3 801ba00: ea43 4300 orr.w r3, r3, r0, lsl #16 801ba04: 4576 cmp r6, lr 801ba06: f84b 3b04 str.w r3, [fp], #4 801ba0a: ea4f 4c20 mov.w ip, r0, asr #16 801ba0e: d8e5 bhi.n 801b9dc <__mdiff+0x88> 801ba10: 1b33 subs r3, r6, r4 801ba12: 3b15 subs r3, #21 801ba14: 3415 adds r4, #21 801ba16: f023 0303 bic.w r3, r3, #3 801ba1a: 42a6 cmp r6, r4 801ba1c: bf38 it cc 801ba1e: 2300 movcc r3, #0 801ba20: 18e8 adds r0, r5, r3 801ba22: 444b add r3, r9 801ba24: 1d1c adds r4, r3, #4 801ba26: 3004 adds r0, #4 801ba28: 4626 mov r6, r4 801ba2a: eba5 0509 sub.w r5, r5, r9 801ba2e: 4546 cmp r6, r8 801ba30: eb06 0e05 add.w lr, r6, r5 801ba34: d30e bcc.n 801ba54 <__mdiff+0x100> 801ba36: f108 0103 add.w r1, r8, #3 801ba3a: 1b09 subs r1, r1, r4 801ba3c: f021 0103 bic.w r1, r1, #3 801ba40: 3301 adds r3, #1 801ba42: 4598 cmp r8, r3 801ba44: bf38 it cc 801ba46: 2100 movcc r1, #0 801ba48: 4401 add r1, r0 801ba4a: f851 3d04 ldr.w r3, [r1, #-4]! 801ba4e: b19b cbz r3, 801ba78 <__mdiff+0x124> 801ba50: 6117 str r7, [r2, #16] 801ba52: e799 b.n 801b988 <__mdiff+0x34> 801ba54: f856 1b04 ldr.w r1, [r6], #4 801ba58: 46e2 mov sl, ip 801ba5a: ea4f 4911 mov.w r9, r1, lsr #16 801ba5e: fa1c fc81 uxtah ip, ip, r1 801ba62: 4451 add r1, sl 801ba64: eb09 492c add.w r9, r9, ip, asr #16 801ba68: b289 uxth r1, r1 801ba6a: ea41 4109 orr.w r1, r1, r9, lsl #16 801ba6e: ea4f 4c29 mov.w ip, r9, asr #16 801ba72: f8ce 1000 str.w r1, [lr] 801ba76: e7da b.n 801ba2e <__mdiff+0xda> 801ba78: 3f01 subs r7, #1 801ba7a: e7e6 b.n 801ba4a <__mdiff+0xf6> 801ba7c: 0801e6a5 .word 0x0801e6a5 801ba80: 0801e6b6 .word 0x0801e6b6 0801ba84 <__ulp>: 801ba84: b082 sub sp, #8 801ba86: ed8d 0b00 vstr d0, [sp] 801ba8a: 9a01 ldr r2, [sp, #4] 801ba8c: 4b0f ldr r3, [pc, #60] @ (801bacc <__ulp+0x48>) 801ba8e: 4013 ands r3, r2 801ba90: f1a3 7350 sub.w r3, r3, #54525952 @ 0x3400000 801ba94: 2b00 cmp r3, #0 801ba96: dc08 bgt.n 801baaa <__ulp+0x26> 801ba98: 425b negs r3, r3 801ba9a: f1b3 7fa0 cmp.w r3, #20971520 @ 0x1400000 801ba9e: ea4f 5223 mov.w r2, r3, asr #20 801baa2: da04 bge.n 801baae <__ulp+0x2a> 801baa4: f44f 2300 mov.w r3, #524288 @ 0x80000 801baa8: 4113 asrs r3, r2 801baaa: 2200 movs r2, #0 801baac: e008 b.n 801bac0 <__ulp+0x3c> 801baae: f1a2 0314 sub.w r3, r2, #20 801bab2: 2b1e cmp r3, #30 801bab4: bfda itte le 801bab6: f04f 4200 movle.w r2, #2147483648 @ 0x80000000 801baba: 40da lsrle r2, r3 801babc: 2201 movgt r2, #1 801babe: 2300 movs r3, #0 801bac0: 4619 mov r1, r3 801bac2: 4610 mov r0, r2 801bac4: ec41 0b10 vmov d0, r0, r1 801bac8: b002 add sp, #8 801baca: 4770 bx lr 801bacc: 7ff00000 .word 0x7ff00000 0801bad0 <__b2d>: 801bad0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801bad4: 6906 ldr r6, [r0, #16] 801bad6: f100 0814 add.w r8, r0, #20 801bada: eb08 0686 add.w r6, r8, r6, lsl #2 801bade: 1f37 subs r7, r6, #4 801bae0: f856 2c04 ldr.w r2, [r6, #-4] 801bae4: 4610 mov r0, r2 801bae6: f7ff fd43 bl 801b570 <__hi0bits> 801baea: f1c0 0320 rsb r3, r0, #32 801baee: 280a cmp r0, #10 801baf0: 600b str r3, [r1, #0] 801baf2: 491b ldr r1, [pc, #108] @ (801bb60 <__b2d+0x90>) 801baf4: dc15 bgt.n 801bb22 <__b2d+0x52> 801baf6: f1c0 0c0b rsb ip, r0, #11 801bafa: fa22 f30c lsr.w r3, r2, ip 801bafe: 45b8 cmp r8, r7 801bb00: ea43 0501 orr.w r5, r3, r1 801bb04: bf34 ite cc 801bb06: f856 3c08 ldrcc.w r3, [r6, #-8] 801bb0a: 2300 movcs r3, #0 801bb0c: 3015 adds r0, #21 801bb0e: fa02 f000 lsl.w r0, r2, r0 801bb12: fa23 f30c lsr.w r3, r3, ip 801bb16: 4303 orrs r3, r0 801bb18: 461c mov r4, r3 801bb1a: ec45 4b10 vmov d0, r4, r5 801bb1e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801bb22: 45b8 cmp r8, r7 801bb24: bf3a itte cc 801bb26: f856 3c08 ldrcc.w r3, [r6, #-8] 801bb2a: f1a6 0708 subcc.w r7, r6, #8 801bb2e: 2300 movcs r3, #0 801bb30: 380b subs r0, #11 801bb32: d012 beq.n 801bb5a <__b2d+0x8a> 801bb34: f1c0 0120 rsb r1, r0, #32 801bb38: fa23 f401 lsr.w r4, r3, r1 801bb3c: 4082 lsls r2, r0 801bb3e: 4322 orrs r2, r4 801bb40: 4547 cmp r7, r8 801bb42: f042 557f orr.w r5, r2, #1069547520 @ 0x3fc00000 801bb46: bf8c ite hi 801bb48: f857 2c04 ldrhi.w r2, [r7, #-4] 801bb4c: 2200 movls r2, #0 801bb4e: 4083 lsls r3, r0 801bb50: 40ca lsrs r2, r1 801bb52: f445 1540 orr.w r5, r5, #3145728 @ 0x300000 801bb56: 4313 orrs r3, r2 801bb58: e7de b.n 801bb18 <__b2d+0x48> 801bb5a: ea42 0501 orr.w r5, r2, r1 801bb5e: e7db b.n 801bb18 <__b2d+0x48> 801bb60: 3ff00000 .word 0x3ff00000 0801bb64 <__d2b>: 801bb64: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 801bb68: 460f mov r7, r1 801bb6a: 2101 movs r1, #1 801bb6c: ec59 8b10 vmov r8, r9, d0 801bb70: 4616 mov r6, r2 801bb72: f7ff fc0d bl 801b390 <_Balloc> 801bb76: 4604 mov r4, r0 801bb78: b930 cbnz r0, 801bb88 <__d2b+0x24> 801bb7a: 4602 mov r2, r0 801bb7c: 4b23 ldr r3, [pc, #140] @ (801bc0c <__d2b+0xa8>) 801bb7e: 4824 ldr r0, [pc, #144] @ (801bc10 <__d2b+0xac>) 801bb80: f240 310f movw r1, #783 @ 0x30f 801bb84: f001 fb50 bl 801d228 <__assert_func> 801bb88: f3c9 550a ubfx r5, r9, #20, #11 801bb8c: f3c9 0313 ubfx r3, r9, #0, #20 801bb90: b10d cbz r5, 801bb96 <__d2b+0x32> 801bb92: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 801bb96: 9301 str r3, [sp, #4] 801bb98: f1b8 0300 subs.w r3, r8, #0 801bb9c: d023 beq.n 801bbe6 <__d2b+0x82> 801bb9e: 4668 mov r0, sp 801bba0: 9300 str r3, [sp, #0] 801bba2: f7ff fd04 bl 801b5ae <__lo0bits> 801bba6: 9900 ldr r1, [sp, #0] 801bba8: b1d8 cbz r0, 801bbe2 <__d2b+0x7e> 801bbaa: 9a01 ldr r2, [sp, #4] 801bbac: f1c0 0320 rsb r3, r0, #32 801bbb0: fa02 f303 lsl.w r3, r2, r3 801bbb4: 430b orrs r3, r1 801bbb6: 40c2 lsrs r2, r0 801bbb8: 6163 str r3, [r4, #20] 801bbba: 9201 str r2, [sp, #4] 801bbbc: 9b01 ldr r3, [sp, #4] 801bbbe: 61a3 str r3, [r4, #24] 801bbc0: 2b00 cmp r3, #0 801bbc2: bf0c ite eq 801bbc4: 2201 moveq r2, #1 801bbc6: 2202 movne r2, #2 801bbc8: 6122 str r2, [r4, #16] 801bbca: b1a5 cbz r5, 801bbf6 <__d2b+0x92> 801bbcc: f2a5 4533 subw r5, r5, #1075 @ 0x433 801bbd0: 4405 add r5, r0 801bbd2: 603d str r5, [r7, #0] 801bbd4: f1c0 0035 rsb r0, r0, #53 @ 0x35 801bbd8: 6030 str r0, [r6, #0] 801bbda: 4620 mov r0, r4 801bbdc: b003 add sp, #12 801bbde: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 801bbe2: 6161 str r1, [r4, #20] 801bbe4: e7ea b.n 801bbbc <__d2b+0x58> 801bbe6: a801 add r0, sp, #4 801bbe8: f7ff fce1 bl 801b5ae <__lo0bits> 801bbec: 9b01 ldr r3, [sp, #4] 801bbee: 6163 str r3, [r4, #20] 801bbf0: 3020 adds r0, #32 801bbf2: 2201 movs r2, #1 801bbf4: e7e8 b.n 801bbc8 <__d2b+0x64> 801bbf6: eb04 0382 add.w r3, r4, r2, lsl #2 801bbfa: f2a0 4032 subw r0, r0, #1074 @ 0x432 801bbfe: 6038 str r0, [r7, #0] 801bc00: 6918 ldr r0, [r3, #16] 801bc02: f7ff fcb5 bl 801b570 <__hi0bits> 801bc06: ebc0 1042 rsb r0, r0, r2, lsl #5 801bc0a: e7e5 b.n 801bbd8 <__d2b+0x74> 801bc0c: 0801e6a5 .word 0x0801e6a5 801bc10: 0801e6b6 .word 0x0801e6b6 0801bc14 <__ratio>: 801bc14: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801bc18: b085 sub sp, #20 801bc1a: e9cd 1000 strd r1, r0, [sp] 801bc1e: a902 add r1, sp, #8 801bc20: f7ff ff56 bl 801bad0 <__b2d> 801bc24: 9800 ldr r0, [sp, #0] 801bc26: a903 add r1, sp, #12 801bc28: ec55 4b10 vmov r4, r5, d0 801bc2c: f7ff ff50 bl 801bad0 <__b2d> 801bc30: 9b01 ldr r3, [sp, #4] 801bc32: 6919 ldr r1, [r3, #16] 801bc34: 9b00 ldr r3, [sp, #0] 801bc36: 691b ldr r3, [r3, #16] 801bc38: 1ac9 subs r1, r1, r3 801bc3a: e9dd 3202 ldrd r3, r2, [sp, #8] 801bc3e: 1a9b subs r3, r3, r2 801bc40: ec5b ab10 vmov sl, fp, d0 801bc44: eb03 1341 add.w r3, r3, r1, lsl #5 801bc48: 2b00 cmp r3, #0 801bc4a: bfce itee gt 801bc4c: 462a movgt r2, r5 801bc4e: ebc3 3303 rsble r3, r3, r3, lsl #12 801bc52: 465a movle r2, fp 801bc54: 462f mov r7, r5 801bc56: 46d9 mov r9, fp 801bc58: bfcc ite gt 801bc5a: eb02 5703 addgt.w r7, r2, r3, lsl #20 801bc5e: eb02 5903 addle.w r9, r2, r3, lsl #20 801bc62: 464b mov r3, r9 801bc64: 4652 mov r2, sl 801bc66: 4620 mov r0, r4 801bc68: 4639 mov r1, r7 801bc6a: f7e4 fdc7 bl 80007fc <__aeabi_ddiv> 801bc6e: ec41 0b10 vmov d0, r0, r1 801bc72: b005 add sp, #20 801bc74: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 0801bc78 <__copybits>: 801bc78: 3901 subs r1, #1 801bc7a: b570 push {r4, r5, r6, lr} 801bc7c: 1149 asrs r1, r1, #5 801bc7e: 6914 ldr r4, [r2, #16] 801bc80: 3101 adds r1, #1 801bc82: f102 0314 add.w r3, r2, #20 801bc86: eb00 0181 add.w r1, r0, r1, lsl #2 801bc8a: eb03 0484 add.w r4, r3, r4, lsl #2 801bc8e: 1f05 subs r5, r0, #4 801bc90: 42a3 cmp r3, r4 801bc92: d30c bcc.n 801bcae <__copybits+0x36> 801bc94: 1aa3 subs r3, r4, r2 801bc96: 3b11 subs r3, #17 801bc98: f023 0303 bic.w r3, r3, #3 801bc9c: 3211 adds r2, #17 801bc9e: 4294 cmp r4, r2 801bca0: bf38 it cc 801bca2: 2300 movcc r3, #0 801bca4: 4418 add r0, r3 801bca6: 2300 movs r3, #0 801bca8: 4288 cmp r0, r1 801bcaa: d305 bcc.n 801bcb8 <__copybits+0x40> 801bcac: bd70 pop {r4, r5, r6, pc} 801bcae: f853 6b04 ldr.w r6, [r3], #4 801bcb2: f845 6f04 str.w r6, [r5, #4]! 801bcb6: e7eb b.n 801bc90 <__copybits+0x18> 801bcb8: f840 3b04 str.w r3, [r0], #4 801bcbc: e7f4 b.n 801bca8 <__copybits+0x30> 0801bcbe <__any_on>: 801bcbe: f100 0214 add.w r2, r0, #20 801bcc2: 6900 ldr r0, [r0, #16] 801bcc4: 114b asrs r3, r1, #5 801bcc6: 4298 cmp r0, r3 801bcc8: b510 push {r4, lr} 801bcca: db11 blt.n 801bcf0 <__any_on+0x32> 801bccc: dd0a ble.n 801bce4 <__any_on+0x26> 801bcce: f011 011f ands.w r1, r1, #31 801bcd2: d007 beq.n 801bce4 <__any_on+0x26> 801bcd4: f852 4023 ldr.w r4, [r2, r3, lsl #2] 801bcd8: fa24 f001 lsr.w r0, r4, r1 801bcdc: fa00 f101 lsl.w r1, r0, r1 801bce0: 428c cmp r4, r1 801bce2: d10b bne.n 801bcfc <__any_on+0x3e> 801bce4: eb02 0383 add.w r3, r2, r3, lsl #2 801bce8: 4293 cmp r3, r2 801bcea: d803 bhi.n 801bcf4 <__any_on+0x36> 801bcec: 2000 movs r0, #0 801bcee: bd10 pop {r4, pc} 801bcf0: 4603 mov r3, r0 801bcf2: e7f7 b.n 801bce4 <__any_on+0x26> 801bcf4: f853 1d04 ldr.w r1, [r3, #-4]! 801bcf8: 2900 cmp r1, #0 801bcfa: d0f5 beq.n 801bce8 <__any_on+0x2a> 801bcfc: 2001 movs r0, #1 801bcfe: e7f6 b.n 801bcee <__any_on+0x30> 0801bd00 : 801bd00: b570 push {r4, r5, r6, lr} 801bd02: 4604 mov r4, r0 801bd04: 460d mov r5, r1 801bd06: ec45 4b10 vmov d0, r4, r5 801bd0a: 4616 mov r6, r2 801bd0c: f7ff feba bl 801ba84 <__ulp> 801bd10: ec51 0b10 vmov r0, r1, d0 801bd14: b17e cbz r6, 801bd36 801bd16: f3c5 530a ubfx r3, r5, #20, #11 801bd1a: f1c3 036b rsb r3, r3, #107 @ 0x6b 801bd1e: 2b00 cmp r3, #0 801bd20: dd09 ble.n 801bd36 801bd22: 051b lsls r3, r3, #20 801bd24: f103 557f add.w r5, r3, #1069547520 @ 0x3fc00000 801bd28: 2400 movs r4, #0 801bd2a: f505 1540 add.w r5, r5, #3145728 @ 0x300000 801bd2e: 4622 mov r2, r4 801bd30: 462b mov r3, r5 801bd32: f7e4 fc39 bl 80005a8 <__aeabi_dmul> 801bd36: ec41 0b10 vmov d0, r0, r1 801bd3a: bd70 pop {r4, r5, r6, pc} 801bd3c: 0000 movs r0, r0 ... 0801bd40 <_strtod_l>: 801bd40: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801bd44: b09d sub sp, #116 @ 0x74 801bd46: 460e mov r6, r1 801bd48: 9215 str r2, [sp, #84] @ 0x54 801bd4a: 2200 movs r2, #0 801bd4c: 9004 str r0, [sp, #16] 801bd4e: 9218 str r2, [sp, #96] @ 0x60 801bd50: f04f 0800 mov.w r8, #0 801bd54: f04f 0900 mov.w r9, #0 801bd58: 9117 str r1, [sp, #92] @ 0x5c 801bd5a: 780a ldrb r2, [r1, #0] 801bd5c: 2a2b cmp r2, #43 @ 0x2b 801bd5e: 460d mov r5, r1 801bd60: f101 0101 add.w r1, r1, #1 801bd64: d01d beq.n 801bda2 <_strtod_l+0x62> 801bd66: d80b bhi.n 801bd80 <_strtod_l+0x40> 801bd68: 2a0d cmp r2, #13 801bd6a: d806 bhi.n 801bd7a <_strtod_l+0x3a> 801bd6c: 2a08 cmp r2, #8 801bd6e: d8f3 bhi.n 801bd58 <_strtod_l+0x18> 801bd70: b17a cbz r2, 801bd92 <_strtod_l+0x52> 801bd72: 2300 movs r3, #0 801bd74: 930b str r3, [sp, #44] @ 0x2c 801bd76: 469a mov sl, r3 801bd78: e083 b.n 801be82 <_strtod_l+0x142> 801bd7a: 2a20 cmp r2, #32 801bd7c: d0ec beq.n 801bd58 <_strtod_l+0x18> 801bd7e: e7f8 b.n 801bd72 <_strtod_l+0x32> 801bd80: 2a2d cmp r2, #45 @ 0x2d 801bd82: d110 bne.n 801bda6 <_strtod_l+0x66> 801bd84: 2201 movs r2, #1 801bd86: 1c69 adds r1, r5, #1 801bd88: 9117 str r1, [sp, #92] @ 0x5c 801bd8a: 920b str r2, [sp, #44] @ 0x2c 801bd8c: 786a ldrb r2, [r5, #1] 801bd8e: 2a00 cmp r2, #0 801bd90: d137 bne.n 801be02 <_strtod_l+0xc2> 801bd92: 9b15 ldr r3, [sp, #84] @ 0x54 801bd94: 9617 str r6, [sp, #92] @ 0x5c 801bd96: 2b00 cmp r3, #0 801bd98: f040 8595 bne.w 801c8c6 <_strtod_l+0xb86> 801bd9c: 4642 mov r2, r8 801bd9e: 464b mov r3, r9 801bda0: e02a b.n 801bdf8 <_strtod_l+0xb8> 801bda2: 2200 movs r2, #0 801bda4: e7ef b.n 801bd86 <_strtod_l+0x46> 801bda6: 2100 movs r1, #0 801bda8: 910b str r1, [sp, #44] @ 0x2c 801bdaa: 2a30 cmp r2, #48 @ 0x30 801bdac: f040 809b bne.w 801bee6 <_strtod_l+0x1a6> 801bdb0: 786a ldrb r2, [r5, #1] 801bdb2: f002 02df and.w r2, r2, #223 @ 0xdf 801bdb6: 2a58 cmp r2, #88 @ 0x58 801bdb8: d15a bne.n 801be70 <_strtod_l+0x130> 801bdba: 9302 str r3, [sp, #8] 801bdbc: 9b0b ldr r3, [sp, #44] @ 0x2c 801bdbe: 9301 str r3, [sp, #4] 801bdc0: ab18 add r3, sp, #96 @ 0x60 801bdc2: 9300 str r3, [sp, #0] 801bdc4: 4a81 ldr r2, [pc, #516] @ (801bfcc <_strtod_l+0x28c>) 801bdc6: 9804 ldr r0, [sp, #16] 801bdc8: ab19 add r3, sp, #100 @ 0x64 801bdca: a917 add r1, sp, #92 @ 0x5c 801bdcc: f001 fac6 bl 801d35c <__gethex> 801bdd0: f010 060f ands.w r6, r0, #15 801bdd4: 4604 mov r4, r0 801bdd6: d005 beq.n 801bde4 <_strtod_l+0xa4> 801bdd8: 2e06 cmp r6, #6 801bdda: d114 bne.n 801be06 <_strtod_l+0xc6> 801bddc: 3501 adds r5, #1 801bdde: 2300 movs r3, #0 801bde0: 9517 str r5, [sp, #92] @ 0x5c 801bde2: 930b str r3, [sp, #44] @ 0x2c 801bde4: 9b15 ldr r3, [sp, #84] @ 0x54 801bde6: 2b00 cmp r3, #0 801bde8: f040 856f bne.w 801c8ca <_strtod_l+0xb8a> 801bdec: 9b0b ldr r3, [sp, #44] @ 0x2c 801bdee: 2b00 cmp r3, #0 801bdf0: d0d4 beq.n 801bd9c <_strtod_l+0x5c> 801bdf2: 4642 mov r2, r8 801bdf4: f109 4300 add.w r3, r9, #2147483648 @ 0x80000000 801bdf8: ec43 2b10 vmov d0, r2, r3 801bdfc: b01d add sp, #116 @ 0x74 801bdfe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801be02: 460d mov r5, r1 801be04: e7d1 b.n 801bdaa <_strtod_l+0x6a> 801be06: 9a18 ldr r2, [sp, #96] @ 0x60 801be08: b13a cbz r2, 801be1a <_strtod_l+0xda> 801be0a: 2135 movs r1, #53 @ 0x35 801be0c: a81a add r0, sp, #104 @ 0x68 801be0e: f7ff ff33 bl 801bc78 <__copybits> 801be12: 9918 ldr r1, [sp, #96] @ 0x60 801be14: 9804 ldr r0, [sp, #16] 801be16: f7ff faf9 bl 801b40c <_Bfree> 801be1a: 3e01 subs r6, #1 801be1c: 2e04 cmp r6, #4 801be1e: d806 bhi.n 801be2e <_strtod_l+0xee> 801be20: e8df f006 tbb [pc, r6] 801be24: 211e0314 .word 0x211e0314 801be28: 14 .byte 0x14 801be29: 00 .byte 0x00 801be2a: e9dd 891a ldrd r8, r9, [sp, #104] @ 0x68 801be2e: 05e0 lsls r0, r4, #23 801be30: bf48 it mi 801be32: f049 4900 orrmi.w r9, r9, #2147483648 @ 0x80000000 801be36: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 801be3a: 0d1b lsrs r3, r3, #20 801be3c: 051b lsls r3, r3, #20 801be3e: 2b00 cmp r3, #0 801be40: d1d0 bne.n 801bde4 <_strtod_l+0xa4> 801be42: f7fe faff bl 801a444 <__errno> 801be46: 2322 movs r3, #34 @ 0x22 801be48: 6003 str r3, [r0, #0] 801be4a: e7cb b.n 801bde4 <_strtod_l+0xa4> 801be4c: e9dd 831a ldrd r8, r3, [sp, #104] @ 0x68 801be50: 9a19 ldr r2, [sp, #100] @ 0x64 801be52: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 801be56: f202 4233 addw r2, r2, #1075 @ 0x433 801be5a: ea43 5902 orr.w r9, r3, r2, lsl #20 801be5e: e7e6 b.n 801be2e <_strtod_l+0xee> 801be60: f8df 9170 ldr.w r9, [pc, #368] @ 801bfd4 <_strtod_l+0x294> 801be64: e7e3 b.n 801be2e <_strtod_l+0xee> 801be66: f06f 4900 mvn.w r9, #2147483648 @ 0x80000000 801be6a: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff 801be6e: e7de b.n 801be2e <_strtod_l+0xee> 801be70: 3501 adds r5, #1 801be72: 9517 str r5, [sp, #92] @ 0x5c 801be74: 782b ldrb r3, [r5, #0] 801be76: 2b30 cmp r3, #48 @ 0x30 801be78: d0fa beq.n 801be70 <_strtod_l+0x130> 801be7a: 2b00 cmp r3, #0 801be7c: d0b2 beq.n 801bde4 <_strtod_l+0xa4> 801be7e: f04f 0a01 mov.w sl, #1 801be82: 2700 movs r7, #0 801be84: 462b mov r3, r5 801be86: 970e str r7, [sp, #56] @ 0x38 801be88: 46bb mov fp, r7 801be8a: 210a movs r1, #10 801be8c: 4618 mov r0, r3 801be8e: f813 4b01 ldrb.w r4, [r3], #1 801be92: f1a4 0230 sub.w r2, r4, #48 @ 0x30 801be96: 2a09 cmp r2, #9 801be98: d928 bls.n 801beec <_strtod_l+0x1ac> 801be9a: 494d ldr r1, [pc, #308] @ (801bfd0 <_strtod_l+0x290>) 801be9c: 2201 movs r2, #1 801be9e: f001 f998 bl 801d1d2 801bea2: 2800 cmp r0, #0 801bea4: d034 beq.n 801bf10 <_strtod_l+0x1d0> 801bea6: 2000 movs r0, #0 801bea8: e9cd 0006 strd r0, r0, [sp, #24] 801beac: 4622 mov r2, r4 801beae: 465c mov r4, fp 801beb0: 2a65 cmp r2, #101 @ 0x65 801beb2: d001 beq.n 801beb8 <_strtod_l+0x178> 801beb4: 2a45 cmp r2, #69 @ 0x45 801beb6: d114 bne.n 801bee2 <_strtod_l+0x1a2> 801beb8: b924 cbnz r4, 801bec4 <_strtod_l+0x184> 801beba: ea5a 0300 orrs.w r3, sl, r0 801bebe: f43f af68 beq.w 801bd92 <_strtod_l+0x52> 801bec2: 2400 movs r4, #0 801bec4: 9e17 ldr r6, [sp, #92] @ 0x5c 801bec6: 1c73 adds r3, r6, #1 801bec8: 9317 str r3, [sp, #92] @ 0x5c 801beca: 7872 ldrb r2, [r6, #1] 801becc: 2a2b cmp r2, #43 @ 0x2b 801bece: d073 beq.n 801bfb8 <_strtod_l+0x278> 801bed0: 2a2d cmp r2, #45 @ 0x2d 801bed2: d077 beq.n 801bfc4 <_strtod_l+0x284> 801bed4: f04f 0c00 mov.w ip, #0 801bed8: f1a2 0330 sub.w r3, r2, #48 @ 0x30 801bedc: 2b09 cmp r3, #9 801bede: d97f bls.n 801bfe0 <_strtod_l+0x2a0> 801bee0: 9617 str r6, [sp, #92] @ 0x5c 801bee2: 2300 movs r3, #0 801bee4: e09e b.n 801c024 <_strtod_l+0x2e4> 801bee6: f04f 0a00 mov.w sl, #0 801beea: e7ca b.n 801be82 <_strtod_l+0x142> 801beec: f1bb 0f08 cmp.w fp, #8 801bef0: bfd8 it le 801bef2: 9a0e ldrle r2, [sp, #56] @ 0x38 801bef4: 9317 str r3, [sp, #92] @ 0x5c 801bef6: bfdb ittet le 801bef8: fb01 4202 mlale r2, r1, r2, r4 801befc: 3a30 suble r2, #48 @ 0x30 801befe: fb01 4207 mlagt r2, r1, r7, r4 801bf02: 920e strle r2, [sp, #56] @ 0x38 801bf04: bfc8 it gt 801bf06: f1a2 0730 subgt.w r7, r2, #48 @ 0x30 801bf0a: f10b 0b01 add.w fp, fp, #1 801bf0e: e7bd b.n 801be8c <_strtod_l+0x14c> 801bf10: 9b17 ldr r3, [sp, #92] @ 0x5c 801bf12: 1c5a adds r2, r3, #1 801bf14: 9217 str r2, [sp, #92] @ 0x5c 801bf16: 785a ldrb r2, [r3, #1] 801bf18: f1bb 0f00 cmp.w fp, #0 801bf1c: d033 beq.n 801bf86 <_strtod_l+0x246> 801bf1e: 9006 str r0, [sp, #24] 801bf20: 465c mov r4, fp 801bf22: f1a2 0330 sub.w r3, r2, #48 @ 0x30 801bf26: 2b09 cmp r3, #9 801bf28: d912 bls.n 801bf50 <_strtod_l+0x210> 801bf2a: 2301 movs r3, #1 801bf2c: 9307 str r3, [sp, #28] 801bf2e: e7bf b.n 801beb0 <_strtod_l+0x170> 801bf30: 9b17 ldr r3, [sp, #92] @ 0x5c 801bf32: 1c5a adds r2, r3, #1 801bf34: 9217 str r2, [sp, #92] @ 0x5c 801bf36: 785a ldrb r2, [r3, #1] 801bf38: 3001 adds r0, #1 801bf3a: 2a30 cmp r2, #48 @ 0x30 801bf3c: d0f8 beq.n 801bf30 <_strtod_l+0x1f0> 801bf3e: f1a2 0331 sub.w r3, r2, #49 @ 0x31 801bf42: 2b08 cmp r3, #8 801bf44: f200 84c6 bhi.w 801c8d4 <_strtod_l+0xb94> 801bf48: 9006 str r0, [sp, #24] 801bf4a: 9d17 ldr r5, [sp, #92] @ 0x5c 801bf4c: 2000 movs r0, #0 801bf4e: 4604 mov r4, r0 801bf50: 3a30 subs r2, #48 @ 0x30 801bf52: f100 0301 add.w r3, r0, #1 801bf56: d010 beq.n 801bf7a <_strtod_l+0x23a> 801bf58: 9906 ldr r1, [sp, #24] 801bf5a: 4419 add r1, r3 801bf5c: 9106 str r1, [sp, #24] 801bf5e: 4420 add r0, r4 801bf60: 230a movs r3, #10 801bf62: 42a0 cmp r0, r4 801bf64: d111 bne.n 801bf8a <_strtod_l+0x24a> 801bf66: 2808 cmp r0, #8 801bf68: f100 0401 add.w r4, r0, #1 801bf6c: dc19 bgt.n 801bfa2 <_strtod_l+0x262> 801bf6e: 990e ldr r1, [sp, #56] @ 0x38 801bf70: 230a movs r3, #10 801bf72: fb03 2301 mla r3, r3, r1, r2 801bf76: 930e str r3, [sp, #56] @ 0x38 801bf78: 2300 movs r3, #0 801bf7a: 9a17 ldr r2, [sp, #92] @ 0x5c 801bf7c: 1c51 adds r1, r2, #1 801bf7e: 9117 str r1, [sp, #92] @ 0x5c 801bf80: 7852 ldrb r2, [r2, #1] 801bf82: 4618 mov r0, r3 801bf84: e7cd b.n 801bf22 <_strtod_l+0x1e2> 801bf86: 4658 mov r0, fp 801bf88: e7d7 b.n 801bf3a <_strtod_l+0x1fa> 801bf8a: 2c08 cmp r4, #8 801bf8c: f104 0401 add.w r4, r4, #1 801bf90: dc03 bgt.n 801bf9a <_strtod_l+0x25a> 801bf92: 990e ldr r1, [sp, #56] @ 0x38 801bf94: 4359 muls r1, r3 801bf96: 910e str r1, [sp, #56] @ 0x38 801bf98: e7e3 b.n 801bf62 <_strtod_l+0x222> 801bf9a: 2c10 cmp r4, #16 801bf9c: bfd8 it le 801bf9e: 435f mulle r7, r3 801bfa0: e7df b.n 801bf62 <_strtod_l+0x222> 801bfa2: 280f cmp r0, #15 801bfa4: bfdc itt le 801bfa6: 230a movle r3, #10 801bfa8: fb03 2707 mlale r7, r3, r7, r2 801bfac: e7e4 b.n 801bf78 <_strtod_l+0x238> 801bfae: 2100 movs r1, #0 801bfb0: 2301 movs r3, #1 801bfb2: e9cd 1306 strd r1, r3, [sp, #24] 801bfb6: e780 b.n 801beba <_strtod_l+0x17a> 801bfb8: f04f 0c00 mov.w ip, #0 801bfbc: 1cb3 adds r3, r6, #2 801bfbe: 9317 str r3, [sp, #92] @ 0x5c 801bfc0: 78b2 ldrb r2, [r6, #2] 801bfc2: e789 b.n 801bed8 <_strtod_l+0x198> 801bfc4: f04f 0c01 mov.w ip, #1 801bfc8: e7f8 b.n 801bfbc <_strtod_l+0x27c> 801bfca: bf00 nop 801bfcc: 0801e8dc .word 0x0801e8dc 801bfd0: 0801e70f .word 0x0801e70f 801bfd4: 7ff00000 .word 0x7ff00000 801bfd8: 9b17 ldr r3, [sp, #92] @ 0x5c 801bfda: 1c5a adds r2, r3, #1 801bfdc: 9217 str r2, [sp, #92] @ 0x5c 801bfde: 785a ldrb r2, [r3, #1] 801bfe0: 2a30 cmp r2, #48 @ 0x30 801bfe2: d0f9 beq.n 801bfd8 <_strtod_l+0x298> 801bfe4: f1a2 0331 sub.w r3, r2, #49 @ 0x31 801bfe8: 2b08 cmp r3, #8 801bfea: f63f af7a bhi.w 801bee2 <_strtod_l+0x1a2> 801bfee: 9b17 ldr r3, [sp, #92] @ 0x5c 801bff0: 9305 str r3, [sp, #20] 801bff2: f1a2 0e30 sub.w lr, r2, #48 @ 0x30 801bff6: 3301 adds r3, #1 801bff8: 9317 str r3, [sp, #92] @ 0x5c 801bffa: 781a ldrb r2, [r3, #0] 801bffc: f1a2 0130 sub.w r1, r2, #48 @ 0x30 801c000: 2909 cmp r1, #9 801c002: d93c bls.n 801c07e <_strtod_l+0x33e> 801c004: 9905 ldr r1, [sp, #20] 801c006: 1a5b subs r3, r3, r1 801c008: 2b08 cmp r3, #8 801c00a: f644 631f movw r3, #19999 @ 0x4e1f 801c00e: dc3c bgt.n 801c08a <_strtod_l+0x34a> 801c010: 459e cmp lr, r3 801c012: 4671 mov r1, lr 801c014: bfa8 it ge 801c016: 4619 movge r1, r3 801c018: 9105 str r1, [sp, #20] 801c01a: f1bc 0f00 cmp.w ip, #0 801c01e: d002 beq.n 801c026 <_strtod_l+0x2e6> 801c020: 9b05 ldr r3, [sp, #20] 801c022: 425b negs r3, r3 801c024: 9305 str r3, [sp, #20] 801c026: 2c00 cmp r4, #0 801c028: d150 bne.n 801c0cc <_strtod_l+0x38c> 801c02a: ea5a 0000 orrs.w r0, sl, r0 801c02e: f47f aed9 bne.w 801bde4 <_strtod_l+0xa4> 801c032: 9b07 ldr r3, [sp, #28] 801c034: 2b00 cmp r3, #0 801c036: f47f aeac bne.w 801bd92 <_strtod_l+0x52> 801c03a: 2a69 cmp r2, #105 @ 0x69 801c03c: d029 beq.n 801c092 <_strtod_l+0x352> 801c03e: dc26 bgt.n 801c08e <_strtod_l+0x34e> 801c040: 2a49 cmp r2, #73 @ 0x49 801c042: d026 beq.n 801c092 <_strtod_l+0x352> 801c044: 2a4e cmp r2, #78 @ 0x4e 801c046: f47f aea4 bne.w 801bd92 <_strtod_l+0x52> 801c04a: 49a1 ldr r1, [pc, #644] @ (801c2d0 <_strtod_l+0x590>) 801c04c: a817 add r0, sp, #92 @ 0x5c 801c04e: f001 fba7 bl 801d7a0 <__match> 801c052: 2800 cmp r0, #0 801c054: f43f ae9d beq.w 801bd92 <_strtod_l+0x52> 801c058: 9b17 ldr r3, [sp, #92] @ 0x5c 801c05a: 781b ldrb r3, [r3, #0] 801c05c: 2b28 cmp r3, #40 @ 0x28 801c05e: d12f bne.n 801c0c0 <_strtod_l+0x380> 801c060: 499c ldr r1, [pc, #624] @ (801c2d4 <_strtod_l+0x594>) 801c062: aa1a add r2, sp, #104 @ 0x68 801c064: a817 add r0, sp, #92 @ 0x5c 801c066: f001 fbaf bl 801d7c8 <__hexnan> 801c06a: 2805 cmp r0, #5 801c06c: d128 bne.n 801c0c0 <_strtod_l+0x380> 801c06e: 9b1b ldr r3, [sp, #108] @ 0x6c 801c070: f8dd 8068 ldr.w r8, [sp, #104] @ 0x68 801c074: f043 49ff orr.w r9, r3, #2139095040 @ 0x7f800000 801c078: f449 09e0 orr.w r9, r9, #7340032 @ 0x700000 801c07c: e6b2 b.n 801bde4 <_strtod_l+0xa4> 801c07e: 210a movs r1, #10 801c080: fb01 220e mla r2, r1, lr, r2 801c084: f1a2 0e30 sub.w lr, r2, #48 @ 0x30 801c088: e7b5 b.n 801bff6 <_strtod_l+0x2b6> 801c08a: 9305 str r3, [sp, #20] 801c08c: e7c5 b.n 801c01a <_strtod_l+0x2da> 801c08e: 2a6e cmp r2, #110 @ 0x6e 801c090: e7d9 b.n 801c046 <_strtod_l+0x306> 801c092: 4991 ldr r1, [pc, #580] @ (801c2d8 <_strtod_l+0x598>) 801c094: a817 add r0, sp, #92 @ 0x5c 801c096: f001 fb83 bl 801d7a0 <__match> 801c09a: 2800 cmp r0, #0 801c09c: f43f ae79 beq.w 801bd92 <_strtod_l+0x52> 801c0a0: 9b17 ldr r3, [sp, #92] @ 0x5c 801c0a2: 498e ldr r1, [pc, #568] @ (801c2dc <_strtod_l+0x59c>) 801c0a4: 3b01 subs r3, #1 801c0a6: a817 add r0, sp, #92 @ 0x5c 801c0a8: 9317 str r3, [sp, #92] @ 0x5c 801c0aa: f001 fb79 bl 801d7a0 <__match> 801c0ae: b910 cbnz r0, 801c0b6 <_strtod_l+0x376> 801c0b0: 9b17 ldr r3, [sp, #92] @ 0x5c 801c0b2: 3301 adds r3, #1 801c0b4: 9317 str r3, [sp, #92] @ 0x5c 801c0b6: f8df 9234 ldr.w r9, [pc, #564] @ 801c2ec <_strtod_l+0x5ac> 801c0ba: f04f 0800 mov.w r8, #0 801c0be: e691 b.n 801bde4 <_strtod_l+0xa4> 801c0c0: 4887 ldr r0, [pc, #540] @ (801c2e0 <_strtod_l+0x5a0>) 801c0c2: f001 f8a9 bl 801d218 801c0c6: ec59 8b10 vmov r8, r9, d0 801c0ca: e68b b.n 801bde4 <_strtod_l+0xa4> 801c0cc: e9dd 3205 ldrd r3, r2, [sp, #20] 801c0d0: 980e ldr r0, [sp, #56] @ 0x38 801c0d2: 1a9b subs r3, r3, r2 801c0d4: f1bb 0f00 cmp.w fp, #0 801c0d8: bf08 it eq 801c0da: 46a3 moveq fp, r4 801c0dc: 2c10 cmp r4, #16 801c0de: 930a str r3, [sp, #40] @ 0x28 801c0e0: 46a2 mov sl, r4 801c0e2: bfa8 it ge 801c0e4: f04f 0a10 movge.w sl, #16 801c0e8: f7e4 f9e4 bl 80004b4 <__aeabi_ui2d> 801c0ec: 2c09 cmp r4, #9 801c0ee: 4680 mov r8, r0 801c0f0: 4689 mov r9, r1 801c0f2: dc13 bgt.n 801c11c <_strtod_l+0x3dc> 801c0f4: 9b0a ldr r3, [sp, #40] @ 0x28 801c0f6: 2b00 cmp r3, #0 801c0f8: f43f ae74 beq.w 801bde4 <_strtod_l+0xa4> 801c0fc: 9b0a ldr r3, [sp, #40] @ 0x28 801c0fe: dd73 ble.n 801c1e8 <_strtod_l+0x4a8> 801c100: 2b16 cmp r3, #22 801c102: dc5a bgt.n 801c1ba <_strtod_l+0x47a> 801c104: 4977 ldr r1, [pc, #476] @ (801c2e4 <_strtod_l+0x5a4>) 801c106: eb01 01c3 add.w r1, r1, r3, lsl #3 801c10a: e9d1 0100 ldrd r0, r1, [r1] 801c10e: 4642 mov r2, r8 801c110: 464b mov r3, r9 801c112: f7e4 fa49 bl 80005a8 <__aeabi_dmul> 801c116: 4680 mov r8, r0 801c118: 4689 mov r9, r1 801c11a: e663 b.n 801bde4 <_strtod_l+0xa4> 801c11c: 4b71 ldr r3, [pc, #452] @ (801c2e4 <_strtod_l+0x5a4>) 801c11e: eb03 03ca add.w r3, r3, sl, lsl #3 801c122: e953 2312 ldrd r2, r3, [r3, #-72] @ 0x48 801c126: f7e4 fa3f bl 80005a8 <__aeabi_dmul> 801c12a: 4680 mov r8, r0 801c12c: 4638 mov r0, r7 801c12e: 4689 mov r9, r1 801c130: f7e4 f9c0 bl 80004b4 <__aeabi_ui2d> 801c134: 4602 mov r2, r0 801c136: 460b mov r3, r1 801c138: 4640 mov r0, r8 801c13a: 4649 mov r1, r9 801c13c: f7e4 f87e bl 800023c <__adddf3> 801c140: 2c0f cmp r4, #15 801c142: 4680 mov r8, r0 801c144: 4689 mov r9, r1 801c146: ddd5 ble.n 801c0f4 <_strtod_l+0x3b4> 801c148: 9b0a ldr r3, [sp, #40] @ 0x28 801c14a: eba4 0a0a sub.w sl, r4, sl 801c14e: 449a add sl, r3 801c150: f1ba 0f00 cmp.w sl, #0 801c154: f340 8097 ble.w 801c286 <_strtod_l+0x546> 801c158: f02a 060f bic.w r6, sl, #15 801c15c: f01a 0a0f ands.w sl, sl, #15 801c160: d151 bne.n 801c206 <_strtod_l+0x4c6> 801c162: f5b6 7f9a cmp.w r6, #308 @ 0x134 801c166: dc5e bgt.n 801c226 <_strtod_l+0x4e6> 801c168: 2300 movs r3, #0 801c16a: f8df a17c ldr.w sl, [pc, #380] @ 801c2e8 <_strtod_l+0x5a8> 801c16e: 1136 asrs r6, r6, #4 801c170: 4640 mov r0, r8 801c172: 4649 mov r1, r9 801c174: 461f mov r7, r3 801c176: 2e01 cmp r6, #1 801c178: d179 bne.n 801c26e <_strtod_l+0x52e> 801c17a: b10b cbz r3, 801c180 <_strtod_l+0x440> 801c17c: 4680 mov r8, r0 801c17e: 4689 mov r9, r1 801c180: 4959 ldr r1, [pc, #356] @ (801c2e8 <_strtod_l+0x5a8>) 801c182: f1a9 7954 sub.w r9, r9, #55574528 @ 0x3500000 801c186: eb01 01c7 add.w r1, r1, r7, lsl #3 801c18a: 4642 mov r2, r8 801c18c: 464b mov r3, r9 801c18e: e9d1 0100 ldrd r0, r1, [r1] 801c192: f7e4 fa09 bl 80005a8 <__aeabi_dmul> 801c196: 4b55 ldr r3, [pc, #340] @ (801c2ec <_strtod_l+0x5ac>) 801c198: 460a mov r2, r1 801c19a: 400b ands r3, r1 801c19c: 4954 ldr r1, [pc, #336] @ (801c2f0 <_strtod_l+0x5b0>) 801c19e: 428b cmp r3, r1 801c1a0: 4680 mov r8, r0 801c1a2: d840 bhi.n 801c226 <_strtod_l+0x4e6> 801c1a4: f5a1 1180 sub.w r1, r1, #1048576 @ 0x100000 801c1a8: 428b cmp r3, r1 801c1aa: bf86 itte hi 801c1ac: f8df 9144 ldrhi.w r9, [pc, #324] @ 801c2f4 <_strtod_l+0x5b4> 801c1b0: f04f 38ff movhi.w r8, #4294967295 @ 0xffffffff 801c1b4: f102 7954 addls.w r9, r2, #55574528 @ 0x3500000 801c1b8: e032 b.n 801c220 <_strtod_l+0x4e0> 801c1ba: 9a0a ldr r2, [sp, #40] @ 0x28 801c1bc: f1c4 0325 rsb r3, r4, #37 @ 0x25 801c1c0: 4293 cmp r3, r2 801c1c2: dbc1 blt.n 801c148 <_strtod_l+0x408> 801c1c4: 4d47 ldr r5, [pc, #284] @ (801c2e4 <_strtod_l+0x5a4>) 801c1c6: f1c4 040f rsb r4, r4, #15 801c1ca: eb05 01c4 add.w r1, r5, r4, lsl #3 801c1ce: 4642 mov r2, r8 801c1d0: 464b mov r3, r9 801c1d2: e9d1 0100 ldrd r0, r1, [r1] 801c1d6: f7e4 f9e7 bl 80005a8 <__aeabi_dmul> 801c1da: 9b0a ldr r3, [sp, #40] @ 0x28 801c1dc: 1b1c subs r4, r3, r4 801c1de: eb05 05c4 add.w r5, r5, r4, lsl #3 801c1e2: e9d5 2300 ldrd r2, r3, [r5] 801c1e6: e794 b.n 801c112 <_strtod_l+0x3d2> 801c1e8: 3316 adds r3, #22 801c1ea: dbad blt.n 801c148 <_strtod_l+0x408> 801c1ec: e9dd 2305 ldrd r2, r3, [sp, #20] 801c1f0: 1a9a subs r2, r3, r2 801c1f2: 4b3c ldr r3, [pc, #240] @ (801c2e4 <_strtod_l+0x5a4>) 801c1f4: eb03 03c2 add.w r3, r3, r2, lsl #3 801c1f8: e9d3 2300 ldrd r2, r3, [r3] 801c1fc: 4640 mov r0, r8 801c1fe: 4649 mov r1, r9 801c200: f7e4 fafc bl 80007fc <__aeabi_ddiv> 801c204: e787 b.n 801c116 <_strtod_l+0x3d6> 801c206: 4937 ldr r1, [pc, #220] @ (801c2e4 <_strtod_l+0x5a4>) 801c208: eb01 01ca add.w r1, r1, sl, lsl #3 801c20c: 4642 mov r2, r8 801c20e: 464b mov r3, r9 801c210: e9d1 0100 ldrd r0, r1, [r1] 801c214: f7e4 f9c8 bl 80005a8 <__aeabi_dmul> 801c218: 4680 mov r8, r0 801c21a: 4689 mov r9, r1 801c21c: 2e00 cmp r6, #0 801c21e: d1a0 bne.n 801c162 <_strtod_l+0x422> 801c220: 2300 movs r3, #0 801c222: 9307 str r3, [sp, #28] 801c224: e0a0 b.n 801c368 <_strtod_l+0x628> 801c226: 2400 movs r4, #0 801c228: 9405 str r4, [sp, #20] 801c22a: 940e str r4, [sp, #56] @ 0x38 801c22c: 9406 str r4, [sp, #24] 801c22e: 9a04 ldr r2, [sp, #16] 801c230: f8df 90b8 ldr.w r9, [pc, #184] @ 801c2ec <_strtod_l+0x5ac> 801c234: 2322 movs r3, #34 @ 0x22 801c236: 6013 str r3, [r2, #0] 801c238: f04f 0800 mov.w r8, #0 801c23c: 9b0e ldr r3, [sp, #56] @ 0x38 801c23e: 2b00 cmp r3, #0 801c240: f43f add0 beq.w 801bde4 <_strtod_l+0xa4> 801c244: 9918 ldr r1, [sp, #96] @ 0x60 801c246: 9804 ldr r0, [sp, #16] 801c248: f7ff f8e0 bl 801b40c <_Bfree> 801c24c: 9906 ldr r1, [sp, #24] 801c24e: 9804 ldr r0, [sp, #16] 801c250: f7ff f8dc bl 801b40c <_Bfree> 801c254: e9dd 0104 ldrd r0, r1, [sp, #16] 801c258: f7ff f8d8 bl 801b40c <_Bfree> 801c25c: 990e ldr r1, [sp, #56] @ 0x38 801c25e: 9804 ldr r0, [sp, #16] 801c260: f7ff f8d4 bl 801b40c <_Bfree> 801c264: 9804 ldr r0, [sp, #16] 801c266: 4621 mov r1, r4 801c268: f7ff f8d0 bl 801b40c <_Bfree> 801c26c: e5ba b.n 801bde4 <_strtod_l+0xa4> 801c26e: 07f2 lsls r2, r6, #31 801c270: d504 bpl.n 801c27c <_strtod_l+0x53c> 801c272: e9da 2300 ldrd r2, r3, [sl] 801c276: f7e4 f997 bl 80005a8 <__aeabi_dmul> 801c27a: 2301 movs r3, #1 801c27c: 3701 adds r7, #1 801c27e: 1076 asrs r6, r6, #1 801c280: f10a 0a08 add.w sl, sl, #8 801c284: e777 b.n 801c176 <_strtod_l+0x436> 801c286: d0cb beq.n 801c220 <_strtod_l+0x4e0> 801c288: f1ca 0a00 rsb sl, sl, #0 801c28c: ea4f 162a mov.w r6, sl, asr #4 801c290: f01a 0a0f ands.w sl, sl, #15 801c294: d10d bne.n 801c2b2 <_strtod_l+0x572> 801c296: 2e1f cmp r6, #31 801c298: dd2e ble.n 801c2f8 <_strtod_l+0x5b8> 801c29a: 2400 movs r4, #0 801c29c: 9405 str r4, [sp, #20] 801c29e: 940e str r4, [sp, #56] @ 0x38 801c2a0: 9406 str r4, [sp, #24] 801c2a2: 9a04 ldr r2, [sp, #16] 801c2a4: 2322 movs r3, #34 @ 0x22 801c2a6: f04f 0800 mov.w r8, #0 801c2aa: f04f 0900 mov.w r9, #0 801c2ae: 6013 str r3, [r2, #0] 801c2b0: e7c4 b.n 801c23c <_strtod_l+0x4fc> 801c2b2: 4b0c ldr r3, [pc, #48] @ (801c2e4 <_strtod_l+0x5a4>) 801c2b4: eb03 03ca add.w r3, r3, sl, lsl #3 801c2b8: 4640 mov r0, r8 801c2ba: 4649 mov r1, r9 801c2bc: e9d3 2300 ldrd r2, r3, [r3] 801c2c0: f7e4 fa9c bl 80007fc <__aeabi_ddiv> 801c2c4: 4680 mov r8, r0 801c2c6: 4689 mov r9, r1 801c2c8: 2e00 cmp r6, #0 801c2ca: d0a9 beq.n 801c220 <_strtod_l+0x4e0> 801c2cc: e7e3 b.n 801c296 <_strtod_l+0x556> 801c2ce: bf00 nop 801c2d0: 0801e5fd .word 0x0801e5fd 801c2d4: 0801e8c8 .word 0x0801e8c8 801c2d8: 0801e5f5 .word 0x0801e5f5 801c2dc: 0801e62c .word 0x0801e62c 801c2e0: 0801e765 .word 0x0801e765 801c2e4: 0801e800 .word 0x0801e800 801c2e8: 0801e7d8 .word 0x0801e7d8 801c2ec: 7ff00000 .word 0x7ff00000 801c2f0: 7ca00000 .word 0x7ca00000 801c2f4: 7fefffff .word 0x7fefffff 801c2f8: f016 0310 ands.w r3, r6, #16 801c2fc: bf18 it ne 801c2fe: 236a movne r3, #106 @ 0x6a 801c300: 4f76 ldr r7, [pc, #472] @ (801c4dc <_strtod_l+0x79c>) 801c302: 9307 str r3, [sp, #28] 801c304: 4640 mov r0, r8 801c306: 4649 mov r1, r9 801c308: 2300 movs r3, #0 801c30a: 07f2 lsls r2, r6, #31 801c30c: d504 bpl.n 801c318 <_strtod_l+0x5d8> 801c30e: e9d7 2300 ldrd r2, r3, [r7] 801c312: f7e4 f949 bl 80005a8 <__aeabi_dmul> 801c316: 2301 movs r3, #1 801c318: 1076 asrs r6, r6, #1 801c31a: f107 0708 add.w r7, r7, #8 801c31e: d1f4 bne.n 801c30a <_strtod_l+0x5ca> 801c320: b10b cbz r3, 801c326 <_strtod_l+0x5e6> 801c322: 4680 mov r8, r0 801c324: 4689 mov r9, r1 801c326: 9b07 ldr r3, [sp, #28] 801c328: b1b3 cbz r3, 801c358 <_strtod_l+0x618> 801c32a: f3c9 520a ubfx r2, r9, #20, #11 801c32e: f1c2 036b rsb r3, r2, #107 @ 0x6b 801c332: 2b00 cmp r3, #0 801c334: 4649 mov r1, r9 801c336: dd0f ble.n 801c358 <_strtod_l+0x618> 801c338: 2b1f cmp r3, #31 801c33a: dd57 ble.n 801c3ec <_strtod_l+0x6ac> 801c33c: 2b34 cmp r3, #52 @ 0x34 801c33e: bfde ittt le 801c340: f04f 33ff movle.w r3, #4294967295 @ 0xffffffff 801c344: f1c2 024b rsble r2, r2, #75 @ 0x4b 801c348: 4093 lslle r3, r2 801c34a: f04f 0800 mov.w r8, #0 801c34e: bfcc ite gt 801c350: f04f 795c movgt.w r9, #57671680 @ 0x3700000 801c354: ea03 0901 andle.w r9, r3, r1 801c358: 2200 movs r2, #0 801c35a: 2300 movs r3, #0 801c35c: 4640 mov r0, r8 801c35e: 4649 mov r1, r9 801c360: f7e4 fb8a bl 8000a78 <__aeabi_dcmpeq> 801c364: 2800 cmp r0, #0 801c366: d198 bne.n 801c29a <_strtod_l+0x55a> 801c368: 9b0e ldr r3, [sp, #56] @ 0x38 801c36a: 9300 str r3, [sp, #0] 801c36c: 9804 ldr r0, [sp, #16] 801c36e: 4623 mov r3, r4 801c370: 465a mov r2, fp 801c372: 4629 mov r1, r5 801c374: f7ff f8b2 bl 801b4dc <__s2b> 801c378: 900e str r0, [sp, #56] @ 0x38 801c37a: 2800 cmp r0, #0 801c37c: f43f af53 beq.w 801c226 <_strtod_l+0x4e6> 801c380: e9dd 2305 ldrd r2, r3, [sp, #20] 801c384: 1a9b subs r3, r3, r2 801c386: 9a0a ldr r2, [sp, #40] @ 0x28 801c388: 2a00 cmp r2, #0 801c38a: bfa8 it ge 801c38c: 2300 movge r3, #0 801c38e: 9312 str r3, [sp, #72] @ 0x48 801c390: 2400 movs r4, #0 801c392: ea22 73e2 bic.w r3, r2, r2, asr #31 801c396: 9314 str r3, [sp, #80] @ 0x50 801c398: 9405 str r4, [sp, #20] 801c39a: 9b0e ldr r3, [sp, #56] @ 0x38 801c39c: 9804 ldr r0, [sp, #16] 801c39e: 6859 ldr r1, [r3, #4] 801c3a0: f7fe fff6 bl 801b390 <_Balloc> 801c3a4: 9006 str r0, [sp, #24] 801c3a6: 2800 cmp r0, #0 801c3a8: f43f af41 beq.w 801c22e <_strtod_l+0x4ee> 801c3ac: 9b0e ldr r3, [sp, #56] @ 0x38 801c3ae: 691a ldr r2, [r3, #16] 801c3b0: 3202 adds r2, #2 801c3b2: f103 010c add.w r1, r3, #12 801c3b6: 0092 lsls r2, r2, #2 801c3b8: 300c adds r0, #12 801c3ba: f7fe f870 bl 801a49e 801c3be: ec49 8b10 vmov d0, r8, r9 801c3c2: 9804 ldr r0, [sp, #16] 801c3c4: aa1a add r2, sp, #104 @ 0x68 801c3c6: a919 add r1, sp, #100 @ 0x64 801c3c8: e9cd 890c strd r8, r9, [sp, #48] @ 0x30 801c3cc: f7ff fbca bl 801bb64 <__d2b> 801c3d0: 9018 str r0, [sp, #96] @ 0x60 801c3d2: 2800 cmp r0, #0 801c3d4: f43f af2b beq.w 801c22e <_strtod_l+0x4ee> 801c3d8: 9804 ldr r0, [sp, #16] 801c3da: 2101 movs r1, #1 801c3dc: f7ff f914 bl 801b608 <__i2b> 801c3e0: 9005 str r0, [sp, #20] 801c3e2: 4603 mov r3, r0 801c3e4: b948 cbnz r0, 801c3fa <_strtod_l+0x6ba> 801c3e6: 2300 movs r3, #0 801c3e8: 9305 str r3, [sp, #20] 801c3ea: e720 b.n 801c22e <_strtod_l+0x4ee> 801c3ec: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801c3f0: fa02 f303 lsl.w r3, r2, r3 801c3f4: ea03 0808 and.w r8, r3, r8 801c3f8: e7ae b.n 801c358 <_strtod_l+0x618> 801c3fa: 9d19 ldr r5, [sp, #100] @ 0x64 801c3fc: 9a1a ldr r2, [sp, #104] @ 0x68 801c3fe: 2d00 cmp r5, #0 801c400: bfab itete ge 801c402: 9b12 ldrge r3, [sp, #72] @ 0x48 801c404: 9b14 ldrlt r3, [sp, #80] @ 0x50 801c406: 9e14 ldrge r6, [sp, #80] @ 0x50 801c408: 9f12 ldrlt r7, [sp, #72] @ 0x48 801c40a: bfac ite ge 801c40c: 18ef addge r7, r5, r3 801c40e: 1b5e sublt r6, r3, r5 801c410: 9b07 ldr r3, [sp, #28] 801c412: 1aed subs r5, r5, r3 801c414: 4415 add r5, r2 801c416: 4b32 ldr r3, [pc, #200] @ (801c4e0 <_strtod_l+0x7a0>) 801c418: 3d01 subs r5, #1 801c41a: 429d cmp r5, r3 801c41c: f1c2 0236 rsb r2, r2, #54 @ 0x36 801c420: da4f bge.n 801c4c2 <_strtod_l+0x782> 801c422: 1b5b subs r3, r3, r5 801c424: 2b1f cmp r3, #31 801c426: eba2 0203 sub.w r2, r2, r3 801c42a: f04f 0101 mov.w r1, #1 801c42e: dc3c bgt.n 801c4aa <_strtod_l+0x76a> 801c430: fa01 fa03 lsl.w sl, r1, r3 801c434: f04f 0b00 mov.w fp, #0 801c438: 18bd adds r5, r7, r2 801c43a: 9b07 ldr r3, [sp, #28] 801c43c: 42af cmp r7, r5 801c43e: 4416 add r6, r2 801c440: 441e add r6, r3 801c442: 463b mov r3, r7 801c444: bfa8 it ge 801c446: 462b movge r3, r5 801c448: 42b3 cmp r3, r6 801c44a: bfa8 it ge 801c44c: 4633 movge r3, r6 801c44e: 2b00 cmp r3, #0 801c450: bfc2 ittt gt 801c452: 1aed subgt r5, r5, r3 801c454: 1af6 subgt r6, r6, r3 801c456: 1aff subgt r7, r7, r3 801c458: 9b12 ldr r3, [sp, #72] @ 0x48 801c45a: 2b00 cmp r3, #0 801c45c: dd16 ble.n 801c48c <_strtod_l+0x74c> 801c45e: e9dd 0104 ldrd r0, r1, [sp, #16] 801c462: 461a mov r2, r3 801c464: f7ff f990 bl 801b788 <__pow5mult> 801c468: 9005 str r0, [sp, #20] 801c46a: 2800 cmp r0, #0 801c46c: d0bb beq.n 801c3e6 <_strtod_l+0x6a6> 801c46e: 4601 mov r1, r0 801c470: 9a18 ldr r2, [sp, #96] @ 0x60 801c472: 9804 ldr r0, [sp, #16] 801c474: f7ff f8de bl 801b634 <__multiply> 801c478: 900f str r0, [sp, #60] @ 0x3c 801c47a: 2800 cmp r0, #0 801c47c: f43f aed7 beq.w 801c22e <_strtod_l+0x4ee> 801c480: 9918 ldr r1, [sp, #96] @ 0x60 801c482: 9804 ldr r0, [sp, #16] 801c484: f7fe ffc2 bl 801b40c <_Bfree> 801c488: 9b0f ldr r3, [sp, #60] @ 0x3c 801c48a: 9318 str r3, [sp, #96] @ 0x60 801c48c: 2d00 cmp r5, #0 801c48e: dc1b bgt.n 801c4c8 <_strtod_l+0x788> 801c490: 9b0a ldr r3, [sp, #40] @ 0x28 801c492: 2b00 cmp r3, #0 801c494: dd26 ble.n 801c4e4 <_strtod_l+0x7a4> 801c496: 9a14 ldr r2, [sp, #80] @ 0x50 801c498: 9906 ldr r1, [sp, #24] 801c49a: 9804 ldr r0, [sp, #16] 801c49c: f7ff f974 bl 801b788 <__pow5mult> 801c4a0: 9006 str r0, [sp, #24] 801c4a2: b9f8 cbnz r0, 801c4e4 <_strtod_l+0x7a4> 801c4a4: 2300 movs r3, #0 801c4a6: 9306 str r3, [sp, #24] 801c4a8: e6c1 b.n 801c22e <_strtod_l+0x4ee> 801c4aa: f1c5 457f rsb r5, r5, #4278190080 @ 0xff000000 801c4ae: f505 057f add.w r5, r5, #16711680 @ 0xff0000 801c4b2: f505 457b add.w r5, r5, #64256 @ 0xfb00 801c4b6: 35e2 adds r5, #226 @ 0xe2 801c4b8: fa01 fb05 lsl.w fp, r1, r5 801c4bc: f04f 0a01 mov.w sl, #1 801c4c0: e7ba b.n 801c438 <_strtod_l+0x6f8> 801c4c2: f04f 0b00 mov.w fp, #0 801c4c6: e7f9 b.n 801c4bc <_strtod_l+0x77c> 801c4c8: 9918 ldr r1, [sp, #96] @ 0x60 801c4ca: 9804 ldr r0, [sp, #16] 801c4cc: 462a mov r2, r5 801c4ce: f7ff f9b7 bl 801b840 <__lshift> 801c4d2: 9018 str r0, [sp, #96] @ 0x60 801c4d4: 2800 cmp r0, #0 801c4d6: d1db bne.n 801c490 <_strtod_l+0x750> 801c4d8: e6a9 b.n 801c22e <_strtod_l+0x4ee> 801c4da: bf00 nop 801c4dc: 0801e8f0 .word 0x0801e8f0 801c4e0: fffffc02 .word 0xfffffc02 801c4e4: 2e00 cmp r6, #0 801c4e6: dd07 ble.n 801c4f8 <_strtod_l+0x7b8> 801c4e8: 9906 ldr r1, [sp, #24] 801c4ea: 9804 ldr r0, [sp, #16] 801c4ec: 4632 mov r2, r6 801c4ee: f7ff f9a7 bl 801b840 <__lshift> 801c4f2: 9006 str r0, [sp, #24] 801c4f4: 2800 cmp r0, #0 801c4f6: d0d5 beq.n 801c4a4 <_strtod_l+0x764> 801c4f8: 2f00 cmp r7, #0 801c4fa: dd08 ble.n 801c50e <_strtod_l+0x7ce> 801c4fc: e9dd 0104 ldrd r0, r1, [sp, #16] 801c500: 463a mov r2, r7 801c502: f7ff f99d bl 801b840 <__lshift> 801c506: 9005 str r0, [sp, #20] 801c508: 2800 cmp r0, #0 801c50a: f43f ae90 beq.w 801c22e <_strtod_l+0x4ee> 801c50e: 9a06 ldr r2, [sp, #24] 801c510: 9918 ldr r1, [sp, #96] @ 0x60 801c512: 9804 ldr r0, [sp, #16] 801c514: f7ff fa1e bl 801b954 <__mdiff> 801c518: 4604 mov r4, r0 801c51a: 2800 cmp r0, #0 801c51c: f43f ae87 beq.w 801c22e <_strtod_l+0x4ee> 801c520: 68c3 ldr r3, [r0, #12] 801c522: 930f str r3, [sp, #60] @ 0x3c 801c524: 2300 movs r3, #0 801c526: 9905 ldr r1, [sp, #20] 801c528: 60c3 str r3, [r0, #12] 801c52a: f7ff f9f7 bl 801b91c <__mcmp> 801c52e: 2800 cmp r0, #0 801c530: da3c bge.n 801c5ac <_strtod_l+0x86c> 801c532: 9b0f ldr r3, [sp, #60] @ 0x3c 801c534: ea53 0308 orrs.w r3, r3, r8 801c538: d15e bne.n 801c5f8 <_strtod_l+0x8b8> 801c53a: f3c9 0313 ubfx r3, r9, #0, #20 801c53e: 464d mov r5, r9 801c540: 2b00 cmp r3, #0 801c542: d159 bne.n 801c5f8 <_strtod_l+0x8b8> 801c544: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 801c548: 0d1b lsrs r3, r3, #20 801c54a: 051b lsls r3, r3, #20 801c54c: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000 801c550: d952 bls.n 801c5f8 <_strtod_l+0x8b8> 801c552: 6963 ldr r3, [r4, #20] 801c554: b913 cbnz r3, 801c55c <_strtod_l+0x81c> 801c556: 6923 ldr r3, [r4, #16] 801c558: 2b01 cmp r3, #1 801c55a: dd4d ble.n 801c5f8 <_strtod_l+0x8b8> 801c55c: 4621 mov r1, r4 801c55e: 2201 movs r2, #1 801c560: 9804 ldr r0, [sp, #16] 801c562: f7ff f96d bl 801b840 <__lshift> 801c566: 9905 ldr r1, [sp, #20] 801c568: 4604 mov r4, r0 801c56a: f7ff f9d7 bl 801b91c <__mcmp> 801c56e: 2800 cmp r0, #0 801c570: dd42 ble.n 801c5f8 <_strtod_l+0x8b8> 801c572: 4bad ldr r3, [pc, #692] @ (801c828 <_strtod_l+0xae8>) 801c574: 9a07 ldr r2, [sp, #28] 801c576: 402b ands r3, r5 801c578: 2a00 cmp r2, #0 801c57a: d05f beq.n 801c63c <_strtod_l+0x8fc> 801c57c: f1b3 6fd6 cmp.w r3, #112197632 @ 0x6b00000 801c580: d85c bhi.n 801c63c <_strtod_l+0x8fc> 801c582: f1b3 7f5c cmp.w r3, #57671680 @ 0x3700000 801c586: f67f ae8c bls.w 801c2a2 <_strtod_l+0x562> 801c58a: 4ba8 ldr r3, [pc, #672] @ (801c82c <_strtod_l+0xaec>) 801c58c: 4640 mov r0, r8 801c58e: 4649 mov r1, r9 801c590: 2200 movs r2, #0 801c592: f7e4 f809 bl 80005a8 <__aeabi_dmul> 801c596: 4ba4 ldr r3, [pc, #656] @ (801c828 <_strtod_l+0xae8>) 801c598: 400b ands r3, r1 801c59a: 4680 mov r8, r0 801c59c: 4689 mov r9, r1 801c59e: 2b00 cmp r3, #0 801c5a0: f47f ae50 bne.w 801c244 <_strtod_l+0x504> 801c5a4: 9a04 ldr r2, [sp, #16] 801c5a6: 2322 movs r3, #34 @ 0x22 801c5a8: 6013 str r3, [r2, #0] 801c5aa: e64b b.n 801c244 <_strtod_l+0x504> 801c5ac: 464d mov r5, r9 801c5ae: d162 bne.n 801c676 <_strtod_l+0x936> 801c5b0: 9a0f ldr r2, [sp, #60] @ 0x3c 801c5b2: f3c9 0313 ubfx r3, r9, #0, #20 801c5b6: b342 cbz r2, 801c60a <_strtod_l+0x8ca> 801c5b8: 4a9d ldr r2, [pc, #628] @ (801c830 <_strtod_l+0xaf0>) 801c5ba: 4293 cmp r3, r2 801c5bc: d128 bne.n 801c610 <_strtod_l+0x8d0> 801c5be: 9b07 ldr r3, [sp, #28] 801c5c0: 4641 mov r1, r8 801c5c2: b1eb cbz r3, 801c600 <_strtod_l+0x8c0> 801c5c4: 4b98 ldr r3, [pc, #608] @ (801c828 <_strtod_l+0xae8>) 801c5c6: 402b ands r3, r5 801c5c8: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000 801c5cc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801c5d0: d819 bhi.n 801c606 <_strtod_l+0x8c6> 801c5d2: 0d1b lsrs r3, r3, #20 801c5d4: f1c3 036b rsb r3, r3, #107 @ 0x6b 801c5d8: fa02 f303 lsl.w r3, r2, r3 801c5dc: 4299 cmp r1, r3 801c5de: d117 bne.n 801c610 <_strtod_l+0x8d0> 801c5e0: 4b94 ldr r3, [pc, #592] @ (801c834 <_strtod_l+0xaf4>) 801c5e2: 429d cmp r5, r3 801c5e4: d102 bne.n 801c5ec <_strtod_l+0x8ac> 801c5e6: 3101 adds r1, #1 801c5e8: f43f ae21 beq.w 801c22e <_strtod_l+0x4ee> 801c5ec: 4b8e ldr r3, [pc, #568] @ (801c828 <_strtod_l+0xae8>) 801c5ee: 402b ands r3, r5 801c5f0: f503 1980 add.w r9, r3, #1048576 @ 0x100000 801c5f4: f04f 0800 mov.w r8, #0 801c5f8: 9b07 ldr r3, [sp, #28] 801c5fa: 2b00 cmp r3, #0 801c5fc: d1c5 bne.n 801c58a <_strtod_l+0x84a> 801c5fe: e621 b.n 801c244 <_strtod_l+0x504> 801c600: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801c604: e7ea b.n 801c5dc <_strtod_l+0x89c> 801c606: 4613 mov r3, r2 801c608: e7e8 b.n 801c5dc <_strtod_l+0x89c> 801c60a: ea53 0308 orrs.w r3, r3, r8 801c60e: d0b0 beq.n 801c572 <_strtod_l+0x832> 801c610: f1bb 0f00 cmp.w fp, #0 801c614: d01b beq.n 801c64e <_strtod_l+0x90e> 801c616: ea1b 0f05 tst.w fp, r5 801c61a: d0ed beq.n 801c5f8 <_strtod_l+0x8b8> 801c61c: 9b0f ldr r3, [sp, #60] @ 0x3c 801c61e: 9a07 ldr r2, [sp, #28] 801c620: 4640 mov r0, r8 801c622: 4649 mov r1, r9 801c624: b1b3 cbz r3, 801c654 <_strtod_l+0x914> 801c626: f7ff fb6b bl 801bd00 801c62a: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801c62e: ec53 2b10 vmov r2, r3, d0 801c632: f7e3 fe03 bl 800023c <__adddf3> 801c636: 4680 mov r8, r0 801c638: 4689 mov r9, r1 801c63a: e7dd b.n 801c5f8 <_strtod_l+0x8b8> 801c63c: f5a3 1380 sub.w r3, r3, #1048576 @ 0x100000 801c640: ea6f 5913 mvn.w r9, r3, lsr #20 801c644: ea6f 5909 mvn.w r9, r9, lsl #20 801c648: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff 801c64c: e7d4 b.n 801c5f8 <_strtod_l+0x8b8> 801c64e: ea1a 0f08 tst.w sl, r8 801c652: e7e2 b.n 801c61a <_strtod_l+0x8da> 801c654: f7ff fb54 bl 801bd00 801c658: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 801c65c: ec53 2b10 vmov r2, r3, d0 801c660: f7e3 fdea bl 8000238 <__aeabi_dsub> 801c664: 2200 movs r2, #0 801c666: 2300 movs r3, #0 801c668: 4680 mov r8, r0 801c66a: 4689 mov r9, r1 801c66c: f7e4 fa04 bl 8000a78 <__aeabi_dcmpeq> 801c670: 2800 cmp r0, #0 801c672: d0c1 beq.n 801c5f8 <_strtod_l+0x8b8> 801c674: e615 b.n 801c2a2 <_strtod_l+0x562> 801c676: 9905 ldr r1, [sp, #20] 801c678: 4620 mov r0, r4 801c67a: f7ff facb bl 801bc14 <__ratio> 801c67e: ec57 6b10 vmov r6, r7, d0 801c682: 2200 movs r2, #0 801c684: f04f 4380 mov.w r3, #1073741824 @ 0x40000000 801c688: 4630 mov r0, r6 801c68a: 4639 mov r1, r7 801c68c: f7e4 fa08 bl 8000aa0 <__aeabi_dcmple> 801c690: 2800 cmp r0, #0 801c692: d070 beq.n 801c776 <_strtod_l+0xa36> 801c694: 9b0f ldr r3, [sp, #60] @ 0x3c 801c696: 2b00 cmp r3, #0 801c698: d17b bne.n 801c792 <_strtod_l+0xa52> 801c69a: f1b8 0f00 cmp.w r8, #0 801c69e: d156 bne.n 801c74e <_strtod_l+0xa0e> 801c6a0: f3c9 0313 ubfx r3, r9, #0, #20 801c6a4: 2b00 cmp r3, #0 801c6a6: d158 bne.n 801c75a <_strtod_l+0xa1a> 801c6a8: 4b63 ldr r3, [pc, #396] @ (801c838 <_strtod_l+0xaf8>) 801c6aa: 2200 movs r2, #0 801c6ac: 4630 mov r0, r6 801c6ae: 4639 mov r1, r7 801c6b0: f7e4 f9ec bl 8000a8c <__aeabi_dcmplt> 801c6b4: 2800 cmp r0, #0 801c6b6: d159 bne.n 801c76c <_strtod_l+0xa2c> 801c6b8: 4b60 ldr r3, [pc, #384] @ (801c83c <_strtod_l+0xafc>) 801c6ba: 2200 movs r2, #0 801c6bc: 4630 mov r0, r6 801c6be: 4639 mov r1, r7 801c6c0: f7e3 ff72 bl 80005a8 <__aeabi_dmul> 801c6c4: 4682 mov sl, r0 801c6c6: 468b mov fp, r1 801c6c8: f10b 4300 add.w r3, fp, #2147483648 @ 0x80000000 801c6cc: f8cd a020 str.w sl, [sp, #32] 801c6d0: 9309 str r3, [sp, #36] @ 0x24 801c6d2: 4b55 ldr r3, [pc, #340] @ (801c828 <_strtod_l+0xae8>) 801c6d4: 4a54 ldr r2, [pc, #336] @ (801c828 <_strtod_l+0xae8>) 801c6d6: 402b ands r3, r5 801c6d8: 9313 str r3, [sp, #76] @ 0x4c 801c6da: 4b59 ldr r3, [pc, #356] @ (801c840 <_strtod_l+0xb00>) 801c6dc: 402a ands r2, r5 801c6de: 429a cmp r2, r3 801c6e0: e9dd 6708 ldrd r6, r7, [sp, #32] 801c6e4: f040 80b0 bne.w 801c848 <_strtod_l+0xb08> 801c6e8: f1a5 7954 sub.w r9, r5, #55574528 @ 0x3500000 801c6ec: ec49 8b10 vmov d0, r8, r9 801c6f0: f7ff f9c8 bl 801ba84 <__ulp> 801c6f4: e9dd 2308 ldrd r2, r3, [sp, #32] 801c6f8: ec51 0b10 vmov r0, r1, d0 801c6fc: f7e3 ff54 bl 80005a8 <__aeabi_dmul> 801c700: 4642 mov r2, r8 801c702: 464b mov r3, r9 801c704: f7e3 fd9a bl 800023c <__adddf3> 801c708: 4d47 ldr r5, [pc, #284] @ (801c828 <_strtod_l+0xae8>) 801c70a: 4a4e ldr r2, [pc, #312] @ (801c844 <_strtod_l+0xb04>) 801c70c: 400d ands r5, r1 801c70e: 4295 cmp r5, r2 801c710: 4680 mov r8, r0 801c712: d945 bls.n 801c7a0 <_strtod_l+0xa60> 801c714: 9a0d ldr r2, [sp, #52] @ 0x34 801c716: 4b47 ldr r3, [pc, #284] @ (801c834 <_strtod_l+0xaf4>) 801c718: 429a cmp r2, r3 801c71a: d103 bne.n 801c724 <_strtod_l+0x9e4> 801c71c: 9b0c ldr r3, [sp, #48] @ 0x30 801c71e: 3301 adds r3, #1 801c720: f43f ad85 beq.w 801c22e <_strtod_l+0x4ee> 801c724: f8df 910c ldr.w r9, [pc, #268] @ 801c834 <_strtod_l+0xaf4> 801c728: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff 801c72c: 9918 ldr r1, [sp, #96] @ 0x60 801c72e: 9804 ldr r0, [sp, #16] 801c730: f7fe fe6c bl 801b40c <_Bfree> 801c734: 9906 ldr r1, [sp, #24] 801c736: 9804 ldr r0, [sp, #16] 801c738: f7fe fe68 bl 801b40c <_Bfree> 801c73c: e9dd 0104 ldrd r0, r1, [sp, #16] 801c740: f7fe fe64 bl 801b40c <_Bfree> 801c744: 9804 ldr r0, [sp, #16] 801c746: 4621 mov r1, r4 801c748: f7fe fe60 bl 801b40c <_Bfree> 801c74c: e625 b.n 801c39a <_strtod_l+0x65a> 801c74e: f1b8 0f01 cmp.w r8, #1 801c752: d102 bne.n 801c75a <_strtod_l+0xa1a> 801c754: 2d00 cmp r5, #0 801c756: f43f ada4 beq.w 801c2a2 <_strtod_l+0x562> 801c75a: ed9f 7b2b vldr d7, [pc, #172] @ 801c808 <_strtod_l+0xac8> 801c75e: f8df b0d8 ldr.w fp, [pc, #216] @ 801c838 <_strtod_l+0xaf8> 801c762: ed8d 7b08 vstr d7, [sp, #32] 801c766: f04f 0a00 mov.w sl, #0 801c76a: e7b2 b.n 801c6d2 <_strtod_l+0x992> 801c76c: f8df b0cc ldr.w fp, [pc, #204] @ 801c83c <_strtod_l+0xafc> 801c770: f04f 0a00 mov.w sl, #0 801c774: e7a8 b.n 801c6c8 <_strtod_l+0x988> 801c776: 4b31 ldr r3, [pc, #196] @ (801c83c <_strtod_l+0xafc>) 801c778: 2200 movs r2, #0 801c77a: 4630 mov r0, r6 801c77c: 4639 mov r1, r7 801c77e: f7e3 ff13 bl 80005a8 <__aeabi_dmul> 801c782: 9b0f ldr r3, [sp, #60] @ 0x3c 801c784: 4682 mov sl, r0 801c786: 468b mov fp, r1 801c788: 2b00 cmp r3, #0 801c78a: d09d beq.n 801c6c8 <_strtod_l+0x988> 801c78c: e9cd ab08 strd sl, fp, [sp, #32] 801c790: e79f b.n 801c6d2 <_strtod_l+0x992> 801c792: ed9f 7b1f vldr d7, [pc, #124] @ 801c810 <_strtod_l+0xad0> 801c796: ed8d 7b08 vstr d7, [sp, #32] 801c79a: ec5b ab17 vmov sl, fp, d7 801c79e: e798 b.n 801c6d2 <_strtod_l+0x992> 801c7a0: f101 7954 add.w r9, r1, #55574528 @ 0x3500000 801c7a4: 9b07 ldr r3, [sp, #28] 801c7a6: 2b00 cmp r3, #0 801c7a8: d1c0 bne.n 801c72c <_strtod_l+0x9ec> 801c7aa: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000 801c7ae: 9a13 ldr r2, [sp, #76] @ 0x4c 801c7b0: 0d1b lsrs r3, r3, #20 801c7b2: 051b lsls r3, r3, #20 801c7b4: 429a cmp r2, r3 801c7b6: d1b9 bne.n 801c72c <_strtod_l+0x9ec> 801c7b8: 4650 mov r0, sl 801c7ba: 4659 mov r1, fp 801c7bc: f7e4 fa3c bl 8000c38 <__aeabi_d2lz> 801c7c0: f7e3 fec4 bl 800054c <__aeabi_l2d> 801c7c4: 4602 mov r2, r0 801c7c6: 460b mov r3, r1 801c7c8: 4650 mov r0, sl 801c7ca: 4659 mov r1, fp 801c7cc: f7e3 fd34 bl 8000238 <__aeabi_dsub> 801c7d0: 9a0f ldr r2, [sp, #60] @ 0x3c 801c7d2: f3c9 0313 ubfx r3, r9, #0, #20 801c7d6: ea43 0308 orr.w r3, r3, r8 801c7da: 4313 orrs r3, r2 801c7dc: 4606 mov r6, r0 801c7de: 460f mov r7, r1 801c7e0: d06b beq.n 801c8ba <_strtod_l+0xb7a> 801c7e2: a30d add r3, pc, #52 @ (adr r3, 801c818 <_strtod_l+0xad8>) 801c7e4: e9d3 2300 ldrd r2, r3, [r3] 801c7e8: f7e4 f950 bl 8000a8c <__aeabi_dcmplt> 801c7ec: 2800 cmp r0, #0 801c7ee: f47f ad29 bne.w 801c244 <_strtod_l+0x504> 801c7f2: a30b add r3, pc, #44 @ (adr r3, 801c820 <_strtod_l+0xae0>) 801c7f4: e9d3 2300 ldrd r2, r3, [r3] 801c7f8: 4630 mov r0, r6 801c7fa: 4639 mov r1, r7 801c7fc: f7e4 f964 bl 8000ac8 <__aeabi_dcmpgt> 801c800: 2800 cmp r0, #0 801c802: d093 beq.n 801c72c <_strtod_l+0x9ec> 801c804: e51e b.n 801c244 <_strtod_l+0x504> 801c806: bf00 nop 801c808: 00000000 .word 0x00000000 801c80c: bff00000 .word 0xbff00000 801c810: 00000000 .word 0x00000000 801c814: 3ff00000 .word 0x3ff00000 801c818: 94a03595 .word 0x94a03595 801c81c: 3fdfffff .word 0x3fdfffff 801c820: 35afe535 .word 0x35afe535 801c824: 3fe00000 .word 0x3fe00000 801c828: 7ff00000 .word 0x7ff00000 801c82c: 39500000 .word 0x39500000 801c830: 000fffff .word 0x000fffff 801c834: 7fefffff .word 0x7fefffff 801c838: 3ff00000 .word 0x3ff00000 801c83c: 3fe00000 .word 0x3fe00000 801c840: 7fe00000 .word 0x7fe00000 801c844: 7c9fffff .word 0x7c9fffff 801c848: 9b07 ldr r3, [sp, #28] 801c84a: b313 cbz r3, 801c892 <_strtod_l+0xb52> 801c84c: 9b13 ldr r3, [sp, #76] @ 0x4c 801c84e: f1b3 6fd4 cmp.w r3, #111149056 @ 0x6a00000 801c852: d81e bhi.n 801c892 <_strtod_l+0xb52> 801c854: a324 add r3, pc, #144 @ (adr r3, 801c8e8 <_strtod_l+0xba8>) 801c856: e9d3 2300 ldrd r2, r3, [r3] 801c85a: 4650 mov r0, sl 801c85c: 4659 mov r1, fp 801c85e: f7e4 f91f bl 8000aa0 <__aeabi_dcmple> 801c862: b190 cbz r0, 801c88a <_strtod_l+0xb4a> 801c864: 4659 mov r1, fp 801c866: 4650 mov r0, sl 801c868: f7e4 f976 bl 8000b58 <__aeabi_d2uiz> 801c86c: 2801 cmp r0, #1 801c86e: bf38 it cc 801c870: 2001 movcc r0, #1 801c872: f7e3 fe1f bl 80004b4 <__aeabi_ui2d> 801c876: 9b0f ldr r3, [sp, #60] @ 0x3c 801c878: 4682 mov sl, r0 801c87a: 468b mov fp, r1 801c87c: b9d3 cbnz r3, 801c8b4 <_strtod_l+0xb74> 801c87e: f101 4300 add.w r3, r1, #2147483648 @ 0x80000000 801c882: 9010 str r0, [sp, #64] @ 0x40 801c884: 9311 str r3, [sp, #68] @ 0x44 801c886: e9dd 6710 ldrd r6, r7, [sp, #64] @ 0x40 801c88a: 9a13 ldr r2, [sp, #76] @ 0x4c 801c88c: f107 63d6 add.w r3, r7, #112197632 @ 0x6b00000 801c890: 1a9f subs r7, r3, r2 801c892: ed9d 0b0c vldr d0, [sp, #48] @ 0x30 801c896: f7ff f8f5 bl 801ba84 <__ulp> 801c89a: 4630 mov r0, r6 801c89c: ec53 2b10 vmov r2, r3, d0 801c8a0: 4639 mov r1, r7 801c8a2: f7e3 fe81 bl 80005a8 <__aeabi_dmul> 801c8a6: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 801c8aa: f7e3 fcc7 bl 800023c <__adddf3> 801c8ae: 4680 mov r8, r0 801c8b0: 4689 mov r9, r1 801c8b2: e777 b.n 801c7a4 <_strtod_l+0xa64> 801c8b4: e9cd ab10 strd sl, fp, [sp, #64] @ 0x40 801c8b8: e7e5 b.n 801c886 <_strtod_l+0xb46> 801c8ba: a30d add r3, pc, #52 @ (adr r3, 801c8f0 <_strtod_l+0xbb0>) 801c8bc: e9d3 2300 ldrd r2, r3, [r3] 801c8c0: f7e4 f8e4 bl 8000a8c <__aeabi_dcmplt> 801c8c4: e79c b.n 801c800 <_strtod_l+0xac0> 801c8c6: 2300 movs r3, #0 801c8c8: 930b str r3, [sp, #44] @ 0x2c 801c8ca: 9a15 ldr r2, [sp, #84] @ 0x54 801c8cc: 9b17 ldr r3, [sp, #92] @ 0x5c 801c8ce: 6013 str r3, [r2, #0] 801c8d0: f7ff ba8c b.w 801bdec <_strtod_l+0xac> 801c8d4: 2a65 cmp r2, #101 @ 0x65 801c8d6: f43f ab6a beq.w 801bfae <_strtod_l+0x26e> 801c8da: 2a45 cmp r2, #69 @ 0x45 801c8dc: f43f ab67 beq.w 801bfae <_strtod_l+0x26e> 801c8e0: 2301 movs r3, #1 801c8e2: 9307 str r3, [sp, #28] 801c8e4: f7ff bba1 b.w 801c02a <_strtod_l+0x2ea> 801c8e8: ffc00000 .word 0xffc00000 801c8ec: 41dfffff .word 0x41dfffff 801c8f0: 94a03595 .word 0x94a03595 801c8f4: 3fcfffff .word 0x3fcfffff 0801c8f8 <_strtod_r>: 801c8f8: 4b01 ldr r3, [pc, #4] @ (801c900 <_strtod_r+0x8>) 801c8fa: f7ff ba21 b.w 801bd40 <_strtod_l> 801c8fe: bf00 nop 801c900: 2000016c .word 0x2000016c 0801c904 <_strtol_l.isra.0>: 801c904: 2b24 cmp r3, #36 @ 0x24 801c906: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801c90a: 4686 mov lr, r0 801c90c: 4690 mov r8, r2 801c90e: d801 bhi.n 801c914 <_strtol_l.isra.0+0x10> 801c910: 2b01 cmp r3, #1 801c912: d106 bne.n 801c922 <_strtol_l.isra.0+0x1e> 801c914: f7fd fd96 bl 801a444 <__errno> 801c918: 2316 movs r3, #22 801c91a: 6003 str r3, [r0, #0] 801c91c: 2000 movs r0, #0 801c91e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801c922: 4834 ldr r0, [pc, #208] @ (801c9f4 <_strtol_l.isra.0+0xf0>) 801c924: 460d mov r5, r1 801c926: 462a mov r2, r5 801c928: f815 4b01 ldrb.w r4, [r5], #1 801c92c: 5d06 ldrb r6, [r0, r4] 801c92e: f016 0608 ands.w r6, r6, #8 801c932: d1f8 bne.n 801c926 <_strtol_l.isra.0+0x22> 801c934: 2c2d cmp r4, #45 @ 0x2d 801c936: d110 bne.n 801c95a <_strtol_l.isra.0+0x56> 801c938: 782c ldrb r4, [r5, #0] 801c93a: 2601 movs r6, #1 801c93c: 1c95 adds r5, r2, #2 801c93e: f033 0210 bics.w r2, r3, #16 801c942: d115 bne.n 801c970 <_strtol_l.isra.0+0x6c> 801c944: 2c30 cmp r4, #48 @ 0x30 801c946: d10d bne.n 801c964 <_strtol_l.isra.0+0x60> 801c948: 782a ldrb r2, [r5, #0] 801c94a: f002 02df and.w r2, r2, #223 @ 0xdf 801c94e: 2a58 cmp r2, #88 @ 0x58 801c950: d108 bne.n 801c964 <_strtol_l.isra.0+0x60> 801c952: 786c ldrb r4, [r5, #1] 801c954: 3502 adds r5, #2 801c956: 2310 movs r3, #16 801c958: e00a b.n 801c970 <_strtol_l.isra.0+0x6c> 801c95a: 2c2b cmp r4, #43 @ 0x2b 801c95c: bf04 itt eq 801c95e: 782c ldrbeq r4, [r5, #0] 801c960: 1c95 addeq r5, r2, #2 801c962: e7ec b.n 801c93e <_strtol_l.isra.0+0x3a> 801c964: 2b00 cmp r3, #0 801c966: d1f6 bne.n 801c956 <_strtol_l.isra.0+0x52> 801c968: 2c30 cmp r4, #48 @ 0x30 801c96a: bf14 ite ne 801c96c: 230a movne r3, #10 801c96e: 2308 moveq r3, #8 801c970: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000 801c974: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff 801c978: 2200 movs r2, #0 801c97a: fbbc f9f3 udiv r9, ip, r3 801c97e: 4610 mov r0, r2 801c980: fb03 ca19 mls sl, r3, r9, ip 801c984: f1a4 0730 sub.w r7, r4, #48 @ 0x30 801c988: 2f09 cmp r7, #9 801c98a: d80f bhi.n 801c9ac <_strtol_l.isra.0+0xa8> 801c98c: 463c mov r4, r7 801c98e: 42a3 cmp r3, r4 801c990: dd1b ble.n 801c9ca <_strtol_l.isra.0+0xc6> 801c992: 1c57 adds r7, r2, #1 801c994: d007 beq.n 801c9a6 <_strtol_l.isra.0+0xa2> 801c996: 4581 cmp r9, r0 801c998: d314 bcc.n 801c9c4 <_strtol_l.isra.0+0xc0> 801c99a: d101 bne.n 801c9a0 <_strtol_l.isra.0+0x9c> 801c99c: 45a2 cmp sl, r4 801c99e: db11 blt.n 801c9c4 <_strtol_l.isra.0+0xc0> 801c9a0: fb00 4003 mla r0, r0, r3, r4 801c9a4: 2201 movs r2, #1 801c9a6: f815 4b01 ldrb.w r4, [r5], #1 801c9aa: e7eb b.n 801c984 <_strtol_l.isra.0+0x80> 801c9ac: f1a4 0741 sub.w r7, r4, #65 @ 0x41 801c9b0: 2f19 cmp r7, #25 801c9b2: d801 bhi.n 801c9b8 <_strtol_l.isra.0+0xb4> 801c9b4: 3c37 subs r4, #55 @ 0x37 801c9b6: e7ea b.n 801c98e <_strtol_l.isra.0+0x8a> 801c9b8: f1a4 0761 sub.w r7, r4, #97 @ 0x61 801c9bc: 2f19 cmp r7, #25 801c9be: d804 bhi.n 801c9ca <_strtol_l.isra.0+0xc6> 801c9c0: 3c57 subs r4, #87 @ 0x57 801c9c2: e7e4 b.n 801c98e <_strtol_l.isra.0+0x8a> 801c9c4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801c9c8: e7ed b.n 801c9a6 <_strtol_l.isra.0+0xa2> 801c9ca: 1c53 adds r3, r2, #1 801c9cc: d108 bne.n 801c9e0 <_strtol_l.isra.0+0xdc> 801c9ce: 2322 movs r3, #34 @ 0x22 801c9d0: f8ce 3000 str.w r3, [lr] 801c9d4: 4660 mov r0, ip 801c9d6: f1b8 0f00 cmp.w r8, #0 801c9da: d0a0 beq.n 801c91e <_strtol_l.isra.0+0x1a> 801c9dc: 1e69 subs r1, r5, #1 801c9de: e006 b.n 801c9ee <_strtol_l.isra.0+0xea> 801c9e0: b106 cbz r6, 801c9e4 <_strtol_l.isra.0+0xe0> 801c9e2: 4240 negs r0, r0 801c9e4: f1b8 0f00 cmp.w r8, #0 801c9e8: d099 beq.n 801c91e <_strtol_l.isra.0+0x1a> 801c9ea: 2a00 cmp r2, #0 801c9ec: d1f6 bne.n 801c9dc <_strtol_l.isra.0+0xd8> 801c9ee: f8c8 1000 str.w r1, [r8] 801c9f2: e794 b.n 801c91e <_strtol_l.isra.0+0x1a> 801c9f4: 0801e919 .word 0x0801e919 0801c9f8 <_strtol_r>: 801c9f8: f7ff bf84 b.w 801c904 <_strtol_l.isra.0> 0801c9fc <__ssputs_r>: 801c9fc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801ca00: 688e ldr r6, [r1, #8] 801ca02: 461f mov r7, r3 801ca04: 42be cmp r6, r7 801ca06: 4682 mov sl, r0 801ca08: 460c mov r4, r1 801ca0a: 4690 mov r8, r2 801ca0c: 4633 mov r3, r6 801ca0e: d853 bhi.n 801cab8 <__ssputs_r+0xbc> 801ca10: f9b1 000c ldrsh.w r0, [r1, #12] 801ca14: f410 6f90 tst.w r0, #1152 @ 0x480 801ca18: d02b beq.n 801ca72 <__ssputs_r+0x76> 801ca1a: 6965 ldr r5, [r4, #20] 801ca1c: 6823 ldr r3, [r4, #0] 801ca1e: 6909 ldr r1, [r1, #16] 801ca20: eb05 0545 add.w r5, r5, r5, lsl #1 801ca24: eba3 0901 sub.w r9, r3, r1 801ca28: eb05 75d5 add.w r5, r5, r5, lsr #31 801ca2c: 1c7b adds r3, r7, #1 801ca2e: 106d asrs r5, r5, #1 801ca30: 444b add r3, r9 801ca32: 42ab cmp r3, r5 801ca34: 462a mov r2, r5 801ca36: bf84 itt hi 801ca38: 461d movhi r5, r3 801ca3a: 462a movhi r2, r5 801ca3c: 0543 lsls r3, r0, #21 801ca3e: d527 bpl.n 801ca90 <__ssputs_r+0x94> 801ca40: 4611 mov r1, r2 801ca42: 4650 mov r0, sl 801ca44: f7fe fc18 bl 801b278 <_malloc_r> 801ca48: 4606 mov r6, r0 801ca4a: b358 cbz r0, 801caa4 <__ssputs_r+0xa8> 801ca4c: 6921 ldr r1, [r4, #16] 801ca4e: 464a mov r2, r9 801ca50: f7fd fd25 bl 801a49e 801ca54: 89a3 ldrh r3, [r4, #12] 801ca56: f423 6390 bic.w r3, r3, #1152 @ 0x480 801ca5a: f043 0380 orr.w r3, r3, #128 @ 0x80 801ca5e: 81a3 strh r3, [r4, #12] 801ca60: 6126 str r6, [r4, #16] 801ca62: 6165 str r5, [r4, #20] 801ca64: 444e add r6, r9 801ca66: eba5 0509 sub.w r5, r5, r9 801ca6a: 6026 str r6, [r4, #0] 801ca6c: 60a5 str r5, [r4, #8] 801ca6e: 463e mov r6, r7 801ca70: 463b mov r3, r7 801ca72: 461f mov r7, r3 801ca74: 6820 ldr r0, [r4, #0] 801ca76: 463a mov r2, r7 801ca78: 4641 mov r1, r8 801ca7a: f000 fb91 bl 801d1a0 801ca7e: 68a3 ldr r3, [r4, #8] 801ca80: 1b9b subs r3, r3, r6 801ca82: 60a3 str r3, [r4, #8] 801ca84: 6823 ldr r3, [r4, #0] 801ca86: 443b add r3, r7 801ca88: 6023 str r3, [r4, #0] 801ca8a: 2000 movs r0, #0 801ca8c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801ca90: 4650 mov r0, sl 801ca92: f000 ff48 bl 801d926 <_realloc_r> 801ca96: 4606 mov r6, r0 801ca98: 2800 cmp r0, #0 801ca9a: d1e1 bne.n 801ca60 <__ssputs_r+0x64> 801ca9c: 6921 ldr r1, [r4, #16] 801ca9e: 4650 mov r0, sl 801caa0: f7fe fb76 bl 801b190 <_free_r> 801caa4: 230c movs r3, #12 801caa6: f8ca 3000 str.w r3, [sl] 801caaa: 89a3 ldrh r3, [r4, #12] 801caac: f043 0340 orr.w r3, r3, #64 @ 0x40 801cab0: 81a3 strh r3, [r4, #12] 801cab2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801cab6: e7e9 b.n 801ca8c <__ssputs_r+0x90> 801cab8: 463e mov r6, r7 801caba: e7db b.n 801ca74 <__ssputs_r+0x78> 0801cabc <_svfiprintf_r>: 801cabc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801cac0: 461f mov r7, r3 801cac2: 898b ldrh r3, [r1, #12] 801cac4: 061b lsls r3, r3, #24 801cac6: b09c sub sp, #112 @ 0x70 801cac8: 4606 mov r6, r0 801caca: 460d mov r5, r1 801cacc: 4614 mov r4, r2 801cace: d510 bpl.n 801caf2 <_svfiprintf_r+0x36> 801cad0: 690b ldr r3, [r1, #16] 801cad2: b973 cbnz r3, 801caf2 <_svfiprintf_r+0x36> 801cad4: 2140 movs r1, #64 @ 0x40 801cad6: f7fe fbcf bl 801b278 <_malloc_r> 801cada: 6028 str r0, [r5, #0] 801cadc: 6128 str r0, [r5, #16] 801cade: b930 cbnz r0, 801caee <_svfiprintf_r+0x32> 801cae0: 230c movs r3, #12 801cae2: 6033 str r3, [r6, #0] 801cae4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801cae8: b01c add sp, #112 @ 0x70 801caea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801caee: 2340 movs r3, #64 @ 0x40 801caf0: 616b str r3, [r5, #20] 801caf2: 2300 movs r3, #0 801caf4: 9309 str r3, [sp, #36] @ 0x24 801caf6: 2320 movs r3, #32 801caf8: f88d 3029 strb.w r3, [sp, #41] @ 0x29 801cafc: 9703 str r7, [sp, #12] 801cafe: 2330 movs r3, #48 @ 0x30 801cb00: 4f65 ldr r7, [pc, #404] @ (801cc98 <_svfiprintf_r+0x1dc>) 801cb02: f88d 302a strb.w r3, [sp, #42] @ 0x2a 801cb06: f04f 0801 mov.w r8, #1 801cb0a: 4623 mov r3, r4 801cb0c: 4699 mov r9, r3 801cb0e: f813 2b01 ldrb.w r2, [r3], #1 801cb12: b10a cbz r2, 801cb18 <_svfiprintf_r+0x5c> 801cb14: 2a25 cmp r2, #37 @ 0x25 801cb16: d1f9 bne.n 801cb0c <_svfiprintf_r+0x50> 801cb18: ebb9 0a04 subs.w sl, r9, r4 801cb1c: d00b beq.n 801cb36 <_svfiprintf_r+0x7a> 801cb1e: 4653 mov r3, sl 801cb20: 4622 mov r2, r4 801cb22: 4629 mov r1, r5 801cb24: 4630 mov r0, r6 801cb26: f7ff ff69 bl 801c9fc <__ssputs_r> 801cb2a: 3001 adds r0, #1 801cb2c: f000 80a4 beq.w 801cc78 <_svfiprintf_r+0x1bc> 801cb30: 9a09 ldr r2, [sp, #36] @ 0x24 801cb32: 4452 add r2, sl 801cb34: 9209 str r2, [sp, #36] @ 0x24 801cb36: f899 3000 ldrb.w r3, [r9] 801cb3a: 2b00 cmp r3, #0 801cb3c: f000 809c beq.w 801cc78 <_svfiprintf_r+0x1bc> 801cb40: 2300 movs r3, #0 801cb42: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801cb46: e9cd 2305 strd r2, r3, [sp, #20] 801cb4a: f109 0901 add.w r9, r9, #1 801cb4e: 9304 str r3, [sp, #16] 801cb50: 9307 str r3, [sp, #28] 801cb52: f88d 3053 strb.w r3, [sp, #83] @ 0x53 801cb56: 931a str r3, [sp, #104] @ 0x68 801cb58: 464c mov r4, r9 801cb5a: 484f ldr r0, [pc, #316] @ (801cc98 <_svfiprintf_r+0x1dc>) 801cb5c: f814 1b01 ldrb.w r1, [r4], #1 801cb60: 2205 movs r2, #5 801cb62: f7e3 fb0d bl 8000180 801cb66: 9b04 ldr r3, [sp, #16] 801cb68: b9d0 cbnz r0, 801cba0 <_svfiprintf_r+0xe4> 801cb6a: 06d8 lsls r0, r3, #27 801cb6c: bf44 itt mi 801cb6e: 2220 movmi r2, #32 801cb70: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53 801cb74: 0719 lsls r1, r3, #28 801cb76: bf44 itt mi 801cb78: 222b movmi r2, #43 @ 0x2b 801cb7a: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53 801cb7e: f899 2000 ldrb.w r2, [r9] 801cb82: 2a2a cmp r2, #42 @ 0x2a 801cb84: d013 beq.n 801cbae <_svfiprintf_r+0xf2> 801cb86: 9a07 ldr r2, [sp, #28] 801cb88: 464c mov r4, r9 801cb8a: 2000 movs r0, #0 801cb8c: f04f 0c0a mov.w ip, #10 801cb90: 4621 mov r1, r4 801cb92: f811 3b01 ldrb.w r3, [r1], #1 801cb96: 3b30 subs r3, #48 @ 0x30 801cb98: 2b09 cmp r3, #9 801cb9a: d949 bls.n 801cc30 <_svfiprintf_r+0x174> 801cb9c: b968 cbnz r0, 801cbba <_svfiprintf_r+0xfe> 801cb9e: e013 b.n 801cbc8 <_svfiprintf_r+0x10c> 801cba0: 1bc0 subs r0, r0, r7 801cba2: fa08 f000 lsl.w r0, r8, r0 801cba6: 4318 orrs r0, r3 801cba8: 9004 str r0, [sp, #16] 801cbaa: 46a1 mov r9, r4 801cbac: e7d4 b.n 801cb58 <_svfiprintf_r+0x9c> 801cbae: 9a03 ldr r2, [sp, #12] 801cbb0: 1d11 adds r1, r2, #4 801cbb2: 6812 ldr r2, [r2, #0] 801cbb4: 9103 str r1, [sp, #12] 801cbb6: 2a00 cmp r2, #0 801cbb8: db01 blt.n 801cbbe <_svfiprintf_r+0x102> 801cbba: 9207 str r2, [sp, #28] 801cbbc: e004 b.n 801cbc8 <_svfiprintf_r+0x10c> 801cbbe: 4252 negs r2, r2 801cbc0: f043 0302 orr.w r3, r3, #2 801cbc4: 9207 str r2, [sp, #28] 801cbc6: 9304 str r3, [sp, #16] 801cbc8: 7823 ldrb r3, [r4, #0] 801cbca: 2b2e cmp r3, #46 @ 0x2e 801cbcc: d10a bne.n 801cbe4 <_svfiprintf_r+0x128> 801cbce: 7863 ldrb r3, [r4, #1] 801cbd0: 2b2a cmp r3, #42 @ 0x2a 801cbd2: d132 bne.n 801cc3a <_svfiprintf_r+0x17e> 801cbd4: 9b03 ldr r3, [sp, #12] 801cbd6: 1d1a adds r2, r3, #4 801cbd8: 681b ldr r3, [r3, #0] 801cbda: 9203 str r2, [sp, #12] 801cbdc: ea43 73e3 orr.w r3, r3, r3, asr #31 801cbe0: 3402 adds r4, #2 801cbe2: 9305 str r3, [sp, #20] 801cbe4: f8df 90c0 ldr.w r9, [pc, #192] @ 801cca8 <_svfiprintf_r+0x1ec> 801cbe8: 7821 ldrb r1, [r4, #0] 801cbea: 2203 movs r2, #3 801cbec: 4648 mov r0, r9 801cbee: f7e3 fac7 bl 8000180 801cbf2: b138 cbz r0, 801cc04 <_svfiprintf_r+0x148> 801cbf4: 9b04 ldr r3, [sp, #16] 801cbf6: eba0 0009 sub.w r0, r0, r9 801cbfa: 2240 movs r2, #64 @ 0x40 801cbfc: 4082 lsls r2, r0 801cbfe: 4313 orrs r3, r2 801cc00: 3401 adds r4, #1 801cc02: 9304 str r3, [sp, #16] 801cc04: f814 1b01 ldrb.w r1, [r4], #1 801cc08: 4824 ldr r0, [pc, #144] @ (801cc9c <_svfiprintf_r+0x1e0>) 801cc0a: f88d 1028 strb.w r1, [sp, #40] @ 0x28 801cc0e: 2206 movs r2, #6 801cc10: f7e3 fab6 bl 8000180 801cc14: 2800 cmp r0, #0 801cc16: d035 beq.n 801cc84 <_svfiprintf_r+0x1c8> 801cc18: 4821 ldr r0, [pc, #132] @ (801cca0 <_svfiprintf_r+0x1e4>) 801cc1a: bb18 cbnz r0, 801cc64 <_svfiprintf_r+0x1a8> 801cc1c: 9b03 ldr r3, [sp, #12] 801cc1e: 3307 adds r3, #7 801cc20: f023 0307 bic.w r3, r3, #7 801cc24: 3308 adds r3, #8 801cc26: 9303 str r3, [sp, #12] 801cc28: 9b09 ldr r3, [sp, #36] @ 0x24 801cc2a: 4403 add r3, r0 801cc2c: 9309 str r3, [sp, #36] @ 0x24 801cc2e: e76c b.n 801cb0a <_svfiprintf_r+0x4e> 801cc30: fb0c 3202 mla r2, ip, r2, r3 801cc34: 460c mov r4, r1 801cc36: 2001 movs r0, #1 801cc38: e7aa b.n 801cb90 <_svfiprintf_r+0xd4> 801cc3a: 2300 movs r3, #0 801cc3c: 3401 adds r4, #1 801cc3e: 9305 str r3, [sp, #20] 801cc40: 4619 mov r1, r3 801cc42: f04f 0c0a mov.w ip, #10 801cc46: 4620 mov r0, r4 801cc48: f810 2b01 ldrb.w r2, [r0], #1 801cc4c: 3a30 subs r2, #48 @ 0x30 801cc4e: 2a09 cmp r2, #9 801cc50: d903 bls.n 801cc5a <_svfiprintf_r+0x19e> 801cc52: 2b00 cmp r3, #0 801cc54: d0c6 beq.n 801cbe4 <_svfiprintf_r+0x128> 801cc56: 9105 str r1, [sp, #20] 801cc58: e7c4 b.n 801cbe4 <_svfiprintf_r+0x128> 801cc5a: fb0c 2101 mla r1, ip, r1, r2 801cc5e: 4604 mov r4, r0 801cc60: 2301 movs r3, #1 801cc62: e7f0 b.n 801cc46 <_svfiprintf_r+0x18a> 801cc64: ab03 add r3, sp, #12 801cc66: 9300 str r3, [sp, #0] 801cc68: 462a mov r2, r5 801cc6a: 4b0e ldr r3, [pc, #56] @ (801cca4 <_svfiprintf_r+0x1e8>) 801cc6c: a904 add r1, sp, #16 801cc6e: 4630 mov r0, r6 801cc70: f7fc fc34 bl 80194dc <_printf_float> 801cc74: 1c42 adds r2, r0, #1 801cc76: d1d7 bne.n 801cc28 <_svfiprintf_r+0x16c> 801cc78: 89ab ldrh r3, [r5, #12] 801cc7a: 065b lsls r3, r3, #25 801cc7c: f53f af32 bmi.w 801cae4 <_svfiprintf_r+0x28> 801cc80: 9809 ldr r0, [sp, #36] @ 0x24 801cc82: e731 b.n 801cae8 <_svfiprintf_r+0x2c> 801cc84: ab03 add r3, sp, #12 801cc86: 9300 str r3, [sp, #0] 801cc88: 462a mov r2, r5 801cc8a: 4b06 ldr r3, [pc, #24] @ (801cca4 <_svfiprintf_r+0x1e8>) 801cc8c: a904 add r1, sp, #16 801cc8e: 4630 mov r0, r6 801cc90: f7fc feba bl 8019a08 <_printf_i> 801cc94: e7ee b.n 801cc74 <_svfiprintf_r+0x1b8> 801cc96: bf00 nop 801cc98: 0801e711 .word 0x0801e711 801cc9c: 0801e71b .word 0x0801e71b 801cca0: 080194dd .word 0x080194dd 801cca4: 0801c9fd .word 0x0801c9fd 801cca8: 0801e717 .word 0x0801e717 0801ccac <__sfputc_r>: 801ccac: 6893 ldr r3, [r2, #8] 801ccae: 3b01 subs r3, #1 801ccb0: 2b00 cmp r3, #0 801ccb2: b410 push {r4} 801ccb4: 6093 str r3, [r2, #8] 801ccb6: da08 bge.n 801ccca <__sfputc_r+0x1e> 801ccb8: 6994 ldr r4, [r2, #24] 801ccba: 42a3 cmp r3, r4 801ccbc: db01 blt.n 801ccc2 <__sfputc_r+0x16> 801ccbe: 290a cmp r1, #10 801ccc0: d103 bne.n 801ccca <__sfputc_r+0x1e> 801ccc2: f85d 4b04 ldr.w r4, [sp], #4 801ccc6: f000 b9d9 b.w 801d07c <__swbuf_r> 801ccca: 6813 ldr r3, [r2, #0] 801cccc: 1c58 adds r0, r3, #1 801ccce: 6010 str r0, [r2, #0] 801ccd0: 7019 strb r1, [r3, #0] 801ccd2: 4608 mov r0, r1 801ccd4: f85d 4b04 ldr.w r4, [sp], #4 801ccd8: 4770 bx lr 0801ccda <__sfputs_r>: 801ccda: b5f8 push {r3, r4, r5, r6, r7, lr} 801ccdc: 4606 mov r6, r0 801ccde: 460f mov r7, r1 801cce0: 4614 mov r4, r2 801cce2: 18d5 adds r5, r2, r3 801cce4: 42ac cmp r4, r5 801cce6: d101 bne.n 801ccec <__sfputs_r+0x12> 801cce8: 2000 movs r0, #0 801ccea: e007 b.n 801ccfc <__sfputs_r+0x22> 801ccec: f814 1b01 ldrb.w r1, [r4], #1 801ccf0: 463a mov r2, r7 801ccf2: 4630 mov r0, r6 801ccf4: f7ff ffda bl 801ccac <__sfputc_r> 801ccf8: 1c43 adds r3, r0, #1 801ccfa: d1f3 bne.n 801cce4 <__sfputs_r+0xa> 801ccfc: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 0801cd00 <_vfiprintf_r>: 801cd00: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 801cd04: 460d mov r5, r1 801cd06: b09c sub sp, #112 @ 0x70 801cd08: 4614 mov r4, r2 801cd0a: 461f mov r7, r3 801cd0c: 4606 mov r6, r0 801cd0e: b118 cbz r0, 801cd18 <_vfiprintf_r+0x18> 801cd10: 6a03 ldr r3, [r0, #32] 801cd12: b90b cbnz r3, 801cd18 <_vfiprintf_r+0x18> 801cd14: f7fd fa38 bl 801a188 <__sinit> 801cd18: 6e6b ldr r3, [r5, #100] @ 0x64 801cd1a: 07d9 lsls r1, r3, #31 801cd1c: d405 bmi.n 801cd2a <_vfiprintf_r+0x2a> 801cd1e: 89ab ldrh r3, [r5, #12] 801cd20: 059a lsls r2, r3, #22 801cd22: d402 bmi.n 801cd2a <_vfiprintf_r+0x2a> 801cd24: 6da8 ldr r0, [r5, #88] @ 0x58 801cd26: f7fd fbb8 bl 801a49a <__retarget_lock_acquire_recursive> 801cd2a: 89ab ldrh r3, [r5, #12] 801cd2c: 071b lsls r3, r3, #28 801cd2e: d501 bpl.n 801cd34 <_vfiprintf_r+0x34> 801cd30: 692b ldr r3, [r5, #16] 801cd32: b99b cbnz r3, 801cd5c <_vfiprintf_r+0x5c> 801cd34: 4629 mov r1, r5 801cd36: 4630 mov r0, r6 801cd38: f000 f9de bl 801d0f8 <__swsetup_r> 801cd3c: b170 cbz r0, 801cd5c <_vfiprintf_r+0x5c> 801cd3e: 6e6b ldr r3, [r5, #100] @ 0x64 801cd40: 07dc lsls r4, r3, #31 801cd42: d504 bpl.n 801cd4e <_vfiprintf_r+0x4e> 801cd44: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801cd48: b01c add sp, #112 @ 0x70 801cd4a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 801cd4e: 89ab ldrh r3, [r5, #12] 801cd50: 0598 lsls r0, r3, #22 801cd52: d4f7 bmi.n 801cd44 <_vfiprintf_r+0x44> 801cd54: 6da8 ldr r0, [r5, #88] @ 0x58 801cd56: f7fd fba1 bl 801a49c <__retarget_lock_release_recursive> 801cd5a: e7f3 b.n 801cd44 <_vfiprintf_r+0x44> 801cd5c: 2300 movs r3, #0 801cd5e: 9309 str r3, [sp, #36] @ 0x24 801cd60: 2320 movs r3, #32 801cd62: f88d 3029 strb.w r3, [sp, #41] @ 0x29 801cd66: 9703 str r7, [sp, #12] 801cd68: 2330 movs r3, #48 @ 0x30 801cd6a: 4f6a ldr r7, [pc, #424] @ (801cf14 <_vfiprintf_r+0x214>) 801cd6c: f88d 302a strb.w r3, [sp, #42] @ 0x2a 801cd70: f04f 0801 mov.w r8, #1 801cd74: 4623 mov r3, r4 801cd76: 4699 mov r9, r3 801cd78: f813 2b01 ldrb.w r2, [r3], #1 801cd7c: b10a cbz r2, 801cd82 <_vfiprintf_r+0x82> 801cd7e: 2a25 cmp r2, #37 @ 0x25 801cd80: d1f9 bne.n 801cd76 <_vfiprintf_r+0x76> 801cd82: ebb9 0a04 subs.w sl, r9, r4 801cd86: d00b beq.n 801cda0 <_vfiprintf_r+0xa0> 801cd88: 4653 mov r3, sl 801cd8a: 4622 mov r2, r4 801cd8c: 4629 mov r1, r5 801cd8e: 4630 mov r0, r6 801cd90: f7ff ffa3 bl 801ccda <__sfputs_r> 801cd94: 3001 adds r0, #1 801cd96: f000 80a4 beq.w 801cee2 <_vfiprintf_r+0x1e2> 801cd9a: 9a09 ldr r2, [sp, #36] @ 0x24 801cd9c: 4452 add r2, sl 801cd9e: 9209 str r2, [sp, #36] @ 0x24 801cda0: f899 3000 ldrb.w r3, [r9] 801cda4: 2b00 cmp r3, #0 801cda6: f000 809c beq.w 801cee2 <_vfiprintf_r+0x1e2> 801cdaa: 2300 movs r3, #0 801cdac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801cdb0: e9cd 2305 strd r2, r3, [sp, #20] 801cdb4: f109 0901 add.w r9, r9, #1 801cdb8: 9304 str r3, [sp, #16] 801cdba: 9307 str r3, [sp, #28] 801cdbc: f88d 3053 strb.w r3, [sp, #83] @ 0x53 801cdc0: 931a str r3, [sp, #104] @ 0x68 801cdc2: 464c mov r4, r9 801cdc4: 4853 ldr r0, [pc, #332] @ (801cf14 <_vfiprintf_r+0x214>) 801cdc6: f814 1b01 ldrb.w r1, [r4], #1 801cdca: 2205 movs r2, #5 801cdcc: f7e3 f9d8 bl 8000180 801cdd0: 9b04 ldr r3, [sp, #16] 801cdd2: b9d0 cbnz r0, 801ce0a <_vfiprintf_r+0x10a> 801cdd4: 06d9 lsls r1, r3, #27 801cdd6: bf44 itt mi 801cdd8: 2220 movmi r2, #32 801cdda: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53 801cdde: 071a lsls r2, r3, #28 801cde0: bf44 itt mi 801cde2: 222b movmi r2, #43 @ 0x2b 801cde4: f88d 2053 strbmi.w r2, [sp, #83] @ 0x53 801cde8: f899 2000 ldrb.w r2, [r9] 801cdec: 2a2a cmp r2, #42 @ 0x2a 801cdee: d013 beq.n 801ce18 <_vfiprintf_r+0x118> 801cdf0: 9a07 ldr r2, [sp, #28] 801cdf2: 464c mov r4, r9 801cdf4: 2000 movs r0, #0 801cdf6: f04f 0c0a mov.w ip, #10 801cdfa: 4621 mov r1, r4 801cdfc: f811 3b01 ldrb.w r3, [r1], #1 801ce00: 3b30 subs r3, #48 @ 0x30 801ce02: 2b09 cmp r3, #9 801ce04: d949 bls.n 801ce9a <_vfiprintf_r+0x19a> 801ce06: b968 cbnz r0, 801ce24 <_vfiprintf_r+0x124> 801ce08: e013 b.n 801ce32 <_vfiprintf_r+0x132> 801ce0a: 1bc0 subs r0, r0, r7 801ce0c: fa08 f000 lsl.w r0, r8, r0 801ce10: 4318 orrs r0, r3 801ce12: 9004 str r0, [sp, #16] 801ce14: 46a1 mov r9, r4 801ce16: e7d4 b.n 801cdc2 <_vfiprintf_r+0xc2> 801ce18: 9a03 ldr r2, [sp, #12] 801ce1a: 1d11 adds r1, r2, #4 801ce1c: 6812 ldr r2, [r2, #0] 801ce1e: 9103 str r1, [sp, #12] 801ce20: 2a00 cmp r2, #0 801ce22: db01 blt.n 801ce28 <_vfiprintf_r+0x128> 801ce24: 9207 str r2, [sp, #28] 801ce26: e004 b.n 801ce32 <_vfiprintf_r+0x132> 801ce28: 4252 negs r2, r2 801ce2a: f043 0302 orr.w r3, r3, #2 801ce2e: 9207 str r2, [sp, #28] 801ce30: 9304 str r3, [sp, #16] 801ce32: 7823 ldrb r3, [r4, #0] 801ce34: 2b2e cmp r3, #46 @ 0x2e 801ce36: d10a bne.n 801ce4e <_vfiprintf_r+0x14e> 801ce38: 7863 ldrb r3, [r4, #1] 801ce3a: 2b2a cmp r3, #42 @ 0x2a 801ce3c: d132 bne.n 801cea4 <_vfiprintf_r+0x1a4> 801ce3e: 9b03 ldr r3, [sp, #12] 801ce40: 1d1a adds r2, r3, #4 801ce42: 681b ldr r3, [r3, #0] 801ce44: 9203 str r2, [sp, #12] 801ce46: ea43 73e3 orr.w r3, r3, r3, asr #31 801ce4a: 3402 adds r4, #2 801ce4c: 9305 str r3, [sp, #20] 801ce4e: f8df 90d4 ldr.w r9, [pc, #212] @ 801cf24 <_vfiprintf_r+0x224> 801ce52: 7821 ldrb r1, [r4, #0] 801ce54: 2203 movs r2, #3 801ce56: 4648 mov r0, r9 801ce58: f7e3 f992 bl 8000180 801ce5c: b138 cbz r0, 801ce6e <_vfiprintf_r+0x16e> 801ce5e: 9b04 ldr r3, [sp, #16] 801ce60: eba0 0009 sub.w r0, r0, r9 801ce64: 2240 movs r2, #64 @ 0x40 801ce66: 4082 lsls r2, r0 801ce68: 4313 orrs r3, r2 801ce6a: 3401 adds r4, #1 801ce6c: 9304 str r3, [sp, #16] 801ce6e: f814 1b01 ldrb.w r1, [r4], #1 801ce72: 4829 ldr r0, [pc, #164] @ (801cf18 <_vfiprintf_r+0x218>) 801ce74: f88d 1028 strb.w r1, [sp, #40] @ 0x28 801ce78: 2206 movs r2, #6 801ce7a: f7e3 f981 bl 8000180 801ce7e: 2800 cmp r0, #0 801ce80: d03e beq.n 801cf00 <_vfiprintf_r+0x200> 801ce82: 4826 ldr r0, [pc, #152] @ (801cf1c <_vfiprintf_r+0x21c>) 801ce84: bb18 cbnz r0, 801cece <_vfiprintf_r+0x1ce> 801ce86: 9b03 ldr r3, [sp, #12] 801ce88: 3307 adds r3, #7 801ce8a: f023 0307 bic.w r3, r3, #7 801ce8e: 3308 adds r3, #8 801ce90: 9303 str r3, [sp, #12] 801ce92: 9b09 ldr r3, [sp, #36] @ 0x24 801ce94: 4403 add r3, r0 801ce96: 9309 str r3, [sp, #36] @ 0x24 801ce98: e76c b.n 801cd74 <_vfiprintf_r+0x74> 801ce9a: fb0c 3202 mla r2, ip, r2, r3 801ce9e: 460c mov r4, r1 801cea0: 2001 movs r0, #1 801cea2: e7aa b.n 801cdfa <_vfiprintf_r+0xfa> 801cea4: 2300 movs r3, #0 801cea6: 3401 adds r4, #1 801cea8: 9305 str r3, [sp, #20] 801ceaa: 4619 mov r1, r3 801ceac: f04f 0c0a mov.w ip, #10 801ceb0: 4620 mov r0, r4 801ceb2: f810 2b01 ldrb.w r2, [r0], #1 801ceb6: 3a30 subs r2, #48 @ 0x30 801ceb8: 2a09 cmp r2, #9 801ceba: d903 bls.n 801cec4 <_vfiprintf_r+0x1c4> 801cebc: 2b00 cmp r3, #0 801cebe: d0c6 beq.n 801ce4e <_vfiprintf_r+0x14e> 801cec0: 9105 str r1, [sp, #20] 801cec2: e7c4 b.n 801ce4e <_vfiprintf_r+0x14e> 801cec4: fb0c 2101 mla r1, ip, r1, r2 801cec8: 4604 mov r4, r0 801ceca: 2301 movs r3, #1 801cecc: e7f0 b.n 801ceb0 <_vfiprintf_r+0x1b0> 801cece: ab03 add r3, sp, #12 801ced0: 9300 str r3, [sp, #0] 801ced2: 462a mov r2, r5 801ced4: 4b12 ldr r3, [pc, #72] @ (801cf20 <_vfiprintf_r+0x220>) 801ced6: a904 add r1, sp, #16 801ced8: 4630 mov r0, r6 801ceda: f7fc faff bl 80194dc <_printf_float> 801cede: 1c43 adds r3, r0, #1 801cee0: d1d7 bne.n 801ce92 <_vfiprintf_r+0x192> 801cee2: 6e6b ldr r3, [r5, #100] @ 0x64 801cee4: 07d9 lsls r1, r3, #31 801cee6: d405 bmi.n 801cef4 <_vfiprintf_r+0x1f4> 801cee8: 89ab ldrh r3, [r5, #12] 801ceea: 059a lsls r2, r3, #22 801ceec: d402 bmi.n 801cef4 <_vfiprintf_r+0x1f4> 801ceee: 6da8 ldr r0, [r5, #88] @ 0x58 801cef0: f7fd fad4 bl 801a49c <__retarget_lock_release_recursive> 801cef4: 89ab ldrh r3, [r5, #12] 801cef6: 065b lsls r3, r3, #25 801cef8: f53f af24 bmi.w 801cd44 <_vfiprintf_r+0x44> 801cefc: 9809 ldr r0, [sp, #36] @ 0x24 801cefe: e723 b.n 801cd48 <_vfiprintf_r+0x48> 801cf00: ab03 add r3, sp, #12 801cf02: 9300 str r3, [sp, #0] 801cf04: 462a mov r2, r5 801cf06: 4b06 ldr r3, [pc, #24] @ (801cf20 <_vfiprintf_r+0x220>) 801cf08: a904 add r1, sp, #16 801cf0a: 4630 mov r0, r6 801cf0c: f7fc fd7c bl 8019a08 <_printf_i> 801cf10: e7e5 b.n 801cede <_vfiprintf_r+0x1de> 801cf12: bf00 nop 801cf14: 0801e711 .word 0x0801e711 801cf18: 0801e71b .word 0x0801e71b 801cf1c: 080194dd .word 0x080194dd 801cf20: 0801ccdb .word 0x0801ccdb 801cf24: 0801e717 .word 0x0801e717 0801cf28 <__sflush_r>: 801cf28: f9b1 200c ldrsh.w r2, [r1, #12] 801cf2c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801cf30: 0716 lsls r6, r2, #28 801cf32: 4605 mov r5, r0 801cf34: 460c mov r4, r1 801cf36: d451 bmi.n 801cfdc <__sflush_r+0xb4> 801cf38: 684b ldr r3, [r1, #4] 801cf3a: 2b00 cmp r3, #0 801cf3c: dc02 bgt.n 801cf44 <__sflush_r+0x1c> 801cf3e: 6c0b ldr r3, [r1, #64] @ 0x40 801cf40: 2b00 cmp r3, #0 801cf42: dd49 ble.n 801cfd8 <__sflush_r+0xb0> 801cf44: 6ae6 ldr r6, [r4, #44] @ 0x2c 801cf46: 2e00 cmp r6, #0 801cf48: d046 beq.n 801cfd8 <__sflush_r+0xb0> 801cf4a: 2300 movs r3, #0 801cf4c: f412 5280 ands.w r2, r2, #4096 @ 0x1000 801cf50: 682f ldr r7, [r5, #0] 801cf52: 602b str r3, [r5, #0] 801cf54: d031 beq.n 801cfba <__sflush_r+0x92> 801cf56: 6d62 ldr r2, [r4, #84] @ 0x54 801cf58: 89a3 ldrh r3, [r4, #12] 801cf5a: 0759 lsls r1, r3, #29 801cf5c: d505 bpl.n 801cf6a <__sflush_r+0x42> 801cf5e: 6863 ldr r3, [r4, #4] 801cf60: 1ad2 subs r2, r2, r3 801cf62: 6b63 ldr r3, [r4, #52] @ 0x34 801cf64: b10b cbz r3, 801cf6a <__sflush_r+0x42> 801cf66: 6c23 ldr r3, [r4, #64] @ 0x40 801cf68: 1ad2 subs r2, r2, r3 801cf6a: 2300 movs r3, #0 801cf6c: 6ae6 ldr r6, [r4, #44] @ 0x2c 801cf6e: 6a21 ldr r1, [r4, #32] 801cf70: 4628 mov r0, r5 801cf72: 47b0 blx r6 801cf74: 1c42 adds r2, r0, #1 801cf76: f9b4 300c ldrsh.w r3, [r4, #12] 801cf7a: d106 bne.n 801cf8a <__sflush_r+0x62> 801cf7c: 6829 ldr r1, [r5, #0] 801cf7e: 291d cmp r1, #29 801cf80: d846 bhi.n 801d010 <__sflush_r+0xe8> 801cf82: 4a29 ldr r2, [pc, #164] @ (801d028 <__sflush_r+0x100>) 801cf84: 40ca lsrs r2, r1 801cf86: 07d6 lsls r6, r2, #31 801cf88: d542 bpl.n 801d010 <__sflush_r+0xe8> 801cf8a: 2200 movs r2, #0 801cf8c: 6062 str r2, [r4, #4] 801cf8e: 04d9 lsls r1, r3, #19 801cf90: 6922 ldr r2, [r4, #16] 801cf92: 6022 str r2, [r4, #0] 801cf94: d504 bpl.n 801cfa0 <__sflush_r+0x78> 801cf96: 1c42 adds r2, r0, #1 801cf98: d101 bne.n 801cf9e <__sflush_r+0x76> 801cf9a: 682b ldr r3, [r5, #0] 801cf9c: b903 cbnz r3, 801cfa0 <__sflush_r+0x78> 801cf9e: 6560 str r0, [r4, #84] @ 0x54 801cfa0: 6b61 ldr r1, [r4, #52] @ 0x34 801cfa2: 602f str r7, [r5, #0] 801cfa4: b1c1 cbz r1, 801cfd8 <__sflush_r+0xb0> 801cfa6: f104 0344 add.w r3, r4, #68 @ 0x44 801cfaa: 4299 cmp r1, r3 801cfac: d002 beq.n 801cfb4 <__sflush_r+0x8c> 801cfae: 4628 mov r0, r5 801cfb0: f7fe f8ee bl 801b190 <_free_r> 801cfb4: 2300 movs r3, #0 801cfb6: 6363 str r3, [r4, #52] @ 0x34 801cfb8: e00e b.n 801cfd8 <__sflush_r+0xb0> 801cfba: 6a21 ldr r1, [r4, #32] 801cfbc: 2301 movs r3, #1 801cfbe: 4628 mov r0, r5 801cfc0: 47b0 blx r6 801cfc2: 4602 mov r2, r0 801cfc4: 1c50 adds r0, r2, #1 801cfc6: d1c7 bne.n 801cf58 <__sflush_r+0x30> 801cfc8: 682b ldr r3, [r5, #0] 801cfca: 2b00 cmp r3, #0 801cfcc: d0c4 beq.n 801cf58 <__sflush_r+0x30> 801cfce: 2b1d cmp r3, #29 801cfd0: d001 beq.n 801cfd6 <__sflush_r+0xae> 801cfd2: 2b16 cmp r3, #22 801cfd4: d11a bne.n 801d00c <__sflush_r+0xe4> 801cfd6: 602f str r7, [r5, #0] 801cfd8: 2000 movs r0, #0 801cfda: e01e b.n 801d01a <__sflush_r+0xf2> 801cfdc: 690f ldr r7, [r1, #16] 801cfde: 2f00 cmp r7, #0 801cfe0: d0fa beq.n 801cfd8 <__sflush_r+0xb0> 801cfe2: 0793 lsls r3, r2, #30 801cfe4: 680e ldr r6, [r1, #0] 801cfe6: bf08 it eq 801cfe8: 694b ldreq r3, [r1, #20] 801cfea: 600f str r7, [r1, #0] 801cfec: bf18 it ne 801cfee: 2300 movne r3, #0 801cff0: eba6 0807 sub.w r8, r6, r7 801cff4: 608b str r3, [r1, #8] 801cff6: f1b8 0f00 cmp.w r8, #0 801cffa: dded ble.n 801cfd8 <__sflush_r+0xb0> 801cffc: 6a21 ldr r1, [r4, #32] 801cffe: 6aa6 ldr r6, [r4, #40] @ 0x28 801d000: 4643 mov r3, r8 801d002: 463a mov r2, r7 801d004: 4628 mov r0, r5 801d006: 47b0 blx r6 801d008: 2800 cmp r0, #0 801d00a: dc08 bgt.n 801d01e <__sflush_r+0xf6> 801d00c: f9b4 300c ldrsh.w r3, [r4, #12] 801d010: f043 0340 orr.w r3, r3, #64 @ 0x40 801d014: 81a3 strh r3, [r4, #12] 801d016: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801d01a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801d01e: 4407 add r7, r0 801d020: eba8 0800 sub.w r8, r8, r0 801d024: e7e7 b.n 801cff6 <__sflush_r+0xce> 801d026: bf00 nop 801d028: 20400001 .word 0x20400001 0801d02c <_fflush_r>: 801d02c: b538 push {r3, r4, r5, lr} 801d02e: 690b ldr r3, [r1, #16] 801d030: 4605 mov r5, r0 801d032: 460c mov r4, r1 801d034: b913 cbnz r3, 801d03c <_fflush_r+0x10> 801d036: 2500 movs r5, #0 801d038: 4628 mov r0, r5 801d03a: bd38 pop {r3, r4, r5, pc} 801d03c: b118 cbz r0, 801d046 <_fflush_r+0x1a> 801d03e: 6a03 ldr r3, [r0, #32] 801d040: b90b cbnz r3, 801d046 <_fflush_r+0x1a> 801d042: f7fd f8a1 bl 801a188 <__sinit> 801d046: f9b4 300c ldrsh.w r3, [r4, #12] 801d04a: 2b00 cmp r3, #0 801d04c: d0f3 beq.n 801d036 <_fflush_r+0xa> 801d04e: 6e62 ldr r2, [r4, #100] @ 0x64 801d050: 07d0 lsls r0, r2, #31 801d052: d404 bmi.n 801d05e <_fflush_r+0x32> 801d054: 0599 lsls r1, r3, #22 801d056: d402 bmi.n 801d05e <_fflush_r+0x32> 801d058: 6da0 ldr r0, [r4, #88] @ 0x58 801d05a: f7fd fa1e bl 801a49a <__retarget_lock_acquire_recursive> 801d05e: 4628 mov r0, r5 801d060: 4621 mov r1, r4 801d062: f7ff ff61 bl 801cf28 <__sflush_r> 801d066: 6e63 ldr r3, [r4, #100] @ 0x64 801d068: 07da lsls r2, r3, #31 801d06a: 4605 mov r5, r0 801d06c: d4e4 bmi.n 801d038 <_fflush_r+0xc> 801d06e: 89a3 ldrh r3, [r4, #12] 801d070: 059b lsls r3, r3, #22 801d072: d4e1 bmi.n 801d038 <_fflush_r+0xc> 801d074: 6da0 ldr r0, [r4, #88] @ 0x58 801d076: f7fd fa11 bl 801a49c <__retarget_lock_release_recursive> 801d07a: e7dd b.n 801d038 <_fflush_r+0xc> 0801d07c <__swbuf_r>: 801d07c: b5f8 push {r3, r4, r5, r6, r7, lr} 801d07e: 460e mov r6, r1 801d080: 4614 mov r4, r2 801d082: 4605 mov r5, r0 801d084: b118 cbz r0, 801d08e <__swbuf_r+0x12> 801d086: 6a03 ldr r3, [r0, #32] 801d088: b90b cbnz r3, 801d08e <__swbuf_r+0x12> 801d08a: f7fd f87d bl 801a188 <__sinit> 801d08e: 69a3 ldr r3, [r4, #24] 801d090: 60a3 str r3, [r4, #8] 801d092: 89a3 ldrh r3, [r4, #12] 801d094: 071a lsls r2, r3, #28 801d096: d501 bpl.n 801d09c <__swbuf_r+0x20> 801d098: 6923 ldr r3, [r4, #16] 801d09a: b943 cbnz r3, 801d0ae <__swbuf_r+0x32> 801d09c: 4621 mov r1, r4 801d09e: 4628 mov r0, r5 801d0a0: f000 f82a bl 801d0f8 <__swsetup_r> 801d0a4: b118 cbz r0, 801d0ae <__swbuf_r+0x32> 801d0a6: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 801d0aa: 4638 mov r0, r7 801d0ac: bdf8 pop {r3, r4, r5, r6, r7, pc} 801d0ae: 6823 ldr r3, [r4, #0] 801d0b0: 6922 ldr r2, [r4, #16] 801d0b2: 1a98 subs r0, r3, r2 801d0b4: 6963 ldr r3, [r4, #20] 801d0b6: b2f6 uxtb r6, r6 801d0b8: 4283 cmp r3, r0 801d0ba: 4637 mov r7, r6 801d0bc: dc05 bgt.n 801d0ca <__swbuf_r+0x4e> 801d0be: 4621 mov r1, r4 801d0c0: 4628 mov r0, r5 801d0c2: f7ff ffb3 bl 801d02c <_fflush_r> 801d0c6: 2800 cmp r0, #0 801d0c8: d1ed bne.n 801d0a6 <__swbuf_r+0x2a> 801d0ca: 68a3 ldr r3, [r4, #8] 801d0cc: 3b01 subs r3, #1 801d0ce: 60a3 str r3, [r4, #8] 801d0d0: 6823 ldr r3, [r4, #0] 801d0d2: 1c5a adds r2, r3, #1 801d0d4: 6022 str r2, [r4, #0] 801d0d6: 701e strb r6, [r3, #0] 801d0d8: 6962 ldr r2, [r4, #20] 801d0da: 1c43 adds r3, r0, #1 801d0dc: 429a cmp r2, r3 801d0de: d004 beq.n 801d0ea <__swbuf_r+0x6e> 801d0e0: 89a3 ldrh r3, [r4, #12] 801d0e2: 07db lsls r3, r3, #31 801d0e4: d5e1 bpl.n 801d0aa <__swbuf_r+0x2e> 801d0e6: 2e0a cmp r6, #10 801d0e8: d1df bne.n 801d0aa <__swbuf_r+0x2e> 801d0ea: 4621 mov r1, r4 801d0ec: 4628 mov r0, r5 801d0ee: f7ff ff9d bl 801d02c <_fflush_r> 801d0f2: 2800 cmp r0, #0 801d0f4: d0d9 beq.n 801d0aa <__swbuf_r+0x2e> 801d0f6: e7d6 b.n 801d0a6 <__swbuf_r+0x2a> 0801d0f8 <__swsetup_r>: 801d0f8: b538 push {r3, r4, r5, lr} 801d0fa: 4b28 ldr r3, [pc, #160] @ (801d19c <__swsetup_r+0xa4>) 801d0fc: 4605 mov r5, r0 801d0fe: 6818 ldr r0, [r3, #0] 801d100: 460c mov r4, r1 801d102: b118 cbz r0, 801d10c <__swsetup_r+0x14> 801d104: 6a03 ldr r3, [r0, #32] 801d106: b90b cbnz r3, 801d10c <__swsetup_r+0x14> 801d108: f7fd f83e bl 801a188 <__sinit> 801d10c: f9b4 300c ldrsh.w r3, [r4, #12] 801d110: 071a lsls r2, r3, #28 801d112: d421 bmi.n 801d158 <__swsetup_r+0x60> 801d114: 06d8 lsls r0, r3, #27 801d116: d407 bmi.n 801d128 <__swsetup_r+0x30> 801d118: 2209 movs r2, #9 801d11a: 602a str r2, [r5, #0] 801d11c: f043 0340 orr.w r3, r3, #64 @ 0x40 801d120: 81a3 strh r3, [r4, #12] 801d122: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801d126: e030 b.n 801d18a <__swsetup_r+0x92> 801d128: 0759 lsls r1, r3, #29 801d12a: d512 bpl.n 801d152 <__swsetup_r+0x5a> 801d12c: 6b61 ldr r1, [r4, #52] @ 0x34 801d12e: b141 cbz r1, 801d142 <__swsetup_r+0x4a> 801d130: f104 0344 add.w r3, r4, #68 @ 0x44 801d134: 4299 cmp r1, r3 801d136: d002 beq.n 801d13e <__swsetup_r+0x46> 801d138: 4628 mov r0, r5 801d13a: f7fe f829 bl 801b190 <_free_r> 801d13e: 2300 movs r3, #0 801d140: 6363 str r3, [r4, #52] @ 0x34 801d142: 2200 movs r2, #0 801d144: f9b4 300c ldrsh.w r3, [r4, #12] 801d148: 6062 str r2, [r4, #4] 801d14a: 6922 ldr r2, [r4, #16] 801d14c: 6022 str r2, [r4, #0] 801d14e: f023 0324 bic.w r3, r3, #36 @ 0x24 801d152: f043 0308 orr.w r3, r3, #8 801d156: 81a3 strh r3, [r4, #12] 801d158: 6922 ldr r2, [r4, #16] 801d15a: b93a cbnz r2, 801d16c <__swsetup_r+0x74> 801d15c: 059a lsls r2, r3, #22 801d15e: d501 bpl.n 801d164 <__swsetup_r+0x6c> 801d160: 0618 lsls r0, r3, #24 801d162: d503 bpl.n 801d16c <__swsetup_r+0x74> 801d164: 4621 mov r1, r4 801d166: 4628 mov r0, r5 801d168: f000 fc4e bl 801da08 <__smakebuf_r> 801d16c: f9b4 300c ldrsh.w r3, [r4, #12] 801d170: f013 0201 ands.w r2, r3, #1 801d174: d00a beq.n 801d18c <__swsetup_r+0x94> 801d176: 2200 movs r2, #0 801d178: 60a2 str r2, [r4, #8] 801d17a: 6962 ldr r2, [r4, #20] 801d17c: 4252 negs r2, r2 801d17e: 61a2 str r2, [r4, #24] 801d180: 6922 ldr r2, [r4, #16] 801d182: b942 cbnz r2, 801d196 <__swsetup_r+0x9e> 801d184: f013 0080 ands.w r0, r3, #128 @ 0x80 801d188: d1c8 bne.n 801d11c <__swsetup_r+0x24> 801d18a: bd38 pop {r3, r4, r5, pc} 801d18c: 0799 lsls r1, r3, #30 801d18e: bf58 it pl 801d190: 6962 ldrpl r2, [r4, #20] 801d192: 60a2 str r2, [r4, #8] 801d194: e7f4 b.n 801d180 <__swsetup_r+0x88> 801d196: 2000 movs r0, #0 801d198: e7f7 b.n 801d18a <__swsetup_r+0x92> 801d19a: bf00 nop 801d19c: 2000011c .word 0x2000011c 0801d1a0 : 801d1a0: 4288 cmp r0, r1 801d1a2: b510 push {r4, lr} 801d1a4: eb01 0402 add.w r4, r1, r2 801d1a8: d902 bls.n 801d1b0 801d1aa: 4284 cmp r4, r0 801d1ac: 4623 mov r3, r4 801d1ae: d807 bhi.n 801d1c0 801d1b0: 1e43 subs r3, r0, #1 801d1b2: 42a1 cmp r1, r4 801d1b4: d007 beq.n 801d1c6 801d1b6: f811 2b01 ldrb.w r2, [r1], #1 801d1ba: f803 2f01 strb.w r2, [r3, #1]! 801d1be: e7f8 b.n 801d1b2 801d1c0: 4402 add r2, r0 801d1c2: 4282 cmp r2, r0 801d1c4: d100 bne.n 801d1c8 801d1c6: bd10 pop {r4, pc} 801d1c8: f813 1d01 ldrb.w r1, [r3, #-1]! 801d1cc: f802 1d01 strb.w r1, [r2, #-1]! 801d1d0: e7f7 b.n 801d1c2 0801d1d2 : 801d1d2: b510 push {r4, lr} 801d1d4: b16a cbz r2, 801d1f2 801d1d6: 3901 subs r1, #1 801d1d8: 1884 adds r4, r0, r2 801d1da: f810 2b01 ldrb.w r2, [r0], #1 801d1de: f811 3f01 ldrb.w r3, [r1, #1]! 801d1e2: 429a cmp r2, r3 801d1e4: d103 bne.n 801d1ee 801d1e6: 42a0 cmp r0, r4 801d1e8: d001 beq.n 801d1ee 801d1ea: 2a00 cmp r2, #0 801d1ec: d1f5 bne.n 801d1da 801d1ee: 1ad0 subs r0, r2, r3 801d1f0: bd10 pop {r4, pc} 801d1f2: 4610 mov r0, r2 801d1f4: e7fc b.n 801d1f0 ... 0801d1f8 <_sbrk_r>: 801d1f8: b538 push {r3, r4, r5, lr} 801d1fa: 4d06 ldr r5, [pc, #24] @ (801d214 <_sbrk_r+0x1c>) 801d1fc: 2300 movs r3, #0 801d1fe: 4604 mov r4, r0 801d200: 4608 mov r0, r1 801d202: 602b str r3, [r5, #0] 801d204: f7e9 faae bl 8006764 <_sbrk> 801d208: 1c43 adds r3, r0, #1 801d20a: d102 bne.n 801d212 <_sbrk_r+0x1a> 801d20c: 682b ldr r3, [r5, #0] 801d20e: b103 cbz r3, 801d212 <_sbrk_r+0x1a> 801d210: 6023 str r3, [r4, #0] 801d212: bd38 pop {r3, r4, r5, pc} 801d214: 20013cd8 .word 0x20013cd8 0801d218 : 801d218: ed9f 0b01 vldr d0, [pc, #4] @ 801d220 801d21c: 4770 bx lr 801d21e: bf00 nop 801d220: 00000000 .word 0x00000000 801d224: 7ff80000 .word 0x7ff80000 0801d228 <__assert_func>: 801d228: b51f push {r0, r1, r2, r3, r4, lr} 801d22a: 4614 mov r4, r2 801d22c: 461a mov r2, r3 801d22e: 4b09 ldr r3, [pc, #36] @ (801d254 <__assert_func+0x2c>) 801d230: 681b ldr r3, [r3, #0] 801d232: 4605 mov r5, r0 801d234: 68d8 ldr r0, [r3, #12] 801d236: b14c cbz r4, 801d24c <__assert_func+0x24> 801d238: 4b07 ldr r3, [pc, #28] @ (801d258 <__assert_func+0x30>) 801d23a: 9100 str r1, [sp, #0] 801d23c: e9cd 3401 strd r3, r4, [sp, #4] 801d240: 4906 ldr r1, [pc, #24] @ (801d25c <__assert_func+0x34>) 801d242: 462b mov r3, r5 801d244: f000 fbaa bl 801d99c 801d248: f000 fc3a bl 801dac0 801d24c: 4b04 ldr r3, [pc, #16] @ (801d260 <__assert_func+0x38>) 801d24e: 461c mov r4, r3 801d250: e7f3 b.n 801d23a <__assert_func+0x12> 801d252: bf00 nop 801d254: 2000011c .word 0x2000011c 801d258: 0801e72a .word 0x0801e72a 801d25c: 0801e737 .word 0x0801e737 801d260: 0801e765 .word 0x0801e765 0801d264 <_calloc_r>: 801d264: b570 push {r4, r5, r6, lr} 801d266: fba1 5402 umull r5, r4, r1, r2 801d26a: b934 cbnz r4, 801d27a <_calloc_r+0x16> 801d26c: 4629 mov r1, r5 801d26e: f7fe f803 bl 801b278 <_malloc_r> 801d272: 4606 mov r6, r0 801d274: b928 cbnz r0, 801d282 <_calloc_r+0x1e> 801d276: 4630 mov r0, r6 801d278: bd70 pop {r4, r5, r6, pc} 801d27a: 220c movs r2, #12 801d27c: 6002 str r2, [r0, #0] 801d27e: 2600 movs r6, #0 801d280: e7f9 b.n 801d276 <_calloc_r+0x12> 801d282: 462a mov r2, r5 801d284: 4621 mov r1, r4 801d286: f7fd f82d bl 801a2e4 801d28a: e7f4 b.n 801d276 <_calloc_r+0x12> 0801d28c : 801d28c: 6903 ldr r3, [r0, #16] 801d28e: ebb3 1f61 cmp.w r3, r1, asr #5 801d292: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 801d296: ea4f 1261 mov.w r2, r1, asr #5 801d29a: f100 0414 add.w r4, r0, #20 801d29e: dd45 ble.n 801d32c 801d2a0: f011 011f ands.w r1, r1, #31 801d2a4: eb04 0683 add.w r6, r4, r3, lsl #2 801d2a8: eb04 0582 add.w r5, r4, r2, lsl #2 801d2ac: d10c bne.n 801d2c8 801d2ae: f100 0710 add.w r7, r0, #16 801d2b2: 4629 mov r1, r5 801d2b4: 42b1 cmp r1, r6 801d2b6: d334 bcc.n 801d322 801d2b8: 1a9b subs r3, r3, r2 801d2ba: 009b lsls r3, r3, #2 801d2bc: 1eea subs r2, r5, #3 801d2be: 4296 cmp r6, r2 801d2c0: bf38 it cc 801d2c2: 2300 movcc r3, #0 801d2c4: 4423 add r3, r4 801d2c6: e015 b.n 801d2f4 801d2c8: f854 7022 ldr.w r7, [r4, r2, lsl #2] 801d2cc: f1c1 0820 rsb r8, r1, #32 801d2d0: 40cf lsrs r7, r1 801d2d2: f105 0e04 add.w lr, r5, #4 801d2d6: 46a1 mov r9, r4 801d2d8: 4576 cmp r6, lr 801d2da: 46f4 mov ip, lr 801d2dc: d815 bhi.n 801d30a 801d2de: 1a9a subs r2, r3, r2 801d2e0: 0092 lsls r2, r2, #2 801d2e2: 3a04 subs r2, #4 801d2e4: 3501 adds r5, #1 801d2e6: 42ae cmp r6, r5 801d2e8: bf38 it cc 801d2ea: 2200 movcc r2, #0 801d2ec: 18a3 adds r3, r4, r2 801d2ee: 50a7 str r7, [r4, r2] 801d2f0: b107 cbz r7, 801d2f4 801d2f2: 3304 adds r3, #4 801d2f4: 1b1a subs r2, r3, r4 801d2f6: 42a3 cmp r3, r4 801d2f8: ea4f 02a2 mov.w r2, r2, asr #2 801d2fc: bf08 it eq 801d2fe: 2300 moveq r3, #0 801d300: 6102 str r2, [r0, #16] 801d302: bf08 it eq 801d304: 6143 streq r3, [r0, #20] 801d306: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 801d30a: f8dc c000 ldr.w ip, [ip] 801d30e: fa0c fc08 lsl.w ip, ip, r8 801d312: ea4c 0707 orr.w r7, ip, r7 801d316: f849 7b04 str.w r7, [r9], #4 801d31a: f85e 7b04 ldr.w r7, [lr], #4 801d31e: 40cf lsrs r7, r1 801d320: e7da b.n 801d2d8 801d322: f851 cb04 ldr.w ip, [r1], #4 801d326: f847 cf04 str.w ip, [r7, #4]! 801d32a: e7c3 b.n 801d2b4 801d32c: 4623 mov r3, r4 801d32e: e7e1 b.n 801d2f4 0801d330 <__hexdig_fun>: 801d330: f1a0 0330 sub.w r3, r0, #48 @ 0x30 801d334: 2b09 cmp r3, #9 801d336: d802 bhi.n 801d33e <__hexdig_fun+0xe> 801d338: 3820 subs r0, #32 801d33a: b2c0 uxtb r0, r0 801d33c: 4770 bx lr 801d33e: f1a0 0361 sub.w r3, r0, #97 @ 0x61 801d342: 2b05 cmp r3, #5 801d344: d801 bhi.n 801d34a <__hexdig_fun+0x1a> 801d346: 3847 subs r0, #71 @ 0x47 801d348: e7f7 b.n 801d33a <__hexdig_fun+0xa> 801d34a: f1a0 0341 sub.w r3, r0, #65 @ 0x41 801d34e: 2b05 cmp r3, #5 801d350: d801 bhi.n 801d356 <__hexdig_fun+0x26> 801d352: 3827 subs r0, #39 @ 0x27 801d354: e7f1 b.n 801d33a <__hexdig_fun+0xa> 801d356: 2000 movs r0, #0 801d358: 4770 bx lr ... 0801d35c <__gethex>: 801d35c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801d360: b085 sub sp, #20 801d362: 468a mov sl, r1 801d364: 9302 str r3, [sp, #8] 801d366: 680b ldr r3, [r1, #0] 801d368: 9001 str r0, [sp, #4] 801d36a: 4690 mov r8, r2 801d36c: 1c9c adds r4, r3, #2 801d36e: 46a1 mov r9, r4 801d370: f814 0b01 ldrb.w r0, [r4], #1 801d374: 2830 cmp r0, #48 @ 0x30 801d376: d0fa beq.n 801d36e <__gethex+0x12> 801d378: eba9 0303 sub.w r3, r9, r3 801d37c: f1a3 0b02 sub.w fp, r3, #2 801d380: f7ff ffd6 bl 801d330 <__hexdig_fun> 801d384: 4605 mov r5, r0 801d386: 2800 cmp r0, #0 801d388: d168 bne.n 801d45c <__gethex+0x100> 801d38a: 49a0 ldr r1, [pc, #640] @ (801d60c <__gethex+0x2b0>) 801d38c: 2201 movs r2, #1 801d38e: 4648 mov r0, r9 801d390: f7ff ff1f bl 801d1d2 801d394: 4607 mov r7, r0 801d396: 2800 cmp r0, #0 801d398: d167 bne.n 801d46a <__gethex+0x10e> 801d39a: f899 0001 ldrb.w r0, [r9, #1] 801d39e: 4626 mov r6, r4 801d3a0: f7ff ffc6 bl 801d330 <__hexdig_fun> 801d3a4: 2800 cmp r0, #0 801d3a6: d062 beq.n 801d46e <__gethex+0x112> 801d3a8: 4623 mov r3, r4 801d3aa: 7818 ldrb r0, [r3, #0] 801d3ac: 2830 cmp r0, #48 @ 0x30 801d3ae: 4699 mov r9, r3 801d3b0: f103 0301 add.w r3, r3, #1 801d3b4: d0f9 beq.n 801d3aa <__gethex+0x4e> 801d3b6: f7ff ffbb bl 801d330 <__hexdig_fun> 801d3ba: fab0 f580 clz r5, r0 801d3be: 096d lsrs r5, r5, #5 801d3c0: f04f 0b01 mov.w fp, #1 801d3c4: 464a mov r2, r9 801d3c6: 4616 mov r6, r2 801d3c8: 3201 adds r2, #1 801d3ca: 7830 ldrb r0, [r6, #0] 801d3cc: f7ff ffb0 bl 801d330 <__hexdig_fun> 801d3d0: 2800 cmp r0, #0 801d3d2: d1f8 bne.n 801d3c6 <__gethex+0x6a> 801d3d4: 498d ldr r1, [pc, #564] @ (801d60c <__gethex+0x2b0>) 801d3d6: 2201 movs r2, #1 801d3d8: 4630 mov r0, r6 801d3da: f7ff fefa bl 801d1d2 801d3de: 2800 cmp r0, #0 801d3e0: d13f bne.n 801d462 <__gethex+0x106> 801d3e2: b944 cbnz r4, 801d3f6 <__gethex+0x9a> 801d3e4: 1c74 adds r4, r6, #1 801d3e6: 4622 mov r2, r4 801d3e8: 4616 mov r6, r2 801d3ea: 3201 adds r2, #1 801d3ec: 7830 ldrb r0, [r6, #0] 801d3ee: f7ff ff9f bl 801d330 <__hexdig_fun> 801d3f2: 2800 cmp r0, #0 801d3f4: d1f8 bne.n 801d3e8 <__gethex+0x8c> 801d3f6: 1ba4 subs r4, r4, r6 801d3f8: 00a7 lsls r7, r4, #2 801d3fa: 7833 ldrb r3, [r6, #0] 801d3fc: f003 03df and.w r3, r3, #223 @ 0xdf 801d400: 2b50 cmp r3, #80 @ 0x50 801d402: d13e bne.n 801d482 <__gethex+0x126> 801d404: 7873 ldrb r3, [r6, #1] 801d406: 2b2b cmp r3, #43 @ 0x2b 801d408: d033 beq.n 801d472 <__gethex+0x116> 801d40a: 2b2d cmp r3, #45 @ 0x2d 801d40c: d034 beq.n 801d478 <__gethex+0x11c> 801d40e: 1c71 adds r1, r6, #1 801d410: 2400 movs r4, #0 801d412: 7808 ldrb r0, [r1, #0] 801d414: f7ff ff8c bl 801d330 <__hexdig_fun> 801d418: 1e43 subs r3, r0, #1 801d41a: b2db uxtb r3, r3 801d41c: 2b18 cmp r3, #24 801d41e: d830 bhi.n 801d482 <__gethex+0x126> 801d420: f1a0 0210 sub.w r2, r0, #16 801d424: f811 0f01 ldrb.w r0, [r1, #1]! 801d428: f7ff ff82 bl 801d330 <__hexdig_fun> 801d42c: f100 3cff add.w ip, r0, #4294967295 @ 0xffffffff 801d430: fa5f fc8c uxtb.w ip, ip 801d434: f1bc 0f18 cmp.w ip, #24 801d438: f04f 030a mov.w r3, #10 801d43c: d91e bls.n 801d47c <__gethex+0x120> 801d43e: b104 cbz r4, 801d442 <__gethex+0xe6> 801d440: 4252 negs r2, r2 801d442: 4417 add r7, r2 801d444: f8ca 1000 str.w r1, [sl] 801d448: b1ed cbz r5, 801d486 <__gethex+0x12a> 801d44a: f1bb 0f00 cmp.w fp, #0 801d44e: bf0c ite eq 801d450: 2506 moveq r5, #6 801d452: 2500 movne r5, #0 801d454: 4628 mov r0, r5 801d456: b005 add sp, #20 801d458: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801d45c: 2500 movs r5, #0 801d45e: 462c mov r4, r5 801d460: e7b0 b.n 801d3c4 <__gethex+0x68> 801d462: 2c00 cmp r4, #0 801d464: d1c7 bne.n 801d3f6 <__gethex+0x9a> 801d466: 4627 mov r7, r4 801d468: e7c7 b.n 801d3fa <__gethex+0x9e> 801d46a: 464e mov r6, r9 801d46c: 462f mov r7, r5 801d46e: 2501 movs r5, #1 801d470: e7c3 b.n 801d3fa <__gethex+0x9e> 801d472: 2400 movs r4, #0 801d474: 1cb1 adds r1, r6, #2 801d476: e7cc b.n 801d412 <__gethex+0xb6> 801d478: 2401 movs r4, #1 801d47a: e7fb b.n 801d474 <__gethex+0x118> 801d47c: fb03 0002 mla r0, r3, r2, r0 801d480: e7ce b.n 801d420 <__gethex+0xc4> 801d482: 4631 mov r1, r6 801d484: e7de b.n 801d444 <__gethex+0xe8> 801d486: eba6 0309 sub.w r3, r6, r9 801d48a: 3b01 subs r3, #1 801d48c: 4629 mov r1, r5 801d48e: 2b07 cmp r3, #7 801d490: dc0a bgt.n 801d4a8 <__gethex+0x14c> 801d492: 9801 ldr r0, [sp, #4] 801d494: f7fd ff7c bl 801b390 <_Balloc> 801d498: 4604 mov r4, r0 801d49a: b940 cbnz r0, 801d4ae <__gethex+0x152> 801d49c: 4b5c ldr r3, [pc, #368] @ (801d610 <__gethex+0x2b4>) 801d49e: 4602 mov r2, r0 801d4a0: 21e4 movs r1, #228 @ 0xe4 801d4a2: 485c ldr r0, [pc, #368] @ (801d614 <__gethex+0x2b8>) 801d4a4: f7ff fec0 bl 801d228 <__assert_func> 801d4a8: 3101 adds r1, #1 801d4aa: 105b asrs r3, r3, #1 801d4ac: e7ef b.n 801d48e <__gethex+0x132> 801d4ae: f100 0a14 add.w sl, r0, #20 801d4b2: 2300 movs r3, #0 801d4b4: 4655 mov r5, sl 801d4b6: 469b mov fp, r3 801d4b8: 45b1 cmp r9, r6 801d4ba: d337 bcc.n 801d52c <__gethex+0x1d0> 801d4bc: f845 bb04 str.w fp, [r5], #4 801d4c0: eba5 050a sub.w r5, r5, sl 801d4c4: 10ad asrs r5, r5, #2 801d4c6: 6125 str r5, [r4, #16] 801d4c8: 4658 mov r0, fp 801d4ca: f7fe f851 bl 801b570 <__hi0bits> 801d4ce: 016d lsls r5, r5, #5 801d4d0: f8d8 6000 ldr.w r6, [r8] 801d4d4: 1a2d subs r5, r5, r0 801d4d6: 42b5 cmp r5, r6 801d4d8: dd54 ble.n 801d584 <__gethex+0x228> 801d4da: 1bad subs r5, r5, r6 801d4dc: 4629 mov r1, r5 801d4de: 4620 mov r0, r4 801d4e0: f7fe fbed bl 801bcbe <__any_on> 801d4e4: 4681 mov r9, r0 801d4e6: b178 cbz r0, 801d508 <__gethex+0x1ac> 801d4e8: 1e6b subs r3, r5, #1 801d4ea: 1159 asrs r1, r3, #5 801d4ec: f003 021f and.w r2, r3, #31 801d4f0: f85a 1021 ldr.w r1, [sl, r1, lsl #2] 801d4f4: f04f 0901 mov.w r9, #1 801d4f8: fa09 f202 lsl.w r2, r9, r2 801d4fc: 420a tst r2, r1 801d4fe: d003 beq.n 801d508 <__gethex+0x1ac> 801d500: 454b cmp r3, r9 801d502: dc36 bgt.n 801d572 <__gethex+0x216> 801d504: f04f 0902 mov.w r9, #2 801d508: 4629 mov r1, r5 801d50a: 4620 mov r0, r4 801d50c: f7ff febe bl 801d28c 801d510: 442f add r7, r5 801d512: f8d8 3008 ldr.w r3, [r8, #8] 801d516: 42bb cmp r3, r7 801d518: da42 bge.n 801d5a0 <__gethex+0x244> 801d51a: 9801 ldr r0, [sp, #4] 801d51c: 4621 mov r1, r4 801d51e: f7fd ff75 bl 801b40c <_Bfree> 801d522: 9a0e ldr r2, [sp, #56] @ 0x38 801d524: 2300 movs r3, #0 801d526: 6013 str r3, [r2, #0] 801d528: 25a3 movs r5, #163 @ 0xa3 801d52a: e793 b.n 801d454 <__gethex+0xf8> 801d52c: f816 2d01 ldrb.w r2, [r6, #-1]! 801d530: 2a2e cmp r2, #46 @ 0x2e 801d532: d012 beq.n 801d55a <__gethex+0x1fe> 801d534: 2b20 cmp r3, #32 801d536: d104 bne.n 801d542 <__gethex+0x1e6> 801d538: f845 bb04 str.w fp, [r5], #4 801d53c: f04f 0b00 mov.w fp, #0 801d540: 465b mov r3, fp 801d542: 7830 ldrb r0, [r6, #0] 801d544: 9303 str r3, [sp, #12] 801d546: f7ff fef3 bl 801d330 <__hexdig_fun> 801d54a: 9b03 ldr r3, [sp, #12] 801d54c: f000 000f and.w r0, r0, #15 801d550: 4098 lsls r0, r3 801d552: ea4b 0b00 orr.w fp, fp, r0 801d556: 3304 adds r3, #4 801d558: e7ae b.n 801d4b8 <__gethex+0x15c> 801d55a: 45b1 cmp r9, r6 801d55c: d8ea bhi.n 801d534 <__gethex+0x1d8> 801d55e: 492b ldr r1, [pc, #172] @ (801d60c <__gethex+0x2b0>) 801d560: 9303 str r3, [sp, #12] 801d562: 2201 movs r2, #1 801d564: 4630 mov r0, r6 801d566: f7ff fe34 bl 801d1d2 801d56a: 9b03 ldr r3, [sp, #12] 801d56c: 2800 cmp r0, #0 801d56e: d1e1 bne.n 801d534 <__gethex+0x1d8> 801d570: e7a2 b.n 801d4b8 <__gethex+0x15c> 801d572: 1ea9 subs r1, r5, #2 801d574: 4620 mov r0, r4 801d576: f7fe fba2 bl 801bcbe <__any_on> 801d57a: 2800 cmp r0, #0 801d57c: d0c2 beq.n 801d504 <__gethex+0x1a8> 801d57e: f04f 0903 mov.w r9, #3 801d582: e7c1 b.n 801d508 <__gethex+0x1ac> 801d584: da09 bge.n 801d59a <__gethex+0x23e> 801d586: 1b75 subs r5, r6, r5 801d588: 4621 mov r1, r4 801d58a: 9801 ldr r0, [sp, #4] 801d58c: 462a mov r2, r5 801d58e: f7fe f957 bl 801b840 <__lshift> 801d592: 1b7f subs r7, r7, r5 801d594: 4604 mov r4, r0 801d596: f100 0a14 add.w sl, r0, #20 801d59a: f04f 0900 mov.w r9, #0 801d59e: e7b8 b.n 801d512 <__gethex+0x1b6> 801d5a0: f8d8 5004 ldr.w r5, [r8, #4] 801d5a4: 42bd cmp r5, r7 801d5a6: dd6f ble.n 801d688 <__gethex+0x32c> 801d5a8: 1bed subs r5, r5, r7 801d5aa: 42ae cmp r6, r5 801d5ac: dc34 bgt.n 801d618 <__gethex+0x2bc> 801d5ae: f8d8 300c ldr.w r3, [r8, #12] 801d5b2: 2b02 cmp r3, #2 801d5b4: d022 beq.n 801d5fc <__gethex+0x2a0> 801d5b6: 2b03 cmp r3, #3 801d5b8: d024 beq.n 801d604 <__gethex+0x2a8> 801d5ba: 2b01 cmp r3, #1 801d5bc: d115 bne.n 801d5ea <__gethex+0x28e> 801d5be: 42ae cmp r6, r5 801d5c0: d113 bne.n 801d5ea <__gethex+0x28e> 801d5c2: 2e01 cmp r6, #1 801d5c4: d10b bne.n 801d5de <__gethex+0x282> 801d5c6: 9a02 ldr r2, [sp, #8] 801d5c8: f8d8 3004 ldr.w r3, [r8, #4] 801d5cc: 6013 str r3, [r2, #0] 801d5ce: 2301 movs r3, #1 801d5d0: 6123 str r3, [r4, #16] 801d5d2: f8ca 3000 str.w r3, [sl] 801d5d6: 9b0e ldr r3, [sp, #56] @ 0x38 801d5d8: 2562 movs r5, #98 @ 0x62 801d5da: 601c str r4, [r3, #0] 801d5dc: e73a b.n 801d454 <__gethex+0xf8> 801d5de: 1e71 subs r1, r6, #1 801d5e0: 4620 mov r0, r4 801d5e2: f7fe fb6c bl 801bcbe <__any_on> 801d5e6: 2800 cmp r0, #0 801d5e8: d1ed bne.n 801d5c6 <__gethex+0x26a> 801d5ea: 9801 ldr r0, [sp, #4] 801d5ec: 4621 mov r1, r4 801d5ee: f7fd ff0d bl 801b40c <_Bfree> 801d5f2: 9a0e ldr r2, [sp, #56] @ 0x38 801d5f4: 2300 movs r3, #0 801d5f6: 6013 str r3, [r2, #0] 801d5f8: 2550 movs r5, #80 @ 0x50 801d5fa: e72b b.n 801d454 <__gethex+0xf8> 801d5fc: 9b0f ldr r3, [sp, #60] @ 0x3c 801d5fe: 2b00 cmp r3, #0 801d600: d1f3 bne.n 801d5ea <__gethex+0x28e> 801d602: e7e0 b.n 801d5c6 <__gethex+0x26a> 801d604: 9b0f ldr r3, [sp, #60] @ 0x3c 801d606: 2b00 cmp r3, #0 801d608: d1dd bne.n 801d5c6 <__gethex+0x26a> 801d60a: e7ee b.n 801d5ea <__gethex+0x28e> 801d60c: 0801e70f .word 0x0801e70f 801d610: 0801e6a5 .word 0x0801e6a5 801d614: 0801e766 .word 0x0801e766 801d618: 1e6f subs r7, r5, #1 801d61a: f1b9 0f00 cmp.w r9, #0 801d61e: d130 bne.n 801d682 <__gethex+0x326> 801d620: b127 cbz r7, 801d62c <__gethex+0x2d0> 801d622: 4639 mov r1, r7 801d624: 4620 mov r0, r4 801d626: f7fe fb4a bl 801bcbe <__any_on> 801d62a: 4681 mov r9, r0 801d62c: 117a asrs r2, r7, #5 801d62e: 2301 movs r3, #1 801d630: f85a 2022 ldr.w r2, [sl, r2, lsl #2] 801d634: f007 071f and.w r7, r7, #31 801d638: 40bb lsls r3, r7 801d63a: 4213 tst r3, r2 801d63c: 4629 mov r1, r5 801d63e: 4620 mov r0, r4 801d640: bf18 it ne 801d642: f049 0902 orrne.w r9, r9, #2 801d646: f7ff fe21 bl 801d28c 801d64a: f8d8 7004 ldr.w r7, [r8, #4] 801d64e: 1b76 subs r6, r6, r5 801d650: 2502 movs r5, #2 801d652: f1b9 0f00 cmp.w r9, #0 801d656: d047 beq.n 801d6e8 <__gethex+0x38c> 801d658: f8d8 300c ldr.w r3, [r8, #12] 801d65c: 2b02 cmp r3, #2 801d65e: d015 beq.n 801d68c <__gethex+0x330> 801d660: 2b03 cmp r3, #3 801d662: d017 beq.n 801d694 <__gethex+0x338> 801d664: 2b01 cmp r3, #1 801d666: d109 bne.n 801d67c <__gethex+0x320> 801d668: f019 0f02 tst.w r9, #2 801d66c: d006 beq.n 801d67c <__gethex+0x320> 801d66e: f8da 3000 ldr.w r3, [sl] 801d672: ea49 0903 orr.w r9, r9, r3 801d676: f019 0f01 tst.w r9, #1 801d67a: d10e bne.n 801d69a <__gethex+0x33e> 801d67c: f045 0510 orr.w r5, r5, #16 801d680: e032 b.n 801d6e8 <__gethex+0x38c> 801d682: f04f 0901 mov.w r9, #1 801d686: e7d1 b.n 801d62c <__gethex+0x2d0> 801d688: 2501 movs r5, #1 801d68a: e7e2 b.n 801d652 <__gethex+0x2f6> 801d68c: 9b0f ldr r3, [sp, #60] @ 0x3c 801d68e: f1c3 0301 rsb r3, r3, #1 801d692: 930f str r3, [sp, #60] @ 0x3c 801d694: 9b0f ldr r3, [sp, #60] @ 0x3c 801d696: 2b00 cmp r3, #0 801d698: d0f0 beq.n 801d67c <__gethex+0x320> 801d69a: f8d4 b010 ldr.w fp, [r4, #16] 801d69e: f104 0314 add.w r3, r4, #20 801d6a2: ea4f 0a8b mov.w sl, fp, lsl #2 801d6a6: eb03 018b add.w r1, r3, fp, lsl #2 801d6aa: f04f 0c00 mov.w ip, #0 801d6ae: 4618 mov r0, r3 801d6b0: f853 2b04 ldr.w r2, [r3], #4 801d6b4: f1b2 3fff cmp.w r2, #4294967295 @ 0xffffffff 801d6b8: d01b beq.n 801d6f2 <__gethex+0x396> 801d6ba: 3201 adds r2, #1 801d6bc: 6002 str r2, [r0, #0] 801d6be: 2d02 cmp r5, #2 801d6c0: f104 0314 add.w r3, r4, #20 801d6c4: d13c bne.n 801d740 <__gethex+0x3e4> 801d6c6: f8d8 2000 ldr.w r2, [r8] 801d6ca: 3a01 subs r2, #1 801d6cc: 42b2 cmp r2, r6 801d6ce: d109 bne.n 801d6e4 <__gethex+0x388> 801d6d0: 1171 asrs r1, r6, #5 801d6d2: 2201 movs r2, #1 801d6d4: f853 3021 ldr.w r3, [r3, r1, lsl #2] 801d6d8: f006 061f and.w r6, r6, #31 801d6dc: fa02 f606 lsl.w r6, r2, r6 801d6e0: 421e tst r6, r3 801d6e2: d13a bne.n 801d75a <__gethex+0x3fe> 801d6e4: f045 0520 orr.w r5, r5, #32 801d6e8: 9b0e ldr r3, [sp, #56] @ 0x38 801d6ea: 601c str r4, [r3, #0] 801d6ec: 9b02 ldr r3, [sp, #8] 801d6ee: 601f str r7, [r3, #0] 801d6f0: e6b0 b.n 801d454 <__gethex+0xf8> 801d6f2: 4299 cmp r1, r3 801d6f4: f843 cc04 str.w ip, [r3, #-4] 801d6f8: d8d9 bhi.n 801d6ae <__gethex+0x352> 801d6fa: 68a3 ldr r3, [r4, #8] 801d6fc: 459b cmp fp, r3 801d6fe: db17 blt.n 801d730 <__gethex+0x3d4> 801d700: 6861 ldr r1, [r4, #4] 801d702: 9801 ldr r0, [sp, #4] 801d704: 3101 adds r1, #1 801d706: f7fd fe43 bl 801b390 <_Balloc> 801d70a: 4681 mov r9, r0 801d70c: b918 cbnz r0, 801d716 <__gethex+0x3ba> 801d70e: 4b1a ldr r3, [pc, #104] @ (801d778 <__gethex+0x41c>) 801d710: 4602 mov r2, r0 801d712: 2184 movs r1, #132 @ 0x84 801d714: e6c5 b.n 801d4a2 <__gethex+0x146> 801d716: 6922 ldr r2, [r4, #16] 801d718: 3202 adds r2, #2 801d71a: f104 010c add.w r1, r4, #12 801d71e: 0092 lsls r2, r2, #2 801d720: 300c adds r0, #12 801d722: f7fc febc bl 801a49e 801d726: 4621 mov r1, r4 801d728: 9801 ldr r0, [sp, #4] 801d72a: f7fd fe6f bl 801b40c <_Bfree> 801d72e: 464c mov r4, r9 801d730: 6923 ldr r3, [r4, #16] 801d732: 1c5a adds r2, r3, #1 801d734: eb04 0383 add.w r3, r4, r3, lsl #2 801d738: 6122 str r2, [r4, #16] 801d73a: 2201 movs r2, #1 801d73c: 615a str r2, [r3, #20] 801d73e: e7be b.n 801d6be <__gethex+0x362> 801d740: 6922 ldr r2, [r4, #16] 801d742: 455a cmp r2, fp 801d744: dd0b ble.n 801d75e <__gethex+0x402> 801d746: 2101 movs r1, #1 801d748: 4620 mov r0, r4 801d74a: f7ff fd9f bl 801d28c 801d74e: f8d8 3008 ldr.w r3, [r8, #8] 801d752: 3701 adds r7, #1 801d754: 42bb cmp r3, r7 801d756: f6ff aee0 blt.w 801d51a <__gethex+0x1be> 801d75a: 2501 movs r5, #1 801d75c: e7c2 b.n 801d6e4 <__gethex+0x388> 801d75e: f016 061f ands.w r6, r6, #31 801d762: d0fa beq.n 801d75a <__gethex+0x3fe> 801d764: 4453 add r3, sl 801d766: f1c6 0620 rsb r6, r6, #32 801d76a: f853 0c04 ldr.w r0, [r3, #-4] 801d76e: f7fd feff bl 801b570 <__hi0bits> 801d772: 42b0 cmp r0, r6 801d774: dbe7 blt.n 801d746 <__gethex+0x3ea> 801d776: e7f0 b.n 801d75a <__gethex+0x3fe> 801d778: 0801e6a5 .word 0x0801e6a5 0801d77c : 801d77c: f1c2 0208 rsb r2, r2, #8 801d780: 0092 lsls r2, r2, #2 801d782: b570 push {r4, r5, r6, lr} 801d784: f1c2 0620 rsb r6, r2, #32 801d788: 6843 ldr r3, [r0, #4] 801d78a: 6804 ldr r4, [r0, #0] 801d78c: fa03 f506 lsl.w r5, r3, r6 801d790: 432c orrs r4, r5 801d792: 40d3 lsrs r3, r2 801d794: 6004 str r4, [r0, #0] 801d796: f840 3f04 str.w r3, [r0, #4]! 801d79a: 4288 cmp r0, r1 801d79c: d3f4 bcc.n 801d788 801d79e: bd70 pop {r4, r5, r6, pc} 0801d7a0 <__match>: 801d7a0: b530 push {r4, r5, lr} 801d7a2: 6803 ldr r3, [r0, #0] 801d7a4: 3301 adds r3, #1 801d7a6: f811 4b01 ldrb.w r4, [r1], #1 801d7aa: b914 cbnz r4, 801d7b2 <__match+0x12> 801d7ac: 6003 str r3, [r0, #0] 801d7ae: 2001 movs r0, #1 801d7b0: bd30 pop {r4, r5, pc} 801d7b2: f813 2b01 ldrb.w r2, [r3], #1 801d7b6: f1a2 0541 sub.w r5, r2, #65 @ 0x41 801d7ba: 2d19 cmp r5, #25 801d7bc: bf98 it ls 801d7be: 3220 addls r2, #32 801d7c0: 42a2 cmp r2, r4 801d7c2: d0f0 beq.n 801d7a6 <__match+0x6> 801d7c4: 2000 movs r0, #0 801d7c6: e7f3 b.n 801d7b0 <__match+0x10> 0801d7c8 <__hexnan>: 801d7c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801d7cc: 680b ldr r3, [r1, #0] 801d7ce: 6801 ldr r1, [r0, #0] 801d7d0: 115e asrs r6, r3, #5 801d7d2: eb02 0686 add.w r6, r2, r6, lsl #2 801d7d6: f013 031f ands.w r3, r3, #31 801d7da: b087 sub sp, #28 801d7dc: bf18 it ne 801d7de: 3604 addne r6, #4 801d7e0: 2500 movs r5, #0 801d7e2: 1f37 subs r7, r6, #4 801d7e4: 4682 mov sl, r0 801d7e6: 4690 mov r8, r2 801d7e8: 9301 str r3, [sp, #4] 801d7ea: f846 5c04 str.w r5, [r6, #-4] 801d7ee: 46b9 mov r9, r7 801d7f0: 463c mov r4, r7 801d7f2: 9502 str r5, [sp, #8] 801d7f4: 46ab mov fp, r5 801d7f6: 784a ldrb r2, [r1, #1] 801d7f8: 1c4b adds r3, r1, #1 801d7fa: 9303 str r3, [sp, #12] 801d7fc: b342 cbz r2, 801d850 <__hexnan+0x88> 801d7fe: 4610 mov r0, r2 801d800: 9105 str r1, [sp, #20] 801d802: 9204 str r2, [sp, #16] 801d804: f7ff fd94 bl 801d330 <__hexdig_fun> 801d808: 2800 cmp r0, #0 801d80a: d153 bne.n 801d8b4 <__hexnan+0xec> 801d80c: 9a04 ldr r2, [sp, #16] 801d80e: 9905 ldr r1, [sp, #20] 801d810: 2a20 cmp r2, #32 801d812: d818 bhi.n 801d846 <__hexnan+0x7e> 801d814: 9b02 ldr r3, [sp, #8] 801d816: 459b cmp fp, r3 801d818: dd13 ble.n 801d842 <__hexnan+0x7a> 801d81a: 454c cmp r4, r9 801d81c: d206 bcs.n 801d82c <__hexnan+0x64> 801d81e: 2d07 cmp r5, #7 801d820: dc04 bgt.n 801d82c <__hexnan+0x64> 801d822: 462a mov r2, r5 801d824: 4649 mov r1, r9 801d826: 4620 mov r0, r4 801d828: f7ff ffa8 bl 801d77c 801d82c: 4544 cmp r4, r8 801d82e: d954 bls.n 801d8da <__hexnan+0x112> 801d830: 2300 movs r3, #0 801d832: f1a4 0904 sub.w r9, r4, #4 801d836: f844 3c04 str.w r3, [r4, #-4] 801d83a: f8cd b008 str.w fp, [sp, #8] 801d83e: 464c mov r4, r9 801d840: 461d mov r5, r3 801d842: 9903 ldr r1, [sp, #12] 801d844: e7d7 b.n 801d7f6 <__hexnan+0x2e> 801d846: 2a29 cmp r2, #41 @ 0x29 801d848: d159 bne.n 801d8fe <__hexnan+0x136> 801d84a: 3102 adds r1, #2 801d84c: f8ca 1000 str.w r1, [sl] 801d850: f1bb 0f00 cmp.w fp, #0 801d854: d053 beq.n 801d8fe <__hexnan+0x136> 801d856: 454c cmp r4, r9 801d858: d206 bcs.n 801d868 <__hexnan+0xa0> 801d85a: 2d07 cmp r5, #7 801d85c: dc04 bgt.n 801d868 <__hexnan+0xa0> 801d85e: 462a mov r2, r5 801d860: 4649 mov r1, r9 801d862: 4620 mov r0, r4 801d864: f7ff ff8a bl 801d77c 801d868: 4544 cmp r4, r8 801d86a: d938 bls.n 801d8de <__hexnan+0x116> 801d86c: f1a8 0204 sub.w r2, r8, #4 801d870: 4623 mov r3, r4 801d872: f853 1b04 ldr.w r1, [r3], #4 801d876: f842 1f04 str.w r1, [r2, #4]! 801d87a: 429f cmp r7, r3 801d87c: d2f9 bcs.n 801d872 <__hexnan+0xaa> 801d87e: 1b3b subs r3, r7, r4 801d880: f023 0303 bic.w r3, r3, #3 801d884: 3401 adds r4, #1 801d886: 3e03 subs r6, #3 801d888: 42b4 cmp r4, r6 801d88a: bf88 it hi 801d88c: 2300 movhi r3, #0 801d88e: f108 0204 add.w r2, r8, #4 801d892: 4413 add r3, r2 801d894: 2100 movs r1, #0 801d896: 461a mov r2, r3 801d898: 3304 adds r3, #4 801d89a: 429f cmp r7, r3 801d89c: 6011 str r1, [r2, #0] 801d89e: d2fa bcs.n 801d896 <__hexnan+0xce> 801d8a0: 683b ldr r3, [r7, #0] 801d8a2: b91b cbnz r3, 801d8ac <__hexnan+0xe4> 801d8a4: 4547 cmp r7, r8 801d8a6: d128 bne.n 801d8fa <__hexnan+0x132> 801d8a8: 2301 movs r3, #1 801d8aa: 603b str r3, [r7, #0] 801d8ac: 2005 movs r0, #5 801d8ae: b007 add sp, #28 801d8b0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 801d8b4: 3501 adds r5, #1 801d8b6: 2d08 cmp r5, #8 801d8b8: f10b 0b01 add.w fp, fp, #1 801d8bc: dd06 ble.n 801d8cc <__hexnan+0x104> 801d8be: 4544 cmp r4, r8 801d8c0: d9bf bls.n 801d842 <__hexnan+0x7a> 801d8c2: 2300 movs r3, #0 801d8c4: f844 3c04 str.w r3, [r4, #-4] 801d8c8: 2501 movs r5, #1 801d8ca: 3c04 subs r4, #4 801d8cc: 6822 ldr r2, [r4, #0] 801d8ce: f000 000f and.w r0, r0, #15 801d8d2: ea40 1002 orr.w r0, r0, r2, lsl #4 801d8d6: 6020 str r0, [r4, #0] 801d8d8: e7b3 b.n 801d842 <__hexnan+0x7a> 801d8da: 2508 movs r5, #8 801d8dc: e7b1 b.n 801d842 <__hexnan+0x7a> 801d8de: 9b01 ldr r3, [sp, #4] 801d8e0: 2b00 cmp r3, #0 801d8e2: d0dd beq.n 801d8a0 <__hexnan+0xd8> 801d8e4: f1c3 0320 rsb r3, r3, #32 801d8e8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801d8ec: 40da lsrs r2, r3 801d8ee: f856 3c04 ldr.w r3, [r6, #-4] 801d8f2: 4013 ands r3, r2 801d8f4: f846 3c04 str.w r3, [r6, #-4] 801d8f8: e7d2 b.n 801d8a0 <__hexnan+0xd8> 801d8fa: 3f04 subs r7, #4 801d8fc: e7d0 b.n 801d8a0 <__hexnan+0xd8> 801d8fe: 2004 movs r0, #4 801d900: e7d5 b.n 801d8ae <__hexnan+0xe6> 0801d902 <__ascii_mbtowc>: 801d902: b082 sub sp, #8 801d904: b901 cbnz r1, 801d908 <__ascii_mbtowc+0x6> 801d906: a901 add r1, sp, #4 801d908: b142 cbz r2, 801d91c <__ascii_mbtowc+0x1a> 801d90a: b14b cbz r3, 801d920 <__ascii_mbtowc+0x1e> 801d90c: 7813 ldrb r3, [r2, #0] 801d90e: 600b str r3, [r1, #0] 801d910: 7812 ldrb r2, [r2, #0] 801d912: 1e10 subs r0, r2, #0 801d914: bf18 it ne 801d916: 2001 movne r0, #1 801d918: b002 add sp, #8 801d91a: 4770 bx lr 801d91c: 4610 mov r0, r2 801d91e: e7fb b.n 801d918 <__ascii_mbtowc+0x16> 801d920: f06f 0001 mvn.w r0, #1 801d924: e7f8 b.n 801d918 <__ascii_mbtowc+0x16> 0801d926 <_realloc_r>: 801d926: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 801d92a: 4607 mov r7, r0 801d92c: 4614 mov r4, r2 801d92e: 460d mov r5, r1 801d930: b921 cbnz r1, 801d93c <_realloc_r+0x16> 801d932: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 801d936: 4611 mov r1, r2 801d938: f7fd bc9e b.w 801b278 <_malloc_r> 801d93c: b92a cbnz r2, 801d94a <_realloc_r+0x24> 801d93e: f7fd fc27 bl 801b190 <_free_r> 801d942: 4625 mov r5, r4 801d944: 4628 mov r0, r5 801d946: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801d94a: f000 f8c0 bl 801dace <_malloc_usable_size_r> 801d94e: 4284 cmp r4, r0 801d950: 4606 mov r6, r0 801d952: d802 bhi.n 801d95a <_realloc_r+0x34> 801d954: ebb4 0f50 cmp.w r4, r0, lsr #1 801d958: d8f4 bhi.n 801d944 <_realloc_r+0x1e> 801d95a: 4621 mov r1, r4 801d95c: 4638 mov r0, r7 801d95e: f7fd fc8b bl 801b278 <_malloc_r> 801d962: 4680 mov r8, r0 801d964: b908 cbnz r0, 801d96a <_realloc_r+0x44> 801d966: 4645 mov r5, r8 801d968: e7ec b.n 801d944 <_realloc_r+0x1e> 801d96a: 42b4 cmp r4, r6 801d96c: 4622 mov r2, r4 801d96e: 4629 mov r1, r5 801d970: bf28 it cs 801d972: 4632 movcs r2, r6 801d974: f7fc fd93 bl 801a49e 801d978: 4629 mov r1, r5 801d97a: 4638 mov r0, r7 801d97c: f7fd fc08 bl 801b190 <_free_r> 801d980: e7f1 b.n 801d966 <_realloc_r+0x40> 0801d982 <__ascii_wctomb>: 801d982: 4603 mov r3, r0 801d984: 4608 mov r0, r1 801d986: b141 cbz r1, 801d99a <__ascii_wctomb+0x18> 801d988: 2aff cmp r2, #255 @ 0xff 801d98a: d904 bls.n 801d996 <__ascii_wctomb+0x14> 801d98c: 228a movs r2, #138 @ 0x8a 801d98e: 601a str r2, [r3, #0] 801d990: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801d994: 4770 bx lr 801d996: 700a strb r2, [r1, #0] 801d998: 2001 movs r0, #1 801d99a: 4770 bx lr 0801d99c : 801d99c: b40e push {r1, r2, r3} 801d99e: b503 push {r0, r1, lr} 801d9a0: 4601 mov r1, r0 801d9a2: ab03 add r3, sp, #12 801d9a4: 4805 ldr r0, [pc, #20] @ (801d9bc ) 801d9a6: f853 2b04 ldr.w r2, [r3], #4 801d9aa: 6800 ldr r0, [r0, #0] 801d9ac: 9301 str r3, [sp, #4] 801d9ae: f7ff f9a7 bl 801cd00 <_vfiprintf_r> 801d9b2: b002 add sp, #8 801d9b4: f85d eb04 ldr.w lr, [sp], #4 801d9b8: b003 add sp, #12 801d9ba: 4770 bx lr 801d9bc: 2000011c .word 0x2000011c 0801d9c0 <__swhatbuf_r>: 801d9c0: b570 push {r4, r5, r6, lr} 801d9c2: 460c mov r4, r1 801d9c4: f9b1 100e ldrsh.w r1, [r1, #14] 801d9c8: 2900 cmp r1, #0 801d9ca: b096 sub sp, #88 @ 0x58 801d9cc: 4615 mov r5, r2 801d9ce: 461e mov r6, r3 801d9d0: da0a bge.n 801d9e8 <__swhatbuf_r+0x28> 801d9d2: 89a1 ldrh r1, [r4, #12] 801d9d4: f011 0180 ands.w r1, r1, #128 @ 0x80 801d9d8: d113 bne.n 801da02 <__swhatbuf_r+0x42> 801d9da: f44f 6280 mov.w r2, #1024 @ 0x400 801d9de: 2000 movs r0, #0 801d9e0: 6031 str r1, [r6, #0] 801d9e2: 602a str r2, [r5, #0] 801d9e4: b016 add sp, #88 @ 0x58 801d9e6: bd70 pop {r4, r5, r6, pc} 801d9e8: 466a mov r2, sp 801d9ea: f000 f847 bl 801da7c <_fstat_r> 801d9ee: 2800 cmp r0, #0 801d9f0: dbef blt.n 801d9d2 <__swhatbuf_r+0x12> 801d9f2: 9901 ldr r1, [sp, #4] 801d9f4: f401 4170 and.w r1, r1, #61440 @ 0xf000 801d9f8: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 801d9fc: 4259 negs r1, r3 801d9fe: 4159 adcs r1, r3 801da00: e7eb b.n 801d9da <__swhatbuf_r+0x1a> 801da02: 2100 movs r1, #0 801da04: 2240 movs r2, #64 @ 0x40 801da06: e7ea b.n 801d9de <__swhatbuf_r+0x1e> 0801da08 <__smakebuf_r>: 801da08: 898b ldrh r3, [r1, #12] 801da0a: b573 push {r0, r1, r4, r5, r6, lr} 801da0c: 079e lsls r6, r3, #30 801da0e: 4605 mov r5, r0 801da10: 460c mov r4, r1 801da12: d507 bpl.n 801da24 <__smakebuf_r+0x1c> 801da14: f104 0347 add.w r3, r4, #71 @ 0x47 801da18: 6023 str r3, [r4, #0] 801da1a: 6123 str r3, [r4, #16] 801da1c: 2301 movs r3, #1 801da1e: 6163 str r3, [r4, #20] 801da20: b002 add sp, #8 801da22: bd70 pop {r4, r5, r6, pc} 801da24: ab01 add r3, sp, #4 801da26: 466a mov r2, sp 801da28: f7ff ffca bl 801d9c0 <__swhatbuf_r> 801da2c: 9e00 ldr r6, [sp, #0] 801da2e: 4628 mov r0, r5 801da30: 4631 mov r1, r6 801da32: f7fd fc21 bl 801b278 <_malloc_r> 801da36: f9b4 300c ldrsh.w r3, [r4, #12] 801da3a: b938 cbnz r0, 801da4c <__smakebuf_r+0x44> 801da3c: 059a lsls r2, r3, #22 801da3e: d4ef bmi.n 801da20 <__smakebuf_r+0x18> 801da40: f023 0303 bic.w r3, r3, #3 801da44: f043 0302 orr.w r3, r3, #2 801da48: 81a3 strh r3, [r4, #12] 801da4a: e7e3 b.n 801da14 <__smakebuf_r+0xc> 801da4c: f043 0380 orr.w r3, r3, #128 @ 0x80 801da50: 81a3 strh r3, [r4, #12] 801da52: 9b01 ldr r3, [sp, #4] 801da54: 6020 str r0, [r4, #0] 801da56: e9c4 0604 strd r0, r6, [r4, #16] 801da5a: 2b00 cmp r3, #0 801da5c: d0e0 beq.n 801da20 <__smakebuf_r+0x18> 801da5e: f9b4 100e ldrsh.w r1, [r4, #14] 801da62: 4628 mov r0, r5 801da64: f000 f81c bl 801daa0 <_isatty_r> 801da68: 2800 cmp r0, #0 801da6a: d0d9 beq.n 801da20 <__smakebuf_r+0x18> 801da6c: 89a3 ldrh r3, [r4, #12] 801da6e: f023 0303 bic.w r3, r3, #3 801da72: f043 0301 orr.w r3, r3, #1 801da76: 81a3 strh r3, [r4, #12] 801da78: e7d2 b.n 801da20 <__smakebuf_r+0x18> ... 0801da7c <_fstat_r>: 801da7c: b538 push {r3, r4, r5, lr} 801da7e: 4d07 ldr r5, [pc, #28] @ (801da9c <_fstat_r+0x20>) 801da80: 2300 movs r3, #0 801da82: 4604 mov r4, r0 801da84: 4608 mov r0, r1 801da86: 4611 mov r1, r2 801da88: 602b str r3, [r5, #0] 801da8a: f7e8 fe43 bl 8006714 <_fstat> 801da8e: 1c43 adds r3, r0, #1 801da90: d102 bne.n 801da98 <_fstat_r+0x1c> 801da92: 682b ldr r3, [r5, #0] 801da94: b103 cbz r3, 801da98 <_fstat_r+0x1c> 801da96: 6023 str r3, [r4, #0] 801da98: bd38 pop {r3, r4, r5, pc} 801da9a: bf00 nop 801da9c: 20013cd8 .word 0x20013cd8 0801daa0 <_isatty_r>: 801daa0: b538 push {r3, r4, r5, lr} 801daa2: 4d06 ldr r5, [pc, #24] @ (801dabc <_isatty_r+0x1c>) 801daa4: 2300 movs r3, #0 801daa6: 4604 mov r4, r0 801daa8: 4608 mov r0, r1 801daaa: 602b str r3, [r5, #0] 801daac: f7e8 fe42 bl 8006734 <_isatty> 801dab0: 1c43 adds r3, r0, #1 801dab2: d102 bne.n 801daba <_isatty_r+0x1a> 801dab4: 682b ldr r3, [r5, #0] 801dab6: b103 cbz r3, 801daba <_isatty_r+0x1a> 801dab8: 6023 str r3, [r4, #0] 801daba: bd38 pop {r3, r4, r5, pc} 801dabc: 20013cd8 .word 0x20013cd8 0801dac0 : 801dac0: b508 push {r3, lr} 801dac2: 2006 movs r0, #6 801dac4: f000 f834 bl 801db30 801dac8: 2001 movs r0, #1 801daca: f7e8 fdef bl 80066ac <_exit> 0801dace <_malloc_usable_size_r>: 801dace: f851 3c04 ldr.w r3, [r1, #-4] 801dad2: 1f18 subs r0, r3, #4 801dad4: 2b00 cmp r3, #0 801dad6: bfbc itt lt 801dad8: 580b ldrlt r3, [r1, r0] 801dada: 18c0 addlt r0, r0, r3 801dadc: 4770 bx lr 0801dade <_raise_r>: 801dade: 291f cmp r1, #31 801dae0: b538 push {r3, r4, r5, lr} 801dae2: 4605 mov r5, r0 801dae4: 460c mov r4, r1 801dae6: d904 bls.n 801daf2 <_raise_r+0x14> 801dae8: 2316 movs r3, #22 801daea: 6003 str r3, [r0, #0] 801daec: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801daf0: bd38 pop {r3, r4, r5, pc} 801daf2: 6bc2 ldr r2, [r0, #60] @ 0x3c 801daf4: b112 cbz r2, 801dafc <_raise_r+0x1e> 801daf6: f852 3021 ldr.w r3, [r2, r1, lsl #2] 801dafa: b94b cbnz r3, 801db10 <_raise_r+0x32> 801dafc: 4628 mov r0, r5 801dafe: f000 f831 bl 801db64 <_getpid_r> 801db02: 4622 mov r2, r4 801db04: 4601 mov r1, r0 801db06: 4628 mov r0, r5 801db08: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 801db0c: f000 b818 b.w 801db40 <_kill_r> 801db10: 2b01 cmp r3, #1 801db12: d00a beq.n 801db2a <_raise_r+0x4c> 801db14: 1c59 adds r1, r3, #1 801db16: d103 bne.n 801db20 <_raise_r+0x42> 801db18: 2316 movs r3, #22 801db1a: 6003 str r3, [r0, #0] 801db1c: 2001 movs r0, #1 801db1e: e7e7 b.n 801daf0 <_raise_r+0x12> 801db20: 2100 movs r1, #0 801db22: f842 1024 str.w r1, [r2, r4, lsl #2] 801db26: 4620 mov r0, r4 801db28: 4798 blx r3 801db2a: 2000 movs r0, #0 801db2c: e7e0 b.n 801daf0 <_raise_r+0x12> ... 0801db30 : 801db30: 4b02 ldr r3, [pc, #8] @ (801db3c ) 801db32: 4601 mov r1, r0 801db34: 6818 ldr r0, [r3, #0] 801db36: f7ff bfd2 b.w 801dade <_raise_r> 801db3a: bf00 nop 801db3c: 2000011c .word 0x2000011c 0801db40 <_kill_r>: 801db40: b538 push {r3, r4, r5, lr} 801db42: 4d07 ldr r5, [pc, #28] @ (801db60 <_kill_r+0x20>) 801db44: 2300 movs r3, #0 801db46: 4604 mov r4, r0 801db48: 4608 mov r0, r1 801db4a: 4611 mov r1, r2 801db4c: 602b str r3, [r5, #0] 801db4e: f7e8 fd9d bl 800668c <_kill> 801db52: 1c43 adds r3, r0, #1 801db54: d102 bne.n 801db5c <_kill_r+0x1c> 801db56: 682b ldr r3, [r5, #0] 801db58: b103 cbz r3, 801db5c <_kill_r+0x1c> 801db5a: 6023 str r3, [r4, #0] 801db5c: bd38 pop {r3, r4, r5, pc} 801db5e: bf00 nop 801db60: 20013cd8 .word 0x20013cd8 0801db64 <_getpid_r>: 801db64: f7e8 bd8a b.w 800667c <_getpid> 0801db68 : 801db68: b538 push {r3, r4, r5, lr} 801db6a: ed2d 8b02 vpush {d8} 801db6e: ec55 4b10 vmov r4, r5, d0 801db72: f000 f82d bl 801dbd0 <__ieee754_sqrt> 801db76: 4622 mov r2, r4 801db78: 462b mov r3, r5 801db7a: 4620 mov r0, r4 801db7c: 4629 mov r1, r5 801db7e: eeb0 8a40 vmov.f32 s16, s0 801db82: eef0 8a60 vmov.f32 s17, s1 801db86: f7e2 ffa9 bl 8000adc <__aeabi_dcmpun> 801db8a: b930 cbnz r0, 801db9a 801db8c: 2200 movs r2, #0 801db8e: 2300 movs r3, #0 801db90: 4620 mov r0, r4 801db92: 4629 mov r1, r5 801db94: f7e2 ff7a bl 8000a8c <__aeabi_dcmplt> 801db98: b930 cbnz r0, 801dba8 801db9a: eeb0 0a48 vmov.f32 s0, s16 801db9e: eef0 0a68 vmov.f32 s1, s17 801dba2: ecbd 8b02 vpop {d8} 801dba6: bd38 pop {r3, r4, r5, pc} 801dba8: f7fc fc4c bl 801a444 <__errno> 801dbac: 2200 movs r2, #0 801dbae: 2300 movs r3, #0 801dbb0: 2121 movs r1, #33 @ 0x21 801dbb2: 6001 str r1, [r0, #0] 801dbb4: 4610 mov r0, r2 801dbb6: 4619 mov r1, r3 801dbb8: f7e2 fe20 bl 80007fc <__aeabi_ddiv> 801dbbc: ec41 0b18 vmov d8, r0, r1 801dbc0: eeb0 0a48 vmov.f32 s0, s16 801dbc4: eef0 0a68 vmov.f32 s1, s17 801dbc8: ecbd 8b02 vpop {d8} 801dbcc: bd38 pop {r3, r4, r5, pc} 801dbce: bf00 nop 0801dbd0 <__ieee754_sqrt>: 801dbd0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 801dbd4: 4977 ldr r1, [pc, #476] @ (801ddb4 <__ieee754_sqrt+0x1e4>) 801dbd6: ec55 4b10 vmov r4, r5, d0 801dbda: 43a9 bics r1, r5 801dbdc: f000 80ae beq.w 801dd3c <__ieee754_sqrt+0x16c> 801dbe0: 2d00 cmp r5, #0 801dbe2: 462a mov r2, r5 801dbe4: 4623 mov r3, r4 801dbe6: dd55 ble.n 801dc94 <__ieee754_sqrt+0xc4> 801dbe8: 152c asrs r4, r5, #20 801dbea: d062 beq.n 801dcb2 <__ieee754_sqrt+0xe2> 801dbec: f3c2 0213 ubfx r2, r2, #0, #20 801dbf0: 07e1 lsls r1, r4, #31 801dbf2: f2a4 37ff subw r7, r4, #1023 @ 0x3ff 801dbf6: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 801dbfa: d403 bmi.n 801dc04 <__ieee754_sqrt+0x34> 801dbfc: 0052 lsls r2, r2, #1 801dbfe: eb02 72d3 add.w r2, r2, r3, lsr #31 801dc02: 005b lsls r3, r3, #1 801dc04: 0052 lsls r2, r2, #1 801dc06: 2600 movs r6, #0 801dc08: eb02 72d3 add.w r2, r2, r3, lsr #31 801dc0c: 107f asrs r7, r7, #1 801dc0e: 005b lsls r3, r3, #1 801dc10: 2416 movs r4, #22 801dc12: 46b4 mov ip, r6 801dc14: f44f 1100 mov.w r1, #2097152 @ 0x200000 801dc18: eb0c 0001 add.w r0, ip, r1 801dc1c: 4290 cmp r0, r2 801dc1e: ea4f 75d3 mov.w r5, r3, lsr #31 801dc22: ea4f 0343 mov.w r3, r3, lsl #1 801dc26: dc03 bgt.n 801dc30 <__ieee754_sqrt+0x60> 801dc28: eb00 0c01 add.w ip, r0, r1 801dc2c: 1a12 subs r2, r2, r0 801dc2e: 440e add r6, r1 801dc30: 3c01 subs r4, #1 801dc32: eb05 0242 add.w r2, r5, r2, lsl #1 801dc36: ea4f 0151 mov.w r1, r1, lsr #1 801dc3a: d1ed bne.n 801dc18 <__ieee754_sqrt+0x48> 801dc3c: 46a0 mov r8, r4 801dc3e: 2520 movs r5, #32 801dc40: f04f 4000 mov.w r0, #2147483648 @ 0x80000000 801dc44: e00a b.n 801dc5c <__ieee754_sqrt+0x8c> 801dc46: d043 beq.n 801dcd0 <__ieee754_sqrt+0x100> 801dc48: 0051 lsls r1, r2, #1 801dc4a: eb01 71d3 add.w r1, r1, r3, lsr #31 801dc4e: 3d01 subs r5, #1 801dc50: 460a mov r2, r1 801dc52: ea4f 0343 mov.w r3, r3, lsl #1 801dc56: ea4f 0050 mov.w r0, r0, lsr #1 801dc5a: d045 beq.n 801dce8 <__ieee754_sqrt+0x118> 801dc5c: 4562 cmp r2, ip 801dc5e: eb00 0e08 add.w lr, r0, r8 801dc62: ddf0 ble.n 801dc46 <__ieee754_sqrt+0x76> 801dc64: f1be 0f00 cmp.w lr, #0 801dc68: eb0e 0800 add.w r8, lr, r0 801dc6c: db0c blt.n 801dc88 <__ieee754_sqrt+0xb8> 801dc6e: 46e1 mov r9, ip 801dc70: eba2 010c sub.w r1, r2, ip 801dc74: 459e cmp lr, r3 801dc76: bf88 it hi 801dc78: f101 31ff addhi.w r1, r1, #4294967295 @ 0xffffffff 801dc7c: 0049 lsls r1, r1, #1 801dc7e: 46cc mov ip, r9 801dc80: eba3 030e sub.w r3, r3, lr 801dc84: 4404 add r4, r0 801dc86: e7e0 b.n 801dc4a <__ieee754_sqrt+0x7a> 801dc88: f1b8 0f00 cmp.w r8, #0 801dc8c: dbef blt.n 801dc6e <__ieee754_sqrt+0x9e> 801dc8e: f10c 0901 add.w r9, ip, #1 801dc92: e7ed b.n 801dc70 <__ieee754_sqrt+0xa0> 801dc94: f025 4100 bic.w r1, r5, #2147483648 @ 0x80000000 801dc98: 4321 orrs r1, r4 801dc9a: d046 beq.n 801dd2a <__ieee754_sqrt+0x15a> 801dc9c: 2d00 cmp r5, #0 801dc9e: d174 bne.n 801dd8a <__ieee754_sqrt+0x1ba> 801dca0: 0ad9 lsrs r1, r3, #11 801dca2: 3a15 subs r2, #21 801dca4: 055b lsls r3, r3, #21 801dca6: 2900 cmp r1, #0 801dca8: d0fa beq.n 801dca0 <__ieee754_sqrt+0xd0> 801dcaa: 02ce lsls r6, r1, #11 801dcac: 4614 mov r4, r2 801dcae: d47d bmi.n 801ddac <__ieee754_sqrt+0x1dc> 801dcb0: 460a mov r2, r1 801dcb2: 2100 movs r1, #0 801dcb4: 0052 lsls r2, r2, #1 801dcb6: 02d5 lsls r5, r2, #11 801dcb8: 4608 mov r0, r1 801dcba: f101 0101 add.w r1, r1, #1 801dcbe: d5f9 bpl.n 801dcb4 <__ieee754_sqrt+0xe4> 801dcc0: f1c1 0520 rsb r5, r1, #32 801dcc4: fa23 f505 lsr.w r5, r3, r5 801dcc8: 432a orrs r2, r5 801dcca: 408b lsls r3, r1 801dccc: 1a24 subs r4, r4, r0 801dcce: e78d b.n 801dbec <__ieee754_sqrt+0x1c> 801dcd0: 459e cmp lr, r3 801dcd2: d902 bls.n 801dcda <__ieee754_sqrt+0x10a> 801dcd4: ea4f 014c mov.w r1, ip, lsl #1 801dcd8: e7b7 b.n 801dc4a <__ieee754_sqrt+0x7a> 801dcda: f1be 0f00 cmp.w lr, #0 801dcde: eb0e 0800 add.w r8, lr, r0 801dce2: db24 blt.n 801dd2e <__ieee754_sqrt+0x15e> 801dce4: 2100 movs r1, #0 801dce6: e7cb b.n 801dc80 <__ieee754_sqrt+0xb0> 801dce8: 4319 orrs r1, r3 801dcea: d012 beq.n 801dd12 <__ieee754_sqrt+0x142> 801dcec: f8df a0c8 ldr.w sl, [pc, #200] @ 801ddb8 <__ieee754_sqrt+0x1e8> 801dcf0: f8df b0c8 ldr.w fp, [pc, #200] @ 801ddbc <__ieee754_sqrt+0x1ec> 801dcf4: e9da 0100 ldrd r0, r1, [sl] 801dcf8: e9db 2300 ldrd r2, r3, [fp] 801dcfc: f7e2 fa9c bl 8000238 <__aeabi_dsub> 801dd00: e9da 8900 ldrd r8, r9, [sl] 801dd04: 4602 mov r2, r0 801dd06: 460b mov r3, r1 801dd08: 4640 mov r0, r8 801dd0a: 4649 mov r1, r9 801dd0c: f7e2 fec8 bl 8000aa0 <__aeabi_dcmple> 801dd10: bb10 cbnz r0, 801dd58 <__ieee754_sqrt+0x188> 801dd12: 0865 lsrs r5, r4, #1 801dd14: 1071 asrs r1, r6, #1 801dd16: f101 517f add.w r1, r1, #1069547520 @ 0x3fc00000 801dd1a: f501 1100 add.w r1, r1, #2097152 @ 0x200000 801dd1e: eb01 5307 add.w r3, r1, r7, lsl #20 801dd22: ea45 72c6 orr.w r2, r5, r6, lsl #31 801dd26: ec43 2b10 vmov d0, r2, r3 801dd2a: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 801dd2e: f1b8 0f00 cmp.w r8, #0 801dd32: dbd7 blt.n 801dce4 <__ieee754_sqrt+0x114> 801dd34: f10c 0c01 add.w ip, ip, #1 801dd38: 2100 movs r1, #0 801dd3a: e7a1 b.n 801dc80 <__ieee754_sqrt+0xb0> 801dd3c: 4622 mov r2, r4 801dd3e: 462b mov r3, r5 801dd40: 4620 mov r0, r4 801dd42: 4629 mov r1, r5 801dd44: f7e2 fc30 bl 80005a8 <__aeabi_dmul> 801dd48: 4622 mov r2, r4 801dd4a: 462b mov r3, r5 801dd4c: f7e2 fa76 bl 800023c <__adddf3> 801dd50: ec41 0b10 vmov d0, r0, r1 801dd54: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 801dd58: f1b4 3fff cmp.w r4, #4294967295 @ 0xffffffff 801dd5c: e9da 0100 ldrd r0, r1, [sl] 801dd60: e9db 2300 ldrd r2, r3, [fp] 801dd64: d01e beq.n 801dda4 <__ieee754_sqrt+0x1d4> 801dd66: f7e2 fa69 bl 800023c <__adddf3> 801dd6a: e9da 8900 ldrd r8, r9, [sl] 801dd6e: 4602 mov r2, r0 801dd70: 460b mov r3, r1 801dd72: 4640 mov r0, r8 801dd74: 4649 mov r1, r9 801dd76: f7e2 fe89 bl 8000a8c <__aeabi_dcmplt> 801dd7a: b1a8 cbz r0, 801dda8 <__ieee754_sqrt+0x1d8> 801dd7c: 1ca3 adds r3, r4, #2 801dd7e: f104 0502 add.w r5, r4, #2 801dd82: bf08 it eq 801dd84: 3601 addeq r6, #1 801dd86: 086d lsrs r5, r5, #1 801dd88: e7c4 b.n 801dd14 <__ieee754_sqrt+0x144> 801dd8a: 4622 mov r2, r4 801dd8c: 462b mov r3, r5 801dd8e: 4620 mov r0, r4 801dd90: 4629 mov r1, r5 801dd92: f7e2 fa51 bl 8000238 <__aeabi_dsub> 801dd96: 4602 mov r2, r0 801dd98: 460b mov r3, r1 801dd9a: f7e2 fd2f bl 80007fc <__aeabi_ddiv> 801dd9e: ec41 0b10 vmov d0, r0, r1 801dda2: e7c2 b.n 801dd2a <__ieee754_sqrt+0x15a> 801dda4: 3601 adds r6, #1 801dda6: e7b5 b.n 801dd14 <__ieee754_sqrt+0x144> 801dda8: 3401 adds r4, #1 801ddaa: e7b2 b.n 801dd12 <__ieee754_sqrt+0x142> 801ddac: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801ddb0: 460a mov r2, r1 801ddb2: e78b b.n 801dccc <__ieee754_sqrt+0xfc> 801ddb4: 7ff00000 .word 0x7ff00000 801ddb8: 0801ea28 .word 0x0801ea28 801ddbc: 0801ea20 .word 0x0801ea20 0801ddc0 <_init>: 801ddc0: b5f8 push {r3, r4, r5, r6, r7, lr} 801ddc2: bf00 nop 801ddc4: bcf8 pop {r3, r4, r5, r6, r7} 801ddc6: bc08 pop {r3} 801ddc8: 469e mov lr, r3 801ddca: 4770 bx lr 0801ddcc <_fini>: 801ddcc: b5f8 push {r3, r4, r5, r6, r7, lr} 801ddce: bf00 nop 801ddd0: bcf8 pop {r3, r4, r5, r6, r7} 801ddd2: bc08 pop {r3} 801ddd4: 469e mov lr, r3 801ddd6: 4770 bx lr